From chris at chris-wilson.co.uk Mon Jun 1 07:24:42 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:42 +0100 Subject: [Intel-gfx] [PATCH 32/36] drm/i915/gem: Assign context id for async work In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-32-chris@chris-wilson.co.uk> Allocate a few dma fence context id that we can use to associate async work [for the CPU] launched on behalf of this context. For extra fun, we allow a configurable concurrency width. A current example would be that we spawn an unbound worker for every userptr get_pages. In the future, we wish to charge this work to the context that initiated the async work and to impose concurrency limits based on the context. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++++ drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 ++++++ drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 6 ++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index f5d59d18cd5b..4e8cebe2e66b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -715,6 +715,10 @@ __create_context(struct drm_i915_private *i915) ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL); mutex_init(&ctx->mutex); + ctx->async.width = rounddown_pow_of_two(num_online_cpus()); + ctx->async.context = dma_fence_context_alloc(ctx->async.width); + ctx->async.width--; + spin_lock_init(&ctx->stale.lock); INIT_LIST_HEAD(&ctx->stale.engines); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h index 3702b2fb27ab..e104ff0ae740 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h @@ -134,6 +134,12 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +static inline u64 i915_gem_context_async_id(struct i915_gem_context *ctx) +{ + return (ctx->async.context + + (atomic_fetch_inc(&ctx->async.cur) & ctx->async.width)); +} + static inline struct i915_gem_context * i915_gem_context_get(struct i915_gem_context *ctx) { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h index 28760bd03265..5f5cfa3a3e9b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h @@ -85,6 +85,12 @@ struct i915_gem_context { struct intel_timeline *timeline; + struct { + u64 context; + atomic_t cur; + unsigned int width; + } async; + /** * @vm: unique address space (GTT) * -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:37 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:37 +0100 Subject: [Intel-gfx] [PATCH 27/36] drm/i915/gem: Teach execbuf how to wait on future syncobj In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-27-chris@chris-wilson.co.uk> If a syncobj has not yet been assigned, treat it as a future fence and install and wait upon a dma-fence-proxy. The proxy will be replace by the real fence later, and that fence will be responsible for signaling our waiter. Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854 Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 2844274c37bb..4fddbe34efa6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2490,8 +2490,24 @@ await_fence_array(struct i915_execbuffer *eb, continue; fence = drm_syncobj_fence_get(syncobj); - if (!fence) - return -EINVAL; + if (!fence) { + struct dma_fence *old; + + fence = dma_fence_create_proxy(); + if (!fence) + return -ENOMEM; + + spin_lock(&syncobj->lock); + old = rcu_dereference_protected(syncobj->fence, true); + if (unlikely(old)) { + dma_fence_put(fence); + fence = dma_fence_get(old); + } else { + rcu_assign_pointer(syncobj->fence, + dma_fence_get(fence)); + } + spin_unlock(&syncobj->lock); + } err = i915_request_await_dma_fence(eb->request, fence); dma_fence_put(fence); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:40 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:40 +0100 Subject: [Intel-gfx] [PATCH 30/36] drm/i915: Drop I915_IDLE_ENGINES_TIMEOUT In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-30-chris@chris-wilson.co.uk> This timeout is only used in one place, to provide a tiny bit of grace for slow igt to cleanup after themselves. If we are a bit stricter and opt to kill outstanding requsts rather than wait, we can speed up igt by not waiting for 200ms after a hang. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 11 ++++++----- drivers/gpu/drm/i915/i915_drv.h | 2 -- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bca036ac6621..c0bd26ef4772 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1462,12 +1462,13 @@ gt_drop_caches(struct intel_gt *gt, u64 val) { int ret; - if (val & DROP_RESET_ACTIVE && - wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) - intel_gt_set_wedged(gt); + if (val & (DROP_RETIRE | DROP_RESET_ACTIVE)) + intel_gt_wait_for_idle(gt, 1); - if (val & DROP_RETIRE) - intel_gt_retire_requests(gt); + if (val & DROP_RESET_ACTIVE && intel_gt_pm_get_if_awake(gt)) { + intel_gt_set_wedged(gt); + intel_gt_pm_put(gt); + } if (val & (DROP_IDLE | DROP_ACTIVE)) { ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 98f2c448cd92..5140b90f7f7d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -616,8 +616,6 @@ struct i915_gem_mm { u32 shrink_count; }; -#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ - unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, u64 context); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:16 +0100 Subject: [Intel-gfx] [PATCH 06/36] drm/i915/gt: Couple tasklet scheduling for all CS interrupts In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-6-chris@chris-wilson.co.uk> If any engine asks for the tasklet to be kicked from the CS interrupt, do so. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 ++++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +++ drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- 4 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 0cc7dd54f4f9..28edf314a319 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -60,6 +60,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir) tasklet_hi_schedule(&engine->execlists.tasklet); } +void gen2_engine_cs_irq(struct intel_engine_cs *engine) +{ + intel_engine_signal_breadcrumbs(engine); + if (intel_engine_needs_breadcrumb_tasklet(engine)) + tasklet_hi_schedule(&engine->execlists.tasklet); +} + static u32 gen11_gt_engine_identity(struct intel_gt *gt, const unsigned int bank, const unsigned int bit) @@ -273,9 +280,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); if (gt_iir & ILK_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); } static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) @@ -299,11 +306,11 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); if (gt_iir & GT_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); if (gt_iir & GT_BLT_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0]); if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | GT_BSD_CS_ERROR_INTERRUPT | diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h index 886c5cf408a2..6c69cd563fe1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h @@ -9,6 +9,7 @@ #include +struct intel_engine_cs; struct intel_gt; #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ @@ -19,6 +20,8 @@ struct intel_gt; GEN8_GT_PM_IRQ | \ GEN8_GT_GUC_IRQ) +void gen2_engine_cs_irq(struct intel_engine_cs *engine); + void gen11_gt_irq_reset(struct intel_gt *gt); void gen11_gt_irq_postinstall(struct intel_gt *gt); void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2f59fc6df3c2..2e4ddc9ca09d 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1741,7 +1741,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) return; if (pm_iir & PM_VEBOX_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine[VECS0]); + gen2_engine_cs_irq(gt->engine[VECS0]); if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 07c0c7ea3795..096123777533 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3678,7 +3678,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i8xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -3783,7 +3783,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) I915_WRITE(GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -3925,10 +3925,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) I915_WRITE(GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[VCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:12 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:12 +0100 Subject: [Intel-gfx] [PATCH 02/36] drm/i915/gt: Split low level gen2-7 CS emitters In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-2-chris@chris-wilson.co.uk> Pull the routines for writing CS packets out of intel_ring_submission into their own files. These are low level operations for building CS instructions, rather than the logic for filling the global ring buffer with requests, and we will wnat to reuse them outside of this context. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/Makefile | 2 + drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 340 +++++++ drivers/gpu/drm/i915/gt/gen2_engine_cs.h | 38 + drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 455 ++++++++++ drivers/gpu/drm/i915/gt/gen6_engine_cs.h | 39 + drivers/gpu/drm/i915/gt/intel_engine.h | 1 - .../gpu/drm/i915/gt/intel_ring_submission.c | 832 +----------------- 7 files changed, 901 insertions(+), 806 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/gen2_engine_cs.c create mode 100644 drivers/gpu/drm/i915/gt/gen2_engine_cs.h create mode 100644 drivers/gpu/drm/i915/gt/gen6_engine_cs.c create mode 100644 drivers/gpu/drm/i915/gt/gen6_engine_cs.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index b0da6ea6e3f1..41a27fd5dbc7 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -78,6 +78,8 @@ gt-y += \ gt/debugfs_engines.o \ gt/debugfs_gt.o \ gt/debugfs_gt_pm.o \ + gt/gen2_engine_cs.o \ + gt/gen6_engine_cs.o \ gt/gen6_ppgtt.o \ gt/gen7_renderclear.o \ gt/gen8_ppgtt.o \ diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c new file mode 100644 index 000000000000..8d2e85081247 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +#include "gen2_engine_cs.h" +#include "i915_drv.h" +#include "intel_engine.h" +#include "intel_gpu_commands.h" +#include "intel_gt.h" +#include "intel_gt_irq.h" +#include "intel_ring.h" + +int gen2_emit_flush(struct i915_request *rq, u32 mode) +{ + unsigned int num_store_dw; + u32 cmd, *cs; + + cmd = MI_FLUSH; + num_store_dw = 0; + if (mode & EMIT_INVALIDATE) + cmd |= MI_READ_FLUSH; + if (mode & EMIT_FLUSH) + num_store_dw = 4; + + cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = cmd; + while (num_store_dw--) { + *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; + *cs++ = intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + *cs++ = 0; + } + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; + + intel_ring_advance(rq, cs); + + return 0; +} + +int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode) +{ + u32 cmd, *cs; + int i; + + /* + * read/write caches: + * + * I915_GEM_DOMAIN_RENDER is always invalidated, but is + * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is + * also flushed at 2d versus 3d pipeline switches. + * + * read-only caches: + * + * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if + * MI_READ_FLUSH is set, and is always flushed on 965. + * + * I915_GEM_DOMAIN_COMMAND may not exist? + * + * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is + * invalidated when MI_EXE_FLUSH is set. + * + * I915_GEM_DOMAIN_VERTEX, which exists on 965, is + * invalidated with every MI_FLUSH. + * + * TLBs: + * + * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND + * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and + * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER + * are flushed at any MI_FLUSH. + */ + + cmd = MI_FLUSH; + if (mode & EMIT_INVALIDATE) { + cmd |= MI_EXE_FLUSH; + if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) + cmd |= MI_INVALIDATE_ISP; + } + + i = 2; + if (mode & EMIT_INVALIDATE) + i += 20; + + cs = intel_ring_begin(rq, i); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = cmd; + + /* + * A random delay to let the CS invalidate take effect? Without this + * delay, the GPU relocation path fails as the CS does not see + * the updated contents. Just as important, if we apply the flushes + * to the EMIT_FLUSH branch (i.e. immediately after the relocation + * write and before the invalidate on the next batch), the relocations + * still fail. This implies that is a delay following invalidation + * that is required to reset the caches as opposed to a delay to + * ensure the memory is written. + */ + if (mode & EMIT_INVALIDATE) { + *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; + *cs++ = intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT) | + PIPE_CONTROL_GLOBAL_GTT; + *cs++ = 0; + *cs++ = 0; + + for (i = 0; i < 12; i++) + *cs++ = MI_FLUSH; + + *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; + *cs++ = intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT) | + PIPE_CONTROL_GLOBAL_GTT; + *cs++ = 0; + *cs++ = 0; + } + + *cs++ = cmd; + + intel_ring_advance(rq, cs); + + return 0; +} + +int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) +{ + u32 *cs; + + cs = intel_ring_begin(rq, 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_FLUSH; + *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); + + return 0; +} + +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) +{ + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); + + *cs++ = MI_FLUSH; + + *cs++ = MI_STORE_DWORD_INDEX; + *cs++ = I915_GEM_HWS_SEQNO_ADDR; + *cs++ = rq->fence.seqno; + + *cs++ = MI_USER_INTERRUPT; + *cs++ = MI_NOOP; + + rq->tail = intel_ring_offset(rq, cs); + assert_ring_tail_valid(rq->ring, rq->tail); + + return cs; +} + +#define GEN5_WA_STORES 8 /* must be at least 1! */ +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) +{ + int i; + + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); + + *cs++ = MI_FLUSH; + + BUILD_BUG_ON(GEN5_WA_STORES < 1); + for (i = 0; i < GEN5_WA_STORES; i++) { + *cs++ = MI_STORE_DWORD_INDEX; + *cs++ = I915_GEM_HWS_SEQNO_ADDR; + *cs++ = rq->fence.seqno; + } + + *cs++ = MI_USER_INTERRUPT; + + rq->tail = intel_ring_offset(rq, cs); + assert_ring_tail_valid(rq->ring, rq->tail); + + return cs; +} +#undef GEN5_WA_STORES + +/* Just userspace ABI convention to limit the wa batch bo to a resonable size */ +#define I830_BATCH_LIMIT SZ_256K +#define I830_TLB_ENTRIES (2) +#define I830_WA_SIZE max(I830_TLB_ENTRIES * SZ_4K, I830_BATCH_LIMIT) +int i830_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags) +{ + u32 *cs, cs_offset = + intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + + GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE); + + cs = intel_ring_begin(rq, 6); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + /* Evict the invalid PTE TLBs */ + *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; + *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; + *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ + *cs++ = cs_offset; + *cs++ = 0xdeadbeef; + *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); + + if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { + if (len > I830_BATCH_LIMIT) + return -ENOSPC; + + cs = intel_ring_begin(rq, 6 + 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + /* + * Blit the batch (which has now all relocs applied) to the + * stable batch scratch bo area (so that the CS never + * stumbles over its tlb invalidation bug) ... + */ + *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2); + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; + *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; + *cs++ = cs_offset; + *cs++ = 4096; + *cs++ = offset; + + *cs++ = MI_FLUSH; + *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); + + /* ... and execute it. */ + offset = cs_offset; + } + + if (!(dispatch_flags & I915_DISPATCH_SECURE)) + offset |= MI_BATCH_NON_SECURE; + + cs = intel_ring_begin(rq, 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; + *cs++ = offset; + intel_ring_advance(rq, cs); + + return 0; +} + +int gen3_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags) +{ + u32 *cs; + + if (!(dispatch_flags & I915_DISPATCH_SECURE)) + offset |= MI_BATCH_NON_SECURE; + + cs = intel_ring_begin(rq, 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; + *cs++ = offset; + intel_ring_advance(rq, cs); + + return 0; +} + +int gen4_emit_bb_start(struct i915_request *rq, + u64 offset, u32 length, + unsigned int dispatch_flags) +{ + u32 security; + u32 *cs; + + security = MI_BATCH_NON_SECURE_I965; + if (dispatch_flags & I915_DISPATCH_SECURE) + security = 0; + + cs = intel_ring_begin(rq, 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security; + *cs++ = offset; + intel_ring_advance(rq, cs); + + return 0; +} + +void gen2_irq_enable(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; + + i915->irq_mask &= ~engine->irq_enable_mask; + intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); + ENGINE_POSTING_READ16(engine, RING_IMR); +} + +void gen2_irq_disable(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; + + i915->irq_mask |= engine->irq_enable_mask; + intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); +} + +void gen3_irq_enable(struct intel_engine_cs *engine) +{ + engine->i915->irq_mask &= ~engine->irq_enable_mask; + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); + intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); +} + +void gen3_irq_disable(struct intel_engine_cs *engine) +{ + engine->i915->irq_mask |= engine->irq_enable_mask; + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); +} + +void gen5_irq_enable(struct intel_engine_cs *engine) +{ + gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); +} + +void gen5_irq_disable(struct intel_engine_cs *engine) +{ + gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); +} diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h new file mode 100644 index 000000000000..a5cd64a65c9e --- /dev/null +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __GEN2_ENGINE_CS_H__ +#define __GEN2_ENGINE_CS_H__ + +#include + +struct i915_request; +struct intel_engine_cs; + +int gen2_emit_flush(struct i915_request *rq, u32 mode); +int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode); +int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode); + +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs); +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs); + +int i830_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags); +int gen3_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags); +int gen4_emit_bb_start(struct i915_request *rq, + u64 offset, u32 length, + unsigned int dispatch_flags); + +void gen2_irq_enable(struct intel_engine_cs *engine); +void gen2_irq_disable(struct intel_engine_cs *engine); +void gen3_irq_enable(struct intel_engine_cs *engine); +void gen3_irq_disable(struct intel_engine_cs *engine); +void gen5_irq_enable(struct intel_engine_cs *engine); +void gen5_irq_disable(struct intel_engine_cs *engine); + +#endif /* __GEN2_ENGINE_CS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c new file mode 100644 index 000000000000..ce38d1bcaba3 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +#include "gen6_engine_cs.h" +#include "intel_engine.h" +#include "intel_gpu_commands.h" +#include "intel_gt.h" +#include "intel_gt_irq.h" +#include "intel_gt_pm_irq.h" +#include "intel_ring.h" + +#define HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) + +/* + * Emits a PIPE_CONTROL with a non-zero post-sync operation, for + * implementing two workarounds on gen6. From section 1.4.7.1 + * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: + * + * [DevSNB-C+{W/A}] Before any depth stall flush (including those + * produced by non-pipelined state commands), software needs to first + * send a PIPE_CONTROL with no bits set except Post-Sync Operation != + * 0. + * + * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable + * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. + * + * And the workaround for these two requires this workaround first: + * + * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent + * BEFORE the pipe-control with a post-sync op and no write-cache + * flushes. + * + * And this last workaround is tricky because of the requirements on + * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM + * volume 2 part 1: + * + * "1 of the following must also be set: + * - Render Target Cache Flush Enable ([12] of DW1) + * - Depth Cache Flush Enable ([0] of DW1) + * - Stall at Pixel Scoreboard ([1] of DW1) + * - Depth Stall ([13] of DW1) + * - Post-Sync Operation ([13] of DW1) + * - Notify Enable ([8] of DW1)" + * + * The cache flushes require the workaround flush that triggered this + * one, so we can't use it. Depth stall would trigger the same. + * Post-sync nonzero is what triggered this second workaround, so we + * can't use that one either. Notify enable is IRQs, which aren't + * really our business. That leaves only stall at scoreboard. + */ +static int +gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) +{ + u32 scratch_addr = + intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); + u32 *cs; + + cs = intel_ring_begin(rq, 6); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = GFX_OP_PIPE_CONTROL(5); + *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; + *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; + *cs++ = 0; /* low dword */ + *cs++ = 0; /* high dword */ + *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); + + cs = intel_ring_begin(rq, 6); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = GFX_OP_PIPE_CONTROL(5); + *cs++ = PIPE_CONTROL_QW_WRITE; + *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; + *cs++ = 0; + *cs++ = 0; + *cs++ = MI_NOOP; + intel_ring_advance(rq, cs); + + return 0; +} + +int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode) +{ + u32 scratch_addr = + intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); + u32 *cs, flags = 0; + int ret; + + /* Force SNB workarounds for PIPE_CONTROL flushes */ + ret = gen6_emit_post_sync_nonzero_flush(rq); + if (ret) + return ret; + + /* + * Just flush everything. Experiments have shown that reducing the + * number of bits based on the write domains has little performance + * impact. And when rearranging requests, the order of flushes is + * unknown. + */ + if (mode & EMIT_FLUSH) { + flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; + flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; + /* + * Ensure that any following seqno writes only happen + * when the render cache is indeed flushed. + */ + flags |= PIPE_CONTROL_CS_STALL; + } + if (mode & EMIT_INVALIDATE) { + flags |= PIPE_CONTROL_TLB_INVALIDATE; + flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + /* + * TLB invalidate requires a post-sync write. + */ + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; + } + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = flags; + *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; + *cs++ = 0; + intel_ring_advance(rq, cs); + + return 0; +} + +u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) +{ + /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; + *cs++ = 0; + *cs++ = 0; + + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = PIPE_CONTROL_QW_WRITE; + *cs++ = intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT) | + PIPE_CONTROL_GLOBAL_GTT; + *cs++ = 0; + + /* Finally we can flush and with it emit the breadcrumb */ + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | + PIPE_CONTROL_DEPTH_CACHE_FLUSH | + PIPE_CONTROL_DC_FLUSH_ENABLE | + PIPE_CONTROL_QW_WRITE | + PIPE_CONTROL_CS_STALL); + *cs++ = i915_request_active_timeline(rq)->hwsp_offset | + PIPE_CONTROL_GLOBAL_GTT; + *cs++ = rq->fence.seqno; + + *cs++ = MI_USER_INTERRUPT; + *cs++ = MI_NOOP; + + rq->tail = intel_ring_offset(rq, cs); + assert_ring_tail_valid(rq->ring, rq->tail); + + return cs; +} + +static int mi_flush_dw(struct i915_request *rq, u32 flags) +{ + u32 cmd, *cs; + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + cmd = MI_FLUSH_DW; + + /* + * We always require a command barrier so that subsequent + * commands, such as breadcrumb interrupts, are strictly ordered + * wrt the contents of the write cache being flushed to memory + * (and thus being coherent from the CPU). + */ + cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; + + /* + * Bspec vol 1c.3 - blitter engine command streamer: + * "If ENABLED, all TLBs will be invalidated once the flush + * operation is complete. This bit is only valid when the + * Post-Sync Operation field is a value of 1h or 3h." + */ + cmd |= flags; + + *cs++ = cmd; + *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = 0; + *cs++ = MI_NOOP; + + intel_ring_advance(rq, cs); + + return 0; +} + +static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) +{ + return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); +} + +int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode) +{ + return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); +} + +int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode) +{ + return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); +} + +int gen6_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags) +{ + u32 security; + u32 *cs; + + security = MI_BATCH_NON_SECURE_I965; + if (dispatch_flags & I915_DISPATCH_SECURE) + security = 0; + + cs = intel_ring_begin(rq, 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + cs = __gen6_emit_bb_start(cs, offset, security); + intel_ring_advance(rq, cs); + + return 0; +} + +int +hsw_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags) +{ + u32 security; + u32 *cs; + + security = MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW; + if (dispatch_flags & I915_DISPATCH_SECURE) + security = 0; + + cs = intel_ring_begin(rq, 2); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + cs = __gen6_emit_bb_start(cs, offset, security); + intel_ring_advance(rq, cs); + + return 0; +} + +static int gen7_stall_cs(struct i915_request *rq) +{ + u32 *cs; + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; + *cs++ = 0; + *cs++ = 0; + intel_ring_advance(rq, cs); + + return 0; +} + +int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode) +{ + u32 scratch_addr = + intel_gt_scratch_offset(rq->engine->gt, + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); + u32 *cs, flags = 0; + + /* + * Ensure that any following seqno writes only happen when the render + * cache is indeed flushed. + * + * Workaround: 4th PIPE_CONTROL command (except the ones with only + * read-cache invalidate bits set) must have the CS_STALL bit set. We + * don't try to be clever and just set it unconditionally. + */ + flags |= PIPE_CONTROL_CS_STALL; + + /* + * CS_STALL suggests at least a post-sync write. + */ + flags |= PIPE_CONTROL_QW_WRITE; + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + + /* + * Just flush everything. Experiments have shown that reducing the + * number of bits based on the write domains has little performance + * impact. + */ + if (mode & EMIT_FLUSH) { + flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; + flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; + flags |= PIPE_CONTROL_FLUSH_ENABLE; + } + if (mode & EMIT_INVALIDATE) { + flags |= PIPE_CONTROL_TLB_INVALIDATE; + flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; + + /* + * Workaround: we must issue a pipe_control with CS-stall bit + * set before a pipe_control command that has the state cache + * invalidate bit set. + */ + gen7_stall_cs(rq); + } + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = flags; + *cs++ = scratch_addr; + *cs++ = 0; + intel_ring_advance(rq, cs); + + return 0; +} + +u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) +{ + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | + PIPE_CONTROL_DEPTH_CACHE_FLUSH | + PIPE_CONTROL_DC_FLUSH_ENABLE | + PIPE_CONTROL_FLUSH_ENABLE | + PIPE_CONTROL_QW_WRITE | + PIPE_CONTROL_GLOBAL_GTT_IVB | + PIPE_CONTROL_CS_STALL); + *cs++ = i915_request_active_timeline(rq)->hwsp_offset; + *cs++ = rq->fence.seqno; + + *cs++ = MI_USER_INTERRUPT; + *cs++ = MI_NOOP; + + rq->tail = intel_ring_offset(rq, cs); + assert_ring_tail_valid(rq->ring, rq->tail); + + return cs; +} + +u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) +{ + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); + + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; + *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = rq->fence.seqno; + + *cs++ = MI_USER_INTERRUPT; + + rq->tail = intel_ring_offset(rq, cs); + assert_ring_tail_valid(rq->ring, rq->tail); + + return cs; +} + +#define GEN7_XCS_WA 32 +u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) +{ + int i; + + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); + + *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | + MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; + *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = rq->fence.seqno; + + for (i = 0; i < GEN7_XCS_WA; i++) { + *cs++ = MI_STORE_DWORD_INDEX; + *cs++ = I915_GEM_HWS_SEQNO_ADDR; + *cs++ = rq->fence.seqno; + } + + *cs++ = MI_FLUSH_DW; + *cs++ = 0; + *cs++ = 0; + + *cs++ = MI_USER_INTERRUPT; + *cs++ = MI_NOOP; + + rq->tail = intel_ring_offset(rq, cs); + assert_ring_tail_valid(rq->ring, rq->tail); + + return cs; +} +#undef GEN7_XCS_WA + +void gen6_irq_enable(struct intel_engine_cs *engine) +{ + ENGINE_WRITE(engine, RING_IMR, + ~(engine->irq_enable_mask | engine->irq_keep_mask)); + + /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ + ENGINE_POSTING_READ(engine, RING_IMR); + + gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); +} + +void gen6_irq_disable(struct intel_engine_cs *engine) +{ + ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); + gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); +} + +void hsw_irq_enable_vecs(struct intel_engine_cs *engine) +{ + ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); + + /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ + ENGINE_POSTING_READ(engine, RING_IMR); + + gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); +} + +void hsw_irq_disable_vecs(struct intel_engine_cs *engine) +{ + ENGINE_WRITE(engine, RING_IMR, ~0); + gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); +} diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.h b/drivers/gpu/drm/i915/gt/gen6_engine_cs.h new file mode 100644 index 000000000000..76c6bc9f3bde --- /dev/null +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __GEN6_ENGINE_CS_H__ +#define __GEN6_ENGINE_CS_H__ + +#include + +#include "intel_gpu_commands.h" + +struct i915_request; +struct intel_engine_cs; + +int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode); +int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode); +int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode); +u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); +u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); + +int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode); +u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); +u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); + +int gen6_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags); +int hsw_emit_bb_start(struct i915_request *rq, + u64 offset, u32 len, + unsigned int dispatch_flags); + +void gen6_irq_enable(struct intel_engine_cs *engine); +void gen6_irq_disable(struct intel_engine_cs *engine); + +void hsw_irq_enable_vecs(struct intel_engine_cs *engine); +void hsw_irq_disable_vecs(struct intel_engine_cs *engine); + +#endif /* __GEN6_ENGINE_CS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 9bf6d4989968..791897f8d847 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -187,7 +187,6 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) #define I915_GEM_HWS_SEQNO 0x40 #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32)) #define I915_GEM_HWS_SCRATCH 0x80 -#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) #define I915_HWS_CSB_BUF0_INDEX 0x10 #define I915_HWS_CSB_WRITE_INDEX 0x1f diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index ca7286e58409..96881cd8b17b 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -27,21 +27,15 @@ * */ -#include - -#include "gem/i915_gem_context.h" - +#include "gen2_engine_cs.h" +#include "gen6_engine_cs.h" #include "gen6_ppgtt.h" #include "gen7_renderclear.h" #include "i915_drv.h" -#include "i915_trace.h" #include "intel_context.h" #include "intel_gt.h" -#include "intel_gt_irq.h" -#include "intel_gt_pm_irq.h" #include "intel_reset.h" #include "intel_ring.h" -#include "intel_workarounds.h" #include "shmem_utils.h" /* Rough estimate of the typical request size, performing a flush, @@ -49,436 +43,6 @@ */ #define LEGACY_REQUEST_SIZE 200 -static int -gen2_render_ring_flush(struct i915_request *rq, u32 mode) -{ - unsigned int num_store_dw; - u32 cmd, *cs; - - cmd = MI_FLUSH; - num_store_dw = 0; - if (mode & EMIT_INVALIDATE) - cmd |= MI_READ_FLUSH; - if (mode & EMIT_FLUSH) - num_store_dw = 4; - - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = cmd; - while (num_store_dw--) { - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; - *cs++ = intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_DEFAULT); - *cs++ = 0; - } - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; - - intel_ring_advance(rq, cs); - - return 0; -} - -static int -gen4_render_ring_flush(struct i915_request *rq, u32 mode) -{ - u32 cmd, *cs; - int i; - - /* - * read/write caches: - * - * I915_GEM_DOMAIN_RENDER is always invalidated, but is - * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is - * also flushed at 2d versus 3d pipeline switches. - * - * read-only caches: - * - * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if - * MI_READ_FLUSH is set, and is always flushed on 965. - * - * I915_GEM_DOMAIN_COMMAND may not exist? - * - * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is - * invalidated when MI_EXE_FLUSH is set. - * - * I915_GEM_DOMAIN_VERTEX, which exists on 965, is - * invalidated with every MI_FLUSH. - * - * TLBs: - * - * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND - * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and - * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER - * are flushed at any MI_FLUSH. - */ - - cmd = MI_FLUSH; - if (mode & EMIT_INVALIDATE) { - cmd |= MI_EXE_FLUSH; - if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) - cmd |= MI_INVALIDATE_ISP; - } - - i = 2; - if (mode & EMIT_INVALIDATE) - i += 20; - - cs = intel_ring_begin(rq, i); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = cmd; - - /* - * A random delay to let the CS invalidate take effect? Without this - * delay, the GPU relocation path fails as the CS does not see - * the updated contents. Just as important, if we apply the flushes - * to the EMIT_FLUSH branch (i.e. immediately after the relocation - * write and before the invalidate on the next batch), the relocations - * still fail. This implies that is a delay following invalidation - * that is required to reset the caches as opposed to a delay to - * ensure the memory is written. - */ - if (mode & EMIT_INVALIDATE) { - *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; - *cs++ = intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_DEFAULT) | - PIPE_CONTROL_GLOBAL_GTT; - *cs++ = 0; - *cs++ = 0; - - for (i = 0; i < 12; i++) - *cs++ = MI_FLUSH; - - *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; - *cs++ = intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_DEFAULT) | - PIPE_CONTROL_GLOBAL_GTT; - *cs++ = 0; - *cs++ = 0; - } - - *cs++ = cmd; - - intel_ring_advance(rq, cs); - - return 0; -} - -/* - * Emits a PIPE_CONTROL with a non-zero post-sync operation, for - * implementing two workarounds on gen6. From section 1.4.7.1 - * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: - * - * [DevSNB-C+{W/A}] Before any depth stall flush (including those - * produced by non-pipelined state commands), software needs to first - * send a PIPE_CONTROL with no bits set except Post-Sync Operation != - * 0. - * - * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable - * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. - * - * And the workaround for these two requires this workaround first: - * - * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent - * BEFORE the pipe-control with a post-sync op and no write-cache - * flushes. - * - * And this last workaround is tricky because of the requirements on - * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM - * volume 2 part 1: - * - * "1 of the following must also be set: - * - Render Target Cache Flush Enable ([12] of DW1) - * - Depth Cache Flush Enable ([0] of DW1) - * - Stall at Pixel Scoreboard ([1] of DW1) - * - Depth Stall ([13] of DW1) - * - Post-Sync Operation ([13] of DW1) - * - Notify Enable ([8] of DW1)" - * - * The cache flushes require the workaround flush that triggered this - * one, so we can't use it. Depth stall would trigger the same. - * Post-sync nonzero is what triggered this second workaround, so we - * can't use that one either. Notify enable is IRQs, which aren't - * really our business. That leaves only stall at scoreboard. - */ -static int -gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) -{ - u32 scratch_addr = - intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); - u32 *cs; - - cs = intel_ring_begin(rq, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = GFX_OP_PIPE_CONTROL(5); - *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; - *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; - *cs++ = 0; /* low dword */ - *cs++ = 0; /* high dword */ - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - - cs = intel_ring_begin(rq, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = GFX_OP_PIPE_CONTROL(5); - *cs++ = PIPE_CONTROL_QW_WRITE; - *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; - *cs++ = 0; - *cs++ = 0; - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - - return 0; -} - -static int -gen6_render_ring_flush(struct i915_request *rq, u32 mode) -{ - u32 scratch_addr = - intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); - u32 *cs, flags = 0; - int ret; - - /* Force SNB workarounds for PIPE_CONTROL flushes */ - ret = gen6_emit_post_sync_nonzero_flush(rq); - if (ret) - return ret; - - /* Just flush everything. Experiments have shown that reducing the - * number of bits based on the write domains has little performance - * impact. - */ - if (mode & EMIT_FLUSH) { - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; - /* - * Ensure that any following seqno writes only happen - * when the render cache is indeed flushed. - */ - flags |= PIPE_CONTROL_CS_STALL; - } - if (mode & EMIT_INVALIDATE) { - flags |= PIPE_CONTROL_TLB_INVALIDATE; - flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; - /* - * TLB invalidate requires a post-sync write. - */ - flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; - } - - cs = intel_ring_begin(rq, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = GFX_OP_PIPE_CONTROL(4); - *cs++ = flags; - *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; - *cs++ = 0; - intel_ring_advance(rq, cs); - - return 0; -} - -static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) -{ - /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ - *cs++ = GFX_OP_PIPE_CONTROL(4); - *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; - *cs++ = 0; - *cs++ = 0; - - *cs++ = GFX_OP_PIPE_CONTROL(4); - *cs++ = PIPE_CONTROL_QW_WRITE; - *cs++ = intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_DEFAULT) | - PIPE_CONTROL_GLOBAL_GTT; - *cs++ = 0; - - /* Finally we can flush and with it emit the breadcrumb */ - *cs++ = GFX_OP_PIPE_CONTROL(4); - *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | - PIPE_CONTROL_DEPTH_CACHE_FLUSH | - PIPE_CONTROL_DC_FLUSH_ENABLE | - PIPE_CONTROL_QW_WRITE | - PIPE_CONTROL_CS_STALL); - *cs++ = i915_request_active_timeline(rq)->hwsp_offset | - PIPE_CONTROL_GLOBAL_GTT; - *cs++ = rq->fence.seqno; - - *cs++ = MI_USER_INTERRUPT; - *cs++ = MI_NOOP; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); - - return cs; -} - -static int -gen7_render_ring_cs_stall_wa(struct i915_request *rq) -{ - u32 *cs; - - cs = intel_ring_begin(rq, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = GFX_OP_PIPE_CONTROL(4); - *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; - *cs++ = 0; - *cs++ = 0; - intel_ring_advance(rq, cs); - - return 0; -} - -static int -gen7_render_ring_flush(struct i915_request *rq, u32 mode) -{ - u32 scratch_addr = - intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); - u32 *cs, flags = 0; - - /* - * Ensure that any following seqno writes only happen when the render - * cache is indeed flushed. - * - * Workaround: 4th PIPE_CONTROL command (except the ones with only - * read-cache invalidate bits set) must have the CS_STALL bit set. We - * don't try to be clever and just set it unconditionally. - */ - flags |= PIPE_CONTROL_CS_STALL; - - /* - * CS_STALL suggests at least a post-sync write. - */ - flags |= PIPE_CONTROL_QW_WRITE; - flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; - - /* Just flush everything. Experiments have shown that reducing the - * number of bits based on the write domains has little performance - * impact. - */ - if (mode & EMIT_FLUSH) { - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; - flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; - flags |= PIPE_CONTROL_FLUSH_ENABLE; - } - if (mode & EMIT_INVALIDATE) { - flags |= PIPE_CONTROL_TLB_INVALIDATE; - flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; - flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; - - /* Workaround: we must issue a pipe_control with CS-stall bit - * set before a pipe_control command that has the state cache - * invalidate bit set. */ - gen7_render_ring_cs_stall_wa(rq); - } - - cs = intel_ring_begin(rq, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = GFX_OP_PIPE_CONTROL(4); - *cs++ = flags; - *cs++ = scratch_addr; - *cs++ = 0; - intel_ring_advance(rq, cs); - - return 0; -} - -static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) -{ - *cs++ = GFX_OP_PIPE_CONTROL(4); - *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | - PIPE_CONTROL_DEPTH_CACHE_FLUSH | - PIPE_CONTROL_DC_FLUSH_ENABLE | - PIPE_CONTROL_FLUSH_ENABLE | - PIPE_CONTROL_QW_WRITE | - PIPE_CONTROL_GLOBAL_GTT_IVB | - PIPE_CONTROL_CS_STALL); - *cs++ = i915_request_active_timeline(rq)->hwsp_offset; - *cs++ = rq->fence.seqno; - - *cs++ = MI_USER_INTERRUPT; - *cs++ = MI_NOOP; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); - - return cs; -} - -static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) -{ - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; - *cs++ = rq->fence.seqno; - - *cs++ = MI_USER_INTERRUPT; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); - - return cs; -} - -#define GEN7_XCS_WA 32 -static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) -{ - int i; - - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | - MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; - *cs++ = rq->fence.seqno; - - for (i = 0; i < GEN7_XCS_WA; i++) { - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; - *cs++ = rq->fence.seqno; - } - - *cs++ = MI_FLUSH_DW; - *cs++ = 0; - *cs++ = 0; - - *cs++ = MI_USER_INTERRUPT; - *cs++ = MI_NOOP; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); - - return cs; -} -#undef GEN7_XCS_WA - static void set_hwstam(struct intel_engine_cs *engine, u32 mask) { /* @@ -918,255 +482,6 @@ static void i9xx_submit_request(struct i915_request *request) intel_ring_set_tail(request->ring, request->tail)); } -static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) -{ - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH; - - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; - *cs++ = rq->fence.seqno; - - *cs++ = MI_USER_INTERRUPT; - *cs++ = MI_NOOP; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); - - return cs; -} - -#define GEN5_WA_STORES 8 /* must be at least 1! */ -static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) -{ - int i; - - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH; - - BUILD_BUG_ON(GEN5_WA_STORES < 1); - for (i = 0; i < GEN5_WA_STORES; i++) { - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; - *cs++ = rq->fence.seqno; - } - - *cs++ = MI_USER_INTERRUPT; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); - - return cs; -} -#undef GEN5_WA_STORES - -static void -gen5_irq_enable(struct intel_engine_cs *engine) -{ - gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); -} - -static void -gen5_irq_disable(struct intel_engine_cs *engine) -{ - gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); -} - -static void -i9xx_irq_enable(struct intel_engine_cs *engine) -{ - engine->i915->irq_mask &= ~engine->irq_enable_mask; - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); - intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); -} - -static void -i9xx_irq_disable(struct intel_engine_cs *engine) -{ - engine->i915->irq_mask |= engine->irq_enable_mask; - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); -} - -static void -i8xx_irq_enable(struct intel_engine_cs *engine) -{ - struct drm_i915_private *i915 = engine->i915; - - i915->irq_mask &= ~engine->irq_enable_mask; - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); - ENGINE_POSTING_READ16(engine, RING_IMR); -} - -static void -i8xx_irq_disable(struct intel_engine_cs *engine) -{ - struct drm_i915_private *i915 = engine->i915; - - i915->irq_mask |= engine->irq_enable_mask; - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); -} - -static int -bsd_ring_flush(struct i915_request *rq, u32 mode) -{ - u32 *cs; - - cs = intel_ring_begin(rq, 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_FLUSH; - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - return 0; -} - -static void -gen6_irq_enable(struct intel_engine_cs *engine) -{ - ENGINE_WRITE(engine, RING_IMR, - ~(engine->irq_enable_mask | engine->irq_keep_mask)); - - /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ - ENGINE_POSTING_READ(engine, RING_IMR); - - gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); -} - -static void -gen6_irq_disable(struct intel_engine_cs *engine) -{ - ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); - gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); -} - -static void -hsw_vebox_irq_enable(struct intel_engine_cs *engine) -{ - ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); - - /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ - ENGINE_POSTING_READ(engine, RING_IMR); - - gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); -} - -static void -hsw_vebox_irq_disable(struct intel_engine_cs *engine) -{ - ENGINE_WRITE(engine, RING_IMR, ~0); - gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); -} - -static int -i965_emit_bb_start(struct i915_request *rq, - u64 offset, u32 length, - unsigned int dispatch_flags) -{ - u32 *cs; - - cs = intel_ring_begin(rq, 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & - I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); - *cs++ = offset; - intel_ring_advance(rq, cs); - - return 0; -} - -/* Just userspace ABI convention to limit the wa batch bo to a resonable size */ -#define I830_BATCH_LIMIT SZ_256K -#define I830_TLB_ENTRIES (2) -#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) -static int -i830_emit_bb_start(struct i915_request *rq, - u64 offset, u32 len, - unsigned int dispatch_flags) -{ - u32 *cs, cs_offset = - intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_DEFAULT); - - GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE); - - cs = intel_ring_begin(rq, 6); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Evict the invalid PTE TLBs */ - *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; - *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; - *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ - *cs++ = cs_offset; - *cs++ = 0xdeadbeef; - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - - if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { - if (len > I830_BATCH_LIMIT) - return -ENOSPC; - - cs = intel_ring_begin(rq, 6 + 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - /* Blit the batch (which has now all relocs applied) to the - * stable batch scratch bo area (so that the CS never - * stumbles over its tlb invalidation bug) ... - */ - *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2); - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; - *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; - *cs++ = cs_offset; - *cs++ = 4096; - *cs++ = offset; - - *cs++ = MI_FLUSH; - *cs++ = MI_NOOP; - intel_ring_advance(rq, cs); - - /* ... and execute it. */ - offset = cs_offset; - } - - cs = intel_ring_begin(rq, 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; - *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : - MI_BATCH_NON_SECURE); - intel_ring_advance(rq, cs); - - return 0; -} - -static int -i915_emit_bb_start(struct i915_request *rq, - u64 offset, u32 len, - unsigned int dispatch_flags) -{ - u32 *cs; - - cs = intel_ring_begin(rq, 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; - *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : - MI_BATCH_NON_SECURE); - intel_ring_advance(rq, cs); - - return 0; -} - static void __ring_context_fini(struct intel_context *ce) { i915_vma_put(ce->state); @@ -1704,99 +1019,6 @@ static void gen6_bsd_submit_request(struct i915_request *request) intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); } -static int mi_flush_dw(struct i915_request *rq, u32 flags) -{ - u32 cmd, *cs; - - cs = intel_ring_begin(rq, 4); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - cmd = MI_FLUSH_DW; - - /* - * We always require a command barrier so that subsequent - * commands, such as breadcrumb interrupts, are strictly ordered - * wrt the contents of the write cache being flushed to memory - * (and thus being coherent from the CPU). - */ - cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; - - /* - * Bspec vol 1c.3 - blitter engine command streamer: - * "If ENABLED, all TLBs will be invalidated once the flush - * operation is complete. This bit is only valid when the - * Post-Sync Operation field is a value of 1h or 3h." - */ - cmd |= flags; - - *cs++ = cmd; - *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; - *cs++ = 0; - *cs++ = MI_NOOP; - - intel_ring_advance(rq, cs); - - return 0; -} - -static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) -{ - return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); -} - -static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) -{ - return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); -} - -static int -hsw_emit_bb_start(struct i915_request *rq, - u64 offset, u32 len, - unsigned int dispatch_flags) -{ - u32 *cs; - - cs = intel_ring_begin(rq, 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? - 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); - /* bit0-7 is the length on GEN6+ */ - *cs++ = offset; - intel_ring_advance(rq, cs); - - return 0; -} - -static int -gen6_emit_bb_start(struct i915_request *rq, - u64 offset, u32 len, - unsigned int dispatch_flags) -{ - u32 *cs; - - cs = intel_ring_begin(rq, 2); - if (IS_ERR(cs)) - return PTR_ERR(cs); - - *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? - 0 : MI_BATCH_NON_SECURE_I965); - /* bit0-7 is the length on GEN6+ */ - *cs++ = offset; - intel_ring_advance(rq, cs); - - return 0; -} - -/* Blitter support (SandyBridge+) */ - -static int gen6_ring_flush(struct i915_request *rq, u32 mode) -{ - return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); -} - static void i9xx_set_default_submission(struct intel_engine_cs *engine) { engine->submit_request = i9xx_submit_request; @@ -1843,11 +1065,11 @@ static void setup_irq(struct intel_engine_cs *engine) engine->irq_enable = gen5_irq_enable; engine->irq_disable = gen5_irq_disable; } else if (INTEL_GEN(i915) >= 3) { - engine->irq_enable = i9xx_irq_enable; - engine->irq_disable = i9xx_irq_disable; + engine->irq_enable = gen3_irq_enable; + engine->irq_disable = gen3_irq_disable; } else { - engine->irq_enable = i8xx_irq_enable; - engine->irq_disable = i8xx_irq_disable; + engine->irq_enable = gen2_irq_enable; + engine->irq_disable = gen2_irq_disable; } } @@ -1874,7 +1096,7 @@ static void setup_common(struct intel_engine_cs *engine) * equivalent to our next initial bread so we can elide * engine->emit_init_breadcrumb(). */ - engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; + engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; if (IS_GEN(i915, 5)) engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; @@ -1883,11 +1105,11 @@ static void setup_common(struct intel_engine_cs *engine) if (INTEL_GEN(i915) >= 6) engine->emit_bb_start = gen6_emit_bb_start; else if (INTEL_GEN(i915) >= 4) - engine->emit_bb_start = i965_emit_bb_start; + engine->emit_bb_start = gen4_emit_bb_start; else if (IS_I830(i915) || IS_I845G(i915)) engine->emit_bb_start = i830_emit_bb_start; else - engine->emit_bb_start = i915_emit_bb_start; + engine->emit_bb_start = gen3_emit_bb_start; } static void setup_rcs(struct intel_engine_cs *engine) @@ -1900,18 +1122,18 @@ static void setup_rcs(struct intel_engine_cs *engine) engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; if (INTEL_GEN(i915) >= 7) { - engine->emit_flush = gen7_render_ring_flush; - engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; + engine->emit_flush = gen7_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; } else if (IS_GEN(i915, 6)) { - engine->emit_flush = gen6_render_ring_flush; - engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; + engine->emit_flush = gen6_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; } else if (IS_GEN(i915, 5)) { - engine->emit_flush = gen4_render_ring_flush; + engine->emit_flush = gen4_emit_flush_rcs; } else { if (INTEL_GEN(i915) < 4) - engine->emit_flush = gen2_render_ring_flush; + engine->emit_flush = gen2_emit_flush; else - engine->emit_flush = gen4_render_ring_flush; + engine->emit_flush = gen4_emit_flush_rcs; engine->irq_enable_mask = I915_USER_INTERRUPT; } @@ -1929,15 +1151,15 @@ static void setup_vcs(struct intel_engine_cs *engine) /* gen6 bsd needs a special wa for tail updates */ if (IS_GEN(i915, 6)) engine->set_default_submission = gen6_bsd_set_default_submission; - engine->emit_flush = gen6_bsd_ring_flush; + engine->emit_flush = gen6_emit_flush_vcs; engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; if (IS_GEN(i915, 6)) - engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; else - engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; } else { - engine->emit_flush = bsd_ring_flush; + engine->emit_flush = gen4_emit_flush_vcs; if (IS_GEN(i915, 5)) engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; else @@ -1949,13 +1171,13 @@ static void setup_bcs(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; - engine->emit_flush = gen6_ring_flush; + engine->emit_flush = gen6_emit_flush_xcs; engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; if (IS_GEN(i915, 6)) - engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; else - engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; } static void setup_vecs(struct intel_engine_cs *engine) @@ -1964,12 +1186,12 @@ static void setup_vecs(struct intel_engine_cs *engine) GEM_BUG_ON(INTEL_GEN(i915) < 7); - engine->emit_flush = gen6_ring_flush; + engine->emit_flush = gen6_emit_flush_xcs; engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; - engine->irq_enable = hsw_vebox_irq_enable; - engine->irq_disable = hsw_vebox_irq_disable; + engine->irq_enable = hsw_irq_enable_vecs; + engine->irq_disable = hsw_irq_disable_vecs; - engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; } static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine, -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:30 +0100 Subject: [Intel-gfx] [PATCH 20/36] drm/i915/gem: Lift GPU relocation allocation In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-20-chris@chris-wilson.co.uk> Since we have reduced the relocations paths to just use the async GPU, we can lift the request allocation to the start of the relocations. Knowing that we use one request for all relocations will simplify tracking the relocation fence. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 98 ++++++++++--------- .../i915/gem/selftests/i915_gem_execbuffer.c | 5 +- 2 files changed, 56 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index bed7c7ea2723..9537fd87e3a4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -900,8 +900,6 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) static void eb_destroy(const struct i915_execbuffer *eb) { - GEM_BUG_ON(eb->reloc_cache.rq); - if (eb->array) eb_vma_array_put(eb->array); @@ -926,7 +924,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->rq = NULL; cache->target = NULL; } @@ -1026,13 +1023,9 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) static int reloc_gpu_flush(struct reloc_cache *cache) { - struct i915_request *rq; + struct i915_request *rq = cache->rq; int err; - rq = fetch_and_zero(&cache->rq); - if (!rq) - return 0; - if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1081,9 +1074,8 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) return err; } -static int __reloc_gpu_alloc(struct i915_execbuffer *eb, - struct intel_engine_cs *engine, - unsigned int len) +static int +__reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { struct reloc_cache *cache = &eb->reloc_cache; struct intel_gt_buffer_pool_node *pool; @@ -1173,33 +1165,14 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, return err; } -static bool reloc_can_use_engine(const struct intel_engine_cs *engine) -{ - return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); -} - -static u32 *reloc_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, + struct i915_vma *vma, + unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (unlikely(!cache->rq)) { - struct intel_engine_cs *engine = eb->engine; - - if (!reloc_can_use_engine(engine)) { - engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; - if (!engine) - return ERR_PTR(-ENODEV); - } - - err = __reloc_gpu_alloc(eb, engine, len); - if (unlikely(err)) - return ERR_PTR(err); - } - if (vma != cache->target) { err = reloc_move_to_gpu(cache->rq, vma); if (unlikely(err)) { @@ -1257,7 +1230,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_gpu(eb, vma, len); + batch = reloc_batch_grow(eb, vma, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1577,6 +1550,47 @@ static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) return required; } +static bool reloc_can_use_engine(const struct intel_engine_cs *engine) +{ + return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); +} + +static int reloc_gpu_alloc(struct i915_execbuffer *eb) +{ + struct intel_engine_cs *engine = eb->engine; + + if (!reloc_can_use_engine(engine)) { + engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; + if (!engine) + return -ENODEV; + } + + return __reloc_gpu_alloc(eb, engine); +} + +static int reloc_gpu(struct i915_execbuffer *eb) +{ + struct eb_vma *ev; + int flush, err; + + err = reloc_gpu_alloc(eb); + if (err) + return err; + GEM_BUG_ON(!eb->reloc_cache.rq); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + err = eb_relocate_vma(eb, ev); + if (err) + goto out; + } + +out: + flush = reloc_gpu_flush(&eb->reloc_cache); + if (!err) + err = flush; + return err; +} + static int eb_relocate(struct i915_execbuffer *eb) { int err; @@ -1594,7 +1608,6 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { struct eb_vma *ev, *en; - int flush; list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { long count; @@ -1607,18 +1620,14 @@ static int eb_relocate(struct i915_execbuffer *eb) list_del_init(&ev->reloc_link); } - list_for_each_entry(ev, &eb->relocs, reloc_link) { - err = eb_relocate_vma(eb, ev); + if (!list_empty(&eb->relocs)) { + err = reloc_gpu(eb); if (err) - break; + return err; } - - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; } - return err; + return 0; } static int eb_move_to_gpu(struct i915_execbuffer *eb) @@ -2618,9 +2627,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, batch = vma; } - /* All GPU relocation batches must be submitted prior to the user rq */ - GEM_BUG_ON(eb.reloc_cache.rq); - /* Allocate a request for this batch buffer nice and early. */ eb.request = i915_request_create(eb.context); if (IS_ERR(eb.request)) { diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 57c14d3340cd..50fe22d87ae1 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -36,6 +36,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) return err; + err = reloc_gpu_alloc(eb); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -63,7 +67,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, err = reloc_gpu_flush(&eb->reloc_cache); if (err) goto put_rq; - GEM_BUG_ON(eb->reloc_cache.rq); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:32 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:32 +0100 Subject: [Intel-gfx] [PATCH 22/36] drm/i915/gem: Add all GPU reloc awaits/signals en masse In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-22-chris@chris-wilson.co.uk> Asynchronous waits and signaling form a traditional semaphore with all the usual ordering problems with taking multiple locks. If we want to add more than one wait on a shared resource by the GPU, we must ensure that all the associated timelines are advanced atomically, ergo we must lock all the timelines en masse. Testcase: igt/gem_exec_reloc/basic-concurrent16 Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") References: https://gitlab.freedesktop.org/drm/intel/-/issues/1889 Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 114 ++++++++++++------ .../i915/gem/selftests/i915_gem_execbuffer.c | 24 ++-- 2 files changed, 93 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c48950d7f1c9..37855ae8f8b3 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -259,7 +259,6 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; - struct i915_vma *target; struct i915_request *rq; struct i915_vma *rq_vma; u32 *rq_cmd; @@ -924,7 +923,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->target = NULL; } static inline void *unmask_page(unsigned long p) @@ -1057,26 +1055,6 @@ static void reloc_gpu_flush(struct reloc_cache *cache) i915_request_add(rq); } -static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) -{ - struct drm_i915_gem_object *obj = vma->obj; - int err; - - i915_vma_lock(vma); - - if (obj->cache_dirty & ~obj->cache_coherent) - i915_gem_clflush_object(obj, 0); - obj->write_domain = 0; - - err = i915_request_await_object(rq, vma->obj, true); - if (err == 0) - err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - - i915_vma_unlock(vma); - - return err; -} - static int __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { @@ -1166,24 +1144,12 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) return err; } -static u32 *reloc_batch_grow(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (vma != cache->target) { - err = reloc_move_to_gpu(cache->rq, vma); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); - return ERR_PTR(err); - } - - cache->target = vma; - } - if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); @@ -1229,7 +1195,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_batch_grow(eb, vma, len); + batch = reloc_batch_grow(eb, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1549,6 +1515,78 @@ static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) return required; } +static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) +{ + struct i915_request *rq = cache->rq; + struct i915_vma *vma = ev->vma; + struct drm_i915_gem_object *obj = vma->obj; + int err; + + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, 0); + + obj->write_domain = I915_GEM_DOMAIN_RENDER; + obj->read_domains = I915_GEM_DOMAIN_RENDER; + + err = i915_request_await_object(rq, obj, true); + if (err) + return err; + + err = __i915_vma_move_to_active(vma, rq); + if (err) + return err; + + dma_resv_add_excl_fence(vma->resv, &rq->fence); + + return 0; +} + +static int +lock_relocs(struct i915_execbuffer *eb) +{ + struct ww_acquire_ctx acquire; + struct eb_vma *ev; + int err = 0; + + ww_acquire_init(&acquire, &reservation_ww_class); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + struct i915_vma *vma = ev->vma; + + err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); + if (err == -EDEADLK) { + struct eb_vma *unlock = ev, *en; + + list_for_each_entry_safe_continue_reverse(unlock, en, + &eb->relocs, + reloc_link) { + ww_mutex_unlock(&unlock->vma->resv->lock); + list_move_tail(&unlock->reloc_link, + &eb->relocs); + } + + GEM_BUG_ON(!list_is_first(&ev->reloc_link, + &eb->relocs)); + err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, + &acquire); + } + if (err) + break; + } + + ww_acquire_done(&acquire); + + list_for_each_entry_continue_reverse(ev, &eb->relocs, reloc_link) { + if (err == 0) + err = reloc_move_to_gpu(&eb->reloc_cache, ev); + ww_mutex_unlock(&ev->vma->resv->lock); + } + + ww_acquire_fini(&acquire); + + return err; +} + static bool reloc_can_use_engine(const struct intel_engine_cs *engine) { return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); @@ -1577,6 +1615,10 @@ static int reloc_gpu(struct i915_execbuffer *eb) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = lock_relocs(eb); + if (err) + goto out; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index faed6480a792..4f10b51f9a7e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -24,15 +24,15 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GENMASK_ULL(eb->reloc_cache.use_64bit_reloc ? 63 : 31, 0); const u32 *map = page_mask_bits(obj->mm.mapping); struct i915_request *rq; - struct i915_vma *vma; + struct eb_vma ev; int err; int i; - vma = i915_vma_instance(obj, eb->context->vm, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + ev.vma = i915_vma_instance(obj, eb->context->vm, NULL); + if (IS_ERR(ev.vma)) + return PTR_ERR(ev.vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + err = i915_vma_pin(ev.vma, 0, 0, PIN_USER | PIN_HIGH); if (err) return err; @@ -40,17 +40,22 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + list_add(&ev.reloc_link, &eb->relocs); + err = lock_relocs(eb); + if (err) + goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto unpin_vma; /* 8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + err = __reloc_entry_gpu(eb, ev.vma, offsets[0] * sizeof(u32), 0); if (err) goto unpin_vma; /* !8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + err = __reloc_entry_gpu(eb, ev.vma, offsets[1] * sizeof(u32), 1); if (err) goto unpin_vma; @@ -62,7 +67,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + err = __reloc_entry_gpu(eb, ev.vma, offsets[2] * sizeof(u32), 2); if (err) goto unpin_vma; @@ -97,7 +102,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, put_rq: i915_request_put(rq); unpin_vma: - i915_vma_unpin(vma); + i915_vma_unpin(ev.vma); return err; } @@ -121,6 +126,7 @@ static int igt_gpu_reloc(void *arg) } for_each_uabi_engine(eb.engine, eb.i915) { + INIT_LIST_HEAD(&eb.relocs); reloc_cache_init(&eb.reloc_cache, eb.i915); memset(map, POISON_INUSE, 4096); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:22 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:22 +0100 Subject: [Intel-gfx] [PATCH 12/36] drm/i915/gt: Track if an engine requires forcewake w/a In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-12-chris@chris-wilson.co.uk> Sometimes an engine might need to keep forcewake active while it is busy submitting requests for a particular workaround. Track such nuisance with engine->fw_domain. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +++++++++ drivers/gpu/drm/i915/gt/intel_ring_scheduler.c | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 3782e27c2945..ccdd69923793 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -313,6 +313,15 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + /* + * Some w/a require forcewake to be held (which prevents RC6) while + * a particular engine is active. If so, we set fw_domain to which + * domains need to be held for the duration of request activity, + * and 0 if none. + */ + unsigned int fw_domain; + unsigned int fw_active; + unsigned long context_tag; struct rb_node uabi_node; diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index aaff554865b1..777cab6d9540 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -60,6 +60,8 @@ static struct i915_request * schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) { __intel_gt_pm_get(engine->gt); + if (!engine->fw_active++ && engine->fw_domain) + intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); intel_engine_context_in(engine); return i915_request_get(rq); } @@ -74,6 +76,8 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_put(rq); intel_engine_context_out(engine); + if (!--engine->fw_active && engine->fw_domain) + intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:34 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:34 +0100 Subject: [Intel-gfx] [PATCH 24/36] drm/i915: Unpeel awaits on a proxy fence In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-24-chris@chris-wilson.co.uk> If the real target for a proxy fence is known at the time we are attaching our awaits, use the real target in preference to hooking up to the proxy. If use the real target instead, we can optimize the awaits, e.g. if it along the same engine, we can order the submission and avoid the wait-for-completion. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_request.c | 157 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_scheduler.c | 41 +++++++ drivers/gpu/drm/i915/i915_scheduler.h | 3 + 3 files changed, 201 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 9537e30f9439..02747c171c54 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -461,6 +462,7 @@ static bool fatal_error(int error) case 0: /* not an error! */ case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */ case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */ + case -EDEADLK: /* cyclic fence lockup (await_proxy) */ return false; default: return true; @@ -1251,6 +1253,138 @@ i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) return err; } +struct await_proxy { + struct wait_queue_entry base; + struct i915_request *request; + struct dma_fence *fence; + struct timer_list timer; + struct work_struct work; + int (*attach)(struct await_proxy *ap); + void *data; +}; + +static void await_proxy_work(struct work_struct *work) +{ + struct await_proxy *ap = container_of(work, typeof(*ap), work); + struct i915_request *rq = ap->request; + + del_timer_sync(&ap->timer); + + if (ap->fence) { + int err = 0; + + /* + * If the fence is external, we impose a 10s timeout. + * However, if the fence is internal, we skip a timeout in + * the belief that all fences are in-order (DAG, no cycles) + * and we can enforce forward progress by reset the GPU if + * necessary. A future fence, provided userspace, can trivially + * generate a cycle in the dependency graph, and so cause + * that entire cycle to become deadlocked and for no forward + * progress to either be made, and the driver being kept + * eternally awake. + */ + if (dma_fence_is_i915(ap->fence) && + !i915_sched_node_verify_dag(&rq->sched, + &to_request(ap->fence)->sched)) + err = -EDEADLK; + + if (!err) { + mutex_lock(&rq->context->timeline->mutex); + err = ap->attach(ap); + mutex_unlock(&rq->context->timeline->mutex); + } + + /* Don't flag an error for co-dependent scheduling */ + if (err == -EDEADLK) { + struct i915_sched_node *waiter = + &to_request(ap->fence)->sched; + struct i915_dependency *p; + + list_for_each_entry_lockless(p, + &rq->sched.waiters_list, + wait_link) { + if (p->waiter == waiter && + p->flags & I915_DEPENDENCY_WEAK) { + err = 0; + break; + } + } + } + + if (err < 0) + i915_sw_fence_set_error_once(&rq->submit, err); + } + + i915_sw_fence_complete(&rq->submit); + + dma_fence_put(ap->fence); + kfree(ap); +} + +static int +await_proxy_wake(struct wait_queue_entry *entry, + unsigned int mode, + int flags, + void *fence) +{ + struct await_proxy *ap = container_of(entry, typeof(*ap), base); + + ap->fence = dma_fence_get(fence); + schedule_work(&ap->work); + + return 0; +} + +static void +await_proxy_timer(struct timer_list *t) +{ + struct await_proxy *ap = container_of(t, typeof(*ap), timer); + + if (dma_fence_remove_proxy_listener(ap->base.private, &ap->base)) { + struct i915_request *rq = ap->request; + + pr_notice("Asynchronous wait on unset proxy fence by %s:%s:%llx timed out\n", + rq->fence.ops->get_driver_name(&rq->fence), + rq->fence.ops->get_timeline_name(&rq->fence), + rq->fence.seqno); + i915_sw_fence_set_error_once(&rq->submit, -ETIMEDOUT); + + schedule_work(&ap->work); + } +} + +static int +__i915_request_await_proxy(struct i915_request *rq, + struct dma_fence *fence, + unsigned long timeout, + int (*attach)(struct await_proxy *ap), + void *data) +{ + struct await_proxy *ap; + + ap = kzalloc(sizeof(*ap), I915_FENCE_GFP); + if (!ap) + return -ENOMEM; + + i915_sw_fence_await(&rq->submit); + mark_external(rq); + + ap->base.private = fence; + ap->base.func = await_proxy_wake; + ap->request = rq; + INIT_WORK(&ap->work, await_proxy_work); + ap->attach = attach; + ap->data = data; + + timer_setup(&ap->timer, await_proxy_timer, 0); + if (timeout) + mod_timer(&ap->timer, round_jiffies_up(jiffies + timeout)); + + dma_fence_add_proxy_listener(fence, &ap->base); + return 0; +} + int i915_request_await_execution(struct i915_request *rq, struct dma_fence *fence, @@ -1349,6 +1483,24 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from) return 0; } +static int await_proxy(struct await_proxy *ap) +{ + return i915_request_await_dma_fence(ap->request, ap->fence); +} + +static int +i915_request_await_proxy(struct i915_request *rq, struct dma_fence *fence) +{ + /* + * Wait until we know the real fence so that can optimise the + * inter-fence synchronisation. + */ + return __i915_request_await_proxy(rq, fence, + i915_fence_context_timeout(rq->i915, + fence->context), + await_proxy, NULL); +} + int i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) { @@ -1356,6 +1508,9 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) unsigned int nchild = 1; int ret; + /* Unpeel the proxy fence if the real target is already known */ + fence = dma_fence_proxy_get_real(fence); + /* * Note that if the fence-array was created in signal-on-any mode, * we should *not* decompose it into its individual fences. However, @@ -1395,6 +1550,8 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) if (dma_fence_is_i915(fence)) ret = i915_request_await_request(rq, to_request(fence)); + else if (dma_fence_is_proxy(fence)) + ret = i915_request_await_proxy(rq, fence); else ret = i915_request_await_external(rq, fence); if (ret < 0) diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index cbb880b10c65..250832768279 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -469,6 +469,47 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node, return 0; } +bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, + struct i915_sched_node *signaler) +{ + struct i915_dependency *dep, *p; + struct i915_dependency stack; + bool result = false; + LIST_HEAD(dfs); + + if (list_empty(&waiter->waiters_list)) + return true; + + spin_lock_irq(&schedule_lock); + + stack.signaler = signaler; + list_add(&stack.dfs_link, &dfs); + + list_for_each_entry(dep, &dfs, dfs_link) { + struct i915_sched_node *node = dep->signaler; + + if (node_signaled(node)) + continue; + + list_for_each_entry(p, &node->signalers_list, signal_link) { + if (p->signaler == waiter) + goto out; + + if (list_empty(&p->dfs_link)) + list_add_tail(&p->dfs_link, &dfs); + } + } + + result = true; +out: + list_for_each_entry_safe(dep, p, &dfs, dfs_link) + INIT_LIST_HEAD(&dep->dfs_link); + + spin_unlock_irq(&schedule_lock); + + return result; +} + void i915_sched_node_fini(struct i915_sched_node *node) { struct i915_dependency *dep, *tmp; diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 6f0bf00fc569..13432add8929 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -28,6 +28,9 @@ void i915_sched_node_init(struct i915_sched_node *node); void i915_sched_node_reinit(struct i915_sched_node *node); +bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, + struct i915_sched_node *signal); + bool __i915_sched_node_add_dependency(struct i915_sched_node *node, struct i915_sched_node *signal, struct i915_dependency *dep, -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:39 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:39 +0100 Subject: [Intel-gfx] [PATCH 29/36] drm/i915/gt: Declare when we enabled timeslicing In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-29-chris@chris-wilson.co.uk> Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING v2: Only declare timeslicing if we can safely preempt userspace. Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3802 Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854 Signed-off-by: Chris Wilson Cc: Kenneth Graunke Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + include/uapi/drm/i915_drm.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 848decee9066..8415511f1465 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) MAP(HAS_PREEMPTION, PREEMPTION), MAP(HAS_SEMAPHORES, SEMAPHORES), MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), + MAP(HAS_TIMESLICES, TIMESLICING), #undef MAP }; struct intel_engine_cs *engine; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 704dd0e3bc1d..1ee227b5131a 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait { #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) #define I915_PARAM_HUC_STATUS 42 -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:45 +0100 Subject: [Intel-gfx] [PATCH 35/36] drm/i915/gem: Asynchronous GTT unbinding In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-35-chris@chris-wilson.co.uk> It is reasonably common for userspace (even modern drivers like iris) to reuse an active address for a new buffer. This would cause the application to stall under its mutex (originally struct_mutex) until the old batches were idle and it could synchronously remove the stale PTE. However, we can queue up a job that waits on the signal for the old nodes to complete and upon those signals, remove the old nodes replacing them with the new ones for the batch. This is still CPU driven, but in theory we can do the GTT patching from the GPU. The job itself has a completion signal allowing the execbuf to wait upon the rebinding, and also other observers to coordinate with the common VM activity. Letting userspace queue up more work, lets it do more stuff without blocking other clients. In turn, we take care not to let it too much concurrent work, creating a small number of queues for each context to limit the number of concurrent tasks. The implementation relies on only scheduling one unbind operation per vma as we use the unbound vma->node location to track the stale PTE. Closes: https://gitlab.freedesktop.org/drm/intel/issues/1402 Signed-off-by: Chris Wilson Cc: Matthew Auld Cc: Andi Shyti --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 810 ++++++++++++++++-- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 4 + drivers/gpu/drm/i915/gt/intel_gtt.h | 2 + drivers/gpu/drm/i915/gt/intel_ppgtt.c | 3 +- drivers/gpu/drm/i915/i915_gem.c | 7 + drivers/gpu/drm/i915/i915_gem_gtt.c | 5 + drivers/gpu/drm/i915/i915_vma.c | 71 +- drivers/gpu/drm/i915/i915_vma.h | 4 + 10 files changed, 813 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index b400eed1f435..49bfae968215 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -19,6 +19,7 @@ #include "gt/intel_gt.h" #include "gt/intel_gt_buffer_pool.h" #include "gt/intel_gt_pm.h" +#include "gt/intel_gt_requests.h" #include "gt/intel_ring.h" #include "i915_drv.h" @@ -32,6 +33,9 @@ struct eb_vma { struct i915_vma *vma; unsigned int flags; + struct drm_mm_node hole; + unsigned int bind_flags; + /** This vma's place in the execbuf reservation list */ struct drm_i915_gem_exec_object2 *exec; struct list_head bind_link; @@ -49,9 +53,10 @@ struct eb_vma_array { #define __EXEC_OBJECT_HAS_PIN BIT(31) #define __EXEC_OBJECT_HAS_FENCE BIT(30) -#define __EXEC_OBJECT_NEEDS_MAP BIT(29) -#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ +#define __EXEC_OBJECT_HAS_PAGES BIT(29) +#define __EXEC_OBJECT_NEEDS_MAP BIT(28) +#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ #define __EXEC_HAS_RELOC BIT(31) #define __EXEC_INTERNAL_FLAGS (~0u << 31) @@ -65,11 +70,12 @@ struct eb_vma_array { I915_EXEC_RESOURCE_STREAMER) /* Catch emission of unexpected errors for CI! */ +#define __EINVAL__ 22 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) #undef EINVAL #define EINVAL ({ \ DRM_DEBUG_DRIVER("EINVAL at %s:%d\n", __func__, __LINE__); \ - 22; \ + __EINVAL__; \ }) #endif @@ -309,6 +315,12 @@ static struct eb_vma_array *eb_vma_array_create(unsigned int count) return arr; } +static struct eb_vma_array *eb_vma_array_get(struct eb_vma_array *arr) +{ + kref_get(&arr->kref); + return arr; +} + static inline void eb_unreserve_vma(struct eb_vma *ev) { struct i915_vma *vma = ev->vma; @@ -319,8 +331,12 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) if (ev->flags & __EXEC_OBJECT_HAS_PIN) __i915_vma_unpin(vma); + if (ev->flags & __EXEC_OBJECT_HAS_PAGES) + i915_vma_put_pages(vma); + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | - __EXEC_OBJECT_HAS_FENCE); + __EXEC_OBJECT_HAS_FENCE | + __EXEC_OBJECT_HAS_PAGES); } static void eb_vma_array_destroy(struct kref *kref) @@ -406,7 +422,7 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry, const struct i915_vma *vma, unsigned int flags) { - if (vma->node.size < entry->pad_to_size) + if (vma->node.size < max(vma->size, entry->pad_to_size)) return true; if (entry->alignment && !IS_ALIGNED(vma->node.start, entry->alignment)) @@ -479,12 +495,18 @@ eb_pin_vma(struct i915_execbuffer *eb, if (entry->flags & EXEC_OBJECT_PINNED) return false; + /* Concurrent async binds in progress, get in the queue */ + if (!i915_active_is_idle(&vma->vm->active)) + return false; + /* Failing that pick any _free_ space if suitable */ if (unlikely(i915_vma_pin(vma, entry->pad_to_size, entry->alignment, eb_pin_flags(entry, ev->flags) | - PIN_USER | PIN_NOEVICT))) + PIN_USER | + PIN_NOEVICT | + PIN_NOSEARCH))) return false; } @@ -609,85 +631,711 @@ eb_add_vma(struct i915_execbuffer *eb, list_add_tail(&ev->lock_link, &eb->lock); } -static int eb_reserve_vma(const struct i915_execbuffer *eb, - struct eb_vma *ev, - u64 pin_flags) +struct eb_vm_work { + struct dma_fence_work base; + struct list_head unbound; + struct eb_vma_array *array; + struct i915_address_space *vm; + struct list_head evict_list; + u64 *p_flags; + u64 active; +}; + +static inline u64 node_end(const struct drm_mm_node *node) +{ + return node->start + node->size; +} + +static int set_bind_fence(struct i915_vma *vma, struct eb_vm_work *work) +{ + struct dma_fence *prev; + int err = 0; + + lockdep_assert_held(&vma->vm->mutex); + prev = i915_active_set_exclusive(&vma->active, &work->base.dma); + if (unlikely(prev)) { + err = i915_sw_fence_await_dma_fence(&work->base.chain, prev, 0, + GFP_NOWAIT | __GFP_NOWARN); + dma_fence_put(prev); + } + + return err < 0 ? err : 0; +} + +static int await_evict(struct eb_vm_work *work, struct i915_vma *vma) +{ + int err; + + if (rcu_access_pointer(vma->active.excl.fence) == &work->base.dma) + return 0; + + /* Wait for all other previous activity */ + err = i915_sw_fence_await_active(&work->base.chain, + &vma->active, + I915_ACTIVE_AWAIT_ACTIVE); + /* Then insert along the exclusive vm->mutex timeline */ + if (err == 0) + err = set_bind_fence(vma, work); + + return err; +} + +static int +evict_for_node(struct eb_vm_work *work, + struct eb_vma *const target, + unsigned int flags) +{ + struct i915_address_space *vm = target->vma->vm; + const unsigned long color = target->vma->node.color; + const u64 start = target->vma->node.start; + const u64 end = start + target->vma->node.size; + u64 hole_start = start, hole_end = end; + struct i915_vma *vma, *next; + struct drm_mm_node *node; + LIST_HEAD(evict_list); + LIST_HEAD(steal_list); + int err = 0; + + lockdep_assert_held(&vm->mutex); + GEM_BUG_ON(drm_mm_node_allocated(&target->vma->node)); + GEM_BUG_ON(!IS_ALIGNED(start, I915_GTT_PAGE_SIZE)); + GEM_BUG_ON(!IS_ALIGNED(end, I915_GTT_PAGE_SIZE)); + + if (i915_vm_has_cache_coloring(vm)) { + /* Expand search to cover neighbouring guard pages (or lack!) */ + if (hole_start) + hole_start -= I915_GTT_PAGE_SIZE; + + /* Always look at the page afterwards to avoid the end-of-GTT */ + hole_end += I915_GTT_PAGE_SIZE; + } + GEM_BUG_ON(hole_start >= hole_end); + + drm_mm_for_each_node_in_range(node, &vm->mm, hole_start, hole_end) { + GEM_BUG_ON(node == &target->vma->node); + + /* If we find any non-objects (!vma), we cannot evict them */ + if (node->color == I915_COLOR_UNEVICTABLE) { + err = -ENOSPC; + goto err; + } + + /* + * If we are using coloring to insert guard pages between + * different cache domains within the address space, we have + * to check whether the objects on either side of our range + * abutt and conflict. If they are in conflict, then we evict + * those as well to make room for our guard pages. + */ + if (i915_vm_has_cache_coloring(vm)) { + if (node_end(node) == start && node->color == color) + continue; + + if (node->start == end && node->color == color) + continue; + } + + GEM_BUG_ON(!drm_mm_node_allocated(node)); + vma = container_of(node, typeof(*vma), node); + + if (i915_vma_is_pinned(vma)) { + err = -ENOSPC; + goto err; + } + + /* If this VMA is already being freed, or idle, steal it! */ + if (!i915_active_acquire_if_busy(&vma->active)) { + list_move(&vma->vm_link, &steal_list); + continue; + } + + if (flags & PIN_NONBLOCK) + err = -EAGAIN; + else + err = await_evict(work, vma); + i915_active_release(&vma->active); + if (err) + goto err; + + GEM_BUG_ON(!i915_vma_is_active(vma)); + list_move(&vma->vm_link, &evict_list); + } + + list_for_each_entry_safe(vma, next, &steal_list, vm_link) { + atomic_and(~I915_VMA_BIND_MASK, &vma->flags); + __i915_vma_evict(vma); + drm_mm_remove_node(&vma->node); + /* No ref held; vma may now be concurrently freed */ + } + + /* No overlapping nodes to evict, claim the slot for ourselves! */ + if (list_empty(&evict_list)) + return drm_mm_reserve_node(&vm->mm, &target->vma->node); + + /* + * Mark this range as reserved. + * + * We have not yet removed the PTEs for the old evicted nodes, so + * must prevent this range from being reused for anything else. The + * PTE will be cleared when the range is idle (during the rebind + * phase in the worker). + */ + target->hole.color = I915_COLOR_UNEVICTABLE; + target->hole.start = start; + target->hole.size = end; + + list_for_each_entry(vma, &evict_list, vm_link) { + target->hole.start = + min(target->hole.start, vma->node.start); + target->hole.size = + max(target->hole.size, node_end(&vma->node)); + + GEM_BUG_ON(vma->node.mm != &vm->mm); + drm_mm_remove_node(&vma->node); + atomic_and(~I915_VMA_BIND_MASK, &vma->flags); + GEM_BUG_ON(i915_vma_is_pinned(vma)); + } + list_splice(&evict_list, &work->evict_list); + + target->hole.size -= target->hole.start; + + return drm_mm_reserve_node(&vm->mm, &target->hole); + +err: + list_splice(&evict_list, &vm->bound_list); + list_splice(&steal_list, &vm->bound_list); + return err; +} + +static int +evict_in_range(struct eb_vm_work *work, + struct eb_vma * const target, + u64 start, u64 end, u64 align) +{ + struct i915_address_space *vm = target->vma->vm; + struct i915_vma *active = NULL; + struct i915_vma *vma, *next; + struct drm_mm_scan scan; + LIST_HEAD(evict_list); + bool found = false; + + lockdep_assert_held(&vm->mutex); + + drm_mm_scan_init_with_range(&scan, &vm->mm, + target->vma->node.size, + align, + target->vma->node.color, + start, end, + DRM_MM_INSERT_BEST); + + list_for_each_entry_safe(vma, next, &vm->bound_list, vm_link) { + if (i915_vma_is_pinned(vma)) + continue; + + if (vma == active) + active = ERR_PTR(-EAGAIN); + + /* Prefer to reuse idle nodes; push all active vma to the end */ + if (active != ERR_PTR(-EAGAIN) && i915_vma_is_active(vma)) { + if (!active) + active = vma; + + list_move_tail(&vma->vm_link, &vm->bound_list); + continue; + } + + list_move(&vma->vm_link, &evict_list); + if (drm_mm_scan_add_block(&scan, &vma->node)) { + target->vma->node.start = + round_up(scan.hit_start, align); + found = true; + break; + } + } + + list_for_each_entry(vma, &evict_list, vm_link) + drm_mm_scan_remove_block(&scan, &vma->node); + list_splice(&evict_list, &vm->bound_list); + if (!found) + return -ENOSPC; + + return evict_for_node(work, target, 0); +} + +static u64 random_offset(u64 start, u64 end, u64 len, u64 align) +{ + u64 range, addr; + + GEM_BUG_ON(range_overflows(start, len, end)); + GEM_BUG_ON(round_up(start, align) > round_down(end - len, align)); + + range = round_down(end - len, align) - round_up(start, align); + if (range) { + if (sizeof(unsigned long) == sizeof(u64)) { + addr = get_random_long(); + } else { + addr = get_random_int(); + if (range > U32_MAX) { + addr <<= 32; + addr |= get_random_int(); + } + } + div64_u64_rem(addr, range, &addr); + start += addr; + } + + return round_up(start, align); +} + +static u64 align0(u64 align) +{ + return align <= I915_GTT_MIN_ALIGNMENT ? 0 : align; +} + +static struct drm_mm_node *__best_hole(struct drm_mm *mm, u64 size) +{ + struct rb_node *rb = mm->holes_size.rb_root.rb_node; + struct drm_mm_node *best = NULL; + + do { + struct drm_mm_node *node = + rb_entry(rb, struct drm_mm_node, rb_hole_size); + + if (size <= node->hole_size) { + best = node; + rb = rb->rb_right; + } else { + rb = rb->rb_left; + } + } while (rb); + + return best; +} + +static int best_hole(struct drm_mm *mm, struct drm_mm_node *node, + u64 start, u64 end, u64 align) +{ + struct drm_mm_node *hole; + u64 size = node->size; + + do { + hole = __best_hole(mm, size); + if (!hole) + return -ENOSPC; + + node->start = round_up(max(start, drm_mm_hole_node_start(hole)), + align); + if (min(drm_mm_hole_node_end(hole), end) >= + node->start + node->size) + return drm_mm_reserve_node(mm, node); + + /* + * Too expensive to search for every single hole every time, + * so just look for the next bigger hole, introducing enough + * space for alignments. Finding the smallest hole with ideal + * alignment scales very poorly, so we choose to waste space + * if an alignment is forced. On the other hand, simply + * randomly selecting an offset in 48b space will cause us + * to use the majority of that space and exhaust all memory + * in storing the page directories. Compromise is required. + */ + size = hole->hole_size + align; + } while (1); +} + +static int eb_reserve_vma(struct eb_vm_work *work, struct eb_vma *ev) { struct drm_i915_gem_exec_object2 *entry = ev->exec; + const unsigned int exec_flags = ev->flags; struct i915_vma *vma = ev->vma; + struct i915_address_space *vm = vma->vm; + u64 start = 0, end = vm->total; + u64 align = entry->alignment ?: I915_GTT_MIN_ALIGNMENT; + unsigned int bind_flags; int err; - if (drm_mm_node_allocated(&vma->node) && - eb_vma_misplaced(entry, vma, ev->flags)) { - err = i915_vma_unbind(vma); - if (err) - return err; + lockdep_assert_held(&vm->mutex); + + bind_flags = PIN_USER; + if (exec_flags & EXEC_OBJECT_NEEDS_GTT) + bind_flags |= PIN_GLOBAL; + + if (drm_mm_node_allocated(&vma->node)) + goto pin; + + GEM_BUG_ON(i915_vma_is_pinned(vma)); + GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_BIND_MASK)); + GEM_BUG_ON(i915_active_fence_isset(&vma->active.excl)); + GEM_BUG_ON(!vma->size); + + /* Reuse old address (if it doesn't conflict with new requirements) */ + if (eb_vma_misplaced(entry, vma, exec_flags)) { + vma->node.start = entry->offset & PIN_OFFSET_MASK; + vma->node.size = max(entry->pad_to_size, vma->size); + vma->node.color = 0; + if (i915_vm_has_cache_coloring(vm)) + vma->node.color = vma->obj->cache_level; } - err = i915_vma_pin(vma, - entry->pad_to_size, entry->alignment, - eb_pin_flags(entry, ev->flags) | pin_flags); - if (err) - return err; + /* + * Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, + * limit address to the first 4GBs for unflagged objects. + */ + if (!(exec_flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)) + end = min_t(u64, end, (1ULL << 32) - I915_GTT_PAGE_SIZE); - if (entry->offset != vma->node.start) { - entry->offset = vma->node.start | UPDATE; - eb->args->flags |= __EXEC_HAS_RELOC; + align = max(align, vma->display_alignment); + if (exec_flags & __EXEC_OBJECT_NEEDS_MAP) { + vma->node.size = max_t(u64, vma->node.size, vma->fence_size); + end = min_t(u64, end, i915_vm_to_ggtt(vm)->mappable_end); + align = max_t(u64, align, vma->fence_alignment); } - if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) { - err = i915_vma_pin_fence(vma); - if (unlikely(err)) { - i915_vma_unpin(vma); + if (exec_flags & __EXEC_OBJECT_NEEDS_BIAS) + start = BATCH_OFFSET_BIAS; + + GEM_BUG_ON(!vma->node.size); + if (vma->node.size > end - start) + return -E2BIG; + + /* Try the user's preferred location first (mandatory if soft-pinned) */ + err = -__EINVAL__; + if (vma->node.start >= start && + IS_ALIGNED(vma->node.start, align) && + !range_overflows(vma->node.start, vma->node.size, end)) { + unsigned int pin_flags; + + if (drm_mm_reserve_node(&vm->mm, &vma->node) == 0) + goto pin; + + pin_flags = 0; + if (!(exec_flags & EXEC_OBJECT_PINNED)) + pin_flags = PIN_NONBLOCK; + + err = evict_for_node(work, ev, pin_flags); + if (err == 0) + goto pin; + } + if (exec_flags & EXEC_OBJECT_PINNED) + return err; + + /* Try the first available free space */ + if (!best_hole(&vm->mm, &vma->node, start, end, align)) + goto pin; + + /* Pick a random slot and see if it's available [O(N) worst case] */ + vma->node.start = random_offset(start, end, vma->node.size, align); + if (evict_for_node(work, ev, 0) == 0) + goto pin; + + /* Otherwise search all free space [degrades to O(N^2)] */ + if (drm_mm_insert_node_in_range(&vm->mm, &vma->node, + vma->node.size, + align0(align), + vma->node.color, + start, end, + DRM_MM_INSERT_BEST) == 0) + goto pin; + + /* Pretty busy! Loop over "LRU" and evict oldest in our search range */ + err = evict_in_range(work, ev, start, end, align); + if (unlikely(err)) + return err; + +pin: + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { + err = __i915_vma_pin_fence(vma); /* XXX no waiting */ + if (unlikely(err)) return err; - } if (vma->fence) ev->flags |= __EXEC_OBJECT_HAS_FENCE; } + bind_flags &= ~atomic_read(&vma->flags); + if (bind_flags) { + err = set_bind_fence(vma, work); + if (unlikely(err)) + return err; + + atomic_add(I915_VMA_PAGES_ACTIVE, &vma->pages_count); + atomic_or(bind_flags, &vma->flags); + + if (i915_vma_is_ggtt(vma)) + __i915_vma_set_map_and_fenceable(vma); + + GEM_BUG_ON(!i915_vma_is_active(vma)); + list_move_tail(&vma->vm_link, &vm->bound_list); + ev->bind_flags = bind_flags; + } + __i915_vma_pin(vma); /* and release */ + + GEM_BUG_ON(!bind_flags && !drm_mm_node_allocated(&vma->node)); + GEM_BUG_ON(!(drm_mm_node_allocated(&vma->node) ^ + drm_mm_node_allocated(&ev->hole))); + + if (entry->offset != vma->node.start) { + entry->offset = vma->node.start | UPDATE; + *work->p_flags |= __EXEC_HAS_RELOC; + } + ev->flags |= __EXEC_OBJECT_HAS_PIN; GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags)); return 0; } -static int eb_reserve(struct i915_execbuffer *eb) +static int __eb_bind_vma(struct eb_vm_work *work, int err) { - const unsigned int count = eb->buffer_count; - unsigned int pin_flags = PIN_USER | PIN_NONBLOCK; - struct list_head last; + struct i915_address_space *vm = work->vm; struct eb_vma *ev; - unsigned int i, pass; - int err = 0; + + GEM_BUG_ON(!intel_gt_pm_is_awake(vm->gt)); /* - * Attempt to pin all of the buffers into the GTT. - * This is done in 3 phases: - * - * 1a. Unbind all objects that do not match the GTT constraints for - * the execbuffer (fenceable, mappable, alignment etc). - * 1b. Increment pin count for already bound objects. - * 2. Bind new objects. - * 3. Decrement pin count. - * - * This avoid unnecessary unbinding of later objects in order to make - * room for the earlier objects *unless* we need to defragment. + * We have to wait until the stale nodes are completely idle before + * we can remove their PTE and unbind their pages. Hence, after + * claiming their slot in the drm_mm, we defer their removal to + * after the fences are signaled. */ + if (!list_empty(&work->evict_list)) { + struct i915_vma *vma, *vn; + + mutex_lock(&vm->mutex); + list_for_each_entry_safe(vma, vn, &work->evict_list, vm_link) { + GEM_BUG_ON(vma->vm != vm); + __i915_vma_evict(vma); + GEM_BUG_ON(!i915_vma_is_active(vma)); + } + mutex_unlock(&vm->mutex); + } + + /* + * Now we know the nodes we require in drm_mm are idle, we can + * replace the PTE in those ranges with our own. + */ + list_for_each_entry(ev, &work->unbound, bind_link) { + struct i915_vma *vma = ev->vma; + + if (!ev->bind_flags) + goto put; + + GEM_BUG_ON(vma->vm != vm); + GEM_BUG_ON(!i915_vma_is_active(vma)); + + if (err == 0) + err = vma->ops->bind_vma(vma, + vma->obj->cache_level, + ev->bind_flags | + I915_VMA_ALLOC); + if (err) + atomic_and(~ev->bind_flags, &vma->flags); + + if (drm_mm_node_allocated(&ev->hole)) { + mutex_lock(&vm->mutex); + GEM_BUG_ON(ev->hole.mm != &vm->mm); + GEM_BUG_ON(ev->hole.color != I915_COLOR_UNEVICTABLE); + GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); + drm_mm_remove_node(&ev->hole); + if (!err) { + drm_mm_reserve_node(&vm->mm, &vma->node); + GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); + } else { + list_del_init(&vma->vm_link); + } + mutex_unlock(&vm->mutex); + } + ev->bind_flags = 0; + +put: + GEM_BUG_ON(drm_mm_node_allocated(&ev->hole)); + } + INIT_LIST_HEAD(&work->unbound); + + return err; +} + +static int eb_bind_vma(struct dma_fence_work *base) +{ + struct eb_vm_work *work = container_of(base, typeof(*work), base); + + return __eb_bind_vma(work, 0); +} + +static void eb_vma_work_release(struct dma_fence_work *base) +{ + struct eb_vm_work *work = container_of(base, typeof(*work), base); + + if (work->active) { + if (!list_empty(&work->unbound)) { + GEM_BUG_ON(!work->base.dma.error); + __eb_bind_vma(work, work->base.dma.error); + } + i915_active_release(&work->vm->active); + } + + eb_vma_array_put(work->array); +} + +static const struct dma_fence_work_ops eb_bind_ops = { + .name = "eb_bind", + .work = eb_bind_vma, + .release = eb_vma_work_release, +}; + +static struct eb_vm_work *eb_vm_work(struct i915_execbuffer *eb) +{ + struct eb_vm_work *work; + + work = kzalloc(sizeof(*work), GFP_KERNEL); + if (!work) + return NULL; + + dma_fence_work_init(&work->base, &eb_bind_ops); + list_replace_init(&eb->unbound, &work->unbound); + work->array = eb_vma_array_get(eb->array); + work->p_flags = &eb->args->flags; + work->vm = eb->context->vm; + + /* Preallocate our slot in vm->active, outside of vm->mutex */ + work->active = i915_gem_context_async_id(eb->gem_context); + if (i915_active_acquire_for_context(&work->vm->active, work->active)) { + work->active = 0; + work->base.dma.error = -ENOMEM; + dma_fence_work_commit(&work->base); + return NULL; + } + + INIT_LIST_HEAD(&work->evict_list); + + GEM_BUG_ON(list_empty(&work->unbound)); + GEM_BUG_ON(!list_empty(&eb->unbound)); + + return work; +} + +static int eb_vm_throttle(struct eb_vm_work *work) +{ + struct dma_fence *p; + int err; + + /* Keep async work queued per context */ + p = __i915_active_ref(&work->vm->active, work->active, &work->base.dma); + if (IS_ERR_OR_NULL(p)) + return PTR_ERR_OR_ZERO(p); + + err = i915_sw_fence_await_dma_fence(&work->base.chain, p, 0, + GFP_NOWAIT | __GFP_NOWARN); + dma_fence_put(p); + + return err < 0 ? err : 0; +} + +static int eb_prepare_vma(struct eb_vma *ev) +{ + struct i915_vma *vma = ev->vma; + int err; + + ev->hole.flags = 0; + ev->bind_flags = 0; - if (mutex_lock_interruptible(&eb->i915->drm.struct_mutex)) - return -EINTR; + if (!(ev->flags & __EXEC_OBJECT_HAS_PAGES)) { + err = i915_vma_get_pages(vma); + if (err) + return err; + + ev->flags |= __EXEC_OBJECT_HAS_PAGES; + } + + return 0; +} + +static int eb_reserve(struct i915_execbuffer *eb) +{ + const unsigned int count = eb->buffer_count; + struct i915_address_space *vm = eb->context->vm; + struct list_head last; + unsigned int i, pass; + struct eb_vma *ev; + int err = 0; pass = 0; do { + struct eb_vm_work *work; + list_for_each_entry(ev, &eb->unbound, bind_link) { - err = eb_reserve_vma(eb, ev, pin_flags); + err = eb_prepare_vma(ev); + switch (err) { + case 0: + break; + case -EAGAIN: + goto retry; + default: + return err; + } + } + + work = eb_vm_work(eb); + if (!work) + return -ENOMEM; + + /* No allocations allowed beyond this point */ + if (mutex_lock_interruptible(&vm->mutex)) { + work->base.dma.error = -EINTR; + dma_fence_work_commit(&work->base); + return -EINTR; + } + + err = eb_vm_throttle(work); + if (err) { + mutex_unlock(&vm->mutex); + work->base.dma.error = err; + dma_fence_work_commit(&work->base); + return err; + } + + list_for_each_entry(ev, &work->unbound, bind_link) { + struct i915_vma *vma = ev->vma; + + /* + * Check if this node is being evicted or must be. + * + * As we use the single node inside the vma to track + * both the eviction and where to insert the new node, + * we cannot handle migrating the vma inside the worker. + */ + if (drm_mm_node_allocated(&vma->node)) { + if (eb_vma_misplaced(ev->exec, vma, ev->flags)) { + err = -ENOSPC; + break; + } + } else { + if (i915_vma_is_active(vma)) { + err = -ENOSPC; + break; + } + } + + err = i915_active_acquire(&vma->active); + if (!err) { + err = eb_reserve_vma(work, ev); + i915_active_release(&vma->active); + } if (err) break; } - if (!(err == -ENOSPC || err == -EAGAIN)) - break; + mutex_unlock(&vm->mutex); + + dma_fence_get(&work->base.dma); + dma_fence_work_commit_imm(&work->base); + if (err == -ENOSPC && dma_fence_wait(&work->base.dma, true)) + err = -EINTR; + dma_fence_put(&work->base.dma); + if (err != -ENOSPC) + return err; + +retry: /* Resort *all* the objects into priority order */ INIT_LIST_HEAD(&eb->unbound); INIT_LIST_HEAD(&last); @@ -716,37 +1364,52 @@ static int eb_reserve(struct i915_execbuffer *eb) } list_splice_tail(&last, &eb->unbound); + if (signal_pending(current)) + return -EINTR; + if (err == -EAGAIN) { - mutex_unlock(&eb->i915->drm.struct_mutex); flush_workqueue(eb->i915->mm.userptr_wq); - mutex_lock(&eb->i915->drm.struct_mutex); continue; } - switch (pass++) { - case 0: - break; + /* Now safe to wait with no reservations held */ + list_for_each_entry(ev, &eb->unbound, bind_link) { + struct i915_vma *vma = ev->vma; - case 1: - /* Too fragmented, unbind everything and retry */ - mutex_lock(&eb->context->vm->mutex); - err = i915_gem_evict_vm(eb->context->vm); - mutex_unlock(&eb->context->vm->mutex); + GEM_BUG_ON(ev->flags & __EXEC_OBJECT_HAS_PIN); + + if (drm_mm_node_allocated(&vma->node) && + eb_vma_misplaced(ev->exec, vma, ev->flags)) { + err = i915_vma_unbind(vma); + if (err) + return err; + } + + /* Wait for previous to avoid reusing vma->node */ + err = i915_vma_wait_for_unbind(vma); if (err) - goto unlock; - break; + return err; + } + switch (pass++) { default: - err = -ENOSPC; - goto unlock; - } + return -ENOSPC; - pin_flags = PIN_USER; - } while (1); + case 2: + if (intel_gt_wait_for_idle(vm->gt, + MAX_SCHEDULE_TIMEOUT)) + return -EINTR; -unlock: - mutex_unlock(&eb->i915->drm.struct_mutex); - return err; + fallthrough; + case 1: + if (i915_active_wait(&vm->active)) + return -EINTR; + + fallthrough; + case 0: + break; + } + } while (1); } static unsigned int eb_batch_index(const struct i915_execbuffer *eb) @@ -1393,6 +2056,8 @@ eb_reloc_valid(struct i915_execbuffer *eb, if (unlikely(!target)) return -ENOENT; + GEM_BUG_ON(!i915_vma_is_pinned(target->vma)); + /* Validate that the target is in a valid r/w GPU domain */ if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { drm_dbg(&i915->drm, "reloc with multiple write domains: " @@ -1787,7 +2452,6 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) err = i915_vma_move_to_active(vma, eb->request, flags); i915_vma_unlock(vma); - eb_unreserve_vma(ev); } ww_acquire_fini(&acquire); @@ -2719,7 +3383,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure * batch" bit. Hence we need to pin secure batches into the global gtt. * hsw should have this fixed, but bdw mucks it up again. */ - batch = eb.batch->vma; + batch = i915_vma_get(eb.batch->vma); if (eb.batch_flags & I915_DISPATCH_SECURE) { struct i915_vma *vma; @@ -2739,6 +3403,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_parse; } + GEM_BUG_ON(vma->obj != batch->obj); batch = vma; } @@ -2814,6 +3479,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, err_parse: if (batch->private) intel_gt_buffer_pool_put(batch->private); + i915_vma_put(batch); err_vma: if (eb.reloc_cache.fence) eb_reloc_signal(&eb, eb.reloc_cache.rq); diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index f4fec7eb4064..2c5ac598ade2 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -370,6 +370,7 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt *ppgtt, int size) atomic_set(&vma->flags, I915_VMA_GGTT); vma->ggtt_view.type = I915_GGTT_VIEW_ROTATED; /* prevent fencing */ + INIT_LIST_HEAD(&vma->vm_link); INIT_LIST_HEAD(&vma->obj_link); INIT_LIST_HEAD(&vma->closed_link); diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 323c328d444a..eaacf369d304 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -582,7 +582,8 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, if (flags & I915_VMA_LOCAL_BIND) { struct i915_ppgtt *alias = i915_vm_to_ggtt(vma->vm)->alias; - if (flags & I915_VMA_ALLOC) { + if (flags & I915_VMA_ALLOC && + !test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { ret = alias->vm.allocate_va_range(&alias->vm, vma->node.start, vma->size); diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 2a72cce63fd9..82d4f943c346 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -194,6 +194,8 @@ void __i915_vm_close(struct i915_address_space *vm) void i915_address_space_fini(struct i915_address_space *vm) { + i915_active_fini(&vm->active); + spin_lock(&vm->free_pages.lock); if (pagevec_count(&vm->free_pages.pvec)) vm_free_pages_release(vm, true); @@ -246,6 +248,8 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) drm_mm_init(&vm->mm, 0, vm->total); vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; + i915_active_init(&vm->active, NULL, NULL); + stash_init(&vm->free_pages); INIT_LIST_HEAD(&vm->bound_list); diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index d93ebdf3fa0e..773fc76dfa1b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -263,6 +263,8 @@ struct i915_address_space { */ struct list_head bound_list; + struct i915_active active; + struct pagestash free_pages; /* Global GTT */ diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index f86f7e68ce5e..ecdd58f4b993 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -162,7 +162,8 @@ static int ppgtt_bind_vma(struct i915_vma *vma, u32 pte_flags; int err; - if (flags & I915_VMA_ALLOC) { + if (flags & I915_VMA_ALLOC && + !test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { err = vma->vm->allocate_va_range(vma->vm, vma->node.start, vma->size); if (err) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0cbcb9f54e7d..6effa85532c6 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -984,6 +984,9 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return vma; if (i915_vma_misplaced(vma, size, alignment, flags)) { + if (flags & PIN_NOEVICT) + return ERR_PTR(-ENOSPC); + if (flags & PIN_NONBLOCK) { if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) return ERR_PTR(-ENOSPC); @@ -998,6 +1001,10 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return ERR_PTR(ret); } + if (flags & PIN_NONBLOCK && + i915_active_fence_isset(&vma->active.excl)) + return ERR_PTR(-EAGAIN); + ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index cb43381b0d37..7e1225874b03 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -219,6 +219,8 @@ int i915_gem_gtt_insert(struct i915_address_space *vm, mode = DRM_MM_INSERT_HIGHEST; if (flags & PIN_MAPPABLE) mode = DRM_MM_INSERT_LOW; + if (flags & PIN_NOSEARCH) + mode |= DRM_MM_INSERT_ONCE; /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, * so we know that we always have a minimum alignment of 4096. @@ -236,6 +238,9 @@ int i915_gem_gtt_insert(struct i915_address_space *vm, if (err != -ENOSPC) return err; + if (flags & PIN_NOSEARCH) + return -ENOSPC; + if (mode & DRM_MM_INSERT_ONCE) { err = drm_mm_insert_node_in_range(&vm->mm, node, size, alignment, color, diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 9b30ddc49e4b..c071669e352a 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -132,6 +132,7 @@ vma_create(struct drm_i915_gem_object *obj, fs_reclaim_release(GFP_KERNEL); } + INIT_LIST_HEAD(&vma->vm_link); INIT_LIST_HEAD(&vma->closed_link); if (view && view->type != I915_GGTT_VIEW_NORMAL) { @@ -342,25 +343,37 @@ struct i915_vma_work *i915_vma_work(void) return vw; } -int i915_vma_wait_for_bind(struct i915_vma *vma) +static int +__i915_vma_wait_excl(struct i915_vma *vma, bool bound, unsigned int flags) { + struct dma_fence *fence; int err = 0; - if (rcu_access_pointer(vma->active.excl.fence)) { - struct dma_fence *fence; + fence = i915_active_fence_get(&vma->active.excl); + if (!fence) + return 0; - rcu_read_lock(); - fence = dma_fence_get_rcu_safe(&vma->active.excl.fence); - rcu_read_unlock(); - if (fence) { - err = dma_fence_wait(fence, MAX_SCHEDULE_TIMEOUT); - dma_fence_put(fence); - } + if (drm_mm_node_allocated(&vma->node) == bound) { + if (flags & PIN_NOEVICT) + err = -EBUSY; + else + err = dma_fence_wait(fence, true); } + dma_fence_put(fence); return err; } +int i915_vma_wait_for_bind(struct i915_vma *vma) +{ + return __i915_vma_wait_excl(vma, true, 0); +} + +int i915_vma_wait_for_unbind(struct i915_vma *vma) +{ + return __i915_vma_wait_excl(vma, false, 0); +} + /** * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. * @vma: VMA to map @@ -628,8 +641,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) u64 start, end; int ret; - GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); + GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_BIND_MASK)); GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); + GEM_BUG_ON(i915_active_fence_isset(&vma->active.excl)); size = max(size, vma->size); alignment = max(alignment, vma->display_alignment); @@ -725,7 +739,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, color)); - list_add_tail(&vma->vm_link, &vma->vm->bound_list); + list_move_tail(&vma->vm_link, &vma->vm->bound_list); return 0; } @@ -733,15 +747,12 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) static void i915_vma_detach(struct i915_vma *vma) { - GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); - GEM_BUG_ON(i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); - /* * And finally now the object is completely decoupled from this * vma, we can drop its hold on the backing storage and allow * it to be reaped by the shrinker. */ - list_del(&vma->vm_link); + list_del_init(&vma->vm_link); } static bool try_qad_pin(struct i915_vma *vma, unsigned int flags) @@ -787,7 +798,7 @@ static bool try_qad_pin(struct i915_vma *vma, unsigned int flags) return pinned; } -static int vma_get_pages(struct i915_vma *vma) +int i915_vma_get_pages(struct i915_vma *vma) { int err = 0; @@ -834,7 +845,7 @@ static void __vma_put_pages(struct i915_vma *vma, unsigned int count) mutex_unlock(&vma->pages_mutex); } -static void vma_put_pages(struct i915_vma *vma) +void i915_vma_put_pages(struct i915_vma *vma) { if (atomic_add_unless(&vma->pages_count, -1, 1)) return; @@ -851,9 +862,13 @@ static void vma_unbind_pages(struct i915_vma *vma) /* The upper portion of pages_count is the number of bindings */ count = atomic_read(&vma->pages_count); count >>= I915_VMA_PAGES_BIAS; - GEM_BUG_ON(!count); + if (count) + __vma_put_pages(vma, count | count << I915_VMA_PAGES_BIAS); +} - __vma_put_pages(vma, count | count << I915_VMA_PAGES_BIAS); +static int __wait_for_unbind(struct i915_vma *vma, unsigned int flags) +{ + return __i915_vma_wait_excl(vma, false, flags); } int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) @@ -872,10 +887,14 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (try_qad_pin(vma, flags & I915_VMA_BIND_MASK)) return 0; - err = vma_get_pages(vma); + err = i915_vma_get_pages(vma); if (err) return err; + err = __wait_for_unbind(vma, flags); + if (err) + goto err_pages; + if (flags & vma->vm->bind_async_flags) { work = i915_vma_work(); if (!work) { @@ -937,6 +956,10 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) goto err_unlock; if (!(bound & I915_VMA_BIND_MASK)) { + err = __wait_for_unbind(vma, flags); + if (err) + goto err_active; + err = i915_vma_insert(vma, size, alignment, flags); if (err) goto err_active; @@ -956,6 +979,7 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) GEM_BUG_ON(bound + I915_VMA_PAGES_ACTIVE < bound); atomic_add(I915_VMA_PAGES_ACTIVE, &vma->pages_count); list_move_tail(&vma->vm_link, &vma->vm->bound_list); + GEM_BUG_ON(!i915_vma_is_active(vma)); __i915_vma_pin(vma); GEM_BUG_ON(!i915_vma_is_pinned(vma)); @@ -977,7 +1001,7 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (wakeref) intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); err_pages: - vma_put_pages(vma); + i915_vma_put_pages(vma); return err; } @@ -1081,6 +1105,7 @@ void i915_vma_release(struct kref *ref) GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); } GEM_BUG_ON(i915_vma_is_active(vma)); + GEM_BUG_ON(!list_empty(&vma->vm_link)); if (vma->obj) { struct drm_i915_gem_object *obj = vma->obj; @@ -1139,7 +1164,7 @@ static void __i915_vma_iounmap(struct i915_vma *vma) { GEM_BUG_ON(i915_vma_is_pinned(vma)); - if (vma->iomap == NULL) + if (!vma->iomap) return; io_mapping_unmap(vma->iomap); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index d0d01f909548..478e8679f331 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -240,6 +240,9 @@ int __must_check i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags); int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags); +int i915_vma_get_pages(struct i915_vma *vma); +void i915_vma_put_pages(struct i915_vma *vma); + static inline int i915_vma_pin_count(const struct i915_vma *vma) { return atomic_read(&vma->flags) & I915_VMA_PIN_MASK; @@ -377,6 +380,7 @@ void i915_vma_make_shrinkable(struct i915_vma *vma); void i915_vma_make_purgeable(struct i915_vma *vma); int i915_vma_wait_for_bind(struct i915_vma *vma); +int i915_vma_wait_for_unbind(struct i915_vma *vma); static inline int i915_vma_sync(struct i915_vma *vma) { -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:29 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:29 +0100 Subject: [Intel-gfx] [PATCH 19/36] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-19-chris@chris-wilson.co.uk> Over the next couple of patches, we will want to lock all the modified vma for relocation processing under a single ww_mutex. We neither want to have to include the vma that are skipped (due to no modifications required) nor do we want those to be marked as written too. So separate out the reloc validation into an early step, which we can use both to reject the execbuf before committing to making our changes, and to filter out the unmodified vma. This does introduce a second pass through the reloc[], but only if we need to emit relocations. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 178 +++++++++++++----- 1 file changed, 133 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 540188454b6d..bed7c7ea2723 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1331,6 +1331,117 @@ static u64 eb_relocate_entry(struct i915_execbuffer *eb, struct eb_vma *ev, const struct drm_i915_gem_relocation_entry *reloc) +{ + struct eb_vma *target; + + /* we've already hold a reference to all valid objects */ + target = eb_get_vma(eb, reloc->target_handle); + if (unlikely(!target)) + return -ENOENT; + + /* + * If the relocation already has the right value in it, no + * more work needs to be done. + */ + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) + return 0; + + /* + * If we write into the object, we need to force the synchronisation + * barrier, either with an asynchronous clflush or if we executed the + * patching using the GPU (though that should be serialised by the + * timeline). To be completely sure, and since we are required to + * do relocations we are already stalling, disable the user's opt + * out of our synchronisation. + */ + ev->flags &= ~EXEC_OBJECT_ASYNC; + + /* and update the user's relocation entry */ + return relocate_entry(eb, ev->vma, reloc, target->vma); +} + +static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +{ +#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) + struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; + const struct drm_i915_gem_exec_object2 *entry = ev->exec; + struct drm_i915_gem_relocation_entry __user *urelocs = + u64_to_user_ptr(entry->relocs_ptr); + unsigned long remain = entry->relocation_count; + + if (unlikely(remain > N_RELOC(ULONG_MAX))) + return -EINVAL; + + /* + * We must check that the entire relocation array is safe + * to read. However, if the array is not writable the user loses + * the updated relocation values. + */ + if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs)))) + return -EFAULT; + + do { + struct drm_i915_gem_relocation_entry *r = stack; + unsigned int count = + min_t(unsigned long, remain, ARRAY_SIZE(stack)); + unsigned int copied; + + /* + * This is the fast path and we cannot handle a pagefault + * whilst holding the struct mutex lest the user pass in the + * relocations contained within a mmaped bo. For in such a case + * we, the page fault handler would call i915_gem_fault() and + * we would try to acquire the struct mutex again. Obviously + * this is bad and so lockdep complains vehemently. + */ + copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); + if (unlikely(copied)) + return -EFAULT; + + remain -= count; + do { + u64 offset = eb_relocate_entry(eb, ev, r); + + if (likely(offset == 0)) { + } else if ((s64)offset < 0) { + return (int)offset; + } else { + /* + * Note that reporting an error now + * leaves everything in an inconsistent + * state as we have *already* changed + * the relocation value inside the + * object. As we have not changed the + * reloc.presumed_offset or will not + * change the execobject.offset, on the + * call we may not rewrite the value + * inside the object, leaving it + * dangling and causing a GPU hang. Unless + * userspace dynamically rebuilds the + * relocations on each execbuf rather than + * presume a static tree. + * + * We did previously check if the relocations + * were writable (access_ok), an error now + * would be a strange race with mprotect, + * having already demonstrated that we + * can read from this userspace address. + */ + offset = gen8_canonical_addr(offset & ~UPDATE); + __put_user(offset, + &urelocs[r - stack].presumed_offset); + } + } while (r++, --count); + urelocs += ARRAY_SIZE(stack); + } while (remain); + + return 0; +} + +static int +eb_reloc_valid(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc) { struct drm_i915_private *i915 = eb->i915; struct eb_vma *target; @@ -1408,21 +1519,10 @@ eb_relocate_entry(struct i915_execbuffer *eb, return -EINVAL; } - /* - * If we write into the object, we need to force the synchronisation - * barrier, either with an asynchronous clflush or if we executed the - * patching using the GPU (though that should be serialised by the - * timeline). To be completely sure, and since we are required to - * do relocations we are already stalling, disable the user's opt - * out of our synchronisation. - */ - ev->flags &= ~EXEC_OBJECT_ASYNC; - - /* and update the user's relocation entry */ - return relocate_entry(eb, ev->vma, reloc, target->vma); + return 1; } -static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) { #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; @@ -1430,6 +1530,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) struct drm_i915_gem_relocation_entry __user *urelocs = u64_to_user_ptr(entry->relocs_ptr); unsigned long remain = entry->relocation_count; + long required = 0; if (unlikely(remain > N_RELOC(ULONG_MAX))) return -EINVAL; @@ -1462,42 +1563,18 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) remain -= count; do { - u64 offset = eb_relocate_entry(eb, ev, r); + int ret; - if (likely(offset == 0)) { - } else if ((s64)offset < 0) { - return (int)offset; - } else { - /* - * Note that reporting an error now - * leaves everything in an inconsistent - * state as we have *already* changed - * the relocation value inside the - * object. As we have not changed the - * reloc.presumed_offset or will not - * change the execobject.offset, on the - * call we may not rewrite the value - * inside the object, leaving it - * dangling and causing a GPU hang. Unless - * userspace dynamically rebuilds the - * relocations on each execbuf rather than - * presume a static tree. - * - * We did previously check if the relocations - * were writable (access_ok), an error now - * would be a strange race with mprotect, - * having already demonstrated that we - * can read from this userspace address. - */ - offset = gen8_canonical_addr(offset & ~UPDATE); - __put_user(offset, - &urelocs[r - stack].presumed_offset); - } + ret = eb_reloc_valid(eb, ev, r); + if (ret < 0) + return ret; + + required += ret; } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); - return 0; + return required; } static int eb_relocate(struct i915_execbuffer *eb) @@ -1516,9 +1593,20 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { - struct eb_vma *ev; + struct eb_vma *ev, *en; int flush; + list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { + long count; + + count = eb_reloc_vma_validate(eb, ev); + if (count < 0) + return count; + + if (count == 0) + list_del_init(&ev->reloc_link); + } + list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:26 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:26 +0100 Subject: [Intel-gfx] [PATCH 16/36] drm/i915/gem: Mark the buffer pool as active for the cmdparser In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-16-chris@chris-wilson.co.uk> If the execbuf is interrupted after building the cmdparser pipeline, and before we commit to submitting the request to HW, we would attempt to clean up the cmdparser early. While we held active references to the vma being parsed and constructed, we did not hold an active reference for the buffer pool itself. The result was that an interrupted execbuf could still have run the cmdparser pipeline, but since the buffer pool was idle, its target vma could have been recycled. Note this problem only occurs if the cmdparser is running async due to pipelined waits on busy fences, and the execbuf is interrupted. Fixes: 686c7c35abc2 ("drm/i915/gem: Asynchronous cmdparser") Fixes: 16e87459673a ("drm/i915/gt: Move the batch buffer pool from the engine to the gt") Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 56 ++++++++++++++++--- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 219a36995b96..0829ac8a55bf 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1987,6 +1987,38 @@ static const struct dma_fence_work_ops eb_parse_ops = { .release = __eb_parse_release, }; +static inline int +__parser_mark_active(struct i915_vma *vma, + struct intel_timeline *tl, + struct dma_fence *fence) +{ + struct intel_gt_buffer_pool_node *node = vma->private; + + return i915_active_ref(&node->active, tl, fence); +} + +static int +parser_mark_active(struct eb_parse_work *pw, struct intel_timeline *tl) +{ + int err; + + mutex_lock(&tl->mutex); + + err = __parser_mark_active(pw->shadow, tl, &pw->base.dma); + if (err) + goto unlock; + + if (pw->trampoline) { + err = __parser_mark_active(pw->trampoline, tl, &pw->base.dma); + if (err) + goto unlock; + } + +unlock: + mutex_unlock(&tl->mutex); + return err; +} + static int eb_parse_pipeline(struct i915_execbuffer *eb, struct i915_vma *shadow, struct i915_vma *trampoline) @@ -2021,20 +2053,25 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, pw->shadow = shadow; pw->trampoline = trampoline; + /* Mark active refs for this worker, in case we get interrupted */ + err = parser_mark_active(pw, eb->context->timeline); + if (err) + goto err_commit; + err = dma_resv_lock_interruptible(pw->batch->resv, NULL); if (err) - goto err_trampoline; + goto err_commit; err = dma_resv_reserve_shared(pw->batch->resv, 1); if (err) - goto err_batch_unlock; + goto err_commit_unlock; /* Wait for all writes (and relocs) into the batch to complete */ err = i915_sw_fence_await_reservation(&pw->base.chain, pw->batch->resv, NULL, false, 0, I915_FENCE_GFP); if (err < 0) - goto err_batch_unlock; + goto err_commit_unlock; /* Keep the batch alive and unwritten as we parse */ dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma); @@ -2049,11 +2086,13 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, dma_fence_work_commit_imm(&pw->base); return 0; -err_batch_unlock: +err_commit_unlock: dma_resv_unlock(pw->batch->resv); -err_trampoline: - if (trampoline) - i915_active_release(&trampoline->active); +err_commit: + i915_sw_fence_set_error_once(&pw->base.chain, err); + dma_fence_work_commit_imm(&pw->base); + return err; + err_shadow: i915_active_release(&shadow->active); err_batch: @@ -2099,6 +2138,7 @@ static int eb_parse(struct i915_execbuffer *eb) goto err; } i915_gem_object_set_readonly(shadow->obj); + shadow->private = pool; trampoline = NULL; if (CMDPARSER_USES_GGTT(eb->i915)) { @@ -2112,6 +2152,7 @@ static int eb_parse(struct i915_execbuffer *eb) shadow = trampoline; goto err_shadow; } + shadow->private = pool; eb->batch_flags |= I915_DISPATCH_SECURE; } @@ -2128,7 +2169,6 @@ static int eb_parse(struct i915_execbuffer *eb) eb->trampoline = trampoline; eb->batch_start_offset = 0; - shadow->private = pool; return 0; err_trampoline: -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:15 +0100 Subject: [Intel-gfx] [PATCH 05/36] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-5-chris@chris-wilson.co.uk> This was removed in commit 478ffad6d690 ("drm/i915: drop engine_pin/unpin_breadcrumbs_irq") as the last user had been removed, but now there is a promise of a new user in the next patch. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c index d907d538176e..03c14ab86d95 100644 --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c @@ -220,6 +220,28 @@ static void signal_irq_work(struct irq_work *work) } } +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine) +{ + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + spin_lock_irq(&b->irq_lock); + if (!b->irq_enabled++) + irq_enable(engine); + GEM_BUG_ON(!b->irq_enabled); /* no overflow! */ + spin_unlock_irq(&b->irq_lock); +} + +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine) +{ + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + spin_lock_irq(&b->irq_lock); + GEM_BUG_ON(!b->irq_enabled); /* no underflow! */ + if (!--b->irq_enabled) + irq_disable(engine); + spin_unlock_irq(&b->irq_lock); +} + static bool __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b) { struct intel_engine_cs *engine = diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..043462b6ce1f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -226,6 +226,9 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine); void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine); +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine); + void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); static inline void -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:18 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:18 +0100 Subject: [Intel-gfx] [PATCH 08/36] drm/i915/gt: Use client timeline address for seqno writes In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-8-chris@chris-wilson.co.uk> If we allow for per-client timelines, even with legacy ring submission, we open the door to a world full of possiblities [scheduling and semaphores]. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c index ce38d1bcaba3..fa11174bb13b 100644 --- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c @@ -373,11 +373,10 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) { - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); + u32 addr = i915_request_active_timeline(rq)->hwsp_offset; - *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW; + *cs++ = addr | MI_FLUSH_DW_USE_GTT; *cs++ = rq->fence.seqno; *cs++ = MI_USER_INTERRUPT; @@ -391,19 +390,17 @@ u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) #define GEN7_XCS_WA 32 u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) { + u32 addr = i915_request_active_timeline(rq)->hwsp_offset; int i; - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | - MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW; + *cs++ = addr | MI_FLUSH_DW_USE_GTT; *cs++ = rq->fence.seqno; for (i = 0; i < GEN7_XCS_WA; i++) { - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = 0; + *cs++ = addr; *cs++ = rq->fence.seqno; } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:20 +0100 Subject: [Intel-gfx] [PATCH 10/36] drm/i915/gt: Infrastructure for ring scheduling In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-10-chris@chris-wilson.co.uk> Build a bare bones scheduler to sit on top the global legacy ringbuffer submission. This virtual execlists scheme should be applicable to all older platforms. A key problem we have with the legacy ring buffer submission is that it only allows for FIFO queuing. All clients share the global request queue and must contend for its lock when submitting. As any client may need to wait for external events, all clients must then wait. However, if we stage each client into their own virtual ringbuffer with their own timelines, we can copy the client requests into the global ringbuffer only when they are ready, reordering the submission around stalls. Furthermore, the ability to reorder gives us rudimentarily priority sorting -- although without preemption support, once something is on the GPU it stays on the GPU, and so it is still possible for a hog to delay a high priority request (such as updating the display). However, it does means that in keeping a short submission queue, the high priority request will be next. This design resembles the old guc submission scheduler, for reordering requests onto a global workqueue. The implementation uses the MI_USER_INTERRUPT at the end of every request to track completion, so is more interrupt happy than execlists [which has an interrupt for each context event, albeit two]. Our interrupts on these system are relatively heavy, and in the past we have been able to completely starve Sandybrige by the interrupt traffic. Our interrupt handlers are being much better (in part offloading the work to bottom halves leaving the interrupt itself only dealing with acking the registers) but we can still see the impact of starvation in the uneven submission latency on a saturated system. Overall though, the short sumission queues and extra interrupts do not appear to be affecting throughput (+-10%, some tasks even improve to the reduced request overheads) and improve latency. [Which is a massive improvement since the introduction of Sandybridge!] Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_engine.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + .../gpu/drm/i915/gt/intel_ring_scheduler.c | 760 ++++++++++++++++++ .../gpu/drm/i915/gt/intel_ring_submission.c | 13 +- .../gpu/drm/i915/gt/intel_ring_submission.h | 16 + 6 files changed, 786 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_ring_scheduler.c create mode 100644 drivers/gpu/drm/i915/gt/intel_ring_submission.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 41a27fd5dbc7..6d98a74da41e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -109,6 +109,7 @@ gt-y += \ gt/intel_renderstate.o \ gt/intel_reset.o \ gt/intel_ring.o \ + gt/intel_ring_scheduler.o \ gt/intel_ring_submission.o \ gt/intel_rps.o \ gt/intel_sseu.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 043462b6ce1f..08176117757e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -209,6 +209,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine); int intel_engine_resume(struct intel_engine_cs *engine); int intel_ring_submission_setup(struct intel_engine_cs *engine); +int intel_ring_scheduler_setup(struct intel_engine_cs *engine); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 2b6cdf47d428..3782e27c2945 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -348,6 +348,7 @@ struct intel_engine_cs { struct { struct intel_ring *ring; struct intel_timeline *timeline; + struct intel_context *context; } legacy; /* diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c new file mode 100644 index 000000000000..c8cd435d1c51 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -0,0 +1,760 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +#include + +#include + +#include "i915_drv.h" +#include "intel_context.h" +#include "intel_gt.h" +#include "intel_gt_pm.h" +#include "intel_gt_requests.h" +#include "intel_reset.h" +#include "intel_ring.h" +#include "intel_ring_submission.h" +#include "shmem_utils.h" + +/* + * Rough estimate of the typical request size, performing a flush, + * set-context and then emitting the batch. + */ +#define LEGACY_REQUEST_SIZE 200 + +static inline int rq_prio(const struct i915_request *rq) +{ + return rq->sched.attr.priority; +} + +static inline struct i915_priolist *to_priolist(struct rb_node *rb) +{ + return rb_entry(rb, struct i915_priolist, node); +} + +static inline int queue_prio(struct rb_node *rb) +{ + return rb ? to_priolist(rb)->priority : INT_MIN; +} + +static inline bool reset_in_progress(const struct intel_engine_execlists *el) +{ + return unlikely(!__tasklet_is_enabled(&el->tasklet)); +} + +static void +set_current_context(struct intel_context **ptr, struct intel_context *ce) +{ + if (ce) + intel_context_get(ce); + + ce = xchg(ptr, ce); + + if (ce) + intel_context_put(ce); +} + +static struct i915_request * +schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) +{ + __intel_gt_pm_get(engine->gt); + return i915_request_get(rq); +} + +static void +schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) +{ + struct intel_context *ce = rq->context; + + if (list_is_last_rcu(&rq->link, &ce->timeline->requests)) + intel_engine_add_retire(engine, ce->timeline); + + i915_request_put(rq); + intel_gt_pm_put_async(engine->gt); +} + +static void reset_prepare(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + unsigned long flags; + + GEM_TRACE("%s\n", engine->name); + + __tasklet_disable_sync_once(&el->tasklet); + GEM_BUG_ON(!reset_in_progress(el)); + + /* And flush any current direct submission. */ + spin_lock_irqsave(&engine->active.lock, flags); + spin_unlock_irqrestore(&engine->active.lock, flags); + + intel_ring_submission_reset_prepare(engine); +} + +static void reset_queue_priority(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + el->queue_priority_hint = queue_prio(rb_first_cached(&el->queue)); +} + +static struct i915_request * +__unwind_incomplete_requests(struct intel_engine_cs *engine) +{ + struct i915_request *rq, *rn, *active = NULL; + struct list_head *uninitialized_var(pl); + int prio = I915_PRIORITY_INVALID; + + lockdep_assert_held(&engine->active.lock); + + list_for_each_entry_safe_reverse(rq, rn, + &engine->active.requests, + sched.link) { + if (i915_request_completed(rq)) + break; + + __i915_request_unsubmit(rq); + + GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); + if (rq_prio(rq) != prio) { + prio = rq_prio(rq); + pl = i915_sched_lookup_priolist(engine, prio); + } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); + + list_move(&rq->sched.link, pl); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + + active = rq; + } + + reset_queue_priority(engine); + + return active; +} + +static inline void clear_ports(struct i915_request **ports, int count) +{ + memset_p((void **)ports, NULL, count); +} + +static void cancel_port_requests(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request * const *port; + + clear_ports(el->pending, ARRAY_SIZE(el->pending)); + for (port = xchg(&el->active, el->pending); *port; port++) + schedule_out(engine, *port); + clear_ports(el->inflight, ARRAY_SIZE(el->inflight)); + + smp_wmb(); /* complete the seqlock for execlists_active() */ + WRITE_ONCE(el->active, el->inflight); +} + +static void __ring_rewind(struct intel_engine_cs *engine, bool stalled) +{ + struct i915_request *rq; + + rq = __unwind_incomplete_requests(engine); + if (rq && i915_request_started(rq)) + __i915_request_reset(rq, stalled); + + cancel_port_requests(engine); + + /* Clear the global submission state, we will submit from scratch */ + intel_ring_reset(engine->legacy.ring, 0); + set_current_context(&engine->legacy.context, NULL); +} + +static void ring_reset_rewind(struct intel_engine_cs *engine, bool stalled) +{ + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + __ring_rewind(engine, stalled); + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void nop_submission_tasklet(unsigned long data) +{ + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + + /* The driver is wedged; don't process any more events. */ + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN); +} + +static void ring_reset_cancel(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request *rq, *rn; + unsigned long flags; + struct rb_node *rb; + + spin_lock_irqsave(&engine->active.lock, flags); + + __ring_rewind(engine, true); + + /* Mark all submitted requests as skipped. */ + list_for_each_entry(rq, &engine->active.requests, sched.link) { + i915_request_set_error_once(rq, -EIO); + i915_request_mark_complete(rq); + } + + /* Flush the queued requests to the timeline list (for retiring). */ + while ((rb = rb_first_cached(&el->queue))) { + struct i915_priolist *p = to_priolist(rb); + int i; + + priolist_for_each_request_consume(rq, rn, p, i) { + i915_request_set_error_once(rq, -EIO); + i915_request_mark_complete(rq); + __i915_request_submit(rq); + } + + rb_erase_cached(&p->node, &el->queue); + i915_priolist_free(p); + } + + el->queue_priority_hint = INT_MIN; + el->queue = RB_ROOT_CACHED; + + /* Remaining _unready_ requests will be nop'ed when submitted */ + + GEM_BUG_ON(__tasklet_is_enabled(&el->tasklet)); + el->tasklet.func = nop_submission_tasklet; + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void reset_finish(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + intel_ring_submission_reset_finish(engine); + + if (__tasklet_enable(&el->tasklet)) + tasklet_hi_schedule(&el->tasklet); +} + +static u32 *ring_map(struct intel_ring *ring, u32 len) +{ + u32 *va; + + if (unlikely(ring->tail + len > ring->effective_size)) { + memset(ring->vaddr + ring->tail, 0, ring->size - ring->tail); + ring->tail = 0; + } + + va = ring->vaddr + ring->tail; + ring->tail = intel_ring_wrap(ring, ring->tail + len); + + return va; +} + +static inline u32 *ring_map_dw(struct intel_ring *ring, u32 len) +{ + return ring_map(ring, len * sizeof(u32)); +} + +static void ring_copy(struct intel_ring *dst, + const struct intel_ring *src, + u32 start, u32 end) +{ + unsigned int len; + void *out; + + len = end - start; + if (end < start) + len += src->size; + out = ring_map(dst, len); + + if (end < start) { + len = src->size - start; + memcpy(out, src->vaddr + start, len); + out += len; + start = 0; + } + + memcpy(out, src->vaddr + start, end - start); +} + +static void switch_context(struct intel_ring *ring, struct i915_request *rq) +{ +} + +static struct i915_request *ring_submit(struct i915_request *rq) +{ + struct intel_ring *ring = rq->engine->legacy.ring; + + __i915_request_submit(rq); + + if (rq->engine->legacy.context != rq->context) { + switch_context(ring, rq); + set_current_context(&rq->engine->legacy.context, rq->context); + } + + ring_copy(ring, rq->ring, rq->head, rq->tail); + return rq; +} + +static struct i915_request ** +copy_active(struct i915_request **port, struct i915_request * const *active) +{ + while (*active) + *port++ = *active++; + + return port; +} + +static void __dequeue(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request ** const last_port = el->pending + el->port_mask; + struct i915_request **port, *last; + struct rb_node *rb; + + lockdep_assert_held(&engine->active.lock); + + port = copy_active(el->pending, el->active); + if (port > last_port) + return; + + last = NULL; + while ((rb = rb_first_cached(&el->queue))) { + struct i915_priolist *p = to_priolist(rb); + struct i915_request *rq, *rn; + int i; + + priolist_for_each_request_consume(rq, rn, p, i) { + GEM_BUG_ON(rq == last); + if (last && rq->context != last->context) { + if (port == last_port) + goto done; + + *port++ = schedule_in(engine, last); + } + + last = ring_submit(rq); + } + + rb_erase_cached(&p->node, &el->queue); + i915_priolist_free(p); + } + +done: + el->queue_priority_hint = queue_prio(rb); + if (last) { + *port++ = schedule_in(engine, last); + *port++ = NULL; + WRITE_ONCE(el->active, el->pending); + + wmb(); /* paranoid flush of WCB before RING_TAIL write */ + ENGINE_WRITE(engine, RING_TAIL, engine->legacy.ring->tail); + memcpy(el->inflight, el->pending, + (port - el->pending) * sizeof(*port)); + + WRITE_ONCE(el->active, el->inflight); + GEM_BUG_ON(!*el->active); + } +} + +static void __submission_tasklet(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request *rq; + + while ((rq = *el->active)) { + if (!i915_request_completed(rq)) + break; + + schedule_out(engine, rq); + el->active++; + } + + if (el->queue_priority_hint != INT_MIN) + __dequeue(engine); +} + +static void submission_tasklet(unsigned long data) +{ + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + __submission_tasklet(engine); + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void queue_request(struct intel_engine_cs *engine, + struct i915_request *rq) +{ + GEM_BUG_ON(!list_empty(&rq->sched.link)); + list_add_tail(&rq->sched.link, + i915_sched_lookup_priolist(engine, rq_prio(rq))); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); +} + +static void __submit_queue_imm(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + if (reset_in_progress(el)) + return; /* defer until we restart the engine following reset */ + + __submission_tasklet(engine); +} + +static void submit_queue(struct intel_engine_cs *engine, + const struct i915_request *rq) +{ + struct intel_engine_execlists *el = &engine->execlists; + + if (rq_prio(rq) <= el->queue_priority_hint) + return; + + el->queue_priority_hint = rq_prio(rq); + __submit_queue_imm(engine); +} + +static void submit_request(struct i915_request *rq) +{ + struct intel_engine_cs *engine = rq->engine; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + + queue_request(engine, rq); + + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); + GEM_BUG_ON(list_empty(&rq->sched.link)); + + submit_queue(engine, rq); + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void submission_park(struct intel_engine_cs *engine) +{ + GEM_BUG_ON(engine->execlists.queue_priority_hint != INT_MIN); + intel_engine_unpin_breadcrumbs_irq(engine); + submission_tasklet((unsigned long)engine); /* drain the submit queue */ +} + +static void submission_unpark(struct intel_engine_cs *engine) +{ + intel_engine_pin_breadcrumbs_irq(engine); +} + +static void ring_context_destroy(struct kref *ref) +{ + struct intel_context *ce = container_of(ref, typeof(*ce), ref); + + GEM_BUG_ON(intel_context_is_pinned(ce)); + + if (ce->state) + i915_vma_put(ce->state); + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) + intel_ring_put(ce->ring); + + intel_context_fini(ce); + intel_context_free(ce); +} + +static void ring_context_unpin(struct intel_context *ce) +{ +} + +static int alloc_context_vma(struct intel_context *ce) + +{ + struct intel_engine_cs *engine = ce->engine; + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int err; + + obj = i915_gem_object_create_shmem(engine->i915, engine->context_size); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + /* + * Try to make the context utilize L3 as well as LLC. + * + * On VLV we don't have L3 controls in the PTEs so we + * shouldn't touch the cache level, especially as that + * would make the object snooped which might have a + * negative performance impact. + * + * Snooping is required on non-llc platforms in execlist + * mode, but since all GGTT accesses use PAT entry 0 we + * get snooping anyway regardless of cache_level. + * + * This is only applicable for Ivy Bridge devices since + * later platforms don't have L3 control bits in the PTE. + */ + if (IS_IVYBRIDGE(engine->i915)) + i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); + + if (engine->default_state) { + void *vaddr; + + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); + if (IS_ERR(vaddr)) { + err = PTR_ERR(vaddr); + goto err_obj; + } + + shmem_read(engine->default_state, 0, + vaddr, engine->context_size); + __set_bit(CONTEXT_VALID_BIT, &ce->flags); + + i915_gem_object_flush_map(obj); + i915_gem_object_unpin_map(obj); + } + + vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto err_obj; + } + + ce->state = vma; + return 0; + +err_obj: + i915_gem_object_put(obj); + return err; +} + +static int alloc_timeline(struct intel_context *ce) +{ + struct intel_engine_cs *engine = ce->engine; + struct intel_timeline *tl; + struct i915_vma *hwsp; + + /* + * Use the static global HWSP for the kernel context, and + * a dynamically allocated cacheline for everyone else. + */ + hwsp = NULL; + if (unlikely(intel_context_is_barrier(ce))) + hwsp = engine->status_page.vma; + + tl = intel_timeline_create(engine->gt, hwsp); + if (IS_ERR(tl)) + return PTR_ERR(tl); + + ce->timeline = tl; + return 0; +} + +static int ring_context_alloc(struct intel_context *ce) +{ + struct intel_engine_cs *engine = ce->engine; + struct intel_ring *ring; + int err; + + GEM_BUG_ON(ce->state); + if (engine->context_size) { + err = alloc_context_vma(ce); + if (err) + return err; + } + + if (!ce->timeline) { + err = alloc_timeline(ce); + if (err) + goto err_vma; + } + + ring = intel_engine_create_ring(engine, + (unsigned long)ce->ring | + INTEL_RING_CREATE_INTERNAL); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto err_timeline; + } + ce->ring = ring; + + return 0; + +err_timeline: + intel_timeline_put(ce->timeline); +err_vma: + if (ce->state) { + i915_vma_put(ce->state); + ce->state = NULL; + } + return err; +} + +static int ring_context_pin(struct intel_context *ce) +{ + return 0; +} + +static void ring_context_reset(struct intel_context *ce) +{ + intel_ring_reset(ce->ring, 0); + clear_bit(CONTEXT_VALID_BIT, &ce->flags); +} + +static const struct intel_context_ops ring_context_ops = { + .alloc = ring_context_alloc, + + .pin = ring_context_pin, + .unpin = ring_context_unpin, + + .enter = intel_context_enter_engine, + .exit = intel_context_exit_engine, + + .reset = ring_context_reset, + .destroy = ring_context_destroy, +}; + +static int ring_request_alloc(struct i915_request *rq) +{ + int ret; + + GEM_BUG_ON(!intel_context_is_pinned(rq->context)); + + /* + * Flush enough space to reduce the likelihood of waiting after + * we start building the request - in which case we will just + * have to repeat work. + */ + rq->reserved_space += LEGACY_REQUEST_SIZE; + + /* Unconditionally invalidate GPU caches and TLBs. */ + ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE); + if (ret) + return ret; + + rq->reserved_space -= LEGACY_REQUEST_SIZE; + return 0; +} + +static void set_default_submission(struct intel_engine_cs *engine) +{ + engine->submit_request = submit_request; + engine->execlists.tasklet.func = submission_tasklet; +} + +static void ring_release(struct intel_engine_cs *engine) +{ + intel_engine_cleanup_common(engine); + + set_current_context(&engine->legacy.context, NULL); + + intel_ring_unpin(engine->legacy.ring); + intel_ring_put(engine->legacy.ring); +} + +static void setup_irq(struct intel_engine_cs *engine) +{ +} + +static void setup_common(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; + + /* gen8+ are only supported with execlists */ + GEM_BUG_ON(INTEL_GEN(i915) >= 8); + GEM_BUG_ON(INTEL_GEN(i915) < 8); + + setup_irq(engine); + + engine->park = submission_park; + engine->unpark = submission_unpark; + engine->schedule = i915_schedule; + + engine->resume = intel_ring_submission_resume; + engine->reset.prepare = reset_prepare; + engine->reset.rewind = ring_reset_rewind; + engine->reset.cancel = ring_reset_cancel; + engine->reset.finish = reset_finish; + + engine->cops = &ring_context_ops; + engine->request_alloc = ring_request_alloc; + + engine->set_default_submission = set_default_submission; +} + +static void setup_rcs(struct intel_engine_cs *engine) +{ +} + +static void setup_vcs(struct intel_engine_cs *engine) +{ +} + +static void setup_bcs(struct intel_engine_cs *engine) +{ +} + +static void setup_vecs(struct intel_engine_cs *engine) +{ + GEM_BUG_ON(!IS_HASWELL(engine->i915)); +} + +static unsigned int global_ring_size(void) +{ + /* Enough space to hold 2 clients and the context switch */ + return roundup_pow_of_two(EXECLIST_MAX_PORTS * SZ_16K + SZ_4K); +} + +int intel_ring_scheduler_setup(struct intel_engine_cs *engine) +{ + struct intel_ring *ring; + int err; + + GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); + + tasklet_init(&engine->execlists.tasklet, + submission_tasklet, (unsigned long)engine); + + setup_common(engine); + + switch (engine->class) { + case RENDER_CLASS: + setup_rcs(engine); + break; + case VIDEO_DECODE_CLASS: + setup_vcs(engine); + break; + case COPY_ENGINE_CLASS: + setup_bcs(engine); + break; + case VIDEO_ENHANCEMENT_CLASS: + setup_vecs(engine); + break; + default: + MISSING_CASE(engine->class); + return -ENODEV; + } + + ring = intel_engine_create_ring(engine, global_ring_size()); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto err; + } + + err = intel_ring_pin(ring); + if (err) + goto err_ring; + + GEM_BUG_ON(engine->legacy.ring); + engine->legacy.ring = ring; + + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; + + /* Finally, take ownership and responsibility for cleanup! */ + engine->release = ring_release; + return 0; + +err_ring: + intel_ring_put(ring); +err: + intel_engine_cleanup_common(engine); + return err; +} diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index d9c1701061b9..bb1ed29cf753 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -36,6 +36,7 @@ #include "intel_gt.h" #include "intel_reset.h" #include "intel_ring.h" +#include "intel_ring_submission.h" #include "shmem_utils.h" /* Rough estimate of the typical request size, performing a flush, @@ -214,7 +215,7 @@ static void set_pp_dir(struct intel_engine_cs *engine) } } -static int xcs_resume(struct intel_engine_cs *engine) +int intel_ring_submission_resume(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; struct intel_ring *ring = engine->legacy.ring; @@ -318,7 +319,7 @@ static int xcs_resume(struct intel_engine_cs *engine) return ret; } -static void reset_prepare(struct intel_engine_cs *engine) +void intel_ring_submission_reset_prepare(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; const u32 base = engine->mmio_base; @@ -425,7 +426,7 @@ static void reset_rewind(struct intel_engine_cs *engine, bool stalled) spin_unlock_irqrestore(&engine->active.lock, flags); } -static void reset_finish(struct intel_engine_cs *engine) +void intel_ring_submission_reset_finish(struct intel_engine_cs *engine) { } @@ -1056,11 +1057,11 @@ static void setup_common(struct intel_engine_cs *engine) setup_irq(engine); - engine->resume = xcs_resume; - engine->reset.prepare = reset_prepare; + engine->resume = intel_ring_submission_resume; + engine->reset.prepare = intel_ring_submission_reset_prepare; engine->reset.rewind = reset_rewind; engine->reset.cancel = reset_cancel; - engine->reset.finish = reset_finish; + engine->reset.finish = intel_ring_submission_reset_finish; engine->cops = &ring_context_ops; engine->request_alloc = ring_request_alloc; diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.h b/drivers/gpu/drm/i915/gt/intel_ring_submission.h new file mode 100644 index 000000000000..701eb033e055 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_RING_SUBMISSION_H__ +#define __INTEL_RING_SUBMISSION_H__ + +struct intel_engine_cs; + +void intel_ring_submission_reset_prepare(struct intel_engine_cs *engine); +void intel_ring_submission_reset_finish(struct intel_engine_cs *engine); + +int intel_ring_submission_resume(struct intel_engine_cs *engine); + +#endif /* __INTEL_RING_SUBMISSION_H__ */ -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:31 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:31 +0100 Subject: [Intel-gfx] [PATCH 21/36] drm/i915/gem: Build the reloc request first In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-21-chris@chris-wilson.co.uk> If we get interrupted in the middle of chaining up the relocation entries, we will fail to submit the relocation batch. However, we will report having already completed some of the relocations, and so the reloc.presumed_offset will no longer match the batch contents, causing confusion and invalid future batches. If we build the relocation request packet first, we can always emit as far as we get up in the relocation chain. Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 51 ++++++++++--------- .../i915/gem/selftests/i915_gem_execbuffer.c | 8 +-- 2 files changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 9537fd87e3a4..c48950d7f1c9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1021,11 +1021,27 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) return cache->gen > 5 ? 0 : I915_DISPATCH_SECURE; } -static int reloc_gpu_flush(struct reloc_cache *cache) +static int reloc_gpu_emit(struct reloc_cache *cache) { struct i915_request *rq = cache->rq; int err; + err = 0; + if (rq->engine->emit_init_breadcrumb) + err = rq->engine->emit_init_breadcrumb(rq); + if (!err) + err = rq->engine->emit_bb_start(rq, + rq->batch->node.start, + PAGE_SIZE, + reloc_bb_flags(cache)); + + return err; +} + +static void reloc_gpu_flush(struct reloc_cache *cache) +{ + struct i915_request *rq = cache->rq; + if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1037,21 +1053,8 @@ static int reloc_gpu_flush(struct reloc_cache *cache) i915_gem_object_unpin_map(obj); } - err = 0; - if (rq->engine->emit_init_breadcrumb) - err = rq->engine->emit_init_breadcrumb(rq); - if (!err) - err = rq->engine->emit_bb_start(rq, - rq->batch->node.start, - PAGE_SIZE, - reloc_bb_flags(cache)); - if (err) - i915_request_set_error_once(rq, err); - intel_gt_chipset_flush(rq->engine->gt); i915_request_add(rq); - - return err; } static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) @@ -1139,7 +1142,7 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) err = i915_vma_move_to_active(batch, rq, 0); i915_vma_unlock(batch); if (err) - goto skip_request; + goto err_request; rq->batch = batch; i915_vma_unpin(batch); @@ -1152,8 +1155,6 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) /* Return with batch mapping (cmd) still pinned */ goto out_pool; -skip_request: - i915_request_set_error_once(rq, err); err_request: i915_request_add(rq); err_unpin: @@ -1186,10 +1187,8 @@ static u32 *reloc_batch_grow(struct i915_execbuffer *eb, if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); + if (unlikely(err)) return ERR_PTR(err); - } } GEM_BUG_ON(cache->rq_size + len >= PAGE_SIZE / sizeof(u32)); @@ -1571,23 +1570,25 @@ static int reloc_gpu_alloc(struct i915_execbuffer *eb) static int reloc_gpu(struct i915_execbuffer *eb) { struct eb_vma *ev; - int flush, err; + int err; err = reloc_gpu_alloc(eb); if (err) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto out; + list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) - goto out; + break; } out: - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; + reloc_gpu_flush(&eb->reloc_cache); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 50fe22d87ae1..faed6480a792 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -40,6 +40,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -64,9 +68,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); - err = reloc_gpu_flush(&eb->reloc_cache); - if (err) - goto put_rq; + reloc_gpu_flush(&eb->reloc_cache); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:35 +0100 Subject: [Intel-gfx] [PATCH 25/36] drm/i915/gem: Make relocations atomic within execbuf In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-25-chris@chris-wilson.co.uk> Although we may chide userspace for reusing the same batches concurrently from multiple threads, at the same time we must be very careful to only execute the batch and its relocations as supplied by the user. If we are not careful, we may allow another thread to rewrite the current batch with its own relocations. We must order the relocations and their batch such that they are an atomic pair on the GPU, and that the ioctl itself appears atomic to userspace. The order of execution may be undetermined, but it will not be subverted. We could do this by moving the relocations into the main request, if it were not for the situation where we need a second engine to perform the relocations for us. Instead, we use the dependency tracking to only publish the write fence on the main request and not on the relocation request, so that concurrent updates are queued after the batch has consumed its relocations. Testcase: igt/gem_exec_reloc/basic-concurrent Fixes: ef398881d27d ("drm/i915/gem: Limit struct_mutex to eb_reserve") Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 92 ++++++++++++++----- .../i915/gem/selftests/i915_gem_execbuffer.c | 11 ++- 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 37855ae8f8b3..2844274c37bb 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -259,6 +260,8 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; + struct dma_fence *fence; + struct i915_request *rq; struct i915_vma *rq_vma; u32 *rq_cmd; @@ -555,16 +558,6 @@ eb_add_vma(struct i915_execbuffer *eb, ev->exec = entry; ev->flags = entry->flags; - if (eb->lut_size > 0) { - ev->handle = entry->handle; - hlist_add_head(&ev->node, - &eb->buckets[hash_32(entry->handle, - eb->lut_size)]); - } - - if (entry->relocation_count) - list_add_tail(&ev->reloc_link, &eb->relocs); - /* * SNA is doing fancy tricks with compressing batch buffers, which leads * to negative relocation deltas. Usually that works out ok since the @@ -581,9 +574,21 @@ eb_add_vma(struct i915_execbuffer *eb, if (eb->reloc_cache.has_fence) ev->flags |= EXEC_OBJECT_NEEDS_FENCE; + INIT_LIST_HEAD(&ev->reloc_link); + eb->batch = ev; } + if (entry->relocation_count) + list_add_tail(&ev->reloc_link, &eb->relocs); + + if (eb->lut_size > 0) { + ev->handle = entry->handle; + hlist_add_head(&ev->node, + &eb->buckets[hash_32(entry->handle, + eb->lut_size)]); + } + if (eb_pin_vma(eb, entry, ev)) { if (entry->offset != vma->node.start) { entry->offset = vma->node.start | UPDATE; @@ -923,6 +928,7 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; + cache->fence = NULL; } static inline void *unmask_page(unsigned long p) @@ -1052,6 +1058,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache) } intel_gt_chipset_flush(rq->engine->gt); + i915_request_get(rq); i915_request_add(rq); } @@ -1284,16 +1291,6 @@ eb_relocate_entry(struct i915_execbuffer *eb, if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) return 0; - /* - * If we write into the object, we need to force the synchronisation - * barrier, either with an asynchronous clflush or if we executed the - * patching using the GPU (though that should be serialised by the - * timeline). To be completely sure, and since we are required to - * do relocations we are already stalling, disable the user's opt - * out of our synchronisation. - */ - ev->flags &= ~EXEC_OBJECT_ASYNC; - /* and update the user's relocation entry */ return relocate_entry(eb, ev->vma, reloc, target->vma); } @@ -1527,6 +1524,11 @@ static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) obj->write_domain = I915_GEM_DOMAIN_RENDER; obj->read_domains = I915_GEM_DOMAIN_RENDER; + ev->flags |= EXEC_OBJECT_ASYNC; + + err = dma_resv_reserve_shared(vma->resv, 1); + if (err) + return err; err = i915_request_await_object(rq, obj, true); if (err) @@ -1537,6 +1539,7 @@ static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) return err; dma_resv_add_excl_fence(vma->resv, &rq->fence); + dma_resv_add_shared_fence(vma->resv, cache->fence); return 0; } @@ -1605,14 +1608,28 @@ static int reloc_gpu_alloc(struct i915_execbuffer *eb) return __reloc_gpu_alloc(eb, engine); } +static void free_reloc_fence(struct i915_execbuffer *eb) +{ + struct dma_fence *f = fetch_and_zero(&eb->reloc_cache.fence); + + dma_fence_signal(f); + dma_fence_put(f); +} + static int reloc_gpu(struct i915_execbuffer *eb) { struct eb_vma *ev; int err; + eb->reloc_cache.fence = __dma_fence_create_proxy(0, 0); + if (!eb->reloc_cache.fence) + return -ENOMEM; + err = reloc_gpu_alloc(eb); - if (err) + if (err) { + free_reloc_fence(eb); return err; + } GEM_BUG_ON(!eb->reloc_cache.rq); err = lock_relocs(eb); @@ -1673,6 +1690,15 @@ static int eb_relocate(struct i915_execbuffer *eb) return 0; } +static void eb_reloc_signal(struct i915_execbuffer *eb, struct i915_request *rq) +{ + dma_fence_proxy_set_real(eb->reloc_cache.fence, &rq->fence); + i915_request_put(eb->reloc_cache.rq); + + dma_fence_put(eb->reloc_cache.fence); + eb->reloc_cache.fence = NULL; +} + static int eb_move_to_gpu(struct i915_execbuffer *eb) { const unsigned int count = eb->buffer_count; @@ -1953,10 +1979,15 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, if (err) goto err_commit_unlock; - /* Wait for all writes (and relocs) into the batch to complete */ - err = i915_sw_fence_await_reservation(&pw->base.chain, - pw->batch->resv, NULL, false, - 0, I915_FENCE_GFP); + /* Wait for all writes (or relocs) into the batch to complete */ + if (!eb->reloc_cache.fence || list_empty(&eb->batch->reloc_link)) + err = i915_sw_fence_await_reservation(&pw->base.chain, + pw->batch->resv, NULL, + false, 0, I915_FENCE_GFP); + else + err = i915_sw_fence_await_dma_fence(&pw->base.chain, + &eb->reloc_cache.rq->fence, + 0, I915_FENCE_GFP); if (err < 0) goto err_commit_unlock; @@ -2084,6 +2115,15 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) { int err; + if (eb->reloc_cache.fence) { + err = i915_request_await_dma_fence(eb->request, + &eb->reloc_cache.rq->fence); + if (err) + return err; + + eb_reloc_signal(eb, eb->request); + } + err = eb_move_to_gpu(eb); if (err) return err; @@ -2743,6 +2783,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (batch->private) intel_gt_buffer_pool_put(batch->private); err_vma: + if (eb.reloc_cache.fence) + eb_reloc_signal(&eb, eb.reloc_cache.rq); if (eb.trampoline) i915_vma_unpin(eb.trampoline); eb_unpin_engine(&eb); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 4f10b51f9a7e..62bba179b455 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -23,7 +23,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, const u64 mask = GENMASK_ULL(eb->reloc_cache.use_64bit_reloc ? 63 : 31, 0); const u32 *map = page_mask_bits(obj->mm.mapping); - struct i915_request *rq; struct eb_vma ev; int err; int i; @@ -40,6 +39,9 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + /* Single stage pipeline in the selftest */ + eb->reloc_cache.fence = &eb->reloc_cache.rq->fence; + list_add(&ev.reloc_link, &eb->relocs); err = lock_relocs(eb); if (err) @@ -71,8 +73,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; - GEM_BUG_ON(!eb->reloc_cache.rq); - rq = i915_request_get(eb->reloc_cache.rq); reloc_gpu_flush(&eb->reloc_cache); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); @@ -81,7 +81,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, goto put_rq; } - if (!i915_request_completed(rq)) { + if (!i915_request_completed(eb->reloc_cache.rq)) { pr_err("%s: did not wait for relocations!\n", eb->engine->name); err = -EINVAL; goto put_rq; @@ -100,7 +100,8 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, igt_hexdump(map, 4096); put_rq: - i915_request_put(rq); + i915_request_put(eb->reloc_cache.rq); + eb->reloc_cache.rq = NULL; unpin_vma: i915_vma_unpin(ev.vma); return err; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:14 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:14 +0100 Subject: [Intel-gfx] [PATCH 04/36] drm/i915: Trim the ironlake+ irq handler In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-4-chris@chris-wilson.co.uk> Ever noticed that our interrupt handlers are where we spend most of our time on a busy system? In part this is unavoidable as each interrupt requires to poll and reset several registers, but we can try and so as efficiently as possible. Function old new delta ilk_irq_handler 2317 2156 -161 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_irq.c | 59 ++++++++++++++++----------------- 1 file changed, 28 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 63579ab71cf6..07c0c7ea3795 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2097,69 +2097,66 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, */ static irqreturn_t ilk_irq_handler(int irq, void *arg) { - struct drm_i915_private *dev_priv = arg; + struct drm_i915_private *i915 = arg; + void __iomem * const regs = i915->uncore.regs; u32 de_iir, gt_iir, de_ier, sde_ier = 0; - irqreturn_t ret = IRQ_NONE; - if (!intel_irqs_enabled(dev_priv)) + if (!unlikely(intel_irqs_enabled(i915))) return IRQ_NONE; /* IRQs are synced during runtime_suspend, we don't require a wakeref */ - disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + disable_rpm_wakeref_asserts(&i915->runtime_pm); /* disable master interrupt before clearing iir */ - de_ier = I915_READ(DEIER); - I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); + de_ier = raw_reg_read(regs, DEIER); + raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); /* Disable south interrupts. We'll only write to SDEIIR once, so further * interrupts will will be stored on its back queue, and then we'll be * able to process them after we restore SDEIER (as soon as we restore * it, we'll get an interrupt if SDEIIR still has something to process * due to its back queue). */ - if (!HAS_PCH_NOP(dev_priv)) { - sde_ier = I915_READ(SDEIER); - I915_WRITE(SDEIER, 0); + if (!HAS_PCH_NOP(i915)) { + sde_ier = raw_reg_read(regs, SDEIER); + raw_reg_write(regs, SDEIER, 0); } /* Find, clear, then process each source of interrupt */ - gt_iir = I915_READ(GTIIR); + gt_iir = raw_reg_read(regs, GTIIR); if (gt_iir) { - I915_WRITE(GTIIR, gt_iir); - ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 6) - gen6_gt_irq_handler(&dev_priv->gt, gt_iir); + raw_reg_write(regs, GTIIR, gt_iir); + if (INTEL_GEN(i915) >= 6) + gen6_gt_irq_handler(&i915->gt, gt_iir); else - gen5_gt_irq_handler(&dev_priv->gt, gt_iir); + gen5_gt_irq_handler(&i915->gt, gt_iir); } - de_iir = I915_READ(DEIIR); + de_iir = raw_reg_read(regs, DEIIR); if (de_iir) { - I915_WRITE(DEIIR, de_iir); - ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 7) - ivb_display_irq_handler(dev_priv, de_iir); + raw_reg_write(regs, DEIIR, de_iir); + if (INTEL_GEN(i915) >= 7) + ivb_display_irq_handler(i915, de_iir); else - ilk_display_irq_handler(dev_priv, de_iir); + ilk_display_irq_handler(i915, de_iir); } - if (INTEL_GEN(dev_priv) >= 6) { - u32 pm_iir = I915_READ(GEN6_PMIIR); + if (INTEL_GEN(i915) >= 6) { + u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); if (pm_iir) { - I915_WRITE(GEN6_PMIIR, pm_iir); - ret = IRQ_HANDLED; - gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); + raw_reg_write(regs, GEN6_PMIIR, pm_iir); + gen6_rps_irq_handler(&i915->gt.rps, pm_iir); } } - I915_WRITE(DEIER, de_ier); - if (!HAS_PCH_NOP(dev_priv)) - I915_WRITE(SDEIER, sde_ier); + raw_reg_write(regs, DEIER, de_ier); + if (sde_ier) + raw_reg_write(regs, SDEIER, sde_ier); /* IRQs are synced during runtime_suspend, we don't require a wakeref */ - enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + enable_rpm_wakeref_asserts(&i915->runtime_pm); - return ret; + return IRQ_HANDLED; } static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:17 +0100 Subject: [Intel-gfx] [PATCH 07/36] drm/i915/gt: Support creation of 'internal' rings In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-7-chris@chris-wilson.co.uk> To support legacy ring buffer scheduling, we want a virtual ringbuffer for each client. These rings are purely for holding the requests as they are being constructed on the CPU and never accessed by the GPU, so they should not be bound into the GGTT, and we can use plain old WB mapped pages. As they are not bound, we need to nerf a few assumptions that a rq->ring is in the GGTT. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 ++---- drivers/gpu/drm/i915/gt/intel_ring.c | 63 ++++++++++++++-------- drivers/gpu/drm/i915/gt/intel_ring.h | 12 ++++- drivers/gpu/drm/i915/gt/intel_ring_types.h | 2 + 5 files changed, 57 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index e4aece20bc80..fd71977c010a 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -127,7 +127,7 @@ int __intel_context_do_pin(struct intel_context *ce) goto err_active; CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", - i915_ggtt_offset(ce->ring->vma), + intel_ring_address(ce->ring), ce->ring->head, ce->ring->tail); smp_mb__before_atomic(); /* flush pin before it is visible */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c8c14981eb5d..64e13c074708 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1261,7 +1261,7 @@ static int print_ring(char *buf, int sz, struct i915_request *rq) len = scnprintf(buf, sz, "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", - i915_ggtt_offset(rq->ring->vma), + intel_ring_address(rq->ring), tl ? tl->hwsp_offset : 0, hwsp_seqno(rq), DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), @@ -1542,7 +1542,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, print_request(m, rq, "\t\tactive "); drm_printf(m, "\t\tring->start: 0x%08x\n", - i915_ggtt_offset(rq->ring->vma)); + intel_ring_address(rq->ring)); drm_printf(m, "\t\tring->head: 0x%08x\n", rq->ring->head); drm_printf(m, "\t\tring->tail: 0x%08x\n", @@ -1621,13 +1621,6 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) return total; } -static bool match_ring(struct i915_request *rq) -{ - u32 ring = ENGINE_READ(rq->engine, RING_START); - - return ring == i915_ggtt_offset(rq->ring->vma); -} - struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine) { @@ -1667,11 +1660,7 @@ intel_engine_find_active_request(struct intel_engine_cs *engine) continue; if (!i915_request_started(request)) - continue; - - /* More than one preemptible request may match! */ - if (!match_ring(request)) - continue; + break; active = request; break; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 8cda1b7e17ba..438637996ab5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -24,33 +24,42 @@ unsigned int intel_ring_update_space(struct intel_ring *ring) int intel_ring_pin(struct intel_ring *ring) { struct i915_vma *vma = ring->vma; - unsigned int flags; void *addr; int ret; if (atomic_fetch_inc(&ring->pin_count)) return 0; - /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ - flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); + if (!(ring->flags & INTEL_RING_CREATE_INTERNAL)) { + unsigned int pin; - if (vma->obj->stolen) - flags |= PIN_MAPPABLE; - else - flags |= PIN_HIGH; + /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ + pin |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); - ret = i915_ggtt_pin(vma, 0, flags); - if (unlikely(ret)) - goto err_unpin; + if (vma->obj->stolen) + pin |= PIN_MAPPABLE; + else + pin |= PIN_HIGH; - if (i915_vma_is_map_and_fenceable(vma)) - addr = (void __force *)i915_vma_pin_iomap(vma); - else - addr = i915_gem_object_pin_map(vma->obj, - i915_coherent_map_type(vma->vm->i915)); - if (IS_ERR(addr)) { - ret = PTR_ERR(addr); - goto err_ring; + ret = i915_ggtt_pin(vma, 0, pin); + if (unlikely(ret)) + goto err_unpin; + + if (i915_vma_is_map_and_fenceable(vma)) + addr = (void __force *)i915_vma_pin_iomap(vma); + else + addr = i915_gem_object_pin_map(vma->obj, + i915_coherent_map_type(vma->vm->i915)); + if (IS_ERR(addr)) { + ret = PTR_ERR(addr); + goto err_ring; + } + } else { + addr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); + if (IS_ERR(addr)) { + ret = PTR_ERR(addr); + goto err_ring; + } } i915_vma_make_unshrinkable(vma); @@ -91,10 +100,12 @@ void intel_ring_unpin(struct intel_ring *ring) i915_gem_object_unpin_map(vma->obj); i915_vma_make_purgeable(vma); - i915_vma_unpin(vma); + if (!(ring->flags & INTEL_RING_CREATE_INTERNAL)) + i915_vma_unpin(vma); } -static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) +static struct i915_vma * +create_ring_vma(struct i915_ggtt *ggtt, int size, unsigned int flags) { struct i915_address_space *vm = &ggtt->vm; struct drm_i915_private *i915 = vm->i915; @@ -102,7 +113,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct i915_vma *vma; obj = ERR_PTR(-ENODEV); - if (i915_ggtt_has_aperture(ggtt)) + if (!(flags & INTEL_RING_CREATE_INTERNAL) && + i915_ggtt_has_aperture(ggtt)) obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); @@ -128,12 +140,14 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) } struct intel_ring * -intel_engine_create_ring(struct intel_engine_cs *engine, int size) +intel_engine_create_ring(struct intel_engine_cs *engine, unsigned int size) { struct drm_i915_private *i915 = engine->i915; + unsigned int flags = size & GENMASK(11, 0); struct intel_ring *ring; struct i915_vma *vma; + size ^= flags; GEM_BUG_ON(!is_power_of_2(size)); GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); @@ -142,8 +156,10 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size) return ERR_PTR(-ENOMEM); kref_init(&ring->ref); + ring->size = size; ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(size); + ring->flags = flags; /* * Workaround an erratum on the i830 which causes a hang if @@ -156,11 +172,12 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size) intel_ring_update_space(ring); - vma = create_ring_vma(engine->gt->ggtt, size); + vma = create_ring_vma(engine->gt->ggtt, size, flags); if (IS_ERR(vma)) { kfree(ring); return ERR_CAST(vma); } + ring->vma = vma; return ring; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h index cc0ebca65167..d022fa209325 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.h +++ b/drivers/gpu/drm/i915/gt/intel_ring.h @@ -9,12 +9,14 @@ #include "i915_gem.h" /* GEM_BUG_ON */ #include "i915_request.h" +#include "i915_vma.h" #include "intel_ring_types.h" struct intel_engine_cs; struct intel_ring * -intel_engine_create_ring(struct intel_engine_cs *engine, int size); +intel_engine_create_ring(struct intel_engine_cs *engine, unsigned int size); +#define INTEL_RING_CREATE_INTERNAL BIT(0) u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords); int intel_ring_cacheline_align(struct i915_request *rq); @@ -137,4 +139,12 @@ __intel_ring_space(unsigned int head, unsigned int tail, unsigned int size) return (head - tail - CACHELINE_BYTES) & (size - 1); } +static inline u32 intel_ring_address(const struct intel_ring *ring) +{ + if (ring->flags & INTEL_RING_CREATE_INTERNAL) + return -1; + + return i915_ggtt_offset(ring->vma); +} + #endif /* INTEL_RING_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_types.h b/drivers/gpu/drm/i915/gt/intel_ring_types.h index 1a189ea00fd8..d927deafcb33 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_types.h +++ b/drivers/gpu/drm/i915/gt/intel_ring_types.h @@ -47,6 +47,8 @@ struct intel_ring { u32 size; u32 wrap; u32 effective_size; + + unsigned long flags; }; #endif /* INTEL_RING_TYPES_H */ -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:24 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:24 +0100 Subject: [Intel-gfx] [PATCH 14/36] drm/i915/gt: Implement ring scheduler for gen6/7 In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-14-chris@chris-wilson.co.uk> A key prolem with legacy ring buffer submission is that it is an inheret FIFO queue across all clients; if one blocks, they all block. A scheduler allows us to avoid that limitation, and ensures that all clients can submit in parallel, removing the resource contention of the global ringbuffer. Having built the ring scheduler infrastructure over top of the global ringbuffer submission, we now need to provide the HW knowledge required to build command packets and implement context switching. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gt/intel_ring_scheduler.c | 417 +++++++++++++++++- 1 file changed, 415 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index 777cab6d9540..68efe63c0037 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -7,6 +7,10 @@ #include +#include "gen2_engine_cs.h" +#include "gen6_engine_cs.h" +#include "gen6_ppgtt.h" +#include "gen7_renderclear.h" #include "i915_drv.h" #include "intel_context.h" #include "intel_engine_stats.h" @@ -286,8 +290,261 @@ static void ring_copy(struct intel_ring *dst, memcpy(out, src->vaddr + start, end - start); } +static void mi_set_context(struct intel_ring *ring, + struct intel_engine_cs *engine, + struct intel_context *ce, + u32 flags) +{ + struct drm_i915_private *i915 = engine->i915; + enum intel_engine_id id; + const int num_engines = + IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; + int len; + u32 *cs; + + len = 4; + if (IS_GEN(i915, 7)) + len += 2 + (num_engines ? 4 * num_engines + 6 : 0); + else if (IS_GEN(i915, 5)) + len += 2; + + cs = ring_map_dw(ring, len); + + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ + if (IS_GEN(i915, 7)) { + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; + if (num_engines) { + struct intel_engine_cs *signaller; + + *cs++ = MI_LOAD_REGISTER_IMM(num_engines); + for_each_engine(signaller, engine->gt, id) { + if (signaller == engine) + continue; + + *cs++ = i915_mmio_reg_offset( + RING_PSMI_CTL(signaller->mmio_base)); + *cs++ = _MASKED_BIT_ENABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + } + } else if (IS_GEN(i915, 5)) { + /* + * This w/a is only listed for pre-production ilk a/b steppings, + * but is also mentioned for programming the powerctx. To be + * safe, just apply the workaround; we do not use SyncFlush so + * this should never take effect and so be a no-op! + */ + *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; + } + + *cs++ = MI_NOOP; + *cs++ = MI_SET_CONTEXT; + *cs++ = i915_ggtt_offset(ce->state) | flags; + /* + * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP + * WaMiSetContext_Hang:snb,ivb,vlv + */ + *cs++ = MI_NOOP; + + if (IS_GEN(i915, 7)) { + if (num_engines) { + struct intel_engine_cs *signaller; + i915_reg_t last_reg = {}; /* keep gcc quiet */ + + *cs++ = MI_LOAD_REGISTER_IMM(num_engines); + for_each_engine(signaller, engine->gt, id) { + if (signaller == engine) + continue; + + last_reg = RING_PSMI_CTL(signaller->mmio_base); + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = _MASKED_BIT_DISABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + + /* Insert a delay before the next switch! */ + *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + *cs++ = MI_NOOP; + } + *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; + } else if (IS_GEN(i915, 5)) { + *cs++ = MI_SUSPEND_FLUSH; + } +} + +static struct i915_address_space *vm_alias(struct i915_address_space *vm) +{ + if (i915_is_ggtt(vm)) + vm = &i915_vm_to_ggtt(vm)->alias->vm; + + return vm; +} + +static void load_pd_dir(struct intel_ring *ring, + struct intel_engine_cs *engine, + const struct i915_ppgtt *ppgtt) +{ + u32 *cs = ring_map_dw(ring, 12); + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); + *cs++ = PP_DIR_DCLV_2G; + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); + *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; + + /* Stall until the page table load is complete? */ + *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); + *cs++ = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); + *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE); +} + +static struct i915_address_space *current_vm(struct intel_engine_cs *engine) +{ + struct intel_context *old = engine->legacy.context; + + return old ? vm_alias(old->vm) : NULL; +} + +static void gen6_emit_invalidate_rcs(struct intel_ring *ring, + struct intel_engine_cs *engine) +{ + u32 addr, flags; + u32 *cs; + + addr = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); + + flags = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; + flags |= PIPE_CONTROL_TLB_INVALIDATE; + + if (INTEL_GEN(engine->i915) >= 7) + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + else + addr |= PIPE_CONTROL_GLOBAL_GTT; + + cs = ring_map_dw(ring, 4); + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = flags; + *cs++ = addr; + *cs++ = 0; +} + +static struct i915_address_space * +clear_residuals(struct intel_ring *ring, struct intel_engine_cs *engine) +{ + struct intel_context *ce = engine->kernel_context; + struct i915_address_space *vm = vm_alias(engine->gt->vm); + u32 flags; + + if (vm != current_vm(engine)) + load_pd_dir(ring, engine, i915_vm_to_ppgtt(vm)); + + if (ce->state) + mi_set_context(ring, engine, ce, + MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT); + + if (IS_HASWELL(engine->i915)) + flags = MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW; + else + flags = MI_BATCH_NON_SECURE_I965; + + __gen6_emit_bb_start(ring_map_dw(ring, 2), + engine->wa_ctx.vma->node.start, flags); + + return vm; +} + +static void remap_l3_slice(struct intel_ring *ring, + struct intel_engine_cs *engine, + int slice) +{ + u32 *cs, *remap_info = engine->i915->l3_parity.remap_info[slice]; + int i; + + if (!remap_info) + return; + + /* + * Note: We do not worry about the concurrent register cacheline hang + * here because no other code should access these registers other than + * at initialization time. + */ + cs = ring_map_dw(ring, GEN7_L3LOG_SIZE / 4 * 2 + 2); + *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE / 4); + for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { + *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); + *cs++ = remap_info[i]; + } + *cs++ = MI_NOOP; +} + +static void remap_l3(struct intel_ring *ring, + struct intel_engine_cs *engine, + struct intel_context *ce) +{ + struct i915_gem_context *ctx = + rcu_dereference_protected(ce->gem_context, true); + int bit, idx = -1; + + if (!ctx || !ctx->remap_slice) + return; + + do { + bit = ffs(ctx->remap_slice); + remap_l3_slice(ring, engine, idx += bit); + } while (ctx->remap_slice >>= bit); +} + static void switch_context(struct intel_ring *ring, struct i915_request *rq) { + struct intel_engine_cs *engine = rq->engine; + struct i915_address_space *cvm = current_vm(engine); + struct intel_context *ce = rq->context; + struct i915_address_space *vm; + + if (engine->wa_ctx.vma && ce != engine->kernel_context) { + if (engine->wa_ctx.vma->private != ce) { + cvm = clear_residuals(ring, engine); + intel_context_put(engine->wa_ctx.vma->private); + engine->wa_ctx.vma->private = intel_context_get(ce); + } + } + + vm = vm_alias(ce->vm); + if (vm != cvm) + load_pd_dir(ring, engine, i915_vm_to_ppgtt(vm)); + + if (ce->state) { + u32 flags; + + GEM_BUG_ON(engine->id != RCS0); + + /* For resource streamer on HSW+ and power context elsewhere */ + BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN); + BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN); + + flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT; + if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) { + gen6_emit_invalidate_rcs(ring, engine); + flags |= MI_RESTORE_EXT_STATE_EN; + } else { + flags |= MI_RESTORE_INHIBIT; + } + + mi_set_context(ring, engine, ce, flags); + } + + remap_l3(ring, engine, ce); } static struct i915_request *ring_submit(struct i915_request *rq) @@ -453,6 +710,33 @@ static void submission_unpark(struct intel_engine_cs *engine) intel_engine_pin_breadcrumbs_irq(engine); } +static int gen6_emit_init_breadcrumb(struct i915_request *rq) +{ + struct intel_timeline *tl = i915_request_timeline(rq); + u32 *cs; + + GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq)); + if (!tl->has_initial_breadcrumb) + return 0; + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = 0; + *cs++ = tl->hwsp_offset; + *cs++ = rq->fence.seqno - 1; + + intel_ring_advance(rq, cs); + + /* Record the updated position of the request's payload */ + rq->infix = intel_ring_offset(rq, cs); + + __set_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags); + return 0; +} + static void ring_context_destroy(struct kref *ref) { struct intel_context *ce = container_of(ref, typeof(*ce), ref); @@ -468,8 +752,30 @@ static void ring_context_destroy(struct kref *ref) intel_context_free(ce); } +static int __context_pin_ppgtt(struct intel_context *ce) +{ + struct i915_address_space *vm; + int err = 0; + + vm = vm_alias(ce->vm); + if (vm) + err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); + + return err; +} + +static void __context_unpin_ppgtt(struct intel_context *ce) +{ + struct i915_address_space *vm; + + vm = vm_alias(ce->vm); + if (vm) + gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); +} + static void ring_context_unpin(struct intel_context *ce) { + __context_unpin_ppgtt(ce); } static int alloc_context_vma(struct intel_context *ce) @@ -597,7 +903,7 @@ static int ring_context_alloc(struct intel_context *ce) static int ring_context_pin(struct intel_context *ce) { - return 0; + return __context_pin_ppgtt(ce); } static void ring_context_reset(struct intel_context *ce) @@ -653,12 +959,19 @@ static void ring_release(struct intel_engine_cs *engine) set_current_context(&engine->legacy.context, NULL); + if (engine->wa_ctx.vma) { + intel_context_put(engine->wa_ctx.vma->private); + i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); + } + intel_ring_unpin(engine->legacy.ring); intel_ring_put(engine->legacy.ring); } static void setup_irq(struct intel_engine_cs *engine) { + engine->irq_enable = gen6_irq_enable; + engine->irq_disable = gen6_irq_disable; } static void setup_common(struct intel_engine_cs *engine) @@ -667,7 +980,7 @@ static void setup_common(struct intel_engine_cs *engine) /* gen8+ are only supported with execlists */ GEM_BUG_ON(INTEL_GEN(i915) >= 8); - GEM_BUG_ON(INTEL_GEN(i915) < 8); + GEM_BUG_ON(INTEL_GEN(i915) < 6); setup_irq(engine); @@ -684,24 +997,62 @@ static void setup_common(struct intel_engine_cs *engine) engine->cops = &ring_context_ops; engine->request_alloc = ring_request_alloc; + engine->emit_init_breadcrumb = gen6_emit_init_breadcrumb; + if (INTEL_GEN(i915) >= 7) + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; + else if (INTEL_GEN(i915) >= 6) + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; + else + engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; + engine->set_default_submission = set_default_submission; + + engine->emit_bb_start = gen6_emit_bb_start; } static void setup_rcs(struct intel_engine_cs *engine) { + struct drm_i915_private *i915 = engine->i915; + + if (HAS_L3_DPF(i915)) + engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; + + engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; + + if (INTEL_GEN(i915) >= 7) { + engine->emit_flush = gen7_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; + if (IS_HASWELL(i915)) + engine->emit_bb_start = hsw_emit_bb_start; + } else { + engine->emit_flush = gen6_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; + } } static void setup_vcs(struct intel_engine_cs *engine) { + engine->emit_flush = gen6_emit_flush_vcs; + engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; + + if (IS_GEN(engine->i915, 6)) + engine->fw_domain = FORCEWAKE_ALL; } static void setup_bcs(struct intel_engine_cs *engine) { + engine->emit_flush = gen6_emit_flush_xcs; + engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; } static void setup_vecs(struct intel_engine_cs *engine) { GEM_BUG_ON(!IS_HASWELL(engine->i915)); + + engine->emit_flush = gen6_emit_flush_xcs; + engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; + engine->irq_enable = hsw_irq_enable_vecs; + engine->irq_disable = hsw_irq_disable_vecs; } static unsigned int global_ring_size(void) @@ -710,6 +1061,58 @@ static unsigned int global_ring_size(void) return roundup_pow_of_two(EXECLIST_MAX_PORTS * SZ_16K + SZ_4K); } +static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine) +{ + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int size; + int err; + + size = gen7_setup_clear_gpr_bb(engine, NULL /* probe size */); + if (size <= 0) + return size; + + size = ALIGN(size, PAGE_SIZE); + obj = i915_gem_object_create_internal(engine->i915, size); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + vma = i915_vma_instance(obj, engine->gt->vm, NULL); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto err_obj; + } + + vma->private = intel_context_create(engine); /* dummy residuals */ + if (IS_ERR(vma->private)) { + err = PTR_ERR(vma->private); + goto err_obj; + } + + err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + if (err) + goto err_private; + + err = i915_vma_sync(vma); + if (err) + goto err_unpin; + + size = gen7_setup_clear_gpr_bb(engine, vma); + if (err) + goto err_unpin; + + engine->wa_ctx.vma = vma; + return 0; + +err_unpin: + i915_vma_unpin(vma); +err_private: + intel_context_put(vma->private); +err_obj: + i915_gem_object_put(obj); + return err; +} + int intel_ring_scheduler_setup(struct intel_engine_cs *engine) { struct intel_ring *ring; @@ -753,13 +1156,23 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) GEM_BUG_ON(engine->legacy.ring); engine->legacy.ring = ring; + if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) { + err = gen7_ctx_switch_bb_init(engine); + if (err) + goto err_ring_unpin; + } + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; engine->flags |= I915_ENGINE_SUPPORTS_STATS; + if (INTEL_GEN(engine->i915) >= 6) + engine->flags |= I915_ENGINE_HAS_SEMAPHORES; /* Finally, take ownership and responsibility for cleanup! */ engine->release = ring_release; return 0; +err_ring_unpin: + intel_ring_unpin(ring); err_ring: intel_ring_put(ring); err: -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:28 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:28 +0100 Subject: [Intel-gfx] [PATCH 18/36] drm/i915: Add list_for_each_entry_safe_continue_reverse In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-18-chris@chris-wilson.co.uk> One more list iterator variant, for when we want to unwind from inside one list iterator with the intention of restarting from the current entry as the new head of the list. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_utils.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h index 03a73d2bd50d..6ebccdd12d4c 100644 --- a/drivers/gpu/drm/i915/i915_utils.h +++ b/drivers/gpu/drm/i915/i915_utils.h @@ -266,6 +266,12 @@ static inline int list_is_last_rcu(const struct list_head *list, return READ_ONCE(list->next) == head; } +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) + /* * Wait until the work is finally complete, even if it tries to postpone * by requeueing itself. Note, that if the worker never cancels itself, -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:11 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:11 +0100 Subject: [Intel-gfx] [PATCH 01/36] drm/i915: Handle very early engine initialisation failure Message-ID: <20200601072446.19548-1-chris@chris-wilson.co.uk> If we fail during engine setup, we may leave some engines not yet setup. During the error cleanup, we have to be careful not to try and use the uninitialise engines before discarding them. [ 16.136152] RIP: 0010:__flush_work+0x198/0x1b0 [ 16.136168] Code: ff ff 8b 0b 48 8b 53 08 83 e1 08 48 0f ba 2b 03 80 c9 f0 e9 63 ff ff ff 0f 0b 48 83 c4 48 44 89 f0 5b 5d 41 5c 41 5d 41 5e c3 <0f> 0b 45 31 f6 e9 62 ff ff ff 66 66 2e 0f 1f 84 00 00 00 00 00 0f [ 16.136186] RSP: 0018:ffffc900003bb928 EFLAGS: 00010246 [ 16.136201] RAX: 0000000000000000 RBX: ffff88844f392168 RCX: 0000000000000000 [ 16.136216] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff88844f392168 [ 16.136231] RBP: ffff88844f392130 R08: 0000000000000000 R09: 0000000000000001 [ 16.136246] R10: ffff888441e31e40 R11: ffff88845e329c70 R12: ffff88844f796988 [ 16.136261] R13: ffff888441e4fb80 R14: 0000000000000001 R15: ffff88844f790000 [ 16.136388] FS: 00007fecbd208880(0000) GS:ffff88845e380000(0000) knlGS:0000000000000000 [ 16.136405] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 16.136420] CR2: 00007ff3ce748f90 CR3: 0000000457a6a001 CR4: 00000000000606e0 [ 16.136437] Call Trace: [ 16.136456] ? try_to_del_timer_sync+0x3a/0x50 [ 16.136529] intel_wakeref_wait_for_idle+0x87/0xb0 [i915] [ 16.136606] ? intel_engines_release+0x68/0xc0 [i915] [ 16.136680] intel_engines_release+0x49/0xc0 [i915] [ 16.136757] intel_gt_init+0x2f4/0x5e0 [i915] Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index da5b61085257..c8c14981eb5d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -414,12 +414,12 @@ void intel_engines_release(struct intel_gt *gt) /* Decouple the backend; but keep the layout for late GPU resets */ for_each_engine(engine, gt, id) { - intel_wakeref_wait_for_idle(&engine->wakeref); - GEM_BUG_ON(intel_engine_pm_is_awake(engine)); - if (!engine->release) continue; + intel_wakeref_wait_for_idle(&engine->wakeref); + GEM_BUG_ON(intel_engine_pm_is_awake(engine)); + engine->release(engine); engine->release = NULL; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:21 +0100 Subject: [Intel-gfx] [PATCH 11/36] drm/i915/gt: Enable busy-stats for ring-scheduler In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-11-chris@chris-wilson.co.uk> Couple up the context in/out accounting to record how long each engine is busy handling requests. This is exposed to userspace for more accurate measurements, and also enables our soft-rps timer. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 +++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------- .../gpu/drm/i915/gt/intel_ring_scheduler.c | 4 + drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 86 +++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ 5 files changed, 145 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include +#include +#include + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6fc0966b75ff..13ef4f58cb08 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1187,39 +1188,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index c8cd435d1c51..aaff554865b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_context.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -59,6 +60,7 @@ static struct i915_request * schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) { __intel_gt_pm_get(engine->gt); + intel_engine_context_in(engine); return i915_request_get(rq); } @@ -71,6 +73,7 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) intel_engine_add_retire(engine, ce->timeline); i915_request_put(rq); + intel_engine_context_out(engine); intel_gt_pm_put_async(engine->gt); } @@ -747,6 +750,7 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) engine->legacy.ring = ring; engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; + engine->flags |= I915_ENGINE_SUPPORTS_STATS; /* Finally, take ownership and responsibility for cleanup! */ engine->release = ring_release; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..5e48c7571b4d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,91 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t dt, de; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + usleep_range(100, 200); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + if (de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + break; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + break; + } + + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + usleep_range(100, 200); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + if (100 * de < 95 * dt) { + pr_err("%s: reported only %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + igt_spinner_fini(&spin); + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +162,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:25 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:25 +0100 Subject: [Intel-gfx] [PATCH 15/36] drm/i915/gt: Enable ring scheduling for gen6/7 In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-15-chris@chris-wilson.co.uk> Switch over from FIFO global submission to the priority-sorted topographical scheduler. At the cost of more busy work on the CPU to keep the GPU supplied with the next packet of requests, this allows us to reorder requests around submission stalls. This also enables the timer based RPS, with the exception of Valleyview who's PCU doesn't take kindly to our interference. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/gt/intel_rps.c | 6 ++---- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index b81978890641..bb57687aea99 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -94,7 +94,7 @@ static int live_nop_switch(void *arg) rq = i915_request_get(this); i915_request_add(this); } - if (i915_request_wait(rq, 0, HZ / 5) < 0) { + if (i915_request_wait(rq, 0, HZ) < 0) { pr_err("Failed to populated %d contexts\n", nctx); intel_gt_set_wedged(&i915->gt); i915_request_put(rq); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 64e13c074708..c29727b3ba4a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -791,6 +791,8 @@ int intel_engines_init(struct intel_gt *gt) if (HAS_EXECLISTS(gt->i915)) setup = intel_execlists_submission_setup; + else if (INTEL_GEN(gt->i915) >= 6) + setup = intel_ring_scheduler_setup; else setup = intel_ring_submission_setup; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2e4ddc9ca09d..22882c2953da 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1053,9 +1053,7 @@ static bool gen6_rps_enable(struct intel_rps *rps) intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000); intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); - rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | - GEN6_PM_RP_DOWN_THRESHOLD | - GEN6_PM_RP_DOWN_TIMEOUT); + rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; return rps_reset(rps); } @@ -1362,7 +1360,7 @@ void intel_rps_enable(struct intel_rps *rps) GEM_BUG_ON(rps->efficient_freq < rps->min_freq); GEM_BUG_ON(rps->efficient_freq > rps->max_freq); - if (has_busy_stats(rps)) + if (has_busy_stats(rps) && !IS_VALLEYVIEW(i915)) intel_rps_set_timer(rps); else if (INTEL_GEN(i915) >= 6) intel_rps_set_interrupts(rps); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:19 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:19 +0100 Subject: [Intel-gfx] [PATCH 09/36] drm/i915: Support inter-engine semaphores on gen6/7 In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-9-chris@chris-wilson.co.uk> Should we gain per-client timelines, we can then utilise the separate HWSP in order to use MI_SEMAPHORE_MBOX with the unique GGTT addresses required for synchronising between clients across different engines. Teach the emit_semaphore_wait about MI_SEMAPHORE_MBOX for the older generations. Note that the engine must still indicate support for the semaphore synchronisation before the context is allowed to use them. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_request.c | 31 +++++++++++++++++++---------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index c5d7220de529..9537e30f9439 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1016,7 +1016,7 @@ __emit_semaphore_wait(struct i915_request *to, int len, err; u32 *cs; - GEM_BUG_ON(INTEL_GEN(to->i915) < 8); + GEM_BUG_ON(INTEL_GEN(to->i915) < 6); GEM_BUG_ON(i915_request_has_initial_breadcrumb(to)); /* We need to pin the signaler's HWSP until we are finished reading. */ @@ -1040,17 +1040,26 @@ __emit_semaphore_wait(struct i915_request *to, * (post-wrap) values than they were expecting (and so wait * forever). */ - *cs++ = (MI_SEMAPHORE_WAIT | - MI_SEMAPHORE_GLOBAL_GTT | - MI_SEMAPHORE_POLL | - MI_SEMAPHORE_SAD_GTE_SDD) + - has_token; - *cs++ = seqno; - *cs++ = hwsp_offset; - *cs++ = 0; - if (has_token) { + if (INTEL_GEN(to->i915) >= 8) { + *cs++ = (MI_SEMAPHORE_WAIT | + MI_SEMAPHORE_GLOBAL_GTT | + MI_SEMAPHORE_POLL | + MI_SEMAPHORE_SAD_GTE_SDD) + + has_token; + *cs++ = seqno; + *cs++ = hwsp_offset; + *cs++ = 0; + if (has_token) { + *cs++ = 0; + *cs++ = MI_NOOP; + } + } else { + *cs++ = (MI_SEMAPHORE_MBOX | + MI_SEMAPHORE_GLOBAL_GTT | + MI_SEMAPHORE_COMPARE); + *cs++ = seqno - 1; /* COMPARE is a strict greater-than */ + *cs++ = hwsp_offset; *cs++ = 0; - *cs++ = MI_NOOP; } intel_ring_advance(to, cs); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:43 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:43 +0100 Subject: [Intel-gfx] [PATCH 33/36] drm/i915: Export a preallocate variant of i915_active_acquire() In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-33-chris@chris-wilson.co.uk> Sometimes we have to be very careful not to allocate underneath a mutex (or spinlock) and yet still want to track activity. Enter i915_active_acquire_for_context(). This raises the activity counter on i915_active prior to use and ensures that the fence-tree contains a slot for the context. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_active.c | 107 ++++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_active.h | 5 ++ 2 files changed, 103 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c index d960d0be5bd2..71ad0d452680 100644 --- a/drivers/gpu/drm/i915/i915_active.c +++ b/drivers/gpu/drm/i915/i915_active.c @@ -217,11 +217,10 @@ excl_retire(struct dma_fence *fence, struct dma_fence_cb *cb) } static struct i915_active_fence * -active_instance(struct i915_active *ref, struct intel_timeline *tl) +active_instance(struct i915_active *ref, u64 idx) { struct active_node *node, *prealloc; struct rb_node **p, *parent; - u64 idx = tl->fence_context; /* * We track the most recently used timeline to skip a rbtree search @@ -367,7 +366,7 @@ int i915_active_ref(struct i915_active *ref, if (err) return err; - active = active_instance(ref, tl); + active = active_instance(ref, tl->fence_context); if (!active) { err = -ENOMEM; goto out; @@ -384,32 +383,104 @@ int i915_active_ref(struct i915_active *ref, atomic_dec(&ref->count); } if (!__i915_active_fence_set(active, fence)) - atomic_inc(&ref->count); + __i915_active_acquire(ref); out: i915_active_release(ref); return err; } -struct dma_fence * -i915_active_set_exclusive(struct i915_active *ref, struct dma_fence *f) +static struct dma_fence * +__i915_active_set_fence(struct i915_active *ref, + struct i915_active_fence *active, + struct dma_fence *fence) { struct dma_fence *prev; /* We expect the caller to manage the exclusive timeline ordering */ GEM_BUG_ON(i915_active_is_idle(ref)); + if (is_barrier(active)) { /* proto-node used by our idle barrier */ + /* + * This request is on the kernel_context timeline, and so + * we can use it to substitute for the pending idle-barrer + * request that we want to emit on the kernel_context. + */ + __active_del_barrier(ref, node_from_active(active)); + RCU_INIT_POINTER(active->fence, NULL); + atomic_dec(&ref->count); + } + rcu_read_lock(); - prev = __i915_active_fence_set(&ref->excl, f); + prev = __i915_active_fence_set(active, fence); if (prev) prev = dma_fence_get_rcu(prev); else - atomic_inc(&ref->count); + __i915_active_acquire(ref); rcu_read_unlock(); return prev; } +static struct i915_active_fence * +__active_lookup(struct i915_active *ref, u64 idx) +{ + struct active_node *node; + struct rb_node *p; + + /* Like active_instance() but with no malloc */ + + node = READ_ONCE(ref->cache); + if (node && node->timeline == idx) + return &node->base; + + spin_lock_irq(&ref->tree_lock); + GEM_BUG_ON(i915_active_is_idle(ref)); + + p = ref->tree.rb_node; + while (p) { + node = rb_entry(p, struct active_node, node); + if (node->timeline == idx) { + ref->cache = node; + spin_unlock_irq(&ref->tree_lock); + return &node->base; + } + + if (node->timeline < idx) + p = p->rb_right; + else + p = p->rb_left; + } + + spin_unlock_irq(&ref->tree_lock); + + return NULL; +} + +struct dma_fence * +__i915_active_ref(struct i915_active *ref, u64 idx, struct dma_fence *fence) +{ + struct dma_fence *prev = ERR_PTR(-ENOENT); + struct i915_active_fence *active; + + if (!i915_active_acquire_if_busy(ref)) + return ERR_PTR(-EINVAL); + + active = __active_lookup(ref, idx); + if (active) + prev = __i915_active_set_fence(ref, active, fence); + + i915_active_release(ref); + return prev; +} + +struct dma_fence * +i915_active_set_exclusive(struct i915_active *ref, struct dma_fence *f) +{ + /* We expect the caller to manage the exclusive timeline ordering */ + return __i915_active_set_fence(ref, &ref->excl, f); +} + bool i915_active_acquire_if_busy(struct i915_active *ref) { debug_active_assert(ref); @@ -443,6 +514,24 @@ int i915_active_acquire(struct i915_active *ref) return err; } +int i915_active_acquire_for_context(struct i915_active *ref, u64 idx) +{ + struct i915_active_fence *active; + int err; + + err = i915_active_acquire(ref); + if (err) + return err; + + active = active_instance(ref, idx); + if (!active) { + i915_active_release(ref); + return -ENOMEM; + } + + return 0; /* return with active ref */ +} + void i915_active_release(struct i915_active *ref) { debug_active_assert(ref); @@ -804,7 +893,7 @@ int i915_active_acquire_preallocate_barrier(struct i915_active *ref, */ RCU_INIT_POINTER(node->base.fence, ERR_PTR(-EAGAIN)); node->base.cb.node.prev = (void *)engine; - atomic_inc(&ref->count); + __i915_active_acquire(ref); } GEM_BUG_ON(rcu_access_pointer(node->base.fence) != ERR_PTR(-EAGAIN)); diff --git a/drivers/gpu/drm/i915/i915_active.h b/drivers/gpu/drm/i915/i915_active.h index cf4058150966..042502abefe5 100644 --- a/drivers/gpu/drm/i915/i915_active.h +++ b/drivers/gpu/drm/i915/i915_active.h @@ -163,6 +163,9 @@ void __i915_active_init(struct i915_active *ref, __i915_active_init(ref, active, retire, &__mkey, &__wkey); \ } while (0) +struct dma_fence * +__i915_active_ref(struct i915_active *ref, u64 idx, struct dma_fence *fence); + int i915_active_ref(struct i915_active *ref, struct intel_timeline *tl, struct dma_fence *fence); @@ -198,7 +201,9 @@ int i915_request_await_active(struct i915_request *rq, #define I915_ACTIVE_AWAIT_BARRIER BIT(2) int i915_active_acquire(struct i915_active *ref); +int i915_active_acquire_for_context(struct i915_active *ref, u64 idx); bool i915_active_acquire_if_busy(struct i915_active *ref); + void i915_active_release(struct i915_active *ref); static inline void __i915_active_acquire(struct i915_active *ref) -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:44 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:44 +0100 Subject: [Intel-gfx] [PATCH 34/36] drm/i915/gem: Separate the ww_mutex walker into its own list In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-34-chris@chris-wilson.co.uk> In preparation for making eb_vma bigger and heavy to run inn parallel, we need to stop apply an in-place swap() to reorder around ww_mutex deadlocks. Keep the array intact and reorder the locks using a dedicated list. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 52 ++++++++++++------- 1 file changed, 32 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index cb4872ccfe58..b400eed1f435 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -36,6 +36,7 @@ struct eb_vma { struct drm_i915_gem_exec_object2 *exec; struct list_head bind_link; struct list_head reloc_link; + struct list_head lock_link; struct hlist_node node; u32 handle; @@ -247,6 +248,8 @@ struct i915_execbuffer { /** list of vma that have execobj.relocation_count */ struct list_head relocs; + struct list_head lock; + /** * Track the most recently used object for relocations, as we * frequently have to perform multiple relocations within the same @@ -391,6 +394,10 @@ static int eb_create(struct i915_execbuffer *eb) eb->lut_size = -eb->buffer_count; } + INIT_LIST_HEAD(&eb->relocs); + INIT_LIST_HEAD(&eb->unbound); + INIT_LIST_HEAD(&eb->lock); + return 0; } @@ -598,6 +605,8 @@ eb_add_vma(struct i915_execbuffer *eb, eb_unreserve_vma(ev); list_add_tail(&ev->bind_link, &eb->unbound); } + + list_add_tail(&ev->lock_link, &eb->lock); } static int eb_reserve_vma(const struct i915_execbuffer *eb, @@ -857,9 +866,6 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) unsigned int i; int err = 0; - INIT_LIST_HEAD(&eb->relocs); - INIT_LIST_HEAD(&eb->unbound); - for (i = 0; i < eb->buffer_count; i++) { struct i915_vma *vma; @@ -1701,38 +1707,43 @@ static void eb_reloc_signal(struct i915_execbuffer *eb, struct i915_request *rq) static int eb_move_to_gpu(struct i915_execbuffer *eb) { - const unsigned int count = eb->buffer_count; struct ww_acquire_ctx acquire; - unsigned int i; + struct eb_vma *ev; int err = 0; ww_acquire_init(&acquire, &reservation_ww_class); - for (i = 0; i < count; i++) { - struct eb_vma *ev = &eb->vma[i]; + list_for_each_entry(ev, &eb->lock, lock_link) { struct i915_vma *vma = ev->vma; err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); if (err == -EDEADLK) { - GEM_BUG_ON(i == 0); - do { - int j = i - 1; - - ww_mutex_unlock(&eb->vma[j].vma->resv->lock); + struct eb_vma *unlock = ev, *en; - swap(eb->vma[i], eb->vma[j]); - } while (--i); + list_for_each_entry_safe_continue_reverse(unlock, en, + &eb->lock, + lock_link) { + ww_mutex_unlock(&unlock->vma->resv->lock); + list_move_tail(&unlock->lock_link, &eb->lock); + } + GEM_BUG_ON(!list_is_first(&ev->lock_link, &eb->lock)); err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, &acquire); } - if (err) - break; + if (err) { + list_for_each_entry_continue_reverse(ev, + &eb->lock, + lock_link) + ww_mutex_unlock(&ev->vma->resv->lock); + + ww_acquire_fini(&acquire); + goto err_skip; + } } ww_acquire_done(&acquire); - while (i--) { - struct eb_vma *ev = &eb->vma[i]; + list_for_each_entry(ev, &eb->lock, lock_link) { struct i915_vma *vma = ev->vma; unsigned int flags = ev->flags; struct drm_i915_gem_object *obj = vma->obj; @@ -2079,9 +2090,10 @@ static int eb_parse(struct i915_execbuffer *eb) if (err) goto err_trampoline; - eb->vma[eb->buffer_count].vma = i915_vma_get(shadow); - eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN; eb->batch = &eb->vma[eb->buffer_count++]; + eb->batch->vma = i915_vma_get(shadow); + eb->batch->flags = __EXEC_OBJECT_HAS_PIN; + list_add_tail(&eb->batch->lock_link, &eb->lock); eb->vma[eb->buffer_count].vma = NULL; eb->trampoline = trampoline; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:27 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:27 +0100 Subject: [Intel-gfx] [PATCH 17/36] drm/i915/gem: Async GPU relocations only In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-17-chris@chris-wilson.co.uk> Reduce the 3 relocation patches down to the single path that accommodates all. The primary motivation for this is to guard the relocations with a natural fence (derived from the i915_request used to write the relocation from the GPU). The tradeoff in using async gpu relocations is that it increases latency over using direct CPU relocations, for the cases where the target is idle and accessible by the CPU. The benefit is greatly reduced lock contention and improved concurrency by pipelining. Note that forcing the async gpu relocations does reveal a few issues they have. Firstly, is that they are visible as writes to gem_busy, causing to mark some buffers are being to written to by the GPU even though userspace only reads. Secondly is that, in combination with the cmdparser, they can cause priority inversions. This should be the case where the work is being put into a common workqueue losing our priority information and so being executed in FIFO from the worker, denying us the opportunity to reorder the requests afterwards. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 295 ++---------------- .../i915/gem/selftests/i915_gem_execbuffer.c | 21 +- 2 files changed, 27 insertions(+), 289 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 0829ac8a55bf..540188454b6d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -45,13 +45,6 @@ struct eb_vma_array { struct eb_vma vma[]; }; -enum { - FORCE_CPU_RELOC = 1, - FORCE_GTT_RELOC, - FORCE_GPU_RELOC, -#define DBG_FORCE_RELOC 0 /* choose one of the above! */ -}; - #define __EXEC_OBJECT_HAS_PIN BIT(31) #define __EXEC_OBJECT_HAS_FENCE BIT(30) #define __EXEC_OBJECT_NEEDS_MAP BIT(29) @@ -260,8 +253,6 @@ struct i915_execbuffer { */ struct reloc_cache { struct drm_mm_node node; /** temporary GTT binding */ - unsigned long vaddr; /** Current kmap address */ - unsigned long page; /** Currently mapped page index */ unsigned int gen; /** Cached value of INTEL_GEN */ bool use_64bit_reloc : 1; bool has_llc : 1; @@ -605,23 +596,6 @@ eb_add_vma(struct i915_execbuffer *eb, } } -static inline int use_cpu_reloc(const struct reloc_cache *cache, - const struct drm_i915_gem_object *obj) -{ - if (!i915_gem_object_has_struct_page(obj)) - return false; - - if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) - return true; - - if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) - return false; - - return (cache->has_llc || - obj->cache_dirty || - obj->cache_level != I915_CACHE_NONE); -} - static int eb_reserve_vma(const struct i915_execbuffer *eb, struct eb_vma *ev, u64 pin_flags) @@ -945,8 +919,6 @@ relocation_target(const struct drm_i915_gem_relocation_entry *reloc, static void reloc_cache_init(struct reloc_cache *cache, struct drm_i915_private *i915) { - cache->page = -1; - cache->vaddr = 0; /* Must be a variable in the struct to allow GCC to unroll. */ cache->gen = INTEL_GEN(i915); cache->has_llc = HAS_LLC(i915); @@ -1089,181 +1061,6 @@ static int reloc_gpu_flush(struct reloc_cache *cache) return err; } -static void reloc_cache_reset(struct reloc_cache *cache) -{ - void *vaddr; - - if (!cache->vaddr) - return; - - vaddr = unmask_page(cache->vaddr); - if (cache->vaddr & KMAP) { - if (cache->vaddr & CLFLUSH_AFTER) - mb(); - - kunmap_atomic(vaddr); - i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); - } else { - struct i915_ggtt *ggtt = cache_to_ggtt(cache); - - intel_gt_flush_ggtt_writes(ggtt->vm.gt); - io_mapping_unmap_atomic((void __iomem *)vaddr); - - if (drm_mm_node_allocated(&cache->node)) { - ggtt->vm.clear_range(&ggtt->vm, - cache->node.start, - cache->node.size); - mutex_lock(&ggtt->vm.mutex); - drm_mm_remove_node(&cache->node); - mutex_unlock(&ggtt->vm.mutex); - } else { - i915_vma_unpin((struct i915_vma *)cache->node.mm); - } - } - - cache->vaddr = 0; - cache->page = -1; -} - -static void *reloc_kmap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - void *vaddr; - - if (cache->vaddr) { - kunmap_atomic(unmask_page(cache->vaddr)); - } else { - unsigned int flushes; - int err; - - err = i915_gem_object_prepare_write(obj, &flushes); - if (err) - return ERR_PTR(err); - - BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); - BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); - - cache->vaddr = flushes | KMAP; - cache->node.mm = (void *)obj; - if (flushes) - mb(); - } - - vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); - cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; - cache->page = page; - - return vaddr; -} - -static void *reloc_iomap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - struct i915_ggtt *ggtt = cache_to_ggtt(cache); - unsigned long offset; - void *vaddr; - - if (cache->vaddr) { - intel_gt_flush_ggtt_writes(ggtt->vm.gt); - io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); - } else { - struct i915_vma *vma; - int err; - - if (i915_gem_object_is_tiled(obj)) - return ERR_PTR(-EINVAL); - - if (use_cpu_reloc(cache, obj)) - return NULL; - - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); - if (err) - return ERR_PTR(err); - - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, - PIN_MAPPABLE | - PIN_NONBLOCK /* NOWARN */ | - PIN_NOEVICT); - if (IS_ERR(vma)) { - memset(&cache->node, 0, sizeof(cache->node)); - mutex_lock(&ggtt->vm.mutex); - err = drm_mm_insert_node_in_range - (&ggtt->vm.mm, &cache->node, - PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, - 0, ggtt->mappable_end, - DRM_MM_INSERT_LOW); - mutex_unlock(&ggtt->vm.mutex); - if (err) /* no inactive aperture space, use cpu reloc */ - return NULL; - } else { - cache->node.start = vma->node.start; - cache->node.mm = (void *)vma; - } - } - - offset = cache->node.start; - if (drm_mm_node_allocated(&cache->node)) { - ggtt->vm.insert_page(&ggtt->vm, - i915_gem_object_get_dma_address(obj, page), - offset, I915_CACHE_NONE, 0); - } else { - offset += page << PAGE_SHIFT; - } - - vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, - offset); - cache->page = page; - cache->vaddr = (unsigned long)vaddr; - - return vaddr; -} - -static void *reloc_vaddr(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - void *vaddr; - - if (cache->page == page) { - vaddr = unmask_page(cache->vaddr); - } else { - vaddr = NULL; - if ((cache->vaddr & KMAP) == 0) - vaddr = reloc_iomap(obj, cache, page); - if (!vaddr) - vaddr = reloc_kmap(obj, cache, page); - } - - return vaddr; -} - -static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) -{ - if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { - if (flushes & CLFLUSH_BEFORE) { - clflushopt(addr); - mb(); - } - - *addr = value; - - /* - * Writes to the same cacheline are serialised by the CPU - * (including clflush). On the write path, we only require - * that it hits memory in an orderly fashion and place - * mb barriers at the start and end of the relocation phase - * to ensure ordering of clflush wrt to the system. - */ - if (flushes & CLFLUSH_AFTER) - clflushopt(addr); - } else - *addr = value; -} - static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) { struct drm_i915_gem_object *obj = vma->obj; @@ -1429,17 +1226,6 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, return cmd; } -static inline bool use_reloc_gpu(struct i915_vma *vma) -{ - if (DBG_FORCE_RELOC == FORCE_GPU_RELOC) - return true; - - if (DBG_FORCE_RELOC) - return false; - - return !dma_resv_test_signaled_rcu(vma->resv, true); -} - static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) { struct page *page; @@ -1454,10 +1240,10 @@ static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) return addr + offset_in_page(offset); } -static bool __reloc_entry_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - u64 offset, - u64 target_addr) +static int __reloc_entry_gpu(struct i915_execbuffer *eb, + struct i915_vma *vma, + u64 offset, + u64 target_addr) { const unsigned int gen = eb->reloc_cache.gen; unsigned int len; @@ -1473,7 +1259,7 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, batch = reloc_gpu(eb, vma, len); if (IS_ERR(batch)) - return false; + return PTR_ERR(batch); addr = gen8_canonical_addr(vma->node.start + offset); if (gen >= 8) { @@ -1522,55 +1308,21 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, *batch++ = target_addr; } - return true; -} - -static bool reloc_entry_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - u64 offset, - u64 target_addr) -{ - if (eb->reloc_cache.vaddr) - return false; - - if (!use_reloc_gpu(vma)) - return false; - - return __reloc_entry_gpu(eb, vma, offset, target_addr); + return 0; } static u64 -relocate_entry(struct i915_vma *vma, +relocate_entry(struct i915_execbuffer *eb, + struct i915_vma *vma, const struct drm_i915_gem_relocation_entry *reloc, - struct i915_execbuffer *eb, const struct i915_vma *target) { u64 target_addr = relocation_target(reloc, target); - u64 offset = reloc->offset; - - if (!reloc_entry_gpu(eb, vma, offset, target_addr)) { - bool wide = eb->reloc_cache.use_64bit_reloc; - void *vaddr; - -repeat: - vaddr = reloc_vaddr(vma->obj, - &eb->reloc_cache, - offset >> PAGE_SHIFT); - if (IS_ERR(vaddr)) - return PTR_ERR(vaddr); - - GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32))); - clflush_write32(vaddr + offset_in_page(offset), - lower_32_bits(target_addr), - eb->reloc_cache.vaddr); - - if (wide) { - offset += sizeof(u32); - target_addr >>= 32; - wide = false; - goto repeat; - } - } + int err; + + err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); + if (err) + return err; return target->node.start | UPDATE; } @@ -1635,8 +1387,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, * If the relocation already has the right value in it, no * more work needs to be done. */ - if (!DBG_FORCE_RELOC && - gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) return 0; /* Check that the relocation address is valid... */ @@ -1668,7 +1419,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, ev->flags &= ~EXEC_OBJECT_ASYNC; /* and update the user's relocation entry */ - return relocate_entry(ev->vma, reloc, eb, target->vma); + return relocate_entry(eb, ev->vma, reloc, target->vma); } static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) @@ -1706,10 +1457,8 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) * this is bad and so lockdep complains vehemently. */ copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); - if (unlikely(copied)) { - remain = -EFAULT; - goto out; - } + if (unlikely(copied)) + return -EFAULT; remain -= count; do { @@ -1717,8 +1466,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) if (likely(offset == 0)) { } else if ((s64)offset < 0) { - remain = (int)offset; - goto out; + return (int)offset; } else { /* * Note that reporting an error now @@ -1748,9 +1496,8 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); -out: - reloc_cache_reset(&eb->reloc_cache); - return remain; + + return 0; } static int eb_relocate(struct i915_execbuffer *eb) @@ -2658,7 +2405,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.i915 = i915; eb.file = file; eb.args = args; - if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) + if (!(args->flags & I915_EXEC_NO_RELOC)) args->flags |= __EXEC_HAS_RELOC; eb.exec = exec; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index a49016f8ee0d..57c14d3340cd 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -37,20 +37,14 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, return err; /* 8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[0] * sizeof(u32), - 0)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + if (err) goto unpin_vma; - } /* !8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[1] * sizeof(u32), - 1)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + if (err) goto unpin_vma; - } /* Skip to the end of the cmd page */ i = PAGE_SIZE / sizeof(u32) - RELOC_TAIL - 1; @@ -60,12 +54,9 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - if (!__reloc_entry_gpu(eb, vma, - offsets[2] * sizeof(u32), - 2)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + if (err) goto unpin_vma; - } GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:46 +0100 Subject: [Intel-gfx] [PATCH 36/36] drm/i915/gem: Bind the fence async for execbuf In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-36-chris@chris-wilson.co.uk> It is illegal to wait on an another vma while holding the vm->mutex, as that easily leads to ABBA deadlocks (we wait on a second vma that waits on us to release the vm->mutex). So while the vm->mutex exists, move the waiting outside of the lock into the async binding pipeline. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 41 ++++-- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 137 +++++++++++++++++- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h | 5 + 3 files changed, 166 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 49bfae968215..aa8d86d4466d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -511,13 +511,23 @@ eb_pin_vma(struct i915_execbuffer *eb, } if (unlikely(ev->flags & EXEC_OBJECT_NEEDS_FENCE)) { - if (unlikely(i915_vma_pin_fence(vma))) { - i915_vma_unpin(vma); - return false; - } + struct i915_fence_reg *reg = vma->fence; - if (vma->fence) + /* Avoid waiting to change the fence; defer to async worker */ + if (reg) { + if (READ_ONCE(reg->dirty)) { + __i915_vma_unpin(vma); + return false; + } + + atomic_inc(®->pin_count); ev->flags |= __EXEC_OBJECT_HAS_FENCE; + } else { + if (i915_gem_object_is_tiled(vma->obj)) { + __i915_vma_unpin(vma); + return false; + } + } } ev->flags |= __EXEC_OBJECT_HAS_PIN; @@ -1043,15 +1053,6 @@ static int eb_reserve_vma(struct eb_vm_work *work, struct eb_vma *ev) return err; pin: - if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { - err = __i915_vma_pin_fence(vma); /* XXX no waiting */ - if (unlikely(err)) - return err; - - if (vma->fence) - ev->flags |= __EXEC_OBJECT_HAS_FENCE; - } - bind_flags &= ~atomic_read(&vma->flags); if (bind_flags) { err = set_bind_fence(vma, work); @@ -1082,6 +1083,15 @@ static int eb_reserve_vma(struct eb_vm_work *work, struct eb_vma *ev) ev->flags |= __EXEC_OBJECT_HAS_PIN; GEM_BUG_ON(eb_vma_misplaced(entry, vma, ev->flags)); + if (unlikely(exec_flags & EXEC_OBJECT_NEEDS_FENCE)) { + err = __i915_vma_pin_fence_async(vma, &work->base); + if (unlikely(err)) + return err; + + if (vma->fence) + ev->flags |= __EXEC_OBJECT_HAS_FENCE; + } + return 0; } @@ -1117,6 +1127,9 @@ static int __eb_bind_vma(struct eb_vm_work *work, int err) list_for_each_entry(ev, &work->unbound, bind_link) { struct i915_vma *vma = ev->vma; + if (ev->flags & __EXEC_OBJECT_HAS_FENCE) + __i915_vma_apply_fence_async(vma); + if (!ev->bind_flags) goto put; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 7fb36b12fe7a..734b6aa61809 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -21,10 +21,13 @@ * IN THE SOFTWARE. */ +#include "i915_active.h" #include "i915_drv.h" #include "i915_scatterlist.h" +#include "i915_sw_fence_work.h" #include "i915_pvinfo.h" #include "i915_vgpu.h" +#include "i915_vma.h" /** * DOC: fence register handling @@ -340,19 +343,37 @@ static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt) return ERR_PTR(-EDEADLK); } +static int fence_wait_bind(struct i915_fence_reg *reg) +{ + struct dma_fence *fence; + int err = 0; + + fence = i915_active_fence_get(®->active.excl); + if (fence) { + err = dma_fence_wait(fence, true); + dma_fence_put(fence); + } + + return err; +} + int __i915_vma_pin_fence(struct i915_vma *vma) { struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm); - struct i915_fence_reg *fence; + struct i915_fence_reg *fence = vma->fence; struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL; int err; lockdep_assert_held(&vma->vm->mutex); /* Just update our place in the LRU if our fence is getting reused. */ - if (vma->fence) { - fence = vma->fence; + if (fence) { GEM_BUG_ON(fence->vma != vma); + + err = fence_wait_bind(fence); + if (err) + return err; + atomic_inc(&fence->pin_count); if (!fence->dirty) { list_move_tail(&fence->link, &ggtt->fence_list); @@ -384,6 +405,116 @@ int __i915_vma_pin_fence(struct i915_vma *vma) return err; } +static int set_bind_fence(struct i915_fence_reg *fence, + struct dma_fence_work *work) +{ + struct dma_fence *prev; + int err; + + if (rcu_access_pointer(fence->active.excl.fence) == &work->dma) + return 0; + + err = i915_sw_fence_await_active(&work->chain, + &fence->active, + I915_ACTIVE_AWAIT_ACTIVE); + if (err) + return err; + + if (i915_active_acquire(&fence->active)) + return -ENOENT; + + prev = i915_active_set_exclusive(&fence->active, &work->dma); + if (unlikely(prev)) { + err = i915_sw_fence_await_dma_fence(&work->chain, prev, 0, + GFP_NOWAIT | __GFP_NOWARN); + dma_fence_put(prev); + } + + i915_active_release(&fence->active); + return err < 0 ? err : 0; +} + +int __i915_vma_pin_fence_async(struct i915_vma *vma, + struct dma_fence_work *work) +{ + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm); + struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL; + struct i915_fence_reg *fence = vma->fence; + int err; + + lockdep_assert_held(&vma->vm->mutex); + + /* Just update our place in the LRU if our fence is getting reused. */ + if (fence) { + GEM_BUG_ON(fence->vma != vma); + GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma)); + } else if (set) { + if (!i915_vma_is_map_and_fenceable(vma)) + return -EINVAL; + + fence = fence_find(ggtt); + if (IS_ERR(fence)) + return -ENOSPC; + + GEM_BUG_ON(atomic_read(&fence->pin_count)); + fence->dirty = true; + } else { + return 0; + } + + atomic_inc(&fence->pin_count); + list_move_tail(&fence->link, &ggtt->fence_list); + if (!fence->dirty) + return 0; + + if (INTEL_GEN(fence_to_i915(fence)) < 4 && + rcu_access_pointer(vma->active.excl.fence) != &work->dma) { + /* implicit 'unfenced' GPU blits */ + err = i915_sw_fence_await_active(&work->chain, + &vma->active, + I915_ACTIVE_AWAIT_ACTIVE); + if (err) + goto err_unpin; + } + + err = set_bind_fence(fence, work); + if (err) + goto err_unpin; + + if (set) { + fence->start = vma->node.start; + fence->size = vma->fence_size; + fence->stride = i915_gem_object_get_stride(vma->obj); + fence->tiling = i915_gem_object_get_tiling(vma->obj); + + vma->fence = fence; + } else { + fence->tiling = 0; + vma->fence = NULL; + } + + set = xchg(&fence->vma, set); + if (set && set != vma) { + GEM_BUG_ON(set->fence != fence); + WRITE_ONCE(set->fence, NULL); + i915_vma_revoke_mmap(set); + } + + return 0; + +err_unpin: + atomic_dec(&fence->pin_count); + return err; +} + +void __i915_vma_apply_fence_async(struct i915_vma *vma) +{ + struct i915_fence_reg *fence = vma->fence; + + if (fence->dirty) + fence_write(fence); +} + /** * i915_vma_pin_fence - set up fencing for a vma * @vma: vma to map through a fence reg diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h index 9eef679e1311..d306ac14d47e 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h @@ -30,6 +30,7 @@ #include "i915_active.h" +struct dma_fence_work; struct drm_i915_gem_object; struct i915_ggtt; struct i915_vma; @@ -70,6 +71,10 @@ void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, struct sg_table *pages); +int __i915_vma_pin_fence_async(struct i915_vma *vma, + struct dma_fence_work *work); +void __i915_vma_apply_fence_async(struct i915_vma *vma); + void intel_ggtt_init_fences(struct i915_ggtt *ggtt); void intel_ggtt_fini_fences(struct i915_ggtt *ggtt); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:36 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:36 +0100 Subject: [Intel-gfx] [PATCH 26/36] drm/syncobj: Allow use of dma-fence-proxy In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-26-chris@chris-wilson.co.uk> Allow the callers to supply a dma-fence-proxy for asynchronous waiting on future fences. Signed-off-by: Chris Wilson --- drivers/gpu/drm/drm_syncobj.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index 42d46414f767..e141db0e1eb6 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -184,6 +184,7 @@ */ #include +#include #include #include #include @@ -324,14 +325,9 @@ void drm_syncobj_replace_fence(struct drm_syncobj *syncobj, struct dma_fence *old_fence; struct syncobj_wait_entry *cur, *tmp; - if (fence) - dma_fence_get(fence); - spin_lock(&syncobj->lock); - old_fence = rcu_dereference_protected(syncobj->fence, - lockdep_is_held(&syncobj->lock)); - rcu_assign_pointer(syncobj->fence, fence); + old_fence = dma_fence_replace_proxy(&syncobj->fence, fence); if (fence != old_fence) { list_for_each_entry_safe(cur, tmp, &syncobj->cb_list, node) -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:13 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:13 +0100 Subject: [Intel-gfx] [PATCH 03/36] drm/i915/gt: Move legacy context wa to intel_workarounds In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-3-chris@chris-wilson.co.uk> Use the central mechanism for recording and verifying that we restore the w/a for the older devices as well. Signed-off-by: Chris Wilson --- .../gpu/drm/i915/gt/intel_ring_submission.c | 28 ----------------- drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 +++++++++++++++++++ 2 files changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 96881cd8b17b..d9c1701061b9 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -429,32 +429,6 @@ static void reset_finish(struct intel_engine_cs *engine) { } -static int rcs_resume(struct intel_engine_cs *engine) -{ - struct drm_i915_private *i915 = engine->i915; - struct intel_uncore *uncore = engine->uncore; - - /* - * Disable CONSTANT_BUFFER before it is loaded from the context - * image. For as it is loaded, it is executed and the stored - * address may no longer be valid, leading to a GPU hang. - * - * This imposes the requirement that userspace reload their - * CONSTANT_BUFFER on every batch, fortunately a requirement - * they are already accustomed to from before contexts were - * enabled. - */ - if (IS_GEN(i915, 4)) - intel_uncore_write(uncore, ECOSKPD, - _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)); - - if (IS_GEN_RANGE(i915, 6, 7)) - intel_uncore_write(uncore, INSTPM, - _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); - - return xcs_resume(engine); -} - static void reset_cancel(struct intel_engine_cs *engine) { struct i915_request *request; @@ -1139,8 +1113,6 @@ static void setup_rcs(struct intel_engine_cs *engine) if (IS_HASWELL(i915)) engine->emit_bb_start = hsw_emit_bb_start; - - engine->resume = rcs_resume; } static void setup_vcs(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index fa1e15657663..94d66a9d760d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -199,6 +199,18 @@ wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) #define WA_SET_FIELD_MASKED(addr, mask, value) \ wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) +static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); +} + +static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); +} + static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { @@ -638,6 +650,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, chv_ctx_workarounds_init(engine, wal); else if (IS_BROADWELL(i915)) bdw_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 7)) + gen7_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 6)) + gen6_ctx_workarounds_init(engine, wal); else if (INTEL_GEN(i915) < 8) return; else @@ -1583,6 +1599,21 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), /* XXX bit doesn't stick on Broadwater */ IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); + + if (IS_GEN(i915, 4)) + /* + * Disable CONSTANT_BUFFER before it is loaded from the context + * image. For as it is loaded, it is executed and the stored + * address may no longer be valid, leading to a GPU hang. + * + * This imposes the requirement that userspace reload their + * CONSTANT_BUFFER on every batch, fortunately a requirement + * they are already accustomed to from before contexts were + * enabled. + */ + wa_add(wal, ECOSKPD, + 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), + 0 /* XXX bit doesn't stick on Broadwater */); } static void -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:41 +0100 Subject: [Intel-gfx] [PATCH 31/36] drm/i915: Always defer fenced work to the worker In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-31-chris@chris-wilson.co.uk> Currently, if an error is raised we always call the cleanup locally [and skip the main work callback]. However, some future users may need to take a mutex to cleanup and so we cannot immediately execute the cleanup as we may still be in interrupt context. With the execute-immediate flag, for most cases this should result in immediate cleanup of an error. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_sw_fence_work.c | 25 +++++++++++------------ 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.c b/drivers/gpu/drm/i915/i915_sw_fence_work.c index a3a81bb8f2c3..29f63ebc24e8 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence_work.c +++ b/drivers/gpu/drm/i915/i915_sw_fence_work.c @@ -16,11 +16,14 @@ static void fence_complete(struct dma_fence_work *f) static void fence_work(struct work_struct *work) { struct dma_fence_work *f = container_of(work, typeof(*f), work); - int err; - err = f->ops->work(f); - if (err) - dma_fence_set_error(&f->dma, err); + if (!f->dma.error) { + int err; + + err = f->ops->work(f); + if (err) + dma_fence_set_error(&f->dma, err); + } fence_complete(f); dma_fence_put(&f->dma); @@ -36,15 +39,11 @@ fence_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) if (fence->error) dma_fence_set_error(&f->dma, fence->error); - if (!f->dma.error) { - dma_fence_get(&f->dma); - if (test_bit(DMA_FENCE_WORK_IMM, &f->dma.flags)) - fence_work(&f->work); - else - queue_work(system_unbound_wq, &f->work); - } else { - fence_complete(f); - } + dma_fence_get(&f->dma); + if (test_bit(DMA_FENCE_WORK_IMM, &f->dma.flags)) + fence_work(&f->work); + else + queue_work(system_unbound_wq, &f->work); break; case FENCE_FREE: -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:23 +0100 Subject: [Intel-gfx] [PATCH 13/36] drm/i915: Relinquish forcewake immediately after manual grouping In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-13-chris@chris-wilson.co.uk> Our forcewake utilisation is split into categories: automatic and manual. Around bare register reads, we look up the right forcewake domain and automatically acquire and release [upon a timer] the forcewake domain. For other access, where we know we require the forcewake across a group of register reads, we manually acquire the forcewake domain and release it at the end. Again, this currently arms the domain timer for a later release. However, looking at some energy utilisation profiles, we have tried to avoid using forcewake [and rely on the natural wake up to post register updates] due to that even keep the fw active for a brief period contributes to a significant power draw [i.e. when the gpu is sleeping with rc6 at high clocks]. But as it turns out, not posting the writes immediately also has unintended consequences, such as not reducing the clocks and so conserving power while busy. As a compromise, let us only arm the domain timer for automatic forcewake usage around bare register access, but immediately release the forcewake when manually acquired by intel_uncore_forcewake_get/_put. The corollary to this is that we may instead have to take forcewake more often, and so incur a latency penalty in doing so. For Sandybridge this was significant, and even on the latest machines, taking forcewake at interrupt frequency is a huge impact. [So we don't do that anymore! Hopefully, this will spare us from still needing the mitigation of the timer for steady state execution.] Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala --- drivers/gpu/drm/i915/intel_uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index a61cb8ca4d50..7d6b9ae7403c 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -709,7 +709,7 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, continue; } - fw_domain_arm_timer(domain); + uncore->funcs.force_wake_put(uncore, domain->mask); } } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:38 +0100 Subject: [Intel-gfx] [PATCH 28/36] drm/i915/gem: Allow combining submit-fences with syncobj In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-28-chris@chris-wilson.co.uk> We allow exported sync_file fences to be used as submit fences, but they are not the only source of user fences. We also accept an array of syncobj, and as with sync_file these are dma_fences underneath and so feature the same set of controls. The submit-fence allows for a request to be scheduled at the same time as the signaler, rather than as normal after. Userspace can combine submit-fence with its own semaphores for intra-batch scheduling. Not exposing submit-fences to syncobj was at the time just a matter of pragmatic expediency. Fixes: a88b6e4cbafd ("drm/i915: Allow specification of parallel execbuf") Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854 Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Lionel Landwerlin Reviewed-by: Tvrtko Ursulin --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 14 +++++++---- drivers/gpu/drm/i915/i915_request.c | 25 +++++++++++++++++++ include/uapi/drm/i915_drm.h | 7 +++--- 3 files changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 4fddbe34efa6..cb4872ccfe58 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2397,7 +2397,7 @@ static void __free_fence_array(struct drm_syncobj **fences, unsigned int n) { while (n--) - drm_syncobj_put(ptr_mask_bits(fences[n], 2)); + drm_syncobj_put(ptr_mask_bits(fences[n], 3)); kvfree(fences); } @@ -2454,7 +2454,7 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args, BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) & ~__I915_EXEC_FENCE_UNKNOWN_FLAGS); - fences[n] = ptr_pack_bits(syncobj, fence.flags, 2); + fences[n] = ptr_pack_bits(syncobj, fence.flags, 3); } return fences; @@ -2485,7 +2485,7 @@ await_fence_array(struct i915_execbuffer *eb, struct dma_fence *fence; unsigned int flags; - syncobj = ptr_unpack_bits(fences[n], &flags, 2); + syncobj = ptr_unpack_bits(fences[n], &flags, 3); if (!(flags & I915_EXEC_FENCE_WAIT)) continue; @@ -2509,7 +2509,11 @@ await_fence_array(struct i915_execbuffer *eb, spin_unlock(&syncobj->lock); } - err = i915_request_await_dma_fence(eb->request, fence); + if (flags & I915_EXEC_FENCE_WAIT_SUBMIT) + err = i915_request_await_execution(eb->request, fence, + eb->engine->bond_execute); + else + err = i915_request_await_dma_fence(eb->request, fence); dma_fence_put(fence); if (err < 0) return err; @@ -2530,7 +2534,7 @@ signal_fence_array(struct i915_execbuffer *eb, struct drm_syncobj *syncobj; unsigned int flags; - syncobj = ptr_unpack_bits(fences[n], &flags, 2); + syncobj = ptr_unpack_bits(fences[n], &flags, 3); if (!(flags & I915_EXEC_FENCE_SIGNAL)) continue; diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 02747c171c54..a570a1f43d70 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1385,6 +1385,27 @@ __i915_request_await_proxy(struct i915_request *rq, return 0; } +static int execution_proxy(struct await_proxy *ap) +{ + return i915_request_await_execution(ap->request, ap->fence, ap->data); +} + +static int +i915_request_await_proxy_execution(struct i915_request *rq, + struct dma_fence *fence, + void (*hook)(struct i915_request *rq, + struct dma_fence *signal)) +{ + /* + * We have to wait until the real request is known in order to + * be able to hook into its execution, as opposed to waiting for + * its completion. + */ + return __i915_request_await_proxy(rq, fence, + i915_fence_timeout(rq->i915), + execution_proxy, hook); +} + int i915_request_await_execution(struct i915_request *rq, struct dma_fence *fence, @@ -1424,6 +1445,10 @@ i915_request_await_execution(struct i915_request *rq, ret = __i915_request_await_execution(rq, to_request(fence), hook); + else if (dma_fence_is_proxy(fence)) + ret = i915_request_await_proxy_execution(rq, + fence, + hook); else ret = i915_request_await_external(rq, fence); if (ret < 0) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 14b67cd6b54b..704dd0e3bc1d 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1040,9 +1040,10 @@ struct drm_i915_gem_exec_fence { */ __u32 handle; -#define I915_EXEC_FENCE_WAIT (1<<0) -#define I915_EXEC_FENCE_SIGNAL (1<<1) -#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1)) +#define I915_EXEC_FENCE_WAIT (1u << 0) +#define I915_EXEC_FENCE_SIGNAL (1u << 1) +#define I915_EXEC_FENCE_WAIT_SUBMIT (1u << 2) +#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_WAIT_SUBMIT << 1)) __u32 flags; }; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 07:24:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 08:24:33 +0100 Subject: [Intel-gfx] [PATCH 23/36] dma-buf: Proxy fence, an unsignaled fence placeholder In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <20200601072446.19548-23-chris@chris-wilson.co.uk> Often we need to create a fence for a future event that has not yet been associated with a fence. We can store a proxy fence, a placeholder, in the timeline and replace it later when the real fence is known. Any listeners that attach to the proxy fence will automatically be signaled when the real fence completes, and any future listeners will instead be attach directly to the real fence avoiding any indirection overhead. Signed-off-by: Chris Wilson Cc: Lionel Landwerlin --- drivers/dma-buf/Makefile | 13 +- drivers/dma-buf/dma-fence-private.h | 20 + drivers/dma-buf/dma-fence-proxy.c | 306 +++++++++++ drivers/dma-buf/dma-fence.c | 4 +- drivers/dma-buf/selftests.h | 1 + drivers/dma-buf/st-dma-fence-proxy.c | 752 +++++++++++++++++++++++++++ include/linux/dma-fence-proxy.h | 38 ++ 7 files changed, 1130 insertions(+), 4 deletions(-) create mode 100644 drivers/dma-buf/dma-fence-private.h create mode 100644 drivers/dma-buf/dma-fence-proxy.c create mode 100644 drivers/dma-buf/st-dma-fence-proxy.c create mode 100644 include/linux/dma-fence-proxy.h diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile index 995e05f609ff..afaf6dadd9a3 100644 --- a/drivers/dma-buf/Makefile +++ b/drivers/dma-buf/Makefile @@ -1,6 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \ - dma-resv.o seqno-fence.o +obj-y := \ + dma-buf.o \ + dma-fence.o \ + dma-fence-array.o \ + dma-fence-chain.o \ + dma-fence-proxy.o \ + dma-resv.o \ + seqno-fence.o obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o obj-$(CONFIG_DMABUF_HEAPS) += heaps/ obj-$(CONFIG_SYNC_FILE) += sync_file.o @@ -10,6 +16,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o dmabuf_selftests-y := \ selftest.o \ st-dma-fence.o \ - st-dma-fence-chain.o + st-dma-fence-chain.o \ + st-dma-fence-proxy.o obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o diff --git a/drivers/dma-buf/dma-fence-private.h b/drivers/dma-buf/dma-fence-private.h new file mode 100644 index 000000000000..6924d28af0fa --- /dev/null +++ b/drivers/dma-buf/dma-fence-private.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf and to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + */ + +#ifndef DMA_FENCE_PRIVATE_H +#define DMA_FENCE_PRIAVTE_H + +struct dma_fence; + +bool __dma_fence_enable_signaling(struct dma_fence *fence); + +#endif /* DMA_FENCE_PRIAVTE_H */ diff --git a/drivers/dma-buf/dma-fence-proxy.c b/drivers/dma-buf/dma-fence-proxy.c new file mode 100644 index 000000000000..42674e92b0f9 --- /dev/null +++ b/drivers/dma-buf/dma-fence-proxy.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dma-fence-proxy: placeholder unsignaled fence + * + * Copyright (C) 2017-2019 Intel Corporation + */ + +#include +#include +#include +#include +#include + +#include "dma-fence-private.h" + +struct dma_fence_proxy { + struct dma_fence base; + + struct dma_fence *real; + struct dma_fence_cb cb; + struct irq_work work; + + wait_queue_head_t wq; +}; + +#ifdef CONFIG_DEBUG_LOCK_ALLOC +#define same_lockclass(A, B) (A)->dep_map.key == (B)->dep_map.key +#else +#define same_lockclass(A, B) 0 +#endif + +static const char *proxy_get_driver_name(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + + return real ? real->ops->get_driver_name(real) : "proxy"; +} + +static const char *proxy_get_timeline_name(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + + return real ? real->ops->get_timeline_name(real) : "unset"; +} + +static void proxy_irq_work(struct irq_work *work) +{ + struct dma_fence_proxy *p = container_of(work, typeof(*p), work); + + dma_fence_signal(&p->base); + dma_fence_put(&p->base); +} + +static void proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb) +{ + struct dma_fence_proxy *p = container_of(cb, typeof(*p), cb); + + /* Signaled before enabling signalling callbacks? */ + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &p->base.flags)) { + dma_fence_put(&p->base); + return; + } + + if (real->error) + dma_fence_set_error(&p->base, real->error); + + /* Lower the height of the proxy chain -> single stack frame */ + irq_work_queue(&p->work); +} + +static bool proxy_enable_signaling(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + bool ret = true; + + if (real) { + spin_lock_nested(real->lock, + same_lockclass(&p->wq.lock, real->lock)); + ret = __dma_fence_enable_signaling(real); + if (!ret && real->error) + dma_fence_set_error(&p->base, real->error); + spin_unlock(real->lock); + } + + return ret; +} + +static void proxy_release(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + + dma_fence_put(p->real); + dma_fence_free(&p->base); +} + +const struct dma_fence_ops dma_fence_proxy_ops = { + .get_driver_name = proxy_get_driver_name, + .get_timeline_name = proxy_get_timeline_name, + .enable_signaling = proxy_enable_signaling, + .wait = dma_fence_default_wait, + .release = proxy_release, +}; +EXPORT_SYMBOL_GPL(dma_fence_proxy_ops); + +/** + * __dma_fence_create_proxy - Create an unset dma-fence + * @context: context number to use for proxy fence + * @seqno: sequence number to use for proxy fence + * + * __dma_fence_create_proxy() creates a new dma_fence stub that is initially + * unsignaled and may later be replaced with a real fence. Any listeners + * to the proxy fence will be signaled when the target fence signals its + * completion. + */ +struct dma_fence *__dma_fence_create_proxy(u64 context, u64 seqno) +{ + struct dma_fence_proxy *p; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) + return NULL; + + init_waitqueue_head(&p->wq); + dma_fence_init(&p->base, &dma_fence_proxy_ops, &p->wq.lock, + context, seqno); + init_irq_work(&p->work, proxy_irq_work); + + return &p->base; +} +EXPORT_SYMBOL(__dma_fence_create_proxy); + +/** + * dma_fence_create_proxy - Create an unset dma-fence + * + * Wraps __dma_fence_create_proxy() to create a new proxy fence with the + * next available (unique) context id. + */ +struct dma_fence *dma_fence_create_proxy(void) +{ + return __dma_fence_create_proxy(dma_fence_context_alloc(1), 0); +} +EXPORT_SYMBOL(dma_fence_create_proxy); + +static void __wake_up_listeners(struct dma_fence_proxy *p) +{ + struct wait_queue_entry *wait, *next; + + list_for_each_entry_safe(wait, next, &p->wq.head, entry) { + INIT_LIST_HEAD(&wait->entry); + wait->func(wait, TASK_NORMAL, 0, p->real); + } +} + +static void set_proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb) +{ + cb->func = proxy_callback; + list_add_tail(&cb->node, &real->cb_list); +} + +static void proxy_assign(struct dma_fence *fence, struct dma_fence *real) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + unsigned long flags; + + if (WARN_ON(fence == real)) + return; + + if (WARN_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) + return; + + if (WARN_ON(p->real)) + return; + + spin_lock_irqsave(&p->wq.lock, flags); + + if (unlikely(!real)) { + dma_fence_signal_locked(&p->base); + goto unlock; + } + + p->real = dma_fence_get(real); + + dma_fence_get(&p->base); + spin_lock_nested(real->lock, same_lockclass(&p->wq.lock, real->lock)); + if (dma_fence_is_signaled_locked(real)) + proxy_callback(real, &p->cb); + else if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &p->base.flags) && + !__dma_fence_enable_signaling(real)) + proxy_callback(real, &p->cb); + else + set_proxy_callback(real, &p->cb); + spin_unlock(real->lock); + +unlock: + __wake_up_listeners(p); + spin_unlock_irqrestore(&p->wq.lock, flags); +} + +/** + * dma_fence_replace_proxy - Replace the proxy fence with the real target + * @slot: pointer to location of fence to update + * @fence: the new fence to store in @slot + * + * Once the real dma_fence is known, we can replace the proxy fence holder + * with a pointer to the real dma fence. Future listeners will attach to + * the real fence, avoiding any indirection overhead. Previous listeners + * will remain attached to the proxy fence, and be signaled in turn when + * the target fence completes. + */ +struct dma_fence * +dma_fence_replace_proxy(struct dma_fence __rcu **slot, struct dma_fence *fence) +{ + struct dma_fence *old; + + if (fence) + dma_fence_get(fence); + + old = rcu_replace_pointer(*slot, fence, true); + if (old && dma_fence_is_proxy(old)) + proxy_assign(old, fence); + + return old; +} +EXPORT_SYMBOL(dma_fence_replace_proxy); + +/** + * dma_fence_proxy_set_real - Set the target of a proxy fence + * @fence: the proxy fence + * @real: the target fence. + * + */ +void dma_fence_proxy_set_real(struct dma_fence *fence, struct dma_fence *real) +{ + if (dma_fence_is_proxy(fence)) + proxy_assign(fence, real); +} +EXPORT_SYMBOL(dma_fence_proxy_set_real); + +/** + * dma_fence_proxy_get_real - Query the target of a proxy fence + * @fence: the proxy fence + * + * Unpeel the proxy fence to see if it has been replaced with a real fence. + */ +struct dma_fence *dma_fence_proxy_get_real(struct dma_fence *fence) +{ + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + + if (p->real) + fence = p->real; + } + + return fence; +} +EXPORT_SYMBOL(dma_fence_proxy_get_real); + +void dma_fence_add_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait) +{ + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + unsigned long flags; + + spin_lock_irqsave(&p->wq.lock, flags); + if (!p->real) { + list_add_tail(&wait->entry, &p->wq.head); + wait = NULL; + } + fence = p->real; + spin_unlock_irqrestore(&p->wq.lock, flags); + } + + if (wait) { + INIT_LIST_HEAD(&wait->entry); + wait->func(wait, TASK_NORMAL, 0, fence); + } +} +EXPORT_SYMBOL(dma_fence_add_proxy_listener); + +bool dma_fence_remove_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait) +{ + bool ret = false; + + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + unsigned long flags; + + spin_lock_irqsave(&p->wq.lock, flags); + if (!list_empty(&wait->entry)) { + list_del_init(&wait->entry); + ret = true; + } + spin_unlock_irqrestore(&p->wq.lock, flags); + } + + return ret; +} +EXPORT_SYMBOL(dma_fence_remove_proxy_listener); diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 656e9ac2d028..329bd033059f 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -19,6 +19,8 @@ #define CREATE_TRACE_POINTS #include +#include "dma-fence-private.h" + EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit); EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal); EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled); @@ -275,7 +277,7 @@ void dma_fence_free(struct dma_fence *fence) } EXPORT_SYMBOL(dma_fence_free); -static bool __dma_fence_enable_signaling(struct dma_fence *fence) +bool __dma_fence_enable_signaling(struct dma_fence *fence) { bool was_set; diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h index 55918ef9adab..616eca70e2d8 100644 --- a/drivers/dma-buf/selftests.h +++ b/drivers/dma-buf/selftests.h @@ -12,3 +12,4 @@ selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */ selftest(dma_fence, dma_fence) selftest(dma_fence_chain, dma_fence_chain) +selftest(dma_fence_proxy, dma_fence_proxy) diff --git a/drivers/dma-buf/st-dma-fence-proxy.c b/drivers/dma-buf/st-dma-fence-proxy.c new file mode 100644 index 000000000000..c3f210bc4e60 --- /dev/null +++ b/drivers/dma-buf/st-dma-fence-proxy.c @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2019 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "selftest.h" + +static struct kmem_cache *slab_fences; + +static struct mock_fence { + struct dma_fence base; + spinlock_t lock; +} *to_mock_fence(struct dma_fence *f) { + return container_of(f, struct mock_fence, base); +} + +static const char *mock_name(struct dma_fence *f) +{ + return "mock"; +} + +static void mock_fence_release(struct dma_fence *f) +{ + kmem_cache_free(slab_fences, to_mock_fence(f)); +} + +static const struct dma_fence_ops mock_ops = { + .get_driver_name = mock_name, + .get_timeline_name = mock_name, + .release = mock_fence_release, +}; + +static struct dma_fence *mock_fence(void) +{ + struct mock_fence *f; + + f = kmem_cache_alloc(slab_fences, GFP_KERNEL); + if (!f) + return NULL; + + spin_lock_init(&f->lock); + dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0); + + return &f->base; +} + +static int sanitycheck(void *arg) +{ + struct dma_fence *f; + + f = dma_fence_create_proxy(); + if (!f) + return -ENOMEM; + + dma_fence_signal(f); + dma_fence_put(f); + + return 0; +} + +struct fences { + struct dma_fence *real; + struct dma_fence *proxy; + struct dma_fence __rcu *slot; +}; + +static int create_fences(struct fences *f, bool attach) +{ + f->proxy = dma_fence_create_proxy(); + if (!f->proxy) + return -ENOMEM; + + RCU_INIT_POINTER(f->slot, f->proxy); + + f->real = mock_fence(); + if (!f->real) { + dma_fence_put(f->proxy); + return -ENOMEM; + } + + if (attach) + dma_fence_replace_proxy(&f->slot, f->real); + + return 0; +} + +static void free_fences(struct fences *f) +{ + dma_fence_put(dma_fence_replace_proxy(&f->slot, NULL)); + + dma_fence_signal(f->real); + dma_fence_put(f->real); + + dma_fence_signal(f->proxy); + dma_fence_put(f->proxy); +} + +static int wrap_target(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_proxy_get_real(f.proxy) != f.proxy) { + pr_err("Unwrapped proxy fenced reported a target fence!\n"); + goto err_free; + } + + dma_fence_proxy_set_real(f.proxy, f.real); + rcu_assign_pointer(f.slot, dma_fence_get(f.real)); /* free_fences() */ + + if (dma_fence_proxy_get_real(f.proxy) != f.real) { + pr_err("Wrapped proxy fenced did not report the target fence!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_proxy(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_proxy_get_real(f.proxy) != f.real) { + pr_err("Wrapped proxy fenced did not report the target fence!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_signaling(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_is_signaled(f.proxy)) { + pr_err("Fence unexpectedly signaled on creation\n"); + goto err_free; + } + + if (dma_fence_signal(f.real)) { + pr_err("Fence reported being already signaled\n"); + goto err_free; + } + + if (!dma_fence_is_signaled(f.proxy)) { + pr_err("Fence not reporting signaled\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_signaling_recurse(void *arg) +{ + struct fences f; + struct dma_fence *chain; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + chain = dma_fence_create_proxy(); + if (!chain) { + err = -ENOMEM; + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, chain); + dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real)); + dma_fence_put(chain); + + /* f.real <- chain <- f.proxy */ + + if (dma_fence_is_signaled(f.proxy)) { + pr_err("Fence unexpectedly signaled on creation\n"); + goto err_free; + } + + if (dma_fence_signal(f.real)) { + pr_err("Fence reported being already signaled\n"); + goto err_free; + } + + if (!dma_fence_is_signaled(f.proxy)) { + pr_err("Fence not reporting signaled\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +struct simple_cb { + struct dma_fence_cb cb; + bool seen; +}; + +static void simple_callback(struct dma_fence *f, struct dma_fence_cb *cb) +{ + /* Ensure the callback marker is visible, no excuses for missing it! */ + smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true); +} + +static int wrap_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_add_callback_recurse(void *arg) +{ + struct simple_cb cb = {}; + struct dma_fence *chain; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + chain = dma_fence_create_proxy(); + if (!chain) { + err = -ENOMEM; + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, chain); + dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real)); + dma_fence_put(chain); + + /* f.real <- chain <- f.proxy */ + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_late_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + dma_fence_signal(f.real); + + if (!dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Added callback, but fence was already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (cb.seen) { + pr_err("Callback called after failed attachment!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback_late(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_signal(f.real); + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback_early(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_rm_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + if (!dma_fence_remove_callback(f.proxy, &cb.cb)) { + pr_err("Failed to remove callback!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (cb.seen) { + pr_err("Callback still signaled after removal!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_late_rm_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + if (dma_fence_remove_callback(f.proxy, &cb.cb)) { + pr_err("Callback removal succeed after being executed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_status(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_get_status(f.proxy)) { + pr_err("Fence unexpectedly has signaled status on creation\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!dma_fence_get_status(f.proxy)) { + pr_err("Fence not reporting signaled status\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_error(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + dma_fence_set_error(f.real, -EIO); + + if (dma_fence_get_status(f.proxy)) { + pr_err("Fence unexpectedly has error status before signal\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (dma_fence_get_status(f.proxy) != -EIO) { + pr_err("Fence not reporting error status, got %d\n", + dma_fence_get_status(f.proxy)); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_wait(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_wait_timeout(f.proxy, false, 0) != 0) { + pr_err("Wait reported complete before being signaled\n"); + goto err_free; + } + + dma_fence_signal(f.real); + + if (dma_fence_wait_timeout(f.proxy, false, 0) == 0) { + pr_err("Wait reported incomplete after being signaled\n"); + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +struct wait_timer { + struct timer_list timer; + struct fences f; +}; + +static void wait_timer(struct timer_list *timer) +{ + struct wait_timer *wt = from_timer(wt, timer, timer); + + dma_fence_signal(wt->f.real); +} + +static int wrap_wait_timeout(void *arg) +{ + struct wait_timer wt; + int err = -EINVAL; + + if (create_fences(&wt.f, true)) + return -ENOMEM; + + timer_setup_on_stack(&wt.timer, wait_timer, 0); + + if (dma_fence_wait_timeout(wt.f.proxy, false, 1) != 0) { + pr_err("Wait reported complete before being signaled\n"); + goto err_free; + } + + mod_timer(&wt.timer, jiffies + 1); + + if (dma_fence_wait_timeout(wt.f.proxy, false, 2) != 0) { + if (timer_pending(&wt.timer)) { + pr_notice("Timer did not fire within the jiffie!\n"); + err = 0; /* not our fault! */ + } else { + pr_err("Wait reported incomplete after timeout\n"); + } + goto err_free; + } + + err = 0; +err_free: + del_timer_sync(&wt.timer); + destroy_timer_on_stack(&wt.timer); + dma_fence_signal(wt.f.real); + free_fences(&wt.f); + return err; +} + +struct proxy_wait { + struct wait_queue_entry base; + struct dma_fence *fence; + bool seen; +}; + +static int proxy_wait_cb(struct wait_queue_entry *entry, + unsigned int mode, int flags, void *key) +{ + struct proxy_wait *p = container_of(entry, typeof(*p), base); + + p->fence = key; + p->seen = true; + + return 0; +} + +static int wrap_listen_early(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_add_proxy_listener(f.proxy, &wait.base); + + if (!wait.seen) { + pr_err("Proxy listener was not called after replace!\n"); + err = -EINVAL; + goto err_free; + } + + if (wait.fence != f.real) { + pr_err("Proxy listener was not passed the real fence!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +static int wrap_listen_late(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_add_proxy_listener(f.proxy, &wait.base); + dma_fence_replace_proxy(&f.slot, f.real); + + if (!wait.seen) { + pr_err("Proxy listener was not called on replace!\n"); + err = -EINVAL; + goto err_free; + } + + if (wait.fence != f.real) { + pr_err("Proxy listener was not passed the real fence!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +static int wrap_listen_cancel(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_add_proxy_listener(f.proxy, &wait.base); + if (!dma_fence_remove_proxy_listener(f.proxy, &wait.base)) { + pr_err("Cancelling listener, already detached?\n"); + err = -EINVAL; + goto err_free; + } + dma_fence_replace_proxy(&f.slot, f.real); + + if (wait.seen) { + pr_err("Proxy listener was called after being removed!\n"); + err = -EINVAL; + goto err_free; + } + + if (dma_fence_remove_proxy_listener(f.proxy, &wait.base)) { + pr_err("Double listener cancellation!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +int dma_fence_proxy(void) +{ + static const struct subtest tests[] = { + SUBTEST(sanitycheck), + SUBTEST(wrap_target), + SUBTEST(wrap_proxy), + SUBTEST(wrap_signaling), + SUBTEST(wrap_signaling_recurse), + SUBTEST(wrap_add_callback), + SUBTEST(wrap_add_callback_recurse), + SUBTEST(wrap_late_add_callback), + SUBTEST(wrap_early_add_callback), + SUBTEST(wrap_early_add_callback_late), + SUBTEST(wrap_early_add_callback_early), + SUBTEST(wrap_rm_callback), + SUBTEST(wrap_late_rm_callback), + SUBTEST(wrap_status), + SUBTEST(wrap_error), + SUBTEST(wrap_wait), + SUBTEST(wrap_wait_timeout), + SUBTEST(wrap_listen_early), + SUBTEST(wrap_listen_late), + SUBTEST(wrap_listen_cancel), + }; + int ret; + + slab_fences = KMEM_CACHE(mock_fence, + SLAB_TYPESAFE_BY_RCU | + SLAB_HWCACHE_ALIGN); + if (!slab_fences) + return -ENOMEM; + + ret = subtests(tests, NULL); + + kmem_cache_destroy(slab_fences); + + return ret; +} diff --git a/include/linux/dma-fence-proxy.h b/include/linux/dma-fence-proxy.h new file mode 100644 index 000000000000..6a986b5bb009 --- /dev/null +++ b/include/linux/dma-fence-proxy.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * dma-fence-proxy: allows waiting upon unset and future fences + * + * Copyright (C) 2017 Intel Corporation + */ + +#ifndef __LINUX_DMA_FENCE_PROXY_H +#define __LINUX_DMA_FENCE_PROXY_H + +#include +#include + +struct wait_queue_entry; + +extern const struct dma_fence_ops dma_fence_proxy_ops; + +struct dma_fence *__dma_fence_create_proxy(u64 context, u64 seqno); +struct dma_fence *dma_fence_create_proxy(void); + +static inline bool dma_fence_is_proxy(struct dma_fence *fence) +{ + return fence->ops == &dma_fence_proxy_ops; +} + +void dma_fence_proxy_set_real(struct dma_fence *fence, struct dma_fence *real); +struct dma_fence *dma_fence_proxy_get_real(struct dma_fence *fence); + +struct dma_fence * +dma_fence_replace_proxy(struct dma_fence __rcu **slot, + struct dma_fence *fence); + +void dma_fence_add_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait); +bool dma_fence_remove_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait); + +#endif /* __LINUX_DMA_FENCE_PROXY_H */ -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 1 07:34:55 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 07:34:55 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/36=5D_drm/i915=3A_Handle_very_ea?= =?utf-8?q?rly_engine_initialisation_failure?= In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <159099689524.14890.11404278274057905125@emeril.freedesktop.org> == Series Details == Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure URL : https://patchwork.freedesktop.org/series/77857/ State : warning == Summary == $ dim checkpatch origin/drm-tip 96d738818236 drm/i915: Handle very early engine initialisation failure 284e5e82f9e8 drm/i915/gt: Split low level gen2-7 CS emitters -:9: WARNING:TYPO_SPELLING: 'wnat' may be misspelled - perhaps 'want'? #9: with requests, and we will wnat to reuse them outside of this context. -:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #27: new file mode 100644 -:179: WARNING:LONG_LINE: line over 100 characters #179: FILE: drivers/gpu/drm/i915/gt/gen2_engine_cs.c:148: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:202: WARNING:LONG_LINE: line over 100 characters #202: FILE: drivers/gpu/drm/i915/gt/gen2_engine_cs.c:171: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:220: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #220: FILE: drivers/gpu/drm/i915/gt/gen2_engine_cs.c:189: +} +#undef GEN5_WA_STORES -:798: WARNING:LONG_LINE: line over 100 characters #798: FILE: drivers/gpu/drm/i915/gt/gen6_engine_cs.c:377: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:818: WARNING:LONG_LINE: line over 100 characters #818: FILE: drivers/gpu/drm/i915/gt/gen6_engine_cs.c:397: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:843: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #843: FILE: drivers/gpu/drm/i915/gt/gen6_engine_cs.c:422: +} +#undef GEN7_XCS_WA total: 0 errors, 6 warnings, 2 checks, 1812 lines checked 8f9e2ddc2328 drm/i915/gt: Move legacy context wa to intel_workarounds 5b9d253c3510 drm/i915: Trim the ironlake+ irq handler cf0807656a76 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" ce9a7aebf8d2 drm/i915/gt: Couple tasklet scheduling for all CS interrupts eacfbfb97087 drm/i915/gt: Support creation of 'internal' rings 58305c0b593a drm/i915/gt: Use client timeline address for seqno writes 703dea6710a7 drm/i915: Support inter-engine semaphores on gen6/7 15787ec4da9d drm/i915/gt: Infrastructure for ring scheduling -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 842 lines checked 0760ab97f627 drm/i915/gt: Enable busy-stats for ring-scheduler -:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #13: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 232 lines checked 118524c684c6 drm/i915/gt: Track if an engine requires forcewake w/a 99a81a3f55b0 drm/i915: Relinquish forcewake immediately after manual grouping 8c829f7c5554 drm/i915/gt: Implement ring scheduler for gen6/7 -:68: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #68: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:324: + *cs++ = i915_mmio_reg_offset( -:70: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #70: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:326: + *cs++ = _MASKED_BIT_ENABLE( -:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #105: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:361: + *cs++ = _MASKED_BIT_DISABLE( total: 0 errors, 0 warnings, 3 checks, 512 lines checked 3148cd01132a drm/i915/gt: Enable ring scheduling for gen6/7 143d1995d466 drm/i915/gem: Mark the buffer pool as active for the cmdparser 033b56b47071 drm/i915/gem: Async GPU relocations only 9b9d4aa5ab50 drm/i915: Add list_for_each_entry_safe_continue_reverse -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) total: 0 errors, 0 warnings, 3 checks, 12 lines checked b2abfeed9589 drm/i915/gem: Separate reloc validation into an earlier step -:101: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return #101: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1408: + return (int)offset; + } else { total: 0 errors, 1 warnings, 0 checks, 217 lines checked c26758f43cfe drm/i915/gem: Lift GPU relocation allocation 6f01210067aa drm/i915/gem: Build the reloc request first 710af09a4672 drm/i915/gem: Add all GPU reloc awaits/signals en masse 6b9cc101590e dma-buf: Proxy fence, an unsignaled fence placeholder -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 -:438: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #438: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20: + spinlock_t lock; total: 0 errors, 1 warnings, 1 checks, 1158 lines checked 06d2116fd5f4 drm/i915: Unpeel awaits on a proxy fence f3cd5ea0ff2c drm/i915/gem: Make relocations atomic within execbuf dda5123316b5 drm/syncobj: Allow use of dma-fence-proxy d03f86e3977c drm/i915/gem: Teach execbuf how to wait on future syncobj 9b560a7e6079 drm/i915/gem: Allow combining submit-fences with syncobj 9675274fc27c drm/i915/gt: Declare when we enabled timeslicing 7cf3aad63437 drm/i915: Drop I915_IDLE_ENGINES_TIMEOUT 308d42d80cb3 drm/i915: Always defer fenced work to the worker b253079dbe95 drm/i915/gem: Assign context id for async work 68f85c40ff48 drm/i915: Export a preallocate variant of i915_active_acquire() d90d92d26c5c drm/i915/gem: Separate the ww_mutex walker into its own list 9c2cdb286a07 drm/i915/gem: Asynchronous GTT unbinding ac90fd42eb1d drm/i915/gem: Bind the fence async for execbuf From kishore.kadiyala at intel.com Mon Jun 1 07:35:44 2020 From: kishore.kadiyala at intel.com (Kishore Kadiyala) Date: Mon, 1 Jun 2020 13:05:44 +0530 Subject: [Intel-gfx] [PATCH v6] drm/i915: Add Plane color encoding support for YCBCR_BT2020 Message-ID: <20200601073544.11291-1-kishore.kadiyala@intel.com> Currently the plane property doesn't have support for YCBCR_BT2020, which enables the corresponding color conversion mode on plane CSC. Enabling the plane property for the planes for GLK & ICL+ platforms. Also as per spec, update the Plane Color CSC from YUV601_TO_RGB709 to YUV601_TO_RGB601. V2: Enabling support for YCBCT_BT2020 for HDR planes on platforms GLK & ICL V3: Refined the condition check to handle GLK & ICL+ HDR planes Also added BT2020 handling in glk_plane_color_ctl. V4: Combine If-else into single If V5: Drop the checking for HDR planes and enable YCBCR_BT2020 for platforms GLK & ICL+. V6: As per Spec, update PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 to PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 as per Ville's feedback. V7: Rebased Cc: Ville Syrjala Cc: Jani Nikula Reviewed-by: Uma Shankar Signed-off-by: Kishore Kadiyala --- drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++---- drivers/gpu/drm/i915/display/intel_sprite.c | 9 +++++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8f9f9b20d5f5..a9f752d26b4e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4812,11 +4812,18 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { - if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) + switch (plane_state->hw.color_encoding) { + case DRM_COLOR_YCBCR_BT709: plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; - else - plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709; - + break; + case DRM_COLOR_YCBCR_BT2020: + plane_color_ctl |= + PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; + break; + default: + plane_color_ctl |= + PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; + } if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; } else if (fb->format->is_yuv) { diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 571c36f929bd..3cd461bf9131 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -3061,6 +3061,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, struct intel_plane *plane; enum drm_plane_type plane_type; unsigned int supported_rotations; + unsigned int supported_csc; const u64 *modifiers; const u32 *formats; int num_formats; @@ -3135,9 +3136,13 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, DRM_MODE_ROTATE_0, supported_rotations); + supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); + + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); + drm_plane_create_color_properties(&plane->base, - BIT(DRM_COLOR_YCBCR_BT601) | - BIT(DRM_COLOR_YCBCR_BT709), + supported_csc, BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | BIT(DRM_COLOR_YCBCR_FULL_RANGE), DRM_COLOR_YCBCR_BT709, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e9d50fe0f375..578cfe11cbb9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6932,7 +6932,7 @@ enum { #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) -#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17) #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) -- 2.26.2 From patchwork at emeril.freedesktop.org Mon Jun 1 07:36:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 07:36:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/36=5D_drm/i915=3A_Handle_very_early_?= =?utf-8?q?engine_initialisation_failure?= In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <159099697876.14888.17247904190884517007@emeril.freedesktop.org> == Series Details == Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure URL : https://patchwork.freedesktop.org/series/77857/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y From stanislav.lisovskiy at intel.com Mon Jun 1 07:49:54 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Mon, 1 Jun 2020 10:49:54 +0300 Subject: [Intel-gfx] [PATCH v1] drm/i915: Fix wrong CDCLK adjustment changes In-Reply-To: <20200529235738.GA3731@intel.com> References: <20200526094852.6967-1-stanislav.lisovskiy@intel.com> <20200529235738.GA3731@intel.com> Message-ID: <20200601074954.GA2239@intel.com> On Fri, May 29, 2020 at 04:57:38PM -0700, Manasi Navare wrote: > On Tue, May 26, 2020 at 12:48:52PM +0300, Stanislav Lisovskiy wrote: > > Previous patch didn't take into account all pipes > > but only those in state, which could cause wrong > > CDCLK conclcusions and calculations. > > Also there was a severe issue with min_cdclk being > > assigned to 0 every compare cycle. > > > > Too bad this was found by me only after merge. > > This could be also causing the issues in test, however > > not clear - anyway marking this as fixing the > > "Adjust CDCLK accordingly to our DBuf bw needs". > > > > Signed-off-by: Stanislav Lisovskiy > > Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") > > --- > > drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++++++-------- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++--- > > drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- > > 3 files changed, 53 insertions(+), 43 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > > index a79bd7aeb03b..8096138abecc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > struct intel_crtc *crtc; > > int max_bw = 0; > > int slice_id; > > + enum pipe pipe; > > int i; > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > @@ -447,7 +448,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > if (IS_ERR(new_bw_state)) > > return PTR_ERR(new_bw_state); > > > > - crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; > > + old_bw_state = intel_atomic_get_old_bw_state(state); > > + > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > > > > @@ -478,6 +481,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > > crtc_bw->used_bw[slice_id] += data_rate; > > } > > + } > > + > > + if (!old_bw_state) > > + return 0; > > + > > + for_each_pipe(dev_priv, pipe) { > > + struct intel_dbuf_bw *crtc_bw; > > + > > So the condition !old_bw_state() will make sure we loop through > only the active pipes and compute crtc_bw only for those right? > > Manasi Well, in fact this condition just checks if we had any crtcs in state - otherwise there were no changes, so bw_state global object doesn't need to be changed. Whenever something happens to crtc we should have it in the state, so this condition just checks if we need to modify bw_state or not. Regarding active/inactive pipes - currently for inactive pipes, we are going to get 0 dbuf slice mask, so we just won't accumulate any data rate for those. So if the pipe got disabled we will get less required min_cdclk which against old_bw_state, which will mean that we are going to acquire the global state lock for writing. In fact we could optimize the code by skipping inactive pipes completely i.e don't even calculate dbuf slice mask, which will be 0. However the logic and the end result would be the same anyway. Stan > > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > for_each_dbuf_slice(slice_id) { > > /* > > @@ -490,14 +502,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > */ > > max_bw += crtc_bw->used_bw[slice_id]; > > } > > - > > - new_bw_state->min_cdclk = max_bw / 64; > > - > > - old_bw_state = intel_atomic_get_old_bw_state(state); > > } > > > > - if (!old_bw_state) > > - return 0; > > + new_bw_state->min_cdclk = max_bw / 64; > > > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > @@ -511,34 +518,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) > > { > > - int i; > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > + struct intel_bw_state *new_bw_state = NULL; > > + struct intel_bw_state *old_bw_state = NULL; > > const struct intel_crtc_state *crtc_state; > > struct intel_crtc *crtc; > > int min_cdclk = 0; > > - struct intel_bw_state *new_bw_state = NULL; > > - struct intel_bw_state *old_bw_state = NULL; > > + enum pipe pipe; > > + int i; > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > - struct intel_cdclk_state *cdclk_state; > > - > > new_bw_state = intel_atomic_get_bw_state(state); > > if (IS_ERR(new_bw_state)) > > return PTR_ERR(new_bw_state); > > > > - cdclk_state = intel_atomic_get_cdclk_state(state); > > - if (IS_ERR(cdclk_state)) > > - return PTR_ERR(cdclk_state); > > - > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > - > > - new_bw_state->min_cdclk = min_cdclk; > > - > > old_bw_state = intel_atomic_get_old_bw_state(state); > > } > > > > if (!old_bw_state) > > return 0; > > > > + for_each_pipe(dev_priv, pipe) { > > + struct intel_cdclk_state *cdclk_state; > > + > > + cdclk_state = intel_atomic_get_new_cdclk_state(state); > > + if (!cdclk_state) > > + return 0; > > + > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > + } > > + > > + new_bw_state->min_cdclk = min_cdclk; > > + > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index f9b0fc7317de..08468b121d02 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > > static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > { > > struct intel_atomic_state *state = cdclk_state->base.state; > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > + struct intel_bw_state *bw_state = NULL; > > struct intel_crtc *crtc; > > struct intel_crtc_state *crtc_state; > > int min_cdclk, i; > > + enum pipe pipe; > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > int ret; > > @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > if (min_cdclk < 0) > > return min_cdclk; > > > > + bw_state = intel_atomic_get_bw_state(state); > > + if (IS_ERR(bw_state)) > > + return PTR_ERR(bw_state); > > + > > if (cdclk_state->min_cdclk[i] == min_cdclk) > > continue; > > > > @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > } > > > > min_cdclk = cdclk_state->force_min_cdclk; > > + for_each_pipe(dev_priv, pipe) { > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > - struct intel_bw_state *bw_state; > > - > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > - > > - bw_state = intel_atomic_get_bw_state(state); > > - if (IS_ERR(bw_state)) > > - return PTR_ERR(bw_state); > > + if (!bw_state) > > + continue; > > > > min_cdclk = max(bw_state->min_cdclk, min_cdclk); > > } > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index f40b909952cc..66af8f3053ed 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > bool *need_cdclk_calc) > > { > > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > - int i; > > + struct intel_cdclk_state *new_cdclk_state; > > struct intel_plane_state *plane_state; > > + struct intel_bw_state *new_bw_state; > > struct intel_plane *plane; > > + int min_cdclk = 0; > > + enum pipe pipe; > > int ret; > > - struct intel_cdclk_state *new_cdclk_state; > > - struct intel_crtc_state *new_crtc_state; > > - struct intel_crtc *crtc; > > + int i; > > /* > > * active_planes bitmask has been updated, and potentially > > * affected planes are part of the state. We can now > > @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > if (ret) > > return ret; > > > > - if (!new_cdclk_state) > > - return 0; > > - > > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > - struct intel_bw_state *bw_state; > > - int min_cdclk = 0; > > + new_bw_state = intel_atomic_get_new_bw_state(state); > > > > - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > + if (!new_cdclk_state || !new_bw_state) > > + return 0; > > > > - bw_state = intel_atomic_get_bw_state(state); > > - if (IS_ERR(bw_state)) > > - return PTR_ERR(bw_state); > > + for_each_pipe(dev_priv, pipe) { > > + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); > > > > /* > > * Currently do this change only if we need to increase > > */ > > - if (bw_state->min_cdclk > min_cdclk) > > + if (new_bw_state->min_cdclk > min_cdclk) > > *need_cdclk_calc = true; > > } > > > > -- > > 2.24.1.485.gad05a3d8e5 > > From patchwork at emeril.freedesktop.org Mon Jun 1 07:56:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 07:56:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/36=5D_drm/i915=3A_Handle_very_early_eng?= =?utf-8?q?ine_initialisation_failure?= In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <159099818964.14891.14266739176950401576@emeril.freedesktop.org> == Series Details == Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure URL : https://patchwork.freedesktop.org/series/77857/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8560 -> Patchwork_17826 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17826 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17826, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17826/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17826: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_engines: - fi-cml-s: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/fi-cml-s/igt at i915_selftest@live at gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17826/fi-cml-s/igt at i915_selftest@live at gt_engines.html New tests --------- New tests have been introduced between CI_DRM_8560 and Patchwork_17826: ### New IGT tests (1) ### * igt at dmabuf@all at dma_fence_proxy: - Statuses : 42 pass(s) - Exec time: [0.02, 0.11] s Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-ehl-1 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8560 -> Patchwork_17826 CI-20190529: 20190529 CI_DRM_8560: 02fe287fdb4a3d6bceb1bb61b3c8538b4b941b3c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5687: 668a5be752186b6e08f361bac34da37309d08393 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17826: ac90fd42eb1dc9c16ba67d9a551bb2b3c238cd42 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ac90fd42eb1d drm/i915/gem: Bind the fence async for execbuf 9c2cdb286a07 drm/i915/gem: Asynchronous GTT unbinding d90d92d26c5c drm/i915/gem: Separate the ww_mutex walker into its own list 68f85c40ff48 drm/i915: Export a preallocate variant of i915_active_acquire() b253079dbe95 drm/i915/gem: Assign context id for async work 308d42d80cb3 drm/i915: Always defer fenced work to the worker 7cf3aad63437 drm/i915: Drop I915_IDLE_ENGINES_TIMEOUT 9675274fc27c drm/i915/gt: Declare when we enabled timeslicing 9b560a7e6079 drm/i915/gem: Allow combining submit-fences with syncobj d03f86e3977c drm/i915/gem: Teach execbuf how to wait on future syncobj dda5123316b5 drm/syncobj: Allow use of dma-fence-proxy f3cd5ea0ff2c drm/i915/gem: Make relocations atomic within execbuf 06d2116fd5f4 drm/i915: Unpeel awaits on a proxy fence 6b9cc101590e dma-buf: Proxy fence, an unsignaled fence placeholder 710af09a4672 drm/i915/gem: Add all GPU reloc awaits/signals en masse 6f01210067aa drm/i915/gem: Build the reloc request first c26758f43cfe drm/i915/gem: Lift GPU relocation allocation b2abfeed9589 drm/i915/gem: Separate reloc validation into an earlier step 9b9d4aa5ab50 drm/i915: Add list_for_each_entry_safe_continue_reverse 033b56b47071 drm/i915/gem: Async GPU relocations only 143d1995d466 drm/i915/gem: Mark the buffer pool as active for the cmdparser 3148cd01132a drm/i915/gt: Enable ring scheduling for gen6/7 8c829f7c5554 drm/i915/gt: Implement ring scheduler for gen6/7 99a81a3f55b0 drm/i915: Relinquish forcewake immediately after manual grouping 118524c684c6 drm/i915/gt: Track if an engine requires forcewake w/a 0760ab97f627 drm/i915/gt: Enable busy-stats for ring-scheduler 15787ec4da9d drm/i915/gt: Infrastructure for ring scheduling 703dea6710a7 drm/i915: Support inter-engine semaphores on gen6/7 58305c0b593a drm/i915/gt: Use client timeline address for seqno writes eacfbfb97087 drm/i915/gt: Support creation of 'internal' rings ce9a7aebf8d2 drm/i915/gt: Couple tasklet scheduling for all CS interrupts cf0807656a76 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" 5b9d253c3510 drm/i915: Trim the ironlake+ irq handler 8f9e2ddc2328 drm/i915/gt: Move legacy context wa to intel_workarounds 284e5e82f9e8 drm/i915/gt: Split low level gen2-7 CS emitters 96d738818236 drm/i915: Handle very early engine initialisation failure == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17826/index.html From stanislav.lisovskiy at intel.com Mon Jun 1 07:59:29 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Mon, 1 Jun 2020 10:59:29 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix global state use-after-frees with a refcount In-Reply-To: <20200529051143.GD6112@intel.com> References: <20200527200245.13184-1-ville.syrjala@linux.intel.com> <20200528193852.GA24971@intel.com> <20200528195852.GA25073@intel.com> <20200529051143.GD6112@intel.com> Message-ID: <20200601075929.GA2431@intel.com> On Fri, May 29, 2020 at 08:11:43AM +0300, Ville Syrj?l? wrote: > On Thu, May 28, 2020 at 10:58:52PM +0300, Lisovskiy, Stanislav wrote: > > On Thu, May 28, 2020 at 10:38:52PM +0300, Lisovskiy, Stanislav wrote: > > > On Wed, May 27, 2020 at 11:02:45PM +0300, Ville Syrjala wrote: > > > > From: Ville Syrj?l? > > > > > > > > While the current locking/serialization of the global state > > > > suffices for protecting the obj->state access and the actual > > > > hardware reprogramming, we do have a problem with accessing > > > > the old/new states during nonblocking commits. > > > > > > > > The state computation and swap will be protected by the crtc > > > > locks, but the commit_tails can finish out of order, thus also > > > > causing the atomic states to be cleaned up out of order. This > > > > would mean the commit that started first but finished last has > > > > had its new state freed as the no-longer-needed old state by the > > > > other commit. > > > > > > > > To fix this let's just refcount the states. obj->state amounts > > > > to one reference, and the intel_atomic_state holds extra references > > > > to both its new and old global obj states. > > > > > > > > Fixes: 0ef1905ecf2e ("drm/i915: Introduce better global state handling") > > > > Signed-off-by: Ville Syrj?l? > > > > --- > > > > .../gpu/drm/i915/display/intel_global_state.c | 45 ++++++++++++++++--- > > > > .../gpu/drm/i915/display/intel_global_state.h | 3 ++ > > > > 2 files changed, 42 insertions(+), 6 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c > > > > index 212d4ee68205..7a19215ad844 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_global_state.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_global_state.c > > > > @@ -10,6 +10,28 @@ > > > > #include "intel_display_types.h" > > > > #include "intel_global_state.h" > > > > > > > > +static void __intel_atomic_global_state_free(struct kref *kref) > > > > +{ > > > > + struct intel_global_state *obj_state = > > > > + container_of(kref, struct intel_global_state, ref); > > > > + struct intel_global_obj *obj = obj_state->obj; > > > > + > > > > + obj->funcs->atomic_destroy_state(obj, obj_state); > > > > +} > > > > + > > > > +static void intel_atomic_global_state_put(struct intel_global_state *obj_state) > > > > +{ > > > > + kref_put(&obj_state->ref, __intel_atomic_global_state_free); > > > > +} > > > > + > > > > +static struct intel_global_state * > > > > +intel_atomic_global_state_get(struct intel_global_state *obj_state) > > > > +{ > > > > + kref_get(&obj_state->ref); > > > > + > > > > + return obj_state; > > > > +} > > > > + > > > > void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, > > > > struct intel_global_obj *obj, > > > > struct intel_global_state *state, > > > > @@ -17,6 +39,10 @@ void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, > > > > { > > > > memset(obj, 0, sizeof(*obj)); > > > > > > > > + state->obj = obj; > > > > + > > > > + kref_init(&state->ref); > > > > + > > > > obj->state = state; > > > > obj->funcs = funcs; > > > > list_add_tail(&obj->head, &dev_priv->global_obj_list); > > > > @@ -28,7 +54,9 @@ void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv) > > > > > > > > list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) { > > > > list_del(&obj->head); > > > > - obj->funcs->atomic_destroy_state(obj, obj->state); > > > > + > > > > + drm_WARN_ON(&dev_priv->drm, kref_read(&obj->state->ref) != 1); > > > > + intel_atomic_global_state_put(obj->state); > > > > } > > > > } > > > > > > > > @@ -97,10 +125,14 @@ intel_atomic_get_global_obj_state(struct intel_atomic_state *state, > > > > if (!obj_state) > > > > return ERR_PTR(-ENOMEM); > > > > > > > > + obj_state->obj = obj; > > > > obj_state->changed = false; > > > > > > > > + kref_init(&obj_state->ref); > > > > + > > > > state->global_objs[index].state = obj_state; > > > > - state->global_objs[index].old_state = obj->state; > > > > + state->global_objs[index].old_state = > > > > + intel_atomic_global_state_get(obj->state); > > > > state->global_objs[index].new_state = obj_state; > > > > state->global_objs[index].ptr = obj; > > > > obj_state->state = state; > > > > @@ -163,7 +195,9 @@ void intel_atomic_swap_global_state(struct intel_atomic_state *state) > > > > new_obj_state->state = NULL; > > > > > > > > state->global_objs[i].state = old_obj_state; > > > > - obj->state = new_obj_state; > > > > + > > > > + intel_atomic_global_state_put(obj->state); > > > > + obj->state = intel_atomic_global_state_get(new_obj_state); > > > > } > > > > } > > > > > > > > @@ -172,10 +206,9 @@ void intel_atomic_clear_global_state(struct intel_atomic_state *state) > > > > int i; > > > > > > > > for (i = 0; i < state->num_global_objs; i++) { > > > > - struct intel_global_obj *obj = state->global_objs[i].ptr; > > > > + intel_atomic_global_state_put(state->global_objs[i].old_state); > > > > + intel_atomic_global_state_put(state->global_objs[i].new_state); > > > > > > Shouldn't we clean old_state only? > > > > > > As I understand in absence of any transaction you now have a pool of > > > global_obj each has a state with single kref taken. > > > > > > So when we are going to get a new state, we do +1 kref to old_state(which is current global obj->state) > > > in order to prevent it being cleared by competing commit. > > > However the new state doesn't have any kref taken by that moment. > > > Then you swap do -1 kref for the old state and do +1 kref for new state, > > > which means that when you -1 kref again for old state in atomic_clear also, > > > it will be destroyed, however regarding the new state, as I understand > > > it still has only single kref grabbed when it was swapped, > > > so isn't it going to be now removed? unless we are lucky and somebody > > > haven't grabbed it already as an old_state in the next commit? > > > > > > Stan > > > > Ah actually I got it - forgot that kref is init as 1. > > But then you probably don't even need to increment kref for new state > > when swapping. > > Before assigning new obj->state you release one kref in swap(which makes sense) > > Then you just do only intel_atomic_global_state_put(old_state) in atomic_clear > > and then no need in doing intel_atomic_global_state_get(new_state) during > > swap. > > I.e we always call intel_atomic_global_state_get/put only regarding "old" > > obj->state and each new_state will be disposed when it becomes old_state. > > > IMO the approach of handing off references is just hard to follow. > Better to just get/put explicitly whenever you assign a pointer. > I already dislike handing off the original kref_init() reference, > and almost added a get+put there too. Maybe I really should do that... Agree, tbh I don't like the idea that kref_init already implicitly holds a reference - it even confused me initially. Typical smartpointer usually increments the ref only when assignment is done. Reviewed-by: Stanislav Lisovskiy > > > > > Stan > > > > > > > > > > - obj->funcs->atomic_destroy_state(obj, > > > > - state->global_objs[i].state); > > > > state->global_objs[i].ptr = NULL; > > > > state->global_objs[i].state = NULL; > > > > state->global_objs[i].old_state = NULL; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h > > > > index e6163a469029..1f16fa3073c9 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_global_state.h > > > > +++ b/drivers/gpu/drm/i915/display/intel_global_state.h > > > > @@ -6,6 +6,7 @@ > > > > #ifndef __INTEL_GLOBAL_STATE_H__ > > > > #define __INTEL_GLOBAL_STATE_H__ > > > > > > > > +#include > > > > #include > > > > > > > > struct drm_i915_private; > > > > @@ -54,7 +55,9 @@ struct intel_global_obj { > > > > for_each_if(obj) > > > > > > > > struct intel_global_state { > > > > + struct intel_global_obj *obj; > > > > struct intel_atomic_state *state; > > > > + struct kref ref; > > > > bool changed; > > > > }; > > > > > > > > -- > > > > 2.26.2 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx at lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From chris at chris-wilson.co.uk Mon Jun 1 08:03:26 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 09:03:26 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Enable busy-stats for ring-scheduler In-Reply-To: <20200601072446.19548-11-chris@chris-wilson.co.uk> References: <20200601072446.19548-11-chris@chris-wilson.co.uk> Message-ID: <20200601080326.28384-1-chris@chris-wilson.co.uk> Couple up the context in/out accounting to record how long each engine is busy handling requests. This is exposed to userspace for more accurate measurements, and also enables our soft-rps timer. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------ .../gpu/drm/i915/gt/intel_ring_scheduler.c | 4 + drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 90 +++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ 5 files changed, 149 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include +#include +#include + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6fc0966b75ff..13ef4f58cb08 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1187,39 +1188,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index c8cd435d1c51..aaff554865b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_context.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -59,6 +60,7 @@ static struct i915_request * schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) { __intel_gt_pm_get(engine->gt); + intel_engine_context_in(engine); return i915_request_get(rq); } @@ -71,6 +73,7 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) intel_engine_add_retire(engine, ce->timeline); i915_request_put(rq); + intel_engine_context_out(engine); intel_gt_pm_put_async(engine->gt); } @@ -747,6 +750,7 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) engine->legacy.ring = ring; engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; + engine->flags |= I915_ENGINE_SUPPORTS_STATS; /* Finally, take ownership and responsibility for cleanup! */ engine->release = ring_release; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..64cfa2fdc9bf 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,95 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t dt, de; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + break; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (100 * de < 95 * dt) { + pr_err("%s: reported only %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + igt_spinner_fini(&spin); + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +166,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 1 08:23:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 08:23:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Add_Plane_color_encoding_support_for_YCBCR=5FBT2020_?= =?utf-8?b?KHJldjYp?= In-Reply-To: <20200601073544.11291-1-kishore.kadiyala@intel.com> References: <20200601073544.11291-1-kishore.kadiyala@intel.com> Message-ID: <159099981801.14888.15973783215975147663@emeril.freedesktop.org> == Series Details == Series: drm/i915: Add Plane color encoding support for YCBCR_BT2020 (rev6) URL : https://patchwork.freedesktop.org/series/75660/ State : success == Summary == CI Bug Log - changes from CI_DRM_8560 -> Patchwork_17827 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/index.html Known issues ------------ Here are the changes found in Patchwork_17827 that come from known issues: ### IGT changes ### #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][1] ([fdo#109271]) -> [FAIL][2] ([i915#62] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-ehl-1 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8560 -> Patchwork_17827 CI-20190529: 20190529 CI_DRM_8560: 02fe287fdb4a3d6bceb1bb61b3c8538b4b941b3c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5687: 668a5be752186b6e08f361bac34da37309d08393 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17827: 2d67bb8cef9491f3109c6c2dbc237b5cff273ebb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2d67bb8cef94 drm/i915: Add Plane color encoding support for YCBCR_BT2020 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/index.html From patchwork at emeril.freedesktop.org Mon Jun 1 08:30:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 08:30:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/36=5D_drm/i915=3A_Handle_very_ea?= =?utf-8?q?rly_engine_initialisation_failure_=28rev2=29?= In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <159100020498.14889.16427392041989155909@emeril.freedesktop.org> == Series Details == Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure (rev2) URL : https://patchwork.freedesktop.org/series/77857/ State : warning == Summary == $ dim checkpatch origin/drm-tip b0896ff73ea4 drm/i915: Handle very early engine initialisation failure 28f59054aa9e drm/i915/gt: Split low level gen2-7 CS emitters -:9: WARNING:TYPO_SPELLING: 'wnat' may be misspelled - perhaps 'want'? #9: with requests, and we will wnat to reuse them outside of this context. -:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #27: new file mode 100644 -:179: WARNING:LONG_LINE: line over 100 characters #179: FILE: drivers/gpu/drm/i915/gt/gen2_engine_cs.c:148: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:202: WARNING:LONG_LINE: line over 100 characters #202: FILE: drivers/gpu/drm/i915/gt/gen2_engine_cs.c:171: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:220: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #220: FILE: drivers/gpu/drm/i915/gt/gen2_engine_cs.c:189: +} +#undef GEN5_WA_STORES -:798: WARNING:LONG_LINE: line over 100 characters #798: FILE: drivers/gpu/drm/i915/gt/gen6_engine_cs.c:377: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:818: WARNING:LONG_LINE: line over 100 characters #818: FILE: drivers/gpu/drm/i915/gt/gen6_engine_cs.c:397: + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); -:843: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #843: FILE: drivers/gpu/drm/i915/gt/gen6_engine_cs.c:422: +} +#undef GEN7_XCS_WA total: 0 errors, 6 warnings, 2 checks, 1812 lines checked 84fb5312e69a drm/i915/gt: Move legacy context wa to intel_workarounds 51c5e9106b00 drm/i915: Trim the ironlake+ irq handler db08f3a83b7d Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" ee444a1c9757 drm/i915/gt: Couple tasklet scheduling for all CS interrupts a186650cc2c0 drm/i915/gt: Support creation of 'internal' rings ad2ec515e737 drm/i915/gt: Use client timeline address for seqno writes 75a19e638ad6 drm/i915: Support inter-engine semaphores on gen6/7 9c8572c7a931 drm/i915/gt: Infrastructure for ring scheduling -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 842 lines checked 5354a72cf88c drm/i915/gt: Enable busy-stats for ring-scheduler -:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #13: new file mode 100644 -:200: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #200: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:47: + udelay(100); -:230: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #230: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:77: + udelay(100); total: 0 errors, 1 warnings, 2 checks, 236 lines checked ad2a6b63bf64 drm/i915/gt: Track if an engine requires forcewake w/a e43d3f056a59 drm/i915: Relinquish forcewake immediately after manual grouping e4172f511dc0 drm/i915/gt: Implement ring scheduler for gen6/7 -:68: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #68: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:324: + *cs++ = i915_mmio_reg_offset( -:70: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #70: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:326: + *cs++ = _MASKED_BIT_ENABLE( -:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #105: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:361: + *cs++ = _MASKED_BIT_DISABLE( total: 0 errors, 0 warnings, 3 checks, 512 lines checked 8f4228e0458d drm/i915/gt: Enable ring scheduling for gen6/7 4223614bdbed drm/i915/gem: Mark the buffer pool as active for the cmdparser 043a8c092764 drm/i915/gem: Async GPU relocations only d6bb9bf39a67 drm/i915: Add list_for_each_entry_safe_continue_reverse -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) total: 0 errors, 0 warnings, 3 checks, 12 lines checked bf626d095a0a drm/i915/gem: Separate reloc validation into an earlier step -:101: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return #101: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1408: + return (int)offset; + } else { total: 0 errors, 1 warnings, 0 checks, 217 lines checked a5a8005dc0d5 drm/i915/gem: Lift GPU relocation allocation cf3caf6ea48e drm/i915/gem: Build the reloc request first b5ed91ed9028 drm/i915/gem: Add all GPU reloc awaits/signals en masse 3d075ea5bad9 dma-buf: Proxy fence, an unsignaled fence placeholder -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 -:438: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #438: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20: + spinlock_t lock; total: 0 errors, 1 warnings, 1 checks, 1158 lines checked ce15d9f7f287 drm/i915: Unpeel awaits on a proxy fence 7f48f9f9cabb drm/i915/gem: Make relocations atomic within execbuf 59c00fdc9150 drm/syncobj: Allow use of dma-fence-proxy 9f06244959ca drm/i915/gem: Teach execbuf how to wait on future syncobj fe5ce9a4c96f drm/i915/gem: Allow combining submit-fences with syncobj 0f995d2bfbe2 drm/i915/gt: Declare when we enabled timeslicing 796d8967ce3e drm/i915: Drop I915_IDLE_ENGINES_TIMEOUT 30672d041d30 drm/i915: Always defer fenced work to the worker f86a694d1a36 drm/i915/gem: Assign context id for async work e8d99d37c64d drm/i915: Export a preallocate variant of i915_active_acquire() 8ed22b7514d8 drm/i915/gem: Separate the ww_mutex walker into its own list 55b772ca8526 drm/i915/gem: Asynchronous GTT unbinding d2ba95a40d8a drm/i915/gem: Bind the fence async for execbuf From patchwork at emeril.freedesktop.org Mon Jun 1 08:31:27 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 08:31:27 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/36=5D_drm/i915=3A_Handle_very_early_?= =?utf-8?q?engine_initialisation_failure_=28rev2=29?= In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <159100028757.14891.10206983541402300325@emeril.freedesktop.org> == Series Details == Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure (rev2) URL : https://patchwork.freedesktop.org/series/77857/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y From patchwork at emeril.freedesktop.org Mon Jun 1 08:51:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 08:51:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/36=5D_drm/i915=3A_Handle_very_early_eng?= =?utf-8?q?ine_initialisation_failure_=28rev2=29?= In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <159100149713.14889.17017104724943724988@emeril.freedesktop.org> == Series Details == Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure (rev2) URL : https://patchwork.freedesktop.org/series/77857/ State : success == Summary == CI Bug Log - changes from CI_DRM_8560 -> Patchwork_17828 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/index.html New tests --------- New tests have been introduced between CI_DRM_8560 and Patchwork_17828: ### New IGT tests (1) ### * igt at dmabuf@all at dma_fence_proxy: - Statuses : 42 pass(s) - Exec time: [0.03, 0.10] s Changes ------- No changes found Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-ehl-1 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8560 -> Patchwork_17828 CI-20190529: 20190529 CI_DRM_8560: 02fe287fdb4a3d6bceb1bb61b3c8538b4b941b3c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5687: 668a5be752186b6e08f361bac34da37309d08393 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17828: d2ba95a40d8a1c2731ac575e5183770cbb118343 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d2ba95a40d8a drm/i915/gem: Bind the fence async for execbuf 55b772ca8526 drm/i915/gem: Asynchronous GTT unbinding 8ed22b7514d8 drm/i915/gem: Separate the ww_mutex walker into its own list e8d99d37c64d drm/i915: Export a preallocate variant of i915_active_acquire() f86a694d1a36 drm/i915/gem: Assign context id for async work 30672d041d30 drm/i915: Always defer fenced work to the worker 796d8967ce3e drm/i915: Drop I915_IDLE_ENGINES_TIMEOUT 0f995d2bfbe2 drm/i915/gt: Declare when we enabled timeslicing fe5ce9a4c96f drm/i915/gem: Allow combining submit-fences with syncobj 9f06244959ca drm/i915/gem: Teach execbuf how to wait on future syncobj 59c00fdc9150 drm/syncobj: Allow use of dma-fence-proxy 7f48f9f9cabb drm/i915/gem: Make relocations atomic within execbuf ce15d9f7f287 drm/i915: Unpeel awaits on a proxy fence 3d075ea5bad9 dma-buf: Proxy fence, an unsignaled fence placeholder b5ed91ed9028 drm/i915/gem: Add all GPU reloc awaits/signals en masse cf3caf6ea48e drm/i915/gem: Build the reloc request first a5a8005dc0d5 drm/i915/gem: Lift GPU relocation allocation bf626d095a0a drm/i915/gem: Separate reloc validation into an earlier step d6bb9bf39a67 drm/i915: Add list_for_each_entry_safe_continue_reverse 043a8c092764 drm/i915/gem: Async GPU relocations only 4223614bdbed drm/i915/gem: Mark the buffer pool as active for the cmdparser 8f4228e0458d drm/i915/gt: Enable ring scheduling for gen6/7 e4172f511dc0 drm/i915/gt: Implement ring scheduler for gen6/7 e43d3f056a59 drm/i915: Relinquish forcewake immediately after manual grouping ad2a6b63bf64 drm/i915/gt: Track if an engine requires forcewake w/a 5354a72cf88c drm/i915/gt: Enable busy-stats for ring-scheduler 9c8572c7a931 drm/i915/gt: Infrastructure for ring scheduling 75a19e638ad6 drm/i915: Support inter-engine semaphores on gen6/7 ad2ec515e737 drm/i915/gt: Use client timeline address for seqno writes a186650cc2c0 drm/i915/gt: Support creation of 'internal' rings ee444a1c9757 drm/i915/gt: Couple tasklet scheduling for all CS interrupts db08f3a83b7d Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" 51c5e9106b00 drm/i915: Trim the ironlake+ irq handler 84fb5312e69a drm/i915/gt: Move legacy context wa to intel_workarounds 28f59054aa9e drm/i915/gt: Split low level gen2-7 CS emitters b0896ff73ea4 drm/i915: Handle very early engine initialisation failure == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/index.html From patchwork at emeril.freedesktop.org Mon Jun 1 10:00:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 10:00:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915=3A_Add_Plane_color_encoding_support_for_YCBCR=5FBT2020_?= =?utf-8?b?KHJldjYp?= In-Reply-To: <20200601073544.11291-1-kishore.kadiyala@intel.com> References: <20200601073544.11291-1-kishore.kadiyala@intel.com> Message-ID: <159100563340.14889.15295626645155238490@emeril.freedesktop.org> == Series Details == Series: drm/i915: Add Plane color encoding support for YCBCR_BT2020 (rev6) URL : https://patchwork.freedesktop.org/series/75660/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8560_full -> Patchwork_17827_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17827_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17827_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17827_full: ### IGT changes ### #### Possible regressions #### * igt at gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs: - shard-apl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl4/igt at gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_ctx_isolation@preservation-s3 at vecs0}: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb8/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb3/igt at gem_ctx_isolation@preservation-s3 at vecs0.html Known issues ------------ Here are the changes found in Patchwork_17827_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-apl: [PASS][5] -> [TIMEOUT][6] ([i915#1635]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl4/igt at kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb1/igt at kms_psr@psr2_primary_mmap_gtt.html #### Possible fixes #### * igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-apl: [FAIL][13] ([i915#54]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl7/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][17] ([i915#72]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-glk9/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-glk7/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * {igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1}: - shard-skl: [FAIL][21] ([i915#1928]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl5/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][23] ([i915#1188]) -> [PASS][24] +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - shard-skl: [FAIL][25] ([i915#53]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl5/igt at kms_pipe_crc_basic@read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][27] ([fdo#108145] / [i915#265]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][29] ([fdo#109441]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb8/igt at kms_psr@psr2_cursor_render.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-kbl: [INCOMPLETE][31] ([i915#155]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl3/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-kbl2/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html * {igt at perf@polling-parameterized}: - shard-iclb: [FAIL][33] ([i915#1542]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb6/igt at perf@polling-parameterized.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb2/igt at perf@polling-parameterized.html #### Warnings #### * igt at kms_content_protection@lic: - shard-apl: [FAIL][35] ([fdo#110321]) -> [TIMEOUT][36] ([i915#1319] / [i915#1635]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl2/igt at kms_content_protection@lic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl2/igt at kms_content_protection@lic.html * igt at kms_cursor_legacy@2x-flip-vs-cursor-atomic: - shard-apl: [SKIP][37] ([fdo#109271]) -> [TIMEOUT][38] ([i915#1635]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_cursor_legacy@2x-flip-vs-cursor-atomic.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl4/igt at kms_cursor_legacy@2x-flip-vs-cursor-atomic.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [FAIL][39] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][40] ([fdo#108145] / [i915#265]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8560 -> Patchwork_17827 CI-20190529: 20190529 CI_DRM_8560: 02fe287fdb4a3d6bceb1bb61b3c8538b4b941b3c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5687: 668a5be752186b6e08f361bac34da37309d08393 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17827: 2d67bb8cef9491f3109c6c2dbc237b5cff273ebb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/index.html From anshuman.gupta at intel.com Mon Jun 1 10:15:16 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Mon, 1 Jun 2020 15:45:16 +0530 Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs Message-ID: <20200601101516.21018-1-anshuman.gupta@intel.com> Gen12 hw are failing to enable lpsp configuration due to PG3 was left on due to valid usgae count of POWER_DOMAIN_AUDIO. It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling a crtc, it should be always i915_audio_component request to get/put AUDIO_POWER_DOMAIN. Cc: stable at vger.kernel.org Cc: Ville Syrj?l? Cc: Maarten Lankhorst Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6c3b11de2daf..f31a579d7a52 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) mask |= BIT_ULL(intel_encoder->power_domain); } - if (HAS_DDI(dev_priv) && crtc_state->has_audio) + /* + * Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to + * enable AUDIO power in order to enable a crtc. + */ + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && crtc_state->has_audio) mask |= BIT_ULL(POWER_DOMAIN_AUDIO); if (crtc_state->shared_dpll) -- 2.26.2 From patchwork at emeril.freedesktop.org Mon Jun 1 11:00:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 11:00:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/36=5D_drm/i915=3A_Handle_very_early_eng?= =?utf-8?q?ine_initialisation_failure_=28rev2=29?= In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <159100924007.14888.836552676635186270@emeril.freedesktop.org> == Series Details == Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure (rev2) URL : https://patchwork.freedesktop.org/series/77857/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8560_full -> Patchwork_17828_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17828_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17828_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17828_full: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - shard-hsw: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw6/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_fence@parallel at vecs0}: - shard-hsw: [PASS][2] -> [FAIL][3] +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-hsw1/igt at gem_exec_fence@parallel at vecs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw2/igt at gem_exec_fence@parallel at vecs0.html * {igt at gem_exec_fence@syncobj-invalid-wait}: - shard-snb: [PASS][4] -> [FAIL][5] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-snb5/igt at gem_exec_fence@syncobj-invalid-wait.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-snb5/igt at gem_exec_fence@syncobj-invalid-wait.html - shard-tglb: [PASS][6] -> [FAIL][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-tglb6/igt at gem_exec_fence@syncobj-invalid-wait.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-tglb8/igt at gem_exec_fence@syncobj-invalid-wait.html - shard-skl: [PASS][8] -> [FAIL][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl8/igt at gem_exec_fence@syncobj-invalid-wait.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl8/igt at gem_exec_fence@syncobj-invalid-wait.html - shard-glk: [PASS][10] -> [FAIL][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-glk6/igt at gem_exec_fence@syncobj-invalid-wait.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-glk1/igt at gem_exec_fence@syncobj-invalid-wait.html - shard-apl: [PASS][12] -> [FAIL][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl1/igt at gem_exec_fence@syncobj-invalid-wait.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-apl1/igt at gem_exec_fence@syncobj-invalid-wait.html - shard-kbl: [PASS][14] -> [FAIL][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl3/igt at gem_exec_fence@syncobj-invalid-wait.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-kbl4/igt at gem_exec_fence@syncobj-invalid-wait.html - shard-iclb: [PASS][16] -> [FAIL][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb2/igt at gem_exec_fence@syncobj-invalid-wait.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-iclb2/igt at gem_exec_fence@syncobj-invalid-wait.html New tests --------- New tests have been introduced between CI_DRM_8560_full and Patchwork_17828_full: ### New IGT tests (1) ### * igt at dmabuf@all at dma_fence_proxy: - Statuses : 8 pass(s) - Exec time: [0.04, 0.10] s Known issues ------------ Here are the changes found in Patchwork_17828_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_param@set-priority-not-supported: - shard-snb: [PASS][18] -> [SKIP][19] ([fdo#109271]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-snb5/igt at gem_ctx_param@set-priority-not-supported.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-snb1/igt at gem_ctx_param@set-priority-not-supported.html - shard-hsw: [PASS][20] -> [SKIP][21] ([fdo#109271]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-hsw1/igt at gem_ctx_param@set-priority-not-supported.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw2/igt at gem_ctx_param@set-priority-not-supported.html * igt at i915_pm_rps@waitboost: - shard-hsw: [PASS][22] -> [FAIL][23] ([i915#39]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-hsw1/igt at i915_pm_rps@waitboost.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw2/igt at i915_pm_rps@waitboost.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][24] -> [INCOMPLETE][25] ([i915#300]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl6/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_legacy@2x-cursor-vs-flip-atomic: - shard-glk: [PASS][26] -> [INCOMPLETE][27] ([i915#58] / [k.org#198133]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-glk2/igt at kms_cursor_legacy@2x-cursor-vs-flip-atomic.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-glk9/igt at kms_cursor_legacy@2x-cursor-vs-flip-atomic.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +2 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][30] -> [FAIL][31] ([fdo#108145] / [i915#265]) +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#109441]) +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-iclb4/igt at kms_psr@psr2_primary_mmap_gtt.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-tglb: [FAIL][34] ([i915#1930]) -> [PASS][35] +1 similar issue [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-tglb1/igt at gem_exec_reloc@basic-concurrent0.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-tglb7/igt at gem_exec_reloc@basic-concurrent0.html - shard-hsw: [FAIL][36] ([i915#1930]) -> [PASS][37] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-hsw2/igt at gem_exec_reloc@basic-concurrent0.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw1/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [FAIL][38] ([i915#1930]) -> [PASS][39] +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html - shard-iclb: [FAIL][40] ([i915#1930]) -> [PASS][41] +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb3/igt at gem_exec_reloc@basic-concurrent16.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-iclb8/igt at gem_exec_reloc@basic-concurrent16.html - shard-skl: [FAIL][42] ([i915#1930]) -> [PASS][43] +1 similar issue [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at gem_exec_reloc@basic-concurrent16.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl4/igt at gem_exec_reloc@basic-concurrent16.html - shard-kbl: [FAIL][44] ([i915#1930]) -> [PASS][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl4/igt at gem_exec_reloc@basic-concurrent16.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-kbl6/igt at gem_exec_reloc@basic-concurrent16.html - shard-apl: [FAIL][46] ([i915#1930]) -> [PASS][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at gem_exec_reloc@basic-concurrent16.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-hsw: [SKIP][48] ([fdo#109271]) -> [PASS][49] +34 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-hsw2/igt at gem_exec_whisper@basic-contexts-priority-all.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw5/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-apl: [FAIL][50] ([i915#54]) -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-apl2/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][52] ([i915#180]) -> [PASS][53] +2 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][54] ([i915#72]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-glk9/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-glk8/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * {igt at kms_flip@2x-flip-vs-absolute-wf_vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][56] ([i915#1928]) -> [PASS][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-glk1/igt at kms_flip@2x-flip-vs-absolute-wf_vblank at ab-hdmi-a1-hdmi-a2.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-glk4/igt at kms_flip@2x-flip-vs-absolute-wf_vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][58] ([i915#180]) -> [PASS][59] +7 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-apl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * {igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1}: - shard-skl: [FAIL][60] ([i915#1928]) -> [PASS][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl4/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][62] ([i915#1188]) -> [PASS][63] +1 similar issue [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl3/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - shard-skl: [FAIL][64] ([i915#53]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl4/igt at kms_pipe_crc_basic@read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][66] ([fdo#108145] / [i915#265]) -> [PASS][67] +2 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][68] ([fdo#109642] / [fdo#111068]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb7/igt at kms_psr2_su@frontbuffer.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][70] ([fdo#109441]) -> [PASS][71] +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb6/igt at kms_psr@psr2_cursor_plane_move.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-kbl: [INCOMPLETE][72] ([i915#155]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl3/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-kbl1/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html * {igt at perf@polling-parameterized}: - shard-iclb: [FAIL][74] ([i915#1542]) -> [PASS][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb6/igt at perf@polling-parameterized.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-iclb8/igt at perf@polling-parameterized.html * {igt at perf_pmu@busy-accuracy-2 at bcs0}: - shard-snb: [SKIP][76] ([fdo#109271]) -> [PASS][77] +33 similar issues [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-snb5/igt at perf_pmu@busy-accuracy-2 at bcs0.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-snb6/igt at perf_pmu@busy-accuracy-2 at bcs0.html #### Warnings #### * igt at kms_content_protection@lic: - shard-apl: [FAIL][78] ([fdo#110321]) -> [TIMEOUT][79] ([i915#1319] / [i915#1635]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl2/igt at kms_content_protection@lic.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-apl8/igt at kms_content_protection@lic.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][80] ([i915#1188]) -> [INCOMPLETE][81] ([i915#198]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8560 -> Patchwork_17828 CI-20190529: 20190529 CI_DRM_8560: 02fe287fdb4a3d6bceb1bb61b3c8538b4b941b3c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5687: 668a5be752186b6e08f361bac34da37309d08393 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17828: d2ba95a40d8a1c2731ac575e5183770cbb118343 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/index.html From patchwork at emeril.freedesktop.org Mon Jun 1 11:06:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 11:06:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Add_Plane_color_encoding_support_for_YCBCR=5FBT2020_?= =?utf-8?b?KHJldjYp?= In-Reply-To: <20200601073544.11291-1-kishore.kadiyala@intel.com> References: <20200601073544.11291-1-kishore.kadiyala@intel.com> Message-ID: <159100957062.14889.5601085746735229343@emeril.freedesktop.org> == Series Details == Series: drm/i915: Add Plane color encoding support for YCBCR_BT2020 (rev6) URL : https://patchwork.freedesktop.org/series/75660/ State : success == Summary == CI Bug Log - changes from CI_DRM_8560_full -> Patchwork_17827_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17827_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_ctx_isolation@preservation-s3 at vecs0}: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb8/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb3/igt at gem_ctx_isolation@preservation-s3 at vecs0.html Known issues ------------ Here are the changes found in Patchwork_17827_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs: - shard-apl: [PASS][3] -> [INCOMPLETE][4] ([i915#1635]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl4/igt at gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html * igt at kms_cursor_crc@pipe-b-cursor-64x21-offscreen: - shard-apl: [PASS][5] -> [TIMEOUT][6] ([i915#1635]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl4/igt at kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb1/igt at kms_psr@psr2_primary_mmap_gtt.html #### Possible fixes #### * igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-apl: [FAIL][13] ([i915#54]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl7/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][17] ([i915#72]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-glk9/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-glk7/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * {igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1}: - shard-skl: [FAIL][21] ([i915#1928]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl5/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][23] ([i915#1188]) -> [PASS][24] +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - shard-skl: [FAIL][25] ([i915#53]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl5/igt at kms_pipe_crc_basic@read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][27] ([fdo#108145] / [i915#265]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][29] ([fdo#109441]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb8/igt at kms_psr@psr2_cursor_render.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-kbl: [INCOMPLETE][31] ([i915#155]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-kbl3/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-kbl2/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html * {igt at perf@polling-parameterized}: - shard-iclb: [FAIL][33] ([i915#1542]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-iclb6/igt at perf@polling-parameterized.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-iclb2/igt at perf@polling-parameterized.html #### Warnings #### * igt at kms_content_protection@lic: - shard-apl: [FAIL][35] ([fdo#110321]) -> [TIMEOUT][36] ([i915#1319] / [i915#1635]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl2/igt at kms_content_protection@lic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl2/igt at kms_content_protection@lic.html * igt at kms_cursor_legacy@2x-flip-vs-cursor-atomic: - shard-apl: [SKIP][37] ([fdo#109271]) -> [TIMEOUT][38] ([i915#1635]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_cursor_legacy@2x-flip-vs-cursor-atomic.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl4/igt at kms_cursor_legacy@2x-flip-vs-cursor-atomic.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [FAIL][39] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][40] ([fdo#108145] / [i915#265]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-apl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8560 -> Patchwork_17827 CI-20190529: 20190529 CI_DRM_8560: 02fe287fdb4a3d6bceb1bb61b3c8538b4b941b3c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5687: 668a5be752186b6e08f361bac34da37309d08393 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17827: 2d67bb8cef9491f3109c6c2dbc237b5cff273ebb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17827/index.html From patchwork at emeril.freedesktop.org Mon Jun 1 11:23:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 11:23:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_lpsp_with_hdmi/dp_outputs?= In-Reply-To: <20200601101516.21018-1-anshuman.gupta@intel.com> References: <20200601101516.21018-1-anshuman.gupta@intel.com> Message-ID: <159101060399.14888.16731273797339898647@emeril.freedesktop.org> == Series Details == Series: drm/i915: lpsp with hdmi/dp outputs URL : https://patchwork.freedesktop.org/series/77866/ State : success == Summary == CI Bug Log - changes from CI_DRM_8561 -> Patchwork_17829 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/index.html Changes ------- No changes found Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8561 -> Patchwork_17829 CI-20190529: 20190529 CI_DRM_8561: 989e079eb7172d7423686cab0dd5d4e47a48f3e1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5688: 33c8411480b4945e44188f82cd6c3a0d53b40485 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17829: 78f04fcced9a26b870739cbc213801bd1b570606 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 78f04fcced9a drm/i915: lpsp with hdmi/dp outputs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/index.html From mika.kuoppala at linux.intel.com Mon Jun 1 11:31:34 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 01 Jun 2020 14:31:34 +0300 Subject: [Intel-gfx] [PATCH 01/36] drm/i915: Handle very early engine initialisation failure In-Reply-To: <20200601072446.19548-1-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> Message-ID: <87pnajhvjd.fsf@gaia.fi.intel.com> Chris Wilson writes: > If we fail during engine setup, we may leave some engines not yet setup. > During the error cleanup, we have to be careful not to try and use the > uninitialise engines before discarding them. > > [ 16.136152] RIP: 0010:__flush_work+0x198/0x1b0 > [ 16.136168] Code: ff ff 8b 0b 48 8b 53 08 83 e1 08 48 0f ba 2b 03 80 c9 f0 e9 63 ff ff ff 0f 0b 48 83 c4 48 44 89 f0 5b 5d 41 5c 41 5d 41 5e c3 <0f> 0b 45 31 f6 e9 62 ff ff ff 66 66 2e 0f 1f 84 00 00 00 00 00 0f > [ 16.136186] RSP: 0018:ffffc900003bb928 EFLAGS: 00010246 > [ 16.136201] RAX: 0000000000000000 RBX: ffff88844f392168 RCX: 0000000000000000 > [ 16.136216] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff88844f392168 > [ 16.136231] RBP: ffff88844f392130 R08: 0000000000000000 R09: 0000000000000001 > [ 16.136246] R10: ffff888441e31e40 R11: ffff88845e329c70 R12: ffff88844f796988 > [ 16.136261] R13: ffff888441e4fb80 R14: 0000000000000001 R15: ffff88844f790000 > [ 16.136388] FS: 00007fecbd208880(0000) GS:ffff88845e380000(0000) knlGS:0000000000000000 > [ 16.136405] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 16.136420] CR2: 00007ff3ce748f90 CR3: 0000000457a6a001 CR4: 00000000000606e0 > [ 16.136437] Call Trace: > [ 16.136456] ? try_to_del_timer_sync+0x3a/0x50 > [ 16.136529] intel_wakeref_wait_for_idle+0x87/0xb0 [i915] > [ 16.136606] ? intel_engines_release+0x68/0xc0 [i915] > [ 16.136680] intel_engines_release+0x49/0xc0 [i915] > [ 16.136757] intel_gt_init+0x2f4/0x5e0 [i915] > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index da5b61085257..c8c14981eb5d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -414,12 +414,12 @@ void intel_engines_release(struct intel_gt *gt) > > /* Decouple the backend; but keep the layout for late GPU resets */ > for_each_engine(engine, gt, id) { > - intel_wakeref_wait_for_idle(&engine->wakeref); > - GEM_BUG_ON(intel_engine_pm_is_awake(engine)); > - > if (!engine->release) > continue; > > + intel_wakeref_wait_for_idle(&engine->wakeref); > + GEM_BUG_ON(intel_engine_pm_is_awake(engine)); > + > engine->release(engine); > engine->release = NULL; > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Mon Jun 1 11:39:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 01 Jun 2020 12:39:57 +0100 Subject: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/36] drm/i915: Handle very early engine initialisation failure (rev2) In-Reply-To: <159100924007.14888.836552676635186270@emeril.freedesktop.org> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <159100924007.14888.836552676635186270@emeril.freedesktop.org> Message-ID: <159101159719.29407.14651351122274434786@build.alporthouse.com> Quoting Patchwork (2020-06-01 12:00:40) > == Series Details == > > Series: series starting with [01/36] drm/i915: Handle very early engine initialisation failure (rev2) > URL : https://patchwork.freedesktop.org/series/77857/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8560_full -> Patchwork_17828_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17828_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17828_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17828_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at runner@aborted: > - shard-hsw: NOTRUN -> [FAIL][1] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw6/igt at runner@aborted.html > > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * {igt at gem_exec_fence@parallel at vecs0}: > - shard-hsw: [PASS][2] -> [FAIL][3] +3 similar issues > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8560/shard-hsw1/igt at gem_exec_fence@parallel at vecs0.html > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17828/shard-hsw2/igt at gem_exec_fence@parallel at vecs0.html Sigh. They dropped the memory compare from MI_SEMAPHORE_MBOX in Haswell. -Chris From mika.kuoppala at linux.intel.com Mon Jun 1 11:49:49 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 01 Jun 2020 14:49:49 +0300 Subject: [Intel-gfx] [PATCH 04/36] drm/i915: Trim the ironlake+ irq handler In-Reply-To: <20200601072446.19548-4-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-4-chris@chris-wilson.co.uk> Message-ID: <87mu5nhuoy.fsf@gaia.fi.intel.com> Chris Wilson writes: > Ever noticed that our interrupt handlers are where we spend most of our > time on a busy system? In part this is unavoidable as each interrupt > requires to poll and reset several registers, but we can try and so as > efficiently as possible. > > Function old new delta > ilk_irq_handler 2317 2156 -161 > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/i915_irq.c | 59 ++++++++++++++++----------------- > 1 file changed, 28 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 63579ab71cf6..07c0c7ea3795 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2097,69 +2097,66 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, > */ > static irqreturn_t ilk_irq_handler(int irq, void *arg) > { > - struct drm_i915_private *dev_priv = arg; > + struct drm_i915_private *i915 = arg; > + void __iomem * const regs = i915->uncore.regs; > u32 de_iir, gt_iir, de_ier, sde_ier = 0; > - irqreturn_t ret = IRQ_NONE; > > - if (!intel_irqs_enabled(dev_priv)) > + if (!unlikely(intel_irqs_enabled(i915))) Put ! inside the unlikely for readability please. > return IRQ_NONE; > > /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > - disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); > + disable_rpm_wakeref_asserts(&i915->runtime_pm); > > /* disable master interrupt before clearing iir */ > - de_ier = I915_READ(DEIER); > - I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); > + de_ier = raw_reg_read(regs, DEIER); > + raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); > > /* Disable south interrupts. We'll only write to SDEIIR once, so further > * interrupts will will be stored on its back queue, and then we'll be > * able to process them after we restore SDEIER (as soon as we restore > * it, we'll get an interrupt if SDEIIR still has something to process > * due to its back queue). */ > - if (!HAS_PCH_NOP(dev_priv)) { > - sde_ier = I915_READ(SDEIER); > - I915_WRITE(SDEIER, 0); > + if (!HAS_PCH_NOP(i915)) { > + sde_ier = raw_reg_read(regs, SDEIER); > + raw_reg_write(regs, SDEIER, 0); > } > > /* Find, clear, then process each source of interrupt */ > > - gt_iir = I915_READ(GTIIR); > + gt_iir = raw_reg_read(regs, GTIIR); > if (gt_iir) { > - I915_WRITE(GTIIR, gt_iir); > - ret = IRQ_HANDLED; > - if (INTEL_GEN(dev_priv) >= 6) > - gen6_gt_irq_handler(&dev_priv->gt, gt_iir); > + raw_reg_write(regs, GTIIR, gt_iir); > + if (INTEL_GEN(i915) >= 6) > + gen6_gt_irq_handler(&i915->gt, gt_iir); > else > - gen5_gt_irq_handler(&dev_priv->gt, gt_iir); > + gen5_gt_irq_handler(&i915->gt, gt_iir); > } > > - de_iir = I915_READ(DEIIR); > + de_iir = raw_reg_read(regs, DEIIR); > if (de_iir) { > - I915_WRITE(DEIIR, de_iir); > - ret = IRQ_HANDLED; > - if (INTEL_GEN(dev_priv) >= 7) > - ivb_display_irq_handler(dev_priv, de_iir); > + raw_reg_write(regs, DEIIR, de_iir); > + if (INTEL_GEN(i915) >= 7) > + ivb_display_irq_handler(i915, de_iir); > else > - ilk_display_irq_handler(dev_priv, de_iir); > + ilk_display_irq_handler(i915, de_iir); > } > > - if (INTEL_GEN(dev_priv) >= 6) { > - u32 pm_iir = I915_READ(GEN6_PMIIR); > + if (INTEL_GEN(i915) >= 6) { > + u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); > if (pm_iir) { > - I915_WRITE(GEN6_PMIIR, pm_iir); > - ret = IRQ_HANDLED; > - gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); > + raw_reg_write(regs, GEN6_PMIIR, pm_iir); > + gen6_rps_irq_handler(&i915->gt.rps, pm_iir); > } > } > > - I915_WRITE(DEIER, de_ier); > - if (!HAS_PCH_NOP(dev_priv)) > - I915_WRITE(SDEIER, sde_ier); > + raw_reg_write(regs, DEIER, de_ier); > + if (sde_ier) > + raw_reg_write(regs, SDEIER, sde_ier); > > /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > - enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); > + enable_rpm_wakeref_asserts(&i915->runtime_pm); > > - return ret; > + return IRQ_HANDLED; Change in here is that if we catch a intr without any work, we now return handled instead of none. And as we have not actually done anything to prevent the next one to kicking off, this is potentially dangerous. But we explicitly clear the enables tho, but is it enough? -Mika > } > > static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Mon Jun 1 12:00:43 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 01 Jun 2020 13:00:43 +0100 Subject: [Intel-gfx] [PATCH 04/36] drm/i915: Trim the ironlake+ irq handler In-Reply-To: <87mu5nhuoy.fsf@gaia.fi.intel.com> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-4-chris@chris-wilson.co.uk> <87mu5nhuoy.fsf@gaia.fi.intel.com> Message-ID: <159101284356.29407.17566133173569257311@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-01 12:49:49) > Chris Wilson writes: > > > Ever noticed that our interrupt handlers are where we spend most of our > > time on a busy system? In part this is unavoidable as each interrupt > > requires to poll and reset several registers, but we can try and so as > > efficiently as possible. > > > > Function old new delta > > ilk_irq_handler 2317 2156 -161 > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/i915_irq.c | 59 ++++++++++++++++----------------- > > 1 file changed, 28 insertions(+), 31 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 63579ab71cf6..07c0c7ea3795 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -2097,69 +2097,66 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, > > */ > > static irqreturn_t ilk_irq_handler(int irq, void *arg) > > { > > - struct drm_i915_private *dev_priv = arg; > > + struct drm_i915_private *i915 = arg; > > + void __iomem * const regs = i915->uncore.regs; > > u32 de_iir, gt_iir, de_ier, sde_ier = 0; > > - irqreturn_t ret = IRQ_NONE; > > > > - if (!intel_irqs_enabled(dev_priv)) > > + if (!unlikely(intel_irqs_enabled(i915))) > > Put ! inside the unlikely for readability please. > > > return IRQ_NONE; > > > > /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > > - disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); > > + disable_rpm_wakeref_asserts(&i915->runtime_pm); > > > > /* disable master interrupt before clearing iir */ > > - de_ier = I915_READ(DEIER); > > - I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); > > + de_ier = raw_reg_read(regs, DEIER); > > + raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); > > > > /* Disable south interrupts. We'll only write to SDEIIR once, so further > > * interrupts will will be stored on its back queue, and then we'll be > > * able to process them after we restore SDEIER (as soon as we restore > > * it, we'll get an interrupt if SDEIIR still has something to process > > * due to its back queue). */ > > - if (!HAS_PCH_NOP(dev_priv)) { > > - sde_ier = I915_READ(SDEIER); > > - I915_WRITE(SDEIER, 0); > > + if (!HAS_PCH_NOP(i915)) { > > + sde_ier = raw_reg_read(regs, SDEIER); > > + raw_reg_write(regs, SDEIER, 0); > > } > > > > /* Find, clear, then process each source of interrupt */ > > > > - gt_iir = I915_READ(GTIIR); > > + gt_iir = raw_reg_read(regs, GTIIR); > > if (gt_iir) { > > - I915_WRITE(GTIIR, gt_iir); > > - ret = IRQ_HANDLED; > > - if (INTEL_GEN(dev_priv) >= 6) > > - gen6_gt_irq_handler(&dev_priv->gt, gt_iir); > > + raw_reg_write(regs, GTIIR, gt_iir); > > + if (INTEL_GEN(i915) >= 6) > > + gen6_gt_irq_handler(&i915->gt, gt_iir); > > else > > - gen5_gt_irq_handler(&dev_priv->gt, gt_iir); > > + gen5_gt_irq_handler(&i915->gt, gt_iir); > > } > > > > - de_iir = I915_READ(DEIIR); > > + de_iir = raw_reg_read(regs, DEIIR); > > if (de_iir) { > > - I915_WRITE(DEIIR, de_iir); > > - ret = IRQ_HANDLED; > > - if (INTEL_GEN(dev_priv) >= 7) > > - ivb_display_irq_handler(dev_priv, de_iir); > > + raw_reg_write(regs, DEIIR, de_iir); > > + if (INTEL_GEN(i915) >= 7) > > + ivb_display_irq_handler(i915, de_iir); > > else > > - ilk_display_irq_handler(dev_priv, de_iir); > > + ilk_display_irq_handler(i915, de_iir); > > } > > > > - if (INTEL_GEN(dev_priv) >= 6) { > > - u32 pm_iir = I915_READ(GEN6_PMIIR); > > + if (INTEL_GEN(i915) >= 6) { > > + u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); > > if (pm_iir) { > > - I915_WRITE(GEN6_PMIIR, pm_iir); > > - ret = IRQ_HANDLED; > > - gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); > > + raw_reg_write(regs, GEN6_PMIIR, pm_iir); > > + gen6_rps_irq_handler(&i915->gt.rps, pm_iir); > > } > > } > > > > - I915_WRITE(DEIER, de_ier); > > - if (!HAS_PCH_NOP(dev_priv)) > > - I915_WRITE(SDEIER, sde_ier); > > + raw_reg_write(regs, DEIER, de_ier); > > + if (sde_ier) > > + raw_reg_write(regs, SDEIER, sde_ier); > > > > /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > > - enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); > > + enable_rpm_wakeref_asserts(&i915->runtime_pm); > > > > - return ret; > > + return IRQ_HANDLED; > > Change in here is that if we catch a intr without any work, we now > return handled instead of none. > > And as we have not actually done anything to prevent the next > one to kicking off, this is potentially dangerous. > > But we explicitly clear the enables tho, but is it enough? It's MSI-X, to get here means there was an interrupt. Let's check how much it adds to track IRQ_HANDLED. -Chris From uma.shankar at intel.com Mon Jun 1 12:04:43 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 1 Jun 2020 12:04:43 +0000 Subject: [Intel-gfx] [PATCH v6] drm/i915: Add Plane color encoding support for YCBCR_BT2020 In-Reply-To: <20200601073544.11291-1-kishore.kadiyala@intel.com> References: <20200601073544.11291-1-kishore.kadiyala@intel.com> Message-ID: > -----Original Message----- > From: Kadiyala, Kishore > Sent: Monday, June 1, 2020 1:06 PM > To: intel-gfx at lists.freedesktop.org > Cc: Kadiyala, Kishore ; Ville Syrjala > ; Nikula, Jani ; Shankar, > Uma > Subject: [PATCH v6] drm/i915: Add Plane color encoding support for > YCBCR_BT2020 > > Currently the plane property doesn't have support for YCBCR_BT2020, which > enables the corresponding color conversion mode on plane CSC. > Enabling the plane property for the planes for GLK & ICL+ platforms. > Also as per spec, update the Plane Color CSC from YUV601_TO_RGB709 to > YUV601_TO_RGB601. > > V2: Enabling support for YCBCT_BT2020 for HDR planes on > platforms GLK & ICL > > V3: Refined the condition check to handle GLK & ICL+ HDR planes > Also added BT2020 handling in glk_plane_color_ctl. > > V4: Combine If-else into single If > > V5: Drop the checking for HDR planes and enable YCBCR_BT2020 > for platforms GLK & ICL+. > > V6: As per Spec, update PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 > to PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 as per Ville's > feedback. > > V7: Rebased Pushed the change to dinq. Thanks for the patch and reviews. Regards, Uma Shankar > Cc: Ville Syrjala > Cc: Jani Nikula > Reviewed-by: Uma Shankar > Signed-off-by: Kishore Kadiyala > --- > drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++---- > drivers/gpu/drm/i915/display/intel_sprite.c | 9 +++++++-- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 3 files changed, 19 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 8f9f9b20d5f5..a9f752d26b4e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -4812,11 +4812,18 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state > *crtc_state, > plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); > > if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { > - if (plane_state->hw.color_encoding == > DRM_COLOR_YCBCR_BT709) > + switch (plane_state->hw.color_encoding) { > + case DRM_COLOR_YCBCR_BT709: > plane_color_ctl |= > PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; > - else > - plane_color_ctl |= > PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709; > - > + break; > + case DRM_COLOR_YCBCR_BT2020: > + plane_color_ctl |= > + > PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020; > + break; > + default: > + plane_color_ctl |= > + PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601; > + } > if (plane_state->hw.color_range == > DRM_COLOR_YCBCR_FULL_RANGE) > plane_color_ctl |= > PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE; > } else if (fb->format->is_yuv) { > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > b/drivers/gpu/drm/i915/display/intel_sprite.c > index 571c36f929bd..3cd461bf9131 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -3061,6 +3061,7 @@ skl_universal_plane_create(struct drm_i915_private > *dev_priv, > struct intel_plane *plane; > enum drm_plane_type plane_type; > unsigned int supported_rotations; > + unsigned int supported_csc; > const u64 *modifiers; > const u32 *formats; > int num_formats; > @@ -3135,9 +3136,13 @@ skl_universal_plane_create(struct drm_i915_private > *dev_priv, > DRM_MODE_ROTATE_0, > supported_rotations); > > + supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | > +BIT(DRM_COLOR_YCBCR_BT709); > + > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > + supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); > + > drm_plane_create_color_properties(&plane->base, > - BIT(DRM_COLOR_YCBCR_BT601) | > - BIT(DRM_COLOR_YCBCR_BT709), > + supported_csc, > > BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | > BIT(DRM_COLOR_YCBCR_FULL_RANGE), > DRM_COLOR_YCBCR_BT709, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e9d50fe0f375..578cfe11cbb9 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6932,7 +6932,7 @@ enum { > #define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ > #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ > #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) > -#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17) > +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17) > #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) > #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) > #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) > -- > 2.26.2 From chris at chris-wilson.co.uk Mon Jun 1 12:08:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 01 Jun 2020 13:08:15 +0100 Subject: [Intel-gfx] [PATCH 04/36] drm/i915: Trim the ironlake+ irq handler In-Reply-To: <159101284356.29407.17566133173569257311@build.alporthouse.com> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-4-chris@chris-wilson.co.uk> <87mu5nhuoy.fsf@gaia.fi.intel.com> <159101284356.29407.17566133173569257311@build.alporthouse.com> Message-ID: <159101329556.29407.2013434789388460697@build.alporthouse.com> Quoting Chris Wilson (2020-06-01 13:00:43) > Quoting Mika Kuoppala (2020-06-01 12:49:49) > > Chris Wilson writes: > > > > > Ever noticed that our interrupt handlers are where we spend most of our > > > time on a busy system? In part this is unavoidable as each interrupt > > > requires to poll and reset several registers, but we can try and so as > > > efficiently as possible. > > > > > > Function old new delta > > > ilk_irq_handler 2317 2156 -161 With irqreturn_t ret, ilk_irq_handler.cold 63 72 +9 ilk_irq_handler 2221 2083 -138 I love how it can change so much simply by recompiling the baseline. -Chris From chris at chris-wilson.co.uk Mon Jun 1 12:14:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 13:14:23 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Trim the ironlake+ irq handler Message-ID: <20200601121423.19842-1-chris@chris-wilson.co.uk> Ever noticed that our interrupt handlers are where we spend most of our time on a busy system? In part this is unavoidable as each interrupt requires to poll and reset several registers, but we can try and do so as efficiently as possible. Function old new delta ilk_irq_handler 2317 2156 -161 v2: Restore the irqreturn_t ret Function old new delta ilk_irq_handler.cold 63 72 +9 ilk_irq_handler 2221 2080 -141 A slight improvement in the baseline overnight as well! Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- drivers/gpu/drm/i915/i915_irq.c | 59 +++++++++++++++++---------------- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 63579ab71cf6..01d4e3cad69d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2097,67 +2097,68 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, */ static irqreturn_t ilk_irq_handler(int irq, void *arg) { - struct drm_i915_private *dev_priv = arg; + struct drm_i915_private *i915 = arg; + void __iomem * const regs = i915->uncore.regs; u32 de_iir, gt_iir, de_ier, sde_ier = 0; irqreturn_t ret = IRQ_NONE; - if (!intel_irqs_enabled(dev_priv)) + if (unlikely(!intel_irqs_enabled(i915))) return IRQ_NONE; /* IRQs are synced during runtime_suspend, we don't require a wakeref */ - disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + disable_rpm_wakeref_asserts(&i915->runtime_pm); /* disable master interrupt before clearing iir */ - de_ier = I915_READ(DEIER); - I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); + de_ier = raw_reg_read(regs, DEIER); + raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); /* Disable south interrupts. We'll only write to SDEIIR once, so further * interrupts will will be stored on its back queue, and then we'll be * able to process them after we restore SDEIER (as soon as we restore * it, we'll get an interrupt if SDEIIR still has something to process * due to its back queue). */ - if (!HAS_PCH_NOP(dev_priv)) { - sde_ier = I915_READ(SDEIER); - I915_WRITE(SDEIER, 0); + if (!HAS_PCH_NOP(i915)) { + sde_ier = raw_reg_read(regs, SDEIER); + raw_reg_write(regs, SDEIER, 0); } /* Find, clear, then process each source of interrupt */ - gt_iir = I915_READ(GTIIR); + gt_iir = raw_reg_read(regs, GTIIR); if (gt_iir) { - I915_WRITE(GTIIR, gt_iir); - ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 6) - gen6_gt_irq_handler(&dev_priv->gt, gt_iir); + raw_reg_write(regs, GTIIR, gt_iir); + if (INTEL_GEN(i915) >= 6) + gen6_gt_irq_handler(&i915->gt, gt_iir); else - gen5_gt_irq_handler(&dev_priv->gt, gt_iir); + gen5_gt_irq_handler(&i915->gt, gt_iir); + ret = IRQ_HANDLED; } - de_iir = I915_READ(DEIIR); + de_iir = raw_reg_read(regs, DEIIR); if (de_iir) { - I915_WRITE(DEIIR, de_iir); - ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 7) - ivb_display_irq_handler(dev_priv, de_iir); + raw_reg_write(regs, DEIIR, de_iir); + if (INTEL_GEN(i915) >= 7) + ivb_display_irq_handler(i915, de_iir); else - ilk_display_irq_handler(dev_priv, de_iir); + ilk_display_irq_handler(i915, de_iir); + ret = IRQ_HANDLED; } - if (INTEL_GEN(dev_priv) >= 6) { - u32 pm_iir = I915_READ(GEN6_PMIIR); + if (INTEL_GEN(i915) >= 6) { + u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); if (pm_iir) { - I915_WRITE(GEN6_PMIIR, pm_iir); - ret = IRQ_HANDLED; - gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); + raw_reg_write(regs, GEN6_PMIIR, pm_iir); + gen6_rps_irq_handler(&i915->gt.rps, pm_iir); } + ret = IRQ_HANDLED; } - I915_WRITE(DEIER, de_ier); - if (!HAS_PCH_NOP(dev_priv)) - I915_WRITE(SDEIER, sde_ier); + raw_reg_write(regs, DEIER, de_ier); + if (sde_ier) + raw_reg_write(regs, SDEIER, sde_ier); /* IRQs are synced during runtime_suspend, we don't require a wakeref */ - enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + enable_rpm_wakeref_asserts(&i915->runtime_pm); return ret; } -- 2.20.1 From mika.kuoppala at linux.intel.com Mon Jun 1 12:17:23 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 01 Jun 2020 15:17:23 +0300 Subject: [Intel-gfx] [PATCH 12/36] drm/i915/gt: Track if an engine requires forcewake w/a In-Reply-To: <20200601072446.19548-12-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-12-chris@chris-wilson.co.uk> Message-ID: <87imgbhtf0.fsf@gaia.fi.intel.com> Chris Wilson writes: > Sometimes an engine might need to keep forcewake active while it is busy > submitting requests for a particular workaround. Track such nuisance > with engine->fw_domain. > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +++++++++ > drivers/gpu/drm/i915/gt/intel_ring_scheduler.c | 4 ++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h > index 3782e27c2945..ccdd69923793 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h > @@ -313,6 +313,15 @@ struct intel_engine_cs { > u32 context_size; > u32 mmio_base; > > + /* > + * Some w/a require forcewake to be held (which prevents RC6) while > + * a particular engine is active. If so, we set fw_domain to which > + * domains need to be held for the duration of request activity, > + * and 0 if none. > + */ > + unsigned int fw_domain; > + unsigned int fw_active; > + > unsigned long context_tag; > > struct rb_node uabi_node; > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c > index aaff554865b1..777cab6d9540 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c > @@ -60,6 +60,8 @@ static struct i915_request * > schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) > { > __intel_gt_pm_get(engine->gt); > + if (!engine->fw_active++ && engine->fw_domain) > + intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); > intel_engine_context_in(engine); > return i915_request_get(rq); > } > @@ -74,6 +76,8 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) > > i915_request_put(rq); > intel_engine_context_out(engine); > + if (!--engine->fw_active && engine->fw_domain) > + intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); > intel_gt_pm_put_async(engine->gt); > } > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Mon Jun 1 12:20:14 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 01 Jun 2020 15:20:14 +0300 Subject: [Intel-gfx] [PATCH 13/36] drm/i915: Relinquish forcewake immediately after manual grouping In-Reply-To: <20200601072446.19548-13-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-13-chris@chris-wilson.co.uk> Message-ID: <87ftbfhta9.fsf@gaia.fi.intel.com> Chris Wilson writes: > Our forcewake utilisation is split into categories: automatic and > manual. Around bare register reads, we look up the right forcewake > domain and automatically acquire and release [upon a timer] the > forcewake domain. For other access, where we know we require the > forcewake across a group of register reads, we manually acquire the > forcewake domain and release it at the end. Again, this currently arms > the domain timer for a later release. > > However, looking at some energy utilisation profiles, we have tried to > avoid using forcewake [and rely on the natural wake up to post register > updates] due to that even keep the fw active for a brief period > contributes to a significant power draw [i.e. when the gpu is sleeping > with rc6 at high clocks]. But as it turns out, not posting the writes > immediately also has unintended consequences, such as not reducing the > clocks and so conserving power while busy. > > As a compromise, let us only arm the domain timer for automatic > forcewake usage around bare register access, but immediately release the > forcewake when manually acquired by intel_uncore_forcewake_get/_put. > > The corollary to this is that we may instead have to take forcewake more > often, and so incur a latency penalty in doing so. For Sandybridge this > was significant, and even on the latest machines, taking forcewake at > interrupt frequency is a huge impact. [So we don't do that anymore! > Hopefully, this will spare us from still needing the mitigation of the > timer for steady state execution.] > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > Cc: Mika Kuoppala I am not a fan of having explicit put relying on timer, Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_uncore.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index a61cb8ca4d50..7d6b9ae7403c 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -709,7 +709,7 @@ static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, > continue; > } > > - fw_domain_arm_timer(domain); > + uncore->funcs.force_wake_put(uncore, domain->mask); > } > } > > -- > 2.20.1 From uma.shankar at intel.com Mon Jun 1 12:49:44 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 1 Jun 2020 12:49:44 +0000 Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs In-Reply-To: <20200601101516.21018-1-anshuman.gupta@intel.com> References: <20200601101516.21018-1-anshuman.gupta@intel.com> Message-ID: > -----Original Message----- > From: Intel-gfx On Behalf Of > Anshuman Gupta > Sent: Monday, June 1, 2020 3:45 PM > To: intel-gfx at lists.freedesktop.org > Cc: stable at vger.kernel.org > Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs > > Gen12 hw are failing to enable lpsp configuration due to PG3 was left on due to > valid usgae count of POWER_DOMAIN_AUDIO. > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling a crtc, > it should be always i915_audio_component request to get/put > AUDIO_POWER_DOMAIN. > > Cc: stable at vger.kernel.org > Cc: Ville Syrj?l? > Cc: Maarten Lankhorst > Signed-off-by: Anshuman Gupta > --- > drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 6c3b11de2daf..f31a579d7a52 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct > intel_crtc_state *crtc_state) > mask |= BIT_ULL(intel_encoder->power_domain); > } > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > + /* > + * Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > + * enable AUDIO power in order to enable a crtc. > + */ > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && > +crtc_state->has_audio) > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); As part of ddi_get_config we determine has_audio using power well enabled: pipe_config->has_audio = intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); If audio power domain is not enabled, we may end up with this as false. Later this may get checked in intel_enable_ddi_hdmi to call audio codec enable if (crtc_state->has_audio) intel_audio_codec_enable(encoder, crtc_state, conn_state); This may cause detection to fail. Please verify this usecase once and confirm. Regards, Uma Shankar > if (crtc_state->shared_dpll) > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Mon Jun 1 13:54:24 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 01 Jun 2020 16:54:24 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Trim the ironlake+ irq handler In-Reply-To: <20200601121423.19842-1-chris@chris-wilson.co.uk> References: <20200601121423.19842-1-chris@chris-wilson.co.uk> Message-ID: <87v9kasxgv.fsf@gaia.fi.intel.com> Chris Wilson writes: > Ever noticed that our interrupt handlers are where we spend most of our > time on a busy system? In part this is unavoidable as each interrupt > requires to poll and reset several registers, but we can try and do so as > efficiently as possible. > > Function old new delta > ilk_irq_handler 2317 2156 -161 > > v2: Restore the irqreturn_t ret > > Function old new delta > ilk_irq_handler.cold 63 72 +9 > ilk_irq_handler 2221 2080 -141 > > A slight improvement in the baseline overnight as well! > > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_irq.c | 59 +++++++++++++++++---------------- > 1 file changed, 30 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 63579ab71cf6..01d4e3cad69d 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2097,67 +2097,68 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, > */ > static irqreturn_t ilk_irq_handler(int irq, void *arg) > { > - struct drm_i915_private *dev_priv = arg; > + struct drm_i915_private *i915 = arg; > + void __iomem * const regs = i915->uncore.regs; > u32 de_iir, gt_iir, de_ier, sde_ier = 0; > irqreturn_t ret = IRQ_NONE; > > - if (!intel_irqs_enabled(dev_priv)) > + if (unlikely(!intel_irqs_enabled(i915))) Doesn't hurt anymore. And dont have to worry about ret so only thing different is void of forcewake dance. Reviewed-by: Mika Kuoppala > return IRQ_NONE; > > /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > - disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); > + disable_rpm_wakeref_asserts(&i915->runtime_pm); > > /* disable master interrupt before clearing iir */ > - de_ier = I915_READ(DEIER); > - I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); > + de_ier = raw_reg_read(regs, DEIER); > + raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); > > /* Disable south interrupts. We'll only write to SDEIIR once, so further > * interrupts will will be stored on its back queue, and then we'll be > * able to process them after we restore SDEIER (as soon as we restore > * it, we'll get an interrupt if SDEIIR still has something to process > * due to its back queue). */ > - if (!HAS_PCH_NOP(dev_priv)) { > - sde_ier = I915_READ(SDEIER); > - I915_WRITE(SDEIER, 0); > + if (!HAS_PCH_NOP(i915)) { > + sde_ier = raw_reg_read(regs, SDEIER); > + raw_reg_write(regs, SDEIER, 0); > } > > /* Find, clear, then process each source of interrupt */ > > - gt_iir = I915_READ(GTIIR); > + gt_iir = raw_reg_read(regs, GTIIR); > if (gt_iir) { > - I915_WRITE(GTIIR, gt_iir); > - ret = IRQ_HANDLED; > - if (INTEL_GEN(dev_priv) >= 6) > - gen6_gt_irq_handler(&dev_priv->gt, gt_iir); > + raw_reg_write(regs, GTIIR, gt_iir); > + if (INTEL_GEN(i915) >= 6) > + gen6_gt_irq_handler(&i915->gt, gt_iir); > else > - gen5_gt_irq_handler(&dev_priv->gt, gt_iir); > + gen5_gt_irq_handler(&i915->gt, gt_iir); > + ret = IRQ_HANDLED; > } > > - de_iir = I915_READ(DEIIR); > + de_iir = raw_reg_read(regs, DEIIR); > if (de_iir) { > - I915_WRITE(DEIIR, de_iir); > - ret = IRQ_HANDLED; > - if (INTEL_GEN(dev_priv) >= 7) > - ivb_display_irq_handler(dev_priv, de_iir); > + raw_reg_write(regs, DEIIR, de_iir); > + if (INTEL_GEN(i915) >= 7) > + ivb_display_irq_handler(i915, de_iir); > else > - ilk_display_irq_handler(dev_priv, de_iir); > + ilk_display_irq_handler(i915, de_iir); > + ret = IRQ_HANDLED; > } > > - if (INTEL_GEN(dev_priv) >= 6) { > - u32 pm_iir = I915_READ(GEN6_PMIIR); > + if (INTEL_GEN(i915) >= 6) { > + u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); > if (pm_iir) { > - I915_WRITE(GEN6_PMIIR, pm_iir); > - ret = IRQ_HANDLED; > - gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); > + raw_reg_write(regs, GEN6_PMIIR, pm_iir); > + gen6_rps_irq_handler(&i915->gt.rps, pm_iir); > } > + ret = IRQ_HANDLED; > } > > - I915_WRITE(DEIER, de_ier); > - if (!HAS_PCH_NOP(dev_priv)) > - I915_WRITE(SDEIER, sde_ier); > + raw_reg_write(regs, DEIER, de_ier); > + if (sde_ier) > + raw_reg_write(regs, SDEIER, sde_ier); > > /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > - enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); > + enable_rpm_wakeref_asserts(&i915->runtime_pm); > > return ret; > } > -- > 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 1 14:00:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 14:00:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915=3A_Trim_the_ironlake+_irq_handler?= In-Reply-To: <20200601121423.19842-1-chris@chris-wilson.co.uk> References: <20200601121423.19842-1-chris@chris-wilson.co.uk> Message-ID: <159102003729.14890.9713714575536241630@emeril.freedesktop.org> == Series Details == Series: drm/i915: Trim the ironlake+ irq handler URL : https://patchwork.freedesktop.org/series/77871/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8562 -> Patchwork_17830 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17830 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17830, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17830/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17830: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8562/fi-cml-s/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17830/fi-cml-s/igt at i915_selftest@live at execlists.html * igt at i915_selftest@live at gt_pm: - fi-bsw-n3050: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8562/fi-bsw-n3050/igt at i915_selftest@live at gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17830/fi-bsw-n3050/igt at i915_selftest@live at gt_pm.html Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8562 -> Patchwork_17830 CI-20190529: 20190529 CI_DRM_8562: bd08b2b513aeceb9b1beaa7d23e6bc11cc590d6f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17830: a883f972cf7ac10a4fee4260afdd95e9f08ede8a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a883f972cf7a drm/i915: Trim the ironlake+ irq handler == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17830/index.html From sean at poorly.run Mon Jun 1 14:02:17 2020 From: sean at poorly.run (Sean Paul) Date: Mon, 1 Jun 2020 10:02:17 -0400 Subject: [Intel-gfx] [PATCH] drm/i915/panel: Reduce race window between bl_update_status and bl_enable Message-ID: <20200601140217.51709-1-sean@poorly.run> From: Sean Paul If the backlight is updated while the panel is being enabled, the value from userspace (which is stored in panel->backlight.device->props.brightness) can be replaced by the hardware's minimum level. There's really no good way to tell if this is happening in enable_backlight() since props.brightness can be initialized to the same value as is being set by userspace. So we'll try to reduce the race window as much as possible. Signed-off-by: Sean Paul --- I don't think there's any way to eliminate this race since grabbing bd->op_lock in panel_enable would cause a lock inversion deadlock with the connection_mutex lock in backlight_device_update_status Suggestions very much welcome! drivers/gpu/drm/i915/display/intel_panel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 3c5056dbf607..abdfb9cc281b 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1285,8 +1285,22 @@ static int intel_backlight_device_update_status(struct backlight_device *bd) struct intel_connector *connector = bl_get_data(bd); struct intel_panel *panel = &connector->panel; struct drm_device *dev = connector->base.dev; + int value; + + /* + * Before we attempt to grab the connection mutex, cache the incoming + * brightness value. If we're in the middle of a modeset, + * intel_panel_enable_backlight will be called and could pave over + * props.brightness. This is still racey, but the race window should be + * significantly smaller and reflects the inherent raceyness of the + * updating props.brightness outside of bd->op_lock. + */ + value = bd->props.brightness; drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + + bd->props.brightness = value; + DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n", bd->props.brightness, bd->props.max_brightness); intel_panel_set_backlight(connector->base.state, bd->props.brightness, -- Sean Paul, Software Engineer, Google / Chromium OS From dan.carpenter at oracle.com Mon Jun 1 14:01:08 2020 From: dan.carpenter at oracle.com (Dan Carpenter) Date: Mon, 1 Jun 2020 17:01:08 +0300 Subject: [Intel-gfx] [PATCH v1] drm/i915: Fix wrong CDCLK adjustment changes In-Reply-To: <20200526094852.6967-1-stanislav.lisovskiy@intel.com> Message-ID: <20200601140108.GR30374@kadam> Hi Stanislav, url: https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-randconfig-m021-20200531 (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kbuild test robot Reported-by: Dan Carpenter smatch warnings: drivers/gpu/drm/i915/display/intel_bw.c:453 skl_bw_calc_min_cdclk() error: uninitialized symbol 'pipe'. # https://github.com/0day-ci/linux/commit/21b0324886122a396687d977d67eb6ce3caf2b17 git remote add linux-review https://github.com/0day-ci/linux git remote update linux-review git checkout 21b0324886122a396687d977d67eb6ce3caf2b17 vim +/pipe +453 drivers/gpu/drm/i915/display/intel_bw.c 366b6200f76e0f Jani Nikula 2019-08-06 430 cd19154608610a Stanislav Lisovskiy 2020-05-20 431 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) cd19154608610a Stanislav Lisovskiy 2020-05-20 432 { cd19154608610a Stanislav Lisovskiy 2020-05-20 433 struct drm_i915_private *dev_priv = to_i915(state->base.dev); cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 434 struct intel_bw_state *new_bw_state = NULL; cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 435 struct intel_bw_state *old_bw_state = NULL; cd19154608610a Stanislav Lisovskiy 2020-05-20 436 const struct intel_crtc_state *crtc_state; cd19154608610a Stanislav Lisovskiy 2020-05-20 437 struct intel_crtc *crtc; cd19154608610a Stanislav Lisovskiy 2020-05-20 438 int max_bw = 0; cd19154608610a Stanislav Lisovskiy 2020-05-20 439 int slice_id; 21b0324886122a Stanislav Lisovskiy 2020-05-26 440 enum pipe pipe; cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 441 int i; cd19154608610a Stanislav Lisovskiy 2020-05-20 442 cd19154608610a Stanislav Lisovskiy 2020-05-20 443 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { cd19154608610a Stanislav Lisovskiy 2020-05-20 444 enum plane_id plane_id; cd19154608610a Stanislav Lisovskiy 2020-05-20 445 struct intel_dbuf_bw *crtc_bw; cd19154608610a Stanislav Lisovskiy 2020-05-20 446 cd19154608610a Stanislav Lisovskiy 2020-05-20 447 new_bw_state = intel_atomic_get_bw_state(state); cd19154608610a Stanislav Lisovskiy 2020-05-20 448 if (IS_ERR(new_bw_state)) cd19154608610a Stanislav Lisovskiy 2020-05-20 449 return PTR_ERR(new_bw_state); cd19154608610a Stanislav Lisovskiy 2020-05-20 450 21b0324886122a Stanislav Lisovskiy 2020-05-26 451 old_bw_state = intel_atomic_get_old_bw_state(state); 21b0324886122a Stanislav Lisovskiy 2020-05-26 452 21b0324886122a Stanislav Lisovskiy 2020-05-26 @453 crtc_bw = &new_bw_state->dbuf_bw[pipe]; ^^^^ Not initialized. Probably "i" was intended? cd19154608610a Stanislav Lisovskiy 2020-05-20 454 cd19154608610a Stanislav Lisovskiy 2020-05-20 455 memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); cd19154608610a Stanislav Lisovskiy 2020-05-20 456 cd19154608610a Stanislav Lisovskiy 2020-05-20 457 for_each_plane_id_on_crtc(crtc, plane_id) { cd19154608610a Stanislav Lisovskiy 2020-05-20 458 const struct skl_ddb_entry *plane_alloc = cd19154608610a Stanislav Lisovskiy 2020-05-20 459 &crtc_state->wm.skl.plane_ddb_y[plane_id]; cd19154608610a Stanislav Lisovskiy 2020-05-20 460 const struct skl_ddb_entry *uv_plane_alloc = cd19154608610a Stanislav Lisovskiy 2020-05-20 461 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; cd19154608610a Stanislav Lisovskiy 2020-05-20 462 unsigned int data_rate = crtc_state->data_rate[plane_id]; cd19154608610a Stanislav Lisovskiy 2020-05-20 463 unsigned int dbuf_mask = 0; cd19154608610a Stanislav Lisovskiy 2020-05-20 464 cd19154608610a Stanislav Lisovskiy 2020-05-20 465 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc); cd19154608610a Stanislav Lisovskiy 2020-05-20 466 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc); cd19154608610a Stanislav Lisovskiy 2020-05-20 467 cd19154608610a Stanislav Lisovskiy 2020-05-20 468 /* cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 469 * FIXME: To calculate that more properly we probably cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 470 * need to to split per plane data_rate into data_rate_y cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 471 * and data_rate_uv for multiplanar formats in order not cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 472 * to get accounted those twice if they happen to reside cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 473 * on different slices. cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 474 * However for pre-icl this would work anyway because cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 475 * we have only single slice and for icl+ uv plane has cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 476 * non-zero data rate. cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 477 * So in worst case those calculation are a bit cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 478 * pessimistic, which shouldn't pose any significant cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 479 * problem anyway. cd19154608610a Stanislav Lisovskiy 2020-05-20 480 */ cd19154608610a Stanislav Lisovskiy 2020-05-20 481 for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) cd19154608610a Stanislav Lisovskiy 2020-05-20 482 crtc_bw->used_bw[slice_id] += data_rate; cd19154608610a Stanislav Lisovskiy 2020-05-20 483 } 21b0324886122a Stanislav Lisovskiy 2020-05-26 484 } 21b0324886122a Stanislav Lisovskiy 2020-05-26 485 21b0324886122a Stanislav Lisovskiy 2020-05-26 486 if (!old_bw_state) 21b0324886122a Stanislav Lisovskiy 2020-05-26 487 return 0; 21b0324886122a Stanislav Lisovskiy 2020-05-26 488 21b0324886122a Stanislav Lisovskiy 2020-05-26 489 for_each_pipe(dev_priv, pipe) { 21b0324886122a Stanislav Lisovskiy 2020-05-26 490 struct intel_dbuf_bw *crtc_bw; 21b0324886122a Stanislav Lisovskiy 2020-05-26 491 21b0324886122a Stanislav Lisovskiy 2020-05-26 492 crtc_bw = &new_bw_state->dbuf_bw[pipe]; cd19154608610a Stanislav Lisovskiy 2020-05-20 493 cd19154608610a Stanislav Lisovskiy 2020-05-20 494 for_each_dbuf_slice(slice_id) { cd19154608610a Stanislav Lisovskiy 2020-05-20 495 /* cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 496 * Current experimental observations show that contrary cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 497 * to BSpec we get underruns once we exceed 64 * CDCLK cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 498 * for slices in total. cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 499 * As a temporary measure in order not to keep CDCLK cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 500 * bumped up all the time we calculate CDCLK according cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 501 * to this formula for overall bw consumed by slices. cd19154608610a Stanislav Lisovskiy 2020-05-20 502 */ cd19154608610a Stanislav Lisovskiy 2020-05-20 503 max_bw += crtc_bw->used_bw[slice_id]; cd19154608610a Stanislav Lisovskiy 2020-05-20 504 } cd19154608610a Stanislav Lisovskiy 2020-05-20 505 } cd19154608610a Stanislav Lisovskiy 2020-05-20 506 21b0324886122a Stanislav Lisovskiy 2020-05-26 507 new_bw_state->min_cdclk = max_bw / 64; cd19154608610a Stanislav Lisovskiy 2020-05-20 508 cd19154608610a Stanislav Lisovskiy 2020-05-20 509 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { cd19154608610a Stanislav Lisovskiy 2020-05-20 510 int ret = intel_atomic_lock_global_state(&new_bw_state->base); cd19154608610a Stanislav Lisovskiy 2020-05-20 511 cd19154608610a Stanislav Lisovskiy 2020-05-20 512 if (ret) cd19154608610a Stanislav Lisovskiy 2020-05-20 513 return ret; cd19154608610a Stanislav Lisovskiy 2020-05-20 514 } cd19154608610a Stanislav Lisovskiy 2020-05-20 515 cd19154608610a Stanislav Lisovskiy 2020-05-20 516 return 0; cd19154608610a Stanislav Lisovskiy 2020-05-20 517 } --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 40683 bytes Desc: not available URL: From chris at chris-wilson.co.uk Mon Jun 1 14:03:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 15:03:55 +0100 Subject: [Intel-gfx] [CI] drm/i915: Trim the ironlake+ irq handler Message-ID: <20200601140355.20243-1-chris@chris-wilson.co.uk> Ever noticed that our interrupt handlers are where we spend most of our time on a busy system? In part this is unavoidable as each interrupt requires to poll and reset several registers, but we can try and do so as efficiently as possible. Function old new delta ilk_irq_handler 2317 2156 -161 v2: Restore the irqreturn_t ret Function old new delta ilk_irq_handler.cold 63 72 +9 ilk_irq_handler 2221 2080 -141 A slight improvement in the baseline overnight as well! Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++---------------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 63579ab71cf6..490574669eaa 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2097,67 +2097,68 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, */ static irqreturn_t ilk_irq_handler(int irq, void *arg) { - struct drm_i915_private *dev_priv = arg; + struct drm_i915_private *i915 = arg; + void __iomem * const regs = i915->uncore.regs; u32 de_iir, gt_iir, de_ier, sde_ier = 0; irqreturn_t ret = IRQ_NONE; - if (!intel_irqs_enabled(dev_priv)) + if (unlikely(!intel_irqs_enabled(i915))) return IRQ_NONE; /* IRQs are synced during runtime_suspend, we don't require a wakeref */ - disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + disable_rpm_wakeref_asserts(&i915->runtime_pm); /* disable master interrupt before clearing iir */ - de_ier = I915_READ(DEIER); - I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); + de_ier = raw_reg_read(regs, DEIER); + raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); /* Disable south interrupts. We'll only write to SDEIIR once, so further * interrupts will will be stored on its back queue, and then we'll be * able to process them after we restore SDEIER (as soon as we restore * it, we'll get an interrupt if SDEIIR still has something to process * due to its back queue). */ - if (!HAS_PCH_NOP(dev_priv)) { - sde_ier = I915_READ(SDEIER); - I915_WRITE(SDEIER, 0); + if (!HAS_PCH_NOP(i915)) { + sde_ier = raw_reg_read(regs, SDEIER); + raw_reg_write(regs, SDEIER, 0); } /* Find, clear, then process each source of interrupt */ - gt_iir = I915_READ(GTIIR); + gt_iir = raw_reg_read(regs, GTIIR); if (gt_iir) { - I915_WRITE(GTIIR, gt_iir); - ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 6) - gen6_gt_irq_handler(&dev_priv->gt, gt_iir); + raw_reg_write(regs, GTIIR, gt_iir); + if (INTEL_GEN(i915) >= 6) + gen6_gt_irq_handler(&i915->gt, gt_iir); else - gen5_gt_irq_handler(&dev_priv->gt, gt_iir); + gen5_gt_irq_handler(&i915->gt, gt_iir); + ret = IRQ_HANDLED; } - de_iir = I915_READ(DEIIR); + de_iir = raw_reg_read(regs, DEIIR); if (de_iir) { - I915_WRITE(DEIIR, de_iir); - ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 7) - ivb_display_irq_handler(dev_priv, de_iir); + raw_reg_write(regs, DEIIR, de_iir); + if (INTEL_GEN(i915) >= 7) + ivb_display_irq_handler(i915, de_iir); else - ilk_display_irq_handler(dev_priv, de_iir); + ilk_display_irq_handler(i915, de_iir); + ret = IRQ_HANDLED; } - if (INTEL_GEN(dev_priv) >= 6) { - u32 pm_iir = I915_READ(GEN6_PMIIR); + if (INTEL_GEN(i915) >= 6) { + u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); if (pm_iir) { - I915_WRITE(GEN6_PMIIR, pm_iir); + raw_reg_write(regs, GEN6_PMIIR, pm_iir); + gen6_rps_irq_handler(&i915->gt.rps, pm_iir); ret = IRQ_HANDLED; - gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); } } - I915_WRITE(DEIER, de_ier); - if (!HAS_PCH_NOP(dev_priv)) - I915_WRITE(SDEIER, sde_ier); + raw_reg_write(regs, DEIER, de_ier); + if (sde_ier) + raw_reg_write(regs, SDEIER, sde_ier); /* IRQs are synced during runtime_suspend, we don't require a wakeref */ - enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); + enable_rpm_wakeref_asserts(&i915->runtime_pm); return ret; } -- 2.20.1 From ville.syrjala at linux.intel.com Mon Jun 1 14:11:32 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 1 Jun 2020 17:11:32 +0300 Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs In-Reply-To: <20200601101516.21018-1-anshuman.gupta@intel.com> References: <20200601101516.21018-1-anshuman.gupta@intel.com> Message-ID: <20200601141132.GK6112@intel.com> On Mon, Jun 01, 2020 at 03:45:16PM +0530, Anshuman Gupta wrote: > Gen12 hw are failing to enable lpsp configuration due to PG3 was left on > due to valid usgae count of POWER_DOMAIN_AUDIO. > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling > a crtc, it should be always i915_audio_component request to get/put > AUDIO_POWER_DOMAIN. > > Cc: stable at vger.kernel.org > Cc: Ville Syrj?l? > Cc: Maarten Lankhorst > Signed-off-by: Anshuman Gupta > --- > drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 6c3b11de2daf..f31a579d7a52 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) > mask |= BIT_ULL(intel_encoder->power_domain); > } > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > + /* > + * Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > + * enable AUDIO power in order to enable a crtc Nothing requires audio power to enable a crtc. What this is saying is that if we want audio then we must enable the audio power. If you didn't want audio then you wouldn't have .has_audio set. That said, looks like audio is moving into the always on well, but not yet in tgl. . > + */ > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && crtc_state->has_audio) > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > if (crtc_state->shared_dpll) > -- > 2.26.2 -- Ville Syrj?l? Intel From stanislav.lisovskiy at intel.com Mon Jun 1 14:12:41 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Mon, 1 Jun 2020 17:12:41 +0300 Subject: [Intel-gfx] [PATCH v1] drm/i915: Fix wrong CDCLK adjustment changes In-Reply-To: <20200601140108.GR30374@kadam> References: <20200526094852.6967-1-stanislav.lisovskiy@intel.com> <20200601140108.GR30374@kadam> Message-ID: <20200601141241.GA21755@intel.com> On Mon, Jun 01, 2020 at 05:01:08PM +0300, Dan Carpenter wrote: > Hi Stanislav, > > url: https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642 > base: git://anongit.freedesktop.org/drm/drm-tip drm-tip > config: i386-randconfig-m021-20200531 (attached as .config) > compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kbuild test robot > Reported-by: Dan Carpenter > > smatch warnings: > drivers/gpu/drm/i915/display/intel_bw.c:453 skl_bw_calc_min_cdclk() error: uninitialized symbol 'pipe'. > > # https://github.com/0day-ci/linux/commit/21b0324886122a396687d977d67eb6ce3caf2b17 > git remote add linux-review https://github.com/0day-ci/linux > git remote update linux-review > git checkout 21b0324886122a396687d977d67eb6ce3caf2b17 > vim +/pipe +453 drivers/gpu/drm/i915/display/intel_bw.c > > 366b6200f76e0f Jani Nikula 2019-08-06 430 > cd19154608610a Stanislav Lisovskiy 2020-05-20 431 int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > cd19154608610a Stanislav Lisovskiy 2020-05-20 432 { > cd19154608610a Stanislav Lisovskiy 2020-05-20 433 struct drm_i915_private *dev_priv = to_i915(state->base.dev); > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 434 struct intel_bw_state *new_bw_state = NULL; > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 435 struct intel_bw_state *old_bw_state = NULL; > cd19154608610a Stanislav Lisovskiy 2020-05-20 436 const struct intel_crtc_state *crtc_state; > cd19154608610a Stanislav Lisovskiy 2020-05-20 437 struct intel_crtc *crtc; > cd19154608610a Stanislav Lisovskiy 2020-05-20 438 int max_bw = 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 439 int slice_id; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 440 enum pipe pipe; > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 441 int i; > cd19154608610a Stanislav Lisovskiy 2020-05-20 442 > cd19154608610a Stanislav Lisovskiy 2020-05-20 443 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 444 enum plane_id plane_id; > cd19154608610a Stanislav Lisovskiy 2020-05-20 445 struct intel_dbuf_bw *crtc_bw; > cd19154608610a Stanislav Lisovskiy 2020-05-20 446 > cd19154608610a Stanislav Lisovskiy 2020-05-20 447 new_bw_state = intel_atomic_get_bw_state(state); > cd19154608610a Stanislav Lisovskiy 2020-05-20 448 if (IS_ERR(new_bw_state)) > cd19154608610a Stanislav Lisovskiy 2020-05-20 449 return PTR_ERR(new_bw_state); > cd19154608610a Stanislav Lisovskiy 2020-05-20 450 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 451 old_bw_state = intel_atomic_get_old_bw_state(state); > 21b0324886122a Stanislav Lisovskiy 2020-05-26 452 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 @453 crtc_bw = &new_bw_state->dbuf_bw[pipe]; > ^^^^ > Not initialized. Probably "i" was intended? Ahh.. Rather silly typo - it should be crtc->pipe. Thanks for spotting. Stan > > cd19154608610a Stanislav Lisovskiy 2020-05-20 454 > cd19154608610a Stanislav Lisovskiy 2020-05-20 455 memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > cd19154608610a Stanislav Lisovskiy 2020-05-20 456 > cd19154608610a Stanislav Lisovskiy 2020-05-20 457 for_each_plane_id_on_crtc(crtc, plane_id) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 458 const struct skl_ddb_entry *plane_alloc = > cd19154608610a Stanislav Lisovskiy 2020-05-20 459 &crtc_state->wm.skl.plane_ddb_y[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 460 const struct skl_ddb_entry *uv_plane_alloc = > cd19154608610a Stanislav Lisovskiy 2020-05-20 461 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 462 unsigned int data_rate = crtc_state->data_rate[plane_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 463 unsigned int dbuf_mask = 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 464 > cd19154608610a Stanislav Lisovskiy 2020-05-20 465 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc); > cd19154608610a Stanislav Lisovskiy 2020-05-20 466 dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc); > cd19154608610a Stanislav Lisovskiy 2020-05-20 467 > cd19154608610a Stanislav Lisovskiy 2020-05-20 468 /* > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 469 * FIXME: To calculate that more properly we probably > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 470 * need to to split per plane data_rate into data_rate_y > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 471 * and data_rate_uv for multiplanar formats in order not > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 472 * to get accounted those twice if they happen to reside > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 473 * on different slices. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 474 * However for pre-icl this would work anyway because > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 475 * we have only single slice and for icl+ uv plane has > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 476 * non-zero data rate. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 477 * So in worst case those calculation are a bit > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 478 * pessimistic, which shouldn't pose any significant > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 479 * problem anyway. > cd19154608610a Stanislav Lisovskiy 2020-05-20 480 */ > cd19154608610a Stanislav Lisovskiy 2020-05-20 481 for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > cd19154608610a Stanislav Lisovskiy 2020-05-20 482 crtc_bw->used_bw[slice_id] += data_rate; > cd19154608610a Stanislav Lisovskiy 2020-05-20 483 } > 21b0324886122a Stanislav Lisovskiy 2020-05-26 484 } > 21b0324886122a Stanislav Lisovskiy 2020-05-26 485 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 486 if (!old_bw_state) > 21b0324886122a Stanislav Lisovskiy 2020-05-26 487 return 0; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 488 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 489 for_each_pipe(dev_priv, pipe) { > 21b0324886122a Stanislav Lisovskiy 2020-05-26 490 struct intel_dbuf_bw *crtc_bw; > 21b0324886122a Stanislav Lisovskiy 2020-05-26 491 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 492 crtc_bw = &new_bw_state->dbuf_bw[pipe]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 493 > cd19154608610a Stanislav Lisovskiy 2020-05-20 494 for_each_dbuf_slice(slice_id) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 495 /* > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 496 * Current experimental observations show that contrary > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 497 * to BSpec we get underruns once we exceed 64 * CDCLK > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 498 * for slices in total. > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 499 * As a temporary measure in order not to keep CDCLK > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 500 * bumped up all the time we calculate CDCLK according > cac91e671ad5dc Stanislav Lisovskiy 2020-05-22 501 * to this formula for overall bw consumed by slices. > cd19154608610a Stanislav Lisovskiy 2020-05-20 502 */ > cd19154608610a Stanislav Lisovskiy 2020-05-20 503 max_bw += crtc_bw->used_bw[slice_id]; > cd19154608610a Stanislav Lisovskiy 2020-05-20 504 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 505 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 506 > 21b0324886122a Stanislav Lisovskiy 2020-05-26 507 new_bw_state->min_cdclk = max_bw / 64; > cd19154608610a Stanislav Lisovskiy 2020-05-20 508 > cd19154608610a Stanislav Lisovskiy 2020-05-20 509 if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > cd19154608610a Stanislav Lisovskiy 2020-05-20 510 int ret = intel_atomic_lock_global_state(&new_bw_state->base); > cd19154608610a Stanislav Lisovskiy 2020-05-20 511 > cd19154608610a Stanislav Lisovskiy 2020-05-20 512 if (ret) > cd19154608610a Stanislav Lisovskiy 2020-05-20 513 return ret; > cd19154608610a Stanislav Lisovskiy 2020-05-20 514 } > cd19154608610a Stanislav Lisovskiy 2020-05-20 515 > cd19154608610a Stanislav Lisovskiy 2020-05-20 516 return 0; > cd19154608610a Stanislav Lisovskiy 2020-05-20 517 } > > --- > 0-DAY CI Kernel Test Service, Intel Corporation > https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org From ville.syrjala at linux.intel.com Mon Jun 1 14:47:55 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 1 Jun 2020 17:47:55 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix global state use-after-frees with a refcount In-Reply-To: <20200601075929.GA2431@intel.com> References: <20200527200245.13184-1-ville.syrjala@linux.intel.com> <20200528193852.GA24971@intel.com> <20200528195852.GA25073@intel.com> <20200529051143.GD6112@intel.com> <20200601075929.GA2431@intel.com> Message-ID: <20200601144755.GL6112@intel.com> On Mon, Jun 01, 2020 at 10:59:29AM +0300, Lisovskiy, Stanislav wrote: > On Fri, May 29, 2020 at 08:11:43AM +0300, Ville Syrj?l? wrote: > > On Thu, May 28, 2020 at 10:58:52PM +0300, Lisovskiy, Stanislav wrote: > > > On Thu, May 28, 2020 at 10:38:52PM +0300, Lisovskiy, Stanislav wrote: > > > > On Wed, May 27, 2020 at 11:02:45PM +0300, Ville Syrjala wrote: > > > > > From: Ville Syrj?l? > > > > > > > > > > While the current locking/serialization of the global state > > > > > suffices for protecting the obj->state access and the actual > > > > > hardware reprogramming, we do have a problem with accessing > > > > > the old/new states during nonblocking commits. > > > > > > > > > > The state computation and swap will be protected by the crtc > > > > > locks, but the commit_tails can finish out of order, thus also > > > > > causing the atomic states to be cleaned up out of order. This > > > > > would mean the commit that started first but finished last has > > > > > had its new state freed as the no-longer-needed old state by the > > > > > other commit. > > > > > > > > > > To fix this let's just refcount the states. obj->state amounts > > > > > to one reference, and the intel_atomic_state holds extra references > > > > > to both its new and old global obj states. > > > > > > > > > > Fixes: 0ef1905ecf2e ("drm/i915: Introduce better global state handling") > > > > > Signed-off-by: Ville Syrj?l? > > > > > --- > > > > > .../gpu/drm/i915/display/intel_global_state.c | 45 ++++++++++++++++--- > > > > > .../gpu/drm/i915/display/intel_global_state.h | 3 ++ > > > > > 2 files changed, 42 insertions(+), 6 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c > > > > > index 212d4ee68205..7a19215ad844 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_global_state.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_global_state.c > > > > > @@ -10,6 +10,28 @@ > > > > > #include "intel_display_types.h" > > > > > #include "intel_global_state.h" > > > > > > > > > > +static void __intel_atomic_global_state_free(struct kref *kref) > > > > > +{ > > > > > + struct intel_global_state *obj_state = > > > > > + container_of(kref, struct intel_global_state, ref); > > > > > + struct intel_global_obj *obj = obj_state->obj; > > > > > + > > > > > + obj->funcs->atomic_destroy_state(obj, obj_state); > > > > > +} > > > > > + > > > > > +static void intel_atomic_global_state_put(struct intel_global_state *obj_state) > > > > > +{ > > > > > + kref_put(&obj_state->ref, __intel_atomic_global_state_free); > > > > > +} > > > > > + > > > > > +static struct intel_global_state * > > > > > +intel_atomic_global_state_get(struct intel_global_state *obj_state) > > > > > +{ > > > > > + kref_get(&obj_state->ref); > > > > > + > > > > > + return obj_state; > > > > > +} > > > > > + > > > > > void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, > > > > > struct intel_global_obj *obj, > > > > > struct intel_global_state *state, > > > > > @@ -17,6 +39,10 @@ void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, > > > > > { > > > > > memset(obj, 0, sizeof(*obj)); > > > > > > > > > > + state->obj = obj; > > > > > + > > > > > + kref_init(&state->ref); > > > > > + > > > > > obj->state = state; > > > > > obj->funcs = funcs; > > > > > list_add_tail(&obj->head, &dev_priv->global_obj_list); > > > > > @@ -28,7 +54,9 @@ void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv) > > > > > > > > > > list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) { > > > > > list_del(&obj->head); > > > > > - obj->funcs->atomic_destroy_state(obj, obj->state); > > > > > + > > > > > + drm_WARN_ON(&dev_priv->drm, kref_read(&obj->state->ref) != 1); > > > > > + intel_atomic_global_state_put(obj->state); > > > > > } > > > > > } > > > > > > > > > > @@ -97,10 +125,14 @@ intel_atomic_get_global_obj_state(struct intel_atomic_state *state, > > > > > if (!obj_state) > > > > > return ERR_PTR(-ENOMEM); > > > > > > > > > > + obj_state->obj = obj; > > > > > obj_state->changed = false; > > > > > > > > > > + kref_init(&obj_state->ref); > > > > > + > > > > > state->global_objs[index].state = obj_state; > > > > > - state->global_objs[index].old_state = obj->state; > > > > > + state->global_objs[index].old_state = > > > > > + intel_atomic_global_state_get(obj->state); > > > > > state->global_objs[index].new_state = obj_state; > > > > > state->global_objs[index].ptr = obj; > > > > > obj_state->state = state; > > > > > @@ -163,7 +195,9 @@ void intel_atomic_swap_global_state(struct intel_atomic_state *state) > > > > > new_obj_state->state = NULL; > > > > > > > > > > state->global_objs[i].state = old_obj_state; > > > > > - obj->state = new_obj_state; > > > > > + > > > > > + intel_atomic_global_state_put(obj->state); > > > > > + obj->state = intel_atomic_global_state_get(new_obj_state); > > > > > } > > > > > } > > > > > > > > > > @@ -172,10 +206,9 @@ void intel_atomic_clear_global_state(struct intel_atomic_state *state) > > > > > int i; > > > > > > > > > > for (i = 0; i < state->num_global_objs; i++) { > > > > > - struct intel_global_obj *obj = state->global_objs[i].ptr; > > > > > + intel_atomic_global_state_put(state->global_objs[i].old_state); > > > > > + intel_atomic_global_state_put(state->global_objs[i].new_state); > > > > > > > > Shouldn't we clean old_state only? > > > > > > > > As I understand in absence of any transaction you now have a pool of > > > > global_obj each has a state with single kref taken. > > > > > > > > So when we are going to get a new state, we do +1 kref to old_state(which is current global obj->state) > > > > in order to prevent it being cleared by competing commit. > > > > However the new state doesn't have any kref taken by that moment. > > > > Then you swap do -1 kref for the old state and do +1 kref for new state, > > > > which means that when you -1 kref again for old state in atomic_clear also, > > > > it will be destroyed, however regarding the new state, as I understand > > > > it still has only single kref grabbed when it was swapped, > > > > so isn't it going to be now removed? unless we are lucky and somebody > > > > haven't grabbed it already as an old_state in the next commit? > > > > > > > > Stan > > > > > > Ah actually I got it - forgot that kref is init as 1. > > > But then you probably don't even need to increment kref for new state > > > when swapping. > > > Before assigning new obj->state you release one kref in swap(which makes sense) > > > Then you just do only intel_atomic_global_state_put(old_state) in atomic_clear > > > and then no need in doing intel_atomic_global_state_get(new_state) during > > > swap. > > > I.e we always call intel_atomic_global_state_get/put only regarding "old" > > > obj->state and each new_state will be disposed when it becomes old_state. > > > > > > IMO the approach of handing off references is just hard to follow. > > Better to just get/put explicitly whenever you assign a pointer. > > I already dislike handing off the original kref_init() reference, > > and almost added a get+put there too. Maybe I really should do that... > > Agree, tbh I don't like the idea that kref_init already implicitly holds > a reference - it even confused me initially. > Typical smartpointer usually increments the ref only when assignment > is done. > > > Reviewed-by: Stanislav Lisovskiy Ta. Pushed. Hopefully few rounds of ci will show whether this fixes things. Though I've also seen some vma related use-after-frees in the logs as well, so there may be further problems elsewhere... -- Ville Syrj?l? Intel From mika.kuoppala at linux.intel.com Mon Jun 1 14:56:55 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 01 Jun 2020 17:56:55 +0300 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_balancer: Disable pre-parser for rewritten batches In-Reply-To: <20200531191307.180023-1-chris@chris-wilson.co.uk> References: <20200531191307.180023-1-chris@chris-wilson.co.uk> Message-ID: <87sgfesuko.fsf@gaia.fi.intel.com> Chris Wilson writes: > As we rewrite the batches on the fly to implement the non-preemptible > lock, we need to tell Tigerlake to read the batch afresh each time. > Amusingly, the disable is a part of an arb-check, so we have to be > careful not to include the arbitration point inside our unpreemptible > loop. > > Signed-off-by: Chris Wilson > --- > tests/i915/gem_exec_balancer.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c > index 026f8347e..0e3b52900 100644 > --- a/tests/i915/gem_exec_balancer.c > +++ b/tests/i915/gem_exec_balancer.c > @@ -1350,6 +1350,11 @@ static void __bonded_dual(int i915, > *out = cycles; > } > > +static uint32_t preparser_disable(void) > +{ > + return 0x5 << 23 | 1 << 8 | 1; /* preparser masked disable */ there is MI_ARB_CHECK > +} > + > static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) > { > uint32_t handle = gem_create(i915, 4096); > @@ -1363,14 +1368,14 @@ static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) > *cs++ = 0; > *cs++ = 0; > > - *cs++ = MI_NOOP; > + *cs++ = preparser_disable(); > *cs++ = MI_NOOP; > *cs++ = MI_NOOP; > *cs++ = MI_NOOP; > > /* wait for them to cancel us */ > *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; > - *cs++ = addr + 16; > + *cs++ = addr + 24; I must be totally confused about the layout as I can't get the +8. You take one nop out and put one arb check in and everything moves with 8? -Mika > *cs++ = 0; > > /* self-heal */ > @@ -1393,14 +1398,14 @@ static uint32_t sync_to(int i915, uint32_t addr, uint32_t target) > > cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); > > - *cs++ = MI_NOOP; > + *cs++ = preparser_disable(); > *cs++ = MI_NOOP; > *cs++ = MI_NOOP; > *cs++ = MI_NOOP; > > /* wait to be cancelled */ > *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; > - *cs++ = addr; > + *cs++ = addr + 8; > *cs++ = 0; > > /* cancel their spin as a compliment */ > -- > 2.27.0.rc2 > > _______________________________________________ > igt-dev mailing list > igt-dev at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/igt-dev From patchwork at emeril.freedesktop.org Mon Jun 1 15:01:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 15:01:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915=3A_lpsp_with_hdmi/dp_outputs?= In-Reply-To: <20200601101516.21018-1-anshuman.gupta@intel.com> References: <20200601101516.21018-1-anshuman.gupta@intel.com> Message-ID: <159102371813.14891.9318720909371907928@emeril.freedesktop.org> == Series Details == Series: drm/i915: lpsp with hdmi/dp outputs URL : https://patchwork.freedesktop.org/series/77866/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8561_full -> Patchwork_17829_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17829_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17829_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17829_full: ### IGT changes ### #### Possible regressions #### * igt at kms_hdmi_inject@inject-audio: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-tglb1/igt at kms_hdmi_inject@inject-audio.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-tglb3/igt at kms_hdmi_inject@inject-audio.html * igt at runner@aborted: - shard-tglb: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-tglb3/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17829_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [PASS][4] -> [FAIL][5] ([i915#1528]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-skl9/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-skl9/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_fenced_exec_thrash@no-spare-fences: - shard-glk: [PASS][6] -> [TIMEOUT][7] ([i915#1958]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-glk5/igt at gem_fenced_exec_thrash@no-spare-fences.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-glk6/igt at gem_fenced_exec_thrash@no-spare-fences.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][8] -> [FAIL][9] ([i915#454]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-iclb3/igt at i915_pm_dc@dc6-psr.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-iclb3/igt at i915_pm_dc@dc6-psr.html * igt at i915_pm_rpm@system-suspend-execbuf: - shard-kbl: [PASS][10] -> [INCOMPLETE][11] ([i915#151] / [i915#155]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-kbl7/igt at i915_pm_rpm@system-suspend-execbuf.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-kbl6/igt at i915_pm_rpm@system-suspend-execbuf.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][12] -> [FAIL][13] ([i915#1119] / [i915#118] / [i915#95]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#1926]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-glk9/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-glk8/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108145] / [i915#265]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109441]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-iclb4/igt at kms_psr@psr2_cursor_plane_onoff.html * igt at kms_setmode@basic: - shard-hsw: [PASS][22] -> [FAIL][23] ([i915#31]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-hsw6/igt at kms_setmode@basic.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-hsw8/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-apl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-apl8/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-apl8/igt at kms_vblank@pipe-b-ts-continuation-suspend.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][26] ([i915#180]) -> [PASS][27] +2 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-apl4/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-apl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-apl: [FAIL][28] ([i915#1930]) -> [PASS][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-apl8/igt at gem_exec_reloc@basic-concurrent0.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-apl8/igt at gem_exec_reloc@basic-concurrent0.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-hsw: [DMESG-WARN][30] ([i915#128]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-hsw4/igt at kms_cursor_legacy@all-pipes-torture-move.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-hsw1/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@flip-vs-suspend at a-edp1}: - shard-skl: [INCOMPLETE][32] ([i915#198]) -> [PASS][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-skl1/igt at kms_flip@flip-vs-suspend at a-edp1.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-skl2/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-kbl: [FAIL][34] ([i915#699] / [i915#93] / [i915#95]) -> [PASS][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-kbl6/igt at kms_flip_tiling@flip-changes-tiling-y.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][36] ([i915#1188]) -> [PASS][37] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-skl5/igt at kms_hdr@bpc-switch.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-skl5/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][38] ([fdo#108145] / [i915#265]) -> [PASS][39] +2 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][40] ([fdo#109441]) -> [PASS][41] +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-iclb5/igt at kms_psr@psr2_sprite_mmap_gtt.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][42] ([i915#180]) -> [PASS][43] [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-kbl4/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-kbl7/igt at kms_vblank@pipe-c-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-hsw: [FAIL][44] ([i915#1542]) -> [PASS][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-hsw6/igt at perf@blocking-parameterized.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-hsw2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][46] ([i915#454]) -> [SKIP][47] ([i915#468]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-tglb5/igt at i915_pm_dc@dc6-psr.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_chamelium@dp-hpd: - shard-glk: [SKIP][48] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][49] ([i915#1958]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-glk5/igt at kms_chamelium@dp-hpd.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-glk6/igt at kms_chamelium@dp-hpd.html * igt at kms_content_protection@lic: - shard-apl: [FAIL][50] ([fdo#110321]) -> [TIMEOUT][51] ([i915#1319] / [i915#1635]) +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8561/shard-apl7/igt at kms_content_protection@lic.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/shard-apl1/igt at kms_content_protection@lic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8561 -> Patchwork_17829 CI-20190529: 20190529 CI_DRM_8561: 989e079eb7172d7423686cab0dd5d4e47a48f3e1 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5688: 33c8411480b4945e44188f82cd6c3a0d53b40485 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17829: 78f04fcced9a26b870739cbc213801bd1b570606 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17829/index.html From patchwork at emeril.freedesktop.org Mon Jun 1 15:22:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 15:22:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/panel=3A_Reduce_race_window_between_bl=5Fupdate=5F?= =?utf-8?q?status_and_bl=5Fenable?= In-Reply-To: <20200601140217.51709-1-sean@poorly.run> References: <20200601140217.51709-1-sean@poorly.run> Message-ID: <159102497648.14891.3467765874422090624@emeril.freedesktop.org> == Series Details == Series: drm/i915/panel: Reduce race window between bl_update_status and bl_enable URL : https://patchwork.freedesktop.org/series/77873/ State : warning == Summary == $ dim checkpatch origin/drm-tip bca376137784 drm/i915/panel: Reduce race window between bl_update_status and bl_enable -:8: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: from userspace (which is stored in panel->backlight.device->props.brightness) total: 0 errors, 1 warnings, 0 checks, 22 lines checked From patchwork at emeril.freedesktop.org Mon Jun 1 15:44:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 15:44:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/panel=3A_Reduce_race_window_between_bl=5Fupdate=5Fstatus_?= =?utf-8?q?and_bl=5Fenable?= In-Reply-To: <20200601140217.51709-1-sean@poorly.run> References: <20200601140217.51709-1-sean@poorly.run> Message-ID: <159102626204.14889.767867458004201234@emeril.freedesktop.org> == Series Details == Series: drm/i915/panel: Reduce race window between bl_update_status and bl_enable URL : https://patchwork.freedesktop.org/series/77873/ State : success == Summary == CI Bug Log - changes from CI_DRM_8565 -> Patchwork_17831 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/index.html Known issues ------------ Here are the changes found in Patchwork_17831 that come from known issues: ### IGT changes ### #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (50 -> 45) ------------------------------ Additional (1): fi-kbl-7560u Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8565 -> Patchwork_17831 CI-20190529: 20190529 CI_DRM_8565: 267bdbf5f8ba7c0931eb6c11a3b9eb893b10fead @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17831: bca3761377846e842068f30f26ae07d5d8b0e42b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bca376137784 drm/i915/panel: Reduce race window between bl_update_status and bl_enable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/index.html From chris at chris-wilson.co.uk Mon Jun 1 15:54:02 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 01 Jun 2020 16:54:02 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_balancer: Disable pre-parser for rewritten batches In-Reply-To: <87sgfesuko.fsf@gaia.fi.intel.com> References: <20200531191307.180023-1-chris@chris-wilson.co.uk> <87sgfesuko.fsf@gaia.fi.intel.com> Message-ID: <159102684249.29407.7177954715956460299@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-01 15:56:55) > Chris Wilson writes: > > > As we rewrite the batches on the fly to implement the non-preemptible > > lock, we need to tell Tigerlake to read the batch afresh each time. > > Amusingly, the disable is a part of an arb-check, so we have to be > > careful not to include the arbitration point inside our unpreemptible > > loop. > > > > Signed-off-by: Chris Wilson > > --- > > tests/i915/gem_exec_balancer.c | 13 +++++++++---- > > 1 file changed, 9 insertions(+), 4 deletions(-) > > > > diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c > > index 026f8347e..0e3b52900 100644 > > --- a/tests/i915/gem_exec_balancer.c > > +++ b/tests/i915/gem_exec_balancer.c > > @@ -1350,6 +1350,11 @@ static void __bonded_dual(int i915, > > *out = cycles; > > } > > > > +static uint32_t preparser_disable(void) > > +{ > > + return 0x5 << 23 | 1 << 8 | 1; /* preparser masked disable */ > > there is MI_ARB_CHECK > > > +} > > + > > static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) > > { > > uint32_t handle = gem_create(i915, 4096); > > @@ -1363,14 +1368,14 @@ static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) > > *cs++ = 0; > > *cs++ = 0; > > > > - *cs++ = MI_NOOP; > > + *cs++ = preparser_disable(); > > *cs++ = MI_NOOP; > > *cs++ = MI_NOOP; > > *cs++ = MI_NOOP; > > > > /* wait for them to cancel us */ > > *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; > > - *cs++ = addr + 16; > > + *cs++ = addr + 24; > > I must be totally confused about the layout as I can't get > the +8. You take one nop out and put one arb check in > and everything moves with 8? It's just skipping over the MI_ARB_CHECK, +4, aligned to the next qword because some old habits die hard. -Chris From patchwork at emeril.freedesktop.org Mon Jun 1 16:10:30 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 16:10:30 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Trim_the_ironlake+_irq_handler_=28rev2=29?= In-Reply-To: <20200601140355.20243-1-chris@chris-wilson.co.uk> References: <20200601140355.20243-1-chris@chris-wilson.co.uk> Message-ID: <159102783055.14889.774209744078017446@emeril.freedesktop.org> == Series Details == Series: drm/i915: Trim the ironlake+ irq handler (rev2) URL : https://patchwork.freedesktop.org/series/77871/ State : success == Summary == CI Bug Log - changes from CI_DRM_8565 -> Patchwork_17832 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/index.html Known issues ------------ Here are the changes found in Patchwork_17832 that come from known issues: ### IGT changes ### #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8565 -> Patchwork_17832 CI-20190529: 20190529 CI_DRM_8565: 267bdbf5f8ba7c0931eb6c11a3b9eb893b10fead @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17832: b61fdbb8c3873e10973bd087a9811566cbb289e9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b61fdbb8c387 drm/i915: Trim the ironlake+ irq handler == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/index.html From chris at chris-wilson.co.uk Mon Jun 1 16:19:42 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 17:19:42 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Whitelist context-local timestamp in the gen9 cmdparser Message-ID: <20200601161942.30854-1-chris@chris-wilson.co.uk> Allow batch buffers to read their own _local_ cumulative HW runtime of their logical context. Fixes: 0f2f39758341 ("drm/i915: Add gen9 BCS cmdparsing") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: # v5.4+ --- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 189b573d02be..372354d33f55 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -572,6 +572,9 @@ struct drm_i915_reg_descriptor { #define REG32(_reg, ...) \ { .addr = (_reg), __VA_ARGS__ } +#define REG32_IDX(_reg, idx) \ + { .addr = _reg(idx) } + /* * Convenience macro for adding 64-bit registers. * @@ -669,6 +672,7 @@ static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), REG32(BCS_SWCTRL), REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), + REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE), REG64_IDX(BCS_GPR, 0), REG64_IDX(BCS_GPR, 1), REG64_IDX(BCS_GPR, 2), -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 1 17:05:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 17:05:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Whitelist_context-local_timestamp_in_the_gen9_cmdparse?= =?utf-8?q?r?= In-Reply-To: <20200601161942.30854-1-chris@chris-wilson.co.uk> References: <20200601161942.30854-1-chris@chris-wilson.co.uk> Message-ID: <159103111332.14888.2762502027441823627@emeril.freedesktop.org> == Series Details == Series: drm/i915: Whitelist context-local timestamp in the gen9 cmdparser URL : https://patchwork.freedesktop.org/series/77877/ State : success == Summary == CI Bug Log - changes from CI_DRM_8565 -> Patchwork_17833 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17833/index.html Known issues ------------ Here are the changes found in Patchwork_17833 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#227]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17833/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][3] ([i915#62]) -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17833/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8565 -> Patchwork_17833 CI-20190529: 20190529 CI_DRM_8565: 267bdbf5f8ba7c0931eb6c11a3b9eb893b10fead @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17833: 9d9cdd9da66e9c37b9a91aaecba4b86b10fbeee0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9d9cdd9da66e drm/i915: Whitelist context-local timestamp in the gen9 cmdparser == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17833/index.html From liviu.dudau at arm.com Mon Jun 1 17:19:59 2020 From: liviu.dudau at arm.com (Liviu Dudau) Date: Mon, 1 Jun 2020 18:19:59 +0100 Subject: [Intel-gfx] [PATCH] drm/atomic-helper: reset vblank on crtc reset In-Reply-To: <20200527095332.1439425-1-daniel.vetter@ffwll.ch> References: <20200527094757.1414174-2-daniel.vetter@ffwll.ch> <20200527095332.1439425-1-daniel.vetter@ffwll.ch> Message-ID: <20200601171959.GO159988@e110455-lin.cambridge.arm.com> On Wed, May 27, 2020 at 11:53:32AM +0200, Daniel Vetter wrote: > Only when vblanks are supported ofc. > > Some drivers do this already, but most unfortunately missed it. This > opens up bugs after driver load, before the crtc is enabled for the > first time. syzbot spotted this when loading vkms as a secondary > output. Given how many drivers are buggy it's best to solve this once > and for all in shared helper code. > > Aside from moving the few existing calls to drm_crtc_vblank_reset into > helpers (i915 doesn't use helpers, so keeps its own) I think the > regression risk is minimal: atomic helpers already rely on drivers > calling drm_crtc_vblank_on/off correctly in their hooks when they > support vblanks. And driver that's failing to handle vblanks after > this is missing those calls already, and vblanks could only work by > accident when enabling a CRTC for the first time right after boot. > > Big thanks to Tetsuo for helping track down what's going wrong here. > > There's only a few drivers which already had the necessary call and > needed some updating: > - komeda, atmel and tidss also needed to be changed to call > __drm_atomic_helper_crtc_reset() intead of open coding it > - tegra and msm even had it in the same place already, just code > motion, and malidp already uses __drm_atomic_helper_crtc_reset(). > > Only call left is in i915, which doesn't use drm_mode_config_reset, > but has its own fastboot infrastructure. So that's the only case where > we actually want this in the driver still. > > I've also reviewed all other drivers which set up vblank support with > drm_vblank_init. After the previous patch fixing mxsfb all atomic > drivers do call drm_crtc_vblank_on/off as they should, the remaining > drivers are either legacy kms or legacy dri1 drivers, so not affected > by this change to atomic helpers. > > v2: Use the drm_dev_has_vblank() helper. > > Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb > Reported-by: Tetsuo Handa > Reported-by: syzbot+0871b14ca2e2fb64f6e3 at syzkaller.appspotmail.com > Cc: Tetsuo Handa > Cc: "James (Qian) Wang" > Cc: Liviu Dudau > Cc: Mihail Atanassov > Cc: Brian Starkey > Cc: Sam Ravnborg > Cc: Boris Brezillon > Cc: Nicolas Ferre > Cc: Alexandre Belloni > Cc: Ludovic Desroches > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Thomas Zimmermann > Cc: David Airlie > Cc: Daniel Vetter > Cc: Thierry Reding > Cc: Jonathan Hunter > Cc: Jyri Sarha > Cc: Tomi Valkeinen > Cc: Rob Clark > Cc: Sean Paul > Cc: Brian Masney > Cc: Emil Velikov > Cc: zhengbin > Cc: Thomas Gleixner > Cc: linux-tegra at vger.kernel.org > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++----- > drivers/gpu/drm/arm/malidp_drv.c | 1 - For the komeda and malidp drivers: Acked-by: Liviu Dudau Best regards, Liviu > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 ++----- > drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ > drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 -- > drivers/gpu/drm/tegra/dc.c | 1 - > drivers/gpu/drm/tidss/tidss_crtc.c | 3 +-- > drivers/gpu/drm/tidss/tidss_kms.c | 4 ---- > 8 files changed, 9 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > index 56bd938961ee..f33418d6e1a0 100644 > --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > @@ -492,10 +492,8 @@ static void komeda_crtc_reset(struct drm_crtc *crtc) > crtc->state = NULL; > > state = kzalloc(sizeof(*state), GFP_KERNEL); > - if (state) { > - crtc->state = &state->base; > - crtc->state->crtc = crtc; > - } > + if (state) > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > } > > static struct drm_crtc_state * > @@ -616,7 +614,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, > return err; > > drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); > - drm_crtc_vblank_reset(crtc); > > crtc->port = kcrtc->master->of_output_port; > > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > index c2507b7d8512..02904392e370 100644 > --- a/drivers/gpu/drm/arm/malidp_drv.c > +++ b/drivers/gpu/drm/arm/malidp_drv.c > @@ -870,7 +870,6 @@ static int malidp_bind(struct device *dev) > drm->irq_enabled = true; > > ret = drm_vblank_init(drm, drm->mode_config.num_crtc); > - drm_crtc_vblank_reset(&malidp->crtc); > if (ret < 0) { > DRM_ERROR("failed to initialise vblank\n"); > goto vblank_fail; > diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > index 10985134ce0b..ce246b96330b 100644 > --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > @@ -411,10 +411,8 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) > } > > state = kzalloc(sizeof(*state), GFP_KERNEL); > - if (state) { > - crtc->state = &state->base; > - crtc->state->crtc = crtc; > - } > + if (state) > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > } > > static struct drm_crtc_state * > @@ -528,7 +526,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) > } > > drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); > - drm_crtc_vblank_reset(&crtc->base); > > drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); > drm_crtc_enable_color_mgmt(&crtc->base, 0, false, > diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c > index 8fce6a115dfe..9ad74045158e 100644 > --- a/drivers/gpu/drm/drm_atomic_state_helper.c > +++ b/drivers/gpu/drm/drm_atomic_state_helper.c > @@ -32,6 +32,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -93,6 +94,9 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, > if (crtc_state) > __drm_atomic_helper_crtc_state_reset(crtc_state, crtc); > > + if (drm_dev_has_vblank(crtc->dev)) > + drm_crtc_vblank_reset(crtc); > + > crtc->state = crtc_state; > } > EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > index ca3368c828d0..9606185c284b 100644 > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > @@ -1117,8 +1117,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc) > mdp5_crtc_destroy_state(crtc, crtc->state); > > __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); > - > - drm_crtc_vblank_reset(crtc); > } > > static const struct drm_crtc_funcs mdp5_crtc_funcs = { > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > index 83f31c6e891c..9b308b572eac 100644 > --- a/drivers/gpu/drm/tegra/dc.c > +++ b/drivers/gpu/drm/tegra/dc.c > @@ -1168,7 +1168,6 @@ static void tegra_crtc_reset(struct drm_crtc *crtc) > tegra_crtc_atomic_destroy_state(crtc, crtc->state); > > __drm_atomic_helper_crtc_reset(crtc, &state->base); > - drm_crtc_vblank_reset(crtc); > } > > static struct drm_crtc_state * > diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c > index 89a226912de8..4d01c4af61cd 100644 > --- a/drivers/gpu/drm/tidss/tidss_crtc.c > +++ b/drivers/gpu/drm/tidss/tidss_crtc.c > @@ -352,8 +352,7 @@ static void tidss_crtc_reset(struct drm_crtc *crtc) > return; > } > > - crtc->state = &tcrtc->base; > - crtc->state->crtc = crtc; > + __drm_atomic_helper_crtc_reset(crtc, &tcrtc->base); > } > > static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) > diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c > index 4b99e9fa84a5..e6ab59eed259 100644 > --- a/drivers/gpu/drm/tidss/tidss_kms.c > +++ b/drivers/gpu/drm/tidss/tidss_kms.c > @@ -278,10 +278,6 @@ int tidss_modeset_init(struct tidss_device *tidss) > if (ret) > return ret; > > - /* Start with vertical blanking interrupt reporting disabled. */ > - for (i = 0; i < tidss->num_crtcs; ++i) > - drm_crtc_vblank_reset(tidss->crtcs[i]); > - > drm_mode_config_reset(ddev); > > dev_dbg(tidss->dev, "%s done\n", __func__); > -- > 2.26.2 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ?\_(?)_/? From stanislav.lisovskiy at intel.com Mon Jun 1 17:30:58 2020 From: stanislav.lisovskiy at intel.com (Stanislav Lisovskiy) Date: Mon, 1 Jun 2020 20:30:58 +0300 Subject: [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes Message-ID: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> Previous patch didn't take into account all pipes but only those in state, which could cause wrong CDCLK conclcusions and calculations. Also there was a severe issue with min_cdclk being assigned to 0 every compare cycle. Too bad this was found by me only after merge. This could be also causing the issues in test, however not clear - anyway marking this as fixing the "Adjust CDCLK accordingly to our DBuf bw needs". v2: - s/pipe/crtc->pipe/ - save a bit of instructions by skipping inactive pipes, without getting 0 DBuf slice mask for it. Signed-off-by: Stanislav Lisovskiy Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") --- drivers/gpu/drm/i915/display/intel_bw.c | 52 +++++++++++++------- drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++--- drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- 3 files changed, 55 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index a79bd7aeb03b..bd060404d249 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) struct intel_crtc *crtc; int max_bw = 0; int slice_id; + enum pipe pipe; int i; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { @@ -447,10 +448,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) if (IS_ERR(new_bw_state)) return PTR_ERR(new_bw_state); + old_bw_state = intel_atomic_get_old_bw_state(state); + crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); + if (!crtc_state->hw.active) + continue; + for_each_plane_id_on_crtc(crtc, plane_id) { const struct skl_ddb_entry *plane_alloc = &crtc_state->wm.skl.plane_ddb_y[plane_id]; @@ -478,6 +484,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) crtc_bw->used_bw[slice_id] += data_rate; } + } + + if (!old_bw_state) + return 0; + + for_each_pipe(dev_priv, pipe) { + struct intel_dbuf_bw *crtc_bw; + + crtc_bw = &new_bw_state->dbuf_bw[pipe]; for_each_dbuf_slice(slice_id) { /* @@ -490,14 +505,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) */ max_bw += crtc_bw->used_bw[slice_id]; } - - new_bw_state->min_cdclk = max_bw / 64; - - old_bw_state = intel_atomic_get_old_bw_state(state); } - if (!old_bw_state) - return 0; + new_bw_state->min_cdclk = max_bw / 64; if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { int ret = intel_atomic_lock_global_state(&new_bw_state->base); @@ -511,34 +521,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) { - int i; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_bw_state *new_bw_state = NULL; + struct intel_bw_state *old_bw_state = NULL; const struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; int min_cdclk = 0; - struct intel_bw_state *new_bw_state = NULL; - struct intel_bw_state *old_bw_state = NULL; + enum pipe pipe; + int i; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct intel_cdclk_state *cdclk_state; - new_bw_state = intel_atomic_get_bw_state(state); if (IS_ERR(new_bw_state)) return PTR_ERR(new_bw_state); - cdclk_state = intel_atomic_get_cdclk_state(state); - if (IS_ERR(cdclk_state)) - return PTR_ERR(cdclk_state); - - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); - - new_bw_state->min_cdclk = min_cdclk; - old_bw_state = intel_atomic_get_old_bw_state(state); } if (!old_bw_state) return 0; + for_each_pipe(dev_priv, pipe) { + struct intel_cdclk_state *cdclk_state; + + cdclk_state = intel_atomic_get_new_cdclk_state(state); + if (!cdclk_state) + return 0; + + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); + } + + new_bw_state->min_cdclk = min_cdclk; + if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { int ret = intel_atomic_lock_global_state(&new_bw_state->base); diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index f9b0fc7317de..08468b121d02 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) { struct intel_atomic_state *state = cdclk_state->base.state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_bw_state *bw_state = NULL; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int min_cdclk, i; + enum pipe pipe; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) if (min_cdclk < 0) return min_cdclk; + bw_state = intel_atomic_get_bw_state(state); + if (IS_ERR(bw_state)) + return PTR_ERR(bw_state); + if (cdclk_state->min_cdclk[i] == min_cdclk) continue; @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) } min_cdclk = cdclk_state->force_min_cdclk; + for_each_pipe(dev_priv, pipe) { + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct intel_bw_state *bw_state; - - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); - - bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(bw_state)) - return PTR_ERR(bw_state); + if (!bw_state) + continue; min_cdclk = max(bw_state->min_cdclk, min_cdclk); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f40b909952cc..66af8f3053ed 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, bool *need_cdclk_calc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - int i; + struct intel_cdclk_state *new_cdclk_state; struct intel_plane_state *plane_state; + struct intel_bw_state *new_bw_state; struct intel_plane *plane; + int min_cdclk = 0; + enum pipe pipe; int ret; - struct intel_cdclk_state *new_cdclk_state; - struct intel_crtc_state *new_crtc_state; - struct intel_crtc *crtc; + int i; /* * active_planes bitmask has been updated, and potentially * affected planes are part of the state. We can now @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, if (ret) return ret; - if (!new_cdclk_state) - return 0; - - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { - struct intel_bw_state *bw_state; - int min_cdclk = 0; + new_bw_state = intel_atomic_get_new_bw_state(state); - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); + if (!new_cdclk_state || !new_bw_state) + return 0; - bw_state = intel_atomic_get_bw_state(state); - if (IS_ERR(bw_state)) - return PTR_ERR(bw_state); + for_each_pipe(dev_priv, pipe) { + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); /* * Currently do this change only if we need to increase */ - if (bw_state->min_cdclk > min_cdclk) + if (new_bw_state->min_cdclk > min_cdclk) *need_cdclk_calc = true; } -- 2.24.1.485.gad05a3d8e5 From jose.souza at intel.com Mon Jun 1 17:54:44 2020 From: jose.souza at intel.com (Souza, Jose) Date: Mon, 1 Jun 2020 17:54:44 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Update_TC_DP_vswing_table?= In-Reply-To: <159081460746.9483.14982003828132717008@emeril.freedesktop.org> References: <20200529232757.37832-1-jose.souza@intel.com> <159081460746.9483.14982003828132717008@emeril.freedesktop.org> Message-ID: On Sat, 2020-05-30 at 04:56 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl: Update TC DP vswing table > URL : https://patchwork.freedesktop.org/series/77806/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_8557_full -> Patchwork_17824_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. Pushed to dinq, thanks for the review Khaled. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17824_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_suspend@basic-s3: > - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-kbl3/igt at gem_exec_suspend@basic-s3.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-kbl7/igt at gem_exec_suspend@basic-s3.html > > * igt at i915_suspend@debugfs-reader: > - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl1/igt at i915_suspend@debugfs-reader.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl4/igt at i915_suspend@debugfs-reader.html > > * igt at i915_suspend@fence-restore-untiled: > - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180] / [i915#93] / [i915#95]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-kbl6/igt at i915_suspend@fence-restore-untiled.html > > * igt at i915_suspend@forcewake: > - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([i915#155]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-kbl7/igt at i915_suspend@forcewake.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-kbl3/igt at i915_suspend@forcewake.html > > * igt at kms_color@pipe-c-legacy-gamma: > - shard-hsw: [PASS][9] -> [INCOMPLETE][10] ([i915#61]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-hsw1/igt at kms_color@pipe-c-legacy-gamma.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-hsw6/igt at kms_color@pipe-c-legacy-gamma.html > > * igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding: > - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#54]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-kbl6/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html > - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl1/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl6/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html > - shard-apl: [PASS][15] -> [FAIL][16] ([i915#54]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl4/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl7/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_psr@psr2_sprite_mmap_cpu: > - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_cpu.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-iclb1/igt at kms_psr@psr2_sprite_mmap_cpu.html > > > #### Possible fixes #### > > * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: > - shard-skl: [FAIL][21] ([i915#1528]) -> [PASS][22] > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl6/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl4/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html > > * igt at gem_softpin@noreloc-s3: > - shard-apl: [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +2 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl4/igt at gem_softpin@noreloc-s3.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl2/igt at gem_softpin@noreloc-s3.html > > * igt at gem_vm_create@isolation: > - shard-apl: [TIMEOUT][25] ([i915#1635]) -> [PASS][26] +3 similar issues > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl7/igt at gem_vm_create@isolation.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl6/igt at gem_vm_create@isolation.html > > * igt at gen9_exec_parse@allowed-all: > - shard-apl: [DMESG-WARN][27] ([i915#1436] / [i915#716]) -> [PASS][28] > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl4/igt at gen9_exec_parse@allowed-all.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl2/igt at gen9_exec_parse@allowed-all.html > > * igt at kms_color@pipe-a-ctm-blue-to-red: > - shard-skl: [FAIL][29] ([i915#129]) -> [PASS][30] > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl4/igt at kms_color@pipe-a-ctm-blue-to-red.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl1/igt at kms_color@pipe-a-ctm-blue-to-red.html > > * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: > - shard-skl: [FAIL][31] ([i915#54]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl10/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html > > * igt at kms_fbcon_fbt@psr-suspend: > - shard-skl: [INCOMPLETE][33] ([i915#69]) -> [PASS][34] > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl7/igt at kms_fbcon_fbt@psr-suspend.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl3/igt at kms_fbcon_fbt@psr-suspend.html > > * {igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1}: > - shard-skl: [FAIL][35] ([i915#1928]) -> [PASS][36] > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl5/igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl6/igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1.html > > * {igt at kms_flip@flip-vs-suspend at b-dp1}: > - shard-kbl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +4 similar issues > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-kbl7/igt at kms_flip@flip-vs-suspend at b-dp1.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-kbl4/igt at kms_flip@flip-vs-suspend at b-dp1.html > > * igt at kms_hdr@bpc-switch-dpms: > - shard-skl: [FAIL][39] ([i915#1188]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [FAIL][41] ([fdo#108145] / [i915#265]) -> [PASS][42] +3 similar issues > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_psr@psr2_primary_mmap_cpu: > - shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +5 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-iclb8/igt at kms_psr@psr2_primary_mmap_cpu.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][45] ([i915#588]) -> [SKIP][46] ([i915#658]) > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at i915_pm_dc@dc6-dpms: > - shard-tglb: [SKIP][47] ([i915#468]) -> [FAIL][48] ([i915#454]) > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-tglb8/igt at i915_pm_dc@dc6-dpms.html > > * igt at kms_content_protection@legacy: > - shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319] / [i915#1635]) > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl2/igt at kms_content_protection@legacy.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl8/igt at kms_content_protection@legacy.html > > * igt at kms_content_protection@srm: > - shard-apl: [TIMEOUT][51] ([i915#1319]) -> [FAIL][52] ([fdo#110321]) > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl7/igt at kms_content_protection@srm.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl8/igt at kms_content_protection@srm.html > > * igt at kms_content_protection@uevent: > - shard-kbl: [FAIL][53] ([i915#357]) -> [FAIL][54] ([i915#357] / [i915#93] / [i915#95]) > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-kbl3/igt at kms_content_protection@uevent.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-kbl7/igt at kms_content_protection@uevent.html > - shard-apl: [FAIL][55] ([i915#357]) -> [FAIL][56] ([i915#357] / [i915#95]) > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl7/igt at kms_content_protection@uevent.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl2/igt at kms_content_protection@uevent.html > > * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: > - shard-glk: [DMESG-WARN][57] ([i915#1926]) -> [DMESG-FAIL][58] ([i915#1925] / [i915#1926]) > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-glk2/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html > > * igt at kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt: > - shard-apl: [TIMEOUT][59] ([i915#1635]) -> [SKIP][60] ([fdo#109271]) > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl7/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl6/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html > > * igt at kms_plane_alpha_blend@pipe-c-alpha-basic: > - shard-apl: [FAIL][61] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][62] ([fdo#108145] / [i915#265]) > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8557/shard-apl7/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/shard-apl8/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#129]: https://gitlab.freedesktop.org/drm/intel/issues/129 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 > [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#357]: https://gitlab.freedesktop.org/drm/intel/issues/357 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8557 -> Patchwork_17824 > > CI-20190529: 20190529 > CI_DRM_8557: cd02c2938ef1c5e2ca72b8240918151060dfbf92 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5684: bd399f5eb8263bb4a84ae6a5bb1a13d329e0515d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17824: 345dd71a89fb0aefcf50fb1c225825ee3cf3cf76 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17824/index.html From mika.kuoppala at linux.intel.com Mon Jun 1 18:23:17 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 01 Jun 2020 21:23:17 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Whitelist context-local timestamp in the gen9 cmdparser In-Reply-To: <20200601161942.30854-1-chris@chris-wilson.co.uk> References: <20200601161942.30854-1-chris@chris-wilson.co.uk> Message-ID: <87d06iir1m.fsf@gaia.fi.intel.com> Chris Wilson writes: > Allow batch buffers to read their own _local_ cumulative HW runtime of > their logical context. > > Fixes: 0f2f39758341 ("drm/i915: Add gen9 BCS cmdparsing") > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: # v5.4+ Reviewed-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 189b573d02be..372354d33f55 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -572,6 +572,9 @@ struct drm_i915_reg_descriptor { > #define REG32(_reg, ...) \ > { .addr = (_reg), __VA_ARGS__ } > > +#define REG32_IDX(_reg, idx) \ > + { .addr = _reg(idx) } > + > /* > * Convenience macro for adding 64-bit registers. > * > @@ -669,6 +672,7 @@ static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { > REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), > REG32(BCS_SWCTRL), > REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), > + REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE), > REG64_IDX(BCS_GPR, 0), > REG64_IDX(BCS_GPR, 1), > REG64_IDX(BCS_GPR, 2), > -- > 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 19:08:09 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 20:08:09 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200601190809.1174616-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 224 +++++++++++++++++++++++++++++++++ 1 file changed, 224 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..0ec21bf54 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,227 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + 1000000000); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void async_delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + if (offset_in_page(cs) & 4) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +timed_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + async_delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + unsigned long *out) +{ + const int batches_per_frame = 3; + struct drm_i915_gem_exec_object2 prev = + timed_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + timed_create(i915, ctx, e, frame_ns / batches_per_frame); + struct timespec tv = {}; + unsigned long count = 0; + + igt_nsec_elapsed(&tv); + igt_until_timeout(timeout) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + for (int n = 0; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + gem_sync(i915, prev.handle); + igt_swap(prev, next); + count++; + } + gem_sync(i915, prev.handle); + *out = igt_nsec_elapsed(&tv) / count; + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); +} + +static int ul_cmp(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout) +{ + const int frame_ns = 16666 * 1000; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + int nchild = n - 1; /* odd for easy medians */ + + memset(result, 0, nchild * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + + fair_child(i915, ctx, e, frame_ns / nchild, + timeout, &result[child]); + + gem_context_destroy(i915, ctx); + } + igt_waitchildren(); + + qsort(result, nchild, sizeof(*result), ul_cmp); + igt_info("%d clients, range: [%lu, %lu], median: %lu\n", + nchild, result[0], result[nchild-1], result[nchild/2]); + + igt_assert(4 * result[0] > 3 * result[nchild-1]); + igt_assert(3 * result[0] < 4 * result[nchild-1]); + + igt_assert(4 * result[nchild/2] > 3 * frame_ns); + igt_assert(3 * result[nchild/2] < 4 * frame_ns); + } +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +2810,9 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fairness", fd, e) + fairness(fd, e, 3); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From patchwork at emeril.freedesktop.org Mon Jun 1 19:13:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 19:13:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_wrong_CDCLK_adjustment_changes_=28rev2=29?= In-Reply-To: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> References: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> Message-ID: <159103881703.14889.4674882538265758382@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix wrong CDCLK adjustment changes (rev2) URL : https://patchwork.freedesktop.org/series/77654/ State : success == Summary == CI Bug Log - changes from CI_DRM_8566 -> Patchwork_17834 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/index.html Known issues ------------ Here are the changes found in Patchwork_17834 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [TIMEOUT][1] ([i915#1288] / [i915#1958]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][3] ([fdo#109271]) -> [FAIL][4] ([i915#62]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1288]: https://gitlab.freedesktop.org/drm/intel/issues/1288 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (50 -> 45) ------------------------------ Additional (1): fi-kbl-soraka Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8566 -> Patchwork_17834 CI-20190529: 20190529 CI_DRM_8566: fed6b89dd6f3c4e2e909805815c5728b1fd65ce5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17834: 6bfe3f7a62bd1c9345f4789886a8030a10e81d32 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6bfe3f7a62bd drm/i915: Fix wrong CDCLK adjustment changes == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/index.html From chris at chris-wilson.co.uk Mon Jun 1 19:53:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 20:53:23 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness In-Reply-To: <20200601190809.1174616-1-chris@chris-wilson.co.uk> References: <20200601190809.1174616-1-chris@chris-wilson.co.uk> Message-ID: <20200601195323.1288550-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 245 +++++++++++++++++++++++++++++++++ 1 file changed, 245 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..5d91e94a3 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,246 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + 1000000000); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void async_delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + if (offset_in_page(cs) & 4) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +timed_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + async_delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + unsigned int flags, + unsigned long *out) +#define F_PACING 0x1 +{ + const int batches_per_frame = 3; + struct drm_i915_gem_exec_object2 prev = + timed_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + timed_create(i915, ctx, e, frame_ns / batches_per_frame); + struct timespec tv = {}; + unsigned long count = 0; + int p_fence = -1, n_fence = -1; + + igt_nsec_elapsed(&tv); + igt_until_timeout(timeout) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~I915_EXEC_FENCE_OUT; + for (int n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + if (flags & F_PACING && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + gem_sync(i915, prev.handle); + *out = igt_nsec_elapsed(&tv) / count; + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); +} + +static int ul_cmp(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + int nchild = n - 1; /* odd for easy medians */ + + memset(result, 0, nchild * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + + fair_child(i915, ctx, e, frame_ns / nchild, + timeout, flags, &result[child]); + + gem_context_destroy(i915, ctx); + } + igt_waitchildren(); + + qsort(result, nchild, sizeof(*result), ul_cmp); + igt_info("%d clients, range: [%lu, %lu], median: %lu\n", + nchild, result[0], result[nchild-1], result[nchild/2]); + + igt_assert(4 * result[0] > 3 * result[nchild-1]); + igt_assert(3 * result[0] < 4 * result[nchild-1]); + + igt_assert(4 * result[nchild/2] > 3 * frame_ns); + igt_assert(3 * result[nchild/2] < 4 * frame_ns); + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +2829,11 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fairness", fd, e) + fairness(fd, e, 3, F_PACING); + test_each_engine_store("unfairness", fd, e) + fairness(fd, e, 3, 0); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From jose.souza at intel.com Mon Jun 1 20:23:08 2020 From: jose.souza at intel.com (Souza, Jose) Date: Mon, 1 Jun 2020 20:23:08 +0000 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Fix ibx max vswing/preemph In-Reply-To: <20200512174145.3186-3-ville.syrjala@linux.intel.com> References: <20200512174145.3186-1-ville.syrjala@linux.intel.com> <20200512174145.3186-3-ville.syrjala@linux.intel.com> Message-ID: On Tue, 2020-05-12 at 20:41 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? > > IBX supports vswing level 3 and pre-emphasis level 3. Don't > limit it to level 2 for those. Matches https://01.org/linuxgraphics/documentation/driver-documentation-prms/2010-intel-core-processor-family Reviewed-by: Jos? Roberto de Souza < jose.souza at intel.com> > > Signed-off-by: Ville Syrj?l? > --- > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 7541264ff4e9..0924e041e1bf 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -3958,7 +3958,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) > if (HAS_DDI(dev_priv)) > return intel_ddi_dp_voltage_max(encoder); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || > - (HAS_PCH_CPT(dev_priv) && port != PORT_A)) > + (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; > else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) > return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; > @@ -3976,7 +3976,7 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing) > if (HAS_DDI(dev_priv)) { > return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing); > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || > - (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { > + (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { > switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { > case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: > return DP_TRAIN_PRE_EMPH_LEVEL_3; From chris at chris-wilson.co.uk Mon Jun 1 20:35:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 21:35:49 +0100 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Set timeslicing priority from queue In-Reply-To: <20200601203550.19192-1-chris@chris-wilson.co.uk> References: <20200601203550.19192-1-chris@chris-wilson.co.uk> Message-ID: <20200601203550.19192-2-chris@chris-wilson.co.uk> If we only submit the first port, leaving the second empty yet have ready requests pending in the queue, use that to set the timeslicing priority (i.e. the priority at which we will decided to enabling timeslicing and evict the currently active context if the queue is of equal priority after its quantum expired). Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6fc0966b75ff..7a3c55e3ad9d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1962,7 +1962,7 @@ static int switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq) { if (list_is_last(&rq->sched.link, &engine->active.requests)) - return INT_MIN; + return engine->execlists.queue_priority_hint; return rq_prio(list_next_entry(rq, sched.link)); } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 20:35:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 21:35:48 +0100 Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Trim set_timer_ms() intervals Message-ID: <20200601203550.19192-1-chris@chris-wilson.co.uk> Use the plain msec_to_jiffies() rather than the _timeout variant so we round down and do not add an extra jiffy to our interval. For example, with timeslicing we do not want to err on the longer side as any fairness depends on catching hogging contexts on the GPU. Bring on CFS. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c index e28eae4a8f70..f42a9e9a0b4f 100644 --- a/drivers/gpu/drm/i915/i915_utils.c +++ b/drivers/gpu/drm/i915/i915_utils.c @@ -91,7 +91,7 @@ void set_timer_ms(struct timer_list *t, unsigned long timeout) return; } - timeout = msecs_to_jiffies_timeout(timeout); + timeout = msecs_to_jiffies(timeout); /* * Paranoia to make sure the compiler computes the timeout before -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 1 20:35:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 21:35:50 +0100 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Always check to enable timeslicing if not submitting In-Reply-To: <20200601203550.19192-1-chris@chris-wilson.co.uk> References: <20200601203550.19192-1-chris@chris-wilson.co.uk> Message-ID: <20200601203550.19192-3-chris@chris-wilson.co.uk> We may choose not to submit for a number of reasons, yet not fill both ELSP. In which case we must start timeslicing (there will be no ACK event on which to hook the start) if the queue would benefit from the currently active context being evicted. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7a3c55e3ad9d..8e611470c121 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2358,10 +2358,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last->context == rq->context) goto done; - if (i915_request_has_sentinel(last)) { - start_timeslice(engine, rq_prio(rq)); + if (i915_request_has_sentinel(last)) goto done; - } /* * If GVT overrides us we only ever submit @@ -2442,6 +2440,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) set_preempt_timeout(engine, *active); execlists_submit_ports(engine); } else { + start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); } -- 2.20.1 From manasi.d.navare at intel.com Mon Jun 1 20:37:19 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Mon, 1 Jun 2020 13:37:19 -0700 Subject: [Intel-gfx] [PATCH v1] drm/i915: Fix wrong CDCLK adjustment changes In-Reply-To: <20200601074954.GA2239@intel.com> References: <20200526094852.6967-1-stanislav.lisovskiy@intel.com> <20200529235738.GA3731@intel.com> <20200601074954.GA2239@intel.com> Message-ID: <20200601203719.GB3731@intel.com> On Mon, Jun 01, 2020 at 10:49:54AM +0300, Lisovskiy, Stanislav wrote: > On Fri, May 29, 2020 at 04:57:38PM -0700, Manasi Navare wrote: > > On Tue, May 26, 2020 at 12:48:52PM +0300, Stanislav Lisovskiy wrote: > > > Previous patch didn't take into account all pipes > > > but only those in state, which could cause wrong > > > CDCLK conclcusions and calculations. > > > Also there was a severe issue with min_cdclk being > > > assigned to 0 every compare cycle. > > > > > > Too bad this was found by me only after merge. > > > This could be also causing the issues in test, however > > > not clear - anyway marking this as fixing the > > > "Adjust CDCLK accordingly to our DBuf bw needs". > > > > > > Signed-off-by: Stanislav Lisovskiy > > > Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") > > > --- > > > drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++++++-------- > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++++--- > > > drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- > > > 3 files changed, 53 insertions(+), 43 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > > > index a79bd7aeb03b..8096138abecc 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > > @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > struct intel_crtc *crtc; > > > int max_bw = 0; > > > int slice_id; > > > + enum pipe pipe; > > > int i; > > > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > @@ -447,7 +448,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > if (IS_ERR(new_bw_state)) > > > return PTR_ERR(new_bw_state); > > > > > > - crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; > > > + old_bw_state = intel_atomic_get_old_bw_state(state); > > > + > > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > > > memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > > > > > > @@ -478,6 +481,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > > > crtc_bw->used_bw[slice_id] += data_rate; > > > } > > > + } > > > + > > > + if (!old_bw_state) > > > + return 0; > > > + > > > + for_each_pipe(dev_priv, pipe) { > > > + struct intel_dbuf_bw *crtc_bw; > > > + > > > > So the condition !old_bw_state() will make sure we loop through > > only the active pipes and compute crtc_bw only for those right? > > > > Manasi > > Well, in fact this condition just checks if we had any crtcs in state - > otherwise there were no changes, so bw_state global object doesn't need > to be changed. Whenever something happens to crtc we should have it > in the state, so this condition just checks if we need to modify bw_state > or not. > > Regarding active/inactive pipes - currently for inactive pipes, > we are going to get 0 dbuf slice mask, so we just won't accumulate any data > rate for those. So if the pipe got disabled we will get less required min_cdclk > which against old_bw_state, which will mean that we are going to acquire > the global state lock for writing. > > In fact we could optimize the code by skipping inactive pipes completely > i.e don't even calculate dbuf slice mask, > which will be 0. However the logic and the end result would be > the same anyway. Okay yes this makes sense, thanks for the clarification. So would be it be an easy change to add a condition to return for an inactive pipe? Manasi > > Stan > > > > > > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > > > > > for_each_dbuf_slice(slice_id) { > > > /* > > > @@ -490,14 +502,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > */ > > > max_bw += crtc_bw->used_bw[slice_id]; > > > } > > > - > > > - new_bw_state->min_cdclk = max_bw / 64; > > > - > > > - old_bw_state = intel_atomic_get_old_bw_state(state); > > > } > > > > > > - if (!old_bw_state) > > > - return 0; > > > + new_bw_state->min_cdclk = max_bw / 64; > > > > > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > > @@ -511,34 +518,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > > > > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) > > > { > > > - int i; > > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > > + struct intel_bw_state *new_bw_state = NULL; > > > + struct intel_bw_state *old_bw_state = NULL; > > > const struct intel_crtc_state *crtc_state; > > > struct intel_crtc *crtc; > > > int min_cdclk = 0; > > > - struct intel_bw_state *new_bw_state = NULL; > > > - struct intel_bw_state *old_bw_state = NULL; > > > + enum pipe pipe; > > > + int i; > > > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > - struct intel_cdclk_state *cdclk_state; > > > - > > > new_bw_state = intel_atomic_get_bw_state(state); > > > if (IS_ERR(new_bw_state)) > > > return PTR_ERR(new_bw_state); > > > > > > - cdclk_state = intel_atomic_get_cdclk_state(state); > > > - if (IS_ERR(cdclk_state)) > > > - return PTR_ERR(cdclk_state); > > > - > > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > > - > > > - new_bw_state->min_cdclk = min_cdclk; > > > - > > > old_bw_state = intel_atomic_get_old_bw_state(state); > > > } > > > > > > if (!old_bw_state) > > > return 0; > > > > > > + for_each_pipe(dev_priv, pipe) { > > > + struct intel_cdclk_state *cdclk_state; > > > + > > > + cdclk_state = intel_atomic_get_new_cdclk_state(state); > > > + if (!cdclk_state) > > > + return 0; > > > + > > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > > + } > > > + > > > + new_bw_state->min_cdclk = min_cdclk; > > > + > > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > > > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > index f9b0fc7317de..08468b121d02 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > > > static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > > { > > > struct intel_atomic_state *state = cdclk_state->base.state; > > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > > + struct intel_bw_state *bw_state = NULL; > > > struct intel_crtc *crtc; > > > struct intel_crtc_state *crtc_state; > > > int min_cdclk, i; > > > + enum pipe pipe; > > > > > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > int ret; > > > @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > > if (min_cdclk < 0) > > > return min_cdclk; > > > > > > + bw_state = intel_atomic_get_bw_state(state); > > > + if (IS_ERR(bw_state)) > > > + return PTR_ERR(bw_state); > > > + > > > if (cdclk_state->min_cdclk[i] == min_cdclk) > > > continue; > > > > > > @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > > > } > > > > > > min_cdclk = cdclk_state->force_min_cdclk; > > > + for_each_pipe(dev_priv, pipe) { > > > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > > > > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > > > - struct intel_bw_state *bw_state; > > > - > > > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > > - > > > - bw_state = intel_atomic_get_bw_state(state); > > > - if (IS_ERR(bw_state)) > > > - return PTR_ERR(bw_state); > > > + if (!bw_state) > > > + continue; > > > > > > min_cdclk = max(bw_state->min_cdclk, min_cdclk); > > > } > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index f40b909952cc..66af8f3053ed 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > > bool *need_cdclk_calc) > > > { > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > > - int i; > > > + struct intel_cdclk_state *new_cdclk_state; > > > struct intel_plane_state *plane_state; > > > + struct intel_bw_state *new_bw_state; > > > struct intel_plane *plane; > > > + int min_cdclk = 0; > > > + enum pipe pipe; > > > int ret; > > > - struct intel_cdclk_state *new_cdclk_state; > > > - struct intel_crtc_state *new_crtc_state; > > > - struct intel_crtc *crtc; > > > + int i; > > > /* > > > * active_planes bitmask has been updated, and potentially > > > * affected planes are part of the state. We can now > > > @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > > > if (ret) > > > return ret; > > > > > > - if (!new_cdclk_state) > > > - return 0; > > > - > > > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > > - struct intel_bw_state *bw_state; > > > - int min_cdclk = 0; > > > + new_bw_state = intel_atomic_get_new_bw_state(state); > > > > > > - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > > > + if (!new_cdclk_state || !new_bw_state) > > > + return 0; > > > > > > - bw_state = intel_atomic_get_bw_state(state); > > > - if (IS_ERR(bw_state)) > > > - return PTR_ERR(bw_state); > > > + for_each_pipe(dev_priv, pipe) { > > > + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); > > > > > > /* > > > * Currently do this change only if we need to increase > > > */ > > > - if (bw_state->min_cdclk > min_cdclk) > > > + if (new_bw_state->min_cdclk > min_cdclk) > > > *need_cdclk_calc = true; > > > } > > > > > > -- > > > 2.24.1.485.gad05a3d8e5 > > > From manasi.d.navare at intel.com Mon Jun 1 20:43:19 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Mon, 1 Jun 2020 13:43:19 -0700 Subject: [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes In-Reply-To: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> References: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> Message-ID: <20200601204319.GC3731@intel.com> On Mon, Jun 01, 2020 at 08:30:58PM +0300, Stanislav Lisovskiy wrote: > Previous patch didn't take into account all pipes > but only those in state, which could cause wrong > CDCLK conclcusions and calculations. > Also there was a severe issue with min_cdclk being > assigned to 0 every compare cycle. > > Too bad this was found by me only after merge. > This could be also causing the issues in test, however > not clear - anyway marking this as fixing the > "Adjust CDCLK accordingly to our DBuf bw needs". > > v2: - s/pipe/crtc->pipe/ > - save a bit of instructions by > skipping inactive pipes, without > getting 0 DBuf slice mask for it. > > Signed-off-by: Stanislav Lisovskiy > Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") Looks good to me, Reviewed-by: Manasi Navare Manasi > --- > drivers/gpu/drm/i915/display/intel_bw.c | 52 +++++++++++++------- > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++--- > drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- > 3 files changed, 55 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index a79bd7aeb03b..bd060404d249 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > struct intel_crtc *crtc; > int max_bw = 0; > int slice_id; > + enum pipe pipe; > int i; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > @@ -447,10 +448,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > if (IS_ERR(new_bw_state)) > return PTR_ERR(new_bw_state); > > + old_bw_state = intel_atomic_get_old_bw_state(state); > + > crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; > > memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > > + if (!crtc_state->hw.active) > + continue; > + > for_each_plane_id_on_crtc(crtc, plane_id) { > const struct skl_ddb_entry *plane_alloc = > &crtc_state->wm.skl.plane_ddb_y[plane_id]; > @@ -478,6 +484,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > crtc_bw->used_bw[slice_id] += data_rate; > } > + } > + > + if (!old_bw_state) > + return 0; > + > + for_each_pipe(dev_priv, pipe) { > + struct intel_dbuf_bw *crtc_bw; > + > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > for_each_dbuf_slice(slice_id) { > /* > @@ -490,14 +505,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > */ > max_bw += crtc_bw->used_bw[slice_id]; > } > - > - new_bw_state->min_cdclk = max_bw / 64; > - > - old_bw_state = intel_atomic_get_old_bw_state(state); > } > > - if (!old_bw_state) > - return 0; > + new_bw_state->min_cdclk = max_bw / 64; > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > @@ -511,34 +521,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) > { > - int i; > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_bw_state *new_bw_state = NULL; > + struct intel_bw_state *old_bw_state = NULL; > const struct intel_crtc_state *crtc_state; > struct intel_crtc *crtc; > int min_cdclk = 0; > - struct intel_bw_state *new_bw_state = NULL; > - struct intel_bw_state *old_bw_state = NULL; > + enum pipe pipe; > + int i; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > - struct intel_cdclk_state *cdclk_state; > - > new_bw_state = intel_atomic_get_bw_state(state); > if (IS_ERR(new_bw_state)) > return PTR_ERR(new_bw_state); > > - cdclk_state = intel_atomic_get_cdclk_state(state); > - if (IS_ERR(cdclk_state)) > - return PTR_ERR(cdclk_state); > - > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > - > - new_bw_state->min_cdclk = min_cdclk; > - > old_bw_state = intel_atomic_get_old_bw_state(state); > } > > if (!old_bw_state) > return 0; > > + for_each_pipe(dev_priv, pipe) { > + struct intel_cdclk_state *cdclk_state; > + > + cdclk_state = intel_atomic_get_new_cdclk_state(state); > + if (!cdclk_state) > + return 0; > + > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > + } > + > + new_bw_state->min_cdclk = min_cdclk; > + > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index f9b0fc7317de..08468b121d02 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > { > struct intel_atomic_state *state = cdclk_state->base.state; > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_bw_state *bw_state = NULL; > struct intel_crtc *crtc; > struct intel_crtc_state *crtc_state; > int min_cdclk, i; > + enum pipe pipe; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > int ret; > @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > if (min_cdclk < 0) > return min_cdclk; > > + bw_state = intel_atomic_get_bw_state(state); > + if (IS_ERR(bw_state)) > + return PTR_ERR(bw_state); > + > if (cdclk_state->min_cdclk[i] == min_cdclk) > continue; > > @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > } > > min_cdclk = cdclk_state->force_min_cdclk; > + for_each_pipe(dev_priv, pipe) { > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > - struct intel_bw_state *bw_state; > - > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > - > - bw_state = intel_atomic_get_bw_state(state); > - if (IS_ERR(bw_state)) > - return PTR_ERR(bw_state); > + if (!bw_state) > + continue; > > min_cdclk = max(bw_state->min_cdclk, min_cdclk); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f40b909952cc..66af8f3053ed 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > bool *need_cdclk_calc) > { > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > - int i; > + struct intel_cdclk_state *new_cdclk_state; > struct intel_plane_state *plane_state; > + struct intel_bw_state *new_bw_state; > struct intel_plane *plane; > + int min_cdclk = 0; > + enum pipe pipe; > int ret; > - struct intel_cdclk_state *new_cdclk_state; > - struct intel_crtc_state *new_crtc_state; > - struct intel_crtc *crtc; > + int i; > /* > * active_planes bitmask has been updated, and potentially > * affected planes are part of the state. We can now > @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > if (ret) > return ret; > > - if (!new_cdclk_state) > - return 0; > - > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > - struct intel_bw_state *bw_state; > - int min_cdclk = 0; > + new_bw_state = intel_atomic_get_new_bw_state(state); > > - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > + if (!new_cdclk_state || !new_bw_state) > + return 0; > > - bw_state = intel_atomic_get_bw_state(state); > - if (IS_ERR(bw_state)) > - return PTR_ERR(bw_state); > + for_each_pipe(dev_priv, pipe) { > + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); > > /* > * Currently do this change only if we need to increase > */ > - if (bw_state->min_cdclk > min_cdclk) > + if (new_bw_state->min_cdclk > min_cdclk) > *need_cdclk_calc = true; > } > > -- > 2.24.1.485.gad05a3d8e5 > From patchwork at emeril.freedesktop.org Mon Jun 1 21:16:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 21:16:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/i915=3A_Trim_set=5Ftimer=5Fms?= =?utf-8?q?=28=29_intervals?= In-Reply-To: <20200601203550.19192-1-chris@chris-wilson.co.uk> References: <20200601203550.19192-1-chris@chris-wilson.co.uk> Message-ID: <159104618326.14891.17244694518895694765@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915: Trim set_timer_ms() intervals URL : https://patchwork.freedesktop.org/series/77888/ State : success == Summary == CI Bug Log - changes from CI_DRM_8567 -> Patchwork_17835 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/index.html Changes ------- No changes found Participating hosts (49 -> 44) ------------------------------ Additional (2): fi-skl-lmem fi-cfl-8109u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8567 -> Patchwork_17835 CI-20190529: 20190529 CI_DRM_8567: d36c7a9807541df70739a5917cbbab42fdf66a29 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17835: 183dd61a0a8d0940db360620100f6455738ceffe @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 183dd61a0a8d drm/i915/gt: Always check to enable timeslicing if not submitting dfd64e60999a drm/i915/gt: Set timeslicing priority from queue 7737d0a8b16f drm/i915: Trim set_timer_ms() intervals == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/index.html From chris at chris-wilson.co.uk Mon Jun 1 21:17:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 1 Jun 2020 22:17:21 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness In-Reply-To: <20200601190809.1174616-1-chris@chris-wilson.co.uk> References: <20200601190809.1174616-1-chris@chris-wilson.co.uk> Message-ID: <20200601211721.1345043-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 253 +++++++++++++++++++++++++++++++++ 1 file changed, 253 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..d58d926b1 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,254 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + 1000000000); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void async_delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + if (offset_in_page(cs) & 4) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +timed_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + async_delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + unsigned int flags, + unsigned long *out) +#define F_PACING 0x1 +{ + const int batches_per_frame = 3; + struct drm_i915_gem_exec_object2 prev = + timed_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + timed_create(i915, ctx, e, frame_ns / batches_per_frame); + struct timespec tv = {}; + unsigned long count = 0; + int p_fence = -1, n_fence = -1; + + igt_nsec_elapsed(&tv); + igt_until_timeout(timeout) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~I915_EXEC_FENCE_OUT; + for (int n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + if (flags & F_PACING && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + gem_sync(i915, prev.handle); + *out = igt_nsec_elapsed(&tv) / count; + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); +} + +static int ul_cmp(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + const int nchild = n - 1; /* odd for easy medians */ + const int iqr_lo = nchild / 4; + const int iqr_hi = (3 * nchild + 3) / 4 - 1; + unsigned long iqr; + + memset(result, 0, nchild * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + + fair_child(i915, ctx, e, frame_ns / nchild, + timeout, flags, &result[child]); + + gem_context_destroy(i915, ctx); + } + igt_waitchildren(); + + qsort(result, nchild, sizeof(*result), ul_cmp); + igt_info("%d clients, range: [%lu, %lu], iqr: [%lu, %lu], median: %lu\n", + nchild, + result[0], result[nchild - 1], + result[iqr_lo], result[iqr_hi], + result[nchild / 2]); + + /* Median within 10% of target */ + igt_assert(10 * result[nchild / 2] > 9 * frame_ns && + 9 * result[nchild / 2] < 10 * frame_ns); + + /* Variance [inter-quartile range] is less than 33% of median */ + iqr = result[iqr_hi] - result[iqr_lo]; + igt_assert(3 * iqr < result[nchild / 2]); + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +2837,11 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fairness", fd, e) + fairness(fd, e, 3, F_PACING); + test_each_engine_store("unfairness", fd, e) + fairness(fd, e, 3, 0); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From patchwork at emeril.freedesktop.org Mon Jun 1 21:40:08 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 21:40:08 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/panel=3A_Reduce_race_window_between_bl=5Fupdate=5Fstatus_?= =?utf-8?q?and_bl=5Fenable?= In-Reply-To: <20200601140217.51709-1-sean@poorly.run> References: <20200601140217.51709-1-sean@poorly.run> Message-ID: <159104760832.14891.14077587564673633188@emeril.freedesktop.org> == Series Details == Series: drm/i915/panel: Reduce race window between bl_update_status and bl_enable URL : https://patchwork.freedesktop.org/series/77873/ State : success == Summary == CI Bug Log - changes from CI_DRM_8565_full -> Patchwork_17831_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17831_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at bcs0: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl7/igt at gem_ctx_persistence@engines-mixed-process at bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-skl3/igt at gem_ctx_persistence@engines-mixed-process at bcs0.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-kbl2/igt at gen9_exec_parse@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-kbl6/igt at gen9_exec_parse@allowed-all.html * igt at kms_cursor_legacy@2x-cursor-vs-flip-legacy: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([i915#1926] / [i915#61]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-hsw2/igt at kms_cursor_legacy@2x-cursor-vs-flip-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-hsw4/igt at kms_cursor_legacy@2x-cursor-vs-flip-legacy.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#1925] / [i915#1926]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk1/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-glk6/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_draw_crc@fill-fb: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl8/igt at kms_draw_crc@fill-fb.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl7/igt at kms_draw_crc@fill-fb.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl7/igt at kms_hdr@bpc-switch.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-skl3/igt at kms_hdr@bpc-switch.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-iclb1/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_primary_render: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb2/igt at kms_psr@psr2_primary_render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-iclb1/igt at kms_psr@psr2_primary_render.html * igt at perf@stress-open-close: - shard-kbl: [PASS][23] -> [INCOMPLETE][24] ([i915#1847] / [i915#1855]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-kbl6/igt at perf@stress-open-close.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-kbl7/igt at perf@stress-open-close.html #### Possible fixes #### * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [FAIL][25] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-glk2/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [INCOMPLETE][27] ([i915#1927] / [i915#58] / [k.org#198133]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk1/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-glk1/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html * {igt at kms_flip@flip-vs-suspend at a-dp1}: - shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +4 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl1/igt at kms_flip@flip-vs-suspend at a-dp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl2/igt at kms_flip@flip-vs-suspend at a-dp1.html * {igt at kms_flip@flip-vs-suspend at a-edp1}: - shard-skl: [INCOMPLETE][31] ([i915#198]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl10/igt at kms_flip@flip-vs-suspend at a-edp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-skl10/igt at kms_flip@flip-vs-suspend at a-edp1.html * {igt at kms_flip@plain-flip-ts-check-interruptible at b-hdmi-a1}: - shard-glk: [FAIL][33] ([i915#1928]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk8/igt at kms_flip@plain-flip-ts-check-interruptible at b-hdmi-a1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-glk2/igt at kms_flip@plain-flip-ts-check-interruptible at b-hdmi-a1.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][35] ([fdo#108145] / [i915#265]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][37] ([fdo#109441]) -> [PASS][38] +5 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb5/igt at kms_psr@psr2_cursor_mmap_cpu.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_setmode@basic: - shard-apl: [FAIL][39] ([i915#31]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl8/igt at kms_setmode@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl7/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][41] ([i915#1542]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb3/igt at perf@blocking-parameterized.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-iclb6/igt at perf@blocking-parameterized.html - shard-hsw: [FAIL][43] ([i915#1542]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-hsw6/igt at perf@blocking-parameterized.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-hsw1/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][45] ([i915#658]) -> [SKIP][46] ([i915#588]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb5/igt at i915_pm_dc@dc3co-vpb-simulation.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][47] ([i915#468]) -> [FAIL][48] ([i915#454]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-tglb3/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at kms_content_protection@atomic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][51] ([i915#1319]) -> [TIMEOUT][52] ([i915#1319] / [i915#1635]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at kms_content_protection@legacy.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [FAIL][53] ([fdo#110321]) -> [TIMEOUT][54] ([i915#1319]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl4/igt at kms_content_protection@lic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl8/igt at kms_content_protection@lic.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][55] ([i915#1925] / [i915#1926]) -> [DMESG-WARN][56] ([i915#1926]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk2/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-glk1/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [FAIL][57] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][58] ([fdo#108145] / [i915#265]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl2/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/shard-apl1/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1847]: https://gitlab.freedesktop.org/drm/intel/issues/1847 [i915#1855]: https://gitlab.freedesktop.org/drm/intel/issues/1855 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8565 -> Patchwork_17831 CI-20190529: 20190529 CI_DRM_8565: 267bdbf5f8ba7c0931eb6c11a3b9eb893b10fead @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17831: bca3761377846e842068f30f26ae07d5d8b0e42b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17831/index.html From jani.nikula at intel.com Mon Jun 1 21:55:08 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Tue, 2 Jun 2020 00:55:08 +0300 Subject: [Intel-gfx] [CI 1/3] drm/i915/params: don't expose inject_probe_failure in debugfs Message-ID: <20200601215510.18379-1-jani.nikula@intel.com> The parameter only makes sense as a module parameter only. Fixes: c43c5a8818d4 ("drm/i915/params: add i915 parameters to debugfs") Cc: Juha-Pekka Heikkil? Cc: Venkata Sandeep Dhanalakota Reviewed-by: Juha-Pekka Heikkila Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_params.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 45323732f099..4f21bfffbf0e 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -64,7 +64,7 @@ struct drm_printer; param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \ param(int, edp_vswing, 0, 0400) \ param(unsigned int, reset, 3, 0600) \ - param(unsigned int, inject_probe_failure, 0, 0600) \ + param(unsigned int, inject_probe_failure, 0, 0) \ param(int, fastboot, -1, 0600) \ param(int, enable_dpcd_backlight, -1, 0600) \ param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \ -- 2.20.1 From jani.nikula at intel.com Mon Jun 1 21:55:09 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Tue, 2 Jun 2020 00:55:09 +0300 Subject: [Intel-gfx] [CI 2/3] drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions In-Reply-To: <20200601215510.18379-1-jani.nikula@intel.com> References: <20200601215510.18379-1-jani.nikula@intel.com> Message-ID: <20200601215510.18379-2-jani.nikula@intel.com> fake_lmem_start does not need to be mutable via module param sysfs. It's only used during driver probe. Fixes: 1629224324b6 ("drm/i915/lmem: add the fake lmem region") Cc: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Reviewed-by: Rodrigo Vivi Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index add00ec1f787..a3dde770226d 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -173,7 +173,7 @@ i915_param_named(enable_gvt, bool, 0400, #endif #if IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM) -i915_param_named_unsafe(fake_lmem_start, ulong, 0600, +i915_param_named_unsafe(fake_lmem_start, ulong, 0400, "Fake LMEM start offset (default: 0)"); #endif -- 2.20.1 From jani.nikula at intel.com Mon Jun 1 21:55:10 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Tue, 2 Jun 2020 00:55:10 +0300 Subject: [Intel-gfx] [CI 3/3] drm/i915/params: prevent changing module params runtime In-Reply-To: <20200601215510.18379-1-jani.nikula@intel.com> References: <20200601215510.18379-1-jani.nikula@intel.com> Message-ID: <20200601215510.18379-3-jani.nikula@intel.com> Only support runtime changes through the debugfs. i915.verbose_state_checks remains an exception, and is not exposed via debugfs. This depends on IGT having been updated to use the debugfs for modifying the parameters. Cc: Juha-Pekka Heikkil? Cc: Venkata Sandeep Dhanalakota Reviewed-by: Juha-Pekka Heikkila Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_params.c | 38 +++++++++++++++++++----------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index a3dde770226d..ace44ad7e6df 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -40,6 +40,15 @@ struct i915_params i915_modparams __read_mostly = { #undef MEMBER }; +/* + * Note: As a rule, keep module parameter sysfs permissions read-only + * 0400. Runtime changes are only supported through i915 debugfs. + * + * For any exceptions requiring write access and runtime changes through module + * parameter sysfs, prevent debugfs file creation by setting the parameter's + * debugfs mode to 0. + */ + i915_param_named(modeset, int, 0400, "Use kernel modesetting [KMS] (0=disable, " "1=on, -1=force vga console preference [default])"); @@ -49,7 +58,7 @@ i915_param_named_unsafe(enable_dc, int, 0400, "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; " "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)"); -i915_param_named_unsafe(enable_fbc, int, 0600, +i915_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " "(default: -1 (use per-chip default))"); @@ -57,7 +66,7 @@ i915_param_named_unsafe(lvds_channel_mode, int, 0400, "Specify LVDS channel mode " "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); -i915_param_named_unsafe(panel_use_ssc, int, 0600, +i915_param_named_unsafe(panel_use_ssc, int, 0400, "Use Spread Spectrum Clock with panels [LVDS/eDP] " "(default: auto from VBT)"); @@ -65,25 +74,25 @@ i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400, "Override/Ignore selection of SDVO panel mode in the VBT " "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); -i915_param_named_unsafe(reset, int, 0600, +i915_param_named_unsafe(reset, int, 0400, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); i915_param_named_unsafe(vbt_firmware, charp, 0400, "Load VBT from specified file under /lib/firmware"); #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) -i915_param_named(error_capture, bool, 0600, +i915_param_named(error_capture, bool, 0400, "Record the GPU state following a hang. " "This information in /sys/class/drm/card/error is vital for " "triaging and debugging hangs."); #endif -i915_param_named_unsafe(enable_hangcheck, bool, 0600, +i915_param_named_unsafe(enable_hangcheck, bool, 0400, "Periodically check GPU activity for detecting hangs. " "WARNING: Disabling this can cause system wide hangs. " "(default: true)"); -i915_param_named_unsafe(enable_psr, int, 0600, +i915_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " "(0=disabled, 1=enabled) " "Default: -1 (use per-chip default)"); @@ -96,22 +105,22 @@ i915_param_named_unsafe(disable_power_well, int, 0400, "Disable display power wells when possible " "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)"); -i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)"); +i915_param_named_unsafe(enable_ips, int, 0400, "Enable IPS (default: true)"); -i915_param_named(fastboot, int, 0600, +i915_param_named(fastboot, int, 0400, "Try to skip unnecessary mode sets at boot time " "(0=disabled, 1=enabled) " "Default: -1 (use per-chip default)"); -i915_param_named_unsafe(load_detect_test, bool, 0600, +i915_param_named_unsafe(load_detect_test, bool, 0400, "Force-enable the VGA load detect code for testing (default:false). " "For developers only."); -i915_param_named_unsafe(force_reset_modeset_test, bool, 0600, +i915_param_named_unsafe(force_reset_modeset_test, bool, 0400, "Force a modeset during gpu reset for testing (default:false). " "For developers only."); -i915_param_named_unsafe(invert_brightness, int, 0600, +i915_param_named_unsafe(invert_brightness, int, 0400, "Invert backlight brightness " "(-1 force normal, 0 machine defaults, 1 force inversion), please " "report PCI device ID, subsystem vendor and subsystem device ID " @@ -121,10 +130,11 @@ i915_param_named_unsafe(invert_brightness, int, 0600, i915_param_named(disable_display, bool, 0400, "Disable display (default: false)"); -i915_param_named(mmio_debug, int, 0600, +i915_param_named(mmio_debug, int, 0400, "Enable the MMIO debug code for the first N failures (default: off). " "This may negatively affect performance."); +/* Special case writable file */ i915_param_named(verbose_state_checks, bool, 0600, "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); @@ -155,7 +165,7 @@ i915_param_named_unsafe(huc_firmware_path, charp, 0400, i915_param_named_unsafe(dmc_firmware_path, charp, 0400, "DMC firmware path to use instead of the default one"); -i915_param_named_unsafe(enable_dp_mst, bool, 0600, +i915_param_named_unsafe(enable_dp_mst, bool, 0400, "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)"); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) @@ -163,7 +173,7 @@ i915_param_named_unsafe(inject_probe_failure, uint, 0400, "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); #endif -i915_param_named(enable_dpcd_backlight, int, 0600, +i915_param_named(enable_dpcd_backlight, int, 0400, "Enable support for DPCD backlight control" "(-1=use per-VBT LFP backlight type setting [default], 0=disabled, 1=enabled)"); -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 1 22:06:36 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 22:06:36 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5BCI=2C1/3=5D_drm/i915/params=3A_don?= =?utf-8?q?=27t_expose_inject=5Fprobe=5Ffailure_in_debugfs?= In-Reply-To: <20200601215510.18379-1-jani.nikula@intel.com> References: <20200601215510.18379-1-jani.nikula@intel.com> Message-ID: <159104919636.14888.17683520732103784577@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/params: don't expose inject_probe_failure in debugfs URL : https://patchwork.freedesktop.org/series/77889/ State : warning == Summary == $ dim checkpatch origin/drm-tip acf490748fe6 drm/i915/params: don't expose inject_probe_failure in debugfs 5cc66b985a6b drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions -:27: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #27: FILE: drivers/gpu/drm/i915/i915_params.c:177: +i915_param_named_unsafe(fake_lmem_start, ulong, 0400, "Fake LMEM start offset (default: 0)"); total: 0 errors, 0 warnings, 1 checks, 8 lines checked 28eb95e6e065 drm/i915/params: prevent changing module params runtime -:48: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #48: FILE: drivers/gpu/drm/i915/i915_params.c:62: +i915_param_named_unsafe(enable_fbc, int, 0400, "Enable frame buffer compression for power savings " -:57: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #57: FILE: drivers/gpu/drm/i915/i915_params.c:70: +i915_param_named_unsafe(panel_use_ssc, int, 0400, "Use Spread Spectrum Clock with panels [LVDS/eDP] " -:66: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #66: FILE: drivers/gpu/drm/i915/i915_params.c:78: +i915_param_named_unsafe(reset, int, 0400, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); -:74: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #74: FILE: drivers/gpu/drm/i915/i915_params.c:85: +i915_param_named(error_capture, bool, 0400, "Record the GPU state following a hang. " -:81: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #81: FILE: drivers/gpu/drm/i915/i915_params.c:91: +i915_param_named_unsafe(enable_hangcheck, bool, 0400, "Periodically check GPU activity for detecting hangs. " -:87: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #87: FILE: drivers/gpu/drm/i915/i915_params.c:96: +i915_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " -:99: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #99: FILE: drivers/gpu/drm/i915/i915_params.c:111: +i915_param_named(fastboot, int, 0400, "Try to skip unnecessary mode sets at boot time " -:105: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #105: FILE: drivers/gpu/drm/i915/i915_params.c:116: +i915_param_named_unsafe(load_detect_test, bool, 0400, "Force-enable the VGA load detect code for testing (default:false). " -:110: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #110: FILE: drivers/gpu/drm/i915/i915_params.c:120: +i915_param_named_unsafe(force_reset_modeset_test, bool, 0400, "Force a modeset during gpu reset for testing (default:false). " -:115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #115: FILE: drivers/gpu/drm/i915/i915_params.c:124: +i915_param_named_unsafe(invert_brightness, int, 0400, "Invert backlight brightness " -:124: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #124: FILE: drivers/gpu/drm/i915/i915_params.c:134: +i915_param_named(mmio_debug, int, 0400, "Enable the MMIO debug code for the first N failures (default: off). " -:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #137: FILE: drivers/gpu/drm/i915/i915_params.c:169: +i915_param_named_unsafe(enable_dp_mst, bool, 0400, "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)"); -:146: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #146: FILE: drivers/gpu/drm/i915/i915_params.c:177: +i915_param_named(enable_dpcd_backlight, int, 0400, "Enable support for DPCD backlight control" total: 0 errors, 0 warnings, 13 checks, 115 lines checked From patchwork at emeril.freedesktop.org Mon Jun 1 22:07:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 22:07:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5BCI=2C1/3=5D_drm/i915/params=3A_don=27t_?= =?utf-8?q?expose_inject=5Fprobe=5Ffailure_in_debugfs?= In-Reply-To: <20200601215510.18379-1-jani.nikula@intel.com> References: <20200601215510.18379-1-jani.nikula@intel.com> Message-ID: <159104926236.14889.5394450610278373174@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/params: don't expose inject_probe_failure in debugfs URL : https://patchwork.freedesktop.org/series/77889/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Mon Jun 1 22:22:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 22:22:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Trim_the_ironlake+_irq_handler_=28rev2=29?= In-Reply-To: <20200601140355.20243-1-chris@chris-wilson.co.uk> References: <20200601140355.20243-1-chris@chris-wilson.co.uk> Message-ID: <159105017823.14890.4044105011287589585@emeril.freedesktop.org> == Series Details == Series: drm/i915: Trim the ironlake+ irq handler (rev2) URL : https://patchwork.freedesktop.org/series/77871/ State : success == Summary == CI Bug Log - changes from CI_DRM_8565_full -> Patchwork_17832_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17832_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_suspend@sysfs-reader: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-kbl7/igt at i915_suspend@sysfs-reader.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-kbl7/igt at i915_suspend@sysfs-reader.html * igt at kms_draw_crc@fill-fb: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl8/igt at kms_draw_crc@fill-fb.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl2/igt at kms_draw_crc@fill-fb.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][5] -> [FAIL][6] ([i915#1188]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108145] / [i915#265]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109642] / [fdo#111068]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-iclb5/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_primary_render: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb2/igt at kms_psr@psr2_primary_render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-iclb5/igt at kms_psr@psr2_primary_render.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][15] ([i915#1930]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_reloc@basic-concurrent16}: - shard-skl: [FAIL][17] ([i915#1930]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl8/igt at gem_exec_reloc@basic-concurrent16.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-skl10/igt at gem_exec_reloc@basic-concurrent16.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [FAIL][19] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-glk6/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [INCOMPLETE][21] ([i915#1927] / [i915#58] / [k.org#198133]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk1/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-glk1/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [FAIL][23] ([i915#72]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk7/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-glk9/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][25] ([fdo#109349]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb1/igt at kms_dp_dsc@basic-dsc-enable-edp.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * {igt at kms_flip@flip-vs-suspend at a-dp1}: - shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl1/igt at kms_flip@flip-vs-suspend at a-dp1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl1/igt at kms_flip@flip-vs-suspend at a-dp1.html * {igt at kms_flip@flip-vs-suspend at a-edp1}: - shard-skl: [INCOMPLETE][29] ([i915#198]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-skl10/igt at kms_flip@flip-vs-suspend at a-edp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-skl7/igt at kms_flip@flip-vs-suspend at a-edp1.html * {igt at kms_flip@plain-flip-ts-check-interruptible at b-hdmi-a1}: - shard-glk: [FAIL][31] ([i915#1928]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-glk8/igt at kms_flip@plain-flip-ts-check-interruptible at b-hdmi-a1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-glk5/igt at kms_flip@plain-flip-ts-check-interruptible at b-hdmi-a1.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_cursor@pipe-b-primary-size-256: - shard-hsw: [DMESG-WARN][35] ([i915#1927]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-hsw2/igt at kms_plane_cursor@pipe-b-primary-size-256.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-hsw4/igt at kms_plane_cursor@pipe-b-primary-size-256.html * igt at kms_prop_blob@blob-prop-lifetime: - shard-apl: [TIMEOUT][37] ([i915#1635]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at kms_prop_blob@blob-prop-lifetime.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl2/igt at kms_prop_blob@blob-prop-lifetime.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb4/igt at kms_psr@psr2_suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-iclb2/igt at kms_psr@psr2_suspend.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][41] ([i915#1542]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-iclb3/igt at perf@blocking-parameterized.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-iclb3/igt at perf@blocking-parameterized.html * {igt at perf_pmu@faulting-read at uc}: - shard-apl: [DMESG-WARN][43] -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at perf_pmu@faulting-read at uc.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl2/igt at perf_pmu@faulting-read at uc.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][45] ([i915#468]) -> [FAIL][46] ([i915#454]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-tglb8/igt at i915_pm_dc@dc6-psr.html * igt at kms_color_chamelium@pipe-a-degamma: - shard-apl: [TIMEOUT][47] ([i915#1635]) -> [SKIP][48] ([fdo#109271] / [fdo#111827]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at kms_color_chamelium@pipe-a-degamma.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl2/igt at kms_color_chamelium@pipe-a-degamma.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at kms_content_protection@atomic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][51] ([i915#1319]) -> [FAIL][52] ([fdo#110321] / [fdo#110336]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at kms_content_protection@legacy.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff: - shard-apl: [TIMEOUT][53] ([i915#1635]) -> [SKIP][54] ([fdo#109271]) +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl6/igt at kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl2/igt at kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [FAIL][55] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][56] ([fdo#108145] / [i915#265]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8565/shard-apl2/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/shard-apl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8565 -> Patchwork_17832 CI-20190529: 20190529 CI_DRM_8565: 267bdbf5f8ba7c0931eb6c11a3b9eb893b10fead @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17832: b61fdbb8c3873e10973bd087a9811566cbb289e9 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17832/index.html From patchwork at emeril.freedesktop.org Mon Jun 1 22:28:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 01 Jun 2020 22:28:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BCI=2C1/3=5D_drm/i915/params=3A_don=27t_exp?= =?utf-8?q?ose_inject=5Fprobe=5Ffailure_in_debugfs?= In-Reply-To: <20200601215510.18379-1-jani.nikula@intel.com> References: <20200601215510.18379-1-jani.nikula@intel.com> Message-ID: <159105050107.14888.13389686433442047181@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/params: don't expose inject_probe_failure in debugfs URL : https://patchwork.freedesktop.org/series/77889/ State : success == Summary == CI Bug Log - changes from CI_DRM_8567 -> Patchwork_17836 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/index.html Known issues ------------ Here are the changes found in Patchwork_17836 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_selftest@live at active: - fi-icl-y: [PASS][1] -> [DMESG-FAIL][2] ([i915#765]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/fi-icl-y/igt at i915_selftest@live at active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/fi-icl-y/igt at i915_selftest@live at active.html [i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765 Participating hosts (49 -> 44) ------------------------------ Additional (2): fi-skl-lmem fi-cfl-8109u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8567 -> Patchwork_17836 CI-20190529: 20190529 CI_DRM_8567: d36c7a9807541df70739a5917cbbab42fdf66a29 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17836: 28eb95e6e065e155a6b0a5c8fb4c4bab9a19c411 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 28eb95e6e065 drm/i915/params: prevent changing module params runtime 5cc66b985a6b drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions acf490748fe6 drm/i915/params: don't expose inject_probe_failure in debugfs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/index.html From chris at chris-wilson.co.uk Tue Jun 2 00:26:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 01:26:50 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200602002650.1355736-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 418 +++++++++++++++++++++++++++++++++ 1 file changed, 418 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..d1121ecd2 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,417 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + if (offset_in_page(cs) & 4) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + int timeline, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_PACING 0x1 +#define F_EXTERNAL 0x2 +{ + const int batches_per_frame = 3; + struct drm_i915_gem_exec_object2 prev = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 ts = tslog_create(i915, ctx, e); + struct timespec tv = {}; + unsigned long count = 0; + int p_fence = -1, n_fence = -1; + uint32_t *map; + int n; + + igt_nsec_elapsed(&tv); + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_EXTERNAL) { + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, count); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + execbuf.buffers_ptr = to_user_pointer(&ts); + execbuf.batch_start_offset = 2048; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACING && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + close(execbuf.rsvd2); + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + gem_sync(i915, prev.handle); + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); + + map = gem_mmap__device_coherent(i915, ts.handle, 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) + map[n - 1] = map[n] - map[n - 1]; + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + + gem_close(i915, ts.handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + int timeline = sw_sync_timeline_create(); + int nframes = timeout * NSEC_PER_SEC / frame_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct igt_mean m; + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + fair_child(i915, ctx, e, frame_ns / nchild, + timeout, timeline, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nframes--) { + struct timespec tv = { .tv_nsec = frame_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) { + struct timespec tv = { .tv_nsec = frame_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + } + igt_waitchildren(); + close(timeline); + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + +#if 0 + /* Mean within 10% of target */ + igt_assert( 9 * igt_mean_get(&m) > 10 * frame_ns && + 10 * igt_mean_get(&m) < 9 * frame_ns); + + /* Variance [inter-quartile range] is less than 33% of median */ + igt_assert(3 * result[hi] - result[lo] < result[nchild / 2]); +#endif + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +3000,13 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACING); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_PACING | F_EXTERNAL); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From patchwork at emeril.freedesktop.org Tue Jun 2 01:36:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 01:36:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_wrong_CDCLK_adjustment_changes_=28rev2=29?= In-Reply-To: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> References: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> Message-ID: <159106177914.21429.9269364037735341204@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix wrong CDCLK adjustment changes (rev2) URL : https://patchwork.freedesktop.org/series/77654/ State : success == Summary == CI Bug Log - changes from CI_DRM_8566_full -> Patchwork_17834_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17834_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at perf_pmu@faulting-read at uc}: - shard-apl: NOTRUN -> [DMESG-WARN][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl4/igt at perf_pmu@faulting-read at uc.html Known issues ------------ Here are the changes found in Patchwork_17834_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at rcs0: - shard-apl: [PASS][2] -> [FAIL][3] ([i915#1528]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl8/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl8/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl4/igt at i915_suspend@fence-restore-tiled2untiled.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl2/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][6] -> [FAIL][7] ([i915#1119] / [i915#118] / [i915#95]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_legacy@pipe-b-torture-bo: - shard-tglb: [PASS][8] -> [DMESG-WARN][9] ([i915#128]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-tglb1/igt at kms_cursor_legacy@pipe-b-torture-bo.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-tglb5/igt at kms_cursor_legacy@pipe-b-torture-bo.html * igt at kms_draw_crc@fill-fb: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#95]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl4/igt at kms_draw_crc@fill-fb.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl2/igt at kms_draw_crc@fill-fb.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#1188]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html - shard-kbl: [PASS][14] -> [FAIL][15] ([i915#1188]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-kbl3/igt at kms_hdr@bpc-switch-dpms.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-kbl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#109642] / [fdo#111068]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb5/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_primary_render: - shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109441]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb2/igt at kms_psr@psr2_primary_render.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb3/igt at kms_psr@psr2_primary_render.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-kbl3/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-kbl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html #### Possible fixes #### * igt at gem_exec_reloc@basic-gtt-wc: - shard-hsw: [DMESG-WARN][22] ([i915#1927]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-hsw1/igt at gem_exec_reloc@basic-gtt-wc.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-hsw2/igt at gem_exec_reloc@basic-gtt-wc.html * igt at kms_color@pipe-a-gamma: - shard-hsw: [INCOMPLETE][24] ([i915#1927] / [i915#61]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-hsw1/igt at kms_color@pipe-a-gamma.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-hsw4/igt at kms_color@pipe-a-gamma.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: [DMESG-WARN][26] ([i915#180]) -> [PASS][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-kbl6/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][28] ([i915#1925] / [i915#1926]) -> [PASS][29] +1 similar issue [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-glk6/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][30] ([i915#1188]) -> [PASS][31] +1 similar issue [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-skl7/igt at kms_hdr@bpc-switch-suspend.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][32] ([fdo#108145] / [i915#265]) -> [PASS][33] +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][34] ([fdo#109441]) -> [PASS][35] +5 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb4/igt at kms_psr@psr2_cursor_render.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [DMESG-WARN][36] ([i915#180]) -> [PASS][37] +3 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl8/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-hsw: [FAIL][38] ([i915#1542]) -> [PASS][39] [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-hsw8/igt at perf@blocking-parameterized.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-hsw1/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][40] ([i915#658]) -> [SKIP][41] ([i915#588]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-iclb3/igt at i915_pm_dc@dc3co-vpb-simulation.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][42] ([i915#454]) -> [SKIP][43] ([i915#468]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-tglb1/igt at i915_pm_dc@dc6-psr.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][44] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][45] ([i915#1319]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl7/igt at kms_content_protection@atomic.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl1/igt at kms_content_protection@atomic.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-apl: [FAIL][46] ([fdo#108145] / [i915#265] / [i915#95]) -> [FAIL][47] ([fdo#108145] / [i915#265]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8566/shard-apl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/shard-apl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8566 -> Patchwork_17834 CI-20190529: 20190529 CI_DRM_8566: fed6b89dd6f3c4e2e909805815c5728b1fd65ce5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5689: 587cbed206689abbad60689d4a32bf9caf0cc124 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17834: 6bfe3f7a62bd1c9345f4789886a8030a10e81d32 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17834/index.html From aditya.swarup at intel.com Tue Jun 2 01:49:10 2020 From: aditya.swarup at intel.com (Aditya Swarup) Date: Mon, 1 Jun 2020 18:49:10 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1409371443 Message-ID: <20200602014910.13019-1-aditya.swarup@intel.com> Set GMBUS0 Pin Pair Select to 1 at boot and each FLR exit. Return GMBUS0 Pin Pair Select to 1 after GMBUS transactions are done. Cc: Michal Wajdeczko Cc: Piotr Pi?rkowski Cc: Matt Roper Cc: Jose Souza Signed-off-by: Aditya Swarup --- drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index a8d119b6b45c..8dd5aa025c3f 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -139,11 +139,19 @@ to_intel_gmbus(struct i2c_adapter *i2c) return container_of(i2c, struct intel_gmbus, adapter); } +static void gmbus0_wa_reset(struct drm_i915_private *dev_priv) +{ + intel_de_write(dev_priv, GMBUS0, 0 | GMBUS_PIN_PAIR_1); +} + void intel_gmbus_reset(struct drm_i915_private *dev_priv) { intel_de_write(dev_priv, GMBUS0, 0); intel_de_write(dev_priv, GMBUS4, 0); + /* Wa_1409371443: tgl[a0] */ + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) + gmbus0_wa_reset(dev_priv); } static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -299,6 +307,10 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter) if (IS_PINEVIEW(dev_priv)) pnv_gmbus_clock_gating(dev_priv, true); + + /* Wa_1409371443: tgl[a0] */ + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) + gmbus0_wa_reset(dev_priv); } static void @@ -955,4 +967,8 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv) bus = &dev_priv->gmbus[pin]; i2c_del_adapter(&bus->adapter); } + + /* Wa_1409371443: tgl[a0] */ + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) + gmbus0_wa_reset(dev_priv); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 578cfe11cbb9..a1640476cefb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3337,6 +3337,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) +#define GMBUS_PIN_PAIR_MASK REG_GENMASK(4, 0) +#define GMBUS_PIN_PAIR_1 REG_FIELD_PREP(GMBUS_PIN_PAIR_MASK, 1) #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ #define GMBUS_SW_CLR_INT (1 << 31) -- 2.26.2 From patchwork at emeril.freedesktop.org Tue Jun 2 02:30:08 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 02:30:08 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Add_Wa=5F1409371443?= In-Reply-To: <20200602014910.13019-1-aditya.swarup@intel.com> References: <20200602014910.13019-1-aditya.swarup@intel.com> Message-ID: <159106500892.21428.15869397875443497866@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Add Wa_1409371443 URL : https://patchwork.freedesktop.org/series/77892/ State : success == Summary == CI Bug Log - changes from CI_DRM_8568 -> Patchwork_17837 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/index.html Changes ------- No changes found Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8568 -> Patchwork_17837 CI-20190529: 20190529 CI_DRM_8568: 124bafc80c3ce62fc61b8eabb2657c87424b999b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17837: fe426e69f68a924170739c2e34f71a3771b37c0f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fe426e69f68a drm/i915/tgl: Add Wa_1409371443 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 03:19:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 03:19:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/dsi=3A_Dont_forget_to_clean_up_the_connector_on_error_=28?= =?utf-8?q?rev3=29?= In-Reply-To: <20200507010103.16040-1-vivek.kasireddy@intel.com> References: <20200507010103.16040-1-vivek.kasireddy@intel.com> Message-ID: <159106798384.21429.6251554645272340176@emeril.freedesktop.org> == Series Details == Series: drm/i915/dsi: Dont forget to clean up the connector on error (rev3) URL : https://patchwork.freedesktop.org/series/77011/ State : success == Summary == CI Bug Log - changes from CI_DRM_8568 -> Patchwork_17838 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/index.html Known issues ------------ Here are the changes found in Patchwork_17838 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_selftest@live at hangcheck: - fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2] ([i915#1250] / [i915#1436] / [i915#1506]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/fi-bsw-nick/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/fi-bsw-nick/igt at i915_selftest@live at hangcheck.html [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1506]: https://gitlab.freedesktop.org/drm/intel/issues/1506 Participating hosts (51 -> 45) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8568 -> Patchwork_17838 CI-20190529: 20190529 CI_DRM_8568: 124bafc80c3ce62fc61b8eabb2657c87424b999b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17838: a30b3a0e479eb9f2f48cf8a737656c9bbb64c15a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a30b3a0e479e drm/i915/dsi: Dont forget to clean up the connector on error (v2) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 04:48:03 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 04:48:03 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/i915=3A_Trim_set=5Ftimer=5Fms?= =?utf-8?q?=28=29_intervals?= In-Reply-To: <20200601203550.19192-1-chris@chris-wilson.co.uk> References: <20200601203550.19192-1-chris@chris-wilson.co.uk> Message-ID: <159107328303.21428.16059723145367507626@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915: Trim set_timer_ms() intervals URL : https://patchwork.freedesktop.org/series/77888/ State : success == Summary == CI Bug Log - changes from CI_DRM_8567_full -> Patchwork_17835_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17835_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_schedule@wide at vcs0}: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl7/igt at gem_exec_schedule@wide at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-skl1/igt at gem_exec_schedule@wide at vcs0.html Known issues ------------ Here are the changes found in Patchwork_17835_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gen9_exec_parse@allowed-all: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl6/igt at gen9_exec_parse@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl4/igt at gen9_exec_parse@allowed-all.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180] / [i915#93] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-a-128x128-right-edge: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#118] / [i915#70] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-glk9/igt at kms_cursor_edge_walk@pipe-a-128x128-right-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-glk8/igt at kms_cursor_edge_walk@pipe-a-128x128-right-edge.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#1188]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl7/igt at kms_hdr@bpc-switch.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-skl6/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#165]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-iclb8/igt at kms_psr@psr2_primary_page_flip.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-kbl: [DMESG-WARN][21] ([i915#180]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [FAIL][23] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-glk6/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: [DMESG-WARN][25] ([i915#180]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-tglb: [INCOMPLETE][27] -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-tglb7/igt at kms_cursor_legacy@cursor-vs-flip-varying-size.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-tglb2/igt at kms_cursor_legacy@cursor-vs-flip-varying-size.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][29] ([fdo#109349]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb6/igt at kms_dp_dsc@basic-dsc-enable-edp.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_draw_crc@draw-method-xrgb8888-pwrite-untiled: - shard-kbl: [FAIL][31] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl7/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl3/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html * igt at kms_draw_crc@fill-fb: - shard-kbl: [FAIL][33] ([i915#52] / [i915#93] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl1/igt at kms_draw_crc@fill-fb.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl2/igt at kms_draw_crc@fill-fb.html * {igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1}: - shard-hsw: [INCOMPLETE][35] ([i915#61]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-hsw8/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][37] ([i915#180] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][39] ([i915#69]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][41] ([fdo#108145] / [i915#265]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb8/igt at kms_psr@psr2_cursor_render.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_setmode@basic: - shard-apl: [FAIL][45] ([i915#31]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl4/igt at kms_setmode@basic.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl7/igt at kms_setmode@basic.html - shard-kbl: [FAIL][47] ([i915#31]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl3/igt at kms_setmode@basic.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-kbl1/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-hsw: [FAIL][49] ([i915#1542]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-hsw6/igt at perf@blocking-parameterized.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-hsw2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][51] ([i915#588]) -> [SKIP][52] ([i915#658]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-iclb8/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][53] ([i915#1319] / [i915#1635]) -> [TIMEOUT][54] ([i915#1319]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl1/igt at kms_content_protection@atomic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][55] ([i915#1319]) -> [TIMEOUT][56] ([i915#1319] / [i915#1635]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl6/igt at kms_content_protection@legacy.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl8/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][57] ([i915#1319] / [i915#1635]) -> [FAIL][58] ([fdo#110321]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl8/igt at kms_content_protection@lic.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl4/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][59] ([fdo#110321]) -> [TIMEOUT][60] ([i915#1319] / [i915#1635]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl4/igt at kms_content_protection@srm.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl7/igt at kms_content_protection@srm.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-FAIL][61] ([i915#1925] / [i915#1926]) -> [DMESG-WARN][62] ([i915#1926] / [i915#1927]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-glk4/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-glk2/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][63] ([i915#1525] / [i915#95]) -> [FAIL][64] ([i915#1525]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl1/igt at kms_fbcon_fbt@fbc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-apl2/igt at kms_fbcon_fbt@fbc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [FAIL][65] ([i915#608]) -> [SKIP][66] ([fdo#109642] / [fdo#111068]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb2/igt at kms_psr2_su@page_flip.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/shard-iclb8/igt at kms_psr2_su@page_flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8567 -> Patchwork_17835 CI-20190529: 20190529 CI_DRM_8567: d36c7a9807541df70739a5917cbbab42fdf66a29 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17835: 183dd61a0a8d0940db360620100f6455738ceffe @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17835/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 06:57:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 06:57:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BCI=2C1/3=5D_drm/i915/params=3A_don=27t_exp?= =?utf-8?q?ose_inject=5Fprobe=5Ffailure_in_debugfs?= In-Reply-To: <20200601215510.18379-1-jani.nikula@intel.com> References: <20200601215510.18379-1-jani.nikula@intel.com> Message-ID: <159108103101.21429.17979833983652384512@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/params: don't expose inject_probe_failure in debugfs URL : https://patchwork.freedesktop.org/series/77889/ State : success == Summary == CI Bug Log - changes from CI_DRM_8567_full -> Patchwork_17836_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17836_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_suspend@forcewake: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl7/igt at i915_suspend@forcewake.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-kbl1/igt at i915_suspend@forcewake.html - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#636] / [i915#69]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl1/igt at i915_suspend@forcewake.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-skl2/igt at i915_suspend@forcewake.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl6/igt at i915_suspend@sysfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-apl4/igt at i915_suspend@sysfs-reader.html * igt at kms_color@pipe-b-degamma: - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([i915#1927] / [i915#61]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-hsw1/igt at kms_color@pipe-b-degamma.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-hsw1/igt at kms_color@pipe-b-degamma.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#49]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl4/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl7/igt at kms_hdr@bpc-switch.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-skl5/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-iclb1/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#69]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl4/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-skl7/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html #### Possible fixes #### * igt at kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-tglb: [INCOMPLETE][19] ([i915#750]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-tglb7/igt at kms_cursor_legacy@cursor-vs-flip-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-tglb6/igt at kms_cursor_legacy@cursor-vs-flip-varying-size.html * igt at kms_draw_crc@fill-fb: - shard-kbl: [FAIL][21] ([i915#52] / [i915#93] / [i915#95]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl1/igt at kms_draw_crc@fill-fb.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-kbl2/igt at kms_draw_crc@fill-fb.html * {igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1}: - shard-hsw: [INCOMPLETE][23] ([i915#61]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-hsw8/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-hsw6/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][25] ([i915#180] / [i915#95]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-apl7/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-kbl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-kbl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][29] ([i915#69]) -> [PASS][30] +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-skl10/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][31] ([fdo#108145] / [i915#265]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][33] ([fdo#109441]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb5/igt at kms_psr@psr2_suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_setmode@basic: - shard-glk: [FAIL][35] ([i915#31]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-glk2/igt at kms_setmode@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-glk7/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-hsw: [FAIL][37] ([i915#1542]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-hsw6/igt at perf@blocking-parameterized.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-hsw2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][39] ([i915#588]) -> [SKIP][40] ([i915#658]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-iclb4/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][41] ([i915#1319] / [i915#1635]) -> [FAIL][42] ([fdo#110321] / [fdo#110336]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl6/igt at kms_content_protection@atomic-dpms.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-apl2/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][43] ([i915#1319]) -> [TIMEOUT][44] ([i915#1319] / [i915#1635]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl6/igt at kms_content_protection@legacy.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-apl1/igt at kms_content_protection@legacy.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [DMESG-WARN][46] ([i915#180] / [i915#95]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-apl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][47] ([i915#1525] / [i915#95]) -> [FAIL][48] ([i915#1525]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-apl1/igt at kms_fbcon_fbt@fbc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-apl2/igt at kms_fbcon_fbt@fbc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [FAIL][49] ([i915#608]) -> [SKIP][50] ([fdo#109642] / [fdo#111068]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8567/shard-iclb2/igt at kms_psr2_su@page_flip.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/shard-iclb4/igt at kms_psr2_su@page_flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8567 -> Patchwork_17836 CI-20190529: 20190529 CI_DRM_8567: d36c7a9807541df70739a5917cbbab42fdf66a29 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17836: 28eb95e6e065e155a6b0a5c8fb4c4bab9a19c411 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17836/index.html From chris at chris-wilson.co.uk Tue Jun 2 08:22:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 09:22:45 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200602082245.1356782-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 436 +++++++++++++++++++++++++++++++++ 1 file changed, 436 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..3045eeb62 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,429 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + if (offset_in_page(cs) & 4) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + int timeline, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 prev = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 ts = tslog_create(i915, ctx, e); + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + uint32_t *map; + int n; + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & (F_FLOW | F_HALF)) { + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, count); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + execbuf.buffers_ptr = to_user_pointer(&ts); + execbuf.batch_start_offset = 2048; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + close(execbuf.rsvd2); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); + + gem_sync(i915, ts.handle); + map = gem_mmap__device_coherent(i915, ts.handle, 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + + gem_close(i915, ts.handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct igt_mean m; + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + fair_child(i915, ctx, e, frame_ns / nchild, + timeout, timeline, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + } + igt_waitchildren(); + close(timeline); + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + +#if 0 + /* Mean within 10% of target */ + igt_assert( 9 * igt_mean_get(&m) > 10 * frame_ns && + 10 * igt_mean_get(&m) < 9 * frame_ns); + + /* Variance [inter-quartile range] is less than 33% of median */ + igt_assert(3 * result[hi] - result[lo] < result[nchild / 2]); +#endif + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +3012,19 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACE); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_SYNC); + test_each_engine_store("fair-flow", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW); + test_each_engine_store("fair-half", fd, e) + fairness(fd, e, 2, F_PACE | F_HALF); + test_each_engine_store("fair-solo", fd, e) + fairness(fd, e, 2, F_SYNC | F_SOLO); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From chris at chris-wilson.co.uk Tue Jun 2 08:32:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 09:32:41 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness In-Reply-To: <20200602082245.1356782-1-chris@chris-wilson.co.uk> References: <20200602082245.1356782-1-chris@chris-wilson.co.uk> Message-ID: <20200602083241.1413087-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 440 +++++++++++++++++++++++++++++++++ 1 file changed, 440 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..911379cad 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,431 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + if (offset_in_page(cs) & 4) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + int timeline, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +#define F_SPARE (1 << 8) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 prev = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 ts = tslog_create(i915, ctx, e); + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + uint32_t *map; + int n; + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_FLOW) { + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, count); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + execbuf.buffers_ptr = to_user_pointer(&ts); + execbuf.batch_start_offset = 2048; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + close(execbuf.rsvd2); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); + + gem_sync(i915, ts.handle); + map = gem_mmap__device_coherent(i915, ts.handle, 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + + gem_close(i915, ts.handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE)); + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct igt_mean m; + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + fair_child(i915, ctx, e, child_ns, + timeout, timeline, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + } + igt_waitchildren(); + close(timeline); + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + +#if 0 + /* Mean within 10% of target */ + igt_assert( 9 * igt_mean_get(&m) > 10 * frame_ns && + 10 * igt_mean_get(&m) < 9 * frame_ns); + + /* Variance [inter-quartile range] is less than 33% of median */ + igt_assert(3 * result[hi] - result[lo] < result[nchild / 2]); +#endif + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +3014,21 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACE); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_SYNC); + test_each_engine_store("fair-solo", fd, e) + fairness(fd, e, 2, F_SYNC | F_SOLO); + test_each_engine_store("fair-flow", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW); + test_each_engine_store("fair-spare", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_SPARE); + test_each_engine_store("fair-half", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_HALF); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From chris at chris-wilson.co.uk Tue Jun 2 08:50:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 09:50:57 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness In-Reply-To: <20200602082245.1356782-1-chris@chris-wilson.co.uk> References: <20200602082245.1356782-1-chris@chris-wilson.co.uk> Message-ID: <20200602085057.1413253-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 442 +++++++++++++++++++++++++++++++++ 1 file changed, 442 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..ced9ee571 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,433 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + if (offset_in_page(cs) & 4) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + int timeline, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +#define F_SPARE (1 << 8) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 prev = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 ts = tslog_create(i915, ctx, e); + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + uint32_t *map; + int n; + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_FLOW) { + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, count); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + execbuf.buffers_ptr = to_user_pointer(&ts); + execbuf.batch_start_offset = 2048; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + close(execbuf.rsvd2); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); + + gem_sync(i915, ts.handle); + map = gem_mmap__device_coherent(i915, ts.handle, 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + + gem_close(i915, ts.handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + igt_require(e->class == I915_ENGINE_CLASS_RENDER || /* XXX excuse me? */ + intel_gen(intel_get_drm_devid(i915)) < 11); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE)); + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct igt_mean m; + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + fair_child(i915, ctx, e, child_ns, + timeout, timeline, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + } + igt_waitchildren(); + close(timeline); + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + +#if 0 + /* Mean within 10% of target */ + igt_assert( 9 * igt_mean_get(&m) > 10 * frame_ns && + 10 * igt_mean_get(&m) < 9 * frame_ns); + + /* Variance [inter-quartile range] is less than 33% of median */ + igt_assert(3 * result[hi] - result[lo] < result[nchild / 2]); +#endif + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +3016,21 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACE); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_SYNC); + test_each_engine_store("fair-solo", fd, e) + fairness(fd, e, 2, F_SYNC | F_SOLO); + test_each_engine_store("fair-flow", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW); + test_each_engine_store("fair-spare", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_SPARE); + test_each_engine_store("fair-half", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_HALF); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From mika.kuoppala at linux.intel.com Tue Jun 2 08:57:20 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 02 Jun 2020 11:57:20 +0300 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_balancer: Disable pre-parser for rewritten batches In-Reply-To: <159102684249.29407.7177954715956460299@build.alporthouse.com> References: <20200531191307.180023-1-chris@chris-wilson.co.uk> <87sgfesuko.fsf@gaia.fi.intel.com> <159102684249.29407.7177954715956460299@build.alporthouse.com> Message-ID: <87a71lj15b.fsf@gaia.fi.intel.com> Chris Wilson writes: > Quoting Mika Kuoppala (2020-06-01 15:56:55) >> Chris Wilson writes: >> >> > As we rewrite the batches on the fly to implement the non-preemptible >> > lock, we need to tell Tigerlake to read the batch afresh each time. >> > Amusingly, the disable is a part of an arb-check, so we have to be >> > careful not to include the arbitration point inside our unpreemptible >> > loop. >> > >> > Signed-off-by: Chris Wilson >> > --- >> > tests/i915/gem_exec_balancer.c | 13 +++++++++---- >> > 1 file changed, 9 insertions(+), 4 deletions(-) >> > >> > diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c >> > index 026f8347e..0e3b52900 100644 >> > --- a/tests/i915/gem_exec_balancer.c >> > +++ b/tests/i915/gem_exec_balancer.c >> > @@ -1350,6 +1350,11 @@ static void __bonded_dual(int i915, >> > *out = cycles; >> > } >> > >> > +static uint32_t preparser_disable(void) >> > +{ >> > + return 0x5 << 23 | 1 << 8 | 1; /* preparser masked disable */ >> >> there is MI_ARB_CHECK >> >> > +} >> > + >> > static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) >> > { >> > uint32_t handle = gem_create(i915, 4096); >> > @@ -1363,14 +1368,14 @@ static uint32_t sync_from(int i915, uint32_t addr, uint32_t target) >> > *cs++ = 0; >> > *cs++ = 0; >> > >> > - *cs++ = MI_NOOP; >> > + *cs++ = preparser_disable(); >> > *cs++ = MI_NOOP; >> > *cs++ = MI_NOOP; >> > *cs++ = MI_NOOP; >> > >> > /* wait for them to cancel us */ >> > *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; >> > - *cs++ = addr + 16; >> > + *cs++ = addr + 24; >> >> I must be totally confused about the layout as I can't get >> the +8. You take one nop out and put one arb check in >> and everything moves with 8? > > It's just skipping over the MI_ARB_CHECK, +4, aligned to the next qword > because some old habits die hard. Well that explains it, Reviewed-by: Mika Kuoppala > -Chris From mika.kuoppala at linux.intel.com Tue Jun 2 09:04:12 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 02 Jun 2020 12:04:12 +0300 Subject: [Intel-gfx] [PATCH 02/36] drm/i915/gt: Split low level gen2-7 CS emitters In-Reply-To: <20200601072446.19548-2-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-2-chris@chris-wilson.co.uk> Message-ID: <877dwpj0tv.fsf@gaia.fi.intel.com> Chris Wilson writes: > Pull the routines for writing CS packets out of intel_ring_submission > into their own files. These are low level operations for building CS > instructions, rather than the logic for filling the global ring buffer > with requests, and we will wnat to reuse them outside of this context. *want. Acked-by: Mika Kuoppala > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/Makefile | 2 + > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 340 +++++++ > drivers/gpu/drm/i915/gt/gen2_engine_cs.h | 38 + > drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 455 ++++++++++ > drivers/gpu/drm/i915/gt/gen6_engine_cs.h | 39 + > drivers/gpu/drm/i915/gt/intel_engine.h | 1 - > .../gpu/drm/i915/gt/intel_ring_submission.c | 832 +----------------- > 7 files changed, 901 insertions(+), 806 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/gen2_engine_cs.c > create mode 100644 drivers/gpu/drm/i915/gt/gen2_engine_cs.h > create mode 100644 drivers/gpu/drm/i915/gt/gen6_engine_cs.c > create mode 100644 drivers/gpu/drm/i915/gt/gen6_engine_cs.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index b0da6ea6e3f1..41a27fd5dbc7 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -78,6 +78,8 @@ gt-y += \ > gt/debugfs_engines.o \ > gt/debugfs_gt.o \ > gt/debugfs_gt_pm.o \ > + gt/gen2_engine_cs.o \ > + gt/gen6_engine_cs.o \ > gt/gen6_ppgtt.o \ > gt/gen7_renderclear.o \ > gt/gen8_ppgtt.o \ > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > new file mode 100644 > index 000000000000..8d2e85081247 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > @@ -0,0 +1,340 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright ? 2020 Intel Corporation > + */ > + > +#include "gen2_engine_cs.h" > +#include "i915_drv.h" > +#include "intel_engine.h" > +#include "intel_gpu_commands.h" > +#include "intel_gt.h" > +#include "intel_gt_irq.h" > +#include "intel_ring.h" > + > +int gen2_emit_flush(struct i915_request *rq, u32 mode) > +{ > + unsigned int num_store_dw; > + u32 cmd, *cs; > + > + cmd = MI_FLUSH; > + num_store_dw = 0; > + if (mode & EMIT_INVALIDATE) > + cmd |= MI_READ_FLUSH; > + if (mode & EMIT_FLUSH) > + num_store_dw = 4; > + > + cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = cmd; > + while (num_store_dw--) { > + *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > + *cs++ = intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_DEFAULT); > + *cs++ = 0; > + } > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > + > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode) > +{ > + u32 cmd, *cs; > + int i; > + > + /* > + * read/write caches: > + * > + * I915_GEM_DOMAIN_RENDER is always invalidated, but is > + * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is > + * also flushed at 2d versus 3d pipeline switches. > + * > + * read-only caches: > + * > + * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if > + * MI_READ_FLUSH is set, and is always flushed on 965. > + * > + * I915_GEM_DOMAIN_COMMAND may not exist? > + * > + * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is > + * invalidated when MI_EXE_FLUSH is set. > + * > + * I915_GEM_DOMAIN_VERTEX, which exists on 965, is > + * invalidated with every MI_FLUSH. > + * > + * TLBs: > + * > + * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND > + * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and > + * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER > + * are flushed at any MI_FLUSH. > + */ > + > + cmd = MI_FLUSH; > + if (mode & EMIT_INVALIDATE) { > + cmd |= MI_EXE_FLUSH; > + if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) > + cmd |= MI_INVALIDATE_ISP; > + } > + > + i = 2; > + if (mode & EMIT_INVALIDATE) > + i += 20; > + > + cs = intel_ring_begin(rq, i); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = cmd; > + > + /* > + * A random delay to let the CS invalidate take effect? Without this > + * delay, the GPU relocation path fails as the CS does not see > + * the updated contents. Just as important, if we apply the flushes > + * to the EMIT_FLUSH branch (i.e. immediately after the relocation > + * write and before the invalidate on the next batch), the relocations > + * still fail. This implies that is a delay following invalidation > + * that is required to reset the caches as opposed to a delay to > + * ensure the memory is written. > + */ > + if (mode & EMIT_INVALIDATE) { > + *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; > + *cs++ = intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_DEFAULT) | > + PIPE_CONTROL_GLOBAL_GTT; > + *cs++ = 0; > + *cs++ = 0; > + > + for (i = 0; i < 12; i++) > + *cs++ = MI_FLUSH; > + > + *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; > + *cs++ = intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_DEFAULT) | > + PIPE_CONTROL_GLOBAL_GTT; > + *cs++ = 0; > + *cs++ = 0; > + } > + > + *cs++ = cmd; > + > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) > +{ > + u32 *cs; > + > + cs = intel_ring_begin(rq, 2); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = MI_FLUSH; > + *cs++ = MI_NOOP; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +{ > + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > + > + *cs++ = MI_FLUSH; > + > + *cs++ = MI_STORE_DWORD_INDEX; > + *cs++ = I915_GEM_HWS_SEQNO_ADDR; > + *cs++ = rq->fence.seqno; > + > + *cs++ = MI_USER_INTERRUPT; > + *cs++ = MI_NOOP; > + > + rq->tail = intel_ring_offset(rq, cs); > + assert_ring_tail_valid(rq->ring, rq->tail); > + > + return cs; > +} > + > +#define GEN5_WA_STORES 8 /* must be at least 1! */ > +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +{ > + int i; > + > + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > + > + *cs++ = MI_FLUSH; > + > + BUILD_BUG_ON(GEN5_WA_STORES < 1); > + for (i = 0; i < GEN5_WA_STORES; i++) { > + *cs++ = MI_STORE_DWORD_INDEX; > + *cs++ = I915_GEM_HWS_SEQNO_ADDR; > + *cs++ = rq->fence.seqno; > + } > + > + *cs++ = MI_USER_INTERRUPT; > + > + rq->tail = intel_ring_offset(rq, cs); > + assert_ring_tail_valid(rq->ring, rq->tail); > + > + return cs; > +} > +#undef GEN5_WA_STORES > + > +/* Just userspace ABI convention to limit the wa batch bo to a resonable size */ > +#define I830_BATCH_LIMIT SZ_256K > +#define I830_TLB_ENTRIES (2) > +#define I830_WA_SIZE max(I830_TLB_ENTRIES * SZ_4K, I830_BATCH_LIMIT) > +int i830_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags) > +{ > + u32 *cs, cs_offset = > + intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_DEFAULT); > + > + GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE); > + > + cs = intel_ring_begin(rq, 6); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + /* Evict the invalid PTE TLBs */ > + *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; > + *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; > + *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ > + *cs++ = cs_offset; > + *cs++ = 0xdeadbeef; > + *cs++ = MI_NOOP; > + intel_ring_advance(rq, cs); > + > + if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { > + if (len > I830_BATCH_LIMIT) > + return -ENOSPC; > + > + cs = intel_ring_begin(rq, 6 + 2); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + /* > + * Blit the batch (which has now all relocs applied) to the > + * stable batch scratch bo area (so that the CS never > + * stumbles over its tlb invalidation bug) ... > + */ > + *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2); > + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; > + *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; > + *cs++ = cs_offset; > + *cs++ = 4096; > + *cs++ = offset; > + > + *cs++ = MI_FLUSH; > + *cs++ = MI_NOOP; > + intel_ring_advance(rq, cs); > + > + /* ... and execute it. */ > + offset = cs_offset; > + } > + > + if (!(dispatch_flags & I915_DISPATCH_SECURE)) > + offset |= MI_BATCH_NON_SECURE; > + > + cs = intel_ring_begin(rq, 2); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; > + *cs++ = offset; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +int gen3_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags) > +{ > + u32 *cs; > + > + if (!(dispatch_flags & I915_DISPATCH_SECURE)) > + offset |= MI_BATCH_NON_SECURE; > + > + cs = intel_ring_begin(rq, 2); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; > + *cs++ = offset; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +int gen4_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 length, > + unsigned int dispatch_flags) > +{ > + u32 security; > + u32 *cs; > + > + security = MI_BATCH_NON_SECURE_I965; > + if (dispatch_flags & I915_DISPATCH_SECURE) > + security = 0; > + > + cs = intel_ring_begin(rq, 2); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | security; > + *cs++ = offset; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +void gen2_irq_enable(struct intel_engine_cs *engine) > +{ > + struct drm_i915_private *i915 = engine->i915; > + > + i915->irq_mask &= ~engine->irq_enable_mask; > + intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); > + ENGINE_POSTING_READ16(engine, RING_IMR); > +} > + > +void gen2_irq_disable(struct intel_engine_cs *engine) > +{ > + struct drm_i915_private *i915 = engine->i915; > + > + i915->irq_mask |= engine->irq_enable_mask; > + intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); > +} > + > +void gen3_irq_enable(struct intel_engine_cs *engine) > +{ > + engine->i915->irq_mask &= ~engine->irq_enable_mask; > + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > + intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); > +} > + > +void gen3_irq_disable(struct intel_engine_cs *engine) > +{ > + engine->i915->irq_mask |= engine->irq_enable_mask; > + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > +} > + > +void gen5_irq_enable(struct intel_engine_cs *engine) > +{ > + gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); > +} > + > +void gen5_irq_disable(struct intel_engine_cs *engine) > +{ > + gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); > +} > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > new file mode 100644 > index 000000000000..a5cd64a65c9e > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > @@ -0,0 +1,38 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright ? 2020 Intel Corporation > + */ > + > +#ifndef __GEN2_ENGINE_CS_H__ > +#define __GEN2_ENGINE_CS_H__ > + > +#include > + > +struct i915_request; > +struct intel_engine_cs; > + > +int gen2_emit_flush(struct i915_request *rq, u32 mode); > +int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode); > +int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode); > + > +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs); > +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs); > + > +int i830_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags); > +int gen3_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags); > +int gen4_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 length, > + unsigned int dispatch_flags); > + > +void gen2_irq_enable(struct intel_engine_cs *engine); > +void gen2_irq_disable(struct intel_engine_cs *engine); > +void gen3_irq_enable(struct intel_engine_cs *engine); > +void gen3_irq_disable(struct intel_engine_cs *engine); > +void gen5_irq_enable(struct intel_engine_cs *engine); > +void gen5_irq_disable(struct intel_engine_cs *engine); > + > +#endif /* __GEN2_ENGINE_CS_H__ */ > diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c > new file mode 100644 > index 000000000000..ce38d1bcaba3 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c > @@ -0,0 +1,455 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright ? 2020 Intel Corporation > + */ > + > +#include "gen6_engine_cs.h" > +#include "intel_engine.h" > +#include "intel_gpu_commands.h" > +#include "intel_gt.h" > +#include "intel_gt_irq.h" > +#include "intel_gt_pm_irq.h" > +#include "intel_ring.h" > + > +#define HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) > + > +/* > + * Emits a PIPE_CONTROL with a non-zero post-sync operation, for > + * implementing two workarounds on gen6. From section 1.4.7.1 > + * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: > + * > + * [DevSNB-C+{W/A}] Before any depth stall flush (including those > + * produced by non-pipelined state commands), software needs to first > + * send a PIPE_CONTROL with no bits set except Post-Sync Operation != > + * 0. > + * > + * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable > + * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. > + * > + * And the workaround for these two requires this workaround first: > + * > + * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent > + * BEFORE the pipe-control with a post-sync op and no write-cache > + * flushes. > + * > + * And this last workaround is tricky because of the requirements on > + * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM > + * volume 2 part 1: > + * > + * "1 of the following must also be set: > + * - Render Target Cache Flush Enable ([12] of DW1) > + * - Depth Cache Flush Enable ([0] of DW1) > + * - Stall at Pixel Scoreboard ([1] of DW1) > + * - Depth Stall ([13] of DW1) > + * - Post-Sync Operation ([13] of DW1) > + * - Notify Enable ([8] of DW1)" > + * > + * The cache flushes require the workaround flush that triggered this > + * one, so we can't use it. Depth stall would trigger the same. > + * Post-sync nonzero is what triggered this second workaround, so we > + * can't use that one either. Notify enable is IRQs, which aren't > + * really our business. That leaves only stall at scoreboard. > + */ > +static int > +gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) > +{ > + u32 scratch_addr = > + intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); > + u32 *cs; > + > + cs = intel_ring_begin(rq, 6); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = GFX_OP_PIPE_CONTROL(5); > + *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; > + *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; > + *cs++ = 0; /* low dword */ > + *cs++ = 0; /* high dword */ > + *cs++ = MI_NOOP; > + intel_ring_advance(rq, cs); > + > + cs = intel_ring_begin(rq, 6); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = GFX_OP_PIPE_CONTROL(5); > + *cs++ = PIPE_CONTROL_QW_WRITE; > + *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; > + *cs++ = 0; > + *cs++ = 0; > + *cs++ = MI_NOOP; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode) > +{ > + u32 scratch_addr = > + intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); > + u32 *cs, flags = 0; > + int ret; > + > + /* Force SNB workarounds for PIPE_CONTROL flushes */ > + ret = gen6_emit_post_sync_nonzero_flush(rq); > + if (ret) > + return ret; > + > + /* > + * Just flush everything. Experiments have shown that reducing the > + * number of bits based on the write domains has little performance > + * impact. And when rearranging requests, the order of flushes is > + * unknown. > + */ > + if (mode & EMIT_FLUSH) { > + flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > + flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > + /* > + * Ensure that any following seqno writes only happen > + * when the render cache is indeed flushed. > + */ > + flags |= PIPE_CONTROL_CS_STALL; > + } > + if (mode & EMIT_INVALIDATE) { > + flags |= PIPE_CONTROL_TLB_INVALIDATE; > + flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; > + /* > + * TLB invalidate requires a post-sync write. > + */ > + flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; > + } > + > + cs = intel_ring_begin(rq, 4); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = GFX_OP_PIPE_CONTROL(4); > + *cs++ = flags; > + *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; > + *cs++ = 0; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) > +{ > + /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ > + *cs++ = GFX_OP_PIPE_CONTROL(4); > + *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; > + *cs++ = 0; > + *cs++ = 0; > + > + *cs++ = GFX_OP_PIPE_CONTROL(4); > + *cs++ = PIPE_CONTROL_QW_WRITE; > + *cs++ = intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_DEFAULT) | > + PIPE_CONTROL_GLOBAL_GTT; > + *cs++ = 0; > + > + /* Finally we can flush and with it emit the breadcrumb */ > + *cs++ = GFX_OP_PIPE_CONTROL(4); > + *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > + PIPE_CONTROL_DEPTH_CACHE_FLUSH | > + PIPE_CONTROL_DC_FLUSH_ENABLE | > + PIPE_CONTROL_QW_WRITE | > + PIPE_CONTROL_CS_STALL); > + *cs++ = i915_request_active_timeline(rq)->hwsp_offset | > + PIPE_CONTROL_GLOBAL_GTT; > + *cs++ = rq->fence.seqno; > + > + *cs++ = MI_USER_INTERRUPT; > + *cs++ = MI_NOOP; > + > + rq->tail = intel_ring_offset(rq, cs); > + assert_ring_tail_valid(rq->ring, rq->tail); > + > + return cs; > +} > + > +static int mi_flush_dw(struct i915_request *rq, u32 flags) > +{ > + u32 cmd, *cs; > + > + cs = intel_ring_begin(rq, 4); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + cmd = MI_FLUSH_DW; > + > + /* > + * We always require a command barrier so that subsequent > + * commands, such as breadcrumb interrupts, are strictly ordered > + * wrt the contents of the write cache being flushed to memory > + * (and thus being coherent from the CPU). > + */ > + cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; > + > + /* > + * Bspec vol 1c.3 - blitter engine command streamer: > + * "If ENABLED, all TLBs will be invalidated once the flush > + * operation is complete. This bit is only valid when the > + * Post-Sync Operation field is a value of 1h or 3h." > + */ > + cmd |= flags; > + > + *cs++ = cmd; > + *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; > + *cs++ = 0; > + *cs++ = MI_NOOP; > + > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) > +{ > + return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); > +} > + > +int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode) > +{ > + return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); > +} > + > +int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode) > +{ > + return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); > +} > + > +int gen6_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags) > +{ > + u32 security; > + u32 *cs; > + > + security = MI_BATCH_NON_SECURE_I965; > + if (dispatch_flags & I915_DISPATCH_SECURE) > + security = 0; > + > + cs = intel_ring_begin(rq, 2); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + cs = __gen6_emit_bb_start(cs, offset, security); > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +int > +hsw_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags) > +{ > + u32 security; > + u32 *cs; > + > + security = MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW; > + if (dispatch_flags & I915_DISPATCH_SECURE) > + security = 0; > + > + cs = intel_ring_begin(rq, 2); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + cs = __gen6_emit_bb_start(cs, offset, security); > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +static int gen7_stall_cs(struct i915_request *rq) > +{ > + u32 *cs; > + > + cs = intel_ring_begin(rq, 4); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = GFX_OP_PIPE_CONTROL(4); > + *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; > + *cs++ = 0; > + *cs++ = 0; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode) > +{ > + u32 scratch_addr = > + intel_gt_scratch_offset(rq->engine->gt, > + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); > + u32 *cs, flags = 0; > + > + /* > + * Ensure that any following seqno writes only happen when the render > + * cache is indeed flushed. > + * > + * Workaround: 4th PIPE_CONTROL command (except the ones with only > + * read-cache invalidate bits set) must have the CS_STALL bit set. We > + * don't try to be clever and just set it unconditionally. > + */ > + flags |= PIPE_CONTROL_CS_STALL; > + > + /* > + * CS_STALL suggests at least a post-sync write. > + */ > + flags |= PIPE_CONTROL_QW_WRITE; > + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; > + > + /* > + * Just flush everything. Experiments have shown that reducing the > + * number of bits based on the write domains has little performance > + * impact. > + */ > + if (mode & EMIT_FLUSH) { > + flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > + flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > + flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; > + flags |= PIPE_CONTROL_FLUSH_ENABLE; > + } > + if (mode & EMIT_INVALIDATE) { > + flags |= PIPE_CONTROL_TLB_INVALIDATE; > + flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; > + > + /* > + * Workaround: we must issue a pipe_control with CS-stall bit > + * set before a pipe_control command that has the state cache > + * invalidate bit set. > + */ > + gen7_stall_cs(rq); > + } > + > + cs = intel_ring_begin(rq, 4); > + if (IS_ERR(cs)) > + return PTR_ERR(cs); > + > + *cs++ = GFX_OP_PIPE_CONTROL(4); > + *cs++ = flags; > + *cs++ = scratch_addr; > + *cs++ = 0; > + intel_ring_advance(rq, cs); > + > + return 0; > +} > + > +u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) > +{ > + *cs++ = GFX_OP_PIPE_CONTROL(4); > + *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > + PIPE_CONTROL_DEPTH_CACHE_FLUSH | > + PIPE_CONTROL_DC_FLUSH_ENABLE | > + PIPE_CONTROL_FLUSH_ENABLE | > + PIPE_CONTROL_QW_WRITE | > + PIPE_CONTROL_GLOBAL_GTT_IVB | > + PIPE_CONTROL_CS_STALL); > + *cs++ = i915_request_active_timeline(rq)->hwsp_offset; > + *cs++ = rq->fence.seqno; > + > + *cs++ = MI_USER_INTERRUPT; > + *cs++ = MI_NOOP; > + > + rq->tail = intel_ring_offset(rq, cs); > + assert_ring_tail_valid(rq->ring, rq->tail); > + > + return cs; > +} > + > +u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) > +{ > + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > + > + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; > + *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; > + *cs++ = rq->fence.seqno; > + > + *cs++ = MI_USER_INTERRUPT; > + > + rq->tail = intel_ring_offset(rq, cs); > + assert_ring_tail_valid(rq->ring, rq->tail); > + > + return cs; > +} > + > +#define GEN7_XCS_WA 32 > +u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) > +{ > + int i; > + > + GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > + GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > + > + *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | > + MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; > + *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; > + *cs++ = rq->fence.seqno; > + > + for (i = 0; i < GEN7_XCS_WA; i++) { > + *cs++ = MI_STORE_DWORD_INDEX; > + *cs++ = I915_GEM_HWS_SEQNO_ADDR; > + *cs++ = rq->fence.seqno; > + } > + > + *cs++ = MI_FLUSH_DW; > + *cs++ = 0; > + *cs++ = 0; > + > + *cs++ = MI_USER_INTERRUPT; > + *cs++ = MI_NOOP; > + > + rq->tail = intel_ring_offset(rq, cs); > + assert_ring_tail_valid(rq->ring, rq->tail); > + > + return cs; > +} > +#undef GEN7_XCS_WA > + > +void gen6_irq_enable(struct intel_engine_cs *engine) > +{ > + ENGINE_WRITE(engine, RING_IMR, > + ~(engine->irq_enable_mask | engine->irq_keep_mask)); > + > + /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ > + ENGINE_POSTING_READ(engine, RING_IMR); > + > + gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); > +} > + > +void gen6_irq_disable(struct intel_engine_cs *engine) > +{ > + ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); > + gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); > +} > + > +void hsw_irq_enable_vecs(struct intel_engine_cs *engine) > +{ > + ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); > + > + /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ > + ENGINE_POSTING_READ(engine, RING_IMR); > + > + gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); > +} > + > +void hsw_irq_disable_vecs(struct intel_engine_cs *engine) > +{ > + ENGINE_WRITE(engine, RING_IMR, ~0); > + gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); > +} > diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.h b/drivers/gpu/drm/i915/gt/gen6_engine_cs.h > new file mode 100644 > index 000000000000..76c6bc9f3bde > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.h > @@ -0,0 +1,39 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright ? 2020 Intel Corporation > + */ > + > +#ifndef __GEN6_ENGINE_CS_H__ > +#define __GEN6_ENGINE_CS_H__ > + > +#include > + > +#include "intel_gpu_commands.h" > + > +struct i915_request; > +struct intel_engine_cs; > + > +int gen6_emit_flush_rcs(struct i915_request *rq, u32 mode); > +int gen6_emit_flush_vcs(struct i915_request *rq, u32 mode); > +int gen6_emit_flush_xcs(struct i915_request *rq, u32 mode); > +u32 *gen6_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); > +u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); > + > +int gen7_emit_flush_rcs(struct i915_request *rq, u32 mode); > +u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs); > +u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs); > + > +int gen6_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags); > +int hsw_emit_bb_start(struct i915_request *rq, > + u64 offset, u32 len, > + unsigned int dispatch_flags); > + > +void gen6_irq_enable(struct intel_engine_cs *engine); > +void gen6_irq_disable(struct intel_engine_cs *engine); > + > +void hsw_irq_enable_vecs(struct intel_engine_cs *engine); > +void hsw_irq_disable_vecs(struct intel_engine_cs *engine); > + > +#endif /* __GEN6_ENGINE_CS_H__ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 9bf6d4989968..791897f8d847 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -187,7 +187,6 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) > #define I915_GEM_HWS_SEQNO 0x40 > #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32)) > #define I915_GEM_HWS_SCRATCH 0x80 > -#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) > > #define I915_HWS_CSB_BUF0_INDEX 0x10 > #define I915_HWS_CSB_WRITE_INDEX 0x1f > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index ca7286e58409..96881cd8b17b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -27,21 +27,15 @@ > * > */ > > -#include > - > -#include "gem/i915_gem_context.h" > - > +#include "gen2_engine_cs.h" > +#include "gen6_engine_cs.h" > #include "gen6_ppgtt.h" > #include "gen7_renderclear.h" > #include "i915_drv.h" > -#include "i915_trace.h" > #include "intel_context.h" > #include "intel_gt.h" > -#include "intel_gt_irq.h" > -#include "intel_gt_pm_irq.h" > #include "intel_reset.h" > #include "intel_ring.h" > -#include "intel_workarounds.h" > #include "shmem_utils.h" > > /* Rough estimate of the typical request size, performing a flush, > @@ -49,436 +43,6 @@ > */ > #define LEGACY_REQUEST_SIZE 200 > > -static int > -gen2_render_ring_flush(struct i915_request *rq, u32 mode) > -{ > - unsigned int num_store_dw; > - u32 cmd, *cs; > - > - cmd = MI_FLUSH; > - num_store_dw = 0; > - if (mode & EMIT_INVALIDATE) > - cmd |= MI_READ_FLUSH; > - if (mode & EMIT_FLUSH) > - num_store_dw = 4; > - > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = cmd; > - while (num_store_dw--) { > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_DEFAULT); > - *cs++ = 0; > - } > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > - > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static int > -gen4_render_ring_flush(struct i915_request *rq, u32 mode) > -{ > - u32 cmd, *cs; > - int i; > - > - /* > - * read/write caches: > - * > - * I915_GEM_DOMAIN_RENDER is always invalidated, but is > - * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is > - * also flushed at 2d versus 3d pipeline switches. > - * > - * read-only caches: > - * > - * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if > - * MI_READ_FLUSH is set, and is always flushed on 965. > - * > - * I915_GEM_DOMAIN_COMMAND may not exist? > - * > - * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is > - * invalidated when MI_EXE_FLUSH is set. > - * > - * I915_GEM_DOMAIN_VERTEX, which exists on 965, is > - * invalidated with every MI_FLUSH. > - * > - * TLBs: > - * > - * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND > - * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and > - * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER > - * are flushed at any MI_FLUSH. > - */ > - > - cmd = MI_FLUSH; > - if (mode & EMIT_INVALIDATE) { > - cmd |= MI_EXE_FLUSH; > - if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) > - cmd |= MI_INVALIDATE_ISP; > - } > - > - i = 2; > - if (mode & EMIT_INVALIDATE) > - i += 20; > - > - cs = intel_ring_begin(rq, i); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = cmd; > - > - /* > - * A random delay to let the CS invalidate take effect? Without this > - * delay, the GPU relocation path fails as the CS does not see > - * the updated contents. Just as important, if we apply the flushes > - * to the EMIT_FLUSH branch (i.e. immediately after the relocation > - * write and before the invalidate on the next batch), the relocations > - * still fail. This implies that is a delay following invalidation > - * that is required to reset the caches as opposed to a delay to > - * ensure the memory is written. > - */ > - if (mode & EMIT_INVALIDATE) { > - *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_DEFAULT) | > - PIPE_CONTROL_GLOBAL_GTT; > - *cs++ = 0; > - *cs++ = 0; > - > - for (i = 0; i < 12; i++) > - *cs++ = MI_FLUSH; > - > - *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_DEFAULT) | > - PIPE_CONTROL_GLOBAL_GTT; > - *cs++ = 0; > - *cs++ = 0; > - } > - > - *cs++ = cmd; > - > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -/* > - * Emits a PIPE_CONTROL with a non-zero post-sync operation, for > - * implementing two workarounds on gen6. From section 1.4.7.1 > - * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: > - * > - * [DevSNB-C+{W/A}] Before any depth stall flush (including those > - * produced by non-pipelined state commands), software needs to first > - * send a PIPE_CONTROL with no bits set except Post-Sync Operation != > - * 0. > - * > - * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable > - * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. > - * > - * And the workaround for these two requires this workaround first: > - * > - * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent > - * BEFORE the pipe-control with a post-sync op and no write-cache > - * flushes. > - * > - * And this last workaround is tricky because of the requirements on > - * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM > - * volume 2 part 1: > - * > - * "1 of the following must also be set: > - * - Render Target Cache Flush Enable ([12] of DW1) > - * - Depth Cache Flush Enable ([0] of DW1) > - * - Stall at Pixel Scoreboard ([1] of DW1) > - * - Depth Stall ([13] of DW1) > - * - Post-Sync Operation ([13] of DW1) > - * - Notify Enable ([8] of DW1)" > - * > - * The cache flushes require the workaround flush that triggered this > - * one, so we can't use it. Depth stall would trigger the same. > - * Post-sync nonzero is what triggered this second workaround, so we > - * can't use that one either. Notify enable is IRQs, which aren't > - * really our business. That leaves only stall at scoreboard. > - */ > -static int > -gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) > -{ > - u32 scratch_addr = > - intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); > - u32 *cs; > - > - cs = intel_ring_begin(rq, 6); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = GFX_OP_PIPE_CONTROL(5); > - *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; > - *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; > - *cs++ = 0; /* low dword */ > - *cs++ = 0; /* high dword */ > - *cs++ = MI_NOOP; > - intel_ring_advance(rq, cs); > - > - cs = intel_ring_begin(rq, 6); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = GFX_OP_PIPE_CONTROL(5); > - *cs++ = PIPE_CONTROL_QW_WRITE; > - *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; > - *cs++ = 0; > - *cs++ = 0; > - *cs++ = MI_NOOP; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static int > -gen6_render_ring_flush(struct i915_request *rq, u32 mode) > -{ > - u32 scratch_addr = > - intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); > - u32 *cs, flags = 0; > - int ret; > - > - /* Force SNB workarounds for PIPE_CONTROL flushes */ > - ret = gen6_emit_post_sync_nonzero_flush(rq); > - if (ret) > - return ret; > - > - /* Just flush everything. Experiments have shown that reducing the > - * number of bits based on the write domains has little performance > - * impact. > - */ > - if (mode & EMIT_FLUSH) { > - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > - /* > - * Ensure that any following seqno writes only happen > - * when the render cache is indeed flushed. > - */ > - flags |= PIPE_CONTROL_CS_STALL; > - } > - if (mode & EMIT_INVALIDATE) { > - flags |= PIPE_CONTROL_TLB_INVALIDATE; > - flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; > - /* > - * TLB invalidate requires a post-sync write. > - */ > - flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; > - } > - > - cs = intel_ring_begin(rq, 4); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = GFX_OP_PIPE_CONTROL(4); > - *cs++ = flags; > - *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; > - *cs++ = 0; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) > -{ > - /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ > - *cs++ = GFX_OP_PIPE_CONTROL(4); > - *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; > - *cs++ = 0; > - *cs++ = 0; > - > - *cs++ = GFX_OP_PIPE_CONTROL(4); > - *cs++ = PIPE_CONTROL_QW_WRITE; > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_DEFAULT) | > - PIPE_CONTROL_GLOBAL_GTT; > - *cs++ = 0; > - > - /* Finally we can flush and with it emit the breadcrumb */ > - *cs++ = GFX_OP_PIPE_CONTROL(4); > - *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > - PIPE_CONTROL_DEPTH_CACHE_FLUSH | > - PIPE_CONTROL_DC_FLUSH_ENABLE | > - PIPE_CONTROL_QW_WRITE | > - PIPE_CONTROL_CS_STALL); > - *cs++ = i915_request_active_timeline(rq)->hwsp_offset | > - PIPE_CONTROL_GLOBAL_GTT; > - *cs++ = rq->fence.seqno; > - > - *cs++ = MI_USER_INTERRUPT; > - *cs++ = MI_NOOP; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > - > - return cs; > -} > - > -static int > -gen7_render_ring_cs_stall_wa(struct i915_request *rq) > -{ > - u32 *cs; > - > - cs = intel_ring_begin(rq, 4); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = GFX_OP_PIPE_CONTROL(4); > - *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; > - *cs++ = 0; > - *cs++ = 0; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static int > -gen7_render_ring_flush(struct i915_request *rq, u32 mode) > -{ > - u32 scratch_addr = > - intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); > - u32 *cs, flags = 0; > - > - /* > - * Ensure that any following seqno writes only happen when the render > - * cache is indeed flushed. > - * > - * Workaround: 4th PIPE_CONTROL command (except the ones with only > - * read-cache invalidate bits set) must have the CS_STALL bit set. We > - * don't try to be clever and just set it unconditionally. > - */ > - flags |= PIPE_CONTROL_CS_STALL; > - > - /* > - * CS_STALL suggests at least a post-sync write. > - */ > - flags |= PIPE_CONTROL_QW_WRITE; > - flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; > - > - /* Just flush everything. Experiments have shown that reducing the > - * number of bits based on the write domains has little performance > - * impact. > - */ > - if (mode & EMIT_FLUSH) { > - flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; > - flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; > - flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; > - flags |= PIPE_CONTROL_FLUSH_ENABLE; > - } > - if (mode & EMIT_INVALIDATE) { > - flags |= PIPE_CONTROL_TLB_INVALIDATE; > - flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; > - flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; > - > - /* Workaround: we must issue a pipe_control with CS-stall bit > - * set before a pipe_control command that has the state cache > - * invalidate bit set. */ > - gen7_render_ring_cs_stall_wa(rq); > - } > - > - cs = intel_ring_begin(rq, 4); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = GFX_OP_PIPE_CONTROL(4); > - *cs++ = flags; > - *cs++ = scratch_addr; > - *cs++ = 0; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) > -{ > - *cs++ = GFX_OP_PIPE_CONTROL(4); > - *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | > - PIPE_CONTROL_DEPTH_CACHE_FLUSH | > - PIPE_CONTROL_DC_FLUSH_ENABLE | > - PIPE_CONTROL_FLUSH_ENABLE | > - PIPE_CONTROL_QW_WRITE | > - PIPE_CONTROL_GLOBAL_GTT_IVB | > - PIPE_CONTROL_CS_STALL); > - *cs++ = i915_request_active_timeline(rq)->hwsp_offset; > - *cs++ = rq->fence.seqno; > - > - *cs++ = MI_USER_INTERRUPT; > - *cs++ = MI_NOOP; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > - > - return cs; > -} > - > -static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) > -{ > - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > - > - *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; > - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; > - *cs++ = rq->fence.seqno; > - > - *cs++ = MI_USER_INTERRUPT; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > - > - return cs; > -} > - > -#define GEN7_XCS_WA 32 > -static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) > -{ > - int i; > - > - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > - > - *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | > - MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; > - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; > - *cs++ = rq->fence.seqno; > - > - for (i = 0; i < GEN7_XCS_WA; i++) { > - *cs++ = MI_STORE_DWORD_INDEX; > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; > - *cs++ = rq->fence.seqno; > - } > - > - *cs++ = MI_FLUSH_DW; > - *cs++ = 0; > - *cs++ = 0; > - > - *cs++ = MI_USER_INTERRUPT; > - *cs++ = MI_NOOP; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > - > - return cs; > -} > -#undef GEN7_XCS_WA > - > static void set_hwstam(struct intel_engine_cs *engine, u32 mask) > { > /* > @@ -918,255 +482,6 @@ static void i9xx_submit_request(struct i915_request *request) > intel_ring_set_tail(request->ring, request->tail)); > } > > -static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) > -{ > - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > - > - *cs++ = MI_FLUSH; > - > - *cs++ = MI_STORE_DWORD_INDEX; > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; > - *cs++ = rq->fence.seqno; > - > - *cs++ = MI_USER_INTERRUPT; > - *cs++ = MI_NOOP; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > - > - return cs; > -} > - > -#define GEN5_WA_STORES 8 /* must be at least 1! */ > -static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) > -{ > - int i; > - > - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > - > - *cs++ = MI_FLUSH; > - > - BUILD_BUG_ON(GEN5_WA_STORES < 1); > - for (i = 0; i < GEN5_WA_STORES; i++) { > - *cs++ = MI_STORE_DWORD_INDEX; > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; > - *cs++ = rq->fence.seqno; > - } > - > - *cs++ = MI_USER_INTERRUPT; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > - > - return cs; > -} > -#undef GEN5_WA_STORES > - > -static void > -gen5_irq_enable(struct intel_engine_cs *engine) > -{ > - gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); > -} > - > -static void > -gen5_irq_disable(struct intel_engine_cs *engine) > -{ > - gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); > -} > - > -static void > -i9xx_irq_enable(struct intel_engine_cs *engine) > -{ > - engine->i915->irq_mask &= ~engine->irq_enable_mask; > - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > - intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); > -} > - > -static void > -i9xx_irq_disable(struct intel_engine_cs *engine) > -{ > - engine->i915->irq_mask |= engine->irq_enable_mask; > - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); > -} > - > -static void > -i8xx_irq_enable(struct intel_engine_cs *engine) > -{ > - struct drm_i915_private *i915 = engine->i915; > - > - i915->irq_mask &= ~engine->irq_enable_mask; > - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); > - ENGINE_POSTING_READ16(engine, RING_IMR); > -} > - > -static void > -i8xx_irq_disable(struct intel_engine_cs *engine) > -{ > - struct drm_i915_private *i915 = engine->i915; > - > - i915->irq_mask |= engine->irq_enable_mask; > - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); > -} > - > -static int > -bsd_ring_flush(struct i915_request *rq, u32 mode) > -{ > - u32 *cs; > - > - cs = intel_ring_begin(rq, 2); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = MI_FLUSH; > - *cs++ = MI_NOOP; > - intel_ring_advance(rq, cs); > - return 0; > -} > - > -static void > -gen6_irq_enable(struct intel_engine_cs *engine) > -{ > - ENGINE_WRITE(engine, RING_IMR, > - ~(engine->irq_enable_mask | engine->irq_keep_mask)); > - > - /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ > - ENGINE_POSTING_READ(engine, RING_IMR); > - > - gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); > -} > - > -static void > -gen6_irq_disable(struct intel_engine_cs *engine) > -{ > - ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); > - gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); > -} > - > -static void > -hsw_vebox_irq_enable(struct intel_engine_cs *engine) > -{ > - ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); > - > - /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ > - ENGINE_POSTING_READ(engine, RING_IMR); > - > - gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); > -} > - > -static void > -hsw_vebox_irq_disable(struct intel_engine_cs *engine) > -{ > - ENGINE_WRITE(engine, RING_IMR, ~0); > - gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); > -} > - > -static int > -i965_emit_bb_start(struct i915_request *rq, > - u64 offset, u32 length, > - unsigned int dispatch_flags) > -{ > - u32 *cs; > - > - cs = intel_ring_begin(rq, 2); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & > - I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); > - *cs++ = offset; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -/* Just userspace ABI convention to limit the wa batch bo to a resonable size */ > -#define I830_BATCH_LIMIT SZ_256K > -#define I830_TLB_ENTRIES (2) > -#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) > -static int > -i830_emit_bb_start(struct i915_request *rq, > - u64 offset, u32 len, > - unsigned int dispatch_flags) > -{ > - u32 *cs, cs_offset = > - intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_DEFAULT); > - > - GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE); > - > - cs = intel_ring_begin(rq, 6); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - /* Evict the invalid PTE TLBs */ > - *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; > - *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; > - *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ > - *cs++ = cs_offset; > - *cs++ = 0xdeadbeef; > - *cs++ = MI_NOOP; > - intel_ring_advance(rq, cs); > - > - if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { > - if (len > I830_BATCH_LIMIT) > - return -ENOSPC; > - > - cs = intel_ring_begin(rq, 6 + 2); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - /* Blit the batch (which has now all relocs applied) to the > - * stable batch scratch bo area (so that the CS never > - * stumbles over its tlb invalidation bug) ... > - */ > - *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2); > - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; > - *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; > - *cs++ = cs_offset; > - *cs++ = 4096; > - *cs++ = offset; > - > - *cs++ = MI_FLUSH; > - *cs++ = MI_NOOP; > - intel_ring_advance(rq, cs); > - > - /* ... and execute it. */ > - offset = cs_offset; > - } > - > - cs = intel_ring_begin(rq, 2); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; > - *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : > - MI_BATCH_NON_SECURE); > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static int > -i915_emit_bb_start(struct i915_request *rq, > - u64 offset, u32 len, > - unsigned int dispatch_flags) > -{ > - u32 *cs; > - > - cs = intel_ring_begin(rq, 2); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; > - *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : > - MI_BATCH_NON_SECURE); > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > static void __ring_context_fini(struct intel_context *ce) > { > i915_vma_put(ce->state); > @@ -1704,99 +1019,6 @@ static void gen6_bsd_submit_request(struct i915_request *request) > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); > } > > -static int mi_flush_dw(struct i915_request *rq, u32 flags) > -{ > - u32 cmd, *cs; > - > - cs = intel_ring_begin(rq, 4); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - cmd = MI_FLUSH_DW; > - > - /* > - * We always require a command barrier so that subsequent > - * commands, such as breadcrumb interrupts, are strictly ordered > - * wrt the contents of the write cache being flushed to memory > - * (and thus being coherent from the CPU). > - */ > - cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; > - > - /* > - * Bspec vol 1c.3 - blitter engine command streamer: > - * "If ENABLED, all TLBs will be invalidated once the flush > - * operation is complete. This bit is only valid when the > - * Post-Sync Operation field is a value of 1h or 3h." > - */ > - cmd |= flags; > - > - *cs++ = cmd; > - *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; > - *cs++ = 0; > - *cs++ = MI_NOOP; > - > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) > -{ > - return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); > -} > - > -static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) > -{ > - return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); > -} > - > -static int > -hsw_emit_bb_start(struct i915_request *rq, > - u64 offset, u32 len, > - unsigned int dispatch_flags) > -{ > - u32 *cs; > - > - cs = intel_ring_begin(rq, 2); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? > - 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); > - /* bit0-7 is the length on GEN6+ */ > - *cs++ = offset; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -static int > -gen6_emit_bb_start(struct i915_request *rq, > - u64 offset, u32 len, > - unsigned int dispatch_flags) > -{ > - u32 *cs; > - > - cs = intel_ring_begin(rq, 2); > - if (IS_ERR(cs)) > - return PTR_ERR(cs); > - > - *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? > - 0 : MI_BATCH_NON_SECURE_I965); > - /* bit0-7 is the length on GEN6+ */ > - *cs++ = offset; > - intel_ring_advance(rq, cs); > - > - return 0; > -} > - > -/* Blitter support (SandyBridge+) */ > - > -static int gen6_ring_flush(struct i915_request *rq, u32 mode) > -{ > - return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); > -} > - > static void i9xx_set_default_submission(struct intel_engine_cs *engine) > { > engine->submit_request = i9xx_submit_request; > @@ -1843,11 +1065,11 @@ static void setup_irq(struct intel_engine_cs *engine) > engine->irq_enable = gen5_irq_enable; > engine->irq_disable = gen5_irq_disable; > } else if (INTEL_GEN(i915) >= 3) { > - engine->irq_enable = i9xx_irq_enable; > - engine->irq_disable = i9xx_irq_disable; > + engine->irq_enable = gen3_irq_enable; > + engine->irq_disable = gen3_irq_disable; > } else { > - engine->irq_enable = i8xx_irq_enable; > - engine->irq_disable = i8xx_irq_disable; > + engine->irq_enable = gen2_irq_enable; > + engine->irq_disable = gen2_irq_disable; > } > } > > @@ -1874,7 +1096,7 @@ static void setup_common(struct intel_engine_cs *engine) > * equivalent to our next initial bread so we can elide > * engine->emit_init_breadcrumb(). > */ > - engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; > + engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; > if (IS_GEN(i915, 5)) > engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; > > @@ -1883,11 +1105,11 @@ static void setup_common(struct intel_engine_cs *engine) > if (INTEL_GEN(i915) >= 6) > engine->emit_bb_start = gen6_emit_bb_start; > else if (INTEL_GEN(i915) >= 4) > - engine->emit_bb_start = i965_emit_bb_start; > + engine->emit_bb_start = gen4_emit_bb_start; > else if (IS_I830(i915) || IS_I845G(i915)) > engine->emit_bb_start = i830_emit_bb_start; > else > - engine->emit_bb_start = i915_emit_bb_start; > + engine->emit_bb_start = gen3_emit_bb_start; > } > > static void setup_rcs(struct intel_engine_cs *engine) > @@ -1900,18 +1122,18 @@ static void setup_rcs(struct intel_engine_cs *engine) > engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; > > if (INTEL_GEN(i915) >= 7) { > - engine->emit_flush = gen7_render_ring_flush; > - engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; > + engine->emit_flush = gen7_emit_flush_rcs; > + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; > } else if (IS_GEN(i915, 6)) { > - engine->emit_flush = gen6_render_ring_flush; > - engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; > + engine->emit_flush = gen6_emit_flush_rcs; > + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; > } else if (IS_GEN(i915, 5)) { > - engine->emit_flush = gen4_render_ring_flush; > + engine->emit_flush = gen4_emit_flush_rcs; > } else { > if (INTEL_GEN(i915) < 4) > - engine->emit_flush = gen2_render_ring_flush; > + engine->emit_flush = gen2_emit_flush; > else > - engine->emit_flush = gen4_render_ring_flush; > + engine->emit_flush = gen4_emit_flush_rcs; > engine->irq_enable_mask = I915_USER_INTERRUPT; > } > > @@ -1929,15 +1151,15 @@ static void setup_vcs(struct intel_engine_cs *engine) > /* gen6 bsd needs a special wa for tail updates */ > if (IS_GEN(i915, 6)) > engine->set_default_submission = gen6_bsd_set_default_submission; > - engine->emit_flush = gen6_bsd_ring_flush; > + engine->emit_flush = gen6_emit_flush_vcs; > engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; > > if (IS_GEN(i915, 6)) > - engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; > + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; > else > - engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; > + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; > } else { > - engine->emit_flush = bsd_ring_flush; > + engine->emit_flush = gen4_emit_flush_vcs; > if (IS_GEN(i915, 5)) > engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; > else > @@ -1949,13 +1171,13 @@ static void setup_bcs(struct intel_engine_cs *engine) > { > struct drm_i915_private *i915 = engine->i915; > > - engine->emit_flush = gen6_ring_flush; > + engine->emit_flush = gen6_emit_flush_xcs; > engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; > > if (IS_GEN(i915, 6)) > - engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; > + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; > else > - engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; > + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; > } > > static void setup_vecs(struct intel_engine_cs *engine) > @@ -1964,12 +1186,12 @@ static void setup_vecs(struct intel_engine_cs *engine) > > GEM_BUG_ON(INTEL_GEN(i915) < 7); > > - engine->emit_flush = gen6_ring_flush; > + engine->emit_flush = gen6_emit_flush_xcs; > engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; > - engine->irq_enable = hsw_vebox_irq_enable; > - engine->irq_disable = hsw_vebox_irq_disable; > + engine->irq_enable = hsw_irq_enable_vecs; > + engine->irq_disable = hsw_irq_disable_vecs; > > - engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; > + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; > } > > static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine, > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Tue Jun 2 09:05:42 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 02 Jun 2020 12:05:42 +0300 Subject: [Intel-gfx] [PATCH 03/36] drm/i915/gt: Move legacy context wa to intel_workarounds In-Reply-To: <20200601072446.19548-3-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-3-chris@chris-wilson.co.uk> Message-ID: <874krtj0rd.fsf@gaia.fi.intel.com> Chris Wilson writes: > Use the central mechanism for recording and verifying that we restore > the w/a for the older devices as well. > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > --- > .../gpu/drm/i915/gt/intel_ring_submission.c | 28 ----------------- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 +++++++++++++++++++ > 2 files changed, 31 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 96881cd8b17b..d9c1701061b9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -429,32 +429,6 @@ static void reset_finish(struct intel_engine_cs *engine) > { > } > > -static int rcs_resume(struct intel_engine_cs *engine) > -{ > - struct drm_i915_private *i915 = engine->i915; > - struct intel_uncore *uncore = engine->uncore; > - > - /* > - * Disable CONSTANT_BUFFER before it is loaded from the context > - * image. For as it is loaded, it is executed and the stored > - * address may no longer be valid, leading to a GPU hang. > - * > - * This imposes the requirement that userspace reload their > - * CONSTANT_BUFFER on every batch, fortunately a requirement > - * they are already accustomed to from before contexts were > - * enabled. > - */ > - if (IS_GEN(i915, 4)) > - intel_uncore_write(uncore, ECOSKPD, > - _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)); > - > - if (IS_GEN_RANGE(i915, 6, 7)) > - intel_uncore_write(uncore, INSTPM, > - _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > - > - return xcs_resume(engine); > -} > - > static void reset_cancel(struct intel_engine_cs *engine) > { > struct i915_request *request; > @@ -1139,8 +1113,6 @@ static void setup_rcs(struct intel_engine_cs *engine) > > if (IS_HASWELL(i915)) > engine->emit_bb_start = hsw_emit_bb_start; > - > - engine->resume = rcs_resume; > } > > static void setup_vcs(struct intel_engine_cs *engine) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index fa1e15657663..94d66a9d760d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -199,6 +199,18 @@ wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) > #define WA_SET_FIELD_MASKED(addr, mask, value) \ > wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) > > +static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, > + struct i915_wa_list *wal) > +{ > + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); > +} > + > +static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, > + struct i915_wa_list *wal) > +{ > + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); > +} > + > static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > { > @@ -638,6 +650,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, > chv_ctx_workarounds_init(engine, wal); > else if (IS_BROADWELL(i915)) > bdw_ctx_workarounds_init(engine, wal); > + else if (IS_GEN(i915, 7)) > + gen7_ctx_workarounds_init(engine, wal); > + else if (IS_GEN(i915, 6)) > + gen6_ctx_workarounds_init(engine, wal); > else if (INTEL_GEN(i915) < 8) > return; > else > @@ -1583,6 +1599,21 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), > /* XXX bit doesn't stick on Broadwater */ > IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); > + > + if (IS_GEN(i915, 4)) > + /* > + * Disable CONSTANT_BUFFER before it is loaded from the context > + * image. For as it is loaded, it is executed and the stored > + * address may no longer be valid, leading to a GPU hang. > + * > + * This imposes the requirement that userspace reload their > + * CONSTANT_BUFFER on every batch, fortunately a requirement > + * they are already accustomed to from before contexts were > + * enabled. > + */ > + wa_add(wal, ECOSKPD, > + 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), > + 0 /* XXX bit doesn't stick on Broadwater */); > } > > static void > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Tue Jun 2 09:18:34 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 02 Jun 2020 12:18:34 +0300 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness In-Reply-To: <20200602002650.1355736-1-chris@chris-wilson.co.uk> References: <20200602002650.1355736-1-chris@chris-wilson.co.uk> Message-ID: <87pnahsu51.fsf@gaia.fi.intel.com> Chris Wilson writes: > An important property for multi-client systems is that each client gets > a 'fair' allotment of system time. (Where fairness is at the whim of the > context properties, such as priorities.) This test forks N independent > clients (albeit they happen to share a single vm), and does an equal > amount of work in client and asserts that they take an equal amount of > time. > > Though we have never claimed to have a completely fair scheduler, that > is what is expected. > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > Cc: Ramalingam C > --- > tests/i915/gem_exec_schedule.c | 418 +++++++++++++++++++++++++++++++++ > 1 file changed, 418 insertions(+) > > diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c > index 56c638833..d1121ecd2 100644 > --- a/tests/i915/gem_exec_schedule.c > +++ b/tests/i915/gem_exec_schedule.c > @@ -2495,6 +2495,417 @@ static void measure_semaphore_power(int i915) > rapl_close(&pkg); > } > > +static int read_timestamp_frequency(int i915) > +{ > + int value = 0; > + drm_i915_getparam_t gp = { > + .value = &value, > + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, > + }; > + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); > + return value; > +} > + > +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) > +{ > + return (x + y - 1) / y; > +} > + > +static uint64_t ns_to_ticks(int i915, uint64_t ns) > +{ > + return div64_u64_round_up(ns * read_timestamp_frequency(i915), > + NSEC_PER_SEC); > +} > + > +static uint64_t ticks_to_ns(int i915, uint64_t ticks) > +{ > + return div64_u64_round_up(ticks * NSEC_PER_SEC, > + read_timestamp_frequency(i915)); > +} > + > +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) > + > +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) > +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) > +/* Opcodes for MI_MATH_INSTR */ > +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) > +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) > +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) > +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) > +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) > +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) > +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) > +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) > +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) > +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) > +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) > +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) > +/* Registers used as operands in MI_MATH_INSTR */ > +#define MI_MATH_REG(x) (x) > +#define MI_MATH_REG_SRCA 0x20 > +#define MI_MATH_REG_SRCB 0x21 > +#define MI_MATH_REG_ACCU 0x31 > +#define MI_MATH_REG_ZF 0x32 > +#define MI_MATH_REG_CF 0x33 Are you thinking that we should just pull in the driver gpu_commands.h as is into lib? -Mika > + > +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) > + > +static void delay(int i915, > + const struct intel_execution_engine2 *e, > + uint32_t handle, > + uint64_t addr, > + uint64_t ns) > +{ > + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; > + const uint32_t base = gem_engine_mmio_base(i915, e->name); > +#define CS_GPR(x) (base + 0x600 + 8 * (x)) > +#define TIMESTAMP (base + 0x3a8) > + enum { START_TS, NOW_TS }; > + uint32_t *map, *cs, *jmp; > + > + igt_require(base); > + > + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); > + > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(START_TS) + 4; > + *cs++ = 0; > + *cs++ = MI_LOAD_REGISTER_REG; > + *cs++ = TIMESTAMP; > + *cs++ = CS_GPR(START_TS); > + > + if (offset_in_page(cs) & 4) > + *cs++ = 0; > + jmp = cs; > + > + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ > + > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(NOW_TS) + 4; > + *cs++ = 0; > + *cs++ = MI_LOAD_REGISTER_REG; > + *cs++ = TIMESTAMP; > + *cs++ = CS_GPR(NOW_TS); > + > + *cs++ = MI_MATH(4); > + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); > + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); > + *cs++ = MI_MATH_SUB; > + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); > + > + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ > + *cs++ = CS_GPR(NOW_TS); > + *cs++ = addr + 4000; > + *cs++ = addr >> 32; > + > + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); > + *cs++ = ~ns_to_ticks(i915, ns); > + *cs++ = addr + 4000; > + *cs++ = addr >> 32; > + > + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; > + *cs++ = addr + offset_in_page(jmp); > + *cs++ = addr >> 32; > + > + munmap(map, 4096); > +} > + > +static struct drm_i915_gem_exec_object2 > +delay_create(int i915, uint32_t ctx, > + const struct intel_execution_engine2 *e, > + uint64_t target_ns) > +{ > + struct drm_i915_gem_exec_object2 obj = { > + .handle = batch_create(i915), > + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, > + }; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(&obj), > + .buffer_count = 1, > + .rsvd1 = ctx, > + .flags = e->flags, > + }; > + > + gem_execbuf(i915, &execbuf); > + gem_sync(i915, obj.handle); > + > + delay(i915, e, obj.handle, obj.offset, target_ns); > + > + obj.flags |= EXEC_OBJECT_PINNED; > + return obj; > +} > + > +static void tslog(int i915, > + const struct intel_execution_engine2 *e, > + uint32_t handle, > + uint64_t addr) > +{ > + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; > + const uint32_t base = gem_engine_mmio_base(i915, e->name); > +#define CS_GPR(x) (base + 0x600 + 8 * (x)) > +#define CS_TIMESTAMP (base + 0x358) > + enum { ONE, MASK, ADDR }; > + uint32_t *timestamp_lo, *addr_lo; > + uint32_t *map, *cs; > + > + igt_require(base); > + > + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); > + cs = map + 512; > + > + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ > + *cs++ = CS_TIMESTAMP; > + timestamp_lo = cs; > + *cs++ = addr; > + *cs++ = addr >> 32; > + > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(ADDR); > + addr_lo = cs; > + *cs++ = addr; > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(ADDR) + 4; > + *cs++ = addr >> 32; > + > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(ONE); > + *cs++ = 4; > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(ONE) + 4; > + *cs++ = 0; > + > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(MASK); > + *cs++ = 0xfffff7ff; > + *cs++ = MI_LOAD_REGISTER_IMM; > + *cs++ = CS_GPR(MASK) + 4; > + *cs++ = 0xffffffff; > + > + *cs++ = MI_MATH(8); > + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); > + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); > + *cs++ = MI_MATH_ADD; > + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); > + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); > + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); > + *cs++ = MI_MATH_AND; > + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); > + > + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ > + *cs++ = CS_GPR(ADDR); > + *cs++ = addr + offset_in_page(timestamp_lo); > + *cs++ = addr >> 32; > + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ > + *cs++ = CS_GPR(ADDR); > + *cs++ = addr + offset_in_page(addr_lo); > + *cs++ = addr >> 32; > + > + *cs++ = MI_BATCH_BUFFER_END; > + > + munmap(map, 4096); > +} > + > +static struct drm_i915_gem_exec_object2 > +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) > +{ > + struct drm_i915_gem_exec_object2 obj = { > + .handle = batch_create(i915), > + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, > + }; > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(&obj), > + .buffer_count = 1, > + .rsvd1 = ctx, > + .flags = e->flags, > + }; > + > + gem_execbuf(i915, &execbuf); > + gem_sync(i915, obj.handle); > + > + tslog(i915, e, obj.handle, obj.offset); > + > + obj.flags |= EXEC_OBJECT_PINNED; > + return obj; > +} > + > +static int cmp_u32(const void *A, const void *B) > +{ > + const unsigned long *a = A, *b = B; > + > + if (*a < *b) > + return -1; > + else if (*a > *b) > + return 1; > + else > + return 0; > +} > + > +static void fair_child(int i915, uint32_t ctx, > + const struct intel_execution_engine2 *e, > + uint64_t frame_ns, > + int timeout, > + int timeline, > + unsigned int flags, > + unsigned long *ctl, > + unsigned long *out) > +#define F_PACING 0x1 > +#define F_EXTERNAL 0x2 > +{ > + const int batches_per_frame = 3; > + struct drm_i915_gem_exec_object2 prev = > + delay_create(i915, ctx, e, frame_ns / batches_per_frame); > + struct drm_i915_gem_exec_object2 next = > + delay_create(i915, ctx, e, frame_ns / batches_per_frame); > + struct drm_i915_gem_exec_object2 ts = tslog_create(i915, ctx, e); > + struct timespec tv = {}; > + unsigned long count = 0; > + int p_fence = -1, n_fence = -1; > + uint32_t *map; > + int n; > + > + igt_nsec_elapsed(&tv); > + while (!READ_ONCE(*ctl)) { > + struct drm_i915_gem_execbuffer2 execbuf = { > + .buffers_ptr = to_user_pointer(&next), > + .buffer_count = 1, > + .rsvd1 = ctx, > + .rsvd2 = -1, > + .flags = e->flags, > + }; > + > + if (flags & F_EXTERNAL) { > + execbuf.rsvd2 = > + sw_sync_timeline_create_fence(timeline, count); > + execbuf.flags |= I915_EXEC_FENCE_IN; > + } > + > + execbuf.flags |= I915_EXEC_FENCE_OUT; > + gem_execbuf_wr(i915, &execbuf); > + n_fence = execbuf.rsvd2 >> 32; > + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); > + for (n = 1; n < batches_per_frame; n++) > + gem_execbuf(i915, &execbuf); > + > + execbuf.buffers_ptr = to_user_pointer(&ts); > + execbuf.batch_start_offset = 2048; > + gem_execbuf(i915, &execbuf); > + > + if (flags & F_PACING && p_fence != -1) { > + struct pollfd pfd = { > + .fd = p_fence, > + .events = POLLIN, > + }; > + poll(&pfd, 1, -1); > + } > + close(p_fence); > + close(execbuf.rsvd2); > + > + igt_swap(prev, next); > + igt_swap(p_fence, n_fence); > + count++; > + } > + gem_sync(i915, prev.handle); > + close(p_fence); > + > + gem_close(i915, next.handle); > + gem_close(i915, prev.handle); > + > + map = gem_mmap__device_coherent(i915, ts.handle, 0, 4096, PROT_WRITE); > + for (n = 1; n < min(count, 512); n++) > + map[n - 1] = map[n] - map[n - 1]; > + qsort(map, --n, sizeof(*map), cmp_u32); > + *out = ticks_to_ns(i915, map[n / 2]); > + munmap(map, 4096); > + > + gem_close(i915, ts.handle); > +} > + > +static int cmp_ul(const void *A, const void *B) > +{ > + const unsigned long *a = A, *b = B; > + > + if (*a < *b) > + return -1; > + else if (*a > *b) > + return 1; > + else > + return 0; > +} > + > +static void fairness(int i915, > + const struct intel_execution_engine2 *e, > + int timeout, unsigned int flags) > +{ > + const int frame_ns = 16666 * 1000; > + unsigned long *result; > + > + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); > + igt_require(gem_class_has_mutable_submission(i915, e->class)); > + > + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); > + > + for (int n = 2; n <= 16; n <<= 1) { > + int timeline = sw_sync_timeline_create(); > + int nframes = timeout * NSEC_PER_SEC / frame_ns + 1; > + const int nchild = n - 1; /* odd for easy medians */ > + const int lo = nchild / 4; > + const int hi = (3 * nchild + 3) / 4 - 1; > + struct igt_mean m; > + > + memset(result, 0, (nchild + 1) * sizeof(result[0])); > + igt_fork(child, nchild) { > + uint32_t ctx = gem_context_clone_with_engines(i915, 0); > + > + fair_child(i915, ctx, e, frame_ns / nchild, > + timeout, timeline, flags, > + &result[nchild], > + &result[child]); > + > + gem_context_destroy(i915, ctx); > + } > + > + while (nframes--) { > + struct timespec tv = { .tv_nsec = frame_ns }; > + nanosleep(&tv, NULL); > + sw_sync_timeline_inc(timeline, 1); > + } > + result[nchild] = 1; > + for (int child = 0; child < nchild; child++) { > + while (!READ_ONCE(result[child])) { > + struct timespec tv = { .tv_nsec = frame_ns }; > + nanosleep(&tv, NULL); > + sw_sync_timeline_inc(timeline, 1); > + } > + } > + igt_waitchildren(); > + close(timeline); > + > + igt_mean_init(&m); > + for (int child = 0; child < nchild; child++) > + igt_mean_add(&m, result[child]); > + > + qsort(result, nchild, sizeof(*result), cmp_ul); > + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", > + nchild, > + 1e-6 * result[0], 1e-6 * result[nchild - 1], > + 1e-6 * result[lo], 1e-6 * result[hi], > + 1e-6 * result[nchild / 2], > + 1e-6 * igt_mean_get(&m), > + 1e-6 * sqrt(igt_mean_get_variance(&m))); > + > +#if 0 > + /* Mean within 10% of target */ > + igt_assert( 9 * igt_mean_get(&m) > 10 * frame_ns && > + 10 * igt_mean_get(&m) < 9 * frame_ns); > + > + /* Variance [inter-quartile range] is less than 33% of median */ > + igt_assert(3 * result[hi] - result[lo] < result[nchild / 2]); > +#endif > + } > + > + munmap(result, 4096); > +} > + > #define test_each_engine(T, i915, e) \ > igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ > igt_dynamic_f("%s", e->name) > @@ -2589,6 +3000,13 @@ igt_main > test_each_engine_store("promotion", fd, e) > promotion(fd, e->flags); > > + test_each_engine_store("fair-none", fd, e) > + fairness(fd, e, 2, 0); > + test_each_engine_store("fair-pace", fd, e) > + fairness(fd, e, 2, F_PACING); > + test_each_engine_store("fair-sync", fd, e) > + fairness(fd, e, 2, F_PACING | F_EXTERNAL); > + > igt_subtest_group { > igt_fixture { > igt_require(gem_scheduler_has_preemption(fd)); > -- > 2.27.0.rc2 > > _______________________________________________ > igt-dev mailing list > igt-dev at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/igt-dev From chris at chris-wilson.co.uk Tue Jun 2 09:23:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 02 Jun 2020 10:23:41 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness In-Reply-To: <87pnahsu51.fsf@gaia.fi.intel.com> References: <20200602002650.1355736-1-chris@chris-wilson.co.uk> <87pnahsu51.fsf@gaia.fi.intel.com> Message-ID: <159108982127.29407.999463186059558684@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-02 10:18:34) > Chris Wilson writes: > > > An important property for multi-client systems is that each client gets > > a 'fair' allotment of system time. (Where fairness is at the whim of the > > context properties, such as priorities.) This test forks N independent > > clients (albeit they happen to share a single vm), and does an equal > > amount of work in client and asserts that they take an equal amount of > > time. > > > > Though we have never claimed to have a completely fair scheduler, that > > is what is expected. > > > > Signed-off-by: Chris Wilson > > Cc: Tvrtko Ursulin > > Cc: Ramalingam C > > --- > > tests/i915/gem_exec_schedule.c | 418 +++++++++++++++++++++++++++++++++ > > 1 file changed, 418 insertions(+) > > > > diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c > > index 56c638833..d1121ecd2 100644 > > --- a/tests/i915/gem_exec_schedule.c > > +++ b/tests/i915/gem_exec_schedule.c > > @@ -2495,6 +2495,417 @@ static void measure_semaphore_power(int i915) > > rapl_close(&pkg); > > } > > > > +static int read_timestamp_frequency(int i915) > > +{ > > + int value = 0; > > + drm_i915_getparam_t gp = { > > + .value = &value, > > + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, > > + }; > > + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); > > + return value; > > +} > > + > > +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) > > +{ > > + return (x + y - 1) / y; > > +} > > + > > +static uint64_t ns_to_ticks(int i915, uint64_t ns) > > +{ > > + return div64_u64_round_up(ns * read_timestamp_frequency(i915), > > + NSEC_PER_SEC); > > +} > > + > > +static uint64_t ticks_to_ns(int i915, uint64_t ticks) > > +{ > > + return div64_u64_round_up(ticks * NSEC_PER_SEC, > > + read_timestamp_frequency(i915)); > > +} > > + > > +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) > > + > > +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) > > +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) > > +/* Opcodes for MI_MATH_INSTR */ > > +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) > > +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) > > +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) > > +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) > > +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) > > +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) > > +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) > > +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) > > +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) > > +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) > > +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) > > +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) > > +/* Registers used as operands in MI_MATH_INSTR */ > > +#define MI_MATH_REG(x) (x) > > +#define MI_MATH_REG_SRCA 0x20 > > +#define MI_MATH_REG_SRCB 0x21 > > +#define MI_MATH_REG_ACCU 0x31 > > +#define MI_MATH_REG_ZF 0x32 > > +#define MI_MATH_REG_CF 0x33 > > Are you thinking that we should just pull in the driver gpu_commands.h > as is into lib? Yes. We should at least share the header for mi commands between the kernel and igt. -Chris From daniel at ffwll.ch Tue Jun 2 09:43:59 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 2 Jun 2020 11:43:59 +0200 Subject: [Intel-gfx] [PATCH] drm/atomic-helper: reset vblank on crtc reset In-Reply-To: <20200530032258.GD5961@pendragon.ideasonboard.com> References: <20200527094757.1414174-2-daniel.vetter@ffwll.ch> <20200527095332.1439425-1-daniel.vetter@ffwll.ch> <20200530032258.GD5961@pendragon.ideasonboard.com> Message-ID: <20200602094359.GA20149@phenom.ffwll.local> On Sat, May 30, 2020 at 06:22:58AM +0300, Laurent Pinchart wrote: > Hi Daniel, > > Thank you for the patch. > > On Wed, May 27, 2020 at 11:53:32AM +0200, Daniel Vetter wrote: > > Only when vblanks are supported ofc. > > > > Some drivers do this already, but most unfortunately missed it. This > > opens up bugs after driver load, before the crtc is enabled for the > > first time. syzbot spotted this when loading vkms as a secondary > > output. Given how many drivers are buggy it's best to solve this once > > and for all in shared helper code. > > > > Aside from moving the few existing calls to drm_crtc_vblank_reset into > > helpers (i915 doesn't use helpers, so keeps its own) I think the > > regression risk is minimal: atomic helpers already rely on drivers > > calling drm_crtc_vblank_on/off correctly in their hooks when they > > support vblanks. And driver that's failing to handle vblanks after > > this is missing those calls already, and vblanks could only work by > > accident when enabling a CRTC for the first time right after boot. > > > > Big thanks to Tetsuo for helping track down what's going wrong here. > > > > There's only a few drivers which already had the necessary call and > > needed some updating: > > - komeda, atmel and tidss also needed to be changed to call > > __drm_atomic_helper_crtc_reset() intead of open coding it > > - tegra and msm even had it in the same place already, just code > > motion, and malidp already uses __drm_atomic_helper_crtc_reset(). > > Have you intentionally not touched drivers that use > drm_crtc_vblank_off() at init time instead of drm_crtc_vblank_reset() ? > I'm thinking about omapdrm and rcar-du that both call neither > drm_crtc_vblank_reset() nor __drm_atomic_helper_crtc_reset() in their > CRTC reset handler, and call drm_crtc_vblank_off() at init time. Should > these (and likely other) drivers be updated ? Good catch, I think we should remove those too with this patch. I also used that opportunity to review all callers fo drm_crtc_vblank_off, and I found two bogus callers in malidp and hdlcd. But only in the unload code, so doesn't matter much. I'll resend a new version. -Daniel > Other than that the patch looks good to me, > > Reviewed-by: Laurent Pinchart > > > Only call left is in i915, which doesn't use drm_mode_config_reset, > > but has its own fastboot infrastructure. So that's the only case where > > we actually want this in the driver still. > > > > I've also reviewed all other drivers which set up vblank support with > > drm_vblank_init. After the previous patch fixing mxsfb all atomic > > drivers do call drm_crtc_vblank_on/off as they should, the remaining > > drivers are either legacy kms or legacy dri1 drivers, so not affected > > by this change to atomic helpers. > > > > v2: Use the drm_dev_has_vblank() helper. > > > > Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb > > Reported-by: Tetsuo Handa > > Reported-by: syzbot+0871b14ca2e2fb64f6e3 at syzkaller.appspotmail.com > > Cc: Tetsuo Handa > > Cc: "James (Qian) Wang" > > Cc: Liviu Dudau > > Cc: Mihail Atanassov > > Cc: Brian Starkey > > Cc: Sam Ravnborg > > Cc: Boris Brezillon > > Cc: Nicolas Ferre > > Cc: Alexandre Belloni > > Cc: Ludovic Desroches > > Cc: Maarten Lankhorst > > Cc: Maxime Ripard > > Cc: Thomas Zimmermann > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: Thierry Reding > > Cc: Jonathan Hunter > > Cc: Jyri Sarha > > Cc: Tomi Valkeinen > > Cc: Rob Clark > > Cc: Sean Paul > > Cc: Brian Masney > > Cc: Emil Velikov > > Cc: zhengbin > > Cc: Thomas Gleixner > > Cc: linux-tegra at vger.kernel.org > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++----- > > drivers/gpu/drm/arm/malidp_drv.c | 1 - > > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 ++----- > > drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ > > drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 -- > > drivers/gpu/drm/tegra/dc.c | 1 - > > drivers/gpu/drm/tidss/tidss_crtc.c | 3 +-- > > drivers/gpu/drm/tidss/tidss_kms.c | 4 ---- > > 8 files changed, 9 insertions(+), 20 deletions(-) > > > > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > > index 56bd938961ee..f33418d6e1a0 100644 > > --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > > @@ -492,10 +492,8 @@ static void komeda_crtc_reset(struct drm_crtc *crtc) > > crtc->state = NULL; > > > > state = kzalloc(sizeof(*state), GFP_KERNEL); > > - if (state) { > > - crtc->state = &state->base; > > - crtc->state->crtc = crtc; > > - } > > + if (state) > > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > > } > > > > static struct drm_crtc_state * > > @@ -616,7 +614,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, > > return err; > > > > drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); > > - drm_crtc_vblank_reset(crtc); > > > > crtc->port = kcrtc->master->of_output_port; > > > > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > > index c2507b7d8512..02904392e370 100644 > > --- a/drivers/gpu/drm/arm/malidp_drv.c > > +++ b/drivers/gpu/drm/arm/malidp_drv.c > > @@ -870,7 +870,6 @@ static int malidp_bind(struct device *dev) > > drm->irq_enabled = true; > > > > ret = drm_vblank_init(drm, drm->mode_config.num_crtc); > > - drm_crtc_vblank_reset(&malidp->crtc); > > if (ret < 0) { > > DRM_ERROR("failed to initialise vblank\n"); > > goto vblank_fail; > > diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > > index 10985134ce0b..ce246b96330b 100644 > > --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > > +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > > @@ -411,10 +411,8 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) > > } > > > > state = kzalloc(sizeof(*state), GFP_KERNEL); > > - if (state) { > > - crtc->state = &state->base; > > - crtc->state->crtc = crtc; > > - } > > + if (state) > > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > > } > > > > static struct drm_crtc_state * > > @@ -528,7 +526,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) > > } > > > > drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); > > - drm_crtc_vblank_reset(&crtc->base); > > > > drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); > > drm_crtc_enable_color_mgmt(&crtc->base, 0, false, > > diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c > > index 8fce6a115dfe..9ad74045158e 100644 > > --- a/drivers/gpu/drm/drm_atomic_state_helper.c > > +++ b/drivers/gpu/drm/drm_atomic_state_helper.c > > @@ -32,6 +32,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > #include > > @@ -93,6 +94,9 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, > > if (crtc_state) > > __drm_atomic_helper_crtc_state_reset(crtc_state, crtc); > > > > + if (drm_dev_has_vblank(crtc->dev)) > > + drm_crtc_vblank_reset(crtc); > > + > > crtc->state = crtc_state; > > } > > EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > > index ca3368c828d0..9606185c284b 100644 > > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > > @@ -1117,8 +1117,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc) > > mdp5_crtc_destroy_state(crtc, crtc->state); > > > > __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); > > - > > - drm_crtc_vblank_reset(crtc); > > } > > > > static const struct drm_crtc_funcs mdp5_crtc_funcs = { > > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > > index 83f31c6e891c..9b308b572eac 100644 > > --- a/drivers/gpu/drm/tegra/dc.c > > +++ b/drivers/gpu/drm/tegra/dc.c > > @@ -1168,7 +1168,6 @@ static void tegra_crtc_reset(struct drm_crtc *crtc) > > tegra_crtc_atomic_destroy_state(crtc, crtc->state); > > > > __drm_atomic_helper_crtc_reset(crtc, &state->base); > > - drm_crtc_vblank_reset(crtc); > > } > > > > static struct drm_crtc_state * > > diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c > > index 89a226912de8..4d01c4af61cd 100644 > > --- a/drivers/gpu/drm/tidss/tidss_crtc.c > > +++ b/drivers/gpu/drm/tidss/tidss_crtc.c > > @@ -352,8 +352,7 @@ static void tidss_crtc_reset(struct drm_crtc *crtc) > > return; > > } > > > > - crtc->state = &tcrtc->base; > > - crtc->state->crtc = crtc; > > + __drm_atomic_helper_crtc_reset(crtc, &tcrtc->base); > > } > > > > static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) > > diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c > > index 4b99e9fa84a5..e6ab59eed259 100644 > > --- a/drivers/gpu/drm/tidss/tidss_kms.c > > +++ b/drivers/gpu/drm/tidss/tidss_kms.c > > @@ -278,10 +278,6 @@ int tidss_modeset_init(struct tidss_device *tidss) > > if (ret) > > return ret; > > > > - /* Start with vertical blanking interrupt reporting disabled. */ > > - for (i = 0; i < tidss->num_crtcs; ++i) > > - drm_crtc_vblank_reset(tidss->crtcs[i]); > > - > > drm_mode_config_reset(ddev); > > > > dev_dbg(tidss->dev, "%s done\n", __func__); > > -- > Regards, > > Laurent Pinchart -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From maarten.lankhorst at linux.intel.com Tue Jun 2 09:45:48 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 2 Jun 2020 11:45:48 +0200 Subject: [Intel-gfx] [RFC 01/17] dma-fence: add might_sleep annotation to _wait() In-Reply-To: <0b1c65ec-adc2-9f02-da68-c398cf7ce80b@amd.com> References: <20200512085944.222637-1-daniel.vetter@ffwll.ch> <20200512085944.222637-2-daniel.vetter@ffwll.ch> <0b1c65ec-adc2-9f02-da68-c398cf7ce80b@amd.com> Message-ID: <105c02b5-f18d-cd08-bffa-93033c923365@linux.intel.com> Op 12-05-2020 om 11:08 schreef Christian K?nig: > Am 12.05.20 um 10:59 schrieb Daniel Vetter: >> But only for non-zero timeout, to avoid false positives. >> >> One question here is whether the might_sleep should be unconditional, >> or only for real timeouts. I'm not sure, so went with the more >> defensive option. But in the interest of locking down the cross-driver >> dma_fence rules we might want to be more aggressive. >> >> Cc: linux-media at vger.kernel.org >> Cc: linaro-mm-sig at lists.linaro.org >> Cc: linux-rdma at vger.kernel.org >> Cc: amd-gfx at lists.freedesktop.org >> Cc: intel-gfx at lists.freedesktop.org >> Cc: Chris Wilson >> Cc: Maarten Lankhorst >> Cc: Christian K?nig >> Signed-off-by: Daniel Vetter >> --- >> ? drivers/dma-buf/dma-fence.c | 3 +++ >> ? 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c >> index 052a41e2451c..6802125349fb 100644 >> --- a/drivers/dma-buf/dma-fence.c >> +++ b/drivers/dma-buf/dma-fence.c >> @@ -208,6 +208,9 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) >> ????? if (WARN_ON(timeout < 0)) >> ????????? return -EINVAL; >> ? +??? if (timeout > 0) >> +??????? might_sleep(); >> + > > I would rather like to see might_sleep() called here all the time even with timeout==0. > > IIRC I removed the code in TTM abusing this in atomic context quite a while ago, but could be that some leaked in again or it is called in atomic context elsewhere as well. Same, glad I'm not the only one who wants it. :) ~Maarten From daniel.vetter at ffwll.ch Tue Jun 2 09:51:39 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 2 Jun 2020 11:51:39 +0200 Subject: [Intel-gfx] [PATCH 2/3] drm/malidp: Don't call drm_crtc_vblank_off on unbind In-Reply-To: <20200602095140.36678-1-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> Message-ID: <20200602095140.36678-2-daniel.vetter@ffwll.ch> This is already done as part of the drm_atomic_helper_shutdown(), and in that case only for the crtc which are actually on. Signed-off-by: Daniel Vetter Cc: Liviu Dudau Cc: Brian Starkey Cc: --- drivers/gpu/drm/arm/malidp_drv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 02904392e370..db6ba5c78042 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -928,7 +928,6 @@ static void malidp_unbind(struct device *dev) drm_dev_unregister(drm); drm_kms_helper_poll_fini(drm); pm_runtime_get_sync(dev); - drm_crtc_vblank_off(&malidp->crtc); malidp_se_irq_fini(hwdev); malidp_de_irq_fini(hwdev); drm->irq_enabled = false; -- 2.26.2 From daniel.vetter at ffwll.ch Tue Jun 2 09:51:38 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 2 Jun 2020 11:51:38 +0200 Subject: [Intel-gfx] [PATCH 1/3] drm/atomic-helper: reset vblank on crtc reset Message-ID: <20200602095140.36678-1-daniel.vetter@ffwll.ch> Only when vblanks are supported ofc. Some drivers do this already, but most unfortunately missed it. This opens up bugs after driver load, before the crtc is enabled for the first time. syzbot spotted this when loading vkms as a secondary output. Given how many drivers are buggy it's best to solve this once and for all in shared helper code. Aside from moving the few existing calls to drm_crtc_vblank_reset into helpers (i915 doesn't use helpers, so keeps its own) I think the regression risk is minimal: atomic helpers already rely on drivers calling drm_crtc_vblank_on/off correctly in their hooks when they support vblanks. And driver that's failing to handle vblanks after this is missing those calls already, and vblanks could only work by accident when enabling a CRTC for the first time right after boot. Big thanks to Tetsuo for helping track down what's going wrong here. There's only a few drivers which already had the necessary call and needed some updating: - komeda, atmel and tidss also needed to be changed to call __drm_atomic_helper_crtc_reset() intead of open coding it - tegra and msm even had it in the same place already, just code motion, and malidp already uses __drm_atomic_helper_crtc_reset(). Only call left is in i915, which doesn't use drm_mode_config_reset, but has its own fastboot infrastructure. So that's the only case where we actually want this in the driver still. I've also reviewed all other drivers which set up vblank support with drm_vblank_init. After the previous patch fixing mxsfb all atomic drivers do call drm_crtc_vblank_on/off as they should, the remaining drivers are either legacy kms or legacy dri1 drivers, so not affected by this change to atomic helpers. v2: Use the drm_dev_has_vblank() helper. v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off instead of drm_crtc_vblank_reset. Adjust them too. Cc: Laurent Pinchart Reviewed-by: Laurent Pinchart Reviewed-by: Boris Brezillon Acked-by: Liviu Dudau Acked-by: Thierry Reding Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb Reported-by: Tetsuo Handa Reported-by: syzbot+0871b14ca2e2fb64f6e3 at syzkaller.appspotmail.com Cc: Tetsuo Handa Cc: "James (Qian) Wang" Cc: Liviu Dudau Cc: Mihail Atanassov Cc: Brian Starkey Cc: Sam Ravnborg Cc: Boris Brezillon Cc: Nicolas Ferre Cc: Alexandre Belloni Cc: Ludovic Desroches Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Daniel Vetter Cc: Thierry Reding Cc: Jonathan Hunter Cc: Jyri Sarha Cc: Tomi Valkeinen Cc: Rob Clark Cc: Sean Paul Cc: Brian Masney Cc: Emil Velikov Cc: zhengbin Cc: Thomas Gleixner Cc: linux-tegra at vger.kernel.org Signed-off-by: Daniel Vetter --- drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++----- drivers/gpu/drm/arm/malidp_drv.c | 1 - drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 ++----- drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 -- drivers/gpu/drm/omapdrm/omap_drv.c | 3 --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 --- drivers/gpu/drm/tegra/dc.c | 1 - drivers/gpu/drm/tidss/tidss_crtc.c | 3 +-- drivers/gpu/drm/tidss/tidss_kms.c | 4 ---- 10 files changed, 9 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 56bd938961ee..f33418d6e1a0 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -492,10 +492,8 @@ static void komeda_crtc_reset(struct drm_crtc *crtc) crtc->state = NULL; state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state) { - crtc->state = &state->base; - crtc->state->crtc = crtc; - } + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state * @@ -616,7 +614,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, return err; drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); - drm_crtc_vblank_reset(crtc); crtc->port = kcrtc->master->of_output_port; diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index c2507b7d8512..02904392e370 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -870,7 +870,6 @@ static int malidp_bind(struct device *dev) drm->irq_enabled = true; ret = drm_vblank_init(drm, drm->mode_config.num_crtc); - drm_crtc_vblank_reset(&malidp->crtc); if (ret < 0) { DRM_ERROR("failed to initialise vblank\n"); goto vblank_fail; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 10985134ce0b..ce246b96330b 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -411,10 +411,8 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) } state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state) { - crtc->state = &state->base; - crtc->state->crtc = crtc; - } + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state * @@ -528,7 +526,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) } drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); - drm_crtc_vblank_reset(&crtc->base); drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); drm_crtc_enable_color_mgmt(&crtc->base, 0, false, diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 8fce6a115dfe..9ad74045158e 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -93,6 +94,9 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, if (crtc_state) __drm_atomic_helper_crtc_state_reset(crtc_state, crtc); + if (drm_dev_has_vblank(crtc->dev)) + drm_crtc_vblank_reset(crtc); + crtc->state = crtc_state; } EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index ca3368c828d0..9606185c284b 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -1117,8 +1117,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc) mdp5_crtc_destroy_state(crtc, crtc->state); __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); - - drm_crtc_vblank_reset(crtc); } static const struct drm_crtc_funcs mdp5_crtc_funcs = { diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 242d28281784..7a7066cded79 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -642,9 +642,6 @@ static int omapdrm_init(struct omap_drm_private *priv, struct device *dev) goto err_cleanup_modeset; } - for (i = 0; i < priv->num_pipes; i++) - drm_crtc_vblank_off(priv->pipes[i].crtc); - omap_fbdev_init(ddev); drm_kms_helper_poll_init(ddev); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index d73e88ddecd0..e2959e32fd19 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -1271,9 +1271,6 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, drm_crtc_helper_add(crtc, &crtc_helper_funcs); - /* Start with vertical blanking interrupt reporting disabled. */ - drm_crtc_vblank_off(crtc); - /* Register the interrupt handler. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { /* The IRQ's are associated with the CRTC (sw)index. */ diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 83f31c6e891c..9b308b572eac 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1168,7 +1168,6 @@ static void tegra_crtc_reset(struct drm_crtc *crtc) tegra_crtc_atomic_destroy_state(crtc, crtc->state); __drm_atomic_helper_crtc_reset(crtc, &state->base); - drm_crtc_vblank_reset(crtc); } static struct drm_crtc_state * diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c index 89a226912de8..4d01c4af61cd 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -352,8 +352,7 @@ static void tidss_crtc_reset(struct drm_crtc *crtc) return; } - crtc->state = &tcrtc->base; - crtc->state->crtc = crtc; + __drm_atomic_helper_crtc_reset(crtc, &tcrtc->base); } static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c index 4b99e9fa84a5..e6ab59eed259 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -278,10 +278,6 @@ int tidss_modeset_init(struct tidss_device *tidss) if (ret) return ret; - /* Start with vertical blanking interrupt reporting disabled. */ - for (i = 0; i < tidss->num_crtcs; ++i) - drm_crtc_vblank_reset(tidss->crtcs[i]); - drm_mode_config_reset(ddev); dev_dbg(tidss->dev, "%s done\n", __func__); -- 2.26.2 From daniel.vetter at ffwll.ch Tue Jun 2 09:51:40 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 2 Jun 2020 11:51:40 +0200 Subject: [Intel-gfx] [PATCH 3/3] drm/hdlcd: Don't call drm_crtc_vblank_off on unbind In-Reply-To: <20200602095140.36678-1-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> Message-ID: <20200602095140.36678-3-daniel.vetter@ffwll.ch> This is already taken care of by drm_atomic_helper_shutdown(), and in that case only for the CRTC which are actually on. Only tricky bit here is that we kill the interrupt handling before we shut down crtc, so need to reorder that. Signed-off-by: Daniel Vetter Cc: Liviu Dudau Cc: Brian Starkey Cc: --- drivers/gpu/drm/arm/hdlcd_drv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c index 194419f47c5e..26bc5d7766f5 100644 --- a/drivers/gpu/drm/arm/hdlcd_drv.c +++ b/drivers/gpu/drm/arm/hdlcd_drv.c @@ -347,9 +347,8 @@ static void hdlcd_drm_unbind(struct device *dev) of_node_put(hdlcd->crtc.port); hdlcd->crtc.port = NULL; pm_runtime_get_sync(dev); - drm_crtc_vblank_off(&hdlcd->crtc); - drm_irq_uninstall(drm); drm_atomic_helper_shutdown(drm); + drm_irq_uninstall(drm); pm_runtime_put(dev); if (pm_runtime_enabled(dev)) pm_runtime_disable(dev); -- 2.26.2 From daniel.vetter at ffwll.ch Tue Jun 2 09:55:05 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 2 Jun 2020 11:55:05 +0200 Subject: [Intel-gfx] [PATCH] drm/malidp: Don't call drm_crtc_vblank_off on unbind In-Reply-To: <20200602095140.36678-2-daniel.vetter@ffwll.ch> References: <20200602095140.36678-2-daniel.vetter@ffwll.ch> Message-ID: <20200602095505.37509-1-daniel.vetter@ffwll.ch> This is already done as part of the drm_atomic_helper_shutdown(), and in that case only for the crtc which are actually on. v2: I overlooked that malidp also needs to have it's interrupt shut down reordered. Signed-off-by: Daniel Vetter Cc: Liviu Dudau Cc: Brian Starkey --- drivers/gpu/drm/arm/malidp_drv.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 02904392e370..cdb817a7c611 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -928,11 +928,10 @@ static void malidp_unbind(struct device *dev) drm_dev_unregister(drm); drm_kms_helper_poll_fini(drm); pm_runtime_get_sync(dev); - drm_crtc_vblank_off(&malidp->crtc); + drm_atomic_helper_shutdown(drm); malidp_se_irq_fini(hwdev); malidp_de_irq_fini(hwdev); drm->irq_enabled = false; - drm_atomic_helper_shutdown(drm); component_unbind_all(dev, drm); of_node_put(malidp->crtc.port); malidp->crtc.port = NULL; -- 2.26.2 From chris at chris-wilson.co.uk Tue Jun 2 09:59:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 10:59:15 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs Message-ID: <20200602095915.24792-1-chris@chris-wilson.co.uk> For reasons that be, the HW only allows usersace to read its own CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for all by adding it to the whitelists. Signed-off-by: Chris Wilson --- This probably means the change occurred in the glk/cfl timeframe... --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 94d66a9d760d..7afe5792d68c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1253,9 +1253,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* hucStatus2RegOffset */ whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), RING_FORCE_TO_NONPRIV_ACCESS_RD); + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1287,6 +1293,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) whitelist_reg(w, HIZ_CHICKEN); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 2 10:05:51 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 11:05:51 +0100 Subject: [Intel-gfx] [PATCH i-g-t 2/2] HAX:fair In-Reply-To: <20200602100551.1413463-1-chris@chris-wilson.co.uk> References: <20200602100551.1413463-1-chris@chris-wilson.co.uk> Message-ID: <20200602100551.1413463-2-chris@chris-wilson.co.uk> --- tests/intel-ci/fast-feedback.testlist | 163 +------------------------- 1 file changed, 3 insertions(+), 160 deletions(-) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index 04f6affcf..9cf460894 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -1,162 +1,5 @@ # Keep alphabetically sorted by default -igt at core_auth@basic-auth -igt at debugfs_test@read_all_entries -igt at fbdev@mmap -igt at gem_basic@bad-close -igt at gem_basic@create-close -igt at gem_basic@create-fd-close -igt at gem_busy@busy at all -igt at gem_close_race@basic-process -igt at gem_close_race@basic-threads -igt at gem_ctx_create@basic -igt at gem_ctx_create@basic-files -igt at gem_ctx_exec@basic -igt at gem_exec_basic@basic -igt at gem_exec_create@basic -igt at gem_exec_fence@basic-busy -igt at gem_exec_fence@basic-wait -igt at gem_exec_fence@basic-await -igt at gem_exec_fence@nb-await -igt at gem_exec_gttfill@basic -igt at gem_exec_parallel@engines -igt at gem_exec_store@basic -igt at gem_exec_suspend@basic-s0 -igt at gem_exec_suspend@basic-s3 -igt at gem_flink_basic@bad-flink -igt at gem_flink_basic@bad-open -igt at gem_flink_basic@basic -igt at gem_flink_basic@double-flink -igt at gem_flink_basic@flink-lifetime -igt at gem_linear_blits@basic -igt at gem_mmap@basic -igt at gem_mmap_gtt@basic -igt at gem_render_linear_blits@basic -igt at gem_render_tiled_blits@basic -igt at gem_ringfill@basic-all -igt at gem_sync@basic-all -igt at gem_sync@basic-each -igt at gem_tiled_blits@basic -igt at gem_tiled_fence_blits@basic -igt at gem_tiled_pread_basic -igt at gem_wait@busy at all -igt at gem_wait@wait at all -igt at i915_getparams_basic@basic-eu-total -igt at i915_getparams_basic@basic-subslice-total -igt at i915_hangman@error-state-basic -igt at kms_addfb_basic@addfb25-bad-modifier -igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling -igt at kms_addfb_basic@addfb25-modifier-no-flag -igt at kms_addfb_basic@addfb25-x-tiled -igt at kms_addfb_basic@addfb25-x-tiled-mismatch -igt at kms_addfb_basic@addfb25-yf-tiled -igt at kms_addfb_basic@addfb25-y-tiled -igt at kms_addfb_basic@addfb25-y-tiled-small -igt at kms_addfb_basic@bad-pitch-0 -igt at kms_addfb_basic@bad-pitch-1024 -igt at kms_addfb_basic@bad-pitch-128 -igt at kms_addfb_basic@bad-pitch-256 -igt at kms_addfb_basic@bad-pitch-32 -igt at kms_addfb_basic@bad-pitch-63 -igt at kms_addfb_basic@bad-pitch-65536 -igt at kms_addfb_basic@bad-pitch-999 -igt at kms_addfb_basic@basic -igt at kms_addfb_basic@basic-x-tiled -igt at kms_addfb_basic@basic-y-tiled -igt at kms_addfb_basic@bo-too-small -igt at kms_addfb_basic@bo-too-small-due-to-tiling -igt at kms_addfb_basic@clobberred-modifier -igt at kms_addfb_basic@framebuffer-vs-set-tiling -igt at kms_addfb_basic@invalid-get-prop -igt at kms_addfb_basic@invalid-get-prop-any -igt at kms_addfb_basic@invalid-set-prop -igt at kms_addfb_basic@invalid-set-prop-any -igt at kms_addfb_basic@no-handle -igt at kms_addfb_basic@size-max -igt at kms_addfb_basic@small-bo -igt at kms_addfb_basic@tile-pitch-mismatch -igt at kms_addfb_basic@too-high -igt at kms_addfb_basic@too-wide -igt at kms_addfb_basic@unused-handle -igt at kms_addfb_basic@unused-modifier -igt at kms_addfb_basic@unused-offsets -igt at kms_addfb_basic@unused-pitches -igt at kms_busy@basic -igt at kms_chamelium@dp-hpd-fast -igt at kms_chamelium@dp-edid-read -igt at kms_chamelium@dp-crc-fast -igt at kms_chamelium@hdmi-hpd-fast -igt at kms_chamelium@hdmi-edid-read -igt at kms_chamelium@hdmi-crc-fast -igt at kms_chamelium@vga-hpd-fast -igt at kms_chamelium@vga-edid-read -igt at kms_chamelium@common-hpd-after-suspend -igt at kms_prop_blob@basic -igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic -igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy -igt at kms_cursor_legacy@basic-flip-after-cursor-atomic -igt at kms_cursor_legacy@basic-flip-after-cursor-legacy -igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size -igt at kms_cursor_legacy@basic-flip-before-cursor-atomic -igt at kms_cursor_legacy@basic-flip-before-cursor-legacy -igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size -igt at kms_flip@basic-flip-vs-dpms -igt at kms_flip@basic-flip-vs-modeset -igt at kms_flip@basic-flip-vs-wf_vblank -igt at kms_flip@basic-plain-flip -igt at kms_force_connector_basic@force-connector-state -igt at kms_force_connector_basic@force-edid -igt at kms_force_connector_basic@force-load-detect -igt at kms_force_connector_basic@prune-stale-modes -igt at kms_frontbuffer_tracking@basic -igt at kms_pipe_crc_basic@hang-read-crc-pipe-a -igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a -igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence -igt at kms_pipe_crc_basic@read-crc-pipe-a -igt at kms_pipe_crc_basic@read-crc-pipe-b -igt at kms_pipe_crc_basic@read-crc-pipe-c -igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence -igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a -igt at kms_psr@primary_page_flip -igt at kms_psr@cursor_plane_move -igt at kms_psr@sprite_plane_onoff -igt at kms_psr@primary_mmap_gtt -igt at kms_setmode@basic-clone-single-crtc -igt at i915_pm_backlight@basic-brightness -igt at i915_pm_rpm@basic-pci-d3-state -igt at i915_pm_rpm@basic-rte -igt at i915_pm_rps@basic-api -igt at prime_self_import@basic-llseek-bad -igt at prime_self_import@basic-llseek-size -igt at prime_self_import@basic-with_fd_dup -igt at prime_self_import@basic-with_one_bo -igt at prime_self_import@basic-with_one_bo_two_files -igt at prime_self_import@basic-with_two_bos -igt at prime_vgem@basic-fence-flip -igt at prime_vgem@basic-fence-mmap -igt at prime_vgem@basic-fence-read -igt at prime_vgem@basic-gtt -igt at prime_vgem@basic-read -igt at prime_vgem@basic-write -igt at vgem_basic@setversion -igt at vgem_basic@create -igt at vgem_basic@debugfs -igt at vgem_basic@dmabuf-export -igt at vgem_basic@dmabuf-fence -igt at vgem_basic@dmabuf-fence-before -igt at vgem_basic@dmabuf-mmap -igt at vgem_basic@mmap -igt at vgem_basic@second-client -igt at vgem_basic@sysfs - -# All tests that do module unloading and reloading are executed last. -# They will sometimes reveal issues of earlier tests leaving the -# driver in a broken state that is not otherwise noticed in that test. - -igt at vgem_basic@unload -igt at i915_module_load@reload -igt at i915_pm_rpm@module-reload - -# Kernel selftests -igt at i915_selftest@live -igt at dmabuf@all +igt at gem_exec_schedule@fair-none +igt at gem_exec_schedule@fair-pace +igt at gem_exec_schedule@fair-flow -- 2.27.0.rc2 From chris at chris-wilson.co.uk Tue Jun 2 10:05:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 11:05:50 +0100 Subject: [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200602100551.1413463-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 448 +++++++++++++++++++++++++++++++++ 1 file changed, 448 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..5274e2c83 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,439 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define TIMESTAMP (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(START_TS); + + while (offset_in_page(cs) & 63) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = TIMESTAMP; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + *cs++ = MI_STORE_DWORD_IMM; + *cs++ = addr + 4064; + *cs++ = addr >> 32; + *cs++ = 0; + } + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + int timeline, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +#define F_SPARE (1 << 8) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 prev = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 ts = tslog_create(i915, ctx, e); + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + uint32_t *map; + int n; + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_FLOW) { + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, count); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + execbuf.buffers_ptr = to_user_pointer(&ts); + execbuf.batch_start_offset = 2048; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + close(execbuf.rsvd2); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); + + gem_sync(i915, ts.handle); + map = gem_mmap__device_coherent(i915, ts.handle, 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + + gem_close(i915, ts.handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 16; n <<= 1) { + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE)); + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct igt_mean m; + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + fair_child(i915, ctx, e, child_ns, + timeout, timeline, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + } + igt_waitchildren(); + close(timeline); + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + +#if 0 + /* Mean within 10% of target */ + igt_assert( 9 * igt_mean_get(&m) > 10 * frame_ns && + 10 * igt_mean_get(&m) < 9 * frame_ns); + + /* Variance [inter-quartile range] is less than 33% of median */ + igt_assert(3 * result[hi] - result[lo] < result[nchild / 2]); +#endif + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +3022,21 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACE); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_SYNC); + test_each_engine_store("fair-solo", fd, e) + fairness(fd, e, 2, F_SYNC | F_SOLO); + test_each_engine_store("fair-flow", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW); + test_each_engine_store("fair-spare", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_SPARE); + test_each_engine_store("fair-half", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_HALF); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0.rc2 From patchwork at emeril.freedesktop.org Tue Jun 2 11:14:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 11:14:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Add_Wa=5F1409371443?= In-Reply-To: <20200602014910.13019-1-aditya.swarup@intel.com> References: <20200602014910.13019-1-aditya.swarup@intel.com> Message-ID: <159109645032.21428.4820634463381266765@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Add Wa_1409371443 URL : https://patchwork.freedesktop.org/series/77892/ State : success == Summary == CI Bug Log - changes from CI_DRM_8568_full -> Patchwork_17837_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17837_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl1/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-skl10/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl4/igt at i915_suspend@fence-restore-tiled2untiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl8/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][5] -> [FAIL][6] ([i915#57]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-hsw2/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108145] / [i915#265]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109441]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-iclb7/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-a-ts-continuation-idle-hang: - shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-snb1/igt at kms_vblank@pipe-a-ts-continuation-idle-hang.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-snb6/igt at kms_vblank@pipe-a-ts-continuation-idle-hang.html * igt at kms_vblank@pipe-c-wait-idle-hang: - shard-apl: [PASS][13] -> [TIMEOUT][14] ([i915#1635]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at kms_vblank@pipe-c-wait-idle-hang.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl8/igt at kms_vblank@pipe-c-wait-idle-hang.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][15] ([i915#180]) -> [PASS][16] +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl6/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_workarounds@suspend-resume-fd: - shard-apl: [INCOMPLETE][17] -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at gem_workarounds@suspend-resume-fd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl6/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_pm_rpm@system-suspend-devices: - shard-hsw: [INCOMPLETE][19] ([i915#151] / [i915#61]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-hsw8/igt at i915_pm_rpm@system-suspend-devices.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-hsw8/igt at i915_pm_rpm@system-suspend-devices.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-apl: [FAIL][21] ([i915#70] / [i915#95]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl4/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl8/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-WARN][23] ([i915#1926]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-glk8/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * {igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1}: - shard-hsw: [INCOMPLETE][25] ([i915#61]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-hsw4/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-hsw4/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][27] ([i915#1188]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][29] ([fdo#108145] / [i915#265]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][31] ([i915#173]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb1/igt at kms_psr@no_drrs.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-iclb4/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][33] ([fdo#109441]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb5/igt at kms_psr@psr2_suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html - shard-skl: [INCOMPLETE][37] ([i915#69]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-skl8/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][39] ([i915#1542]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-hsw6/igt at perf@polling-parameterized.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-hsw1/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][41] ([i915#468]) -> [FAIL][42] ([i915#1899]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-tglb6/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][43] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][44] ([i915#1319] / [i915#1635]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl6/igt at kms_content_protection@atomic.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][45] ([i915#1319] / [i915#1635]) -> [FAIL][46] ([fdo#110321] / [fdo#110336]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at kms_content_protection@atomic-dpms.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][47] ([fdo#110321]) -> [TIMEOUT][48] ([i915#1319] / [i915#1635]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl4/igt at kms_content_protection@srm.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-WARN][49] ([i915#1926]) -> [DMESG-FAIL][50] ([i915#1925] / [i915#1926]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/shard-glk2/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8568 -> Patchwork_17837 CI-20190529: 20190529 CI_DRM_8568: 124bafc80c3ce62fc61b8eabb2657c87424b999b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17837: fe426e69f68a924170739c2e34f71a3771b37c0f @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17837/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 11:22:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 11:22:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/dsi=3A_Dont_forget_to_clean_up_the_connector_on_error_=28?= =?utf-8?q?rev3=29?= In-Reply-To: <20200507010103.16040-1-vivek.kasireddy@intel.com> References: <20200507010103.16040-1-vivek.kasireddy@intel.com> Message-ID: <159109693008.21427.10089451260181328056@emeril.freedesktop.org> == Series Details == Series: drm/i915/dsi: Dont forget to clean up the connector on error (rev3) URL : https://patchwork.freedesktop.org/series/77011/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8568_full -> Patchwork_17838_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17838_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17838_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17838_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_reloc@basic-cpu-read: - shard-skl: [PASS][1] -> [TIMEOUT][2] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl5/igt at gem_exec_reloc@basic-cpu-read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl9/igt at gem_exec_reloc@basic-cpu-read.html * igt at kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-iclb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb6/igt at kms_plane_multiple@atomic-pipe-b-tiling-none.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb1/igt at kms_plane_multiple@atomic-pipe-b-tiling-none.html Known issues ------------ Here are the changes found in Patchwork_17838_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#648] / [i915#69]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl9/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb5/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-c-wait-idle-hang: - shard-apl: [PASS][13] -> [TIMEOUT][14] ([i915#1635]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at kms_vblank@pipe-c-wait-idle-hang.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl6/igt at kms_vblank@pipe-c-wait-idle-hang.html #### Possible fixes #### * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][15] ([i915#82]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_workarounds@suspend-resume-fd: - shard-apl: [INCOMPLETE][17] -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at gem_workarounds@suspend-resume-fd.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl6/igt at gem_workarounds@suspend-resume-fd.html * {igt at kms_flip@flip-vs-suspend at a-dp1}: - shard-apl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl1/igt at kms_flip@flip-vs-suspend at a-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl7/igt at kms_flip@flip-vs-suspend at a-dp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1}: - shard-skl: [FAIL][21] ([i915#1928]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl9/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][23] ([i915#1188]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl2/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][25] ([fdo#108145] / [i915#265]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][27] ([i915#173]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb1/igt at kms_psr@no_drrs.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb8/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][29] ([fdo#109441]) -> [PASS][30] +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html - shard-skl: [INCOMPLETE][33] ([i915#69]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl10/igt at kms_vblank@pipe-a-ts-continuation-suspend.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][35] ([i915#468]) -> [FAIL][36] ([i915#1899]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-tglb3/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][37] ([i915#1319] / [i915#1635]) -> [TIMEOUT][38] ([i915#1319]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at kms_content_protection@atomic-dpms.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][39] ([fdo#110321]) -> [TIMEOUT][40] ([i915#1319] / [i915#1635]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl4/igt at kms_content_protection@srm.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl1/igt at kms_content_protection@srm.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-WARN][41] ([i915#1926]) -> [DMESG-FAIL][42] ([i915#1925] / [i915#1926]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-WARN][43] ([i915#1926]) -> [DMESG-WARN][44] ([i915#1927]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][45] ([i915#1525] / [i915#95]) -> [FAIL][46] ([i915#1525]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl6/igt at kms_fbcon_fbt@fbc.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl8/igt at kms_fbcon_fbt@fbc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8568 -> Patchwork_17838 CI-20190529: 20190529 CI_DRM_8568: 124bafc80c3ce62fc61b8eabb2657c87424b999b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17838: a30b3a0e479eb9f2f48cf8a737656c9bbb64c15a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 12:11:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 12:11:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/3=5D_drm/atomic-helper=3A_reset_v?= =?utf-8?q?blank_on_crtc_reset_=28rev2=29?= In-Reply-To: <20200602095140.36678-1-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> Message-ID: <159109989823.21427.13668097704241451725@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/atomic-helper: reset vblank on crtc reset (rev2) URL : https://patchwork.freedesktop.org/series/77908/ State : warning == Summary == $ dim checkpatch origin/drm-tip c9cd581c2623 drm/atomic-helper: reset vblank on crtc reset -:247: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 113 lines checked e80c8ed59e03 drm/malidp: Don't call drm_crtc_vblank_off on unbind -:32: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 0 errors, 1 warnings, 0 checks, 12 lines checked 011586de521b drm/hdlcd: Don't call drm_crtc_vblank_off on unbind -:15: WARNING:BAD_SIGN_OFF: Use a single space after Cc: #15: Cc: -:15: ERROR:BAD_SIGN_OFF: Unrecognized email address: '' #15: Cc: -:31: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter ' total: 1 errors, 2 warnings, 0 checks, 10 lines checked From chris at chris-wilson.co.uk Tue Jun 2 12:15:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 13:15:56 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Identify Cometlake platform Message-ID: <20200602121557.3888-1-chris@chris-wilson.co.uk> Cometlake is small refresh of Coffeelake, but since we have found out a difference in the plaforms, we need to identify the separate platforms. Since we previously took Coffeelake/Cometlake as identical, update all IS_COFFEELAKE() to also include IS_COMETLAKE(). Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_csr.c | 4 ++- drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++-- drivers/gpu/drm/i915/display/intel_hdcp.c | 7 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++---- drivers/gpu/drm/i915/gvt/display.c | 30 +++++++++++------ drivers/gpu/drm/i915/gvt/edid.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++++---- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_pci.c | 22 ++++++++++--- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_gvt.c | 2 ++ drivers/gpu/drm/i915/intel_pch.c | 36 ++++++++++++++------- drivers/gpu/drm/i915/intel_pm.c | 10 ++++-- 13 files changed, 112 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 319932b03e88..9843c9af6c13 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -707,7 +707,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) csr->fw_path = GLK_CSR_PATH; csr->required_version = GLK_CSR_VERSION_REQUIRED; csr->max_fw_size = GLK_CSR_MAX_FW_SIZE; - } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { + } else if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { csr->fw_path = KBL_CSR_PATH; csr->required_version = KBL_CSR_VERSION_REQUIRED; csr->max_fw_size = KBL_CSR_MAX_FW_SIZE; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index cd211f48c401..c8b8f96a3ae2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -752,7 +752,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) } } - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return kbl_get_buf_trans_dp(dev_priv, n_entries); else return skl_get_buf_trans_dp(dev_priv, n_entries); @@ -784,7 +786,9 @@ static const struct ddi_buf_trans * intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, enum port port, int *n_entries) { - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { const struct ddi_buf_trans *ddi_translations = kbl_get_buf_trans_dp(dev_priv, n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 2cbc4619b4ce..815b054bb167 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -1923,8 +1923,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) return false; - return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || - IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)); + return (INTEL_GEN(dev_priv) >= 10 || + IS_GEMINILAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)); } void intel_hdcp_component_init(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 94d66a9d760d..6e1accbcc045 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -361,7 +361,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, HDC_FORCE_NON_COHERENT); /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); @@ -636,7 +639,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) cnl_ctx_workarounds_init(engine, wal); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_ctx_workarounds_init(engine, wal); else if (IS_GEMINILAKE(i915)) glk_ctx_workarounds_init(engine, wal); @@ -706,7 +709,7 @@ static void gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { /* WaDisableKillLogic:bxt,skl,kbl */ - if (!IS_COFFEELAKE(i915)) + if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) wa_write_or(wal, GAM_ECOCHK, ECOCHK_DIS_TLB); @@ -969,7 +972,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) cnl_gt_workarounds_init(i915, wal); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_gt_workarounds_init(i915, wal); else if (IS_GEMINILAKE(i915)) glk_gt_workarounds_init(i915, wal); @@ -1304,7 +1307,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) icl_whitelist_build(engine); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(engine); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_whitelist_build(engine); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(engine); @@ -1515,7 +1518,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_FFSC_PERCTX_PREEMPT_CTRL); } - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ wa_write_or(wal, GEN8_GARBCNTL, diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index a1696e9ce4b6..7ba16ddfe75f 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -199,8 +199,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT); - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) { + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | SDE_PORTE_HOTPLUG_SPT); vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= @@ -314,8 +316,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; } - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) && + if ((IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) && intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; } @@ -498,8 +502,10 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) struct drm_i915_private *i915 = vgpu->gvt->gt->i915; /* TODO: add more platforms support */ - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915)) { + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { if (connected) { vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; @@ -527,8 +533,10 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) clean_virtual_dp_monitor(vgpu, PORT_D); else clean_virtual_dp_monitor(vgpu, PORT_B); @@ -551,8 +559,10 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) intel_vgpu_init_i2c_edid(vgpu); - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, resolution); else diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c index 190651df5db1..22247805c345 100644 --- a/drivers/gpu/drm/i915/gvt/edid.c +++ b/drivers/gpu/drm/i915/gvt/edid.c @@ -149,7 +149,7 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, if (IS_BROXTON(i915)) port = bxt_get_port_from_gmbus0(pin_select); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) port = cnp_get_port_from_gmbus0(pin_select); else port = get_port_from_gmbus0(pin_select); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 3e88e3b5c43a..26cae4846c82 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -59,7 +59,7 @@ unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) return D_KBL; else if (IS_BROXTON(i915)) return D_BXT; - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) return D_CFL; return 0; @@ -1435,7 +1435,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, case GEN9_PCODE_READ_MEM_LATENCY: if (IS_SKYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) || - IS_COFFEELAKE(vgpu->gvt->gt->i915)) { + IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) { /** * "Read memory latency" command on gen9. * Below memory latency values are read @@ -1460,7 +1461,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, case SKL_PCODE_CDCLK_CONTROL: if (IS_SKYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) || - IS_COFFEELAKE(vgpu->gvt->gt->i915)) + IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) *data0 = SKL_CDCLK_READY_FOR_CHANGE; break; case GEN6_PCODE_READ_RC6VIDS: @@ -1722,7 +1724,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, int ret; (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); - if (IS_COFFEELAKE(vgpu->gvt->gt->i915)) + if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); write_vreg(vgpu, offset, p_data, bytes); @@ -1731,7 +1734,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, return 0; } - if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && + if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) && data & _MASKED_BIT_ENABLE(2)) { enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); return 0; @@ -3393,7 +3397,8 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) goto err; } else if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915)) { + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { ret = init_bdw_mmio_info(gvt); if (ret) goto err; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 98f2c448cd92..3594cc384c70 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1414,6 +1414,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) +#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 7e3252fbad8e..07b09af3a9c3 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -766,6 +766,20 @@ static const struct intel_device_info cfl_gt3_info = { BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; +#define CML_PLATFORM \ + GEN9_FEATURES, \ + PLATFORM(INTEL_COMETLAKE) + +static const struct intel_device_info cml_gt1_info = { + CML_PLATFORM, + .gt = 1, +}; + +static const struct intel_device_info cml_gt2_info = { + CML_PLATFORM, + .gt = 2, +}; + #define GEN10_FEATURES \ GEN9_FEATURES, \ GEN(10), \ @@ -942,10 +956,10 @@ static const struct pci_device_id pciidlist[] = { INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), - INTEL_CML_GT1_IDS(&cfl_gt1_info), - INTEL_CML_GT2_IDS(&cfl_gt2_info), - INTEL_CML_U_GT1_IDS(&cfl_gt1_info), - INTEL_CML_U_GT2_IDS(&cfl_gt2_info), + INTEL_CML_GT1_IDS(&cml_gt1_info), + INTEL_CML_GT2_IDS(&cml_gt2_info), + INTEL_CML_U_GT1_IDS(&cml_gt1_info), + INTEL_CML_U_GT2_IDS(&cml_gt2_info), INTEL_CNL_IDS(&cnl_info), INTEL_ICL_11_IDS(&icl_info), INTEL_EHL_IDS(&ehl_info), diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index c912acd06109..3613c04904e0 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -73,6 +73,7 @@ enum intel_platform { INTEL_KABYLAKE, INTEL_GEMINILAKE, INTEL_COFFEELAKE, + INTEL_COMETLAKE, /* gen10 */ INTEL_CANNONLAKE, /* gen11 */ diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 21b91313cc5d..dd8981340d6e 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -52,6 +52,8 @@ static bool is_supported_device(struct drm_i915_private *dev_priv) return true; if (IS_COFFEELAKE(dev_priv)) return true; + if (IS_COMETLAKE(dev_priv)) + return true; return false; } diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 102b03d24f90..c668e99eb2e4 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -64,37 +64,49 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + !IS_SKYLAKE(dev_priv) && + !IS_KABYLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_SPT; case INTEL_PCH_KBP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n"); drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + !IS_SKYLAKE(dev_priv) && + !IS_KABYLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); /* KBP is SPT compatible */ return PCH_SPT; case INTEL_PCH_CNP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_CANNONLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_CNP; case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake LP PCH (CNP-LP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_CANNONLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_CNP; case INTEL_PCH_CMP_DEVICE_ID_TYPE: case INTEL_PCH_CMP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv) && + drm_WARN_ON(&dev_priv->drm, + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv) && !IS_ROCKETLAKE(dev_priv)); /* CometPoint is CNP Compatible */ return PCH_CNP; case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); /* Comet Lake V PCH is based on KBP, which is SPT compatible */ return PCH_SPT; case INTEL_PCH_ICP_DEVICE_ID_TYPE: @@ -149,7 +161,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; else if (IS_ICELAKE(dev_priv)) id = INTEL_PCH_ICP_DEVICE_ID_TYPE; - else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + else if (IS_CANNONLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) id = INTEL_PCH_CNP_DEVICE_ID_TYPE; else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) id = INTEL_PCH_SPT_DEVICE_ID_TYPE; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b134a1b9d738..26b670fa3f88 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5256,7 +5256,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, * WaIncreaseLatencyIPCEnabled: kbl,cfl * Display WA #1141: kbl,cfl */ - if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) && + if ((IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) && dev_priv->ipc_enabled) latency += 4; @@ -6822,7 +6824,9 @@ static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv) return false; /* Display WA #1141: SKL:all KBL:all CFL */ - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return dev_priv->dram_info.symmetric_memory; return true; @@ -7703,7 +7707,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = icl_init_clock_gating; else if (IS_CANNONLAKE(dev_priv)) dev_priv->display.init_clock_gating = cnl_init_clock_gating; - else if (IS_COFFEELAKE(dev_priv)) + else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) dev_priv->display.init_clock_gating = cfl_init_clock_gating; else if (IS_SKYLAKE(dev_priv)) dev_priv->display.init_clock_gating = skl_init_clock_gating; -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 2 12:15:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 13:15:57 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs In-Reply-To: <20200602121557.3888-1-chris@chris-wilson.co.uk> References: <20200602121557.3888-1-chris@chris-wilson.co.uk> Message-ID: <20200602121557.3888-2-chris@chris-wilson.co.uk> For reasons that be, the HW only allows usersace to read its own CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for all by adding it to the whitelists. v2: The change took effect from Cometlake. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6e1accbcc045..0731bbcef06c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) RING_FORCE_TO_NONPRIV_RANGE_4); } +static void cml_whitelist_build(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + + if (engine->class != RENDER_CLASS) + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); + + cfl_whitelist_build(engine); +} + static void cnl_whitelist_build(struct intel_engine_cs *engine) { struct i915_wa_list *w = &engine->whitelist; @@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* hucStatus2RegOffset */ whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), RING_FORCE_TO_NONPRIV_ACCESS_RD); + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) whitelist_reg(w, HIZ_CHICKEN); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) icl_whitelist_build(engine); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(engine); - else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) + else if (IS_COMETLAKE(i915)) + cml_whitelist_build(engine); + else if (IS_COFFEELAKE(i915)) cfl_whitelist_build(engine); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(engine); -- 2.20.1 From anshuman.gupta at intel.com Tue Jun 2 12:06:34 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Tue, 2 Jun 2020 17:36:34 +0530 Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs In-Reply-To: References: <20200601101516.21018-1-anshuman.gupta@intel.com> Message-ID: <20200602120633.GM4452@intel.com> On 2020-06-01 at 18:19:44 +0530, Shankar, Uma wrote: > > > > -----Original Message----- > > From: Intel-gfx On Behalf Of > > Anshuman Gupta > > Sent: Monday, June 1, 2020 3:45 PM > > To: intel-gfx at lists.freedesktop.org > > Cc: stable at vger.kernel.org > > Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs > > > > Gen12 hw are failing to enable lpsp configuration due to PG3 was left on due to > > valid usgae count of POWER_DOMAIN_AUDIO. > > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling a crtc, > > it should be always i915_audio_component request to get/put > > AUDIO_POWER_DOMAIN. > > > > Cc: stable at vger.kernel.org > > Cc: Ville Syrj?l? > > Cc: Maarten Lankhorst > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 6c3b11de2daf..f31a579d7a52 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct > > intel_crtc_state *crtc_state) > > mask |= BIT_ULL(intel_encoder->power_domain); > > } > > > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > > + /* > > + * Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > > + * enable AUDIO power in order to enable a crtc. > > + */ > > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && > > +crtc_state->has_audio) > > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > As part of ddi_get_config we determine has_audio using power well enabled: > pipe_config->has_audio = > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); IMO AUDIO power will also be requested by i915_audio_component get request, we can always use HDMI display without audio playback, AUDIO power should be enabled when audio driver request for it. if we get AUDIO_POWER_DOMAIN while enabling crtc PG3 will always kept on till CRTC is disabled, that is the issue required to be addressed here. This is just RFC to initiate a discussion around it. Thanks, Anshuman Gupta. > > If audio power domain is not enabled, we may end up with this as false. > Later this may get checked in intel_enable_ddi_hdmi to call audio codec enable > > if (crtc_state->has_audio) > intel_audio_codec_enable(encoder, crtc_state, conn_state); > > This may cause detection to fail. Please verify this usecase once and confirm. > > Regards, > Uma Shankar > > > if (crtc_state->shared_dpll) > > -- > > 2.26.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Tue Jun 2 12:21:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 13:21:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Identify Cometlake platform In-Reply-To: <20200602121557.3888-1-chris@chris-wilson.co.uk> References: <20200602121557.3888-1-chris@chris-wilson.co.uk> Message-ID: <20200602122121.13701-1-chris@chris-wilson.co.uk> Cometlake is small refresh of Coffeelake, but since we have found out a difference in the plaforms, we need to identify the separate platforms. Since we previously took Coffeelake/Cometlake as identical, update all IS_COFFEELAKE() to also include IS_COMETLAKE(). Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_csr.c | 4 ++- drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++------ drivers/gpu/drm/i915/display/intel_hdcp.c | 7 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++---- drivers/gpu/drm/i915/gvt/display.c | 30 +++++++++++------ drivers/gpu/drm/i915/gvt/edid.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++++---- drivers/gpu/drm/i915/i915_drv.h | 9 ++++++ drivers/gpu/drm/i915/i915_pci.c | 22 ++++++++++--- drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_gvt.c | 2 ++ drivers/gpu/drm/i915/intel_pch.c | 36 ++++++++++++++------- drivers/gpu/drm/i915/intel_pm.c | 10 ++++-- 13 files changed, 138 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 319932b03e88..9843c9af6c13 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -707,7 +707,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) csr->fw_path = GLK_CSR_PATH; csr->required_version = GLK_CSR_VERSION_REQUIRED; csr->max_fw_size = GLK_CSR_MAX_FW_SIZE; - } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { + } else if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { csr->fw_path = KBL_CSR_PATH; csr->required_version = KBL_CSR_VERSION_REQUIRED; csr->max_fw_size = KBL_CSR_MAX_FW_SIZE; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index cd211f48c401..bb8107ab5a51 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -722,10 +722,14 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) static const struct ddi_buf_trans * kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) { - if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { + if (IS_KBL_ULX(dev_priv) || + IS_CFL_ULX(dev_priv) || + IS_CML_ULX(dev_priv)) { *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); return kbl_y_ddi_translations_dp; - } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { + } else if (IS_KBL_ULT(dev_priv) || + IS_CFL_ULT(dev_priv) || + IS_CML_ULT(dev_priv)) { *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); return kbl_u_ddi_translations_dp; } else { @@ -738,12 +742,16 @@ static const struct ddi_buf_trans * skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) { if (dev_priv->vbt.edp.low_vswing) { - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || - IS_CFL_ULX(dev_priv)) { + if (IS_SKL_ULX(dev_priv) || + IS_KBL_ULX(dev_priv) || + IS_CFL_ULX(dev_priv) || + IS_CML_ULX(dev_priv)) { *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); return skl_y_ddi_translations_edp; - } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || - IS_CFL_ULT(dev_priv)) { + } else if (IS_SKL_ULT(dev_priv) || + IS_KBL_ULT(dev_priv) || + IS_CFL_ULT(dev_priv) || + IS_CML_ULT(dev_priv)) { *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); return skl_u_ddi_translations_edp; } else { @@ -752,7 +760,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) } } - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return kbl_get_buf_trans_dp(dev_priv, n_entries); else return skl_get_buf_trans_dp(dev_priv, n_entries); @@ -761,8 +771,10 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) static const struct ddi_buf_trans * skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || - IS_CFL_ULX(dev_priv)) { + if (IS_SKL_ULX(dev_priv) || + IS_KBL_ULX(dev_priv) || + IS_CFL_ULX(dev_priv) || + IS_CML_ULX(dev_priv)) { *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); return skl_y_ddi_translations_hdmi; } else { @@ -784,7 +796,9 @@ static const struct ddi_buf_trans * intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, enum port port, int *n_entries) { - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { const struct ddi_buf_trans *ddi_translations = kbl_get_buf_trans_dp(dev_priv, n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 2cbc4619b4ce..815b054bb167 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -1923,8 +1923,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) return false; - return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || - IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)); + return (INTEL_GEN(dev_priv) >= 10 || + IS_GEMINILAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)); } void intel_hdcp_component_init(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 94d66a9d760d..6e1accbcc045 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -361,7 +361,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, HDC_FORCE_NON_COHERENT); /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); @@ -636,7 +639,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) cnl_ctx_workarounds_init(engine, wal); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_ctx_workarounds_init(engine, wal); else if (IS_GEMINILAKE(i915)) glk_ctx_workarounds_init(engine, wal); @@ -706,7 +709,7 @@ static void gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { /* WaDisableKillLogic:bxt,skl,kbl */ - if (!IS_COFFEELAKE(i915)) + if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) wa_write_or(wal, GAM_ECOCHK, ECOCHK_DIS_TLB); @@ -969,7 +972,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) cnl_gt_workarounds_init(i915, wal); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_gt_workarounds_init(i915, wal); else if (IS_GEMINILAKE(i915)) glk_gt_workarounds_init(i915, wal); @@ -1304,7 +1307,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) icl_whitelist_build(engine); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(engine); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_whitelist_build(engine); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(engine); @@ -1515,7 +1518,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_FFSC_PERCTX_PREEMPT_CTRL); } - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ wa_write_or(wal, GEN8_GARBCNTL, diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index a1696e9ce4b6..7ba16ddfe75f 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -199,8 +199,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT); - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) { + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | SDE_PORTE_HOTPLUG_SPT); vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= @@ -314,8 +316,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; } - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) && + if ((IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) && intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; } @@ -498,8 +502,10 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) struct drm_i915_private *i915 = vgpu->gvt->gt->i915; /* TODO: add more platforms support */ - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915)) { + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { if (connected) { vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; @@ -527,8 +533,10 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) clean_virtual_dp_monitor(vgpu, PORT_D); else clean_virtual_dp_monitor(vgpu, PORT_B); @@ -551,8 +559,10 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) intel_vgpu_init_i2c_edid(vgpu); - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, resolution); else diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c index 190651df5db1..22247805c345 100644 --- a/drivers/gpu/drm/i915/gvt/edid.c +++ b/drivers/gpu/drm/i915/gvt/edid.c @@ -149,7 +149,7 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, if (IS_BROXTON(i915)) port = bxt_get_port_from_gmbus0(pin_select); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) port = cnp_get_port_from_gmbus0(pin_select); else port = get_port_from_gmbus0(pin_select); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 3e88e3b5c43a..26cae4846c82 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -59,7 +59,7 @@ unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) return D_KBL; else if (IS_BROXTON(i915)) return D_BXT; - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) return D_CFL; return 0; @@ -1435,7 +1435,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, case GEN9_PCODE_READ_MEM_LATENCY: if (IS_SKYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) || - IS_COFFEELAKE(vgpu->gvt->gt->i915)) { + IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) { /** * "Read memory latency" command on gen9. * Below memory latency values are read @@ -1460,7 +1461,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, case SKL_PCODE_CDCLK_CONTROL: if (IS_SKYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) || - IS_COFFEELAKE(vgpu->gvt->gt->i915)) + IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) *data0 = SKL_CDCLK_READY_FOR_CHANGE; break; case GEN6_PCODE_READ_RC6VIDS: @@ -1722,7 +1724,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, int ret; (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); - if (IS_COFFEELAKE(vgpu->gvt->gt->i915)) + if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); write_vreg(vgpu, offset, p_data, bytes); @@ -1731,7 +1734,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, return 0; } - if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && + if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) && data & _MASKED_BIT_ENABLE(2)) { enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); return 0; @@ -3393,7 +3397,8 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) goto err; } else if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915)) { + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { ret = init_bdw_mmio_info(gvt); if (ret) goto err; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 98f2c448cd92..e99255e17eb7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1414,6 +1414,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) +#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) @@ -1462,6 +1463,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, INTEL_INFO(dev_priv)->gt == 2) #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 3) + +#define IS_CML_ULT(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) +#define IS_CML_ULX(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) +#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ + INTEL_INFO(dev_priv)->gt == 2) + #define IS_CNL_WITH_PORT_F(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) #define IS_ICL_WITH_PORT_F(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 7e3252fbad8e..07b09af3a9c3 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -766,6 +766,20 @@ static const struct intel_device_info cfl_gt3_info = { BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; +#define CML_PLATFORM \ + GEN9_FEATURES, \ + PLATFORM(INTEL_COMETLAKE) + +static const struct intel_device_info cml_gt1_info = { + CML_PLATFORM, + .gt = 1, +}; + +static const struct intel_device_info cml_gt2_info = { + CML_PLATFORM, + .gt = 2, +}; + #define GEN10_FEATURES \ GEN9_FEATURES, \ GEN(10), \ @@ -942,10 +956,10 @@ static const struct pci_device_id pciidlist[] = { INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), - INTEL_CML_GT1_IDS(&cfl_gt1_info), - INTEL_CML_GT2_IDS(&cfl_gt2_info), - INTEL_CML_U_GT1_IDS(&cfl_gt1_info), - INTEL_CML_U_GT2_IDS(&cfl_gt2_info), + INTEL_CML_GT1_IDS(&cml_gt1_info), + INTEL_CML_GT2_IDS(&cml_gt2_info), + INTEL_CML_U_GT1_IDS(&cml_gt1_info), + INTEL_CML_U_GT2_IDS(&cml_gt2_info), INTEL_CNL_IDS(&cnl_info), INTEL_ICL_11_IDS(&icl_info), INTEL_EHL_IDS(&ehl_info), diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index c912acd06109..3613c04904e0 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -73,6 +73,7 @@ enum intel_platform { INTEL_KABYLAKE, INTEL_GEMINILAKE, INTEL_COFFEELAKE, + INTEL_COMETLAKE, /* gen10 */ INTEL_CANNONLAKE, /* gen11 */ diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 21b91313cc5d..dd8981340d6e 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -52,6 +52,8 @@ static bool is_supported_device(struct drm_i915_private *dev_priv) return true; if (IS_COFFEELAKE(dev_priv)) return true; + if (IS_COMETLAKE(dev_priv)) + return true; return false; } diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 102b03d24f90..c668e99eb2e4 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -64,37 +64,49 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + !IS_SKYLAKE(dev_priv) && + !IS_KABYLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_SPT; case INTEL_PCH_KBP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n"); drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + !IS_SKYLAKE(dev_priv) && + !IS_KABYLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); /* KBP is SPT compatible */ return PCH_SPT; case INTEL_PCH_CNP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_CANNONLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_CNP; case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake LP PCH (CNP-LP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_CANNONLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_CNP; case INTEL_PCH_CMP_DEVICE_ID_TYPE: case INTEL_PCH_CMP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv) && + drm_WARN_ON(&dev_priv->drm, + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv) && !IS_ROCKETLAKE(dev_priv)); /* CometPoint is CNP Compatible */ return PCH_CNP; case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); /* Comet Lake V PCH is based on KBP, which is SPT compatible */ return PCH_SPT; case INTEL_PCH_ICP_DEVICE_ID_TYPE: @@ -149,7 +161,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; else if (IS_ICELAKE(dev_priv)) id = INTEL_PCH_ICP_DEVICE_ID_TYPE; - else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + else if (IS_CANNONLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) id = INTEL_PCH_CNP_DEVICE_ID_TYPE; else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) id = INTEL_PCH_SPT_DEVICE_ID_TYPE; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b134a1b9d738..26b670fa3f88 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5256,7 +5256,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, * WaIncreaseLatencyIPCEnabled: kbl,cfl * Display WA #1141: kbl,cfl */ - if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) && + if ((IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) && dev_priv->ipc_enabled) latency += 4; @@ -6822,7 +6824,9 @@ static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv) return false; /* Display WA #1141: SKL:all KBL:all CFL */ - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return dev_priv->dram_info.symmetric_memory; return true; @@ -7703,7 +7707,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = icl_init_clock_gating; else if (IS_CANNONLAKE(dev_priv)) dev_priv->display.init_clock_gating = cnl_init_clock_gating; - else if (IS_COFFEELAKE(dev_priv)) + else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) dev_priv->display.init_clock_gating = cfl_init_clock_gating; else if (IS_SKYLAKE(dev_priv)) dev_priv->display.init_clock_gating = skl_init_clock_gating; -- 2.20.1 From hdegoede at redhat.com Tue Jun 2 12:21:30 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Tue, 2 Jun 2020 14:21:30 +0200 Subject: [Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) Message-ID: <20200602122130.45630-1-hdegoede@redhat.com> The pins on the Bay Trail SoC have separate input-buffer and output-buffer enable bits and a read of the level bit of the value register will always return the value from the input-buffer. The BIOS of a device may configure a pin in output-only mode, only enabling the output buffer, and write 1 to the level bit to drive the pin high. This 1 written to the level bit will be stored inside the data-latch of the output buffer. But a subsequent read of the value register will return 0 for the level bit because the input-buffer is disabled. This causes a read-modify-write as done by byt_gpio_set_direction() to write 0 to the level bit, driving the pin low! Before this commit byt_gpio_direction_output() relied on pinctrl_gpio_direction_output() to set the direction, followed by a call to byt_gpio_set() to apply the selected value. This causes the pin to go low between the pinctrl_gpio_direction_output() and byt_gpio_set() calls. Change byt_gpio_direction_output() to directly make the register modifications itself instead. Replacing the 2 subsequent writes to the value register with a single write. Note that the pinctrl code does not keep track internally of the direction, so not going through pinctrl_gpio_direction_output() is not an issue. This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is already on at boot (no external monitor connected), then the i915 driver does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The temporarily going low of that GPIO was causing the panel to reset itself after which it would not show an image until it was turned off and back on again (until a full modeset was done on it). This commit fixes this. Cc: stable at vger.kernel.org Signed-off-by: Hans de Goede --- Note the factoring out of the direct IRQ mode warning is deliberately not split into a separate patch to make backporting this easier. --- drivers/pinctrl/intel/pinctrl-baytrail.c | 46 +++++++++++++++++------- 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 9b821c9cbd16..83be13b83eb5 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -800,6 +800,21 @@ static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, pm_runtime_put(vg->dev); } +static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, + unsigned int offset) +{ + void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); + + /* + * Before making any direction modifications, do a check if gpio is set + * for direct IRQ. On baytrail, setting GPIO to output does not make + * sense, so let's at least inform the caller before they shoot + * themselves in the foot. + */ + if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) + dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output"); +} + static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, struct pinctrl_gpio_range *range, unsigned int offset, @@ -807,7 +822,6 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, { struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); - void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); unsigned long flags; u32 value; @@ -817,14 +831,8 @@ static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, value &= ~BYT_DIR_MASK; if (input) value |= BYT_OUTPUT_EN; - else if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) - /* - * Before making any direction modifications, do a check if gpio - * is set for direct IRQ. On baytrail, setting GPIO to output - * does not make sense, so let's at least inform the caller before - * they shoot themselves in the foot. - */ - dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output"); + else + byt_gpio_direct_irq_check(vg, offset); writel(value, val_reg); @@ -1171,13 +1179,25 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) static int byt_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - int ret = pinctrl_gpio_direction_output(chip->base + offset); + struct intel_pinctrl *vg = gpiochip_get_data(chip); + void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); + unsigned long flags; + u32 reg; - if (ret) - return ret; + raw_spin_lock_irqsave(&byt_lock, flags); - byt_gpio_set(chip, offset, value); + byt_gpio_direct_irq_check(vg, offset); + reg = readl(val_reg); + reg &= ~BYT_DIR_MASK; + if (value) + reg |= BYT_LEVEL; + else + reg &= ~BYT_LEVEL; + + writel(reg, val_reg); + + raw_spin_unlock_irqrestore(&byt_lock, flags); return 0; } -- 2.26.2 From patchwork at emeril.freedesktop.org Tue Jun 2 12:33:34 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 12:33:34 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/atomic-helper=3A_reset_vblank_o?= =?utf-8?q?n_crtc_reset_=28rev2=29?= In-Reply-To: <20200602095140.36678-1-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> Message-ID: <159110121444.21429.16545345078147195258@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/atomic-helper: reset vblank on crtc reset (rev2) URL : https://patchwork.freedesktop.org/series/77908/ State : success == Summary == CI Bug Log - changes from CI_DRM_8571 -> Patchwork_17839 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/index.html Changes ------- No changes found Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8571 -> Patchwork_17839 CI-20190529: 20190529 CI_DRM_8571: 0536dff30eff69abcf6355bdd9b9fdf45a560099 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17839: 011586de521b2df487223c8f7c1739f041bd7d07 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 011586de521b drm/hdlcd: Don't call drm_crtc_vblank_off on unbind e80c8ed59e03 drm/malidp: Don't call drm_crtc_vblank_off on unbind c9cd581c2623 drm/atomic-helper: reset vblank on crtc reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/index.html From anshuman.gupta at intel.com Tue Jun 2 12:28:07 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Tue, 2 Jun 2020 17:58:07 +0530 Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs In-Reply-To: <20200601141132.GK6112@intel.com> References: <20200601101516.21018-1-anshuman.gupta@intel.com> <20200601141132.GK6112@intel.com> Message-ID: <20200602122807.GN4452@intel.com> On 2020-06-01 at 17:11:32 +0300, Ville Syrj?l? wrote: > On Mon, Jun 01, 2020 at 03:45:16PM +0530, Anshuman Gupta wrote: > > Gen12 hw are failing to enable lpsp configuration due to PG3 was left on > > due to valid usgae count of POWER_DOMAIN_AUDIO. > > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling > > a crtc, it should be always i915_audio_component request to get/put > > AUDIO_POWER_DOMAIN. > > > > Cc: stable at vger.kernel.org > > Cc: Ville Syrj?l? > > Cc: Maarten Lankhorst > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 6c3b11de2daf..f31a579d7a52 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) > > mask |= BIT_ULL(intel_encoder->power_domain); > > } > > > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > > + /* > > + * Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > > + * enable AUDIO power in order to enable a crtc > > Nothing requires audio power to enable a crtc. What this is saying is > that if we want audio then we must enable the audio power. If you > didn't want audio then you wouldn't have .has_audio set. IMO i915_audio_component_get_power also enables audio power, and i915_audio_component_put_power releases the usage count based upon audio runtime idleness but here get_crtc_power_domains() gets the POWER_DOMAIN_AUDIO usages count, which will be released only when this crtc get disbaled. It may enable AUDIO power despite of fact that audio driver has released the usage count. Please correct me if i am wrong here. > > That said, looks like audio is moving into the always on well, but not > yet in tgl. Still some of audio functional stuff lies in PG3, not completely removed from PG3. Thanks, Anshuman Gupta. > > . > > + */ > > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && crtc_state->has_audio) > > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > > > if (crtc_state->shared_dpll) > > -- > > 2.26.2 > > -- > Ville Syrj?l? > Intel From christian.koenig at amd.com Tue Jun 2 12:47:43 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Tue, 2 Jun 2020 14:47:43 +0200 Subject: [Intel-gfx] [RFC PATCH 1/1] drm/mm: add ig_frag selftest In-Reply-To: <80a791cd-1319-795d-bd8a-1bf7dd6b9cc3@amd.com> References: <20200529163351.5228-1-nirmoy.das@amd.com> <159076753114.8851.15594151673471255964@build.alporthouse.com> <80a791cd-1319-795d-bd8a-1bf7dd6b9cc3@amd.com> Message-ID: <9cbdb0e2-5a44-5f87-df83-74c6b0c72e27@amd.com> Nirmoy please keep in mind that your current implementation doesn't fully solve the issue the test case is exercising. In other words what you have implement is fast skipping of fragmented address space for bottom-up and top-down. But what this test here exercises is the fast skipping of aligned allocations. You should probably adjust the test case a bit. Regards, Christian. Am 29.05.20 um 23:01 schrieb Nirmoy: > > On 5/29/20 5:52 PM, Chris Wilson wrote: >> Quoting Nirmoy (2020-05-29 16:40:53) >>> This works correctly most of the times but sometimes > > > I have to take my word back. In another machine,? 20k insertions in > > best mode takes 6-9 times more than 10k insertions, all most all the > time. > > evict, bottom-up and top-down modes remains in 2-5 times range. > > > If I reduce the insertions to 1k and 2k then scaling factor for best > mode stays? below 4 most of the time. > > evict, bottom-up and top-down modes remains in 2-3 times range. > > > I wonder if it makes sense to test with only 1k and 2k insertions and > tolerate more than error if the mode == best. > > Regards, > > Nirmoy > >>> >>> 20k insertions can take more than 8 times of 10k insertion time. >> The pressure is on to improve then :) >> >>> Regards, >>> >>> Nirmoy >>> >>> On 5/29/20 6:33 PM, Nirmoy Das wrote: >>>> This patch introduces fragmentation in the address range >>>> and measures time taken by 10k and 20k insertions. ig_frag() >>>> will fail if time taken by 20k insertions takes more than 4 times >>>> of 10k insertions as we know that insertions scale quadratically. >>>> Also tolerate 10% error because of kernel scheduler's jitters. >>>> >>>> Output: >>>> >>>> [ 8092.653518] drm_mm: Testing DRM range manger (struct drm_mm), >>>> with random_seed=0x9bfb4117 max_iterations=8192 max_prime=128 >>>> [ 8092.653520] drm_mm: igt_sanitycheck - ok! >>>> [ 8092.653525] igt_debug 0x0000000000000000-0x0000000000000200: >>>> 512: free >>>> [ 8092.653526] igt_debug 0x0000000000000200-0x0000000000000600: >>>> 1024: used >>>> [ 8092.653527] igt_debug 0x0000000000000600-0x0000000000000a00: >>>> 1024: free >>>> [ 8092.653528] igt_debug 0x0000000000000a00-0x0000000000000e00: >>>> 1024: used >>>> [ 8092.653529] igt_debug 0x0000000000000e00-0x0000000000001000: >>>> 512: free >>>> [ 8092.653529] igt_debug total: 4096, used 2048 free 2048 >>>> [ 8112.569813] drm_mm: best fragmented insert of 10000 and 20000 >>>> insertions took 504 and 1996 msecs >>>> [ 8112.723254] drm_mm: bottom-up fragmented insert of 10000 and >>>> 20000 insertions took 44 and 108 msecs >>>> [ 8112.813212] drm_mm: top-down fragmented insert of 10000 and >>>> 20000 insertions took 40 and 44 msecs >>>> [ 8112.847733] drm_mm: evict fragmented insert of 10000 and 20000 >>>> insertions took 8 and 20 msecs >>>> >>>> >>>> Signed-off-by: Nirmoy Das >>>> --- >>>> ?? drivers/gpu/drm/selftests/drm_mm_selftests.h |? 1 + >>>> ?? drivers/gpu/drm/selftests/test-drm_mm.c????? | 73 >>>> ++++++++++++++++++++ >>>> ?? 2 files changed, 74 insertions(+) >>>> >>>> diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>> b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>> index 6b943ea1c57d..8c87c964176b 100644 >>>> --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>> +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>> @@ -14,6 +14,7 @@ selftest(insert, igt_insert) >>>> ?? selftest(replace, igt_replace) >>>> ?? selftest(insert_range, igt_insert_range) >>>> ?? selftest(align, igt_align) >>>> +selftest(frag, igt_frag) >>>> ?? selftest(align32, igt_align32) >>>> ?? selftest(align64, igt_align64) >>>> ?? selftest(evict, igt_evict) >>>> diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c >>>> b/drivers/gpu/drm/selftests/test-drm_mm.c >>>> index 9aabe82dcd3a..05d8f3659b4d 100644 >>>> --- a/drivers/gpu/drm/selftests/test-drm_mm.c >>>> +++ b/drivers/gpu/drm/selftests/test-drm_mm.c >>>> @@ -1033,6 +1033,79 @@ static int igt_insert_range(void *ignored) >>>> ?????? return 0; >>>> ?? } >>>> ?? +static int get_insert_time(unsigned int num_insert, >>>> +??????????????????????? const struct insert_mode *mode) >>>> +{ >>>> +???? struct drm_mm mm; >>>> +???? struct drm_mm_node *nodes, *node, *next; >>>> +???? unsigned int size = 4096, align = 8192; >>>> +???? unsigned long start; >>>> +???? unsigned int i; >>>> +???? int ret = -EINVAL; >>>> + >>>> +???? drm_mm_init(&mm, 1, U64_MAX - 2); >>>> +???? nodes = vzalloc(array_size(num_insert, sizeof(*nodes))); >>>> +???? if (!nodes) >>>> +???????????? goto err; >>>> + >>>> +???? start = jiffies; >> Use ktime_t start = ktime_now(); >> >>>> +???? for (i = 0; i < num_insert; i++) { >>>> +???????????? if (!expect_insert(&mm, &nodes[i], size, align, i, >>>> mode)) { >>>> +???????????????????? pr_err("%s insert failed\n", mode->name); >>>> +???????????????????? goto out; >>>> +???????????? } >>>> +???? } >>>> + >>>> +???? ret = jiffies_to_msecs(jiffies - start); >> ret = ktime_sub(ktime_now(), start); >> >> The downside to using ktime is remembering it is s64 and so requires >> care >> and attention in doing math. >> >>>> +out: >>>> +???? drm_mm_for_each_node_safe(node, next, &mm) >>>> +???????????? drm_mm_remove_node(node); >>>> +???? drm_mm_takedown(&mm); >>>> +???? vfree(nodes); >>>> +err: >>>> +???? return ret; >>>> + >>>> +} >>>> + >>>> +static int igt_frag(void *ignored) >>>> +{ >>>> +???? const struct insert_mode *mode; >>>> +???? unsigned int insert_time1, insert_time2; >>>> +???? unsigned int insert_size = 10000; >>>> +???? unsigned int scale_factor = 4; >>>> +???? /* tolerate 10% excess insertion duration */ >>>> +???? unsigned int error_factor = 110; >>>> +???? int ret = -EINVAL; >>>> + >>>> +???? for (mode = insert_modes; mode->name; mode++) { >>>> +???????????? unsigned int expected_time; >>>> + >>>> +???????????? insert_time1 = get_insert_time(insert_size, mode); >>>> +???????????? if (insert_time1 < 0) >>>> +???????????????????? goto err; >> Ah, can you propagate the actual error. I see you are returning EINVAL >> for ENOMEM errors. Just wait until it hits and you have to debug why :) >> >>>> +???????????? insert_time2 = get_insert_time((insert_size * 2), mode); >>>> +???????????? if (insert_time2 < 0) >>>> +???????????????????? goto err; >>>> + >>>> +???????????? expected_time = (scale_factor * insert_time1 * >>>> +????????????????????????????? error_factor)/100; >>>> +???????????? if (insert_time2 > expected_time) { >>>> +???????????????????? pr_err("%s fragmented insert took more %u >>>> msecs\n", >>>> +??????????????????????????? mode->name, insert_time2 - >>>> expected_time); >>>> +???????????????????? goto err; >>>> +???????????? } >>>> + >>>> +???????????? pr_info("%s fragmented insert of %u and %u insertions >>>> took %u and %u msecs\n", >>>> +???????????????????? mode->name, insert_size, insert_size * 2, >>>> insert_time1, >>>> +???????????????????? insert_time2); >> Put the info first before the error. We always want the full details, >> with the error message explaining why it's unhappy. >> -Chris >> _______________________________________________ >> dri-devel mailing list >> dri-devel at lists.freedesktop.org >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=02%7C01%7Cnirmoy.das%40amd.com%7C5c7df129b9cf44b3ae4008d803e84445%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637263643415833767&sdata=PrCQse4nhN0ZITT9OniuHhF7A5uxJD6ehk0PMjm7WMU%3D&reserved=0 >> From liviu.dudau at arm.com Tue Jun 2 12:59:48 2020 From: liviu.dudau at arm.com (Liviu Dudau) Date: Tue, 2 Jun 2020 13:59:48 +0100 Subject: [Intel-gfx] [PATCH 2/3] drm/malidp: Don't call drm_crtc_vblank_off on unbind In-Reply-To: <20200602095140.36678-2-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> <20200602095140.36678-2-daniel.vetter@ffwll.ch> Message-ID: <20200602125948.GQ159988@e110455-lin.cambridge.arm.com> Hi Daniel, On Tue, Jun 02, 2020 at 11:51:39AM +0200, Daniel Vetter wrote: > This is already done as part of the drm_atomic_helper_shutdown(), > and in that case only for the crtc which are actually on. > I'm pretty sure that it didn't used to be the case when I wrote the code and I was hitting warnings from 84014b0a39eef6df ("drm/atomic-helper: check that drivers call drm_crtc_vblank_off"), but I'm happy that things have now been fixed. > Signed-off-by: Daniel Vetter > Cc: Liviu Dudau Acked-by: Liviu Dudau Best regards, Liviu > Cc: Brian Starkey > Cc: > --- > drivers/gpu/drm/arm/malidp_drv.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > index 02904392e370..db6ba5c78042 100644 > --- a/drivers/gpu/drm/arm/malidp_drv.c > +++ b/drivers/gpu/drm/arm/malidp_drv.c > @@ -928,7 +928,6 @@ static void malidp_unbind(struct device *dev) > drm_dev_unregister(drm); > drm_kms_helper_poll_fini(drm); > pm_runtime_get_sync(dev); > - drm_crtc_vblank_off(&malidp->crtc); > malidp_se_irq_fini(hwdev); > malidp_de_irq_fini(hwdev); > drm->irq_enabled = false; > -- > 2.26.2 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ?\_(?)_/? From liviu.dudau at arm.com Tue Jun 2 13:00:16 2020 From: liviu.dudau at arm.com (Liviu Dudau) Date: Tue, 2 Jun 2020 14:00:16 +0100 Subject: [Intel-gfx] [PATCH 3/3] drm/hdlcd: Don't call drm_crtc_vblank_off on unbind In-Reply-To: <20200602095140.36678-3-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> <20200602095140.36678-3-daniel.vetter@ffwll.ch> Message-ID: <20200602130016.GR159988@e110455-lin.cambridge.arm.com> On Tue, Jun 02, 2020 at 11:51:40AM +0200, Daniel Vetter wrote: > This is already taken care of by drm_atomic_helper_shutdown(), and > in that case only for the CRTC which are actually on. > > Only tricky bit here is that we kill the interrupt handling before we > shut down crtc, so need to reorder that. > > Signed-off-by: Daniel Vetter > Cc: Liviu Dudau Acked-by: Liviu Dudau Best regards, Liviu > Cc: Brian Starkey > Cc: > --- > drivers/gpu/drm/arm/hdlcd_drv.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c > index 194419f47c5e..26bc5d7766f5 100644 > --- a/drivers/gpu/drm/arm/hdlcd_drv.c > +++ b/drivers/gpu/drm/arm/hdlcd_drv.c > @@ -347,9 +347,8 @@ static void hdlcd_drm_unbind(struct device *dev) > of_node_put(hdlcd->crtc.port); > hdlcd->crtc.port = NULL; > pm_runtime_get_sync(dev); > - drm_crtc_vblank_off(&hdlcd->crtc); > - drm_irq_uninstall(drm); > drm_atomic_helper_shutdown(drm); > + drm_irq_uninstall(drm); > pm_runtime_put(dev); > if (pm_runtime_enabled(dev)) > pm_runtime_disable(dev); > -- > 2.26.2 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ?\_(?)_/? From patchwork at emeril.freedesktop.org Tue Jun 2 13:00:30 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 13:00:30 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Make_the_CTX=5FTIMESTAMP_readable_on_!rcs?= In-Reply-To: <20200602095915.24792-1-chris@chris-wilson.co.uk> References: <20200602095915.24792-1-chris@chris-wilson.co.uk> Message-ID: <159110283094.21428.16730310743737018716@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs URL : https://patchwork.freedesktop.org/series/77910/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8571 -> Patchwork_17840 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17840 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17840, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17840: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at workarounds: - fi-icl-y: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-y/igt at i915_selftest@live at workarounds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-icl-y/igt at i915_selftest@live at workarounds.html - fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-y/igt at i915_selftest@live at workarounds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-tgl-y/igt at i915_selftest@live at workarounds.html - fi-icl-guc: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-guc/igt at i915_selftest@live at workarounds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-icl-guc/igt at i915_selftest@live at workarounds.html - fi-icl-u2: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-u2/igt at i915_selftest@live at workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-icl-u2/igt at i915_selftest@live at workarounds.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at workarounds: - {fi-tgl-dsi}: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html - {fi-ehl-1}: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-ehl-1/igt at i915_selftest@live at workarounds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-ehl-1/igt at i915_selftest@live at workarounds.html - {fi-tgl-u}: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-u/igt at i915_selftest@live at workarounds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/fi-tgl-u/igt at i915_selftest@live at workarounds.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8571 -> Patchwork_17840 CI-20190529: 20190529 CI_DRM_8571: 0536dff30eff69abcf6355bdd9b9fdf45a560099 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17840: ecf32dcbc65f20a3c18eab819236813936a61e10 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ecf32dcbc65f drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17840/index.html From liviu.dudau at arm.com Tue Jun 2 13:02:25 2020 From: liviu.dudau at arm.com (Liviu Dudau) Date: Tue, 2 Jun 2020 14:02:25 +0100 Subject: [Intel-gfx] [PATCH] drm/malidp: Don't call drm_crtc_vblank_off on unbind In-Reply-To: <20200602095505.37509-1-daniel.vetter@ffwll.ch> References: <20200602095140.36678-2-daniel.vetter@ffwll.ch> <20200602095505.37509-1-daniel.vetter@ffwll.ch> Message-ID: <20200602130225.GS159988@e110455-lin.cambridge.arm.com> Hi Daniel, On Tue, Jun 02, 2020 at 11:55:05AM +0200, Daniel Vetter wrote: > This is already done as part of the drm_atomic_helper_shutdown(), > and in that case only for the crtc which are actually on. > > v2: I overlooked that malidp also needs to have it's interrupt shut > down reordered. Got confused by the subject not having any version of the patch, so I've acked the other one, but this is the one I've meant to Ack. So, Acked-by: Liviu Dudau Best regards, Liviu > > Signed-off-by: Daniel Vetter > Cc: Liviu Dudau > Cc: Brian Starkey > --- > drivers/gpu/drm/arm/malidp_drv.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > index 02904392e370..cdb817a7c611 100644 > --- a/drivers/gpu/drm/arm/malidp_drv.c > +++ b/drivers/gpu/drm/arm/malidp_drv.c > @@ -928,11 +928,10 @@ static void malidp_unbind(struct device *dev) > drm_dev_unregister(drm); > drm_kms_helper_poll_fini(drm); > pm_runtime_get_sync(dev); > - drm_crtc_vblank_off(&malidp->crtc); > + drm_atomic_helper_shutdown(drm); > malidp_se_irq_fini(hwdev); > malidp_de_irq_fini(hwdev); > drm->irq_enabled = false; > - drm_atomic_helper_shutdown(drm); > component_unbind_all(dev, drm); > of_node_put(malidp->crtc.port); > malidp->crtc.port = NULL; > -- > 2.26.2 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ?\_(?)_/? From uma.shankar at intel.com Tue Jun 2 13:02:44 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Tue, 2 Jun 2020 13:02:44 +0000 Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs In-Reply-To: <20200602120633.GM4452@intel.com> References: <20200601101516.21018-1-anshuman.gupta@intel.com> <20200602120633.GM4452@intel.com> Message-ID: > -----Original Message----- > From: Gupta, Anshuman > Sent: Tuesday, June 2, 2020 5:37 PM > To: Shankar, Uma > Cc: intel-gfx at lists.freedesktop.org; stable at vger.kernel.org > Subject: Re: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs > > On 2020-06-01 at 18:19:44 +0530, Shankar, Uma wrote: > > > > > > > -----Original Message----- > > > From: Intel-gfx On Behalf > > > Of Anshuman Gupta > > > Sent: Monday, June 1, 2020 3:45 PM > > > To: intel-gfx at lists.freedesktop.org > > > Cc: stable at vger.kernel.org > > > Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs > > > > > > Gen12 hw are failing to enable lpsp configuration due to PG3 was > > > left on due to valid usgae count of POWER_DOMAIN_AUDIO. > > > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling > > > a crtc, it should be always i915_audio_component request to get/put > > > AUDIO_POWER_DOMAIN. > > > > > > Cc: stable at vger.kernel.org > > > Cc: Ville Syrj?l? > > > Cc: Maarten Lankhorst > > > Signed-off-by: Anshuman Gupta > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- > > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > index 6c3b11de2daf..f31a579d7a52 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct > > > intel_crtc_state *crtc_state) > > > mask |= BIT_ULL(intel_encoder->power_domain); > > > } > > > > > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > > > + /* > > > + * Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > > > + * enable AUDIO power in order to enable a crtc. > > > + */ > > > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && > > > +crtc_state->has_audio) > > > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > > > As part of ddi_get_config we determine has_audio using power well enabled: > > pipe_config->has_audio = > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); > IMO AUDIO power will also be requested by i915_audio_component get request, > we can always use HDMI display without audio playback, AUDIO power should > be enabled when audio driver request for it. > if we get AUDIO_POWER_DOMAIN while enabling crtc PG3 will always kept on till > CRTC is disabled, that is the issue required to be addressed here. Yes HDMI can be enabled without audio, but if we want audio we will need to notify audio driver through HSW_AUD_PIN_ELD_CP_VLD and also prepare and write ELD data in hardware register. If I understand correctly this will need power and by this time audio driver would not have requested for it. Hence this will fail audio detection. > This is just RFC to initiate a discussion around it. > Thanks, > Anshuman Gupta. > > > > If audio power domain is not enabled, we may end up with this as false. > > Later this may get checked in intel_enable_ddi_hdmi to call audio > > codec enable > > > > if (crtc_state->has_audio) > > intel_audio_codec_enable(encoder, crtc_state, > > conn_state); > > > > This may cause detection to fail. Please verify this usecase once and confirm. > > > > Regards, > > Uma Shankar > > > > > if (crtc_state->shared_dpll) > > > -- > > > 2.26.2 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Tue Jun 2 13:04:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 13:04:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_drm/i915=3A_Identify_Cometlake_platfor?= =?utf-8?q?m_=28rev2=29?= In-Reply-To: <20200602121557.3888-1-chris@chris-wilson.co.uk> References: <20200602121557.3888-1-chris@chris-wilson.co.uk> Message-ID: <159110307159.21429.13752457768310694750@emeril.freedesktop.org> == Series Details == Series: series starting with drm/i915: Identify Cometlake platform (rev2) URL : https://patchwork.freedesktop.org/series/77916/ State : warning == Summary == $ dim checkpatch origin/drm-tip b57ebeadf460 drm/i915: Identify Cometlake platform -:354: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #354: FILE: drivers/gpu/drm/i915/i915_drv.h:1471: +#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ + INTEL_INFO(dev_priv)->gt == 2) -:368: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #368: FILE: drivers/gpu/drm/i915/i915_pci.c:769: +#define CML_PLATFORM \ + GEN9_FEATURES, \ + PLATFORM(INTEL_COMETLAKE) total: 1 errors, 0 warnings, 1 checks, 433 lines checked e06a98a10785 drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs From patchwork at emeril.freedesktop.org Tue Jun 2 13:05:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 13:05:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_drm/i915=3A_Identify_Cometlake_platform_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200602121557.3888-1-chris@chris-wilson.co.uk> References: <20200602121557.3888-1-chris@chris-wilson.co.uk> Message-ID: <159110314000.21429.2162559788605183802@emeril.freedesktop.org> == Series Details == Series: series starting with drm/i915: Identify Cometlake platform (rev2) URL : https://patchwork.freedesktop.org/series/77916/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Tue Jun 2 13:27:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 13:27:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_drm/i915=3A_Identify_Cometlake_platform_=28re?= =?utf-8?b?djIp?= In-Reply-To: <20200602121557.3888-1-chris@chris-wilson.co.uk> References: <20200602121557.3888-1-chris@chris-wilson.co.uk> Message-ID: <159110443809.21429.330278143866511747@emeril.freedesktop.org> == Series Details == Series: series starting with drm/i915: Identify Cometlake platform (rev2) URL : https://patchwork.freedesktop.org/series/77916/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8571 -> Patchwork_17841 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17841 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17841, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17841: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at workarounds: - fi-icl-y: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-y/igt at i915_selftest@live at workarounds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-icl-y/igt at i915_selftest@live at workarounds.html - fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-y/igt at i915_selftest@live at workarounds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-tgl-y/igt at i915_selftest@live at workarounds.html - fi-icl-guc: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-guc/igt at i915_selftest@live at workarounds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-icl-guc/igt at i915_selftest@live at workarounds.html - fi-icl-u2: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-u2/igt at i915_selftest@live at workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-icl-u2/igt at i915_selftest@live at workarounds.html * igt at runner@aborted: - fi-cml-u2: NOTRUN -> [FAIL][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-cml-u2/igt at runner@aborted.html - fi-cml-s: NOTRUN -> [FAIL][10] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-cml-s/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at workarounds: - {fi-tgl-dsi}: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html - {fi-ehl-1}: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-ehl-1/igt at i915_selftest@live at workarounds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-ehl-1/igt at i915_selftest@live at workarounds.html - {fi-tgl-u}: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-tgl-u/igt at i915_selftest@live at workarounds.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/fi-tgl-u/igt at i915_selftest@live at workarounds.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). Participating hosts (50 -> 45) ------------------------------ Additional (1): fi-kbl-7560u Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8571 -> Patchwork_17841 CI-20190529: 20190529 CI_DRM_8571: 0536dff30eff69abcf6355bdd9b9fdf45a560099 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17841: e06a98a107857728c714419a7849f41ba2c6dd11 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e06a98a10785 drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs b57ebeadf460 drm/i915: Identify Cometlake platform == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17841/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 13:53:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 13:53:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgcGlu?= =?utf-8?q?ctrl=3A_baytrail=3A_Fix_pin_being_driven_low_for_a_while_on_gpi?= =?utf-8?b?b2RfZ2V0KC4uLiwgR1BJT0RfT1VUX0hJR0gp?= In-Reply-To: <20200602122130.45630-1-hdegoede@redhat.com> References: <20200602122130.45630-1-hdegoede@redhat.com> Message-ID: <159110599865.21428.6554267277325012916@emeril.freedesktop.org> == Series Details == Series: pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) URL : https://patchwork.freedesktop.org/series/77917/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8571 -> Patchwork_17842 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17842 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17842, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17842/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17842: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - fi-icl-y: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-y/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17842/fi-icl-y/igt at i915_selftest@live at execlists.html Known issues ------------ Here are the changes found in Patchwork_17842 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#262]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17842/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 Participating hosts (50 -> 45) ------------------------------ Additional (1): fi-kbl-7560u Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8571 -> Patchwork_17842 CI-20190529: 20190529 CI_DRM_8571: 0536dff30eff69abcf6355bdd9b9fdf45a560099 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17842: 3632b22bc93f0e4441d082dfeebfaaf05976684c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3632b22bc93f pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17842/index.html From joonas.lahtinen at linux.intel.com Tue Jun 2 14:04:38 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Tue, 02 Jun 2020 17:04:38 +0300 Subject: [Intel-gfx] [PULL] gvt-next-fixes In-Reply-To: <20200528033559.GG23961@zhen-hp.sh.intel.com> References: <20200528033559.GG23961@zhen-hp.sh.intel.com> Message-ID: <159110667839.24106.18398193602690473504@jlahtine-desk.ger.corp.intel.com> Quoting Zhenyu Wang (2020-05-28 06:35:59) > > Hi, > > Here's two queued warning fixes for gvt-next. One is for clang warning > on debug only function and another one from coccicheck to use ARRAY_SIZE. Pulled now, thanks for the PR. Regards, Joonas > > Thanks > -- > The following changes since commit 3a36aa237e4ed04553c0998cf5f47eda3e206e4f: > > drm/i915: Update DRIVER_DATE to 20200515 (2020-05-15 14:49:24 +0300) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux tags/gvt-next-fixes-2020-05-28 > > for you to fetch changes up to cb7ee52284a244fd14caec73df0d49e02891aac4: > > drm/i915/gvt: Use ARRAY_SIZE for vgpu_types (2020-05-19 17:18:50 +0800) > > ---------------------------------------------------------------- > gvt-next-fixes-2020-05-28 > > - Fix one clang warning on debug only function (Nathan) > - Use ARRAY_SIZE for coccicheck warn (Aishwarya) > > ---------------------------------------------------------------- > Aishwarya Ramakrishnan (1): > drm/i915/gvt: Use ARRAY_SIZE for vgpu_types > > Nathan Chancellor (1): > drm/i915: Mark check_shadow_context_ppgtt as maybe unused > > drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- > drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > > -- > Open Source Technology Center, Intel ltd. > > $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 From chris at chris-wilson.co.uk Tue Jun 2 14:05:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 15:05:41 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <20200602140541.5481-2-chris@chris-wilson.co.uk> For reasons that be, the HW only allows usersace to read its own CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for all by adding it to the whitelists. v2: The change took effect from Cometlake. v3: Ignore timestamps that autoincrement when validating the whitelist Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++- .../gpu/drm/i915/gt/selftest_workarounds.c | 16 ++++++++++++ 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6e1accbcc045..0731bbcef06c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) RING_FORCE_TO_NONPRIV_RANGE_4); } +static void cml_whitelist_build(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + + if (engine->class != RENDER_CLASS) + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); + + cfl_whitelist_build(engine); +} + static void cnl_whitelist_build(struct intel_engine_cs *engine) { struct i915_wa_list *w = &engine->whitelist; @@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* hucStatus2RegOffset */ whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), RING_FORCE_TO_NONPRIV_ACCESS_RD); + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) whitelist_reg(w, HIZ_CHICKEN); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) icl_whitelist_build(engine); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(engine); - else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) + else if (IS_COMETLAKE(i915)) + cml_whitelist_build(engine); + else if (IS_COFFEELAKE(i915)) cfl_whitelist_build(engine); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(engine); diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 32785463ec9e..e61af5bcf1c6 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -417,6 +417,19 @@ static bool wo_register(struct intel_engine_cs *engine, u32 reg) return false; } +static bool timestamp(const struct intel_engine_cs *engine, u32 reg) +{ + switch (reg - engine->mmio_base) { + case 0x358: + case 0x35c: + case 0x3a8: + return true; + + default: + return false; + } +} + static bool ro_register(u32 reg) { if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == @@ -497,6 +510,9 @@ static int check_dirty_whitelist(struct intel_context *ce) if (wo_register(engine, reg)) continue; + if (timestamp(engine, reg)) + continue; /* timestamps are expected to autoincrement */ + ro_reg = ro_register(reg); /* Clear non priv flags */ -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 2 14:05:40 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 15:05:40 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Identify Cometlake platform Message-ID: <20200602140541.5481-1-chris@chris-wilson.co.uk> Cometlake is small refresh of Coffeelake, but since we have found out a difference in the plaforms, we need to identify the separate platforms. Since we previously took Coffeelake/Cometlake as identical, update all IS_COFFEELAKE() to also include IS_COMETLAKE(). Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/display/intel_csr.c | 4 ++- drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++------ drivers/gpu/drm/i915/display/intel_hdcp.c | 7 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++---- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- drivers/gpu/drm/i915/gvt/display.c | 30 +++++++++++------ drivers/gpu/drm/i915/gvt/edid.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++++---- drivers/gpu/drm/i915/i915_drv.h | 9 ++++++ drivers/gpu/drm/i915/i915_pci.c | 22 ++++++++++--- drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_gvt.c | 2 ++ drivers/gpu/drm/i915/intel_pch.c | 36 ++++++++++++++------- drivers/gpu/drm/i915/intel_pm.c | 10 ++++-- 15 files changed, 140 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 319932b03e88..9843c9af6c13 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -707,7 +707,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) csr->fw_path = GLK_CSR_PATH; csr->required_version = GLK_CSR_VERSION_REQUIRED; csr->max_fw_size = GLK_CSR_MAX_FW_SIZE; - } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { + } else if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { csr->fw_path = KBL_CSR_PATH; csr->required_version = KBL_CSR_VERSION_REQUIRED; csr->max_fw_size = KBL_CSR_MAX_FW_SIZE; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index cd211f48c401..bb8107ab5a51 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -722,10 +722,14 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) static const struct ddi_buf_trans * kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) { - if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { + if (IS_KBL_ULX(dev_priv) || + IS_CFL_ULX(dev_priv) || + IS_CML_ULX(dev_priv)) { *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); return kbl_y_ddi_translations_dp; - } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { + } else if (IS_KBL_ULT(dev_priv) || + IS_CFL_ULT(dev_priv) || + IS_CML_ULT(dev_priv)) { *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); return kbl_u_ddi_translations_dp; } else { @@ -738,12 +742,16 @@ static const struct ddi_buf_trans * skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) { if (dev_priv->vbt.edp.low_vswing) { - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || - IS_CFL_ULX(dev_priv)) { + if (IS_SKL_ULX(dev_priv) || + IS_KBL_ULX(dev_priv) || + IS_CFL_ULX(dev_priv) || + IS_CML_ULX(dev_priv)) { *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); return skl_y_ddi_translations_edp; - } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || - IS_CFL_ULT(dev_priv)) { + } else if (IS_SKL_ULT(dev_priv) || + IS_KBL_ULT(dev_priv) || + IS_CFL_ULT(dev_priv) || + IS_CML_ULT(dev_priv)) { *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); return skl_u_ddi_translations_edp; } else { @@ -752,7 +760,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) } } - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return kbl_get_buf_trans_dp(dev_priv, n_entries); else return skl_get_buf_trans_dp(dev_priv, n_entries); @@ -761,8 +771,10 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) static const struct ddi_buf_trans * skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || - IS_CFL_ULX(dev_priv)) { + if (IS_SKL_ULX(dev_priv) || + IS_KBL_ULX(dev_priv) || + IS_CFL_ULX(dev_priv) || + IS_CML_ULX(dev_priv)) { *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); return skl_y_ddi_translations_hdmi; } else { @@ -784,7 +796,9 @@ static const struct ddi_buf_trans * intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, enum port port, int *n_entries) { - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { const struct ddi_buf_trans *ddi_translations = kbl_get_buf_trans_dp(dev_priv, n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 2cbc4619b4ce..815b054bb167 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -1923,8 +1923,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) return false; - return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || - IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)); + return (INTEL_GEN(dev_priv) >= 10 || + IS_GEMINILAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)); } void intel_hdcp_component_init(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 94d66a9d760d..6e1accbcc045 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -361,7 +361,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, HDC_FORCE_NON_COHERENT); /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, GEN8_SAMPLER_POWER_BYPASS_DIS); @@ -636,7 +639,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) cnl_ctx_workarounds_init(engine, wal); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_ctx_workarounds_init(engine, wal); else if (IS_GEMINILAKE(i915)) glk_ctx_workarounds_init(engine, wal); @@ -706,7 +709,7 @@ static void gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { /* WaDisableKillLogic:bxt,skl,kbl */ - if (!IS_COFFEELAKE(i915)) + if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) wa_write_or(wal, GAM_ECOCHK, ECOCHK_DIS_TLB); @@ -969,7 +972,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) cnl_gt_workarounds_init(i915, wal); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_gt_workarounds_init(i915, wal); else if (IS_GEMINILAKE(i915)) glk_gt_workarounds_init(i915, wal); @@ -1304,7 +1307,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) icl_whitelist_build(engine); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(engine); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) cfl_whitelist_build(engine); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(engine); @@ -1515,7 +1518,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_FFSC_PERCTX_PREEMPT_CTRL); } - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ wa_write_or(wal, GEN8_GARBCNTL, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 9b6218128d09..e75be3999358 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -55,7 +55,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ - fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ + fw_def(COMETLAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index a1696e9ce4b6..7ba16ddfe75f 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -199,8 +199,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT); - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) { + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) { vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | SDE_PORTE_HOTPLUG_SPT); vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= @@ -314,8 +316,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; } - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) && + if ((IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) && intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; } @@ -498,8 +502,10 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) struct drm_i915_private *i915 = vgpu->gvt->gt->i915; /* TODO: add more platforms support */ - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915)) { + if (IS_SKYLAKE(i915) || + IS_KABYLAKE(i915) || + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { if (connected) { vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; @@ -527,8 +533,10 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) clean_virtual_dp_monitor(vgpu, PORT_D); else clean_virtual_dp_monitor(vgpu, PORT_B); @@ -551,8 +559,10 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) intel_vgpu_init_i2c_edid(vgpu); - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_COFFEELAKE(dev_priv)) + if (IS_SKYLAKE(dev_priv) || + IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, resolution); else diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c index 190651df5db1..22247805c345 100644 --- a/drivers/gpu/drm/i915/gvt/edid.c +++ b/drivers/gpu/drm/i915/gvt/edid.c @@ -149,7 +149,7 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, if (IS_BROXTON(i915)) port = bxt_get_port_from_gmbus0(pin_select); - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) port = cnp_get_port_from_gmbus0(pin_select); else port = get_port_from_gmbus0(pin_select); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 3e88e3b5c43a..26cae4846c82 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -59,7 +59,7 @@ unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) return D_KBL; else if (IS_BROXTON(i915)) return D_BXT; - else if (IS_COFFEELAKE(i915)) + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) return D_CFL; return 0; @@ -1435,7 +1435,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, case GEN9_PCODE_READ_MEM_LATENCY: if (IS_SKYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) || - IS_COFFEELAKE(vgpu->gvt->gt->i915)) { + IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) { /** * "Read memory latency" command on gen9. * Below memory latency values are read @@ -1460,7 +1461,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, case SKL_PCODE_CDCLK_CONTROL: if (IS_SKYLAKE(vgpu->gvt->gt->i915) || IS_KABYLAKE(vgpu->gvt->gt->i915) || - IS_COFFEELAKE(vgpu->gvt->gt->i915)) + IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) *data0 = SKL_CDCLK_READY_FOR_CHANGE; break; case GEN6_PCODE_READ_RC6VIDS: @@ -1722,7 +1724,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, int ret; (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); - if (IS_COFFEELAKE(vgpu->gvt->gt->i915)) + if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); write_vreg(vgpu, offset, p_data, bytes); @@ -1731,7 +1734,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, return 0; } - if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && + if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) && data & _MASKED_BIT_ENABLE(2)) { enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); return 0; @@ -3393,7 +3397,8 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) goto err; } else if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915)) { + IS_COFFEELAKE(i915) || + IS_COMETLAKE(i915)) { ret = init_bdw_mmio_info(gvt); if (ret) goto err; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 98f2c448cd92..e99255e17eb7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1414,6 +1414,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) +#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) @@ -1462,6 +1463,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, INTEL_INFO(dev_priv)->gt == 2) #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 3) + +#define IS_CML_ULT(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) +#define IS_CML_ULX(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) +#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ + INTEL_INFO(dev_priv)->gt == 2) + #define IS_CNL_WITH_PORT_F(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) #define IS_ICL_WITH_PORT_F(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 7e3252fbad8e..07b09af3a9c3 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -766,6 +766,20 @@ static const struct intel_device_info cfl_gt3_info = { BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; +#define CML_PLATFORM \ + GEN9_FEATURES, \ + PLATFORM(INTEL_COMETLAKE) + +static const struct intel_device_info cml_gt1_info = { + CML_PLATFORM, + .gt = 1, +}; + +static const struct intel_device_info cml_gt2_info = { + CML_PLATFORM, + .gt = 2, +}; + #define GEN10_FEATURES \ GEN9_FEATURES, \ GEN(10), \ @@ -942,10 +956,10 @@ static const struct pci_device_id pciidlist[] = { INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), - INTEL_CML_GT1_IDS(&cfl_gt1_info), - INTEL_CML_GT2_IDS(&cfl_gt2_info), - INTEL_CML_U_GT1_IDS(&cfl_gt1_info), - INTEL_CML_U_GT2_IDS(&cfl_gt2_info), + INTEL_CML_GT1_IDS(&cml_gt1_info), + INTEL_CML_GT2_IDS(&cml_gt2_info), + INTEL_CML_U_GT1_IDS(&cml_gt1_info), + INTEL_CML_U_GT2_IDS(&cml_gt2_info), INTEL_CNL_IDS(&cnl_info), INTEL_ICL_11_IDS(&icl_info), INTEL_EHL_IDS(&ehl_info), diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index c245c10c9bee..544ac61fbc36 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -57,6 +57,7 @@ static const char * const platform_names[] = { PLATFORM_NAME(KABYLAKE), PLATFORM_NAME(GEMINILAKE), PLATFORM_NAME(COFFEELAKE), + PLATFORM_NAME(COMETLAKE), PLATFORM_NAME(CANNONLAKE), PLATFORM_NAME(ICELAKE), PLATFORM_NAME(ELKHARTLAKE), diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index c912acd06109..3613c04904e0 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -73,6 +73,7 @@ enum intel_platform { INTEL_KABYLAKE, INTEL_GEMINILAKE, INTEL_COFFEELAKE, + INTEL_COMETLAKE, /* gen10 */ INTEL_CANNONLAKE, /* gen11 */ diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 21b91313cc5d..dd8981340d6e 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -52,6 +52,8 @@ static bool is_supported_device(struct drm_i915_private *dev_priv) return true; if (IS_COFFEELAKE(dev_priv)) return true; + if (IS_COMETLAKE(dev_priv)) + return true; return false; } diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index 102b03d24f90..c668e99eb2e4 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -64,37 +64,49 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + !IS_SKYLAKE(dev_priv) && + !IS_KABYLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_SPT; case INTEL_PCH_KBP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n"); drm_WARN_ON(&dev_priv->drm, - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + !IS_SKYLAKE(dev_priv) && + !IS_KABYLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); /* KBP is SPT compatible */ return PCH_SPT; case INTEL_PCH_CNP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_CANNONLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_CNP; case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake LP PCH (CNP-LP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && - !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_CANNONLAKE(dev_priv) && + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); return PCH_CNP; case INTEL_PCH_CMP_DEVICE_ID_TYPE: case INTEL_PCH_CMP2_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv) && + drm_WARN_ON(&dev_priv->drm, + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv) && !IS_ROCKETLAKE(dev_priv)); /* CometPoint is CNP Compatible */ return PCH_CNP; case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n"); - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, + !IS_COFFEELAKE(dev_priv) && + !IS_COMETLAKE(dev_priv)); /* Comet Lake V PCH is based on KBP, which is SPT compatible */ return PCH_SPT; case INTEL_PCH_ICP_DEVICE_ID_TYPE: @@ -149,7 +161,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) id = INTEL_PCH_MCC_DEVICE_ID_TYPE; else if (IS_ICELAKE(dev_priv)) id = INTEL_PCH_ICP_DEVICE_ID_TYPE; - else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + else if (IS_CANNONLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) id = INTEL_PCH_CNP_DEVICE_ID_TYPE; else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) id = INTEL_PCH_SPT_DEVICE_ID_TYPE; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b134a1b9d738..26b670fa3f88 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5256,7 +5256,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, * WaIncreaseLatencyIPCEnabled: kbl,cfl * Display WA #1141: kbl,cfl */ - if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) && + if ((IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) && dev_priv->ipc_enabled) latency += 4; @@ -6822,7 +6824,9 @@ static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv) return false; /* Display WA #1141: SKL:all KBL:all CFL */ - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) + if (IS_KABYLAKE(dev_priv) || + IS_COFFEELAKE(dev_priv) || + IS_COMETLAKE(dev_priv)) return dev_priv->dram_info.symmetric_memory; return true; @@ -7703,7 +7707,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = icl_init_clock_gating; else if (IS_CANNONLAKE(dev_priv)) dev_priv->display.init_clock_gating = cnl_init_clock_gating; - else if (IS_COFFEELAKE(dev_priv)) + else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) dev_priv->display.init_clock_gating = cfl_init_clock_gating; else if (IS_SKYLAKE(dev_priv)) dev_priv->display.init_clock_gating = skl_init_clock_gating; -- 2.20.1 From christian.koenig at amd.com Tue Jun 2 14:25:02 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Tue, 2 Jun 2020 16:25:02 +0200 Subject: [Intel-gfx] [RFC PATCH 1/1] drm/mm: add ig_frag selftest In-Reply-To: <6b2d0137-8b7c-2dd0-b49f-1bf6bb300c06@amd.com> References: <20200529163351.5228-1-nirmoy.das@amd.com> <159076753114.8851.15594151673471255964@build.alporthouse.com> <80a791cd-1319-795d-bd8a-1bf7dd6b9cc3@amd.com> <9cbdb0e2-5a44-5f87-df83-74c6b0c72e27@amd.com> <6b2d0137-8b7c-2dd0-b49f-1bf6bb300c06@amd.com> Message-ID: Am 02.06.20 um 16:13 schrieb Nirmoy: > Hi Christian, > > On 6/2/20 2:47 PM, Christian K?nig wrote: >> Nirmoy please keep in mind that your current implementation doesn't >> fully solve the issue the test case is exercising. >> >> In other words what you have implement is fast skipping of fragmented >> address space for bottom-up and top-down. >> >> But what this test here exercises is the fast skipping of aligned >> allocations. You should probably adjust the test case a bit. > > > Allocations with size=4k and aign = 8k is known to introduce > fragmentation, Yes, but this fragmentation can't be avoided with what we already implemented. For this we would need the extension with the alignment I already explained. > do you mean I should only test bottom-up and top-down > > for now ? Yes and no. What we need to test is the following: 1. Make tons of allocations with size=4k and align=0. 2. Free every other of those allocations. 3. Make tons of allocations with size=8k and align=0. Previously bottom-up and top-down would have checked all the holes created in step #2. With your change they can immediately see that this doesn't make sense and shortcut to the leftmost/rightmost leaf node in the tree with the large free block. That we can handle the alignment as well is the next step of that. Regards, Christian. > > > Regards, > > Nirmoy > > >> >> >> Regards, >> Christian. >> >> Am 29.05.20 um 23:01 schrieb Nirmoy: >>> >>> On 5/29/20 5:52 PM, Chris Wilson wrote: >>>> Quoting Nirmoy (2020-05-29 16:40:53) >>>>> This works correctly most of the times but sometimes >>> >>> >>> I have to take my word back. In another machine,? 20k insertions in >>> >>> best mode takes 6-9 times more than 10k insertions, all most all the >>> time. >>> >>> evict, bottom-up and top-down modes remains in 2-5 times range. >>> >>> >>> If I reduce the insertions to 1k and 2k then scaling factor for best >>> mode stays? below 4 most of the time. >>> >>> evict, bottom-up and top-down modes remains in 2-3 times range. >>> >>> >>> I wonder if it makes sense to test with only 1k and 2k insertions >>> and tolerate more than error if the mode == best. >>> >>> Regards, >>> >>> Nirmoy >>> >>>>> >>>>> 20k insertions can take more than 8 times of 10k insertion time. >>>> The pressure is on to improve then :) >>>> >>>>> Regards, >>>>> >>>>> Nirmoy >>>>> >>>>> On 5/29/20 6:33 PM, Nirmoy Das wrote: >>>>>> This patch introduces fragmentation in the address range >>>>>> and measures time taken by 10k and 20k insertions. ig_frag() >>>>>> will fail if time taken by 20k insertions takes more than 4 times >>>>>> of 10k insertions as we know that insertions scale quadratically. >>>>>> Also tolerate 10% error because of kernel scheduler's jitters. >>>>>> >>>>>> Output: >>>>>> >>>>>> [ 8092.653518] drm_mm: Testing DRM range manger (struct drm_mm), >>>>>> with random_seed=0x9bfb4117 max_iterations=8192 max_prime=128 >>>>>> [ 8092.653520] drm_mm: igt_sanitycheck - ok! >>>>>> [ 8092.653525] igt_debug 0x0000000000000000-0x0000000000000200: >>>>>> 512: free >>>>>> [ 8092.653526] igt_debug 0x0000000000000200-0x0000000000000600: >>>>>> 1024: used >>>>>> [ 8092.653527] igt_debug 0x0000000000000600-0x0000000000000a00: >>>>>> 1024: free >>>>>> [ 8092.653528] igt_debug 0x0000000000000a00-0x0000000000000e00: >>>>>> 1024: used >>>>>> [ 8092.653529] igt_debug 0x0000000000000e00-0x0000000000001000: >>>>>> 512: free >>>>>> [ 8092.653529] igt_debug total: 4096, used 2048 free 2048 >>>>>> [ 8112.569813] drm_mm: best fragmented insert of 10000 and 20000 >>>>>> insertions took 504 and 1996 msecs >>>>>> [ 8112.723254] drm_mm: bottom-up fragmented insert of 10000 and >>>>>> 20000 insertions took 44 and 108 msecs >>>>>> [ 8112.813212] drm_mm: top-down fragmented insert of 10000 and >>>>>> 20000 insertions took 40 and 44 msecs >>>>>> [ 8112.847733] drm_mm: evict fragmented insert of 10000 and 20000 >>>>>> insertions took 8 and 20 msecs >>>>>> >>>>>> >>>>>> Signed-off-by: Nirmoy Das >>>>>> --- >>>>>> ?? drivers/gpu/drm/selftests/drm_mm_selftests.h |? 1 + >>>>>> ?? drivers/gpu/drm/selftests/test-drm_mm.c????? | 73 >>>>>> ++++++++++++++++++++ >>>>>> ?? 2 files changed, 74 insertions(+) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>> b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>> index 6b943ea1c57d..8c87c964176b 100644 >>>>>> --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>> +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>> @@ -14,6 +14,7 @@ selftest(insert, igt_insert) >>>>>> ?? selftest(replace, igt_replace) >>>>>> ?? selftest(insert_range, igt_insert_range) >>>>>> ?? selftest(align, igt_align) >>>>>> +selftest(frag, igt_frag) >>>>>> ?? selftest(align32, igt_align32) >>>>>> ?? selftest(align64, igt_align64) >>>>>> ?? selftest(evict, igt_evict) >>>>>> diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>> b/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>> index 9aabe82dcd3a..05d8f3659b4d 100644 >>>>>> --- a/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>> +++ b/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>> @@ -1033,6 +1033,79 @@ static int igt_insert_range(void *ignored) >>>>>> ?????? return 0; >>>>>> ?? } >>>>>> ?? +static int get_insert_time(unsigned int num_insert, >>>>>> +??????????????????????? const struct insert_mode *mode) >>>>>> +{ >>>>>> +???? struct drm_mm mm; >>>>>> +???? struct drm_mm_node *nodes, *node, *next; >>>>>> +???? unsigned int size = 4096, align = 8192; >>>>>> +???? unsigned long start; >>>>>> +???? unsigned int i; >>>>>> +???? int ret = -EINVAL; >>>>>> + >>>>>> +???? drm_mm_init(&mm, 1, U64_MAX - 2); >>>>>> +???? nodes = vzalloc(array_size(num_insert, sizeof(*nodes))); >>>>>> +???? if (!nodes) >>>>>> +???????????? goto err; >>>>>> + >>>>>> +???? start = jiffies; >>>> Use ktime_t start = ktime_now(); >>>> >>>>>> +???? for (i = 0; i < num_insert; i++) { >>>>>> +???????????? if (!expect_insert(&mm, &nodes[i], size, align, i, >>>>>> mode)) { >>>>>> +???????????????????? pr_err("%s insert failed\n", mode->name); >>>>>> +???????????????????? goto out; >>>>>> +???????????? } >>>>>> +???? } >>>>>> + >>>>>> +???? ret = jiffies_to_msecs(jiffies - start); >>>> ret = ktime_sub(ktime_now(), start); >>>> >>>> The downside to using ktime is remembering it is s64 and so >>>> requires care >>>> and attention in doing math. >>>> >>>>>> +out: >>>>>> +???? drm_mm_for_each_node_safe(node, next, &mm) >>>>>> +???????????? drm_mm_remove_node(node); >>>>>> +???? drm_mm_takedown(&mm); >>>>>> +???? vfree(nodes); >>>>>> +err: >>>>>> +???? return ret; >>>>>> + >>>>>> +} >>>>>> + >>>>>> +static int igt_frag(void *ignored) >>>>>> +{ >>>>>> +???? const struct insert_mode *mode; >>>>>> +???? unsigned int insert_time1, insert_time2; >>>>>> +???? unsigned int insert_size = 10000; >>>>>> +???? unsigned int scale_factor = 4; >>>>>> +???? /* tolerate 10% excess insertion duration */ >>>>>> +???? unsigned int error_factor = 110; >>>>>> +???? int ret = -EINVAL; >>>>>> + >>>>>> +???? for (mode = insert_modes; mode->name; mode++) { >>>>>> +???????????? unsigned int expected_time; >>>>>> + >>>>>> +???????????? insert_time1 = get_insert_time(insert_size, mode); >>>>>> +???????????? if (insert_time1 < 0) >>>>>> +???????????????????? goto err; >>>> Ah, can you propagate the actual error. I see you are returning EINVAL >>>> for ENOMEM errors. Just wait until it hits and you have to debug >>>> why :) >>>> >>>>>> +???????????? insert_time2 = get_insert_time((insert_size * 2), >>>>>> mode); >>>>>> +???????????? if (insert_time2 < 0) >>>>>> +???????????????????? goto err; >>>>>> + >>>>>> +???????????? expected_time = (scale_factor * insert_time1 * >>>>>> +????????????????????????????? error_factor)/100; >>>>>> +???????????? if (insert_time2 > expected_time) { >>>>>> +???????????????????? pr_err("%s fragmented insert took more %u >>>>>> msecs\n", >>>>>> +??????????????????????????? mode->name, insert_time2 - >>>>>> expected_time); >>>>>> +???????????????????? goto err; >>>>>> +???????????? } >>>>>> + >>>>>> +???????????? pr_info("%s fragmented insert of %u and %u >>>>>> insertions took %u and %u msecs\n", >>>>>> +???????????????????? mode->name, insert_size, insert_size * 2, >>>>>> insert_time1, >>>>>> +???????????????????? insert_time2); >>>> Put the info first before the error. We always want the full details, >>>> with the error message explaining why it's unhappy. >>>> -Chris >>>> _______________________________________________ >>>> dri-devel mailing list >>>> dri-devel at lists.freedesktop.org >>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=02%7C01%7Cnirmoy.das%40amd.com%7C5c7df129b9cf44b3ae4008d803e84445%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637263643415833767&sdata=PrCQse4nhN0ZITT9OniuHhF7A5uxJD6ehk0PMjm7WMU%3D&reserved=0 >>>> >> From patchwork at emeril.freedesktop.org Tue Jun 2 15:08:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 15:08:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/2=5D_drm/i915=3A_Identify_Cometla?= =?utf-8?q?ke_platform?= In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <159111049800.21429.5192006753433775744@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Identify Cometlake platform URL : https://patchwork.freedesktop.org/series/77922/ State : warning == Summary == $ dim checkpatch origin/drm-tip cb7a71f01dd4 drm/i915: Identify Cometlake platform -:367: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #367: FILE: drivers/gpu/drm/i915/i915_drv.h:1471: +#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ + INTEL_INFO(dev_priv)->gt == 2) -:381: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #381: FILE: drivers/gpu/drm/i915/i915_pci.c:769: +#define CML_PLATFORM \ + GEN9_FEATURES, \ + PLATFORM(INTEL_COMETLAKE) total: 1 errors, 0 warnings, 1 checks, 448 lines checked fd76a0e5a47e drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs From patchwork at emeril.freedesktop.org Tue Jun 2 15:09:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 15:09:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/2=5D_drm/i915=3A_Identify_Cometlake_p?= =?utf-8?q?latform?= In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <159111056545.21427.2670011003206128968@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Identify Cometlake platform URL : https://patchwork.freedesktop.org/series/77922/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From jani.nikula at intel.com Tue Jun 2 15:11:26 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Tue, 2 Jun 2020 18:11:26 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/params: fix i915.reset module param type Message-ID: <20200602151126.25626-1-jani.nikula@intel.com> The reset member in i915_params was previously changed to unsigned, but this failed to change the actual module parameter. Fixes: aae970d8454b ("drm/i915: Mark i915.reset as unsigned") Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index ace44ad7e6df..fd3b14caf4ce 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -74,7 +74,7 @@ i915_param_named_unsafe(vbt_sdvo_panel_type, int, 0400, "Override/Ignore selection of SDVO panel mode in the VBT " "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); -i915_param_named_unsafe(reset, int, 0400, +i915_param_named_unsafe(reset, uint, 0400, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); i915_param_named_unsafe(vbt_firmware, charp, 0400, -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 2 15:16:43 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 02 Jun 2020 16:16:43 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/params: fix i915.reset module param type In-Reply-To: <20200602151126.25626-1-jani.nikula@intel.com> References: <20200602151126.25626-1-jani.nikula@intel.com> Message-ID: <159111100381.29407.10499392760570265777@build.alporthouse.com> Quoting Jani Nikula (2020-06-02 16:11:26) > The reset member in i915_params was previously changed to unsigned, but > this failed to change the actual module parameter. > > Fixes: aae970d8454b ("drm/i915: Mark i915.reset as unsigned") > Cc: Chris Wilson > Cc: Mika Kuoppala > Signed-off-by: Jani Nikula Reviewed-by: Chris Wilson -Chris From andriy.shevchenko at linux.intel.com Tue Jun 2 15:23:17 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Tue, 2 Jun 2020 18:23:17 +0300 Subject: [Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) In-Reply-To: <20200602122130.45630-1-hdegoede@redhat.com> References: <20200602122130.45630-1-hdegoede@redhat.com> Message-ID: <20200602152317.GI2428291@smile.fi.intel.com> On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote: > The pins on the Bay Trail SoC have separate input-buffer and output-buffer > enable bits and a read of the level bit of the value register will always > return the value from the input-buffer. > > The BIOS of a device may configure a pin in output-only mode, only enabling > the output buffer, and write 1 to the level bit to drive the pin high. > This 1 written to the level bit will be stored inside the data-latch of the > output buffer. > > But a subsequent read of the value register will return 0 for the level bit > because the input-buffer is disabled. This causes a read-modify-write as > done by byt_gpio_set_direction() to write 0 to the level bit, driving the > pin low! > > Before this commit byt_gpio_direction_output() relied on > pinctrl_gpio_direction_output() to set the direction, followed by a call > to byt_gpio_set() to apply the selected value. This causes the pin to > go low between the pinctrl_gpio_direction_output() and byt_gpio_set() > calls. > > Change byt_gpio_direction_output() to directly make the register > modifications itself instead. Replacing the 2 subsequent writes to the > value register with a single write. > > Note that the pinctrl code does not keep track internally of the direction, > so not going through pinctrl_gpio_direction_output() is not an issue. > > This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is > already on at boot (no external monitor connected), then the i915 driver > does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The > temporarily going low of that GPIO was causing the panel to reset itself > after which it would not show an image until it was turned off and back on > again (until a full modeset was done on it). This commit fixes this. No Fixes tag? > Cc: stable at vger.kernel.org > Signed-off-by: Hans de Goede ... > +static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, > + unsigned int offset) > +{ > + void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); > + > + /* > + * Before making any direction modifications, do a check if gpio is set > + * for direct IRQ. On baytrail, setting GPIO to output does not make Since we change this, perhaps 'IRQ. On baytrail' -> 'IRQ. On Baytrail' (one space and capital 'B'). > + * sense, so let's at least inform the caller before they shoot > + * themselves in the foot. > + */ > + if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) > + dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output"); > +} ... > static int byt_gpio_direction_output(struct gpio_chip *chip, > unsigned int offset, int value) > { > - int ret = pinctrl_gpio_direction_output(chip->base + offset); > + struct intel_pinctrl *vg = gpiochip_get_data(chip); > + void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); > + unsigned long flags; > + u32 reg; > > - if (ret) > - return ret; > + raw_spin_lock_irqsave(&byt_lock, flags); > > - byt_gpio_set(chip, offset, value); > + byt_gpio_direct_irq_check(vg, offset); > > + reg = readl(val_reg); > + reg &= ~BYT_DIR_MASK; > + if (value) > + reg |= BYT_LEVEL; > + else > + reg &= ~BYT_LEVEL; > + > + writel(reg, val_reg); > + > + raw_spin_unlock_irqrestore(&byt_lock, flags); > return 0; > } Wouldn't be simple below fix the issue? @@ -1171,14 +1171,10 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) static int byt_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - int ret = pinctrl_gpio_direction_output(chip->base + offset); - - if (ret) - return ret; - + /* Set value first to avoid a glitch */ byt_gpio_set(chip, offset, value); - return 0; + return pinctrl_gpio_direction_output(chip->base + offset); } P.S. It's mangled, sorry. -- With Best Regards, Andy Shevchenko From andriy.shevchenko at linux.intel.com Tue Jun 2 15:25:55 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Tue, 2 Jun 2020 18:25:55 +0300 Subject: [Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) In-Reply-To: <20200602152317.GI2428291@smile.fi.intel.com> References: <20200602122130.45630-1-hdegoede@redhat.com> <20200602152317.GI2428291@smile.fi.intel.com> Message-ID: <20200602152555.GJ2428291@smile.fi.intel.com> On Tue, Jun 02, 2020 at 06:23:17PM +0300, Andy Shevchenko wrote: > On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote: ... > Wouldn't be simple below fix the issue? > > @@ -1171,14 +1171,10 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) > static int byt_gpio_direction_output(struct gpio_chip *chip, > unsigned int offset, int value) > { > - int ret = pinctrl_gpio_direction_output(chip->base + offset); > - > - if (ret) > - return ret; > - > + /* Set value first to avoid a glitch */ > byt_gpio_set(chip, offset, value); > > - return 0; > + return pinctrl_gpio_direction_output(chip->base + offset); > } > > > P.S. It's mangled, sorry. Cherrytrail does this way, btw, 549e783f6a1. -- With Best Regards, Andy Shevchenko From patchwork at emeril.freedesktop.org Tue Jun 2 15:31:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 15:31:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915=3A_Identify_Cometlake_plat?= =?utf-8?q?form?= In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <159111187231.21427.14144857571350440750@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Identify Cometlake platform URL : https://patchwork.freedesktop.org/series/77922/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8572 -> Patchwork_17843 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17843 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17843, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17843: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at workarounds: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-cml-s/igt at i915_selftest@live at workarounds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-cml-s/igt at i915_selftest@live at workarounds.html - fi-icl-y: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-icl-y/igt at i915_selftest@live at workarounds.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-icl-y/igt at i915_selftest@live at workarounds.html - fi-tgl-y: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-tgl-y/igt at i915_selftest@live at workarounds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-tgl-y/igt at i915_selftest@live at workarounds.html - fi-icl-guc: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-icl-guc/igt at i915_selftest@live at workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-icl-guc/igt at i915_selftest@live at workarounds.html - fi-icl-u2: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-icl-u2/igt at i915_selftest@live at workarounds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-icl-u2/igt at i915_selftest@live at workarounds.html - fi-cml-u2: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-cml-u2/igt at i915_selftest@live at workarounds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-cml-u2/igt at i915_selftest@live at workarounds.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at workarounds: - {fi-tgl-dsi}: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html - {fi-ehl-1}: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-ehl-1/igt at i915_selftest@live at workarounds.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-ehl-1/igt at i915_selftest@live at workarounds.html - {fi-tgl-u}: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-tgl-u/igt at i915_selftest@live at workarounds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-tgl-u/igt at i915_selftest@live at workarounds.html Known issues ------------ Here are the changes found in Patchwork_17843 that come from known issues: ### IGT changes ### #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][19] ([i915#62]) -> [SKIP][20] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8572 -> Patchwork_17843 CI-20190529: 20190529 CI_DRM_8572: 8a7011d0518058c59f13f10af147d1f97b0a1cd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17843: fd76a0e5a47e2313ced8653e0272073b12370610 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fd76a0e5a47e drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs cb7a71f01dd4 drm/i915: Identify Cometlake platform == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17843/index.html From jose.souza at intel.com Tue Jun 2 15:33:05 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 2 Jun 2020 15:33:05 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/dsi: Dont forget to clean up the connector on error (v2) In-Reply-To: <20200522202630.7604-1-vivek.kasireddy@intel.com> References: <20200507010103.16040-1-vivek.kasireddy@intel.com> <20200522202630.7604-1-vivek.kasireddy@intel.com> Message-ID: <472c8f97c12555081cfd45448100c54a9197b564.camel@intel.com> On Fri, 2020-05-22 at 13:26 -0700, Vivek Kasireddy wrote: > If an error is encountered during the DSI initialization setup, the > drm connector object also needs to be cleaned up along with the encoder. > The error can happen due to a missing mode in the VBT or for other > reasons. > > v2: Rephrase the commit message to make it more clear. > Reviewed-by: Jos? Roberto de Souza > Cc: Jani Nikula > Cc: Vandita Kulkarni > Signed-off-by: Vivek Kasireddy > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c > index 4fec5bd64920..f93f72463df5 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1954,6 +1954,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) > return; > > err: > + drm_connector_cleanup(connector); > drm_encoder_cleanup(&encoder->base); > kfree(intel_dsi); > kfree(intel_connector); From patchwork at emeril.freedesktop.org Tue Jun 2 15:34:55 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 15:34:55 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/params=3A_fix_i915=2Ereset_module_param_type?= In-Reply-To: <20200602151126.25626-1-jani.nikula@intel.com> References: <20200602151126.25626-1-jani.nikula@intel.com> Message-ID: <159111209517.21427.12373126367453704843@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: fix i915.reset module param type URL : https://patchwork.freedesktop.org/series/77923/ State : warning == Summary == $ dim checkpatch origin/drm-tip b693251369b3 drm/i915/params: fix i915.reset module param type -:25: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #25: FILE: drivers/gpu/drm/i915/i915_params.c:78: +i915_param_named_unsafe(reset, uint, 0400, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); total: 0 errors, 0 warnings, 1 checks, 8 lines checked From jose.souza at intel.com Tue Jun 2 15:35:12 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 2 Jun 2020 15:35:12 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/dsi=3A_Dont_forget_to_clean_up_the_connector_on_error_=28?= =?utf-8?q?rev3=29?= In-Reply-To: <159109693008.21427.10089451260181328056@emeril.freedesktop.org> References: <20200507010103.16040-1-vivek.kasireddy@intel.com> <159109693008.21427.10089451260181328056@emeril.freedesktop.org> Message-ID: On Tue, 2020-06-02 at 11:22 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/dsi: Dont forget to clean up the connector on error (rev3) > URL : https://patchwork.freedesktop.org/series/77011/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8568_full -> Patchwork_17838_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17838_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17838_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17838_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at gem_exec_reloc@basic-cpu-read: > - shard-skl: [PASS][1] -> [TIMEOUT][2] +2 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl5/igt at gem_exec_reloc@basic-cpu-read.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl9/igt at gem_exec_reloc@basic-cpu-read.html > > * igt at kms_plane_multiple@atomic-pipe-b-tiling-none: > - shard-iclb: [PASS][3] -> [FAIL][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb6/igt at kms_plane_multiple@atomic-pipe-b-tiling-none.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb1/igt at kms_plane_multiple@atomic-pipe-b-tiling-none.html > > Not related to this changes. Pushed to dinq, thanks for the patch. > > Known issues > ------------ > > Here are the changes found in Patchwork_17838_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +3 similar issues > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#648] / [i915#69]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl9/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][9] -> [FAIL][10] ([fdo#108145] / [i915#265]) +1 similar issue > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_psr@psr2_cursor_render: > - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109441]) +1 similar issue > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb2/igt at kms_psr@psr2_cursor_render.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb5/igt at kms_psr@psr2_cursor_render.html > > * igt at kms_vblank@pipe-c-wait-idle-hang: > - shard-apl: [PASS][13] -> [TIMEOUT][14] ([i915#1635]) +2 similar issues > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at kms_vblank@pipe-c-wait-idle-hang.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl6/igt at kms_vblank@pipe-c-wait-idle-hang.html > > > #### Possible fixes #### > > * {igt at gem_exec_schedule@implicit-write-read at rcs0}: > - shard-snb: [INCOMPLETE][15] ([i915#82]) -> [PASS][16] > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html > > * igt at gem_workarounds@suspend-resume-fd: > - shard-apl: [INCOMPLETE][17] -> [PASS][18] > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at gem_workarounds@suspend-resume-fd.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl6/igt at gem_workarounds@suspend-resume-fd.html > > * {igt at kms_flip@flip-vs-suspend at a-dp1}: > - shard-apl: [DMESG-WARN][19] ([i915#180]) -> [PASS][20] +3 similar issues > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl1/igt at kms_flip@flip-vs-suspend at a-dp1.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl7/igt at kms_flip@flip-vs-suspend at a-dp1.html > > * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1}: > - shard-skl: [FAIL][21] ([i915#1928]) -> [PASS][22] > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl9/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html > > * igt at kms_hdr@bpc-switch-dpms: > - shard-skl: [FAIL][23] ([i915#1188]) -> [PASS][24] +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl2/igt at kms_hdr@bpc-switch-dpms.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [FAIL][25] ([fdo#108145] / [i915#265]) -> [PASS][26] > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt at kms_psr@no_drrs: > - shard-iclb: [FAIL][27] ([i915#173]) -> [PASS][28] > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb1/igt at kms_psr@no_drrs.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb8/igt at kms_psr@no_drrs.html > > * igt at kms_psr@psr2_primary_mmap_cpu: > - shard-iclb: [SKIP][29] ([fdo#109441]) -> [PASS][30] +2 similar issues > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html > > * igt at kms_vblank@pipe-a-ts-continuation-suspend: > - shard-kbl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +1 similar issue > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > - shard-skl: [INCOMPLETE][33] ([i915#69]) -> [PASS][34] +1 similar issue > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-skl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-skl10/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc6-psr: > - shard-tglb: [SKIP][35] ([i915#468]) -> [FAIL][36] ([i915#1899]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-tglb2/igt at i915_pm_dc@dc6-psr.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-tglb3/igt at i915_pm_dc@dc6-psr.html > > * igt at kms_content_protection@atomic-dpms: > - shard-apl: [TIMEOUT][37] ([i915#1319] / [i915#1635]) -> [TIMEOUT][38] ([i915#1319]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl8/igt at kms_content_protection@atomic-dpms.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl6/igt at kms_content_protection@atomic-dpms.html > > * igt at kms_content_protection@srm: > - shard-apl: [FAIL][39] ([fdo#110321]) -> [TIMEOUT][40] ([i915#1319] / [i915#1635]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl4/igt at kms_content_protection@srm.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl1/igt at kms_content_protection@srm.html > > * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: > - shard-glk: [DMESG-WARN][41] ([i915#1926]) -> [DMESG-FAIL][42] ([i915#1925] / [i915#1926]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html > > * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: > - shard-glk: [DMESG-WARN][43] ([i915#1926]) -> [DMESG-WARN][44] ([i915#1927]) > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html > > * igt at kms_fbcon_fbt@fbc: > - shard-apl: [FAIL][45] ([i915#1525] / [i915#95]) -> [FAIL][46] ([i915#1525]) > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8568/shard-apl6/igt at kms_fbcon_fbt@fbc.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/shard-apl8/igt at kms_fbcon_fbt@fbc.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 > [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 > [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 > [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8568 -> Patchwork_17838 > > CI-20190529: 20190529 > CI_DRM_8568: 124bafc80c3ce62fc61b8eabb2657c87424b999b @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17838: a30b3a0e479eb9f2f48cf8a737656c9bbb64c15a @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17838/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Tue Jun 2 15:48:39 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 16:48:39 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs In-Reply-To: <20200602140541.5481-2-chris@chris-wilson.co.uk> References: <20200602140541.5481-2-chris@chris-wilson.co.uk> Message-ID: <20200602154839.6902-1-chris@chris-wilson.co.uk> For reasons that be, the HW only allows usersace to read its own CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for all by adding it to the whitelists. v2: The change took effect from Cometlake. v3: Ignore timestamps that autoincrement when validating the whitelist Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++- .../gpu/drm/i915/gt/selftest_workarounds.c | 17 +++++++++++++ 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6e1accbcc045..0731bbcef06c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) RING_FORCE_TO_NONPRIV_RANGE_4); } +static void cml_whitelist_build(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + + if (engine->class != RENDER_CLASS) + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); + + cfl_whitelist_build(engine); +} + static void cnl_whitelist_build(struct intel_engine_cs *engine) { struct i915_wa_list *w = &engine->whitelist; @@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* hucStatus2RegOffset */ whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), RING_FORCE_TO_NONPRIV_ACCESS_RD); + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) whitelist_reg(w, HIZ_CHICKEN); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) icl_whitelist_build(engine); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(engine); - else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) + else if (IS_COMETLAKE(i915)) + cml_whitelist_build(engine); + else if (IS_COFFEELAKE(i915)) cfl_whitelist_build(engine); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(engine); diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 32785463ec9e..febc9e6692ba 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -417,6 +417,20 @@ static bool wo_register(struct intel_engine_cs *engine, u32 reg) return false; } +static bool timestamp(const struct intel_engine_cs *engine, u32 reg) +{ + reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK; + switch (reg) { + case 0x358: + case 0x35c: + case 0x3a8: + return true; + + default: + return false; + } +} + static bool ro_register(u32 reg) { if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == @@ -497,6 +511,9 @@ static int check_dirty_whitelist(struct intel_context *ce) if (wo_register(engine, reg)) continue; + if (timestamp(engine, reg)) + continue; /* timestamps are expected to autoincrement */ + ro_reg = ro_register(reg); /* Clear non priv flags */ -- 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 2 15:56:14 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 15:56:14 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_fix_i915=2Ereset_module_param_type?= In-Reply-To: <20200602151126.25626-1-jani.nikula@intel.com> References: <20200602151126.25626-1-jani.nikula@intel.com> Message-ID: <159111337411.21429.1630006561503068563@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: fix i915.reset module param type URL : https://patchwork.freedesktop.org/series/77923/ State : success == Summary == CI Bug Log - changes from CI_DRM_8572 -> Patchwork_17844 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/index.html Known issues ------------ Here are the changes found in Patchwork_17844 that come from known issues: ### IGT changes ### #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [FAIL][1] ([i915#62]) -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8572 -> Patchwork_17844 CI-20190529: 20190529 CI_DRM_8572: 8a7011d0518058c59f13f10af147d1f97b0a1cd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17844: b693251369b3179f16a1789d74a0d7395ef3a7a8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b693251369b3 drm/i915/params: fix i915.reset module param type == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 16:27:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 16:27:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/2=5D_drm/i915=3A_Identify_Cometla?= =?utf-8?q?ke_platform_=28rev2=29?= In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <159111522214.21429.13983172343805581803@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Identify Cometlake platform (rev2) URL : https://patchwork.freedesktop.org/series/77922/ State : warning == Summary == $ dim checkpatch origin/drm-tip a71c14019fde drm/i915: Identify Cometlake platform -:367: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #367: FILE: drivers/gpu/drm/i915/i915_drv.h:1471: +#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ + INTEL_INFO(dev_priv)->gt == 2) -:381: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #381: FILE: drivers/gpu/drm/i915/i915_pci.c:769: +#define CML_PLATFORM \ + GEN9_FEATURES, \ + PLATFORM(INTEL_COMETLAKE) total: 1 errors, 0 warnings, 1 checks, 448 lines checked 444c42325fd7 drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs From patchwork at emeril.freedesktop.org Tue Jun 2 16:28:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 16:28:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/2=5D_drm/i915=3A_Identify_Cometlake_p?= =?utf-8?q?latform_=28rev2=29?= In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <159111529106.21427.13573369941760861434@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Identify Cometlake platform (rev2) URL : https://patchwork.freedesktop.org/series/77922/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Tue Jun 2 16:48:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 16:48:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915=3A_Identify_Cometlake_plat?= =?utf-8?q?form_=28rev2=29?= In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <159111650626.21428.18210285900488592785@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Identify Cometlake platform (rev2) URL : https://patchwork.freedesktop.org/series/77922/ State : success == Summary == CI Bug Log - changes from CI_DRM_8573 -> Patchwork_17845 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/index.html Changes ------- No changes found Participating hosts (51 -> 45) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17845 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17845: 444c42325fd7dc34d47e11e6a4d63d10e0cabc29 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 444c42325fd7 drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs a71c14019fde drm/i915: Identify Cometlake platform == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/index.html From nirmodas at amd.com Tue Jun 2 14:13:43 2020 From: nirmodas at amd.com (Nirmoy) Date: Tue, 2 Jun 2020 16:13:43 +0200 Subject: [Intel-gfx] [RFC PATCH 1/1] drm/mm: add ig_frag selftest In-Reply-To: <9cbdb0e2-5a44-5f87-df83-74c6b0c72e27@amd.com> References: <20200529163351.5228-1-nirmoy.das@amd.com> <159076753114.8851.15594151673471255964@build.alporthouse.com> <80a791cd-1319-795d-bd8a-1bf7dd6b9cc3@amd.com> <9cbdb0e2-5a44-5f87-df83-74c6b0c72e27@amd.com> Message-ID: <6b2d0137-8b7c-2dd0-b49f-1bf6bb300c06@amd.com> Hi Christian, On 6/2/20 2:47 PM, Christian K?nig wrote: > Nirmoy please keep in mind that your current implementation doesn't > fully solve the issue the test case is exercising. > > In other words what you have implement is fast skipping of fragmented > address space for bottom-up and top-down. > > But what this test here exercises is the fast skipping of aligned > allocations. You should probably adjust the test case a bit. Allocations with size=4k and aign = 8k is known to introduce fragmentation, do you mean I should only test bottom-up and top-down for now ? Regards, Nirmoy > > > Regards, > Christian. > > Am 29.05.20 um 23:01 schrieb Nirmoy: >> >> On 5/29/20 5:52 PM, Chris Wilson wrote: >>> Quoting Nirmoy (2020-05-29 16:40:53) >>>> This works correctly most of the times but sometimes >> >> >> I have to take my word back. In another machine,? 20k insertions in >> >> best mode takes 6-9 times more than 10k insertions, all most all the >> time. >> >> evict, bottom-up and top-down modes remains in 2-5 times range. >> >> >> If I reduce the insertions to 1k and 2k then scaling factor for best >> mode stays? below 4 most of the time. >> >> evict, bottom-up and top-down modes remains in 2-3 times range. >> >> >> I wonder if it makes sense to test with only 1k and 2k insertions and >> tolerate more than error if the mode == best. >> >> Regards, >> >> Nirmoy >> >>>> >>>> 20k insertions can take more than 8 times of 10k insertion time. >>> The pressure is on to improve then :) >>> >>>> Regards, >>>> >>>> Nirmoy >>>> >>>> On 5/29/20 6:33 PM, Nirmoy Das wrote: >>>>> This patch introduces fragmentation in the address range >>>>> and measures time taken by 10k and 20k insertions. ig_frag() >>>>> will fail if time taken by 20k insertions takes more than 4 times >>>>> of 10k insertions as we know that insertions scale quadratically. >>>>> Also tolerate 10% error because of kernel scheduler's jitters. >>>>> >>>>> Output: >>>>> >>>>> [ 8092.653518] drm_mm: Testing DRM range manger (struct drm_mm), >>>>> with random_seed=0x9bfb4117 max_iterations=8192 max_prime=128 >>>>> [ 8092.653520] drm_mm: igt_sanitycheck - ok! >>>>> [ 8092.653525] igt_debug 0x0000000000000000-0x0000000000000200: >>>>> 512: free >>>>> [ 8092.653526] igt_debug 0x0000000000000200-0x0000000000000600: >>>>> 1024: used >>>>> [ 8092.653527] igt_debug 0x0000000000000600-0x0000000000000a00: >>>>> 1024: free >>>>> [ 8092.653528] igt_debug 0x0000000000000a00-0x0000000000000e00: >>>>> 1024: used >>>>> [ 8092.653529] igt_debug 0x0000000000000e00-0x0000000000001000: >>>>> 512: free >>>>> [ 8092.653529] igt_debug total: 4096, used 2048 free 2048 >>>>> [ 8112.569813] drm_mm: best fragmented insert of 10000 and 20000 >>>>> insertions took 504 and 1996 msecs >>>>> [ 8112.723254] drm_mm: bottom-up fragmented insert of 10000 and >>>>> 20000 insertions took 44 and 108 msecs >>>>> [ 8112.813212] drm_mm: top-down fragmented insert of 10000 and >>>>> 20000 insertions took 40 and 44 msecs >>>>> [ 8112.847733] drm_mm: evict fragmented insert of 10000 and 20000 >>>>> insertions took 8 and 20 msecs >>>>> >>>>> >>>>> Signed-off-by: Nirmoy Das >>>>> --- >>>>> ?? drivers/gpu/drm/selftests/drm_mm_selftests.h |? 1 + >>>>> ?? drivers/gpu/drm/selftests/test-drm_mm.c????? | 73 >>>>> ++++++++++++++++++++ >>>>> ?? 2 files changed, 74 insertions(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>> b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>> index 6b943ea1c57d..8c87c964176b 100644 >>>>> --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>> +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>> @@ -14,6 +14,7 @@ selftest(insert, igt_insert) >>>>> ?? selftest(replace, igt_replace) >>>>> ?? selftest(insert_range, igt_insert_range) >>>>> ?? selftest(align, igt_align) >>>>> +selftest(frag, igt_frag) >>>>> ?? selftest(align32, igt_align32) >>>>> ?? selftest(align64, igt_align64) >>>>> ?? selftest(evict, igt_evict) >>>>> diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c >>>>> b/drivers/gpu/drm/selftests/test-drm_mm.c >>>>> index 9aabe82dcd3a..05d8f3659b4d 100644 >>>>> --- a/drivers/gpu/drm/selftests/test-drm_mm.c >>>>> +++ b/drivers/gpu/drm/selftests/test-drm_mm.c >>>>> @@ -1033,6 +1033,79 @@ static int igt_insert_range(void *ignored) >>>>> ?????? return 0; >>>>> ?? } >>>>> ?? +static int get_insert_time(unsigned int num_insert, >>>>> +??????????????????????? const struct insert_mode *mode) >>>>> +{ >>>>> +???? struct drm_mm mm; >>>>> +???? struct drm_mm_node *nodes, *node, *next; >>>>> +???? unsigned int size = 4096, align = 8192; >>>>> +???? unsigned long start; >>>>> +???? unsigned int i; >>>>> +???? int ret = -EINVAL; >>>>> + >>>>> +???? drm_mm_init(&mm, 1, U64_MAX - 2); >>>>> +???? nodes = vzalloc(array_size(num_insert, sizeof(*nodes))); >>>>> +???? if (!nodes) >>>>> +???????????? goto err; >>>>> + >>>>> +???? start = jiffies; >>> Use ktime_t start = ktime_now(); >>> >>>>> +???? for (i = 0; i < num_insert; i++) { >>>>> +???????????? if (!expect_insert(&mm, &nodes[i], size, align, i, >>>>> mode)) { >>>>> +???????????????????? pr_err("%s insert failed\n", mode->name); >>>>> +???????????????????? goto out; >>>>> +???????????? } >>>>> +???? } >>>>> + >>>>> +???? ret = jiffies_to_msecs(jiffies - start); >>> ret = ktime_sub(ktime_now(), start); >>> >>> The downside to using ktime is remembering it is s64 and so requires >>> care >>> and attention in doing math. >>> >>>>> +out: >>>>> +???? drm_mm_for_each_node_safe(node, next, &mm) >>>>> +???????????? drm_mm_remove_node(node); >>>>> +???? drm_mm_takedown(&mm); >>>>> +???? vfree(nodes); >>>>> +err: >>>>> +???? return ret; >>>>> + >>>>> +} >>>>> + >>>>> +static int igt_frag(void *ignored) >>>>> +{ >>>>> +???? const struct insert_mode *mode; >>>>> +???? unsigned int insert_time1, insert_time2; >>>>> +???? unsigned int insert_size = 10000; >>>>> +???? unsigned int scale_factor = 4; >>>>> +???? /* tolerate 10% excess insertion duration */ >>>>> +???? unsigned int error_factor = 110; >>>>> +???? int ret = -EINVAL; >>>>> + >>>>> +???? for (mode = insert_modes; mode->name; mode++) { >>>>> +???????????? unsigned int expected_time; >>>>> + >>>>> +???????????? insert_time1 = get_insert_time(insert_size, mode); >>>>> +???????????? if (insert_time1 < 0) >>>>> +???????????????????? goto err; >>> Ah, can you propagate the actual error. I see you are returning EINVAL >>> for ENOMEM errors. Just wait until it hits and you have to debug why :) >>> >>>>> +???????????? insert_time2 = get_insert_time((insert_size * 2), >>>>> mode); >>>>> +???????????? if (insert_time2 < 0) >>>>> +???????????????????? goto err; >>>>> + >>>>> +???????????? expected_time = (scale_factor * insert_time1 * >>>>> +????????????????????????????? error_factor)/100; >>>>> +???????????? if (insert_time2 > expected_time) { >>>>> +???????????????????? pr_err("%s fragmented insert took more %u >>>>> msecs\n", >>>>> +??????????????????????????? mode->name, insert_time2 - >>>>> expected_time); >>>>> +???????????????????? goto err; >>>>> +???????????? } >>>>> + >>>>> +???????????? pr_info("%s fragmented insert of %u and %u >>>>> insertions took %u and %u msecs\n", >>>>> +???????????????????? mode->name, insert_size, insert_size * 2, >>>>> insert_time1, >>>>> +???????????????????? insert_time2); >>> Put the info first before the error. We always want the full details, >>> with the error message explaining why it's unhappy. >>> -Chris >>> _______________________________________________ >>> dri-devel mailing list >>> dri-devel at lists.freedesktop.org >>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=02%7C01%7Cnirmoy.das%40amd.com%7C5c7df129b9cf44b3ae4008d803e84445%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637263643415833767&sdata=PrCQse4nhN0ZITT9OniuHhF7A5uxJD6ehk0PMjm7WMU%3D&reserved=0 >>> > From peterz at infradead.org Tue Jun 2 17:46:39 2020 From: peterz at infradead.org (Peter Zijlstra) Date: Tue, 2 Jun 2020 19:46:39 +0200 Subject: [Intel-gfx] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 Message-ID: <20200602174639.GB2604@hirez.programming.kicks-ass.net> Hi All, My desktop (Intel(R) Xeon(R) CPU E3-1245 v5 @ 3.50GHz) is spewing tons and tons of: [ 778.461227] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 778.477763] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 778.577718] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 778.577824] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 at a rate of ~3 per second, and X isn't as stable as one would like (it crashes every few days, sometimes taking the whole kernel along). Sadly, this being my desktop, I don't actually have a serial line connected to it, although I could hook one up if required. It is currently running 5.6.14-1 (as per debian testing), but it seems to have done this for a while, I only now got around to reporting it :/ What else I you need to know, want me to try etc.. ? ~ Peter From jose.souza at intel.com Tue Jun 2 18:08:03 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 2 Jun 2020 18:08:03 +0000 Subject: [Intel-gfx] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 In-Reply-To: <20200602174639.GB2604@hirez.programming.kicks-ass.net> References: <20200602174639.GB2604@hirez.programming.kicks-ass.net> Message-ID: <5a40182c8a865d6c5603de4a1ff72c450ff403c3.camel@intel.com> Hi Peter Please file a bug by follow this instructions: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs On Tue, 2020-06-02 at 19:46 +0200, Peter Zijlstra wrote: > Hi All, > > My desktop (Intel(R) Xeon(R) CPU E3-1245 v5 @ 3.50GHz) is spewing tons > and tons of: > > [ 778.461227] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 778.477763] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 778.577718] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 778.577824] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > > at a rate of ~3 per second, and X isn't as stable as one would like (it > crashes every few days, sometimes taking the whole kernel along). Sadly, > this being my desktop, I don't actually have a serial line connected to > it, although I could hook one up if required. > > It is currently running 5.6.14-1 (as per debian testing), but it seems > to have done this for a while, I only now got around to reporting it :/ > > What else I you need to know, want me to try etc.. ? > > ~ Peter > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From peterz at infradead.org Tue Jun 2 18:27:10 2020 From: peterz at infradead.org (Peter Zijlstra) Date: Tue, 2 Jun 2020 20:27:10 +0200 Subject: [Intel-gfx] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 In-Reply-To: <5a40182c8a865d6c5603de4a1ff72c450ff403c3.camel@intel.com> References: <20200602174639.GB2604@hirez.programming.kicks-ass.net> <5a40182c8a865d6c5603de4a1ff72c450ff403c3.camel@intel.com> Message-ID: <20200602182710.GD2604@hirez.programming.kicks-ass.net> On Tue, Jun 02, 2020 at 06:08:03PM +0000, Souza, Jose wrote: > Hi Peter > Please file a bug by follow this instructions: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs *sigh*, top posting and webforms :-( Steps to reproduce: Boot into X How often: Always uname -r: 5.6.0-2-amd64 Machine: Supermicro X11SSZ-F Display connector: [ 14.907] (II) intel(0): switch to mode 3840x2160 at 60.0 on DP2 using pipe 0, position (0, 0), rotation normal, reflection none [ 14.918] (II) intel(0): switch to mode 3840x2160 at 60.0 on DP3 using pipe 1, position (0, 0), rotation normal, reflection none I'll add the kernel parameters next time I reboot this thing, I'll also add the latest drm next time I build a kernel for this machine. From clinton.a.taylor at intel.com Tue Jun 2 19:25:01 2020 From: clinton.a.taylor at intel.com (clinton.a.taylor at intel.com) Date: Tue, 2 Jun 2020 12:25:01 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Implement WA_16011163337 Message-ID: <20200602192501.5446-1-clinton.a.taylor@intel.com> From: Clint Taylor Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2 not being able to be read. Cc: Caz Yokoyama Cc: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index fa1e15657663..7bc6474cce0e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -594,11 +594,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1604555607:gen12 and Wa_1608008084:gen12 * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit - * masks. So instead of doing a RMW we should just write the TDS timer - * value for Wa_1604555607. + * masks. So instead of doing a RMW we should just write the GS Timer + * and TDS timer values for Wa_1604555607 and Wa_16011163337. */ - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_TDS_TIMER_128, 0); + wa_add(wal, FF_MODE2, FF_MODE2_GS_TIMER_MASK & FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_GS_TIMER_224 & FF_MODE2_TDS_TIMER_128, 0); /* WaDisableGPGPUMidThreadPreemption:tgl */ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 578cfe11cbb9..96d351fbeebb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8004,6 +8004,8 @@ enum { #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) #define FF_MODE2 _MMIO(0x6604) +#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) +#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) -- 2.26.0 From patchwork at emeril.freedesktop.org Tue Jun 2 19:44:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 19:44:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/atomic-helper=3A_reset_vblank_o?= =?utf-8?q?n_crtc_reset_=28rev2=29?= In-Reply-To: <20200602095140.36678-1-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> Message-ID: <159112705077.21429.2698232940867199747@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/atomic-helper: reset vblank on crtc reset (rev2) URL : https://patchwork.freedesktop.org/series/77908/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8571_full -> Patchwork_17839_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17839_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17839_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17839_full: ### IGT changes ### #### Possible regressions #### * igt at gem_ctx_persistence@replace-hostile at rcs0: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-skl10/igt at gem_ctx_persistence@replace-hostile at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-skl2/igt at gem_ctx_persistence@replace-hostile at rcs0.html * igt at gem_workarounds@suspend-resume-fd: - shard-apl: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-apl6/igt at gem_workarounds@suspend-resume-fd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-apl6/igt at gem_workarounds@suspend-resume-fd.html * igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-render: - shard-tglb: [PASS][5] -> [TIMEOUT][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-render.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-tglb5/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-render.html Known issues ------------ Here are the changes found in Patchwork_17839_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_workarounds@suspend-resume-fd: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#69]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-skl4/igt at gem_workarounds@suspend-resume-fd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-skl9/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_pm_rpm@gem-evict-pwrite: - shard-tglb: [PASS][9] -> [SKIP][10] ([i915#579]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-tglb8/igt at i915_pm_rpm@gem-evict-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-tglb5/igt at i915_pm_rpm@gem-evict-pwrite.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#1119] / [i915#118] / [i915#95]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-glk7/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#54] / [i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][15] -> [FAIL][16] ([i915#57]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-hsw1/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1926]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-glk7/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-glk2/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][19] -> [DMESG-FAIL][20] ([i915#1925] / [i915#1926]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-glk8/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-glk6/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109349]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-iclb1/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180] / [i915#93] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-kbl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-iclb: [PASS][27] -> [INCOMPLETE][28] ([i915#1185] / [i915#250]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-iclb4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-iclb3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-iclb8/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-apl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-apl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html #### Possible fixes #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [FAIL][33] ([i915#1528]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-skl4/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-skl1/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gen9_exec_parse@allowed-all: - shard-glk: [DMESG-WARN][35] ([i915#1436] / [i915#716]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-glk9/igt at gen9_exec_parse@allowed-all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-glk6/igt at gen9_exec_parse@allowed-all.html * igt at i915_pm_rpm@gem-execbuf-stress: - shard-iclb: [INCOMPLETE][37] ([i915#189]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-iclb4/igt at i915_pm_rpm@gem-execbuf-stress.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-iclb1/igt at i915_pm_rpm@gem-execbuf-stress.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-apl: [FAIL][39] ([i915#70] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-apl6/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-apl2/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * {igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][41] ([i915#79]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-glk1/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-glk1/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@2x-flip-vs-rmfb-interruptible at ab-vga1-hdmi-a1}: - shard-hsw: [INCOMPLETE][43] ([i915#1927] / [i915#61]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-hsw8/igt at kms_flip@2x-flip-vs-rmfb-interruptible at ab-vga1-hdmi-a1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-hsw6/igt at kms_flip@2x-flip-vs-rmfb-interruptible at ab-vga1-hdmi-a1.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +5 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][49] ([i915#1188]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-iclb8/igt at kms_psr@psr2_sprite_plane_move.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][55] ([i915#658]) -> [SKIP][56] ([i915#588]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-iclb5/igt at i915_pm_dc@dc3co-vpb-simulation.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_color@pipe-d-ctm-red-to-blue: - shard-hsw: [SKIP][57] ([fdo#109271]) -> [FAIL][58] ([i915#1927]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-hsw4/igt at kms_color@pipe-d-ctm-red-to-blue.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-hsw6/igt at kms_color@pipe-d-ctm-red-to-blue.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][59] ([i915#1319] / [i915#1635]) -> [FAIL][60] ([fdo#110321] / [fdo#110336]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-apl4/igt at kms_content_protection@atomic-dpms.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][61] ([i915#1319] / [i915#1635]) -> [FAIL][62] ([fdo#110321]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-apl8/igt at kms_content_protection@lic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-apl4/igt at kms_content_protection@lic.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][63] ([i915#1525] / [i915#95]) -> [FAIL][64] ([i915#1525]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-apl1/igt at kms_fbcon_fbt@fbc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-apl8/igt at kms_fbcon_fbt@fbc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [FAIL][66] ([i915#608]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-iclb5/igt at kms_psr2_su@page_flip.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at runner@aborted: - shard-hsw: [FAIL][67] -> [FAIL][68] ([fdo#109271] / [i915#1927]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8571/shard-hsw8/igt at runner@aborted.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/shard-hsw6/igt at runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8571 -> Patchwork_17839 CI-20190529: 20190529 CI_DRM_8571: 0536dff30eff69abcf6355bdd9b9fdf45a560099 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17839: 011586de521b2df487223c8f7c1739f041bd7d07 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17839/index.html From jose.souza at intel.com Tue Jun 2 19:52:34 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 2 Jun 2020 19:52:34 +0000 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Identify Cometlake platform In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <13aef8d1600a692438aaf013e456a82ec849b81c.camel@intel.com> On Tue, 2020-06-02 at 15:05 +0100, Chris Wilson wrote: > Cometlake is small refresh of Coffeelake, but since we have found out a > difference in the plaforms, we need to identify the separate platforms. > > Since we previously took Coffeelake/Cometlake as identical, update all > IS_COFFEELAKE() to also include IS_COMETLAKE(). No IS_COFFEELAKE() check left without a IS_COMETLAKE(). Reviewed-by: Jos? Roberto de Souza > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/display/intel_csr.c | 4 ++- > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++------ > drivers/gpu/drm/i915/display/intel_hdcp.c | 7 ++-- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++---- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +- > drivers/gpu/drm/i915/gvt/display.c | 30 +++++++++++------ > drivers/gpu/drm/i915/gvt/edid.c | 2 +- > drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++++---- > drivers/gpu/drm/i915/i915_drv.h | 9 ++++++ > drivers/gpu/drm/i915/i915_pci.c | 22 ++++++++++--- > drivers/gpu/drm/i915/intel_device_info.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 1 + > drivers/gpu/drm/i915/intel_gvt.c | 2 ++ > drivers/gpu/drm/i915/intel_pch.c | 36 ++++++++++++++------- > drivers/gpu/drm/i915/intel_pm.c | 10 ++++-- > 15 files changed, 140 insertions(+), 55 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c > index 319932b03e88..9843c9af6c13 100644 > --- a/drivers/gpu/drm/i915/display/intel_csr.c > +++ b/drivers/gpu/drm/i915/display/intel_csr.c > @@ -707,7 +707,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) > csr->fw_path = GLK_CSR_PATH; > csr->required_version = GLK_CSR_VERSION_REQUIRED; > csr->max_fw_size = GLK_CSR_MAX_FW_SIZE; > - } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { > + } else if (IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) { > csr->fw_path = KBL_CSR_PATH; > csr->required_version = KBL_CSR_VERSION_REQUIRED; > csr->max_fw_size = KBL_CSR_MAX_FW_SIZE; > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index cd211f48c401..bb8107ab5a51 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -722,10 +722,14 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > static const struct ddi_buf_trans * > kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > { > - if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) { > + if (IS_KBL_ULX(dev_priv) || > + IS_CFL_ULX(dev_priv) || > + IS_CML_ULX(dev_priv)) { > *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); > return kbl_y_ddi_translations_dp; > - } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) { > + } else if (IS_KBL_ULT(dev_priv) || > + IS_CFL_ULT(dev_priv) || > + IS_CML_ULT(dev_priv)) { > *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); > return kbl_u_ddi_translations_dp; > } else { > @@ -738,12 +742,16 @@ static const struct ddi_buf_trans * > skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > { > if (dev_priv->vbt.edp.low_vswing) { > - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || > - IS_CFL_ULX(dev_priv)) { > + if (IS_SKL_ULX(dev_priv) || > + IS_KBL_ULX(dev_priv) || > + IS_CFL_ULX(dev_priv) || > + IS_CML_ULX(dev_priv)) { > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); > return skl_y_ddi_translations_edp; > - } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) || > - IS_CFL_ULT(dev_priv)) { > + } else if (IS_SKL_ULT(dev_priv) || > + IS_KBL_ULT(dev_priv) || > + IS_CFL_ULT(dev_priv) || > + IS_CML_ULT(dev_priv)) { > *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); > return skl_u_ddi_translations_edp; > } else { > @@ -752,7 +760,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > } > } > > - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) > + if (IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) > return kbl_get_buf_trans_dp(dev_priv, n_entries); > else > return skl_get_buf_trans_dp(dev_priv, n_entries); > @@ -761,8 +771,10 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > static const struct ddi_buf_trans * > skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) > { > - if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || > - IS_CFL_ULX(dev_priv)) { > + if (IS_SKL_ULX(dev_priv) || > + IS_KBL_ULX(dev_priv) || > + IS_CFL_ULX(dev_priv) || > + IS_CML_ULX(dev_priv)) { > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); > return skl_y_ddi_translations_hdmi; > } else { > @@ -784,7 +796,9 @@ static const struct ddi_buf_trans * > intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, > enum port port, int *n_entries) > { > - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { > + if (IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) { > const struct ddi_buf_trans *ddi_translations = > kbl_get_buf_trans_dp(dev_priv, n_entries); > *n_entries = skl_buf_trans_num_entries(port, *n_entries); > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 2cbc4619b4ce..815b054bb167 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -1923,8 +1923,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *dev_priv) > if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) > return false; > > - return (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || > - IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)); > + return (INTEL_GEN(dev_priv) >= 10 || > + IS_GEMINILAKE(dev_priv) || > + IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)); > } > > void intel_hdcp_component_init(struct drm_i915_private *dev_priv) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 94d66a9d760d..6e1accbcc045 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -361,7 +361,10 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, > HDC_FORCE_NON_COHERENT); > > /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */ > - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) > + if (IS_SKYLAKE(i915) || > + IS_KABYLAKE(i915) || > + IS_COFFEELAKE(i915) || > + IS_COMETLAKE(i915)) > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, > GEN8_SAMPLER_POWER_BYPASS_DIS); > > @@ -636,7 +639,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, > icl_ctx_workarounds_init(engine, wal); > else if (IS_CANNONLAKE(i915)) > cnl_ctx_workarounds_init(engine, wal); > - else if (IS_COFFEELAKE(i915)) > + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) > cfl_ctx_workarounds_init(engine, wal); > else if (IS_GEMINILAKE(i915)) > glk_ctx_workarounds_init(engine, wal); > @@ -706,7 +709,7 @@ static void > gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > /* WaDisableKillLogic:bxt,skl,kbl */ > - if (!IS_COFFEELAKE(i915)) > + if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) > wa_write_or(wal, > GAM_ECOCHK, > ECOCHK_DIS_TLB); > @@ -969,7 +972,7 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > icl_gt_workarounds_init(i915, wal); > else if (IS_CANNONLAKE(i915)) > cnl_gt_workarounds_init(i915, wal); > - else if (IS_COFFEELAKE(i915)) > + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) > cfl_gt_workarounds_init(i915, wal); > else if (IS_GEMINILAKE(i915)) > glk_gt_workarounds_init(i915, wal); > @@ -1304,7 +1307,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) > icl_whitelist_build(engine); > else if (IS_CANNONLAKE(i915)) > cnl_whitelist_build(engine); > - else if (IS_COFFEELAKE(i915)) > + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) > cfl_whitelist_build(engine); > else if (IS_GEMINILAKE(i915)) > glk_whitelist_build(engine); > @@ -1515,7 +1518,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > GEN9_FFSC_PERCTX_PREEMPT_CTRL); > } > > - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { > + if (IS_SKYLAKE(i915) || > + IS_KABYLAKE(i915) || > + IS_COFFEELAKE(i915) || > + IS_COMETLAKE(i915)) { > /* WaEnableGapsTsvCreditFix:skl,kbl,cfl */ > wa_write_or(wal, > GEN8_GARBCNTL, > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > index 9b6218128d09..e75be3999358 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > @@ -55,7 +55,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, > fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \ > fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \ > fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \ > - fw_def(COFFEELAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ > + fw_def(COMETLAKE, 5, guc_def(cml, 33, 0, 0), huc_def(cml, 4, 0, 0)) \ > fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ > fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 4, 0, 0)) \ > fw_def(KABYLAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 4, 0, 0)) \ > diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c > index a1696e9ce4b6..7ba16ddfe75f 100644 > --- a/drivers/gpu/drm/i915/gvt/display.c > +++ b/drivers/gpu/drm/i915/gvt/display.c > @@ -199,8 +199,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) > SDE_PORTC_HOTPLUG_CPT | > SDE_PORTD_HOTPLUG_CPT); > > - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv)) { > + if (IS_SKYLAKE(dev_priv) || > + IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) { > vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT | > SDE_PORTE_HOTPLUG_SPT); > vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |= > @@ -314,8 +316,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) > vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED; > } > > - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv)) && > + if ((IS_SKYLAKE(dev_priv) || > + IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) && > intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { > vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT; > } > @@ -498,8 +502,10 @@ void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected) > struct drm_i915_private *i915 = vgpu->gvt->gt->i915; > > /* TODO: add more platforms support */ > - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || > - IS_COFFEELAKE(i915)) { > + if (IS_SKYLAKE(i915) || > + IS_KABYLAKE(i915) || > + IS_COFFEELAKE(i915) || > + IS_COMETLAKE(i915)) { > if (connected) { > vgpu_vreg_t(vgpu, SFUSE_STRAP) |= > SFUSE_STRAP_DDID_DETECTED; > @@ -527,8 +533,10 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) > { > struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; > > - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv)) > + if (IS_SKYLAKE(dev_priv) || > + IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) > clean_virtual_dp_monitor(vgpu, PORT_D); > else > clean_virtual_dp_monitor(vgpu, PORT_B); > @@ -551,8 +559,10 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) > > intel_vgpu_init_i2c_edid(vgpu); > > - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) || > - IS_COFFEELAKE(dev_priv)) > + if (IS_SKYLAKE(dev_priv) || > + IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) > return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D, > resolution); > else > diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c > index 190651df5db1..22247805c345 100644 > --- a/drivers/gpu/drm/i915/gvt/edid.c > +++ b/drivers/gpu/drm/i915/gvt/edid.c > @@ -149,7 +149,7 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, > > if (IS_BROXTON(i915)) > port = bxt_get_port_from_gmbus0(pin_select); > - else if (IS_COFFEELAKE(i915)) > + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) > port = cnp_get_port_from_gmbus0(pin_select); > else > port = get_port_from_gmbus0(pin_select); > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index 3e88e3b5c43a..26cae4846c82 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -59,7 +59,7 @@ unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) > return D_KBL; > else if (IS_BROXTON(i915)) > return D_BXT; > - else if (IS_COFFEELAKE(i915)) > + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) > return D_CFL; > > return 0; > @@ -1435,7 +1435,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, > case GEN9_PCODE_READ_MEM_LATENCY: > if (IS_SKYLAKE(vgpu->gvt->gt->i915) || > IS_KABYLAKE(vgpu->gvt->gt->i915) || > - IS_COFFEELAKE(vgpu->gvt->gt->i915)) { > + IS_COFFEELAKE(vgpu->gvt->gt->i915) || > + IS_COMETLAKE(vgpu->gvt->gt->i915)) { > /** > * "Read memory latency" command on gen9. > * Below memory latency values are read > @@ -1460,7 +1461,8 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, > case SKL_PCODE_CDCLK_CONTROL: > if (IS_SKYLAKE(vgpu->gvt->gt->i915) || > IS_KABYLAKE(vgpu->gvt->gt->i915) || > - IS_COFFEELAKE(vgpu->gvt->gt->i915)) > + IS_COFFEELAKE(vgpu->gvt->gt->i915) || > + IS_COMETLAKE(vgpu->gvt->gt->i915)) > *data0 = SKL_CDCLK_READY_FOR_CHANGE; > break; > case GEN6_PCODE_READ_RC6VIDS: > @@ -1722,7 +1724,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, > int ret; > > (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); > - if (IS_COFFEELAKE(vgpu->gvt->gt->i915)) > + if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || > + IS_COMETLAKE(vgpu->gvt->gt->i915)) > (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); > write_vreg(vgpu, offset, p_data, bytes); > > @@ -1731,7 +1734,8 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, > return 0; > } > > - if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && > + if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || > + IS_COMETLAKE(vgpu->gvt->gt->i915)) && > data & _MASKED_BIT_ENABLE(2)) { > enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); > return 0; > @@ -3393,7 +3397,8 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) > goto err; > } else if (IS_SKYLAKE(i915) || > IS_KABYLAKE(i915) || > - IS_COFFEELAKE(i915)) { > + IS_COFFEELAKE(i915) || > + IS_COMETLAKE(i915)) { > ret = init_bdw_mmio_info(gvt); > if (ret) > goto err; > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 98f2c448cd92..e99255e17eb7 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1414,6 +1414,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) > #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) > #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) > +#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) > #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) > #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) > #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) > @@ -1462,6 +1463,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > INTEL_INFO(dev_priv)->gt == 2) > #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ > INTEL_INFO(dev_priv)->gt == 3) > + > +#define IS_CML_ULT(dev_priv) \ > + IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) > +#define IS_CML_ULX(dev_priv) \ > + IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) > +#define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ > + INTEL_INFO(dev_priv)->gt == 2) > + > #define IS_CNL_WITH_PORT_F(dev_priv) \ > IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) > #define IS_ICL_WITH_PORT_F(dev_priv) \ > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 7e3252fbad8e..07b09af3a9c3 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -766,6 +766,20 @@ static const struct intel_device_info cfl_gt3_info = { > BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), > }; > > +#define CML_PLATFORM \ > + GEN9_FEATURES, \ > + PLATFORM(INTEL_COMETLAKE) > + > +static const struct intel_device_info cml_gt1_info = { > + CML_PLATFORM, > + .gt = 1, > +}; > + > +static const struct intel_device_info cml_gt2_info = { > + CML_PLATFORM, > + .gt = 2, > +}; > + > #define GEN10_FEATURES \ > GEN9_FEATURES, \ > GEN(10), \ > @@ -942,10 +956,10 @@ static const struct pci_device_id pciidlist[] = { > INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), > INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), > INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), > - INTEL_CML_GT1_IDS(&cfl_gt1_info), > - INTEL_CML_GT2_IDS(&cfl_gt2_info), > - INTEL_CML_U_GT1_IDS(&cfl_gt1_info), > - INTEL_CML_U_GT2_IDS(&cfl_gt2_info), > + INTEL_CML_GT1_IDS(&cml_gt1_info), > + INTEL_CML_GT2_IDS(&cml_gt2_info), > + INTEL_CML_U_GT1_IDS(&cml_gt1_info), > + INTEL_CML_U_GT2_IDS(&cml_gt2_info), > INTEL_CNL_IDS(&cnl_info), > INTEL_ICL_11_IDS(&icl_info), > INTEL_EHL_IDS(&ehl_info), > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index c245c10c9bee..544ac61fbc36 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -57,6 +57,7 @@ static const char * const platform_names[] = { > PLATFORM_NAME(KABYLAKE), > PLATFORM_NAME(GEMINILAKE), > PLATFORM_NAME(COFFEELAKE), > + PLATFORM_NAME(COMETLAKE), > PLATFORM_NAME(CANNONLAKE), > PLATFORM_NAME(ICELAKE), > PLATFORM_NAME(ELKHARTLAKE), > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index c912acd06109..3613c04904e0 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -73,6 +73,7 @@ enum intel_platform { > INTEL_KABYLAKE, > INTEL_GEMINILAKE, > INTEL_COFFEELAKE, > + INTEL_COMETLAKE, > /* gen10 */ > INTEL_CANNONLAKE, > /* gen11 */ > diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c > index 21b91313cc5d..dd8981340d6e 100644 > --- a/drivers/gpu/drm/i915/intel_gvt.c > +++ b/drivers/gpu/drm/i915/intel_gvt.c > @@ -52,6 +52,8 @@ static bool is_supported_device(struct drm_i915_private *dev_priv) > return true; > if (IS_COFFEELAKE(dev_priv)) > return true; > + if (IS_COMETLAKE(dev_priv)) > + return true; > > return false; > } > diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c > index 102b03d24f90..c668e99eb2e4 100644 > --- a/drivers/gpu/drm/i915/intel_pch.c > +++ b/drivers/gpu/drm/i915/intel_pch.c > @@ -64,37 +64,49 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) > case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); > drm_WARN_ON(&dev_priv->drm, > - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && > - !IS_COFFEELAKE(dev_priv)); > + !IS_SKYLAKE(dev_priv) && > + !IS_KABYLAKE(dev_priv) && > + !IS_COFFEELAKE(dev_priv) && > + !IS_COMETLAKE(dev_priv)); > return PCH_SPT; > case INTEL_PCH_KBP_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n"); > drm_WARN_ON(&dev_priv->drm, > - !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) && > - !IS_COFFEELAKE(dev_priv)); > + !IS_SKYLAKE(dev_priv) && > + !IS_KABYLAKE(dev_priv) && > + !IS_COFFEELAKE(dev_priv) && > + !IS_COMETLAKE(dev_priv)); > /* KBP is SPT compatible */ > return PCH_SPT; > case INTEL_PCH_CNP_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n"); > - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && > - !IS_COFFEELAKE(dev_priv)); > + drm_WARN_ON(&dev_priv->drm, > + !IS_CANNONLAKE(dev_priv) && > + !IS_COFFEELAKE(dev_priv) && > + !IS_COMETLAKE(dev_priv)); > return PCH_CNP; > case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, > "Found Cannon Lake LP PCH (CNP-LP)\n"); > - drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && > - !IS_COFFEELAKE(dev_priv)); > + drm_WARN_ON(&dev_priv->drm, > + !IS_CANNONLAKE(dev_priv) && > + !IS_COFFEELAKE(dev_priv) && > + !IS_COMETLAKE(dev_priv)); > return PCH_CNP; > case INTEL_PCH_CMP_DEVICE_ID_TYPE: > case INTEL_PCH_CMP2_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n"); > - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv) && > + drm_WARN_ON(&dev_priv->drm, > + !IS_COFFEELAKE(dev_priv) && > + !IS_COMETLAKE(dev_priv) && > !IS_ROCKETLAKE(dev_priv)); > /* CometPoint is CNP Compatible */ > return PCH_CNP; > case INTEL_PCH_CMP_V_DEVICE_ID_TYPE: > drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n"); > - drm_WARN_ON(&dev_priv->drm, !IS_COFFEELAKE(dev_priv)); > + drm_WARN_ON(&dev_priv->drm, > + !IS_COFFEELAKE(dev_priv) && > + !IS_COMETLAKE(dev_priv)); > /* Comet Lake V PCH is based on KBP, which is SPT compatible */ > return PCH_SPT; > case INTEL_PCH_ICP_DEVICE_ID_TYPE: > @@ -149,7 +161,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) > id = INTEL_PCH_MCC_DEVICE_ID_TYPE; > else if (IS_ICELAKE(dev_priv)) > id = INTEL_PCH_ICP_DEVICE_ID_TYPE; > - else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) > + else if (IS_CANNONLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) > id = INTEL_PCH_CNP_DEVICE_ID_TYPE; > else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) > id = INTEL_PCH_SPT_DEVICE_ID_TYPE; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b134a1b9d738..26b670fa3f88 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5256,7 +5256,9 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, > * WaIncreaseLatencyIPCEnabled: kbl,cfl > * Display WA #1141: kbl,cfl > */ > - if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) && > + if ((IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) && > dev_priv->ipc_enabled) > latency += 4; > > @@ -6822,7 +6824,9 @@ static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv) > return false; > > /* Display WA #1141: SKL:all KBL:all CFL */ > - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) > + if (IS_KABYLAKE(dev_priv) || > + IS_COFFEELAKE(dev_priv) || > + IS_COMETLAKE(dev_priv)) > return dev_priv->dram_info.symmetric_memory; > > return true; > @@ -7703,7 +7707,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.init_clock_gating = icl_init_clock_gating; > else if (IS_CANNONLAKE(dev_priv)) > dev_priv->display.init_clock_gating = cnl_init_clock_gating; > - else if (IS_COFFEELAKE(dev_priv)) > + else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) > dev_priv->display.init_clock_gating = cfl_init_clock_gating; > else if (IS_SKYLAKE(dev_priv)) > dev_priv->display.init_clock_gating = skl_init_clock_gating; From jose.souza at intel.com Tue Jun 2 19:56:12 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 2 Jun 2020 19:56:12 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs In-Reply-To: <20200602154839.6902-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-2-chris@chris-wilson.co.uk> <20200602154839.6902-1-chris@chris-wilson.co.uk> Message-ID: <78e2807cd9d6d36a8e13ec38f6001ef7413cda1c.camel@intel.com> On Tue, 2020-06-02 at 16:48 +0100, Chris Wilson wrote: > For reasons that be, the HW only allows usersace to read its own > CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for > all by adding it to the whitelists. > > v2: The change took effect from Cometlake. > v3: Ignore timestamps that autoincrement when validating the whitelist I would have separated add the register to the whitelist from the selftest but anyways looks good. Reviewed-by: Jos? Roberto de Souza > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++- > .../gpu/drm/i915/gt/selftest_workarounds.c | 17 +++++++++++++ > 2 files changed, 41 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6e1accbcc045..0731bbcef06c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) > RING_FORCE_TO_NONPRIV_RANGE_4); > } > > +static void cml_whitelist_build(struct intel_engine_cs *engine) > +{ > + struct i915_wa_list *w = &engine->whitelist; > + > + if (engine->class != RENDER_CLASS) > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > + > + cfl_whitelist_build(engine); > +} > + > static void cnl_whitelist_build(struct intel_engine_cs *engine) > { > struct i915_wa_list *w = &engine->whitelist; > @@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) > /* hucStatus2RegOffset */ > whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), > RING_FORCE_TO_NONPRIV_ACCESS_RD); > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > break; > > default: > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > break; > } > } > @@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) > whitelist_reg(w, HIZ_CHICKEN); > break; > default: > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > break; > } > } > @@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) > icl_whitelist_build(engine); > else if (IS_CANNONLAKE(i915)) > cnl_whitelist_build(engine); > - else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) > + else if (IS_COMETLAKE(i915)) > + cml_whitelist_build(engine); > + else if (IS_COFFEELAKE(i915)) > cfl_whitelist_build(engine); > else if (IS_GEMINILAKE(i915)) > glk_whitelist_build(engine); > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > index 32785463ec9e..febc9e6692ba 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > @@ -417,6 +417,20 @@ static bool wo_register(struct intel_engine_cs *engine, u32 reg) > return false; > } > > +static bool timestamp(const struct intel_engine_cs *engine, u32 reg) > +{ > + reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK; > + switch (reg) { > + case 0x358: > + case 0x35c: > + case 0x3a8: > + return true; > + > + default: > + return false; > + } > +} > + > static bool ro_register(u32 reg) > { > if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == > @@ -497,6 +511,9 @@ static int check_dirty_whitelist(struct intel_context *ce) > if (wo_register(engine, reg)) > continue; > > + if (timestamp(engine, reg)) > + continue; /* timestamps are expected to autoincrement */ > + > ro_reg = ro_register(reg); > > /* Clear non priv flags */ From patchwork at emeril.freedesktop.org Tue Jun 2 20:11:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 20:11:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Implement_WA=5F16011163337?= In-Reply-To: <20200602192501.5446-1-clinton.a.taylor@intel.com> References: <20200602192501.5446-1-clinton.a.taylor@intel.com> Message-ID: <159112867923.21427.13196545568994493372@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Implement WA_16011163337 URL : https://patchwork.freedesktop.org/series/77933/ State : success == Summary == CI Bug Log - changes from CI_DRM_8573 -> Patchwork_17846 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/index.html Changes ------- No changes found Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17846 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17846: fd295d4b23d0b98f18f5be0f265d525bb3f9ebce @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fd295d4b23d0 drm/i915/tgl: Implement WA_16011163337 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/index.html From chris at chris-wilson.co.uk Tue Jun 2 20:17:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 02 Jun 2020 21:17:54 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Implement WA_16011163337 In-Reply-To: <20200602192501.5446-1-clinton.a.taylor@intel.com> References: <20200602192501.5446-1-clinton.a.taylor@intel.com> Message-ID: <159112907493.29407.4400269611880004007@build.alporthouse.com> Quoting clinton.a.taylor at intel.com (2020-06-02 20:25:01) > From: Clint Taylor > > Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2 > not being able to be read. > > Cc: Caz Yokoyama > Cc: Matt Atwood > Signed-off-by: Clint Taylor > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++---- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index fa1e15657663..7bc6474cce0e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -594,11 +594,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > * Wa_1604555607:gen12 and Wa_1608008084:gen12 > * FF_MODE2 register will return the wrong value when read. The default > * value for this register is zero for all fields and there are no bit > - * masks. So instead of doing a RMW we should just write the TDS timer > - * value for Wa_1604555607. > + * masks. So instead of doing a RMW we should just write the GS Timer > + * and TDS timer values for Wa_1604555607 and Wa_16011163337. > */ > - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, > - FF_MODE2_TDS_TIMER_128, 0); > + wa_add(wal, FF_MODE2, FF_MODE2_GS_TIMER_MASK & FF_MODE2_TDS_TIMER_MASK, GS_TIMER_MASK & TDS_TIMER_MASK is 0 I think you meant | -Chris From jose.souza at intel.com Tue Jun 2 20:54:24 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Tue, 2 Jun 2020 13:54:24 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Add HBR and HBR2+ voltage swing table Message-ID: <20200602205424.138143-1-jose.souza@intel.com> As latest update we have now 2 voltage swing tables for DP over DKL PHY with only one difference in Level 0 pre-emphasis 3. So with 2 tables for DP is time to have one single function to return all DKL voltage swing tables. BSpec: 49292 Cc: Khaled Almahallawy Signed-off-by: Jos? Roberto de Souza --- drivers/gpu/drm/i915/display/intel_ddi.c | 50 ++++++++++++++++++++---- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index cd211f48c401..763d76056ca9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -641,6 +641,20 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ + { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ + { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ + { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ + { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ + { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ + { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ + { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ +}; + +static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { + /* VS pre-emp Non-trans mV Pre-emph dB */ + { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ + { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ + { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ @@ -1014,6 +1028,22 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, return tgl_combo_phy_ddi_translations_dp_hbr; } +static const struct tgl_dkl_phy_ddi_buf_trans * +tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, + int *n_entries) +{ + if (type == INTEL_OUTPUT_HDMI) { + *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); + return tgl_dkl_phy_hdmi_ddi_trans; + } else if (rate > 270000) { + *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); + return tgl_dkl_phy_dp_ddi_trans_hbr2; + } + + *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); + return tgl_dkl_phy_dp_ddi_trans; +} + static int intel_ddi_hdmi_level(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1025,7 +1055,8 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder) tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, &n_entries); else - n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); + tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, + &n_entries); default_entry = n_entries - 1; } else if (INTEL_GEN(dev_priv) == 11) { if (intel_phy_is_combo(dev_priv, phy)) @@ -2108,7 +2139,8 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) tgl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); else - n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); + tgl_get_dkl_buf_trans(dev_priv, encoder->type, + intel_dp->link_rate, &n_entries); } else if (INTEL_GEN(dev_priv) == 11) { if (IS_ELKHARTLAKE(dev_priv)) ehl_get_combo_buf_trans(dev_priv, encoder->type, @@ -2585,15 +2617,17 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; + int rate = 0; - if (encoder->type == INTEL_OUTPUT_HDMI) { - n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); - ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; - } else { - n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); - ddi_translations = tgl_dkl_phy_dp_ddi_trans; + if (encoder->type != INTEL_OUTPUT_HDMI) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + rate = intel_dp->link_rate; } + ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate, + &n_entries); + if (level >= n_entries) level = n_entries - 1; -- 2.26.2 From patchwork at emeril.freedesktop.org Tue Jun 2 21:52:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 21:52:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Add_HBR_and_HBR2+_voltage_swing_table?= In-Reply-To: <20200602205424.138143-1-jose.souza@intel.com> References: <20200602205424.138143-1-jose.souza@intel.com> Message-ID: <159113476133.21429.16156133905361705592@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Add HBR and HBR2+ voltage swing table URL : https://patchwork.freedesktop.org/series/77934/ State : success == Summary == CI Bug Log - changes from CI_DRM_8573 -> Patchwork_17847 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/index.html Changes ------- No changes found Participating hosts (51 -> 45) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17847 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17847: 6c49c456cc63e42fd77667b19ef3e88780a047dc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6c49c456cc63 drm/i915/tgl: Add HBR and HBR2+ voltage swing table == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/index.html From chris at chris-wilson.co.uk Tue Jun 2 22:09:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 2 Jun 2020 23:09:53 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Drop i915_request.i915 backpointer Message-ID: <20200602220953.21178-1-chris@chris-wilson.co.uk> We infrequently use the direct i915 backpointer from the i915_request, so do we really need to waste the space in the struct for it? 8 bytes from the most frequently allocated struct vs an 3 bytes and pointer chasing in using rq->engine->i915? Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++---- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++-- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++++----- drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++-- drivers/gpu/drm/i915/gvt/scheduler.c | 4 ++-- drivers/gpu/drm/i915/i915_request.c | 12 ++++++------ drivers/gpu/drm/i915/i915_request.h | 3 --- drivers/gpu/drm/i915/i915_trace.h | 10 +++++----- drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +- drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++------- 17 files changed, 43 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 219a36995b96..02a5c0ce39ca 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1910,8 +1910,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) u32 *cs; int i; - if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) { - drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n"); + if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) { + drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c index 8d2e85081247..3fb0dc1fb910 100644 --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c @@ -77,7 +77,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode) cmd = MI_FLUSH; if (mode & EMIT_INVALIDATE) { cmd |= MI_EXE_FLUSH; - if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) + if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5)) cmd |= MI_INVALIDATE_ISP; } diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c index 487299cb91f2..27ae48049239 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq, *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = lower_32_bits(offset); *cs++ = upper_32_bits(offset); - *cs++ = intel_sseu_make_rpcs(rq->i915, &sseu); + *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu); intel_ring_advance(rq, cs); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c8c14981eb5d..e37490d459c2 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -661,7 +661,6 @@ static int measure_breadcrumb_dw(struct intel_context *ce) if (!frame) return -ENOMEM; - frame->rq.i915 = engine->i915; frame->rq.engine = engine; frame->rq.context = ce; rcu_assign_pointer(frame->rq.timeline, ce->timeline); @@ -1192,8 +1191,7 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine) } } -static int print_sched_attr(struct drm_i915_private *i915, - const struct i915_sched_attr *attr, +static int print_sched_attr(const struct i915_sched_attr *attr, char *buf, int x, int len) { if (attr->priority == I915_PRIORITY_INVALID) @@ -1213,7 +1211,7 @@ static void print_request(struct drm_printer *m, char buf[80] = ""; int x = 0; - x = print_sched_attr(rq->i915, &rq->sched.attr, buf, x, sizeof(buf)); + x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf)); drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n", prefix, diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6fc0966b75ff..aac8da18694f 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3533,7 +3533,7 @@ static int emit_pdps(struct i915_request *rq) int err, i; u32 *cs; - GEM_BUG_ON(intel_vgpu_active(rq->i915)); + GEM_BUG_ON(intel_vgpu_active(rq->engine->i915)); /* * Beware ye of the dragons, this sequence is magic! @@ -4512,11 +4512,11 @@ static int gen8_emit_flush_render(struct i915_request *request, * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL * pipe control. */ - if (IS_GEN(request->i915, 9)) + if (IS_GEN(request->engine->i915, 9)) vf_flush_wa = true; /* WaForGAMHang:kbl */ - if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) + if (IS_KBL_REVID(request->engine->i915, 0, KBL_REVID_B0)) dc_flush_wa = true; } diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index d9c1701061b9..68a08486fc87 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -645,8 +645,8 @@ static inline int mi_set_context(struct i915_request *rq, struct intel_context *ce, u32 flags) { - struct drm_i915_private *i915 = rq->i915; struct intel_engine_cs *engine = rq->engine; + struct drm_i915_private *i915 = engine->i915; enum intel_engine_id id; const int num_engines = IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; @@ -760,7 +760,7 @@ static inline int mi_set_context(struct i915_request *rq, static int remap_l3_slice(struct i915_request *rq, int slice) { - u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; + u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice]; int i; if (!remap_info) @@ -871,7 +871,7 @@ static int switch_context(struct i915_request *rq) void **residuals = NULL; int ret; - GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); + GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); if (engine->wa_ctx.vma && ce != engine->kernel_context) { if (engine->wa_ctx.vma->private != ce) { diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 94d66a9d760d..9ae903f1ab57 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1728,7 +1728,7 @@ wa_list_srm(struct i915_request *rq, const struct i915_wa_list *wal, struct i915_vma *vma) { - struct drm_i915_private *i915 = rq->i915; + struct drm_i915_private *i915 = rq->engine->i915; unsigned int i, count = 0; const struct i915_wa *wa; u32 srm, *cs; @@ -1817,7 +1817,7 @@ static int engine_wa_list_verify(struct intel_context *ce, err = 0; for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { - if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) + if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg))) continue; if (!wa_verify(wa, results[i], wal->name, from)) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c index f88e445a1cae..729c3c7b11e2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c @@ -49,7 +49,7 @@ static int write_timestamp(struct i915_request *rq, int slot) return PTR_ERR(cs); cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT; - if (INTEL_GEN(rq->i915) >= 8) + if (INTEL_GEN(rq->engine->i915) >= 8) cmd++; *cs++ = cmd; *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base)); diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index 8831ffee2061..7bae64018ad9 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -143,7 +143,7 @@ static int read_mocs_table(struct i915_request *rq, { u32 addr; - if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915)) + if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) addr = global_mocs_offset(); else addr = mocs_offset(rq->engine); diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 2dc460624bbc..3c8434846fa1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -132,7 +132,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce) } cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT; - if (INTEL_GEN(rq->i915) >= 8) + if (INTEL_GEN(rq->engine->i915) >= 8) cmd++; *cs++ = cmd; @@ -197,10 +197,10 @@ int live_rc6_ctx_wa(void *arg) int pass; for (pass = 0; pass < 2; pass++) { + struct i915_gpu_error *error = >->i915->gpu_error; struct intel_context *ce; unsigned int resets = - i915_reset_engine_count(>->i915->gpu_error, - engine); + i915_reset_engine_count(error, engine); const u32 *res; /* Use a sacrifical context */ @@ -230,8 +230,7 @@ int live_rc6_ctx_wa(void *arg) engine->name, READ_ONCE(*res)); if (resets != - i915_reset_engine_count(>->i915->gpu_error, - engine)) { + i915_reset_engine_count(error, engine)) { pr_err("%s: GPU reset required\n", engine->name); add_taint_for_CI(TAINT_WARN); diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index ef1c35073dc0..b2aad7ef046a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -426,12 +426,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value) if (IS_ERR(cs)) return PTR_ERR(cs); - if (INTEL_GEN(rq->i915) >= 8) { + if (INTEL_GEN(rq->engine->i915) >= 8) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = addr; *cs++ = 0; *cs++ = value; - } else if (INTEL_GEN(rq->i915) >= 4) { + } else if (INTEL_GEN(rq->engine->i915) >= 4) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = 0; *cs++ = addr; diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 0fb1df71c637..8fc2ad4517e9 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -348,7 +348,7 @@ static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload) u32 *cs; int err; - if (IS_GEN(req->i915, 9) && is_inhibit_context(req->context)) + if (IS_GEN(req->engine->i915, 9) && is_inhibit_context(req->context)) intel_vgpu_restore_inhibit_context(vgpu, req); /* @@ -939,7 +939,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload) context_page_num = rq->engine->context_size; context_page_num = context_page_num >> PAGE_SHIFT; - if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0) + if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0) context_page_num = 19; context_base = (void *) ctx->lrc_reg_state - diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index c5d7220de529..3bb7320249ae 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -56,7 +56,7 @@ static struct i915_global_request { static const char *i915_fence_get_driver_name(struct dma_fence *fence) { - return dev_name(to_request(fence)->i915->drm.dev); + return dev_name(to_request(fence)->engine->i915->drm.dev); } static const char *i915_fence_get_timeline_name(struct dma_fence *fence) @@ -812,7 +812,6 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp) } } - rq->i915 = ce->engine->i915; rq->context = ce; rq->engine = ce->engine; rq->ring = ce->ring; @@ -1011,12 +1010,12 @@ __emit_semaphore_wait(struct i915_request *to, struct i915_request *from, u32 seqno) { - const int has_token = INTEL_GEN(to->i915) >= 12; + const int has_token = INTEL_GEN(to->engine->i915) >= 12; u32 hwsp_offset; int len, err; u32 *cs; - GEM_BUG_ON(INTEL_GEN(to->i915) < 8); + GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8); GEM_BUG_ON(i915_request_has_initial_breadcrumb(to)); /* We need to pin the signaler's HWSP until we are finished reading. */ @@ -1211,7 +1210,7 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) { mark_external(rq); return i915_sw_fence_await_dma_fence(&rq->submit, fence, - i915_fence_context_timeout(rq->i915, + i915_fence_context_timeout(rq->engine->i915, fence->context), I915_FENCE_GFP); } @@ -1782,7 +1781,8 @@ long i915_request_wait(struct i915_request *rq, * (bad for battery). */ if (flags & I915_WAIT_PRIORITY) { - if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6) + if (!i915_request_started(rq) && + INTEL_GEN(rq->engine->i915) >= 6) intel_rps_boost(rq); } diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index 5d4709a3dace..118ab6650d1f 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -162,9 +162,6 @@ struct i915_request { struct dma_fence fence; spinlock_t lock; - /** On Which ring this request was generated */ - struct drm_i915_private *i915; - /** * Context and ring buffer related to this request * Contexts are refcounted, so when this request is associated with a diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index bc854ad60954..a4addcc64978 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -735,7 +735,7 @@ TRACE_EVENT(i915_request_queue, ), TP_fast_assign( - __entry->dev = rq->i915->drm.primary->index; + __entry->dev = rq->engine->i915->drm.primary->index; __entry->class = rq->engine->uabi_class; __entry->instance = rq->engine->uabi_instance; __entry->ctx = rq->fence.context; @@ -761,7 +761,7 @@ DECLARE_EVENT_CLASS(i915_request, ), TP_fast_assign( - __entry->dev = rq->i915->drm.primary->index; + __entry->dev = rq->engine->i915->drm.primary->index; __entry->class = rq->engine->uabi_class; __entry->instance = rq->engine->uabi_instance; __entry->ctx = rq->fence.context; @@ -804,7 +804,7 @@ TRACE_EVENT(i915_request_in, ), TP_fast_assign( - __entry->dev = rq->i915->drm.primary->index; + __entry->dev = rq->engine->i915->drm.primary->index; __entry->class = rq->engine->uabi_class; __entry->instance = rq->engine->uabi_instance; __entry->ctx = rq->fence.context; @@ -833,7 +833,7 @@ TRACE_EVENT(i915_request_out, ), TP_fast_assign( - __entry->dev = rq->i915->drm.primary->index; + __entry->dev = rq->engine->i915->drm.primary->index; __entry->class = rq->engine->uabi_class; __entry->instance = rq->engine->uabi_instance; __entry->ctx = rq->fence.context; @@ -895,7 +895,7 @@ TRACE_EVENT(i915_request_wait_begin, * less desirable. */ TP_fast_assign( - __entry->dev = rq->i915->drm.primary->index; + __entry->dev = rq->engine->i915->drm.primary->index; __entry->class = rq->engine->uabi_class; __entry->instance = rq->engine->uabi_instance; __entry->ctx = rq->fence.context; diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c index 8eb3108f1767..be54570c407c 100644 --- a/drivers/gpu/drm/i915/selftests/i915_perf.c +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c @@ -162,7 +162,7 @@ static int write_timestamp(struct i915_request *rq, int slot) return PTR_ERR(cs); len = 5; - if (INTEL_GEN(rq->i915) >= 8) + if (INTEL_GEN(rq->engine->i915) >= 8) len++; *cs++ = GFX_OP_PIPE_CONTROL(len); diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c index e35ba5f9e73f..699bfe0328fb 100644 --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c @@ -134,15 +134,15 @@ igt_spinner_create_request(struct igt_spinner *spin, batch = spin->batch; - if (INTEL_GEN(rq->i915) >= 8) { + if (INTEL_GEN(rq->engine->i915) >= 8) { *batch++ = MI_STORE_DWORD_IMM_GEN4; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = upper_32_bits(hws_address(hws, rq)); - } else if (INTEL_GEN(rq->i915) >= 6) { + } else if (INTEL_GEN(rq->engine->i915) >= 6) { *batch++ = MI_STORE_DWORD_IMM_GEN4; *batch++ = 0; *batch++ = hws_address(hws, rq); - } else if (INTEL_GEN(rq->i915) >= 4) { + } else if (INTEL_GEN(rq->engine->i915) >= 4) { *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *batch++ = 0; *batch++ = hws_address(hws, rq); @@ -154,11 +154,11 @@ igt_spinner_create_request(struct igt_spinner *spin, *batch++ = arbitration_command; - if (INTEL_GEN(rq->i915) >= 8) + if (INTEL_GEN(rq->engine->i915) >= 8) *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1; - else if (IS_HASWELL(rq->i915)) + else if (IS_HASWELL(rq->engine->i915)) *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW; - else if (INTEL_GEN(rq->i915) >= 6) + else if (INTEL_GEN(rq->engine->i915) >= 6) *batch++ = MI_BATCH_BUFFER_START; else *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; @@ -176,7 +176,7 @@ igt_spinner_create_request(struct igt_spinner *spin, } flags = 0; - if (INTEL_GEN(rq->i915) <= 5) + if (INTEL_GEN(rq->engine->i915) <= 5) flags |= I915_DISPATCH_SECURE; err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); -- 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 2 22:41:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 22:41:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Drop_i915=5Frequest=2Ei915_backpointer?= In-Reply-To: <20200602220953.21178-1-chris@chris-wilson.co.uk> References: <20200602220953.21178-1-chris@chris-wilson.co.uk> Message-ID: <159113766771.21427.8138184145532724653@emeril.freedesktop.org> == Series Details == Series: drm/i915: Drop i915_request.i915 backpointer URL : https://patchwork.freedesktop.org/series/77936/ State : success == Summary == CI Bug Log - changes from CI_DRM_8573 -> Patchwork_17848 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/index.html Known issues ------------ Here are the changes found in Patchwork_17848 that come from known issues: ### IGT changes ### #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][1] ([fdo#109271]) -> [FAIL][2] ([i915#62] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17848 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17848: d2ad01d6c2e69f34b4b905ce168aae955b948d12 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d2ad01d6c2e6 drm/i915: Drop i915_request.i915 backpointer == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/index.html From patchwork at emeril.freedesktop.org Tue Jun 2 23:05:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 02 Jun 2020 23:05:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_fix_i915=2Ereset_module_param_type?= In-Reply-To: <20200602151126.25626-1-jani.nikula@intel.com> References: <20200602151126.25626-1-jani.nikula@intel.com> Message-ID: <159113910202.21427.18350801214152988482@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: fix i915.reset module param type URL : https://patchwork.freedesktop.org/series/77923/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8572_full -> Patchwork_17844_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17844_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17844_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17844_full: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - shard-hsw: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-hsw8/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17844_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#1119] / [i915#118] / [i915#95]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-glk1/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][6] -> [FAIL][7] ([i915#1188]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][10] -> [FAIL][11] ([fdo#108145] / [i915#265]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109441]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-iclb5/igt at kms_psr@psr2_cursor_plane_onoff.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-apl: [FAIL][14] ([i915#1930]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl2/igt at gem_exec_reloc@basic-concurrent0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_workarounds@suspend-resume-fd: - shard-apl: [INCOMPLETE][16] -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl7/igt at gem_workarounds@suspend-resume-fd.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl1/igt at gem_workarounds@suspend-resume-fd.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][18] ([i915#1436] / [i915#716]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-skl3/igt at gen9_exec_parse@allowed-single.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-skl4/igt at gen9_exec_parse@allowed-single.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-hsw: [WARN][20] ([i915#1519]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-hsw6/igt at i915_pm_rc6_residency@rc6-idle.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-hsw6/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [FAIL][22] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-glk9/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [INCOMPLETE][24] ([i915#1926] / [i915#61]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-hsw8/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-hsw8/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][26] ([i915#180]) -> [PASS][27] +2 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html - shard-apl: [DMESG-WARN][28] ([i915#180]) -> [PASS][29] +3 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][30] ([i915#180] / [i915#93] / [i915#95]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html - shard-apl: [DMESG-WARN][32] ([i915#180] / [i915#95]) -> [PASS][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl1/igt at kms_frontbuffer_tracking@fbc-suspend.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl2/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][34] ([i915#1188]) -> [PASS][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][36] ([fdo#108145] / [i915#265]) -> [PASS][37] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-iclb: [FAIL][38] -> [PASS][39] [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-iclb1/igt at kms_plane_multiple@atomic-pipe-b-tiling-none.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-iclb8/igt at kms_plane_multiple@atomic-pipe-b-tiling-none.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][40] ([fdo#109441]) -> [PASS][41] +3 similar issues [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-iclb3/igt at kms_psr@psr2_primary_mmap_cpu.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html #### Warnings #### * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][42] ([i915#1515]) -> [FAIL][43] ([i915#1515]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-iclb2/igt at i915_pm_rc6_residency@rc6-idle.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-iclb5/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][44] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][45] ([i915#1319] / [i915#1635]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl7/igt at kms_content_protection@atomic-dpms.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][46] ([i915#1319] / [i915#1635]) -> [TIMEOUT][47] ([i915#1319]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl1/igt at kms_content_protection@srm.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl1/igt at kms_content_protection@srm.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][48] ([i915#1925] / [i915#1926]) -> [DMESG-WARN][49] ([i915#1926]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-glk4/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-WARN][50] ([i915#1926]) -> [DMESG-FAIL][51] ([i915#1925] / [i915#1926]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-glk4/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][52] ([i915#1525] / [i915#95]) -> [FAIL][53] ([i915#1525]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8572/shard-apl1/igt at kms_fbcon_fbt@fbc.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/shard-apl2/igt at kms_fbcon_fbt@fbc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8572 -> Patchwork_17844 CI-20190529: 20190529 CI_DRM_8572: 8a7011d0518058c59f13f10af147d1f97b0a1cd0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17844: b693251369b3179f16a1789d74a0d7395ef3a7a8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17844/index.html From sfr at canb.auug.org.au Tue Jun 2 23:08:16 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Wed, 3 Jun 2020 09:08:16 +1000 Subject: [Intel-gfx] linux-next: manual merge of the drm-intel-fixes tree with Linus' tree Message-ID: <20200603090816.6437acec@canb.auug.org.au> Hi all, Today's linux-next merge of the drm-intel-fixes tree got a conflict in: drivers/gpu/drm/i915/gt/intel_lrc.c between commit: f53ae29c0ea1 ("drm/i915/gt: Include a few tracek for timeslicing") from Linus' tree and commit: 00febf644648 ("drm/i915/gt: Incorporate the virtual engine into timeslicing") from the drm-intel-fixes tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell diff --cc drivers/gpu/drm/i915/gt/intel_lrc.c index 87e6c5bdd2dc,e77f89b43e5f..000000000000 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@@ -1971,20 -1853,12 +1990,19 @@@ static void set_timeslice(struct intel_ if (!intel_engine_has_timeslices(engine)) return; - set_timer_ms(&engine->execlists.timer, active_timeslice(engine)); + duration = active_timeslice(engine); + ENGINE_TRACE(engine, "bump timeslicing, interval:%lu", duration); + + set_timer_ms(&engine->execlists.timer, duration); } - static void start_timeslice(struct intel_engine_cs *engine) + static void start_timeslice(struct intel_engine_cs *engine, int prio) { struct intel_engine_execlists *execlists = &engine->execlists; - const int prio = queue_prio(execlists); + unsigned long duration; + + if (!intel_engine_has_timeslices(engine)) + return; WRITE_ONCE(execlists->switch_priority_hint, prio); if (prio == INT_MIN) @@@ -2140,13 -1994,8 +2158,13 @@@ static void execlists_dequeue(struct in __unwind_incomplete_requests(engine); last = NULL; - } else if (need_timeslice(engine, last) && + } else if (need_timeslice(engine, last, rb) && timeslice_expired(execlists, last)) { + if (i915_request_completed(last)) { + tasklet_hi_schedule(&execlists->tasklet); + return; + } + ENGINE_TRACE(engine, "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n", last->fence.context, -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: From laurent.pinchart at ideasonboard.com Wed Jun 3 00:19:00 2020 From: laurent.pinchart at ideasonboard.com (Laurent Pinchart) Date: Wed, 3 Jun 2020 03:19:00 +0300 Subject: [Intel-gfx] [PATCH 1/3] drm/atomic-helper: reset vblank on crtc reset In-Reply-To: <20200602095140.36678-1-daniel.vetter@ffwll.ch> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> Message-ID: <20200603001900.GV6547@pendragon.ideasonboard.com> Hi Daniel, Thank you for the patch. May I remind you about the -v option to git-format-patch ? :-) Seriously speaking, it really helps review. On Tue, Jun 02, 2020 at 11:51:38AM +0200, Daniel Vetter wrote: > Only when vblanks are supported ofc. > > Some drivers do this already, but most unfortunately missed it. This > opens up bugs after driver load, before the crtc is enabled for the > first time. syzbot spotted this when loading vkms as a secondary > output. Given how many drivers are buggy it's best to solve this once > and for all in shared helper code. > > Aside from moving the few existing calls to drm_crtc_vblank_reset into > helpers (i915 doesn't use helpers, so keeps its own) I think the > regression risk is minimal: atomic helpers already rely on drivers > calling drm_crtc_vblank_on/off correctly in their hooks when they > support vblanks. And driver that's failing to handle vblanks after > this is missing those calls already, and vblanks could only work by > accident when enabling a CRTC for the first time right after boot. > > Big thanks to Tetsuo for helping track down what's going wrong here. > > There's only a few drivers which already had the necessary call and > needed some updating: > - komeda, atmel and tidss also needed to be changed to call > __drm_atomic_helper_crtc_reset() intead of open coding it > - tegra and msm even had it in the same place already, just code > motion, and malidp already uses __drm_atomic_helper_crtc_reset(). > > Only call left is in i915, which doesn't use drm_mode_config_reset, > but has its own fastboot infrastructure. So that's the only case where > we actually want this in the driver still. > > I've also reviewed all other drivers which set up vblank support with > drm_vblank_init. After the previous patch fixing mxsfb all atomic > drivers do call drm_crtc_vblank_on/off as they should, the remaining > drivers are either legacy kms or legacy dri1 drivers, so not affected > by this change to atomic helpers. > > v2: Use the drm_dev_has_vblank() helper. > > v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off > instead of drm_crtc_vblank_reset. Adjust them too. > > Cc: Laurent Pinchart > Reviewed-by: Laurent Pinchart > Reviewed-by: Boris Brezillon > Acked-by: Liviu Dudau > Acked-by: Thierry Reding > Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb > Reported-by: Tetsuo Handa > Reported-by: syzbot+0871b14ca2e2fb64f6e3 at syzkaller.appspotmail.com > Cc: Tetsuo Handa > Cc: "James (Qian) Wang" > Cc: Liviu Dudau > Cc: Mihail Atanassov > Cc: Brian Starkey > Cc: Sam Ravnborg > Cc: Boris Brezillon > Cc: Nicolas Ferre > Cc: Alexandre Belloni > Cc: Ludovic Desroches > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Thomas Zimmermann > Cc: David Airlie > Cc: Daniel Vetter > Cc: Thierry Reding > Cc: Jonathan Hunter > Cc: Jyri Sarha > Cc: Tomi Valkeinen > Cc: Rob Clark > Cc: Sean Paul > Cc: Brian Masney > Cc: Emil Velikov > Cc: zhengbin > Cc: Thomas Gleixner > Cc: linux-tegra at vger.kernel.org > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++----- > drivers/gpu/drm/arm/malidp_drv.c | 1 - > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 ++----- > drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ > drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 -- > drivers/gpu/drm/omapdrm/omap_drv.c | 3 --- > drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 --- > drivers/gpu/drm/tegra/dc.c | 1 - > drivers/gpu/drm/tidss/tidss_crtc.c | 3 +-- > drivers/gpu/drm/tidss/tidss_kms.c | 4 ---- > 10 files changed, 9 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > index 56bd938961ee..f33418d6e1a0 100644 > --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > @@ -492,10 +492,8 @@ static void komeda_crtc_reset(struct drm_crtc *crtc) > crtc->state = NULL; > > state = kzalloc(sizeof(*state), GFP_KERNEL); > - if (state) { > - crtc->state = &state->base; > - crtc->state->crtc = crtc; > - } > + if (state) > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > } > > static struct drm_crtc_state * > @@ -616,7 +614,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, > return err; > > drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); > - drm_crtc_vblank_reset(crtc); > > crtc->port = kcrtc->master->of_output_port; > > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > index c2507b7d8512..02904392e370 100644 > --- a/drivers/gpu/drm/arm/malidp_drv.c > +++ b/drivers/gpu/drm/arm/malidp_drv.c > @@ -870,7 +870,6 @@ static int malidp_bind(struct device *dev) > drm->irq_enabled = true; > > ret = drm_vblank_init(drm, drm->mode_config.num_crtc); > - drm_crtc_vblank_reset(&malidp->crtc); > if (ret < 0) { > DRM_ERROR("failed to initialise vblank\n"); > goto vblank_fail; > diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > index 10985134ce0b..ce246b96330b 100644 > --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > @@ -411,10 +411,8 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) > } > > state = kzalloc(sizeof(*state), GFP_KERNEL); > - if (state) { > - crtc->state = &state->base; > - crtc->state->crtc = crtc; > - } > + if (state) > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > } > > static struct drm_crtc_state * > @@ -528,7 +526,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) > } > > drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); > - drm_crtc_vblank_reset(&crtc->base); > > drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); > drm_crtc_enable_color_mgmt(&crtc->base, 0, false, > diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c > index 8fce6a115dfe..9ad74045158e 100644 > --- a/drivers/gpu/drm/drm_atomic_state_helper.c > +++ b/drivers/gpu/drm/drm_atomic_state_helper.c > @@ -32,6 +32,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -93,6 +94,9 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, > if (crtc_state) > __drm_atomic_helper_crtc_state_reset(crtc_state, crtc); > > + if (drm_dev_has_vblank(crtc->dev)) > + drm_crtc_vblank_reset(crtc); > + > crtc->state = crtc_state; > } > EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > index ca3368c828d0..9606185c284b 100644 > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > @@ -1117,8 +1117,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc) > mdp5_crtc_destroy_state(crtc, crtc->state); > > __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); > - > - drm_crtc_vblank_reset(crtc); > } > > static const struct drm_crtc_funcs mdp5_crtc_funcs = { > diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c > index 242d28281784..7a7066cded79 100644 > --- a/drivers/gpu/drm/omapdrm/omap_drv.c > +++ b/drivers/gpu/drm/omapdrm/omap_drv.c > @@ -642,9 +642,6 @@ static int omapdrm_init(struct omap_drm_private *priv, struct device *dev) > goto err_cleanup_modeset; > } > > - for (i = 0; i < priv->num_pipes; i++) > - drm_crtc_vblank_off(priv->pipes[i].crtc); > - > omap_fbdev_init(ddev); > > drm_kms_helper_poll_init(ddev); > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > index d73e88ddecd0..e2959e32fd19 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > @@ -1271,9 +1271,6 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, > > drm_crtc_helper_add(crtc, &crtc_helper_funcs); > > - /* Start with vertical blanking interrupt reporting disabled. */ > - drm_crtc_vblank_off(crtc); > - I'm sure I've added this code for a good reason, I would have sworn that vblank would be either broken or would complain very loudly without this call. I've however tested this patch, and haven't noticed any regression. Has something changed since I've added the call to drm_crtc_vblank_off() in the rcar-du driver ? It can't be __drm_atomic_helper_crtc_reset() handling it, as the rcar-du driver has a custom CRTC reset handler that doesn't call __drm_atomic_helper_crtc_reset(). If it works without calling drm_crtc_vblank_off() or drm_crtc_vblank_reset(), what's the purpose of drm_crtc_vblank_reset() ? /me is very puzzled > /* Register the interrupt handler. */ > if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { > /* The IRQ's are associated with the CRTC (sw)index. */ > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > index 83f31c6e891c..9b308b572eac 100644 > --- a/drivers/gpu/drm/tegra/dc.c > +++ b/drivers/gpu/drm/tegra/dc.c > @@ -1168,7 +1168,6 @@ static void tegra_crtc_reset(struct drm_crtc *crtc) > tegra_crtc_atomic_destroy_state(crtc, crtc->state); > > __drm_atomic_helper_crtc_reset(crtc, &state->base); > - drm_crtc_vblank_reset(crtc); > } > > static struct drm_crtc_state * > diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c > index 89a226912de8..4d01c4af61cd 100644 > --- a/drivers/gpu/drm/tidss/tidss_crtc.c > +++ b/drivers/gpu/drm/tidss/tidss_crtc.c > @@ -352,8 +352,7 @@ static void tidss_crtc_reset(struct drm_crtc *crtc) > return; > } > > - crtc->state = &tcrtc->base; > - crtc->state->crtc = crtc; > + __drm_atomic_helper_crtc_reset(crtc, &tcrtc->base); > } > > static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) > diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c > index 4b99e9fa84a5..e6ab59eed259 100644 > --- a/drivers/gpu/drm/tidss/tidss_kms.c > +++ b/drivers/gpu/drm/tidss/tidss_kms.c > @@ -278,10 +278,6 @@ int tidss_modeset_init(struct tidss_device *tidss) > if (ret) > return ret; > > - /* Start with vertical blanking interrupt reporting disabled. */ > - for (i = 0; i < tidss->num_crtcs; ++i) > - drm_crtc_vblank_reset(tidss->crtcs[i]); > - > drm_mode_config_reset(ddev); > > dev_dbg(tidss->dev, "%s done\n", __func__); -- Regards, Laurent Pinchart From patchwork at emeril.freedesktop.org Wed Jun 3 00:35:16 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 00:35:16 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915=3A_Identify_Cometlake_plat?= =?utf-8?q?form_=28rev2=29?= In-Reply-To: <20200602140541.5481-1-chris@chris-wilson.co.uk> References: <20200602140541.5481-1-chris@chris-wilson.co.uk> Message-ID: <159114451620.12266.12507283067683035355@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Identify Cometlake platform (rev2) URL : https://patchwork.freedesktop.org/series/77922/ State : success == Summary == CI Bug Log - changes from CI_DRM_8573_full -> Patchwork_17845_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17845_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#70] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl2/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl7/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#1188]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_hdr@bpc-switch.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-skl10/igt at kms_hdr@bpc-switch.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl9/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-skl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-kbl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_dpms: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at kms_psr@psr2_dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-iclb8/igt at kms_psr@psr2_dpms.html #### Possible fixes #### * {igt at i915_selftest@perf at request}: - shard-tglb: [DMESG-FAIL][15] -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-tglb5/igt at i915_selftest@perf at request.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-tglb1/igt at i915_selftest@perf at request.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [FAIL][17] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-0.html * {igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][19] ([i915#1928]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk2/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-glk4/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][21] ([i915#79]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][23] ([i915#180]) -> [PASS][24] +8 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1}: - shard-skl: [FAIL][25] ([i915#1928]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-skl9/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [INCOMPLETE][27] ([i915#123] / [i915#69]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_frontbuffer_tracking@psr-suspend.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-skl10/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][29] ([fdo#108145] / [i915#265]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb6/igt at kms_psr@psr2_sprite_plane_move.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +3 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@polling-parameterized}: - shard-iclb: [FAIL][35] ([i915#1542]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at perf@polling-parameterized.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-iclb1/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][37] ([i915#658]) -> [SKIP][38] ([i915#588]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb5/igt at i915_pm_dc@dc3co-vpb-simulation.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_rpm@gem-execbuf: - shard-snb: [SKIP][39] ([fdo#109271]) -> [INCOMPLETE][40] ([i915#82]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-snb5/igt at i915_pm_rpm@gem-execbuf.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-snb6/igt at i915_pm_rpm@gem-execbuf.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][41] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][42] ([fdo#110321]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl7/igt at kms_content_protection@atomic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][43] ([i915#1319] / [i915#1635]) -> [FAIL][44] ([fdo#110321] / [fdo#110336]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@atomic-dpms.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl2/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][45] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][46] ([i915#1319] / [i915#1635]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@legacy.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][47] ([i915#1319]) -> [TIMEOUT][48] ([i915#1319] / [i915#1635]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl8/igt at kms_content_protection@lic.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl4/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][49] ([i915#1319] / [i915#1635]) -> [FAIL][50] ([fdo#110321]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl2/igt at kms_content_protection@srm.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl7/igt at kms_content_protection@srm.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][51] ([i915#1525] / [i915#95]) -> [FAIL][52] ([i915#1525]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl7/igt at kms_fbcon_fbt@fbc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-apl8/igt at kms_fbcon_fbt@fbc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][53] ([fdo#109642] / [fdo#111068]) -> [FAIL][54] ([i915#608]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb5/igt at kms_psr2_su@page_flip.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/shard-iclb2/igt at kms_psr2_su@page_flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17845 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17845: 444c42325fd7dc34d47e11e6a4d63d10e0cabc29 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17845/index.html From akeem.g.abodunrin at intel.com Wed Jun 3 00:47:20 2020 From: akeem.g.abodunrin at intel.com (Abodunrin, Akeem G) Date: Wed, 3 Jun 2020 00:47:20 +0000 Subject: [Intel-gfx] [PATCH] drm/i915: Drop i915_request.i915 backpointer In-Reply-To: <20200602220953.21178-1-chris@chris-wilson.co.uk> References: <20200602220953.21178-1-chris@chris-wilson.co.uk> Message-ID: > -----Original Message----- > From: Intel-gfx On Behalf Of Chris > Wilson > Sent: Tuesday, June 02, 2020 3:10 PM > To: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson > Subject: [Intel-gfx] [PATCH] drm/i915: Drop i915_request.i915 backpointer > > We infrequently use the direct i915 backpointer from the i915_request, so do > we really need to waste the space in the struct for it? 8 bytes from the most > frequently allocated struct vs an 3 bytes and pointer chasing in using rq- > >engine->i915? > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 ++---- > drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++--- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 6 +++--- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++-- > drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- > drivers/gpu/drm/i915/gt/selftest_rc6.c | 9 ++++----- > drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++-- > drivers/gpu/drm/i915/gvt/scheduler.c | 4 ++-- > drivers/gpu/drm/i915/i915_request.c | 12 ++++++------ > drivers/gpu/drm/i915/i915_request.h | 3 --- > drivers/gpu/drm/i915/i915_trace.h | 10 +++++----- > drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +- > drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++------- > 17 files changed, 43 insertions(+), 49 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 219a36995b96..02a5c0ce39ca 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -1910,8 +1910,8 @@ static int i915_reset_gen7_sol_offsets(struct > i915_request *rq) > u32 *cs; > int i; > > - if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) { > - drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n"); > + if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) { > + drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs > only\n"); > return -EINVAL; > } > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > index 8d2e85081247..3fb0dc1fb910 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > @@ -77,7 +77,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 > mode) > cmd = MI_FLUSH; > if (mode & EMIT_INVALIDATE) { > cmd |= MI_EXE_FLUSH; > - if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) > + if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5)) > cmd |= MI_INVALIDATE_ISP; > } > > diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c > b/drivers/gpu/drm/i915/gt/intel_context_sseu.c > index 487299cb91f2..27ae48049239 100644 > --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c > @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request > *rq, > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > *cs++ = lower_32_bits(offset); > *cs++ = upper_32_bits(offset); > - *cs++ = intel_sseu_make_rpcs(rq->i915, &sseu); > + *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu); > > intel_ring_advance(rq, cs); > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index c8c14981eb5d..e37490d459c2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -661,7 +661,6 @@ static int measure_breadcrumb_dw(struct > intel_context *ce) > if (!frame) > return -ENOMEM; > > - frame->rq.i915 = engine->i915; > frame->rq.engine = engine; > frame->rq.context = ce; > rcu_assign_pointer(frame->rq.timeline, ce->timeline); @@ -1192,8 > +1191,7 @@ bool intel_engine_can_store_dword(struct intel_engine_cs > *engine) > } > } > > -static int print_sched_attr(struct drm_i915_private *i915, > - const struct i915_sched_attr *attr, > +static int print_sched_attr(const struct i915_sched_attr *attr, > char *buf, int x, int len) > { > if (attr->priority == I915_PRIORITY_INVALID) @@ -1213,7 +1211,7 > @@ static void print_request(struct drm_printer *m, > char buf[80] = ""; > int x = 0; > > - x = print_sched_attr(rq->i915, &rq->sched.attr, buf, x, sizeof(buf)); > + x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf)); > > drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n", > prefix, > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 6fc0966b75ff..aac8da18694f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -3533,7 +3533,7 @@ static int emit_pdps(struct i915_request *rq) > int err, i; > u32 *cs; > > - GEM_BUG_ON(intel_vgpu_active(rq->i915)); > + GEM_BUG_ON(intel_vgpu_active(rq->engine->i915)); > > /* > * Beware ye of the dragons, this sequence is magic! > @@ -4512,11 +4512,11 @@ static int gen8_emit_flush_render(struct > i915_request *request, > * On GEN9: before VF_CACHE_INVALIDATE we need to emit > a NULL > * pipe control. > */ > - if (IS_GEN(request->i915, 9)) > + if (IS_GEN(request->engine->i915, 9)) > vf_flush_wa = true; > > /* WaForGAMHang:kbl */ > - if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) > + if (IS_KBL_REVID(request->engine->i915, 0, KBL_REVID_B0)) > dc_flush_wa = true; > } > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index d9c1701061b9..68a08486fc87 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -645,8 +645,8 @@ static inline int mi_set_context(struct i915_request > *rq, > struct intel_context *ce, > u32 flags) > { > - struct drm_i915_private *i915 = rq->i915; > struct intel_engine_cs *engine = rq->engine; > + struct drm_i915_private *i915 = engine->i915; > enum intel_engine_id id; > const int num_engines = > IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : > 0; @@ -760,7 +760,7 @@ static inline int mi_set_context(struct i915_request > *rq, > > static int remap_l3_slice(struct i915_request *rq, int slice) { > - u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; > + u32 *cs, *remap_info = rq->engine->i915- > >l3_parity.remap_info[slice]; > int i; > > if (!remap_info) > @@ -871,7 +871,7 @@ static int switch_context(struct i915_request *rq) > void **residuals = NULL; > int ret; > > - GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); > + GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); > > if (engine->wa_ctx.vma && ce != engine->kernel_context) { > if (engine->wa_ctx.vma->private != ce) { diff --git > a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 94d66a9d760d..9ae903f1ab57 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1728,7 +1728,7 @@ wa_list_srm(struct i915_request *rq, > const struct i915_wa_list *wal, > struct i915_vma *vma) > { > - struct drm_i915_private *i915 = rq->i915; > + struct drm_i915_private *i915 = rq->engine->i915; > unsigned int i, count = 0; > const struct i915_wa *wa; > u32 srm, *cs; > @@ -1817,7 +1817,7 @@ static int engine_wa_list_verify(struct intel_context > *ce, > > err = 0; > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { > - if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg))) > + if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa- > >reg))) > continue; > > if (!wa_verify(wa, results[i], wal->name, from)) diff --git > a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c > b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c > index f88e445a1cae..729c3c7b11e2 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c > @@ -49,7 +49,7 @@ static int write_timestamp(struct i915_request *rq, int > slot) > return PTR_ERR(cs); > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT; > - if (INTEL_GEN(rq->i915) >= 8) > + if (INTEL_GEN(rq->engine->i915) >= 8) > cmd++; > *cs++ = cmd; > *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine- > >mmio_base)); > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c > b/drivers/gpu/drm/i915/gt/selftest_mocs.c > index 8831ffee2061..7bae64018ad9 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c > @@ -143,7 +143,7 @@ static int read_mocs_table(struct i915_request *rq, { > u32 addr; > > - if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915)) > + if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915)) > addr = global_mocs_offset(); > else > addr = mocs_offset(rq->engine); > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c > b/drivers/gpu/drm/i915/gt/selftest_rc6.c > index 2dc460624bbc..3c8434846fa1 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c > @@ -132,7 +132,7 @@ static const u32 *__live_rc6_ctx(struct intel_context > *ce) > } > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT; > - if (INTEL_GEN(rq->i915) >= 8) > + if (INTEL_GEN(rq->engine->i915) >= 8) > cmd++; > > *cs++ = cmd; > @@ -197,10 +197,10 @@ int live_rc6_ctx_wa(void *arg) > int pass; > > for (pass = 0; pass < 2; pass++) { > + struct i915_gpu_error *error = >->i915->gpu_error; > struct intel_context *ce; > unsigned int resets = > - i915_reset_engine_count(>->i915- > >gpu_error, > - engine); > + i915_reset_engine_count(error, engine); > const u32 *res; > > /* Use a sacrifical context */ > @@ -230,8 +230,7 @@ int live_rc6_ctx_wa(void *arg) > engine->name, READ_ONCE(*res)); > > if (resets != > - i915_reset_engine_count(>->i915->gpu_error, > - engine)) { > + i915_reset_engine_count(error, engine)) { > pr_err("%s: GPU reset required\n", > engine->name); > add_taint_for_CI(TAINT_WARN); > diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c > b/drivers/gpu/drm/i915/gt/selftest_timeline.c > index ef1c35073dc0..b2aad7ef046a 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c > +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c > @@ -426,12 +426,12 @@ static int emit_ggtt_store_dw(struct i915_request > *rq, u32 addr, u32 value) > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - if (INTEL_GEN(rq->i915) >= 8) { > + if (INTEL_GEN(rq->engine->i915) >= 8) { > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > *cs++ = addr; > *cs++ = 0; > *cs++ = value; > - } else if (INTEL_GEN(rq->i915) >= 4) { > + } else if (INTEL_GEN(rq->engine->i915) >= 4) { > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > *cs++ = 0; > *cs++ = addr; > diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c > b/drivers/gpu/drm/i915/gvt/scheduler.c > index 0fb1df71c637..8fc2ad4517e9 100644 > --- a/drivers/gpu/drm/i915/gvt/scheduler.c > +++ b/drivers/gpu/drm/i915/gvt/scheduler.c > @@ -348,7 +348,7 @@ static int copy_workload_to_ring_buffer(struct > intel_vgpu_workload *workload) > u32 *cs; > int err; > > - if (IS_GEN(req->i915, 9) && is_inhibit_context(req->context)) > + if (IS_GEN(req->engine->i915, 9) && is_inhibit_context(req->context)) > intel_vgpu_restore_inhibit_context(vgpu, req); > > /* > @@ -939,7 +939,7 @@ static void update_guest_context(struct > intel_vgpu_workload *workload) > context_page_num = rq->engine->context_size; > context_page_num = context_page_num >> PAGE_SHIFT; > > - if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0) > + if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0) > context_page_num = 19; > > context_base = (void *) ctx->lrc_reg_state - diff --git > a/drivers/gpu/drm/i915/i915_request.c > b/drivers/gpu/drm/i915/i915_request.c > index c5d7220de529..3bb7320249ae 100644 > --- a/drivers/gpu/drm/i915/i915_request.c > +++ b/drivers/gpu/drm/i915/i915_request.c > @@ -56,7 +56,7 @@ static struct i915_global_request { > > static const char *i915_fence_get_driver_name(struct dma_fence *fence) { > - return dev_name(to_request(fence)->i915->drm.dev); > + return dev_name(to_request(fence)->engine->i915->drm.dev); > } > > static const char *i915_fence_get_timeline_name(struct dma_fence *fence) > @@ -812,7 +812,6 @@ __i915_request_create(struct intel_context *ce, gfp_t > gfp) > } > } > > - rq->i915 = ce->engine->i915; > rq->context = ce; > rq->engine = ce->engine; > rq->ring = ce->ring; > @@ -1011,12 +1010,12 @@ __emit_semaphore_wait(struct i915_request > *to, > struct i915_request *from, > u32 seqno) > { > - const int has_token = INTEL_GEN(to->i915) >= 12; > + const int has_token = INTEL_GEN(to->engine->i915) >= 12; > u32 hwsp_offset; > int len, err; > u32 *cs; > > - GEM_BUG_ON(INTEL_GEN(to->i915) < 8); > + GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8); > GEM_BUG_ON(i915_request_has_initial_breadcrumb(to)); > > /* We need to pin the signaler's HWSP until we are finished reading. > */ @@ -1211,7 +1210,7 @@ __i915_request_await_external(struct > i915_request *rq, struct dma_fence *fence) { > mark_external(rq); > return i915_sw_fence_await_dma_fence(&rq->submit, fence, > - i915_fence_context_timeout(rq- > >i915, > + i915_fence_context_timeout(rq- > >engine->i915, > fence- > >context), > I915_FENCE_GFP); > } > @@ -1782,7 +1781,8 @@ long i915_request_wait(struct i915_request *rq, > * (bad for battery). > */ > if (flags & I915_WAIT_PRIORITY) { > - if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6) > + if (!i915_request_started(rq) && > + INTEL_GEN(rq->engine->i915) >= 6) > intel_rps_boost(rq); > } > > diff --git a/drivers/gpu/drm/i915/i915_request.h > b/drivers/gpu/drm/i915/i915_request.h > index 5d4709a3dace..118ab6650d1f 100644 > --- a/drivers/gpu/drm/i915/i915_request.h > +++ b/drivers/gpu/drm/i915/i915_request.h > @@ -162,9 +162,6 @@ struct i915_request { > struct dma_fence fence; > spinlock_t lock; > > - /** On Which ring this request was generated */ > - struct drm_i915_private *i915; > - > /** > * Context and ring buffer related to this request > * Contexts are refcounted, so when this request is associated with a > diff --git a/drivers/gpu/drm/i915/i915_trace.h > b/drivers/gpu/drm/i915/i915_trace.h > index bc854ad60954..a4addcc64978 100644 > --- a/drivers/gpu/drm/i915/i915_trace.h > +++ b/drivers/gpu/drm/i915/i915_trace.h > @@ -735,7 +735,7 @@ TRACE_EVENT(i915_request_queue, > ), > > TP_fast_assign( > - __entry->dev = rq->i915->drm.primary->index; > + __entry->dev = rq->engine->i915->drm.primary- > >index; > __entry->class = rq->engine->uabi_class; > __entry->instance = rq->engine->uabi_instance; > __entry->ctx = rq->fence.context; @@ -761,7 > +761,7 @@ DECLARE_EVENT_CLASS(i915_request, > ), > > TP_fast_assign( > - __entry->dev = rq->i915->drm.primary->index; > + __entry->dev = rq->engine->i915->drm.primary- > >index; > __entry->class = rq->engine->uabi_class; > __entry->instance = rq->engine->uabi_instance; > __entry->ctx = rq->fence.context; @@ -804,7 > +804,7 @@ TRACE_EVENT(i915_request_in, > ), > > TP_fast_assign( > - __entry->dev = rq->i915->drm.primary->index; > + __entry->dev = rq->engine->i915->drm.primary- > >index; > __entry->class = rq->engine->uabi_class; > __entry->instance = rq->engine->uabi_instance; > __entry->ctx = rq->fence.context; @@ -833,7 > +833,7 @@ TRACE_EVENT(i915_request_out, > ), > > TP_fast_assign( > - __entry->dev = rq->i915->drm.primary->index; > + __entry->dev = rq->engine->i915->drm.primary- > >index; > __entry->class = rq->engine->uabi_class; > __entry->instance = rq->engine->uabi_instance; > __entry->ctx = rq->fence.context; @@ -895,7 > +895,7 @@ TRACE_EVENT(i915_request_wait_begin, > * less desirable. > */ > TP_fast_assign( > - __entry->dev = rq->i915->drm.primary->index; > + __entry->dev = rq->engine->i915->drm.primary- > >index; > __entry->class = rq->engine->uabi_class; > __entry->instance = rq->engine->uabi_instance; > __entry->ctx = rq->fence.context; diff --git > a/drivers/gpu/drm/i915/selftests/i915_perf.c > b/drivers/gpu/drm/i915/selftests/i915_perf.c > index 8eb3108f1767..be54570c407c 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_perf.c > +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c > @@ -162,7 +162,7 @@ static int write_timestamp(struct i915_request *rq, > int slot) > return PTR_ERR(cs); > > len = 5; > - if (INTEL_GEN(rq->i915) >= 8) > + if (INTEL_GEN(rq->engine->i915) >= 8) > len++; > > *cs++ = GFX_OP_PIPE_CONTROL(len); > diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c > b/drivers/gpu/drm/i915/selftests/igt_spinner.c > index e35ba5f9e73f..699bfe0328fb 100644 > --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c > +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c > @@ -134,15 +134,15 @@ igt_spinner_create_request(struct igt_spinner > *spin, > > batch = spin->batch; > > - if (INTEL_GEN(rq->i915) >= 8) { > + if (INTEL_GEN(rq->engine->i915) >= 8) { > *batch++ = MI_STORE_DWORD_IMM_GEN4; > *batch++ = lower_32_bits(hws_address(hws, rq)); > *batch++ = upper_32_bits(hws_address(hws, rq)); > - } else if (INTEL_GEN(rq->i915) >= 6) { > + } else if (INTEL_GEN(rq->engine->i915) >= 6) { > *batch++ = MI_STORE_DWORD_IMM_GEN4; > *batch++ = 0; > *batch++ = hws_address(hws, rq); > - } else if (INTEL_GEN(rq->i915) >= 4) { > + } else if (INTEL_GEN(rq->engine->i915) >= 4) { > *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > *batch++ = 0; > *batch++ = hws_address(hws, rq); > @@ -154,11 +154,11 @@ igt_spinner_create_request(struct igt_spinner > *spin, > > *batch++ = arbitration_command; > > - if (INTEL_GEN(rq->i915) >= 8) > + if (INTEL_GEN(rq->engine->i915) >= 8) > *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1; > - else if (IS_HASWELL(rq->i915)) > + else if (IS_HASWELL(rq->engine->i915)) > *batch++ = MI_BATCH_BUFFER_START | > MI_BATCH_PPGTT_HSW; > - else if (INTEL_GEN(rq->i915) >= 6) > + else if (INTEL_GEN(rq->engine->i915) >= 6) > *batch++ = MI_BATCH_BUFFER_START; > else > *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; > @@ -176,7 +176,7 @@ igt_spinner_create_request(struct igt_spinner *spin, > } > > flags = 0; > - if (INTEL_GEN(rq->i915) <= 5) > + if (INTEL_GEN(rq->engine->i915) <= 5) > flags |= I915_DISPATCH_SECURE; > err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); > Good concepts! Reviewed-by: Akeem G Abodunrin > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Wed Jun 3 04:28:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 04:28:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Implement_WA=5F16011163337?= In-Reply-To: <20200602192501.5446-1-clinton.a.taylor@intel.com> References: <20200602192501.5446-1-clinton.a.taylor@intel.com> Message-ID: <159115851922.12265.9499488037199771510@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Implement WA_16011163337 URL : https://patchwork.freedesktop.org/series/77933/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8573_full -> Patchwork_17846_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17846_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17846_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17846_full: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - shard-hsw: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-hsw6/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17846_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gen9_exec_parse@allowed-all: - shard-glk: [PASS][2] -> [DMESG-WARN][3] ([i915#1436] / [i915#716]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk1/igt at gen9_exec_parse@allowed-all.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-glk5/igt at gen9_exec_parse@allowed-all.html * igt at i915_pm_dc@dc5-dpms: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#198]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at i915_pm_dc@dc5-dpms.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-skl4/igt at i915_pm_dc@dc5-dpms.html * igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-kbl: [PASS][6] -> [FAIL][7] ([i915#54] / [i915#93] / [i915#95]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html * igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [PASS][8] -> [INCOMPLETE][9] ([i915#1926] / [i915#61]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-hsw4/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-hsw1/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-kbl: [PASS][10] -> [DMESG-WARN][11] ([i915#128]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl2/igt at kms_cursor_legacy@pipe-c-torture-bo.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-kbl7/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][12] -> [FAIL][13] ([i915#1188]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +4 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][16] -> [FAIL][17] ([i915#173]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at kms_psr@no_drrs.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_dpms: - shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#109441]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at kms_psr@psr2_dpms.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-iclb6/igt at kms_psr@psr2_dpms.html #### Possible fixes #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: - shard-skl: [FAIL][20] ([i915#1528]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-skl5/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html * {igt at i915_selftest@perf at request}: - shard-tglb: [DMESG-FAIL][22] -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-tglb5/igt at i915_selftest@perf at request.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-tglb8/igt at i915_selftest@perf at request.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [FAIL][24] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-0.html * {igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][26] ([i915#1928]) -> [PASS][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk2/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-glk9/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][28] ([i915#79]) -> [PASS][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-apl: [DMESG-WARN][30] ([i915#180]) -> [PASS][31] +7 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1}: - shard-skl: [FAIL][32] ([i915#1928]) -> [PASS][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [INCOMPLETE][34] ([i915#123] / [i915#69]) -> [PASS][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_frontbuffer_tracking@psr-suspend.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-skl8/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][36] ([fdo#109441]) -> [PASS][37] +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb3/igt at kms_psr@psr2_suspend.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][38] ([i915#180]) -> [PASS][39] +2 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@polling-parameterized}: - shard-iclb: [FAIL][40] ([i915#1542]) -> [PASS][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at perf@polling-parameterized.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-iclb1/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][42] ([i915#1899]) -> [SKIP][43] ([i915#468]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-tglb1/igt at i915_pm_dc@dc6-psr.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_chamelium@hdmi-audio-edid: - shard-hsw: [SKIP][44] ([fdo#109271] / [fdo#111827]) -> [SKIP][45] ([fdo#109271] / [fdo#111827] / [i915#1927]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-hsw1/igt at kms_chamelium@hdmi-audio-edid.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-hsw6/igt at kms_chamelium@hdmi-audio-edid.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][46] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][47] ([i915#1319] / [i915#1635]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@legacy.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-apl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][48] ([i915#1319]) -> [FAIL][49] ([fdo#110321]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl8/igt at kms_content_protection@lic.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-FAIL][50] ([i915#1925] / [i915#1926]) -> [DMESG-WARN][51] ([i915#1926]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk1/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/shard-glk5/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17846 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17846: fd295d4b23d0b98f18f5be0f265d525bb3f9ebce @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17846/index.html From patchwork at emeril.freedesktop.org Wed Jun 3 05:55:01 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 05:55:01 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Add_HBR_and_HBR2+_voltage_swing_table?= In-Reply-To: <20200602205424.138143-1-jose.souza@intel.com> References: <20200602205424.138143-1-jose.souza@intel.com> Message-ID: <159116370185.12267.4347121232376396516@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Add HBR and HBR2+ voltage swing table URL : https://patchwork.freedesktop.org/series/77934/ State : success == Summary == CI Bug Log - changes from CI_DRM_8573_full -> Patchwork_17847_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17847_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl3/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html * igt at i915_pm_rpm@system-suspend-execbuf: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#1185] / [i915#189]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb4/igt at i915_pm_rpm@system-suspend-execbuf.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb4/igt at i915_pm_rpm@system-suspend-execbuf.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl3/igt at i915_suspend@forcewake.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-kbl4/igt at i915_suspend@forcewake.html * igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#54] / [i915#93] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#70] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl2/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl8/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#1525] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl6/igt at kms_fbcon_fbt@fbc-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl2/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_hdr@bpc-switch.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl8/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_dpms: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at kms_psr@psr2_dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb7/igt at kms_psr@psr2_dpms.html #### Possible fixes #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: - shard-skl: [FAIL][21] ([i915#1528]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl3/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html * {igt at i915_selftest@perf at request}: - shard-tglb: [DMESG-FAIL][23] ([i915#1823]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-tglb5/igt at i915_selftest@perf at request.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-tglb3/igt at i915_selftest@perf at request.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [FAIL][25] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-FAIL][27] ([i915#1925] / [i915#1926]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk1/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-glk5/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * {igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][29] ([i915#1928]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk2/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-glk8/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][31] ([i915#79]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +8 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl7/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1}: - shard-skl: [FAIL][35] ([i915#1928]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [INCOMPLETE][37] ([i915#123] / [i915#69]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_frontbuffer_tracking@psr-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl8/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][39] ([fdo#108145] / [i915#265]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb3/igt at kms_psr@psr2_suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@polling-parameterized}: - shard-iclb: [FAIL][45] ([i915#1542]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at perf@polling-parameterized.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb6/igt at perf@polling-parameterized.html #### Warnings #### * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][47] ([i915#1319] / [i915#1635]) -> [FAIL][48] ([fdo#110321] / [fdo#110336]) +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@atomic-dpms.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319] / [i915#1635]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@legacy.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl1/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][51] ([i915#1319]) -> [TIMEOUT][52] ([i915#1319] / [i915#1635]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl8/igt at kms_content_protection@lic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl4/igt at kms_content_protection@lic.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][53] ([i915#1525] / [i915#95]) -> [FAIL][54] ([i915#1525]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl7/igt at kms_fbcon_fbt@fbc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl8/igt at kms_fbcon_fbt@fbc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17847 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17847: 6c49c456cc63e42fd77667b19ef3e88780a047dc @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/index.html From patchwork at emeril.freedesktop.org Wed Jun 3 06:02:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 06:02:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Drop_i915=5Frequest=2Ei915_backpointer?= In-Reply-To: <20200602220953.21178-1-chris@chris-wilson.co.uk> References: <20200602220953.21178-1-chris@chris-wilson.co.uk> Message-ID: <159116416929.12266.7667979651431237508@emeril.freedesktop.org> == Series Details == Series: drm/i915: Drop i915_request.i915 backpointer URL : https://patchwork.freedesktop.org/series/77936/ State : success == Summary == CI Bug Log - changes from CI_DRM_8573_full -> Patchwork_17848_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17848_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at sysfs_heartbeat_interval@nopreempt at vecs0}: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk5/igt at sysfs_heartbeat_interval@nopreempt at vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-glk2/igt at sysfs_heartbeat_interval@nopreempt at vecs0.html Known issues ------------ Here are the changes found in Patchwork_17848_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_workarounds@suspend-resume-context: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-apl1/igt at gem_workarounds@suspend-resume-context.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl3/igt at i915_suspend@forcewake.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-kbl4/igt at i915_suspend@forcewake.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#1119] / [i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk4/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#49]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_dpms: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at kms_psr@psr2_dpms.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-iclb5/igt at kms_psr@psr2_dpms.html #### Possible fixes #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: - shard-skl: [FAIL][17] ([i915#1528]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl9/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-apl: [FAIL][19] ([i915#1930]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl8/igt at gem_exec_reloc@basic-concurrent0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-apl6/igt at gem_exec_reloc@basic-concurrent0.html * {igt at i915_selftest@perf at request}: - shard-tglb: [DMESG-FAIL][21] ([i915#1823]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-tglb5/igt at i915_selftest@perf at request.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-tglb2/igt at i915_selftest@perf at request.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [FAIL][23] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][25] ([i915#1925] / [i915#1926]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk8/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-glk5/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * {igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][27] ([i915#1928]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk2/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-glk5/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][29] ([i915#79]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@flip-vs-suspend at a-dp1}: - shard-apl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +4 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl6/igt at kms_flip@flip-vs-suspend at a-dp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-apl1/igt at kms_flip@flip-vs-suspend at a-dp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1}: - shard-skl: [FAIL][33] ([i915#1928]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl4/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [INCOMPLETE][35] ([i915#123] / [i915#69]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_frontbuffer_tracking@psr-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl1/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][37] ([fdo#108145] / [i915#265]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb3/igt at kms_psr@psr2_suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][41] ([i915#31]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl4/igt at kms_setmode@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-kbl1/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +3 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@polling-parameterized}: - shard-iclb: [FAIL][45] ([i915#1542]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at perf@polling-parameterized.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-iclb6/igt at perf@polling-parameterized.html #### Warnings #### * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][47] ([i915#1319] / [i915#1635]) -> [FAIL][48] ([fdo#110321] / [fdo#110336]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@atomic-dpms.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-apl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319] / [i915#1635]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@legacy.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-apl1/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][51] ([i915#1319]) -> [TIMEOUT][52] ([i915#1319] / [i915#1635]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl8/igt at kms_content_protection@lic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/shard-apl6/igt at kms_content_protection@lic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8573 -> Patchwork_17848 CI-20190529: 20190529 CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17848: d2ad01d6c2e69f34b4b905ce168aae955b948d12 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17848/index.html From daniel.vetter at ffwll.ch Wed Jun 3 07:55:12 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Wed, 3 Jun 2020 09:55:12 +0200 Subject: [Intel-gfx] [PATCH 1/3] drm/atomic-helper: reset vblank on crtc reset In-Reply-To: <20200603001900.GV6547@pendragon.ideasonboard.com> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> <20200603001900.GV6547@pendragon.ideasonboard.com> Message-ID: On Wed, Jun 3, 2020 at 2:19 AM Laurent Pinchart wrote: > > Hi Daniel, > > Thank you for the patch. > > May I remind you about the -v option to git-format-patch ? :-) Seriously > speaking, it really helps review. > > On Tue, Jun 02, 2020 at 11:51:38AM +0200, Daniel Vetter wrote: > > Only when vblanks are supported ofc. > > > > Some drivers do this already, but most unfortunately missed it. This > > opens up bugs after driver load, before the crtc is enabled for the > > first time. syzbot spotted this when loading vkms as a secondary > > output. Given how many drivers are buggy it's best to solve this once > > and for all in shared helper code. > > > > Aside from moving the few existing calls to drm_crtc_vblank_reset into > > helpers (i915 doesn't use helpers, so keeps its own) I think the > > regression risk is minimal: atomic helpers already rely on drivers > > calling drm_crtc_vblank_on/off correctly in their hooks when they > > support vblanks. And driver that's failing to handle vblanks after > > this is missing those calls already, and vblanks could only work by > > accident when enabling a CRTC for the first time right after boot. > > > > Big thanks to Tetsuo for helping track down what's going wrong here. > > > > There's only a few drivers which already had the necessary call and > > needed some updating: > > - komeda, atmel and tidss also needed to be changed to call > > __drm_atomic_helper_crtc_reset() intead of open coding it > > - tegra and msm even had it in the same place already, just code > > motion, and malidp already uses __drm_atomic_helper_crtc_reset(). > > > > Only call left is in i915, which doesn't use drm_mode_config_reset, > > but has its own fastboot infrastructure. So that's the only case where > > we actually want this in the driver still. > > > > I've also reviewed all other drivers which set up vblank support with > > drm_vblank_init. After the previous patch fixing mxsfb all atomic > > drivers do call drm_crtc_vblank_on/off as they should, the remaining > > drivers are either legacy kms or legacy dri1 drivers, so not affected > > by this change to atomic helpers. > > > > v2: Use the drm_dev_has_vblank() helper. > > > > v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off > > instead of drm_crtc_vblank_reset. Adjust them too. > > > > Cc: Laurent Pinchart > > Reviewed-by: Laurent Pinchart > > Reviewed-by: Boris Brezillon > > Acked-by: Liviu Dudau > > Acked-by: Thierry Reding > > Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb > > Reported-by: Tetsuo Handa > > Reported-by: syzbot+0871b14ca2e2fb64f6e3 at syzkaller.appspotmail.com > > Cc: Tetsuo Handa > > Cc: "James (Qian) Wang" > > Cc: Liviu Dudau > > Cc: Mihail Atanassov > > Cc: Brian Starkey > > Cc: Sam Ravnborg > > Cc: Boris Brezillon > > Cc: Nicolas Ferre > > Cc: Alexandre Belloni > > Cc: Ludovic Desroches > > Cc: Maarten Lankhorst > > Cc: Maxime Ripard > > Cc: Thomas Zimmermann > > Cc: David Airlie > > Cc: Daniel Vetter > > Cc: Thierry Reding > > Cc: Jonathan Hunter > > Cc: Jyri Sarha > > Cc: Tomi Valkeinen > > Cc: Rob Clark > > Cc: Sean Paul > > Cc: Brian Masney > > Cc: Emil Velikov > > Cc: zhengbin > > Cc: Thomas Gleixner > > Cc: linux-tegra at vger.kernel.org > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++----- > > drivers/gpu/drm/arm/malidp_drv.c | 1 - > > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 ++----- > > drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ > > drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 -- > > drivers/gpu/drm/omapdrm/omap_drv.c | 3 --- > > drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 --- > > drivers/gpu/drm/tegra/dc.c | 1 - > > drivers/gpu/drm/tidss/tidss_crtc.c | 3 +-- > > drivers/gpu/drm/tidss/tidss_kms.c | 4 ---- > > 10 files changed, 9 insertions(+), 26 deletions(-) > > > > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > > index 56bd938961ee..f33418d6e1a0 100644 > > --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c > > @@ -492,10 +492,8 @@ static void komeda_crtc_reset(struct drm_crtc *crtc) > > crtc->state = NULL; > > > > state = kzalloc(sizeof(*state), GFP_KERNEL); > > - if (state) { > > - crtc->state = &state->base; > > - crtc->state->crtc = crtc; > > - } > > + if (state) > > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > > } > > > > static struct drm_crtc_state * > > @@ -616,7 +614,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, > > return err; > > > > drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); > > - drm_crtc_vblank_reset(crtc); > > > > crtc->port = kcrtc->master->of_output_port; > > > > diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c > > index c2507b7d8512..02904392e370 100644 > > --- a/drivers/gpu/drm/arm/malidp_drv.c > > +++ b/drivers/gpu/drm/arm/malidp_drv.c > > @@ -870,7 +870,6 @@ static int malidp_bind(struct device *dev) > > drm->irq_enabled = true; > > > > ret = drm_vblank_init(drm, drm->mode_config.num_crtc); > > - drm_crtc_vblank_reset(&malidp->crtc); > > if (ret < 0) { > > DRM_ERROR("failed to initialise vblank\n"); > > goto vblank_fail; > > diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > > index 10985134ce0b..ce246b96330b 100644 > > --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > > +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c > > @@ -411,10 +411,8 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) > > } > > > > state = kzalloc(sizeof(*state), GFP_KERNEL); > > - if (state) { > > - crtc->state = &state->base; > > - crtc->state->crtc = crtc; > > - } > > + if (state) > > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > > } > > > > static struct drm_crtc_state * > > @@ -528,7 +526,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) > > } > > > > drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); > > - drm_crtc_vblank_reset(&crtc->base); > > > > drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); > > drm_crtc_enable_color_mgmt(&crtc->base, 0, false, > > diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c > > index 8fce6a115dfe..9ad74045158e 100644 > > --- a/drivers/gpu/drm/drm_atomic_state_helper.c > > +++ b/drivers/gpu/drm/drm_atomic_state_helper.c > > @@ -32,6 +32,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > #include > > @@ -93,6 +94,9 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, > > if (crtc_state) > > __drm_atomic_helper_crtc_state_reset(crtc_state, crtc); > > > > + if (drm_dev_has_vblank(crtc->dev)) > > + drm_crtc_vblank_reset(crtc); > > + > > crtc->state = crtc_state; > > } > > EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > > index ca3368c828d0..9606185c284b 100644 > > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c > > @@ -1117,8 +1117,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc) > > mdp5_crtc_destroy_state(crtc, crtc->state); > > > > __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); > > - > > - drm_crtc_vblank_reset(crtc); > > } > > > > static const struct drm_crtc_funcs mdp5_crtc_funcs = { > > diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c > > index 242d28281784..7a7066cded79 100644 > > --- a/drivers/gpu/drm/omapdrm/omap_drv.c > > +++ b/drivers/gpu/drm/omapdrm/omap_drv.c > > @@ -642,9 +642,6 @@ static int omapdrm_init(struct omap_drm_private *priv, struct device *dev) > > goto err_cleanup_modeset; > > } > > > > - for (i = 0; i < priv->num_pipes; i++) > > - drm_crtc_vblank_off(priv->pipes[i].crtc); > > - > > omap_fbdev_init(ddev); > > > > drm_kms_helper_poll_init(ddev); > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > > index d73e88ddecd0..e2959e32fd19 100644 > > --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > > +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c > > @@ -1271,9 +1271,6 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, > > > > drm_crtc_helper_add(crtc, &crtc_helper_funcs); > > > > - /* Start with vertical blanking interrupt reporting disabled. */ > > - drm_crtc_vblank_off(crtc); > > - > > I'm sure I've added this code for a good reason, I would have sworn that > vblank would be either broken or would complain very loudly without this > call. I've however tested this patch, and haven't noticed any > regression. Has something changed since I've added the call to > drm_crtc_vblank_off() in the rcar-du driver ? It can't be > __drm_atomic_helper_crtc_reset() handling it, as the rcar-du driver has > a custom CRTC reset handler that doesn't call > __drm_atomic_helper_crtc_reset(). If it works without calling > drm_crtc_vblank_off() or drm_crtc_vblank_reset(), what's the purpose of > drm_crtc_vblank_reset() ? > > /me is very puzzled Uh yeah this breaks stuff, I forgot to review the two drivers I've changed to make sure they're using the __drm_atomic_helper_crtc_reset function. Like they should. I'll respin. -Daniel > > /* Register the interrupt handler. */ > > if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { > > /* The IRQ's are associated with the CRTC (sw)index. */ > > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > > index 83f31c6e891c..9b308b572eac 100644 > > --- a/drivers/gpu/drm/tegra/dc.c > > +++ b/drivers/gpu/drm/tegra/dc.c > > @@ -1168,7 +1168,6 @@ static void tegra_crtc_reset(struct drm_crtc *crtc) > > tegra_crtc_atomic_destroy_state(crtc, crtc->state); > > > > __drm_atomic_helper_crtc_reset(crtc, &state->base); > > - drm_crtc_vblank_reset(crtc); > > } > > > > static struct drm_crtc_state * > > diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c > > index 89a226912de8..4d01c4af61cd 100644 > > --- a/drivers/gpu/drm/tidss/tidss_crtc.c > > +++ b/drivers/gpu/drm/tidss/tidss_crtc.c > > @@ -352,8 +352,7 @@ static void tidss_crtc_reset(struct drm_crtc *crtc) > > return; > > } > > > > - crtc->state = &tcrtc->base; > > - crtc->state->crtc = crtc; > > + __drm_atomic_helper_crtc_reset(crtc, &tcrtc->base); > > } > > > > static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) > > diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c > > index 4b99e9fa84a5..e6ab59eed259 100644 > > --- a/drivers/gpu/drm/tidss/tidss_kms.c > > +++ b/drivers/gpu/drm/tidss/tidss_kms.c > > @@ -278,10 +278,6 @@ int tidss_modeset_init(struct tidss_device *tidss) > > if (ret) > > return ret; > > > > - /* Start with vertical blanking interrupt reporting disabled. */ > > - for (i = 0; i < tidss->num_crtcs; ++i) > > - drm_crtc_vblank_reset(tidss->crtcs[i]); > > - > > drm_mode_config_reset(ddev); > > > > dev_dbg(tidss->dev, "%s done\n", __func__); > > -- > Regards, > > Laurent Pinchart -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From chris at chris-wilson.co.uk Wed Jun 3 08:38:31 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 3 Jun 2020 09:38:31 +0100 Subject: [Intel-gfx] [PATCH i-g-t 2/2] HAX:fair In-Reply-To: <20200603083831.1789770-1-chris@chris-wilson.co.uk> References: <20200603083831.1789770-1-chris@chris-wilson.co.uk> Message-ID: <20200603083831.1789770-2-chris@chris-wilson.co.uk> --- tests/intel-ci/fast-feedback.testlist | 163 +------------------------- 1 file changed, 3 insertions(+), 160 deletions(-) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index 04f6affcf..9cf460894 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -1,162 +1,5 @@ # Keep alphabetically sorted by default -igt at core_auth@basic-auth -igt at debugfs_test@read_all_entries -igt at fbdev@mmap -igt at gem_basic@bad-close -igt at gem_basic@create-close -igt at gem_basic@create-fd-close -igt at gem_busy@busy at all -igt at gem_close_race@basic-process -igt at gem_close_race@basic-threads -igt at gem_ctx_create@basic -igt at gem_ctx_create@basic-files -igt at gem_ctx_exec@basic -igt at gem_exec_basic@basic -igt at gem_exec_create@basic -igt at gem_exec_fence@basic-busy -igt at gem_exec_fence@basic-wait -igt at gem_exec_fence@basic-await -igt at gem_exec_fence@nb-await -igt at gem_exec_gttfill@basic -igt at gem_exec_parallel@engines -igt at gem_exec_store@basic -igt at gem_exec_suspend@basic-s0 -igt at gem_exec_suspend@basic-s3 -igt at gem_flink_basic@bad-flink -igt at gem_flink_basic@bad-open -igt at gem_flink_basic@basic -igt at gem_flink_basic@double-flink -igt at gem_flink_basic@flink-lifetime -igt at gem_linear_blits@basic -igt at gem_mmap@basic -igt at gem_mmap_gtt@basic -igt at gem_render_linear_blits@basic -igt at gem_render_tiled_blits@basic -igt at gem_ringfill@basic-all -igt at gem_sync@basic-all -igt at gem_sync@basic-each -igt at gem_tiled_blits@basic -igt at gem_tiled_fence_blits@basic -igt at gem_tiled_pread_basic -igt at gem_wait@busy at all -igt at gem_wait@wait at all -igt at i915_getparams_basic@basic-eu-total -igt at i915_getparams_basic@basic-subslice-total -igt at i915_hangman@error-state-basic -igt at kms_addfb_basic@addfb25-bad-modifier -igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling -igt at kms_addfb_basic@addfb25-modifier-no-flag -igt at kms_addfb_basic@addfb25-x-tiled -igt at kms_addfb_basic@addfb25-x-tiled-mismatch -igt at kms_addfb_basic@addfb25-yf-tiled -igt at kms_addfb_basic@addfb25-y-tiled -igt at kms_addfb_basic@addfb25-y-tiled-small -igt at kms_addfb_basic@bad-pitch-0 -igt at kms_addfb_basic@bad-pitch-1024 -igt at kms_addfb_basic@bad-pitch-128 -igt at kms_addfb_basic@bad-pitch-256 -igt at kms_addfb_basic@bad-pitch-32 -igt at kms_addfb_basic@bad-pitch-63 -igt at kms_addfb_basic@bad-pitch-65536 -igt at kms_addfb_basic@bad-pitch-999 -igt at kms_addfb_basic@basic -igt at kms_addfb_basic@basic-x-tiled -igt at kms_addfb_basic@basic-y-tiled -igt at kms_addfb_basic@bo-too-small -igt at kms_addfb_basic@bo-too-small-due-to-tiling -igt at kms_addfb_basic@clobberred-modifier -igt at kms_addfb_basic@framebuffer-vs-set-tiling -igt at kms_addfb_basic@invalid-get-prop -igt at kms_addfb_basic@invalid-get-prop-any -igt at kms_addfb_basic@invalid-set-prop -igt at kms_addfb_basic@invalid-set-prop-any -igt at kms_addfb_basic@no-handle -igt at kms_addfb_basic@size-max -igt at kms_addfb_basic@small-bo -igt at kms_addfb_basic@tile-pitch-mismatch -igt at kms_addfb_basic@too-high -igt at kms_addfb_basic@too-wide -igt at kms_addfb_basic@unused-handle -igt at kms_addfb_basic@unused-modifier -igt at kms_addfb_basic@unused-offsets -igt at kms_addfb_basic@unused-pitches -igt at kms_busy@basic -igt at kms_chamelium@dp-hpd-fast -igt at kms_chamelium@dp-edid-read -igt at kms_chamelium@dp-crc-fast -igt at kms_chamelium@hdmi-hpd-fast -igt at kms_chamelium@hdmi-edid-read -igt at kms_chamelium@hdmi-crc-fast -igt at kms_chamelium@vga-hpd-fast -igt at kms_chamelium@vga-edid-read -igt at kms_chamelium@common-hpd-after-suspend -igt at kms_prop_blob@basic -igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic -igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy -igt at kms_cursor_legacy@basic-flip-after-cursor-atomic -igt at kms_cursor_legacy@basic-flip-after-cursor-legacy -igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size -igt at kms_cursor_legacy@basic-flip-before-cursor-atomic -igt at kms_cursor_legacy@basic-flip-before-cursor-legacy -igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size -igt at kms_flip@basic-flip-vs-dpms -igt at kms_flip@basic-flip-vs-modeset -igt at kms_flip@basic-flip-vs-wf_vblank -igt at kms_flip@basic-plain-flip -igt at kms_force_connector_basic@force-connector-state -igt at kms_force_connector_basic@force-edid -igt at kms_force_connector_basic@force-load-detect -igt at kms_force_connector_basic@prune-stale-modes -igt at kms_frontbuffer_tracking@basic -igt at kms_pipe_crc_basic@hang-read-crc-pipe-a -igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a -igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence -igt at kms_pipe_crc_basic@read-crc-pipe-a -igt at kms_pipe_crc_basic@read-crc-pipe-b -igt at kms_pipe_crc_basic@read-crc-pipe-c -igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence -igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a -igt at kms_psr@primary_page_flip -igt at kms_psr@cursor_plane_move -igt at kms_psr@sprite_plane_onoff -igt at kms_psr@primary_mmap_gtt -igt at kms_setmode@basic-clone-single-crtc -igt at i915_pm_backlight@basic-brightness -igt at i915_pm_rpm@basic-pci-d3-state -igt at i915_pm_rpm@basic-rte -igt at i915_pm_rps@basic-api -igt at prime_self_import@basic-llseek-bad -igt at prime_self_import@basic-llseek-size -igt at prime_self_import@basic-with_fd_dup -igt at prime_self_import@basic-with_one_bo -igt at prime_self_import@basic-with_one_bo_two_files -igt at prime_self_import@basic-with_two_bos -igt at prime_vgem@basic-fence-flip -igt at prime_vgem@basic-fence-mmap -igt at prime_vgem@basic-fence-read -igt at prime_vgem@basic-gtt -igt at prime_vgem@basic-read -igt at prime_vgem@basic-write -igt at vgem_basic@setversion -igt at vgem_basic@create -igt at vgem_basic@debugfs -igt at vgem_basic@dmabuf-export -igt at vgem_basic@dmabuf-fence -igt at vgem_basic@dmabuf-fence-before -igt at vgem_basic@dmabuf-mmap -igt at vgem_basic@mmap -igt at vgem_basic@second-client -igt at vgem_basic@sysfs - -# All tests that do module unloading and reloading are executed last. -# They will sometimes reveal issues of earlier tests leaving the -# driver in a broken state that is not otherwise noticed in that test. - -igt at vgem_basic@unload -igt at i915_module_load@reload -igt at i915_pm_rpm@module-reload - -# Kernel selftests -igt at i915_selftest@live -igt at dmabuf@all +igt at gem_exec_schedule@fair-none +igt at gem_exec_schedule@fair-pace +igt at gem_exec_schedule@fair-flow -- 2.27.0 From chris at chris-wilson.co.uk Wed Jun 3 08:38:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 3 Jun 2020 09:38:30 +0100 Subject: [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200603083831.1789770-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C --- tests/i915/gem_exec_schedule.c | 484 +++++++++++++++++++++++++++++++++ 1 file changed, 484 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..3483d4b24 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -2495,6 +2495,467 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define RUNTIME (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(START_TS); + + while (offset_in_page(cs) & 63) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + *cs++ = MI_STORE_DWORD_IMM; + if (use_64b) { + *cs++ = addr + 4064; + *cs++ = addr >> 32; + } else { + *cs++ = 0; + *cs++ = addr + 4064; + } + *cs++ = 0; + } + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + int timeline, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +#define F_SPARE (1 << 5) +#define F_NEXT (1 << 6) +#define F_VIP (1 << 7) +#define F_RRUL (1 << 8) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 prev = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 next = + delay_create(i915, ctx, e, frame_ns / batches_per_frame); + struct drm_i915_gem_exec_object2 ts = tslog_create(i915, ctx, e); + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + uint32_t *map; + int n; + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&next), + .buffer_count = 1, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_FLOW) { + unsigned int seq; + + seq = count; + if (flags & F_NEXT) + seq++; + + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, seq); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + + execbuf.buffers_ptr = to_user_pointer(&ts); + execbuf.batch_start_offset = 2048; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + close(execbuf.rsvd2); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + igt_swap(prev, next); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, next.handle); + gem_close(i915, prev.handle); + + gem_sync(i915, ts.handle); + map = gem_mmap__device_coherent(i915, ts.handle, 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + + gem_close(i915, ts.handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int ncpus = sysconf(_SC_NPROCESSORS_ONLN); + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 2 * ncpus; n <<= 1) { + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE)); + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct igt_mean m; + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + if (flags & F_VIP && child == 0) { + gem_context_set_priority(i915, ctx, MAX_PRIO); + flags |= F_FLOW; + } + if (flags & F_RRUL && child == 0) + flags |= F_SOLO | F_FLOW | F_SYNC; + + fair_child(i915, ctx, e, child_ns, + timeout, timeline, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) { + struct timespec tv = { .tv_nsec = fence_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); + } + } + igt_waitchildren(); + close(timeline); + + if (flags & (F_VIP | F_RRUL)) { + igt_info("VIP interval %.2f ms\n", 1e-6 * result[0]); + igt_assert(4 * result[0] > 3 * fence_ns && + 3 * result[0] < 4 * fence_ns); + } + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + + /* Mean within 25% of target */ + igt_assert(4 * igt_mean_get(&m) > 3 * fence_ns && + 3 * igt_mean_get(&m) < 4 * fence_ns); + +#if 0 + /* Variance [inter-quartile range] is less than 33% of median */ + igt_assert(3 * result[hi] - result[lo] < result[nchild / 2]); +#endif + } + + munmap(result, 4096); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +3050,29 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-none-vip", fd, e) + fairness(fd, e, 2, F_VIP); + test_each_engine_store("fair-none-rrul", fd, e) + fairness(fd, e, 2, F_RRUL); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACE); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_SYNC); + test_each_engine_store("fair-sync-vip", fd, e) + fairness(fd, e, 2, F_SYNC | F_VIP); + test_each_engine_store("fair-solo", fd, e) + fairness(fd, e, 2, F_SYNC | F_SOLO); + test_each_engine_store("fair-flow", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW); + test_each_engine_store("fair-next", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_NEXT); + test_each_engine_store("fair-spare", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_SPARE); + test_each_engine_store("fair-half", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_HALF); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0 From ville.syrjala at linux.intel.com Wed Jun 3 10:05:48 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 3 Jun 2020 13:05:48 +0300 Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs In-Reply-To: <20200602122807.GN4452@intel.com> References: <20200601101516.21018-1-anshuman.gupta@intel.com> <20200601141132.GK6112@intel.com> <20200602122807.GN4452@intel.com> Message-ID: <20200603100548.GN6112@intel.com> On Tue, Jun 02, 2020 at 05:58:07PM +0530, Anshuman Gupta wrote: > On 2020-06-01 at 17:11:32 +0300, Ville Syrj?l? wrote: > > On Mon, Jun 01, 2020 at 03:45:16PM +0530, Anshuman Gupta wrote: > > > Gen12 hw are failing to enable lpsp configuration due to PG3 was left on > > > due to valid usgae count of POWER_DOMAIN_AUDIO. > > > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling > > > a crtc, it should be always i915_audio_component request to get/put > > > AUDIO_POWER_DOMAIN. > > > > > > Cc: stable at vger.kernel.org > > > Cc: Ville Syrj?l? > > > Cc: Maarten Lankhorst > > > Signed-off-by: Anshuman Gupta > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- > > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index 6c3b11de2daf..f31a579d7a52 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) > > > mask |= BIT_ULL(intel_encoder->power_domain); > > > } > > > > > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > > > + /* > > > + * Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > > > + * enable AUDIO power in order to enable a crtc > > > > Nothing requires audio power to enable a crtc. What this is saying is > > that if we want audio then we must enable the audio power. If you > > didn't want audio then you wouldn't have .has_audio set. > IMO i915_audio_component_get_power also enables audio power, and > i915_audio_component_put_power releases the usage count based upon audio > runtime idleness but here get_crtc_power_domains() gets the POWER_DOMAIN_AUDIO usages > count, which will be released only when this crtc get disbaled. > It may enable AUDIO power despite of fact that audio driver has released the > usage count. > Please correct me if i am wrong here. The audio component stuff doesn't actually do the audio enable/disable sequence. > > > > > That said, looks like audio is moving into the always on well, but not > > yet in tgl. > Still some of audio functional stuff lies in PG3, not completely removed > from PG3. > Thanks, > Anshuman Gupta. > > > > . > > > + */ > > > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && crtc_state->has_audio) > > > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > > > > > if (crtc_state->shared_dpll) > > > -- > > > 2.26.2 > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From matthew.auld at intel.com Wed Jun 3 10:07:51 2020 From: matthew.auld at intel.com (Matthew Auld) Date: Wed, 3 Jun 2020 11:07:51 +0100 Subject: [Intel-gfx] [PATCH] i915: purge i915_gem_create_v2 Message-ID: <20200603100751.304637-1-matthew.auld@intel.com> The gem_create_v2 uapi was never merged, which would have been a nice addition to allow userspace to utilise stolen memory. Since it can only get in the way at this point, let's just remove it. Signed-off-by: Matthew Auld Cc: Chris Wilson --- lib/ioctl_wrappers.c | 70 ------------------------------- lib/ioctl_wrappers.h | 3 -- tests/i915/gem_create.c | 46 +++----------------- tests/i915/gem_pread.c | 93 ----------------------------------------- tests/i915/gem_pwrite.c | 43 ------------------- 5 files changed, 5 insertions(+), 250 deletions(-) diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c index 61f93bd8..3781286d 100644 --- a/lib/ioctl_wrappers.c +++ b/lib/ioctl_wrappers.c @@ -469,76 +469,6 @@ void gem_sync(int fd, uint32_t handle) errno = 0; } - -bool gem_create__has_stolen_support(int fd) -{ - int has_stolen_support; - struct drm_i915_getparam gp; - int val = -1; - - memset(&gp, 0, sizeof(gp)); - gp.param = 38; /* CREATE_VERSION */ - gp.value = &val; - - /* Do we have the extended gem_create_ioctl? */ - ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp); - has_stolen_support = val >= 2; - - return has_stolen_support; -} - -struct local_i915_gem_create_v2 { - uint64_t size; - uint32_t handle; - uint32_t pad; -#define I915_CREATE_PLACEMENT_STOLEN (1<<0) - uint32_t flags; -}; - -#define LOCAL_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct local_i915_gem_create_v2) -uint32_t __gem_create_stolen(int fd, uint64_t size) -{ - struct local_i915_gem_create_v2 create; - int ret; - - memset(&create, 0, sizeof(create)); - create.handle = 0; - create.size = size; - create.flags = I915_CREATE_PLACEMENT_STOLEN; - ret = igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_CREATE, &create); - - if (ret < 0) - return 0; - - errno = 0; - return create.handle; -} - -/** - * gem_create_stolen: - * @fd: open i915 drm file descriptor - * @size: desired size of the buffer - * - * This wraps the new GEM_CREATE ioctl, which allocates a new gem buffer - * object of @size and placement in stolen memory region. - * - * Returns: The file-private handle of the created buffer object - */ - -uint32_t gem_create_stolen(int fd, uint64_t size) -{ - struct local_i915_gem_create_v2 create; - - memset(&create, 0, sizeof(create)); - create.handle = 0; - create.size = size; - create.flags = I915_CREATE_PLACEMENT_STOLEN; - do_ioctl(fd, LOCAL_IOCTL_I915_GEM_CREATE, &create); - igt_assert(create.handle); - - return create.handle; -} - int __gem_create(int fd, uint64_t size, uint32_t *handle) { struct drm_i915_gem_create create = { diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h index 435fc813..870ac8b7 100644 --- a/lib/ioctl_wrappers.h +++ b/lib/ioctl_wrappers.h @@ -75,9 +75,6 @@ int __gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write); void gem_set_domain(int fd, uint32_t handle, uint32_t read, uint32_t write); int gem_wait(int fd, uint32_t handle, int64_t *timeout_ns); void gem_sync(int fd, uint32_t handle); -bool gem_create__has_stolen_support(int fd); -uint32_t __gem_create_stolen(int fd, uint64_t size); -uint32_t gem_create_stolen(int fd, uint64_t size); int __gem_create(int fd, uint64_t size, uint32_t *handle); uint32_t gem_create(int fd, uint64_t size); void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf); diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c index e376f8ae..c7444d55 100644 --- a/tests/i915/gem_create.c +++ b/tests/i915/gem_create.c @@ -27,11 +27,8 @@ /** @file gem_create.c * - * This is a test for the extended and old gem_create ioctl, that - * includes allocation of object from stolen memory and shmem. - * - * The goal is to simply ensure that basics work and invalid input - * combinations are rejected. + * This is a test for the gem_create ioctl. The goal is to simply ensure that + * basics work and invalid input combinations are rejected. */ #include @@ -59,42 +56,12 @@ #include "i915/gem_mman.h" #include "i915_drm.h" -IGT_TEST_DESCRIPTION("This is a test for the extended & old gem_create ioctl," - " that includes allocation of object from stolen memory" - " and shmem."); +IGT_TEST_DESCRIPTION("This is a test for the gem_create ioctl," + " where the goal is to simply ensure that basics work" + " and invalid input combinations are rejected."); -#define CLEAR(s) memset(&s, 0, sizeof(s)) #define PAGE_SIZE 4096 -struct local_i915_gem_create_v2 { - uint64_t size; - uint32_t handle; - uint32_t pad; -#define I915_CREATE_PLACEMENT_STOLEN (1<<0) - uint32_t flags; -} create_v2; - -#define LOCAL_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct local_i915_gem_create_v2) - -static void invalid_flag_test(int fd) -{ - int ret; - - gem_require_stolen_support(fd); - - create_v2.handle = 0; - create_v2.size = PAGE_SIZE; - create_v2.flags = ~I915_CREATE_PLACEMENT_STOLEN; - ret = drmIoctl(fd, LOCAL_IOCTL_I915_GEM_CREATE, &create_v2); - - igt_assert(ret <= 0); - - create_v2.flags = ~0; - ret = drmIoctl(fd, LOCAL_IOCTL_I915_GEM_CREATE, &create_v2); - - igt_assert(ret <= 0); -} - static int create_ioctl(int fd, struct drm_i915_gem_create *create) { int err = 0; @@ -278,9 +245,6 @@ igt_main fd = drm_open_driver(DRIVER_INTEL); } - igt_subtest("stolen-invalid-flag") - invalid_flag_test(fd); - igt_subtest("create-invalid-size") invalid_size_test(fd); diff --git a/tests/i915/gem_pread.c b/tests/i915/gem_pread.c index 5b926ab0..6d12b8e9 100644 --- a/tests/i915/gem_pread.c +++ b/tests/i915/gem_pread.c @@ -73,7 +73,6 @@ static void pread_self(int i915) } #define OBJECT_SIZE 16384 -#define LARGE_OBJECT_SIZE 1024 * 1024 #define KGRN "\x1B[32m" #define KRED "\x1B[31m" #define KNRM "\x1B[0m" @@ -110,10 +109,7 @@ static const char *bytes_per_sec(char *buf, double v) return buf; } - uint32_t *src, dst; -uint32_t *dst_user, src_stolen, large_stolen; -uint32_t *stolen_pf_user, *stolen_nopf_user; int fd, count; int object_size = 0; @@ -156,8 +152,6 @@ igt_main_args("s:", NULL, help_str, opt_handler, NULL) dst = gem_create(fd, object_size); src = malloc(object_size); - src_stolen = gem_create_stolen(fd, object_size); - dst_user = malloc(object_size); } igt_subtest("bench") { @@ -197,96 +191,9 @@ igt_main_args("s:", NULL, help_str, opt_handler, NULL) } } - igt_subtest("stolen-normal") { - gem_require_stolen_support(fd); - for (count = 1; count <= 1<<17; count <<= 1) { - struct timeval start, end; - - gettimeofday(&start, NULL); - do_gem_read(fd, src_stolen, dst_user, object_size, count); - gettimeofday(&end, NULL); - usecs = elapsed(&start, &end, count); - bps = bytes_per_sec(buf, object_size/usecs*1e6); - igt_info("Time to pread %d bytes x %6d: %7.3f?s, %s\n", - object_size, count, usecs, bps); - fflush(stdout); - } - } - for (c = cache; c->level != -1; c++) { - igt_subtest_f("stolen-%s", c->name) { - gem_require_stolen_support(fd); - gem_set_caching(fd, src_stolen, c->level); - - for (count = 1; count <= 1<<17; count <<= 1) { - struct timeval start, end; - - gettimeofday(&start, NULL); - do_gem_read(fd, src_stolen, dst_user, - object_size, count); - gettimeofday(&end, NULL); - usecs = elapsed(&start, &end, count); - bps = bytes_per_sec(buf, object_size/usecs*1e6); - igt_info("Time to stolen-%s pread %d bytes x %6d: %7.3f?s, %s\n", - c->name, object_size, count, usecs, bps); - fflush(stdout); - } - } - } - - /* List the time taken in pread operation for stolen objects, with - * and without the overhead of page fault handling on accessing the - * user space buffer - */ - igt_subtest("pagefault-pread") { - gem_require_stolen_support(fd); - large_stolen = gem_create_stolen(fd, LARGE_OBJECT_SIZE); - stolen_nopf_user = (uint32_t *) mmap(NULL, LARGE_OBJECT_SIZE, - PROT_WRITE, - MAP_ANONYMOUS|MAP_PRIVATE, - -1, 0); - igt_assert(stolen_nopf_user); - - for (count = 1; count <= 10; count ++) { - struct timeval start, end; - double t_elapsed = 0; - - gettimeofday(&start, NULL); - do_gem_read(fd, large_stolen, stolen_nopf_user, - LARGE_OBJECT_SIZE, 1); - gettimeofday(&end, NULL); - t_elapsed = elapsed(&start, &end, count); - bps = bytes_per_sec(buf, object_size/t_elapsed*1e6); - igt_info("Pagefault-N - Time to pread %d bytes: %7.3f?s, %s\n", - LARGE_OBJECT_SIZE, t_elapsed, bps); - - stolen_pf_user = (uint32_t *) mmap(NULL, LARGE_OBJECT_SIZE, - PROT_WRITE, - MAP_ANONYMOUS|MAP_PRIVATE, - -1, 0); - igt_assert(stolen_pf_user); - - gettimeofday(&start, NULL); - do_gem_read(fd, large_stolen, stolen_pf_user, - LARGE_OBJECT_SIZE, 1); - gettimeofday(&end, NULL); - usecs = elapsed(&start, &end, count); - bps = bytes_per_sec(buf, object_size/usecs*1e6); - igt_info("Pagefault-Y - Time to pread %d bytes: %7.3f?s, %s%s%s\n", - LARGE_OBJECT_SIZE, usecs, - t_elapsed < usecs ? KGRN : KRED, bps, KNRM); - fflush(stdout); - munmap(stolen_pf_user, LARGE_OBJECT_SIZE); - } - munmap(stolen_nopf_user, LARGE_OBJECT_SIZE); - gem_close(fd, large_stolen); - } - - igt_fixture { free(src); gem_close(fd, dst); - free(dst_user); - gem_close(fd, src_stolen); close(fd); } diff --git a/tests/i915/gem_pwrite.c b/tests/i915/gem_pwrite.c index 20e9728b..e491263f 100644 --- a/tests/i915/gem_pwrite.c +++ b/tests/i915/gem_pwrite.c @@ -277,7 +277,6 @@ static void test_random(int fd) } uint32_t *src, dst; -uint32_t *src_user, dst_stolen; int fd; int object_size = 0; @@ -321,8 +320,6 @@ igt_main_args("s:", NULL, help_str, opt_handler, NULL) dst = gem_create(fd, object_size); src = malloc(object_size); - dst_stolen = gem_create_stolen(fd, object_size); - src_user = malloc(object_size); } igt_subtest("bench") { @@ -362,49 +359,9 @@ igt_main_args("s:", NULL, help_str, opt_handler, NULL) } } - igt_subtest("stolen-normal") { - gem_require_stolen_support(fd); - for (count = 1; count <= 1<<17; count <<= 1) { - struct timeval start, end; - - gettimeofday(&start, NULL); - do_gem_write(fd, dst_stolen, src_user, - object_size, count); - gettimeofday(&end, NULL); - usecs = elapsed(&start, &end, count); - bps = bytes_per_sec(buf, object_size/usecs*1e6); - igt_info("Time to pwrite %d bytes x %6d: %7.3f?s, %s\n", - object_size, count, usecs, bps); - fflush(stdout); - } - } - - for (c = cache; c->level != -1; c++) { - igt_subtest_f("stolen-%s", c->name) { - gem_require_stolen_support(fd); - gem_set_caching(fd, dst, c->level); - for (count = 1; count <= 1<<17; count <<= 1) { - struct timeval start, end; - - gettimeofday(&start, NULL); - do_gem_write(fd, dst_stolen, src_user, - object_size, count); - gettimeofday(&end, NULL); - bps = bytes_per_sec(buf, - object_size/usecs*1e6); - igt_info("Time to stolen-%s pwrite %d bytes x %6d: %7.3f?s, %s\n", - c->name, object_size, count, - usecs, bps); - fflush(stdout); - } - } - } - igt_fixture { free(src); gem_close(fd, dst); - free(src_user); - gem_close(fd, dst_stolen); } igt_subtest_f("basic-random") -- 2.26.2 From chris at chris-wilson.co.uk Wed Jun 3 10:11:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 03 Jun 2020 11:11:15 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH] i915: purge i915_gem_create_v2 In-Reply-To: <20200603100751.304637-1-matthew.auld@intel.com> References: <20200603100751.304637-1-matthew.auld@intel.com> Message-ID: <159117907576.25109.10669419078526321419@build.alporthouse.com> Quoting Matthew Auld (2020-06-03 11:07:51) > The gem_create_v2 uapi was never merged, which would have been a nice > addition to allow userspace to utilise stolen memory. Since it can only > get in the way at this point, let's just remove it. Just imagine all the trouble we could have saved had we been doing asynchronous clearing of stolen memory for userspace 5+ years ago :| > Signed-off-by: Matthew Auld > Cc: Chris Wilson Reviewed-by: Chris Wilson -Chris From chris at chris-wilson.co.uk Wed Jun 3 10:46:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 3 Jun 2020 11:46:57 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Suppress the error message for GT init failure on error injection Message-ID: <20200603104657.25651-1-chris@chris-wilson.co.uk> If we injected an error (such as pretending the GuC firmware was broken), then suppress the error message as it is expected and our CI complains if it sees any *ERROR*. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 6bdb434a442d..f1d5333f9456 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -214,8 +214,8 @@ int intel_gt_resume(struct intel_gt *gt) /* Only when the HW is re-initialised, can we replay the requests */ err = intel_gt_init_hw(gt); if (err) { - drm_err(>->i915->drm, - "Failed to initialize GPU, declaring it wedged!\n"); + i915_probe_error(gt->i915, + "Failed to initialize GPU, declaring it wedged!\n"); goto err_wedged; } -- 2.20.1 From matthew.william.auld at gmail.com Wed Jun 3 11:07:11 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Wed, 3 Jun 2020 12:07:11 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Suppress the error message for GT init failure on error injection In-Reply-To: <20200603104657.25651-1-chris@chris-wilson.co.uk> References: <20200603104657.25651-1-chris@chris-wilson.co.uk> Message-ID: On Wed, 3 Jun 2020 at 11:47, Chris Wilson wrote: > > If we injected an error (such as pretending the GuC firmware was > broken), then suppress the error message as it is expected and our CI > complains if it sees any *ERROR*. > > Signed-off-by: Chris Wilson Reviewed-by: Matthew Auld From patchwork at emeril.freedesktop.org Wed Jun 3 11:21:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 11:21:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBp?= =?utf-8?q?915=3A_purge_i915=5Fgem=5Fcreate=5Fv2?= In-Reply-To: <20200603100751.304637-1-matthew.auld@intel.com> References: <20200603100751.304637-1-matthew.auld@intel.com> Message-ID: <159118331259.12266.14381020861835205823@emeril.freedesktop.org> == Series Details == Series: i915: purge i915_gem_create_v2 URL : https://patchwork.freedesktop.org/series/77947/ State : failure == Summary == Applying: i915: purge i915_gem_create_v2 error: sha1 information is lacking or useless (lib/ioctl_wrappers.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 i915: purge i915_gem_create_v2 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Wed Jun 3 11:50:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 11:50:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Suppress_the_error_message_for_GT_init_failure_on_e?= =?utf-8?q?rror_injection?= In-Reply-To: <20200603104657.25651-1-chris@chris-wilson.co.uk> References: <20200603104657.25651-1-chris@chris-wilson.co.uk> Message-ID: <159118502432.12265.1100695372224956185@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Suppress the error message for GT init failure on error injection URL : https://patchwork.freedesktop.org/series/77949/ State : success == Summary == CI Bug Log - changes from CI_DRM_8575 -> Patchwork_17850 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/index.html Known issues ------------ Here are the changes found in Patchwork_17850 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2] ([i915#151] / [i915#1844] / [i915#1909] / [i915#392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-bsw-kefka/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-bsw-kefka/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1372]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][21] ([fdo#109271]) -> [DMESG-FAIL][22] ([i915#62]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92]) -> [DMESG-WARN][26] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1844]: https://gitlab.freedesktop.org/drm/intel/issues/1844 [i915#1909]: https://gitlab.freedesktop.org/drm/intel/issues/1909 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 45) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8575 -> Patchwork_17850 CI-20190529: 20190529 CI_DRM_8575: b261605291bae8f267174f92df7513a3a7184573 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5692: c98c9ad6d06c4eb8b05b23ef0bbe0159730e387f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17850: cde9b765b01965ff9ab1c632022242467263c608 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cde9b765b019 drm/i915/gt: Suppress the error message for GT init failure on error injection == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/index.html From ville.syrjala at linux.intel.com Wed Jun 3 12:42:35 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 3 Jun 2020 15:42:35 +0300 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/display/hsw+: Do not program the same vswing entry twice In-Reply-To: References: <20200528200356.36756-1-jose.souza@intel.com> <20200529065148.GG6112@intel.com> Message-ID: <20200603124235.GP6112@intel.com> On Fri, May 29, 2020 at 08:52:38PM +0000, Souza, Jose wrote: > On Fri, 2020-05-29 at 09:51 +0300, Ville Syrj?l? wrote: > > On Thu, May 28, 2020 at 01:03:53PM -0700, Jos? Roberto de Souza wrote: > > > It will be programed right before the link training, so no need to do > > > it twice. > > > It will not strictly follow BSpec sequences but most of this sequences > > > are not matching anyways. > > > > > > Signed-off-by: Jos? Roberto de Souza > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++--------------- > > > 1 file changed, 4 insertions(+), 15 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index aa22465bb56e..c100efc6a2c4 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -3115,7 +3115,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, > > > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > > > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > > > - int level = intel_ddi_dp_level(intel_dp); > > > enum transcoder transcoder = crtc_state->cpu_transcoder; > > > > > > intel_dp_set_link_params(intel_dp, crtc_state->port_clock, > > > @@ -3190,9 +3189,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, > > > * down this function. > > > */ > > > > > > - /* 7.e Configure voltage swing and related IO settings */ > > > - tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, > > > - encoder->type); > > > + /* > > > + * 7.e Configure voltage swing and related IO settings > > > + * It will be done in intel_dp_start_link_train(), no need to do twice > > > + */ > > > > Hmm. Do we still set it up before turning on the port? > > No. > > intel_dp_start_link_train() > intel_dp_link_training_clock_recovery() > intel_dp->prepare_link_retrain(intel_dp)/intel_ddi_prepare_link_retrain();/* Port is enabled here in training mode */ > > .... > > intel_dp_reset_link_train() > intel_dp_set_signal_levels() /* Vswing table is set here */ > Guess is safer keep programming it twice then? Probably. > > > > > > > > > > /* > > > * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up > > > @@ -3257,7 +3257,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, > > > enum phy phy = intel_port_to_phy(dev_priv, port); > > > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > > > bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); > > > - int level = intel_ddi_dp_level(intel_dp); > > > > > > if (INTEL_GEN(dev_priv) < 11) > > > drm_WARN_ON(&dev_priv->drm, > > > @@ -3279,16 +3278,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, > > > > > > icl_program_mg_dp_mode(dig_port, crtc_state); > > > > > > - if (INTEL_GEN(dev_priv) >= 11) > > > - icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, > > > - level, encoder->type); > > > - else if (IS_CANNONLAKE(dev_priv)) > > > - cnl_ddi_vswing_sequence(encoder, level, encoder->type); > > > - else if (IS_GEN9_LP(dev_priv)) > > > - bxt_ddi_vswing_sequence(encoder, level, encoder->type); > > > - else > > > - intel_prepare_dp_ddi_buffers(encoder, crtc_state); > > > > This last one definitely has to stay IIRC. HSW/BDW/SKL buf trans > > stuff works quite bit differently than the BXT+ style more manual > > programming. > > > > > - > > > if (intel_phy_is_combo(dev_priv, phy)) { > > > bool lane_reversal = > > > dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; > > > -- > > > 2.26.2 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From daniel at ffwll.ch Wed Jun 3 12:57:34 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 3 Jun 2020 14:57:34 +0200 Subject: [Intel-gfx] [PATCH 5/9] drm/udl: Don't call get/put_pages on imported dma-buf In-Reply-To: <20200514124757.GY206103@phenom.ffwll.local> References: <20200511093554.211493-1-daniel.vetter@ffwll.ch> <20200511093554.211493-6-daniel.vetter@ffwll.ch> <1f21209e-c041-7203-af94-5e71d9ee9234@suse.de> <20200514124757.GY206103@phenom.ffwll.local> Message-ID: <20200603125734.GM20149@phenom.ffwll.local> On Thu, May 14, 2020 at 02:47:57PM +0200, Daniel Vetter wrote: > On Thu, May 14, 2020 at 09:25:18AM +0200, Thomas Zimmermann wrote: > > Hi, > > > > given the upcoming removal of this file, I don't know if you really want > > to merge this patch. If so, please see my comment on patch 6 and > > Yeah I can wait for your patch to land, I just looked at that series. I'm > kinda just keeping this around as a reminder locally. Still applied cleanly to drm-misc-next, so I applied it. -Daniel > -Daniel > > > > > Acked-by: Thomas Zimmermann > > > > Am 11.05.20 um 11:35 schrieb Daniel Vetter: > > > There's no direct harm, because for the shmem helpers these are noops > > > on imported buffers. The trouble is in the locks these take - I want > > > to change dma_buf_vmap locking, and so need to make sure that we only > > > ever take certain locks on one side of the dma-buf interface: Either > > > for exporters, or for importers. > > > > > > Signed-off-by: Daniel Vetter > > > Cc: Dave Airlie > > > Cc: Sean Paul > > > Cc: Gerd Hoffmann > > > Cc: Thomas Zimmermann > > > Cc: Alex Deucher > > > Cc: Daniel Vetter > > > Cc: Thomas Gleixner > > > Cc: Sam Ravnborg > > > --- > > > drivers/gpu/drm/udl/udl_gem.c | 22 ++++++++++++---------- > > > 1 file changed, 12 insertions(+), 10 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/udl/udl_gem.c b/drivers/gpu/drm/udl/udl_gem.c > > > index b6e26f98aa0a..c68d3e265329 100644 > > > --- a/drivers/gpu/drm/udl/udl_gem.c > > > +++ b/drivers/gpu/drm/udl/udl_gem.c > > > @@ -46,29 +46,31 @@ static void *udl_gem_object_vmap(struct drm_gem_object *obj) > > > if (shmem->vmap_use_count++ > 0) > > > goto out; > > > > > > - ret = drm_gem_shmem_get_pages(shmem); > > > - if (ret) > > > - goto err_zero_use; > > > - > > > - if (obj->import_attach) > > > + if (obj->import_attach) { > > > shmem->vaddr = dma_buf_vmap(obj->import_attach->dmabuf); > > > - else > > > + } else { > > > + ret = drm_gem_shmem_get_pages(shmem); > > > + if (ret) > > > + goto err; > > > + > > > shmem->vaddr = vmap(shmem->pages, obj->size >> PAGE_SHIFT, > > > VM_MAP, PAGE_KERNEL); > > > > > > + if (!shmem->vaddr) > > > + drm_gem_shmem_put_pages(shmem); > > > + } > > > + > > > if (!shmem->vaddr) { > > > DRM_DEBUG_KMS("Failed to vmap pages\n"); > > > ret = -ENOMEM; > > > - goto err_put_pages; > > > + goto err; > > > } > > > > > > out: > > > mutex_unlock(&shmem->vmap_lock); > > > return shmem->vaddr; > > > > > > -err_put_pages: > > > - drm_gem_shmem_put_pages(shmem); > > > -err_zero_use: > > > +err: > > > shmem->vmap_use_count = 0; > > > mutex_unlock(&shmem->vmap_lock); > > > return ERR_PTR(ret); > > > > > > > -- > > Thomas Zimmermann > > Graphics Driver Developer > > SUSE Software Solutions Germany GmbH > > Maxfeldstr. 5, 90409 N?rnberg, Germany > > (HRB 36809, AG N?rnberg) > > Gesch?ftsf?hrer: Felix Imend?rffer > > > > > > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From daniel at ffwll.ch Wed Jun 3 13:12:09 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 3 Jun 2020 15:12:09 +0200 Subject: [Intel-gfx] [PATCH 8/9] drm/shmem-helpers: Ensure get_pages is not called on imported dma-buf In-Reply-To: <41b3f24c-de0c-9390-6b8c-e71ceadb6d07@suse.de> References: <20200511093554.211493-1-daniel.vetter@ffwll.ch> <20200511093554.211493-9-daniel.vetter@ffwll.ch> <41b3f24c-de0c-9390-6b8c-e71ceadb6d07@suse.de> Message-ID: <20200603131209.GN20149@phenom.ffwll.local> On Thu, May 14, 2020 at 09:30:04AM +0200, Thomas Zimmermann wrote: > Hi > > Am 11.05.20 um 11:35 schrieb Daniel Vetter: > > Just a bit of light paranoia. Also sprinkle this check over > > drm_gem_shmem_get_sg_table, which should only be called when > > exporting, same for the pin/unpin functions, on which it relies to > > work correctly. > > > > Cc: Gerd Hoffmann > > Cc: Rob Herring > > Cc: Noralf Tr?nnes > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/drm_gem_shmem_helper.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > > index 117a7841e284..f7011338813e 100644 > > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > > @@ -170,6 +170,8 @@ int drm_gem_shmem_get_pages(struct drm_gem_shmem_object *shmem) > > { > > int ret; > > > > + WARN_ON(shmem->base.import_attach); > > + > > ret = mutex_lock_interruptible(&shmem->pages_lock); > > if (ret) > > return ret; > > @@ -225,6 +227,8 @@ int drm_gem_shmem_pin(struct drm_gem_object *obj) > > { > > struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > > > > + WARN_ON(shmem->base.import_attach); > > + > > I don't understand this change. If a driver pins pages it now has to > check that the pages are not imported? Nope. There's two classes of functions in the helpers, and I'm trying to unconfuse them: - stuff used to implement gem_funcs. These are obviously only ever used on native objects, never on imported ones (on imported ones we try to forward through the dma-buf layer to the exporter). drm_gem_shmem_pin is only used in that role to implement gem_funcs->pin. Calling it on an imported buffer is indeed a bug. - the other set of functions are for drivers to do their stuff. The interface which (implicitly) pins stuff into places is various set of get_pages, which do have different paths for native and imported objects. Apologies that I missed your question here, I merged all the patches leading up to this one for now. Thanks, Daniel > > > > return drm_gem_shmem_get_pages(shmem); > > } > > EXPORT_SYMBOL(drm_gem_shmem_pin); > > @@ -240,6 +244,8 @@ void drm_gem_shmem_unpin(struct drm_gem_object *obj) > > { > > struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > > > > + WARN_ON(shmem->base.import_attach); > > + > > drm_gem_shmem_put_pages(shmem); > > } > > EXPORT_SYMBOL(drm_gem_shmem_unpin); > > @@ -510,6 +516,8 @@ static void drm_gem_shmem_vm_open(struct vm_area_struct *vma) > > struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > > int ret; > > > > + WARN_ON(shmem->base.import_attach); > > + > > ret = drm_gem_shmem_get_pages(shmem); > > WARN_ON_ONCE(ret != 0); > > > > @@ -611,6 +619,8 @@ struct sg_table *drm_gem_shmem_get_sg_table(struct drm_gem_object *obj) > > { > > struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > > > > + WARN_ON(shmem->base.import_attach); > > + > > return drm_prime_pages_to_sg(shmem->pages, obj->size >> PAGE_SHIFT); > > } > > EXPORT_SYMBOL_GPL(drm_gem_shmem_get_sg_table); > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 N?rnberg, Germany > (HRB 36809, AG N?rnberg) > Gesch?ftsf?hrer: Felix Imend?rffer > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From daniel at ffwll.ch Wed Jun 3 13:46:58 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 3 Jun 2020 15:46:58 +0200 Subject: [Intel-gfx] [PATCH 3/3] drm/hdlcd: Don't call drm_crtc_vblank_off on unbind In-Reply-To: <20200602130016.GR159988@e110455-lin.cambridge.arm.com> References: <20200602095140.36678-1-daniel.vetter@ffwll.ch> <20200602095140.36678-3-daniel.vetter@ffwll.ch> <20200602130016.GR159988@e110455-lin.cambridge.arm.com> Message-ID: <20200603134658.GQ20149@phenom.ffwll.local> On Tue, Jun 02, 2020 at 02:00:16PM +0100, Liviu Dudau wrote: > On Tue, Jun 02, 2020 at 11:51:40AM +0200, Daniel Vetter wrote: > > This is already taken care of by drm_atomic_helper_shutdown(), and > > in that case only for the CRTC which are actually on. > > > > Only tricky bit here is that we kill the interrupt handling before we > > shut down crtc, so need to reorder that. > > > > Signed-off-by: Daniel Vetter > > Cc: Liviu Dudau > > Acked-by: Liviu Dudau Ok I merged the two arm patches, thanks for taking a look. First patch needs more work ... -Daniel > > Best regards, > Liviu > > > Cc: Brian Starkey > > Cc: > > --- > > drivers/gpu/drm/arm/hdlcd_drv.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c > > index 194419f47c5e..26bc5d7766f5 100644 > > --- a/drivers/gpu/drm/arm/hdlcd_drv.c > > +++ b/drivers/gpu/drm/arm/hdlcd_drv.c > > @@ -347,9 +347,8 @@ static void hdlcd_drm_unbind(struct device *dev) > > of_node_put(hdlcd->crtc.port); > > hdlcd->crtc.port = NULL; > > pm_runtime_get_sync(dev); > > - drm_crtc_vblank_off(&hdlcd->crtc); > > - drm_irq_uninstall(drm); > > drm_atomic_helper_shutdown(drm); > > + drm_irq_uninstall(drm); > > pm_runtime_put(dev); > > if (pm_runtime_enabled(dev)) > > pm_runtime_disable(dev); > > -- > > 2.26.2 > > > > -- > ==================== > | I would like to | > | fix the world, | > | but they're not | > | giving me the | > \ source code! / > --------------- > ?\_(?)_/? -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From chris at chris-wilson.co.uk Wed Jun 3 14:55:29 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 3 Jun 2020 15:55:29 +0100 Subject: [Intel-gfx] [PATCH] Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") Message-ID: <20200603145529.3851-1-chris@chris-wilson.co.uk> This restores 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") by reverting commit 921f0c47f228 ("drm/i915: Revert "drm/i915/tgl: Wa_1607138340""). Our CI machines are recording a rare error where the CS events are out of order, leading to a machine death. Restoring the Wa_1607138340 (i.e. forcing a full restore on every context switch) prevents it. Whether or not is it the same root cause remains to be seen, but since the machine death is quite easy to hit on B0, it is unresolved. Fixes: 921f0c47f228 ("drm/i915: Revert "drm/i915/tgl: Wa_1607138340"") References: 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Francesco Balestrieri --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index aac8da18694f..e5e709dccef4 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1520,6 +1520,10 @@ static u64 execlists_update_context(struct i915_request *rq) */ wmb(); + /* Wa_1607138340:tgl */ + if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_B0)) + desc |= CTX_DESC_FORCE_RESTORE; + ce->lrc.desc &= ~CTX_DESC_FORCE_RESTORE; return desc; } -- 2.20.1 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:53 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:53 +0200 Subject: [Intel-gfx] [PATCH 04/24] drm/i915: Parse command buffer earlier in eb_relocate(slow) In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-4-maarten.lankhorst@linux.intel.com> We want to introduce backoff logic, but we need to lock the pool object as well for command parsing. Because of this, we will need backoff logic for the engine pool obj, move the batch validation up slightly to eb_lookup_vmas, and the actual command parsing in a separate function which can get called from execbuf relocation fast and slowpath. Signed-off-by: Maarten Lankhorst --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 68 ++++++++++--------- 1 file changed, 37 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 0f0c77bdf160..768a967054e4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -292,6 +292,8 @@ struct i915_execbuffer { struct eb_vma_array *array; }; +static int eb_parse(struct i915_execbuffer *eb); + static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) { return intel_engine_requires_cmd_parser(eb->engine) || @@ -875,6 +877,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) static int eb_lookup_vmas(struct i915_execbuffer *eb) { + struct drm_i915_private *i915 = eb->i915; unsigned int batch = eb_batch_index(eb); unsigned int i; int err = 0; @@ -888,18 +891,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) vma = eb_lookup_vma(eb, eb->exec[i].handle); if (IS_ERR(vma)) { err = PTR_ERR(vma); - break; + goto err; } err = eb_validate_vma(eb, &eb->exec[i], vma); if (unlikely(err)) { i915_vma_put(vma); - break; + goto err; } eb_add_vma(eb, i, batch, vma); } + if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) { + drm_dbg(&i915->drm, + "Attempting to use self-modifying batch buffer\n"); + return -EINVAL; + } + + if (range_overflows_t(u64, + eb->batch_start_offset, eb->batch_len, + eb->batch->vma->size)) { + drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); + return -EINVAL; + } + + if (eb->batch_len == 0) + eb->batch_len = eb->batch->vma->size - eb->batch_start_offset; + + return 0; + +err: eb->vma[i].vma = NULL; return err; } @@ -1911,7 +1933,7 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb) return 0; } -static noinline int eb_relocate_slow(struct i915_execbuffer *eb) +static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) { bool have_copy = false; struct eb_vma *ev; @@ -1972,6 +1994,11 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) if (err) goto err; + /* as last step, parse the command buffer */ + err = eb_parse(eb); + if (err) + goto err; + /* * Leave the user relocations as are, this is the painfully slow path, * and we want to avoid the complication of dropping the lock whilst @@ -2004,7 +2031,7 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) return err; } -static int eb_relocate(struct i915_execbuffer *eb) +static int eb_relocate_parse(struct i915_execbuffer *eb) { int err; @@ -2033,10 +2060,10 @@ static int eb_relocate(struct i915_execbuffer *eb) if (!err) err = flush; else - return eb_relocate_slow(eb); + return eb_relocate_parse_slow(eb); } - return err; + return eb_parse(eb); } static int eb_move_to_gpu(struct i915_execbuffer *eb) @@ -2934,7 +2961,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_context; - err = eb_relocate(&eb); + err = eb_relocate_parse(&eb); if (err) { /* * If the user expects the execobject.offset and @@ -2947,33 +2974,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } - if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) { - drm_dbg(&i915->drm, - "Attempting to use self-modifying batch buffer\n"); - err = -EINVAL; - goto err_vma; - } - - if (range_overflows_t(u64, - eb.batch_start_offset, eb.batch_len, - eb.batch->vma->size)) { - drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); - err = -EINVAL; - goto err_vma; - } - - if (eb.batch_len == 0) - eb.batch_len = eb.batch->vma->size - eb.batch_start_offset; - - err = eb_parse(&eb); - if (err) - goto err_vma; - /* * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure * batch" bit. Hence we need to pin secure batches into the global gtt. * hsw should have this fixed, but bdw mucks it up again. */ - batch = eb.batch->vma; if (eb.batch_flags & I915_DISPATCH_SECURE) { struct i915_vma *vma; @@ -2987,13 +2991,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, * fitting due to fragmentation. * So this is actually safe. */ - vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); + vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { err = PTR_ERR(vma); goto err_parse; } batch = vma; + } else { + batch = eb.batch->vma; } /* All GPU relocation batches must be submitted prior to the user rq */ -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:54 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:54 +0200 Subject: [Intel-gfx] [PATCH 05/24] Revert "drm/i915/gem: Split eb_vma into its own allocation" In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-5-maarten.lankhorst@linux.intel.com> This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974. This conflicts with the ww mutex handling, which needs to drop the references after gpu submission anyway, because otherwise we may risk unlocking a BO after first freeing it. Signed-off-by: Maarten Lankhorst --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 124 +++++++----------- 1 file changed, 51 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 768a967054e4..e1d63588ed8f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -40,11 +40,6 @@ struct eb_vma { u32 handle; }; -struct eb_vma_array { - struct kref kref; - struct eb_vma vma[]; -}; - enum { FORCE_CPU_RELOC = 1, FORCE_GTT_RELOC, @@ -57,6 +52,7 @@ enum { #define __EXEC_OBJECT_NEEDS_MAP BIT(29) #define __EXEC_OBJECT_NEEDS_BIAS BIT(28) #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ +#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) #define __EXEC_HAS_RELOC BIT(31) #define __EXEC_INTERNAL_FLAGS (~0u << 31) @@ -289,7 +285,6 @@ struct i915_execbuffer { */ int lut_size; struct hlist_head *buckets; /** ht for relocation handles */ - struct eb_vma_array *array; }; static int eb_parse(struct i915_execbuffer *eb); @@ -301,62 +296,8 @@ static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) eb->args->batch_len); } -static struct eb_vma_array *eb_vma_array_create(unsigned int count) -{ - struct eb_vma_array *arr; - - arr = kvmalloc(struct_size(arr, vma, count), GFP_KERNEL | __GFP_NOWARN); - if (!arr) - return NULL; - - kref_init(&arr->kref); - arr->vma[0].vma = NULL; - - return arr; -} - -static inline void eb_unreserve_vma(struct eb_vma *ev) -{ - struct i915_vma *vma = ev->vma; - - if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE)) - __i915_vma_unpin_fence(vma); - - if (ev->flags & __EXEC_OBJECT_HAS_PIN) - __i915_vma_unpin(vma); - - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | - __EXEC_OBJECT_HAS_FENCE); -} - -static void eb_vma_array_destroy(struct kref *kref) -{ - struct eb_vma_array *arr = container_of(kref, typeof(*arr), kref); - struct eb_vma *ev = arr->vma; - - while (ev->vma) { - eb_unreserve_vma(ev); - i915_vma_put(ev->vma); - ev++; - } - - kvfree(arr); -} - -static void eb_vma_array_put(struct eb_vma_array *arr) -{ - kref_put(&arr->kref, eb_vma_array_destroy); -} - static int eb_create(struct i915_execbuffer *eb) { - /* Allocate an extra slot for use by the command parser + sentinel */ - eb->array = eb_vma_array_create(eb->buffer_count + 2); - if (!eb->array) - return -ENOMEM; - - eb->vma = eb->array->vma; - if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { unsigned int size = 1 + ilog2(eb->buffer_count); @@ -390,10 +331,8 @@ static int eb_create(struct i915_execbuffer *eb) break; } while (--size); - if (unlikely(!size)) { - eb_vma_array_put(eb->array); + if (unlikely(!size)) return -ENOMEM; - } eb->lut_size = size; } else { @@ -504,6 +443,26 @@ eb_pin_vma(struct i915_execbuffer *eb, return !eb_vma_misplaced(entry, vma, ev->flags); } +static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) +{ + GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); + + if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) + __i915_vma_unpin_fence(vma); + + __i915_vma_unpin(vma); +} + +static inline void +eb_unreserve_vma(struct eb_vma *ev) +{ + if (!(ev->flags & __EXEC_OBJECT_HAS_PIN)) + return; + + __eb_unreserve_vma(ev->vma, ev->flags); + ev->flags &= ~__EXEC_OBJECT_RESERVED; +} + static int eb_validate_vma(struct i915_execbuffer *eb, struct drm_i915_gem_exec_object2 *entry, @@ -946,13 +905,31 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) } } +static void eb_release_vmas(const struct i915_execbuffer *eb) +{ + const unsigned int count = eb->buffer_count; + unsigned int i; + + for (i = 0; i < count; i++) { + struct eb_vma *ev = &eb->vma[i]; + struct i915_vma *vma = ev->vma; + + if (!vma) + break; + + eb->vma[i].vma = NULL; + + if (ev->flags & __EXEC_OBJECT_HAS_PIN) + __eb_unreserve_vma(vma, ev->flags); + + i915_vma_put(vma); + } +} + static void eb_destroy(const struct i915_execbuffer *eb) { GEM_BUG_ON(eb->reloc_cache.rq); - if (eb->array) - eb_vma_array_put(eb->array); - if (eb->lut_size > 0) kfree(eb->buckets); } @@ -2143,12 +2120,9 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) err = i915_vma_move_to_active(vma, eb->request, flags); i915_vma_unlock(vma); - eb_unreserve_vma(ev); } ww_acquire_fini(&acquire); - eb_vma_array_put(fetch_and_zero(&eb->array)); - if (unlikely(err)) goto err_skip; @@ -2403,7 +2377,6 @@ static int eb_parse(struct i915_execbuffer *eb) eb->vma[eb->buffer_count].vma = i915_vma_get(shadow); eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN; eb->batch = &eb->vma[eb->buffer_count++]; - eb->vma[eb->buffer_count].vma = NULL; eb->trampoline = trampoline; eb->batch_start_offset = 0; @@ -2902,6 +2875,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, args->flags |= __EXEC_HAS_RELOC; eb.exec = exec; + eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); + eb.vma[0].vma = NULL; eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; reloc_cache_init(&eb.reloc_cache, eb.i915); @@ -3078,6 +3053,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (batch->private) intel_gt_buffer_pool_put(batch->private); err_vma: + if (eb.exec) + eb_release_vmas(&eb); if (eb.trampoline) i915_vma_unpin(eb.trampoline); eb_unpin_engine(&eb); @@ -3095,7 +3072,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, static size_t eb_element_size(void) { - return sizeof(struct drm_i915_gem_exec_object2); + return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma); } static bool check_buffer_count(size_t count) @@ -3151,7 +3128,7 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, /* Copy in the exec list from userland */ exec_list = kvmalloc_array(count, sizeof(*exec_list), __GFP_NOWARN | GFP_KERNEL); - exec2_list = kvmalloc_array(count, eb_element_size(), + exec2_list = kvmalloc_array(count + 1, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec_list == NULL || exec2_list == NULL) { drm_dbg(&i915->drm, @@ -3229,7 +3206,8 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, if (err) return err; - exec2_list = kvmalloc_array(count, eb_element_size(), + /* Allocate an extra slot for use by the command parser */ + exec2_list = kvmalloc_array(count + 1, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec2_list == NULL) { drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:59 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:59 +0200 Subject: [Intel-gfx] [PATCH 10/24] drm/i915: Nuke arguments to eb_pin_engine In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-10-maarten.lankhorst@linux.intel.com> Those arguments are already set as eb.file and eb.args, so kill off the extra arguments. This will allow us to move eb_pin_engine() to after we reserved all BO's. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 5bcc802e0014..3dc0c0eb0e05 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2689,11 +2689,10 @@ static void eb_unpin_engine(struct i915_execbuffer *eb) } static unsigned int -eb_select_legacy_ring(struct i915_execbuffer *eb, - struct drm_file *file, - struct drm_i915_gem_execbuffer2 *args) +eb_select_legacy_ring(struct i915_execbuffer *eb) { struct drm_i915_private *i915 = eb->i915; + struct drm_i915_gem_execbuffer2 *args = eb->args; unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; if (user_ring_id != I915_EXEC_BSD && @@ -2708,7 +2707,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb, unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; if (bsd_idx == I915_EXEC_BSD_DEFAULT) { - bsd_idx = gen8_dispatch_bsd_engine(i915, file); + bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file); } else if (bsd_idx >= I915_EXEC_BSD_RING1 && bsd_idx <= I915_EXEC_BSD_RING2) { bsd_idx >>= I915_EXEC_BSD_SHIFT; @@ -2733,18 +2732,16 @@ eb_select_legacy_ring(struct i915_execbuffer *eb, } static int -eb_pin_engine(struct i915_execbuffer *eb, - struct drm_file *file, - struct drm_i915_gem_execbuffer2 *args) +eb_pin_engine(struct i915_execbuffer *eb) { struct intel_context *ce; unsigned int idx; int err; if (i915_gem_context_user_engines(eb->gem_context)) - idx = args->flags & I915_EXEC_RING_MASK; + idx = eb->args->flags & I915_EXEC_RING_MASK; else - idx = eb_select_legacy_ring(eb, file, args); + idx = eb_select_legacy_ring(eb); ce = i915_gem_context_get_engine(eb->gem_context, idx); if (IS_ERR(ce)) @@ -3010,7 +3007,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_destroy; - err = eb_pin_engine(&eb, file, args); + err = eb_pin_engine(&eb); if (unlikely(err)) goto err_context; -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:57 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:57 +0200 Subject: [Intel-gfx] [PATCH 08/24] drm/i915: Use ww locking in intel_renderstate. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-8-maarten.lankhorst@linux.intel.com> We want to start using ww locking in intel_context_pin, for this we need to lock multiple objects, and the single i915_gem_object_lock is not enough. Convert to using ww-waiting, and make sure we always pin intel_context_state, even if we don't have a renderstate object. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_gt.c | 21 +++--- drivers/gpu/drm/i915/gt/intel_renderstate.c | 78 ++++++++++++++------- drivers/gpu/drm/i915/gt/intel_renderstate.h | 9 ++- 3 files changed, 72 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ebc29b6ee86c..24a0e47a2477 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -398,21 +398,20 @@ static int __engines_record_defaults(struct intel_gt *gt) /* We must be able to switch to something! */ GEM_BUG_ON(!engine->kernel_context); - err = intel_renderstate_init(&so, engine); - if (err) - goto out; - ce = intel_context_create(engine); if (IS_ERR(ce)) { err = PTR_ERR(ce); goto out; } - rq = intel_context_create_request(ce); + err = intel_renderstate_init(&so, ce); + if (err) + goto err; + + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); - intel_context_put(ce); - goto out; + goto err_fini; } err = intel_engine_emit_ctx_wa(rq); @@ -426,9 +425,13 @@ static int __engines_record_defaults(struct intel_gt *gt) err_rq: requests[id] = i915_request_get(rq); i915_request_add(rq); - intel_renderstate_fini(&so); - if (err) +err_fini: + intel_renderstate_fini(&so, ce); +err: + if (err) { + intel_context_put(ce); goto out; + } } /* Flush the default context image to memory, and enable powersaving. */ diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index d133e6b40d6c..a289f22ced3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -27,6 +27,7 @@ #include "i915_drv.h" #include "intel_renderstate.h" +#include "gt/intel_context.h" #include "intel_ring.h" static const struct intel_renderstate_rodata * @@ -74,10 +75,9 @@ static int render_state_setup(struct intel_renderstate *so, u32 *d; int ret; - i915_gem_object_lock(so->vma->obj, NULL); ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush); if (ret) - goto out_unlock; + return ret; d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0)); @@ -158,8 +158,6 @@ static int render_state_setup(struct intel_renderstate *so, ret = 0; out: i915_gem_object_finish_access(so->vma->obj); -out_unlock: - i915_gem_object_unlock(so->vma->obj); return ret; err: @@ -171,33 +169,47 @@ static int render_state_setup(struct intel_renderstate *so, #undef OUT_BATCH int intel_renderstate_init(struct intel_renderstate *so, - struct intel_engine_cs *engine) + struct intel_context *ce) { - struct drm_i915_gem_object *obj; + struct intel_engine_cs *engine = ce->engine; + struct drm_i915_gem_object *obj = NULL; int err; memset(so, 0, sizeof(*so)); so->rodata = render_state_get_rodata(engine); - if (!so->rodata) - return 0; + if (so->rodata) { + if (so->rodata->batch_items * 4 > PAGE_SIZE) + return -EINVAL; + + obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); + if (IS_ERR(so->vma)) { + err = PTR_ERR(so->vma); + goto err_obj; + } + } - if (so->rodata->batch_items * 4 > PAGE_SIZE) - return -EINVAL; + i915_gem_ww_ctx_init(&so->ww, true); +retry: + err = intel_context_pin(ce); + if (err) + goto err_fini; - obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); - if (IS_ERR(obj)) - return PTR_ERR(obj); + /* return early if there's nothing to setup */ + if (!err && !so->rodata) + return 0; - so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); - if (IS_ERR(so->vma)) { - err = PTR_ERR(so->vma); - goto err_obj; - } + err = i915_gem_object_lock(so->vma->obj, &so->ww); + if (err) + goto err_context; err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH); if (err) - goto err_obj; + goto err_context; err = render_state_setup(so, engine->i915); if (err) @@ -207,8 +219,18 @@ int intel_renderstate_init(struct intel_renderstate *so, err_unpin: i915_vma_unpin(so->vma); +err_context: + intel_context_unpin(ce); +err_fini: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&so->ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&so->ww); err_obj: - i915_gem_object_put(obj); + if (obj) + i915_gem_object_put(obj); so->vma = NULL; return err; } @@ -222,11 +244,9 @@ int intel_renderstate_emit(struct intel_renderstate *so, if (!so->vma) return 0; - i915_vma_lock(so->vma); err = i915_request_await_object(rq, so->vma->obj, false); if (err == 0) err = i915_vma_move_to_active(so->vma, rq, 0); - i915_vma_unlock(so->vma); if (err) return err; @@ -247,7 +267,17 @@ int intel_renderstate_emit(struct intel_renderstate *so, return 0; } -void intel_renderstate_fini(struct intel_renderstate *so) +void intel_renderstate_fini(struct intel_renderstate *so, + struct intel_context *ce) { - i915_vma_unpin_and_release(&so->vma, 0); + if (so->vma) { + i915_vma_unpin(so->vma); + i915_vma_close(so->vma); + } + + intel_context_unpin(ce); + i915_gem_ww_ctx_fini(&so->ww); + + if (so->vma) + i915_gem_object_put(so->vma->obj); } diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.h b/drivers/gpu/drm/i915/gt/intel_renderstate.h index 5700be69a05a..713aa1e86c80 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.h +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.h @@ -25,9 +25,10 @@ #define _INTEL_RENDERSTATE_H_ #include +#include "i915_gem.h" struct i915_request; -struct intel_engine_cs; +struct intel_context; struct i915_vma; struct intel_renderstate_rodata { @@ -49,6 +50,7 @@ extern const struct intel_renderstate_rodata gen8_null_state; extern const struct intel_renderstate_rodata gen9_null_state; struct intel_renderstate { + struct i915_gem_ww_ctx ww; const struct intel_renderstate_rodata *rodata; struct i915_vma *vma; u32 batch_offset; @@ -58,9 +60,10 @@ struct intel_renderstate { }; int intel_renderstate_init(struct intel_renderstate *so, - struct intel_engine_cs *engine); + struct intel_context *ce); int intel_renderstate_emit(struct intel_renderstate *so, struct i915_request *rq); -void intel_renderstate_fini(struct intel_renderstate *so); +void intel_renderstate_fini(struct intel_renderstate *so, + struct intel_context *ce); #endif /* _INTEL_RENDERSTATE_H_ */ -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:56 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:56 +0200 Subject: [Intel-gfx] [PATCH 07/24] drm/i915: Use per object locking in execbuf, v11. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-7-maarten.lankhorst@linux.intel.com> Now that we changed execbuf submission slightly to allow us to do all pinning in one place, we can now simply add ww versions on top of struct_mutex. All we have to do is a separate path for -EDEADLK handling, which needs to unpin all gem bo's before dropping the lock, then starting over. This finally allows us to do parallel submission, but because not all of the pinning code uses the ww ctx yet, we cannot completely drop struct_mutex yet. Changes since v1: - Keep struct_mutex for now. :( Changes since v2: - Make sure we always lock the ww context in slowpath. Changes since v3: - Don't call __eb_unreserve_vma in eb_move_to_gpu now; this can be done on normal unlock path. - Unconditionally release vmas and context. Changes since v4: - Rebased on top of struct_mutex reduction. Changes since v5: - Remove training wheels. Changes since v6: - Fix accidentally broken -ENOSPC handling. Changes since v7: - Handle gt buffer pool better. Changes since v8: - Properly clear variables, to make -EDEADLK handling not BUG. Change since v9: - Fix unpinning fence on pnv and below. Changes since v10: - Make relocation gpu chaining working again. Signed-off-by: Maarten Lankhorst --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 396 +++++++++++------- .../i915/gem/selftests/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 6 + drivers/gpu/drm/i915/i915_gem.h | 1 + 4 files changed, 249 insertions(+), 156 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 4ef6e48da8f1..5bcc802e0014 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -249,6 +249,8 @@ struct i915_execbuffer { /** list of vma that have execobj.relocation_count */ struct list_head relocs; + struct i915_gem_ww_ctx ww; + /** * Track the most recently used object for relocations, as we * frequently have to perform multiple relocations within the same @@ -269,14 +271,18 @@ struct i915_execbuffer { struct i915_vma *rq_vma; u32 *rq_cmd; unsigned int rq_size; + struct intel_gt_buffer_pool_node *pool; } reloc_cache; + struct intel_gt_buffer_pool_node *reloc_pool; /** relocation pool for -EDEADLK handling */ + u64 invalid_flags; /** Set of execobj.flags that are invalid */ u32 context_flags; /** Set of execobj.flags to insert from the ctx */ u32 batch_start_offset; /** Location within object of batch */ u32 batch_len; /** Length of batch within object */ u32 batch_flags; /** Flags composed for emit_bb_start() */ + struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */ /** * Indicate either the size of the hastable used to resolve @@ -443,23 +449,16 @@ eb_pin_vma(struct i915_execbuffer *eb, return !eb_vma_misplaced(entry, vma, ev->flags); } -static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) -{ - GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); - - if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) - __i915_vma_unpin_fence(vma); - - __i915_vma_unpin(vma); -} - static inline void eb_unreserve_vma(struct eb_vma *ev) { if (!(ev->flags & __EXEC_OBJECT_HAS_PIN)) return; - __eb_unreserve_vma(ev->vma, ev->flags); + if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE)) + __i915_vma_unpin_fence(ev->vma); + + __i915_vma_unpin(ev->vma); ev->flags &= ~__EXEC_OBJECT_RESERVED; } @@ -554,16 +553,6 @@ eb_add_vma(struct i915_execbuffer *eb, eb->batch = ev; } - - if (eb_pin_vma(eb, entry, ev)) { - if (entry->offset != vma->node.start) { - entry->offset = vma->node.start | UPDATE; - eb->args->flags |= __EXEC_HAS_RELOC; - } - } else { - eb_unreserve_vma(ev); - list_add_tail(&ev->bind_link, &eb->unbound); - } } static inline int use_cpu_reloc(const struct reloc_cache *cache, @@ -648,10 +637,6 @@ static int eb_reserve(struct i915_execbuffer *eb) * This avoid unnecessary unbinding of later objects in order to make * room for the earlier objects *unless* we need to defragment. */ - - if (mutex_lock_interruptible(&eb->i915->drm.struct_mutex)) - return -EINTR; - pass = 0; do { list_for_each_entry(ev, &eb->unbound, bind_link) { @@ -659,8 +644,8 @@ static int eb_reserve(struct i915_execbuffer *eb) if (err) break; } - if (!(err == -ENOSPC || err == -EAGAIN)) - break; + if (err != -ENOSPC) + return err; /* Resort *all* the objects into priority order */ INIT_LIST_HEAD(&eb->unbound); @@ -690,13 +675,6 @@ static int eb_reserve(struct i915_execbuffer *eb) } list_splice_tail(&last, &eb->unbound); - if (err == -EAGAIN) { - mutex_unlock(&eb->i915->drm.struct_mutex); - flush_workqueue(eb->i915->mm.userptr_wq); - mutex_lock(&eb->i915->drm.struct_mutex); - continue; - } - switch (pass++) { case 0: break; @@ -707,20 +685,15 @@ static int eb_reserve(struct i915_execbuffer *eb) err = i915_gem_evict_vm(eb->context->vm); mutex_unlock(&eb->context->vm->mutex); if (err) - goto unlock; + return err; break; default: - err = -ENOSPC; - goto unlock; + return -ENOSPC; } pin_flags = PIN_USER; } while (1); - -unlock: - mutex_unlock(&eb->i915->drm.struct_mutex); - return err; } static unsigned int eb_batch_index(const struct i915_execbuffer *eb) @@ -848,7 +821,6 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) int err = 0; INIT_LIST_HEAD(&eb->relocs); - INIT_LIST_HEAD(&eb->unbound); for (i = 0; i < eb->buffer_count; i++) { struct i915_vma *vma; @@ -891,6 +863,48 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) return err; } +static int eb_validate_vmas(struct i915_execbuffer *eb) +{ + unsigned int i; + int err; + + INIT_LIST_HEAD(&eb->unbound); + + for (i = 0; i < eb->buffer_count; i++) { + struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; + struct eb_vma *ev = &eb->vma[i]; + struct i915_vma *vma = ev->vma; + + err = i915_gem_object_lock(vma->obj, &eb->ww); + if (err) + return err; + + if (eb_pin_vma(eb, entry, ev)) { + if (entry->offset != vma->node.start) { + entry->offset = vma->node.start | UPDATE; + eb->args->flags |= __EXEC_HAS_RELOC; + } + } else { + eb_unreserve_vma(ev); + + list_add_tail(&ev->bind_link, &eb->unbound); + if (drm_mm_node_allocated(&vma->node)) { + err = i915_vma_unbind(vma); + if (err) + return err; + } + } + + GEM_BUG_ON(drm_mm_node_allocated(&vma->node) && + eb_vma_misplaced(&eb->exec[i], vma, ev->flags)); + } + + if (!list_empty(&eb->unbound)) + return eb_reserve(eb); + + return 0; +} + static struct eb_vma * eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) { @@ -911,7 +925,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) } } -static void eb_release_vmas(const struct i915_execbuffer *eb) +static void eb_release_vmas(const struct i915_execbuffer *eb, bool final) { const unsigned int count = eb->buffer_count; unsigned int i; @@ -923,12 +937,10 @@ static void eb_release_vmas(const struct i915_execbuffer *eb) if (!vma) break; - eb->vma[i].vma = NULL; - - if (ev->flags & __EXEC_OBJECT_HAS_PIN) - __eb_unreserve_vma(vma, ev->flags); + eb_unreserve_vma(ev); - i915_vma_put(vma); + if (final) + i915_vma_put(vma); } } @@ -947,6 +959,15 @@ relocation_target(const struct drm_i915_gem_relocation_entry *reloc, return gen8_canonical_addr((int)reloc->delta + target->node.start); } +static void reloc_cache_clear(struct reloc_cache *cache) +{ + cache->rq = NULL; + cache->rq_cmd = NULL; + cache->pool = NULL; + cache->rq_size = 0; + cache->target = NULL; +} + static void reloc_cache_init(struct reloc_cache *cache, struct drm_i915_private *i915) { @@ -959,8 +980,7 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->rq = NULL; - cache->target = NULL; + reloc_cache_clear(cache); } static inline void *unmask_page(unsigned long p) @@ -984,17 +1004,41 @@ static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) #define RELOC_TAIL 4 -static int reloc_gpu_chain(struct reloc_cache *cache) +static void reloc_cache_put_pool(struct i915_execbuffer *eb, struct reloc_cache *cache) { - struct intel_gt_buffer_pool_node *pool; + if (!cache->pool) + return; + + /* + * This is a bit nasty, normally we keep objects locked until the end + * of execbuffer, but we already submit this, and have to unlock before + * dropping the reference. Fortunately we can only hold 1 pool node at + * a time, so this should be harmless. + */ + i915_gem_ww_unlock_single(cache->pool->obj); + intel_gt_buffer_pool_put(cache->pool); + cache->pool = NULL; +} + +static int reloc_gpu_chain(struct i915_execbuffer *eb, struct reloc_cache *cache) +{ + struct intel_gt_buffer_pool_node *pool = eb->reloc_pool; struct i915_request *rq = cache->rq; struct i915_vma *batch; u32 *cmd; int err; - pool = intel_gt_get_buffer_pool(rq->engine->gt, PAGE_SIZE); - if (IS_ERR(pool)) - return PTR_ERR(pool); + if (!pool || pool == cache->pool) { + pool = intel_gt_get_buffer_pool(rq->engine->gt, PAGE_SIZE); + + if (IS_ERR(pool)) + return PTR_ERR(pool); + } + eb->reloc_pool = pool; + + err = i915_gem_object_lock_interruptible(pool->obj, &eb->ww); + if (err) + goto out_pool; batch = i915_vma_instance(pool->obj, rq->context->vm, NULL); if (IS_ERR(batch)) { @@ -1023,11 +1067,9 @@ static int reloc_gpu_chain(struct reloc_cache *cache) err = intel_gt_buffer_pool_mark_active(pool, rq); if (err == 0) { - i915_vma_lock(batch); err = i915_request_await_object(rq, batch->obj, false); if (err == 0) err = i915_vma_move_to_active(batch, rq, 0); - i915_vma_unlock(batch); } i915_vma_unpin(batch); if (err) @@ -1048,7 +1090,11 @@ static int reloc_gpu_chain(struct reloc_cache *cache) cache->rq_vma = batch; out_pool: - intel_gt_buffer_pool_put(pool); + /* Remove the old pool from chain */ + reloc_cache_put_pool(eb, cache); + + if (!err) + cache->pool = pool; return err; } @@ -1057,7 +1103,7 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) return cache->gen > 5 ? 0 : I915_DISPATCH_SECURE; } -static int reloc_gpu_flush(struct reloc_cache *cache) +static int reloc_gpu_flush(struct i915_execbuffer *eb, struct reloc_cache *cache) { struct i915_request *rq; int err; @@ -1091,7 +1137,12 @@ static int reloc_gpu_flush(struct reloc_cache *cache) intel_gt_chipset_flush(rq->engine->gt); i915_request_add(rq); + reloc_cache_put_pool(eb, cache); + reloc_cache_clear(cache); + + eb->reloc_pool = NULL; return err; + } static void reloc_cache_reset(struct reloc_cache *cache) @@ -1110,7 +1161,6 @@ static void reloc_cache_reset(struct reloc_cache *cache) kunmap_atomic(vaddr); i915_gem_object_finish_access(obj); - i915_gem_object_unlock(obj); } else { struct i915_ggtt *ggtt = cache_to_ggtt(cache); @@ -1145,15 +1195,9 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj, unsigned int flushes; int err; - err = i915_gem_object_lock_interruptible(obj, NULL); - if (err) - return ERR_PTR(err); - err = i915_gem_object_prepare_write(obj, &flushes); - if (err) { - i915_gem_object_unlock(obj); + if (err) return ERR_PTR(err); - } BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); @@ -1192,9 +1236,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, if (use_cpu_reloc(cache, obj)) return NULL; - i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); if (err) return ERR_PTR(err); @@ -1283,7 +1325,7 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) struct drm_i915_gem_object *obj = vma->obj; int err; - i915_vma_lock(vma); + assert_vma_held(vma); if (obj->cache_dirty & ~obj->cache_coherent) i915_gem_clflush_object(obj, 0); @@ -1293,8 +1335,6 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); - return err; } @@ -1303,15 +1343,22 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; - struct intel_gt_buffer_pool_node *pool; + struct intel_gt_buffer_pool_node *pool = eb->reloc_pool; struct i915_request *rq; struct i915_vma *batch; u32 *cmd; int err; - pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE); - if (IS_ERR(pool)) - return PTR_ERR(pool); + if (!pool) { + pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE); + if (IS_ERR(pool)) + return PTR_ERR(pool); + } + eb->reloc_pool = NULL; + + err = i915_gem_object_lock(pool->obj, &eb->ww); + if (err) + goto err_pool; cmd = i915_gem_object_pin_map(pool->obj, cache->has_llc ? @@ -1319,7 +1366,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, I915_MAP_FORCE_WC); if (IS_ERR(cmd)) { err = PTR_ERR(cmd); - goto out_pool; + goto err_pool; } batch = i915_vma_instance(pool->obj, eb->context->vm, NULL); @@ -1358,11 +1405,11 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, if (err) goto err_request; - i915_vma_lock(batch); + + assert_vma_held(batch); err = i915_request_await_object(rq, batch->obj, false); if (err == 0) err = i915_vma_move_to_active(batch, rq, 0); - i915_vma_unlock(batch); if (err) goto skip_request; @@ -1373,9 +1420,10 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, cache->rq_cmd = cmd; cache->rq_size = 0; cache->rq_vma = batch; + cache->pool = pool; /* Return with batch mapping (cmd) still pinned */ - goto out_pool; + return 0; skip_request: i915_request_set_error_once(rq, err); @@ -1385,8 +1433,8 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, i915_vma_unpin(batch); err_unmap: i915_gem_object_unpin_map(pool->obj); -out_pool: - intel_gt_buffer_pool_put(pool); +err_pool: + eb->reloc_pool = pool; return err; } @@ -1429,7 +1477,7 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { - err = reloc_gpu_chain(cache); + err = reloc_gpu_chain(eb, cache); if (unlikely(err)) { i915_request_set_error_once(cache->rq, err); return ERR_PTR(err); @@ -1468,7 +1516,7 @@ static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) return addr + offset_in_page(offset); } -static bool __reloc_entry_gpu(struct i915_execbuffer *eb, +static int __reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, u64 offset, u64 target_addr) @@ -1486,7 +1534,9 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, len = 3; batch = reloc_gpu(eb, vma, len); - if (IS_ERR(batch)) + if (batch == ERR_PTR(-EDEADLK)) + return (s64)-EDEADLK; + else if (IS_ERR(batch)) return false; addr = gen8_canonical_addr(vma->node.start + offset); @@ -1539,7 +1589,7 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, return true; } -static bool reloc_entry_gpu(struct i915_execbuffer *eb, +static int reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, u64 offset, u64 target_addr) @@ -1561,8 +1611,12 @@ relocate_entry(struct i915_vma *vma, { u64 target_addr = relocation_target(reloc, target); u64 offset = reloc->offset; + int reloc_gpu = reloc_entry_gpu(eb, vma, offset, target_addr); - if (!reloc_entry_gpu(eb, vma, offset, target_addr)) { + if (reloc_gpu < 0) + return reloc_gpu; + + if (!reloc_gpu) { bool wide = eb->reloc_cache.use_64bit_reloc; void *vaddr; @@ -1928,6 +1982,10 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) goto out; } + /* We may process another execbuffer during the unlock... */ + eb_release_vmas(eb, false); + i915_gem_ww_ctx_fini(&eb->ww); + /* * We take 3 passes through the slowpatch. * @@ -1950,9 +2008,21 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) cond_resched(); err = 0; } + + flush_workqueue(eb->i915->mm.userptr_wq); + + i915_gem_ww_ctx_init(&eb->ww, true); if (err) goto out; + /* reacquire the objects */ +repeat_validate: + err = eb_validate_vmas(eb); + if (err) + goto err; + + GEM_BUG_ON(!eb->batch); + list_for_each_entry(ev, &eb->relocs, reloc_link) { if (!have_copy) { pagefault_disable(); @@ -1967,7 +2037,10 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) } } - flush = reloc_gpu_flush(&eb->reloc_cache); + flush = reloc_gpu_flush(eb, &eb->reloc_cache); + if (err == -EDEADLK) + goto err; + if (err && !have_copy) goto repeat; @@ -1990,6 +2063,13 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) */ err: + if (err == -EDEADLK) { + eb_release_vmas(eb, false); + err = i915_gem_ww_ctx_backoff(&eb->ww); + if (!err) + goto repeat_validate; + } + if (err == -EAGAIN) goto repeat; @@ -2018,15 +2098,12 @@ static int eb_relocate_parse(struct i915_execbuffer *eb) { int err; - err = eb_lookup_vmas(eb); - if (err) - return err; - - if (!list_empty(&eb->unbound)) { - err = eb_reserve(eb); - if (err) - return err; - } +retry: + err = eb_validate_vmas(eb); + if (err == -EAGAIN) + goto slow; + else if (err) + goto err; /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { @@ -2039,48 +2116,49 @@ static int eb_relocate_parse(struct i915_execbuffer *eb) break; } - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; + flush = reloc_gpu_flush(eb, &eb->reloc_cache); + if (err == -EDEADLK) + goto err; + else if (err) + goto slow; else - return eb_relocate_parse_slow(eb); + err = flush; + } + + if (!err) + err = eb_parse(eb); + +err: + if (err == -EDEADLK) { + eb_release_vmas(eb, false); + err = i915_gem_ww_ctx_backoff(&eb->ww); + if (!err) + goto retry; } - return eb_parse(eb); + return err; + +slow: + err = eb_relocate_parse_slow(eb); + if (err) + /* + * If the user expects the execobject.offset and + * reloc.presumed_offset to be an exact match, + * as for using NO_RELOC, then we cannot update + * the execobject.offset until we have completed + * relocation. + */ + eb->args->flags &= ~__EXEC_HAS_RELOC; + + return err; } static int eb_move_to_gpu(struct i915_execbuffer *eb) { const unsigned int count = eb->buffer_count; - struct ww_acquire_ctx acquire; - unsigned int i; + unsigned int i = count; int err = 0; - ww_acquire_init(&acquire, &reservation_ww_class); - - for (i = 0; i < count; i++) { - struct eb_vma *ev = &eb->vma[i]; - struct i915_vma *vma = ev->vma; - - err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); - if (err == -EDEADLK) { - GEM_BUG_ON(i == 0); - do { - int j = i - 1; - - ww_mutex_unlock(&eb->vma[j].vma->resv->lock); - - swap(eb->vma[i], eb->vma[j]); - } while (--i); - - err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, - &acquire); - } - if (err) - break; - } - ww_acquire_done(&acquire); - while (i--) { struct eb_vma *ev = &eb->vma[i]; struct i915_vma *vma = ev->vma; @@ -2124,10 +2202,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) if (err == 0) err = i915_vma_move_to_active(vma, eb->request, flags); - - i915_vma_unlock(vma); } - ww_acquire_fini(&acquire); if (unlikely(err)) goto err_skip; @@ -2281,10 +2356,6 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, pw->shadow = shadow; pw->trampoline = trampoline; - err = dma_resv_lock_interruptible(pw->batch->resv, NULL); - if (err) - goto err_trampoline; - err = dma_resv_reserve_shared(pw->batch->resv, 1); if (err) goto err_batch_unlock; @@ -2299,19 +2370,14 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, /* Keep the batch alive and unwritten as we parse */ dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma); - dma_resv_unlock(pw->batch->resv); - /* Force execution to wait for completion of the parser */ - dma_resv_lock(shadow->resv, NULL); dma_resv_add_excl_fence(shadow->resv, &pw->base.dma); - dma_resv_unlock(shadow->resv); dma_fence_work_commit_imm(&pw->base); return 0; err_batch_unlock: dma_resv_unlock(pw->batch->resv); -err_trampoline: if (trampoline) i915_active_release(&trampoline->active); err_shadow: @@ -2326,7 +2392,7 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, static int eb_parse(struct i915_execbuffer *eb) { struct drm_i915_private *i915 = eb->i915; - struct intel_gt_buffer_pool_node *pool; + struct intel_gt_buffer_pool_node *pool = eb->batch_pool; struct i915_vma *shadow, *trampoline; unsigned int len; int err; @@ -2349,9 +2415,16 @@ static int eb_parse(struct i915_execbuffer *eb) len += I915_CMD_PARSER_TRAMPOLINE_SIZE; } - pool = intel_gt_get_buffer_pool(eb->engine->gt, len); - if (IS_ERR(pool)) - return PTR_ERR(pool); + if (!pool) { + pool = intel_gt_get_buffer_pool(eb->engine->gt, len); + if (IS_ERR(pool)) + return PTR_ERR(pool); + eb->batch_pool = pool; + } + + err = i915_gem_object_lock(pool->obj, &eb->ww); + if (err) + goto err; shadow = shadow_batch_pin(pool->obj, eb->context->vm, PIN_USER); if (IS_ERR(shadow)) { @@ -2387,7 +2460,6 @@ static int eb_parse(struct i915_execbuffer *eb) eb->trampoline = trampoline; eb->batch_start_offset = 0; - shadow->private = pool; return 0; err_trampoline: @@ -2396,7 +2468,6 @@ static int eb_parse(struct i915_execbuffer *eb) err_shadow: i915_vma_unpin(shadow); err: - intel_gt_buffer_pool_put(pool); return err; } @@ -2883,6 +2954,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.exec = exec; eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); eb.vma[0].vma = NULL; + eb.reloc_pool = eb.batch_pool = NULL; eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; reloc_cache_init(&eb.reloc_cache, eb.i915); @@ -2942,6 +3014,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_context; + err = eb_lookup_vmas(&eb); + if (err) { + eb_release_vmas(&eb, true); + goto err_engine; + } + + i915_gem_ww_ctx_init(&eb.ww, true); + err = eb_relocate_parse(&eb); if (err) { /* @@ -2955,6 +3035,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } + ww_acquire_done(&eb.ww.ctx); + /* * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure * batch" bit. Hence we need to pin secure batches into the global gtt. @@ -2975,7 +3057,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { err = PTR_ERR(vma); - goto err_parse; + goto err_vma; } batch = vma; @@ -3027,8 +3109,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, * to explicitly hold another reference here. */ eb.request->batch = batch; - if (batch->private) - intel_gt_buffer_pool_mark_active(batch->private, eb.request); + if (eb.batch_pool) + intel_gt_buffer_pool_mark_active(eb.batch_pool, eb.request); trace_i915_request_queue(eb.request, eb.batch_flags); err = eb_submit(&eb, batch); @@ -3055,14 +3137,18 @@ i915_gem_do_execbuffer(struct drm_device *dev, err_batch_unpin: if (eb.batch_flags & I915_DISPATCH_SECURE) i915_vma_unpin(batch); -err_parse: - if (batch->private) - intel_gt_buffer_pool_put(batch->private); err_vma: - if (eb.exec) - eb_release_vmas(&eb); + eb_release_vmas(&eb, true); if (eb.trampoline) i915_vma_unpin(eb.trampoline); + WARN_ON(err == -EDEADLK); + i915_gem_ww_ctx_fini(&eb.ww); + + if (eb.batch_pool) + intel_gt_buffer_pool_put(eb.batch_pool); + if (eb.reloc_pool) + intel_gt_buffer_pool_put(eb.reloc_pool); +err_engine: eb_unpin_engine(&eb); err_context: i915_gem_context_put(eb.gem_context); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index a49016f8ee0d..5ecf0afc3e71 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -69,7 +69,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); - err = reloc_gpu_flush(&eb->reloc_cache); + err = reloc_gpu_flush(eb, &eb->reloc_cache); if (err) goto put_rq; GEM_BUG_ON(eb->reloc_cache.rq); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6846241f9079..470a89761fd7 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1360,6 +1360,12 @@ static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) } } +void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj) +{ + list_del(&obj->obj_link); + i915_gem_object_unlock(obj); +} + void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) { i915_gem_ww_ctx_unlock_all(ww); diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 988755dbf4be..f6bef9894111 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -126,5 +126,6 @@ struct i915_gem_ww_ctx { void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx); +void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj); #endif /* __I915_GEM_H__ */ -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:58 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:58 +0200 Subject: [Intel-gfx] [PATCH 09/24] drm/i915: Add ww context handling to context_barrier_task In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-9-maarten.lankhorst@linux.intel.com> This is required if we want to pass a ww context in intel_context_pin and gen6_ppgtt_pin(). Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 55 ++++++++++++++----- .../drm/i915/gem/selftests/i915_gem_context.c | 22 +++----- 2 files changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 46abf903dc8a..9aa9b70a8ecb 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1094,6 +1094,7 @@ I915_SELFTEST_DECLARE(static intel_engine_mask_t context_barrier_inject_fault); static int context_barrier_task(struct i915_gem_context *ctx, intel_engine_mask_t engines, bool (*skip)(struct intel_context *ce, void *data), + int (*pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void *data), int (*emit)(struct i915_request *rq, void *data), void (*task)(void *data), void *data) @@ -1101,6 +1102,7 @@ static int context_barrier_task(struct i915_gem_context *ctx, struct context_barrier_task *cb; struct i915_gem_engines_iter it; struct i915_gem_engines *e; + struct i915_gem_ww_ctx ww; struct intel_context *ce; int err = 0; @@ -1138,10 +1140,21 @@ static int context_barrier_task(struct i915_gem_context *ctx, if (skip && skip(ce, data)) continue; - rq = intel_context_create_request(ce); + i915_gem_ww_ctx_init(&ww, true); +retry: + err = intel_context_pin(ce); + if (err) + goto err; + + if (pin) + err = pin(ce, &ww, data); + if (err) + goto err_unpin; + + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); - break; + goto err_unpin; } err = 0; @@ -1151,6 +1164,16 @@ static int context_barrier_task(struct i915_gem_context *ctx, err = i915_active_add_request(&cb->base, rq); i915_request_add(rq); +err_unpin: + intel_context_unpin(ce); +err: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + if (err) break; } @@ -1206,6 +1229,17 @@ static void set_ppgtt_barrier(void *data) i915_vm_close(old); } +static int pin_ppgtt_update(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void *data) +{ + struct i915_address_space *vm = ce->vm; + + if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915)) + /* ppGTT is not part of the legacy context image */ + return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm)); + + return 0; +} + static int emit_ppgtt_update(struct i915_request *rq, void *data) { struct i915_address_space *vm = rq->context->vm; @@ -1262,20 +1296,10 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data) static bool skip_ppgtt_update(struct intel_context *ce, void *data) { - if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) - return true; - if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915)) - return false; - - if (!atomic_read(&ce->pin_count)) - return true; - - /* ppGTT is not part of the legacy context image */ - if (gen6_ppgtt_pin(i915_vm_to_ppgtt(ce->vm))) - return true; - - return false; + return !ce->state; + else + return !atomic_read(&ce->pin_count); } static int set_ppgtt(struct drm_i915_file_private *file_priv, @@ -1326,6 +1350,7 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv, */ err = context_barrier_task(ctx, ALL_ENGINES, skip_ppgtt_update, + pin_ppgtt_update, emit_ppgtt_update, set_ppgtt_barrier, old); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 76671f587b9d..1217f7a43069 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1917,8 +1917,8 @@ static int mock_context_barrier(void *arg) return -ENOMEM; counter = 0; - err = context_barrier_task(ctx, 0, - NULL, NULL, mock_barrier_task, &counter); + err = context_barrier_task(ctx, 0, NULL, NULL, NULL, + mock_barrier_task, &counter); if (err) { pr_err("Failed at line %d, err=%d\n", __LINE__, err); goto out; @@ -1930,11 +1930,8 @@ static int mock_context_barrier(void *arg) } counter = 0; - err = context_barrier_task(ctx, ALL_ENGINES, - skip_unused_engines, - NULL, - mock_barrier_task, - &counter); + err = context_barrier_task(ctx, ALL_ENGINES, skip_unused_engines, + NULL, NULL, mock_barrier_task, &counter); if (err) { pr_err("Failed at line %d, err=%d\n", __LINE__, err); goto out; @@ -1954,8 +1951,8 @@ static int mock_context_barrier(void *arg) counter = 0; context_barrier_inject_fault = BIT(RCS0); - err = context_barrier_task(ctx, ALL_ENGINES, - NULL, NULL, mock_barrier_task, &counter); + err = context_barrier_task(ctx, ALL_ENGINES, NULL, NULL, NULL, + mock_barrier_task, &counter); context_barrier_inject_fault = 0; if (err == -ENXIO) err = 0; @@ -1969,11 +1966,8 @@ static int mock_context_barrier(void *arg) goto out; counter = 0; - err = context_barrier_task(ctx, ALL_ENGINES, - skip_unused_engines, - NULL, - mock_barrier_task, - &counter); + err = context_barrier_task(ctx, ALL_ENGINES, skip_unused_engines, + NULL, NULL, mock_barrier_task, &counter); if (err) { pr_err("Failed at line %d, err=%d\n", __LINE__, err); goto out; -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:03 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:03 +0200 Subject: [Intel-gfx] [PATCH 14/24] drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-14-maarten.lankhorst@linux.intel.com> This is the last part outside of selftests that still don't use the correct lock ordering of timeline->mutex vs resv_lock. With gem fixed, there are a few places that still get locking wrong: - gvt/scheduler.c - i915_perf.c - Most if not all selftests. Changes since v1: - Add intel_engine_pm_get/put() calls to fix use-after-free when using intel_engine_get_pool(). Signed-off-by: Maarten Lankhorst --- .../gpu/drm/i915/gem/i915_gem_client_blt.c | 78 +++++++-- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 157 +++++++++++------- .../gpu/drm/i915/gem/i915_gem_object_blt.h | 3 + 3 files changed, 164 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c index c182091c00ff..c141d7ce8a75 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c @@ -156,6 +156,7 @@ static void clear_pages_worker(struct work_struct *work) struct clear_pages_work *w = container_of(work, typeof(*w), work); struct drm_i915_gem_object *obj = w->sleeve->vma->obj; struct i915_vma *vma = w->sleeve->vma; + struct i915_gem_ww_ctx ww; struct i915_request *rq; struct i915_vma *batch; int err = w->dma.error; @@ -171,17 +172,20 @@ static void clear_pages_worker(struct work_struct *work) obj->read_domains = I915_GEM_GPU_DOMAINS; obj->write_domain = 0; - err = i915_vma_pin(vma, 0, 0, PIN_USER); - if (unlikely(err)) + i915_gem_ww_ctx_init(&ww, false); + intel_engine_pm_get(w->ce->engine); +retry: + err = intel_context_pin_ww(w->ce, &ww); + if (err) goto out_signal; - batch = intel_emit_vma_fill_blt(w->ce, vma, w->value); + batch = intel_emit_vma_fill_blt(w->ce, vma, &ww, w->value); if (IS_ERR(batch)) { err = PTR_ERR(batch); - goto out_unpin; + goto out_ctx; } - rq = intel_context_create_request(w->ce); + rq = i915_request_create(w->ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); goto out_batch; @@ -223,9 +227,19 @@ static void clear_pages_worker(struct work_struct *work) i915_request_add(rq); out_batch: intel_emit_vma_release(w->ce, batch); -out_unpin: - i915_vma_unpin(vma); +out_ctx: + intel_context_unpin(w->ce); out_signal: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + + i915_vma_unpin(w->sleeve->vma); + intel_engine_pm_put(w->ce->engine); + if (unlikely(err)) { dma_fence_set_error(&w->dma, err); dma_fence_signal(&w->dma); @@ -233,6 +247,44 @@ static void clear_pages_worker(struct work_struct *work) } } +static int pin_wait_clear_pages_work(struct clear_pages_work *w, + struct intel_context *ce) +{ + struct i915_vma *vma = w->sleeve->vma; + struct i915_gem_ww_ctx ww; + int err; + + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(vma->obj, &ww); + if (err) + goto out; + + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); + if (unlikely(err)) + goto out; + + err = i915_sw_fence_await_reservation(&w->wait, + vma->obj->base.resv, NULL, + true, 0, I915_FENCE_GFP); + if (err) + goto err_unpin_vma; + + dma_resv_add_excl_fence(vma->obj->base.resv, &w->dma); + +err_unpin_vma: + if (err) + i915_vma_unpin(vma); +out: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + return err; +} + static int __i915_sw_fence_call clear_pages_work_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) @@ -286,17 +338,9 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0); i915_sw_fence_init(&work->wait, clear_pages_work_notify); - i915_gem_object_lock(obj, NULL); - err = i915_sw_fence_await_reservation(&work->wait, - obj->base.resv, NULL, true, 0, - I915_FENCE_GFP); - if (err < 0) { + err = pin_wait_clear_pages_work(work, ce); + if (err < 0) dma_fence_set_error(&work->dma, err); - } else { - dma_resv_add_excl_fence(obj->base.resv, &work->dma); - err = 0; - } - i915_gem_object_unlock(obj); dma_fence_get(&work->dma); i915_sw_fence_commit(&work->wait); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index 65abc7784009..4d279e490583 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -14,6 +14,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, struct i915_vma *vma, + struct i915_gem_ww_ctx *ww, u32 value) { struct drm_i915_private *i915 = ce->vm->i915; @@ -39,10 +40,24 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, goto out_pm; } + err = i915_gem_object_lock(pool->obj, ww); + if (err) + goto out_put; + + batch = i915_vma_instance(pool->obj, ce->vm, NULL); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto out_put; + } + + err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER); + if (unlikely(err)) + goto out_put; + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC); if (IS_ERR(cmd)) { err = PTR_ERR(cmd); - goto out_put; + goto out_unpin; } rem = vma->size; @@ -84,19 +99,11 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, intel_gt_chipset_flush(ce->vm->gt); - batch = i915_vma_instance(pool->obj, ce->vm, NULL); - if (IS_ERR(batch)) { - err = PTR_ERR(batch); - goto out_put; - } - - err = i915_vma_pin(batch, 0, 0, PIN_USER); - if (unlikely(err)) - goto out_put; - batch->private = pool; return batch; +out_unpin: + i915_vma_unpin(batch); out_put: intel_gt_buffer_pool_put(pool); out_pm: @@ -108,11 +115,9 @@ int intel_emit_vma_mark_active(struct i915_vma *vma, struct i915_request *rq) { int err; - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (err == 0) err = i915_vma_move_to_active(vma, rq, 0); - i915_vma_unlock(vma); if (unlikely(err)) return err; @@ -130,6 +135,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, struct intel_context *ce, u32 value) { + struct i915_gem_ww_ctx ww; struct i915_request *rq; struct i915_vma *batch; struct i915_vma *vma; @@ -139,23 +145,31 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, if (IS_ERR(vma)) return PTR_ERR(vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER); - if (unlikely(err)) - return err; + i915_gem_ww_ctx_init(&ww, true); + intel_engine_pm_get(ce->engine); +retry: + err = i915_gem_object_lock(obj, &ww); + if (err) + goto out; + + err = intel_context_pin_ww(ce, &ww); + if (err) + goto out; + + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); + if (err) + goto out_ctx; - if (obj->cache_dirty & ~obj->cache_coherent) { - i915_gem_object_lock(obj, NULL); + if (obj->cache_dirty & ~obj->cache_coherent) i915_gem_clflush_object(obj, 0); - i915_gem_object_unlock(obj); - } - batch = intel_emit_vma_fill_blt(ce, vma, value); + batch = intel_emit_vma_fill_blt(ce, vma, &ww, value); if (IS_ERR(batch)) { err = PTR_ERR(batch); - goto out_unpin; + goto out_vma; } - rq = intel_context_create_request(ce); + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); goto out_batch; @@ -175,11 +189,9 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, goto out_request; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); if (unlikely(err)) goto out_request; @@ -193,8 +205,18 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, i915_request_add(rq); out_batch: intel_emit_vma_release(ce, batch); -out_unpin: +out_vma: i915_vma_unpin(vma); +out_ctx: + intel_context_unpin(ce); +out: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + intel_engine_pm_put(ce->engine); return err; } @@ -210,6 +232,7 @@ static bool wa_1209644611_applies(struct drm_i915_private *i915, u32 size) } struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, struct i915_vma *src, struct i915_vma *dst) { @@ -236,10 +259,24 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, goto out_pm; } + err = i915_gem_object_lock(pool->obj, ww); + if (err) + goto out_put; + + batch = i915_vma_instance(pool->obj, ce->vm, NULL); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto out_put; + } + + err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER); + if (unlikely(err)) + goto out_put; + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC); if (IS_ERR(cmd)) { err = PTR_ERR(cmd); - goto out_put; + goto out_unpin; } rem = src->size; @@ -296,20 +333,11 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, i915_gem_object_unpin_map(pool->obj); intel_gt_chipset_flush(ce->vm->gt); - - batch = i915_vma_instance(pool->obj, ce->vm, NULL); - if (IS_ERR(batch)) { - err = PTR_ERR(batch); - goto out_put; - } - - err = i915_vma_pin(batch, 0, 0, PIN_USER); - if (unlikely(err)) - goto out_put; - batch->private = pool; return batch; +out_unpin: + i915_vma_unpin(batch); out_put: intel_gt_buffer_pool_put(pool); out_pm: @@ -331,10 +359,9 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, struct drm_i915_gem_object *dst, struct intel_context *ce) { - struct drm_gem_object *objs[] = { &src->base, &dst->base }; struct i915_address_space *vm = ce->vm; struct i915_vma *vma[2], *batch; - struct ww_acquire_ctx acquire; + struct i915_gem_ww_ctx ww; struct i915_request *rq; int err, i; @@ -342,25 +369,36 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, if (IS_ERR(vma[0])) return PTR_ERR(vma[0]); - err = i915_vma_pin(vma[0], 0, 0, PIN_USER); - if (unlikely(err)) - return err; - vma[1] = i915_vma_instance(dst, vm, NULL); if (IS_ERR(vma[1])) - goto out_unpin_src; + return PTR_ERR(vma); - err = i915_vma_pin(vma[1], 0, 0, PIN_USER); + i915_gem_ww_ctx_init(&ww, true); + intel_engine_pm_get(ce->engine); +retry: + err = i915_gem_object_lock(src, &ww); + if (!err) + err = i915_gem_object_lock(dst, &ww); + if (!err) + err = intel_context_pin_ww(ce, &ww); + if (err) + goto out; + + err = i915_vma_pin_ww(vma[0], &ww, 0, 0, PIN_USER); + if (err) + goto out_ctx; + + err = i915_vma_pin_ww(vma[1], &ww, 0, 0, PIN_USER); if (unlikely(err)) goto out_unpin_src; - batch = intel_emit_vma_copy_blt(ce, vma[0], vma[1]); + batch = intel_emit_vma_copy_blt(ce, &ww, vma[0], vma[1]); if (IS_ERR(batch)) { err = PTR_ERR(batch); goto out_unpin_dst; } - rq = intel_context_create_request(ce); + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); goto out_batch; @@ -370,14 +408,10 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, if (unlikely(err)) goto out_request; - err = drm_gem_lock_reservations(objs, ARRAY_SIZE(objs), &acquire); - if (unlikely(err)) - goto out_request; - for (i = 0; i < ARRAY_SIZE(vma); i++) { err = move_to_gpu(vma[i], rq, i); if (unlikely(err)) - goto out_unlock; + goto out_request; } for (i = 0; i < ARRAY_SIZE(vma); i++) { @@ -385,20 +419,19 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, err = i915_vma_move_to_active(vma[i], rq, flags); if (unlikely(err)) - goto out_unlock; + goto out_request; } if (rq->engine->emit_init_breadcrumb) { err = rq->engine->emit_init_breadcrumb(rq); if (unlikely(err)) - goto out_unlock; + goto out_request; } err = rq->engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0); -out_unlock: - drm_gem_unlock_reservations(objs, ARRAY_SIZE(objs), &acquire); + out_request: if (unlikely(err)) i915_request_set_error_once(rq, err); @@ -410,6 +443,16 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, i915_vma_unpin(vma[1]); out_unpin_src: i915_vma_unpin(vma[0]); +out_ctx: + intel_context_unpin(ce); +out: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + intel_engine_pm_put(ce->engine); return err; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h index 8bcd336a90dc..2409fdcccf0e 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h @@ -13,12 +13,15 @@ #include "i915_vma.h" struct drm_i915_gem_object; +struct i915_gem_ww_ctx; struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, struct i915_vma *vma, + struct i915_gem_ww_ctx *ww, u32 value); struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, struct i915_vma *src, struct i915_vma *dst); -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:05 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:05 +0200 Subject: [Intel-gfx] [PATCH 16/24] drm/i915: Convert i915_perf to ww locking as well In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-16-maarten.lankhorst@linux.intel.com> We have the ordering of timeline->mutex vs resv_lock wrong, convert the i915_pin_vma and intel_context_pin as well to future-proof this. We may need to do future changes to do this more transaction-like, and only get down to a single i915_gem_ww_ctx, but for now this should work. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_perf.c | 57 +++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index f35712d04ba4..056e53914760 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1195,24 +1195,39 @@ static struct intel_context *oa_pin_context(struct i915_perf_stream *stream) struct i915_gem_engines_iter it; struct i915_gem_context *ctx = stream->ctx; struct intel_context *ce; - int err; + struct i915_gem_ww_ctx ww; + int err = -ENODEV; for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) { if (ce->engine != stream->engine) /* first match! */ continue; - /* - * As the ID is the gtt offset of the context's vma we - * pin the vma to ensure the ID remains fixed. - */ - err = intel_context_pin(ce); - if (err == 0) { - stream->pinned_ctx = ce; - break; - } + err = 0; + break; } i915_gem_context_unlock_engines(ctx); + if (err) + return ERR_PTR(err); + + i915_gem_ww_ctx_init(&ww, true); +retry: + /* + * As the ID is the gtt offset of the context's vma we + * pin the vma to ensure the ID remains fixed. + */ + err = intel_context_pin_ww(ce, &ww); + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + + if (err) + return ERR_PTR(err); + + stream->pinned_ctx = ce; return stream->pinned_ctx; } @@ -1922,15 +1937,22 @@ emit_oa_config(struct i915_perf_stream *stream, { struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; int err; vma = get_oa_vma(stream, oa_config); if (IS_ERR(vma)) return PTR_ERR(vma); - err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); + i915_gem_ww_ctx_init(&ww, true); +retry: + err = i915_gem_object_lock(vma->obj, &ww); + if (err) + goto err; + + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH); if (err) - goto err_vma_put; + goto err; intel_engine_pm_get(ce->engine); rq = i915_request_create(ce); @@ -1952,11 +1974,9 @@ emit_oa_config(struct i915_perf_stream *stream, goto err_add_request; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, 0); if (!err) err = i915_vma_move_to_active(vma, rq, 0); - i915_vma_unlock(vma); if (err) goto err_add_request; @@ -1970,7 +1990,14 @@ emit_oa_config(struct i915_perf_stream *stream, i915_request_add(rq); err_vma_unpin: i915_vma_unpin(vma); -err_vma_put: +err: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + + i915_gem_ww_ctx_fini(&ww); i915_vma_put(vma); return err; } -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:12 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:12 +0200 Subject: [Intel-gfx] [PATCH 23/24] drm/i915: Ensure we hold the pin mutex In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-23-maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/i915_vma.c | 9 ++++++++- drivers/gpu/drm/i915/i915_vma.h | 3 +++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index 86a5a8ba4f80..bee35fd5a015 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -207,7 +207,7 @@ int intel_renderstate_init(struct intel_renderstate *so, if (err) goto err_context; - err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH); + err = i915_vma_pin_ww(so->vma, &so->ww, 0, 0, PIN_GLOBAL | PIN_HIGH); if (err) goto err_context; diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 1e81b368c792..057aaed17259 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -867,6 +867,8 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, #ifdef CONFIG_PROVE_LOCKING if (debug_locks && lockdep_is_held(&vma->vm->i915->drm.struct_mutex)) WARN_ON(!ww); + if (debug_locks && ww && vma->resv) + assert_vma_held(vma); #endif BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); @@ -1006,8 +1008,13 @@ int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, GEM_BUG_ON(!i915_vma_is_ggtt(vma)); + WARN_ON(!ww && vma->resv && dma_resv_held(vma->resv)); + do { - err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL); + if (ww) + err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL); + else + err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL); if (err != -ENOSPC) { if (!err) { err = i915_vma_wait_for_bind(vma); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 5b3a3c653454..838bbbeb11cc 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -243,6 +243,9 @@ i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, static inline int __must_check i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) { +#ifdef CONFIG_LOCKDEP + WARN_ON_ONCE(vma->resv && dma_resv_held(vma->resv)); +#endif return i915_vma_pin_ww(vma, NULL, size, alignment, flags); } -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:50 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:50 +0200 Subject: [Intel-gfx] [PATCH 01/24] Revert "drm/i915/gem: Drop relocation slowpath". Message-ID: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation slowpath"). We need the slowpath relocation for taking ww-mutex inside the page fault handler, and we will take this mutex when pinning all objects. [mlankhorst: Adjusted for reloc_gpu_flush() changes] Cc: Chris Wilson Cc: Matthew Auld Signed-off-by: Maarten Lankhorst --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 246 +++++++++++++++++- 1 file changed, 245 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 219a36995b96..c141ce1156d7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1705,7 +1705,9 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) * we would try to acquire the struct mutex again. Obviously * this is bad and so lockdep complains vehemently. */ - copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); + pagefault_disable(); + copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0])); + pagefault_enable(); if (unlikely(copied)) { remain = -EFAULT; goto out; @@ -1753,6 +1755,246 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) return remain; } +static int +eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev) +{ + const struct drm_i915_gem_exec_object2 *entry = ev->exec; + struct drm_i915_gem_relocation_entry *relocs = + u64_to_ptr(typeof(*relocs), entry->relocs_ptr); + unsigned int i; + int err; + + for (i = 0; i < entry->relocation_count; i++) { + u64 offset = eb_relocate_entry(eb, ev, &relocs[i]); + + if ((s64)offset < 0) { + err = (int)offset; + goto err; + } + } + err = 0; +err: + reloc_cache_reset(&eb->reloc_cache); + return err; +} + +static int check_relocations(const struct drm_i915_gem_exec_object2 *entry) +{ + const char __user *addr, *end; + unsigned long size; + char __maybe_unused c; + + size = entry->relocation_count; + if (size == 0) + return 0; + + if (size > N_RELOC(ULONG_MAX)) + return -EINVAL; + + addr = u64_to_user_ptr(entry->relocs_ptr); + size *= sizeof(struct drm_i915_gem_relocation_entry); + if (!access_ok(addr, size)) + return -EFAULT; + + end = addr + size; + for (; addr < end; addr += PAGE_SIZE) { + int err = __get_user(c, addr); + if (err) + return err; + } + return __get_user(c, end - 1); +} + +static int eb_copy_relocations(const struct i915_execbuffer *eb) +{ + struct drm_i915_gem_relocation_entry *relocs; + const unsigned int count = eb->buffer_count; + unsigned int i; + int err; + + for (i = 0; i < count; i++) { + const unsigned int nreloc = eb->exec[i].relocation_count; + struct drm_i915_gem_relocation_entry __user *urelocs; + unsigned long size; + unsigned long copied; + + if (nreloc == 0) + continue; + + err = check_relocations(&eb->exec[i]); + if (err) + goto err; + + urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr); + size = nreloc * sizeof(*relocs); + + relocs = kvmalloc_array(size, 1, GFP_KERNEL); + if (!relocs) { + err = -ENOMEM; + goto err; + } + + /* copy_from_user is limited to < 4GiB */ + copied = 0; + do { + unsigned int len = + min_t(u64, BIT_ULL(31), size - copied); + + if (__copy_from_user((char *)relocs + copied, + (char __user *)urelocs + copied, + len)) + goto end; + + copied += len; + } while (copied < size); + + /* + * As we do not update the known relocation offsets after + * relocating (due to the complexities in lock handling), + * we need to mark them as invalid now so that we force the + * relocation processing next time. Just in case the target + * object is evicted and then rebound into its old + * presumed_offset before the next execbuffer - if that + * happened we would make the mistake of assuming that the + * relocations were valid. + */ + if (!user_access_begin(urelocs, size)) + goto end; + + for (copied = 0; copied < nreloc; copied++) + unsafe_put_user(-1, + &urelocs[copied].presumed_offset, + end_user); + user_access_end(); + + eb->exec[i].relocs_ptr = (uintptr_t)relocs; + } + + return 0; + +end_user: + user_access_end(); +end: + kvfree(relocs); + err = -EFAULT; +err: + while (i--) { + relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr); + if (eb->exec[i].relocation_count) + kvfree(relocs); + } + return err; +} + +static int eb_prefault_relocations(const struct i915_execbuffer *eb) +{ + const unsigned int count = eb->buffer_count; + unsigned int i; + + for (i = 0; i < count; i++) { + int err; + + err = check_relocations(&eb->exec[i]); + if (err) + return err; + } + + return 0; +} + +static noinline int eb_relocate_slow(struct i915_execbuffer *eb) +{ + bool have_copy = false; + struct eb_vma *ev; + int err = 0, flush; + +repeat: + if (signal_pending(current)) { + err = -ERESTARTSYS; + goto out; + } + + /* + * We take 3 passes through the slowpatch. + * + * 1 - we try to just prefault all the user relocation entries and + * then attempt to reuse the atomic pagefault disabled fast path again. + * + * 2 - we copy the user entries to a local buffer here outside of the + * local and allow ourselves to wait upon any rendering before + * relocations + * + * 3 - we already have a local copy of the relocation entries, but + * were interrupted (EAGAIN) whilst waiting for the objects, try again. + */ + if (!err) { + err = eb_prefault_relocations(eb); + } else if (!have_copy) { + err = eb_copy_relocations(eb); + have_copy = err == 0; + } else { + cond_resched(); + err = 0; + } + if (err) + goto out; + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + if (!have_copy) { + pagefault_disable(); + err = eb_relocate_vma(eb, ev); + pagefault_enable(); + if (err) + break; + } else { + err = eb_relocate_vma_slow(eb, ev); + if (err) + break; + } + } + + flush = reloc_gpu_flush(&eb->reloc_cache); + if (err && !have_copy) + goto repeat; + + if (!err) + err = flush; + + if (err) + goto err; + + /* + * Leave the user relocations as are, this is the painfully slow path, + * and we want to avoid the complication of dropping the lock whilst + * having buffers reserved in the aperture and so causing spurious + * ENOSPC for random operations. + */ + +err: + if (err == -EAGAIN) + goto repeat; + +out: + if (have_copy) { + const unsigned int count = eb->buffer_count; + unsigned int i; + + for (i = 0; i < count; i++) { + const struct drm_i915_gem_exec_object2 *entry = + &eb->exec[i]; + struct drm_i915_gem_relocation_entry *relocs; + + if (!entry->relocation_count) + continue; + + relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); + kvfree(relocs); + } + } + + return err; +} + static int eb_relocate(struct i915_execbuffer *eb) { int err; @@ -1781,6 +2023,8 @@ static int eb_relocate(struct i915_execbuffer *eb) flush = reloc_gpu_flush(&eb->reloc_cache); if (!err) err = flush; + else + return eb_relocate_slow(eb); } return err; base-commit: 0536dff30eff69abcf6355bdd9b9fdf45a560099 prerequisite-patch-id: e6315738715ac4ffccaeb4c4bf5a94651fb8da1d -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:52 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:52 +0200 Subject: [Intel-gfx] [PATCH 03/24] drm/i915: Remove locking from i915_gem_object_prepare_read/write In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-3-maarten.lankhorst@linux.intel.com> Execbuffer submission will perform its own WW locking, and we cannot rely on the implicit lock there. This also makes it clear that the GVT code will get a lockdep splat when multiple batchbuffer shadows need to be performed in the same instance, fix that up. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 20 ++++++------------- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 13 ++++++++++-- drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 - .../gpu/drm/i915/gem/selftests/huge_pages.c | 5 ++++- .../i915/gem/selftests/i915_gem_coherency.c | 14 +++++++++---- .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++++++++--- drivers/gpu/drm/i915/gt/intel_renderstate.c | 5 ++++- drivers/gpu/drm/i915/gvt/cmd_parser.c | 9 ++++++++- drivers/gpu/drm/i915/i915_gem.c | 20 +++++++++++++++++-- 9 files changed, 70 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index c0acfc97fae3..8ebceebd11b0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -576,19 +576,17 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj, NULL); - if (ret) - return ret; + assert_object_held(obj); ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); if (ret) - goto err_unlock; + return ret; ret = i915_gem_object_pin_pages(obj); if (ret) - goto err_unlock; + return ret; if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || !static_cpu_has(X86_FEATURE_CLFLUSH)) { @@ -616,8 +614,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, err_unpin: i915_gem_object_unpin_pages(obj); -err_unlock: - i915_gem_object_unlock(obj); return ret; } @@ -630,20 +626,18 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj, NULL); - if (ret) - return ret; + assert_object_held(obj); ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, MAX_SCHEDULE_TIMEOUT); if (ret) - goto err_unlock; + return ret; ret = i915_gem_object_pin_pages(obj); if (ret) - goto err_unlock; + return ret; if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || !static_cpu_has(X86_FEATURE_CLFLUSH)) { @@ -680,7 +674,5 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, err_unpin: i915_gem_object_unpin_pages(obj); -err_unlock: - i915_gem_object_unlock(obj); return ret; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index b00b2e49a362..0f0c77bdf160 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1098,11 +1098,14 @@ static void reloc_cache_reset(struct reloc_cache *cache) vaddr = unmask_page(cache->vaddr); if (cache->vaddr & KMAP) { + struct drm_i915_gem_object *obj = + (struct drm_i915_gem_object *)cache->node.mm; if (cache->vaddr & CLFLUSH_AFTER) mb(); kunmap_atomic(vaddr); - i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); + i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); } else { struct i915_ggtt *ggtt = cache_to_ggtt(cache); @@ -1137,10 +1140,16 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj, unsigned int flushes; int err; - err = i915_gem_object_prepare_write(obj, &flushes); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) return ERR_PTR(err); + err = i915_gem_object_prepare_write(obj, &flushes); + if (err) { + i915_gem_object_unlock(obj); + return ERR_PTR(err); + } + BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 5103067269b0..11b8e2735071 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -434,7 +434,6 @@ static inline void i915_gem_object_finish_access(struct drm_i915_gem_object *obj) { i915_gem_object_unpin_pages(obj); - i915_gem_object_unlock(obj); } static inline struct intel_engine_cs * diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index eb2011ccb92b..fff11327a8da 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -964,9 +964,10 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) unsigned long n; int err; + i915_gem_object_lock(obj, NULL); err = i915_gem_object_prepare_read(obj, &needs_flush); if (err) - return err; + goto err_unlock; for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) { u32 *ptr = kmap_atomic(i915_gem_object_get_page(obj, n)); @@ -986,6 +987,8 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) } i915_gem_object_finish_access(obj); +err_unlock: + i915_gem_object_unlock(obj); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 1de2959b153c..dcdfc396f2f8 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -27,9 +27,10 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) u32 *cpu; int err; + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); if (err) - return err; + goto out; page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); @@ -46,7 +47,9 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) kunmap_atomic(map); i915_gem_object_finish_access(ctx->obj); - return 0; +out: + i915_gem_object_unlock(ctx->obj); + return err; } static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) @@ -57,9 +60,10 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) u32 *cpu; int err; + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); if (err) - return err; + goto out; page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); @@ -73,7 +77,9 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) kunmap_atomic(map); i915_gem_object_finish_access(ctx->obj); - return 0; +out: + i915_gem_object_unlock(ctx->obj); + return err; } static int gtt_set(struct context *ctx, unsigned long offset, u32 v) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 438c15ef2184..76671f587b9d 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -461,9 +461,10 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) unsigned int n, m, need_flush; int err; + i915_gem_object_lock(obj, NULL); err = i915_gem_object_prepare_write(obj, &need_flush); if (err) - return err; + goto out; for (n = 0; n < real_page_count(obj); n++) { u32 *map; @@ -479,7 +480,9 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) i915_gem_object_finish_access(obj); obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU; obj->write_domain = 0; - return 0; +out: + i915_gem_object_unlock(obj); + return err; } static noinline int cpu_check(struct drm_i915_gem_object *obj, @@ -488,9 +491,10 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, unsigned int n, m, needs_flush; int err; + i915_gem_object_lock(obj, NULL); err = i915_gem_object_prepare_read(obj, &needs_flush); if (err) - return err; + goto out_unlock; for (n = 0; n < real_page_count(obj); n++) { u32 *map; @@ -527,6 +531,8 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, } i915_gem_object_finish_access(obj); +out_unlock: + i915_gem_object_unlock(obj); return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index f59e7875cc5e..d133e6b40d6c 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -74,9 +74,10 @@ static int render_state_setup(struct intel_renderstate *so, u32 *d; int ret; + i915_gem_object_lock(so->vma->obj, NULL); ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush); if (ret) - return ret; + goto out_unlock; d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0)); @@ -157,6 +158,8 @@ static int render_state_setup(struct intel_renderstate *so, ret = 0; out: i915_gem_object_finish_access(so->vma->obj); +out_unlock: + i915_gem_object_unlock(so->vma->obj); return ret; err: diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index b20db0d965ff..01e125add115 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1904,10 +1904,14 @@ static int perform_bb_shadow(struct parser_exec_state *s) goto err_free_bb; } - ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush); + ret = i915_gem_object_lock_interruptible(bb->obj, NULL); if (ret) goto err_free_obj; + ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush); + if (ret) + goto err_unlock; + bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); if (IS_ERR(bb->va)) { ret = PTR_ERR(bb->va); @@ -1932,6 +1936,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) if (ret) goto err_unmap; + i915_gem_object_unlock(bb->obj); INIT_LIST_HEAD(&bb->list); list_add(&bb->list, &s->workload->shadow_bb); @@ -1958,6 +1963,8 @@ static int perform_bb_shadow(struct parser_exec_state *s) i915_gem_object_unpin_map(bb->obj); err_finish_shmem_access: i915_gem_object_finish_access(bb->obj); +err_unlock: + i915_gem_object_unlock(bb->obj); err_free_obj: i915_gem_object_put(bb->obj); err_free_bb: diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3eedd4e0ebab..6846241f9079 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -335,12 +335,20 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj, u64 remain; int ret; - ret = i915_gem_object_prepare_read(obj, &needs_clflush); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; + ret = i915_gem_object_prepare_read(obj, &needs_clflush); + if (ret) { + i915_gem_object_unlock(obj); + return ret; + } + fence = i915_gem_object_lock_fence(obj); i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); + if (!fence) return -ENOMEM; @@ -734,12 +742,20 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, u64 remain; int ret; - ret = i915_gem_object_prepare_write(obj, &needs_clflush); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; + ret = i915_gem_object_prepare_write(obj, &needs_clflush); + if (ret) { + i915_gem_object_unlock(obj); + return ret; + } + fence = i915_gem_object_lock_fence(obj); i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); + if (!fence) return -ENOMEM; -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:51 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:51 +0200 Subject: [Intel-gfx] [PATCH 02/24] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-2-maarten.lankhorst@linux.intel.com> i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory eviction. We don't use it yet, but lets start adding the definition first. To use it, we have to pass a non-NULL ww to gem_object_lock, and don't unlock directly. It is done in i915_gem_ww_ctx_fini. Changes since v1: - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +- .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- drivers/gpu/drm/i915/i915_gem.h | 11 ++++ drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- .../drm/i915/selftests/intel_memory_region.c | 2 +- 25 files changed, 174 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a9f752d26b4e..afa4328c3f54 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) { - i915_gem_object_lock(vma->obj); + i915_gem_object_lock(vma->obj, NULL); if (flags & PLANE_HAS_FENCE) i915_vma_unpin_fence(vma); i915_gem_object_unpin_from_display_plane(vma); @@ -17112,7 +17112,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, if (!intel_fb->frontbuffer) return -ENOMEM; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); tiling = i915_gem_object_get_tiling(obj); stride = i915_gem_object_get_stride(obj); i915_gem_object_unlock(obj); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c index d3a86a4d5c04..c182091c00ff 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c @@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0); i915_sw_fence_init(&work->wait, clear_pages_work_notify); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_sw_fence_await_reservation(&work->wait, obj->base.resv, NULL, true, 0, I915_FENCE_GFP); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index f5d59d18cd5b..46abf903dc8a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx) continue; rcu_read_unlock(); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); list_for_each_entry(lut, &obj->lut_list, obj_link) { if (lut->ctx != ctx) continue; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 2679380159fc..27fddc22a7c6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_dire if (err) return err; - err = i915_gem_object_lock_interruptible(obj); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) goto out; @@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direct if (err) return err; - err = i915_gem_object_lock_interruptible(obj); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 7f76fc68f498..c0acfc97fae3 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -32,7 +32,7 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) if (!i915_gem_object_is_framebuffer(obj)) return; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); __i915_gem_object_flush_for_display(obj); i915_gem_object_unlock(obj); } @@ -197,7 +197,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (ret) return ret; - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; @@ -536,7 +536,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, if (err) goto out; - err = i915_gem_object_lock_interruptible(obj); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) goto out_unpin; @@ -576,7 +576,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; @@ -630,7 +630,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c141ce1156d7..b00b2e49a362 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -815,7 +815,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, if (err == 0) { /* And nor has this handle */ struct drm_i915_gem_object *obj = vma->obj; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); if (idr_find(&eb->file->object_idr, handle) == obj) { list_add(&lut->obj_link, &obj->lut_list); } else { @@ -1178,7 +1178,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, if (use_cpu_reloc(cache, obj)) return NULL; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index b6ec5b50d93b..b59e2d40c347 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -108,7 +108,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) struct i915_lut_handle *lut, *ln; LIST_HEAD(close); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { struct i915_gem_context *ctx = lut->ctx; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 2faa481cc18f..5103067269b0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -110,20 +110,44 @@ i915_gem_object_put(struct drm_i915_gem_object *obj) #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv) -static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj) +static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + bool intr) { - dma_resv_lock(obj->base.resv, NULL); + int ret; + + if (intr) + ret = dma_resv_lock_interruptible(obj->base.resv, ww ? &ww->ctx : NULL); + else + ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL); + + if (!ret && ww) + list_add_tail(&obj->obj_link, &ww->obj_list); + if (ret == -EALREADY) + ret = 0; + + if (ret == -EDEADLK) + ww->contended = obj; + + return ret; } -static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) +static inline int i915_gem_object_lock(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww) { - return dma_resv_trylock(obj->base.resv); + return __i915_gem_object_lock(obj, ww, ww && ww->intr); } -static inline int -i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj) +static inline int i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww) { - return dma_resv_lock_interruptible(obj->base.resv, NULL); + WARN_ON(ww && !ww->intr); + return __i915_gem_object_lock(obj, ww, true); +} + +static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) +{ + return dma_resv_trylock(obj->base.resv); } static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index f457d7130491..65abc7784009 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -144,7 +144,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, return err; if (obj->cache_dirty & ~obj->cache_coherent) { - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); i915_gem_clflush_object(obj, 0); i915_gem_object_unlock(obj); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index b1f82a11aef2..3740c0080e38 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -122,6 +122,15 @@ struct drm_i915_gem_object { */ struct list_head lut_list; + /** + * @obj_link: Link into @i915_gem_ww_ctx.obj_list + * + * When we lock this object through i915_gem_object_lock() with a + * context, we add it to the list to ensure we can unlock everything + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. + */ + struct list_head obj_link; + /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; union { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 3d215164dd5a..40d3e40500fa 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c @@ -84,7 +84,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) spin_unlock_irqrestore(&i915->mm.obj_lock, flags); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); drm_WARN_ON(&i915->drm, i915_gem_object_set_to_gtt_domain(obj, false)); i915_gem_object_unlock(obj); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c index 0158e49bf9bb..65fbf29c4852 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c @@ -249,7 +249,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, * whilst executing a fenced command for an untiled object. */ - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); if (i915_gem_object_is_framebuffer(obj)) { i915_gem_object_unlock(obj); return -EBUSY; diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index 8291ede6902c..eb2011ccb92b 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -947,7 +947,7 @@ static int gpu_write(struct intel_context *ce, { int err; - i915_gem_object_lock(vma->obj); + i915_gem_object_lock(vma->obj, NULL); err = i915_gem_object_set_to_gtt_domain(vma->obj, true); i915_gem_object_unlock(vma->obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index 8fe3ad2ee34e..efaa77010d6d 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -75,7 +75,7 @@ static int __igt_client_fill(struct intel_engine_cs *engine) if (err) goto err_unpin; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_cpu_domain(obj, false); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 87d7d8aa080f..1de2959b153c 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -82,7 +82,7 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v) u32 __iomem *map; int err = 0; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); i915_gem_object_unlock(ctx->obj); if (err) @@ -115,7 +115,7 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) u32 __iomem *map; int err = 0; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); i915_gem_object_unlock(ctx->obj); if (err) @@ -147,7 +147,7 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v) u32 *map; int err; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_wc_domain(ctx->obj, true); i915_gem_object_unlock(ctx->obj); if (err) @@ -170,7 +170,7 @@ static int wc_get(struct context *ctx, unsigned long offset, u32 *v) u32 *map; int err; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_wc_domain(ctx->obj, false); i915_gem_object_unlock(ctx->obj); if (err) @@ -193,7 +193,7 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) u32 *cs; int err; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); i915_gem_object_unlock(ctx->obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index b81978890641..438c15ef2184 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -950,7 +950,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, if (IS_ERR(vma)) return PTR_ERR(vma); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, false); i915_gem_object_unlock(obj); if (err) @@ -1706,7 +1706,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, i915_request_add(rq); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_cpu_domain(obj, false); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 9c7402ce5bf9..9fb95a45bcad 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -103,7 +103,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj, GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) { @@ -188,7 +188,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj, GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) { diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c index 34932871b3a5..a94243dc4c5c 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c @@ -44,7 +44,7 @@ static int mock_phys_object(void *arg) } /* Make the object dirty so that put_pages must do copy back the data */ - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) { diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 32785463ec9e..6e4f7a9099d5 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -214,7 +214,7 @@ static int check_whitelist(struct i915_gem_context *ctx, return PTR_ERR(results); err = 0; - i915_gem_object_lock(results); + i915_gem_object_lock(results, NULL); intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */ err = i915_gem_object_set_to_cpu_domain(results, false); i915_gem_object_unlock(results); diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 8b87f130f7f1..b20db0d965ff 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -2994,7 +2994,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) goto put_obj; } - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); ret = i915_gem_object_set_to_cpu_domain(obj, false); i915_gem_object_unlock(obj); if (ret) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0cbcb9f54e7d..3eedd4e0ebab 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -420,7 +420,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, GEM_BUG_ON(!drm_mm_node_allocated(&node)); } - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) goto out_unpin; @@ -619,7 +619,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, GEM_BUG_ON(!drm_mm_node_allocated(&node)); } - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) goto out_unpin; @@ -1272,7 +1272,7 @@ int i915_gem_freeze_late(struct drm_i915_private *i915) i915_gem_drain_freed_objects(i915); list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) { - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); drm_WARN_ON(&i915->drm, i915_gem_object_set_to_cpu_domain(obj, true)); i915_gem_object_unlock(obj); @@ -1326,6 +1326,52 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) return ret; } +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr) +{ + ww_acquire_init(&ww->ctx, &reservation_ww_class); + INIT_LIST_HEAD(&ww->obj_list); + ww->intr = intr; + ww->contended = NULL; +} + +static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) +{ + struct drm_i915_gem_object *obj; + + while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { + list_del(&obj->obj_link); + i915_gem_object_unlock(obj); + } +} + +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) +{ + i915_gem_ww_ctx_unlock_all(ww); + WARN_ON(ww->contended); + ww_acquire_fini(&ww->ctx); +} + +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww) +{ + int ret = 0; + + if (WARN_ON(!ww->contended)) + return -EINVAL; + + i915_gem_ww_ctx_unlock_all(ww); + if (ww->intr) + ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx); + else + dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx); + + if (!ret) + list_add_tail(&ww->contended->obj_link, &ww->obj_list); + + ww->contended = NULL; + + return ret; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/mock_gem_device.c" #include "selftests/i915_gem.c" diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 1753c84d6c0d..988755dbf4be 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -116,4 +116,15 @@ static inline bool __tasklet_is_scheduled(struct tasklet_struct *t) return test_bit(TASKLET_STATE_SCHED, &t->state); } +struct i915_gem_ww_ctx { + struct ww_acquire_ctx ctx; + struct list_head obj_list; + bool intr; + struct drm_i915_gem_object *contended; +}; + +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx); + #endif /* __I915_GEM_H__ */ diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c index 88d400b9df88..23a6132c5f4e 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c @@ -199,11 +199,52 @@ static int igt_gem_hibernate(void *arg) return err; } +static int igt_gem_ww_ctx(void *arg) +{ + struct drm_i915_private *i915 = arg; + struct drm_i915_gem_object *obj, *obj2; + struct i915_gem_ww_ctx ww; + int err = 0; + + obj = i915_gem_object_create_internal(i915, PAGE_SIZE); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE); + if (IS_ERR(obj)) { + err = PTR_ERR(obj); + goto put1; + } + + i915_gem_ww_ctx_init(&ww, true); +retry: + /* Lock the objects, twice for good measure (-EALREADY handling) */ + err = i915_gem_object_lock(obj, &ww); + if (!err) + err = i915_gem_object_lock_interruptible(obj, &ww); + if (!err) + err = i915_gem_object_lock_interruptible(obj2, &ww); + if (!err) + err = i915_gem_object_lock(obj2, &ww); + + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + i915_gem_object_put(obj2); +put1: + i915_gem_object_put(obj); + return err; +} + int i915_gem_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { SUBTEST(igt_gem_suspend), SUBTEST(igt_gem_hibernate), + SUBTEST(igt_gem_ww_ctx), }; if (intel_gt_is_wedged(&i915->gt)) diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c index af89c7fc8f59..88c5e9acb84c 100644 --- a/drivers/gpu/drm/i915/selftests/i915_vma.c +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c @@ -892,7 +892,7 @@ static int igt_vma_remapped_gtt(void *arg) unsigned int x, y; int err; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c index 6e80d99048e4..957a7a52def7 100644 --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c @@ -509,7 +509,7 @@ static int igt_lmem_write_cpu(void *arg) if (err) goto out_unpin; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_wc_domain(obj, true); i915_gem_object_unlock(obj); if (err) -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:00 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:00 +0200 Subject: [Intel-gfx] [PATCH 11/24] drm/i915: Pin engine before pinning all objects, v4. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-11-maarten.lankhorst@linux.intel.com> We want to lock all gem objects, including the engine context objects, rework the throttling to ensure that we can do this. Now we only throttle once, but can take eb_pin_engine while acquiring objects. This means we will have to drop the lock to wait. If we don't have to throttle we can still take the fastpath, if not we will take the slowpath and wait for the throttle request while unlocked. The engine has to be pinned as first step, otherwise gpu relocations won't work. Changes since v1: - Only need to get a throttled request in the fastpath, no need for a global flag any more. - Always free the waited request correctly. Changes since v2: - Use intel_engine_pm_get()/put() to keeep engine pool alive during EDEADLK handling. Changes since v3: - Fix small rq leak. Signed-off-by: Maarten Lankhorst --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 185 ++++++++++++------ 1 file changed, 129 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 3dc0c0eb0e05..0b012abbdad5 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -55,7 +55,8 @@ enum { #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) #define __EXEC_HAS_RELOC BIT(31) -#define __EXEC_INTERNAL_FLAGS (~0u << 31) +#define __EXEC_ENGINE_PINNED BIT(30) +#define __EXEC_INTERNAL_FLAGS (~0u << 30) #define UPDATE PIN_OFFSET_FIXED #define BATCH_OFFSET_BIAS (256*1024) @@ -294,6 +295,9 @@ struct i915_execbuffer { }; static int eb_parse(struct i915_execbuffer *eb); +static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, + bool throttle); +static void eb_unpin_engine(struct i915_execbuffer *eb); static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) { @@ -925,7 +929,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) } } -static void eb_release_vmas(const struct i915_execbuffer *eb, bool final) +static void eb_release_vmas(struct i915_execbuffer *eb, bool final) { const unsigned int count = eb->buffer_count; unsigned int i; @@ -942,6 +946,8 @@ static void eb_release_vmas(const struct i915_execbuffer *eb, bool final) if (final) i915_vma_put(vma); } + + eb_unpin_engine(eb); } static void eb_destroy(const struct i915_execbuffer *eb) @@ -1970,7 +1976,8 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb) return 0; } -static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) +static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb, + struct i915_request *rq) { bool have_copy = false; struct eb_vma *ev; @@ -1986,6 +1993,21 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) eb_release_vmas(eb, false); i915_gem_ww_ctx_fini(&eb->ww); + if (rq) { + /* nonblocking is always false */ + if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, + MAX_SCHEDULE_TIMEOUT) < 0) { + i915_request_put(rq); + rq = NULL; + + err = -EINTR; + goto err_relock; + } + + i915_request_put(rq); + rq = NULL; + } + /* * We take 3 passes through the slowpatch. * @@ -2009,14 +2031,25 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) err = 0; } - flush_workqueue(eb->i915->mm.userptr_wq); + if (!err) + flush_workqueue(eb->i915->mm.userptr_wq); +err_relock: i915_gem_ww_ctx_init(&eb->ww, true); if (err) goto out; /* reacquire the objects */ repeat_validate: + rq = eb_pin_engine(eb, false); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err; + } + + /* We didn't throttle, should be NULL */ + GEM_WARN_ON(rq); + err = eb_validate_vmas(eb); if (err) goto err; @@ -2091,14 +2124,49 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) } } + if (rq) + i915_request_put(rq); + return err; } static int eb_relocate_parse(struct i915_execbuffer *eb) { int err; + struct i915_request *rq = NULL; + bool throttle = true; retry: + rq = eb_pin_engine(eb, throttle); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + rq = NULL; + if (err != -EDEADLK) + return err; + + goto err; + } + + if (rq) { + bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; + + /* Need to drop all locks now for throttling, take slowpath */ + err = i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, 0); + if (err == -ETIME) { + if (nonblock) { + err = -EWOULDBLOCK; + i915_request_put(rq); + goto err; + } + goto slow; + } + i915_request_put(rq); + rq = NULL; + } + + /* only throttle once, even if we didn't need to throttle */ + throttle = false; + err = eb_validate_vmas(eb); if (err == -EAGAIN) goto slow; @@ -2139,7 +2207,7 @@ static int eb_relocate_parse(struct i915_execbuffer *eb) return err; slow: - err = eb_relocate_parse_slow(eb); + err = eb_relocate_parse_slow(eb, rq); if (err) /* * If the user expects the execobject.offset and @@ -2565,7 +2633,7 @@ static const enum intel_engine_id user_ring_map[] = { [I915_EXEC_VEBOX] = VECS0 }; -static struct i915_request *eb_throttle(struct intel_context *ce) +static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce) { struct intel_ring *ring = ce->ring; struct intel_timeline *tl = ce->timeline; @@ -2599,22 +2667,17 @@ static struct i915_request *eb_throttle(struct intel_context *ce) return i915_request_get(rq); } -static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) +static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, bool throttle) { + struct intel_context *ce = eb->context; struct intel_timeline *tl; - struct i915_request *rq; + struct i915_request *rq = NULL; int err; - /* - * ABI: Before userspace accesses the GPU (e.g. execbuffer), report - * EIO if the GPU is already wedged. - */ - err = intel_gt_terminally_wedged(ce->engine->gt); - if (err) - return err; + GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED); if (unlikely(intel_context_is_banned(ce))) - return -EIO; + return ERR_PTR(-EIO); /* * Pinning the contexts may generate requests in order to acquire @@ -2623,7 +2686,7 @@ static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) */ err = intel_context_pin(ce); if (err) - return err; + return ERR_PTR(err); /* * Take a local wakeref for preparing to dispatch the execbuf as @@ -2635,45 +2698,17 @@ static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) */ tl = intel_context_timeline_lock(ce); if (IS_ERR(tl)) { - err = PTR_ERR(tl); - goto err_unpin; + intel_context_unpin(ce); + return ERR_CAST(tl); } intel_context_enter(ce); - rq = eb_throttle(ce); - + if (throttle) + rq = eb_throttle(eb, ce); intel_context_timeline_unlock(tl); - if (rq) { - bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; - long timeout; - - timeout = MAX_SCHEDULE_TIMEOUT; - if (nonblock) - timeout = 0; - - timeout = i915_request_wait(rq, - I915_WAIT_INTERRUPTIBLE, - timeout); - i915_request_put(rq); - - if (timeout < 0) { - err = nonblock ? -EWOULDBLOCK : timeout; - goto err_exit; - } - } - - eb->engine = ce->engine; - eb->context = ce; - return 0; - -err_exit: - mutex_lock(&tl->mutex); - intel_context_exit(ce); - intel_context_timeline_unlock(tl); -err_unpin: - intel_context_unpin(ce); - return err; + eb->args->flags |= __EXEC_ENGINE_PINNED; + return rq; } static void eb_unpin_engine(struct i915_execbuffer *eb) @@ -2681,6 +2716,11 @@ static void eb_unpin_engine(struct i915_execbuffer *eb) struct intel_context *ce = eb->context; struct intel_timeline *tl = ce->timeline; + if (!(eb->args->flags & __EXEC_ENGINE_PINNED)) + return; + + eb->args->flags &= ~__EXEC_ENGINE_PINNED; + mutex_lock(&tl->mutex); intel_context_exit(ce); mutex_unlock(&tl->mutex); @@ -2732,7 +2772,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb) } static int -eb_pin_engine(struct i915_execbuffer *eb) +eb_select_engine(struct i915_execbuffer *eb) { struct intel_context *ce; unsigned int idx; @@ -2747,10 +2787,43 @@ eb_pin_engine(struct i915_execbuffer *eb) if (IS_ERR(ce)) return PTR_ERR(ce); - err = __eb_pin_engine(eb, ce); - intel_context_put(ce); + intel_gt_pm_get(ce->engine->gt); + if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { + err = intel_context_alloc_state(ce); + if (err) + goto err; + } + + /* + * ABI: Before userspace accesses the GPU (e.g. execbuffer), report + * EIO if the GPU is already wedged. + */ + err = intel_gt_terminally_wedged(ce->engine->gt); + if (err) + goto err; + + eb->context = ce; + eb->engine = ce->engine; + + /* + * Make sure engine pool stays alive even if we call intel_context_put + * during ww handling. The pool is destroyed when last pm reference + * is dropped, which breaks our -EDEADLK handling. + */ return err; + +err: + intel_gt_pm_put(ce->engine->gt); + intel_context_put(ce); + return err; +} + +static void +eb_put_engine(struct i915_execbuffer *eb) +{ + intel_gt_pm_put(eb->engine->gt); + intel_context_put(eb->context); } static void @@ -3007,7 +3080,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_destroy; - err = eb_pin_engine(&eb); + err = eb_select_engine(&eb); if (unlikely(err)) goto err_context; @@ -3146,7 +3219,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (eb.reloc_pool) intel_gt_buffer_pool_put(eb.reloc_pool); err_engine: - eb_unpin_engine(&eb); + eb_put_engine(&eb); err_context: i915_gem_context_put(eb.gem_context); err_destroy: -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:01 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:01 +0200 Subject: [Intel-gfx] [PATCH 12/24] drm/i915: Rework intel_context pinning to do everything outside of pin_mutex In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-12-maarten.lankhorst@linux.intel.com> Instead of doing everything inside of pin_mutex, we move all pinning outside. Because i915_active has its own reference counting and pinning is also having the same issues vs mutexes, we make sure everything is pinned first, so the pinning in i915_active only needs to bump refcounts. This allows us to take pin refcounts correctly all the time. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 232 +++++++++++------- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 34 ++- .../gpu/drm/i915/gt/intel_ring_submission.c | 13 +- drivers/gpu/drm/i915/gt/mock_engine.c | 13 +- 5 files changed, 190 insertions(+), 106 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index e4aece20bc80..c039e87a46c4 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -93,79 +93,6 @@ static void intel_context_active_release(struct intel_context *ce) i915_active_release(&ce->active); } -int __intel_context_do_pin(struct intel_context *ce) -{ - int err; - - if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) { - err = intel_context_alloc_state(ce); - if (err) - return err; - } - - err = i915_active_acquire(&ce->active); - if (err) - return err; - - if (mutex_lock_interruptible(&ce->pin_mutex)) { - err = -EINTR; - goto out_release; - } - - if (unlikely(intel_context_is_closed(ce))) { - err = -ENOENT; - goto out_unlock; - } - - if (likely(!atomic_add_unless(&ce->pin_count, 1, 0))) { - err = intel_context_active_acquire(ce); - if (unlikely(err)) - goto out_unlock; - - err = ce->ops->pin(ce); - if (unlikely(err)) - goto err_active; - - CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", - i915_ggtt_offset(ce->ring->vma), - ce->ring->head, ce->ring->tail); - - smp_mb__before_atomic(); /* flush pin before it is visible */ - atomic_inc(&ce->pin_count); - } - - GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */ - GEM_BUG_ON(i915_active_is_idle(&ce->active)); - goto out_unlock; - -err_active: - intel_context_active_release(ce); -out_unlock: - mutex_unlock(&ce->pin_mutex); -out_release: - i915_active_release(&ce->active); - return err; -} - -void intel_context_unpin(struct intel_context *ce) -{ - if (!atomic_dec_and_test(&ce->pin_count)) - return; - - CE_TRACE(ce, "unpin\n"); - ce->ops->unpin(ce); - - /* - * Once released, we may asynchronously drop the active reference. - * As that may be the only reference keeping the context alive, - * take an extra now so that it is not freed before we finish - * dereferencing it. - */ - intel_context_get(ce); - intel_context_active_release(ce); - intel_context_put(ce); -} - static int __context_pin_state(struct i915_vma *vma) { unsigned int bias = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS; @@ -225,6 +152,138 @@ static void __ring_retire(struct intel_ring *ring) i915_active_release(&ring->vma->active); } +static int intel_context_pre_pin(struct intel_context *ce) +{ + int err; + + CE_TRACE(ce, "active\n"); + + err = __ring_active(ce->ring); + if (err) + return err; + + err = intel_timeline_pin(ce->timeline); + if (err) + goto err_ring; + + if (!ce->state) + return 0; + + err = __context_pin_state(ce->state); + if (err) + goto err_timeline; + + + return 0; + +err_timeline: + intel_timeline_unpin(ce->timeline); +err_ring: + __ring_retire(ce->ring); + return err; +} + +static void intel_context_post_unpin(struct intel_context *ce) +{ + if (ce->state) + __context_unpin_state(ce->state); + + intel_timeline_unpin(ce->timeline); + __ring_retire(ce->ring); +} + +int __intel_context_do_pin(struct intel_context *ce) +{ + bool handoff = false; + void *vaddr; + int err = 0; + + if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) { + err = intel_context_alloc_state(ce); + if (err) + return err; + } + + /* + * We always pin the context/ring/timeline here, to ensure a pin + * refcount for __intel_context_active(), which prevent a lock + * inversion of ce->pin_mutex vs dma_resv_lock(). + */ + err = intel_context_pre_pin(ce); + if (err) + return err; + + err = i915_active_acquire(&ce->active); + if (err) + goto err_ctx_unpin; + + err = ce->ops->pre_pin(ce, &vaddr); + if (err) + goto err_release; + + err = mutex_lock_interruptible(&ce->pin_mutex); + if (err) + goto err_post_unpin; + + if (unlikely(intel_context_is_closed(ce))) { + err = -ENOENT; + goto err_unlock; + } + + if (likely(!atomic_add_unless(&ce->pin_count, 1, 0))) { + err = intel_context_active_acquire(ce); + if (unlikely(err)) + goto err_unlock; + + err = ce->ops->pin(ce, vaddr); + if (err) { + intel_context_active_release(ce); + goto err_unlock; + } + + CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", + i915_ggtt_offset(ce->ring->vma), + ce->ring->head, ce->ring->tail); + + handoff = true; + smp_mb__before_atomic(); /* flush pin before it is visible */ + atomic_inc(&ce->pin_count); + } + + GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */ + +err_unlock: + mutex_unlock(&ce->pin_mutex); +err_post_unpin: + if (!handoff) + ce->ops->post_unpin(ce); +err_release: + i915_active_release(&ce->active); +err_ctx_unpin: + intel_context_post_unpin(ce); + return err; +} + +void intel_context_unpin(struct intel_context *ce) +{ + if (!atomic_dec_and_test(&ce->pin_count)) + return; + + CE_TRACE(ce, "unpin\n"); + ce->ops->unpin(ce); + ce->ops->post_unpin(ce); + + /* + * Once released, we may asynchronously drop the active reference. + * As that may be the only reference keeping the context alive, + * take an extra now so that it is not freed before we finish + * dereferencing it. + */ + intel_context_get(ce); + intel_context_active_release(ce); + intel_context_put(ce); +} + __i915_active_call static void __intel_context_retire(struct i915_active *active) { @@ -235,12 +294,7 @@ static void __intel_context_retire(struct i915_active *active) intel_context_get_avg_runtime_ns(ce)); set_bit(CONTEXT_VALID_BIT, &ce->flags); - if (ce->state) - __context_unpin_state(ce->state); - - intel_timeline_unpin(ce->timeline); - __ring_retire(ce->ring); - + intel_context_post_unpin(ce); intel_context_put(ce); } @@ -249,29 +303,25 @@ static int __intel_context_active(struct i915_active *active) struct intel_context *ce = container_of(active, typeof(*ce), active); int err; - CE_TRACE(ce, "active\n"); - intel_context_get(ce); + /* everything should already be activated by intel_context_pre_pin() */ err = __ring_active(ce->ring); - if (err) + if (GEM_WARN_ON(err)) goto err_put; err = intel_timeline_pin(ce->timeline); - if (err) + if (GEM_WARN_ON(err)) goto err_ring; - if (!ce->state) - return 0; - - err = __context_pin_state(ce->state); - if (err) - goto err_timeline; + if (ce->state) { + GEM_WARN_ON(!i915_active_acquire_if_busy(&ce->state->active)); + __i915_vma_pin(ce->state); + i915_vma_make_unshrinkable(ce->state); + } return 0; -err_timeline: - intel_timeline_unpin(ce->timeline); err_ring: __ring_retire(ce->ring); err_put: diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 4954b0df4864..ca8e05b4d3ef 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -30,8 +30,10 @@ struct intel_ring; struct intel_context_ops { int (*alloc)(struct intel_context *ce); - int (*pin)(struct intel_context *ce); + int (*pre_pin)(struct intel_context *ce, void **vaddr); + int (*pin)(struct intel_context *ce, void *vaddr); void (*unpin)(struct intel_context *ce); + void (*post_unpin)(struct intel_context *ce); void (*enter)(struct intel_context *ce); void (*exit)(struct intel_context *ce); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6fc0966b75ff..3d6a82b6648e 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3269,7 +3269,10 @@ static void execlists_context_unpin(struct intel_context *ce) { check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET, ce->engine); +} +static void execlists_context_post_unpin(struct intel_context *ce) +{ i915_gem_object_unpin_map(ce->state->obj); } @@ -3431,20 +3434,23 @@ __execlists_update_reg_state(const struct intel_context *ce, } static int -__execlists_context_pin(struct intel_context *ce, - struct intel_engine_cs *engine) +execlists_context_pre_pin(struct intel_context *ce, void **vaddr) { - void *vaddr; - GEM_BUG_ON(!ce->state); GEM_BUG_ON(!i915_vma_is_pinned(ce->state)); - vaddr = i915_gem_object_pin_map(ce->state->obj, - i915_coherent_map_type(engine->i915) | + *vaddr = i915_gem_object_pin_map(ce->state->obj, + i915_coherent_map_type(ce->engine->i915) | I915_MAP_OVERRIDE); - if (IS_ERR(vaddr)) - return PTR_ERR(vaddr); + return PTR_ERR_OR_ZERO(*vaddr); +} + +static int +__execlists_context_pin(struct intel_context *ce, + struct intel_engine_cs *engine, + void *vaddr) +{ ce->lrc.lrca = lrc_descriptor(ce, engine) | CTX_DESC_FORCE_RESTORE; ce->lrc_reg_state = vaddr + LRC_STATE_OFFSET; __execlists_update_reg_state(ce, engine, ce->ring->tail); @@ -3452,9 +3458,9 @@ __execlists_context_pin(struct intel_context *ce, return 0; } -static int execlists_context_pin(struct intel_context *ce) +static int execlists_context_pin(struct intel_context *ce, void *vaddr) { - return __execlists_context_pin(ce, ce->engine); + return __execlists_context_pin(ce, ce->engine, vaddr); } static int execlists_context_alloc(struct intel_context *ce) @@ -3480,8 +3486,10 @@ static void execlists_context_reset(struct intel_context *ce) static const struct intel_context_ops execlists_context_ops = { .alloc = execlists_context_alloc, + .pre_pin = execlists_context_pre_pin, .pin = execlists_context_pin, .unpin = execlists_context_unpin, + .post_unpin = execlists_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, @@ -5398,13 +5406,13 @@ static int virtual_context_alloc(struct intel_context *ce) return __execlists_context_alloc(ce, ve->siblings[0]); } -static int virtual_context_pin(struct intel_context *ce) +static int virtual_context_pin(struct intel_context *ce, void *vaddr) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); int err; /* Note: we must use a real engine class for setting up reg state */ - err = __execlists_context_pin(ce, ve->siblings[0]); + err = __execlists_context_pin(ce, ve->siblings[0], vaddr); if (err) return err; @@ -5437,8 +5445,10 @@ static void virtual_context_exit(struct intel_context *ce) static const struct intel_context_ops virtual_context_ops = { .alloc = virtual_context_alloc, + .pre_pin = execlists_context_pre_pin, .pin = virtual_context_pin, .unpin = execlists_context_unpin, + .post_unpin = execlists_context_post_unpin, .enter = virtual_context_enter, .exit = virtual_context_exit, diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index d9c1701061b9..f9ef34a489ec 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -496,6 +496,10 @@ static void __context_unpin_ppgtt(struct intel_context *ce) } static void ring_context_unpin(struct intel_context *ce) +{ +} + +static void ring_context_post_unpin(struct intel_context *ce) { __context_unpin_ppgtt(ce); } @@ -584,11 +588,16 @@ static int ring_context_alloc(struct intel_context *ce) return 0; } -static int ring_context_pin(struct intel_context *ce) +static int ring_context_pre_pin(struct intel_context *ce, void **unused) { return __context_pin_ppgtt(ce); } +static int ring_context_pin(struct intel_context *ce, void *unused) +{ + return 0; +} + static void ring_context_reset(struct intel_context *ce) { intel_ring_reset(ce->ring, ce->ring->emit); @@ -597,8 +606,10 @@ static void ring_context_reset(struct intel_context *ce) static const struct intel_context_ops ring_context_ops = { .alloc = ring_context_alloc, + .pre_pin = ring_context_pre_pin, .pin = ring_context_pin, .unpin = ring_context_unpin, + .post_unpin = ring_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index b8dd3cbc8696..62664601e683 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -131,6 +131,10 @@ static void mock_context_unpin(struct intel_context *ce) { } +static void mock_context_post_unpin(struct intel_context *ce) +{ +} + static void mock_context_destroy(struct kref *ref) { struct intel_context *ce = container_of(ref, typeof(*ce), ref); @@ -164,7 +168,12 @@ static int mock_context_alloc(struct intel_context *ce) return 0; } -static int mock_context_pin(struct intel_context *ce) +static int mock_context_pre_pin(struct intel_context *ce, void **unused) +{ + return 0; +} + +static int mock_context_pin(struct intel_context *ce, void *unused) { return 0; } @@ -176,8 +185,10 @@ static void mock_context_reset(struct intel_context *ce) static const struct intel_context_ops mock_context_ops = { .alloc = mock_context_alloc, + .pre_pin = mock_context_pre_pin, .pin = mock_context_pin, .unpin = mock_context_unpin, + .post_unpin = mock_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:02 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:02 +0200 Subject: [Intel-gfx] [PATCH 13/24] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-13-maarten.lankhorst@linux.intel.com> As a preparation step for full object locking and wait/wound handling during pin and object mapping, ensure that we always pass the ww context in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this happens. This also requires changing the order of eb_parse slightly, to ensure we pass ww at a point where we could still handle -EDEADLK safely. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 140 ++++++++++-------- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +- drivers/gpu/drm/i915/gt/intel_context.c | 65 +++++--- drivers/gpu/drm/i915/gt/intel_context.h | 13 ++ drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/gt/intel_ring.c | 10 +- drivers/gpu/drm/i915/gt/intel_ring.h | 3 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 15 +- drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +- drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +- drivers/gpu/drm/i915/gt/mock_engine.c | 3 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 13 +- drivers/gpu/drm/i915/i915_gem.c | 11 +- drivers/gpu/drm/i915/i915_vma.c | 13 +- drivers/gpu/drm/i915/i915_vma.h | 13 +- 25 files changed, 215 insertions(+), 135 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index afa4328c3f54..1aead8e0d3de 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3449,7 +3449,7 @@ initial_plane_vma(struct drm_i915_private *i915, if (IS_ERR(vma)) goto err_obj; - if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) + if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) goto err_obj; if (i915_gem_object_is_tiled(obj) && diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 9aa9b70a8ecb..2048b21ac8b2 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1142,7 +1142,7 @@ static int context_barrier_task(struct i915_gem_context *ctx, i915_gem_ww_ctx_init(&ww, true); retry: - err = intel_context_pin(ce); + err = intel_context_pin_ww(ce, &ww); if (err) goto err; @@ -1235,7 +1235,7 @@ static int pin_ppgtt_update(struct intel_context *ce, struct i915_gem_ww_ctx *ww if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915)) /* ppGTT is not part of the legacy context image */ - return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm)); + return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm), ww); return 0; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 0b012abbdad5..ff9f20e3f4d4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -426,16 +426,17 @@ eb_pin_vma(struct i915_execbuffer *eb, pin_flags |= PIN_GLOBAL; /* Attempt to reuse the current location if available */ - if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) { + /* TODO: Add -EDEADLK handling here */ + if (unlikely(i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags))) { if (entry->flags & EXEC_OBJECT_PINNED) return false; /* Failing that pick any _free_ space if suitable */ - if (unlikely(i915_vma_pin(vma, - entry->pad_to_size, - entry->alignment, - eb_pin_flags(entry, ev->flags) | - PIN_USER | PIN_NOEVICT))) + if (unlikely(i915_vma_pin_ww(vma, &eb->ww, + entry->pad_to_size, + entry->alignment, + eb_pin_flags(entry, ev->flags) | + PIN_USER | PIN_NOEVICT))) return false; } @@ -576,7 +577,7 @@ static inline int use_cpu_reloc(const struct reloc_cache *cache, obj->cache_level != I915_CACHE_NONE); } -static int eb_reserve_vma(const struct i915_execbuffer *eb, +static int eb_reserve_vma(struct i915_execbuffer *eb, struct eb_vma *ev, u64 pin_flags) { @@ -591,7 +592,7 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, return err; } - err = i915_vma_pin(vma, + err = i915_vma_pin_ww(vma, &eb->ww, entry->pad_to_size, entry->alignment, eb_pin_flags(entry, ev->flags) | pin_flags); if (err) @@ -1052,7 +1053,7 @@ static int reloc_gpu_chain(struct i915_execbuffer *eb, struct reloc_cache *cache goto out_pool; } - err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK); + err = i915_vma_pin_ww(batch, &eb->ww, 0, 0, PIN_USER | PIN_NONBLOCK); if (err) goto out_pool; @@ -1222,9 +1223,10 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj, } static void *reloc_iomap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, + struct i915_execbuffer *eb, unsigned long page) { + struct reloc_cache *cache = &eb->reloc_cache; struct i915_ggtt *ggtt = cache_to_ggtt(cache); unsigned long offset; void *vaddr; @@ -1246,10 +1248,13 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, if (err) return ERR_PTR(err); - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, - PIN_MAPPABLE | - PIN_NONBLOCK /* NOWARN */ | - PIN_NOEVICT); + vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0, + PIN_MAPPABLE | + PIN_NONBLOCK /* NOWARN */ | + PIN_NOEVICT); + if (vma == ERR_PTR(-EDEADLK)) + return vma; + if (IS_ERR(vma)) { memset(&cache->node, 0, sizeof(cache->node)); mutex_lock(&ggtt->vm.mutex); @@ -1285,9 +1290,10 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, } static void *reloc_vaddr(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, + struct i915_execbuffer *eb, unsigned long page) { + struct reloc_cache *cache = &eb->reloc_cache; void *vaddr; if (cache->page == page) { @@ -1295,7 +1301,7 @@ static void *reloc_vaddr(struct drm_i915_gem_object *obj, } else { vaddr = NULL; if ((cache->vaddr & KMAP) == 0) - vaddr = reloc_iomap(obj, cache, page); + vaddr = reloc_iomap(obj, eb, page); if (!vaddr) vaddr = reloc_kmap(obj, cache, page); } @@ -1381,7 +1387,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, goto err_unmap; } - err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK); + err = i915_vma_pin_ww(batch, &eb->ww, 0, 0, PIN_USER | PIN_NONBLOCK); if (err) goto err_unmap; @@ -1627,8 +1633,7 @@ relocate_entry(struct i915_vma *vma, void *vaddr; repeat: - vaddr = reloc_vaddr(vma->obj, - &eb->reloc_cache, + vaddr = reloc_vaddr(vma->obj, eb, offset >> PAGE_SHIFT); if (IS_ERR(vaddr)) return PTR_ERR(vaddr); @@ -2044,6 +2049,7 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb, rq = eb_pin_engine(eb, false); if (IS_ERR(rq)) { err = PTR_ERR(rq); + rq = NULL; goto err; } @@ -2334,7 +2340,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) } static struct i915_vma * -shadow_batch_pin(struct drm_i915_gem_object *obj, +shadow_batch_pin(struct i915_execbuffer *eb, + struct drm_i915_gem_object *obj, struct i915_address_space *vm, unsigned int flags) { @@ -2345,7 +2352,7 @@ shadow_batch_pin(struct drm_i915_gem_object *obj, if (IS_ERR(vma)) return vma; - err = i915_vma_pin(vma, 0, 0, flags); + err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags); if (err) return ERR_PTR(err); @@ -2457,16 +2464,33 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, return err; } +static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma) +{ + /* + * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure + * batch" bit. Hence we need to pin secure batches into the global gtt. + * hsw should have this fixed, but bdw mucks it up again. */ + if (eb->batch_flags & I915_DISPATCH_SECURE) + return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, 0); + + return NULL; +} + static int eb_parse(struct i915_execbuffer *eb) { struct drm_i915_private *i915 = eb->i915; struct intel_gt_buffer_pool_node *pool = eb->batch_pool; - struct i915_vma *shadow, *trampoline; + struct i915_vma *shadow, *trampoline, *batch; unsigned int len; int err; - if (!eb_use_cmdparser(eb)) - return 0; + if (!eb_use_cmdparser(eb)) { + batch = eb_dispatch_secure(eb, eb->batch->vma); + if (IS_ERR(batch)) + return PTR_ERR(batch); + + goto secure_batch; + } len = eb->batch_len; if (!CMDPARSER_USES_GGTT(eb->i915)) { @@ -2494,7 +2518,7 @@ static int eb_parse(struct i915_execbuffer *eb) if (err) goto err; - shadow = shadow_batch_pin(pool->obj, eb->context->vm, PIN_USER); + shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER); if (IS_ERR(shadow)) { err = PTR_ERR(shadow); goto err; @@ -2505,7 +2529,7 @@ static int eb_parse(struct i915_execbuffer *eb) if (CMDPARSER_USES_GGTT(eb->i915)) { trampoline = shadow; - shadow = shadow_batch_pin(pool->obj, + shadow = shadow_batch_pin(eb, pool->obj, &eb->engine->gt->ggtt->vm, PIN_GLOBAL); if (IS_ERR(shadow)) { @@ -2517,19 +2541,34 @@ static int eb_parse(struct i915_execbuffer *eb) eb->batch_flags |= I915_DISPATCH_SECURE; } + batch = eb_dispatch_secure(eb, shadow); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto err_trampoline; + } + err = eb_parse_pipeline(eb, shadow, trampoline); if (err) - goto err_trampoline; + goto err_unpin_batch; - eb->vma[eb->buffer_count].vma = i915_vma_get(shadow); - eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN; eb->batch = &eb->vma[eb->buffer_count++]; + eb->batch->vma = i915_vma_get(shadow); + eb->batch->flags = __EXEC_OBJECT_HAS_PIN; eb->trampoline = trampoline; eb->batch_start_offset = 0; +secure_batch: + if (batch) { + eb->batch = &eb->vma[eb->buffer_count++]; + eb->batch->flags = __EXEC_OBJECT_HAS_PIN; + eb->batch->vma = i915_vma_get(batch); + } return 0; +err_unpin_batch: + if (batch) + i915_vma_unpin(batch); err_trampoline: if (trampoline) i915_vma_unpin(trampoline); @@ -2684,7 +2723,7 @@ static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, bool throt * GGTT space, so do this first before we reserve a seqno for * ourselves. */ - err = intel_context_pin(ce); + err = intel_context_pin_ww(ce, &eb->ww); if (err) return ERR_PTR(err); @@ -3107,33 +3146,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, ww_acquire_done(&eb.ww.ctx); - /* - * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure - * batch" bit. Hence we need to pin secure batches into the global gtt. - * hsw should have this fixed, but bdw mucks it up again. */ - if (eb.batch_flags & I915_DISPATCH_SECURE) { - struct i915_vma *vma; - - /* - * So on first glance it looks freaky that we pin the batch here - * outside of the reservation loop. But: - * - The batch is already pinned into the relevant ppgtt, so we - * already have the backing storage fully allocated. - * - No other BO uses the global gtt (well contexts, but meh), - * so we don't really have issues with multiple objects not - * fitting due to fragmentation. - * So this is actually safe. - */ - vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); - if (IS_ERR(vma)) { - err = PTR_ERR(vma); - goto err_vma; - } - - batch = vma; - } else { - batch = eb.batch->vma; - } + batch = eb.batch->vma; /* All GPU relocation batches must be submitted prior to the user rq */ GEM_BUG_ON(eb.reloc_cache.rq); @@ -3142,7 +3155,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.request = i915_request_create(eb.context); if (IS_ERR(eb.request)) { err = PTR_ERR(eb.request); - goto err_batch_unpin; + goto err_vma; } if (in_fence) { @@ -3204,9 +3217,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, } i915_request_put(eb.request); -err_batch_unpin: - if (eb.batch_flags & I915_DISPATCH_SECURE) - i915_vma_unpin(batch); err_vma: eb_release_vmas(&eb, true); if (eb.trampoline) @@ -3290,7 +3300,9 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, /* Copy in the exec list from userland */ exec_list = kvmalloc_array(count, sizeof(*exec_list), __GFP_NOWARN | GFP_KERNEL); - exec2_list = kvmalloc_array(count + 1, eb_element_size(), + + /* Allocate extra slots for use by the command parser */ + exec2_list = kvmalloc_array(count + 2, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec_list == NULL || exec2_list == NULL) { drm_dbg(&i915->drm, @@ -3368,8 +3380,8 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, if (err) return err; - /* Allocate an extra slot for use by the command parser */ - exec2_list = kvmalloc_array(count + 1, eb_element_size(), + /* Allocate extra slots for use by the command parser */ + exec2_list = kvmalloc_array(count + 2, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec2_list == NULL) { drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index f4fec7eb4064..8248efa9229f 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -376,7 +376,7 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt *ppgtt, int size) return vma; } -int gen6_ppgtt_pin(struct i915_ppgtt *base) +int gen6_ppgtt_pin(struct i915_ppgtt *base, struct i915_gem_ww_ctx *ww) { struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base); int err; @@ -402,7 +402,7 @@ int gen6_ppgtt_pin(struct i915_ppgtt *base) */ err = 0; if (!atomic_read(&ppgtt->pin_count)) - err = i915_ggtt_pin(ppgtt->vma, GEN6_PD_ALIGN, PIN_HIGH); + err = i915_ggtt_pin(ppgtt->vma, ww, GEN6_PD_ALIGN, PIN_HIGH); if (!err) atomic_inc(&ppgtt->pin_count); mutex_unlock(&ppgtt->pin_mutex); diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h index 72e481806c96..00032a931bae 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h @@ -8,6 +8,8 @@ #include "intel_gtt.h" +struct i915_gem_ww_ctx; + struct gen6_ppgtt { struct i915_ppgtt base; @@ -66,7 +68,7 @@ static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base) (pt = i915_pt_entry(pd, iter), true); \ ++iter) -int gen6_ppgtt_pin(struct i915_ppgtt *base); +int gen6_ppgtt_pin(struct i915_ppgtt *base, struct i915_gem_ww_ctx *ww); void gen6_ppgtt_unpin(struct i915_ppgtt *base); void gen6_ppgtt_unpin_all(struct i915_ppgtt *base); void gen6_ppgtt_enable(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index c039e87a46c4..64948386630f 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -93,12 +93,12 @@ static void intel_context_active_release(struct intel_context *ce) i915_active_release(&ce->active); } -static int __context_pin_state(struct i915_vma *vma) +static int __context_pin_state(struct i915_vma *vma, struct i915_gem_ww_ctx *ww) { unsigned int bias = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS; int err; - err = i915_ggtt_pin(vma, 0, bias | PIN_HIGH); + err = i915_ggtt_pin(vma, ww, 0, bias | PIN_HIGH); if (err) return err; @@ -127,7 +127,8 @@ static void __context_unpin_state(struct i915_vma *vma) __i915_vma_unpin(vma); } -static int __ring_active(struct intel_ring *ring) +static int __ring_active(struct intel_ring *ring, + struct i915_gem_ww_ctx *ww) { int err; @@ -135,7 +136,7 @@ static int __ring_active(struct intel_ring *ring) if (err) return err; - err = intel_ring_pin(ring); + err = intel_ring_pin(ring, ww); if (err) goto err_active; @@ -152,24 +153,25 @@ static void __ring_retire(struct intel_ring *ring) i915_active_release(&ring->vma->active); } -static int intel_context_pre_pin(struct intel_context *ce) +static int intel_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww) { int err; CE_TRACE(ce, "active\n"); - err = __ring_active(ce->ring); + err = __ring_active(ce->ring, ww); if (err) return err; - err = intel_timeline_pin(ce->timeline); + err = intel_timeline_pin(ce->timeline, ww); if (err) goto err_ring; if (!ce->state) return 0; - err = __context_pin_state(ce->state); + err = __context_pin_state(ce->state, ww); if (err) goto err_timeline; @@ -192,7 +194,8 @@ static void intel_context_post_unpin(struct intel_context *ce) __ring_retire(ce->ring); } -int __intel_context_do_pin(struct intel_context *ce) +int __intel_context_do_pin_ww(struct intel_context *ce, + struct i915_gem_ww_ctx *ww) { bool handoff = false; void *vaddr; @@ -209,7 +212,14 @@ int __intel_context_do_pin(struct intel_context *ce) * refcount for __intel_context_active(), which prevent a lock * inversion of ce->pin_mutex vs dma_resv_lock(). */ - err = intel_context_pre_pin(ce); + + err = i915_gem_object_lock(ce->timeline->hwsp_ggtt->obj, ww); + if (!err && ce->ring->vma->obj) + err = i915_gem_object_lock(ce->ring->vma->obj, ww); + if (!err && ce->state) + err = i915_gem_object_lock(ce->state->obj, ww); + if (!err) + err = intel_context_pre_pin(ce, ww); if (err) return err; @@ -217,7 +227,7 @@ int __intel_context_do_pin(struct intel_context *ce) if (err) goto err_ctx_unpin; - err = ce->ops->pre_pin(ce, &vaddr); + err = ce->ops->pre_pin(ce, ww, &vaddr); if (err) goto err_release; @@ -264,6 +274,23 @@ int __intel_context_do_pin(struct intel_context *ce) return err; } +int __intel_context_do_pin(struct intel_context *ce) +{ + struct i915_gem_ww_ctx ww; + int err; + + i915_gem_ww_ctx_init(&ww, true); +retry: + err = __intel_context_do_pin_ww(ce, &ww); + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + return err; +} + void intel_context_unpin(struct intel_context *ce) { if (!atomic_dec_and_test(&ce->pin_count)) @@ -301,18 +328,14 @@ static void __intel_context_retire(struct i915_active *active) static int __intel_context_active(struct i915_active *active) { struct intel_context *ce = container_of(active, typeof(*ce), active); - int err; intel_context_get(ce); /* everything should already be activated by intel_context_pre_pin() */ - err = __ring_active(ce->ring); - if (GEM_WARN_ON(err)) - goto err_put; + GEM_WARN_ON(!i915_active_acquire_if_busy(&ce->ring->vma->active)); + __intel_ring_pin(ce->ring); - err = intel_timeline_pin(ce->timeline); - if (GEM_WARN_ON(err)) - goto err_ring; + __intel_timeline_pin(ce->timeline); if (ce->state) { GEM_WARN_ON(!i915_active_acquire_if_busy(&ce->state->active)); @@ -321,12 +344,6 @@ static int __intel_context_active(struct i915_active *active) } return 0; - -err_ring: - __ring_retire(ce->ring); -err_put: - intel_context_put(ce); - return err; } void diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h index 07be021882cc..fda2eba81e22 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.h +++ b/drivers/gpu/drm/i915/gt/intel_context.h @@ -25,6 +25,8 @@ ##__VA_ARGS__); \ } while (0) +struct i915_gem_ww_ctx; + void intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine); void intel_context_fini(struct intel_context *ce); @@ -81,6 +83,8 @@ static inline void intel_context_unlock_pinned(struct intel_context *ce) } int __intel_context_do_pin(struct intel_context *ce); +int __intel_context_do_pin_ww(struct intel_context *ce, + struct i915_gem_ww_ctx *ww); static inline bool intel_context_pin_if_active(struct intel_context *ce) { @@ -95,6 +99,15 @@ static inline int intel_context_pin(struct intel_context *ce) return __intel_context_do_pin(ce); } +static inline int intel_context_pin_ww(struct intel_context *ce, + struct i915_gem_ww_ctx *ww) +{ + if (likely(intel_context_pin_if_active(ce))) + return 0; + + return __intel_context_do_pin_ww(ce, ww); +} + static inline void __intel_context_pin(struct intel_context *ce) { GEM_BUG_ON(!intel_context_is_pinned(ce)); diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index ca8e05b4d3ef..552cb57a2e8c 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -23,6 +23,7 @@ DECLARE_EWMA(runtime, 3, 8); struct i915_gem_context; +struct i915_gem_ww_ctx; struct i915_vma; struct intel_context; struct intel_ring; @@ -30,7 +31,7 @@ struct intel_ring; struct intel_context_ops { int (*alloc)(struct intel_context *ce); - int (*pre_pin)(struct intel_context *ce, void **vaddr); + int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr); int (*pin)(struct intel_context *ce, void *vaddr); void (*unpin)(struct intel_context *ce); void (*post_unpin)(struct intel_context *ce); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c8c14981eb5d..d967debba28d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -559,7 +559,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, else flags = PIN_HIGH; - return i915_ggtt_pin(vma, 0, flags); + return i915_ggtt_pin(vma, NULL, 0, flags); } static int init_status_page(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 24a0e47a2477..1942f53a60c2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -348,7 +348,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) goto err_unref; } - ret = i915_ggtt_pin(vma, 0, PIN_HIGH); + ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); if (ret) goto err_unref; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 3d6a82b6648e..4948368062b2 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3434,7 +3434,8 @@ __execlists_update_reg_state(const struct intel_context *ce, } static int -execlists_context_pre_pin(struct intel_context *ce, void **vaddr) +execlists_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, void **vaddr) { GEM_BUG_ON(!ce->state); GEM_BUG_ON(!i915_vma_is_pinned(ce->state)); @@ -3853,7 +3854,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) goto err; } - err = i915_ggtt_pin(vma, 0, PIN_HIGH); + err = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); if (err) goto err; diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index a289f22ced3b..86a5a8ba4f80 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -195,7 +195,7 @@ int intel_renderstate_init(struct intel_renderstate *so, i915_gem_ww_ctx_init(&so->ww, true); retry: - err = intel_context_pin(ce); + err = intel_context_pin_ww(ce, &so->ww); if (err) goto err_fini; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 8cda1b7e17ba..71b404973ce1 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -21,7 +21,13 @@ unsigned int intel_ring_update_space(struct intel_ring *ring) return space; } -int intel_ring_pin(struct intel_ring *ring) +void __intel_ring_pin(struct intel_ring *ring) +{ + GEM_BUG_ON(!atomic_read(&ring->pin_count)); + atomic_inc(&ring->pin_count); +} + +int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww) { struct i915_vma *vma = ring->vma; unsigned int flags; @@ -39,7 +45,7 @@ int intel_ring_pin(struct intel_ring *ring) else flags |= PIN_HIGH; - ret = i915_ggtt_pin(vma, 0, flags); + ret = i915_ggtt_pin(vma, ww, 0, flags); if (unlikely(ret)) goto err_unpin; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h index cc0ebca65167..1700579bdc93 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.h +++ b/drivers/gpu/drm/i915/gt/intel_ring.h @@ -21,7 +21,8 @@ int intel_ring_cacheline_align(struct i915_request *rq); unsigned int intel_ring_update_space(struct intel_ring *ring); -int intel_ring_pin(struct intel_ring *ring); +void __intel_ring_pin(struct intel_ring *ring); +int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww); void intel_ring_unpin(struct intel_ring *ring); void intel_ring_reset(struct intel_ring *ring, u32 tail); diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index f9ef34a489ec..d714737f3f7f 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -474,14 +474,16 @@ static void ring_context_destroy(struct kref *ref) intel_context_free(ce); } -static int __context_pin_ppgtt(struct intel_context *ce) +static int ring_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, + void **unused) { struct i915_address_space *vm; int err = 0; vm = vm_alias(ce->vm); if (vm) - err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); + err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww); return err; } @@ -588,11 +590,6 @@ static int ring_context_alloc(struct intel_context *ce) return 0; } -static int ring_context_pre_pin(struct intel_context *ce, void **unused) -{ - return __context_pin_ppgtt(ce); -} - static int ring_context_pin(struct intel_context *ce, void *unused) { return 0; @@ -1268,7 +1265,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine) } GEM_BUG_ON(timeline->has_initial_breadcrumb); - err = intel_timeline_pin(timeline); + err = intel_timeline_pin(timeline, NULL); if (err) goto err_timeline; @@ -1278,7 +1275,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine) goto err_timeline_unpin; } - err = intel_ring_pin(ring); + err = intel_ring_pin(ring, NULL); if (err) goto err_ring; diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c index 4546284fede1..e53f958bb819 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.c +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c @@ -313,14 +313,20 @@ intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp) return timeline; } -int intel_timeline_pin(struct intel_timeline *tl) +void __intel_timeline_pin(struct intel_timeline *tl) +{ + GEM_BUG_ON(!atomic_read(&tl->pin_count)); + atomic_inc(&tl->pin_count); +} + +int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww) { int err; if (atomic_add_unless(&tl->pin_count, 1, 0)) return 0; - err = i915_ggtt_pin(tl->hwsp_ggtt, 0, PIN_HIGH); + err = i915_ggtt_pin(tl->hwsp_ggtt, ww, 0, PIN_HIGH); if (err) return err; @@ -460,7 +466,7 @@ __intel_timeline_get_seqno(struct intel_timeline *tl, goto err_rollback; } - err = i915_ggtt_pin(vma, 0, PIN_HIGH); + err = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); if (err) { __idle_hwsp_free(vma->private, cacheline); goto err_rollback; diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h index 4298b9ac7327..ff293dfdbc3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.h +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h @@ -71,7 +71,8 @@ static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl, return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno); } -int intel_timeline_pin(struct intel_timeline *tl); +void __intel_timeline_pin(struct intel_timeline *tl); +int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww); void intel_timeline_enter(struct intel_timeline *tl); int intel_timeline_get_seqno(struct intel_timeline *tl, struct i915_request *rq, diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index 62664601e683..f349cb9115ce 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -168,7 +168,8 @@ static int mock_context_alloc(struct intel_context *ce) return 0; } -static int mock_context_pre_pin(struct intel_context *ce, void **unused) +static int mock_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, void **unused) { return 0; } diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 3e35a45d6218..46379df7b52d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2989,7 +2989,7 @@ static struct i915_vma *create_global(struct intel_gt *gt, size_t sz) return vma; } - err = i915_ggtt_pin(vma, 0, 0); + err = i915_ggtt_pin(vma, NULL, 0, 0); if (err) { i915_vma_put(vma); return ERR_PTR(err); diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index ef1c35073dc0..db49adcc6f78 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -454,7 +454,7 @@ tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value) struct i915_request *rq; int err; - err = intel_timeline_pin(tl); + err = intel_timeline_pin(tl, NULL); if (err) { rq = ERR_PTR(err); goto out; @@ -664,7 +664,7 @@ static int live_hwsp_wrap(void *arg) if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline) goto out_free; - err = intel_timeline_pin(tl); + err = intel_timeline_pin(tl, NULL); if (err) goto out_free; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 861657897c0f..942c7c187adb 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -677,7 +677,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) goto err; flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); - ret = i915_ggtt_pin(vma, 0, flags); + ret = i915_ggtt_pin(vma, NULL, 0, flags); if (ret) { vma = ERR_PTR(ret); goto err; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 98f2c448cd92..3dea3df34532 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1757,11 +1757,18 @@ static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) } struct i915_vma * __must_check +i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + const struct i915_ggtt_view *view, + u64 size, u64 alignment, u64 flags); + +static inline struct i915_vma * __must_check i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, - u64 size, - u64 alignment, - u64 flags); + u64 size, u64 alignment, u64 flags) +{ + return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags); +} int i915_gem_object_unbind(struct drm_i915_gem_object *obj, unsigned long flags); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 470a89761fd7..10a2af30ed74 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -950,11 +950,10 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915) } struct i915_vma * -i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, - const struct i915_ggtt_view *view, - u64 size, - u64 alignment, - u64 flags) +i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + const struct i915_ggtt_view *view, + u64 size, u64 alignment, u64 flags) { struct drm_i915_private *i915 = to_i915(obj->base.dev); struct i915_ggtt *ggtt = &i915->ggtt; @@ -1014,7 +1013,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return ERR_PTR(ret); } - ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); + ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 9b30ddc49e4b..1e81b368c792 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -856,13 +856,19 @@ static void vma_unbind_pages(struct i915_vma *vma) __vma_put_pages(vma, count | count << I915_VMA_PAGES_BIAS); } -int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) +int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u64 size, u64 alignment, u64 flags) { struct i915_vma_work *work = NULL; intel_wakeref_t wakeref = 0; unsigned int bound; int err; +#ifdef CONFIG_PROVE_LOCKING + if (debug_locks && lockdep_is_held(&vma->vm->i915->drm.struct_mutex)) + WARN_ON(!ww); +#endif + BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND); @@ -992,7 +998,8 @@ static void flush_idle_contexts(struct intel_gt *gt) intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); } -int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags) +int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u32 align, unsigned int flags) { struct i915_address_space *vm = vma->vm; int err; @@ -1000,7 +1007,7 @@ int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags) GEM_BUG_ON(!i915_vma_is_ggtt(vma)); do { - err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL); + err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL); if (err != -ENOSPC) { if (!err) { err = i915_vma_wait_for_bind(vma); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index d0d01f909548..5b3a3c653454 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -237,8 +237,17 @@ static inline void i915_vma_unlock(struct i915_vma *vma) } int __must_check -i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags); -int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags); +i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u64 size, u64 alignment, u64 flags); + +static inline int __must_check +i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) +{ + return i915_vma_pin_ww(vma, NULL, size, alignment, flags); +} + +int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u32 align, unsigned int flags); static inline int i915_vma_pin_count(const struct i915_vma *vma) { -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:04 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:04 +0200 Subject: [Intel-gfx] [PATCH 15/24] drm/i915: Kill last user of intel_context_create_request outside of selftests In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-15-maarten.lankhorst@linux.intel.com> Instead of using intel_context_create_request(), use intel_context_pin() and i915_create_request directly. Now all those calls are gone outside of selftests. :) Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++++++++++++++------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 94d66a9d760d..4ad167d18329 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1769,6 +1769,7 @@ static int engine_wa_list_verify(struct intel_context *ce, const struct i915_wa *wa; struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; unsigned int i; u32 *results; int err; @@ -1781,29 +1782,34 @@ static int engine_wa_list_verify(struct intel_context *ce, return PTR_ERR(vma); intel_engine_pm_get(ce->engine); - rq = intel_context_create_request(ce); - intel_engine_pm_put(ce->engine); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(vma->obj, &ww); + if (err == 0) + err = intel_context_pin_ww(ce, &ww); + if (err) + goto err_pm; + + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); - goto err_vma; + goto err_unpin; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); - if (err) { - i915_request_add(rq); - goto err_vma; - } - - err = wa_list_srm(rq, wal, vma); - if (err) - goto err_vma; + if (err == 0) + err = wa_list_srm(rq, wal, vma); i915_request_get(rq); + if (err) + i915_request_set_error_once(rq, err); i915_request_add(rq); + + if (err) + goto err_rq; + if (i915_request_wait(rq, 0, HZ / 5) < 0) { err = -ETIME; goto err_rq; @@ -1828,7 +1834,16 @@ static int engine_wa_list_verify(struct intel_context *ce, err_rq: i915_request_put(rq); -err_vma: +err_unpin: + intel_context_unpin(ce); +err_pm: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + intel_engine_pm_put(ce->engine); i915_vma_unpin(vma); i915_vma_put(vma); return err; -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:06 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:06 +0200 Subject: [Intel-gfx] [PATCH 17/24] drm/i915: Dirty hack to fix selftests locking inversion In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-17-maarten.lankhorst@linux.intel.com> Some i915 selftests still use i915_vma_lock() as inner lock, and intel_context_create_request() intel_timeline->mutex as outer lock. Fortunately for selftests this is not an issue, they should be fixed but we can move ahead and cleanify lockdep now. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 64948386630f..fe9fff5a63b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -459,6 +459,18 @@ struct i915_request *intel_context_create_request(struct intel_context *ce) rq = i915_request_create(ce); intel_context_unpin(ce); + if (IS_ERR(rq)) + return rq; + + /* + * timeline->mutex should be the inner lock, but is used as outer lock. + * Hack around this to shut up lockdep in selftests.. + */ + lockdep_unpin_lock(&ce->timeline->mutex, rq->cookie); + mutex_release(&ce->timeline->mutex.dep_map, _RET_IP_); + mutex_acquire(&ce->timeline->mutex.dep_map, SINGLE_DEPTH_NESTING, 0, _RET_IP_); + rq->cookie = lockdep_pin_lock(&ce->timeline->mutex); + return rq; } -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:07 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:07 +0200 Subject: [Intel-gfx] [PATCH 18/24] drm/i915/selftests: Fix locking inversion in lrc selftest. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-18-maarten.lankhorst@linux.intel.com> This function does not use intel_context_create_request, so it has to use the same locking order as normal code. This is required to shut up lockdep in selftests. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 46379df7b52d..c56a7e7a5abd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -4910,6 +4910,7 @@ static int __live_lrc_state(struct intel_engine_cs *engine, { struct intel_context *ce; struct i915_request *rq; + struct i915_gem_ww_ctx ww; enum { RING_START_IDX = 0, RING_TAIL_IDX, @@ -4924,7 +4925,11 @@ static int __live_lrc_state(struct intel_engine_cs *engine, if (IS_ERR(ce)) return PTR_ERR(ce); - err = intel_context_pin(ce); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(scratch->obj, &ww); + if (!err) + err = intel_context_pin_ww(ce, &ww); if (err) goto err_put; @@ -4953,11 +4958,9 @@ static int __live_lrc_state(struct intel_engine_cs *engine, *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); *cs++ = 0; - i915_vma_lock(scratch); err = i915_request_await_object(rq, scratch->obj, true); if (!err) err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(scratch); i915_request_get(rq); i915_request_add(rq); @@ -4994,6 +4997,12 @@ static int __live_lrc_state(struct intel_engine_cs *engine, err_unpin: intel_context_unpin(ce); err_put: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); intel_context_put(ce); return err; } -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:10 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:10 +0200 Subject: [Intel-gfx] [PATCH 21/24] drm/i915: Add ww locking to vm_fault_gtt In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-21-maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 51 +++++++++++++++--------- 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index 9d306dc9849d..a8f1d438affd 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -283,37 +283,46 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) struct intel_runtime_pm *rpm = &i915->runtime_pm; struct i915_ggtt *ggtt = &i915->ggtt; bool write = area->vm_flags & VM_WRITE; + struct i915_gem_ww_ctx ww; intel_wakeref_t wakeref; struct i915_vma *vma; pgoff_t page_offset; int srcu; int ret; - /* Sanity check that we allow writing into this object */ - if (i915_gem_object_is_readonly(obj) && write) - return VM_FAULT_SIGBUS; - /* We don't use vmf->pgoff since that has the fake offset */ page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; trace_i915_gem_object_fault(obj, page_offset, true, write); - ret = i915_gem_object_pin_pages(obj); + wakeref = intel_runtime_pm_get(rpm); + + i915_gem_ww_ctx_init(&ww, true); +retry: + ret = i915_gem_object_lock(obj, &ww); if (ret) - goto err; + goto err_rpm; - wakeref = intel_runtime_pm_get(rpm); + /* Sanity check that we allow writing into this object */ + if (i915_gem_object_is_readonly(obj) && write) { + ret = -EFAULT; + goto err_rpm; + } - ret = intel_gt_reset_trylock(ggtt->vm.gt, &srcu); + ret = i915_gem_object_pin_pages(obj); if (ret) goto err_rpm; + ret = intel_gt_reset_trylock(ggtt->vm.gt, &srcu); + if (ret) + goto err_pages; + /* Now pin it into the GTT as needed */ - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, - PIN_MAPPABLE | - PIN_NONBLOCK /* NOWARN */ | - PIN_NOEVICT); - if (IS_ERR(vma)) { + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0, + PIN_MAPPABLE | + PIN_NONBLOCK /* NOWARN */ | + PIN_NOEVICT); + if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) { /* Use a partial view if it is bigger than available space */ struct i915_ggtt_view view = compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); @@ -328,11 +337,11 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) * all hope that the hardware is able to track future writes. */ - vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags); - if (IS_ERR(vma)) { + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags); + if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) { flags = PIN_MAPPABLE; view.type = I915_GGTT_VIEW_PARTIAL; - vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags); + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags); } /* The entire mappable GGTT is pinned? Unexpected! */ @@ -389,10 +398,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) __i915_vma_unpin(vma); err_reset: intel_gt_reset_unlock(ggtt->vm.gt, srcu); +err_pages: + i915_gem_object_unpin_pages(obj); err_rpm: + if (ret == -EDEADLK) { + ret = i915_gem_ww_ctx_backoff(&ww); + if (!ret) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); intel_runtime_pm_put(rpm, wakeref); - i915_gem_object_unpin_pages(obj); -err: return i915_error_to_vmf_fault(ret); } -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:09 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:09 +0200 Subject: [Intel-gfx] [PATCH 20/24] drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-20-maarten.lankhorst@linux.intel.com> Make sure vma_lock is not used as inner lock when kernel context is used, and add ww handling where appropriate. Ensure that execbuf selftests keep passing by using ww handling. Signed-off-by: Maarten Lankhorst --- .../i915/gem/selftests/i915_gem_coherency.c | 26 ++++++------ .../i915/gem/selftests/i915_gem_execbuffer.c | 26 +++++++++--- .../drm/i915/gem/selftests/i915_gem_mman.c | 41 ++++++++++++++----- drivers/gpu/drm/i915/gt/selftest_rps.c | 30 ++++++++------ drivers/gpu/drm/i915/selftests/i915_request.c | 18 +++++--- 5 files changed, 95 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index dcdfc396f2f8..7049a6bbc03d 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -201,25 +201,25 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); - i915_gem_object_unlock(ctx->obj); if (err) - return err; + goto out_unlock; vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0); - if (IS_ERR(vma)) - return PTR_ERR(vma); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto out_unlock; + } rq = intel_engine_create_kernel_request(ctx->engine); if (IS_ERR(rq)) { - i915_vma_unpin(vma); - return PTR_ERR(rq); + err = PTR_ERR(rq); + goto out_unpin; } cs = intel_ring_begin(rq, 4); if (IS_ERR(cs)) { - i915_request_add(rq); - i915_vma_unpin(vma); - return PTR_ERR(cs); + err = PTR_ERR(cs); + goto out_rq; } if (INTEL_GEN(ctx->engine->i915) >= 8) { @@ -240,14 +240,16 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) } intel_ring_advance(rq, cs); - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); - i915_vma_unpin(vma); +out_rq: i915_request_add(rq); +out_unpin: + i915_vma_unpin(vma); +out_unlock: + i915_gem_object_unlock(ctx->obj); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 5ecf0afc3e71..fcb1368c011a 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -124,6 +124,8 @@ static int igt_gpu_reloc(void *arg) goto err_scratch; } + intel_gt_pm_get(&eb.i915->gt); + for_each_uabi_engine(eb.engine, eb.i915) { reloc_cache_init(&eb.reloc_cache, eb.i915); memset(map, POISON_INUSE, 4096); @@ -134,15 +136,26 @@ static int igt_gpu_reloc(void *arg) err = PTR_ERR(eb.context); goto err_pm; } + eb.reloc_pool = NULL; - err = intel_context_pin(eb.context); - if (err) - goto err_put; + i915_gem_ww_ctx_init(&eb.ww, false); +retry: + err = intel_context_pin_ww(eb.context, &eb.ww); + if (!err) { + err = __igt_gpu_reloc(&eb, scratch); + + intel_context_unpin(eb.context); + } + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&eb.ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&eb.ww); - err = __igt_gpu_reloc(&eb, scratch); + if (eb.reloc_pool) + intel_gt_buffer_pool_put(eb.reloc_pool); - intel_context_unpin(eb.context); -err_put: intel_context_put(eb.context); err_pm: intel_engine_pm_put(eb.engine); @@ -153,6 +166,7 @@ static int igt_gpu_reloc(void *arg) if (igt_flush_test(eb.i915)) err = -EIO; + intel_gt_pm_put(&eb.i915->gt); err_scratch: i915_gem_object_put(scratch); return err; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 9fb95a45bcad..d27d87a678c8 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -528,31 +528,42 @@ static int make_obj_busy(struct drm_i915_gem_object *obj) for_each_uabi_engine(engine, i915) { struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; int err; vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); if (IS_ERR(vma)) return PTR_ERR(vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(obj, &ww); + if (!err) + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); if (err) - return err; + goto err; rq = intel_engine_create_kernel_request(engine); if (IS_ERR(rq)) { - i915_vma_unpin(vma); - return PTR_ERR(rq); + err = PTR_ERR(rq); + goto err_unpin; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); i915_request_add(rq); +err_unpin: i915_vma_unpin(vma); +err: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); if (err) return err; } @@ -1123,6 +1134,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, for_each_uabi_engine(engine, i915) { struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; vma = i915_vma_instance(obj, engine->kernel_context->vm, NULL); if (IS_ERR(vma)) { @@ -1130,9 +1142,13 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, goto out_unmap; } - err = i915_vma_pin(vma, 0, 0, PIN_USER); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(obj, &ww); + if (!err) + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); if (err) - goto out_unmap; + goto out_ww; rq = i915_request_create(engine->kernel_context); if (IS_ERR(rq)) { @@ -1140,11 +1156,9 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, goto out_unpin; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (err == 0) err = i915_vma_move_to_active(vma, rq, 0); - i915_vma_unlock(vma); err = engine->emit_bb_start(rq, vma->node.start, 0, 0); i915_request_get(rq); @@ -1166,6 +1180,13 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, out_unpin: i915_vma_unpin(vma); +out_ww: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); if (err) goto out_unmap; } diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..f2071019599f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -92,20 +92,20 @@ create_spin_counter(struct intel_engine_cs *engine, vma = i915_vma_instance(obj, vm, NULL); if (IS_ERR(vma)) { - i915_gem_object_put(obj); - return vma; + err = PTR_ERR(vma); + goto err_put; } err = i915_vma_pin(vma, 0, 0, PIN_USER); - if (err) { - i915_vma_put(vma); - return ERR_PTR(err); - } + if (err) + goto err_unlock; + + i915_vma_lock(vma); base = i915_gem_object_pin_map(obj, I915_MAP_WC); if (IS_ERR(base)) { - i915_gem_object_put(obj); - return ERR_CAST(base); + err = PTR_ERR(base); + goto err_unpin; } cs = base; @@ -149,6 +149,14 @@ create_spin_counter(struct intel_engine_cs *engine, *cancel = base + loop; *counter = srm ? memset32(base + end, 0, 1) : NULL; return vma; + +err_unpin: + i915_vma_unpin(vma); +err_unlock: + i915_vma_unlock(vma); +err_put: + i915_gem_object_put(obj); + return ERR_PTR(err); } static u8 wait_for_freq(struct intel_rps *rps, u8 freq, int timeout_ms) @@ -654,7 +662,6 @@ int live_rps_frequency_cs(void *arg) goto err_vma; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (!err) err = i915_vma_move_to_active(vma, rq, 0); @@ -662,7 +669,6 @@ int live_rps_frequency_cs(void *arg) err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, 0); - i915_vma_unlock(vma); i915_request_add(rq); if (err) goto err_vma; @@ -723,6 +729,7 @@ int live_rps_frequency_cs(void *arg) i915_gem_object_flush_map(vma->obj); i915_gem_object_unpin_map(vma->obj); i915_vma_unpin(vma); + i915_vma_unlock(vma); i915_vma_put(vma); engine_heartbeat_enable(engine); @@ -796,7 +803,6 @@ int live_rps_frequency_srm(void *arg) goto err_vma; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (!err) err = i915_vma_move_to_active(vma, rq, 0); @@ -804,7 +810,6 @@ int live_rps_frequency_srm(void *arg) err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, 0); - i915_vma_unlock(vma); i915_request_add(rq); if (err) goto err_vma; @@ -864,6 +869,7 @@ int live_rps_frequency_srm(void *arg) i915_gem_object_flush_map(vma->obj); i915_gem_object_unpin_map(vma->obj); i915_vma_unpin(vma); + i915_vma_unlock(vma); i915_vma_put(vma); engine_heartbeat_enable(engine); diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 92c628f18c60..8d3b854a83c6 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -861,6 +861,8 @@ static int live_all_engines(void *arg) goto out_free; } + i915_vma_lock(batch); + idx = 0; for_each_uabi_engine(engine, i915) { request[idx] = intel_engine_create_kernel_request(engine); @@ -871,11 +873,9 @@ static int live_all_engines(void *arg) goto out_request; } - i915_vma_lock(batch); err = i915_request_await_object(request[idx], batch->obj, 0); if (err == 0) err = i915_vma_move_to_active(batch, request[idx], 0); - i915_vma_unlock(batch); GEM_BUG_ON(err); err = engine->emit_bb_start(request[idx], @@ -890,6 +890,8 @@ static int live_all_engines(void *arg) idx++; } + i915_vma_unlock(batch); + idx = 0; for_each_uabi_engine(engine, i915) { if (i915_request_completed(request[idx])) { @@ -980,12 +982,13 @@ static int live_sequential_engines(void *arg) goto out_free; } + i915_vma_lock(batch); request[idx] = intel_engine_create_kernel_request(engine); if (IS_ERR(request[idx])) { err = PTR_ERR(request[idx]); pr_err("%s: Request allocation failed for %s with err=%d\n", __func__, engine->name, err); - goto out_request; + goto out_unlock; } if (prev) { @@ -995,16 +998,14 @@ static int live_sequential_engines(void *arg) i915_request_add(request[idx]); pr_err("%s: Request await failed for %s with err=%d\n", __func__, engine->name, err); - goto out_request; + goto out_unlock; } } - i915_vma_lock(batch); err = i915_request_await_object(request[idx], batch->obj, false); if (err == 0) err = i915_vma_move_to_active(batch, request[idx], 0); - i915_vma_unlock(batch); GEM_BUG_ON(err); err = engine->emit_bb_start(request[idx], @@ -1019,6 +1020,11 @@ static int live_sequential_engines(void *arg) prev = request[idx]; idx++; + +out_unlock: + i915_vma_unlock(batch); + if (err) + goto out_request; } idx = 0; -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:13 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:13 +0200 Subject: [Intel-gfx] [PATCH 24/24] drm/i915: Kill context before taking ctx->mutex In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-24-maarten.lankhorst@linux.intel.com> Killing context before taking ctx->mutex fixes a hang in gem_ctx_persistence.close-replace-race, where lut_close takes obj->resv.lock which is already held by execbuf, causing a stalling indefinitely. [ 1904.342847] 2 locks held by gem_ctx_persist/11520: [ 1904.342849] #0: ffff8882188e4968 (&ctx->mutex){+.+.}-{3:3}, at: context_close+0xe6/0x850 [i915] [ 1904.342941] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: lut_close+0x2c2/0xba0 [i915] [ 1904.343033] 3 locks held by gem_ctx_persist/11521: [ 1904.343035] #0: ffffc900008ff938 (reservation_ww_class_acquire){+.+.}-{0:0}, at: i915_gem_do_execbuffer+0x103d/0x54c0 [i915] [ 1904.343157] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: eb_validate_vmas+0x602/0x2010 [i915] [ 1904.343267] #2: ffff88820afd9200 (&vm->mutex/1){+.+.}-{3:3}, at: i915_vma_pin_ww+0x335/0x2300 [i915] Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 24 ++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 2048b21ac8b2..05df7ffff624 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -623,6 +623,18 @@ static void context_close(struct i915_gem_context *ctx) i915_gem_context_set_closed(ctx); mutex_unlock(&ctx->engines_mutex); + /* + * If the user has disabled hangchecking, we can not be sure that + * the batches will ever complete after the context is closed, + * keeping the context and all resources pinned forever. So in this + * case we opt to forcibly kill off all remaining requests on + * context close. + */ + if (!i915_gem_context_is_persistent(ctx) || + !i915_modparams.enable_hangcheck) + kill_context(ctx); + + mutex_lock(&ctx->mutex); set_closed_name(ctx); @@ -641,18 +653,6 @@ static void context_close(struct i915_gem_context *ctx) lut_close(ctx); mutex_unlock(&ctx->mutex); - - /* - * If the user has disabled hangchecking, we can not be sure that - * the batches will ever complete after the context is closed, - * keeping the context and all resources pinned forever. So in this - * case we opt to forcibly kill off all remaining requests on - * context close. - */ - if (!i915_gem_context_is_persistent(ctx) || - !i915_modparams.enable_hangcheck) - kill_context(ctx); - i915_gem_context_put(ctx); } -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:11 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:11 +0200 Subject: [Intel-gfx] [PATCH 22/24] drm/i915: Add ww locking to pin_to_display_plane In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-22-maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 65 ++++++++++++++++------ drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 + 2 files changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 8ebceebd11b0..c0d153284984 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -37,6 +37,12 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) i915_gem_object_unlock(obj); } +void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj) +{ + if (i915_gem_object_is_framebuffer(obj)) + __i915_gem_object_flush_for_display(obj); +} + /** * Moves a single object to the WC read, and possibly write domain. * @obj: object to act on @@ -197,18 +203,12 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (ret) return ret; - ret = i915_gem_object_lock_interruptible(obj, NULL); - if (ret) - return ret; - /* Always invalidate stale cachelines */ if (obj->cache_level != cache_level) { i915_gem_object_set_cache_coherency(obj, cache_level); obj->cache_dirty = true; } - i915_gem_object_unlock(obj); - /* The cache-level will be applied when each vma is rebound. */ return i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE | @@ -255,6 +255,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, struct drm_i915_gem_caching *args = data; struct drm_i915_gem_object *obj; enum i915_cache_level level; + struct i915_gem_ww_ctx ww; int ret = 0; switch (args->caching) { @@ -293,7 +294,18 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, goto out; } - ret = i915_gem_object_set_cache_level(obj, level); + i915_gem_ww_ctx_init(&ww, true); +retry: + ret = i915_gem_object_lock(obj, &ww); + if (!ret) + ret = i915_gem_object_set_cache_level(obj, level); + + if (ret == -EDEADLK) { + ret = i915_gem_ww_ctx_backoff(&ww); + if (!ret) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); out: i915_gem_object_put(obj); @@ -313,6 +325,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, unsigned int flags) { struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_gem_ww_ctx ww; struct i915_vma *vma; int ret; @@ -320,6 +333,11 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj)) return ERR_PTR(-EINVAL); + i915_gem_ww_ctx_init(&ww, true); +retry: + ret = i915_gem_object_lock(obj, &ww); + if (ret) + goto err; /* * The display engine is not coherent with the LLC cache on gen6. As * a result, we make sure that the pinning that is about to occur is @@ -334,7 +352,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE); if (ret) - return ERR_PTR(ret); + goto err; /* * As the user may map the buffer once pinned in the display plane @@ -347,18 +365,31 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, vma = ERR_PTR(-ENOSPC); if ((flags & PIN_MAPPABLE) == 0 && (!view || view->type == I915_GGTT_VIEW_NORMAL)) - vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, - flags | - PIN_MAPPABLE | - PIN_NONBLOCK); - if (IS_ERR(vma)) - vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); - if (IS_ERR(vma)) - return vma; + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0, alignment, + flags | PIN_MAPPABLE | + PIN_NONBLOCK); + if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0, + alignment, flags); + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); + goto err; + } vma->display_alignment = max_t(u64, vma->display_alignment, alignment); - i915_gem_object_flush_if_display(obj); + i915_gem_object_flush_if_display_locked(obj); + +err: + if (ret == -EDEADLK) { + ret = i915_gem_ww_ctx_backoff(&ww); + if (!ret) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + + if (ret) + return ERR_PTR(ret); return vma; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 11b8e2735071..409fd00c8709 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -456,6 +456,7 @@ i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, unsigned int cache_level); void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj); +void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj); int __must_check i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:56:55 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:56:55 +0200 Subject: [Intel-gfx] [PATCH 06/24] drm/i915/gem: Make eb_add_lut interruptible wait on object lock. In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-6-maarten.lankhorst@linux.intel.com> The lock here should be interruptible, so we can backoff if needed. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index e1d63588ed8f..4ef6e48da8f1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -776,7 +776,12 @@ static int __eb_add_lut(struct i915_execbuffer *eb, if (err == 0) { /* And nor has this handle */ struct drm_i915_gem_object *obj = vma->obj; - i915_gem_object_lock(obj, NULL); + err = i915_gem_object_lock_interruptible(obj, NULL); + if (err) { + radix_tree_delete(&ctx->handles_vma, handle); + goto unlock; + } + if (idr_find(&eb->file->object_idr, handle) == obj) { list_add(&lut->obj_link, &obj->lut_list); } else { @@ -785,6 +790,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, } i915_gem_object_unlock(obj); } +unlock: mutex_unlock(&ctx->mutex); } if (unlikely(err)) -- 2.26.2 From maarten.lankhorst at linux.intel.com Wed Jun 3 14:57:08 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 3 Jun 2020 16:57:08 +0200 Subject: [Intel-gfx] [PATCH 19/24] drm/i915: Use ww pinning for intel_context_create_request() In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200603145713.3835124-19-maarten.lankhorst@linux.intel.com> We want to get rid of intel_context_pin(), convert intel_context_create_request() first. :) Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index fe9fff5a63b1..e148e2d69ae1 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -449,15 +449,25 @@ int intel_context_prepare_remote_request(struct intel_context *ce, struct i915_request *intel_context_create_request(struct intel_context *ce) { + struct i915_gem_ww_ctx ww; struct i915_request *rq; int err; - err = intel_context_pin(ce); - if (unlikely(err)) - return ERR_PTR(err); + i915_gem_ww_ctx_init(&ww, true); +retry: + err = intel_context_pin_ww(ce, &ww); + if (!err) { + rq = i915_request_create(ce); + intel_context_unpin(ce); + } else if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } else { + rq = ERR_PTR(err); + } - rq = i915_request_create(ce); - intel_context_unpin(ce); + i915_gem_ww_ctx_fini(&ww); if (IS_ERR(rq)) return rq; -- 2.26.2 From patchwork at emeril.freedesktop.org Wed Jun 3 15:22:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 15:22:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/dp=3A_Include_the_AUX_CH_name_in_the_debug_messages_=28rev2=29?= In-Reply-To: <20200514184040.20700-1-ville.syrjala@linux.intel.com> References: <20200514184040.20700-1-ville.syrjala@linux.intel.com> Message-ID: <159119775519.12266.10502034296357750307@emeril.freedesktop.org> == Series Details == Series: drm/dp: Include the AUX CH name in the debug messages (rev2) URL : https://patchwork.freedesktop.org/series/77276/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17851 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/index.html Known issues ------------ Here are the changes found in Patchwork_17851 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-tgl-y: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][7] ([i915#1928]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/fi-kbl-x1275/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17851 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17851: b40213e78a826fd098477aa050e49072f8cc61a5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b40213e78a82 drm/dp: Include the AUX CH name in the debug messages == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/index.html From patchwork at emeril.freedesktop.org Wed Jun 3 15:27:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 15:27:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/params=3A_fix_i915=2Ereset_module_param_type_=28re?= =?utf-8?b?djIp?= In-Reply-To: <20200602151126.25626-1-jani.nikula@intel.com> References: <20200602151126.25626-1-jani.nikula@intel.com> Message-ID: <159119803123.12265.9461535744458867890@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: fix i915.reset module param type (rev2) URL : https://patchwork.freedesktop.org/series/77923/ State : warning == Summary == $ dim checkpatch origin/drm-tip 41ac3a8d0f09 drm/i915/params: fix i915.reset module param type -:25: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #25: FILE: drivers/gpu/drm/i915/i915_params.c:78: +i915_param_named_unsafe(reset, uint, 0400, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])"); total: 0 errors, 0 warnings, 1 checks, 8 lines checked From patchwork at emeril.freedesktop.org Wed Jun 3 15:48:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 15:48:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_fix_i915=2Ereset_module_param_type_=28rev2=29?= In-Reply-To: <20200602151126.25626-1-jani.nikula@intel.com> References: <20200602151126.25626-1-jani.nikula@intel.com> Message-ID: <159119931968.12267.14279074377996756475@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: fix i915.reset module param type (rev2) URL : https://patchwork.freedesktop.org/series/77923/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17852 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/index.html Known issues ------------ Here are the changes found in Patchwork_17852 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][5] -> [DMESG-WARN][6] ([i915#62] / [i915#92] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_chamelium@hdmi-crc-fast: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_chamelium@hdmi-crc-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-icl-u2/igt at kms_chamelium@hdmi-crc-fast.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][15] ([i915#1928]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17852 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17852: 41ac3a8d0f0941f9f86f34672ec72bfa3aaa7e8c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 41ac3a8d0f09 drm/i915/params: fix i915.reset module param type == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/index.html From patchwork at emeril.freedesktop.org Wed Jun 3 15:50:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 15:50:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBS?= =?utf-8?q?estore_=2208fff7aeddc9_=28=22drm/i915/tgl=3A_Wa=5F1607138340=22?= =?utf-8?q?=29?= In-Reply-To: <20200603145529.3851-1-chris@chris-wilson.co.uk> References: <20200603145529.3851-1-chris@chris-wilson.co.uk> Message-ID: <159119942138.12268.17308425473904002804@emeril.freedesktop.org> == Series Details == Series: Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") URL : https://patchwork.freedesktop.org/series/77959/ State : failure == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:136:0: drivers/gpu/drm/i915/gt/intel_lrc.c: In function ?execlists_update_context?: drivers/gpu/drm/i915/gt/intel_lrc.c:1524:21: error: ?struct i915_request? has no member named ?i915? if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_B0)) ^ ./drivers/gpu/drm/i915/i915_drv.h:1421:44: note: in definition of macro ?IS_TIGERLAKE? #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) ^~~~~~~~ drivers/gpu/drm/i915/gt/intel_lrc.c:1524:6: note: in expansion of macro ?IS_TGL_REVID? if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_B0)) ^~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_lrc.c:1524:21: error: ?struct i915_request? has no member named ?i915? if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_B0)) ^ ./drivers/gpu/drm/i915/i915_drv.h:1297:33: note: in definition of macro ?INTEL_REVID? #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) ^~~~~~~~ ./drivers/gpu/drm/i915/i915_drv.h:1542:22: note: in expansion of macro ?IS_REVID? (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) ^~~~~~~~ drivers/gpu/drm/i915/gt/intel_lrc.c:1524:6: note: in expansion of macro ?IS_TGL_REVID? if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_B0)) ^~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_lrc.c:1524:21: error: ?struct i915_request? has no member named ?i915? if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_B0)) ^ ./drivers/gpu/drm/i915/i915_drv.h:1297:33: note: in definition of macro ?INTEL_REVID? #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) ^~~~~~~~ ./drivers/gpu/drm/i915/i915_drv.h:1542:22: note: in expansion of macro ?IS_REVID? (IS_TIGERLAKE(p) && IS_REVID(p, since, until)) ^~~~~~~~ drivers/gpu/drm/i915/gt/intel_lrc.c:1524:6: note: in expansion of macro ?IS_TGL_REVID? if (IS_TGL_REVID(rq->i915, TGL_REVID_A0, TGL_REVID_B0)) ^~~~~~~~~~~~ scripts/Makefile.build:266: recipe for target 'drivers/gpu/drm/i915/gt/intel_lrc.o' failed make[4]: *** [drivers/gpu/drm/i915/gt/intel_lrc.o] Error 1 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1729: recipe for target 'drivers' failed make: *** [drivers] Error 2 From patchwork at emeril.freedesktop.org Wed Jun 3 15:57:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 15:57:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/24=5D_Revert_=22drm/i915/gem=3A_?= =?utf-8?q?Drop_relocation_slowpath=22=2E?= In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <159119983989.12268.1563755641554731988@emeril.freedesktop.org> == Series Details == Series: series starting with [01/24] Revert "drm/i915/gem: Drop relocation slowpath". URL : https://patchwork.freedesktop.org/series/77960/ State : warning == Summary == $ dim checkpatch origin/drm-tip a8a26d902de0 Revert "drm/i915/gem: Drop relocation slowpath". -:80: WARNING:LINE_SPACING: Missing a blank line after declarations #80: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1802: + int err = __get_user(c, addr); + if (err) total: 0 errors, 1 warnings, 0 checks, 264 lines checked 1534f179b1ab drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. -:493: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #493: FILE: drivers/gpu/drm/i915/i915_gem.c:1341: + while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { total: 0 errors, 1 warnings, 0 checks, 473 lines checked c412b07e522c drm/i915: Remove locking from i915_gem_object_prepare_read/write ef8df645976c drm/i915: Parse command buffer earlier in eb_relocate(slow) 550bd4348656 Revert "drm/i915/gem: Split eb_vma into its own allocation" 7d8b20457516 drm/i915/gem: Make eb_add_lut interruptible wait on object lock. 45f9dff46487 drm/i915: Use per object locking in execbuf, v11. -:473: CHECK:LINE_SPACING: Please don't use multiple blank lines #473: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1408: + -:520: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #520: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1520: +static int __reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, -:540: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #540: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1593: +static int reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, -:552: ERROR:TRAILING_WHITESPACE: trailing whitespace #552: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1618: +^I$ -:811: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #811: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2957: + eb.reloc_pool = eb.batch_pool = NULL; total: 1 errors, 0 warnings, 4 checks, 811 lines checked 2d2857b3d5ae drm/i915: Use ww locking in intel_renderstate. -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: Convert to using ww-waiting, and make sure we always pin intel_context_state, total: 0 errors, 1 warnings, 0 checks, 209 lines checked b25ba367c26d drm/i915: Add ww context handling to context_barrier_task -:19: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #19: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:1097: + int (*pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void *data), total: 0 errors, 1 warnings, 0 checks, 146 lines checked 36d3bd7c0420 drm/i915: Nuke arguments to eb_pin_engine 5e983148f18d drm/i915: Pin engine before pinning all objects, v4. 2da536f6aca7 drm/i915: Rework intel_context pinning to do everything outside of pin_mutex -:125: CHECK:LINE_SPACING: Please don't use multiple blank lines #125: FILE: drivers/gpu/drm/i915/gt/intel_context.c:176: + + -:338: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #338: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3443: + *vaddr = i915_gem_object_pin_map(ce->state->obj, + i915_coherent_map_type(ce->engine->i915) | total: 0 errors, 0 warnings, 2 checks, 435 lines checked fc5ed58aad70 drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. -:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #95: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:596: + err = i915_vma_pin_ww(vma, &eb->ww, entry->pad_to_size, entry->alignment, -:213: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #213: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2472: + * hsw should have this fixed, but bdw mucks it up again. */ total: 0 errors, 1 warnings, 1 checks, 850 lines checked 18ebd9d92415 drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. de5ef8ca658c drm/i915: Kill last user of intel_context_create_request outside of selftests 756385fc367b drm/i915: Convert i915_perf to ww locking as well 4b168d7eb625 drm/i915: Dirty hack to fix selftests locking inversion 51a11c92d700 drm/i915/selftests: Fix locking inversion in lrc selftest. 78eb94b06623 drm/i915: Use ww pinning for intel_context_create_request() 9bb49e2f74c1 drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2. -:108: ERROR:TRAILING_WHITESPACE: trailing whitespace #108: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c:154: +^I^Ii915_gem_ww_ctx_fini(&eb.ww); $ total: 1 errors, 0 warnings, 0 checks, 347 lines checked 2f3fd8b5e141 drm/i915: Add ww locking to vm_fault_gtt -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 91 lines checked f60b4639d689 drm/i915: Add ww locking to pin_to_display_plane -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 129 lines checked 1f073601ee7f drm/i915: Ensure we hold the pin mutex -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 39 lines checked de0fb243bf50 drm/i915: Kill context before taking ctx->mutex -:40: CHECK:LINE_SPACING: Please don't use multiple blank lines #40: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:637: + + total: 0 errors, 0 warnings, 1 checks, 36 lines checked From patchwork at emeril.freedesktop.org Wed Jun 3 15:58:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 15:58:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/24=5D_Revert_=22drm/i915/gem=3A_Drop?= =?utf-8?q?_relocation_slowpath=22=2E?= In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <159119991255.12265.12982340014174462432@emeril.freedesktop.org> == Series Details == Series: series starting with [01/24] Revert "drm/i915/gem: Drop relocation slowpath". URL : https://patchwork.freedesktop.org/series/77960/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From chris at chris-wilson.co.uk Wed Jun 3 16:09:32 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 3 Jun 2020 17:09:32 +0100 Subject: [Intel-gfx] [PATCH] Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") In-Reply-To: <20200603145529.3851-1-chris@chris-wilson.co.uk> References: <20200603145529.3851-1-chris@chris-wilson.co.uk> Message-ID: <20200603160932.1805-1-chris@chris-wilson.co.uk> This restores 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") by reverting commit 921f0c47f228 ("drm/i915: Revert "drm/i915/tgl: Wa_1607138340""). Our CI machines are recording a rare error where the CS events are out of order, leading to a machine death. Restoring the Wa_1607138340 (i.e. forcing a full restore on every context switch) prevents it. Whether or not is it the same root cause remains to be seen, but since the machine death is quite easy to hit on B0, it is unresolved. Fixes: 921f0c47f228 ("drm/i915: Revert "drm/i915/tgl: Wa_1607138340"") References: 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Francesco Balestrieri --- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index aac8da18694f..b28ea01375ba 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1520,6 +1520,10 @@ static u64 execlists_update_context(struct i915_request *rq) */ wmb(); + /* Wa_1607138340:tgl */ + if (IS_TGL_REVID(ce->engine->i915, TGL_REVID_A0, TGL_REVID_B0)) + desc |= CTX_DESC_FORCE_RESTORE; + ce->lrc.desc &= ~CTX_DESC_FORCE_RESTORE; return desc; } -- 2.20.1 From patchwork at emeril.freedesktop.org Wed Jun 3 16:20:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 16:20:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/24=5D_Revert_=22drm/i915/gem=3A_Drop_re?= =?utf-8?q?location_slowpath=22=2E?= In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <159120125365.12268.4550952652707832957@emeril.freedesktop.org> == Series Details == Series: series starting with [01/24] Revert "drm/i915/gem: Drop relocation slowpath". URL : https://patchwork.freedesktop.org/series/77960/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17854 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17854 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17854, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17854: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gem_contexts: - fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-cfl-8109u/igt at i915_selftest@live at gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-cfl-8109u/igt at i915_selftest@live at gem_contexts.html - fi-skl-lmem: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-skl-lmem/igt at i915_selftest@live at gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-skl-lmem/igt at i915_selftest@live at gem_contexts.html * igt at runner@aborted: - fi-pnv-d510: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-pnv-d510/igt at runner@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][6] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-snb-2520m/igt at runner@aborted.html - fi-byt-n2820: NOTRUN -> [FAIL][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-byt-n2820/igt at runner@aborted.html - fi-snb-2600: NOTRUN -> [FAIL][8] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-snb-2600/igt at runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][9] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-ivb-3770/igt at runner@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][10] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-byt-j1900/igt at runner@aborted.html - fi-elk-e7500: NOTRUN -> [FAIL][11] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-elk-e7500/igt at runner@aborted.html - fi-blb-e6850: NOTRUN -> [FAIL][12] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-blb-e6850/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at i915_selftest@live at gem_execbuf}: - fi-skl-6600u: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-skl-6600u/igt at i915_selftest@live at gem_execbuf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-skl-6600u/igt at i915_selftest@live at gem_execbuf.html - fi-cfl-8109u: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-cfl-8109u/igt at i915_selftest@live at gem_execbuf.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-cfl-8109u/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-7500u: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-7500u/igt at i915_selftest@live at gem_execbuf.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-7500u/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-guc: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-guc/igt at i915_selftest@live at gem_execbuf.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-guc/igt at i915_selftest@live at gem_execbuf.html - fi-bsw-nick: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-nick/igt at i915_selftest@live at gem_execbuf.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bsw-nick/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-8809g: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-8809g/igt at i915_selftest@live at gem_execbuf.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-8809g/igt at i915_selftest@live at gem_execbuf.html - fi-icl-y: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-y/igt at i915_selftest@live at gem_execbuf.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-icl-y/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-r: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-r/igt at i915_selftest@live at gem_execbuf.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-r/igt at i915_selftest@live at gem_execbuf.html - fi-blb-e6850: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-blb-e6850/igt at i915_selftest@live at gem_execbuf.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-blb-e6850/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-x1275: [PASS][31] -> [INCOMPLETE][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at i915_selftest@live at gem_execbuf.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-x1275/igt at i915_selftest@live at gem_execbuf.html - fi-bsw-kefka: [PASS][33] -> [INCOMPLETE][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at i915_selftest@live at gem_execbuf.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bsw-kefka/igt at i915_selftest@live at gem_execbuf.html - fi-cml-s: [PASS][35] -> [INCOMPLETE][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-cml-s/igt at i915_selftest@live at gem_execbuf.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-cml-s/igt at i915_selftest@live at gem_execbuf.html - fi-tgl-y: [PASS][37] -> [INCOMPLETE][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at i915_selftest@live at gem_execbuf.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-tgl-y/igt at i915_selftest@live at gem_execbuf.html - fi-cfl-guc: [PASS][39] -> [INCOMPLETE][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-cfl-guc/igt at i915_selftest@live at gem_execbuf.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-cfl-guc/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-soraka: [PASS][41] -> [INCOMPLETE][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-soraka/igt at i915_selftest@live at gem_execbuf.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-soraka/igt at i915_selftest@live at gem_execbuf.html - {fi-ehl-1}: [PASS][43] -> [INCOMPLETE][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-ehl-1/igt at i915_selftest@live at gem_execbuf.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-ehl-1/igt at i915_selftest@live at gem_execbuf.html - fi-bsw-n3050: [PASS][45] -> [INCOMPLETE][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-n3050/igt at i915_selftest@live at gem_execbuf.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bsw-n3050/igt at i915_selftest@live at gem_execbuf.html - fi-ivb-3770: [PASS][47] -> [INCOMPLETE][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-ivb-3770/igt at i915_selftest@live at gem_execbuf.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-ivb-3770/igt at i915_selftest@live at gem_execbuf.html - fi-skl-lmem: [PASS][49] -> [INCOMPLETE][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-skl-lmem/igt at i915_selftest@live at gem_execbuf.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-skl-lmem/igt at i915_selftest@live at gem_execbuf.html - fi-ilk-650: [PASS][51] -> [INCOMPLETE][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-ilk-650/igt at i915_selftest@live at gem_execbuf.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-ilk-650/igt at i915_selftest@live at gem_execbuf.html - fi-cml-u2: [PASS][53] -> [INCOMPLETE][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-cml-u2/igt at i915_selftest@live at gem_execbuf.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-cml-u2/igt at i915_selftest@live at gem_execbuf.html - fi-icl-guc: [PASS][55] -> [INCOMPLETE][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-guc/igt at i915_selftest@live at gem_execbuf.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-icl-guc/igt at i915_selftest@live at gem_execbuf.html - fi-cfl-8700k: [PASS][57] -> [INCOMPLETE][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-cfl-8700k/igt at i915_selftest@live at gem_execbuf.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-cfl-8700k/igt at i915_selftest@live at gem_execbuf.html - fi-bxt-dsi: [PASS][59] -> [INCOMPLETE][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bxt-dsi/igt at i915_selftest@live at gem_execbuf.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bxt-dsi/igt at i915_selftest@live at gem_execbuf.html - fi-hsw-4770: [PASS][61] -> [INCOMPLETE][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-hsw-4770/igt at i915_selftest@live at gem_execbuf.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-hsw-4770/igt at i915_selftest@live at gem_execbuf.html - {fi-tgl-u}: [PASS][63] -> [INCOMPLETE][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-u/igt at i915_selftest@live at gem_execbuf.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-tgl-u/igt at i915_selftest@live at gem_execbuf.html - fi-skl-6700k2: [PASS][65] -> [INCOMPLETE][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-skl-6700k2/igt at i915_selftest@live at gem_execbuf.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-skl-6700k2/igt at i915_selftest@live at gem_execbuf.html - fi-icl-u2: [PASS][67] -> [INCOMPLETE][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at i915_selftest@live at gem_execbuf.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-icl-u2/igt at i915_selftest@live at gem_execbuf.html - {fi-tgl-dsi}: [PASS][69] -> [INCOMPLETE][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-dsi/igt at i915_selftest@live at gem_execbuf.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-tgl-dsi/igt at i915_selftest@live at gem_execbuf.html - fi-snb-2520m: [PASS][71] -> [INCOMPLETE][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-snb-2520m/igt at i915_selftest@live at gem_execbuf.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-snb-2520m/igt at i915_selftest@live at gem_execbuf.html - fi-whl-u: [PASS][73] -> [INCOMPLETE][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-whl-u/igt at i915_selftest@live at gem_execbuf.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-whl-u/igt at i915_selftest@live at gem_execbuf.html - fi-apl-guc: [PASS][75] -> [INCOMPLETE][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-apl-guc/igt at i915_selftest@live at gem_execbuf.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-apl-guc/igt at i915_selftest@live at gem_execbuf.html - fi-skl-guc: [PASS][77] -> [INCOMPLETE][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-skl-guc/igt at i915_selftest@live at gem_execbuf.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-skl-guc/igt at i915_selftest@live at gem_execbuf.html - fi-bdw-5557u: [PASS][79] -> [INCOMPLETE][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bdw-5557u/igt at i915_selftest@live at gem_execbuf.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bdw-5557u/igt at i915_selftest@live at gem_execbuf.html - fi-bwr-2160: [PASS][81] -> [INCOMPLETE][82] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at i915_selftest@live at gem_execbuf.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bwr-2160/igt at i915_selftest@live at gem_execbuf.html Known issues ------------ Here are the changes found in Patchwork_17854 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-u2: [PASS][83] -> [DMESG-WARN][84] ([i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][85] ([i915#1982]) -> [PASS][86] +1 similar issue [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: [DMESG-WARN][87] ([i915#1982]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-soraka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-soraka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][89] ([i915#1982]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][91] ([i915#1928]) -> [PASS][92] [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][93] ([i915#1982]) -> [PASS][94] [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][95] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][96] ([i915#62] / [i915#92]) +4 similar issues [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][97] ([fdo#109271]) -> [DMESG-FAIL][98] ([i915#62]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][99] ([i915#62] / [i915#92]) -> [DMESG-WARN][100] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#66]: https://gitlab.freedesktop.org/drm/intel/issues/66 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17854 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17854: de0fb243bf50a40b9f92e8689e7b39848d53cc95 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == de0fb243bf50 drm/i915: Kill context before taking ctx->mutex 1f073601ee7f drm/i915: Ensure we hold the pin mutex f60b4639d689 drm/i915: Add ww locking to pin_to_display_plane 2f3fd8b5e141 drm/i915: Add ww locking to vm_fault_gtt 9bb49e2f74c1 drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2. 78eb94b06623 drm/i915: Use ww pinning for intel_context_create_request() 51a11c92d700 drm/i915/selftests: Fix locking inversion in lrc selftest. 4b168d7eb625 drm/i915: Dirty hack to fix selftests locking inversion 756385fc367b drm/i915: Convert i915_perf to ww locking as well de5ef8ca658c drm/i915: Kill last user of intel_context_create_request outside of selftests 18ebd9d92415 drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. fc5ed58aad70 drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. 2da536f6aca7 drm/i915: Rework intel_context pinning to do everything outside of pin_mutex 5e983148f18d drm/i915: Pin engine before pinning all objects, v4. 36d3bd7c0420 drm/i915: Nuke arguments to eb_pin_engine b25ba367c26d drm/i915: Add ww context handling to context_barrier_task 2d2857b3d5ae drm/i915: Use ww locking in intel_renderstate. 45f9dff46487 drm/i915: Use per object locking in execbuf, v11. 7d8b20457516 drm/i915/gem: Make eb_add_lut interruptible wait on object lock. 550bd4348656 Revert "drm/i915/gem: Split eb_vma into its own allocation" ef8df645976c drm/i915: Parse command buffer earlier in eb_relocate(slow) c412b07e522c drm/i915: Remove locking from i915_gem_object_prepare_read/write 1534f179b1ab drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. a8a26d902de0 Revert "drm/i915/gem: Drop relocation slowpath". == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/index.html From patchwork at emeril.freedesktop.org Wed Jun 3 16:24:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 16:24:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Restore_=2208fff7aeddc9_=28=22drm/i915/tgl=3A_Wa=5F16071383?= =?utf-8?b?NDAiKSAocmV2Mik=?= In-Reply-To: <20200603145529.3851-1-chris@chris-wilson.co.uk> References: <20200603145529.3851-1-chris@chris-wilson.co.uk> Message-ID: <159120144760.12265.1909503251791691921@emeril.freedesktop.org> == Series Details == Series: Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") (rev2) URL : https://patchwork.freedesktop.org/series/77959/ State : warning == Summary == $ dim checkpatch origin/drm-tip 86cd48e787fe Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") -:6: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("")' - ie: 'commit 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340")' #6: This restores 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") by reverting -:7: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 921f0c47f228 ("drm/i915: Revert "drm/i915/tgl: Wa_1607138340"")' #7: commit 921f0c47f228 ("drm/i915: Revert "drm/i915/tgl: Wa_1607138340""). -:16: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340")' #16: References: 08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") total: 3 errors, 0 warnings, 0 checks, 10 lines checked From patchwork at emeril.freedesktop.org Wed Jun 3 16:51:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 16:51:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgUmVz?= =?utf-8?q?tore_=2208fff7aeddc9_=28=22drm/i915/tgl=3A_Wa=5F1607138340=22?= =?utf-8?b?KSAocmV2Mik=?= In-Reply-To: <20200603145529.3851-1-chris@chris-wilson.co.uk> References: <20200603145529.3851-1-chris@chris-wilson.co.uk> Message-ID: <159120310339.12267.7864264457769158564@emeril.freedesktop.org> == Series Details == Series: Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") (rev2) URL : https://patchwork.freedesktop.org/series/77959/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17855 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17855 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17855, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17855: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at hangcheck: - fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-tgl-y/igt at i915_selftest@live at hangcheck.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at hangcheck: - {fi-tgl-u}: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-u/igt at i915_selftest@live at hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-tgl-u/igt at i915_selftest@live at hangcheck.html - {fi-tgl-dsi}: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-dsi/igt at i915_selftest@live at hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-tgl-dsi/igt at i915_selftest@live at hangcheck.html Known issues ------------ Here are the changes found in Patchwork_17855 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#1982] / [i915#62] / [i915#92]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 43) ------------------------------ Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17855 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17855: 86cd48e787fedad887373f1d9eabf80342fd8afe @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 86cd48e787fe Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/index.html From chris at chris-wilson.co.uk Wed Jun 3 16:56:13 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 03 Jun 2020 17:56:13 +0100 Subject: [Intel-gfx] ✗ Fi.CI.BAT: failure for Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") (rev2) In-Reply-To: <159120310339.12267.7864264457769158564@emeril.freedesktop.org> References: <20200603145529.3851-1-chris@chris-wilson.co.uk> <159120310339.12267.7864264457769158564@emeril.freedesktop.org> Message-ID: <159120337346.25109.17865252221702367032@build.alporthouse.com> Quoting Patchwork (2020-06-03 17:51:43) > == Series Details == > > Series: Restore "08fff7aeddc9 ("drm/i915/tgl: Wa_1607138340") (rev2) > URL : https://patchwork.freedesktop.org/series/77959/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17855 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17855 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17855, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17855: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at i915_selftest@live at hangcheck: > - fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at i915_selftest@live at hangcheck.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-tgl-y/igt at i915_selftest@live at hangcheck.html > > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * igt at i915_selftest@live at hangcheck: > - {fi-tgl-u}: [PASS][3] -> [INCOMPLETE][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-u/igt at i915_selftest@live at hangcheck.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-tgl-u/igt at i915_selftest@live at hangcheck.html > - {fi-tgl-dsi}: [PASS][5] -> [INCOMPLETE][6] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-dsi/igt at i915_selftest@live at hangcheck.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17855/fi-tgl-dsi/igt at i915_selftest@live at hangcheck.html Well that would be a compelling reason not to. Let's just wait for working HW. -Chris From patchwork at emeril.freedesktop.org Wed Jun 3 17:10:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 17:10:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Suppress_the_error_message_for_GT_init_failure_on_e?= =?utf-8?q?rror_injection?= In-Reply-To: <20200603104657.25651-1-chris@chris-wilson.co.uk> References: <20200603104657.25651-1-chris@chris-wilson.co.uk> Message-ID: <159120421131.12268.18369030796443070150@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Suppress the error message for GT init failure on error injection URL : https://patchwork.freedesktop.org/series/77949/ State : success == Summary == CI Bug Log - changes from CI_DRM_8575_full -> Patchwork_17850_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17850_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-queues-priority-all: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#93] / [i915#95]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-kbl3/igt at gem_exec_whisper@basic-queues-priority-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-kbl6/igt at gem_exec_whisper@basic-queues-priority-all.html * igt at gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#644]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-glk8/igt at gem_ppgtt@flink-and-close-vma-leak.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-glk2/igt at gem_ppgtt@flink-and-close-vma-leak.html * igt at i915_pm_rpm@fences-dpms: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl7/igt at i915_pm_rpm@fences-dpms.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl6/igt at i915_pm_rpm@fences-dpms.html * igt at kms_color@pipe-b-ctm-negative: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-skl7/igt at kms_color@pipe-b-ctm-negative.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-skl1/igt at kms_color@pipe-b-ctm-negative.html * igt at kms_cursor_crc@pipe-a-cursor-dpms: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-dpms.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-skl10/igt at kms_cursor_crc@pipe-a-cursor-dpms.html - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-dpms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-dpms.html - shard-apl: [PASS][13] -> [FAIL][14] ([i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl3/igt at kms_cursor_crc@pipe-a-cursor-dpms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl7/igt at kms_cursor_crc@pipe-a-cursor-dpms.html * igt at kms_cursor_crc@pipe-c-cursor-64x21-onscreen: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +17 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl2/igt at kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-64x21-onscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#52] / [i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-skl1/igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-skl10/igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-iclb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl2/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][27] -> [INCOMPLETE][28] ([i915#648] / [i915#69]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-skl10/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-skl10/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html #### Possible fixes #### * igt at gem_ctx_param@basic: - shard-glk: [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-glk8/igt at gem_ctx_param@basic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-glk2/igt at gem_ctx_param@basic.html * igt at gem_exec_nop@basic-parallel: - shard-apl: [DMESG-WARN][31] ([i915#95]) -> [PASS][32] +19 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl7/igt at gem_exec_nop@basic-parallel.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl8/igt at gem_exec_nop@basic-parallel.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [DMESG-WARN][33] ([i915#1992]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html * {igt at kms_atomic_transition@plane-all-transition-nonblocking at pipe-c}: - shard-tglb: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking at pipe-c.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-tglb5/igt at kms_atomic_transition@plane-all-transition-nonblocking at pipe-c.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][37] ([i915#118] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_big_fb@yf-tiled-16bpp-rotate-0: - shard-apl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl2/igt at kms_big_fb@yf-tiled-16bpp-rotate-0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl8/igt at kms_big_fb@yf-tiled-16bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-green-to-red: - shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +5 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-skl8/igt at kms_color@pipe-c-ctm-green-to-red.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-skl6/igt at kms_color@pipe-c-ctm-green-to-red.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - shard-kbl: [DMESG-WARN][43] ([i915#93] / [i915#95]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-kbl3/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-kbl6/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * {igt at kms_flip@flip-vs-expired-vblank at c-dp1}: - shard-apl: [FAIL][45] ([i915#79]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl1/igt at kms_flip@flip-vs-expired-vblank at c-dp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl1/igt at kms_flip@flip-vs-expired-vblank at c-dp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-edp1}: - shard-skl: [INCOMPLETE][47] ([i915#198]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-skl6/igt at kms_flip@flip-vs-suspend-interruptible at a-edp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-skl3/igt at kms_flip@flip-vs-suspend-interruptible at a-edp1.html * {igt at kms_flip@flip-vs-suspend at a-dp1}: - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +4 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl8/igt at kms_flip@flip-vs-suspend at a-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl3/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-iclb8/igt at kms_psr@psr2_cursor_plane_onoff.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-iclb: [INCOMPLETE][57] ([i915#1078] / [i915#1185]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-iclb3/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-iclb8/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][59] ([i915#468]) -> [FAIL][60] ([i915#1899]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-tglb8/igt at i915_pm_dc@dc6-psr.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][61] ([i915#1515]) -> [WARN][62] ([i915#1515]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-iclb6/igt at i915_pm_rc6_residency@rc6-idle.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-iclb3/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][63] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][64] ([i915#1319] / [i915#1635]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl7/igt at kms_content_protection@atomic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][65] ([i915#1319]) -> [FAIL][66] ([fdo#110321] / [fdo#110336]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl1/igt at kms_content_protection@atomic-dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][67] ([i915#1319]) -> [FAIL][68] ([fdo#110321]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl3/igt at kms_content_protection@lic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][69] ([fdo#110321]) -> [TIMEOUT][70] ([i915#1319]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-apl2/igt at kms_content_protection@srm.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [DMESG-FAIL][71] ([i915#1925] / [i915#1926]) -> [DMESG-WARN][72] ([i915#1926]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-glk8/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-glk1/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-FAIL][73] ([i915#1925] / [i915#1926]) -> [DMESG-WARN][74] ([i915#1927]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8575/shard-glk8/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/shard-glk2/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1078]: https://gitlab.freedesktop.org/drm/intel/issues/1078 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1992]: https://gitlab.freedesktop.org/drm/intel/issues/1992 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8575 -> Patchwork_17850 CI-20190529: 20190529 CI_DRM_8575: b261605291bae8f267174f92df7513a3a7184573 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5692: c98c9ad6d06c4eb8b05b23ef0bbe0159730e387f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17850: cde9b765b01965ff9ab1c632022242467263c608 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17850/index.html From nirmodas at amd.com Wed Jun 3 09:10:29 2020 From: nirmodas at amd.com (Nirmoy) Date: Wed, 3 Jun 2020 11:10:29 +0200 Subject: [Intel-gfx] [RFC PATCH 1/1] drm/mm: add ig_frag selftest In-Reply-To: <dd8eb88b-3d48-0ece-7290-2a7fc8e1e3af@amd.com> References: <20200529163351.5228-1-nirmoy.das@amd.com> <cdb604b7-0817-c786-45f6-3c2f9a395c70@amd.com> <159076753114.8851.15594151673471255964@build.alporthouse.com> <80a791cd-1319-795d-bd8a-1bf7dd6b9cc3@amd.com> <9cbdb0e2-5a44-5f87-df83-74c6b0c72e27@amd.com> <6b2d0137-8b7c-2dd0-b49f-1bf6bb300c06@amd.com> <dd8eb88b-3d48-0ece-7290-2a7fc8e1e3af@amd.com> Message-ID: <df085c97-c9b6-2223-b045-ca671b4b808b@amd.com> On 6/2/20 4:25 PM, Christian K?nig wrote: > Am 02.06.20 um 16:13 schrieb Nirmoy: >> Hi Christian, >> >> On 6/2/20 2:47 PM, Christian K?nig wrote: >>> Nirmoy please keep in mind that your current implementation doesn't >>> fully solve the issue the test case is exercising. >>> >>> In other words what you have implement is fast skipping of >>> fragmented address space for bottom-up and top-down. >>> >>> But what this test here exercises is the fast skipping of aligned >>> allocations. You should probably adjust the test case a bit. >> >> >> Allocations with size=4k and aign = 8k is known to introduce >> fragmentation, > > Yes, but this fragmentation can't be avoided with what we already > implemented. For this we would need the extension with the alignment I > already explained. > >> do you mean I should only test bottom-up and top-down >> >> for now ? > > Yes and no. > > What we need to test is the following: > > 1. Make tons of allocations with size=4k and align=0. > > 2. Free every other of those allocations. > > 3. Make tons of allocations with size=8k and align=0. > > Previously bottom-up and top-down would have checked all the holes > created in step #2. > > With your change they can immediately see that this doesn't make sense > and shortcut to the leftmost/rightmost leaf node in the tree with the > large free block. > > That we can handle the alignment as well is the next step of that. Thanks Christian for the detailed explanation. I have modified this as you suggested, will send in few minutes. Regards, Nirmoy > > Regards, > Christian. > >> >> >> Regards, >> >> Nirmoy >> >> >>> >>> >>> Regards, >>> Christian. >>> >>> Am 29.05.20 um 23:01 schrieb Nirmoy: >>>> >>>> On 5/29/20 5:52 PM, Chris Wilson wrote: >>>>> Quoting Nirmoy (2020-05-29 16:40:53) >>>>>> This works correctly most of the times but sometimes >>>> >>>> >>>> I have to take my word back. In another machine,? 20k insertions in >>>> >>>> best mode takes 6-9 times more than 10k insertions, all most all >>>> the time. >>>> >>>> evict, bottom-up and top-down modes remains in 2-5 times range. >>>> >>>> >>>> If I reduce the insertions to 1k and 2k then scaling factor for >>>> best mode stays? below 4 most of the time. >>>> >>>> evict, bottom-up and top-down modes remains in 2-3 times range. >>>> >>>> >>>> I wonder if it makes sense to test with only 1k and 2k insertions >>>> and tolerate more than error if the mode == best. >>>> >>>> Regards, >>>> >>>> Nirmoy >>>> >>>>>> >>>>>> 20k insertions can take more than 8 times of 10k insertion time. >>>>> The pressure is on to improve then :) >>>>> >>>>>> Regards, >>>>>> >>>>>> Nirmoy >>>>>> >>>>>> On 5/29/20 6:33 PM, Nirmoy Das wrote: >>>>>>> This patch introduces fragmentation in the address range >>>>>>> and measures time taken by 10k and 20k insertions. ig_frag() >>>>>>> will fail if time taken by 20k insertions takes more than 4 times >>>>>>> of 10k insertions as we know that insertions scale quadratically. >>>>>>> Also tolerate 10% error because of kernel scheduler's jitters. >>>>>>> >>>>>>> Output: >>>>>>> <snip> >>>>>>> [ 8092.653518] drm_mm: Testing DRM range manger (struct drm_mm), >>>>>>> with random_seed=0x9bfb4117 max_iterations=8192 max_prime=128 >>>>>>> [ 8092.653520] drm_mm: igt_sanitycheck - ok! >>>>>>> [ 8092.653525] igt_debug 0x0000000000000000-0x0000000000000200: >>>>>>> 512: free >>>>>>> [ 8092.653526] igt_debug 0x0000000000000200-0x0000000000000600: >>>>>>> 1024: used >>>>>>> [ 8092.653527] igt_debug 0x0000000000000600-0x0000000000000a00: >>>>>>> 1024: free >>>>>>> [ 8092.653528] igt_debug 0x0000000000000a00-0x0000000000000e00: >>>>>>> 1024: used >>>>>>> [ 8092.653529] igt_debug 0x0000000000000e00-0x0000000000001000: >>>>>>> 512: free >>>>>>> [ 8092.653529] igt_debug total: 4096, used 2048 free 2048 >>>>>>> [ 8112.569813] drm_mm: best fragmented insert of 10000 and 20000 >>>>>>> insertions took 504 and 1996 msecs >>>>>>> [ 8112.723254] drm_mm: bottom-up fragmented insert of 10000 and >>>>>>> 20000 insertions took 44 and 108 msecs >>>>>>> [ 8112.813212] drm_mm: top-down fragmented insert of 10000 and >>>>>>> 20000 insertions took 40 and 44 msecs >>>>>>> [ 8112.847733] drm_mm: evict fragmented insert of 10000 and >>>>>>> 20000 insertions took 8 and 20 msecs >>>>>>> <snip> >>>>>>> >>>>>>> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com> >>>>>>> --- >>>>>>> ?? drivers/gpu/drm/selftests/drm_mm_selftests.h |? 1 + >>>>>>> ?? drivers/gpu/drm/selftests/test-drm_mm.c????? | 73 >>>>>>> ++++++++++++++++++++ >>>>>>> ?? 2 files changed, 74 insertions(+) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>>> b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>>> index 6b943ea1c57d..8c87c964176b 100644 >>>>>>> --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>>> +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>>>>>> @@ -14,6 +14,7 @@ selftest(insert, igt_insert) >>>>>>> ?? selftest(replace, igt_replace) >>>>>>> ?? selftest(insert_range, igt_insert_range) >>>>>>> ?? selftest(align, igt_align) >>>>>>> +selftest(frag, igt_frag) >>>>>>> ?? selftest(align32, igt_align32) >>>>>>> ?? selftest(align64, igt_align64) >>>>>>> ?? selftest(evict, igt_evict) >>>>>>> diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>>> b/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>>> index 9aabe82dcd3a..05d8f3659b4d 100644 >>>>>>> --- a/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>>> +++ b/drivers/gpu/drm/selftests/test-drm_mm.c >>>>>>> @@ -1033,6 +1033,79 @@ static int igt_insert_range(void *ignored) >>>>>>> ?????? return 0; >>>>>>> ?? } >>>>>>> ?? +static int get_insert_time(unsigned int num_insert, >>>>>>> +??????????????????????? const struct insert_mode *mode) >>>>>>> +{ >>>>>>> +???? struct drm_mm mm; >>>>>>> +???? struct drm_mm_node *nodes, *node, *next; >>>>>>> +???? unsigned int size = 4096, align = 8192; >>>>>>> +???? unsigned long start; >>>>>>> +???? unsigned int i; >>>>>>> +???? int ret = -EINVAL; >>>>>>> + >>>>>>> +???? drm_mm_init(&mm, 1, U64_MAX - 2); >>>>>>> +???? nodes = vzalloc(array_size(num_insert, sizeof(*nodes))); >>>>>>> +???? if (!nodes) >>>>>>> +???????????? goto err; >>>>>>> + >>>>>>> +???? start = jiffies; >>>>> Use ktime_t start = ktime_now(); >>>>> >>>>>>> +???? for (i = 0; i < num_insert; i++) { >>>>>>> +???????????? if (!expect_insert(&mm, &nodes[i], size, align, i, >>>>>>> mode)) { >>>>>>> +???????????????????? pr_err("%s insert failed\n", mode->name); >>>>>>> +???????????????????? goto out; >>>>>>> +???????????? } >>>>>>> +???? } >>>>>>> + >>>>>>> +???? ret = jiffies_to_msecs(jiffies - start); >>>>> ret = ktime_sub(ktime_now(), start); >>>>> >>>>> The downside to using ktime is remembering it is s64 and so >>>>> requires care >>>>> and attention in doing math. >>>>> >>>>>>> +out: >>>>>>> +???? drm_mm_for_each_node_safe(node, next, &mm) >>>>>>> +???????????? drm_mm_remove_node(node); >>>>>>> +???? drm_mm_takedown(&mm); >>>>>>> +???? vfree(nodes); >>>>>>> +err: >>>>>>> +???? return ret; >>>>>>> + >>>>>>> +} >>>>>>> + >>>>>>> +static int igt_frag(void *ignored) >>>>>>> +{ >>>>>>> +???? const struct insert_mode *mode; >>>>>>> +???? unsigned int insert_time1, insert_time2; >>>>>>> +???? unsigned int insert_size = 10000; >>>>>>> +???? unsigned int scale_factor = 4; >>>>>>> +???? /* tolerate 10% excess insertion duration */ >>>>>>> +???? unsigned int error_factor = 110; >>>>>>> +???? int ret = -EINVAL; >>>>>>> + >>>>>>> +???? for (mode = insert_modes; mode->name; mode++) { >>>>>>> +???????????? unsigned int expected_time; >>>>>>> + >>>>>>> +???????????? insert_time1 = get_insert_time(insert_size, mode); >>>>>>> +???????????? if (insert_time1 < 0) >>>>>>> +???????????????????? goto err; >>>>> Ah, can you propagate the actual error. I see you are returning >>>>> EINVAL >>>>> for ENOMEM errors. Just wait until it hits and you have to debug >>>>> why :) >>>>> >>>>>>> +???????????? insert_time2 = get_insert_time((insert_size * 2), >>>>>>> mode); >>>>>>> +???????????? if (insert_time2 < 0) >>>>>>> +???????????????????? goto err; >>>>>>> + >>>>>>> +???????????? expected_time = (scale_factor * insert_time1 * >>>>>>> +????????????????????????????? error_factor)/100; >>>>>>> +???????????? if (insert_time2 > expected_time) { >>>>>>> +???????????????????? pr_err("%s fragmented insert took more %u >>>>>>> msecs\n", >>>>>>> +??????????????????????????? mode->name, insert_time2 - >>>>>>> expected_time); >>>>>>> +???????????????????? goto err; >>>>>>> +???????????? } >>>>>>> + >>>>>>> +???????????? pr_info("%s fragmented insert of %u and %u >>>>>>> insertions took %u and %u msecs\n", >>>>>>> +???????????????????? mode->name, insert_size, insert_size * 2, >>>>>>> insert_time1, >>>>>>> +???????????????????? insert_time2); >>>>> Put the info first before the error. We always want the full details, >>>>> with the error message explaining why it's unhappy. >>>>> -Chris >>>>> _______________________________________________ >>>>> dri-devel mailing list >>>>> dri-devel at lists.freedesktop.org >>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=02%7C01%7Cnirmoy.das%40amd.com%7C5c7df129b9cf44b3ae4008d803e84445%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637263643415833767&sdata=PrCQse4nhN0ZITT9OniuHhF7A5uxJD6ehk0PMjm7WMU%3D&reserved=0 >>>>> >>> > From nirmoy.aiemd at gmail.com Wed Jun 3 10:32:23 2020 From: nirmoy.aiemd at gmail.com (Nirmoy Das) Date: Wed, 3 Jun 2020 12:32:23 +0200 Subject: [Intel-gfx] [PATCH v2 1/1] drm/mm: add ig_frag selftest Message-ID: <20200603103223.10443-1-nirmoy.das@amd.com> This patch introduces fragmentation in the address range and measures time taken by 10k and 20k insertions. ig_frag() will fail if the time taken by 20k insertions takes more than 4 times of 10k insertions as we know that insertions should at most scale quadratically. v2: introduce fragmentation by freeing every other node. only test bottom-up and top-down for now. Signed-off-by: Nirmoy Das <nirmoy.das at amd.com> --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 124 +++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h b/drivers/gpu/drm/selftests/drm_mm_selftests.h index 6b943ea1c57d..8c87c964176b 100644 --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h @@ -14,6 +14,7 @@ selftest(insert, igt_insert) selftest(replace, igt_replace) selftest(insert_range, igt_insert_range) selftest(align, igt_align) +selftest(frag, igt_frag) selftest(align32, igt_align32) selftest(align64, igt_align64) selftest(evict, igt_evict) diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c b/drivers/gpu/drm/selftests/test-drm_mm.c index 9aabe82dcd3a..34231baacd87 100644 --- a/drivers/gpu/drm/selftests/test-drm_mm.c +++ b/drivers/gpu/drm/selftests/test-drm_mm.c @@ -10,6 +10,7 @@ #include <linux/slab.h> #include <linux/random.h> #include <linux/vmalloc.h> +#include <linux/ktime.h> #include <drm/drm_mm.h> @@ -1033,6 +1034,129 @@ static int igt_insert_range(void *ignored) return 0; } +static int prepare_igt_frag(struct drm_mm *mm, + struct drm_mm_node *nodes, + unsigned int num_insert, + const struct insert_mode *mode) +{ + unsigned int size = 4096; + unsigned int i; + u64 ret = -EINVAL; + + for (i = 0; i < num_insert; i++) { + if (!expect_insert(mm, &nodes[i], size, 0, i, + mode) != 0) { + pr_err("%s insert failed\n", mode->name); + goto out; + } + } + + /* introduce fragmentation by freeing every other node */ + for (i = 0; i < num_insert; i++) { + if (i % 2 == 0) + drm_mm_remove_node(&nodes[i]); + } + +out: + return ret; + +} + +static u64 get_insert_time(struct drm_mm *mm, + unsigned int num_insert, + struct drm_mm_node *nodes, + const struct insert_mode *mode) +{ + unsigned int size = 8192; + ktime_t start; + unsigned int i; + u64 ret = -EINVAL; + + start = ktime_get(); + for (i = 0; i < num_insert; i++) { + if (!expect_insert(mm, &nodes[i], size, 0, i, mode) != 0) { + pr_err("%s insert failed\n", mode->name); + goto out; + } + } + + ret = ktime_to_ns(ktime_sub(ktime_get(), start)); + +out: + return ret; + +} + +static int igt_frag(void *ignored) +{ + struct drm_mm mm; + const struct insert_mode *mode; + struct drm_mm_node *nodes, *node, *next; + unsigned int insert_size = 10000; + unsigned int scale_factor = 4; + int ret = -EINVAL; + + /* We need 4 * insert_size nodes to hold intermediate allocated + * drm_mm nodes. + * 1 times for prepare_igt_frag() + * 1 times for get_insert_time() + * 2 times for get_insert_time() + */ + nodes = vzalloc(array_size(insert_size * 4, sizeof(*nodes))); + if (!nodes) + return -ENOMEM; + + /* For BOTTOMUP and TOPDOWN, we first fragment the + * address space using prepare_igt_frag() and then try to verify + * that that insertions scale quadratically from 10k to 20k insertions + */ + drm_mm_init(&mm, 1, U64_MAX - 2); + for (mode = insert_modes; mode->name; mode++) { + u64 insert_time1, insert_time2; + + if (mode->mode != DRM_MM_INSERT_LOW || + mode->mode != DRM_MM_INSERT_HIGH) + continue; + + ret = prepare_igt_frag(&mm, nodes, insert_size, mode); + if (!ret) + goto err; + + insert_time1 = get_insert_time(&mm, insert_size, + nodes + insert_size, mode); + if (insert_time1 < 0) + goto err; + + insert_time2 = get_insert_time(&mm, (insert_size * 2), + nodes + insert_size * 2, mode); + if (insert_time2 < 0) + goto err; + + pr_info("%s fragmented insert of %u and %u insertions took %llu and %llu nsecs\n", + mode->name, insert_size, insert_size * 2, + insert_time1, insert_time2); + + if (insert_time2 > (scale_factor * insert_time1)) { + pr_err("%s fragmented insert took %llu nsecs more\n", + mode->name, + insert_time2 - (scale_factor * insert_time1)); + goto err; + } + + drm_mm_for_each_node_safe(node, next, &mm) + drm_mm_remove_node(node); + } + + ret = 0; +err: + drm_mm_for_each_node_safe(node, next, &mm) + drm_mm_remove_node(node); + drm_mm_takedown(&mm); + vfree(nodes); + + return ret; +} + static int igt_align(void *ignored) { const struct insert_mode *mode; -- 2.26.2 From patchwork at emeril.freedesktop.org Wed Jun 3 18:07:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 18:07:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv2=2C1/1=5D_drm/mm=3A_add_ig=5Ffrag?= =?utf-8?q?_selftest?= In-Reply-To: <20200603103223.10443-1-nirmoy.das@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> Message-ID: <159120767033.12268.17202571959839081190@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/1] drm/mm: add ig_frag selftest URL : https://patchwork.freedesktop.org/series/77964/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3560e47537d1 drm/mm: add ig_frag selftest -:72: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #72: FILE: drivers/gpu/drm/selftests/test-drm_mm.c:1063: + +} -:97: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #97: FILE: drivers/gpu/drm/selftests/test-drm_mm.c:1088: + +} -:171: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Nirmoy Das <nirmoy.aiemd at gmail.com>' total: 0 errors, 1 warnings, 2 checks, 143 lines checked From patchwork at emeril.freedesktop.org Wed Jun 3 18:29:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 18:29:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/1=5D_drm/mm=3A_add_ig=5Ffrag_selfte?= =?utf-8?q?st?= In-Reply-To: <20200603103223.10443-1-nirmoy.das@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> Message-ID: <159120896408.12265.16056016731329406693@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/1] drm/mm: add ig_frag selftest URL : https://patchwork.freedesktop.org/series/77964/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17856 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/index.html Known issues ------------ Here are the changes found in Patchwork_17856 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_psr@primary_page_flip: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at kms_psr@primary_page_flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-tgl-y/igt at kms_psr@primary_page_flip.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][15] ([i915#1928]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][19] ([fdo#109271]) -> [DMESG-FAIL][20] ([i915#62] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 45) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17856 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17856: 3560e47537d1185a5d719e8abc8dc0eb5a4289d2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3560e47537d1 drm/mm: add ig_frag selftest == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/index.html From jose.souza at intel.com Wed Jun 3 19:43:06 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Wed, 3 Jun 2020 12:43:06 -0700 Subject: [Intel-gfx] [PATCH v2 1/3] drm/i915/bios: Parse HOBL parameter Message-ID: <20200603194308.78622-1-jose.souza@intel.com> HOBL means hours of battery life, it is a power-saving feature were supported motherboards can use a special voltage swing table that uses less power. So here parsing the VBT to check if this feature is supported. While at it already added the VRR parameter too. BSpec: 20150 Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 3 +++ drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 839124647202..b3c453aa7623 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -722,6 +722,9 @@ parse_power_conservation_features(struct drm_i915_private *dev_priv, */ if (!(power->drrs & BIT(panel_type))) dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; + + if (bdb->version >= 232) + dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type); } static void diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index aef7fe932d1a..65f552f57e06 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -820,6 +820,8 @@ struct bdb_lfp_power { u16 adb; u16 lace_enabled_status; struct agressiveness_profile_entry aggressivenes[16]; + u16 hobl; /* 232+ */ + u16 vrr; /* 233+ */ } __packed; /* diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e99255e17eb7..2336c9231eef 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -690,6 +690,7 @@ struct intel_vbt_data { bool initialized; int bpp; struct edp_power_seq pps; + bool hobl; } edp; struct { -- 2.27.0 From jose.souza at intel.com Wed Jun 3 19:43:07 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Wed, 3 Jun 2020 12:43:07 -0700 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915/display: Implement HOBL In-Reply-To: <20200603194308.78622-1-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> Message-ID: <20200603194308.78622-2-jose.souza@intel.com> Hours Of Battery Life is a new GEN12+ power-saving feature that allows supported motherboards to use a special voltage swing table for eDP panels that uses less power. So here if supported by HW, OEM will set it in VBT and i915 will try to train link with HOBL vswing table if link training fails it fall back to the original table. Just not sure if DP compliance should also use this new voltage swing table too, cced some folks that worked in DP compliance. BSpec: 49291 BSpec: 49399 Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Animesh Manna <animesh.manna at intel.com> Cc: Manasi Navare <manasi.d.navare at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++-- .../drm/i915/display/intel_display_types.h | 2 + .../drm/i915/display/intel_dp_link_training.c | 20 +++++++- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 2 + 5 files changed, 69 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 236f3762b6f9..57174a111976 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { + { 0x6, 0x7F, 0x3F, 0x00, 0x00 } +}; + static const struct ddi_buf_trans * bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) { @@ -2301,14 +2305,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); } +/* + * If supported return HOBL vswing table and set registers to enable HOBL + * otherwise returns NULL and unset registers to enable HOBL. + */ +static const struct cnl_ddi_buf_trans * +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv, + struct intel_encoder *encoder, int type, int rate, + u32 level, int *n_entries) +{ + const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct intel_dp *intel_dp; + + if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP) + return NULL; + + intel_dp = enc_to_intel_dp(encoder); + if (!intel_dp->try_hobl || rate > 540000) { + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0); + return NULL; + } + + drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy)); + drm_WARN_ON_ONCE(&dev_priv->drm, level > 0); + + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en); + /* Same table applies to TGL, RKL and DG1 */ + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; +} + static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, - u32 level, enum phy phy, int type, - int rate) + struct intel_encoder *encoder, + u32 level, enum phy phy, int type, + int rate) { const struct cnl_ddi_buf_trans *ddi_translations = NULL; u32 n_entries, val; int ln; + ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type, + rate, level, &n_entries); + if (ddi_translations) + goto hobl_found; + if (INTEL_GEN(dev_priv) >= 12) ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, &n_entries); @@ -2321,6 +2362,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, if (!ddi_translations) return; +hobl_found: if (level >= n_entries) { drm_dbg_kms(&dev_priv->drm, "DDI translation not found for level %d. Using %d instead.", @@ -2428,7 +2470,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); + icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate); /* 6. Set training enable to trigger update */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..f8943b67819d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1375,6 +1375,8 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; + + bool try_hobl; }; enum lspcon_vendor { diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index b9e4ee2dbddc..88f366bb28d7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -52,12 +52,24 @@ static u8 dp_voltage_max(u8 preemph) void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const u8 link_status[DP_LINK_STATUS_SIZE]) { + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 v = 0; u8 p = 0; int lane; u8 voltage_max; u8 preemph_max; + if (intel_dp->try_hobl) { + /* + * Do not adjust, try now with the regular table using VSwing 0 + * and pre-emp 0 + */ + intel_dp->try_hobl = false; + drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link " + "training, switching back to regular table\n"); + return; + } + for (lane = 0; lane < intel_dp->lane_count; lane++) { v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); @@ -103,9 +115,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, } static bool -intel_dp_reset_link_train(struct intel_dp *intel_dp, - u8 dp_train_pat) +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) { + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) + intel_dp->try_hobl = true; + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp_set_signal_levels(intel_dp); return intel_dp_set_link_train(intel_dp, dp_train_pat); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2336c9231eef..c7e7df17eef2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1687,6 +1687,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12) + static inline bool intel_vtd_active(void) { #ifdef CONFIG_INTEL_IOMMU diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 578cfe11cbb9..d4611171f075 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define PWR_DOWN_LN_3_1_0 (0xb << 4) #define PWR_DOWN_LN_MASK (0xf << 4) #define PWR_DOWN_LN_SHIFT 4 +#define EDP4K2K_MODE_OVRD_EN (1 << 3) +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) #define ICL_LANE_ENABLE_AUX (1 << 0) -- 2.27.0 From jose.souza at intel.com Wed Jun 3 19:43:08 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Wed, 3 Jun 2020 12:43:08 -0700 Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/display: Enable HOBL regardless the VBT value In-Reply-To: <20200603194308.78622-1-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> Message-ID: <20200603194308.78622-3-jose.souza@intel.com> HOBL worked in my TGL RVP even without the necessary HW support, also it worked in more than half of the TGL machines in CI so it is worthy to enable it by default. Even if link training fails with this new vswing table it will only cause one additional link training, that is worthy the try to get the additional power-savings. Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 88f366bb28d7..13f7bc0a4bc0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -119,7 +119,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) + if (HAS_HOBL(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->try_hobl = true; memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); -- 2.27.0 From patchwork at emeril.freedesktop.org Wed Jun 3 19:50:47 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 19:50:47 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5Bv2=2C1/3=5D_drm/i915/bios=3A_Parse_HOBL?= =?utf-8?q?_parameter?= In-Reply-To: <20200603194308.78622-1-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> Message-ID: <159121384771.12267.16975685391362277040@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/3] drm/i915/bios: Parse HOBL parameter URL : https://patchwork.freedesktop.org/series/77966/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Wed Jun 3 20:11:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 20:11:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/3=5D_drm/i915/bios=3A_Parse_HOBL_pa?= =?utf-8?q?rameter?= In-Reply-To: <20200603194308.78622-1-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> Message-ID: <159121508849.12267.2815626409616194703@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/3] drm/i915/bios: Parse HOBL parameter URL : https://patchwork.freedesktop.org/series/77966/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17857 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/index.html Known issues ------------ Here are the changes found in Patchwork_17857 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][9] ([i915#1928]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at i915_pm_rpm@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-kbl-x1275/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17857 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17857: e333b5ede9369eb28a775ce63e45def78b64d4a3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e333b5ede936 drm/i915/display: Enable HOBL regardless the VBT value 35dda9799440 drm/i915/display: Implement HOBL f4eeb33eb557 drm/i915/bios: Parse HOBL parameter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/index.html From ville.syrjala at linux.intel.com Wed Jun 3 20:33:46 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 3 Jun 2020 23:33:46 +0300 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915/display: Implement HOBL In-Reply-To: <20200603194308.78622-2-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> <20200603194308.78622-2-jose.souza@intel.com> Message-ID: <20200603203346.GQ6112@intel.com> On Wed, Jun 03, 2020 at 12:43:07PM -0700, Jos? Roberto de Souza wrote: > Hours Of Battery Life is a new GEN12+ power-saving feature that allows > supported motherboards to use a special voltage swing table for eDP > panels that uses less power. > > So here if supported by HW, OEM will set it in VBT and i915 will try > to train link with HOBL vswing table if link training fails it fall > back to the original table. > > Just not sure if DP compliance should also use this new voltage swing > table too, cced some folks that worked in DP compliance. > > BSpec: 49291 > BSpec: 49399 > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Animesh Manna <animesh.manna at intel.com> > Cc: Manasi Navare <manasi.d.navare at intel.com> > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++-- > .../drm/i915/display/intel_display_types.h | 2 + > .../drm/i915/display/intel_dp_link_training.c | 20 +++++++- > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/i915_reg.h | 2 + > 5 files changed, 69 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 236f3762b6f9..57174a111976 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 } > +}; > + > static const struct ddi_buf_trans * > bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > { > @@ -2301,14 +2305,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); > } > > +/* > + * If supported return HOBL vswing table and set registers to enable HOBL > + * otherwise returns NULL and unset registers to enable HOBL. > + */ > +static const struct cnl_ddi_buf_trans * > +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv, > + struct intel_encoder *encoder, int type, int rate, > + u32 level, int *n_entries) > +{ > + const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; > + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > + struct intel_dp *intel_dp; > + > + if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP) > + return NULL; Not a real fan of the "hobl" name. It just sounds like nonsense. Also bspec doesn't use that term at all. It only appears in the vbt spec. Not sure if there's a better one though. > + > + intel_dp = enc_to_intel_dp(encoder); > + if (!intel_dp->try_hobl || rate > 540000) { > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0); I would vote for just doing this programming unconditionally in the normal sequence. > + return NULL; > + } > + > + drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy)); > + drm_WARN_ON_ONCE(&dev_priv->drm, level > 0); > + > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en); > + /* Same table applies to TGL, RKL and DG1 */ > + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); > + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; > +} > + > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > - u32 level, enum phy phy, int type, > - int rate) > + struct intel_encoder *encoder, > + u32 level, enum phy phy, int type, > + int rate) If we're passing in the encoder then a bunch of this other stuff is redundant. > { > const struct cnl_ddi_buf_trans *ddi_translations = NULL; > u32 n_entries, val; > int ln; > > + ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type, > + rate, level, &n_entries); > + if (ddi_translations) > + goto hobl_found; Why not just put it into tgl_get_combo_buf_trans(). Hmm. I guess to not upset .voltage_max(). This feels a bit hackish, but I don't have better ideas for now. > + > if (INTEL_GEN(dev_priv) >= 12) > ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, > &n_entries); > @@ -2321,6 +2362,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > if (!ddi_translations) > return; > > +hobl_found: > if (level >= n_entries) { > drm_dbg_kms(&dev_priv->drm, > "DDI translation not found for level %d. Using %d instead.", > @@ -2428,7 +2470,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); > > /* 5. Program swing and de-emphasis */ > - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); > + icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate); > > /* 6. Set training enable to trigger update */ > val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 4b0aaa3081c9..f8943b67819d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1375,6 +1375,8 @@ struct intel_dp { > > /* Display stream compression testing */ > bool force_dsc_en; > + > + bool try_hobl; > }; > > enum lspcon_vendor { > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index b9e4ee2dbddc..88f366bb28d7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -52,12 +52,24 @@ static u8 dp_voltage_max(u8 preemph) > void intel_dp_get_adjust_train(struct intel_dp *intel_dp, > const u8 link_status[DP_LINK_STATUS_SIZE]) > { > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > u8 v = 0; > u8 p = 0; > int lane; > u8 voltage_max; > u8 preemph_max; > > + if (intel_dp->try_hobl) { > + /* > + * Do not adjust, try now with the regular table using VSwing 0 > + * and pre-emp 0 > + */ What if the sink is still asking for vswing 0 + preemph 0? The spec is rather ambiguous when it comes to this stuff. The table also doesn't specify the vswing/preemph for which we should use this optimized value. Your interpretation of 0+0 seems like the most sensible thing, but given that the VBT can also specifiy the fast link training vswing/preemph as something else (and maybe there was also something like this for normal link training?) I'm not 100% sure. Hmm. Actually noticed that all the eDP tables are missing the vswing/preemph levels (they do have the raw mV/dB values but not the DP spec levels). I filed a few issues in the hopes of clarification. > + intel_dp->try_hobl = false; > + drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link " > + "training, switching back to regular table\n"); > + return; > + } > + > for (lane = 0; lane < intel_dp->lane_count; lane++) { > v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); > p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); > @@ -103,9 +115,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, > } > > static bool > -intel_dp_reset_link_train(struct intel_dp *intel_dp, > - u8 dp_train_pat) > +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) > { > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + > + if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) > + intel_dp->try_hobl = true; If it failed once does it make sense to keep trying to use it? > + > memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); > intel_dp_set_signal_levels(intel_dp); > return intel_dp_set_link_train(intel_dp, dp_train_pat); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 2336c9231eef..c7e7df17eef2 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1687,6 +1687,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define INTEL_DISPLAY_ENABLED(dev_priv) \ > (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) > > +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12) > + > static inline bool intel_vtd_active(void) > { > #ifdef CONFIG_INTEL_IOMMU > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 578cfe11cbb9..d4611171f075 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define PWR_DOWN_LN_3_1_0 (0xb << 4) > #define PWR_DOWN_LN_MASK (0xf << 4) > #define PWR_DOWN_LN_SHIFT 4 > +#define EDP4K2K_MODE_OVRD_EN (1 << 3) > +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) > > #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) > #define ICL_LANE_ENABLE_AUX (1 << 0) > -- > 2.27.0 -- Ville Syrj?l? Intel From jose.souza at intel.com Wed Jun 3 20:55:59 2020 From: jose.souza at intel.com (Souza, Jose) Date: Wed, 3 Jun 2020 20:55:59 +0000 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915/display: Implement HOBL In-Reply-To: <20200603203346.GQ6112@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> <20200603194308.78622-2-jose.souza@intel.com> <20200603203346.GQ6112@intel.com> Message-ID: <57dcd40d816546b4aad57feeb73131817a8419fd.camel@intel.com> On Wed, 2020-06-03 at 23:33 +0300, Ville Syrj?l? wrote: > On Wed, Jun 03, 2020 at 12:43:07PM -0700, Jos? Roberto de Souza wrote: > > Hours Of Battery Life is a new GEN12+ power-saving feature that allows > > supported motherboards to use a special voltage swing table for eDP > > panels that uses less power. > > > > So here if supported by HW, OEM will set it in VBT and i915 will try > > to train link with HOBL vswing table if link training fails it fall > > back to the original table. > > > > Just not sure if DP compliance should also use this new voltage swing > > table too, cced some folks that worked in DP compliance. > > > > BSpec: 49291 > > BSpec: 49399 > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Animesh Manna <animesh.manna at intel.com> > > Cc: Manasi Navare <manasi.d.navare at intel.com> > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++-- > > .../drm/i915/display/intel_display_types.h | 2 + > > .../drm/i915/display/intel_dp_link_training.c | 20 +++++++- > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > drivers/gpu/drm/i915/i915_reg.h | 2 + > > 5 files changed, 69 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 236f3762b6f9..57174a111976 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > > }; > > > > +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 } > > +}; > > + > > static const struct ddi_buf_trans * > > bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > > { > > @@ -2301,14 +2305,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > > intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); > > } > > > > +/* > > + * If supported return HOBL vswing table and set registers to enable HOBL > > + * otherwise returns NULL and unset registers to enable HOBL. > > + */ > > +static const struct cnl_ddi_buf_trans * > > +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv, > > + struct intel_encoder *encoder, int type, int rate, > > + u32 level, int *n_entries) > > +{ > > + const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; > > + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > + struct intel_dp *intel_dp; > > + > > + if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP) > > + return NULL; > > Not a real fan of the "hobl" name. It just sounds like nonsense. Also > bspec doesn't use that term at all. It only appears in the vbt spec. > Not sure if there's a better one though. Maybe power_optimized_edp? > > > + > > + intel_dp = enc_to_intel_dp(encoder); > > + if (!intel_dp->try_hobl || rate > 540000) { > > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0); > > I would vote for just doing this programming unconditionally in the normal > sequence. Thought about that but intel_combo_phy_power_up_lanes() that program this ICL_PORT_CL_DW10 is called right after tgl_ddi_vswing_sequence(). > > > + return NULL; > > + } > > + > > + drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy)); > > + drm_WARN_ON_ONCE(&dev_priv->drm, level > 0); > > + > > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en); > > + /* Same table applies to TGL, RKL and DG1 */ > > + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); > > + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; > > +} > > + > > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > > - u32 level, enum phy phy, int type, > > - int rate) > > + struct intel_encoder *encoder, > > + u32 level, enum phy phy, int type, > > + int rate) > > If we're passing in the encoder then a bunch of this other stuff is > redundant. Okay > > > { > > const struct cnl_ddi_buf_trans *ddi_translations = NULL; > > u32 n_entries, val; > > int ln; > > > > + ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type, > > + rate, level, &n_entries); > > + if (ddi_translations) > > + goto hobl_found; > > Why not just put it into tgl_get_combo_buf_trans(). Hmm. I guess to not > upset .voltage_max(). This feels a bit hackish, but I don't have better > ideas for now. Exactly. > > > + > > if (INTEL_GEN(dev_priv) >= 12) > > ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, > > &n_entries); > > @@ -2321,6 +2362,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > > if (!ddi_translations) > > return; > > > > +hobl_found: > > if (level >= n_entries) { > > drm_dbg_kms(&dev_priv->drm, > > "DDI translation not found for level %d. Using %d instead.", > > @@ -2428,7 +2470,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); > > > > /* 5. Program swing and de-emphasis */ > > - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); > > + icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate); > > > > /* 6. Set training enable to trigger update */ > > val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 4b0aaa3081c9..f8943b67819d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1375,6 +1375,8 @@ struct intel_dp { > > > > /* Display stream compression testing */ > > bool force_dsc_en; > > + > > + bool try_hobl; > > }; > > > > enum lspcon_vendor { > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > index b9e4ee2dbddc..88f366bb28d7 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > @@ -52,12 +52,24 @@ static u8 dp_voltage_max(u8 preemph) > > void intel_dp_get_adjust_train(struct intel_dp *intel_dp, > > const u8 link_status[DP_LINK_STATUS_SIZE]) > > { > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > u8 v = 0; > > u8 p = 0; > > int lane; > > u8 voltage_max; > > u8 preemph_max; > > > > + if (intel_dp->try_hobl) { > > + /* > > + * Do not adjust, try now with the regular table using VSwing 0 > > + * and pre-emp 0 > > + */ > > What if the sink is still asking for vswing 0 + preemph 0? The spec is > rather ambiguous when it comes to this stuff. As it will fallback to regular table vswing 0 + preemph 0 that is not a issue. > > The table also doesn't specify the vswing/preemph for which we should > use this optimized value. Your interpretation of 0+0 seems like the most > sensible thing, but given that the VBT can also specifiy the fast link > training vswing/preemph as something else (and maybe there was also > something like this for normal link training?) I'm not 100% sure. Yeah don't make much sense it not be vswing 0 + preemph 0 but lets wait for BSpec clarification then. > > Hmm. Actually noticed that all the eDP tables are missing the > vswing/preemph levels (they do have the raw mV/dB values but not the > DP spec levels). I filed a few issues in the hopes of clarification. > > > + intel_dp->try_hobl = false; > > + drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link " > > + "training, switching back to regular table\n"); > > + return; > > + } > > + > > for (lane = 0; lane < intel_dp->lane_count; lane++) { > > v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); > > p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); > > @@ -103,9 +115,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, > > } > > > > static bool > > -intel_dp_reset_link_train(struct intel_dp *intel_dp, > > - u8 dp_train_pat) > > +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) > > { > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > + > > + if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) > > + intel_dp->try_hobl = true; > > If it failed once does it make sense to keep trying to use it? It could pass in a different bit rate and would be to much complicated keep track of that. Thanks for the review, lets wait for the BSpec clarifications that you asked. > > > + > > memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); > > intel_dp_set_signal_levels(intel_dp); > > return intel_dp_set_link_train(intel_dp, dp_train_pat); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 2336c9231eef..c7e7df17eef2 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1687,6 +1687,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define INTEL_DISPLAY_ENABLED(dev_priv) \ > > (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) > > > > +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12) > > + > > static inline bool intel_vtd_active(void) > > { > > #ifdef CONFIG_INTEL_IOMMU > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 578cfe11cbb9..d4611171f075 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define PWR_DOWN_LN_3_1_0 (0xb << 4) > > #define PWR_DOWN_LN_MASK (0xf << 4) > > #define PWR_DOWN_LN_SHIFT 4 > > +#define EDP4K2K_MODE_OVRD_EN (1 << 3) > > +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) > > > > #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) > > #define ICL_LANE_ENABLE_AUX (1 << 0) > > -- > > 2.27.0 From imre.deak at intel.com Wed Jun 3 21:10:38 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 00:10:38 +0300 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/dp_mst: Fix disabling MST on a port Message-ID: <20200603211040.8190-1-imre.deak@intel.com> Currently MST on a port can get enabled/disabled from the hotplug work and get disabled from the short pulse work in a racy way. Fix this by relying on the MST state checking in the hotplug work and just schedule a hotplug work from the short pulse handler if some problem happened during the MST interrupt handling. This removes the explicit MST disabling in case of an AUX failure, but if AUX fails, then probably the detection will also fail during the scheduled hotplug work and it's not guaranteed that we'll see intermittent errors anyway. While at it also simplify the error checking of the MST interrupt handler. Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 33 +++---------------------- 1 file changed, 4 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 55fda074c0ad..befbcacddaa1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5604,7 +5604,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) } } - return need_retrain; + return need_retrain ? -EINVAL : 0; } static bool @@ -7255,35 +7255,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) } if (intel_dp->is_mst) { - switch (intel_dp_check_mst_status(intel_dp)) { - case -EINVAL: - /* - * If we were in MST mode, and device is not - * there, get out of MST mode - */ - drm_dbg_kms(&i915->drm, - "MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, - intel_dp->mst_mgr.mst_state); - intel_dp->is_mst = false; - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, - intel_dp->is_mst); - - return IRQ_NONE; - case 1: - return IRQ_NONE; - default: - break; - } - } - - if (!intel_dp->is_mst) { - bool handled; - - handled = intel_dp_short_pulse(intel_dp); - - if (!handled) + if (intel_dp_check_mst_status(intel_dp) < 0) return IRQ_NONE; + } else if (!intel_dp_short_pulse(intel_dp)) { + return IRQ_NONE; } return IRQ_HANDLED; -- 2.23.1 From imre.deak at intel.com Wed Jun 3 21:10:39 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 00:10:39 +0300 Subject: [Intel-gfx] [PATCH 2/3] drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <20200603211040.8190-2-imre.deak@intel.com> Make the locking look symmetric with the unlocking. Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 1bdf3cfeeebb..5bc72e800b85 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1183,7 +1183,7 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, ret = wait_event_timeout(mgr->tx_waitq, check_txmsg_state(mgr, txmsg), (4 * HZ)); - mutex_lock(&mstb->mgr->qlock); + mutex_lock(&mgr->qlock); if (ret > 0) { if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { ret = -EIO; -- 2.23.1 From imre.deak at intel.com Wed Jun 3 21:10:40 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 00:10:40 +0300 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <20200603211040.8190-3-imre.deak@intel.com> Some TypeC -> native DP adapters, at least the Club CAC-1557 adapter, incorrectly filter out HPD short pulses with a duration less than ~540 usec, leading to MST probe failures. According to the DP alt mode specification adapters should forward short pulses with a duration greater than 250 usec. According to the DP specificatin DP sources should detect short pulses in the 500 usec -> 2 ms range. Based on this filtering out short pulses with a duration less than 540 usec is incorrect. To make such adapters work add support for a driver polling on MST inerrupt flags, and wire this up in the i915 driver. The sink can clear an interrupt it raised after 110 ms if the source doesn't respond, so use a 50 ms poll period to avoid missing an interrupt. Polling of the MST interrupt flags is explicitly allowed by the DP specification. This fixes MST probe failures I saw using this adapter and a DELL U2515H monitor. Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 18 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 +++++++++++++++ include/drm/drm_dp_mst_helper.h | 1 + 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 5bc72e800b85..d1bf340a95a8 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1178,11 +1178,23 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, struct drm_dp_sideband_msg_tx *txmsg) { struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; + unsigned long wait_expires = jiffies + msecs_to_jiffies(4000); int ret; - ret = wait_event_timeout(mgr->tx_waitq, - check_txmsg_state(mgr, txmsg), - (4 * HZ)); + for (;;) { + ret = wait_event_timeout(mgr->tx_waitq, + check_txmsg_state(mgr, txmsg), + mgr->cbs->update_hpd_irq_state ? + msecs_to_jiffies(50) : + wait_expires); + + if (ret || !mgr->cbs->update_hpd_irq_state || + time_after(jiffies, wait_expires)) + break; + + mgr->cbs->update_hpd_irq_state(mgr); + } + mutex_lock(&mgr->qlock); if (ret > 0) { if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d18b406f2a7d..1ff7d0096262 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -765,8 +765,23 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo return NULL; } +static void +intel_dp_mst_update_hpd_irq_state(struct drm_dp_mst_topology_mgr *mgr) +{ + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + spin_lock_irq(&i915->irq_lock); + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); + spin_unlock_irq(&i915->irq_lock); + + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); +} + static const struct drm_dp_mst_topology_cbs mst_cbs = { .add_connector = intel_dp_add_mst_connector, + .update_hpd_irq_state = intel_dp_mst_update_hpd_irq_state, }; static struct intel_dp_mst_encoder * diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 9e1ffcd7cb68..c902f4380200 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -475,6 +475,7 @@ struct drm_dp_mst_topology_mgr; struct drm_dp_mst_topology_cbs { /* create a connector for a port */ struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); + void (*update_hpd_irq_state)(struct drm_dp_mst_topology_mgr *mgr); }; #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) -- 2.23.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:14 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:14 -0700 Subject: [Intel-gfx] [PATCH v3 00/15] Remaining RKL patches Message-ID: <20200603211529.3005059-1-matthew.d.roper@intel.com> I got pulled away by another task for a few weeks and had to put the RKL upstreaming on hold, so these remaining patches needed a bit of additional rebasing on top of other changes that have landed in the meantime, but there weren't any serious conflicts. The functional changes from the last series are relatively small: - Additional patch to only program ABOX_CTL on RKL and not the extra ABOX{1,2}_CTL registers that TGL added. The bspec documentation here isn't fully updated yet, but we've confirmed experimentatlly that RKL doesn't have the additional register instances. - We now setup the transcoder mask properly in the device_info and use for_each_cpu_transcoder_masked() for our loops. A couple of the patches included here already have r-b's, but since it's been a while since they were originally posted it's probably worth getting another CI run before applying them. Aditya Swarup (1): drm/i915/rkl: Don't try to read out DSI transcoders Jos? Roberto de Souza (1): drm/i915/rkl: Disable PSR2 Lucas De Marchi (1): drm/i915/rkl: provide port/phy mapping for vbt Matt Roper (12): drm/i915/rkl: Set transcoder mask properly drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1,2} drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout drm/i915/rkl: Setup ports/phys drm/i915/rkl: Update TGP's pin mapping when paired with RKL drm/i915/rkl: Add DDC pin mapping drm/i915/rkl: Don't try to access transcoder D drm/i915/rkl: Handle comp master/slave relationships for PHYs drm/i915/rkl: Add DPLL4 support drm/i915/rkl: Handle HTI drm/i915/rkl: Add initial workarounds drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++----- .../gpu/drm/i915/display/intel_combo_phy.c | 25 +++++- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++- drivers/gpu/drm/i915/display/intel_display.c | 82 ++++++++++++----- .../drm/i915/display/intel_display_power.c | 46 +++++----- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++++++- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 22 ++++- drivers/gpu/drm/i915/display/intel_psr.c | 15 ++++ drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++++++++++++------- drivers/gpu/drm/i915/i915_drv.h | 5 ++ drivers/gpu/drm/i915/i915_irq.c | 23 ++++- drivers/gpu/drm/i915/i915_pci.c | 5 ++ drivers/gpu/drm/i915/i915_reg.h | 30 +++++-- drivers/gpu/drm/i915/intel_device_info.h | 1 + 16 files changed, 372 insertions(+), 116 deletions(-) -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:15 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:15 -0700 Subject: [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-2-matthew.d.roper@intel.com> Although we properly captured RKL's three pipes in the device info structure, we forgot to make the corresponding update to the transcoder mask. Set this field so that our transcoder loops will operate properly. Fixes: 123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids") Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 07b09af3a9c3..0ed586ee2047 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -881,6 +881,8 @@ static const struct intel_device_info rkl_info = { GEN12_FEATURES, PLATFORM(INTEL_ROCKETLAKE), .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ + BIT(TRANSCODER_C), .require_force_probe = 1, .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:16 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:16 -0700 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-3-matthew.d.roper@intel.com> RKL uses the same BW_BUDDY programming table as TGL, but programs the values into a single set BUDDY0 set of registers rather than the BUDDY1/BUDDY2 sets used by TGL. Bspec: 49218 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- .../drm/i915/display/intel_display_power.c | 44 +++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 14 ++++-- 2 files changed, 35 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 72312b67b57a..2c1ce50b572b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) enum intel_dram_type type = dev_priv->dram_info.type; u8 num_channels = dev_priv->dram_info.num_channels; const struct buddy_page_mask *table; - int i; + int config, min_buddy, max_buddy, i; if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) /* Wa_1409767108: tgl */ @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) else table = tgl_buddy_page_masks; - for (i = 0; table[i].page_mask != 0; i++) - if (table[i].num_channels == num_channels && - table[i].type == type) + if (IS_ROCKETLAKE(dev_priv)) { + min_buddy = max_buddy = 0; + } else { + min_buddy = 1; + max_buddy = 2; + } + + for (config = 0; table[config].page_mask != 0; config++) + if (table[config].num_channels == num_channels && + table[config].type == type) break; - if (table[i].page_mask == 0) { + if (table[config].page_mask == 0) { drm_dbg(&dev_priv->drm, "Unknown memory configuration; disabling address buddy logic.\n"); - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); + for (i = min_buddy; i <= max_buddy; i++) + intel_de_write(dev_priv, BW_BUDDY_CTL(i), + BW_BUDDY_DISABLE); } else { - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, - table[i].page_mask); - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, - table[i].page_mask); - - /* Wa_22010178259:tgl */ - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, - BW_BUDDY_TLB_REQ_TIMER_MASK, - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, - BW_BUDDY_TLB_REQ_TIMER_MASK, - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); + for (i = min_buddy; i <= max_buddy; i++) { + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), + table[config].page_mask); + + /* Wa_22010178259:tgl,rkl */ + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), + BW_BUDDY_TLB_REQ_TIMER_MASK, + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, + 0x8)); + } } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 578cfe11cbb9..3e79cefc510a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7837,13 +7837,19 @@ enum { #define WAIT_FOR_PCH_RESET_ACK (1 << 1) #define WAIT_FOR_PCH_FLR_ACK (1 << 0) -#define BW_BUDDY1_CTL _MMIO(0x45140) -#define BW_BUDDY2_CTL _MMIO(0x45150) +#define _BW_BUDDY0_CTL 0x45130 +#define _BW_BUDDY1_CTL 0x45140 +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_CTL, \ + _BW_BUDDY1_CTL)) #define BW_BUDDY_DISABLE REG_BIT(31) #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) +#define _BW_BUDDY0_PAGE_MASK 0x45134 +#define _BW_BUDDY1_PAGE_MASK 0x45144 +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_PAGE_MASK, \ + _BW_BUDDY1_PAGE_MASK)) #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:17 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:17 -0700 Subject: [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-4-matthew.d.roper@intel.com> Although RKL is a gen12 platform, it doesn't have the two extra instances of the ABOX control register; we should only program the single MBUS_ABOX_CTL on this platform. Bspec: 50096 Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 2c1ce50b572b..37847b3d733c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4772,7 +4772,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) MBUS_ABOX_BW_CREDIT(1); intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val); - if (INTEL_GEN(dev_priv) >= 12) { + if (INTEL_GEN(dev_priv) >= 12 && !IS_ROCKETLAKE(dev_priv)) { intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val); intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val); } -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:18 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:18 -0700 Subject: [Intel-gfx] [PATCH v3 04/15] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-5-matthew.d.roper@intel.com> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. v2: - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 - Checkpatch style fixes Bspec: 50287 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 236f3762b6f9..6752f63d1686 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2736,7 +2736,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, enum phy phy) { - if (intel_phy_is_combo(dev_priv, phy)) { + if (IS_ROCKETLAKE(dev_priv)) { + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + } else if (intel_phy_is_combo(dev_priv, phy)) { return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } else if (intel_phy_is_tc(dev_priv, phy)) { enum tc_port tc_port = intel_port_to_tc(dev_priv, @@ -2763,6 +2765,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { + u32 mask, sel; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } + /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -2773,8 +2785,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + val &= ~mask; + val |= sel; intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a9f752d26b4e..b4f8c88c779f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10782,9 +10782,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + u32 mask, shift; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } + + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; + id = temp >> shift; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3e79cefc510a..db031269a05a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10173,12 +10173,18 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ (tc_port) + 12 : \ (tc_port) - PORT_TC4 + 21)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) /* CNL PLL */ #define DPLL0_ENABLE 0x46010 -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:22 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:22 -0700 Subject: [Intel-gfx] [PATCH v3 08/15] drm/i915/rkl: Add DDC pin mapping In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-9-matthew.d.roper@intel.com> The pin mapping for the final two outputs varies according to which PCH is present on the platform: with TGP the pins are remapped into the TC range, whereas with CMP they stay in the traditional combo output range. Bspec: 49181 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com> --- drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 010f37240710..a31a98d26882 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3082,6 +3082,24 @@ static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return ddc_pin; } +static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + enum phy phy = intel_port_to_phy(dev_priv, port); + + WARN_ON(port == PORT_C); + + /* + * Pin mapping for RKL depends on which PCH is present. With TGP, the + * final two outputs use type-c pins, even though they're actually + * combo outputs. With CMP, the traditional DDI A-D pins are used for + * all outputs. + */ + if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) + return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; + + return GMBUS_PIN_1_BXT + phy; +} + static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { @@ -3119,7 +3137,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) return ddc_pin; } - if (HAS_PCH_MCC(dev_priv)) + if (IS_ROCKETLAKE(dev_priv)) + ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); + else if (HAS_PCH_MCC(dev_priv)) ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) ddc_pin = icl_port_to_ddc_pin(dev_priv, port); -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:21 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:21 -0700 Subject: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-8-matthew.d.roper@intel.com> When TGP is paired with RKL it uses a different HPD pin mapping than when paired with TGL. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 490574669eaa..f3ea81a17352 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), }; +/* + * TGP when paired with RKL has different pin mappings than when paired + * with TGL. + */ +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = { + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), + [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1), + [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2), +}; + static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) { struct i915_hotplug *hpd = &dev_priv->hotplug; @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) return; - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) + if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv)) + hpd->pch_hpd = hpd_rkl_tgp; + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) hpd->pch_hpd = hpd_tgp; else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) hpd->pch_hpd = hpd_icp; -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:20 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:20 -0700 Subject: [Intel-gfx] [PATCH v3 06/15] drm/i915/rkl: provide port/phy mapping for vbt In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-7-matthew.d.roper@intel.com> From: Lucas De Marchi <lucas.demarchi at intel.com> RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of view, so all DDI/pipe/transcoder register use these indexes to refer to them. Combo phy and IO functions follow another namespace that we keep as "enum phy". The VBT in theory would use the DE point of view, but that does not happen in practice. Provide a table to convert the child devices to the "correct" port numbering we use. Now this is the output we get while reading the VBT: DDIA: [drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT) [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:275:DDI A] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT) DDIB: [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default) [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:291:DDI B] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT) DDI USBC1: [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT) [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:295:DDI D] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT) DDI USBC2: [drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT) [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:306:DDI E] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT) Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++++++++------- 1 file changed, 51 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 839124647202..4f1a72a90b8f 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) return 0; } -static enum port dvo_port_to_port(u8 dvo_port) +static enum port __dvo_port_to_port(int n_ports, int n_dvo, + const int port_mapping[][3], u8 dvo_port) { - /* - * Each DDI port can have more than one value on the "DVO Port" field, - * so look for all the possible values for each port. - */ - static const int dvo_ports[][3] = { - [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1}, - [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1}, - [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1}, - [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1}, - [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE}, - [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1}, - [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1}, - }; enum port port; int i; - for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) { - for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) { - if (dvo_ports[port][i] == -1) + for (port = PORT_A; port < n_ports; port++) { + for (i = 0; i < n_dvo; i++) { + if (port_mapping[port][i] == -1) break; - if (dvo_port == dvo_ports[port][i]) + if (dvo_port == port_mapping[port][i]) return port; } } @@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port) return PORT_NONE; } +static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, + u8 dvo_port) +{ + /* + * Each DDI port can have more than one value on the "DVO Port" field, + * so look for all the possible values for each port. + */ + static const int port_mapping[][3] = { + [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, + [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, + [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, + [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, + [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 }, + [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, + [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, + }; + /* + * Bspec lists the ports as A, B, C, D - however internally in our + * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the + * registers in Display Engine match the right offsets. Apply the + * mapping here to translate from VBT to internal convention. + */ + static const int rkl_port_mapping[][3] = { + [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, + [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, + [PORT_C] = { -1 }, + [PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, + [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, + }; + + if (IS_ROCKETLAKE(dev_priv)) + return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), + ARRAY_SIZE(rkl_port_mapping[0]), + rkl_port_mapping, + dvo_port); + else + return __dvo_port_to_port(ARRAY_SIZE(port_mapping), + ARRAY_SIZE(port_mapping[0]), + port_mapping, + dvo_port); +} + static void parse_ddi_port(struct drm_i915_private *dev_priv, struct display_device_data *devdata, u8 bdb_version) @@ -1659,7 +1689,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; enum port port; - port = dvo_port_to_port(child->dvo_port); + port = dvo_port_to_port(dev_priv, child->dvo_port); if (port == PORT_NONE) return; @@ -2603,10 +2633,10 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, aux_ch = AUX_CH_B; break; case DP_AUX_C: - aux_ch = AUX_CH_C; + aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C; break; case DP_AUX_D: - aux_ch = AUX_CH_D; + aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D; break; case DP_AUX_E: aux_ch = AUX_CH_E; -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:23 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:23 -0700 Subject: [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-10-matthew.d.roper@intel.com> There are a couple places in our driver that loop over transcoders A..D for gen11+; since RKL only has three pipes/transcoders, this can lead to unclaimed register reads/writes. We should add checks for transcoder existence where appropriate. v2: Move one transcoder check that wound up in the wrong function after conflict resolution. It belongs in bdw_get_trans_port_sync_config rather than bxt_get_dsi_transcoder_state. v3: Switch loops to use for_each_cpu_transcoder_masked() since this iterator already checks the platform's transcoder mask for us. (Ville) Cc: Aditya Swarup <aditya.swarup at intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f3ea81a17352..40a71c4a1ef5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2885,13 +2885,15 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; enum pipe pipe; + u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | + BIT(TRANSCODER_C) | BIT(TRANSCODER_D); intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); if (INTEL_GEN(dev_priv) >= 12) { enum transcoder trans; - for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) { + for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { enum intel_display_power_domain domain; domain = POWER_DOMAIN_TRANSCODER(trans); @@ -3413,6 +3415,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; u32 de_misc_masked = GEN8_DE_EDP_PSR; + u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | + BIT(TRANSCODER_C) | BIT(TRANSCODER_D); enum pipe pipe; if (INTEL_GEN(dev_priv) <= 10) @@ -3433,7 +3437,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 12) { enum transcoder trans; - for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) { + for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { enum intel_display_power_domain domain; domain = POWER_DOMAIN_TRANSCODER(trans); -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:19 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:19 -0700 Subject: [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-6-matthew.d.roper@intel.com> RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D. Bspec: 49181 Cc: Imre Deak <imre.deak at intel.com> Cc: Aditya Swarup <aditya.swarup at intel.com> Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 4 ++- 2 files changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b4f8c88c779f..019fef8023ca 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7218,30 +7218,33 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { if (phy == PHY_NONE) return false; - - if (IS_ELKHARTLAKE(dev_priv)) + else if (IS_ROCKETLAKE(dev_priv)) + return phy <= PHY_D; + else if (IS_ELKHARTLAKE(dev_priv)) return phy <= PHY_C; - - if (INTEL_GEN(dev_priv) >= 11) + else if (INTEL_GEN(dev_priv) >= 11) return phy <= PHY_B; - - return false; + else + return false; } bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { - if (INTEL_GEN(dev_priv) >= 12) + if (IS_ROCKETLAKE(dev_priv)) + return false; + else if (INTEL_GEN(dev_priv) >= 12) return phy >= PHY_D && phy <= PHY_I; - - if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) + else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) return phy >= PHY_C && phy <= PHY_F; - - return false; + else + return false; } enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) { - if (IS_ELKHARTLAKE(i915) && port == PORT_D) + if (IS_ROCKETLAKE(i915) && port >= PORT_D) + return (enum phy)port - 1; + else if (IS_ELKHARTLAKE(i915) && port == PORT_D) return PHY_A; return (enum phy)port; @@ -16829,7 +16832,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) return; - if (INTEL_GEN(dev_priv) >= 12) { + if (IS_ROCKETLAKE(dev_priv)) { + intel_ddi_init(dev_priv, PORT_A); + intel_ddi_init(dev_priv, PORT_B); + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); intel_ddi_init(dev_priv, PORT_D); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index db031269a05a..85137d268c4a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _ICL_COMBOPHY_A 0x162000 #define _ICL_COMBOPHY_B 0x6C000 #define _EHL_COMBOPHY_C 0x160000 +#define _RKL_COMBOPHY_D 0x161000 #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ _ICL_COMBOPHY_B, \ - _EHL_COMBOPHY_C) + _EHL_COMBOPHY_C, \ + _RKL_COMBOPHY_D) /* CNL/ICL Port CL_DW registers */ #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:26 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:26 -0700 Subject: [Intel-gfx] [PATCH v3 12/15] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-13-matthew.d.roper@intel.com> Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were DPLL2, so no extra offset handling is needed either. v2: - Add new .update_ref_clks() hook. Bspec: 49202 Bspec: 49443 Bspec: 50288 Bspec: 50289 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b45185b80bec..b5f4d4cef682 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, return false; } - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) + if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - else + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { + dpll_mask = + BIT(DPLL_ID_EHL_DPLL4) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else { dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); + } port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info rkl_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, + { }, +}; + +static const struct intel_dpll_mgr rkl_pll_mgr = { + .dpll_info = rkl_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (INTEL_GEN(dev_priv) >= 12) + if (IS_ROCKETLAKE(dev_priv)) + dpll_mgr = &rkl_pll_mgr; + else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr; else if (IS_ELKHARTLAKE(dev_priv)) dpll_mgr = &ehl_pll_mgr; -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:27 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:27 -0700 Subject: [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-14-matthew.d.roper@intel.com> If HTI (also sometimes called HDPORT) is enabled at startup, it may be using some of the PHYs and DPLLs making them unavailable for general usage. Let's read out the HDPORT_STATE register and avoid making use of resources that HTI is already using. v2: - Fix minor checkpatch warnings Bspec: 49189 Bspec: 53707 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++ 5 files changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bcc6dc4e321b..cdd84a419cf7 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -46,6 +46,7 @@ #include "display/intel_ddi.h" #include "display/intel_dp.h" #include "display/intel_dp_mst.h" +#include "display/intel_dpll_mgr.h" #include "display/intel_dsi.h" #include "display/intel_dvo.h" #include "display/intel_gmbus.h" @@ -16817,6 +16818,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } +static bool hti_uses_phy(u32 hdport_state, enum phy phy) +{ + return hdport_state & HDPORT_ENABLED && + (hdport_state & HDPORT_PHY_USED_DP(phy) || + hdport_state & HDPORT_PHY_USED_HDMI(phy)); +} + static void intel_setup_outputs(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; @@ -16828,10 +16836,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_ROCKETLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + /* + * If HTI (aka HDPORT) is enabled at boot, it may have taken + * over some of the PHYs and made them unavailable to the + * driver. In that case we should skip initializing the + * corresponding outputs. + */ + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + + if (!hti_uses_phy(hdport_state, PHY_A)) + intel_ddi_init(dev_priv, PORT_A); + if (!hti_uses_phy(hdport_state, PHY_B)) + intel_ddi_init(dev_priv, PORT_B); + if (!hti_uses_phy(hdport_state, PHY_C)) + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + if (!hti_uses_phy(hdport_state, PHY_D)) + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); @@ -18379,6 +18399,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) intel_dpll_readout_hw_state(dev_priv); + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); + for_each_intel_encoder(dev, encoder) { pipe = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b5f4d4cef682..6f59f9ec453b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) mutex_unlock(&dev_priv->dpll.lock); } +/* + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them + * unavailable for use. + */ +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) +{ + u32 hdport_state; + + if (!IS_ROCKETLAKE(dev_priv)) + return 0; + + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + if (!(hdport_state & HDPORT_ENABLED)) + return 0; + + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); +} + static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + /* Eliminate DPLLs from consideration if reserved by HTI */ + dpll_mask &= ~dev_priv->hti_pll_mask; + for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { pll = &dev_priv->dpll.shared_dplls[i]; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 5d9a2bc371e7..ac2238646fe7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device *dev); void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e99255e17eb7..668b3c9cf3ae 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1037,6 +1037,9 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ + u32 hti_pll_mask; + /* * edram size in MB. * Cannot be determined by PCIID. You must always read a register. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 85137d268c4a..b9faf0f978cf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2906,6 +2906,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) +#define HDPORT_STATE _MMIO(0x45050) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*(phy) + 2) +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2*(phy) + 1) +#define HDPORT_ENABLED REG_BIT(0) + /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:29 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:29 -0700 Subject: [Intel-gfx] [PATCH v3 15/15] drm/i915/rkl: Add initial workarounds In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-16-matthew.d.roper@intel.com> RKL and TGL share some general gen12 workarounds, but each platform also has its own platform-specific workarounds. Cc: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++-------- 2 files changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3cd461bf9131..63ac79f88fa2 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0] */ - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) + /* Wa_14010477008:tgl[a0..c0],rkl[all] */ + if (IS_ROCKETLAKE(dev_priv) || + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 30cd798b9664..d2f8e285491f 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -590,8 +590,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) { /* * Wa_1409142259:tgl @@ -601,12 +601,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1409207793:tgl * Wa_1409178076:tgl * Wa_1408979724:tgl + * Wa_14010443199:rkl + * Wa_14010698770:rkl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); + /* WaDisableGPGPUMidThreadPreemption:gen12 */ + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, + GEN9_PREEMPT_GPGPU_LEVEL_MASK, + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); +} + +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + /* - * Wa_1604555607:gen12 and Wa_1608008084:gen12 + * Wa_1604555607:tgl + * + * Note that the implementation of this workaround is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit * masks. So instead of doing a RMW we should just write the TDS timer @@ -614,11 +630,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, */ wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128, 0); - - /* WaDisableGPGPUMidThreadPreemption:tgl */ - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, - GEN9_PREEMPT_GPGPU_LEVEL_MASK, - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); } static void @@ -633,8 +644,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 12)) + gen12_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 11)) icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) @@ -946,9 +959,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen12_gt_workarounds_init(struct drm_i915_private *i915, + struct i915_wa_list *wal) { wa_init_mcr(i915, wal); +} + +static void +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) @@ -966,8 +986,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 12)) + gen12_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 11)) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) @@ -1385,18 +1407,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); - /* - * Wa_1607030317:tgl - * Wa_1607186500:tgl - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 - * of then says it is fixed on B0 the other one says it is - * permanent - */ - wa_masked_en(wal, - GEN6_RC_SLEEP_PSMI_CONTROL, - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE); - /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1415,24 +1425,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl */ + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); - /* Wa_1409804808:tgl */ + /* Wa_1409804808:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); - /* Wa_1606700617:tgl */ - wa_masked_en(wal, - GEN9_CS_DEBUG_MODE1, - FF_DOP_CLOCK_GATE_DISABLE); - /* * Wa_1409085225:tgl - * Wa_14010229206:tgl + * Wa_14010229206:tgl,rkl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); + + /* + * Wa_1607030317:tgl + * Wa_1607186500:tgl + * Wa_1607297627:tgl,rkl there are multiple entries for this + * WA in the BSpec; some indicate this is an A0-only WA, + * others indicate it applies to all steppings. + */ + wa_masked_en(wal, + GEN6_RC_SLEEP_PSMI_CONTROL, + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + } + + if (IS_TIGERLAKE(i915)) { + /* Wa_1606700617:tgl */ + wa_masked_en(wal, + GEN9_CS_DEBUG_MODE1, + FF_DOP_CLOCK_GATE_DISABLE); } if (IS_GEN(i915, 11)) { -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:24 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:24 -0700 Subject: [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-11-matthew.d.roper@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI transcoder registers. v2(MattR): - Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask against the platform's cpu_transcoder_mask to filter out the ones that don't exist on a given platform. (Ville) Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 019fef8023ca..bcc6dc4e321b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10904,19 +10904,13 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum intel_display_power_domain power_domain; - unsigned long panel_transcoder_mask = 0; + unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP) | + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); unsigned long enabled_panel_transcoders = 0; enum transcoder panel_transcoder; intel_wakeref_t wf; u32 tmp; - if (INTEL_GEN(dev_priv) >= 11) - panel_transcoder_mask |= - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); - - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP)) - panel_transcoder_mask |= BIT(TRANSCODER_EDP); - /* * The pipe->transcoder mapping is fixed with the exception of the eDP * and DSI transcoders handled below. @@ -10927,6 +10921,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, * XXX: Do intel_display_power_get_if_enabled before reading this (for * consistency and less surprising code; it's in always on power). */ + panel_transcoder_mask &= INTEL_INFO(dev_priv)->cpu_transcoder_mask; for_each_set_bit(panel_transcoder, &panel_transcoder_mask, ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) { -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:25 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:25 -0700 Subject: [Intel-gfx] [PATCH v3 11/15] drm/i915/rkl: Handle comp master/slave relationships for PHYs In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-12-matthew.d.roper@intel.com> Certain combo PHYs act as a compensation master to other PHYs and need to be initialized with a special irefgen bit in the PORT_COMP_DW8 register. Previously PHY A was the only compensation master (for PHYs B & C), but RKL adds a fourth PHY which is slaved to PHY C instead. Bspec: 49291 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 43d8784f6fa0..77b04bb3ec62 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -234,6 +234,27 @@ static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) return false; } +static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) +{ + /* + * Certain PHYs are connected to compensation resistors and act + * as masters to other PHYs. + * + * ICL,TGL: + * A(master) -> B(slave), C(slave) + * RKL: + * A(master) -> B(slave) + * C(master) -> D(slave) + * + * We must set the IREFGEN bit for any PHY acting as a master + * to another PHY. + */ + if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C) + return true; + + return phy == PHY_A; +} + static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, enum phy phy) { @@ -245,7 +266,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, ret = cnl_verify_procmon_ref_values(dev_priv, phy); - if (phy == PHY_A) { + if (phy_is_master(dev_priv, phy)) { ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), IREFGEN, IREFGEN); @@ -356,7 +377,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) skip_phy_misc: cnl_set_procmon_ref_values(dev_priv, phy); - if (phy == PHY_A) { + if (phy_is_master(dev_priv, phy)) { val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); val |= IREFGEN; intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 3 21:15:28 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 14:15:28 -0700 Subject: [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2 In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <20200603211529.3005059-15-matthew.d.roper@intel.com> From: Jos? Roberto de Souza <jose.souza at intel.com> RKL doesn't have PSR2 HW tracking, it was replaced by software/manual tracking. The driver is required to track the areas that needs update and program hardware to send selective updates. So until the software tracking is implemented, PSR2 needs to be disabled for platforms without PSR2 HW tracking. BSpec: 50422 BSpec: 50424 Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 3 +++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 4 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b7a2c102648a..714c590b39f5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -646,6 +646,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + /* + * Some platforms lack PSR2 HW tracking and instead require manual + * tracking by software. In this case, the driver is required to track + * the areas that need updates and program hardware to send selective + * updates. + * + * So until the software tracking is implemented, PSR2 needs to be + * disabled for platforms without PSR2 HW tracking. + */ + if (!HAS_PSR_HW_TRACKING(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, + "No PSR2 HW tracking in the platform\n"); + return false; + } + /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 668b3c9cf3ae..87f4000413f1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1644,6 +1644,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) +#define HAS_PSR_HW_TRACKING(dev_priv) \ + (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 0ed586ee2047..ef4a457a6c4f 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = { .display.has_ddi = 1, \ .has_fpga_dbg = 1, \ .display.has_psr = 1, \ + .display.has_psr_hw_tracking = 1, \ .display.has_dp_mst = 1, \ .has_rc6p = 0 /* RC6p removed-by HSW */, \ HSW_PIPE_OFFSETS, \ @@ -690,6 +691,7 @@ static const struct intel_device_info skl_gt4_info = { .display.has_fbc = 1, \ .display.has_hdcp = 1, \ .display.has_psr = 1, \ + .display.has_psr_hw_tracking = 1, \ .has_runtime_pm = 1, \ .display.has_csr = 1, \ .has_rc6 = 1, \ @@ -884,6 +886,7 @@ static const struct intel_device_info rkl_info = { .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C), .require_force_probe = 1, + .display.has_psr_hw_tracking = 0, .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), }; diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 3613c04904e0..34dbffd65bad 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -148,6 +148,7 @@ enum intel_ppgtt_type { func(has_modular_fia); \ func(has_overlay); \ func(has_psr); \ + func(has_psr_hw_tracking); \ func(overlay_needs_physical); \ func(supports_tv); -- 2.24.1 From jose.souza at intel.com Wed Jun 3 21:27:03 2020 From: jose.souza at intel.com (Souza, Jose) Date: Wed, 3 Jun 2020 21:27:03 +0000 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <dc4e459534b6815b932c16ec38a1e2714d94ec07.camel@intel.com> On Thu, 2020-06-04 at 00:10 +0300, Imre Deak wrote: > Currently MST on a port can get enabled/disabled from the hotplug work > and get disabled from the short pulse work in a racy way. Fix this by > relying on the MST state checking in the hotplug work and just schedule > a hotplug work from the short pulse handler if some problem happened > during the MST interrupt handling. Nice > > This removes the explicit MST disabling in case of an AUX failure, but > if AUX fails, then probably the detection will also fail during the > scheduled hotplug work and it's not guaranteed that we'll see > intermittent errors anyway. > > While at it also simplify the error checking of the MST interrupt > handler. > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++---------------------- > 1 file changed, 4 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 55fda074c0ad..befbcacddaa1 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5604,7 +5604,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) > } > } > > - return need_retrain; > + return need_retrain ? -EINVAL : 0; > } > > static bool > @@ -7255,35 +7255,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > } > > if (intel_dp->is_mst) { > - switch (intel_dp_check_mst_status(intel_dp)) { > - case -EINVAL: > - /* > - * If we were in MST mode, and device is not > - * there, get out of MST mode > - */ > - drm_dbg_kms(&i915->drm, > - "MST device may have disappeared %d vs %d\n", > - intel_dp->is_mst, > - intel_dp->mst_mgr.mst_state); > - intel_dp->is_mst = false; > - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > - intel_dp->is_mst); > - > - return IRQ_NONE; > - case 1: > - return IRQ_NONE; > - default: > - break; > - } > - } > - > - if (!intel_dp->is_mst) { > - bool handled; > - > - handled = intel_dp_short_pulse(intel_dp); > - > - if (!handled) > + if (intel_dp_check_mst_status(intel_dp) < 0) > return IRQ_NONE; > + } else if (!intel_dp_short_pulse(intel_dp)) { > + return IRQ_NONE; > } > > return IRQ_HANDLED; From jose.souza at intel.com Wed Jun 3 21:27:56 2020 From: jose.souza at intel.com (Souza, Jose) Date: Wed, 3 Jun 2020 21:27:56 +0000 Subject: [Intel-gfx] [PATCH 2/3] drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() In-Reply-To: <20200603211040.8190-2-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> <20200603211040.8190-2-imre.deak@intel.com> Message-ID: <e7abd54653ae305f9df136e487951dd940f07ae2.camel@intel.com> On Thu, 2020-06-04 at 00:10 +0300, Imre Deak wrote: > Make the locking look symmetric with the unlocking. > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 1bdf3cfeeebb..5bc72e800b85 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -1183,7 +1183,7 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, > ret = wait_event_timeout(mgr->tx_waitq, > check_txmsg_state(mgr, txmsg), > (4 * HZ)); > - mutex_lock(&mstb->mgr->qlock); > + mutex_lock(&mgr->qlock); > if (ret > 0) { > if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { > ret = -EIO; From patchwork at emeril.freedesktop.org Wed Jun 3 21:34:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 21:34:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/3=5D_drm/i915/dp=5Fmst=3A_Fix_dis?= =?utf-8?q?abling_MST_on_a_port?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159122008011.12268.3679410813087741873@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/dp_mst: Fix disabling MST on a port URL : https://patchwork.freedesktop.org/series/77969/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1fa53eafe47a drm/i915/dp_mst: Fix disabling MST on a port 6474c11029fb drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() 7a10916bbf7e drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses -:13: WARNING:TYPO_SPELLING: 'specificatin' may be misspelled - perhaps 'specification'? #13: specificatin DP sources should detect short pulses in the total: 0 errors, 1 warnings, 0 checks, 56 lines checked From patchwork at emeril.freedesktop.org Wed Jun 3 21:56:09 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 21:56:09 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/i915/dp=5Fmst=3A_Fix_disabling_?= =?utf-8?q?MST_on_a_port?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159122136981.12267.8909339668211195633@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/dp_mst: Fix disabling MST on a port URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17858 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/index.html Known issues ------------ Here are the changes found in Patchwork_17858 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-tgl-y: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][11] ([i915#1928]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17858 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17858: 7a10916bbf7e8b6d18f552c3d6135250da4caa20 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7a10916bbf7e drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses 6474c11029fb drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() 1fa53eafe47a drm/i915/dp_mst: Fix disabling MST on a port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/index.html From patchwork at emeril.freedesktop.org Wed Jun 3 22:02:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 22:02:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Remaining_RKL_patches?= In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <159122173721.12268.10472269082071576936@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches URL : https://patchwork.freedesktop.org/series/77971/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9433b10a50aa drm/i915/rkl: Set transcoder mask properly -:22: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations #22: FILE: drivers/gpu/drm/i915/i915_pci.c:884: + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ total: 0 errors, 1 warnings, 0 checks, 8 lines checked d848bdb66774 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 -:36: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #36: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:5266: + min_buddy = max_buddy = 0; total: 0 errors, 0 warnings, 1 checks, 84 lines checked ef03bae65599 drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} 6c98fe20e57a drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout 9f0cbd84fd69 drm/i915/rkl: Setup ports/phys 3ae91df36611 drm/i915/rkl: provide port/phy mapping for vbt -:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #20: [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A] total: 0 errors, 1 warnings, 0 checks, 104 lines checked 8795a1027509 drm/i915/rkl: Update TGP's pin mapping when paired with RKL e05a981ee980 drm/i915/rkl: Add DDC pin mapping 729aaa26c152 drm/i915/rkl: Don't try to access transcoder D 8a112abfdc1c drm/i915/rkl: Don't try to read out DSI transcoders 307b9ecdbdbb drm/i915/rkl: Handle comp master/slave relationships for PHYs f57c6c3d15ce drm/i915/rkl: Add DPLL4 support 20a10ff5d3a6 drm/i915/rkl: Handle HTI -:156: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #156: FILE: drivers/gpu/drm/i915/i915_reg.h:2911: +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*(phy) + 2) ^ -:157: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #157: FILE: drivers/gpu/drm/i915/i915_reg.h:2912: +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2*(phy) + 1) ^ total: 0 errors, 0 warnings, 2 checks, 115 lines checked bfe78337ad8d drm/i915/rkl: Disable PSR2 c298c9e3576e drm/i915/rkl: Add initial workarounds From patchwork at emeril.freedesktop.org Wed Jun 3 22:03:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 22:03:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Remaining_RKL_patches?= In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <159122180922.12265.2402010855953631965@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches URL : https://patchwork.freedesktop.org/series/77971/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From clinton.a.taylor at intel.com Wed Jun 3 22:11:50 2020 From: clinton.a.taylor at intel.com (clinton.a.taylor at intel.com) Date: Wed, 3 Jun 2020 15:11:50 -0700 Subject: [Intel-gfx] [PATCH v2] drm/i915/tgl: Implement WA_16011163337 Message-ID: <20200603221150.14745-1-clinton.a.taylor@intel.com> From: Clint Taylor <clinton.a.taylor at intel.com> Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2 not being able to be read. V2: Math issue fixed Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Caz Yokoyama <caz.yokoyama at intel.com> Cc: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 30cd798b9664..a2d5624e5542 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -609,11 +609,11 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1604555607:gen12 and Wa_1608008084:gen12 * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit - * masks. So instead of doing a RMW we should just write the TDS timer - * value for Wa_1604555607. + * masks. So instead of doing a RMW we should just write the GS Timer + * and TDS timer values for Wa_1604555607 and Wa_16011163337. */ - wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, - FF_MODE2_TDS_TIMER_128, 0); + wa_add(wal, FF_MODE2, FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, + FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 0); /* WaDisableGPGPUMidThreadPreemption:tgl */ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 578cfe11cbb9..96d351fbeebb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8004,6 +8004,8 @@ enum { #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) #define FF_MODE2 _MMIO(0x6604) +#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) +#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) -- 2.26.0 From imre.deak at intel.com Wed Jun 3 22:18:59 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 01:18:59 +0300 Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200603211040.8190-3-imre.deak@intel.com> References: <20200603211040.8190-3-imre.deak@intel.com> Message-ID: <20200603221859.9600-1-imre.deak@intel.com> Some TypeC -> native DP adapters, at least the Club CAC-1557 adapter, incorrectly filter out HPD short pulses with a duration less than ~540 usec, leading to MST probe failures. According to the DP alt mode specification adapters should forward short pulses with a duration greater than 250 usec. According to the DP specificatin DP sources should detect short pulses in the 500 usec -> 2 ms range. Based on this filtering out short pulses with a duration less than 540 usec is incorrect. To make such adapters work add support for a driver polling on MST inerrupt flags, and wire this up in the i915 driver. The sink can clear an interrupt it raised after 110 ms if the source doesn't respond, so use a 50 ms poll period to avoid missing an interrupt. Polling of the MST interrupt flags is explicitly allowed by the DP specification. This fixes MST probe failures I saw using this adapter and a DELL U2515H monitor. v2: - Fix the wait event timeout for the no-poll case. Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 19 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 +++++++++++++++ include/drm/drm_dp_mst_helper.h | 1 + 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 5bc72e800b85..4e987a513df8 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1178,11 +1178,24 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, struct drm_dp_sideband_msg_tx *txmsg) { struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; + unsigned long wait_timeout = msecs_to_jiffies(4000); + unsigned long wait_expires = jiffies + wait_timeout; int ret; - ret = wait_event_timeout(mgr->tx_waitq, - check_txmsg_state(mgr, txmsg), - (4 * HZ)); + for (;;) { + ret = wait_event_timeout(mgr->tx_waitq, + check_txmsg_state(mgr, txmsg), + mgr->cbs->update_hpd_irq_state ? + msecs_to_jiffies(50) : + wait_timeout); + + if (ret || !mgr->cbs->update_hpd_irq_state || + time_after(jiffies, wait_expires)) + break; + + mgr->cbs->update_hpd_irq_state(mgr); + } + mutex_lock(&mgr->qlock); if (ret > 0) { if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d18b406f2a7d..1ff7d0096262 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -765,8 +765,23 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo return NULL; } +static void +intel_dp_mst_update_hpd_irq_state(struct drm_dp_mst_topology_mgr *mgr) +{ + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + spin_lock_irq(&i915->irq_lock); + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); + spin_unlock_irq(&i915->irq_lock); + + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); +} + static const struct drm_dp_mst_topology_cbs mst_cbs = { .add_connector = intel_dp_add_mst_connector, + .update_hpd_irq_state = intel_dp_mst_update_hpd_irq_state, }; static struct intel_dp_mst_encoder * diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 9e1ffcd7cb68..c902f4380200 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -475,6 +475,7 @@ struct drm_dp_mst_topology_mgr; struct drm_dp_mst_topology_cbs { /* create a connector for a port */ struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); + void (*update_hpd_irq_state)(struct drm_dp_mst_topology_mgr *mgr); }; #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) -- 2.23.1 From patchwork at emeril.freedesktop.org Wed Jun 3 22:23:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 22:23:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches?= In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <159122301333.12266.10654874056800043161@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17859 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html Known issues ------------ Here are the changes found in Patchwork_17859 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][9] ([i915#1928]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 45) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17859 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17859: c298c9e3576e74cdc573db5a6f877f920d106bbb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c298c9e3576e drm/i915/rkl: Add initial workarounds bfe78337ad8d drm/i915/rkl: Disable PSR2 20a10ff5d3a6 drm/i915/rkl: Handle HTI f57c6c3d15ce drm/i915/rkl: Add DPLL4 support 307b9ecdbdbb drm/i915/rkl: Handle comp master/slave relationships for PHYs 8a112abfdc1c drm/i915/rkl: Don't try to read out DSI transcoders 729aaa26c152 drm/i915/rkl: Don't try to access transcoder D e05a981ee980 drm/i915/rkl: Add DDC pin mapping 8795a1027509 drm/i915/rkl: Update TGP's pin mapping when paired with RKL 3ae91df36611 drm/i915/rkl: provide port/phy mapping for vbt 9f0cbd84fd69 drm/i915/rkl: Setup ports/phys 6c98fe20e57a drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout ef03bae65599 drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} d848bdb66774 drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 9433b10a50aa drm/i915/rkl: Set transcoder mask properly == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html From aditya.swarup at intel.com Wed Jun 3 22:34:32 2020 From: aditya.swarup at intel.com (Aditya Swarup) Date: Wed, 3 Jun 2020 15:34:32 -0700 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 In-Reply-To: <20200603211529.3005059-3-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-3-matthew.d.roper@intel.com> Message-ID: <20200603223432.GA23488@aswarup-mobl> On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote: > RKL uses the same BW_BUDDY programming table as TGL, but programs the > values into a single set BUDDY0 set of registers rather than the > BUDDY1/BUDDY2 sets used by TGL. > > Bspec: 49218 > Cc: Aditya Swarup <aditya.swarup at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > .../drm/i915/display/intel_display_power.c | 44 +++++++++++-------- > drivers/gpu/drm/i915/i915_reg.h | 14 ++++-- > 2 files changed, 35 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 72312b67b57a..2c1ce50b572b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > enum intel_dram_type type = dev_priv->dram_info.type; > u8 num_channels = dev_priv->dram_info.num_channels; > const struct buddy_page_mask *table; > - int i; > + int config, min_buddy, max_buddy, i; > > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) > /* Wa_1409767108: tgl */ > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > else > table = tgl_buddy_page_masks; > > - for (i = 0; table[i].page_mask != 0; i++) > - if (table[i].num_channels == num_channels && > - table[i].type == type) > + if (IS_ROCKETLAKE(dev_priv)) { > + min_buddy = max_buddy = 0; > + } else { > + min_buddy = 1; > + max_buddy = 2; > + } > + > + for (config = 0; table[config].page_mask != 0; config++) > + if (table[config].num_channels == num_channels && > + table[config].type == type) > break; > > - if (table[i].page_mask == 0) { > + if (table[config].page_mask == 0) { > drm_dbg(&dev_priv->drm, > "Unknown memory configuration; disabling address buddy logic.\n"); > - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); > - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); > + for (i = min_buddy; i <= max_buddy; i++) > + intel_de_write(dev_priv, BW_BUDDY_CTL(i), > + BW_BUDDY_DISABLE); > } else { > - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, > - table[i].page_mask); > - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, > - table[i].page_mask); > - > - /* Wa_22010178259:tgl */ > - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, > - BW_BUDDY_TLB_REQ_TIMER_MASK, > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, > - BW_BUDDY_TLB_REQ_TIMER_MASK, > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > + for (i = min_buddy; i <= max_buddy; i++) { > + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > + table[config].page_mask); > + > + /* Wa_22010178259:tgl,rkl */ > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > + BW_BUDDY_TLB_REQ_TIMER_MASK, > + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, > + 0x8)); We should be using REG_FIELD_PREP() in i915_reg.h to declare TLB_REQ_TIMER value and then use the value here. > + } > } > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 578cfe11cbb9..3e79cefc510a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7837,13 +7837,19 @@ enum { > #define WAIT_FOR_PCH_RESET_ACK (1 << 1) > #define WAIT_FOR_PCH_FLR_ACK (1 << 0) > > -#define BW_BUDDY1_CTL _MMIO(0x45140) > -#define BW_BUDDY2_CTL _MMIO(0x45150) > +#define _BW_BUDDY0_CTL 0x45130 > +#define _BW_BUDDY1_CTL 0x45140 > +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ > + _BW_BUDDY0_CTL, \ > + _BW_BUDDY1_CTL)) > #define BW_BUDDY_DISABLE REG_BIT(31) > #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) > > -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) > -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) > +#define _BW_BUDDY0_PAGE_MASK 0x45134 > +#define _BW_BUDDY1_PAGE_MASK 0x45144 > +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ > + _BW_BUDDY0_PAGE_MASK, \ > + _BW_BUDDY1_PAGE_MASK)) > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > -- > 2.24.1 > From patchwork at emeril.freedesktop.org Wed Jun 3 22:50:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 22:50:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Implement_WA=5F16011163337_=28rev2=29?= In-Reply-To: <20200603221150.14745-1-clinton.a.taylor@intel.com> References: <20200603221150.14745-1-clinton.a.taylor@intel.com> Message-ID: <159122463717.12267.17853930366660022029@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Implement WA_16011163337 (rev2) URL : https://patchwork.freedesktop.org/series/77933/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17860 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/index.html Known issues ------------ Here are the changes found in Patchwork_17860 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_busy@basic at flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][5] ([i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][7] ([i915#1928]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_pipe_crc_basic@read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 45) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17860 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17860: db356ac08f68ff4efb08d69e177faeb2b550c252 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == db356ac08f68 drm/i915/tgl: Implement WA_16011163337 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/index.html From patchwork at emeril.freedesktop.org Wed Jun 3 22:56:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 22:56:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/3=5D_drm/i915/dp=5Fmst=3A_Fix_dis?= =?utf-8?q?abling_MST_on_a_port_=28rev2=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159122499556.12265.7309677309374973839@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev2) URL : https://patchwork.freedesktop.org/series/77969/ State : warning == Summary == $ dim checkpatch origin/drm-tip 240b4ea78683 drm/i915/dp_mst: Fix disabling MST on a port 36ebc90ef54b drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() 10ec0f0a95d1 drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses -:13: WARNING:TYPO_SPELLING: 'specificatin' may be misspelled - perhaps 'specification'? #13: specificatin DP sources should detect short pulses in the total: 0 errors, 1 warnings, 0 checks, 57 lines checked From matthew.d.roper at intel.com Wed Jun 3 23:12:59 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 3 Jun 2020 16:12:59 -0700 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 In-Reply-To: <20200603223432.GA23488@aswarup-mobl> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-3-matthew.d.roper@intel.com> <20200603223432.GA23488@aswarup-mobl> Message-ID: <20200603231259.GC2992531@mdroper-desk1.amr.corp.intel.com> On Wed, Jun 03, 2020 at 03:34:32PM -0700, Aditya Swarup wrote: > On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote: > > RKL uses the same BW_BUDDY programming table as TGL, but programs the > > values into a single set BUDDY0 set of registers rather than the > > BUDDY1/BUDDY2 sets used by TGL. > > > > Bspec: 49218 > > Cc: Aditya Swarup <aditya.swarup at intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > --- > > .../drm/i915/display/intel_display_power.c | 44 +++++++++++-------- > > drivers/gpu/drm/i915/i915_reg.h | 14 ++++-- > > 2 files changed, 35 insertions(+), 23 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 72312b67b57a..2c1ce50b572b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > enum intel_dram_type type = dev_priv->dram_info.type; > > u8 num_channels = dev_priv->dram_info.num_channels; > > const struct buddy_page_mask *table; > > - int i; > > + int config, min_buddy, max_buddy, i; > > > > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) > > /* Wa_1409767108: tgl */ > > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > else > > table = tgl_buddy_page_masks; > > > > - for (i = 0; table[i].page_mask != 0; i++) > > - if (table[i].num_channels == num_channels && > > - table[i].type == type) > > + if (IS_ROCKETLAKE(dev_priv)) { > > + min_buddy = max_buddy = 0; > > + } else { > > + min_buddy = 1; > > + max_buddy = 2; > > + } > > + > > + for (config = 0; table[config].page_mask != 0; config++) > > + if (table[config].num_channels == num_channels && > > + table[config].type == type) > > break; > > > > - if (table[i].page_mask == 0) { > > + if (table[config].page_mask == 0) { > > drm_dbg(&dev_priv->drm, > > "Unknown memory configuration; disabling address buddy logic.\n"); > > - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); > > - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); > > + for (i = min_buddy; i <= max_buddy; i++) > > + intel_de_write(dev_priv, BW_BUDDY_CTL(i), > > + BW_BUDDY_DISABLE); > > } else { > > - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, > > - table[i].page_mask); > > - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, > > - table[i].page_mask); > > - > > - /* Wa_22010178259:tgl */ > > - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > + for (i = min_buddy; i <= max_buddy; i++) { > > + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > > + table[config].page_mask); > > + > > + /* Wa_22010178259:tgl,rkl */ > > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > > + BW_BUDDY_TLB_REQ_TIMER_MASK, > > + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, > > + 0x8)); > We should be using REG_FIELD_PREP() in i915_reg.h to declare > TLB_REQ_TIMER value and then use the value here. Any specific reason why? The value "8" doesn't have any specific hardware meaning that would be meaningful to define in the general register definitions. It's just a value that this specific hardware workaround asked for in this case. I'm not sure if we want to spread the definition of the workaround into the register file if the value isn't going to be meaningful to other driver programming or workarounds. Matt > > + } > > } > > } > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 578cfe11cbb9..3e79cefc510a 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7837,13 +7837,19 @@ enum { > > #define WAIT_FOR_PCH_RESET_ACK (1 << 1) > > #define WAIT_FOR_PCH_FLR_ACK (1 << 0) > > > > -#define BW_BUDDY1_CTL _MMIO(0x45140) > > -#define BW_BUDDY2_CTL _MMIO(0x45150) > > +#define _BW_BUDDY0_CTL 0x45130 > > +#define _BW_BUDDY1_CTL 0x45140 > > +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ > > + _BW_BUDDY0_CTL, \ > > + _BW_BUDDY1_CTL)) > > #define BW_BUDDY_DISABLE REG_BIT(31) > > #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) > > > > -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) > > -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) > > +#define _BW_BUDDY0_PAGE_MASK 0x45134 > > +#define _BW_BUDDY1_PAGE_MASK 0x45144 > > +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ > > + _BW_BUDDY0_PAGE_MASK, \ > > + _BW_BUDDY1_PAGE_MASK)) > > > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > > #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > > -- > > 2.24.1 > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From patchwork at emeril.freedesktop.org Wed Jun 3 23:18:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 03 Jun 2020 23:18:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/i915/dp=5Fmst=3A_Fix_disabling_?= =?utf-8?q?MST_on_a_port_=28rev2=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159122633746.12266.4565398390253539659@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev2) URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17861 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/index.html Known issues ------------ Here are the changes found in Patchwork_17861 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#1372]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-7500u/igt at kms_chamelium@hdmi-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-kbl-7500u/igt at kms_chamelium@hdmi-crc-fast.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-glk-dsi: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-glk-dsi/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-glk-dsi/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][15] ([i915#1928]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17861 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17861: 10ec0f0a95d1ed7b600df217f021788844964bc8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 10ec0f0a95d1 drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses 36ebc90ef54b drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() 240b4ea78683 drm/i915/dp_mst: Fix disabling MST on a port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/index.html From chris at chris-wilson.co.uk Wed Jun 3 23:47:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 00:47:58 +0100 Subject: [Intel-gfx] [PATCH i-g-t 2/2] HAX:fair In-Reply-To: <20200603234758.1961637-1-chris@chris-wilson.co.uk> References: <20200603234758.1961637-1-chris@chris-wilson.co.uk> Message-ID: <20200603234758.1961637-2-chris@chris-wilson.co.uk> --- tests/intel-ci/fast-feedback.testlist | 163 +------------------------- 1 file changed, 3 insertions(+), 160 deletions(-) diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist index 04f6affcf..9cf460894 100644 --- a/tests/intel-ci/fast-feedback.testlist +++ b/tests/intel-ci/fast-feedback.testlist @@ -1,162 +1,5 @@ # Keep alphabetically sorted by default -igt at core_auth@basic-auth -igt at debugfs_test@read_all_entries -igt at fbdev@mmap -igt at gem_basic@bad-close -igt at gem_basic@create-close -igt at gem_basic@create-fd-close -igt at gem_busy@busy at all -igt at gem_close_race@basic-process -igt at gem_close_race@basic-threads -igt at gem_ctx_create@basic -igt at gem_ctx_create@basic-files -igt at gem_ctx_exec@basic -igt at gem_exec_basic@basic -igt at gem_exec_create@basic -igt at gem_exec_fence@basic-busy -igt at gem_exec_fence@basic-wait -igt at gem_exec_fence@basic-await -igt at gem_exec_fence@nb-await -igt at gem_exec_gttfill@basic -igt at gem_exec_parallel@engines -igt at gem_exec_store@basic -igt at gem_exec_suspend@basic-s0 -igt at gem_exec_suspend@basic-s3 -igt at gem_flink_basic@bad-flink -igt at gem_flink_basic@bad-open -igt at gem_flink_basic@basic -igt at gem_flink_basic@double-flink -igt at gem_flink_basic@flink-lifetime -igt at gem_linear_blits@basic -igt at gem_mmap@basic -igt at gem_mmap_gtt@basic -igt at gem_render_linear_blits@basic -igt at gem_render_tiled_blits@basic -igt at gem_ringfill@basic-all -igt at gem_sync@basic-all -igt at gem_sync@basic-each -igt at gem_tiled_blits@basic -igt at gem_tiled_fence_blits@basic -igt at gem_tiled_pread_basic -igt at gem_wait@busy at all -igt at gem_wait@wait at all -igt at i915_getparams_basic@basic-eu-total -igt at i915_getparams_basic@basic-subslice-total -igt at i915_hangman@error-state-basic -igt at kms_addfb_basic@addfb25-bad-modifier -igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling -igt at kms_addfb_basic@addfb25-modifier-no-flag -igt at kms_addfb_basic@addfb25-x-tiled -igt at kms_addfb_basic@addfb25-x-tiled-mismatch -igt at kms_addfb_basic@addfb25-yf-tiled -igt at kms_addfb_basic@addfb25-y-tiled -igt at kms_addfb_basic@addfb25-y-tiled-small -igt at kms_addfb_basic@bad-pitch-0 -igt at kms_addfb_basic@bad-pitch-1024 -igt at kms_addfb_basic@bad-pitch-128 -igt at kms_addfb_basic@bad-pitch-256 -igt at kms_addfb_basic@bad-pitch-32 -igt at kms_addfb_basic@bad-pitch-63 -igt at kms_addfb_basic@bad-pitch-65536 -igt at kms_addfb_basic@bad-pitch-999 -igt at kms_addfb_basic@basic -igt at kms_addfb_basic@basic-x-tiled -igt at kms_addfb_basic@basic-y-tiled -igt at kms_addfb_basic@bo-too-small -igt at kms_addfb_basic@bo-too-small-due-to-tiling -igt at kms_addfb_basic@clobberred-modifier -igt at kms_addfb_basic@framebuffer-vs-set-tiling -igt at kms_addfb_basic@invalid-get-prop -igt at kms_addfb_basic@invalid-get-prop-any -igt at kms_addfb_basic@invalid-set-prop -igt at kms_addfb_basic@invalid-set-prop-any -igt at kms_addfb_basic@no-handle -igt at kms_addfb_basic@size-max -igt at kms_addfb_basic@small-bo -igt at kms_addfb_basic@tile-pitch-mismatch -igt at kms_addfb_basic@too-high -igt at kms_addfb_basic@too-wide -igt at kms_addfb_basic@unused-handle -igt at kms_addfb_basic@unused-modifier -igt at kms_addfb_basic@unused-offsets -igt at kms_addfb_basic@unused-pitches -igt at kms_busy@basic -igt at kms_chamelium@dp-hpd-fast -igt at kms_chamelium@dp-edid-read -igt at kms_chamelium@dp-crc-fast -igt at kms_chamelium@hdmi-hpd-fast -igt at kms_chamelium@hdmi-edid-read -igt at kms_chamelium@hdmi-crc-fast -igt at kms_chamelium@vga-hpd-fast -igt at kms_chamelium@vga-edid-read -igt at kms_chamelium@common-hpd-after-suspend -igt at kms_prop_blob@basic -igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic -igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy -igt at kms_cursor_legacy@basic-flip-after-cursor-atomic -igt at kms_cursor_legacy@basic-flip-after-cursor-legacy -igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size -igt at kms_cursor_legacy@basic-flip-before-cursor-atomic -igt at kms_cursor_legacy@basic-flip-before-cursor-legacy -igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size -igt at kms_flip@basic-flip-vs-dpms -igt at kms_flip@basic-flip-vs-modeset -igt at kms_flip@basic-flip-vs-wf_vblank -igt at kms_flip@basic-plain-flip -igt at kms_force_connector_basic@force-connector-state -igt at kms_force_connector_basic@force-edid -igt at kms_force_connector_basic@force-load-detect -igt at kms_force_connector_basic@prune-stale-modes -igt at kms_frontbuffer_tracking@basic -igt at kms_pipe_crc_basic@hang-read-crc-pipe-a -igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a -igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence -igt at kms_pipe_crc_basic@read-crc-pipe-a -igt at kms_pipe_crc_basic@read-crc-pipe-b -igt at kms_pipe_crc_basic@read-crc-pipe-c -igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence -igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a -igt at kms_psr@primary_page_flip -igt at kms_psr@cursor_plane_move -igt at kms_psr@sprite_plane_onoff -igt at kms_psr@primary_mmap_gtt -igt at kms_setmode@basic-clone-single-crtc -igt at i915_pm_backlight@basic-brightness -igt at i915_pm_rpm@basic-pci-d3-state -igt at i915_pm_rpm@basic-rte -igt at i915_pm_rps@basic-api -igt at prime_self_import@basic-llseek-bad -igt at prime_self_import@basic-llseek-size -igt at prime_self_import@basic-with_fd_dup -igt at prime_self_import@basic-with_one_bo -igt at prime_self_import@basic-with_one_bo_two_files -igt at prime_self_import@basic-with_two_bos -igt at prime_vgem@basic-fence-flip -igt at prime_vgem@basic-fence-mmap -igt at prime_vgem@basic-fence-read -igt at prime_vgem@basic-gtt -igt at prime_vgem@basic-read -igt at prime_vgem@basic-write -igt at vgem_basic@setversion -igt at vgem_basic@create -igt at vgem_basic@debugfs -igt at vgem_basic@dmabuf-export -igt at vgem_basic@dmabuf-fence -igt at vgem_basic@dmabuf-fence-before -igt at vgem_basic@dmabuf-mmap -igt at vgem_basic@mmap -igt at vgem_basic@second-client -igt at vgem_basic@sysfs - -# All tests that do module unloading and reloading are executed last. -# They will sometimes reveal issues of earlier tests leaving the -# driver in a broken state that is not otherwise noticed in that test. - -igt at vgem_basic@unload -igt at i915_module_load@reload -igt at i915_pm_rpm@module-reload - -# Kernel selftests -igt at i915_selftest@live -igt at dmabuf@all +igt at gem_exec_schedule@fair-none +igt at gem_exec_schedule@fair-pace +igt at gem_exec_schedule@fair-flow -- 2.27.0 From chris at chris-wilson.co.uk Wed Jun 3 23:47:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 00:47:57 +0100 Subject: [Intel-gfx] [PATCH i-g-t 1/2] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200603234758.1961637-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Ramalingam C <ramalingam.c at intel.com> --- tests/i915/gem_exec_schedule.c | 571 +++++++++++++++++++++++++++++++++ 1 file changed, 571 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..160b04b2f 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -29,6 +29,7 @@ #include <sys/poll.h> #include <sys/ioctl.h> #include <sys/mman.h> +#include <sys/resource.h> #include <sys/syscall.h> #include <sched.h> #include <signal.h> @@ -2495,6 +2496,545 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define RUNTIME (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(START_TS); + + while (offset_in_page(cs) & 63) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + *cs++ = MI_STORE_DWORD_IMM; + if (use_64b) { + *cs++ = addr + 4064; + *cs++ = addr >> 32; + } else { + *cs++ = 0; + *cs++ = addr + 4064; + } + *cs++ = 0; + } + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static struct intel_execution_engine2 +pick_random_engine(int i915, const struct intel_execution_engine2 *not) +{ + const struct intel_execution_engine2 *e; + unsigned int count = 0; + + __for_each_physical_engine(i915, e) { + if (e->flags == not->flags) + continue; + if (!gem_class_has_mutable_submission(i915, e->class)) + continue; + count++; + } + if (!count) + return *not; + + count = rand() % count; + __for_each_physical_engine(i915, e) { + if (e->flags == not->flags) + continue; + if (!gem_class_has_mutable_submission(i915, e->class)) + continue; + if (!count--) + break; + } + + return *e; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeout, + int timeline, + uint32_t common, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +#define F_SPARE (1 << 5) +#define F_NEXT (1 << 6) +#define F_VIP (1 << 7) +#define F_RRUL (1 << 8) +#define F_SHARE (1 << 9) +#define F_PING (1 << 10) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 obj[4] = { + {}, + { + .handle = common ?: gem_create(i915, 4096), + }, + delay_create(i915, ctx, e, frame_ns / batches_per_frame), + delay_create(i915, ctx, e, frame_ns / batches_per_frame), + }; + struct intel_execution_engine2 ping = *e; + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + uint32_t *map; + int n; + + srandom(getpid()); + if (flags & F_PING) + ping = pick_random_engine(i915, e); + obj[0] = tslog_create(i915, ctx, &ping); + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(obj), + .buffer_count = 4, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_FLOW) { + unsigned int seq; + + seq = count; + if (flags & F_NEXT) + seq++; + + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, seq); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + close(execbuf.rsvd2); + + execbuf.buffer_count = 1; + execbuf.batch_start_offset = 2048; + execbuf.flags = ping.flags | I915_EXEC_FENCE_IN; + execbuf.rsvd2 = n_fence; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + igt_swap(obj[2], obj[3]); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, obj[3].handle); + gem_close(i915, obj[2].handle); + if (obj[1].handle != common) + gem_close(i915, obj[1].handle); + + gem_sync(i915, obj[0].handle); + map = gem_mmap__device_coherent(i915, obj[0].handle, 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[(9 *n + 9) / 10 - 1]); + munmap(map, 4096); + + gem_close(i915, obj[0].handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static uint64_t d_cpu_time(const struct rusage *a, const struct rusage *b) +{ + uint64_t cpu_time = 0; + + cpu_time += (a->ru_utime.tv_sec - b->ru_utime.tv_sec) * NSEC_PER_SEC; + cpu_time += (a->ru_utime.tv_usec - b->ru_utime.tv_usec) * 1000; + + cpu_time += (a->ru_stime.tv_sec - b->ru_stime.tv_sec) * NSEC_PER_SEC; + cpu_time += (a->ru_stime.tv_usec - b->ru_stime.tv_usec) * 1000; + + return cpu_time; +} + +static void timeline_advance(int timeline, int delay_ns) +{ + struct timespec tv = { .tv_nsec = delay_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + uint32_t common = 0; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + if (flags & F_SHARE) + common = gem_create(i915, 4095); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 32; n <<= 1) { /* 32 == 500us per client */ + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE)); + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct rusage old_usage, usage; + uint64_t cpu_time, d_time; + struct timespec tv; + struct igt_mean m; + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + getrusage(RUSAGE_CHILDREN, &old_usage); + igt_nsec_elapsed(memset(&tv, 0, sizeof(tv))); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + if (flags & F_VIP && child == 0) { + gem_context_set_priority(i915, ctx, MAX_PRIO); + flags |= F_FLOW; + } + if (flags & F_RRUL && child == 0) + flags |= F_SOLO | F_FLOW | F_SYNC; + + fair_child(i915, ctx, e, child_ns, + timeout, timeline, common, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) + timeline_advance(timeline, fence_ns); + + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) + timeline_advance(timeline, fence_ns); + } + + igt_waitchildren(); + close(timeline); + + d_time = igt_nsec_elapsed(&tv); + getrusage(RUSAGE_CHILDREN, &usage); + cpu_time = d_cpu_time(&usage, &old_usage); + if (2 * cpu_time > d_time) { + igt_info("%.0f%% CPU usage, presuming capacity exceeded\n", + 100.* cpu_time / d_time); + break; + } + + if (flags & (F_VIP | F_RRUL)) { + igt_info("VIP interval %.2f ms\n", 1e-6 * result[0]); + igt_assert(4 * result[0] > 3 * fence_ns && + 3 * result[0] < 4 * fence_ns); + } + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + + /* Mean within 25% of target */ + igt_assert(4 * igt_mean_get(&m) > 3 * fence_ns && + 3 * igt_mean_get(&m) < 4 * fence_ns); + + /* Variance [inter-quartile range] is less than 25% of median */ + igt_assert(4 * (result[hi] - result[lo]) < result[nchild / 2]); + } + + munmap(result, 4096); + if (common) + gem_close(i915, common); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2589,6 +3129,37 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-none-vip", fd, e) + fairness(fd, e, 2, F_VIP); + test_each_engine_store("fair-none-share", fd, e) + fairness(fd, e, 2, F_SHARE); + test_each_engine_store("fair-none-rrul", fd, e) + fairness(fd, e, 2, F_RRUL); + test_each_engine_store("fair-none-ping", fd, e) + fairness(fd, e, 2, F_PING); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACE); + test_each_engine_store("fair-pace-share", fd, e) + fairness(fd, e, 2, F_PACE | F_SHARE); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_SYNC); + test_each_engine_store("fair-sync-vip", fd, e) + fairness(fd, e, 2, F_SYNC | F_VIP); + test_each_engine_store("fair-solo", fd, e) + fairness(fd, e, 2, F_SYNC | F_SOLO); + test_each_engine_store("fair-flow", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW); + test_each_engine_store("fair-next", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_NEXT); + test_each_engine_store("fair-next-share", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_NEXT | F_SHARE); + test_each_engine_store("fair-spare", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_SPARE); + test_each_engine_store("fair-half", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_HALF); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0 From manasi.d.navare at intel.com Thu Jun 4 00:23:59 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Wed, 3 Jun 2020 17:23:59 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect Message-ID: <20200604002359.17128-1-manasi.d.navare@intel.com> We have noticed that when link training fails the panel sends a long pulse indicating connector disconnect. In this case we need to reset the link parameters instead of continuing to use the fallback parameters since else this long pulse by the panel followed by a modeset request which was triggered by the userspace before getting the connector status as disconnected, will result into a modeset now using lower link rate/lane count values. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1385 Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++-------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 55fda074c0ad..f7af372647dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6111,6 +6111,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) intel_dp->edid_quirks = 0; } +static void +intel_dp_reset_link_params(struct intel_dp *intel_dp) +{ + /* Initial max link lane count */ + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); + + /* Initial max link rate */ + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); + + intel_dp->reset_link_params = false; +} + static int intel_dp_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, @@ -6139,6 +6151,11 @@ intel_dp_detect(struct drm_connector *connector, memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); + intel_dp_reset_link_params(intel_dp); + if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, "MST device may have disappeared %d vs %d\n", @@ -6152,15 +6169,8 @@ intel_dp_detect(struct drm_connector *connector, goto out; } - if (intel_dp->reset_link_params) { - /* Initial max link lane count */ - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); - - /* Initial max link rate */ - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); - - intel_dp->reset_link_params = false; - } + if (intel_dp->reset_link_params) + intel_dp_reset_link_params(intel_dp); intel_dp_print_rates(intel_dp); -- 2.19.1 From patchwork at emeril.freedesktop.org Thu Jun 4 00:49:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 00:49:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/dp=3A_Reset_link_params_on_connector_disconnect?= In-Reply-To: <20200604002359.17128-1-manasi.d.navare@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> Message-ID: <159123174013.14552.8786805896643161723@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp: Reset link params on connector disconnect URL : https://patchwork.freedesktop.org/series/77974/ State : warning == Summary == $ dim checkpatch origin/drm-tip 01ef52e81850 drm/i915/dp: Reset link params on connector disconnect -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: by the panel followed by a modeset request which was triggered by the userspace total: 0 errors, 1 warnings, 0 checks, 46 lines checked From aditya.swarup at intel.com Thu Jun 4 01:18:02 2020 From: aditya.swarup at intel.com (Aditya Swarup) Date: Wed, 3 Jun 2020 18:18:02 -0700 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 In-Reply-To: <20200603231259.GC2992531@mdroper-desk1.amr.corp.intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-3-matthew.d.roper@intel.com> <20200603223432.GA23488@aswarup-mobl> <20200603231259.GC2992531@mdroper-desk1.amr.corp.intel.com> Message-ID: <20200604011802.GB23488@aswarup-mobl> On Wed, Jun 03, 2020 at 04:12:59PM -0700, Matt Roper wrote: > On Wed, Jun 03, 2020 at 03:34:32PM -0700, Aditya Swarup wrote: > > On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote: > > > RKL uses the same BW_BUDDY programming table as TGL, but programs the > > > values into a single set BUDDY0 set of registers rather than the > > > BUDDY1/BUDDY2 sets used by TGL. > > > > > > Bspec: 49218 > > > Cc: Aditya Swarup <aditya.swarup at intel.com> > > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > > --- > > > .../drm/i915/display/intel_display_power.c | 44 +++++++++++-------- > > > drivers/gpu/drm/i915/i915_reg.h | 14 ++++-- > > > 2 files changed, 35 insertions(+), 23 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > > > index 72312b67b57a..2c1ce50b572b 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > > enum intel_dram_type type = dev_priv->dram_info.type; > > > u8 num_channels = dev_priv->dram_info.num_channels; > > > const struct buddy_page_mask *table; > > > - int i; > > > + int config, min_buddy, max_buddy, i; > > > > > > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) > > > /* Wa_1409767108: tgl */ > > > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > > else > > > table = tgl_buddy_page_masks; > > > > > > - for (i = 0; table[i].page_mask != 0; i++) > > > - if (table[i].num_channels == num_channels && > > > - table[i].type == type) > > > + if (IS_ROCKETLAKE(dev_priv)) { > > > + min_buddy = max_buddy = 0; > > > + } else { > > > + min_buddy = 1; > > > + max_buddy = 2; > > > + } > > > + > > > + for (config = 0; table[config].page_mask != 0; config++) > > > + if (table[config].num_channels == num_channels && > > > + table[config].type == type) > > > break; > > > > > > - if (table[i].page_mask == 0) { > > > + if (table[config].page_mask == 0) { > > > drm_dbg(&dev_priv->drm, > > > "Unknown memory configuration; disabling address buddy logic.\n"); > > > - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); > > > - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); > > > + for (i = min_buddy; i <= max_buddy; i++) > > > + intel_de_write(dev_priv, BW_BUDDY_CTL(i), > > > + BW_BUDDY_DISABLE); > > > } else { > > > - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, > > > - table[i].page_mask); > > > - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, > > > - table[i].page_mask); > > > - > > > - /* Wa_22010178259:tgl */ > > > - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, > > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > > - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, > > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > > + for (i = min_buddy; i <= max_buddy; i++) { > > > + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > > > + table[config].page_mask); > > > + > > > + /* Wa_22010178259:tgl,rkl */ > > > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > > > + BW_BUDDY_TLB_REQ_TIMER_MASK, > > > + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, > > > + 0x8)); > > We should be using REG_FIELD_PREP() in i915_reg.h to declare > > TLB_REQ_TIMER value and then use the value here. > > Any specific reason why? The value "8" doesn't have any specific > hardware meaning that would be meaningful to define in the general > register definitions. It's just a value that this specific hardware > workaround asked for in this case. I'm not sure if we want to spread > the definition of the workaround into the register file if the value > isn't going to be meaningful to other driver programming or workarounds. > > > Matt The value 8 is constant and as such should be defined in a header file for that bitmask. If there was variable used to prepare the value on the fly, I would have understood this usage. If you are concerned about 8 being a random value and not spreading to i915_reg.h, I would prefer a macro in i915_reg.h like: #define TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK,(x)) Then the value doesn't filter to i915_reg.h and according to me looks cleaner. Most of the usage of REG_FIELD_PREP in *.c files is based on creating bitfields using variable. Here we are using a constant which can easily be moved to i915_reg.h. It shouldn't matter if it is a WA or not. Adi > > > > + } > > > } > > > } > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 578cfe11cbb9..3e79cefc510a 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -7837,13 +7837,19 @@ enum { > > > #define WAIT_FOR_PCH_RESET_ACK (1 << 1) > > > #define WAIT_FOR_PCH_FLR_ACK (1 << 0) > > > > > > -#define BW_BUDDY1_CTL _MMIO(0x45140) > > > -#define BW_BUDDY2_CTL _MMIO(0x45150) > > > +#define _BW_BUDDY0_CTL 0x45130 > > > +#define _BW_BUDDY1_CTL 0x45140 > > > +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ > > > + _BW_BUDDY0_CTL, \ > > > + _BW_BUDDY1_CTL)) > > > #define BW_BUDDY_DISABLE REG_BIT(31) > > > #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) > > > > > > -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) > > > -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) > > > +#define _BW_BUDDY0_PAGE_MASK 0x45134 > > > +#define _BW_BUDDY1_PAGE_MASK 0x45144 > > > +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ > > > + _BW_BUDDY0_PAGE_MASK, \ > > > + _BW_BUDDY1_PAGE_MASK)) > > > > > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > > > #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > > > -- > > > 2.24.1 > > > > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 From patchwork at emeril.freedesktop.org Thu Jun 4 01:19:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 01:19:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/dp=3A_Reset_link_params_on_connector_disconnect?= In-Reply-To: <20200604002359.17128-1-manasi.d.navare@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> Message-ID: <159123355360.14552.15835652768974221537@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp: Reset link params on connector disconnect URL : https://patchwork.freedesktop.org/series/77974/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17862 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17862 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17862, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17862/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17862: ### IGT changes ### #### Possible regressions #### * igt at kms_chamelium@dp-hpd-fast: - fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17862/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html - fi-kbl-7500u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-7500u/igt at kms_chamelium@dp-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17862/fi-kbl-7500u/igt at kms_chamelium@dp-hpd-fast.html Known issues ------------ Here are the changes found in Patchwork_17862 that come from known issues: ### IGT changes ### #### Possible fixes #### * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][5] ([i915#1928]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17862/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 Participating hosts (51 -> 9) ------------------------------ ERROR: It appears as if the changes made in Patchwork_17862 prevented too many machines from booting. Missing (42): fi-kbl-soraka fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc fi-snb-2520m fi-icl-y fi-skl-lmem fi-byt-n2820 fi-icl-guc fi-icl-dsi fi-skl-6600u fi-snb-2600 fi-bxt-dsi fi-bdw-5557u fi-cml-s fi-tgl-u fi-bsw-n3050 fi-byt-j1900 fi-glk-dsi fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-kbl-7560u fi-tgl-y fi-bsw-nick fi-skl-6700k2 fi-kbl-r fi-ilk-m540 fi-ehl-1 fi-tgl-dsi fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-whl-u fi-kbl-x1275 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17862 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17862: 01ef52e818506813a16584526c1365017ca7aefa @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 01ef52e81850 drm/i915/dp: Reset link params on connector disconnect == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17862/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 04:43:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 04:43:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/dp=3A_Include_the_AUX_CH_name_in_the_debug_messages_=28rev2=29?= In-Reply-To: <20200514184040.20700-1-ville.syrjala@linux.intel.com> References: <20200514184040.20700-1-ville.syrjala@linux.intel.com> Message-ID: <159124578075.14555.17918584564922035534@emeril.freedesktop.org> == Series Details == Series: drm/dp: Include the AUX CH name in the debug messages (rev2) URL : https://patchwork.freedesktop.org/series/77276/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17851_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17851_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-write-gtt: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at gem_exec_reloc@basic-write-gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-tglb6/igt at gem_exec_reloc@basic-write-gtt.html * igt at gem_tiled_partial_pwrite_pread@writes-after-reads: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +14 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl3/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk1/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_big_fb@y-tiled-32bpp-rotate-90: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl8/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl7/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl4/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_legacy@cursora-vs-flipb-atomic-transitions: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118] / [i915#95]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk1/igt at kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-glk8/igt at kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#1925] / [i915#1926]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-glk2/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl1/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-glk2/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl1/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-kbl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane@plane-panning-bottom-right-pipe-a-planes: - shard-iclb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt at kms_plane@plane-panning-bottom-right-pipe-a-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-iclb3/igt at kms_plane@plane-panning-bottom-right-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-iclb8/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_setmode@basic: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#31]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl1/igt at kms_setmode@basic.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#93] / [i915#95]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-kbl3/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-tglb: [FAIL][39] ([i915#1930]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb6/igt at gem_exec_reloc@basic-concurrent0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-tglb8/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][41] ([i915#82]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl6/igt at gem_workarounds@suspend-resume-context.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-180: - shard-apl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][47] ([i915#402]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-tglb1/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [FAIL][49] ([i915#72]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-glk1/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][51] ([i915#46]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-kbl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-kbl: [DMESG-WARN][55] ([i915#93] / [i915#95]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_hdr@bpc-switch.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl8/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][59] ([i915#69]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +9 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl5/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-iclb2/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb7/igt at kms_psr@psr2_primary_mmap_cpu.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][69] ([i915#180]) -> [PASS][70] +4 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb8/igt at perf@blocking-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-iclb1/igt at perf@blocking-parameterized.html - shard-tglb: [FAIL][73] ([i915#1542]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-tglb2/igt at perf@blocking-parameterized.html * igt at vgem_basic@dmabuf-mmap: - shard-apl: [DMESG-WARN][75] ([i915#95]) -> [PASS][76] +6 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at vgem_basic@dmabuf-mmap.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl3/igt at vgem_basic@dmabuf-mmap.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][81] ([fdo#110321]) -> [TIMEOUT][82] ([i915#1319] / [i915#1635]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl1/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [DMESG-FAIL][83] ([i915#49] / [i915#95]) -> [FAIL][84] ([i915#49]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17851 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17851: b40213e78a826fd098477aa050e49072f8cc61a5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17851/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 04:50:27 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 04:50:27 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_fix_i915=2Ereset_module_param_type_=28rev2=29?= In-Reply-To: <20200602151126.25626-1-jani.nikula@intel.com> References: <20200602151126.25626-1-jani.nikula@intel.com> Message-ID: <159124622794.14555.11656156799755554915@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: fix i915.reset module param type (rev2) URL : https://patchwork.freedesktop.org/series/77923/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17852_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17852_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk2/igt at gem_exec_whisper@basic-queues-forked-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-glk5/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_color@pipe-a-ctm-0-5.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl10/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl3/igt at kms_cursor_crc@pipe-c-cursor-size-change.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#1925] / [i915#1926]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-glk8/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl5/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-glk8/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#53]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl3/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-iclb8/igt at kms_psr@psr2_primary_page_flip.html * igt at prime_self_import@reimport-vs-gem_close-race: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#95]) +21 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl8/igt at prime_self_import@reimport-vs-gem_close-race.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl4/igt at prime_self_import@reimport-vs-gem_close-race.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][33] ([i915#1930]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl1/igt at gem_workarounds@suspend-resume-context.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-180: - shard-apl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl8/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][41] ([i915#402]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-tglb7/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * igt at kms_cursor_edge_walk@pipe-a-64x64-top-edge: - shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +25 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_cursor_edge_walk@pipe-a-64x64-top-edge.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl3/igt at kms_cursor_edge_walk@pipe-a-64x64-top-edge.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][45] ([i915#46]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-tglb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-tglb2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][49] ([i915#69]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl10/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +9 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl9/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-iclb4/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][57] ([fdo#109642] / [fdo#111068]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb1/igt at kms_psr2_su@frontbuffer.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_dpms: - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb8/igt at kms_psr@psr2_dpms.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-iclb2/igt at kms_psr@psr2_dpms.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62] +5 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-tglb3/igt at perf@blocking-parameterized.html * igt at perf_pmu@rc6-runtime-pm: - shard-glk: [TIMEOUT][65] ([i915#1958]) -> [PASS][66] +3 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at perf_pmu@rc6-runtime-pm.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-glk5/igt at perf_pmu@rc6-runtime-pm.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][67] ([i915#454]) -> [SKIP][68] ([i915#468]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at i915_pm_dc@dc6-psr.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][69] ([i915#1319]) -> [DMESG-FAIL][70] ([fdo#110321] / [i915#95]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at kms_content_protection@atomic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-kbl2/igt at kms_content_protection@atomic.html - shard-apl: [TIMEOUT][71] ([i915#1319] / [i915#1635]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1635]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl3/igt at kms_content_protection@atomic-dpms.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [DMESG-FAIL][75] ([i915#49] / [i915#95]) -> [FAIL][76] ([i915#49]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][77] ([i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#180] / [i915#93] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-glk: [TIMEOUT][79] ([i915#1640] / [i915#1958]) -> [SKIP][80] ([fdo#109271]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at kms_vblank@pipe-d-query-idle-hang.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/shard-glk5/igt at kms_vblank@pipe-d-query-idle-hang.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17852 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17852: 41ac3a8d0f0941f9f86f34672ec72bfa3aaa7e8c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17852/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 04:57:59 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 04:57:59 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/1=5D_drm/mm=3A_add_ig=5Ffrag_selfte?= =?utf-8?q?st?= In-Reply-To: <20200603103223.10443-1-nirmoy.das@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> Message-ID: <159124667906.14555.17005409538215385980@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/1] drm/mm: add ig_frag selftest URL : https://patchwork.freedesktop.org/series/77964/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17856_full ==================================================== Summary ------- **SUCCESS** No regressions found. New tests --------- New tests have been introduced between CI_DRM_8579_full and Patchwork_17856_full: ### New IGT tests (1) ### * igt at drm_mm@all at frag: - Statuses : 7 pass(s) - Exec time: [0.03, 0.07] s Known issues ------------ Here are the changes found in Patchwork_17856_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_eio@in-flight-suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#69]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at gem_eio@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl2/igt at gem_eio@in-flight-suspend.html * igt at gem_mmap_offset@basic-uaf: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +11 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at gem_mmap_offset@basic-uaf.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl1/igt at gem_mmap_offset@basic-uaf.html * igt at gem_mmap_offset@close-race: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#1927] / [i915#58] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk8/igt at gem_mmap_offset@close-race.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-glk4/igt at gem_mmap_offset@close-race.html * igt at i915_module_load@reload: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-tglb2/igt at i915_module_load@reload.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl10/igt at kms_cursor_crc@pipe-c-cursor-size-change.html * igt at kms_cursor_edge_walk@pipe-b-256x256-right-edge: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl6/igt at kms_cursor_edge_walk@pipe-b-256x256-right-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl1/igt at kms_cursor_edge_walk@pipe-b-256x256-right-edge.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1926]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-glk6/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl8/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-glk6/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#53]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl10/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-iclb8/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_setmode@basic: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#31]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl6/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-kbl7/igt at kms_vblank@pipe-c-ts-continuation-suspend.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][39] -> [DMESG-WARN][40] ([i915#93] / [i915#95]) +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-kbl2/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][41] ([i915#1930]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_reloc@basic-concurrent16}: - shard-skl: [FAIL][43] ([i915#1930]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at gem_exec_reloc@basic-concurrent16.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl7/igt at gem_exec_reloc@basic-concurrent16.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][45] ([i915#82]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl3/igt at gem_workarounds@suspend-resume-context.html * igt at i915_suspend@sysfs-reader: - shard-apl: [TIMEOUT][49] ([i915#1635]) -> [PASS][50] +2 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at i915_suspend@sysfs-reader.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl4/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-skl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +5 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl7/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][53] ([i915#402]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-tglb6/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_hdr@bpc-switch.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl3/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][57] ([i915#69]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-iclb5/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb5/igt at kms_psr@psr2_no_drrs.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-iclb2/igt at kms_psr@psr2_no_drrs.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][65] ([i915#180]) -> [PASS][66] +4 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][67] ([i915#1542]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-tglb1/igt at perf@blocking-parameterized.html * igt at vgem_basic@dmabuf-mmap: - shard-apl: [DMESG-WARN][69] ([i915#95]) -> [PASS][70] +11 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at vgem_basic@dmabuf-mmap.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl7/igt at vgem_basic@dmabuf-mmap.html #### Warnings #### * igt at gem_ctx_bad_destroy@invalid-pad: - shard-apl: [TIMEOUT][71] ([i915#1635]) -> [DMESG-WARN][72] ([i915#95]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at gem_ctx_bad_destroy@invalid-pad.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl4/igt at gem_ctx_bad_destroy@invalid-pad.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][75] ([i915#1319]) -> [FAIL][76] ([fdo#110321] / [fdo#110336]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][77] ([fdo#110321]) -> [TIMEOUT][78] ([i915#1319] / [i915#1635]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl2/igt at kms_content_protection@srm.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-apl: [TIMEOUT][79] ([i915#1635] / [i915#1640]) -> [SKIP][80] ([fdo#109271]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at kms_vblank@pipe-d-query-idle-hang.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/shard-apl4/igt at kms_vblank@pipe-d-query-idle-hang.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17856 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17856: 3560e47537d1185a5d719e8abc8dc0eb5a4289d2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17856/index.html From vidya.srinivas at intel.com Thu Jun 4 05:03:48 2020 From: vidya.srinivas at intel.com (Vidya Srinivas) Date: Thu, 4 Jun 2020 10:33:48 +0530 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL Message-ID: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 40 ++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7223367171d1..44663e8ac9a1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value, trans_ddi_port_mask; + enum port port = intel_dig_port->base.port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_PORT_MASK); + trans_ddi_port_mask); trans_conf_value &= ~PIPECONF_ENABLE; dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); } static void @@ -5497,20 +5507,28 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) enum port port = intel_dig_port->base.port; struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value, trans_ddi_sel_port; + i915_reg_t dp_tp_reg; + + if (IS_ELKHARTLAKE(dev_priv)) { + dp_tp_reg = DP_TP_CTL(port); + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); + } else if (IS_TIGERLAKE(dev_priv)) { + dp_tp_reg = TGL_DP_TP_CTL(pipe); + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); + } trans_ddi_func_ctl_value = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); - trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | - TGL_TRANS_DDI_SELECT_PORT(port); + trans_ddi_sel_port; trans_conf_value |= PIPECONF_ENABLE; dp_tp_ctl_value |= DP_TP_CTL_ENABLE; intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), trans_ddi_func_ctl_value); } @@ -5557,6 +5575,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) static void intel_dp_handle_test_request(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *dev_priv = i915; u8 response = DP_TEST_NAK; u8 request = 0; int status; @@ -5582,6 +5601,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: + if (!IS_ELKHARTLAKE(dev_priv) || !IS_TIGERLAKE(dev_priv)) { + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); + return; + } drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; -- 2.7.4 From patchwork at emeril.freedesktop.org Thu Jun 4 05:34:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 05:34:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/dp=3A_DP_PHY_compliance_for_JSL?= In-Reply-To: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> Message-ID: <159124889191.14553.13020502131747172550@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp: DP PHY compliance for JSL URL : https://patchwork.freedesktop.org/series/77977/ State : warning == Summary == $ dim checkpatch origin/drm-tip ce289f0dd8a5 drm/i915/dp: DP PHY compliance for JSL -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one -:97: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #97: FILE: drivers/gpu/drm/i915/display/intel_dp.c:5561: + drm_dbg_kms(&i915->drm, + "PHY compliance for platform not supported\n"); total: 0 errors, 1 warnings, 1 checks, 86 lines checked From patchwork at emeril.freedesktop.org Thu Jun 4 05:56:01 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 05:56:01 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/dp=3A_DP_PHY_compliance_for_JSL?= In-Reply-To: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> Message-ID: <159125016169.14552.14848988374615548114@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp: DP PHY compliance for JSL URL : https://patchwork.freedesktop.org/series/77977/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579 -> Patchwork_17863 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/index.html Known issues ------------ Here are the changes found in Patchwork_17863 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-byt-n2820/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/fi-byt-n2820/igt at i915_module_load@reload.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1}: - fi-bwr-2160: [FAIL][3] ([i915#1928]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/fi-bwr-2160/igt at kms_flip@basic-flip-vs-wf_vblank at b-dvi-d1.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92]) -> [DMESG-WARN][6] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#62] / [i915#92]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-bdw-gvtdvm fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17863 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17863: ce289f0dd8a55b4539309ed6a20bcd48ff88f449 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ce289f0dd8a5 drm/i915/dp: DP PHY compliance for JSL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 06:36:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 06:36:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/3=5D_drm/i915/bios=3A_Parse_HOBL_pa?= =?utf-8?q?rameter?= In-Reply-To: <20200603194308.78622-1-jose.souza@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> Message-ID: <159125257885.14555.18367232604158003051@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/3] drm/i915/bios: Parse HOBL parameter URL : https://patchwork.freedesktop.org/series/77966/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17857_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17857_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_mmap_offset@basic-uaf: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at gem_mmap_offset@basic-uaf.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl1/igt at gem_mmap_offset@basic-uaf.html * igt at i915_module_load@reload: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl7/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html * igt at kms_big_fb@y-tiled-32bpp-rotate-90: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl2/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html * igt at kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl1/igt at kms_cursor_crc@pipe-c-cursor-size-change.html * igt at kms_cursor_legacy@all-pipes-torture-bo: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#128]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_cursor_legacy@all-pipes-torture-bo.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-kbl1/igt at kms_cursor_legacy@all-pipes-torture-bo.html - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#128]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb8/igt at kms_cursor_legacy@all-pipes-torture-bo.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-tglb2/igt at kms_cursor_legacy@all-pipes-torture-bo.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#1925] / [i915#1926]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-glk8/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl6/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-glk9/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#53]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl1/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-iclb7/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_setmode@basic: - shard-apl: [PASS][33] -> [FAIL][34] ([i915#31]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl4/igt at kms_setmode@basic.html * igt at prime_mmap_coherency@write: - shard-glk: [PASS][35] -> [DMESG-WARN][36] ([i915#118] / [i915#95]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at prime_mmap_coherency@write.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-glk1/igt at prime_mmap_coherency@write.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#93] / [i915#95]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][39] ([i915#1930]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_sync@basic-many-each: - shard-kbl: [DMESG-WARN][41] ([i915#93] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at gem_sync@basic-many-each.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-kbl3/igt at gem_sync@basic-many-each.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl8/igt at gem_workarounds@suspend-resume-context.html * igt at kms_big_fb@y-tiled-8bpp-rotate-0: - shard-apl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl4/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][47] ([i915#402]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-tglb1/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][49] ([i915#46]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-tglb3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_hdr@bpc-switch.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl7/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +9 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-skl1/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-iclb1/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][59] ([fdo#109642] / [fdo#111068]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb1/igt at kms_psr2_su@page_flip.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_psr@psr2_sprite_mmap_gtt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +4 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][65] ([i915#1542]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb8/igt at perf@blocking-parameterized.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-iclb4/igt at perf@blocking-parameterized.html - shard-tglb: [FAIL][67] ([i915#1542]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-tglb6/igt at perf@blocking-parameterized.html * igt at perf_pmu@rc6-runtime-pm: - shard-glk: [TIMEOUT][69] ([i915#1958]) -> [PASS][70] +3 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at perf_pmu@rc6-runtime-pm.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-glk9/igt at perf_pmu@rc6-runtime-pm.html * igt at vgem_basic@dmabuf-mmap: - shard-apl: [DMESG-WARN][71] ([i915#95]) -> [PASS][72] +17 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at vgem_basic@dmabuf-mmap.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl4/igt at vgem_basic@dmabuf-mmap.html #### Warnings #### * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1635]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][75] ([i915#1319] / [i915#1635]) -> [FAIL][76] ([fdo#110321]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@lic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [DMESG-FAIL][77] ([i915#49] / [i915#95]) -> [FAIL][78] ([i915#49]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-glk: [TIMEOUT][79] ([i915#1640] / [i915#1958]) -> [SKIP][80] ([fdo#109271]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at kms_vblank@pipe-d-query-idle-hang.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/shard-glk9/igt at kms_vblank@pipe-d-query-idle-hang.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17857 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17857: e333b5ede9369eb28a775ce63e45def78b64d4a3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17857/index.html From daniel at ffwll.ch Thu Jun 4 08:05:07 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:05:07 +0200 Subject: [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny In-Reply-To: <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-54-daniel.vetter@ffwll.ch> <20200415094512.GA30444@ravnborg.org> <MWHPR12MB14532DA5713E3B579ABFE1F4A1DB0@MWHPR12MB1453.namprd12.prod.outlook.com> <CAKMK7uGDGgt8Cm_bFoyzeoP2CWyiUNdUwb7GL6Ohu3k0rP0p1w@mail.gmail.com> <20200428140842.GL3456981@phenom.ffwll.local> <CH2PR12MB3894B40C6D71435D3E759A34A1A20@CH2PR12MB3894.namprd12.prod.outlook.com> <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com> Message-ID: <20200604080507.GT20149@phenom.ffwll.local> On Fri, May 08, 2020 at 08:07:41PM +0200, Daniel Vetter wrote: > On Fri, May 8, 2020 at 3:56 PM Alexey Brodkin > <Alexey.Brodkin at synopsys.com> wrote: > > > > Hi Daniel, > > > > > > Looking at this patch series, feels a bit like hand-rolling of bridge > > > > code, badly. We should get away from that. > > > > > > > > Once you have that I think the end result is tiny enough that it can > > > > stay, bridges intergrate quite well into simple display pipe drivers. > > > > > > > > > BTW should I pull that series in my tree and send you a pull-request > > > > > or that kind of change needs to go through another tree? > > > > > > > > > > Also I'd like to test the change we discuss here to make sure stuff > > > > > still works. Once we do that I'll send an update. Any hint on > > > > > when that change needs to be acked/nacked? > > > > > > > > Simplest is if this can all land through drm-misc, is arc not > > > > maintained in there? And there's plenty of time for testing, I'm just > > > > slowly crawling through the tree to get everything polished and > > > > cleaned up in this area. > > > > > > Any updates on testing this pile here? First patch landed now, and I've > > > started to push driver patches. So would be good to get this sorted out > > > too. > > > > Sorry we're in the middle of 2 long weekends so missed this one. > > I guess we'll be able to test it in a week or two from now. > > > > Is that OK? > > This aren't high-priority, so totally ok. As long as you don't land a > driver rewrite and I have to rebase everything :-) Ping for a bit of testing on this stuff ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From daniel.vetter at ffwll.ch Thu Jun 4 08:12:06 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:06 +0200 Subject: [Intel-gfx] [PATCH 00/18] dma-fence lockdep annotations, round 2 Message-ID: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Hi all, Still very much early stuff, still very much looking for initial thoughts and maybe some ideas how this could all be rolled out across drivers. Full intro probably best from the RFC cover letter: https://lore.kernel.org/amd-gfx/20200512085944.222637-1-daniel.vetter at ffwll.ch/ Changes since last time around: - might_sleep annotation has landed already, I split that out as a stand-alone - now with an mm patch to improve direct reclaim annotations for mmu notifiers. This allows us to very easily catch issues in that area, no more need for exaustive testing and luck to make sure we're not leaving a GFP_NOFS or GPF_NOIO around which should be a GFP_ATOMIC - kerneldoc that explains all the reasoning behind the annotations and priming, hopefully Driver patches still largely just meant as examples to illustrate usage, but from various irc chats I think discussing them is really useful to gain clarity on the exact places the annotations should be put. Cheers, Daniel Daniel Vetter (18): mm: Track mmu notifiers in fs_reclaim_acquire/release dma-buf: minor doc touch-ups dma-fence: basic lockdep annotations dma-fence: prime lockdep annotations drm/vkms: Annotate vblank timer drm/vblank: Annotate with dma-fence signalling section drm/atomic-helper: Add dma-fence annotations drm/amdgpu: add dma-fence annotations to atomic commit path drm/scheduler: use dma-fence annotations in main thread drm/amdgpu: use dma-fence annotations in cs_submit() drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code drm/amdgpu: DC also loves to allocate stuff where it shouldn't drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail drm/scheduler: use dma-fence annotations in tdr work drm/amdgpu: use dma-fence annotations for gpu reset code Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" drm/amdgpu: gpu recovery does full modesets drm/i915: Annotate dma_fence_work Documentation/driver-api/dma-buf.rst | 18 +- drivers/dma-buf/dma-buf.c | 6 +- drivers/dma-buf/dma-fence.c | 202 ++++++++++++++++++ drivers/dma-buf/dma-resv.c | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 +- drivers/gpu/drm/amd/amdgpu/atom.c | 2 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/drm_atomic_helper.c | 16 ++ drivers/gpu/drm/drm_vblank.c | 8 +- drivers/gpu/drm/i915/i915_sw_fence_work.c | 3 + drivers/gpu/drm/scheduler/sched_main.c | 11 + drivers/gpu/drm/vkms/vkms_crtc.c | 8 +- include/linux/dma-fence.h | 13 ++ mm/mmu_notifier.c | 7 - mm/page_alloc.c | 23 +- 20 files changed, 341 insertions(+), 35 deletions(-) -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:07 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:07 +0200 Subject: [Intel-gfx] [PATCH 01/18] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-2-daniel.vetter@ffwll.ch> fs_reclaim_acquire/release nicely catch recursion issues when allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend to use to keep the excessive caches in check). For mmu notifier recursions we do have lockdep annotations since 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). But these only fire if a path actually results in some pte invalidation - for most small allocations that's very rarely the case. The other trouble is that pte invalidation can happen any time when __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe choice, GFP_NOIO isn't good enough to avoid potential mmu notifier recursion. I was pondering whether we should just do the general annotation, but there's always the risk for false positives. Plus I'm assuming that the core fs and io code is a lot better reviewed and tested than random mmu notifier code in drivers. Hence why I decide to only annotate for that specific case. Furthermore even if we'd create a lockdep map for direct reclaim, we'd still need to explicit pull in the mmu notifier map - there's a lot more places that do pte invalidation than just direct reclaim, these two contexts arent the same. Note that the mmu notifiers needing their own independent lockdep map is also the reason we can't hold them from fs_reclaim_acquire to fs_reclaim_release - it would nest with the acquistion in the pte invalidation code, causing a lockdep splat. And we can't remove the annotations from pte invalidation and all the other places since they're called from many other places than page reclaim. Hence we can only do the equivalent of might_lock, but on the raw lockdep map. With this we can also remove the lockdep priming added in 66204f1d2d1b ("mm/mmu_notifiers: prime lockdep") since the new annotations are strictly more powerful. Cc: Andrew Morton <akpm at linux-foundation.org> Cc: Jason Gunthorpe <jgg at mellanox.com> Cc: linux-mm at kvack.org Cc: linux-rdma at vger.kernel.org Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- This is part of a gpu lockdep annotation series simply because it really helps to catch issues where gpu subsystem locks and primitives can deadlock with themselves through allocations and mmu notifiers. But aside from that motivation it should be completely free-standing, and can land through -mm/-rdma/-hmm or any other tree really whenever. -Daniel --- mm/mmu_notifier.c | 7 ------- mm/page_alloc.c | 23 ++++++++++++++--------- 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c index 06852b896fa6..5d578b9122f8 100644 --- a/mm/mmu_notifier.c +++ b/mm/mmu_notifier.c @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, lockdep_assert_held_write(&mm->mmap_sem); BUG_ON(atomic_read(&mm->mm_users) <= 0); - if (IS_ENABLED(CONFIG_LOCKDEP)) { - fs_reclaim_acquire(GFP_KERNEL); - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); - lock_map_release(&__mmu_notifier_invalidate_range_start_map); - fs_reclaim_release(GFP_KERNEL); - } - if (!mm->notifier_subscriptions) { /* * kmalloc cannot be called under mm_take_all_locks(), but we diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 13cc653122b7..f8a222db4a53 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -57,6 +57,7 @@ #include <trace/events/oom.h> #include <linux/prefetch.h> #include <linux/mm_inline.h> +#include <linux/mmu_notifier.h> #include <linux/migrate.h> #include <linux/hugetlb.h> #include <linux/sched/rt.h> @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla static struct lockdep_map __fs_reclaim_map = STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); -static bool __need_fs_reclaim(gfp_t gfp_mask) +static bool __need_reclaim(gfp_t gfp_mask) { gfp_mask = current_gfp_context(gfp_mask); @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) if (current->flags & PF_MEMALLOC) return false; - /* We're only interested __GFP_FS allocations for now */ - if (!(gfp_mask & __GFP_FS)) - return false; - if (gfp_mask & __GFP_NOLOCKDEP) return false; @@ -4158,15 +4155,23 @@ void __fs_reclaim_release(void) void fs_reclaim_acquire(gfp_t gfp_mask) { - if (__need_fs_reclaim(gfp_mask)) - __fs_reclaim_acquire(); + if (__need_reclaim(gfp_mask)) { + if (!(gfp_mask & __GFP_FS)) + __fs_reclaim_acquire(); + + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); + + } } EXPORT_SYMBOL_GPL(fs_reclaim_acquire); void fs_reclaim_release(gfp_t gfp_mask) { - if (__need_fs_reclaim(gfp_mask)) - __fs_reclaim_release(); + if (__need_reclaim(gfp_mask)) { + if (!(gfp_mask & __GFP_FS)) + __fs_reclaim_release(); + } } EXPORT_SYMBOL_GPL(fs_reclaim_release); #endif -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:08 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:08 +0200 Subject: [Intel-gfx] [PATCH 02/18] dma-buf: minor doc touch-ups In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-3-daniel.vetter@ffwll.ch> Just some tiny edits: - fix link to struct dma_fence - give slightly more meaningful title - the polling here is about implicit fences, explicit fences (in sync_file or drm_syncobj) also have their own polling Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/dma-buf/dma-buf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 01ce125f8e8d..e018ef80451e 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -161,11 +161,11 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) } /** - * DOC: fence polling + * DOC: implicit fence polling * * To support cross-device and cross-driver synchronization of buffer access - * implicit fences (represented internally in the kernel with &struct fence) can - * be attached to a &dma_buf. The glue for that and a few related things are + * implicit fences (represented internally in the kernel with &struct dma_fence) + * can be attached to a &dma_buf. The glue for that and a few related things are * provided in the &dma_resv structure. * * Userspace can query the state of these implicitly tracked fences using poll() -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:09 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:09 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-4-daniel.vetter@ffwll.ch> Design is similar to the lockdep annotations for workers, but with some twists: - We use a read-lock for the execution/worker/completion side, so that this explicit annotation can be more liberally sprinkled around. With read locks lockdep isn't going to complain if the read-side isn't nested the same way under all circumstances, so ABBA deadlocks are ok. Which they are, since this is an annotation only. - We're using non-recursive lockdep read lock mode, since in recursive read lock mode lockdep does not catch read side hazards. And we _very_ much want read side hazards to be caught. For full details of this limitation see commit e91498589746065e3ae95d9a00b068e525eec34f Author: Peter Zijlstra <peterz at infradead.org> Date: Wed Aug 23 13:13:11 2017 +0200 locking/lockdep/selftests: Add mixed read-write ABBA tests - To allow nesting of the read-side explicit annotations we explicitly keep track of the nesting. lock_is_held() allows us to do that. - The wait-side annotation is a write lock, and entirely done within dma_fence_wait() for everyone by default. - To be able to freely annotate helper functions I want to make it ok to call dma_fence_begin/end_signalling from soft/hardirq context. First attempt was using the hardirq locking context for the write side in lockdep, but this forces all normal spinlocks nested within dma_fence_begin/end_signalling to be spinlocks. That bollocks. The approach now is to simple check in_atomic(), and for these cases entirely rely on the might_sleep() check in dma_fence_wait(). That will catch any wrong nesting against spinlocks from soft/hardirq contexts. The idea here is that every code path that's critical for eventually signalling a dma_fence should be annotated with dma_fence_begin/end_signalling. The annotation ideally starts right after a dma_fence is published (added to a dma_resv, exposed as a sync_file fd, attached to a drm_syncobj fd, or anything else that makes the dma_fence visible to other kernel threads), up to and including the dma_fence_wait(). Examples are irq handlers, the scheduler rt threads, the tail of execbuf (after the corresponding fences are visible), any workers that end up signalling dma_fences and really anything else. Not annotated should be code paths that only complete fences opportunistically as the gpu progresses, like e.g. shrinker/eviction code. The main class of deadlocks this is supposed to catch are: Thread A: mutex_lock(A); mutex_unlock(A); dma_fence_signal(); Thread B: mutex_lock(A); dma_fence_wait(); mutex_unlock(A); Thread B is blocked on A signalling the fence, but A never gets around to that because it cannot acquire the lock A. Note that dma_fence_wait() is allowed to be nested within dma_fence_begin/end_signalling sections. To allow this to happen the read lock needs to be upgraded to a write lock, which means that any other lock is acquired between the dma_fence_begin_signalling() call and the call to dma_fence_wait(), and still held, this will result in an immediate lockdep complaint. The only other option would be to not annotate such calls, defeating the point. Therefore these annotations cannot be sprinkled over the code entirely mindless to avoid false positives. v2: handle soft/hardirq ctx better against write side and dont forget EXPORT_SYMBOL, drivers can't use this otherwise. v3: Kerneldoc. v4: Some spelling fixes from Mika Cc: Mika Kuoppala <mika.kuoppala at intel.com> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- Documentation/driver-api/dma-buf.rst | 12 +- drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ include/linux/dma-fence.h | 12 ++ 3 files changed, 182 insertions(+), 3 deletions(-) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 63dec76d1d8d..05d856131140 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects .. kernel-doc:: drivers/dma-buf/dma-buf.c :doc: cpu access -Fence Poll Support -~~~~~~~~~~~~~~~~~~ +Implicit Fence Poll Support +~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. kernel-doc:: drivers/dma-buf/dma-buf.c - :doc: fence polling + :doc: implicit fence polling Kernel Functions and Structures Reference ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -133,6 +133,12 @@ DMA Fences .. kernel-doc:: drivers/dma-buf/dma-fence.c :doc: DMA fences overview +DMA Fence Signalling Annotations +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence.c + :doc: fence signalling annotation + DMA Fences Functions Reference ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 656e9ac2d028..0005bc002529 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) } EXPORT_SYMBOL(dma_fence_context_alloc); +/** + * DOC: fence signalling annotation + * + * Proving correctness of all the kernel code around &dma_fence through code + * review and testing is tricky for a few reasons: + * + * * It is a cross-driver contract, and therefore all drivers must follow the + * same rules for lock nesting order, calling contexts for various functions + * and anything else significant for in-kernel interfaces. But it is also + * impossible to test all drivers in a single machine, hence brute-force N vs. + * N testing of all combinations is impossible. Even just limiting to the + * possible combinations is infeasible. + * + * * There is an enormous amount of driver code involved. For render drivers + * there's the tail of command submission, after fences are published, + * scheduler code, interrupt and workers to process job completion, + * and timeout, gpu reset and gpu hang recovery code. Plus for integration + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, + * and &shrinker. For modesetting drivers there's the commit tail functions + * between when fences for an atomic modeset are published, and when the + * corresponding vblank completes, including any interrupt processing and + * related workers. Auditing all that code, across all drivers, is not + * feasible. + * + * * Due to how many other subsystems are involved and the locking hierarchies + * this pulls in there is extremely thin wiggle-room for driver-specific + * differences. &dma_fence interacts with almost all of the core memory + * handling through page fault handlers via &dma_resv, dma_resv_lock() and + * dma_resv_unlock(). On the other side it also interacts through all + * allocation sites through &mmu_notifier and &shrinker. + * + * Furthermore lockdep does not handle cross-release dependencies, which means + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught + * at runtime with some quick testing. The simplest example is one thread + * waiting on a &dma_fence while holding a lock:: + * + * lock(A); + * dma_fence_wait(B); + * unlock(A); + * + * while the other thread is stuck trying to acquire the same lock, which + * prevents it from signalling the fence the previous thread is stuck waiting + * on:: + * + * lock(A); + * unlock(A); + * dma_fence_signal(B); + * + * By manually annotating all code relevant to signalling a &dma_fence we can + * teach lockdep about these dependencies, which also helps with the validation + * headache since now lockdep can check all the rules for us:: + * + * cookie = dma_fence_begin_signalling(); + * lock(A); + * unlock(A); + * dma_fence_signal(B); + * dma_fence_end_signalling(cookie); + * + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to + * annotate critical sections the following rules need to be observed: + * + * * All code necessary to complete a &dma_fence must be annotated, from the + * point where a fence is accessible to other threads, to the point where + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, + * and due to the very strict rules and many corner cases it is infeasible to + * catch these just with review or normal stress testing. + * + * * &struct dma_resv deserves a special note, since the readers are only + * protected by rcu. This means the signalling critical section starts as soon + * as the new fences are installed, even before dma_resv_unlock() is called. + * + * * The only exception are fast paths and opportunistic signalling code, which + * calls dma_fence_signal() purely as an optimization, but is not required to + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL + * which calls dma_fence_signal(), while the mandatory completion path goes + * through a hardware interrupt and possible job completion worker. + * + * * To aid composability of code, the annotations can be freely nested, as long + * as the overall locking hierarchy is consistent. The annotations also work + * both in interrupt and process context. Due to implementation details this + * requires that callers pass an opaque cookie from + * dma_fence_begin_signalling() to dma_fence_end_signalling(). + * + * * Validation against the cross driver contract is implemented by priming + * lockdep with the relevant hierarchy at boot-up. This means even just + * testing with a single device is enough to validate a driver, at least as + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are + * concerned. + */ +#ifdef CONFIG_LOCKDEP +struct lockdep_map dma_fence_lockdep_map = { + .name = "dma_fence_map" +}; + +/** + * dma_fence_begin_signalling - begin a critical DMA fence signalling section + * + * Drivers should use this to annotate the beginning of any code section + * required to eventually complete &dma_fence by calling dma_fence_signal(). + * + * The end of these critical sections are annotated with + * dma_fence_end_signalling(). + * + * Returns: + * + * Opaque cookie needed by the implementation, which needs to be passed to + * dma_fence_end_signalling(). + */ +bool dma_fence_begin_signalling(void) +{ + /* explicitly nesting ... */ + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) + return true; + + /* rely on might_sleep check for soft/hardirq locks */ + if (in_atomic()) + return true; + + /* ... and non-recursive readlock */ + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); + + return false; +} +EXPORT_SYMBOL(dma_fence_begin_signalling); + +/** + * dma_fence_end_signalling - end a critical DMA fence signalling section + * + * Closes a critical section annotation opened by dma_fence_begin_signalling(). + */ +void dma_fence_end_signalling(bool cookie) +{ + if (cookie) + return; + + lock_release(&dma_fence_lockdep_map, _RET_IP_); +} +EXPORT_SYMBOL(dma_fence_end_signalling); + +void __dma_fence_might_wait(void) +{ + bool tmp; + + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); + if (tmp) + lock_release(&dma_fence_lockdep_map, _THIS_IP_); + lock_map_acquire(&dma_fence_lockdep_map); + lock_map_release(&dma_fence_lockdep_map); + if (tmp) + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); +} +#endif + + /** * dma_fence_signal_locked - signal completion of a fence * @fence: the fence to signal @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) { unsigned long flags; int ret; + bool tmp; if (!fence) return -EINVAL; + tmp = dma_fence_begin_signalling(); + spin_lock_irqsave(fence->lock, flags); ret = dma_fence_signal_locked(fence); spin_unlock_irqrestore(fence->lock, flags); + dma_fence_end_signalling(tmp); + return ret; } EXPORT_SYMBOL(dma_fence_signal); @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) might_sleep(); + __dma_fence_might_wait(); + trace_dma_fence_wait_start(fence); if (fence->ops->wait) ret = fence->ops->wait(fence, intr, timeout); diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 3347c54f3a87..3f288f7db2ef 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) } while (1); } +#ifdef CONFIG_LOCKDEP +bool dma_fence_begin_signalling(void); +void dma_fence_end_signalling(bool cookie); +#else +static inline bool dma_fence_begin_signalling(void) +{ + return true; +} +static inline void dma_fence_end_signalling(bool cookie) {} +static inline void __dma_fence_might_wait(void) {} +#endif + int dma_fence_signal(struct dma_fence *fence); int dma_fence_signal_locked(struct dma_fence *fence); signed long dma_fence_default_wait(struct dma_fence *fence, -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:10 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:10 +0200 Subject: [Intel-gfx] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-5-daniel.vetter@ffwll.ch> Two in one go: - it is allowed to call dma_fence_wait() while holding a dma_resv_lock(). This is fundamental to how eviction works with ttm, so required. - it is allowed to call dma_fence_wait() from memory reclaim contexts, specifically from shrinker callbacks (which i915 does), and from mmu notifier callbacks (which amdgpu does, and which i915 sometimes also does, and probably always should, but that's kinda a debate). Also for stuff like HMM we really need to be able to do this, or things get real dicey. Consequence is that any critical path necessary to get to a dma_fence_signal for a fence must never a) call dma_resv_lock nor b) allocate memory with GFP_KERNEL. Also by implication of dma_resv_lock(), no userspace faulting allowed. That's some supremely obnoxious limitations, which is why we need to sprinkle the right annotations to all relevant paths. The one big locking context we're leaving out here is mmu notifiers, added in commit 23b68395c7c78a764e8963fc15a7cfd318bf187f Author: Daniel Vetter <daniel.vetter at ffwll.ch> Date: Mon Aug 26 22:14:21 2019 +0200 mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end that one covers a lot of other callsites, and it's also allowed to wait on dma-fences from mmu notifiers. But there's no ready-made functions exposed to prime this, so I've left it out for now. v2: Also track against mmu notifier context. v3: kerneldoc to spec the cross-driver contract. Note that currently i915 throws in a hard-coded 10s timeout on foreign fences (not sure why that was done, but it's there), which is why that rule is worded with SHOULD instead of MUST. Also some of the mmu_notifier/shrinker rules might surprise SoC drivers, I haven't fully audited them all. Which is infeasible anyway, we'll need to run them with lockdep and dma-fence annotations and see what goes boom. v4: A spelling fix from Mika Cc: Mika Kuoppala <mika.kuoppala at intel.com> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- Documentation/driver-api/dma-buf.rst | 6 ++++ drivers/dma-buf/dma-fence.c | 41 ++++++++++++++++++++++++++++ drivers/dma-buf/dma-resv.c | 4 +++ include/linux/dma-fence.h | 1 + 4 files changed, 52 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 05d856131140..f8f6decde359 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -133,6 +133,12 @@ DMA Fences .. kernel-doc:: drivers/dma-buf/dma-fence.c :doc: DMA fences overview +DMA Fence Cross-Driver Contract +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence.c + :doc: fence cross-driver contract + DMA Fence Signalling Annotations ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 0005bc002529..754e6fb84fb7 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -64,6 +64,47 @@ static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(1); * &dma_buf.resv pointer. */ +/** + * DOC: fence cross-driver contract + * + * Since &dma_fence provide a cross driver contract, all drivers must follow the + * same rules: + * + * * Fences must complete in a reasonable time. Fences which represent kernels + * and shaders submitted by userspace, which could run forever, must be backed + * up by timeout and gpu hang recovery code. Minimally that code must prevent + * further command submission and force complete all in-flight fences, e.g. + * when the driver or hardware do not support gpu reset, or if the gpu reset + * failed for some reason. Ideally the driver supports gpu recovery which only + * affects the offending userspace context, and no other userspace + * submissions. + * + * * Drivers may have different ideas of what completion within a reasonable + * time means. Some hang recovery code uses a fixed timeout, others a mix + * between observing forward progress and increasingly strict timeouts. + * Drivers should not try to second guess timeout handling of fences from + * other drivers. + * + * * To ensure there's no deadlocks of dma_fence_wait() against other locks + * drivers should annotate all code required to reach dma_fence_signal(), + * which completes the fences, with dma_fence_begin_signalling() and + * dma_fence_end_signalling(). + * + * * Drivers are allowed to call dma_fence_wait() while holding dma_resv_lock(). + * This means any code required for fence completion cannot acquire a + * &dma_resv lock. Note that this also pulls in the entire established + * locking hierarchy around dma_resv_lock() and dma_resv_unlock(). + * + * * Drivers are allowed to call dma_fence_wait() from their &shrinker + * callbacks. This means any code required for fence completion cannot + * allocate memory with GFP_KERNEL. + * + * * Drivers are allowed to call dma_fence_wait() from their &mmu_notifier + * respectively &mmu_interval_notifier callbacks. This means any code required + * for fence completeion cannot allocate memory with GFP_NOFS or GFP_NOIO. + * Only GFP_ATOMIC is permissible, which might fail. + */ + static const char *dma_fence_stub_get_name(struct dma_fence *fence) { return "stub"; diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 99c0a33c918d..c223f32425c4 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -35,6 +35,7 @@ #include <linux/dma-resv.h> #include <linux/export.h> #include <linux/sched/mm.h> +#include <linux/mmu_notifier.h> /** * DOC: Reservation Object Overview @@ -115,6 +116,9 @@ static int __init dma_resv_lockdep(void) if (ret == -EDEADLK) dma_resv_lock_slow(&obj, &ctx); fs_reclaim_acquire(GFP_KERNEL); + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + __dma_fence_might_wait(); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); fs_reclaim_release(GFP_KERNEL); ww_mutex_unlock(&obj.lock); ww_acquire_fini(&ctx); diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 3f288f7db2ef..09e23adb351d 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -360,6 +360,7 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) #ifdef CONFIG_LOCKDEP bool dma_fence_begin_signalling(void); void dma_fence_end_signalling(bool cookie); +void __dma_fence_might_wait(void); #else static inline bool dma_fence_begin_signalling(void) { -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:11 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:11 +0200 Subject: [Intel-gfx] [PATCH 05/18] drm/vkms: Annotate vblank timer In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-6-daniel.vetter@ffwll.ch> This is needed to signal the fences from page flips, annotate it accordingly. We need to annotate entire timer callback since if we get stuck anywhere in there, then the timer stops, and hence fences stop. Just annotating the top part that does the vblank handling isn't enough. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: Rodrigo Siqueira <rodrigosiqueiramelo at gmail.com> Cc: Haneen Mohammed <hamohammed.sa at gmail.com> Cc: Daniel Vetter <daniel at ffwll.ch> --- drivers/gpu/drm/vkms/vkms_crtc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_crtc.c index ac85e17428f8..a53a40848a72 100644 --- a/drivers/gpu/drm/vkms/vkms_crtc.c +++ b/drivers/gpu/drm/vkms/vkms_crtc.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <linux/dma-fence.h> + #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_probe_helper.h> @@ -14,7 +16,9 @@ static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) struct drm_crtc *crtc = &output->crtc; struct vkms_crtc_state *state; u64 ret_overrun; - bool ret; + bool ret, fence_cookie; + + fence_cookie = dma_fence_begin_signalling(); ret_overrun = hrtimer_forward_now(&output->vblank_hrtimer, output->period_ns); @@ -49,6 +53,8 @@ static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) DRM_DEBUG_DRIVER("Composer worker already queued\n"); } + dma_fence_end_signalling(fence_cookie); + return HRTIMER_RESTART; } -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:12 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:12 +0200 Subject: [Intel-gfx] [PATCH 06/18] drm/vblank: Annotate with dma-fence signalling section In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-7-daniel.vetter@ffwll.ch> This is rather overkill since currently all drivers call this from hardirq (or at least timers). But maybe in the future we're going to have thread irq handlers and what not, doesn't hurt to be prepared. Plus this is an easy start for sprinkling these fence annotations into shared code. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/drm_vblank.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index 85e5f2db1608..93a5bba5f665 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -24,6 +24,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <linux/dma-fence.h> #include <linux/export.h> #include <linux/moduleparam.h> @@ -1908,7 +1909,7 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; unsigned long irqflags; - bool disable_irq; + bool disable_irq, fence_cookie; if (drm_WARN_ON_ONCE(dev, !drm_dev_has_vblank(dev))) return false; @@ -1916,6 +1917,8 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe) if (drm_WARN_ON(dev, pipe >= dev->num_crtcs)) return false; + fence_cookie = dma_fence_begin_signalling(); + spin_lock_irqsave(&dev->event_lock, irqflags); /* Need timestamp lock to prevent concurrent execution with @@ -1928,6 +1931,7 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe) if (!vblank->enabled) { spin_unlock(&dev->vblank_time_lock); spin_unlock_irqrestore(&dev->event_lock, irqflags); + dma_fence_end_signalling(fence_cookie); return false; } @@ -1953,6 +1957,8 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe) if (disable_irq) vblank_disable_fn(&vblank->disable_timer); + dma_fence_end_signalling(fence_cookie); + return true; } EXPORT_SYMBOL(drm_handle_vblank); -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:13 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:13 +0200 Subject: [Intel-gfx] [PATCH 07/18] drm/atomic-helper: Add dma-fence annotations In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-8-daniel.vetter@ffwll.ch> This is a bit disappointing since we need to split the annotations over all the different parts. I was considering just leaking the critical section into the ->atomic_commit_tail callback of each driver. But that would mean we need to pass the fence_cookie into each driver (there's a total of 13 implementations of this hook right now), so bad flag day. And also a bit leaky abstraction. Hence just do it function-by-function. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/drm_atomic_helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 7cd7fe0d57b4..bfcc7857a9a1 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1549,6 +1549,7 @@ EXPORT_SYMBOL(drm_atomic_helper_wait_for_flip_done); void drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state) { struct drm_device *dev = old_state->dev; + bool fence_cookie = dma_fence_begin_signalling(); drm_atomic_helper_commit_modeset_disables(dev, old_state); @@ -1560,6 +1561,8 @@ void drm_atomic_helper_commit_tail(struct drm_atomic_state *old_state) drm_atomic_helper_commit_hw_done(old_state); + dma_fence_end_signalling(fence_cookie); + drm_atomic_helper_wait_for_vblanks(dev, old_state); drm_atomic_helper_cleanup_planes(dev, old_state); @@ -1579,6 +1582,7 @@ EXPORT_SYMBOL(drm_atomic_helper_commit_tail); void drm_atomic_helper_commit_tail_rpm(struct drm_atomic_state *old_state) { struct drm_device *dev = old_state->dev; + bool fence_cookie = dma_fence_begin_signalling(); drm_atomic_helper_commit_modeset_disables(dev, old_state); @@ -1591,6 +1595,8 @@ void drm_atomic_helper_commit_tail_rpm(struct drm_atomic_state *old_state) drm_atomic_helper_commit_hw_done(old_state); + dma_fence_end_signalling(fence_cookie); + drm_atomic_helper_wait_for_vblanks(dev, old_state); drm_atomic_helper_cleanup_planes(dev, old_state); @@ -1606,6 +1612,9 @@ static void commit_tail(struct drm_atomic_state *old_state) ktime_t start; s64 commit_time_ms; unsigned int i, new_self_refresh_mask = 0; + bool fence_cookie; + + fence_cookie = dma_fence_begin_signalling(); funcs = dev->mode_config.helper_private; @@ -1634,6 +1643,8 @@ static void commit_tail(struct drm_atomic_state *old_state) if (new_crtc_state->self_refresh_active) new_self_refresh_mask |= BIT(i); + dma_fence_end_signalling(fence_cookie); + if (funcs && funcs->atomic_commit_tail) funcs->atomic_commit_tail(old_state); else @@ -1789,6 +1800,7 @@ int drm_atomic_helper_commit(struct drm_device *dev, bool nonblock) { int ret; + bool fence_cookie; if (state->async_update) { ret = drm_atomic_helper_prepare_planes(dev, state); @@ -1811,6 +1823,8 @@ int drm_atomic_helper_commit(struct drm_device *dev, if (ret) return ret; + fence_cookie = dma_fence_begin_signalling(); + if (!nonblock) { ret = drm_atomic_helper_wait_for_fences(dev, state, true); if (ret) @@ -1848,6 +1862,7 @@ int drm_atomic_helper_commit(struct drm_device *dev, */ drm_atomic_state_get(state); + dma_fence_end_signalling(fence_cookie); if (nonblock) queue_work(system_unbound_wq, &state->commit_work); else @@ -1856,6 +1871,7 @@ int drm_atomic_helper_commit(struct drm_device *dev, return 0; err: + dma_fence_end_signalling(fence_cookie); drm_atomic_helper_cleanup_planes(dev, state); return ret; } -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:14 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:14 +0200 Subject: [Intel-gfx] [PATCH 08/18] drm/amdgpu: add dma-fence annotations to atomic commit path In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-9-daniel.vetter@ffwll.ch> I need a canary in a ttm-based atomic driver to make sure the dma_fence_begin/end_signalling annotations actually work. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bdba0bfd6df1..adabfa929f42 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -57,6 +57,7 @@ #include "ivsrcid/ivsrcid_vislands30.h" +#include <linux/module.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/version.h> @@ -7320,6 +7321,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct drm_connector_state *old_con_state, *new_con_state; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; int crtc_disable_count = 0; + bool fence_cookie; + + fence_cookie = dma_fence_begin_signalling(); drm_atomic_helper_update_legacy_modeset_state(dev, state); @@ -7600,6 +7604,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* Signal HW programming completion */ drm_atomic_helper_commit_hw_done(state); + dma_fence_end_signalling(fence_cookie); + if (wait_for_vblank) drm_atomic_helper_wait_for_flip_done(dev, state); -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:15 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:15 +0200 Subject: [Intel-gfx] [PATCH 09/18] drm/scheduler: use dma-fence annotations in main thread In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-10-daniel.vetter@ffwll.ch> If the scheduler rt thread gets stuck on a mutex that we're holding while waiting for gpu workloads to complete, we have a problem. Add dma-fence annotations so that lockdep can check this for us. I've tried to quite carefully review this, and I think it's at the right spot. But obviosly no expert on drm scheduler. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/scheduler/sched_main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index 2f319102ae9f..06a736e506ad 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -763,9 +763,12 @@ static int drm_sched_main(void *param) struct sched_param sparam = {.sched_priority = 1}; struct drm_gpu_scheduler *sched = (struct drm_gpu_scheduler *)param; int r; + bool fence_cookie; sched_setscheduler(current, SCHED_FIFO, &sparam); + fence_cookie = dma_fence_begin_signalling(); + while (!kthread_should_stop()) { struct drm_sched_entity *entity = NULL; struct drm_sched_fence *s_fence; @@ -823,6 +826,9 @@ static int drm_sched_main(void *param) wake_up(&sched->job_scheduled); } + + dma_fence_end_signalling(fence_cookie); + return 0; } -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:16 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:16 +0200 Subject: [Intel-gfx] [PATCH 10/18] drm/amdgpu: use dma-fence annotations in cs_submit() In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-11-daniel.vetter@ffwll.ch> This is a bit tricky, since ->notifier_lock is held while calling dma_fence_wait we must ensure that also the read side (i.e. dma_fence_begin_signalling) is on the same side. If we mix this up lockdep complaints, and that's again why we want to have these annotations. A nice side effect of this is that because of the fs_reclaim priming for dma_fence_enable lockdep now automatically checks for us that nothing in here allocates memory, without even running any userptr workloads. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a25fb59c127c..e109666aec14 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1212,6 +1212,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, struct amdgpu_job *job; uint64_t seq; int r; + bool fence_cookie; job = p->job; p->job = NULL; @@ -1226,6 +1227,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, */ mutex_lock(&p->adev->notifier_lock); + fence_cookie = dma_fence_begin_signalling(); + /* If userptr are invalidated after amdgpu_cs_parser_bos(), return * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl. */ @@ -1262,12 +1265,14 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm); ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence); + dma_fence_end_signalling(fence_cookie); mutex_unlock(&p->adev->notifier_lock); return 0; error_abort: drm_sched_job_cleanup(&job->base); + dma_fence_end_signalling(fence_cookie); mutex_unlock(&p->adev->notifier_lock); error_unlock: -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:17 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:17 +0200 Subject: [Intel-gfx] [PATCH 11/18] drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-12-daniel.vetter@ffwll.ch> My dma-fence lockdep annotations caught an inversion because we allocate memory where we really shouldn't: kmem_cache_alloc+0x2b/0x6d0 amdgpu_fence_emit+0x30/0x330 [amdgpu] amdgpu_ib_schedule+0x306/0x550 [amdgpu] amdgpu_job_run+0x10f/0x260 [amdgpu] drm_sched_main+0x1b9/0x490 [gpu_sched] kthread+0x12e/0x150 Trouble right now is that lockdep only validates against GFP_FS, which would be good enough for shrinkers. But for mmu_notifiers we actually need !GFP_ATOMIC, since they can be called from any page laundering, even if GFP_NOFS or GFP_NOIO are set. I guess we should improve the lockdep annotations for fs_reclaim_acquire/release. Ofc real fix is to properly preallocate this fence and stuff it into the amdgpu job structure. But GFP_ATOMIC gets the lockdep splat out of the way. v2: Two more allocations in scheduler paths. Frist one: __kmalloc+0x58/0x720 amdgpu_vmid_grab+0x100/0xca0 [amdgpu] amdgpu_job_dependency+0xf9/0x120 [amdgpu] drm_sched_entity_pop_job+0x3f/0x440 [gpu_sched] drm_sched_main+0xf9/0x490 [gpu_sched] Second one: kmem_cache_alloc+0x2b/0x6d0 amdgpu_sync_fence+0x7e/0x110 [amdgpu] amdgpu_vmid_grab+0x86b/0xca0 [amdgpu] amdgpu_job_dependency+0xf9/0x120 [amdgpu] drm_sched_entity_pop_job+0x3f/0x440 [gpu_sched] drm_sched_main+0xf9/0x490 [gpu_sched] Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d878fe7fee51..055b47241bb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -143,7 +143,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, uint32_t seq; int r; - fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); + fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC); if (fence == NULL) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index fe92dcd94d4a..fdcd6659f5ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -208,7 +208,7 @@ static int amdgpu_vmid_grab_idle(struct amdgpu_vm *vm, if (ring->vmid_wait && !dma_fence_is_signaled(ring->vmid_wait)) return amdgpu_sync_fence(sync, ring->vmid_wait, false); - fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL); + fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_ATOMIC); if (!fences) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index b87ca171986a..330476cc0c86 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -168,7 +168,7 @@ int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f, if (amdgpu_sync_add_later(sync, f, explicit)) return 0; - e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL); + e = kmem_cache_alloc(amdgpu_sync_slab, GFP_ATOMIC); if (!e) return -ENOMEM; -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:18 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:18 +0200 Subject: [Intel-gfx] [PATCH 12/18] drm/amdgpu: DC also loves to allocate stuff where it shouldn't In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-13-daniel.vetter@ffwll.ch> Not going to bother with a complete&pretty commit message, just offending backtrace: kvmalloc_node+0x47/0x80 dc_create_state+0x1f/0x60 [amdgpu] dc_commit_state+0xcb/0x9b0 [amdgpu] amdgpu_dm_atomic_commit_tail+0xd31/0x2010 [amdgpu] commit_tail+0xa4/0x140 [drm_kms_helper] drm_atomic_helper_commit+0x152/0x180 [drm_kms_helper] drm_client_modeset_commit_atomic+0x1ea/0x250 [drm] drm_client_modeset_commit_locked+0x55/0x190 [drm] drm_client_modeset_commit+0x24/0x40 [drm] v2: Found more in DC code, I'm just going to pile them all up. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/amd/amdgpu/atom.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 4cfc786699c7..1b0c674fab25 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1226,7 +1226,7 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, ectx.abort = false; ectx.last_jump = 0; if (ws) - ectx.ws = kcalloc(4, ws, GFP_KERNEL); + ectx.ws = kcalloc(4, ws, GFP_ATOMIC); else ectx.ws = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index adabfa929f42..c575e7394d03 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6833,7 +6833,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct dc_stream_update stream_update; } *bundle; - bundle = kzalloc(sizeof(*bundle), GFP_KERNEL); + bundle = kzalloc(sizeof(*bundle), GFP_ATOMIC); if (!bundle) { dm_error("Failed to allocate update bundle\n"); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 45cfb7c45566..9a8e321a7a15 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1416,8 +1416,10 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) struct dc_state *dc_create_state(struct dc *dc) { + /* No you really cant allocate random crap here this late in + * atomic_commit_tail. */ struct dc_state *context = kvzalloc(sizeof(struct dc_state), - GFP_KERNEL); + GFP_ATOMIC); if (!context) return NULL; -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:19 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:19 +0200 Subject: [Intel-gfx] [PATCH 13/18] drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-14-daniel.vetter@ffwll.ch> Trying to grab dma_resv_lock while in commit_tail before we've done all the code that leads to the eventual signalling of the vblank event (which can be a dma_fence) is deadlock-y. Don't do that. Here the solution is easy because just grabbing locks to read something races anyway. We don't need to bother, READ_ONCE is equivalent. And avoids the locking issue. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c575e7394d03..04c11443b9ca 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6910,7 +6910,11 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * explicitly on fences instead * and in general should be called for * blocking commit to as per framework helpers + * + * Yes, this deadlocks, since you're calling dma_resv_lock in a + * path that leads to a dma_fence_signal(). Don't do that. */ +#if 0 r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) DRM_ERROR("failed to reserve buffer before flip\n"); @@ -6920,6 +6924,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, tmz_surface = amdgpu_bo_encrypted(abo); amdgpu_bo_unreserve(abo); +#endif + /* + * this races anyway, so READ_ONCE isn't any better or worse + * than the stuff above. Except the stuff above can deadlock. + */ + tiling_flags = READ_ONCE(abo->tiling_flags); fill_dc_plane_info_and_addr( dm->adev, new_plane_state, tiling_flags, -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:21 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:21 +0200 Subject: [Intel-gfx] [PATCH 15/18] drm/amdgpu: use dma-fence annotations for gpu reset code In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-16-daniel.vetter@ffwll.ch> To improve coverage also annotate the gpu reset code itself, since that's called from other places than drm/scheduler (which is already annotated). Annotations nests, so this doesn't break anything, and allows easier testing. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a027a8f7b281..ac0286a5f2fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4215,6 +4215,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) ? true : false; bool audio_suspended = false; + bool fence_cookie; + + fence_cookie = dma_fence_begin_signalling(); /* * Flush RAM to disk so that after reboot @@ -4243,6 +4246,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress", job ? job->base.id : -1, hive->hive_id); mutex_unlock(&hive->hive_lock); + dma_fence_end_signalling(fence_cookie); return 0; } @@ -4253,8 +4257,10 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ INIT_LIST_HEAD(&device_list); if (adev->gmc.xgmi.num_physical_nodes > 1) { - if (!hive) + if (!hive) { + dma_fence_end_signalling(fence_cookie); return -ENODEV; + } if (!list_is_first(&adev->gmc.xgmi.head, &hive->device_list)) list_rotate_to_front(&adev->gmc.xgmi.head, &hive->device_list); device_list_handle = &hive->device_list; @@ -4269,6 +4275,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress", job ? job->base.id : -1); mutex_unlock(&hive->hive_lock); + dma_fence_end_signalling(fence_cookie); return 0; } @@ -4409,6 +4416,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, if (r) dev_info(adev->dev, "GPU reset end with ret = %d\n", r); + dma_fence_end_signalling(fence_cookie); return r; } -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:20 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:20 +0200 Subject: [Intel-gfx] [PATCH 14/18] drm/scheduler: use dma-fence annotations in tdr work In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-15-daniel.vetter@ffwll.ch> In the face of unpriviledged userspace being able to submit bogus gpu workloads the kernel needs gpu timeout and reset (tdr) to guarantee that dma_fences actually complete. Annotate this worker to make sure we don't have any accidental locking inversions or other problems lurking. Originally this was part of the overall scheduler annotation patch. But amdgpu has some glorious inversions here: - grabs console_lock - does a full modeset, which grabs all kinds of locks (drm_modeset_lock, dma_resv_lock) which can deadlock with dma_fence_wait held inside them. - almost minor at that point, but the modeset code also allocates memory These all look like they'll be very hard to fix properly, the hardware seems to require a full display reset with any gpu recovery. Hence split out as a seperate patch. Since amdgpu isn't the only hardware driver that needs to reset the display (at least gen2/3 on intel have the same problem) we need a generic solution for this. There's two tricks we could still from drm/i915 and lift to dma-fence: - The big whack, aka force-complete all fences. i915 does this for all pending jobs if the reset is somehow stuck. Trouble is we'd need to do this for all fences in the entire system, and just the book-keeping for that will be fun. Plus lots of drivers use fences for all kinds of internal stuff like memory management, so unconditionally resetting all of them doesn't work. I'm also hoping that with these fence annotations we could enlist lockdep in finding the last offenders causing deadlocks, and we could remove this get-out-of-jail trick. - The more feasible approach (across drivers at least as part of the dma_fence contract) is what drm/i915 does for gen2/3: When we need to reset the display we wake up all dma_fence_wait_interruptible calls, or well at least the equivalent of those in i915 internally. Relying on ioctl restart we force all other threads to release their locks, which means the tdr thread is guaranteed to be able to get them. I think we could implement this at the dma_fence level, including proper lockdep annotations. dma_fence_begin_tdr(): - must be nested within a dma_fence_begin/end_signalling section - will wake up all interruptible (but not the non-interruptible) dma_fence_wait() calls and force them to complete with a -ERESTARTSYS errno code. All new interrupitble calls to dma_fence_wait() will immeidately fail with the same error code. dma_fence_end_trdr(): - this will convert dma_fence_wait() calls back to normal. Of course interrupting dma_fence_wait is only ok if the caller specified that, which means we need to split the annotations into interruptible and non-interruptible version. If we then make sure that we only use interruptible dma_fence_wait() calls while holding drm_modeset_lock we can grab them in tdr code, and allow display resets. Doing the same for dma_resv_lock might be a lot harder, so buffer updates must be avoided. What's worse, we're not going to be able to make the dma_fence_wait calls in mmu-notifiers interruptible, that doesn't work. So allocating memory still wont' be allowed, even in tdr sections. Plus obviously we can use this trick only in tdr, it is rather intrusive. Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/scheduler/sched_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index 06a736e506ad..e34a44376e87 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -279,9 +279,12 @@ static void drm_sched_job_timedout(struct work_struct *work) { struct drm_gpu_scheduler *sched; struct drm_sched_job *job; + bool fence_cookie; sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work); + fence_cookie = dma_fence_begin_signalling(); + /* Protects against concurrent deletion in drm_sched_get_cleanup_job */ spin_lock(&sched->job_list_lock); job = list_first_entry_or_null(&sched->ring_mirror_list, @@ -313,6 +316,8 @@ static void drm_sched_job_timedout(struct work_struct *work) spin_lock(&sched->job_list_lock); drm_sched_start_timeout(sched); spin_unlock(&sched->job_list_lock); + + dma_fence_end_signalling(fence_cookie); } /** -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:22 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:22 +0200 Subject: [Intel-gfx] [PATCH 16/18] Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-17-daniel.vetter@ffwll.ch> This is one from the department of "maybe play lottery if you hit this, karma compensation might work". Or at least lockdep ftw! This reverts commit 565d1941557756a584ac357d945bc374d5fcd1d0. It's not quite as low-risk as the commit message claims, because this grabs console_lock, which might be held when we allocate memory, which might never happen because the dma_fence_wait() is stuck waiting on our gpu reset: [ 136.763714] ====================================================== [ 136.763714] WARNING: possible circular locking dependency detected [ 136.763715] 5.7.0-rc3+ #346 Tainted: G W [ 136.763716] ------------------------------------------------------ [ 136.763716] kworker/2:3/682 is trying to acquire lock: [ 136.763716] ffffffff8226f140 (console_lock){+.+.}-{0:0}, at: drm_fb_helper_set_suspend_unlocked+0x7b/0xa0 [drm_kms_helper] [ 136.763723] but task is already holding lock: [ 136.763724] ffffffff82318c80 (dma_fence_map){++++}-{0:0}, at: drm_sched_job_timedout+0x25/0xf0 [gpu_sched] [ 136.763726] which lock already depends on the new lock. [ 136.763726] the existing dependency chain (in reverse order) is: [ 136.763727] -> #2 (dma_fence_map){++++}-{0:0}: [ 136.763730] __dma_fence_might_wait+0x41/0xb0 [ 136.763732] dma_resv_lockdep+0x171/0x202 [ 136.763734] do_one_initcall+0x5d/0x2f0 [ 136.763736] kernel_init_freeable+0x20d/0x26d [ 136.763738] kernel_init+0xa/0xfb [ 136.763740] ret_from_fork+0x27/0x50 [ 136.763740] -> #1 (fs_reclaim){+.+.}-{0:0}: [ 136.763743] fs_reclaim_acquire.part.0+0x25/0x30 [ 136.763745] kmem_cache_alloc_trace+0x2e/0x6e0 [ 136.763747] device_create_groups_vargs+0x52/0xf0 [ 136.763747] device_create+0x49/0x60 [ 136.763749] fb_console_init+0x25/0x145 [ 136.763750] fbmem_init+0xcc/0xe2 [ 136.763750] do_one_initcall+0x5d/0x2f0 [ 136.763751] kernel_init_freeable+0x20d/0x26d [ 136.763752] kernel_init+0xa/0xfb [ 136.763753] ret_from_fork+0x27/0x50 [ 136.763753] -> #0 (console_lock){+.+.}-{0:0}: [ 136.763755] __lock_acquire+0x1241/0x23f0 [ 136.763756] lock_acquire+0xad/0x370 [ 136.763757] console_lock+0x47/0x70 [ 136.763761] drm_fb_helper_set_suspend_unlocked+0x7b/0xa0 [drm_kms_helper] [ 136.763809] amdgpu_device_gpu_recover.cold+0x21e/0xe7b [amdgpu] [ 136.763850] amdgpu_job_timedout+0xfb/0x150 [amdgpu] [ 136.763851] drm_sched_job_timedout+0x8a/0xf0 [gpu_sched] [ 136.763852] process_one_work+0x23c/0x580 [ 136.763853] worker_thread+0x50/0x3b0 [ 136.763854] kthread+0x12e/0x150 [ 136.763855] ret_from_fork+0x27/0x50 [ 136.763855] other info that might help us debug this: [ 136.763856] Chain exists of: console_lock --> fs_reclaim --> dma_fence_map [ 136.763857] Possible unsafe locking scenario: [ 136.763857] CPU0 CPU1 [ 136.763857] ---- ---- [ 136.763857] lock(dma_fence_map); [ 136.763858] lock(fs_reclaim); [ 136.763858] lock(dma_fence_map); [ 136.763858] lock(console_lock); [ 136.763859] *** DEADLOCK *** [ 136.763860] 4 locks held by kworker/2:3/682: [ 136.763860] #0: ffff8887fb81c938 ((wq_completion)events){+.+.}-{0:0}, at: process_one_work+0x1bc/0x580 [ 136.763862] #1: ffffc90000cafe58 ((work_completion)(&(&sched->work_tdr)->work)){+.+.}-{0:0}, at: process_one_work+0x1bc/0x580 [ 136.763863] #2: ffffffff82318c80 (dma_fence_map){++++}-{0:0}, at: drm_sched_job_timedout+0x25/0xf0 [gpu_sched] [ 136.763865] #3: ffff8887ab621748 (&adev->lock_reset){+.+.}-{3:3}, at: amdgpu_device_gpu_recover.cold+0x5ab/0xe7b [amdgpu] [ 136.763914] stack backtrace: [ 136.763915] CPU: 2 PID: 682 Comm: kworker/2:3 Tainted: G W 5.7.0-rc3+ #346 [ 136.763916] Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 4011 04/19/2018 [ 136.763918] Workqueue: events drm_sched_job_timedout [gpu_sched] [ 136.763919] Call Trace: [ 136.763922] dump_stack+0x8f/0xd0 [ 136.763924] check_noncircular+0x162/0x180 [ 136.763926] __lock_acquire+0x1241/0x23f0 [ 136.763927] lock_acquire+0xad/0x370 [ 136.763932] ? drm_fb_helper_set_suspend_unlocked+0x7b/0xa0 [drm_kms_helper] [ 136.763933] ? mark_held_locks+0x2d/0x80 [ 136.763934] ? _raw_spin_unlock_irqrestore+0x46/0x60 [ 136.763936] console_lock+0x47/0x70 [ 136.763940] ? drm_fb_helper_set_suspend_unlocked+0x7b/0xa0 [drm_kms_helper] [ 136.763944] drm_fb_helper_set_suspend_unlocked+0x7b/0xa0 [drm_kms_helper] [ 136.763993] amdgpu_device_gpu_recover.cold+0x21e/0xe7b [amdgpu] [ 136.764036] amdgpu_job_timedout+0xfb/0x150 [amdgpu] [ 136.764038] drm_sched_job_timedout+0x8a/0xf0 [gpu_sched] [ 136.764040] process_one_work+0x23c/0x580 [ 136.764041] worker_thread+0x50/0x3b0 [ 136.764042] ? process_one_work+0x580/0x580 [ 136.764044] kthread+0x12e/0x150 [ 136.764045] ? kthread_create_worker_on_cpu+0x70/0x70 [ 136.764046] ret_from_fork+0x27/0x50 Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ac0286a5f2fc..4c4492de670c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4063,8 +4063,6 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive, if (r) goto out; - amdgpu_fbdev_set_suspend(tmp_adev, 0); - /* must succeed. */ amdgpu_ras_resume(tmp_adev); @@ -4305,8 +4303,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ amdgpu_unregister_gpu_instance(tmp_adev); - amdgpu_fbdev_set_suspend(tmp_adev, 1); - /* disable ras on ALL IPs */ if (!(in_ras_intr && !use_baco) && amdgpu_device_ip_need_full_reset(tmp_adev)) -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:23 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:23 +0200 Subject: [Intel-gfx] [PATCH 17/18] drm/amdgpu: gpu recovery does full modesets In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-18-daniel.vetter@ffwll.ch> ... I think it's time to stop this little exercise. The lockdep splat, for the record: [ 132.583381] ====================================================== [ 132.584091] WARNING: possible circular locking dependency detected [ 132.584775] 5.7.0-rc3+ #346 Tainted: G W [ 132.585461] ------------------------------------------------------ [ 132.586184] kworker/2:3/865 is trying to acquire lock: [ 132.586857] ffffc90000677c70 (crtc_ww_class_acquire){+.+.}-{0:0}, at: drm_atomic_helper_suspend+0x38/0x120 [drm_kms_helper] [ 132.587569] but task is already holding lock: [ 132.589044] ffffffff82318c80 (dma_fence_map){++++}-{0:0}, at: drm_sched_job_timedout+0x25/0xf0 [gpu_sched] [ 132.589803] which lock already depends on the new lock. [ 132.592009] the existing dependency chain (in reverse order) is: [ 132.593507] -> #2 (dma_fence_map){++++}-{0:0}: [ 132.595019] dma_fence_begin_signalling+0x50/0x60 [ 132.595767] drm_atomic_helper_commit+0xa1/0x180 [drm_kms_helper] [ 132.596567] drm_client_modeset_commit_atomic+0x1ea/0x250 [drm] [ 132.597420] drm_client_modeset_commit_locked+0x55/0x190 [drm] [ 132.598178] drm_client_modeset_commit+0x24/0x40 [drm] [ 132.598948] drm_fb_helper_restore_fbdev_mode_unlocked+0x4b/0xa0 [drm_kms_helper] [ 132.599738] drm_fb_helper_set_par+0x30/0x40 [drm_kms_helper] [ 132.600539] fbcon_init+0x2e8/0x660 [ 132.601344] visual_init+0xce/0x130 [ 132.602156] do_bind_con_driver+0x1bc/0x2b0 [ 132.602970] do_take_over_console+0x115/0x180 [ 132.603763] do_fbcon_takeover+0x58/0xb0 [ 132.604564] register_framebuffer+0x1ee/0x300 [ 132.605369] __drm_fb_helper_initial_config_and_unlock+0x36e/0x520 [drm_kms_helper] [ 132.606187] amdgpu_fbdev_init+0xb3/0xf0 [amdgpu] [ 132.607032] amdgpu_device_init.cold+0xe90/0x1677 [amdgpu] [ 132.607862] amdgpu_driver_load_kms+0x5a/0x200 [amdgpu] [ 132.608697] amdgpu_pci_probe+0xf7/0x180 [amdgpu] [ 132.609511] local_pci_probe+0x42/0x80 [ 132.610324] pci_device_probe+0x104/0x1a0 [ 132.611130] really_probe+0x147/0x3c0 [ 132.611939] driver_probe_device+0xb6/0x100 [ 132.612766] device_driver_attach+0x53/0x60 [ 132.613593] __driver_attach+0x8c/0x150 [ 132.614419] bus_for_each_dev+0x7b/0xc0 [ 132.615249] bus_add_driver+0x14c/0x1f0 [ 132.616071] driver_register+0x6c/0xc0 [ 132.616902] do_one_initcall+0x5d/0x2f0 [ 132.617731] do_init_module+0x5c/0x230 [ 132.618560] load_module+0x2981/0x2bc0 [ 132.619391] __do_sys_finit_module+0xaa/0x110 [ 132.620228] do_syscall_64+0x5a/0x250 [ 132.621064] entry_SYSCALL_64_after_hwframe+0x49/0xb3 [ 132.621903] -> #1 (crtc_ww_class_mutex){+.+.}-{3:3}: [ 132.623587] __ww_mutex_lock.constprop.0+0xcc/0x10c0 [ 132.624448] ww_mutex_lock+0x43/0xb0 [ 132.625315] drm_modeset_lock+0x44/0x120 [drm] [ 132.626184] drmm_mode_config_init+0x2db/0x8b0 [drm] [ 132.627098] amdgpu_device_init.cold+0xbd1/0x1677 [amdgpu] [ 132.628007] amdgpu_driver_load_kms+0x5a/0x200 [amdgpu] [ 132.628920] amdgpu_pci_probe+0xf7/0x180 [amdgpu] [ 132.629804] local_pci_probe+0x42/0x80 [ 132.630690] pci_device_probe+0x104/0x1a0 [ 132.631583] really_probe+0x147/0x3c0 [ 132.632479] driver_probe_device+0xb6/0x100 [ 132.633379] device_driver_attach+0x53/0x60 [ 132.634275] __driver_attach+0x8c/0x150 [ 132.635170] bus_for_each_dev+0x7b/0xc0 [ 132.636069] bus_add_driver+0x14c/0x1f0 [ 132.636974] driver_register+0x6c/0xc0 [ 132.637870] do_one_initcall+0x5d/0x2f0 [ 132.638765] do_init_module+0x5c/0x230 [ 132.639654] load_module+0x2981/0x2bc0 [ 132.640522] __do_sys_finit_module+0xaa/0x110 [ 132.641372] do_syscall_64+0x5a/0x250 [ 132.642203] entry_SYSCALL_64_after_hwframe+0x49/0xb3 [ 132.643022] -> #0 (crtc_ww_class_acquire){+.+.}-{0:0}: [ 132.644643] __lock_acquire+0x1241/0x23f0 [ 132.645469] lock_acquire+0xad/0x370 [ 132.646274] drm_modeset_acquire_init+0xd2/0x100 [drm] [ 132.647071] drm_atomic_helper_suspend+0x38/0x120 [drm_kms_helper] [ 132.647902] dm_suspend+0x1c/0x60 [amdgpu] [ 132.648698] amdgpu_device_ip_suspend_phase1+0x83/0xe0 [amdgpu] [ 132.649498] amdgpu_device_ip_suspend+0x1c/0x60 [amdgpu] [ 132.650300] amdgpu_device_gpu_recover.cold+0x4e6/0xe64 [amdgpu] [ 132.651084] amdgpu_job_timedout+0xfb/0x150 [amdgpu] [ 132.651825] drm_sched_job_timedout+0x8a/0xf0 [gpu_sched] [ 132.652594] process_one_work+0x23c/0x580 [ 132.653402] worker_thread+0x50/0x3b0 [ 132.654139] kthread+0x12e/0x150 [ 132.654868] ret_from_fork+0x27/0x50 [ 132.655598] other info that might help us debug this: [ 132.657739] Chain exists of: crtc_ww_class_acquire --> crtc_ww_class_mutex --> dma_fence_map [ 132.659877] Possible unsafe locking scenario: [ 132.661416] CPU0 CPU1 [ 132.662126] ---- ---- [ 132.662847] lock(dma_fence_map); [ 132.663574] lock(crtc_ww_class_mutex); [ 132.664319] lock(dma_fence_map); [ 132.665063] lock(crtc_ww_class_acquire); [ 132.665799] *** DEADLOCK *** [ 132.667965] 4 locks held by kworker/2:3/865: [ 132.668701] #0: ffff8887fb81c938 ((wq_completion)events){+.+.}-{0:0}, at: process_one_work+0x1bc/0x580 [ 132.669462] #1: ffffc90000677e58 ((work_completion)(&(&sched->work_tdr)->work)){+.+.}-{0:0}, at: process_one_work+0x1bc/0x580 [ 132.670242] #2: ffffffff82318c80 (dma_fence_map){++++}-{0:0}, at: drm_sched_job_timedout+0x25/0xf0 [gpu_sched] [ 132.671039] #3: ffff8887b84a1748 (&adev->lock_reset){+.+.}-{3:3}, at: amdgpu_device_gpu_recover.cold+0x59e/0xe64 [amdgpu] [ 132.671902] stack backtrace: [ 132.673515] CPU: 2 PID: 865 Comm: kworker/2:3 Tainted: G W 5.7.0-rc3+ #346 [ 132.674347] Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 4011 04/19/2018 [ 132.675194] Workqueue: events drm_sched_job_timedout [gpu_sched] [ 132.676046] Call Trace: [ 132.676897] dump_stack+0x8f/0xd0 [ 132.677748] check_noncircular+0x162/0x180 [ 132.678604] ? stack_trace_save+0x4b/0x70 [ 132.679459] __lock_acquire+0x1241/0x23f0 [ 132.680311] lock_acquire+0xad/0x370 [ 132.681163] ? drm_atomic_helper_suspend+0x38/0x120 [drm_kms_helper] [ 132.682021] ? cpumask_next+0x16/0x20 [ 132.682880] ? module_assert_mutex_or_preempt+0x14/0x40 [ 132.683737] ? __module_address+0x28/0xf0 [ 132.684601] drm_modeset_acquire_init+0xd2/0x100 [drm] [ 132.685466] ? drm_atomic_helper_suspend+0x38/0x120 [drm_kms_helper] [ 132.686335] drm_atomic_helper_suspend+0x38/0x120 [drm_kms_helper] [ 132.687255] dm_suspend+0x1c/0x60 [amdgpu] [ 132.688152] amdgpu_device_ip_suspend_phase1+0x83/0xe0 [amdgpu] [ 132.689057] ? amdgpu_fence_process+0x4c/0x150 [amdgpu] [ 132.689963] amdgpu_device_ip_suspend+0x1c/0x60 [amdgpu] [ 132.690893] amdgpu_device_gpu_recover.cold+0x4e6/0xe64 [amdgpu] [ 132.691818] amdgpu_job_timedout+0xfb/0x150 [amdgpu] [ 132.692707] drm_sched_job_timedout+0x8a/0xf0 [gpu_sched] [ 132.693597] process_one_work+0x23c/0x580 [ 132.694487] worker_thread+0x50/0x3b0 [ 132.695373] ? process_one_work+0x580/0x580 [ 132.696264] kthread+0x12e/0x150 [ 132.697154] ? kthread_create_worker_on_cpu+0x70/0x70 [ 132.698057] ret_from_fork+0x27/0x50 Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4c4492de670c..3ea4b9258fb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2441,6 +2441,14 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) /* displays are handled separately */ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { /* XXX handle errors */ + + /* + * This is dm_suspend, which calls modeset locks, and + * that a pretty good inversion against dma_fence_signal + * which gpu recovery is supposed to guarantee. + * + * Dont ask me how to fix this. + */ r = adev->ip_blocks[i].version->funcs->suspend(adev); /* XXX handle errors */ if (r) { -- 2.26.2 From daniel.vetter at ffwll.ch Thu Jun 4 08:12:24 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 10:12:24 +0200 Subject: [Intel-gfx] [PATCH 18/18] drm/i915: Annotate dma_fence_work In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <20200604081224.863494-19-daniel.vetter@ffwll.ch> i915 does tons of allocations from this worker, which lockdep catches. Also generic infrastructure like this with big potential for how dma_fence or other cross driver contracts work, really should be reviewed on dri-devel. Implementing custom wheels for everything within the driver is a classic case of "platform problem" [1]. Which in upstream we really shouldn't have. Since there's no quick way to solve these splats (dma_fence_work is used a bunch in basic buffer management and command submission) like for amdgpu, I'm giving up at this point here. Annotating i915 scheduler and gpu reset could would be interesting, but since lockdep is one-shot we can't see what surprises would lurk there. 1: https://lwn.net/Articles/443531/ Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/i915/i915_sw_fence_work.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_sw_fence_work.c b/drivers/gpu/drm/i915/i915_sw_fence_work.c index a3a81bb8f2c3..5b74acadaef5 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence_work.c +++ b/drivers/gpu/drm/i915/i915_sw_fence_work.c @@ -17,12 +17,15 @@ static void fence_work(struct work_struct *work) { struct dma_fence_work *f = container_of(work, typeof(*f), work); int err; + bool fence_cookie; + fence_cookie = dma_fence_begin_signalling(); err = f->ops->work(f); if (err) dma_fence_set_error(&f->dma, err); fence_complete(f); + dma_fence_end_signalling(fence_cookie); dma_fence_put(&f->dma); } -- 2.26.2 From patchwork at emeril.freedesktop.org Thu Jun 4 08:26:16 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 08:26:16 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/i915/dp=5Fmst=3A_Fix_disabling_?= =?utf-8?q?MST_on_a_port?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159125917647.14554.7653253231789861779@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/dp_mst: Fix disabling MST on a port URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17858_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17858_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-write-gtt-active: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb6/igt at gem_exec_reloc@basic-write-gtt-active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-tglb7/igt at gem_exec_reloc@basic-write-gtt-active.html * igt at gem_sync@basic-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk6/igt at gem_sync@basic-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-glk4/igt at gem_sync@basic-all.html * igt at gem_tiled_partial_pwrite_pread@writes-after-reads: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +19 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl3/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html * igt at i915_suspend@debugfs-reader: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#69]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl6/igt at i915_suspend@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl6/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +10 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl2/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html * igt at kms_big_fb@y-tiled-32bpp-rotate-90: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl1/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#1925] / [i915#1926]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-glk6/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb1/igt at kms_cursor_legacy@pipe-b-torture-move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-iclb4/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl5/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-snb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc: - shard-iclb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-iclb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#49]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][31] -> [FAIL][32] ([i915#1188]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl8/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145] / [i915#265]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-iclb8/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_setmode@basic: - shard-apl: [PASS][39] -> [FAIL][40] ([i915#31]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl3/igt at kms_setmode@basic.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#93] / [i915#95]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-kbl4/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * igt at gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [DMESG-WARN][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at gem_exec_whisper@basic-contexts-forked-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-glk9/igt at gem_exec_whisper@basic-contexts-forked-all.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl7/igt at gem_workarounds@suspend-resume-context.html * igt at kms_big_fb@y-tiled-8bpp-rotate-0: - shard-apl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl3/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][49] ([i915#402]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-tglb8/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * igt at kms_cursor_edge_walk@pipe-a-64x64-top-edge: - shard-apl: [DMESG-WARN][51] ([i915#95]) -> [PASS][52] +8 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_cursor_edge_walk@pipe-a-64x64-top-edge.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl2/igt at kms_cursor_edge_walk@pipe-a-64x64-top-edge.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][53] ([i915#46]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-kbl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][57] ([i915#93] / [i915#95]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][59] ([i915#69]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl9/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-position-hole-pipe-a-planes: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +10 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at kms_plane@plane-position-hole-pipe-a-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl4/igt at kms_plane@plane-position-hole-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][67] ([fdo#109642] / [fdo#111068]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb1/igt at kms_psr2_su@page_flip.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_cursor_mmap_gtt: - shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt at kms_psr@psr2_cursor_mmap_gtt.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_gtt.html * igt at kms_setmode@basic: - shard-skl: [FAIL][71] ([i915#31]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_setmode@basic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-skl5/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +5 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][75] ([i915#1542]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-tglb2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][81] ([i915#1319] / [i915#1635]) -> [FAIL][82] ([fdo#110321] / [fdo#110336]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at kms_content_protection@legacy.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][83] ([fdo#110321]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl4/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-tglb: [DMESG-WARN][85] ([i915#1982]) -> [DMESG-WARN][86] ([i915#1982] / [i915#402]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [DMESG-FAIL][87] ([i915#49] / [i915#95]) -> [FAIL][88] ([i915#49]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17858 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17858: 7a10916bbf7e8b6d18f552c3d6135250da4caa20 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17858/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 08:34:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 08:34:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches?= In-Reply-To: <20200603211529.3005059-1-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> Message-ID: <159125964432.14555.14975271091238919132@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17859_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_ctx_isolation@preservation-s3 at vcs0}: - shard-kbl: [INCOMPLETE][1] ([i915#1780]) -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at vcs0.html Known issues ------------ Here are the changes found in Patchwork_17859_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_eio@in-flight-internal-10ms: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at gem_eio@in-flight-internal-10ms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt at gem_eio@in-flight-internal-10ms.html * igt at gem_eio@in-flight-suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at gem_eio@in-flight-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl10/igt at gem_eio@in-flight-suspend.html * igt at gem_mmap_offset@clear: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +10 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at gem_mmap_offset@clear.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl9/igt at gem_mmap_offset@clear.html * igt at i915_module_load@reload: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb2/igt at i915_module_load@reload.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at i915_suspend@forcewake.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl4/igt at i915_suspend@forcewake.html * igt at kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-size-change.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt at kms_cursor_legacy@all-pipes-torture-move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb6/igt at kms_cursor_legacy@all-pipes-torture-move.html - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#128]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at kms_cursor_legacy@all-pipes-torture-move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb6/igt at kms_cursor_legacy@all-pipes-torture-move.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][21] -> [DMESG-FAIL][22] ([i915#1925] / [i915#1926]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk7/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#49]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: - shard-skl: [PASS][31] -> [FAIL][32] ([i915#53]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#173]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt at kms_psr@no_drrs.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_setmode@basic: - shard-apl: [PASS][37] -> [FAIL][38] ([i915#31]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-wait-busy: - shard-tglb: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_vblank@pipe-c-wait-busy.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt at kms_vblank@pipe-c-wait-busy.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#93] / [i915#95]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl3/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][43] ([i915#1930]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html - shard-apl: [FAIL][45] ([i915#1930]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at gem_exec_reloc@basic-concurrent0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][47] ([i915#82]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +2 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt at gem_workarounds@suspend-resume-context.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-180: - shard-apl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][53] ([i915#402]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb8/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][55] ([i915#46]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][63] ([i915#69]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +10 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl5/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][67] ([i915#95]) -> [PASS][68] +11 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb8/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +4 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][73] ([i915#1542]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt at perf@blocking-parameterized.html * igt at perf_pmu@rc6-runtime-pm: - shard-glk: [TIMEOUT][75] ([i915#1958]) -> [PASS][76] +3 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at perf_pmu@rc6-runtime-pm.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt at perf_pmu@rc6-runtime-pm.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][77] ([i915#1319]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl7/igt at kms_content_protection@atomic.html - shard-apl: [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][80] ([fdo#110321] / [i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][81] ([i915#1319]) -> [FAIL][82] ([fdo#110321] / [fdo#110336]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][83] ([i915#1319] / [i915#1635]) -> [TIMEOUT][84] ([i915#1319]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@lic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][85] ([fdo#110321]) -> [TIMEOUT][86] ([i915#1319]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [DMESG-FAIL][87] ([i915#49] / [i915#95]) -> [FAIL][88] ([i915#49]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-glk: [TIMEOUT][89] ([i915#1640] / [i915#1958]) -> [SKIP][90] ([fdo#109271]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at kms_vblank@pipe-d-query-idle-hang.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt at kms_vblank@pipe-d-query-idle-hang.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#1780]: https://gitlab.freedesktop.org/drm/intel/issues/1780 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17859 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17859: c298c9e3576e74cdc573db5a6f877f920d106bbb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 08:40:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 08:40:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Implement_WA=5F16011163337_=28rev2=29?= In-Reply-To: <20200603221150.14745-1-clinton.a.taylor@intel.com> References: <20200603221150.14745-1-clinton.a.taylor@intel.com> Message-ID: <159126005186.14552.950506138232872445@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Implement WA_16011163337 (rev2) URL : https://patchwork.freedesktop.org/series/77933/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17860_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17860_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-tglb7/igt at i915_module_load@reload.html * igt at i915_suspend@sysfs-reader: - shard-skl: [PASS][3] -> [TIMEOUT][4] ([i915#1958]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at i915_suspend@sysfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl4/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@y-tiled-32bpp-rotate-180: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl10/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl8/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-size-change.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#1925] / [i915#1926]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-glk7/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +18 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#53]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl8/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#648] / [i915#69]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl5/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_cursor@pipe-a-overlay-size-256: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#198]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_plane_cursor@pipe-a-overlay-size-256.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl2/igt at kms_plane_cursor@pipe-a-overlay-size-256.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#173]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt at kms_psr@no_drrs.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-kbl3/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at perf@polling: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at perf@polling.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl7/igt at perf@polling.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#93] / [i915#95]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-kbl2/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at bcs0}: - shard-kbl: [FAIL][35] ([fdo#103375]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * {igt at gem_ctx_isolation@preservation-s3 at vcs0}: - shard-kbl: [INCOMPLETE][37] ([i915#1780]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][39] ([i915#1930]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html - shard-apl: [FAIL][41] ([i915#1930]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at gem_exec_reloc@basic-concurrent0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [FAIL][43] ([i915#1930]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][45] ([i915#82]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl1/igt at gem_workarounds@suspend-resume-context.html * igt at kms_big_fb@y-tiled-8bpp-rotate-0: - shard-apl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl7/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][51] ([i915#402]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-tglb5/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [FAIL][53] ([i915#72]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-glk7/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-tglb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-tglb2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][57] ([i915#93] / [i915#95]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_hdr@bpc-switch.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl2/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][61] ([i915#69]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +10 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl7/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][69] ([i915#180]) -> [PASS][70] +4 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-tglb6/igt at perf@blocking-parameterized.html * igt at vgem_basic@dmabuf-mmap: - shard-apl: [DMESG-WARN][73] ([i915#95]) -> [PASS][74] +13 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at vgem_basic@dmabuf-mmap.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl7/igt at vgem_basic@dmabuf-mmap.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][75] ([i915#454]) -> [SKIP][76] ([i915#468]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at i915_pm_dc@dc6-psr.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][77] ([i915#1319]) -> [FAIL][78] ([fdo#110321] / [fdo#110336]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl2/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [TIMEOUT][80] ([i915#1319]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@lic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl3/igt at kms_content_protection@lic.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite: - shard-skl: [SKIP][81] ([fdo#109271]) -> [TIMEOUT][82] ([i915#1958]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl4/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [DMESG-FAIL][83] ([i915#49] / [i915#95]) -> [FAIL][84] ([i915#49]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-skl: [SKIP][85] ([fdo#109271]) -> [TIMEOUT][86] ([i915#1640] / [i915#1958]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_vblank@pipe-d-query-idle-hang.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/shard-skl4/igt at kms_vblank@pipe-d-query-idle-hang.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#1780]: https://gitlab.freedesktop.org/drm/intel/issues/1780 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17860 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17860: db356ac08f68ff4efb08d69e177faeb2b550c252 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17860/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 08:47:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 08:47:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/i915/dp=5Fmst=3A_Fix_disabling_?= =?utf-8?q?MST_on_a_port_=28rev2=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159126045280.14554.5059977157347722996@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev2) URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17861_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17861_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_tiled_partial_pwrite_pread@writes-after-reads: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +16 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl3/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl6/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at kms_color@pipe-c-ctm-0-25.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl2/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl1/igt at kms_cursor_crc@pipe-c-cursor-size-change.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#1925] / [i915#1926]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-glk7/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#53]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl1/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_setmode@basic: - shard-apl: [PASS][21] -> [FAIL][22] ([i915#31]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl8/igt at kms_setmode@basic.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#93] / [i915#95]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at bcs0}: - shard-kbl: [FAIL][25] ([fdo#103375]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * {igt at gem_ctx_isolation@preservation-s3 at vcs0}: - shard-kbl: [INCOMPLETE][27] ([i915#1780]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][29] ([i915#1930]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][31] ([i915#82]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at gem_exec_whisper@basic-contexts-forked-all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-glk2/igt at gem_exec_whisper@basic-contexts-forked-all.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl3/igt at gem_workarounds@suspend-resume-context.html * igt at i915_suspend@sysfs-reader: - shard-apl: [TIMEOUT][37] ([i915#1635]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at i915_suspend@sysfs-reader.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl7/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@y-tiled-8bpp-rotate-0: - shard-apl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl3/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][41] ([i915#402]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-tglb1/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][43] ([i915#46]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html - shard-tglb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-tglb3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][49] ([i915#69]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-position-hole-pipe-a-planes: - shard-skl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +8 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at kms_plane@plane-position-hole-pipe-a-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-skl2/igt at kms_plane@plane-position-hole-pipe-a-planes.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-iclb5/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +5 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-tglb7/igt at perf@blocking-parameterized.html * igt at vgem_basic@dmabuf-mmap: - shard-apl: [DMESG-WARN][59] ([i915#95]) -> [PASS][60] +6 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at vgem_basic@dmabuf-mmap.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl3/igt at vgem_basic@dmabuf-mmap.html #### Warnings #### * igt at gem_ctx_bad_destroy@invalid-pad: - shard-apl: [TIMEOUT][61] ([i915#1635]) -> [DMESG-WARN][62] ([i915#95]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at gem_ctx_bad_destroy@invalid-pad.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl7/igt at gem_ctx_bad_destroy@invalid-pad.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][63] ([i915#454]) -> [SKIP][64] ([i915#468]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at i915_pm_dc@dc6-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at i915_pm_rpm@sysfs-read: - shard-snb: [SKIP][65] ([fdo#109271]) -> [INCOMPLETE][66] ([i915#82]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb4/igt at i915_pm_rpm@sysfs-read.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-snb4/igt at i915_pm_rpm@sysfs-read.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [TIMEOUT][68] ([i915#1319]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][69] ([i915#1319]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][73] ([i915#93] / [i915#95]) -> [DMESG-WARN][74] ([i915#180] / [i915#93] / [i915#95]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-apl: [TIMEOUT][75] ([i915#1635] / [i915#1640]) -> [SKIP][76] ([fdo#109271]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at kms_vblank@pipe-d-query-idle-hang.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/shard-apl7/igt at kms_vblank@pipe-d-query-idle-hang.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 [i915#1780]: https://gitlab.freedesktop.org/drm/intel/issues/1780 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17861 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17861: 10ec0f0a95d1ed7b600df217f021788844964bc8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17861/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 08:55:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 08:55:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_dma-fence_lockdep_annotations=2C_round_2?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159126092019.14555.14482397890321884859@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim checkpatch origin/drm-tip 199c3f9df986 mm: Track mmu notifiers in fs_reclaim_acquire/release -:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #12: recursions we do have lockdep annotations since 23b68395c7c7 -:41: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 66204f1d2d1b ("mm/mmu_notifiers: prime lockdep")' #41: With this we can also remove the lockdep priming added in 66204f1d2d1b -:116: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #116: FILE: mm/page_alloc.c:4165: + + } -:130: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 2 errors, 1 warnings, 1 checks, 65 lines checked b85d9997eaca dma-buf: minor doc touch-ups -:32: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 14 lines checked 7f8c3b44f8eb dma-fence: basic lockdep annotations -:23: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e91498589746 ("locking/lockdep/selftests: Add mixed read-write ABBA tests")' #23: commit e91498589746065e3ae95d9a00b068e525eec34f -:261: ERROR:IN_ATOMIC: do not use in_atomic in drivers #261: FILE: drivers/dma-buf/dma-fence.c:228: + if (in_atomic()) -:299: CHECK:LINE_SPACING: Please don't use multiple blank lines #299: FILE: drivers/dma-buf/dma-fence.c:266: + + -:348: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #348: FILE: include/linux/dma-fence.h:368: +} +static inline void dma_fence_end_signalling(bool cookie) {} -:354: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 2 errors, 1 warnings, 2 checks, 231 lines checked 96b50a5032df dma-fence: prime lockdep annotations -:31: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #31: commit 23b68395c7c78a764e8963fc15a7cfd318bf187f -:169: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 1 errors, 1 warnings, 0 checks, 82 lines checked 2fb5c8b43ac8 drm/vkms: Annotate vblank timer -:59: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 25 lines checked 93efe4f7dc82 drm/vblank: Annotate with dma-fence signalling section -:71: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 38 lines checked 9d42aa205b3f drm/atomic-helper: Add dma-fence annotations -:119: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 76 lines checked 911b274bb909 drm/amdgpu: add dma-fence annotations to atomic commit path -:52: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 24 lines checked 0485794be8aa drm/scheduler: use dma-fence annotations in main thread -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 21 lines checked 82020872a9a2 drm/amdgpu: use dma-fence annotations in cs_submit() -:65: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 29 lines checked 05627337ac19 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code -:82: WARNING:ALLOC_ARRAY_ARGS: kmalloc_array uses number as first arg, sizeof is generally wrong #82: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:211: + fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_ATOMIC); -:98: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 24 lines checked 753d44dd8a51 drm/amdgpu: DC also loves to allocate stuff where it shouldn't -:70: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #70: FILE: drivers/gpu/drm/amd/display/dc/core/dc.c:1420: + * atomic_commit_tail. */ -:76: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 27 lines checked 838703bb63b9 drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail -:39: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif #39: FILE: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6917: +#if 0 -:55: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 23 lines checked 6fd3e8ef0756 drm/scheduler: use dma-fence annotations in tdr work -:28: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'? #28: Hence split out as a seperate patch. -:114: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 20 lines checked 552ee41a6739 drm/amdgpu: use dma-fence annotations for gpu reset code 1bb25e8d8189 Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" -:145: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 16 lines checked 77ef9df05cc0 drm/amdgpu: gpu recovery does full modesets -:186: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 14 lines checked 4db85879be37 drm/i915: Annotate dma_fence_work -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 15 lines checked From patchwork at emeril.freedesktop.org Thu Jun 4 08:57:08 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 08:57:08 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?dma-fence_lockdep_annotations=2C_round_2?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159126102813.14555.4341433947486233055@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '<asn:2>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '<asn:2> From thomas_os at shipmail.org Thu Jun 4 08:57:35 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Thu, 4 Jun 2020 10:57:35 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <20200604081224.863494-4-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> Message-ID: <edbfc1aa-9297-8202-cef8-1facafaa0dfe@shipmail.org> On 6/4/20 10:12 AM, Daniel Vetter wrote: ... > Thread A: > > mutex_lock(A); > mutex_unlock(A); > > dma_fence_signal(); > > Thread B: > > mutex_lock(A); > dma_fence_wait(); > mutex_unlock(A); > > Thread B is blocked on A signalling the fence, but A never gets around > to that because it cannot acquire the lock A. > > Note that dma_fence_wait() is allowed to be nested within > dma_fence_begin/end_signalling sections. To allow this to happen the > read lock needs to be upgraded to a write lock, which means that any > other lock is acquired between the dma_fence_begin_signalling() call and > the call to dma_fence_wait(), and still held, this will result in an > immediate lockdep complaint. The only other option would be to not > annotate such calls, defeating the point. Therefore these annotations > cannot be sprinkled over the code entirely mindless to avoid false > positives. Just realized, isn't that example actually a true positive, or at least a great candidate for a true positive, since if another thread reenters that signaling path, it will block on that mutex, and the fence would never be signaled unless there is another signaling path? Although I agree the conclusion is sound: These annotations cannot be sprinkled mindlessly over the code. /Thomas > > v2: handle soft/hardirq ctx better against write side and dont forget > EXPORT_SYMBOL, drivers can't use this otherwise. > > v3: Kerneldoc. > > v4: Some spelling fixes from Mika > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > Cc: linux-media at vger.kernel.org > Cc: linaro-mm-sig at lists.linaro.org > Cc: linux-rdma at vger.kernel.org > Cc: amd-gfx at lists.freedesktop.org > Cc: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > Documentation/driver-api/dma-buf.rst | 12 +- > drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ > include/linux/dma-fence.h | 12 ++ > 3 files changed, 182 insertions(+), 3 deletions(-) > > diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > index 63dec76d1d8d..05d856131140 100644 > --- a/Documentation/driver-api/dma-buf.rst > +++ b/Documentation/driver-api/dma-buf.rst > @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > .. kernel-doc:: drivers/dma-buf/dma-buf.c > :doc: cpu access > > -Fence Poll Support > -~~~~~~~~~~~~~~~~~~ > +Implicit Fence Poll Support > +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > - :doc: fence polling > + :doc: implicit fence polling > > Kernel Functions and Structures Reference > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > @@ -133,6 +133,12 @@ DMA Fences > .. kernel-doc:: drivers/dma-buf/dma-fence.c > :doc: DMA fences overview > > +DMA Fence Signalling Annotations > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +.. kernel-doc:: drivers/dma-buf/dma-fence.c > + :doc: fence signalling annotation > + > DMA Fences Functions Reference > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > index 656e9ac2d028..0005bc002529 100644 > --- a/drivers/dma-buf/dma-fence.c > +++ b/drivers/dma-buf/dma-fence.c > @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) > } > EXPORT_SYMBOL(dma_fence_context_alloc); > > +/** > + * DOC: fence signalling annotation > + * > + * Proving correctness of all the kernel code around &dma_fence through code > + * review and testing is tricky for a few reasons: > + * > + * * It is a cross-driver contract, and therefore all drivers must follow the > + * same rules for lock nesting order, calling contexts for various functions > + * and anything else significant for in-kernel interfaces. But it is also > + * impossible to test all drivers in a single machine, hence brute-force N vs. > + * N testing of all combinations is impossible. Even just limiting to the > + * possible combinations is infeasible. > + * > + * * There is an enormous amount of driver code involved. For render drivers > + * there's the tail of command submission, after fences are published, > + * scheduler code, interrupt and workers to process job completion, > + * and timeout, gpu reset and gpu hang recovery code. Plus for integration > + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, > + * and &shrinker. For modesetting drivers there's the commit tail functions > + * between when fences for an atomic modeset are published, and when the > + * corresponding vblank completes, including any interrupt processing and > + * related workers. Auditing all that code, across all drivers, is not > + * feasible. > + * > + * * Due to how many other subsystems are involved and the locking hierarchies > + * this pulls in there is extremely thin wiggle-room for driver-specific > + * differences. &dma_fence interacts with almost all of the core memory > + * handling through page fault handlers via &dma_resv, dma_resv_lock() and > + * dma_resv_unlock(). On the other side it also interacts through all > + * allocation sites through &mmu_notifier and &shrinker. > + * > + * Furthermore lockdep does not handle cross-release dependencies, which means > + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught > + * at runtime with some quick testing. The simplest example is one thread > + * waiting on a &dma_fence while holding a lock:: > + * > + * lock(A); > + * dma_fence_wait(B); > + * unlock(A); > + * > + * while the other thread is stuck trying to acquire the same lock, which > + * prevents it from signalling the fence the previous thread is stuck waiting > + * on:: > + * > + * lock(A); > + * unlock(A); > + * dma_fence_signal(B); > + * > + * By manually annotating all code relevant to signalling a &dma_fence we can > + * teach lockdep about these dependencies, which also helps with the validation > + * headache since now lockdep can check all the rules for us:: > + * > + * cookie = dma_fence_begin_signalling(); > + * lock(A); > + * unlock(A); > + * dma_fence_signal(B); > + * dma_fence_end_signalling(cookie); > + * > + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to > + * annotate critical sections the following rules need to be observed: > + * > + * * All code necessary to complete a &dma_fence must be annotated, from the > + * point where a fence is accessible to other threads, to the point where > + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, > + * and due to the very strict rules and many corner cases it is infeasible to > + * catch these just with review or normal stress testing. > + * > + * * &struct dma_resv deserves a special note, since the readers are only > + * protected by rcu. This means the signalling critical section starts as soon > + * as the new fences are installed, even before dma_resv_unlock() is called. > + * > + * * The only exception are fast paths and opportunistic signalling code, which > + * calls dma_fence_signal() purely as an optimization, but is not required to > + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL > + * which calls dma_fence_signal(), while the mandatory completion path goes > + * through a hardware interrupt and possible job completion worker. > + * > + * * To aid composability of code, the annotations can be freely nested, as long > + * as the overall locking hierarchy is consistent. The annotations also work > + * both in interrupt and process context. Due to implementation details this > + * requires that callers pass an opaque cookie from > + * dma_fence_begin_signalling() to dma_fence_end_signalling(). > + * > + * * Validation against the cross driver contract is implemented by priming > + * lockdep with the relevant hierarchy at boot-up. This means even just > + * testing with a single device is enough to validate a driver, at least as > + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are > + * concerned. > + */ > +#ifdef CONFIG_LOCKDEP > +struct lockdep_map dma_fence_lockdep_map = { > + .name = "dma_fence_map" > +}; > + > +/** > + * dma_fence_begin_signalling - begin a critical DMA fence signalling section > + * > + * Drivers should use this to annotate the beginning of any code section > + * required to eventually complete &dma_fence by calling dma_fence_signal(). > + * > + * The end of these critical sections are annotated with > + * dma_fence_end_signalling(). > + * > + * Returns: > + * > + * Opaque cookie needed by the implementation, which needs to be passed to > + * dma_fence_end_signalling(). > + */ > +bool dma_fence_begin_signalling(void) > +{ > + /* explicitly nesting ... */ > + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) > + return true; > + > + /* rely on might_sleep check for soft/hardirq locks */ > + if (in_atomic()) > + return true; > + > + /* ... and non-recursive readlock */ > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > + > + return false; > +} > +EXPORT_SYMBOL(dma_fence_begin_signalling); > + > +/** > + * dma_fence_end_signalling - end a critical DMA fence signalling section > + * > + * Closes a critical section annotation opened by dma_fence_begin_signalling(). > + */ > +void dma_fence_end_signalling(bool cookie) > +{ > + if (cookie) > + return; > + > + lock_release(&dma_fence_lockdep_map, _RET_IP_); > +} > +EXPORT_SYMBOL(dma_fence_end_signalling); > + > +void __dma_fence_might_wait(void) > +{ > + bool tmp; > + > + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); > + if (tmp) > + lock_release(&dma_fence_lockdep_map, _THIS_IP_); > + lock_map_acquire(&dma_fence_lockdep_map); > + lock_map_release(&dma_fence_lockdep_map); > + if (tmp) > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > +} > +#endif > + > + > /** > * dma_fence_signal_locked - signal completion of a fence > * @fence: the fence to signal > @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) > { > unsigned long flags; > int ret; > + bool tmp; > > if (!fence) > return -EINVAL; > > + tmp = dma_fence_begin_signalling(); > + > spin_lock_irqsave(fence->lock, flags); > ret = dma_fence_signal_locked(fence); > spin_unlock_irqrestore(fence->lock, flags); > > + dma_fence_end_signalling(tmp); > + > return ret; > } > EXPORT_SYMBOL(dma_fence_signal); > @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) > > might_sleep(); > > + __dma_fence_might_wait(); > + > trace_dma_fence_wait_start(fence); > if (fence->ops->wait) > ret = fence->ops->wait(fence, intr, timeout); > diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h > index 3347c54f3a87..3f288f7db2ef 100644 > --- a/include/linux/dma-fence.h > +++ b/include/linux/dma-fence.h > @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) > } while (1); > } > > +#ifdef CONFIG_LOCKDEP > +bool dma_fence_begin_signalling(void); > +void dma_fence_end_signalling(bool cookie); > +#else > +static inline bool dma_fence_begin_signalling(void) > +{ > + return true; > +} > +static inline void dma_fence_end_signalling(bool cookie) {} > +static inline void __dma_fence_might_wait(void) {} > +#endif > + > int dma_fence_signal(struct dma_fence *fence); > int dma_fence_signal_locked(struct dma_fence *fence); > signed long dma_fence_default_wait(struct dma_fence *fence, From patchwork at emeril.freedesktop.org Thu Jun 4 09:08:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 09:08:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZG1h?= =?utf-8?q?-fence_lockdep_annotations=2C_round_2?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159126170083.14555.15660446529910252360@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 URL : https://patchwork.freedesktop.org/series/77986/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8580 -> Patchwork_17864 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17864 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17864, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17864: ### IGT changes ### #### Possible regressions #### * igt at gem_close_race@basic-process: - fi-ivb-3770: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-ivb-3770/igt at gem_close_race@basic-process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-ivb-3770/igt at gem_close_race@basic-process.html - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-byt-j1900/igt at gem_close_race@basic-process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-byt-j1900/igt at gem_close_race@basic-process.html - fi-hsw-4770: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-hsw-4770/igt at gem_close_race@basic-process.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-hsw-4770/igt at gem_close_race@basic-process.html - fi-byt-n2820: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-byt-n2820/igt at gem_close_race@basic-process.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-byt-n2820/igt at gem_close_race@basic-process.html * igt at gem_tiled_blits@basic: - fi-pnv-d510: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-pnv-d510/igt at gem_tiled_blits@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-pnv-d510/igt at gem_tiled_blits@basic.html * igt at kms_busy@basic at flip: - fi-snb-2600: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-snb-2600/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-snb-2600/igt at kms_busy@basic at flip.html - fi-snb-2520m: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-snb-2520m/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-snb-2520m/igt at kms_busy@basic at flip.html * igt at kms_frontbuffer_tracking@basic: - fi-ilk-650: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html * igt at runner@aborted: - fi-pnv-d510: NOTRUN -> [FAIL][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-pnv-d510/igt at runner@aborted.html - fi-cfl-8700k: NOTRUN -> [FAIL][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cfl-8700k/igt at runner@aborted.html - fi-tgl-y: NOTRUN -> [FAIL][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-tgl-y/igt at runner@aborted.html - fi-cfl-8109u: NOTRUN -> [FAIL][20] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cfl-8109u/igt at runner@aborted.html - fi-icl-u2: NOTRUN -> [FAIL][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-icl-u2/igt at runner@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][22] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-snb-2520m/igt at runner@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][23] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-bdw-5557u/igt at runner@aborted.html - fi-byt-n2820: NOTRUN -> [FAIL][24] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-byt-n2820/igt at runner@aborted.html - fi-icl-guc: NOTRUN -> [FAIL][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-icl-guc/igt at runner@aborted.html - fi-hsw-4770: NOTRUN -> [FAIL][26] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-hsw-4770/igt at runner@aborted.html - fi-snb-2600: NOTRUN -> [FAIL][27] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-snb-2600/igt at runner@aborted.html - fi-whl-u: NOTRUN -> [FAIL][28] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-whl-u/igt at runner@aborted.html - fi-cml-u2: NOTRUN -> [FAIL][29] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cml-u2/igt at runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][30] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-ivb-3770/igt at runner@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][31] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-bxt-dsi/igt at runner@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][32] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-byt-j1900/igt at runner@aborted.html - fi-cml-s: NOTRUN -> [FAIL][33] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cml-s/igt at runner@aborted.html - fi-cfl-guc: NOTRUN -> [FAIL][34] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cfl-guc/igt at runner@aborted.html - fi-icl-y: NOTRUN -> [FAIL][35] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-icl-y/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_busy@busy at all}: - fi-kbl-x1275: [PASS][36] -> [DMESG-WARN][37] [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-kbl-x1275/igt at gem_busy@busy at all.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-kbl-x1275/igt at gem_busy@busy at all.html - fi-cfl-8700k: [PASS][38] -> [DMESG-WARN][39] [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-cfl-8700k/igt at gem_busy@busy at all.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cfl-8700k/igt at gem_busy@busy at all.html - fi-tgl-y: [PASS][40] -> [DMESG-WARN][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-tgl-y/igt at gem_busy@busy at all.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-tgl-y/igt at gem_busy@busy at all.html - fi-skl-6600u: [PASS][42] -> [DMESG-WARN][43] [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-skl-6600u/igt at gem_busy@busy at all.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-skl-6600u/igt at gem_busy@busy at all.html - fi-cfl-8109u: [PASS][44] -> [DMESG-WARN][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-cfl-8109u/igt at gem_busy@busy at all.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cfl-8109u/igt at gem_busy@busy at all.html - fi-icl-u2: [PASS][46] -> [DMESG-WARN][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-icl-u2/igt at gem_busy@busy at all.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-icl-u2/igt at gem_busy@busy at all.html - {fi-tgl-dsi}: [PASS][48] -> [DMESG-WARN][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-tgl-dsi/igt at gem_busy@busy at all.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-tgl-dsi/igt at gem_busy@busy at all.html - fi-glk-dsi: [PASS][50] -> [DMESG-WARN][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-glk-dsi/igt at gem_busy@busy at all.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-glk-dsi/igt at gem_busy@busy at all.html - fi-kbl-8809g: [PASS][52] -> [DMESG-WARN][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-kbl-8809g/igt at gem_busy@busy at all.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-kbl-8809g/igt at gem_busy@busy at all.html - fi-skl-lmem: [PASS][54] -> [DMESG-WARN][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-skl-lmem/igt at gem_busy@busy at all.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-skl-lmem/igt at gem_busy@busy at all.html - fi-kbl-r: [PASS][56] -> [DMESG-WARN][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-kbl-r/igt at gem_busy@busy at all.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-kbl-r/igt at gem_busy@busy at all.html - fi-bdw-5557u: [PASS][58] -> [DMESG-WARN][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-bdw-5557u/igt at gem_busy@busy at all.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-bdw-5557u/igt at gem_busy@busy at all.html - fi-icl-guc: [PASS][60] -> [DMESG-WARN][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-icl-guc/igt at gem_busy@busy at all.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-icl-guc/igt at gem_busy@busy at all.html - fi-kbl-soraka: [PASS][62] -> [DMESG-WARN][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-kbl-soraka/igt at gem_busy@busy at all.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-kbl-soraka/igt at gem_busy@busy at all.html - {fi-ehl-1}: [PASS][64] -> [DMESG-WARN][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-ehl-1/igt at gem_busy@busy at all.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-ehl-1/igt at gem_busy@busy at all.html - fi-kbl-7500u: [PASS][66] -> [DMESG-WARN][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-kbl-7500u/igt at gem_busy@busy at all.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-kbl-7500u/igt at gem_busy@busy at all.html - fi-kbl-guc: [PASS][68] -> [DMESG-WARN][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-kbl-guc/igt at gem_busy@busy at all.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-kbl-guc/igt at gem_busy@busy at all.html - fi-whl-u: [PASS][70] -> [DMESG-WARN][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-whl-u/igt at gem_busy@busy at all.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-whl-u/igt at gem_busy@busy at all.html - fi-cml-u2: [PASS][72] -> [DMESG-WARN][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-cml-u2/igt at gem_busy@busy at all.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cml-u2/igt at gem_busy@busy at all.html - fi-bxt-dsi: [PASS][74] -> [DMESG-WARN][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-bxt-dsi/igt at gem_busy@busy at all.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-bxt-dsi/igt at gem_busy@busy at all.html - {fi-tgl-u}: [PASS][76] -> [DMESG-WARN][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-tgl-u/igt at gem_busy@busy at all.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-tgl-u/igt at gem_busy@busy at all.html - fi-cml-s: [PASS][78] -> [DMESG-WARN][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-cml-s/igt at gem_busy@busy at all.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cml-s/igt at gem_busy@busy at all.html - fi-cfl-guc: [PASS][80] -> [DMESG-WARN][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-cfl-guc/igt at gem_busy@busy at all.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-cfl-guc/igt at gem_busy@busy at all.html - fi-icl-y: [PASS][82] -> [DMESG-WARN][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-icl-y/igt at gem_busy@busy at all.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-icl-y/igt at gem_busy@busy at all.html - fi-skl-guc: [PASS][84] -> [DMESG-WARN][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-skl-guc/igt at gem_busy@busy at all.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-skl-guc/igt at gem_busy@busy at all.html - fi-skl-6700k2: [PASS][86] -> [DMESG-WARN][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-skl-6700k2/igt at gem_busy@busy at all.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-skl-6700k2/igt at gem_busy@busy at all.html * igt at runner@aborted: - {fi-tgl-dsi}: NOTRUN -> [FAIL][88] [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-tgl-dsi/igt at runner@aborted.html - {fi-ehl-1}: NOTRUN -> [FAIL][89] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-ehl-1/igt at runner@aborted.html - {fi-tgl-u}: NOTRUN -> [FAIL][90] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-tgl-u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17864 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-kbl-soraka: [PASS][91] -> [DMESG-WARN][92] ([i915#1982]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8580/fi-kbl-soraka/igt at debugfs_test@read_all_entries.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/fi-kbl-soraka/igt at debugfs_test@read_all_entries.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8580 -> Patchwork_17864 CI-20190529: 20190529 CI_DRM_8580: dbab119950f978cd41000b0daba1ff332e5b0856 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17864: 4db85879be37fd460696d0ea753a5eb243880719 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4db85879be37 drm/i915: Annotate dma_fence_work 77ef9df05cc0 drm/amdgpu: gpu recovery does full modesets 1bb25e8d8189 Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" 552ee41a6739 drm/amdgpu: use dma-fence annotations for gpu reset code 6fd3e8ef0756 drm/scheduler: use dma-fence annotations in tdr work 838703bb63b9 drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail 753d44dd8a51 drm/amdgpu: DC also loves to allocate stuff where it shouldn't 05627337ac19 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code 82020872a9a2 drm/amdgpu: use dma-fence annotations in cs_submit() 0485794be8aa drm/scheduler: use dma-fence annotations in main thread 911b274bb909 drm/amdgpu: add dma-fence annotations to atomic commit path 9d42aa205b3f drm/atomic-helper: Add dma-fence annotations 93efe4f7dc82 drm/vblank: Annotate with dma-fence signalling section 2fb5c8b43ac8 drm/vkms: Annotate vblank timer 96b50a5032df dma-fence: prime lockdep annotations 7f8c3b44f8eb dma-fence: basic lockdep annotations b85d9997eaca dma-buf: minor doc touch-ups 199c3f9df986 mm: Track mmu notifiers in fs_reclaim_acquire/release == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17864/index.html From daniel.vetter at ffwll.ch Thu Jun 4 09:21:46 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 11:21:46 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <edbfc1aa-9297-8202-cef8-1facafaa0dfe@shipmail.org> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <edbfc1aa-9297-8202-cef8-1facafaa0dfe@shipmail.org> Message-ID: <CAKMK7uGLAPvvgHCCZhg0cea3Fz=Zqhf-GKS2OC3mZudYe3mKhw@mail.gmail.com> On Thu, Jun 4, 2020 at 10:57 AM Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> wrote: > > > On 6/4/20 10:12 AM, Daniel Vetter wrote: > ... > > Thread A: > > > > mutex_lock(A); > > mutex_unlock(A); > > > > dma_fence_signal(); > > > > Thread B: > > > > mutex_lock(A); > > dma_fence_wait(); > > mutex_unlock(A); > > > > Thread B is blocked on A signalling the fence, but A never gets around > > to that because it cannot acquire the lock A. > > > > Note that dma_fence_wait() is allowed to be nested within > > dma_fence_begin/end_signalling sections. To allow this to happen the > > read lock needs to be upgraded to a write lock, which means that any > > other lock is acquired between the dma_fence_begin_signalling() call and > > the call to dma_fence_wait(), and still held, this will result in an > > immediate lockdep complaint. The only other option would be to not > > annotate such calls, defeating the point. Therefore these annotations > > cannot be sprinkled over the code entirely mindless to avoid false > > positives. > > Just realized, isn't that example actually a true positive, or at least > a great candidate for a true positive, since if another thread reenters > that signaling path, it will block on that mutex, and the fence would > never be signaled unless there is another signaling path? Not sure I understand fully, but I think the answer is "it's complicated". dma_fence are meant to be a DAG (directed acyclic graph). Now it would be nice to enforce that, and i915 has some attempts to that effect, but these annotations here don't try to pull off that miracle. I'm assuming that all the dependencies between dma_fence don't create a loop, and instead I'm only focusing on deadlocks between dma_fences and other locks. Usually an async work looks like this: 1. wait for a bunch of dma_fence that we have as dependencies 2. do work (e.g. atomic commit) 3. signal the dma_fence that represents our work This can happen on the cpu in a kthread or worker, or on the gpu. Now for reasons you might want to have a per-work mutex or something and hold that while going through all this, and this is the false positive I'm thinking off. Of course, if your fences aren't a DAG, or if you're holding a mutex that's shared with some other work which is part of your dependency chain, then this goes boom. But it doesn't have to. I think in general it's best to purely rely on ordering, and remove as much locking as possible. This is the design behind the atomic modeset commit code, which is does not take any mutexes in the commit path, at least not in the helpers. Drivers can still do stuff of course. Then the only locks you're left with are spinlocks (maybe irq safe ones) to coordinate with interrupt handlers, workers, handle the wait/wake queues, manage work/scheduler run queues and all that stuff, and no spinlocks. Now for the case where you have something like the below: thread 1: dma_fence_begin_signalling() mutex_lock(a); dma_fence_wait(b1); mutex_unlock(a); dma_fence_signal(b2); dma_fence_end_signalling(); That's indeed a bit problematic, assuming you're annotating stuff correctly, and the locking is actually required. I've seen a few of these, and annotating the properly needs care: - often the mutex_lock/unlock is not needed, and just gets in the way. This was the case for the original atomic modeset commit work patches, which again locked all the modeset locks. But strict ordering of commit work was all that was needed to make this work, plus making sure data structure lifetimes are handled correctly too. I think the tendency to abuse locking to handle lifetime and ordering problems is fairly common, but it can lead to lots of trouble. Ime all async work items with the above problematic pattern can be fixed like this. - other often case is that the dma_fence_begin_signalling() can&should be pushed down past the mutex_lock, and maybe even past the dma_fence_wait, depending upon when/how the dma_fence is published. The fence signalling critical section can still extend past the mutex_unlock, lockdep and semantics are fine with that (I think at least). This is more the case for execbuf tails, where you take locks, set up some async work, publish the fences and then begin to process these fences (which could just be pushing the work to the job scheduler, but could also involve running it directly in the userspace process thread context, but with locks already dropped). So I wouldn't go out and say these are true positives, just maybe unecessary locking and over-eager annotations, without any real bugs in the code. Or am I completely off the track and you're thinking of something else? > Although I agree the conclusion is sound: These annotations cannot be > sprinkled mindlessly over the code. Yup, that much is for sure. -Daniel > > /Thomas > > > > > > > > > > v2: handle soft/hardirq ctx better against write side and dont forget > > EXPORT_SYMBOL, drivers can't use this otherwise. > > > > v3: Kerneldoc. > > > > v4: Some spelling fixes from Mika > > > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > > Cc: linux-media at vger.kernel.org > > Cc: linaro-mm-sig at lists.linaro.org > > Cc: linux-rdma at vger.kernel.org > > Cc: amd-gfx at lists.freedesktop.org > > Cc: intel-gfx at lists.freedesktop.org > > Cc: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > --- > > Documentation/driver-api/dma-buf.rst | 12 +- > > drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ > > include/linux/dma-fence.h | 12 ++ > > 3 files changed, 182 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > > index 63dec76d1d8d..05d856131140 100644 > > --- a/Documentation/driver-api/dma-buf.rst > > +++ b/Documentation/driver-api/dma-buf.rst > > @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > > :doc: cpu access > > > > -Fence Poll Support > > -~~~~~~~~~~~~~~~~~~ > > +Implicit Fence Poll Support > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > > - :doc: fence polling > > + :doc: implicit fence polling > > > > Kernel Functions and Structures Reference > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > @@ -133,6 +133,12 @@ DMA Fences > > .. kernel-doc:: drivers/dma-buf/dma-fence.c > > :doc: DMA fences overview > > > > +DMA Fence Signalling Annotations > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > + > > +.. kernel-doc:: drivers/dma-buf/dma-fence.c > > + :doc: fence signalling annotation > > + > > DMA Fences Functions Reference > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > > index 656e9ac2d028..0005bc002529 100644 > > --- a/drivers/dma-buf/dma-fence.c > > +++ b/drivers/dma-buf/dma-fence.c > > @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) > > } > > EXPORT_SYMBOL(dma_fence_context_alloc); > > > > +/** > > + * DOC: fence signalling annotation > > + * > > + * Proving correctness of all the kernel code around &dma_fence through code > > + * review and testing is tricky for a few reasons: > > + * > > + * * It is a cross-driver contract, and therefore all drivers must follow the > > + * same rules for lock nesting order, calling contexts for various functions > > + * and anything else significant for in-kernel interfaces. But it is also > > + * impossible to test all drivers in a single machine, hence brute-force N vs. > > + * N testing of all combinations is impossible. Even just limiting to the > > + * possible combinations is infeasible. > > + * > > + * * There is an enormous amount of driver code involved. For render drivers > > + * there's the tail of command submission, after fences are published, > > + * scheduler code, interrupt and workers to process job completion, > > + * and timeout, gpu reset and gpu hang recovery code. Plus for integration > > + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, > > + * and &shrinker. For modesetting drivers there's the commit tail functions > > + * between when fences for an atomic modeset are published, and when the > > + * corresponding vblank completes, including any interrupt processing and > > + * related workers. Auditing all that code, across all drivers, is not > > + * feasible. > > + * > > + * * Due to how many other subsystems are involved and the locking hierarchies > > + * this pulls in there is extremely thin wiggle-room for driver-specific > > + * differences. &dma_fence interacts with almost all of the core memory > > + * handling through page fault handlers via &dma_resv, dma_resv_lock() and > > + * dma_resv_unlock(). On the other side it also interacts through all > > + * allocation sites through &mmu_notifier and &shrinker. > > + * > > + * Furthermore lockdep does not handle cross-release dependencies, which means > > + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught > > + * at runtime with some quick testing. The simplest example is one thread > > + * waiting on a &dma_fence while holding a lock:: > > + * > > + * lock(A); > > + * dma_fence_wait(B); > > + * unlock(A); > > + * > > + * while the other thread is stuck trying to acquire the same lock, which > > + * prevents it from signalling the fence the previous thread is stuck waiting > > + * on:: > > + * > > + * lock(A); > > + * unlock(A); > > + * dma_fence_signal(B); > > + * > > + * By manually annotating all code relevant to signalling a &dma_fence we can > > + * teach lockdep about these dependencies, which also helps with the validation > > + * headache since now lockdep can check all the rules for us:: > > + * > > + * cookie = dma_fence_begin_signalling(); > > + * lock(A); > > + * unlock(A); > > + * dma_fence_signal(B); > > + * dma_fence_end_signalling(cookie); > > + * > > + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to > > + * annotate critical sections the following rules need to be observed: > > + * > > + * * All code necessary to complete a &dma_fence must be annotated, from the > > + * point where a fence is accessible to other threads, to the point where > > + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, > > + * and due to the very strict rules and many corner cases it is infeasible to > > + * catch these just with review or normal stress testing. > > + * > > + * * &struct dma_resv deserves a special note, since the readers are only > > + * protected by rcu. This means the signalling critical section starts as soon > > + * as the new fences are installed, even before dma_resv_unlock() is called. > > + * > > + * * The only exception are fast paths and opportunistic signalling code, which > > + * calls dma_fence_signal() purely as an optimization, but is not required to > > + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL > > + * which calls dma_fence_signal(), while the mandatory completion path goes > > + * through a hardware interrupt and possible job completion worker. > > + * > > + * * To aid composability of code, the annotations can be freely nested, as long > > + * as the overall locking hierarchy is consistent. The annotations also work > > + * both in interrupt and process context. Due to implementation details this > > + * requires that callers pass an opaque cookie from > > + * dma_fence_begin_signalling() to dma_fence_end_signalling(). > > + * > > + * * Validation against the cross driver contract is implemented by priming > > + * lockdep with the relevant hierarchy at boot-up. This means even just > > + * testing with a single device is enough to validate a driver, at least as > > + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are > > + * concerned. > > + */ > > +#ifdef CONFIG_LOCKDEP > > +struct lockdep_map dma_fence_lockdep_map = { > > + .name = "dma_fence_map" > > +}; > > + > > +/** > > + * dma_fence_begin_signalling - begin a critical DMA fence signalling section > > + * > > + * Drivers should use this to annotate the beginning of any code section > > + * required to eventually complete &dma_fence by calling dma_fence_signal(). > > + * > > + * The end of these critical sections are annotated with > > + * dma_fence_end_signalling(). > > + * > > + * Returns: > > + * > > + * Opaque cookie needed by the implementation, which needs to be passed to > > + * dma_fence_end_signalling(). > > + */ > > +bool dma_fence_begin_signalling(void) > > +{ > > + /* explicitly nesting ... */ > > + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) > > + return true; > > + > > + /* rely on might_sleep check for soft/hardirq locks */ > > + if (in_atomic()) > > + return true; > > + > > + /* ... and non-recursive readlock */ > > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > > + > > + return false; > > +} > > +EXPORT_SYMBOL(dma_fence_begin_signalling); > > + > > +/** > > + * dma_fence_end_signalling - end a critical DMA fence signalling section > > + * > > + * Closes a critical section annotation opened by dma_fence_begin_signalling(). > > + */ > > +void dma_fence_end_signalling(bool cookie) > > +{ > > + if (cookie) > > + return; > > + > > + lock_release(&dma_fence_lockdep_map, _RET_IP_); > > +} > > +EXPORT_SYMBOL(dma_fence_end_signalling); > > + > > +void __dma_fence_might_wait(void) > > +{ > > + bool tmp; > > + > > + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); > > + if (tmp) > > + lock_release(&dma_fence_lockdep_map, _THIS_IP_); > > + lock_map_acquire(&dma_fence_lockdep_map); > > + lock_map_release(&dma_fence_lockdep_map); > > + if (tmp) > > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > > +} > > +#endif > > + > > + > > /** > > * dma_fence_signal_locked - signal completion of a fence > > * @fence: the fence to signal > > @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) > > { > > unsigned long flags; > > int ret; > > + bool tmp; > > > > if (!fence) > > return -EINVAL; > > > > + tmp = dma_fence_begin_signalling(); > > + > > spin_lock_irqsave(fence->lock, flags); > > ret = dma_fence_signal_locked(fence); > > spin_unlock_irqrestore(fence->lock, flags); > > > > + dma_fence_end_signalling(tmp); > > + > > return ret; > > } > > EXPORT_SYMBOL(dma_fence_signal); > > @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) > > > > might_sleep(); > > > > + __dma_fence_might_wait(); > > + > > trace_dma_fence_wait_start(fence); > > if (fence->ops->wait) > > ret = fence->ops->wait(fence, intr, timeout); > > diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h > > index 3347c54f3a87..3f288f7db2ef 100644 > > --- a/include/linux/dma-fence.h > > +++ b/include/linux/dma-fence.h > > @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) > > } while (1); > > } > > > > +#ifdef CONFIG_LOCKDEP > > +bool dma_fence_begin_signalling(void); > > +void dma_fence_end_signalling(bool cookie); > > +#else > > +static inline bool dma_fence_begin_signalling(void) > > +{ > > + return true; > > +} > > +static inline void dma_fence_end_signalling(bool cookie) {} > > +static inline void __dma_fence_might_wait(void) {} > > +#endif > > + > > int dma_fence_signal(struct dma_fence *fence); > > int dma_fence_signal_locked(struct dma_fence *fence); > > signed long dma_fence_default_wait(struct dma_fence *fence, -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From chris at chris-wilson.co.uk Thu Jun 4 09:26:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 04 Jun 2020 10:26:58 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <CAKMK7uGLAPvvgHCCZhg0cea3Fz=Zqhf-GKS2OC3mZudYe3mKhw@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <edbfc1aa-9297-8202-cef8-1facafaa0dfe@shipmail.org> <CAKMK7uGLAPvvgHCCZhg0cea3Fz=Zqhf-GKS2OC3mZudYe3mKhw@mail.gmail.com> Message-ID: <159126281827.25109.3992161193069793005@build.alporthouse.com> Quoting Daniel Vetter (2020-06-04 10:21:46) > On Thu, Jun 4, 2020 at 10:57 AM Thomas Hellstr?m (Intel) > <thomas_os at shipmail.org> wrote: > > > > > > On 6/4/20 10:12 AM, Daniel Vetter wrote: > > ... > > > Thread A: > > > > > > mutex_lock(A); > > > mutex_unlock(A); > > > > > > dma_fence_signal(); > > > > > > Thread B: > > > > > > mutex_lock(A); > > > dma_fence_wait(); > > > mutex_unlock(A); > > > > > > Thread B is blocked on A signalling the fence, but A never gets around > > > to that because it cannot acquire the lock A. > > > > > > Note that dma_fence_wait() is allowed to be nested within > > > dma_fence_begin/end_signalling sections. To allow this to happen the > > > read lock needs to be upgraded to a write lock, which means that any > > > other lock is acquired between the dma_fence_begin_signalling() call and > > > the call to dma_fence_wait(), and still held, this will result in an > > > immediate lockdep complaint. The only other option would be to not > > > annotate such calls, defeating the point. Therefore these annotations > > > cannot be sprinkled over the code entirely mindless to avoid false > > > positives. > > > > Just realized, isn't that example actually a true positive, or at least > > a great candidate for a true positive, since if another thread reenters > > that signaling path, it will block on that mutex, and the fence would > > never be signaled unless there is another signaling path? > > Not sure I understand fully, but I think the answer is "it's complicated". See cd8084f91c02 ("locking/lockdep: Apply crossrelease to completions") dma_fence usage here is nothing but another name for a completion. -Chris From jani.nikula at intel.com Thu Jun 4 09:31:48 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Thu, 04 Jun 2020 12:31:48 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/params: fix i915.reset module param type In-Reply-To: <159111100381.29407.10499392760570265777@build.alporthouse.com> References: <20200602151126.25626-1-jani.nikula@intel.com> <159111100381.29407.10499392760570265777@build.alporthouse.com> Message-ID: <871rmvyy63.fsf@intel.com> On Tue, 02 Jun 2020, Chris Wilson <chris at chris-wilson.co.uk> wrote: > Quoting Jani Nikula (2020-06-02 16:11:26) >> The reset member in i915_params was previously changed to unsigned, but >> this failed to change the actual module parameter. >> >> Fixes: aae970d8454b ("drm/i915: Mark i915.reset as unsigned") >> Cc: Chris Wilson <chris at chris-wilson.co.uk> >> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> >> Signed-off-by: Jani Nikula <jani.nikula at intel.com> > Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> Thanks, pushed. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center From daniel.vetter at ffwll.ch Thu Jun 4 09:36:24 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 11:36:24 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <159126281827.25109.3992161193069793005@build.alporthouse.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <edbfc1aa-9297-8202-cef8-1facafaa0dfe@shipmail.org> <CAKMK7uGLAPvvgHCCZhg0cea3Fz=Zqhf-GKS2OC3mZudYe3mKhw@mail.gmail.com> <159126281827.25109.3992161193069793005@build.alporthouse.com> Message-ID: <CAKMK7uHOcH+rWhor7zzqqcjCUtxz_-5stLAOVD=4_ED+QjN8oQ@mail.gmail.com> On Thu, Jun 4, 2020 at 11:27 AM Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Quoting Daniel Vetter (2020-06-04 10:21:46) > > On Thu, Jun 4, 2020 at 10:57 AM Thomas Hellstr?m (Intel) > > <thomas_os at shipmail.org> wrote: > > > > > > > > > On 6/4/20 10:12 AM, Daniel Vetter wrote: > > > ... > > > > Thread A: > > > > > > > > mutex_lock(A); > > > > mutex_unlock(A); > > > > > > > > dma_fence_signal(); > > > > > > > > Thread B: > > > > > > > > mutex_lock(A); > > > > dma_fence_wait(); > > > > mutex_unlock(A); > > > > > > > > Thread B is blocked on A signalling the fence, but A never gets around > > > > to that because it cannot acquire the lock A. > > > > > > > > Note that dma_fence_wait() is allowed to be nested within > > > > dma_fence_begin/end_signalling sections. To allow this to happen the > > > > read lock needs to be upgraded to a write lock, which means that any > > > > other lock is acquired between the dma_fence_begin_signalling() call and > > > > the call to dma_fence_wait(), and still held, this will result in an > > > > immediate lockdep complaint. The only other option would be to not > > > > annotate such calls, defeating the point. Therefore these annotations > > > > cannot be sprinkled over the code entirely mindless to avoid false > > > > positives. > > > > > > Just realized, isn't that example actually a true positive, or at least > > > a great candidate for a true positive, since if another thread reenters > > > that signaling path, it will block on that mutex, and the fence would > > > never be signaled unless there is another signaling path? > > > > Not sure I understand fully, but I think the answer is "it's complicated". > > See cd8084f91c02 ("locking/lockdep: Apply crossrelease to completions") > > dma_fence usage here is nothing but another name for a completion. Quoting from my previous cover letter: "I've dragged my feet for years on this, hoping that cross-release lockdep would do this for us, but well that never really happened unfortunately. So here we are." I discussed this with Peter, cross-release not getting in is pretty final it seems. The trouble is false positives without explicit begin/end annotations reviewed by humans - ime from just these few examples you just can't guess this stuff by computeres, you need real brains thinking about all the edge cases, and where exactly the critical section starts and ends. Without that you're just going to drown in a sea of false positives and yuck. So yeah I had hopes for cross-release too, unfortunately that was entirely in vain and a distraction. Now I guess it would be nice if there's a per-class completion_begin/end annotation for the more generic problem. But then also most people don't have a cross-driver completion api contract like dma_fence is, with some of the most ridiculous over the top constraints of what's possible and what's not possible on each side of the cross-release. We do have a bit an outsized benefit (in pain reduction) vs cost ratio here. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From chris at chris-wilson.co.uk Thu Jun 4 10:21:40 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:21:40 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise all copy engines with the blt routines Message-ID: <20200604102140.8845-1-chris@chris-wilson.co.uk> Just to remove an obnoxious HAS_ENGINES(), and in the process make the code agnostic to the available of any particular engine by making it exercise any and all such engines declared on the system. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Matthew Auld <matthew.auld at intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> --- .../i915/gem/selftests/i915_gem_client_blt.c | 3 - .../i915/gem/selftests/i915_gem_object_blt.c | 55 ++++++++++++------- .../gpu/drm/i915/gem/selftests/mock_context.c | 34 ++++++++++++ .../gpu/drm/i915/gem/selftests/mock_context.h | 4 ++ drivers/gpu/drm/i915/i915_drv.h | 5 ++ 5 files changed, 77 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index 8fe3ad2ee34e..299c29e9ad86 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -702,8 +702,5 @@ int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915) if (intel_gt_is_wedged(&i915->gt)) return 0; - if (!HAS_ENGINE(i915, BCS0)) - return 0; - return i915_live_subtests(tests, i915); } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c index 31549ad83fa6..23b6e11bbc3e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c @@ -193,7 +193,7 @@ static int perf_copy_blt(void *arg) } struct igt_thread_arg { - struct drm_i915_private *i915; + struct intel_engine_cs *engine; struct i915_gem_context *ctx; struct file *file; struct rnd_state prng; @@ -203,7 +203,7 @@ struct igt_thread_arg { static int igt_fill_blt_thread(void *arg) { struct igt_thread_arg *thread = arg; - struct drm_i915_private *i915 = thread->i915; + struct intel_engine_cs *engine = thread->engine; struct rnd_state *prng = &thread->prng; struct drm_i915_gem_object *obj; struct i915_gem_context *ctx; @@ -215,7 +215,7 @@ static int igt_fill_blt_thread(void *arg) ctx = thread->ctx; if (!ctx) { - ctx = live_context(i915, thread->file); + ctx = live_context_for_engine(engine, thread->file); if (IS_ERR(ctx)) return PTR_ERR(ctx); @@ -223,7 +223,7 @@ static int igt_fill_blt_thread(void *arg) ctx->sched.priority = I915_USER_PRIORITY(prio); } - ce = i915_gem_context_get_engine(ctx, BCS0); + ce = i915_gem_context_get_engine(ctx, 0); GEM_BUG_ON(IS_ERR(ce)); /* @@ -256,7 +256,7 @@ static int igt_fill_blt_thread(void *arg) pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__, phys_sz, sz, val); - obj = huge_gem_object(i915, phys_sz, sz); + obj = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(obj)) { err = PTR_ERR(obj); goto err_flush; @@ -321,7 +321,7 @@ static int igt_fill_blt_thread(void *arg) static int igt_copy_blt_thread(void *arg) { struct igt_thread_arg *thread = arg; - struct drm_i915_private *i915 = thread->i915; + struct intel_engine_cs *engine = thread->engine; struct rnd_state *prng = &thread->prng; struct drm_i915_gem_object *src, *dst; struct i915_gem_context *ctx; @@ -333,7 +333,7 @@ static int igt_copy_blt_thread(void *arg) ctx = thread->ctx; if (!ctx) { - ctx = live_context(i915, thread->file); + ctx = live_context_for_engine(engine, thread->file); if (IS_ERR(ctx)) return PTR_ERR(ctx); @@ -341,7 +341,7 @@ static int igt_copy_blt_thread(void *arg) ctx->sched.priority = I915_USER_PRIORITY(prio); } - ce = i915_gem_context_get_engine(ctx, BCS0); + ce = i915_gem_context_get_engine(ctx, 0); GEM_BUG_ON(IS_ERR(ce)); /* @@ -374,7 +374,7 @@ static int igt_copy_blt_thread(void *arg) pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__, phys_sz, sz, val); - src = huge_gem_object(i915, phys_sz, sz); + src = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(src)) { err = PTR_ERR(src); goto err_flush; @@ -394,7 +394,7 @@ static int igt_copy_blt_thread(void *arg) if (!(src->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) src->cache_dirty = true; - dst = huge_gem_object(i915, phys_sz, sz); + dst = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(dst)) { err = PTR_ERR(dst); goto err_put_src; @@ -456,7 +456,7 @@ static int igt_copy_blt_thread(void *arg) return err; } -static int igt_threaded_blt(struct drm_i915_private *i915, +static int igt_threaded_blt(struct intel_engine_cs *engine, int (*blt_fn)(void *arg), unsigned int flags) #define SINGLE_CTX BIT(0) @@ -477,14 +477,14 @@ static int igt_threaded_blt(struct drm_i915_private *i915, if (!thread) goto out_tsk; - thread[0].file = mock_file(i915); + thread[0].file = mock_file(engine->i915); if (IS_ERR(thread[0].file)) { err = PTR_ERR(thread[0].file); goto out_thread; } if (flags & SINGLE_CTX) { - thread[0].ctx = live_context(i915, thread[0].file); + thread[0].ctx = live_context_for_engine(engine, thread[0].file); if (IS_ERR(thread[0].ctx)) { err = PTR_ERR(thread[0].ctx); goto out_file; @@ -492,7 +492,7 @@ static int igt_threaded_blt(struct drm_i915_private *i915, } for (i = 0; i < n_cpus; ++i) { - thread[i].i915 = i915; + thread[i].engine = engine; thread[i].file = thread[0].file; thread[i].ctx = thread[0].ctx; thread[i].n_cpus = n_cpus; @@ -532,24 +532,40 @@ static int igt_threaded_blt(struct drm_i915_private *i915, return err; } +static int test_copy_engines(struct drm_i915_private *i915, + int (*fn)(void *arg), + unsigned int flags) +{ + struct intel_engine_cs *engine; + int ret; + + for_each_uabi_class_engine(engine, I915_ENGINE_CLASS_COPY, i915) { + ret = igt_threaded_blt(engine, fn, flags); + if (ret) + return ret; + } + + return 0; +} + static int igt_fill_blt(void *arg) { - return igt_threaded_blt(arg, igt_fill_blt_thread, 0); + return test_copy_engines(arg, igt_fill_blt_thread, 0); } static int igt_fill_blt_ctx0(void *arg) { - return igt_threaded_blt(arg, igt_fill_blt_thread, SINGLE_CTX); + return test_copy_engines(arg, igt_fill_blt_thread, SINGLE_CTX); } static int igt_copy_blt(void *arg) { - return igt_threaded_blt(arg, igt_copy_blt_thread, 0); + return test_copy_engines(arg, igt_copy_blt_thread, 0); } static int igt_copy_blt_ctx0(void *arg) { - return igt_threaded_blt(arg, igt_copy_blt_thread, SINGLE_CTX); + return test_copy_engines(arg, igt_copy_blt_thread, SINGLE_CTX); } int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915) @@ -564,9 +580,6 @@ int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915) if (intel_gt_is_wedged(&i915->gt)) return 0; - if (!HAS_ENGINE(i915, BCS0)) - return 0; - return i915_live_subtests(tests, i915); } diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c b/drivers/gpu/drm/i915/gem/selftests/mock_context.c index e7e3c620f542..987918ca35ef 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c @@ -99,6 +99,40 @@ live_context(struct drm_i915_private *i915, struct file *file) return ERR_PTR(err); } +struct i915_gem_context * +live_context_for_engine(struct intel_engine_cs *engine, struct file *file) +{ + struct i915_gem_engines *engines; + struct i915_gem_context *ctx; + struct intel_context *ce; + + engines = alloc_engines(1); + if (!engines) + return ERR_PTR(-ENOMEM); + + ctx = live_context(engine->i915, file); + if (IS_ERR(ctx)) + return ctx; + + ce = intel_context_create(engine); + if (IS_ERR(ce)) { + __free_engines(engines, 0); + return ERR_CAST(ce); + } + + intel_context_set_gem(ce, ctx); + engines->engines[0] = ce; + + mutex_lock(&ctx->engines_mutex); + i915_gem_context_set_user_engines(ctx); + engines = rcu_replace_pointer(ctx->engines, engines, 1); + mutex_unlock(&ctx->engines_mutex); + + engines_idle_release(ctx, engines); + + return ctx; +} + struct i915_gem_context * kernel_context(struct drm_i915_private *i915) { diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.h b/drivers/gpu/drm/i915/gem/selftests/mock_context.h index fb83d2f09212..2a6121d33352 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.h +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.h @@ -9,6 +9,7 @@ struct file; struct drm_i915_private; +struct intel_engine_cs; void mock_init_contexts(struct drm_i915_private *i915); @@ -21,6 +22,9 @@ void mock_context_close(struct i915_gem_context *ctx); struct i915_gem_context * live_context(struct drm_i915_private *i915, struct file *file); +struct i915_gem_context * +live_context_for_engine(struct intel_engine_cs *engine, struct file *file); + struct i915_gem_context *kernel_context(struct drm_i915_private *i915); void kernel_context_close(struct i915_gem_context *ctx); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e99255e17eb7..1e49abc5a342 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1264,6 +1264,11 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +#define for_each_uabi_class_engine(engine__, class__, i915__) \ + for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ + (engine__) && (engine__)->uabi_class == (class__); \ + (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) + #define I915_GTT_OFFSET_NONE ((u32)-1) /* -- 2.20.1 From patchwork at emeril.freedesktop.org Thu Jun 4 10:28:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 10:28:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/dp=3A_DP_PHY_compliance_for_JSL?= In-Reply-To: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> Message-ID: <159126652645.14555.9274110608347919556@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp: DP PHY compliance for JSL URL : https://patchwork.freedesktop.org/series/77977/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17863_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17863_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17863_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17863_full: ### IGT changes ### #### Possible regressions #### * igt at i915_pm_dc@dc5-dpms: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at i915_pm_dc@dc5-dpms.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-tglb7/igt at i915_pm_dc@dc5-dpms.html Known issues ------------ Here are the changes found in Patchwork_17863_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_balancer@invalid-balancer: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#1927]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at gem_exec_balancer@invalid-balancer.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk2/igt at gem_exec_balancer@invalid-balancer.html * igt at gem_mmap_offset@basic-uaf: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +20 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at gem_mmap_offset@basic-uaf.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl1/igt at gem_mmap_offset@basic-uaf.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at i915_suspend@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-kbl3/igt at i915_suspend@debugfs-reader.html * igt at i915_suspend@forcewake: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at i915_suspend@forcewake.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl6/igt at i915_suspend@forcewake.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_big_fb@linear-32bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl3/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@y-tiled-32bpp-rotate-90: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl4/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb7/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#52] / [i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl8/igt at kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl3/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#49]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-iclb8/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [PASS][33] -> [INCOMPLETE][34] ([i915#69]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl2/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at syncobj_wait@single-wait-all-signaled: - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#93] / [i915#95]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-kbl3/igt at syncobj_wait@single-wait-all-signaled.html #### Possible fixes #### * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at gem_exec_whisper@basic-contexts-forked-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk7/igt at gem_exec_whisper@basic-contexts-forked-all.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl2/igt at gem_workarounds@suspend-resume-context.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +8 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-tglb: [DMESG-WARN][45] ([i915#402]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][47] ([i915#46]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl10/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-kbl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-tglb3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][53] ([i915#69]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt at kms_psr@psr2_sprite_plane_move.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_setmode@basic: - shard-glk: [FAIL][61] ([i915#31]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk8/igt at kms_setmode@basic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk6/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +5 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][65] ([i915#1542]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-tglb7/igt at perf@blocking-parameterized.html * igt at perf_pmu@rc6-runtime-pm: - shard-glk: [TIMEOUT][67] ([i915#1958]) -> [PASS][68] +3 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at perf_pmu@rc6-runtime-pm.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk6/igt at perf_pmu@rc6-runtime-pm.html * igt at vgem_basic@dmabuf-mmap: - shard-apl: [DMESG-WARN][69] ([i915#95]) -> [PASS][70] +18 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at vgem_basic@dmabuf-mmap.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl3/igt at vgem_basic@dmabuf-mmap.html #### Warnings #### * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][71] ([i915#1515]) -> [FAIL][72] ([i915#1515]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at i915_pm_rc6_residency@rc6-idle.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-iclb8/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][74] ([fdo#110321] / [i915#95]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][75] ([i915#1319]) -> [FAIL][76] ([fdo#110321] / [fdo#110336]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][77] ([fdo#110321]) -> [TIMEOUT][78] ([i915#1319] / [i915#1635]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][79] ([fdo#109349]) -> [DMESG-WARN][80] ([i915#1226]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt at kms_dp_dsc@basic-dsc-enable-edp.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-glk: [TIMEOUT][81] ([i915#1640] / [i915#1958]) -> [SKIP][82] ([fdo#109271]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at kms_vblank@pipe-d-query-idle-hang.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk6/igt at kms_vblank@pipe-d-query-idle-hang.html * igt at runner@aborted: - shard-glk: [FAIL][83] ([k.org#202321]) -> ([FAIL][84], [FAIL][85]) ([i915#1611] / [k.org#202321]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at runner@aborted.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk6/igt at runner@aborted.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/shard-glk2/igt at runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#275]: https://gitlab.freedesktop.org/drm/intel/issues/275 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8579 -> Patchwork_17863 CI-20190529: 20190529 CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17863: ce289f0dd8a55b4539309ed6a20bcd48ff88f449 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17863/index.html From chris at chris-wilson.co.uk Thu Jun 4 10:37:37 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:37 +0100 Subject: [Intel-gfx] [PATCH 08/22] drm/i915/gt: Use client timeline address for seqno writes In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-8-chris@chris-wilson.co.uk> If we allow for per-client timelines, even with legacy ring submission, we open the door to a world full of possiblities [scheduling and semaphores]. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c index ce38d1bcaba3..fa11174bb13b 100644 --- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c @@ -373,11 +373,10 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) { - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); + u32 addr = i915_request_active_timeline(rq)->hwsp_offset; - *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW; + *cs++ = addr | MI_FLUSH_DW_USE_GTT; *cs++ = rq->fence.seqno; *cs++ = MI_USER_INTERRUPT; @@ -391,19 +390,17 @@ u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) #define GEN7_XCS_WA 32 u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) { + u32 addr = i915_request_active_timeline(rq)->hwsp_offset; int i; - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | - MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW; + *cs++ = addr | MI_FLUSH_DW_USE_GTT; *cs++ = rq->fence.seqno; for (i = 0; i < GEN7_XCS_WA; i++) { - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = 0; + *cs++ = addr; *cs++ = rq->fence.seqno; } -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:31 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:31 +0100 Subject: [Intel-gfx] [PATCH 02/22] drm/i915: Trim set_timer_ms() intervals In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-2-chris@chris-wilson.co.uk> Use the plain msec_to_jiffies() rather than the _timeout variant so we round down and do not add an extra jiffy to our interval. For example, with timeslicing we do not want to err on the longer side as any fairness depends on catching hogging contexts on the GPU. Bring on CFS. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c index e28eae4a8f70..f42a9e9a0b4f 100644 --- a/drivers/gpu/drm/i915/i915_utils.c +++ b/drivers/gpu/drm/i915/i915_utils.c @@ -91,7 +91,7 @@ void set_timer_ms(struct timer_list *t, unsigned long timeout) return; } - timeout = msecs_to_jiffies_timeout(timeout); + timeout = msecs_to_jiffies(timeout); /* * Paranoia to make sure the compiler computes the timeout before -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:35 +0100 Subject: [Intel-gfx] [PATCH 06/22] drm/i915/gt: Couple tasklet scheduling for all CS interrupts In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-6-chris@chris-wilson.co.uk> If any engine asks for the tasklet to be kicked from the CS interrupt, do so. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 ++++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +++ drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- 4 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 0cc7dd54f4f9..28edf314a319 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -60,6 +60,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir) tasklet_hi_schedule(&engine->execlists.tasklet); } +void gen2_engine_cs_irq(struct intel_engine_cs *engine) +{ + intel_engine_signal_breadcrumbs(engine); + if (intel_engine_needs_breadcrumb_tasklet(engine)) + tasklet_hi_schedule(&engine->execlists.tasklet); +} + static u32 gen11_gt_engine_identity(struct intel_gt *gt, const unsigned int bank, const unsigned int bit) @@ -273,9 +280,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); if (gt_iir & ILK_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); } static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) @@ -299,11 +306,11 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); if (gt_iir & GT_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); if (gt_iir & GT_BLT_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0]); if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | GT_BSD_CS_ERROR_INTERRUPT | diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h index 886c5cf408a2..6c69cd563fe1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h @@ -9,6 +9,7 @@ #include <linux/types.h> +struct intel_engine_cs; struct intel_gt; #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ @@ -19,6 +20,8 @@ struct intel_gt; GEN8_GT_PM_IRQ | \ GEN8_GT_GUC_IRQ) +void gen2_engine_cs_irq(struct intel_engine_cs *engine); + void gen11_gt_irq_reset(struct intel_gt *gt); void gen11_gt_irq_postinstall(struct intel_gt *gt); void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2f59fc6df3c2..2e4ddc9ca09d 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1741,7 +1741,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) return; if (pm_iir & PM_VEBOX_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine[VECS0]); + gen2_engine_cs_irq(gt->engine[VECS0]); if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 490574669eaa..bade4371d1a4 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3682,7 +3682,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i8xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -3787,7 +3787,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) I915_WRITE(GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -3929,10 +3929,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) I915_WRITE(GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[VCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:33 +0100 Subject: [Intel-gfx] [PATCH 04/22] drm/i915/gt: Always check to enable timeslicing if not submitting In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-4-chris@chris-wilson.co.uk> We may choose not to submit for a number of reasons, yet not fill both ELSP. In which case we must start timeslicing (there will be no ACK event on which to hook the start) if the queue would benefit from the currently active context being evicted. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index c27f4279ae53..d95b5261f59f 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2358,10 +2358,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last->context == rq->context) goto done; - if (i915_request_has_sentinel(last)) { - start_timeslice(engine, rq_prio(rq)); + if (i915_request_has_sentinel(last)) goto done; - } /* * If GVT overrides us we only ever submit @@ -2442,6 +2440,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) set_preempt_timeout(engine, *active); execlists_submit_ports(engine); } else { + start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); } -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:41 +0100 Subject: [Intel-gfx] [PATCH 12/22] drm/i915/gt: Implement ring scheduler for gen6/7 In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-12-chris@chris-wilson.co.uk> A key prolem with legacy ring buffer submission is that it is an inheret FIFO queue across all clients; if one blocks, they all block. A scheduler allows us to avoid that limitation, and ensures that all clients can submit in parallel, removing the resource contention of the global ringbuffer. Having built the ring scheduler infrastructure over top of the global ringbuffer submission, we now need to provide the HW knowledge required to build command packets and implement context switching. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gt/intel_ring_scheduler.c | 412 +++++++++++++++++- 1 file changed, 410 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index 777cab6d9540..a3ba069f031e 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -7,6 +7,10 @@ #include <drm/i915_drm.h> +#include "gen2_engine_cs.h" +#include "gen6_engine_cs.h" +#include "gen6_ppgtt.h" +#include "gen7_renderclear.h" #include "i915_drv.h" #include "intel_context.h" #include "intel_engine_stats.h" @@ -286,8 +290,258 @@ static void ring_copy(struct intel_ring *dst, memcpy(out, src->vaddr + start, end - start); } +static void mi_set_context(struct intel_ring *ring, + struct intel_engine_cs *engine, + struct intel_context *ce, + u32 flags) +{ + struct drm_i915_private *i915 = engine->i915; + enum intel_engine_id id; + const int num_engines = + IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; + int len; + u32 *cs; + + len = 4; + if (IS_GEN(i915, 7)) + len += 2 + (num_engines ? 4 * num_engines + 6 : 0); + else if (IS_GEN(i915, 5)) + len += 2; + + cs = ring_map_dw(ring, len); + + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ + if (IS_GEN(i915, 7)) { + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; + if (num_engines) { + struct intel_engine_cs *signaller; + + *cs++ = MI_LOAD_REGISTER_IMM(num_engines); + for_each_engine(signaller, engine->gt, id) { + if (signaller == engine) + continue; + + *cs++ = i915_mmio_reg_offset( + RING_PSMI_CTL(signaller->mmio_base)); + *cs++ = _MASKED_BIT_ENABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + } + } else if (IS_GEN(i915, 5)) { + /* + * This w/a is only listed for pre-production ilk a/b steppings, + * but is also mentioned for programming the powerctx. To be + * safe, just apply the workaround; we do not use SyncFlush so + * this should never take effect and so be a no-op! + */ + *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; + } + + *cs++ = MI_NOOP; + *cs++ = MI_SET_CONTEXT; + *cs++ = i915_ggtt_offset(ce->state) | flags; + /* + * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP + * WaMiSetContext_Hang:snb,ivb,vlv + */ + *cs++ = MI_NOOP; + + if (IS_GEN(i915, 7)) { + if (num_engines) { + struct intel_engine_cs *signaller; + i915_reg_t last_reg = {}; /* keep gcc quiet */ + + *cs++ = MI_LOAD_REGISTER_IMM(num_engines); + for_each_engine(signaller, engine->gt, id) { + if (signaller == engine) + continue; + + last_reg = RING_PSMI_CTL(signaller->mmio_base); + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = _MASKED_BIT_DISABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + + /* Insert a delay before the next switch! */ + *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + *cs++ = MI_NOOP; + } + *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; + } else if (IS_GEN(i915, 5)) { + *cs++ = MI_SUSPEND_FLUSH; + } +} + +static struct i915_address_space *vm_alias(struct i915_address_space *vm) +{ + if (i915_is_ggtt(vm)) + vm = &i915_vm_to_ggtt(vm)->alias->vm; + + return vm; +} + +static void load_pd_dir(struct intel_ring *ring, + struct intel_engine_cs *engine, + const struct i915_ppgtt *ppgtt) +{ + u32 *cs = ring_map_dw(ring, 10); + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); + *cs++ = PP_DIR_DCLV_2G; + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); + *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; + + /* Stall until the page table load is complete? */ + *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); + *cs++ = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + *cs++ = MI_NOOP; +} + +static struct i915_address_space *current_vm(struct intel_engine_cs *engine) +{ + struct intel_context *old = engine->legacy.context; + + return old ? vm_alias(old->vm) : NULL; +} + +static void gen6_emit_invalidate_rcs(struct intel_ring *ring, + struct intel_engine_cs *engine) +{ + u32 addr, flags; + u32 *cs; + + addr = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); + + flags = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; + flags |= PIPE_CONTROL_TLB_INVALIDATE; + + if (INTEL_GEN(engine->i915) >= 7) + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + else + addr |= PIPE_CONTROL_GLOBAL_GTT; + + cs = ring_map_dw(ring, 4); + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = flags; + *cs++ = addr; + *cs++ = 0; +} + +static struct i915_address_space * +clear_residuals(struct intel_ring *ring, struct intel_engine_cs *engine) +{ + struct intel_context *ce = engine->kernel_context; + struct i915_address_space *vm = vm_alias(engine->gt->vm); + u32 flags; + + if (vm != current_vm(engine)) + load_pd_dir(ring, engine, i915_vm_to_ppgtt(vm)); + + if (ce->state) + mi_set_context(ring, engine, ce, + MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT); + + if (IS_HASWELL(engine->i915)) + flags = MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW; + else + flags = MI_BATCH_NON_SECURE_I965; + + __gen6_emit_bb_start(ring_map_dw(ring, 2), + engine->wa_ctx.vma->node.start, flags); + + return vm; +} + +static void remap_l3_slice(struct intel_ring *ring, + struct intel_engine_cs *engine, + int slice) +{ + u32 *cs, *remap_info = engine->i915->l3_parity.remap_info[slice]; + int i; + + if (!remap_info) + return; + + /* + * Note: We do not worry about the concurrent register cacheline hang + * here because no other code should access these registers other than + * at initialization time. + */ + cs = ring_map_dw(ring, GEN7_L3LOG_SIZE / 4 * 2 + 2); + *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE / 4); + for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { + *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); + *cs++ = remap_info[i]; + } + *cs++ = MI_NOOP; +} + +static void remap_l3(struct intel_ring *ring, + struct intel_engine_cs *engine, + struct intel_context *ce) +{ + struct i915_gem_context *ctx = + rcu_dereference_protected(ce->gem_context, true); + int bit, idx = -1; + + if (!ctx || !ctx->remap_slice) + return; + + do { + bit = ffs(ctx->remap_slice); + remap_l3_slice(ring, engine, idx += bit); + } while (ctx->remap_slice >>= bit); +} + static void switch_context(struct intel_ring *ring, struct i915_request *rq) { + struct intel_engine_cs *engine = rq->engine; + struct i915_address_space *cvm = current_vm(engine); + struct intel_context *ce = rq->context; + struct i915_address_space *vm; + + if (engine->wa_ctx.vma && ce != engine->kernel_context) { + if (engine->wa_ctx.vma->private != ce) { + cvm = clear_residuals(ring, engine); + intel_context_put(engine->wa_ctx.vma->private); + engine->wa_ctx.vma->private = intel_context_get(ce); + } + } + + vm = vm_alias(ce->vm); + if (vm != cvm) + load_pd_dir(ring, engine, i915_vm_to_ppgtt(vm)); + + if (ce->state) { + u32 flags; + + GEM_BUG_ON(engine->id != RCS0); + + /* For resource streamer on HSW+ and power context elsewhere */ + BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN); + BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN); + + flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT; + if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) { + gen6_emit_invalidate_rcs(ring, engine); + flags |= MI_RESTORE_EXT_STATE_EN; + } else { + flags |= MI_RESTORE_INHIBIT; + } + + mi_set_context(ring, engine, ce, flags); + } + + remap_l3(ring, engine, ce); } static struct i915_request *ring_submit(struct i915_request *rq) @@ -453,6 +707,33 @@ static void submission_unpark(struct intel_engine_cs *engine) intel_engine_pin_breadcrumbs_irq(engine); } +static int gen6_emit_init_breadcrumb(struct i915_request *rq) +{ + struct intel_timeline *tl = i915_request_timeline(rq); + u32 *cs; + + GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq)); + if (!tl->has_initial_breadcrumb) + return 0; + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = 0; + *cs++ = tl->hwsp_offset; + *cs++ = rq->fence.seqno - 1; + + intel_ring_advance(rq, cs); + + /* Record the updated position of the request's payload */ + rq->infix = intel_ring_offset(rq, cs); + + __set_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags); + return 0; +} + static void ring_context_destroy(struct kref *ref) { struct intel_context *ce = container_of(ref, typeof(*ce), ref); @@ -468,8 +749,30 @@ static void ring_context_destroy(struct kref *ref) intel_context_free(ce); } +static int __context_pin_ppgtt(struct intel_context *ce) +{ + struct i915_address_space *vm; + int err = 0; + + vm = vm_alias(ce->vm); + if (vm) + err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); + + return err; +} + +static void __context_unpin_ppgtt(struct intel_context *ce) +{ + struct i915_address_space *vm; + + vm = vm_alias(ce->vm); + if (vm) + gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); +} + static void ring_context_unpin(struct intel_context *ce) { + __context_unpin_ppgtt(ce); } static int alloc_context_vma(struct intel_context *ce) @@ -597,7 +900,7 @@ static int ring_context_alloc(struct intel_context *ce) static int ring_context_pin(struct intel_context *ce) { - return 0; + return __context_pin_ppgtt(ce); } static void ring_context_reset(struct intel_context *ce) @@ -653,12 +956,19 @@ static void ring_release(struct intel_engine_cs *engine) set_current_context(&engine->legacy.context, NULL); + if (engine->wa_ctx.vma) { + intel_context_put(engine->wa_ctx.vma->private); + i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); + } + intel_ring_unpin(engine->legacy.ring); intel_ring_put(engine->legacy.ring); } static void setup_irq(struct intel_engine_cs *engine) { + engine->irq_enable = gen6_irq_enable; + engine->irq_disable = gen6_irq_disable; } static void setup_common(struct intel_engine_cs *engine) @@ -667,7 +977,7 @@ static void setup_common(struct intel_engine_cs *engine) /* gen8+ are only supported with execlists */ GEM_BUG_ON(INTEL_GEN(i915) >= 8); - GEM_BUG_ON(INTEL_GEN(i915) < 8); + GEM_BUG_ON(INTEL_GEN(i915) < 6); setup_irq(engine); @@ -684,24 +994,62 @@ static void setup_common(struct intel_engine_cs *engine) engine->cops = &ring_context_ops; engine->request_alloc = ring_request_alloc; + engine->emit_init_breadcrumb = gen6_emit_init_breadcrumb; + if (INTEL_GEN(i915) >= 7) + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; + else if (INTEL_GEN(i915) >= 6) + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; + else + engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; + engine->set_default_submission = set_default_submission; + + engine->emit_bb_start = gen6_emit_bb_start; } static void setup_rcs(struct intel_engine_cs *engine) { + struct drm_i915_private *i915 = engine->i915; + + if (HAS_L3_DPF(i915)) + engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; + + engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; + + if (INTEL_GEN(i915) >= 7) { + engine->emit_flush = gen7_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; + if (IS_HASWELL(i915)) + engine->emit_bb_start = hsw_emit_bb_start; + } else { + engine->emit_flush = gen6_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; + } } static void setup_vcs(struct intel_engine_cs *engine) { + engine->emit_flush = gen6_emit_flush_vcs; + engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; + + if (IS_GEN(engine->i915, 6)) + engine->fw_domain = FORCEWAKE_ALL; } static void setup_bcs(struct intel_engine_cs *engine) { + engine->emit_flush = gen6_emit_flush_xcs; + engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; } static void setup_vecs(struct intel_engine_cs *engine) { GEM_BUG_ON(!IS_HASWELL(engine->i915)); + + engine->emit_flush = gen6_emit_flush_xcs; + engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; + engine->irq_enable = hsw_irq_enable_vecs; + engine->irq_disable = hsw_irq_disable_vecs; } static unsigned int global_ring_size(void) @@ -710,6 +1058,58 @@ static unsigned int global_ring_size(void) return roundup_pow_of_two(EXECLIST_MAX_PORTS * SZ_16K + SZ_4K); } +static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine) +{ + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int size; + int err; + + size = gen7_setup_clear_gpr_bb(engine, NULL /* probe size */); + if (size <= 0) + return size; + + size = ALIGN(size, PAGE_SIZE); + obj = i915_gem_object_create_internal(engine->i915, size); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + vma = i915_vma_instance(obj, engine->gt->vm, NULL); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto err_obj; + } + + vma->private = intel_context_create(engine); /* dummy residuals */ + if (IS_ERR(vma->private)) { + err = PTR_ERR(vma->private); + goto err_obj; + } + + err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + if (err) + goto err_private; + + err = i915_vma_sync(vma); + if (err) + goto err_unpin; + + size = gen7_setup_clear_gpr_bb(engine, vma); + if (err) + goto err_unpin; + + engine->wa_ctx.vma = vma; + return 0; + +err_unpin: + i915_vma_unpin(vma); +err_private: + intel_context_put(vma->private); +err_obj: + i915_gem_object_put(obj); + return err; +} + int intel_ring_scheduler_setup(struct intel_engine_cs *engine) { struct intel_ring *ring; @@ -753,6 +1153,12 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) GEM_BUG_ON(engine->legacy.ring); engine->legacy.ring = ring; + if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) { + err = gen7_ctx_switch_bb_init(engine); + if (err) + goto err_ring_unpin; + } + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; engine->flags |= I915_ENGINE_SUPPORTS_STATS; @@ -760,6 +1166,8 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) engine->release = ring_release; return 0; +err_ring_unpin: + intel_ring_unpin(ring); err_ring: intel_ring_put(ring); err: -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:44 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:44 +0100 Subject: [Intel-gfx] [PATCH 15/22] drm/i915: Add list_for_each_entry_safe_continue_reverse In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-15-chris@chris-wilson.co.uk> One more list iterator variant, for when we want to unwind from inside one list iterator with the intention of restarting from the current entry as the new head of the list. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_utils.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h index 03a73d2bd50d..6ebccdd12d4c 100644 --- a/drivers/gpu/drm/i915/i915_utils.h +++ b/drivers/gpu/drm/i915/i915_utils.h @@ -266,6 +266,12 @@ static inline int list_is_last_rcu(const struct list_head *list, return READ_ONCE(list->next) == head; } +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) + /* * Wait until the work is finally complete, even if it tries to postpone * by requeueing itself. Note, that if the worker never cancels itself, -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:34 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:34 +0100 Subject: [Intel-gfx] [PATCH 05/22] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-5-chris@chris-wilson.co.uk> This was removed in commit 478ffad6d690 ("drm/i915: drop engine_pin/unpin_breadcrumbs_irq") as the last user had been removed, but now there is a promise of a new user in the next patch. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c index d907d538176e..03c14ab86d95 100644 --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c @@ -220,6 +220,28 @@ static void signal_irq_work(struct irq_work *work) } } +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine) +{ + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + spin_lock_irq(&b->irq_lock); + if (!b->irq_enabled++) + irq_enable(engine); + GEM_BUG_ON(!b->irq_enabled); /* no overflow! */ + spin_unlock_irq(&b->irq_lock); +} + +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine) +{ + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + spin_lock_irq(&b->irq_lock); + GEM_BUG_ON(!b->irq_enabled); /* no underflow! */ + if (!--b->irq_enabled) + irq_disable(engine); + spin_unlock_irq(&b->irq_lock); +} + static bool __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b) { struct intel_engine_cs *engine = diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..043462b6ce1f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -226,6 +226,9 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine); void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine); +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine); + void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); static inline void -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:38 +0100 Subject: [Intel-gfx] [PATCH 09/22] drm/i915/gt: Infrastructure for ring scheduling In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-9-chris@chris-wilson.co.uk> Build a bare bones scheduler to sit on top the global legacy ringbuffer submission. This virtual execlists scheme should be applicable to all older platforms. A key problem we have with the legacy ring buffer submission is that it only allows for FIFO queuing. All clients share the global request queue and must contend for its lock when submitting. As any client may need to wait for external events, all clients must then wait. However, if we stage each client into their own virtual ringbuffer with their own timelines, we can copy the client requests into the global ringbuffer only when they are ready, reordering the submission around stalls. Furthermore, the ability to reorder gives us rudimentarily priority sorting -- although without preemption support, once something is on the GPU it stays on the GPU, and so it is still possible for a hog to delay a high priority request (such as updating the display). However, it does means that in keeping a short submission queue, the high priority request will be next. This design resembles the old guc submission scheduler, for reordering requests onto a global workqueue. The implementation uses the MI_USER_INTERRUPT at the end of every request to track completion, so is more interrupt happy than execlists [which has an interrupt for each context event, albeit two]. Our interrupts on these system are relatively heavy, and in the past we have been able to completely starve Sandybrige by the interrupt traffic. Our interrupt handlers are being much better (in part offloading the work to bottom halves leaving the interrupt itself only dealing with acking the registers) but we can still see the impact of starvation in the uneven submission latency on a saturated system. Overall though, the short sumission queues and extra interrupts do not appear to be affecting throughput (+-10%, some tasks even improve to the reduced request overheads) and improve latency. [Which is a massive improvement since the introduction of Sandybridge!] Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_engine.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + .../gpu/drm/i915/gt/intel_ring_scheduler.c | 760 ++++++++++++++++++ .../gpu/drm/i915/gt/intel_ring_submission.c | 13 +- .../gpu/drm/i915/gt/intel_ring_submission.h | 16 + 6 files changed, 786 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_ring_scheduler.c create mode 100644 drivers/gpu/drm/i915/gt/intel_ring_submission.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 41a27fd5dbc7..6d98a74da41e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -109,6 +109,7 @@ gt-y += \ gt/intel_renderstate.o \ gt/intel_reset.o \ gt/intel_ring.o \ + gt/intel_ring_scheduler.o \ gt/intel_ring_submission.o \ gt/intel_rps.o \ gt/intel_sseu.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 043462b6ce1f..08176117757e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -209,6 +209,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine); int intel_engine_resume(struct intel_engine_cs *engine); int intel_ring_submission_setup(struct intel_engine_cs *engine); +int intel_ring_scheduler_setup(struct intel_engine_cs *engine); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 2b6cdf47d428..3782e27c2945 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -348,6 +348,7 @@ struct intel_engine_cs { struct { struct intel_ring *ring; struct intel_timeline *timeline; + struct intel_context *context; } legacy; /* diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c new file mode 100644 index 000000000000..c8cd435d1c51 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -0,0 +1,760 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +#include <linux/log2.h> + +#include <drm/i915_drm.h> + +#include "i915_drv.h" +#include "intel_context.h" +#include "intel_gt.h" +#include "intel_gt_pm.h" +#include "intel_gt_requests.h" +#include "intel_reset.h" +#include "intel_ring.h" +#include "intel_ring_submission.h" +#include "shmem_utils.h" + +/* + * Rough estimate of the typical request size, performing a flush, + * set-context and then emitting the batch. + */ +#define LEGACY_REQUEST_SIZE 200 + +static inline int rq_prio(const struct i915_request *rq) +{ + return rq->sched.attr.priority; +} + +static inline struct i915_priolist *to_priolist(struct rb_node *rb) +{ + return rb_entry(rb, struct i915_priolist, node); +} + +static inline int queue_prio(struct rb_node *rb) +{ + return rb ? to_priolist(rb)->priority : INT_MIN; +} + +static inline bool reset_in_progress(const struct intel_engine_execlists *el) +{ + return unlikely(!__tasklet_is_enabled(&el->tasklet)); +} + +static void +set_current_context(struct intel_context **ptr, struct intel_context *ce) +{ + if (ce) + intel_context_get(ce); + + ce = xchg(ptr, ce); + + if (ce) + intel_context_put(ce); +} + +static struct i915_request * +schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) +{ + __intel_gt_pm_get(engine->gt); + return i915_request_get(rq); +} + +static void +schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) +{ + struct intel_context *ce = rq->context; + + if (list_is_last_rcu(&rq->link, &ce->timeline->requests)) + intel_engine_add_retire(engine, ce->timeline); + + i915_request_put(rq); + intel_gt_pm_put_async(engine->gt); +} + +static void reset_prepare(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + unsigned long flags; + + GEM_TRACE("%s\n", engine->name); + + __tasklet_disable_sync_once(&el->tasklet); + GEM_BUG_ON(!reset_in_progress(el)); + + /* And flush any current direct submission. */ + spin_lock_irqsave(&engine->active.lock, flags); + spin_unlock_irqrestore(&engine->active.lock, flags); + + intel_ring_submission_reset_prepare(engine); +} + +static void reset_queue_priority(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + el->queue_priority_hint = queue_prio(rb_first_cached(&el->queue)); +} + +static struct i915_request * +__unwind_incomplete_requests(struct intel_engine_cs *engine) +{ + struct i915_request *rq, *rn, *active = NULL; + struct list_head *uninitialized_var(pl); + int prio = I915_PRIORITY_INVALID; + + lockdep_assert_held(&engine->active.lock); + + list_for_each_entry_safe_reverse(rq, rn, + &engine->active.requests, + sched.link) { + if (i915_request_completed(rq)) + break; + + __i915_request_unsubmit(rq); + + GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); + if (rq_prio(rq) != prio) { + prio = rq_prio(rq); + pl = i915_sched_lookup_priolist(engine, prio); + } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); + + list_move(&rq->sched.link, pl); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + + active = rq; + } + + reset_queue_priority(engine); + + return active; +} + +static inline void clear_ports(struct i915_request **ports, int count) +{ + memset_p((void **)ports, NULL, count); +} + +static void cancel_port_requests(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request * const *port; + + clear_ports(el->pending, ARRAY_SIZE(el->pending)); + for (port = xchg(&el->active, el->pending); *port; port++) + schedule_out(engine, *port); + clear_ports(el->inflight, ARRAY_SIZE(el->inflight)); + + smp_wmb(); /* complete the seqlock for execlists_active() */ + WRITE_ONCE(el->active, el->inflight); +} + +static void __ring_rewind(struct intel_engine_cs *engine, bool stalled) +{ + struct i915_request *rq; + + rq = __unwind_incomplete_requests(engine); + if (rq && i915_request_started(rq)) + __i915_request_reset(rq, stalled); + + cancel_port_requests(engine); + + /* Clear the global submission state, we will submit from scratch */ + intel_ring_reset(engine->legacy.ring, 0); + set_current_context(&engine->legacy.context, NULL); +} + +static void ring_reset_rewind(struct intel_engine_cs *engine, bool stalled) +{ + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + __ring_rewind(engine, stalled); + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void nop_submission_tasklet(unsigned long data) +{ + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + + /* The driver is wedged; don't process any more events. */ + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN); +} + +static void ring_reset_cancel(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request *rq, *rn; + unsigned long flags; + struct rb_node *rb; + + spin_lock_irqsave(&engine->active.lock, flags); + + __ring_rewind(engine, true); + + /* Mark all submitted requests as skipped. */ + list_for_each_entry(rq, &engine->active.requests, sched.link) { + i915_request_set_error_once(rq, -EIO); + i915_request_mark_complete(rq); + } + + /* Flush the queued requests to the timeline list (for retiring). */ + while ((rb = rb_first_cached(&el->queue))) { + struct i915_priolist *p = to_priolist(rb); + int i; + + priolist_for_each_request_consume(rq, rn, p, i) { + i915_request_set_error_once(rq, -EIO); + i915_request_mark_complete(rq); + __i915_request_submit(rq); + } + + rb_erase_cached(&p->node, &el->queue); + i915_priolist_free(p); + } + + el->queue_priority_hint = INT_MIN; + el->queue = RB_ROOT_CACHED; + + /* Remaining _unready_ requests will be nop'ed when submitted */ + + GEM_BUG_ON(__tasklet_is_enabled(&el->tasklet)); + el->tasklet.func = nop_submission_tasklet; + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void reset_finish(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + intel_ring_submission_reset_finish(engine); + + if (__tasklet_enable(&el->tasklet)) + tasklet_hi_schedule(&el->tasklet); +} + +static u32 *ring_map(struct intel_ring *ring, u32 len) +{ + u32 *va; + + if (unlikely(ring->tail + len > ring->effective_size)) { + memset(ring->vaddr + ring->tail, 0, ring->size - ring->tail); + ring->tail = 0; + } + + va = ring->vaddr + ring->tail; + ring->tail = intel_ring_wrap(ring, ring->tail + len); + + return va; +} + +static inline u32 *ring_map_dw(struct intel_ring *ring, u32 len) +{ + return ring_map(ring, len * sizeof(u32)); +} + +static void ring_copy(struct intel_ring *dst, + const struct intel_ring *src, + u32 start, u32 end) +{ + unsigned int len; + void *out; + + len = end - start; + if (end < start) + len += src->size; + out = ring_map(dst, len); + + if (end < start) { + len = src->size - start; + memcpy(out, src->vaddr + start, len); + out += len; + start = 0; + } + + memcpy(out, src->vaddr + start, end - start); +} + +static void switch_context(struct intel_ring *ring, struct i915_request *rq) +{ +} + +static struct i915_request *ring_submit(struct i915_request *rq) +{ + struct intel_ring *ring = rq->engine->legacy.ring; + + __i915_request_submit(rq); + + if (rq->engine->legacy.context != rq->context) { + switch_context(ring, rq); + set_current_context(&rq->engine->legacy.context, rq->context); + } + + ring_copy(ring, rq->ring, rq->head, rq->tail); + return rq; +} + +static struct i915_request ** +copy_active(struct i915_request **port, struct i915_request * const *active) +{ + while (*active) + *port++ = *active++; + + return port; +} + +static void __dequeue(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request ** const last_port = el->pending + el->port_mask; + struct i915_request **port, *last; + struct rb_node *rb; + + lockdep_assert_held(&engine->active.lock); + + port = copy_active(el->pending, el->active); + if (port > last_port) + return; + + last = NULL; + while ((rb = rb_first_cached(&el->queue))) { + struct i915_priolist *p = to_priolist(rb); + struct i915_request *rq, *rn; + int i; + + priolist_for_each_request_consume(rq, rn, p, i) { + GEM_BUG_ON(rq == last); + if (last && rq->context != last->context) { + if (port == last_port) + goto done; + + *port++ = schedule_in(engine, last); + } + + last = ring_submit(rq); + } + + rb_erase_cached(&p->node, &el->queue); + i915_priolist_free(p); + } + +done: + el->queue_priority_hint = queue_prio(rb); + if (last) { + *port++ = schedule_in(engine, last); + *port++ = NULL; + WRITE_ONCE(el->active, el->pending); + + wmb(); /* paranoid flush of WCB before RING_TAIL write */ + ENGINE_WRITE(engine, RING_TAIL, engine->legacy.ring->tail); + memcpy(el->inflight, el->pending, + (port - el->pending) * sizeof(*port)); + + WRITE_ONCE(el->active, el->inflight); + GEM_BUG_ON(!*el->active); + } +} + +static void __submission_tasklet(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request *rq; + + while ((rq = *el->active)) { + if (!i915_request_completed(rq)) + break; + + schedule_out(engine, rq); + el->active++; + } + + if (el->queue_priority_hint != INT_MIN) + __dequeue(engine); +} + +static void submission_tasklet(unsigned long data) +{ + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + __submission_tasklet(engine); + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void queue_request(struct intel_engine_cs *engine, + struct i915_request *rq) +{ + GEM_BUG_ON(!list_empty(&rq->sched.link)); + list_add_tail(&rq->sched.link, + i915_sched_lookup_priolist(engine, rq_prio(rq))); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); +} + +static void __submit_queue_imm(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + if (reset_in_progress(el)) + return; /* defer until we restart the engine following reset */ + + __submission_tasklet(engine); +} + +static void submit_queue(struct intel_engine_cs *engine, + const struct i915_request *rq) +{ + struct intel_engine_execlists *el = &engine->execlists; + + if (rq_prio(rq) <= el->queue_priority_hint) + return; + + el->queue_priority_hint = rq_prio(rq); + __submit_queue_imm(engine); +} + +static void submit_request(struct i915_request *rq) +{ + struct intel_engine_cs *engine = rq->engine; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + + queue_request(engine, rq); + + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); + GEM_BUG_ON(list_empty(&rq->sched.link)); + + submit_queue(engine, rq); + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void submission_park(struct intel_engine_cs *engine) +{ + GEM_BUG_ON(engine->execlists.queue_priority_hint != INT_MIN); + intel_engine_unpin_breadcrumbs_irq(engine); + submission_tasklet((unsigned long)engine); /* drain the submit queue */ +} + +static void submission_unpark(struct intel_engine_cs *engine) +{ + intel_engine_pin_breadcrumbs_irq(engine); +} + +static void ring_context_destroy(struct kref *ref) +{ + struct intel_context *ce = container_of(ref, typeof(*ce), ref); + + GEM_BUG_ON(intel_context_is_pinned(ce)); + + if (ce->state) + i915_vma_put(ce->state); + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) + intel_ring_put(ce->ring); + + intel_context_fini(ce); + intel_context_free(ce); +} + +static void ring_context_unpin(struct intel_context *ce) +{ +} + +static int alloc_context_vma(struct intel_context *ce) + +{ + struct intel_engine_cs *engine = ce->engine; + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int err; + + obj = i915_gem_object_create_shmem(engine->i915, engine->context_size); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + /* + * Try to make the context utilize L3 as well as LLC. + * + * On VLV we don't have L3 controls in the PTEs so we + * shouldn't touch the cache level, especially as that + * would make the object snooped which might have a + * negative performance impact. + * + * Snooping is required on non-llc platforms in execlist + * mode, but since all GGTT accesses use PAT entry 0 we + * get snooping anyway regardless of cache_level. + * + * This is only applicable for Ivy Bridge devices since + * later platforms don't have L3 control bits in the PTE. + */ + if (IS_IVYBRIDGE(engine->i915)) + i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); + + if (engine->default_state) { + void *vaddr; + + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); + if (IS_ERR(vaddr)) { + err = PTR_ERR(vaddr); + goto err_obj; + } + + shmem_read(engine->default_state, 0, + vaddr, engine->context_size); + __set_bit(CONTEXT_VALID_BIT, &ce->flags); + + i915_gem_object_flush_map(obj); + i915_gem_object_unpin_map(obj); + } + + vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto err_obj; + } + + ce->state = vma; + return 0; + +err_obj: + i915_gem_object_put(obj); + return err; +} + +static int alloc_timeline(struct intel_context *ce) +{ + struct intel_engine_cs *engine = ce->engine; + struct intel_timeline *tl; + struct i915_vma *hwsp; + + /* + * Use the static global HWSP for the kernel context, and + * a dynamically allocated cacheline for everyone else. + */ + hwsp = NULL; + if (unlikely(intel_context_is_barrier(ce))) + hwsp = engine->status_page.vma; + + tl = intel_timeline_create(engine->gt, hwsp); + if (IS_ERR(tl)) + return PTR_ERR(tl); + + ce->timeline = tl; + return 0; +} + +static int ring_context_alloc(struct intel_context *ce) +{ + struct intel_engine_cs *engine = ce->engine; + struct intel_ring *ring; + int err; + + GEM_BUG_ON(ce->state); + if (engine->context_size) { + err = alloc_context_vma(ce); + if (err) + return err; + } + + if (!ce->timeline) { + err = alloc_timeline(ce); + if (err) + goto err_vma; + } + + ring = intel_engine_create_ring(engine, + (unsigned long)ce->ring | + INTEL_RING_CREATE_INTERNAL); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto err_timeline; + } + ce->ring = ring; + + return 0; + +err_timeline: + intel_timeline_put(ce->timeline); +err_vma: + if (ce->state) { + i915_vma_put(ce->state); + ce->state = NULL; + } + return err; +} + +static int ring_context_pin(struct intel_context *ce) +{ + return 0; +} + +static void ring_context_reset(struct intel_context *ce) +{ + intel_ring_reset(ce->ring, 0); + clear_bit(CONTEXT_VALID_BIT, &ce->flags); +} + +static const struct intel_context_ops ring_context_ops = { + .alloc = ring_context_alloc, + + .pin = ring_context_pin, + .unpin = ring_context_unpin, + + .enter = intel_context_enter_engine, + .exit = intel_context_exit_engine, + + .reset = ring_context_reset, + .destroy = ring_context_destroy, +}; + +static int ring_request_alloc(struct i915_request *rq) +{ + int ret; + + GEM_BUG_ON(!intel_context_is_pinned(rq->context)); + + /* + * Flush enough space to reduce the likelihood of waiting after + * we start building the request - in which case we will just + * have to repeat work. + */ + rq->reserved_space += LEGACY_REQUEST_SIZE; + + /* Unconditionally invalidate GPU caches and TLBs. */ + ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE); + if (ret) + return ret; + + rq->reserved_space -= LEGACY_REQUEST_SIZE; + return 0; +} + +static void set_default_submission(struct intel_engine_cs *engine) +{ + engine->submit_request = submit_request; + engine->execlists.tasklet.func = submission_tasklet; +} + +static void ring_release(struct intel_engine_cs *engine) +{ + intel_engine_cleanup_common(engine); + + set_current_context(&engine->legacy.context, NULL); + + intel_ring_unpin(engine->legacy.ring); + intel_ring_put(engine->legacy.ring); +} + +static void setup_irq(struct intel_engine_cs *engine) +{ +} + +static void setup_common(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; + + /* gen8+ are only supported with execlists */ + GEM_BUG_ON(INTEL_GEN(i915) >= 8); + GEM_BUG_ON(INTEL_GEN(i915) < 8); + + setup_irq(engine); + + engine->park = submission_park; + engine->unpark = submission_unpark; + engine->schedule = i915_schedule; + + engine->resume = intel_ring_submission_resume; + engine->reset.prepare = reset_prepare; + engine->reset.rewind = ring_reset_rewind; + engine->reset.cancel = ring_reset_cancel; + engine->reset.finish = reset_finish; + + engine->cops = &ring_context_ops; + engine->request_alloc = ring_request_alloc; + + engine->set_default_submission = set_default_submission; +} + +static void setup_rcs(struct intel_engine_cs *engine) +{ +} + +static void setup_vcs(struct intel_engine_cs *engine) +{ +} + +static void setup_bcs(struct intel_engine_cs *engine) +{ +} + +static void setup_vecs(struct intel_engine_cs *engine) +{ + GEM_BUG_ON(!IS_HASWELL(engine->i915)); +} + +static unsigned int global_ring_size(void) +{ + /* Enough space to hold 2 clients and the context switch */ + return roundup_pow_of_two(EXECLIST_MAX_PORTS * SZ_16K + SZ_4K); +} + +int intel_ring_scheduler_setup(struct intel_engine_cs *engine) +{ + struct intel_ring *ring; + int err; + + GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); + + tasklet_init(&engine->execlists.tasklet, + submission_tasklet, (unsigned long)engine); + + setup_common(engine); + + switch (engine->class) { + case RENDER_CLASS: + setup_rcs(engine); + break; + case VIDEO_DECODE_CLASS: + setup_vcs(engine); + break; + case COPY_ENGINE_CLASS: + setup_bcs(engine); + break; + case VIDEO_ENHANCEMENT_CLASS: + setup_vecs(engine); + break; + default: + MISSING_CASE(engine->class); + return -ENODEV; + } + + ring = intel_engine_create_ring(engine, global_ring_size()); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto err; + } + + err = intel_ring_pin(ring); + if (err) + goto err_ring; + + GEM_BUG_ON(engine->legacy.ring); + engine->legacy.ring = ring; + + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; + + /* Finally, take ownership and responsibility for cleanup! */ + engine->release = ring_release; + return 0; + +err_ring: + intel_ring_put(ring); +err: + intel_engine_cleanup_common(engine); + return err; +} diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 68a08486fc87..4cf7c6486223 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -36,6 +36,7 @@ #include "intel_gt.h" #include "intel_reset.h" #include "intel_ring.h" +#include "intel_ring_submission.h" #include "shmem_utils.h" /* Rough estimate of the typical request size, performing a flush, @@ -214,7 +215,7 @@ static void set_pp_dir(struct intel_engine_cs *engine) } } -static int xcs_resume(struct intel_engine_cs *engine) +int intel_ring_submission_resume(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; struct intel_ring *ring = engine->legacy.ring; @@ -318,7 +319,7 @@ static int xcs_resume(struct intel_engine_cs *engine) return ret; } -static void reset_prepare(struct intel_engine_cs *engine) +void intel_ring_submission_reset_prepare(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; const u32 base = engine->mmio_base; @@ -425,7 +426,7 @@ static void reset_rewind(struct intel_engine_cs *engine, bool stalled) spin_unlock_irqrestore(&engine->active.lock, flags); } -static void reset_finish(struct intel_engine_cs *engine) +void intel_ring_submission_reset_finish(struct intel_engine_cs *engine) { } @@ -1056,11 +1057,11 @@ static void setup_common(struct intel_engine_cs *engine) setup_irq(engine); - engine->resume = xcs_resume; - engine->reset.prepare = reset_prepare; + engine->resume = intel_ring_submission_resume; + engine->reset.prepare = intel_ring_submission_reset_prepare; engine->reset.rewind = reset_rewind; engine->reset.cancel = reset_cancel; - engine->reset.finish = reset_finish; + engine->reset.finish = intel_ring_submission_reset_finish; engine->cops = &ring_context_ops; engine->request_alloc = ring_request_alloc; diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.h b/drivers/gpu/drm/i915/gt/intel_ring_submission.h new file mode 100644 index 000000000000..701eb033e055 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_RING_SUBMISSION_H__ +#define __INTEL_RING_SUBMISSION_H__ + +struct intel_engine_cs; + +void intel_ring_submission_reset_prepare(struct intel_engine_cs *engine); +void intel_ring_submission_reset_finish(struct intel_engine_cs *engine); + +int intel_ring_submission_resume(struct intel_engine_cs *engine); + +#endif /* __INTEL_RING_SUBMISSION_H__ */ -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:42 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:42 +0100 Subject: [Intel-gfx] [PATCH 13/22] drm/i915/gt: Enable ring scheduling for gen6/7 In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-13-chris@chris-wilson.co.uk> Switch over from FIFO global submission to the priority-sorted topographical scheduler. At the cost of more busy work on the CPU to keep the GPU supplied with the next packet of requests, this allows us to reorder requests around submission stalls. This also enables the timer based RPS, with the exception of Valleyview who's PCU doesn't take kindly to our interference. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/gt/intel_rps.c | 6 ++---- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index b81978890641..bb57687aea99 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -94,7 +94,7 @@ static int live_nop_switch(void *arg) rq = i915_request_get(this); i915_request_add(this); } - if (i915_request_wait(rq, 0, HZ / 5) < 0) { + if (i915_request_wait(rq, 0, HZ) < 0) { pr_err("Failed to populated %d contexts\n", nctx); intel_gt_set_wedged(&i915->gt); i915_request_put(rq); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4b36378af119..2312e8313325 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -790,6 +790,8 @@ int intel_engines_init(struct intel_gt *gt) if (HAS_EXECLISTS(gt->i915)) setup = intel_execlists_submission_setup; + else if (INTEL_GEN(gt->i915) >= 6) + setup = intel_ring_scheduler_setup; else setup = intel_ring_submission_setup; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2e4ddc9ca09d..22882c2953da 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1053,9 +1053,7 @@ static bool gen6_rps_enable(struct intel_rps *rps) intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000); intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); - rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | - GEN6_PM_RP_DOWN_THRESHOLD | - GEN6_PM_RP_DOWN_TIMEOUT); + rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; return rps_reset(rps); } @@ -1362,7 +1360,7 @@ void intel_rps_enable(struct intel_rps *rps) GEM_BUG_ON(rps->efficient_freq < rps->min_freq); GEM_BUG_ON(rps->efficient_freq > rps->max_freq); - if (has_busy_stats(rps)) + if (has_busy_stats(rps) && !IS_VALLEYVIEW(i915)) intel_rps_set_timer(rps); else if (INTEL_GEN(i915) >= 6) intel_rps_set_interrupts(rps); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:51 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:51 +0100 Subject: [Intel-gfx] [PATCH 22/22] drm/i915/gem: Make relocations atomic within execbuf In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-22-chris@chris-wilson.co.uk> Although we may chide userspace for reusing the same batches concurrently from multiple threads, at the same time we must be very careful to only execute the batch and its relocations as supplied by the user. If we are not careful, we may allow another thread to rewrite the current batch with its own relocations. We must order the relocations and their batch such that they are an atomic pair on the GPU, and that the ioctl itself appears atomic to userspace. The order of execution may be undetermined, but it will not be subverted. We could do this by moving the relocations into the main request, if it were not for the situation where we need a second engine to perform the relocations for us. Instead, we use the dependency tracking to only publish the write fence on the main request and not on the relocation request, so that concurrent updates are queued after the batch has consumed its relocations. Testcase: igt/gem_exec_reloc/basic-concurrent Fixes: ef398881d27d ("drm/i915/gem: Limit struct_mutex to eb_reserve") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 92 ++++++++++++++----- .../i915/gem/selftests/i915_gem_execbuffer.c | 11 ++- 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 373d5eea7a5a..72865ab3945c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -5,6 +5,7 @@ */ #include <linux/intel-iommu.h> +#include <linux/dma-fence-proxy.h> #include <linux/dma-resv.h> #include <linux/sync_file.h> #include <linux/uaccess.h> @@ -259,6 +260,8 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; + struct dma_fence *fence; + struct i915_request *rq; struct i915_vma *rq_vma; u32 *rq_cmd; @@ -555,16 +558,6 @@ eb_add_vma(struct i915_execbuffer *eb, ev->exec = entry; ev->flags = entry->flags; - if (eb->lut_size > 0) { - ev->handle = entry->handle; - hlist_add_head(&ev->node, - &eb->buckets[hash_32(entry->handle, - eb->lut_size)]); - } - - if (entry->relocation_count) - list_add_tail(&ev->reloc_link, &eb->relocs); - /* * SNA is doing fancy tricks with compressing batch buffers, which leads * to negative relocation deltas. Usually that works out ok since the @@ -581,9 +574,21 @@ eb_add_vma(struct i915_execbuffer *eb, if (eb->reloc_cache.has_fence) ev->flags |= EXEC_OBJECT_NEEDS_FENCE; + INIT_LIST_HEAD(&ev->reloc_link); + eb->batch = ev; } + if (entry->relocation_count) + list_add_tail(&ev->reloc_link, &eb->relocs); + + if (eb->lut_size > 0) { + ev->handle = entry->handle; + hlist_add_head(&ev->node, + &eb->buckets[hash_32(entry->handle, + eb->lut_size)]); + } + if (eb_pin_vma(eb, entry, ev)) { if (entry->offset != vma->node.start) { entry->offset = vma->node.start | UPDATE; @@ -923,6 +928,7 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; + cache->fence = NULL; } static inline void *unmask_page(unsigned long p) @@ -1052,6 +1058,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache) } intel_gt_chipset_flush(rq->engine->gt); + i915_request_get(rq); i915_request_add(rq); } @@ -1284,16 +1291,6 @@ eb_relocate_entry(struct i915_execbuffer *eb, if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) return 0; - /* - * If we write into the object, we need to force the synchronisation - * barrier, either with an asynchronous clflush or if we executed the - * patching using the GPU (though that should be serialised by the - * timeline). To be completely sure, and since we are required to - * do relocations we are already stalling, disable the user's opt - * out of our synchronisation. - */ - ev->flags &= ~EXEC_OBJECT_ASYNC; - /* and update the user's relocation entry */ return relocate_entry(eb, ev->vma, reloc, target->vma); } @@ -1527,6 +1524,11 @@ static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) obj->write_domain = I915_GEM_DOMAIN_RENDER; obj->read_domains = I915_GEM_DOMAIN_RENDER; + ev->flags |= EXEC_OBJECT_ASYNC; + + err = dma_resv_reserve_shared(vma->resv, 1); + if (err) + return err; err = i915_request_await_object(rq, obj, true); if (err) @@ -1537,6 +1539,7 @@ static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) return err; dma_resv_add_excl_fence(vma->resv, &rq->fence); + dma_resv_add_shared_fence(vma->resv, cache->fence); return 0; } @@ -1605,14 +1608,28 @@ static int reloc_gpu_alloc(struct i915_execbuffer *eb) return __reloc_gpu_alloc(eb, engine); } +static void free_reloc_fence(struct i915_execbuffer *eb) +{ + struct dma_fence *f = fetch_and_zero(&eb->reloc_cache.fence); + + dma_fence_signal(f); + dma_fence_put(f); +} + static int reloc_gpu(struct i915_execbuffer *eb) { struct eb_vma *ev; int err; + eb->reloc_cache.fence = __dma_fence_create_proxy(0, 0); + if (!eb->reloc_cache.fence) + return -ENOMEM; + err = reloc_gpu_alloc(eb); - if (err) + if (err) { + free_reloc_fence(eb); return err; + } GEM_BUG_ON(!eb->reloc_cache.rq); err = lock_relocs(eb); @@ -1673,6 +1690,15 @@ static int eb_relocate(struct i915_execbuffer *eb) return 0; } +static void eb_reloc_signal(struct i915_execbuffer *eb, struct i915_request *rq) +{ + dma_fence_proxy_set_real(eb->reloc_cache.fence, &rq->fence); + i915_request_put(eb->reloc_cache.rq); + + dma_fence_put(eb->reloc_cache.fence); + eb->reloc_cache.fence = NULL; +} + static int eb_move_to_gpu(struct i915_execbuffer *eb) { const unsigned int count = eb->buffer_count; @@ -1953,10 +1979,15 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, if (err) goto err_commit_unlock; - /* Wait for all writes (and relocs) into the batch to complete */ - err = i915_sw_fence_await_reservation(&pw->base.chain, - pw->batch->resv, NULL, false, - 0, I915_FENCE_GFP); + /* Wait for all writes (or relocs) into the batch to complete */ + if (!eb->reloc_cache.fence || list_empty(&eb->batch->reloc_link)) + err = i915_sw_fence_await_reservation(&pw->base.chain, + pw->batch->resv, NULL, + false, 0, I915_FENCE_GFP); + else + err = i915_sw_fence_await_dma_fence(&pw->base.chain, + &eb->reloc_cache.rq->fence, + 0, I915_FENCE_GFP); if (err < 0) goto err_commit_unlock; @@ -2084,6 +2115,15 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) { int err; + if (eb->reloc_cache.fence) { + err = i915_request_await_dma_fence(eb->request, + &eb->reloc_cache.rq->fence); + if (err) + return err; + + eb_reloc_signal(eb, eb->request); + } + err = eb_move_to_gpu(eb); if (err) return err; @@ -2743,6 +2783,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (batch->private) intel_gt_buffer_pool_put(batch->private); err_vma: + if (eb.reloc_cache.fence) + eb_reloc_signal(&eb, eb.reloc_cache.rq); if (eb.trampoline) i915_vma_unpin(eb.trampoline); eb_unpin_engine(&eb); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 4f10b51f9a7e..62bba179b455 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -23,7 +23,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, const u64 mask = GENMASK_ULL(eb->reloc_cache.use_64bit_reloc ? 63 : 31, 0); const u32 *map = page_mask_bits(obj->mm.mapping); - struct i915_request *rq; struct eb_vma ev; int err; int i; @@ -40,6 +39,9 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + /* Single stage pipeline in the selftest */ + eb->reloc_cache.fence = &eb->reloc_cache.rq->fence; + list_add(&ev.reloc_link, &eb->relocs); err = lock_relocs(eb); if (err) @@ -71,8 +73,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; - GEM_BUG_ON(!eb->reloc_cache.rq); - rq = i915_request_get(eb->reloc_cache.rq); reloc_gpu_flush(&eb->reloc_cache); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); @@ -81,7 +81,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, goto put_rq; } - if (!i915_request_completed(rq)) { + if (!i915_request_completed(eb->reloc_cache.rq)) { pr_err("%s: did not wait for relocations!\n", eb->engine->name); err = -EINVAL; goto put_rq; @@ -100,7 +100,8 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, igt_hexdump(map, 4096); put_rq: - i915_request_put(rq); + i915_request_put(eb->reloc_cache.rq); + eb->reloc_cache.rq = NULL; unpin_vma: i915_vma_unpin(ev.vma); return err; -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:43 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:43 +0100 Subject: [Intel-gfx] [PATCH 14/22] drm/i915/gem: Async GPU relocations only In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-14-chris@chris-wilson.co.uk> Reduce the 3 relocation patches down to the single path that accommodates all. The primary motivation for this is to guard the relocations with a natural fence (derived from the i915_request used to write the relocation from the GPU). The tradeoff in using async gpu relocations is that it increases latency over using direct CPU relocations, for the cases where the target is idle and accessible by the CPU. The benefit is greatly reduced lock contention and improved concurrency by pipelining. Note that forcing the async gpu relocations does reveal a few issues they have. Firstly, is that they are visible as writes to gem_busy, causing to mark some buffers are being to written to by the GPU even though userspace only reads. Secondly is that, in combination with the cmdparser, they can cause priority inversions. This should be the case where the work is being put into a common workqueue losing our priority information and so being executed in FIFO from the worker, denying us the opportunity to reorder the requests afterwards. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 295 ++---------------- .../i915/gem/selftests/i915_gem_execbuffer.c | 21 +- 2 files changed, 27 insertions(+), 289 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 3e87deb35626..ae3a3ff3535b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -45,13 +45,6 @@ struct eb_vma_array { struct eb_vma vma[]; }; -enum { - FORCE_CPU_RELOC = 1, - FORCE_GTT_RELOC, - FORCE_GPU_RELOC, -#define DBG_FORCE_RELOC 0 /* choose one of the above! */ -}; - #define __EXEC_OBJECT_HAS_PIN BIT(31) #define __EXEC_OBJECT_HAS_FENCE BIT(30) #define __EXEC_OBJECT_NEEDS_MAP BIT(29) @@ -260,8 +253,6 @@ struct i915_execbuffer { */ struct reloc_cache { struct drm_mm_node node; /** temporary GTT binding */ - unsigned long vaddr; /** Current kmap address */ - unsigned long page; /** Currently mapped page index */ unsigned int gen; /** Cached value of INTEL_GEN */ bool use_64bit_reloc : 1; bool has_llc : 1; @@ -605,23 +596,6 @@ eb_add_vma(struct i915_execbuffer *eb, } } -static inline int use_cpu_reloc(const struct reloc_cache *cache, - const struct drm_i915_gem_object *obj) -{ - if (!i915_gem_object_has_struct_page(obj)) - return false; - - if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) - return true; - - if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) - return false; - - return (cache->has_llc || - obj->cache_dirty || - obj->cache_level != I915_CACHE_NONE); -} - static int eb_reserve_vma(const struct i915_execbuffer *eb, struct eb_vma *ev, u64 pin_flags) @@ -945,8 +919,6 @@ relocation_target(const struct drm_i915_gem_relocation_entry *reloc, static void reloc_cache_init(struct reloc_cache *cache, struct drm_i915_private *i915) { - cache->page = -1; - cache->vaddr = 0; /* Must be a variable in the struct to allow GCC to unroll. */ cache->gen = INTEL_GEN(i915); cache->has_llc = HAS_LLC(i915); @@ -1089,181 +1061,6 @@ static int reloc_gpu_flush(struct reloc_cache *cache) return err; } -static void reloc_cache_reset(struct reloc_cache *cache) -{ - void *vaddr; - - if (!cache->vaddr) - return; - - vaddr = unmask_page(cache->vaddr); - if (cache->vaddr & KMAP) { - if (cache->vaddr & CLFLUSH_AFTER) - mb(); - - kunmap_atomic(vaddr); - i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); - } else { - struct i915_ggtt *ggtt = cache_to_ggtt(cache); - - intel_gt_flush_ggtt_writes(ggtt->vm.gt); - io_mapping_unmap_atomic((void __iomem *)vaddr); - - if (drm_mm_node_allocated(&cache->node)) { - ggtt->vm.clear_range(&ggtt->vm, - cache->node.start, - cache->node.size); - mutex_lock(&ggtt->vm.mutex); - drm_mm_remove_node(&cache->node); - mutex_unlock(&ggtt->vm.mutex); - } else { - i915_vma_unpin((struct i915_vma *)cache->node.mm); - } - } - - cache->vaddr = 0; - cache->page = -1; -} - -static void *reloc_kmap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - void *vaddr; - - if (cache->vaddr) { - kunmap_atomic(unmask_page(cache->vaddr)); - } else { - unsigned int flushes; - int err; - - err = i915_gem_object_prepare_write(obj, &flushes); - if (err) - return ERR_PTR(err); - - BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); - BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); - - cache->vaddr = flushes | KMAP; - cache->node.mm = (void *)obj; - if (flushes) - mb(); - } - - vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); - cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; - cache->page = page; - - return vaddr; -} - -static void *reloc_iomap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - struct i915_ggtt *ggtt = cache_to_ggtt(cache); - unsigned long offset; - void *vaddr; - - if (cache->vaddr) { - intel_gt_flush_ggtt_writes(ggtt->vm.gt); - io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); - } else { - struct i915_vma *vma; - int err; - - if (i915_gem_object_is_tiled(obj)) - return ERR_PTR(-EINVAL); - - if (use_cpu_reloc(cache, obj)) - return NULL; - - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); - if (err) - return ERR_PTR(err); - - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, - PIN_MAPPABLE | - PIN_NONBLOCK /* NOWARN */ | - PIN_NOEVICT); - if (IS_ERR(vma)) { - memset(&cache->node, 0, sizeof(cache->node)); - mutex_lock(&ggtt->vm.mutex); - err = drm_mm_insert_node_in_range - (&ggtt->vm.mm, &cache->node, - PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, - 0, ggtt->mappable_end, - DRM_MM_INSERT_LOW); - mutex_unlock(&ggtt->vm.mutex); - if (err) /* no inactive aperture space, use cpu reloc */ - return NULL; - } else { - cache->node.start = vma->node.start; - cache->node.mm = (void *)vma; - } - } - - offset = cache->node.start; - if (drm_mm_node_allocated(&cache->node)) { - ggtt->vm.insert_page(&ggtt->vm, - i915_gem_object_get_dma_address(obj, page), - offset, I915_CACHE_NONE, 0); - } else { - offset += page << PAGE_SHIFT; - } - - vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, - offset); - cache->page = page; - cache->vaddr = (unsigned long)vaddr; - - return vaddr; -} - -static void *reloc_vaddr(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - void *vaddr; - - if (cache->page == page) { - vaddr = unmask_page(cache->vaddr); - } else { - vaddr = NULL; - if ((cache->vaddr & KMAP) == 0) - vaddr = reloc_iomap(obj, cache, page); - if (!vaddr) - vaddr = reloc_kmap(obj, cache, page); - } - - return vaddr; -} - -static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) -{ - if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { - if (flushes & CLFLUSH_BEFORE) { - clflushopt(addr); - mb(); - } - - *addr = value; - - /* - * Writes to the same cacheline are serialised by the CPU - * (including clflush). On the write path, we only require - * that it hits memory in an orderly fashion and place - * mb barriers at the start and end of the relocation phase - * to ensure ordering of clflush wrt to the system. - */ - if (flushes & CLFLUSH_AFTER) - clflushopt(addr); - } else - *addr = value; -} - static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) { struct drm_i915_gem_object *obj = vma->obj; @@ -1429,17 +1226,6 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, return cmd; } -static inline bool use_reloc_gpu(struct i915_vma *vma) -{ - if (DBG_FORCE_RELOC == FORCE_GPU_RELOC) - return true; - - if (DBG_FORCE_RELOC) - return false; - - return !dma_resv_test_signaled_rcu(vma->resv, true); -} - static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) { struct page *page; @@ -1454,10 +1240,10 @@ static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) return addr + offset_in_page(offset); } -static bool __reloc_entry_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - u64 offset, - u64 target_addr) +static int __reloc_entry_gpu(struct i915_execbuffer *eb, + struct i915_vma *vma, + u64 offset, + u64 target_addr) { const unsigned int gen = eb->reloc_cache.gen; unsigned int len; @@ -1473,7 +1259,7 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, batch = reloc_gpu(eb, vma, len); if (IS_ERR(batch)) - return false; + return PTR_ERR(batch); addr = gen8_canonical_addr(vma->node.start + offset); if (gen >= 8) { @@ -1522,55 +1308,21 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, *batch++ = target_addr; } - return true; -} - -static bool reloc_entry_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - u64 offset, - u64 target_addr) -{ - if (eb->reloc_cache.vaddr) - return false; - - if (!use_reloc_gpu(vma)) - return false; - - return __reloc_entry_gpu(eb, vma, offset, target_addr); + return 0; } static u64 -relocate_entry(struct i915_vma *vma, +relocate_entry(struct i915_execbuffer *eb, + struct i915_vma *vma, const struct drm_i915_gem_relocation_entry *reloc, - struct i915_execbuffer *eb, const struct i915_vma *target) { u64 target_addr = relocation_target(reloc, target); - u64 offset = reloc->offset; - - if (!reloc_entry_gpu(eb, vma, offset, target_addr)) { - bool wide = eb->reloc_cache.use_64bit_reloc; - void *vaddr; - -repeat: - vaddr = reloc_vaddr(vma->obj, - &eb->reloc_cache, - offset >> PAGE_SHIFT); - if (IS_ERR(vaddr)) - return PTR_ERR(vaddr); - - GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32))); - clflush_write32(vaddr + offset_in_page(offset), - lower_32_bits(target_addr), - eb->reloc_cache.vaddr); - - if (wide) { - offset += sizeof(u32); - target_addr >>= 32; - wide = false; - goto repeat; - } - } + int err; + + err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); + if (err) + return err; return target->node.start | UPDATE; } @@ -1635,8 +1387,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, * If the relocation already has the right value in it, no * more work needs to be done. */ - if (!DBG_FORCE_RELOC && - gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) return 0; /* Check that the relocation address is valid... */ @@ -1668,7 +1419,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, ev->flags &= ~EXEC_OBJECT_ASYNC; /* and update the user's relocation entry */ - return relocate_entry(ev->vma, reloc, eb, target->vma); + return relocate_entry(eb, ev->vma, reloc, target->vma); } static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) @@ -1706,10 +1457,8 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) * this is bad and so lockdep complains vehemently. */ copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); - if (unlikely(copied)) { - remain = -EFAULT; - goto out; - } + if (unlikely(copied)) + return -EFAULT; remain -= count; do { @@ -1717,8 +1466,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) if (likely(offset == 0)) { } else if ((s64)offset < 0) { - remain = (int)offset; - goto out; + return (int)offset; } else { /* * Note that reporting an error now @@ -1748,9 +1496,8 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); -out: - reloc_cache_reset(&eb->reloc_cache); - return remain; + + return 0; } static int eb_relocate(struct i915_execbuffer *eb) @@ -2658,7 +2405,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.i915 = i915; eb.file = file; eb.args = args; - if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) + if (!(args->flags & I915_EXEC_NO_RELOC)) args->flags |= __EXEC_HAS_RELOC; eb.exec = exec; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index a49016f8ee0d..57c14d3340cd 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -37,20 +37,14 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, return err; /* 8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[0] * sizeof(u32), - 0)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + if (err) goto unpin_vma; - } /* !8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[1] * sizeof(u32), - 1)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + if (err) goto unpin_vma; - } /* Skip to the end of the cmd page */ i = PAGE_SIZE / sizeof(u32) - RELOC_TAIL - 1; @@ -60,12 +54,9 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - if (!__reloc_entry_gpu(eb, vma, - offsets[2] * sizeof(u32), - 2)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + if (err) goto unpin_vma; - } GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:45 +0100 Subject: [Intel-gfx] [PATCH 16/22] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-16-chris@chris-wilson.co.uk> Over the next couple of patches, we will want to lock all the modified vma for relocation processing under a single ww_mutex. We neither want to have to include the vma that are skipped (due to no modifications required) nor do we want those to be marked as written too. So separate out the reloc validation into an early step, which we can use both to reject the execbuf before committing to making our changes, and to filter out the unmodified vma. This does introduce a second pass through the reloc[], but only if we need to emit relocations. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 178 +++++++++++++----- 1 file changed, 133 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index ae3a3ff3535b..eda770f36b34 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1331,6 +1331,117 @@ static u64 eb_relocate_entry(struct i915_execbuffer *eb, struct eb_vma *ev, const struct drm_i915_gem_relocation_entry *reloc) +{ + struct eb_vma *target; + + /* we've already hold a reference to all valid objects */ + target = eb_get_vma(eb, reloc->target_handle); + if (unlikely(!target)) + return -ENOENT; + + /* + * If the relocation already has the right value in it, no + * more work needs to be done. + */ + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) + return 0; + + /* + * If we write into the object, we need to force the synchronisation + * barrier, either with an asynchronous clflush or if we executed the + * patching using the GPU (though that should be serialised by the + * timeline). To be completely sure, and since we are required to + * do relocations we are already stalling, disable the user's opt + * out of our synchronisation. + */ + ev->flags &= ~EXEC_OBJECT_ASYNC; + + /* and update the user's relocation entry */ + return relocate_entry(eb, ev->vma, reloc, target->vma); +} + +static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +{ +#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) + struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; + const struct drm_i915_gem_exec_object2 *entry = ev->exec; + struct drm_i915_gem_relocation_entry __user *urelocs = + u64_to_user_ptr(entry->relocs_ptr); + unsigned long remain = entry->relocation_count; + + if (unlikely(remain > N_RELOC(ULONG_MAX))) + return -EINVAL; + + /* + * We must check that the entire relocation array is safe + * to read. However, if the array is not writable the user loses + * the updated relocation values. + */ + if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs)))) + return -EFAULT; + + do { + struct drm_i915_gem_relocation_entry *r = stack; + unsigned int count = + min_t(unsigned long, remain, ARRAY_SIZE(stack)); + unsigned int copied; + + /* + * This is the fast path and we cannot handle a pagefault + * whilst holding the struct mutex lest the user pass in the + * relocations contained within a mmaped bo. For in such a case + * we, the page fault handler would call i915_gem_fault() and + * we would try to acquire the struct mutex again. Obviously + * this is bad and so lockdep complains vehemently. + */ + copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); + if (unlikely(copied)) + return -EFAULT; + + remain -= count; + do { + u64 offset = eb_relocate_entry(eb, ev, r); + + if (likely(offset == 0)) { + } else if ((s64)offset < 0) { + return (int)offset; + } else { + /* + * Note that reporting an error now + * leaves everything in an inconsistent + * state as we have *already* changed + * the relocation value inside the + * object. As we have not changed the + * reloc.presumed_offset or will not + * change the execobject.offset, on the + * call we may not rewrite the value + * inside the object, leaving it + * dangling and causing a GPU hang. Unless + * userspace dynamically rebuilds the + * relocations on each execbuf rather than + * presume a static tree. + * + * We did previously check if the relocations + * were writable (access_ok), an error now + * would be a strange race with mprotect, + * having already demonstrated that we + * can read from this userspace address. + */ + offset = gen8_canonical_addr(offset & ~UPDATE); + __put_user(offset, + &urelocs[r - stack].presumed_offset); + } + } while (r++, --count); + urelocs += ARRAY_SIZE(stack); + } while (remain); + + return 0; +} + +static int +eb_reloc_valid(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc) { struct drm_i915_private *i915 = eb->i915; struct eb_vma *target; @@ -1408,21 +1519,10 @@ eb_relocate_entry(struct i915_execbuffer *eb, return -EINVAL; } - /* - * If we write into the object, we need to force the synchronisation - * barrier, either with an asynchronous clflush or if we executed the - * patching using the GPU (though that should be serialised by the - * timeline). To be completely sure, and since we are required to - * do relocations we are already stalling, disable the user's opt - * out of our synchronisation. - */ - ev->flags &= ~EXEC_OBJECT_ASYNC; - - /* and update the user's relocation entry */ - return relocate_entry(eb, ev->vma, reloc, target->vma); + return 1; } -static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) { #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; @@ -1430,6 +1530,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) struct drm_i915_gem_relocation_entry __user *urelocs = u64_to_user_ptr(entry->relocs_ptr); unsigned long remain = entry->relocation_count; + long required = 0; if (unlikely(remain > N_RELOC(ULONG_MAX))) return -EINVAL; @@ -1462,42 +1563,18 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) remain -= count; do { - u64 offset = eb_relocate_entry(eb, ev, r); + int ret; - if (likely(offset == 0)) { - } else if ((s64)offset < 0) { - return (int)offset; - } else { - /* - * Note that reporting an error now - * leaves everything in an inconsistent - * state as we have *already* changed - * the relocation value inside the - * object. As we have not changed the - * reloc.presumed_offset or will not - * change the execobject.offset, on the - * call we may not rewrite the value - * inside the object, leaving it - * dangling and causing a GPU hang. Unless - * userspace dynamically rebuilds the - * relocations on each execbuf rather than - * presume a static tree. - * - * We did previously check if the relocations - * were writable (access_ok), an error now - * would be a strange race with mprotect, - * having already demonstrated that we - * can read from this userspace address. - */ - offset = gen8_canonical_addr(offset & ~UPDATE); - __put_user(offset, - &urelocs[r - stack].presumed_offset); - } + ret = eb_reloc_valid(eb, ev, r); + if (ret < 0) + return ret; + + required += ret; } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); - return 0; + return required; } static int eb_relocate(struct i915_execbuffer *eb) @@ -1516,9 +1593,20 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { - struct eb_vma *ev; + struct eb_vma *ev, *en; int flush; + list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { + long count; + + count = eb_reloc_vma_validate(eb, ev); + if (count < 0) + return count; + + if (count == 0) + list_del_init(&ev->reloc_link); + } + list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:30 +0100 Subject: [Intel-gfx] [PATCH 01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser Message-ID: <20200604103751.18816-1-chris@chris-wilson.co.uk> If the execbuf is interrupted after building the cmdparser pipeline, and before we commit to submitting the request to HW, we would attempt to clean up the cmdparser early. While we held active references to the vma being parsed and constructed, we did not hold an active reference for the buffer pool itself. The result was that an interrupted execbuf could still have run the cmdparser pipeline, but since the buffer pool was idle, its target vma could have been recycled. Note this problem only occurs if the cmdparser is running async due to pipelined waits on busy fences, and the execbuf is interrupted. Fixes: 686c7c35abc2 ("drm/i915/gem: Asynchronous cmdparser") Fixes: 16e87459673a ("drm/i915/gt: Move the batch buffer pool from the engine to the gt") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 56 ++++++++++++++++--- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 02a5c0ce39ca..3e87deb35626 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1987,6 +1987,38 @@ static const struct dma_fence_work_ops eb_parse_ops = { .release = __eb_parse_release, }; +static inline int +__parser_mark_active(struct i915_vma *vma, + struct intel_timeline *tl, + struct dma_fence *fence) +{ + struct intel_gt_buffer_pool_node *node = vma->private; + + return i915_active_ref(&node->active, tl, fence); +} + +static int +parser_mark_active(struct eb_parse_work *pw, struct intel_timeline *tl) +{ + int err; + + mutex_lock(&tl->mutex); + + err = __parser_mark_active(pw->shadow, tl, &pw->base.dma); + if (err) + goto unlock; + + if (pw->trampoline) { + err = __parser_mark_active(pw->trampoline, tl, &pw->base.dma); + if (err) + goto unlock; + } + +unlock: + mutex_unlock(&tl->mutex); + return err; +} + static int eb_parse_pipeline(struct i915_execbuffer *eb, struct i915_vma *shadow, struct i915_vma *trampoline) @@ -2021,20 +2053,25 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, pw->shadow = shadow; pw->trampoline = trampoline; + /* Mark active refs for this worker, in case we get interrupted */ + err = parser_mark_active(pw, eb->context->timeline); + if (err) + goto err_commit; + err = dma_resv_lock_interruptible(pw->batch->resv, NULL); if (err) - goto err_trampoline; + goto err_commit; err = dma_resv_reserve_shared(pw->batch->resv, 1); if (err) - goto err_batch_unlock; + goto err_commit_unlock; /* Wait for all writes (and relocs) into the batch to complete */ err = i915_sw_fence_await_reservation(&pw->base.chain, pw->batch->resv, NULL, false, 0, I915_FENCE_GFP); if (err < 0) - goto err_batch_unlock; + goto err_commit_unlock; /* Keep the batch alive and unwritten as we parse */ dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma); @@ -2049,11 +2086,13 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, dma_fence_work_commit_imm(&pw->base); return 0; -err_batch_unlock: +err_commit_unlock: dma_resv_unlock(pw->batch->resv); -err_trampoline: - if (trampoline) - i915_active_release(&trampoline->active); +err_commit: + i915_sw_fence_set_error_once(&pw->base.chain, err); + dma_fence_work_commit_imm(&pw->base); + return err; + err_shadow: i915_active_release(&shadow->active); err_batch: @@ -2099,6 +2138,7 @@ static int eb_parse(struct i915_execbuffer *eb) goto err; } i915_gem_object_set_readonly(shadow->obj); + shadow->private = pool; trampoline = NULL; if (CMDPARSER_USES_GGTT(eb->i915)) { @@ -2112,6 +2152,7 @@ static int eb_parse(struct i915_execbuffer *eb) shadow = trampoline; goto err_shadow; } + shadow->private = pool; eb->batch_flags |= I915_DISPATCH_SECURE; } @@ -2128,7 +2169,6 @@ static int eb_parse(struct i915_execbuffer *eb) eb->trampoline = trampoline; eb->batch_start_offset = 0; - shadow->private = pool; return 0; err_trampoline: -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:40 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:40 +0100 Subject: [Intel-gfx] [PATCH 11/22] drm/i915/gt: Track if an engine requires forcewake w/a In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-11-chris@chris-wilson.co.uk> Sometimes an engine might need to keep forcewake active while it is busy submitting requests for a particular workaround. Track such nuisance with engine->fw_domain. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 ++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_ring_scheduler.c | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 3782e27c2945..d3ca8e8f605f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -24,6 +24,7 @@ #include "i915_selftest.h" #include "intel_sseu.h" #include "intel_timeline_types.h" +#include "intel_uncore.h" #include "intel_wakeref.h" #include "intel_workarounds_types.h" @@ -313,6 +314,15 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + /* + * Some w/a require forcewake to be held (which prevents RC6) while + * a particular engine is active. If so, we set fw_domain to which + * domains need to be held for the duration of request activity, + * and 0 if none. + */ + enum forcewake_domains fw_domain; + unsigned int fw_active; + unsigned long context_tag; struct rb_node uabi_node; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 10d83d6327b1..5f9a66fc9649 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1341,6 +1341,8 @@ __execlists_schedule_in(struct i915_request *rq) ce->lrc.ccid |= engine->execlists.ccid; __intel_gt_pm_get(engine->gt); + if (!engine->fw_active++ && engine->fw_domain) + intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); @@ -1409,6 +1411,8 @@ __execlists_schedule_out(struct i915_request *rq, intel_context_update_runtime(ce); intel_engine_context_out(engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); + if (!--engine->fw_active && engine->fw_domain) + intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); /* diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index aaff554865b1..777cab6d9540 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -60,6 +60,8 @@ static struct i915_request * schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) { __intel_gt_pm_get(engine->gt); + if (!engine->fw_active++ && engine->fw_domain) + intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); intel_engine_context_in(engine); return i915_request_get(rq); } @@ -74,6 +76,8 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_put(rq); intel_engine_context_out(engine); + if (!--engine->fw_active && engine->fw_domain) + intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); } -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:39 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:39 +0100 Subject: [Intel-gfx] [PATCH 10/22] drm/i915/gt: Enable busy-stats for ring-scheduler In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-10-chris@chris-wilson.co.uk> Couple up the context in/out accounting to record how long each engine is busy handling requests. This is exposed to userspace for more accurate measurements, and also enables our soft-rps timer. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------ .../gpu/drm/i915/gt/intel_ring_scheduler.c | 4 + drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 90 +++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ 5 files changed, 149 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include <linux/atomic.h> +#include <linux/ktime.h> +#include <linux/seqlock.h> + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d95b5261f59f..10d83d6327b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1187,39 +1188,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index c8cd435d1c51..aaff554865b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_context.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -59,6 +60,7 @@ static struct i915_request * schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) { __intel_gt_pm_get(engine->gt); + intel_engine_context_in(engine); return i915_request_get(rq); } @@ -71,6 +73,7 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) intel_engine_add_retire(engine, ce->timeline); i915_request_put(rq); + intel_engine_context_out(engine); intel_gt_pm_put_async(engine->gt); } @@ -747,6 +750,7 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) engine->legacy.ring = ring; engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; + engine->flags |= I915_ENGINE_SUPPORTS_STATS; /* Finally, take ownership and responsibility for cleanup! */ engine->release = ring_release; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..fef9709b7cfa 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,95 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t dt, de; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + break; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (100 * de < 95 * dt) { + pr_err("%s: reported only %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + igt_spinner_fini(&spin); + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +166,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:32 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:32 +0100 Subject: [Intel-gfx] [PATCH 03/22] drm/i915/gt: Set timeslicing priority from queue In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-3-chris@chris-wilson.co.uk> If we only submit the first port, leaving the second empty yet have ready requests pending in the queue, use that to set the timeslicing priority (i.e. the priority at which we will decided to enabling timeslicing and evict the currently active context if the queue is of equal priority after its quantum expired). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index aac8da18694f..c27f4279ae53 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1962,7 +1962,7 @@ static int switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq) { if (list_is_last(&rq->sched.link, &engine->active.requests)) - return INT_MIN; + return engine->execlists.queue_priority_hint; return rq_prio(list_next_entry(rq, sched.link)); } -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:50 +0100 Subject: [Intel-gfx] [PATCH 21/22] drm/i915: Unpeel awaits on a proxy fence In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-21-chris@chris-wilson.co.uk> If the real target for a proxy fence is known at the time we are attaching our awaits, use the real target in preference to hooking up to the proxy. If use the real target instead, we can optimize the awaits, e.g. if it along the same engine, we can order the submission and avoid the wait-for-completion. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_request.c | 157 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_scheduler.c | 41 +++++++ drivers/gpu/drm/i915/i915_scheduler.h | 3 + 3 files changed, 201 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..70c07c13794c 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -24,6 +24,7 @@ #include <linux/dma-fence-array.h> #include <linux/dma-fence-chain.h> +#include <linux/dma-fence-proxy.h> #include <linux/irq_work.h> #include <linux/prefetch.h> #include <linux/sched.h> @@ -461,6 +462,7 @@ static bool fatal_error(int error) case 0: /* not an error! */ case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */ case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */ + case -EDEADLK: /* cyclic fence lockup (await_proxy) */ return false; default: return true; @@ -1241,6 +1243,138 @@ i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) return err; } +struct await_proxy { + struct wait_queue_entry base; + struct i915_request *request; + struct dma_fence *fence; + struct timer_list timer; + struct work_struct work; + int (*attach)(struct await_proxy *ap); + void *data; +}; + +static void await_proxy_work(struct work_struct *work) +{ + struct await_proxy *ap = container_of(work, typeof(*ap), work); + struct i915_request *rq = ap->request; + + del_timer_sync(&ap->timer); + + if (ap->fence) { + int err = 0; + + /* + * If the fence is external, we impose a 10s timeout. + * However, if the fence is internal, we skip a timeout in + * the belief that all fences are in-order (DAG, no cycles) + * and we can enforce forward progress by reset the GPU if + * necessary. A future fence, provided userspace, can trivially + * generate a cycle in the dependency graph, and so cause + * that entire cycle to become deadlocked and for no forward + * progress to either be made, and the driver being kept + * eternally awake. + */ + if (dma_fence_is_i915(ap->fence) && + !i915_sched_node_verify_dag(&rq->sched, + &to_request(ap->fence)->sched)) + err = -EDEADLK; + + if (!err) { + mutex_lock(&rq->context->timeline->mutex); + err = ap->attach(ap); + mutex_unlock(&rq->context->timeline->mutex); + } + + /* Don't flag an error for co-dependent scheduling */ + if (err == -EDEADLK) { + struct i915_sched_node *waiter = + &to_request(ap->fence)->sched; + struct i915_dependency *p; + + list_for_each_entry_lockless(p, + &rq->sched.waiters_list, + wait_link) { + if (p->waiter == waiter && + p->flags & I915_DEPENDENCY_WEAK) { + err = 0; + break; + } + } + } + + if (err < 0) + i915_sw_fence_set_error_once(&rq->submit, err); + } + + i915_sw_fence_complete(&rq->submit); + + dma_fence_put(ap->fence); + kfree(ap); +} + +static int +await_proxy_wake(struct wait_queue_entry *entry, + unsigned int mode, + int flags, + void *fence) +{ + struct await_proxy *ap = container_of(entry, typeof(*ap), base); + + ap->fence = dma_fence_get(fence); + schedule_work(&ap->work); + + return 0; +} + +static void +await_proxy_timer(struct timer_list *t) +{ + struct await_proxy *ap = container_of(t, typeof(*ap), timer); + + if (dma_fence_remove_proxy_listener(ap->base.private, &ap->base)) { + struct i915_request *rq = ap->request; + + pr_notice("Asynchronous wait on unset proxy fence by %s:%s:%llx timed out\n", + rq->fence.ops->get_driver_name(&rq->fence), + rq->fence.ops->get_timeline_name(&rq->fence), + rq->fence.seqno); + i915_sw_fence_set_error_once(&rq->submit, -ETIMEDOUT); + + schedule_work(&ap->work); + } +} + +static int +__i915_request_await_proxy(struct i915_request *rq, + struct dma_fence *fence, + unsigned long timeout, + int (*attach)(struct await_proxy *ap), + void *data) +{ + struct await_proxy *ap; + + ap = kzalloc(sizeof(*ap), I915_FENCE_GFP); + if (!ap) + return -ENOMEM; + + i915_sw_fence_await(&rq->submit); + mark_external(rq); + + ap->base.private = fence; + ap->base.func = await_proxy_wake; + ap->request = rq; + INIT_WORK(&ap->work, await_proxy_work); + ap->attach = attach; + ap->data = data; + + timer_setup(&ap->timer, await_proxy_timer, 0); + if (timeout) + mod_timer(&ap->timer, round_jiffies_up(jiffies + timeout)); + + dma_fence_add_proxy_listener(fence, &ap->base); + return 0; +} + int i915_request_await_execution(struct i915_request *rq, struct dma_fence *fence, @@ -1339,6 +1473,24 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from) return 0; } +static int await_proxy(struct await_proxy *ap) +{ + return i915_request_await_dma_fence(ap->request, ap->fence); +} + +static int +i915_request_await_proxy(struct i915_request *rq, struct dma_fence *fence) +{ + /* + * Wait until we know the real fence so that can optimise the + * inter-fence synchronisation. + */ + return __i915_request_await_proxy(rq, fence, + i915_fence_context_timeout(rq->engine->i915, + fence->context), + await_proxy, NULL); +} + int i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) { @@ -1346,6 +1498,9 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) unsigned int nchild = 1; int ret; + /* Unpeel the proxy fence if the real target is already known */ + fence = dma_fence_proxy_get_real(fence); + /* * Note that if the fence-array was created in signal-on-any mode, * we should *not* decompose it into its individual fences. However, @@ -1385,6 +1540,8 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) if (dma_fence_is_i915(fence)) ret = i915_request_await_request(rq, to_request(fence)); + else if (dma_fence_is_proxy(fence)) + ret = i915_request_await_proxy(rq, fence); else ret = i915_request_await_external(rq, fence); if (ret < 0) diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index cbb880b10c65..250832768279 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -469,6 +469,47 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node, return 0; } +bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, + struct i915_sched_node *signaler) +{ + struct i915_dependency *dep, *p; + struct i915_dependency stack; + bool result = false; + LIST_HEAD(dfs); + + if (list_empty(&waiter->waiters_list)) + return true; + + spin_lock_irq(&schedule_lock); + + stack.signaler = signaler; + list_add(&stack.dfs_link, &dfs); + + list_for_each_entry(dep, &dfs, dfs_link) { + struct i915_sched_node *node = dep->signaler; + + if (node_signaled(node)) + continue; + + list_for_each_entry(p, &node->signalers_list, signal_link) { + if (p->signaler == waiter) + goto out; + + if (list_empty(&p->dfs_link)) + list_add_tail(&p->dfs_link, &dfs); + } + } + + result = true; +out: + list_for_each_entry_safe(dep, p, &dfs, dfs_link) + INIT_LIST_HEAD(&dep->dfs_link); + + spin_unlock_irq(&schedule_lock); + + return result; +} + void i915_sched_node_fini(struct i915_sched_node *node) { struct i915_dependency *dep, *tmp; diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 6f0bf00fc569..13432add8929 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -28,6 +28,9 @@ void i915_sched_node_init(struct i915_sched_node *node); void i915_sched_node_reinit(struct i915_sched_node *node); +bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, + struct i915_sched_node *signal); + bool __i915_sched_node_add_dependency(struct i915_sched_node *node, struct i915_sched_node *signal, struct i915_dependency *dep, -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:47 +0100 Subject: [Intel-gfx] [PATCH 18/22] drm/i915/gem: Build the reloc request first In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-18-chris@chris-wilson.co.uk> If we get interrupted in the middle of chaining up the relocation entries, we will fail to submit the relocation batch. However, we will report having already completed some of the relocations, and so the reloc.presumed_offset will no longer match the batch contents, causing confusion and invalid future batches. If we build the relocation request packet first, we can always emit as far as we get up in the relocation chain. Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 51 ++++++++++--------- .../i915/gem/selftests/i915_gem_execbuffer.c | 8 +-- 2 files changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 06e1a1f2aa1d..4c3461ab8a63 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1021,11 +1021,27 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) return cache->gen > 5 ? 0 : I915_DISPATCH_SECURE; } -static int reloc_gpu_flush(struct reloc_cache *cache) +static int reloc_gpu_emit(struct reloc_cache *cache) { struct i915_request *rq = cache->rq; int err; + err = 0; + if (rq->engine->emit_init_breadcrumb) + err = rq->engine->emit_init_breadcrumb(rq); + if (!err) + err = rq->engine->emit_bb_start(rq, + rq->batch->node.start, + PAGE_SIZE, + reloc_bb_flags(cache)); + + return err; +} + +static void reloc_gpu_flush(struct reloc_cache *cache) +{ + struct i915_request *rq = cache->rq; + if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1037,21 +1053,8 @@ static int reloc_gpu_flush(struct reloc_cache *cache) i915_gem_object_unpin_map(obj); } - err = 0; - if (rq->engine->emit_init_breadcrumb) - err = rq->engine->emit_init_breadcrumb(rq); - if (!err) - err = rq->engine->emit_bb_start(rq, - rq->batch->node.start, - PAGE_SIZE, - reloc_bb_flags(cache)); - if (err) - i915_request_set_error_once(rq, err); - intel_gt_chipset_flush(rq->engine->gt); i915_request_add(rq); - - return err; } static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) @@ -1139,7 +1142,7 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) err = i915_vma_move_to_active(batch, rq, 0); i915_vma_unlock(batch); if (err) - goto skip_request; + goto err_request; rq->batch = batch; i915_vma_unpin(batch); @@ -1152,8 +1155,6 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) /* Return with batch mapping (cmd) still pinned */ goto out_pool; -skip_request: - i915_request_set_error_once(rq, err); err_request: i915_request_add(rq); err_unpin: @@ -1186,10 +1187,8 @@ static u32 *reloc_batch_grow(struct i915_execbuffer *eb, if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); + if (unlikely(err)) return ERR_PTR(err); - } } GEM_BUG_ON(cache->rq_size + len >= PAGE_SIZE / sizeof(u32)); @@ -1571,23 +1570,25 @@ static int reloc_gpu_alloc(struct i915_execbuffer *eb) static int reloc_gpu(struct i915_execbuffer *eb) { struct eb_vma *ev; - int flush, err; + int err; err = reloc_gpu_alloc(eb); if (err) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto out; + list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) - goto out; + break; } out: - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; + reloc_gpu_flush(&eb->reloc_cache); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 50fe22d87ae1..faed6480a792 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -40,6 +40,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -64,9 +68,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); - err = reloc_gpu_flush(&eb->reloc_cache); - if (err) - goto put_rq; + reloc_gpu_flush(&eb->reloc_cache); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:48 +0100 Subject: [Intel-gfx] [PATCH 19/22] drm/i915/gem: Add all GPU reloc awaits/signals en masse In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-19-chris@chris-wilson.co.uk> Asynchronous waits and signaling form a traditional semaphore with all the usual ordering problems with taking multiple locks. If we want to add more than one wait on a shared resource by the GPU, we must ensure that all the associated timelines are advanced atomically, ergo we must lock all the timelines en masse. Testcase: igt/gem_exec_reloc/basic-concurrent16 Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") References: https://gitlab.freedesktop.org/drm/intel/-/issues/1889 Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 114 ++++++++++++------ .../i915/gem/selftests/i915_gem_execbuffer.c | 24 ++-- 2 files changed, 93 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 4c3461ab8a63..373d5eea7a5a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -259,7 +259,6 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; - struct i915_vma *target; struct i915_request *rq; struct i915_vma *rq_vma; u32 *rq_cmd; @@ -924,7 +923,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->target = NULL; } static inline void *unmask_page(unsigned long p) @@ -1057,26 +1055,6 @@ static void reloc_gpu_flush(struct reloc_cache *cache) i915_request_add(rq); } -static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) -{ - struct drm_i915_gem_object *obj = vma->obj; - int err; - - i915_vma_lock(vma); - - if (obj->cache_dirty & ~obj->cache_coherent) - i915_gem_clflush_object(obj, 0); - obj->write_domain = 0; - - err = i915_request_await_object(rq, vma->obj, true); - if (err == 0) - err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - - i915_vma_unlock(vma); - - return err; -} - static int __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { @@ -1166,24 +1144,12 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) return err; } -static u32 *reloc_batch_grow(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (vma != cache->target) { - err = reloc_move_to_gpu(cache->rq, vma); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); - return ERR_PTR(err); - } - - cache->target = vma; - } - if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); @@ -1229,7 +1195,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_batch_grow(eb, vma, len); + batch = reloc_batch_grow(eb, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1549,6 +1515,78 @@ static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) return required; } +static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) +{ + struct i915_request *rq = cache->rq; + struct i915_vma *vma = ev->vma; + struct drm_i915_gem_object *obj = vma->obj; + int err; + + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, 0); + + obj->write_domain = I915_GEM_DOMAIN_RENDER; + obj->read_domains = I915_GEM_DOMAIN_RENDER; + + err = i915_request_await_object(rq, obj, true); + if (err) + return err; + + err = __i915_vma_move_to_active(vma, rq); + if (err) + return err; + + dma_resv_add_excl_fence(vma->resv, &rq->fence); + + return 0; +} + +static int +lock_relocs(struct i915_execbuffer *eb) +{ + struct ww_acquire_ctx acquire; + struct eb_vma *ev; + int err = 0; + + ww_acquire_init(&acquire, &reservation_ww_class); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + struct i915_vma *vma = ev->vma; + + err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); + if (err == -EDEADLK) { + struct eb_vma *unlock = ev, *en; + + list_for_each_entry_safe_continue_reverse(unlock, en, + &eb->relocs, + reloc_link) { + ww_mutex_unlock(&unlock->vma->resv->lock); + list_move_tail(&unlock->reloc_link, + &eb->relocs); + } + + GEM_BUG_ON(!list_is_first(&ev->reloc_link, + &eb->relocs)); + err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, + &acquire); + } + if (err) + break; + } + + ww_acquire_done(&acquire); + + list_for_each_entry_continue_reverse(ev, &eb->relocs, reloc_link) { + if (err == 0) + err = reloc_move_to_gpu(&eb->reloc_cache, ev); + ww_mutex_unlock(&ev->vma->resv->lock); + } + + ww_acquire_fini(&acquire); + + return err; +} + static bool reloc_can_use_engine(const struct intel_engine_cs *engine) { return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); @@ -1577,6 +1615,10 @@ static int reloc_gpu(struct i915_execbuffer *eb) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = lock_relocs(eb); + if (err) + goto out; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index faed6480a792..4f10b51f9a7e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -24,15 +24,15 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GENMASK_ULL(eb->reloc_cache.use_64bit_reloc ? 63 : 31, 0); const u32 *map = page_mask_bits(obj->mm.mapping); struct i915_request *rq; - struct i915_vma *vma; + struct eb_vma ev; int err; int i; - vma = i915_vma_instance(obj, eb->context->vm, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + ev.vma = i915_vma_instance(obj, eb->context->vm, NULL); + if (IS_ERR(ev.vma)) + return PTR_ERR(ev.vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + err = i915_vma_pin(ev.vma, 0, 0, PIN_USER | PIN_HIGH); if (err) return err; @@ -40,17 +40,22 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + list_add(&ev.reloc_link, &eb->relocs); + err = lock_relocs(eb); + if (err) + goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto unpin_vma; /* 8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + err = __reloc_entry_gpu(eb, ev.vma, offsets[0] * sizeof(u32), 0); if (err) goto unpin_vma; /* !8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + err = __reloc_entry_gpu(eb, ev.vma, offsets[1] * sizeof(u32), 1); if (err) goto unpin_vma; @@ -62,7 +67,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + err = __reloc_entry_gpu(eb, ev.vma, offsets[2] * sizeof(u32), 2); if (err) goto unpin_vma; @@ -97,7 +102,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, put_rq: i915_request_put(rq); unpin_vma: - i915_vma_unpin(vma); + i915_vma_unpin(ev.vma); return err; } @@ -121,6 +126,7 @@ static int igt_gpu_reloc(void *arg) } for_each_uabi_engine(eb.engine, eb.i915) { + INIT_LIST_HEAD(&eb.relocs); reloc_cache_init(&eb.reloc_cache, eb.i915); memset(map, POISON_INUSE, 4096); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:46 +0100 Subject: [Intel-gfx] [PATCH 17/22] drm/i915/gem: Lift GPU relocation allocation In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-17-chris@chris-wilson.co.uk> Since we have reduced the relocations paths to just use the async GPU, we can lift the request allocation to the start of the relocations. Knowing that we use one request for all relocations will simplify tracking the relocation fence. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 98 ++++++++++--------- .../i915/gem/selftests/i915_gem_execbuffer.c | 5 +- 2 files changed, 56 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index eda770f36b34..06e1a1f2aa1d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -900,8 +900,6 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) static void eb_destroy(const struct i915_execbuffer *eb) { - GEM_BUG_ON(eb->reloc_cache.rq); - if (eb->array) eb_vma_array_put(eb->array); @@ -926,7 +924,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->rq = NULL; cache->target = NULL; } @@ -1026,13 +1023,9 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) static int reloc_gpu_flush(struct reloc_cache *cache) { - struct i915_request *rq; + struct i915_request *rq = cache->rq; int err; - rq = fetch_and_zero(&cache->rq); - if (!rq) - return 0; - if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1081,9 +1074,8 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) return err; } -static int __reloc_gpu_alloc(struct i915_execbuffer *eb, - struct intel_engine_cs *engine, - unsigned int len) +static int +__reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { struct reloc_cache *cache = &eb->reloc_cache; struct intel_gt_buffer_pool_node *pool; @@ -1173,33 +1165,14 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, return err; } -static bool reloc_can_use_engine(const struct intel_engine_cs *engine) -{ - return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); -} - -static u32 *reloc_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, + struct i915_vma *vma, + unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (unlikely(!cache->rq)) { - struct intel_engine_cs *engine = eb->engine; - - if (!reloc_can_use_engine(engine)) { - engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; - if (!engine) - return ERR_PTR(-ENODEV); - } - - err = __reloc_gpu_alloc(eb, engine, len); - if (unlikely(err)) - return ERR_PTR(err); - } - if (vma != cache->target) { err = reloc_move_to_gpu(cache->rq, vma); if (unlikely(err)) { @@ -1257,7 +1230,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_gpu(eb, vma, len); + batch = reloc_batch_grow(eb, vma, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1577,6 +1550,47 @@ static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) return required; } +static bool reloc_can_use_engine(const struct intel_engine_cs *engine) +{ + return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); +} + +static int reloc_gpu_alloc(struct i915_execbuffer *eb) +{ + struct intel_engine_cs *engine = eb->engine; + + if (!reloc_can_use_engine(engine)) { + engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; + if (!engine) + return -ENODEV; + } + + return __reloc_gpu_alloc(eb, engine); +} + +static int reloc_gpu(struct i915_execbuffer *eb) +{ + struct eb_vma *ev; + int flush, err; + + err = reloc_gpu_alloc(eb); + if (err) + return err; + GEM_BUG_ON(!eb->reloc_cache.rq); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + err = eb_relocate_vma(eb, ev); + if (err) + goto out; + } + +out: + flush = reloc_gpu_flush(&eb->reloc_cache); + if (!err) + err = flush; + return err; +} + static int eb_relocate(struct i915_execbuffer *eb) { int err; @@ -1594,7 +1608,6 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { struct eb_vma *ev, *en; - int flush; list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { long count; @@ -1607,18 +1620,14 @@ static int eb_relocate(struct i915_execbuffer *eb) list_del_init(&ev->reloc_link); } - list_for_each_entry(ev, &eb->relocs, reloc_link) { - err = eb_relocate_vma(eb, ev); + if (!list_empty(&eb->relocs)) { + err = reloc_gpu(eb); if (err) - break; + return err; } - - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; } - return err; + return 0; } static int eb_move_to_gpu(struct i915_execbuffer *eb) @@ -2618,9 +2627,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, batch = vma; } - /* All GPU relocation batches must be submitted prior to the user rq */ - GEM_BUG_ON(eb.reloc_cache.rq); - /* Allocate a request for this batch buffer nice and early. */ eb.request = i915_request_create(eb.context); if (IS_ERR(eb.request)) { diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 57c14d3340cd..50fe22d87ae1 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -36,6 +36,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) return err; + err = reloc_gpu_alloc(eb); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -63,7 +67,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, err = reloc_gpu_flush(&eb->reloc_cache); if (err) goto put_rq; - GEM_BUG_ON(eb->reloc_cache.rq); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:36 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:36 +0100 Subject: [Intel-gfx] [PATCH 07/22] drm/i915/gt: Support creation of 'internal' rings In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-7-chris@chris-wilson.co.uk> To support legacy ring buffer scheduling, we want a virtual ringbuffer for each client. These rings are purely for holding the requests as they are being constructed on the CPU and never accessed by the GPU, so they should not be bound into the GGTT, and we can use plain old WB mapped pages. As they are not bound, we need to nerf a few assumptions that a rq->ring is in the GGTT. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 ++---- drivers/gpu/drm/i915/gt/intel_ring.c | 63 ++++++++++++++-------- drivers/gpu/drm/i915/gt/intel_ring.h | 12 ++++- drivers/gpu/drm/i915/gt/intel_ring_types.h | 2 + 5 files changed, 57 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index e4aece20bc80..fd71977c010a 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -127,7 +127,7 @@ int __intel_context_do_pin(struct intel_context *ce) goto err_active; CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", - i915_ggtt_offset(ce->ring->vma), + intel_ring_address(ce->ring), ce->ring->head, ce->ring->tail); smp_mb__before_atomic(); /* flush pin before it is visible */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e37490d459c2..4b36378af119 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1259,7 +1259,7 @@ static int print_ring(char *buf, int sz, struct i915_request *rq) len = scnprintf(buf, sz, "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", - i915_ggtt_offset(rq->ring->vma), + intel_ring_address(rq->ring), tl ? tl->hwsp_offset : 0, hwsp_seqno(rq), DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), @@ -1540,7 +1540,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, print_request(m, rq, "\t\tactive "); drm_printf(m, "\t\tring->start: 0x%08x\n", - i915_ggtt_offset(rq->ring->vma)); + intel_ring_address(rq->ring)); drm_printf(m, "\t\tring->head: 0x%08x\n", rq->ring->head); drm_printf(m, "\t\tring->tail: 0x%08x\n", @@ -1619,13 +1619,6 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) return total; } -static bool match_ring(struct i915_request *rq) -{ - u32 ring = ENGINE_READ(rq->engine, RING_START); - - return ring == i915_ggtt_offset(rq->ring->vma); -} - struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine) { @@ -1665,11 +1658,7 @@ intel_engine_find_active_request(struct intel_engine_cs *engine) continue; if (!i915_request_started(request)) - continue; - - /* More than one preemptible request may match! */ - if (!match_ring(request)) - continue; + break; active = request; break; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 8cda1b7e17ba..438637996ab5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -24,33 +24,42 @@ unsigned int intel_ring_update_space(struct intel_ring *ring) int intel_ring_pin(struct intel_ring *ring) { struct i915_vma *vma = ring->vma; - unsigned int flags; void *addr; int ret; if (atomic_fetch_inc(&ring->pin_count)) return 0; - /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ - flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); + if (!(ring->flags & INTEL_RING_CREATE_INTERNAL)) { + unsigned int pin; - if (vma->obj->stolen) - flags |= PIN_MAPPABLE; - else - flags |= PIN_HIGH; + /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ + pin |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); - ret = i915_ggtt_pin(vma, 0, flags); - if (unlikely(ret)) - goto err_unpin; + if (vma->obj->stolen) + pin |= PIN_MAPPABLE; + else + pin |= PIN_HIGH; - if (i915_vma_is_map_and_fenceable(vma)) - addr = (void __force *)i915_vma_pin_iomap(vma); - else - addr = i915_gem_object_pin_map(vma->obj, - i915_coherent_map_type(vma->vm->i915)); - if (IS_ERR(addr)) { - ret = PTR_ERR(addr); - goto err_ring; + ret = i915_ggtt_pin(vma, 0, pin); + if (unlikely(ret)) + goto err_unpin; + + if (i915_vma_is_map_and_fenceable(vma)) + addr = (void __force *)i915_vma_pin_iomap(vma); + else + addr = i915_gem_object_pin_map(vma->obj, + i915_coherent_map_type(vma->vm->i915)); + if (IS_ERR(addr)) { + ret = PTR_ERR(addr); + goto err_ring; + } + } else { + addr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); + if (IS_ERR(addr)) { + ret = PTR_ERR(addr); + goto err_ring; + } } i915_vma_make_unshrinkable(vma); @@ -91,10 +100,12 @@ void intel_ring_unpin(struct intel_ring *ring) i915_gem_object_unpin_map(vma->obj); i915_vma_make_purgeable(vma); - i915_vma_unpin(vma); + if (!(ring->flags & INTEL_RING_CREATE_INTERNAL)) + i915_vma_unpin(vma); } -static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) +static struct i915_vma * +create_ring_vma(struct i915_ggtt *ggtt, int size, unsigned int flags) { struct i915_address_space *vm = &ggtt->vm; struct drm_i915_private *i915 = vm->i915; @@ -102,7 +113,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct i915_vma *vma; obj = ERR_PTR(-ENODEV); - if (i915_ggtt_has_aperture(ggtt)) + if (!(flags & INTEL_RING_CREATE_INTERNAL) && + i915_ggtt_has_aperture(ggtt)) obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); @@ -128,12 +140,14 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) } struct intel_ring * -intel_engine_create_ring(struct intel_engine_cs *engine, int size) +intel_engine_create_ring(struct intel_engine_cs *engine, unsigned int size) { struct drm_i915_private *i915 = engine->i915; + unsigned int flags = size & GENMASK(11, 0); struct intel_ring *ring; struct i915_vma *vma; + size ^= flags; GEM_BUG_ON(!is_power_of_2(size)); GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); @@ -142,8 +156,10 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size) return ERR_PTR(-ENOMEM); kref_init(&ring->ref); + ring->size = size; ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(size); + ring->flags = flags; /* * Workaround an erratum on the i830 which causes a hang if @@ -156,11 +172,12 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size) intel_ring_update_space(ring); - vma = create_ring_vma(engine->gt->ggtt, size); + vma = create_ring_vma(engine->gt->ggtt, size, flags); if (IS_ERR(vma)) { kfree(ring); return ERR_CAST(vma); } + ring->vma = vma; return ring; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h index cc0ebca65167..d022fa209325 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.h +++ b/drivers/gpu/drm/i915/gt/intel_ring.h @@ -9,12 +9,14 @@ #include "i915_gem.h" /* GEM_BUG_ON */ #include "i915_request.h" +#include "i915_vma.h" #include "intel_ring_types.h" struct intel_engine_cs; struct intel_ring * -intel_engine_create_ring(struct intel_engine_cs *engine, int size); +intel_engine_create_ring(struct intel_engine_cs *engine, unsigned int size); +#define INTEL_RING_CREATE_INTERNAL BIT(0) u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords); int intel_ring_cacheline_align(struct i915_request *rq); @@ -137,4 +139,12 @@ __intel_ring_space(unsigned int head, unsigned int tail, unsigned int size) return (head - tail - CACHELINE_BYTES) & (size - 1); } +static inline u32 intel_ring_address(const struct intel_ring *ring) +{ + if (ring->flags & INTEL_RING_CREATE_INTERNAL) + return -1; + + return i915_ggtt_offset(ring->vma); +} + #endif /* INTEL_RING_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_types.h b/drivers/gpu/drm/i915/gt/intel_ring_types.h index 1a189ea00fd8..d927deafcb33 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_types.h +++ b/drivers/gpu/drm/i915/gt/intel_ring_types.h @@ -47,6 +47,8 @@ struct intel_ring { u32 size; u32 wrap; u32 effective_size; + + unsigned long flags; }; #endif /* INTEL_RING_TYPES_H */ -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 10:37:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 11:37:49 +0100 Subject: [Intel-gfx] [PATCH 20/22] dma-buf: Proxy fence, an unsignaled fence placeholder In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <20200604103751.18816-20-chris@chris-wilson.co.uk> Often we need to create a fence for a future event that has not yet been associated with a fence. We can store a proxy fence, a placeholder, in the timeline and replace it later when the real fence is known. Any listeners that attach to the proxy fence will automatically be signaled when the real fence completes, and any future listeners will instead be attach directly to the real fence avoiding any indirection overhead. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com> --- drivers/dma-buf/Makefile | 13 +- drivers/dma-buf/dma-fence-private.h | 20 + drivers/dma-buf/dma-fence-proxy.c | 306 +++++++++++ drivers/dma-buf/dma-fence.c | 4 +- drivers/dma-buf/selftests.h | 1 + drivers/dma-buf/st-dma-fence-proxy.c | 752 +++++++++++++++++++++++++++ include/linux/dma-fence-proxy.h | 38 ++ 7 files changed, 1130 insertions(+), 4 deletions(-) create mode 100644 drivers/dma-buf/dma-fence-private.h create mode 100644 drivers/dma-buf/dma-fence-proxy.c create mode 100644 drivers/dma-buf/st-dma-fence-proxy.c create mode 100644 include/linux/dma-fence-proxy.h diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile index 995e05f609ff..afaf6dadd9a3 100644 --- a/drivers/dma-buf/Makefile +++ b/drivers/dma-buf/Makefile @@ -1,6 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \ - dma-resv.o seqno-fence.o +obj-y := \ + dma-buf.o \ + dma-fence.o \ + dma-fence-array.o \ + dma-fence-chain.o \ + dma-fence-proxy.o \ + dma-resv.o \ + seqno-fence.o obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o obj-$(CONFIG_DMABUF_HEAPS) += heaps/ obj-$(CONFIG_SYNC_FILE) += sync_file.o @@ -10,6 +16,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o dmabuf_selftests-y := \ selftest.o \ st-dma-fence.o \ - st-dma-fence-chain.o + st-dma-fence-chain.o \ + st-dma-fence-proxy.o obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o diff --git a/drivers/dma-buf/dma-fence-private.h b/drivers/dma-buf/dma-fence-private.h new file mode 100644 index 000000000000..6924d28af0fa --- /dev/null +++ b/drivers/dma-buf/dma-fence-private.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf and to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark <robdclark at gmail.com> + * Maarten Lankhorst <maarten.lankhorst at canonical.com> + */ + +#ifndef DMA_FENCE_PRIVATE_H +#define DMA_FENCE_PRIAVTE_H + +struct dma_fence; + +bool __dma_fence_enable_signaling(struct dma_fence *fence); + +#endif /* DMA_FENCE_PRIAVTE_H */ diff --git a/drivers/dma-buf/dma-fence-proxy.c b/drivers/dma-buf/dma-fence-proxy.c new file mode 100644 index 000000000000..42674e92b0f9 --- /dev/null +++ b/drivers/dma-buf/dma-fence-proxy.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dma-fence-proxy: placeholder unsignaled fence + * + * Copyright (C) 2017-2019 Intel Corporation + */ + +#include <linux/dma-fence.h> +#include <linux/dma-fence-proxy.h> +#include <linux/export.h> +#include <linux/irq_work.h> +#include <linux/slab.h> + +#include "dma-fence-private.h" + +struct dma_fence_proxy { + struct dma_fence base; + + struct dma_fence *real; + struct dma_fence_cb cb; + struct irq_work work; + + wait_queue_head_t wq; +}; + +#ifdef CONFIG_DEBUG_LOCK_ALLOC +#define same_lockclass(A, B) (A)->dep_map.key == (B)->dep_map.key +#else +#define same_lockclass(A, B) 0 +#endif + +static const char *proxy_get_driver_name(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + + return real ? real->ops->get_driver_name(real) : "proxy"; +} + +static const char *proxy_get_timeline_name(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + + return real ? real->ops->get_timeline_name(real) : "unset"; +} + +static void proxy_irq_work(struct irq_work *work) +{ + struct dma_fence_proxy *p = container_of(work, typeof(*p), work); + + dma_fence_signal(&p->base); + dma_fence_put(&p->base); +} + +static void proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb) +{ + struct dma_fence_proxy *p = container_of(cb, typeof(*p), cb); + + /* Signaled before enabling signalling callbacks? */ + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &p->base.flags)) { + dma_fence_put(&p->base); + return; + } + + if (real->error) + dma_fence_set_error(&p->base, real->error); + + /* Lower the height of the proxy chain -> single stack frame */ + irq_work_queue(&p->work); +} + +static bool proxy_enable_signaling(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + bool ret = true; + + if (real) { + spin_lock_nested(real->lock, + same_lockclass(&p->wq.lock, real->lock)); + ret = __dma_fence_enable_signaling(real); + if (!ret && real->error) + dma_fence_set_error(&p->base, real->error); + spin_unlock(real->lock); + } + + return ret; +} + +static void proxy_release(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + + dma_fence_put(p->real); + dma_fence_free(&p->base); +} + +const struct dma_fence_ops dma_fence_proxy_ops = { + .get_driver_name = proxy_get_driver_name, + .get_timeline_name = proxy_get_timeline_name, + .enable_signaling = proxy_enable_signaling, + .wait = dma_fence_default_wait, + .release = proxy_release, +}; +EXPORT_SYMBOL_GPL(dma_fence_proxy_ops); + +/** + * __dma_fence_create_proxy - Create an unset dma-fence + * @context: context number to use for proxy fence + * @seqno: sequence number to use for proxy fence + * + * __dma_fence_create_proxy() creates a new dma_fence stub that is initially + * unsignaled and may later be replaced with a real fence. Any listeners + * to the proxy fence will be signaled when the target fence signals its + * completion. + */ +struct dma_fence *__dma_fence_create_proxy(u64 context, u64 seqno) +{ + struct dma_fence_proxy *p; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) + return NULL; + + init_waitqueue_head(&p->wq); + dma_fence_init(&p->base, &dma_fence_proxy_ops, &p->wq.lock, + context, seqno); + init_irq_work(&p->work, proxy_irq_work); + + return &p->base; +} +EXPORT_SYMBOL(__dma_fence_create_proxy); + +/** + * dma_fence_create_proxy - Create an unset dma-fence + * + * Wraps __dma_fence_create_proxy() to create a new proxy fence with the + * next available (unique) context id. + */ +struct dma_fence *dma_fence_create_proxy(void) +{ + return __dma_fence_create_proxy(dma_fence_context_alloc(1), 0); +} +EXPORT_SYMBOL(dma_fence_create_proxy); + +static void __wake_up_listeners(struct dma_fence_proxy *p) +{ + struct wait_queue_entry *wait, *next; + + list_for_each_entry_safe(wait, next, &p->wq.head, entry) { + INIT_LIST_HEAD(&wait->entry); + wait->func(wait, TASK_NORMAL, 0, p->real); + } +} + +static void set_proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb) +{ + cb->func = proxy_callback; + list_add_tail(&cb->node, &real->cb_list); +} + +static void proxy_assign(struct dma_fence *fence, struct dma_fence *real) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + unsigned long flags; + + if (WARN_ON(fence == real)) + return; + + if (WARN_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) + return; + + if (WARN_ON(p->real)) + return; + + spin_lock_irqsave(&p->wq.lock, flags); + + if (unlikely(!real)) { + dma_fence_signal_locked(&p->base); + goto unlock; + } + + p->real = dma_fence_get(real); + + dma_fence_get(&p->base); + spin_lock_nested(real->lock, same_lockclass(&p->wq.lock, real->lock)); + if (dma_fence_is_signaled_locked(real)) + proxy_callback(real, &p->cb); + else if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &p->base.flags) && + !__dma_fence_enable_signaling(real)) + proxy_callback(real, &p->cb); + else + set_proxy_callback(real, &p->cb); + spin_unlock(real->lock); + +unlock: + __wake_up_listeners(p); + spin_unlock_irqrestore(&p->wq.lock, flags); +} + +/** + * dma_fence_replace_proxy - Replace the proxy fence with the real target + * @slot: pointer to location of fence to update + * @fence: the new fence to store in @slot + * + * Once the real dma_fence is known, we can replace the proxy fence holder + * with a pointer to the real dma fence. Future listeners will attach to + * the real fence, avoiding any indirection overhead. Previous listeners + * will remain attached to the proxy fence, and be signaled in turn when + * the target fence completes. + */ +struct dma_fence * +dma_fence_replace_proxy(struct dma_fence __rcu **slot, struct dma_fence *fence) +{ + struct dma_fence *old; + + if (fence) + dma_fence_get(fence); + + old = rcu_replace_pointer(*slot, fence, true); + if (old && dma_fence_is_proxy(old)) + proxy_assign(old, fence); + + return old; +} +EXPORT_SYMBOL(dma_fence_replace_proxy); + +/** + * dma_fence_proxy_set_real - Set the target of a proxy fence + * @fence: the proxy fence + * @real: the target fence. + * + */ +void dma_fence_proxy_set_real(struct dma_fence *fence, struct dma_fence *real) +{ + if (dma_fence_is_proxy(fence)) + proxy_assign(fence, real); +} +EXPORT_SYMBOL(dma_fence_proxy_set_real); + +/** + * dma_fence_proxy_get_real - Query the target of a proxy fence + * @fence: the proxy fence + * + * Unpeel the proxy fence to see if it has been replaced with a real fence. + */ +struct dma_fence *dma_fence_proxy_get_real(struct dma_fence *fence) +{ + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + + if (p->real) + fence = p->real; + } + + return fence; +} +EXPORT_SYMBOL(dma_fence_proxy_get_real); + +void dma_fence_add_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait) +{ + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + unsigned long flags; + + spin_lock_irqsave(&p->wq.lock, flags); + if (!p->real) { + list_add_tail(&wait->entry, &p->wq.head); + wait = NULL; + } + fence = p->real; + spin_unlock_irqrestore(&p->wq.lock, flags); + } + + if (wait) { + INIT_LIST_HEAD(&wait->entry); + wait->func(wait, TASK_NORMAL, 0, fence); + } +} +EXPORT_SYMBOL(dma_fence_add_proxy_listener); + +bool dma_fence_remove_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait) +{ + bool ret = false; + + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + unsigned long flags; + + spin_lock_irqsave(&p->wq.lock, flags); + if (!list_empty(&wait->entry)) { + list_del_init(&wait->entry); + ret = true; + } + spin_unlock_irqrestore(&p->wq.lock, flags); + } + + return ret; +} +EXPORT_SYMBOL(dma_fence_remove_proxy_listener); diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 656e9ac2d028..329bd033059f 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -19,6 +19,8 @@ #define CREATE_TRACE_POINTS #include <trace/events/dma_fence.h> +#include "dma-fence-private.h" + EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit); EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal); EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled); @@ -275,7 +277,7 @@ void dma_fence_free(struct dma_fence *fence) } EXPORT_SYMBOL(dma_fence_free); -static bool __dma_fence_enable_signaling(struct dma_fence *fence) +bool __dma_fence_enable_signaling(struct dma_fence *fence) { bool was_set; diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h index 55918ef9adab..616eca70e2d8 100644 --- a/drivers/dma-buf/selftests.h +++ b/drivers/dma-buf/selftests.h @@ -12,3 +12,4 @@ selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */ selftest(dma_fence, dma_fence) selftest(dma_fence_chain, dma_fence_chain) +selftest(dma_fence_proxy, dma_fence_proxy) diff --git a/drivers/dma-buf/st-dma-fence-proxy.c b/drivers/dma-buf/st-dma-fence-proxy.c new file mode 100644 index 000000000000..c3f210bc4e60 --- /dev/null +++ b/drivers/dma-buf/st-dma-fence-proxy.c @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2019 Intel Corporation + */ + +#include <linux/delay.h> +#include <linux/dma-fence.h> +#include <linux/dma-fence-proxy.h> +#include <linux/kernel.h> +#include <linux/sched/signal.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#include "selftest.h" + +static struct kmem_cache *slab_fences; + +static struct mock_fence { + struct dma_fence base; + spinlock_t lock; +} *to_mock_fence(struct dma_fence *f) { + return container_of(f, struct mock_fence, base); +} + +static const char *mock_name(struct dma_fence *f) +{ + return "mock"; +} + +static void mock_fence_release(struct dma_fence *f) +{ + kmem_cache_free(slab_fences, to_mock_fence(f)); +} + +static const struct dma_fence_ops mock_ops = { + .get_driver_name = mock_name, + .get_timeline_name = mock_name, + .release = mock_fence_release, +}; + +static struct dma_fence *mock_fence(void) +{ + struct mock_fence *f; + + f = kmem_cache_alloc(slab_fences, GFP_KERNEL); + if (!f) + return NULL; + + spin_lock_init(&f->lock); + dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0); + + return &f->base; +} + +static int sanitycheck(void *arg) +{ + struct dma_fence *f; + + f = dma_fence_create_proxy(); + if (!f) + return -ENOMEM; + + dma_fence_signal(f); + dma_fence_put(f); + + return 0; +} + +struct fences { + struct dma_fence *real; + struct dma_fence *proxy; + struct dma_fence __rcu *slot; +}; + +static int create_fences(struct fences *f, bool attach) +{ + f->proxy = dma_fence_create_proxy(); + if (!f->proxy) + return -ENOMEM; + + RCU_INIT_POINTER(f->slot, f->proxy); + + f->real = mock_fence(); + if (!f->real) { + dma_fence_put(f->proxy); + return -ENOMEM; + } + + if (attach) + dma_fence_replace_proxy(&f->slot, f->real); + + return 0; +} + +static void free_fences(struct fences *f) +{ + dma_fence_put(dma_fence_replace_proxy(&f->slot, NULL)); + + dma_fence_signal(f->real); + dma_fence_put(f->real); + + dma_fence_signal(f->proxy); + dma_fence_put(f->proxy); +} + +static int wrap_target(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_proxy_get_real(f.proxy) != f.proxy) { + pr_err("Unwrapped proxy fenced reported a target fence!\n"); + goto err_free; + } + + dma_fence_proxy_set_real(f.proxy, f.real); + rcu_assign_pointer(f.slot, dma_fence_get(f.real)); /* free_fences() */ + + if (dma_fence_proxy_get_real(f.proxy) != f.real) { + pr_err("Wrapped proxy fenced did not report the target fence!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_proxy(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_proxy_get_real(f.proxy) != f.real) { + pr_err("Wrapped proxy fenced did not report the target fence!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_signaling(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_is_signaled(f.proxy)) { + pr_err("Fence unexpectedly signaled on creation\n"); + goto err_free; + } + + if (dma_fence_signal(f.real)) { + pr_err("Fence reported being already signaled\n"); + goto err_free; + } + + if (!dma_fence_is_signaled(f.proxy)) { + pr_err("Fence not reporting signaled\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_signaling_recurse(void *arg) +{ + struct fences f; + struct dma_fence *chain; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + chain = dma_fence_create_proxy(); + if (!chain) { + err = -ENOMEM; + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, chain); + dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real)); + dma_fence_put(chain); + + /* f.real <- chain <- f.proxy */ + + if (dma_fence_is_signaled(f.proxy)) { + pr_err("Fence unexpectedly signaled on creation\n"); + goto err_free; + } + + if (dma_fence_signal(f.real)) { + pr_err("Fence reported being already signaled\n"); + goto err_free; + } + + if (!dma_fence_is_signaled(f.proxy)) { + pr_err("Fence not reporting signaled\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +struct simple_cb { + struct dma_fence_cb cb; + bool seen; +}; + +static void simple_callback(struct dma_fence *f, struct dma_fence_cb *cb) +{ + /* Ensure the callback marker is visible, no excuses for missing it! */ + smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true); +} + +static int wrap_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_add_callback_recurse(void *arg) +{ + struct simple_cb cb = {}; + struct dma_fence *chain; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + chain = dma_fence_create_proxy(); + if (!chain) { + err = -ENOMEM; + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, chain); + dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real)); + dma_fence_put(chain); + + /* f.real <- chain <- f.proxy */ + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_late_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + dma_fence_signal(f.real); + + if (!dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Added callback, but fence was already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (cb.seen) { + pr_err("Callback called after failed attachment!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback_late(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_signal(f.real); + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback_early(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_rm_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + if (!dma_fence_remove_callback(f.proxy, &cb.cb)) { + pr_err("Failed to remove callback!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (cb.seen) { + pr_err("Callback still signaled after removal!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_late_rm_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + if (dma_fence_remove_callback(f.proxy, &cb.cb)) { + pr_err("Callback removal succeed after being executed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_status(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_get_status(f.proxy)) { + pr_err("Fence unexpectedly has signaled status on creation\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!dma_fence_get_status(f.proxy)) { + pr_err("Fence not reporting signaled status\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_error(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + dma_fence_set_error(f.real, -EIO); + + if (dma_fence_get_status(f.proxy)) { + pr_err("Fence unexpectedly has error status before signal\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (dma_fence_get_status(f.proxy) != -EIO) { + pr_err("Fence not reporting error status, got %d\n", + dma_fence_get_status(f.proxy)); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_wait(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_wait_timeout(f.proxy, false, 0) != 0) { + pr_err("Wait reported complete before being signaled\n"); + goto err_free; + } + + dma_fence_signal(f.real); + + if (dma_fence_wait_timeout(f.proxy, false, 0) == 0) { + pr_err("Wait reported incomplete after being signaled\n"); + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +struct wait_timer { + struct timer_list timer; + struct fences f; +}; + +static void wait_timer(struct timer_list *timer) +{ + struct wait_timer *wt = from_timer(wt, timer, timer); + + dma_fence_signal(wt->f.real); +} + +static int wrap_wait_timeout(void *arg) +{ + struct wait_timer wt; + int err = -EINVAL; + + if (create_fences(&wt.f, true)) + return -ENOMEM; + + timer_setup_on_stack(&wt.timer, wait_timer, 0); + + if (dma_fence_wait_timeout(wt.f.proxy, false, 1) != 0) { + pr_err("Wait reported complete before being signaled\n"); + goto err_free; + } + + mod_timer(&wt.timer, jiffies + 1); + + if (dma_fence_wait_timeout(wt.f.proxy, false, 2) != 0) { + if (timer_pending(&wt.timer)) { + pr_notice("Timer did not fire within the jiffie!\n"); + err = 0; /* not our fault! */ + } else { + pr_err("Wait reported incomplete after timeout\n"); + } + goto err_free; + } + + err = 0; +err_free: + del_timer_sync(&wt.timer); + destroy_timer_on_stack(&wt.timer); + dma_fence_signal(wt.f.real); + free_fences(&wt.f); + return err; +} + +struct proxy_wait { + struct wait_queue_entry base; + struct dma_fence *fence; + bool seen; +}; + +static int proxy_wait_cb(struct wait_queue_entry *entry, + unsigned int mode, int flags, void *key) +{ + struct proxy_wait *p = container_of(entry, typeof(*p), base); + + p->fence = key; + p->seen = true; + + return 0; +} + +static int wrap_listen_early(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_add_proxy_listener(f.proxy, &wait.base); + + if (!wait.seen) { + pr_err("Proxy listener was not called after replace!\n"); + err = -EINVAL; + goto err_free; + } + + if (wait.fence != f.real) { + pr_err("Proxy listener was not passed the real fence!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +static int wrap_listen_late(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_add_proxy_listener(f.proxy, &wait.base); + dma_fence_replace_proxy(&f.slot, f.real); + + if (!wait.seen) { + pr_err("Proxy listener was not called on replace!\n"); + err = -EINVAL; + goto err_free; + } + + if (wait.fence != f.real) { + pr_err("Proxy listener was not passed the real fence!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +static int wrap_listen_cancel(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_add_proxy_listener(f.proxy, &wait.base); + if (!dma_fence_remove_proxy_listener(f.proxy, &wait.base)) { + pr_err("Cancelling listener, already detached?\n"); + err = -EINVAL; + goto err_free; + } + dma_fence_replace_proxy(&f.slot, f.real); + + if (wait.seen) { + pr_err("Proxy listener was called after being removed!\n"); + err = -EINVAL; + goto err_free; + } + + if (dma_fence_remove_proxy_listener(f.proxy, &wait.base)) { + pr_err("Double listener cancellation!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +int dma_fence_proxy(void) +{ + static const struct subtest tests[] = { + SUBTEST(sanitycheck), + SUBTEST(wrap_target), + SUBTEST(wrap_proxy), + SUBTEST(wrap_signaling), + SUBTEST(wrap_signaling_recurse), + SUBTEST(wrap_add_callback), + SUBTEST(wrap_add_callback_recurse), + SUBTEST(wrap_late_add_callback), + SUBTEST(wrap_early_add_callback), + SUBTEST(wrap_early_add_callback_late), + SUBTEST(wrap_early_add_callback_early), + SUBTEST(wrap_rm_callback), + SUBTEST(wrap_late_rm_callback), + SUBTEST(wrap_status), + SUBTEST(wrap_error), + SUBTEST(wrap_wait), + SUBTEST(wrap_wait_timeout), + SUBTEST(wrap_listen_early), + SUBTEST(wrap_listen_late), + SUBTEST(wrap_listen_cancel), + }; + int ret; + + slab_fences = KMEM_CACHE(mock_fence, + SLAB_TYPESAFE_BY_RCU | + SLAB_HWCACHE_ALIGN); + if (!slab_fences) + return -ENOMEM; + + ret = subtests(tests, NULL); + + kmem_cache_destroy(slab_fences); + + return ret; +} diff --git a/include/linux/dma-fence-proxy.h b/include/linux/dma-fence-proxy.h new file mode 100644 index 000000000000..6a986b5bb009 --- /dev/null +++ b/include/linux/dma-fence-proxy.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * dma-fence-proxy: allows waiting upon unset and future fences + * + * Copyright (C) 2017 Intel Corporation + */ + +#ifndef __LINUX_DMA_FENCE_PROXY_H +#define __LINUX_DMA_FENCE_PROXY_H + +#include <linux/kernel.h> +#include <linux/dma-fence.h> + +struct wait_queue_entry; + +extern const struct dma_fence_ops dma_fence_proxy_ops; + +struct dma_fence *__dma_fence_create_proxy(u64 context, u64 seqno); +struct dma_fence *dma_fence_create_proxy(void); + +static inline bool dma_fence_is_proxy(struct dma_fence *fence) +{ + return fence->ops == &dma_fence_proxy_ops; +} + +void dma_fence_proxy_set_real(struct dma_fence *fence, struct dma_fence *real); +struct dma_fence *dma_fence_proxy_get_real(struct dma_fence *fence); + +struct dma_fence * +dma_fence_replace_proxy(struct dma_fence __rcu **slot, + struct dma_fence *fence); + +void dma_fence_add_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait); +bool dma_fence_remove_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait); + +#endif /* __LINUX_DMA_FENCE_PROXY_H */ -- 2.20.1 From Eugeniy.Paltsev at synopsys.com Thu Jun 4 10:38:31 2020 From: Eugeniy.Paltsev at synopsys.com (Eugeniy Paltsev) Date: Thu, 4 Jun 2020 10:38:31 +0000 Subject: [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny In-Reply-To: <20200604080507.GT20149@phenom.ffwll.local> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-54-daniel.vetter@ffwll.ch> <20200415094512.GA30444@ravnborg.org> <MWHPR12MB14532DA5713E3B579ABFE1F4A1DB0@MWHPR12MB1453.namprd12.prod.outlook.com> <CAKMK7uGDGgt8Cm_bFoyzeoP2CWyiUNdUwb7GL6Ohu3k0rP0p1w@mail.gmail.com> <20200428140842.GL3456981@phenom.ffwll.local> <CH2PR12MB3894B40C6D71435D3E759A34A1A20@CH2PR12MB3894.namprd12.prod.outlook.com> <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com>, <20200604080507.GT20149@phenom.ffwll.local> Message-ID: <CY4PR1201MB01363EB95985A2C64ADA6841DE890@CY4PR1201MB0136.namprd12.prod.outlook.com> Hi Daniel, I've already tested it (and found several issues), so please check my reply here: https://www.mail-archive.com/linux-snps-arc at lists.infradead.org/msg07403.html Not sure why you didn't receive my reply (probably the reason is because it was sent to your @ffwll.ch mail instead of @intel.com one). ________________________________________ From: Daniel Vetter <daniel at ffwll.ch> Sent: Thursday, June 4, 2020 11:05 To: Alexey Brodkin Cc: Intel Graphics Development; DRI Development; Daniel Vetter; Eugeniy Paltsev; Sam Ravnborg Subject: Re: [PATCH 53/59] drm/arc: Move to drm/tiny On Fri, May 08, 2020 at 08:07:41PM +0200, Daniel Vetter wrote: > On Fri, May 8, 2020 at 3:56 PM Alexey Brodkin > <Alexey.Brodkin at synopsys.com> wrote: > > > > Hi Daniel, > > > > > > Looking at this patch series, feels a bit like hand-rolling of bridge > > > > code, badly. We should get away from that. > > > > > > > > Once you have that I think the end result is tiny enough that it can > > > > stay, bridges intergrate quite well into simple display pipe drivers. > > > > > > > > > BTW should I pull that series in my tree and send you a pull-request > > > > > or that kind of change needs to go through another tree? > > > > > > > > > > Also I'd like to test the change we discuss here to make sure stuff > > > > > still works. Once we do that I'll send an update. Any hint on > > > > > when that change needs to be acked/nacked? > > > > > > > > Simplest is if this can all land through drm-misc, is arc not > > > > maintained in there? And there's plenty of time for testing, I'm just > > > > slowly crawling through the tree to get everything polished and > > > > cleaned up in this area. > > > > > > Any updates on testing this pile here? First patch landed now, and I've > > > started to push driver patches. So would be good to get this sorted out > > > too. > > > > Sorry we're in the middle of 2 long weekends so missed this one. > > I guess we'll be able to test it in a week or two from now. > > > > Is that OK? > > This aren't high-priority, so totally ok. As long as you don't land a > driver rewrite and I have to rebase everything :-) Ping for a bit of testing on this stuff ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation https://urldefense.com/v3/__http://blog.ffwll.ch__;!!A4F2R9G_pg!Ncpf9M5g5wUEicELHfzz8syA0c0KogYc2E0tdnXGHGmUwGbROv-vwMDISCh7u6w58Dgs-ws$ From matthew.auld at intel.com Thu Jun 4 10:55:33 2020 From: matthew.auld at intel.com (Matthew Auld) Date: Thu, 4 Jun 2020 11:55:33 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise all copy engines with the blt routines In-Reply-To: <20200604102140.8845-1-chris@chris-wilson.co.uk> References: <20200604102140.8845-1-chris@chris-wilson.co.uk> Message-ID: <c86b06e8-6402-ef90-03d9-03642aa9fb52@intel.com> On 04/06/2020 11:21, Chris Wilson wrote: > Just to remove an obnoxious HAS_ENGINES(), and in the process make the > code agnostic to the available of any particular engine by making it > exercise any and all such engines declared on the system. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > Cc: Matthew Auld <matthew.auld at intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>Reviewed-by: Matthew Auld <matthew.auld at intel.com> From patchwork at emeril.freedesktop.org Thu Jun 4 11:08:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 11:08:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/selftests=3A_Exercise_all_copy_engines_with_the_bl?= =?utf-8?q?t_routines?= In-Reply-To: <20200604102140.8845-1-chris@chris-wilson.co.uk> References: <20200604102140.8845-1-chris@chris-wilson.co.uk> Message-ID: <159126889246.14554.292823011637408147@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise all copy engines with the blt routines URL : https://patchwork.freedesktop.org/series/77994/ State : warning == Summary == $ dim checkpatch origin/drm-tip dbd180308199 drm/i915/selftests: Exercise all copy engines with the blt routines -:288: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects? #288: FILE: drivers/gpu/drm/i915/i915_drv.h:1267: +#define for_each_uabi_class_engine(engine__, class__, i915__) \ + for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ + (engine__) && (engine__)->uabi_class == (class__); \ + (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) -:288: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'class__' - possible side-effects? #288: FILE: drivers/gpu/drm/i915/i915_drv.h:1267: +#define for_each_uabi_class_engine(engine__, class__, i915__) \ + for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ + (engine__) && (engine__)->uabi_class == (class__); \ + (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) total: 0 errors, 0 warnings, 2 checks, 240 lines checked From daniel at ffwll.ch Thu Jun 4 11:19:36 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Thu, 4 Jun 2020 13:19:36 +0200 Subject: [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny In-Reply-To: <CY4PR1201MB01363EB95985A2C64ADA6841DE890@CY4PR1201MB0136.namprd12.prod.outlook.com> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-54-daniel.vetter@ffwll.ch> <20200415094512.GA30444@ravnborg.org> <MWHPR12MB14532DA5713E3B579ABFE1F4A1DB0@MWHPR12MB1453.namprd12.prod.outlook.com> <CAKMK7uGDGgt8Cm_bFoyzeoP2CWyiUNdUwb7GL6Ohu3k0rP0p1w@mail.gmail.com> <20200428140842.GL3456981@phenom.ffwll.local> <CH2PR12MB3894B40C6D71435D3E759A34A1A20@CH2PR12MB3894.namprd12.prod.outlook.com> <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com> <20200604080507.GT20149@phenom.ffwll.local> <CY4PR1201MB01363EB95985A2C64ADA6841DE890@CY4PR1201MB0136.namprd12.prod.outlook.com> Message-ID: <CAKMK7uFLvV3=uhfnf=MreKBM==-gzXqx3NrV8KDA2D5sTAn2SQ@mail.gmail.com> Hi Eugeniy, Apologies, somehow I missed your mail. I looked at the code again, and I think I fumbled something. Does the below diff help to prevent the issues? Thanks, Daniel diff --git a/drivers/gpu/drm/tiny/arcpgu.c b/drivers/gpu/drm/tiny/arcpgu.c index 857812f25bec..33d812a5ad7f 100644 --- a/drivers/gpu/drm/tiny/arcpgu.c +++ b/drivers/gpu/drm/tiny/arcpgu.c @@ -228,6 +228,9 @@ static void arc_pgu_update(struct drm_simple_display_pipe *pipe, struct arcpgu_drm_private *arcpgu; struct drm_gem_cma_object *gem; + if (!pipe->plane.state->fb) + return; + arcpgu = pipe_to_arcpgu_priv(pipe); gem = drm_fb_cma_get_gem_obj(pipe->plane.state->fb, 0); arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr); -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Thu Jun 4 11:25:05 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 11:25:05 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/24=5D_Revert_=22drm/i915/gem=3A_Drop_re?= =?utf-8?q?location_slowpath=22=2E?= In-Reply-To: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> Message-ID: <159126990575.14555.9682902816970582597@emeril.freedesktop.org> == Series Details == Series: series starting with [01/24] Revert "drm/i915/gem: Drop relocation slowpath". URL : https://patchwork.freedesktop.org/series/77960/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17854_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17854_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17854_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17854_full: ### IGT changes ### #### Possible regressions #### * igt at gem_close@many-handles-one-vma: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at gem_close@many-handles-one-vma.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk7/igt at gem_close@many-handles-one-vma.html - shard-apl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl8/igt at gem_close@many-handles-one-vma.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl2/igt at gem_close@many-handles-one-vma.html - shard-skl: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl10/igt at gem_close@many-handles-one-vma.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl10/igt at gem_close@many-handles-one-vma.html - shard-tglb: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at gem_close@many-handles-one-vma.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb1/igt at gem_close@many-handles-one-vma.html - shard-kbl: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at gem_close@many-handles-one-vma.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl4/igt at gem_close@many-handles-one-vma.html - shard-iclb: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt at gem_close@many-handles-one-vma.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb4/igt at gem_close@many-handles-one-vma.html * igt at i915_module_load@reload-no-display: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb8/igt at i915_module_load@reload-no-display.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb6/igt at i915_module_load@reload-no-display.html - shard-apl: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at i915_module_load@reload-no-display.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at i915_module_load@reload-no-display.html - shard-tglb: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb6/igt at i915_module_load@reload-no-display.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb3/igt at i915_module_load@reload-no-display.html - shard-skl: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl6/igt at i915_module_load@reload-no-display.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl10/igt at i915_module_load@reload-no-display.html - shard-kbl: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at i915_module_load@reload-no-display.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl2/igt at i915_module_load@reload-no-display.html * igt at i915_selftest@live at gem_contexts: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at i915_selftest@live at gem_contexts.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl4/igt at i915_selftest@live at gem_contexts.html * igt at i915_selftest@mock: - shard-glk: NOTRUN -> [FAIL][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk8/igt at i915_selftest@mock.html - shard-iclb: NOTRUN -> [FAIL][26] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb7/igt at i915_selftest@mock.html - shard-kbl: NOTRUN -> [FAIL][27] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl7/igt at i915_selftest@mock.html - shard-tglb: NOTRUN -> [FAIL][28] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb2/igt at i915_selftest@mock.html - shard-skl: NOTRUN -> [FAIL][29] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl4/igt at i915_selftest@mock.html - shard-apl: NOTRUN -> [FAIL][30] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl1/igt at i915_selftest@mock.html * igt at runner@aborted: - shard-iclb: NOTRUN -> ([FAIL][31], [FAIL][32], [FAIL][33]) ([i915#1580]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb4/igt at runner@aborted.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb6/igt at runner@aborted.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb7/igt at runner@aborted.html - shard-apl: NOTRUN -> ([FAIL][34], [FAIL][35], [FAIL][36]) ([i915#1423] / [i915#529]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl1/igt at runner@aborted.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl2/igt at runner@aborted.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at runner@aborted.html - shard-tglb: NOTRUN -> ([FAIL][37], [FAIL][38], [FAIL][39]) ([i915#1233] / [i915#1764] / [i915#529]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb2/igt at runner@aborted.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb1/igt at runner@aborted.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb3/igt at runner@aborted.html - shard-snb: NOTRUN -> ([FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44]) ([i915#1821]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb4/igt at runner@aborted.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb6/igt at runner@aborted.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb5/igt at runner@aborted.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb4/igt at runner@aborted.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb4/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_reloc@basic-parallel}: - shard-snb: [PASS][45] -> [DMESG-WARN][46] +3 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb6/igt at gem_exec_reloc@basic-parallel.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb4/igt at gem_exec_reloc@basic-parallel.html * {igt at i915_selftest@live at gem_execbuf}: - shard-kbl: [PASS][47] -> [INCOMPLETE][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at i915_selftest@live at gem_execbuf.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl4/igt at i915_selftest@live at gem_execbuf.html - shard-skl: [PASS][49] -> [INCOMPLETE][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl10/igt at i915_selftest@live at gem_execbuf.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl10/igt at i915_selftest@live at gem_execbuf.html - shard-apl: [PASS][51] -> [INCOMPLETE][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl8/igt at i915_selftest@live at gem_execbuf.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl2/igt at i915_selftest@live at gem_execbuf.html - shard-iclb: [PASS][53] -> [INCOMPLETE][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt at i915_selftest@live at gem_execbuf.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb4/igt at i915_selftest@live at gem_execbuf.html - shard-tglb: [PASS][55] -> [INCOMPLETE][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at i915_selftest@live at gem_execbuf.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb1/igt at i915_selftest@live at gem_execbuf.html Known issues ------------ Here are the changes found in Patchwork_17854_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload-no-display: - shard-snb: [PASS][57] -> [INCOMPLETE][58] ([i915#82]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb1/igt at i915_module_load@reload-no-display.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb5/igt at i915_module_load@reload-no-display.html - shard-glk: [PASS][59] -> [INCOMPLETE][60] ([i915#58] / [k.org#198133]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at i915_module_load@reload-no-display.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk1/igt at i915_module_load@reload-no-display.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at i915_suspend@forcewake.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl3/igt at i915_suspend@forcewake.html * igt at kms_available_modes_crc@available_mode_test_crc: - shard-kbl: [PASS][63] -> [DMESG-WARN][64] ([i915#93] / [i915#95]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at kms_available_modes_crc@available_mode_test_crc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl2/igt at kms_available_modes_crc@available_mode_test_crc.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][65] -> [DMESG-FAIL][66] ([i915#118] / [i915#95]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk1/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][67] -> [DMESG-WARN][68] ([i915#1982]) +10 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at kms_color@pipe-c-ctm-0-25.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl3/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-c-cursor-size-change: - shard-skl: [PASS][69] -> [FAIL][70] ([i915#54]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-size-change.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][71] -> [INCOMPLETE][72] ([i915#300]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@cursora-vs-flipb-atomic-transitions: - shard-glk: [PASS][73] -> [DMESG-WARN][74] ([i915#118] / [i915#95]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk1/igt at kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk8/igt at kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [PASS][75] -> [DMESG-FAIL][76] ([i915#1925] / [i915#1926]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled: - shard-apl: [PASS][77] -> [DMESG-WARN][78] ([i915#95]) +11 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl3/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][79] -> [FAIL][80] ([i915#1188]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: - shard-skl: [PASS][81] -> [FAIL][82] ([i915#53]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl4/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-glk: [PASS][83] -> [DMESG-WARN][84] ([i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][85] -> [DMESG-WARN][86] ([i915#180]) +2 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][87] -> [FAIL][88] ([fdo#108145] / [i915#265]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_plane_cursor@pipe-a-primary-size-256: - shard-snb: [PASS][89] -> [SKIP][90] ([fdo#109271]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb1/igt at kms_plane_cursor@pipe-a-primary-size-256.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb2/igt at kms_plane_cursor@pipe-a-primary-size-256.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][91] -> [SKIP][92] ([fdo#109441]) +2 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb1/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_setmode@basic: - shard-apl: [PASS][93] -> [FAIL][94] ([i915#31]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at kms_setmode@basic.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at vcs0}: - shard-kbl: [INCOMPLETE][95] ([i915#1780]) -> [PASS][96] [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][97] ([i915#1930]) -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk1/igt at gem_exec_reloc@basic-concurrent0.html - shard-apl: [FAIL][99] ([i915#1930]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at gem_exec_reloc@basic-concurrent0.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [FAIL][101] ([i915#1930]) -> [PASS][102] +1 similar issue [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html - shard-iclb: [FAIL][103] ([i915#1930]) -> [PASS][104] +1 similar issue [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb5/igt at gem_exec_reloc@basic-concurrent16.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb3/igt at gem_exec_reloc@basic-concurrent16.html - shard-skl: [FAIL][105] ([i915#1930]) -> [PASS][106] +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at gem_exec_reloc@basic-concurrent16.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl6/igt at gem_exec_reloc@basic-concurrent16.html - shard-kbl: [FAIL][107] ([i915#1930]) -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at gem_exec_reloc@basic-concurrent16.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl3/igt at gem_exec_reloc@basic-concurrent16.html - shard-tglb: [FAIL][109] ([i915#1930]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb5/igt at gem_exec_reloc@basic-concurrent16.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb3/igt at gem_exec_reloc@basic-concurrent16.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][111] ([i915#82]) -> [PASS][112] [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [DMESG-WARN][113] ([i915#118] / [i915#95]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk7/igt at gem_exec_whisper@basic-contexts-forked-all.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk7/igt at gem_exec_whisper@basic-contexts-forked-all.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][115] ([i915#180]) -> [PASS][116] +2 similar issues [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl2/igt at gem_workarounds@suspend-resume-context.html * igt at i915_suspend@sysfs-reader: - shard-apl: [TIMEOUT][117] ([i915#1635]) -> [PASS][118] +3 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at i915_suspend@sysfs-reader.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@y-tiled-8bpp-rotate-0: - shard-apl: [DMESG-WARN][119] ([i915#1982]) -> [PASS][120] +1 similar issue [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-skl: [DMESG-WARN][121] ([i915#1982]) -> [PASS][122] +9 similar issues [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][123] ([i915#46]) -> [PASS][124] [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][125] ([i915#93] / [i915#95]) -> [PASS][126] [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][127] ([i915#69]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][129] ([i915#95]) -> [PASS][130] +10 similar issues [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl3/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][131] ([fdo#108145] / [i915#265]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][133] ([fdo#109441]) -> [PASS][134] +1 similar issue [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb7/igt at kms_psr@psr2_cursor_render.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][135] ([i915#180]) -> [PASS][136] +3 similar issues [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][137] ([i915#1542]) -> [PASS][138] [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-tglb6/igt at perf@blocking-parameterized.html * {igt at perf_pmu@module-unload}: - shard-iclb: [DMESG-WARN][139] ([i915#1982]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt at perf_pmu@module-unload.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-iclb1/igt at perf_pmu@module-unload.html * igt at perf_pmu@rc6-runtime-pm: - shard-glk: [TIMEOUT][141] ([i915#1958]) -> [PASS][142] +4 similar issues [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at perf_pmu@rc6-runtime-pm.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk2/igt at perf_pmu@rc6-runtime-pm.html #### Warnings #### * igt at gem_ctx_bad_destroy@invalid-pad: - shard-apl: [TIMEOUT][143] ([i915#1635]) -> [DMESG-WARN][144] ([i915#95]) [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at gem_ctx_bad_destroy@invalid-pad.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at gem_ctx_bad_destroy@invalid-pad.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][145] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][146] ([fdo#110321] / [i915#95]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][147] ([i915#1319]) -> [TIMEOUT][148] ([i915#1319] / [i915#1635]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][149] ([i915#1319] / [i915#1635]) -> [FAIL][150] ([fdo#110321]) [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@lic.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl1/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [FAIL][151] ([fdo#110321]) -> [TIMEOUT][152] ([i915#1319] / [i915#1635]) [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [DMESG-FAIL][153] ([i915#49] / [i915#95]) -> [FAIL][154] ([i915#49]) [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_vblank@pipe-d-query-idle-hang: - shard-apl: [TIMEOUT][155] ([i915#1635] / [i915#1640]) -> [SKIP][156] ([fdo#109271]) [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl4/igt at kms_vblank@pipe-d-query-idle-hang.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-apl7/igt at kms_vblank@pipe-d-query-idle-hang.html - shard-glk: [TIMEOUT][157] ([i915#1640] / [i915#1958]) -> [SKIP][158] ([fdo#109271]) [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at kms_vblank@pipe-d-query-idle-hang.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk2/igt at kms_vblank@pipe-d-query-idle-hang.html * igt at runner@aborted: - shard-kbl: [FAIL][159] ([i915#1436]) -> ([FAIL][160], [FAIL][161], [FAIL][162]) ([i915#1423] / [i915#1436] / [i915#1784] / [i915#656]) [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at runner@aborted.html [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl7/igt at runner@aborted.html [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl4/igt at runner@aborted.html [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-kbl2/igt at runner@aborted.html - shard-glk: [FAIL][163] ([k.org#202321]) -> ([FAIL][164], [FAIL][165], [FAIL][166]) ([i915#1423] / [k.org#202321]) [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at runner@aborted.html [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk7/igt at runner@aborted.html [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk8/igt at runner@aborted.html [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/shard-glk1/igt at runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1423]: https://gitlab.freedesktop.org/drm/intel/issues/1423 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.fre == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17854/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 11:36:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 11:36:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/22=5D_drm/i915/gem=3A_Mark_the_b?= =?utf-8?q?uffer_pool_as_active_for_the_cmdparser?= In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <159127058804.14555.941712483607278305@emeril.freedesktop.org> == Series Details == Series: series starting with [01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser URL : https://patchwork.freedesktop.org/series/77996/ State : warning == Summary == $ dim checkpatch origin/drm-tip 47e5bfbf30e3 drm/i915/gem: Mark the buffer pool as active for the cmdparser 7ec3c01e7a42 drm/i915: Trim set_timer_ms() intervals 00d105eacda7 drm/i915/gt: Set timeslicing priority from queue 7e77d0a206b9 drm/i915/gt: Always check to enable timeslicing if not submitting b26c3cc35bd3 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" fb7bb70a7283 drm/i915/gt: Couple tasklet scheduling for all CS interrupts cba96e7cdecf drm/i915/gt: Support creation of 'internal' rings ce8cae5ec931 drm/i915/gt: Use client timeline address for seqno writes 710e6262e4f4 drm/i915/gt: Infrastructure for ring scheduling -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 842 lines checked f5112dc2ae3b drm/i915/gt: Enable busy-stats for ring-scheduler -:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #13: new file mode 100644 -:200: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #200: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:47: + udelay(100); -:230: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #230: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:77: + udelay(100); total: 0 errors, 1 warnings, 2 checks, 236 lines checked d8fa9292586c drm/i915/gt: Track if an engine requires forcewake w/a 2cdc09a8fc16 drm/i915/gt: Implement ring scheduler for gen6/7 -:68: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #68: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:324: + *cs++ = i915_mmio_reg_offset( -:70: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #70: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:326: + *cs++ = _MASKED_BIT_ENABLE( -:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #105: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:361: + *cs++ = _MASKED_BIT_DISABLE( total: 0 errors, 0 warnings, 3 checks, 506 lines checked 2ff1bb716df2 drm/i915/gt: Enable ring scheduling for gen6/7 cfed75109fb2 drm/i915/gem: Async GPU relocations only dd90a9050b61 drm/i915: Add list_for_each_entry_safe_continue_reverse -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) total: 0 errors, 0 warnings, 3 checks, 12 lines checked a5768b96efc5 drm/i915/gem: Separate reloc validation into an earlier step -:101: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return #101: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1408: + return (int)offset; + } else { total: 0 errors, 1 warnings, 0 checks, 217 lines checked 37ab424926eb drm/i915/gem: Lift GPU relocation allocation 38ad7f8804a1 drm/i915/gem: Build the reloc request first 7cb671e36bbd drm/i915/gem: Add all GPU reloc awaits/signals en masse 1f32dc179ff3 dma-buf: Proxy fence, an unsignaled fence placeholder -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 -:438: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #438: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20: + spinlock_t lock; total: 0 errors, 1 warnings, 1 checks, 1158 lines checked e665d3e71c75 drm/i915: Unpeel awaits on a proxy fence f155632b03ef drm/i915/gem: Make relocations atomic within execbuf From patchwork at emeril.freedesktop.org Thu Jun 4 11:37:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 11:37:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/22=5D_drm/i915/gem=3A_Mark_the_buffe?= =?utf-8?q?r_pool_as_active_for_the_cmdparser?= In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <159127066093.14555.14536997288961206056@emeril.freedesktop.org> == Series Details == Series: series starting with [01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser URL : https://patchwork.freedesktop.org/series/77996/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Thu Jun 4 11:58:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 11:58:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBk?= =?utf-8?q?evm=5Fdrm=5Fdev=5Falloc=2C_v2_=28rev2=29?= In-Reply-To: <20200415074034.175360-1-daniel.vetter@ffwll.ch> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> Message-ID: <159127189383.14553.5210126157828133103@emeril.freedesktop.org> == Series Details == Series: devm_drm_dev_alloc, v2 (rev2) URL : https://patchwork.freedesktop.org/series/75956/ State : failure == Summary == Applying: drm: Add devm_drm_dev_alloc macro error: sha1 information is lacking or useless (drivers/gpu/drm/drm_drv.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm: Add devm_drm_dev_alloc macro When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Thu Jun 4 12:02:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 12:02:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Exercise_all_copy_engines_with_the_blt_routi?= =?utf-8?q?nes?= In-Reply-To: <20200604102140.8845-1-chris@chris-wilson.co.uk> References: <20200604102140.8845-1-chris@chris-wilson.co.uk> Message-ID: <159127217230.14552.2720258254670054683@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise all copy engines with the blt routines URL : https://patchwork.freedesktop.org/series/77994/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8581 -> Patchwork_17865 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17865 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17865, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17865: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at blt: - fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-cml-u2/igt at i915_selftest@live at blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-cml-u2/igt at i915_selftest@live at blt.html - fi-whl-u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-whl-u/igt at i915_selftest@live at blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-whl-u/igt at i915_selftest@live at blt.html - fi-bxt-dsi: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bxt-dsi/igt at i915_selftest@live at blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-bxt-dsi/igt at i915_selftest@live at blt.html - fi-cfl-8700k: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-cfl-8700k/igt at i915_selftest@live at blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-cfl-8700k/igt at i915_selftest@live at blt.html - fi-skl-6600u: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-skl-6600u/igt at i915_selftest@live at blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-skl-6600u/igt at i915_selftest@live at blt.html - fi-cfl-8109u: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-cfl-8109u/igt at i915_selftest@live at blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-cfl-8109u/igt at i915_selftest@live at blt.html - fi-icl-u2: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-icl-u2/igt at i915_selftest@live at blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-icl-u2/igt at i915_selftest@live at blt.html - fi-snb-2520m: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-snb-2520m/igt at i915_selftest@live at blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-snb-2520m/igt at i915_selftest@live at blt.html - fi-icl-y: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-icl-y/igt at i915_selftest@live at blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-icl-y/igt at i915_selftest@live at blt.html - fi-kbl-8809g: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-8809g/igt at i915_selftest@live at blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-8809g/igt at i915_selftest@live at blt.html - fi-apl-guc: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-apl-guc/igt at i915_selftest@live at blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-apl-guc/igt at i915_selftest@live at blt.html - fi-kbl-r: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-r/igt at i915_selftest@live at blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-r/igt at i915_selftest@live at blt.html - fi-skl-guc: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-skl-guc/igt at i915_selftest@live at blt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-skl-guc/igt at i915_selftest@live at blt.html - fi-bdw-5557u: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bdw-5557u/igt at i915_selftest@live at blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-bdw-5557u/igt at i915_selftest@live at blt.html - fi-kbl-7500u: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-7500u/igt at i915_selftest@live at blt.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-7500u/igt at i915_selftest@live at blt.html - fi-kbl-x1275: [PASS][31] -> [INCOMPLETE][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at i915_selftest@live at blt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-x1275/igt at i915_selftest@live at blt.html - fi-kbl-guc: [PASS][33] -> [INCOMPLETE][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-guc/igt at i915_selftest@live at blt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-guc/igt at i915_selftest@live at blt.html - fi-ivb-3770: [PASS][35] -> [INCOMPLETE][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-ivb-3770/igt at i915_selftest@live at blt.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-ivb-3770/igt at i915_selftest@live at blt.html - fi-skl-lmem: [PASS][37] -> [INCOMPLETE][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-skl-lmem/igt at i915_selftest@live at blt.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-skl-lmem/igt at i915_selftest@live at blt.html - fi-cml-s: [PASS][39] -> [INCOMPLETE][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-cml-s/igt at i915_selftest@live at blt.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-cml-s/igt at i915_selftest@live at blt.html - fi-icl-guc: [PASS][41] -> [INCOMPLETE][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-icl-guc/igt at i915_selftest@live at blt.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-icl-guc/igt at i915_selftest@live at blt.html - fi-kbl-soraka: [PASS][43] -> [INCOMPLETE][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-soraka/igt at i915_selftest@live at blt.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-soraka/igt at i915_selftest@live at blt.html - fi-cfl-guc: [PASS][45] -> [INCOMPLETE][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-cfl-guc/igt at i915_selftest@live at blt.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-cfl-guc/igt at i915_selftest@live at blt.html - fi-hsw-4770: [PASS][47] -> [INCOMPLETE][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-hsw-4770/igt at i915_selftest@live at blt.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-hsw-4770/igt at i915_selftest@live at blt.html - fi-skl-6700k2: [PASS][49] -> [INCOMPLETE][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-skl-6700k2/igt at i915_selftest@live at blt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-skl-6700k2/igt at i915_selftest@live at blt.html * igt at runner@aborted: - fi-snb-2520m: NOTRUN -> [FAIL][51] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-snb-2520m/igt at runner@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][52] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-bdw-5557u/igt at runner@aborted.html - fi-byt-n2820: NOTRUN -> [FAIL][53] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-byt-n2820/igt at runner@aborted.html - fi-snb-2600: NOTRUN -> [FAIL][54] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-snb-2600/igt at runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][55] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-ivb-3770/igt at runner@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][56] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-byt-j1900/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at blt: - {fi-ehl-1}: [PASS][57] -> [INCOMPLETE][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-ehl-1/igt at i915_selftest@live at blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-ehl-1/igt at i915_selftest@live at blt.html Known issues ------------ Here are the changes found in Patchwork_17865 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_render_linear_blits@basic: - fi-tgl-y: [PASS][59] -> [DMESG-WARN][60] ([i915#402]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-y/igt at gem_render_linear_blits@basic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-tgl-y/igt at gem_render_linear_blits@basic.html * igt at i915_module_load@reload: - fi-kbl-soraka: [PASS][61] -> [DMESG-WARN][62] ([i915#1982]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-soraka/igt at i915_module_load@reload.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-soraka/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][63] -> [DMESG-WARN][64] ([i915#1982]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at blt: - fi-byt-j1900: [PASS][65] -> [INCOMPLETE][66] ([i915#45]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-byt-j1900/igt at i915_selftest@live at blt.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-byt-j1900/igt at i915_selftest@live at blt.html - fi-bsw-nick: [PASS][67] -> [INCOMPLETE][68] ([i915#392]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bsw-nick/igt at i915_selftest@live at blt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-bsw-nick/igt at i915_selftest@live at blt.html - fi-bsw-kefka: [PASS][69] -> [INCOMPLETE][70] ([i915#392]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bsw-kefka/igt at i915_selftest@live at blt.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-bsw-kefka/igt at i915_selftest@live at blt.html - fi-tgl-y: [PASS][71] -> [INCOMPLETE][72] ([i915#750]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-y/igt at i915_selftest@live at blt.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-tgl-y/igt at i915_selftest@live at blt.html - fi-snb-2600: [PASS][73] -> [INCOMPLETE][74] ([i915#82]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-snb-2600/igt at i915_selftest@live at blt.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-snb-2600/igt at i915_selftest@live at blt.html - fi-glk-dsi: [PASS][75] -> [INCOMPLETE][76] ([i915#58] / [k.org#198133]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-glk-dsi/igt at i915_selftest@live at blt.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-glk-dsi/igt at i915_selftest@live at blt.html - fi-byt-n2820: [PASS][77] -> [INCOMPLETE][78] ([i915#45]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-byt-n2820/igt at i915_selftest@live at blt.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-byt-n2820/igt at i915_selftest@live at blt.html - fi-bsw-n3050: [PASS][79] -> [INCOMPLETE][80] ([i915#392]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bsw-n3050/igt at i915_selftest@live at blt.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-bsw-n3050/igt at i915_selftest@live at blt.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][81] -> [DMESG-WARN][82] ([i915#62] / [i915#92] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at kms_busy@basic at flip.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [PASS][83] -> [DMESG-WARN][84] ([i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][85] ([i915#1982]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-plain-flip at d-dsi1}: - {fi-tgl-dsi}: [DMESG-WARN][87] ([i915#1982]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-dsi/igt at kms_flip@basic-plain-flip at d-dsi1.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-tgl-dsi/igt at kms_flip@basic-plain-flip at d-dsi1.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-tgl-y: [DMESG-WARN][89] ([i915#1982]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html #### Warnings #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-kbl-x1275: [DMESG-WARN][91] ([i915#62] / [i915#92]) -> [DMESG-WARN][92] ([i915#62] / [i915#92] / [i915#95]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at i915_pm_rpm@basic-pci-d3-state.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-x1275/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][93] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][94] ([i915#62] / [i915#92]) +6 similar issues [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8581 -> Patchwork_17865 CI-20190529: 20190529 CI_DRM_8581: a3ae560b4c2a6dfb0d550cc40471a7b0c7043500 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17865: dbd180308199326bb193a078f3e4a407c58fa046 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dbd180308199 drm/i915/selftests: Exercise all copy engines with the blt routines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17865/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 12:06:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 12:06:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/22=5D_drm/i915/gem=3A_Mark_the_buffer_p?= =?utf-8?q?ool_as_active_for_the_cmdparser?= In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <159127238615.14553.564684845605068396@emeril.freedesktop.org> == Series Details == Series: series starting with [01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser URL : https://patchwork.freedesktop.org/series/77996/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8581 -> Patchwork_17866 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17866 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17866, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17866: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_engines: - fi-icl-y: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-icl-y/igt at i915_selftest@live at gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-icl-y/igt at i915_selftest@live at gt_engines.html * igt at i915_selftest@live at hangcheck: - fi-snb-2520m: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-snb-2520m/igt at i915_selftest@live at hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-snb-2520m/igt at i915_selftest@live at hangcheck.html * igt at runner@aborted: - fi-snb-2520m: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-snb-2520m/igt at runner@aborted.html New tests --------- New tests have been introduced between CI_DRM_8581 and Patchwork_17866: ### New IGT tests (1) ### * igt at dmabuf@all at dma_fence_proxy: - Statuses : 41 pass(s) - Exec time: [0.03, 0.10] s Known issues ------------ Here are the changes found in Patchwork_17866 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-guc: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-plain-flip at d-dsi1}: - {fi-tgl-dsi}: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-dsi/igt at kms_flip@basic-plain-flip at d-dsi1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-tgl-dsi/igt at kms_flip@basic-plain-flip at d-dsi1.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-tgl-y: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][17] ([i915#62] / [i915#92]) +5 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8581 -> Patchwork_17866 CI-20190529: 20190529 CI_DRM_8581: a3ae560b4c2a6dfb0d550cc40471a7b0c7043500 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17866: f155632b03efee471b40239252a862a43ffd022d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f155632b03ef drm/i915/gem: Make relocations atomic within execbuf e665d3e71c75 drm/i915: Unpeel awaits on a proxy fence 1f32dc179ff3 dma-buf: Proxy fence, an unsignaled fence placeholder 7cb671e36bbd drm/i915/gem: Add all GPU reloc awaits/signals en masse 38ad7f8804a1 drm/i915/gem: Build the reloc request first 37ab424926eb drm/i915/gem: Lift GPU relocation allocation a5768b96efc5 drm/i915/gem: Separate reloc validation into an earlier step dd90a9050b61 drm/i915: Add list_for_each_entry_safe_continue_reverse cfed75109fb2 drm/i915/gem: Async GPU relocations only 2ff1bb716df2 drm/i915/gt: Enable ring scheduling for gen6/7 2cdc09a8fc16 drm/i915/gt: Implement ring scheduler for gen6/7 d8fa9292586c drm/i915/gt: Track if an engine requires forcewake w/a f5112dc2ae3b drm/i915/gt: Enable busy-stats for ring-scheduler 710e6262e4f4 drm/i915/gt: Infrastructure for ring scheduling ce8cae5ec931 drm/i915/gt: Use client timeline address for seqno writes cba96e7cdecf drm/i915/gt: Support creation of 'internal' rings fb7bb70a7283 drm/i915/gt: Couple tasklet scheduling for all CS interrupts b26c3cc35bd3 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" 7e77d0a206b9 drm/i915/gt: Always check to enable timeslicing if not submitting 00d105eacda7 drm/i915/gt: Set timeslicing priority from queue 7ec3c01e7a42 drm/i915: Trim set_timer_ms() intervals 47e5bfbf30e3 drm/i915/gem: Mark the buffer pool as active for the cmdparser == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17866/index.html From chris at chris-wilson.co.uk Thu Jun 4 12:36:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 13:36:41 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise all copy engines with the blt routines In-Reply-To: <20200604102140.8845-1-chris@chris-wilson.co.uk> References: <20200604102140.8845-1-chris@chris-wilson.co.uk> Message-ID: <20200604123641.767-1-chris@chris-wilson.co.uk> Just to remove an obnoxious HAS_ENGINES(), and in the process make the code agnostic to the availabilty of any particular engine by making it exercise any and all such engines declared on the system. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Matthew Auld <matthew.auld at intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Reviewed-by: Matthew Auld <matthew.auld at intel.com> --- .../i915/gem/selftests/i915_gem_client_blt.c | 3 - .../i915/gem/selftests/i915_gem_object_blt.c | 55 ++++++++++++------- .../gpu/drm/i915/gem/selftests/mock_context.c | 37 +++++++++++++ .../gpu/drm/i915/gem/selftests/mock_context.h | 4 ++ drivers/gpu/drm/i915/i915_drv.h | 5 ++ 5 files changed, 80 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index 8fe3ad2ee34e..299c29e9ad86 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -702,8 +702,5 @@ int i915_gem_client_blt_live_selftests(struct drm_i915_private *i915) if (intel_gt_is_wedged(&i915->gt)) return 0; - if (!HAS_ENGINE(i915, BCS0)) - return 0; - return i915_live_subtests(tests, i915); } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c index 31549ad83fa6..23b6e11bbc3e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c @@ -193,7 +193,7 @@ static int perf_copy_blt(void *arg) } struct igt_thread_arg { - struct drm_i915_private *i915; + struct intel_engine_cs *engine; struct i915_gem_context *ctx; struct file *file; struct rnd_state prng; @@ -203,7 +203,7 @@ struct igt_thread_arg { static int igt_fill_blt_thread(void *arg) { struct igt_thread_arg *thread = arg; - struct drm_i915_private *i915 = thread->i915; + struct intel_engine_cs *engine = thread->engine; struct rnd_state *prng = &thread->prng; struct drm_i915_gem_object *obj; struct i915_gem_context *ctx; @@ -215,7 +215,7 @@ static int igt_fill_blt_thread(void *arg) ctx = thread->ctx; if (!ctx) { - ctx = live_context(i915, thread->file); + ctx = live_context_for_engine(engine, thread->file); if (IS_ERR(ctx)) return PTR_ERR(ctx); @@ -223,7 +223,7 @@ static int igt_fill_blt_thread(void *arg) ctx->sched.priority = I915_USER_PRIORITY(prio); } - ce = i915_gem_context_get_engine(ctx, BCS0); + ce = i915_gem_context_get_engine(ctx, 0); GEM_BUG_ON(IS_ERR(ce)); /* @@ -256,7 +256,7 @@ static int igt_fill_blt_thread(void *arg) pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__, phys_sz, sz, val); - obj = huge_gem_object(i915, phys_sz, sz); + obj = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(obj)) { err = PTR_ERR(obj); goto err_flush; @@ -321,7 +321,7 @@ static int igt_fill_blt_thread(void *arg) static int igt_copy_blt_thread(void *arg) { struct igt_thread_arg *thread = arg; - struct drm_i915_private *i915 = thread->i915; + struct intel_engine_cs *engine = thread->engine; struct rnd_state *prng = &thread->prng; struct drm_i915_gem_object *src, *dst; struct i915_gem_context *ctx; @@ -333,7 +333,7 @@ static int igt_copy_blt_thread(void *arg) ctx = thread->ctx; if (!ctx) { - ctx = live_context(i915, thread->file); + ctx = live_context_for_engine(engine, thread->file); if (IS_ERR(ctx)) return PTR_ERR(ctx); @@ -341,7 +341,7 @@ static int igt_copy_blt_thread(void *arg) ctx->sched.priority = I915_USER_PRIORITY(prio); } - ce = i915_gem_context_get_engine(ctx, BCS0); + ce = i915_gem_context_get_engine(ctx, 0); GEM_BUG_ON(IS_ERR(ce)); /* @@ -374,7 +374,7 @@ static int igt_copy_blt_thread(void *arg) pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__, phys_sz, sz, val); - src = huge_gem_object(i915, phys_sz, sz); + src = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(src)) { err = PTR_ERR(src); goto err_flush; @@ -394,7 +394,7 @@ static int igt_copy_blt_thread(void *arg) if (!(src->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) src->cache_dirty = true; - dst = huge_gem_object(i915, phys_sz, sz); + dst = huge_gem_object(engine->i915, phys_sz, sz); if (IS_ERR(dst)) { err = PTR_ERR(dst); goto err_put_src; @@ -456,7 +456,7 @@ static int igt_copy_blt_thread(void *arg) return err; } -static int igt_threaded_blt(struct drm_i915_private *i915, +static int igt_threaded_blt(struct intel_engine_cs *engine, int (*blt_fn)(void *arg), unsigned int flags) #define SINGLE_CTX BIT(0) @@ -477,14 +477,14 @@ static int igt_threaded_blt(struct drm_i915_private *i915, if (!thread) goto out_tsk; - thread[0].file = mock_file(i915); + thread[0].file = mock_file(engine->i915); if (IS_ERR(thread[0].file)) { err = PTR_ERR(thread[0].file); goto out_thread; } if (flags & SINGLE_CTX) { - thread[0].ctx = live_context(i915, thread[0].file); + thread[0].ctx = live_context_for_engine(engine, thread[0].file); if (IS_ERR(thread[0].ctx)) { err = PTR_ERR(thread[0].ctx); goto out_file; @@ -492,7 +492,7 @@ static int igt_threaded_blt(struct drm_i915_private *i915, } for (i = 0; i < n_cpus; ++i) { - thread[i].i915 = i915; + thread[i].engine = engine; thread[i].file = thread[0].file; thread[i].ctx = thread[0].ctx; thread[i].n_cpus = n_cpus; @@ -532,24 +532,40 @@ static int igt_threaded_blt(struct drm_i915_private *i915, return err; } +static int test_copy_engines(struct drm_i915_private *i915, + int (*fn)(void *arg), + unsigned int flags) +{ + struct intel_engine_cs *engine; + int ret; + + for_each_uabi_class_engine(engine, I915_ENGINE_CLASS_COPY, i915) { + ret = igt_threaded_blt(engine, fn, flags); + if (ret) + return ret; + } + + return 0; +} + static int igt_fill_blt(void *arg) { - return igt_threaded_blt(arg, igt_fill_blt_thread, 0); + return test_copy_engines(arg, igt_fill_blt_thread, 0); } static int igt_fill_blt_ctx0(void *arg) { - return igt_threaded_blt(arg, igt_fill_blt_thread, SINGLE_CTX); + return test_copy_engines(arg, igt_fill_blt_thread, SINGLE_CTX); } static int igt_copy_blt(void *arg) { - return igt_threaded_blt(arg, igt_copy_blt_thread, 0); + return test_copy_engines(arg, igt_copy_blt_thread, 0); } static int igt_copy_blt_ctx0(void *arg) { - return igt_threaded_blt(arg, igt_copy_blt_thread, SINGLE_CTX); + return test_copy_engines(arg, igt_copy_blt_thread, SINGLE_CTX); } int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915) @@ -564,9 +580,6 @@ int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915) if (intel_gt_is_wedged(&i915->gt)) return 0; - if (!HAS_ENGINE(i915, BCS0)) - return 0; - return i915_live_subtests(tests, i915); } diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c b/drivers/gpu/drm/i915/gem/selftests/mock_context.c index e7e3c620f542..aa0d06cf1903 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c @@ -99,6 +99,43 @@ live_context(struct drm_i915_private *i915, struct file *file) return ERR_PTR(err); } +struct i915_gem_context * +live_context_for_engine(struct intel_engine_cs *engine, struct file *file) +{ + struct i915_gem_engines *engines; + struct i915_gem_context *ctx; + struct intel_context *ce; + + engines = alloc_engines(1); + if (!engines) + return ERR_PTR(-ENOMEM); + + ctx = live_context(engine->i915, file); + if (IS_ERR(ctx)) { + __free_engines(engines, 0); + return ctx; + } + + ce = intel_context_create(engine); + if (IS_ERR(ce)) { + __free_engines(engines, 0); + return ERR_CAST(ce); + } + + intel_context_set_gem(ce, ctx); + engines->engines[0] = ce; + engines->num_engines = 1; + + mutex_lock(&ctx->engines_mutex); + i915_gem_context_set_user_engines(ctx); + engines = rcu_replace_pointer(ctx->engines, engines, 1); + mutex_unlock(&ctx->engines_mutex); + + engines_idle_release(ctx, engines); + + return ctx; +} + struct i915_gem_context * kernel_context(struct drm_i915_private *i915) { diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.h b/drivers/gpu/drm/i915/gem/selftests/mock_context.h index fb83d2f09212..2a6121d33352 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.h +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.h @@ -9,6 +9,7 @@ struct file; struct drm_i915_private; +struct intel_engine_cs; void mock_init_contexts(struct drm_i915_private *i915); @@ -21,6 +22,9 @@ void mock_context_close(struct i915_gem_context *ctx); struct i915_gem_context * live_context(struct drm_i915_private *i915, struct file *file); +struct i915_gem_context * +live_context_for_engine(struct intel_engine_cs *engine, struct file *file); + struct i915_gem_context *kernel_context(struct drm_i915_private *i915); void kernel_context_close(struct i915_gem_context *ctx); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e99255e17eb7..1e49abc5a342 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1264,6 +1264,11 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) (engine__); \ (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) +#define for_each_uabi_class_engine(engine__, class__, i915__) \ + for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ + (engine__) && (engine__)->uabi_class == (class__); \ + (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) + #define I915_GTT_OFFSET_NONE ((u32)-1) /* -- 2.20.1 From matthew.william.auld at gmail.com Thu Jun 4 12:49:06 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Thu, 4 Jun 2020 13:49:06 +0100 Subject: [Intel-gfx] [PATCH 01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHNe5ssL2tzyg6b7g0zdeypPSy_krYY3bPdRRP6O7-OQRg@mail.gmail.com> On Thu, 4 Jun 2020 at 11:38, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > If the execbuf is interrupted after building the cmdparser pipeline, and > before we commit to submitting the request to HW, we would attempt to > clean up the cmdparser early. While we held active references to the vma > being parsed and constructed, we did not hold an active reference for > the buffer pool itself. The result was that an interrupted execbuf could > still have run the cmdparser pipeline, but since the buffer pool was > idle, its target vma could have been recycled. > > Note this problem only occurs if the cmdparser is running async due to > pipelined waits on busy fences, and the execbuf is interrupted. > > Fixes: 686c7c35abc2 ("drm/i915/gem: Asynchronous cmdparser") > Fixes: 16e87459673a ("drm/i915/gt: Move the batch buffer pool from the engine to the gt") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From patchwork at emeril.freedesktop.org Thu Jun 4 12:54:03 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 12:54:03 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/selftests=3A_Exercise_all_copy_engines_with_the_bl?= =?utf-8?q?t_routines_=28rev2=29?= In-Reply-To: <20200604102140.8845-1-chris@chris-wilson.co.uk> References: <20200604102140.8845-1-chris@chris-wilson.co.uk> Message-ID: <159127524366.14554.4317136333331096360@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise all copy engines with the blt routines (rev2) URL : https://patchwork.freedesktop.org/series/77994/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9edabff31b22 drm/i915/selftests: Exercise all copy engines with the blt routines -:292: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'engine__' - possible side-effects? #292: FILE: drivers/gpu/drm/i915/i915_drv.h:1267: +#define for_each_uabi_class_engine(engine__, class__, i915__) \ + for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ + (engine__) && (engine__)->uabi_class == (class__); \ + (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) -:292: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'class__' - possible side-effects? #292: FILE: drivers/gpu/drm/i915/i915_drv.h:1267: +#define for_each_uabi_class_engine(engine__, class__, i915__) \ + for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ + (engine__) && (engine__)->uabi_class == (class__); \ + (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) total: 0 errors, 0 warnings, 2 checks, 243 lines checked From matthew.william.auld at gmail.com Thu Jun 4 12:54:34 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Thu, 4 Jun 2020 13:54:34 +0100 Subject: [Intel-gfx] [PATCH 02/22] drm/i915: Trim set_timer_ms() intervals In-Reply-To: <20200604103751.18816-2-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> <20200604103751.18816-2-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHPNdmV5JUXXKJYNFZ56nwVE7spRPBGP-vsYwSOkA7USBg@mail.gmail.com> On Thu, 4 Jun 2020 at 11:38, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Use the plain msec_to_jiffies() rather than the _timeout variant so we > round down and do not add an extra jiffy to our interval. For example, > with timeslicing we do not want to err on the longer side as any > fairness depends on catching hogging contexts on the GPU. Bring on > CFS. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From peterz at infradead.org Thu Jun 4 10:11:07 2020 From: peterz at infradead.org (Peter Zijlstra) Date: Thu, 4 Jun 2020 12:11:07 +0200 Subject: [Intel-gfx] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 In-Reply-To: <20200602182710.GD2604@hirez.programming.kicks-ass.net> References: <20200602174639.GB2604@hirez.programming.kicks-ass.net> <5a40182c8a865d6c5603de4a1ff72c450ff403c3.camel@intel.com> <20200602182710.GD2604@hirez.programming.kicks-ass.net> Message-ID: <20200604101107.GA2948@hirez.programming.kicks-ass.net> On Tue, Jun 02, 2020 at 08:27:10PM +0200, Peter Zijlstra wrote: > On Tue, Jun 02, 2020 at 06:08:03PM +0000, Souza, Jose wrote: > > Hi Peter > > Please file a bug by follow this instructions: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs > > *sigh*, top posting and webforms :-( > > Steps to reproduce: Boot into X > > How often: Always > > uname -r: 5.6.0-2-amd64 > > Machine: Supermicro X11SSZ-F > > Display connector: > > [ 14.907] (II) intel(0): switch to mode 3840x2160 at 60.0 on DP2 using pipe 0, position (0, 0), rotation normal, reflection none > [ 14.918] (II) intel(0): switch to mode 3840x2160 at 60.0 on DP3 using pipe 1, position (0, 0), rotation normal, reflection none > > > I'll add the kernel parameters next time I reboot this thing, I'll also > add the latest drm next time I build a kernel for this machine. dmesg attached, I've yet to build a new kernel for this box.. -------------- next part -------------- [ 0.000000] microcode: microcode updated early to revision 0xd6, date = 2019-10-03 [ 0.000000] Linux version 5.6.0-2-amd64 (debian-kernel at lists.debian.org) (gcc version 9.3.0 (Debian 9.3.0-13)) #1 SMP Debian 5.6.14-1 (2020-05-23) [ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-5.6.0-2-amd64 root=UUID=8b0cce80-c4f1-4b44-8227-b0e10b4cb575 ro drm.debug=0x1e log_buf_len=1M quiet drm.debug=0x1e log_buf_len=1M [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' [ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 [ 0.000000] x86/fpu: xstate_offset[3]: 832, xstate_sizes[3]: 64 [ 0.000000] x86/fpu: xstate_offset[4]: 896, xstate_sizes[4]: 64 [ 0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format. [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000098bff] usable [ 0.000000] BIOS-e820: [mem 0x0000000000098c00-0x000000000009ffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x0000000080be4fff] usable [ 0.000000] BIOS-e820: [mem 0x0000000080be5000-0x0000000080be5fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x0000000080be6000-0x0000000080be6fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000080be7000-0x000000008ac6efff] usable [ 0.000000] BIOS-e820: [mem 0x000000008ac6f000-0x000000008b022fff] reserved [ 0.000000] BIOS-e820: [mem 0x000000008b023000-0x000000008b158fff] usable [ 0.000000] BIOS-e820: [mem 0x000000008b159000-0x000000008b82efff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x000000008b82f000-0x000000008bffefff] reserved [ 0.000000] BIOS-e820: [mem 0x000000008bfff000-0x000000008bffffff] usable [ 0.000000] BIOS-e820: [mem 0x000000008c000000-0x000000008f7fffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed00fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000086e7fffff] usable [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] SMBIOS 3.0.0 present. [ 0.000000] DMI: Supermicro Super Server/X11SSZ-F, BIOS 2.0 01/26/2017 [ 0.000000] tsc: Detected 3500.000 MHz processor [ 0.001405] tsc: Detected 3499.912 MHz TSC [ 0.001406] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.001407] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.001411] last_pfn = 0x86e800 max_arch_pfn = 0x400000000 [ 0.001414] MTRR default type: write-back [ 0.001414] MTRR fixed ranges enabled: [ 0.001415] 00000-9FFFF write-back [ 0.001416] A0000-BFFFF uncachable [ 0.001416] C0000-FFFFF write-protect [ 0.001417] MTRR variable ranges enabled: [ 0.001418] 0 base 00C0000000 mask 7FC0000000 uncachable [ 0.001418] 1 base 00A0000000 mask 7FE0000000 uncachable [ 0.001419] 2 base 0090000000 mask 7FF0000000 uncachable [ 0.001419] 3 base 008E000000 mask 7FFE000000 uncachable [ 0.001420] 4 base 008D000000 mask 7FFF000000 uncachable [ 0.001420] 5 disabled [ 0.001420] 6 disabled [ 0.001421] 7 disabled [ 0.001421] 8 disabled [ 0.001421] 9 disabled [ 0.001815] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT [ 0.001948] last_pfn = 0x8c000 max_arch_pfn = 0x400000000 [ 0.007624] found SMP MP-table at [mem 0x000fcce0-0x000fccef] [ 0.007674] Using GB pages for direct mapping [ 0.007676] BRK [0x6bb201000, 0x6bb201fff] PGTABLE [ 0.007677] BRK [0x6bb202000, 0x6bb202fff] PGTABLE [ 0.007677] BRK [0x6bb203000, 0x6bb203fff] PGTABLE [ 0.007694] BRK [0x6bb204000, 0x6bb204fff] PGTABLE [ 0.007695] BRK [0x6bb205000, 0x6bb205fff] PGTABLE [ 0.007767] BRK [0x6bb206000, 0x6bb206fff] PGTABLE [ 0.007792] BRK [0x6bb207000, 0x6bb207fff] PGTABLE [ 0.007869] BRK [0x6bb208000, 0x6bb208fff] PGTABLE [ 0.007910] BRK [0x6bb209000, 0x6bb209fff] PGTABLE [ 0.007942] BRK [0x6bb20a000, 0x6bb20afff] PGTABLE [ 0.008010] printk: log_buf_len: 1048576 bytes [ 0.008011] printk: early log buf free: 126272(96%) [ 0.008012] RAMDISK: [mem 0x32ae7000-0x3556afff] [ 0.008016] ACPI: Early table checksum verification disabled [ 0.008018] ACPI: RSDP 0x00000000000F05B0 000024 (v02 SUPERM) [ 0.008020] ACPI: XSDT 0x000000008B1590C0 0000FC (v01 SUPERM SUPERM 01072009 AMI 00010013) [ 0.008024] ACPI: FACP 0x000000008B17F320 000114 (v06 01072009 AMI 00010013) [ 0.008028] ACPI: DSDT 0x000000008B159250 0260CB (v02 SUPERM SMCI--MB 01072009 INTL 20160422) [ 0.008030] ACPI: FACS 0x000000008B82EC80 000040 [ 0.008032] ACPI: APIC 0x000000008B17F438 0000BC (v03 01072009 AMI 00010013) [ 0.008033] ACPI: FPDT 0x000000008B17F4F8 000044 (v01 01072009 AMI 00010013) [ 0.008035] ACPI: SPMI 0x000000008B17F540 000040 (v05 SUPERM SMCI--MB 00000000 AMI. 00000000) [ 0.008037] ACPI: MCFG 0x000000008B17F580 00003C (v01 SUPERM SMCI--MB 01072009 MSFT 00000097) [ 0.008039] ACPI: SSDT 0x000000008B17F5C0 000224 (v01 SataRe SataTabl 00001000 INTL 20160422) [ 0.008040] ACPI: FIDT 0x000000008B17F7E8 00009C (v01 SUPERM SMCI--MB 01072009 AMI 00010013) [ 0.008042] ACPI: SSDT 0x000000008B17F888 003159 (v02 SaSsdt SaSsdt 00003000 INTL 20160422) [ 0.008044] ACPI: SSDT 0x000000008B1829E8 00255F (v02 PegSsd PegSsdt 00001000 INTL 20160422) [ 0.008046] ACPI: HPET 0x000000008B184F48 000038 (v01 INTEL SKL 00000001 MSFT 0000005F) [ 0.008047] ACPI: SSDT 0x000000008B184F80 000024 (v02 INTEL OEM_RTD3 00001000 INTL 20160422) [ 0.008049] ACPI: SSDT 0x000000008B184FA8 000DE5 (v02 INTEL Ther_Rvp 00001000 INTL 20160422) [ 0.008051] ACPI: SSDT 0x000000008B185D90 000AF2 (v02 INTEL xh_rvp08 00000000 INTL 20160422) [ 0.008052] ACPI: UEFI 0x000000008B186888 000042 (v01 INTEL EDK2 00000002 01000013) [ 0.008054] ACPI: SSDT 0x000000008B1868D0 000EDE (v02 CpuRef CpuSsdt 00003000 INTL 20160422) [ 0.008056] ACPI: LPIT 0x000000008B1877B0 000094 (v01 INTEL SKL 00000000 MSFT 0000005F) [ 0.008057] ACPI: WSMT 0x000000008B187848 000028 (v01 INTEL SKL 00000000 MSFT 0000005F) [ 0.008059] ACPI: SSDT 0x000000008B187870 00029F (v02 INTEL sensrhub 00000000 INTL 20160422) [ 0.008061] ACPI: SSDT 0x000000008B187B10 003002 (v02 INTEL PtidDevc 00001000 INTL 20160422) [ 0.008062] ACPI: DBGP 0x000000008B18AB18 000034 (v01 INTEL 00000002 MSFT 0000005F) [ 0.008064] ACPI: DBG2 0x000000008B18AB50 000054 (v00 INTEL 00000002 MSFT 0000005F) [ 0.008065] ACPI: DMAR 0x000000008B18ABA8 000114 (v01 INTEL SKL 00000001 INTL 00000001) [ 0.008067] ACPI: ASF! 0x000000008B18ACC0 0000A0 (v32 INTEL HCG 00000001 TFSM 000F4240) [ 0.008069] ACPI: EINJ 0x000000008B18AD60 000130 (v01 AMI AMI.EINJ 00000000 AMI. 00000000) [ 0.008071] ACPI: ERST 0x000000008B18AE90 000230 (v01 AMIER AMI.ERST 00000000 AMI. 00000000) [ 0.008072] ACPI: BERT 0x000000008B18B0C0 000030 (v01 AMI AMI.BERT 00000000 AMI. 00000000) [ 0.008074] ACPI: HEST 0x000000008B18B0F0 0000A8 (v01 AMI AMI.HEST 00000000 AMI. 00000000) [ 0.008079] ACPI: Local APIC address 0xfee00000 [ 0.008229] No NUMA configuration found [ 0.008229] Faking a node at [mem 0x0000000000000000-0x000000086e7fffff] [ 0.008232] NODE_DATA(0) allocated [mem 0x86e6fb000-0x86e6fffff] [ 0.008261] Zone ranges: [ 0.008262] DMA [mem 0x0000000000001000-0x0000000000ffffff] [ 0.008262] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] [ 0.008263] Normal [mem 0x0000000100000000-0x000000086e7fffff] [ 0.008264] Device empty [ 0.008264] Movable zone start for each node [ 0.008265] Early memory node ranges [ 0.008265] node 0: [mem 0x0000000000001000-0x0000000000097fff] [ 0.008266] node 0: [mem 0x0000000000100000-0x0000000080be4fff] [ 0.008266] node 0: [mem 0x0000000080be7000-0x000000008ac6efff] [ 0.008267] node 0: [mem 0x000000008b023000-0x000000008b158fff] [ 0.008267] node 0: [mem 0x000000008bfff000-0x000000008bffffff] [ 0.008267] node 0: [mem 0x0000000100000000-0x000000086e7fffff] [ 0.008451] Zeroed struct page in unavailable ranges: 27333 pages [ 0.008452] Initmem setup node 0 [mem 0x0000000000001000-0x000000086e7fffff] [ 0.008453] On node 0 totalpages: 8361275 [ 0.008454] DMA zone: 64 pages used for memmap [ 0.008454] DMA zone: 21 pages reserved [ 0.008455] DMA zone: 3991 pages, LIFO batch:0 [ 0.008498] DMA32 zone: 8823 pages used for memmap [ 0.008498] DMA32 zone: 564644 pages, LIFO batch:63 [ 0.014514] Normal zone: 121760 pages used for memmap [ 0.014515] Normal zone: 7792640 pages, LIFO batch:63 [ 0.014866] Reserving Intel graphics memory at [mem 0x8d800000-0x8f7fffff] [ 0.015181] ACPI: PM-Timer IO Port: 0x1808 [ 0.015182] ACPI: Local APIC address 0xfee00000 [ 0.015186] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) [ 0.015187] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1]) [ 0.015187] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1]) [ 0.015188] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1]) [ 0.015188] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1]) [ 0.015188] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1]) [ 0.015189] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1]) [ 0.015189] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1]) [ 0.015215] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119 [ 0.015216] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.015217] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [ 0.015218] ACPI: IRQ0 used by override. [ 0.015218] ACPI: IRQ9 used by override. [ 0.015219] Using ACPI (MADT) for SMP configuration information [ 0.015220] ACPI: HPET id: 0x8086a201 base: 0xfed00000 [ 0.015223] smpboot: Allowing 8 CPUs, 0 hotplug CPUs [ 0.015235] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff] [ 0.015236] PM: hibernation: Registered nosave memory: [mem 0x00098000-0x00098fff] [ 0.015236] PM: hibernation: Registered nosave memory: [mem 0x00099000-0x0009ffff] [ 0.015236] PM: hibernation: Registered nosave memory: [mem 0x000a0000-0x000dffff] [ 0.015237] PM: hibernation: Registered nosave memory: [mem 0x000e0000-0x000fffff] [ 0.015238] PM: hibernation: Registered nosave memory: [mem 0x80be5000-0x80be5fff] [ 0.015238] PM: hibernation: Registered nosave memory: [mem 0x80be6000-0x80be6fff] [ 0.015239] PM: hibernation: Registered nosave memory: [mem 0x8ac6f000-0x8b022fff] [ 0.015240] PM: hibernation: Registered nosave memory: [mem 0x8b159000-0x8b82efff] [ 0.015240] PM: hibernation: Registered nosave memory: [mem 0x8b82f000-0x8bffefff] [ 0.015241] PM: hibernation: Registered nosave memory: [mem 0x8c000000-0x8f7fffff] [ 0.015242] PM: hibernation: Registered nosave memory: [mem 0x8f800000-0xdfffffff] [ 0.015242] PM: hibernation: Registered nosave memory: [mem 0xe0000000-0xefffffff] [ 0.015242] PM: hibernation: Registered nosave memory: [mem 0xf0000000-0xfdffffff] [ 0.015243] PM: hibernation: Registered nosave memory: [mem 0xfe000000-0xfe010fff] [ 0.015243] PM: hibernation: Registered nosave memory: [mem 0xfe011000-0xfebfffff] [ 0.015243] PM: hibernation: Registered nosave memory: [mem 0xfec00000-0xfec00fff] [ 0.015244] PM: hibernation: Registered nosave memory: [mem 0xfec01000-0xfecfffff] [ 0.015244] PM: hibernation: Registered nosave memory: [mem 0xfed00000-0xfed00fff] [ 0.015244] PM: hibernation: Registered nosave memory: [mem 0xfed01000-0xfedfffff] [ 0.015245] PM: hibernation: Registered nosave memory: [mem 0xfee00000-0xfee00fff] [ 0.015245] PM: hibernation: Registered nosave memory: [mem 0xfee01000-0xfeffffff] [ 0.015245] PM: hibernation: Registered nosave memory: [mem 0xff000000-0xffffffff] [ 0.015246] [mem 0x8f800000-0xdfffffff] available for PCI devices [ 0.015247] Booting paravirtualized kernel on bare hardware [ 0.015249] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns [ 0.017968] setup_percpu: NR_CPUS:512 nr_cpumask_bits:512 nr_cpu_ids:8 nr_node_ids:1 [ 0.018085] percpu: Embedded 55 pages/cpu s188120 r8192 d28968 u262144 [ 0.018090] pcpu-alloc: s188120 r8192 d28968 u262144 alloc=1*2097152 [ 0.018090] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 [ 0.018105] Built 1 zonelists, mobility grouping on. Total pages: 8230607 [ 0.018105] Policy zone: Normal [ 0.018106] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-5.6.0-2-amd64 root=UUID=8b0cce80-c4f1-4b44-8227-b0e10b4cb575 ro drm.debug=0x1e log_buf_len=1M quiet drm.debug=0x1e log_buf_len=1M [ 0.019244] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear) [ 0.019780] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear) [ 0.019835] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.033348] Memory: 2296456K/33445100K available (10243K kernel code, 1285K rwdata, 3976K rodata, 1612K init, 1976K bss, 710496K reserved, 0K cma-reserved) [ 0.033354] random: get_random_u64 called from __kmem_cache_create+0x3e/0x530 with crng_init=0 [ 0.033429] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 [ 0.033437] Kernel/User page tables isolation: enabled [ 0.033446] ftrace: allocating 34646 entries in 136 pages [ 0.042912] ftrace: allocated 136 pages with 2 groups [ 0.042970] rcu: Hierarchical RCU implementation. [ 0.042971] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=8. [ 0.042972] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.042972] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 [ 0.044921] NR_IRQS: 33024, nr_irqs: 2048, preallocated irqs: 16 [ 0.045216] random: crng done (trusting CPU's manufacturer) [ 0.047453] Console: colour VGA+ 80x25 [ 0.047456] printk: console [tty0] enabled [ 0.047468] ACPI: Core revision 20200110 [ 0.047689] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns [ 0.047753] APIC: Switch to symmetric I/O mode setup [ 0.047754] DMAR: Host address width 39 [ 0.047755] DMAR: DRHD base: 0x000000fed90000 flags: 0x0 [ 0.047758] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 7e3ff0505e [ 0.047759] DMAR: DRHD base: 0x000000fed91000 flags: 0x1 [ 0.047761] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da [ 0.047762] DMAR: RMRR base: 0x0000008af45000 end: 0x0000008af64fff [ 0.047763] DMAR: RMRR base: 0x0000008d000000 end: 0x0000008f7fffff [ 0.047763] DMAR: ANDD device: 1 name: \_SB.PCI0.I2C0 [ 0.047764] DMAR: ANDD device: 2 name: \_SB.PCI0.I2C1 [ 0.047764] DMAR: ANDD device: 9 name: \_SB.PCI0.UA00 [ 0.047765] DMAR-IR: IOAPIC id 2 under DRHD base 0xfed91000 IOMMU 1 [ 0.047766] DMAR-IR: HPET id 0 under DRHD base 0xfed91000 [ 0.047766] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping. [ 0.049206] DMAR-IR: Enabled IRQ remapping in x2apic mode [ 0.049207] x2apic enabled [ 0.049219] Switched APIC routing to cluster x2apic. [ 0.053180] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.071756] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x3272fd97217, max_idle_ns: 440795241220 ns [ 0.071759] Calibrating delay loop (skipped), value calculated using timer frequency.. 6999.82 BogoMIPS (lpj=13999648) [ 0.071760] pid_max: default: 32768 minimum: 301 [ 0.071779] LSM: Security Framework initializing [ 0.071783] Yama: disabled by default; enable with sysctl kernel.yama.* [ 0.071798] AppArmor: AppArmor initialized [ 0.071799] TOMOYO Linux initialized [ 0.071846] Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) [ 0.071883] Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) [ 0.072051] mce: CPU0: Thermal monitoring enabled (TM1) [ 0.072066] process: using mwait in idle threads [ 0.072067] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8 [ 0.072068] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4 [ 0.072069] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization [ 0.072070] Spectre V2 : Mitigation: Full generic retpoline [ 0.072071] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch [ 0.072071] Spectre V2 : Enabling Restricted Speculation for firmware calls [ 0.072072] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier [ 0.072072] Spectre V2 : User space: Mitigation: STIBP via seccomp and prctl [ 0.072073] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp [ 0.072075] TAA: Mitigation: Clear CPU buffers [ 0.072075] MDS: Mitigation: Clear CPU buffers [ 0.072245] Freeing SMP alternatives memory: 32K [ 0.075804] TSC deadline timer enabled [ 0.075809] smpboot: CPU0: Intel(R) Xeon(R) CPU E3-1245 v5 @ 3.50GHz (family: 0x6, model: 0x5e, stepping: 0x3) [ 0.075874] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver. [ 0.075878] ... version: 4 [ 0.075878] ... bit width: 48 [ 0.075879] ... generic registers: 4 [ 0.075879] ... value mask: 0000ffffffffffff [ 0.075879] ... max period: 00007fffffffffff [ 0.075880] ... fixed-purpose events: 3 [ 0.075880] ... event mask: 000000070000000f [ 0.075907] rcu: Hierarchical SRCU implementation. [ 0.076474] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter. [ 0.076517] smp: Bringing up secondary CPUs ... [ 0.076563] x86: Booting SMP configuration: [ 0.076564] .... node #0, CPUs: #1 #2 #3 #4 [ 0.081378] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details. [ 0.081378] TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details. [ 0.081378] #5 #6 #7 [ 0.081378] smp: Brought up 1 node, 8 CPUs [ 0.081378] smpboot: Max logical packages: 1 [ 0.081378] smpboot: Total of 8 processors activated (55998.59 BogoMIPS) [ 0.155762] node 0 initialised, 7609537 pages in 72ms [ 0.156270] devtmpfs: initialized [ 0.156270] x86/mm: Memory block size: 128MB [ 0.160353] PM: Registering ACPI NVS region [mem 0x80be5000-0x80be5fff] (4096 bytes) [ 0.160353] PM: Registering ACPI NVS region [mem 0x8b159000-0x8b82efff] (7168000 bytes) [ 0.160353] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.160353] futex hash table entries: 2048 (order: 5, 131072 bytes, linear) [ 0.160353] pinctrl core: initialized pinctrl subsystem [ 0.160353] thermal_sys: Registered thermal governor 'fair_share' [ 0.160353] thermal_sys: Registered thermal governor 'bang_bang' [ 0.160353] thermal_sys: Registered thermal governor 'step_wise' [ 0.160353] thermal_sys: Registered thermal governor 'user_space' [ 0.160353] NET: Registered protocol family 16 [ 0.160353] audit: initializing netlink subsys (disabled) [ 0.160353] audit: type=2000 audit(1591264845.112:1): state=initialized audit_enabled=0 res=1 [ 0.160353] cpuidle: using governor ladder [ 0.160353] cpuidle: using governor menu [ 0.160353] ACPI: bus type PCI registered [ 0.160353] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 [ 0.160353] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) [ 0.160353] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 [ 0.160353] PCI: Using configuration type 1 for base access [ 0.161723] ENERGY_PERF_BIAS: Set to 'normal', was 'performance' [ 0.161727] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages [ 0.161727] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages [ 0.256378] ACPI: Added _OSI(Module Device) [ 0.256378] ACPI: Added _OSI(Processor Device) [ 0.256378] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.256378] ACPI: Added _OSI(Processor Aggregator Device) [ 0.256378] ACPI: Added _OSI(Linux-Dell-Video) [ 0.256378] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) [ 0.256378] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics) [ 0.285387] ACPI: 10 ACPI AML tables successfully acquired and loaded [ 0.287173] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored [ 0.290492] ACPI: Dynamic OEM Table Load: [ 0.290496] ACPI: SSDT 0xFFFF8D5D471C8800 000738 (v02 PmRef Cpu0Ist 00003000 INTL 20160422) [ 0.291399] ACPI: \_PR_.CPU0: _OSC native thermal LVT Acked [ 0.292269] ACPI: Dynamic OEM Table Load: [ 0.292273] ACPI: SSDT 0xFFFF8D62FB315C00 0003FF (v02 PmRef Cpu0Cst 00003001 INTL 20160422) [ 0.293140] ACPI: Dynamic OEM Table Load: [ 0.293143] ACPI: SSDT 0xFFFF8D5D47338200 000115 (v02 PmRef Cpu0Hwp 00003000 INTL 20160422) [ 0.293929] ACPI: Dynamic OEM Table Load: [ 0.293931] ACPI: SSDT 0xFFFF8D5D4733BE00 0001A4 (v02 PmRef HwpLvt 00003000 INTL 20160422) [ 0.294919] ACPI: Dynamic OEM Table Load: [ 0.294924] ACPI: SSDT 0xFFFF8D648B0D6800 00065C (v02 PmRef ApIst 00003000 INTL 20160422) [ 0.295947] ACPI: Dynamic OEM Table Load: [ 0.295950] ACPI: SSDT 0xFFFF8D5D4733B000 000197 (v02 PmRef ApHwp 00003000 INTL 20160422) [ 0.296809] ACPI: Dynamic OEM Table Load: [ 0.296811] ACPI: SSDT 0xFFFF8D5D47338000 00018A (v02 PmRef ApCst 00003000 INTL 20160422) [ 0.299965] ACPI: Interpreter enabled [ 0.299995] ACPI: (supports S0 S3 S4 S5) [ 0.299995] ACPI: Using IOAPIC for interrupt routing [ 0.300040] HEST: Table parsing has been initialized. [ 0.300041] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.300687] ACPI: Enabled 6 GPEs in block 00 to 7F [ 0.302397] ACPI: Power Resource [PG00] (on) [ 0.302684] ACPI: Power Resource [PG01] (on) [ 0.302955] ACPI: Power Resource [PG02] (on) [ 0.304697] ACPI: Power Resource [WRST] (on) [ 0.304941] ACPI: Power Resource [WRST] (on) [ 0.305205] ACPI: Power Resource [WRST] (on) [ 0.305466] ACPI: Power Resource [WRST] (on) [ 0.305697] ACPI: Power Resource [WRST] (on) [ 0.305935] ACPI: Power Resource [WRST] (on) [ 0.306163] ACPI: Power Resource [WRST] (on) [ 0.306389] ACPI: Power Resource [WRST] (on) [ 0.306616] ACPI: Power Resource [WRST] (on) [ 0.306845] ACPI: Power Resource [WRST] (on) [ 0.307100] ACPI: Power Resource [WRST] (on) [ 0.307327] ACPI: Power Resource [WRST] (on) [ 0.307554] ACPI: Power Resource [WRST] (on) [ 0.307785] ACPI: Power Resource [WRST] (on) [ 0.308016] ACPI: Power Resource [WRST] (on) [ 0.308247] ACPI: Power Resource [WRST] (on) [ 0.308477] ACPI: Power Resource [WRST] (on) [ 0.309341] ACPI: Power Resource [WRST] (on) [ 0.309569] ACPI: Power Resource [WRST] (on) [ 0.309796] ACPI: Power Resource [WRST] (on) [ 0.318885] ACPI: Power Resource [FN00] (off) [ 0.318941] ACPI: Power Resource [FN01] (off) [ 0.318993] ACPI: Power Resource [FN02] (off) [ 0.319045] ACPI: Power Resource [FN03] (off) [ 0.319099] ACPI: Power Resource [FN04] (off) [ 0.319874] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe]) [ 0.319878] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] [ 0.321077] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME AER PCIeCapability LTR] [ 0.321595] PCI host bridge to bus 0000:00 [ 0.321596] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] [ 0.321597] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 0.321598] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] [ 0.321598] pci_bus 0000:00: root bus resource [mem 0x8f800000-0xdfffffff window] [ 0.321599] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window] [ 0.321600] pci_bus 0000:00: root bus resource [bus 00-fe] [ 0.321607] pci 0000:00:00.0: [8086:1918] type 00 class 0x060000 [ 0.321855] pci 0000:00:02.0: [8086:191d] type 00 class 0x030000 [ 0.321863] pci 0000:00:02.0: reg 0x10: [mem 0xdd000000-0xddffffff 64bit] [ 0.321867] pci 0000:00:02.0: reg 0x18: [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.321870] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f] [ 0.321988] pci 0000:00:08.0: [8086:1911] type 00 class 0x088000 [ 0.321997] pci 0000:00:08.0: reg 0x10: [mem 0xdf253000-0xdf253fff 64bit] [ 0.322118] pci 0000:00:14.0: [8086:a12f] type 00 class 0x0c0330 [ 0.322136] pci 0000:00:14.0: reg 0x10: [mem 0xdf230000-0xdf23ffff 64bit] [ 0.322190] pci 0000:00:14.0: PME# supported from D3hot D3cold [ 0.322340] pci 0000:00:14.2: [8086:a131] type 00 class 0x118000 [ 0.322358] pci 0000:00:14.2: reg 0x10: [mem 0xdf252000-0xdf252fff 64bit] [ 0.322529] pci 0000:00:15.0: [8086:a160] type 00 class 0x118000 [ 0.322577] pci 0000:00:15.0: reg 0x10: [mem 0xdf251000-0xdf251fff 64bit] [ 0.322829] pci 0000:00:15.1: [8086:a161] type 00 class 0x118000 [ 0.322889] pci 0000:00:15.1: reg 0x10: [mem 0xdf250000-0xdf250fff 64bit] [ 0.323125] pci 0000:00:16.0: [8086:a13a] type 00 class 0x078000 [ 0.323147] pci 0000:00:16.0: reg 0x10: [mem 0xdf24f000-0xdf24ffff 64bit] [ 0.323210] pci 0000:00:16.0: PME# supported from D3hot [ 0.323323] pci 0000:00:16.3: [8086:a13d] type 00 class 0x070002 [ 0.323336] pci 0000:00:16.3: reg 0x10: [io 0xf0a0-0xf0a7] [ 0.323342] pci 0000:00:16.3: reg 0x14: [mem 0xdf24e000-0xdf24efff] [ 0.323468] pci 0000:00:17.0: [8086:a102] type 00 class 0x010601 [ 0.323482] pci 0000:00:17.0: reg 0x10: [mem 0xdf248000-0xdf249fff] [ 0.323487] pci 0000:00:17.0: reg 0x14: [mem 0xdf24d000-0xdf24d0ff] [ 0.323493] pci 0000:00:17.0: reg 0x18: [io 0xf090-0xf097] [ 0.323498] pci 0000:00:17.0: reg 0x1c: [io 0xf080-0xf083] [ 0.323504] pci 0000:00:17.0: reg 0x20: [io 0xf060-0xf07f] [ 0.323509] pci 0000:00:17.0: reg 0x24: [mem 0xdf24c000-0xdf24c7ff] [ 0.323541] pci 0000:00:17.0: PME# supported from D3hot [ 0.323653] pci 0000:00:1b.0: [8086:a167] type 01 class 0x060400 [ 0.323722] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold [ 0.323737] pci 0000:00:1b.0: Intel SPT PCH root port ACS workaround enabled [ 0.323886] pci 0000:00:1c.0: [8086:a110] type 01 class 0x060400 [ 0.323954] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold [ 0.323969] pci 0000:00:1c.0: Intel SPT PCH root port ACS workaround enabled [ 0.324114] pci 0000:00:1d.0: [8086:a118] type 01 class 0x060400 [ 0.324169] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold [ 0.324290] pci 0000:00:1d.1: [8086:a119] type 01 class 0x060400 [ 0.324350] pci 0000:00:1d.1: PME# supported from D0 D3hot D3cold [ 0.324363] pci 0000:00:1d.1: Intel SPT PCH root port ACS workaround enabled [ 0.324485] pci 0000:00:1d.2: [8086:a11a] type 01 class 0x060400 [ 0.324544] pci 0000:00:1d.2: PME# supported from D0 D3hot D3cold [ 0.324557] pci 0000:00:1d.2: Intel SPT PCH root port ACS workaround enabled [ 0.324729] pci 0000:00:1e.0: [8086:a127] type 00 class 0x118000 [ 0.324778] pci 0000:00:1e.0: reg 0x10: [mem 0xdf24b000-0xdf24bfff 64bit] [ 0.325019] pci 0000:00:1f.0: [8086:a149] type 00 class 0x060100 [ 0.325212] pci 0000:00:1f.2: [8086:a121] type 00 class 0x058000 [ 0.325225] pci 0000:00:1f.2: reg 0x10: [mem 0xdf244000-0xdf247fff] [ 0.325368] pci 0000:00:1f.3: [8086:a170] type 00 class 0x040300 [ 0.325392] pci 0000:00:1f.3: reg 0x10: [mem 0xdf240000-0xdf243fff 64bit] [ 0.325420] pci 0000:00:1f.3: reg 0x20: [mem 0xdf220000-0xdf22ffff 64bit] [ 0.325463] pci 0000:00:1f.3: PME# supported from D3hot D3cold [ 0.325618] pci 0000:00:1f.4: [8086:a123] type 00 class 0x0c0500 [ 0.325677] pci 0000:00:1f.4: reg 0x10: [mem 0xdf24a000-0xdf24a0ff 64bit] [ 0.325746] pci 0000:00:1f.4: reg 0x20: [io 0xf040-0xf05f] [ 0.325921] pci 0000:00:1f.6: [8086:15b7] type 00 class 0x020000 [ 0.325946] pci 0000:00:1f.6: reg 0x10: [mem 0xdf200000-0xdf21ffff] [ 0.326047] pci 0000:00:1f.6: PME# supported from D0 D3hot D3cold [ 0.326187] pci 0000:00:1b.0: PCI bridge to [bus 01] [ 0.326225] pci 0000:00:1c.0: PCI bridge to [bus 02] [ 0.326267] acpiphp: Slot [1] registered [ 0.326269] pci 0000:00:1d.0: PCI bridge to [bus 03] [ 0.326340] pci 0000:04:00.0: [8086:1533] type 00 class 0x020000 [ 0.326371] pci 0000:04:00.0: reg 0x10: [mem 0xdf100000-0xdf17ffff] [ 0.326395] pci 0000:04:00.0: reg 0x18: [io 0xe000-0xe01f] [ 0.326407] pci 0000:04:00.0: reg 0x1c: [mem 0xdf180000-0xdf183fff] [ 0.326544] pci 0000:04:00.0: PME# supported from D0 D3hot D3cold [ 0.326704] pci 0000:00:1d.1: PCI bridge to [bus 04] [ 0.326706] pci 0000:00:1d.1: bridge window [io 0xe000-0xefff] [ 0.326707] pci 0000:00:1d.1: bridge window [mem 0xdf100000-0xdf1fffff] [ 0.326760] pci 0000:05:00.0: [1a03:1150] type 01 class 0x060400 [ 0.326824] pci 0000:05:00.0: enabling Extended Tags [ 0.326887] pci 0000:05:00.0: supports D1 D2 [ 0.326888] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 0.326976] pci 0000:05:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' [ 0.326984] pci 0000:00:1d.2: PCI bridge to [bus 05-06] [ 0.326986] pci 0000:00:1d.2: bridge window [io 0xd000-0xdfff] [ 0.326988] pci 0000:00:1d.2: bridge window [mem 0xde000000-0xdf0fffff] [ 0.327030] pci_bus 0000:06: extended config space not accessible [ 0.327048] pci 0000:06:00.0: [1a03:2000] type 00 class 0x030000 [ 0.327066] pci 0000:06:00.0: reg 0x10: [mem 0xde000000-0xdeffffff] [ 0.327074] pci 0000:06:00.0: reg 0x14: [mem 0xdf000000-0xdf01ffff] [ 0.327082] pci 0000:06:00.0: reg 0x18: [io 0xd000-0xd07f] [ 0.327161] pci 0000:06:00.0: supports D1 D2 [ 0.327161] pci 0000:06:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 0.327241] pci 0000:05:00.0: PCI bridge to [bus 06] [ 0.327247] pci 0000:05:00.0: bridge window [io 0xd000-0xdfff] [ 0.327250] pci 0000:05:00.0: bridge window [mem 0xde000000-0xdf0fffff] [ 0.329656] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.329656] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15) [ 0.329656] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.329656] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.329656] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.329656] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.329656] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.329656] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15) [ 0.329656] iommu: Default domain type: Translated [ 0.329656] pci 0000:00:02.0: vgaarb: setting as boot VGA device [ 0.329656] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none [ 0.329656] pci 0000:06:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none [ 0.329656] pci 0000:00:02.0: vgaarb: no bridge control possible [ 0.329656] pci 0000:06:00.0: vgaarb: bridge control possible [ 0.329656] vgaarb: loaded [ 0.329656] EDAC MC: Ver: 3.0.0 [ 0.329656] PCI: Using ACPI for IRQ routing [ 0.358681] PCI: pci_cache_line_size set to 64 bytes [ 0.358802] e820: reserve RAM buffer [mem 0x00098c00-0x0009ffff] [ 0.358803] e820: reserve RAM buffer [mem 0x80be5000-0x83ffffff] [ 0.358804] e820: reserve RAM buffer [mem 0x8ac6f000-0x8bffffff] [ 0.358804] e820: reserve RAM buffer [mem 0x8b159000-0x8bffffff] [ 0.358805] e820: reserve RAM buffer [mem 0x86e800000-0x86fffffff] [ 0.358865] NetLabel: Initializing [ 0.358865] NetLabel: domain hash size = 128 [ 0.358865] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO [ 0.358874] NetLabel: unlabeled traffic allowed by default [ 0.359255] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 [ 0.359257] hpet0: 8 comparators, 64-bit 24.000000 MHz counter [ 0.360784] clocksource: Switched to clocksource tsc-early [ 0.366604] VFS: Disk quotas dquot_6.6.0 [ 0.366614] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) [ 0.366684] AppArmor: AppArmor Filesystem Enabled [ 0.366692] pnp: PnP ACPI init [ 0.366734] system 00:00: [io 0x0a00-0x0a0f] has been reserved [ 0.366734] system 00:00: [io 0x0a10-0x0a1f] has been reserved [ 0.366734] system 00:00: [io 0x0a20-0x0a2f] has been reserved [ 0.366734] system 00:00: [io 0x0a30-0x0a3f] has been reserved [ 0.366734] system 00:00: [io 0x0a40-0x0a4f] has been reserved [ 0.366734] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.366734] pnp 00:01: [dma 0 disabled] [ 0.366734] pnp 00:01: Plug and Play ACPI device, IDs PNP0501 (active) [ 0.366734] pnp 00:02: [dma 0 disabled] [ 0.366734] pnp 00:02: Plug and Play ACPI device, IDs PNP0501 (active) [ 0.366734] system 00:03: [io 0x0680-0x069f] has been reserved [ 0.366734] system 00:03: [io 0xffff] has been reserved [ 0.366734] system 00:03: [io 0xffff] has been reserved [ 0.366734] system 00:03: [io 0xffff] has been reserved [ 0.366734] system 00:03: [io 0x1800-0x18fe] has been reserved [ 0.366734] system 00:03: [io 0x164e-0x164f] has been reserved [ 0.366734] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.366734] system 00:04: [io 0x0800-0x087f] has been reserved [ 0.366734] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.366734] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.366734] system 00:06: [io 0x1854-0x1857] has been reserved [ 0.366734] system 00:06: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) [ 0.367824] system 00:07: [mem 0xfed10000-0xfed17fff] has been reserved [ 0.367825] system 00:07: [mem 0xfed18000-0xfed18fff] has been reserved [ 0.367825] system 00:07: [mem 0xfed19000-0xfed19fff] has been reserved [ 0.367826] system 00:07: [mem 0xe0000000-0xefffffff] has been reserved [ 0.367827] system 00:07: [mem 0xfed20000-0xfed3ffff] has been reserved [ 0.367828] system 00:07: [mem 0xfed90000-0xfed93fff] could not be reserved [ 0.367829] system 00:07: [mem 0xfed45000-0xfed8ffff] has been reserved [ 0.367829] system 00:07: [mem 0xff000000-0xffffffff] has been reserved [ 0.367830] system 00:07: [mem 0xfee00000-0xfeefffff] could not be reserved [ 0.367831] system 00:07: [mem 0xdffe0000-0xdfffffff] has been reserved [ 0.367833] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.367862] system 00:08: [mem 0xfd000000-0xfdabffff] has been reserved [ 0.367863] system 00:08: [mem 0xfdad0000-0xfdadffff] has been reserved [ 0.367863] system 00:08: [mem 0xfdb00000-0xfdffffff] has been reserved [ 0.367864] system 00:08: [mem 0xfe000000-0xfe01ffff] could not be reserved [ 0.367865] system 00:08: [mem 0xfe036000-0xfe03bfff] has been reserved [ 0.367867] system 00:08: [mem 0xfe03d000-0xfe3fffff] has been reserved [ 0.367868] system 00:08: [mem 0xfe410000-0xfe7fffff] has been reserved [ 0.367869] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.368081] system 00:09: [io 0xff00-0xfffe] has been reserved [ 0.368082] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.368798] system 00:0a: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.369460] pnp: PnP ACPI: found 11 devices [ 0.374670] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns [ 0.374694] pci 0000:00:1b.0: PCI bridge to [bus 01] [ 0.374701] pci 0000:00:1c.0: PCI bridge to [bus 02] [ 0.374708] pci 0000:00:1d.0: PCI bridge to [bus 03] [ 0.374713] pci 0000:00:1d.1: PCI bridge to [bus 04] [ 0.374715] pci 0000:00:1d.1: bridge window [io 0xe000-0xefff] [ 0.374717] pci 0000:00:1d.1: bridge window [mem 0xdf100000-0xdf1fffff] [ 0.374722] pci 0000:05:00.0: PCI bridge to [bus 06] [ 0.374724] pci 0000:05:00.0: bridge window [io 0xd000-0xdfff] [ 0.374728] pci 0000:05:00.0: bridge window [mem 0xde000000-0xdf0fffff] [ 0.374737] pci 0000:00:1d.2: PCI bridge to [bus 05-06] [ 0.374738] pci 0000:00:1d.2: bridge window [io 0xd000-0xdfff] [ 0.374740] pci 0000:00:1d.2: bridge window [mem 0xde000000-0xdf0fffff] [ 0.374745] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] [ 0.374746] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] [ 0.374747] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] [ 0.374748] pci_bus 0000:00: resource 7 [mem 0x8f800000-0xdfffffff window] [ 0.374748] pci_bus 0000:00: resource 8 [mem 0xfd000000-0xfe7fffff window] [ 0.374749] pci_bus 0000:04: resource 0 [io 0xe000-0xefff] [ 0.374750] pci_bus 0000:04: resource 1 [mem 0xdf100000-0xdf1fffff] [ 0.374751] pci_bus 0000:05: resource 0 [io 0xd000-0xdfff] [ 0.374751] pci_bus 0000:05: resource 1 [mem 0xde000000-0xdf0fffff] [ 0.374752] pci_bus 0000:06: resource 0 [io 0xd000-0xdfff] [ 0.374753] pci_bus 0000:06: resource 1 [mem 0xde000000-0xdf0fffff] [ 0.374852] NET: Registered protocol family 2 [ 0.374928] tcp_listen_portaddr_hash hash table entries: 16384 (order: 6, 262144 bytes, linear) [ 0.374952] TCP established hash table entries: 262144 (order: 9, 2097152 bytes, linear) [ 0.375122] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear) [ 0.375203] TCP: Hash tables configured (established 262144 bind 65536) [ 0.375220] UDP hash table entries: 16384 (order: 7, 524288 bytes, linear) [ 0.375263] UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes, linear) [ 0.375339] NET: Registered protocol family 1 [ 0.375342] NET: Registered protocol family 44 [ 0.375348] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] [ 0.375585] PCI: CLS 64 bytes, default 64 [ 0.375607] Trying to unpack rootfs image as initramfs... [ 0.874166] Freeing initrd memory: 43536K [ 0.874200] DMAR: ACPI device "device:7d" under DMAR at fed91000 as 00:15.0 [ 0.874202] DMAR: ACPI device "device:7e" under DMAR at fed91000 as 00:15.1 [ 0.874203] DMAR: ACPI device "device:7f" under DMAR at fed91000 as 00:1e.0 [ 0.874213] DMAR: No ATSR found [ 0.874244] DMAR: dmar0: Using Queued invalidation [ 0.874246] DMAR: dmar1: Using Queued invalidation [ 0.874571] pci 0000:00:00.0: Adding to iommu group 0 [ 0.877343] pci 0000:00:02.0: Adding to iommu group 1 [ 0.877492] pci 0000:00:02.0: Using iommu direct mapping [ 0.877518] pci 0000:00:08.0: Adding to iommu group 2 [ 0.877571] pci 0000:00:14.0: Adding to iommu group 3 [ 0.877578] pci 0000:00:14.2: Adding to iommu group 3 [ 0.877616] pci 0000:00:15.0: Adding to iommu group 4 [ 0.877623] pci 0000:00:15.1: Adding to iommu group 4 [ 0.877665] pci 0000:00:16.0: Adding to iommu group 5 [ 0.877672] pci 0000:00:16.3: Adding to iommu group 5 [ 0.877704] pci 0000:00:17.0: Adding to iommu group 6 [ 0.877741] pci 0000:00:1b.0: Adding to iommu group 7 [ 0.877779] pci 0000:00:1c.0: Adding to iommu group 8 [ 0.877816] pci 0000:00:1d.0: Adding to iommu group 9 [ 0.877853] pci 0000:00:1d.1: Adding to iommu group 10 [ 0.877887] pci 0000:00:1d.2: Adding to iommu group 11 [ 0.877927] pci 0000:00:1e.0: Adding to iommu group 12 [ 0.879057] pci 0000:00:1f.0: Adding to iommu group 13 [ 0.879065] pci 0000:00:1f.2: Adding to iommu group 13 [ 0.879073] pci 0000:00:1f.3: Adding to iommu group 13 [ 0.879081] pci 0000:00:1f.4: Adding to iommu group 13 [ 0.879118] pci 0000:00:1f.6: Adding to iommu group 14 [ 0.879155] pci 0000:04:00.0: Adding to iommu group 15 [ 0.879197] pci 0000:05:00.0: Adding to iommu group 16 [ 0.879201] pci 0000:06:00.0: Adding to iommu group 16 [ 0.879322] DMAR: Intel(R) Virtualization Technology for Directed I/O [ 0.881046] Initialise system trusted keyrings [ 0.881052] Key type blacklist registered [ 0.881068] workingset: timestamp_bits=40 max_order=23 bucket_order=0 [ 0.881844] zbud: loaded [ 0.881949] Platform Keyring initialized [ 0.881950] Key type asymmetric registered [ 0.881951] Asymmetric key parser 'x509' registered [ 0.881955] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) [ 0.881977] io scheduler mq-deadline registered [ 0.882205] pcieport 0000:00:1b.0: PME: Signaling with IRQ 122 [ 0.882240] pcieport 0000:00:1b.0: AER: enabled with IRQ 122 [ 0.882395] pcieport 0000:00:1c.0: PME: Signaling with IRQ 123 [ 0.882423] pcieport 0000:00:1c.0: AER: enabled with IRQ 123 [ 0.882556] pcieport 0000:00:1d.0: PME: Signaling with IRQ 124 [ 0.882685] pcieport 0000:00:1d.1: PME: Signaling with IRQ 125 [ 0.882713] pcieport 0000:00:1d.1: AER: enabled with IRQ 125 [ 0.882842] pcieport 0000:00:1d.2: PME: Signaling with IRQ 126 [ 0.882869] pcieport 0000:00:1d.2: AER: enabled with IRQ 126 [ 0.882938] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 [ 0.882948] intel_idle: MWAIT substates: 0x142120 [ 0.882949] intel_idle: v0.4.1 model 0x5E [ 0.883190] intel_idle: lapic_timer_reliable_states 0xffffffff [ 0.884073] thermal LNXTHERM:00: registered as thermal_zone0 [ 0.884073] ACPI: Thermal Zone [TZ00] (28 C) [ 0.884156] thermal LNXTHERM:01: registered as thermal_zone1 [ 0.884156] ACPI: Thermal Zone [TZ01] (30 C) [ 0.884204] ERST: Error Record Serialization Table (ERST) support is initialized. [ 0.884205] pstore: Registered erst as persistent store backend [ 0.884247] GHES: APEI firmware first mode is enabled by APEI bit. [ 0.884315] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.884597] 00:01: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A [ 0.885709] 00:02: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A [ 0.887065] 0000:00:16.3: ttyS2 at I/O 0xf0a0 (irq = 19, base_baud = 115200) is a 16550A [ 0.887264] Linux agpgart interface v0.103 [ 0.887304] AMD-Vi: AMD IOMMUv2 driver by Joerg Roedel <jroedel at suse.de> [ 0.887304] AMD-Vi: AMD IOMMUv2 functionality not available on this system [ 0.887717] i8042: PNP: No PS/2 controller found. [ 0.887745] mousedev: PS/2 mouse device common for all mice [ 0.887775] rtc_cmos 00:05: RTC can wake from S4 [ 0.888255] rtc_cmos 00:05: registered as rtc0 [ 0.888264] rtc_cmos 00:05: alarms up to one month, y3k, 242 bytes nvram, hpet irqs [ 0.888268] intel_pstate: Intel P-state driver initializing [ 0.888916] intel_pstate: HWP enabled [ 0.889037] ledtrig-cpu: registered to indicate activity on CPUs [ 0.889161] drop_monitor: Initializing network drop monitor service [ 0.889300] NET: Registered protocol family 10 [ 0.896122] Segment Routing with IPv6 [ 0.896134] mip6: Mobile IPv6 [ 0.896134] NET: Registered protocol family 17 [ 0.896240] mpls_gso: MPLS GSO support [ 0.896919] microcode: sig=0x506e3, pf=0x2, revision=0xd6 [ 0.897087] microcode: Microcode Update Driver: v2.2. [ 0.897089] IPI shorthand broadcast: enabled [ 0.897107] sched_clock: Marking stable (894292599, 2568221)->(990520866, -93660046) [ 0.897298] registered taskstats version 1 [ 0.897299] Loading compiled-in X.509 certificates [ 0.918917] Loaded X.509 cert 'Debian Secure Boot CA: 6ccece7e4c6c0d1f6149f3dd27dfcc5cbb419ea1' [ 0.918927] Loaded X.509 cert 'Debian Secure Boot Signer: 00a7468def' [ 0.918939] zswap: loaded using pool lzo/zbud [ 0.919345] Key type ._fscrypt registered [ 0.919345] Key type .fscrypt registered [ 0.919346] Key type fscrypt-provisioning registered [ 0.919383] pstore: Using crash dump compression: deflate [ 0.919391] AppArmor: AppArmor sha1 policy hashing enabled [ 0.920358] rtc_cmos 00:05: setting system clock to 2020-06-04T10:00:46 UTC (1591264846) [ 0.921101] Freeing unused kernel image (initmem) memory: 1612K [ 0.996075] Write protecting the kernel read-only data: 16384k [ 0.997114] Freeing unused kernel image (text/rodata gap) memory: 2044K [ 0.997307] Freeing unused kernel image (rodata/data gap) memory: 120K [ 1.056373] x86/mm: Checked W+X mappings: passed, no W+X pages found. [ 1.056373] x86/mm: Checking user space page tables [ 1.083217] x86/mm: Checked W+X mappings: passed, no W+X pages found. [ 1.083218] Run /init as init process [ 1.083218] with arguments: [ 1.083219] /init [ 1.083219] with environment: [ 1.083219] HOME=/ [ 1.083220] TERM=linux [ 1.083220] BOOT_IMAGE=/boot/vmlinuz-5.6.0-2-amd64 [ 1.139558] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input0 [ 1.139580] ACPI: Sleep Button [SLPB] [ 1.139624] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 [ 1.139637] ACPI: Power Button [PWRB] [ 1.139662] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 [ 1.139689] ACPI: Power Button [PWRF] [ 1.151483] pps_core: LinuxPPS API ver. 1 registered [ 1.151484] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti at linux.it> [ 1.152700] PTP clock support registered [ 1.153198] dca service started, version 1.12.1 [ 1.158304] i801_smbus 0000:00:1f.4: SPD Write Disable is set [ 1.158344] i801_smbus 0000:00:1f.4: SMBus using PCI interrupt [ 1.158466] intel-lpss 0000:00:15.0: enabling device (0000 -> 0002) [ 1.158710] idma64 idma64.0: Found Intel integrated DMA 64-bit [ 1.161029] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.6.0-k [ 1.161029] igb: Copyright (c) 2007-2014 Intel Corporation. [ 1.164440] ACPI: bus type USB registered [ 1.164455] usbcore: registered new interface driver usbfs [ 1.164462] usbcore: registered new interface driver hub [ 1.164488] usbcore: registered new device driver usb [ 1.168522] intel-lpss 0000:00:15.1: enabling device (0000 -> 0002) [ 1.168762] idma64 idma64.1: Found Intel integrated DMA 64-bit [ 1.173453] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k [ 1.173454] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. [ 1.174603] intel-lpss 0000:00:1e.0: enabling device (0000 -> 0002) [ 1.174626] e1000e 0000:00:1f.6: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode [ 1.174879] idma64 idma64.2: Found Intel integrated DMA 64-bit [ 1.175017] SCSI subsystem initialized [ 1.175935] dw-apb-uart.2: ttyS3 at MMIO 0xdf24b000 (irq = 20, base_baud = 115200) is a 16550A [ 1.185340] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 1.185347] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1 [ 1.186451] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x0000000001109810 [ 1.187465] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported [ 1.187661] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.06 [ 1.187663] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.187664] usb usb1: Product: xHCI Host Controller [ 1.187665] usb usb1: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd [ 1.187666] usb usb1: SerialNumber: 0000:00:14.0 [ 1.187773] hub 1-0:1.0: USB hub found [ 1.187790] hub 1-0:1.0: 16 ports detected [ 1.187842] libata version 3.00 loaded. [ 1.191212] ahci 0000:00:17.0: version 3.0 [ 1.192724] ast 0000:06:00.0: enabling device (0140 -> 0143) [ 1.199510] pps pps0: new PPS source ptp0 [ 1.199542] igb 0000:04:00.0: added PHC on eth0 [ 1.199543] igb 0000:04:00.0: Intel(R) Gigabit Ethernet Network Connection [ 1.199545] igb 0000:04:00.0: eth0: (PCIe:2.5Gb/s:Width x1) 0c:c4:7a:cf:6c:d7 [ 1.199618] igb 0000:04:00.0: eth0: PBA No: 010B00-000 [ 1.199619] igb 0000:04:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s) [ 1.200298] igb 0000:04:00.0 eno2: renamed from eth0 [ 1.209686] [drm] Using P2A bridge for configuration [ 1.209701] [drm] AST 2400 detected [ 1.209713] [drm] Analog VGA only [ 1.209731] [drm] dram MCLK=408 Mhz type=1 bus_width=16 size=01000000 [ 1.209763] [TTM] Zone kernel: Available graphics memory: 16423934 KiB [ 1.209765] ahci 0000:00:17.0: AHCI 0001.0301 32 slots 4 ports 6 Gbps 0xf impl SATA mode [ 1.209765] [TTM] Zone dma32: Available graphics memory: 2097152 KiB [ 1.209766] ahci 0000:00:17.0: flags: 64bit ncq sntf led clo only pio slum part ems deso sadm sds apst [ 1.209767] [TTM] Initializing pool allocator [ 1.209775] [TTM] Initializing DMA pool allocator [ 1.210535] [drm:drm_client_modeset_probe [drm]] [ 1.210544] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] [ 1.210551] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] status updated from unknown to connected [ 1.214089] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter AST i2c bit bus [ 1.214125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "848x480": 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 1.214137] [drm:drm_mode_prune_invalid [drm]] Not using 848x480 mode: NOMODE [ 1.214145] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] probed modes : [ 1.214158] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.214170] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.214182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 1.214195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.214209] [drm:drm_client_modeset_probe [drm]] connector 35 enabled? yes [ 1.214223] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 1.214236] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 35 [ 1.214248] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 35 0 [ 1.214261] [drm:drm_client_modeset_probe [drm]] found mode 1024x768 [ 1.214273] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 1920x2048 config [ 1.214286] [drm:drm_client_modeset_probe [drm]] desired mode 1024x768 set on crtc 33 (0,0) [ 1.214294] ast 0000:06:00.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane [ 1.214302] ast 0000:06:00.0: [drm:drm_fb_helper_generic_probe [drm_kms_helper]] surface width(1024), height(768) and bpp(32) [ 1.214322] [drm:drm_mode_addfb2 [drm]] [FB:36] [ 1.216083] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 [ 1.216098] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000706e661a state to 00000000d3c00277 [ 1.216111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000b376c70b state to 00000000d3c00277 [ 1.216125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000b376c70b [ 1.216139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 [ 1.216153] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1024x768] for [CRTC:33:crtc-0] state 000000000505a613 [ 1.216166] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane-0] state 00000000706e661a to [CRTC:33:crtc-0] [ 1.216179] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000706e661a [ 1.216192] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.216205] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000007c015743 state to 00000000d3c00277 [ 1.216219] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000007c015743 to [CRTC:33:crtc-0] [ 1.216231] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 [ 1.216240] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] mode changed [ 1.216246] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] enable changed [ 1.216252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] active changed [ 1.216258] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 1.216265] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] using [ENCODER:34:DAC-34] on [CRTC:33:crtc-0] [ 1.216271] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] needs all connectors, enable: y, active: y [ 1.216284] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.216296] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.216310] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 [ 1.317254] [drm:drm_atomic_helper_commit_modeset_disables [drm_kms_helper]] modeset on [ENCODER:34:DAC-34] [ 1.317708] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [CRTC:33:crtc-0] [ 1.321530] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [ENCODER:34:DAC-34] [ 1.321546] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 [ 1.321559] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 [ 1.321591] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 [ 1.321604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000009f032e5a state to 00000000d3c00277 [ 1.321616] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000005efad0e6 state to 00000000d3c00277 [ 1.321629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000033f48d87 state to 00000000d3c00277 [ 1.321642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000033f48d87 [ 1.321656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000009f032e5a [ 1.321669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.321682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000004014674f state to 00000000d3c00277 [ 1.321695] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [NOCRTC] [ 1.321708] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [CRTC:33:crtc-0] [ 1.321720] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 [ 1.321728] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 1.321734] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 1.321747] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 [ 1.321805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 [ 1.321818] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 [ 1.324095] e1000e 0000:00:1f.6 0000:00:1f.6 (uninitialized): registered PHC clock [ 1.324820] Console: switching to colour frame buffer device 128x48 [ 1.341554] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 [ 1.341567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000f7eff311 state to 00000000d3c00277 [ 1.341579] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 [ 1.341591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000d2da0efa state to 00000000d3c00277 [ 1.341605] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000d2da0efa [ 1.341619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000f7eff311 [ 1.341631] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.341644] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000cebac407 state to 00000000d3c00277 [ 1.341657] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [NOCRTC] [ 1.341670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [CRTC:33:crtc-0] [ 1.341682] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 [ 1.341690] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 1.341696] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 1.341709] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 [ 1.341749] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 [ 1.341761] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 [ 1.344652] ast 0000:06:00.0: fb0: astdrmfb frame buffer device [ 1.366247] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 1.366250] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 [ 1.366253] xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed [ 1.366292] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.06 [ 1.366293] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.366294] usb usb2: Product: xHCI Host Controller [ 1.366295] usb usb2: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd [ 1.366296] usb usb2: SerialNumber: 0000:00:14.0 [ 1.366371] scsi host0: ahci [ 1.366512] hub 2-0:1.0: USB hub found [ 1.366540] hub 2-0:1.0: 10 ports detected [ 1.366542] scsi host1: ahci [ 1.366632] scsi host2: ahci [ 1.366704] scsi host3: ahci [ 1.366744] ata1: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c100 irq 134 [ 1.366746] ata2: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c180 irq 134 [ 1.366747] ata3: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c200 irq 134 [ 1.366748] ata4: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c280 irq 134 [ 1.367439] usb: port power management may be unreliable [ 1.390078] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 1024K [ 1.390116] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]] enable_guc=0 (guc:no submission:no huc:no) [ 1.390147] [drm:i915_gem_init_early [i915]] fake context support initialized [ 1.390174] i915 0000:00:02.0: [drm:intel_pch_type [i915]] Found SunrisePoint PCH [ 1.390207] [drm:intel_power_domains_init [i915]] Allowed DC state mask 02 [ 1.390244] i915 0000:00:02.0: [drm:intel_uncore_init_mmio [i915]] unclaimed mmio detected on uncore init, clearing [ 1.390619] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M [ 1.390645] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M [ 1.390669] [drm:i915_ggtt_probe_hw [i915]] DSM size = 32M [ 1.390670] i915 0000:00:02.0: VT-d active for gfx access [ 1.390671] i915 0000:00:02.0: vgaarb: deactivate vga console [ 1.390754] [drm:init_stolen [i915]] GEN6_STOLEN_RESERVED = 8f700047 [ 1.390788] [drm:init_stolen [i915]] Memory reserved for graphics device: 32768K, usable: 31744K [ 1.390818] [drm:intel_gt_init_workarounds [i915]] Initialized 4 GT workarounds on global [ 1.390868] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params [ 1.390899] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8b82a018 [ 1.390933] [drm:intel_opregion_setup [i915]] ACPI OpRegion version 2.0.0 [ 1.390962] [drm:intel_opregion_setup [i915]] Public ACPI methods supported [ 1.390989] [drm:intel_opregion_setup [i915]] SWSCI supported [ 1.392097] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483 [ 1.392125] [drm:intel_opregion_setup [i915]] ASLE supported [ 1.392152] [drm:intel_opregion_setup [i915]] ASLE extension supported [ 1.392179] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4) [ 1.392203] [drm:i915_driver_probe [i915]] DRAM type: DDR4 [ 1.392227] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no [ 1.392249] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no [ 1.392271] [drm:skl_dram_get_channel_info [i915]] CH0 ranks: 2, 16Gb DIMMs: no [ 1.392292] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no [ 1.392313] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no [ 1.392332] [drm:skl_dram_get_channel_info [i915]] CH1 ranks: 2, 16Gb DIMMs: no [ 1.392352] [drm:i915_driver_probe [i915]] Memory configuration is symmetric? yes [ 1.392371] [drm:i915_driver_probe [i915]] DRAM bandwidth: 34133344 kBps, channels: 2 [ 1.392391] [drm:i915_driver_probe [i915]] DRAM ranks: 2, 16Gb DIMMs: no [ 1.392391] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 1.392392] [drm] Driver supports precise vblank timestamp query. [ 1.392424] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz [ 1.392456] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE ", BDB version 205 [ 1.392487] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 [ 1.392517] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 [ 1.392547] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68d6 [ 1.392575] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 [ 1.392604] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 [ 1.392632] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68c6 [ 1.392985] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0) [ 1.393028] [drm:intel_bios_init [i915]] Panel type: 2 (VBT) [ 1.393056] [drm:intel_bios_init [i915]] DRRS supported mode is static [ 1.393085] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT legacy lfp table: [ 1.393098] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa [ 1.393126] [drm:intel_bios_init [i915]] VBT initial LVDS value 300 [ 1.393154] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0 [ 1.393181] [drm:intel_bios_init [i915]] DRRS State Enabled:1 [ 1.393209] [drm:intel_bios_init [i915]] Skipping SDVO device mapping [ 1.393237] [drm:intel_bios_init [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393264] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8 [ 1.393292] [drm:intel_bios_init [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393318] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8 [ 1.393346] [drm:intel_bios_init [i915]] Port D VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393373] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8 [ 1.393400] [drm:intel_bios_init [i915]] Port E VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393427] [drm:intel_bios_init [i915]] VBT HDMI level shift for port E: 0 [ 1.393534] [drm:intel_dsm_detect [i915]] no _DSM method for intel device [ 1.393577] [drm:intel_power_domains_init_hw [i915]] rawclk rate: 24000 kHz [ 1.393610] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 [ 1.393643] [drm:intel_power_well_enable [i915]] enabling power well 1 [ 1.393675] [drm:intel_power_well_enable [i915]] enabling MISC IO power well [ 1.393708] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 [ 1.393740] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz [ 1.393770] [drm:intel_cdclk_init [i915]] Max dotclock rate: 675000 kHz [ 1.393813] [drm:intel_power_well_enable [i915]] enabling always-on [ 1.393843] [drm:intel_power_well_enable [i915]] enabling DC off [ 1.393873] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 [ 1.393906] [drm:intel_power_well_enable [i915]] enabling power well 2 [ 1.393909] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=io+mem [ 1.393964] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well [ 1.394014] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 1.394042] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well [ 1.394069] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well [ 1.394113] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_27.bin [ 1.394155] i915 0000:00:02.0: firmware: direct-loading firmware i915/skl_dmc_ver1_27.bin [ 1.394459] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_27.bin (v1.27) [ 1.394625] [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled [ 1.394695] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 [ 1.394722] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec) [ 1.394745] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec) [ 1.394767] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec) [ 1.394788] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec) [ 1.394808] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec) [ 1.394828] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec) [ 1.394848] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec) [ 1.394867] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec) [ 1.394988] [drm:intel_modeset_init [i915]] 3 display pipes available. [ 1.395056] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 [ 1.395385] [drm:intel_modeset_init [i915]] VBT says port A is not DVI/HDMI/DP compatible, respect it [ 1.395421] [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (VBT) [ 1.395451] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:94:DDI B] [ 1.395488] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:94:DDI B] [ 1.395516] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT) [ 1.395550] [drm:intel_bios_port_aux_ch [i915]] using AUX C for port C (VBT) [ 1.395578] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:109:DDI C] [ 1.395609] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:109:DDI C] [ 1.395636] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT) [ 1.395669] [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT) [ 1.395697] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:119:DDI D] [ 1.395727] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:119:DDI D] [ 1.395754] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT) [ 1.395816] [drm:intel_bios_port_aux_ch [i915]] using AUX A for port E (VBT) [ 1.395862] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:129:DDI E] [ 1.395917] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:51:pipe A] hw state readout: enabled [ 1.395960] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:72:pipe B] hw state readout: disabled [ 1.396018] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:93:pipe C] hw state readout: disabled [ 1.396064] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] hw state readout: disabled, pipe A [ 1.396065] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 0c:c4:7a:cf:6c:d6 [ 1.396066] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection [ 1.396107] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] hw state readout: disabled, pipe A [ 1.396162] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] hw state readout: disabled, pipe A [ 1.396213] e1000e 0000:00:1f.6 eth0: MAC: 12, PHY: 12, PBA No: 010BFF-0FF [ 1.396274] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] hw state readout: disabled, pipe B [ 1.396309] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] hw state readout: disabled, pipe B [ 1.396355] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] hw state readout: disabled, pipe B [ 1.396437] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] hw state readout: disabled, pipe C [ 1.396511] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] hw state readout: disabled, pipe C [ 1.396559] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] hw state readout: disabled, pipe C [ 1.396597] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1 [ 1.396641] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000001, on 1 [ 1.396695] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0 [ 1.396736] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0 [ 1.396777] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:94:DDI B] hw state readout: disabled, pipe A [ 1.396820] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:96:DP-MST A] hw state readout: disabled, pipe A [ 1.396861] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:97:DP-MST B] hw state readout: disabled, pipe B [ 1.396907] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:98:DP-MST C] hw state readout: disabled, pipe C [ 1.396908] e1000e 0000:00:1f.6 eno1: renamed from eth0 [ 1.396988] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:109:DDI C] hw state readout: enabled, pipe A [ 1.397033] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:111:DP-MST A] hw state readout: disabled, pipe A [ 1.397083] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:112:DP-MST B] hw state readout: disabled, pipe B [ 1.397134] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:113:DP-MST C] hw state readout: disabled, pipe C [ 1.397184] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:119:DDI D] hw state readout: disabled, pipe A [ 1.397234] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:121:DP-MST A] hw state readout: disabled, pipe A [ 1.397284] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:122:DP-MST B] hw state readout: disabled, pipe B [ 1.397333] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:123:DP-MST C] hw state readout: disabled, pipe C [ 1.397383] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:129:DDI E] hw state readout: disabled, pipe A [ 1.397433] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:95:DP-1] hw state readout: disabled [ 1.397484] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:104:HDMI-A-1] hw state readout: disabled [ 1.397536] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:110:DP-2] hw state readout: enabled [ 1.397588] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:116:HDMI-A-2] hw state readout: disabled [ 1.397638] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:120:DP-3] hw state readout: disabled [ 1.397688] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:126:HDMI-A-3] hw state readout: disabled [ 1.397737] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:130:DP-4] hw state readout: disabled [ 1.397764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 0000000016992e5d [ 1.397814] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] min_cdclk 0 kHz [ 1.397864] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] min_cdclk 0 kHz [ 1.397913] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] min_cdclk 0 kHz [ 1.397964] [drm:intel_modeset_setup_hw_state [i915]] pipe A data rate 0 num active planes 0 [ 1.398014] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] min_cdclk 0 kHz [ 1.398063] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] min_cdclk 0 kHz [ 1.398112] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] min_cdclk 0 kHz [ 1.398161] [drm:intel_modeset_setup_hw_state [i915]] pipe B data rate 0 num active planes 0 [ 1.398211] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] min_cdclk 0 kHz [ 1.398259] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] min_cdclk 0 kHz [ 1.398308] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] min_cdclk 0 kHz [ 1.398357] [drm:intel_modeset_setup_hw_state [i915]] pipe C data rate 0 num active planes 0 [ 1.398413] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [setup_hw_state] [ 1.398465] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB [ 1.398516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 1.398568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 517734, link_n: 524288, tu: 64 [ 1.398618] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0 [ 1.398667] [drm:intel_dump_pipe_config [i915]] requested mode: [ 1.398685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 720 3902 3950 4000 400 2163 2168 2222 0x40 0x9 [ 1.398735] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 1.398752] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 3840 3902 3950 4000 2160 2163 2168 2222 0x40 0x9 [ 1.398803] [drm:intel_dump_pipe_config [i915]] crtc timings: 533249 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x40 flags: 0x9 [ 1.398853] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 720x400, pixel rate 533249 [ 1.398903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 [ 1.398952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0f000870, enabled, force thru: no [ 1.399001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 1.399051] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 1.399100] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 [ 1.399149] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> [ 1.399199] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: no [setup_hw_state] [ 1.399248] [drm:intel_dump_pipe_config [i915]] [CRTC:93:pipe C] enable: no [setup_hw_state] [ 1.399299] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling [ 1.399340] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff7e1cca [ 1.399359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000197e100e state to 00000000ff7e1cca [ 1.399376] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000ff7e1cca [ 1.399393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000aef36d99 state to 00000000ff7e1cca [ 1.399410] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000069886caf state to 00000000ff7e1cca [ 1.399426] [drm:drm_atomic_check_only [drm]] checking 00000000ff7e1cca [ 1.399485] [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:51 [ 1.399504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002ca0145a state to 00000000ff7e1cca [ 1.399520] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a93965e7 state to 00000000ff7e1cca [ 1.399536] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008fa1e3fc state to 00000000ff7e1cca [ 1.399552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae2843ea state to 00000000ff7e1cca [ 1.399567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000afe69d21 state to 00000000ff7e1cca [ 1.399582] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a4be912 state to 00000000ff7e1cca [ 1.399597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002017bf88 state to 00000000ff7e1cca [ 1.399612] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000977f527e state to 00000000ff7e1cca [ 1.399627] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000059814b3a state to 00000000ff7e1cca [ 1.399679] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 [ 1.399727] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.399773] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.399867] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.399911] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.399954] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.399997] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400039] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400082] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400123] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400165] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400206] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400247] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400288] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400329] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400370] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400411] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400451] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400492] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400533] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400573] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400613] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400654] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400735] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400775] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400816] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400857] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400897] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400936] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400977] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401017] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401057] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401096] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.401137] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401177] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401217] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401236] [drm:drm_atomic_commit [drm]] committing 00000000ff7e1cca [ 1.403979] [drm] Initialized ast 0.1.0 20120228 for 0000:06:00.0 on minor 0 [ 1.417469] [drm:i915_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000] [ 1.419056] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff7e1cca [ 1.419076] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff7e1cca [ 1.419161] [drm:intel_engine_init_workarounds [i915]] Initialized 5 engine workarounds on rcs'0 [ 1.419213] [drm:intel_engine_init_whitelist [i915]] Initialized 5 whitelist workarounds on rcs'0 [ 1.419264] [drm:intel_engine_init_ctx_wa [i915]] Initialized 12 context workarounds on rcs'0 [ 1.420147] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping [ 1.420202] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping [ 1.420253] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping [ 1.420305] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config [ 1.420418] [drm:intel_engines_driver_register [i915]] renamed rcs'0 to rcs0 [ 1.420466] [drm:intel_engines_driver_register [i915]] renamed bcs'0 to bcs0 [ 1.420513] [drm:intel_engines_driver_register [i915]] renamed vcs'0 to vcs0 [ 1.420558] [drm:intel_engines_driver_register [i915]] renamed vecs'0 to vecs0 [ 1.421101] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card1-DP-1 [ 1.421269] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card1-DP-2 [ 1.421470] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card1-DP-3 [ 1.421665] [drm:intel_dp_connector_register [i915]] registering DPDDC-E bus for card1-DP-4 [ 1.421746] [drm] Initialized i915 1.6.0 20200114 for 0000:00:02.0 on minor 1 [ 1.421881] [drm:intel_opregion_resume [i915]] 7 outputs detected [ 1.424122] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 1.424463] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3 [ 1.424632] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well [ 1.424650] [drm:drm_client_modeset_probe [drm]] [ 1.424733] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 1.424743] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 1.424798] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 1.424851] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well [ 1.424855] i915 device info: pciid=0x191d rev=0x06 platform=SKYLAKE (subplatform=0x0) gen=9 [ 1.424857] i915 device info: engines: 47 [ 1.424857] i915 device info: gen: 9 [ 1.424858] i915 device info: gt: 2 [ 1.424859] i915 device info: iommu: enabled [ 1.424860] i915 device info: memory-regions: 5 [ 1.424861] i915 device info: page-sizes: 11000 [ 1.424861] i915 device info: platform: SKYLAKE [ 1.424869] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] status updated from unknown to disconnected [ 1.424869] i915 device info: ppgtt-size: 48 [ 1.424870] i915 device info: ppgtt-type: 2 [ 1.424871] i915 device info: is_mobile: no [ 1.424872] i915 device info: is_lp: no [ 1.424873] i915 device info: require_force_probe: no [ 1.424879] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 1.424880] i915 device info: is_dgfx: no [ 1.424900] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 1.424901] i915 device info: has_64bit_reloc: yes [ 1.424902] i915 device info: gpu_reset_clobbers_display: no [ 1.424903] i915 device info: has_reset_engine: yes [ 1.424904] i915 device info: has_fpga_dbg: yes [ 1.424905] i915 device info: has_global_mocs: no [ 1.424919] i915 device info: has_gt_uc: yes [ 1.424920] i915 device info: has_l3_dpf: no [ 1.424921] i915 device info: has_llc: yes [ 1.424922] i915 device info: has_logical_ring_contexts: yes [ 1.424923] i915 device info: has_logical_ring_elsq: no [ 1.424959] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 1.424960] i915 device info: has_logical_ring_preemption: yes [ 1.424961] i915 device info: has_pooled_eu: no [ 1.424962] i915 device info: has_rc6: yes [ 1.424963] i915 device info: has_rc6p: no [ 1.424963] i915 device info: has_rps: yes [ 1.424964] i915 device info: has_runtime_pm: yes [ 1.424965] i915 device info: has_snoop: no [ 1.424966] i915 device info: has_coherent_ggtt: yes [ 1.424967] i915 device info: unfenced_needs_alignment: no [ 1.424968] i915 device info: hws_needs_physical: no [ 1.424969] i915 device info: cursor_needs_physical: no [ 1.424970] i915 device info: has_csr: yes [ 1.424970] i915 device info: has_ddi: yes [ 1.424971] i915 device info: has_dp_mst: yes [ 1.424972] i915 device info: has_dsb: no [ 1.424973] i915 device info: has_dsc: no [ 1.424974] i915 device info: has_fbc: no [ 1.424974] i915 device info: has_gmch: no [ 1.424975] i915 device info: has_hdcp: yes [ 1.424976] i915 device info: has_hotplug: yes [ 1.424977] i915 device info: has_ipc: yes [ 1.424978] i915 device info: has_modular_fia: no [ 1.424979] i915 device info: has_overlay: no [ 1.424980] i915 device info: has_psr: yes [ 1.424981] i915 device info: overlay_needs_physical: no [ 1.424981] i915 device info: supports_tv: no [ 1.424982] i915 device info: slice total: 1, mask=0001 [ 1.424983] i915 device info: subslice total: 3 [ 1.424985] i915 device info: slice0: 3 subslices, mask=00000007 [ 1.424986] i915 device info: slice1: 0 subslices, mask=00000000 [ 1.424987] i915 device info: slice2: 0 subslices, mask=00000000 [ 1.424987] i915 device info: EU total: 24 [ 1.424988] i915 device info: EU per subslice: 8 [ 1.424989] i915 device info: has slice power gating: no [ 1.424990] i915 device info: has subslice power gating: no [ 1.424991] i915 device info: has EU power gating: yes [ 1.424992] i915 device info: CS timestamp frequency: 12000 kHz [ 1.425215] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.425265] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.425502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.425525] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 1.425552] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 1.425579] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 1.428627] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 1.428673] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 1.428929] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.428956] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.429243] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.429262] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 1.429267] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] status updated from unknown to disconnected [ 1.429271] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 1.429275] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 1.429304] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 1.429716] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 1.430070] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 1.431595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 1.431624] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 1.431652] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 1.431941] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 1.437548] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 1.438071] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] status updated from unknown to connected [ 1.438083] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.438095] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 1.438105] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 1.438114] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.438303] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.438311] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.438318] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.438325] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.438333] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438339] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438346] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438353] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438360] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438366] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438373] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438379] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438387] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 1.438394] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.438401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 1.438408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 1.438414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 1.438421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 1.438428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.438434] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.438441] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.438448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.438454] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 1.438461] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 1.438468] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.438475] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.438481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 1.438488] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 1.438495] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.438501] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.438508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.438515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.438521] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.438528] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.438535] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 1.438541] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.438548] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.438555] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.438562] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.438568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.438575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.438582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438588] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438595] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438602] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.438615] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 1.438621] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.438628] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.438635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.438639] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 1.438670] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 1.438979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.439008] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.439309] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.439332] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 1.439360] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 1.439388] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 1.442034] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 1.442060] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 1.442363] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.442389] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.442674] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.442693] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 1.442697] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] status updated from unknown to disconnected [ 1.442701] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 1.442704] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 1.442731] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 1.443143] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 1.443498] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 1.445026] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 1.445055] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 1.445083] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 1.445371] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 1.450984] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 1.451505] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] status updated from unknown to connected [ 1.451514] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.451523] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 1.451530] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 1.451537] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.451717] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.451724] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.451732] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.451738] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.451746] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451752] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451760] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451772] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451779] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451785] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451792] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451798] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451806] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 1.451813] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.451832] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 1.451839] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 1.451845] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 1.451851] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 1.451858] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.451864] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.451870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.451877] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.451883] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 1.451890] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 1.451896] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.451902] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.451909] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 1.451915] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 1.451921] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.451928] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.451934] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.451940] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.451947] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.451953] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.451959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 1.451966] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.451972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.451978] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.451985] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.451991] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.451997] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.452004] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452010] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452016] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452023] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452029] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.452035] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 1.452042] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.452048] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.452054] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.452058] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 1.452153] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 1.452459] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 1.452487] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 1.452774] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 1.452796] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 1.452823] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 1.452849] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 1.455460] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 1.455486] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 1.455821] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 1.455849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 1.456135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 1.456153] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 1.456158] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] status updated from unknown to disconnected [ 1.456161] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 1.456165] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 1.456192] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 1.456202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] status updated from unknown to disconnected [ 1.456205] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 1.456214] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no [ 1.456223] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no [ 1.456230] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes [ 1.456237] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no [ 1.456244] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes [ 1.456250] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no [ 1.456257] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no [ 1.456264] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 1.456271] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 [ 1.456278] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 [ 1.456285] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 1.456291] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 [ 1.456297] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 [ 1.456304] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 1.456310] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 16384x16384 config [ 1.456319] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) [ 1.456325] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) [ 1.456331] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane [ 1.456335] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 1 primary plane [ 1.456339] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 2 primary plane [ 1.456368] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one [ 1.461444] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000 [ 1.461492] fbcon: i915drmfb (fb1) is primary device [ 1.461493] fbcon: Remapping primary device, fb1, to tty 1-63 [ 1.461508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 1.461518] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002dfe43fd state to 00000000fc0cb429 [ 1.461526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000000bf01569 state to 00000000fc0cb429 [ 1.461535] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000000bf01569 [ 1.461543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ab6fdf3f state to 00000000fc0cb429 [ 1.461550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ab6fdf3f [ 1.461558] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d93e8df3 state to 00000000fc0cb429 [ 1.461566] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000015cf0577 state to 00000000fc0cb429 [ 1.461573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000015cf0577 [ 1.461580] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003292b89f state to 00000000fc0cb429 [ 1.461588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003292b89f [ 1.461595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f4491376 state to 00000000fc0cb429 [ 1.461602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e2798a03 state to 00000000fc0cb429 [ 1.461609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e2798a03 [ 1.461616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007f2e9b45 state to 00000000fc0cb429 [ 1.461624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007f2e9b45 [ 1.461632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 [ 1.461640] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000de3ff82c [ 1.461648] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane 1A] state 000000002dfe43fd to [CRTC:51:pipe A] [ 1.461655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002dfe43fd [ 1.461662] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 1.461670] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034523972 state to 00000000fc0cb429 [ 1.461678] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [NOCRTC] [ 1.461685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [CRTC:51:pipe A] [ 1.461693] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 00000000fc0cb429 [ 1.461700] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 00000000dd2a82ac [ 1.461707] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:52:plane 1B] state 00000000d93e8df3 to [CRTC:72:pipe B] [ 1.461714] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d93e8df3 [ 1.461721] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 1.461730] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000de1711cf state to 00000000fc0cb429 [ 1.461736] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000de1711cf to [CRTC:72:pipe B] [ 1.461744] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e46349dc state to 00000000fc0cb429 [ 1.461751] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e46349dc [ 1.461758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f4491376 [ 1.461765] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 1.461772] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 1.461779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] mode changed [ 1.461783] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] mode changed [ 1.461786] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] enable changed [ 1.461790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] active changed [ 1.461795] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.461798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.461802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.461805] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] using [ENCODER:119:DDI D] on [CRTC:72:pipe B] [ 1.461808] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] needs all connectors, enable: y, active: y [ 1.461816] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 1.461823] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000fc0cb429 [ 1.461827] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] needs all connectors, enable: y, active: y [ 1.461834] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 1.461841] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:72:pipe B] to 00000000fc0cb429 [ 1.461874] [drm:intel_atomic_check [i915]] [CONNECTOR:110:DP-2] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 [ 1.461911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz [ 1.461941] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 [ 1.461968] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 [ 1.461996] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 [ 1.462030] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 [ 1.462061] [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in has_audio unable to verify whether state matches exactly, forcing modeset (expected no, found yes) [ 1.462091] [drm:intel_atomic_check [i915]] [CONNECTOR:120:DP-3] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 [ 1.462124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz [ 1.462151] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 [ 1.462178] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 [ 1.462204] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 [ 1.462236] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 [ 1.462265] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in lane_count (expected 0, found 4) [ 1.462294] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in dp_m_n (expected tu 0 gmch 0/0 link 0/0, or tu 0 gmch 0/0 link 0/0, found tu 64, gmch 6212812/8388608 link 1035468/1048576) [ 1.462321] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_types (expected 0x00000000, found 0x00000080) [ 1.462349] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 3840) [ 1.462376] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 4000) [ 1.462402] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 3840) [ 1.462429] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 4000) [ 1.462455] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 3902) [ 1.462481] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 3950) [ 1.462507] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 2160) [ 1.462533] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 2222) [ 1.462559] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 2160) [ 1.462584] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 2222) [ 1.462610] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 2163) [ 1.462636] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 2168) [ 1.462662] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pixel_multiplier (expected 0, found 1) [ 1.462688] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_format (expected 0, found 1) [ 1.462714] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in has_audio (expected no, found yes) [ 1.462740] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (1) (expected 0, found 1) [ 1.462766] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8) [ 1.462792] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pipe_bpp (expected 0, found 24) [ 1.462818] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 533250) [ 1.462843] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in port_clock (expected 0, found 540000) [ 1.462875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 1.462904] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 0 -> 1, off 0, on 1, ms 1 [ 1.462933] [drm:intel_modeset_calc_cdclk [i915]] Modeset required for cdclk change [ 1.462960] [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 1.462986] [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 2, actual 2 [ 1.463015] [drm:intel_find_shared_dpll [i915]] [CRTC:51:pipe A] allocated DPLL 1 [ 1.463043] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe A [ 1.463071] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 [ 1.463099] [drm:intel_find_shared_dpll [i915]] [CRTC:72:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 1) [ 1.463126] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe B [ 1.463157] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 0) -> ( 0 - 401), size 0 -> 401 [ 1.463181] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 847 - 892) -> ( 401 - 446), size 45 -> 45 [ 1.463204] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm [ 1.463227] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 [ 1.463249] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 [ 1.463271] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 [ 1.463292] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] ddb ( 0 - 0) -> ( 446 - 847), size 0 -> 401 [ 1.463312] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 [ 1.463332] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm [ 1.463353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 [ 1.463373] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 [ 1.463392] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 [ 1.463423] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [modeset] [ 1.463453] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB [ 1.463482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 1.463510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 [ 1.463537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 [ 1.463564] [drm:intel_dump_pipe_config [i915]] requested mode: [ 1.463573] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.463600] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 1.463608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.463636] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 1.463662] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 1.463689] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 1.463715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no [ 1.463741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 1.463768] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 1.463831] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 [ 1.463857] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> [ 1.463883] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes [ 1.463909] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 [ 1.463935] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 [ 1.463961] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no [ 1.463987] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor A] fb: [NOFB], visible: no [ 1.464013] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [modeset] [ 1.464039] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB [ 1.464064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 1.464090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 [ 1.464115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 [ 1.464140] [drm:intel_dump_pipe_config [i915]] requested mode: [ 1.464148] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.464174] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 1.464182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.464209] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 1.464234] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 1.464260] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 1.464286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no [ 1.464311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 1.464336] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 1.464362] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 [ 1.464387] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> [ 1.464414] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes [ 1.464439] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 [ 1.464465] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 [ 1.464491] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 2B] fb: [NOFB], visible: no [ 1.464516] [drm:intel_dump_pipe_config [i915]] [PLANE:68:cursor B] fb: [NOFB], visible: no [ 1.464526] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 1.464573] [drm:intel_disable_pipe [i915]] disabling pipe A [ 1.467843] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well [ 1.467878] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 51 [ 1.467923] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 1.467957] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 2 [ 1.467991] i915 0000:00:02.0: [drm:intel_disable_sagv [i915]] Disabling SAGV [ 1.468025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI B] [ 1.468055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:96:DP-MST A] [ 1.468085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:97:DP-MST B] [ 1.468114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:98:DP-MST C] [ 1.468143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:109:DDI C] [ 1.468172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:111:DP-MST A] [ 1.468200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:112:DP-MST B] [ 1.468228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:113:DP-MST C] [ 1.468256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:119:DDI D] [ 1.468284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:121:DP-MST A] [ 1.468312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:122:DP-MST B] [ 1.468340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:123:DP-MST C] [ 1.468367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:129:DDI E] [ 1.468396] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 0 [ 1.468424] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 [ 1.468452] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 2 [ 1.468481] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 3 [ 1.468512] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 51 [ 1.468542] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 1.468641] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well [ 1.469400] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 [ 1.469709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 1.469737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 1.469765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 1.469793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 1.470489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 [ 1.470517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 [ 1.470544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.471230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 [ 1.471257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 [ 1.471284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.471974] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 1.472002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 1.473297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 1.473473] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:110:DP-2] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 1.473640] [drm:intel_enable_pipe [i915]] enabling pipe A [ 1.473675] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 1.473705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:110:DP-2], [ENCODER:109:DDI C] [ 1.473735] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder A, 36 bytes ELD [ 1.473767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 1.473810] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 72 [ 1.473841] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well [ 1.474602] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 [ 1.474908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 1.474936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 1.474964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 1.474992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 1.475686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 [ 1.475714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 [ 1.475740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.476426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 [ 1.476454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 [ 1.476481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.477166] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 1.477193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 1.478488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 1.478664] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:120:DP-3] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 1.478830] [drm:intel_enable_pipe [i915]] enabling pipe B [ 1.478862] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 1.478897] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun [ 1.478928] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:120:DP-3], [ENCODER:119:DDI D] [ 1.478957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder B, 36 bytes ELD [ 1.478988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 1.495987] [drm:verify_connector_state [i915]] [CONNECTOR:110:DP-2] [ 1.496025] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A] [ 1.496067] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 [ 1.496104] [drm:verify_connector_state [i915]] [CONNECTOR:120:DP-3] [ 1.496135] [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B] [ 1.496171] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 [ 1.496241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 [ 1.496252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a8e00a70 state to 000000002a70fa07 [ 1.496261] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 000000002a70fa07 [ 1.496285] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c4a0e3a state to 000000002a70fa07 [ 1.496310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c4a0e3a [ 1.496324] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 1.496335] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 1.496350] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 000000002a70fa07 [ 1.496359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f [ 1.496366] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000062109416 state to 000000002a70fa07 [ 1.496374] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 000000002a70fa07 [ 1.496381] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f97067cf state to 000000002a70fa07 [ 1.496389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f97067cf [ 1.496397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a6369fc8 state to 000000002a70fa07 [ 1.496404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a6369fc8 [ 1.496412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000091b367b1 state to 000000002a70fa07 [ 1.496421] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000009bdf158a state to 000000002a70fa07 [ 1.496428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000009bdf158a [ 1.496435] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fb662b09 state to 000000002a70fa07 [ 1.496443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fb662b09 [ 1.496455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a8e00a70 [ 1.496463] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 [ 1.496471] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 000000002a70fa07 [ 1.496479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] [ 1.496486] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] [ 1.496494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000062109416 [ 1.496501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 [ 1.496509] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000860da491 state to 000000002a70fa07 [ 1.496516] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [NOCRTC] [ 1.496523] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [CRTC:72:pipe B] [ 1.496531] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 000000002a70fa07 [ 1.496538] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 1.496545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000091b367b1 [ 1.496552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 [ 1.496560] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 [ 1.496570] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.496574] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.496578] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.496581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.496625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.496658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.496675] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 [ 1.512640] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 [ 1.512654] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 [ 1.524341] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 1.524352] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 [ 1.524362] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 1.524370] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 [ 1.524382] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f [ 1.524394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 [ 1.524403] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 [ 1.524412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 1.524420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 1.524428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 [ 1.524437] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 1.524446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 [ 1.524454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 1.524463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 [ 1.524471] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 [ 1.524479] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 [ 1.524489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 [ 1.524497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a [ 1.524506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c [ 1.524515] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 1.524524] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003979f4ee state to 0000000098df4bf3 [ 1.524533] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [NOCRTC] [ 1.524542] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [CRTC:51:pipe A] [ 1.524551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 1.524559] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 1.524568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 [ 1.524576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] [ 1.524585] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] [ 1.524593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 1.524602] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 1.524610] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f [ 1.524619] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 1.524628] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 1.524638] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.524643] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.524648] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.524652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.524716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.524754] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.524771] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 1.553743] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 1.553761] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 [ 1.553774] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 1.553786] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015579631 state to 00000000482d1aa4 [ 1.553798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 00000000482d1aa4 [ 1.553808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000482d1aa4 [ 1.553819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b [ 1.553830] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000482d1aa4 [ 1.553840] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 [ 1.553850] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000041c6228e state to 00000000482d1aa4 [ 1.553860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000022f73fd2 state to 00000000482d1aa4 [ 1.553869] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001f82d691 state to 00000000482d1aa4 [ 1.553879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001f82d691 [ 1.553889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 [ 1.553899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 [ 1.553909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e5892e4f state to 00000000482d1aa4 [ 1.553921] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c3b3ca94 state to 00000000482d1aa4 [ 1.553931] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c3b3ca94 [ 1.553940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000074f436be state to 00000000482d1aa4 [ 1.553950] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000074f436be [ 1.553960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015579631 [ 1.553970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 [ 1.553981] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000482d1aa4 [ 1.553991] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] [ 1.554000] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] [ 1.554010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000041c6228e [ 1.554020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 [ 1.554030] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000482d1aa4 [ 1.554039] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 1.554048] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 1.554058] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000006ede65dd state to 00000000482d1aa4 [ 1.554067] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000006ede65dd [ 1.554076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e5892e4f [ 1.554086] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 [ 1.554096] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 [ 1.554108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.554113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.554118] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.554123] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.554190] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.554233] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.554259] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 [ 1.562628] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 [ 1.562645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 [ 1.575634] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c [ 1.575648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 00000000fcb1012c [ 1.575660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000fcb1012c [ 1.575670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ccf8507 state to 00000000fcb1012c [ 1.575681] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ccf8507 [ 1.575691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bb3d8d45 state to 00000000fcb1012c [ 1.575702] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bb3d8d45 [ 1.575716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000485c2b88 state to 00000000fcb1012c [ 1.575725] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002ba4f36a state to 00000000fcb1012c [ 1.575735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004e08d13d state to 00000000fcb1012c [ 1.575745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004e08d13d [ 1.575754] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b2b055b6 state to 00000000fcb1012c [ 1.575767] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b2b055b6 [ 1.575798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000010a446a8 state to 00000000fcb1012c [ 1.575807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c [ 1.575817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf [ 1.575854] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d365bfc5 state to 00000000fcb1012c [ 1.575863] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d365bfc5 [ 1.575874] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a [ 1.575884] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c [ 1.575894] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001d9bfafc state to 00000000fcb1012c [ 1.575904] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [NOCRTC] [ 1.575914] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [CRTC:51:pipe A] [ 1.575924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000485c2b88 [ 1.575933] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c [ 1.575943] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000514f7582 state to 00000000fcb1012c [ 1.575952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [NOCRTC] [ 1.575961] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [CRTC:72:pipe B] [ 1.575971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c [ 1.575980] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 [ 1.575989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000010a446a8 [ 1.575999] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c [ 1.576008] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c [ 1.576020] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.576025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.576030] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.576035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.576097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.576139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.576167] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c [ 1.610983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bb4d667a [ 1.611007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c [ 1.611032] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e9b5f5ed state to 00000000bb4d667a [ 1.611054] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c [ 1.611079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000bb4d667a [ 1.611096] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000122a804f state to 00000000bb4d667a [ 1.611115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000122a804f [ 1.611131] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005d690c84 state to 00000000bb4d667a [ 1.611149] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005d690c84 [ 1.611165] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c775be6 state to 00000000bb4d667a [ 1.611183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000bb4d667a [ 1.611198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000b5f6abf5 state to 00000000bb4d667a [ 1.611214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000b5f6abf5 [ 1.611230] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000281af025 state to 00000000bb4d667a [ 1.611246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000281af025 [ 1.611261] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053454233 state to 00000000bb4d667a [ 1.611276] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b2cdb294 state to 00000000bb4d667a [ 1.611292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b2cdb294 [ 1.611308] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000555d146c state to 00000000bb4d667a [ 1.611323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000555d146c [ 1.611341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e9b5f5ed [ 1.611358] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000bb4d667a [ 1.611375] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000084c59d5f state to 00000000bb4d667a [ 1.611396] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [NOCRTC] [ 1.611412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [CRTC:51:pipe A] [ 1.611428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c775be6 [ 1.611444] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000bb4d667a [ 1.611460] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000adc2b291 state to 00000000bb4d667a [ 1.611476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [NOCRTC] [ 1.611491] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [CRTC:72:pipe B] [ 1.611508] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000bb4d667a [ 1.611524] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d [ 1.611539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053454233 [ 1.611560] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000bb4d667a [ 1.611577] [drm:drm_atomic_check_only [drm]] checking 00000000bb4d667a [ 1.611603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.611612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.611620] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.611628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.611728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.611798] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.611840] [drm:drm_atomic_commit [drm]] committing 00000000bb4d667a [ 1.645601] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bb4d667a [ 1.645625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 [ 1.645642] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bb4d667a [ 1.645659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000060d5862a state to 00000000482d1aa4 [ 1.645675] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000482d1aa4 [ 1.645689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000071f245df state to 00000000482d1aa4 [ 1.645705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000071f245df [ 1.645722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000482d1aa4 [ 1.645736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be [ 1.645752] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 00000000482d1aa4 [ 1.645767] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000669bfcd7 state to 00000000482d1aa4 [ 1.645779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5892e4f state to 00000000482d1aa4 [ 1.645794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5892e4f [ 1.645807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 [ 1.645820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 [ 1.645834] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001f82d691 state to 00000000482d1aa4 [ 1.645846] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 00000000482d1aa4 [ 1.645860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e [ 1.645874] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 00000000482d1aa4 [ 1.645888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 [ 1.645902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000060d5862a [ 1.645916] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 [ 1.645930] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 00000000482d1aa4 [ 1.645945] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 1.645958] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 1.645971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 [ 1.645984] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 [ 1.645998] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 00000000482d1aa4 [ 1.646011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 1.646024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 1.646037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d7f71e60 state to 00000000482d1aa4 [ 1.646050] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d7f71e60 [ 1.646063] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001f82d691 [ 1.646076] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 [ 1.646090] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 [ 1.646105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.646113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.646120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.646126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.646207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.646267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.646298] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 [ 1.662741] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 [ 1.662763] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 [ 1.682625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 1.682648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f101de7e state to 0000000098df4bf3 [ 1.682667] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 1.682683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e81eafbe state to 0000000098df4bf3 [ 1.682701] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e81eafbe [ 1.682718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000026a13e4f state to 0000000098df4bf3 [ 1.682735] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000026a13e4f [ 1.682755] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 [ 1.682770] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 1.682784] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005342f7e7 state to 0000000098df4bf3 [ 1.682801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005342f7e7 [ 1.682816] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fb96f9d3 state to 0000000098df4bf3 [ 1.682832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fb96f9d3 [ 1.682848] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000003eec9b7 state to 0000000098df4bf3 [ 1.682863] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 [ 1.682879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a [ 1.682894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 [ 1.682909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 [ 1.682926] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f101de7e [ 1.682942] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 1.682962] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000064c4b21e state to 0000000098df4bf3 [ 1.682979] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [NOCRTC] [ 1.682994] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [CRTC:51:pipe A] [ 1.683010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe [ 1.683025] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 1.683041] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 [ 1.683056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] [ 1.683072] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] [ 1.683088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 1.683103] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 1.683118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000003eec9b7 [ 1.683133] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 1.683149] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 1.683178] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.683187] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.683196] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.683203] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.683302] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.683372] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.683406] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 1.683650] ata1: SATA link down (SStatus 4 SControl 300) [ 1.683668] ata4: SATA link down (SStatus 4 SControl 300) [ 1.683686] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 1.683711] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) [ 1.685953] ata2.00: supports DRM functions and may not be fully accessible [ 1.686212] ata3.00: ATAPI: TSSTcorp CDDVDW SH-224GB, SB00, max UDMA/100 [ 1.687451] ata3.00: configured for UDMA/100 [ 1.692177] ata2.00: disabling queued TRIM support [ 1.692194] ata2.00: ATA-9: Samsung SSD 850 PRO 512GB, EXM02B6Q, max UDMA/133 [ 1.692196] ata2.00: 1000215216 sectors, multi 1: LBA48 NCQ (depth 32), AA [ 1.696183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 1.696209] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 1.698509] ata2.00: supports DRM functions and may not be fully accessible [ 1.699829] usb 1-7: new high-speed USB device number 2 using xhci_hcd [ 1.704324] ata2.00: disabling queued TRIM support [ 1.710263] ata2.00: configured for UDMA/133 [ 1.710469] scsi 1:0:0:0: Direct-Access ATA Samsung SSD 850 2B6Q PQ: 0 ANSI: 5 [ 1.713317] scsi 2:0:0:0: CD-ROM TSSTcorp CDDVDW SH-224GB SB00 PQ: 0 ANSI: 5 [ 1.725160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c [ 1.725192] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000c8bd6dc state to 00000000fcb1012c [ 1.725221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 00000000fcb1012c [ 1.725245] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000083c05b3d state to 00000000fcb1012c [ 1.725273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000083c05b3d [ 1.725297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008409a024 state to 00000000fcb1012c [ 1.725322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008409a024 [ 1.725347] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006164f3e3 state to 00000000fcb1012c [ 1.725370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 00000000fcb1012c [ 1.725394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000382acb58 state to 00000000fcb1012c [ 1.725418] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000382acb58 [ 1.725442] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a9a5a77 state to 00000000fcb1012c [ 1.725466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009a9a5a77 [ 1.725489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d365bfc5 state to 00000000fcb1012c [ 1.725510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c [ 1.725534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf [ 1.725557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010a446a8 state to 00000000fcb1012c [ 1.725580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010a446a8 [ 1.725608] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000c8bd6dc [ 1.725633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c [ 1.725662] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000008c0081a2 state to 00000000fcb1012c [ 1.725687] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [NOCRTC] [ 1.725712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [CRTC:51:pipe A] [ 1.725736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006164f3e3 [ 1.725759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c [ 1.725783] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 00000000fcb1012c [ 1.725806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] [ 1.725828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] [ 1.725853] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c [ 1.725876] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 [ 1.725898] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d365bfc5 [ 1.725921] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c [ 1.725945] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c [ 1.725977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.725990] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.726002] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.726013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.726148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.726252] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.726302] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c [ 1.740953] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c [ 1.740990] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c [ 1.776024] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000895e0f29 [ 1.776052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000bf89eae0 state to 00000000895e0f29 [ 1.776075] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002aa6a9f8 state to 00000000895e0f29 [ 1.776097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f454a2f1 state to 00000000895e0f29 [ 1.776121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f454a2f1 [ 1.776142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000895e0f29 [ 1.776163] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 [ 1.776185] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001e3a4a97 state to 00000000895e0f29 [ 1.776208] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 00000000895e0f29 [ 1.776228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000f80a3c5 state to 00000000895e0f29 [ 1.776249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000f80a3c5 [ 1.776269] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000002f5f5ecb state to 00000000895e0f29 [ 1.776289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000002f5f5ecb [ 1.776311] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000082c8a15 state to 00000000895e0f29 [ 1.776330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000017301ddd state to 00000000895e0f29 [ 1.776350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000017301ddd [ 1.776369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000bd98ba2f state to 00000000895e0f29 [ 1.776389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000bd98ba2f [ 1.776415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000bf89eae0 [ 1.776436] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000895e0f29 [ 1.776458] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002f3cb69d state to 00000000895e0f29 [ 1.776479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [NOCRTC] [ 1.776499] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [CRTC:51:pipe A] [ 1.776522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001e3a4a97 [ 1.776542] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000895e0f29 [ 1.776562] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001bc59558 state to 00000000895e0f29 [ 1.776582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [NOCRTC] [ 1.776601] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [CRTC:72:pipe B] [ 1.776621] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e59c9ea1 state to 00000000895e0f29 [ 1.776641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e59c9ea1 [ 1.776659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000082c8a15 [ 1.776679] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000895e0f29 [ 1.776700] [drm:drm_atomic_check_only [drm]] checking 00000000895e0f29 [ 1.776735] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.776746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.776757] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.776766] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.776890] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.776981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.777022] [drm:drm_atomic_commit [drm]] committing 00000000895e0f29 [ 1.804096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 [ 1.804107] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000895e0f29 [ 1.804118] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001e6f8dac state to 00000000548834f9 [ 1.804128] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000895e0f29 [ 1.804139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005b7d8c1d state to 00000000548834f9 [ 1.804146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b0a2562b state to 00000000548834f9 [ 1.804155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b0a2562b [ 1.804162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000210ee201 state to 00000000548834f9 [ 1.804172] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000210ee201 [ 1.804179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074e96990 state to 00000000548834f9 [ 1.804190] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000085f180bd state to 00000000548834f9 [ 1.804196] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018d44f01 state to 00000000548834f9 [ 1.804204] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018d44f01 [ 1.804211] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c0bd820d state to 00000000548834f9 [ 1.804218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c0bd820d [ 1.804225] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c73eec69 state to 00000000548834f9 [ 1.804232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000080dfd757 state to 00000000548834f9 [ 1.804239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000080dfd757 [ 1.804246] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f141c893 state to 00000000548834f9 [ 1.804253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f141c893 [ 1.804261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001e6f8dac [ 1.804268] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 [ 1.804281] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000f3f263f3 state to 00000000548834f9 [ 1.804291] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [NOCRTC] [ 1.804298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [CRTC:51:pipe A] [ 1.804306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000074e96990 [ 1.804313] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 [ 1.804320] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000af6800c9 state to 00000000548834f9 [ 1.804327] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [NOCRTC] [ 1.804334] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [CRTC:72:pipe B] [ 1.804341] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 [ 1.804348] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 [ 1.804355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c73eec69 [ 1.804362] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 [ 1.804369] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 [ 1.804388] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.804392] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.804398] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.804401] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.804446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.804478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.804499] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 [ 1.823766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 [ 1.823787] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 [ 1.823804] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 1.823818] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 000000006432a660 [ 1.823827] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 [ 1.823835] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c471465 state to 000000006432a660 [ 1.823845] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c471465 [ 1.823853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5b7e29b state to 000000006432a660 [ 1.823862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5b7e29b [ 1.823870] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 [ 1.823878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 [ 1.823885] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e7bdd2e4 state to 000000006432a660 [ 1.823893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e7bdd2e4 [ 1.823901] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 [ 1.823909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 [ 1.823917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000087dc1fd8 state to 000000006432a660 [ 1.823925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 000000006432a660 [ 1.823933] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d [ 1.823941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000df34b7b3 state to 000000006432a660 [ 1.823949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000df34b7b3 [ 1.823957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a [ 1.823965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 1.823974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 [ 1.823982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] [ 1.823990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] [ 1.824001] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa [ 1.824009] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 1.824017] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 [ 1.824025] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] [ 1.824032] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] [ 1.824041] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 1.824048] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 1.824056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000087dc1fd8 [ 1.824063] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 1.824071] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 1.824082] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.824099] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.824106] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.824110] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.824157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.824191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.824208] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 1.841121] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 1.841136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 1.854405] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 1.854418] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057ed1a51 state to 00000000c6c933d1 [ 1.854430] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 [ 1.854441] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008ffba3f3 state to 00000000c6c933d1 [ 1.854453] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008ffba3f3 [ 1.854464] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 [ 1.854476] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 [ 1.854489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 [ 1.854499] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 1.854509] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 [ 1.854520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 [ 1.854530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 1.854541] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 1.854552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 [ 1.854561] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 [ 1.854572] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab [ 1.854584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 [ 1.854594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 [ 1.854606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000057ed1a51 [ 1.854617] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 1.854628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 [ 1.854640] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] [ 1.854650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] [ 1.854661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 [ 1.854671] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 1.854682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 [ 1.854692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] [ 1.854703] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] [ 1.854714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 [ 1.854724] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 [ 1.854734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 [ 1.854744] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 1.854755] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 1.854767] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.854773] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.854779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.854784] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.854860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.854907] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.854927] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 1.879165] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 1.879183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 1.879202] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 [ 1.879217] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 1.879236] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 [ 1.879248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 [ 1.879265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 [ 1.879281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 [ 1.879294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 [ 1.879306] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 [ 1.879317] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 [ 1.879328] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 [ 1.879346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 [ 1.879357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 [ 1.879369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd [ 1.879382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 [ 1.879393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 [ 1.879405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 [ 1.879416] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 1.879428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 1.879440] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 [ 1.879453] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 1.879465] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 [ 1.879478] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] [ 1.879490] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] [ 1.879502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 [ 1.879514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 1.879526] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 1.879538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 1.879549] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 1.879561] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 1.879573] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 1.879584] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 [ 1.879596] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 1.879608] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 1.879622] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.879629] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.879635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.879641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.879713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.879765] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.879801] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 1.896360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 1.896381] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 1.912612] tsc: Refined TSC clocksource calibration: 3503.999 MHz [ 1.912618] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x3282124c47b, max_idle_ns: 440795239402 ns [ 1.912658] clocksource: Switched to clocksource tsc [ 1.912681] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 1.912697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 [ 1.912714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 1.912729] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 [ 1.912743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe [ 1.912756] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 [ 1.912769] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 [ 1.912781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 1.912793] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 1.912804] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 [ 1.912817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 [ 1.912829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 [ 1.912841] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f [ 1.912853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 [ 1.912866] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 [ 1.912878] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 [ 1.912889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 [ 1.912901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e [ 1.912914] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f [ 1.912926] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 1.912939] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000095845c0a state to 0000000098df4bf3 [ 1.912952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [NOCRTC] [ 1.912964] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [CRTC:51:pipe A] [ 1.912976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 1.912987] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 1.912999] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 [ 1.913011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] [ 1.913023] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] [ 1.913035] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 1.913047] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 1.913058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c [ 1.913070] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 1.913082] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 1.913095] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.913102] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.913108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.913114] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.913187] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.913239] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.913263] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 1.929772] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 1.929793] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 1.949476] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 [ 1.949495] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006a25a70b state to 000000002a70fa07 [ 1.949513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e46349dc state to 000000002a70fa07 [ 1.949530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f2e9b45 state to 000000002a70fa07 [ 1.949549] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f2e9b45 [ 1.949565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e2798a03 state to 000000002a70fa07 [ 1.949583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e2798a03 [ 1.949599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f4491376 state to 000000002a70fa07 [ 1.949615] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 000000002a70fa07 [ 1.949630] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003292b89f state to 000000002a70fa07 [ 1.949647] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003292b89f [ 1.949662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000015cf0577 state to 000000002a70fa07 [ 1.949679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000015cf0577 [ 1.949694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 000000002a70fa07 [ 1.949709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ab6fdf3f state to 000000002a70fa07 [ 1.949725] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ab6fdf3f [ 1.949744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bf01569 state to 000000002a70fa07 [ 1.949760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bf01569 [ 1.949777] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006a25a70b [ 1.949793] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 [ 1.949811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003a5f3d7f state to 000000002a70fa07 [ 1.949828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [NOCRTC] [ 1.949844] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [CRTC:51:pipe A] [ 1.949862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f4491376 [ 1.949879] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 [ 1.949895] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000bd54c871 state to 000000002a70fa07 [ 1.949911] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [NOCRTC] [ 1.949926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [CRTC:72:pipe B] [ 1.949943] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000de3ff82c state to 000000002a70fa07 [ 1.949959] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000de3ff82c [ 1.949974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 [ 1.949990] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 [ 1.950007] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 [ 1.950024] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.950034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.950042] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.950050] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.950146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.950217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.950249] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 [ 1.963116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 [ 1.963143] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 [ 1.975843] usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd [ 1.982659] usb 1-7: New USB device found, idVendor=1307, idProduct=0330, bcdDevice= 1.00 [ 1.982661] usb 1-7: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 1.982663] usb 1-7: Product: Mass Storage Device [ 1.982664] usb 1-7: Manufacturer: Generic [ 1.982665] usb 1-7: SerialNumber: 00000000000006 [ 1.984947] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 1.984976] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000087dc1fd8 state to 000000006432a660 [ 1.985005] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 [ 1.985028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ada87627 state to 000000006432a660 [ 1.985054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ada87627 [ 1.985077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e7bdd2e4 state to 000000006432a660 [ 1.985102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e7bdd2e4 [ 1.985125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 [ 1.985148] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 [ 1.985170] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5b7e29b state to 000000006432a660 [ 1.985194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5b7e29b [ 1.985218] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001c471465 state to 000000006432a660 [ 1.985242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001c471465 [ 1.985264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 [ 1.985286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000bf357c4b state to 000000006432a660 [ 1.985309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000bf357c4b [ 1.985332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 000000006432a660 [ 1.985355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 [ 1.985380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000087dc1fd8 [ 1.985403] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 1.985435] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 [ 1.985459] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] [ 1.985483] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] [ 1.985507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa [ 1.985530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 1.985553] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 [ 1.985576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 1.985600] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 1.985623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 1.985646] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 1.985668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a [ 1.985691] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 1.985714] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 1.985747] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.985759] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.985771] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.985782] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.985898] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.985980] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.986020] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 1.988961] usb-storage 1-7:1.0: USB Mass Storage device detected [ 1.989364] scsi host4: usb-storage 1-7:1.0 [ 1.989455] usbcore: registered new interface driver usb-storage [ 1.991210] usbcore: registered new interface driver uas [ 1.996109] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 1.996129] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 1.999995] usb 2-1: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 [ 1.999996] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.000778] hub 2-1:1.0: USB hub found [ 2.000960] hub 2-1:1.0: 4 ports detected [ 2.013903] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.013919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 [ 2.013933] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 [ 2.013946] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 [ 2.013961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 [ 2.013975] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000183fcb7 state to 00000000c6c933d1 [ 2.013989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000183fcb7 [ 2.014002] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000aff706ab state to 00000000c6c933d1 [ 2.014015] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 2.014028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.014042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fc1d1694 [ 2.014055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 2.014068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 2.014080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003e7fb927 state to 00000000c6c933d1 [ 2.014092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001964fcb3 state to 00000000c6c933d1 [ 2.014105] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001964fcb3 [ 2.014117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000dd33f136 state to 00000000c6c933d1 [ 2.014129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000dd33f136 [ 2.014143] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 [ 2.014156] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.014169] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 [ 2.014182] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] [ 2.014195] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] [ 2.014208] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000aff706ab [ 2.014221] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.014234] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 [ 2.014247] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] [ 2.014260] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] [ 2.014273] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 [ 2.014286] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 [ 2.014299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003e7fb927 [ 2.014312] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.014325] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.014340] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.014348] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.014354] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.014361] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.014425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.014482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.014507] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.029646] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.029666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.047486] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000246f13a6 [ 2.047504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f80a3c5 state to 00000000246f13a6 [ 2.047520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ad566469 state to 00000000246f13a6 [ 2.047534] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001e3a4a97 state to 00000000246f13a6 [ 2.047550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001e3a4a97 [ 2.047567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000246f13a6 [ 2.047581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 [ 2.047595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f454a2f1 state to 00000000246f13a6 [ 2.047608] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 00000000246f13a6 [ 2.047620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bf89eae0 state to 00000000246f13a6 [ 2.047634] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bf89eae0 [ 2.047648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000082c8a15 state to 00000000246f13a6 [ 2.047661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000082c8a15 [ 2.047674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000017301ddd state to 00000000246f13a6 [ 2.047690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9473c9b state to 00000000246f13a6 [ 2.047704] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9473c9b [ 2.047717] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fdc091c8 state to 00000000246f13a6 [ 2.047730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fdc091c8 [ 2.047744] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000f80a3c5 [ 2.047758] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000246f13a6 [ 2.047779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000079f595ad state to 00000000246f13a6 [ 2.047793] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [NOCRTC] [ 2.047806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [CRTC:51:pipe A] [ 2.047819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f454a2f1 [ 2.047833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000246f13a6 [ 2.047846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005876474e state to 00000000246f13a6 [ 2.047860] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [NOCRTC] [ 2.047872] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [CRTC:72:pipe B] [ 2.047886] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000009be30044 state to 00000000246f13a6 [ 2.047899] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000009be30044 [ 2.047912] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000017301ddd [ 2.047925] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000246f13a6 [ 2.047938] [drm:drm_atomic_check_only [drm]] checking 00000000246f13a6 [ 2.047954] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.047962] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.047968] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.047975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.048064] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.048124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.048152] [drm:drm_atomic_commit [drm]] committing 00000000246f13a6 [ 2.063067] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000246f13a6 [ 2.063089] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000246f13a6 [ 2.084698] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 [ 2.084727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f1595a5f state to 00000000548834f9 [ 2.084747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ca8a0e1e state to 00000000548834f9 [ 2.084765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f97cb978 state to 00000000548834f9 [ 2.084787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f97cb978 [ 2.084806] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e88acfd1 state to 00000000548834f9 [ 2.084826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e88acfd1 [ 2.084845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c2abb21 state to 00000000548834f9 [ 2.084864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000ff2cde6 state to 00000000548834f9 [ 2.084881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009f37190d state to 00000000548834f9 [ 2.084900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009f37190d [ 2.084918] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008793e16f state to 00000000548834f9 [ 2.084937] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008793e16f [ 2.084955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a71ddeb0 state to 00000000548834f9 [ 2.084972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005371ffea state to 00000000548834f9 [ 2.084990] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005371ffea [ 2.085008] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000757b68ad state to 00000000548834f9 [ 2.085026] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000757b68ad [ 2.085045] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f1595a5f [ 2.085064] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 [ 2.085084] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000e808d856 state to 00000000548834f9 [ 2.085103] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [NOCRTC] [ 2.085121] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [CRTC:51:pipe A] [ 2.085139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c2abb21 [ 2.085157] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 [ 2.085175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000004ac112a0 state to 00000000548834f9 [ 2.085194] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [NOCRTC] [ 2.085211] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [CRTC:72:pipe B] [ 2.085231] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 [ 2.085249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 [ 2.085265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a71ddeb0 [ 2.085283] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 [ 2.085303] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 [ 2.085324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.085335] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.085344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.085353] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.085466] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.085547] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.085583] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 [ 2.096461] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 [ 2.096491] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 [ 2.119701] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.119718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 [ 2.119732] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 [ 2.119746] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 [ 2.119761] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be [ 2.119781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 [ 2.119794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df [ 2.119807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 [ 2.119819] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 [ 2.119831] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 [ 2.119844] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 [ 2.119858] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 [ 2.119870] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b [ 2.119882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 [ 2.119893] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 [ 2.119906] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 [ 2.119917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.119930] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.119943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e [ 2.119956] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.119971] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 [ 2.119984] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 2.119996] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 2.120008] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a [ 2.120020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.120033] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.120045] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.120056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.120073] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.120085] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.120096] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a [ 2.120108] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.120120] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.120134] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.120141] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.120147] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.120153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.120236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.120291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.120315] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.129725] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.129746] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.143811] usb 1-10: new high-speed USB device number 3 using xhci_hcd [ 2.146032] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.146049] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000053155f00 state to 0000000098df4bf3 [ 2.146065] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.146077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f5e6213 state to 0000000098df4bf3 [ 2.146093] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f5e6213 [ 2.146107] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000515dc00f state to 0000000098df4bf3 [ 2.146120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000515dc00f [ 2.146133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 [ 2.146145] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.146156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009d539ce0 state to 0000000098df4bf3 [ 2.146170] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009d539ce0 [ 2.146181] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a35c929d state to 0000000098df4bf3 [ 2.146194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a35c929d [ 2.146205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000046234f6 state to 0000000098df4bf3 [ 2.146217] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 [ 2.146229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e [ 2.146240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 [ 2.146252] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 [ 2.146265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000053155f00 [ 2.146278] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.146292] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000b34fddb1 state to 0000000098df4bf3 [ 2.146305] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [NOCRTC] [ 2.146317] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [CRTC:51:pipe A] [ 2.146329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d [ 2.146341] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.146354] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000416eca0f state to 0000000098df4bf3 [ 2.146366] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [NOCRTC] [ 2.146377] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [CRTC:72:pipe B] [ 2.146390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.146402] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 2.146413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000046234f6 [ 2.146425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.146438] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.146451] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.146458] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.146465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.146470] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.146546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.146602] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.146626] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.163065] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.163088] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.192362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 2.192398] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000091b367b1 state to 00000000fc0cb429 [ 2.192425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 [ 2.192450] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a6369fc8 state to 00000000fc0cb429 [ 2.192481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a6369fc8 [ 2.192510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000062109416 state to 00000000fc0cb429 [ 2.192537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000062109416 [ 2.192562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005fe5cc2f state to 00000000fc0cb429 [ 2.192586] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 00000000fc0cb429 [ 2.192609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000bf01569 state to 00000000fc0cb429 [ 2.192636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000bf01569 [ 2.192659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ab6fdf3f state to 00000000fc0cb429 [ 2.192686] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ab6fdf3f [ 2.192709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 [ 2.192731] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 [ 2.192756] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 [ 2.192779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 [ 2.192804] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f [ 2.192830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000091b367b1 [ 2.192855] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 2.192882] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000168ff23b state to 00000000fc0cb429 [ 2.192908] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [NOCRTC] [ 2.192933] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [CRTC:51:pipe A] [ 2.192960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005fe5cc2f [ 2.192986] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 2.193011] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000da9b77f0 state to 00000000fc0cb429 [ 2.193036] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [NOCRTC] [ 2.193061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [CRTC:72:pipe B] [ 2.193088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ca6e974 state to 00000000fc0cb429 [ 2.193113] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ca6e974 [ 2.193137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 [ 2.193161] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 2.193187] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 2.193212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.193227] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.193239] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.193252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.193403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.193510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.193559] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 2.207959] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 2.207999] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 2.235181] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.235205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 000000001ff947e6 [ 2.235220] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 [ 2.235233] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010a446a8 state to 000000001ff947e6 [ 2.235247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010a446a8 [ 2.235260] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c23288bf state to 000000001ff947e6 [ 2.235274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c23288bf [ 2.235287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d365bfc5 state to 000000001ff947e6 [ 2.235301] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001775ba6b state to 000000001ff947e6 [ 2.235316] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009a9a5a77 state to 000000001ff947e6 [ 2.235328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009a9a5a77 [ 2.235340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000382acb58 state to 000000001ff947e6 [ 2.235352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000382acb58 [ 2.235364] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006164f3e3 state to 000000001ff947e6 [ 2.235376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000008409a024 state to 000000001ff947e6 [ 2.235388] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000008409a024 [ 2.235400] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000083c05b3d state to 000000001ff947e6 [ 2.235412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000083c05b3d [ 2.235425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a [ 2.235438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.235451] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000fc47d714 state to 000000001ff947e6 [ 2.235464] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [NOCRTC] [ 2.235476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [CRTC:51:pipe A] [ 2.235489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d365bfc5 [ 2.235501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.235514] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 000000001ff947e6 [ 2.235526] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] [ 2.235538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] [ 2.235551] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000048e8a8c4 state to 000000001ff947e6 [ 2.235563] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000048e8a8c4 [ 2.235575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006164f3e3 [ 2.235587] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.235599] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.235628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.235635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.235641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.235647] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.235730] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.235784] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.235815] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.246467] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.246485] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.258018] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.258028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 [ 2.258037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 000000006432a660 [ 2.258045] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 [ 2.258054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 [ 2.258061] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 [ 2.258069] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 [ 2.258077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 [ 2.258084] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 000000006432a660 [ 2.258092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 [ 2.258100] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 [ 2.258110] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 [ 2.258118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f [ 2.258125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 [ 2.258132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 [ 2.258139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 [ 2.258146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.258153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.258161] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa [ 2.258169] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.258178] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000227e02b1 state to 000000006432a660 [ 2.258186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [NOCRTC] [ 2.258193] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [CRTC:51:pipe A] [ 2.258203] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 [ 2.258210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.258219] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 [ 2.258226] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] [ 2.258233] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] [ 2.258242] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.258249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.258256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 [ 2.258263] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.258271] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.258281] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.258285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.258289] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.258293] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.258354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.258387] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.258403] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.274508] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.274524] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.287455] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.287470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 [ 2.287483] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.287494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 [ 2.287508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f [ 2.287519] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 [ 2.287531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 [ 2.287542] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 2.287553] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.287563] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 [ 2.287574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 2.287585] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 [ 2.287595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 2.287610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 [ 2.287624] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 [ 2.287635] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 [ 2.287645] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 [ 2.287656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a [ 2.287667] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c [ 2.287678] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.287690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009b609533 state to 0000000098df4bf3 [ 2.287701] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [NOCRTC] [ 2.287712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [CRTC:51:pipe A] [ 2.287723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 2.287734] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.287744] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000050cb1035 state to 0000000098df4bf3 [ 2.287755] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [NOCRTC] [ 2.287765] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [CRTC:72:pipe B] [ 2.287782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.287792] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 2.287803] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f [ 2.287813] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.287825] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.287839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.287846] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.287851] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.287856] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.287928] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.287977] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.287999] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.292557] usb 1-10: New USB device found, idVendor=0557, idProduct=7000, bcdDevice= 0.00 [ 2.292559] usb 1-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.293488] hub 1-10:1.0: USB hub found [ 2.293604] hub 1-10:1.0: 4 ports detected [ 2.296162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.296181] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.314444] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 2.314463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c4a0e3a state to 00000000fc0cb429 [ 2.314480] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 00000000fc0cb429 [ 2.314494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a8e00a70 state to 00000000fc0cb429 [ 2.314511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a8e00a70 [ 2.314525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007f2e9b45 state to 00000000fc0cb429 [ 2.314540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000007f2e9b45 [ 2.314554] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 [ 2.314568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 00000000fc0cb429 [ 2.314581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f4491376 state to 00000000fc0cb429 [ 2.314596] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f4491376 [ 2.314609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009bdf158a state to 00000000fc0cb429 [ 2.314623] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009bdf158a [ 2.314636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003292b89f state to 00000000fc0cb429 [ 2.314649] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 [ 2.314663] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 [ 2.314677] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d93e8df3 state to 00000000fc0cb429 [ 2.314690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d93e8df3 [ 2.314705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c4a0e3a [ 2.314719] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 2.314734] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000309bb6f5 state to 00000000fc0cb429 [ 2.314749] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [NOCRTC] [ 2.314763] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [CRTC:51:pipe A] [ 2.314776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 [ 2.314791] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 2.314805] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000005b4f258 state to 00000000fc0cb429 [ 2.314818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [NOCRTC] [ 2.314832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [CRTC:72:pipe B] [ 2.314846] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 [ 2.314859] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 2.314872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003292b89f [ 2.314886] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 2.314900] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 2.314915] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.314923] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.314930] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.314936] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.315024] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.315085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.315120] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 2.329803] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 2.329826] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 2.348527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.348550] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000df34b7b3 state to 000000006432a660 [ 2.348569] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 [ 2.348583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ed11a5b9 state to 000000006432a660 [ 2.348600] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ed11a5b9 [ 2.348615] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000f8d239cd state to 000000006432a660 [ 2.348630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000f8d239cd [ 2.348644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005f11c147 state to 000000006432a660 [ 2.348661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 [ 2.348674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000457aaa57 state to 000000006432a660 [ 2.348689] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000457aaa57 [ 2.348702] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b1ca1c71 state to 000000006432a660 [ 2.348716] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b1ca1c71 [ 2.348730] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b4343291 state to 000000006432a660 [ 2.348743] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000067db6375 state to 000000006432a660 [ 2.348758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000067db6375 [ 2.348777] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.348791] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.348806] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000df34b7b3 [ 2.348821] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.348836] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 [ 2.348851] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] [ 2.348865] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] [ 2.348883] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005f11c147 [ 2.348897] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.348911] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.348926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.348939] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.348954] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.348969] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.348982] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b4343291 [ 2.348996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.349010] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.349026] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.349034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.349041] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.349048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.349141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.349203] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.349231] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.363033] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.363056] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.381721] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.381738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008ffba3f3 state to 00000000c6c933d1 [ 2.381754] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 [ 2.381767] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 [ 2.381784] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 [ 2.381798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 [ 2.381813] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 [ 2.381827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 [ 2.381841] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 2.381853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 [ 2.381868] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 [ 2.381882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 2.381896] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 2.381909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.381922] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 [ 2.381935] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab [ 2.381948] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 [ 2.381962] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 [ 2.381976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008ffba3f3 [ 2.381992] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.382007] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000046dc0413 state to 00000000c6c933d1 [ 2.382021] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [NOCRTC] [ 2.382035] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [CRTC:51:pipe A] [ 2.382048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 [ 2.382062] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.382075] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000002e396b94 state to 00000000c6c933d1 [ 2.382089] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [NOCRTC] [ 2.382101] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [CRTC:72:pipe B] [ 2.382115] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 [ 2.382129] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f [ 2.382142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 [ 2.382155] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.382169] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.382186] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.382194] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.382206] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.382212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.382288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.382348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.382376] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.396184] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.396207] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.414905] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.414925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003eec9b7 state to 0000000098df4bf3 [ 2.414942] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.414957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fb96f9d3 state to 0000000098df4bf3 [ 2.414973] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fb96f9d3 [ 2.414988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005342f7e7 state to 0000000098df4bf3 [ 2.415003] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005342f7e7 [ 2.415020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 [ 2.415034] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.415047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000026a13e4f state to 0000000098df4bf3 [ 2.415062] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000026a13e4f [ 2.415076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e81eafbe state to 0000000098df4bf3 [ 2.415090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e81eafbe [ 2.415103] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f101de7e state to 0000000098df4bf3 [ 2.415123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 [ 2.415137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a [ 2.415150] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 [ 2.415164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 [ 2.415180] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003eec9b7 [ 2.415194] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.415209] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009e77ee4b state to 0000000098df4bf3 [ 2.415227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [NOCRTC] [ 2.415241] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [CRTC:51:pipe A] [ 2.415255] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe [ 2.415269] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.415284] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006fd04029 state to 0000000098df4bf3 [ 2.415298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [NOCRTC] [ 2.415311] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [CRTC:72:pipe B] [ 2.415328] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.415342] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 2.415355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f101de7e [ 2.415369] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.415383] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.415399] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.415407] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.415414] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.415423] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.415506] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.415569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.415598] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.420197] usb 2-2: new SuperSpeed Gen 1 USB device number 3 using xhci_hcd [ 2.429805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.429829] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.440080] usb 2-2: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 [ 2.440081] usb 2-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.441055] hub 2-2:1.0: USB hub found [ 2.441232] hub 2-2:1.0: 4 ports detected [ 2.451314] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 2.451340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a6369fc8 state to 00000000fc0cb429 [ 2.451359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 [ 2.451375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000091b367b1 state to 00000000fc0cb429 [ 2.451395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000091b367b1 [ 2.451412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 00000000fc0cb429 [ 2.451429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f [ 2.451446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bf01569 state to 00000000fc0cb429 [ 2.451462] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 [ 2.451477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ab6fdf3f state to 00000000fc0cb429 [ 2.451494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ab6fdf3f [ 2.451510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 [ 2.451526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b [ 2.451543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 [ 2.451559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 [ 2.451575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 [ 2.451591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 [ 2.451607] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f [ 2.451624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a6369fc8 [ 2.451641] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 2.451660] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ee6ef05 state to 00000000fc0cb429 [ 2.451677] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [NOCRTC] [ 2.451693] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [CRTC:51:pipe A] [ 2.451710] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bf01569 [ 2.451726] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 2.451743] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009647804d state to 00000000fc0cb429 [ 2.451760] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [NOCRTC] [ 2.451784] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [CRTC:72:pipe B] [ 2.451801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000dd2a82ac state to 00000000fc0cb429 [ 2.451817] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000dd2a82ac [ 2.451832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 [ 2.451848] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 2.451865] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 2.451883] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.451892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.451900] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.451908] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.452011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.452082] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.452114] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 2.463087] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 2.463114] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 2.484902] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.484925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 [ 2.484941] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 000000006432a660 [ 2.484955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 [ 2.484971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 [ 2.484985] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 [ 2.485000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f [ 2.485015] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 [ 2.485028] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 000000006432a660 [ 2.485041] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 [ 2.485055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 [ 2.485067] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 [ 2.485081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 [ 2.485094] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 [ 2.485106] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 [ 2.485120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa [ 2.485132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.485146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.485160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 [ 2.485174] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.485189] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 000000006432a660 [ 2.485203] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] [ 2.485216] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] [ 2.485229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 [ 2.485243] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.485257] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 [ 2.485270] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 2.485283] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 2.485297] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.485310] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.485322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 [ 2.485336] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.485349] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.485365] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.485373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.485380] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.485386] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.485476] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.485536] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.485568] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.496321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.496343] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.514099] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.514115] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000086e6c525 state to 00000000c6c933d1 [ 2.514130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 [ 2.514143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000076facd10 state to 00000000c6c933d1 [ 2.514159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000076facd10 [ 2.514173] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000900779b1 state to 00000000c6c933d1 [ 2.514187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000900779b1 [ 2.514201] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 [ 2.514214] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 2.514227] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 [ 2.514241] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab [ 2.514254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.514267] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 [ 2.514281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 [ 2.514293] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 [ 2.514306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 [ 2.514319] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 [ 2.514332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 [ 2.514346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000086e6c525 [ 2.514359] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.514373] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000006978e08c state to 00000000c6c933d1 [ 2.514389] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [NOCRTC] [ 2.514402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [CRTC:51:pipe A] [ 2.514415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 [ 2.514429] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.514442] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009efdc675 state to 00000000c6c933d1 [ 2.514455] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [NOCRTC] [ 2.514467] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [CRTC:72:pipe B] [ 2.514485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 [ 2.514499] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 [ 2.514511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f [ 2.514523] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.514537] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.514551] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.514559] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.514566] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.514572] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.514659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.514717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.514743] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.529754] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.529779] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.550511] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.550530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c471465 state to 000000006432a660 [ 2.550547] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 [ 2.550562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059814b3a state to 000000006432a660 [ 2.550581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059814b3a [ 2.550597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bf357c4b state to 000000006432a660 [ 2.550614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bf357c4b [ 2.550629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d9e36170 state to 000000006432a660 [ 2.550644] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 [ 2.550658] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 000000006432a660 [ 2.550675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a [ 2.550690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000071f245df state to 000000006432a660 [ 2.550705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000071f245df [ 2.550720] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000074f436be state to 000000006432a660 [ 2.550735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 000000006432a660 [ 2.550750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e [ 2.550765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.550780] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.550798] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c471465 [ 2.550814] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.550831] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 [ 2.550847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 2.550862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 2.550876] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d9e36170 [ 2.550891] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.550907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.550922] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.550937] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.550953] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.550967] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.550981] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000074f436be [ 2.550996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.551012] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.551029] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.551037] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.551045] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.551053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.551151] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.551217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.551247] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.563034] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.563060] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.567816] usb 1-11: new high-speed USB device number 4 using xhci_hcd [ 2.582973] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.582995] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 [ 2.583010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.583024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 [ 2.583039] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe [ 2.583052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 [ 2.583066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 [ 2.583080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 2.583096] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.583108] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 [ 2.583121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 [ 2.583133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 [ 2.583146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f [ 2.583159] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 [ 2.583171] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 [ 2.583184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 [ 2.583197] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 [ 2.583210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e [ 2.583224] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f [ 2.583237] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.583251] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 0000000098df4bf3 [ 2.583265] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] [ 2.583278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] [ 2.583290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 2.583303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.583317] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 [ 2.583329] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] [ 2.583342] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] [ 2.583355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.583368] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 2.583380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c [ 2.583392] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.583406] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.583424] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.583432] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.583438] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.583444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.583528] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.583585] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.583612] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.596477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.596495] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.610890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.610906] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000382acb58 state to 000000001ff947e6 [ 2.610919] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 000000001ff947e6 [ 2.610930] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009a9a5a77 state to 000000001ff947e6 [ 2.610943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009a9a5a77 [ 2.610955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d365bfc5 state to 000000001ff947e6 [ 2.610966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d365bfc5 [ 2.610978] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c23288bf state to 000000001ff947e6 [ 2.610989] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 000000001ff947e6 [ 2.611000] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000010a446a8 state to 000000001ff947e6 [ 2.611012] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000010a446a8 [ 2.611022] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e536e28a state to 000000001ff947e6 [ 2.611033] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e536e28a [ 2.611044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fac02d29 state to 000000001ff947e6 [ 2.611054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e23783d2 state to 000000001ff947e6 [ 2.611065] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e23783d2 [ 2.611075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000009ecd9d0a state to 000000001ff947e6 [ 2.611086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000009ecd9d0a [ 2.611097] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000382acb58 [ 2.611109] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.611121] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000949ef34b state to 000000001ff947e6 [ 2.611132] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [NOCRTC] [ 2.611143] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [CRTC:51:pipe A] [ 2.611153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c23288bf [ 2.611164] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.611175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000025f34563 state to 000000001ff947e6 [ 2.611186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [NOCRTC] [ 2.611196] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [CRTC:72:pipe B] [ 2.611213] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 000000001ff947e6 [ 2.611224] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b [ 2.611234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fac02d29 [ 2.611244] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.611255] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.611268] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.611274] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.611280] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.611285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.611363] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.611411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.611436] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.624544] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.624568] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.648394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.648422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 [ 2.648448] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 [ 2.648470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 [ 2.648494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 [ 2.648515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 [ 2.648536] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 [ 2.648557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 [ 2.648577] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 [ 2.648596] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 [ 2.648618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 [ 2.648637] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 [ 2.648657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f [ 2.648680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 [ 2.648699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 [ 2.648719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 [ 2.648738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.648758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.648785] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa [ 2.648805] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.648826] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 [ 2.648848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] [ 2.648867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] [ 2.648892] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 [ 2.648912] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.648933] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 [ 2.648953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] [ 2.648972] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] [ 2.648999] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.649018] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.649037] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 [ 2.649057] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.649077] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.649105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.649116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.649126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.649136] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.649258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.649348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.649388] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.663045] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.663078] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.695073] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.695099] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000046234f6 state to 0000000098df4bf3 [ 2.695121] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.695139] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a35c929d state to 0000000098df4bf3 [ 2.695164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a35c929d [ 2.695189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 0000000098df4bf3 [ 2.695210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 [ 2.695229] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 [ 2.695248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.695265] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 0000000098df4bf3 [ 2.695284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f [ 2.695303] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007f5e6213 state to 0000000098df4bf3 [ 2.695322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007f5e6213 [ 2.695340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053155f00 state to 0000000098df4bf3 [ 2.695357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 [ 2.695376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e [ 2.695396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 [ 2.695414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 [ 2.695435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000046234f6 [ 2.695454] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.695474] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 0000000098df4bf3 [ 2.695494] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] [ 2.695512] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] [ 2.695531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d [ 2.695550] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.695569] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 [ 2.695587] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] [ 2.695604] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] [ 2.695623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.695641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 2.695658] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053155f00 [ 2.695676] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.695695] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.695725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.695736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.695745] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.695755] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.695886] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.695968] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.696005] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.713154] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.713185] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.716173] usb 1-11: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 [ 2.716176] usb 1-11: New USB device strings: Mfr=0, Product=0, SerialNumber=1 [ 2.716179] usb 1-11: SerialNumber: DC0F18713FF2 [ 2.717025] hub 1-11:1.0: USB hub found [ 2.717053] hub 1-11:1.0: 4 ports detected [ 2.744349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.744373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000098081998 state to 000000001ff947e6 [ 2.744393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 [ 2.744411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007284ebf4 state to 000000001ff947e6 [ 2.744433] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007284ebf4 [ 2.744451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000092bd7e4c state to 000000001ff947e6 [ 2.744470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000092bd7e4c [ 2.744488] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000687f38c3 state to 000000001ff947e6 [ 2.744505] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003eebba06 state to 000000001ff947e6 [ 2.744522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000072a9793c state to 000000001ff947e6 [ 2.744540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000072a9793c [ 2.744559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 000000001ff947e6 [ 2.744577] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac [ 2.744593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 000000001ff947e6 [ 2.744609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 000000001ff947e6 [ 2.744627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 [ 2.744643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 000000001ff947e6 [ 2.744660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c [ 2.744678] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000098081998 [ 2.744696] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.744715] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ebbd72c state to 000000001ff947e6 [ 2.744734] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [NOCRTC] [ 2.744751] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [CRTC:51:pipe A] [ 2.744773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000687f38c3 [ 2.744790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.744808] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001175f931 state to 000000001ff947e6 [ 2.744825] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [NOCRTC] [ 2.744842] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [CRTC:72:pipe B] [ 2.744860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000053a23bd6 state to 000000001ff947e6 [ 2.744877] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000053a23bd6 [ 2.744893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e [ 2.744911] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.744928] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.744948] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.744958] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.744969] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.744977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.745085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.745164] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.745209] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.757894] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.757923] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.781266] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.781290] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 [ 2.781313] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 [ 2.781332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 [ 2.781353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 [ 2.781371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 [ 2.781390] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 [ 2.781409] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 [ 2.781426] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 [ 2.781443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 [ 2.781462] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 [ 2.781478] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 [ 2.781496] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd [ 2.781514] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 [ 2.781530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 [ 2.781548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 [ 2.781565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.781583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.781602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 [ 2.781620] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.781639] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 [ 2.781658] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] [ 2.781675] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] [ 2.781694] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 [ 2.781712] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.781729] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.781747] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.781764] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.781782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.781800] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.781816] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 [ 2.781833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.781851] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.781869] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.781879] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.781888] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.781897] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.782005] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.782084] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.782120] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.796434] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.796463] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.815843] usb 1-10.1: new low-speed USB device number 5 using xhci_hcd [ 2.830298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.830323] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dd33f136 state to 00000000c6c933d1 [ 2.830358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 [ 2.830378] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 [ 2.830401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 [ 2.830422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008ffba3f3 state to 00000000c6c933d1 [ 2.830443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008ffba3f3 [ 2.830466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 [ 2.830485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 2.830504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 [ 2.830525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 [ 2.830544] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 2.830564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 2.830583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.830601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 [ 2.830621] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab [ 2.830640] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 [ 2.830659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 [ 2.830684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000dd33f136 [ 2.830704] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.830725] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 [ 2.830746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] [ 2.830766] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] [ 2.830788] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 [ 2.830808] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.830828] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 [ 2.830848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] [ 2.830867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] [ 2.830890] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 [ 2.830910] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 [ 2.830928] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 [ 2.830948] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.830968] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.831004] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.831015] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.831025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.831035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.831156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.831242] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.831281] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.846410] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.846458] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.877085] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.877104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 [ 2.877120] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.877135] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 [ 2.877153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f [ 2.877167] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 [ 2.877181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 [ 2.877195] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 2.877209] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.877222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 [ 2.877236] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 2.877248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 [ 2.877262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 2.877275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 [ 2.877287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 [ 2.877301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 [ 2.877313] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 [ 2.877327] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a [ 2.877344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c [ 2.877357] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.877372] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 0000000098df4bf3 [ 2.877386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] [ 2.877399] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] [ 2.877412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 2.877426] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.877439] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 [ 2.877452] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] [ 2.877465] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] [ 2.877479] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.877492] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 2.877504] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f [ 2.877517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.877531] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.877553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.877561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.877571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.877577] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.877659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.877719] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.877747] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.891314] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.891333] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.906312] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.906333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000918919b3 state to 000000001ff947e6 [ 2.906347] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 000000001ff947e6 [ 2.906358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000005a00270 state to 000000001ff947e6 [ 2.906372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000005a00270 [ 2.906384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000512c7fb3 state to 000000001ff947e6 [ 2.906396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000512c7fb3 [ 2.906408] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000063c0bfb2 state to 000000001ff947e6 [ 2.906419] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 000000001ff947e6 [ 2.906433] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004acae8d3 state to 000000001ff947e6 [ 2.906445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004acae8d3 [ 2.906456] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 000000001ff947e6 [ 2.906468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 [ 2.906479] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 000000001ff947e6 [ 2.906489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a4c468ad state to 000000001ff947e6 [ 2.906500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a4c468ad [ 2.906511] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000320b468c state to 000000001ff947e6 [ 2.906522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000320b468c [ 2.906542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000918919b3 [ 2.906555] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.906568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ba4c5dc3 state to 000000001ff947e6 [ 2.906580] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [NOCRTC] [ 2.906591] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [CRTC:51:pipe A] [ 2.906602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000063c0bfb2 [ 2.906613] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.906625] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ae0223f3 state to 000000001ff947e6 [ 2.906636] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [NOCRTC] [ 2.906646] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [CRTC:72:pipe B] [ 2.906661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 000000001ff947e6 [ 2.906672] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 [ 2.906682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d [ 2.906693] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.906705] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.906718] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.906725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.906731] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.906736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.906813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.906863] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.906886] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.913164] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.913183] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.933406] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.933430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 [ 2.933451] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 [ 2.933468] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 [ 2.933490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 [ 2.933508] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 [ 2.933527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f [ 2.933545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 [ 2.933563] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 [ 2.933583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 [ 2.933601] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 [ 2.933618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 [ 2.933636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 [ 2.933653] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 [ 2.933670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 [ 2.933687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa [ 2.933705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.933723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.933741] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 [ 2.933759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.933778] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 [ 2.933800] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] [ 2.933818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] [ 2.933836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 [ 2.933853] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.933871] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 [ 2.933888] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 2.933905] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 2.933923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.933940] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.933957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 [ 2.933974] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.933992] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.934021] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.934031] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.934039] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.934048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.934156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.934235] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.934270] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.945099] usb 1-10.1: New USB device found, idVendor=0557, idProduct=2419, bcdDevice= 1.00 [ 2.945102] usb 1-10.1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.946202] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.946230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.969637] hid: raw HID events driver (C) Jiri Kosina [ 2.980218] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.980244] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 [ 2.980267] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 [ 2.980286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 [ 2.980309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 [ 2.980330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000097efae80 state to 00000000c6c933d1 [ 2.980351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000097efae80 [ 2.980372] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 [ 2.980391] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 2.980410] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 [ 2.980431] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab [ 2.980449] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.980470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 [ 2.980489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 [ 2.980507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 [ 2.980527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 [ 2.980547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 [ 2.980566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 [ 2.980587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 [ 2.980607] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.980628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 [ 2.980650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] [ 2.980670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] [ 2.980690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 [ 2.980709] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.980728] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 [ 2.980748] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] [ 2.980767] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] [ 2.980792] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 [ 2.980812] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 [ 2.980830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f [ 2.980850] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.980871] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.980898] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.980910] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.980920] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.980929] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.981048] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.981050] usbcore: registered new interface driver usbhid [ 2.981135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.981135] usbhid: USB HID core driver [ 2.981182] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.983750] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.0/0003:0557:2419.0001/input/input4 [ 2.996172] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.996195] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.016364] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 3.016380] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 [ 3.016393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 [ 3.016405] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 [ 3.016419] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be [ 3.016432] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 [ 3.016445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df [ 3.016458] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 [ 3.016470] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 [ 3.016481] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 [ 3.016494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 [ 3.016507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 [ 3.016519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b [ 3.016531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 [ 3.016543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 [ 3.016556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 [ 3.016568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 3.016580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 3.016593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e [ 3.016606] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 3.016619] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 [ 3.016632] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 3.016644] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 3.016657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a [ 3.016669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 3.016682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 3.016694] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 3.016706] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 3.016719] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 3.016731] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 3.016743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a [ 3.016755] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 3.016767] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 3.016778] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.016785] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.016791] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.016798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.016860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.016917] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.016940] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 3.020983] scsi 4:0:0:0: Direct-Access Generic Compact Flash 0.00 PQ: 0 ANSI: 2 [ 3.021765] scsi 4:0:0:1: Direct-Access Generic SD/MMC 0.00 PQ: 0 ANSI: 2 [ 3.022194] scsi 4:0:0:2: Direct-Access Generic microSD 0.00 PQ: 0 ANSI: 2 [ 3.022768] scsi 4:0:0:3: Direct-Access Generic MS/MS-PRO 0.00 PQ: 0 ANSI: 2 [ 3.023138] scsi 4:0:0:4: Direct-Access Generic SM/xD-Picture 0.00 PQ: 0 ANSI: 2 [ 3.029581] sd 1:0:0:0: [sda] 1000215216 512-byte logical blocks: (512 GB/477 GiB) [ 3.029588] sd 1:0:0:0: [sda] Write Protect is off [ 3.029589] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 3.029597] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 3.043978] hid-generic 0003:0557:2419.0001: input,hidraw0: USB HID v1.00 Keyboard [HID 0557:2419] on usb-0000:00:14.0-10.1/input0 [ 3.044084] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.1/0003:0557:2419.0002/input/input5 [ 3.044277] hid-generic 0003:0557:2419.0002: input,hidraw1: USB HID v1.00 Mouse [HID 0557:2419] on usb-0000:00:14.0-10.1/input1 [ 3.044891] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 3.044908] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 [ 3.044928] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 3.044945] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007b36813f state to 00000000c29bd936 [ 3.044964] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ec014e4 state to 00000000c29bd936 [ 3.044984] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000555d146c state to 00000000c29bd936 [ 3.045005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000555d146c [ 3.045023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b2cdb294 state to 00000000c29bd936 [ 3.045041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b2cdb294 [ 3.045060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000053454233 state to 00000000c29bd936 [ 3.045079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a746018c state to 00000000c29bd936 [ 3.045097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 [ 3.045113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 [ 3.045123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b5f6abf5 state to 00000000c29bd936 [ 3.045134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b5f6abf5 [ 3.045147] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000c775be6 state to 00000000c29bd936 [ 3.045156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005d690c84 state to 00000000c29bd936 [ 3.045167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005d690c84 [ 3.045177] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000122a804f state to 00000000c29bd936 [ 3.045188] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000122a804f [ 3.045200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007b36813f [ 3.045211] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 [ 3.045222] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004edc31e9 state to 00000000c29bd936 [ 3.045238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [NOCRTC] [ 3.045256] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [CRTC:51:pipe A] [ 3.045274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000053454233 [ 3.045294] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 [ 3.045312] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005d1fe044 state to 00000000c29bd936 [ 3.045325] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [NOCRTC] [ 3.045335] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [CRTC:72:pipe B] [ 3.045350] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ef13faa state to 00000000c29bd936 [ 3.045360] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ef13faa [ 3.045369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000c775be6 [ 3.045380] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 [ 3.045390] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 [ 3.045403] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.045410] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.045415] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.045420] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.045496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.045543] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.045577] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 [ 3.052647] sd 4:0:0:4: [sdf] Attached SCSI removable disk [ 3.054117] sda: sda1 sda2 < sda5 > [ 3.054604] sd 1:0:0:0: [sda] supports TCG Opal [ 3.054605] sd 1:0:0:0: [sda] Attached SCSI disk [ 3.056264] sd 4:0:0:3: [sde] Attached SCSI removable disk [ 3.057329] sd 4:0:0:1: [sdc] Attached SCSI removable disk [ 3.057645] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 [ 3.057661] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 [ 3.060799] sd 4:0:0:0: [sdb] Attached SCSI removable disk [ 3.071802] usb 1-12: new high-speed USB device number 6 using xhci_hcd [ 3.072920] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 [ 3.072942] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fac02d29 state to 00000000ffbe70d8 [ 3.072961] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000ffbe70d8 [ 3.072980] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ecd9d0a state to 00000000ffbe70d8 [ 3.072992] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ecd9d0a [ 3.073004] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000098081998 state to 00000000ffbe70d8 [ 3.073017] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000098081998 [ 3.073035] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007284ebf4 state to 00000000ffbe70d8 [ 3.073054] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 [ 3.073071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000092bd7e4c state to 00000000ffbe70d8 [ 3.073089] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000092bd7e4c [ 3.073105] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 00000000ffbe70d8 [ 3.073123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac [ 3.073140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 00000000ffbe70d8 [ 3.073157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 00000000ffbe70d8 [ 3.073175] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 [ 3.073189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 00000000ffbe70d8 [ 3.073199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c [ 3.073211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000fac02d29 [ 3.073222] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 [ 3.073233] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000be46149d state to 00000000ffbe70d8 [ 3.073244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [NOCRTC] [ 3.073254] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [CRTC:51:pipe A] [ 3.073265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000007284ebf4 [ 3.073276] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 [ 3.073286] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000068a1fb01 state to 00000000ffbe70d8 [ 3.073297] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [NOCRTC] [ 3.073307] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [CRTC:72:pipe B] [ 3.073318] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000cf23fbdd state to 00000000ffbe70d8 [ 3.073328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000cf23fbdd [ 3.073338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e [ 3.073348] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 [ 3.073359] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 [ 3.073371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.073377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.073382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.073387] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.073458] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.073505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.073529] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 [ 3.073552] sd 4:0:0:2: [sdd] Attached SCSI removable disk [ 3.079604] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 [ 3.079650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 [ 3.108427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 [ 3.108443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000122a804f state to 00000000c29bd936 [ 3.108457] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000228f716d state to 00000000c29bd936 [ 3.108470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000005d690c84 state to 00000000c29bd936 [ 3.108486] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000005d690c84 [ 3.108499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000c775be6 state to 00000000c29bd936 [ 3.108513] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000c775be6 [ 3.108527] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b5f6abf5 state to 00000000c29bd936 [ 3.108540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 [ 3.108552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 [ 3.108566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 [ 3.108578] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053454233 state to 00000000c29bd936 [ 3.108592] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053454233 [ 3.108604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b2cdb294 state to 00000000c29bd936 [ 3.108616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000555d146c state to 00000000c29bd936 [ 3.108630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000555d146c [ 3.108642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007b36813f state to 00000000c29bd936 [ 3.108655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007b36813f [ 3.108668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000122a804f [ 3.108682] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 [ 3.108695] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eee09833 state to 00000000c29bd936 [ 3.108709] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [NOCRTC] [ 3.108722] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [CRTC:51:pipe A] [ 3.108736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b5f6abf5 [ 3.108749] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 [ 3.108761] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000898e3e27 state to 00000000c29bd936 [ 3.108774] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [NOCRTC] [ 3.108787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [CRTC:72:pipe B] [ 3.108801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d0e256d1 state to 00000000c29bd936 [ 3.108814] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d0e256d1 [ 3.108826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b2cdb294 [ 3.108839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 [ 3.108865] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 [ 3.108875] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.108882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.108887] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.108892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.108956] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.109003] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.109025] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 [ 3.124527] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 [ 3.124544] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 [ 3.137517] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a6b51f [ 3.137531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000012530223 state to 0000000073a6b51f [ 3.137543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000009be30044 state to 0000000073a6b51f [ 3.137555] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ffe00c37 state to 0000000073a6b51f [ 3.137567] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ffe00c37 [ 3.137577] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000023a9a422 state to 0000000073a6b51f [ 3.137587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000023a9a422 [ 3.137598] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bdb8d82 state to 0000000073a6b51f [ 3.137607] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 0000000073a6b51f [ 3.137617] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e3147659 state to 0000000073a6b51f [ 3.137627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e3147659 [ 3.137636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000004825b29a state to 0000000073a6b51f [ 3.137646] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000004825b29a [ 3.137657] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005788f64c state to 0000000073a6b51f [ 3.137667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000032e38a43 state to 0000000073a6b51f [ 3.137676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000032e38a43 [ 3.137685] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000089408e5f state to 0000000073a6b51f [ 3.137695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000089408e5f [ 3.137705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000012530223 [ 3.137715] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000073a6b51f [ 3.137726] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000748c93aa state to 0000000073a6b51f [ 3.137737] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [NOCRTC] [ 3.137746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [CRTC:51:pipe A] [ 3.137760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bdb8d82 [ 3.137769] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000073a6b51f [ 3.137779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f1b6922b state to 0000000073a6b51f [ 3.137789] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [NOCRTC] [ 3.137798] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [CRTC:72:pipe B] [ 3.137808] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ad566469 state to 0000000073a6b51f [ 3.137818] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ad566469 [ 3.137827] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005788f64c [ 3.137836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000073a6b51f [ 3.137846] [drm:drm_atomic_check_only [drm]] checking 0000000073a6b51f [ 3.137866] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.137872] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.137882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.137886] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.137944] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.137988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.138008] [drm:drm_atomic_commit [drm]] committing 0000000073a6b51f [ 3.146528] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a6b51f [ 3.146545] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a6b51f [ 3.157850] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 [ 3.157860] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002f4e481a state to 00000000619b20f5 [ 3.157869] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001b7eae74 state to 00000000619b20f5 [ 3.157877] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000025544875 state to 00000000619b20f5 [ 3.157886] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000025544875 [ 3.157894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008c95634f state to 00000000619b20f5 [ 3.157902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008c95634f [ 3.157910] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000483335fe state to 00000000619b20f5 [ 3.157917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ae874d06 state to 00000000619b20f5 [ 3.157925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 00000000619b20f5 [ 3.157932] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 3.157941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000865de88c state to 00000000619b20f5 [ 3.157948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000865de88c [ 3.157955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001c64fec3 state to 00000000619b20f5 [ 3.157962] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001726835f state to 00000000619b20f5 [ 3.157970] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001726835f [ 3.157977] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006011267c state to 00000000619b20f5 [ 3.157984] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006011267c [ 3.157993] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002f4e481a [ 3.158001] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 [ 3.158009] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 00000000619b20f5 [ 3.158017] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] [ 3.158024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] [ 3.158031] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000483335fe [ 3.158039] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 [ 3.158046] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000b34fddb1 state to 00000000619b20f5 [ 3.158054] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [NOCRTC] [ 3.158061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [CRTC:72:pipe B] [ 3.158069] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000904bdb49 state to 00000000619b20f5 [ 3.158076] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000904bdb49 [ 3.158083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001c64fec3 [ 3.158090] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 [ 3.158098] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 [ 3.158108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.158112] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.158116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.158119] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.158180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.158213] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.158229] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 [ 3.174683] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 [ 3.174697] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 [ 3.186485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.186502] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f11c147 state to 00000000f3200e59 [ 3.186513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 00000000f3200e59 [ 3.186523] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000457aaa57 state to 00000000f3200e59 [ 3.186534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000457aaa57 [ 3.186545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 00000000f3200e59 [ 3.186555] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 [ 3.186565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b4343291 state to 00000000f3200e59 [ 3.186575] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 00000000f3200e59 [ 3.186584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000067db6375 state to 00000000f3200e59 [ 3.186594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000067db6375 [ 3.186604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ed11a5b9 state to 00000000f3200e59 [ 3.186614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ed11a5b9 [ 3.186623] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df34b7b3 state to 00000000f3200e59 [ 3.186632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e5b7e29b state to 00000000f3200e59 [ 3.186641] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e5b7e29b [ 3.186650] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001c471465 state to 00000000f3200e59 [ 3.186659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001c471465 [ 3.186670] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000005f11c147 [ 3.186680] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.186690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000140b0238 state to 00000000f3200e59 [ 3.186704] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [NOCRTC] [ 3.186714] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [CRTC:51:pipe A] [ 3.186723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b4343291 [ 3.186733] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.186742] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001ddd4fdd state to 00000000f3200e59 [ 3.186752] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [NOCRTC] [ 3.186761] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [CRTC:72:pipe B] [ 3.186772] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 00000000f3200e59 [ 3.186781] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 3.186790] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df34b7b3 [ 3.186800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.186810] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.186829] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.186834] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.186839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.186844] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.186901] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.186949] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.186968] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.196452] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.196472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.216790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 [ 3.216813] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000063c0bfb2 state to 00000000ffbe70d8 [ 3.216833] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 00000000ffbe70d8 [ 3.216851] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000918919b3 state to 00000000ffbe70d8 [ 3.216872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000918919b3 [ 3.216889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000005a00270 state to 00000000ffbe70d8 [ 3.216907] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000005a00270 [ 3.216924] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000512c7fb3 state to 00000000ffbe70d8 [ 3.216940] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 [ 3.216956] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018dbb82d state to 00000000ffbe70d8 [ 3.216974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018dbb82d [ 3.216990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 [ 3.217006] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 [ 3.217023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a4c468ad state to 00000000ffbe70d8 [ 3.217038] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000320b468c state to 00000000ffbe70d8 [ 3.217055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000320b468c [ 3.217074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000063ec03c state to 00000000ffbe70d8 [ 3.217090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000063ec03c [ 3.217108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000063c0bfb2 [ 3.217125] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 [ 3.217143] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d05a5c4c state to 00000000ffbe70d8 [ 3.217161] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [NOCRTC] [ 3.217177] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [CRTC:51:pipe A] [ 3.217193] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000512c7fb3 [ 3.217210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 [ 3.217227] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000fc47d714 state to 00000000ffbe70d8 [ 3.217243] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [NOCRTC] [ 3.217259] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [CRTC:72:pipe B] [ 3.217276] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 [ 3.217293] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b [ 3.217308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a4c468ad [ 3.217325] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 [ 3.217342] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 [ 3.217360] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.217371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.217382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.217390] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.217495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.217569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.217604] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 [ 3.220944] usb 1-12: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 [ 3.220946] usb 1-12: New USB device strings: Mfr=0, Product=0, SerialNumber=1 [ 3.220948] usb 1-12: SerialNumber: CD0F18513FF2 [ 3.221863] hub 1-12:1.0: USB hub found [ 3.221920] hub 1-12:1.0: 4 ports detected [ 3.229639] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 [ 3.229666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 [ 3.259936] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 [ 3.259967] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007835ad2c state to 00000000c29bd936 [ 3.259995] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000c29bd936 [ 3.260020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a0e4907f state to 00000000c29bd936 [ 3.260049] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a0e4907f [ 3.260075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c342e8b6 state to 00000000c29bd936 [ 3.260102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c342e8b6 [ 3.260127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f85c23ef state to 00000000c29bd936 [ 3.260151] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 [ 3.260174] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e025482e state to 00000000c29bd936 [ 3.260200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e025482e [ 3.260224] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000fcc8f6c state to 00000000c29bd936 [ 3.260249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000000fcc8f6c [ 3.260275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000093fc8e4 state to 00000000c29bd936 [ 3.260299] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005f84ed88 state to 00000000c29bd936 [ 3.260324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005f84ed88 [ 3.260348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006115325a state to 00000000c29bd936 [ 3.260373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006115325a [ 3.260399] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007835ad2c [ 3.260425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 [ 3.260452] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000093f6ce9d state to 00000000c29bd936 [ 3.260479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [NOCRTC] [ 3.260503] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [CRTC:51:pipe A] [ 3.260528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f85c23ef [ 3.260552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 [ 3.260578] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000074011bcd state to 00000000c29bd936 [ 3.260602] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [NOCRTC] [ 3.260626] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [CRTC:72:pipe B] [ 3.260651] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000c29bd936 [ 3.260677] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d [ 3.260700] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000093fc8e4 [ 3.260725] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 [ 3.260750] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 [ 3.260776] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.260790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.260802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.260815] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.260951] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.261061] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.261109] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 [ 3.274626] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 [ 3.274674] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 [ 3.299821] usb 1-11.2: new full-speed USB device number 7 using xhci_hcd [ 3.303479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006379f080 [ 3.303499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000559c57fd state to 000000006379f080 [ 3.303517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e59c9ea1 state to 000000006379f080 [ 3.303532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fdc091c8 state to 000000006379f080 [ 3.303551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fdc091c8 [ 3.303572] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a9473c9b state to 000000006379f080 [ 3.303588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a9473c9b [ 3.303604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000089408e5f state to 000000006379f080 [ 3.303618] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 000000006379f080 [ 3.303632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000032e38a43 state to 000000006379f080 [ 3.303648] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000032e38a43 [ 3.303662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005788f64c state to 000000006379f080 [ 3.303677] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005788f64c [ 3.303691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000004825b29a state to 000000006379f080 [ 3.303705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e3147659 state to 000000006379f080 [ 3.303720] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e3147659 [ 3.303734] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bdb8d82 state to 000000006379f080 [ 3.303750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bdb8d82 [ 3.303766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000559c57fd [ 3.303790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006379f080 [ 3.303807] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000000e02d6ba state to 000000006379f080 [ 3.303835] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [NOCRTC] [ 3.303847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [CRTC:51:pipe A] [ 3.303860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000089408e5f [ 3.303872] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006379f080 [ 3.303886] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f298f57c state to 000000006379f080 [ 3.303898] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [NOCRTC] [ 3.303910] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [CRTC:72:pipe B] [ 3.303923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000002aa6a9f8 state to 000000006379f080 [ 3.303935] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000002aa6a9f8 [ 3.303947] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000004825b29a [ 3.303959] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006379f080 [ 3.303971] [drm:drm_atomic_check_only [drm]] checking 000000006379f080 [ 3.304000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.304007] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.304013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.304019] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.304102] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.304157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.304182] [drm:drm_atomic_commit [drm]] committing 000000006379f080 [ 3.313100] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006379f080 [ 3.313118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006379f080 [ 3.326983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 [ 3.326998] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000515dc00f state to 00000000619b20f5 [ 3.327010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b7f89a8d state to 00000000619b20f5 [ 3.327021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008cab647d state to 00000000619b20f5 [ 3.327036] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008cab647d [ 3.327047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 00000000619b20f5 [ 3.327058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 [ 3.327071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a35c929d state to 00000000619b20f5 [ 3.327081] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000347fbd12 state to 00000000619b20f5 [ 3.327091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000046234f6 state to 00000000619b20f5 [ 3.327102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000046234f6 [ 3.327112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053155f00 state to 00000000619b20f5 [ 3.327122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053155f00 [ 3.327132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f3527d8e state to 00000000619b20f5 [ 3.327141] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 00000000619b20f5 [ 3.327152] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 [ 3.327163] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000022fc4ece state to 00000000619b20f5 [ 3.327173] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000022fc4ece [ 3.327184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000515dc00f [ 3.327195] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 [ 3.327206] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 00000000619b20f5 [ 3.327217] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] [ 3.327227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] [ 3.327238] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000a35c929d [ 3.327248] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 [ 3.327258] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009b609533 state to 00000000619b20f5 [ 3.327268] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [NOCRTC] [ 3.327278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [CRTC:72:pipe B] [ 3.327289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 [ 3.327299] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce [ 3.327308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f3527d8e [ 3.327318] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 [ 3.327329] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 [ 3.327341] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.327346] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.327352] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.327356] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.327430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.327475] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.327501] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 [ 3.341307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 [ 3.341359] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 [ 3.379822] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.379844] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 00000000f3200e59 [ 3.379864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000f3200e59 [ 3.379881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000f3200e59 [ 3.379901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b [ 3.379920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000f3200e59 [ 3.379938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 [ 3.379955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 00000000f3200e59 [ 3.379972] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 [ 3.379988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000071f245df state to 00000000f3200e59 [ 3.380005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000071f245df [ 3.380021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000074f436be state to 00000000f3200e59 [ 3.380038] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000074f436be [ 3.380054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000041c6228e state to 00000000f3200e59 [ 3.380069] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 00000000f3200e59 [ 3.380086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d [ 3.380101] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001f82d691 state to 00000000f3200e59 [ 3.380117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001f82d691 [ 3.380135] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a [ 3.380153] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.380174] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ce20e5c8 state to 00000000f3200e59 [ 3.380192] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [NOCRTC] [ 3.380208] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [CRTC:51:pipe A] [ 3.380225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a [ 3.380242] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.380263] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001b5c4b62 state to 00000000f3200e59 [ 3.380279] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [NOCRTC] [ 3.380295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [CRTC:72:pipe B] [ 3.380312] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 00000000f3200e59 [ 3.380328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 3.380344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000041c6228e [ 3.380360] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.380376] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.380402] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.380411] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.380419] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.380427] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.380529] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.380604] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.380646] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.396469] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.396503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.410062] usb 1-11.2: New USB device found, idVendor=17ef, idProduct=6047, bcdDevice= 3.00 [ 3.410064] usb 1-11.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 3.410065] usb 1-11.2: Product: ThinkPad Compact USB Keyboard with TrackPoint [ 3.410067] usb 1-11.2: Manufacturer: Lenovo [ 3.418473] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 [ 3.418496] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001090afab state to 00000000ffbe70d8 [ 3.418515] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000053a23bd6 state to 00000000ffbe70d8 [ 3.418532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028cdc562 state to 00000000ffbe70d8 [ 3.418552] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028cdc562 [ 3.418574] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000063ec03c state to 00000000ffbe70d8 [ 3.418593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000063ec03c [ 3.418610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000320b468c state to 00000000ffbe70d8 [ 3.418627] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a4f0e9bc state to 00000000ffbe70d8 [ 3.418642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000a4c468ad state to 00000000ffbe70d8 [ 3.418660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000a4c468ad [ 3.418680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 [ 3.418697] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 [ 3.418713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 00000000ffbe70d8 [ 3.418728] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000512c7fb3 state to 00000000ffbe70d8 [ 3.418745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000512c7fb3 [ 3.418761] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000005a00270 state to 00000000ffbe70d8 [ 3.418778] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000005a00270 [ 3.418800] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001090afab [ 3.418817] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 [ 3.418835] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001175f931 state to 00000000ffbe70d8 [ 3.418853] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [NOCRTC] [ 3.418869] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [CRTC:51:pipe A] [ 3.418888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000320b468c [ 3.418905] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 [ 3.418922] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ebbd72c state to 00000000ffbe70d8 [ 3.418938] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [NOCRTC] [ 3.418953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [CRTC:72:pipe B] [ 3.418971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 [ 3.418987] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b [ 3.419002] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d [ 3.419018] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 [ 3.419035] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 [ 3.419053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.419062] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.419070] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.419078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.419184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.419258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.419291] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 [ 3.425539] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.0/0003:17EF:6047.0003/input/input6 [ 3.429543] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 [ 3.429570] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 [ 3.451015] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.451031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008af22ea7 state to 00000000c6c933d1 [ 3.451046] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 [ 3.451060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 [ 3.451076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be [ 3.451089] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002a1c343e state to 00000000c6c933d1 [ 3.451104] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002a1c343e [ 3.451117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f7870136 state to 00000000c6c933d1 [ 3.451130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 3.451142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ad384e88 state to 00000000c6c933d1 [ 3.451156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ad384e88 [ 3.451172] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008fde4998 state to 00000000c6c933d1 [ 3.451186] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008fde4998 [ 3.451198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000071cce0a state to 00000000c6c933d1 [ 3.451210] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000007ba2cc3a state to 00000000c6c933d1 [ 3.451223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000007ba2cc3a [ 3.451236] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac0b8286 state to 00000000c6c933d1 [ 3.451249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac0b8286 [ 3.451262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008af22ea7 [ 3.451280] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.451294] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eb0da826 state to 00000000c6c933d1 [ 3.451308] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [NOCRTC] [ 3.451321] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [CRTC:51:pipe A] [ 3.451334] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f7870136 [ 3.451347] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.451361] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 [ 3.451373] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] [ 3.451386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] [ 3.451399] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 [ 3.451412] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 [ 3.451425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000071cce0a [ 3.451438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.451451] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.451465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.451473] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.451481] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.451487] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.451560] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.451617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.451643] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.463098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.463116] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.478096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 [ 3.478112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001726835f state to 00000000619b20f5 [ 3.478125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000be800543 state to 00000000619b20f5 [ 3.478137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c64fec3 state to 00000000619b20f5 [ 3.478150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c64fec3 [ 3.478162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000865de88c state to 00000000619b20f5 [ 3.478174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000865de88c [ 3.478186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000000fcc975 state to 00000000619b20f5 [ 3.478197] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000068c99925 state to 00000000619b20f5 [ 3.478209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000483335fe state to 00000000619b20f5 [ 3.478220] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000483335fe [ 3.478231] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008c95634f state to 00000000619b20f5 [ 3.478243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008c95634f [ 3.478254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000025544875 state to 00000000619b20f5 [ 3.478264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 00000000619b20f5 [ 3.478276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a [ 3.478286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f101de7e state to 00000000619b20f5 [ 3.478297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f101de7e [ 3.478309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001726835f [ 3.478321] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 [ 3.478334] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 00000000619b20f5 [ 3.478346] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] [ 3.478357] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] [ 3.478368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000000fcc975 [ 3.478379] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 [ 3.478390] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009e77ee4b state to 00000000619b20f5 [ 3.478402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [NOCRTC] [ 3.478412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [CRTC:72:pipe B] [ 3.478425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 [ 3.478436] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce [ 3.478446] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000025544875 [ 3.478457] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 [ 3.478469] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 [ 3.478482] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.478488] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.478494] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.478500] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.478579] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.478630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.478659] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 [ 3.484276] lenovo 0003:17EF:6047.0003: input,hidraw2: USB HID v1.00 Keyboard [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input0 [ 3.484522] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.1/0003:17EF:6047.0004/input/input7 [ 3.491321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 [ 3.491337] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 [ 3.504241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 3.504253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015cf0577 state to 00000000fc0cb429 [ 3.504264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 [ 3.504273] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003292b89f state to 00000000fc0cb429 [ 3.504285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003292b89f [ 3.504294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009bdf158a state to 00000000fc0cb429 [ 3.504305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009bdf158a [ 3.504315] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 [ 3.504324] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cf9cfc99 state to 00000000fc0cb429 [ 3.504333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007f2e9b45 state to 00000000fc0cb429 [ 3.504342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007f2e9b45 [ 3.504356] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 [ 3.504366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b [ 3.504375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005fe5cc2f state to 00000000fc0cb429 [ 3.504384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000091b367b1 state to 00000000fc0cb429 [ 3.504393] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000091b367b1 [ 3.504402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000a6369fc8 state to 00000000fc0cb429 [ 3.504411] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000a6369fc8 [ 3.504422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015cf0577 [ 3.504431] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 3.504443] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000bd54c871 state to 00000000fc0cb429 [ 3.504453] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [NOCRTC] [ 3.504462] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [CRTC:51:pipe A] [ 3.504472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 [ 3.504481] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 3.504491] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000309bb6f5 state to 00000000fc0cb429 [ 3.504500] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [NOCRTC] [ 3.504510] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [CRTC:72:pipe B] [ 3.504519] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 [ 3.504529] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 3.504538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005fe5cc2f [ 3.504547] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 3.504558] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 3.504571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.504576] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.504581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.504586] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.504640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.504682] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.504701] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 3.513214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 3.513230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 3.527601] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.527620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002938b22d state to 00000000f3200e59 [ 3.527632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000022f73fd2 state to 00000000f3200e59 [ 3.527643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000041c6228e state to 00000000f3200e59 [ 3.527656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000041c6228e [ 3.527667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000f3200e59 [ 3.527679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be [ 3.527692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000071f245df state to 00000000f3200e59 [ 3.527705] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 [ 3.527716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 00000000f3200e59 [ 3.527728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a [ 3.527738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000d9e36170 state to 00000000f3200e59 [ 3.527749] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000d9e36170 [ 3.527760] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bf357c4b state to 00000000f3200e59 [ 3.527776] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000059814b3a state to 00000000f3200e59 [ 3.527787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000059814b3a [ 3.527798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 [ 3.527809] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd [ 3.527828] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002938b22d [ 3.527839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.527850] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000300c269e state to 00000000f3200e59 [ 3.527862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [NOCRTC] [ 3.527873] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [CRTC:51:pipe A] [ 3.527884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000071f245df [ 3.527894] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.527907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000000afdf5db state to 00000000f3200e59 [ 3.527917] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [NOCRTC] [ 3.527928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [CRTC:72:pipe B] [ 3.527939] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 [ 3.527949] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e [ 3.527959] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bf357c4b [ 3.527970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.527981] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.527993] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.528000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.528005] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.528010] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.528081] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.528130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.528155] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.532011] usb 1-14: new full-speed USB device number 8 using xhci_hcd [ 3.541291] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.541309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.544126] lenovo 0003:17EF:6047.0004: input,hiddev0,hidraw3: USB HID v1.00 Mouse [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input1 [ 3.556564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.556581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000023110e55 state to 00000000c6c933d1 [ 3.556594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 [ 3.556605] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b9dd800a state to 00000000c6c933d1 [ 3.556617] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b9dd800a [ 3.556628] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000edf72591 state to 00000000c6c933d1 [ 3.556640] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000edf72591 [ 3.556651] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009869db1d state to 00000000c6c933d1 [ 3.556661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 3.556671] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bd903151 state to 00000000c6c933d1 [ 3.556682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bd903151 [ 3.556692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c282abaf state to 00000000c6c933d1 [ 3.556703] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c282abaf [ 3.556713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000009f04fd17 state to 00000000c6c933d1 [ 3.556723] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c31f7fa4 state to 00000000c6c933d1 [ 3.556734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c31f7fa4 [ 3.556744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000eac50bee state to 00000000c6c933d1 [ 3.556754] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000eac50bee [ 3.556766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000023110e55 [ 3.556777] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.556793] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000dddcb6a7 state to 00000000c6c933d1 [ 3.556804] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [NOCRTC] [ 3.556814] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [CRTC:51:pipe A] [ 3.556825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009869db1d [ 3.556836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.556846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 [ 3.556857] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] [ 3.556867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] [ 3.556878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 [ 3.556889] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 [ 3.556899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000009f04fd17 [ 3.556909] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.556920] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.556932] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.556938] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.556944] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.556949] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.557021] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.557068] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.557089] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.563101] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.563118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.577479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.577503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003073c677 state to 00000000f3200e59 [ 3.577514] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 00000000f3200e59 [ 3.577525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e5892e4f state to 00000000f3200e59 [ 3.577537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e5892e4f [ 3.577548] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c3b3ca94 state to 00000000f3200e59 [ 3.577559] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c3b3ca94 [ 3.577570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000015579631 state to 00000000f3200e59 [ 3.577580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 00000000f3200e59 [ 3.577590] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000083fdb4aa state to 00000000f3200e59 [ 3.577602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000083fdb4aa [ 3.577614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000087dc1fd8 state to 00000000f3200e59 [ 3.577624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000087dc1fd8 [ 3.577635] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ada87627 state to 00000000f3200e59 [ 3.577644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e7bdd2e4 state to 00000000f3200e59 [ 3.577655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e7bdd2e4 [ 3.577666] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 [ 3.577676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd [ 3.577687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000003073c677 [ 3.577698] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.577711] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000f3200e59 [ 3.577725] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] [ 3.577735] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] [ 3.577746] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000015579631 [ 3.577756] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.577766] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000f3200e59 [ 3.577777] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 3.577787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 3.577798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 [ 3.577808] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e [ 3.577818] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ada87627 [ 3.577828] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.577839] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.577852] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.577858] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.577863] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.577868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.577941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.577988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.578009] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.591295] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.591314] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.605686] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.605699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003494222 state to 00000000c6c933d1 [ 3.605711] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 [ 3.605722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010343cf4 state to 00000000c6c933d1 [ 3.605736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010343cf4 [ 3.605747] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e6ce87e3 state to 00000000c6c933d1 [ 3.605758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e6ce87e3 [ 3.605769] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac0b8286 state to 00000000c6c933d1 [ 3.605779] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 3.605789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007ba2cc3a state to 00000000c6c933d1 [ 3.605801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007ba2cc3a [ 3.605811] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000071cce0a state to 00000000c6c933d1 [ 3.605822] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000071cce0a [ 3.605832] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008fde4998 state to 00000000c6c933d1 [ 3.605842] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ad384e88 state to 00000000c6c933d1 [ 3.605852] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ad384e88 [ 3.605862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f7870136 state to 00000000c6c933d1 [ 3.605872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f7870136 [ 3.605884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003494222 [ 3.605895] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.605907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 [ 3.605918] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] [ 3.605928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] [ 3.605943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000ac0b8286 [ 3.605953] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.605964] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 [ 3.605975] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] [ 3.605985] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] [ 3.605996] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 [ 3.606007] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f [ 3.606016] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008fde4998 [ 3.606027] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.606038] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.606061] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.606067] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.606072] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.606078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.606138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.606184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.606205] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.613058] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.613075] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.626981] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.626992] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002a1c343e state to 00000000c6c933d1 [ 3.627002] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 [ 3.627011] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 [ 3.627022] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be [ 3.627031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008af22ea7 state to 00000000c6c933d1 [ 3.627042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008af22ea7 [ 3.627051] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b777cf9c state to 00000000c6c933d1 [ 3.627060] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 3.627074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fcdab79b state to 00000000c6c933d1 [ 3.627083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fcdab79b [ 3.627092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000031a1a724 state to 00000000c6c933d1 [ 3.627102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000031a1a724 [ 3.627111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008f0802a0 state to 00000000c6c933d1 [ 3.627119] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000098e2986c state to 00000000c6c933d1 [ 3.627128] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000098e2986c [ 3.627137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000859ae2da state to 00000000c6c933d1 [ 3.627146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000859ae2da [ 3.627156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002a1c343e [ 3.627166] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.627184] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003d8ac4de state to 00000000c6c933d1 [ 3.627198] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [NOCRTC] [ 3.627207] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [CRTC:51:pipe A] [ 3.627217] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b777cf9c [ 3.627226] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.627235] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006c42b361 state to 00000000c6c933d1 [ 3.627244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [NOCRTC] [ 3.627253] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [CRTC:72:pipe B] [ 3.627263] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 [ 3.627272] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 [ 3.627280] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008f0802a0 [ 3.627289] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.627298] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.627309] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.627315] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.627319] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.627324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.627377] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.627418] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.627437] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.641307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.641321] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.641349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.641359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b5c379f5 state to 00000000c6c933d1 [ 3.641368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 [ 3.641376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f7870136 state to 00000000c6c933d1 [ 3.641387] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f7870136 [ 3.641396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ad384e88 state to 00000000c6c933d1 [ 3.641405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ad384e88 [ 3.641414] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008fde4998 state to 00000000c6c933d1 [ 3.641422] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 3.641430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000071cce0a state to 00000000c6c933d1 [ 3.641439] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000071cce0a [ 3.641448] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007ba2cc3a state to 00000000c6c933d1 [ 3.641457] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007ba2cc3a [ 3.641465] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ac0b8286 state to 00000000c6c933d1 [ 3.641473] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e6ce87e3 state to 00000000c6c933d1 [ 3.641482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e6ce87e3 [ 3.641490] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010343cf4 state to 00000000c6c933d1 [ 3.641498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010343cf4 [ 3.641508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000b5c379f5 [ 3.641517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.641530] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000091d2cf4c state to 00000000c6c933d1 [ 3.641539] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [NOCRTC] [ 3.641547] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [CRTC:51:pipe A] [ 3.641556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008fde4998 [ 3.641564] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.641573] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000706e661a state to 00000000c6c933d1 [ 3.641582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [NOCRTC] [ 3.641590] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [CRTC:72:pipe B] [ 3.641599] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 [ 3.641607] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 [ 3.641615] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ac0b8286 [ 3.641624] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.641634] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.641652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.641657] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.641662] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.641666] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.641717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.641755] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.641773] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.657984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.658001] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.672900] i915 0000:00:02.0: fb1: i915drmfb frame buffer device [ 3.672952] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] [ 3.672975] [drm:drm_client_modeset_probe [drm]] [ 3.672989] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 3.673056] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 3.673077] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 3.673087] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 3.673141] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 3.673439] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.673482] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.674059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.674108] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.674144] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.674179] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 3.676928] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.676971] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 3.677594] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.677624] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.677924] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.677959] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.677966] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 3.677973] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 3.678004] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 3.678433] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.678800] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.680367] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.680395] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.680424] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.680717] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 3.681517] usb 1-14: New USB device found, idVendor=045e, idProduct=028e, bcdDevice= 1.10 [ 3.681519] usb 1-14: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 3.681521] usb 1-14: Product: TGZ Controller [ 3.681522] usb 1-14: Manufacturer: D [ 3.681523] usb 1-14: SerialNumber: 3E5296A0 [ 3.687203] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.687816] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.687827] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.687847] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.687853] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.688062] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.688070] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.688077] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.688084] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.688090] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688097] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688104] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688110] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688116] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688122] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688129] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688135] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688143] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 3.688150] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.688157] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.688163] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.688169] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.688176] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.688182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.688188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.688195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.688201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.688208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.688214] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.688220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.688227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.688233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.688239] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.688246] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.688252] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.688258] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.688264] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.688271] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.688277] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.688283] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.688290] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.688296] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.688302] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.688309] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.688315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.688321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.688330] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688337] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688344] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688350] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688357] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.688363] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.688369] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.688375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.688382] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.688386] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 3.688411] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 3.688721] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.688741] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.689059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.689088] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.689107] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.689125] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 3.691950] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.691968] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 3.692263] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.692279] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.692557] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.692584] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.692588] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 3.692592] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 3.692612] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 3.693013] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.693367] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.694886] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.694906] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.694925] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.695202] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 3.701116] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.701642] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.701650] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.701657] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.701664] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.701855] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.701862] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.701870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.701877] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.701884] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701891] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701898] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701904] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701911] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701918] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701925] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701931] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701938] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 3.701945] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.701952] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.701959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.701965] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.701972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.701979] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.701986] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.701992] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.701999] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.702006] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.702013] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.702019] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.702026] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.702033] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.702039] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.702046] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.702053] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.702060] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.702066] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.702073] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.702080] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.702086] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.702093] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.702100] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.702106] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.702113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.702120] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.702127] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.702133] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702160] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.702167] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.702173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.702180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.702187] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.702191] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 3.702219] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 3.702518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.702538] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.702817] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.702840] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.702858] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.702876] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 3.705524] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.705544] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 3.705839] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.705857] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.706135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.706154] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.706159] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 3.706163] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 3.706183] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 3.706193] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 3.706203] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no [ 3.706211] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no [ 3.706219] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes [ 3.706226] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no [ 3.706234] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes [ 3.706241] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no [ 3.706248] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no [ 3.706256] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 3.706264] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 [ 3.706271] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 [ 3.706277] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.706284] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 [ 3.706291] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 [ 3.706298] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.706304] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config [ 3.706313] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) [ 3.706320] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) [ 3.706338] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 3.706348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000092327a12 state to 00000000fc0cb429 [ 3.706357] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ca6e974 state to 00000000fc0cb429 [ 3.706365] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000aea8f107 state to 00000000fc0cb429 [ 3.706373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000aea8f107 [ 3.706382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000e4b6e50 state to 00000000fc0cb429 [ 3.706389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000e4b6e50 [ 3.706397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000098d0b1b state to 00000000fc0cb429 [ 3.706405] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000374f38f state to 00000000fc0cb429 [ 3.706413] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ba689a33 state to 00000000fc0cb429 [ 3.706420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ba689a33 [ 3.706428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ae016691 state to 00000000fc0cb429 [ 3.706435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ae016691 [ 3.706443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002012d358 state to 00000000fc0cb429 [ 3.706451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000eb42cb6c state to 00000000fc0cb429 [ 3.706458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000eb42cb6c [ 3.706466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac043c4a state to 00000000fc0cb429 [ 3.706473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac043c4a [ 3.706481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000092327a12 [ 3.706489] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 3.706497] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000005b4f258 state to 00000000fc0cb429 [ 3.706505] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [NOCRTC] [ 3.706513] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [CRTC:51:pipe A] [ 3.706520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000098d0b1b [ 3.706528] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 3.706536] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ee6ef05 state to 00000000fc0cb429 [ 3.706543] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [NOCRTC] [ 3.706551] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [CRTC:72:pipe B] [ 3.706559] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 [ 3.706566] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 3.706573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000002012d358 [ 3.706581] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 3.706589] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 3.706597] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.706601] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.706605] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.706609] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.706636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.706659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.706675] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 3.713140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 3.713154] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 3.713179] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] [ 3.713188] [drm:drm_client_modeset_probe [drm]] [ 3.713202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 3.713233] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 3.713246] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 3.713251] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 3.713275] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 3.713582] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.713608] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.713894] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.713919] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.713941] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.713961] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 3.716582] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.716601] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 3.716897] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.716914] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.717193] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.717219] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.717223] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 3.717228] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 3.717250] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 3.717659] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.718014] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.719533] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.719553] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.719572] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.719697] sr 2:0:0:0: [sr0] scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray [ 3.719699] cdrom: Uniform CD-ROM driver Revision: 3.20 [ 3.719853] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 3.725765] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.726292] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.726302] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.726310] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.726317] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.726526] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.726533] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.726540] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.726547] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.726554] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726561] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726574] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726581] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726587] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726594] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726600] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726606] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 3.726613] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.726620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.726626] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.726633] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.726639] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.726646] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.726652] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.726659] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.726666] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.726672] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.726679] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.726685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.726692] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.726698] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.726705] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.726711] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.726718] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.726724] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.726731] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.726737] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.726744] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.726750] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.726757] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.726763] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.726770] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.726776] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.726783] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.726789] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.726796] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726802] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726809] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726815] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726822] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.726828] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.726835] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.726841] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.726848] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.726852] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 3.726874] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 3.727171] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.727191] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.727470] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.727492] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.727511] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.727530] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 3.730191] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.730209] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 3.730502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.730519] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.730796] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.730814] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.730818] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 3.730822] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 3.730841] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 3.731245] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.731600] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.733115] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.733135] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.733153] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.733432] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 3.735981] sr 2:0:0:0: Attached scsi CD-ROM sr0 [ 3.739342] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.739867] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.739875] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.739883] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.739889] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.740070] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.740077] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.740085] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.740092] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.740099] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740106] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740119] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740133] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740152] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 3.740159] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.740166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.740173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.740180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.740186] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.740193] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.740200] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.740206] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.740213] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.740220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.740227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.740233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.740240] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.740247] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.740254] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.740260] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.740267] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.740274] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.740280] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.740287] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.740294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.740301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.740307] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.740314] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.740321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.740328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.740334] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.740341] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.740348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740361] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.740381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.740388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.740395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.740401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.740405] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 3.740428] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 3.740726] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.740746] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.741027] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.741049] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.741068] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.741086] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 3.743693] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.743712] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 3.744007] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.744024] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.744301] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.744320] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.744324] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 3.744328] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 3.744346] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 3.744356] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 3.744365] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no [ 3.744373] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no [ 3.744380] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes [ 3.744387] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no [ 3.744394] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes [ 3.744400] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no [ 3.744407] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no [ 3.744415] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 3.744422] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 [ 3.744428] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 [ 3.744434] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.744441] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 [ 3.744447] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 [ 3.744453] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.744460] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config [ 3.744468] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) [ 3.744475] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) [ 3.744485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 3.744494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062abf8d7 state to 00000000fc0cb429 [ 3.744503] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 [ 3.744510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059907653 state to 00000000fc0cb429 [ 3.744518] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059907653 [ 3.744526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002b958a81 state to 00000000fc0cb429 [ 3.744533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002b958a81 [ 3.744541] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dff2ac2f state to 00000000fc0cb429 [ 3.744548] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 [ 3.744557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005ed6e442 state to 00000000fc0cb429 [ 3.744564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005ed6e442 [ 3.744571] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006d13a46c state to 00000000fc0cb429 [ 3.744578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006d13a46c [ 3.744586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000dc86a4bd state to 00000000fc0cb429 [ 3.744597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000002f6b4ed state to 00000000fc0cb429 [ 3.744604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000002f6b4ed [ 3.744611] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000009db6fe1 state to 00000000fc0cb429 [ 3.744618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000009db6fe1 [ 3.744626] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000062abf8d7 [ 3.744633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 3.744641] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 00000000fc0cb429 [ 3.744648] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] [ 3.744656] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] [ 3.744662] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000dff2ac2f [ 3.744670] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 3.744677] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000057c6efeb state to 00000000fc0cb429 [ 3.744685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [NOCRTC] [ 3.744692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [CRTC:72:pipe B] [ 3.744706] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000422ac28a state to 00000000fc0cb429 [ 3.744713] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000422ac28a [ 3.744719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000dc86a4bd [ 3.744727] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 3.744734] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 3.744741] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.744746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.744749] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.744753] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.744786] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.744808] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.744823] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 3.757962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 3.758007] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 3.760005] usb 1-11.3: new full-speed USB device number 9 using xhci_hcd [ 3.863221] usb 1-11.3: New USB device found, idVendor=056a, idProduct=0392, bcdDevice= 1.07 [ 3.863226] usb 1-11.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 3.863230] usb 1-11.3: Product: Wacom Intuos Pro S [ 3.863232] usb 1-11.3: Manufacturer: Wacom Co.,Ltd. [ 3.863235] usb 1-11.3: SerialNumber: 9IQ0111006826 [ 3.875163] hid-generic 0003:056A:0392.0005: hiddev1,hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 [ 3.878106] hid-generic 0003:056A:0392.0006: hiddev2,hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 [ 3.901638] input: Wacom Intuos Pro S Pen as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input8 [ 3.901775] input: Wacom Intuos Pro S Pad as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input10 [ 3.901851] wacom 0003:056A:0392.0005: hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 [ 3.902858] input: Wacom Intuos Pro S Finger as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.1/0003:056A:0392.0006/input/input12 [ 3.902979] wacom 0003:056A:0392.0006: hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 [ 3.943873] usb 1-12.1: new high-speed USB device number 10 using xhci_hcd [ 4.045574] usb 1-12.1: New USB device found, idVendor=16d0, idProduct=071a, bcdDevice= 1.96 [ 4.045583] usb 1-12.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.045586] usb 1-12.1: Product: Combo384 Amanero [ 4.045589] usb 1-12.1: Manufacturer: Amanero Technologies [ 4.045592] usb 1-12.1: SerialNumber: 413-001 [ 4.136728] process '/usr/bin/fstype' started with executable stack [ 4.149281] PM: Image not found (code -22) [ 4.267305] SGI XFS with ACLs, security attributes, realtime, quota, no debug enabled [ 4.270230] XFS (sda1): Mounting V5 Filesystem [ 4.283488] XFS (sda1): Ending clean mount [ 4.381935] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist. [ 4.466746] systemd[1]: Inserted module 'autofs4' [ 4.493716] systemd[1]: systemd 245.5-3 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=hybrid) [ 4.512168] systemd[1]: Detected architecture x86-64. [ 4.541853] systemd[1]: Set hostname to <hirez>. [ 4.676468] systemd[1]: /lib/systemd/system/dbus.socket:5: ListenStream= references a path below legacy directory /var/run/, updating /var/run/dbus/system_bus_socket ? /run/dbus/system_bus_socket; please update the unit file accordingly. [ 4.732617] systemd[1]: Created slice system-getty.slice. [ 4.732826] systemd[1]: Created slice system-modprobe.slice. [ 4.733006] systemd[1]: Created slice system-postfix.slice. [ 4.733241] systemd[1]: Created slice User and Session Slice. [ 4.733308] systemd[1]: Started Forward Password Requests to Wall Directory Watch. [ 4.733466] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. [ 4.733508] systemd[1]: Reached target User and Group Name Lookups. [ 4.733523] systemd[1]: Reached target Slices. [ 4.736775] systemd[1]: Listening on RPCbind Server Activation Socket. [ 4.737370] systemd[1]: Listening on Syslog Socket. [ 4.737434] systemd[1]: Listening on initctl Compatibility Named Pipe. [ 4.737838] systemd[1]: Listening on Journal Audit Socket. [ 4.737907] systemd[1]: Listening on Journal Socket (/dev/log). [ 4.737992] systemd[1]: Listening on Journal Socket. [ 4.738085] systemd[1]: Listening on udev Control Socket. [ 4.738133] systemd[1]: Listening on udev Kernel Socket. [ 4.738771] systemd[1]: Mounting Huge Pages File System... [ 4.739449] systemd[1]: Mounting POSIX Message Queue File System... [ 4.740120] systemd[1]: Mounting RPC Pipe File System... [ 4.741130] systemd[1]: Mounting Kernel Debug File System... [ 4.742089] systemd[1]: Mounting Kernel Trace File System... [ 4.742177] systemd[1]: Condition check resulted in Kernel Module supporting RPCSEC_GSS being skipped. [ 4.743057] systemd[1]: Starting Wait for network to be configured by ifupdown... [ 4.744088] systemd[1]: Starting Set the console keyboard layout... [ 4.744753] systemd[1]: Starting Create list of static device nodes for the current kernel... [ 4.744784] systemd[1]: Condition check resulted in Load Kernel Module drm being skipped. [ 4.745130] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped. [ 4.746296] systemd[1]: Starting Journal Service... [ 4.748422] systemd[1]: Starting Load Kernel Modules... [ 4.749115] systemd[1]: Starting Remount Root and Kernel File Systems... [ 4.749944] systemd[1]: Starting udev Coldplug all Devices... [ 4.751645] systemd[1]: Mounted Huge Pages File System. [ 4.751832] systemd[1]: Mounted POSIX Message Queue File System. [ 4.751979] systemd[1]: Mounted Kernel Debug File System. [ 4.752111] systemd[1]: Mounted Kernel Trace File System. [ 4.752618] systemd[1]: Finished Wait for network to be configured by ifupdown. [ 4.753157] systemd[1]: Finished Create list of static device nodes for the current kernel. [ 4.761518] lp: driver loaded but no devices found [ 4.763837] ppdev: user-space parallel port driver [ 4.771880] systemd[1]: Finished Load Kernel Modules. [ 4.772256] systemd[1]: Condition check resulted in FUSE Control File System being skipped. [ 4.772353] systemd[1]: Condition check resulted in Kernel Configuration File System being skipped. [ 4.772373] xfs filesystem being remounted at / supports timestamps until 2038 (0x7fffffff) [ 4.773269] systemd[1]: Starting Apply Kernel Variables... [ 4.773401] RPC: Registered named UNIX socket transport module. [ 4.773402] RPC: Registered udp transport module. [ 4.773402] RPC: Registered tcp transport module. [ 4.773403] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 4.775228] systemd[1]: Mounted RPC Pipe File System. [ 4.775747] systemd[1]: Finished Remount Root and Kernel File Systems. [ 4.776247] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped. [ 4.776285] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped. [ 4.777070] systemd[1]: Starting Load/Save Random Seed... [ 4.777955] systemd[1]: Starting Create System Users... [ 4.780674] systemd[1]: Finished Apply Kernel Variables. [ 4.793614] systemd[1]: Finished Load/Save Random Seed. [ 4.796908] systemd[1]: Finished Create System Users. [ 4.797598] systemd[1]: Starting Create Static Device Nodes in /dev... [ 4.802675] systemd[1]: Finished Set the console keyboard layout. [ 4.808929] systemd[1]: Finished Create Static Device Nodes in /dev. [ 4.809034] systemd[1]: Reached target Local File Systems (Pre). [ 4.809044] systemd[1]: Reached target Local File Systems. [ 4.809658] systemd[1]: Starting Load AppArmor profiles... [ 4.810278] systemd[1]: Starting Enable support for additional executable binary formats... [ 4.811095] systemd[1]: Starting Set console font and keymap... [ 4.811940] systemd[1]: Starting Preprocess NFS configuration... [ 4.812829] systemd[1]: Starting Tell Plymouth To Write Out Runtime Data... [ 4.812857] systemd[1]: Condition check resulted in Store a System Token in an EFI Variable being skipped. [ 4.812897] systemd[1]: Condition check resulted in Commit a transient machine-id on disk being skipped. [ 4.813667] systemd[1]: Starting udev Kernel Device Manager... [ 4.813843] systemd[1]: proc-sys-fs-binfmt_misc.automount: Got automount request for /proc/sys/fs/binfmt_misc, triggered by 350 (update-binfmts) [ 4.814689] systemd[1]: Mounting Arbitrary Executable File Formats File System... [ 4.815333] systemd[1]: Finished Set console font and keymap. [ 4.815579] systemd[1]: nfs-config.service: Succeeded. [ 4.815929] systemd[1]: Finished Preprocess NFS configuration. [ 4.816074] systemd[1]: Condition check resulted in RPC security service for NFS client and server being skipped. [ 4.816102] systemd[1]: Condition check resulted in RPC security service for NFS server being skipped. [ 4.816118] systemd[1]: Reached target NFS client services. [ 4.820384] systemd[1]: Mounted Arbitrary Executable File Formats File System. [ 4.824947] systemd[1]: Finished Enable support for additional executable binary formats. [ 4.825708] systemd[1]: Received SIGRTMIN+20 from PID 243 (plymouthd). [ 4.828330] systemd[1]: Finished Tell Plymouth To Write Out Runtime Data. [ 4.840263] audit: type=1400 audit(1591264850.416:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="firejail-default" pid=368 comm="apparmor_parser" [ 4.840263] systemd[1]: Finished udev Coldplug all Devices. [ 4.841296] systemd[1]: Starting Helper to synchronize boot up for ifupdown... [ 4.841705] audit: type=1400 audit(1591264850.416:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-senddoc" pid=372 comm="apparmor_parser" [ 4.843324] audit: type=1400 audit(1591264850.416:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="postgresql_akonadi" pid=370 comm="apparmor_parser" [ 4.843644] audit: type=1400 audit(1591264850.416:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-oopslash" pid=371 comm="apparmor_parser" [ 4.843772] systemd[1]: Finished Helper to synchronize boot up for ifupdown. [ 4.843977] audit: type=1400 audit(1591264850.420:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=369 comm="apparmor_parser" [ 4.843989] audit: type=1400 audit(1591264850.420:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=369 comm="apparmor_parser" [ 4.843990] audit: type=1400 audit(1591264850.420:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=369 comm="apparmor_parser" [ 4.844372] audit: type=1400 audit(1591264850.420:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-xpdfimport" pid=375 comm="apparmor_parser" [ 4.845764] audit: type=1400 audit(1591264850.420:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cups-browsed" pid=365 comm="apparmor_parser" [ 4.911836] systemd[1]: Finished Load AppArmor profiles. [ 4.912675] systemd[1]: Starting Raise network interfaces... [ 4.952184] systemd[1]: Finished Raise network interfaces. [ 4.954977] systemd[1]: Started udev Kernel Device Manager. [ 4.955663] systemd[1]: Starting Show Plymouth Boot Screen... [ 4.981642] systemd[1]: Started Show Plymouth Boot Screen. [ 4.981868] systemd[1]: Condition check resulted in Dispatch Password Requests to Console Directory Watch being skipped. [ 4.981983] systemd[1]: Started Forward Password Requests to Plymouth Directory Watch. [ 4.982014] systemd[1]: Reached target Local Encrypted Volumes. [ 5.003794] IPMI message handler: version 39.2 [ 5.007344] ipmi device interface [ 5.014857] ipmi_si: IPMI System Interface driver [ 5.014872] ipmi_si dmi-ipmi-si.0: ipmi_platform: probing via SMBIOS [ 5.014874] ipmi_platform: ipmi_si: SMBIOS: io 0xca2 regsize 1 spacing 1 irq 0 [ 5.014875] ipmi_si: Adding SMBIOS-specified kcs state machine [ 5.015655] ipmi_si IPI0001:00: ipmi_platform: probing via ACPI [ 5.015806] ipmi_si IPI0001:00: ipmi_platform: [io 0x0ca4] regsize 1 spacing 1 irq 0 [ 5.015807] ipmi_si: Adding ACPI-specified kcs state machine [ 5.015884] ipmi_si: Trying SMBIOS-specified kcs state machine at i/o address 0xca2, slave address 0x20, irq 0 [ 5.088154] EDAC MC0: Giving out device to module ie31200_edac controller IE31200: DEV 0000:00:00.0 (POLLED) [ 5.089876] sd 1:0:0:0: Attached scsi generic sg0 type 0 [ 5.090024] sr 2:0:0:0: Attached scsi generic sg1 type 5 [ 5.090192] sd 4:0:0:0: Attached scsi generic sg2 type 0 [ 5.090241] sd 4:0:0:1: Attached scsi generic sg3 type 0 [ 5.090266] sd 4:0:0:2: Attached scsi generic sg4 type 0 [ 5.090320] sd 4:0:0:3: Attached scsi generic sg5 type 0 [ 5.090373] sd 4:0:0:4: Attached scsi generic sg6 type 0 [ 5.091437] iTCO_vendor_support: vendor-support=0 [ 5.092650] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11 [ 5.092707] mei_me 0000:00:16.0: enabling device (0000 -> 0002) [ 5.092778] input: Microsoft X-Box 360 pad as /devices/pci0000:00/0000:00:14.0/usb1/1-14/1-14:1.0/input/input14 [ 5.092783] iTCO_wdt: unable to reset NO_REBOOT flag, device disabled by hardware/BIOS [ 5.092866] usbcore: registered new interface driver xpad [ 5.116588] mc: Linux media interface: v0.10 [ 5.141208] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer [ 5.141209] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules [ 5.141210] RAPL PMU: hw unit of domain package 2^-14 Joules [ 5.141211] RAPL PMU: hw unit of domain dram 2^-14 Joules [ 5.141211] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules [ 5.150008] systemd[1]: Found device Samsung_SSD_850_PRO_512GB 5. [ 5.159157] systemd[1]: Activating swap /dev/disk/by-uuid/602df9e6-40fb-41aa-b0df-96a9088df593... [ 5.186454] systemd[1]: Started Journal Service. [ 5.189868] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) [ 5.192407] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. [ 5.192408] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 2, val = -32767/0/1 [ 5.193209] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ef6f2003 [ 5.193220] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ea16da3d state to 00000000ef6f2003 [ 5.193230] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000088487cf7 state to 00000000ef6f2003 [ 5.193238] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028b01bfa state to 00000000ef6f2003 [ 5.193247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028b01bfa [ 5.193255] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008a2f3e8a state to 00000000ef6f2003 [ 5.193264] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008a2f3e8a [ 5.193294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000eb2a745f state to 00000000ef6f2003 [ 5.193315] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000faa616df state to 00000000ef6f2003 [ 5.193324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cbb299c1 state to 00000000ef6f2003 [ 5.193332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cbb299c1 [ 5.193353] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000079bcaa7c state to 00000000ef6f2003 [ 5.193361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000079bcaa7c [ 5.193369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000fb71ed5 state to 00000000ef6f2003 [ 5.193376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9cfd0f1 state to 00000000ef6f2003 [ 5.193384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9cfd0f1 [ 5.193393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007908e825 state to 00000000ef6f2003 [ 5.193401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007908e825 [ 5.193414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000ea16da3d [ 5.193422] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ef6f2003 [ 5.193431] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000018b0a306 state to 00000000ef6f2003 [ 5.193440] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [NOCRTC] [ 5.193447] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [CRTC:51:pipe A] [ 5.193463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000eb2a745f [ 5.193472] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ef6f2003 [ 5.193481] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000008dfecd46 state to 00000000ef6f2003 [ 5.193488] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [NOCRTC] [ 5.193496] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [CRTC:72:pipe B] [ 5.193507] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000fd253e01 state to 00000000ef6f2003 [ 5.193515] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000fd253e01 [ 5.193522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000fb71ed5 [ 5.193530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ef6f2003 [ 5.193538] [drm:drm_atomic_check_only [drm]] checking 00000000ef6f2003 [ 5.193549] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 5.193553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 5.193557] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 5.193561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 5.193595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 5.193618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 5.193635] [drm:drm_atomic_commit [drm]] committing 00000000ef6f2003 [ 5.196839] cryptd: max_cpu_qlen set to 1000 [ 5.196865] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. [ 5.196867] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 1, val = -32767/0/1 [ 5.197058] usbcore: registered new interface driver snd-usb-audio [ 5.208924] Adding 33442812k swap on /dev/sda5. Priority:-2 extents:1 across:33442812k SSFS [ 5.209024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ef6f2003 [ 5.209049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ef6f2003 [ 5.214980] systemd-journald[324]: Received client request to flush runtime journal. [ 5.232082] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9f8f61b [ 5.232093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d30af224 state to 00000000f9f8f61b [ 5.232103] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 00000000f9f8f61b [ 5.232112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a3a0e390 state to 00000000f9f8f61b [ 5.232121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a3a0e390 [ 5.232129] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000050c6aee state to 00000000f9f8f61b [ 5.232138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000050c6aee [ 5.232151] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000330ef6e state to 00000000f9f8f61b [ 5.232159] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a16f6bc3 state to 00000000f9f8f61b [ 5.232166] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bb4d02e2 state to 00000000f9f8f61b [ 5.232174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bb4d02e2 [ 5.232182] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a99d3259 state to 00000000f9f8f61b [ 5.232192] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a99d3259 [ 5.232200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c8e13b43 state to 00000000f9f8f61b [ 5.232207] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ece028f4 state to 00000000f9f8f61b [ 5.232215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ece028f4 [ 5.232222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000c21cbeb state to 00000000f9f8f61b [ 5.232232] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000c21cbeb [ 5.232240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000d30af224 [ 5.232250] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f9f8f61b [ 5.232264] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004431baab state to 00000000f9f8f61b [ 5.232274] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [NOCRTC] [ 5.232282] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [CRTC:51:pipe A] [ 5.232289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000330ef6e [ 5.232297] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f9f8f61b [ 5.232305] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000641aa27e state to 00000000f9f8f61b [ 5.232314] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [NOCRTC] [ 5.232322] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [CRTC:72:pipe B] [ 5.232331] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e1c94e20 state to 00000000f9f8f61b [ 5.232338] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e1c94e20 [ 5.232345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c8e13b43 [ 5.232353] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f9f8f61b [ 5.232362] [drm:drm_atomic_check_only [drm]] checking 00000000f9f8f61b [ 5.232373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 5.232377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 5.232381] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 5.232385] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 5.232421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 5.232445] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 5.232472] [drm:drm_atomic_commit [drm]] committing 00000000f9f8f61b [ 5.246294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9f8f61b [ 5.246308] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9f8f61b [ 5.268023] AVX2 version of gcm_enc/dec engaged. [ 5.268024] AES CTR mode by8 optimization enabled [ 5.278985] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC888-VD: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:line [ 5.278986] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 5.278987] snd_hda_codec_realtek hdaudioC0D0: hp_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: inputs: [ 5.278989] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 [ 5.293862] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 5.293885] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 5.293906] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 5.293928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 5.293948] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 5.293970] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 5.293988] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 5.295775] ipmi_si dmi-ipmi-si.0: The BMC does not support clearing the recv irq bit, compensating, but the BMC needs to be fixed. [ 5.312401] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1f.3/sound/card0/input15 [ 5.312465] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input16 [ 5.312514] input: HDA Intel PCH Front Line Out as /devices/pci0000:00/0000:00:1f.3/sound/card0/input17 [ 5.312560] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input18 [ 5.312604] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input19 [ 5.312651] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input20 [ 5.312690] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input21 [ 5.312737] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input22 [ 5.388997] ipmi_si dmi-ipmi-si.0: IPMI message handler: Found new BMC (man_id: 0x002a7c, prod_id: 0x0888, dev_id: 0x20) [ 5.430745] ipmi_si dmi-ipmi-si.0: IPMI kcs interface initialized [ 5.442072] ipmi_ssif: IPMI SSIF Interface driver [ 5.690895] intel_rapl_common: Found RAPL domain package [ 5.690897] intel_rapl_common: Found RAPL domain core [ 5.690899] intel_rapl_common: Found RAPL domain uncore [ 5.690900] intel_rapl_common: Found RAPL domain dram [ 6.053475] alg: No test for fips(ansi_cprng) (fips_ansi_cprng) [ 6.145869] Bluetooth: Core ver 2.22 [ 6.145879] NET: Registered protocol family 31 [ 6.145880] Bluetooth: HCI device and connection manager initialized [ 6.145883] Bluetooth: HCI socket layer initialized [ 6.145884] Bluetooth: L2CAP socket layer initialized [ 6.145886] Bluetooth: SCO socket layer initialized [ 6.256918] kauditd_printk_skb: 16 callbacks suppressed [ 6.256919] audit: type=1400 audit(1591264851.832:27): apparmor="DENIED" operation="capable" profile="/usr/sbin/cups-browsed" pid=724 comm="cups-browsed" capability=23 capname="sys_nice" [ 10.310500] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx [ 10.310581] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready [ 14.126521] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx [ 14.914834] FS-Cache: Loaded [ 14.953494] FS-Cache: Netfs 'nfs' registered for caching [ 14.956761] Key type dns_resolver registered [ 15.082476] NFS: Registering the id_resolver key type [ 15.082496] Key type id_resolver registered [ 15.082497] Key type id_legacy registered [ 15.296934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d166d111 [ 15.296974] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008bf5b86d state to 00000000d166d111 [ 15.297001] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 00000000bd8bd551 state to 00000000d166d111 [ 15.297024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000835fb348 state to 00000000d166d111 [ 15.297051] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000835fb348 [ 15.297077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008bf5b86d [ 15.297103] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d166d111 [ 15.297127] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000f4bb3954 state to 00000000d166d111 [ 15.297151] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [NOCRTC] [ 15.297173] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [CRTC:33:crtc-0] [ 15.297196] [drm:drm_atomic_check_only [drm]] checking 00000000d166d111 [ 15.297215] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 15.297228] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 15.297255] [drm:drm_atomic_commit [drm]] committing 00000000d166d111 [ 15.297321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d166d111 [ 15.297345] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d166d111 [ 15.297375] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 [ 15.297451] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004b92744e [ 15.297477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 000000004b92744e [ 15.297500] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed9cb119 state to 000000004b92744e [ 15.297522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000046234f6 state to 000000004b92744e [ 15.297547] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000046234f6 [ 15.297570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a35c929d state to 000000004b92744e [ 15.297594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a35c929d [ 15.297618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009d539ce0 state to 000000004b92744e [ 15.297640] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed29f6c9 state to 000000004b92744e [ 15.297662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 000000004b92744e [ 15.297685] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f [ 15.297707] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 000000004b92744e [ 15.297730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 15.297753] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000e89c017 state to 000000004b92744e [ 15.297774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000029001d73 state to 000000004b92744e [ 15.297797] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000029001d73 [ 15.297820] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000708b01e5 state to 000000004b92744e [ 15.297853] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000708b01e5 [ 15.297871] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f3527d8e [ 15.297888] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000004b92744e [ 15.297908] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000efae517b state to 000000004b92744e [ 15.297927] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [NOCRTC] [ 15.297944] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [CRTC:51:pipe A] [ 15.297961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009d539ce0 [ 15.297978] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000004b92744e [ 15.297996] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000033858fd0 state to 000000004b92744e [ 15.298013] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [NOCRTC] [ 15.298030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [CRTC:72:pipe B] [ 15.298048] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d397071c state to 000000004b92744e [ 15.298065] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d397071c [ 15.298081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000e89c017 [ 15.298098] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000004b92744e [ 15.298115] [drm:drm_atomic_check_only [drm]] checking 000000004b92744e [ 15.298143] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 15.298153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 15.298161] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 15.298170] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 15.298248] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 15.298299] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 15.298333] [drm:drm_atomic_commit [drm]] committing 000000004b92744e [ 15.313540] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004b92744e [ 15.313557] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004b92744e [ 15.330791] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 [ 15.330803] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000033ce3db8 [ 15.330813] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000008fdc242 state to 0000000033ce3db8 [ 15.330826] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000024c9c604 state to 0000000033ce3db8 [ 15.330836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000024c9c604 [ 15.330845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000063a0901f state to 0000000033ce3db8 [ 15.330854] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000063a0901f [ 15.330862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f9f236ad state to 0000000033ce3db8 [ 15.330870] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e1c94e20 state to 0000000033ce3db8 [ 15.330879] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001976c542 state to 0000000033ce3db8 [ 15.330887] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001976c542 [ 15.330895] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000023bce10 state to 0000000033ce3db8 [ 15.330903] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000023bce10 [ 15.330912] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d3ee8271 state to 0000000033ce3db8 [ 15.330919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000026db81c9 state to 0000000033ce3db8 [ 15.330927] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000026db81c9 [ 15.330940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003685cc7f state to 0000000033ce3db8 [ 15.330948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003685cc7f [ 15.330956] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f [ 15.330965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 [ 15.330974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009eadb78e state to 0000000033ce3db8 [ 15.330982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [NOCRTC] [ 15.330990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [CRTC:51:pipe A] [ 15.330998] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f9f236ad [ 15.331006] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 [ 15.331014] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ef54c858 state to 0000000033ce3db8 [ 15.331022] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [NOCRTC] [ 15.331030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [CRTC:72:pipe B] [ 15.331049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a16f6bc3 state to 0000000033ce3db8 [ 15.331057] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a16f6bc3 [ 15.331064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d3ee8271 [ 15.331072] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 [ 15.331080] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 [ 15.331092] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 15.331096] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 15.331100] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 15.331104] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 15.331140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 15.331173] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 15.331191] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 [ 15.346869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 [ 15.346883] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 [ 15.347242] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009bf2742d [ 15.347253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008c267a81 state to 000000009bf2742d [ 15.347264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 0000000042ba191e state to 000000009bf2742d [ 15.347275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000050ba9058 state to 000000009bf2742d [ 15.347285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000050ba9058 [ 15.347294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008c267a81 [ 15.347303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 000000009bf2742d [ 15.347311] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000002bd5700a state to 000000009bf2742d [ 15.347320] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [NOCRTC] [ 15.347328] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [CRTC:33:crtc-0] [ 15.347337] [drm:drm_atomic_check_only [drm]] checking 000000009bf2742d [ 15.347344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 15.347349] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 15.347359] [drm:drm_atomic_commit [drm]] committing 000000009bf2742d [ 15.347396] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009bf2742d [ 15.347405] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009bf2742d [ 15.347415] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 [ 15.358909] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 [ 15.358920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f6bb1f5 state to 0000000033ce3db8 [ 15.358931] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 0000000033ce3db8 [ 15.358939] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000002749498f state to 0000000033ce3db8 [ 15.358949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000002749498f [ 15.358961] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000006153d5d9 state to 0000000033ce3db8 [ 15.358980] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000006153d5d9 [ 15.358996] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006a05b5f7 state to 0000000033ce3db8 [ 15.359012] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d397071c state to 0000000033ce3db8 [ 15.359027] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cca4b9f0 state to 0000000033ce3db8 [ 15.359042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cca4b9f0 [ 15.359058] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009e05e90a state to 0000000033ce3db8 [ 15.359072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009e05e90a [ 15.359091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bc644261 state to 0000000033ce3db8 [ 15.359109] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000000e16ac42 state to 0000000033ce3db8 [ 15.359124] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000000e16ac42 [ 15.359140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ed4faf45 state to 0000000033ce3db8 [ 15.359155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ed4faf45 [ 15.359171] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008f6bb1f5 [ 15.359186] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 [ 15.359203] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000025aaf842 state to 0000000033ce3db8 [ 15.359223] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [NOCRTC] [ 15.359238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [CRTC:51:pipe A] [ 15.359254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006a05b5f7 [ 15.359270] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 [ 15.359285] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000a470917a state to 0000000033ce3db8 [ 15.359302] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [NOCRTC] [ 15.359323] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [CRTC:72:pipe B] [ 15.359340] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ed29f6c9 state to 0000000033ce3db8 [ 15.359358] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ed29f6c9 [ 15.359372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bc644261 [ 15.359388] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 [ 15.359403] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 [ 15.359433] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 15.359441] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 15.359449] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 15.359456] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 15.359505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 15.359557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 15.359583] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 [ 15.375008] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 [ 15.375022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 [ 15.405098] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.405480] [drm:intel_framebuffer_init [i915]] No Y tiling for legacy addfb [ 15.405515] [drm:drm_internal_framebuffer_create [drm]] could not create framebuffer [ 15.405547] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.405606] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.405820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 [ 15.405829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000053cd4a56 state to 00000000403c96a5 [ 15.405838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000053cd4a56 [ 15.405847] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 [ 15.405873] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 [ 15.405892] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 [ 15.405899] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 [ 15.405949] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 [ 15.405957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007a41a1eb state to 00000000403c96a5 [ 15.405965] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007a41a1eb [ 15.405972] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 [ 15.405980] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 [ 15.405991] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 [ 15.405998] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 [ 15.406048] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 [ 15.406055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000746efc3b state to 00000000403c96a5 [ 15.406064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000746efc3b [ 15.406071] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 [ 15.406078] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 [ 15.406089] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 [ 15.406095] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 [ 15.485516] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.486080] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a [ 15.486117] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040560145 state to 000000005e0e4b0a [ 15.486145] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a [ 15.486179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000044e6fdf state to 000000005e0e4b0a [ 15.486215] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a [ 15.491766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a [ 15.491810] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a [ 15.491933] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a [ 15.491973] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000577ba344 state to 000000005e0e4b0a [ 15.491999] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a [ 15.492030] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c21eb74a state to 000000005e0e4b0a [ 15.492064] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a [ 15.496975] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a [ 15.497010] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a [ 16.356678] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] [ 16.356693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] [ 16.356708] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.356722] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000548ffd9d state to 000000006e858879 [ 16.356739] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e1f1c0f1 state to 000000006e858879 [ 16.356764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000548ffd9d [ 16.356783] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000e1f1c0f1 [ 16.356800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006e858879 [ 16.356811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000030b3daa1 state to 000000006e858879 [ 16.356822] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [NOCRTC] [ 16.356832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [CRTC:51:pipe A] [ 16.356859] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.356868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 16.356874] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 16.356915] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 16.356943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm [ 16.356968] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 [ 16.356988] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 [ 16.357008] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 [ 16.357022] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.375313] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.375339] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 16.375389] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] [ 16.375408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] [ 16.375426] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.375445] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000040560145 state to 000000006e858879 [ 16.375461] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c8047799 state to 000000006e858879 [ 16.375481] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 0000000040560145 [ 16.375498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 00000000c8047799 [ 16.375514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006e858879 [ 16.375531] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000679f9f9c state to 000000006e858879 [ 16.375548] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [NOCRTC] [ 16.375564] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [CRTC:72:pipe B] [ 16.375583] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.375603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 16.375612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 16.375678] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 16.375718] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm [ 16.375749] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 [ 16.375779] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 [ 16.375838] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 [ 16.375862] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.380403] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.380432] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 16.466326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.466379] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c21eb74a state to 000000006e858879 [ 16.466420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000577ba344 state to 000000006e858879 [ 16.466461] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c21eb74a to [CRTC:51:pipe A] [ 16.466499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c21eb74a [ 16.466536] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.466670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 16.466727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c8a5ea85 state to 000000006e858879 [ 16.466807] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 16.466878] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 16.466943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 16.467007] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 16.467049] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.467221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.467261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 16.467316] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.467354] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e1f1c0f1 state to 000000006e858879 [ 16.467390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000548ffd9d state to 000000006e858879 [ 16.467430] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000e1f1c0f1 to [CRTC:72:pipe B] [ 16.467467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1f1c0f1 [ 16.467502] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.467614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 [ 16.467660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002570d1d3 state to 000000006e858879 [ 16.467736] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 16.467826] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 16.467926] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 16.467996] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 16.468047] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.468167] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.468223] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 17.212714] [drm:drm_mode_addfb2 [drm]] [FB:143] [ 17.262341] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 17.262375] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 17.262413] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 17.262454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 17.262494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 17.262529] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 17.262568] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 17.309802] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 17.325138] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 17.363673] [drm:drm_mode_addfb2 [drm]] [FB:144] [ 17.389030] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 17.389043] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e83b417b state to 000000004c5d43a8 [ 17.389056] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c7c74428 state to 000000004c5d43a8 [ 17.389066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000c7c74428 [ 17.389074] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 17.389129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 17.389159] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking [ 17.389353] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 17.389363] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004440fec8 state to 00000000ad3ae327 [ 17.389375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000339eee21 state to 00000000ad3ae327 [ 17.389384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000339eee21 [ 17.389392] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 17.389436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 17.389452] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking [ 17.391197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000000e9d0b2a [ 17.391354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 17.391422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1364291 [ 17.391485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 17.397162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 17.397187] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 17.405872] [drm:drm_mode_addfb2 [drm]] [FB:145] [ 17.407506] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 17.408550] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 17.408565] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a [ 17.408580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a [ 17.408590] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 17.408600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a [ 17.408611] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000246ed832 [ 17.408621] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a [ 17.408716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 17.408748] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking [ 17.408968] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 17.408980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 00000000505d8d8e [ 17.408990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae9d6619 state to 00000000505d8d8e [ 17.409000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000ae9d6619 [ 17.409009] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 17.409053] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 17.409068] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 17.413297] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 17.413439] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 17.413467] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 17.413503] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 17.413565] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 17.414011] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 17.414382] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 17.415995] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 17.416021] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 17.416045] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 17.416334] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 17.422310] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 17.422857] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.422873] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 17.422882] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 17.422890] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.423105] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.423116] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.423125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.423133] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.423147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423156] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423172] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423187] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423214] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423243] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423259] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 17.423276] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 17.423294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 17.423312] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 17.423329] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 17.423347] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 17.423364] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.423383] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.423398] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.423410] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.423424] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 17.423439] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 17.423448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.423456] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.423464] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 17.423473] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 17.423481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.423493] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.423500] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 17.423508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.423515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.423523] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.423530] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 17.423538] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 17.423545] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 17.423553] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 17.423560] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 17.423568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.423575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.423582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423590] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423597] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423605] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423612] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 17.423620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 17.423627] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.423635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.423642] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 17.423723] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 17.423770] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 17.424191] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 17.424555] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 17.425122] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a [ 17.425141] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a [ 17.426094] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 17.426117] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 17.426138] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 17.426420] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 17.430296] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 17.430309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 17.432359] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 17.432885] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.432895] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 17.432902] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 17.432909] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.433097] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.433104] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.433112] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.433119] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.433126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433132] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433139] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433159] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433173] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433181] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 17.433188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 17.433195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 17.433201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 17.433208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 17.433215] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 17.433221] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.433228] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.433235] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.433241] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.433248] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 17.433255] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 17.433261] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.433268] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.433275] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 17.433282] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 17.433288] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.433295] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.433301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 17.433308] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.433315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.433321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.433328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 17.433335] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 17.433342] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 17.433348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 17.433355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 17.433362] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.433368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.433375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 17.433408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 17.433414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.433421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.433428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 17.433471] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 17.433509] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 17.433520] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 17.433527] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 17.433550] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 17.433849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 17.433869] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 17.434149] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 17.434171] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 17.434191] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 17.434211] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 17.436907] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 17.436928] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 17.437223] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 17.437240] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 17.437518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 17.437537] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 17.437542] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 17.437550] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 17.437568] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 17.437863] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 17.437881] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 17.438159] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 17.438181] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 17.438199] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 17.438217] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 17.441061] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 17.441079] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 17.441325] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 17.441343] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 17.441621] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 17.441640] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 17.441644] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 17.441651] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 17.441669] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 17.441962] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 17.441979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 17.442257] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 17.442279] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 17.442296] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 17.442313] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 17.445210] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 17.445228] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 17.445474] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 17.445491] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 17.445708] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 17.445727] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 17.445731] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 19.033461] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 19.033498] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 0000000014564192 [ 19.033528] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003a6df13b state to 0000000014564192 [ 19.033539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000003a6df13b [ 19.033550] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 19.033613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 19.033632] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 19.033658] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 19.033668] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000cb785d4f [ 19.033699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000cb785d4f [ 19.033708] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005752a175 [ 19.033715] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 19.033841] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 19.033872] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 19.041962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 19.041981] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 19.047276] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 19.047303] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 20.006109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000009e366e46 [ 20.006141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.006159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004fa5331c [ 20.006182] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.016139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.016171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.016190] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.016223] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.026083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.026110] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.026125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.026148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.036073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.036098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.036113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.036136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.046072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.046097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.046112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.046135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.056072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.056097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.056112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.056135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.066083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.066108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.066123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.066146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.076072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.076096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.076111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.076134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.096072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.096097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.096112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.096135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.104071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.104096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.104110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.104134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.114071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.114096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.114111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.114134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.124071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.124097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.124111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.124135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.134070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.134095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.134109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.134133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.144072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.144097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.144112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.144136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.154070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.154095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.154110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.154133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.164071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.164095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.164110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.164133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.174076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.174101] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.174115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.174139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.184071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.184095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.184110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.184133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.194072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.194096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.194111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.194134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.204074] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.204099] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.204114] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.204138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.214071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.214095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.214110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.214133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.234073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.234098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.234112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.234135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.274070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.274096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.274111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.274135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.314088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.314124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.314142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.314166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.334077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.334104] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.334119] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.334142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.354068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.354093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.354108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.354130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.376068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.376093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.376108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.376131] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.394073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.394098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.394113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.394135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.416078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.416114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.416129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.416152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.422661] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 [ 20.422673] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000017b31376 state to 00000000c58cae11 [ 20.422683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000009d80489d state to 00000000c58cae11 [ 20.422695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000009d80489d [ 20.422710] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 [ 20.422856] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.422898] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking [ 20.422943] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 [ 20.422952] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c88e1744 state to 000000003fe34687 [ 20.422963] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a3a0e390 state to 000000003fe34687 [ 20.422972] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000a3a0e390 [ 20.422979] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 [ 20.423027] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.423038] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking [ 20.442150] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 [ 20.442172] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 [ 20.444199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 [ 20.444330] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.444367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 [ 20.444407] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.447302] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 [ 20.447322] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 [ 20.447342] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c [ 20.447364] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005a9a925a state to 0000000072b4047c [ 20.447382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000072b4047c [ 20.447401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000000f06e049 [ 20.447415] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c [ 20.447562] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.447597] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking [ 20.447635] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f12def7f [ 20.447648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000019eb48a0 state to 00000000f12def7f [ 20.447661] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000f12def7f [ 20.447672] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 [ 20.447682] [drm:drm_atomic_check_only [drm]] checking 00000000f12def7f [ 20.447804] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.447847] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f12def7f nonblocking [ 20.458776] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c [ 20.458805] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c [ 20.464009] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f12def7f [ 20.464033] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c [ 20.464062] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f12def7f [ 20.464080] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d5af1617 state to 0000000072b4047c [ 20.464097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008416fa19 state to 0000000072b4047c [ 20.464113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000008416fa19 [ 20.464129] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c [ 20.464285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.464318] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking [ 20.464369] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 20.464382] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 00000000cb785d4f [ 20.464393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac1a10e7 state to 00000000cb785d4f [ 20.464405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000ac1a10e7 [ 20.464417] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 20.464521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.464539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 20.475453] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c [ 20.475483] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c [ 20.476153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 [ 20.476220] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.476244] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 [ 20.476294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.480583] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 20.480602] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 20.480623] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 20.480648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ff2d6d95 state to 0000000014564192 [ 20.480667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ae9d6619 state to 0000000014564192 [ 20.480684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000ae9d6619 [ 20.480699] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 20.480847] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.480875] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 20.480904] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 20.480917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000505d8d8e [ 20.480932] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003a6df13b state to 00000000505d8d8e [ 20.480944] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003a6df13b [ 20.480955] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 20.481001] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.481025] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 20.492049] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 20.492073] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 20.497297] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 20.497326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a [ 20.497344] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 20.497358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a [ 20.497371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008112a9e3 state to 00000000ae0bb06a [ 20.497384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000008112a9e3 [ 20.497397] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a [ 20.497510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.497533] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking [ 20.497566] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff [ 20.497580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 0000000094adecff [ 20.497593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 0000000094adecff [ 20.497606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 [ 20.497616] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff [ 20.497695] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.497714] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking [ 20.506275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000010080940 [ 20.506427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.506500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000002603cbe2 [ 20.506557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.508755] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a [ 20.508773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a [ 20.513913] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff [ 20.513934] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff [ 20.513955] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a [ 20.513980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000ae0bb06a [ 20.513997] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a [ 20.514015] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000246ed832 [ 20.514028] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a [ 20.514142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.514173] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking [ 20.514201] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 20.514212] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000505d8d8e [ 20.514223] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000638906d4 state to 00000000505d8d8e [ 20.514235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000638906d4 [ 20.514247] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 20.514285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.514301] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 20.525405] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a [ 20.525425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a [ 20.530631] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 20.530656] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 20.530680] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 0000000014564192 [ 20.530693] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 20.530711] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000014564192 [ 20.530728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000000f06e049 [ 20.530743] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 20.530859] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.530884] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 20.530917] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 20.530930] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000cb785d4f [ 20.530941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008416fa19 state to 00000000cb785d4f [ 20.530953] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000008416fa19 [ 20.530963] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 20.531011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.531031] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 20.536073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 [ 20.536114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.536134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 [ 20.536168] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.542007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 20.542022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 20.547157] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 20.547169] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 20.554047] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 [ 20.554089] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.554106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 [ 20.554133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.947422] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f09b7a6e [ 20.947449] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f1af5452 state to 00000000f09b7a6e [ 20.947459] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057d750db state to 00000000f09b7a6e [ 20.947469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000057d750db [ 20.947479] [drm:drm_atomic_check_only [drm]] checking 00000000f09b7a6e [ 20.947522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.947539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f09b7a6e nonblocking [ 20.947567] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000b295a68 [ 20.947578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000fe6b27d8 state to 000000000b295a68 [ 20.947586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3db559a state to 000000000b295a68 [ 20.947595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000f3db559a [ 20.947602] [drm:drm_atomic_check_only [drm]] checking 000000000b295a68 [ 20.947692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.947707] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000b295a68 nonblocking [ 20.958693] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f09b7a6e [ 20.958709] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f09b7a6e [ 20.963851] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000b295a68 [ 20.963860] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000b295a68 [ 21.143151] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 21.143174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000046499d3 [ 21.143186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b830a5b4 state to 00000000046499d3 [ 21.143195] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000b830a5b4 [ 21.143205] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 21.143259] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.143281] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 21.143326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.143336] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf [ 21.143346] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 0000000064a524bf [ 21.143356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000fe3c3ec4 [ 21.143363] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.143448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.143465] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.158722] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 21.158733] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 21.163865] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.163876] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.317441] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 [ 21.317452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000590d9307 [ 21.317460] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 00000000590d9307 [ 21.317469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000005ba888f4 [ 21.317477] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 [ 21.317520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.317539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking [ 21.317562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.317578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e2607dec state to 0000000064a524bf [ 21.317588] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 0000000064a524bf [ 21.317598] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 [ 21.317606] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.317634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.317682] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.325356] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 [ 21.325365] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 [ 21.330594] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.330605] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.453357] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 21.453368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 000000008bd3a823 [ 21.453377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 [ 21.453386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000419d8fd6 [ 21.453428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 21.453462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.453476] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 21.453492] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 21.453532] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 [ 21.453560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 [ 21.453568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c [ 21.453577] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 21.453622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.453635] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 21.463882] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 21.463892] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 21.475399] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 21.475425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 21.637365] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 21.637400] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000008bd3a823 [ 21.637411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 [ 21.637420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 [ 21.637428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 21.637463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.637477] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 21.637525] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 21.637560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 [ 21.637575] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007ae821d2 state to 00000000cff3fe76 [ 21.637586] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000007ae821d2 [ 21.637596] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 21.637625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.637639] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 21.647227] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 21.647237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 21.658762] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 21.658773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 21.781319] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 21.781359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 00000000046499d3 [ 21.781367] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 00000000046499d3 [ 21.781375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 [ 21.781383] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 21.781435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.781450] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 21.781490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.781518] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf [ 21.781529] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 0000000064a524bf [ 21.781539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 [ 21.781547] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.781576] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.781612] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.792098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 21.792109] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 21.797229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.797242] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.941164] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.941174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf [ 21.941206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 0000000064a524bf [ 21.941215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000010080940 [ 21.941223] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.941263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.941280] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.941298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 21.941307] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 [ 21.941322] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 [ 21.941337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 [ 21.941345] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 21.941375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.941387] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 21.958730] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.958740] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.963967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 21.963978] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 22.037360] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 22.037370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000008bd3a823 [ 22.037402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 [ 22.037414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000f4690955 [ 22.037422] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 22.037456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.037470] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 22.037494] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 22.037552] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 [ 22.037560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 [ 22.037569] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c [ 22.037583] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 22.037620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.037633] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 22.047250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 22.047261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 22.058781] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 22.058792] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 22.237345] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 22.237355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 000000008bd3a823 [ 22.237363] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 [ 22.237372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000419d8fd6 [ 22.237380] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 22.237430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.237444] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 22.237460] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 22.237469] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 [ 22.237503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005ba888f4 state to 00000000cff3fe76 [ 22.237533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005ba888f4 [ 22.237550] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 22.237580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.237609] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 22.247260] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 22.247270] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 22.258795] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 22.258806] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 22.349362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 [ 22.349402] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000009f1364b2 [ 22.349412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007ae821d2 state to 000000009f1364b2 [ 22.349421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000007ae821d2 [ 22.349429] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 [ 22.349478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.349492] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking [ 22.349527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 22.349560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000046499d3 [ 22.349568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 00000000046499d3 [ 22.349578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 [ 22.349587] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 22.349614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.349638] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 22.358789] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 [ 22.358802] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 [ 22.363927] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 22.363940] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 22.429393] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 22.429406] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf [ 22.429440] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 0000000064a524bf [ 22.429449] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 [ 22.429456] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 22.429498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.429511] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 22.429532] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 22.429540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 [ 22.429547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 [ 22.429556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 [ 22.429563] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 22.429597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.429616] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 22.442367] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 22.442417] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 22.447561] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 22.447614] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 22.528747] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 [ 22.528805] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000009f1364b2 [ 22.528847] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000009f1364b2 [ 22.528891] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 0000000010080940 [ 22.528932] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 [ 22.529197] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.529272] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking [ 22.529370] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 [ 22.529413] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed110662 state to 00000000590d9307 [ 22.529452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000590d9307 [ 22.529494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c [ 22.529530] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 [ 22.529653] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.529710] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking [ 22.542364] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 [ 22.542414] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 [ 22.547589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 [ 22.547653] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 [ 23.009536] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000397d0932 [ 23.009568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000397d0932 [ 23.009587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 00000000397d0932 [ 23.009616] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 [ 23.009643] [drm:drm_atomic_check_only [drm]] checking 00000000397d0932 [ 23.009799] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 23.009865] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000397d0932 nonblocking [ 23.009938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 23.009955] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000008bd3a823 [ 23.009972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000419d8fd6 state to 000000008bd3a823 [ 23.009988] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000419d8fd6 [ 23.010003] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 23.010108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 23.010143] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 23.025518] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000397d0932 [ 23.025539] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000397d0932 [ 23.030677] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 23.030696] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 23.071823] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000050c6aee [ 23.071864] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 23.071900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c8e13b43 [ 23.071924] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 23.392525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000e59e4cfa [ 23.392582] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 23.392624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000057d750db [ 23.392689] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 23.607003] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 23.607025] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000003ce8e850 state to 00000000ad3ae327 [ 23.607036] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000ad3ae327 [ 23.607047] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000003ce8e850 to [NOCRTC] [ 23.607056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000003ce8e850 [ 23.607065] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 23.607134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 23.607157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000233ad802 state to 00000000ad3ae327 [ 23.607179] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 23.607195] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.607210] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.607229] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.607244] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 [ 23.624682] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 23.624698] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 23.624736] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 23.624745] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000024c9c604 state to 00000000ad3ae327 [ 23.624757] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 00000000ad3ae327 [ 23.624766] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 0000000024c9c604 to [NOCRTC] [ 23.624774] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000024c9c604 [ 23.624782] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 23.624840] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 [ 23.624868] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 00000000ad3ae327 [ 23.624886] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 23.624901] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.624933] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.624947] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.624957] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 [ 23.624984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 23.624993] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 23.736690] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 23.736728] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 23.736759] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 23.736792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 23.736817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 23.736845] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 23.736873] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 23.778545] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 23.800425] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 23.881716] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 25.150487] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 25.150587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007ede24bf state to 000000006e858879 [ 25.150641] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000006e858879 [ 25.150670] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007ede24bf to [CRTC:51:pipe A] [ 25.150717] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007ede24bf [ 25.150772] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 25.151167] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.151358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000caa1c353 state to 000000006e858879 [ 25.151721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.152004] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.152367] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.152468] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.152618] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 25.152866] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 25.152887] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 25.152974] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 25.152988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000bda1a70 state to 000000006e858879 [ 25.153008] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ea06c3a state to 000000006e858879 [ 25.153028] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 000000000bda1a70 to [CRTC:72:pipe B] [ 25.153048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:68:cursor B] state 000000000bda1a70 [ 25.153060] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 25.153217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 [ 25.153252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d5e0ab1c state to 000000006e858879 [ 25.153289] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.153313] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.153339] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.153361] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.153383] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 25.153438] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 25.153449] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 25.153980] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c [ 25.153999] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b830a5b4 state to 000000004178cf0c [ 25.154024] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 000000004178cf0c [ 25.154041] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000b830a5b4 to [NOCRTC] [ 25.154061] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b830a5b4 [ 25.154077] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c [ 25.154166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 25.154206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057b81693 state to 000000004178cf0c [ 25.154259] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 25.154300] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154379] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c [ 25.154444] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c [ 25.154460] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c [ 25.154493] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c [ 25.154515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000708b01e5 state to 000000004178cf0c [ 25.154536] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 000000004178cf0c [ 25.154560] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000708b01e5 to [NOCRTC] [ 25.154576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000708b01e5 [ 25.154587] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c [ 25.154631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 [ 25.154655] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ce0e84b state to 000000004178cf0c [ 25.154695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 25.154722] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154748] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154769] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154792] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c [ 25.154835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c [ 25.154848] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c [ 25.273763] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 [ 25.273802] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040a74b19 state to 00000000383de8b5 [ 25.273827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000303042be state to 00000000383de8b5 [ 25.273843] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000303042be [ 25.273859] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 [ 25.274049] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.274099] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking [ 25.274159] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 [ 25.274183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000f55d2354 [ 25.274209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009ff1aeec state to 00000000f55d2354 [ 25.274223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000009ff1aeec [ 25.274237] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 [ 25.274352] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.274385] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking [ 25.292269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 [ 25.292288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 [ 25.297446] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 [ 25.297472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 [ 25.297764] [drm:drm_mode_addfb2 [drm]] [FB:133] [ 25.309363] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 [ 25.309501] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000086edd36c state to 00000000590d9307 [ 25.309726] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007d32f8a2 state to 00000000590d9307 [ 25.309825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:31:plane 1A] state 000000007d32f8a2 [ 25.309919] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 [ 25.310337] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.310572] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking [ 25.311148] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 [ 25.311195] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 000000009f1364b2 [ 25.311226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000da8e7b56 state to 000000009f1364b2 [ 25.311247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:52:plane 1B] state 00000000da8e7b56 [ 25.311272] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 [ 25.311530] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.311615] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking [ 25.313976] audit: type=1400 audit(1591264870.888:28): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 [ 25.325815] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 [ 25.325907] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 [ 25.330935] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 [ 25.330979] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 [ 25.348755] audit: type=1400 audit(1591264870.924:29): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 [ 25.370627] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 25.370629] Bluetooth: BNEP filters: protocol multicast [ 25.370633] Bluetooth: BNEP socket layer initialized [ 25.375033] [drm:drm_mode_addfb2 [drm]] [FB:138] [ 25.375312] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] [ 25.375341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] [ 25.375361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 [ 25.375375] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004b47c821 state to 0000000033ce3db8 [ 25.375387] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006ac09869 state to 0000000033ce3db8 [ 25.375404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000006ac09869 [ 25.375420] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 [ 25.375436] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000001f8dd32 state to 0000000033ce3db8 [ 25.375454] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [NOCRTC] [ 25.375474] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [CRTC:51:pipe A] [ 25.375497] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 [ 25.375537] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 25.375552] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 25.375686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.375746] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 [ 25.392250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 [ 25.392268] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 [ 25.392303] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] [ 25.392323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] [ 25.392335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.392348] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 [ 25.392359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 [ 25.392372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 [ 25.392384] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 [ 25.392396] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000034523972 state to 000000009a35bdf3 [ 25.392410] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [NOCRTC] [ 25.392421] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [CRTC:72:pipe B] [ 25.392434] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.392444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 25.392450] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 25.392498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.392518] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 [ 25.397429] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.397444] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.397934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.397958] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005cff5841 state to 000000009a35bdf3 [ 25.397971] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.397987] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fa10941b state to 000000009a35bdf3 [ 25.398000] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 [ 25.414143] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.414156] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.414191] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] [ 25.414202] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] [ 25.414212] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.414223] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 [ 25.414232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 [ 25.414244] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:] for [CRTC:72:pipe B] state 00000000a5b8210f [ 25.414253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 [ 25.414265] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 [ 25.414277] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000083c2e296 state to 000000009a35bdf3 [ 25.414286] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [NOCRTC] [ 25.414295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [CRTC:72:pipe B] [ 25.414307] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.414316] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 25.414321] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 25.414366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.414381] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 [ 25.430771] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.430790] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.587615] [drm:drm_mode_addfb2 [drm]] [FB:137] [ 25.588562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000607204c5 [ 25.588594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 00000000607204c5 [ 25.588614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005aa8cfac state to 00000000607204c5 [ 25.588633] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000005aa8cfac [ 25.588649] [drm:drm_atomic_check_only [drm]] checking 00000000607204c5 [ 25.588824] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.588864] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000607204c5 nonblocking [ 25.589160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000006db89b4 [ 25.589182] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 0000000006db89b4 [ 25.589198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000ca4c9ba state to 0000000006db89b4 [ 25.589216] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000000ca4c9ba [ 25.589231] [drm:drm_atomic_check_only [drm]] checking 0000000006db89b4 [ 25.589319] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.589346] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000006db89b4 nonblocking [ 25.609114] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000607204c5 [ 25.609175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000607204c5 [ 25.614340] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000006db89b4 [ 25.614399] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000006db89b4 [ 25.631657] [drm:drm_mode_addfb2 [drm]] [FB:147] [ 25.632478] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a82a142d [ 25.632494] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000bfbd51fd state to 00000000a82a142d [ 25.632510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004b6af36c state to 00000000a82a142d [ 25.632526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004b6af36c [ 25.632545] [drm:drm_atomic_check_only [drm]] checking 00000000a82a142d [ 25.632706] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.632837] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a82a142d nonblocking [ 25.633235] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a9357def [ 25.633289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000780eaeb2 state to 00000000a9357def [ 25.633327] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ce7ebae0 state to 00000000a9357def [ 25.633378] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 00000000ce7ebae0 [ 25.633406] [drm:drm_atomic_check_only [drm]] checking 00000000a9357def [ 25.633671] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.633810] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a9357def nonblocking [ 25.659221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a82a142d [ 25.659354] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a82a142d [ 25.664414] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a9357def [ 25.664483] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 25.664520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000cb785d4f [ 25.664540] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a9357def [ 25.664556] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000024c9c604 state to 00000000cb785d4f [ 25.664570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000024c9c604 [ 25.664595] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 25.664849] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.664952] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 25.665286] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c [ 25.665325] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 0000000072b4047c [ 25.665373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 0000000072b4047c [ 25.665410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000002fdb83bd [ 25.665470] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c [ 25.665744] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.665883] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking [ 25.681106] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c [ 25.681311] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c [ 25.692362] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 25.692394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c329590e [ 25.692419] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 25.692437] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 00000000c329590e [ 25.692453] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002592f0c5 state to 00000000c329590e [ 25.692466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002592f0c5 [ 25.692479] [drm:drm_atomic_check_only [drm]] checking 00000000c329590e [ 25.692638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.692670] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c329590e nonblocking [ 25.692784] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.692797] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 000000009a35bdf3 [ 25.692808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000044e6fdf state to 000000009a35bdf3 [ 25.692820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000044e6fdf [ 25.692830] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.692941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.692966] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009a35bdf3 nonblocking [ 25.709084] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c329590e [ 25.709105] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c329590e [ 25.714310] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.714357] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.732545] [drm:drm_mode_addfb2 [drm]] [FB:148] [ 25.732641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 [ 25.732658] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cee74316 state to 000000003fe34687 [ 25.732679] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004ceca9e7 state to 000000003fe34687 [ 25.732693] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004ceca9e7 [ 25.732715] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 [ 25.732769] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.732802] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking [ 25.733102] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 [ 25.733225] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a7e0ad69 state to 00000000c58cae11 [ 25.733274] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002b75481e state to 00000000c58cae11 [ 25.733300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 000000002b75481e [ 25.733353] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 [ 25.733574] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.733722] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking [ 25.742433] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 [ 25.742504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 [ 25.747591] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 [ 25.747612] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 [ 25.747631] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 [ 25.747646] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 0000000033635145 [ 25.747660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000a08190f state to 0000000033635145 [ 25.747674] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:31:plane 1A] state 000000000a08190f [ 25.747686] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 [ 25.747857] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.747911] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking [ 25.748026] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f [ 25.748049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c56546ad state to 00000000e7507c6f [ 25.748062] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008ef93bc9 state to 00000000e7507c6f [ 25.748078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:52:plane 1B] state 000000008ef93bc9 [ 25.748091] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f [ 25.748209] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.748234] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e7507c6f nonblocking [ 25.759225] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 [ 25.759284] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 [ 25.764229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f [ 25.764250] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 [ 25.764265] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f [ 25.764284] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d304b4ce state to 00000000a72ea9e2 [ 25.764297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007150ba46 state to 00000000a72ea9e2 [ 25.764311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000007150ba46 [ 25.764322] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 [ 25.764463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.764494] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking [ 25.764530] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 25.764542] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7bb92f2 state to 000000004c5d43a8 [ 25.764552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a4812a5a state to 000000004c5d43a8 [ 25.764564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000a4812a5a [ 25.764574] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 25.764643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.764660] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking [ 25.792509] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 [ 25.792625] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 [ 25.797616] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 25.797650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 25.800508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 [ 25.800567] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000859f7d52 state to 0000000033635145 [ 25.800618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000065e53c0c state to 0000000033635145 [ 25.800656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000065e53c0c [ 25.800702] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 [ 25.800976] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.801119] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking [ 25.801505] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 [ 25.801543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 00000000f55d2354 [ 25.801584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a1a9a3bd state to 00000000f55d2354 [ 25.801609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000a1a9a3bd [ 25.801638] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 [ 25.801969] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.802166] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking [ 25.825728] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 [ 25.825748] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 [ 25.830902] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 [ 25.830932] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 [ 25.837586] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 25.837660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 00000000a7c3d9eb [ 25.837689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000de4c477a state to 00000000a7c3d9eb [ 25.837726] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000de4c477a [ 25.837761] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 25.837997] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.838175] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking [ 25.838378] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 25.838452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000006e8a3f03 [ 25.838489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c00467ed state to 000000006e8a3f03 [ 25.838516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000c00467ed [ 25.838580] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 25.838855] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.839042] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking [ 25.864311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 25.864356] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 25.875747] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 25.875867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 25.876790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9b8f040 [ 25.876815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ea06c3a state to 00000000f9b8f040 [ 25.876837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cc7821e8 state to 00000000f9b8f040 [ 25.876856] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000cc7821e8 [ 25.876876] [drm:drm_atomic_check_only [drm]] checking 00000000f9b8f040 [ 25.877085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.877133] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f9b8f040 nonblocking [ 25.877191] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 [ 25.877221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 000000005795e3f4 [ 25.877240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000466fb708 state to 000000005795e3f4 [ 25.877257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000466fb708 [ 25.877271] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 [ 25.877359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.877378] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking [ 25.909168] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9b8f040 [ 25.909283] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9b8f040 [ 25.914266] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 [ 25.914289] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 [ 25.933490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b [ 25.933516] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040ff38e3 state to 00000000d223d21b [ 25.933535] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002062a680 state to 00000000d223d21b [ 25.933551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002062a680 [ 25.933566] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b [ 25.933717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.933757] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking [ 25.933867] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 [ 25.933906] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005ea21f1d state to 000000005795e3f4 [ 25.933940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000038b73e52 state to 000000005795e3f4 [ 25.933995] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000038b73e52 [ 25.934034] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 [ 25.934359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.934554] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking [ 25.959269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b [ 25.959471] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b [ 25.964230] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 [ 25.964288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 [ 25.965190] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 [ 25.965227] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000383de8b5 [ 25.965252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a1a9a3bd state to 00000000383de8b5 [ 25.965276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000a1a9a3bd [ 25.965293] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 [ 25.965486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.965520] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking [ 25.965577] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 [ 25.965598] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000f55d2354 [ 25.965625] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3527d8e state to 00000000f55d2354 [ 25.965654] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000f3527d8e [ 25.965674] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 [ 25.965862] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.965959] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking [ 25.966673] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 [ 25.966697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bbab38cb state to 0000000033635145 [ 25.966723] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000033635145 [ 25.966747] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000bbab38cb to [CRTC:51:pipe A] [ 25.966765] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000bbab38cb [ 25.966785] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 [ 25.966981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.967029] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 0000000033635145 [ 25.967093] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.967142] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.967186] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.967233] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.967258] [drm:drm_atomic_commit [drm]] committing 0000000033635145 [ 25.970239] audit: type=1400 audit(1591264871.544:30): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 [ 25.971457] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f [ 25.971516] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ffb1c30d state to 00000000e7507c6f [ 25.971540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c56546ad state to 00000000e7507c6f [ 25.971557] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ffb1c30d to [CRTC:51:pipe A] [ 25.971574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:150] for [PLANE:47:cursor A] state 00000000ffb1c30d [ 25.971595] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f [ 25.971816] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.971916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035459c5a state to 00000000e7507c6f [ 25.972107] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.972162] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.972196] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.972235] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.972271] [drm:drm_atomic_commit [drm]] committing 00000000e7507c6f [ 25.976346] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d [ 25.976369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000056d83168 state to 000000000949282d [ 25.976387] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 000000000949282d [ 25.976401] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000056d83168 to [CRTC:51:pipe A] [ 25.976412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:151] for [PLANE:47:cursor A] state 0000000056d83168 [ 25.976424] [drm:drm_atomic_check_only [drm]] checking 000000000949282d [ 25.976565] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.976600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000000949282d [ 25.976650] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.976680] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.976701] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.976729] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.976744] [drm:drm_atomic_commit [drm]] committing 000000000949282d [ 25.981361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059bcf2ab [ 25.981377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000048a2243e state to 0000000059bcf2ab [ 25.981395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000059bcf2ab [ 25.981415] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000048a2243e to [CRTC:51:pipe A] [ 25.981427] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:152] for [PLANE:47:cursor A] state 0000000048a2243e [ 25.981439] [drm:drm_atomic_check_only [drm]] checking 0000000059bcf2ab [ 25.981587] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.981634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035f866f8 state to 0000000059bcf2ab [ 25.981732] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.981763] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.981793] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.981814] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.981833] [drm:drm_atomic_commit [drm]] committing 0000000059bcf2ab [ 25.986335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 [ 25.986358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 [ 25.986378] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 [ 25.986391] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] [ 25.986405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:153] for [PLANE:47:cursor A] state 000000007d32f8a2 [ 25.986419] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 [ 25.986566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.986601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 [ 25.986671] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.986697] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.986721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.986745] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.986760] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 [ 25.990116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059bcf2ab [ 25.990136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059bcf2ab [ 25.990147] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d [ 25.990160] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d [ 25.990183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f [ 25.990214] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f [ 25.990233] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 [ 25.990250] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 [ 25.991475] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 [ 25.991566] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 [ 25.991821] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 [ 25.992024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 [ 25.992099] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 [ 25.992156] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] [ 25.992212] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 000000007d32f8a2 [ 25.992229] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 [ 25.992294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.992311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 [ 25.992332] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 [ 25.992348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 [ 25.992378] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.992399] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.992427] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.992446] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.992459] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 [ 25.992502] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 [ 25.992514] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 [ 25.997491] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 [ 25.997513] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 [ 26.001019] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cd3e6c30 [ 26.001079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000cd3e6c30 [ 26.001104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000efc3561e state to 00000000cd3e6c30 [ 26.001122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000efc3561e [ 26.001139] [drm:drm_atomic_check_only [drm]] checking 00000000cd3e6c30 [ 26.001381] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.001424] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cd3e6c30 nonblocking [ 26.001502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 [ 26.001517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 00000000fb7b81d0 [ 26.001539] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000fb7b81d0 [ 26.001553] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000008a19b957 [ 26.001564] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 [ 26.001663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.001718] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fb7b81d0 nonblocking [ 26.025633] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cd3e6c30 [ 26.025657] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cd3e6c30 [ 26.031038] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 [ 26.031111] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 [ 26.032140] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d [ 26.032186] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002822e6ce state to 000000000949282d [ 26.032214] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 000000000949282d [ 26.032242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005ba888f4 [ 26.032278] [drm:drm_atomic_check_only [drm]] checking 000000000949282d [ 26.032460] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.032551] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000949282d nonblocking [ 26.032715] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 [ 26.032747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000048287824 [ 26.032774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000010080940 state to 0000000048287824 [ 26.032814] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000010080940 [ 26.032843] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 [ 26.033033] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.033133] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking [ 26.058971] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d [ 26.058986] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d [ 26.064135] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 [ 26.064151] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 [ 26.065142] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f [ 26.065161] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000db144c3f [ 26.065176] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003338987c state to 00000000db144c3f [ 26.065189] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003338987c [ 26.065202] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f [ 26.065341] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.065389] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking [ 26.065427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 [ 26.065439] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 0000000048287824 [ 26.065452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003d3598b9 state to 0000000048287824 [ 26.065464] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003d3598b9 [ 26.065477] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 [ 26.065545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.065571] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking [ 26.092355] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f [ 26.092369] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f [ 26.097513] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 [ 26.097527] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 [ 26.098050] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 26.098064] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7bb92f2 state to 000000004c5d43a8 [ 26.098076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f17f63d state to 000000004c5d43a8 [ 26.098088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000008f17f63d [ 26.098098] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 26.098144] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.098173] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking [ 26.098205] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 [ 26.098216] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d304b4ce state to 00000000a72ea9e2 [ 26.098226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000001a43d2f state to 00000000a72ea9e2 [ 26.098237] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000001a43d2f [ 26.098247] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 [ 26.098291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.098309] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking [ 26.125651] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 26.125679] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 26.130834] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 [ 26.130867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 [ 26.131366] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 26.131383] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 00000000ad3ae327 [ 26.131396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062957589 state to 00000000ad3ae327 [ 26.131409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000062957589 [ 26.131421] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 26.131472] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.131499] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking [ 26.131531] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 [ 26.131543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 000000009ab7d7a2 [ 26.131553] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e42a1bac state to 000000009ab7d7a2 [ 26.131565] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000e42a1bac [ 26.131577] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 [ 26.131662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.131685] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking [ 26.158952] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 26.158972] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 26.164140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 [ 26.164157] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 [ 26.164688] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 [ 26.164707] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c88e1744 state to 000000009ab7d7a2 [ 26.164721] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002b4570b0 state to 000000009ab7d7a2 [ 26.164732] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000002b4570b0 [ 26.164741] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 [ 26.164779] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.164794] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking [ 26.164817] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 26.164828] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cfd8c976 state to 00000000ad3ae327 [ 26.164837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000217fb779 state to 00000000ad3ae327 [ 26.164846] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000217fb779 [ 26.164854] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 26.164902] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.164925] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking [ 26.192294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 [ 26.192316] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 [ 26.197558] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 26.197586] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 26.198086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 [ 26.198107] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000005795e3f4 [ 26.198125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d5e0ab1c state to 000000005795e3f4 [ 26.198142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000d5e0ab1c [ 26.198161] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 [ 26.198224] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.198254] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking [ 26.198298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b [ 26.198316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 00000000d223d21b [ 26.198334] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001aa4b64b state to 00000000d223d21b [ 26.198353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001aa4b64b [ 26.198369] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b [ 26.198496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.198527] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking [ 26.214153] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b [ 26.214175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b [ 26.225632] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 [ 26.225662] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 [ 26.462632] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 [ 26.462656] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007d558a50 state to 00000000e7804b44 [ 26.462673] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 [ 26.462708] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006d587bbb state to 00000000e7804b44 [ 26.462727] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 [ 26.475706] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 [ 26.475726] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 [ 26.475759] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 [ 26.475794] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008598d75f state to 00000000e7804b44 [ 26.475808] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 [ 26.475829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 00000000e7804b44 [ 26.475857] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 [ 26.480907] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 [ 26.480929] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 [ 26.490104] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b [ 26.490125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000d223d21b [ 26.490143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000bda1a70 state to 00000000d223d21b [ 26.490160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000000bda1a70 [ 26.490174] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b [ 26.490263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.490296] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking [ 26.490379] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005b4fe663 [ 26.490395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 000000005b4fe663 [ 26.490412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ad4d2a9 state to 000000005b4fe663 [ 26.490432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000004ad4d2a9 [ 26.490446] [drm:drm_atomic_check_only [drm]] checking 000000005b4fe663 [ 26.490577] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.490612] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005b4fe663 nonblocking [ 26.508990] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b [ 26.509012] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b [ 26.514166] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005b4fe663 [ 26.514193] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005b4fe663 [ 27.203105] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 [ 27.203118] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 0000000048287824 [ 27.203128] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003d3598b9 state to 0000000048287824 [ 27.203138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003d3598b9 [ 27.203147] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 [ 27.203191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 27.203207] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking [ 27.203239] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f [ 27.203248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000db144c3f [ 27.203257] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006225429c state to 00000000db144c3f [ 27.203266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000006225429c [ 27.203274] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f [ 27.203327] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 27.203340] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking [ 27.214214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f [ 27.214237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f [ 27.225708] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 [ 27.225729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 [ 27.559248] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 27.559266] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000a7c3d9eb [ 27.559287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000048a2243e state to 00000000a7c3d9eb [ 27.559302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000048a2243e [ 27.559317] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 27.559457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 27.559500] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking [ 27.559579] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 [ 27.559595] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000073a3fc87 [ 27.559614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c26d3cf7 state to 0000000073a3fc87 [ 27.559630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000c26d3cf7 [ 27.559644] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 [ 27.559875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 27.559954] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking [ 27.564240] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 [ 27.564260] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 [ 27.575734] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 27.575758] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 27.673875] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006fb947e5 [ 27.673893] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000006fb947e5 [ 27.673907] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003def6fcc state to 000000006fb947e5 [ 27.673919] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003def6fcc [ 27.673930] [drm:drm_atomic_check_only [drm]] checking 000000006fb947e5 [ 27.674063] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 27.674111] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006fb947e5 nonblocking [ 27.674162] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000022edf81f [ 27.674180] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bfbd51fd state to 0000000022edf81f [ 27.674205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ba74e4f8 state to 0000000022edf81f [ 27.674221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000ba74e4f8 [ 27.674236] [drm:drm_atomic_check_only [drm]] checking 0000000022edf81f [ 27.674351] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 27.674383] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000022edf81f nonblocking [ 27.692395] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006fb947e5 [ 27.692416] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006fb947e5 [ 27.697567] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000022edf81f [ 27.697587] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000022edf81f [ 28.369864] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 [ 28.369881] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f4595bbc state to 00000000a72ea9e2 [ 28.369892] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e0f8f74a state to 00000000a72ea9e2 [ 28.369905] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000e0f8f74a [ 28.369917] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 [ 28.370044] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 28.370094] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking [ 28.370128] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e2245646 [ 28.370140] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000080a25d5d state to 00000000e2245646 [ 28.370155] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ec8b7f51 state to 00000000e2245646 [ 28.370165] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000ec8b7f51 [ 28.370173] [drm:drm_atomic_check_only [drm]] checking 00000000e2245646 [ 28.370236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 28.370259] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e2245646 nonblocking [ 28.392441] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 [ 28.392456] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 [ 28.397627] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e2245646 [ 28.397645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e2245646 [ 28.441580] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007c7bef8b [ 28.441593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 000000007c7bef8b [ 28.441602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 000000007c7bef8b [ 28.441619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000919acba8 [ 28.441636] [drm:drm_atomic_check_only [drm]] checking 000000007c7bef8b [ 28.441807] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 28.441857] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007c7bef8b nonblocking [ 28.441895] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e4cb9fa [ 28.441926] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004f0788b2 state to 000000009e4cb9fa [ 28.441949] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003cdbbe01 state to 000000009e4cb9fa [ 28.441966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003cdbbe01 [ 28.441983] [drm:drm_atomic_check_only [drm]] checking 000000009e4cb9fa [ 28.442129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 28.442151] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e4cb9fa nonblocking [ 28.459102] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007c7bef8b [ 28.459118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007c7bef8b [ 28.464290] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e4cb9fa [ 28.464312] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e4cb9fa [ 28.722641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 28.722655] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007b516bb0 state to 00000000cb785d4f [ 28.722664] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dfbf1324 state to 00000000cb785d4f [ 28.722675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000dfbf1324 [ 28.722684] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 28.722813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 28.722835] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 28.722882] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff [ 28.722908] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003cd98772 state to 0000000094adecff [ 28.722916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009beb6a90 state to 0000000094adecff [ 28.722941] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000009beb6a90 [ 28.722949] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff [ 28.723029] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 28.723064] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking [ 28.742477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 28.742503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 28.747618] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff [ 28.747633] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff [ 31.314482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 31.314504] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 33.564502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff [ 33.564557] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001450a92b state to 0000000094adecff [ 33.564599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fb9c3f95 state to 0000000094adecff [ 33.564642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000fb9c3f95 [ 33.564680] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff [ 33.564830] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 33.564895] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking [ 33.564991] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 33.565033] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d785a3ff state to 00000000cb785d4f [ 33.565068] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001694423a state to 00000000cb785d4f [ 33.565110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001694423a [ 33.565145] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 33.565280] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 33.565331] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 33.581360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 33.581410] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 33.592967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff [ 33.593018] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff [ 38.906236] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 38.906257] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fbb9145a state to 00000000a7c3d9eb [ 38.906277] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 38.906300] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031040ef6 state to 00000000a7c3d9eb [ 38.906317] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb [ 38.909717] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 38.909729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 38.909751] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 38.909763] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000036e370a5 state to 00000000a7c3d9eb [ 38.909772] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 38.909789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000021d5013d state to 00000000a7c3d9eb [ 38.909799] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb [ 38.914888] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 38.914897] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 38.919179] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 38.919191] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000dbca7270 state to 00000000a7c3d9eb [ 38.919200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f5920396 state to 00000000a7c3d9eb [ 38.919210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000f5920396 [ 38.919219] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 38.919269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 38.919283] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking [ 38.919307] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3b84e34 [ 38.919316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007a397cd1 state to 00000000d3b84e34 [ 38.919324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000d3b84e34 [ 38.919333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000008a19b957 [ 38.919340] [drm:drm_atomic_check_only [drm]] checking 00000000d3b84e34 [ 38.919369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 38.919380] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3b84e34 nonblocking [ 38.943037] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 38.943049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 38.948213] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3b84e34 [ 38.948227] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3b84e34 [ 41.313990] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 41.314011] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000dffa3a5 state to 000000006e8a3f03 [ 41.314024] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 41.314044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000311fb5cc state to 000000006e8a3f03 [ 41.314058] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 [ 41.326599] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 41.326616] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 41.326650] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 41.326666] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000006e8a3f03 [ 41.326677] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 41.326694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f678ed03 state to 000000006e8a3f03 [ 41.326708] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 [ 41.331765] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 41.331799] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 41.340881] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 41.340898] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b35cdb13 state to 0000000014564192 [ 41.340911] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002bd9f19b state to 0000000014564192 [ 41.340924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002bd9f19b [ 41.340936] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 41.341000] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 41.341031] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 41.341070] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 41.341083] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000505d8d8e [ 41.341093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000628b1791 state to 00000000505d8d8e [ 41.341106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000628b1791 [ 41.341117] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 41.341171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 41.341187] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 41.359835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 41.359858] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 41.365024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 41.365048] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 41.615782] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000336440de [ 41.615833] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 41.617086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 [ 41.617101] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000029690ea0 [ 41.617111] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 [ 41.617127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000043ec3708 state to 0000000029690ea0 [ 41.617139] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 [ 41.626562] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 [ 41.626572] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 [ 41.626602] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 [ 41.626612] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000029690ea0 [ 41.626620] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 [ 41.626634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dd5969b1 state to 0000000029690ea0 [ 41.626644] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 [ 41.631801] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 [ 41.631813] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 [ 41.636417] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 41.636431] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005cff5841 state to 000000006e8a3f03 [ 41.636443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f261da0 state to 000000006e8a3f03 [ 41.636455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005f261da0 [ 41.636465] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 41.636505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 41.636529] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking [ 41.636564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 [ 41.636574] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004b47c821 state to 0000000073a3fc87 [ 41.636583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005b73df2f state to 0000000073a3fc87 [ 41.636593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000005b73df2f [ 41.636601] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 [ 41.636649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 41.636661] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking [ 41.659846] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 41.659868] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 41.665021] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 [ 41.665038] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 [ 41.694775] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000b6d87631 [ 41.694823] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 42.188680] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 42.188751] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000568d4c state to 00000000ad3ae327 [ 42.188815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000041d1b185 state to 00000000ad3ae327 [ 42.188876] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000000568d4c to [NOCRTC] [ 42.188938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000568d4c [ 42.188994] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 42.189140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 42.189200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ccaa86bb state to 00000000ad3ae327 [ 42.189327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 42.189398] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 42.189464] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 42.189528] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 42.189570] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 [ 42.189702] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 42.189745] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 -------------- next part -------------- [ 1.187465] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported [ 1.187661] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.06 [ 1.187663] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.187664] usb usb1: Product: xHCI Host Controller [ 1.187665] usb usb1: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd [ 1.187666] usb usb1: SerialNumber: 0000:00:14.0 [ 1.187773] hub 1-0:1.0: USB hub found [ 1.187790] hub 1-0:1.0: 16 ports detected [ 1.187842] libata version 3.00 loaded. [ 1.191212] ahci 0000:00:17.0: version 3.0 [ 1.192724] ast 0000:06:00.0: enabling device (0140 -> 0143) [ 1.199510] pps pps0: new PPS source ptp0 [ 1.199542] igb 0000:04:00.0: added PHC on eth0 [ 1.199543] igb 0000:04:00.0: Intel(R) Gigabit Ethernet Network Connection [ 1.199545] igb 0000:04:00.0: eth0: (PCIe:2.5Gb/s:Width x1) 0c:c4:7a:cf:6c:d7 [ 1.199618] igb 0000:04:00.0: eth0: PBA No: 010B00-000 [ 1.199619] igb 0000:04:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s) [ 1.200298] igb 0000:04:00.0 eno2: renamed from eth0 [ 1.209686] [drm] Using P2A bridge for configuration [ 1.209701] [drm] AST 2400 detected [ 1.209713] [drm] Analog VGA only [ 1.209731] [drm] dram MCLK=408 Mhz type=1 bus_width=16 size=01000000 [ 1.209763] [TTM] Zone kernel: Available graphics memory: 16423934 KiB [ 1.209765] ahci 0000:00:17.0: AHCI 0001.0301 32 slots 4 ports 6 Gbps 0xf impl SATA mode [ 1.209765] [TTM] Zone dma32: Available graphics memory: 2097152 KiB [ 1.209766] ahci 0000:00:17.0: flags: 64bit ncq sntf led clo only pio slum part ems deso sadm sds apst [ 1.209767] [TTM] Initializing pool allocator [ 1.209775] [TTM] Initializing DMA pool allocator [ 1.210535] [drm:drm_client_modeset_probe [drm]] [ 1.210544] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] [ 1.210551] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] status updated from unknown to connected [ 1.214089] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter AST i2c bit bus [ 1.214125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "848x480": 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5 [ 1.214137] [drm:drm_mode_prune_invalid [drm]] Not using 848x480 mode: NOMODE [ 1.214145] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] probed modes : [ 1.214158] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.214170] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.214182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 [ 1.214195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.214209] [drm:drm_client_modeset_probe [drm]] connector 35 enabled? yes [ 1.214223] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 1.214236] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 35 [ 1.214248] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 35 0 [ 1.214261] [drm:drm_client_modeset_probe [drm]] found mode 1024x768 [ 1.214273] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 1920x2048 config [ 1.214286] [drm:drm_client_modeset_probe [drm]] desired mode 1024x768 set on crtc 33 (0,0) [ 1.214294] ast 0000:06:00.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane [ 1.214302] ast 0000:06:00.0: [drm:drm_fb_helper_generic_probe [drm_kms_helper]] surface width(1024), height(768) and bpp(32) [ 1.214322] [drm:drm_mode_addfb2 [drm]] [FB:36] [ 1.216083] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 [ 1.216098] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000706e661a state to 00000000d3c00277 [ 1.216111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000b376c70b state to 00000000d3c00277 [ 1.216125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000b376c70b [ 1.216139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 [ 1.216153] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1024x768] for [CRTC:33:crtc-0] state 000000000505a613 [ 1.216166] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane-0] state 00000000706e661a to [CRTC:33:crtc-0] [ 1.216179] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000706e661a [ 1.216192] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.216205] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000007c015743 state to 00000000d3c00277 [ 1.216219] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000007c015743 to [CRTC:33:crtc-0] [ 1.216231] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 [ 1.216240] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] mode changed [ 1.216246] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] enable changed [ 1.216252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] active changed [ 1.216258] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 1.216265] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] using [ENCODER:34:DAC-34] on [CRTC:33:crtc-0] [ 1.216271] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] needs all connectors, enable: y, active: y [ 1.216284] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.216296] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.216310] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 [ 1.317254] [drm:drm_atomic_helper_commit_modeset_disables [drm_kms_helper]] modeset on [ENCODER:34:DAC-34] [ 1.317708] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [CRTC:33:crtc-0] [ 1.321530] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [ENCODER:34:DAC-34] [ 1.321546] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 [ 1.321559] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 [ 1.321591] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 [ 1.321604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000009f032e5a state to 00000000d3c00277 [ 1.321616] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000005efad0e6 state to 00000000d3c00277 [ 1.321629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000033f48d87 state to 00000000d3c00277 [ 1.321642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000033f48d87 [ 1.321656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000009f032e5a [ 1.321669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.321682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000004014674f state to 00000000d3c00277 [ 1.321695] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [NOCRTC] [ 1.321708] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [CRTC:33:crtc-0] [ 1.321720] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 [ 1.321728] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 1.321734] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 1.321747] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 [ 1.321805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 [ 1.321818] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 [ 1.324095] e1000e 0000:00:1f.6 0000:00:1f.6 (uninitialized): registered PHC clock [ 1.324820] Console: switching to colour frame buffer device 128x48 [ 1.341554] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 [ 1.341567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000f7eff311 state to 00000000d3c00277 [ 1.341579] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 [ 1.341591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000d2da0efa state to 00000000d3c00277 [ 1.341605] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000d2da0efa [ 1.341619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000f7eff311 [ 1.341631] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 [ 1.341644] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000cebac407 state to 00000000d3c00277 [ 1.341657] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [NOCRTC] [ 1.341670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [CRTC:33:crtc-0] [ 1.341682] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 [ 1.341690] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 1.341696] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 1.341709] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 [ 1.341749] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 [ 1.341761] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 [ 1.344652] ast 0000:06:00.0: fb0: astdrmfb frame buffer device [ 1.366247] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 1.366250] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 [ 1.366253] xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed [ 1.366292] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.06 [ 1.366293] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 1.366294] usb usb2: Product: xHCI Host Controller [ 1.366295] usb usb2: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd [ 1.366296] usb usb2: SerialNumber: 0000:00:14.0 [ 1.366371] scsi host0: ahci [ 1.366512] hub 2-0:1.0: USB hub found [ 1.366540] hub 2-0:1.0: 10 ports detected [ 1.366542] scsi host1: ahci [ 1.366632] scsi host2: ahci [ 1.366704] scsi host3: ahci [ 1.366744] ata1: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c100 irq 134 [ 1.366746] ata2: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c180 irq 134 [ 1.366747] ata3: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c200 irq 134 [ 1.366748] ata4: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c280 irq 134 [ 1.367439] usb: port power management may be unreliable [ 1.390078] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 1024K [ 1.390116] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]] enable_guc=0 (guc:no submission:no huc:no) [ 1.390147] [drm:i915_gem_init_early [i915]] fake context support initialized [ 1.390174] i915 0000:00:02.0: [drm:intel_pch_type [i915]] Found SunrisePoint PCH [ 1.390207] [drm:intel_power_domains_init [i915]] Allowed DC state mask 02 [ 1.390244] i915 0000:00:02.0: [drm:intel_uncore_init_mmio [i915]] unclaimed mmio detected on uncore init, clearing [ 1.390619] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M [ 1.390645] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M [ 1.390669] [drm:i915_ggtt_probe_hw [i915]] DSM size = 32M [ 1.390670] i915 0000:00:02.0: VT-d active for gfx access [ 1.390671] i915 0000:00:02.0: vgaarb: deactivate vga console [ 1.390754] [drm:init_stolen [i915]] GEN6_STOLEN_RESERVED = 8f700047 [ 1.390788] [drm:init_stolen [i915]] Memory reserved for graphics device: 32768K, usable: 31744K [ 1.390818] [drm:intel_gt_init_workarounds [i915]] Initialized 4 GT workarounds on global [ 1.390868] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params [ 1.390899] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8b82a018 [ 1.390933] [drm:intel_opregion_setup [i915]] ACPI OpRegion version 2.0.0 [ 1.390962] [drm:intel_opregion_setup [i915]] Public ACPI methods supported [ 1.390989] [drm:intel_opregion_setup [i915]] SWSCI supported [ 1.392097] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483 [ 1.392125] [drm:intel_opregion_setup [i915]] ASLE supported [ 1.392152] [drm:intel_opregion_setup [i915]] ASLE extension supported [ 1.392179] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4) [ 1.392203] [drm:i915_driver_probe [i915]] DRAM type: DDR4 [ 1.392227] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no [ 1.392249] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no [ 1.392271] [drm:skl_dram_get_channel_info [i915]] CH0 ranks: 2, 16Gb DIMMs: no [ 1.392292] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no [ 1.392313] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no [ 1.392332] [drm:skl_dram_get_channel_info [i915]] CH1 ranks: 2, 16Gb DIMMs: no [ 1.392352] [drm:i915_driver_probe [i915]] Memory configuration is symmetric? yes [ 1.392371] [drm:i915_driver_probe [i915]] DRAM bandwidth: 34133344 kBps, channels: 2 [ 1.392391] [drm:i915_driver_probe [i915]] DRAM ranks: 2, 16Gb DIMMs: no [ 1.392391] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 1.392392] [drm] Driver supports precise vblank timestamp query. [ 1.392424] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz [ 1.392456] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE ", BDB version 205 [ 1.392487] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 [ 1.392517] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 [ 1.392547] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68d6 [ 1.392575] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 [ 1.392604] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 [ 1.392632] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68c6 [ 1.392985] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0) [ 1.393028] [drm:intel_bios_init [i915]] Panel type: 2 (VBT) [ 1.393056] [drm:intel_bios_init [i915]] DRRS supported mode is static [ 1.393085] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT legacy lfp table: [ 1.393098] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa [ 1.393126] [drm:intel_bios_init [i915]] VBT initial LVDS value 300 [ 1.393154] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0 [ 1.393181] [drm:intel_bios_init [i915]] DRRS State Enabled:1 [ 1.393209] [drm:intel_bios_init [i915]] Skipping SDVO device mapping [ 1.393237] [drm:intel_bios_init [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393264] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8 [ 1.393292] [drm:intel_bios_init [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393318] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8 [ 1.393346] [drm:intel_bios_init [i915]] Port D VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393373] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8 [ 1.393400] [drm:intel_bios_init [i915]] Port E VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [ 1.393427] [drm:intel_bios_init [i915]] VBT HDMI level shift for port E: 0 [ 1.393534] [drm:intel_dsm_detect [i915]] no _DSM method for intel device [ 1.393577] [drm:intel_power_domains_init_hw [i915]] rawclk rate: 24000 kHz [ 1.393610] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 [ 1.393643] [drm:intel_power_well_enable [i915]] enabling power well 1 [ 1.393675] [drm:intel_power_well_enable [i915]] enabling MISC IO power well [ 1.393708] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 [ 1.393740] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz [ 1.393770] [drm:intel_cdclk_init [i915]] Max dotclock rate: 675000 kHz [ 1.393813] [drm:intel_power_well_enable [i915]] enabling always-on [ 1.393843] [drm:intel_power_well_enable [i915]] enabling DC off [ 1.393873] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 [ 1.393906] [drm:intel_power_well_enable [i915]] enabling power well 2 [ 1.393909] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=io+mem [ 1.393964] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well [ 1.394014] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well [ 1.394042] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well [ 1.394069] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well [ 1.394113] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_27.bin [ 1.394155] i915 0000:00:02.0: firmware: direct-loading firmware i915/skl_dmc_ver1_27.bin [ 1.394459] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_27.bin (v1.27) [ 1.394625] [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled [ 1.394695] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 [ 1.394722] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec) [ 1.394745] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec) [ 1.394767] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec) [ 1.394788] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec) [ 1.394808] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec) [ 1.394828] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec) [ 1.394848] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec) [ 1.394867] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec) [ 1.394988] [drm:intel_modeset_init [i915]] 3 display pipes available. [ 1.395056] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 [ 1.395385] [drm:intel_modeset_init [i915]] VBT says port A is not DVI/HDMI/DP compatible, respect it [ 1.395421] [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (VBT) [ 1.395451] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:94:DDI B] [ 1.395488] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:94:DDI B] [ 1.395516] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT) [ 1.395550] [drm:intel_bios_port_aux_ch [i915]] using AUX C for port C (VBT) [ 1.395578] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:109:DDI C] [ 1.395609] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:109:DDI C] [ 1.395636] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT) [ 1.395669] [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT) [ 1.395697] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:119:DDI D] [ 1.395727] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:119:DDI D] [ 1.395754] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT) [ 1.395816] [drm:intel_bios_port_aux_ch [i915]] using AUX A for port E (VBT) [ 1.395862] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:129:DDI E] [ 1.395917] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:51:pipe A] hw state readout: enabled [ 1.395960] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:72:pipe B] hw state readout: disabled [ 1.396018] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:93:pipe C] hw state readout: disabled [ 1.396064] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] hw state readout: disabled, pipe A [ 1.396065] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 0c:c4:7a:cf:6c:d6 [ 1.396066] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection [ 1.396107] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] hw state readout: disabled, pipe A [ 1.396162] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] hw state readout: disabled, pipe A [ 1.396213] e1000e 0000:00:1f.6 eth0: MAC: 12, PHY: 12, PBA No: 010BFF-0FF [ 1.396274] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] hw state readout: disabled, pipe B [ 1.396309] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] hw state readout: disabled, pipe B [ 1.396355] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] hw state readout: disabled, pipe B [ 1.396437] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] hw state readout: disabled, pipe C [ 1.396511] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] hw state readout: disabled, pipe C [ 1.396559] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] hw state readout: disabled, pipe C [ 1.396597] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1 [ 1.396641] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000001, on 1 [ 1.396695] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0 [ 1.396736] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0 [ 1.396777] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:94:DDI B] hw state readout: disabled, pipe A [ 1.396820] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:96:DP-MST A] hw state readout: disabled, pipe A [ 1.396861] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:97:DP-MST B] hw state readout: disabled, pipe B [ 1.396907] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:98:DP-MST C] hw state readout: disabled, pipe C [ 1.396908] e1000e 0000:00:1f.6 eno1: renamed from eth0 [ 1.396988] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:109:DDI C] hw state readout: enabled, pipe A [ 1.397033] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:111:DP-MST A] hw state readout: disabled, pipe A [ 1.397083] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:112:DP-MST B] hw state readout: disabled, pipe B [ 1.397134] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:113:DP-MST C] hw state readout: disabled, pipe C [ 1.397184] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:119:DDI D] hw state readout: disabled, pipe A [ 1.397234] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:121:DP-MST A] hw state readout: disabled, pipe A [ 1.397284] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:122:DP-MST B] hw state readout: disabled, pipe B [ 1.397333] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:123:DP-MST C] hw state readout: disabled, pipe C [ 1.397383] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:129:DDI E] hw state readout: disabled, pipe A [ 1.397433] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:95:DP-1] hw state readout: disabled [ 1.397484] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:104:HDMI-A-1] hw state readout: disabled [ 1.397536] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:110:DP-2] hw state readout: enabled [ 1.397588] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:116:HDMI-A-2] hw state readout: disabled [ 1.397638] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:120:DP-3] hw state readout: disabled [ 1.397688] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:126:HDMI-A-3] hw state readout: disabled [ 1.397737] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:130:DP-4] hw state readout: disabled [ 1.397764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 0000000016992e5d [ 1.397814] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] min_cdclk 0 kHz [ 1.397864] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] min_cdclk 0 kHz [ 1.397913] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] min_cdclk 0 kHz [ 1.397964] [drm:intel_modeset_setup_hw_state [i915]] pipe A data rate 0 num active planes 0 [ 1.398014] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] min_cdclk 0 kHz [ 1.398063] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] min_cdclk 0 kHz [ 1.398112] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] min_cdclk 0 kHz [ 1.398161] [drm:intel_modeset_setup_hw_state [i915]] pipe B data rate 0 num active planes 0 [ 1.398211] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] min_cdclk 0 kHz [ 1.398259] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] min_cdclk 0 kHz [ 1.398308] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] min_cdclk 0 kHz [ 1.398357] [drm:intel_modeset_setup_hw_state [i915]] pipe C data rate 0 num active planes 0 [ 1.398413] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [setup_hw_state] [ 1.398465] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB [ 1.398516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 1.398568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 517734, link_n: 524288, tu: 64 [ 1.398618] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0 [ 1.398667] [drm:intel_dump_pipe_config [i915]] requested mode: [ 1.398685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 720 3902 3950 4000 400 2163 2168 2222 0x40 0x9 [ 1.398735] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 1.398752] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 3840 3902 3950 4000 2160 2163 2168 2222 0x40 0x9 [ 1.398803] [drm:intel_dump_pipe_config [i915]] crtc timings: 533249 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x40 flags: 0x9 [ 1.398853] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 720x400, pixel rate 533249 [ 1.398903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 [ 1.398952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0f000870, enabled, force thru: no [ 1.399001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 1.399051] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 1.399100] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 [ 1.399149] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> [ 1.399199] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: no [setup_hw_state] [ 1.399248] [drm:intel_dump_pipe_config [i915]] [CRTC:93:pipe C] enable: no [setup_hw_state] [ 1.399299] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling [ 1.399340] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff7e1cca [ 1.399359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000197e100e state to 00000000ff7e1cca [ 1.399376] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000ff7e1cca [ 1.399393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000aef36d99 state to 00000000ff7e1cca [ 1.399410] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000069886caf state to 00000000ff7e1cca [ 1.399426] [drm:drm_atomic_check_only [drm]] checking 00000000ff7e1cca [ 1.399485] [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:51 [ 1.399504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002ca0145a state to 00000000ff7e1cca [ 1.399520] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a93965e7 state to 00000000ff7e1cca [ 1.399536] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008fa1e3fc state to 00000000ff7e1cca [ 1.399552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae2843ea state to 00000000ff7e1cca [ 1.399567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000afe69d21 state to 00000000ff7e1cca [ 1.399582] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a4be912 state to 00000000ff7e1cca [ 1.399597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002017bf88 state to 00000000ff7e1cca [ 1.399612] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000977f527e state to 00000000ff7e1cca [ 1.399627] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000059814b3a state to 00000000ff7e1cca [ 1.399679] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 [ 1.399727] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.399773] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.399867] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.399911] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.399954] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.399997] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400039] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400082] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400123] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400165] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400206] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400247] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400288] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400329] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400370] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400411] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400451] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400492] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400533] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400573] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400613] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400654] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400735] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400775] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400816] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400857] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400897] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.400936] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.400977] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401017] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401057] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401096] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 1.401137] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401177] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401217] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 1.401236] [drm:drm_atomic_commit [drm]] committing 00000000ff7e1cca [ 1.403979] [drm] Initialized ast 0.1.0 20120228 for 0000:06:00.0 on minor 0 [ 1.417469] [drm:i915_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000] [ 1.419056] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff7e1cca [ 1.419076] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff7e1cca [ 1.419161] [drm:intel_engine_init_workarounds [i915]] Initialized 5 engine workarounds on rcs'0 [ 1.419213] [drm:intel_engine_init_whitelist [i915]] Initialized 5 whitelist workarounds on rcs'0 [ 1.419264] [drm:intel_engine_init_ctx_wa [i915]] Initialized 12 context workarounds on rcs'0 [ 1.420147] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping [ 1.420202] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping [ 1.420253] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping [ 1.420305] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config [ 1.420418] [drm:intel_engines_driver_register [i915]] renamed rcs'0 to rcs0 [ 1.420466] [drm:intel_engines_driver_register [i915]] renamed bcs'0 to bcs0 [ 1.420513] [drm:intel_engines_driver_register [i915]] renamed vcs'0 to vcs0 [ 1.420558] [drm:intel_engines_driver_register [i915]] renamed vecs'0 to vecs0 [ 1.421101] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card1-DP-1 [ 1.421269] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card1-DP-2 [ 1.421470] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card1-DP-3 [ 1.421665] [drm:intel_dp_connector_register [i915]] registering DPDDC-E bus for card1-DP-4 [ 1.421746] [drm] Initialized i915 1.6.0 20200114 for 0000:00:02.0 on minor 1 [ 1.421881] [drm:intel_opregion_resume [i915]] 7 outputs detected [ 1.424122] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 1.424463] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3 [ 1.424632] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well [ 1.424650] [drm:drm_client_modeset_probe [drm]] [ 1.424733] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well [ 1.424743] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 1.424798] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 1.424851] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well [ 1.424855] i915 device info: pciid=0x191d rev=0x06 platform=SKYLAKE (subplatform=0x0) gen=9 [ 1.424857] i915 device info: engines: 47 [ 1.424857] i915 device info: gen: 9 [ 1.424858] i915 device info: gt: 2 [ 1.424859] i915 device info: iommu: enabled [ 1.424860] i915 device info: memory-regions: 5 [ 1.424861] i915 device info: page-sizes: 11000 [ 1.424861] i915 device info: platform: SKYLAKE [ 1.424869] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] status updated from unknown to disconnected [ 1.424869] i915 device info: ppgtt-size: 48 [ 1.424870] i915 device info: ppgtt-type: 2 [ 1.424871] i915 device info: is_mobile: no [ 1.424872] i915 device info: is_lp: no [ 1.424873] i915 device info: require_force_probe: no [ 1.424879] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 1.424880] i915 device info: is_dgfx: no [ 1.424900] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 1.424901] i915 device info: has_64bit_reloc: yes [ 1.424902] i915 device info: gpu_reset_clobbers_display: no [ 1.424903] i915 device info: has_reset_engine: yes [ 1.424904] i915 device info: has_fpga_dbg: yes [ 1.424905] i915 device info: has_global_mocs: no [ 1.424919] i915 device info: has_gt_uc: yes [ 1.424920] i915 device info: has_l3_dpf: no [ 1.424921] i915 device info: has_llc: yes [ 1.424922] i915 device info: has_logical_ring_contexts: yes [ 1.424923] i915 device info: has_logical_ring_elsq: no [ 1.424959] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 1.424960] i915 device info: has_logical_ring_preemption: yes [ 1.424961] i915 device info: has_pooled_eu: no [ 1.424962] i915 device info: has_rc6: yes [ 1.424963] i915 device info: has_rc6p: no [ 1.424963] i915 device info: has_rps: yes [ 1.424964] i915 device info: has_runtime_pm: yes [ 1.424965] i915 device info: has_snoop: no [ 1.424966] i915 device info: has_coherent_ggtt: yes [ 1.424967] i915 device info: unfenced_needs_alignment: no [ 1.424968] i915 device info: hws_needs_physical: no [ 1.424969] i915 device info: cursor_needs_physical: no [ 1.424970] i915 device info: has_csr: yes [ 1.424970] i915 device info: has_ddi: yes [ 1.424971] i915 device info: has_dp_mst: yes [ 1.424972] i915 device info: has_dsb: no [ 1.424973] i915 device info: has_dsc: no [ 1.424974] i915 device info: has_fbc: no [ 1.424974] i915 device info: has_gmch: no [ 1.424975] i915 device info: has_hdcp: yes [ 1.424976] i915 device info: has_hotplug: yes [ 1.424977] i915 device info: has_ipc: yes [ 1.424978] i915 device info: has_modular_fia: no [ 1.424979] i915 device info: has_overlay: no [ 1.424980] i915 device info: has_psr: yes [ 1.424981] i915 device info: overlay_needs_physical: no [ 1.424981] i915 device info: supports_tv: no [ 1.424982] i915 device info: slice total: 1, mask=0001 [ 1.424983] i915 device info: subslice total: 3 [ 1.424985] i915 device info: slice0: 3 subslices, mask=00000007 [ 1.424986] i915 device info: slice1: 0 subslices, mask=00000000 [ 1.424987] i915 device info: slice2: 0 subslices, mask=00000000 [ 1.424987] i915 device info: EU total: 24 [ 1.424988] i915 device info: EU per subslice: 8 [ 1.424989] i915 device info: has slice power gating: no [ 1.424990] i915 device info: has subslice power gating: no [ 1.424991] i915 device info: has EU power gating: yes [ 1.424992] i915 device info: CS timestamp frequency: 12000 kHz [ 1.425215] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.425265] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.425502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 1.425525] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 1.425552] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 1.425579] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 1.428627] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 1.428673] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 1.428929] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.428956] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 1.429243] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 1.429262] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 1.429267] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] status updated from unknown to disconnected [ 1.429271] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 1.429275] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 1.429304] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 1.429716] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 1.430070] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 1.431595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 1.431624] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 1.431652] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 1.431941] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 1.437548] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 1.438071] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] status updated from unknown to connected [ 1.438083] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.438095] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 1.438105] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 1.438114] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.438303] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.438311] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.438318] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.438325] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.438333] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438339] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438346] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438353] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438360] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438366] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438373] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.438379] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.438387] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 1.438394] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.438401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 1.438408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 1.438414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 1.438421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 1.438428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.438434] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.438441] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.438448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.438454] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 1.438461] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 1.438468] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.438475] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.438481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 1.438488] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 1.438495] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.438501] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.438508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.438515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.438521] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.438528] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.438535] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 1.438541] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.438548] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.438555] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.438562] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.438568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.438575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.438582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438588] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438595] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438602] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.438608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.438615] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 1.438621] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.438628] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.438635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.438639] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 1.438670] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 1.438979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.439008] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.439309] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 1.439332] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 1.439360] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 1.439388] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 1.442034] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 1.442060] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 1.442363] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.442389] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 1.442674] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 1.442693] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 1.442697] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] status updated from unknown to disconnected [ 1.442701] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 1.442704] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 1.442731] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 1.443143] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 1.443498] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 1.445026] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 1.445055] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 1.445083] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 1.445371] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 1.450984] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 1.451505] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] status updated from unknown to connected [ 1.451514] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.451523] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 1.451530] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 1.451537] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 1.451717] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.451724] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.451732] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 1.451738] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 1.451746] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451752] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451760] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451772] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451779] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451785] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451792] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 1.451798] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 1.451806] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 1.451813] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.451832] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 1.451839] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 1.451845] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 1.451851] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 1.451858] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.451864] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 1.451870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.451877] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 1.451883] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 1.451890] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 1.451896] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.451902] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 1.451909] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 1.451915] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 1.451921] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.451928] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 1.451934] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 1.451940] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.451947] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.451953] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 1.451959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 1.451966] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 1.451972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 1.451978] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 1.451985] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 1.451991] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.451997] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 1.452004] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452010] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452016] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452023] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 1.452029] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 1.452035] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 1.452042] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.452048] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 1.452054] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 1.452058] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 1.452153] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 1.452459] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 1.452487] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 1.452774] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 1.452796] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 1.452823] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 1.452849] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 1.455460] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 1.455486] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 1.455821] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 1.455849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 1.456135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 1.456153] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 1.456158] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] status updated from unknown to disconnected [ 1.456161] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 1.456165] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 1.456192] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 1.456202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] status updated from unknown to disconnected [ 1.456205] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 1.456214] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no [ 1.456223] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no [ 1.456230] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes [ 1.456237] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no [ 1.456244] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes [ 1.456250] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no [ 1.456257] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no [ 1.456264] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 1.456271] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 [ 1.456278] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 [ 1.456285] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 1.456291] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 [ 1.456297] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 [ 1.456304] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 1.456310] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 16384x16384 config [ 1.456319] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) [ 1.456325] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) [ 1.456331] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane [ 1.456335] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 1 primary plane [ 1.456339] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 2 primary plane [ 1.456368] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one [ 1.461444] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000 [ 1.461492] fbcon: i915drmfb (fb1) is primary device [ 1.461493] fbcon: Remapping primary device, fb1, to tty 1-63 [ 1.461508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 1.461518] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002dfe43fd state to 00000000fc0cb429 [ 1.461526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000000bf01569 state to 00000000fc0cb429 [ 1.461535] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000000bf01569 [ 1.461543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ab6fdf3f state to 00000000fc0cb429 [ 1.461550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ab6fdf3f [ 1.461558] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d93e8df3 state to 00000000fc0cb429 [ 1.461566] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000015cf0577 state to 00000000fc0cb429 [ 1.461573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000015cf0577 [ 1.461580] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003292b89f state to 00000000fc0cb429 [ 1.461588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003292b89f [ 1.461595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f4491376 state to 00000000fc0cb429 [ 1.461602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e2798a03 state to 00000000fc0cb429 [ 1.461609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e2798a03 [ 1.461616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007f2e9b45 state to 00000000fc0cb429 [ 1.461624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007f2e9b45 [ 1.461632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 [ 1.461640] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000de3ff82c [ 1.461648] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane 1A] state 000000002dfe43fd to [CRTC:51:pipe A] [ 1.461655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002dfe43fd [ 1.461662] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 1.461670] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034523972 state to 00000000fc0cb429 [ 1.461678] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [NOCRTC] [ 1.461685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [CRTC:51:pipe A] [ 1.461693] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 00000000fc0cb429 [ 1.461700] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 00000000dd2a82ac [ 1.461707] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:52:plane 1B] state 00000000d93e8df3 to [CRTC:72:pipe B] [ 1.461714] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d93e8df3 [ 1.461721] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 1.461730] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000de1711cf state to 00000000fc0cb429 [ 1.461736] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000de1711cf to [CRTC:72:pipe B] [ 1.461744] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e46349dc state to 00000000fc0cb429 [ 1.461751] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e46349dc [ 1.461758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f4491376 [ 1.461765] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 1.461772] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 1.461779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] mode changed [ 1.461783] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] mode changed [ 1.461786] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] enable changed [ 1.461790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] active changed [ 1.461795] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.461798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.461802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.461805] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] using [ENCODER:119:DDI D] on [CRTC:72:pipe B] [ 1.461808] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] needs all connectors, enable: y, active: y [ 1.461816] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 1.461823] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000fc0cb429 [ 1.461827] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] needs all connectors, enable: y, active: y [ 1.461834] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 1.461841] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:72:pipe B] to 00000000fc0cb429 [ 1.461874] [drm:intel_atomic_check [i915]] [CONNECTOR:110:DP-2] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 [ 1.461911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz [ 1.461941] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 [ 1.461968] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 [ 1.461996] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 [ 1.462030] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 [ 1.462061] [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in has_audio unable to verify whether state matches exactly, forcing modeset (expected no, found yes) [ 1.462091] [drm:intel_atomic_check [i915]] [CONNECTOR:120:DP-3] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 [ 1.462124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz [ 1.462151] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 [ 1.462178] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 [ 1.462204] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 [ 1.462236] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 [ 1.462265] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in lane_count (expected 0, found 4) [ 1.462294] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in dp_m_n (expected tu 0 gmch 0/0 link 0/0, or tu 0 gmch 0/0 link 0/0, found tu 64, gmch 6212812/8388608 link 1035468/1048576) [ 1.462321] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_types (expected 0x00000000, found 0x00000080) [ 1.462349] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 3840) [ 1.462376] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 4000) [ 1.462402] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 3840) [ 1.462429] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 4000) [ 1.462455] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 3902) [ 1.462481] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 3950) [ 1.462507] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 2160) [ 1.462533] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 2222) [ 1.462559] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 2160) [ 1.462584] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 2222) [ 1.462610] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 2163) [ 1.462636] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 2168) [ 1.462662] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pixel_multiplier (expected 0, found 1) [ 1.462688] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_format (expected 0, found 1) [ 1.462714] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in has_audio (expected no, found yes) [ 1.462740] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (1) (expected 0, found 1) [ 1.462766] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8) [ 1.462792] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pipe_bpp (expected 0, found 24) [ 1.462818] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 533250) [ 1.462843] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in port_clock (expected 0, found 540000) [ 1.462875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 [ 1.462904] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 0 -> 1, off 0, on 1, ms 1 [ 1.462933] [drm:intel_modeset_calc_cdclk [i915]] Modeset required for cdclk change [ 1.462960] [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz [ 1.462986] [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 2, actual 2 [ 1.463015] [drm:intel_find_shared_dpll [i915]] [CRTC:51:pipe A] allocated DPLL 1 [ 1.463043] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe A [ 1.463071] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 [ 1.463099] [drm:intel_find_shared_dpll [i915]] [CRTC:72:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 1) [ 1.463126] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe B [ 1.463157] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 0) -> ( 0 - 401), size 0 -> 401 [ 1.463181] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 847 - 892) -> ( 401 - 446), size 45 -> 45 [ 1.463204] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm [ 1.463227] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 [ 1.463249] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 [ 1.463271] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 [ 1.463292] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] ddb ( 0 - 0) -> ( 446 - 847), size 0 -> 401 [ 1.463312] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 [ 1.463332] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm [ 1.463353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 [ 1.463373] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 [ 1.463392] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 [ 1.463423] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [modeset] [ 1.463453] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB [ 1.463482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 [ 1.463510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 [ 1.463537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 [ 1.463564] [drm:intel_dump_pipe_config [i915]] requested mode: [ 1.463573] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.463600] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 1.463608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.463636] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 1.463662] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 1.463689] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 1.463715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no [ 1.463741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 1.463768] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 1.463831] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 [ 1.463857] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> [ 1.463883] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes [ 1.463909] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 [ 1.463935] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 [ 1.463961] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no [ 1.463987] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor A] fb: [NOFB], visible: no [ 1.464013] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [modeset] [ 1.464039] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB [ 1.464064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 [ 1.464090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 [ 1.464115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 [ 1.464140] [drm:intel_dump_pipe_config [i915]] requested mode: [ 1.464148] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.464174] [drm:intel_dump_pipe_config [i915]] adjusted mode: [ 1.464182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 1.464209] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 [ 1.464234] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 [ 1.464260] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 [ 1.464286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no [ 1.464311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [ 1.464336] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 [ 1.464362] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 [ 1.464387] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> [ 1.464414] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes [ 1.464439] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 [ 1.464465] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 [ 1.464491] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 2B] fb: [NOFB], visible: no [ 1.464516] [drm:intel_dump_pipe_config [i915]] [PLANE:68:cursor B] fb: [NOFB], visible: no [ 1.464526] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 1.464573] [drm:intel_disable_pipe [i915]] disabling pipe A [ 1.467843] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well [ 1.467878] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 51 [ 1.467923] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 [ 1.467957] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 2 [ 1.467991] i915 0000:00:02.0: [drm:intel_disable_sagv [i915]] Disabling SAGV [ 1.468025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI B] [ 1.468055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:96:DP-MST A] [ 1.468085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:97:DP-MST B] [ 1.468114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:98:DP-MST C] [ 1.468143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:109:DDI C] [ 1.468172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:111:DP-MST A] [ 1.468200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:112:DP-MST B] [ 1.468228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:113:DP-MST C] [ 1.468256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:119:DDI D] [ 1.468284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:121:DP-MST A] [ 1.468312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:122:DP-MST B] [ 1.468340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:123:DP-MST C] [ 1.468367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:129:DDI E] [ 1.468396] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 0 [ 1.468424] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 [ 1.468452] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 2 [ 1.468481] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 3 [ 1.468512] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 51 [ 1.468542] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 [ 1.468641] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well [ 1.469400] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 [ 1.469709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 1.469737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 1.469765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 1.469793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 1.470489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 [ 1.470517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 [ 1.470544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.471230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 [ 1.471257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 [ 1.471284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.471974] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 1.472002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 1.473297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 1.473473] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:110:DP-2] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 1.473640] [drm:intel_enable_pipe [i915]] enabling pipe A [ 1.473675] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 1.473705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:110:DP-2], [ENCODER:109:DDI C] [ 1.473735] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder A, 36 bytes ELD [ 1.473767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 1.473810] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 72 [ 1.473841] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well [ 1.474602] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 [ 1.474908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 [ 1.474936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 [ 1.474964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 [ 1.474992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 [ 1.475686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 [ 1.475714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 [ 1.475740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.476426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 [ 1.476454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 [ 1.476481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 [ 1.477166] [drm:intel_dp_start_link_train [i915]] clock recovery OK [ 1.477193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 [ 1.478488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful [ 1.478664] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:120:DP-3] Link Training Passed at Link Rate = 540000, Lane count = 4 [ 1.478830] [drm:intel_enable_pipe [i915]] enabling pipe B [ 1.478862] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS [ 1.478897] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun [ 1.478928] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:120:DP-3], [ENCODER:119:DDI D] [ 1.478957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder B, 36 bytes ELD [ 1.478988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud [ 1.495987] [drm:verify_connector_state [i915]] [CONNECTOR:110:DP-2] [ 1.496025] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A] [ 1.496067] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 [ 1.496104] [drm:verify_connector_state [i915]] [CONNECTOR:120:DP-3] [ 1.496135] [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B] [ 1.496171] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 [ 1.496241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 [ 1.496252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a8e00a70 state to 000000002a70fa07 [ 1.496261] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 000000002a70fa07 [ 1.496285] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c4a0e3a state to 000000002a70fa07 [ 1.496310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c4a0e3a [ 1.496324] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 1.496335] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 1.496350] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 000000002a70fa07 [ 1.496359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f [ 1.496366] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000062109416 state to 000000002a70fa07 [ 1.496374] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 000000002a70fa07 [ 1.496381] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f97067cf state to 000000002a70fa07 [ 1.496389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f97067cf [ 1.496397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a6369fc8 state to 000000002a70fa07 [ 1.496404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a6369fc8 [ 1.496412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000091b367b1 state to 000000002a70fa07 [ 1.496421] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000009bdf158a state to 000000002a70fa07 [ 1.496428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000009bdf158a [ 1.496435] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fb662b09 state to 000000002a70fa07 [ 1.496443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fb662b09 [ 1.496455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a8e00a70 [ 1.496463] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 [ 1.496471] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 000000002a70fa07 [ 1.496479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] [ 1.496486] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] [ 1.496494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000062109416 [ 1.496501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 [ 1.496509] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000860da491 state to 000000002a70fa07 [ 1.496516] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [NOCRTC] [ 1.496523] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [CRTC:72:pipe B] [ 1.496531] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 000000002a70fa07 [ 1.496538] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 1.496545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000091b367b1 [ 1.496552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 [ 1.496560] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 [ 1.496570] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.496574] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.496578] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.496581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.496625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.496658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.496675] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 [ 1.512640] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 [ 1.512654] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 [ 1.524341] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 1.524352] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 [ 1.524362] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 1.524370] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 [ 1.524382] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f [ 1.524394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 [ 1.524403] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 [ 1.524412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 1.524420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 1.524428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 [ 1.524437] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 1.524446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 [ 1.524454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 1.524463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 [ 1.524471] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 [ 1.524479] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 [ 1.524489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 [ 1.524497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a [ 1.524506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c [ 1.524515] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 1.524524] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003979f4ee state to 0000000098df4bf3 [ 1.524533] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [NOCRTC] [ 1.524542] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [CRTC:51:pipe A] [ 1.524551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 1.524559] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 1.524568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 [ 1.524576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] [ 1.524585] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] [ 1.524593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 1.524602] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 1.524610] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f [ 1.524619] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 1.524628] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 1.524638] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.524643] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.524648] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.524652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.524716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.524754] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.524771] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 1.553743] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 1.553761] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 [ 1.553774] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 1.553786] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015579631 state to 00000000482d1aa4 [ 1.553798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 00000000482d1aa4 [ 1.553808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000482d1aa4 [ 1.553819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b [ 1.553830] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000482d1aa4 [ 1.553840] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 [ 1.553850] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000041c6228e state to 00000000482d1aa4 [ 1.553860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000022f73fd2 state to 00000000482d1aa4 [ 1.553869] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001f82d691 state to 00000000482d1aa4 [ 1.553879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001f82d691 [ 1.553889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 [ 1.553899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 [ 1.553909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e5892e4f state to 00000000482d1aa4 [ 1.553921] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c3b3ca94 state to 00000000482d1aa4 [ 1.553931] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c3b3ca94 [ 1.553940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000074f436be state to 00000000482d1aa4 [ 1.553950] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000074f436be [ 1.553960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015579631 [ 1.553970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 [ 1.553981] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000482d1aa4 [ 1.553991] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] [ 1.554000] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] [ 1.554010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000041c6228e [ 1.554020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 [ 1.554030] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000482d1aa4 [ 1.554039] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 1.554048] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 1.554058] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000006ede65dd state to 00000000482d1aa4 [ 1.554067] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000006ede65dd [ 1.554076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e5892e4f [ 1.554086] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 [ 1.554096] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 [ 1.554108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.554113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.554118] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.554123] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.554190] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.554233] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.554259] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 [ 1.562628] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 [ 1.562645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 [ 1.575634] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c [ 1.575648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 00000000fcb1012c [ 1.575660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000fcb1012c [ 1.575670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ccf8507 state to 00000000fcb1012c [ 1.575681] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ccf8507 [ 1.575691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bb3d8d45 state to 00000000fcb1012c [ 1.575702] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bb3d8d45 [ 1.575716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000485c2b88 state to 00000000fcb1012c [ 1.575725] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002ba4f36a state to 00000000fcb1012c [ 1.575735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004e08d13d state to 00000000fcb1012c [ 1.575745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004e08d13d [ 1.575754] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b2b055b6 state to 00000000fcb1012c [ 1.575767] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b2b055b6 [ 1.575798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000010a446a8 state to 00000000fcb1012c [ 1.575807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c [ 1.575817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf [ 1.575854] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d365bfc5 state to 00000000fcb1012c [ 1.575863] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d365bfc5 [ 1.575874] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a [ 1.575884] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c [ 1.575894] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001d9bfafc state to 00000000fcb1012c [ 1.575904] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [NOCRTC] [ 1.575914] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [CRTC:51:pipe A] [ 1.575924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000485c2b88 [ 1.575933] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c [ 1.575943] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000514f7582 state to 00000000fcb1012c [ 1.575952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [NOCRTC] [ 1.575961] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [CRTC:72:pipe B] [ 1.575971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c [ 1.575980] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 [ 1.575989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000010a446a8 [ 1.575999] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c [ 1.576008] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c [ 1.576020] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.576025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.576030] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.576035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.576097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.576139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.576167] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c [ 1.610983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bb4d667a [ 1.611007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c [ 1.611032] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e9b5f5ed state to 00000000bb4d667a [ 1.611054] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c [ 1.611079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000bb4d667a [ 1.611096] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000122a804f state to 00000000bb4d667a [ 1.611115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000122a804f [ 1.611131] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005d690c84 state to 00000000bb4d667a [ 1.611149] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005d690c84 [ 1.611165] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c775be6 state to 00000000bb4d667a [ 1.611183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000bb4d667a [ 1.611198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000b5f6abf5 state to 00000000bb4d667a [ 1.611214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000b5f6abf5 [ 1.611230] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000281af025 state to 00000000bb4d667a [ 1.611246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000281af025 [ 1.611261] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053454233 state to 00000000bb4d667a [ 1.611276] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b2cdb294 state to 00000000bb4d667a [ 1.611292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b2cdb294 [ 1.611308] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000555d146c state to 00000000bb4d667a [ 1.611323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000555d146c [ 1.611341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e9b5f5ed [ 1.611358] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000bb4d667a [ 1.611375] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000084c59d5f state to 00000000bb4d667a [ 1.611396] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [NOCRTC] [ 1.611412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [CRTC:51:pipe A] [ 1.611428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c775be6 [ 1.611444] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000bb4d667a [ 1.611460] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000adc2b291 state to 00000000bb4d667a [ 1.611476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [NOCRTC] [ 1.611491] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [CRTC:72:pipe B] [ 1.611508] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000bb4d667a [ 1.611524] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d [ 1.611539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053454233 [ 1.611560] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000bb4d667a [ 1.611577] [drm:drm_atomic_check_only [drm]] checking 00000000bb4d667a [ 1.611603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.611612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.611620] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.611628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.611728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.611798] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.611840] [drm:drm_atomic_commit [drm]] committing 00000000bb4d667a [ 1.645601] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bb4d667a [ 1.645625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 [ 1.645642] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bb4d667a [ 1.645659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000060d5862a state to 00000000482d1aa4 [ 1.645675] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000482d1aa4 [ 1.645689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000071f245df state to 00000000482d1aa4 [ 1.645705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000071f245df [ 1.645722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000482d1aa4 [ 1.645736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be [ 1.645752] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 00000000482d1aa4 [ 1.645767] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000669bfcd7 state to 00000000482d1aa4 [ 1.645779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5892e4f state to 00000000482d1aa4 [ 1.645794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5892e4f [ 1.645807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 [ 1.645820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 [ 1.645834] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001f82d691 state to 00000000482d1aa4 [ 1.645846] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 00000000482d1aa4 [ 1.645860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e [ 1.645874] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 00000000482d1aa4 [ 1.645888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 [ 1.645902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000060d5862a [ 1.645916] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 [ 1.645930] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 00000000482d1aa4 [ 1.645945] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 1.645958] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 1.645971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 [ 1.645984] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 [ 1.645998] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 00000000482d1aa4 [ 1.646011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 1.646024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 1.646037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d7f71e60 state to 00000000482d1aa4 [ 1.646050] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d7f71e60 [ 1.646063] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001f82d691 [ 1.646076] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 [ 1.646090] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 [ 1.646105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.646113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.646120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.646126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.646207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.646267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.646298] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 [ 1.662741] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 [ 1.662763] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 [ 1.682625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 1.682648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f101de7e state to 0000000098df4bf3 [ 1.682667] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 1.682683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e81eafbe state to 0000000098df4bf3 [ 1.682701] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e81eafbe [ 1.682718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000026a13e4f state to 0000000098df4bf3 [ 1.682735] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000026a13e4f [ 1.682755] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 [ 1.682770] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 1.682784] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005342f7e7 state to 0000000098df4bf3 [ 1.682801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005342f7e7 [ 1.682816] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fb96f9d3 state to 0000000098df4bf3 [ 1.682832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fb96f9d3 [ 1.682848] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000003eec9b7 state to 0000000098df4bf3 [ 1.682863] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 [ 1.682879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a [ 1.682894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 [ 1.682909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 [ 1.682926] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f101de7e [ 1.682942] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 1.682962] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000064c4b21e state to 0000000098df4bf3 [ 1.682979] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [NOCRTC] [ 1.682994] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [CRTC:51:pipe A] [ 1.683010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe [ 1.683025] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 1.683041] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 [ 1.683056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] [ 1.683072] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] [ 1.683088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 1.683103] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 1.683118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000003eec9b7 [ 1.683133] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 1.683149] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 1.683178] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.683187] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.683196] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.683203] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.683302] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.683372] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.683406] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 1.683650] ata1: SATA link down (SStatus 4 SControl 300) [ 1.683668] ata4: SATA link down (SStatus 4 SControl 300) [ 1.683686] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 1.683711] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) [ 1.685953] ata2.00: supports DRM functions and may not be fully accessible [ 1.686212] ata3.00: ATAPI: TSSTcorp CDDVDW SH-224GB, SB00, max UDMA/100 [ 1.687451] ata3.00: configured for UDMA/100 [ 1.692177] ata2.00: disabling queued TRIM support [ 1.692194] ata2.00: ATA-9: Samsung SSD 850 PRO 512GB, EXM02B6Q, max UDMA/133 [ 1.692196] ata2.00: 1000215216 sectors, multi 1: LBA48 NCQ (depth 32), AA [ 1.696183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 1.696209] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 1.698509] ata2.00: supports DRM functions and may not be fully accessible [ 1.699829] usb 1-7: new high-speed USB device number 2 using xhci_hcd [ 1.704324] ata2.00: disabling queued TRIM support [ 1.710263] ata2.00: configured for UDMA/133 [ 1.710469] scsi 1:0:0:0: Direct-Access ATA Samsung SSD 850 2B6Q PQ: 0 ANSI: 5 [ 1.713317] scsi 2:0:0:0: CD-ROM TSSTcorp CDDVDW SH-224GB SB00 PQ: 0 ANSI: 5 [ 1.725160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c [ 1.725192] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000c8bd6dc state to 00000000fcb1012c [ 1.725221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 00000000fcb1012c [ 1.725245] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000083c05b3d state to 00000000fcb1012c [ 1.725273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000083c05b3d [ 1.725297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008409a024 state to 00000000fcb1012c [ 1.725322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008409a024 [ 1.725347] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006164f3e3 state to 00000000fcb1012c [ 1.725370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 00000000fcb1012c [ 1.725394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000382acb58 state to 00000000fcb1012c [ 1.725418] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000382acb58 [ 1.725442] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a9a5a77 state to 00000000fcb1012c [ 1.725466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009a9a5a77 [ 1.725489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d365bfc5 state to 00000000fcb1012c [ 1.725510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c [ 1.725534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf [ 1.725557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010a446a8 state to 00000000fcb1012c [ 1.725580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010a446a8 [ 1.725608] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000c8bd6dc [ 1.725633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c [ 1.725662] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000008c0081a2 state to 00000000fcb1012c [ 1.725687] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [NOCRTC] [ 1.725712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [CRTC:51:pipe A] [ 1.725736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006164f3e3 [ 1.725759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c [ 1.725783] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 00000000fcb1012c [ 1.725806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] [ 1.725828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] [ 1.725853] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c [ 1.725876] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 [ 1.725898] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d365bfc5 [ 1.725921] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c [ 1.725945] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c [ 1.725977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.725990] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.726002] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.726013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.726148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.726252] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.726302] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c [ 1.740953] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c [ 1.740990] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c [ 1.776024] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000895e0f29 [ 1.776052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000bf89eae0 state to 00000000895e0f29 [ 1.776075] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002aa6a9f8 state to 00000000895e0f29 [ 1.776097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f454a2f1 state to 00000000895e0f29 [ 1.776121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f454a2f1 [ 1.776142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000895e0f29 [ 1.776163] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 [ 1.776185] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001e3a4a97 state to 00000000895e0f29 [ 1.776208] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 00000000895e0f29 [ 1.776228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000f80a3c5 state to 00000000895e0f29 [ 1.776249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000f80a3c5 [ 1.776269] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000002f5f5ecb state to 00000000895e0f29 [ 1.776289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000002f5f5ecb [ 1.776311] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000082c8a15 state to 00000000895e0f29 [ 1.776330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000017301ddd state to 00000000895e0f29 [ 1.776350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000017301ddd [ 1.776369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000bd98ba2f state to 00000000895e0f29 [ 1.776389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000bd98ba2f [ 1.776415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000bf89eae0 [ 1.776436] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000895e0f29 [ 1.776458] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002f3cb69d state to 00000000895e0f29 [ 1.776479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [NOCRTC] [ 1.776499] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [CRTC:51:pipe A] [ 1.776522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001e3a4a97 [ 1.776542] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000895e0f29 [ 1.776562] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001bc59558 state to 00000000895e0f29 [ 1.776582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [NOCRTC] [ 1.776601] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [CRTC:72:pipe B] [ 1.776621] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e59c9ea1 state to 00000000895e0f29 [ 1.776641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e59c9ea1 [ 1.776659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000082c8a15 [ 1.776679] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000895e0f29 [ 1.776700] [drm:drm_atomic_check_only [drm]] checking 00000000895e0f29 [ 1.776735] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.776746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.776757] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.776766] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.776890] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.776981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.777022] [drm:drm_atomic_commit [drm]] committing 00000000895e0f29 [ 1.804096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 [ 1.804107] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000895e0f29 [ 1.804118] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001e6f8dac state to 00000000548834f9 [ 1.804128] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000895e0f29 [ 1.804139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005b7d8c1d state to 00000000548834f9 [ 1.804146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b0a2562b state to 00000000548834f9 [ 1.804155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b0a2562b [ 1.804162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000210ee201 state to 00000000548834f9 [ 1.804172] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000210ee201 [ 1.804179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074e96990 state to 00000000548834f9 [ 1.804190] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000085f180bd state to 00000000548834f9 [ 1.804196] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018d44f01 state to 00000000548834f9 [ 1.804204] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018d44f01 [ 1.804211] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c0bd820d state to 00000000548834f9 [ 1.804218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c0bd820d [ 1.804225] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c73eec69 state to 00000000548834f9 [ 1.804232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000080dfd757 state to 00000000548834f9 [ 1.804239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000080dfd757 [ 1.804246] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f141c893 state to 00000000548834f9 [ 1.804253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f141c893 [ 1.804261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001e6f8dac [ 1.804268] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 [ 1.804281] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000f3f263f3 state to 00000000548834f9 [ 1.804291] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [NOCRTC] [ 1.804298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [CRTC:51:pipe A] [ 1.804306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000074e96990 [ 1.804313] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 [ 1.804320] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000af6800c9 state to 00000000548834f9 [ 1.804327] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [NOCRTC] [ 1.804334] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [CRTC:72:pipe B] [ 1.804341] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 [ 1.804348] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 [ 1.804355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c73eec69 [ 1.804362] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 [ 1.804369] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 [ 1.804388] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.804392] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.804398] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.804401] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.804446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.804478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.804499] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 [ 1.823766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 [ 1.823787] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 [ 1.823804] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 1.823818] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 000000006432a660 [ 1.823827] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 [ 1.823835] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c471465 state to 000000006432a660 [ 1.823845] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c471465 [ 1.823853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5b7e29b state to 000000006432a660 [ 1.823862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5b7e29b [ 1.823870] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 [ 1.823878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 [ 1.823885] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e7bdd2e4 state to 000000006432a660 [ 1.823893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e7bdd2e4 [ 1.823901] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 [ 1.823909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 [ 1.823917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000087dc1fd8 state to 000000006432a660 [ 1.823925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 000000006432a660 [ 1.823933] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d [ 1.823941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000df34b7b3 state to 000000006432a660 [ 1.823949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000df34b7b3 [ 1.823957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a [ 1.823965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 1.823974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 [ 1.823982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] [ 1.823990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] [ 1.824001] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa [ 1.824009] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 1.824017] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 [ 1.824025] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] [ 1.824032] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] [ 1.824041] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 1.824048] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 1.824056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000087dc1fd8 [ 1.824063] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 1.824071] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 1.824082] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.824099] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.824106] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.824110] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.824157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.824191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.824208] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 1.841121] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 1.841136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 1.854405] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 1.854418] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057ed1a51 state to 00000000c6c933d1 [ 1.854430] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 [ 1.854441] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008ffba3f3 state to 00000000c6c933d1 [ 1.854453] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008ffba3f3 [ 1.854464] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 [ 1.854476] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 [ 1.854489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 [ 1.854499] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 1.854509] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 [ 1.854520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 [ 1.854530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 1.854541] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 1.854552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 [ 1.854561] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 [ 1.854572] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab [ 1.854584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 [ 1.854594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 [ 1.854606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000057ed1a51 [ 1.854617] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 1.854628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 [ 1.854640] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] [ 1.854650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] [ 1.854661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 [ 1.854671] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 1.854682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 [ 1.854692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] [ 1.854703] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] [ 1.854714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 [ 1.854724] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 [ 1.854734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 [ 1.854744] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 1.854755] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 1.854767] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.854773] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.854779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.854784] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.854860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.854907] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.854927] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 1.879165] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 1.879183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 1.879202] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 [ 1.879217] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 1.879236] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 [ 1.879248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 [ 1.879265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 [ 1.879281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 [ 1.879294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 [ 1.879306] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 [ 1.879317] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 [ 1.879328] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 [ 1.879346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 [ 1.879357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 [ 1.879369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd [ 1.879382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 [ 1.879393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 [ 1.879405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 [ 1.879416] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 1.879428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 1.879440] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 [ 1.879453] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 1.879465] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 [ 1.879478] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] [ 1.879490] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] [ 1.879502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 [ 1.879514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 1.879526] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 1.879538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 1.879549] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 1.879561] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 1.879573] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 1.879584] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 [ 1.879596] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 1.879608] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 1.879622] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.879629] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.879635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.879641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.879713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.879765] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.879801] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 1.896360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 1.896381] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 1.912612] tsc: Refined TSC clocksource calibration: 3503.999 MHz [ 1.912618] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x3282124c47b, max_idle_ns: 440795239402 ns [ 1.912658] clocksource: Switched to clocksource tsc [ 1.912681] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 1.912697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 [ 1.912714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 1.912729] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 [ 1.912743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe [ 1.912756] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 [ 1.912769] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 [ 1.912781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 1.912793] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 1.912804] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 [ 1.912817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 [ 1.912829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 [ 1.912841] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f [ 1.912853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 [ 1.912866] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 [ 1.912878] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 [ 1.912889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 [ 1.912901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e [ 1.912914] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f [ 1.912926] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 1.912939] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000095845c0a state to 0000000098df4bf3 [ 1.912952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [NOCRTC] [ 1.912964] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [CRTC:51:pipe A] [ 1.912976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 1.912987] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 1.912999] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 [ 1.913011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] [ 1.913023] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] [ 1.913035] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 1.913047] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 1.913058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c [ 1.913070] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 1.913082] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 1.913095] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.913102] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.913108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.913114] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.913187] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.913239] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.913263] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 1.929772] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 1.929793] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 1.949476] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 [ 1.949495] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006a25a70b state to 000000002a70fa07 [ 1.949513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e46349dc state to 000000002a70fa07 [ 1.949530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f2e9b45 state to 000000002a70fa07 [ 1.949549] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f2e9b45 [ 1.949565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e2798a03 state to 000000002a70fa07 [ 1.949583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e2798a03 [ 1.949599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f4491376 state to 000000002a70fa07 [ 1.949615] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 000000002a70fa07 [ 1.949630] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003292b89f state to 000000002a70fa07 [ 1.949647] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003292b89f [ 1.949662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000015cf0577 state to 000000002a70fa07 [ 1.949679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000015cf0577 [ 1.949694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 000000002a70fa07 [ 1.949709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ab6fdf3f state to 000000002a70fa07 [ 1.949725] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ab6fdf3f [ 1.949744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bf01569 state to 000000002a70fa07 [ 1.949760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bf01569 [ 1.949777] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006a25a70b [ 1.949793] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 [ 1.949811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003a5f3d7f state to 000000002a70fa07 [ 1.949828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [NOCRTC] [ 1.949844] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [CRTC:51:pipe A] [ 1.949862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f4491376 [ 1.949879] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 [ 1.949895] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000bd54c871 state to 000000002a70fa07 [ 1.949911] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [NOCRTC] [ 1.949926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [CRTC:72:pipe B] [ 1.949943] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000de3ff82c state to 000000002a70fa07 [ 1.949959] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000de3ff82c [ 1.949974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 [ 1.949990] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 [ 1.950007] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 [ 1.950024] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.950034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.950042] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.950050] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.950146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.950217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.950249] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 [ 1.963116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 [ 1.963143] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 [ 1.975843] usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd [ 1.982659] usb 1-7: New USB device found, idVendor=1307, idProduct=0330, bcdDevice= 1.00 [ 1.982661] usb 1-7: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 1.982663] usb 1-7: Product: Mass Storage Device [ 1.982664] usb 1-7: Manufacturer: Generic [ 1.982665] usb 1-7: SerialNumber: 00000000000006 [ 1.984947] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 1.984976] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000087dc1fd8 state to 000000006432a660 [ 1.985005] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 [ 1.985028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ada87627 state to 000000006432a660 [ 1.985054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ada87627 [ 1.985077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e7bdd2e4 state to 000000006432a660 [ 1.985102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e7bdd2e4 [ 1.985125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 [ 1.985148] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 [ 1.985170] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5b7e29b state to 000000006432a660 [ 1.985194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5b7e29b [ 1.985218] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001c471465 state to 000000006432a660 [ 1.985242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001c471465 [ 1.985264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 [ 1.985286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000bf357c4b state to 000000006432a660 [ 1.985309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000bf357c4b [ 1.985332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 000000006432a660 [ 1.985355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 [ 1.985380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000087dc1fd8 [ 1.985403] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 1.985435] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 [ 1.985459] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] [ 1.985483] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] [ 1.985507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa [ 1.985530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 1.985553] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 [ 1.985576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 1.985600] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 1.985623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 1.985646] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 1.985668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a [ 1.985691] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 1.985714] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 1.985747] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 1.985759] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 1.985771] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 1.985782] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 1.985898] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 1.985980] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 1.986020] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 1.988961] usb-storage 1-7:1.0: USB Mass Storage device detected [ 1.989364] scsi host4: usb-storage 1-7:1.0 [ 1.989455] usbcore: registered new interface driver usb-storage [ 1.991210] usbcore: registered new interface driver uas [ 1.996109] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 1.996129] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 1.999995] usb 2-1: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 [ 1.999996] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.000778] hub 2-1:1.0: USB hub found [ 2.000960] hub 2-1:1.0: 4 ports detected [ 2.013903] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.013919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 [ 2.013933] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 [ 2.013946] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 [ 2.013961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 [ 2.013975] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000183fcb7 state to 00000000c6c933d1 [ 2.013989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000183fcb7 [ 2.014002] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000aff706ab state to 00000000c6c933d1 [ 2.014015] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 2.014028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.014042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fc1d1694 [ 2.014055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 2.014068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 2.014080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003e7fb927 state to 00000000c6c933d1 [ 2.014092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001964fcb3 state to 00000000c6c933d1 [ 2.014105] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001964fcb3 [ 2.014117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000dd33f136 state to 00000000c6c933d1 [ 2.014129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000dd33f136 [ 2.014143] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 [ 2.014156] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.014169] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 [ 2.014182] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] [ 2.014195] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] [ 2.014208] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000aff706ab [ 2.014221] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.014234] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 [ 2.014247] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] [ 2.014260] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] [ 2.014273] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 [ 2.014286] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 [ 2.014299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003e7fb927 [ 2.014312] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.014325] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.014340] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.014348] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.014354] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.014361] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.014425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.014482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.014507] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.029646] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.029666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.047486] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000246f13a6 [ 2.047504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f80a3c5 state to 00000000246f13a6 [ 2.047520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ad566469 state to 00000000246f13a6 [ 2.047534] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001e3a4a97 state to 00000000246f13a6 [ 2.047550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001e3a4a97 [ 2.047567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000246f13a6 [ 2.047581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 [ 2.047595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f454a2f1 state to 00000000246f13a6 [ 2.047608] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 00000000246f13a6 [ 2.047620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bf89eae0 state to 00000000246f13a6 [ 2.047634] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bf89eae0 [ 2.047648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000082c8a15 state to 00000000246f13a6 [ 2.047661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000082c8a15 [ 2.047674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000017301ddd state to 00000000246f13a6 [ 2.047690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9473c9b state to 00000000246f13a6 [ 2.047704] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9473c9b [ 2.047717] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fdc091c8 state to 00000000246f13a6 [ 2.047730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fdc091c8 [ 2.047744] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000f80a3c5 [ 2.047758] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000246f13a6 [ 2.047779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000079f595ad state to 00000000246f13a6 [ 2.047793] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [NOCRTC] [ 2.047806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [CRTC:51:pipe A] [ 2.047819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f454a2f1 [ 2.047833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000246f13a6 [ 2.047846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005876474e state to 00000000246f13a6 [ 2.047860] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [NOCRTC] [ 2.047872] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [CRTC:72:pipe B] [ 2.047886] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000009be30044 state to 00000000246f13a6 [ 2.047899] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000009be30044 [ 2.047912] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000017301ddd [ 2.047925] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000246f13a6 [ 2.047938] [drm:drm_atomic_check_only [drm]] checking 00000000246f13a6 [ 2.047954] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.047962] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.047968] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.047975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.048064] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.048124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.048152] [drm:drm_atomic_commit [drm]] committing 00000000246f13a6 [ 2.063067] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000246f13a6 [ 2.063089] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000246f13a6 [ 2.084698] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 [ 2.084727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f1595a5f state to 00000000548834f9 [ 2.084747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ca8a0e1e state to 00000000548834f9 [ 2.084765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f97cb978 state to 00000000548834f9 [ 2.084787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f97cb978 [ 2.084806] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e88acfd1 state to 00000000548834f9 [ 2.084826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e88acfd1 [ 2.084845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c2abb21 state to 00000000548834f9 [ 2.084864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000ff2cde6 state to 00000000548834f9 [ 2.084881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009f37190d state to 00000000548834f9 [ 2.084900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009f37190d [ 2.084918] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008793e16f state to 00000000548834f9 [ 2.084937] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008793e16f [ 2.084955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a71ddeb0 state to 00000000548834f9 [ 2.084972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005371ffea state to 00000000548834f9 [ 2.084990] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005371ffea [ 2.085008] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000757b68ad state to 00000000548834f9 [ 2.085026] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000757b68ad [ 2.085045] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f1595a5f [ 2.085064] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 [ 2.085084] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000e808d856 state to 00000000548834f9 [ 2.085103] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [NOCRTC] [ 2.085121] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [CRTC:51:pipe A] [ 2.085139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c2abb21 [ 2.085157] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 [ 2.085175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000004ac112a0 state to 00000000548834f9 [ 2.085194] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [NOCRTC] [ 2.085211] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [CRTC:72:pipe B] [ 2.085231] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 [ 2.085249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 [ 2.085265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a71ddeb0 [ 2.085283] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 [ 2.085303] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 [ 2.085324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.085335] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.085344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.085353] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.085466] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.085547] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.085583] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 [ 2.096461] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 [ 2.096491] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 [ 2.119701] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.119718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 [ 2.119732] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 [ 2.119746] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 [ 2.119761] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be [ 2.119781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 [ 2.119794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df [ 2.119807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 [ 2.119819] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 [ 2.119831] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 [ 2.119844] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 [ 2.119858] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 [ 2.119870] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b [ 2.119882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 [ 2.119893] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 [ 2.119906] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 [ 2.119917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.119930] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.119943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e [ 2.119956] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.119971] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 [ 2.119984] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 2.119996] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 2.120008] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a [ 2.120020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.120033] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.120045] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.120056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.120073] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.120085] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.120096] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a [ 2.120108] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.120120] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.120134] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.120141] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.120147] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.120153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.120236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.120291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.120315] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.129725] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.129746] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.143811] usb 1-10: new high-speed USB device number 3 using xhci_hcd [ 2.146032] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.146049] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000053155f00 state to 0000000098df4bf3 [ 2.146065] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.146077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f5e6213 state to 0000000098df4bf3 [ 2.146093] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f5e6213 [ 2.146107] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000515dc00f state to 0000000098df4bf3 [ 2.146120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000515dc00f [ 2.146133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 [ 2.146145] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.146156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009d539ce0 state to 0000000098df4bf3 [ 2.146170] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009d539ce0 [ 2.146181] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a35c929d state to 0000000098df4bf3 [ 2.146194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a35c929d [ 2.146205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000046234f6 state to 0000000098df4bf3 [ 2.146217] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 [ 2.146229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e [ 2.146240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 [ 2.146252] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 [ 2.146265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000053155f00 [ 2.146278] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.146292] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000b34fddb1 state to 0000000098df4bf3 [ 2.146305] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [NOCRTC] [ 2.146317] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [CRTC:51:pipe A] [ 2.146329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d [ 2.146341] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.146354] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000416eca0f state to 0000000098df4bf3 [ 2.146366] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [NOCRTC] [ 2.146377] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [CRTC:72:pipe B] [ 2.146390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.146402] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 2.146413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000046234f6 [ 2.146425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.146438] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.146451] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.146458] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.146465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.146470] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.146546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.146602] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.146626] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.163065] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.163088] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.192362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 2.192398] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000091b367b1 state to 00000000fc0cb429 [ 2.192425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 [ 2.192450] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a6369fc8 state to 00000000fc0cb429 [ 2.192481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a6369fc8 [ 2.192510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000062109416 state to 00000000fc0cb429 [ 2.192537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000062109416 [ 2.192562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005fe5cc2f state to 00000000fc0cb429 [ 2.192586] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 00000000fc0cb429 [ 2.192609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000bf01569 state to 00000000fc0cb429 [ 2.192636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000bf01569 [ 2.192659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ab6fdf3f state to 00000000fc0cb429 [ 2.192686] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ab6fdf3f [ 2.192709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 [ 2.192731] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 [ 2.192756] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 [ 2.192779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 [ 2.192804] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f [ 2.192830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000091b367b1 [ 2.192855] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 2.192882] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000168ff23b state to 00000000fc0cb429 [ 2.192908] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [NOCRTC] [ 2.192933] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [CRTC:51:pipe A] [ 2.192960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005fe5cc2f [ 2.192986] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 2.193011] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000da9b77f0 state to 00000000fc0cb429 [ 2.193036] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [NOCRTC] [ 2.193061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [CRTC:72:pipe B] [ 2.193088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ca6e974 state to 00000000fc0cb429 [ 2.193113] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ca6e974 [ 2.193137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 [ 2.193161] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 2.193187] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 2.193212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.193227] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.193239] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.193252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.193403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.193510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.193559] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 2.207959] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 2.207999] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 2.235181] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.235205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 000000001ff947e6 [ 2.235220] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 [ 2.235233] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010a446a8 state to 000000001ff947e6 [ 2.235247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010a446a8 [ 2.235260] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c23288bf state to 000000001ff947e6 [ 2.235274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c23288bf [ 2.235287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d365bfc5 state to 000000001ff947e6 [ 2.235301] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001775ba6b state to 000000001ff947e6 [ 2.235316] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009a9a5a77 state to 000000001ff947e6 [ 2.235328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009a9a5a77 [ 2.235340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000382acb58 state to 000000001ff947e6 [ 2.235352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000382acb58 [ 2.235364] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006164f3e3 state to 000000001ff947e6 [ 2.235376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000008409a024 state to 000000001ff947e6 [ 2.235388] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000008409a024 [ 2.235400] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000083c05b3d state to 000000001ff947e6 [ 2.235412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000083c05b3d [ 2.235425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a [ 2.235438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.235451] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000fc47d714 state to 000000001ff947e6 [ 2.235464] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [NOCRTC] [ 2.235476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [CRTC:51:pipe A] [ 2.235489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d365bfc5 [ 2.235501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.235514] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 000000001ff947e6 [ 2.235526] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] [ 2.235538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] [ 2.235551] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000048e8a8c4 state to 000000001ff947e6 [ 2.235563] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000048e8a8c4 [ 2.235575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006164f3e3 [ 2.235587] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.235599] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.235628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.235635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.235641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.235647] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.235730] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.235784] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.235815] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.246467] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.246485] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.258018] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.258028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 [ 2.258037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 000000006432a660 [ 2.258045] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 [ 2.258054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 [ 2.258061] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 [ 2.258069] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 [ 2.258077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 [ 2.258084] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 000000006432a660 [ 2.258092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 [ 2.258100] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 [ 2.258110] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 [ 2.258118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f [ 2.258125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 [ 2.258132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 [ 2.258139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 [ 2.258146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.258153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.258161] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa [ 2.258169] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.258178] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000227e02b1 state to 000000006432a660 [ 2.258186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [NOCRTC] [ 2.258193] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [CRTC:51:pipe A] [ 2.258203] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 [ 2.258210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.258219] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 [ 2.258226] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] [ 2.258233] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] [ 2.258242] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.258249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.258256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 [ 2.258263] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.258271] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.258281] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.258285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.258289] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.258293] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.258354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.258387] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.258403] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.274508] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.274524] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.287455] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.287470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 [ 2.287483] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.287494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 [ 2.287508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f [ 2.287519] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 [ 2.287531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 [ 2.287542] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 2.287553] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.287563] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 [ 2.287574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 2.287585] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 [ 2.287595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 2.287610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 [ 2.287624] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 [ 2.287635] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 [ 2.287645] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 [ 2.287656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a [ 2.287667] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c [ 2.287678] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.287690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009b609533 state to 0000000098df4bf3 [ 2.287701] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [NOCRTC] [ 2.287712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [CRTC:51:pipe A] [ 2.287723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 2.287734] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.287744] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000050cb1035 state to 0000000098df4bf3 [ 2.287755] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [NOCRTC] [ 2.287765] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [CRTC:72:pipe B] [ 2.287782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.287792] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 2.287803] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f [ 2.287813] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.287825] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.287839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.287846] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.287851] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.287856] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.287928] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.287977] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.287999] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.292557] usb 1-10: New USB device found, idVendor=0557, idProduct=7000, bcdDevice= 0.00 [ 2.292559] usb 1-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.293488] hub 1-10:1.0: USB hub found [ 2.293604] hub 1-10:1.0: 4 ports detected [ 2.296162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.296181] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.314444] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 2.314463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c4a0e3a state to 00000000fc0cb429 [ 2.314480] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 00000000fc0cb429 [ 2.314494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a8e00a70 state to 00000000fc0cb429 [ 2.314511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a8e00a70 [ 2.314525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007f2e9b45 state to 00000000fc0cb429 [ 2.314540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000007f2e9b45 [ 2.314554] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 [ 2.314568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 00000000fc0cb429 [ 2.314581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f4491376 state to 00000000fc0cb429 [ 2.314596] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f4491376 [ 2.314609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009bdf158a state to 00000000fc0cb429 [ 2.314623] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009bdf158a [ 2.314636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003292b89f state to 00000000fc0cb429 [ 2.314649] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 [ 2.314663] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 [ 2.314677] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d93e8df3 state to 00000000fc0cb429 [ 2.314690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d93e8df3 [ 2.314705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c4a0e3a [ 2.314719] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 2.314734] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000309bb6f5 state to 00000000fc0cb429 [ 2.314749] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [NOCRTC] [ 2.314763] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [CRTC:51:pipe A] [ 2.314776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 [ 2.314791] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 2.314805] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000005b4f258 state to 00000000fc0cb429 [ 2.314818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [NOCRTC] [ 2.314832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [CRTC:72:pipe B] [ 2.314846] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 [ 2.314859] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 2.314872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003292b89f [ 2.314886] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 2.314900] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 2.314915] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.314923] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.314930] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.314936] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.315024] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.315085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.315120] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 2.329803] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 2.329826] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 2.348527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.348550] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000df34b7b3 state to 000000006432a660 [ 2.348569] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 [ 2.348583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ed11a5b9 state to 000000006432a660 [ 2.348600] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ed11a5b9 [ 2.348615] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000f8d239cd state to 000000006432a660 [ 2.348630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000f8d239cd [ 2.348644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005f11c147 state to 000000006432a660 [ 2.348661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 [ 2.348674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000457aaa57 state to 000000006432a660 [ 2.348689] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000457aaa57 [ 2.348702] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b1ca1c71 state to 000000006432a660 [ 2.348716] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b1ca1c71 [ 2.348730] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b4343291 state to 000000006432a660 [ 2.348743] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000067db6375 state to 000000006432a660 [ 2.348758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000067db6375 [ 2.348777] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.348791] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.348806] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000df34b7b3 [ 2.348821] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.348836] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 [ 2.348851] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] [ 2.348865] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] [ 2.348883] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005f11c147 [ 2.348897] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.348911] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.348926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.348939] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.348954] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.348969] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.348982] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b4343291 [ 2.348996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.349010] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.349026] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.349034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.349041] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.349048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.349141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.349203] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.349231] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.363033] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.363056] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.381721] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.381738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008ffba3f3 state to 00000000c6c933d1 [ 2.381754] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 [ 2.381767] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 [ 2.381784] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 [ 2.381798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 [ 2.381813] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 [ 2.381827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 [ 2.381841] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 2.381853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 [ 2.381868] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 [ 2.381882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 2.381896] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 2.381909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.381922] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 [ 2.381935] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab [ 2.381948] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 [ 2.381962] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 [ 2.381976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008ffba3f3 [ 2.381992] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.382007] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000046dc0413 state to 00000000c6c933d1 [ 2.382021] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [NOCRTC] [ 2.382035] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [CRTC:51:pipe A] [ 2.382048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 [ 2.382062] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.382075] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000002e396b94 state to 00000000c6c933d1 [ 2.382089] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [NOCRTC] [ 2.382101] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [CRTC:72:pipe B] [ 2.382115] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 [ 2.382129] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f [ 2.382142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 [ 2.382155] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.382169] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.382186] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.382194] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.382206] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.382212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.382288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.382348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.382376] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.396184] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.396207] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.414905] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.414925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003eec9b7 state to 0000000098df4bf3 [ 2.414942] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.414957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fb96f9d3 state to 0000000098df4bf3 [ 2.414973] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fb96f9d3 [ 2.414988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005342f7e7 state to 0000000098df4bf3 [ 2.415003] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005342f7e7 [ 2.415020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 [ 2.415034] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.415047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000026a13e4f state to 0000000098df4bf3 [ 2.415062] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000026a13e4f [ 2.415076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e81eafbe state to 0000000098df4bf3 [ 2.415090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e81eafbe [ 2.415103] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f101de7e state to 0000000098df4bf3 [ 2.415123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 [ 2.415137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a [ 2.415150] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 [ 2.415164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 [ 2.415180] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003eec9b7 [ 2.415194] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.415209] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009e77ee4b state to 0000000098df4bf3 [ 2.415227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [NOCRTC] [ 2.415241] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [CRTC:51:pipe A] [ 2.415255] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe [ 2.415269] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.415284] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006fd04029 state to 0000000098df4bf3 [ 2.415298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [NOCRTC] [ 2.415311] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [CRTC:72:pipe B] [ 2.415328] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.415342] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 2.415355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f101de7e [ 2.415369] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.415383] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.415399] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.415407] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.415414] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.415423] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.415506] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.415569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.415598] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.420197] usb 2-2: new SuperSpeed Gen 1 USB device number 3 using xhci_hcd [ 2.429805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.429829] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.440080] usb 2-2: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 [ 2.440081] usb 2-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.441055] hub 2-2:1.0: USB hub found [ 2.441232] hub 2-2:1.0: 4 ports detected [ 2.451314] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 2.451340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a6369fc8 state to 00000000fc0cb429 [ 2.451359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 [ 2.451375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000091b367b1 state to 00000000fc0cb429 [ 2.451395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000091b367b1 [ 2.451412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 00000000fc0cb429 [ 2.451429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f [ 2.451446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bf01569 state to 00000000fc0cb429 [ 2.451462] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 [ 2.451477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ab6fdf3f state to 00000000fc0cb429 [ 2.451494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ab6fdf3f [ 2.451510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 [ 2.451526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b [ 2.451543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 [ 2.451559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 [ 2.451575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 [ 2.451591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 [ 2.451607] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f [ 2.451624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a6369fc8 [ 2.451641] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 2.451660] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ee6ef05 state to 00000000fc0cb429 [ 2.451677] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [NOCRTC] [ 2.451693] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [CRTC:51:pipe A] [ 2.451710] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bf01569 [ 2.451726] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 2.451743] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009647804d state to 00000000fc0cb429 [ 2.451760] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [NOCRTC] [ 2.451784] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [CRTC:72:pipe B] [ 2.451801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000dd2a82ac state to 00000000fc0cb429 [ 2.451817] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000dd2a82ac [ 2.451832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 [ 2.451848] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 2.451865] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 2.451883] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.451892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.451900] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.451908] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.452011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.452082] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.452114] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 2.463087] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 2.463114] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 2.484902] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.484925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 [ 2.484941] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 000000006432a660 [ 2.484955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 [ 2.484971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 [ 2.484985] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 [ 2.485000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f [ 2.485015] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 [ 2.485028] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 000000006432a660 [ 2.485041] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 [ 2.485055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 [ 2.485067] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 [ 2.485081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 [ 2.485094] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 [ 2.485106] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 [ 2.485120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa [ 2.485132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.485146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.485160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 [ 2.485174] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.485189] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 000000006432a660 [ 2.485203] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] [ 2.485216] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] [ 2.485229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 [ 2.485243] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.485257] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 [ 2.485270] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 2.485283] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 2.485297] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.485310] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.485322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 [ 2.485336] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.485349] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.485365] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.485373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.485380] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.485386] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.485476] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.485536] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.485568] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.496321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.496343] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.514099] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.514115] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000086e6c525 state to 00000000c6c933d1 [ 2.514130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 [ 2.514143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000076facd10 state to 00000000c6c933d1 [ 2.514159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000076facd10 [ 2.514173] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000900779b1 state to 00000000c6c933d1 [ 2.514187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000900779b1 [ 2.514201] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 [ 2.514214] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 2.514227] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 [ 2.514241] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab [ 2.514254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.514267] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 [ 2.514281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 [ 2.514293] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 [ 2.514306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 [ 2.514319] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 [ 2.514332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 [ 2.514346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000086e6c525 [ 2.514359] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.514373] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000006978e08c state to 00000000c6c933d1 [ 2.514389] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [NOCRTC] [ 2.514402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [CRTC:51:pipe A] [ 2.514415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 [ 2.514429] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.514442] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009efdc675 state to 00000000c6c933d1 [ 2.514455] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [NOCRTC] [ 2.514467] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [CRTC:72:pipe B] [ 2.514485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 [ 2.514499] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 [ 2.514511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f [ 2.514523] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.514537] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.514551] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.514559] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.514566] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.514572] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.514659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.514717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.514743] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.529754] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.529779] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.550511] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.550530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c471465 state to 000000006432a660 [ 2.550547] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 [ 2.550562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059814b3a state to 000000006432a660 [ 2.550581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059814b3a [ 2.550597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bf357c4b state to 000000006432a660 [ 2.550614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bf357c4b [ 2.550629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d9e36170 state to 000000006432a660 [ 2.550644] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 [ 2.550658] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 000000006432a660 [ 2.550675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a [ 2.550690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000071f245df state to 000000006432a660 [ 2.550705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000071f245df [ 2.550720] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000074f436be state to 000000006432a660 [ 2.550735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 000000006432a660 [ 2.550750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e [ 2.550765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.550780] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.550798] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c471465 [ 2.550814] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.550831] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 [ 2.550847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 2.550862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 2.550876] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d9e36170 [ 2.550891] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.550907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.550922] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.550937] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.550953] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.550967] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.550981] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000074f436be [ 2.550996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.551012] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.551029] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.551037] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.551045] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.551053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.551151] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.551217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.551247] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.563034] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.563060] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.567816] usb 1-11: new high-speed USB device number 4 using xhci_hcd [ 2.582973] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.582995] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 [ 2.583010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.583024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 [ 2.583039] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe [ 2.583052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 [ 2.583066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 [ 2.583080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 2.583096] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.583108] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 [ 2.583121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 [ 2.583133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 [ 2.583146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f [ 2.583159] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 [ 2.583171] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 [ 2.583184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 [ 2.583197] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 [ 2.583210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e [ 2.583224] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f [ 2.583237] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.583251] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 0000000098df4bf3 [ 2.583265] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] [ 2.583278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] [ 2.583290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 2.583303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.583317] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 [ 2.583329] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] [ 2.583342] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] [ 2.583355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.583368] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 2.583380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c [ 2.583392] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.583406] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.583424] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.583432] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.583438] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.583444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.583528] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.583585] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.583612] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.596477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.596495] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.610890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.610906] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000382acb58 state to 000000001ff947e6 [ 2.610919] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 000000001ff947e6 [ 2.610930] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009a9a5a77 state to 000000001ff947e6 [ 2.610943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009a9a5a77 [ 2.610955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d365bfc5 state to 000000001ff947e6 [ 2.610966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d365bfc5 [ 2.610978] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c23288bf state to 000000001ff947e6 [ 2.610989] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 000000001ff947e6 [ 2.611000] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000010a446a8 state to 000000001ff947e6 [ 2.611012] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000010a446a8 [ 2.611022] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e536e28a state to 000000001ff947e6 [ 2.611033] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e536e28a [ 2.611044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fac02d29 state to 000000001ff947e6 [ 2.611054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e23783d2 state to 000000001ff947e6 [ 2.611065] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e23783d2 [ 2.611075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000009ecd9d0a state to 000000001ff947e6 [ 2.611086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000009ecd9d0a [ 2.611097] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000382acb58 [ 2.611109] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.611121] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000949ef34b state to 000000001ff947e6 [ 2.611132] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [NOCRTC] [ 2.611143] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [CRTC:51:pipe A] [ 2.611153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c23288bf [ 2.611164] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.611175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000025f34563 state to 000000001ff947e6 [ 2.611186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [NOCRTC] [ 2.611196] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [CRTC:72:pipe B] [ 2.611213] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 000000001ff947e6 [ 2.611224] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b [ 2.611234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fac02d29 [ 2.611244] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.611255] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.611268] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.611274] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.611280] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.611285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.611363] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.611411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.611436] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.624544] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.624568] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.648394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.648422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 [ 2.648448] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 [ 2.648470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 [ 2.648494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 [ 2.648515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 [ 2.648536] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 [ 2.648557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 [ 2.648577] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 [ 2.648596] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 [ 2.648618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 [ 2.648637] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 [ 2.648657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f [ 2.648680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 [ 2.648699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 [ 2.648719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 [ 2.648738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.648758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.648785] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa [ 2.648805] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.648826] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 [ 2.648848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] [ 2.648867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] [ 2.648892] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 [ 2.648912] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.648933] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 [ 2.648953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] [ 2.648972] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] [ 2.648999] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 2.649018] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 2.649037] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 [ 2.649057] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.649077] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.649105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.649116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.649126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.649136] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.649258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.649348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.649388] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.663045] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.663078] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.695073] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.695099] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000046234f6 state to 0000000098df4bf3 [ 2.695121] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.695139] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a35c929d state to 0000000098df4bf3 [ 2.695164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a35c929d [ 2.695189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 0000000098df4bf3 [ 2.695210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 [ 2.695229] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 [ 2.695248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.695265] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 0000000098df4bf3 [ 2.695284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f [ 2.695303] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007f5e6213 state to 0000000098df4bf3 [ 2.695322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007f5e6213 [ 2.695340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053155f00 state to 0000000098df4bf3 [ 2.695357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 [ 2.695376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e [ 2.695396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 [ 2.695414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 [ 2.695435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000046234f6 [ 2.695454] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.695474] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 0000000098df4bf3 [ 2.695494] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] [ 2.695512] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] [ 2.695531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d [ 2.695550] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.695569] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 [ 2.695587] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] [ 2.695604] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] [ 2.695623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.695641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 [ 2.695658] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053155f00 [ 2.695676] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.695695] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.695725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.695736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.695745] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.695755] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.695886] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.695968] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.696005] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.713154] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.713185] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.716173] usb 1-11: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 [ 2.716176] usb 1-11: New USB device strings: Mfr=0, Product=0, SerialNumber=1 [ 2.716179] usb 1-11: SerialNumber: DC0F18713FF2 [ 2.717025] hub 1-11:1.0: USB hub found [ 2.717053] hub 1-11:1.0: 4 ports detected [ 2.744349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.744373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000098081998 state to 000000001ff947e6 [ 2.744393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 [ 2.744411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007284ebf4 state to 000000001ff947e6 [ 2.744433] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007284ebf4 [ 2.744451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000092bd7e4c state to 000000001ff947e6 [ 2.744470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000092bd7e4c [ 2.744488] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000687f38c3 state to 000000001ff947e6 [ 2.744505] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003eebba06 state to 000000001ff947e6 [ 2.744522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000072a9793c state to 000000001ff947e6 [ 2.744540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000072a9793c [ 2.744559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 000000001ff947e6 [ 2.744577] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac [ 2.744593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 000000001ff947e6 [ 2.744609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 000000001ff947e6 [ 2.744627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 [ 2.744643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 000000001ff947e6 [ 2.744660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c [ 2.744678] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000098081998 [ 2.744696] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.744715] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ebbd72c state to 000000001ff947e6 [ 2.744734] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [NOCRTC] [ 2.744751] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [CRTC:51:pipe A] [ 2.744773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000687f38c3 [ 2.744790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.744808] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001175f931 state to 000000001ff947e6 [ 2.744825] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [NOCRTC] [ 2.744842] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [CRTC:72:pipe B] [ 2.744860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000053a23bd6 state to 000000001ff947e6 [ 2.744877] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000053a23bd6 [ 2.744893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e [ 2.744911] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.744928] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.744948] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.744958] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.744969] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.744977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.745085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.745164] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.745209] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.757894] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.757923] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.781266] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.781290] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 [ 2.781313] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 [ 2.781332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 [ 2.781353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 [ 2.781371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 [ 2.781390] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 [ 2.781409] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 [ 2.781426] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 [ 2.781443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 [ 2.781462] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 [ 2.781478] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 [ 2.781496] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd [ 2.781514] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 [ 2.781530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 [ 2.781548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 [ 2.781565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 [ 2.781583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d [ 2.781602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 [ 2.781620] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.781639] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 [ 2.781658] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] [ 2.781675] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] [ 2.781694] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 [ 2.781712] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.781729] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 2.781747] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 2.781764] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 2.781782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.781800] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.781816] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 [ 2.781833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.781851] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.781869] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.781879] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.781888] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.781897] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.782005] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.782084] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.782120] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.796434] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.796463] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.815843] usb 1-10.1: new low-speed USB device number 5 using xhci_hcd [ 2.830298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.830323] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dd33f136 state to 00000000c6c933d1 [ 2.830358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 [ 2.830378] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 [ 2.830401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 [ 2.830422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008ffba3f3 state to 00000000c6c933d1 [ 2.830443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008ffba3f3 [ 2.830466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 [ 2.830485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 2.830504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 [ 2.830525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 [ 2.830544] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 [ 2.830564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f [ 2.830583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.830601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 [ 2.830621] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab [ 2.830640] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 [ 2.830659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 [ 2.830684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000dd33f136 [ 2.830704] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.830725] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 [ 2.830746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] [ 2.830766] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] [ 2.830788] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 [ 2.830808] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.830828] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 [ 2.830848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] [ 2.830867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] [ 2.830890] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 [ 2.830910] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 [ 2.830928] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 [ 2.830948] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.830968] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.831004] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.831015] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.831025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.831035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.831156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.831242] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.831281] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.846410] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.846458] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 2.877085] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 [ 2.877104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 [ 2.877120] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 [ 2.877135] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 [ 2.877153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f [ 2.877167] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 [ 2.877181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 [ 2.877195] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 [ 2.877209] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 [ 2.877222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 [ 2.877236] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 2.877248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 [ 2.877262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 2.877275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 [ 2.877287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 [ 2.877301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 [ 2.877313] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 [ 2.877327] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a [ 2.877344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c [ 2.877357] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 [ 2.877372] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 0000000098df4bf3 [ 2.877386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] [ 2.877399] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] [ 2.877412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c [ 2.877426] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 [ 2.877439] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 [ 2.877452] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] [ 2.877465] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] [ 2.877479] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 [ 2.877492] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 [ 2.877504] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f [ 2.877517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 [ 2.877531] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 [ 2.877553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.877561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.877571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.877577] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.877659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.877719] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.877747] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 [ 2.891314] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 [ 2.891333] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 [ 2.906312] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 [ 2.906333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000918919b3 state to 000000001ff947e6 [ 2.906347] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 000000001ff947e6 [ 2.906358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000005a00270 state to 000000001ff947e6 [ 2.906372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000005a00270 [ 2.906384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000512c7fb3 state to 000000001ff947e6 [ 2.906396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000512c7fb3 [ 2.906408] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000063c0bfb2 state to 000000001ff947e6 [ 2.906419] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 000000001ff947e6 [ 2.906433] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004acae8d3 state to 000000001ff947e6 [ 2.906445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004acae8d3 [ 2.906456] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 000000001ff947e6 [ 2.906468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 [ 2.906479] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 000000001ff947e6 [ 2.906489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a4c468ad state to 000000001ff947e6 [ 2.906500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a4c468ad [ 2.906511] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000320b468c state to 000000001ff947e6 [ 2.906522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000320b468c [ 2.906542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000918919b3 [ 2.906555] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 [ 2.906568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ba4c5dc3 state to 000000001ff947e6 [ 2.906580] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [NOCRTC] [ 2.906591] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [CRTC:51:pipe A] [ 2.906602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000063c0bfb2 [ 2.906613] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 [ 2.906625] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ae0223f3 state to 000000001ff947e6 [ 2.906636] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [NOCRTC] [ 2.906646] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [CRTC:72:pipe B] [ 2.906661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 000000001ff947e6 [ 2.906672] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 [ 2.906682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d [ 2.906693] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 [ 2.906705] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 [ 2.906718] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.906725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.906731] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.906736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.906813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.906863] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.906886] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 [ 2.913164] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 [ 2.913183] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 [ 2.933406] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 2.933430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 [ 2.933451] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 [ 2.933468] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 [ 2.933490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 [ 2.933508] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 [ 2.933527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f [ 2.933545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 [ 2.933563] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 [ 2.933583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 [ 2.933601] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 [ 2.933618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 [ 2.933636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 [ 2.933653] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 [ 2.933670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 [ 2.933687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa [ 2.933705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 2.933723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 2.933741] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 [ 2.933759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 2.933778] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 [ 2.933800] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] [ 2.933818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] [ 2.933836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 [ 2.933853] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 2.933871] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 [ 2.933888] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 2.933905] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 2.933923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 [ 2.933940] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 2.933957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 [ 2.933974] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 2.933992] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 2.934021] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.934031] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.934039] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.934048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.934156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.934235] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.934270] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 2.945099] usb 1-10.1: New USB device found, idVendor=0557, idProduct=2419, bcdDevice= 1.00 [ 2.945102] usb 1-10.1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.946202] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 2.946230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 2.969637] hid: raw HID events driver (C) Jiri Kosina [ 2.980218] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 2.980244] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 [ 2.980267] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 [ 2.980286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 [ 2.980309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 [ 2.980330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000097efae80 state to 00000000c6c933d1 [ 2.980351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000097efae80 [ 2.980372] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 [ 2.980391] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 2.980410] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 [ 2.980431] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab [ 2.980449] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 [ 2.980470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 [ 2.980489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 [ 2.980507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 [ 2.980527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 [ 2.980547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 [ 2.980566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 [ 2.980587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 [ 2.980607] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 2.980628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 [ 2.980650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] [ 2.980670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] [ 2.980690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 [ 2.980709] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 2.980728] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 [ 2.980748] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] [ 2.980767] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] [ 2.980792] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 [ 2.980812] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 [ 2.980830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f [ 2.980850] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 2.980871] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 2.980898] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 2.980910] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 2.980920] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 2.980929] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 2.981048] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 2.981050] usbcore: registered new interface driver usbhid [ 2.981135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 2.981135] usbhid: USB HID core driver [ 2.981182] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 2.983750] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.0/0003:0557:2419.0001/input/input4 [ 2.996172] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 2.996195] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.016364] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 [ 3.016380] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 [ 3.016393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 [ 3.016405] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 [ 3.016419] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be [ 3.016432] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 [ 3.016445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df [ 3.016458] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 [ 3.016470] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 [ 3.016481] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 [ 3.016494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 [ 3.016507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 [ 3.016519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b [ 3.016531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 [ 3.016543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 [ 3.016556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 [ 3.016568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 [ 3.016580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b [ 3.016593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e [ 3.016606] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 [ 3.016619] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 [ 3.016632] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] [ 3.016644] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] [ 3.016657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a [ 3.016669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 [ 3.016682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 [ 3.016694] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] [ 3.016706] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] [ 3.016719] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 [ 3.016731] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 3.016743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a [ 3.016755] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 [ 3.016767] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 [ 3.016778] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.016785] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.016791] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.016798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.016860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.016917] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.016940] [drm:drm_atomic_commit [drm]] committing 000000006432a660 [ 3.020983] scsi 4:0:0:0: Direct-Access Generic Compact Flash 0.00 PQ: 0 ANSI: 2 [ 3.021765] scsi 4:0:0:1: Direct-Access Generic SD/MMC 0.00 PQ: 0 ANSI: 2 [ 3.022194] scsi 4:0:0:2: Direct-Access Generic microSD 0.00 PQ: 0 ANSI: 2 [ 3.022768] scsi 4:0:0:3: Direct-Access Generic MS/MS-PRO 0.00 PQ: 0 ANSI: 2 [ 3.023138] scsi 4:0:0:4: Direct-Access Generic SM/xD-Picture 0.00 PQ: 0 ANSI: 2 [ 3.029581] sd 1:0:0:0: [sda] 1000215216 512-byte logical blocks: (512 GB/477 GiB) [ 3.029588] sd 1:0:0:0: [sda] Write Protect is off [ 3.029589] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 3.029597] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 3.043978] hid-generic 0003:0557:2419.0001: input,hidraw0: USB HID v1.00 Keyboard [HID 0557:2419] on usb-0000:00:14.0-10.1/input0 [ 3.044084] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.1/0003:0557:2419.0002/input/input5 [ 3.044277] hid-generic 0003:0557:2419.0002: input,hidraw1: USB HID v1.00 Mouse [HID 0557:2419] on usb-0000:00:14.0-10.1/input1 [ 3.044891] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 [ 3.044908] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 [ 3.044928] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 [ 3.044945] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007b36813f state to 00000000c29bd936 [ 3.044964] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ec014e4 state to 00000000c29bd936 [ 3.044984] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000555d146c state to 00000000c29bd936 [ 3.045005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000555d146c [ 3.045023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b2cdb294 state to 00000000c29bd936 [ 3.045041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b2cdb294 [ 3.045060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000053454233 state to 00000000c29bd936 [ 3.045079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a746018c state to 00000000c29bd936 [ 3.045097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 [ 3.045113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 [ 3.045123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b5f6abf5 state to 00000000c29bd936 [ 3.045134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b5f6abf5 [ 3.045147] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000c775be6 state to 00000000c29bd936 [ 3.045156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005d690c84 state to 00000000c29bd936 [ 3.045167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005d690c84 [ 3.045177] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000122a804f state to 00000000c29bd936 [ 3.045188] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000122a804f [ 3.045200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007b36813f [ 3.045211] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 [ 3.045222] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004edc31e9 state to 00000000c29bd936 [ 3.045238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [NOCRTC] [ 3.045256] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [CRTC:51:pipe A] [ 3.045274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000053454233 [ 3.045294] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 [ 3.045312] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005d1fe044 state to 00000000c29bd936 [ 3.045325] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [NOCRTC] [ 3.045335] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [CRTC:72:pipe B] [ 3.045350] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ef13faa state to 00000000c29bd936 [ 3.045360] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ef13faa [ 3.045369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000c775be6 [ 3.045380] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 [ 3.045390] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 [ 3.045403] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.045410] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.045415] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.045420] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.045496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.045543] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.045577] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 [ 3.052647] sd 4:0:0:4: [sdf] Attached SCSI removable disk [ 3.054117] sda: sda1 sda2 < sda5 > [ 3.054604] sd 1:0:0:0: [sda] supports TCG Opal [ 3.054605] sd 1:0:0:0: [sda] Attached SCSI disk [ 3.056264] sd 4:0:0:3: [sde] Attached SCSI removable disk [ 3.057329] sd 4:0:0:1: [sdc] Attached SCSI removable disk [ 3.057645] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 [ 3.057661] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 [ 3.060799] sd 4:0:0:0: [sdb] Attached SCSI removable disk [ 3.071802] usb 1-12: new high-speed USB device number 6 using xhci_hcd [ 3.072920] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 [ 3.072942] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fac02d29 state to 00000000ffbe70d8 [ 3.072961] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000ffbe70d8 [ 3.072980] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ecd9d0a state to 00000000ffbe70d8 [ 3.072992] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ecd9d0a [ 3.073004] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000098081998 state to 00000000ffbe70d8 [ 3.073017] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000098081998 [ 3.073035] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007284ebf4 state to 00000000ffbe70d8 [ 3.073054] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 [ 3.073071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000092bd7e4c state to 00000000ffbe70d8 [ 3.073089] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000092bd7e4c [ 3.073105] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 00000000ffbe70d8 [ 3.073123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac [ 3.073140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 00000000ffbe70d8 [ 3.073157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 00000000ffbe70d8 [ 3.073175] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 [ 3.073189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 00000000ffbe70d8 [ 3.073199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c [ 3.073211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000fac02d29 [ 3.073222] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 [ 3.073233] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000be46149d state to 00000000ffbe70d8 [ 3.073244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [NOCRTC] [ 3.073254] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [CRTC:51:pipe A] [ 3.073265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000007284ebf4 [ 3.073276] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 [ 3.073286] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000068a1fb01 state to 00000000ffbe70d8 [ 3.073297] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [NOCRTC] [ 3.073307] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [CRTC:72:pipe B] [ 3.073318] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000cf23fbdd state to 00000000ffbe70d8 [ 3.073328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000cf23fbdd [ 3.073338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e [ 3.073348] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 [ 3.073359] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 [ 3.073371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.073377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.073382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.073387] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.073458] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.073505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.073529] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 [ 3.073552] sd 4:0:0:2: [sdd] Attached SCSI removable disk [ 3.079604] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 [ 3.079650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 [ 3.108427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 [ 3.108443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000122a804f state to 00000000c29bd936 [ 3.108457] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000228f716d state to 00000000c29bd936 [ 3.108470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000005d690c84 state to 00000000c29bd936 [ 3.108486] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000005d690c84 [ 3.108499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000c775be6 state to 00000000c29bd936 [ 3.108513] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000c775be6 [ 3.108527] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b5f6abf5 state to 00000000c29bd936 [ 3.108540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 [ 3.108552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 [ 3.108566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 [ 3.108578] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053454233 state to 00000000c29bd936 [ 3.108592] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053454233 [ 3.108604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b2cdb294 state to 00000000c29bd936 [ 3.108616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000555d146c state to 00000000c29bd936 [ 3.108630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000555d146c [ 3.108642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007b36813f state to 00000000c29bd936 [ 3.108655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007b36813f [ 3.108668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000122a804f [ 3.108682] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 [ 3.108695] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eee09833 state to 00000000c29bd936 [ 3.108709] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [NOCRTC] [ 3.108722] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [CRTC:51:pipe A] [ 3.108736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b5f6abf5 [ 3.108749] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 [ 3.108761] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000898e3e27 state to 00000000c29bd936 [ 3.108774] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [NOCRTC] [ 3.108787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [CRTC:72:pipe B] [ 3.108801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d0e256d1 state to 00000000c29bd936 [ 3.108814] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d0e256d1 [ 3.108826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b2cdb294 [ 3.108839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 [ 3.108865] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 [ 3.108875] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.108882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.108887] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.108892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.108956] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.109003] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.109025] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 [ 3.124527] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 [ 3.124544] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 [ 3.137517] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a6b51f [ 3.137531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000012530223 state to 0000000073a6b51f [ 3.137543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000009be30044 state to 0000000073a6b51f [ 3.137555] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ffe00c37 state to 0000000073a6b51f [ 3.137567] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ffe00c37 [ 3.137577] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000023a9a422 state to 0000000073a6b51f [ 3.137587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000023a9a422 [ 3.137598] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bdb8d82 state to 0000000073a6b51f [ 3.137607] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 0000000073a6b51f [ 3.137617] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e3147659 state to 0000000073a6b51f [ 3.137627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e3147659 [ 3.137636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000004825b29a state to 0000000073a6b51f [ 3.137646] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000004825b29a [ 3.137657] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005788f64c state to 0000000073a6b51f [ 3.137667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000032e38a43 state to 0000000073a6b51f [ 3.137676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000032e38a43 [ 3.137685] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000089408e5f state to 0000000073a6b51f [ 3.137695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000089408e5f [ 3.137705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000012530223 [ 3.137715] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000073a6b51f [ 3.137726] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000748c93aa state to 0000000073a6b51f [ 3.137737] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [NOCRTC] [ 3.137746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [CRTC:51:pipe A] [ 3.137760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bdb8d82 [ 3.137769] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000073a6b51f [ 3.137779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f1b6922b state to 0000000073a6b51f [ 3.137789] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [NOCRTC] [ 3.137798] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [CRTC:72:pipe B] [ 3.137808] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ad566469 state to 0000000073a6b51f [ 3.137818] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ad566469 [ 3.137827] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005788f64c [ 3.137836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000073a6b51f [ 3.137846] [drm:drm_atomic_check_only [drm]] checking 0000000073a6b51f [ 3.137866] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.137872] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.137882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.137886] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.137944] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.137988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.138008] [drm:drm_atomic_commit [drm]] committing 0000000073a6b51f [ 3.146528] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a6b51f [ 3.146545] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a6b51f [ 3.157850] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 [ 3.157860] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002f4e481a state to 00000000619b20f5 [ 3.157869] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001b7eae74 state to 00000000619b20f5 [ 3.157877] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000025544875 state to 00000000619b20f5 [ 3.157886] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000025544875 [ 3.157894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008c95634f state to 00000000619b20f5 [ 3.157902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008c95634f [ 3.157910] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000483335fe state to 00000000619b20f5 [ 3.157917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ae874d06 state to 00000000619b20f5 [ 3.157925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 00000000619b20f5 [ 3.157932] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 [ 3.157941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000865de88c state to 00000000619b20f5 [ 3.157948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000865de88c [ 3.157955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001c64fec3 state to 00000000619b20f5 [ 3.157962] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001726835f state to 00000000619b20f5 [ 3.157970] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001726835f [ 3.157977] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006011267c state to 00000000619b20f5 [ 3.157984] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006011267c [ 3.157993] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002f4e481a [ 3.158001] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 [ 3.158009] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 00000000619b20f5 [ 3.158017] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] [ 3.158024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] [ 3.158031] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000483335fe [ 3.158039] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 [ 3.158046] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000b34fddb1 state to 00000000619b20f5 [ 3.158054] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [NOCRTC] [ 3.158061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [CRTC:72:pipe B] [ 3.158069] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000904bdb49 state to 00000000619b20f5 [ 3.158076] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000904bdb49 [ 3.158083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001c64fec3 [ 3.158090] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 [ 3.158098] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 [ 3.158108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.158112] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.158116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.158119] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.158180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.158213] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.158229] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 [ 3.174683] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 [ 3.174697] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 [ 3.186485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.186502] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f11c147 state to 00000000f3200e59 [ 3.186513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 00000000f3200e59 [ 3.186523] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000457aaa57 state to 00000000f3200e59 [ 3.186534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000457aaa57 [ 3.186545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 00000000f3200e59 [ 3.186555] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 [ 3.186565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b4343291 state to 00000000f3200e59 [ 3.186575] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 00000000f3200e59 [ 3.186584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000067db6375 state to 00000000f3200e59 [ 3.186594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000067db6375 [ 3.186604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ed11a5b9 state to 00000000f3200e59 [ 3.186614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ed11a5b9 [ 3.186623] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df34b7b3 state to 00000000f3200e59 [ 3.186632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e5b7e29b state to 00000000f3200e59 [ 3.186641] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e5b7e29b [ 3.186650] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001c471465 state to 00000000f3200e59 [ 3.186659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001c471465 [ 3.186670] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000005f11c147 [ 3.186680] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.186690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000140b0238 state to 00000000f3200e59 [ 3.186704] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [NOCRTC] [ 3.186714] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [CRTC:51:pipe A] [ 3.186723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b4343291 [ 3.186733] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.186742] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001ddd4fdd state to 00000000f3200e59 [ 3.186752] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [NOCRTC] [ 3.186761] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [CRTC:72:pipe B] [ 3.186772] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 00000000f3200e59 [ 3.186781] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 [ 3.186790] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df34b7b3 [ 3.186800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.186810] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.186829] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.186834] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.186839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.186844] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.186901] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.186949] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.186968] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.196452] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.196472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.216790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 [ 3.216813] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000063c0bfb2 state to 00000000ffbe70d8 [ 3.216833] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 00000000ffbe70d8 [ 3.216851] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000918919b3 state to 00000000ffbe70d8 [ 3.216872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000918919b3 [ 3.216889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000005a00270 state to 00000000ffbe70d8 [ 3.216907] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000005a00270 [ 3.216924] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000512c7fb3 state to 00000000ffbe70d8 [ 3.216940] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 [ 3.216956] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018dbb82d state to 00000000ffbe70d8 [ 3.216974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018dbb82d [ 3.216990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 [ 3.217006] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 [ 3.217023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a4c468ad state to 00000000ffbe70d8 [ 3.217038] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000320b468c state to 00000000ffbe70d8 [ 3.217055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000320b468c [ 3.217074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000063ec03c state to 00000000ffbe70d8 [ 3.217090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000063ec03c [ 3.217108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000063c0bfb2 [ 3.217125] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 [ 3.217143] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d05a5c4c state to 00000000ffbe70d8 [ 3.217161] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [NOCRTC] [ 3.217177] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [CRTC:51:pipe A] [ 3.217193] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000512c7fb3 [ 3.217210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 [ 3.217227] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000fc47d714 state to 00000000ffbe70d8 [ 3.217243] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [NOCRTC] [ 3.217259] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [CRTC:72:pipe B] [ 3.217276] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 [ 3.217293] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b [ 3.217308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a4c468ad [ 3.217325] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 [ 3.217342] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 [ 3.217360] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.217371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.217382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.217390] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.217495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.217569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.217604] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 [ 3.220944] usb 1-12: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 [ 3.220946] usb 1-12: New USB device strings: Mfr=0, Product=0, SerialNumber=1 [ 3.220948] usb 1-12: SerialNumber: CD0F18513FF2 [ 3.221863] hub 1-12:1.0: USB hub found [ 3.221920] hub 1-12:1.0: 4 ports detected [ 3.229639] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 [ 3.229666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 [ 3.259936] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 [ 3.259967] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007835ad2c state to 00000000c29bd936 [ 3.259995] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000c29bd936 [ 3.260020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a0e4907f state to 00000000c29bd936 [ 3.260049] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a0e4907f [ 3.260075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c342e8b6 state to 00000000c29bd936 [ 3.260102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c342e8b6 [ 3.260127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f85c23ef state to 00000000c29bd936 [ 3.260151] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 [ 3.260174] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e025482e state to 00000000c29bd936 [ 3.260200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e025482e [ 3.260224] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000fcc8f6c state to 00000000c29bd936 [ 3.260249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000000fcc8f6c [ 3.260275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000093fc8e4 state to 00000000c29bd936 [ 3.260299] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005f84ed88 state to 00000000c29bd936 [ 3.260324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005f84ed88 [ 3.260348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006115325a state to 00000000c29bd936 [ 3.260373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006115325a [ 3.260399] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007835ad2c [ 3.260425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 [ 3.260452] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000093f6ce9d state to 00000000c29bd936 [ 3.260479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [NOCRTC] [ 3.260503] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [CRTC:51:pipe A] [ 3.260528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f85c23ef [ 3.260552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 [ 3.260578] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000074011bcd state to 00000000c29bd936 [ 3.260602] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [NOCRTC] [ 3.260626] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [CRTC:72:pipe B] [ 3.260651] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000c29bd936 [ 3.260677] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d [ 3.260700] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000093fc8e4 [ 3.260725] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 [ 3.260750] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 [ 3.260776] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.260790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.260802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.260815] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.260951] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.261061] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.261109] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 [ 3.274626] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 [ 3.274674] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 [ 3.299821] usb 1-11.2: new full-speed USB device number 7 using xhci_hcd [ 3.303479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006379f080 [ 3.303499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000559c57fd state to 000000006379f080 [ 3.303517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e59c9ea1 state to 000000006379f080 [ 3.303532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fdc091c8 state to 000000006379f080 [ 3.303551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fdc091c8 [ 3.303572] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a9473c9b state to 000000006379f080 [ 3.303588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a9473c9b [ 3.303604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000089408e5f state to 000000006379f080 [ 3.303618] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 000000006379f080 [ 3.303632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000032e38a43 state to 000000006379f080 [ 3.303648] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000032e38a43 [ 3.303662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005788f64c state to 000000006379f080 [ 3.303677] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005788f64c [ 3.303691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000004825b29a state to 000000006379f080 [ 3.303705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e3147659 state to 000000006379f080 [ 3.303720] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e3147659 [ 3.303734] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bdb8d82 state to 000000006379f080 [ 3.303750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bdb8d82 [ 3.303766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000559c57fd [ 3.303790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006379f080 [ 3.303807] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000000e02d6ba state to 000000006379f080 [ 3.303835] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [NOCRTC] [ 3.303847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [CRTC:51:pipe A] [ 3.303860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000089408e5f [ 3.303872] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006379f080 [ 3.303886] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f298f57c state to 000000006379f080 [ 3.303898] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [NOCRTC] [ 3.303910] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [CRTC:72:pipe B] [ 3.303923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000002aa6a9f8 state to 000000006379f080 [ 3.303935] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000002aa6a9f8 [ 3.303947] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000004825b29a [ 3.303959] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006379f080 [ 3.303971] [drm:drm_atomic_check_only [drm]] checking 000000006379f080 [ 3.304000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.304007] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.304013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.304019] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.304102] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.304157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.304182] [drm:drm_atomic_commit [drm]] committing 000000006379f080 [ 3.313100] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006379f080 [ 3.313118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006379f080 [ 3.326983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 [ 3.326998] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000515dc00f state to 00000000619b20f5 [ 3.327010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b7f89a8d state to 00000000619b20f5 [ 3.327021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008cab647d state to 00000000619b20f5 [ 3.327036] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008cab647d [ 3.327047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 00000000619b20f5 [ 3.327058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 [ 3.327071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a35c929d state to 00000000619b20f5 [ 3.327081] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000347fbd12 state to 00000000619b20f5 [ 3.327091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000046234f6 state to 00000000619b20f5 [ 3.327102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000046234f6 [ 3.327112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053155f00 state to 00000000619b20f5 [ 3.327122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053155f00 [ 3.327132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f3527d8e state to 00000000619b20f5 [ 3.327141] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 00000000619b20f5 [ 3.327152] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 [ 3.327163] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000022fc4ece state to 00000000619b20f5 [ 3.327173] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000022fc4ece [ 3.327184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000515dc00f [ 3.327195] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 [ 3.327206] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 00000000619b20f5 [ 3.327217] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] [ 3.327227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] [ 3.327238] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000a35c929d [ 3.327248] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 [ 3.327258] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009b609533 state to 00000000619b20f5 [ 3.327268] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [NOCRTC] [ 3.327278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [CRTC:72:pipe B] [ 3.327289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 [ 3.327299] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce [ 3.327308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f3527d8e [ 3.327318] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 [ 3.327329] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 [ 3.327341] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.327346] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.327352] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.327356] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.327430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.327475] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.327501] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 [ 3.341307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 [ 3.341359] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 [ 3.379822] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.379844] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 00000000f3200e59 [ 3.379864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000f3200e59 [ 3.379881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000f3200e59 [ 3.379901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b [ 3.379920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000f3200e59 [ 3.379938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 [ 3.379955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 00000000f3200e59 [ 3.379972] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 [ 3.379988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000071f245df state to 00000000f3200e59 [ 3.380005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000071f245df [ 3.380021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000074f436be state to 00000000f3200e59 [ 3.380038] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000074f436be [ 3.380054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000041c6228e state to 00000000f3200e59 [ 3.380069] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 00000000f3200e59 [ 3.380086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d [ 3.380101] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001f82d691 state to 00000000f3200e59 [ 3.380117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001f82d691 [ 3.380135] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a [ 3.380153] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.380174] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ce20e5c8 state to 00000000f3200e59 [ 3.380192] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [NOCRTC] [ 3.380208] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [CRTC:51:pipe A] [ 3.380225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a [ 3.380242] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.380263] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001b5c4b62 state to 00000000f3200e59 [ 3.380279] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [NOCRTC] [ 3.380295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [CRTC:72:pipe B] [ 3.380312] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 00000000f3200e59 [ 3.380328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 [ 3.380344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000041c6228e [ 3.380360] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.380376] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.380402] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.380411] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.380419] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.380427] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.380529] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.380604] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.380646] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.396469] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.396503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.410062] usb 1-11.2: New USB device found, idVendor=17ef, idProduct=6047, bcdDevice= 3.00 [ 3.410064] usb 1-11.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 3.410065] usb 1-11.2: Product: ThinkPad Compact USB Keyboard with TrackPoint [ 3.410067] usb 1-11.2: Manufacturer: Lenovo [ 3.418473] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 [ 3.418496] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001090afab state to 00000000ffbe70d8 [ 3.418515] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000053a23bd6 state to 00000000ffbe70d8 [ 3.418532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028cdc562 state to 00000000ffbe70d8 [ 3.418552] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028cdc562 [ 3.418574] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000063ec03c state to 00000000ffbe70d8 [ 3.418593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000063ec03c [ 3.418610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000320b468c state to 00000000ffbe70d8 [ 3.418627] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a4f0e9bc state to 00000000ffbe70d8 [ 3.418642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000a4c468ad state to 00000000ffbe70d8 [ 3.418660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000a4c468ad [ 3.418680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 [ 3.418697] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 [ 3.418713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 00000000ffbe70d8 [ 3.418728] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000512c7fb3 state to 00000000ffbe70d8 [ 3.418745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000512c7fb3 [ 3.418761] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000005a00270 state to 00000000ffbe70d8 [ 3.418778] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000005a00270 [ 3.418800] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001090afab [ 3.418817] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 [ 3.418835] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001175f931 state to 00000000ffbe70d8 [ 3.418853] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [NOCRTC] [ 3.418869] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [CRTC:51:pipe A] [ 3.418888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000320b468c [ 3.418905] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 [ 3.418922] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ebbd72c state to 00000000ffbe70d8 [ 3.418938] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [NOCRTC] [ 3.418953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [CRTC:72:pipe B] [ 3.418971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 [ 3.418987] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b [ 3.419002] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d [ 3.419018] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 [ 3.419035] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 [ 3.419053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.419062] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.419070] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.419078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.419184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.419258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.419291] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 [ 3.425539] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.0/0003:17EF:6047.0003/input/input6 [ 3.429543] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 [ 3.429570] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 [ 3.451015] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.451031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008af22ea7 state to 00000000c6c933d1 [ 3.451046] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 [ 3.451060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 [ 3.451076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be [ 3.451089] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002a1c343e state to 00000000c6c933d1 [ 3.451104] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002a1c343e [ 3.451117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f7870136 state to 00000000c6c933d1 [ 3.451130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 3.451142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ad384e88 state to 00000000c6c933d1 [ 3.451156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ad384e88 [ 3.451172] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008fde4998 state to 00000000c6c933d1 [ 3.451186] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008fde4998 [ 3.451198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000071cce0a state to 00000000c6c933d1 [ 3.451210] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000007ba2cc3a state to 00000000c6c933d1 [ 3.451223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000007ba2cc3a [ 3.451236] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac0b8286 state to 00000000c6c933d1 [ 3.451249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac0b8286 [ 3.451262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008af22ea7 [ 3.451280] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.451294] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eb0da826 state to 00000000c6c933d1 [ 3.451308] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [NOCRTC] [ 3.451321] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [CRTC:51:pipe A] [ 3.451334] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f7870136 [ 3.451347] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.451361] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 [ 3.451373] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] [ 3.451386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] [ 3.451399] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 [ 3.451412] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 [ 3.451425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000071cce0a [ 3.451438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.451451] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.451465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.451473] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.451481] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.451487] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.451560] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.451617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.451643] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.463098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.463116] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.478096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 [ 3.478112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001726835f state to 00000000619b20f5 [ 3.478125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000be800543 state to 00000000619b20f5 [ 3.478137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c64fec3 state to 00000000619b20f5 [ 3.478150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c64fec3 [ 3.478162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000865de88c state to 00000000619b20f5 [ 3.478174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000865de88c [ 3.478186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000000fcc975 state to 00000000619b20f5 [ 3.478197] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000068c99925 state to 00000000619b20f5 [ 3.478209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000483335fe state to 00000000619b20f5 [ 3.478220] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000483335fe [ 3.478231] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008c95634f state to 00000000619b20f5 [ 3.478243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008c95634f [ 3.478254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000025544875 state to 00000000619b20f5 [ 3.478264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 00000000619b20f5 [ 3.478276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a [ 3.478286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f101de7e state to 00000000619b20f5 [ 3.478297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f101de7e [ 3.478309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001726835f [ 3.478321] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 [ 3.478334] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 00000000619b20f5 [ 3.478346] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] [ 3.478357] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] [ 3.478368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000000fcc975 [ 3.478379] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 [ 3.478390] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009e77ee4b state to 00000000619b20f5 [ 3.478402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [NOCRTC] [ 3.478412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [CRTC:72:pipe B] [ 3.478425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 [ 3.478436] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce [ 3.478446] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000025544875 [ 3.478457] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 [ 3.478469] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 [ 3.478482] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.478488] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.478494] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.478500] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.478579] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.478630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.478659] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 [ 3.484276] lenovo 0003:17EF:6047.0003: input,hidraw2: USB HID v1.00 Keyboard [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input0 [ 3.484522] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.1/0003:17EF:6047.0004/input/input7 [ 3.491321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 [ 3.491337] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 [ 3.504241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 3.504253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015cf0577 state to 00000000fc0cb429 [ 3.504264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 [ 3.504273] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003292b89f state to 00000000fc0cb429 [ 3.504285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003292b89f [ 3.504294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009bdf158a state to 00000000fc0cb429 [ 3.504305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009bdf158a [ 3.504315] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 [ 3.504324] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cf9cfc99 state to 00000000fc0cb429 [ 3.504333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007f2e9b45 state to 00000000fc0cb429 [ 3.504342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007f2e9b45 [ 3.504356] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 [ 3.504366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b [ 3.504375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005fe5cc2f state to 00000000fc0cb429 [ 3.504384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000091b367b1 state to 00000000fc0cb429 [ 3.504393] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000091b367b1 [ 3.504402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000a6369fc8 state to 00000000fc0cb429 [ 3.504411] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000a6369fc8 [ 3.504422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015cf0577 [ 3.504431] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 3.504443] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000bd54c871 state to 00000000fc0cb429 [ 3.504453] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [NOCRTC] [ 3.504462] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [CRTC:51:pipe A] [ 3.504472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 [ 3.504481] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 3.504491] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000309bb6f5 state to 00000000fc0cb429 [ 3.504500] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [NOCRTC] [ 3.504510] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [CRTC:72:pipe B] [ 3.504519] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 [ 3.504529] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 3.504538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005fe5cc2f [ 3.504547] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 3.504558] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 3.504571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.504576] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.504581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.504586] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.504640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.504682] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.504701] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 3.513214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 3.513230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 3.527601] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.527620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002938b22d state to 00000000f3200e59 [ 3.527632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000022f73fd2 state to 00000000f3200e59 [ 3.527643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000041c6228e state to 00000000f3200e59 [ 3.527656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000041c6228e [ 3.527667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000f3200e59 [ 3.527679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be [ 3.527692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000071f245df state to 00000000f3200e59 [ 3.527705] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 [ 3.527716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 00000000f3200e59 [ 3.527728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a [ 3.527738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000d9e36170 state to 00000000f3200e59 [ 3.527749] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000d9e36170 [ 3.527760] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bf357c4b state to 00000000f3200e59 [ 3.527776] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000059814b3a state to 00000000f3200e59 [ 3.527787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000059814b3a [ 3.527798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 [ 3.527809] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd [ 3.527828] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002938b22d [ 3.527839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.527850] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000300c269e state to 00000000f3200e59 [ 3.527862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [NOCRTC] [ 3.527873] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [CRTC:51:pipe A] [ 3.527884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000071f245df [ 3.527894] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.527907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000000afdf5db state to 00000000f3200e59 [ 3.527917] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [NOCRTC] [ 3.527928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [CRTC:72:pipe B] [ 3.527939] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 [ 3.527949] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e [ 3.527959] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bf357c4b [ 3.527970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.527981] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.527993] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.528000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.528005] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.528010] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.528081] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.528130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.528155] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.532011] usb 1-14: new full-speed USB device number 8 using xhci_hcd [ 3.541291] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.541309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.544126] lenovo 0003:17EF:6047.0004: input,hiddev0,hidraw3: USB HID v1.00 Mouse [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input1 [ 3.556564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.556581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000023110e55 state to 00000000c6c933d1 [ 3.556594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 [ 3.556605] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b9dd800a state to 00000000c6c933d1 [ 3.556617] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b9dd800a [ 3.556628] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000edf72591 state to 00000000c6c933d1 [ 3.556640] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000edf72591 [ 3.556651] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009869db1d state to 00000000c6c933d1 [ 3.556661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 3.556671] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bd903151 state to 00000000c6c933d1 [ 3.556682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bd903151 [ 3.556692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c282abaf state to 00000000c6c933d1 [ 3.556703] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c282abaf [ 3.556713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000009f04fd17 state to 00000000c6c933d1 [ 3.556723] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c31f7fa4 state to 00000000c6c933d1 [ 3.556734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c31f7fa4 [ 3.556744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000eac50bee state to 00000000c6c933d1 [ 3.556754] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000eac50bee [ 3.556766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000023110e55 [ 3.556777] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.556793] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000dddcb6a7 state to 00000000c6c933d1 [ 3.556804] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [NOCRTC] [ 3.556814] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [CRTC:51:pipe A] [ 3.556825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009869db1d [ 3.556836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.556846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 [ 3.556857] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] [ 3.556867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] [ 3.556878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 [ 3.556889] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 [ 3.556899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000009f04fd17 [ 3.556909] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.556920] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.556932] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.556938] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.556944] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.556949] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.557021] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.557068] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.557089] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.563101] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.563118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.577479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 [ 3.577503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003073c677 state to 00000000f3200e59 [ 3.577514] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 00000000f3200e59 [ 3.577525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e5892e4f state to 00000000f3200e59 [ 3.577537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e5892e4f [ 3.577548] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c3b3ca94 state to 00000000f3200e59 [ 3.577559] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c3b3ca94 [ 3.577570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000015579631 state to 00000000f3200e59 [ 3.577580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 00000000f3200e59 [ 3.577590] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000083fdb4aa state to 00000000f3200e59 [ 3.577602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000083fdb4aa [ 3.577614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000087dc1fd8 state to 00000000f3200e59 [ 3.577624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000087dc1fd8 [ 3.577635] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ada87627 state to 00000000f3200e59 [ 3.577644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e7bdd2e4 state to 00000000f3200e59 [ 3.577655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e7bdd2e4 [ 3.577666] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 [ 3.577676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd [ 3.577687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000003073c677 [ 3.577698] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 [ 3.577711] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000f3200e59 [ 3.577725] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] [ 3.577735] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] [ 3.577746] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000015579631 [ 3.577756] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 [ 3.577766] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000f3200e59 [ 3.577777] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] [ 3.577787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] [ 3.577798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 [ 3.577808] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e [ 3.577818] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ada87627 [ 3.577828] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 [ 3.577839] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 [ 3.577852] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.577858] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.577863] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.577868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.577941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.577988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.578009] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 [ 3.591295] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 [ 3.591314] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 [ 3.605686] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.605699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003494222 state to 00000000c6c933d1 [ 3.605711] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 [ 3.605722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010343cf4 state to 00000000c6c933d1 [ 3.605736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010343cf4 [ 3.605747] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e6ce87e3 state to 00000000c6c933d1 [ 3.605758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e6ce87e3 [ 3.605769] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac0b8286 state to 00000000c6c933d1 [ 3.605779] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 3.605789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007ba2cc3a state to 00000000c6c933d1 [ 3.605801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007ba2cc3a [ 3.605811] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000071cce0a state to 00000000c6c933d1 [ 3.605822] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000071cce0a [ 3.605832] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008fde4998 state to 00000000c6c933d1 [ 3.605842] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ad384e88 state to 00000000c6c933d1 [ 3.605852] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ad384e88 [ 3.605862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f7870136 state to 00000000c6c933d1 [ 3.605872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f7870136 [ 3.605884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003494222 [ 3.605895] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.605907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 [ 3.605918] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] [ 3.605928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] [ 3.605943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000ac0b8286 [ 3.605953] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.605964] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 [ 3.605975] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] [ 3.605985] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] [ 3.605996] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 [ 3.606007] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f [ 3.606016] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008fde4998 [ 3.606027] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.606038] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.606061] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.606067] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.606072] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.606078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.606138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.606184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.606205] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.613058] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.613075] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.626981] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.626992] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002a1c343e state to 00000000c6c933d1 [ 3.627002] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 [ 3.627011] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 [ 3.627022] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be [ 3.627031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008af22ea7 state to 00000000c6c933d1 [ 3.627042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008af22ea7 [ 3.627051] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b777cf9c state to 00000000c6c933d1 [ 3.627060] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 [ 3.627074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fcdab79b state to 00000000c6c933d1 [ 3.627083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fcdab79b [ 3.627092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000031a1a724 state to 00000000c6c933d1 [ 3.627102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000031a1a724 [ 3.627111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008f0802a0 state to 00000000c6c933d1 [ 3.627119] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000098e2986c state to 00000000c6c933d1 [ 3.627128] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000098e2986c [ 3.627137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000859ae2da state to 00000000c6c933d1 [ 3.627146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000859ae2da [ 3.627156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002a1c343e [ 3.627166] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.627184] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003d8ac4de state to 00000000c6c933d1 [ 3.627198] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [NOCRTC] [ 3.627207] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [CRTC:51:pipe A] [ 3.627217] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b777cf9c [ 3.627226] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.627235] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006c42b361 state to 00000000c6c933d1 [ 3.627244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [NOCRTC] [ 3.627253] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [CRTC:72:pipe B] [ 3.627263] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 [ 3.627272] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 [ 3.627280] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008f0802a0 [ 3.627289] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.627298] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.627309] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.627315] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.627319] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.627324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.627377] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.627418] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.627437] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.641307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.641321] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.641349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 [ 3.641359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b5c379f5 state to 00000000c6c933d1 [ 3.641368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 [ 3.641376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f7870136 state to 00000000c6c933d1 [ 3.641387] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f7870136 [ 3.641396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ad384e88 state to 00000000c6c933d1 [ 3.641405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ad384e88 [ 3.641414] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008fde4998 state to 00000000c6c933d1 [ 3.641422] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 [ 3.641430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000071cce0a state to 00000000c6c933d1 [ 3.641439] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000071cce0a [ 3.641448] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007ba2cc3a state to 00000000c6c933d1 [ 3.641457] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007ba2cc3a [ 3.641465] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ac0b8286 state to 00000000c6c933d1 [ 3.641473] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e6ce87e3 state to 00000000c6c933d1 [ 3.641482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e6ce87e3 [ 3.641490] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010343cf4 state to 00000000c6c933d1 [ 3.641498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010343cf4 [ 3.641508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000b5c379f5 [ 3.641517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 [ 3.641530] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000091d2cf4c state to 00000000c6c933d1 [ 3.641539] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [NOCRTC] [ 3.641547] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [CRTC:51:pipe A] [ 3.641556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008fde4998 [ 3.641564] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 [ 3.641573] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000706e661a state to 00000000c6c933d1 [ 3.641582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [NOCRTC] [ 3.641590] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [CRTC:72:pipe B] [ 3.641599] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 [ 3.641607] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 [ 3.641615] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ac0b8286 [ 3.641624] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 [ 3.641634] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 [ 3.641652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.641657] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.641662] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.641666] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.641717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.641755] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.641773] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 [ 3.657984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 [ 3.658001] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 [ 3.672900] i915 0000:00:02.0: fb1: i915drmfb frame buffer device [ 3.672952] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] [ 3.672975] [drm:drm_client_modeset_probe [drm]] [ 3.672989] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 3.673056] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 3.673077] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 3.673087] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 3.673141] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 3.673439] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.673482] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.674059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.674108] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.674144] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.674179] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 3.676928] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.676971] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 3.677594] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.677624] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.677924] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.677959] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.677966] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 3.677973] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 3.678004] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 3.678433] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.678800] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.680367] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.680395] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.680424] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.680717] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 3.681517] usb 1-14: New USB device found, idVendor=045e, idProduct=028e, bcdDevice= 1.10 [ 3.681519] usb 1-14: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 3.681521] usb 1-14: Product: TGZ Controller [ 3.681522] usb 1-14: Manufacturer: D [ 3.681523] usb 1-14: SerialNumber: 3E5296A0 [ 3.687203] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.687816] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.687827] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.687847] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.687853] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.688062] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.688070] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.688077] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.688084] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.688090] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688097] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688104] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688110] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688116] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688122] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688129] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.688135] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.688143] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 3.688150] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.688157] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.688163] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.688169] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.688176] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.688182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.688188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.688195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.688201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.688208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.688214] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.688220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.688227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.688233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.688239] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.688246] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.688252] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.688258] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.688264] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.688271] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.688277] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.688283] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.688290] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.688296] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.688302] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.688309] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.688315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.688321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.688330] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688337] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688344] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688350] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.688357] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.688363] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.688369] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.688375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.688382] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.688386] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 3.688411] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 3.688721] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.688741] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.689059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.689088] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.689107] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.689125] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 3.691950] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.691968] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 3.692263] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.692279] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.692557] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.692584] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.692588] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 3.692592] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 3.692612] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 3.693013] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.693367] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.694886] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.694906] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.694925] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.695202] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 3.701116] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.701642] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.701650] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.701657] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.701664] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.701855] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.701862] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.701870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.701877] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.701884] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701891] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701898] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701904] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701911] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701918] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701925] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.701931] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.701938] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 3.701945] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.701952] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.701959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.701965] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.701972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.701979] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.701986] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.701992] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.701999] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.702006] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.702013] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.702019] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.702026] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.702033] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.702039] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.702046] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.702053] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.702060] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.702066] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.702073] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.702080] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.702086] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.702093] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.702100] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.702106] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.702113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.702120] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.702127] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.702133] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.702160] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.702167] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.702173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.702180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.702187] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.702191] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 3.702219] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 3.702518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.702538] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.702817] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.702840] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.702858] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.702876] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 3.705524] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.705544] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 3.705839] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.705857] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.706135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.706154] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.706159] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 3.706163] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 3.706183] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 3.706193] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 3.706203] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no [ 3.706211] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no [ 3.706219] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes [ 3.706226] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no [ 3.706234] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes [ 3.706241] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no [ 3.706248] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no [ 3.706256] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 3.706264] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 [ 3.706271] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 [ 3.706277] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.706284] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 [ 3.706291] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 [ 3.706298] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.706304] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config [ 3.706313] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) [ 3.706320] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) [ 3.706338] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 3.706348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000092327a12 state to 00000000fc0cb429 [ 3.706357] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ca6e974 state to 00000000fc0cb429 [ 3.706365] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000aea8f107 state to 00000000fc0cb429 [ 3.706373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000aea8f107 [ 3.706382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000e4b6e50 state to 00000000fc0cb429 [ 3.706389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000e4b6e50 [ 3.706397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000098d0b1b state to 00000000fc0cb429 [ 3.706405] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000374f38f state to 00000000fc0cb429 [ 3.706413] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ba689a33 state to 00000000fc0cb429 [ 3.706420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ba689a33 [ 3.706428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ae016691 state to 00000000fc0cb429 [ 3.706435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ae016691 [ 3.706443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002012d358 state to 00000000fc0cb429 [ 3.706451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000eb42cb6c state to 00000000fc0cb429 [ 3.706458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000eb42cb6c [ 3.706466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac043c4a state to 00000000fc0cb429 [ 3.706473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac043c4a [ 3.706481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000092327a12 [ 3.706489] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 3.706497] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000005b4f258 state to 00000000fc0cb429 [ 3.706505] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [NOCRTC] [ 3.706513] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [CRTC:51:pipe A] [ 3.706520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000098d0b1b [ 3.706528] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 3.706536] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ee6ef05 state to 00000000fc0cb429 [ 3.706543] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [NOCRTC] [ 3.706551] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [CRTC:72:pipe B] [ 3.706559] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 [ 3.706566] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 [ 3.706573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000002012d358 [ 3.706581] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 3.706589] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 3.706597] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.706601] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.706605] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.706609] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.706636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.706659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.706675] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 3.713140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 3.713154] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 3.713179] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] [ 3.713188] [drm:drm_client_modeset_probe [drm]] [ 3.713202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 3.713233] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 3.713246] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 3.713251] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 3.713275] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 3.713582] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.713608] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.713894] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 3.713919] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.713941] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.713961] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 3.716582] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 3.716601] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 3.716897] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.716914] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 3.717193] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 3.717219] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.717223] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 3.717228] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 3.717250] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 3.717659] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.718014] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.719533] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.719553] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.719572] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.719697] sr 2:0:0:0: [sr0] scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray [ 3.719699] cdrom: Uniform CD-ROM driver Revision: 3.20 [ 3.719853] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 3.725765] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.726292] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.726302] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.726310] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.726317] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.726526] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.726533] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.726540] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.726547] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.726554] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726561] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726574] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726581] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726587] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726594] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.726600] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.726606] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 3.726613] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.726620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.726626] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.726633] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.726639] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.726646] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.726652] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.726659] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.726666] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.726672] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.726679] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.726685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.726692] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.726698] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.726705] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.726711] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.726718] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.726724] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.726731] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.726737] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.726744] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.726750] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.726757] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.726763] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.726770] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.726776] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.726783] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.726789] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.726796] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726802] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726809] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726815] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.726822] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.726828] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.726835] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.726841] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.726848] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.726852] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 3.726874] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 3.727171] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.727191] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.727470] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 3.727492] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.727511] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.727530] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 3.730191] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 3.730209] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 3.730502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.730519] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 3.730796] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 3.730814] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.730818] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 3.730822] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 3.730841] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 3.731245] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 3.731600] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 3.733115] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 3.733135] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 3.733153] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 3.733432] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 3.735981] sr 2:0:0:0: Attached scsi CD-ROM sr0 [ 3.739342] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 3.739867] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.739875] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 3.739883] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 3.739889] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 3.740070] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.740077] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.740085] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 3.740092] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 3.740099] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740106] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740119] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740133] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 3.740146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 3.740152] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 3.740159] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 3.740166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 3.740173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 3.740180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 3.740186] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 3.740193] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.740200] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 3.740206] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.740213] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 3.740220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 3.740227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 3.740233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.740240] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 3.740247] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 3.740254] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 3.740260] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.740267] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 3.740274] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 3.740280] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.740287] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.740294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 3.740301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 3.740307] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 3.740314] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 3.740321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 3.740328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 3.740334] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.740341] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 3.740348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740361] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 3.740375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 3.740381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 3.740388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.740395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 3.740401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 3.740405] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 3.740428] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 3.740726] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.740746] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.741027] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 3.741049] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.741068] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 3.741086] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 3.743693] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 3.743712] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 3.744007] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.744024] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 3.744301] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 3.744320] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 3.744324] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 3.744328] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 3.744346] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 3.744356] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 3.744365] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no [ 3.744373] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no [ 3.744380] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes [ 3.744387] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no [ 3.744394] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes [ 3.744400] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no [ 3.744407] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no [ 3.744415] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration [ 3.744422] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 [ 3.744428] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 [ 3.744434] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.744441] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 [ 3.744447] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 [ 3.744453] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 [ 3.744460] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config [ 3.744468] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) [ 3.744475] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) [ 3.744485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 [ 3.744494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062abf8d7 state to 00000000fc0cb429 [ 3.744503] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 [ 3.744510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059907653 state to 00000000fc0cb429 [ 3.744518] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059907653 [ 3.744526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002b958a81 state to 00000000fc0cb429 [ 3.744533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002b958a81 [ 3.744541] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dff2ac2f state to 00000000fc0cb429 [ 3.744548] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 [ 3.744557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005ed6e442 state to 00000000fc0cb429 [ 3.744564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005ed6e442 [ 3.744571] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006d13a46c state to 00000000fc0cb429 [ 3.744578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006d13a46c [ 3.744586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000dc86a4bd state to 00000000fc0cb429 [ 3.744597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000002f6b4ed state to 00000000fc0cb429 [ 3.744604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000002f6b4ed [ 3.744611] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000009db6fe1 state to 00000000fc0cb429 [ 3.744618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000009db6fe1 [ 3.744626] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000062abf8d7 [ 3.744633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 [ 3.744641] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 00000000fc0cb429 [ 3.744648] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] [ 3.744656] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] [ 3.744662] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000dff2ac2f [ 3.744670] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 [ 3.744677] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000057c6efeb state to 00000000fc0cb429 [ 3.744685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [NOCRTC] [ 3.744692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [CRTC:72:pipe B] [ 3.744706] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000422ac28a state to 00000000fc0cb429 [ 3.744713] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000422ac28a [ 3.744719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000dc86a4bd [ 3.744727] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 [ 3.744734] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 [ 3.744741] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 3.744746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 3.744749] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 3.744753] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 3.744786] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 3.744808] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 3.744823] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 [ 3.757962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 [ 3.758007] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 [ 3.760005] usb 1-11.3: new full-speed USB device number 9 using xhci_hcd [ 3.863221] usb 1-11.3: New USB device found, idVendor=056a, idProduct=0392, bcdDevice= 1.07 [ 3.863226] usb 1-11.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 3.863230] usb 1-11.3: Product: Wacom Intuos Pro S [ 3.863232] usb 1-11.3: Manufacturer: Wacom Co.,Ltd. [ 3.863235] usb 1-11.3: SerialNumber: 9IQ0111006826 [ 3.875163] hid-generic 0003:056A:0392.0005: hiddev1,hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 [ 3.878106] hid-generic 0003:056A:0392.0006: hiddev2,hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 [ 3.901638] input: Wacom Intuos Pro S Pen as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input8 [ 3.901775] input: Wacom Intuos Pro S Pad as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input10 [ 3.901851] wacom 0003:056A:0392.0005: hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 [ 3.902858] input: Wacom Intuos Pro S Finger as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.1/0003:056A:0392.0006/input/input12 [ 3.902979] wacom 0003:056A:0392.0006: hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 [ 3.943873] usb 1-12.1: new high-speed USB device number 10 using xhci_hcd [ 4.045574] usb 1-12.1: New USB device found, idVendor=16d0, idProduct=071a, bcdDevice= 1.96 [ 4.045583] usb 1-12.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.045586] usb 1-12.1: Product: Combo384 Amanero [ 4.045589] usb 1-12.1: Manufacturer: Amanero Technologies [ 4.045592] usb 1-12.1: SerialNumber: 413-001 [ 4.136728] process '/usr/bin/fstype' started with executable stack [ 4.149281] PM: Image not found (code -22) [ 4.267305] SGI XFS with ACLs, security attributes, realtime, quota, no debug enabled [ 4.270230] XFS (sda1): Mounting V5 Filesystem [ 4.283488] XFS (sda1): Ending clean mount [ 4.381935] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist. [ 4.466746] systemd[1]: Inserted module 'autofs4' [ 4.493716] systemd[1]: systemd 245.5-3 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=hybrid) [ 4.512168] systemd[1]: Detected architecture x86-64. [ 4.541853] systemd[1]: Set hostname to <hirez>. [ 4.676468] systemd[1]: /lib/systemd/system/dbus.socket:5: ListenStream= references a path below legacy directory /var/run/, updating /var/run/dbus/system_bus_socket ? /run/dbus/system_bus_socket; please update the unit file accordingly. [ 4.732617] systemd[1]: Created slice system-getty.slice. [ 4.732826] systemd[1]: Created slice system-modprobe.slice. [ 4.733006] systemd[1]: Created slice system-postfix.slice. [ 4.733241] systemd[1]: Created slice User and Session Slice. [ 4.733308] systemd[1]: Started Forward Password Requests to Wall Directory Watch. [ 4.733466] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. [ 4.733508] systemd[1]: Reached target User and Group Name Lookups. [ 4.733523] systemd[1]: Reached target Slices. [ 4.736775] systemd[1]: Listening on RPCbind Server Activation Socket. [ 4.737370] systemd[1]: Listening on Syslog Socket. [ 4.737434] systemd[1]: Listening on initctl Compatibility Named Pipe. [ 4.737838] systemd[1]: Listening on Journal Audit Socket. [ 4.737907] systemd[1]: Listening on Journal Socket (/dev/log). [ 4.737992] systemd[1]: Listening on Journal Socket. [ 4.738085] systemd[1]: Listening on udev Control Socket. [ 4.738133] systemd[1]: Listening on udev Kernel Socket. [ 4.738771] systemd[1]: Mounting Huge Pages File System... [ 4.739449] systemd[1]: Mounting POSIX Message Queue File System... [ 4.740120] systemd[1]: Mounting RPC Pipe File System... [ 4.741130] systemd[1]: Mounting Kernel Debug File System... [ 4.742089] systemd[1]: Mounting Kernel Trace File System... [ 4.742177] systemd[1]: Condition check resulted in Kernel Module supporting RPCSEC_GSS being skipped. [ 4.743057] systemd[1]: Starting Wait for network to be configured by ifupdown... [ 4.744088] systemd[1]: Starting Set the console keyboard layout... [ 4.744753] systemd[1]: Starting Create list of static device nodes for the current kernel... [ 4.744784] systemd[1]: Condition check resulted in Load Kernel Module drm being skipped. [ 4.745130] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped. [ 4.746296] systemd[1]: Starting Journal Service... [ 4.748422] systemd[1]: Starting Load Kernel Modules... [ 4.749115] systemd[1]: Starting Remount Root and Kernel File Systems... [ 4.749944] systemd[1]: Starting udev Coldplug all Devices... [ 4.751645] systemd[1]: Mounted Huge Pages File System. [ 4.751832] systemd[1]: Mounted POSIX Message Queue File System. [ 4.751979] systemd[1]: Mounted Kernel Debug File System. [ 4.752111] systemd[1]: Mounted Kernel Trace File System. [ 4.752618] systemd[1]: Finished Wait for network to be configured by ifupdown. [ 4.753157] systemd[1]: Finished Create list of static device nodes for the current kernel. [ 4.761518] lp: driver loaded but no devices found [ 4.763837] ppdev: user-space parallel port driver [ 4.771880] systemd[1]: Finished Load Kernel Modules. [ 4.772256] systemd[1]: Condition check resulted in FUSE Control File System being skipped. [ 4.772353] systemd[1]: Condition check resulted in Kernel Configuration File System being skipped. [ 4.772373] xfs filesystem being remounted at / supports timestamps until 2038 (0x7fffffff) [ 4.773269] systemd[1]: Starting Apply Kernel Variables... [ 4.773401] RPC: Registered named UNIX socket transport module. [ 4.773402] RPC: Registered udp transport module. [ 4.773402] RPC: Registered tcp transport module. [ 4.773403] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 4.775228] systemd[1]: Mounted RPC Pipe File System. [ 4.775747] systemd[1]: Finished Remount Root and Kernel File Systems. [ 4.776247] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped. [ 4.776285] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped. [ 4.777070] systemd[1]: Starting Load/Save Random Seed... [ 4.777955] systemd[1]: Starting Create System Users... [ 4.780674] systemd[1]: Finished Apply Kernel Variables. [ 4.793614] systemd[1]: Finished Load/Save Random Seed. [ 4.796908] systemd[1]: Finished Create System Users. [ 4.797598] systemd[1]: Starting Create Static Device Nodes in /dev... [ 4.802675] systemd[1]: Finished Set the console keyboard layout. [ 4.808929] systemd[1]: Finished Create Static Device Nodes in /dev. [ 4.809034] systemd[1]: Reached target Local File Systems (Pre). [ 4.809044] systemd[1]: Reached target Local File Systems. [ 4.809658] systemd[1]: Starting Load AppArmor profiles... [ 4.810278] systemd[1]: Starting Enable support for additional executable binary formats... [ 4.811095] systemd[1]: Starting Set console font and keymap... [ 4.811940] systemd[1]: Starting Preprocess NFS configuration... [ 4.812829] systemd[1]: Starting Tell Plymouth To Write Out Runtime Data... [ 4.812857] systemd[1]: Condition check resulted in Store a System Token in an EFI Variable being skipped. [ 4.812897] systemd[1]: Condition check resulted in Commit a transient machine-id on disk being skipped. [ 4.813667] systemd[1]: Starting udev Kernel Device Manager... [ 4.813843] systemd[1]: proc-sys-fs-binfmt_misc.automount: Got automount request for /proc/sys/fs/binfmt_misc, triggered by 350 (update-binfmts) [ 4.814689] systemd[1]: Mounting Arbitrary Executable File Formats File System... [ 4.815333] systemd[1]: Finished Set console font and keymap. [ 4.815579] systemd[1]: nfs-config.service: Succeeded. [ 4.815929] systemd[1]: Finished Preprocess NFS configuration. [ 4.816074] systemd[1]: Condition check resulted in RPC security service for NFS client and server being skipped. [ 4.816102] systemd[1]: Condition check resulted in RPC security service for NFS server being skipped. [ 4.816118] systemd[1]: Reached target NFS client services. [ 4.820384] systemd[1]: Mounted Arbitrary Executable File Formats File System. [ 4.824947] systemd[1]: Finished Enable support for additional executable binary formats. [ 4.825708] systemd[1]: Received SIGRTMIN+20 from PID 243 (plymouthd). [ 4.828330] systemd[1]: Finished Tell Plymouth To Write Out Runtime Data. [ 4.840263] audit: type=1400 audit(1591264850.416:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="firejail-default" pid=368 comm="apparmor_parser" [ 4.840263] systemd[1]: Finished udev Coldplug all Devices. [ 4.841296] systemd[1]: Starting Helper to synchronize boot up for ifupdown... [ 4.841705] audit: type=1400 audit(1591264850.416:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-senddoc" pid=372 comm="apparmor_parser" [ 4.843324] audit: type=1400 audit(1591264850.416:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="postgresql_akonadi" pid=370 comm="apparmor_parser" [ 4.843644] audit: type=1400 audit(1591264850.416:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-oopslash" pid=371 comm="apparmor_parser" [ 4.843772] systemd[1]: Finished Helper to synchronize boot up for ifupdown. [ 4.843977] audit: type=1400 audit(1591264850.420:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=369 comm="apparmor_parser" [ 4.843989] audit: type=1400 audit(1591264850.420:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=369 comm="apparmor_parser" [ 4.843990] audit: type=1400 audit(1591264850.420:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=369 comm="apparmor_parser" [ 4.844372] audit: type=1400 audit(1591264850.420:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-xpdfimport" pid=375 comm="apparmor_parser" [ 4.845764] audit: type=1400 audit(1591264850.420:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cups-browsed" pid=365 comm="apparmor_parser" [ 4.911836] systemd[1]: Finished Load AppArmor profiles. [ 4.912675] systemd[1]: Starting Raise network interfaces... [ 4.952184] systemd[1]: Finished Raise network interfaces. [ 4.954977] systemd[1]: Started udev Kernel Device Manager. [ 4.955663] systemd[1]: Starting Show Plymouth Boot Screen... [ 4.981642] systemd[1]: Started Show Plymouth Boot Screen. [ 4.981868] systemd[1]: Condition check resulted in Dispatch Password Requests to Console Directory Watch being skipped. [ 4.981983] systemd[1]: Started Forward Password Requests to Plymouth Directory Watch. [ 4.982014] systemd[1]: Reached target Local Encrypted Volumes. [ 5.003794] IPMI message handler: version 39.2 [ 5.007344] ipmi device interface [ 5.014857] ipmi_si: IPMI System Interface driver [ 5.014872] ipmi_si dmi-ipmi-si.0: ipmi_platform: probing via SMBIOS [ 5.014874] ipmi_platform: ipmi_si: SMBIOS: io 0xca2 regsize 1 spacing 1 irq 0 [ 5.014875] ipmi_si: Adding SMBIOS-specified kcs state machine [ 5.015655] ipmi_si IPI0001:00: ipmi_platform: probing via ACPI [ 5.015806] ipmi_si IPI0001:00: ipmi_platform: [io 0x0ca4] regsize 1 spacing 1 irq 0 [ 5.015807] ipmi_si: Adding ACPI-specified kcs state machine [ 5.015884] ipmi_si: Trying SMBIOS-specified kcs state machine at i/o address 0xca2, slave address 0x20, irq 0 [ 5.088154] EDAC MC0: Giving out device to module ie31200_edac controller IE31200: DEV 0000:00:00.0 (POLLED) [ 5.089876] sd 1:0:0:0: Attached scsi generic sg0 type 0 [ 5.090024] sr 2:0:0:0: Attached scsi generic sg1 type 5 [ 5.090192] sd 4:0:0:0: Attached scsi generic sg2 type 0 [ 5.090241] sd 4:0:0:1: Attached scsi generic sg3 type 0 [ 5.090266] sd 4:0:0:2: Attached scsi generic sg4 type 0 [ 5.090320] sd 4:0:0:3: Attached scsi generic sg5 type 0 [ 5.090373] sd 4:0:0:4: Attached scsi generic sg6 type 0 [ 5.091437] iTCO_vendor_support: vendor-support=0 [ 5.092650] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11 [ 5.092707] mei_me 0000:00:16.0: enabling device (0000 -> 0002) [ 5.092778] input: Microsoft X-Box 360 pad as /devices/pci0000:00/0000:00:14.0/usb1/1-14/1-14:1.0/input/input14 [ 5.092783] iTCO_wdt: unable to reset NO_REBOOT flag, device disabled by hardware/BIOS [ 5.092866] usbcore: registered new interface driver xpad [ 5.116588] mc: Linux media interface: v0.10 [ 5.141208] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer [ 5.141209] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules [ 5.141210] RAPL PMU: hw unit of domain package 2^-14 Joules [ 5.141211] RAPL PMU: hw unit of domain dram 2^-14 Joules [ 5.141211] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules [ 5.150008] systemd[1]: Found device Samsung_SSD_850_PRO_512GB 5. [ 5.159157] systemd[1]: Activating swap /dev/disk/by-uuid/602df9e6-40fb-41aa-b0df-96a9088df593... [ 5.186454] systemd[1]: Started Journal Service. [ 5.189868] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) [ 5.192407] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. [ 5.192408] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 2, val = -32767/0/1 [ 5.193209] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ef6f2003 [ 5.193220] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ea16da3d state to 00000000ef6f2003 [ 5.193230] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000088487cf7 state to 00000000ef6f2003 [ 5.193238] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028b01bfa state to 00000000ef6f2003 [ 5.193247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028b01bfa [ 5.193255] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008a2f3e8a state to 00000000ef6f2003 [ 5.193264] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008a2f3e8a [ 5.193294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000eb2a745f state to 00000000ef6f2003 [ 5.193315] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000faa616df state to 00000000ef6f2003 [ 5.193324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cbb299c1 state to 00000000ef6f2003 [ 5.193332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cbb299c1 [ 5.193353] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000079bcaa7c state to 00000000ef6f2003 [ 5.193361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000079bcaa7c [ 5.193369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000fb71ed5 state to 00000000ef6f2003 [ 5.193376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9cfd0f1 state to 00000000ef6f2003 [ 5.193384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9cfd0f1 [ 5.193393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007908e825 state to 00000000ef6f2003 [ 5.193401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007908e825 [ 5.193414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000ea16da3d [ 5.193422] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ef6f2003 [ 5.193431] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000018b0a306 state to 00000000ef6f2003 [ 5.193440] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [NOCRTC] [ 5.193447] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [CRTC:51:pipe A] [ 5.193463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000eb2a745f [ 5.193472] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ef6f2003 [ 5.193481] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000008dfecd46 state to 00000000ef6f2003 [ 5.193488] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [NOCRTC] [ 5.193496] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [CRTC:72:pipe B] [ 5.193507] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000fd253e01 state to 00000000ef6f2003 [ 5.193515] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000fd253e01 [ 5.193522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000fb71ed5 [ 5.193530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ef6f2003 [ 5.193538] [drm:drm_atomic_check_only [drm]] checking 00000000ef6f2003 [ 5.193549] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 5.193553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 5.193557] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 5.193561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 5.193595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 5.193618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 5.193635] [drm:drm_atomic_commit [drm]] committing 00000000ef6f2003 [ 5.196839] cryptd: max_cpu_qlen set to 1000 [ 5.196865] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. [ 5.196867] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 1, val = -32767/0/1 [ 5.197058] usbcore: registered new interface driver snd-usb-audio [ 5.208924] Adding 33442812k swap on /dev/sda5. Priority:-2 extents:1 across:33442812k SSFS [ 5.209024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ef6f2003 [ 5.209049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ef6f2003 [ 5.214980] systemd-journald[324]: Received client request to flush runtime journal. [ 5.232082] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9f8f61b [ 5.232093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d30af224 state to 00000000f9f8f61b [ 5.232103] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 00000000f9f8f61b [ 5.232112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a3a0e390 state to 00000000f9f8f61b [ 5.232121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a3a0e390 [ 5.232129] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000050c6aee state to 00000000f9f8f61b [ 5.232138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000050c6aee [ 5.232151] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000330ef6e state to 00000000f9f8f61b [ 5.232159] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a16f6bc3 state to 00000000f9f8f61b [ 5.232166] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bb4d02e2 state to 00000000f9f8f61b [ 5.232174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bb4d02e2 [ 5.232182] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a99d3259 state to 00000000f9f8f61b [ 5.232192] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a99d3259 [ 5.232200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c8e13b43 state to 00000000f9f8f61b [ 5.232207] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ece028f4 state to 00000000f9f8f61b [ 5.232215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ece028f4 [ 5.232222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000c21cbeb state to 00000000f9f8f61b [ 5.232232] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000c21cbeb [ 5.232240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000d30af224 [ 5.232250] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f9f8f61b [ 5.232264] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004431baab state to 00000000f9f8f61b [ 5.232274] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [NOCRTC] [ 5.232282] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [CRTC:51:pipe A] [ 5.232289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000330ef6e [ 5.232297] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f9f8f61b [ 5.232305] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000641aa27e state to 00000000f9f8f61b [ 5.232314] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [NOCRTC] [ 5.232322] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [CRTC:72:pipe B] [ 5.232331] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e1c94e20 state to 00000000f9f8f61b [ 5.232338] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e1c94e20 [ 5.232345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c8e13b43 [ 5.232353] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f9f8f61b [ 5.232362] [drm:drm_atomic_check_only [drm]] checking 00000000f9f8f61b [ 5.232373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 5.232377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 5.232381] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 5.232385] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 5.232421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 5.232445] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 5.232472] [drm:drm_atomic_commit [drm]] committing 00000000f9f8f61b [ 5.246294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9f8f61b [ 5.246308] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9f8f61b [ 5.268023] AVX2 version of gcm_enc/dec engaged. [ 5.268024] AES CTR mode by8 optimization enabled [ 5.278985] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC888-VD: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:line [ 5.278986] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 5.278987] snd_hda_codec_realtek hdaudioC0D0: hp_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: inputs: [ 5.278989] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 [ 5.293862] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 5.293885] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 5.293906] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 5.293928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 5.293948] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 5.293970] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 5.293988] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 5.295775] ipmi_si dmi-ipmi-si.0: The BMC does not support clearing the recv irq bit, compensating, but the BMC needs to be fixed. [ 5.312401] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1f.3/sound/card0/input15 [ 5.312465] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input16 [ 5.312514] input: HDA Intel PCH Front Line Out as /devices/pci0000:00/0000:00:1f.3/sound/card0/input17 [ 5.312560] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input18 [ 5.312604] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input19 [ 5.312651] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input20 [ 5.312690] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input21 [ 5.312737] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input22 [ 5.388997] ipmi_si dmi-ipmi-si.0: IPMI message handler: Found new BMC (man_id: 0x002a7c, prod_id: 0x0888, dev_id: 0x20) [ 5.430745] ipmi_si dmi-ipmi-si.0: IPMI kcs interface initialized [ 5.442072] ipmi_ssif: IPMI SSIF Interface driver [ 5.690895] intel_rapl_common: Found RAPL domain package [ 5.690897] intel_rapl_common: Found RAPL domain core [ 5.690899] intel_rapl_common: Found RAPL domain uncore [ 5.690900] intel_rapl_common: Found RAPL domain dram [ 6.053475] alg: No test for fips(ansi_cprng) (fips_ansi_cprng) [ 6.145869] Bluetooth: Core ver 2.22 [ 6.145879] NET: Registered protocol family 31 [ 6.145880] Bluetooth: HCI device and connection manager initialized [ 6.145883] Bluetooth: HCI socket layer initialized [ 6.145884] Bluetooth: L2CAP socket layer initialized [ 6.145886] Bluetooth: SCO socket layer initialized [ 6.256918] kauditd_printk_skb: 16 callbacks suppressed [ 6.256919] audit: type=1400 audit(1591264851.832:27): apparmor="DENIED" operation="capable" profile="/usr/sbin/cups-browsed" pid=724 comm="cups-browsed" capability=23 capname="sys_nice" [ 10.310500] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx [ 10.310581] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready [ 14.126521] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx [ 14.914834] FS-Cache: Loaded [ 14.953494] FS-Cache: Netfs 'nfs' registered for caching [ 14.956761] Key type dns_resolver registered [ 15.082476] NFS: Registering the id_resolver key type [ 15.082496] Key type id_resolver registered [ 15.082497] Key type id_legacy registered [ 15.296934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d166d111 [ 15.296974] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008bf5b86d state to 00000000d166d111 [ 15.297001] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 00000000bd8bd551 state to 00000000d166d111 [ 15.297024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000835fb348 state to 00000000d166d111 [ 15.297051] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000835fb348 [ 15.297077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008bf5b86d [ 15.297103] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d166d111 [ 15.297127] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000f4bb3954 state to 00000000d166d111 [ 15.297151] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [NOCRTC] [ 15.297173] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [CRTC:33:crtc-0] [ 15.297196] [drm:drm_atomic_check_only [drm]] checking 00000000d166d111 [ 15.297215] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 15.297228] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 15.297255] [drm:drm_atomic_commit [drm]] committing 00000000d166d111 [ 15.297321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d166d111 [ 15.297345] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d166d111 [ 15.297375] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 [ 15.297451] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004b92744e [ 15.297477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 000000004b92744e [ 15.297500] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed9cb119 state to 000000004b92744e [ 15.297522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000046234f6 state to 000000004b92744e [ 15.297547] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000046234f6 [ 15.297570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a35c929d state to 000000004b92744e [ 15.297594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a35c929d [ 15.297618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009d539ce0 state to 000000004b92744e [ 15.297640] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed29f6c9 state to 000000004b92744e [ 15.297662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 000000004b92744e [ 15.297685] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f [ 15.297707] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 000000004b92744e [ 15.297730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe [ 15.297753] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000e89c017 state to 000000004b92744e [ 15.297774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000029001d73 state to 000000004b92744e [ 15.297797] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000029001d73 [ 15.297820] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000708b01e5 state to 000000004b92744e [ 15.297853] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000708b01e5 [ 15.297871] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f3527d8e [ 15.297888] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000004b92744e [ 15.297908] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000efae517b state to 000000004b92744e [ 15.297927] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [NOCRTC] [ 15.297944] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [CRTC:51:pipe A] [ 15.297961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009d539ce0 [ 15.297978] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000004b92744e [ 15.297996] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000033858fd0 state to 000000004b92744e [ 15.298013] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [NOCRTC] [ 15.298030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [CRTC:72:pipe B] [ 15.298048] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d397071c state to 000000004b92744e [ 15.298065] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d397071c [ 15.298081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000e89c017 [ 15.298098] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000004b92744e [ 15.298115] [drm:drm_atomic_check_only [drm]] checking 000000004b92744e [ 15.298143] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 15.298153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 15.298161] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 15.298170] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 15.298248] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 15.298299] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 15.298333] [drm:drm_atomic_commit [drm]] committing 000000004b92744e [ 15.313540] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004b92744e [ 15.313557] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004b92744e [ 15.330791] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 [ 15.330803] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000033ce3db8 [ 15.330813] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000008fdc242 state to 0000000033ce3db8 [ 15.330826] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000024c9c604 state to 0000000033ce3db8 [ 15.330836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000024c9c604 [ 15.330845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000063a0901f state to 0000000033ce3db8 [ 15.330854] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000063a0901f [ 15.330862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f9f236ad state to 0000000033ce3db8 [ 15.330870] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e1c94e20 state to 0000000033ce3db8 [ 15.330879] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001976c542 state to 0000000033ce3db8 [ 15.330887] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001976c542 [ 15.330895] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000023bce10 state to 0000000033ce3db8 [ 15.330903] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000023bce10 [ 15.330912] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d3ee8271 state to 0000000033ce3db8 [ 15.330919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000026db81c9 state to 0000000033ce3db8 [ 15.330927] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000026db81c9 [ 15.330940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003685cc7f state to 0000000033ce3db8 [ 15.330948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003685cc7f [ 15.330956] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f [ 15.330965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 [ 15.330974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009eadb78e state to 0000000033ce3db8 [ 15.330982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [NOCRTC] [ 15.330990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [CRTC:51:pipe A] [ 15.330998] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f9f236ad [ 15.331006] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 [ 15.331014] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ef54c858 state to 0000000033ce3db8 [ 15.331022] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [NOCRTC] [ 15.331030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [CRTC:72:pipe B] [ 15.331049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a16f6bc3 state to 0000000033ce3db8 [ 15.331057] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a16f6bc3 [ 15.331064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d3ee8271 [ 15.331072] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 [ 15.331080] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 [ 15.331092] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 15.331096] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 15.331100] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 15.331104] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 15.331140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 15.331173] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 15.331191] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 [ 15.346869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 [ 15.346883] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 [ 15.347242] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009bf2742d [ 15.347253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008c267a81 state to 000000009bf2742d [ 15.347264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 0000000042ba191e state to 000000009bf2742d [ 15.347275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000050ba9058 state to 000000009bf2742d [ 15.347285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000050ba9058 [ 15.347294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008c267a81 [ 15.347303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 000000009bf2742d [ 15.347311] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000002bd5700a state to 000000009bf2742d [ 15.347320] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [NOCRTC] [ 15.347328] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [CRTC:33:crtc-0] [ 15.347337] [drm:drm_atomic_check_only [drm]] checking 000000009bf2742d [ 15.347344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] [ 15.347349] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] [ 15.347359] [drm:drm_atomic_commit [drm]] committing 000000009bf2742d [ 15.347396] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009bf2742d [ 15.347405] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009bf2742d [ 15.347415] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 [ 15.358909] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 [ 15.358920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f6bb1f5 state to 0000000033ce3db8 [ 15.358931] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 0000000033ce3db8 [ 15.358939] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000002749498f state to 0000000033ce3db8 [ 15.358949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000002749498f [ 15.358961] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000006153d5d9 state to 0000000033ce3db8 [ 15.358980] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000006153d5d9 [ 15.358996] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006a05b5f7 state to 0000000033ce3db8 [ 15.359012] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d397071c state to 0000000033ce3db8 [ 15.359027] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cca4b9f0 state to 0000000033ce3db8 [ 15.359042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cca4b9f0 [ 15.359058] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009e05e90a state to 0000000033ce3db8 [ 15.359072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009e05e90a [ 15.359091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bc644261 state to 0000000033ce3db8 [ 15.359109] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000000e16ac42 state to 0000000033ce3db8 [ 15.359124] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000000e16ac42 [ 15.359140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ed4faf45 state to 0000000033ce3db8 [ 15.359155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ed4faf45 [ 15.359171] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008f6bb1f5 [ 15.359186] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 [ 15.359203] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000025aaf842 state to 0000000033ce3db8 [ 15.359223] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [NOCRTC] [ 15.359238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [CRTC:51:pipe A] [ 15.359254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006a05b5f7 [ 15.359270] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 [ 15.359285] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000a470917a state to 0000000033ce3db8 [ 15.359302] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [NOCRTC] [ 15.359323] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [CRTC:72:pipe B] [ 15.359340] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ed29f6c9 state to 0000000033ce3db8 [ 15.359358] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ed29f6c9 [ 15.359372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bc644261 [ 15.359388] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 [ 15.359403] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 [ 15.359433] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 15.359441] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 15.359449] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 15.359456] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 15.359505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 15.359557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 15.359583] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 [ 15.375008] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 [ 15.375022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 [ 15.405098] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.405480] [drm:intel_framebuffer_init [i915]] No Y tiling for legacy addfb [ 15.405515] [drm:drm_internal_framebuffer_create [drm]] could not create framebuffer [ 15.405547] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.405606] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.405820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 [ 15.405829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000053cd4a56 state to 00000000403c96a5 [ 15.405838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000053cd4a56 [ 15.405847] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 [ 15.405873] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 [ 15.405892] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 [ 15.405899] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 [ 15.405949] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 [ 15.405957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007a41a1eb state to 00000000403c96a5 [ 15.405965] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007a41a1eb [ 15.405972] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 [ 15.405980] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 [ 15.405991] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 [ 15.405998] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 [ 15.406048] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 [ 15.406055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000746efc3b state to 00000000403c96a5 [ 15.406064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000746efc3b [ 15.406071] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 [ 15.406078] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 [ 15.406089] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 [ 15.406095] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 [ 15.485516] [drm:drm_mode_addfb2 [drm]] [FB:134] [ 15.486080] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a [ 15.486117] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040560145 state to 000000005e0e4b0a [ 15.486145] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a [ 15.486179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000044e6fdf state to 000000005e0e4b0a [ 15.486215] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a [ 15.491766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a [ 15.491810] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a [ 15.491933] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a [ 15.491973] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000577ba344 state to 000000005e0e4b0a [ 15.491999] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a [ 15.492030] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c21eb74a state to 000000005e0e4b0a [ 15.492064] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a [ 15.496975] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a [ 15.497010] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a [ 16.356678] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] [ 16.356693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] [ 16.356708] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.356722] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000548ffd9d state to 000000006e858879 [ 16.356739] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e1f1c0f1 state to 000000006e858879 [ 16.356764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000548ffd9d [ 16.356783] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000e1f1c0f1 [ 16.356800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006e858879 [ 16.356811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000030b3daa1 state to 000000006e858879 [ 16.356822] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [NOCRTC] [ 16.356832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [CRTC:51:pipe A] [ 16.356859] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.356868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 16.356874] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 16.356915] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 16.356943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm [ 16.356968] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 [ 16.356988] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 [ 16.357008] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 [ 16.357022] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.375313] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.375339] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 16.375389] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] [ 16.375408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] [ 16.375426] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.375445] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000040560145 state to 000000006e858879 [ 16.375461] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c8047799 state to 000000006e858879 [ 16.375481] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 0000000040560145 [ 16.375498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 00000000c8047799 [ 16.375514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006e858879 [ 16.375531] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000679f9f9c state to 000000006e858879 [ 16.375548] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [NOCRTC] [ 16.375564] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [CRTC:72:pipe B] [ 16.375583] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.375603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 16.375612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 16.375678] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 16.375718] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm [ 16.375749] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 [ 16.375779] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 [ 16.375838] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 [ 16.375862] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.380403] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.380432] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 16.466326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.466379] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c21eb74a state to 000000006e858879 [ 16.466420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000577ba344 state to 000000006e858879 [ 16.466461] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c21eb74a to [CRTC:51:pipe A] [ 16.466499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c21eb74a [ 16.466536] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.466670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 16.466727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c8a5ea85 state to 000000006e858879 [ 16.466807] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 16.466878] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 16.466943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 16.467007] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 16.467049] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.467221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.467261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 16.467316] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 16.467354] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e1f1c0f1 state to 000000006e858879 [ 16.467390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000548ffd9d state to 000000006e858879 [ 16.467430] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000e1f1c0f1 to [CRTC:72:pipe B] [ 16.467467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1f1c0f1 [ 16.467502] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 16.467614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 [ 16.467660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002570d1d3 state to 000000006e858879 [ 16.467736] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 16.467826] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 16.467926] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 16.467996] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 16.468047] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 16.468167] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 16.468223] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 17.212714] [drm:drm_mode_addfb2 [drm]] [FB:143] [ 17.262341] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 17.262375] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 17.262413] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 17.262454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 17.262494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 17.262529] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 17.262568] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 17.309802] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 17.325138] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 17.363673] [drm:drm_mode_addfb2 [drm]] [FB:144] [ 17.389030] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 17.389043] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e83b417b state to 000000004c5d43a8 [ 17.389056] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c7c74428 state to 000000004c5d43a8 [ 17.389066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000c7c74428 [ 17.389074] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 17.389129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 17.389159] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking [ 17.389353] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 17.389363] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004440fec8 state to 00000000ad3ae327 [ 17.389375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000339eee21 state to 00000000ad3ae327 [ 17.389384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000339eee21 [ 17.389392] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 17.389436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 17.389452] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking [ 17.391197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000000e9d0b2a [ 17.391354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 17.391422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1364291 [ 17.391485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 17.397162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 17.397187] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 17.405872] [drm:drm_mode_addfb2 [drm]] [FB:145] [ 17.407506] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 17.408550] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 17.408565] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a [ 17.408580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a [ 17.408590] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 17.408600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a [ 17.408611] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000246ed832 [ 17.408621] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a [ 17.408716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 17.408748] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking [ 17.408968] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 17.408980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 00000000505d8d8e [ 17.408990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae9d6619 state to 00000000505d8d8e [ 17.409000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000ae9d6619 [ 17.409009] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 17.409053] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 17.409068] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 17.413297] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] [ 17.413439] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] [ 17.413467] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected [ 17.413503] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] [ 17.413565] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] [ 17.414011] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 17.414382] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 17.415995] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 17.416021] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 17.416045] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 17.416334] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes [ 17.422310] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 17.422857] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.422873] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 17.422882] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 17.422890] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.423105] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.423116] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.423125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.423133] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.423147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423156] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423172] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423187] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423214] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.423243] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.423259] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : [ 17.423276] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 17.423294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 17.423312] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 17.423329] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 17.423347] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 17.423364] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.423383] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.423398] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.423410] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.423424] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 17.423439] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 17.423448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.423456] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.423464] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 17.423473] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 17.423481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.423493] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.423500] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 17.423508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.423515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.423523] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.423530] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 17.423538] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 17.423545] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 17.423553] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 17.423560] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 17.423568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.423575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.423582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423590] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423597] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423605] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.423612] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 17.423620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 17.423627] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.423635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.423642] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 17.423723] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] [ 17.423770] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] [ 17.424191] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 [ 17.424555] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 [ 17.425122] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a [ 17.425141] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a [ 17.426094] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 [ 17.426117] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 17.426138] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 17.426420] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes [ 17.430296] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 17.430309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 17.432359] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support [ 17.432885] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.432895] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q [ 17.432902] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 [ 17.432909] [drm:drm_add_display_info [drm]] non_desktop set to 0 [ 17.433097] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.433104] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.433112] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a [ 17.433119] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL [ 17.433126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433132] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433139] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433159] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a [ 17.433173] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL [ 17.433181] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : [ 17.433188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 [ 17.433195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 [ 17.433201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 [ 17.433208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 [ 17.433215] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 [ 17.433221] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.433228] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 [ 17.433235] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.433241] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 [ 17.433248] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 [ 17.433255] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 [ 17.433261] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.433268] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 [ 17.433275] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 [ 17.433282] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 [ 17.433288] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.433295] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 [ 17.433301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 [ 17.433308] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.433315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.433321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 [ 17.433328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 [ 17.433335] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 [ 17.433342] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 17.433348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 [ 17.433355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 17.433362] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.433368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa [ 17.433375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa [ 17.433401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa [ 17.433408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 17.433414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.433421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa [ 17.433428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 17.433471] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] [ 17.433509] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] [ 17.433520] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected [ 17.433527] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] [ 17.433550] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] [ 17.433849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 17.433869] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 17.434149] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [ 17.434171] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 17.434191] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 17.434211] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 [ 17.436907] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb [ 17.436928] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 [ 17.437223] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 17.437240] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry [ 17.437518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [ 17.437537] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 17.437542] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected [ 17.437550] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] [ 17.437568] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] [ 17.437863] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 17.437881] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 17.438159] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) [ 17.438181] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 17.438199] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 17.438217] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 [ 17.441061] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc [ 17.441079] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 [ 17.441325] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 17.441343] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry [ 17.441621] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) [ 17.441640] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 17.441644] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected [ 17.441651] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] [ 17.441669] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] [ 17.441962] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 17.441979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 17.442257] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) [ 17.442279] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 17.442296] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging [ 17.442313] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 [ 17.445210] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd [ 17.445228] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 [ 17.445474] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 17.445491] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry [ 17.445708] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) [ 17.445727] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) [ 17.445731] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected [ 19.033461] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 19.033498] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 0000000014564192 [ 19.033528] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003a6df13b state to 0000000014564192 [ 19.033539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000003a6df13b [ 19.033550] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 19.033613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 19.033632] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 19.033658] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 19.033668] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000cb785d4f [ 19.033699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000cb785d4f [ 19.033708] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005752a175 [ 19.033715] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 19.033841] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 19.033872] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 19.041962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 19.041981] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 19.047276] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 19.047303] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 20.006109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000009e366e46 [ 20.006141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.006159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004fa5331c [ 20.006182] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.016139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.016171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.016190] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.016223] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.026083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.026110] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.026125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.026148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.036073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.036098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.036113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.036136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.046072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.046097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.046112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.046135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.056072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.056097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.056112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.056135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.066083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.066108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.066123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.066146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.076072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.076096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.076111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.076134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.096072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.096097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.096112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.096135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.104071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.104096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.104110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.104134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.114071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.114096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.114111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.114134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.124071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.124097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.124111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.124135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.134070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.134095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.134109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.134133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.144072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.144097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.144112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.144136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.154070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.154095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.154110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.154133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.164071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.164095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.164110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.164133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.174076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.174101] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.174115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.174139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.184071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.184095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.184110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.184133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.194072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.194096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.194111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.194134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.204074] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.204099] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.204114] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.204138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.214071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.214095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.214110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.214133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.234073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.234098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.234112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.234135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.274070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.274096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.274111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.274135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.314088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.314124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.314142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.314166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.334077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.334104] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.334119] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.334142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.354068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.354093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.354108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.354130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.376068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 [ 20.376093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.376108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 [ 20.376131] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.394073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 [ 20.394098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.394113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 [ 20.394135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.416078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 [ 20.416114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.416129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 [ 20.416152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.422661] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 [ 20.422673] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000017b31376 state to 00000000c58cae11 [ 20.422683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000009d80489d state to 00000000c58cae11 [ 20.422695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000009d80489d [ 20.422710] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 [ 20.422856] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.422898] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking [ 20.422943] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 [ 20.422952] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c88e1744 state to 000000003fe34687 [ 20.422963] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a3a0e390 state to 000000003fe34687 [ 20.422972] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000a3a0e390 [ 20.422979] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 [ 20.423027] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.423038] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking [ 20.442150] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 [ 20.442172] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 [ 20.444199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 [ 20.444330] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.444367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 [ 20.444407] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.447302] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 [ 20.447322] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 [ 20.447342] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c [ 20.447364] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005a9a925a state to 0000000072b4047c [ 20.447382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000072b4047c [ 20.447401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000000f06e049 [ 20.447415] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c [ 20.447562] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.447597] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking [ 20.447635] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f12def7f [ 20.447648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000019eb48a0 state to 00000000f12def7f [ 20.447661] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000f12def7f [ 20.447672] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 [ 20.447682] [drm:drm_atomic_check_only [drm]] checking 00000000f12def7f [ 20.447804] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.447847] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f12def7f nonblocking [ 20.458776] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c [ 20.458805] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c [ 20.464009] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f12def7f [ 20.464033] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c [ 20.464062] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f12def7f [ 20.464080] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d5af1617 state to 0000000072b4047c [ 20.464097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008416fa19 state to 0000000072b4047c [ 20.464113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000008416fa19 [ 20.464129] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c [ 20.464285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.464318] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking [ 20.464369] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 20.464382] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 00000000cb785d4f [ 20.464393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac1a10e7 state to 00000000cb785d4f [ 20.464405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000ac1a10e7 [ 20.464417] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 20.464521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.464539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 20.475453] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c [ 20.475483] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c [ 20.476153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 [ 20.476220] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.476244] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 [ 20.476294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.480583] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 20.480602] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 20.480623] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 20.480648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ff2d6d95 state to 0000000014564192 [ 20.480667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ae9d6619 state to 0000000014564192 [ 20.480684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000ae9d6619 [ 20.480699] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 20.480847] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.480875] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 20.480904] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 20.480917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000505d8d8e [ 20.480932] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003a6df13b state to 00000000505d8d8e [ 20.480944] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003a6df13b [ 20.480955] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 20.481001] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.481025] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 20.492049] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 20.492073] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 20.497297] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 20.497326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a [ 20.497344] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 20.497358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a [ 20.497371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008112a9e3 state to 00000000ae0bb06a [ 20.497384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000008112a9e3 [ 20.497397] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a [ 20.497510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.497533] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking [ 20.497566] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff [ 20.497580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 0000000094adecff [ 20.497593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 0000000094adecff [ 20.497606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 [ 20.497616] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff [ 20.497695] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.497714] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking [ 20.506275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000010080940 [ 20.506427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.506500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000002603cbe2 [ 20.506557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.508755] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a [ 20.508773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a [ 20.513913] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff [ 20.513934] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff [ 20.513955] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a [ 20.513980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000ae0bb06a [ 20.513997] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a [ 20.514015] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000246ed832 [ 20.514028] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a [ 20.514142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.514173] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking [ 20.514201] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 20.514212] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000505d8d8e [ 20.514223] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000638906d4 state to 00000000505d8d8e [ 20.514235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000638906d4 [ 20.514247] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 20.514285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.514301] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 20.525405] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a [ 20.525425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a [ 20.530631] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 20.530656] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 20.530680] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 0000000014564192 [ 20.530693] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 20.530711] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000014564192 [ 20.530728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000000f06e049 [ 20.530743] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 20.530859] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.530884] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 20.530917] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 20.530930] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000cb785d4f [ 20.530941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008416fa19 state to 00000000cb785d4f [ 20.530953] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000008416fa19 [ 20.530963] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 20.531011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.531031] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 20.536073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 [ 20.536114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.536134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 [ 20.536168] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.542007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 20.542022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 20.547157] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 20.547169] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 20.554047] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 [ 20.554089] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.554106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 [ 20.554133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.947422] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f09b7a6e [ 20.947449] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f1af5452 state to 00000000f09b7a6e [ 20.947459] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057d750db state to 00000000f09b7a6e [ 20.947469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000057d750db [ 20.947479] [drm:drm_atomic_check_only [drm]] checking 00000000f09b7a6e [ 20.947522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 20.947539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f09b7a6e nonblocking [ 20.947567] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000b295a68 [ 20.947578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000fe6b27d8 state to 000000000b295a68 [ 20.947586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3db559a state to 000000000b295a68 [ 20.947595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000f3db559a [ 20.947602] [drm:drm_atomic_check_only [drm]] checking 000000000b295a68 [ 20.947692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 20.947707] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000b295a68 nonblocking [ 20.958693] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f09b7a6e [ 20.958709] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f09b7a6e [ 20.963851] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000b295a68 [ 20.963860] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000b295a68 [ 21.143151] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 21.143174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000046499d3 [ 21.143186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b830a5b4 state to 00000000046499d3 [ 21.143195] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000b830a5b4 [ 21.143205] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 21.143259] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.143281] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 21.143326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.143336] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf [ 21.143346] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 0000000064a524bf [ 21.143356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000fe3c3ec4 [ 21.143363] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.143448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.143465] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.158722] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 21.158733] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 21.163865] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.163876] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.317441] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 [ 21.317452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000590d9307 [ 21.317460] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 00000000590d9307 [ 21.317469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000005ba888f4 [ 21.317477] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 [ 21.317520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.317539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking [ 21.317562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.317578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e2607dec state to 0000000064a524bf [ 21.317588] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 0000000064a524bf [ 21.317598] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 [ 21.317606] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.317634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.317682] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.325356] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 [ 21.325365] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 [ 21.330594] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.330605] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.453357] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 21.453368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 000000008bd3a823 [ 21.453377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 [ 21.453386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000419d8fd6 [ 21.453428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 21.453462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.453476] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 21.453492] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 21.453532] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 [ 21.453560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 [ 21.453568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c [ 21.453577] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 21.453622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.453635] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 21.463882] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 21.463892] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 21.475399] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 21.475425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 21.637365] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 21.637400] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000008bd3a823 [ 21.637411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 [ 21.637420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 [ 21.637428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 21.637463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.637477] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 21.637525] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 21.637560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 [ 21.637575] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007ae821d2 state to 00000000cff3fe76 [ 21.637586] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000007ae821d2 [ 21.637596] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 21.637625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.637639] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 21.647227] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 21.647237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 21.658762] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 21.658773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 21.781319] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 21.781359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 00000000046499d3 [ 21.781367] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 00000000046499d3 [ 21.781375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 [ 21.781383] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 21.781435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.781450] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 21.781490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.781518] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf [ 21.781529] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 0000000064a524bf [ 21.781539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 [ 21.781547] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.781576] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.781612] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.792098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 21.792109] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 21.797229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.797242] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.941164] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 21.941174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf [ 21.941206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 0000000064a524bf [ 21.941215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000010080940 [ 21.941223] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 21.941263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 21.941280] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 21.941298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 21.941307] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 [ 21.941322] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 [ 21.941337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 [ 21.941345] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 21.941375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 21.941387] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 21.958730] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 21.958740] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 21.963967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 21.963978] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 22.037360] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 22.037370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000008bd3a823 [ 22.037402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 [ 22.037414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000f4690955 [ 22.037422] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 22.037456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.037470] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 22.037494] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 22.037552] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 [ 22.037560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 [ 22.037569] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c [ 22.037583] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 22.037620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.037633] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 22.047250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 22.047261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 22.058781] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 22.058792] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 22.237345] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 22.237355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 000000008bd3a823 [ 22.237363] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 [ 22.237372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000419d8fd6 [ 22.237380] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 22.237430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.237444] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 22.237460] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 [ 22.237469] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 [ 22.237503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005ba888f4 state to 00000000cff3fe76 [ 22.237533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005ba888f4 [ 22.237550] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 [ 22.237580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.237609] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking [ 22.247260] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 [ 22.247270] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 [ 22.258795] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 22.258806] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 22.349362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 [ 22.349402] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000009f1364b2 [ 22.349412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007ae821d2 state to 000000009f1364b2 [ 22.349421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000007ae821d2 [ 22.349429] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 [ 22.349478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.349492] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking [ 22.349527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 22.349560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000046499d3 [ 22.349568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 00000000046499d3 [ 22.349578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 [ 22.349587] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 22.349614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.349638] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 22.358789] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 [ 22.358802] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 [ 22.363927] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 22.363940] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 22.429393] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf [ 22.429406] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf [ 22.429440] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 0000000064a524bf [ 22.429449] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 [ 22.429456] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf [ 22.429498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.429511] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking [ 22.429532] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 [ 22.429540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 [ 22.429547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 [ 22.429556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 [ 22.429563] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 [ 22.429597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.429616] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking [ 22.442367] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf [ 22.442417] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf [ 22.447561] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 [ 22.447614] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 [ 22.528747] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 [ 22.528805] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000009f1364b2 [ 22.528847] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000009f1364b2 [ 22.528891] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 0000000010080940 [ 22.528932] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 [ 22.529197] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 22.529272] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking [ 22.529370] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 [ 22.529413] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed110662 state to 00000000590d9307 [ 22.529452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000590d9307 [ 22.529494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c [ 22.529530] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 [ 22.529653] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 22.529710] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking [ 22.542364] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 [ 22.542414] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 [ 22.547589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 [ 22.547653] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 [ 23.009536] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000397d0932 [ 23.009568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000397d0932 [ 23.009587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 00000000397d0932 [ 23.009616] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 [ 23.009643] [drm:drm_atomic_check_only [drm]] checking 00000000397d0932 [ 23.009799] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 23.009865] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000397d0932 nonblocking [ 23.009938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 [ 23.009955] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000008bd3a823 [ 23.009972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000419d8fd6 state to 000000008bd3a823 [ 23.009988] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000419d8fd6 [ 23.010003] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 [ 23.010108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 23.010143] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking [ 23.025518] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000397d0932 [ 23.025539] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000397d0932 [ 23.030677] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 [ 23.030696] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 [ 23.071823] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000050c6aee [ 23.071864] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 23.071900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c8e13b43 [ 23.071924] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 23.392525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000e59e4cfa [ 23.392582] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 23.392624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000057d750db [ 23.392689] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 23.607003] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 23.607025] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000003ce8e850 state to 00000000ad3ae327 [ 23.607036] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000ad3ae327 [ 23.607047] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000003ce8e850 to [NOCRTC] [ 23.607056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000003ce8e850 [ 23.607065] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 23.607134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 23.607157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000233ad802 state to 00000000ad3ae327 [ 23.607179] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 23.607195] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.607210] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.607229] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.607244] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 [ 23.624682] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 23.624698] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 23.624736] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 23.624745] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000024c9c604 state to 00000000ad3ae327 [ 23.624757] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 00000000ad3ae327 [ 23.624766] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 0000000024c9c604 to [NOCRTC] [ 23.624774] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000024c9c604 [ 23.624782] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 23.624840] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 [ 23.624868] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 00000000ad3ae327 [ 23.624886] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 23.624901] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.624933] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.624947] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 23.624957] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 [ 23.624984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 23.624993] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 23.736690] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 23.736728] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 23.736759] [drm:i915_audio_component_get_eld [i915]] Not valid for port B [ 23.736792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 23.736817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C [ 23.736845] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 23.736873] [drm:i915_audio_component_get_eld [i915]] Not valid for port D [ 23.778545] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 23.800425] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 23.881716] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 [ 25.150487] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 25.150587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007ede24bf state to 000000006e858879 [ 25.150641] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000006e858879 [ 25.150670] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007ede24bf to [CRTC:51:pipe A] [ 25.150717] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007ede24bf [ 25.150772] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 25.151167] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.151358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000caa1c353 state to 000000006e858879 [ 25.151721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.152004] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.152367] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.152468] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.152618] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 25.152866] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 25.152887] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 25.152974] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 [ 25.152988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000bda1a70 state to 000000006e858879 [ 25.153008] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ea06c3a state to 000000006e858879 [ 25.153028] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 000000000bda1a70 to [CRTC:72:pipe B] [ 25.153048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:68:cursor B] state 000000000bda1a70 [ 25.153060] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 [ 25.153217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 [ 25.153252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d5e0ab1c state to 000000006e858879 [ 25.153289] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.153313] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.153339] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.153361] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.153383] [drm:drm_atomic_commit [drm]] committing 000000006e858879 [ 25.153438] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 [ 25.153449] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 [ 25.153980] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c [ 25.153999] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b830a5b4 state to 000000004178cf0c [ 25.154024] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 000000004178cf0c [ 25.154041] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000b830a5b4 to [NOCRTC] [ 25.154061] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b830a5b4 [ 25.154077] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c [ 25.154166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 25.154206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057b81693 state to 000000004178cf0c [ 25.154259] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 25.154300] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154379] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c [ 25.154444] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c [ 25.154460] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c [ 25.154493] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c [ 25.154515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000708b01e5 state to 000000004178cf0c [ 25.154536] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 000000004178cf0c [ 25.154560] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000708b01e5 to [NOCRTC] [ 25.154576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000708b01e5 [ 25.154587] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c [ 25.154631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 [ 25.154655] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ce0e84b state to 000000004178cf0c [ 25.154695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 25.154722] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154748] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154769] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 25.154792] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c [ 25.154835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c [ 25.154848] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c [ 25.273763] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 [ 25.273802] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040a74b19 state to 00000000383de8b5 [ 25.273827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000303042be state to 00000000383de8b5 [ 25.273843] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000303042be [ 25.273859] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 [ 25.274049] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.274099] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking [ 25.274159] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 [ 25.274183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000f55d2354 [ 25.274209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009ff1aeec state to 00000000f55d2354 [ 25.274223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000009ff1aeec [ 25.274237] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 [ 25.274352] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.274385] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking [ 25.292269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 [ 25.292288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 [ 25.297446] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 [ 25.297472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 [ 25.297764] [drm:drm_mode_addfb2 [drm]] [FB:133] [ 25.309363] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 [ 25.309501] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000086edd36c state to 00000000590d9307 [ 25.309726] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007d32f8a2 state to 00000000590d9307 [ 25.309825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:31:plane 1A] state 000000007d32f8a2 [ 25.309919] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 [ 25.310337] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.310572] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking [ 25.311148] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 [ 25.311195] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 000000009f1364b2 [ 25.311226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000da8e7b56 state to 000000009f1364b2 [ 25.311247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:52:plane 1B] state 00000000da8e7b56 [ 25.311272] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 [ 25.311530] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.311615] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking [ 25.313976] audit: type=1400 audit(1591264870.888:28): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 [ 25.325815] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 [ 25.325907] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 [ 25.330935] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 [ 25.330979] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 [ 25.348755] audit: type=1400 audit(1591264870.924:29): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 [ 25.370627] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 [ 25.370629] Bluetooth: BNEP filters: protocol multicast [ 25.370633] Bluetooth: BNEP socket layer initialized [ 25.375033] [drm:drm_mode_addfb2 [drm]] [FB:138] [ 25.375312] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] [ 25.375341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] [ 25.375361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 [ 25.375375] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004b47c821 state to 0000000033ce3db8 [ 25.375387] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006ac09869 state to 0000000033ce3db8 [ 25.375404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000006ac09869 [ 25.375420] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 [ 25.375436] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000001f8dd32 state to 0000000033ce3db8 [ 25.375454] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [NOCRTC] [ 25.375474] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [CRTC:51:pipe A] [ 25.375497] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 [ 25.375537] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] [ 25.375552] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] [ 25.375686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.375746] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 [ 25.392250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 [ 25.392268] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 [ 25.392303] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] [ 25.392323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] [ 25.392335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.392348] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 [ 25.392359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 [ 25.392372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 [ 25.392384] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 [ 25.392396] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000034523972 state to 000000009a35bdf3 [ 25.392410] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [NOCRTC] [ 25.392421] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [CRTC:72:pipe B] [ 25.392434] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.392444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 25.392450] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 25.392498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.392518] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 [ 25.397429] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.397444] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.397934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.397958] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005cff5841 state to 000000009a35bdf3 [ 25.397971] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.397987] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fa10941b state to 000000009a35bdf3 [ 25.398000] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 [ 25.414143] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.414156] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.414191] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] [ 25.414202] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] [ 25.414212] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.414223] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 [ 25.414232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 [ 25.414244] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:] for [CRTC:72:pipe B] state 00000000a5b8210f [ 25.414253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 [ 25.414265] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 [ 25.414277] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000083c2e296 state to 000000009a35bdf3 [ 25.414286] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [NOCRTC] [ 25.414295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [CRTC:72:pipe B] [ 25.414307] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.414316] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] [ 25.414321] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] [ 25.414366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.414381] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 [ 25.430771] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.430790] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.587615] [drm:drm_mode_addfb2 [drm]] [FB:137] [ 25.588562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000607204c5 [ 25.588594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 00000000607204c5 [ 25.588614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005aa8cfac state to 00000000607204c5 [ 25.588633] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000005aa8cfac [ 25.588649] [drm:drm_atomic_check_only [drm]] checking 00000000607204c5 [ 25.588824] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.588864] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000607204c5 nonblocking [ 25.589160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000006db89b4 [ 25.589182] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 0000000006db89b4 [ 25.589198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000ca4c9ba state to 0000000006db89b4 [ 25.589216] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000000ca4c9ba [ 25.589231] [drm:drm_atomic_check_only [drm]] checking 0000000006db89b4 [ 25.589319] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.589346] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000006db89b4 nonblocking [ 25.609114] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000607204c5 [ 25.609175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000607204c5 [ 25.614340] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000006db89b4 [ 25.614399] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000006db89b4 [ 25.631657] [drm:drm_mode_addfb2 [drm]] [FB:147] [ 25.632478] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a82a142d [ 25.632494] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000bfbd51fd state to 00000000a82a142d [ 25.632510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004b6af36c state to 00000000a82a142d [ 25.632526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004b6af36c [ 25.632545] [drm:drm_atomic_check_only [drm]] checking 00000000a82a142d [ 25.632706] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.632837] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a82a142d nonblocking [ 25.633235] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a9357def [ 25.633289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000780eaeb2 state to 00000000a9357def [ 25.633327] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ce7ebae0 state to 00000000a9357def [ 25.633378] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 00000000ce7ebae0 [ 25.633406] [drm:drm_atomic_check_only [drm]] checking 00000000a9357def [ 25.633671] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.633810] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a9357def nonblocking [ 25.659221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a82a142d [ 25.659354] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a82a142d [ 25.664414] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a9357def [ 25.664483] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 25.664520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000cb785d4f [ 25.664540] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a9357def [ 25.664556] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000024c9c604 state to 00000000cb785d4f [ 25.664570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000024c9c604 [ 25.664595] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 25.664849] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.664952] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 25.665286] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c [ 25.665325] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 0000000072b4047c [ 25.665373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 0000000072b4047c [ 25.665410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000002fdb83bd [ 25.665470] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c [ 25.665744] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.665883] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking [ 25.681106] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c [ 25.681311] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c [ 25.692362] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 25.692394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c329590e [ 25.692419] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 25.692437] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 00000000c329590e [ 25.692453] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002592f0c5 state to 00000000c329590e [ 25.692466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002592f0c5 [ 25.692479] [drm:drm_atomic_check_only [drm]] checking 00000000c329590e [ 25.692638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.692670] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c329590e nonblocking [ 25.692784] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 [ 25.692797] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 000000009a35bdf3 [ 25.692808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000044e6fdf state to 000000009a35bdf3 [ 25.692820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000044e6fdf [ 25.692830] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 [ 25.692941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.692966] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009a35bdf3 nonblocking [ 25.709084] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c329590e [ 25.709105] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c329590e [ 25.714310] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 [ 25.714357] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 [ 25.732545] [drm:drm_mode_addfb2 [drm]] [FB:148] [ 25.732641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 [ 25.732658] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cee74316 state to 000000003fe34687 [ 25.732679] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004ceca9e7 state to 000000003fe34687 [ 25.732693] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004ceca9e7 [ 25.732715] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 [ 25.732769] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.732802] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking [ 25.733102] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 [ 25.733225] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a7e0ad69 state to 00000000c58cae11 [ 25.733274] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002b75481e state to 00000000c58cae11 [ 25.733300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 000000002b75481e [ 25.733353] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 [ 25.733574] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.733722] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking [ 25.742433] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 [ 25.742504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 [ 25.747591] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 [ 25.747612] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 [ 25.747631] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 [ 25.747646] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 0000000033635145 [ 25.747660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000a08190f state to 0000000033635145 [ 25.747674] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:31:plane 1A] state 000000000a08190f [ 25.747686] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 [ 25.747857] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.747911] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking [ 25.748026] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f [ 25.748049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c56546ad state to 00000000e7507c6f [ 25.748062] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008ef93bc9 state to 00000000e7507c6f [ 25.748078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:52:plane 1B] state 000000008ef93bc9 [ 25.748091] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f [ 25.748209] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.748234] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e7507c6f nonblocking [ 25.759225] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 [ 25.759284] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 [ 25.764229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f [ 25.764250] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 [ 25.764265] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f [ 25.764284] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d304b4ce state to 00000000a72ea9e2 [ 25.764297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007150ba46 state to 00000000a72ea9e2 [ 25.764311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000007150ba46 [ 25.764322] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 [ 25.764463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.764494] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking [ 25.764530] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 25.764542] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7bb92f2 state to 000000004c5d43a8 [ 25.764552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a4812a5a state to 000000004c5d43a8 [ 25.764564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000a4812a5a [ 25.764574] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 25.764643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.764660] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking [ 25.792509] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 [ 25.792625] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 [ 25.797616] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 25.797650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 25.800508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 [ 25.800567] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000859f7d52 state to 0000000033635145 [ 25.800618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000065e53c0c state to 0000000033635145 [ 25.800656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000065e53c0c [ 25.800702] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 [ 25.800976] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.801119] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking [ 25.801505] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 [ 25.801543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 00000000f55d2354 [ 25.801584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a1a9a3bd state to 00000000f55d2354 [ 25.801609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000a1a9a3bd [ 25.801638] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 [ 25.801969] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.802166] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking [ 25.825728] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 [ 25.825748] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 [ 25.830902] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 [ 25.830932] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 [ 25.837586] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 25.837660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 00000000a7c3d9eb [ 25.837689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000de4c477a state to 00000000a7c3d9eb [ 25.837726] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000de4c477a [ 25.837761] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 25.837997] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.838175] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking [ 25.838378] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 25.838452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000006e8a3f03 [ 25.838489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c00467ed state to 000000006e8a3f03 [ 25.838516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000c00467ed [ 25.838580] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 25.838855] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.839042] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking [ 25.864311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 25.864356] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 25.875747] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 25.875867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 25.876790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9b8f040 [ 25.876815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ea06c3a state to 00000000f9b8f040 [ 25.876837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cc7821e8 state to 00000000f9b8f040 [ 25.876856] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000cc7821e8 [ 25.876876] [drm:drm_atomic_check_only [drm]] checking 00000000f9b8f040 [ 25.877085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.877133] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f9b8f040 nonblocking [ 25.877191] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 [ 25.877221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 000000005795e3f4 [ 25.877240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000466fb708 state to 000000005795e3f4 [ 25.877257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000466fb708 [ 25.877271] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 [ 25.877359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.877378] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking [ 25.909168] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9b8f040 [ 25.909283] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9b8f040 [ 25.914266] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 [ 25.914289] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 [ 25.933490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b [ 25.933516] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040ff38e3 state to 00000000d223d21b [ 25.933535] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002062a680 state to 00000000d223d21b [ 25.933551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002062a680 [ 25.933566] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b [ 25.933717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.933757] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking [ 25.933867] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 [ 25.933906] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005ea21f1d state to 000000005795e3f4 [ 25.933940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000038b73e52 state to 000000005795e3f4 [ 25.933995] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000038b73e52 [ 25.934034] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 [ 25.934359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.934554] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking [ 25.959269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b [ 25.959471] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b [ 25.964230] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 [ 25.964288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 [ 25.965190] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 [ 25.965227] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000383de8b5 [ 25.965252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a1a9a3bd state to 00000000383de8b5 [ 25.965276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000a1a9a3bd [ 25.965293] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 [ 25.965486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 25.965520] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking [ 25.965577] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 [ 25.965598] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000f55d2354 [ 25.965625] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3527d8e state to 00000000f55d2354 [ 25.965654] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000f3527d8e [ 25.965674] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 [ 25.965862] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 25.965959] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking [ 25.966673] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 [ 25.966697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bbab38cb state to 0000000033635145 [ 25.966723] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000033635145 [ 25.966747] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000bbab38cb to [CRTC:51:pipe A] [ 25.966765] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000bbab38cb [ 25.966785] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 [ 25.966981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.967029] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 0000000033635145 [ 25.967093] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.967142] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.967186] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.967233] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.967258] [drm:drm_atomic_commit [drm]] committing 0000000033635145 [ 25.970239] audit: type=1400 audit(1591264871.544:30): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 [ 25.971457] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f [ 25.971516] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ffb1c30d state to 00000000e7507c6f [ 25.971540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c56546ad state to 00000000e7507c6f [ 25.971557] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ffb1c30d to [CRTC:51:pipe A] [ 25.971574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:150] for [PLANE:47:cursor A] state 00000000ffb1c30d [ 25.971595] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f [ 25.971816] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.971916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035459c5a state to 00000000e7507c6f [ 25.972107] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.972162] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.972196] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.972235] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.972271] [drm:drm_atomic_commit [drm]] committing 00000000e7507c6f [ 25.976346] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d [ 25.976369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000056d83168 state to 000000000949282d [ 25.976387] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 000000000949282d [ 25.976401] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000056d83168 to [CRTC:51:pipe A] [ 25.976412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:151] for [PLANE:47:cursor A] state 0000000056d83168 [ 25.976424] [drm:drm_atomic_check_only [drm]] checking 000000000949282d [ 25.976565] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.976600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000000949282d [ 25.976650] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.976680] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.976701] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.976729] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.976744] [drm:drm_atomic_commit [drm]] committing 000000000949282d [ 25.981361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059bcf2ab [ 25.981377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000048a2243e state to 0000000059bcf2ab [ 25.981395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000059bcf2ab [ 25.981415] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000048a2243e to [CRTC:51:pipe A] [ 25.981427] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:152] for [PLANE:47:cursor A] state 0000000048a2243e [ 25.981439] [drm:drm_atomic_check_only [drm]] checking 0000000059bcf2ab [ 25.981587] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.981634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035f866f8 state to 0000000059bcf2ab [ 25.981732] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.981763] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.981793] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.981814] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.981833] [drm:drm_atomic_commit [drm]] committing 0000000059bcf2ab [ 25.986335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 [ 25.986358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 [ 25.986378] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 [ 25.986391] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] [ 25.986405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:153] for [PLANE:47:cursor A] state 000000007d32f8a2 [ 25.986419] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 [ 25.986566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.986601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 [ 25.986671] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.986697] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.986721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.986745] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.986760] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 [ 25.990116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059bcf2ab [ 25.990136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059bcf2ab [ 25.990147] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d [ 25.990160] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d [ 25.990183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f [ 25.990214] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f [ 25.990233] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 [ 25.990250] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 [ 25.991475] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 [ 25.991566] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 [ 25.991821] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 [ 25.992024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 [ 25.992099] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 [ 25.992156] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] [ 25.992212] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 000000007d32f8a2 [ 25.992229] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 [ 25.992294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 25.992311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 [ 25.992332] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 [ 25.992348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 [ 25.992378] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 25.992399] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 25.992427] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 25.992446] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 25.992459] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 [ 25.992502] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 [ 25.992514] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 [ 25.997491] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 [ 25.997513] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 [ 26.001019] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cd3e6c30 [ 26.001079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000cd3e6c30 [ 26.001104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000efc3561e state to 00000000cd3e6c30 [ 26.001122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000efc3561e [ 26.001139] [drm:drm_atomic_check_only [drm]] checking 00000000cd3e6c30 [ 26.001381] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.001424] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cd3e6c30 nonblocking [ 26.001502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 [ 26.001517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 00000000fb7b81d0 [ 26.001539] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000fb7b81d0 [ 26.001553] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000008a19b957 [ 26.001564] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 [ 26.001663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.001718] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fb7b81d0 nonblocking [ 26.025633] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cd3e6c30 [ 26.025657] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cd3e6c30 [ 26.031038] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 [ 26.031111] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 [ 26.032140] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d [ 26.032186] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002822e6ce state to 000000000949282d [ 26.032214] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 000000000949282d [ 26.032242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005ba888f4 [ 26.032278] [drm:drm_atomic_check_only [drm]] checking 000000000949282d [ 26.032460] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.032551] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000949282d nonblocking [ 26.032715] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 [ 26.032747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000048287824 [ 26.032774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000010080940 state to 0000000048287824 [ 26.032814] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000010080940 [ 26.032843] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 [ 26.033033] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.033133] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking [ 26.058971] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d [ 26.058986] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d [ 26.064135] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 [ 26.064151] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 [ 26.065142] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f [ 26.065161] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000db144c3f [ 26.065176] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003338987c state to 00000000db144c3f [ 26.065189] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003338987c [ 26.065202] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f [ 26.065341] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.065389] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking [ 26.065427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 [ 26.065439] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 0000000048287824 [ 26.065452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003d3598b9 state to 0000000048287824 [ 26.065464] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003d3598b9 [ 26.065477] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 [ 26.065545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.065571] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking [ 26.092355] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f [ 26.092369] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f [ 26.097513] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 [ 26.097527] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 [ 26.098050] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 26.098064] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7bb92f2 state to 000000004c5d43a8 [ 26.098076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f17f63d state to 000000004c5d43a8 [ 26.098088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000008f17f63d [ 26.098098] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 26.098144] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.098173] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking [ 26.098205] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 [ 26.098216] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d304b4ce state to 00000000a72ea9e2 [ 26.098226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000001a43d2f state to 00000000a72ea9e2 [ 26.098237] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000001a43d2f [ 26.098247] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 [ 26.098291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.098309] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking [ 26.125651] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 26.125679] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 26.130834] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 [ 26.130867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 [ 26.131366] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 26.131383] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 00000000ad3ae327 [ 26.131396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062957589 state to 00000000ad3ae327 [ 26.131409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000062957589 [ 26.131421] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 26.131472] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.131499] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking [ 26.131531] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 [ 26.131543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 000000009ab7d7a2 [ 26.131553] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e42a1bac state to 000000009ab7d7a2 [ 26.131565] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000e42a1bac [ 26.131577] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 [ 26.131662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.131685] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking [ 26.158952] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 26.158972] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 26.164140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 [ 26.164157] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 [ 26.164688] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 [ 26.164707] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c88e1744 state to 000000009ab7d7a2 [ 26.164721] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002b4570b0 state to 000000009ab7d7a2 [ 26.164732] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000002b4570b0 [ 26.164741] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 [ 26.164779] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.164794] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking [ 26.164817] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 26.164828] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cfd8c976 state to 00000000ad3ae327 [ 26.164837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000217fb779 state to 00000000ad3ae327 [ 26.164846] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000217fb779 [ 26.164854] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 26.164902] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.164925] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking [ 26.192294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 [ 26.192316] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 [ 26.197558] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 26.197586] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 26.198086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 [ 26.198107] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000005795e3f4 [ 26.198125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d5e0ab1c state to 000000005795e3f4 [ 26.198142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000d5e0ab1c [ 26.198161] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 [ 26.198224] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.198254] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking [ 26.198298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b [ 26.198316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 00000000d223d21b [ 26.198334] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001aa4b64b state to 00000000d223d21b [ 26.198353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001aa4b64b [ 26.198369] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b [ 26.198496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.198527] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking [ 26.214153] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b [ 26.214175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b [ 26.225632] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 [ 26.225662] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 [ 26.462632] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 [ 26.462656] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007d558a50 state to 00000000e7804b44 [ 26.462673] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 [ 26.462708] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006d587bbb state to 00000000e7804b44 [ 26.462727] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 [ 26.475706] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 [ 26.475726] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 [ 26.475759] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 [ 26.475794] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008598d75f state to 00000000e7804b44 [ 26.475808] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 [ 26.475829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 00000000e7804b44 [ 26.475857] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 [ 26.480907] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 [ 26.480929] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 [ 26.490104] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b [ 26.490125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000d223d21b [ 26.490143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000bda1a70 state to 00000000d223d21b [ 26.490160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000000bda1a70 [ 26.490174] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b [ 26.490263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 26.490296] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking [ 26.490379] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005b4fe663 [ 26.490395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 000000005b4fe663 [ 26.490412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ad4d2a9 state to 000000005b4fe663 [ 26.490432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000004ad4d2a9 [ 26.490446] [drm:drm_atomic_check_only [drm]] checking 000000005b4fe663 [ 26.490577] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 26.490612] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005b4fe663 nonblocking [ 26.508990] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b [ 26.509012] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b [ 26.514166] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005b4fe663 [ 26.514193] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005b4fe663 [ 27.203105] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 [ 27.203118] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 0000000048287824 [ 27.203128] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003d3598b9 state to 0000000048287824 [ 27.203138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003d3598b9 [ 27.203147] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 [ 27.203191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 27.203207] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking [ 27.203239] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f [ 27.203248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000db144c3f [ 27.203257] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006225429c state to 00000000db144c3f [ 27.203266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000006225429c [ 27.203274] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f [ 27.203327] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 27.203340] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking [ 27.214214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f [ 27.214237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f [ 27.225708] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 [ 27.225729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 [ 27.559248] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 27.559266] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000a7c3d9eb [ 27.559287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000048a2243e state to 00000000a7c3d9eb [ 27.559302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000048a2243e [ 27.559317] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 27.559457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 27.559500] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking [ 27.559579] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 [ 27.559595] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000073a3fc87 [ 27.559614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c26d3cf7 state to 0000000073a3fc87 [ 27.559630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000c26d3cf7 [ 27.559644] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 [ 27.559875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 27.559954] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking [ 27.564240] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 [ 27.564260] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 [ 27.575734] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 27.575758] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 27.673875] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006fb947e5 [ 27.673893] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000006fb947e5 [ 27.673907] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003def6fcc state to 000000006fb947e5 [ 27.673919] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003def6fcc [ 27.673930] [drm:drm_atomic_check_only [drm]] checking 000000006fb947e5 [ 27.674063] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 27.674111] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006fb947e5 nonblocking [ 27.674162] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000022edf81f [ 27.674180] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bfbd51fd state to 0000000022edf81f [ 27.674205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ba74e4f8 state to 0000000022edf81f [ 27.674221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000ba74e4f8 [ 27.674236] [drm:drm_atomic_check_only [drm]] checking 0000000022edf81f [ 27.674351] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 27.674383] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000022edf81f nonblocking [ 27.692395] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006fb947e5 [ 27.692416] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006fb947e5 [ 27.697567] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000022edf81f [ 27.697587] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000022edf81f [ 28.369864] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 [ 28.369881] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f4595bbc state to 00000000a72ea9e2 [ 28.369892] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e0f8f74a state to 00000000a72ea9e2 [ 28.369905] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000e0f8f74a [ 28.369917] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 [ 28.370044] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 28.370094] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking [ 28.370128] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e2245646 [ 28.370140] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000080a25d5d state to 00000000e2245646 [ 28.370155] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ec8b7f51 state to 00000000e2245646 [ 28.370165] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000ec8b7f51 [ 28.370173] [drm:drm_atomic_check_only [drm]] checking 00000000e2245646 [ 28.370236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 28.370259] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e2245646 nonblocking [ 28.392441] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 [ 28.392456] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 [ 28.397627] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e2245646 [ 28.397645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e2245646 [ 28.441580] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007c7bef8b [ 28.441593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 000000007c7bef8b [ 28.441602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 000000007c7bef8b [ 28.441619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000919acba8 [ 28.441636] [drm:drm_atomic_check_only [drm]] checking 000000007c7bef8b [ 28.441807] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 28.441857] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007c7bef8b nonblocking [ 28.441895] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e4cb9fa [ 28.441926] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004f0788b2 state to 000000009e4cb9fa [ 28.441949] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003cdbbe01 state to 000000009e4cb9fa [ 28.441966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003cdbbe01 [ 28.441983] [drm:drm_atomic_check_only [drm]] checking 000000009e4cb9fa [ 28.442129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 28.442151] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e4cb9fa nonblocking [ 28.459102] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007c7bef8b [ 28.459118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007c7bef8b [ 28.464290] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e4cb9fa [ 28.464312] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e4cb9fa [ 28.722641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 28.722655] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007b516bb0 state to 00000000cb785d4f [ 28.722664] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dfbf1324 state to 00000000cb785d4f [ 28.722675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000dfbf1324 [ 28.722684] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 28.722813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 28.722835] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 28.722882] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff [ 28.722908] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003cd98772 state to 0000000094adecff [ 28.722916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009beb6a90 state to 0000000094adecff [ 28.722941] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000009beb6a90 [ 28.722949] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff [ 28.723029] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 28.723064] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking [ 28.742477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 28.742503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 28.747618] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff [ 28.747633] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff [ 31.314482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 31.314504] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 33.564502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff [ 33.564557] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001450a92b state to 0000000094adecff [ 33.564599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fb9c3f95 state to 0000000094adecff [ 33.564642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000fb9c3f95 [ 33.564680] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff [ 33.564830] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 33.564895] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking [ 33.564991] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f [ 33.565033] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d785a3ff state to 00000000cb785d4f [ 33.565068] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001694423a state to 00000000cb785d4f [ 33.565110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001694423a [ 33.565145] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f [ 33.565280] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 33.565331] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking [ 33.581360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f [ 33.581410] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f [ 33.592967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff [ 33.593018] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff [ 38.906236] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 38.906257] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fbb9145a state to 00000000a7c3d9eb [ 38.906277] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 38.906300] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031040ef6 state to 00000000a7c3d9eb [ 38.906317] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb [ 38.909717] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 38.909729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 38.909751] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 38.909763] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000036e370a5 state to 00000000a7c3d9eb [ 38.909772] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 38.909789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000021d5013d state to 00000000a7c3d9eb [ 38.909799] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb [ 38.914888] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 38.914897] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 38.919179] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb [ 38.919191] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000dbca7270 state to 00000000a7c3d9eb [ 38.919200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f5920396 state to 00000000a7c3d9eb [ 38.919210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000f5920396 [ 38.919219] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb [ 38.919269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 38.919283] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking [ 38.919307] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3b84e34 [ 38.919316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007a397cd1 state to 00000000d3b84e34 [ 38.919324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000d3b84e34 [ 38.919333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000008a19b957 [ 38.919340] [drm:drm_atomic_check_only [drm]] checking 00000000d3b84e34 [ 38.919369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 38.919380] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3b84e34 nonblocking [ 38.943037] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb [ 38.943049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb [ 38.948213] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3b84e34 [ 38.948227] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3b84e34 [ 41.313990] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 41.314011] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000dffa3a5 state to 000000006e8a3f03 [ 41.314024] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 41.314044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000311fb5cc state to 000000006e8a3f03 [ 41.314058] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 [ 41.326599] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 41.326616] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 41.326650] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 41.326666] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000006e8a3f03 [ 41.326677] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 41.326694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f678ed03 state to 000000006e8a3f03 [ 41.326708] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 [ 41.331765] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 41.331799] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 41.340881] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 [ 41.340898] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b35cdb13 state to 0000000014564192 [ 41.340911] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002bd9f19b state to 0000000014564192 [ 41.340924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002bd9f19b [ 41.340936] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 [ 41.341000] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 41.341031] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking [ 41.341070] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e [ 41.341083] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000505d8d8e [ 41.341093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000628b1791 state to 00000000505d8d8e [ 41.341106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000628b1791 [ 41.341117] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e [ 41.341171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 41.341187] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking [ 41.359835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 [ 41.359858] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 [ 41.365024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e [ 41.365048] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e [ 41.615782] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000336440de [ 41.615833] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 41.617086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 [ 41.617101] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000029690ea0 [ 41.617111] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 [ 41.617127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000043ec3708 state to 0000000029690ea0 [ 41.617139] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 [ 41.626562] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 [ 41.626572] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 [ 41.626602] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 [ 41.626612] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000029690ea0 [ 41.626620] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 [ 41.626634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dd5969b1 state to 0000000029690ea0 [ 41.626644] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 [ 41.631801] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 [ 41.631813] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 [ 41.636417] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 [ 41.636431] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005cff5841 state to 000000006e8a3f03 [ 41.636443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f261da0 state to 000000006e8a3f03 [ 41.636455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005f261da0 [ 41.636465] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 [ 41.636505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 41.636529] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking [ 41.636564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 [ 41.636574] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004b47c821 state to 0000000073a3fc87 [ 41.636583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005b73df2f state to 0000000073a3fc87 [ 41.636593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000005b73df2f [ 41.636601] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 [ 41.636649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 41.636661] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking [ 41.659846] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 [ 41.659868] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 [ 41.665021] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 [ 41.665038] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 [ 41.694775] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000b6d87631 [ 41.694823] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 42.188680] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 [ 42.188751] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000568d4c state to 00000000ad3ae327 [ 42.188815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000041d1b185 state to 00000000ad3ae327 [ 42.188876] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000000568d4c to [NOCRTC] [ 42.188938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000568d4c [ 42.188994] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 [ 42.189140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 42.189200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ccaa86bb state to 00000000ad3ae327 [ 42.189327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 42.189398] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 42.189464] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 42.189528] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 42.189570] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 [ 42.189702] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 [ 42.189745] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 [ 75.712241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000607204c5 [ 75.712254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000576bf63 state to 00000000607204c5 [ 75.712264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000143dcc1f state to 00000000607204c5 [ 75.712276] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000000576bf63 to [CRTC:51:pipe A] [ 75.712285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000576bf63 [ 75.712296] [drm:drm_atomic_check_only [drm]] checking 00000000607204c5 [ 75.712332] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 75.712348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000ffcd5de state to 00000000607204c5 [ 75.712381] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 75.712399] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 75.712415] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 75.712431] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 75.712442] [drm:drm_atomic_commit [drm]] committing 00000000607204c5 [ 75.712495] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000607204c5 [ 75.712504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000607204c5 [ 75.781357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ad4520e1 [ 75.781395] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.791429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 [ 75.791470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.801366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ad4520e1 [ 75.801416] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.811455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 [ 75.811526] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.821420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ad4520e1 [ 75.821537] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.822025] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004f41ae90 [ 75.822160] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.828890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000111517e [ 75.828945] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004474ffb0 state to 000000000111517e [ 75.828985] [drm:drm_atomic_check_only [drm]] checking 000000000111517e [ 75.829049] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001dbce9c7 state to 000000000111517e [ 75.829094] [drm:drm_atomic_commit [drm]] committing 000000000111517e [ 75.845350] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000111517e [ 75.845405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 [ 75.845533] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.845576] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000111517e [ 75.845662] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000111517e [ 75.845711] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f252405b state to 000000000111517e [ 75.845747] [drm:drm_atomic_check_only [drm]] checking 000000000111517e [ 75.845797] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000065cb5608 state to 000000000111517e [ 75.845840] [drm:drm_atomic_commit [drm]] committing 000000000111517e [ 75.850710] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000111517e [ 75.850765] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.850899] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.850942] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000111517e [ 75.851263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 [ 75.851378] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.852514] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c16485eb [ 75.852646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.861172] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.861226] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.871150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 75.871191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.881240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.881355] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.893221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 75.893271] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.903314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.903439] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.913297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 75.913425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.923441] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.923656] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.933291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 75.933421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.943379] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.943566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.953281] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 75.953413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.963369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.963556] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.973333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 75.973559] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.983300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 75.983431] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 75.993401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 75.993546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.003301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 [ 76.003435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.013376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd [ 76.013646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.023314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004f41ae90 [ 76.023453] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.033435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f [ 76.033571] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.043538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001f6da878 [ 76.043679] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.048401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eb35d02a [ 76.048532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.053296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f [ 76.053412] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.063269] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.063388] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.083545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f [ 76.083684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.223546] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.223683] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.233482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f [ 76.233614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.243500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.243637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.253466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f [ 76.253601] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.263265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.263394] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.273468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f [ 76.273600] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.275225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 76.275358] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.283228] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.283340] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.293214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.293326] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.303554] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.303690] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.313316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.313448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.323542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.323679] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.333455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.333591] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.343258] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.343390] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.353459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.353594] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.363280] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.363411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.373466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.373593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.383343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.383482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.393463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.393597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.403300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.403426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.413475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.413603] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.423544] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.423680] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.433472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.433605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.443555] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.443734] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.453483] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.453624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.463485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.463630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.473481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.473620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.493468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 [ 76.493600] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.545324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.545445] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.595519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 [ 76.595647] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.623497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.623629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.643494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 [ 76.643630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.663554] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.663713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.683463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 [ 76.683597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.703310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.703442] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.723290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 [ 76.723417] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.743544] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.743720] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.783547] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 [ 76.783725] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.843532] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.843662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.905560] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 [ 76.905699] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 76.965472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 76.965607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 77.025455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 [ 77.025591] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 77.074419] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009658a4c3 [ 77.074439] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 000000009658a4c3 [ 77.074457] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000ffcd5de state to 000000009658a4c3 [ 77.074472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000000ffcd5de [ 77.074485] [drm:drm_atomic_check_only [drm]] checking 000000009658a4c3 [ 77.074568] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 77.074593] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009658a4c3 nonblocking [ 77.074640] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 [ 77.074656] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c6de3170 state to 00000000a311e694 [ 77.074668] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000000568d4c state to 00000000a311e694 [ 77.074683] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000000568d4c [ 77.074695] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 [ 77.074751] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 77.074769] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a311e694 nonblocking [ 77.095355] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009658a4c3 [ 77.095391] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009658a4c3 [ 77.100625] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 [ 77.100677] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 [ 77.585381] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 [ 77.585398] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d29c2cef state to 00000000a311e694 [ 77.585407] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 [ 77.585424] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 00000000a311e694 [ 77.585434] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 [ 77.595300] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 [ 77.595322] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 [ 77.595350] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 [ 77.595363] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000df3dd718 state to 00000000a311e694 [ 77.595371] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 [ 77.595384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a35c929d state to 00000000a311e694 [ 77.595395] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 [ 77.600480] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 [ 77.600493] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 [ 77.603245] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 [ 77.603259] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 00000000a311e694 [ 77.603269] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 [ 77.603287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000000568d4c state to 00000000a311e694 [ 77.603297] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 [ 77.611945] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 [ 77.611956] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 [ 77.611976] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 [ 77.611986] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000065c69239 state to 00000000a311e694 [ 77.611994] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 [ 77.612005] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000046234f6 state to 00000000a311e694 [ 77.612015] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 [ 77.617129] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 [ 77.617140] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 [ 77.622988] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 [ 77.623007] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000df3dd718 state to 00000000a311e694 [ 77.623020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 00000000a311e694 [ 77.623030] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000f3527d8e [ 77.623039] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 [ 77.623136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 77.623170] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a311e694 nonblocking [ 77.623230] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009658a4c3 [ 77.623242] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005e067cfa state to 000000009658a4c3 [ 77.623252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009b956d2f state to 000000009658a4c3 [ 77.623261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000009b956d2f [ 77.623271] [drm:drm_atomic_check_only [drm]] checking 000000009658a4c3 [ 77.623350] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 77.623373] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009658a4c3 nonblocking [ 77.624696] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 77.624912] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 77.645249] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 [ 77.645275] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 [ 77.650421] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009658a4c3 [ 77.650436] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009658a4c3 [ 79.835317] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cf2f853c [ 79.835486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.845507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d [ 79.845624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.855334] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba [ 79.855448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.865484] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d [ 79.865622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.875475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba [ 79.875613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.885352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d [ 79.885532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.895528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba [ 79.895690] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.905325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d [ 79.905461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.915469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba [ 79.915615] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.925302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d [ 79.925433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.935312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 79.935454] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.945282] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 79.945405] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.955494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 79.955663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.965460] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 79.965593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.975471] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 79.975609] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.985296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 79.985441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 79.995529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 79.995681] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.005487] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 80.005627] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.015327] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 80.015464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.025288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 80.025420] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.035299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 80.035437] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.045482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 80.045611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.055317] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 80.055457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.065490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 80.065624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.075462] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d [ 80.075610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.125351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 [ 80.125485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.135356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.135496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.145284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.145413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.155461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.155609] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.165266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.165398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.177475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.177613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.183287] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.183415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.193307] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.193441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.203311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.203450] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.217262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.217388] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.227279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.227401] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.237310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.237448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.247500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.247655] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.257333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.257473] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.267469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.267601] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.277467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.277607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.285323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.285464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.295452] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.295588] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.305318] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.305470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.315543] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.315696] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.335338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.335468] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.385288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 [ 80.385430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 80.445465] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f [ 80.445594] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 82.028033] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 82.028049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000004c5d43a8 [ 82.028060] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 82.028080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000154a4b83 state to 000000004c5d43a8 [ 82.028092] [drm:drm_atomic_commit [drm]] committing 000000004c5d43a8 [ 82.028824] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 82.028834] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 82.028849] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 [ 82.028878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000008fdc242 state to 000000004c5d43a8 [ 82.028886] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 [ 82.028898] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007a36128c state to 000000004c5d43a8 [ 82.028909] [drm:drm_atomic_commit [drm]] committing 000000004c5d43a8 [ 82.034056] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 [ 82.034069] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 [ 82.037311] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004eb6a0eb [ 82.037326] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002d5bfaf4 state to 000000004eb6a0eb [ 82.037337] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000004eb6a0eb [ 82.037348] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000010080940 [ 82.037359] [drm:drm_atomic_check_only [drm]] checking 000000004eb6a0eb [ 82.037416] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 82.037436] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004eb6a0eb nonblocking [ 82.037464] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000093e3499b [ 82.037476] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006047c305 state to 0000000093e3499b [ 82.037488] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a7136fb4 state to 0000000093e3499b [ 82.037499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000a7136fb4 [ 82.037509] [drm:drm_atomic_check_only [drm]] checking 0000000093e3499b [ 82.037544] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 82.037558] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000093e3499b nonblocking [ 82.062210] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004eb6a0eb [ 82.062236] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004eb6a0eb [ 82.067378] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093e3499b [ 82.067394] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000093e3499b [ 84.543578] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ed46affd [ 84.543602] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004b47c821 state to 00000000ed46affd [ 84.543618] [drm:drm_atomic_check_only [drm]] checking 00000000ed46affd [ 84.543648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002603cbe2 state to 00000000ed46affd [ 84.543666] [drm:drm_atomic_commit [drm]] committing 00000000ed46affd [ 84.545657] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ed46affd [ 84.545673] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ed46affd [ 84.545701] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ed46affd [ 84.545718] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002d5bfaf4 state to 00000000ed46affd [ 84.545731] [drm:drm_atomic_check_only [drm]] checking 00000000ed46affd [ 84.545748] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000010080940 state to 00000000ed46affd [ 84.545763] [drm:drm_atomic_commit [drm]] committing 00000000ed46affd [ 84.550847] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ed46affd [ 84.550860] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ed46affd [ 84.557572] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006d11616c [ 84.557590] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000006d11616c [ 84.557608] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000069618bd2 state to 000000006d11616c [ 84.557623] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000069618bd2 [ 84.557634] [drm:drm_atomic_check_only [drm]] checking 000000006d11616c [ 84.557741] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 84.557765] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006d11616c nonblocking [ 84.557820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072283c24 [ 84.557834] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006746a59a state to 0000000072283c24 [ 84.557845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b4d7ac94 state to 0000000072283c24 [ 84.557857] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000b4d7ac94 [ 84.557867] [drm:drm_atomic_check_only [drm]] checking 0000000072283c24 [ 84.557936] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 84.557952] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072283c24 nonblocking [ 84.578982] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006d11616c [ 84.579000] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006d11616c [ 84.584154] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072283c24 [ 84.584177] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072283c24 [ 84.810041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009e7e27ec [ 84.810134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 84.813702] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a92e964 [ 84.813718] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f0788b2 state to 000000002a92e964 [ 84.813728] [drm:drm_atomic_check_only [drm]] checking 000000002a92e964 [ 84.813749] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010343cf4 state to 000000002a92e964 [ 84.813760] [drm:drm_atomic_commit [drm]] committing 000000002a92e964 [ 84.829128] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a92e964 [ 84.829143] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a92e964 [ 84.829191] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a92e964 [ 84.829204] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000b35e8fe1 state to 000000002a92e964 [ 84.829214] [drm:drm_atomic_check_only [drm]] checking 000000002a92e964 [ 84.829228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a24a2bb2 state to 000000002a92e964 [ 84.829240] [drm:drm_atomic_commit [drm]] committing 000000002a92e964 [ 84.834375] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a92e964 [ 84.834390] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a92e964 [ 84.837643] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ed46affd [ 84.837657] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d304b4ce state to 00000000ed46affd [ 84.837668] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002603cbe2 state to 00000000ed46affd [ 84.837680] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002603cbe2 [ 84.837691] [drm:drm_atomic_check_only [drm]] checking 00000000ed46affd [ 84.837740] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 84.837767] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ed46affd nonblocking [ 84.837799] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000093e3499b [ 84.837810] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 0000000093e3499b [ 84.837820] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007ae821d2 state to 0000000093e3499b [ 84.837831] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000007ae821d2 [ 84.837840] [drm:drm_atomic_check_only [drm]] checking 0000000093e3499b [ 84.837885] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 84.837905] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000093e3499b nonblocking [ 84.862321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ed46affd [ 84.862340] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ed46affd [ 84.867503] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093e3499b [ 84.867515] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000093e3499b [ 84.896014] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000f1c75f07 [ 84.896056] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 87.939190] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009bdf158a [ 87.939238] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 87.949179] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 [ 87.949242] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 87.959161] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009bdf158a [ 87.959214] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 87.969364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 [ 87.969408] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 87.979229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 [ 87.979284] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 87.989350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c [ 87.989426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 87.999240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 [ 87.999345] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.009303] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c [ 88.009432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.019315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 [ 88.019497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.031529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c [ 88.031666] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.037250] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 [ 88.037398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.047541] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c [ 88.047682] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.057296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 [ 88.057434] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.057767] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ba74e4f8 [ 88.057883] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.058961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003def6fcc [ 88.059085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.059176] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ba74e4f8 [ 88.059286] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.059361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003def6fcc [ 88.059483] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.067549] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c [ 88.067677] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.068174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ba74e4f8 [ 88.068333] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.070123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003def6fcc [ 88.070245] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.077300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000011d500be [ 88.077477] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.087298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000158adbaf [ 88.087482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.097298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000011d500be [ 88.097475] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.107169] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000158adbaf [ 88.107272] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.117202] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000011d500be [ 88.117301] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.127203] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007445155b [ 88.127307] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.137297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 88.137440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.147296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007445155b [ 88.147444] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.157417] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 88.157677] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.167323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007445155b [ 88.167508] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.177435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 88.177607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.187310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 [ 88.187456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.197418] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e0498636 [ 88.197627] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.207404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 [ 88.207631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.217445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e0498636 [ 88.217669] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.227381] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 [ 88.227606] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.237296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e0498636 [ 88.237426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.247467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 [ 88.247674] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 88.601051] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 88.601084] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 88.815597] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b436c25 [ 88.815609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ddf8aae9 state to 000000001b436c25 [ 88.815619] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 000000001b436c25 [ 88.815629] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ddf8aae9 to [NOCRTC] [ 88.815637] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ddf8aae9 [ 88.815646] [drm:drm_atomic_check_only [drm]] checking 000000001b436c25 [ 88.815710] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 88.815730] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000080184d54 state to 000000001b436c25 [ 88.815750] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 88.815779] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 88.815808] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 88.815824] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 88.815833] [drm:drm_atomic_commit [drm]] committing 000000001b436c25 [ 88.815877] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b436c25 [ 88.815887] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b436c25 [ 88.817733] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 88.817767] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 89.801101] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 89.801125] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 94.868102] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 94.868146] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 96.201520] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 96.201544] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 98.735069] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 98.735183] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 100.606232] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 [ 100.606285] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009ad673f7 state to 000000009ab7d7a2 [ 100.606333] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006047c305 state to 000000009ab7d7a2 [ 100.606377] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000009ad673f7 to [CRTC:51:pipe A] [ 100.606417] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009ad673f7 [ 100.606456] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 [ 100.606598] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 100.606651] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000444592af state to 000000009ab7d7a2 [ 100.606734] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 100.606807] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 100.606875] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 100.606943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 100.606985] [drm:drm_atomic_commit [drm]] committing 000000009ab7d7a2 [ 100.607113] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 [ 100.607152] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 [ 100.655506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 [ 100.655644] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.665498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000092fcae0b [ 100.665636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.679509] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 [ 100.679646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.685421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000092fcae0b [ 100.685553] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.695279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 [ 100.695410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.705491] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000092fcae0b [ 100.705621] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.715556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 [ 100.715694] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.716246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004a0693b5 [ 100.716379] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.725283] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 [ 100.725478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.735276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.735410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.746365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 [ 100.746523] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.755234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.755310] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.765226] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 [ 100.765298] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.775291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.775412] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.785333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 [ 100.785497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.792131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb [ 100.792223] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.795223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.795321] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.805337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c [ 100.805517] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.815332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.815555] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.825362] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c [ 100.825538] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.835433] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.835644] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.845319] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c [ 100.845456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.855444] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.855641] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.865347] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c [ 100.865484] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.875405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.875586] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.885342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c [ 100.885486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.895475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.895647] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.905451] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c [ 100.905587] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.915225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 [ 100.915349] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.925461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c [ 100.925595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.935324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 100.935498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.945484] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 100.945616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.955553] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 100.955687] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.965499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 100.965634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.975545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 100.975681] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 100.985336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 100.985468] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.005483] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 101.005619] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.035325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 101.035479] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.075556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 101.075692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.127499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 101.127634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 101.674425] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000034d78fc [ 101.674497] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c83bd8e4 state to 00000000034d78fc [ 101.674558] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000379a654d state to 00000000034d78fc [ 101.674624] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c83bd8e4 to [NOCRTC] [ 101.674681] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 101.674738] [drm:drm_atomic_check_only [drm]] checking 00000000034d78fc [ 101.674869] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 101.674948] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007b42b813 state to 00000000034d78fc [ 101.675042] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 101.675113] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 101.675180] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 101.675244] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 101.675287] [drm:drm_atomic_commit [drm]] committing 00000000034d78fc [ 101.675456] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000034d78fc [ 101.675502] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000034d78fc [ 103.335218] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 103.335242] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 106.809611] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e4cb9fa [ 106.809627] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a4ba128e state to 000000009e4cb9fa [ 106.809641] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f53352ac state to 000000009e4cb9fa [ 106.809654] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000a4ba128e to [CRTC:51:pipe A] [ 106.809666] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a4ba128e [ 106.809682] [drm:drm_atomic_check_only [drm]] checking 000000009e4cb9fa [ 106.809728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 106.809748] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006506bed9 state to 000000009e4cb9fa [ 106.809786] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 106.809809] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 106.809830] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 106.809851] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 106.809864] [drm:drm_atomic_commit [drm]] committing 000000009e4cb9fa [ 106.809912] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e4cb9fa [ 106.809924] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e4cb9fa [ 106.849138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 106.849192] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.859127] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 106.859181] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.869117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 106.869157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.879122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 106.879161] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.889116] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 106.889168] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.901127] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be [ 106.901174] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.907187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 [ 106.907228] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.917130] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 106.917175] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.927128] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 [ 106.927179] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.937134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 106.937188] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.947131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 [ 106.947175] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.957270] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 106.957396] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.967192] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 [ 106.967302] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.977266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 106.977384] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.987258] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 [ 106.987375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 106.997153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 106.997219] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.007115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 [ 107.007163] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.017131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 107.017170] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.027157] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 [ 107.027207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.037124] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 [ 107.037163] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.047167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 107.047207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.057182] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 [ 107.057220] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.067150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 107.067189] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.077139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 [ 107.077188] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.087207] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 107.087243] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.097162] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 [ 107.097194] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.107134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 107.107180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.117148] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 [ 107.117184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.127131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 107.127176] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.137117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 [ 107.137152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.147141] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 107.147178] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.147365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000035459c5a [ 107.147421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.149200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bbab38cb [ 107.149262] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.157134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 107.157186] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.167144] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.167207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.177139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e [ 107.177180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.187196] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 [ 107.187274] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.197185] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.197235] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.207211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.207307] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.217287] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.217411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.227218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.227311] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.237176] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.237228] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.247200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.247267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.257213] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.257290] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.267196] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.267248] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.277184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.277241] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.287191] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.287262] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.297243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.297291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.309162] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.309214] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.319196] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.319256] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.329219] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.329288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.339184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.339252] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.349153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.349191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.359123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.359171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.369136] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 [ 107.369170] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.379109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 107.379152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.998833] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000056590bd0 [ 107.998848] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000080cfc270 state to 0000000056590bd0 [ 107.998859] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000158adbaf state to 0000000056590bd0 [ 107.998871] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000158adbaf [ 107.998882] [drm:drm_atomic_check_only [drm]] checking 0000000056590bd0 [ 107.998938] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 107.998958] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000056590bd0 nonblocking [ 107.998993] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006886a344 [ 107.999004] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bae29b57 state to 000000006886a344 [ 107.999013] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002901bd51 state to 000000006886a344 [ 107.999024] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000002901bd51 [ 107.999034] [drm:drm_atomic_check_only [drm]] checking 000000006886a344 [ 107.999072] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 107.999090] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006886a344 nonblocking [ 108.030368] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000056590bd0 [ 108.030383] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000056590bd0 [ 108.035497] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006886a344 [ 108.035511] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006886a344 [ 112.219065] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 112.219103] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 113.003417] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e437d9b1 [ 113.003430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ffeb4101 state to 00000000e437d9b1 [ 113.003440] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c6c81551 state to 00000000e437d9b1 [ 113.003450] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ffeb4101 to [NOCRTC] [ 113.003459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ffeb4101 [ 113.003470] [drm:drm_atomic_check_only [drm]] checking 00000000e437d9b1 [ 113.003514] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 113.003528] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000027864345 state to 00000000e437d9b1 [ 113.003549] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 113.003566] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 113.003582] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 113.003598] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 113.003608] [drm:drm_atomic_commit [drm]] committing 00000000e437d9b1 [ 113.003647] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e437d9b1 [ 113.003663] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e437d9b1 [ 118.152150] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006ab1917d [ 118.152201] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007f2e9b45 state to 000000006ab1917d [ 118.152243] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000614b5ce state to 000000006ab1917d [ 118.152286] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007f2e9b45 to [CRTC:51:pipe A] [ 118.152323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 [ 118.152362] [drm:drm_atomic_check_only [drm]] checking 000000006ab1917d [ 118.152506] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 118.152561] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e2798a03 state to 000000006ab1917d [ 118.152644] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 118.152717] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 118.152785] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 118.152852] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 118.152896] [drm:drm_atomic_commit [drm]] committing 000000006ab1917d [ 118.153029] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006ab1917d [ 118.153068] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006ab1917d [ 118.211570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 118.211702] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.221496] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fe3a22f0 [ 118.221630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.231475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 118.231610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.241492] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fe3a22f0 [ 118.241626] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.251361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 [ 118.251500] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.261486] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fe3a22f0 [ 118.261624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.271461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.271591] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.281458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.281594] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.291544] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.291670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.301470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.301610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.311473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.311605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.321455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.321595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.331448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.331575] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.341472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.341608] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.351430] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.351563] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.361455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.361597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.371478] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.371609] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.381444] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.381580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.391455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.391584] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.401319] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.401459] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.411530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.411658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.421455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.421593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.431467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 [ 118.431595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.432097] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009bdf158a [ 118.432246] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.436826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 [ 118.436961] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.441244] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.441371] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.451290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.451442] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.461385] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.461544] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.471242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.471340] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.481218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.481297] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.491325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.491469] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.501336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.501464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.511201] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.511286] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.521282] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.521422] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.531256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.531363] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.541365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.541527] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.551421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.551612] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.561422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.561626] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.571460] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.571668] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.581305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.581436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.591429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.591614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.601286] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.601427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.611450] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.611595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.621470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 118.621606] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 118.631489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 118.631623] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 119.225511] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000685c0b37 [ 119.225580] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007880e175 state to 00000000685c0b37 [ 119.225622] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005a9a925a state to 00000000685c0b37 [ 119.225664] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007880e175 to [NOCRTC] [ 119.225701] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000007880e175 [ 119.225739] [drm:drm_atomic_check_only [drm]] checking 00000000685c0b37 [ 119.225870] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 119.225921] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001da1458b state to 00000000685c0b37 [ 119.226002] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 119.226072] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 119.226138] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 119.226202] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 119.226243] [drm:drm_atomic_commit [drm]] committing 00000000685c0b37 [ 119.226379] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000685c0b37 [ 119.226421] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000685c0b37 [ 122.315481] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006886a344 [ 122.315493] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000568d4c state to 000000006886a344 [ 122.315503] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000c0a9ee8 state to 000000006886a344 [ 122.315525] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000000568d4c to [CRTC:51:pipe A] [ 122.315533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c [ 122.315541] [drm:drm_atomic_check_only [drm]] checking 000000006886a344 [ 122.315580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 122.315596] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000009bed8e52 state to 000000006886a344 [ 122.315616] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 122.315631] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 122.315646] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 122.315660] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 122.315669] [drm:drm_atomic_commit [drm]] committing 000000006886a344 [ 122.315710] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006886a344 [ 122.315722] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006886a344 [ 122.375447] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.375512] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.385420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.385514] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.395457] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.395593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.405500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.405638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.415533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.415670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.425503] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.425638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.435376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.435507] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.445489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.445628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.455488] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.455625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.465493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.465631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.475551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.475684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.485474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.485611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.495551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.495684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.505507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.505645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.515543] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.515675] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.525494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.525624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.535385] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.535515] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.545498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 [ 122.545633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.546132] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004af5af33 [ 122.546275] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.550766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd [ 122.550966] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.555297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.555491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.565289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.565468] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.575437] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.575649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.585311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.585474] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.595309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.595486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.605288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.605465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.615395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.615532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.625404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.625565] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.635310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.635442] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.645367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.645525] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.655318] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.655370] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.665309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.665417] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.675298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.675415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.685454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.685679] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.695368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.695517] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.705448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.705645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.715392] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.715588] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.725438] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.725646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.735369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.735505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.745500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.745640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.755529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.755663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.765337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.765470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.775249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.775378] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.785251] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.785375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.805153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe [ 122.805208] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 122.825138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 122.825177] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 123.640446] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000daeee49c [ 123.640511] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002bd9c591 state to 00000000daeee49c [ 123.640555] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007c9cb52f state to 00000000daeee49c [ 123.640597] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000002bd9c591 to [NOCRTC] [ 123.640633] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002bd9c591 [ 123.640671] [drm:drm_atomic_check_only [drm]] checking 00000000daeee49c [ 123.640810] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 123.640865] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c94fae9e state to 00000000daeee49c [ 123.640957] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 123.641028] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 123.641095] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 123.641172] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 123.641213] [drm:drm_atomic_commit [drm]] committing 00000000daeee49c [ 123.641343] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000daeee49c [ 123.641384] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000daeee49c [ 141.078241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005f403807 [ 141.078301] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000037fd6bb5 state to 000000005f403807 [ 141.078343] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d785a3ff state to 000000005f403807 [ 141.078387] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000037fd6bb5 to [CRTC:51:pipe A] [ 141.078425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000037fd6bb5 [ 141.078464] [drm:drm_atomic_check_only [drm]] checking 000000005f403807 [ 141.078605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 141.078659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cf223f59 state to 000000005f403807 [ 141.078742] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 141.078815] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 141.078884] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 141.078951] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 141.078994] [drm:drm_atomic_commit [drm]] committing 000000005f403807 [ 141.079121] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005f403807 [ 141.079161] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005f403807 [ 141.107538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.107620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.117497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.117630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.127474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.127612] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.137491] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.137625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.147568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.147705] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.157364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.157499] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.167567] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.167705] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.177487] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.177624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.187485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.187617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.193485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.193628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.203485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.203622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.214506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.214643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.223478] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.223611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.233209] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.233263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.243516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.243588] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.253441] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.253542] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.263521] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.263656] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.275556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.275692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.285356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.285495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.295568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.295709] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.305494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.305633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.315515] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.315648] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.325495] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 [ 141.325631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.335367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cea88f98 [ 141.335505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.345454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 [ 141.345586] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.346101] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e7418dfc [ 141.346276] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.355141] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cea88f98 [ 141.355189] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.365147] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb [ 141.365194] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.375197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cea88f98 [ 141.375275] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.380369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001c7ca7f0 [ 141.380409] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.385246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb [ 141.385295] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.395288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 141.395358] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.405301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb [ 141.405362] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.415276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 [ 141.415341] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.425309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb [ 141.425390] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.435298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e [ 141.435413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.445404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 [ 141.445562] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.455423] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e [ 141.455581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.465409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 [ 141.465566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.475410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e [ 141.475566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.485376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 [ 141.485535] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.495337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e [ 141.495482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.505402] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 [ 141.505569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.515416] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e [ 141.515598] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.525379] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 [ 141.525533] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.535346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e [ 141.535521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.545387] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 [ 141.545546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 141.616461] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 [ 141.616535] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000036a79273 state to 00000000f9a25c26 [ 141.616600] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001a688f4f state to 00000000f9a25c26 [ 141.616671] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000036a79273 to [NOCRTC] [ 141.616734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000036a79273 [ 141.616797] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 [ 141.616990] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 141.617070] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000347b066 state to 00000000f9a25c26 [ 141.617214] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 141.617361] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 141.617502] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 141.617642] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 141.617718] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 [ 141.617930] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 [ 141.618018] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 [ 142.420971] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 142.421067] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 162.373184] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 [ 162.373240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000446d08f state to 00000000f9a25c26 [ 162.373284] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f53352ac state to 00000000f9a25c26 [ 162.373326] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000000446d08f to [CRTC:51:pipe A] [ 162.373364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f [ 162.373405] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 [ 162.373543] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 162.373604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031204d92 state to 00000000f9a25c26 [ 162.373687] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 162.373759] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 162.373828] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 162.373895] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 162.373938] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 [ 162.374065] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 [ 162.374105] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 [ 162.412539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.412677] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.422500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.422637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.432369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.432523] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.442503] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.442633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.452374] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.452534] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.462502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.462639] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.472522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.472657] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.482493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.482629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.492573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.492706] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.502330] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.502470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.512587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.512722] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.524571] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.524709] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.534493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.534628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.544376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.544545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.554495] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.554628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.564566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 [ 162.564705] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.565166] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000587edb49 [ 162.565305] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.569116] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eb35d02a [ 162.569249] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.574136] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.574187] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.584146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.584195] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.594234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.594303] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.604214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.604270] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.614257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.614315] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.624366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.624535] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.634314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.634358] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.644386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.644533] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.654324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.654411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.664456] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.664686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.674345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.674484] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.684450] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.684647] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.696485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.696691] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.702435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.702636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.712353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.712616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.722404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.722602] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.732474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.732733] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.742357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.742494] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.752401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.752654] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.762467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.762603] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.772538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.772670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.782490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 [ 162.782619] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.792604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 [ 162.792735] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 162.792821] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039732f38 [ 162.792870] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000077bb1be state to 0000000039732f38 [ 162.792916] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005e067cfa state to 0000000039732f38 [ 162.792960] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000077bb1be to [CRTC:72:pipe B] [ 162.793002] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000077bb1be [ 162.793047] [drm:drm_atomic_check_only [drm]] checking 0000000039732f38 [ 162.793170] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 [ 162.793229] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000024b64037 state to 0000000039732f38 [ 162.793312] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 162.793386] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 162.793457] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 162.793529] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 162.793574] [drm:drm_atomic_commit [drm]] committing 0000000039732f38 [ 162.793714] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039732f38 [ 162.793764] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039732f38 [ 162.794202] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005fdb65d [ 162.794252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c739c83e state to 0000000005fdb65d [ 162.794296] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b35cdb13 state to 0000000005fdb65d [ 162.794338] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c739c83e to [NOCRTC] [ 162.794375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c739c83e [ 162.794414] [drm:drm_atomic_check_only [drm]] checking 0000000005fdb65d [ 162.794531] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 162.794581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cf223f59 state to 0000000005fdb65d [ 162.794662] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 162.794735] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 162.794802] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 162.794869] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 162.794912] [drm:drm_atomic_commit [drm]] committing 0000000005fdb65d [ 162.795027] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005fdb65d [ 162.795069] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005fdb65d [ 162.795125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 [ 162.795237] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 162.802263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 162.802383] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 162.812558] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 [ 162.812693] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 162.826474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 162.826607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 162.836357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 [ 162.836524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 162.837177] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000ffeb4101 [ 162.837329] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 162.841039] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 [ 162.841094] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006723bfc6 state to 00000000f9a25c26 [ 162.841132] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 [ 162.841187] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031204d92 state to 00000000f9a25c26 [ 162.841230] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 [ 162.850260] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 [ 162.850315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 162.850349] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 [ 162.850478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 162.850548] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 [ 162.850590] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000164d9b7a state to 00000000f9a25c26 [ 162.850622] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 [ 162.850668] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000eb35d02a state to 00000000f9a25c26 [ 162.850706] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 [ 162.855668] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 [ 162.855724] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 [ 163.084554] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.084691] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.094298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 163.094430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.104289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.104429] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.114472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 163.114610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.124320] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.124457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.134242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 163.134366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.144247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.144371] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.154294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 163.154423] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.164304] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.164446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.174288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 163.174420] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.174937] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000209127dd [ 163.175089] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.179030] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.179083] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000010dc5853 state to 00000000be7b5d5a [ 163.179121] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.179173] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007bfc2d05 state to 00000000be7b5d5a [ 163.179219] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.183630] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.183680] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.183762] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.183810] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c0b4aeaa state to 00000000be7b5d5a [ 163.183846] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.183895] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002901bd51 state to 00000000be7b5d5a [ 163.183938] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.188875] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.188930] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.189059] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.189102] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.190572] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.190623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000c0a9ee8 state to 00000000be7b5d5a [ 163.190661] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.190712] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000bd435351 state to 00000000be7b5d5a [ 163.190754] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.200278] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.200329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 163.200462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.200504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.200614] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.200675] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000025c16090 state to 00000000be7b5d5a [ 163.200708] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.200755] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007bfc2d05 state to 00000000be7b5d5a [ 163.200795] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.205520] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.205574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.205697] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.205740] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.214356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 163.214554] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.224571] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.224821] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.234254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 163.234361] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.244345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.244519] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.254382] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 163.254560] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.264229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 163.264326] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.280340] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b4820d38 [ 163.280404] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.282204] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000001da1458b [ 163.282256] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.284167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 163.284205] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.344181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.344296] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.364377] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.364426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.384493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.384575] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.394307] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.394438] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.404254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.404369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.414256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.414374] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.424270] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.424393] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.434269] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.434392] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.444299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.444435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.454316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.454440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.464222] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.464313] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.474216] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.474278] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.484241] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.484286] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.494263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.494347] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.504245] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.504314] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.514209] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.514276] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.524212] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.524268] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.534243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.534290] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.544309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 [ 163.544448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.552285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007b42b813 [ 163.552334] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.554208] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.554281] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.564224] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 163.564295] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.574166] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.574229] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.584233] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 163.584288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.594160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.594238] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.604200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 163.604269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.614168] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.614216] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.616918] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.616952] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000bae29b57 state to 00000000be7b5d5a [ 163.616971] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.617000] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002901bd51 state to 00000000be7b5d5a [ 163.617023] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.633795] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.633819] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.633836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 163.633879] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.633938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.633954] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000080cfc270 state to 00000000be7b5d5a [ 163.633966] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.633988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000bd435351 state to 00000000be7b5d5a [ 163.634002] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.638759] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.638776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.638830] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.638849] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.641820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.641848] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000010dc5853 state to 00000000be7b5d5a [ 163.641866] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.641894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007bfc2d05 state to 00000000be7b5d5a [ 163.641919] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.650229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.650244] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.650260] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 163.650301] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.650356] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a [ 163.650372] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c0b4aeaa state to 00000000be7b5d5a [ 163.650384] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a [ 163.650401] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002901bd51 state to 00000000be7b5d5a [ 163.650414] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a [ 163.655440] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a [ 163.655459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 [ 163.655472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a [ 163.655522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.664185] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 [ 163.664267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.674174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 163.674227] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.684271] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 [ 163.684368] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.694235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 163.694314] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.716235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 [ 163.716316] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.746263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 163.746311] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.786322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 163.786444] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.796558] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 163.796732] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.806376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 163.806516] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.816289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 163.816430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.824360] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 163.824500] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.834302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 163.834431] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.844210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 163.844334] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.854306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 163.854429] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.864293] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 163.864421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.874316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 [ 163.874446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.894337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cde16ff8 [ 163.894471] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.904283] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 163.904433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.914493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 163.914633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.924325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 163.924456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.934489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 163.934625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.944593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 163.944734] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.953688] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bd435351 [ 163.953820] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.954247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 163.954361] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.974321] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f [ 163.974458] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 163.994386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 163.994437] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.002341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000825c5808 [ 164.002399] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.014429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 164.014487] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.044329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 164.044410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.214575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 164.214713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.264599] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 164.264739] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.374516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 164.374649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.393776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb [ 164.393946] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.394313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000db85fe38 [ 164.394431] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.434448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000002a4c0c42 [ 164.434584] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.554295] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000db85fe38 [ 164.554421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 164.564820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bbab38cb [ 164.564985] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 165.034734] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005fdb65d [ 165.034787] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001450a92b state to 0000000005fdb65d [ 165.034827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007a36128c state to 0000000005fdb65d [ 165.034869] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000007a36128c [ 165.034909] [drm:drm_atomic_check_only [drm]] checking 0000000005fdb65d [ 165.035059] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 165.035120] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000005fdb65d nonblocking [ 165.035217] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000023b91fcc [ 165.035276] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003cd98772 state to 0000000023b91fcc [ 165.035334] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000db85fe38 state to 0000000023b91fcc [ 165.035381] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000db85fe38 [ 165.035417] [drm:drm_atomic_check_only [drm]] checking 0000000023b91fcc [ 165.035581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 165.035648] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000023b91fcc nonblocking [ 165.066992] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005fdb65d [ 165.067043] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005fdb65d [ 165.072198] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000023b91fcc [ 165.072271] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000023b91fcc [ 165.186505] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 165.186637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 165.193125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d4543e4a [ 165.193254] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 165.226330] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006506bed9 [ 165.226461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 165.559366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000922e52d2 [ 165.559409] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.198591] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.198728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.208274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.208427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.218301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.218420] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.228529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.228668] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.238482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.238613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.248312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.248448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.258354] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.258495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.268277] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.268411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.278371] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.278499] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.288245] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.288379] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.298279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.298399] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.308485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.308661] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.318507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.318641] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.328332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.328470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.338492] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.338629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.348315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.348443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.358336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.358482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.368340] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.368476] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.378281] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.378408] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.388609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.388746] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.398501] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.398637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.408591] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.408735] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.418335] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.418467] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.428298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.428427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.438508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.438645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.448320] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.448451] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.458413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.458546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.468336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.468471] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.478286] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.478413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.488310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.488437] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.498485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.498618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.508309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 166.508436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.510409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000009ad673f7 [ 166.510568] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.518309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.518443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.528202] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.528279] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.538201] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f [ 166.538251] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.548174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 166.548225] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.558268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 166.558443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.568325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 166.568466] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.578325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 166.578461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.588292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 166.588425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.598243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 166.598339] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.608234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 166.608325] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.618305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 166.618440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.628243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 166.628370] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.638472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 166.638607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.648346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 166.648472] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.658304] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 [ 166.658435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.668200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.668266] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.678440] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 166.678510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.688538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.688612] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.698392] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 166.698462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.718507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.718644] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.738502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 166.738635] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.798352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.798491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.918347] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 166.918485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.928302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.928430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.938357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 166.938493] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.948336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.948520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.958328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 166.958461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.968326] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.968512] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.980579] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 166.980746] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 166.990348] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 166.990503] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.000335] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.000513] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.010297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 167.010432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.020339] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.020482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.030319] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 167.030478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.040275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.040405] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.048710] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000009bed8e52 [ 167.048845] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.050289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 167.050415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.060268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.060398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.070294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 167.070384] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.080251] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.080344] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.088239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 [ 167.088330] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.098201] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001da1458b [ 167.098336] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.098523] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.098643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.108239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f [ 167.108334] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.118273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.118405] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.128501] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f [ 167.128614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.131207] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000009aed900f [ 167.131301] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.138279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.138369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.148267] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 167.148366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.158284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.158410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.168298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 167.168438] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.178446] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 167.178586] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.188561] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 167.188697] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.198352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 167.198491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.208264] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 167.208388] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.218455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 167.218593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.228299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 167.228428] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.238268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 167.238390] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.248278] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 167.248403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.258438] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 167.258577] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.268293] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 167.268425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.278483] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 167.278616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.288588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 167.288718] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.298353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 167.298492] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.305607] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 167.305696] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 167.308291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.308419] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.318288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 167.318416] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.338474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 [ 167.338607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.358489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 [ 167.358625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 167.418431] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 167.418566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 169.189257] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 169.189356] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 170.722681] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 170.722781] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 174.105940] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 174.105971] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 177.239718] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 177.239826] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 179.073151] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 179.073248] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 179.539621] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 179.539709] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 180.939876] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 181.556405] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 181.556493] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 183.573184] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 183.573274] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 184.723475] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 184.723574] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 185.023495] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 185.023591] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 186.190028] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 186.190120] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 186.806925] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 186.807022] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 187.140278] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 187.140374] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 188.556970] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 188.557072] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 196.710472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.710606] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.720275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.720400] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.730361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.730503] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.740292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.740426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.750290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.750418] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.760164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.760206] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.770148] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.770206] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.780499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.780634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.790477] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.790611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.810349] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.810482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.820270] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.820399] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.830365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.830507] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.840325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.840459] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.850300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.850424] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.860274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.860395] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.870281] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.870401] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.880273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.880397] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.890286] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.890412] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.900295] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.900423] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.910278] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.910406] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.920282] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.920403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.940275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.940403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.960275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 196.960398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 196.980269] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 196.980395] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 197.000256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 197.000379] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 197.020490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 197.020629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 197.030324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 197.030452] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 197.490874] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 197.490997] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 198.357316] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 198.357343] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 198.840664] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 198.840681] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 199.324033] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 199.324062] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 199.354350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b9b497e2 [ 199.354389] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 201.057610] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 201.057742] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 202.691169] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 202.691299] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 204.448344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 [ 204.448482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.458388] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c [ 204.458526] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.465902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 [ 204.466039] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.468343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f62f4859 [ 204.468525] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.478222] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b30bcde6 [ 204.478278] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.488310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f62f4859 [ 204.488357] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.498181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b30bcde6 [ 204.498258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.498534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a3057dc4 [ 204.498581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.508268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 [ 204.508329] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.518263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b30bcde6 [ 204.518345] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.528507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 [ 204.528590] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.538373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b30bcde6 [ 204.538504] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.548353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 [ 204.548526] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.548878] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007696cdb5 [ 204.548996] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.558432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b30bcde6 [ 204.558479] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.565739] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004ca3e431 [ 204.565873] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.568331] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c [ 204.568454] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.578458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006912db03 [ 204.578593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.588351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c [ 204.588486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.598370] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006912db03 [ 204.598509] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.608300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c [ 204.608432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.615008] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fe3a22f0 [ 204.615136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.618338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cf223f59 [ 204.618500] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.628289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 [ 204.628417] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.632195] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffeb4101 [ 204.632327] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.648396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 [ 204.648566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.658313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 204.658447] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.678279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 [ 204.678409] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.698323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 204.698464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.718329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 [ 204.718469] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.738316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000dcf9b2a1 [ 204.738448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.748362] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 204.748492] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.768326] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000922e52d2 [ 204.768453] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.778287] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 204.778414] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.788473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000922e52d2 [ 204.788600] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.798291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001acc1fa3 [ 204.798419] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.808487] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000922e52d2 [ 204.808618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.815138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000092affbec [ 204.815294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.818341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cf223f59 [ 204.818524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.828359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b9f6ed2f [ 204.828545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.838330] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cf223f59 [ 204.838469] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.848390] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b9f6ed2f [ 204.848541] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.848960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cd4c0663 [ 204.849109] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.858312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006912db03 [ 204.858447] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.868343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 [ 204.868480] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.878307] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007445155b [ 204.878441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.881982] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 204.882116] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.888331] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b [ 204.888465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.898303] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 204.898440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.908318] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b [ 204.908451] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.918320] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 204.918450] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.938328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b [ 204.938465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.958470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 204.958605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.978352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b [ 204.978491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 204.998371] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 204.998556] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.001389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000fd13abdd [ 205.001522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.018351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007445155b [ 205.018532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.038351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000444592af [ 205.038481] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.068339] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.068479] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.088481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf [ 205.088617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.108530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.108662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.128532] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf [ 205.128669] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.148343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.148521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.168306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf [ 205.168443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.188473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.188611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.208542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf [ 205.208683] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.230360] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.230498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.246443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf [ 205.246622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.265397] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a3057dc4 [ 205.265563] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.266346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.266465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.286348] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003cdbbe01 [ 205.286489] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.306389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.306531] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.330329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003cdbbe01 [ 205.330464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.348313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ffb1c30d [ 205.348467] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.348956] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bd435351 [ 205.349098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.379469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003cdbbe01 [ 205.379605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.418302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000919acba8 [ 205.418470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.468395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003cdbbe01 [ 205.468531] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.481838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007a57587a [ 205.481983] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.798479] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000919acba8 [ 205.798617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.803775] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000209127dd [ 205.803902] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.858576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 [ 205.858713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.891292] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 205.891418] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 205.898383] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb [ 205.898521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 205.958585] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 [ 205.958718] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 206.098587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb [ 206.098727] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 206.640585] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 [ 206.640683] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 206.700510] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb [ 206.700648] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 206.770448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 [ 206.770585] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 207.053512] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 207.053611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 207.310459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b [ 207.310589] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 209.041306] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 209.041387] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 209.124871] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 209.125001] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 209.241320] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 209.241452] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 211.658353] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 211.658482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 213.091482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 213.091505] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 213.625128] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 213.625263] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 217.492020] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 217.492164] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 223.609034] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 223.609177] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 226.792505] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 226.792643] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 231.176075] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 231.176218] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 231.542819] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 231.542950] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 231.976181] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 231.976317] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 237.426491] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 237.426628] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 238.293205] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 238.293327] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 239.576613] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 239.576751] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 242.443341] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 242.443474] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 244.510032] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 246.593680] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 246.593814] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 247.943758] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 247.943891] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 248.310445] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 248.310575] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 257.060944] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 257.061081] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 264.077820] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 264.077959] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 266.428065] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 266.428196] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 270.261496] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 270.261629] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 271.428241] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 275.562001] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 275.562106] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 276.595394] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 276.595493] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 281.612158] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 281.612255] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 288.579413] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 288.579517] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 292.596309] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 292.596419] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 296.546344] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 296.546450] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 297.446586] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 297.446682] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 299.696715] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 299.696817] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 300.246745] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 300.246841] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 301.763500] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 301.763596] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 302.113314] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 302.113407] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 303.296919] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 303.297018] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 304.513662] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 304.513760] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 307.330490] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 307.330600] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 310.580465] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 310.580565] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 316.297662] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 316.297769] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 317.047628] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 317.047703] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 319.697854] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 319.697958] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 321.647745] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 321.647843] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 322.764591] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 322.764694] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 323.781427] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 323.781524] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 323.831427] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 323.831523] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 326.231565] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 326.231663] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 329.281738] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 329.281845] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 329.948253] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 329.948347] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 331.298519] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 331.298616] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 333.331975] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 333.332082] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 334.795068] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000072ce196 [ 334.795080] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007b516bb0 state to 00000000072ce196 [ 334.795091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b9f6ed2f state to 00000000072ce196 [ 334.795101] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000b9f6ed2f [ 334.795110] [drm:drm_atomic_check_only [drm]] checking 00000000072ce196 [ 334.795147] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 334.795163] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000072ce196 nonblocking [ 334.795210] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000030d0d581 [ 334.795220] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d785a3ff state to 0000000030d0d581 [ 334.795228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007c47dfc7 state to 0000000030d0d581 [ 334.795237] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000007c47dfc7 [ 334.795246] [drm:drm_atomic_check_only [drm]] checking 0000000030d0d581 [ 334.795312] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 334.795325] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000030d0d581 nonblocking [ 334.815151] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000030d0d581 [ 334.815167] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000030d0d581 [ 334.826605] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000072ce196 [ 334.826620] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000072ce196 [ 335.194808] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 [ 335.194821] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c56546ad state to 00000000a311e694 [ 335.194830] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031204d92 state to 00000000a311e694 [ 335.194840] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000031204d92 [ 335.194848] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 [ 335.194907] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 335.194924] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a311e694 nonblocking [ 335.194961] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ca04647c [ 335.194970] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002822e6ce state to 00000000ca04647c [ 335.194978] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000bd3cbac4 state to 00000000ca04647c [ 335.194987] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000bd3cbac4 [ 335.194995] [drm:drm_atomic_check_only [drm]] checking 00000000ca04647c [ 335.195025] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 335.195043] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ca04647c nonblocking [ 335.215172] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ca04647c [ 335.215186] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ca04647c [ 335.226657] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 [ 335.226670] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 [ 338.015377] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 338.015451] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 339.415470] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 339.944709] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055a34068 [ 339.944724] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000080cfc270 state to 0000000055a34068 [ 339.944736] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059907653 state to 0000000055a34068 [ 339.944748] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000059907653 [ 339.944762] [drm:drm_atomic_check_only [drm]] checking 0000000055a34068 [ 339.944816] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 339.944835] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000055a34068 nonblocking [ 339.944878] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005d1b0ba1 [ 339.944889] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c0b4aeaa state to 000000005d1b0ba1 [ 339.944900] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b467cabb state to 000000005d1b0ba1 [ 339.944911] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000b467cabb [ 339.944921] [drm:drm_atomic_check_only [drm]] checking 000000005d1b0ba1 [ 339.944970] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 339.944985] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005d1b0ba1 nonblocking [ 339.965419] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005d1b0ba1 [ 339.965435] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005d1b0ba1 [ 339.976869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055a34068 [ 339.976882] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055a34068 [ 340.092434] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fd9f3f13 [ 340.092486] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007c9cb52f state to 00000000fd9f3f13 [ 340.092526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001fb03d75 state to 00000000fd9f3f13 [ 340.092568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000001fb03d75 [ 340.092607] [drm:drm_atomic_check_only [drm]] checking 00000000fd9f3f13 [ 340.092794] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 [ 340.092869] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fd9f3f13 nonblocking [ 340.092992] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000026cdbbf8 [ 340.093031] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000b21b516a state to 0000000026cdbbf8 [ 340.093066] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000068ed95b2 state to 0000000026cdbbf8 [ 340.093105] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000068ed95b2 [ 340.093140] [drm:drm_atomic_check_only [drm]] checking 0000000026cdbbf8 [ 340.093266] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 [ 340.093323] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000026cdbbf8 nonblocking [ 340.110397] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fd9f3f13 [ 340.110444] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fd9f3f13 [ 340.115690] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000026cdbbf8 [ 340.115773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000026cdbbf8 [ 342.565703] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 342.565827] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 344.599279] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 344.599405] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 345.965958] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 345.966085] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 348.116149] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 348.116281] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 350.132928] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 350.133053] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 353.932944] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 353.933067] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 355.183111] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 355.183235] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 357.383343] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 357.383471] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 357.516488] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 357.516606] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 360.083402] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 360.083527] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 360.333317] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 360.333438] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 360.666861] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 360.666983] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 362.883659] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 362.883789] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 376.551105] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 376.551238] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 377.984452] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 377.984580] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 380.084572] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 380.084705] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 380.817966] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 380.818094] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 380.934689] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 380.934810] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 381.668065] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 381.668189] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 383.218154] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 383.218287] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 383.684846] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 383.684968] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 384.183653] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000000b4adf6f [ 384.183785] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.193259] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f5a85039 [ 384.193310] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.203350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000000b4adf6f [ 384.203414] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.213293] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f5a85039 [ 384.213382] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.223412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.223549] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.234408] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd [ 384.234546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.243375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.243509] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.253548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd [ 384.253686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.263372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.263503] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.273419] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd [ 384.273558] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.283420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.283559] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.303397] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd [ 384.303525] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.323391] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.323524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.333300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd [ 384.333424] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.343528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.343663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.353374] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd [ 384.353505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.363343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.363467] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.373404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd [ 384.373544] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 384.383515] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 [ 384.383652] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 386.118054] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 386.118095] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 386.368064] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 386.368086] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 386.534738] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 386.534760] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 386.851505] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 386.851579] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 387.034830] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 387.034903] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 387.201648] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 387.201751] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 388.535123] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 388.535222] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 [ 389.151261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003441ac2c [ 389.151332] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.161368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d5b9564c [ 389.161497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.171380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003441ac2c [ 389.171520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.181354] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d5b9564c [ 389.181483] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.191360] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003441ac2c [ 389.191491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.201291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d5b9564c [ 389.201415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.204571] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cde16ff8 [ 389.204695] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.211441] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003441ac2c [ 389.211573] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.221362] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ac527557 [ 389.221497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.231523] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003441ac2c [ 389.231660] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.241534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ac527557 [ 389.241670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.251526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003441ac2c [ 389.251654] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.255414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 [ 389.255545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.262582] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ac527557 [ 389.262716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.271369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b9b497e2 [ 389.271499] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.281579] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ac527557 [ 389.281715] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.282180] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 [ 389.282317] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.291370] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b9b497e2 [ 389.291497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.301572] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d269f013 [ 389.301701] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.311529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b9b497e2 [ 389.311664] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.321434] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d269f013 [ 389.321571] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.331543] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db481eed [ 389.331593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000060e05122 state to 00000000db481eed [ 389.331636] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008ce8e041 state to 00000000db481eed [ 389.331678] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000060e05122 to [CRTC:51:pipe A] [ 389.331717] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 0000000060e05122 [ 389.331756] [drm:drm_atomic_check_only [drm]] checking 00000000db481eed [ 389.331893] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 [ 389.331947] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002bd9c591 state to 00000000db481eed [ 389.332030] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm [ 389.332103] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 [ 389.332171] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 [ 389.332238] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 [ 389.332281] [drm:drm_atomic_commit [drm]] committing 00000000db481eed [ 389.332422] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db481eed [ 389.332462] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db481eed [ 389.332519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cd4c0663 [ 389.332629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.333062] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000c13c0ab2 [ 389.333180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.333247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000009ad771e5 [ 389.333357] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 [ 389.335824] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006ab1917d [ 389.335880] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7bb92f2 state to 000000006ab1917d [ 389.335918] [drm:drm_atomic_check_only [drm]] checking 000000006ab1917d [ 389.335975] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ed23d599 state to 000000006ab1917d [ 389.336020] [drm:drm_atomic_commit [drm]] committing 000000006ab1917d [ 389.346611] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006ab1917d [ 389.346667] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000d269f013 [ 389.346799] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.346842] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006ab1917d [ 389.346940] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db481eed [ 389.346985] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c94fae9e state to 00000000db481eed [ 389.347024] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007c9cb52f state to 00000000db481eed [ 389.347066] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000c94fae9e to [NOCRTC] [ 389.347102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c94fae9e [ 389.347142] [drm:drm_atomic_check_only [drm]] checking 00000000db481eed [ 389.347272] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 [ 389.347323] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ffeb4101 state to 00000000db481eed [ 389.347412] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 389.347484] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 389.347552] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 389.347620] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 389.347663] [drm:drm_atomic_commit [drm]] committing 00000000db481eed [ 389.347798] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db481eed [ 389.347857] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fd4b06be [ 389.347893] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db481eed [ 389.347949] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000925d662a state to 00000000fd4b06be [ 389.347989] [drm:drm_atomic_check_only [drm]] checking 00000000fd4b06be [ 389.348040] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000007ebffa5 state to 00000000fd4b06be [ 389.348083] [drm:drm_atomic_commit [drm]] committing 00000000fd4b06be [ 389.351742] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fd4b06be [ 389.351790] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fd4b06be [ 389.353402] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.353595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.360773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 0000000067b08824 [ 389.360912] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.363314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.363441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.373413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.373563] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.383342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.383433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.393312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.393383] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.403313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.403384] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.413444] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.413617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.423299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.423376] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.433429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.433579] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.443324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.443433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.453396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.453524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.463485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.463715] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.473438] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.473575] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.483524] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.483759] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.493424] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.493554] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.503451] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.503650] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.513409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.513542] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.523461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.523649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.533584] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.533720] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.543529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.543665] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.553561] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.553691] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.563508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.563642] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.573564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.573700] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.583443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.583581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.593579] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.593715] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.603525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.603661] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.613565] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.613694] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.623535] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.623669] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.633570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.633699] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.643522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.643655] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.653590] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.653773] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.663513] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.663650] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.673585] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 [ 389.673721] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 389.733576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 [ 389.733708] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 [ 390.576434] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db481eed [ 390.576484] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000068ed95b2 state to 00000000db481eed [ 390.576527] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b21b516a state to 00000000db481eed [ 390.576569] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000068ed95b2 to [NOCRTC] [ 390.576607] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000068ed95b2 [ 390.576645] [drm:drm_atomic_check_only [drm]] checking 00000000db481eed [ 390.576784] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 [ 390.576837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000039b49928 state to 00000000db481eed [ 390.576921] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm [ 390.576993] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 390.577061] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 390.577128] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 [ 390.577170] [drm:drm_atomic_commit [drm]] committing 00000000db481eed [ 390.577307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db481eed [ 390.577351] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db481eed From nixiaoming at huawei.com Thu Jun 4 08:45:20 2020 From: nixiaoming at huawei.com (Xiaoming Ni) Date: Thu, 4 Jun 2020 16:45:20 +0800 Subject: [Intel-gfx] [PATCH 13/13] fs: move binfmt_misc sysctl to its own file In-Reply-To: <20200529074108.16928-14-mcgrof@kernel.org> References: <20200529074108.16928-1-mcgrof@kernel.org> <20200529074108.16928-14-mcgrof@kernel.org> Message-ID: <6cbba430-a768-72db-bd45-bcbba0376219@huawei.com> On 2020/5/29 15:41, Luis Chamberlain wrote: > This moves the binfmt_misc sysctl to its own file to help remove > clutter from kernel/sysctl.c. > > Signed-off-by: Luis Chamberlain <mcgrof at kernel.org> > --- > fs/binfmt_misc.c | 1 + > kernel/sysctl.c | 7 ------- > 2 files changed, 1 insertion(+), 7 deletions(-) > > diff --git a/fs/binfmt_misc.c b/fs/binfmt_misc.c > index f69a043f562b..656b3f5f3bbf 100644 > --- a/fs/binfmt_misc.c > +++ b/fs/binfmt_misc.c > @@ -821,6 +821,7 @@ static int __init init_misc_binfmt(void) > int err = register_filesystem(&bm_fs_type); > if (!err) > insert_binfmt(&misc_format); > + register_sysctl_empty_subdir("fs", "binfmt_misc"); > return err; > } build error when CONFIG_BINFMT_MISC=m ERROR: modpost: "register_sysctl_empty_subdir" [fs/binfmt_misc.ko] undefined! diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 27f0c9ea..4129dfb 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -2853,6 +2853,7 @@ void register_sysctl_empty_subdir(const char *base, { register_sysctl_subdir(base, subdir, sysctl_mount_point); } +EXPORT_SYMBOL_GPL(register_sysctl_empty_subdir); #endif /* CONFIG_SYSCTL */ Thanks Xiaoming Ni From patchwork at emeril.freedesktop.org Thu Jun 4 13:15:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 13:15:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Exercise_all_copy_engines_with_the_blt_routi?= =?utf-8?q?nes_=28rev2=29?= In-Reply-To: <20200604102140.8845-1-chris@chris-wilson.co.uk> References: <20200604102140.8845-1-chris@chris-wilson.co.uk> Message-ID: <159127654688.14554.17341921798400321079@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise all copy engines with the blt routines (rev2) URL : https://patchwork.freedesktop.org/series/77994/ State : success == Summary == CI Bug Log - changes from CI_DRM_8581 -> Patchwork_17868 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/index.html Known issues ------------ Here are the changes found in Patchwork_17868 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * {igt at kms_flip@basic-plain-flip at d-dsi1}: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-dsi/igt at kms_flip@basic-plain-flip at d-dsi1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/fi-tgl-dsi/igt at kms_flip@basic-plain-flip at d-dsi1.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-tgl-y: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8581 -> Patchwork_17868 CI-20190529: 20190529 CI_DRM_8581: a3ae560b4c2a6dfb0d550cc40471a7b0c7043500 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17868: 9edabff31b225d1b8b4860cf92c7f19a1645c079 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9edabff31b22 drm/i915/selftests: Exercise all copy engines with the blt routines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 13:16:03 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 13:16:03 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBz?= =?utf-8?q?ysctl=3A_spring_cleaning_=28rev2=29?= In-Reply-To: <20200529074108.16928-1-mcgrof@kernel.org> References: <20200529074108.16928-1-mcgrof@kernel.org> Message-ID: <159127656372.14552.12310835096311921928@emeril.freedesktop.org> == Series Details == Series: sysctl: spring cleaning (rev2) URL : https://patchwork.freedesktop.org/series/77780/ State : failure == Summary == Applying: sysctl: add new register_sysctl_subdir() helper error: sha1 information is lacking or useless (include/linux/sysctl.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 sysctl: add new register_sysctl_subdir() helper When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From chris at chris-wilson.co.uk Thu Jun 4 13:23:05 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 14:23:05 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Trace HWSP cachelines Message-ID: <20200604132305.22089-1-chris@chris-wilson.co.uk> Trace the acquire/release of individual cachelines within the HWSP, so we can look back in anger. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_timeline.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c index 4546284fede1..efce02a6d69e 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.c +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c @@ -145,6 +145,10 @@ static void __cacheline_retire(struct i915_active *active) struct intel_timeline_cacheline *cl = container_of(active, typeof(*cl), active); + GT_TRACE(cl->hwsp->gt, "cacheline:%08lx retire\n", + i915_ggtt_offset(cl->hwsp->vma) + + ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES); + i915_vma_unpin(cl->hwsp->vma); if (ptr_test_bit(cl->vaddr, CACHELINE_FREE)) __idle_cacheline_free(cl); @@ -156,6 +160,11 @@ static int __cacheline_active(struct i915_active *active) container_of(active, typeof(*cl), active); __i915_vma_pin(cl->hwsp->vma); + + GT_TRACE(cl->hwsp->gt, "cacheline:%08lx active\n", + i915_ggtt_offset(cl->hwsp->vma) + + ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES); + return 0; } @@ -334,6 +343,9 @@ int intel_timeline_pin(struct intel_timeline *tl) __i915_vma_unpin(tl->hwsp_ggtt); } + GT_TRACE(tl->gt, "fence:%llx acquire hwsp:%08x\n", + tl->fence_context, tl->hwsp_offset); + return 0; } @@ -483,6 +495,9 @@ __intel_timeline_get_seqno(struct intel_timeline *tl, if (err) goto err_cacheline; + GT_TRACE(tl->gt, "fence:%llx release hwsp:%08x\n", + tl->fence_context, tl->hwsp_offset); + cacheline_release(tl->hwsp_cacheline); /* ownership now xfered to rq */ cacheline_free(tl->hwsp_cacheline); @@ -501,6 +516,9 @@ __intel_timeline_get_seqno(struct intel_timeline *tl, cacheline_acquire(cl); tl->hwsp_cacheline = cl; + GT_TRACE(tl->gt, "fence:%llx acquire hwsp:%08x\n", + tl->fence_context, tl->hwsp_offset); + *seqno = timeline_advance(tl); GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno)); return 0; @@ -576,6 +594,9 @@ void intel_timeline_unpin(struct intel_timeline *tl) if (!atomic_dec_and_test(&tl->pin_count)) return; + GT_TRACE(tl->gt, "fence:%llx release hwsp:%08x\n", + tl->fence_context, tl->hwsp_offset); + cacheline_release(tl->hwsp_cacheline); __i915_vma_unpin(tl->hwsp_ggtt); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 4 13:25:07 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 04 Jun 2020 14:25:07 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915/tgl: Implement WA_16011163337 In-Reply-To: <20200603221150.14745-1-clinton.a.taylor@intel.com> References: <20200603221150.14745-1-clinton.a.taylor@intel.com> Message-ID: <159127710726.25109.14710135033049757544@build.alporthouse.com> Quoting clinton.a.taylor at intel.com (2020-06-03 23:11:50) > From: Clint Taylor <clinton.a.taylor at intel.com> > > Set GS Timer to 224. Combine with Wa_1604555607 due to register FF_MODE2 > not being able to be read. > > V2: Math issue fixed > > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Caz Yokoyama <caz.yokoyama at intel.com> > Cc: Matt Atwood <matthew.s.atwood at intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com> Acked-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From matthew.william.auld at gmail.com Thu Jun 4 13:37:40 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Thu, 4 Jun 2020 14:37:40 +0100 Subject: [Intel-gfx] [PATCH 14/22] drm/i915/gem: Async GPU relocations only In-Reply-To: <20200604103751.18816-14-chris@chris-wilson.co.uk> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> <20200604103751.18816-14-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHM=qwi9h20Lu9JCz8KXPNJHo7ToUv63t9eADM-U9MZm9A@mail.gmail.com> On Thu, 4 Jun 2020 at 11:38, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Reduce the 3 relocation patches down to the single path that accommodates > all. The primary motivation for this is to guard the relocations with a > natural fence (derived from the i915_request used to write the > relocation from the GPU). > > The tradeoff in using async gpu relocations is that it increases latency > over using direct CPU relocations, for the cases where the target is > idle and accessible by the CPU. The benefit is greatly reduced lock > contention and improved concurrency by pipelining. > > Note that forcing the async gpu relocations does reveal a few issues > they have. Firstly, is that they are visible as writes to gem_busy, > causing to mark some buffers are being to written to by the GPU even > though userspace only reads. Secondly is that, in combination with the > cmdparser, they can cause priority inversions. This should be the case > where the work is being put into a common workqueue losing our priority > information and so being executed in FIFO from the worker, denying us > the opportunity to reorder the requests afterwards. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From chris at chris-wilson.co.uk Thu Jun 4 13:44:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 04 Jun 2020 14:44:23 +0100 Subject: [Intel-gfx] [PATCH 14/22] drm/i915/gem: Async GPU relocations only In-Reply-To: <CAM0jSHM=qwi9h20Lu9JCz8KXPNJHo7ToUv63t9eADM-U9MZm9A@mail.gmail.com> References: <20200604103751.18816-1-chris@chris-wilson.co.uk> <20200604103751.18816-14-chris@chris-wilson.co.uk> <CAM0jSHM=qwi9h20Lu9JCz8KXPNJHo7ToUv63t9eADM-U9MZm9A@mail.gmail.com> Message-ID: <159127826380.25109.18308915602088724728@build.alporthouse.com> Quoting Matthew Auld (2020-06-04 14:37:40) > On Thu, 4 Jun 2020 at 11:38, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > Reduce the 3 relocation patches down to the single path that accommodates > > all. The primary motivation for this is to guard the relocations with a > > natural fence (derived from the i915_request used to write the > > relocation from the GPU). > > > > The tradeoff in using async gpu relocations is that it increases latency > > over using direct CPU relocations, for the cases where the target is > > idle and accessible by the CPU. The benefit is greatly reduced lock > > contention and improved concurrency by pipelining. > > > > Note that forcing the async gpu relocations does reveal a few issues > > they have. Firstly, is that they are visible as writes to gem_busy, > > causing to mark some buffers are being to written to by the GPU even > > though userspace only reads. Secondly is that, in combination with the > > cmdparser, they can cause priority inversions. This should be the case > > where the work is being put into a common workqueue losing our priority > > information and so being executed in FIFO from the worker, denying us > > the opportunity to reorder the requests afterwards. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Reviewed-by: Matthew Auld <matthew.auld at intel.com> Fwiw, if anyone else is as concerned about the priority inversions via the global system workqueues as am I, we need to teach the CPU scheduler about our priorities. I am considering a per-CPU kthread and plugging them into our scheduling backend. That should be then be applicable to all our async tasks (clflushing, binding, pages, random other tasks). The devil is in the details of course. -Chris From chris at chris-wilson.co.uk Thu Jun 4 13:59:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 14:59:38 +0100 Subject: [Intel-gfx] [CI] drm/i915: Trim set_timer_ms() intervals Message-ID: <20200604135938.3975-1-chris@chris-wilson.co.uk> Use the plain msec_to_jiffies() rather than the _timeout variant so we round down and do not add an extra jiffy to our interval. For example, with timeslicing we do not want to err on the longer side as any fairness depends on catching hogging contexts on the GPU. Bring on CFS. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 29 +++++++++++--------------- drivers/gpu/drm/i915/i915_utils.c | 2 +- 2 files changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 3e35a45d6218..67d74e6432a8 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -1140,9 +1140,17 @@ static struct i915_request *nop_request(struct intel_engine_cs *engine) return rq; } -static long timeslice_threshold(const struct intel_engine_cs *engine) +static long slice_timeout(struct intel_engine_cs *engine) { - return 2 * msecs_to_jiffies_timeout(timeslice(engine)) + 1; + long timeout; + + /* Enough time for a timeslice to kick in, and kick out */ + timeout = 2 * msecs_to_jiffies_timeout(timeslice(engine)); + + /* Enough time for the nop request to complete */ + timeout += HZ / 5; + + return timeout + 1; } static int live_timeslice_queue(void *arg) @@ -1260,7 +1268,7 @@ static int live_timeslice_queue(void *arg) } /* Timeslice every jiffy, so within 2 we should signal */ - if (i915_request_wait(rq, 0, timeslice_threshold(engine)) < 0) { + if (i915_request_wait(rq, 0, slice_timeout(engine)) < 0) { struct drm_printer p = drm_info_printer(gt->i915->drm.dev); @@ -1379,7 +1387,7 @@ static int live_timeslice_nopreempt(void *arg) * allow the maximum priority barrier through. Wait long * enough to see if it is timesliced in by mistake. */ - if (i915_request_wait(rq, 0, timeslice_threshold(engine)) >= 0) { + if (i915_request_wait(rq, 0, slice_timeout(engine)) >= 0) { pr_err("%s: I915_PRIORITY_BARRIER request completed, bypassing no-preempt request\n", engine->name); err = -EINVAL; @@ -3890,19 +3898,6 @@ static int live_virtual_mask(void *arg) return 0; } -static long slice_timeout(struct intel_engine_cs *engine) -{ - long timeout; - - /* Enough time for a timeslice to kick in, and kick out */ - timeout = 2 * msecs_to_jiffies_timeout(timeslice(engine)); - - /* Enough time for the nop request to complete */ - timeout += HZ / 5; - - return timeout; -} - static int slicein_virtual_engine(struct intel_gt *gt, struct intel_engine_cs **siblings, unsigned int nsibling) diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c index e28eae4a8f70..f42a9e9a0b4f 100644 --- a/drivers/gpu/drm/i915/i915_utils.c +++ b/drivers/gpu/drm/i915/i915_utils.c @@ -91,7 +91,7 @@ void set_timer_ms(struct timer_list *t, unsigned long timeout) return; } - timeout = msecs_to_jiffies_timeout(timeout); + timeout = msecs_to_jiffies(timeout); /* * Paranoia to make sure the compiler computes the timeout before -- 2.20.1 From ville.syrjala at linux.intel.com Thu Jun 4 14:55:30 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 17:55:30 +0300 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <20200604145530.GS6112@intel.com> On Thu, Jun 04, 2020 at 12:10:38AM +0300, Imre Deak wrote: > Currently MST on a port can get enabled/disabled from the hotplug work > and get disabled from the short pulse work in a racy way. Fix this by > relying on the MST state checking in the hotplug work and just schedule > a hotplug work from the short pulse handler if some problem happened > during the MST interrupt handling. > > This removes the explicit MST disabling in case of an AUX failure, but > if AUX fails, then probably the detection will also fail during the > scheduled hotplug work and it's not guaranteed that we'll see > intermittent errors anyway. > > While at it also simplify the error checking of the MST interrupt > handler. > > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++---------------------- > 1 file changed, 4 insertions(+), 29 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 55fda074c0ad..befbcacddaa1 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5604,7 +5604,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) > } > } > > - return need_retrain; > + return need_retrain ? -EINVAL : 0; > } > > static bool > @@ -7255,35 +7255,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > } > > if (intel_dp->is_mst) { > - switch (intel_dp_check_mst_status(intel_dp)) { > - case -EINVAL: > - /* > - * If we were in MST mode, and device is not > - * there, get out of MST mode > - */ > - drm_dbg_kms(&i915->drm, > - "MST device may have disappeared %d vs %d\n", > - intel_dp->is_mst, > - intel_dp->mst_mgr.mst_state); > - intel_dp->is_mst = false; > - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > - intel_dp->is_mst); > - > - return IRQ_NONE; > - case 1: > - return IRQ_NONE; > - default: > - break; > - } > - } > - > - if (!intel_dp->is_mst) { > - bool handled; > - > - handled = intel_dp_short_pulse(intel_dp); > - > - if (!handled) > + if (intel_dp_check_mst_status(intel_dp) < 0) > return IRQ_NONE; Since we no longer need the tristate return, can you follow up with a conversion to bool return? I'd vote to make it match the semantics of intel_dp_short_pulse() so we get one step closer to unifying the hpd_irq handling across the board. > + } else if (!intel_dp_short_pulse(intel_dp)) { > + return IRQ_NONE; > } > > return IRQ_HANDLED; > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Thu Jun 4 15:02:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 15:02:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Trace_HWSP_cachelines?= In-Reply-To: <20200604132305.22089-1-chris@chris-wilson.co.uk> References: <20200604132305.22089-1-chris@chris-wilson.co.uk> Message-ID: <159128295519.14554.13111082927383132306@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Trace HWSP cachelines URL : https://patchwork.freedesktop.org/series/78000/ State : success == Summary == CI Bug Log - changes from CI_DRM_8583 -> Patchwork_17870 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/index.html Known issues ------------ Here are the changes found in Patchwork_17870 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * {igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1}: - fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at kms_force_connector_basic@force-connector-state: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#62] / [i915#92]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8583 -> Patchwork_17870 CI-20190529: 20190529 CI_DRM_8583: e147ef9bced964b97283851a519aea132a5613e6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17870: bb11ec0255995d1b00b7e3b7d4fad4f375d49c6b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bb11ec025599 drm/i915/gt: Trace HWSP cachelines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 15:03:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 15:03:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Exercise_all_copy_engines_with_the_blt_routi?= =?utf-8?q?nes_=28rev2=29?= In-Reply-To: <20200604102140.8845-1-chris@chris-wilson.co.uk> References: <20200604102140.8845-1-chris@chris-wilson.co.uk> Message-ID: <159128302995.14555.17337539674658542412@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise all copy engines with the blt routines (rev2) URL : https://patchwork.freedesktop.org/series/77994/ State : success == Summary == CI Bug Log - changes from CI_DRM_8581_full -> Patchwork_17868_full ==================================================== Summary ------- **SUCCESS** No regressions found. New tests --------- New tests have been introduced between CI_DRM_8581_full and Patchwork_17868_full: ### New IGT tests (11) ### * igt at gem_ctx_engines@execute-allforone: - Statuses : 7 pass(s) - Exec time: [0.00, 0.04] s * igt at gem_ctx_engines@execute-one: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.20, 4.60] s * igt at gem_ctx_engines@execute-oneforall: - Statuses : 7 pass(s) - Exec time: [0.06, 1.19] s * igt at gem_ctx_engines@idempotent: - Statuses : 6 pass(s) - Exec time: [0.00, 0.01] s * igt at gem_ctx_engines@independent: - Statuses : 1 dmesg-warn(s) 5 pass(s) 1 skip(s) - Exec time: [0.0, 0.32] s * igt at gem_ctx_engines@invalid-engines: - Statuses : 7 pass(s) - Exec time: [0.00, 0.01] s * igt at gem_ctx_shared@create-shared-gtt: - Statuses : 6 pass(s) - Exec time: [2.15, 2.16] s * igt at gem_ctx_shared@detached-shared-gtt: - Statuses : 7 pass(s) - Exec time: [2.15, 2.16] s * igt at gem_ctx_shared@disjoint-timelines: - Statuses : 2 dmesg-warn(s) 4 pass(s) 1 skip(s) - Exec time: [0.0, 0.09] s * igt at gem_ctx_shared@q-smoketest-all: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 32.47] s * igt at gem_ctx_shared@single-timeline: - Statuses : 6 pass(s) 1 skip(s) - Exec time: [0.0, 0.03] s Known issues ------------ Here are the changes found in Patchwork_17868_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-tglb8/igt at i915_module_load@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-tglb7/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-iclb8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-iclb3/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_big_fb@y-tiled-8bpp-rotate-0: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-apl6/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-apl6/igt at kms_big_fb@y-tiled-8bpp-rotate-0.html * igt at kms_cursor_edge_walk@pipe-b-256x256-right-edge: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl5/igt at kms_cursor_edge_walk@pipe-b-256x256-right-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl9/igt at kms_cursor_edge_walk@pipe-b-256x256-right-edge.html * igt at kms_draw_crc@fill-fb: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) +6 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-snb2/igt at kms_draw_crc@fill-fb.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-snb2/igt at kms_draw_crc@fill-fb.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl6/igt at kms_flip_tiling@flip-yf-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl4/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl4/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl2/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +12 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-apl8/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-apl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-iclb3/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_setmode@basic: - shard-apl: [PASS][25] -> [FAIL][26] ([i915#31]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-apl6/igt at kms_setmode@basic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-apl6/igt at kms_setmode@basic.html #### Possible fixes #### * igt at gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [DMESG-WARN][27] ([i915#118] / [i915#95]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-glk9/igt at gem_exec_whisper@basic-contexts-forked-all.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-glk8/igt at gem_exec_whisper@basic-contexts-forked-all.html * igt at gem_exec_whisper@basic-fds-forked-all: - shard-kbl: [INCOMPLETE][29] ([i915#1318]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-kbl7/igt at gem_exec_whisper@basic-fds-forked-all.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-kbl1/igt at gem_exec_whisper@basic-fds-forked-all.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-skl: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +5 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl6/igt at kms_big_fb@linear-32bpp-rotate-180.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl4/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-glk9/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_big_fb@y-tiled-32bpp-rotate-90: - shard-apl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-apl8/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-apl4/igt at kms_big_fb@y-tiled-32bpp-rotate-90.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][37] ([i915#300]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl10/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html - shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-apl1/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-apl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * {igt at kms_flip@flip-vs-suspend at a-dp1}: - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +5 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-kbl7/igt at kms_flip@flip-vs-suspend at a-dp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-kbl1/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +15 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][45] ([i915#69]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][47] ([fdo#108145] / [i915#265]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-iclb5/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][51] ([i915#173]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-iclb1/igt at kms_psr@no_drrs.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-iclb6/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-iclb6/igt at kms_psr@psr2_sprite_blt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][55] ([i915#31]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-kbl2/igt at kms_setmode@basic.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-kbl1/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-wait-busy: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-tglb8/igt at kms_vblank@pipe-c-wait-busy.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-tglb7/igt at kms_vblank@pipe-c-wait-busy.html #### Warnings #### * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [FAIL][59] ([i915#49]) -> [DMESG-FAIL][60] ([i915#49] / [i915#95]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8581/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1318]: https://gitlab.freedesktop.org/drm/intel/issues/1318 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#1780]: https://gitlab.freedesktop.org/drm/intel/issues/1780 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8581 -> Patchwork_17868 CI-20190529: 20190529 CI_DRM_8581: a3ae560b4c2a6dfb0d550cc40471a7b0c7043500 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17868: 9edabff31b225d1b8b4860cf92c7f19a1645c079 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17868/index.html From joonas.lahtinen at linux.intel.com Thu Jun 4 15:04:54 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Thu, 4 Jun 2020 18:04:54 +0300 Subject: [Intel-gfx] [PULL] drm-intel-next-fixes Message-ID: <20200604150454.GA59322@jlahtine-desk.ger.corp.intel.com> Hi Dave & Daniel, Fixes use-after free on display global state tracking. Then the removal of write bits from sysfs files where changed value is not reflected anywhere. Two scheduler fixes with deps that are Cc: stable. Includes the GVT pull which has two build warning fixes at this time. CI_DINF_194 at https://intel-gfx-ci.01.org/tree/drm-intel-next-fixes/combined-alt.html? Regards, Joonas *** drm-intel-next-fixes-2020-06-04: - Includes gvt-next-fixes-2020-05-28 - Use after free fix for display global state. - Whitelisting context-local timestamp on Gen9 and two scheduler fixes with deps (Cc: stable) - Removal of write flag from sysfs files where ineffective The following changes since commit d96536f0fe699729a0974eb5b65eb0d87cc747e1: drm/i915: Fix AUX power domain toggling across TypeC mode resets (2020-05-19 17:54:07 +0300) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2020-06-04 for you to fetch changes up to f8665d797b1ce9bd81f7ed7744ef3a18d6b186ea: Merge tag 'gvt-next-fixes-2020-05-28' of https://github.com/intel/gvt-linux into drm-intel-next-fixes (2020-06-02 16:45:06 +0300) ---------------------------------------------------------------- - Includes gvt-next-fixes-2020-05-28 - Use after free fix for display global state. - Whitelisting context-local timestamp on Gen9 and two scheduler fixes with deps (Cc: stable) - Removal of write flag from sysfs files where ineffective ---------------------------------------------------------------- Aishwarya Ramakrishnan (1): drm/i915/gvt: Use ARRAY_SIZE for vgpu_types Chris Wilson (9): drm/i915: Don't set queue-priority hint when supressing the reschedule drm/i915/gt: Remove errant assertion in __intel_context_do_pin drm/i915: Disable semaphore inter-engine sync without timeslicing drm/i915: Avoid using rq->engine after free during i915_fence_release drm/i915/gem: Avoid iterating an empty list drm/i915: Reorder await_execution before await_request drm/i915/gt: Do not schedule normal requests immediately along virtual drm/i915: Check for awaits on still currently executing requests drm/i915: Whitelist context-local timestamp in the gen9 cmdparser Jani Nikula (2): drm/i915/params: don't expose inject_probe_failure in debugfs drm/i915/params: fix i915.fake_lmem_start module param sysfs permissions Joonas Lahtinen (1): Merge tag 'gvt-next-fixes-2020-05-28' of https://github.com/intel/gvt-linux into drm-intel-next-fixes Nathan Chancellor (1): drm/i915: Mark check_shadow_context_ppgtt as maybe unused Ville Syrj?l? (1): drm/i915: Fix global state use-after-frees with a refcount drivers/gpu/drm/i915/display/intel_global_state.c | 45 ++- drivers/gpu/drm/i915/display/intel_global_state.h | 3 + drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 15 +- drivers/gpu/drm/i915/gt/intel_context.c | 2 - drivers/gpu/drm/i915/gvt/vgpu.c | 2 +- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 + drivers/gpu/drm/i915/i915_params.c | 2 +- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/i915_request.c | 359 ++++++++++++++-------- drivers/gpu/drm/i915/i915_scheduler.c | 16 +- 11 files changed, 295 insertions(+), 159 deletions(-) From jani.nikula at intel.com Thu Jun 4 15:05:03 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Thu, 4 Jun 2020 18:05:03 +0300 Subject: [Intel-gfx] [CI] drm/i915/params: switch to device specific parameters Message-ID: <20200604150503.17199-1-jani.nikula@intel.com> Start using device specific parameters instead of module parameters for most things. The module parameters become the immutable initial values for i915 parameters. The device specific parameters in i915->params start life as a copy of i915_modparams. Any later changes are only reflected in the debugfs. The stragglers are: * i915.force_probe and i915.modeset. Needed before dev_priv is available. This is fine because the parameters are read-only and never modified. * i915.verbose_state_checks. Passing dev_priv to I915_STATE_WARN and I915_STATE_WARN_ON would result in massive and ugly churn. This is handled by not exposing the parameter via debugfs, and leaving the parameter writable in sysfs. This may be fixed up in follow-up work. * i915.inject_probe_failure. Only makes sense in terms of the module, not the device. This is handled by not exposing the parameter via debugfs. Cc: Juha-Pekka Heikkil? <juha-pekka.heikkila at intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Jani Nikula <jani.nikula at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 6 ++--- drivers/gpu/drm/i915/display/intel_crt.c | 4 ++-- drivers/gpu/drm/i915/display/intel_csr.c | 6 ++--- drivers/gpu/drm/i915/display/intel_display.c | 12 +++++----- .../drm/i915/display/intel_display_debugfs.c | 2 +- .../drm/i915/display/intel_display_power.c | 14 ++++++------ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++--- .../drm/i915/display/intel_dp_aux_backlight.c | 4 ++-- drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++++----- drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++-- drivers/gpu/drm/i915/display/intel_opregion.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 4 ++-- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++--- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++-- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 ++- drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++--- .../drm/i915/gt/selftest_engine_heartbeat.c | 6 ++--- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 15 ++++++++----- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +++- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 20 ++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 22 ++++++++++--------- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_debugfs_params.c | 7 +----- drivers/gpu/drm/i915/i915_drv.c | 9 ++++++-- drivers/gpu/drm/i915/i915_drv.h | 5 ++++- drivers/gpu/drm/i915/i915_getparam.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++-- drivers/gpu/drm/i915/intel_gvt.c | 8 +++---- drivers/gpu/drm/i915/intel_region_lmem.c | 6 ++--- drivers/gpu/drm/i915/intel_uncore.c | 8 +++---- 30 files changed, 114 insertions(+), 101 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 839124647202..ec8af2b7bf01 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -479,7 +479,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv, struct drm_display_mode *panel_fixed_mode; int index; - index = i915_modparams.vbt_sdvo_panel_type; + index = dev_priv->params.vbt_sdvo_panel_type; if (index == -2) { drm_dbg_kms(&dev_priv->drm, "Ignore SDVO panel mode from BIOS VBT tables.\n"); @@ -829,9 +829,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) u8 vswing; /* Don't read from VBT if module parameter has valid value*/ - if (i915_modparams.edp_vswing) { + if (dev_priv->params.edp_vswing) { dev_priv->vbt.edp.low_vswing = - i915_modparams.edp_vswing == 1; + dev_priv->params.edp_vswing == 1; } else { vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; dev_priv->vbt.edp.low_vswing = vswing == 0; diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 2f5b9a4baafd..5b4510ce5693 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -833,7 +833,7 @@ intel_crt_detect(struct drm_connector *connector, connector->base.id, connector->name, force); - if (i915_modparams.load_detect_test) { + if (dev_priv->params.load_detect_test) { wakeref = intel_display_power_get(dev_priv, intel_encoder->power_domain); goto load_detect; @@ -889,7 +889,7 @@ intel_crt_detect(struct drm_connector *connector, else if (INTEL_GEN(dev_priv) < 4) status = intel_crt_load_detect(crt, to_intel_crtc(connector->state->crtc)->pipe); - else if (i915_modparams.load_detect_test) + else if (dev_priv->params.load_detect_test) status = connector_status_disconnected; else status = connector_status_unknown; diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 9843c9af6c13..f22a7645c249 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -723,15 +723,15 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) csr->max_fw_size = BXT_CSR_MAX_FW_SIZE; } - if (i915_modparams.dmc_firmware_path) { - if (strlen(i915_modparams.dmc_firmware_path) == 0) { + if (dev_priv->params.dmc_firmware_path) { + if (strlen(dev_priv->params.dmc_firmware_path) == 0) { csr->fw_path = NULL; drm_info(&dev_priv->drm, "Disabling CSR firmware and runtime PM\n"); return; } - csr->fw_path = i915_modparams.dmc_firmware_path; + csr->fw_path = dev_priv->params.dmc_firmware_path; /* Bypass version check for firmware override. */ csr->required_version = 0; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a9f752d26b4e..73108ea5a8d9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4886,7 +4886,7 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) int ret; /* reset doesn't touch the display */ - if (!i915_modparams.force_reset_modeset_test && + if (!dev_priv->params.force_reset_modeset_test && !gpu_reset_clobbers_display(dev_priv)) return; @@ -7879,7 +7879,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) if (!hsw_crtc_supports_ips(crtc)) return false; - if (!i915_modparams.enable_ips) + if (!dev_priv->params.enable_ips) return false; if (crtc_state->pipe_bpp > 24) @@ -8150,8 +8150,8 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) { - if (i915_modparams.panel_use_ssc >= 0) - return i915_modparams.panel_use_ssc != 0; + if (dev_priv->params.panel_use_ssc >= 0) + return dev_priv->params.panel_use_ssc != 0; return dev_priv->vbt.lvds_use_ssc && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); } @@ -13584,8 +13584,8 @@ pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, static bool fastboot_enabled(struct drm_i915_private *dev_priv) { - if (i915_modparams.fastboot != -1) - return i915_modparams.fastboot; + if (dev_priv->params.fastboot != -1) + return dev_priv->params.fastboot; /* Enable fastboot by default on Skylake and newer */ if (INTEL_GEN(dev_priv) >= 9) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 2b640d8ab9d2..05468b793c4b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -125,7 +125,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); seq_printf(m, "Enabled by kernel parameter: %s\n", - yesno(i915_modparams.enable_ips)); + yesno(dev_priv->params.enable_ips)); if (INTEL_GEN(dev_priv) >= 8) { seq_puts(m, "Currently: unknown\n"); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 72312b67b57a..d2c5be926c4f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4513,7 +4513,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, mask = 0; } - if (!i915_modparams.disable_power_well) + if (!dev_priv->params.disable_power_well) max_dc = 0; if (enable_dc >= 0 && enable_dc <= max_dc) { @@ -4602,11 +4602,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; int err; - i915_modparams.disable_power_well = + dev_priv->params.disable_power_well = sanitize_disable_power_well_option(dev_priv, - i915_modparams.disable_power_well); + dev_priv->params.disable_power_well); dev_priv->csr.allowed_dc_mask = - get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); + get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); dev_priv->csr.target_dc_state = sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); @@ -5563,7 +5563,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) intel_display_power_get(i915, POWER_DOMAIN_INIT); /* Disable power support if the user asked so. */ - if (!i915_modparams.disable_power_well) + if (!i915->params.disable_power_well) intel_display_power_get(i915, POWER_DOMAIN_INIT); intel_power_domains_sync_hw(i915); @@ -5587,7 +5587,7 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915) fetch_and_zero(&i915->power_domains.wakeref); /* Remove the refcount we took to keep power well support disabled. */ - if (!i915_modparams.disable_power_well) + if (!i915->params.disable_power_well) intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT); intel_display_power_flush_work_sync(i915); @@ -5676,7 +5676,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, * Even if power well support was disabled we still want to disable * power wells if power domains must be deinitialized for suspend. */ - if (!i915_modparams.disable_power_well) + if (!i915->params.disable_power_well) intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT); intel_display_power_flush_work(i915); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 55fda074c0ad..08ebe349b29e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4707,7 +4707,9 @@ intel_dp_sink_can_mst(struct intel_dp *intel_dp) static bool intel_dp_can_mst(struct intel_dp *intel_dp) { - return i915_modparams.enable_dp_mst && + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + return i915->params.enable_dp_mst && intel_dp->can_mst && intel_dp_sink_can_mst(intel_dp); } @@ -4724,13 +4726,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", encoder->base.base.id, encoder->base.name, yesno(intel_dp->can_mst), yesno(sink_can_mst), - yesno(i915_modparams.enable_dp_mst)); + yesno(i915->params.enable_dp_mst)); if (!intel_dp->can_mst) return; intel_dp->is_mst = sink_can_mst && - i915_modparams.enable_dp_mst; + i915->params.enable_dp_mst; drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 0722540d64ad..acbd7eb66cbe 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -348,7 +348,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder); struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (i915_modparams.enable_dpcd_backlight == 0 || + if (i915->params.enable_dpcd_backlight == 0 || !intel_dp_aux_display_control_capable(intel_connector)) return -ENODEV; @@ -358,7 +358,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) */ if (i915->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE && - i915_modparams.enable_dpcd_backlight != 1 && + i915->params.enable_dpcd_backlight != 1 && !drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks, DP_QUIRK_FORCE_DPCD_BACKLIGHT)) { drm_info(&i915->drm, diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1c26673acb2d..30649e17cfb7 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -740,7 +740,7 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) return false; } - if (!i915_modparams.enable_fbc) { + if (!dev_priv->params.enable_fbc) { fbc->no_fbc_reason = "disabled per module param or by default"; return false; } @@ -1017,7 +1017,7 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) fbc->flip_pending = false; - if (!i915_modparams.enable_fbc) { + if (!dev_priv->params.enable_fbc) { intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); __intel_fbc_disable(dev_priv); @@ -1370,8 +1370,8 @@ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) */ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) { - if (i915_modparams.enable_fbc >= 0) - return !!i915_modparams.enable_fbc; + if (dev_priv->params.enable_fbc >= 0) + return !!dev_priv->params.enable_fbc; if (!HAS_FBC(dev_priv)) return 0; @@ -1415,9 +1415,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) if (need_fbc_vtd_wa(dev_priv)) mkwrite_device_info(dev_priv)->display.has_fbc = false; - i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv); + dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv); drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", - i915_modparams.enable_fbc); + dev_priv->params.enable_fbc); if (!HAS_FBC(dev_priv)) { fbc->no_fbc_reason = "unsupported by this chipset"; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 872f2a489339..1888611244db 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -784,8 +784,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) struct drm_i915_private *dev_priv = to_i915(dev); /* use the module option value if specified */ - if (i915_modparams.lvds_channel_mode > 0) - return i915_modparams.lvds_channel_mode == 2; + if (dev_priv->params.lvds_channel_mode > 0) + return dev_priv->params.lvds_channel_mode == 2; /* single channel LVDS is limited to 112 MHz */ if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index cc6b00959586..de995362f428 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -801,7 +801,7 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; const struct firmware *fw = NULL; - const char *name = i915_modparams.vbt_firmware; + const char *name = dev_priv->params.vbt_firmware; int ret; if (!name || !*name) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 3c5056dbf607..aaed9eb3b56c 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -521,10 +521,10 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector, drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); - if (i915_modparams.invert_brightness < 0) + if (dev_priv->params.invert_brightness < 0) return val; - if (i915_modparams.invert_brightness > 0 || + if (dev_priv->params.invert_brightness > 0 || dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { return panel->backlight.max - val + panel->backlight.min; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b7a2c102648a..c84a2ed19f7b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -83,7 +83,7 @@ static bool psr_global_enabled(struct drm_i915_private *i915) { switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { case I915_PSR_DEBUG_DEFAULT: - return i915_modparams.enable_psr; + return i915->params.enable_psr; case I915_PSR_DEBUG_DISABLE: return false; default: @@ -1450,9 +1450,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv) */ dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; - if (i915_modparams.enable_psr == -1) + if (dev_priv->params.enable_psr == -1) if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) - i915_modparams.enable_psr = 0; + dev_priv->params.enable_psr = 0; /* Set link_standby x link_off defaults */ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index f5d59d18cd5b..4d88faeb4d4c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -650,7 +650,7 @@ static void context_close(struct i915_gem_context *ctx) * context close. */ if (!i915_gem_context_is_persistent(ctx) || - !i915_modparams.enable_hangcheck) + !ctx->i915->params.enable_hangcheck) kill_context(ctx); i915_gem_context_put(ctx); @@ -667,7 +667,7 @@ static int __context_set_persistence(struct i915_gem_context *ctx, bool state) * reset] are allowed to survive past termination. We require * hangcheck to ensure that the persistent requests are healthy. */ - if (!i915_modparams.enable_hangcheck) + if (!ctx->i915->params.enable_hangcheck) return -EINVAL; i915_gem_context_set_persistence(ctx); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index f67ad937eefb..2b2fad14767c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -4,6 +4,7 @@ * Copyright ? 2019 Intel Corporation */ +#include "i915_drv.h" #include "i915_request.h" #include "intel_context.h" @@ -130,7 +131,7 @@ static void heartbeat(struct work_struct *wrk) goto unlock; idle_pulse(engine, rq); - if (i915_modparams.enable_hangcheck) + if (engine->i915->params.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); __i915_request_commit(rq); diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..0156f1f5c736 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -638,7 +638,7 @@ int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask) bool intel_has_gpu_reset(const struct intel_gt *gt) { - if (!i915_modparams.reset) + if (!gt->i915->params.reset) return NULL; return intel_get_gpu_reset(gt); @@ -646,7 +646,7 @@ bool intel_has_gpu_reset(const struct intel_gt *gt) bool intel_has_reset_engine(const struct intel_gt *gt) { - if (i915_modparams.reset < 2) + if (gt->i915->params.reset < 2) return false; return INTEL_INFO(gt->i915)->has_reset_engine; @@ -1038,7 +1038,7 @@ void intel_gt_reset(struct intel_gt *gt, awake = reset_prepare(gt); if (!intel_has_gpu_reset(gt)) { - if (i915_modparams.reset) + if (gt->i915->params.reset) drm_err(>->i915->drm, "GPU reset not supported\n"); else drm_dbg(>->i915->drm, "GPU reset disabled\n"); diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 697114dd1f47..9f04c54c4d0f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -386,11 +386,11 @@ int intel_heartbeat_live_selftests(struct drm_i915_private *i915) if (intel_gt_is_wedged(&i915->gt)) return 0; - saved_hangcheck = i915_modparams.enable_hangcheck; - i915_modparams.enable_hangcheck = INT_MAX; + saved_hangcheck = i915->params.enable_hangcheck; + i915->params.enable_hangcheck = INT_MAX; err = intel_gt_live_subtests(tests, &i915->gt); - i915_modparams.enable_hangcheck = saved_hangcheck; + i915->params.enable_hangcheck = saved_hangcheck; return err; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c index fb10f3597ea5..9bbe8a795cb8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c @@ -424,25 +424,28 @@ static void guc_log_capture_logs(struct intel_guc_log *log) static u32 __get_default_log_level(struct intel_guc_log *log) { + struct intel_guc *guc = log_to_guc(log); + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + /* A negative value means "use platform/config default" */ - if (i915_modparams.guc_log_level < 0) { + if (i915->params.guc_log_level < 0) { return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) || IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ? GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_NON_VERBOSE; } - if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) { + if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) { DRM_WARN("Incompatible option detected: %s=%d, %s!\n", - "guc_log_level", i915_modparams.guc_log_level, + "guc_log_level", i915->params.guc_log_level, "verbosity too high"); return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) || IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ? GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_DISABLED; } - GEM_BUG_ON(i915_modparams.guc_log_level < GUC_LOG_LEVEL_DISABLED); - GEM_BUG_ON(i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX); - return i915_modparams.guc_log_level; + GEM_BUG_ON(i915->params.guc_log_level < GUC_LOG_LEVEL_DISABLED); + GEM_BUG_ON(i915->params.guc_log_level > GUC_LOG_LEVEL_MAX); + return i915->params.guc_log_level; } int intel_guc_log_create(struct intel_guc_log *log) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 94eb63f309ce..fdfeb4b9b0f5 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -660,10 +660,12 @@ void intel_guc_submission_disable(struct intel_guc *guc) static bool __guc_submission_selected(struct intel_guc *guc) { + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + if (!intel_guc_submission_is_supported(guc)) return false; - return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION; + return i915->params.enable_guc & ENABLE_GUC_SUBMISSION; } void intel_guc_submission_init_early(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index f518fe05c6f9..1c2d6358826c 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -47,15 +47,15 @@ static void __confirm_options(struct intel_uc *uc) drm_dbg(&i915->drm, "enable_guc=%d (guc:%s submission:%s huc:%s)\n", - i915_modparams.enable_guc, + i915->params.enable_guc, yesno(intel_uc_wants_guc(uc)), yesno(intel_uc_wants_guc_submission(uc)), yesno(intel_uc_wants_huc(uc))); - if (i915_modparams.enable_guc == -1) + if (i915->params.enable_guc == -1) return; - if (i915_modparams.enable_guc == 0) { + if (i915->params.enable_guc == 0) { GEM_BUG_ON(intel_uc_wants_guc(uc)); GEM_BUG_ON(intel_uc_wants_guc_submission(uc)); GEM_BUG_ON(intel_uc_wants_huc(uc)); @@ -65,25 +65,25 @@ static void __confirm_options(struct intel_uc *uc) if (!intel_uc_supports_guc(uc)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "GuC is not supported!"); + i915->params.enable_guc, "GuC is not supported!"); - if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC && + if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC && !intel_uc_supports_huc(uc)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "HuC is not supported!"); + i915->params.enable_guc, "HuC is not supported!"); - if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION && + if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION && !intel_uc_supports_guc_submission(uc)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "GuC submission is N/A"); + i915->params.enable_guc, "GuC submission is N/A"); - if (i915_modparams.enable_guc & ~(ENABLE_GUC_SUBMISSION | + if (i915->params.enable_guc & ~(ENABLE_GUC_SUBMISSION | ENABLE_GUC_LOAD_HUC)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "undocumented flag"); + i915->params.enable_guc, "undocumented flag"); } void intel_uc_init_early(struct intel_uc *uc) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index e75be3999358..0cbd69abb523 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -117,6 +117,7 @@ struct __packed uc_fw_platform_requirement { static void __uc_fw_auto_select(struct intel_uc_fw *uc_fw, enum intel_platform p, u8 rev) { + struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915; static const struct uc_fw_platform_requirement fw_blobs[] = { INTEL_UC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, HUC_FW_BLOB) }; @@ -154,35 +155,36 @@ __uc_fw_auto_select(struct intel_uc_fw *uc_fw, enum intel_platform p, u8 rev) } /* We don't want to enable GuC/HuC on pre-Gen11 by default */ - if (i915_modparams.enable_guc == -1 && p < INTEL_ICELAKE) + if (i915->params.enable_guc == -1 && p < INTEL_ICELAKE) uc_fw->path = NULL; } -static const char *__override_guc_firmware_path(void) +static const char *__override_guc_firmware_path(struct drm_i915_private *i915) { - if (i915_modparams.enable_guc & (ENABLE_GUC_SUBMISSION | - ENABLE_GUC_LOAD_HUC)) - return i915_modparams.guc_firmware_path; + if (i915->params.enable_guc & (ENABLE_GUC_SUBMISSION | + ENABLE_GUC_LOAD_HUC)) + return i915->params.guc_firmware_path; return ""; } -static const char *__override_huc_firmware_path(void) +static const char *__override_huc_firmware_path(struct drm_i915_private *i915) { - if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC) - return i915_modparams.huc_firmware_path; + if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC) + return i915->params.huc_firmware_path; return ""; } static void __uc_fw_user_override(struct intel_uc_fw *uc_fw) { + struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915; const char *path = NULL; switch (uc_fw->type) { case INTEL_UC_FW_TYPE_GUC: - path = __override_guc_firmware_path(); + path = __override_guc_firmware_path(i915); break; case INTEL_UC_FW_TYPE_HUC: - path = __override_huc_firmware_path(); + path = __override_huc_firmware_path(i915); break; } diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bca036ac6621..8594a8ef08ce 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -64,7 +64,7 @@ static int i915_capabilities(struct seq_file *m, void *data) intel_driver_caps_print(&i915->caps, &p); kernel_param_lock(THIS_MODULE); - i915_params_dump(&i915_modparams, &p); + i915_params_dump(&i915->params, &p); kernel_param_unlock(THIS_MODULE); return 0; diff --git a/drivers/gpu/drm/i915/i915_debugfs_params.c b/drivers/gpu/drm/i915/i915_debugfs_params.c index 62b2c5f0495d..4e2b077692cb 100644 --- a/drivers/gpu/drm/i915/i915_debugfs_params.c +++ b/drivers/gpu/drm/i915/i915_debugfs_params.c @@ -138,9 +138,6 @@ static ssize_t i915_param_charp_write(struct file *file, char **s = m->private; char *new, *old; - /* FIXME: remove locking after params aren't the module params */ - kernel_param_lock(THIS_MODULE); - old = *s; new = strndup_user(ubuf, PAGE_SIZE); if (IS_ERR(new)) { @@ -152,8 +149,6 @@ static ssize_t i915_param_charp_write(struct file *file, kfree(old); out: - kernel_param_unlock(THIS_MODULE); - return len; } @@ -229,7 +224,7 @@ _i915_param_create_file(struct dentry *parent, const char *name, struct dentry *i915_debugfs_params(struct drm_i915_private *i915) { struct drm_minor *minor = i915->drm.primary; - struct i915_params *params = &i915_modparams; + struct i915_params *params = &i915->params; struct dentry *dir; dir = debugfs_create_dir("i915_params", minor->debugfs_root); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 34ee12f3f02d..67102dc26fce 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -501,6 +501,8 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv) cpu_latency_qos_remove_request(&dev_priv->sb_qos); mutex_destroy(&dev_priv->sb_lock); + + i915_params_free(&dev_priv->params); } /** @@ -915,6 +917,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) i915->drm.pdev = pdev; pci_set_drvdata(pdev, i915); + /* Device parameters start as a copy of module parameters. */ + i915_params_copy(&i915->params, &i915_modparams); + /* Setup the write-once "constant" device info */ device_info = mkwrite_device_info(i915); memcpy(device_info, match_info, sizeof(*device_info)); @@ -948,7 +953,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return PTR_ERR(i915); /* Disable nuclear pageflip by default on pre-ILK */ - if (!i915_modparams.nuclear_pageflip && match_info->gen < 5) + if (!i915->params.nuclear_pageflip && match_info->gen < 5) i915->drm.driver_features &= ~DRIVER_ATOMIC; /* @@ -958,7 +963,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) { if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 && - i915_modparams.fake_lmem_start) { + i915->params.fake_lmem_start) { mkwrite_device_info(i915)->memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN; mkwrite_device_info(i915)->is_dgfx = true; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e99255e17eb7..f399d868d930 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -830,6 +830,9 @@ struct drm_i915_private { /* FIXME: Device release actions should all be moved to drmm_ */ bool do_release; + /* i915 device parameters */ + struct i915_params params; + const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ struct intel_driver_caps caps; @@ -1684,7 +1687,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, /* Only valid when HAS_DISPLAY() is true */ #define INTEL_DISPLAY_ENABLED(dev_priv) \ - (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) + (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) static inline bool intel_vtd_active(void) { diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index d042644b9cd2..40390b2352b1 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -80,7 +80,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, return -ENODEV; break; case I915_PARAM_HAS_GPU_RESET: - value = i915_modparams.enable_hangcheck && + value = i915->params.enable_hangcheck && intel_has_gpu_reset(&i915->gt); if (value && intel_has_reset_engine(&i915->gt)) value = 2; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index eec292d06f11..866166ada10e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1698,7 +1698,7 @@ static void capture_gen(struct i915_gpu_coredump *error) error->reset_count = i915_reset_count(&i915->gpu_error); error->suspend_count = i915->suspend_count; - i915_params_copy(&error->params, &i915_modparams); + i915_params_copy(&error->params, &i915->params); memcpy(&error->device_info, INTEL_INFO(i915), sizeof(error->device_info)); @@ -1713,7 +1713,7 @@ i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) { struct i915_gpu_coredump *error; - if (!i915_modparams.error_capture) + if (!i915->params.error_capture) return NULL; error = kzalloc(sizeof(*error), gfp); diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index dd8981340d6e..99fe8aef1c67 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -66,7 +66,7 @@ static bool is_supported_device(struct drm_i915_private *dev_priv) */ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv) { - if (!i915_modparams.enable_gvt) + if (!dev_priv->params.enable_gvt) return; if (intel_vgpu_active(dev_priv)) { @@ -82,7 +82,7 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv) return; bail: - i915_modparams.enable_gvt = 0; + dev_priv->params.enable_gvt = 0; } /** @@ -102,7 +102,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) if (i915_inject_probe_failure(dev_priv)) return -ENODEV; - if (!i915_modparams.enable_gvt) { + if (!dev_priv->params.enable_gvt) { drm_dbg(&dev_priv->drm, "GVT-g is disabled by kernel params\n"); return 0; @@ -123,7 +123,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; bail: - i915_modparams.enable_gvt = 0; + dev_priv->params.enable_gvt = 0; return 0; } diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c index 14b59b899c9b..40d8f1a95df6 100644 --- a/drivers/gpu/drm/i915/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/intel_region_lmem.c @@ -76,7 +76,7 @@ region_lmem_init(struct intel_memory_region *mem) { int ret; - if (i915_modparams.fake_lmem_start) { + if (mem->i915->params.fake_lmem_start) { ret = init_fake_lmem_bar(mem); GEM_BUG_ON(ret); } @@ -111,12 +111,12 @@ intel_setup_fake_lmem(struct drm_i915_private *i915) resource_size_t start; GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt)); - GEM_BUG_ON(!i915_modparams.fake_lmem_start); + GEM_BUG_ON(!i915->params.fake_lmem_start); /* Your mappable aperture belongs to me now! */ mappable_end = pci_resource_len(pdev, 2); io_start = pci_resource_start(pdev, 2), - start = i915_modparams.fake_lmem_start; + start = i915->params.fake_lmem_start; mem = intel_memory_region_create(i915, start, diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 7d6b9ae7403c..592364aed2da 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1185,7 +1185,7 @@ __unclaimed_reg_debug(struct intel_uncore *uncore, read ? "read from" : "write to", i915_mmio_reg_offset(reg))) /* Only report the first N failures */ - i915_modparams.mmio_debug--; + uncore->i915->params.mmio_debug--; } static inline void @@ -1194,7 +1194,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore, const bool read, const bool before) { - if (likely(!i915_modparams.mmio_debug)) + if (likely(!uncore->i915->params.mmio_debug)) return; /* interrupts are disabled and re-enabled around uncore->lock usage */ @@ -2093,12 +2093,12 @@ intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) goto out; if (unlikely(check_for_unclaimed_mmio(uncore))) { - if (!i915_modparams.mmio_debug) { + if (!uncore->i915->params.mmio_debug) { drm_dbg(&uncore->i915->drm, "Unclaimed register detected, " "enabling oneshot unclaimed register reporting. " "Please use i915.mmio_debug=N for more information.\n"); - i915_modparams.mmio_debug++; + uncore->i915->params.mmio_debug++; } uncore->debug->unclaimed_mmio_check--; ret = true; -- 2.20.1 From imre.deak at intel.com Thu Jun 4 15:09:42 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 18:09:42 +0300 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <20200604145530.GS6112@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> <20200604145530.GS6112@intel.com> Message-ID: <20200604150942.GC15427@ideak-desk.fi.intel.com> On Thu, Jun 04, 2020 at 05:55:30PM +0300, Ville Syrj?l? wrote: > On Thu, Jun 04, 2020 at 12:10:38AM +0300, Imre Deak wrote: > > Currently MST on a port can get enabled/disabled from the hotplug work > > and get disabled from the short pulse work in a racy way. Fix this by > > relying on the MST state checking in the hotplug work and just schedule > > a hotplug work from the short pulse handler if some problem happened > > during the MST interrupt handling. > > > > This removes the explicit MST disabling in case of an AUX failure, but > > if AUX fails, then probably the detection will also fail during the > > scheduled hotplug work and it's not guaranteed that we'll see > > intermittent errors anyway. > > > > While at it also simplify the error checking of the MST interrupt > > handler. > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++---------------------- > > 1 file changed, 4 insertions(+), 29 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 55fda074c0ad..befbcacddaa1 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5604,7 +5604,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) > > } > > } > > > > - return need_retrain; > > + return need_retrain ? -EINVAL : 0; > > } > > > > static bool > > @@ -7255,35 +7255,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > > } > > > > if (intel_dp->is_mst) { > > - switch (intel_dp_check_mst_status(intel_dp)) { > > - case -EINVAL: > > - /* > > - * If we were in MST mode, and device is not > > - * there, get out of MST mode > > - */ > > - drm_dbg_kms(&i915->drm, > > - "MST device may have disappeared %d vs %d\n", > > - intel_dp->is_mst, > > - intel_dp->mst_mgr.mst_state); > > - intel_dp->is_mst = false; > > - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > > - intel_dp->is_mst); > > - > > - return IRQ_NONE; > > - case 1: > > - return IRQ_NONE; > > - default: > > - break; > > - } > > - } > > - > > - if (!intel_dp->is_mst) { > > - bool handled; > > - > > - handled = intel_dp_short_pulse(intel_dp); > > - > > - if (!handled) > > + if (intel_dp_check_mst_status(intel_dp) < 0) > > return IRQ_NONE; > > Since we no longer need the tristate return, can you follow up > with a conversion to bool return? I'd vote to make it match the > semantics of intel_dp_short_pulse() so we get one step > closer to unifying the hpd_irq handling across the board. Ok, makes sense. > > > + } else if (!intel_dp_short_pulse(intel_dp)) { > > + return IRQ_NONE; > > } > > > > return IRQ_HANDLED; > > -- > > 2.23.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Thu Jun 4 15:12:27 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 18:12:27 +0300 Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200603221859.9600-1-imre.deak@intel.com> References: <20200603211040.8190-3-imre.deak@intel.com> <20200603221859.9600-1-imre.deak@intel.com> Message-ID: <20200604151227.GT6112@intel.com> On Thu, Jun 04, 2020 at 01:18:59AM +0300, Imre Deak wrote: > Some TypeC -> native DP adapters, at least the Club CAC-1557 adapter, > incorrectly filter out HPD short pulses with a duration less than ~540 > usec, leading to MST probe failures. > > According to the DP alt mode specification adapters should forward short > pulses with a duration greater than 250 usec. According to the DP > specificatin DP sources should detect short pulses in the > 500 usec -> 2 ms range. IIRC it was 250 usec -> 2 ms as well in the DP spec. 500 usec -> 1 ms is the duration of the short hpd the signalling side should use. > Based on this filtering out short pulses with a > duration less than 540 usec is incorrect. > > To make such adapters work add support for a driver polling on MST > inerrupt flags, and wire this up in the i915 driver. The sink can clear > an interrupt it raised after 110 ms if the source doesn't respond, so > use a 50 ms poll period to avoid missing an interrupt. Polling of the > MST interrupt flags is explicitly allowed by the DP specification. > > This fixes MST probe failures I saw using this adapter and a DELL U2515H > monitor. > > v2: > - Fix the wait event timeout for the no-poll case. > > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 19 ++++++++++++++++--- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 +++++++++++++++ > include/drm/drm_dp_mst_helper.h | 1 + > 3 files changed, 32 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 5bc72e800b85..4e987a513df8 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -1178,11 +1178,24 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, > struct drm_dp_sideband_msg_tx *txmsg) > { > struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; > + unsigned long wait_timeout = msecs_to_jiffies(4000); > + unsigned long wait_expires = jiffies + wait_timeout; > int ret; > > - ret = wait_event_timeout(mgr->tx_waitq, > - check_txmsg_state(mgr, txmsg), > - (4 * HZ)); > + for (;;) { > + ret = wait_event_timeout(mgr->tx_waitq, > + check_txmsg_state(mgr, txmsg), > + mgr->cbs->update_hpd_irq_state ? > + msecs_to_jiffies(50) : > + wait_timeout); > + > + if (ret || !mgr->cbs->update_hpd_irq_state || > + time_after(jiffies, wait_expires)) > + break; First I thought this was changing the behaviour when the callback isn't provided, but then I noticed the ?: stuff for the timeout. I think this stuff deserves a comment to explain why we would ever do such a thing instead of simply waiting like we did before. > + > + mgr->cbs->update_hpd_irq_state(mgr); > + } > + > mutex_lock(&mgr->qlock); > if (ret > 0) { > if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d18b406f2a7d..1ff7d0096262 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -765,8 +765,23 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo > return NULL; > } > > +static void > +intel_dp_mst_update_hpd_irq_state(struct drm_dp_mst_topology_mgr *mgr) > +{ > + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + > + spin_lock_irq(&i915->irq_lock); > + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); > + spin_unlock_irq(&i915->irq_lock); > + > + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); I might suggest putting this code right next to intel_hpd_irq_handler() so that people can actually see it when working on the hotplug code. > +} > + > static const struct drm_dp_mst_topology_cbs mst_cbs = { > .add_connector = intel_dp_add_mst_connector, > + .update_hpd_irq_state = intel_dp_mst_update_hpd_irq_state, > }; > > static struct intel_dp_mst_encoder * > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 9e1ffcd7cb68..c902f4380200 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -475,6 +475,7 @@ struct drm_dp_mst_topology_mgr; > struct drm_dp_mst_topology_cbs { > /* create a connector for a port */ > struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); > + void (*update_hpd_irq_state)(struct drm_dp_mst_topology_mgr *mgr); I guess a bit of docs for this might be nice. Maybe s/update/poll/ might make the intention more clear? Not sure. > }; > > #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From chris at chris-wilson.co.uk Thu Jun 4 15:24:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 16:24:30 +0100 Subject: [Intel-gfx] [CI] drm/i915/gt: Track if an engine requires forcewake w/a Message-ID: <20200604152430.3861-1-chris@chris-wilson.co.uk> Sometimes an engine might need to keep forcewake active while it is busy submitting requests for a particular workaround. Track such nuisance with engine->fw_domain. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 ++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 2b6cdf47d428..28b70c13d691 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -24,6 +24,7 @@ #include "i915_selftest.h" #include "intel_sseu.h" #include "intel_timeline_types.h" +#include "intel_uncore.h" #include "intel_wakeref.h" #include "intel_workarounds_types.h" @@ -313,6 +314,15 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + /* + * Some w/a require forcewake to be held (which prevents RC6) while + * a particular engine is active. If so, we set fw_domain to which + * domains need to be held for the duration of request activity, + * and 0 if none. + */ + enum forcewake_domains fw_domain; + unsigned int fw_active; + unsigned long context_tag; struct rb_node uabi_node; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index aac8da18694f..3de3a357074e 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1373,6 +1373,8 @@ __execlists_schedule_in(struct i915_request *rq) ce->lrc.ccid |= engine->execlists.ccid; __intel_gt_pm_get(engine->gt); + if (!engine->fw_active++ && engine->fw_domain) + intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); @@ -1441,6 +1443,8 @@ __execlists_schedule_out(struct i915_request *rq, intel_context_update_runtime(ce); intel_engine_context_out(engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); + if (!--engine->fw_active && engine->fw_domain) + intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); /* -- 2.20.1 From ville.syrjala at linux.intel.com Thu Jun 4 15:25:43 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 18:25:43 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604002359.17128-1-manasi.d.navare@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> Message-ID: <20200604152543.GU6112@intel.com> On Wed, Jun 03, 2020 at 05:23:59PM -0700, Manasi Navare wrote: > We have noticed that when link training fails the panel > sends a long pulse indicating connector disconnect. In this case > we need to reset the link parameters instead of continuing > to use the fallback parameters since else this long pulse > by the panel followed by a modeset request which was triggered by the userspace > before getting the connector status as disconnected, will > result into a modeset now using lower link rate/lane count values. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1385 > Cc: Jani Nikula <jani.nikula at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++-------- > 1 file changed, 19 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 55fda074c0ad..f7af372647dd 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6111,6 +6111,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > intel_dp->edid_quirks = 0; > } > > +static void > +intel_dp_reset_link_params(struct intel_dp *intel_dp) > +{ > + /* Initial max link lane count */ > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > + > + /* Initial max link rate */ > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > + > + intel_dp->reset_link_params = false; > +} > + > static int > intel_dp_detect(struct drm_connector *connector, > struct drm_modeset_acquire_ctx *ctx, > @@ -6139,6 +6151,11 @@ intel_dp_detect(struct drm_connector *connector, > memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); > memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > + /*Reset the immutable VRR Capable property */ > + drm_connector_set_vrr_capable_property(connector, > + false); > + intel_dp_reset_link_params(intel_dp); > + Why would we care what those are when the sink is disconnected? > if (intel_dp->is_mst) { > drm_dbg_kms(&dev_priv->drm, > "MST device may have disappeared %d vs %d\n", > @@ -6152,15 +6169,8 @@ intel_dp_detect(struct drm_connector *connector, > goto out; > } > > - if (intel_dp->reset_link_params) { > - /* Initial max link lane count */ > - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > - > - /* Initial max link rate */ > - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > - > - intel_dp->reset_link_params = false; > - } > + if (intel_dp->reset_link_params) > + intel_dp_reset_link_params(intel_dp); > > intel_dp_print_rates(intel_dp); > > -- > 2.19.1 -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Thu Jun 4 15:28:30 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 15:28:30 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Trim_set=5Ftimer=5Fms=28=29_intervals?= In-Reply-To: <20200604135938.3975-1-chris@chris-wilson.co.uk> References: <20200604135938.3975-1-chris@chris-wilson.co.uk> Message-ID: <159128451083.14555.13011380529138973532@emeril.freedesktop.org> == Series Details == Series: drm/i915: Trim set_timer_ms() intervals URL : https://patchwork.freedesktop.org/series/78002/ State : success == Summary == CI Bug Log - changes from CI_DRM_8583 -> Patchwork_17871 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/index.html Known issues ------------ Here are the changes found in Patchwork_17871 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-rte: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-tgl-y/igt at i915_pm_rpm@basic-rte.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/fi-tgl-y/igt at i915_pm_rpm@basic-rte.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][3] ([i915#95]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92]) -> [DMESG-WARN][6] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#62] / [i915#92]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8583 -> Patchwork_17871 CI-20190529: 20190529 CI_DRM_8583: e147ef9bced964b97283851a519aea132a5613e6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17871: 5e06d688ea6b95e0bbeaf12390351a259dfb391c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5e06d688ea6b drm/i915: Trim set_timer_ms() intervals == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/index.html From chris at chris-wilson.co.uk Thu Jun 4 15:31:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 16:31:45 +0100 Subject: [Intel-gfx] [CI] drm/i915/gt: Track if an engine requires forcewake w/a Message-ID: <20200604153145.21068-1-chris@chris-wilson.co.uk> Sometimes an engine might need to keep forcewake active while it is busy submitting requests for a particular workaround. Track such nuisance with engine->fw_domain. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 11 +++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 2b6cdf47d428..073c3769e8cc 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -24,6 +24,7 @@ #include "i915_selftest.h" #include "intel_sseu.h" #include "intel_timeline_types.h" +#include "intel_uncore.h" #include "intel_wakeref.h" #include "intel_workarounds_types.h" @@ -313,6 +314,16 @@ struct intel_engine_cs { u32 context_size; u32 mmio_base; + /* + * Some w/a require forcewake to be held (which prevents RC6) while + * a particular engine is active. If so, we set fw_domain to which + * domains need to be held for the duration of request activity, + * and 0 if none. We try to limit the duration of the hold as much + * as possible. + */ + enum forcewake_domains fw_domain; + atomic_t fw_active; + unsigned long context_tag; struct rb_node uabi_node; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index aac8da18694f..33b7173b7195 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1373,6 +1373,8 @@ __execlists_schedule_in(struct i915_request *rq) ce->lrc.ccid |= engine->execlists.ccid; __intel_gt_pm_get(engine->gt); + if (engine->fw_domain && !atomic_fetch_inc(&engine->fw_active)) + intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); @@ -1441,6 +1443,8 @@ __execlists_schedule_out(struct i915_request *rq, intel_context_update_runtime(ce); intel_engine_context_out(engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); + if (engine->fw_domain && !atomic_dec_return(&engine->fw_active)) + intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); /* -- 2.20.1 From ville.syrjala at linux.intel.com Thu Jun 4 15:34:05 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 18:34:05 +0300 Subject: [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly In-Reply-To: <20200603211529.3005059-2-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-2-matthew.d.roper@intel.com> Message-ID: <20200604153405.GV6112@intel.com> On Wed, Jun 03, 2020 at 02:15:15PM -0700, Matt Roper wrote: > Although we properly captured RKL's three pipes in the device info > structure, we forgot to make the corresponding update to the transcoder > mask. Set this field so that our transcoder loops will operate > properly. > > Fixes: 123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids") > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Matches what I see in the spec. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/i915_pci.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 07b09af3a9c3..0ed586ee2047 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -881,6 +881,8 @@ static const struct intel_device_info rkl_info = { > GEN12_FEATURES, > PLATFORM(INTEL_ROCKETLAKE), > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), > + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > + BIT(TRANSCODER_C), > .require_force_probe = 1, > .engine_mask = > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From imre.deak at intel.com Thu Jun 4 15:41:34 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 18:41:34 +0300 Subject: [Intel-gfx] [PATCH v2 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200604151227.GT6112@intel.com> References: <20200603211040.8190-3-imre.deak@intel.com> <20200603221859.9600-1-imre.deak@intel.com> <20200604151227.GT6112@intel.com> Message-ID: <20200604154134.GD15427@ideak-desk.fi.intel.com> On Thu, Jun 04, 2020 at 06:12:27PM +0300, Ville Syrj?l? wrote: > On Thu, Jun 04, 2020 at 01:18:59AM +0300, Imre Deak wrote: > > Some TypeC -> native DP adapters, at least the Club CAC-1557 adapter, > > incorrectly filter out HPD short pulses with a duration less than ~540 > > usec, leading to MST probe failures. > > > > According to the DP alt mode specification adapters should forward short > > pulses with a duration greater than 250 usec. According to the DP > > specificatin DP sources should detect short pulses in the > > 500 usec -> 2 ms range. > > IIRC it was 250 usec -> 2 ms as well in the DP spec. > > 500 usec -> 1 ms is the duration of the short hpd > the signalling side should use. Ah, correct (and this is what makes actually sense). For reference it's described under "5.1.4 Source Device Behavior upon HPD Pulse Detection" > > Based on this filtering out short pulses with a > > duration less than 540 usec is incorrect. > > > > To make such adapters work add support for a driver polling on MST > > inerrupt flags, and wire this up in the i915 driver. The sink can clear > > an interrupt it raised after 110 ms if the source doesn't respond, so > > use a 50 ms poll period to avoid missing an interrupt. Polling of the > > MST interrupt flags is explicitly allowed by the DP specification. > > > > This fixes MST probe failures I saw using this adapter and a DELL U2515H > > monitor. > > > > v2: > > - Fix the wait event timeout for the no-poll case. > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 19 ++++++++++++++++--- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 +++++++++++++++ > > include/drm/drm_dp_mst_helper.h | 1 + > > 3 files changed, 32 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > index 5bc72e800b85..4e987a513df8 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -1178,11 +1178,24 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, > > struct drm_dp_sideband_msg_tx *txmsg) > > { > > struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; > > + unsigned long wait_timeout = msecs_to_jiffies(4000); > > + unsigned long wait_expires = jiffies + wait_timeout; > > int ret; > > > > - ret = wait_event_timeout(mgr->tx_waitq, > > - check_txmsg_state(mgr, txmsg), > > - (4 * HZ)); > > + for (;;) { > > + ret = wait_event_timeout(mgr->tx_waitq, > > + check_txmsg_state(mgr, txmsg), > > + mgr->cbs->update_hpd_irq_state ? > > + msecs_to_jiffies(50) : > > + wait_timeout); > > + > > + if (ret || !mgr->cbs->update_hpd_irq_state || > > + time_after(jiffies, wait_expires)) > > + break; > > First I thought this was changing the behaviour when the callback > isn't provided, but then I noticed the ?: stuff for the timeout. > > I think this stuff deserves a comment to explain why we would > ever do such a thing instead of simply waiting like we did before. Ok, will add a compact form of the commit log explanation. > > > + > > + mgr->cbs->update_hpd_irq_state(mgr); > > + } > > + > > mutex_lock(&mgr->qlock); > > if (ret > 0) { > > if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index d18b406f2a7d..1ff7d0096262 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -765,8 +765,23 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo > > return NULL; > > } > > > > +static void > > +intel_dp_mst_update_hpd_irq_state(struct drm_dp_mst_topology_mgr *mgr) > > +{ > > + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); > > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + > > + spin_lock_irq(&i915->irq_lock); > > + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); > > + spin_unlock_irq(&i915->irq_lock); > > + > > + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); > > I might suggest putting this code right next to intel_hpd_irq_handler() > so that people can actually see it when working on the hotplug code. Ok. > > > +} > > + > > static const struct drm_dp_mst_topology_cbs mst_cbs = { > > .add_connector = intel_dp_add_mst_connector, > > + .update_hpd_irq_state = intel_dp_mst_update_hpd_irq_state, > > }; > > > > static struct intel_dp_mst_encoder * > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > > index 9e1ffcd7cb68..c902f4380200 100644 > > --- a/include/drm/drm_dp_mst_helper.h > > +++ b/include/drm/drm_dp_mst_helper.h > > @@ -475,6 +475,7 @@ struct drm_dp_mst_topology_mgr; > > struct drm_dp_mst_topology_cbs { > > /* create a connector for a port */ > > struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); > > + void (*update_hpd_irq_state)(struct drm_dp_mst_topology_mgr *mgr); > > I guess a bit of docs for this might be nice. Maybe s/update/poll/ > might make the intention more clear? Not sure. Ok. > > > }; > > > > #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) > > -- > > 2.23.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Thu Jun 4 15:49:09 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 15:49:09 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_switch_to_device_specific_parameters?= In-Reply-To: <20200604150503.17199-1-jani.nikula@intel.com> References: <20200604150503.17199-1-jani.nikula@intel.com> Message-ID: <159128574934.14555.5243811314207063969@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: switch to device specific parameters URL : https://patchwork.freedesktop.org/series/78004/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8583 -> Patchwork_17872 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17872 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17872, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17872: ### CI changes ### #### Possible regressions #### * boot: - fi-kbl-8809g: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-8809g/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-kbl-8809g/boot.html - fi-icl-y: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-y/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-icl-y/boot.html - fi-icl-u2: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-u2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-icl-u2/boot.html - fi-cfl-8109u: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-cfl-8109u/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-cfl-8109u/boot.html - fi-skl-6600u: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-skl-6600u/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-skl-6600u/boot.html - fi-cfl-8700k: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-cfl-8700k/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-cfl-8700k/boot.html - fi-bxt-dsi: [PASS][13] -> [FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-bxt-dsi/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-bxt-dsi/boot.html - fi-icl-dsi: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-dsi/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-icl-dsi/boot.html - fi-whl-u: [PASS][17] -> [FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-whl-u/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-whl-u/boot.html - fi-cml-u2: [PASS][19] -> [FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-cml-u2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-cml-u2/boot.html - fi-skl-6700k2: [PASS][21] -> [FAIL][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-skl-6700k2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-skl-6700k2/boot.html - fi-cfl-guc: [PASS][23] -> [FAIL][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-cfl-guc/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-cfl-guc/boot.html - fi-kbl-soraka: [PASS][25] -> [FAIL][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-soraka/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-kbl-soraka/boot.html - fi-icl-guc: [PASS][27] -> [FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-guc/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-icl-guc/boot.html - fi-cml-s: [PASS][29] -> [FAIL][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-cml-s/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-cml-s/boot.html - fi-skl-lmem: [PASS][31] -> [FAIL][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-skl-lmem/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-skl-lmem/boot.html - fi-glk-dsi: [PASS][33] -> [FAIL][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-glk-dsi/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-glk-dsi/boot.html - fi-tgl-y: [PASS][35] -> [FAIL][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-tgl-y/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-tgl-y/boot.html - fi-kbl-guc: [PASS][37] -> [FAIL][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-guc/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-kbl-guc/boot.html - fi-kbl-x1275: [PASS][39] -> [FAIL][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-kbl-x1275/boot.html - fi-kbl-7500u: [PASS][41] -> [FAIL][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-7500u/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-kbl-7500u/boot.html - fi-skl-guc: [PASS][43] -> [FAIL][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-skl-guc/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-skl-guc/boot.html - fi-kbl-r: [PASS][45] -> [FAIL][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-r/boot.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-kbl-r/boot.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * boot: - {fi-tgl-dsi}: [PASS][47] -> [FAIL][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-tgl-dsi/boot.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-tgl-dsi/boot.html - {fi-tgl-u}: [PASS][49] -> [FAIL][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-tgl-u/boot.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-tgl-u/boot.html - {fi-kbl-7560u}: NOTRUN -> [FAIL][51] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-kbl-7560u/boot.html - {fi-ehl-1}: [PASS][52] -> [FAIL][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-ehl-1/boot.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-ehl-1/boot.html Known issues ------------ Here are the changes found in Patchwork_17872 that come from known issues: ### CI changes ### #### Issues hit #### * boot: - fi-apl-guc: [PASS][54] -> [FAIL][55] ([i915#348]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-apl-guc/boot.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-apl-guc/boot.html ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-bsw-n3050: [PASS][56] -> [DMESG-WARN][57] ([i915#1982]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-bsw-n3050/igt at i915_module_load@reload.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-bsw-n3050/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][58] -> [DMESG-WARN][59] ([i915#1982]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#348]: https://gitlab.freedesktop.org/drm/intel/issues/348 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8583 -> Patchwork_17872 CI-20190529: 20190529 CI_DRM_8583: e147ef9bced964b97283851a519aea132a5613e6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17872: 121db1e864d600a3de364f26a4df211cadc0f7c5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 121db1e864d6 drm/i915/params: switch to device specific parameters == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17872/index.html From patchwork at emeril.freedesktop.org Thu Jun 4 16:22:14 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 16:22:14 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Track_if_an_engine_requires_forcewake_w/a_=28rev2?= =?utf-8?q?=29?= In-Reply-To: <20200604153145.21068-1-chris@chris-wilson.co.uk> References: <20200604153145.21068-1-chris@chris-wilson.co.uk> Message-ID: <159128773448.14555.1212994467018220145@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Track if an engine requires forcewake w/a (rev2) URL : https://patchwork.freedesktop.org/series/78005/ State : success == Summary == CI Bug Log - changes from CI_DRM_8583 -> Patchwork_17873 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/index.html Known issues ------------ Here are the changes found in Patchwork_17873 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-tgl-y/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/fi-tgl-y/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8583 -> Patchwork_17873 CI-20190529: 20190529 CI_DRM_8583: e147ef9bced964b97283851a519aea132a5613e6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17873: 7042716777f39a6e12bbac546bcd4dbe97048bff @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7042716777f3 drm/i915/gt: Track if an engine requires forcewake w/a == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/index.html From chris at chris-wilson.co.uk Thu Jun 4 16:38:36 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 17:38:36 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Extract busy-stats for use in other schedulers Message-ID: <20200604163836.7514-1-chris@chris-wilson.co.uk> Once again extract the context in/out accounting for use elsewhere, and add a selftest to check that the busy-stats are being reported correctly. Other than keep userspace informed, the busy-stats are a funamental building block for activity tracking such as RPS. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 +++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 91 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ 4 files changed, 146 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include <linux/atomic.h> +#include <linux/ktime.h> +#include <linux/seqlock.h> + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d55a5e0466e5..36e2ce4ac2fa 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1187,39 +1188,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..a35737958735 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,96 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t dt, de; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + break; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (100 * de < 95 * dt) { + pr_err("%s: reported only %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + break; + } + + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + igt_spinner_fini(&spin); + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +167,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From matthew.d.roper at intel.com Thu Jun 4 16:39:16 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 4 Jun 2020 09:39:16 -0700 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches?= In-Reply-To: <159125964432.14555.14975271091238919132@emeril.freedesktop.org> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <159125964432.14555.14975271091238919132@emeril.freedesktop.org> Message-ID: <20200604163916.GA3023929@mdroper-desk1.amr.corp.intel.com> On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote: > == Series Details == > > Series: Remaining RKL patches > URL : https://patchwork.freedesktop.org/series/77971/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's. Matt > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17859_full: > > ### IGT changes ### > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * {igt at gem_ctx_isolation@preservation-s3 at vcs0}: > - shard-kbl: [INCOMPLETE][1] ([i915#1780]) -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vcs0.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at vcs0.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_17859_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_eio@in-flight-internal-10ms: > - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +8 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl3/igt at gem_eio@in-flight-internal-10ms.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt at gem_eio@in-flight-internal-10ms.html > > * igt at gem_eio@in-flight-suspend: > - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) +1 similar issue > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at gem_eio@in-flight-suspend.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl10/igt at gem_eio@in-flight-suspend.html > > * igt at gem_mmap_offset@clear: > - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +10 similar issues > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl4/igt at gem_mmap_offset@clear.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl9/igt at gem_mmap_offset@clear.html > > * igt at i915_module_load@reload: > - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at i915_module_load@reload.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb2/igt at i915_module_load@reload.html > > * igt at i915_suspend@fence-restore-tiled2untiled: > - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt at i915_suspend@fence-restore-tiled2untiled.html > > * igt at i915_suspend@forcewake: > - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at i915_suspend@forcewake.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl4/igt at i915_suspend@forcewake.html > > * igt at kms_cursor_crc@pipe-c-cursor-size-change: > - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-size-change.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-size-change.html > > * igt at kms_cursor_legacy@all-pipes-torture-move: > - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb6/igt at kms_cursor_legacy@all-pipes-torture-move.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb6/igt at kms_cursor_legacy@all-pipes-torture-move.html > - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#128]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb3/igt at kms_cursor_legacy@all-pipes-torture-move.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb6/igt at kms_cursor_legacy@all-pipes-torture-move.html > > * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: > - shard-glk: [PASS][21] -> [DMESG-FAIL][22] ([i915#1925] / [i915#1926]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk9/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk7/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html > > * igt at kms_flip_tiling@flip-yf-tiled: > - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145]) > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_flip_tiling@flip-yf-tiled.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_flip_tiling@flip-yf-tiled.html > > * igt at kms_frontbuffer_tracking@fbc-badstride: > - shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu: > - shard-iclb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu: > - shard-skl: [PASS][29] -> [FAIL][30] ([i915#49]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html > > * igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence: > - shard-skl: [PASS][31] -> [FAIL][32] ([i915#53]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl2/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl4/igt at kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html > > * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > > * igt at kms_psr@no_drrs: > - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#173]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb4/igt at kms_psr@no_drrs.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb1/igt at kms_psr@no_drrs.html > > * igt at kms_setmode@basic: > - shard-apl: [PASS][37] -> [FAIL][38] ([i915#31]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_setmode@basic.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt at kms_setmode@basic.html > > * igt at kms_vblank@pipe-c-wait-busy: > - shard-tglb: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_vblank@pipe-c-wait-busy.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt at kms_vblank@pipe-c-wait-busy.html > > * igt at syncobj_wait@single-wait-all-signaled: > - shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#93] / [i915#95]) +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl7/igt at syncobj_wait@single-wait-all-signaled.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl3/igt at syncobj_wait@single-wait-all-signaled.html > > > #### Possible fixes #### > > * {igt at gem_exec_reloc@basic-concurrent0}: > - shard-glk: [FAIL][43] ([i915#1930]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html > - shard-apl: [FAIL][45] ([i915#1930]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at gem_exec_reloc@basic-concurrent0.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl4/igt at gem_exec_reloc@basic-concurrent0.html > > * {igt at gem_exec_schedule@implicit-write-read at rcs0}: > - shard-snb: [INCOMPLETE][47] ([i915#82]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html > > * igt at gem_workarounds@suspend-resume-context: > - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +2 similar issues > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at gem_workarounds@suspend-resume-context.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt at gem_workarounds@suspend-resume-context.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-180: > - shard-apl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt at kms_big_fb@yf-tiled-32bpp-rotate-180.html > > * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: > - shard-tglb: [DMESG-WARN][53] ([i915#402]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb2/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb8/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html > > * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: > - shard-skl: [FAIL][55] ([i915#46]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl8/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html > > * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1}: > - shard-kbl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html > > * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: > - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html > - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html > > * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: > - shard-skl: [INCOMPLETE][63] ([i915#69]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html > > * igt at kms_plane@plane-panning-top-left-pipe-c-planes: > - shard-skl: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +10 similar issues > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-skl9/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-skl5/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: > - shard-apl: [DMESG-WARN][67] ([i915#95]) -> [PASS][68] +11 similar issues > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html > > * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: > - shard-iclb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +1 similar issue > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-iclb8/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html > > * igt at kms_vblank@pipe-a-ts-continuation-suspend: > - shard-kbl: [DMESG-WARN][71] ([i915#180]) -> [PASS][72] +4 similar issues > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > > * {igt at perf@blocking-parameterized}: > - shard-tglb: [FAIL][73] ([i915#1542]) -> [PASS][74] > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-tglb7/igt at perf@blocking-parameterized.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-tglb3/igt at perf@blocking-parameterized.html > > * igt at perf_pmu@rc6-runtime-pm: > - shard-glk: [TIMEOUT][75] ([i915#1958]) -> [PASS][76] +3 similar issues > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at perf_pmu@rc6-runtime-pm.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt at perf_pmu@rc6-runtime-pm.html > > > #### Warnings #### > > * igt at kms_content_protection@atomic: > - shard-kbl: [TIMEOUT][77] ([i915#1319]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-kbl4/igt at kms_content_protection@atomic.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-kbl7/igt at kms_content_protection@atomic.html > - shard-apl: [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][80] ([fdo#110321] / [i915#95]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@atomic.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@atomic-dpms: > - shard-apl: [TIMEOUT][81] ([i915#1319]) -> [FAIL][82] ([fdo#110321] / [fdo#110336]) > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl1/igt at kms_content_protection@atomic-dpms.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl6/igt at kms_content_protection@atomic-dpms.html > > * igt at kms_content_protection@lic: > - shard-apl: [TIMEOUT][83] ([i915#1319] / [i915#1635]) -> [TIMEOUT][84] ([i915#1319]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl6/igt at kms_content_protection@lic.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl7/igt at kms_content_protection@lic.html > > * igt at kms_content_protection@srm: > - shard-apl: [FAIL][85] ([fdo#110321]) -> [TIMEOUT][86] ([i915#1319]) > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_content_protection@srm.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt at kms_content_protection@srm.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: > - shard-apl: [DMESG-FAIL][87] ([i915#49] / [i915#95]) -> [FAIL][88] ([i915#49]) > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html > > * igt at kms_vblank@pipe-d-query-idle-hang: > - shard-glk: [TIMEOUT][89] ([i915#1640] / [i915#1958]) -> [SKIP][90] ([fdo#109271]) > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8579/shard-glk5/igt at kms_vblank@pipe-d-query-idle-hang.html > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/shard-glk1/igt at kms_vblank@pipe-d-query-idle-hang.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#1640]: https://gitlab.freedesktop.org/drm/intel/issues/1640 > [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 > [i915#1780]: https://gitlab.freedesktop.org/drm/intel/issues/1780 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 > [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8579 -> Patchwork_17859 > > CI-20190529: 20190529 > CI_DRM_8579: 289eb12c88c49a4ac8d325dc457d8878c7f5bdc0 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5694: a9b6c4c74bfddf7d3d2da3be08804fe315945cea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17859: c298c9e3576e74cdc573db5a6f877f920d106bbb @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17859/index.html -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From ville.syrjala at linux.intel.com Thu Jun 4 16:55:29 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 19:55:29 +0300 Subject: [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D In-Reply-To: <20200603211529.3005059-10-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-10-matthew.d.roper@intel.com> Message-ID: <20200604165529.GW6112@intel.com> On Wed, Jun 03, 2020 at 02:15:23PM -0700, Matt Roper wrote: > There are a couple places in our driver that loop over transcoders A..D > for gen11+; since RKL only has three pipes/transcoders, this can lead to > unclaimed register reads/writes. We should add checks for transcoder > existence where appropriate. > > v2: Move one transcoder check that wound up in the wrong function after > conflict resolution. It belongs in bdw_get_trans_port_sync_config > rather than bxt_get_dsi_transcoder_state. > > v3: Switch loops to use for_each_cpu_transcoder_masked() since this > iterator already checks the platform's transcoder mask for us. > (Ville) > > Cc: Aditya Swarup <aditya.swarup at intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index f3ea81a17352..40a71c4a1ef5 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2885,13 +2885,15 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) > { > struct intel_uncore *uncore = &dev_priv->uncore; > enum pipe pipe; > + u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D); > > intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); > > if (INTEL_GEN(dev_priv) >= 12) { > enum transcoder trans; > > - for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) { > + for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { > enum intel_display_power_domain domain; > > domain = POWER_DOMAIN_TRANSCODER(trans); > @@ -3413,6 +3415,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); > u32 de_port_enables; > u32 de_misc_masked = GEN8_DE_EDP_PSR; > + u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D); > enum pipe pipe; > > if (INTEL_GEN(dev_priv) <= 10) > @@ -3433,7 +3437,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > if (INTEL_GEN(dev_priv) >= 12) { > enum transcoder trans; > > - for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) { > + for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { > enum intel_display_power_domain domain; > > domain = POWER_DOMAIN_TRANSCODER(trans); > -- > 2.24.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 4 16:59:00 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 19:59:00 +0300 Subject: [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders In-Reply-To: <20200603211529.3005059-11-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-11-matthew.d.roper@intel.com> Message-ID: <20200604165900.GX6112@intel.com> On Wed, Jun 03, 2020 at 02:15:24PM -0700, Matt Roper wrote: > From: Aditya Swarup <aditya.swarup at intel.com> > > RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI > transcoder registers. > > v2(MattR): > - Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask > against the platform's cpu_transcoder_mask to filter out the ones > that don't exist on a given platform. (Ville) > > Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 11 +++-------- > 1 file changed, 3 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 019fef8023ca..bcc6dc4e321b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -10904,19 +10904,13 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > enum intel_display_power_domain power_domain; > - unsigned long panel_transcoder_mask = 0; > + unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP) | > + BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); TRANSCODER_DSI_0/1 alias TRANSCODER_DSI_A/C which we do not want in this mask. > unsigned long enabled_panel_transcoders = 0; > enum transcoder panel_transcoder; > intel_wakeref_t wf; > u32 tmp; > > - if (INTEL_GEN(dev_priv) >= 11) > - panel_transcoder_mask |= > - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); > - > - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP)) > - panel_transcoder_mask |= BIT(TRANSCODER_EDP); > - > /* > * The pipe->transcoder mapping is fixed with the exception of the eDP > * and DSI transcoders handled below. > @@ -10927,6 +10921,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, > * XXX: Do intel_display_power_get_if_enabled before reading this (for > * consistency and less surprising code; it's in always on power). > */ > + panel_transcoder_mask &= INTEL_INFO(dev_priv)->cpu_transcoder_mask; > for_each_set_bit(panel_transcoder, > &panel_transcoder_mask, > ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) { Can't we just use for_each_cpu_transcoder_masked() ? > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 4 16:59:55 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 19:59:55 +0300 Subject: [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI In-Reply-To: <20200603211529.3005059-14-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-14-matthew.d.roper@intel.com> Message-ID: <20200604165955.GY6112@intel.com> On Wed, Jun 03, 2020 at 02:15:27PM -0700, Matt Roper wrote: > If HTI (also sometimes called HDPORT) is enabled at startup, it may be whatis HTI? > using some of the PHYs and DPLLs making them unavailable for general > usage. Let's read out the HDPORT_STATE register and avoid making use of > resources that HTI is already using. > > v2: > - Fix minor checkpatch warnings > > Bspec: 49189 > Bspec: 53707 > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + > drivers/gpu/drm/i915/i915_drv.h | 3 ++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++ > 5 files changed, 57 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index bcc6dc4e321b..cdd84a419cf7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -46,6 +46,7 @@ > #include "display/intel_ddi.h" > #include "display/intel_dp.h" > #include "display/intel_dp_mst.h" > +#include "display/intel_dpll_mgr.h" > #include "display/intel_dsi.h" > #include "display/intel_dvo.h" > #include "display/intel_gmbus.h" > @@ -16817,6 +16818,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) > intel_pps_unlock_regs_wa(dev_priv); > } > > +static bool hti_uses_phy(u32 hdport_state, enum phy phy) > +{ > + return hdport_state & HDPORT_ENABLED && > + (hdport_state & HDPORT_PHY_USED_DP(phy) || > + hdport_state & HDPORT_PHY_USED_HDMI(phy)); > +} > + > static void intel_setup_outputs(struct drm_i915_private *dev_priv) > { > struct intel_encoder *encoder; > @@ -16828,10 +16836,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > return; > > if (IS_ROCKETLAKE(dev_priv)) { > - intel_ddi_init(dev_priv, PORT_A); > - intel_ddi_init(dev_priv, PORT_B); > - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > + /* > + * If HTI (aka HDPORT) is enabled at boot, it may have taken > + * over some of the PHYs and made them unavailable to the > + * driver. In that case we should skip initializing the > + * corresponding outputs. > + */ > + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); > + > + if (!hti_uses_phy(hdport_state, PHY_A)) > + intel_ddi_init(dev_priv, PORT_A); > + if (!hti_uses_phy(hdport_state, PHY_B)) > + intel_ddi_init(dev_priv, PORT_B); > + if (!hti_uses_phy(hdport_state, PHY_C)) > + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > + if (!hti_uses_phy(hdport_state, PHY_D)) > + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > } else if (INTEL_GEN(dev_priv) >= 12) { > intel_ddi_init(dev_priv, PORT_A); > intel_ddi_init(dev_priv, PORT_B); > @@ -18379,6 +18399,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) > > intel_dpll_readout_hw_state(dev_priv); > > + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); > + > for_each_intel_encoder(dev, encoder) { > pipe = 0; > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index b5f4d4cef682..6f59f9ec453b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) > mutex_unlock(&dev_priv->dpll.lock); > } > > +/* > + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them > + * unavailable for use. > + */ > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) > +{ > + u32 hdport_state; > + > + if (!IS_ROCKETLAKE(dev_priv)) > + return 0; > + > + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); > + if (!(hdport_state & HDPORT_ENABLED)) > + return 0; > + > + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); > +} > + > static struct intel_shared_dpll * > intel_find_shared_dpll(struct intel_atomic_state *state, > const struct intel_crtc *crtc, > @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, > > drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); > > + /* Eliminate DPLLs from consideration if reserved by HTI */ > + dpll_mask &= ~dev_priv->hti_pll_mask; > + > for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { > pll = &dev_priv->dpll.shared_dplls[i]; > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > index 5d9a2bc371e7..ac2238646fe7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); > void intel_shared_dpll_init(struct drm_device *dev); > void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); > void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); > > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, > const struct intel_dpll_hw_state *hw_state); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index e99255e17eb7..668b3c9cf3ae 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1037,6 +1037,9 @@ struct drm_i915_private { > > struct intel_l3_parity l3_parity; > > + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ > + u32 hti_pll_mask; > + > /* > * edram size in MB. > * Cannot be determined by PCIID. You must always read a register. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 85137d268c4a..b9faf0f978cf 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2906,6 +2906,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) > #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) > > +#define HDPORT_STATE _MMIO(0x45050) > +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) > +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*(phy) + 2) > +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2*(phy) + 1) > +#define HDPORT_ENABLED REG_BIT(0) > + > /* Make render/texture TLB fetches lower priorty than associated data > * fetches. This is not turned on by default > */ > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Thu Jun 4 17:00:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 17:00:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Trace_HWSP_cachelines?= In-Reply-To: <20200604132305.22089-1-chris@chris-wilson.co.uk> References: <20200604132305.22089-1-chris@chris-wilson.co.uk> Message-ID: <159129001867.14555.392947895830138885@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Trace HWSP cachelines URL : https://patchwork.freedesktop.org/series/78000/ State : success == Summary == CI Bug Log - changes from CI_DRM_8583_full -> Patchwork_17870_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17870_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_tiled_pread_basic: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +16 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl8/igt at gem_tiled_pread_basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl4/igt at gem_tiled_pread_basic.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl7/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@all-pipes-torture-bo: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#128]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb2/igt at kms_cursor_legacy@all-pipes-torture-bo.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-tglb1/igt at kms_cursor_legacy@all-pipes-torture-bo.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#1925] / [i915#1926]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-glk8/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [PASS][15] -> [FAIL][16] ([IGT#5]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl10/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl3/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-apl: [PASS][17] -> [TIMEOUT][18] ([i915#1635]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl8/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#49]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl8/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl5/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#648] / [i915#69]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#173]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb2/igt at kms_psr@no_drrs.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-iclb1/igt at kms_psr@psr2_sprite_blt.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl2/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-kbl7/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-tglb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-tglb1/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl8/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html * igt at prime_vgem@basic-fence-flip: - shard-skl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl5/igt at prime_vgem@basic-fence-flip.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl6/igt at prime_vgem@basic-fence-flip.html #### Possible fixes #### * igt at gem_exec_whisper@basic-normal-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk7/igt at gem_exec_whisper@basic-normal-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-glk2/igt at gem_exec_whisper@basic-normal-all.html * igt at gem_softpin@noreloc-s3: - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl3/igt at gem_softpin@noreloc-s3.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-kbl6/igt at gem_softpin@noreloc-s3.html * igt at i915_suspend@forcewake: - shard-apl: [INCOMPLETE][43] -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl1/igt at i915_suspend@forcewake.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl1/igt at i915_suspend@forcewake.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl3/igt at kms_color@pipe-c-ctm-red-to-blue.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-kbl6/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [DMESG-FAIL][49] ([i915#54] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-hsw7/igt at kms_cursor_legacy@pipe-c-torture-move.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-hsw7/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-apl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl8/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl3/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * {igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][55] ([i915#1928]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk7/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-glk2/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][59] ([i915#95]) -> [PASS][60] +18 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl4/igt at kms_flip_tiling@flip-x-tiled.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl3/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: - shard-skl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +10 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl1/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl8/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][69] ([i915#31]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl1/igt at kms_setmode@basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-kbl1/igt at kms_setmode@basic.html * {igt at perf_pmu@module-unload}: - shard-tglb: [DMESG-WARN][71] ([i915#402]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb1/igt at perf_pmu@module-unload.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-tglb6/igt at perf_pmu@module-unload.html * {igt at sysfs_heartbeat_interval@mixed at vcs1}: - shard-iclb: [DMESG-WARN][73] ([i915#1982]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb2/igt at sysfs_heartbeat_interval@mixed at vcs1.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-iclb1/igt at sysfs_heartbeat_interval@mixed at vcs1.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [INCOMPLETE][75] ([i915#82]) -> [SKIP][76] ([fdo#109271]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-snb1/igt at i915_pm_dc@dc3co-vpb-simulation.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-snb6/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][77] ([i915#454]) -> [SKIP][78] ([i915#468]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb8/igt at i915_pm_dc@dc6-psr.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][79] ([i915#1515]) -> [FAIL][80] ([i915#1515]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb2/igt at i915_pm_rc6_residency@rc6-idle.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-iclb1/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][81] ([i915#1319] / [i915#1635]) -> [FAIL][82] ([fdo#110321] / [fdo#110336]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl6/igt at kms_content_protection@atomic-dpms.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-WARN][83] ([i915#1926]) -> [DMESG-FAIL][84] ([i915#1925] / [i915#1926]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-glk8/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-glk: [INCOMPLETE][85] ([i915#58] / [k.org#198133]) -> [TIMEOUT][86] ([i915#1958]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-apl: [SKIP][87] ([fdo#109271]) -> [TIMEOUT][88] ([i915#1635]) +1 similar issue [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl8/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][89] ([i915#180] / [i915#95]) -> [DMESG-WARN][90] ([i915#95]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/shard-apl1/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8583 -> Patchwork_17870 CI-20190529: 20190529 CI_DRM_8583: e147ef9bced964b97283851a519aea132a5613e6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17870: bb11ec0255995d1b00b7e3b7d4fad4f375d49c6b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17870/index.html From ville.syrjala at linux.intel.com Thu Jun 4 17:01:57 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 20:01:57 +0300 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 In-Reply-To: <20200603211529.3005059-3-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-3-matthew.d.roper@intel.com> Message-ID: <20200604170157.GZ6112@intel.com> On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote: > RKL uses the same BW_BUDDY programming table as TGL, but programs the > values into a single set BUDDY0 set of registers rather than the > BUDDY1/BUDDY2 sets used by TGL. Maybe we just want some kind of HAS_ABOX() so we could use the same thing here and in the ABOX_CTL programming? > > Bspec: 49218 > Cc: Aditya Swarup <aditya.swarup at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > .../drm/i915/display/intel_display_power.c | 44 +++++++++++-------- > drivers/gpu/drm/i915/i915_reg.h | 14 ++++-- > 2 files changed, 35 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 72312b67b57a..2c1ce50b572b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > enum intel_dram_type type = dev_priv->dram_info.type; > u8 num_channels = dev_priv->dram_info.num_channels; > const struct buddy_page_mask *table; > - int i; > + int config, min_buddy, max_buddy, i; > > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) > /* Wa_1409767108: tgl */ > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > else > table = tgl_buddy_page_masks; > > - for (i = 0; table[i].page_mask != 0; i++) > - if (table[i].num_channels == num_channels && > - table[i].type == type) > + if (IS_ROCKETLAKE(dev_priv)) { > + min_buddy = max_buddy = 0; > + } else { > + min_buddy = 1; > + max_buddy = 2; > + } > + > + for (config = 0; table[config].page_mask != 0; config++) > + if (table[config].num_channels == num_channels && > + table[config].type == type) > break; > > - if (table[i].page_mask == 0) { > + if (table[config].page_mask == 0) { > drm_dbg(&dev_priv->drm, > "Unknown memory configuration; disabling address buddy logic.\n"); > - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); > - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); > + for (i = min_buddy; i <= max_buddy; i++) > + intel_de_write(dev_priv, BW_BUDDY_CTL(i), > + BW_BUDDY_DISABLE); > } else { > - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, > - table[i].page_mask); > - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, > - table[i].page_mask); > - > - /* Wa_22010178259:tgl */ > - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, > - BW_BUDDY_TLB_REQ_TIMER_MASK, > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, > - BW_BUDDY_TLB_REQ_TIMER_MASK, > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > + for (i = min_buddy; i <= max_buddy; i++) { > + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > + table[config].page_mask); > + > + /* Wa_22010178259:tgl,rkl */ > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > + BW_BUDDY_TLB_REQ_TIMER_MASK, > + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, > + 0x8)); > + } > } > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 578cfe11cbb9..3e79cefc510a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7837,13 +7837,19 @@ enum { > #define WAIT_FOR_PCH_RESET_ACK (1 << 1) > #define WAIT_FOR_PCH_FLR_ACK (1 << 0) > > -#define BW_BUDDY1_CTL _MMIO(0x45140) > -#define BW_BUDDY2_CTL _MMIO(0x45150) > +#define _BW_BUDDY0_CTL 0x45130 > +#define _BW_BUDDY1_CTL 0x45140 > +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ > + _BW_BUDDY0_CTL, \ > + _BW_BUDDY1_CTL)) > #define BW_BUDDY_DISABLE REG_BIT(31) > #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) > > -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) > -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) > +#define _BW_BUDDY0_PAGE_MASK 0x45134 > +#define _BW_BUDDY1_PAGE_MASK 0x45144 > +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ > + _BW_BUDDY0_PAGE_MASK, \ > + _BW_BUDDY1_PAGE_MASK)) > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 4 17:09:14 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 20:09:14 +0300 Subject: [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys In-Reply-To: <20200603211529.3005059-6-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-6-matthew.d.roper@intel.com> Message-ID: <20200604170914.GA6112@intel.com> On Wed, Jun 03, 2020 at 02:15:19PM -0700, Matt Roper wrote: > RKL uses DDI's A, B, TC1, and TC2 which need to map to combo PHY's A-D. > > Bspec: 49181 > Cc: Imre Deak <imre.deak at intel.com> > Cc: Aditya Swarup <aditya.swarup at intel.com> > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++-------- > drivers/gpu/drm/i915/i915_reg.h | 4 ++- > 2 files changed, 24 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index b4f8c88c779f..019fef8023ca 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7218,30 +7218,33 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) > { > if (phy == PHY_NONE) > return false; > - > - if (IS_ELKHARTLAKE(dev_priv)) > + else if (IS_ROCKETLAKE(dev_priv)) > + return phy <= PHY_D; Or just 'return true' since combo PHYs is all we have. /me weeps when looking at these functions. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > + else if (IS_ELKHARTLAKE(dev_priv)) > return phy <= PHY_C; > - > - if (INTEL_GEN(dev_priv) >= 11) > + else if (INTEL_GEN(dev_priv) >= 11) > return phy <= PHY_B; > - > - return false; > + else > + return false; > } > > bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) > { > - if (INTEL_GEN(dev_priv) >= 12) > + if (IS_ROCKETLAKE(dev_priv)) > + return false; > + else if (INTEL_GEN(dev_priv) >= 12) > return phy >= PHY_D && phy <= PHY_I; > - > - if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) > + else if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv)) > return phy >= PHY_C && phy <= PHY_F; > - > - return false; > + else > + return false; > } > > enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) > { > - if (IS_ELKHARTLAKE(i915) && port == PORT_D) > + if (IS_ROCKETLAKE(i915) && port >= PORT_D) > + return (enum phy)port - 1; > + else if (IS_ELKHARTLAKE(i915) && port == PORT_D) > return PHY_A; > > return (enum phy)port; > @@ -16829,7 +16832,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) > return; > > - if (INTEL_GEN(dev_priv) >= 12) { > + if (IS_ROCKETLAKE(dev_priv)) { > + intel_ddi_init(dev_priv, PORT_A); > + intel_ddi_init(dev_priv, PORT_B); > + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > + } else if (INTEL_GEN(dev_priv) >= 12) { > intel_ddi_init(dev_priv, PORT_A); > intel_ddi_init(dev_priv, PORT_B); > intel_ddi_init(dev_priv, PORT_D); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index db031269a05a..85137d268c4a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1869,9 +1869,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define _ICL_COMBOPHY_A 0x162000 > #define _ICL_COMBOPHY_B 0x6C000 > #define _EHL_COMBOPHY_C 0x160000 > +#define _RKL_COMBOPHY_D 0x161000 > #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ > _ICL_COMBOPHY_B, \ > - _EHL_COMBOPHY_C) > + _EHL_COMBOPHY_C, \ > + _RKL_COMBOPHY_D) > > /* CNL/ICL Port CL_DW registers */ > #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Thu Jun 4 17:18:14 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 17:18:14 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gt=3A_Extract_busy-stats_for_use_in_other_schedule?= =?utf-8?q?rs?= In-Reply-To: <20200604163836.7514-1-chris@chris-wilson.co.uk> References: <20200604163836.7514-1-chris@chris-wilson.co.uk> Message-ID: <159129109414.14555.3822733976572237011@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Extract busy-stats for use in other schedulers URL : https://patchwork.freedesktop.org/series/78007/ State : warning == Summary == $ dim checkpatch origin/drm-tip ffa4cc633b49 drm/i915/gt: Extract busy-stats for use in other schedulers -:14: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #14: new file mode 100644 -:165: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #165: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:47: + udelay(100); -:195: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #195: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:77: + udelay(100); total: 0 errors, 1 warnings, 2 checks, 209 lines checked From patchwork at emeril.freedesktop.org Thu Jun 4 17:42:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 17:42:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Extract_busy-stats_for_use_in_other_schedulers?= In-Reply-To: <20200604163836.7514-1-chris@chris-wilson.co.uk> References: <20200604163836.7514-1-chris@chris-wilson.co.uk> Message-ID: <159129255399.14554.16009622065809505658@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Extract busy-stats for use in other schedulers URL : https://patchwork.freedesktop.org/series/78007/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8584 -> Patchwork_17874 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17874 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17874, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17874: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_engines: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-icl-y/igt at i915_selftest@live at gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/fi-icl-y/igt at i915_selftest@live at gt_engines.html - fi-tgl-y: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-tgl-y/igt at i915_selftest@live at gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/fi-tgl-y/igt at i915_selftest@live at gt_engines.html Known issues ------------ Here are the changes found in Patchwork_17874 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_pm_rpm@basic-rte: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-tgl-dsi/igt at i915_pm_rpm@basic-rte.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/fi-tgl-dsi/igt at i915_pm_rpm@basic-rte.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 44) ------------------------------ Additional (4): fi-bsw-kefka fi-skl-lmem fi-cml-s fi-bsw-n3050 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8584 -> Patchwork_17874 CI-20190529: 20190529 CI_DRM_8584: 2219a8bbaa3c87f07656725f4d2ea6623d1fd09a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17874: ffa4cc633b498c858ed7646f2c040e0f9f6ee394 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ffa4cc633b49 drm/i915/gt: Extract busy-stats for use in other schedulers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17874/index.html From rodrigo.vivi at intel.com Thu Jun 4 17:41:38 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Thu, 4 Jun 2020 10:41:38 -0700 Subject: [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2 In-Reply-To: <20200603211529.3005059-15-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-15-matthew.d.roper@intel.com> Message-ID: <20200604174138.GF3190340@intel.com> On Wed, Jun 03, 2020 at 02:15:28PM -0700, Matt Roper wrote: > From: Jos? Roberto de Souza <jose.souza at intel.com> > > RKL doesn't have PSR2 HW tracking, it was replaced by software/manual > tracking. The driver is required to track the areas that needs update > and program hardware to send selective updates. > > So until the software tracking is implemented, PSR2 needs to be disabled > for platforms without PSR2 HW tracking. > > BSpec: 50422 > BSpec: 50424 > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_pci.c | 3 +++ > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 4 files changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index b7a2c102648a..714c590b39f5 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -646,6 +646,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > + /* > + * Some platforms lack PSR2 HW tracking and instead require manual > + * tracking by software. In this case, the driver is required to track > + * the areas that need updates and program hardware to send selective > + * updates. > + * > + * So until the software tracking is implemented, PSR2 needs to be > + * disabled for platforms without PSR2 HW tracking. > + */ > + if (!HAS_PSR_HW_TRACKING(dev_priv)) { > + drm_dbg_kms(&dev_priv->drm, > + "No PSR2 HW tracking in the platform\n"); > + return false; > + } > + > /* > * DSC and PSR2 cannot be enabled simultaneously. If a requested > * resolution requires DSC to be enabled, priority is given to DSC > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 668b3c9cf3ae..87f4000413f1 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1644,6 +1644,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) > #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) > #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > +#define HAS_PSR_HW_TRACKING(dev_priv) \ > + (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) > #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) > > #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 0ed586ee2047..ef4a457a6c4f 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -536,6 +536,7 @@ static const struct intel_device_info vlv_info = { > .display.has_ddi = 1, \ > .has_fpga_dbg = 1, \ > .display.has_psr = 1, \ > + .display.has_psr_hw_tracking = 1, \ > .display.has_dp_mst = 1, \ > .has_rc6p = 0 /* RC6p removed-by HSW */, \ > HSW_PIPE_OFFSETS, \ > @@ -690,6 +691,7 @@ static const struct intel_device_info skl_gt4_info = { > .display.has_fbc = 1, \ > .display.has_hdcp = 1, \ > .display.has_psr = 1, \ > + .display.has_psr_hw_tracking = 1, \ > .has_runtime_pm = 1, \ > .display.has_csr = 1, \ > .has_rc6 = 1, \ > @@ -884,6 +886,7 @@ static const struct intel_device_info rkl_info = { > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > BIT(TRANSCODER_C), > .require_force_probe = 1, > + .display.has_psr_hw_tracking = 0, > .engine_mask = > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), > }; > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 3613c04904e0..34dbffd65bad 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -148,6 +148,7 @@ enum intel_ppgtt_type { > func(has_modular_fia); \ > func(has_overlay); \ > func(has_psr); \ > + func(has_psr_hw_tracking); \ > func(overlay_needs_physical); \ > func(supports_tv); > > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Thu Jun 4 17:44:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 17:44:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Trim_set=5Ftimer=5Fms=28=29_intervals?= In-Reply-To: <20200604135938.3975-1-chris@chris-wilson.co.uk> References: <20200604135938.3975-1-chris@chris-wilson.co.uk> Message-ID: <159129266903.14553.10376186463947059620@emeril.freedesktop.org> == Series Details == Series: drm/i915: Trim set_timer_ms() intervals URL : https://patchwork.freedesktop.org/series/78002/ State : success == Summary == CI Bug Log - changes from CI_DRM_8583_full -> Patchwork_17871_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17871_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk1/igt at gem_exec_whisper@basic-queues-forked-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk8/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([i915#155]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl7/igt at i915_suspend@debugfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl2/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl7/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl5/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#95]) +19 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_cursor_legacy@cursora-vs-flipb-toggle: - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#1925] / [i915#1926]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk8/igt at kms_cursor_legacy@cursora-vs-flipb-toggle.html * igt at kms_cursor_legacy@short-flip-after-cursor-toggle: - shard-snb: [PASS][15] -> [SKIP][16] ([fdo#109271]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-snb5/igt at kms_cursor_legacy@short-flip-after-cursor-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-snb6/igt at kms_cursor_legacy@short-flip-after-cursor-toggle.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-apl: [PASS][17] -> [TIMEOUT][18] ([i915#1635]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#49]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl8/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-skl6/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [PASS][23] -> [FAIL][24] ([i915#1188]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl2/igt at kms_hdr@bpc-switch-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-iclb: [PASS][25] -> [INCOMPLETE][26] ([CI#80] / [i915#1185]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-iclb3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-c-plane-scaling: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +6 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl8/igt at kms_plane_scaling@pipe-c-plane-scaling.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-skl6/igt at kms_plane_scaling@pipe-c-plane-scaling.html * igt at kms_psr@psr2_suspend: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb2/igt at kms_psr@psr2_suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-iclb1/igt at kms_psr@psr2_suspend.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#93] / [i915#95]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl2/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl6/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][35] ([i915#1930]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk1/igt at gem_exec_reloc@basic-concurrent0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_softpin@noreloc-s3: - shard-kbl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl3/igt at gem_softpin@noreloc-s3.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl1/igt at gem_softpin@noreloc-s3.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][39] ([i915#1436] / [i915#716]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl7/igt at gen9_exec_parse@allowed-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl3/igt at gen9_exec_parse@allowed-all.html * igt at i915_suspend@forcewake: - shard-apl: [INCOMPLETE][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl1/igt at i915_suspend@forcewake.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl2/igt at i915_suspend@forcewake.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-5: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +8 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl1/igt at kms_color@pipe-c-ctm-0-5.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-skl3/igt at kms_color@pipe-c-ctm-0-5.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] +3 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl3/igt at kms_color@pipe-c-ctm-red-to-blue.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl6/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [DMESG-FAIL][49] ([i915#54] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [INCOMPLETE][51] ([i915#1926] / [i915#61]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-hsw2/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-hsw1/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-WARN][53] ([i915#1926]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk1/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][55] ([i915#128]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-hsw7/igt at kms_cursor_legacy@pipe-c-torture-move.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-hsw5/igt at kms_cursor_legacy@pipe-c-torture-move.html * {igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][57] ([i915#1928]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk7/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk7/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_properties@invalid-properties-legacy: - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [PASS][64] +18 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl6/igt at kms_properties@invalid-properties-legacy.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl8/igt at kms_properties@invalid-properties-legacy.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +3 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb3/igt at kms_psr@psr2_cursor_blt.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][67] ([i915#31]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl1/igt at kms_setmode@basic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-kbl2/igt at kms_setmode@basic.html * {igt at perf_pmu@busy-start at bcs0}: - shard-glk: [DMESG-WARN][69] ([i915#118] / [i915#95]) -> [PASS][70] +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk1/igt at perf_pmu@busy-start at bcs0.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk5/igt at perf_pmu@busy-start at bcs0.html * {igt at perf_pmu@module-unload}: - shard-tglb: [DMESG-WARN][71] ([i915#402]) -> [PASS][72] +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb1/igt at perf_pmu@module-unload.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-tglb3/igt at perf_pmu@module-unload.html #### Warnings #### * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-apl: [SKIP][73] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][74] ([i915#1366] / [i915#1635]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl1/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][75] ([i915#1319] / [i915#1635]) -> [TIMEOUT][76] ([i915#1319]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl4/igt at kms_content_protection@atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl6/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl8/igt at kms_content_protection@lic.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-glk: [INCOMPLETE][79] ([i915#58] / [k.org#198133]) -> [TIMEOUT][80] ([i915#1958]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-apl: [SKIP][81] ([fdo#109271]) -> [TIMEOUT][82] ([i915#1635]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl1/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][83] ([i915#180] / [i915#95]) -> [DMESG-WARN][84] ([i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at runner@aborted: - shard-glk: [FAIL][85] ([k.org#202321]) -> [FAIL][86] ([i915#1611] / [k.org#202321]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at runner@aborted.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/shard-glk1/igt at runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1366]: https://gitlab.freedesktop.org/drm/intel/issues/1366 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8583 -> Patchwork_17871 CI-20190529: 20190529 CI_DRM_8583: e147ef9bced964b97283851a519aea132a5613e6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17871: 5e06d688ea6b95e0bbeaf12390351a259dfb391c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17871/index.html From manasi.d.navare at intel.com Thu Jun 4 18:16:00 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 4 Jun 2020 11:16:00 -0700 Subject: [Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes In-Reply-To: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> References: <20200601173058.5084-1-stanislav.lisovskiy@intel.com> Message-ID: <20200604181600.GA3922@intel.com> Pushed to dinq, thanks for the patch. Manasi On Mon, Jun 01, 2020 at 08:30:58PM +0300, Stanislav Lisovskiy wrote: > Previous patch didn't take into account all pipes > but only those in state, which could cause wrong > CDCLK conclcusions and calculations. > Also there was a severe issue with min_cdclk being > assigned to 0 every compare cycle. > > Too bad this was found by me only after merge. > This could be also causing the issues in test, however > not clear - anyway marking this as fixing the > "Adjust CDCLK accordingly to our DBuf bw needs". > > v2: - s/pipe/crtc->pipe/ > - save a bit of instructions by > skipping inactive pipes, without > getting 0 DBuf slice mask for it. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > Fixes: cd1915460861 ("Adjust CDCLK accordingly to our DBuf bw needs") > --- > drivers/gpu/drm/i915/display/intel_bw.c | 52 +++++++++++++------- > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++--- > drivers/gpu/drm/i915/display/intel_display.c | 26 +++++----- > 3 files changed, 55 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index a79bd7aeb03b..bd060404d249 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -437,6 +437,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > struct intel_crtc *crtc; > int max_bw = 0; > int slice_id; > + enum pipe pipe; > int i; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > @@ -447,10 +448,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > if (IS_ERR(new_bw_state)) > return PTR_ERR(new_bw_state); > > + old_bw_state = intel_atomic_get_old_bw_state(state); > + > crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe]; > > memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw)); > > + if (!crtc_state->hw.active) > + continue; > + > for_each_plane_id_on_crtc(crtc, plane_id) { > const struct skl_ddb_entry *plane_alloc = > &crtc_state->wm.skl.plane_ddb_y[plane_id]; > @@ -478,6 +484,15 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) > crtc_bw->used_bw[slice_id] += data_rate; > } > + } > + > + if (!old_bw_state) > + return 0; > + > + for_each_pipe(dev_priv, pipe) { > + struct intel_dbuf_bw *crtc_bw; > + > + crtc_bw = &new_bw_state->dbuf_bw[pipe]; > > for_each_dbuf_slice(slice_id) { > /* > @@ -490,14 +505,9 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > */ > max_bw += crtc_bw->used_bw[slice_id]; > } > - > - new_bw_state->min_cdclk = max_bw / 64; > - > - old_bw_state = intel_atomic_get_old_bw_state(state); > } > > - if (!old_bw_state) > - return 0; > + new_bw_state->min_cdclk = max_bw / 64; > > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > @@ -511,34 +521,38 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) > > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state) > { > - int i; > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_bw_state *new_bw_state = NULL; > + struct intel_bw_state *old_bw_state = NULL; > const struct intel_crtc_state *crtc_state; > struct intel_crtc *crtc; > int min_cdclk = 0; > - struct intel_bw_state *new_bw_state = NULL; > - struct intel_bw_state *old_bw_state = NULL; > + enum pipe pipe; > + int i; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > - struct intel_cdclk_state *cdclk_state; > - > new_bw_state = intel_atomic_get_bw_state(state); > if (IS_ERR(new_bw_state)) > return PTR_ERR(new_bw_state); > > - cdclk_state = intel_atomic_get_cdclk_state(state); > - if (IS_ERR(cdclk_state)) > - return PTR_ERR(cdclk_state); > - > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > - > - new_bw_state->min_cdclk = min_cdclk; > - > old_bw_state = intel_atomic_get_old_bw_state(state); > } > > if (!old_bw_state) > return 0; > > + for_each_pipe(dev_priv, pipe) { > + struct intel_cdclk_state *cdclk_state; > + > + cdclk_state = intel_atomic_get_new_cdclk_state(state); > + if (!cdclk_state) > + return 0; > + > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > + } > + > + new_bw_state->min_cdclk = min_cdclk; > + > if (new_bw_state->min_cdclk != old_bw_state->min_cdclk) { > int ret = intel_atomic_lock_global_state(&new_bw_state->base); > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index f9b0fc7317de..08468b121d02 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2084,9 +2084,12 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > { > struct intel_atomic_state *state = cdclk_state->base.state; > + struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_bw_state *bw_state = NULL; > struct intel_crtc *crtc; > struct intel_crtc_state *crtc_state; > int min_cdclk, i; > + enum pipe pipe; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > int ret; > @@ -2095,6 +2098,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > if (min_cdclk < 0) > return min_cdclk; > > + bw_state = intel_atomic_get_bw_state(state); > + if (IS_ERR(bw_state)) > + return PTR_ERR(bw_state); > + > if (cdclk_state->min_cdclk[i] == min_cdclk) > continue; > > @@ -2106,15 +2113,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) > } > > min_cdclk = cdclk_state->force_min_cdclk; > + for_each_pipe(dev_priv, pipe) { > + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > - struct intel_bw_state *bw_state; > - > - min_cdclk = max(cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > - > - bw_state = intel_atomic_get_bw_state(state); > - if (IS_ERR(bw_state)) > - return PTR_ERR(bw_state); > + if (!bw_state) > + continue; > > min_cdclk = max(bw_state->min_cdclk, min_cdclk); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f40b909952cc..66af8f3053ed 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -14708,13 +14708,14 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > bool *need_cdclk_calc) > { > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > - int i; > + struct intel_cdclk_state *new_cdclk_state; > struct intel_plane_state *plane_state; > + struct intel_bw_state *new_bw_state; > struct intel_plane *plane; > + int min_cdclk = 0; > + enum pipe pipe; > int ret; > - struct intel_cdclk_state *new_cdclk_state; > - struct intel_crtc_state *new_crtc_state; > - struct intel_crtc *crtc; > + int i; > /* > * active_planes bitmask has been updated, and potentially > * affected planes are part of the state. We can now > @@ -14735,23 +14736,18 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, > if (ret) > return ret; > > - if (!new_cdclk_state) > - return 0; > - > - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > - struct intel_bw_state *bw_state; > - int min_cdclk = 0; > + new_bw_state = intel_atomic_get_new_bw_state(state); > > - min_cdclk = max(new_cdclk_state->min_cdclk[crtc->pipe], min_cdclk); > + if (!new_cdclk_state || !new_bw_state) > + return 0; > > - bw_state = intel_atomic_get_bw_state(state); > - if (IS_ERR(bw_state)) > - return PTR_ERR(bw_state); > + for_each_pipe(dev_priv, pipe) { > + min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk); > > /* > * Currently do this change only if we need to increase > */ > - if (bw_state->min_cdclk > min_cdclk) > + if (new_bw_state->min_cdclk > min_cdclk) > *need_cdclk_calc = true; > } > > -- > 2.24.1.485.gad05a3d8e5 > From patchwork at emeril.freedesktop.org Thu Jun 4 18:28:01 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 18:28:01 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Track_if_an_engine_requires_forcewake_w/a_=28rev2?= =?utf-8?q?=29?= In-Reply-To: <20200604153145.21068-1-chris@chris-wilson.co.uk> References: <20200604153145.21068-1-chris@chris-wilson.co.uk> Message-ID: <159129528105.14554.1536086890159739494@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Track if an engine requires forcewake w/a (rev2) URL : https://patchwork.freedesktop.org/series/78005/ State : success == Summary == CI Bug Log - changes from CI_DRM_8583_full -> Patchwork_17873_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17873_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vecs0: - shard-kbl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl1/igt at gem_ctx_persistence@engines-mixed-process at vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl3/igt at gem_ctx_persistence@engines-mixed-process at vecs0.html * igt at gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk1/igt at gem_exec_whisper@basic-forked-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk2/igt at gem_exec_whisper@basic-forked-all.html * igt at gem_tiled_pread_basic: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +18 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl8/igt at gem_tiled_pread_basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl4/igt at gem_tiled_pread_basic.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl2/igt at gem_workarounds@suspend-resume-context.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl6/igt at gem_workarounds@suspend-resume-context.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][11] -> [INCOMPLETE][12] ([i915#155]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl7/igt at i915_suspend@debugfs-reader.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl6/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl7/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl3/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk8/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +9 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl3/igt at kms_color@pipe-c-ctm-0-25.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-skl8/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl8/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl1/igt at kms_hdr@bpc-switch.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-skl10/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_suspend: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb2/igt at kms_psr@psr2_suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-iclb4/igt at kms_psr@psr2_suspend.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl2/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl6/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-tglb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-tglb3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html * igt at kms_vblank@pipe-b-wait-busy: - shard-iclb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb4/igt at kms_vblank@pipe-b-wait-busy.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-iclb8/igt at kms_vblank@pipe-b-wait-busy.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][37] ([i915#1930]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk1/igt at gem_exec_reloc@basic-concurrent0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_softpin@noreloc-s3: - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl3/igt at gem_softpin@noreloc-s3.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl1/igt at gem_softpin@noreloc-s3.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][41] ([i915#1436] / [i915#716]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl7/igt at gen9_exec_parse@allowed-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl6/igt at gen9_exec_parse@allowed-all.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk9/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-5: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +5 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-skl1/igt at kms_color@pipe-c-ctm-0-5.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-skl10/igt at kms_color@pipe-c-ctm-0-5.html * igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [INCOMPLETE][47] ([i915#1926] / [i915#61]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-hsw2/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-hsw2/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][49] ([i915#128]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-hsw7/igt at kms_cursor_legacy@pipe-c-torture-move.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-hsw2/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-apl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl8/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl1/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-glk: [INCOMPLETE][53] ([i915#58] / [k.org#198133]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk5/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * {igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][55] ([i915#1928]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk7/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk6/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl2/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][59] ([i915#95]) -> [PASS][60] +22 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl4/igt at kms_flip_tiling@flip-x-tiled.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt: - shard-glk: [INCOMPLETE][61] ([i915#1927] / [i915#58] / [k.org#198133]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk1/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][63] ([i915#93] / [i915#95]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-glk: [TIMEOUT][65] ([i915#1958]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk5/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][67] ([fdo#109642] / [fdo#111068]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb1/igt at kms_psr2_su@page_flip.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_plane_onoff: - shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb6/igt at kms_psr@psr2_sprite_plane_onoff.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-iclb2/igt at kms_psr@psr2_sprite_plane_onoff.html * {igt at perf_pmu@busy-start at bcs0}: - shard-glk: [DMESG-WARN][71] ([i915#118] / [i915#95]) -> [PASS][72] +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk1/igt at perf_pmu@busy-start at bcs0.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk2/igt at perf_pmu@busy-start at bcs0.html * {igt at perf_pmu@module-unload}: - shard-tglb: [DMESG-WARN][73] ([i915#402]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-tglb1/igt at perf_pmu@module-unload.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-tglb5/igt at perf_pmu@module-unload.html * {igt at sysfs_heartbeat_interval@mixed at vcs1}: - shard-iclb: [DMESG-WARN][75] ([i915#1982]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb2/igt at sysfs_heartbeat_interval@mixed at vcs1.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-iclb4/igt at sysfs_heartbeat_interval@mixed at vcs1.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [INCOMPLETE][77] ([i915#82]) -> [SKIP][78] ([fdo#109271]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-snb1/igt at i915_pm_dc@dc3co-vpb-simulation.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-snb6/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_suspend@forcewake: - shard-apl: [INCOMPLETE][79] -> [DMESG-WARN][80] ([i915#180]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl1/igt at i915_suspend@forcewake.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl4/igt at i915_suspend@forcewake.html * igt at kms_ccs@pipe-c-crc-primary-basic: - shard-glk: [TIMEOUT][81] ([i915#1958]) -> [SKIP][82] ([fdo#109271]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk6/igt at kms_ccs@pipe-c-crc-primary-basic.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk5/igt at kms_ccs@pipe-c-crc-primary-basic.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][83] ([i915#1319] / [i915#1635]) -> [TIMEOUT][84] ([i915#1319]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl4/igt at kms_content_protection@atomic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][85] ([i915#1319] / [i915#1635]) -> [FAIL][86] ([fdo#110321] / [fdo#110336]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl1/igt at kms_content_protection@legacy.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][87] ([i915#1319]) -> [DMESG-FAIL][88] ([fdo#110321] / [i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-kbl6/igt at kms_content_protection@srm.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-kbl2/igt at kms_content_protection@srm.html * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-glk: [DMESG-WARN][89] ([i915#1926]) -> [DMESG-FAIL][90] ([i915#1925] / [i915#1926]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-glk2/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-glk5/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][91] ([fdo#109349]) -> [DMESG-WARN][92] ([i915#1226]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-iclb6/igt at kms_dp_dsc@basic-dsc-enable-edp.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][93] ([i915#180] / [i915#95]) -> [DMESG-WARN][94] ([i915#95]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8583/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/shard-apl2/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1927]: https://gitlab.freedesktop.org/drm/intel/issues/1927 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 10) ------------------------------ Missing (1): pig-icl-1065g7 Build changes ------------- * Linux: CI_DRM_8583 -> Patchwork_17873 CI-20190529: 20190529 CI_DRM_8583: e147ef9bced964b97283851a519aea132a5613e6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17873: 7042716777f39a6e12bbac546bcd4dbe97048bff @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17873/index.html From ville.syrjala at linux.intel.com Thu Jun 4 18:29:19 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 21:29:19 +0300 Subject: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL In-Reply-To: <20200603211529.3005059-8-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-8-matthew.d.roper@intel.com> Message-ID: <20200604182919.GB6112@intel.com> On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote: > When TGP is paired with RKL it uses a different HPD pin mapping than > when paired with TGL. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 490574669eaa..f3ea81a17352 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), > }; > > +/* > + * TGP when paired with RKL has different pin mappings than when paired > + * with TGL. > + */ > +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = { > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), > + [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1), > + [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2), > +}; Hmm. So basically it looks like we'd want to pick the hpd_pin based on the DDI rather than the PHY on this platform? OK, I guess we need to remap somehow. The question is whether we want to do it before or after selecting hpd_pin... I think we would want to do it before, as otherwise the long_detect() stuff won't work right AFAICS. Or am I missing something? Side note: we should probably convert the long_detect() switches to arrays just like we have for the isr bits here. Would potentially avoid having to touch that code every time they tweak these thinhs in hw. And in fact it looks like icp already has all the same hpd pins as tgp, so I'm thinking we should just s/hpd_tgp/hpd_icp/ and for icl/jsl we should remap hpd_pin as well. Oh and the mcc case would just need a slightly different mapping of port C -> HPD_PORT_D (aka. tc1). This way all the hpd[] arrays and whatnot would just be based on the actual pch type and not based on what it happens to be paired with. Anwyays, most of that is out of scope for this rkl stuff, so I guess for now just add a bit of logic to remap hpd_pin for rkl? > + > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > { > struct i915_hotplug *hpd = &dev_priv->hotplug; > @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) > return; > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > + if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv)) > + hpd->pch_hpd = hpd_rkl_tgp; > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > hpd->pch_hpd = hpd_tgp; > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) > hpd->pch_hpd = hpd_icp; > -- > 2.24.1 -- Ville Syrj?l? Intel From ayaz.siddiqui at intel.com Thu Jun 4 18:26:58 2020 From: ayaz.siddiqui at intel.com (Ayaz A Siddiqui) Date: Thu, 4 Jun 2020 23:56:58 +0530 Subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices Message-ID: <20200604182658.878417-1-ayaz.siddiqui@intel.com> In order to avoid functional breakage of mis-programmed applications that have grown to depend on unused MOCS entries, we are programming those entries to be equal to fully cached ("L3 + LLC") entry as per the recommendation from architecture team. These reserved and unspecified entries should not be used as they may be changed to less performant variants with better coherency in the future if more entries are needed. Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- 1 file changed, 89 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 632e08a4592b..1089bd5fdba2 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { L3_1_UC) static const struct drm_i915_mocs_entry tgl_mocs_table[] = { - /* Base - Error (Reserved for Non-Use) */ - MOCS_ENTRY(0, 0x0, 0x0), - /* Base - Reserved */ - MOCS_ENTRY(1, 0x0, 0x0), GEN11_MOCS_ENTRIES, @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { MOCS_ENTRY(61, LE_1_UC | LE_TC_1_LLC, L3_3_WB), + + /* NOTE: + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). + * These reserved entry should never be used, they may be chanaged + * to low performant variants with better coherency in the future if + * more entries are needed. + */ + + /* Reserved index 0 and 1 */ + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Reserved index 16 and 17 */ + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Reserved index 24 and 25 */ + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Unspecified indices 26 to 47 */ + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Unspecified indices 52 to 59 */ + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB) }; static const struct drm_i915_mocs_entry icl_mocs_table[] = { -- 2.26.2 From ville.syrjala at linux.intel.com Thu Jun 4 18:31:39 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 21:31:39 +0300 Subject: [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} In-Reply-To: <20200603211529.3005059-4-matthew.d.roper@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-4-matthew.d.roper@intel.com> Message-ID: <20200604183139.GC6112@intel.com> On Wed, Jun 03, 2020 at 02:15:17PM -0700, Matt Roper wrote: > Although RKL is a gen12 platform, it doesn't have the two extra > instances of the ABOX control register; we should only program > the single MBUS_ABOX_CTL on this platform. > > Bspec: 50096 > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 2c1ce50b572b..37847b3d733c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -4772,7 +4772,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) > MBUS_ABOX_BW_CREDIT(1); > > intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val); > - if (INTEL_GEN(dev_priv) >= 12) { > + if (INTEL_GEN(dev_priv) >= 12 && !IS_ROCKETLAKE(dev_priv)) { > intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val); > intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val); > } Can't find anyting definitive in bspec, so not 100% sure but since you say it gives unclaim reg errors it seems correct. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Though I think I'd like to see that HAS_ABOX() thing I suggested and use it here as well. > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From manasi.d.navare at intel.com Thu Jun 4 18:35:30 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 4 Jun 2020 11:35:30 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604152543.GU6112@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> Message-ID: <20200604183530.GB3922@intel.com> On Thu, Jun 04, 2020 at 06:25:43PM +0300, Ville Syrj?l? wrote: > On Wed, Jun 03, 2020 at 05:23:59PM -0700, Manasi Navare wrote: > > We have noticed that when link training fails the panel > > sends a long pulse indicating connector disconnect. In this case > > we need to reset the link parameters instead of continuing > > to use the fallback parameters since else this long pulse > > by the panel followed by a modeset request which was triggered by the userspace > > before getting the connector status as disconnected, will > > result into a modeset now using lower link rate/lane count values. > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1385 > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++-------- > > 1 file changed, 19 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 55fda074c0ad..f7af372647dd 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -6111,6 +6111,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > > intel_dp->edid_quirks = 0; > > } > > > > +static void > > +intel_dp_reset_link_params(struct intel_dp *intel_dp) > > +{ > > + /* Initial max link lane count */ > > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > + > > + /* Initial max link rate */ > > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > + > > + intel_dp->reset_link_params = false; > > +} > > + > > static int > > intel_dp_detect(struct drm_connector *connector, > > struct drm_modeset_acquire_ctx *ctx, > > @@ -6139,6 +6151,11 @@ intel_dp_detect(struct drm_connector *connector, > > memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); > > memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > > > + /*Reset the immutable VRR Capable property */ > > + drm_connector_set_vrr_capable_property(connector, > > + false); > > + intel_dp_reset_link_params(intel_dp); > > + > > Why would we care what those are when the sink is disconnected? We are noticing this happen in case the panel send this long pulse indicating status change to disconnected, while the modeset was already triggered by userspace in this case IGT, so the modeset continues right after i915_hotplug_work_fn so we need to reset all params which fixes the bug mentioned. Manasi > > > if (intel_dp->is_mst) { > > drm_dbg_kms(&dev_priv->drm, > > "MST device may have disappeared %d vs %d\n", > > @@ -6152,15 +6169,8 @@ intel_dp_detect(struct drm_connector *connector, > > goto out; > > } > > > > - if (intel_dp->reset_link_params) { > > - /* Initial max link lane count */ > > - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > - > > - /* Initial max link rate */ > > - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > - > > - intel_dp->reset_link_params = false; > > - } > > + if (intel_dp->reset_link_params) > > + intel_dp_reset_link_params(intel_dp); > > > > intel_dp_print_rates(intel_dp); > > > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Thu Jun 4 18:38:19 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 21:38:19 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604183530.GB3922@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> Message-ID: <20200604183819.GD6112@intel.com> On Thu, Jun 04, 2020 at 11:35:30AM -0700, Manasi Navare wrote: > On Thu, Jun 04, 2020 at 06:25:43PM +0300, Ville Syrj?l? wrote: > > On Wed, Jun 03, 2020 at 05:23:59PM -0700, Manasi Navare wrote: > > > We have noticed that when link training fails the panel > > > sends a long pulse indicating connector disconnect. In this case > > > we need to reset the link parameters instead of continuing > > > to use the fallback parameters since else this long pulse > > > by the panel followed by a modeset request which was triggered by the userspace > > > before getting the connector status as disconnected, will > > > result into a modeset now using lower link rate/lane count values. > > > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1385 > > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++-------- > > > 1 file changed, 19 insertions(+), 9 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 55fda074c0ad..f7af372647dd 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -6111,6 +6111,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > > > intel_dp->edid_quirks = 0; > > > } > > > > > > +static void > > > +intel_dp_reset_link_params(struct intel_dp *intel_dp) > > > +{ > > > + /* Initial max link lane count */ > > > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > + > > > + /* Initial max link rate */ > > > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > + > > > + intel_dp->reset_link_params = false; > > > +} > > > + > > > static int > > > intel_dp_detect(struct drm_connector *connector, > > > struct drm_modeset_acquire_ctx *ctx, > > > @@ -6139,6 +6151,11 @@ intel_dp_detect(struct drm_connector *connector, > > > memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); > > > memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > > > > > + /*Reset the immutable VRR Capable property */ > > > + drm_connector_set_vrr_capable_property(connector, > > > + false); > > > + intel_dp_reset_link_params(intel_dp); > > > + > > > > Why would we care what those are when the sink is disconnected? > > We are noticing this happen in case the panel send this long pulse indicating > status change to disconnected, while the modeset was already triggered by userspace > in this case IGT, so the modeset continues right after i915_hotplug_work_fn > so we need to reset all params which fixes the bug mentioned. Why did the link params get out of whack before hpd in the first place? > > Manasi > > > > > > if (intel_dp->is_mst) { > > > drm_dbg_kms(&dev_priv->drm, > > > "MST device may have disappeared %d vs %d\n", > > > @@ -6152,15 +6169,8 @@ intel_dp_detect(struct drm_connector *connector, > > > goto out; > > > } > > > > > > - if (intel_dp->reset_link_params) { > > > - /* Initial max link lane count */ > > > - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > - > > > - /* Initial max link rate */ > > > - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > - > > > - intel_dp->reset_link_params = false; > > > - } > > > + if (intel_dp->reset_link_params) > > > + intel_dp_reset_link_params(intel_dp); > > > > > > intel_dp_print_rates(intel_dp); > > > > > > -- > > > 2.19.1 > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From imre.deak at intel.com Thu Jun 4 18:44:59 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 21:44:59 +0300 Subject: [Intel-gfx] [PATCH v2 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <20200604184500.23730-1-imre.deak@intel.com> Currently MST on a port can get enabled/disabled from the hotplug work and get disabled from the short pulse work in a racy way. Fix this by relying on the MST state checking in the hotplug work and just schedule a hotplug work from the short pulse handler if some problem happened during the MST interrupt handling. This removes the explicit MST disabling in case of an AUX failure, but if AUX fails, then probably the detection will also fail during the scheduled hotplug work and it's not guaranteed that we'll see intermittent errors anyway. While at it also simplify the error checking of the MST interrupt handler. v2: - Convert intel_dp_check_mst_status() to return bool. (Ville) - Change the intel_dp->is_mst check to an assert, since after this patch the condition can't change after we checked it previously. - Document the return value from intel_dp_check_mst_status(). Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> (v1) Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 67 ++++++++++--------------- 1 file changed, 27 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 55fda074c0ad..4b6e7cf577dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5556,35 +5556,47 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) "Could not write test response to sink\n"); } -static int +/** + * intel_dp_check_mst_status - service any pending MST interrupts, check link status + * @intel_dp: Intel DP struct + * + * Read any pending MST interrupts, call MST core to handle these and ack the + * interrupts. Check if the main and AUX link state is ok. + * + * Returns: + * - %true if pending interrupts were serviced (or no interrupts were + * pending) w/o detecting an error condition. + * - %false if an error condition - like AUX failure or a loss of link - is + * detected, which needs servicing from the hotplug work. + */ +static bool intel_dp_check_mst_status(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - bool need_retrain = false; - - if (!intel_dp->is_mst) - return -EINVAL; + bool link_ok = true; + drm_WARN_ON_ONCE(&i915->drm, !intel_dp->is_mst); drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); for (;;) { u8 esi[DP_DPRX_ESI_LEN] = {}; - bool bret, handled; + bool handled; int retry; - bret = intel_dp_get_sink_irq_esi(intel_dp, esi); - if (!bret) { + if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { drm_dbg_kms(&i915->drm, "failed to get ESI - device may have failed\n"); - return -EINVAL; + link_ok = false; + + break; } /* check link status - esi[10] = 0x200c */ - if (intel_dp->active_mst_links > 0 && !need_retrain && + if (intel_dp->active_mst_links > 0 && link_ok && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { drm_dbg_kms(&i915->drm, "channel EQ not ok, retraining\n"); - need_retrain = true; + link_ok = false; } drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); @@ -5604,7 +5616,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) } } - return need_retrain; + return link_ok; } static bool @@ -7255,35 +7267,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) } if (intel_dp->is_mst) { - switch (intel_dp_check_mst_status(intel_dp)) { - case -EINVAL: - /* - * If we were in MST mode, and device is not - * there, get out of MST mode - */ - drm_dbg_kms(&i915->drm, - "MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, - intel_dp->mst_mgr.mst_state); - intel_dp->is_mst = false; - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, - intel_dp->is_mst); - - return IRQ_NONE; - case 1: - return IRQ_NONE; - default: - break; - } - } - - if (!intel_dp->is_mst) { - bool handled; - - handled = intel_dp_short_pulse(intel_dp); - - if (!handled) + if (!intel_dp_check_mst_status(intel_dp)) return IRQ_NONE; + } else if (!intel_dp_short_pulse(intel_dp)) { + return IRQ_NONE; } return IRQ_HANDLED; -- 2.23.1 From imre.deak at intel.com Thu Jun 4 18:45:00 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 21:45:00 +0300 Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200603211040.8190-3-imre.deak@intel.com> References: <20200603211040.8190-3-imre.deak@intel.com> Message-ID: <20200604184500.23730-2-imre.deak@intel.com> Some TypeC -> native DP adapters, at least the Club 3D CAC-1557 adapter, incorrectly filter out HPD short pulses with a duration less than ~540 usec, leading to MST probe failures. According to the DP Standard 2.0 section 5.1.4: - DP sinks should generate short pulses in the 500 usec -> 1 msec range - DP sources should detect short pulses in the 250 usec -> 2 msec range According to the DP Alt Mode on TypeC Standard section 3.9.2, adapters should detect and forward short pulses according to how sources should detect them as specified in the DP Standard (250 usec -> 2 msec). Based on the above filtering out short pulses with a duration less than 540 usec is incorrect. To make such adapters work add support for a driver polling on MST inerrupt flags, and wire this up in the i915 driver. The sink can clear an interrupt it raised after 110 msec if the source doesn't respond, so use a 50 msec poll period to avoid missing an interrupt. Polling of the MST interrupt flags is explicitly allowed by the DP Standard. This fixes MST probe failures I saw using this adapter and a DELL U2515H monitor. v2: - Fix the wait event timeout for the no-poll case. v3 (Ville): - Fix the short pulse duration limits in the commit log prescribed by the DP Standard. - Add code comment explaining why/how polling is used. - Factor out a helper to schedule the port's hpd irq handler and move it to the rest of hotplug handlers. - Document the new MST callback. - s/update_hpd_irq_state/poll_hpd_irq/ Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 32 ++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++ drivers/gpu/drm/i915/display/intel_hotplug.c | 18 +++++++++++ drivers/gpu/drm/i915/display/intel_hotplug.h | 2 ++ include/drm/drm_dp_mst_helper.h | 9 ++++++ 5 files changed, 68 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 5bc72e800b85..2a309fb2c4cc 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1178,11 +1178,37 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, struct drm_dp_sideband_msg_tx *txmsg) { struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; + unsigned long wait_timeout = msecs_to_jiffies(4000); + unsigned long wait_expires = jiffies + wait_timeout; int ret; - ret = wait_event_timeout(mgr->tx_waitq, - check_txmsg_state(mgr, txmsg), - (4 * HZ)); + for (;;) { + /* + * If the driver provides a way for this, change to + * poll-waiting for the MST reply interrupt if we didn't receive + * it for 50 msec. This would cater for cases where the HPD + * pulse signal got lost somewhere, even though the sink raised + * the corresponding MST interrupt correctly. One example is the + * Club 3D CAC-1557 TypeC -> DP adapter which for some reason + * filters out short pulses with a duration less than ~540 usec. + * + * The poll period is 50 msec to avoid missing an interrupt + * after the sink has cleared it (after a 110msec timeout + * since it raised the interrupt). + */ + ret = wait_event_timeout(mgr->tx_waitq, + check_txmsg_state(mgr, txmsg), + mgr->cbs->poll_hpd_irq ? + msecs_to_jiffies(50) : + wait_timeout); + + if (ret || !mgr->cbs->poll_hpd_irq || + time_after(jiffies, wait_expires)) + break; + + mgr->cbs->poll_hpd_irq(mgr); + } + mutex_lock(&mgr->qlock); if (ret > 0) { if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d18b406f2a7d..9be52643205d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -33,6 +33,7 @@ #include "intel_connector.h" #include "intel_ddi.h" #include "intel_display_types.h" +#include "intel_hotplug.h" #include "intel_dp.h" #include "intel_dp_mst.h" #include "intel_dpio_phy.h" @@ -765,8 +766,17 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo return NULL; } +static void +intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) +{ + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); + + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); +} + static const struct drm_dp_mst_topology_cbs mst_cbs = { .add_connector = intel_dp_add_mst_connector, + .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, }; static struct intel_dp_mst_encoder * diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 4f6f560e093e..664f88354101 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -347,6 +347,24 @@ static void i915_digport_work_func(struct work_struct *work) } } +/** + * intel_hpd_trigger_irq - trigger an hpd irq event for a port + * @dig_port: digital port + * + * Trigger an HPD interrupt event for the given port, emulating a short pulse + * generated by the sink, and schedule the dig port work to handle it. + */ +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + spin_lock_irq(&i915->irq_lock); + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); + spin_unlock_irq(&i915->irq_lock); + + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); +} + /* * Handle hotplug events outside the interrupt handler proper. */ diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h index 777b0743257e..a704d7c94d16 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.h +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h @@ -10,6 +10,7 @@ struct drm_i915_private; struct intel_connector; +struct intel_digital_port; struct intel_encoder; enum port; @@ -18,6 +19,7 @@ enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder, struct intel_connector *connector); void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 pin_mask, u32 long_mask); +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port); void intel_hpd_init(struct drm_i915_private *dev_priv); void intel_hpd_init_work(struct drm_i915_private *dev_priv); void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 9e1ffcd7cb68..b230ff6f7081 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -475,6 +475,15 @@ struct drm_dp_mst_topology_mgr; struct drm_dp_mst_topology_cbs { /* create a connector for a port */ struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); + /* + * Checks for any pending MST interrupts, passing them to MST core for + * processing, the same way an HPD IRQ pulse handler would do this. + * If provided MST core calls this callback from a poll-waiting loop + * when waiting for MST down message replies. The driver is expected + * to guard against a race between this callback and the driver's HPD + * IRQ pulse handler. + */ + void (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *mgr); }; #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) -- 2.23.1 From manasi.d.navare at intel.com Thu Jun 4 18:52:24 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 4 Jun 2020 11:52:24 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604183819.GD6112@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> Message-ID: <20200604185223.GC3922@intel.com> On Thu, Jun 04, 2020 at 09:38:19PM +0300, Ville Syrj?l? wrote: > On Thu, Jun 04, 2020 at 11:35:30AM -0700, Manasi Navare wrote: > > On Thu, Jun 04, 2020 at 06:25:43PM +0300, Ville Syrj?l? wrote: > > > On Wed, Jun 03, 2020 at 05:23:59PM -0700, Manasi Navare wrote: > > > > We have noticed that when link training fails the panel > > > > sends a long pulse indicating connector disconnect. In this case > > > > we need to reset the link parameters instead of continuing > > > > to use the fallback parameters since else this long pulse > > > > by the panel followed by a modeset request which was triggered by the userspace > > > > before getting the connector status as disconnected, will > > > > result into a modeset now using lower link rate/lane count values. > > > > > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1385 > > > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++-------- > > > > 1 file changed, 19 insertions(+), 9 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 55fda074c0ad..f7af372647dd 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -6111,6 +6111,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > > > > intel_dp->edid_quirks = 0; > > > > } > > > > > > > > +static void > > > > +intel_dp_reset_link_params(struct intel_dp *intel_dp) > > > > +{ > > > > + /* Initial max link lane count */ > > > > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > + > > > > + /* Initial max link rate */ > > > > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > > + > > > > + intel_dp->reset_link_params = false; > > > > +} > > > > + > > > > static int > > > > intel_dp_detect(struct drm_connector *connector, > > > > struct drm_modeset_acquire_ctx *ctx, > > > > @@ -6139,6 +6151,11 @@ intel_dp_detect(struct drm_connector *connector, > > > > memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); > > > > memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > > > > > > > + /*Reset the immutable VRR Capable property */ > > > > + drm_connector_set_vrr_capable_property(connector, > > > > + false); > > > > + intel_dp_reset_link_params(intel_dp); > > > > + > > > > > > Why would we care what those are when the sink is disconnected? > > > > We are noticing this happen in case the panel send this long pulse indicating > > status change to disconnected, while the modeset was already triggered by userspace > > in this case IGT, so the modeset continues right after i915_hotplug_work_fn > > so we need to reset all params which fixes the bug mentioned. > > Why did the link params get out of whack before hpd in the first place? > Most of the failures, we see the link training fails due to AUX timeouts and then link params fallback to lower values Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode with fallback values and return encoder config failure. So after reseting the params, the modeset happens with original values and that time link training passes. This is seen in all kms_atomic_transitions IGT tests Manasi > > > > Manasi > > > > > > > > > if (intel_dp->is_mst) { > > > > drm_dbg_kms(&dev_priv->drm, > > > > "MST device may have disappeared %d vs %d\n", > > > > @@ -6152,15 +6169,8 @@ intel_dp_detect(struct drm_connector *connector, > > > > goto out; > > > > } > > > > > > > > - if (intel_dp->reset_link_params) { > > > > - /* Initial max link lane count */ > > > > - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > - > > > > - /* Initial max link rate */ > > > > - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > > - > > > > - intel_dp->reset_link_params = false; > > > > - } > > > > + if (intel_dp->reset_link_params) > > > > + intel_dp_reset_link_params(intel_dp); > > > > > > > > intel_dp_print_rates(intel_dp); > > > > > > > > -- > > > > 2.19.1 > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Thu Jun 4 18:54:57 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 21:54:57 +0300 Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200604184500.23730-2-imre.deak@intel.com> References: <20200603211040.8190-3-imre.deak@intel.com> <20200604184500.23730-2-imre.deak@intel.com> Message-ID: <20200604185457.GF6112@intel.com> On Thu, Jun 04, 2020 at 09:45:00PM +0300, Imre Deak wrote: > Some TypeC -> native DP adapters, at least the Club 3D CAC-1557 adapter, > incorrectly filter out HPD short pulses with a duration less than > ~540 usec, leading to MST probe failures. > > According to the DP Standard 2.0 section 5.1.4: > - DP sinks should generate short pulses in the 500 usec -> 1 msec range > - DP sources should detect short pulses in the 250 usec -> 2 msec range > > According to the DP Alt Mode on TypeC Standard section 3.9.2, adapters > should detect and forward short pulses according to how sources should > detect them as specified in the DP Standard (250 usec -> 2 msec). > > Based on the above filtering out short pulses with a duration less than > 540 usec is incorrect. > > To make such adapters work add support for a driver polling on MST > inerrupt flags, and wire this up in the i915 driver. The sink can clear > an interrupt it raised after 110 msec if the source doesn't respond, so > use a 50 msec poll period to avoid missing an interrupt. Polling of the > MST interrupt flags is explicitly allowed by the DP Standard. > > This fixes MST probe failures I saw using this adapter and a DELL U2515H > monitor. > > v2: > - Fix the wait event timeout for the no-poll case. > v3 (Ville): > - Fix the short pulse duration limits in the commit log prescribed by the > DP Standard. > - Add code comment explaining why/how polling is used. > - Factor out a helper to schedule the port's hpd irq handler and move it > to the rest of hotplug handlers. > - Document the new MST callback. > - s/update_hpd_irq_state/poll_hpd_irq/ > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> lgtm Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 32 ++++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++ > drivers/gpu/drm/i915/display/intel_hotplug.c | 18 +++++++++++ > drivers/gpu/drm/i915/display/intel_hotplug.h | 2 ++ > include/drm/drm_dp_mst_helper.h | 9 ++++++ > 5 files changed, 68 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 5bc72e800b85..2a309fb2c4cc 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -1178,11 +1178,37 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, > struct drm_dp_sideband_msg_tx *txmsg) > { > struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; > + unsigned long wait_timeout = msecs_to_jiffies(4000); > + unsigned long wait_expires = jiffies + wait_timeout; > int ret; > > - ret = wait_event_timeout(mgr->tx_waitq, > - check_txmsg_state(mgr, txmsg), > - (4 * HZ)); > + for (;;) { > + /* > + * If the driver provides a way for this, change to > + * poll-waiting for the MST reply interrupt if we didn't receive > + * it for 50 msec. This would cater for cases where the HPD > + * pulse signal got lost somewhere, even though the sink raised > + * the corresponding MST interrupt correctly. One example is the > + * Club 3D CAC-1557 TypeC -> DP adapter which for some reason > + * filters out short pulses with a duration less than ~540 usec. > + * > + * The poll period is 50 msec to avoid missing an interrupt > + * after the sink has cleared it (after a 110msec timeout > + * since it raised the interrupt). > + */ > + ret = wait_event_timeout(mgr->tx_waitq, > + check_txmsg_state(mgr, txmsg), > + mgr->cbs->poll_hpd_irq ? > + msecs_to_jiffies(50) : > + wait_timeout); > + > + if (ret || !mgr->cbs->poll_hpd_irq || > + time_after(jiffies, wait_expires)) > + break; > + > + mgr->cbs->poll_hpd_irq(mgr); > + } > + > mutex_lock(&mgr->qlock); > if (ret > 0) { > if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d18b406f2a7d..9be52643205d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -33,6 +33,7 @@ > #include "intel_connector.h" > #include "intel_ddi.h" > #include "intel_display_types.h" > +#include "intel_hotplug.h" > #include "intel_dp.h" > #include "intel_dp_mst.h" > #include "intel_dpio_phy.h" > @@ -765,8 +766,17 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo > return NULL; > } > > +static void > +intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) > +{ > + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); > + > + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); > +} > + > static const struct drm_dp_mst_topology_cbs mst_cbs = { > .add_connector = intel_dp_add_mst_connector, > + .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, > }; > > static struct intel_dp_mst_encoder * > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c > index 4f6f560e093e..664f88354101 100644 > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c > @@ -347,6 +347,24 @@ static void i915_digport_work_func(struct work_struct *work) > } > } > > +/** > + * intel_hpd_trigger_irq - trigger an hpd irq event for a port > + * @dig_port: digital port > + * > + * Trigger an HPD interrupt event for the given port, emulating a short pulse > + * generated by the sink, and schedule the dig port work to handle it. > + */ > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + > + spin_lock_irq(&i915->irq_lock); > + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); > + spin_unlock_irq(&i915->irq_lock); > + > + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); > +} > + > /* > * Handle hotplug events outside the interrupt handler proper. > */ > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h > index 777b0743257e..a704d7c94d16 100644 > --- a/drivers/gpu/drm/i915/display/intel_hotplug.h > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h > @@ -10,6 +10,7 @@ > > struct drm_i915_private; > struct intel_connector; > +struct intel_digital_port; > struct intel_encoder; > enum port; > > @@ -18,6 +19,7 @@ enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder, > struct intel_connector *connector); > void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, > u32 pin_mask, u32 long_mask); > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port); > void intel_hpd_init(struct drm_i915_private *dev_priv); > void intel_hpd_init_work(struct drm_i915_private *dev_priv); > void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 9e1ffcd7cb68..b230ff6f7081 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -475,6 +475,15 @@ struct drm_dp_mst_topology_mgr; > struct drm_dp_mst_topology_cbs { > /* create a connector for a port */ > struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); > + /* > + * Checks for any pending MST interrupts, passing them to MST core for > + * processing, the same way an HPD IRQ pulse handler would do this. > + * If provided MST core calls this callback from a poll-waiting loop > + * when waiting for MST down message replies. The driver is expected > + * to guard against a race between this callback and the driver's HPD > + * IRQ pulse handler. > + */ > + void (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *mgr); > }; > > #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) > -- > 2.23.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 4 18:58:24 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 21:58:24 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604185223.GC3922@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> <20200604185223.GC3922@intel.com> Message-ID: <20200604185824.GG6112@intel.com> On Thu, Jun 04, 2020 at 11:52:24AM -0700, Manasi Navare wrote: > On Thu, Jun 04, 2020 at 09:38:19PM +0300, Ville Syrj?l? wrote: > > On Thu, Jun 04, 2020 at 11:35:30AM -0700, Manasi Navare wrote: > > > On Thu, Jun 04, 2020 at 06:25:43PM +0300, Ville Syrj?l? wrote: > > > > On Wed, Jun 03, 2020 at 05:23:59PM -0700, Manasi Navare wrote: > > > > > We have noticed that when link training fails the panel > > > > > sends a long pulse indicating connector disconnect. In this case > > > > > we need to reset the link parameters instead of continuing > > > > > to use the fallback parameters since else this long pulse > > > > > by the panel followed by a modeset request which was triggered by the userspace > > > > > before getting the connector status as disconnected, will > > > > > result into a modeset now using lower link rate/lane count values. > > > > > > > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1385 > > > > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++-------- > > > > > 1 file changed, 19 insertions(+), 9 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > index 55fda074c0ad..f7af372647dd 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > @@ -6111,6 +6111,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > > > > > intel_dp->edid_quirks = 0; > > > > > } > > > > > > > > > > +static void > > > > > +intel_dp_reset_link_params(struct intel_dp *intel_dp) > > > > > +{ > > > > > + /* Initial max link lane count */ > > > > > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > > + > > > > > + /* Initial max link rate */ > > > > > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > > > + > > > > > + intel_dp->reset_link_params = false; > > > > > +} > > > > > + > > > > > static int > > > > > intel_dp_detect(struct drm_connector *connector, > > > > > struct drm_modeset_acquire_ctx *ctx, > > > > > @@ -6139,6 +6151,11 @@ intel_dp_detect(struct drm_connector *connector, > > > > > memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); > > > > > memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > > > > > > > > > + /*Reset the immutable VRR Capable property */ > > > > > + drm_connector_set_vrr_capable_property(connector, > > > > > + false); > > > > > + intel_dp_reset_link_params(intel_dp); > > > > > + > > > > > > > > Why would we care what those are when the sink is disconnected? > > > > > > We are noticing this happen in case the panel send this long pulse indicating > > > status change to disconnected, while the modeset was already triggered by userspace > > > in this case IGT, so the modeset continues right after i915_hotplug_work_fn > > > so we need to reset all params which fixes the bug mentioned. > > > > Why did the link params get out of whack before hpd in the first place? > > > > Most of the failures, we see the link training fails due to AUX timeouts and then link params fallback to lower values > Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues > with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode > with fallback values and return encoder config failure. If the link training failed then clearly the sink didn't like us anymore anyway. So feels like resetting these here is just shifting some race window around a bit, but it could still fail if the sink still doesn't like us. Would be good if someone was able to figure out why the sink goes bad in the first place. > > So after reseting the params, the modeset happens with original values and that time link training passes. > This is seen in all kms_atomic_transitions IGT tests > > Manasi > > > > > > > Manasi > > > > > > > > > > > > if (intel_dp->is_mst) { > > > > > drm_dbg_kms(&dev_priv->drm, > > > > > "MST device may have disappeared %d vs %d\n", > > > > > @@ -6152,15 +6169,8 @@ intel_dp_detect(struct drm_connector *connector, > > > > > goto out; > > > > > } > > > > > > > > > > - if (intel_dp->reset_link_params) { > > > > > - /* Initial max link lane count */ > > > > > - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > > - > > > > > - /* Initial max link rate */ > > > > > - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > > > - > > > > > - intel_dp->reset_link_params = false; > > > > > - } > > > > > + if (intel_dp->reset_link_params) > > > > > + intel_dp_reset_link_params(intel_dp); > > > > > > > > > > intel_dp_print_rates(intel_dp); > > > > > > > > > > -- > > > > > 2.19.1 > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From Eugeniy.Paltsev at synopsys.com Thu Jun 4 19:00:21 2020 From: Eugeniy.Paltsev at synopsys.com (Eugeniy Paltsev) Date: Thu, 4 Jun 2020 19:00:21 +0000 Subject: [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny In-Reply-To: <CAKMK7uFLvV3=uhfnf=MreKBM==-gzXqx3NrV8KDA2D5sTAn2SQ@mail.gmail.com> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-54-daniel.vetter@ffwll.ch> <20200415094512.GA30444@ravnborg.org> <MWHPR12MB14532DA5713E3B579ABFE1F4A1DB0@MWHPR12MB1453.namprd12.prod.outlook.com> <CAKMK7uGDGgt8Cm_bFoyzeoP2CWyiUNdUwb7GL6Ohu3k0rP0p1w@mail.gmail.com> <20200428140842.GL3456981@phenom.ffwll.local> <CH2PR12MB3894B40C6D71435D3E759A34A1A20@CH2PR12MB3894.namprd12.prod.outlook.com> <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com> <20200604080507.GT20149@phenom.ffwll.local> <CY4PR1201MB01363EB95985A2C64ADA6841DE890@CY4PR1201MB0136.namprd12.prod.outlook.com>, <CAKMK7uFLvV3=uhfnf=MreKBM==-gzXqx3NrV8KDA2D5sTAn2SQ@mail.gmail.com> Message-ID: <CY4PR1201MB013642EB94E07AED91813A5FDE890@CY4PR1201MB0136.namprd12.prod.outlook.com> I've tested your change and one issue gone. However I still see kernel crash (due to invalid read in kernel mode by 0x0 address) on weston stop: ----------------------------------->8------------------------------------------- Oops Path: (null) CPU: 0 PID: 12 Comm: kworker/0:1 Not tainted 5.7.0-rc6-01594-g4ceda91a4176-dirty #6 Workqueue: events drm_mode_rmfb_work_fn Invalid Read @ 0x00000000 by insn @ drm_gem_fb_destroy+0x32/0x130 ECR: 0x00050100 EFA: 0x00000000 ERET: 0x813b9a76 STAT32: 0x80080602 [IE K ] BTA: 0x813b9a72 BLK: drm_gem_fb_destroy+0xc0/0x130 SP: 0x9f055ea4 FP: 0x00000000 LPS: 0x813560ec LPE: 0x813560f0 LPC: 0x00000000 r00: 0x00000000 r01: 0x9f6a6100 r02: 0x00000001 r03: 0x9fd5dde8 r04: 0x810f5de8 r05: 0x00000000 r06: 0x00000000 r07: 0x00000000 r08: 0x000000e1 r09: 0x00000000 r10: 0x00000000 r11: 0x000000e1 r12: 0x813b9b04 Stack Trace: drm_gem_fb_destroy+0x32/0x130 drm_framebuffer_remove+0x1d2/0x358 drm_mode_rmfb_work_fn+0x28/0x38 process_one_work+0x19a/0x358 worker_thread+0x2c4/0x494 kthread+0xec/0x100 ret_from_fork+0x18/0x1c ----------------------------------->8------------------------------------------- The stack traces may vary but always end in drm_gem_fb_destroy: ----------------------------------->8------------------------------------------- Stack Trace: drm_gem_fb_destroy+0x32/0x130 drm_mode_rmfb+0x10e/0x148 drm_ioctl_kernel+0x70/0xa0 drm_ioctl+0x284/0x410 ksys_ioctl+0xea/0xa3c EV_Trap+0xcc/0xd0 ----------------------------------->8------------------------------------------- Stack Trace: drm_gem_fb_destroy+0x32/0x130 drm_fb_release+0x66/0xb0 drm_file_free.part.11+0x112/0x1bc drm_release+0x80/0x120 __fput+0x98/0x1bc task_work_run+0x6e/0xa8 do_exit+0x2b4/0x7fc do_group_exit+0x2a/0x8c get_signal+0x9a/0x5f0 do_signal+0x86/0x23c resume_user_mode_begin+0x88/0xd0 ----------------------------------->8------------------------------------------- --- Eugeniy Paltsev ________________________________________ From: Daniel Vetter <daniel at ffwll.ch> Sent: Thursday, June 4, 2020 14:19 To: Eugeniy Paltsev Cc: Intel Graphics Development; DRI Development; Daniel Vetter; Sam Ravnborg; Alexey Brodkin Subject: Re: [PATCH 53/59] drm/arc: Move to drm/tiny Hi Eugeniy, Apologies, somehow I missed your mail. I looked at the code again, and I think I fumbled something. Does the below diff help to prevent the issues? Thanks, Daniel diff --git a/drivers/gpu/drm/tiny/arcpgu.c b/drivers/gpu/drm/tiny/arcpgu.c index 857812f25bec..33d812a5ad7f 100644 --- a/drivers/gpu/drm/tiny/arcpgu.c +++ b/drivers/gpu/drm/tiny/arcpgu.c @@ -228,6 +228,9 @@ static void arc_pgu_update(struct drm_simple_display_pipe *pipe, struct arcpgu_drm_private *arcpgu; struct drm_gem_cma_object *gem; + if (!pipe->plane.state->fb) + return; + arcpgu = pipe_to_arcpgu_priv(pipe); gem = drm_fb_cma_get_gem_obj(pipe->plane.state->fb, 0); arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr); -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - https://urldefense.com/v3/__http://blog.ffwll.ch__;!!A4F2R9G_pg!P0EvyJfMuDwqbeZmHZM5S9po30QWr4KgGrggRirNfgo7wrRXfnUO-8iq0AA4fQCW2WGPlDc$ From ville.syrjala at linux.intel.com Thu Jun 4 19:01:40 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 22:01:40 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604185824.GG6112@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> <20200604185223.GC3922@intel.com> <20200604185824.GG6112@intel.com> Message-ID: <20200604190140.GH6112@intel.com> On Thu, Jun 04, 2020 at 09:58:24PM +0300, Ville Syrj?l? wrote: > On Thu, Jun 04, 2020 at 11:52:24AM -0700, Manasi Navare wrote: > > On Thu, Jun 04, 2020 at 09:38:19PM +0300, Ville Syrj?l? wrote: > > > On Thu, Jun 04, 2020 at 11:35:30AM -0700, Manasi Navare wrote: > > > > On Thu, Jun 04, 2020 at 06:25:43PM +0300, Ville Syrj?l? wrote: > > > > > On Wed, Jun 03, 2020 at 05:23:59PM -0700, Manasi Navare wrote: > > > > > > We have noticed that when link training fails the panel > > > > > > sends a long pulse indicating connector disconnect. In this case > > > > > > we need to reset the link parameters instead of continuing > > > > > > to use the fallback parameters since else this long pulse > > > > > > by the panel followed by a modeset request which was triggered by the userspace > > > > > > before getting the connector status as disconnected, will > > > > > > result into a modeset now using lower link rate/lane count values. > > > > > > > > > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1385 > > > > > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++-------- > > > > > > 1 file changed, 19 insertions(+), 9 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > index 55fda074c0ad..f7af372647dd 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > @@ -6111,6 +6111,18 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > > > > > > intel_dp->edid_quirks = 0; > > > > > > } > > > > > > > > > > > > +static void > > > > > > +intel_dp_reset_link_params(struct intel_dp *intel_dp) > > > > > > +{ > > > > > > + /* Initial max link lane count */ > > > > > > + intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > > > + > > > > > > + /* Initial max link rate */ > > > > > > + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > > > > + > > > > > > + intel_dp->reset_link_params = false; > > > > > > +} > > > > > > + > > > > > > static int > > > > > > intel_dp_detect(struct drm_connector *connector, > > > > > > struct drm_modeset_acquire_ctx *ctx, > > > > > > @@ -6139,6 +6151,11 @@ intel_dp_detect(struct drm_connector *connector, > > > > > > memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); > > > > > > memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); > > > > > > > > > > > > + /*Reset the immutable VRR Capable property */ > > > > > > + drm_connector_set_vrr_capable_property(connector, > > > > > > + false); > > > > > > + intel_dp_reset_link_params(intel_dp); > > > > > > + > > > > > > > > > > Why would we care what those are when the sink is disconnected? > > > > > > > > We are noticing this happen in case the panel send this long pulse indicating > > > > status change to disconnected, while the modeset was already triggered by userspace > > > > in this case IGT, so the modeset continues right after i915_hotplug_work_fn > > > > so we need to reset all params which fixes the bug mentioned. > > > > > > Why did the link params get out of whack before hpd in the first place? > > > > > > > Most of the failures, we see the link training fails due to AUX timeouts and then link params fallback to lower values > > Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues > > with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode > > with fallback values and return encoder config failure. > > If the link training failed then clearly the sink didn't like us anymore > anyway. So feels like resetting these here is just shifting some race > window around a bit, but it could still fail if the sink still doesn't > like us. > > Would be good if someone was able to figure out why the sink goes bad in > the first place. Oh, and don't we now have Imre's "weird hpd happened in the middle of the test, don't trust the results" thing in igt? > > > > > So after reseting the params, the modeset happens with original values and that time link training passes. > > This is seen in all kms_atomic_transitions IGT tests > > > > Manasi > > > > > > > > > > Manasi > > > > > > > > > > > > > > > if (intel_dp->is_mst) { > > > > > > drm_dbg_kms(&dev_priv->drm, > > > > > > "MST device may have disappeared %d vs %d\n", > > > > > > @@ -6152,15 +6169,8 @@ intel_dp_detect(struct drm_connector *connector, > > > > > > goto out; > > > > > > } > > > > > > > > > > > > - if (intel_dp->reset_link_params) { > > > > > > - /* Initial max link lane count */ > > > > > > - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > > > - > > > > > > - /* Initial max link rate */ > > > > > > - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); > > > > > > - > > > > > > - intel_dp->reset_link_params = false; > > > > > > - } > > > > > > + if (intel_dp->reset_link_params) > > > > > > + intel_dp_reset_link_params(intel_dp); > > > > > > > > > > > > intel_dp_print_rates(intel_dp); > > > > > > > > > > > > -- > > > > > > 2.19.1 > > > > > > > > > > -- > > > > > Ville Syrj?l? > > > > > Intel > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 4 19:06:12 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 4 Jun 2020 22:06:12 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> Message-ID: <20200604190612.GI6112@intel.com> On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 40 ++++++++++++++++++++++++++------- > 1 file changed, 32 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 7223367171d1..44663e8ac9a1 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) > struct drm_i915_private *dev_priv = to_i915(dev); > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); > enum pipe pipe = crtc->pipe; > - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; > + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value, trans_ddi_port_mask; > + enum port port = intel_dig_port->base.port; > + i915_reg_t dp_tp_reg; > + > + if (IS_ELKHARTLAKE(dev_priv)) { > + dp_tp_reg = DP_TP_CTL(port); > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > + } else if (IS_TIGERLAKE(dev_priv)) { > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > + } > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > TRANS_DDI_FUNC_CTL(pipe)); > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > - TGL_TRANS_DDI_PORT_MASK); > + trans_ddi_port_mask); > trans_conf_value &= ~PIPECONF_ENABLE; > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > trans_ddi_func_ctl_value); > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); All this ad-hoc modeset code really should not exist. It's going to have different bugs than the norma modeset paths, so compliance testing this special code proves absolutely nothing about the normal modeset code. IMO someone needs to take up the task of rewrtiting all this to just perform normal modesets. > } > > static void > @@ -5497,20 +5507,28 @@ intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) > enum port port = intel_dig_port->base.port; > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); > enum pipe pipe = crtc->pipe; > - u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; > + u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value, trans_ddi_sel_port; > + i915_reg_t dp_tp_reg; > + > + if (IS_ELKHARTLAKE(dev_priv)) { > + dp_tp_reg = DP_TP_CTL(port); > + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); > + } else if (IS_TIGERLAKE(dev_priv)) { > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); > + } > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > TRANS_DDI_FUNC_CTL(pipe)); > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > - > trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | > - TGL_TRANS_DDI_SELECT_PORT(port); > + trans_ddi_sel_port; > trans_conf_value |= PIPECONF_ENABLE; > dp_tp_ctl_value |= DP_TP_CTL_ENABLE; > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > trans_ddi_func_ctl_value); > } > @@ -5557,6 +5575,7 @@ static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) > static void intel_dp_handle_test_request(struct intel_dp *intel_dp) > { > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + struct drm_i915_private *dev_priv = i915; > u8 response = DP_TEST_NAK; > u8 request = 0; > int status; > @@ -5582,6 +5601,11 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) > response = intel_dp_autotest_edid(intel_dp); > break; > case DP_TEST_LINK_PHY_TEST_PATTERN: > + if (!IS_ELKHARTLAKE(dev_priv) || !IS_TIGERLAKE(dev_priv)) { > + drm_dbg_kms(&i915->drm, > + "PHY compliance for platform not supported\n"); > + return; > + } > drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); > response = intel_dp_autotest_phy_pattern(intel_dp); > break; > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Thu Jun 4 19:08:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 19:08:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Initialize_reserved_and_unspecified_MOCS_indices?= In-Reply-To: <20200604182658.878417-1-ayaz.siddiqui@intel.com> References: <20200604182658.878417-1-ayaz.siddiqui@intel.com> Message-ID: <159129773865.14552.2370079157351104305@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Initialize reserved and unspecified MOCS indices URL : https://patchwork.freedesktop.org/series/78012/ State : success == Summary == CI Bug Log - changes from CI_DRM_8585 -> Patchwork_17875 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/index.html Known issues ------------ Here are the changes found in Patchwork_17875 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-apl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-apl-guc/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-apl-guc/igt at i915_module_load@reload.html * igt at kms_frontbuffer_tracking@basic: - fi-tgl-y: [PASS][3] -> [DMESG-FAIL][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-y/igt at kms_frontbuffer_tracking@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-y/igt at kms_frontbuffer_tracking@basic.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][9] ([i915#1993]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-icl-y/igt at i915_selftest@live at execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-tgl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-y/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-y/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-dsi/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-tgl-dsi/igt at kms_pipe_crc_basic@read-crc-pipe-c.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8585 -> Patchwork_17875 CI-20190529: 20190529 CI_DRM_8585: 3aef9a510cfe66ba71ed397e91c517402f7c26ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17875: 74e4956ad45f89c7f37ff7f79108099c834ff6d8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 74e4956ad45f drm/i915/gt: Initialize reserved and unspecified MOCS indices == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/index.html From imre.deak at intel.com Thu Jun 4 19:08:58 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 22:08:58 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604190140.GH6112@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> <20200604185223.GC3922@intel.com> <20200604185824.GG6112@intel.com> <20200604190140.GH6112@intel.com> Message-ID: <20200604190858.GE15427@ideak-desk.fi.intel.com> On Thu, Jun 04, 2020 at 10:01:40PM +0300, Ville Syrj?l? wrote: > [...] > > > Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues > > > with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode > > > with fallback values and return encoder config failure. > > > > If the link training failed then clearly the sink didn't like us anymore > > anyway. So feels like resetting these here is just shifting some race > > window around a bit, but it could still fail if the sink still doesn't > > like us. > > > > Would be good if someone was able to figure out why the sink goes bad in > > the first place. > > Oh, and don't we now have Imre's "weird hpd happened in the middle of > the test, don't trust the results" thing in igt? An LG and IIyama monitor this happens on disconnect and reconnect after waking from an idle state when modesetting them, not sure if it's the same case. --Imre From manasi.d.navare at intel.com Thu Jun 4 19:20:39 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 4 Jun 2020 12:20:39 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604190858.GE15427@ideak-desk.fi.intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> <20200604185223.GC3922@intel.com> <20200604185824.GG6112@intel.com> <20200604190140.GH6112@intel.com> <20200604190858.GE15427@ideak-desk.fi.intel.com> Message-ID: <20200604192039.GD3922@intel.com> On Thu, Jun 04, 2020 at 10:08:58PM +0300, Imre Deak wrote: > On Thu, Jun 04, 2020 at 10:01:40PM +0300, Ville Syrj?l? wrote: > > [...] > > > > Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues > > > > with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode > > > > with fallback values and return encoder config failure. > > > > > > If the link training failed then clearly the sink didn't like us anymore > > > anyway. So feels like resetting these here is just shifting some race > > > window around a bit, but it could still fail if the sink still doesn't > > > like us. > > > > > > Would be good if someone was able to figure out why the sink goes bad in > > > the first place. > > > > Oh, and don't we now have Imre's "weird hpd happened in the middle of > > the test, don't trust the results" thing in igt? > > An LG and IIyama monitor this happens on disconnect and reconnect after > waking from an idle state when modesetting them, not sure if it's the > same case. Well in this case, it happens just after link training failure due to some AUX timeouts then looks like the panel detects that the link was not enabled and sends this HPD which puts us into connector status changing from connected to disconnected. But in IGT, we dont get any uevent so we dont reprobe and continue with the next igt_display_commit. So should we in IGT in kms_atomic_transitions, plane-all-modeset-transitions subtest, should we check the connector status everytime before back to back commit calls? Like I think in real use case, after a link failure the userspace would get a uevent and respond to it by reprobing a connector, but we dont do that in IGT so these random link failures cause issues like in here. Manasi > > --Imre From imre.deak at intel.com Thu Jun 4 19:23:40 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 22:23:40 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604190858.GE15427@ideak-desk.fi.intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> <20200604185223.GC3922@intel.com> <20200604185824.GG6112@intel.com> <20200604190140.GH6112@intel.com> <20200604190858.GE15427@ideak-desk.fi.intel.com> Message-ID: <20200604192340.GF15427@ideak-desk.fi.intel.com> On Thu, Jun 04, 2020 at 10:08:58PM +0300, Imre Deak wrote: > On Thu, Jun 04, 2020 at 10:01:40PM +0300, Ville Syrj?l? wrote: > > [...] > > > > Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues > > > > with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode > > > > with fallback values and return encoder config failure. > > > > > > If the link training failed then clearly the sink didn't like us anymore > > > anyway. So feels like resetting these here is just shifting some race > > > window around a bit, but it could still fail if the sink still doesn't > > > like us. > > > > > > Would be good if someone was able to figure out why the sink goes bad in > > > the first place. > > > > Oh, and don't we now have Imre's "weird hpd happened in the middle of > > the test, don't trust the results" thing in igt? > > An LG and IIyama monitor this happens on disconnect and reconnect after > waking from an idle state when modesetting them, not sure if it's the > same case. Manasi, could you try if a modeset on the monitor after it has been disabled for a while always results in a long HPD pulse a few seconds after the modeset? If so does this also happen when you just modeset in a sequence from one mode to the other not letting the monitor idle? The same monitor should be also tested then with the above sequences on older platforms if it behaves the same on those too. > > --Imre > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Thu Jun 4 19:36:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 19:36:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBk?= =?utf-8?q?evm=5Fdrm=5Fdev=5Falloc=2C_v2_=28rev3=29?= In-Reply-To: <20200415074034.175360-1-daniel.vetter@ffwll.ch> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> Message-ID: <159129936425.14555.12402909729104470952@emeril.freedesktop.org> == Series Details == Series: devm_drm_dev_alloc, v2 (rev3) URL : https://patchwork.freedesktop.org/series/75956/ State : failure == Summary == Applying: drm: Add devm_drm_dev_alloc macro error: sha1 information is lacking or useless (drivers/gpu/drm/drm_drv.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm: Add devm_drm_dev_alloc macro When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Thu Jun 4 19:36:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 19:36:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/3=5D_drm/i915/dp=5Fmst=3A_Fix_disab?= =?utf-8?q?ling_MST_on_a_port_=28rev4=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159129937043.14554.17290504257366763304@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev4) URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8585 -> Patchwork_17876 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/index.html Known issues ------------ Here are the changes found in Patchwork_17876 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][5] ([i915#1993]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-icl-y/igt at i915_selftest@live at execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-y/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-tgl-y/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-tgl-dsi/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-tgl-dsi/igt at kms_pipe_crc_basic@read-crc-pipe-c.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8585 -> Patchwork_17876 CI-20190529: 20190529 CI_DRM_8585: 3aef9a510cfe66ba71ed397e91c517402f7c26ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17876: 510b25246e2201dfbad5a4a34e0cec24f91db43e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 510b25246e22 drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses fb42f8a70d4f drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() 90c80197a498 drm/i915/dp_mst: Fix disabling MST on a port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/index.html From manasi.d.navare at intel.com Thu Jun 4 19:40:20 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 4 Jun 2020 12:40:20 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604192340.GF15427@ideak-desk.fi.intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> <20200604185223.GC3922@intel.com> <20200604185824.GG6112@intel.com> <20200604190140.GH6112@intel.com> <20200604190858.GE15427@ideak-desk.fi.intel.com> <20200604192340.GF15427@ideak-desk.fi.intel.com> Message-ID: <20200604194020.GE3922@intel.com> On Thu, Jun 04, 2020 at 10:23:40PM +0300, Imre Deak wrote: > On Thu, Jun 04, 2020 at 10:08:58PM +0300, Imre Deak wrote: > > On Thu, Jun 04, 2020 at 10:01:40PM +0300, Ville Syrj?l? wrote: > > > [...] > > > > > Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues > > > > > with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode > > > > > with fallback values and return encoder config failure. > > > > > > > > If the link training failed then clearly the sink didn't like us anymore > > > > anyway. So feels like resetting these here is just shifting some race > > > > window around a bit, but it could still fail if the sink still doesn't > > > > like us. > > > > > > > > Would be good if someone was able to figure out why the sink goes bad in > > > > the first place. > > > > > > Oh, and don't we now have Imre's "weird hpd happened in the middle of > > > the test, don't trust the results" thing in igt? > > > > An LG and IIyama monitor this happens on disconnect and reconnect after > > waking from an idle state when modesetting them, not sure if it's the > > same case. > > Manasi, could you try if a modeset on the monitor after it has been > disabled for a while always results in a long HPD pulse a few seconds > after the modeset? If so does this also happen when you just modeset in > a sequence from one mode to the other not letting the monitor idle? The > same monitor should be also tested then with the above sequences on > older platforms if it behaves the same on those too. > This test has been passing on older ICL platforms. But on TGL we do see these AUX E timeouts once in a while which recover on their own for the next modeset. Any idea why these spurious AUX timeouts and how I can possibly rootcause why these timeouts are seen only with AUX E? Manasi > > > > --Imre > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From imre.deak at intel.com Thu Jun 4 19:49:35 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 4 Jun 2020 22:49:35 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect In-Reply-To: <20200604194020.GE3922@intel.com> References: <20200604002359.17128-1-manasi.d.navare@intel.com> <20200604152543.GU6112@intel.com> <20200604183530.GB3922@intel.com> <20200604183819.GD6112@intel.com> <20200604185223.GC3922@intel.com> <20200604185824.GG6112@intel.com> <20200604190140.GH6112@intel.com> <20200604190858.GE15427@ideak-desk.fi.intel.com> <20200604192340.GF15427@ideak-desk.fi.intel.com> <20200604194020.GE3922@intel.com> Message-ID: <20200604194935.GG15427@ideak-desk.fi.intel.com> On Thu, Jun 04, 2020 at 12:40:20PM -0700, Manasi Navare wrote: > On Thu, Jun 04, 2020 at 10:23:40PM +0300, Imre Deak wrote: > > On Thu, Jun 04, 2020 at 10:08:58PM +0300, Imre Deak wrote: > > > On Thu, Jun 04, 2020 at 10:01:40PM +0300, Ville Syrj?l? wrote: > > > > [...] > > > > > > Then we get this hpd, in this case if we dont reset the param to max values, prev triggered modeset continues > > > > > > with fallback values but since connector probe doesnt happen again through IGT, it tries the same mode > > > > > > with fallback values and return encoder config failure. > > > > > > > > > > If the link training failed then clearly the sink didn't like us anymore > > > > > anyway. So feels like resetting these here is just shifting some race > > > > > window around a bit, but it could still fail if the sink still doesn't > > > > > like us. > > > > > > > > > > Would be good if someone was able to figure out why the sink goes bad in > > > > > the first place. > > > > > > > > Oh, and don't we now have Imre's "weird hpd happened in the middle of > > > > the test, don't trust the results" thing in igt? > > > > > > An LG and IIyama monitor this happens on disconnect and reconnect after > > > waking from an idle state when modesetting them, not sure if it's the > > > same case. > > > > Manasi, could you try if a modeset on the monitor after it has been > > disabled for a while always results in a long HPD pulse a few seconds > > after the modeset? If so does this also happen when you just modeset in > > a sequence from one mode to the other not letting the monitor idle? The > > same monitor should be also tested then with the above sequences on > > older platforms if it behaves the same on those too. > > > > This test has been passing on older ICL platforms. But on TGL we do > see these AUX E timeouts once in a while which recover on their own > for the next modeset. Any idea why these spurious AUX timeouts and how > I can possibly rootcause why these timeouts are seen only with AUX E? If the monitor is in a disconnected state as you described, then AUX will fail too. So you need to root cause why the monitor gets disconnected. One possibility for that is what I described above. You can't really make a conclusion on a test passing on ICL and not on TGL, the timing can be different. You'd need to check if a disconnect happens due to long HPD pulse when using the same monitor with the sequences I described above, both on TGL and then also on ICL. > > Manasi > > > > > > > --Imre > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From khaled.almahallawy at intel.com Thu Jun 4 20:01:03 2020 From: khaled.almahallawy at intel.com (Almahallawy, Khaled) Date: Thu, 4 Jun 2020 20:01:03 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200604190612.GI6112@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> Message-ID: <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > ++++++++++++++++++++++++++------- > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 7223367171d1..44663e8ac9a1 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > intel_dp *intel_dp) > > struct drm_i915_private *dev_priv = to_i915(dev); > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > >base.base.crtc); > > enum pipe pipe = crtc->pipe; > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > dp_tp_ctl_value; > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > dp_tp_ctl_value, trans_ddi_port_mask; > > + enum port port = intel_dig_port->base.port; > > + i915_reg_t dp_tp_reg; > > + > > + if (IS_ELKHARTLAKE(dev_priv)) { > > + dp_tp_reg = DP_TP_CTL(port); > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > + } else if (IS_TIGERLAKE(dev_priv)) { > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > + } > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > TRANS_DDI_FUNC_CTL(pip > > e)); > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > - TGL_TRANS_DDI_PORT_MASK); > > + trans_ddi_port_mask); > > trans_conf_value &= ~PIPECONF_ENABLE; > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > trans_ddi_func_ctl_value); > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > All this ad-hoc modeset code really should not exist. It's going to > have different bugs than the norma modeset paths, so compliance > testing > this special code proves absolutely nothing about the normal modeset > code. IMO someone needs to take up the task of rewrtiting all this to > just perform normal modesets. Agree. I've just found that we get kernel NULL pointer dereference and panic when we try to access to_intel_crtc(intel_dig_port- >base.base.crtc). This is because we didn't realize when we developed the code that test scope has an option to send PHY test request on Long HPD. Current desing assume PHY test request on short HPD. Because of that we got the following error [ 106.810882] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] digital hpd on [ENCODER:308:DDI F] - long [ 106.810916] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 9 - cnt: 10 [ 106.811026] i915 0000:00:02.0: [drm:intel_dp_hpd_pulse [i915]] got hpd irq on [ENCODER:308:DDI F] - long [ 106.811095] i915 0000:00:02.0: [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions [ 106.811184] i915 0000:00:02.0: [drm:i915_hotplug_work_func [i915]] Connector DP-3 (pin 9) received hotplug event. (retry 0) [ 106.811227] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [CONNECTOR:309:DP-3] [ 106.811292] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling TC cold off [ 106.811365] i915 0000:00:02.0: [drm:tgl_tc_cold_request [i915]] TC cold block succeeded [ 106.811489] i915 0000:00:02.0: [drm:__intel_tc_port_lock [i915]] Port F/TC#3: TC port mode reset (tbt-alt -> dp-alt) [ 106.811663] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] enabling AUX F TC3 [ 106.812449] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00000 AUX -> (ret= 15) 12 14 04 80 00 00 01 00 00 00 00 00 00 00 00 [ 106.812484] i915 0000:00:02.0: [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 04 80 00 00 01 00 00 00 00 00 00 00 00 [ 106.813266] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00400 AUX -> (ret= 12) 00 00 00 00 00 00 00 00 00 00 00 00 [ 106.813271] [drm:drm_dp_read_desc] DP sink: OUI 00-00-00 dev-ID HW- rev 0.0 SW-rev 0.0 quirks 0x0000 [ 106.813891] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00200 AUX -> (ret= 1) 01 [ 106.813940] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 [ 106.813974] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 [ 106.814007] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 [ 106.814550] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00021 AUX -> (ret= 1) 00 [ 106.814583] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] [ENCODER:308:DDI F] MST support: port: yes, sink: no, modparam: yes ..... [ 106.927291] i915 0000:00:02.0: [drm:intel_dp_check_service_irq [i915]] PHY_PATTERN test requested [ 106.927897] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00219 AUX -> (ret= 1) 0a [ 106.928507] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00220 AUX -> (ret= 1) 04 [ 106.929143] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00248 AUX -> (ret= 1) 00 [ 106.929824] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00202 AUX -> (ret= 6) 00 00 80 00 00 00 [ 106.929830] BUG: kernel NULL pointer dereference, address: 0000000000000578 [ 106.936809] #PF: supervisor read access in kernel mode [ 106.941953] #PF: error_code(0x0000) - not-present page [ 106.947082] PGD 0 P4D 0 [ 106.949643] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 106.954010] CPU: 6 PID: 200 Comm: kworker/6:2 Not tainted 5.7.0-rc7- CI-CI_DRM_8566+ #5 [ 106.975251] Workqueue: events i915_hotplug_work_func [i915] [ 106.980887] RIP: 0010:intel_dp_process_phy_request+0x94/0x5a0 [i915] [ 106.987239] Code: 48 83 c4 20 5b 5d 41 5c 41 5d 41 5e 41 5f c3 48 8d 74 24 12 4c 89 f7 e8 3a 3e 00 00 49 8b 86 28 ff ff ff 49 8b 9e d8 fe ff ff <48> 63 80 78 05 00 00 8b 93 54 0d 00 00 48 8d ab e8 0e 00 00 48 89 [ 107.005890] RSP: 0018:ffffc9000046fb20 EFLAGS: 00010246 I plan to temporarily fix this issue by ignoreing scope request on long HPD, until we have modeset based implementation. > > } > > > > static void > > @@ -5497,20 +5507,28 @@ intel_dp_autotest_phy_ddi_enable(struct > > intel_dp *intel_dp, uint8_t lane_cnt) > > enum port port = intel_dig_port->base.port; > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > >base.base.crtc); > > enum pipe pipe = crtc->pipe; > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > dp_tp_ctl_value; > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > dp_tp_ctl_value, trans_ddi_sel_port; > > + i915_reg_t dp_tp_reg; > > + > > + if (IS_ELKHARTLAKE(dev_priv)) { > > + dp_tp_reg = DP_TP_CTL(port); > > + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); > > + } else if (IS_TIGERLAKE(dev_priv)) { > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); > > + } > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > TRANS_DDI_FUNC_CTL(pip > > e)); > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > - > > trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | > > - TGL_TRANS_DDI_SELECT_PORT(port); > > + trans_ddi_sel_port; > > trans_conf_value |= PIPECONF_ENABLE; > > dp_tp_ctl_value |= DP_TP_CTL_ENABLE; > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > trans_ddi_func_ctl_value); > > } > > @@ -5557,6 +5575,7 @@ static u8 > > intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) > > static void intel_dp_handle_test_request(struct intel_dp > > *intel_dp) > > { > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > + struct drm_i915_private *dev_priv = i915; > > u8 response = DP_TEST_NAK; > > u8 request = 0; > > int status; > > @@ -5582,6 +5601,11 @@ static void > > intel_dp_handle_test_request(struct intel_dp *intel_dp) > > response = intel_dp_autotest_edid(intel_dp); > > break; > > case DP_TEST_LINK_PHY_TEST_PATTERN: > > + if (!IS_ELKHARTLAKE(dev_priv) || > > !IS_TIGERLAKE(dev_priv)) { > > + drm_dbg_kms(&i915->drm, > > + "PHY compliance for platform not > > supported\n"); > > + return; > > + } > > drm_dbg_kms(&i915->drm, "PHY_PATTERN test > > requested\n"); > > response = intel_dp_autotest_phy_pattern(intel_dp); > > break; > > -- > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > From khaled.almahallawy at intel.com Thu Jun 4 20:05:36 2020 From: khaled.almahallawy at intel.com (Almahallawy, Khaled) Date: Thu, 4 Jun 2020 20:05:36 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Add HBR and HBR2+ voltage swing table In-Reply-To: <20200602205424.138143-1-jose.souza@intel.com> References: <20200602205424.138143-1-jose.souza@intel.com> Message-ID: <127fff4c24554a8a269590a5f49f38101032a0b8.camel@intel.com> On Tue, 2020-06-02 at 13:54 -0700, Jos? Roberto de Souza wrote: > As latest update we have now 2 voltage swing tables for DP over DKL > PHY with only one difference in Level 0 pre-emphasis 3. > So with 2 tables for DP is time to have one single function to return > all DKL voltage swing tables. > > BSpec: 49292 > Cc: Khaled Almahallawy <khaled.almahallawy at intel.com> > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 50 ++++++++++++++++++++ > ---- > 1 file changed, 42 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index cd211f48c401..763d76056ca9 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -641,6 +641,20 @@ static const struct tgl_dkl_phy_ddi_buf_trans > tgl_dkl_phy_dp_ddi_trans[] = { > { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB > */ > { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 > dB */ > { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB > */ > + { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 > dB */ > + { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB > */ > + { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 > dB */ > + { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB > */ > + { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB > */ > + { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 > dB */ > + { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB > HDMI default */ > +}; > + > +static const struct tgl_dkl_phy_ddi_buf_trans > tgl_dkl_phy_dp_ddi_trans_hbr2[] = { > + /* VS pre-emp Non-trans mV Pre- > emph dB */ > + { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB > */ > + { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 > dB */ > + { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB > */ > { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 > dB */ > { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB > */ > { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 > dB */ > @@ -1014,6 +1028,22 @@ tgl_get_combo_buf_trans(struct > drm_i915_private *dev_priv, int type, int rate, > return tgl_combo_phy_ddi_translations_dp_hbr; > } > > +static const struct tgl_dkl_phy_ddi_buf_trans * > +tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, > int rate, > + int *n_entries) > +{ > + if (type == INTEL_OUTPUT_HDMI) { > + *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); > + return tgl_dkl_phy_hdmi_ddi_trans; > + } else if (rate > 270000) { > + *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); > + return tgl_dkl_phy_dp_ddi_trans_hbr2; > + } > + > + *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); > + return tgl_dkl_phy_dp_ddi_trans; > +} > + > static int intel_ddi_hdmi_level(struct intel_encoder *encoder) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > @@ -1025,7 +1055,8 @@ static int intel_ddi_hdmi_level(struct > intel_encoder *encoder) > tgl_get_combo_buf_trans(dev_priv, > INTEL_OUTPUT_HDMI, > 0, &n_entries); > else > - n_entries = > ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); > + tgl_get_dkl_buf_trans(dev_priv, > INTEL_OUTPUT_HDMI, 0, > + &n_entries); > default_entry = n_entries - 1; > } else if (INTEL_GEN(dev_priv) == 11) { > if (intel_phy_is_combo(dev_priv, phy)) > @@ -2108,7 +2139,8 @@ u8 intel_ddi_dp_voltage_max(struct > intel_encoder *encoder) > tgl_get_combo_buf_trans(dev_priv, encoder- > >type, > intel_dp->link_rate, > &n_entries); > else > - n_entries = > ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); > + tgl_get_dkl_buf_trans(dev_priv, encoder->type, > + intel_dp->link_rate, > &n_entries); > } else if (INTEL_GEN(dev_priv) == 11) { > if (IS_ELKHARTLAKE(dev_priv)) > ehl_get_combo_buf_trans(dev_priv, encoder- > >type, > @@ -2585,15 +2617,17 @@ tgl_dkl_phy_ddi_vswing_sequence(struct > intel_encoder *encoder, int link_clock, > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder- > >port); > const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; > u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; > + int rate = 0; > > - if (encoder->type == INTEL_OUTPUT_HDMI) { > - n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); > - ddi_translations = tgl_dkl_phy_hdmi_ddi_trans; > - } else { > - n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); > - ddi_translations = tgl_dkl_phy_dp_ddi_trans; > + if (encoder->type != INTEL_OUTPUT_HDMI) { > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + rate = intel_dp->link_rate; > } > > + ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder- > >type, rate, > + &n_entries); > + > if (level >= n_entries) > level = n_entries - 1; > This implementation passes DPoC1.4a Phy compliance PLTPAT tests. Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com> Reviewed-by: Khaled Almahallawy<khaled.almahallawy at intel.com> From jose.souza at intel.com Thu Jun 4 20:43:25 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 4 Jun 2020 20:43:25 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Add_HBR_and_HBR2+_voltage_swing_table?= In-Reply-To: <159116370185.12267.4347121232376396516@emeril.freedesktop.org> References: <20200602205424.138143-1-jose.souza@intel.com> <159116370185.12267.4347121232376396516@emeril.freedesktop.org> Message-ID: <1cb4c98a3b9612158b6390ee7501b4bd7515a08e.camel@intel.com> On Wed, 2020-06-03 at 05:55 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl: Add HBR and HBR2+ voltage swing table > URL : https://patchwork.freedesktop.org/series/77934/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_8573_full -> Patchwork_17847_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. Thanks for the review Khaled, pushed to dinq. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17847_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: > - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl3/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html > > * igt at i915_pm_rpm@system-suspend-execbuf: > - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([i915#1185] / [i915#189]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb4/igt at i915_pm_rpm@system-suspend-execbuf.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb4/igt at i915_pm_rpm@system-suspend-execbuf.html > > * igt at i915_suspend@forcewake: > - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl3/igt at i915_suspend@forcewake.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-kbl4/igt at i915_suspend@forcewake.html > > * igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding: > - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#54] / [i915#93] / [i915#95]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x64-sliding.html > > * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: > - shard-apl: [PASS][9] -> [FAIL][10] ([i915#70] / [i915#95]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl2/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl8/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html > > * igt at kms_fbcon_fbt@fbc-suspend: > - shard-apl: [PASS][11] -> [FAIL][12] ([i915#1525] / [i915#95]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl6/igt at kms_fbcon_fbt@fbc-suspend.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl2/igt at kms_fbcon_fbt@fbc-suspend.html > > * igt at kms_hdr@bpc-switch: > - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_hdr@bpc-switch.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl8/igt at kms_hdr@bpc-switch.html > > * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: > - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt at kms_psr@psr2_dpms: > - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at kms_psr@psr2_dpms.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb7/igt at kms_psr@psr2_dpms.html > > > #### Possible fixes #### > > * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: > - shard-skl: [FAIL][21] ([i915#1528]) -> [PASS][22] > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl3/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html > > * {igt at i915_selftest@perf at request}: > - shard-tglb: [DMESG-FAIL][23] ([i915#1823]) -> [PASS][24] > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-tglb5/igt at i915_selftest@perf at request.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-tglb3/igt at i915_selftest@perf at request.html > > * igt at kms_big_fb@linear-64bpp-rotate-0: > - shard-glk: [FAIL][25] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][26] > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-0.html > > * igt at kms_cursor_legacy@cursorb-vs-flipa-toggle: > - shard-glk: [DMESG-FAIL][27] ([i915#1925] / [i915#1926]) -> [PASS][28] > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk1/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-glk5/igt at kms_cursor_legacy@cursorb-vs-flipa-toggle.html > > * {igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2}: > - shard-glk: [FAIL][29] ([i915#1928]) -> [PASS][30] > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-glk2/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-glk8/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at bc-hdmi-a1-hdmi-a2.html > > * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: > - shard-skl: [FAIL][31] ([i915#79]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html > > * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: > - shard-apl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +8 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl7/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > > * {igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1}: > - shard-skl: [FAIL][35] ([i915#1928]) -> [PASS][36] > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html > > * igt at kms_frontbuffer_tracking@psr-suspend: > - shard-skl: [INCOMPLETE][37] ([i915#123] / [i915#69]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_frontbuffer_tracking@psr-suspend.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl8/igt at kms_frontbuffer_tracking@psr-suspend.html > > * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: [FAIL][39] ([fdo#108145] / [i915#265]) -> [PASS][40] +1 similar issue > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > > * igt at kms_psr@psr2_suspend: > - shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb3/igt at kms_psr@psr2_suspend.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb2/igt at kms_psr@psr2_suspend.html > > * igt at kms_vblank@pipe-a-ts-continuation-suspend: > - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > > * {igt at perf@polling-parameterized}: > - shard-iclb: [FAIL][45] ([i915#1542]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-iclb2/igt at perf@polling-parameterized.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-iclb6/igt at perf@polling-parameterized.html > > > #### Warnings #### > > * igt at kms_content_protection@atomic-dpms: > - shard-apl: [TIMEOUT][47] ([i915#1319] / [i915#1635]) -> [FAIL][48] ([fdo#110321] / [fdo#110336]) +1 similar issue > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@atomic-dpms.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl1/igt at kms_content_protection@atomic-dpms.html > > * igt at kms_content_protection@legacy: > - shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319] / [i915#1635]) > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl1/igt at kms_content_protection@legacy.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl1/igt at kms_content_protection@legacy.html > > * igt at kms_content_protection@lic: > - shard-apl: [TIMEOUT][51] ([i915#1319]) -> [TIMEOUT][52] ([i915#1319] / [i915#1635]) > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl8/igt at kms_content_protection@lic.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl4/igt at kms_content_protection@lic.html > > * igt at kms_fbcon_fbt@fbc: > - shard-apl: [FAIL][53] ([i915#1525] / [i915#95]) -> [FAIL][54] ([i915#1525]) > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8573/shard-apl7/igt at kms_fbcon_fbt@fbc.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/shard-apl8/igt at kms_fbcon_fbt@fbc.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 > [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189 > [i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925 > [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8573 -> Patchwork_17847 > > CI-20190529: 20190529 > CI_DRM_8573: 7dd051b025ee88fc5e358bc7d3438e1764f68257 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5690: bea881189520a9cccbb1c1cb454ac5b6fdaea40e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17847: 6c49c456cc63e42fd77667b19ef3e88780a047dc @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17847/index.html From ville.syrjala at linux.intel.com Thu Jun 4 21:03:19 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 5 Jun 2020 00:03:19 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> Message-ID: <20200604210319.GJ6112@intel.com> On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > ++++++++++++++++++++++++++------- > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 7223367171d1..44663e8ac9a1 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > intel_dp *intel_dp) > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > >base.base.crtc); > > > enum pipe pipe = crtc->pipe; > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > dp_tp_ctl_value; > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > + enum port port = intel_dig_port->base.port; > > > + i915_reg_t dp_tp_reg; > > > + > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > + dp_tp_reg = DP_TP_CTL(port); > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > + } > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > TRANS_DDI_FUNC_CTL(pip > > > e)); > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > - TGL_TRANS_DDI_PORT_MASK); > > > + trans_ddi_port_mask); > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > trans_ddi_func_ctl_value); > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > All this ad-hoc modeset code really should not exist. It's going to > > have different bugs than the norma modeset paths, so compliance > > testing > > this special code proves absolutely nothing about the normal modeset > > code. IMO someone needs to take up the task of rewrtiting all this to > > just perform normal modesets. > > Agree. I've just found that we get kernel NULL pointer dereference and > panic when we try to access to_intel_crtc(intel_dig_port- > >base.base.crtc). Yeah, that's a legacy pointer which should no longer be used at all with atomic drivers. I'm slowly trying to clear out all this legacy cruft. The next step I had hoped to take was https://patchwork.freedesktop.org/series/76993/ but then this compliacnce stuff landed and threw another wrench into the works. -- Ville Syrj?l? Intel From chris at chris-wilson.co.uk Thu Jun 4 21:14:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 4 Jun 2020 22:14:57 +0100 Subject: [Intel-gfx] [CI] drm/i915/gem: Async GPU relocations only Message-ID: <20200604211457.19696-1-chris@chris-wilson.co.uk> Reduce the 3 relocation paths down to the single path that accommodates all. The primary motivation for this is to guard the relocations with a natural fence (derived from the i915_request used to write the relocation from the GPU). The tradeoff in using async gpu relocations is that it increases latency over using direct CPU relocations, for the cases where the target is idle and accessible by the CPU. The benefit is greatly reduced lock contention and improved concurrency by pipelining. Note that forcing the async gpu relocations does reveal a few issues they have. Firstly, is that they are visible as writes to gem_busy, causing to mark some buffers are being to written to by the GPU even though userspace only reads. Secondly is that, in combination with the cmdparser, they can cause priority inversions. This should be the case where the work is being put into a common workqueue losing our priority information and so being executed in FIFO from the worker, denying us the opportunity to reorder the requests afterwards. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 295 ++---------------- .../i915/gem/selftests/i915_gem_execbuffer.c | 21 +- 2 files changed, 27 insertions(+), 289 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 340e7f108baf..cfe6d2cdbef1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -45,13 +45,6 @@ struct eb_vma_array { struct eb_vma vma[]; }; -enum { - FORCE_CPU_RELOC = 1, - FORCE_GTT_RELOC, - FORCE_GPU_RELOC, -#define DBG_FORCE_RELOC 0 /* choose one of the above! */ -}; - #define __EXEC_OBJECT_HAS_PIN BIT(31) #define __EXEC_OBJECT_HAS_FENCE BIT(30) #define __EXEC_OBJECT_NEEDS_MAP BIT(29) @@ -260,8 +253,6 @@ struct i915_execbuffer { */ struct reloc_cache { struct drm_mm_node node; /** temporary GTT binding */ - unsigned long vaddr; /** Current kmap address */ - unsigned long page; /** Currently mapped page index */ unsigned int gen; /** Cached value of INTEL_GEN */ bool use_64bit_reloc : 1; bool has_llc : 1; @@ -605,23 +596,6 @@ eb_add_vma(struct i915_execbuffer *eb, } } -static inline int use_cpu_reloc(const struct reloc_cache *cache, - const struct drm_i915_gem_object *obj) -{ - if (!i915_gem_object_has_struct_page(obj)) - return false; - - if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) - return true; - - if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) - return false; - - return (cache->has_llc || - obj->cache_dirty || - obj->cache_level != I915_CACHE_NONE); -} - static int eb_reserve_vma(const struct i915_execbuffer *eb, struct eb_vma *ev, u64 pin_flags) @@ -945,8 +919,6 @@ relocation_target(const struct drm_i915_gem_relocation_entry *reloc, static void reloc_cache_init(struct reloc_cache *cache, struct drm_i915_private *i915) { - cache->page = -1; - cache->vaddr = 0; /* Must be a variable in the struct to allow GCC to unroll. */ cache->gen = INTEL_GEN(i915); cache->has_llc = HAS_LLC(i915); @@ -1089,181 +1061,6 @@ static int reloc_gpu_flush(struct reloc_cache *cache) return err; } -static void reloc_cache_reset(struct reloc_cache *cache) -{ - void *vaddr; - - if (!cache->vaddr) - return; - - vaddr = unmask_page(cache->vaddr); - if (cache->vaddr & KMAP) { - if (cache->vaddr & CLFLUSH_AFTER) - mb(); - - kunmap_atomic(vaddr); - i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); - } else { - struct i915_ggtt *ggtt = cache_to_ggtt(cache); - - intel_gt_flush_ggtt_writes(ggtt->vm.gt); - io_mapping_unmap_atomic((void __iomem *)vaddr); - - if (drm_mm_node_allocated(&cache->node)) { - ggtt->vm.clear_range(&ggtt->vm, - cache->node.start, - cache->node.size); - mutex_lock(&ggtt->vm.mutex); - drm_mm_remove_node(&cache->node); - mutex_unlock(&ggtt->vm.mutex); - } else { - i915_vma_unpin((struct i915_vma *)cache->node.mm); - } - } - - cache->vaddr = 0; - cache->page = -1; -} - -static void *reloc_kmap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - void *vaddr; - - if (cache->vaddr) { - kunmap_atomic(unmask_page(cache->vaddr)); - } else { - unsigned int flushes; - int err; - - err = i915_gem_object_prepare_write(obj, &flushes); - if (err) - return ERR_PTR(err); - - BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); - BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); - - cache->vaddr = flushes | KMAP; - cache->node.mm = (void *)obj; - if (flushes) - mb(); - } - - vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); - cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; - cache->page = page; - - return vaddr; -} - -static void *reloc_iomap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - struct i915_ggtt *ggtt = cache_to_ggtt(cache); - unsigned long offset; - void *vaddr; - - if (cache->vaddr) { - intel_gt_flush_ggtt_writes(ggtt->vm.gt); - io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); - } else { - struct i915_vma *vma; - int err; - - if (i915_gem_object_is_tiled(obj)) - return ERR_PTR(-EINVAL); - - if (use_cpu_reloc(cache, obj)) - return NULL; - - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); - if (err) - return ERR_PTR(err); - - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, - PIN_MAPPABLE | - PIN_NONBLOCK /* NOWARN */ | - PIN_NOEVICT); - if (IS_ERR(vma)) { - memset(&cache->node, 0, sizeof(cache->node)); - mutex_lock(&ggtt->vm.mutex); - err = drm_mm_insert_node_in_range - (&ggtt->vm.mm, &cache->node, - PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, - 0, ggtt->mappable_end, - DRM_MM_INSERT_LOW); - mutex_unlock(&ggtt->vm.mutex); - if (err) /* no inactive aperture space, use cpu reloc */ - return NULL; - } else { - cache->node.start = vma->node.start; - cache->node.mm = (void *)vma; - } - } - - offset = cache->node.start; - if (drm_mm_node_allocated(&cache->node)) { - ggtt->vm.insert_page(&ggtt->vm, - i915_gem_object_get_dma_address(obj, page), - offset, I915_CACHE_NONE, 0); - } else { - offset += page << PAGE_SHIFT; - } - - vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, - offset); - cache->page = page; - cache->vaddr = (unsigned long)vaddr; - - return vaddr; -} - -static void *reloc_vaddr(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, - unsigned long page) -{ - void *vaddr; - - if (cache->page == page) { - vaddr = unmask_page(cache->vaddr); - } else { - vaddr = NULL; - if ((cache->vaddr & KMAP) == 0) - vaddr = reloc_iomap(obj, cache, page); - if (!vaddr) - vaddr = reloc_kmap(obj, cache, page); - } - - return vaddr; -} - -static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) -{ - if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { - if (flushes & CLFLUSH_BEFORE) { - clflushopt(addr); - mb(); - } - - *addr = value; - - /* - * Writes to the same cacheline are serialised by the CPU - * (including clflush). On the write path, we only require - * that it hits memory in an orderly fashion and place - * mb barriers at the start and end of the relocation phase - * to ensure ordering of clflush wrt to the system. - */ - if (flushes & CLFLUSH_AFTER) - clflushopt(addr); - } else - *addr = value; -} - static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) { struct drm_i915_gem_object *obj = vma->obj; @@ -1429,17 +1226,6 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, return cmd; } -static inline bool use_reloc_gpu(struct i915_vma *vma) -{ - if (DBG_FORCE_RELOC == FORCE_GPU_RELOC) - return true; - - if (DBG_FORCE_RELOC) - return false; - - return !dma_resv_test_signaled_rcu(vma->resv, true); -} - static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) { struct page *page; @@ -1454,10 +1240,10 @@ static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) return addr + offset_in_page(offset); } -static bool __reloc_entry_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - u64 offset, - u64 target_addr) +static int __reloc_entry_gpu(struct i915_execbuffer *eb, + struct i915_vma *vma, + u64 offset, + u64 target_addr) { const unsigned int gen = eb->reloc_cache.gen; unsigned int len; @@ -1473,7 +1259,7 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, batch = reloc_gpu(eb, vma, len); if (IS_ERR(batch)) - return false; + return PTR_ERR(batch); addr = gen8_canonical_addr(vma->node.start + offset); if (gen >= 8) { @@ -1522,55 +1308,21 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, *batch++ = target_addr; } - return true; -} - -static bool reloc_entry_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - u64 offset, - u64 target_addr) -{ - if (eb->reloc_cache.vaddr) - return false; - - if (!use_reloc_gpu(vma)) - return false; - - return __reloc_entry_gpu(eb, vma, offset, target_addr); + return 0; } static u64 -relocate_entry(struct i915_vma *vma, +relocate_entry(struct i915_execbuffer *eb, + struct i915_vma *vma, const struct drm_i915_gem_relocation_entry *reloc, - struct i915_execbuffer *eb, const struct i915_vma *target) { u64 target_addr = relocation_target(reloc, target); - u64 offset = reloc->offset; - - if (!reloc_entry_gpu(eb, vma, offset, target_addr)) { - bool wide = eb->reloc_cache.use_64bit_reloc; - void *vaddr; - -repeat: - vaddr = reloc_vaddr(vma->obj, - &eb->reloc_cache, - offset >> PAGE_SHIFT); - if (IS_ERR(vaddr)) - return PTR_ERR(vaddr); - - GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32))); - clflush_write32(vaddr + offset_in_page(offset), - lower_32_bits(target_addr), - eb->reloc_cache.vaddr); - - if (wide) { - offset += sizeof(u32); - target_addr >>= 32; - wide = false; - goto repeat; - } - } + int err; + + err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); + if (err) + return err; return target->node.start | UPDATE; } @@ -1635,8 +1387,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, * If the relocation already has the right value in it, no * more work needs to be done. */ - if (!DBG_FORCE_RELOC && - gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) return 0; /* Check that the relocation address is valid... */ @@ -1668,7 +1419,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, ev->flags &= ~EXEC_OBJECT_ASYNC; /* and update the user's relocation entry */ - return relocate_entry(ev->vma, reloc, eb, target->vma); + return relocate_entry(eb, ev->vma, reloc, target->vma); } static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) @@ -1706,10 +1457,8 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) * this is bad and so lockdep complains vehemently. */ copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); - if (unlikely(copied)) { - remain = -EFAULT; - goto out; - } + if (unlikely(copied)) + return -EFAULT; remain -= count; do { @@ -1717,8 +1466,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) if (likely(offset == 0)) { } else if ((s64)offset < 0) { - remain = (int)offset; - goto out; + return (int)offset; } else { /* * Note that reporting an error now @@ -1748,9 +1496,8 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); -out: - reloc_cache_reset(&eb->reloc_cache); - return remain; + + return 0; } static int eb_relocate(struct i915_execbuffer *eb) @@ -2658,7 +2405,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.i915 = i915; eb.file = file; eb.args = args; - if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) + if (!(args->flags & I915_EXEC_NO_RELOC)) args->flags |= __EXEC_HAS_RELOC; eb.exec = exec; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index a49016f8ee0d..57c14d3340cd 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -37,20 +37,14 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, return err; /* 8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[0] * sizeof(u32), - 0)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + if (err) goto unpin_vma; - } /* !8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[1] * sizeof(u32), - 1)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + if (err) goto unpin_vma; - } /* Skip to the end of the cmd page */ i = PAGE_SIZE / sizeof(u32) - RELOC_TAIL - 1; @@ -60,12 +54,9 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - if (!__reloc_entry_gpu(eb, vma, - offsets[2] * sizeof(u32), - 2)) { - err = -EIO; + err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + if (err) goto unpin_vma; - } GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); -- 2.20.1 From currojerez at riseup.net Thu Jun 4 21:34:57 2020 From: currojerez at riseup.net (Francisco Jerez) Date: Thu, 04 Jun 2020 14:34:57 -0700 Subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices In-Reply-To: <20200604182658.878417-1-ayaz.siddiqui@intel.com> References: <20200604182658.878417-1-ayaz.siddiqui@intel.com> Message-ID: <87eequpla6.fsf@riseup.net> Ayaz A Siddiqui <ayaz.siddiqui at intel.com> writes: > In order to avoid functional breakage of mis-programmed applications that > have grown to depend on unused MOCS entries, we are programming > those entries to be equal to fully cached ("L3 + LLC") entry as per the > recommendation from architecture team. > > These reserved and unspecified entries should not be used as they may be > changed to less performant variants with better coherency in the future > if more entries are needed. > This change seems highly questionable to me... If a future kernel release introduces a new MOCS entry with more strict coherency semantics, and an application starts relying on it, that application won't work when run on an older kernel version with this patch is applied. IOW setting uninitialized entries to the most strict caching setting available (UC) ensures forwards compatibility with future userspace, which seems like a more important design principle than giving full caching to broken userspace that accidentally makes use of an undefined MOCS entry not part of the kernel ABI. > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- > 1 file changed, 89 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > index 632e08a4592b..1089bd5fdba2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > L3_1_UC) > > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > - /* Base - Error (Reserved for Non-Use) */ > - MOCS_ENTRY(0, 0x0, 0x0), > - /* Base - Reserved */ > - MOCS_ENTRY(1, 0x0, 0x0), > > GEN11_MOCS_ENTRIES, > > @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > MOCS_ENTRY(61, > LE_1_UC | LE_TC_1_LLC, > L3_3_WB), > + > + /* NOTE: > + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). > + * These reserved entry should never be used, they may be chanaged > + * to low performant variants with better coherency in the future if > + * more entries are needed. > + */ > + > + /* Reserved index 0 and 1 */ > + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Reserved index 16 and 17 */ > + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Reserved index 24 and 25 */ > + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Unspecified indices 26 to 47 */ > + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + > + /* Unspecified indices 52 to 59 */ > + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB), > + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > + L3_3_WB) > }; > > static const struct drm_i915_mocs_entry icl_mocs_table[] = { > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 227 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200604/0e352603/attachment.sig> From matthew.d.roper at intel.com Thu Jun 4 22:12:40 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 4 Jun 2020 15:12:40 -0700 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 In-Reply-To: <20200604170157.GZ6112@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-3-matthew.d.roper@intel.com> <20200604170157.GZ6112@intel.com> Message-ID: <20200604221240.GC3023929@mdroper-desk1.amr.corp.intel.com> On Thu, Jun 04, 2020 at 08:01:57PM +0300, Ville Syrj?l? wrote: > On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote: > > RKL uses the same BW_BUDDY programming table as TGL, but programs the > > values into a single set BUDDY0 set of registers rather than the > > BUDDY1/BUDDY2 sets used by TGL. > > Maybe we just want some kind of HAS_ABOX() so we could use the same > thing here and in the ABOX_CTL programming? Although these are both related to how the display controller accesses memory, I don't think they're quite a 1:1 mapping. TGL has MBUX_ABOX_CTL{0,1,2} (and we're directed to program all three), but only has BW_BUDDY_CTL{1,2} and no 0 instance. For now I'll just add separate bw_buddy and abox masks to our platform device info structure. Matt > > > > > Bspec: 49218 > > Cc: Aditya Swarup <aditya.swarup at intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > --- > > .../drm/i915/display/intel_display_power.c | 44 +++++++++++-------- > > drivers/gpu/drm/i915/i915_reg.h | 14 ++++-- > > 2 files changed, 35 insertions(+), 23 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > > index 72312b67b57a..2c1ce50b572b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > enum intel_dram_type type = dev_priv->dram_info.type; > > u8 num_channels = dev_priv->dram_info.num_channels; > > const struct buddy_page_mask *table; > > - int i; > > + int config, min_buddy, max_buddy, i; > > > > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) > > /* Wa_1409767108: tgl */ > > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > else > > table = tgl_buddy_page_masks; > > > > - for (i = 0; table[i].page_mask != 0; i++) > > - if (table[i].num_channels == num_channels && > > - table[i].type == type) > > + if (IS_ROCKETLAKE(dev_priv)) { > > + min_buddy = max_buddy = 0; > > + } else { > > + min_buddy = 1; > > + max_buddy = 2; > > + } > > + > > + for (config = 0; table[config].page_mask != 0; config++) > > + if (table[config].num_channels == num_channels && > > + table[config].type == type) > > break; > > > > - if (table[i].page_mask == 0) { > > + if (table[config].page_mask == 0) { > > drm_dbg(&dev_priv->drm, > > "Unknown memory configuration; disabling address buddy logic.\n"); > > - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); > > - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); > > + for (i = min_buddy; i <= max_buddy; i++) > > + intel_de_write(dev_priv, BW_BUDDY_CTL(i), > > + BW_BUDDY_DISABLE); > > } else { > > - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, > > - table[i].page_mask); > > - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, > > - table[i].page_mask); > > - > > - /* Wa_22010178259:tgl */ > > - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > + for (i = min_buddy; i <= max_buddy; i++) { > > + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > > + table[config].page_mask); > > + > > + /* Wa_22010178259:tgl,rkl */ > > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > > + BW_BUDDY_TLB_REQ_TIMER_MASK, > > + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, > > + 0x8)); > > + } > > } > > } > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 578cfe11cbb9..3e79cefc510a 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -7837,13 +7837,19 @@ enum { > > #define WAIT_FOR_PCH_RESET_ACK (1 << 1) > > #define WAIT_FOR_PCH_FLR_ACK (1 << 0) > > > > -#define BW_BUDDY1_CTL _MMIO(0x45140) > > -#define BW_BUDDY2_CTL _MMIO(0x45150) > > +#define _BW_BUDDY0_CTL 0x45130 > > +#define _BW_BUDDY1_CTL 0x45140 > > +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ > > + _BW_BUDDY0_CTL, \ > > + _BW_BUDDY1_CTL)) > > #define BW_BUDDY_DISABLE REG_BIT(31) > > #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) > > > > -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) > > -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) > > +#define _BW_BUDDY0_PAGE_MASK 0x45134 > > +#define _BW_BUDDY1_PAGE_MASK 0x45144 > > +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ > > + _BW_BUDDY0_PAGE_MASK, \ > > + _BW_BUDDY1_PAGE_MASK)) > > > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > > #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > > -- > > 2.24.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From patchwork at emeril.freedesktop.org Thu Jun 4 22:35:15 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 22:35:15 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Async_GPU_relocations_only?= In-Reply-To: <20200604211457.19696-1-chris@chris-wilson.co.uk> References: <20200604211457.19696-1-chris@chris-wilson.co.uk> Message-ID: <159131011586.14553.12869786226495671555@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Async GPU relocations only URL : https://patchwork.freedesktop.org/series/78016/ State : success == Summary == CI Bug Log - changes from CI_DRM_8588 -> Patchwork_17878 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/index.html Known issues ------------ Here are the changes found in Patchwork_17878 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html - fi-glk-dsi: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-tgl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8588 -> Patchwork_17878 CI-20190529: 20190529 CI_DRM_8588: 294330ea49d6c0763514747ebc994f0b29a5afbe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17878: 7b08ef0f711fac0ebdbfe22db9a445f3c3361e27 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7b08ef0f711f drm/i915/gem: Async GPU relocations only == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/index.html From matthew.d.roper at intel.com Thu Jun 4 22:55:58 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 4 Jun 2020 15:55:58 -0700 Subject: [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI In-Reply-To: <20200604165955.GY6112@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-14-matthew.d.roper@intel.com> <20200604165955.GY6112@intel.com> Message-ID: <20200604225558.GD3023929@mdroper-desk1.amr.corp.intel.com> On Thu, Jun 04, 2020 at 07:59:55PM +0300, Ville Syrj?l? wrote: > On Wed, Jun 03, 2020 at 02:15:27PM -0700, Matt Roper wrote: > > If HTI (also sometimes called HDPORT) is enabled at startup, it may be > > whatis HTI? That's not really clear in the bspec or any other documents I've seen. It sounds like its something setup by the boot firmware that can potentially steal PLL and PHYs away. Driver-wise there doesn't seem to be much we need to do other than avoid using the reserved resources, sort of like how we avoid using fused off units. Matt > > > using some of the PHYs and DPLLs making them unavailable for general > > usage. Let's read out the HDPORT_STATE register and avoid making use of > > resources that HTI is already using. > > > > v2: > > - Fix minor checkpatch warnings > > > > Bspec: 49189 > > Bspec: 53707 > > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + > > drivers/gpu/drm/i915/i915_drv.h | 3 ++ > > drivers/gpu/drm/i915/i915_reg.h | 6 ++++ > > 5 files changed, 57 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index bcc6dc4e321b..cdd84a419cf7 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -46,6 +46,7 @@ > > #include "display/intel_ddi.h" > > #include "display/intel_dp.h" > > #include "display/intel_dp_mst.h" > > +#include "display/intel_dpll_mgr.h" > > #include "display/intel_dsi.h" > > #include "display/intel_dvo.h" > > #include "display/intel_gmbus.h" > > @@ -16817,6 +16818,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) > > intel_pps_unlock_regs_wa(dev_priv); > > } > > > > +static bool hti_uses_phy(u32 hdport_state, enum phy phy) > > +{ > > + return hdport_state & HDPORT_ENABLED && > > + (hdport_state & HDPORT_PHY_USED_DP(phy) || > > + hdport_state & HDPORT_PHY_USED_HDMI(phy)); > > +} > > + > > static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > { > > struct intel_encoder *encoder; > > @@ -16828,10 +16836,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > return; > > > > if (IS_ROCKETLAKE(dev_priv)) { > > - intel_ddi_init(dev_priv, PORT_A); > > - intel_ddi_init(dev_priv, PORT_B); > > - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > > - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > > + /* > > + * If HTI (aka HDPORT) is enabled at boot, it may have taken > > + * over some of the PHYs and made them unavailable to the > > + * driver. In that case we should skip initializing the > > + * corresponding outputs. > > + */ > > + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); > > + > > + if (!hti_uses_phy(hdport_state, PHY_A)) > > + intel_ddi_init(dev_priv, PORT_A); > > + if (!hti_uses_phy(hdport_state, PHY_B)) > > + intel_ddi_init(dev_priv, PORT_B); > > + if (!hti_uses_phy(hdport_state, PHY_C)) > > + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > > + if (!hti_uses_phy(hdport_state, PHY_D)) > > + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > > } else if (INTEL_GEN(dev_priv) >= 12) { > > intel_ddi_init(dev_priv, PORT_A); > > intel_ddi_init(dev_priv, PORT_B); > > @@ -18379,6 +18399,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) > > > > intel_dpll_readout_hw_state(dev_priv); > > > > + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); > > + > > for_each_intel_encoder(dev, encoder) { > > pipe = 0; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > index b5f4d4cef682..6f59f9ec453b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) > > mutex_unlock(&dev_priv->dpll.lock); > > } > > > > +/* > > + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them > > + * unavailable for use. > > + */ > > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) > > +{ > > + u32 hdport_state; > > + > > + if (!IS_ROCKETLAKE(dev_priv)) > > + return 0; > > + > > + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); > > + if (!(hdport_state & HDPORT_ENABLED)) > > + return 0; > > + > > + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); > > +} > > + > > static struct intel_shared_dpll * > > intel_find_shared_dpll(struct intel_atomic_state *state, > > const struct intel_crtc *crtc, > > @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, > > > > drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); > > > > + /* Eliminate DPLLs from consideration if reserved by HTI */ > > + dpll_mask &= ~dev_priv->hti_pll_mask; > > + > > for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { > > pll = &dev_priv->dpll.shared_dplls[i]; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > index 5d9a2bc371e7..ac2238646fe7 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); > > void intel_shared_dpll_init(struct drm_device *dev); > > void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); > > void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); > > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); > > > > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, > > const struct intel_dpll_hw_state *hw_state); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index e99255e17eb7..668b3c9cf3ae 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1037,6 +1037,9 @@ struct drm_i915_private { > > > > struct intel_l3_parity l3_parity; > > > > + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ > > + u32 hti_pll_mask; > > + > > /* > > * edram size in MB. > > * Cannot be determined by PCIID. You must always read a register. > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 85137d268c4a..b9faf0f978cf 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -2906,6 +2906,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) > > #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) > > > > +#define HDPORT_STATE _MMIO(0x45050) > > +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) > > +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2*(phy) + 2) > > +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2*(phy) + 1) > > +#define HDPORT_ENABLED REG_BIT(0) > > + > > /* Make render/texture TLB fetches lower priorty than associated data > > * fetches. This is not turned on by default > > */ > > -- > > 2.24.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From patchwork at emeril.freedesktop.org Thu Jun 4 23:10:54 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 23:10:54 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Initialize_reserved_and_unspecified_MOCS_indices?= In-Reply-To: <20200604182658.878417-1-ayaz.siddiqui@intel.com> References: <20200604182658.878417-1-ayaz.siddiqui@intel.com> Message-ID: <159131225431.14555.4932495597094434710@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Initialize reserved and unspecified MOCS indices URL : https://patchwork.freedesktop.org/series/78012/ State : success == Summary == CI Bug Log - changes from CI_DRM_8585_full -> Patchwork_17875_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17875_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_reloc@basic-concurrent16}: - shard-kbl: [TIMEOUT][1] ([i915#1930]) -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt at gem_exec_reloc@basic-concurrent16.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl2/igt at gem_exec_reloc@basic-concurrent16.html Known issues ------------ Here are the changes found in Patchwork_17875_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk9/igt at gem_exec_whisper@basic-contexts-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk8/igt at gem_exec_whisper@basic-contexts-forked.html * igt at i915_suspend@debugfs-reader: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl7/igt at i915_suspend@debugfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl10/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk4/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-32bpp-rotate-270: - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#1172] / [i915#1897]) +10 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb1/igt at kms_big_fb@y-tiled-32bpp-rotate-270.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb1/igt at kms_big_fb@y-tiled-32bpp-rotate-270.html * igt at kms_cursor_crc@pipe-b-cursor-256x85-offscreen: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl6/igt at kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl4/igt at kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +15 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl8/igt at kms_flip_tiling@flip-x-tiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl4/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb5/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-tglb: [PASS][21] -> [FAIL][22] ([i915#1897]) +139 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl9/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt at kms_plane_scaling@pipe-c-plane-scaling: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +7 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl8/igt at kms_plane_scaling@pipe-c-plane-scaling.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl4/igt at kms_plane_scaling@pipe-c-plane-scaling.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-iclb7/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl8/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * {igt at gem_exec_schedule@implicit-boths at bcs0}: - shard-snb: [INCOMPLETE][33] ([i915#82]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-snb4/igt at gem_exec_schedule@implicit-boths at bcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-snb4/igt at gem_exec_schedule@implicit-boths at bcs0.html * {igt at gem_exec_schedule@preempt at bcs0}: - shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb8/igt at gem_exec_schedule@preempt at bcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb1/igt at gem_exec_schedule@preempt at bcs0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk4/igt at gem_exec_whisper@basic-queues-forked-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk1/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][39] ([i915#1436] / [i915#716]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl3/igt at gen9_exec_parse@allowed-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl2/igt at gen9_exec_parse@allowed-all.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl1/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl2/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl1/igt at kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl1/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl5/igt at kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl9/igt at kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [DMESG-FAIL][49] ([i915#54] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl6/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk5/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk7/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][55] ([i915#128]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-hsw7/igt at kms_cursor_legacy@pipe-c-torture-move.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-hsw7/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb7/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-tglb2/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl3/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl1/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1}: - shard-skl: [FAIL][61] ([i915#1928]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl9/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * {igt at kms_getfb@getfb2-handle-protection}: - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [PASS][64] +15 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl7/igt at kms_getfb@getfb2-handle-protection.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl4/igt at kms_getfb@getfb2-handle-protection.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][65] ([i915#1188]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb5/igt at kms_psr@psr2_primary_page_flip.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html #### Warnings #### * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt at kms_content_protection@atomic-dpms.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl2/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][71] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][72] ([fdo#110321] / [i915#95]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt at kms_content_protection@lic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-apl8/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl2/igt at kms_content_protection@srm.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-kbl1/igt at kms_content_protection@srm.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-glk: [INCOMPLETE][75] ([i915#58] / [k.org#198133]) -> [TIMEOUT][76] ([i915#1958]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/shard-glk9/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1172]: https://gitlab.freedesktop.org/drm/intel/issues/1172 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8585 -> Patchwork_17875 CI-20190529: 20190529 CI_DRM_8585: 3aef9a510cfe66ba71ed397e91c517402f7c26ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17875: 74e4956ad45f89c7f37ff7f79108099c834ff6d8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17875/index.html From matthew.d.roper at intel.com Thu Jun 4 23:18:49 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 4 Jun 2020 16:18:49 -0700 Subject: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL In-Reply-To: <20200604182919.GB6112@intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-8-matthew.d.roper@intel.com> <20200604182919.GB6112@intel.com> Message-ID: <20200604231849.GE3023929@mdroper-desk1.amr.corp.intel.com> On Thu, Jun 04, 2020 at 09:29:19PM +0300, Ville Syrj?l? wrote: > On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote: > > When TGP is paired with RKL it uses a different HPD pin mapping than > > when paired with TGL. > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > --- > > drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++- > > 1 file changed, 14 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 490574669eaa..f3ea81a17352 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { > > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), > > }; > > > > +/* > > + * TGP when paired with RKL has different pin mappings than when paired > > + * with TGL. > > + */ > > +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = { > > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), > > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), > > + [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1), > > + [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2), > > +}; > > Hmm. So basically it looks like we'd want to pick the hpd_pin > based on the DDI rather than the PHY on this platform? I may be misinterpreting the table on bspec 49181, but I *think* it looks like we use the DDI when paired with a TGP PCH and the PHY when paired with CMP PCH. So if I just set the hpd_pin based on the DDI, then I think that will break the CMP-based systems (although I haven't tested on one of those, so I'm not 100% sure). Matt > > OK, I guess we need to remap somehow. The question is > whether we want to do it before or after selecting hpd_pin... > I think we would want to do it before, as otherwise the > long_detect() stuff won't work right AFAICS. Or am I > missing something? > > Side note: we should probably convert the long_detect() > switches to arrays just like we have for the isr bits here. > Would potentially avoid having to touch that code every time > they tweak these thinhs in hw. > > And in fact it looks like icp already has all the same hpd > pins as tgp, so I'm thinking we should just s/hpd_tgp/hpd_icp/ > and for icl/jsl we should remap hpd_pin as well. Oh and the > mcc case would just need a slightly different mapping of > port C -> HPD_PORT_D (aka. tc1). > > This way all the hpd[] arrays and whatnot would just be based > on the actual pch type and not based on what it happens to be > paired with. > > Anwyays, most of that is out of scope for this rkl stuff, so > I guess for now just add a bit of logic to remap hpd_pin for rkl? > > > + > > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > > { > > struct i915_hotplug *hpd = &dev_priv->hotplug; > > @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > > if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) > > return; > > > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > > + if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv)) > > + hpd->pch_hpd = hpd_rkl_tgp; > > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > > hpd->pch_hpd = hpd_tgp; > > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) > > hpd->pch_hpd = hpd_icp; > > -- > > 2.24.1 > > -- > Ville Syrj?l? > Intel -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From gwan-gyeong.mun at intel.com Thu Jun 4 23:38:47 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Thu, 4 Jun 2020 23:38:47 +0000 Subject: [Intel-gfx] [PATCH] drm/i915: Add psr_safest_params In-Reply-To: <20200520212756.354623-1-jose.souza@intel.com> References: <20200520212756.354623-1-jose.souza@intel.com> Message-ID: <ab3384950d24cfc0584c82540092879ec4476ec7.camel@intel.com> Looks good to me. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> On Wed, 2020-05-20 at 14:27 -0700, Jos? Roberto de Souza wrote: > This parameter is meant to be used when PSR issues are found as some > issues in the past was due wrong values set in VBT so this would be > a quick and easy way to ask users or for us to check if the issue is > due VBT values. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 37 ++++++++++++++++++-- > ---- > drivers/gpu/drm/i915/i915_params.c | 5 ++++ > drivers/gpu/drm/i915/i915_params.h | 1 + > 3 files changed, 34 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index b7a2c102648a..859780853f42 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -426,6 +426,12 @@ static u32 intel_psr1_get_tp_time(struct > intel_dp *intel_dp) > if (INTEL_GEN(dev_priv) >= 11) > val |= EDP_PSR_TP4_TIME_0US; > > + if (i915_modparams.psr_safest_params) { > + val |= EDP_PSR_TP1_TIME_2500us; > + val |= EDP_PSR_TP2_TP3_TIME_2500us; > + goto check_tp3_sel; > + } > + > if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) > val |= EDP_PSR_TP1_TIME_0us; > else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) > @@ -444,6 +450,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp > *intel_dp) > else > val |= EDP_PSR_TP2_TP3_TIME_2500us; > > +check_tp3_sel: > if (intel_dp_source_supports_hbr2(intel_dp) && > drm_dp_tps3_supported(intel_dp->dpcd)) > val |= EDP_PSR_TP1_TP3_SEL; > @@ -495,18 +502,13 @@ static void hsw_activate_psr1(struct intel_dp > *intel_dp) > intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), > val); > } > > -static void hsw_activate_psr2(struct intel_dp *intel_dp) > +static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - u32 val; > - > - val = psr_compute_idle_frames(intel_dp) << > EDP_PSR2_IDLE_FRAME_SHIFT; > - > - val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > - val |= EDP_Y_COORDINATE_ENABLE; > + u32 val = 0; > > - val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency > + 1); > + if (i915_modparams.psr_safest_params) > + return EDP_PSR2_TP2_TIME_2500us; > > if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && > dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) > @@ -518,6 +520,23 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > else > val |= EDP_PSR2_TP2_TIME_2500us; > > + return val; > +} > + > +static void hsw_activate_psr2(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + u32 val; > + > + val = psr_compute_idle_frames(intel_dp) << > EDP_PSR2_IDLE_FRAME_SHIFT; > + > + val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > + val |= EDP_Y_COORDINATE_ENABLE; > + > + val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency > + 1); > + val |= intel_psr2_get_tp_time(intel_dp); > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec > is > * recommending keep this bit unset while PSR2 is enabled. > diff --git a/drivers/gpu/drm/i915/i915_params.c > b/drivers/gpu/drm/i915/i915_params.c > index add00ec1f787..307e4667fc62 100644 > --- a/drivers/gpu/drm/i915/i915_params.c > +++ b/drivers/gpu/drm/i915/i915_params.c > @@ -88,6 +88,11 @@ i915_param_named_unsafe(enable_psr, int, 0600, > "(0=disabled, 1=enabled) " > "Default: -1 (use per-chip default)"); > > +i915_param_named(psr_safest_params, bool, 0400, > + "Replace PSR VBT parameters by the safest and not optimal ones. > This " > + "is helpfull to detect if PSR issues are related to bad values > set in " > + " VBT. (0=use VBT paramters, 1=use safest parameters)"); > + > i915_param_named_unsafe(force_probe, charp, 0400, > "Force probe the driver for specified devices. " > "See CONFIG_DRM_I915_FORCE_PROBE for details."); > diff --git a/drivers/gpu/drm/i915/i915_params.h > b/drivers/gpu/drm/i915/i915_params.h > index 45323732f099..2a99c908c7c8 100644 > --- a/drivers/gpu/drm/i915/i915_params.h > +++ b/drivers/gpu/drm/i915/i915_params.h > @@ -53,6 +53,7 @@ struct drm_printer; > param(int, enable_dc, -1, 0400) \ > param(int, enable_fbc, -1, 0600) \ > param(int, enable_psr, -1, 0600) \ > + param(bool, psr_safest_params, false, 0600) \ > param(int, disable_power_well, -1, 0400) \ > param(int, enable_ips, 1, 0600) \ > param(int, invert_brightness, 0, 0600) \ From matthew.d.roper at intel.com Thu Jun 4 23:53:20 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 4 Jun 2020 16:53:20 -0700 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Message-ID: <20200604235321.3190817-1-matthew.d.roper@intel.com> RKL uses the same BW_BUDDY programming table as TGL, but programs the values into a single set BUDDY0 set of registers rather than the BUDDY1/BUDDY2 sets used by TGL and DG1. v2: - Store the mask of platform-specific buddy registers in the device info structure. - Add a TLB_REQ_TIMER() helper macro. (Aditya) Bspec: 49218 Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- .../drm/i915/display/intel_display_power.c | 43 ++++++++++--------- drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_reg.h | 15 +++++-- drivers/gpu/drm/i915/intel_device_info.h | 2 + 4 files changed, 37 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 72312b67b57a..5a324d5c9fe4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5254,7 +5254,11 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) enum intel_dram_type type = dev_priv->dram_info.type; u8 num_channels = dev_priv->dram_info.num_channels; const struct buddy_page_mask *table; - int i; + unsigned long buddy_regs = INTEL_INFO(dev_priv)->bw_buddy_mask; + int config, i; + + if (!buddy_regs) + return; if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) /* Wa_1409767108: tgl */ @@ -5262,29 +5266,27 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) else table = tgl_buddy_page_masks; - for (i = 0; table[i].page_mask != 0; i++) - if (table[i].num_channels == num_channels && - table[i].type == type) + for (config = 0; table[config].page_mask != 0; config++) + if (table[config].num_channels == num_channels && + table[config].type == type) break; - if (table[i].page_mask == 0) { + if (table[config].page_mask == 0) { drm_dbg(&dev_priv->drm, "Unknown memory configuration; disabling address buddy logic.\n"); - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); + for_each_set_bit(i, &buddy_regs, sizeof(buddy_regs)) + intel_de_write(dev_priv, BW_BUDDY_CTL(i), + BW_BUDDY_DISABLE); } else { - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, - table[i].page_mask); - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, - table[i].page_mask); - - /* Wa_22010178259:tgl */ - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, - BW_BUDDY_TLB_REQ_TIMER_MASK, - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, - BW_BUDDY_TLB_REQ_TIMER_MASK, - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); + for_each_set_bit(i, &buddy_regs, sizeof(buddy_regs)) { + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), + table[config].page_mask); + + /* Wa_22010178259:tgl,rkl */ + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), + BW_BUDDY_TLB_REQ_TIMER_MASK, + BW_BUDDY_TLB_REQ_TIMER(0x8)); + } } } @@ -5321,8 +5323,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, icl_mbus_init(dev_priv); /* 7. Program arbiter BW_BUDDY registers */ - if (INTEL_GEN(dev_priv) >= 12) - tgl_bw_buddy_init(dev_priv); + tgl_bw_buddy_init(dev_priv); if (resume && dev_priv->csr.dmc_payload) intel_csr_load_program(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 192f1cd172b8..3f1ccd899f4b 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -847,6 +847,7 @@ static const struct intel_device_info ehl_info = { #define GEN12_FEATURES \ GEN11_FEATURES, \ GEN(12), \ + .bw_buddy_mask = GENMASK(2, 1), \ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ @@ -882,6 +883,7 @@ static const struct intel_device_info tgl_info = { static const struct intel_device_info rkl_info = { GEN12_FEATURES, PLATFORM(INTEL_ROCKETLAKE), + .bw_buddy_mask = BIT(0), .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 814a70945468..fe2aefc12141 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7839,13 +7839,20 @@ enum { #define WAIT_FOR_PCH_RESET_ACK (1 << 1) #define WAIT_FOR_PCH_FLR_ACK (1 << 0) -#define BW_BUDDY1_CTL _MMIO(0x45140) -#define BW_BUDDY2_CTL _MMIO(0x45150) +#define _BW_BUDDY0_CTL 0x45130 +#define _BW_BUDDY1_CTL 0x45140 +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_CTL, \ + _BW_BUDDY1_CTL)) #define BW_BUDDY_DISABLE REG_BIT(31) #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) +#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) +#define _BW_BUDDY0_PAGE_MASK 0x45134 +#define _BW_BUDDY1_PAGE_MASK 0x45144 +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_PAGE_MASK, \ + _BW_BUDDY1_PAGE_MASK)) #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 34dbffd65bad..73da4f1b8e2e 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -175,6 +175,8 @@ struct intel_device_info { u8 pipe_mask; u8 cpu_transcoder_mask; + u8 bw_buddy_mask; + #define DEFINE_FLAG(name) u8 name:1 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); #undef DEFINE_FLAG -- 2.24.1 From matthew.d.roper at intel.com Thu Jun 4 23:53:21 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 4 Jun 2020 16:53:21 -0700 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} In-Reply-To: <20200604235321.3190817-1-matthew.d.roper@intel.com> References: <20200604235321.3190817-1-matthew.d.roper@intel.com> Message-ID: <20200604235321.3190817-2-matthew.d.roper@intel.com> Although RKL is a gen12 platform, it doesn't have the two extra instances of the ABOX control register; we should only program the single MBUS_ABOX_CTL on this platform. Note that the bspec tagging for this is a bit misleading/inconsistent; the details that ABOX1/2 don't exist exists in the bspec, but is tagged in a strange limbo state such that it doesn't take effect when a RKL filter view is applied; we've confirmed experimentally that these two extra register instances don't exist on the platform (and trigger unclaimed register errors when accessed). v2: - Store the mask of platform-specific abox registers in the device info structure. Bspec: 50096 Bspec: 49218 Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 10 ++++------ drivers/gpu/drm/i915/i915_pci.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 9 ++++++--- drivers/gpu/drm/i915/intel_device_info.h | 1 + 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 5a324d5c9fe4..a2b9f1fe3bc7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4760,7 +4760,8 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) static void icl_mbus_init(struct drm_i915_private *dev_priv) { - u32 mask, val; + unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; + u32 mask, val, i; mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | MBUS_ABOX_BT_CREDIT_POOL2_MASK | @@ -4771,11 +4772,8 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) MBUS_ABOX_B_CREDIT(1) | MBUS_ABOX_BW_CREDIT(1); - intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val); - if (INTEL_GEN(dev_priv) >= 12) { - intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val); - intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val); - } + for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) + intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); } static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 3f1ccd899f4b..49651f60113b 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -804,6 +804,7 @@ static const struct intel_device_info cnl_info = { #define GEN11_FEATURES \ GEN10_FEATURES, \ GEN11_DEFAULT_PAGE_SIZES, \ + .abox_mask = BIT(0), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ @@ -848,6 +849,7 @@ static const struct intel_device_info ehl_info = { GEN11_FEATURES, \ GEN(12), \ .bw_buddy_mask = GENMASK(2, 1), \ + .abox_mask = GENMASK(2, 0), \ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ @@ -884,6 +886,7 @@ static const struct intel_device_info rkl_info = { GEN12_FEATURES, PLATFORM(INTEL_ROCKETLAKE), .bw_buddy_mask = BIT(0), + .abox_mask = BIT(0), .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fe2aefc12141..4c3e822e1024 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2879,9 +2879,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ -#define MBUS_ABOX_CTL _MMIO(0x45038) -#define MBUS_ABOX1_CTL _MMIO(0x45048) -#define MBUS_ABOX2_CTL _MMIO(0x4504C) +#define _MBUS_ABOX0_CTL 0x45038 +#define _MBUS_ABOX1_CTL 0x45048 +#define _MBUS_ABOX2_CTL 0x4504C +#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ + _MBUS_ABOX1_CTL, \ + _MBUS_ABOX2_CTL)) #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 73da4f1b8e2e..363f62e2d361 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -176,6 +176,7 @@ struct intel_device_info { u8 cpu_transcoder_mask; u8 bw_buddy_mask; + u8 abox_mask; #define DEFINE_FLAG(name) u8 name:1 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); -- 2.24.1 From patchwork at emeril.freedesktop.org Thu Jun 4 23:55:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 04 Jun 2020 23:55:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/3=5D_drm/i915/dp=5Fmst=3A_Fix_disab?= =?utf-8?q?ling_MST_on_a_port_=28rev4=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159131491383.14554.14078846176039129280@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev4) URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8585_full -> Patchwork_17876_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17876_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_param@basic: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +13 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl2/igt at gem_ctx_param@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl1/igt at gem_ctx_param@basic.html * igt at gem_exec_nop@basic-series: - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([i915#61]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-hsw8/igt at gem_exec_nop@basic-series.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-hsw6/igt at gem_exec_nop@basic-series.html * igt at gem_exec_whisper@basic-queues-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk8/igt at gem_exec_whisper@basic-queues-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-glk8/igt at gem_exec_whisper@basic-queues-all.html * igt at i915_selftest@mock at requests: - shard-glk: [PASS][7] -> [INCOMPLETE][8] ([i915#58] / [k.org#198133]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk1/igt at i915_selftest@mock at requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-glk8/igt at i915_selftest@mock at requests.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@all-pipes-torture-bo: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([i915#128]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-hsw4/igt at kms_cursor_legacy@all-pipes-torture-bo.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-hsw5/igt at kms_cursor_legacy@all-pipes-torture-bo.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-c-plane-scaling: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl8/igt at kms_plane_scaling@pipe-c-plane-scaling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl1/igt at kms_plane_scaling@pipe-c-plane-scaling.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-iclb3/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb6/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-tglb7/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html * igt at perf@blocking: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1542]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl6/igt at perf@blocking.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl9/igt at perf@blocking.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * {igt at gem_exec_schedule@implicit-boths at bcs0}: - shard-snb: [INCOMPLETE][29] ([i915#82]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-snb4/igt at gem_exec_schedule@implicit-boths at bcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-snb1/igt at gem_exec_schedule@implicit-boths at bcs0.html * {igt at gem_exec_schedule@preempt at bcs0}: - shard-tglb: [DMESG-WARN][31] ([i915#402]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb8/igt at gem_exec_schedule@preempt at bcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-tglb2/igt at gem_exec_schedule@preempt at bcs0.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][33] ([i915#118] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-glk9/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +4 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl1/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl7/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][37] ([i915#93] / [i915#95]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl1/igt at kms_color@pipe-c-ctm-red-to-blue.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl3/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-128x42-offscreen: - shard-skl: [FAIL][39] ([i915#54]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl5/igt at kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl2/igt at kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [DMESG-FAIL][41] ([i915#54] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl6/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl7/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-glk: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk5/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-glk9/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][47] ([i915#128]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-hsw7/igt at kms_cursor_legacy@pipe-c-torture-move.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb7/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-tglb3/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html - shard-apl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl3/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl8/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-kbl: [TIMEOUT][53] -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1}: - shard-skl: [FAIL][55] ([i915#1928]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl9/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl6/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * {igt at kms_getfb@getfb2-handle-protection}: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +20 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl7/igt at kms_getfb@getfb2-handle-protection.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl2/igt at kms_getfb@getfb2-handle-protection.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl7/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-iclb8/igt at kms_psr@psr2_cursor_render.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * {igt at perf_pmu@enable-race at vecs0}: - shard-glk: [DMESG-WARN][65] ([i915#118] / [i915#95]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk7/igt at perf_pmu@enable-race at vecs0.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-glk7/igt at perf_pmu@enable-race at vecs0.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][67] ([i915#454]) -> [SKIP][68] ([i915#468]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-tglb8/igt at i915_pm_dc@dc6-psr.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_ccs@pipe-c-crc-primary-basic: - shard-kbl: [TIMEOUT][69] -> [SKIP][70] ([fdo#109271]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt at kms_ccs@pipe-c-crc-primary-basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl1/igt at kms_ccs@pipe-c-crc-primary-basic.html * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-kbl: [INCOMPLETE][71] -> [SKIP][72] ([fdo#109271] / [fdo#111827]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl4/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl1/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][73] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][74] ([i915#1319] / [i915#1635]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][75] ([i915#1319] / [i915#1635]) -> [FAIL][76] ([fdo#110321] / [fdo#110336]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl1/igt at kms_content_protection@legacy.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-apl4/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-apl3/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][79] ([fdo#110321] / [i915#95]) -> [TIMEOUT][80] ([i915#1319]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-kbl2/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-kbl7/igt at kms_content_protection@srm.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-glk: [INCOMPLETE][81] ([i915#58] / [k.org#198133]) -> [TIMEOUT][82] ([i915#1958]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-glk6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-WARN][83] ([i915#1982]) -> [DMESG-FAIL][84] ([fdo#108145] / [i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8585/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8585 -> Patchwork_17876 CI-20190529: 20190529 CI_DRM_8585: 3aef9a510cfe66ba71ed397e91c517402f7c26ac @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17876: 510b25246e2201dfbad5a4a34e0cec24f91db43e @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17876/index.html From gwan-gyeong.mun at intel.com Fri Jun 5 00:23:50 2020 From: gwan-gyeong.mun at intel.com (Gwan-gyeong Mun) Date: Fri, 5 Jun 2020 03:23:50 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/psr: Program default IO buffer Wake and Fast Wake Message-ID: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> The IO buffer Wake and Fast Wake bit size and value have been changed from Gen12+. It programs default value of IO buffer Wake and Fast Wake on Gen12+. - Pre Gen12 Bit location: IO buffer Wake: Register_PSR2_CTL[14:13] Fast Wake: Register_PSR2_CTL[12:11] Value: 0x0: 8 lines 0x1: 7 lines 0x2: 6 lines 0x3: 5 lines - Gen12+ Bit location: IO buffer Wake: Register_PSR2_CTL[15:13] Fast Wake: Register_PSR2_CTL[12:10] Value: 0x0: 5 lines 0x1: 6 lines 0x2: 7 lines 0x3: 8 lines 0x4: 9 lines 0x5: 10 lines 0x6: 11 lines 0x7: 12 lines Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b7a2c102648a..de2a17fe8860 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -518,6 +518,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) else val |= EDP_PSR2_TP2_TIME_2500us; + if (INTEL_GEN(dev_priv) >= 12) { + /* + * TODO: In order to setting an optimal power consumption, + * lower than 4k resoluition mode needs to decrese IO_BUFFER_WAKE + * and FAST_WAKE. And higher than 4K resolution mode needs + * to increase IO_BUFFER_WAKE and FAST_WAKE. + */ + u32 io_buffer_wake = 0x2; /* default BSpec value, 7 lines */ + u32 fast_wake = 0x2; /* default BSpec value, 7 lines */ + + /* + * To program line 9 to 12 on IO_BUFFER_WAKE and FAST_WAKE, + * EDP_PSR2_CTL should be set EDP_PSR2_BLOCK_COUNT_NUM_3. + */ + val |= EDP_PSR2_BLOCK_COUNT_NUM_2; + val |= EDP_PSR2_IO_BUFFER_WAKE(io_buffer_wake); + val |= EDP_PSR2_FAST_WAKE(fast_wake); + } + /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 96d351fbeebb..d055b7d93a5d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4514,10 +4514,16 @@ enum { #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) #define EDP_PSR2_ENABLE (1 << 31) #define EDP_SU_TRACK_ENABLE (1 << 30) +#define EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) /* TGL+ */ +#define EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) /* TGL+ */ #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) +#define EDP_PSR2_IO_BUFFER_WAKE(a) ((a) << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (0x7 << 13) /* TGL+ */ +#define EDP_PSR2_FAST_WAKE(a) ((a) << 10) /* TGL+ */ +#define EDP_PSR2_FAST_WAKE_MASK (0x7 << 10) /* TGL+ */ #define EDP_PSR2_TP2_TIME_500us (0 << 8) #define EDP_PSR2_TP2_TIME_100us (1 << 8) #define EDP_PSR2_TP2_TIME_2500us (2 << 8) -- 2.25.0 From patchwork at emeril.freedesktop.org Fri Jun 5 00:29:09 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 00:29:09 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/rkl=3A_Program_BW=5FBUDDY0?= =?utf-8?q?_registers_instead_of_BW=5FBUDDY1/2?= In-Reply-To: <20200604235321.3190817-1-matthew.d.roper@intel.com> References: <20200604235321.3190817-1-matthew.d.roper@intel.com> Message-ID: <159131694935.18509.4997565491589163387@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 URL : https://patchwork.freedesktop.org/series/78018/ State : success == Summary == CI Bug Log - changes from CI_DRM_8588 -> Patchwork_17879 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/index.html Known issues ------------ Here are the changes found in Patchwork_17879 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][5] ([i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html - fi-glk-dsi: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-tgl-y: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][17] ([fdo#109271]) -> [DMESG-FAIL][18] ([i915#62] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 44) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8588 -> Patchwork_17879 CI-20190529: 20190529 CI_DRM_8588: 294330ea49d6c0763514747ebc994f0b29a5afbe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17879: 2b4ef2a8b8d4062203cb55a06187f02ff458b6f9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2b4ef2a8b8d4 drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2} d968bd205dad drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 00:57:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 00:57:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake?= In-Reply-To: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> References: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> Message-ID: <159131865505.18509.4598146394715373960@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake URL : https://patchwork.freedesktop.org/series/78019/ State : success == Summary == CI Bug Log - changes from CI_DRM_8588 -> Patchwork_17880 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/index.html Known issues ------------ Here are the changes found in Patchwork_17880 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-tgl-y: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-b.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (51 -> 43) ------------------------------ Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8588 -> Patchwork_17880 CI-20190529: 20190529 CI_DRM_8588: 294330ea49d6c0763514747ebc994f0b29a5afbe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17880: e9614a0decc2832e66f99bf0681151dd4488be2b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e9614a0decc2 drm/i915/psr: Program default IO buffer Wake and Fast Wake == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/index.html From jose.souza at intel.com Fri Jun 5 01:51:19 2020 From: jose.souza at intel.com (Souza, Jose) Date: Fri, 5 Jun 2020 01:51:19 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/psr: Program default IO buffer Wake and Fast Wake In-Reply-To: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> References: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> Message-ID: <863417d4a19babccaaafeaf00b1c8bdb8cbc8562.camel@intel.com> On Fri, 2020-06-05 at 03:23 +0300, Gwan-gyeong Mun wrote: > The IO buffer Wake and Fast Wake bit size and value have been changed from > Gen12+. > It programs default value of IO buffer Wake and Fast Wake on Gen12+. > > - Pre Gen12 > Bit location: IO buffer Wake: Register_PSR2_CTL[14:13] > Fast Wake: Register_PSR2_CTL[12:11] > > Value: 0x0: 8 lines > 0x1: 7 lines > 0x2: 6 lines > 0x3: 5 lines > > - Gen12+ > Bit location: IO buffer Wake: Register_PSR2_CTL[15:13] > Fast Wake: Register_PSR2_CTL[12:10] > > Value: 0x0: 5 lines > 0x1: 6 lines > 0x2: 7 lines > 0x3: 8 lines > 0x4: 9 lines > 0x5: 10 lines > 0x6: 11 lines > 0x7: 12 lines If you define the macro like bellow you don't need to add this information to the commit description. > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 2 files changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index b7a2c102648a..de2a17fe8860 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -518,6 +518,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > else > val |= EDP_PSR2_TP2_TIME_2500us; > > + if (INTEL_GEN(dev_priv) >= 12) { > + /* > + * TODO: In order to setting an optimal power consumption, > + * lower than 4k resoluition mode needs to decrese IO_BUFFER_WAKE > + * and FAST_WAKE. And higher than 4K resolution mode needs > + * to increase IO_BUFFER_WAKE and FAST_WAKE. > + */ > + u32 io_buffer_wake = 0x2; /* default BSpec value, 7 lines */ > + u32 fast_wake = 0x2; /* default BSpec value, 7 lines */ > + > + /* > + * To program line 9 to 12 on IO_BUFFER_WAKE and FAST_WAKE, > + * EDP_PSR2_CTL should be set EDP_PSR2_BLOCK_COUNT_NUM_3. > + */ > + val |= EDP_PSR2_BLOCK_COUNT_NUM_2; > + val |= EDP_PSR2_IO_BUFFER_WAKE(io_buffer_wake); > + val |= EDP_PSR2_FAST_WAKE(fast_wake); The parameter for this 2 macros should be the number of the lines not the bit value. As you are at it, please set the GEN9+ default values, the TGL macros will need a "TGL_" prefix. > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > * recommending keep this bit unset while PSR2 is enabled. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 96d351fbeebb..d055b7d93a5d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4514,10 +4514,16 @@ enum { > #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > #define EDP_PSR2_ENABLE (1 << 31) > #define EDP_SU_TRACK_ENABLE (1 << 30) > +#define EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) /* TGL+ */ > +#define EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) /* TGL+ */ > #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > +#define EDP_PSR2_IO_BUFFER_WAKE(a) ((a) << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (0x7 << 13) /* TGL+ */ > +#define EDP_PSR2_FAST_WAKE(a) ((a) << 10) /* TGL+ */ > +#define EDP_PSR2_FAST_WAKE_MASK (0x7 << 10) /* TGL+ */ > #define EDP_PSR2_TP2_TIME_500us (0 << 8) > #define EDP_PSR2_TP2_TIME_100us (1 << 8) > #define EDP_PSR2_TP2_TIME_2500us (2 << 8) From jose.souza at intel.com Fri Jun 5 02:40:45 2020 From: jose.souza at intel.com (Souza, Jose) Date: Fri, 5 Jun 2020 02:40:45 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Add_psr=5Fsafest=5Fparams?= In-Reply-To: <159007707803.4442.11836084606547528845@emeril.freedesktop.org> References: <20200520212756.354623-1-jose.souza@intel.com> <159007707803.4442.11836084606547528845@emeril.freedesktop.org> Message-ID: <d6aa1618aa9f7be36468286a1feeb2f79443ffbf.camel@intel.com> On Thu, 2020-05-21 at 16:04 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915: Add psr_safest_params > URL : https://patchwork.freedesktop.org/series/77491/ > State : success Pushed to dinq, thanks for the review GG. > > == Summary == > > CI Bug Log - changes from CI_DRM_8515_full -> Patchwork_17738_full > ==================================================== > > Summary > ------- > > **WARNING** > > Minor unknown changes coming with Patchwork_17738_full need to be verified > manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17738_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17738_full: > > ### IGT changes ### > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][1] ([i915#588]) -> [SKIP][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-iclb3/igt at i915_pm_dc@dc3co-vpb-simulation.html > > > New tests > --------- > > New tests have been introduced between CI_DRM_8515_full and Patchwork_17738_full: > > ### New IGT tests (74) ### > > * igt at kms_big_fb@linear-16bpp-rotate-0: > - Statuses : 7 pass(s) > - Exec time: [1.51, 7.43] s > > * igt at kms_big_fb@linear-16bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.61, 7.23] s > > * igt at kms_big_fb@linear-16bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.01, 0.19] s > > * igt at kms_big_fb@linear-16bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.02, 0.19] s > > * igt at kms_big_fb@linear-32bpp-rotate-0: > - Statuses : 7 pass(s) > - Exec time: [1.65, 11.03] s > > * igt at kms_big_fb@linear-32bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.63, 10.83] s > > * igt at kms_big_fb@linear-32bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.01, 0.20] s > > * igt at kms_big_fb@linear-32bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.01, 0.19] s > > * igt at kms_big_fb@linear-64bpp-rotate-0: > - Statuses : 6 pass(s) > - Exec time: [1.91, 10.99] s > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.92, 10.95] s > > * igt at kms_big_fb@linear-64bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.04, 0.78] s > > * igt at kms_big_fb@linear-64bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.06, 0.85] s > > * igt at kms_big_fb@linear-8bpp-rotate-0: > - Statuses : 7 pass(s) > - Exec time: [1.46, 6.00] s > > * igt at kms_big_fb@linear-8bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.48, 5.51] s > > * igt at kms_big_fb@linear-8bpp-rotate-270: > - Statuses : 6 skip(s) > - Exec time: [0.02, 0.21] s > > * igt at kms_big_fb@linear-8bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.02, 0.30] s > > * igt at kms_big_fb@linear-addfb: > - Statuses : 7 pass(s) > - Exec time: [0.0, 0.00] s > > * igt at kms_big_fb@x-tiled-16bpp-rotate-0: > - Statuses : 7 pass(s) > - Exec time: [1.46, 7.09] s > > * igt at kms_big_fb@x-tiled-16bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.58, 7.07] s > > * igt at kms_big_fb@x-tiled-16bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.01, 0.19] s > > * igt at kms_big_fb@x-tiled-16bpp-rotate-90: > - Statuses : 6 skip(s) > - Exec time: [0.01, 0.20] s > > * igt at kms_big_fb@x-tiled-32bpp-rotate-0: > - Statuses : 7 pass(s) > - Exec time: [1.56, 10.64] s > > * igt at kms_big_fb@x-tiled-32bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.59, 10.58] s > > * igt at kms_big_fb@x-tiled-32bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.01, 0.21] s > > * igt at kms_big_fb@x-tiled-32bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.02, 0.21] s > > * igt at kms_big_fb@x-tiled-64bpp-rotate-0: > - Statuses : 7 pass(s) > - Exec time: [1.87, 11.61] s > > * igt at kms_big_fb@x-tiled-64bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.97, 10.64] s > > * igt at kms_big_fb@x-tiled-64bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.04, 0.87] s > > * igt at kms_big_fb@x-tiled-64bpp-rotate-90: > - Statuses : 6 skip(s) > - Exec time: [0.05, 0.76] s > > * igt at kms_big_fb@x-tiled-8bpp-rotate-0: > - Statuses : 7 pass(s) > - Exec time: [1.28, 5.08] s > > * igt at kms_big_fb@x-tiled-8bpp-rotate-180: > - Statuses : 7 pass(s) > - Exec time: [1.40, 5.49] s > > * igt at kms_big_fb@x-tiled-8bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.02, 0.29] s > > * igt at kms_big_fb@x-tiled-8bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.03, 0.42] s > > * igt at kms_big_fb@x-tiled-addfb: > - Statuses : 7 pass(s) > - Exec time: [0.0, 0.00] s > > * igt at kms_big_fb@x-tiled-addfb-size-offset-overflow: > - Statuses : 4 pass(s) 3 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@x-tiled-addfb-size-overflow: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 0.00] s > > * igt at kms_big_fb@y-tiled-16bpp-rotate-0: > - Statuses : 5 pass(s) 1 skip(s) > - Exec time: [0.0, 7.18] s > > * igt at kms_big_fb@y-tiled-16bpp-rotate-180: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 7.01] s > > * igt at kms_big_fb@y-tiled-16bpp-rotate-270: > - Statuses : 2 pass(s) 5 skip(s) > - Exec time: [0.0, 1.64] s > > * igt at kms_big_fb@y-tiled-16bpp-rotate-90: > - Statuses : 2 pass(s) 5 skip(s) > - Exec time: [0.0, 1.90] s > > * igt at kms_big_fb@y-tiled-32bpp-rotate-0: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 10.76] s > > * igt at kms_big_fb@y-tiled-32bpp-rotate-180: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 11.56] s > > * igt at kms_big_fb@y-tiled-32bpp-rotate-270: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 11.24] s > > * igt at kms_big_fb@y-tiled-32bpp-rotate-90: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 10.58] s > > * igt at kms_big_fb@y-tiled-64bpp-rotate-0: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 7.04] s > > * igt at kms_big_fb@y-tiled-64bpp-rotate-180: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 7.79] s > > * igt at kms_big_fb@y-tiled-64bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.0, 0.99] s > > * igt at kms_big_fb@y-tiled-64bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.0, 0.96] s > > * igt at kms_big_fb@y-tiled-8bpp-rotate-0: > - Statuses : 5 pass(s) 1 skip(s) > - Exec time: [0.0, 2.45] s > > * igt at kms_big_fb@y-tiled-8bpp-rotate-180: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 5.08] s > > * igt at kms_big_fb@y-tiled-8bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.0, 0.34] s > > * igt at kms_big_fb@y-tiled-8bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.0, 0.42] s > > * igt at kms_big_fb@y-tiled-addfb: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 0.00] s > > * igt at kms_big_fb@y-tiled-addfb-size-offset-overflow: > - Statuses : 4 pass(s) 3 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@y-tiled-addfb-size-overflow: > - Statuses : 6 pass(s) 1 skip(s) > - Exec time: [0.0, 0.00] s > > * igt at kms_big_fb@yf-tiled-16bpp-rotate-0: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 7.47] s > > * igt at kms_big_fb@yf-tiled-16bpp-rotate-180: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 7.14] s > > * igt at kms_big_fb@yf-tiled-16bpp-rotate-270: > - Statuses : 1 pass(s) 5 skip(s) > - Exec time: [0.0, 1.85] s > > * igt at kms_big_fb@yf-tiled-16bpp-rotate-90: > - Statuses : 1 pass(s) 5 skip(s) > - Exec time: [0.0, 1.68] s > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 11.56] s > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-180: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 11.05] s > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 13.39] s > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-90: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 11.89] s > > * igt at kms_big_fb@yf-tiled-64bpp-rotate-0: > - Statuses : 7 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@yf-tiled-64bpp-rotate-180: > - Statuses : 7 skip(s) > - Exec time: [0.0, 0.05] s > > * igt at kms_big_fb@yf-tiled-64bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.0, 0.05] s > > * igt at kms_big_fb@yf-tiled-64bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@yf-tiled-8bpp-rotate-0: > - Statuses : 7 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@yf-tiled-8bpp-rotate-180: > - Statuses : 7 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@yf-tiled-8bpp-rotate-270: > - Statuses : 7 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@yf-tiled-8bpp-rotate-90: > - Statuses : 7 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@yf-tiled-addfb: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 0.00] s > > * igt at kms_big_fb@yf-tiled-addfb-size-offset-overflow: > - Statuses : 3 pass(s) 4 skip(s) > - Exec time: [0.0] s > > * igt at kms_big_fb@yf-tiled-addfb-size-overflow: > - Statuses : 5 pass(s) 2 skip(s) > - Exec time: [0.0, 0.00] s > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17738_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gen9_exec_parse@allowed-all: > - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl3/igt at gen9_exec_parse@allowed-all.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl6/igt at gen9_exec_parse@allowed-all.html > > * igt at i915_selftest@live at execlists: > - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#1795] / [i915#1874]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl2/igt at i915_selftest@live at execlists.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl1/igt at i915_selftest@live at execlists.html > > * igt at kms_hdr@bpc-switch-dpms: > - shard-skl: [PASS][7] -> [FAIL][8] ([i915#1188]) +1 similar issue > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl8/igt at kms_hdr@bpc-switch-dpms.html > > * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt at kms_plane_cursor@pipe-a-overlay-size-256: > - shard-kbl: [PASS][15] -> [FAIL][16] ([i915#1559] / [i915#93] / [i915#95]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-kbl7/igt at kms_plane_cursor@pipe-a-overlay-size-256.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-kbl1/igt at kms_plane_cursor@pipe-a-overlay-size-256.html > - shard-apl: [PASS][17] -> [FAIL][18] ([i915#1559] / [i915#95]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl8/igt at kms_plane_cursor@pipe-a-overlay-size-256.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl3/igt at kms_plane_cursor@pipe-a-overlay-size-256.html > > * igt at kms_psr@psr2_basic: > - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-iclb2/igt at kms_psr@psr2_basic.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-iclb3/igt at kms_psr@psr2_basic.html > > * igt at kms_psr@suspend: > - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#198]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl6/igt at kms_psr@suspend.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl10/igt at kms_psr@suspend.html > > * igt at kms_vblank@pipe-b-accuracy-idle: > - shard-glk: [PASS][23] -> [FAIL][24] ([i915#43]) > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-glk6/igt at kms_vblank@pipe-b-accuracy-idle.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-glk1/igt at kms_vblank@pipe-b-accuracy-idle.html > > > #### Possible fixes #### > > * igt at gem_ctx_persistence@legacy-engines-mixed-process at render: > - shard-apl: [FAIL][25] ([i915#1528]) -> [PASS][26] > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl8/igt at gem_ctx_persistence@legacy-engines-mixed-process at render.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at render.html > > * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: > - shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +2 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > - shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +6 similar issues > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * {igt at kms_flip@flip-vs-suspend-interruptible at b-edp1}: > - shard-skl: [INCOMPLETE][31] ([i915#198]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl6/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl3/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html > > * igt at kms_flip_tiling@flip-changes-tiling-yf: > - shard-kbl: [FAIL][33] ([i915#699] / [i915#93] / [i915#95]) -> [PASS][34] > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-kbl2/igt at kms_flip_tiling@flip-changes-tiling-yf.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling-yf.html > > * igt at kms_frontbuffer_tracking@psr-suspend: > - shard-skl: [INCOMPLETE][35] ([i915#123] / [i915#69]) -> [PASS][36] > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl10/igt at kms_frontbuffer_tracking@psr-suspend.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl6/igt at kms_frontbuffer_tracking@psr-suspend.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][37] ([i915#1188]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [FAIL][39] ([fdo#108145] / [i915#265]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_psr@psr2_primary_render: > - shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-iclb3/igt at kms_psr@psr2_primary_render.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-iclb2/igt at kms_psr@psr2_primary_render.html > > * igt at kms_setmode@basic: > - shard-apl: [FAIL][43] ([i915#31]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl1/igt at kms_setmode@basic.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl8/igt at kms_setmode@basic.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc6-psr: > - shard-tglb: [SKIP][45] ([i915#468]) -> [FAIL][46] ([i915#454]) > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-tglb2/igt at i915_pm_dc@dc6-psr.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-tglb5/igt at i915_pm_dc@dc6-psr.html > > * igt at i915_pm_rc6_residency@rc6-idle: > - shard-iclb: [FAIL][47] ([i915#1515]) -> [WARN][48] ([i915#1515]) > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-iclb4/igt at i915_pm_rc6_residency@rc6-idle.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-iclb6/igt at i915_pm_rc6_residency@rc6-idle.html > > * igt at kms_content_protection@atomic: > - shard-apl: [TIMEOUT][49] ([i915#1319]) -> [FAIL][50] ([fdo#110321] / [fdo#110336]) > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl4/igt at kms_content_protection@atomic.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl1/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@atomic-dpms: > - shard-apl: [FAIL][51] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][52] ([i915#1319]) > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl8/igt at kms_content_protection@atomic-dpms.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl7/igt at kms_content_protection@atomic-dpms.html > > * igt at kms_content_protection@lic: > - shard-apl: [FAIL][53] ([fdo#110321]) -> [DMESG-FAIL][54] ([fdo#110321]) > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl6/igt at kms_content_protection@lic.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl2/igt at kms_content_protection@lic.html > > * igt at kms_content_protection@srm: > - shard-apl: [FAIL][55] ([fdo#110321]) -> [TIMEOUT][56] ([i915#1319]) > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-apl1/igt at kms_content_protection@srm.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-apl8/igt at kms_content_protection@srm.html > > * igt at kms_psr2_su@page_flip: > - shard-iclb: [FAIL][57] ([i915#608]) -> [SKIP][58] ([fdo#109642] / [fdo#111068]) > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8515/shard-iclb2/igt at kms_psr2_su@page_flip.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/shard-iclb6/igt at kms_psr2_su@page_flip.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559 > [i915#1795]: https://gitlab.freedesktop.org/drm/intel/issues/1795 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1874]: https://gitlab.freedesktop.org/drm/intel/issues/1874 > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8515 -> Patchwork_17738 > > CI-20190529: 20190529 > CI_DRM_8515: 41f9bb782f3bb2f30be09683184bbeecb1fd31bb @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5665: c5e5b0ce26fc321591a6d0235c639a1e8ec3cdfa @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17738: 7f3095d8f257cc9646071b19df534a8a5df7ed60 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17738/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 04:11:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 04:11:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Async_GPU_relocations_only?= In-Reply-To: <20200604211457.19696-1-chris@chris-wilson.co.uk> References: <20200604211457.19696-1-chris@chris-wilson.co.uk> Message-ID: <159133031122.18506.8287483097583441405@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Async GPU relocations only URL : https://patchwork.freedesktop.org/series/78016/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8588_full -> Patchwork_17878_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17878_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17878_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17878_full: ### IGT changes ### #### Possible regressions #### * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-snb2/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html - shard-hsw: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-hsw7/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-hsw5/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html #### Warnings #### * igt at kms_ccs@pipe-c-crc-primary-basic: - shard-hsw: [SKIP][5] ([fdo#109271]) -> [TIMEOUT][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-hsw7/igt at kms_ccs@pipe-c-crc-primary-basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-hsw5/igt at kms_ccs@pipe-c-crc-primary-basic.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [SKIP][7] ([fdo#109271]) -> [TIMEOUT][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-snb2/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [FAIL][9] ([i915#1930]) -> [TIMEOUT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html - shard-iclb: [FAIL][11] ([i915#1930]) -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb8/igt at gem_exec_reloc@basic-concurrent16.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-iclb3/igt at gem_exec_reloc@basic-concurrent16.html - shard-hsw: [FAIL][13] ([i915#1930]) -> [TIMEOUT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-hsw7/igt at gem_exec_reloc@basic-concurrent16.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-hsw5/igt at gem_exec_reloc@basic-concurrent16.html - shard-tglb: [FAIL][15] ([i915#1930]) -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb6/igt at gem_exec_reloc@basic-concurrent16.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-tglb2/igt at gem_exec_reloc@basic-concurrent16.html * {igt at kms_chamelium@vga-hpd-enable-disable-mode}: - shard-hsw: [SKIP][17] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-hsw7/igt at kms_chamelium@vga-hpd-enable-disable-mode.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-hsw5/igt at kms_chamelium@vga-hpd-enable-disable-mode.html - shard-snb: [SKIP][19] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-snb6/igt at kms_chamelium@vga-hpd-enable-disable-mode.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-snb2/igt at kms_chamelium@vga-hpd-enable-disable-mode.html Known issues ------------ Here are the changes found in Patchwork_17878_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-normal: - shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#118] / [i915#95]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk1/igt at gem_exec_whisper@basic-normal.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-glk5/igt at gem_exec_whisper@basic-normal.html * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl1/igt at gem_workarounds@suspend-resume-fd.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl6/igt at gem_workarounds@suspend-resume-fd.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_color@pipe-d-ctm-0-5: - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1149] / [i915#402]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-tglb8/igt at kms_color@pipe-d-ctm-0-5.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [PASS][29] -> [DMESG-FAIL][30] ([i915#54] / [i915#95]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +16 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl4/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl10/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#128]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb5/igt at kms_cursor_legacy@pipe-c-torture-bo.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-iclb5/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#95]) +19 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][39] -> [DMESG-WARN][40] ([i915#93] / [i915#95]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [PASS][41] -> [FAIL][42] ([i915#49]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl9/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl10/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][43] -> [FAIL][44] ([i915#1188]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl4/igt at kms_hdr@bpc-switch.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl6/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][45] -> [DMESG-WARN][46] ([i915#180]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][47] -> [FAIL][48] ([fdo#108145] / [i915#265]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109441]) +2 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-iclb4/igt at kms_psr@psr2_cursor_blt.html * igt at kms_setmode@basic: - shard-kbl: [PASS][51] -> [FAIL][52] ([i915#31]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl1/igt at kms_setmode@basic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl6/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-b-wait-busy: - shard-kbl: [PASS][53] -> [DMESG-WARN][54] ([i915#1982]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl1/igt at kms_vblank@pipe-b-wait-busy.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl6/igt at kms_vblank@pipe-b-wait-busy.html #### Possible fixes #### * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][55] ([i915#1436] / [i915#716]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl6/igt at gen9_exec_parse@allowed-all.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl4/igt at gen9_exec_parse@allowed-all.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][57] ([i915#454]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb4/igt at i915_pm_dc@dc6-psr.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-iclb7/igt at i915_pm_dc@dc6-psr.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: - shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +5 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl9/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][61] ([i915#93] / [i915#95]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][63] ([i915#54]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl10/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [DMESG-WARN][65] ([i915#95]) -> [PASS][66] +19 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl7/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled: - shard-apl: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl7/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-glk: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk8/igt at kms_fbcon_fbt@fbc-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-glk8/igt at kms_fbcon_fbt@fbc-suspend.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1}: - shard-glk: [FAIL][71] ([i915#79]) -> [PASS][72] +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk7/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-glk4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [FAIL][73] ([i915#49]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl1/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl10/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][75] ([i915#1188]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +3 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][79] ([fdo#108145] / [i915#265]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][81] ([fdo#109441]) -> [PASS][82] +2 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb6/igt at kms_psr@psr2_primary_page_flip.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_setmode@basic: - shard-skl: [FAIL][83] ([i915#31]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl8/igt at kms_setmode@basic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl2/igt at kms_setmode@basic.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-tglb: [DMESG-WARN][85] ([i915#1982]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb1/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-tglb6/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html #### Warnings #### * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [SKIP][87] ([fdo#109271] / [fdo#111827]) -> [INCOMPLETE][88] ([i915#82]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-snb6/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-snb2/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][89] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][90] ([i915#1319] / [i915#1635]) +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl1/igt at kms_content_protection@atomic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][91] ([i915#1319] / [i915#1635]) -> [FAIL][92] ([fdo#110321] / [fdo#110336]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_content_protection@atomic-dpms.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][93] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][94] ([fdo#110321] / [i915#95]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl3/igt at kms_content_protection@srm.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-hsw: [SKIP][95] ([fdo#109271]) -> [INCOMPLETE][96] ([i915#61]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-hsw7/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-hsw5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-skl: [FAIL][97] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][98] ([fdo#108145] / [i915#1982]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt at runner@aborted: - shard-tglb: [FAIL][99] ([i915#1602]) -> ([FAIL][100], [FAIL][101]) ([i915#1602] / [i915#1759]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb7/igt at runner@aborted.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-tglb3/igt at runner@aborted.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/shard-tglb7/igt at runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8588 -> Patchwork_17878 CI-20190529: 20190529 CI_DRM_8588: 294330ea49d6c0763514747ebc994f0b29a5afbe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17878: 7b08ef0f711fac0ebdbfe22db9a445f3c3361e27 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17878/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 05:47:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 05:47:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/rkl=3A_Program_BW=5FBUDDY0?= =?utf-8?q?_registers_instead_of_BW=5FBUDDY1/2?= In-Reply-To: <20200604235321.3190817-1-matthew.d.roper@intel.com> References: <20200604235321.3190817-1-matthew.d.roper@intel.com> Message-ID: <159133605121.18506.15481920089383679882@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 URL : https://patchwork.freedesktop.org/series/78018/ State : success == Summary == CI Bug Log - changes from CI_DRM_8588_full -> Patchwork_17879_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17879_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_param@basic: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +18 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl3/igt at gem_ctx_param@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl7/igt at gem_ctx_param@basic.html * igt at gem_exec_params@control: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb2/igt at gem_exec_params@control.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-tglb1/igt at gem_exec_params@control.html * igt at gem_exec_whisper@basic-contexts-priority: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk9/igt at gem_exec_whisper@basic-contexts-priority.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-glk2/igt at gem_exec_whisper@basic-contexts-priority.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([i915#155]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl6/igt at i915_suspend@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl1/igt at i915_suspend@debugfs-reader.html * igt at i915_suspend@forcewake: - shard-glk: [PASS][9] -> [INCOMPLETE][10] ([i915#58] / [k.org#198133]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk4/igt at i915_suspend@forcewake.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-glk6/igt at i915_suspend@forcewake.html - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#636] / [i915#69]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl1/igt at i915_suspend@forcewake.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl5/igt at i915_suspend@forcewake.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at i915_suspend@sysfs-reader.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl4/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl10/igt at kms_color@pipe-c-ctm-0-25.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl10/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_color@pipe-d-ctm-0-5: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1149] / [i915#402]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-tglb2/igt at kms_color@pipe-d-ctm-0-5.html * igt at kms_cursor_crc@pipe-a-cursor-128x128-offscreen: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl8/igt at kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl9/igt at kms_cursor_crc@pipe-a-cursor-128x128-offscreen.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +8 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-b-cursor-256x256-sliding: - shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-snb2/igt at kms_cursor_crc@pipe-b-cursor-256x256-sliding.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-snb1/igt at kms_cursor_crc@pipe-b-cursor-256x256-sliding.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#128]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl1/igt at kms_cursor_legacy@all-pipes-torture-move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl7/igt at kms_cursor_legacy@all-pipes-torture-move.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl3/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl2/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [PASS][33] -> [FAIL][34] ([i915#49]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl9/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl1/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145] / [i915#265]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-iclb5/igt at kms_psr@psr2_cursor_blt.html * igt at kms_setmode@basic: - shard-kbl: [PASS][39] -> [FAIL][40] ([i915#31]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl1/igt at kms_setmode@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl7/igt at kms_setmode@basic.html #### Possible fixes #### * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk4/igt at gem_exec_whisper@basic-queues-forked-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-glk8/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][43] ([i915#1436] / [i915#716]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl6/igt at gen9_exec_parse@allowed-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl2/igt at gen9_exec_parse@allowed-all.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][45] ([i915#454]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb4/igt at i915_pm_dc@dc6-psr.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-iclb5/igt at i915_pm_dc@dc6-psr.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][47] ([i915#118] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][49] ([i915#93] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl3/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [DMESG-WARN][51] ([i915#95]) -> [PASS][52] +14 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled: - shard-apl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl6/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1}: - shard-glk: [FAIL][55] ([i915#79]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk7/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-glk4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl2/igt at kms_hdr@bpc-switch-dpms.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_scaling@pipe-c-plane-scaling: - shard-skl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +4 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl2/igt at kms_plane_scaling@pipe-c-plane-scaling.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-skl3/igt at kms_plane_scaling@pipe-c-plane-scaling.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb3/igt at kms_psr2_su@page_flip.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb6/igt at kms_psr@psr2_sprite_plane_move.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-tglb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb1/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-tglb2/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html * igt at perf_pmu@other-init-1: - shard-iclb: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb7/igt at perf_pmu@other-init-1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-iclb4/igt at perf_pmu@other-init-1.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [SKIP][73] ([fdo#109271]) -> [INCOMPLETE][74] ([i915#82]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-snb6/igt at i915_pm_dc@dc3co-vpb-simulation.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-snb6/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][75] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl1/igt at kms_content_protection@atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][77] ([fdo#110321] / [i915#95]) -> [TIMEOUT][78] ([i915#1319] / [i915#1635]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl2/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl3/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][80] ([fdo#110321] / [i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl3/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-apl4/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][81] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][82] ([i915#93] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8588 -> Patchwork_17879 CI-20190529: 20190529 CI_DRM_8588: 294330ea49d6c0763514747ebc994f0b29a5afbe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17879: 2b4ef2a8b8d4062203cb55a06187f02ff458b6f9 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17879/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 06:34:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 06:34:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake?= In-Reply-To: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> References: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> Message-ID: <159133889665.18509.12475960341884433098@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake URL : https://patchwork.freedesktop.org/series/78019/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8588_full -> Patchwork_17880_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17880_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17880_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17880_full: ### IGT changes ### #### Possible regressions #### * igt at i915_suspend@forcewake: - shard-apl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl7/igt at i915_suspend@forcewake.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl2/igt at i915_suspend@forcewake.html Known issues ------------ Here are the changes found in Patchwork_17880_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_param@basic: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl3/igt at gem_ctx_param@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl1/igt at gem_ctx_param@basic.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk2/igt at gem_exec_whisper@basic-contexts-forked.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk9/igt at gem_exec_whisper@basic-contexts-forked.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][7] -> [INCOMPLETE][8] ([i915#155]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl6/igt at i915_suspend@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-kbl3/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_color@pipe-d-ctm-0-5: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#1149] / [i915#402]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@all-pipes-torture-bo: - shard-iclb: [PASS][15] -> [DMESG-WARN][16] ([i915#128]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb1/igt at kms_cursor_legacy@all-pipes-torture-bo.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-iclb1/igt at kms_cursor_legacy@all-pipes-torture-bo.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-skl2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@flip-vs-cursor-toggle: - shard-skl: [PASS][19] -> [FAIL][20] ([IGT#5] / [i915#697]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl8/igt at kms_cursor_legacy@flip-vs-cursor-toggle.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-toggle.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#128]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb7/igt at kms_cursor_legacy@pipe-b-torture-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-tglb6/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#93] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack: - shard-iclb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb8/igt at kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-iclb8/igt at kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-glk: [PASS][27] -> [INCOMPLETE][28] ([i915#58] / [k.org#198133]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk6/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk4/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-glk: [PASS][31] -> [TIMEOUT][32] ([i915#1958]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk4/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-iclb5/igt at kms_psr@psr2_cursor_blt.html * igt at kms_setmode@basic: - shard-kbl: [PASS][35] -> [FAIL][36] ([i915#31]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl1/igt at kms_setmode@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-kbl2/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-skl: [PASS][37] -> [INCOMPLETE][38] ([i915#69]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl8/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-skl8/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html #### Possible fixes #### * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk4/igt at gem_exec_whisper@basic-queues-forked-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk5/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][41] ([i915#454]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb4/igt at i915_pm_dc@dc6-psr.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-iclb3/igt at i915_pm_dc@dc6-psr.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [DMESG-WARN][47] ([i915#95]) -> [PASS][48] +13 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl7/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled: - shard-apl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-glk: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk8/igt at kms_fbcon_fbt@fbc-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk6/igt at kms_fbcon_fbt@fbc-suspend.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1}: - shard-glk: [FAIL][53] ([i915#79]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk7/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk1/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a1.html * {igt at kms_flip@flip-vs-suspend-interruptible at b-dp1}: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-FAIL][59] ([fdo#108145] / [i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-c-plane-scaling: - shard-skl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +6 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-skl2/igt at kms_plane_scaling@pipe-c-plane-scaling.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-skl2/igt at kms_plane_scaling@pipe-c-plane-scaling.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb5/igt at kms_psr@psr2_sprite_mmap_cpu.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at perf_pmu@other-init-1: - shard-iclb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-iclb7/igt at perf_pmu@other-init-1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-iclb8/igt at perf_pmu@other-init-1.html #### Warnings #### * igt at kms_ccs@pipe-c-crc-primary-basic: - shard-glk: [SKIP][69] ([fdo#109271]) -> [TIMEOUT][70] ([i915#1958]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-glk6/igt at kms_ccs@pipe-c-crc-primary-basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-glk4/igt at kms_ccs@pipe-c-crc-primary-basic.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][71] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl1/igt at kms_content_protection@atomic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [FAIL][74] ([fdo#110321] / [fdo#110336]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][75] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][76] ([i915#93] / [i915#95]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html - shard-apl: [DMESG-WARN][77] ([i915#95]) -> [DMESG-WARN][78] ([i915#180] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at runner@aborted: - shard-tglb: [FAIL][79] ([i915#1602]) -> ([FAIL][80], [FAIL][81]) ([i915#1602] / [i915#1759]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8588/shard-tglb7/igt at runner@aborted.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-tglb8/igt at runner@aborted.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/shard-tglb8/igt at runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#697]: https://gitlab.freedesktop.org/drm/intel/issues/697 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8588 -> Patchwork_17880 CI-20190529: 20190529 CI_DRM_8588: 294330ea49d6c0763514747ebc994f0b29a5afbe @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17880: e9614a0decc2832e66f99bf0681151dd4488be2b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17880/index.html From christian.koenig at amd.com Fri Jun 5 07:45:29 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Fri, 5 Jun 2020 09:45:29 +0200 Subject: [Intel-gfx] [PATCH v2 1/1] drm/mm: add ig_frag selftest In-Reply-To: <20200603103223.10443-1-nirmoy.das@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> Message-ID: <d11d0f7b-6273-e1be-65db-1698e9c31228@amd.com> Am 03.06.20 um 12:32 schrieb Nirmoy Das: > This patch introduces fragmentation in the address range > and measures time taken by 10k and 20k insertions. ig_frag() > will fail if the time taken by 20k insertions takes more than > 4 times of 10k insertions as we know that insertions should at > most scale quadratically. > > v2: > introduce fragmentation by freeing every other node. > only test bottom-up and top-down for now. > > Signed-off-by: Nirmoy Das <nirmoy.das at amd.com> > --- > drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + > drivers/gpu/drm/selftests/test-drm_mm.c | 124 +++++++++++++++++++ > 2 files changed, 125 insertions(+) > > diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h b/drivers/gpu/drm/selftests/drm_mm_selftests.h > index 6b943ea1c57d..8c87c964176b 100644 > --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h > +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h > @@ -14,6 +14,7 @@ selftest(insert, igt_insert) > selftest(replace, igt_replace) > selftest(insert_range, igt_insert_range) > selftest(align, igt_align) > +selftest(frag, igt_frag) > selftest(align32, igt_align32) > selftest(align64, igt_align64) > selftest(evict, igt_evict) > diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c b/drivers/gpu/drm/selftests/test-drm_mm.c > index 9aabe82dcd3a..34231baacd87 100644 > --- a/drivers/gpu/drm/selftests/test-drm_mm.c > +++ b/drivers/gpu/drm/selftests/test-drm_mm.c > @@ -10,6 +10,7 @@ > #include <linux/slab.h> > #include <linux/random.h> > #include <linux/vmalloc.h> > +#include <linux/ktime.h> > > #include <drm/drm_mm.h> > > @@ -1033,6 +1034,129 @@ static int igt_insert_range(void *ignored) > return 0; > } > > +static int prepare_igt_frag(struct drm_mm *mm, > + struct drm_mm_node *nodes, > + unsigned int num_insert, > + const struct insert_mode *mode) > +{ > + unsigned int size = 4096; > + unsigned int i; > + u64 ret = -EINVAL; > + > + for (i = 0; i < num_insert; i++) { > + if (!expect_insert(mm, &nodes[i], size, 0, i, > + mode) != 0) { > + pr_err("%s insert failed\n", mode->name); > + goto out; > + } > + } > + > + /* introduce fragmentation by freeing every other node */ > + for (i = 0; i < num_insert; i++) { > + if (i % 2 == 0) > + drm_mm_remove_node(&nodes[i]); > + } > + > +out: > + return ret; > + > +} > + > +static u64 get_insert_time(struct drm_mm *mm, > + unsigned int num_insert, > + struct drm_mm_node *nodes, > + const struct insert_mode *mode) > +{ > + unsigned int size = 8192; > + ktime_t start; > + unsigned int i; > + u64 ret = -EINVAL; > + > + start = ktime_get(); > + for (i = 0; i < num_insert; i++) { > + if (!expect_insert(mm, &nodes[i], size, 0, i, mode) != 0) { > + pr_err("%s insert failed\n", mode->name); > + goto out; > + } > + } > + > + ret = ktime_to_ns(ktime_sub(ktime_get(), start)); > + > +out: > + return ret; > + > +} > + > +static int igt_frag(void *ignored) > +{ > + struct drm_mm mm; > + const struct insert_mode *mode; > + struct drm_mm_node *nodes, *node, *next; > + unsigned int insert_size = 10000; > + unsigned int scale_factor = 4; > + int ret = -EINVAL; > + > + /* We need 4 * insert_size nodes to hold intermediate allocated > + * drm_mm nodes. > + * 1 times for prepare_igt_frag() > + * 1 times for get_insert_time() > + * 2 times for get_insert_time() > + */ > + nodes = vzalloc(array_size(insert_size * 4, sizeof(*nodes))); > + if (!nodes) > + return -ENOMEM; > + > + /* For BOTTOMUP and TOPDOWN, we first fragment the > + * address space using prepare_igt_frag() and then try to verify > + * that that insertions scale quadratically from 10k to 20k insertions > + */ > + drm_mm_init(&mm, 1, U64_MAX - 2); > + for (mode = insert_modes; mode->name; mode++) { > + u64 insert_time1, insert_time2; > + > + if (mode->mode != DRM_MM_INSERT_LOW || > + mode->mode != DRM_MM_INSERT_HIGH) > + continue; This check here is wrong, that needs to be && instead of || or the test wouldn't execute at all. Christian. > + > + ret = prepare_igt_frag(&mm, nodes, insert_size, mode); > + if (!ret) > + goto err; > + > + insert_time1 = get_insert_time(&mm, insert_size, > + nodes + insert_size, mode); > + if (insert_time1 < 0) > + goto err; > + > + insert_time2 = get_insert_time(&mm, (insert_size * 2), > + nodes + insert_size * 2, mode); > + if (insert_time2 < 0) > + goto err; > + > + pr_info("%s fragmented insert of %u and %u insertions took %llu and %llu nsecs\n", > + mode->name, insert_size, insert_size * 2, > + insert_time1, insert_time2); > + > + if (insert_time2 > (scale_factor * insert_time1)) { > + pr_err("%s fragmented insert took %llu nsecs more\n", > + mode->name, > + insert_time2 - (scale_factor * insert_time1)); > + goto err; > + } > + > + drm_mm_for_each_node_safe(node, next, &mm) > + drm_mm_remove_node(node); > + } > + > + ret = 0; > +err: > + drm_mm_for_each_node_safe(node, next, &mm) > + drm_mm_remove_node(node); > + drm_mm_takedown(&mm); > + vfree(nodes); > + > + return ret; > +} > + > static int igt_align(void *ignored) > { > const struct insert_mode *mode; From pierre-eric.pelloux-prayer at amd.com Fri Jun 5 08:30:01 2020 From: pierre-eric.pelloux-prayer at amd.com (Pierre-Eric Pelloux-Prayer) Date: Fri, 5 Jun 2020 10:30:01 +0200 Subject: [Intel-gfx] [PATCH 13/18] drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail In-Reply-To: <20200604081224.863494-14-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-14-daniel.vetter@ffwll.ch> Message-ID: <e0bfd872-5d38-6718-a23d-6b14b3c14f25@amd.com> Hi Daniel, On 04/06/2020 10:12, Daniel Vetter wrote: [...] > @@ -6910,7 +6910,11 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, > * explicitly on fences instead > * and in general should be called for > * blocking commit to as per framework helpers > + * > + * Yes, this deadlocks, since you're calling dma_resv_lock in a > + * path that leads to a dma_fence_signal(). Don't do that. > */ > +#if 0 > r = amdgpu_bo_reserve(abo, true); > if (unlikely(r != 0)) > DRM_ERROR("failed to reserve buffer before flip\n"); > @@ -6920,6 +6924,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, > tmz_surface = amdgpu_bo_encrypted(abo); > > amdgpu_bo_unreserve(abo); > +#endif > + /* > + * this races anyway, so READ_ONCE isn't any better or worse > + * than the stuff above. Except the stuff above can deadlock. > + */ > + tiling_flags = READ_ONCE(abo->tiling_flags); With this change "tmz_surface" won't be initialized properly. Adding the following line should fix it: tmz_surface = READ_ONCE(abo->flags) & AMDGPU_GEM_CREATE_ENCRYPTED; Pierre-Eric > > fill_dc_plane_info_and_addr( > dm->adev, new_plane_state, tiling_flags, > From christian.koenig at amd.com Fri Jun 5 08:39:46 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Fri, 5 Jun 2020 10:39:46 +0200 Subject: [Intel-gfx] [PATCH v2 1/1] drm/mm: add ig_frag selftest In-Reply-To: <f4368a5f-083c-9718-ad3d-95d45e89f107@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> <d11d0f7b-6273-e1be-65db-1698e9c31228@amd.com> <f4368a5f-083c-9718-ad3d-95d45e89f107@amd.com> Message-ID: <ffb4d3af-0522-bb2f-a2f0-962da4d9c634@amd.com> Am 05.06.20 um 10:18 schrieb Nirmoy: > > On 6/5/20 9:45 AM, Christian K?nig wrote: >> Am 03.06.20 um 12:32 schrieb Nirmoy Das: >>> This patch introduces fragmentation in the address range >>> and measures time taken by 10k and 20k insertions. ig_frag() >>> will fail if the time taken by 20k insertions takes more than >>> 4 times of 10k insertions as we know that insertions should at >>> most scale quadratically. >>> >>> v2: >>> introduce fragmentation by freeing every other node. >>> only test bottom-up and top-down for now. >>> >>> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com> >>> --- >>> ? drivers/gpu/drm/selftests/drm_mm_selftests.h |?? 1 + >>> ? drivers/gpu/drm/selftests/test-drm_mm.c????? | 124 >>> +++++++++++++++++++ >>> ? 2 files changed, 125 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>> b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>> index 6b943ea1c57d..8c87c964176b 100644 >>> --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h >>> +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h >>> @@ -14,6 +14,7 @@ selftest(insert, igt_insert) >>> ? selftest(replace, igt_replace) >>> ? selftest(insert_range, igt_insert_range) >>> ? selftest(align, igt_align) >>> +selftest(frag, igt_frag) >>> ? selftest(align32, igt_align32) >>> ? selftest(align64, igt_align64) >>> ? selftest(evict, igt_evict) >>> diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c >>> b/drivers/gpu/drm/selftests/test-drm_mm.c >>> index 9aabe82dcd3a..34231baacd87 100644 >>> --- a/drivers/gpu/drm/selftests/test-drm_mm.c >>> +++ b/drivers/gpu/drm/selftests/test-drm_mm.c >>> @@ -10,6 +10,7 @@ >>> ? #include <linux/slab.h> >>> ? #include <linux/random.h> >>> ? #include <linux/vmalloc.h> >>> +#include <linux/ktime.h> >>> ? ? #include <drm/drm_mm.h> >>> ? @@ -1033,6 +1034,129 @@ static int igt_insert_range(void *ignored) >>> ????? return 0; >>> ? } >>> ? +static int prepare_igt_frag(struct drm_mm *mm, >>> +??????????????? struct drm_mm_node *nodes, >>> +??????????????? unsigned int num_insert, >>> +??????????????? const struct insert_mode *mode) >>> +{ >>> +??? unsigned int size = 4096; >>> +??? unsigned int i; >>> +??? u64 ret = -EINVAL; >>> + >>> +??? for (i = 0; i < num_insert; i++) { >>> +??????? if (!expect_insert(mm, &nodes[i], size, 0, i, >>> +?????????????????? mode) != 0) { >>> +??????????? pr_err("%s insert failed\n", mode->name); >>> +??????????? goto out; >>> +??????? } >>> +??? } >>> + >>> +??? /* introduce fragmentation by freeing every other node */ >>> +??? for (i = 0; i < num_insert; i++) { >>> +??????? if (i % 2 == 0) >>> +??????????? drm_mm_remove_node(&nodes[i]); >>> +??? } >>> + >>> +out: >>> +??? return ret; >>> + >>> +} >>> + >>> +static u64 get_insert_time(struct drm_mm *mm, >>> +?????????????? unsigned int num_insert, >>> +?????????????? struct drm_mm_node *nodes, >>> +?????????????? const struct insert_mode *mode) >>> +{ >>> +??? unsigned int size = 8192; >>> +??? ktime_t start; >>> +??? unsigned int i; >>> +??? u64 ret = -EINVAL; >>> + >>> +??? start = ktime_get(); >>> +??? for (i = 0; i < num_insert; i++) { >>> +??????? if (!expect_insert(mm, &nodes[i], size, 0, i, mode) != 0) { >>> +??????????? pr_err("%s insert failed\n", mode->name); >>> +??????????? goto out; >>> +??????? } >>> +??? } >>> + >>> +??? ret = ktime_to_ns(ktime_sub(ktime_get(), start)); >>> + >>> +out: >>> +??? return ret; >>> + >>> +} >>> + >>> +static int igt_frag(void *ignored) >>> +{ >>> +??? struct drm_mm mm; >>> +??? const struct insert_mode *mode; >>> +??? struct drm_mm_node *nodes, *node, *next; >>> +??? unsigned int insert_size = 10000; >>> +??? unsigned int scale_factor = 4; >>> +??? int ret = -EINVAL; >>> + >>> +??? /* We need 4 * insert_size nodes to hold intermediate allocated >>> +???? * drm_mm nodes. >>> +???? * 1 times for prepare_igt_frag() >>> +???? * 1 times for get_insert_time() >>> +???? * 2 times for? get_insert_time() >>> +???? */ >>> +??? nodes = vzalloc(array_size(insert_size * 4, sizeof(*nodes))); >>> +??? if (!nodes) >>> +??????? return -ENOMEM; >>> + >>> +??? /* For BOTTOMUP and TOPDOWN, we first fragment the >>> +???? * address space using prepare_igt_frag() and then try to verify >>> +???? * that that insertions scale quadratically from 10k to 20k >>> insertions >>> +???? */ >>> +??? drm_mm_init(&mm, 1, U64_MAX - 2); >>> +??? for (mode = insert_modes; mode->name; mode++) { >>> +??????? u64 insert_time1, insert_time2; >>> + >>> +??????? if (mode->mode != DRM_MM_INSERT_LOW || >>> +??????????? mode->mode != DRM_MM_INSERT_HIGH) >>> +??????????? continue; >> >> This check here is wrong, that needs to be && instead of || or the >> test wouldn't execute at all. > > > I didn't bother to check dmesg after adding that "simple" check and > the test ran fine. :/ Yeah, after that the test seems to work. But there are is another issues. We only cut of the right or the left branch of the tree and that still makes the implementation rather inefficient. In other words we first go down leftmost or rightmost even if we know that this way is no valuable candidate and then back off again towards the top. Going to look into this, but your patches already improves insertion time by a factor of nearly 30 in a fragmented address space. That is rather nice. Regards, Christian. > > Sending again. > > Nirmoy > > >> >> Christian. >> >>> + >>> +??????? ret = prepare_igt_frag(&mm, nodes, insert_size, mode); >>> +??????? if (!ret) >>> +??????????? goto err; >>> + >>> +??????? insert_time1 = get_insert_time(&mm, insert_size, >>> +?????????????????????????? nodes + insert_size, mode); >>> +??????? if (insert_time1 < 0) >>> +??????????? goto err; >>> + >>> +??????? insert_time2 = get_insert_time(&mm, (insert_size * 2), >>> +?????????????????????????? nodes + insert_size * 2, mode); >>> +??????? if (insert_time2 < 0) >>> +??????????? goto err; >>> + >>> +??????? pr_info("%s fragmented insert of %u and %u insertions took >>> %llu and %llu nsecs\n", >>> +??????????? mode->name, insert_size, insert_size * 2, >>> +??????????? insert_time1, insert_time2); >>> + >>> +??????? if (insert_time2 > (scale_factor * insert_time1)) { >>> +??????????? pr_err("%s fragmented insert took %llu nsecs more\n", >>> +?????????????????? mode->name, >>> +?????????????????? insert_time2 - (scale_factor * insert_time1)); >>> +??????????? goto err; >>> +??????? } >>> + >>> +??????? drm_mm_for_each_node_safe(node, next, &mm) >>> +??????????? drm_mm_remove_node(node); >>> +??? } >>> + >>> +??? ret = 0; >>> +err: >>> +??? drm_mm_for_each_node_safe(node, next, &mm) >>> +??????? drm_mm_remove_node(node); >>> +??? drm_mm_takedown(&mm); >>> +??? vfree(nodes); >>> + >>> +??? return ret; >>> +} >>> + >>> ? static int igt_align(void *ignored) >>> ? { >>> ????? const struct insert_mode *mode; >> From imre.deak at intel.com Fri Jun 5 09:16:21 2020 From: imre.deak at intel.com (Imre Deak) Date: Fri, 5 Jun 2020 12:16:21 +0300 Subject: [Intel-gfx] [PATCH v3 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <20200604184500.23730-1-imre.deak@intel.com> References: <20200604184500.23730-1-imre.deak@intel.com> Message-ID: <20200605091621.17026-1-imre.deak@intel.com> Currently MST on a port can get enabled/disabled from the hotplug work and get disabled from the short pulse work in a racy way. Fix this by relying on the MST state checking in the hotplug work and just schedule a hotplug work from the short pulse handler if some problem happened during the MST interrupt handling. This removes the explicit MST disabling in case of an AUX failure, but if AUX fails, then probably the detection will also fail during the scheduled hotplug work and it's not guaranteed that we'll see intermittent errors anyway. While at it also simplify the error checking of the MST interrupt handler. v2: - Convert intel_dp_check_mst_status() to return bool. (Ville) - Change the intel_dp->is_mst check to an assert, since after this patch the condition can't change after we checked it previously. - Document the return value from intel_dp_check_mst_status(). v3: - Remove the intel_dp->is_mst check from intel_dp_check_mst_status(). There is no point in checking the same condition twice, even though there is a chance that the hotplug work running concurrently changes it. Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> (v1) Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++--------------- 1 file changed, 26 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7ef60af8308b..ade21157f29b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5556,14 +5556,24 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) "Could not write test response to sink\n"); } -static int +/** + * intel_dp_check_mst_status - service any pending MST interrupts, check link status + * @intel_dp: Intel DP struct + * + * Read any pending MST interrupts, call MST core to handle these and ack the + * interrupts. Check if the main and AUX link state is ok. + * + * Returns: + * - %true if pending interrupts were serviced (or no interrupts were + * pending) w/o detecting an error condition. + * - %false if an error condition - like AUX failure or a loss of link - is + * detected, which needs servicing from the hotplug work. + */ +static bool intel_dp_check_mst_status(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - bool need_retrain = false; - - if (!intel_dp->is_mst) - return -EINVAL; + bool link_ok = true; drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); @@ -5591,22 +5601,23 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) for (;;) { u8 esi[DP_DPRX_ESI_LEN] = {}; - bool bret, handled; + bool handled; int retry; - bret = intel_dp_get_sink_irq_esi(intel_dp, esi); - if (!bret) { + if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { drm_dbg_kms(&i915->drm, "failed to get ESI - device may have failed\n"); - return -EINVAL; + link_ok = false; + + break; } /* check link status - esi[10] = 0x200c */ - if (intel_dp->active_mst_links > 0 && !need_retrain && + if (intel_dp->active_mst_links > 0 && link_ok && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { drm_dbg_kms(&i915->drm, "channel EQ not ok, retraining\n"); - need_retrain = true; + link_ok = false; } drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); @@ -5626,7 +5637,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) } } - return need_retrain; + return link_ok; } static bool @@ -7277,35 +7288,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) } if (intel_dp->is_mst) { - switch (intel_dp_check_mst_status(intel_dp)) { - case -EINVAL: - /* - * If we were in MST mode, and device is not - * there, get out of MST mode - */ - drm_dbg_kms(&i915->drm, - "MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, - intel_dp->mst_mgr.mst_state); - intel_dp->is_mst = false; - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, - intel_dp->is_mst); - - return IRQ_NONE; - case 1: - return IRQ_NONE; - default: - break; - } - } - - if (!intel_dp->is_mst) { - bool handled; - - handled = intel_dp_short_pulse(intel_dp); - - if (!handled) + if (!intel_dp_check_mst_status(intel_dp)) return IRQ_NONE; + } else if (!intel_dp_short_pulse(intel_dp)) { + return IRQ_NONE; } return IRQ_HANDLED; -- 2.23.1 From patchwork at emeril.freedesktop.org Fri Jun 5 09:27:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 09:27:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBz?= =?utf-8?q?eries_starting_with_=5Bv3=2C1/3=5D_drm/i915/dp=5Fmst=3A_Fix_dis?= =?utf-8?q?abling_MST_on_a_port_=28rev5=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159134927713.18507.2239887309536236434@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev5) URL : https://patchwork.freedesktop.org/series/77969/ State : failure == Summary == Applying: drm/i915/dp_mst: Fix disabling MST on a port error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_dp.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915/dp_mst: Fix disabling MST on a port When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From imre.deak at intel.com Fri Jun 5 09:48:01 2020 From: imre.deak at intel.com (Imre Deak) Date: Fri, 5 Jun 2020 12:48:01 +0300 Subject: [Intel-gfx] [PATCH RESEND v3 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <20200604184500.23730-1-imre.deak@intel.com> References: <20200604184500.23730-1-imre.deak@intel.com> Message-ID: <20200605094801.17709-1-imre.deak@intel.com> Currently MST on a port can get enabled/disabled from the hotplug work and get disabled from the short pulse work in a racy way. Fix this by relying on the MST state checking in the hotplug work and just schedule a hotplug work from the short pulse handler if some problem happened during the MST interrupt handling. This removes the explicit MST disabling in case of an AUX failure, but if AUX fails, then probably the detection will also fail during the scheduled hotplug work and it's not guaranteed that we'll see intermittent errors anyway. While at it also simplify the error checking of the MST interrupt handler. v2: - Convert intel_dp_check_mst_status() to return bool. (Ville) - Change the intel_dp->is_mst check to an assert, since after this patch the condition can't change after we checked it previously. - Document the return value from intel_dp_check_mst_status(). v3: - Remove the intel_dp->is_mst check from intel_dp_check_mst_status(). There is no point in checking the same condition twice, even though there is a chance that the hotplug work running concurrently changes it. Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> (v1) Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++--------------- 1 file changed, 26 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 55fda074c0ad..42589cae766d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5556,35 +5556,46 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) "Could not write test response to sink\n"); } -static int +/** + * intel_dp_check_mst_status - service any pending MST interrupts, check link status + * @intel_dp: Intel DP struct + * + * Read any pending MST interrupts, call MST core to handle these and ack the + * interrupts. Check if the main and AUX link state is ok. + * + * Returns: + * - %true if pending interrupts were serviced (or no interrupts were + * pending) w/o detecting an error condition. + * - %false if an error condition - like AUX failure or a loss of link - is + * detected, which needs servicing from the hotplug work. + */ +static bool intel_dp_check_mst_status(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - bool need_retrain = false; - - if (!intel_dp->is_mst) - return -EINVAL; + bool link_ok = true; drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); for (;;) { u8 esi[DP_DPRX_ESI_LEN] = {}; - bool bret, handled; + bool handled; int retry; - bret = intel_dp_get_sink_irq_esi(intel_dp, esi); - if (!bret) { + if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { drm_dbg_kms(&i915->drm, "failed to get ESI - device may have failed\n"); - return -EINVAL; + link_ok = false; + + break; } /* check link status - esi[10] = 0x200c */ - if (intel_dp->active_mst_links > 0 && !need_retrain && + if (intel_dp->active_mst_links > 0 && link_ok && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { drm_dbg_kms(&i915->drm, "channel EQ not ok, retraining\n"); - need_retrain = true; + link_ok = false; } drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); @@ -5604,7 +5615,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) } } - return need_retrain; + return link_ok; } static bool @@ -7255,35 +7266,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) } if (intel_dp->is_mst) { - switch (intel_dp_check_mst_status(intel_dp)) { - case -EINVAL: - /* - * If we were in MST mode, and device is not - * there, get out of MST mode - */ - drm_dbg_kms(&i915->drm, - "MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, - intel_dp->mst_mgr.mst_state); - intel_dp->is_mst = false; - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, - intel_dp->is_mst); - - return IRQ_NONE; - case 1: - return IRQ_NONE; - default: - break; - } - } - - if (!intel_dp->is_mst) { - bool handled; - - handled = intel_dp_short_pulse(intel_dp); - - if (!handled) + if (!intel_dp_check_mst_status(intel_dp)) return IRQ_NONE; + } else if (!intel_dp_short_pulse(intel_dp)) { + return IRQ_NONE; } return IRQ_HANDLED; -- 2.23.1 From chris at chris-wilson.co.uk Fri Jun 5 09:58:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 10:58:54 +0100 Subject: [Intel-gfx] [PATCH 1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse Message-ID: <20200605095858.28455-1-chris@chris-wilson.co.uk> One more list iterator variant, for when we want to unwind from inside one list iterator with the intention of restarting from the current entry as the new head of the list. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_utils.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h index 03a73d2bd50d..6ebccdd12d4c 100644 --- a/drivers/gpu/drm/i915/i915_utils.h +++ b/drivers/gpu/drm/i915/i915_utils.h @@ -266,6 +266,12 @@ static inline int list_is_last_rcu(const struct list_head *list, return READ_ONCE(list->next) == head; } +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) + /* * Wait until the work is finally complete, even if it tries to postpone * by requeueing itself. Note, that if the worker never cancels itself, -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 09:58:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 10:58:55 +0100 Subject: [Intel-gfx] [PATCH 2/5] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <20200605095858.28455-2-chris@chris-wilson.co.uk> Over the next couple of patches, we will want to lock all the modified vma for relocation processing under a single ww_mutex. We neither want to have to include the vma that are skipped (due to no modifications required) nor do we want those to be marked as written too. So separate out the reloc validation into an early step, which we can use both to reject the execbuf before committing to making our changes, and to filter out the unmodified vma. This does introduce a second pass through the reloc[], but only if we need to emit relocations. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 178 +++++++++++++----- 1 file changed, 133 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index cfe6d2cdbef1..7d4464fddca8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1331,6 +1331,117 @@ static u64 eb_relocate_entry(struct i915_execbuffer *eb, struct eb_vma *ev, const struct drm_i915_gem_relocation_entry *reloc) +{ + struct eb_vma *target; + + /* we've already hold a reference to all valid objects */ + target = eb_get_vma(eb, reloc->target_handle); + if (unlikely(!target)) + return -ENOENT; + + /* + * If the relocation already has the right value in it, no + * more work needs to be done. + */ + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) + return 0; + + /* + * If we write into the object, we need to force the synchronisation + * barrier, either with an asynchronous clflush or if we executed the + * patching using the GPU (though that should be serialised by the + * timeline). To be completely sure, and since we are required to + * do relocations we are already stalling, disable the user's opt + * out of our synchronisation. + */ + ev->flags &= ~EXEC_OBJECT_ASYNC; + + /* and update the user's relocation entry */ + return relocate_entry(eb, ev->vma, reloc, target->vma); +} + +static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +{ +#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) + struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; + const struct drm_i915_gem_exec_object2 *entry = ev->exec; + struct drm_i915_gem_relocation_entry __user *urelocs = + u64_to_user_ptr(entry->relocs_ptr); + unsigned long remain = entry->relocation_count; + + if (unlikely(remain > N_RELOC(ULONG_MAX))) + return -EINVAL; + + /* + * We must check that the entire relocation array is safe + * to read. However, if the array is not writable the user loses + * the updated relocation values. + */ + if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs)))) + return -EFAULT; + + do { + struct drm_i915_gem_relocation_entry *r = stack; + unsigned int count = + min_t(unsigned long, remain, ARRAY_SIZE(stack)); + unsigned int copied; + + /* + * This is the fast path and we cannot handle a pagefault + * whilst holding the struct mutex lest the user pass in the + * relocations contained within a mmaped bo. For in such a case + * we, the page fault handler would call i915_gem_fault() and + * we would try to acquire the struct mutex again. Obviously + * this is bad and so lockdep complains vehemently. + */ + copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); + if (unlikely(copied)) + return -EFAULT; + + remain -= count; + do { + u64 offset = eb_relocate_entry(eb, ev, r); + + if (likely(offset == 0)) { + } else if ((s64)offset < 0) { + return (int)offset; + } else { + /* + * Note that reporting an error now + * leaves everything in an inconsistent + * state as we have *already* changed + * the relocation value inside the + * object. As we have not changed the + * reloc.presumed_offset or will not + * change the execobject.offset, on the + * call we may not rewrite the value + * inside the object, leaving it + * dangling and causing a GPU hang. Unless + * userspace dynamically rebuilds the + * relocations on each execbuf rather than + * presume a static tree. + * + * We did previously check if the relocations + * were writable (access_ok), an error now + * would be a strange race with mprotect, + * having already demonstrated that we + * can read from this userspace address. + */ + offset = gen8_canonical_addr(offset & ~UPDATE); + __put_user(offset, + &urelocs[r - stack].presumed_offset); + } + } while (r++, --count); + urelocs += ARRAY_SIZE(stack); + } while (remain); + + return 0; +} + +static int +eb_reloc_valid(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc) { struct drm_i915_private *i915 = eb->i915; struct eb_vma *target; @@ -1408,21 +1519,10 @@ eb_relocate_entry(struct i915_execbuffer *eb, return -EINVAL; } - /* - * If we write into the object, we need to force the synchronisation - * barrier, either with an asynchronous clflush or if we executed the - * patching using the GPU (though that should be serialised by the - * timeline). To be completely sure, and since we are required to - * do relocations we are already stalling, disable the user's opt - * out of our synchronisation. - */ - ev->flags &= ~EXEC_OBJECT_ASYNC; - - /* and update the user's relocation entry */ - return relocate_entry(eb, ev->vma, reloc, target->vma); + return 1; } -static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) { #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; @@ -1430,6 +1530,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) struct drm_i915_gem_relocation_entry __user *urelocs = u64_to_user_ptr(entry->relocs_ptr); unsigned long remain = entry->relocation_count; + long required = 0; if (unlikely(remain > N_RELOC(ULONG_MAX))) return -EINVAL; @@ -1462,42 +1563,18 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) remain -= count; do { - u64 offset = eb_relocate_entry(eb, ev, r); + int ret; - if (likely(offset == 0)) { - } else if ((s64)offset < 0) { - return (int)offset; - } else { - /* - * Note that reporting an error now - * leaves everything in an inconsistent - * state as we have *already* changed - * the relocation value inside the - * object. As we have not changed the - * reloc.presumed_offset or will not - * change the execobject.offset, on the - * call we may not rewrite the value - * inside the object, leaving it - * dangling and causing a GPU hang. Unless - * userspace dynamically rebuilds the - * relocations on each execbuf rather than - * presume a static tree. - * - * We did previously check if the relocations - * were writable (access_ok), an error now - * would be a strange race with mprotect, - * having already demonstrated that we - * can read from this userspace address. - */ - offset = gen8_canonical_addr(offset & ~UPDATE); - __put_user(offset, - &urelocs[r - stack].presumed_offset); - } + ret = eb_reloc_valid(eb, ev, r); + if (ret < 0) + return ret; + + required += ret; } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); - return 0; + return required; } static int eb_relocate(struct i915_execbuffer *eb) @@ -1516,9 +1593,20 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { - struct eb_vma *ev; + struct eb_vma *ev, *en; int flush; + list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { + long count; + + count = eb_reloc_vma_validate(eb, ev); + if (count < 0) + return count; + + if (count == 0) + list_del_init(&ev->reloc_link); + } + list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 09:58:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 10:58:58 +0100 Subject: [Intel-gfx] [PATCH 5/5] drm/i915/gem: Add all GPU reloc awaits/signals en masse In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <20200605095858.28455-5-chris@chris-wilson.co.uk> Asynchronous waits and signaling form a traditional semaphore with all the usual ordering problems with taking multiple locks. If we want to add more than one wait on a shared resource by the GPU, we must ensure that all the associated timelines are advanced atomically, ergo we must lock all the timelines en masse. Testcase: igt/gem_exec_reloc/basic-concurrent16 Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") References: https://gitlab.freedesktop.org/drm/intel/-/issues/1889 Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 114 ++++++++++++------ .../i915/gem/selftests/i915_gem_execbuffer.c | 24 ++-- 2 files changed, 93 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 489960ebe608..76dc5d1c27e9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -259,7 +259,6 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; - struct i915_vma *target; struct i915_request *rq; struct i915_vma *rq_vma; u32 *rq_cmd; @@ -924,7 +923,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->target = NULL; } static inline void *unmask_page(unsigned long p) @@ -1057,26 +1055,6 @@ static void reloc_gpu_flush(struct reloc_cache *cache) i915_request_add(rq); } -static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) -{ - struct drm_i915_gem_object *obj = vma->obj; - int err; - - i915_vma_lock(vma); - - if (obj->cache_dirty & ~obj->cache_coherent) - i915_gem_clflush_object(obj, 0); - obj->write_domain = 0; - - err = i915_request_await_object(rq, vma->obj, true); - if (err == 0) - err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - - i915_vma_unlock(vma); - - return err; -} - static int __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { @@ -1166,24 +1144,12 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) return err; } -static u32 *reloc_batch_grow(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (vma != cache->target) { - err = reloc_move_to_gpu(cache->rq, vma); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); - return ERR_PTR(err); - } - - cache->target = vma; - } - if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); @@ -1229,7 +1195,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_batch_grow(eb, vma, len); + batch = reloc_batch_grow(eb, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1549,6 +1515,78 @@ static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) return required; } +static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) +{ + struct i915_request *rq = cache->rq; + struct i915_vma *vma = ev->vma; + struct drm_i915_gem_object *obj = vma->obj; + int err; + + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, 0); + + obj->write_domain = I915_GEM_DOMAIN_RENDER; + obj->read_domains = I915_GEM_DOMAIN_RENDER; + + err = i915_request_await_object(rq, obj, true); + if (err) + return err; + + err = __i915_vma_move_to_active(vma, rq); + if (err) + return err; + + dma_resv_add_excl_fence(vma->resv, &rq->fence); + + return 0; +} + +static int +lock_relocs(struct i915_execbuffer *eb) +{ + struct ww_acquire_ctx acquire; + struct eb_vma *ev; + int err = 0; + + ww_acquire_init(&acquire, &reservation_ww_class); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + struct i915_vma *vma = ev->vma; + + err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); + if (err == -EDEADLK) { + struct eb_vma *unlock = ev, *en; + + list_for_each_entry_safe_continue_reverse(unlock, en, + &eb->relocs, + reloc_link) { + ww_mutex_unlock(&unlock->vma->resv->lock); + list_move_tail(&unlock->reloc_link, + &eb->relocs); + } + + GEM_BUG_ON(!list_is_first(&ev->reloc_link, + &eb->relocs)); + err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, + &acquire); + } + if (err) + break; + } + + ww_acquire_done(&acquire); + + list_for_each_entry_continue_reverse(ev, &eb->relocs, reloc_link) { + if (err == 0) + err = reloc_move_to_gpu(&eb->reloc_cache, ev); + ww_mutex_unlock(&ev->vma->resv->lock); + } + + ww_acquire_fini(&acquire); + + return err; +} + static bool reloc_can_use_engine(const struct intel_engine_cs *engine) { return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); @@ -1577,6 +1615,10 @@ static int reloc_gpu(struct i915_execbuffer *eb) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = lock_relocs(eb); + if (err) + goto out; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index faed6480a792..4f10b51f9a7e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -24,15 +24,15 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GENMASK_ULL(eb->reloc_cache.use_64bit_reloc ? 63 : 31, 0); const u32 *map = page_mask_bits(obj->mm.mapping); struct i915_request *rq; - struct i915_vma *vma; + struct eb_vma ev; int err; int i; - vma = i915_vma_instance(obj, eb->context->vm, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + ev.vma = i915_vma_instance(obj, eb->context->vm, NULL); + if (IS_ERR(ev.vma)) + return PTR_ERR(ev.vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + err = i915_vma_pin(ev.vma, 0, 0, PIN_USER | PIN_HIGH); if (err) return err; @@ -40,17 +40,22 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + list_add(&ev.reloc_link, &eb->relocs); + err = lock_relocs(eb); + if (err) + goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto unpin_vma; /* 8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + err = __reloc_entry_gpu(eb, ev.vma, offsets[0] * sizeof(u32), 0); if (err) goto unpin_vma; /* !8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + err = __reloc_entry_gpu(eb, ev.vma, offsets[1] * sizeof(u32), 1); if (err) goto unpin_vma; @@ -62,7 +67,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + err = __reloc_entry_gpu(eb, ev.vma, offsets[2] * sizeof(u32), 2); if (err) goto unpin_vma; @@ -97,7 +102,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, put_rq: i915_request_put(rq); unpin_vma: - i915_vma_unpin(vma); + i915_vma_unpin(ev.vma); return err; } @@ -121,6 +126,7 @@ static int igt_gpu_reloc(void *arg) } for_each_uabi_engine(eb.engine, eb.i915) { + INIT_LIST_HEAD(&eb.relocs); reloc_cache_init(&eb.reloc_cache, eb.i915); memset(map, POISON_INUSE, 4096); -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 09:58:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 10:58:56 +0100 Subject: [Intel-gfx] [PATCH 3/5] drm/i915/gem: Lift GPU relocation allocation In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <20200605095858.28455-3-chris@chris-wilson.co.uk> Since we have reduced the relocations paths to just use the async GPU, we can lift the request allocation to the start of the relocations. Knowing that we use one request for all relocations will simplify tracking the relocation fence. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 98 ++++++++++--------- .../i915/gem/selftests/i915_gem_execbuffer.c | 5 +- 2 files changed, 56 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 7d4464fddca8..59e1856c99fc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -900,8 +900,6 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) static void eb_destroy(const struct i915_execbuffer *eb) { - GEM_BUG_ON(eb->reloc_cache.rq); - if (eb->array) eb_vma_array_put(eb->array); @@ -926,7 +924,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->rq = NULL; cache->target = NULL; } @@ -1026,13 +1023,9 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) static int reloc_gpu_flush(struct reloc_cache *cache) { - struct i915_request *rq; + struct i915_request *rq = cache->rq; int err; - rq = fetch_and_zero(&cache->rq); - if (!rq) - return 0; - if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1081,9 +1074,8 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) return err; } -static int __reloc_gpu_alloc(struct i915_execbuffer *eb, - struct intel_engine_cs *engine, - unsigned int len) +static int +__reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { struct reloc_cache *cache = &eb->reloc_cache; struct intel_gt_buffer_pool_node *pool; @@ -1173,33 +1165,14 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, return err; } -static bool reloc_can_use_engine(const struct intel_engine_cs *engine) -{ - return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); -} - -static u32 *reloc_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, + struct i915_vma *vma, + unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (unlikely(!cache->rq)) { - struct intel_engine_cs *engine = eb->engine; - - if (!reloc_can_use_engine(engine)) { - engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; - if (!engine) - return ERR_PTR(-ENODEV); - } - - err = __reloc_gpu_alloc(eb, engine, len); - if (unlikely(err)) - return ERR_PTR(err); - } - if (vma != cache->target) { err = reloc_move_to_gpu(cache->rq, vma); if (unlikely(err)) { @@ -1257,7 +1230,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_gpu(eb, vma, len); + batch = reloc_batch_grow(eb, vma, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1577,6 +1550,47 @@ static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) return required; } +static bool reloc_can_use_engine(const struct intel_engine_cs *engine) +{ + return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); +} + +static int reloc_gpu_alloc(struct i915_execbuffer *eb) +{ + struct intel_engine_cs *engine = eb->engine; + + if (!reloc_can_use_engine(engine)) { + engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; + if (!engine) + return -ENODEV; + } + + return __reloc_gpu_alloc(eb, engine); +} + +static int reloc_gpu(struct i915_execbuffer *eb) +{ + struct eb_vma *ev; + int flush, err; + + err = reloc_gpu_alloc(eb); + if (err) + return err; + GEM_BUG_ON(!eb->reloc_cache.rq); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + err = eb_relocate_vma(eb, ev); + if (err) + goto out; + } + +out: + flush = reloc_gpu_flush(&eb->reloc_cache); + if (!err) + err = flush; + return err; +} + static int eb_relocate(struct i915_execbuffer *eb) { int err; @@ -1594,7 +1608,6 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { struct eb_vma *ev, *en; - int flush; list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { long count; @@ -1607,18 +1620,14 @@ static int eb_relocate(struct i915_execbuffer *eb) list_del_init(&ev->reloc_link); } - list_for_each_entry(ev, &eb->relocs, reloc_link) { - err = eb_relocate_vma(eb, ev); + if (!list_empty(&eb->relocs)) { + err = reloc_gpu(eb); if (err) - break; + return err; } - - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; } - return err; + return 0; } static int eb_move_to_gpu(struct i915_execbuffer *eb) @@ -2618,9 +2627,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, batch = vma; } - /* All GPU relocation batches must be submitted prior to the user rq */ - GEM_BUG_ON(eb.reloc_cache.rq); - /* Allocate a request for this batch buffer nice and early. */ eb.request = i915_request_create(eb.context); if (IS_ERR(eb.request)) { diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 57c14d3340cd..50fe22d87ae1 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -36,6 +36,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) return err; + err = reloc_gpu_alloc(eb); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -63,7 +67,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, err = reloc_gpu_flush(&eb->reloc_cache); if (err) goto put_rq; - GEM_BUG_ON(eb->reloc_cache.rq); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 09:58:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 10:58:57 +0100 Subject: [Intel-gfx] [PATCH 4/5] drm/i915/gem: Build the reloc request first In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <20200605095858.28455-4-chris@chris-wilson.co.uk> If we get interrupted in the middle of chaining up the relocation entries, we will fail to submit the relocation batch. However, we will report having already completed some of the relocations, and so the reloc.presumed_offset will no longer match the batch contents, causing confusion and invalid future batches. If we build the relocation request packet first, we can always emit as far as we get up in the relocation chain. Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 51 ++++++++++--------- .../i915/gem/selftests/i915_gem_execbuffer.c | 8 +-- 2 files changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 59e1856c99fc..489960ebe608 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1021,11 +1021,27 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) return cache->gen > 5 ? 0 : I915_DISPATCH_SECURE; } -static int reloc_gpu_flush(struct reloc_cache *cache) +static int reloc_gpu_emit(struct reloc_cache *cache) { struct i915_request *rq = cache->rq; int err; + err = 0; + if (rq->engine->emit_init_breadcrumb) + err = rq->engine->emit_init_breadcrumb(rq); + if (!err) + err = rq->engine->emit_bb_start(rq, + rq->batch->node.start, + PAGE_SIZE, + reloc_bb_flags(cache)); + + return err; +} + +static void reloc_gpu_flush(struct reloc_cache *cache) +{ + struct i915_request *rq = cache->rq; + if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1037,21 +1053,8 @@ static int reloc_gpu_flush(struct reloc_cache *cache) i915_gem_object_unpin_map(obj); } - err = 0; - if (rq->engine->emit_init_breadcrumb) - err = rq->engine->emit_init_breadcrumb(rq); - if (!err) - err = rq->engine->emit_bb_start(rq, - rq->batch->node.start, - PAGE_SIZE, - reloc_bb_flags(cache)); - if (err) - i915_request_set_error_once(rq, err); - intel_gt_chipset_flush(rq->engine->gt); i915_request_add(rq); - - return err; } static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) @@ -1139,7 +1142,7 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) err = i915_vma_move_to_active(batch, rq, 0); i915_vma_unlock(batch); if (err) - goto skip_request; + goto err_request; rq->batch = batch; i915_vma_unpin(batch); @@ -1152,8 +1155,6 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) /* Return with batch mapping (cmd) still pinned */ goto out_pool; -skip_request: - i915_request_set_error_once(rq, err); err_request: i915_request_add(rq); err_unpin: @@ -1186,10 +1187,8 @@ static u32 *reloc_batch_grow(struct i915_execbuffer *eb, if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); + if (unlikely(err)) return ERR_PTR(err); - } } GEM_BUG_ON(cache->rq_size + len >= PAGE_SIZE / sizeof(u32)); @@ -1571,23 +1570,25 @@ static int reloc_gpu_alloc(struct i915_execbuffer *eb) static int reloc_gpu(struct i915_execbuffer *eb) { struct eb_vma *ev; - int flush, err; + int err; err = reloc_gpu_alloc(eb); if (err) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto out; + list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) - goto out; + break; } out: - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; + reloc_gpu_flush(&eb->reloc_cache); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 50fe22d87ae1..faed6480a792 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -40,6 +40,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -64,9 +68,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); - err = reloc_gpu_flush(&eb->reloc_cache); - if (err) - goto put_rq; + reloc_gpu_flush(&eb->reloc_cache); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 5 10:24:03 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 10:24:03 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BRESEND=2Cv3=2C1/3=5D_drm/i915/dp=5Fmst=3A_?= =?utf-8?q?Fix_disabling_MST_on_a_port_=28rev6=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159135264343.18506.3824081121476583172@emeril.freedesktop.org> == Series Details == Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6) URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17882 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/index.html Known issues ------------ Here are the changes found in Patchwork_17882 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at active: - fi-whl-u: [DMESG-FAIL][9] ([i915#666]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_selftest@live at active.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-whl-u/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17882 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17882: 23fe5e3ae83585e3d4ad9ecdfea368dd42ff6dfb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 23fe5e3ae835 drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses ceb861eabe52 drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() ba27048a7abb drm/i915/dp_mst: Fix disabling MST on a port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 10:30:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 10:30:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/5=5D_drm/i915=3A_Add_list=5Ffor?= =?utf-8?q?=5Feach=5Fentry=5Fsafe=5Fcontinue=5Freverse?= In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <159135304276.18509.15269286085694950595@emeril.freedesktop.org> == Series Details == Series: series starting with [1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse URL : https://patchwork.freedesktop.org/series/78031/ State : warning == Summary == $ dim checkpatch origin/drm-tip e7d5754aeb38 drm/i915: Add list_for_each_entry_safe_continue_reverse -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible side-effects? #20: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) total: 0 errors, 0 warnings, 3 checks, 12 lines checked cc00968a346f drm/i915/gem: Separate reloc validation into an earlier step -:101: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return #101: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1408: + return (int)offset; + } else { total: 0 errors, 1 warnings, 0 checks, 217 lines checked b7fc02099400 drm/i915/gem: Lift GPU relocation allocation 43567189b2df drm/i915/gem: Build the reloc request first 00beaabc4fe0 drm/i915/gem: Add all GPU reloc awaits/signals en masse From patchwork at emeril.freedesktop.org Fri Jun 5 10:31:54 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 10:31:54 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/5=5D_drm/i915=3A_Add_list=5Ffor=5Feac?= =?utf-8?q?h=5Fentry=5Fsafe=5Fcontinue=5Freverse?= In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <159135311405.18506.695072761789910896@emeril.freedesktop.org> == Series Details == Series: series starting with [1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse URL : https://patchwork.freedesktop.org/series/78031/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Fri Jun 5 10:52:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 10:52:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/5=5D_drm/i915=3A_Add_list=5Ffor=5Feach?= =?utf-8?q?=5Fentry=5Fsafe=5Fcontinue=5Freverse?= In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <159135434320.18506.18282848617230703970@emeril.freedesktop.org> == Series Details == Series: series starting with [1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse URL : https://patchwork.freedesktop.org/series/78031/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17883 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/index.html Known issues ------------ Here are the changes found in Patchwork_17883 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-byt-n2820/igt at i915_module_load@reload.html - fi-tgl-y: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-tgl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at active: - fi-whl-u: [DMESG-FAIL][11] ([i915#666]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_selftest@live at active.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-whl-u/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1}: - fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17883 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17883: 00beaabc4fe051ae2d54aeba089389d20131e280 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 00beaabc4fe0 drm/i915/gem: Add all GPU reloc awaits/signals en masse 43567189b2df drm/i915/gem: Build the reloc request first b7fc02099400 drm/i915/gem: Lift GPU relocation allocation cc00968a346f drm/i915/gem: Separate reloc validation into an earlier step e7d5754aeb38 drm/i915: Add list_for_each_entry_safe_continue_reverse == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/index.html From chris at chris-wilson.co.uk Fri Jun 5 10:56:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 11:56:45 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Discard a misplaced GGTT vma Message-ID: <20200605105646.24300-1-chris@chris-wilson.co.uk> Across the many users of the GGTT vma (internal objects, mmapings, display etc), we may end up with conflicting requirements for the placement. Currently, we try to resolve the conflict by unbinding the vma and rebinding it to match the new constraints; over time we will end up with a GGTT that matches the most strict constraints over all concurrent users. However, this causes a problem if the vma is currently in use as we must wait until it is idle before moving it. But there is no restriction on the number of views we may use (apart from the limited size of the GGTT itself), and so if the active vma does not meet our requirements, try and build a new one! Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem.c | 44 +++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0cbcb9f54e7d..29a4594ddef2 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -933,6 +933,44 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915) } } +static bool +discard_ggtt_vma(struct i915_vma *vma, const struct i915_ggtt_view *view) +{ + const struct i915_ggtt_view discard = { + .type = I915_GGTT_VIEW_PARTIAL, + }; + struct drm_i915_gem_object *obj = vma->obj; + + spin_lock(&obj->vma.lock); + if (i915_vma_compare(vma, vma->vm, &discard)) { + struct rb_node *rb, **p; + + rb_erase(&vma->obj_node, &obj->vma.tree); + vma->ggtt_view = discard; + + rb = NULL; + p = &obj->vma.tree.rb_node; + while (*p) { + struct i915_vma *pos; + long cmp; + + rb = *p; + pos = rb_entry(rb, struct i915_vma, obj_node); + + cmp = i915_vma_compare(pos, vma->vm, &discard); + if (cmp < 0) + p = &rb->rb_right; + else + p = &rb->rb_left; + } + rb_link_node(&vma->obj_node, rb, p); + rb_insert_color(&vma->obj_node, &obj->vma.tree); + } + spin_unlock(&obj->vma.lock); + + return i915_vma_compare(vma, vma->vm, view); +} + struct i915_vma * i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, @@ -979,6 +1017,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return ERR_PTR(-ENOSPC); } +new_vma: vma = i915_vma_instance(obj, &ggtt->vm, view); if (IS_ERR(vma)) return vma; @@ -993,6 +1032,11 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return ERR_PTR(-ENOSPC); } + if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) { + if (discard_ggtt_vma(vma, view)) + goto new_vma; + } + ret = i915_vma_unbind(vma); if (ret) return ERR_PTR(ret); -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 10:56:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 11:56:46 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Avoid kmalloc under i915->mm_lock In-Reply-To: <20200605105646.24300-1-chris@chris-wilson.co.uk> References: <20200605105646.24300-1-chris@chris-wilson.co.uk> Message-ID: <20200605105646.24300-2-chris@chris-wilson.co.uk> Rearrange the allocation of the mm_struct registration to avoid allocating underneath the i915->mm_lock, so that we avoid tainting the lock (and in turn many other locks that may be held as i915->mm_lock is taken, and those locks we may want on the free [shrinker] paths). In doing so, we convert the lookup to be RCU protected by courtesy of converting the free-worker to be an rcu_work. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 123 +++++++++----------- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 59 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index 2adc0ea429fb..3dd2bbb37577 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -21,7 +21,7 @@ struct i915_mm_struct { struct i915_mmu_notifier *mn; struct hlist_node node; struct kref kref; - struct work_struct work; + struct rcu_work work; }; #if defined(CONFIG_MMU_NOTIFIER) @@ -189,40 +189,31 @@ i915_gem_userptr_release__mmu_notifier(struct drm_i915_gem_object *obj) static struct i915_mmu_notifier * i915_mmu_notifier_find(struct i915_mm_struct *mm) { - struct i915_mmu_notifier *mn; - int err = 0; + struct i915_mmu_notifier *mn, *old; + int err; - mn = mm->mn; - if (mn) + mn = READ_ONCE(mm->mn); + if (likely(mn)) return mn; mn = i915_mmu_notifier_create(mm); if (IS_ERR(mn)) - err = PTR_ERR(mn); - - down_write(&mm->mm->mmap_sem); - mutex_lock(&mm->i915->mm_lock); - if (mm->mn == NULL && !err) { - /* Protected by mmap_sem (write-lock) */ - err = __mmu_notifier_register(&mn->mn, mm->mm); - if (!err) { - /* Protected by mm_lock */ - mm->mn = fetch_and_zero(&mn); - } - } else if (mm->mn) { - /* - * Someone else raced and successfully installed the mmu - * notifier, we can cancel our own errors. - */ - err = 0; + return mn; + + err = mmu_notifier_register(&mn->mn, mm->mm); + if (err) { + kfree(mn); + return ERR_PTR(err); } - mutex_unlock(&mm->i915->mm_lock); - up_write(&mm->mm->mmap_sem); - if (mn && !IS_ERR(mn)) + old = cmpxchg(&mm->mn, NULL, mn); + if (old) { + mmu_notifier_unregister(&mn->mn, mm->mm); kfree(mn); + mn = old; + } - return err ? ERR_PTR(err) : mm->mn; + return mn; } static int @@ -301,23 +292,26 @@ i915_mmu_notifier_free(struct i915_mmu_notifier *mn, #endif static struct i915_mm_struct * -__i915_mm_struct_find(struct drm_i915_private *dev_priv, struct mm_struct *real) +__i915_mm_struct_find(struct drm_i915_private *i915, struct mm_struct *real) { - struct i915_mm_struct *mm; + struct i915_mm_struct *it, *mm = NULL; - /* Protected by dev_priv->mm_lock */ - hash_for_each_possible(dev_priv->mm_structs, mm, node, (unsigned long)real) - if (mm->mm == real) - return mm; + rcu_read_lock(); + hash_for_each_possible(i915->mm_structs, it, node, (unsigned long)real) + if (it->mm == real && kref_get_unless_zero(&it->kref)) { + mm = it; + break; + } + rcu_read_unlock(); - return NULL; + return mm; } static int i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) { - struct drm_i915_private *dev_priv = to_i915(obj->base.dev); - struct i915_mm_struct *mm; + struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_mm_struct *mm, *new; int ret = 0; /* During release of the GEM object we hold the struct_mutex. This @@ -330,39 +324,40 @@ i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) * struct_mutex, i.e. we need to schedule a worker to do the clean * up. */ - mutex_lock(&dev_priv->mm_lock); - mm = __i915_mm_struct_find(dev_priv, current->mm); - if (mm == NULL) { - mm = kmalloc(sizeof(*mm), GFP_KERNEL); - if (mm == NULL) { - ret = -ENOMEM; - goto out; - } + mm = __i915_mm_struct_find(i915, current->mm); + if (mm) + goto out; - kref_init(&mm->kref); - mm->i915 = to_i915(obj->base.dev); - - mm->mm = current->mm; - mmgrab(current->mm); + new = kmalloc(sizeof(*mm), GFP_KERNEL); + if (new == NULL) + return -ENOMEM; - mm->mn = NULL; + kref_init(&new->kref); + new->i915 = to_i915(obj->base.dev); + new->mm = current->mm; + new->mn = NULL; - /* Protected by dev_priv->mm_lock */ - hash_add(dev_priv->mm_structs, - &mm->node, (unsigned long)mm->mm); - } else - kref_get(&mm->kref); + spin_lock(&i915->mm_lock); + mm = __i915_mm_struct_find(i915, current->mm); + if (!mm) { + hash_add(i915->mm_structs, &new->node, (unsigned long)new->mm); + mmgrab(current->mm); + mm = new; + } + spin_unlock(&i915->mm_lock); + if (mm != new) + kfree(new); - obj->userptr.mm = mm; out: - mutex_unlock(&dev_priv->mm_lock); + obj->userptr.mm = mm; return ret; } static void __i915_mm_struct_free__worker(struct work_struct *work) { - struct i915_mm_struct *mm = container_of(work, typeof(*mm), work); + struct i915_mm_struct *mm = container_of(work, typeof(*mm), work.work); + i915_mmu_notifier_free(mm->mn, mm->mm); mmdrop(mm->mm); kfree(mm); @@ -373,12 +368,12 @@ __i915_mm_struct_free(struct kref *kref) { struct i915_mm_struct *mm = container_of(kref, typeof(*mm), kref); - /* Protected by dev_priv->mm_lock */ + spin_lock(&mm->i915->mm_lock); hash_del(&mm->node); - mutex_unlock(&mm->i915->mm_lock); + spin_unlock(&mm->i915->mm_lock); - INIT_WORK(&mm->work, __i915_mm_struct_free__worker); - queue_work(mm->i915->mm.userptr_wq, &mm->work); + INIT_RCU_WORK(&mm->work, __i915_mm_struct_free__worker); + queue_rcu_work(mm->i915->mm.userptr_wq, &mm->work); } static void @@ -387,9 +382,7 @@ i915_gem_userptr_release__mm_struct(struct drm_i915_gem_object *obj) if (obj->userptr.mm == NULL) return; - kref_put_mutex(&obj->userptr.mm->kref, - __i915_mm_struct_free, - &to_i915(obj->base.dev)->mm_lock); + kref_put(&obj->userptr.mm->kref, __i915_mm_struct_free); obj->userptr.mm = NULL; } @@ -839,7 +832,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, int i915_gem_init_userptr(struct drm_i915_private *dev_priv) { - mutex_init(&dev_priv->mm_lock); + spin_lock_init(&dev_priv->mm_lock); hash_init(dev_priv->mm_structs); dev_priv->mm.userptr_wq = diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..7464656253c9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -988,7 +988,7 @@ struct drm_i915_private { struct i915_gem_mm mm; DECLARE_HASHTABLE(mm_structs, 7); - struct mutex mm_lock; + spinlock_t mm_lock; /* Kernel Modesetting */ -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 5 11:21:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 11:21:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/2=5D_drm/i915=3A_Discard_a_mispla?= =?utf-8?q?ced_GGTT_vma?= In-Reply-To: <20200605105646.24300-1-chris@chris-wilson.co.uk> References: <20200605105646.24300-1-chris@chris-wilson.co.uk> Message-ID: <159135611814.18506.4833058667327118028@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Discard a misplaced GGTT vma URL : https://patchwork.freedesktop.org/series/78033/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5de23154206a drm/i915: Discard a misplaced GGTT vma 8f309332415b drm/i915/gem: Avoid kmalloc under i915->mm_lock -:143: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!new" #143: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:332: + if (new == NULL) -:230: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #230: FILE: drivers/gpu/drm/i915/i915_drv.h:991: + spinlock_t mm_lock; total: 0 errors, 0 warnings, 2 checks, 203 lines checked From patchwork at emeril.freedesktop.org Fri Jun 5 11:26:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 11:26:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BRESEND=2Cv3=2C1/3=5D_drm/i915/dp=5Fmst=3A_?= =?utf-8?q?Fix_disabling_MST_on_a_port_=28rev6=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159135637372.18508.17555303407147804828@emeril.freedesktop.org> == Series Details == Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6) URL : https://patchwork.freedesktop.org/series/77969/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17882_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17882_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17882_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17882_full: ### IGT changes ### #### Possible regressions #### * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html #### Warnings #### * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [SKIP][3] ([fdo#109271]) -> [TIMEOUT][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [FAIL][5] ([i915#1930]) -> [TIMEOUT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html * {igt at kms_chamelium@vga-hpd-enable-disable-mode}: - shard-snb: [SKIP][7] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_chamelium@vga-hpd-enable-disable-mode.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_chamelium@vga-hpd-enable-disable-mode.html Known issues ------------ Here are the changes found in Patchwork_17882_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk7/igt at gem_exec_whisper@basic-forked-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk2/igt at gem_exec_whisper@basic-forked-all.html * igt at gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at gem_mmap_gtt@cpuset-big-copy-odd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at gem_mmap_gtt@cpuset-big-copy-odd.html * igt at gem_workarounds@suspend-resume: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_workarounds@suspend-resume.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_workarounds@suspend-resume.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +9 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_big_fb@linear-32bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / [i915#95]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk4/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +17 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#49]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_lowres@pipe-a-tiling-x: - shard-snb: [PASS][31] -> [SKIP][32] ([fdo#109271]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at kms_plane_lowres@pipe-a-tiling-x.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_lowres@pipe-a-tiling-x.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +3 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb4/igt at kms_psr@psr2_cursor_blt.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#402]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][43] ([i915#1436] / [i915#716]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at gen9_exec_parse@allowed-all.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [INCOMPLETE][45] ([i915#155]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl6/igt at i915_suspend@debugfs-reader.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_color@pipe-d-ctm-0-5: - shard-tglb: [DMESG-WARN][49] ([i915#1149] / [i915#402]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb2/igt at kms_color@pipe-d-ctm-0-5.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +26 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +3 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_setmode@basic: - shard-apl: [FAIL][65] ([i915#31]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_setmode@basic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_setmode@basic.html - shard-kbl: [FAIL][67] ([i915#31]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_setmode@basic.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][69] ([i915#1542]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-hsw5/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [SKIP][71] ([fdo#109271]) -> [INCOMPLETE][72] ([i915#82]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb5/igt at i915_pm_dc@dc3co-vpb-simulation.html - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#588]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][75] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][77] ([fdo#110321]) -> [TIMEOUT][78] ([i915#1319] / [i915#1958]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][79] ([fdo#110321] / [i915#95]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][81] ([fdo#110321] / [i915#95]) -> [TIMEOUT][82] ([i915#1319]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html - shard-apl: [DMESG-WARN][85] ([i915#180] / [i915#95]) -> [DMESG-WARN][86] ([i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-WARN][87] ([i915#1982]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1982]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17882 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17882: 23fe5e3ae83585e3d4ad9ecdfea368dd42ff6dfb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 11:43:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 11:43:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915=3A_Discard_a_misplaced_GGT?= =?utf-8?q?T_vma?= In-Reply-To: <20200605105646.24300-1-chris@chris-wilson.co.uk> References: <20200605105646.24300-1-chris@chris-wilson.co.uk> Message-ID: <159135741577.18507.11493599421105724250@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Discard a misplaced GGTT vma URL : https://patchwork.freedesktop.org/series/78033/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17884 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/index.html Known issues ------------ Here are the changes found in Patchwork_17884 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-byt-n2820/igt at i915_module_load@reload.html - fi-tgl-y: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-tgl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-whl-u: [DMESG-WARN][9] ([i915#95]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at active: - fi-whl-u: [DMESG-FAIL][13] ([i915#666]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_selftest@live at active.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-whl-u/igt at i915_selftest@live at active.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17884 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17884: 8f309332415b32d03c96f11a8a4b451ac66f2742 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8f309332415b drm/i915/gem: Avoid kmalloc under i915->mm_lock 5de23154206a drm/i915: Discard a misplaced GGTT vma == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/index.html From ville.syrjala at linux.intel.com Fri Jun 5 11:43:52 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 5 Jun 2020 14:43:52 +0300 Subject: [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 In-Reply-To: <20200604221240.GC3023929@mdroper-desk1.amr.corp.intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-3-matthew.d.roper@intel.com> <20200604170157.GZ6112@intel.com> <20200604221240.GC3023929@mdroper-desk1.amr.corp.intel.com> Message-ID: <20200605114352.GK6112@intel.com> On Thu, Jun 04, 2020 at 03:12:40PM -0700, Matt Roper wrote: > On Thu, Jun 04, 2020 at 08:01:57PM +0300, Ville Syrj?l? wrote: > > On Wed, Jun 03, 2020 at 02:15:16PM -0700, Matt Roper wrote: > > > RKL uses the same BW_BUDDY programming table as TGL, but programs the > > > values into a single set BUDDY0 set of registers rather than the > > > BUDDY1/BUDDY2 sets used by TGL. > > > > Maybe we just want some kind of HAS_ABOX() so we could use the same > > thing here and in the ABOX_CTL programming? > > Although these are both related to how the display controller accesses > memory, I don't think they're quite a 1:1 mapping. TGL has > MBUX_ABOX_CTL{0,1,2} (and we're directed to program all three), but only > has BW_BUDDY_CTL{1,2} and no 0 instance. I see three different notes on this: tgl style: "Abox1 and Abox2 are used for pixel data reads. Program the BW_BUDDY1 and BW_BUDDY2 registers." abox0 is the legacy path, so doesn't need this stuff apparently. abox1/2 are the dedicated path. rkl style: "Abox0 is used for pixel data reads. Program the BW_BUDDY0 registers." the dedicated path is removed so I guess they had to add the buddy registers for the legacy path abox. some other style: "Abox0 and Abox1 are used for pixel data reads. Program the BW_BUDDY0 and BW_BUDDY1 registers." I presume this means the legacy path is getting nuked, and thus the two aboxes for the dedicated path are just getting shifted down. Unfortunately I can't find a hsd which tells the story. So yeah, there is a slight difference for the tgl style in that we still want to program ABOX_CTL0 but not BW_BUDDY0. > > For now I'll just add separate bw_buddy and abox masks to our platform > device info structure. Or could maybe just add an exception for tgl. Either if (HAS_ABOX(0) || IS_TGL) write(ABOX_CTL0); ... or if (HAS_ABOX(0) && !IS_TGL) write(BUDDY0); ... would seem reasonable enough to me. > > > Matt > > > > > > > > > Bspec: 49218 > > > Cc: Aditya Swarup <aditya.swarup at intel.com> > > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > > --- > > > .../drm/i915/display/intel_display_power.c | 44 +++++++++++-------- > > > drivers/gpu/drm/i915/i915_reg.h | 14 ++++-- > > > 2 files changed, 35 insertions(+), 23 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > > > index 72312b67b57a..2c1ce50b572b 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > > @@ -5254,7 +5254,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > > enum intel_dram_type type = dev_priv->dram_info.type; > > > u8 num_channels = dev_priv->dram_info.num_channels; > > > const struct buddy_page_mask *table; > > > - int i; > > > + int config, min_buddy, max_buddy, i; > > > > > > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) > > > /* Wa_1409767108: tgl */ > > > @@ -5262,29 +5262,35 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > > > else > > > table = tgl_buddy_page_masks; > > > > > > - for (i = 0; table[i].page_mask != 0; i++) > > > - if (table[i].num_channels == num_channels && > > > - table[i].type == type) > > > + if (IS_ROCKETLAKE(dev_priv)) { > > > + min_buddy = max_buddy = 0; > > > + } else { > > > + min_buddy = 1; > > > + max_buddy = 2; > > > + } > > > + > > > + for (config = 0; table[config].page_mask != 0; config++) > > > + if (table[config].num_channels == num_channels && > > > + table[config].type == type) > > > break; > > > > > > - if (table[i].page_mask == 0) { > > > + if (table[config].page_mask == 0) { > > > drm_dbg(&dev_priv->drm, > > > "Unknown memory configuration; disabling address buddy logic.\n"); > > > - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); > > > - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); > > > + for (i = min_buddy; i <= max_buddy; i++) > > > + intel_de_write(dev_priv, BW_BUDDY_CTL(i), > > > + BW_BUDDY_DISABLE); > > > } else { > > > - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, > > > - table[i].page_mask); > > > - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, > > > - table[i].page_mask); > > > - > > > - /* Wa_22010178259:tgl */ > > > - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, > > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > > - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, > > > - BW_BUDDY_TLB_REQ_TIMER_MASK, > > > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > > > + for (i = min_buddy; i <= max_buddy; i++) { > > > + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > > > + table[config].page_mask); > > > + > > > + /* Wa_22010178259:tgl,rkl */ > > > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > > > + BW_BUDDY_TLB_REQ_TIMER_MASK, > > > + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, > > > + 0x8)); > > > + } > > > } > > > } > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 578cfe11cbb9..3e79cefc510a 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -7837,13 +7837,19 @@ enum { > > > #define WAIT_FOR_PCH_RESET_ACK (1 << 1) > > > #define WAIT_FOR_PCH_FLR_ACK (1 << 0) > > > > > > -#define BW_BUDDY1_CTL _MMIO(0x45140) > > > -#define BW_BUDDY2_CTL _MMIO(0x45150) > > > +#define _BW_BUDDY0_CTL 0x45130 > > > +#define _BW_BUDDY1_CTL 0x45140 > > > +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ > > > + _BW_BUDDY0_CTL, \ > > > + _BW_BUDDY1_CTL)) > > > #define BW_BUDDY_DISABLE REG_BIT(31) > > > #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) > > > > > > -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) > > > -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) > > > +#define _BW_BUDDY0_PAGE_MASK 0x45134 > > > +#define _BW_BUDDY1_PAGE_MASK 0x45144 > > > +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ > > > + _BW_BUDDY0_PAGE_MASK, \ > > > + _BW_BUDDY1_PAGE_MASK)) > > > > > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > > > #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > > > -- > > > 2.24.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrj?l? > > Intel > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 -- Ville Syrj?l? Intel From imre.deak at intel.com Fri Jun 5 11:50:01 2020 From: imre.deak at intel.com (Imre Deak) Date: Fri, 5 Jun 2020 14:50:01 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BRESEND=2Cv3=2C1/3=5D_drm/i915/dp=5Fmst=3A_?= =?utf-8?q?Fix_disabling_MST_on_a_port_=28rev6=29?= In-Reply-To: <159135637372.18508.17555303407147804828@emeril.freedesktop.org> References: <20200603211040.8190-1-imre.deak@intel.com> <159135637372.18508.17555303407147804828@emeril.freedesktop.org> Message-ID: <20200605115001.GB17978@ideak-desk.fi.intel.com> On Fri, Jun 05, 2020 at 11:26:13AM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6) > URL : https://patchwork.freedesktop.org/series/77969/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17882_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17882_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17882_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17882_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: > - shard-snb: [PASS][1] -> [TIMEOUT][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html > > > #### Warnings #### > > * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: > - shard-snb: [SKIP][3] ([fdo#109271]) -> [TIMEOUT][4] +1 similar issue > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html Both of the above are unrelated, since there's only a VGA output connected to shard-snb1. Both tests time out because an earlier failure: <7>[ 96.713236] [IGT] gem_exec_reloc: starting subtest basic-concurrent16 <5>[ 216.856564] [IGT] Per-test timeout exceeded. Killing the current test with SIGQUIT. <6>[ 216.880307] gem_exec_reloc S12784 1625 1624 0x00000000 <4>[ 216.880311] Call Trace: <4>[ 216.880317] __schedule+0x2ff/0x8d0 <4>[ 216.880325] schedule+0x37/0xe0 <4>[ 216.880328] schedule_timeout+0x1aa/0x2e0 <4>[ 216.880390] ? mock_breadcrumbs_smoketest+0x290/0x290 [i915] <4>[ 216.880394] ? find_held_lock+0x2d/0x90 <4>[ 216.880442] ? hwsp_seqno+0x5b/0xd0 [i915] <4>[ 216.880449] io_schedule_timeout+0x14/0x40 <4>[ 216.880502] i915_request_wait+0x159/0x550 [i915] <4>[ 216.880548] ? __i915_request_await_external+0x40/0x40 [i915] <4>[ 216.880593] i915_gem_object_wait+0xb2/0x540 [i915] <4>[ 216.880640] i915_gem_wait_ioctl+0x113/0x2d0 [i915] <4>[ 216.880683] ? i915_gem_object_wait+0x540/0x540 [i915] <4>[ 216.880688] drm_ioctl_kernel+0xb0/0xf0 <4>[ 216.880694] drm_ioctl+0x305/0x3c0 <4>[ 216.880737] ? i915_gem_object_wait+0x540/0x540 [i915] <4>[ 216.880750] ksys_ioctl+0x7b/0x90 <4>[ 216.880755] __x64_sys_ioctl+0x11/0x20 <4>[ 216.880757] do_syscall_64+0x4f/0x220 <4>[ 216.880760] entry_SYSCALL_64_after_hwframe+0x49/0xb3 > > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * {igt at gem_exec_reloc@basic-concurrent16}: > - shard-snb: [FAIL][5] ([i915#1930]) -> [TIMEOUT][6] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html > > * {igt at kms_chamelium@vga-hpd-enable-disable-mode}: > - shard-snb: [SKIP][7] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][8] > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_chamelium@vga-hpd-enable-disable-mode.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_chamelium@vga-hpd-enable-disable-mode.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_17882_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_whisper@basic-forked-all: > - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk7/igt at gem_exec_whisper@basic-forked-all.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk2/igt at gem_exec_whisper@basic-forked-all.html > > * igt at gem_mmap_gtt@cpuset-big-copy-odd: > - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > > * igt at gem_workarounds@suspend-resume: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_workarounds@suspend-resume.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_workarounds@suspend-resume.html > > * igt at kms_big_fb@linear-32bpp-rotate-180: > - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +9 similar issues > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_big_fb@linear-32bpp-rotate-180.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_big_fb@linear-32bpp-rotate-180.html > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / [i915#95]) +1 similar issue > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html > > * igt at kms_big_fb@x-tiled-16bpp-rotate-0: > - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk4/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html > > * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: > - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +17 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html > > * igt at kms_cursor_crc@pipe-c-cursor-suspend: > - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > > * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: > - shard-skl: [PASS][27] -> [FAIL][28] ([i915#49]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt at kms_plane_lowres@pipe-a-tiling-x: > - shard-snb: [PASS][31] -> [SKIP][32] ([fdo#109271]) +1 similar issue > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at kms_plane_lowres@pipe-a-tiling-x.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_lowres@pipe-a-tiling-x.html > > * igt at kms_psr@psr2_cursor_blt: > - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +3 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb4/igt at kms_psr@psr2_cursor_blt.html > > * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: > - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html > > * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: > - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#402]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html > > > #### Possible fixes #### > > * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: > - shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +2 similar issues > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html > > * igt at gem_exec_whisper@basic-queues-forked-all: > - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html > > * igt at gen9_exec_parse@allowed-all: > - shard-kbl: [DMESG-WARN][43] ([i915#1436] / [i915#716]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at gen9_exec_parse@allowed-all.html > > * igt at i915_suspend@debugfs-reader: > - shard-kbl: [INCOMPLETE][45] ([i915#155]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl6/igt at i915_suspend@debugfs-reader.html > > * igt at kms_color@pipe-c-ctm-red-to-blue: > - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html > > * igt at kms_color@pipe-d-ctm-0-5: > - shard-tglb: [DMESG-WARN][49] ([i915#1149] / [i915#402]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb2/igt at kms_color@pipe-d-ctm-0-5.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html > > * igt at kms_cursor_legacy@all-pipes-torture-move: > - shard-skl: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_cursor_legacy@all-pipes-torture-move.html > > * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: > - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html > > * igt at kms_flip_tiling@flip-x-tiled: > - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +26 similar issues > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_flip_tiling@flip-x-tiled.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: > - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +3 similar issues > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > > * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: > - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +2 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html > > * igt at kms_psr@psr2_primary_mmap_cpu: > - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html > > * igt at kms_setmode@basic: > - shard-apl: [FAIL][65] ([i915#31]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_setmode@basic.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_setmode@basic.html > - shard-kbl: [FAIL][67] ([i915#31]) -> [PASS][68] > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_setmode@basic.html > > * {igt at perf@polling-parameterized}: > - shard-hsw: [FAIL][69] ([i915#1542]) -> [PASS][70] > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-hsw5/igt at perf@polling-parameterized.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-snb: [SKIP][71] ([fdo#109271]) -> [INCOMPLETE][72] ([i915#82]) +1 similar issue > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb5/igt at i915_pm_dc@dc3co-vpb-simulation.html > - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#588]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at kms_content_protection@atomic: > - shard-apl: [FAIL][75] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@legacy: > - shard-kbl: [DMESG-FAIL][77] ([fdo#110321]) -> [TIMEOUT][78] ([i915#1319] / [i915#1958]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_content_protection@legacy.html > > * igt at kms_content_protection@lic: > - shard-apl: [DMESG-FAIL][79] ([fdo#110321] / [i915#95]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) +1 similar issue > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at kms_content_protection@lic.html > > * igt at kms_content_protection@srm: > - shard-kbl: [DMESG-FAIL][81] ([fdo#110321] / [i915#95]) -> [TIMEOUT][82] ([i915#1319]) > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_content_protection@srm.html > > * igt at kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html > - shard-apl: [DMESG-WARN][85] ([i915#180] / [i915#95]) -> [DMESG-WARN][86] ([i915#95]) > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [DMESG-WARN][87] ([i915#1982]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1982]) > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8590 -> Patchwork_17882 > > CI-20190529: 20190529 > CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17882: 23fe5e3ae83585e3d4ad9ecdfea368dd42ff6dfb @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/index.html From ville.syrjala at linux.intel.com Fri Jun 5 11:52:14 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 5 Jun 2020 14:52:14 +0300 Subject: [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL In-Reply-To: <20200604231849.GE3023929@mdroper-desk1.amr.corp.intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <20200603211529.3005059-8-matthew.d.roper@intel.com> <20200604182919.GB6112@intel.com> <20200604231849.GE3023929@mdroper-desk1.amr.corp.intel.com> Message-ID: <20200605115214.GL6112@intel.com> On Thu, Jun 04, 2020 at 04:18:49PM -0700, Matt Roper wrote: > On Thu, Jun 04, 2020 at 09:29:19PM +0300, Ville Syrj?l? wrote: > > On Wed, Jun 03, 2020 at 02:15:21PM -0700, Matt Roper wrote: > > > When TGP is paired with RKL it uses a different HPD pin mapping than > > > when paired with TGL. > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++++++++- > > > 1 file changed, 14 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > > index 490574669eaa..f3ea81a17352 100644 > > > --- a/drivers/gpu/drm/i915/i915_irq.c > > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > > @@ -167,6 +167,17 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { > > > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), > > > }; > > > > > > +/* > > > + * TGP when paired with RKL has different pin mappings than when paired > > > + * with TGL. > > > + */ > > > +static const u32 hpd_rkl_tgp[HPD_NUM_PINS] = { > > > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), > > > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), > > > + [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1), > > > + [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2), > > > +}; > > > > Hmm. So basically it looks like we'd want to pick the hpd_pin > > based on the DDI rather than the PHY on this platform? > > I may be misinterpreting the table on bspec 49181, but I *think* it > looks like we use the DDI when paired with a TGP PCH and the PHY when > paired with CMP PCH. So if I just set the hpd_pin based on the DDI, > then I think that will break the CMP-based systems (although I haven't > tested on one of those, so I'm not 100% sure). After staring at the spec+code a bit I think what I want to do is introduce proper HPD_PORT_TC1-6 enums (and remove HPD_PORT_F+ since they become unused). In the meantime I think assigning hpd_pin in a custom way for rkl only should work. > > > Matt > > > > > OK, I guess we need to remap somehow. The question is > > whether we want to do it before or after selecting hpd_pin... > > I think we would want to do it before, as otherwise the > > long_detect() stuff won't work right AFAICS. Or am I > > missing something? > > > > Side note: we should probably convert the long_detect() > > switches to arrays just like we have for the isr bits here. > > Would potentially avoid having to touch that code every time > > they tweak these thinhs in hw. > > > > And in fact it looks like icp already has all the same hpd > > pins as tgp, so I'm thinking we should just s/hpd_tgp/hpd_icp/ > > and for icl/jsl we should remap hpd_pin as well. Oh and the > > mcc case would just need a slightly different mapping of > > port C -> HPD_PORT_D (aka. tc1). > > > > This way all the hpd[] arrays and whatnot would just be based > > on the actual pch type and not based on what it happens to be > > paired with. > > > > Anwyays, most of that is out of scope for this rkl stuff, so > > I guess for now just add a bit of logic to remap hpd_pin for rkl? > > > > > + > > > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > > > { > > > struct i915_hotplug *hpd = &dev_priv->hotplug; > > > @@ -196,7 +207,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > > > if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) > > > return; > > > > > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > > > + if (HAS_PCH_TGP(dev_priv) && IS_ROCKETLAKE(dev_priv)) > > > + hpd->pch_hpd = hpd_rkl_tgp; > > > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > > > hpd->pch_hpd = hpd_tgp; > > > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) > > > hpd->pch_hpd = hpd_icp; > > > -- > > > 2.24.1 > > > > -- > > Ville Syrj?l? > > Intel > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Fri Jun 5 12:10:14 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 12:10:14 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/5=5D_drm/i915=3A_Add_list=5Ffor=5Feach?= =?utf-8?q?=5Fentry=5Fsafe=5Fcontinue=5Freverse?= In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <159135901447.18509.1489882016024324506@emeril.freedesktop.org> == Series Details == Series: series starting with [1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse URL : https://patchwork.freedesktop.org/series/78031/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17883_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17883_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl1/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk8/igt at gem_exec_whisper@basic-contexts-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-glk9/igt at gem_exec_whisper@basic-contexts-forked.html * igt at gem_tiled_swapping@non-threaded: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#183]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at gem_tiled_swapping@non-threaded.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-glk8/igt at gem_tiled_swapping@non-threaded.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +13 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl1/igt at kms_color@pipe-c-ctm-0-25.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl8/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [PASS][13] -> [DMESG-FAIL][14] ([i915#54] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl7/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#95]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#93] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#49]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +3 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-iclb1/igt at kms_psr@psr2_cursor_blt.html * igt at kms_vblank@pipe-b-wait-busy: - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb1/igt at kms_vblank@pipe-b-wait-busy.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-iclb8/igt at kms_vblank@pipe-b-wait-busy.html * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#402]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-tglb3/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][39] ([i915#1930]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +3 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [INCOMPLETE][43] ([i915#155]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl7/igt at i915_suspend@debugfs-reader.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl3/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][49] ([i915#128]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl1/igt at kms_cursor_legacy@all-pipes-torture-move.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-hsw: [TIMEOUT][51] -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw5/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-hsw5/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * {igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][53] ([i915#79]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +10 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl8/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl6/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62] +4 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_scaling@pipe-c-plane-scaling: - shard-skl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_plane_scaling@pipe-c-plane-scaling.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-skl10/igt at kms_plane_scaling@pipe-c-plane-scaling.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][67] ([i915#31]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl2/igt at kms_setmode@basic.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][69] ([i915#454]) -> [SKIP][70] ([i915#468]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb3/igt at i915_pm_dc@dc6-psr.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_ccs@pipe-c-crc-primary-basic: - shard-hsw: [TIMEOUT][71] -> [SKIP][72] ([fdo#109271]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw5/igt at kms_ccs@pipe-c-crc-primary-basic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-hsw5/igt at kms_ccs@pipe-c-crc-primary-basic.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][73] ([fdo#110321] / [fdo#110336]) -> [DMESG-FAIL][74] ([fdo#110321]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][75] ([fdo#110321]) -> [TIMEOUT][76] ([i915#1319]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][77] ([fdo#110321] / [i915#95]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl3/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][79] ([fdo#110321] / [i915#95]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl8/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl6/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-hsw: [INCOMPLETE][81] ([i915#61]) -> [SKIP][82] ([fdo#109271]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-hsw5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html - shard-apl: [DMESG-WARN][85] ([i915#180] / [i915#95]) -> [DMESG-WARN][86] ([i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/shard-apl7/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#183]: https://gitlab.freedesktop.org/drm/intel/issues/183 [i915#1893]: https://gitlab.freedesktop.org/drm/intel/issues/1893 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17883 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17883: 00beaabc4fe051ae2d54aeba089389d20131e280 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17883/index.html From chris at chris-wilson.co.uk Fri Jun 5 12:23:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:33 +0100 Subject: [Intel-gfx] [PATCH 09/10] drm/i915/gt: Implement ring scheduler for gen6/7 In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-9-chris@chris-wilson.co.uk> A key prolem with legacy ring buffer submission is that it is an inheret FIFO queue across all clients; if one blocks, they all block. A scheduler allows us to avoid that limitation, and ensures that all clients can submit in parallel, removing the resource contention of the global ringbuffer. Having built the ring scheduler infrastructure over top of the global ringbuffer submission, we now need to provide the HW knowledge required to build command packets and implement context switching. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gt/intel_ring_scheduler.c | 412 +++++++++++++++++- 1 file changed, 410 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index aaff554865b1..463c836cbde2 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -7,6 +7,10 @@ #include <drm/i915_drm.h> +#include "gen2_engine_cs.h" +#include "gen6_engine_cs.h" +#include "gen6_ppgtt.h" +#include "gen7_renderclear.h" #include "i915_drv.h" #include "intel_context.h" #include "intel_engine_stats.h" @@ -282,8 +286,258 @@ static void ring_copy(struct intel_ring *dst, memcpy(out, src->vaddr + start, end - start); } +static void mi_set_context(struct intel_ring *ring, + struct intel_engine_cs *engine, + struct intel_context *ce, + u32 flags) +{ + struct drm_i915_private *i915 = engine->i915; + enum intel_engine_id id; + const int num_engines = + IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; + int len; + u32 *cs; + + len = 4; + if (IS_GEN(i915, 7)) + len += 2 + (num_engines ? 4 * num_engines + 6 : 0); + else if (IS_GEN(i915, 5)) + len += 2; + + cs = ring_map_dw(ring, len); + + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ + if (IS_GEN(i915, 7)) { + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; + if (num_engines) { + struct intel_engine_cs *signaller; + + *cs++ = MI_LOAD_REGISTER_IMM(num_engines); + for_each_engine(signaller, engine->gt, id) { + if (signaller == engine) + continue; + + *cs++ = i915_mmio_reg_offset( + RING_PSMI_CTL(signaller->mmio_base)); + *cs++ = _MASKED_BIT_ENABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + } + } else if (IS_GEN(i915, 5)) { + /* + * This w/a is only listed for pre-production ilk a/b steppings, + * but is also mentioned for programming the powerctx. To be + * safe, just apply the workaround; we do not use SyncFlush so + * this should never take effect and so be a no-op! + */ + *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN; + } + + *cs++ = MI_NOOP; + *cs++ = MI_SET_CONTEXT; + *cs++ = i915_ggtt_offset(ce->state) | flags; + /* + * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP + * WaMiSetContext_Hang:snb,ivb,vlv + */ + *cs++ = MI_NOOP; + + if (IS_GEN(i915, 7)) { + if (num_engines) { + struct intel_engine_cs *signaller; + i915_reg_t last_reg = {}; /* keep gcc quiet */ + + *cs++ = MI_LOAD_REGISTER_IMM(num_engines); + for_each_engine(signaller, engine->gt, id) { + if (signaller == engine) + continue; + + last_reg = RING_PSMI_CTL(signaller->mmio_base); + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = _MASKED_BIT_DISABLE( + GEN6_PSMI_SLEEP_MSG_DISABLE); + } + + /* Insert a delay before the next switch! */ + *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(last_reg); + *cs++ = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + *cs++ = MI_NOOP; + } + *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; + } else if (IS_GEN(i915, 5)) { + *cs++ = MI_SUSPEND_FLUSH; + } +} + +static struct i915_address_space *vm_alias(struct i915_address_space *vm) +{ + if (i915_is_ggtt(vm)) + vm = &i915_vm_to_ggtt(vm)->alias->vm; + + return vm; +} + +static void load_pd_dir(struct intel_ring *ring, + struct intel_engine_cs *engine, + const struct i915_ppgtt *ppgtt) +{ + u32 *cs = ring_map_dw(ring, 10); + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); + *cs++ = PP_DIR_DCLV_2G; + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); + *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; + + /* Stall until the page table load is complete? */ + *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; + *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); + *cs++ = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_DEFAULT); + *cs++ = MI_NOOP; +} + +static struct i915_address_space *current_vm(struct intel_engine_cs *engine) +{ + struct intel_context *old = engine->legacy.context; + + return old ? vm_alias(old->vm) : NULL; +} + +static void gen6_emit_invalidate_rcs(struct intel_ring *ring, + struct intel_engine_cs *engine) +{ + u32 addr, flags; + u32 *cs; + + addr = intel_gt_scratch_offset(engine->gt, + INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH); + + flags = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; + flags |= PIPE_CONTROL_TLB_INVALIDATE; + + if (INTEL_GEN(engine->i915) >= 7) + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + else + addr |= PIPE_CONTROL_GLOBAL_GTT; + + cs = ring_map_dw(ring, 4); + *cs++ = GFX_OP_PIPE_CONTROL(4); + *cs++ = flags; + *cs++ = addr; + *cs++ = 0; +} + +static struct i915_address_space * +clear_residuals(struct intel_ring *ring, struct intel_engine_cs *engine) +{ + struct intel_context *ce = engine->kernel_context; + struct i915_address_space *vm = vm_alias(engine->gt->vm); + u32 flags; + + if (vm != current_vm(engine)) + load_pd_dir(ring, engine, i915_vm_to_ppgtt(vm)); + + if (ce->state) + mi_set_context(ring, engine, ce, + MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT); + + if (IS_HASWELL(engine->i915)) + flags = MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW; + else + flags = MI_BATCH_NON_SECURE_I965; + + __gen6_emit_bb_start(ring_map_dw(ring, 2), + engine->wa_ctx.vma->node.start, flags); + + return vm; +} + +static void remap_l3_slice(struct intel_ring *ring, + struct intel_engine_cs *engine, + int slice) +{ + u32 *cs, *remap_info = engine->i915->l3_parity.remap_info[slice]; + int i; + + if (!remap_info) + return; + + /* + * Note: We do not worry about the concurrent register cacheline hang + * here because no other code should access these registers other than + * at initialization time. + */ + cs = ring_map_dw(ring, GEN7_L3LOG_SIZE / 4 * 2 + 2); + *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE / 4); + for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { + *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); + *cs++ = remap_info[i]; + } + *cs++ = MI_NOOP; +} + +static void remap_l3(struct intel_ring *ring, + struct intel_engine_cs *engine, + struct intel_context *ce) +{ + struct i915_gem_context *ctx = + rcu_dereference_protected(ce->gem_context, true); + int bit, idx = -1; + + if (!ctx || !ctx->remap_slice) + return; + + do { + bit = ffs(ctx->remap_slice); + remap_l3_slice(ring, engine, idx += bit); + } while (ctx->remap_slice >>= bit); +} + static void switch_context(struct intel_ring *ring, struct i915_request *rq) { + struct intel_engine_cs *engine = rq->engine; + struct i915_address_space *cvm = current_vm(engine); + struct intel_context *ce = rq->context; + struct i915_address_space *vm; + + if (engine->wa_ctx.vma && ce != engine->kernel_context) { + if (engine->wa_ctx.vma->private != ce) { + cvm = clear_residuals(ring, engine); + intel_context_put(engine->wa_ctx.vma->private); + engine->wa_ctx.vma->private = intel_context_get(ce); + } + } + + vm = vm_alias(ce->vm); + if (vm != cvm) + load_pd_dir(ring, engine, i915_vm_to_ppgtt(vm)); + + if (ce->state) { + u32 flags; + + GEM_BUG_ON(engine->id != RCS0); + + /* For resource streamer on HSW+ and power context elsewhere */ + BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN); + BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN); + + flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT; + if (test_bit(CONTEXT_VALID_BIT, &ce->flags)) { + gen6_emit_invalidate_rcs(ring, engine); + flags |= MI_RESTORE_EXT_STATE_EN; + } else { + flags |= MI_RESTORE_INHIBIT; + } + + mi_set_context(ring, engine, ce, flags); + } + + remap_l3(ring, engine, ce); } static struct i915_request *ring_submit(struct i915_request *rq) @@ -449,6 +703,33 @@ static void submission_unpark(struct intel_engine_cs *engine) intel_engine_pin_breadcrumbs_irq(engine); } +static int gen6_emit_init_breadcrumb(struct i915_request *rq) +{ + struct intel_timeline *tl = i915_request_timeline(rq); + u32 *cs; + + GEM_BUG_ON(i915_request_has_initial_breadcrumb(rq)); + if (!tl->has_initial_breadcrumb) + return 0; + + cs = intel_ring_begin(rq, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = 0; + *cs++ = tl->hwsp_offset; + *cs++ = rq->fence.seqno - 1; + + intel_ring_advance(rq, cs); + + /* Record the updated position of the request's payload */ + rq->infix = intel_ring_offset(rq, cs); + + __set_bit(I915_FENCE_FLAG_INITIAL_BREADCRUMB, &rq->fence.flags); + return 0; +} + static void ring_context_destroy(struct kref *ref) { struct intel_context *ce = container_of(ref, typeof(*ce), ref); @@ -464,8 +745,30 @@ static void ring_context_destroy(struct kref *ref) intel_context_free(ce); } +static int __context_pin_ppgtt(struct intel_context *ce) +{ + struct i915_address_space *vm; + int err = 0; + + vm = vm_alias(ce->vm); + if (vm) + err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); + + return err; +} + +static void __context_unpin_ppgtt(struct intel_context *ce) +{ + struct i915_address_space *vm; + + vm = vm_alias(ce->vm); + if (vm) + gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm)); +} + static void ring_context_unpin(struct intel_context *ce) { + __context_unpin_ppgtt(ce); } static int alloc_context_vma(struct intel_context *ce) @@ -593,7 +896,7 @@ static int ring_context_alloc(struct intel_context *ce) static int ring_context_pin(struct intel_context *ce) { - return 0; + return __context_pin_ppgtt(ce); } static void ring_context_reset(struct intel_context *ce) @@ -649,12 +952,19 @@ static void ring_release(struct intel_engine_cs *engine) set_current_context(&engine->legacy.context, NULL); + if (engine->wa_ctx.vma) { + intel_context_put(engine->wa_ctx.vma->private); + i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); + } + intel_ring_unpin(engine->legacy.ring); intel_ring_put(engine->legacy.ring); } static void setup_irq(struct intel_engine_cs *engine) { + engine->irq_enable = gen6_irq_enable; + engine->irq_disable = gen6_irq_disable; } static void setup_common(struct intel_engine_cs *engine) @@ -663,7 +973,7 @@ static void setup_common(struct intel_engine_cs *engine) /* gen8+ are only supported with execlists */ GEM_BUG_ON(INTEL_GEN(i915) >= 8); - GEM_BUG_ON(INTEL_GEN(i915) < 8); + GEM_BUG_ON(INTEL_GEN(i915) < 6); setup_irq(engine); @@ -680,24 +990,62 @@ static void setup_common(struct intel_engine_cs *engine) engine->cops = &ring_context_ops; engine->request_alloc = ring_request_alloc; + engine->emit_init_breadcrumb = gen6_emit_init_breadcrumb; + if (INTEL_GEN(i915) >= 7) + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs; + else if (INTEL_GEN(i915) >= 6) + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs; + else + engine->emit_fini_breadcrumb = gen3_emit_breadcrumb; + engine->set_default_submission = set_default_submission; + + engine->emit_bb_start = gen6_emit_bb_start; } static void setup_rcs(struct intel_engine_cs *engine) { + struct drm_i915_private *i915 = engine->i915; + + if (HAS_L3_DPF(i915)) + engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; + + engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; + + if (INTEL_GEN(i915) >= 7) { + engine->emit_flush = gen7_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs; + if (IS_HASWELL(i915)) + engine->emit_bb_start = hsw_emit_bb_start; + } else { + engine->emit_flush = gen6_emit_flush_rcs; + engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs; + } } static void setup_vcs(struct intel_engine_cs *engine) { + engine->emit_flush = gen6_emit_flush_vcs; + engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; + + if (IS_GEN(engine->i915, 6)) + engine->fw_domain = FORCEWAKE_ALL; } static void setup_bcs(struct intel_engine_cs *engine) { + engine->emit_flush = gen6_emit_flush_xcs; + engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; } static void setup_vecs(struct intel_engine_cs *engine) { GEM_BUG_ON(!IS_HASWELL(engine->i915)); + + engine->emit_flush = gen6_emit_flush_xcs; + engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; + engine->irq_enable = hsw_irq_enable_vecs; + engine->irq_disable = hsw_irq_disable_vecs; } static unsigned int global_ring_size(void) @@ -706,6 +1054,58 @@ static unsigned int global_ring_size(void) return roundup_pow_of_two(EXECLIST_MAX_PORTS * SZ_16K + SZ_4K); } +static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine) +{ + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int size; + int err; + + size = gen7_setup_clear_gpr_bb(engine, NULL /* probe size */); + if (size <= 0) + return size; + + size = ALIGN(size, PAGE_SIZE); + obj = i915_gem_object_create_internal(engine->i915, size); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + vma = i915_vma_instance(obj, engine->gt->vm, NULL); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto err_obj; + } + + vma->private = intel_context_create(engine); /* dummy residuals */ + if (IS_ERR(vma->private)) { + err = PTR_ERR(vma->private); + goto err_obj; + } + + err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + if (err) + goto err_private; + + err = i915_vma_sync(vma); + if (err) + goto err_unpin; + + size = gen7_setup_clear_gpr_bb(engine, vma); + if (err) + goto err_unpin; + + engine->wa_ctx.vma = vma; + return 0; + +err_unpin: + i915_vma_unpin(vma); +err_private: + intel_context_put(vma->private); +err_obj: + i915_gem_object_put(obj); + return err; +} + int intel_ring_scheduler_setup(struct intel_engine_cs *engine) { struct intel_ring *ring; @@ -749,6 +1149,12 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) GEM_BUG_ON(engine->legacy.ring); engine->legacy.ring = ring; + if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) { + err = gen7_ctx_switch_bb_init(engine); + if (err) + goto err_ring_unpin; + } + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; engine->flags |= I915_ENGINE_SUPPORTS_STATS; @@ -756,6 +1162,8 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) engine->release = ring_release; return 0; +err_ring_unpin: + intel_ring_unpin(ring); err_ring: intel_ring_put(ring); err: -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:26 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:26 +0100 Subject: [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-2-chris@chris-wilson.co.uk> We may choose not to submit for a number of reasons, yet not fill both ELSP. In which case we must start timeslicing (there will be no ACK event on which to hook the start) if the queue would benefit from the currently active context being evicted. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 92c3368ffcbd..d55a5e0466e5 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2362,10 +2362,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last->context == rq->context) goto done; - if (i915_request_has_sentinel(last)) { - start_timeslice(engine, rq_prio(rq)); + if (i915_request_has_sentinel(last)) goto done; - } /* * If GVT overrides us we only ever submit @@ -2446,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) set_preempt_timeout(engine, *active); execlists_submit_ports(engine); } else { + start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); } -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:25 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:25 +0100 Subject: [Intel-gfx] [PATCH 01/10] drm/i915/gt: Set timeslicing priority from queue Message-ID: <20200605122334.2798-1-chris@chris-wilson.co.uk> If we only submit the first port, leaving the second empty yet have ready requests pending in the queue, use that to set the timeslicing priority (i.e. the priority at which we will decided to enabling timeslicing and evict the currently active context if the queue is of equal priority after its quantum expired). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 33b7173b7195..92c3368ffcbd 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1966,7 +1966,7 @@ static int switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq) { if (list_is_last(&rq->sched.link, &engine->active.requests)) - return INT_MIN; + return engine->execlists.queue_priority_hint; return rq_prio(list_next_entry(rq, sched.link)); } -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:29 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:29 +0100 Subject: [Intel-gfx] [PATCH 05/10] drm/i915/gt: Support creation of 'internal' rings In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-5-chris@chris-wilson.co.uk> To support legacy ring buffer scheduling, we want a virtual ringbuffer for each client. These rings are purely for holding the requests as they are being constructed on the CPU and never accessed by the GPU, so they should not be bound into the GGTT, and we can use plain old WB mapped pages. As they are not bound, we need to nerf a few assumptions that a rq->ring is in the GGTT. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 ++---- drivers/gpu/drm/i915/gt/intel_ring.c | 63 ++++++++++++++-------- drivers/gpu/drm/i915/gt/intel_ring.h | 12 ++++- drivers/gpu/drm/i915/gt/intel_ring_types.h | 2 + 5 files changed, 57 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index e4aece20bc80..fd71977c010a 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -127,7 +127,7 @@ int __intel_context_do_pin(struct intel_context *ce) goto err_active; CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", - i915_ggtt_offset(ce->ring->vma), + intel_ring_address(ce->ring), ce->ring->head, ce->ring->tail); smp_mb__before_atomic(); /* flush pin before it is visible */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e37490d459c2..4b36378af119 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1259,7 +1259,7 @@ static int print_ring(char *buf, int sz, struct i915_request *rq) len = scnprintf(buf, sz, "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ", - i915_ggtt_offset(rq->ring->vma), + intel_ring_address(rq->ring), tl ? tl->hwsp_offset : 0, hwsp_seqno(rq), DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context), @@ -1540,7 +1540,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, print_request(m, rq, "\t\tactive "); drm_printf(m, "\t\tring->start: 0x%08x\n", - i915_ggtt_offset(rq->ring->vma)); + intel_ring_address(rq->ring)); drm_printf(m, "\t\tring->head: 0x%08x\n", rq->ring->head); drm_printf(m, "\t\tring->tail: 0x%08x\n", @@ -1619,13 +1619,6 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) return total; } -static bool match_ring(struct i915_request *rq) -{ - u32 ring = ENGINE_READ(rq->engine, RING_START); - - return ring == i915_ggtt_offset(rq->ring->vma); -} - struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine) { @@ -1665,11 +1658,7 @@ intel_engine_find_active_request(struct intel_engine_cs *engine) continue; if (!i915_request_started(request)) - continue; - - /* More than one preemptible request may match! */ - if (!match_ring(request)) - continue; + break; active = request; break; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 8cda1b7e17ba..438637996ab5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -24,33 +24,42 @@ unsigned int intel_ring_update_space(struct intel_ring *ring) int intel_ring_pin(struct intel_ring *ring) { struct i915_vma *vma = ring->vma; - unsigned int flags; void *addr; int ret; if (atomic_fetch_inc(&ring->pin_count)) return 0; - /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ - flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); + if (!(ring->flags & INTEL_RING_CREATE_INTERNAL)) { + unsigned int pin; - if (vma->obj->stolen) - flags |= PIN_MAPPABLE; - else - flags |= PIN_HIGH; + /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ + pin |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); - ret = i915_ggtt_pin(vma, 0, flags); - if (unlikely(ret)) - goto err_unpin; + if (vma->obj->stolen) + pin |= PIN_MAPPABLE; + else + pin |= PIN_HIGH; - if (i915_vma_is_map_and_fenceable(vma)) - addr = (void __force *)i915_vma_pin_iomap(vma); - else - addr = i915_gem_object_pin_map(vma->obj, - i915_coherent_map_type(vma->vm->i915)); - if (IS_ERR(addr)) { - ret = PTR_ERR(addr); - goto err_ring; + ret = i915_ggtt_pin(vma, 0, pin); + if (unlikely(ret)) + goto err_unpin; + + if (i915_vma_is_map_and_fenceable(vma)) + addr = (void __force *)i915_vma_pin_iomap(vma); + else + addr = i915_gem_object_pin_map(vma->obj, + i915_coherent_map_type(vma->vm->i915)); + if (IS_ERR(addr)) { + ret = PTR_ERR(addr); + goto err_ring; + } + } else { + addr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); + if (IS_ERR(addr)) { + ret = PTR_ERR(addr); + goto err_ring; + } } i915_vma_make_unshrinkable(vma); @@ -91,10 +100,12 @@ void intel_ring_unpin(struct intel_ring *ring) i915_gem_object_unpin_map(vma->obj); i915_vma_make_purgeable(vma); - i915_vma_unpin(vma); + if (!(ring->flags & INTEL_RING_CREATE_INTERNAL)) + i915_vma_unpin(vma); } -static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) +static struct i915_vma * +create_ring_vma(struct i915_ggtt *ggtt, int size, unsigned int flags) { struct i915_address_space *vm = &ggtt->vm; struct drm_i915_private *i915 = vm->i915; @@ -102,7 +113,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) struct i915_vma *vma; obj = ERR_PTR(-ENODEV); - if (i915_ggtt_has_aperture(ggtt)) + if (!(flags & INTEL_RING_CREATE_INTERNAL) && + i915_ggtt_has_aperture(ggtt)) obj = i915_gem_object_create_stolen(i915, size); if (IS_ERR(obj)) obj = i915_gem_object_create_internal(i915, size); @@ -128,12 +140,14 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size) } struct intel_ring * -intel_engine_create_ring(struct intel_engine_cs *engine, int size) +intel_engine_create_ring(struct intel_engine_cs *engine, unsigned int size) { struct drm_i915_private *i915 = engine->i915; + unsigned int flags = size & GENMASK(11, 0); struct intel_ring *ring; struct i915_vma *vma; + size ^= flags; GEM_BUG_ON(!is_power_of_2(size)); GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); @@ -142,8 +156,10 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size) return ERR_PTR(-ENOMEM); kref_init(&ring->ref); + ring->size = size; ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(size); + ring->flags = flags; /* * Workaround an erratum on the i830 which causes a hang if @@ -156,11 +172,12 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size) intel_ring_update_space(ring); - vma = create_ring_vma(engine->gt->ggtt, size); + vma = create_ring_vma(engine->gt->ggtt, size, flags); if (IS_ERR(vma)) { kfree(ring); return ERR_CAST(vma); } + ring->vma = vma; return ring; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h index cc0ebca65167..d022fa209325 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.h +++ b/drivers/gpu/drm/i915/gt/intel_ring.h @@ -9,12 +9,14 @@ #include "i915_gem.h" /* GEM_BUG_ON */ #include "i915_request.h" +#include "i915_vma.h" #include "intel_ring_types.h" struct intel_engine_cs; struct intel_ring * -intel_engine_create_ring(struct intel_engine_cs *engine, int size); +intel_engine_create_ring(struct intel_engine_cs *engine, unsigned int size); +#define INTEL_RING_CREATE_INTERNAL BIT(0) u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords); int intel_ring_cacheline_align(struct i915_request *rq); @@ -137,4 +139,12 @@ __intel_ring_space(unsigned int head, unsigned int tail, unsigned int size) return (head - tail - CACHELINE_BYTES) & (size - 1); } +static inline u32 intel_ring_address(const struct intel_ring *ring) +{ + if (ring->flags & INTEL_RING_CREATE_INTERNAL) + return -1; + + return i915_ggtt_offset(ring->vma); +} + #endif /* INTEL_RING_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_types.h b/drivers/gpu/drm/i915/gt/intel_ring_types.h index 1a189ea00fd8..d927deafcb33 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_types.h +++ b/drivers/gpu/drm/i915/gt/intel_ring_types.h @@ -47,6 +47,8 @@ struct intel_ring { u32 size; u32 wrap; u32 effective_size; + + unsigned long flags; }; #endif /* INTEL_RING_TYPES_H */ -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:28 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:28 +0100 Subject: [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-4-chris@chris-wilson.co.uk> If any engine asks for the tasklet to be kicked from the CS interrupt, do so. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 ++++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +++ drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- 4 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 0cc7dd54f4f9..28edf314a319 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -60,6 +60,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir) tasklet_hi_schedule(&engine->execlists.tasklet); } +void gen2_engine_cs_irq(struct intel_engine_cs *engine) +{ + intel_engine_signal_breadcrumbs(engine); + if (intel_engine_needs_breadcrumb_tasklet(engine)) + tasklet_hi_schedule(&engine->execlists.tasklet); +} + static u32 gen11_gt_engine_identity(struct intel_gt *gt, const unsigned int bank, const unsigned int bit) @@ -273,9 +280,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); if (gt_iir & ILK_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); } static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) @@ -299,11 +306,11 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) { if (gt_iir & GT_RENDER_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); if (gt_iir & GT_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); if (gt_iir & GT_BLT_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]); + gen2_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0]); if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | GT_BSD_CS_ERROR_INTERRUPT | diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h index 886c5cf408a2..6c69cd563fe1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h @@ -9,6 +9,7 @@ #include <linux/types.h> +struct intel_engine_cs; struct intel_gt; #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ @@ -19,6 +20,8 @@ struct intel_gt; GEN8_GT_PM_IRQ | \ GEN8_GT_GUC_IRQ) +void gen2_engine_cs_irq(struct intel_engine_cs *engine); + void gen11_gt_irq_reset(struct intel_gt *gt); void gen11_gt_irq_postinstall(struct intel_gt *gt); void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2f59fc6df3c2..2e4ddc9ca09d 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1741,7 +1741,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) return; if (pm_iir & PM_VEBOX_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(gt->engine[VECS0]); + gen2_engine_cs_irq(gt->engine[VECS0]); if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8e823ba25f5f..b64f3b3bca70 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3686,7 +3686,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i8xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -3791,7 +3791,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) I915_WRITE(GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); @@ -3933,10 +3933,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) I915_WRITE(GEN2_IIR, iir); if (iir & I915_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); if (iir & I915_BSD_USER_INTERRUPT) - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); + gen2_engine_cs_irq(dev_priv->gt.engine[VCS0]); if (iir & I915_MASTER_ERROR_INTERRUPT) i9xx_error_irq_handler(dev_priv, eir, eir_stuck); -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:34 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:34 +0100 Subject: [Intel-gfx] [PATCH 10/10] drm/i915/gt: Enable ring scheduling for gen6/7 In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-10-chris@chris-wilson.co.uk> Switch over from FIFO global submission to the priority-sorted topographical scheduler. At the cost of more busy work on the CPU to keep the GPU supplied with the next packet of requests, this allows us to reorder requests around submission stalls. This also enables the timer based RPS, with the exception of Valleyview who's PCU doesn't take kindly to our interference. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/gt/intel_rps.c | 6 ++---- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index b81978890641..bb57687aea99 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -94,7 +94,7 @@ static int live_nop_switch(void *arg) rq = i915_request_get(this); i915_request_add(this); } - if (i915_request_wait(rq, 0, HZ / 5) < 0) { + if (i915_request_wait(rq, 0, HZ) < 0) { pr_err("Failed to populated %d contexts\n", nctx); intel_gt_set_wedged(&i915->gt); i915_request_put(rq); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4b36378af119..2312e8313325 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -790,6 +790,8 @@ int intel_engines_init(struct intel_gt *gt) if (HAS_EXECLISTS(gt->i915)) setup = intel_execlists_submission_setup; + else if (INTEL_GEN(gt->i915) >= 6) + setup = intel_ring_scheduler_setup; else setup = intel_ring_submission_setup; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2e4ddc9ca09d..22882c2953da 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1053,9 +1053,7 @@ static bool gen6_rps_enable(struct intel_rps *rps) intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000); intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10); - rps->pm_events = (GEN6_PM_RP_UP_THRESHOLD | - GEN6_PM_RP_DOWN_THRESHOLD | - GEN6_PM_RP_DOWN_TIMEOUT); + rps->pm_events = GEN6_PM_RP_UP_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD; return rps_reset(rps); } @@ -1362,7 +1360,7 @@ void intel_rps_enable(struct intel_rps *rps) GEM_BUG_ON(rps->efficient_freq < rps->min_freq); GEM_BUG_ON(rps->efficient_freq > rps->max_freq); - if (has_busy_stats(rps)) + if (has_busy_stats(rps) && !IS_VALLEYVIEW(i915)) intel_rps_set_timer(rps); else if (INTEL_GEN(i915) >= 6) intel_rps_set_interrupts(rps); -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:32 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:32 +0100 Subject: [Intel-gfx] [PATCH 08/10] drm/i915/gt: Enable busy-stats for ring-scheduler In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-8-chris@chris-wilson.co.uk> Couple up the context in/out accounting to record how long each engine is busy handling requests. This is exposed to userspace for more accurate measurements, and also enables our soft-rps timer. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------ .../gpu/drm/i915/gt/intel_ring_scheduler.c | 4 + drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 90 +++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ 5 files changed, 149 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include <linux/atomic.h> +#include <linux/ktime.h> +#include <linux/seqlock.h> + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d55a5e0466e5..36e2ce4ac2fa 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1187,39 +1188,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c index c8cd435d1c51..aaff554865b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -9,6 +9,7 @@ #include "i915_drv.h" #include "intel_context.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -59,6 +60,7 @@ static struct i915_request * schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) { __intel_gt_pm_get(engine->gt); + intel_engine_context_in(engine); return i915_request_get(rq); } @@ -71,6 +73,7 @@ schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) intel_engine_add_retire(engine, ce->timeline); i915_request_put(rq); + intel_engine_context_out(engine); intel_gt_pm_put_async(engine->gt); } @@ -747,6 +750,7 @@ int intel_ring_scheduler_setup(struct intel_engine_cs *engine) engine->legacy.ring = ring; engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; + engine->flags |= I915_ENGINE_SUPPORTS_STATS; /* Finally, take ownership and responsibility for cleanup! */ engine->release = ring_release; diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..fef9709b7cfa 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,95 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t dt, de; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + break; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + break; + } + + preempt_disable(); + dt = ktime_get(); + de = intel_engine_get_busy_time(engine); + udelay(100); + dt = ktime_sub(ktime_get(), dt); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + preempt_enable(); + if (100 * de < 95 * dt) { + pr_err("%s: reported only %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + igt_spinner_fini(&spin); + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +166,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:27 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:27 +0100 Subject: [Intel-gfx] [PATCH 03/10] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-3-chris@chris-wilson.co.uk> This was removed in commit 478ffad6d690 ("drm/i915: drop engine_pin/unpin_breadcrumbs_irq") as the last user had been removed, but now there is a promise of a new user in the next patch. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c index d907d538176e..03c14ab86d95 100644 --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c @@ -220,6 +220,28 @@ static void signal_irq_work(struct irq_work *work) } } +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine) +{ + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + spin_lock_irq(&b->irq_lock); + if (!b->irq_enabled++) + irq_enable(engine); + GEM_BUG_ON(!b->irq_enabled); /* no overflow! */ + spin_unlock_irq(&b->irq_lock); +} + +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine) +{ + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + spin_lock_irq(&b->irq_lock); + GEM_BUG_ON(!b->irq_enabled); /* no underflow! */ + if (!--b->irq_enabled) + irq_disable(engine); + spin_unlock_irq(&b->irq_lock); +} + static bool __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b) { struct intel_engine_cs *engine = diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..043462b6ce1f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -226,6 +226,9 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine); void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine); +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine); + void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); static inline void -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:31 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:31 +0100 Subject: [Intel-gfx] [PATCH 07/10] drm/i915/gt: Infrastructure for ring scheduling In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-7-chris@chris-wilson.co.uk> Build a bare bones scheduler to sit on top the global legacy ringbuffer submission. This virtual execlists scheme should be applicable to all older platforms. A key problem we have with the legacy ring buffer submission is that it only allows for FIFO queuing. All clients share the global request queue and must contend for its lock when submitting. As any client may need to wait for external events, all clients must then wait. However, if we stage each client into their own virtual ringbuffer with their own timelines, we can copy the client requests into the global ringbuffer only when they are ready, reordering the submission around stalls. Furthermore, the ability to reorder gives us rudimentarily priority sorting -- although without preemption support, once something is on the GPU it stays on the GPU, and so it is still possible for a hog to delay a high priority request (such as updating the display). However, it does means that in keeping a short submission queue, the high priority request will be next. This design resembles the old guc submission scheduler, for reordering requests onto a global workqueue. The implementation uses the MI_USER_INTERRUPT at the end of every request to track completion, so is more interrupt happy than execlists [which has an interrupt for each context event, albeit two]. Our interrupts on these system are relatively heavy, and in the past we have been able to completely starve Sandybrige by the interrupt traffic. Our interrupt handlers are being much better (in part offloading the work to bottom halves leaving the interrupt itself only dealing with acking the registers) but we can still see the impact of starvation in the uneven submission latency on a saturated system. Overall though, the short sumission queues and extra interrupts do not appear to be affecting throughput (+-10%, some tasks even improve to the reduced request overheads) and improve latency. [Which is a massive improvement since the introduction of Sandybridge!] Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_engine.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + .../gpu/drm/i915/gt/intel_ring_scheduler.c | 760 ++++++++++++++++++ .../gpu/drm/i915/gt/intel_ring_submission.c | 13 +- .../gpu/drm/i915/gt/intel_ring_submission.h | 16 + 6 files changed, 786 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_ring_scheduler.c create mode 100644 drivers/gpu/drm/i915/gt/intel_ring_submission.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 41a27fd5dbc7..6d98a74da41e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -109,6 +109,7 @@ gt-y += \ gt/intel_renderstate.o \ gt/intel_reset.o \ gt/intel_ring.o \ + gt/intel_ring_scheduler.o \ gt/intel_ring_submission.o \ gt/intel_rps.o \ gt/intel_sseu.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 043462b6ce1f..08176117757e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -209,6 +209,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine); int intel_engine_resume(struct intel_engine_cs *engine); int intel_ring_submission_setup(struct intel_engine_cs *engine); +int intel_ring_scheduler_setup(struct intel_engine_cs *engine); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 073c3769e8cc..5d72690fd83e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -359,6 +359,7 @@ struct intel_engine_cs { struct { struct intel_ring *ring; struct intel_timeline *timeline; + struct intel_context *context; } legacy; /* diff --git a/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c new file mode 100644 index 000000000000..c8cd435d1c51 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_ring_scheduler.c @@ -0,0 +1,760 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +#include <linux/log2.h> + +#include <drm/i915_drm.h> + +#include "i915_drv.h" +#include "intel_context.h" +#include "intel_gt.h" +#include "intel_gt_pm.h" +#include "intel_gt_requests.h" +#include "intel_reset.h" +#include "intel_ring.h" +#include "intel_ring_submission.h" +#include "shmem_utils.h" + +/* + * Rough estimate of the typical request size, performing a flush, + * set-context and then emitting the batch. + */ +#define LEGACY_REQUEST_SIZE 200 + +static inline int rq_prio(const struct i915_request *rq) +{ + return rq->sched.attr.priority; +} + +static inline struct i915_priolist *to_priolist(struct rb_node *rb) +{ + return rb_entry(rb, struct i915_priolist, node); +} + +static inline int queue_prio(struct rb_node *rb) +{ + return rb ? to_priolist(rb)->priority : INT_MIN; +} + +static inline bool reset_in_progress(const struct intel_engine_execlists *el) +{ + return unlikely(!__tasklet_is_enabled(&el->tasklet)); +} + +static void +set_current_context(struct intel_context **ptr, struct intel_context *ce) +{ + if (ce) + intel_context_get(ce); + + ce = xchg(ptr, ce); + + if (ce) + intel_context_put(ce); +} + +static struct i915_request * +schedule_in(struct intel_engine_cs *engine, struct i915_request *rq) +{ + __intel_gt_pm_get(engine->gt); + return i915_request_get(rq); +} + +static void +schedule_out(struct intel_engine_cs *engine, struct i915_request *rq) +{ + struct intel_context *ce = rq->context; + + if (list_is_last_rcu(&rq->link, &ce->timeline->requests)) + intel_engine_add_retire(engine, ce->timeline); + + i915_request_put(rq); + intel_gt_pm_put_async(engine->gt); +} + +static void reset_prepare(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + unsigned long flags; + + GEM_TRACE("%s\n", engine->name); + + __tasklet_disable_sync_once(&el->tasklet); + GEM_BUG_ON(!reset_in_progress(el)); + + /* And flush any current direct submission. */ + spin_lock_irqsave(&engine->active.lock, flags); + spin_unlock_irqrestore(&engine->active.lock, flags); + + intel_ring_submission_reset_prepare(engine); +} + +static void reset_queue_priority(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + el->queue_priority_hint = queue_prio(rb_first_cached(&el->queue)); +} + +static struct i915_request * +__unwind_incomplete_requests(struct intel_engine_cs *engine) +{ + struct i915_request *rq, *rn, *active = NULL; + struct list_head *uninitialized_var(pl); + int prio = I915_PRIORITY_INVALID; + + lockdep_assert_held(&engine->active.lock); + + list_for_each_entry_safe_reverse(rq, rn, + &engine->active.requests, + sched.link) { + if (i915_request_completed(rq)) + break; + + __i915_request_unsubmit(rq); + + GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); + if (rq_prio(rq) != prio) { + prio = rq_prio(rq); + pl = i915_sched_lookup_priolist(engine, prio); + } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); + + list_move(&rq->sched.link, pl); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + + active = rq; + } + + reset_queue_priority(engine); + + return active; +} + +static inline void clear_ports(struct i915_request **ports, int count) +{ + memset_p((void **)ports, NULL, count); +} + +static void cancel_port_requests(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request * const *port; + + clear_ports(el->pending, ARRAY_SIZE(el->pending)); + for (port = xchg(&el->active, el->pending); *port; port++) + schedule_out(engine, *port); + clear_ports(el->inflight, ARRAY_SIZE(el->inflight)); + + smp_wmb(); /* complete the seqlock for execlists_active() */ + WRITE_ONCE(el->active, el->inflight); +} + +static void __ring_rewind(struct intel_engine_cs *engine, bool stalled) +{ + struct i915_request *rq; + + rq = __unwind_incomplete_requests(engine); + if (rq && i915_request_started(rq)) + __i915_request_reset(rq, stalled); + + cancel_port_requests(engine); + + /* Clear the global submission state, we will submit from scratch */ + intel_ring_reset(engine->legacy.ring, 0); + set_current_context(&engine->legacy.context, NULL); +} + +static void ring_reset_rewind(struct intel_engine_cs *engine, bool stalled) +{ + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + __ring_rewind(engine, stalled); + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void nop_submission_tasklet(unsigned long data) +{ + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + + /* The driver is wedged; don't process any more events. */ + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN); +} + +static void ring_reset_cancel(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request *rq, *rn; + unsigned long flags; + struct rb_node *rb; + + spin_lock_irqsave(&engine->active.lock, flags); + + __ring_rewind(engine, true); + + /* Mark all submitted requests as skipped. */ + list_for_each_entry(rq, &engine->active.requests, sched.link) { + i915_request_set_error_once(rq, -EIO); + i915_request_mark_complete(rq); + } + + /* Flush the queued requests to the timeline list (for retiring). */ + while ((rb = rb_first_cached(&el->queue))) { + struct i915_priolist *p = to_priolist(rb); + int i; + + priolist_for_each_request_consume(rq, rn, p, i) { + i915_request_set_error_once(rq, -EIO); + i915_request_mark_complete(rq); + __i915_request_submit(rq); + } + + rb_erase_cached(&p->node, &el->queue); + i915_priolist_free(p); + } + + el->queue_priority_hint = INT_MIN; + el->queue = RB_ROOT_CACHED; + + /* Remaining _unready_ requests will be nop'ed when submitted */ + + GEM_BUG_ON(__tasklet_is_enabled(&el->tasklet)); + el->tasklet.func = nop_submission_tasklet; + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void reset_finish(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + intel_ring_submission_reset_finish(engine); + + if (__tasklet_enable(&el->tasklet)) + tasklet_hi_schedule(&el->tasklet); +} + +static u32 *ring_map(struct intel_ring *ring, u32 len) +{ + u32 *va; + + if (unlikely(ring->tail + len > ring->effective_size)) { + memset(ring->vaddr + ring->tail, 0, ring->size - ring->tail); + ring->tail = 0; + } + + va = ring->vaddr + ring->tail; + ring->tail = intel_ring_wrap(ring, ring->tail + len); + + return va; +} + +static inline u32 *ring_map_dw(struct intel_ring *ring, u32 len) +{ + return ring_map(ring, len * sizeof(u32)); +} + +static void ring_copy(struct intel_ring *dst, + const struct intel_ring *src, + u32 start, u32 end) +{ + unsigned int len; + void *out; + + len = end - start; + if (end < start) + len += src->size; + out = ring_map(dst, len); + + if (end < start) { + len = src->size - start; + memcpy(out, src->vaddr + start, len); + out += len; + start = 0; + } + + memcpy(out, src->vaddr + start, end - start); +} + +static void switch_context(struct intel_ring *ring, struct i915_request *rq) +{ +} + +static struct i915_request *ring_submit(struct i915_request *rq) +{ + struct intel_ring *ring = rq->engine->legacy.ring; + + __i915_request_submit(rq); + + if (rq->engine->legacy.context != rq->context) { + switch_context(ring, rq); + set_current_context(&rq->engine->legacy.context, rq->context); + } + + ring_copy(ring, rq->ring, rq->head, rq->tail); + return rq; +} + +static struct i915_request ** +copy_active(struct i915_request **port, struct i915_request * const *active) +{ + while (*active) + *port++ = *active++; + + return port; +} + +static void __dequeue(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request ** const last_port = el->pending + el->port_mask; + struct i915_request **port, *last; + struct rb_node *rb; + + lockdep_assert_held(&engine->active.lock); + + port = copy_active(el->pending, el->active); + if (port > last_port) + return; + + last = NULL; + while ((rb = rb_first_cached(&el->queue))) { + struct i915_priolist *p = to_priolist(rb); + struct i915_request *rq, *rn; + int i; + + priolist_for_each_request_consume(rq, rn, p, i) { + GEM_BUG_ON(rq == last); + if (last && rq->context != last->context) { + if (port == last_port) + goto done; + + *port++ = schedule_in(engine, last); + } + + last = ring_submit(rq); + } + + rb_erase_cached(&p->node, &el->queue); + i915_priolist_free(p); + } + +done: + el->queue_priority_hint = queue_prio(rb); + if (last) { + *port++ = schedule_in(engine, last); + *port++ = NULL; + WRITE_ONCE(el->active, el->pending); + + wmb(); /* paranoid flush of WCB before RING_TAIL write */ + ENGINE_WRITE(engine, RING_TAIL, engine->legacy.ring->tail); + memcpy(el->inflight, el->pending, + (port - el->pending) * sizeof(*port)); + + WRITE_ONCE(el->active, el->inflight); + GEM_BUG_ON(!*el->active); + } +} + +static void __submission_tasklet(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request *rq; + + while ((rq = *el->active)) { + if (!i915_request_completed(rq)) + break; + + schedule_out(engine, rq); + el->active++; + } + + if (el->queue_priority_hint != INT_MIN) + __dequeue(engine); +} + +static void submission_tasklet(unsigned long data) +{ + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + __submission_tasklet(engine); + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void queue_request(struct intel_engine_cs *engine, + struct i915_request *rq) +{ + GEM_BUG_ON(!list_empty(&rq->sched.link)); + list_add_tail(&rq->sched.link, + i915_sched_lookup_priolist(engine, rq_prio(rq))); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); +} + +static void __submit_queue_imm(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + + if (reset_in_progress(el)) + return; /* defer until we restart the engine following reset */ + + __submission_tasklet(engine); +} + +static void submit_queue(struct intel_engine_cs *engine, + const struct i915_request *rq) +{ + struct intel_engine_execlists *el = &engine->execlists; + + if (rq_prio(rq) <= el->queue_priority_hint) + return; + + el->queue_priority_hint = rq_prio(rq); + __submit_queue_imm(engine); +} + +static void submit_request(struct i915_request *rq) +{ + struct intel_engine_cs *engine = rq->engine; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + + queue_request(engine, rq); + + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); + GEM_BUG_ON(list_empty(&rq->sched.link)); + + submit_queue(engine, rq); + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + +static void submission_park(struct intel_engine_cs *engine) +{ + GEM_BUG_ON(engine->execlists.queue_priority_hint != INT_MIN); + intel_engine_unpin_breadcrumbs_irq(engine); + submission_tasklet((unsigned long)engine); /* drain the submit queue */ +} + +static void submission_unpark(struct intel_engine_cs *engine) +{ + intel_engine_pin_breadcrumbs_irq(engine); +} + +static void ring_context_destroy(struct kref *ref) +{ + struct intel_context *ce = container_of(ref, typeof(*ce), ref); + + GEM_BUG_ON(intel_context_is_pinned(ce)); + + if (ce->state) + i915_vma_put(ce->state); + if (test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) + intel_ring_put(ce->ring); + + intel_context_fini(ce); + intel_context_free(ce); +} + +static void ring_context_unpin(struct intel_context *ce) +{ +} + +static int alloc_context_vma(struct intel_context *ce) + +{ + struct intel_engine_cs *engine = ce->engine; + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + int err; + + obj = i915_gem_object_create_shmem(engine->i915, engine->context_size); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + /* + * Try to make the context utilize L3 as well as LLC. + * + * On VLV we don't have L3 controls in the PTEs so we + * shouldn't touch the cache level, especially as that + * would make the object snooped which might have a + * negative performance impact. + * + * Snooping is required on non-llc platforms in execlist + * mode, but since all GGTT accesses use PAT entry 0 we + * get snooping anyway regardless of cache_level. + * + * This is only applicable for Ivy Bridge devices since + * later platforms don't have L3 control bits in the PTE. + */ + if (IS_IVYBRIDGE(engine->i915)) + i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC); + + if (engine->default_state) { + void *vaddr; + + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); + if (IS_ERR(vaddr)) { + err = PTR_ERR(vaddr); + goto err_obj; + } + + shmem_read(engine->default_state, 0, + vaddr, engine->context_size); + __set_bit(CONTEXT_VALID_BIT, &ce->flags); + + i915_gem_object_flush_map(obj); + i915_gem_object_unpin_map(obj); + } + + vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto err_obj; + } + + ce->state = vma; + return 0; + +err_obj: + i915_gem_object_put(obj); + return err; +} + +static int alloc_timeline(struct intel_context *ce) +{ + struct intel_engine_cs *engine = ce->engine; + struct intel_timeline *tl; + struct i915_vma *hwsp; + + /* + * Use the static global HWSP for the kernel context, and + * a dynamically allocated cacheline for everyone else. + */ + hwsp = NULL; + if (unlikely(intel_context_is_barrier(ce))) + hwsp = engine->status_page.vma; + + tl = intel_timeline_create(engine->gt, hwsp); + if (IS_ERR(tl)) + return PTR_ERR(tl); + + ce->timeline = tl; + return 0; +} + +static int ring_context_alloc(struct intel_context *ce) +{ + struct intel_engine_cs *engine = ce->engine; + struct intel_ring *ring; + int err; + + GEM_BUG_ON(ce->state); + if (engine->context_size) { + err = alloc_context_vma(ce); + if (err) + return err; + } + + if (!ce->timeline) { + err = alloc_timeline(ce); + if (err) + goto err_vma; + } + + ring = intel_engine_create_ring(engine, + (unsigned long)ce->ring | + INTEL_RING_CREATE_INTERNAL); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto err_timeline; + } + ce->ring = ring; + + return 0; + +err_timeline: + intel_timeline_put(ce->timeline); +err_vma: + if (ce->state) { + i915_vma_put(ce->state); + ce->state = NULL; + } + return err; +} + +static int ring_context_pin(struct intel_context *ce) +{ + return 0; +} + +static void ring_context_reset(struct intel_context *ce) +{ + intel_ring_reset(ce->ring, 0); + clear_bit(CONTEXT_VALID_BIT, &ce->flags); +} + +static const struct intel_context_ops ring_context_ops = { + .alloc = ring_context_alloc, + + .pin = ring_context_pin, + .unpin = ring_context_unpin, + + .enter = intel_context_enter_engine, + .exit = intel_context_exit_engine, + + .reset = ring_context_reset, + .destroy = ring_context_destroy, +}; + +static int ring_request_alloc(struct i915_request *rq) +{ + int ret; + + GEM_BUG_ON(!intel_context_is_pinned(rq->context)); + + /* + * Flush enough space to reduce the likelihood of waiting after + * we start building the request - in which case we will just + * have to repeat work. + */ + rq->reserved_space += LEGACY_REQUEST_SIZE; + + /* Unconditionally invalidate GPU caches and TLBs. */ + ret = rq->engine->emit_flush(rq, EMIT_INVALIDATE); + if (ret) + return ret; + + rq->reserved_space -= LEGACY_REQUEST_SIZE; + return 0; +} + +static void set_default_submission(struct intel_engine_cs *engine) +{ + engine->submit_request = submit_request; + engine->execlists.tasklet.func = submission_tasklet; +} + +static void ring_release(struct intel_engine_cs *engine) +{ + intel_engine_cleanup_common(engine); + + set_current_context(&engine->legacy.context, NULL); + + intel_ring_unpin(engine->legacy.ring); + intel_ring_put(engine->legacy.ring); +} + +static void setup_irq(struct intel_engine_cs *engine) +{ +} + +static void setup_common(struct intel_engine_cs *engine) +{ + struct drm_i915_private *i915 = engine->i915; + + /* gen8+ are only supported with execlists */ + GEM_BUG_ON(INTEL_GEN(i915) >= 8); + GEM_BUG_ON(INTEL_GEN(i915) < 8); + + setup_irq(engine); + + engine->park = submission_park; + engine->unpark = submission_unpark; + engine->schedule = i915_schedule; + + engine->resume = intel_ring_submission_resume; + engine->reset.prepare = reset_prepare; + engine->reset.rewind = ring_reset_rewind; + engine->reset.cancel = ring_reset_cancel; + engine->reset.finish = reset_finish; + + engine->cops = &ring_context_ops; + engine->request_alloc = ring_request_alloc; + + engine->set_default_submission = set_default_submission; +} + +static void setup_rcs(struct intel_engine_cs *engine) +{ +} + +static void setup_vcs(struct intel_engine_cs *engine) +{ +} + +static void setup_bcs(struct intel_engine_cs *engine) +{ +} + +static void setup_vecs(struct intel_engine_cs *engine) +{ + GEM_BUG_ON(!IS_HASWELL(engine->i915)); +} + +static unsigned int global_ring_size(void) +{ + /* Enough space to hold 2 clients and the context switch */ + return roundup_pow_of_two(EXECLIST_MAX_PORTS * SZ_16K + SZ_4K); +} + +int intel_ring_scheduler_setup(struct intel_engine_cs *engine) +{ + struct intel_ring *ring; + int err; + + GEM_BUG_ON(HAS_EXECLISTS(engine->i915)); + + tasklet_init(&engine->execlists.tasklet, + submission_tasklet, (unsigned long)engine); + + setup_common(engine); + + switch (engine->class) { + case RENDER_CLASS: + setup_rcs(engine); + break; + case VIDEO_DECODE_CLASS: + setup_vcs(engine); + break; + case COPY_ENGINE_CLASS: + setup_bcs(engine); + break; + case VIDEO_ENHANCEMENT_CLASS: + setup_vecs(engine); + break; + default: + MISSING_CASE(engine->class); + return -ENODEV; + } + + ring = intel_engine_create_ring(engine, global_ring_size()); + if (IS_ERR(ring)) { + err = PTR_ERR(ring); + goto err; + } + + err = intel_ring_pin(ring); + if (err) + goto err_ring; + + GEM_BUG_ON(engine->legacy.ring); + engine->legacy.ring = ring; + + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; + + /* Finally, take ownership and responsibility for cleanup! */ + engine->release = ring_release; + return 0; + +err_ring: + intel_ring_put(ring); +err: + intel_engine_cleanup_common(engine); + return err; +} diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 68a08486fc87..4cf7c6486223 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -36,6 +36,7 @@ #include "intel_gt.h" #include "intel_reset.h" #include "intel_ring.h" +#include "intel_ring_submission.h" #include "shmem_utils.h" /* Rough estimate of the typical request size, performing a flush, @@ -214,7 +215,7 @@ static void set_pp_dir(struct intel_engine_cs *engine) } } -static int xcs_resume(struct intel_engine_cs *engine) +int intel_ring_submission_resume(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; struct intel_ring *ring = engine->legacy.ring; @@ -318,7 +319,7 @@ static int xcs_resume(struct intel_engine_cs *engine) return ret; } -static void reset_prepare(struct intel_engine_cs *engine) +void intel_ring_submission_reset_prepare(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; const u32 base = engine->mmio_base; @@ -425,7 +426,7 @@ static void reset_rewind(struct intel_engine_cs *engine, bool stalled) spin_unlock_irqrestore(&engine->active.lock, flags); } -static void reset_finish(struct intel_engine_cs *engine) +void intel_ring_submission_reset_finish(struct intel_engine_cs *engine) { } @@ -1056,11 +1057,11 @@ static void setup_common(struct intel_engine_cs *engine) setup_irq(engine); - engine->resume = xcs_resume; - engine->reset.prepare = reset_prepare; + engine->resume = intel_ring_submission_resume; + engine->reset.prepare = intel_ring_submission_reset_prepare; engine->reset.rewind = reset_rewind; engine->reset.cancel = reset_cancel; - engine->reset.finish = reset_finish; + engine->reset.finish = intel_ring_submission_reset_finish; engine->cops = &ring_context_ops; engine->request_alloc = ring_request_alloc; diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.h b/drivers/gpu/drm/i915/gt/intel_ring_submission.h new file mode 100644 index 000000000000..701eb033e055 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_RING_SUBMISSION_H__ +#define __INTEL_RING_SUBMISSION_H__ + +struct intel_engine_cs; + +void intel_ring_submission_reset_prepare(struct intel_engine_cs *engine); +void intel_ring_submission_reset_finish(struct intel_engine_cs *engine); + +int intel_ring_submission_resume(struct intel_engine_cs *engine); + +#endif /* __INTEL_RING_SUBMISSION_H__ */ -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 12:23:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 13:23:30 +0100 Subject: [Intel-gfx] [PATCH 06/10] drm/i915/gt: Use client timeline address for seqno writes In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <20200605122334.2798-6-chris@chris-wilson.co.uk> If we allow for per-client timelines, even with legacy ring submission, we open the door to a world full of possiblities [scheduling and semaphores]. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c index ce38d1bcaba3..fa11174bb13b 100644 --- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c @@ -373,11 +373,10 @@ u32 *gen7_emit_breadcrumb_rcs(struct i915_request *rq, u32 *cs) u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) { - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); + u32 addr = i915_request_active_timeline(rq)->hwsp_offset; - *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW; + *cs++ = addr | MI_FLUSH_DW_USE_GTT; *cs++ = rq->fence.seqno; *cs++ = MI_USER_INTERRUPT; @@ -391,19 +390,17 @@ u32 *gen6_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) #define GEN7_XCS_WA 32 u32 *gen7_emit_breadcrumb_xcs(struct i915_request *rq, u32 *cs) { + u32 addr = i915_request_active_timeline(rq)->hwsp_offset; int i; - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | - MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; + *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW; + *cs++ = addr | MI_FLUSH_DW_USE_GTT; *cs++ = rq->fence.seqno; for (i = 0; i < GEN7_XCS_WA; i++) { - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; + *cs++ = 0; + *cs++ = addr; *cs++ = rq->fence.seqno; } -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 5 12:38:47 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 12:38:47 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/10=5D_drm/i915/gt=3A_Set_timesli?= =?utf-8?q?cing_priority_from_queue?= In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <159136072701.18507.4090522909912855456@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue URL : https://patchwork.freedesktop.org/series/78037/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3a69666621c1 drm/i915/gt: Set timeslicing priority from queue 5e2b5f7efc76 drm/i915/gt: Always check to enable timeslicing if not submitting 2555bb3785f7 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" b5285725cfc7 drm/i915/gt: Couple tasklet scheduling for all CS interrupts 4834051a2ae5 drm/i915/gt: Support creation of 'internal' rings ea2e5e762bd4 drm/i915/gt: Use client timeline address for seqno writes 01def7b10c3d drm/i915/gt: Infrastructure for ring scheduling -:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #79: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 842 lines checked 77d4a18ad122 drm/i915/gt: Enable busy-stats for ring-scheduler -:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #13: new file mode 100644 -:200: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #200: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:47: + udelay(100); -:230: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #230: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:77: + udelay(100); total: 0 errors, 1 warnings, 2 checks, 236 lines checked af2eaeac159b drm/i915/gt: Implement ring scheduler for gen6/7 -:68: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #68: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:320: + *cs++ = i915_mmio_reg_offset( -:70: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #70: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:322: + *cs++ = _MASKED_BIT_ENABLE( -:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #105: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:357: + *cs++ = _MASKED_BIT_DISABLE( total: 0 errors, 0 warnings, 3 checks, 506 lines checked 49e963cbf709 drm/i915/gt: Enable ring scheduling for gen6/7 From patchwork at emeril.freedesktop.org Fri Jun 5 12:39:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 12:39:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/10=5D_drm/i915/gt=3A_Set_timeslicing?= =?utf-8?q?_priority_from_queue?= In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <159136079864.18507.13900244389846053124@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue URL : https://patchwork.freedesktop.org/series/78037/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From daniel.vetter at ffwll.ch Fri Jun 5 12:41:34 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 5 Jun 2020 14:41:34 +0200 Subject: [Intel-gfx] [PATCH 13/18] drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail In-Reply-To: <e0bfd872-5d38-6718-a23d-6b14b3c14f25@amd.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-14-daniel.vetter@ffwll.ch> <e0bfd872-5d38-6718-a23d-6b14b3c14f25@amd.com> Message-ID: <CAKMK7uG6VN93ZS3Rbi6edvDAMefXJ6CotMx5j916VcUy2nuvqQ@mail.gmail.com> On Fri, Jun 5, 2020 at 10:30 AM Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com> wrote: > > Hi Daniel, > > On 04/06/2020 10:12, Daniel Vetter wrote: > [...] > > @@ -6910,7 +6910,11 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, > > * explicitly on fences instead > > * and in general should be called for > > * blocking commit to as per framework helpers > > + * > > + * Yes, this deadlocks, since you're calling dma_resv_lock in a > > + * path that leads to a dma_fence_signal(). Don't do that. > > */ > > +#if 0 > > r = amdgpu_bo_reserve(abo, true); > > if (unlikely(r != 0)) > > DRM_ERROR("failed to reserve buffer before flip\n"); > > @@ -6920,6 +6924,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, > > tmz_surface = amdgpu_bo_encrypted(abo); > > > > amdgpu_bo_unreserve(abo); > > +#endif > > + /* > > + * this races anyway, so READ_ONCE isn't any better or worse > > + * than the stuff above. Except the stuff above can deadlock. > > + */ > > + tiling_flags = READ_ONCE(abo->tiling_flags); > > With this change "tmz_surface" won't be initialized properly. > Adding the following line should fix it: > > tmz_surface = READ_ONCE(abo->flags) & AMDGPU_GEM_CREATE_ENCRYPTED; So to make this clear, I'm not really proposing to fix up all the drivers in detail. There's a lot more bugs in all the other drivers, I'm pretty sure. The driver fixups really are just quick hacks to illustrate the problem, and at least in some cases, maybe illustrate a possible solution. For the real fixes I think this needs driver teams working on this, and make sure it's all solid. I can help a bit with review (especially for placing the annotations, e.g. the one I put in cs_submit() annotates a bit too much), but that's it. Also I think the patch is from before tmz landed, and I just blindly rebased over it :-) -Daniel > > > Pierre-Eric > > > > > > fill_dc_plane_info_and_addr( > > dm->adev, new_plane_state, tiling_flags, > > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Fri Jun 5 12:53:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 12:53:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915=3A_Discard_a_misplaced_GGT?= =?utf-8?q?T_vma?= In-Reply-To: <20200605105646.24300-1-chris@chris-wilson.co.uk> References: <20200605105646.24300-1-chris@chris-wilson.co.uk> Message-ID: <159136163859.18509.16185250988031168662@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915: Discard a misplaced GGTT vma URL : https://patchwork.freedesktop.org/series/78033/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17884_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17884_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl4/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl7/igt at gem_exec_suspend@basic-s3.html * igt at gem_tiled_pread_basic: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl3/igt at gem_tiled_pread_basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-apl7/igt at gem_tiled_pread_basic.html * igt at i915_suspend@forcewake: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#58] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk8/igt at i915_suspend@forcewake.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-glk8/igt at i915_suspend@forcewake.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-apl3/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_color@pipe-a-ctm-0-5.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl2/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_crc@pipe-c-cursor-128x42-sliding: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-128x42-sliding.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl3/igt at kms_cursor_crc@pipe-c-cursor-128x42-sliding.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#49]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#173]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb3/igt at kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-iclb3/igt at kms_psr@psr2_cursor_blt.html * igt at kms_rmfb@rmfb-ioctl: - shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at kms_rmfb@rmfb-ioctl.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-snb1/igt at kms_rmfb@rmfb-ioctl.html * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#402]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-tglb8/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-apl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * {igt at gem_exec_schedule@preempt at vecs0}: - shard-skl: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +5 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl8/igt at gem_exec_schedule@preempt at vecs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl8/igt at gem_exec_schedule@preempt at vecs0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-glk8/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][35] ([i915#1436] / [i915#716]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl3/igt at gen9_exec_parse@allowed-all.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][37] ([i915#93] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][39] ([i915#128]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl6/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][41] ([i915#79]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-glk6/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-glk9/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][45] ([i915#95]) -> [PASS][46] +18 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-apl8/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][47] ([i915#1188]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_hdr@bpc-switch.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl7/igt at kms_hdr@bpc-switch.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +5 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at kms_psr@psr2_suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][53] ([i915#31]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl2/igt at kms_setmode@basic.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][55] ([i915#1542]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-hsw5/igt at perf@polling-parameterized.html #### Warnings #### * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][57] ([fdo#110321]) -> [TIMEOUT][58] ([i915#1319]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl6/igt at kms_content_protection@legacy.html - shard-apl: [TIMEOUT][59] ([i915#1319] / [i915#1635]) -> [FAIL][60] ([fdo#110321] / [fdo#110336]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl3/igt at kms_content_protection@legacy.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-apl2/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][61] ([fdo#110321] / [i915#95]) -> [TIMEOUT][62] ([i915#1319] / [i915#1635]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-apl1/igt at kms_content_protection@lic.html - shard-kbl: [TIMEOUT][63] ([i915#1319]) -> [TIMEOUT][64] ([i915#1319] / [i915#1958]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_content_protection@lic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl4/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][65] ([fdo#110321] / [i915#95]) -> [TIMEOUT][66] ([i915#1319]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl7/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][67] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][68] ([i915#93] / [i915#95]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-WARN][69] ([i915#1982]) -> [FAIL][70] ([fdo#108145] / [i915#265]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17884 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17884: 8f309332415b32d03c96f11a8a4b451ac66f2742 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17884/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 13:00:47 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 13:00:47 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/10=5D_drm/i915/gt=3A_Set_timeslicing_pr?= =?utf-8?q?iority_from_queue?= In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <159136204707.18506.8686832967483329332@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue URL : https://patchwork.freedesktop.org/series/78037/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17885 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/index.html Known issues ------------ Here are the changes found in Patchwork_17885 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-icl-guc/igt at i915_module_load@reload.html * igt at kms_busy@basic at flip: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-tgl-y/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-byt-n2820/igt at i915_module_load@reload.html - fi-tgl-y: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-tgl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at active: - fi-whl-u: [DMESG-FAIL][15] ([i915#666]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_selftest@live at active.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-whl-u/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_busy@basic at flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1}: - fi-icl-u2: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][29] ([fdo#109271]) -> [DMESG-FAIL][30] ([i915#62] / [i915#95]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17885 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17885: 49e963cbf7098a41ba1f958aeb235b4af2166697 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 49e963cbf709 drm/i915/gt: Enable ring scheduling for gen6/7 af2eaeac159b drm/i915/gt: Implement ring scheduler for gen6/7 77d4a18ad122 drm/i915/gt: Enable busy-stats for ring-scheduler 01def7b10c3d drm/i915/gt: Infrastructure for ring scheduling ea2e5e762bd4 drm/i915/gt: Use client timeline address for seqno writes 4834051a2ae5 drm/i915/gt: Support creation of 'internal' rings b5285725cfc7 drm/i915/gt: Couple tasklet scheduling for all CS interrupts 2555bb3785f7 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" 5e2b5f7efc76 drm/i915/gt: Always check to enable timeslicing if not submitting 3a69666621c1 drm/i915/gt: Set timeslicing priority from queue == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/index.html From daniel.vetter at ffwll.ch Fri Jun 5 13:29:53 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 5 Jun 2020 15:29:53 +0200 Subject: [Intel-gfx] [PATCH] dma-fence: basic lockdep annotations In-Reply-To: <20200604081224.863494-4-daniel.vetter@ffwll.ch> References: <20200604081224.863494-4-daniel.vetter@ffwll.ch> Message-ID: <20200605132953.899664-1-daniel.vetter@ffwll.ch> Design is similar to the lockdep annotations for workers, but with some twists: - We use a read-lock for the execution/worker/completion side, so that this explicit annotation can be more liberally sprinkled around. With read locks lockdep isn't going to complain if the read-side isn't nested the same way under all circumstances, so ABBA deadlocks are ok. Which they are, since this is an annotation only. - We're using non-recursive lockdep read lock mode, since in recursive read lock mode lockdep does not catch read side hazards. And we _very_ much want read side hazards to be caught. For full details of this limitation see commit e91498589746065e3ae95d9a00b068e525eec34f Author: Peter Zijlstra <peterz at infradead.org> Date: Wed Aug 23 13:13:11 2017 +0200 locking/lockdep/selftests: Add mixed read-write ABBA tests - To allow nesting of the read-side explicit annotations we explicitly keep track of the nesting. lock_is_held() allows us to do that. - The wait-side annotation is a write lock, and entirely done within dma_fence_wait() for everyone by default. - To be able to freely annotate helper functions I want to make it ok to call dma_fence_begin/end_signalling from soft/hardirq context. First attempt was using the hardirq locking context for the write side in lockdep, but this forces all normal spinlocks nested within dma_fence_begin/end_signalling to be spinlocks. That bollocks. The approach now is to simple check in_atomic(), and for these cases entirely rely on the might_sleep() check in dma_fence_wait(). That will catch any wrong nesting against spinlocks from soft/hardirq contexts. The idea here is that every code path that's critical for eventually signalling a dma_fence should be annotated with dma_fence_begin/end_signalling. The annotation ideally starts right after a dma_fence is published (added to a dma_resv, exposed as a sync_file fd, attached to a drm_syncobj fd, or anything else that makes the dma_fence visible to other kernel threads), up to and including the dma_fence_wait(). Examples are irq handlers, the scheduler rt threads, the tail of execbuf (after the corresponding fences are visible), any workers that end up signalling dma_fences and really anything else. Not annotated should be code paths that only complete fences opportunistically as the gpu progresses, like e.g. shrinker/eviction code. The main class of deadlocks this is supposed to catch are: Thread A: mutex_lock(A); mutex_unlock(A); dma_fence_signal(); Thread B: mutex_lock(A); dma_fence_wait(); mutex_unlock(A); Thread B is blocked on A signalling the fence, but A never gets around to that because it cannot acquire the lock A. Note that dma_fence_wait() is allowed to be nested within dma_fence_begin/end_signalling sections. To allow this to happen the read lock needs to be upgraded to a write lock, which means that any other lock is acquired between the dma_fence_begin_signalling() call and the call to dma_fence_wait(), and still held, this will result in an immediate lockdep complaint. The only other option would be to not annotate such calls, defeating the point. Therefore these annotations cannot be sprinkled over the code entirely mindless to avoid false positives. Originally I hope that the cross-release lockdep extensions would alleviate the need for explicit annotations: https://lwn.net/Articles/709849/ But there's a few reasons why that's not an option: - It's not happening in upstream, since it got reverted due to too many false positives: commit e966eaeeb623f09975ef362c2866fae6f86844f9 Author: Ingo Molnar <mingo at kernel.org> Date: Tue Dec 12 12:31:16 2017 +0100 locking/lockdep: Remove the cross-release locking checks This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), while it found a number of old bugs initially, was also causing too many false positives that caused people to disable lockdep - which is arguably a worse overall outcome. - cross-release uses the complete() call to annotate the end of critical sections, for dma_fence that would be dma_fence_signal(). But we do not want all dma_fence_signal() calls to be treated as critical, since many are opportunistic cleanup of gpu requests. If these get stuck there's still the main completion interrupt and workers who can unblock everyone. Automatically annotating all dma_fence_signal() calls would hence cause false positives. - cross-release had some educated guesses for when a critical section starts, like fresh syscall or fresh work callback. This would again cause false positives without explicit annotations, since for dma_fence the critical sections only starts when we publish a fence. - Furthermore there can be cases where a thread never does a dma_fence_signal, but is still critical for reaching completion of fences. One example would be a scheduler kthread which picks up jobs and pushes them into hardware, where the interrupt handler or another completion thread calls dma_fence_signal(). But if the scheduler thread hangs, then all the fences hang, hence we need to manually annotate it. cross-release aimed to solve this by chaining cross-release dependencies, but the dependency from scheduler thread to the completion interrupt handler goes through hw where cross-release code can't observe it. In short, without manual annotations and careful review of the start and end of critical sections, cross-relese dependency tracking doesn't work. We need explicit annotations. v2: handle soft/hardirq ctx better against write side and dont forget EXPORT_SYMBOL, drivers can't use this otherwise. v3: Kerneldoc. v4: Some spelling fixes from Mika v5: Amend commit message to explain in detail why cross-release isn't the solution. Cc: Mika Kuoppala <mika.kuoppala at intel.com> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- Documentation/driver-api/dma-buf.rst | 12 +- drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ include/linux/dma-fence.h | 12 ++ 3 files changed, 182 insertions(+), 3 deletions(-) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 63dec76d1d8d..05d856131140 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects .. kernel-doc:: drivers/dma-buf/dma-buf.c :doc: cpu access -Fence Poll Support -~~~~~~~~~~~~~~~~~~ +Implicit Fence Poll Support +~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. kernel-doc:: drivers/dma-buf/dma-buf.c - :doc: fence polling + :doc: implicit fence polling Kernel Functions and Structures Reference ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -133,6 +133,12 @@ DMA Fences .. kernel-doc:: drivers/dma-buf/dma-fence.c :doc: DMA fences overview +DMA Fence Signalling Annotations +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence.c + :doc: fence signalling annotation + DMA Fences Functions Reference ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 656e9ac2d028..0005bc002529 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) } EXPORT_SYMBOL(dma_fence_context_alloc); +/** + * DOC: fence signalling annotation + * + * Proving correctness of all the kernel code around &dma_fence through code + * review and testing is tricky for a few reasons: + * + * * It is a cross-driver contract, and therefore all drivers must follow the + * same rules for lock nesting order, calling contexts for various functions + * and anything else significant for in-kernel interfaces. But it is also + * impossible to test all drivers in a single machine, hence brute-force N vs. + * N testing of all combinations is impossible. Even just limiting to the + * possible combinations is infeasible. + * + * * There is an enormous amount of driver code involved. For render drivers + * there's the tail of command submission, after fences are published, + * scheduler code, interrupt and workers to process job completion, + * and timeout, gpu reset and gpu hang recovery code. Plus for integration + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, + * and &shrinker. For modesetting drivers there's the commit tail functions + * between when fences for an atomic modeset are published, and when the + * corresponding vblank completes, including any interrupt processing and + * related workers. Auditing all that code, across all drivers, is not + * feasible. + * + * * Due to how many other subsystems are involved and the locking hierarchies + * this pulls in there is extremely thin wiggle-room for driver-specific + * differences. &dma_fence interacts with almost all of the core memory + * handling through page fault handlers via &dma_resv, dma_resv_lock() and + * dma_resv_unlock(). On the other side it also interacts through all + * allocation sites through &mmu_notifier and &shrinker. + * + * Furthermore lockdep does not handle cross-release dependencies, which means + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught + * at runtime with some quick testing. The simplest example is one thread + * waiting on a &dma_fence while holding a lock:: + * + * lock(A); + * dma_fence_wait(B); + * unlock(A); + * + * while the other thread is stuck trying to acquire the same lock, which + * prevents it from signalling the fence the previous thread is stuck waiting + * on:: + * + * lock(A); + * unlock(A); + * dma_fence_signal(B); + * + * By manually annotating all code relevant to signalling a &dma_fence we can + * teach lockdep about these dependencies, which also helps with the validation + * headache since now lockdep can check all the rules for us:: + * + * cookie = dma_fence_begin_signalling(); + * lock(A); + * unlock(A); + * dma_fence_signal(B); + * dma_fence_end_signalling(cookie); + * + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to + * annotate critical sections the following rules need to be observed: + * + * * All code necessary to complete a &dma_fence must be annotated, from the + * point where a fence is accessible to other threads, to the point where + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, + * and due to the very strict rules and many corner cases it is infeasible to + * catch these just with review or normal stress testing. + * + * * &struct dma_resv deserves a special note, since the readers are only + * protected by rcu. This means the signalling critical section starts as soon + * as the new fences are installed, even before dma_resv_unlock() is called. + * + * * The only exception are fast paths and opportunistic signalling code, which + * calls dma_fence_signal() purely as an optimization, but is not required to + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL + * which calls dma_fence_signal(), while the mandatory completion path goes + * through a hardware interrupt and possible job completion worker. + * + * * To aid composability of code, the annotations can be freely nested, as long + * as the overall locking hierarchy is consistent. The annotations also work + * both in interrupt and process context. Due to implementation details this + * requires that callers pass an opaque cookie from + * dma_fence_begin_signalling() to dma_fence_end_signalling(). + * + * * Validation against the cross driver contract is implemented by priming + * lockdep with the relevant hierarchy at boot-up. This means even just + * testing with a single device is enough to validate a driver, at least as + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are + * concerned. + */ +#ifdef CONFIG_LOCKDEP +struct lockdep_map dma_fence_lockdep_map = { + .name = "dma_fence_map" +}; + +/** + * dma_fence_begin_signalling - begin a critical DMA fence signalling section + * + * Drivers should use this to annotate the beginning of any code section + * required to eventually complete &dma_fence by calling dma_fence_signal(). + * + * The end of these critical sections are annotated with + * dma_fence_end_signalling(). + * + * Returns: + * + * Opaque cookie needed by the implementation, which needs to be passed to + * dma_fence_end_signalling(). + */ +bool dma_fence_begin_signalling(void) +{ + /* explicitly nesting ... */ + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) + return true; + + /* rely on might_sleep check for soft/hardirq locks */ + if (in_atomic()) + return true; + + /* ... and non-recursive readlock */ + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); + + return false; +} +EXPORT_SYMBOL(dma_fence_begin_signalling); + +/** + * dma_fence_end_signalling - end a critical DMA fence signalling section + * + * Closes a critical section annotation opened by dma_fence_begin_signalling(). + */ +void dma_fence_end_signalling(bool cookie) +{ + if (cookie) + return; + + lock_release(&dma_fence_lockdep_map, _RET_IP_); +} +EXPORT_SYMBOL(dma_fence_end_signalling); + +void __dma_fence_might_wait(void) +{ + bool tmp; + + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); + if (tmp) + lock_release(&dma_fence_lockdep_map, _THIS_IP_); + lock_map_acquire(&dma_fence_lockdep_map); + lock_map_release(&dma_fence_lockdep_map); + if (tmp) + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); +} +#endif + + /** * dma_fence_signal_locked - signal completion of a fence * @fence: the fence to signal @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) { unsigned long flags; int ret; + bool tmp; if (!fence) return -EINVAL; + tmp = dma_fence_begin_signalling(); + spin_lock_irqsave(fence->lock, flags); ret = dma_fence_signal_locked(fence); spin_unlock_irqrestore(fence->lock, flags); + dma_fence_end_signalling(tmp); + return ret; } EXPORT_SYMBOL(dma_fence_signal); @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) might_sleep(); + __dma_fence_might_wait(); + trace_dma_fence_wait_start(fence); if (fence->ops->wait) ret = fence->ops->wait(fence, intr, timeout); diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 3347c54f3a87..3f288f7db2ef 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) } while (1); } +#ifdef CONFIG_LOCKDEP +bool dma_fence_begin_signalling(void); +void dma_fence_end_signalling(bool cookie); +#else +static inline bool dma_fence_begin_signalling(void) +{ + return true; +} +static inline void dma_fence_end_signalling(bool cookie) {} +static inline void __dma_fence_might_wait(void) {} +#endif + int dma_fence_signal(struct dma_fence *fence); int dma_fence_signal_locked(struct dma_fence *fence); signed long dma_fence_default_wait(struct dma_fence *fence, -- 2.26.2 From patchwork at emeril.freedesktop.org Fri Jun 5 13:53:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 13:53:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BRESEND=2Cv3=2C1/3=5D_drm/i915/dp=5Fmst=3A_?= =?utf-8?q?Fix_disabling_MST_on_a_port_=28rev6=29?= In-Reply-To: <20200603211040.8190-1-imre.deak@intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> Message-ID: <159136523293.18507.17008252253062518394@emeril.freedesktop.org> == Series Details == Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6) URL : https://patchwork.freedesktop.org/series/77969/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17882_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17882_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk7/igt at gem_exec_whisper@basic-forked-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk2/igt at gem_exec_whisper@basic-forked-all.html * igt at gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at gem_mmap_gtt@cpuset-big-copy-odd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at gem_mmap_gtt@cpuset-big-copy-odd.html * igt at gem_workarounds@suspend-resume: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_workarounds@suspend-resume.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_workarounds@suspend-resume.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +9 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_big_fb@linear-32bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk4/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +17 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [PASS][17] -> [TIMEOUT][18] ([i915#1958]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#49]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_lowres@pipe-a-tiling-x: - shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at kms_plane_lowres@pipe-a-tiling-x.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_lowres@pipe-a-tiling-x.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb4/igt at kms_psr@psr2_cursor_blt.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#402]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][37] ([i915#1436] / [i915#716]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at gen9_exec_parse@allowed-all.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [INCOMPLETE][39] ([i915#155]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl6/igt at i915_suspend@debugfs-reader.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][41] ([i915#93] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_color@pipe-d-ctm-0-5: - shard-tglb: [DMESG-WARN][43] ([i915#1149] / [i915#402]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb2/igt at kms_color@pipe-d-ctm-0-5.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][45] ([i915#128]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +26 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +3 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: - shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_setmode@basic: - shard-apl: [FAIL][59] ([i915#31]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_setmode@basic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_setmode@basic.html - shard-kbl: [FAIL][61] ([i915#31]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_setmode@basic.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-hsw5/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [SKIP][65] ([fdo#109271]) -> [INCOMPLETE][66] ([i915#82]) +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb5/igt at i915_pm_dc@dc3co-vpb-simulation.html - shard-iclb: [SKIP][67] ([i915#658]) -> [SKIP][68] ([i915#588]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319] / [i915#1958]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319] / [i915#1635]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][77] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#93] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html - shard-apl: [DMESG-WARN][79] ([i915#180] / [i915#95]) -> [DMESG-WARN][80] ([i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-WARN][81] ([i915#1982]) -> [DMESG-FAIL][82] ([fdo#108145] / [i915#1982]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [SKIP][83] ([fdo#109271]) -> [TIMEOUT][84] ([i915#1958]) +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17882 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17882: 23fe5e3ae83585e3d4ad9ecdfea368dd42ff6dfb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 13:59:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 13:59:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_dma-fence_lockdep_annotations=2C_round_2_=28rev2=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159136557321.18507.11509095777198532203@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev2) URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim checkpatch origin/drm-tip e78a321ad3b9 mm: Track mmu notifiers in fs_reclaim_acquire/release -:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #12: recursions we do have lockdep annotations since 23b68395c7c7 -:41: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 66204f1d2d1b ("mm/mmu_notifiers: prime lockdep")' #41: With this we can also remove the lockdep priming added in 66204f1d2d1b -:116: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #116: FILE: mm/page_alloc.c:4165: + + } -:130: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 2 errors, 1 warnings, 1 checks, 65 lines checked 7e972dd54c14 dma-buf: minor doc touch-ups -:32: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 14 lines checked 83bbee724172 dma-fence: basic lockdep annotations -:23: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e91498589746 ("locking/lockdep/selftests: Add mixed read-write ABBA tests")' #23: commit e91498589746065e3ae95d9a00b068e525eec34f -:97: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e966eaeeb623 ("locking/lockdep: Remove the cross-release locking checks")' #97: commit e966eaeeb623f09975ef362c2866fae6f86844f9 -:103: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #103: This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), -:313: ERROR:IN_ATOMIC: do not use in_atomic in drivers #313: FILE: drivers/dma-buf/dma-fence.c:228: + if (in_atomic()) -:351: CHECK:LINE_SPACING: Please don't use multiple blank lines #351: FILE: drivers/dma-buf/dma-fence.c:266: + + -:400: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #400: FILE: include/linux/dma-fence.h:368: +} +static inline void dma_fence_end_signalling(bool cookie) {} -:406: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 3 errors, 2 warnings, 2 checks, 231 lines checked 24dfd7c2f31d dma-fence: prime lockdep annotations -:31: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #31: commit 23b68395c7c78a764e8963fc15a7cfd318bf187f -:169: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 1 errors, 1 warnings, 0 checks, 82 lines checked f0ab547cc6c5 drm/vkms: Annotate vblank timer -:59: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 25 lines checked 5594f77b32e6 drm/vblank: Annotate with dma-fence signalling section -:71: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 38 lines checked 46b7c2fd5ffd drm/atomic-helper: Add dma-fence annotations -:119: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 76 lines checked ac0b1f52d0fe drm/amdgpu: add dma-fence annotations to atomic commit path -:52: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 24 lines checked c0009c21b60f drm/scheduler: use dma-fence annotations in main thread -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 21 lines checked 0e0f7023514c drm/amdgpu: use dma-fence annotations in cs_submit() -:65: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 29 lines checked 47de02c44f96 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code -:82: WARNING:ALLOC_ARRAY_ARGS: kmalloc_array uses number as first arg, sizeof is generally wrong #82: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:211: + fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_ATOMIC); -:98: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 24 lines checked 4c8281f15785 drm/amdgpu: DC also loves to allocate stuff where it shouldn't -:70: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #70: FILE: drivers/gpu/drm/amd/display/dc/core/dc.c:1420: + * atomic_commit_tail. */ -:76: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 27 lines checked 2a75b848a16e drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail -:39: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif #39: FILE: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6917: +#if 0 -:55: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 23 lines checked 428021cf6ac1 drm/scheduler: use dma-fence annotations in tdr work -:28: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'? #28: Hence split out as a seperate patch. -:114: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 20 lines checked edb53cc8cdcc drm/amdgpu: use dma-fence annotations for gpu reset code ca71ae15991e Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" -:145: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 16 lines checked 92582d6b872d drm/amdgpu: gpu recovery does full modesets -:186: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 14 lines checked edc7511baed1 drm/i915: Annotate dma_fence_work -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 15 lines checked From patchwork at emeril.freedesktop.org Fri Jun 5 14:01:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 14:01:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?dma-fence_lockdep_annotations=2C_round_2_=28rev2=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159136567721.18509.11977385106322080914@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev2) URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '<asn:2>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '<asn:2> From gwan-gyeong.mun at intel.com Fri Jun 5 14:02:05 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Fri, 5 Jun 2020 14:02:05 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/psr: Program default IO buffer Wake and Fast Wake In-Reply-To: <863417d4a19babccaaafeaf00b1c8bdb8cbc8562.camel@intel.com> References: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> <863417d4a19babccaaafeaf00b1c8bdb8cbc8562.camel@intel.com> Message-ID: <8ad8b2d6ac1cb6c3b381a2bc39d6e0d3fce0a35d.camel@intel.com> On Thu, 2020-06-04 at 18:51 -0700, Souza, Jose wrote: > On Fri, 2020-06-05 at 03:23 +0300, Gwan-gyeong Mun wrote: > > The IO buffer Wake and Fast Wake bit size and value have been > > changed from > > Gen12+. > > It programs default value of IO buffer Wake and Fast Wake on > > Gen12+. > > > > - Pre Gen12 > > Bit location: IO buffer Wake: Register_PSR2_CTL[14:13] > > Fast Wake: Register_PSR2_CTL[12:11] > > > > Value: 0x0: 8 lines > > 0x1: 7 lines > > 0x2: 6 lines > > 0x3: 5 lines > > > > - Gen12+ > > Bit location: IO buffer Wake: Register_PSR2_CTL[15:13] > > Fast Wake: Register_PSR2_CTL[12:10] > > > > Value: 0x0: 5 lines > > 0x1: 6 lines > > 0x2: 7 lines > > 0x3: 8 lines > > 0x4: 9 lines > > 0x5: 10 lines > > 0x6: 11 lines > > 0x7: 12 lines > > If you define the macro like bellow you don't need to add this > information to the commit description. > > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++++ > > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > > 2 files changed, 25 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index b7a2c102648a..de2a17fe8860 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -518,6 +518,25 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > else > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > + if (INTEL_GEN(dev_priv) >= 12) { > > + /* > > + * TODO: In order to setting an optimal power > > consumption, > > + * lower than 4k resoluition mode needs to decrese > > IO_BUFFER_WAKE > > + * and FAST_WAKE. And higher than 4K resolution mode > > needs > > + * to increase IO_BUFFER_WAKE and FAST_WAKE. > > + */ > > + u32 io_buffer_wake = 0x2; /* default BSpec value, 7 > > lines */ > > + u32 fast_wake = 0x2; /* default BSpec value, 7 lines */ > > + > > + /* > > + * To program line 9 to 12 on IO_BUFFER_WAKE and > > FAST_WAKE, > > + * EDP_PSR2_CTL should be set > > EDP_PSR2_BLOCK_COUNT_NUM_3. > > + */ > > + val |= EDP_PSR2_BLOCK_COUNT_NUM_2; > > + val |= EDP_PSR2_IO_BUFFER_WAKE(io_buffer_wake); > > + val |= EDP_PSR2_FAST_WAKE(fast_wake); > > The parameter for this 2 macros should be the number of the lines not > the bit value. > As you are at it, please set the GEN9+ default values, the TGL macros > will need a "TGL_" prefix. > > Okay I'll send the addressed v2 patch. > > + > > /* > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec > > is > > * recommending keep this bit unset while PSR2 is enabled. > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index 96d351fbeebb..d055b7d93a5d 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4514,10 +4514,16 @@ enum { > > #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > > #define EDP_PSR2_ENABLE (1 << 31) > > #define EDP_SU_TRACK_ENABLE (1 << 30) > > +#define EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) /* TGL+ */ > > +#define EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) /* TGL+ */ > > #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > > #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > > #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > > #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > > +#define EDP_PSR2_IO_BUFFER_WAKE(a) ((a) << 13) > > +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (0x7 << 13) /* TGL+ */ > > +#define EDP_PSR2_FAST_WAKE(a) ((a) << 10) /* TGL+ */ > > +#define EDP_PSR2_FAST_WAKE_MASK (0x7 << 10) /* TGL+ */ > > #define EDP_PSR2_TP2_TIME_500us (0 << 8) > > #define EDP_PSR2_TP2_TIME_100us (1 << 8) > > #define EDP_PSR2_TP2_TIME_2500us (2 << 8) From gwan-gyeong.mun at intel.com Fri Jun 5 14:04:22 2020 From: gwan-gyeong.mun at intel.com (Gwan-gyeong Mun) Date: Fri, 5 Jun 2020 17:04:22 +0300 Subject: [Intel-gfx] [PATCH v2] drm/i915/psr: Program default IO buffer Wake and Fast Wake Message-ID: <20200605140422.280195-1-gwan-gyeong.mun@intel.com> The IO buffer Wake and Fast Wake bit size and value have been changed from Gen12+. It programs the default value of IO buffer Wake and Fast Wake on Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 and Gen12+. And it aligns PSR2 definition macros. v2: Fix macro definitions. (Jos?) Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 12 +++++ drivers/gpu/drm/i915/i915_reg.h | 68 +++++++++++++++++------- 2 files changed, 61 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7a0011e42e00..765740d2f32f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -537,6 +537,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); val |= intel_psr2_get_tp_time(intel_dp); + if (INTEL_GEN(dev_priv) >= 12) { + /* + * TODO: In order to setting an optimal power consumption, + * lower than 4k resoluition mode needs to decrese IO_BUFFER_WAKE + * and FAST_WAKE. And higher than 4K resolution mode needs + * to increase IO_BUFFER_WAKE and FAST_WAKE. + */ + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE_7lines; /* default BSpec value */ + val |= TGL_EDP_PSR2_FAST_WAKE_7lines; /* default BSpec value */ + } + /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 814a70945468..bf8988e9ff70 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4511,25 +4511,55 @@ enum { #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ -#define _PSR2_CTL_A 0x60900 -#define _PSR2_CTL_EDP 0x6f900 -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) -#define EDP_PSR2_ENABLE (1 << 31) -#define EDP_SU_TRACK_ENABLE (1 << 30) -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ -#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) -#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) -#define EDP_PSR2_TP2_TIME_500us (0 << 8) -#define EDP_PSR2_TP2_TIME_100us (1 << 8) -#define EDP_PSR2_TP2_TIME_2500us (2 << 8) -#define EDP_PSR2_TP2_TIME_50us (3 << 8) -#define EDP_PSR2_TP2_TIME_MASK (3 << 8) -#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 -#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) -#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) -#define EDP_PSR2_IDLE_FRAME_MASK 0xf -#define EDP_PSR2_IDLE_FRAME_SHIFT 0 +#define _PSR2_CTL_A 0x60900 +#define _PSR2_CTL_EDP 0x6f900 +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) +#define EDP_PSR2_ENABLE (1 << 31) +#define EDP_SU_TRACK_ENABLE (1 << 30) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) +#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ +#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ +#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) +#define EDP_PSR2_IO_BUFFER_WAKE_5lines (3 << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_6lines (2 << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_7lines (1 << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_8lines (0 << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_5lines (0 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_6lines (1 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_7lines (2 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_8lines (3 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_9lines (4 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_10lines (5 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_11lines (6 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_12lines (7 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) +#define EDP_PSR2_FAST_WAKE_5lines (3 << 11) +#define EDP_PSR2_FAST_WAKE_6lines (2 << 11) +#define EDP_PSR2_FAST_WAKE_7lines (1 << 11) +#define EDP_PSR2_FAST_WAKE_8lines (0 << 11) +#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) +#define TGL_EDP_PSR2_FAST_WAKE_5lines (0 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_6lines (1 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_7lines (2 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_8lines (3 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_9lines (4 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_10lines (5 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_11lines (6 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_12lines (7 << 10) +#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) +#define EDP_PSR2_TP2_TIME_500us (0 << 8) +#define EDP_PSR2_TP2_TIME_100us (1 << 8) +#define EDP_PSR2_TP2_TIME_2500us (2 << 8) +#define EDP_PSR2_TP2_TIME_50us (3 << 8) +#define EDP_PSR2_TP2_TIME_MASK (3 << 8) +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) +#define EDP_PSR2_IDLE_FRAME_MASK 0xf +#define EDP_PSR2_IDLE_FRAME_SHIFT 0 #define _PSR_EVENT_TRANS_A 0x60848 #define _PSR_EVENT_TRANS_B 0x61848 -- 2.25.0 From patchwork at emeril.freedesktop.org Fri Jun 5 14:15:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 14:15:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZG1h?= =?utf-8?q?-fence_lockdep_annotations=2C_round_2_=28rev2=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159136650265.18507.16407660034706237133@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev2) URL : https://patchwork.freedesktop.org/series/77986/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17886 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17886 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17886, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17886: ### IGT changes ### #### Possible regressions #### * igt at gem_close_race@basic-process: - fi-ivb-3770: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-ivb-3770/igt at gem_close_race@basic-process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-ivb-3770/igt at gem_close_race@basic-process.html - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at gem_close_race@basic-process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-byt-j1900/igt at gem_close_race@basic-process.html - fi-hsw-4770: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-hsw-4770/igt at gem_close_race@basic-process.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-hsw-4770/igt at gem_close_race@basic-process.html - fi-byt-n2820: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at gem_close_race@basic-process.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-byt-n2820/igt at gem_close_race@basic-process.html * igt at kms_busy@basic at flip: - fi-snb-2600: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-snb-2600/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-snb-2600/igt at kms_busy@basic at flip.html - fi-snb-2520m: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-snb-2520m/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-snb-2520m/igt at kms_busy@basic at flip.html * igt at kms_frontbuffer_tracking@basic: - fi-ilk-650: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html * igt at runner@aborted: - fi-cfl-8700k: NOTRUN -> [FAIL][15] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cfl-8700k/igt at runner@aborted.html - fi-tgl-y: NOTRUN -> [FAIL][16] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-tgl-y/igt at runner@aborted.html - fi-cfl-8109u: NOTRUN -> [FAIL][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cfl-8109u/igt at runner@aborted.html - fi-icl-u2: NOTRUN -> [FAIL][18] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-icl-u2/igt at runner@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][19] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-snb-2520m/igt at runner@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][20] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-bdw-5557u/igt at runner@aborted.html - fi-byt-n2820: NOTRUN -> [FAIL][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-byt-n2820/igt at runner@aborted.html - fi-icl-guc: NOTRUN -> [FAIL][22] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-icl-guc/igt at runner@aborted.html - fi-hsw-4770: NOTRUN -> [FAIL][23] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-hsw-4770/igt at runner@aborted.html - fi-snb-2600: NOTRUN -> [FAIL][24] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-snb-2600/igt at runner@aborted.html - fi-whl-u: NOTRUN -> [FAIL][25] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-whl-u/igt at runner@aborted.html - fi-cml-u2: NOTRUN -> [FAIL][26] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cml-u2/igt at runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][27] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-ivb-3770/igt at runner@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][28] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-bxt-dsi/igt at runner@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][29] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-byt-j1900/igt at runner@aborted.html - fi-cml-s: NOTRUN -> [FAIL][30] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cml-s/igt at runner@aborted.html - fi-cfl-guc: NOTRUN -> [FAIL][31] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cfl-guc/igt at runner@aborted.html - fi-icl-y: NOTRUN -> [FAIL][32] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-icl-y/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_busy@busy at all}: - fi-kbl-x1275: [PASS][33] -> [DMESG-WARN][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at gem_busy@busy at all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-x1275/igt at gem_busy@busy at all.html - fi-cfl-8700k: [PASS][35] -> [DMESG-WARN][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-cfl-8700k/igt at gem_busy@busy at all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cfl-8700k/igt at gem_busy@busy at all.html - fi-tgl-y: [PASS][37] -> [DMESG-WARN][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at gem_busy@busy at all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-tgl-y/igt at gem_busy@busy at all.html - fi-skl-6600u: [PASS][39] -> [DMESG-WARN][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-skl-6600u/igt at gem_busy@busy at all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-skl-6600u/igt at gem_busy@busy at all.html - fi-cfl-8109u: [PASS][41] -> [DMESG-WARN][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-cfl-8109u/igt at gem_busy@busy at all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cfl-8109u/igt at gem_busy@busy at all.html - fi-icl-u2: [PASS][43] -> [DMESG-WARN][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-u2/igt at gem_busy@busy at all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-icl-u2/igt at gem_busy@busy at all.html - {fi-tgl-dsi}: [PASS][45] -> [DMESG-WARN][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-dsi/igt at gem_busy@busy at all.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-tgl-dsi/igt at gem_busy@busy at all.html - fi-glk-dsi: [PASS][47] -> [DMESG-WARN][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-glk-dsi/igt at gem_busy@busy at all.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-glk-dsi/igt at gem_busy@busy at all.html - fi-kbl-8809g: [PASS][49] -> [DMESG-WARN][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-8809g/igt at gem_busy@busy at all.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-8809g/igt at gem_busy@busy at all.html - fi-skl-lmem: [PASS][51] -> [DMESG-WARN][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-skl-lmem/igt at gem_busy@busy at all.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-skl-lmem/igt at gem_busy@busy at all.html - fi-kbl-r: [PASS][53] -> [DMESG-WARN][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-r/igt at gem_busy@busy at all.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-r/igt at gem_busy@busy at all.html - fi-bdw-5557u: [PASS][55] -> [DMESG-WARN][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bdw-5557u/igt at gem_busy@busy at all.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-bdw-5557u/igt at gem_busy@busy at all.html - fi-icl-guc: [PASS][57] -> [DMESG-WARN][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at gem_busy@busy at all.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-icl-guc/igt at gem_busy@busy at all.html - fi-kbl-soraka: [PASS][59] -> [DMESG-WARN][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-soraka/igt at gem_busy@busy at all.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-soraka/igt at gem_busy@busy at all.html - {fi-ehl-1}: [PASS][61] -> [DMESG-WARN][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-ehl-1/igt at gem_busy@busy at all.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-ehl-1/igt at gem_busy@busy at all.html - fi-kbl-7500u: [PASS][63] -> [DMESG-WARN][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-7500u/igt at gem_busy@busy at all.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-7500u/igt at gem_busy@busy at all.html - fi-kbl-guc: [PASS][65] -> [DMESG-WARN][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-guc/igt at gem_busy@busy at all.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-guc/igt at gem_busy@busy at all.html - fi-whl-u: [PASS][67] -> [DMESG-WARN][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at gem_busy@busy at all.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-whl-u/igt at gem_busy@busy at all.html - fi-cml-u2: [PASS][69] -> [DMESG-WARN][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-cml-u2/igt at gem_busy@busy at all.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cml-u2/igt at gem_busy@busy at all.html - {fi-kbl-7560u}: NOTRUN -> [DMESG-WARN][71] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-7560u/igt at gem_busy@busy at all.html - fi-bxt-dsi: [PASS][72] -> [DMESG-WARN][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bxt-dsi/igt at gem_busy@busy at all.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-bxt-dsi/igt at gem_busy@busy at all.html - {fi-tgl-u}: [PASS][74] -> [DMESG-WARN][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-u/igt at gem_busy@busy at all.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-tgl-u/igt at gem_busy@busy at all.html - fi-cml-s: [PASS][76] -> [DMESG-WARN][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-cml-s/igt at gem_busy@busy at all.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cml-s/igt at gem_busy@busy at all.html - fi-cfl-guc: [PASS][78] -> [DMESG-WARN][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-cfl-guc/igt at gem_busy@busy at all.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-cfl-guc/igt at gem_busy@busy at all.html - fi-icl-y: [PASS][80] -> [DMESG-WARN][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-y/igt at gem_busy@busy at all.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-icl-y/igt at gem_busy@busy at all.html - fi-skl-6700k2: [PASS][82] -> [DMESG-WARN][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-skl-6700k2/igt at gem_busy@busy at all.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-skl-6700k2/igt at gem_busy@busy at all.html * igt at runner@aborted: - {fi-tgl-dsi}: NOTRUN -> [FAIL][84] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-tgl-dsi/igt at runner@aborted.html - {fi-ehl-1}: NOTRUN -> [FAIL][85] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-ehl-1/igt at runner@aborted.html - {fi-tgl-u}: NOTRUN -> [FAIL][86] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-tgl-u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17886 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-kbl-soraka: [PASS][87] -> [DMESG-WARN][88] ([i915#1982]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-soraka/igt at debugfs_test@read_all_entries.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-soraka/igt at debugfs_test@read_all_entries.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][89] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][90] ([i915#62] / [i915#92]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17886 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17886: edc7511baed1bde446c55372c108b49f5f7acf39 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == edc7511baed1 drm/i915: Annotate dma_fence_work 92582d6b872d drm/amdgpu: gpu recovery does full modesets ca71ae15991e Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" edb53cc8cdcc drm/amdgpu: use dma-fence annotations for gpu reset code 428021cf6ac1 drm/scheduler: use dma-fence annotations in tdr work 2a75b848a16e drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail 4c8281f15785 drm/amdgpu: DC also loves to allocate stuff where it shouldn't 47de02c44f96 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code 0e0f7023514c drm/amdgpu: use dma-fence annotations in cs_submit() c0009c21b60f drm/scheduler: use dma-fence annotations in main thread ac0b1f52d0fe drm/amdgpu: add dma-fence annotations to atomic commit path 46b7c2fd5ffd drm/atomic-helper: Add dma-fence annotations 5594f77b32e6 drm/vblank: Annotate with dma-fence signalling section f0ab547cc6c5 drm/vkms: Annotate vblank timer 24dfd7c2f31d dma-fence: prime lockdep annotations 83bbee724172 dma-fence: basic lockdep annotations 7e972dd54c14 dma-buf: minor doc touch-ups e78a321ad3b9 mm: Track mmu notifiers in fs_reclaim_acquire/release == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17886/index.html From keescook at chromium.org Fri Jun 5 14:19:53 2020 From: keescook at chromium.org (Kees Cook) Date: Fri, 5 Jun 2020 07:19:53 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Fix comments mentioning typo in IS_ENABLED() Message-ID: <202006050718.9D4FCFC2E@keescook> This has no code changes, but the typo is clearly getting copy/pasted, so better to avoid this now and fix the typo. IS_ENABLED() takes full names, and must have the "CONFIG_" prefix. Reported-by: Joe Perches <joe at perches.com> Link: https://lore.kernel.org/lkml/b08611018fdb6d88757c6008a5c02fa0e07b32fb.camel at perches.com Signed-off-by: Kees Cook <keescook at chromium.org> --- drivers/dma-buf/selftests.h | 2 +- drivers/gpu/drm/i915/selftests/i915_live_selftests.h | 2 +- drivers/gpu/drm/i915/selftests/i915_mock_selftests.h | 2 +- drivers/gpu/drm/i915/selftests/i915_perf_selftests.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h index 55918ef9adab..bc8cea67bf1e 100644 --- a/drivers/dma-buf/selftests.h +++ b/drivers/dma-buf/selftests.h @@ -5,7 +5,7 @@ * a module parameter. It must be unique and legal for a C identifier. * * The function should be of type int function(void). It may be conditionally - * compiled using #if IS_ENABLED(DRM_I915_SELFTEST). + * compiled using #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST). * * Tests are executed in order by igt/dmabuf_selftest */ diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h index 5dd5d81646c4..e42ea9c6703b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h +++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h @@ -11,7 +11,7 @@ * a module parameter. It must be unique and legal for a C identifier. * * The function should be of type int function(void). It may be conditionally - * compiled using #if IS_ENABLED(DRM_I915_SELFTEST). + * compiled using #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST). * * Tests are executed in order by igt/drv_selftest */ diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h index 6a2be7d0dd95..4be044198af9 100644 --- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h +++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h @@ -11,7 +11,7 @@ * a module parameter. It must be unique and legal for a C identifier. * * The function should be of type int function(void). It may be conditionally - * compiled using #if IS_ENABLED(DRM_I915_SELFTEST). + * compiled using #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST). * * Tests are executed in order by igt/drv_selftest */ diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h index d8da142985eb..c2389f8a257d 100644 --- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h +++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h @@ -11,7 +11,7 @@ * a module parameter. It must be unique and legal for a C identifier. * * The function should be of type int function(void). It may be conditionally - * compiled using #if IS_ENABLED(DRM_I915_SELFTEST). + * compiled using #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST). * * Tests are executed in order by igt/i915_selftest */ -- 2.25.1 -- Kees Cook From patchwork at emeril.freedesktop.org Fri Jun 5 14:28:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 14:28:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/10=5D_drm/i915/gt=3A_Set_timeslicing_pr?= =?utf-8?q?iority_from_queue?= In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <159136728457.18508.708179512871737136@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue URL : https://patchwork.freedesktop.org/series/78037/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17885_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17885_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17885_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17885_full: ### IGT changes ### #### Possible regressions #### * igt at gem_ctx_persistence@close-replace-race: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl5/igt at gem_ctx_persistence@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-skl10/igt at gem_ctx_persistence@close-replace-race.html Known issues ------------ Here are the changes found in Patchwork_17885_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_param@set-priority-not-supported: - shard-snb: [PASS][3] -> [SKIP][4] ([fdo#109271]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb4/igt at gem_ctx_param@set-priority-not-supported.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-snb6/igt at gem_ctx_param@set-priority-not-supported.html - shard-hsw: [PASS][5] -> [SKIP][6] ([fdo#109271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw2/igt at gem_ctx_param@set-priority-not-supported.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-hsw8/igt at gem_ctx_param@set-priority-not-supported.html * igt at i915_suspend@debugfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at i915_suspend@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl6/igt at i915_suspend@debugfs-reader.html * igt at kms_addfb_basic@addfb25-y-tiled: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl1/igt at kms_addfb_basic@addfb25-y-tiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-skl2/igt at kms_addfb_basic@addfb25-y-tiled.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-glk2/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl8/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#93] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +10 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl4/igt at kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#173]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb3/igt at kms_psr@no_drrs.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-iclb8/igt at kms_psr@psr2_cursor_blt.html * igt at kms_vblank@pipe-b-wait-busy: - shard-iclb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb1/igt at kms_vblank@pipe-b-wait-busy.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-iclb1/igt at kms_vblank@pipe-b-wait-busy.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_ctx_shared@detached-shared-gtt: - shard-apl: [DMESG-WARN][33] ([i915#95]) -> [PASS][34] +13 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at gem_ctx_shared@detached-shared-gtt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl6/igt at gem_ctx_shared@detached-shared-gtt.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][35] ([i915#1930]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html - shard-apl: [FAIL][37] ([i915#1930]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl8/igt at gem_exec_reloc@basic-concurrent0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl1/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-hsw: [SKIP][39] ([fdo#109271]) -> [PASS][40] +27 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw1/igt at gem_exec_whisper@basic-contexts-priority-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-hsw5/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-glk5/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][43] ([i915#1436] / [i915#716]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl2/igt at gen9_exec_parse@allowed-all.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [INCOMPLETE][45] ([i915#155]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl2/igt at i915_suspend@debugfs-reader.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][49] ([i915#128]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-skl3/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-glk6/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +5 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_lowres@pipe-c-tiling-yf: - shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl7/igt at kms_plane_lowres@pipe-c-tiling-yf.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-skl1/igt at kms_plane_lowres@pipe-c-tiling-yf.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at kms_psr@psr2_cursor_mmap_cpu.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_setmode@basic: - shard-apl: [FAIL][63] ([i915#31]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_setmode@basic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl6/igt at kms_setmode@basic.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][65] ([i915#1542]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-hsw7/igt at perf@polling-parameterized.html * {igt at perf_pmu@busy-accuracy-2 at bcs0}: - shard-snb: [SKIP][67] ([fdo#109271]) -> [PASS][68] +22 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at perf_pmu@busy-accuracy-2 at bcs0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-snb1/igt at perf_pmu@busy-accuracy-2 at bcs0.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl1/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl4/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl1/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][77] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#93] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html - shard-apl: [DMESG-WARN][79] ([i915#180] / [i915#95]) -> [DMESG-WARN][80] ([i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-apl7/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-WARN][81] ([i915#1982]) -> [DMESG-FAIL][82] ([fdo#108145] / [i915#1982]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17885 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17885: 49e963cbf7098a41ba1f958aeb235b4af2166697 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17885/index.html From hdegoede at redhat.com Fri Jun 5 14:33:47 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Fri, 5 Jun 2020 16:33:47 +0200 Subject: [Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) In-Reply-To: <20200602152317.GI2428291@smile.fi.intel.com> References: <20200602122130.45630-1-hdegoede@redhat.com> <20200602152317.GI2428291@smile.fi.intel.com> Message-ID: <ba931618-9259-aca0-142c-c1dfb67e737e@redhat.com> Hi, On 6/2/20 5:23 PM, Andy Shevchenko wrote: > On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote: >> The pins on the Bay Trail SoC have separate input-buffer and output-buffer >> enable bits and a read of the level bit of the value register will always >> return the value from the input-buffer. >> >> The BIOS of a device may configure a pin in output-only mode, only enabling >> the output buffer, and write 1 to the level bit to drive the pin high. >> This 1 written to the level bit will be stored inside the data-latch of the >> output buffer. >> >> But a subsequent read of the value register will return 0 for the level bit >> because the input-buffer is disabled. This causes a read-modify-write as >> done by byt_gpio_set_direction() to write 0 to the level bit, driving the >> pin low! >> >> Before this commit byt_gpio_direction_output() relied on >> pinctrl_gpio_direction_output() to set the direction, followed by a call >> to byt_gpio_set() to apply the selected value. This causes the pin to >> go low between the pinctrl_gpio_direction_output() and byt_gpio_set() >> calls. >> >> Change byt_gpio_direction_output() to directly make the register >> modifications itself instead. Replacing the 2 subsequent writes to the >> value register with a single write. >> >> Note that the pinctrl code does not keep track internally of the direction, >> so not going through pinctrl_gpio_direction_output() is not an issue. >> >> This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is >> already on at boot (no external monitor connected), then the i915 driver >> does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The >> temporarily going low of that GPIO was causing the panel to reset itself >> after which it would not show an image until it was turned off and back on >> again (until a full modeset was done on it). This commit fixes this. > > No Fixes tag? It is sort of hard to pin the introduction of this down to a single commit. If I were to guess, I guess the commit introducing the driver? >> Cc: stable at vger.kernel.org >> Signed-off-by: Hans de Goede <hdegoede at redhat.com> > > ... > >> +static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, >> + unsigned int offset) >> +{ >> + void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); >> + >> + /* >> + * Before making any direction modifications, do a check if gpio is set > >> + * for direct IRQ. On baytrail, setting GPIO to output does not make > > Since we change this, perhaps > > 'IRQ. On baytrail' -> 'IRQ. On Baytrail' (one space and capital 'B'). Sure, not sure if that is worth respinning the patch for though, either way let me know. >> + * sense, so let's at least inform the caller before they shoot >> + * themselves in the foot. >> + */ >> + if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) >> + dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output"); >> +} > > ... > >> static int byt_gpio_direction_output(struct gpio_chip *chip, >> unsigned int offset, int value) >> { >> - int ret = pinctrl_gpio_direction_output(chip->base + offset); >> + struct intel_pinctrl *vg = gpiochip_get_data(chip); >> + void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); >> + unsigned long flags; >> + u32 reg; >> >> - if (ret) >> - return ret; >> + raw_spin_lock_irqsave(&byt_lock, flags); >> >> - byt_gpio_set(chip, offset, value); >> + byt_gpio_direct_irq_check(vg, offset); >> >> + reg = readl(val_reg); >> + reg &= ~BYT_DIR_MASK; >> + if (value) >> + reg |= BYT_LEVEL; >> + else >> + reg &= ~BYT_LEVEL; >> + >> + writel(reg, val_reg); >> + >> + raw_spin_unlock_irqrestore(&byt_lock, flags); >> return 0; >> } > > Wouldn't be simple below fix the issue? > > @@ -1171,14 +1171,10 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) > static int byt_gpio_direction_output(struct gpio_chip *chip, > unsigned int offset, int value) > { > - int ret = pinctrl_gpio_direction_output(chip->base + offset); > - > - if (ret) > - return ret; > - > + /* Set value first to avoid a glitch */ > byt_gpio_set(chip, offset, value); > > - return 0; > + return pinctrl_gpio_direction_output(chip->base + offset); > } No that will not help the pin is already high, but any reads of the register will return the BYT_LEVEL bit as being low, so the read-write-modify done when setting the direction reads BYT_LEVEL as 0 and writes it back as such. So your proposal would actually make the problem much worse (and more obvious) if we do the byt_gpio_set() first then for pins which have there input-buffer initially disabled, the value passed to byt_gpio_direction_output will be completely ignored and they will always end up as being driven low. Regards, Hans From thomas_os at shipmail.org Fri Jun 5 14:30:39 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Fri, 5 Jun 2020 16:30:39 +0200 Subject: [Intel-gfx] [PATCH] dma-fence: basic lockdep annotations In-Reply-To: <20200605132953.899664-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-4-daniel.vetter@ffwll.ch> <20200605132953.899664-1-daniel.vetter@ffwll.ch> Message-ID: <83805409-ad4a-65a3-d9cf-21878308dc92@shipmail.org> On 6/5/20 3:29 PM, Daniel Vetter wrote: > Design is similar to the lockdep annotations for workers, but with > some twists: > > - We use a read-lock for the execution/worker/completion side, so that > this explicit annotation can be more liberally sprinkled around. > With read locks lockdep isn't going to complain if the read-side > isn't nested the same way under all circumstances, so ABBA deadlocks > are ok. Which they are, since this is an annotation only. > > - We're using non-recursive lockdep read lock mode, since in recursive > read lock mode lockdep does not catch read side hazards. And we > _very_ much want read side hazards to be caught. For full details of > this limitation see > > commit e91498589746065e3ae95d9a00b068e525eec34f > Author: Peter Zijlstra <peterz at infradead.org> > Date: Wed Aug 23 13:13:11 2017 +0200 > > locking/lockdep/selftests: Add mixed read-write ABBA tests > > - To allow nesting of the read-side explicit annotations we explicitly > keep track of the nesting. lock_is_held() allows us to do that. > > - The wait-side annotation is a write lock, and entirely done within > dma_fence_wait() for everyone by default. > > - To be able to freely annotate helper functions I want to make it ok > to call dma_fence_begin/end_signalling from soft/hardirq context. > First attempt was using the hardirq locking context for the write > side in lockdep, but this forces all normal spinlocks nested within > dma_fence_begin/end_signalling to be spinlocks. That bollocks. > > The approach now is to simple check in_atomic(), and for these cases > entirely rely on the might_sleep() check in dma_fence_wait(). That > will catch any wrong nesting against spinlocks from soft/hardirq > contexts. > > The idea here is that every code path that's critical for eventually > signalling a dma_fence should be annotated with > dma_fence_begin/end_signalling. The annotation ideally starts right > after a dma_fence is published (added to a dma_resv, exposed as a > sync_file fd, attached to a drm_syncobj fd, or anything else that > makes the dma_fence visible to other kernel threads), up to and > including the dma_fence_wait(). Examples are irq handlers, the > scheduler rt threads, the tail of execbuf (after the corresponding > fences are visible), any workers that end up signalling dma_fences and > really anything else. Not annotated should be code paths that only > complete fences opportunistically as the gpu progresses, like e.g. > shrinker/eviction code. > > The main class of deadlocks this is supposed to catch are: > > Thread A: > > mutex_lock(A); > mutex_unlock(A); > > dma_fence_signal(); > > Thread B: > > mutex_lock(A); > dma_fence_wait(); > mutex_unlock(A); > > Thread B is blocked on A signalling the fence, but A never gets around > to that because it cannot acquire the lock A. > > Note that dma_fence_wait() is allowed to be nested within > dma_fence_begin/end_signalling sections. To allow this to happen the > read lock needs to be upgraded to a write lock, which means that any > other lock is acquired between the dma_fence_begin_signalling() call and > the call to dma_fence_wait(), and still held, this will result in an > immediate lockdep complaint. The only other option would be to not > annotate such calls, defeating the point. Therefore these annotations > cannot be sprinkled over the code entirely mindless to avoid false > positives. > > Originally I hope that the cross-release lockdep extensions would > alleviate the need for explicit annotations: > > https://lwn.net/Articles/709849/ > > But there's a few reasons why that's not an option: > > - It's not happening in upstream, since it got reverted due to too > many false positives: > > commit e966eaeeb623f09975ef362c2866fae6f86844f9 > Author: Ingo Molnar <mingo at kernel.org> > Date: Tue Dec 12 12:31:16 2017 +0100 > > locking/lockdep: Remove the cross-release locking checks > > This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), > while it found a number of old bugs initially, was also causing too many > false positives that caused people to disable lockdep - which is arguably > a worse overall outcome. > > - cross-release uses the complete() call to annotate the end of > critical sections, for dma_fence that would be dma_fence_signal(). > But we do not want all dma_fence_signal() calls to be treated as > critical, since many are opportunistic cleanup of gpu requests. If > these get stuck there's still the main completion interrupt and > workers who can unblock everyone. Automatically annotating all > dma_fence_signal() calls would hence cause false positives. > > - cross-release had some educated guesses for when a critical section > starts, like fresh syscall or fresh work callback. This would again > cause false positives without explicit annotations, since for > dma_fence the critical sections only starts when we publish a fence. > > - Furthermore there can be cases where a thread never does a > dma_fence_signal, but is still critical for reaching completion of > fences. One example would be a scheduler kthread which picks up jobs > and pushes them into hardware, where the interrupt handler or > another completion thread calls dma_fence_signal(). But if the > scheduler thread hangs, then all the fences hang, hence we need to > manually annotate it. cross-release aimed to solve this by chaining > cross-release dependencies, but the dependency from scheduler thread > to the completion interrupt handler goes through hw where > cross-release code can't observe it. > > In short, without manual annotations and careful review of the start > and end of critical sections, cross-relese dependency tracking doesn't > work. We need explicit annotations. > > v2: handle soft/hardirq ctx better against write side and dont forget > EXPORT_SYMBOL, drivers can't use this otherwise. > > v3: Kerneldoc. > > v4: Some spelling fixes from Mika > > v5: Amend commit message to explain in detail why cross-release isn't > the solution. > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > Cc: linux-media at vger.kernel.org > Cc: linaro-mm-sig at lists.linaro.org > Cc: linux-rdma at vger.kernel.org > Cc: amd-gfx at lists.freedesktop.org > Cc: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> From chris at chris-wilson.co.uk Fri Jun 5 14:40:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 05 Jun 2020 15:40:46 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Fix comments mentioning typo in IS_ENABLED() In-Reply-To: <202006050718.9D4FCFC2E@keescook> References: <202006050718.9D4FCFC2E@keescook> Message-ID: <159136804617.22562.13050948656630993484@build.alporthouse.com> Quoting Kees Cook (2020-06-05 15:19:53) > This has no code changes, but the typo is clearly getting copy/pasted, > so better to avoid this now and fix the typo. IS_ENABLED() takes full > names, and must have the "CONFIG_" prefix. > > Reported-by: Joe Perches <joe at perches.com> > Link: https://lore.kernel.org/lkml/b08611018fdb6d88757c6008a5c02fa0e07b32fb.camel at perches.com > Signed-off-by: Kees Cook <keescook at chromium.org> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Fri Jun 5 14:47:05 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 15:47:05 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Include the engine's fw-domains in the debug info Message-ID: <20200605144705.31127-1-chris@chris-wilson.co.uk> Add engine->fw_domain/active to the pretty printer for debug dumps and debugfs. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 8942cf936111..b84848db1bce 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1517,6 +1517,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, yesno(!llist_empty(&engine->barrier_tasks))); drm_printf(m, "\tLatency: %luus\n", ewma__engine_latency_read(&engine->latency)); + drm_printf(m, "\tForcewake: %x domains, %d active\n", + engine->fw_domain, atomic_read(&engine->fw_active)); rcu_read_lock(); rq = READ_ONCE(engine->heartbeat.systole); -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 5 14:48:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 14:48:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake_=28re?= =?utf-8?b?djIp?= In-Reply-To: <20200605140422.280195-1-gwan-gyeong.mun@intel.com> References: <20200605140422.280195-1-gwan-gyeong.mun@intel.com> Message-ID: <159136851106.18509.5271154487175266097@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev2) URL : https://patchwork.freedesktop.org/series/78019/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17887 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/index.html Known issues ------------ Here are the changes found in Patchwork_17887 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-byt-n2820/igt at i915_module_load@reload.html - fi-tgl-y: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-tgl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at active: - fi-whl-u: [DMESG-FAIL][11] ([i915#666]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_selftest@live at active.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-whl-u/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-icl-guc: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1}: - fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-skl-lmem fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17887 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17887: 2553fbc0995b01bd08a3a732dfe008cae98fb915 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2553fbc0995b drm/i915/psr: Program default IO buffer Wake and Fast Wake == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/index.html From mika.kuoppala at linux.intel.com Fri Jun 5 14:47:24 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 05 Jun 2020 17:47:24 +0300 Subject: [Intel-gfx] [PATCH 01/10] drm/i915/gt: Set timeslicing priority from queue In-Reply-To: <20200605122334.2798-1-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> Message-ID: <87zh9ha7sz.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > If we only submit the first port, leaving the second empty yet have > ready requests pending in the queue, use that to set the timeslicing > priority (i.e. the priority at which we will decided to enabling s/decided/decide > timeslicing and evict the currently active context if the queue is of > equal priority after its quantum expired). > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 33b7173b7195..92c3368ffcbd 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1966,7 +1966,7 @@ static int > switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq) > { > if (list_is_last(&rq->sched.link, &engine->active.requests)) > - return INT_MIN; > + return engine->execlists.queue_priority_hint; > > return rq_prio(list_next_entry(rq, sched.link)); > } > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From tvrtko.ursulin at linux.intel.com Fri Jun 5 14:50:05 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 5 Jun 2020 15:50:05 +0100 Subject: [Intel-gfx] [PATCH 1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <793dd101-48c9-7344-5291-8e7f5b65ca96@linux.intel.com> On 05/06/2020 10:58, Chris Wilson wrote: > One more list iterator variant, for when we want to unwind from inside > one list iterator with the intention of restarting from the current > entry as the new head of the list. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_utils.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h > index 03a73d2bd50d..6ebccdd12d4c 100644 > --- a/drivers/gpu/drm/i915/i915_utils.h > +++ b/drivers/gpu/drm/i915/i915_utils.h > @@ -266,6 +266,12 @@ static inline int list_is_last_rcu(const struct list_head *list, > return READ_ONCE(list->next) == head; > } > > +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ > + for (pos = list_prev_entry(pos, member), \ > + n = list_prev_entry(pos, member); \ > + &pos->member != (head); \ > + pos = n, n = list_prev_entry(n, member)) > + > /* > * Wait until the work is finally complete, even if it tries to postpone > * by requeueing itself. Note, that if the worker never cancels itself, > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From matthew.william.auld at gmail.com Fri Jun 5 15:00:49 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 5 Jun 2020 16:00:49 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Discard a misplaced GGTT vma In-Reply-To: <20200605105646.24300-1-chris@chris-wilson.co.uk> References: <20200605105646.24300-1-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHOEBC9AWEzx2rgRZ3u221PTB4U-p36G3+XSeCwZzXXfpA@mail.gmail.com> On Fri, 5 Jun 2020 at 11:56, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Across the many users of the GGTT vma (internal objects, mmapings, > display etc), we may end up with conflicting requirements for the > placement. Currently, we try to resolve the conflict by unbinding the > vma and rebinding it to match the new constraints; over time we will end > up with a GGTT that matches the most strict constraints over all > concurrent users. However, this causes a problem if the vma is currently > in use as we must wait until it is idle before moving it. But there is > no restriction on the number of views we may use (apart from the limited > size of the GGTT itself), and so if the active vma does not meet our > requirements, try and build a new one! > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Heebie-jeebies aside, Reviewed-by: Matthew Auld <matthew.auld at intel.com> From lakshminarayana.vudum at intel.com Fri Jun 5 15:03:45 2020 From: lakshminarayana.vudum at intel.com (Vudum, Lakshminarayana) Date: Fri, 5 Jun 2020 15:03:45 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BRESEND=2Cv3=2C1/3=5D_drm/i915/dp=5Fmst=3A_?= =?utf-8?q?Fix_disabling_MST_on_a_port_=28rev6=29?= In-Reply-To: <20200605115001.GB17978@ideak-desk.fi.intel.com> References: <20200603211040.8190-1-imre.deak@intel.com> <159135637372.18508.17555303407147804828@emeril.freedesktop.org> <20200605115001.GB17978@ideak-desk.fi.intel.com> Message-ID: <7977c22465bf436498d0d1d95a1dc63e@intel.com> Imre, I have addressed and re-reported. Lakshmi. -----Original Message----- From: Imre Deak <imre.deak at intel.com> Sent: Friday, June 5, 2020 2:50 PM To: intel-gfx at lists.freedesktop.org Cc: Vudum, Lakshminarayana <lakshminarayana.vudum at intel.com> Subject: Re: ? Fi.CI.IGT: failure for series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6) On Fri, Jun 05, 2020 at 11:26:13AM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6) > URL : https://patchwork.freedesktop.org/series/77969/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17882_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17882_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17882_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17882_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: > - shard-snb: [PASS][1] -> [TIMEOUT][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/ig > t at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html > > > #### Warnings #### > > * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: > - shard-snb: [SKIP][3] ([fdo#109271]) -> [TIMEOUT][4] +1 similar issue > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/ig > t at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html Both of the above are unrelated, since there's only a VGA output connected to shard-snb1. Both tests time out because an earlier failure: <7>[ 96.713236] [IGT] gem_exec_reloc: starting subtest basic-concurrent16 <5>[ 216.856564] [IGT] Per-test timeout exceeded. Killing the current test with SIGQUIT. <6>[ 216.880307] gem_exec_reloc S12784 1625 1624 0x00000000 <4>[ 216.880311] Call Trace: <4>[ 216.880317] __schedule+0x2ff/0x8d0 <4>[ 216.880325] schedule+0x37/0xe0 <4>[ 216.880328] schedule_timeout+0x1aa/0x2e0 <4>[ 216.880390] ? mock_breadcrumbs_smoketest+0x290/0x290 [i915] <4>[ 216.880394] ? find_held_lock+0x2d/0x90 <4>[ 216.880442] ? hwsp_seqno+0x5b/0xd0 [i915] <4>[ 216.880449] io_schedule_timeout+0x14/0x40 <4>[ 216.880502] i915_request_wait+0x159/0x550 [i915] <4>[ 216.880548] ? __i915_request_await_external+0x40/0x40 [i915] <4>[ 216.880593] i915_gem_object_wait+0xb2/0x540 [i915] <4>[ 216.880640] i915_gem_wait_ioctl+0x113/0x2d0 [i915] <4>[ 216.880683] ? i915_gem_object_wait+0x540/0x540 [i915] <4>[ 216.880688] drm_ioctl_kernel+0xb0/0xf0 <4>[ 216.880694] drm_ioctl+0x305/0x3c0 <4>[ 216.880737] ? i915_gem_object_wait+0x540/0x540 [i915] <4>[ 216.880750] ksys_ioctl+0x7b/0x90 <4>[ 216.880755] __x64_sys_ioctl+0x11/0x20 <4>[ 216.880757] do_syscall_64+0x4f/0x220 <4>[ 216.880760] entry_SYSCALL_64_after_hwframe+0x49/0xb3 > > > #### Suppressed #### > > The following results come from untrusted machines, tests, or statuses. > They do not affect the overall result. > > * {igt at gem_exec_reloc@basic-concurrent16}: > - shard-snb: [FAIL][5] ([i915#1930]) -> [TIMEOUT][6] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/ig > t at gem_exec_reloc@basic-concurrent16.html > > * {igt at kms_chamelium@vga-hpd-enable-disable-mode}: > - shard-snb: [SKIP][7] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][8] > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_chamelium@vga-hpd-enable-disable-mode.html > [8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/ig > t at kms_chamelium@vga-hpd-enable-disable-mode.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_17882_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_whisper@basic-forked-all: > - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk7/igt at gem_exec_whisper@basic-forked-all.html > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk2/ig > t at gem_exec_whisper@basic-forked-all.html > > * igt at gem_mmap_gtt@cpuset-big-copy-odd: > - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > [12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/i > gt at gem_mmap_gtt@cpuset-big-copy-odd.html > > * igt at gem_workarounds@suspend-resume: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_workarounds@suspend-resume.html > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/ig > t at gem_workarounds@suspend-resume.html > > * igt at kms_big_fb@linear-32bpp-rotate-180: > - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +9 similar issues > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_big_fb@linear-32bpp-rotate-180.html > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/ig > t at kms_big_fb@linear-32bpp-rotate-180.html > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / [i915#95]) +1 similar issue > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html > [18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/ig > t at kms_big_fb@linear-64bpp-rotate-180.html > > * igt at kms_big_fb@x-tiled-16bpp-rotate-0: > - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html > [20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk4/ig > t at kms_big_fb@x-tiled-16bpp-rotate-0.html > > * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: > - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +17 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html > [22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/ig > t at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html > > * igt at kms_cursor_crc@pipe-c-cursor-suspend: > - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > [24]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/ig > t at kms_cursor_crc@pipe-c-cursor-suspend.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > [26]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl1/ig > t at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > > * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: > - shard-skl: [PASS][27] -> [FAIL][28] ([i915#49]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html > [28]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl9/ig > t at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [30]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/ig > t at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt at kms_plane_lowres@pipe-a-tiling-x: > - shard-snb: [PASS][31] -> [SKIP][32] ([fdo#109271]) +1 similar issue > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at kms_plane_lowres@pipe-a-tiling-x.html > [32]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/ig > t at kms_plane_lowres@pipe-a-tiling-x.html > > * igt at kms_psr@psr2_cursor_blt: > - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +3 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html > [34]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb4/i > gt at kms_psr@psr2_cursor_blt.html > > * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: > - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html > [36]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/ig > t at kms_universal_plane@universal-plane-gen9-features-pipe-c.html > > * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: > - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#402]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html > [38]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb7/i > gt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html > > > #### Possible fixes #### > > * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: > - shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +2 similar issues > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html > [40]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/ig > t at gem_ctx_isolation@preservation-s3 at rcs0.html > > * igt at gem_exec_whisper@basic-queues-forked-all: > - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html > [42]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk9/ig > t at gem_exec_whisper@basic-queues-forked-all.html > > * igt at gen9_exec_parse@allowed-all: > - shard-kbl: [DMESG-WARN][43] ([i915#1436] / [i915#716]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html > [44]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/ig > t at gen9_exec_parse@allowed-all.html > > * igt at i915_suspend@debugfs-reader: > - shard-kbl: [INCOMPLETE][45] ([i915#155]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html > [46]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl6/ig > t at i915_suspend@debugfs-reader.html > > * igt at kms_color@pipe-c-ctm-red-to-blue: > - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html > [48]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/ig > t at kms_color@pipe-c-ctm-red-to-blue.html > > * igt at kms_color@pipe-d-ctm-0-5: > - shard-tglb: [DMESG-WARN][49] ([i915#1149] / [i915#402]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb2/igt at kms_color@pipe-d-ctm-0-5.html > [50]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb1/i > gt at kms_color@pipe-d-ctm-0-5.html > > * igt at kms_cursor_legacy@all-pipes-torture-move: > - shard-skl: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html > [52]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/ig > t at kms_cursor_legacy@all-pipes-torture-move.html > > * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: > - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html > [54]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/ig > t at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html > > * igt at kms_flip_tiling@flip-x-tiled: > - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +26 similar issues > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html > [56]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/ig > t at kms_flip_tiling@flip-x-tiled.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html > [58]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/ig > t at kms_hdr@bpc-switch-suspend.html > > * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: > - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +3 similar issues > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > [60]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/ig > t at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > > * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: > - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +2 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html > [62]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/ig > t at kms_plane@plane-panning-bottom-right-pipe-c-planes.html > > * igt at kms_psr@psr2_primary_mmap_cpu: > - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html > [64]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/i > gt at kms_psr@psr2_primary_mmap_cpu.html > > * igt at kms_setmode@basic: > - shard-apl: [FAIL][65] ([i915#31]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_setmode@basic.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_setmode@basic.html > - shard-kbl: [FAIL][67] ([i915#31]) -> [PASS][68] > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html > [68]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/ig > t at kms_setmode@basic.html > > * {igt at perf@polling-parameterized}: > - shard-hsw: [FAIL][69] ([i915#1542]) -> [PASS][70] > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html > [70]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-hsw5/ig > t at perf@polling-parameterized.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-snb: [SKIP][71] ([fdo#109271]) -> [INCOMPLETE][72] ([i915#82]) +1 similar issue > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb5/igt at i915_pm_dc@dc3co-vpb-simulation.html > - shard-iclb: [SKIP][73] ([i915#658]) -> [SKIP][74] ([i915#588]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html > [74]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/i > gt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at kms_content_protection@atomic: > - shard-apl: [FAIL][75] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html > [76]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/ig > t at kms_content_protection@atomic.html > > * igt at kms_content_protection@legacy: > - shard-kbl: [DMESG-FAIL][77] ([fdo#110321]) -> [TIMEOUT][78] ([i915#1319] / [i915#1958]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html > [78]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/ig > t at kms_content_protection@legacy.html > > * igt at kms_content_protection@lic: > - shard-apl: [DMESG-FAIL][79] ([fdo#110321] / [i915#95]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) +1 similar issue > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html > [80]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/ig > t at kms_content_protection@lic.html > > * igt at kms_content_protection@srm: > - shard-kbl: [DMESG-FAIL][81] ([fdo#110321] / [i915#95]) -> [TIMEOUT][82] ([i915#1319]) > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html > [82]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/ig > t at kms_content_protection@srm.html > > * igt at kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html > - shard-apl: [DMESG-WARN][85] ([i915#180] / [i915#95]) -> [DMESG-WARN][86] ([i915#95]) > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html > [86]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/ig > t at kms_frontbuffer_tracking@fbc-suspend.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [DMESG-WARN][87] ([i915#1982]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1982]) > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [88]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/ig > t at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8590 -> Patchwork_17882 > > CI-20190529: 20190529 > CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17882: 23fe5e3ae83585e3d4ad9ecdfea368dd42ff6dfb @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/index.html --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From mika.kuoppala at linux.intel.com Fri Jun 5 15:20:34 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 05 Jun 2020 18:20:34 +0300 Subject: [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting In-Reply-To: <20200605122334.2798-2-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> <20200605122334.2798-2-chris@chris-wilson.co.uk> Message-ID: <87wo4la69p.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > We may choose not to submit for a number of reasons, yet not fill both > ELSP. In which case we must start timeslicing (there will be no ACK > event on which to hook the start) if the queue would benefit from the > currently active context being evicted. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 92c3368ffcbd..d55a5e0466e5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -2362,10 +2362,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > if (last->context == rq->context) > goto done; > > - if (i915_request_has_sentinel(last)) { > - start_timeslice(engine, rq_prio(rq)); > + if (i915_request_has_sentinel(last)) > goto done; > - } > > /* > * If GVT overrides us we only ever submit > @@ -2446,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > set_preempt_timeout(engine, *active); > execlists_submit_ports(engine); > } else { > + start_timeslice(engine, execlists->queue_priority_hint); If we ended up with same set of request, we want to skip submitting. But why would we want to skip timeslicing? -Mika > skip_submit: > ring_set_paused(engine, 0); > } > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Fri Jun 5 15:22:59 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 05 Jun 2020 18:22:59 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Include the engine's fw-domains in the debug info In-Reply-To: <20200605144705.31127-1-chris@chris-wilson.co.uk> References: <20200605144705.31127-1-chris@chris-wilson.co.uk> Message-ID: <87tuzpa65o.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Add engine->fw_domain/active to the pretty printer for debug dumps and > debugfs. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 8942cf936111..b84848db1bce 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1517,6 +1517,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, > yesno(!llist_empty(&engine->barrier_tasks))); > drm_printf(m, "\tLatency: %luus\n", > ewma__engine_latency_read(&engine->latency)); > + drm_printf(m, "\tForcewake: %x domains, %d active\n", This new world of omitting 0x is peculiar :O -Mika > + engine->fw_domain, atomic_read(&engine->fw_active)); > > rcu_read_lock(); > rq = READ_ONCE(engine->heartbeat.systole); > -- > 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 15:27:06 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 05 Jun 2020 16:27:06 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Discard a misplaced GGTT vma In-Reply-To: <CAM0jSHOEBC9AWEzx2rgRZ3u221PTB4U-p36G3+XSeCwZzXXfpA@mail.gmail.com> References: <20200605105646.24300-1-chris@chris-wilson.co.uk> <CAM0jSHOEBC9AWEzx2rgRZ3u221PTB4U-p36G3+XSeCwZzXXfpA@mail.gmail.com> Message-ID: <159137082695.22562.10637211751464660148@build.alporthouse.com> Quoting Matthew Auld (2020-06-05 16:00:49) > On Fri, 5 Jun 2020 at 11:56, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > Across the many users of the GGTT vma (internal objects, mmapings, > > display etc), we may end up with conflicting requirements for the > > placement. Currently, we try to resolve the conflict by unbinding the > > vma and rebinding it to match the new constraints; over time we will end > > up with a GGTT that matches the most strict constraints over all > > concurrent users. However, this causes a problem if the vma is currently > > in use as we must wait until it is idle before moving it. But there is > > no restriction on the number of views we may use (apart from the limited > > size of the GGTT itself), and so if the active vma does not meet our > > requirements, try and build a new one! > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Heebie-jeebies aside, > Reviewed-by: Matthew Auld <matthew.auld at intel.com> It's definitely "interesting". This is certainly one case where it would be nice to decouple the vma and let it expire as soon as it becomes inactive. As it stands, it has to wait around until it is evicted so adding to the fragmentation pressure. I'm sure it's not the only stall compositors see [changing to uncached and clflushing is the major one]. The trick I used in the ddx was to fault in a ggtt mmap, so that the framebuffer stood a chance of being in the aperture prior to use, along with making it uncached before use. But long gone are the days where userspace drivers control this. But it does prevent at least one instance of an arbitrary lockup in igt, so it probably helps somewhere. -Chris From tvrtko.ursulin at linux.intel.com Fri Jun 5 15:27:26 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 5 Jun 2020 16:27:26 +0100 Subject: [Intel-gfx] [PATCH 2/5] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <20200605095858.28455-2-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> <20200605095858.28455-2-chris@chris-wilson.co.uk> Message-ID: <8c33c119-0d7f-6897-c697-c0e95a7e0bc5@linux.intel.com> On 05/06/2020 10:58, Chris Wilson wrote: > Over the next couple of patches, we will want to lock all the modified > vma for relocation processing under a single ww_mutex. We neither want > to have to include the vma that are skipped (due to no modifications > required) nor do we want those to be marked as written too. So separate > out the reloc validation into an early step, which we can use both to > reject the execbuf before committing to making our changes, and to > filter out the unmodified vma. > > This does introduce a second pass through the reloc[], but only if we > need to emit relocations. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 178 +++++++++++++----- > 1 file changed, 133 insertions(+), 45 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index cfe6d2cdbef1..7d4464fddca8 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -1331,6 +1331,117 @@ static u64 > eb_relocate_entry(struct i915_execbuffer *eb, > struct eb_vma *ev, > const struct drm_i915_gem_relocation_entry *reloc) > +{ > + struct eb_vma *target; > + > + /* we've already hold a reference to all valid objects */ > + target = eb_get_vma(eb, reloc->target_handle); > + if (unlikely(!target)) > + return -ENOENT; > + > + /* > + * If the relocation already has the right value in it, no > + * more work needs to be done. > + */ > + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) > + return 0; These have been filtered out, no? > + > + /* > + * If we write into the object, we need to force the synchronisation > + * barrier, either with an asynchronous clflush or if we executed the > + * patching using the GPU (though that should be serialised by the > + * timeline). To be completely sure, and since we are required to > + * do relocations we are already stalling, disable the user's opt > + * out of our synchronisation. > + */ > + ev->flags &= ~EXEC_OBJECT_ASYNC; > + > + /* and update the user's relocation entry */ > + return relocate_entry(eb, ev->vma, reloc, target->vma); > +} > + > +static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > +{ > +#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) > + struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; > + const struct drm_i915_gem_exec_object2 *entry = ev->exec; > + struct drm_i915_gem_relocation_entry __user *urelocs = > + u64_to_user_ptr(entry->relocs_ptr); > + unsigned long remain = entry->relocation_count; > + > + if (unlikely(remain > N_RELOC(ULONG_MAX))) > + return -EINVAL; This has been checked already in eb_reloca_vma_validate. > + > + /* > + * We must check that the entire relocation array is safe > + * to read. However, if the array is not writable the user loses > + * the updated relocation values. > + */ > + if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs)))) > + return -EFAULT; > + > + do { > + struct drm_i915_gem_relocation_entry *r = stack; > + unsigned int count = > + min_t(unsigned long, remain, ARRAY_SIZE(stack)); > + unsigned int copied; > + > + /* > + * This is the fast path and we cannot handle a pagefault > + * whilst holding the struct mutex lest the user pass in the > + * relocations contained within a mmaped bo. For in such a case > + * we, the page fault handler would call i915_gem_fault() and > + * we would try to acquire the struct mutex again. Obviously > + * this is bad and so lockdep complains vehemently. > + */ > + copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); > + if (unlikely(copied)) > + return -EFAULT; > + > + remain -= count; The above two comments end up duplicated which is kind of ugly. Not sure how a common "runner/looper" would look with just the per-reloc body being a passed in function. > + do { > + u64 offset = eb_relocate_entry(eb, ev, r); > + > + if (likely(offset == 0)) { > + } else if ((s64)offset < 0) { > + return (int)offset; > + } else { > + /* > + * Note that reporting an error now > + * leaves everything in an inconsistent > + * state as we have *already* changed > + * the relocation value inside the > + * object. As we have not changed the > + * reloc.presumed_offset or will not > + * change the execobject.offset, on the > + * call we may not rewrite the value > + * inside the object, leaving it > + * dangling and causing a GPU hang. Unless > + * userspace dynamically rebuilds the > + * relocations on each execbuf rather than > + * presume a static tree. > + * > + * We did previously check if the relocations > + * were writable (access_ok), an error now > + * would be a strange race with mprotect, > + * having already demonstrated that we > + * can read from this userspace address. > + */ > + offset = gen8_canonical_addr(offset & ~UPDATE); > + __put_user(offset, > + &urelocs[r - stack].presumed_offset); > + } > + } while (r++, --count); > + urelocs += ARRAY_SIZE(stack); > + } while (remain); > + > + return 0; > +} > + > +static int > +eb_reloc_valid(struct i915_execbuffer *eb, > + struct eb_vma *ev, > + const struct drm_i915_gem_relocation_entry *reloc) It does a bit more than check for validity so if you agree maybe eb_reloc_prepare(_entry)? > { > struct drm_i915_private *i915 = eb->i915; > struct eb_vma *target; > @@ -1408,21 +1519,10 @@ eb_relocate_entry(struct i915_execbuffer *eb, > return -EINVAL; > } > > - /* > - * If we write into the object, we need to force the synchronisation > - * barrier, either with an asynchronous clflush or if we executed the > - * patching using the GPU (though that should be serialised by the > - * timeline). To be completely sure, and since we are required to > - * do relocations we are already stalling, disable the user's opt > - * out of our synchronisation. > - */ > - ev->flags &= ~EXEC_OBJECT_ASYNC; > - > - /* and update the user's relocation entry */ > - return relocate_entry(eb, ev->vma, reloc, target->vma); > + return 1; > } > > -static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > +static long eb_reloc_vma_validate(struct i915_execbuffer *eb, struct eb_vma *ev) > { > #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) > struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; > @@ -1430,6 +1530,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > struct drm_i915_gem_relocation_entry __user *urelocs = > u64_to_user_ptr(entry->relocs_ptr); > unsigned long remain = entry->relocation_count; > + long required = 0; > > if (unlikely(remain > N_RELOC(ULONG_MAX))) > return -EINVAL; > @@ -1462,42 +1563,18 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > > remain -= count; > do { > - u64 offset = eb_relocate_entry(eb, ev, r); > + int ret; > > - if (likely(offset == 0)) { > - } else if ((s64)offset < 0) { > - return (int)offset; > - } else { > - /* > - * Note that reporting an error now > - * leaves everything in an inconsistent > - * state as we have *already* changed > - * the relocation value inside the > - * object. As we have not changed the > - * reloc.presumed_offset or will not > - * change the execobject.offset, on the > - * call we may not rewrite the value > - * inside the object, leaving it > - * dangling and causing a GPU hang. Unless > - * userspace dynamically rebuilds the > - * relocations on each execbuf rather than > - * presume a static tree. > - * > - * We did previously check if the relocations > - * were writable (access_ok), an error now > - * would be a strange race with mprotect, > - * having already demonstrated that we > - * can read from this userspace address. > - */ > - offset = gen8_canonical_addr(offset & ~UPDATE); > - __put_user(offset, > - &urelocs[r - stack].presumed_offset); > - } > + ret = eb_reloc_valid(eb, ev, r); > + if (ret < 0) > + return ret; > + > + required += ret; > } while (r++, --count); > urelocs += ARRAY_SIZE(stack); > } while (remain); > > - return 0; > + return required; > } > > static int eb_relocate(struct i915_execbuffer *eb) > @@ -1516,9 +1593,20 @@ static int eb_relocate(struct i915_execbuffer *eb) > > /* The objects are in their final locations, apply the relocations. */ > if (eb->args->flags & __EXEC_HAS_RELOC) { > - struct eb_vma *ev; > + struct eb_vma *ev, *en; > int flush; > > + list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { > + long count; > + > + count = eb_reloc_vma_validate(eb, ev); > + if (count < 0) > + return count; > + > + if (count == 0) > + list_del_init(&ev->reloc_link); > + } > + > list_for_each_entry(ev, &eb->relocs, reloc_link) { > err = eb_relocate_vma(eb, ev); > if (err) > Regards, Tvrtko From chris at chris-wilson.co.uk Fri Jun 5 15:32:27 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 05 Jun 2020 16:32:27 +0100 Subject: [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting In-Reply-To: <87wo4la69p.fsf@gaia.fi.intel.com> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> <20200605122334.2798-2-chris@chris-wilson.co.uk> <87wo4la69p.fsf@gaia.fi.intel.com> Message-ID: <159137114732.22562.14510475315266373484@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-05 16:20:34) > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > We may choose not to submit for a number of reasons, yet not fill both > > ELSP. In which case we must start timeslicing (there will be no ACK > > event on which to hook the start) if the queue would benefit from the > > currently active context being evicted. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++--- > > 1 file changed, 2 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > > index 92c3368ffcbd..d55a5e0466e5 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > > @@ -2362,10 +2362,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > > if (last->context == rq->context) > > goto done; > > > > - if (i915_request_has_sentinel(last)) { > > - start_timeslice(engine, rq_prio(rq)); > > + if (i915_request_has_sentinel(last)) > > goto done; > > - } > > > > /* > > * If GVT overrides us we only ever submit > > @@ -2446,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > > set_preempt_timeout(engine, *active); > > execlists_submit_ports(engine); > > } else { > > + start_timeslice(engine, execlists->queue_priority_hint); > > If we ended up with same set of request, we want to skip submitting. > But why would we want to skip timeslicing? Because we have already submitted the exact same pair of requests and so there will a be a set_timeslice() either pending or have taken place. In particular, we wanted to stop timeslicing if after a timeslice expiry we submitted exactly the same requests as before the timelice -- we know that until the arrival of a new request that there is no need for a new timeslice, that will just result in the same pair being submitted in order each time. -Chris From mika.kuoppala at linux.intel.com Fri Jun 5 15:30:22 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 05 Jun 2020 18:30:22 +0300 Subject: [Intel-gfx] [PATCH 03/10] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" In-Reply-To: <20200605122334.2798-3-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> <20200605122334.2798-3-chris@chris-wilson.co.uk> Message-ID: <87r1uta5td.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > This was removed in commit 478ffad6d690 ("drm/i915: drop > engine_pin/unpin_breadcrumbs_irq") as the last user had been removed, > but now there is a promise of a new user in the next patch. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22 +++++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_engine.h | 3 +++ > 2 files changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c > index d907d538176e..03c14ab86d95 100644 > --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c > +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c > @@ -220,6 +220,28 @@ static void signal_irq_work(struct irq_work *work) > } > } > > +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine) > +{ > + struct intel_breadcrumbs *b = &engine->breadcrumbs; > + > + spin_lock_irq(&b->irq_lock); > + if (!b->irq_enabled++) > + irq_enable(engine); > + GEM_BUG_ON(!b->irq_enabled); /* no overflow! */ > + spin_unlock_irq(&b->irq_lock); > +} > + > +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine) > +{ > + struct intel_breadcrumbs *b = &engine->breadcrumbs; > + > + spin_lock_irq(&b->irq_lock); > + GEM_BUG_ON(!b->irq_enabled); /* no underflow! */ > + if (!--b->irq_enabled) > + irq_disable(engine); > + spin_unlock_irq(&b->irq_lock); > +} > + > static bool __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b) > { > struct intel_engine_cs *engine = > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 791897f8d847..043462b6ce1f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -226,6 +226,9 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine); > void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); > void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); > > +void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine); > +void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine); > + > void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); > > static inline void > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Fri Jun 5 15:33:19 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 05 Jun 2020 18:33:19 +0300 Subject: [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts In-Reply-To: <20200605122334.2798-4-chris@chris-wilson.co.uk> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> <20200605122334.2798-4-chris@chris-wilson.co.uk> Message-ID: <87o8pxa5og.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > If any engine asks for the tasklet to be kicked from the CS interrupt, > do so. The why part is a bit thin. The plan is to use execlist tasklet for move stuff from virtual rings to real ones? -Mika > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 ++++++++++++----- > drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- > drivers/gpu/drm/i915/i915_irq.c | 8 ++++---- > 4 files changed, 20 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > index 0cc7dd54f4f9..28edf314a319 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > @@ -60,6 +60,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir) > tasklet_hi_schedule(&engine->execlists.tasklet); > } > > +void gen2_engine_cs_irq(struct intel_engine_cs *engine) > +{ > + intel_engine_signal_breadcrumbs(engine); > + if (intel_engine_needs_breadcrumb_tasklet(engine)) > + tasklet_hi_schedule(&engine->execlists.tasklet); > +} > + > static u32 > gen11_gt_engine_identity(struct intel_gt *gt, > const unsigned int bank, const unsigned int bit) > @@ -273,9 +280,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt) > void gen5_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) > { > if (gt_iir & GT_RENDER_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); > + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); > if (gt_iir & ILK_BSD_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); > + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); > } > > static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) > @@ -299,11 +306,11 @@ static void gen7_parity_error_irq_handler(struct intel_gt *gt, u32 iir) > void gen6_gt_irq_handler(struct intel_gt *gt, u32 gt_iir) > { > if (gt_iir & GT_RENDER_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(gt->engine_class[RENDER_CLASS][0]); > + gen2_engine_cs_irq(gt->engine_class[RENDER_CLASS][0]); > if (gt_iir & GT_BSD_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(gt->engine_class[VIDEO_DECODE_CLASS][0]); > + gen2_engine_cs_irq(gt->engine_class[VIDEO_DECODE_CLASS][0]); > if (gt_iir & GT_BLT_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(gt->engine_class[COPY_ENGINE_CLASS][0]); > + gen2_engine_cs_irq(gt->engine_class[COPY_ENGINE_CLASS][0]); > > if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | > GT_BSD_CS_ERROR_INTERRUPT | > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.h b/drivers/gpu/drm/i915/gt/intel_gt_irq.h > index 886c5cf408a2..6c69cd563fe1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.h > @@ -9,6 +9,7 @@ > > #include <linux/types.h> > > +struct intel_engine_cs; > struct intel_gt; > > #define GEN8_GT_IRQS (GEN8_GT_RCS_IRQ | \ > @@ -19,6 +20,8 @@ struct intel_gt; > GEN8_GT_PM_IRQ | \ > GEN8_GT_GUC_IRQ) > > +void gen2_engine_cs_irq(struct intel_engine_cs *engine); > + > void gen11_gt_irq_reset(struct intel_gt *gt); > void gen11_gt_irq_postinstall(struct intel_gt *gt); > void gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl); > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 2f59fc6df3c2..2e4ddc9ca09d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -1741,7 +1741,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir) > return; > > if (pm_iir & PM_VEBOX_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(gt->engine[VECS0]); > + gen2_engine_cs_irq(gt->engine[VECS0]); > > if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) > DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 8e823ba25f5f..b64f3b3bca70 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3686,7 +3686,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) > intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); > > if (iir & I915_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); > + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); > > if (iir & I915_MASTER_ERROR_INTERRUPT) > i8xx_error_irq_handler(dev_priv, eir, eir_stuck); > @@ -3791,7 +3791,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) > I915_WRITE(GEN2_IIR, iir); > > if (iir & I915_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); > + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); > > if (iir & I915_MASTER_ERROR_INTERRUPT) > i9xx_error_irq_handler(dev_priv, eir, eir_stuck); > @@ -3933,10 +3933,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > I915_WRITE(GEN2_IIR, iir); > > if (iir & I915_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); > + gen2_engine_cs_irq(dev_priv->gt.engine[RCS0]); > > if (iir & I915_BSD_USER_INTERRUPT) > - intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); > + gen2_engine_cs_irq(dev_priv->gt.engine[VCS0]); > > if (iir & I915_MASTER_ERROR_INTERRUPT) > i9xx_error_irq_handler(dev_priv, eir, eir_stuck); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Fri Jun 5 15:34:52 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 05 Jun 2020 18:34:52 +0300 Subject: [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting In-Reply-To: <159137114732.22562.14510475315266373484@build.alporthouse.com> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> <20200605122334.2798-2-chris@chris-wilson.co.uk> <87wo4la69p.fsf@gaia.fi.intel.com> <159137114732.22562.14510475315266373484@build.alporthouse.com> Message-ID: <87lfl1a5lv.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Quoting Mika Kuoppala (2020-06-05 16:20:34) >> Chris Wilson <chris at chris-wilson.co.uk> writes: >> >> > We may choose not to submit for a number of reasons, yet not fill both >> > ELSP. In which case we must start timeslicing (there will be no ACK >> > event on which to hook the start) if the queue would benefit from the >> > currently active context being evicted. >> > >> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >> > --- >> > drivers/gpu/drm/i915/gt/intel_lrc.c | 5 ++--- >> > 1 file changed, 2 insertions(+), 3 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c >> > index 92c3368ffcbd..d55a5e0466e5 100644 >> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >> > @@ -2362,10 +2362,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) >> > if (last->context == rq->context) >> > goto done; >> > >> > - if (i915_request_has_sentinel(last)) { >> > - start_timeslice(engine, rq_prio(rq)); >> > + if (i915_request_has_sentinel(last)) >> > goto done; >> > - } >> > >> > /* >> > * If GVT overrides us we only ever submit >> > @@ -2446,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) >> > set_preempt_timeout(engine, *active); >> > execlists_submit_ports(engine); >> > } else { >> > + start_timeslice(engine, execlists->queue_priority_hint); >> >> If we ended up with same set of request, we want to skip submitting. >> But why would we want to skip timeslicing? > > Because we have already submitted the exact same pair of requests > and so there will a be a set_timeslice() either pending or have taken > place. In particular, we wanted to stop timeslicing if after a timeslice > expiry we submitted exactly the same requests as before the timelice -- > we know that until the arrival of a new request that there is no need > for a new timeslice, that will just result in the same pair being > submitted in order each time. Makes sense. I managed look over the set_timeslice. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > -Chris From chris at chris-wilson.co.uk Fri Jun 5 15:38:25 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 05 Jun 2020 16:38:25 +0100 Subject: [Intel-gfx] [PATCH 2/5] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <8c33c119-0d7f-6897-c697-c0e95a7e0bc5@linux.intel.com> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> <20200605095858.28455-2-chris@chris-wilson.co.uk> <8c33c119-0d7f-6897-c697-c0e95a7e0bc5@linux.intel.com> Message-ID: <159137150578.22562.7904269772462642978@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-05 16:27:26) > > On 05/06/2020 10:58, Chris Wilson wrote: > > Over the next couple of patches, we will want to lock all the modified > > vma for relocation processing under a single ww_mutex. We neither want > > to have to include the vma that are skipped (due to no modifications > > required) nor do we want those to be marked as written too. So separate > > out the reloc validation into an early step, which we can use both to > > reject the execbuf before committing to making our changes, and to > > filter out the unmodified vma. > > > > This does introduce a second pass through the reloc[], but only if we > > need to emit relocations. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 178 +++++++++++++----- > > 1 file changed, 133 insertions(+), 45 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > index cfe6d2cdbef1..7d4464fddca8 100644 > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > @@ -1331,6 +1331,117 @@ static u64 > > eb_relocate_entry(struct i915_execbuffer *eb, > > struct eb_vma *ev, > > const struct drm_i915_gem_relocation_entry *reloc) > > +{ > > + struct eb_vma *target; > > + > > + /* we've already hold a reference to all valid objects */ > > + target = eb_get_vma(eb, reloc->target_handle); > > + if (unlikely(!target)) > > + return -ENOENT; > > + > > + /* > > + * If the relocation already has the right value in it, no > > + * more work needs to be done. > > + */ > > + if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) > > + return 0; > > These have been filtered out, no? Only if the entire execobj->reloc[] was skipped. If some skipped and some did not, we may end up here. > > > + > > + /* > > + * If we write into the object, we need to force the synchronisation > > + * barrier, either with an asynchronous clflush or if we executed the > > + * patching using the GPU (though that should be serialised by the > > + * timeline). To be completely sure, and since we are required to > > + * do relocations we are already stalling, disable the user's opt > > + * out of our synchronisation. > > + */ > > + ev->flags &= ~EXEC_OBJECT_ASYNC; > > + > > + /* and update the user's relocation entry */ > > + return relocate_entry(eb, ev->vma, reloc, target->vma); > > +} > > + > > +static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > > +{ > > +#define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) > > + struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; > > + const struct drm_i915_gem_exec_object2 *entry = ev->exec; > > + struct drm_i915_gem_relocation_entry __user *urelocs = > > + u64_to_user_ptr(entry->relocs_ptr); > > + unsigned long remain = entry->relocation_count; > > + > > + if (unlikely(remain > N_RELOC(ULONG_MAX))) > > + return -EINVAL; > > This has been checked already in eb_reloca_vma_validate. Ok. It didn't even register. > > > + > > + /* > > + * We must check that the entire relocation array is safe > > + * to read. However, if the array is not writable the user loses > > + * the updated relocation values. > > + */ > > + if (unlikely(!access_ok(urelocs, remain * sizeof(*urelocs)))) > > + return -EFAULT; > > + > > + do { > > + struct drm_i915_gem_relocation_entry *r = stack; > > + unsigned int count = > > + min_t(unsigned long, remain, ARRAY_SIZE(stack)); > > + unsigned int copied; > > + > > + /* > > + * This is the fast path and we cannot handle a pagefault > > + * whilst holding the struct mutex lest the user pass in the > > + * relocations contained within a mmaped bo. For in such a case > > + * we, the page fault handler would call i915_gem_fault() and > > + * we would try to acquire the struct mutex again. Obviously > > + * this is bad and so lockdep complains vehemently. > > + */ > > + copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); > > + if (unlikely(copied)) > > + return -EFAULT; > > + > > + remain -= count; > > The above two comments end up duplicated which is kind of ugly. Not sure > how a common "runner/looper" would look with just the per-reloc body > being a passed in function. I looked and thought it would just be the outer pair of loops being saved. Still probably worth it, but it felt like more work than cut'n'paste! > > > + do { > > + u64 offset = eb_relocate_entry(eb, ev, r); > > + > > + if (likely(offset == 0)) { > > + } else if ((s64)offset < 0) { > > + return (int)offset; > > + } else { > > + /* > > + * Note that reporting an error now > > + * leaves everything in an inconsistent > > + * state as we have *already* changed > > + * the relocation value inside the > > + * object. As we have not changed the > > + * reloc.presumed_offset or will not > > + * change the execobject.offset, on the > > + * call we may not rewrite the value > > + * inside the object, leaving it > > + * dangling and causing a GPU hang. Unless > > + * userspace dynamically rebuilds the > > + * relocations on each execbuf rather than > > + * presume a static tree. > > + * > > + * We did previously check if the relocations > > + * were writable (access_ok), an error now > > + * would be a strange race with mprotect, > > + * having already demonstrated that we > > + * can read from this userspace address. > > + */ > > + offset = gen8_canonical_addr(offset & ~UPDATE); > > + __put_user(offset, > > + &urelocs[r - stack].presumed_offset); > > + } > > + } while (r++, --count); > > + urelocs += ARRAY_SIZE(stack); > > + } while (remain); > > + > > + return 0; > > +} > > + > > +static int > > +eb_reloc_valid(struct i915_execbuffer *eb, > > + struct eb_vma *ev, > > + const struct drm_i915_gem_relocation_entry *reloc) > > It does a bit more than check for validity so if you agree maybe > eb_reloc_prepare(_entry)? You mean the deeply buried gen6 w/a eb_reloc_prepare doesn't sound too bad. -Chris From patchwork at emeril.freedesktop.org Fri Jun 5 15:39:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 15:39:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_comments_mentioning_typo_in_IS=5FENABLED=28=29?= In-Reply-To: <202006050718.9D4FCFC2E@keescook> References: <202006050718.9D4FCFC2E@keescook> Message-ID: <159137156202.18507.4812611255695179700@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix comments mentioning typo in IS_ENABLED() URL : https://patchwork.freedesktop.org/series/78044/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17888 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/index.html Known issues ------------ Here are the changes found in Patchwork_17888 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-byt-n2820/igt at i915_module_load@reload.html - fi-tgl-y: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-tgl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at active: - fi-whl-u: [DMESG-FAIL][13] ([i915#666]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_selftest@live at active.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-whl-u/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_busy@basic at flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17888 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17888: f6f5eb4457be93abbc43374cbb6e2c6cca6f2035 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f6f5eb4457be drm/i915: Fix comments mentioning typo in IS_ENABLED() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/index.html From chris at chris-wilson.co.uk Fri Jun 5 15:40:14 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 05 Jun 2020 16:40:14 +0100 Subject: [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts In-Reply-To: <87o8pxa5og.fsf@gaia.fi.intel.com> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> <20200605122334.2798-4-chris@chris-wilson.co.uk> <87o8pxa5og.fsf@gaia.fi.intel.com> Message-ID: <159137161429.22562.587818863316529518@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-05 16:33:19) > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > If any engine asks for the tasklet to be kicked from the CS interrupt, > > do so. > > The why part is a bit thin. The plan is to use execlist tasklet > for move stuff from virtual rings to real ones? Yes. I thought that part was self explanatory, since we're coupling up a call to engine->execlists.tasklet if the engine opts into receiving the interrupt. -Chris From jose.souza at intel.com Fri Jun 5 15:44:01 2020 From: jose.souza at intel.com (Souza, Jose) Date: Fri, 5 Jun 2020 15:44:01 +0000 Subject: [Intel-gfx] [PATCH v2] drm/i915/psr: Program default IO buffer Wake and Fast Wake In-Reply-To: <20200605140422.280195-1-gwan-gyeong.mun@intel.com> References: <20200605140422.280195-1-gwan-gyeong.mun@intel.com> Message-ID: <06259c0d05d5c8050db4c93f74472cd22bfc2b77.camel@intel.com> On Fri, 2020-06-05 at 17:04 +0300, Gwan-gyeong Mun wrote: > The IO buffer Wake and Fast Wake bit size and value have been changed from > Gen12+. It programs the default value of IO buffer Wake and Fast Wake on > Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 > and Gen12+. And it aligns PSR2 definition macros. > > v2: Fix macro definitions. (Jos?) > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 12 +++++ > drivers/gpu/drm/i915/i915_reg.h | 68 +++++++++++++++++------- > 2 files changed, 61 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 7a0011e42e00..765740d2f32f 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -537,6 +537,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); > val |= intel_psr2_get_tp_time(intel_dp); > > + if (INTEL_GEN(dev_priv) >= 12) { > + /* > + * TODO: In order to setting an optimal power consumption, > + * lower than 4k resoluition mode needs to decrese IO_BUFFER_WAKE > + * and FAST_WAKE. And higher than 4K resolution mode needs > + * to increase IO_BUFFER_WAKE and FAST_WAKE. > + */ > + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; Better to update the comment above saying that you are setting the default values and not the optimal ones and remove this 2 comments. > + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE_7lines; /* default BSpec value */ > + val |= TGL_EDP_PSR2_FAST_WAKE_7lines; /* default BSpec value */ > + } Missing set the default values for GEN9. > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > * recommending keep this bit unset while PSR2 is enabled. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 814a70945468..bf8988e9ff70 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4511,25 +4511,55 @@ enum { > #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ > #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ > > -#define _PSR2_CTL_A 0x60900 > -#define _PSR2_CTL_EDP 0x6f900 > -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > -#define EDP_PSR2_ENABLE (1 << 31) > -#define EDP_SU_TRACK_ENABLE (1 << 30) > -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > -#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > -#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > -#define EDP_PSR2_TP2_TIME_500us (0 << 8) > -#define EDP_PSR2_TP2_TIME_100us (1 << 8) > -#define EDP_PSR2_TP2_TIME_2500us (2 << 8) > -#define EDP_PSR2_TP2_TIME_50us (3 << 8) > -#define EDP_PSR2_TP2_TIME_MASK (3 << 8) > -#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > -#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) > -#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) > -#define EDP_PSR2_IDLE_FRAME_MASK 0xf > -#define EDP_PSR2_IDLE_FRAME_SHIFT 0 > +#define _PSR2_CTL_A 0x60900 > +#define _PSR2_CTL_EDP 0x6f900 > +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > +#define EDP_PSR2_ENABLE (1 << 31) > +#define EDP_SU_TRACK_ENABLE (1 << 30) > +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) > +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) > +#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > +#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > +#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > +#define EDP_PSR2_IO_BUFFER_WAKE_5lines (3 << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_6lines (2 << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_7lines (1 << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_8lines (0 << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_5lines (0 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_6lines (1 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_7lines (2 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_8lines (3 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_9lines (4 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_10lines (5 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_11lines (6 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_12lines (7 << 13) Not wrong but you could have something like: #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) ((lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) Macro users will be responsible to check and not use a number of lines lower than TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES. Same for fast wake. > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) > +#define EDP_PSR2_FAST_WAKE_5lines (3 << 11) > +#define EDP_PSR2_FAST_WAKE_6lines (2 << 11) > +#define EDP_PSR2_FAST_WAKE_7lines (1 << 11) > +#define EDP_PSR2_FAST_WAKE_8lines (0 << 11) > +#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) > +#define TGL_EDP_PSR2_FAST_WAKE_5lines (0 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_6lines (1 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_7lines (2 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_8lines (3 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_9lines (4 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_10lines (5 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_11lines (6 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_12lines (7 << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) > +#define EDP_PSR2_TP2_TIME_500us (0 << 8) > +#define EDP_PSR2_TP2_TIME_100us (1 << 8) > +#define EDP_PSR2_TP2_TIME_2500us (2 << 8) > +#define EDP_PSR2_TP2_TIME_50us (3 << 8) > +#define EDP_PSR2_TP2_TIME_MASK (3 << 8) > +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) > +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) > +#define EDP_PSR2_IDLE_FRAME_MASK 0xf > +#define EDP_PSR2_IDLE_FRAME_SHIFT 0 > > #define _PSR_EVENT_TRANS_A 0x60848 > #define _PSR_EVENT_TRANS_B 0x61848 From mika.kuoppala at linux.intel.com Fri Jun 5 15:43:26 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 05 Jun 2020 18:43:26 +0300 Subject: [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts In-Reply-To: <159137161429.22562.587818863316529518@build.alporthouse.com> References: <20200605122334.2798-1-chris@chris-wilson.co.uk> <20200605122334.2798-4-chris@chris-wilson.co.uk> <87o8pxa5og.fsf@gaia.fi.intel.com> <159137161429.22562.587818863316529518@build.alporthouse.com> Message-ID: <87img5a57l.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Quoting Mika Kuoppala (2020-06-05 16:33:19) >> Chris Wilson <chris at chris-wilson.co.uk> writes: >> >> > If any engine asks for the tasklet to be kicked from the CS interrupt, >> > do so. >> >> The why part is a bit thin. The plan is to use execlist tasklet >> for move stuff from virtual rings to real ones? > > Yes. I thought that part was self explanatory, since we're coupling up a > call to engine->execlists.tasklet if the engine opts into receiving the Reading further into series it is obvious, but you can carry the plot further in here already! "Aim is to mimic execlist port type submission and hopefully gain opportunities for code sharing"... Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > interrupt. > -Chris From patchwork at emeril.freedesktop.org Fri Jun 5 15:47:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 15:47:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake_=28re?= =?utf-8?b?djIp?= In-Reply-To: <20200605140422.280195-1-gwan-gyeong.mun@intel.com> References: <20200605140422.280195-1-gwan-gyeong.mun@intel.com> Message-ID: <159137203736.18508.1802712635744304390@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev2) URL : https://patchwork.freedesktop.org/series/78019/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17887_full ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_17887_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17887_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17887_full: ### IGT changes ### #### Warnings #### * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-hsw: [INCOMPLETE][1] ([i915#61]) -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-hsw6/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html New tests --------- New tests have been introduced between CI_DRM_8590_full and Patchwork_17887_full: ### New IGT tests (14) ### * igt at gem_exec_balancer@bonded-cork: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.20] s * igt at gem_exec_balancer@bonded-imm: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 9.79] s * igt at gem_exec_balancer@busy: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 5.07] s * igt at gem_exec_balancer@full: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.50] s * igt at gem_exec_balancer@full-late: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.29] s * igt at gem_exec_balancer@full-late-pulse: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.45] s * igt at gem_exec_balancer@full-pulse: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.54] s * igt at gem_exec_balancer@indices: - Statuses : 5 pass(s) 2 skip(s) - Exec time: [0.0, 10.25] s * igt at gem_exec_balancer@individual: - Statuses : - Exec time: [None] s * igt at gem_exec_balancer@invalid-balancer: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.02] s * igt at gem_exec_balancer@invalid-bonds: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 0.04] s * igt at gem_exec_balancer@nop: - Statuses : 5 pass(s) 2 skip(s) - Exec time: [0.0, 49.59] s * igt at gem_exec_balancer@semaphore: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 9.77] s * igt at gem_exec_balancer@smoke: - Statuses : 5 pass(s) 2 skip(s) - Exec time: [0.0, 23.02] s Known issues ------------ Here are the changes found in Patchwork_17887_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_flush@basic-wb-prw-default: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at gem_exec_flush@basic-wb-prw-default.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-glk6/igt at gem_exec_flush@basic-wb-prw-default.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb7/igt at i915_pm_dc@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-iclb4/igt at i915_pm_dc@dc6-psr.html * igt at i915_suspend@forcewake: - shard-apl: [PASS][7] -> [INCOMPLETE][8] ([i915#1630]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl3/igt at i915_suspend@forcewake.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl3/igt at i915_suspend@forcewake.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-glk8/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl8/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +12 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl1/igt at kms_color@pipe-c-ctm-0-25.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl4/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [PASS][17] -> [TIMEOUT][18] ([i915#1958]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-snb1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb5/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +14 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#93] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#49]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-iclb3/igt at kms_psr@psr2_cursor_blt.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +8 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#402]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl8/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][41] ([i915#1930]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-normal-all: - shard-glk: [DMESG-WARN][43] ([i915#118] / [i915#95]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk7/igt at gem_exec_whisper@basic-normal-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-glk5/igt at gem_exec_whisper@basic-normal-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][45] ([i915#1436] / [i915#716]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl1/igt at gen9_exec_parse@allowed-all.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl6/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][49] ([i915#54]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl5/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl2/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][53] ([i915#79]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +15 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl2/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +5 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: - shard-skl: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +3 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-skl9/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb5/igt at kms_psr@psr2_cursor_plane_move.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][69] ([i915#31]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl1/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb5/igt at perf@blocking-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-iclb2/igt at perf@blocking-parameterized.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][73] ([i915#1542]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-hsw7/igt at perf@polling-parameterized.html #### Warnings #### * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [SKIP][75] ([fdo#109271] / [fdo#111827]) -> [INCOMPLETE][76] ([CI#80] / [i915#82]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-snb1/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][77] ([fdo#110321] / [fdo#110336]) -> [DMESG-FAIL][78] ([fdo#110321]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][79] ([fdo#110321]) -> [TIMEOUT][80] ([i915#1319]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl7/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][81] ([fdo#110321] / [i915#95]) -> [TIMEOUT][82] ([i915#1319]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl1/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][83] ([fdo#110321] / [i915#95]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl8/igt at kms_content_protection@srm.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl6/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][85] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][86] ([i915#93] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html - shard-apl: [DMESG-WARN][87] ([i915#180] / [i915#95]) -> [DMESG-WARN][88] ([i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-apl1/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [SKIP][89] ([fdo#109271]) -> [TIMEOUT][90] ([i915#1958]) +2 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/shard-snb1/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1630]: https://gitlab.freedesktop.org/drm/intel/issues/1630 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17887 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17887: 2553fbc0995b01bd08a3a732dfe008cae98fb915 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17887/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 16:07:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 16:07:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Include_the_engine=27s_fw-domains_in_the_debug_info?= In-Reply-To: <20200605144705.31127-1-chris@chris-wilson.co.uk> References: <20200605144705.31127-1-chris@chris-wilson.co.uk> Message-ID: <159137324319.18509.1049441143580277662@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Include the engine's fw-domains in the debug info URL : https://patchwork.freedesktop.org/series/78048/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590 -> Patchwork_17889 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/index.html Known issues ------------ Here are the changes found in Patchwork_17889 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-j1900/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-byt-n2820/igt at i915_module_load@reload.html - fi-tgl-y: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-y/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-tgl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at active: - fi-whl-u: [DMESG-FAIL][11] ([i915#666]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-whl-u/igt at i915_selftest@live at active.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-whl-u/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1}: - fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17889 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17889: 82bcf6d36ac4669b3b4b6b9a1b5b02fb2584c8bc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 82bcf6d36ac4 drm/i915/gt: Include the engine's fw-domains in the debug info == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/index.html From chris at chris-wilson.co.uk Fri Jun 5 16:07:18 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 17:07:18 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <20200605095858.28455-2-chris@chris-wilson.co.uk> References: <20200605095858.28455-2-chris@chris-wilson.co.uk> Message-ID: <20200605160718.8676-1-chris@chris-wilson.co.uk> Over the next couple of patches, we will want to lock all the modified vma for relocation processing under a single ww_mutex. We neither want to have to include the vma that are skipped (due to no modifications required) nor do we want those to be marked as written too. So separate out the reloc validation into an early step, which we can use both to reject the execbuf before committing to making our changes, and to filter out the unmodified vma. This does introduce a second pass through the reloc[], but only if we need to emit relocations. v2: reuse the outer loop, not cut'n'paste. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 145 +++++++++++------- 1 file changed, 86 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index cfe6d2cdbef1..7b9785754a25 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -911,9 +911,9 @@ static void eb_destroy(const struct i915_execbuffer *eb) static inline u64 relocation_target(const struct drm_i915_gem_relocation_entry *reloc, - const struct i915_vma *target) + u64 target) { - return gen8_canonical_addr((int)reloc->delta + target->node.start); + return gen8_canonical_addr((int)reloc->delta + target); } static void reloc_cache_init(struct reloc_cache *cache, @@ -1311,26 +1311,11 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, return 0; } -static u64 -relocate_entry(struct i915_execbuffer *eb, - struct i915_vma *vma, - const struct drm_i915_gem_relocation_entry *reloc, - const struct i915_vma *target) -{ - u64 target_addr = relocation_target(reloc, target); - int err; - - err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); - if (err) - return err; - - return target->node.start | UPDATE; -} - -static u64 -eb_relocate_entry(struct i915_execbuffer *eb, - struct eb_vma *ev, - const struct drm_i915_gem_relocation_entry *reloc) +static int +eb_reloc_prepare(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc, + struct drm_i915_gem_relocation_entry __user *user) { struct drm_i915_private *i915 = eb->i915; struct eb_vma *target; @@ -1408,6 +1393,32 @@ eb_relocate_entry(struct i915_execbuffer *eb, return -EINVAL; } + return 1; +} + +static int +eb_reloc_entry(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc, + struct drm_i915_gem_relocation_entry __user *user) +{ + struct eb_vma *target; + u64 offset; + int err; + + /* we've already hold a reference to all valid objects */ + target = eb_get_vma(eb, reloc->target_handle); + if (unlikely(!target)) + return -ENOENT; + + /* + * If the relocation already has the right value in it, no + * more work needs to be done. + */ + offset = gen8_canonical_addr(target->vma->node.start); + if (offset == reloc->presumed_offset) + return 0; + /* * If we write into the object, we need to force the synchronisation * barrier, either with an asynchronous clflush or if we executed the @@ -1418,11 +1429,41 @@ eb_relocate_entry(struct i915_execbuffer *eb, */ ev->flags &= ~EXEC_OBJECT_ASYNC; - /* and update the user's relocation entry */ - return relocate_entry(eb, ev->vma, reloc, target->vma); + err = __reloc_entry_gpu(eb, ev->vma, reloc->offset, + relocation_target(reloc, offset)); + if (err) + return err; + + /* + * Note that reporting an error now + * leaves everything in an inconsistent + * state as we have *already* changed + * the relocation value inside the + * object. As we have not changed the + * reloc.presumed_offset or will not + * change the execobject.offset, on the + * call we may not rewrite the value + * inside the object, leaving it + * dangling and causing a GPU hang. Unless + * userspace dynamically rebuilds the + * relocations on each execbuf rather than + * presume a static tree. + * + * We did previously check if the relocations + * were writable (access_ok), an error now + * would be a strange race with mprotect, + * having already demonstrated that we + * can read from this userspace address. + */ + __put_user(offset, &user->presumed_offset); + return 0; } -static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +static long eb_reloc_vma(struct i915_execbuffer *eb, struct eb_vma *ev, + int (*fn)(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc, + struct drm_i915_gem_relocation_entry __user *user)) { #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; @@ -1430,6 +1471,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) struct drm_i915_gem_relocation_entry __user *urelocs = u64_to_user_ptr(entry->relocs_ptr); unsigned long remain = entry->relocation_count; + int required = 0; if (unlikely(remain > N_RELOC(ULONG_MAX))) return -EINVAL; @@ -1462,42 +1504,18 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) remain -= count; do { - u64 offset = eb_relocate_entry(eb, ev, r); + int ret; - if (likely(offset == 0)) { - } else if ((s64)offset < 0) { - return (int)offset; - } else { - /* - * Note that reporting an error now - * leaves everything in an inconsistent - * state as we have *already* changed - * the relocation value inside the - * object. As we have not changed the - * reloc.presumed_offset or will not - * change the execobject.offset, on the - * call we may not rewrite the value - * inside the object, leaving it - * dangling and causing a GPU hang. Unless - * userspace dynamically rebuilds the - * relocations on each execbuf rather than - * presume a static tree. - * - * We did previously check if the relocations - * were writable (access_ok), an error now - * would be a strange race with mprotect, - * having already demonstrated that we - * can read from this userspace address. - */ - offset = gen8_canonical_addr(offset & ~UPDATE); - __put_user(offset, - &urelocs[r - stack].presumed_offset); - } + ret = fn(eb, ev, r, &urelocs[r - stack]); + if (ret < 0) + return ret; + + required |= ret; } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); - return 0; + return required; } static int eb_relocate(struct i915_execbuffer *eb) @@ -1516,12 +1534,21 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { - struct eb_vma *ev; + struct eb_vma *ev, *en; int flush; + list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { + err = eb_reloc_vma(eb, ev, eb_reloc_prepare); + if (err < 0) + return err; + + if (err == 0) + list_del_init(&ev->reloc_link); + } + list_for_each_entry(ev, &eb->relocs, reloc_link) { - err = eb_relocate_vma(eb, ev); - if (err) + err = eb_reloc_vma(eb, ev, eb_reloc_entry); + if (err < 0) break; } -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 5 16:52:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 17:52:58 +0100 Subject: [Intel-gfx] [CI] drm/i915: Discard a misplaced GGTT vma Message-ID: <20200605165258.1483-1-chris@chris-wilson.co.uk> Across the many users of the GGTT vma (internal objects, mmapings, display etc), we may end up with conflicting requirements for the placement. Currently, we try to resolve the conflict by unbinding the vma and rebinding it to match the new constraints; over time we will end up with a GGTT that matches the most strict constraints over all concurrent users. However, this causes a problem if the vma is currently in use as we must wait until it is idle before moving it. But there is no restriction on the number of views we may use (apart from the limited size of the GGTT itself), and so if the active vma does not meet our requirements, try and build a new one! Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 45 +++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0cbcb9f54e7d..f1acd1889d37 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -933,6 +933,45 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915) } } +static bool +discard_ggtt_vma(struct i915_vma *vma, const struct i915_ggtt_view *view) +{ + const struct i915_ggtt_view discard = { + .type = I915_GGTT_VIEW_PARTIAL, + }; + struct drm_i915_gem_object *obj = vma->obj; + + spin_lock(&obj->vma.lock); + if (i915_vma_compare(vma, vma->vm, &discard)) { + struct rb_node *rb, **p; + + rb_erase(&vma->obj_node, &obj->vma.tree); + vma->ggtt_view = discard; + GEM_BUG_ON(i915_vma_compare(vma, vma->vm, view)); + + rb = NULL; + p = &obj->vma.tree.rb_node; + while (*p) { + struct i915_vma *pos; + long cmp; + + rb = *p; + pos = rb_entry(rb, struct i915_vma, obj_node); + + cmp = i915_vma_compare(pos, vma->vm, &discard); + if (cmp < 0) + p = &rb->rb_right; + else + p = &rb->rb_left; + } + rb_link_node(&vma->obj_node, rb, p); + rb_insert_color(&vma->obj_node, &obj->vma.tree); + } + spin_unlock(&obj->vma.lock); + + return i915_vma_compare(vma, vma->vm, view); +} + struct i915_vma * i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, @@ -979,6 +1018,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return ERR_PTR(-ENOSPC); } +new_vma: vma = i915_vma_instance(obj, &ggtt->vm, view); if (IS_ERR(vma)) return vma; @@ -993,6 +1033,11 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return ERR_PTR(-ENOSPC); } + if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) { + if (discard_ggtt_vma(vma, view)) + goto new_vma; + } + ret = i915_vma_unbind(vma); if (ret) return ERR_PTR(ret); -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 5 16:58:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 16:58:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBz?= =?utf-8?q?eries_starting_with_=5B1/5=5D_drm/i915=3A_Add_list=5Ffor=5Feach?= =?utf-8?q?=5Fentry=5Fsafe=5Fcontinue=5Freverse_=28rev2=29?= In-Reply-To: <20200605095858.28455-1-chris@chris-wilson.co.uk> References: <20200605095858.28455-1-chris@chris-wilson.co.uk> Message-ID: <159137629785.18509.513731909955759287@emeril.freedesktop.org> == Series Details == Series: series starting with [1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse (rev2) URL : https://patchwork.freedesktop.org/series/78031/ State : failure == Summary == Applying: drm/i915: Add list_for_each_entry_safe_continue_reverse Applying: drm/i915/gem: Separate reloc validation into an earlier step Applying: drm/i915/gem: Lift GPU relocation allocation Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 drm/i915/gem: Lift GPU relocation allocation When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From andriy.shevchenko at linux.intel.com Fri Jun 5 17:09:31 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Fri, 5 Jun 2020 20:09:31 +0300 Subject: [Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) In-Reply-To: <ba931618-9259-aca0-142c-c1dfb67e737e@redhat.com> References: <20200602122130.45630-1-hdegoede@redhat.com> <20200602152317.GI2428291@smile.fi.intel.com> <ba931618-9259-aca0-142c-c1dfb67e737e@redhat.com> Message-ID: <20200605170931.GR2428291@smile.fi.intel.com> On Fri, Jun 05, 2020 at 04:33:47PM +0200, Hans de Goede wrote: > On 6/2/20 5:23 PM, Andy Shevchenko wrote: > > On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote: > > > The pins on the Bay Trail SoC have separate input-buffer and output-buffer > > > enable bits and a read of the level bit of the value register will always > > > return the value from the input-buffer. > > > > > > The BIOS of a device may configure a pin in output-only mode, only enabling > > > the output buffer, and write 1 to the level bit to drive the pin high. > > > This 1 written to the level bit will be stored inside the data-latch of the > > > output buffer. > > > > > > But a subsequent read of the value register will return 0 for the level bit > > > because the input-buffer is disabled. This causes a read-modify-write as > > > done by byt_gpio_set_direction() to write 0 to the level bit, driving the > > > pin low! > > > > > > Before this commit byt_gpio_direction_output() relied on > > > pinctrl_gpio_direction_output() to set the direction, followed by a call > > > to byt_gpio_set() to apply the selected value. This causes the pin to > > > go low between the pinctrl_gpio_direction_output() and byt_gpio_set() > > > calls. > > > > > > Change byt_gpio_direction_output() to directly make the register > > > modifications itself instead. Replacing the 2 subsequent writes to the > > > value register with a single write. > > > > > > Note that the pinctrl code does not keep track internally of the direction, > > > so not going through pinctrl_gpio_direction_output() is not an issue. > > > > > > This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is > > > already on at boot (no external monitor connected), then the i915 driver > > > does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The > > > temporarily going low of that GPIO was causing the panel to reset itself > > > after which it would not show an image until it was turned off and back on > > > again (until a full modeset was done on it). This commit fixes this. > > > > No Fixes tag? > > It is sort of hard to pin the introduction of this down to a single > commit. If I were to guess, I guess the commit introducing the driver? Why not? Good guess to me (but I think rather the one which converts GPIO driver to pin control). ... > > > + /* > > > + * Before making any direction modifications, do a check if gpio is set > > > > > + * for direct IRQ. On baytrail, setting GPIO to output does not make > > > > Since we change this, perhaps > > > > 'IRQ. On baytrail' -> 'IRQ. On Baytrail' (one space and capital 'B'). > > Sure, not sure if that is worth respinning the patch for though, > either way let me know. I think makes sense to respin. We still have time. > > > + * sense, so let's at least inform the caller before they shoot > > > + * themselves in the foot. > > > + */ ... > > Wouldn't be simple below fix the issue? > No that will not help the pin is already high, but any reads > of the register will return the BYT_LEVEL bit as being low, so > the read-write-modify done when setting the direction reads BYT_LEVEL > as 0 and writes it back as such. So, if I read documentation correctly, there is no means to read back current output value if input is disabled. Alas, quite a bad design of hardware. And on top of that likely nobody has tested that on non-Windows platform. > So your proposal would actually make the problem much worse (and more > obvious) if we do the byt_gpio_set() first then for pins which have > there input-buffer initially disabled, the value passed to > byt_gpio_direction_output will be completely ignored and they will > always end up as being driven low. What I proposed is not gonna work AFAIU documentation. Btw, can we for sake of consistency update direction_input() as well? -- With Best Regards, Andy Shevchenko From patchwork at emeril.freedesktop.org Fri Jun 5 17:15:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 17:15:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_comments_mentioning_typo_in_IS=5FENABLED=28=29?= In-Reply-To: <202006050718.9D4FCFC2E@keescook> References: <202006050718.9D4FCFC2E@keescook> Message-ID: <159137731214.18508.5808059313404731727@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix comments mentioning typo in IS_ENABLED() URL : https://patchwork.freedesktop.org/series/78044/ State : success == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17888_full ==================================================== Summary ------- **SUCCESS** No regressions found. New tests --------- New tests have been introduced between CI_DRM_8590_full and Patchwork_17888_full: ### New IGT tests (14) ### * igt at gem_exec_balancer@bonded-cork: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.11] s * igt at gem_exec_balancer@bonded-imm: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 9.77] s * igt at gem_exec_balancer@busy: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 5.08] s * igt at gem_exec_balancer@full: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.29] s * igt at gem_exec_balancer@full-late: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.39] s * igt at gem_exec_balancer@full-late-pulse: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.48] s * igt at gem_exec_balancer@full-pulse: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.54] s * igt at gem_exec_balancer@indices: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.19] s * igt at gem_exec_balancer@individual: - Statuses : 1 skip(s) - Exec time: [0.0] s * igt at gem_exec_balancer@invalid-balancer: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.07] s * igt at gem_exec_balancer@invalid-bonds: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 0.04] s * igt at gem_exec_balancer@nop: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 45.82] s * igt at gem_exec_balancer@semaphore: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 9.92] s * igt at gem_exec_balancer@smoke: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 23.00] s Known issues ------------ Here are the changes found in Patchwork_17888_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl4/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl7/igt at gem_exec_suspend@basic-s3.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk8/igt at gem_exec_whisper@basic-contexts-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-glk8/igt at gem_exec_whisper@basic-contexts-forked.html * igt at gem_tiled_pread_basic: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +17 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl3/igt at gem_tiled_pread_basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl6/igt at gem_tiled_pread_basic.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at i915_suspend@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at i915_suspend@forcewake: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#58] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk8/igt at i915_suspend@forcewake.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-glk2/igt at i915_suspend@forcewake.html - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#636] / [i915#69]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl1/igt at i915_suspend@forcewake.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl7/igt at i915_suspend@forcewake.html * igt at kms_big_fb@x-tiled-32bpp-rotate-0: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl2/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk4/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-glk6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [PASS][21] -> [DMESG-FAIL][22] ([i915#54] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][23] -> [FAIL][24] ([i915#57]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw4/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#62] / [i915#92]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#49]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl8/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-iclb8/igt at kms_psr@psr2_cursor_blt.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-d: - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb1/igt at kms_universal_plane@universal-plane-gen9-features-pipe-d.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-tglb8/igt at kms_universal_plane@universal-plane-gen9-features-pipe-d.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_eio@in-flight-suspend: - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl4/igt at gem_eio@in-flight-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl1/igt at gem_eio@in-flight-suspend.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][41] ([i915#1930]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-normal-all: - shard-glk: [DMESG-WARN][43] ([i915#118] / [i915#95]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk7/igt at gem_exec_whisper@basic-normal-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-glk2/igt at gem_exec_whisper@basic-normal-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][45] ([i915#1436] / [i915#716]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl6/igt at gen9_exec_parse@allowed-all.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [INCOMPLETE][47] ([i915#155]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl2/igt at i915_suspend@debugfs-reader.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][49] ([i915#93] / [i915#95]) -> [PASS][50] +4 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][51] ([i915#54]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl2/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][53] ([i915#128]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl5/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-glk5/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [FAIL][57] ([i915#49]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl2/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * {igt at kms_getfb@getfb2-handle-protection}: - shard-apl: [DMESG-WARN][59] ([i915#95]) -> [PASS][60] +22 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_getfb@getfb2-handle-protection.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl8/igt at kms_getfb@getfb2-handle-protection.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][63] ([fdo#109642] / [fdo#111068]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb1/igt at kms_psr2_su@frontbuffer.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][65] ([i915#31]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl1/igt at kms_setmode@basic.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][67] ([i915#1542]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-hsw2/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_rpm@reg-read-ioctl: - shard-kbl: [DMESG-WARN][69] ([i915#93] / [i915#95]) -> [DMESG-WARN][70] ([i915#62] / [i915#92]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at i915_pm_rpm@reg-read-ioctl.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl2/igt at i915_pm_rpm@reg-read-ioctl.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][71] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][75] ([fdo#110321]) -> [TIMEOUT][76] ([i915#1319] / [i915#1958]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][77] ([fdo#110321] / [i915#95]) -> [TIMEOUT][78] ([i915#1319] / [i915#1635]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][79] ([fdo#110321] / [i915#95]) -> [TIMEOUT][80] ([i915#1319]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-kbl7/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][81] ([i915#180] / [i915#95]) -> [DMESG-WARN][82] ([i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/shard-apl7/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17888 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17888: f6f5eb4457be93abbc43374cbb6e2c6cca6f2035 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17888/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 17:26:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 17:26:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Discard_a_misplaced_GGTT_vma_=28rev2=29?= In-Reply-To: <20200605165258.1483-1-chris@chris-wilson.co.uk> References: <20200605165258.1483-1-chris@chris-wilson.co.uk> Message-ID: <159137799705.18506.6266010912135368102@emeril.freedesktop.org> == Series Details == Series: drm/i915: Discard a misplaced GGTT vma (rev2) URL : https://patchwork.freedesktop.org/series/77786/ State : success == Summary == CI Bug Log - changes from CI_DRM_8592 -> Patchwork_17891 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/index.html Known issues ------------ Here are the changes found in Patchwork_17891 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/fi-kbl-x1275/igt at kms_busy@basic at flip.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1}: - fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#1982] / [i915#62] / [i915#92]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8592 -> Patchwork_17891 CI-20190529: 20190529 CI_DRM_8592: c400ab174e2f9c0a025a3b5acd60293d0a5460bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17891: ce3f32b549aff1275a68d091bd071783feda66c3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ce3f32b549af drm/i915: Discard a misplaced GGTT vma == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/index.html From hdegoede at redhat.com Fri Jun 5 17:31:35 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Fri, 5 Jun 2020 19:31:35 +0200 Subject: [Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) In-Reply-To: <20200605170931.GR2428291@smile.fi.intel.com> References: <20200602122130.45630-1-hdegoede@redhat.com> <20200602152317.GI2428291@smile.fi.intel.com> <ba931618-9259-aca0-142c-c1dfb67e737e@redhat.com> <20200605170931.GR2428291@smile.fi.intel.com> Message-ID: <1cf9b188-1e59-b321-6909-bf6afa93685d@redhat.com> Hi, On 6/5/20 7:09 PM, Andy Shevchenko wrote: > On Fri, Jun 05, 2020 at 04:33:47PM +0200, Hans de Goede wrote: >> On 6/2/20 5:23 PM, Andy Shevchenko wrote: >>> On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote: >>>> The pins on the Bay Trail SoC have separate input-buffer and output-buffer >>>> enable bits and a read of the level bit of the value register will always >>>> return the value from the input-buffer. >>>> >>>> The BIOS of a device may configure a pin in output-only mode, only enabling >>>> the output buffer, and write 1 to the level bit to drive the pin high. >>>> This 1 written to the level bit will be stored inside the data-latch of the >>>> output buffer. >>>> >>>> But a subsequent read of the value register will return 0 for the level bit >>>> because the input-buffer is disabled. This causes a read-modify-write as >>>> done by byt_gpio_set_direction() to write 0 to the level bit, driving the >>>> pin low! >>>> >>>> Before this commit byt_gpio_direction_output() relied on >>>> pinctrl_gpio_direction_output() to set the direction, followed by a call >>>> to byt_gpio_set() to apply the selected value. This causes the pin to >>>> go low between the pinctrl_gpio_direction_output() and byt_gpio_set() >>>> calls. >>>> >>>> Change byt_gpio_direction_output() to directly make the register >>>> modifications itself instead. Replacing the 2 subsequent writes to the >>>> value register with a single write. >>>> >>>> Note that the pinctrl code does not keep track internally of the direction, >>>> so not going through pinctrl_gpio_direction_output() is not an issue. >>>> >>>> This issue was noticed on a Trekstor SurfTab Twin 10.1. When the panel is >>>> already on at boot (no external monitor connected), then the i915 driver >>>> does a gpiod_get(..., GPIOD_OUT_HIGH) for the panel-enable GPIO. The >>>> temporarily going low of that GPIO was causing the panel to reset itself >>>> after which it would not show an image until it was turned off and back on >>>> again (until a full modeset was done on it). This commit fixes this. >>> >>> No Fixes tag? >> >> It is sort of hard to pin the introduction of this down to a single >> commit. If I were to guess, I guess the commit introducing the driver? > > Why not? Good guess to me (but I think rather the one which converts GPIO > driver to pin control). I will check and add a fixes tag for v2. > ... > >>>> + /* >>>> + * Before making any direction modifications, do a check if gpio is set >>> >>>> + * for direct IRQ. On baytrail, setting GPIO to output does not make >>> >>> Since we change this, perhaps >>> >>> 'IRQ. On baytrail' -> 'IRQ. On Baytrail' (one space and capital 'B'). >> >> Sure, not sure if that is worth respinning the patch for though, >> either way let me know. > > I think makes sense to respin. We still have time. I wasn't talking about timing, more just that it creates extra work (for me) and if that was just for the capital 'B' thingie it would not be worth the extra work IMHO, but since we need a v2 for the fixes tag anyways I'll fix this as well. >>>> + * sense, so let's at least inform the caller before they shoot >>>> + * themselves in the foot. >>>> + */ > > ... > >>> Wouldn't be simple below fix the issue? > >> No that will not help the pin is already high, but any reads >> of the register will return the BYT_LEVEL bit as being low, so >> the read-write-modify done when setting the direction reads BYT_LEVEL >> as 0 and writes it back as such. > > So, if I read documentation correctly, there is no means to read back current > output value if input is disabled. Alas, quite a bad design of hardware. > And on top of that likely nobody has tested that on non-Windows platform. > >> So your proposal would actually make the problem much worse (and more >> obvious) if we do the byt_gpio_set() first then for pins which have >> there input-buffer initially disabled, the value passed to >> byt_gpio_direction_output will be completely ignored and they will >> always end up as being driven low. > > What I proposed is not gonna work AFAIU documentation. > > Btw, can we for sake of consistency update direction_input() as well? Sure, the change for that will be quite small, so shall I out it in this patch, or do you want a second patch for that? Regards, Hans From patchwork at emeril.freedesktop.org Fri Jun 5 17:58:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 17:58:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Include_the_engine=27s_fw-domains_in_the_debug_info?= In-Reply-To: <20200605144705.31127-1-chris@chris-wilson.co.uk> References: <20200605144705.31127-1-chris@chris-wilson.co.uk> Message-ID: <159137993282.18506.4247758612818073836@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Include the engine's fw-domains in the debug info URL : https://patchwork.freedesktop.org/series/78048/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17889_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17889_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17889_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17889_full: ### IGT changes ### #### Possible regressions #### * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html #### Warnings #### * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [SKIP][3] ([fdo#109271]) -> [TIMEOUT][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [FAIL][5] ([i915#1930]) -> [TIMEOUT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html * {igt at kms_chamelium@vga-hpd-enable-disable-mode}: - shard-snb: [SKIP][7] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_chamelium@vga-hpd-enable-disable-mode.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-snb6/igt at kms_chamelium@vga-hpd-enable-disable-mode.html New tests --------- New tests have been introduced between CI_DRM_8590_full and Patchwork_17889_full: ### New IGT tests (14) ### * igt at gem_exec_balancer@bonded-cork: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.31] s * igt at gem_exec_balancer@bonded-imm: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 9.77] s * igt at gem_exec_balancer@busy: - Statuses : 5 pass(s) 2 skip(s) - Exec time: [0.0, 5.09] s * igt at gem_exec_balancer@full: - Statuses : 5 pass(s) 2 skip(s) - Exec time: [0.0, 10.40] s * igt at gem_exec_balancer@full-late: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.30] s * igt at gem_exec_balancer@full-late-pulse: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.39] s * igt at gem_exec_balancer@full-pulse: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.47] s * igt at gem_exec_balancer@indices: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.17] s * igt at gem_exec_balancer@individual: - Statuses : - Exec time: [None] s * igt at gem_exec_balancer@invalid-balancer: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 9.96] s * igt at gem_exec_balancer@invalid-bonds: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 0.04] s * igt at gem_exec_balancer@nop: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 46.96] s * igt at gem_exec_balancer@semaphore: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 10.16] s * igt at gem_exec_balancer@smoke: - Statuses : 6 pass(s) 2 skip(s) - Exec time: [0.0, 23.04] s Known issues ------------ Here are the changes found in Patchwork_17889_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk8/igt at gem_exec_whisper@basic-contexts-forked.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-glk5/igt at gem_exec_whisper@basic-contexts-forked.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#454]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb7/igt at i915_pm_dc@dc6-psr.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-iclb4/igt at i915_pm_dc@dc6-psr.html * igt at kms_color@pipe-b-ctm-negative: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +11 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_color@pipe-b-ctm-negative.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl7/igt at kms_color@pipe-b-ctm-negative.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [PASS][17] -> [DMESG-FAIL][18] ([i915#54] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#93] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#95]) +9 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt: - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-tglb1/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#49]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl3/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-iclb1/igt at kms_psr@psr2_cursor_blt.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: - shard-apl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][39] ([i915#1930]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][43] ([i915#1436] / [i915#716]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl3/igt at gen9_exec_parse@allowed-all.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-skl: [DMESG-WARN][49] ([i915#128]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl8/igt at kms_cursor_legacy@all-pipes-torture-move.html * {igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-glk1/igt at kms_flip@2x-flip-vs-expired-vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [FAIL][55] ([i915#49]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl6/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * {igt at kms_getfb@getfb2-handle-protection}: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +14 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_getfb@getfb2-handle-protection.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl6/igt at kms_getfb@getfb2-handle-protection.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +3 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +3 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl4/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb4/igt at kms_psr2_su@page_flip.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb8/igt at kms_psr@psr2_sprite_mmap_gtt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][69] ([i915#31]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl1/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb5/igt at perf@blocking-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-iclb1/igt at perf@blocking-parameterized.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][73] ([i915#1542]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-hsw7/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][75] ([i915#454]) -> [SKIP][76] ([i915#468]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb3/igt at i915_pm_dc@dc6-psr.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [SKIP][77] ([fdo#109271] / [fdo#111827]) -> [INCOMPLETE][78] ([CI#80] / [i915#82]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-snb6/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][79] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_content_protection@atomic-dpms.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl3/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [DMESG-FAIL][81] ([fdo#110321]) -> [TIMEOUT][82] ([i915#1319]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-kbl2/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][83] ([fdo#110321] / [i915#95]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl2/igt at kms_content_protection@lic.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][85] ([i915#180] / [i915#95]) -> [DMESG-WARN][86] ([i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-apl3/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-WARN][87] ([i915#1982]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1982]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8590 -> Patchwork_17889 CI-20190529: 20190529 CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17889: 82bcf6d36ac4669b3b4b6b9a1b5b02fb2584c8bc @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17889/index.html From andriy.shevchenko at linux.intel.com Fri Jun 5 18:45:41 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Fri, 5 Jun 2020 21:45:41 +0300 Subject: [Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH) In-Reply-To: <1cf9b188-1e59-b321-6909-bf6afa93685d@redhat.com> References: <20200602122130.45630-1-hdegoede@redhat.com> <20200602152317.GI2428291@smile.fi.intel.com> <ba931618-9259-aca0-142c-c1dfb67e737e@redhat.com> <20200605170931.GR2428291@smile.fi.intel.com> <1cf9b188-1e59-b321-6909-bf6afa93685d@redhat.com> Message-ID: <20200605184541.GU2428291@smile.fi.intel.com> On Fri, Jun 05, 2020 at 07:31:35PM +0200, Hans de Goede wrote: > On 6/5/20 7:09 PM, Andy Shevchenko wrote: > > On Fri, Jun 05, 2020 at 04:33:47PM +0200, Hans de Goede wrote: > > > On 6/2/20 5:23 PM, Andy Shevchenko wrote: > > > > On Tue, Jun 02, 2020 at 02:21:30PM +0200, Hans de Goede wrote: ... > > > Sure, not sure if that is worth respinning the patch for though, > > > either way let me know. > > > > I think makes sense to respin. We still have time. > > I wasn't talking about timing, more just that it creates extra > work (for me) and if that was just for the capital 'B' thingie it > would not be worth the extra work IMHO, but since we need a v2 for > the fixes tag anyways I'll fix this as well. I got your point, no problem, I would fix myself, if it is only the comment to address. ... > > Btw, can we for sake of consistency update direction_input() as well? > > Sure, the change for that will be quite small, so shall I out it > in this patch, or do you want a second patch for that? I think we can do in one. -- With Best Regards, Andy Shevchenko From chris at chris-wilson.co.uk Fri Jun 5 18:48:44 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 19:48:44 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Correct discard i915_vma_compare assertion Message-ID: <20200605184844.24644-1-chris@chris-wilson.co.uk> As a last minute addition, I added an assertion to make sure that the new i915_vma view would be equal to the discard. However, the positive encouragement from CI only goes to show that we rarely take this path, and it wasn't until the post-merge run did we hit the assert. Fixes: 9bdcaa5e3a2f ("drm/i915: Discard a misplaced GGTT vma") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f1acd1889d37..41553e9e57a9 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -947,7 +947,8 @@ discard_ggtt_vma(struct i915_vma *vma, const struct i915_ggtt_view *view) rb_erase(&vma->obj_node, &obj->vma.tree); vma->ggtt_view = discard; - GEM_BUG_ON(i915_vma_compare(vma, vma->vm, view)); + GEM_BUG_ON(i915_vma_compare(vma, vma->vm, &discard)); + GEM_BUG_ON(i915_vma_compare(vma, vma->vm, view) == 0); rb = NULL; p = &obj->vma.tree.rb_node; -- 2.20.1 From matthew.william.auld at gmail.com Fri Jun 5 19:05:03 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 5 Jun 2020 20:05:03 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Correct discard i915_vma_compare assertion In-Reply-To: <20200605184844.24644-1-chris@chris-wilson.co.uk> References: <20200605184844.24644-1-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHMk1PxtXcXkqZknTtw24tBP+Xv2LCMaZc1teKYAj9ehxg@mail.gmail.com> On Fri, 5 Jun 2020 at 19:49, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > As a last minute addition, I added an assertion to make sure that the > new i915_vma view would be equal to the discard. However, the positive > encouragement from CI only goes to show that we rarely take this path, > and it wasn't until the post-merge run did we hit the assert. > > Fixes: 9bdcaa5e3a2f ("drm/i915: Discard a misplaced GGTT vma") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Matthew Auld <matthew.auld at intel.com> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From nirmodas at amd.com Fri Jun 5 08:18:08 2020 From: nirmodas at amd.com (Nirmoy) Date: Fri, 5 Jun 2020 10:18:08 +0200 Subject: [Intel-gfx] [PATCH v2 1/1] drm/mm: add ig_frag selftest In-Reply-To: <d11d0f7b-6273-e1be-65db-1698e9c31228@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> <d11d0f7b-6273-e1be-65db-1698e9c31228@amd.com> Message-ID: <f4368a5f-083c-9718-ad3d-95d45e89f107@amd.com> On 6/5/20 9:45 AM, Christian K?nig wrote: > Am 03.06.20 um 12:32 schrieb Nirmoy Das: >> This patch introduces fragmentation in the address range >> and measures time taken by 10k and 20k insertions. ig_frag() >> will fail if the time taken by 20k insertions takes more than >> 4 times of 10k insertions as we know that insertions should at >> most scale quadratically. >> >> v2: >> introduce fragmentation by freeing every other node. >> only test bottom-up and top-down for now. >> >> Signed-off-by: Nirmoy Das <nirmoy.das at amd.com> >> --- >> ? drivers/gpu/drm/selftests/drm_mm_selftests.h |?? 1 + >> ? drivers/gpu/drm/selftests/test-drm_mm.c????? | 124 +++++++++++++++++++ >> ? 2 files changed, 125 insertions(+) >> >> diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h >> b/drivers/gpu/drm/selftests/drm_mm_selftests.h >> index 6b943ea1c57d..8c87c964176b 100644 >> --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h >> +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h >> @@ -14,6 +14,7 @@ selftest(insert, igt_insert) >> ? selftest(replace, igt_replace) >> ? selftest(insert_range, igt_insert_range) >> ? selftest(align, igt_align) >> +selftest(frag, igt_frag) >> ? selftest(align32, igt_align32) >> ? selftest(align64, igt_align64) >> ? selftest(evict, igt_evict) >> diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c >> b/drivers/gpu/drm/selftests/test-drm_mm.c >> index 9aabe82dcd3a..34231baacd87 100644 >> --- a/drivers/gpu/drm/selftests/test-drm_mm.c >> +++ b/drivers/gpu/drm/selftests/test-drm_mm.c >> @@ -10,6 +10,7 @@ >> ? #include <linux/slab.h> >> ? #include <linux/random.h> >> ? #include <linux/vmalloc.h> >> +#include <linux/ktime.h> >> ? ? #include <drm/drm_mm.h> >> ? @@ -1033,6 +1034,129 @@ static int igt_insert_range(void *ignored) >> ????? return 0; >> ? } >> ? +static int prepare_igt_frag(struct drm_mm *mm, >> +??????????????? struct drm_mm_node *nodes, >> +??????????????? unsigned int num_insert, >> +??????????????? const struct insert_mode *mode) >> +{ >> +??? unsigned int size = 4096; >> +??? unsigned int i; >> +??? u64 ret = -EINVAL; >> + >> +??? for (i = 0; i < num_insert; i++) { >> +??????? if (!expect_insert(mm, &nodes[i], size, 0, i, >> +?????????????????? mode) != 0) { >> +??????????? pr_err("%s insert failed\n", mode->name); >> +??????????? goto out; >> +??????? } >> +??? } >> + >> +??? /* introduce fragmentation by freeing every other node */ >> +??? for (i = 0; i < num_insert; i++) { >> +??????? if (i % 2 == 0) >> +??????????? drm_mm_remove_node(&nodes[i]); >> +??? } >> + >> +out: >> +??? return ret; >> + >> +} >> + >> +static u64 get_insert_time(struct drm_mm *mm, >> +?????????????? unsigned int num_insert, >> +?????????????? struct drm_mm_node *nodes, >> +?????????????? const struct insert_mode *mode) >> +{ >> +??? unsigned int size = 8192; >> +??? ktime_t start; >> +??? unsigned int i; >> +??? u64 ret = -EINVAL; >> + >> +??? start = ktime_get(); >> +??? for (i = 0; i < num_insert; i++) { >> +??????? if (!expect_insert(mm, &nodes[i], size, 0, i, mode) != 0) { >> +??????????? pr_err("%s insert failed\n", mode->name); >> +??????????? goto out; >> +??????? } >> +??? } >> + >> +??? ret = ktime_to_ns(ktime_sub(ktime_get(), start)); >> + >> +out: >> +??? return ret; >> + >> +} >> + >> +static int igt_frag(void *ignored) >> +{ >> +??? struct drm_mm mm; >> +??? const struct insert_mode *mode; >> +??? struct drm_mm_node *nodes, *node, *next; >> +??? unsigned int insert_size = 10000; >> +??? unsigned int scale_factor = 4; >> +??? int ret = -EINVAL; >> + >> +??? /* We need 4 * insert_size nodes to hold intermediate allocated >> +???? * drm_mm nodes. >> +???? * 1 times for prepare_igt_frag() >> +???? * 1 times for get_insert_time() >> +???? * 2 times for? get_insert_time() >> +???? */ >> +??? nodes = vzalloc(array_size(insert_size * 4, sizeof(*nodes))); >> +??? if (!nodes) >> +??????? return -ENOMEM; >> + >> +??? /* For BOTTOMUP and TOPDOWN, we first fragment the >> +???? * address space using prepare_igt_frag() and then try to verify >> +???? * that that insertions scale quadratically from 10k to 20k >> insertions >> +???? */ >> +??? drm_mm_init(&mm, 1, U64_MAX - 2); >> +??? for (mode = insert_modes; mode->name; mode++) { >> +??????? u64 insert_time1, insert_time2; >> + >> +??????? if (mode->mode != DRM_MM_INSERT_LOW || >> +??????????? mode->mode != DRM_MM_INSERT_HIGH) >> +??????????? continue; > > This check here is wrong, that needs to be && instead of || or the > test wouldn't execute at all. I didn't bother to check dmesg after adding that "simple" check and the test ran fine. :/ Sending again. Nirmoy > > Christian. > >> + >> +??????? ret = prepare_igt_frag(&mm, nodes, insert_size, mode); >> +??????? if (!ret) >> +??????????? goto err; >> + >> +??????? insert_time1 = get_insert_time(&mm, insert_size, >> +?????????????????????????? nodes + insert_size, mode); >> +??????? if (insert_time1 < 0) >> +??????????? goto err; >> + >> +??????? insert_time2 = get_insert_time(&mm, (insert_size * 2), >> +?????????????????????????? nodes + insert_size * 2, mode); >> +??????? if (insert_time2 < 0) >> +??????????? goto err; >> + >> +??????? pr_info("%s fragmented insert of %u and %u insertions took >> %llu and %llu nsecs\n", >> +??????????? mode->name, insert_size, insert_size * 2, >> +??????????? insert_time1, insert_time2); >> + >> +??????? if (insert_time2 > (scale_factor * insert_time1)) { >> +??????????? pr_err("%s fragmented insert took %llu nsecs more\n", >> +?????????????????? mode->name, >> +?????????????????? insert_time2 - (scale_factor * insert_time1)); >> +??????????? goto err; >> +??????? } >> + >> +??????? drm_mm_for_each_node_safe(node, next, &mm) >> +??????????? drm_mm_remove_node(node); >> +??? } >> + >> +??? ret = 0; >> +err: >> +??? drm_mm_for_each_node_safe(node, next, &mm) >> +??????? drm_mm_remove_node(node); >> +??? drm_mm_takedown(&mm); >> +??? vfree(nodes); >> + >> +??? return ret; >> +} >> + >> ? static int igt_align(void *ignored) >> ? { >> ????? const struct insert_mode *mode; > From nirmoy.aiemd at gmail.com Fri Jun 5 09:14:02 2020 From: nirmoy.aiemd at gmail.com (Nirmoy Das) Date: Fri, 5 Jun 2020 11:14:02 +0200 Subject: [Intel-gfx] [PATCH v3 1/1] drm/mm: add ig_frag selftest In-Reply-To: <d11d0f7b-6273-e1be-65db-1698e9c31228@amd.com> References: <d11d0f7b-6273-e1be-65db-1698e9c31228@amd.com> Message-ID: <20200605091402.4408-1-nirmoy.das@amd.com> This patch introduces fragmentation in the address range and measures time taken by 10k and 20k insertions. ig_frag() will fail if the time taken by 20k insertions takes more than 4 times of 10k insertions as we know that insertions should at most scale quadratically. v2: introduce fragmentation by freeing every other node. only test bottom-up and top-down for now. v3: fix incorrect mode check Signed-off-by: Nirmoy Das <nirmoy.das at amd.com> --- drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 124 +++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/drivers/gpu/drm/selftests/drm_mm_selftests.h b/drivers/gpu/drm/selftests/drm_mm_selftests.h index 6b943ea1c57d..8c87c964176b 100644 --- a/drivers/gpu/drm/selftests/drm_mm_selftests.h +++ b/drivers/gpu/drm/selftests/drm_mm_selftests.h @@ -14,6 +14,7 @@ selftest(insert, igt_insert) selftest(replace, igt_replace) selftest(insert_range, igt_insert_range) selftest(align, igt_align) +selftest(frag, igt_frag) selftest(align32, igt_align32) selftest(align64, igt_align64) selftest(evict, igt_evict) diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c b/drivers/gpu/drm/selftests/test-drm_mm.c index 9aabe82dcd3a..ca5f35def905 100644 --- a/drivers/gpu/drm/selftests/test-drm_mm.c +++ b/drivers/gpu/drm/selftests/test-drm_mm.c @@ -10,6 +10,7 @@ #include <linux/slab.h> #include <linux/random.h> #include <linux/vmalloc.h> +#include <linux/ktime.h> #include <drm/drm_mm.h> @@ -1033,6 +1034,129 @@ static int igt_insert_range(void *ignored) return 0; } +static int prepare_igt_frag(struct drm_mm *mm, + struct drm_mm_node *nodes, + unsigned int num_insert, + const struct insert_mode *mode) +{ + unsigned int size = 4096; + unsigned int i; + u64 ret = -EINVAL; + + for (i = 0; i < num_insert; i++) { + if (!expect_insert(mm, &nodes[i], size, 0, i, + mode) != 0) { + pr_err("%s insert failed\n", mode->name); + goto out; + } + } + + /* introduce fragmentation by freeing every other node */ + for (i = 0; i < num_insert; i++) { + if (i % 2 == 0) + drm_mm_remove_node(&nodes[i]); + } + +out: + return ret; + +} + +static u64 get_insert_time(struct drm_mm *mm, + unsigned int num_insert, + struct drm_mm_node *nodes, + const struct insert_mode *mode) +{ + unsigned int size = 8192; + ktime_t start; + unsigned int i; + u64 ret = -EINVAL; + + start = ktime_get(); + for (i = 0; i < num_insert; i++) { + if (!expect_insert(mm, &nodes[i], size, 0, i, mode) != 0) { + pr_err("%s insert failed\n", mode->name); + goto out; + } + } + + ret = ktime_to_ns(ktime_sub(ktime_get(), start)); + +out: + return ret; + +} + +static int igt_frag(void *ignored) +{ + struct drm_mm mm; + const struct insert_mode *mode; + struct drm_mm_node *nodes, *node, *next; + unsigned int insert_size = 10000; + unsigned int scale_factor = 4; + int ret = -EINVAL; + + /* We need 4 * insert_size nodes to hold intermediate allocated + * drm_mm nodes. + * 1 times for prepare_igt_frag() + * 1 times for get_insert_time() + * 2 times for get_insert_time() + */ + nodes = vzalloc(array_size(insert_size * 4, sizeof(*nodes))); + if (!nodes) + return -ENOMEM; + + /* For BOTTOMUP and TOPDOWN, we first fragment the + * address space using prepare_igt_frag() and then try to verify + * that that insertions scale quadratically from 10k to 20k insertions + */ + drm_mm_init(&mm, 1, U64_MAX - 2); + for (mode = insert_modes; mode->name; mode++) { + u64 insert_time1, insert_time2; + + if (mode->mode != DRM_MM_INSERT_LOW && + mode->mode != DRM_MM_INSERT_HIGH) + continue; + + ret = prepare_igt_frag(&mm, nodes, insert_size, mode); + if (!ret) + goto err; + + insert_time1 = get_insert_time(&mm, insert_size, + nodes + insert_size, mode); + if (insert_time1 < 0) + goto err; + + insert_time2 = get_insert_time(&mm, (insert_size * 2), + nodes + insert_size * 2, mode); + if (insert_time2 < 0) + goto err; + + pr_info("%s fragmented insert of %u and %u insertions took %llu and %llu nsecs\n", + mode->name, insert_size, insert_size * 2, + insert_time1, insert_time2); + + if (insert_time2 > (scale_factor * insert_time1)) { + pr_err("%s fragmented insert took %llu nsecs more\n", + mode->name, + insert_time2 - (scale_factor * insert_time1)); + goto err; + } + + drm_mm_for_each_node_safe(node, next, &mm) + drm_mm_remove_node(node); + } + + ret = 0; +err: + drm_mm_for_each_node_safe(node, next, &mm) + drm_mm_remove_node(node); + drm_mm_takedown(&mm); + vfree(nodes); + + return ret; +} + static int igt_align(void *ignored) { const struct insert_mode *mode; -- 2.26.2 From patchwork at emeril.freedesktop.org Fri Jun 5 19:21:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 19:21:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Correct_discard_i915=5Fvma=5Fcompare_assertion?= In-Reply-To: <20200605184844.24644-1-chris@chris-wilson.co.uk> References: <20200605184844.24644-1-chris@chris-wilson.co.uk> Message-ID: <159138488461.18508.3296549350844878225@emeril.freedesktop.org> == Series Details == Series: drm/i915: Correct discard i915_vma_compare assertion URL : https://patchwork.freedesktop.org/series/78053/ State : success == Summary == CI Bug Log - changes from CI_DRM_8593 -> Patchwork_17892 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/index.html Known issues ------------ Here are the changes found in Patchwork_17892 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-byt-j1900/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-byt-j1900/igt at i915_module_load@reload.html - fi-bxt-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-bxt-dsi/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-bxt-dsi/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [PASS][7] -> [DMESG-FAIL][8] ([i915#1993]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-icl-y/igt at i915_selftest@live at execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-icl-y/igt at i915_selftest@live at execlists.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-byt-n2820/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-kbl-x1275/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][17] ([fdo#109271]) -> [DMESG-FAIL][18] ([i915#62] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-tgl-y Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8593 -> Patchwork_17892 CI-20190529: 20190529 CI_DRM_8593: 11c8af407947d7e9f56a99419f3867972d6c138d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17892: 954be4018799277620ca00c171ccbb02d1a14691 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 954be4018799 drm/i915: Correct discard i915_vma_compare assertion == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 19:25:59 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 19:25:59 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv3=2C1/1=5D_drm/mm=3A_add_ig=5Ffrag?= =?utf-8?q?_selftest_=28rev2=29?= In-Reply-To: <20200603103223.10443-1-nirmoy.das@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> Message-ID: <159138515967.18508.12936367917148900811@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/1] drm/mm: add ig_frag selftest (rev2) URL : https://patchwork.freedesktop.org/series/77964/ State : warning == Summary == $ dim checkpatch origin/drm-tip 375207a3bd0b drm/mm: add ig_frag selftest -:75: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #75: FILE: drivers/gpu/drm/selftests/test-drm_mm.c:1063: + +} -:100: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #100: FILE: drivers/gpu/drm/selftests/test-drm_mm.c:1088: + +} -:174: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Nirmoy Das <nirmoy.aiemd at gmail.com>' total: 0 errors, 1 warnings, 2 checks, 143 lines checked From chris at chris-wilson.co.uk Fri Jun 5 19:27:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 05 Jun 2020 20:27:35 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Correct discard i915_vma_compare assertion In-Reply-To: <CAM0jSHMk1PxtXcXkqZknTtw24tBP+Xv2LCMaZc1teKYAj9ehxg@mail.gmail.com> References: <20200605184844.24644-1-chris@chris-wilson.co.uk> <CAM0jSHMk1PxtXcXkqZknTtw24tBP+Xv2LCMaZc1teKYAj9ehxg@mail.gmail.com> Message-ID: <159138525558.22562.15325070153859665526@build.alporthouse.com> Quoting Matthew Auld (2020-06-05 20:05:03) > On Fri, 5 Jun 2020 at 19:49, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > As a last minute addition, I added an assertion to make sure that the > > new i915_vma view would be equal to the discard. However, the positive > > encouragement from CI only goes to show that we rarely take this path, > > and it wasn't until the post-merge run did we hit the assert. > > > > Fixes: 9bdcaa5e3a2f ("drm/i915: Discard a misplaced GGTT vma") > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Matthew Auld <matthew.auld at intel.com> > Reviewed-by: Matthew Auld <matthew.auld at intel.com> Ta, and apologies for the silly typo. -Chris From patchwork at emeril.freedesktop.org Fri Jun 5 19:47:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 19:47:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv3=2C1/1=5D_drm/mm=3A_add_ig=5Ffrag_selfte?= =?utf-8?b?c3QgKHJldjIp?= In-Reply-To: <20200603103223.10443-1-nirmoy.das@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> Message-ID: <159138643100.18509.4588477522006599062@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/1] drm/mm: add ig_frag selftest (rev2) URL : https://patchwork.freedesktop.org/series/77964/ State : success == Summary == CI Bug Log - changes from CI_DRM_8593 -> Patchwork_17893 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/index.html Known issues ------------ Here are the changes found in Patchwork_17893 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-byt-n2820/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-tgl-dsi}: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#62] / [i915#92]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-tgl-y Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8593 -> Patchwork_17893 CI-20190529: 20190529 CI_DRM_8593: 11c8af407947d7e9f56a99419f3867972d6c138d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17893: 375207a3bd0bdff00c10ad2a0722ac5fe9f1bca4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 375207a3bd0b drm/mm: add ig_frag selftest == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/index.html From lkp at intel.com Fri Jun 5 19:54:37 2020 From: lkp at intel.com (kernel test robot) Date: Sat, 6 Jun 2020 03:54:37 +0800 Subject: [Intel-gfx] [drm-intel:drm-intel-next-queued 1/7] drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused function 'unmask_page' Message-ID: <202006060326.1Vu6JFUY%lkp@intel.com> tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued head: 84d24cb5247a356a4310a25761f8aa56b8814538 commit: 9e0f9464e2ab36b864359a59b0e9058fdef0ce47 [1/7] drm/i915/gem: Async GPU relocations only config: x86_64-randconfig-a011-20200605 (attached as .config) compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 6dd738e2f0609f7d3313b574a1d471263d2d3ba1) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu git checkout 9e0f9464e2ab36b864359a59b0e9058fdef0ce47 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused function 'unmask_page' [-Werror,-Wunused-function] static inline void *unmask_page(unsigned long p) ^ >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:938:28: error: unused function 'unmask_flags' [-Werror,-Wunused-function] static inline unsigned int unmask_flags(unsigned long p) ^ >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:945:33: error: unused function 'cache_to_ggtt' [-Werror,-Wunused-function] static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) ^ 3 errors generated. vim +/unmask_page +933 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 5032d871f7d300 drivers/gpu/drm/i915/i915_gem_execbuffer.c Rafael Barbalho 2013-08-21 932 d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 @933 static inline void *unmask_page(unsigned long p) d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 934 { d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 935 return (void *)(uintptr_t)(p & PAGE_MASK); d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 936 } d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 937 d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 @938 static inline unsigned int unmask_flags(unsigned long p) d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 939 { d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 940 return p & ~PAGE_MASK; d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 941 } d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 942 d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 943 #define KMAP 0x4 /* after CLFLUSH_FLAGS */ d50415cc6c8395 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2016-08-18 944 650bc63568e421 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2017-06-15 @945 static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) 650bc63568e421 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2017-06-15 946 { 650bc63568e421 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2017-06-15 947 struct drm_i915_private *i915 = 650bc63568e421 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2017-06-15 948 container_of(cache, struct i915_execbuffer, reloc_cache)->i915; 650bc63568e421 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2017-06-15 949 return &i915->ggtt; 650bc63568e421 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2017-06-15 950 } 650bc63568e421 drivers/gpu/drm/i915/i915_gem_execbuffer.c Chris Wilson 2017-06-15 951 :::::: The code at line 933 was first introduced by commit :::::: d50415cc6c8395602052b39a1a39290fba3d313e drm/i915: Refactor execbuffer relocation writing :::::: TO: Chris Wilson <chris at chris-wilson.co.uk> :::::: CC: Chris Wilson <chris at chris-wilson.co.uk> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 34036 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200606/5f573525/attachment-0001.gz> From daniel at ffwll.ch Fri Jun 5 19:55:53 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 5 Jun 2020 21:55:53 +0200 Subject: [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny In-Reply-To: <CY4PR1201MB013642EB94E07AED91813A5FDE890@CY4PR1201MB0136.namprd12.prod.outlook.com> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-54-daniel.vetter@ffwll.ch> <20200415094512.GA30444@ravnborg.org> <MWHPR12MB14532DA5713E3B579ABFE1F4A1DB0@MWHPR12MB1453.namprd12.prod.outlook.com> <CAKMK7uGDGgt8Cm_bFoyzeoP2CWyiUNdUwb7GL6Ohu3k0rP0p1w@mail.gmail.com> <20200428140842.GL3456981@phenom.ffwll.local> <CH2PR12MB3894B40C6D71435D3E759A34A1A20@CH2PR12MB3894.namprd12.prod.outlook.com> <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com> <20200604080507.GT20149@phenom.ffwll.local> <CY4PR1201MB01363EB95985A2C64ADA6841DE890@CY4PR1201MB0136.namprd12.prod.outlook.com> <CAKMK7uFLvV3=uhfnf=MreKBM==-gzXqx3NrV8KDA2D5sTAn2SQ@mail.gmail.com> <CY4PR1201MB013642EB94E07AED91813A5FDE890@CY4PR1201MB0136.namprd12.prod.outlook.com> Message-ID: <CAKMK7uESUnLR1N07T513RjGUAp8FA6oHaO1Y+uvTKpFuM_8+gQ@mail.gmail.com> Hi Eugeniy, Thanks for testing. I looked at the second one (I hoped it would just magically disappear) and I still don't understand what's going on there. My patch series isn't touching that area at all, so really confused. I squashed in the bugfix from the previous round into the right patches, and pushed a branch with just the arcpgu changes here: https://cgit.freedesktop.org/~danvet/drm/log/?h=for-eugeniy Maybe it's something in my pile of not-so-tested stuff :-) Can you pls test this? And if it still fails, try to bisect where it breaks? Thanks, Daniel On Thu, Jun 4, 2020 at 9:00 PM Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> wrote: > > I've tested your change and one issue gone. > > However I still see kernel crash (due to invalid read in kernel mode by 0x0 address) on weston stop: > ----------------------------------->8------------------------------------------- > Oops > Path: (null) > CPU: 0 PID: 12 Comm: kworker/0:1 Not tainted 5.7.0-rc6-01594-g4ceda91a4176-dirty #6 > Workqueue: events drm_mode_rmfb_work_fn > Invalid Read @ 0x00000000 by insn @ drm_gem_fb_destroy+0x32/0x130 > ECR: 0x00050100 EFA: 0x00000000 ERET: 0x813b9a76 > STAT32: 0x80080602 [IE K ] BTA: 0x813b9a72 > BLK: drm_gem_fb_destroy+0xc0/0x130 > SP: 0x9f055ea4 FP: 0x00000000 > LPS: 0x813560ec LPE: 0x813560f0 LPC: 0x00000000 > r00: 0x00000000 r01: 0x9f6a6100 r02: 0x00000001 > r03: 0x9fd5dde8 r04: 0x810f5de8 r05: 0x00000000 > r06: 0x00000000 r07: 0x00000000 r08: 0x000000e1 > r09: 0x00000000 r10: 0x00000000 r11: 0x000000e1 > r12: 0x813b9b04 > > Stack Trace: > drm_gem_fb_destroy+0x32/0x130 > drm_framebuffer_remove+0x1d2/0x358 > drm_mode_rmfb_work_fn+0x28/0x38 > process_one_work+0x19a/0x358 > worker_thread+0x2c4/0x494 > kthread+0xec/0x100 > ret_from_fork+0x18/0x1c > ----------------------------------->8------------------------------------------- > > > The stack traces may vary but always end in drm_gem_fb_destroy: > ----------------------------------->8------------------------------------------- > Stack Trace: > drm_gem_fb_destroy+0x32/0x130 > drm_mode_rmfb+0x10e/0x148 > drm_ioctl_kernel+0x70/0xa0 > drm_ioctl+0x284/0x410 > ksys_ioctl+0xea/0xa3c > EV_Trap+0xcc/0xd0 > ----------------------------------->8------------------------------------------- > Stack Trace: > drm_gem_fb_destroy+0x32/0x130 > drm_fb_release+0x66/0xb0 > drm_file_free.part.11+0x112/0x1bc > drm_release+0x80/0x120 > __fput+0x98/0x1bc > task_work_run+0x6e/0xa8 > do_exit+0x2b4/0x7fc > do_group_exit+0x2a/0x8c > get_signal+0x9a/0x5f0 > do_signal+0x86/0x23c > resume_user_mode_begin+0x88/0xd0 > ----------------------------------->8------------------------------------------- > > > --- > Eugeniy Paltsev > > > ________________________________________ > From: Daniel Vetter <daniel at ffwll.ch> > Sent: Thursday, June 4, 2020 14:19 > To: Eugeniy Paltsev > Cc: Intel Graphics Development; DRI Development; Daniel Vetter; Sam Ravnborg; Alexey Brodkin > Subject: Re: [PATCH 53/59] drm/arc: Move to drm/tiny > > Hi Eugeniy, > > Apologies, somehow I missed your mail. I looked at the code again, and I > think I fumbled something. Does the below diff help to prevent the issues? > > Thanks, Daniel > > > diff --git a/drivers/gpu/drm/tiny/arcpgu.c b/drivers/gpu/drm/tiny/arcpgu.c > index 857812f25bec..33d812a5ad7f 100644 > --- a/drivers/gpu/drm/tiny/arcpgu.c > +++ b/drivers/gpu/drm/tiny/arcpgu.c > @@ -228,6 +228,9 @@ static void arc_pgu_update(struct drm_simple_display_pipe *pipe, > struct arcpgu_drm_private *arcpgu; > struct drm_gem_cma_object *gem; > > + if (!pipe->plane.state->fb) > + return; > + > arcpgu = pipe_to_arcpgu_priv(pipe); > gem = drm_fb_cma_get_gem_obj(pipe->plane.state->fb, 0); > arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr); > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - https://urldefense.com/v3/__http://blog.ffwll.ch__;!!A4F2R9G_pg!P0EvyJfMuDwqbeZmHZM5S9po30QWr4KgGrggRirNfgo7wrRXfnUO-8iq0AA4fQCW2WGPlDc$ -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch From chris at chris-wilson.co.uk Fri Jun 5 20:03:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 5 Jun 2020 21:03:57 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gem: Delete unused code Message-ID: <20200605200357.13069-1-chris@chris-wilson.co.uk> Unused as of commit 9e0f9464e2ab ("drm/i915/gem: Async GPU relocations only"), but left behind. >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused function 'unmask_page' [-Werror,-Wunused-function] static inline void *unmask_page(unsigned long p) ^ >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:938:28: error: unused function 'unmask_flags' [-Werror,-Wunused-function] static inline unsigned int unmask_flags(unsigned long p) ^ >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:945:33: error: unused function 'cache_to_ggtt' [-Werror,-Wunused-function] static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) Reported-by: kernel test robot <lkp at intel.com> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index cfe6d2cdbef1..23db79b806db 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -930,25 +930,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->target = NULL; } -static inline void *unmask_page(unsigned long p) -{ - return (void *)(uintptr_t)(p & PAGE_MASK); -} - -static inline unsigned int unmask_flags(unsigned long p) -{ - return p & ~PAGE_MASK; -} - -#define KMAP 0x4 /* after CLFLUSH_FLAGS */ - -static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) -{ - struct drm_i915_private *i915 = - container_of(cache, struct i915_execbuffer, reloc_cache)->i915; - return &i915->ggtt; -} - #define RELOC_TAIL 4 static int reloc_gpu_chain(struct reloc_cache *cache) -- 2.20.1 From matthew.william.auld at gmail.com Fri Jun 5 20:22:24 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 5 Jun 2020 21:22:24 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gem: Delete unused code In-Reply-To: <20200605200357.13069-1-chris@chris-wilson.co.uk> References: <20200605200357.13069-1-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHNmuOx0696sdHefZCG7K5kFM-Wn4QxvUXt+9wmMcDv-PQ@mail.gmail.com> On Fri, 5 Jun 2020 at 21:04, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Unused as of commit 9e0f9464e2ab ("drm/i915/gem: Async GPU relocations > only"), but left behind. > > >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused function 'unmask_page' [-Werror,-Wunused-function] > static inline void *unmask_page(unsigned long p) > ^ > >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:938:28: error: unused function 'unmask_flags' [-Werror,-Wunused-function] > static inline unsigned int unmask_flags(unsigned long p) > ^ > >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:945:33: error: unused function 'cache_to_ggtt' [-Werror,-Wunused-function] > static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) > > Reported-by: kernel test robot <lkp at intel.com> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From patchwork at emeril.freedesktop.org Fri Jun 5 20:39:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 20:39:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915=3A_Discard_a_misplaced_GGTT_vma_=28rev2=29?= In-Reply-To: <20200605165258.1483-1-chris@chris-wilson.co.uk> References: <20200605165258.1483-1-chris@chris-wilson.co.uk> Message-ID: <159138955144.18509.15690659915029474507@emeril.freedesktop.org> == Series Details == Series: drm/i915: Discard a misplaced GGTT vma (rev2) URL : https://patchwork.freedesktop.org/series/77786/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8592_full -> Patchwork_17891_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17891_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17891_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17891_full: ### IGT changes ### #### Possible regressions #### * igt at gem_mmap_gtt@fault-concurrent: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-tglb7/igt at gem_mmap_gtt@fault-concurrent.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-tglb2/igt at gem_mmap_gtt@fault-concurrent.html Known issues ------------ Here are the changes found in Patchwork_17891_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_shared@detached-shared-gtt: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl6/igt at gem_ctx_shared@detached-shared-gtt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl4/igt at gem_ctx_shared@detached-shared-gtt.html * igt at gem_exec_whisper@basic-normal: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-glk1/igt at gem_exec_whisper@basic-normal.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-glk1/igt at gem_exec_whisper@basic-normal.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl6/igt at gen9_exec_parse@allowed-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl7/igt at gen9_exec_parse@allowed-all.html * igt at i915_module_load@reload: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +10 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-skl9/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-skl4/igt at i915_module_load@reload.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][11] -> [INCOMPLETE][12] ([i915#155]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl6/igt at i915_suspend@debugfs-reader.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl4/igt at i915_suspend@debugfs-reader.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl6/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl6/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_crc@pipe-c-cursor-128x128-random: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-128x128-random.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-skl6/igt at kms_cursor_crc@pipe-c-cursor-128x128-random.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#95]) +14 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl8/igt at kms_flip_tiling@flip-x-tiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-tglb5/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-skl1/igt at kms_hdr@bpc-switch.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-skl7/igt at kms_hdr@bpc-switch.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-iclb1/igt at kms_psr@psr2_primary_mmap_gtt.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][27] ([i915#1930]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30] +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-glk2/igt at gem_exec_whisper@basic-queues-forked-all.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gem_tiled_pread_basic: - shard-apl: [DMESG-WARN][31] ([i915#95]) -> [PASS][32] +19 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl7/igt at gem_tiled_pread_basic.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl8/igt at gem_tiled_pread_basic.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][33] ([i915#93] / [i915#95]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl1/igt at kms_color@pipe-c-ctm-red-to-blue.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl1/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +9 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-skl7/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-skl5/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-tglb: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-tglb7/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-tglb2/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [TIMEOUT][39] -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-snb5/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled: - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl2/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl3/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html * igt at kms_fbcon_fbt@psr-suspend: - shard-skl: [INCOMPLETE][43] ([i915#69]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-skl9/igt at kms_fbcon_fbt@psr-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-skl10/igt at kms_fbcon_fbt@psr-suspend.html * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: - shard-glk: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-glk9/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-glk5/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +9 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl7/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [FAIL][49] ([i915#49]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-skl6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +4 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-iclb8/igt at kms_psr@psr2_primary_mmap_cpu.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][59] ([i915#31]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl3/igt at kms_setmode@basic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl6/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][61] ([i915#1542]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-iclb8/igt at perf@blocking-parameterized.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-iclb2/igt at perf@blocking-parameterized.html * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: - shard-tglb: [DMESG-WARN][63] ([i915#402]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-tglb2/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-iclb8/igt at i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][67] ([i915#468]) -> [FAIL][68] ([i915#454]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-tglb7/igt at i915_pm_dc@dc6-psr.html * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [INCOMPLETE][69] ([CI#80] / [i915#82]) -> [SKIP][70] ([fdo#109271] / [fdo#111827]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-snb6/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-snb5/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][71] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl1/igt at kms_content_protection@atomic-dpms.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl4/igt at kms_content_protection@atomic-dpms.html - shard-kbl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-kbl7/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-kbl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][75] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][76] ([fdo#110321] / [i915#95]) +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl7/igt at kms_content_protection@lic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl2/igt at kms_content_protection@lic.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][77] ([i915#180] / [i915#95]) -> [DMESG-WARN][78] ([i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-apl1/igt at kms_frontbuffer_tracking@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [TIMEOUT][79] -> [SKIP][80] ([fdo#109271]) +2 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8592/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/shard-snb5/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1895]: https://gitlab.freedesktop.org/drm/intel/issues/1895 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8592 -> Patchwork_17891 CI-20190529: 20190529 CI_DRM_8592: c400ab174e2f9c0a025a3b5acd60293d0a5460bd @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17891: ce3f32b549aff1275a68d091bd071783feda66c3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17891/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 20:39:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 20:39:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gem=3A_Delete_unused_code?= In-Reply-To: <20200605200357.13069-1-chris@chris-wilson.co.uk> References: <20200605200357.13069-1-chris@chris-wilson.co.uk> Message-ID: <159138957200.18508.2921781062807088474@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Delete unused code URL : https://patchwork.freedesktop.org/series/78055/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7b2f658eb02d drm/i915/gem: Delete unused code -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: >> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:933:21: error: unused function 'unmask_page' [-Werror,-Wunused-function] total: 0 errors, 1 warnings, 0 checks, 25 lines checked From patchwork at emeril.freedesktop.org Fri Jun 5 21:01:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 21:01:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Delete_unused_code?= In-Reply-To: <20200605200357.13069-1-chris@chris-wilson.co.uk> References: <20200605200357.13069-1-chris@chris-wilson.co.uk> Message-ID: <159139088143.18506.8665360291369606444@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Delete unused code URL : https://patchwork.freedesktop.org/series/78055/ State : success == Summary == CI Bug Log - changes from CI_DRM_8594 -> Patchwork_17894 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/index.html Known issues ------------ Here are the changes found in Patchwork_17894 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-kbl-x1275/igt at kms_busy@basic at flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-n3050: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-tgl-dsi/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-tgl-dsi/igt at kms_busy@basic at flip.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#1982] / [i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8594 -> Patchwork_17894 CI-20190529: 20190529 CI_DRM_8594: 6d6b387f9c60b269a434f75fe9b859a7aa6feb88 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17894: 7b2f658eb02da85bb09391b95d3b556fc9e7d997 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7b2f658eb02d drm/i915/gem: Delete unused code == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/index.html From patchwork at emeril.freedesktop.org Fri Jun 5 22:01:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 22:01:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Correct_discard_i915=5Fvma=5Fcompare_assertion?= In-Reply-To: <20200605184844.24644-1-chris@chris-wilson.co.uk> References: <20200605184844.24644-1-chris@chris-wilson.co.uk> Message-ID: <159139447204.18509.15977358433754147089@emeril.freedesktop.org> == Series Details == Series: drm/i915: Correct discard i915_vma_compare assertion URL : https://patchwork.freedesktop.org/series/78053/ State : success == Summary == CI Bug Log - changes from CI_DRM_8593_full -> Patchwork_17892_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17892_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#69]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl10/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl3/igt at gem_exec_suspend@basic-s3.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk4/igt at gem_exec_whisper@basic-contexts-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-glk1/igt at gem_exec_whisper@basic-contexts-forked.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl10/igt at gen9_exec_parse@allowed-single.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl6/igt at gen9_exec_parse@allowed-single.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-tglb7/igt at i915_module_load@reload-with-fault-injection.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_big_fb@linear-8bpp-rotate-180: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl1/igt at kms_big_fb@linear-8bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl10/igt at kms_big_fb@linear-8bpp-rotate-180.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk5/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-glk7/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-b-cursor-256x85-offscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl6/igt at kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-256x85-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +20 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl6/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl2/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [PASS][23] -> [DMESG-WARN][24] ([i915#128]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-hsw5/igt at kms_cursor_legacy@pipe-c-torture-move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-iclb1/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl6/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-kbl6/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at vcs0}: - shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * igt at gem_exec_whisper@basic-fds-forked-all: - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk6/igt at gem_exec_whisper@basic-fds-forked-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-glk5/igt at gem_exec_whisper@basic-fds-forked-all.html * igt at gem_tiled_pread_basic: - shard-apl: [DMESG-WARN][39] ([i915#95]) -> [PASS][40] +18 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl4/igt at gem_tiled_pread_basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl3/igt at gem_tiled_pread_basic.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-glk4/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-a-ctm-0-75: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl8/igt at kms_color@pipe-a-ctm-0-75.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl4/igt at kms_color@pipe-a-ctm-0-75.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl7/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl8/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_legacy@cursor-vs-flip-atomic: - shard-hsw: [FAIL][49] ([i915#57]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-atomic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-hsw1/igt at kms_cursor_legacy@cursor-vs-flip-atomic.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-apl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl7/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl3/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [TIMEOUT][53] -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb4/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-snb5/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1}: - shard-skl: [FAIL][55] ([i915#1928]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl9/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [FAIL][57] ([i915#49]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-iclb8/igt at kms_psr@psr2_sprite_blt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [INCOMPLETE][63] ([i915#82]) -> [SKIP][64] ([fdo#109271]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html - shard-iclb: [SKIP][65] ([i915#588]) -> [SKIP][66] ([i915#658]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][67] ([i915#468]) -> [FAIL][68] ([i915#454]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-tglb5/igt at i915_pm_dc@dc6-psr.html * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [INCOMPLETE][69] ([CI#80] / [i915#82]) -> [SKIP][70] ([fdo#109271] / [fdo#111827]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb4/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-snb5/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][71] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][72] ([fdo#110321]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl8/igt at kms_content_protection@atomic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [FAIL][74] ([fdo#110321] / [fdo#110336]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl8/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl3/igt at kms_content_protection@lic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl6/igt at kms_content_protection@lic.html - shard-kbl: [DMESG-FAIL][77] ([fdo#110321] / [i915#95]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl2/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-kbl7/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1958]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl7/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-kbl4/igt at kms_content_protection@srm.html - shard-apl: [TIMEOUT][81] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][82] ([fdo#110321] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl3/igt at kms_content_protection@srm.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [TIMEOUT][83] -> [SKIP][84] ([fdo#109271]) +2 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb4/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/shard-snb5/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (10 -> 11) ------------------------------ Additional (1): pig-icl-1065g7 Build changes ------------- * Linux: CI_DRM_8593 -> Patchwork_17892 CI-20190529: 20190529 CI_DRM_8593: 11c8af407947d7e9f56a99419f3867972d6c138d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17892: 954be4018799277620ca00c171ccbb02d1a14691 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17892/index.html From chris at chris-wilson.co.uk Fri Jun 5 22:11:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 05 Jun 2020 23:11:23 +0100 Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches In-Reply-To: <20200604163916.GA3023929@mdroper-desk1.amr.corp.intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <159125964432.14555.14975271091238919132@emeril.freedesktop.org> <20200604163916.GA3023929@mdroper-desk1.amr.corp.intel.com> Message-ID: <159139508324.22562.3240839281624363557@build.alporthouse.com> Quoting Matt Roper (2020-06-04 17:39:16) > On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote: > > == Series Details == > > > > Series: Remaining RKL patches > > URL : https://patchwork.freedesktop.org/series/77971/ > > State : success > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full > > ==================================================== > > > > Summary > > ------- > > > > **SUCCESS** > > > > No regressions found. > > Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's. This seems to have introduced https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-skl-guc/igt at runner@aborted.html <4>[ 3.422515] i915 0000:00:02.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev)) <4>[ 3.422528] WARNING: CPU: 4 PID: 372 at drivers/gpu/drm/drm_vblank.c:719 drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370 <4>[ 3.422529] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp snd_hda_intel snd_intel_dspcfg crct10dif_pclmul snd_hda_codec crc32_pclmul snd_hwdep snd_hda_core ghash_clmulni_intel snd_pcm mei_me e1000e mei ptp prime_numbers pps_core <4>[ 3.422540] CPU: 4 PID: 372 Comm: systemd-udevd Tainted: G U 5.7.0-CI-CI_DRM_8584+ #1 <4>[ 3.422542] Hardware name: System manufacturer System Product Name/Z170 PRO GAMING, BIOS 3402 04/26/2017 <4>[ 3.422544] RIP: 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370 <4>[ 3.422547] Code: 8b 5f 50 48 85 db 0f 84 e8 00 00 00 e8 65 62 01 00 48 c7 c1 08 90 35 82 48 89 da 48 89 c6 48 c7 c7 c8 95 35 82 e8 ec d6 9c ff <0f> 0b 45 31 d2 e9 32 ff ff ff 48 8b 7b 18 8b 4d 9c 48 c7 c2 40 90 <4>[ 3.422548] RSP: 0018:ffffc9000050b808 EFLAGS: 00010082 <4>[ 3.422550] RAX: 0000000000000000 RBX: ffff88822ba975a0 RCX: 0000000000000003 <4>[ 3.422552] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffffffff82383f0a <4>[ 3.422554] RBP: ffffc9000050b878 R08: 0000000000000000 R09: 0000000000000001 <4>[ 3.422555] R10: 0000000000000000 R11: 00000000e5a843ae R12: ffff8882193eb800 <4>[ 3.422557] R13: ffffc9000050b8c8 R14: 0000000000000000 R15: ffff88820c1fd350 <4>[ 3.422559] FS: 00007f3e6ef07680(0000) GS:ffff88822ec00000(0000) knlGS:0000000000000000 <4>[ 3.422561] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4>[ 3.422562] CR2: 00007f91492aa290 CR3: 000000022368a004 CR4: 00000000003606e0 <4>[ 3.422564] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 <4>[ 3.422565] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 <4>[ 3.422567] Call Trace: <4>[ 3.422604] ? fwtable_read32+0x83/0x310 [i915] <4>[ 3.422611] drm_get_last_vbltimestamp+0xb2/0xc0 <4>[ 3.422616] drm_reset_vblank_timestamp+0x54/0xc0 <4>[ 3.422621] drm_crtc_vblank_on+0x83/0x140 <4>[ 3.422670] intel_modeset_setup_hw_state+0x8f7/0x16c0 [i915] <4>[ 3.422676] ? drm_modeset_lock+0xad/0x120 <4>[ 3.422727] intel_modeset_init+0x582/0x1c50 [i915] <4>[ 3.422731] ? _raw_spin_unlock_irqrestore+0x34/0x60 <4>[ 3.422764] ? intel_irq_postinstall+0x284/0x610 [i915] <4>[ 3.422799] i915_driver_probe+0x778/0xf90 [i915] <4>[ 3.422805] ? __pm_runtime_resume+0x4f/0x80 <4>[ 3.422840] i915_pci_probe+0x3b/0x1d0 [i915] <4>[ 3.422843] ? _raw_spin_unlock_irqrestore+0x34/0x60 <4>[ 3.422849] pci_device_probe+0x9e/0x120 <4>[ 3.422853] really_probe+0xea/0x430 <4>[ 3.422858] driver_probe_device+0x10b/0x120 <4>[ 3.422861] device_driver_attach+0x4a/0x50 <4>[ 3.422865] __driver_attach+0x97/0x130 <4>[ 3.422868] ? device_driver_attach+0x50/0x50 <4>[ 3.422871] bus_for_each_dev+0x74/0xc0 <4>[ 3.422875] bus_add_driver+0x142/0x220 <4>[ 3.422879] driver_register+0x56/0xf0 <4>[ 3.422913] i915_init+0x6c/0x7c [i915] <4>[ 3.422916] ? 0xffffffffa08c9000 <4>[ 3.422918] do_one_initcall+0x58/0x300 <4>[ 3.422921] ? do_init_module+0x1d/0x1f2 <4>[ 3.422924] ? rcu_read_lock_sched_held+0x4d/0x80 <4>[ 3.422928] ? kmem_cache_alloc_trace+0x2a6/0x2d0 <4>[ 3.422933] do_init_module+0x56/0x1f2 <4>[ 3.422936] load_module+0x2339/0x2a20 <4>[ 3.422953] ? __do_sys_finit_module+0xe9/0x110 <4>[ 3.422955] __do_sys_finit_module+0xe9/0x110 <4>[ 3.422966] do_syscall_64+0x4f/0x220 <4>[ 3.422969] entry_SYSCALL_64_after_hwframe+0x49/0xb3 <4>[ 3.422971] RIP: 0033:0x7f3e6ea28839 <4>[ 3.422973] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48 <4>[ 3.422975] RSP: 002b:00007ffebbc0c118 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 <4>[ 3.422977] RAX: ffffffffffffffda RBX: 0000557f8afde730 RCX: 00007f3e6ea28839 <4>[ 3.422979] RDX: 0000000000000000 RSI: 0000557f8afd62c0 RDI: 000000000000000f <4>[ 3.422980] RBP: 0000557f8afd62c0 R08: 0000000000000000 R09: 00007ffebbc0c230 <4>[ 3.422982] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000 <4>[ 3.422984] R13: 0000557f8afb99e0 R14: 0000000000020000 R15: 0000000000000000 <4>[ 3.422993] irq event stamp: 603166 <4>[ 3.422996] hardirqs last enabled at (603165): [<ffffffff81a4dfd7>] _raw_spin_unlock_irqrestore+0x47/0x60 <4>[ 3.422998] hardirqs last disabled at (603166): [<ffffffff81a4dd5d>] _raw_spin_lock_irqsave+0xd/0x50 <4>[ 3.423000] softirqs last enabled at (603132): [<ffffffff81e00395>] __do_softirq+0x395/0x -Chris From patchwork at emeril.freedesktop.org Fri Jun 5 22:45:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 05 Jun 2020 22:45:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv3=2C1/1=5D_drm/mm=3A_add_ig=5Ffrag_selfte?= =?utf-8?b?c3QgKHJldjIp?= In-Reply-To: <20200603103223.10443-1-nirmoy.das@amd.com> References: <20200603103223.10443-1-nirmoy.das@amd.com> Message-ID: <159139712889.18506.8045358033523258943@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/1] drm/mm: add ig_frag selftest (rev2) URL : https://patchwork.freedesktop.org/series/77964/ State : success == Summary == CI Bug Log - changes from CI_DRM_8593_full -> Patchwork_17893_full ==================================================== Summary ------- **SUCCESS** No regressions found. New tests --------- New tests have been introduced between CI_DRM_8593_full and Patchwork_17893_full: ### New IGT tests (1) ### * igt at drm_mm@all at frag: - Statuses : 8 pass(s) - Exec time: [0.19, 2.19] s Known issues ------------ Here are the changes found in Patchwork_17893_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at render: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl4/igt at gem_ctx_persistence@legacy-engines-mixed-process at render.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl1/igt at gem_ctx_persistence@legacy-engines-mixed-process at render.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk4/igt at gem_exec_whisper@basic-contexts-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-glk8/igt at gem_exec_whisper@basic-contexts-forked.html * igt at gem_set_tiling_vs_blt@tiled-to-untiled: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +18 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl8/igt at gem_set_tiling_vs_blt@tiled-to-untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl7/igt at gem_set_tiling_vs_blt@tiled-to-untiled.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl7/igt at gen9_exec_parse@allowed-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-kbl1/igt at gen9_exec_parse@allowed-all.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk2/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-glk8/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_color@pipe-d-ctm-0-5: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#1149] / [i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-tglb5/igt at kms_color@pipe-d-ctm-0-5.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-tglb3/igt at kms_color@pipe-d-ctm-0-5.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +9 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl10/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#49]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl6/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl6/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([CI#80] / [i915#1185]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-iclb1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-iclb3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-iclb1/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#93] / [i915#95]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-skl: [PASS][31] -> [INCOMPLETE][32] ([i915#69]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl4/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: - shard-tglb: [PASS][33] -> [DMESG-WARN][34] ([i915#402]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-tglb5/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at vcs0}: - shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * igt at gem_ctx_param@basic: - shard-apl: [DMESG-WARN][37] ([i915#95]) -> [PASS][38] +22 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl4/igt at gem_ctx_param@basic.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl3/igt at gem_ctx_param@basic.html * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][39] ([i915#82]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk1/igt at gem_exec_whisper@basic-queues-forked-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-glk6/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-glk4/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl7/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_legacy@cursor-vs-flip-atomic: - shard-hsw: [FAIL][49] ([i915#57]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-atomic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-hsw2/igt at kms_cursor_legacy@cursor-vs-flip-atomic.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-apl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl7/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl8/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [TIMEOUT][53] -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb4/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1}: - shard-skl: [FAIL][55] ([i915#1928]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [FAIL][57] ([i915#49]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +6 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl4/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl1/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-FAIL][63] ([fdo#108145] / [i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-iclb8/igt at kms_psr@psr2_suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-iclb2/igt at kms_psr@psr2_suspend.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-snb: [INCOMPLETE][67] ([i915#82]) -> [SKIP][68] ([fdo#109271]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-snb6/igt at i915_pm_dc@dc3co-vpb-simulation.html - shard-iclb: [SKIP][69] ([i915#588]) -> [SKIP][70] ([i915#658]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][71] ([i915#468]) -> [FAIL][72] ([i915#454]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-tglb6/igt at i915_pm_dc@dc6-psr.html * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [INCOMPLETE][73] ([CI#80] / [i915#82]) -> [SKIP][74] ([fdo#109271] / [fdo#111827]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb4/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-snb6/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][75] ([i915#1319] / [i915#1635]) -> [FAIL][76] ([fdo#110321] / [fdo#110336]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl2/igt at kms_content_protection@legacy.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-kbl: [DMESG-FAIL][77] ([fdo#110321] / [i915#95]) -> [TIMEOUT][78] ([i915#1319] / [i915#1958]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl2/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-kbl4/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1958]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-kbl7/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-kbl4/igt at kms_content_protection@srm.html - shard-apl: [TIMEOUT][81] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][82] ([fdo#110321] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-apl3/igt at kms_content_protection@srm.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [TIMEOUT][83] -> [SKIP][84] ([fdo#109271]) +2 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8593/shard-snb4/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (10 -> 11) ------------------------------ Additional (1): pig-icl-1065g7 Build changes ------------- * Linux: CI_DRM_8593 -> Patchwork_17893 CI-20190529: 20190529 CI_DRM_8593: 11c8af407947d7e9f56a99419f3867972d6c138d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17893: 375207a3bd0bdff00c10ad2a0722ac5fe9f1bca4 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17893/index.html From rodrigo.vivi at intel.com Fri Jun 5 22:46:27 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Fri, 5 Jun 2020 15:46:27 -0700 Subject: [Intel-gfx] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 In-Reply-To: <20200604101107.GA2948@hirez.programming.kicks-ass.net> References: <20200602174639.GB2604@hirez.programming.kicks-ass.net> <5a40182c8a865d6c5603de4a1ff72c450ff403c3.camel@intel.com> <20200602182710.GD2604@hirez.programming.kicks-ass.net> <20200604101107.GA2948@hirez.programming.kicks-ass.net> Message-ID: <20200605224627.GG3190340@intel.com> On Thu, Jun 04, 2020 at 12:11:07PM +0200, Peter Zijlstra wrote: > On Tue, Jun 02, 2020 at 08:27:10PM +0200, Peter Zijlstra wrote: > > On Tue, Jun 02, 2020 at 06:08:03PM +0000, Souza, Jose wrote: > > > Hi Peter > > > Please file a bug by follow this instructions: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs > > > > *sigh*, top posting and webforms :-( > > > > Steps to reproduce: Boot into X > > > > How often: Always > > > > uname -r: 5.6.0-2-amd64 > > > > Machine: Supermicro X11SSZ-F > > > > Display connector: > > > > [ 14.907] (II) intel(0): switch to mode 3840x2160 at 60.0 on DP2 using pipe 0, position (0, 0), rotation normal, reflection none > > [ 14.918] (II) intel(0): switch to mode 3840x2160 at 60.0 on DP3 using pipe 1, position (0, 0), rotation normal, reflection none I have just filed the issue on gitlab: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs > > > > > > I'll add the kernel parameters next time I reboot this thing, I'll also > > add the latest drm next time I build a kernel for this machine. > > dmesg attached, I've yet to build a new kernel for this box.. Yes, testing with drm-tip would be great. Please! Thanks for reporting, Rodrigo. > [ 0.000000] microcode: microcode updated early to revision 0xd6, date = 2019-10-03 > [ 0.000000] Linux version 5.6.0-2-amd64 (debian-kernel at lists.debian.org) (gcc version 9.3.0 (Debian 9.3.0-13)) #1 SMP Debian 5.6.14-1 (2020-05-23) > [ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-5.6.0-2-amd64 root=UUID=8b0cce80-c4f1-4b44-8227-b0e10b4cb575 ro drm.debug=0x1e log_buf_len=1M quiet drm.debug=0x1e log_buf_len=1M > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' > [ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 > [ 0.000000] x86/fpu: xstate_offset[3]: 832, xstate_sizes[3]: 64 > [ 0.000000] x86/fpu: xstate_offset[4]: 896, xstate_sizes[4]: 64 > [ 0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format. > [ 0.000000] BIOS-provided physical RAM map: > [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000098bff] usable > [ 0.000000] BIOS-e820: [mem 0x0000000000098c00-0x000000000009ffff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000000e0000-0x00000000000fffff] reserved > [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x0000000080be4fff] usable > [ 0.000000] BIOS-e820: [mem 0x0000000080be5000-0x0000000080be5fff] ACPI NVS > [ 0.000000] BIOS-e820: [mem 0x0000000080be6000-0x0000000080be6fff] reserved > [ 0.000000] BIOS-e820: [mem 0x0000000080be7000-0x000000008ac6efff] usable > [ 0.000000] BIOS-e820: [mem 0x000000008ac6f000-0x000000008b022fff] reserved > [ 0.000000] BIOS-e820: [mem 0x000000008b023000-0x000000008b158fff] usable > [ 0.000000] BIOS-e820: [mem 0x000000008b159000-0x000000008b82efff] ACPI NVS > [ 0.000000] BIOS-e820: [mem 0x000000008b82f000-0x000000008bffefff] reserved > [ 0.000000] BIOS-e820: [mem 0x000000008bfff000-0x000000008bffffff] usable > [ 0.000000] BIOS-e820: [mem 0x000000008c000000-0x000000008f7fffff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed00fff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved > [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000086e7fffff] usable > [ 0.000000] NX (Execute Disable) protection: active > [ 0.000000] SMBIOS 3.0.0 present. > [ 0.000000] DMI: Supermicro Super Server/X11SSZ-F, BIOS 2.0 01/26/2017 > [ 0.000000] tsc: Detected 3500.000 MHz processor > [ 0.001405] tsc: Detected 3499.912 MHz TSC > [ 0.001406] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved > [ 0.001407] e820: remove [mem 0x000a0000-0x000fffff] usable > [ 0.001411] last_pfn = 0x86e800 max_arch_pfn = 0x400000000 > [ 0.001414] MTRR default type: write-back > [ 0.001414] MTRR fixed ranges enabled: > [ 0.001415] 00000-9FFFF write-back > [ 0.001416] A0000-BFFFF uncachable > [ 0.001416] C0000-FFFFF write-protect > [ 0.001417] MTRR variable ranges enabled: > [ 0.001418] 0 base 00C0000000 mask 7FC0000000 uncachable > [ 0.001418] 1 base 00A0000000 mask 7FE0000000 uncachable > [ 0.001419] 2 base 0090000000 mask 7FF0000000 uncachable > [ 0.001419] 3 base 008E000000 mask 7FFE000000 uncachable > [ 0.001420] 4 base 008D000000 mask 7FFF000000 uncachable > [ 0.001420] 5 disabled > [ 0.001420] 6 disabled > [ 0.001421] 7 disabled > [ 0.001421] 8 disabled > [ 0.001421] 9 disabled > [ 0.001815] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT > [ 0.001948] last_pfn = 0x8c000 max_arch_pfn = 0x400000000 > [ 0.007624] found SMP MP-table at [mem 0x000fcce0-0x000fccef] > [ 0.007674] Using GB pages for direct mapping > [ 0.007676] BRK [0x6bb201000, 0x6bb201fff] PGTABLE > [ 0.007677] BRK [0x6bb202000, 0x6bb202fff] PGTABLE > [ 0.007677] BRK [0x6bb203000, 0x6bb203fff] PGTABLE > [ 0.007694] BRK [0x6bb204000, 0x6bb204fff] PGTABLE > [ 0.007695] BRK [0x6bb205000, 0x6bb205fff] PGTABLE > [ 0.007767] BRK [0x6bb206000, 0x6bb206fff] PGTABLE > [ 0.007792] BRK [0x6bb207000, 0x6bb207fff] PGTABLE > [ 0.007869] BRK [0x6bb208000, 0x6bb208fff] PGTABLE > [ 0.007910] BRK [0x6bb209000, 0x6bb209fff] PGTABLE > [ 0.007942] BRK [0x6bb20a000, 0x6bb20afff] PGTABLE > [ 0.008010] printk: log_buf_len: 1048576 bytes > [ 0.008011] printk: early log buf free: 126272(96%) > [ 0.008012] RAMDISK: [mem 0x32ae7000-0x3556afff] > [ 0.008016] ACPI: Early table checksum verification disabled > [ 0.008018] ACPI: RSDP 0x00000000000F05B0 000024 (v02 SUPERM) > [ 0.008020] ACPI: XSDT 0x000000008B1590C0 0000FC (v01 SUPERM SUPERM 01072009 AMI 00010013) > [ 0.008024] ACPI: FACP 0x000000008B17F320 000114 (v06 01072009 AMI 00010013) > [ 0.008028] ACPI: DSDT 0x000000008B159250 0260CB (v02 SUPERM SMCI--MB 01072009 INTL 20160422) > [ 0.008030] ACPI: FACS 0x000000008B82EC80 000040 > [ 0.008032] ACPI: APIC 0x000000008B17F438 0000BC (v03 01072009 AMI 00010013) > [ 0.008033] ACPI: FPDT 0x000000008B17F4F8 000044 (v01 01072009 AMI 00010013) > [ 0.008035] ACPI: SPMI 0x000000008B17F540 000040 (v05 SUPERM SMCI--MB 00000000 AMI. 00000000) > [ 0.008037] ACPI: MCFG 0x000000008B17F580 00003C (v01 SUPERM SMCI--MB 01072009 MSFT 00000097) > [ 0.008039] ACPI: SSDT 0x000000008B17F5C0 000224 (v01 SataRe SataTabl 00001000 INTL 20160422) > [ 0.008040] ACPI: FIDT 0x000000008B17F7E8 00009C (v01 SUPERM SMCI--MB 01072009 AMI 00010013) > [ 0.008042] ACPI: SSDT 0x000000008B17F888 003159 (v02 SaSsdt SaSsdt 00003000 INTL 20160422) > [ 0.008044] ACPI: SSDT 0x000000008B1829E8 00255F (v02 PegSsd PegSsdt 00001000 INTL 20160422) > [ 0.008046] ACPI: HPET 0x000000008B184F48 000038 (v01 INTEL SKL 00000001 MSFT 0000005F) > [ 0.008047] ACPI: SSDT 0x000000008B184F80 000024 (v02 INTEL OEM_RTD3 00001000 INTL 20160422) > [ 0.008049] ACPI: SSDT 0x000000008B184FA8 000DE5 (v02 INTEL Ther_Rvp 00001000 INTL 20160422) > [ 0.008051] ACPI: SSDT 0x000000008B185D90 000AF2 (v02 INTEL xh_rvp08 00000000 INTL 20160422) > [ 0.008052] ACPI: UEFI 0x000000008B186888 000042 (v01 INTEL EDK2 00000002 01000013) > [ 0.008054] ACPI: SSDT 0x000000008B1868D0 000EDE (v02 CpuRef CpuSsdt 00003000 INTL 20160422) > [ 0.008056] ACPI: LPIT 0x000000008B1877B0 000094 (v01 INTEL SKL 00000000 MSFT 0000005F) > [ 0.008057] ACPI: WSMT 0x000000008B187848 000028 (v01 INTEL SKL 00000000 MSFT 0000005F) > [ 0.008059] ACPI: SSDT 0x000000008B187870 00029F (v02 INTEL sensrhub 00000000 INTL 20160422) > [ 0.008061] ACPI: SSDT 0x000000008B187B10 003002 (v02 INTEL PtidDevc 00001000 INTL 20160422) > [ 0.008062] ACPI: DBGP 0x000000008B18AB18 000034 (v01 INTEL 00000002 MSFT 0000005F) > [ 0.008064] ACPI: DBG2 0x000000008B18AB50 000054 (v00 INTEL 00000002 MSFT 0000005F) > [ 0.008065] ACPI: DMAR 0x000000008B18ABA8 000114 (v01 INTEL SKL 00000001 INTL 00000001) > [ 0.008067] ACPI: ASF! 0x000000008B18ACC0 0000A0 (v32 INTEL HCG 00000001 TFSM 000F4240) > [ 0.008069] ACPI: EINJ 0x000000008B18AD60 000130 (v01 AMI AMI.EINJ 00000000 AMI. 00000000) > [ 0.008071] ACPI: ERST 0x000000008B18AE90 000230 (v01 AMIER AMI.ERST 00000000 AMI. 00000000) > [ 0.008072] ACPI: BERT 0x000000008B18B0C0 000030 (v01 AMI AMI.BERT 00000000 AMI. 00000000) > [ 0.008074] ACPI: HEST 0x000000008B18B0F0 0000A8 (v01 AMI AMI.HEST 00000000 AMI. 00000000) > [ 0.008079] ACPI: Local APIC address 0xfee00000 > [ 0.008229] No NUMA configuration found > [ 0.008229] Faking a node at [mem 0x0000000000000000-0x000000086e7fffff] > [ 0.008232] NODE_DATA(0) allocated [mem 0x86e6fb000-0x86e6fffff] > [ 0.008261] Zone ranges: > [ 0.008262] DMA [mem 0x0000000000001000-0x0000000000ffffff] > [ 0.008262] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] > [ 0.008263] Normal [mem 0x0000000100000000-0x000000086e7fffff] > [ 0.008264] Device empty > [ 0.008264] Movable zone start for each node > [ 0.008265] Early memory node ranges > [ 0.008265] node 0: [mem 0x0000000000001000-0x0000000000097fff] > [ 0.008266] node 0: [mem 0x0000000000100000-0x0000000080be4fff] > [ 0.008266] node 0: [mem 0x0000000080be7000-0x000000008ac6efff] > [ 0.008267] node 0: [mem 0x000000008b023000-0x000000008b158fff] > [ 0.008267] node 0: [mem 0x000000008bfff000-0x000000008bffffff] > [ 0.008267] node 0: [mem 0x0000000100000000-0x000000086e7fffff] > [ 0.008451] Zeroed struct page in unavailable ranges: 27333 pages > [ 0.008452] Initmem setup node 0 [mem 0x0000000000001000-0x000000086e7fffff] > [ 0.008453] On node 0 totalpages: 8361275 > [ 0.008454] DMA zone: 64 pages used for memmap > [ 0.008454] DMA zone: 21 pages reserved > [ 0.008455] DMA zone: 3991 pages, LIFO batch:0 > [ 0.008498] DMA32 zone: 8823 pages used for memmap > [ 0.008498] DMA32 zone: 564644 pages, LIFO batch:63 > [ 0.014514] Normal zone: 121760 pages used for memmap > [ 0.014515] Normal zone: 7792640 pages, LIFO batch:63 > [ 0.014866] Reserving Intel graphics memory at [mem 0x8d800000-0x8f7fffff] > [ 0.015181] ACPI: PM-Timer IO Port: 0x1808 > [ 0.015182] ACPI: Local APIC address 0xfee00000 > [ 0.015186] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) > [ 0.015187] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1]) > [ 0.015187] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1]) > [ 0.015188] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1]) > [ 0.015188] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1]) > [ 0.015188] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1]) > [ 0.015189] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1]) > [ 0.015189] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1]) > [ 0.015215] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119 > [ 0.015216] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) > [ 0.015217] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) > [ 0.015218] ACPI: IRQ0 used by override. > [ 0.015218] ACPI: IRQ9 used by override. > [ 0.015219] Using ACPI (MADT) for SMP configuration information > [ 0.015220] ACPI: HPET id: 0x8086a201 base: 0xfed00000 > [ 0.015223] smpboot: Allowing 8 CPUs, 0 hotplug CPUs > [ 0.015235] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff] > [ 0.015236] PM: hibernation: Registered nosave memory: [mem 0x00098000-0x00098fff] > [ 0.015236] PM: hibernation: Registered nosave memory: [mem 0x00099000-0x0009ffff] > [ 0.015236] PM: hibernation: Registered nosave memory: [mem 0x000a0000-0x000dffff] > [ 0.015237] PM: hibernation: Registered nosave memory: [mem 0x000e0000-0x000fffff] > [ 0.015238] PM: hibernation: Registered nosave memory: [mem 0x80be5000-0x80be5fff] > [ 0.015238] PM: hibernation: Registered nosave memory: [mem 0x80be6000-0x80be6fff] > [ 0.015239] PM: hibernation: Registered nosave memory: [mem 0x8ac6f000-0x8b022fff] > [ 0.015240] PM: hibernation: Registered nosave memory: [mem 0x8b159000-0x8b82efff] > [ 0.015240] PM: hibernation: Registered nosave memory: [mem 0x8b82f000-0x8bffefff] > [ 0.015241] PM: hibernation: Registered nosave memory: [mem 0x8c000000-0x8f7fffff] > [ 0.015242] PM: hibernation: Registered nosave memory: [mem 0x8f800000-0xdfffffff] > [ 0.015242] PM: hibernation: Registered nosave memory: [mem 0xe0000000-0xefffffff] > [ 0.015242] PM: hibernation: Registered nosave memory: [mem 0xf0000000-0xfdffffff] > [ 0.015243] PM: hibernation: Registered nosave memory: [mem 0xfe000000-0xfe010fff] > [ 0.015243] PM: hibernation: Registered nosave memory: [mem 0xfe011000-0xfebfffff] > [ 0.015243] PM: hibernation: Registered nosave memory: [mem 0xfec00000-0xfec00fff] > [ 0.015244] PM: hibernation: Registered nosave memory: [mem 0xfec01000-0xfecfffff] > [ 0.015244] PM: hibernation: Registered nosave memory: [mem 0xfed00000-0xfed00fff] > [ 0.015244] PM: hibernation: Registered nosave memory: [mem 0xfed01000-0xfedfffff] > [ 0.015245] PM: hibernation: Registered nosave memory: [mem 0xfee00000-0xfee00fff] > [ 0.015245] PM: hibernation: Registered nosave memory: [mem 0xfee01000-0xfeffffff] > [ 0.015245] PM: hibernation: Registered nosave memory: [mem 0xff000000-0xffffffff] > [ 0.015246] [mem 0x8f800000-0xdfffffff] available for PCI devices > [ 0.015247] Booting paravirtualized kernel on bare hardware > [ 0.015249] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns > [ 0.017968] setup_percpu: NR_CPUS:512 nr_cpumask_bits:512 nr_cpu_ids:8 nr_node_ids:1 > [ 0.018085] percpu: Embedded 55 pages/cpu s188120 r8192 d28968 u262144 > [ 0.018090] pcpu-alloc: s188120 r8192 d28968 u262144 alloc=1*2097152 > [ 0.018090] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 > [ 0.018105] Built 1 zonelists, mobility grouping on. Total pages: 8230607 > [ 0.018105] Policy zone: Normal > [ 0.018106] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-5.6.0-2-amd64 root=UUID=8b0cce80-c4f1-4b44-8227-b0e10b4cb575 ro drm.debug=0x1e log_buf_len=1M quiet drm.debug=0x1e log_buf_len=1M > [ 0.019244] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear) > [ 0.019780] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear) > [ 0.019835] mem auto-init: stack:off, heap alloc:off, heap free:off > [ 0.033348] Memory: 2296456K/33445100K available (10243K kernel code, 1285K rwdata, 3976K rodata, 1612K init, 1976K bss, 710496K reserved, 0K cma-reserved) > [ 0.033354] random: get_random_u64 called from __kmem_cache_create+0x3e/0x530 with crng_init=0 > [ 0.033429] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 > [ 0.033437] Kernel/User page tables isolation: enabled > [ 0.033446] ftrace: allocating 34646 entries in 136 pages > [ 0.042912] ftrace: allocated 136 pages with 2 groups > [ 0.042970] rcu: Hierarchical RCU implementation. > [ 0.042971] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=8. > [ 0.042972] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. > [ 0.042972] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 > [ 0.044921] NR_IRQS: 33024, nr_irqs: 2048, preallocated irqs: 16 > [ 0.045216] random: crng done (trusting CPU's manufacturer) > [ 0.047453] Console: colour VGA+ 80x25 > [ 0.047456] printk: console [tty0] enabled > [ 0.047468] ACPI: Core revision 20200110 > [ 0.047689] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns > [ 0.047753] APIC: Switch to symmetric I/O mode setup > [ 0.047754] DMAR: Host address width 39 > [ 0.047755] DMAR: DRHD base: 0x000000fed90000 flags: 0x0 > [ 0.047758] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 7e3ff0505e > [ 0.047759] DMAR: DRHD base: 0x000000fed91000 flags: 0x1 > [ 0.047761] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da > [ 0.047762] DMAR: RMRR base: 0x0000008af45000 end: 0x0000008af64fff > [ 0.047763] DMAR: RMRR base: 0x0000008d000000 end: 0x0000008f7fffff > [ 0.047763] DMAR: ANDD device: 1 name: \_SB.PCI0.I2C0 > [ 0.047764] DMAR: ANDD device: 2 name: \_SB.PCI0.I2C1 > [ 0.047764] DMAR: ANDD device: 9 name: \_SB.PCI0.UA00 > [ 0.047765] DMAR-IR: IOAPIC id 2 under DRHD base 0xfed91000 IOMMU 1 > [ 0.047766] DMAR-IR: HPET id 0 under DRHD base 0xfed91000 > [ 0.047766] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping. > [ 0.049206] DMAR-IR: Enabled IRQ remapping in x2apic mode > [ 0.049207] x2apic enabled > [ 0.049219] Switched APIC routing to cluster x2apic. > [ 0.053180] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 > [ 0.071756] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x3272fd97217, max_idle_ns: 440795241220 ns > [ 0.071759] Calibrating delay loop (skipped), value calculated using timer frequency.. 6999.82 BogoMIPS (lpj=13999648) > [ 0.071760] pid_max: default: 32768 minimum: 301 > [ 0.071779] LSM: Security Framework initializing > [ 0.071783] Yama: disabled by default; enable with sysctl kernel.yama.* > [ 0.071798] AppArmor: AppArmor initialized > [ 0.071799] TOMOYO Linux initialized > [ 0.071846] Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) > [ 0.071883] Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) > [ 0.072051] mce: CPU0: Thermal monitoring enabled (TM1) > [ 0.072066] process: using mwait in idle threads > [ 0.072067] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8 > [ 0.072068] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4 > [ 0.072069] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization > [ 0.072070] Spectre V2 : Mitigation: Full generic retpoline > [ 0.072071] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch > [ 0.072071] Spectre V2 : Enabling Restricted Speculation for firmware calls > [ 0.072072] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier > [ 0.072072] Spectre V2 : User space: Mitigation: STIBP via seccomp and prctl > [ 0.072073] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp > [ 0.072075] TAA: Mitigation: Clear CPU buffers > [ 0.072075] MDS: Mitigation: Clear CPU buffers > [ 0.072245] Freeing SMP alternatives memory: 32K > [ 0.075804] TSC deadline timer enabled > [ 0.075809] smpboot: CPU0: Intel(R) Xeon(R) CPU E3-1245 v5 @ 3.50GHz (family: 0x6, model: 0x5e, stepping: 0x3) > [ 0.075874] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver. > [ 0.075878] ... version: 4 > [ 0.075878] ... bit width: 48 > [ 0.075879] ... generic registers: 4 > [ 0.075879] ... value mask: 0000ffffffffffff > [ 0.075879] ... max period: 00007fffffffffff > [ 0.075880] ... fixed-purpose events: 3 > [ 0.075880] ... event mask: 000000070000000f > [ 0.075907] rcu: Hierarchical SRCU implementation. > [ 0.076474] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter. > [ 0.076517] smp: Bringing up secondary CPUs ... > [ 0.076563] x86: Booting SMP configuration: > [ 0.076564] .... node #0, CPUs: #1 #2 #3 #4 > [ 0.081378] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details. > [ 0.081378] TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details. > [ 0.081378] #5 #6 #7 > [ 0.081378] smp: Brought up 1 node, 8 CPUs > [ 0.081378] smpboot: Max logical packages: 1 > [ 0.081378] smpboot: Total of 8 processors activated (55998.59 BogoMIPS) > [ 0.155762] node 0 initialised, 7609537 pages in 72ms > [ 0.156270] devtmpfs: initialized > [ 0.156270] x86/mm: Memory block size: 128MB > [ 0.160353] PM: Registering ACPI NVS region [mem 0x80be5000-0x80be5fff] (4096 bytes) > [ 0.160353] PM: Registering ACPI NVS region [mem 0x8b159000-0x8b82efff] (7168000 bytes) > [ 0.160353] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns > [ 0.160353] futex hash table entries: 2048 (order: 5, 131072 bytes, linear) > [ 0.160353] pinctrl core: initialized pinctrl subsystem > [ 0.160353] thermal_sys: Registered thermal governor 'fair_share' > [ 0.160353] thermal_sys: Registered thermal governor 'bang_bang' > [ 0.160353] thermal_sys: Registered thermal governor 'step_wise' > [ 0.160353] thermal_sys: Registered thermal governor 'user_space' > [ 0.160353] NET: Registered protocol family 16 > [ 0.160353] audit: initializing netlink subsys (disabled) > [ 0.160353] audit: type=2000 audit(1591264845.112:1): state=initialized audit_enabled=0 res=1 > [ 0.160353] cpuidle: using governor ladder > [ 0.160353] cpuidle: using governor menu > [ 0.160353] ACPI: bus type PCI registered > [ 0.160353] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 > [ 0.160353] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) > [ 0.160353] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 > [ 0.160353] PCI: Using configuration type 1 for base access > [ 0.161723] ENERGY_PERF_BIAS: Set to 'normal', was 'performance' > [ 0.161727] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages > [ 0.161727] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages > [ 0.256378] ACPI: Added _OSI(Module Device) > [ 0.256378] ACPI: Added _OSI(Processor Device) > [ 0.256378] ACPI: Added _OSI(3.0 _SCP Extensions) > [ 0.256378] ACPI: Added _OSI(Processor Aggregator Device) > [ 0.256378] ACPI: Added _OSI(Linux-Dell-Video) > [ 0.256378] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) > [ 0.256378] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics) > [ 0.285387] ACPI: 10 ACPI AML tables successfully acquired and loaded > [ 0.287173] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored > [ 0.290492] ACPI: Dynamic OEM Table Load: > [ 0.290496] ACPI: SSDT 0xFFFF8D5D471C8800 000738 (v02 PmRef Cpu0Ist 00003000 INTL 20160422) > [ 0.291399] ACPI: \_PR_.CPU0: _OSC native thermal LVT Acked > [ 0.292269] ACPI: Dynamic OEM Table Load: > [ 0.292273] ACPI: SSDT 0xFFFF8D62FB315C00 0003FF (v02 PmRef Cpu0Cst 00003001 INTL 20160422) > [ 0.293140] ACPI: Dynamic OEM Table Load: > [ 0.293143] ACPI: SSDT 0xFFFF8D5D47338200 000115 (v02 PmRef Cpu0Hwp 00003000 INTL 20160422) > [ 0.293929] ACPI: Dynamic OEM Table Load: > [ 0.293931] ACPI: SSDT 0xFFFF8D5D4733BE00 0001A4 (v02 PmRef HwpLvt 00003000 INTL 20160422) > [ 0.294919] ACPI: Dynamic OEM Table Load: > [ 0.294924] ACPI: SSDT 0xFFFF8D648B0D6800 00065C (v02 PmRef ApIst 00003000 INTL 20160422) > [ 0.295947] ACPI: Dynamic OEM Table Load: > [ 0.295950] ACPI: SSDT 0xFFFF8D5D4733B000 000197 (v02 PmRef ApHwp 00003000 INTL 20160422) > [ 0.296809] ACPI: Dynamic OEM Table Load: > [ 0.296811] ACPI: SSDT 0xFFFF8D5D47338000 00018A (v02 PmRef ApCst 00003000 INTL 20160422) > [ 0.299965] ACPI: Interpreter enabled > [ 0.299995] ACPI: (supports S0 S3 S4 S5) > [ 0.299995] ACPI: Using IOAPIC for interrupt routing > [ 0.300040] HEST: Table parsing has been initialized. > [ 0.300041] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug > [ 0.300687] ACPI: Enabled 6 GPEs in block 00 to 7F > [ 0.302397] ACPI: Power Resource [PG00] (on) > [ 0.302684] ACPI: Power Resource [PG01] (on) > [ 0.302955] ACPI: Power Resource [PG02] (on) > [ 0.304697] ACPI: Power Resource [WRST] (on) > [ 0.304941] ACPI: Power Resource [WRST] (on) > [ 0.305205] ACPI: Power Resource [WRST] (on) > [ 0.305466] ACPI: Power Resource [WRST] (on) > [ 0.305697] ACPI: Power Resource [WRST] (on) > [ 0.305935] ACPI: Power Resource [WRST] (on) > [ 0.306163] ACPI: Power Resource [WRST] (on) > [ 0.306389] ACPI: Power Resource [WRST] (on) > [ 0.306616] ACPI: Power Resource [WRST] (on) > [ 0.306845] ACPI: Power Resource [WRST] (on) > [ 0.307100] ACPI: Power Resource [WRST] (on) > [ 0.307327] ACPI: Power Resource [WRST] (on) > [ 0.307554] ACPI: Power Resource [WRST] (on) > [ 0.307785] ACPI: Power Resource [WRST] (on) > [ 0.308016] ACPI: Power Resource [WRST] (on) > [ 0.308247] ACPI: Power Resource [WRST] (on) > [ 0.308477] ACPI: Power Resource [WRST] (on) > [ 0.309341] ACPI: Power Resource [WRST] (on) > [ 0.309569] ACPI: Power Resource [WRST] (on) > [ 0.309796] ACPI: Power Resource [WRST] (on) > [ 0.318885] ACPI: Power Resource [FN00] (off) > [ 0.318941] ACPI: Power Resource [FN01] (off) > [ 0.318993] ACPI: Power Resource [FN02] (off) > [ 0.319045] ACPI: Power Resource [FN03] (off) > [ 0.319099] ACPI: Power Resource [FN04] (off) > [ 0.319874] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe]) > [ 0.319878] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] > [ 0.321077] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME AER PCIeCapability LTR] > [ 0.321595] PCI host bridge to bus 0000:00 > [ 0.321596] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] > [ 0.321597] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] > [ 0.321598] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] > [ 0.321598] pci_bus 0000:00: root bus resource [mem 0x8f800000-0xdfffffff window] > [ 0.321599] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window] > [ 0.321600] pci_bus 0000:00: root bus resource [bus 00-fe] > [ 0.321607] pci 0000:00:00.0: [8086:1918] type 00 class 0x060000 > [ 0.321855] pci 0000:00:02.0: [8086:191d] type 00 class 0x030000 > [ 0.321863] pci 0000:00:02.0: reg 0x10: [mem 0xdd000000-0xddffffff 64bit] > [ 0.321867] pci 0000:00:02.0: reg 0x18: [mem 0xc0000000-0xcfffffff 64bit pref] > [ 0.321870] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f] > [ 0.321988] pci 0000:00:08.0: [8086:1911] type 00 class 0x088000 > [ 0.321997] pci 0000:00:08.0: reg 0x10: [mem 0xdf253000-0xdf253fff 64bit] > [ 0.322118] pci 0000:00:14.0: [8086:a12f] type 00 class 0x0c0330 > [ 0.322136] pci 0000:00:14.0: reg 0x10: [mem 0xdf230000-0xdf23ffff 64bit] > [ 0.322190] pci 0000:00:14.0: PME# supported from D3hot D3cold > [ 0.322340] pci 0000:00:14.2: [8086:a131] type 00 class 0x118000 > [ 0.322358] pci 0000:00:14.2: reg 0x10: [mem 0xdf252000-0xdf252fff 64bit] > [ 0.322529] pci 0000:00:15.0: [8086:a160] type 00 class 0x118000 > [ 0.322577] pci 0000:00:15.0: reg 0x10: [mem 0xdf251000-0xdf251fff 64bit] > [ 0.322829] pci 0000:00:15.1: [8086:a161] type 00 class 0x118000 > [ 0.322889] pci 0000:00:15.1: reg 0x10: [mem 0xdf250000-0xdf250fff 64bit] > [ 0.323125] pci 0000:00:16.0: [8086:a13a] type 00 class 0x078000 > [ 0.323147] pci 0000:00:16.0: reg 0x10: [mem 0xdf24f000-0xdf24ffff 64bit] > [ 0.323210] pci 0000:00:16.0: PME# supported from D3hot > [ 0.323323] pci 0000:00:16.3: [8086:a13d] type 00 class 0x070002 > [ 0.323336] pci 0000:00:16.3: reg 0x10: [io 0xf0a0-0xf0a7] > [ 0.323342] pci 0000:00:16.3: reg 0x14: [mem 0xdf24e000-0xdf24efff] > [ 0.323468] pci 0000:00:17.0: [8086:a102] type 00 class 0x010601 > [ 0.323482] pci 0000:00:17.0: reg 0x10: [mem 0xdf248000-0xdf249fff] > [ 0.323487] pci 0000:00:17.0: reg 0x14: [mem 0xdf24d000-0xdf24d0ff] > [ 0.323493] pci 0000:00:17.0: reg 0x18: [io 0xf090-0xf097] > [ 0.323498] pci 0000:00:17.0: reg 0x1c: [io 0xf080-0xf083] > [ 0.323504] pci 0000:00:17.0: reg 0x20: [io 0xf060-0xf07f] > [ 0.323509] pci 0000:00:17.0: reg 0x24: [mem 0xdf24c000-0xdf24c7ff] > [ 0.323541] pci 0000:00:17.0: PME# supported from D3hot > [ 0.323653] pci 0000:00:1b.0: [8086:a167] type 01 class 0x060400 > [ 0.323722] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold > [ 0.323737] pci 0000:00:1b.0: Intel SPT PCH root port ACS workaround enabled > [ 0.323886] pci 0000:00:1c.0: [8086:a110] type 01 class 0x060400 > [ 0.323954] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold > [ 0.323969] pci 0000:00:1c.0: Intel SPT PCH root port ACS workaround enabled > [ 0.324114] pci 0000:00:1d.0: [8086:a118] type 01 class 0x060400 > [ 0.324169] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold > [ 0.324290] pci 0000:00:1d.1: [8086:a119] type 01 class 0x060400 > [ 0.324350] pci 0000:00:1d.1: PME# supported from D0 D3hot D3cold > [ 0.324363] pci 0000:00:1d.1: Intel SPT PCH root port ACS workaround enabled > [ 0.324485] pci 0000:00:1d.2: [8086:a11a] type 01 class 0x060400 > [ 0.324544] pci 0000:00:1d.2: PME# supported from D0 D3hot D3cold > [ 0.324557] pci 0000:00:1d.2: Intel SPT PCH root port ACS workaround enabled > [ 0.324729] pci 0000:00:1e.0: [8086:a127] type 00 class 0x118000 > [ 0.324778] pci 0000:00:1e.0: reg 0x10: [mem 0xdf24b000-0xdf24bfff 64bit] > [ 0.325019] pci 0000:00:1f.0: [8086:a149] type 00 class 0x060100 > [ 0.325212] pci 0000:00:1f.2: [8086:a121] type 00 class 0x058000 > [ 0.325225] pci 0000:00:1f.2: reg 0x10: [mem 0xdf244000-0xdf247fff] > [ 0.325368] pci 0000:00:1f.3: [8086:a170] type 00 class 0x040300 > [ 0.325392] pci 0000:00:1f.3: reg 0x10: [mem 0xdf240000-0xdf243fff 64bit] > [ 0.325420] pci 0000:00:1f.3: reg 0x20: [mem 0xdf220000-0xdf22ffff 64bit] > [ 0.325463] pci 0000:00:1f.3: PME# supported from D3hot D3cold > [ 0.325618] pci 0000:00:1f.4: [8086:a123] type 00 class 0x0c0500 > [ 0.325677] pci 0000:00:1f.4: reg 0x10: [mem 0xdf24a000-0xdf24a0ff 64bit] > [ 0.325746] pci 0000:00:1f.4: reg 0x20: [io 0xf040-0xf05f] > [ 0.325921] pci 0000:00:1f.6: [8086:15b7] type 00 class 0x020000 > [ 0.325946] pci 0000:00:1f.6: reg 0x10: [mem 0xdf200000-0xdf21ffff] > [ 0.326047] pci 0000:00:1f.6: PME# supported from D0 D3hot D3cold > [ 0.326187] pci 0000:00:1b.0: PCI bridge to [bus 01] > [ 0.326225] pci 0000:00:1c.0: PCI bridge to [bus 02] > [ 0.326267] acpiphp: Slot [1] registered > [ 0.326269] pci 0000:00:1d.0: PCI bridge to [bus 03] > [ 0.326340] pci 0000:04:00.0: [8086:1533] type 00 class 0x020000 > [ 0.326371] pci 0000:04:00.0: reg 0x10: [mem 0xdf100000-0xdf17ffff] > [ 0.326395] pci 0000:04:00.0: reg 0x18: [io 0xe000-0xe01f] > [ 0.326407] pci 0000:04:00.0: reg 0x1c: [mem 0xdf180000-0xdf183fff] > [ 0.326544] pci 0000:04:00.0: PME# supported from D0 D3hot D3cold > [ 0.326704] pci 0000:00:1d.1: PCI bridge to [bus 04] > [ 0.326706] pci 0000:00:1d.1: bridge window [io 0xe000-0xefff] > [ 0.326707] pci 0000:00:1d.1: bridge window [mem 0xdf100000-0xdf1fffff] > [ 0.326760] pci 0000:05:00.0: [1a03:1150] type 01 class 0x060400 > [ 0.326824] pci 0000:05:00.0: enabling Extended Tags > [ 0.326887] pci 0000:05:00.0: supports D1 D2 > [ 0.326888] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold > [ 0.326976] pci 0000:05:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' > [ 0.326984] pci 0000:00:1d.2: PCI bridge to [bus 05-06] > [ 0.326986] pci 0000:00:1d.2: bridge window [io 0xd000-0xdfff] > [ 0.326988] pci 0000:00:1d.2: bridge window [mem 0xde000000-0xdf0fffff] > [ 0.327030] pci_bus 0000:06: extended config space not accessible > [ 0.327048] pci 0000:06:00.0: [1a03:2000] type 00 class 0x030000 > [ 0.327066] pci 0000:06:00.0: reg 0x10: [mem 0xde000000-0xdeffffff] > [ 0.327074] pci 0000:06:00.0: reg 0x14: [mem 0xdf000000-0xdf01ffff] > [ 0.327082] pci 0000:06:00.0: reg 0x18: [io 0xd000-0xd07f] > [ 0.327161] pci 0000:06:00.0: supports D1 D2 > [ 0.327161] pci 0000:06:00.0: PME# supported from D0 D1 D2 D3hot D3cold > [ 0.327241] pci 0000:05:00.0: PCI bridge to [bus 06] > [ 0.327247] pci 0000:05:00.0: bridge window [io 0xd000-0xdfff] > [ 0.327250] pci 0000:05:00.0: bridge window [mem 0xde000000-0xdf0fffff] > [ 0.329656] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15) > [ 0.329656] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15) > [ 0.329656] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15) > [ 0.329656] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15) > [ 0.329656] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15) > [ 0.329656] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15) > [ 0.329656] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15) > [ 0.329656] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15) > [ 0.329656] iommu: Default domain type: Translated > [ 0.329656] pci 0000:00:02.0: vgaarb: setting as boot VGA device > [ 0.329656] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none > [ 0.329656] pci 0000:06:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none > [ 0.329656] pci 0000:00:02.0: vgaarb: no bridge control possible > [ 0.329656] pci 0000:06:00.0: vgaarb: bridge control possible > [ 0.329656] vgaarb: loaded > [ 0.329656] EDAC MC: Ver: 3.0.0 > [ 0.329656] PCI: Using ACPI for IRQ routing > [ 0.358681] PCI: pci_cache_line_size set to 64 bytes > [ 0.358802] e820: reserve RAM buffer [mem 0x00098c00-0x0009ffff] > [ 0.358803] e820: reserve RAM buffer [mem 0x80be5000-0x83ffffff] > [ 0.358804] e820: reserve RAM buffer [mem 0x8ac6f000-0x8bffffff] > [ 0.358804] e820: reserve RAM buffer [mem 0x8b159000-0x8bffffff] > [ 0.358805] e820: reserve RAM buffer [mem 0x86e800000-0x86fffffff] > [ 0.358865] NetLabel: Initializing > [ 0.358865] NetLabel: domain hash size = 128 > [ 0.358865] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO > [ 0.358874] NetLabel: unlabeled traffic allowed by default > [ 0.359255] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 > [ 0.359257] hpet0: 8 comparators, 64-bit 24.000000 MHz counter > [ 0.360784] clocksource: Switched to clocksource tsc-early > [ 0.366604] VFS: Disk quotas dquot_6.6.0 > [ 0.366614] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) > [ 0.366684] AppArmor: AppArmor Filesystem Enabled > [ 0.366692] pnp: PnP ACPI init > [ 0.366734] system 00:00: [io 0x0a00-0x0a0f] has been reserved > [ 0.366734] system 00:00: [io 0x0a10-0x0a1f] has been reserved > [ 0.366734] system 00:00: [io 0x0a20-0x0a2f] has been reserved > [ 0.366734] system 00:00: [io 0x0a30-0x0a3f] has been reserved > [ 0.366734] system 00:00: [io 0x0a40-0x0a4f] has been reserved > [ 0.366734] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.366734] pnp 00:01: [dma 0 disabled] > [ 0.366734] pnp 00:01: Plug and Play ACPI device, IDs PNP0501 (active) > [ 0.366734] pnp 00:02: [dma 0 disabled] > [ 0.366734] pnp 00:02: Plug and Play ACPI device, IDs PNP0501 (active) > [ 0.366734] system 00:03: [io 0x0680-0x069f] has been reserved > [ 0.366734] system 00:03: [io 0xffff] has been reserved > [ 0.366734] system 00:03: [io 0xffff] has been reserved > [ 0.366734] system 00:03: [io 0xffff] has been reserved > [ 0.366734] system 00:03: [io 0x1800-0x18fe] has been reserved > [ 0.366734] system 00:03: [io 0x164e-0x164f] has been reserved > [ 0.366734] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.366734] system 00:04: [io 0x0800-0x087f] has been reserved > [ 0.366734] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.366734] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active) > [ 0.366734] system 00:06: [io 0x1854-0x1857] has been reserved > [ 0.366734] system 00:06: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) > [ 0.367824] system 00:07: [mem 0xfed10000-0xfed17fff] has been reserved > [ 0.367825] system 00:07: [mem 0xfed18000-0xfed18fff] has been reserved > [ 0.367825] system 00:07: [mem 0xfed19000-0xfed19fff] has been reserved > [ 0.367826] system 00:07: [mem 0xe0000000-0xefffffff] has been reserved > [ 0.367827] system 00:07: [mem 0xfed20000-0xfed3ffff] has been reserved > [ 0.367828] system 00:07: [mem 0xfed90000-0xfed93fff] could not be reserved > [ 0.367829] system 00:07: [mem 0xfed45000-0xfed8ffff] has been reserved > [ 0.367829] system 00:07: [mem 0xff000000-0xffffffff] has been reserved > [ 0.367830] system 00:07: [mem 0xfee00000-0xfeefffff] could not be reserved > [ 0.367831] system 00:07: [mem 0xdffe0000-0xdfffffff] has been reserved > [ 0.367833] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.367862] system 00:08: [mem 0xfd000000-0xfdabffff] has been reserved > [ 0.367863] system 00:08: [mem 0xfdad0000-0xfdadffff] has been reserved > [ 0.367863] system 00:08: [mem 0xfdb00000-0xfdffffff] has been reserved > [ 0.367864] system 00:08: [mem 0xfe000000-0xfe01ffff] could not be reserved > [ 0.367865] system 00:08: [mem 0xfe036000-0xfe03bfff] has been reserved > [ 0.367867] system 00:08: [mem 0xfe03d000-0xfe3fffff] has been reserved > [ 0.367868] system 00:08: [mem 0xfe410000-0xfe7fffff] has been reserved > [ 0.367869] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.368081] system 00:09: [io 0xff00-0xfffe] has been reserved > [ 0.368082] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.368798] system 00:0a: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.369460] pnp: PnP ACPI: found 11 devices > [ 0.374670] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns > [ 0.374694] pci 0000:00:1b.0: PCI bridge to [bus 01] > [ 0.374701] pci 0000:00:1c.0: PCI bridge to [bus 02] > [ 0.374708] pci 0000:00:1d.0: PCI bridge to [bus 03] > [ 0.374713] pci 0000:00:1d.1: PCI bridge to [bus 04] > [ 0.374715] pci 0000:00:1d.1: bridge window [io 0xe000-0xefff] > [ 0.374717] pci 0000:00:1d.1: bridge window [mem 0xdf100000-0xdf1fffff] > [ 0.374722] pci 0000:05:00.0: PCI bridge to [bus 06] > [ 0.374724] pci 0000:05:00.0: bridge window [io 0xd000-0xdfff] > [ 0.374728] pci 0000:05:00.0: bridge window [mem 0xde000000-0xdf0fffff] > [ 0.374737] pci 0000:00:1d.2: PCI bridge to [bus 05-06] > [ 0.374738] pci 0000:00:1d.2: bridge window [io 0xd000-0xdfff] > [ 0.374740] pci 0000:00:1d.2: bridge window [mem 0xde000000-0xdf0fffff] > [ 0.374745] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] > [ 0.374746] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] > [ 0.374747] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] > [ 0.374748] pci_bus 0000:00: resource 7 [mem 0x8f800000-0xdfffffff window] > [ 0.374748] pci_bus 0000:00: resource 8 [mem 0xfd000000-0xfe7fffff window] > [ 0.374749] pci_bus 0000:04: resource 0 [io 0xe000-0xefff] > [ 0.374750] pci_bus 0000:04: resource 1 [mem 0xdf100000-0xdf1fffff] > [ 0.374751] pci_bus 0000:05: resource 0 [io 0xd000-0xdfff] > [ 0.374751] pci_bus 0000:05: resource 1 [mem 0xde000000-0xdf0fffff] > [ 0.374752] pci_bus 0000:06: resource 0 [io 0xd000-0xdfff] > [ 0.374753] pci_bus 0000:06: resource 1 [mem 0xde000000-0xdf0fffff] > [ 0.374852] NET: Registered protocol family 2 > [ 0.374928] tcp_listen_portaddr_hash hash table entries: 16384 (order: 6, 262144 bytes, linear) > [ 0.374952] TCP established hash table entries: 262144 (order: 9, 2097152 bytes, linear) > [ 0.375122] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear) > [ 0.375203] TCP: Hash tables configured (established 262144 bind 65536) > [ 0.375220] UDP hash table entries: 16384 (order: 7, 524288 bytes, linear) > [ 0.375263] UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes, linear) > [ 0.375339] NET: Registered protocol family 1 > [ 0.375342] NET: Registered protocol family 44 > [ 0.375348] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] > [ 0.375585] PCI: CLS 64 bytes, default 64 > [ 0.375607] Trying to unpack rootfs image as initramfs... > [ 0.874166] Freeing initrd memory: 43536K > [ 0.874200] DMAR: ACPI device "device:7d" under DMAR at fed91000 as 00:15.0 > [ 0.874202] DMAR: ACPI device "device:7e" under DMAR at fed91000 as 00:15.1 > [ 0.874203] DMAR: ACPI device "device:7f" under DMAR at fed91000 as 00:1e.0 > [ 0.874213] DMAR: No ATSR found > [ 0.874244] DMAR: dmar0: Using Queued invalidation > [ 0.874246] DMAR: dmar1: Using Queued invalidation > [ 0.874571] pci 0000:00:00.0: Adding to iommu group 0 > [ 0.877343] pci 0000:00:02.0: Adding to iommu group 1 > [ 0.877492] pci 0000:00:02.0: Using iommu direct mapping > [ 0.877518] pci 0000:00:08.0: Adding to iommu group 2 > [ 0.877571] pci 0000:00:14.0: Adding to iommu group 3 > [ 0.877578] pci 0000:00:14.2: Adding to iommu group 3 > [ 0.877616] pci 0000:00:15.0: Adding to iommu group 4 > [ 0.877623] pci 0000:00:15.1: Adding to iommu group 4 > [ 0.877665] pci 0000:00:16.0: Adding to iommu group 5 > [ 0.877672] pci 0000:00:16.3: Adding to iommu group 5 > [ 0.877704] pci 0000:00:17.0: Adding to iommu group 6 > [ 0.877741] pci 0000:00:1b.0: Adding to iommu group 7 > [ 0.877779] pci 0000:00:1c.0: Adding to iommu group 8 > [ 0.877816] pci 0000:00:1d.0: Adding to iommu group 9 > [ 0.877853] pci 0000:00:1d.1: Adding to iommu group 10 > [ 0.877887] pci 0000:00:1d.2: Adding to iommu group 11 > [ 0.877927] pci 0000:00:1e.0: Adding to iommu group 12 > [ 0.879057] pci 0000:00:1f.0: Adding to iommu group 13 > [ 0.879065] pci 0000:00:1f.2: Adding to iommu group 13 > [ 0.879073] pci 0000:00:1f.3: Adding to iommu group 13 > [ 0.879081] pci 0000:00:1f.4: Adding to iommu group 13 > [ 0.879118] pci 0000:00:1f.6: Adding to iommu group 14 > [ 0.879155] pci 0000:04:00.0: Adding to iommu group 15 > [ 0.879197] pci 0000:05:00.0: Adding to iommu group 16 > [ 0.879201] pci 0000:06:00.0: Adding to iommu group 16 > [ 0.879322] DMAR: Intel(R) Virtualization Technology for Directed I/O > [ 0.881046] Initialise system trusted keyrings > [ 0.881052] Key type blacklist registered > [ 0.881068] workingset: timestamp_bits=40 max_order=23 bucket_order=0 > [ 0.881844] zbud: loaded > [ 0.881949] Platform Keyring initialized > [ 0.881950] Key type asymmetric registered > [ 0.881951] Asymmetric key parser 'x509' registered > [ 0.881955] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251) > [ 0.881977] io scheduler mq-deadline registered > [ 0.882205] pcieport 0000:00:1b.0: PME: Signaling with IRQ 122 > [ 0.882240] pcieport 0000:00:1b.0: AER: enabled with IRQ 122 > [ 0.882395] pcieport 0000:00:1c.0: PME: Signaling with IRQ 123 > [ 0.882423] pcieport 0000:00:1c.0: AER: enabled with IRQ 123 > [ 0.882556] pcieport 0000:00:1d.0: PME: Signaling with IRQ 124 > [ 0.882685] pcieport 0000:00:1d.1: PME: Signaling with IRQ 125 > [ 0.882713] pcieport 0000:00:1d.1: AER: enabled with IRQ 125 > [ 0.882842] pcieport 0000:00:1d.2: PME: Signaling with IRQ 126 > [ 0.882869] pcieport 0000:00:1d.2: AER: enabled with IRQ 126 > [ 0.882938] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 > [ 0.882948] intel_idle: MWAIT substates: 0x142120 > [ 0.882949] intel_idle: v0.4.1 model 0x5E > [ 0.883190] intel_idle: lapic_timer_reliable_states 0xffffffff > [ 0.884073] thermal LNXTHERM:00: registered as thermal_zone0 > [ 0.884073] ACPI: Thermal Zone [TZ00] (28 C) > [ 0.884156] thermal LNXTHERM:01: registered as thermal_zone1 > [ 0.884156] ACPI: Thermal Zone [TZ01] (30 C) > [ 0.884204] ERST: Error Record Serialization Table (ERST) support is initialized. > [ 0.884205] pstore: Registered erst as persistent store backend > [ 0.884247] GHES: APEI firmware first mode is enabled by APEI bit. > [ 0.884315] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled > [ 0.884597] 00:01: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A > [ 0.885709] 00:02: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A > [ 0.887065] 0000:00:16.3: ttyS2 at I/O 0xf0a0 (irq = 19, base_baud = 115200) is a 16550A > [ 0.887264] Linux agpgart interface v0.103 > [ 0.887304] AMD-Vi: AMD IOMMUv2 driver by Joerg Roedel <jroedel at suse.de> > [ 0.887304] AMD-Vi: AMD IOMMUv2 functionality not available on this system > [ 0.887717] i8042: PNP: No PS/2 controller found. > [ 0.887745] mousedev: PS/2 mouse device common for all mice > [ 0.887775] rtc_cmos 00:05: RTC can wake from S4 > [ 0.888255] rtc_cmos 00:05: registered as rtc0 > [ 0.888264] rtc_cmos 00:05: alarms up to one month, y3k, 242 bytes nvram, hpet irqs > [ 0.888268] intel_pstate: Intel P-state driver initializing > [ 0.888916] intel_pstate: HWP enabled > [ 0.889037] ledtrig-cpu: registered to indicate activity on CPUs > [ 0.889161] drop_monitor: Initializing network drop monitor service > [ 0.889300] NET: Registered protocol family 10 > [ 0.896122] Segment Routing with IPv6 > [ 0.896134] mip6: Mobile IPv6 > [ 0.896134] NET: Registered protocol family 17 > [ 0.896240] mpls_gso: MPLS GSO support > [ 0.896919] microcode: sig=0x506e3, pf=0x2, revision=0xd6 > [ 0.897087] microcode: Microcode Update Driver: v2.2. > [ 0.897089] IPI shorthand broadcast: enabled > [ 0.897107] sched_clock: Marking stable (894292599, 2568221)->(990520866, -93660046) > [ 0.897298] registered taskstats version 1 > [ 0.897299] Loading compiled-in X.509 certificates > [ 0.918917] Loaded X.509 cert 'Debian Secure Boot CA: 6ccece7e4c6c0d1f6149f3dd27dfcc5cbb419ea1' > [ 0.918927] Loaded X.509 cert 'Debian Secure Boot Signer: 00a7468def' > [ 0.918939] zswap: loaded using pool lzo/zbud > [ 0.919345] Key type ._fscrypt registered > [ 0.919345] Key type .fscrypt registered > [ 0.919346] Key type fscrypt-provisioning registered > [ 0.919383] pstore: Using crash dump compression: deflate > [ 0.919391] AppArmor: AppArmor sha1 policy hashing enabled > [ 0.920358] rtc_cmos 00:05: setting system clock to 2020-06-04T10:00:46 UTC (1591264846) > [ 0.921101] Freeing unused kernel image (initmem) memory: 1612K > [ 0.996075] Write protecting the kernel read-only data: 16384k > [ 0.997114] Freeing unused kernel image (text/rodata gap) memory: 2044K > [ 0.997307] Freeing unused kernel image (rodata/data gap) memory: 120K > [ 1.056373] x86/mm: Checked W+X mappings: passed, no W+X pages found. > [ 1.056373] x86/mm: Checking user space page tables > [ 1.083217] x86/mm: Checked W+X mappings: passed, no W+X pages found. > [ 1.083218] Run /init as init process > [ 1.083218] with arguments: > [ 1.083219] /init > [ 1.083219] with environment: > [ 1.083219] HOME=/ > [ 1.083220] TERM=linux > [ 1.083220] BOOT_IMAGE=/boot/vmlinuz-5.6.0-2-amd64 > [ 1.139558] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input0 > [ 1.139580] ACPI: Sleep Button [SLPB] > [ 1.139624] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 > [ 1.139637] ACPI: Power Button [PWRB] > [ 1.139662] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 > [ 1.139689] ACPI: Power Button [PWRF] > [ 1.151483] pps_core: LinuxPPS API ver. 1 registered > [ 1.151484] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti at linux.it> > [ 1.152700] PTP clock support registered > [ 1.153198] dca service started, version 1.12.1 > [ 1.158304] i801_smbus 0000:00:1f.4: SPD Write Disable is set > [ 1.158344] i801_smbus 0000:00:1f.4: SMBus using PCI interrupt > [ 1.158466] intel-lpss 0000:00:15.0: enabling device (0000 -> 0002) > [ 1.158710] idma64 idma64.0: Found Intel integrated DMA 64-bit > [ 1.161029] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.6.0-k > [ 1.161029] igb: Copyright (c) 2007-2014 Intel Corporation. > [ 1.164440] ACPI: bus type USB registered > [ 1.164455] usbcore: registered new interface driver usbfs > [ 1.164462] usbcore: registered new interface driver hub > [ 1.164488] usbcore: registered new device driver usb > [ 1.168522] intel-lpss 0000:00:15.1: enabling device (0000 -> 0002) > [ 1.168762] idma64 idma64.1: Found Intel integrated DMA 64-bit > [ 1.173453] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k > [ 1.173454] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. > [ 1.174603] intel-lpss 0000:00:1e.0: enabling device (0000 -> 0002) > [ 1.174626] e1000e 0000:00:1f.6: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode > [ 1.174879] idma64 idma64.2: Found Intel integrated DMA 64-bit > [ 1.175017] SCSI subsystem initialized > [ 1.175935] dw-apb-uart.2: ttyS3 at MMIO 0xdf24b000 (irq = 20, base_baud = 115200) is a 16550A > [ 1.185340] xhci_hcd 0000:00:14.0: xHCI Host Controller > [ 1.185347] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1 > [ 1.186451] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x0000000001109810 > [ 1.187465] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported > [ 1.187661] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.06 > [ 1.187663] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 > [ 1.187664] usb usb1: Product: xHCI Host Controller > [ 1.187665] usb usb1: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd > [ 1.187666] usb usb1: SerialNumber: 0000:00:14.0 > [ 1.187773] hub 1-0:1.0: USB hub found > [ 1.187790] hub 1-0:1.0: 16 ports detected > [ 1.187842] libata version 3.00 loaded. > [ 1.191212] ahci 0000:00:17.0: version 3.0 > [ 1.192724] ast 0000:06:00.0: enabling device (0140 -> 0143) > [ 1.199510] pps pps0: new PPS source ptp0 > [ 1.199542] igb 0000:04:00.0: added PHC on eth0 > [ 1.199543] igb 0000:04:00.0: Intel(R) Gigabit Ethernet Network Connection > [ 1.199545] igb 0000:04:00.0: eth0: (PCIe:2.5Gb/s:Width x1) 0c:c4:7a:cf:6c:d7 > [ 1.199618] igb 0000:04:00.0: eth0: PBA No: 010B00-000 > [ 1.199619] igb 0000:04:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s) > [ 1.200298] igb 0000:04:00.0 eno2: renamed from eth0 > [ 1.209686] [drm] Using P2A bridge for configuration > [ 1.209701] [drm] AST 2400 detected > [ 1.209713] [drm] Analog VGA only > [ 1.209731] [drm] dram MCLK=408 Mhz type=1 bus_width=16 size=01000000 > [ 1.209763] [TTM] Zone kernel: Available graphics memory: 16423934 KiB > [ 1.209765] ahci 0000:00:17.0: AHCI 0001.0301 32 slots 4 ports 6 Gbps 0xf impl SATA mode > [ 1.209765] [TTM] Zone dma32: Available graphics memory: 2097152 KiB > [ 1.209766] ahci 0000:00:17.0: flags: 64bit ncq sntf led clo only pio slum part ems deso sadm sds apst > [ 1.209767] [TTM] Initializing pool allocator > [ 1.209775] [TTM] Initializing DMA pool allocator > [ 1.210535] [drm:drm_client_modeset_probe [drm]] > [ 1.210544] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] > [ 1.210551] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] status updated from unknown to connected > [ 1.214089] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter AST i2c bit bus > [ 1.214125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "848x480": 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5 > [ 1.214137] [drm:drm_mode_prune_invalid [drm]] Not using 848x480 mode: NOMODE > [ 1.214145] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] probed modes : > [ 1.214158] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 1.214170] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 1.214182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 > [ 1.214195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.214209] [drm:drm_client_modeset_probe [drm]] connector 35 enabled? yes > [ 1.214223] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 1.214236] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 35 > [ 1.214248] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 35 0 > [ 1.214261] [drm:drm_client_modeset_probe [drm]] found mode 1024x768 > [ 1.214273] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 1920x2048 config > [ 1.214286] [drm:drm_client_modeset_probe [drm]] desired mode 1024x768 set on crtc 33 (0,0) > [ 1.214294] ast 0000:06:00.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane > [ 1.214302] ast 0000:06:00.0: [drm:drm_fb_helper_generic_probe [drm_kms_helper]] surface width(1024), height(768) and bpp(32) > [ 1.214322] [drm:drm_mode_addfb2 [drm]] [FB:36] > [ 1.216083] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 > [ 1.216098] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000706e661a state to 00000000d3c00277 > [ 1.216111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000b376c70b state to 00000000d3c00277 > [ 1.216125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000b376c70b > [ 1.216139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 > [ 1.216153] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1024x768] for [CRTC:33:crtc-0] state 000000000505a613 > [ 1.216166] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane-0] state 00000000706e661a to [CRTC:33:crtc-0] > [ 1.216179] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000706e661a > [ 1.216192] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.216205] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000007c015743 state to 00000000d3c00277 > [ 1.216219] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000007c015743 to [CRTC:33:crtc-0] > [ 1.216231] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 > [ 1.216240] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] mode changed > [ 1.216246] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] enable changed > [ 1.216252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] active changed > [ 1.216258] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 1.216265] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] using [ENCODER:34:DAC-34] on [CRTC:33:crtc-0] > [ 1.216271] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] needs all connectors, enable: y, active: y > [ 1.216284] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.216296] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.216310] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 > [ 1.317254] [drm:drm_atomic_helper_commit_modeset_disables [drm_kms_helper]] modeset on [ENCODER:34:DAC-34] > [ 1.317708] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [CRTC:33:crtc-0] > [ 1.321530] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [ENCODER:34:DAC-34] > [ 1.321546] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 > [ 1.321559] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 > [ 1.321591] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 > [ 1.321604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000009f032e5a state to 00000000d3c00277 > [ 1.321616] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000005efad0e6 state to 00000000d3c00277 > [ 1.321629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000033f48d87 state to 00000000d3c00277 > [ 1.321642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000033f48d87 > [ 1.321656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000009f032e5a > [ 1.321669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.321682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000004014674f state to 00000000d3c00277 > [ 1.321695] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [NOCRTC] > [ 1.321708] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [CRTC:33:crtc-0] > [ 1.321720] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 > [ 1.321728] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 1.321734] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 1.321747] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 > [ 1.321805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 > [ 1.321818] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 > [ 1.324095] e1000e 0000:00:1f.6 0000:00:1f.6 (uninitialized): registered PHC clock > [ 1.324820] Console: switching to colour frame buffer device 128x48 > [ 1.341554] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 > [ 1.341567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000f7eff311 state to 00000000d3c00277 > [ 1.341579] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 > [ 1.341591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000d2da0efa state to 00000000d3c00277 > [ 1.341605] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000d2da0efa > [ 1.341619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000f7eff311 > [ 1.341631] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.341644] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000cebac407 state to 00000000d3c00277 > [ 1.341657] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [NOCRTC] > [ 1.341670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [CRTC:33:crtc-0] > [ 1.341682] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 > [ 1.341690] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 1.341696] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 1.341709] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 > [ 1.341749] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 > [ 1.341761] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 > [ 1.344652] ast 0000:06:00.0: fb0: astdrmfb frame buffer device > [ 1.366247] xhci_hcd 0000:00:14.0: xHCI Host Controller > [ 1.366250] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 > [ 1.366253] xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed > [ 1.366292] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.06 > [ 1.366293] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 > [ 1.366294] usb usb2: Product: xHCI Host Controller > [ 1.366295] usb usb2: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd > [ 1.366296] usb usb2: SerialNumber: 0000:00:14.0 > [ 1.366371] scsi host0: ahci > [ 1.366512] hub 2-0:1.0: USB hub found > [ 1.366540] hub 2-0:1.0: 10 ports detected > [ 1.366542] scsi host1: ahci > [ 1.366632] scsi host2: ahci > [ 1.366704] scsi host3: ahci > [ 1.366744] ata1: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c100 irq 134 > [ 1.366746] ata2: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c180 irq 134 > [ 1.366747] ata3: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c200 irq 134 > [ 1.366748] ata4: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c280 irq 134 > [ 1.367439] usb: port power management may be unreliable > [ 1.390078] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 1024K > [ 1.390116] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]] enable_guc=0 (guc:no submission:no huc:no) > [ 1.390147] [drm:i915_gem_init_early [i915]] fake context support initialized > [ 1.390174] i915 0000:00:02.0: [drm:intel_pch_type [i915]] Found SunrisePoint PCH > [ 1.390207] [drm:intel_power_domains_init [i915]] Allowed DC state mask 02 > [ 1.390244] i915 0000:00:02.0: [drm:intel_uncore_init_mmio [i915]] unclaimed mmio detected on uncore init, clearing > [ 1.390619] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M > [ 1.390645] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M > [ 1.390669] [drm:i915_ggtt_probe_hw [i915]] DSM size = 32M > [ 1.390670] i915 0000:00:02.0: VT-d active for gfx access > [ 1.390671] i915 0000:00:02.0: vgaarb: deactivate vga console > [ 1.390754] [drm:init_stolen [i915]] GEN6_STOLEN_RESERVED = 8f700047 > [ 1.390788] [drm:init_stolen [i915]] Memory reserved for graphics device: 32768K, usable: 31744K > [ 1.390818] [drm:intel_gt_init_workarounds [i915]] Initialized 4 GT workarounds on global > [ 1.390868] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params > [ 1.390899] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8b82a018 > [ 1.390933] [drm:intel_opregion_setup [i915]] ACPI OpRegion version 2.0.0 > [ 1.390962] [drm:intel_opregion_setup [i915]] Public ACPI methods supported > [ 1.390989] [drm:intel_opregion_setup [i915]] SWSCI supported > [ 1.392097] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483 > [ 1.392125] [drm:intel_opregion_setup [i915]] ASLE supported > [ 1.392152] [drm:intel_opregion_setup [i915]] ASLE extension supported > [ 1.392179] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4) > [ 1.392203] [drm:i915_driver_probe [i915]] DRAM type: DDR4 > [ 1.392227] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no > [ 1.392249] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no > [ 1.392271] [drm:skl_dram_get_channel_info [i915]] CH0 ranks: 2, 16Gb DIMMs: no > [ 1.392292] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no > [ 1.392313] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no > [ 1.392332] [drm:skl_dram_get_channel_info [i915]] CH1 ranks: 2, 16Gb DIMMs: no > [ 1.392352] [drm:i915_driver_probe [i915]] Memory configuration is symmetric? yes > [ 1.392371] [drm:i915_driver_probe [i915]] DRAM bandwidth: 34133344 kBps, channels: 2 > [ 1.392391] [drm:i915_driver_probe [i915]] DRAM ranks: 2, 16Gb DIMMs: no > [ 1.392391] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [ 1.392392] [drm] Driver supports precise vblank timestamp query. > [ 1.392424] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz > [ 1.392456] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE ", BDB version 205 > [ 1.392487] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 > [ 1.392517] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 > [ 1.392547] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68d6 > [ 1.392575] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 > [ 1.392604] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 > [ 1.392632] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68c6 > [ 1.392985] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0) > [ 1.393028] [drm:intel_bios_init [i915]] Panel type: 2 (VBT) > [ 1.393056] [drm:intel_bios_init [i915]] DRRS supported mode is static > [ 1.393085] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT legacy lfp table: > [ 1.393098] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa > [ 1.393126] [drm:intel_bios_init [i915]] VBT initial LVDS value 300 > [ 1.393154] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0 > [ 1.393181] [drm:intel_bios_init [i915]] DRRS State Enabled:1 > [ 1.393209] [drm:intel_bios_init [i915]] Skipping SDVO device mapping > [ 1.393237] [drm:intel_bios_init [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393264] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8 > [ 1.393292] [drm:intel_bios_init [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393318] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8 > [ 1.393346] [drm:intel_bios_init [i915]] Port D VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393373] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8 > [ 1.393400] [drm:intel_bios_init [i915]] Port E VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393427] [drm:intel_bios_init [i915]] VBT HDMI level shift for port E: 0 > [ 1.393534] [drm:intel_dsm_detect [i915]] no _DSM method for intel device > [ 1.393577] [drm:intel_power_domains_init_hw [i915]] rawclk rate: 24000 kHz > [ 1.393610] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 > [ 1.393643] [drm:intel_power_well_enable [i915]] enabling power well 1 > [ 1.393675] [drm:intel_power_well_enable [i915]] enabling MISC IO power well > [ 1.393708] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 > [ 1.393740] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz > [ 1.393770] [drm:intel_cdclk_init [i915]] Max dotclock rate: 675000 kHz > [ 1.393813] [drm:intel_power_well_enable [i915]] enabling always-on > [ 1.393843] [drm:intel_power_well_enable [i915]] enabling DC off > [ 1.393873] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 > [ 1.393906] [drm:intel_power_well_enable [i915]] enabling power well 2 > [ 1.393909] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=io+mem > [ 1.393964] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well > [ 1.394014] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well > [ 1.394042] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well > [ 1.394069] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well > [ 1.394113] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_27.bin > [ 1.394155] i915 0000:00:02.0: firmware: direct-loading firmware i915/skl_dmc_ver1_27.bin > [ 1.394459] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_27.bin (v1.27) > [ 1.394625] [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled > [ 1.394695] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 > [ 1.394722] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec) > [ 1.394745] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec) > [ 1.394767] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec) > [ 1.394788] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec) > [ 1.394808] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec) > [ 1.394828] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec) > [ 1.394848] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec) > [ 1.394867] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec) > [ 1.394988] [drm:intel_modeset_init [i915]] 3 display pipes available. > [ 1.395056] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 > [ 1.395385] [drm:intel_modeset_init [i915]] VBT says port A is not DVI/HDMI/DP compatible, respect it > [ 1.395421] [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (VBT) > [ 1.395451] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:94:DDI B] > [ 1.395488] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:94:DDI B] > [ 1.395516] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT) > [ 1.395550] [drm:intel_bios_port_aux_ch [i915]] using AUX C for port C (VBT) > [ 1.395578] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:109:DDI C] > [ 1.395609] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:109:DDI C] > [ 1.395636] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT) > [ 1.395669] [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT) > [ 1.395697] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:119:DDI D] > [ 1.395727] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:119:DDI D] > [ 1.395754] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT) > [ 1.395816] [drm:intel_bios_port_aux_ch [i915]] using AUX A for port E (VBT) > [ 1.395862] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:129:DDI E] > [ 1.395917] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:51:pipe A] hw state readout: enabled > [ 1.395960] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:72:pipe B] hw state readout: disabled > [ 1.396018] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:93:pipe C] hw state readout: disabled > [ 1.396064] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] hw state readout: disabled, pipe A > [ 1.396065] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 0c:c4:7a:cf:6c:d6 > [ 1.396066] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection > [ 1.396107] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] hw state readout: disabled, pipe A > [ 1.396162] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] hw state readout: disabled, pipe A > [ 1.396213] e1000e 0000:00:1f.6 eth0: MAC: 12, PHY: 12, PBA No: 010BFF-0FF > [ 1.396274] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] hw state readout: disabled, pipe B > [ 1.396309] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] hw state readout: disabled, pipe B > [ 1.396355] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] hw state readout: disabled, pipe B > [ 1.396437] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] hw state readout: disabled, pipe C > [ 1.396511] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] hw state readout: disabled, pipe C > [ 1.396559] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] hw state readout: disabled, pipe C > [ 1.396597] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1 > [ 1.396641] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000001, on 1 > [ 1.396695] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0 > [ 1.396736] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0 > [ 1.396777] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:94:DDI B] hw state readout: disabled, pipe A > [ 1.396820] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:96:DP-MST A] hw state readout: disabled, pipe A > [ 1.396861] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:97:DP-MST B] hw state readout: disabled, pipe B > [ 1.396907] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:98:DP-MST C] hw state readout: disabled, pipe C > [ 1.396908] e1000e 0000:00:1f.6 eno1: renamed from eth0 > [ 1.396988] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:109:DDI C] hw state readout: enabled, pipe A > [ 1.397033] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:111:DP-MST A] hw state readout: disabled, pipe A > [ 1.397083] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:112:DP-MST B] hw state readout: disabled, pipe B > [ 1.397134] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:113:DP-MST C] hw state readout: disabled, pipe C > [ 1.397184] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:119:DDI D] hw state readout: disabled, pipe A > [ 1.397234] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:121:DP-MST A] hw state readout: disabled, pipe A > [ 1.397284] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:122:DP-MST B] hw state readout: disabled, pipe B > [ 1.397333] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:123:DP-MST C] hw state readout: disabled, pipe C > [ 1.397383] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:129:DDI E] hw state readout: disabled, pipe A > [ 1.397433] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:95:DP-1] hw state readout: disabled > [ 1.397484] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:104:HDMI-A-1] hw state readout: disabled > [ 1.397536] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:110:DP-2] hw state readout: enabled > [ 1.397588] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:116:HDMI-A-2] hw state readout: disabled > [ 1.397638] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:120:DP-3] hw state readout: disabled > [ 1.397688] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:126:HDMI-A-3] hw state readout: disabled > [ 1.397737] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:130:DP-4] hw state readout: disabled > [ 1.397764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 0000000016992e5d > [ 1.397814] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] min_cdclk 0 kHz > [ 1.397864] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] min_cdclk 0 kHz > [ 1.397913] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] min_cdclk 0 kHz > [ 1.397964] [drm:intel_modeset_setup_hw_state [i915]] pipe A data rate 0 num active planes 0 > [ 1.398014] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] min_cdclk 0 kHz > [ 1.398063] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] min_cdclk 0 kHz > [ 1.398112] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] min_cdclk 0 kHz > [ 1.398161] [drm:intel_modeset_setup_hw_state [i915]] pipe B data rate 0 num active planes 0 > [ 1.398211] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] min_cdclk 0 kHz > [ 1.398259] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] min_cdclk 0 kHz > [ 1.398308] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] min_cdclk 0 kHz > [ 1.398357] [drm:intel_modeset_setup_hw_state [i915]] pipe C data rate 0 num active planes 0 > [ 1.398413] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [setup_hw_state] > [ 1.398465] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB > [ 1.398516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 > [ 1.398568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 517734, link_n: 524288, tu: 64 > [ 1.398618] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0 > [ 1.398667] [drm:intel_dump_pipe_config [i915]] requested mode: > [ 1.398685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 720 3902 3950 4000 400 2163 2168 2222 0x40 0x9 > [ 1.398735] [drm:intel_dump_pipe_config [i915]] adjusted mode: > [ 1.398752] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 3840 3902 3950 4000 2160 2163 2168 2222 0x40 0x9 > [ 1.398803] [drm:intel_dump_pipe_config [i915]] crtc timings: 533249 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x40 flags: 0x9 > [ 1.398853] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 720x400, pixel rate 533249 > [ 1.398903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 > [ 1.398952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0f000870, enabled, force thru: no > [ 1.399001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 > [ 1.399051] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 > [ 1.399100] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > [ 1.399149] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> > [ 1.399199] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: no [setup_hw_state] > [ 1.399248] [drm:intel_dump_pipe_config [i915]] [CRTC:93:pipe C] enable: no [setup_hw_state] > [ 1.399299] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling > [ 1.399340] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff7e1cca > [ 1.399359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000197e100e state to 00000000ff7e1cca > [ 1.399376] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000ff7e1cca > [ 1.399393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000aef36d99 state to 00000000ff7e1cca > [ 1.399410] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000069886caf state to 00000000ff7e1cca > [ 1.399426] [drm:drm_atomic_check_only [drm]] checking 00000000ff7e1cca > [ 1.399485] [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:51 > [ 1.399504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002ca0145a state to 00000000ff7e1cca > [ 1.399520] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a93965e7 state to 00000000ff7e1cca > [ 1.399536] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008fa1e3fc state to 00000000ff7e1cca > [ 1.399552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae2843ea state to 00000000ff7e1cca > [ 1.399567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000afe69d21 state to 00000000ff7e1cca > [ 1.399582] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a4be912 state to 00000000ff7e1cca > [ 1.399597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002017bf88 state to 00000000ff7e1cca > [ 1.399612] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000977f527e state to 00000000ff7e1cca > [ 1.399627] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000059814b3a state to 00000000ff7e1cca > [ 1.399679] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 > [ 1.399727] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.399773] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.399867] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.399911] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.399954] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.399997] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400039] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400082] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400123] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400165] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400206] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400247] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400288] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400329] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400370] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400411] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400451] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400492] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400533] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400573] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400613] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400654] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400735] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400775] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400816] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400857] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400897] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400936] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400977] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401017] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401057] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401096] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.401137] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401177] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401217] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401236] [drm:drm_atomic_commit [drm]] committing 00000000ff7e1cca > [ 1.403979] [drm] Initialized ast 0.1.0 20120228 for 0000:06:00.0 on minor 0 > [ 1.417469] [drm:i915_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000] > [ 1.419056] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff7e1cca > [ 1.419076] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff7e1cca > [ 1.419161] [drm:intel_engine_init_workarounds [i915]] Initialized 5 engine workarounds on rcs'0 > [ 1.419213] [drm:intel_engine_init_whitelist [i915]] Initialized 5 whitelist workarounds on rcs'0 > [ 1.419264] [drm:intel_engine_init_ctx_wa [i915]] Initialized 12 context workarounds on rcs'0 > [ 1.420147] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping > [ 1.420202] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping > [ 1.420253] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping > [ 1.420305] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config > [ 1.420418] [drm:intel_engines_driver_register [i915]] renamed rcs'0 to rcs0 > [ 1.420466] [drm:intel_engines_driver_register [i915]] renamed bcs'0 to bcs0 > [ 1.420513] [drm:intel_engines_driver_register [i915]] renamed vcs'0 to vcs0 > [ 1.420558] [drm:intel_engines_driver_register [i915]] renamed vecs'0 to vecs0 > [ 1.421101] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card1-DP-1 > [ 1.421269] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card1-DP-2 > [ 1.421470] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card1-DP-3 > [ 1.421665] [drm:intel_dp_connector_register [i915]] registering DPDDC-E bus for card1-DP-4 > [ 1.421746] [drm] Initialized i915 1.6.0 20200114 for 0000:00:02.0 on minor 1 > [ 1.421881] [drm:intel_opregion_resume [i915]] 7 outputs detected > [ 1.424122] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) > [ 1.424463] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3 > [ 1.424632] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well > [ 1.424650] [drm:drm_client_modeset_probe [drm]] > [ 1.424733] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well > [ 1.424743] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 1.424798] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 1.424851] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well > [ 1.424855] i915 device info: pciid=0x191d rev=0x06 platform=SKYLAKE (subplatform=0x0) gen=9 > [ 1.424857] i915 device info: engines: 47 > [ 1.424857] i915 device info: gen: 9 > [ 1.424858] i915 device info: gt: 2 > [ 1.424859] i915 device info: iommu: enabled > [ 1.424860] i915 device info: memory-regions: 5 > [ 1.424861] i915 device info: page-sizes: 11000 > [ 1.424861] i915 device info: platform: SKYLAKE > [ 1.424869] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] status updated from unknown to disconnected > [ 1.424869] i915 device info: ppgtt-size: 48 > [ 1.424870] i915 device info: ppgtt-type: 2 > [ 1.424871] i915 device info: is_mobile: no > [ 1.424872] i915 device info: is_lp: no > [ 1.424873] i915 device info: require_force_probe: no > [ 1.424879] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 1.424880] i915 device info: is_dgfx: no > [ 1.424900] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 1.424901] i915 device info: has_64bit_reloc: yes > [ 1.424902] i915 device info: gpu_reset_clobbers_display: no > [ 1.424903] i915 device info: has_reset_engine: yes > [ 1.424904] i915 device info: has_fpga_dbg: yes > [ 1.424905] i915 device info: has_global_mocs: no > [ 1.424919] i915 device info: has_gt_uc: yes > [ 1.424920] i915 device info: has_l3_dpf: no > [ 1.424921] i915 device info: has_llc: yes > [ 1.424922] i915 device info: has_logical_ring_contexts: yes > [ 1.424923] i915 device info: has_logical_ring_elsq: no > [ 1.424959] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 1.424960] i915 device info: has_logical_ring_preemption: yes > [ 1.424961] i915 device info: has_pooled_eu: no > [ 1.424962] i915 device info: has_rc6: yes > [ 1.424963] i915 device info: has_rc6p: no > [ 1.424963] i915 device info: has_rps: yes > [ 1.424964] i915 device info: has_runtime_pm: yes > [ 1.424965] i915 device info: has_snoop: no > [ 1.424966] i915 device info: has_coherent_ggtt: yes > [ 1.424967] i915 device info: unfenced_needs_alignment: no > [ 1.424968] i915 device info: hws_needs_physical: no > [ 1.424969] i915 device info: cursor_needs_physical: no > [ 1.424970] i915 device info: has_csr: yes > [ 1.424970] i915 device info: has_ddi: yes > [ 1.424971] i915 device info: has_dp_mst: yes > [ 1.424972] i915 device info: has_dsb: no > [ 1.424973] i915 device info: has_dsc: no > [ 1.424974] i915 device info: has_fbc: no > [ 1.424974] i915 device info: has_gmch: no > [ 1.424975] i915 device info: has_hdcp: yes > [ 1.424976] i915 device info: has_hotplug: yes > [ 1.424977] i915 device info: has_ipc: yes > [ 1.424978] i915 device info: has_modular_fia: no > [ 1.424979] i915 device info: has_overlay: no > [ 1.424980] i915 device info: has_psr: yes > [ 1.424981] i915 device info: overlay_needs_physical: no > [ 1.424981] i915 device info: supports_tv: no > [ 1.424982] i915 device info: slice total: 1, mask=0001 > [ 1.424983] i915 device info: subslice total: 3 > [ 1.424985] i915 device info: slice0: 3 subslices, mask=00000007 > [ 1.424986] i915 device info: slice1: 0 subslices, mask=00000000 > [ 1.424987] i915 device info: slice2: 0 subslices, mask=00000000 > [ 1.424987] i915 device info: EU total: 24 > [ 1.424988] i915 device info: EU per subslice: 8 > [ 1.424989] i915 device info: has slice power gating: no > [ 1.424990] i915 device info: has subslice power gating: no > [ 1.424991] i915 device info: has EU power gating: yes > [ 1.424992] i915 device info: CS timestamp frequency: 12000 kHz > [ 1.425215] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 1.425265] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 1.425502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 1.425525] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 1.425552] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 1.425579] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 1.428627] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 1.428673] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 1.428929] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 1.428956] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 1.429243] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 1.429262] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 1.429267] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] status updated from unknown to disconnected > [ 1.429271] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 1.429275] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 1.429304] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 1.429716] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 1.430070] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 1.431595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 1.431624] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 1.431652] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 1.431941] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 1.437548] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 1.438071] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] status updated from unknown to connected > [ 1.438083] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.438095] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 1.438105] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 1.438114] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.438303] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.438311] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.438318] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.438325] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.438333] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438339] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438346] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438353] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438360] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438366] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438373] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438379] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438387] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 1.438394] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.438401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 1.438408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 1.438414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 1.438421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 1.438428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.438434] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.438441] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.438448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.438454] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 1.438461] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 1.438468] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.438475] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.438481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 1.438488] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 1.438495] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.438501] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.438508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 1.438515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.438521] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.438528] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.438535] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 1.438541] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 1.438548] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 1.438555] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 1.438562] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 1.438568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.438575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.438582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438588] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438595] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438602] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 1.438615] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.438621] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.438628] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.438635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 1.438639] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 1.438670] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 1.438979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 1.439008] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 1.439309] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 1.439332] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 1.439360] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 1.439388] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 1.442034] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 1.442060] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 1.442363] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 1.442389] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 1.442674] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 1.442693] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 1.442697] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] status updated from unknown to disconnected > [ 1.442701] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 1.442704] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 1.442731] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 1.443143] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 1.443498] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 1.445026] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 1.445055] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 1.445083] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 1.445371] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 1.450984] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 1.451505] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] status updated from unknown to connected > [ 1.451514] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.451523] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 1.451530] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 1.451537] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.451717] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.451724] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.451732] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.451738] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.451746] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451752] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451760] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451772] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451779] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451785] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451792] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451798] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451806] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 1.451813] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.451832] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 1.451839] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 1.451845] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 1.451851] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 1.451858] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.451864] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.451870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.451877] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.451883] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 1.451890] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 1.451896] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.451902] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.451909] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 1.451915] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 1.451921] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.451928] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.451934] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 1.451940] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.451947] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.451953] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.451959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 1.451966] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 1.451972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 1.451978] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 1.451985] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 1.451991] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.451997] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.452004] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452010] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452016] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452023] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452029] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 1.452035] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.452042] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.452048] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.452054] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 1.452058] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 1.452153] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 1.452459] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 1.452487] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 1.452774] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 1.452796] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 1.452823] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 1.452849] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 1.455460] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 1.455486] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 1.455821] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 1.455849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 1.456135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 1.456153] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 1.456158] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] status updated from unknown to disconnected > [ 1.456161] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 1.456165] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 1.456192] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 1.456202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] status updated from unknown to disconnected > [ 1.456205] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 1.456214] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no > [ 1.456223] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no > [ 1.456230] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes > [ 1.456237] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no > [ 1.456244] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes > [ 1.456250] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no > [ 1.456257] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no > [ 1.456264] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 1.456271] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 > [ 1.456278] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 > [ 1.456285] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 1.456291] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 > [ 1.456297] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 > [ 1.456304] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 1.456310] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 16384x16384 config > [ 1.456319] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) > [ 1.456325] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) > [ 1.456331] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane > [ 1.456335] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 1 primary plane > [ 1.456339] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 2 primary plane > [ 1.456368] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one > [ 1.461444] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000 > [ 1.461492] fbcon: i915drmfb (fb1) is primary device > [ 1.461493] fbcon: Remapping primary device, fb1, to tty 1-63 > [ 1.461508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 1.461518] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002dfe43fd state to 00000000fc0cb429 > [ 1.461526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000000bf01569 state to 00000000fc0cb429 > [ 1.461535] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000000bf01569 > [ 1.461543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ab6fdf3f state to 00000000fc0cb429 > [ 1.461550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ab6fdf3f > [ 1.461558] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d93e8df3 state to 00000000fc0cb429 > [ 1.461566] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000015cf0577 state to 00000000fc0cb429 > [ 1.461573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000015cf0577 > [ 1.461580] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003292b89f state to 00000000fc0cb429 > [ 1.461588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003292b89f > [ 1.461595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f4491376 state to 00000000fc0cb429 > [ 1.461602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e2798a03 state to 00000000fc0cb429 > [ 1.461609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e2798a03 > [ 1.461616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007f2e9b45 state to 00000000fc0cb429 > [ 1.461624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007f2e9b45 > [ 1.461632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 > [ 1.461640] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000de3ff82c > [ 1.461648] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane 1A] state 000000002dfe43fd to [CRTC:51:pipe A] > [ 1.461655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002dfe43fd > [ 1.461662] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 1.461670] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034523972 state to 00000000fc0cb429 > [ 1.461678] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [NOCRTC] > [ 1.461685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [CRTC:51:pipe A] > [ 1.461693] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 00000000fc0cb429 > [ 1.461700] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 00000000dd2a82ac > [ 1.461707] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:52:plane 1B] state 00000000d93e8df3 to [CRTC:72:pipe B] > [ 1.461714] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d93e8df3 > [ 1.461721] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 1.461730] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000de1711cf state to 00000000fc0cb429 > [ 1.461736] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000de1711cf to [CRTC:72:pipe B] > [ 1.461744] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e46349dc state to 00000000fc0cb429 > [ 1.461751] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e46349dc > [ 1.461758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f4491376 > [ 1.461765] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 1.461772] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 1.461779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] mode changed > [ 1.461783] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] mode changed > [ 1.461786] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] enable changed > [ 1.461790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] active changed > [ 1.461795] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.461798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.461802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.461805] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] using [ENCODER:119:DDI D] on [CRTC:72:pipe B] > [ 1.461808] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] needs all connectors, enable: y, active: y > [ 1.461816] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 1.461823] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 1.461827] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] needs all connectors, enable: y, active: y > [ 1.461834] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 1.461841] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 1.461874] [drm:intel_atomic_check [i915]] [CONNECTOR:110:DP-2] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 > [ 1.461911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz > [ 1.461941] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > [ 1.461968] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 > [ 1.461996] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 > [ 1.462030] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 > [ 1.462061] [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in has_audio unable to verify whether state matches exactly, forcing modeset (expected no, found yes) > [ 1.462091] [drm:intel_atomic_check [i915]] [CONNECTOR:120:DP-3] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 > [ 1.462124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz > [ 1.462151] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > [ 1.462178] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 > [ 1.462204] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 > [ 1.462236] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 > [ 1.462265] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in lane_count (expected 0, found 4) > [ 1.462294] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in dp_m_n (expected tu 0 gmch 0/0 link 0/0, or tu 0 gmch 0/0 link 0/0, found tu 64, gmch 6212812/8388608 link 1035468/1048576) > [ 1.462321] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_types (expected 0x00000000, found 0x00000080) > [ 1.462349] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 3840) > [ 1.462376] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 4000) > [ 1.462402] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 3840) > [ 1.462429] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 4000) > [ 1.462455] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 3902) > [ 1.462481] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 3950) > [ 1.462507] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 2160) > [ 1.462533] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 2222) > [ 1.462559] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 2160) > [ 1.462584] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 2222) > [ 1.462610] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 2163) > [ 1.462636] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 2168) > [ 1.462662] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pixel_multiplier (expected 0, found 1) > [ 1.462688] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_format (expected 0, found 1) > [ 1.462714] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in has_audio (expected no, found yes) > [ 1.462740] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (1) (expected 0, found 1) > [ 1.462766] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8) > [ 1.462792] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pipe_bpp (expected 0, found 24) > [ 1.462818] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 533250) > [ 1.462843] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in port_clock (expected 0, found 540000) > [ 1.462875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 > [ 1.462904] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 0 -> 1, off 0, on 1, ms 1 > [ 1.462933] [drm:intel_modeset_calc_cdclk [i915]] Modeset required for cdclk change > [ 1.462960] [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz > [ 1.462986] [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 2, actual 2 > [ 1.463015] [drm:intel_find_shared_dpll [i915]] [CRTC:51:pipe A] allocated DPLL 1 > [ 1.463043] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe A > [ 1.463071] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 > [ 1.463099] [drm:intel_find_shared_dpll [i915]] [CRTC:72:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 1) > [ 1.463126] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe B > [ 1.463157] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 0) -> ( 0 - 401), size 0 -> 401 > [ 1.463181] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 847 - 892) -> ( 401 - 446), size 45 -> 45 > [ 1.463204] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm > [ 1.463227] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 > [ 1.463249] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 > [ 1.463271] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 > [ 1.463292] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] ddb ( 0 - 0) -> ( 446 - 847), size 0 -> 401 > [ 1.463312] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 > [ 1.463332] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm > [ 1.463353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 > [ 1.463373] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 > [ 1.463392] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 > [ 1.463423] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [modeset] > [ 1.463453] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB > [ 1.463482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 > [ 1.463510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 > [ 1.463537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 > [ 1.463564] [drm:intel_dump_pipe_config [i915]] requested mode: > [ 1.463573] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.463600] [drm:intel_dump_pipe_config [i915]] adjusted mode: > [ 1.463608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.463636] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 > [ 1.463662] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 > [ 1.463689] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 > [ 1.463715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no > [ 1.463741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 > [ 1.463768] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 > [ 1.463831] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > [ 1.463857] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> > [ 1.463883] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes > [ 1.463909] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 > [ 1.463935] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 > [ 1.463961] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no > [ 1.463987] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor A] fb: [NOFB], visible: no > [ 1.464013] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [modeset] > [ 1.464039] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB > [ 1.464064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 > [ 1.464090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 > [ 1.464115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 > [ 1.464140] [drm:intel_dump_pipe_config [i915]] requested mode: > [ 1.464148] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.464174] [drm:intel_dump_pipe_config [i915]] adjusted mode: > [ 1.464182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.464209] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 > [ 1.464234] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 > [ 1.464260] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 > [ 1.464286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no > [ 1.464311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 > [ 1.464336] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 > [ 1.464362] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > [ 1.464387] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> > [ 1.464414] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes > [ 1.464439] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 > [ 1.464465] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 > [ 1.464491] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 2B] fb: [NOFB], visible: no > [ 1.464516] [drm:intel_dump_pipe_config [i915]] [PLANE:68:cursor B] fb: [NOFB], visible: no > [ 1.464526] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 1.464573] [drm:intel_disable_pipe [i915]] disabling pipe A > [ 1.467843] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well > [ 1.467878] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 51 > [ 1.467923] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 > [ 1.467957] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 2 > [ 1.467991] i915 0000:00:02.0: [drm:intel_disable_sagv [i915]] Disabling SAGV > [ 1.468025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI B] > [ 1.468055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:96:DP-MST A] > [ 1.468085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:97:DP-MST B] > [ 1.468114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:98:DP-MST C] > [ 1.468143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:109:DDI C] > [ 1.468172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:111:DP-MST A] > [ 1.468200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:112:DP-MST B] > [ 1.468228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:113:DP-MST C] > [ 1.468256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:119:DDI D] > [ 1.468284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:121:DP-MST A] > [ 1.468312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:122:DP-MST B] > [ 1.468340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:123:DP-MST C] > [ 1.468367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:129:DDI E] > [ 1.468396] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 0 > [ 1.468424] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 > [ 1.468452] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 2 > [ 1.468481] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 3 > [ 1.468512] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 51 > [ 1.468542] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 > [ 1.468641] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well > [ 1.469400] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 > [ 1.469709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 > [ 1.469737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 > [ 1.469765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 > [ 1.469793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 > [ 1.470489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 > [ 1.470517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 > [ 1.470544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.471230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 > [ 1.471257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 > [ 1.471284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.471974] [drm:intel_dp_start_link_train [i915]] clock recovery OK > [ 1.472002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 > [ 1.473297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful > [ 1.473473] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:110:DP-2] Link Training Passed at Link Rate = 540000, Lane count = 4 > [ 1.473640] [drm:intel_enable_pipe [i915]] enabling pipe A > [ 1.473675] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS > [ 1.473705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:110:DP-2], [ENCODER:109:DDI C] > [ 1.473735] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder A, 36 bytes ELD > [ 1.473767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud > [ 1.473810] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 72 > [ 1.473841] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well > [ 1.474602] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 > [ 1.474908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 > [ 1.474936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 > [ 1.474964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 > [ 1.474992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 > [ 1.475686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 > [ 1.475714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 > [ 1.475740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.476426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 > [ 1.476454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 > [ 1.476481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.477166] [drm:intel_dp_start_link_train [i915]] clock recovery OK > [ 1.477193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 > [ 1.478488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful > [ 1.478664] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:120:DP-3] Link Training Passed at Link Rate = 540000, Lane count = 4 > [ 1.478830] [drm:intel_enable_pipe [i915]] enabling pipe B > [ 1.478862] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS > [ 1.478897] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun > [ 1.478928] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:120:DP-3], [ENCODER:119:DDI D] > [ 1.478957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder B, 36 bytes ELD > [ 1.478988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud > [ 1.495987] [drm:verify_connector_state [i915]] [CONNECTOR:110:DP-2] > [ 1.496025] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A] > [ 1.496067] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 > [ 1.496104] [drm:verify_connector_state [i915]] [CONNECTOR:120:DP-3] > [ 1.496135] [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B] > [ 1.496171] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 > [ 1.496241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 > [ 1.496252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a8e00a70 state to 000000002a70fa07 > [ 1.496261] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 000000002a70fa07 > [ 1.496285] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c4a0e3a state to 000000002a70fa07 > [ 1.496310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c4a0e3a > [ 1.496324] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 1.496335] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 1.496350] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 000000002a70fa07 > [ 1.496359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f > [ 1.496366] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000062109416 state to 000000002a70fa07 > [ 1.496374] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 000000002a70fa07 > [ 1.496381] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f97067cf state to 000000002a70fa07 > [ 1.496389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f97067cf > [ 1.496397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a6369fc8 state to 000000002a70fa07 > [ 1.496404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a6369fc8 > [ 1.496412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000091b367b1 state to 000000002a70fa07 > [ 1.496421] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000009bdf158a state to 000000002a70fa07 > [ 1.496428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000009bdf158a > [ 1.496435] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fb662b09 state to 000000002a70fa07 > [ 1.496443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fb662b09 > [ 1.496455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a8e00a70 > [ 1.496463] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 > [ 1.496471] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 000000002a70fa07 > [ 1.496479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] > [ 1.496486] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] > [ 1.496494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000062109416 > [ 1.496501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 > [ 1.496509] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000860da491 state to 000000002a70fa07 > [ 1.496516] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [NOCRTC] > [ 1.496523] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [CRTC:72:pipe B] > [ 1.496531] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 000000002a70fa07 > [ 1.496538] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 1.496545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000091b367b1 > [ 1.496552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 > [ 1.496560] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 > [ 1.496570] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.496574] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.496578] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.496581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.496625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.496658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.496675] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 > [ 1.512640] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 > [ 1.512654] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 > [ 1.524341] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 1.524352] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 > [ 1.524362] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 1.524370] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 > [ 1.524382] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f > [ 1.524394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 > [ 1.524403] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 > [ 1.524412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 1.524420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 1.524428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 > [ 1.524437] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 1.524446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 > [ 1.524454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 1.524463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 > [ 1.524471] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 > [ 1.524479] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 > [ 1.524489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 > [ 1.524497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a > [ 1.524506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c > [ 1.524515] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 1.524524] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003979f4ee state to 0000000098df4bf3 > [ 1.524533] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [NOCRTC] > [ 1.524542] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [CRTC:51:pipe A] > [ 1.524551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 1.524559] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 1.524568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 > [ 1.524576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] > [ 1.524585] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] > [ 1.524593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 1.524602] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 1.524610] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f > [ 1.524619] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 1.524628] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 1.524638] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.524643] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.524648] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.524652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.524716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.524754] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.524771] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 1.553743] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 1.553761] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 > [ 1.553774] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 1.553786] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015579631 state to 00000000482d1aa4 > [ 1.553798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 00000000482d1aa4 > [ 1.553808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000482d1aa4 > [ 1.553819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b > [ 1.553830] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000482d1aa4 > [ 1.553840] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 > [ 1.553850] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000041c6228e state to 00000000482d1aa4 > [ 1.553860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000022f73fd2 state to 00000000482d1aa4 > [ 1.553869] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001f82d691 state to 00000000482d1aa4 > [ 1.553879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001f82d691 > [ 1.553889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 > [ 1.553899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 > [ 1.553909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e5892e4f state to 00000000482d1aa4 > [ 1.553921] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c3b3ca94 state to 00000000482d1aa4 > [ 1.553931] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c3b3ca94 > [ 1.553940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000074f436be state to 00000000482d1aa4 > [ 1.553950] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000074f436be > [ 1.553960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015579631 > [ 1.553970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 > [ 1.553981] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000482d1aa4 > [ 1.553991] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] > [ 1.554000] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] > [ 1.554010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000041c6228e > [ 1.554020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 > [ 1.554030] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000482d1aa4 > [ 1.554039] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 1.554048] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 1.554058] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000006ede65dd state to 00000000482d1aa4 > [ 1.554067] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000006ede65dd > [ 1.554076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e5892e4f > [ 1.554086] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 > [ 1.554096] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 > [ 1.554108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.554113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.554118] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.554123] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.554190] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.554233] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.554259] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 > [ 1.562628] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 > [ 1.562645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 > [ 1.575634] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c > [ 1.575648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 00000000fcb1012c > [ 1.575660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000fcb1012c > [ 1.575670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ccf8507 state to 00000000fcb1012c > [ 1.575681] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ccf8507 > [ 1.575691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bb3d8d45 state to 00000000fcb1012c > [ 1.575702] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bb3d8d45 > [ 1.575716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000485c2b88 state to 00000000fcb1012c > [ 1.575725] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002ba4f36a state to 00000000fcb1012c > [ 1.575735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004e08d13d state to 00000000fcb1012c > [ 1.575745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004e08d13d > [ 1.575754] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b2b055b6 state to 00000000fcb1012c > [ 1.575767] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b2b055b6 > [ 1.575798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000010a446a8 state to 00000000fcb1012c > [ 1.575807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c > [ 1.575817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf > [ 1.575854] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d365bfc5 state to 00000000fcb1012c > [ 1.575863] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d365bfc5 > [ 1.575874] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a > [ 1.575884] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c > [ 1.575894] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001d9bfafc state to 00000000fcb1012c > [ 1.575904] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [NOCRTC] > [ 1.575914] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [CRTC:51:pipe A] > [ 1.575924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000485c2b88 > [ 1.575933] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c > [ 1.575943] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000514f7582 state to 00000000fcb1012c > [ 1.575952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [NOCRTC] > [ 1.575961] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [CRTC:72:pipe B] > [ 1.575971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c > [ 1.575980] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 > [ 1.575989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000010a446a8 > [ 1.575999] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c > [ 1.576008] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c > [ 1.576020] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.576025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.576030] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.576035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.576097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.576139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.576167] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c > [ 1.610983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bb4d667a > [ 1.611007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c > [ 1.611032] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e9b5f5ed state to 00000000bb4d667a > [ 1.611054] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c > [ 1.611079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000bb4d667a > [ 1.611096] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000122a804f state to 00000000bb4d667a > [ 1.611115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000122a804f > [ 1.611131] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005d690c84 state to 00000000bb4d667a > [ 1.611149] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005d690c84 > [ 1.611165] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c775be6 state to 00000000bb4d667a > [ 1.611183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000bb4d667a > [ 1.611198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000b5f6abf5 state to 00000000bb4d667a > [ 1.611214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000b5f6abf5 > [ 1.611230] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000281af025 state to 00000000bb4d667a > [ 1.611246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000281af025 > [ 1.611261] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053454233 state to 00000000bb4d667a > [ 1.611276] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b2cdb294 state to 00000000bb4d667a > [ 1.611292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b2cdb294 > [ 1.611308] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000555d146c state to 00000000bb4d667a > [ 1.611323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000555d146c > [ 1.611341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e9b5f5ed > [ 1.611358] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000bb4d667a > [ 1.611375] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000084c59d5f state to 00000000bb4d667a > [ 1.611396] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [NOCRTC] > [ 1.611412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [CRTC:51:pipe A] > [ 1.611428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c775be6 > [ 1.611444] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000bb4d667a > [ 1.611460] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000adc2b291 state to 00000000bb4d667a > [ 1.611476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [NOCRTC] > [ 1.611491] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [CRTC:72:pipe B] > [ 1.611508] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000bb4d667a > [ 1.611524] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d > [ 1.611539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053454233 > [ 1.611560] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000bb4d667a > [ 1.611577] [drm:drm_atomic_check_only [drm]] checking 00000000bb4d667a > [ 1.611603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.611612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.611620] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.611628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.611728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.611798] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.611840] [drm:drm_atomic_commit [drm]] committing 00000000bb4d667a > [ 1.645601] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bb4d667a > [ 1.645625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 > [ 1.645642] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bb4d667a > [ 1.645659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000060d5862a state to 00000000482d1aa4 > [ 1.645675] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000482d1aa4 > [ 1.645689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000071f245df state to 00000000482d1aa4 > [ 1.645705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000071f245df > [ 1.645722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000482d1aa4 > [ 1.645736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be > [ 1.645752] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 00000000482d1aa4 > [ 1.645767] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000669bfcd7 state to 00000000482d1aa4 > [ 1.645779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5892e4f state to 00000000482d1aa4 > [ 1.645794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5892e4f > [ 1.645807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 > [ 1.645820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 > [ 1.645834] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001f82d691 state to 00000000482d1aa4 > [ 1.645846] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 00000000482d1aa4 > [ 1.645860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e > [ 1.645874] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 00000000482d1aa4 > [ 1.645888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 > [ 1.645902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000060d5862a > [ 1.645916] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 > [ 1.645930] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 00000000482d1aa4 > [ 1.645945] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 1.645958] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 1.645971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 > [ 1.645984] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 > [ 1.645998] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 00000000482d1aa4 > [ 1.646011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 1.646024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 1.646037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d7f71e60 state to 00000000482d1aa4 > [ 1.646050] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d7f71e60 > [ 1.646063] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001f82d691 > [ 1.646076] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 > [ 1.646090] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 > [ 1.646105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.646113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.646120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.646126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.646207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.646267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.646298] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 > [ 1.662741] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 > [ 1.662763] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 > [ 1.682625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 1.682648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f101de7e state to 0000000098df4bf3 > [ 1.682667] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 1.682683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e81eafbe state to 0000000098df4bf3 > [ 1.682701] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e81eafbe > [ 1.682718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000026a13e4f state to 0000000098df4bf3 > [ 1.682735] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000026a13e4f > [ 1.682755] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 > [ 1.682770] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 1.682784] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005342f7e7 state to 0000000098df4bf3 > [ 1.682801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005342f7e7 > [ 1.682816] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fb96f9d3 state to 0000000098df4bf3 > [ 1.682832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fb96f9d3 > [ 1.682848] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000003eec9b7 state to 0000000098df4bf3 > [ 1.682863] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 > [ 1.682879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a > [ 1.682894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 > [ 1.682909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 > [ 1.682926] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f101de7e > [ 1.682942] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 1.682962] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000064c4b21e state to 0000000098df4bf3 > [ 1.682979] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [NOCRTC] > [ 1.682994] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [CRTC:51:pipe A] > [ 1.683010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe > [ 1.683025] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 1.683041] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 > [ 1.683056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] > [ 1.683072] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] > [ 1.683088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 1.683103] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 1.683118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000003eec9b7 > [ 1.683133] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 1.683149] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 1.683178] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.683187] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.683196] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.683203] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.683302] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.683372] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.683406] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 1.683650] ata1: SATA link down (SStatus 4 SControl 300) > [ 1.683668] ata4: SATA link down (SStatus 4 SControl 300) > [ 1.683686] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300) > [ 1.683711] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) > [ 1.685953] ata2.00: supports DRM functions and may not be fully accessible > [ 1.686212] ata3.00: ATAPI: TSSTcorp CDDVDW SH-224GB, SB00, max UDMA/100 > [ 1.687451] ata3.00: configured for UDMA/100 > [ 1.692177] ata2.00: disabling queued TRIM support > [ 1.692194] ata2.00: ATA-9: Samsung SSD 850 PRO 512GB, EXM02B6Q, max UDMA/133 > [ 1.692196] ata2.00: 1000215216 sectors, multi 1: LBA48 NCQ (depth 32), AA > [ 1.696183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 1.696209] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 1.698509] ata2.00: supports DRM functions and may not be fully accessible > [ 1.699829] usb 1-7: new high-speed USB device number 2 using xhci_hcd > [ 1.704324] ata2.00: disabling queued TRIM support > [ 1.710263] ata2.00: configured for UDMA/133 > [ 1.710469] scsi 1:0:0:0: Direct-Access ATA Samsung SSD 850 2B6Q PQ: 0 ANSI: 5 > [ 1.713317] scsi 2:0:0:0: CD-ROM TSSTcorp CDDVDW SH-224GB SB00 PQ: 0 ANSI: 5 > [ 1.725160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c > [ 1.725192] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000c8bd6dc state to 00000000fcb1012c > [ 1.725221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 00000000fcb1012c > [ 1.725245] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000083c05b3d state to 00000000fcb1012c > [ 1.725273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000083c05b3d > [ 1.725297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008409a024 state to 00000000fcb1012c > [ 1.725322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008409a024 > [ 1.725347] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006164f3e3 state to 00000000fcb1012c > [ 1.725370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 00000000fcb1012c > [ 1.725394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000382acb58 state to 00000000fcb1012c > [ 1.725418] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000382acb58 > [ 1.725442] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a9a5a77 state to 00000000fcb1012c > [ 1.725466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009a9a5a77 > [ 1.725489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d365bfc5 state to 00000000fcb1012c > [ 1.725510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c > [ 1.725534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf > [ 1.725557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010a446a8 state to 00000000fcb1012c > [ 1.725580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010a446a8 > [ 1.725608] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000c8bd6dc > [ 1.725633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c > [ 1.725662] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000008c0081a2 state to 00000000fcb1012c > [ 1.725687] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [NOCRTC] > [ 1.725712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [CRTC:51:pipe A] > [ 1.725736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006164f3e3 > [ 1.725759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c > [ 1.725783] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 00000000fcb1012c > [ 1.725806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] > [ 1.725828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] > [ 1.725853] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c > [ 1.725876] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 > [ 1.725898] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d365bfc5 > [ 1.725921] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c > [ 1.725945] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c > [ 1.725977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.725990] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.726002] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.726013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.726148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.726252] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.726302] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c > [ 1.740953] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c > [ 1.740990] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c > [ 1.776024] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000895e0f29 > [ 1.776052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000bf89eae0 state to 00000000895e0f29 > [ 1.776075] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002aa6a9f8 state to 00000000895e0f29 > [ 1.776097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f454a2f1 state to 00000000895e0f29 > [ 1.776121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f454a2f1 > [ 1.776142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000895e0f29 > [ 1.776163] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 > [ 1.776185] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001e3a4a97 state to 00000000895e0f29 > [ 1.776208] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 00000000895e0f29 > [ 1.776228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000f80a3c5 state to 00000000895e0f29 > [ 1.776249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000f80a3c5 > [ 1.776269] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000002f5f5ecb state to 00000000895e0f29 > [ 1.776289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000002f5f5ecb > [ 1.776311] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000082c8a15 state to 00000000895e0f29 > [ 1.776330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000017301ddd state to 00000000895e0f29 > [ 1.776350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000017301ddd > [ 1.776369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000bd98ba2f state to 00000000895e0f29 > [ 1.776389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000bd98ba2f > [ 1.776415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000bf89eae0 > [ 1.776436] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000895e0f29 > [ 1.776458] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002f3cb69d state to 00000000895e0f29 > [ 1.776479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [NOCRTC] > [ 1.776499] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [CRTC:51:pipe A] > [ 1.776522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001e3a4a97 > [ 1.776542] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000895e0f29 > [ 1.776562] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001bc59558 state to 00000000895e0f29 > [ 1.776582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [NOCRTC] > [ 1.776601] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [CRTC:72:pipe B] > [ 1.776621] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e59c9ea1 state to 00000000895e0f29 > [ 1.776641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e59c9ea1 > [ 1.776659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000082c8a15 > [ 1.776679] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000895e0f29 > [ 1.776700] [drm:drm_atomic_check_only [drm]] checking 00000000895e0f29 > [ 1.776735] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.776746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.776757] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.776766] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.776890] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.776981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.777022] [drm:drm_atomic_commit [drm]] committing 00000000895e0f29 > [ 1.804096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 > [ 1.804107] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000895e0f29 > [ 1.804118] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001e6f8dac state to 00000000548834f9 > [ 1.804128] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000895e0f29 > [ 1.804139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005b7d8c1d state to 00000000548834f9 > [ 1.804146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b0a2562b state to 00000000548834f9 > [ 1.804155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b0a2562b > [ 1.804162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000210ee201 state to 00000000548834f9 > [ 1.804172] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000210ee201 > [ 1.804179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074e96990 state to 00000000548834f9 > [ 1.804190] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000085f180bd state to 00000000548834f9 > [ 1.804196] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018d44f01 state to 00000000548834f9 > [ 1.804204] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018d44f01 > [ 1.804211] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c0bd820d state to 00000000548834f9 > [ 1.804218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c0bd820d > [ 1.804225] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c73eec69 state to 00000000548834f9 > [ 1.804232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000080dfd757 state to 00000000548834f9 > [ 1.804239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000080dfd757 > [ 1.804246] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f141c893 state to 00000000548834f9 > [ 1.804253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f141c893 > [ 1.804261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001e6f8dac > [ 1.804268] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 > [ 1.804281] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000f3f263f3 state to 00000000548834f9 > [ 1.804291] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [NOCRTC] > [ 1.804298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [CRTC:51:pipe A] > [ 1.804306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000074e96990 > [ 1.804313] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 > [ 1.804320] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000af6800c9 state to 00000000548834f9 > [ 1.804327] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [NOCRTC] > [ 1.804334] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [CRTC:72:pipe B] > [ 1.804341] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 > [ 1.804348] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 > [ 1.804355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c73eec69 > [ 1.804362] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 > [ 1.804369] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 > [ 1.804388] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.804392] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.804398] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.804401] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.804446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.804478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.804499] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 > [ 1.823766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 > [ 1.823787] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 > [ 1.823804] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 1.823818] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 000000006432a660 > [ 1.823827] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 > [ 1.823835] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c471465 state to 000000006432a660 > [ 1.823845] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c471465 > [ 1.823853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5b7e29b state to 000000006432a660 > [ 1.823862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5b7e29b > [ 1.823870] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 > [ 1.823878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 > [ 1.823885] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e7bdd2e4 state to 000000006432a660 > [ 1.823893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e7bdd2e4 > [ 1.823901] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 > [ 1.823909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 > [ 1.823917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000087dc1fd8 state to 000000006432a660 > [ 1.823925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 000000006432a660 > [ 1.823933] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d > [ 1.823941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000df34b7b3 state to 000000006432a660 > [ 1.823949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000df34b7b3 > [ 1.823957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a > [ 1.823965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 1.823974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 > [ 1.823982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] > [ 1.823990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] > [ 1.824001] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa > [ 1.824009] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 1.824017] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 > [ 1.824025] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] > [ 1.824032] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] > [ 1.824041] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 1.824048] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 1.824056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000087dc1fd8 > [ 1.824063] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 1.824071] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 1.824082] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.824099] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.824106] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.824110] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.824157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.824191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.824208] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 1.841121] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 1.841136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 1.854405] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 1.854418] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057ed1a51 state to 00000000c6c933d1 > [ 1.854430] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 > [ 1.854441] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008ffba3f3 state to 00000000c6c933d1 > [ 1.854453] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008ffba3f3 > [ 1.854464] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 > [ 1.854476] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 > [ 1.854489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 > [ 1.854499] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 1.854509] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 > [ 1.854520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 > [ 1.854530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 1.854541] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 1.854552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 > [ 1.854561] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 > [ 1.854572] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab > [ 1.854584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 > [ 1.854594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 > [ 1.854606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000057ed1a51 > [ 1.854617] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 1.854628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 > [ 1.854640] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] > [ 1.854650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] > [ 1.854661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 > [ 1.854671] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 1.854682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 > [ 1.854692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] > [ 1.854703] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] > [ 1.854714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 > [ 1.854724] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 > [ 1.854734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 > [ 1.854744] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 1.854755] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 1.854767] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.854773] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.854779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.854784] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.854860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.854907] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.854927] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 1.879165] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 1.879183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 1.879202] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 > [ 1.879217] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 1.879236] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 > [ 1.879248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 > [ 1.879265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 > [ 1.879281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 > [ 1.879294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 > [ 1.879306] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 > [ 1.879317] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 > [ 1.879328] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 > [ 1.879346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 > [ 1.879357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 > [ 1.879369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd > [ 1.879382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 > [ 1.879393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 > [ 1.879405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 > [ 1.879416] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 1.879428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 1.879440] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 > [ 1.879453] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 1.879465] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 > [ 1.879478] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] > [ 1.879490] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] > [ 1.879502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 > [ 1.879514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 1.879526] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 1.879538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 1.879549] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 1.879561] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 1.879573] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 1.879584] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 > [ 1.879596] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 1.879608] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 1.879622] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.879629] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.879635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.879641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.879713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.879765] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.879801] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 1.896360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 1.896381] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 1.912612] tsc: Refined TSC clocksource calibration: 3503.999 MHz > [ 1.912618] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x3282124c47b, max_idle_ns: 440795239402 ns > [ 1.912658] clocksource: Switched to clocksource tsc > [ 1.912681] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 1.912697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 > [ 1.912714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 1.912729] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 > [ 1.912743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe > [ 1.912756] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 > [ 1.912769] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 > [ 1.912781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 1.912793] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 1.912804] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 > [ 1.912817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 > [ 1.912829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 > [ 1.912841] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f > [ 1.912853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 > [ 1.912866] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 1.912878] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 > [ 1.912889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 > [ 1.912901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e > [ 1.912914] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f > [ 1.912926] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 1.912939] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000095845c0a state to 0000000098df4bf3 > [ 1.912952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [NOCRTC] > [ 1.912964] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [CRTC:51:pipe A] > [ 1.912976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 1.912987] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 1.912999] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 > [ 1.913011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] > [ 1.913023] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] > [ 1.913035] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 1.913047] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 1.913058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c > [ 1.913070] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 1.913082] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 1.913095] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.913102] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.913108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.913114] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.913187] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.913239] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.913263] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 1.929772] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 1.929793] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 1.949476] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 > [ 1.949495] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006a25a70b state to 000000002a70fa07 > [ 1.949513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e46349dc state to 000000002a70fa07 > [ 1.949530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f2e9b45 state to 000000002a70fa07 > [ 1.949549] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f2e9b45 > [ 1.949565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e2798a03 state to 000000002a70fa07 > [ 1.949583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e2798a03 > [ 1.949599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f4491376 state to 000000002a70fa07 > [ 1.949615] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 000000002a70fa07 > [ 1.949630] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003292b89f state to 000000002a70fa07 > [ 1.949647] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003292b89f > [ 1.949662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000015cf0577 state to 000000002a70fa07 > [ 1.949679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000015cf0577 > [ 1.949694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 000000002a70fa07 > [ 1.949709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ab6fdf3f state to 000000002a70fa07 > [ 1.949725] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ab6fdf3f > [ 1.949744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bf01569 state to 000000002a70fa07 > [ 1.949760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bf01569 > [ 1.949777] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006a25a70b > [ 1.949793] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 > [ 1.949811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003a5f3d7f state to 000000002a70fa07 > [ 1.949828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [NOCRTC] > [ 1.949844] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [CRTC:51:pipe A] > [ 1.949862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f4491376 > [ 1.949879] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 > [ 1.949895] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000bd54c871 state to 000000002a70fa07 > [ 1.949911] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [NOCRTC] > [ 1.949926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [CRTC:72:pipe B] > [ 1.949943] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000de3ff82c state to 000000002a70fa07 > [ 1.949959] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000de3ff82c > [ 1.949974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 > [ 1.949990] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 > [ 1.950007] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 > [ 1.950024] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.950034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.950042] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.950050] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.950146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.950217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.950249] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 > [ 1.963116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 > [ 1.963143] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 > [ 1.975843] usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd > [ 1.982659] usb 1-7: New USB device found, idVendor=1307, idProduct=0330, bcdDevice= 1.00 > [ 1.982661] usb 1-7: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 1.982663] usb 1-7: Product: Mass Storage Device > [ 1.982664] usb 1-7: Manufacturer: Generic > [ 1.982665] usb 1-7: SerialNumber: 00000000000006 > [ 1.984947] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 1.984976] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000087dc1fd8 state to 000000006432a660 > [ 1.985005] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 > [ 1.985028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ada87627 state to 000000006432a660 > [ 1.985054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ada87627 > [ 1.985077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e7bdd2e4 state to 000000006432a660 > [ 1.985102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e7bdd2e4 > [ 1.985125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 > [ 1.985148] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 > [ 1.985170] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5b7e29b state to 000000006432a660 > [ 1.985194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5b7e29b > [ 1.985218] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001c471465 state to 000000006432a660 > [ 1.985242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001c471465 > [ 1.985264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 > [ 1.985286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000bf357c4b state to 000000006432a660 > [ 1.985309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000bf357c4b > [ 1.985332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 000000006432a660 > [ 1.985355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 > [ 1.985380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000087dc1fd8 > [ 1.985403] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 1.985435] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 > [ 1.985459] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] > [ 1.985483] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] > [ 1.985507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa > [ 1.985530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 1.985553] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 > [ 1.985576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 1.985600] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 1.985623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 1.985646] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 1.985668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a > [ 1.985691] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 1.985714] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 1.985747] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.985759] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.985771] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.985782] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.985898] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.985980] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.986020] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 1.988961] usb-storage 1-7:1.0: USB Mass Storage device detected > [ 1.989364] scsi host4: usb-storage 1-7:1.0 > [ 1.989455] usbcore: registered new interface driver usb-storage > [ 1.991210] usbcore: registered new interface driver uas > [ 1.996109] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 1.996129] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 1.999995] usb 2-1: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 > [ 1.999996] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.000778] hub 2-1:1.0: USB hub found > [ 2.000960] hub 2-1:1.0: 4 ports detected > [ 2.013903] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.013919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 > [ 2.013933] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 > [ 2.013946] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 > [ 2.013961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 > [ 2.013975] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.013989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000183fcb7 > [ 2.014002] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000aff706ab state to 00000000c6c933d1 > [ 2.014015] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 2.014028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.014042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fc1d1694 > [ 2.014055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 2.014068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 2.014080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.014092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.014105] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001964fcb3 > [ 2.014117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000dd33f136 state to 00000000c6c933d1 > [ 2.014129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000dd33f136 > [ 2.014143] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 > [ 2.014156] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.014169] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 > [ 2.014182] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] > [ 2.014195] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] > [ 2.014208] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000aff706ab > [ 2.014221] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.014234] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 > [ 2.014247] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] > [ 2.014260] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] > [ 2.014273] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 > [ 2.014286] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 > [ 2.014299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003e7fb927 > [ 2.014312] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.014325] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.014340] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.014348] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.014354] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.014361] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.014425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.014482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.014507] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.029646] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.029666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.047486] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000246f13a6 > [ 2.047504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f80a3c5 state to 00000000246f13a6 > [ 2.047520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ad566469 state to 00000000246f13a6 > [ 2.047534] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001e3a4a97 state to 00000000246f13a6 > [ 2.047550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001e3a4a97 > [ 2.047567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000246f13a6 > [ 2.047581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 > [ 2.047595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f454a2f1 state to 00000000246f13a6 > [ 2.047608] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 00000000246f13a6 > [ 2.047620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bf89eae0 state to 00000000246f13a6 > [ 2.047634] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bf89eae0 > [ 2.047648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000082c8a15 state to 00000000246f13a6 > [ 2.047661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000082c8a15 > [ 2.047674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000017301ddd state to 00000000246f13a6 > [ 2.047690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9473c9b state to 00000000246f13a6 > [ 2.047704] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9473c9b > [ 2.047717] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fdc091c8 state to 00000000246f13a6 > [ 2.047730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fdc091c8 > [ 2.047744] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000f80a3c5 > [ 2.047758] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000246f13a6 > [ 2.047779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000079f595ad state to 00000000246f13a6 > [ 2.047793] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [NOCRTC] > [ 2.047806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [CRTC:51:pipe A] > [ 2.047819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f454a2f1 > [ 2.047833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000246f13a6 > [ 2.047846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005876474e state to 00000000246f13a6 > [ 2.047860] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [NOCRTC] > [ 2.047872] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [CRTC:72:pipe B] > [ 2.047886] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000009be30044 state to 00000000246f13a6 > [ 2.047899] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000009be30044 > [ 2.047912] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000017301ddd > [ 2.047925] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000246f13a6 > [ 2.047938] [drm:drm_atomic_check_only [drm]] checking 00000000246f13a6 > [ 2.047954] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.047962] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.047968] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.047975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.048064] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.048124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.048152] [drm:drm_atomic_commit [drm]] committing 00000000246f13a6 > [ 2.063067] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000246f13a6 > [ 2.063089] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000246f13a6 > [ 2.084698] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 > [ 2.084727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f1595a5f state to 00000000548834f9 > [ 2.084747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ca8a0e1e state to 00000000548834f9 > [ 2.084765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f97cb978 state to 00000000548834f9 > [ 2.084787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f97cb978 > [ 2.084806] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e88acfd1 state to 00000000548834f9 > [ 2.084826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e88acfd1 > [ 2.084845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c2abb21 state to 00000000548834f9 > [ 2.084864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000ff2cde6 state to 00000000548834f9 > [ 2.084881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009f37190d state to 00000000548834f9 > [ 2.084900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009f37190d > [ 2.084918] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008793e16f state to 00000000548834f9 > [ 2.084937] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008793e16f > [ 2.084955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a71ddeb0 state to 00000000548834f9 > [ 2.084972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005371ffea state to 00000000548834f9 > [ 2.084990] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005371ffea > [ 2.085008] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000757b68ad state to 00000000548834f9 > [ 2.085026] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000757b68ad > [ 2.085045] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f1595a5f > [ 2.085064] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 > [ 2.085084] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000e808d856 state to 00000000548834f9 > [ 2.085103] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [NOCRTC] > [ 2.085121] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [CRTC:51:pipe A] > [ 2.085139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c2abb21 > [ 2.085157] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 > [ 2.085175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000004ac112a0 state to 00000000548834f9 > [ 2.085194] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [NOCRTC] > [ 2.085211] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [CRTC:72:pipe B] > [ 2.085231] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 > [ 2.085249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 > [ 2.085265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a71ddeb0 > [ 2.085283] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 > [ 2.085303] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 > [ 2.085324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.085335] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.085344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.085353] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.085466] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.085547] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.085583] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 > [ 2.096461] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 > [ 2.096491] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 > [ 2.119701] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.119718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 > [ 2.119732] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 > [ 2.119746] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 > [ 2.119761] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be > [ 2.119781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 > [ 2.119794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df > [ 2.119807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 > [ 2.119819] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 > [ 2.119831] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 > [ 2.119844] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 > [ 2.119858] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 > [ 2.119870] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b > [ 2.119882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 > [ 2.119893] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 > [ 2.119906] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 > [ 2.119917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.119930] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.119943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e > [ 2.119956] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.119971] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 > [ 2.119984] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 2.119996] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 2.120008] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a > [ 2.120020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.120033] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.120045] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.120056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.120073] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.120085] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.120096] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a > [ 2.120108] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.120120] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.120134] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.120141] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.120147] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.120153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.120236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.120291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.120315] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.129725] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.129746] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.143811] usb 1-10: new high-speed USB device number 3 using xhci_hcd > [ 2.146032] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.146049] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000053155f00 state to 0000000098df4bf3 > [ 2.146065] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.146077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f5e6213 state to 0000000098df4bf3 > [ 2.146093] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f5e6213 > [ 2.146107] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000515dc00f state to 0000000098df4bf3 > [ 2.146120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000515dc00f > [ 2.146133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 > [ 2.146145] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.146156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009d539ce0 state to 0000000098df4bf3 > [ 2.146170] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009d539ce0 > [ 2.146181] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a35c929d state to 0000000098df4bf3 > [ 2.146194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a35c929d > [ 2.146205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000046234f6 state to 0000000098df4bf3 > [ 2.146217] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 > [ 2.146229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e > [ 2.146240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 2.146252] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 > [ 2.146265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000053155f00 > [ 2.146278] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.146292] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000b34fddb1 state to 0000000098df4bf3 > [ 2.146305] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [NOCRTC] > [ 2.146317] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [CRTC:51:pipe A] > [ 2.146329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d > [ 2.146341] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.146354] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000416eca0f state to 0000000098df4bf3 > [ 2.146366] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [NOCRTC] > [ 2.146377] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [CRTC:72:pipe B] > [ 2.146390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.146402] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 2.146413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000046234f6 > [ 2.146425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.146438] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.146451] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.146458] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.146465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.146470] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.146546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.146602] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.146626] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.163065] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.163088] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.192362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 2.192398] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000091b367b1 state to 00000000fc0cb429 > [ 2.192425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 2.192450] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a6369fc8 state to 00000000fc0cb429 > [ 2.192481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a6369fc8 > [ 2.192510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000062109416 state to 00000000fc0cb429 > [ 2.192537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000062109416 > [ 2.192562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005fe5cc2f state to 00000000fc0cb429 > [ 2.192586] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 00000000fc0cb429 > [ 2.192609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000bf01569 state to 00000000fc0cb429 > [ 2.192636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000bf01569 > [ 2.192659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ab6fdf3f state to 00000000fc0cb429 > [ 2.192686] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ab6fdf3f > [ 2.192709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 > [ 2.192731] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 > [ 2.192756] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 > [ 2.192779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 > [ 2.192804] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f > [ 2.192830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000091b367b1 > [ 2.192855] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 2.192882] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000168ff23b state to 00000000fc0cb429 > [ 2.192908] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [NOCRTC] > [ 2.192933] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [CRTC:51:pipe A] > [ 2.192960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005fe5cc2f > [ 2.192986] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 2.193011] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000da9b77f0 state to 00000000fc0cb429 > [ 2.193036] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [NOCRTC] > [ 2.193061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [CRTC:72:pipe B] > [ 2.193088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ca6e974 state to 00000000fc0cb429 > [ 2.193113] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ca6e974 > [ 2.193137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 > [ 2.193161] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 2.193187] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 2.193212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.193227] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.193239] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.193252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.193403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.193510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.193559] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 2.207959] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 2.207999] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 2.235181] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.235205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 000000001ff947e6 > [ 2.235220] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 > [ 2.235233] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010a446a8 state to 000000001ff947e6 > [ 2.235247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010a446a8 > [ 2.235260] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c23288bf state to 000000001ff947e6 > [ 2.235274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c23288bf > [ 2.235287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d365bfc5 state to 000000001ff947e6 > [ 2.235301] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001775ba6b state to 000000001ff947e6 > [ 2.235316] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009a9a5a77 state to 000000001ff947e6 > [ 2.235328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009a9a5a77 > [ 2.235340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000382acb58 state to 000000001ff947e6 > [ 2.235352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000382acb58 > [ 2.235364] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006164f3e3 state to 000000001ff947e6 > [ 2.235376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000008409a024 state to 000000001ff947e6 > [ 2.235388] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000008409a024 > [ 2.235400] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000083c05b3d state to 000000001ff947e6 > [ 2.235412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000083c05b3d > [ 2.235425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a > [ 2.235438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.235451] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000fc47d714 state to 000000001ff947e6 > [ 2.235464] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [NOCRTC] > [ 2.235476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [CRTC:51:pipe A] > [ 2.235489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d365bfc5 > [ 2.235501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.235514] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 000000001ff947e6 > [ 2.235526] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] > [ 2.235538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] > [ 2.235551] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000048e8a8c4 state to 000000001ff947e6 > [ 2.235563] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000048e8a8c4 > [ 2.235575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006164f3e3 > [ 2.235587] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.235599] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.235628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.235635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.235641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.235647] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.235730] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.235784] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.235815] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.246467] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.246485] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.258018] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.258028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 > [ 2.258037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 000000006432a660 > [ 2.258045] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.258054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 > [ 2.258061] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 > [ 2.258069] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 > [ 2.258077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.258084] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 000000006432a660 > [ 2.258092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.258100] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 > [ 2.258110] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 > [ 2.258118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f > [ 2.258125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 > [ 2.258132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 > [ 2.258139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 > [ 2.258146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.258153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.258161] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa > [ 2.258169] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.258178] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000227e02b1 state to 000000006432a660 > [ 2.258186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [NOCRTC] > [ 2.258193] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [CRTC:51:pipe A] > [ 2.258203] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 > [ 2.258210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.258219] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 > [ 2.258226] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] > [ 2.258233] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] > [ 2.258242] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.258249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.258256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 > [ 2.258263] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.258271] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.258281] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.258285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.258289] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.258293] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.258354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.258387] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.258403] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.274508] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.274524] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.287455] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.287470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 > [ 2.287483] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.287494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 > [ 2.287508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f > [ 2.287519] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 > [ 2.287531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 > [ 2.287542] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 2.287553] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.287563] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 > [ 2.287574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 2.287585] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 > [ 2.287595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 2.287610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 > [ 2.287624] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 > [ 2.287635] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 > [ 2.287645] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 > [ 2.287656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a > [ 2.287667] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c > [ 2.287678] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.287690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009b609533 state to 0000000098df4bf3 > [ 2.287701] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [NOCRTC] > [ 2.287712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [CRTC:51:pipe A] > [ 2.287723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 2.287734] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.287744] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000050cb1035 state to 0000000098df4bf3 > [ 2.287755] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [NOCRTC] > [ 2.287765] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [CRTC:72:pipe B] > [ 2.287782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.287792] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 2.287803] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f > [ 2.287813] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.287825] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.287839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.287846] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.287851] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.287856] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.287928] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.287977] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.287999] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.292557] usb 1-10: New USB device found, idVendor=0557, idProduct=7000, bcdDevice= 0.00 > [ 2.292559] usb 1-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.293488] hub 1-10:1.0: USB hub found > [ 2.293604] hub 1-10:1.0: 4 ports detected > [ 2.296162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.296181] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.314444] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 2.314463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c4a0e3a state to 00000000fc0cb429 > [ 2.314480] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 00000000fc0cb429 > [ 2.314494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a8e00a70 state to 00000000fc0cb429 > [ 2.314511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a8e00a70 > [ 2.314525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007f2e9b45 state to 00000000fc0cb429 > [ 2.314540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000007f2e9b45 > [ 2.314554] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 > [ 2.314568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 00000000fc0cb429 > [ 2.314581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f4491376 state to 00000000fc0cb429 > [ 2.314596] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f4491376 > [ 2.314609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009bdf158a state to 00000000fc0cb429 > [ 2.314623] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009bdf158a > [ 2.314636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003292b89f state to 00000000fc0cb429 > [ 2.314649] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 > [ 2.314663] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 > [ 2.314677] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d93e8df3 state to 00000000fc0cb429 > [ 2.314690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d93e8df3 > [ 2.314705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c4a0e3a > [ 2.314719] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 2.314734] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000309bb6f5 state to 00000000fc0cb429 > [ 2.314749] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [NOCRTC] > [ 2.314763] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [CRTC:51:pipe A] > [ 2.314776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 > [ 2.314791] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 2.314805] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000005b4f258 state to 00000000fc0cb429 > [ 2.314818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [NOCRTC] > [ 2.314832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [CRTC:72:pipe B] > [ 2.314846] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 > [ 2.314859] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 2.314872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003292b89f > [ 2.314886] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 2.314900] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 2.314915] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.314923] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.314930] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.314936] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.315024] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.315085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.315120] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 2.329803] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 2.329826] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 2.348527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.348550] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000df34b7b3 state to 000000006432a660 > [ 2.348569] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 > [ 2.348583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ed11a5b9 state to 000000006432a660 > [ 2.348600] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ed11a5b9 > [ 2.348615] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000f8d239cd state to 000000006432a660 > [ 2.348630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000f8d239cd > [ 2.348644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005f11c147 state to 000000006432a660 > [ 2.348661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 > [ 2.348674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000457aaa57 state to 000000006432a660 > [ 2.348689] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000457aaa57 > [ 2.348702] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b1ca1c71 state to 000000006432a660 > [ 2.348716] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b1ca1c71 > [ 2.348730] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b4343291 state to 000000006432a660 > [ 2.348743] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000067db6375 state to 000000006432a660 > [ 2.348758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000067db6375 > [ 2.348777] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.348791] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.348806] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000df34b7b3 > [ 2.348821] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.348836] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 > [ 2.348851] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] > [ 2.348865] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] > [ 2.348883] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005f11c147 > [ 2.348897] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.348911] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.348926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.348939] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.348954] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.348969] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.348982] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b4343291 > [ 2.348996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.349010] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.349026] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.349034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.349041] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.349048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.349141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.349203] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.349231] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.363033] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.363056] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.381721] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.381738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008ffba3f3 state to 00000000c6c933d1 > [ 2.381754] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 > [ 2.381767] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 > [ 2.381784] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 > [ 2.381798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 > [ 2.381813] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 > [ 2.381827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.381841] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 2.381853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.381868] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 > [ 2.381882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 2.381896] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 2.381909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.381922] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 > [ 2.381935] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab > [ 2.381948] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.381962] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 > [ 2.381976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008ffba3f3 > [ 2.381992] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.382007] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000046dc0413 state to 00000000c6c933d1 > [ 2.382021] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [NOCRTC] > [ 2.382035] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [CRTC:51:pipe A] > [ 2.382048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 > [ 2.382062] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.382075] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000002e396b94 state to 00000000c6c933d1 > [ 2.382089] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [NOCRTC] > [ 2.382101] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [CRTC:72:pipe B] > [ 2.382115] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 > [ 2.382129] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f > [ 2.382142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 > [ 2.382155] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.382169] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.382186] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.382194] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.382206] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.382212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.382288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.382348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.382376] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.396184] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.396207] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.414905] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.414925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003eec9b7 state to 0000000098df4bf3 > [ 2.414942] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.414957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fb96f9d3 state to 0000000098df4bf3 > [ 2.414973] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fb96f9d3 > [ 2.414988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005342f7e7 state to 0000000098df4bf3 > [ 2.415003] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005342f7e7 > [ 2.415020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 > [ 2.415034] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.415047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000026a13e4f state to 0000000098df4bf3 > [ 2.415062] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000026a13e4f > [ 2.415076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e81eafbe state to 0000000098df4bf3 > [ 2.415090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e81eafbe > [ 2.415103] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f101de7e state to 0000000098df4bf3 > [ 2.415123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 > [ 2.415137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a > [ 2.415150] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 > [ 2.415164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 > [ 2.415180] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003eec9b7 > [ 2.415194] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.415209] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009e77ee4b state to 0000000098df4bf3 > [ 2.415227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [NOCRTC] > [ 2.415241] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [CRTC:51:pipe A] > [ 2.415255] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe > [ 2.415269] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.415284] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006fd04029 state to 0000000098df4bf3 > [ 2.415298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [NOCRTC] > [ 2.415311] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [CRTC:72:pipe B] > [ 2.415328] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.415342] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 2.415355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f101de7e > [ 2.415369] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.415383] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.415399] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.415407] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.415414] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.415423] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.415506] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.415569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.415598] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.420197] usb 2-2: new SuperSpeed Gen 1 USB device number 3 using xhci_hcd > [ 2.429805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.429829] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.440080] usb 2-2: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 > [ 2.440081] usb 2-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.441055] hub 2-2:1.0: USB hub found > [ 2.441232] hub 2-2:1.0: 4 ports detected > [ 2.451314] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 2.451340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a6369fc8 state to 00000000fc0cb429 > [ 2.451359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 2.451375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000091b367b1 state to 00000000fc0cb429 > [ 2.451395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000091b367b1 > [ 2.451412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 00000000fc0cb429 > [ 2.451429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f > [ 2.451446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bf01569 state to 00000000fc0cb429 > [ 2.451462] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 > [ 2.451477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ab6fdf3f state to 00000000fc0cb429 > [ 2.451494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ab6fdf3f > [ 2.451510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 > [ 2.451526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b > [ 2.451543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 > [ 2.451559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 > [ 2.451575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 > [ 2.451591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 > [ 2.451607] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f > [ 2.451624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a6369fc8 > [ 2.451641] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 2.451660] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ee6ef05 state to 00000000fc0cb429 > [ 2.451677] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [NOCRTC] > [ 2.451693] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [CRTC:51:pipe A] > [ 2.451710] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bf01569 > [ 2.451726] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 2.451743] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009647804d state to 00000000fc0cb429 > [ 2.451760] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [NOCRTC] > [ 2.451784] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [CRTC:72:pipe B] > [ 2.451801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000dd2a82ac state to 00000000fc0cb429 > [ 2.451817] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000dd2a82ac > [ 2.451832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 > [ 2.451848] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 2.451865] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 2.451883] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.451892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.451900] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.451908] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.452011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.452082] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.452114] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 2.463087] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 2.463114] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 2.484902] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.484925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 > [ 2.484941] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 000000006432a660 > [ 2.484955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 > [ 2.484971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 > [ 2.484985] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 > [ 2.485000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f > [ 2.485015] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.485028] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 000000006432a660 > [ 2.485041] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.485055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 > [ 2.485067] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 > [ 2.485081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 > [ 2.485094] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.485106] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 > [ 2.485120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa > [ 2.485132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.485146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.485160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 > [ 2.485174] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.485189] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 000000006432a660 > [ 2.485203] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] > [ 2.485216] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] > [ 2.485229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 > [ 2.485243] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.485257] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 > [ 2.485270] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 2.485283] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 2.485297] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.485310] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.485322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 > [ 2.485336] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.485349] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.485365] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.485373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.485380] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.485386] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.485476] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.485536] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.485568] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.496321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.496343] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.514099] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.514115] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000086e6c525 state to 00000000c6c933d1 > [ 2.514130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 > [ 2.514143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000076facd10 state to 00000000c6c933d1 > [ 2.514159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000076facd10 > [ 2.514173] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000900779b1 state to 00000000c6c933d1 > [ 2.514187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000900779b1 > [ 2.514201] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.514214] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 2.514227] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 > [ 2.514241] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab > [ 2.514254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.514267] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 > [ 2.514281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 > [ 2.514293] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.514306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 > [ 2.514319] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.514332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 > [ 2.514346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000086e6c525 > [ 2.514359] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.514373] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000006978e08c state to 00000000c6c933d1 > [ 2.514389] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [NOCRTC] > [ 2.514402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [CRTC:51:pipe A] > [ 2.514415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 > [ 2.514429] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.514442] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009efdc675 state to 00000000c6c933d1 > [ 2.514455] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [NOCRTC] > [ 2.514467] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [CRTC:72:pipe B] > [ 2.514485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 > [ 2.514499] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 > [ 2.514511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f > [ 2.514523] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.514537] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.514551] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.514559] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.514566] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.514572] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.514659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.514717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.514743] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.529754] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.529779] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.550511] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.550530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c471465 state to 000000006432a660 > [ 2.550547] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 > [ 2.550562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059814b3a state to 000000006432a660 > [ 2.550581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059814b3a > [ 2.550597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bf357c4b state to 000000006432a660 > [ 2.550614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bf357c4b > [ 2.550629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d9e36170 state to 000000006432a660 > [ 2.550644] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 > [ 2.550658] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 000000006432a660 > [ 2.550675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a > [ 2.550690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000071f245df state to 000000006432a660 > [ 2.550705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000071f245df > [ 2.550720] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000074f436be state to 000000006432a660 > [ 2.550735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 000000006432a660 > [ 2.550750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e > [ 2.550765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.550780] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.550798] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c471465 > [ 2.550814] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.550831] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 > [ 2.550847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 2.550862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 2.550876] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d9e36170 > [ 2.550891] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.550907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.550922] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.550937] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.550953] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.550967] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.550981] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000074f436be > [ 2.550996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.551012] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.551029] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.551037] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.551045] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.551053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.551151] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.551217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.551247] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.563034] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.563060] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.567816] usb 1-11: new high-speed USB device number 4 using xhci_hcd > [ 2.582973] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.582995] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 > [ 2.583010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.583024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 > [ 2.583039] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe > [ 2.583052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 > [ 2.583066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 > [ 2.583080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 2.583096] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.583108] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 > [ 2.583121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 > [ 2.583133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 > [ 2.583146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f > [ 2.583159] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 > [ 2.583171] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 2.583184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 > [ 2.583197] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 > [ 2.583210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e > [ 2.583224] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f > [ 2.583237] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.583251] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 0000000098df4bf3 > [ 2.583265] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] > [ 2.583278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] > [ 2.583290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 2.583303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.583317] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 > [ 2.583329] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] > [ 2.583342] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] > [ 2.583355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.583368] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 2.583380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c > [ 2.583392] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.583406] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.583424] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.583432] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.583438] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.583444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.583528] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.583585] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.583612] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.596477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.596495] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.610890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.610906] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000382acb58 state to 000000001ff947e6 > [ 2.610919] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 000000001ff947e6 > [ 2.610930] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009a9a5a77 state to 000000001ff947e6 > [ 2.610943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009a9a5a77 > [ 2.610955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d365bfc5 state to 000000001ff947e6 > [ 2.610966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d365bfc5 > [ 2.610978] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c23288bf state to 000000001ff947e6 > [ 2.610989] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 000000001ff947e6 > [ 2.611000] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000010a446a8 state to 000000001ff947e6 > [ 2.611012] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000010a446a8 > [ 2.611022] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e536e28a state to 000000001ff947e6 > [ 2.611033] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e536e28a > [ 2.611044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fac02d29 state to 000000001ff947e6 > [ 2.611054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e23783d2 state to 000000001ff947e6 > [ 2.611065] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e23783d2 > [ 2.611075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000009ecd9d0a state to 000000001ff947e6 > [ 2.611086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000009ecd9d0a > [ 2.611097] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000382acb58 > [ 2.611109] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.611121] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000949ef34b state to 000000001ff947e6 > [ 2.611132] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [NOCRTC] > [ 2.611143] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [CRTC:51:pipe A] > [ 2.611153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c23288bf > [ 2.611164] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.611175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000025f34563 state to 000000001ff947e6 > [ 2.611186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [NOCRTC] > [ 2.611196] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [CRTC:72:pipe B] > [ 2.611213] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 000000001ff947e6 > [ 2.611224] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b > [ 2.611234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fac02d29 > [ 2.611244] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.611255] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.611268] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.611274] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.611280] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.611285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.611363] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.611411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.611436] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.624544] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.624568] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.648394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.648422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 > [ 2.648448] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 > [ 2.648470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.648494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 > [ 2.648515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 > [ 2.648536] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 > [ 2.648557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.648577] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 > [ 2.648596] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.648618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 > [ 2.648637] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 > [ 2.648657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f > [ 2.648680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 > [ 2.648699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 > [ 2.648719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 > [ 2.648738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.648758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.648785] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa > [ 2.648805] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.648826] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 > [ 2.648848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] > [ 2.648867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] > [ 2.648892] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 > [ 2.648912] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.648933] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 > [ 2.648953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] > [ 2.648972] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] > [ 2.648999] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.649018] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.649037] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 > [ 2.649057] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.649077] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.649105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.649116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.649126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.649136] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.649258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.649348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.649388] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.663045] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.663078] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.695073] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.695099] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000046234f6 state to 0000000098df4bf3 > [ 2.695121] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.695139] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a35c929d state to 0000000098df4bf3 > [ 2.695164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a35c929d > [ 2.695189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 0000000098df4bf3 > [ 2.695210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 > [ 2.695229] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 > [ 2.695248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.695265] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 0000000098df4bf3 > [ 2.695284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f > [ 2.695303] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007f5e6213 state to 0000000098df4bf3 > [ 2.695322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007f5e6213 > [ 2.695340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053155f00 state to 0000000098df4bf3 > [ 2.695357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 > [ 2.695376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e > [ 2.695396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 2.695414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 > [ 2.695435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000046234f6 > [ 2.695454] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.695474] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 0000000098df4bf3 > [ 2.695494] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] > [ 2.695512] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] > [ 2.695531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d > [ 2.695550] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.695569] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 > [ 2.695587] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] > [ 2.695604] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] > [ 2.695623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.695641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 2.695658] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053155f00 > [ 2.695676] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.695695] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.695725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.695736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.695745] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.695755] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.695886] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.695968] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.696005] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.713154] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.713185] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.716173] usb 1-11: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 > [ 2.716176] usb 1-11: New USB device strings: Mfr=0, Product=0, SerialNumber=1 > [ 2.716179] usb 1-11: SerialNumber: DC0F18713FF2 > [ 2.717025] hub 1-11:1.0: USB hub found > [ 2.717053] hub 1-11:1.0: 4 ports detected > [ 2.744349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.744373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000098081998 state to 000000001ff947e6 > [ 2.744393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 > [ 2.744411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007284ebf4 state to 000000001ff947e6 > [ 2.744433] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007284ebf4 > [ 2.744451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000092bd7e4c state to 000000001ff947e6 > [ 2.744470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000092bd7e4c > [ 2.744488] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000687f38c3 state to 000000001ff947e6 > [ 2.744505] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003eebba06 state to 000000001ff947e6 > [ 2.744522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000072a9793c state to 000000001ff947e6 > [ 2.744540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000072a9793c > [ 2.744559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 000000001ff947e6 > [ 2.744577] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac > [ 2.744593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 000000001ff947e6 > [ 2.744609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 000000001ff947e6 > [ 2.744627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 > [ 2.744643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 000000001ff947e6 > [ 2.744660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c > [ 2.744678] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000098081998 > [ 2.744696] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.744715] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ebbd72c state to 000000001ff947e6 > [ 2.744734] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [NOCRTC] > [ 2.744751] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [CRTC:51:pipe A] > [ 2.744773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000687f38c3 > [ 2.744790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.744808] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001175f931 state to 000000001ff947e6 > [ 2.744825] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [NOCRTC] > [ 2.744842] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [CRTC:72:pipe B] > [ 2.744860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000053a23bd6 state to 000000001ff947e6 > [ 2.744877] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000053a23bd6 > [ 2.744893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e > [ 2.744911] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.744928] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.744948] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.744958] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.744969] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.744977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.745085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.745164] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.745209] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.757894] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.757923] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.781266] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.781290] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 > [ 2.781313] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 > [ 2.781332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 > [ 2.781353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 > [ 2.781371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 > [ 2.781390] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 > [ 2.781409] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 > [ 2.781426] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 > [ 2.781443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 > [ 2.781462] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 > [ 2.781478] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 > [ 2.781496] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd > [ 2.781514] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 > [ 2.781530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 > [ 2.781548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 > [ 2.781565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.781583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.781602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 > [ 2.781620] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.781639] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 > [ 2.781658] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] > [ 2.781675] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] > [ 2.781694] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 > [ 2.781712] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.781729] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.781747] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.781764] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.781782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.781800] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.781816] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 > [ 2.781833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.781851] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.781869] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.781879] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.781888] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.781897] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.782005] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.782084] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.782120] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.796434] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.796463] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.815843] usb 1-10.1: new low-speed USB device number 5 using xhci_hcd > [ 2.830298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.830323] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dd33f136 state to 00000000c6c933d1 > [ 2.830358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 > [ 2.830378] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 > [ 2.830401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 > [ 2.830422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008ffba3f3 state to 00000000c6c933d1 > [ 2.830443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008ffba3f3 > [ 2.830466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.830485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 2.830504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.830525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 > [ 2.830544] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 2.830564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 2.830583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.830601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 > [ 2.830621] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab > [ 2.830640] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.830659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 > [ 2.830684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000dd33f136 > [ 2.830704] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.830725] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 > [ 2.830746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] > [ 2.830766] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] > [ 2.830788] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 > [ 2.830808] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.830828] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 > [ 2.830848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] > [ 2.830867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] > [ 2.830890] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 > [ 2.830910] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 > [ 2.830928] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 > [ 2.830948] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.830968] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.831004] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.831015] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.831025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.831035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.831156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.831242] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.831281] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.846410] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.846458] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.877085] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.877104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 > [ 2.877120] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.877135] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 > [ 2.877153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f > [ 2.877167] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 > [ 2.877181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 > [ 2.877195] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 2.877209] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.877222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 > [ 2.877236] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 2.877248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 > [ 2.877262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 2.877275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 > [ 2.877287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 > [ 2.877301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 > [ 2.877313] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 > [ 2.877327] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a > [ 2.877344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c > [ 2.877357] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.877372] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 0000000098df4bf3 > [ 2.877386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] > [ 2.877399] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] > [ 2.877412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 2.877426] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.877439] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 > [ 2.877452] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] > [ 2.877465] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] > [ 2.877479] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.877492] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 2.877504] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f > [ 2.877517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.877531] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.877553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.877561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.877571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.877577] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.877659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.877719] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.877747] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.891314] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.891333] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.906312] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.906333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000918919b3 state to 000000001ff947e6 > [ 2.906347] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 000000001ff947e6 > [ 2.906358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000005a00270 state to 000000001ff947e6 > [ 2.906372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000005a00270 > [ 2.906384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000512c7fb3 state to 000000001ff947e6 > [ 2.906396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000512c7fb3 > [ 2.906408] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000063c0bfb2 state to 000000001ff947e6 > [ 2.906419] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 000000001ff947e6 > [ 2.906433] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004acae8d3 state to 000000001ff947e6 > [ 2.906445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004acae8d3 > [ 2.906456] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 000000001ff947e6 > [ 2.906468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 > [ 2.906479] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 000000001ff947e6 > [ 2.906489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a4c468ad state to 000000001ff947e6 > [ 2.906500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a4c468ad > [ 2.906511] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000320b468c state to 000000001ff947e6 > [ 2.906522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000320b468c > [ 2.906542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000918919b3 > [ 2.906555] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.906568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ba4c5dc3 state to 000000001ff947e6 > [ 2.906580] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [NOCRTC] > [ 2.906591] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [CRTC:51:pipe A] > [ 2.906602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000063c0bfb2 > [ 2.906613] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.906625] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ae0223f3 state to 000000001ff947e6 > [ 2.906636] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [NOCRTC] > [ 2.906646] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [CRTC:72:pipe B] > [ 2.906661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 000000001ff947e6 > [ 2.906672] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 > [ 2.906682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d > [ 2.906693] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.906705] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.906718] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.906725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.906731] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.906736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.906813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.906863] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.906886] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.913164] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.913183] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.933406] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.933430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 > [ 2.933451] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 > [ 2.933468] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 > [ 2.933490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 > [ 2.933508] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 > [ 2.933527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f > [ 2.933545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.933563] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 > [ 2.933583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.933601] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 > [ 2.933618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 > [ 2.933636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 > [ 2.933653] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.933670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 > [ 2.933687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa > [ 2.933705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.933723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.933741] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 > [ 2.933759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.933778] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 > [ 2.933800] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] > [ 2.933818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] > [ 2.933836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 > [ 2.933853] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.933871] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 > [ 2.933888] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 2.933905] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 2.933923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.933940] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.933957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 > [ 2.933974] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.933992] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.934021] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.934031] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.934039] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.934048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.934156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.934235] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.934270] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.945099] usb 1-10.1: New USB device found, idVendor=0557, idProduct=2419, bcdDevice= 1.00 > [ 2.945102] usb 1-10.1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.946202] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.946230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.969637] hid: raw HID events driver (C) Jiri Kosina > [ 2.980218] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.980244] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 > [ 2.980267] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 > [ 2.980286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 > [ 2.980309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 > [ 2.980330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000097efae80 state to 00000000c6c933d1 > [ 2.980351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000097efae80 > [ 2.980372] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.980391] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 2.980410] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 > [ 2.980431] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab > [ 2.980449] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.980470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 > [ 2.980489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 > [ 2.980507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.980527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 > [ 2.980547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.980566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 > [ 2.980587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 > [ 2.980607] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.980628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 > [ 2.980650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] > [ 2.980670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] > [ 2.980690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 > [ 2.980709] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.980728] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 > [ 2.980748] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] > [ 2.980767] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] > [ 2.980792] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 > [ 2.980812] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 > [ 2.980830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f > [ 2.980850] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.980871] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.980898] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.980910] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.980920] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.980929] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.981048] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.981050] usbcore: registered new interface driver usbhid > [ 2.981135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.981135] usbhid: USB HID core driver > [ 2.981182] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.983750] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.0/0003:0557:2419.0001/input/input4 > [ 2.996172] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.996195] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.016364] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 3.016380] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 > [ 3.016393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 > [ 3.016405] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 > [ 3.016419] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be > [ 3.016432] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 > [ 3.016445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df > [ 3.016458] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 > [ 3.016470] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 > [ 3.016481] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 > [ 3.016494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 > [ 3.016507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 > [ 3.016519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b > [ 3.016531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 > [ 3.016543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 > [ 3.016556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 > [ 3.016568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 3.016580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 3.016593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e > [ 3.016606] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 3.016619] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 > [ 3.016632] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 3.016644] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 3.016657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a > [ 3.016669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 3.016682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 3.016694] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 3.016706] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 3.016719] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 3.016731] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 3.016743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a > [ 3.016755] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 3.016767] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 3.016778] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.016785] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.016791] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.016798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.016860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.016917] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.016940] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 3.020983] scsi 4:0:0:0: Direct-Access Generic Compact Flash 0.00 PQ: 0 ANSI: 2 > [ 3.021765] scsi 4:0:0:1: Direct-Access Generic SD/MMC 0.00 PQ: 0 ANSI: 2 > [ 3.022194] scsi 4:0:0:2: Direct-Access Generic microSD 0.00 PQ: 0 ANSI: 2 > [ 3.022768] scsi 4:0:0:3: Direct-Access Generic MS/MS-PRO 0.00 PQ: 0 ANSI: 2 > [ 3.023138] scsi 4:0:0:4: Direct-Access Generic SM/xD-Picture 0.00 PQ: 0 ANSI: 2 > [ 3.029581] sd 1:0:0:0: [sda] 1000215216 512-byte logical blocks: (512 GB/477 GiB) > [ 3.029588] sd 1:0:0:0: [sda] Write Protect is off > [ 3.029589] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00 > [ 3.029597] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA > [ 3.043978] hid-generic 0003:0557:2419.0001: input,hidraw0: USB HID v1.00 Keyboard [HID 0557:2419] on usb-0000:00:14.0-10.1/input0 > [ 3.044084] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.1/0003:0557:2419.0002/input/input5 > [ 3.044277] hid-generic 0003:0557:2419.0002: input,hidraw1: USB HID v1.00 Mouse [HID 0557:2419] on usb-0000:00:14.0-10.1/input1 > [ 3.044891] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 3.044908] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 > [ 3.044928] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 3.044945] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007b36813f state to 00000000c29bd936 > [ 3.044964] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ec014e4 state to 00000000c29bd936 > [ 3.044984] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000555d146c state to 00000000c29bd936 > [ 3.045005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000555d146c > [ 3.045023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b2cdb294 state to 00000000c29bd936 > [ 3.045041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b2cdb294 > [ 3.045060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000053454233 state to 00000000c29bd936 > [ 3.045079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a746018c state to 00000000c29bd936 > [ 3.045097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 > [ 3.045113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 > [ 3.045123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b5f6abf5 state to 00000000c29bd936 > [ 3.045134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b5f6abf5 > [ 3.045147] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000c775be6 state to 00000000c29bd936 > [ 3.045156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005d690c84 state to 00000000c29bd936 > [ 3.045167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005d690c84 > [ 3.045177] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000122a804f state to 00000000c29bd936 > [ 3.045188] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000122a804f > [ 3.045200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007b36813f > [ 3.045211] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 > [ 3.045222] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004edc31e9 state to 00000000c29bd936 > [ 3.045238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [NOCRTC] > [ 3.045256] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [CRTC:51:pipe A] > [ 3.045274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000053454233 > [ 3.045294] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 > [ 3.045312] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005d1fe044 state to 00000000c29bd936 > [ 3.045325] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [NOCRTC] > [ 3.045335] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [CRTC:72:pipe B] > [ 3.045350] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ef13faa state to 00000000c29bd936 > [ 3.045360] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ef13faa > [ 3.045369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000c775be6 > [ 3.045380] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 > [ 3.045390] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 > [ 3.045403] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.045410] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.045415] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.045420] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.045496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.045543] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.045577] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 > [ 3.052647] sd 4:0:0:4: [sdf] Attached SCSI removable disk > [ 3.054117] sda: sda1 sda2 < sda5 > > [ 3.054604] sd 1:0:0:0: [sda] supports TCG Opal > [ 3.054605] sd 1:0:0:0: [sda] Attached SCSI disk > [ 3.056264] sd 4:0:0:3: [sde] Attached SCSI removable disk > [ 3.057329] sd 4:0:0:1: [sdc] Attached SCSI removable disk > [ 3.057645] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 > [ 3.057661] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 > [ 3.060799] sd 4:0:0:0: [sdb] Attached SCSI removable disk > [ 3.071802] usb 1-12: new high-speed USB device number 6 using xhci_hcd > [ 3.072920] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 > [ 3.072942] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fac02d29 state to 00000000ffbe70d8 > [ 3.072961] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000ffbe70d8 > [ 3.072980] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ecd9d0a state to 00000000ffbe70d8 > [ 3.072992] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ecd9d0a > [ 3.073004] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000098081998 state to 00000000ffbe70d8 > [ 3.073017] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000098081998 > [ 3.073035] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007284ebf4 state to 00000000ffbe70d8 > [ 3.073054] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 > [ 3.073071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000092bd7e4c state to 00000000ffbe70d8 > [ 3.073089] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000092bd7e4c > [ 3.073105] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 00000000ffbe70d8 > [ 3.073123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac > [ 3.073140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 00000000ffbe70d8 > [ 3.073157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 00000000ffbe70d8 > [ 3.073175] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 > [ 3.073189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 00000000ffbe70d8 > [ 3.073199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c > [ 3.073211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000fac02d29 > [ 3.073222] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 > [ 3.073233] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000be46149d state to 00000000ffbe70d8 > [ 3.073244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [NOCRTC] > [ 3.073254] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [CRTC:51:pipe A] > [ 3.073265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000007284ebf4 > [ 3.073276] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 > [ 3.073286] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000068a1fb01 state to 00000000ffbe70d8 > [ 3.073297] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [NOCRTC] > [ 3.073307] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [CRTC:72:pipe B] > [ 3.073318] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000cf23fbdd state to 00000000ffbe70d8 > [ 3.073328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000cf23fbdd > [ 3.073338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e > [ 3.073348] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 > [ 3.073359] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 > [ 3.073371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.073377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.073382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.073387] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.073458] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.073505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.073529] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 > [ 3.073552] sd 4:0:0:2: [sdd] Attached SCSI removable disk > [ 3.079604] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 > [ 3.079650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 > [ 3.108427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 > [ 3.108443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000122a804f state to 00000000c29bd936 > [ 3.108457] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000228f716d state to 00000000c29bd936 > [ 3.108470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000005d690c84 state to 00000000c29bd936 > [ 3.108486] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000005d690c84 > [ 3.108499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000c775be6 state to 00000000c29bd936 > [ 3.108513] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000c775be6 > [ 3.108527] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b5f6abf5 state to 00000000c29bd936 > [ 3.108540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 > [ 3.108552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 > [ 3.108566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 > [ 3.108578] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053454233 state to 00000000c29bd936 > [ 3.108592] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053454233 > [ 3.108604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b2cdb294 state to 00000000c29bd936 > [ 3.108616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000555d146c state to 00000000c29bd936 > [ 3.108630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000555d146c > [ 3.108642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007b36813f state to 00000000c29bd936 > [ 3.108655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007b36813f > [ 3.108668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000122a804f > [ 3.108682] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 > [ 3.108695] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eee09833 state to 00000000c29bd936 > [ 3.108709] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [NOCRTC] > [ 3.108722] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [CRTC:51:pipe A] > [ 3.108736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b5f6abf5 > [ 3.108749] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 > [ 3.108761] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000898e3e27 state to 00000000c29bd936 > [ 3.108774] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [NOCRTC] > [ 3.108787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [CRTC:72:pipe B] > [ 3.108801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d0e256d1 state to 00000000c29bd936 > [ 3.108814] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d0e256d1 > [ 3.108826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b2cdb294 > [ 3.108839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 > [ 3.108865] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 > [ 3.108875] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.108882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.108887] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.108892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.108956] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.109003] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.109025] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 > [ 3.124527] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 > [ 3.124544] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 > [ 3.137517] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a6b51f > [ 3.137531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000012530223 state to 0000000073a6b51f > [ 3.137543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000009be30044 state to 0000000073a6b51f > [ 3.137555] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ffe00c37 state to 0000000073a6b51f > [ 3.137567] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ffe00c37 > [ 3.137577] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000023a9a422 state to 0000000073a6b51f > [ 3.137587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000023a9a422 > [ 3.137598] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bdb8d82 state to 0000000073a6b51f > [ 3.137607] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 0000000073a6b51f > [ 3.137617] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e3147659 state to 0000000073a6b51f > [ 3.137627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e3147659 > [ 3.137636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000004825b29a state to 0000000073a6b51f > [ 3.137646] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000004825b29a > [ 3.137657] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005788f64c state to 0000000073a6b51f > [ 3.137667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000032e38a43 state to 0000000073a6b51f > [ 3.137676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000032e38a43 > [ 3.137685] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000089408e5f state to 0000000073a6b51f > [ 3.137695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000089408e5f > [ 3.137705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000012530223 > [ 3.137715] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000073a6b51f > [ 3.137726] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000748c93aa state to 0000000073a6b51f > [ 3.137737] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [NOCRTC] > [ 3.137746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [CRTC:51:pipe A] > [ 3.137760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bdb8d82 > [ 3.137769] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000073a6b51f > [ 3.137779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f1b6922b state to 0000000073a6b51f > [ 3.137789] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [NOCRTC] > [ 3.137798] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [CRTC:72:pipe B] > [ 3.137808] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ad566469 state to 0000000073a6b51f > [ 3.137818] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ad566469 > [ 3.137827] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005788f64c > [ 3.137836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000073a6b51f > [ 3.137846] [drm:drm_atomic_check_only [drm]] checking 0000000073a6b51f > [ 3.137866] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.137872] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.137882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.137886] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.137944] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.137988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.138008] [drm:drm_atomic_commit [drm]] committing 0000000073a6b51f > [ 3.146528] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a6b51f > [ 3.146545] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a6b51f > [ 3.157850] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 > [ 3.157860] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002f4e481a state to 00000000619b20f5 > [ 3.157869] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001b7eae74 state to 00000000619b20f5 > [ 3.157877] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000025544875 state to 00000000619b20f5 > [ 3.157886] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000025544875 > [ 3.157894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008c95634f state to 00000000619b20f5 > [ 3.157902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008c95634f > [ 3.157910] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000483335fe state to 00000000619b20f5 > [ 3.157917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ae874d06 state to 00000000619b20f5 > [ 3.157925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 00000000619b20f5 > [ 3.157932] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 3.157941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000865de88c state to 00000000619b20f5 > [ 3.157948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000865de88c > [ 3.157955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001c64fec3 state to 00000000619b20f5 > [ 3.157962] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001726835f state to 00000000619b20f5 > [ 3.157970] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001726835f > [ 3.157977] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006011267c state to 00000000619b20f5 > [ 3.157984] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006011267c > [ 3.157993] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002f4e481a > [ 3.158001] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 > [ 3.158009] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 00000000619b20f5 > [ 3.158017] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] > [ 3.158024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] > [ 3.158031] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000483335fe > [ 3.158039] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 > [ 3.158046] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000b34fddb1 state to 00000000619b20f5 > [ 3.158054] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [NOCRTC] > [ 3.158061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [CRTC:72:pipe B] > [ 3.158069] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000904bdb49 state to 00000000619b20f5 > [ 3.158076] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000904bdb49 > [ 3.158083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001c64fec3 > [ 3.158090] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 > [ 3.158098] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 > [ 3.158108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.158112] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.158116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.158119] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.158180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.158213] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.158229] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 > [ 3.174683] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 > [ 3.174697] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 > [ 3.186485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.186502] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f11c147 state to 00000000f3200e59 > [ 3.186513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 00000000f3200e59 > [ 3.186523] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000457aaa57 state to 00000000f3200e59 > [ 3.186534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000457aaa57 > [ 3.186545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 00000000f3200e59 > [ 3.186555] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 > [ 3.186565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b4343291 state to 00000000f3200e59 > [ 3.186575] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 00000000f3200e59 > [ 3.186584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000067db6375 state to 00000000f3200e59 > [ 3.186594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000067db6375 > [ 3.186604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ed11a5b9 state to 00000000f3200e59 > [ 3.186614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ed11a5b9 > [ 3.186623] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df34b7b3 state to 00000000f3200e59 > [ 3.186632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e5b7e29b state to 00000000f3200e59 > [ 3.186641] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e5b7e29b > [ 3.186650] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001c471465 state to 00000000f3200e59 > [ 3.186659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001c471465 > [ 3.186670] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000005f11c147 > [ 3.186680] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.186690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000140b0238 state to 00000000f3200e59 > [ 3.186704] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [NOCRTC] > [ 3.186714] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [CRTC:51:pipe A] > [ 3.186723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b4343291 > [ 3.186733] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.186742] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001ddd4fdd state to 00000000f3200e59 > [ 3.186752] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [NOCRTC] > [ 3.186761] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [CRTC:72:pipe B] > [ 3.186772] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 00000000f3200e59 > [ 3.186781] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 3.186790] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df34b7b3 > [ 3.186800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.186810] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.186829] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.186834] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.186839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.186844] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.186901] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.186949] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.186968] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.196452] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.196472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.216790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 > [ 3.216813] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000063c0bfb2 state to 00000000ffbe70d8 > [ 3.216833] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 00000000ffbe70d8 > [ 3.216851] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000918919b3 state to 00000000ffbe70d8 > [ 3.216872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000918919b3 > [ 3.216889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000005a00270 state to 00000000ffbe70d8 > [ 3.216907] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000005a00270 > [ 3.216924] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000512c7fb3 state to 00000000ffbe70d8 > [ 3.216940] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 > [ 3.216956] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018dbb82d state to 00000000ffbe70d8 > [ 3.216974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018dbb82d > [ 3.216990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 > [ 3.217006] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 > [ 3.217023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a4c468ad state to 00000000ffbe70d8 > [ 3.217038] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000320b468c state to 00000000ffbe70d8 > [ 3.217055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000320b468c > [ 3.217074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000063ec03c state to 00000000ffbe70d8 > [ 3.217090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000063ec03c > [ 3.217108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000063c0bfb2 > [ 3.217125] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 > [ 3.217143] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d05a5c4c state to 00000000ffbe70d8 > [ 3.217161] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [NOCRTC] > [ 3.217177] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [CRTC:51:pipe A] > [ 3.217193] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000512c7fb3 > [ 3.217210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 > [ 3.217227] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000fc47d714 state to 00000000ffbe70d8 > [ 3.217243] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [NOCRTC] > [ 3.217259] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [CRTC:72:pipe B] > [ 3.217276] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 > [ 3.217293] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b > [ 3.217308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a4c468ad > [ 3.217325] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 > [ 3.217342] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 > [ 3.217360] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.217371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.217382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.217390] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.217495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.217569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.217604] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 > [ 3.220944] usb 1-12: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 > [ 3.220946] usb 1-12: New USB device strings: Mfr=0, Product=0, SerialNumber=1 > [ 3.220948] usb 1-12: SerialNumber: CD0F18513FF2 > [ 3.221863] hub 1-12:1.0: USB hub found > [ 3.221920] hub 1-12:1.0: 4 ports detected > [ 3.229639] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 > [ 3.229666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 > [ 3.259936] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 > [ 3.259967] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007835ad2c state to 00000000c29bd936 > [ 3.259995] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000c29bd936 > [ 3.260020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a0e4907f state to 00000000c29bd936 > [ 3.260049] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a0e4907f > [ 3.260075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c342e8b6 state to 00000000c29bd936 > [ 3.260102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c342e8b6 > [ 3.260127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f85c23ef state to 00000000c29bd936 > [ 3.260151] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 > [ 3.260174] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e025482e state to 00000000c29bd936 > [ 3.260200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e025482e > [ 3.260224] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000fcc8f6c state to 00000000c29bd936 > [ 3.260249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000000fcc8f6c > [ 3.260275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000093fc8e4 state to 00000000c29bd936 > [ 3.260299] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005f84ed88 state to 00000000c29bd936 > [ 3.260324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005f84ed88 > [ 3.260348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006115325a state to 00000000c29bd936 > [ 3.260373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006115325a > [ 3.260399] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007835ad2c > [ 3.260425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 > [ 3.260452] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000093f6ce9d state to 00000000c29bd936 > [ 3.260479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [NOCRTC] > [ 3.260503] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [CRTC:51:pipe A] > [ 3.260528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f85c23ef > [ 3.260552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 > [ 3.260578] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000074011bcd state to 00000000c29bd936 > [ 3.260602] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [NOCRTC] > [ 3.260626] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [CRTC:72:pipe B] > [ 3.260651] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000c29bd936 > [ 3.260677] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d > [ 3.260700] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000093fc8e4 > [ 3.260725] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 > [ 3.260750] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 > [ 3.260776] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.260790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.260802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.260815] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.260951] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.261061] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.261109] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 > [ 3.274626] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 > [ 3.274674] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 > [ 3.299821] usb 1-11.2: new full-speed USB device number 7 using xhci_hcd > [ 3.303479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006379f080 > [ 3.303499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000559c57fd state to 000000006379f080 > [ 3.303517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e59c9ea1 state to 000000006379f080 > [ 3.303532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fdc091c8 state to 000000006379f080 > [ 3.303551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fdc091c8 > [ 3.303572] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a9473c9b state to 000000006379f080 > [ 3.303588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a9473c9b > [ 3.303604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000089408e5f state to 000000006379f080 > [ 3.303618] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 000000006379f080 > [ 3.303632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000032e38a43 state to 000000006379f080 > [ 3.303648] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000032e38a43 > [ 3.303662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005788f64c state to 000000006379f080 > [ 3.303677] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005788f64c > [ 3.303691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000004825b29a state to 000000006379f080 > [ 3.303705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e3147659 state to 000000006379f080 > [ 3.303720] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e3147659 > [ 3.303734] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bdb8d82 state to 000000006379f080 > [ 3.303750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bdb8d82 > [ 3.303766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000559c57fd > [ 3.303790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006379f080 > [ 3.303807] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000000e02d6ba state to 000000006379f080 > [ 3.303835] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [NOCRTC] > [ 3.303847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [CRTC:51:pipe A] > [ 3.303860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000089408e5f > [ 3.303872] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006379f080 > [ 3.303886] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f298f57c state to 000000006379f080 > [ 3.303898] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [NOCRTC] > [ 3.303910] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [CRTC:72:pipe B] > [ 3.303923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000002aa6a9f8 state to 000000006379f080 > [ 3.303935] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000002aa6a9f8 > [ 3.303947] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000004825b29a > [ 3.303959] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006379f080 > [ 3.303971] [drm:drm_atomic_check_only [drm]] checking 000000006379f080 > [ 3.304000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.304007] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.304013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.304019] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.304102] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.304157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.304182] [drm:drm_atomic_commit [drm]] committing 000000006379f080 > [ 3.313100] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006379f080 > [ 3.313118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006379f080 > [ 3.326983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 > [ 3.326998] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000515dc00f state to 00000000619b20f5 > [ 3.327010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b7f89a8d state to 00000000619b20f5 > [ 3.327021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008cab647d state to 00000000619b20f5 > [ 3.327036] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008cab647d > [ 3.327047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 00000000619b20f5 > [ 3.327058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 > [ 3.327071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a35c929d state to 00000000619b20f5 > [ 3.327081] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000347fbd12 state to 00000000619b20f5 > [ 3.327091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000046234f6 state to 00000000619b20f5 > [ 3.327102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000046234f6 > [ 3.327112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053155f00 state to 00000000619b20f5 > [ 3.327122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053155f00 > [ 3.327132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f3527d8e state to 00000000619b20f5 > [ 3.327141] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 00000000619b20f5 > [ 3.327152] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 > [ 3.327163] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000022fc4ece state to 00000000619b20f5 > [ 3.327173] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000022fc4ece > [ 3.327184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000515dc00f > [ 3.327195] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 > [ 3.327206] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 00000000619b20f5 > [ 3.327217] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] > [ 3.327227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] > [ 3.327238] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000a35c929d > [ 3.327248] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 > [ 3.327258] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009b609533 state to 00000000619b20f5 > [ 3.327268] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [NOCRTC] > [ 3.327278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [CRTC:72:pipe B] > [ 3.327289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 > [ 3.327299] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce > [ 3.327308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f3527d8e > [ 3.327318] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 > [ 3.327329] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 > [ 3.327341] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.327346] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.327352] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.327356] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.327430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.327475] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.327501] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 > [ 3.341307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 > [ 3.341359] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 > [ 3.379822] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.379844] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 00000000f3200e59 > [ 3.379864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000f3200e59 > [ 3.379881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000f3200e59 > [ 3.379901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b > [ 3.379920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000f3200e59 > [ 3.379938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 > [ 3.379955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 00000000f3200e59 > [ 3.379972] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 > [ 3.379988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000071f245df state to 00000000f3200e59 > [ 3.380005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000071f245df > [ 3.380021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000074f436be state to 00000000f3200e59 > [ 3.380038] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000074f436be > [ 3.380054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000041c6228e state to 00000000f3200e59 > [ 3.380069] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 00000000f3200e59 > [ 3.380086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d > [ 3.380101] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001f82d691 state to 00000000f3200e59 > [ 3.380117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001f82d691 > [ 3.380135] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a > [ 3.380153] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.380174] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ce20e5c8 state to 00000000f3200e59 > [ 3.380192] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [NOCRTC] > [ 3.380208] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [CRTC:51:pipe A] > [ 3.380225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a > [ 3.380242] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.380263] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001b5c4b62 state to 00000000f3200e59 > [ 3.380279] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [NOCRTC] > [ 3.380295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [CRTC:72:pipe B] > [ 3.380312] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 00000000f3200e59 > [ 3.380328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 3.380344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000041c6228e > [ 3.380360] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.380376] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.380402] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.380411] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.380419] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.380427] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.380529] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.380604] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.380646] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.396469] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.396503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.410062] usb 1-11.2: New USB device found, idVendor=17ef, idProduct=6047, bcdDevice= 3.00 > [ 3.410064] usb 1-11.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 > [ 3.410065] usb 1-11.2: Product: ThinkPad Compact USB Keyboard with TrackPoint > [ 3.410067] usb 1-11.2: Manufacturer: Lenovo > [ 3.418473] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 > [ 3.418496] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001090afab state to 00000000ffbe70d8 > [ 3.418515] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000053a23bd6 state to 00000000ffbe70d8 > [ 3.418532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028cdc562 state to 00000000ffbe70d8 > [ 3.418552] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028cdc562 > [ 3.418574] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000063ec03c state to 00000000ffbe70d8 > [ 3.418593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000063ec03c > [ 3.418610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000320b468c state to 00000000ffbe70d8 > [ 3.418627] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a4f0e9bc state to 00000000ffbe70d8 > [ 3.418642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000a4c468ad state to 00000000ffbe70d8 > [ 3.418660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000a4c468ad > [ 3.418680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 > [ 3.418697] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 > [ 3.418713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 00000000ffbe70d8 > [ 3.418728] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000512c7fb3 state to 00000000ffbe70d8 > [ 3.418745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000512c7fb3 > [ 3.418761] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000005a00270 state to 00000000ffbe70d8 > [ 3.418778] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000005a00270 > [ 3.418800] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001090afab > [ 3.418817] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 > [ 3.418835] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001175f931 state to 00000000ffbe70d8 > [ 3.418853] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [NOCRTC] > [ 3.418869] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [CRTC:51:pipe A] > [ 3.418888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000320b468c > [ 3.418905] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 > [ 3.418922] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ebbd72c state to 00000000ffbe70d8 > [ 3.418938] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [NOCRTC] > [ 3.418953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [CRTC:72:pipe B] > [ 3.418971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 > [ 3.418987] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b > [ 3.419002] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d > [ 3.419018] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 > [ 3.419035] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 > [ 3.419053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.419062] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.419070] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.419078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.419184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.419258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.419291] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 > [ 3.425539] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.0/0003:17EF:6047.0003/input/input6 > [ 3.429543] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 > [ 3.429570] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 > [ 3.451015] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.451031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008af22ea7 state to 00000000c6c933d1 > [ 3.451046] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 > [ 3.451060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 > [ 3.451076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be > [ 3.451089] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002a1c343e state to 00000000c6c933d1 > [ 3.451104] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002a1c343e > [ 3.451117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f7870136 state to 00000000c6c933d1 > [ 3.451130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 3.451142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ad384e88 state to 00000000c6c933d1 > [ 3.451156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ad384e88 > [ 3.451172] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008fde4998 state to 00000000c6c933d1 > [ 3.451186] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008fde4998 > [ 3.451198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000071cce0a state to 00000000c6c933d1 > [ 3.451210] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000007ba2cc3a state to 00000000c6c933d1 > [ 3.451223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000007ba2cc3a > [ 3.451236] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac0b8286 state to 00000000c6c933d1 > [ 3.451249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac0b8286 > [ 3.451262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008af22ea7 > [ 3.451280] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.451294] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eb0da826 state to 00000000c6c933d1 > [ 3.451308] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [NOCRTC] > [ 3.451321] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [CRTC:51:pipe A] > [ 3.451334] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f7870136 > [ 3.451347] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.451361] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 > [ 3.451373] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] > [ 3.451386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] > [ 3.451399] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 > [ 3.451412] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 > [ 3.451425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000071cce0a > [ 3.451438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.451451] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.451465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.451473] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.451481] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.451487] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.451560] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.451617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.451643] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.463098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.463116] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.478096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 > [ 3.478112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001726835f state to 00000000619b20f5 > [ 3.478125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000be800543 state to 00000000619b20f5 > [ 3.478137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c64fec3 state to 00000000619b20f5 > [ 3.478150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c64fec3 > [ 3.478162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000865de88c state to 00000000619b20f5 > [ 3.478174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000865de88c > [ 3.478186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000000fcc975 state to 00000000619b20f5 > [ 3.478197] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000068c99925 state to 00000000619b20f5 > [ 3.478209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000483335fe state to 00000000619b20f5 > [ 3.478220] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000483335fe > [ 3.478231] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008c95634f state to 00000000619b20f5 > [ 3.478243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008c95634f > [ 3.478254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000025544875 state to 00000000619b20f5 > [ 3.478264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 00000000619b20f5 > [ 3.478276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a > [ 3.478286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f101de7e state to 00000000619b20f5 > [ 3.478297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f101de7e > [ 3.478309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001726835f > [ 3.478321] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 > [ 3.478334] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 00000000619b20f5 > [ 3.478346] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] > [ 3.478357] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] > [ 3.478368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000000fcc975 > [ 3.478379] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 > [ 3.478390] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009e77ee4b state to 00000000619b20f5 > [ 3.478402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [NOCRTC] > [ 3.478412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [CRTC:72:pipe B] > [ 3.478425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 > [ 3.478436] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce > [ 3.478446] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000025544875 > [ 3.478457] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 > [ 3.478469] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 > [ 3.478482] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.478488] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.478494] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.478500] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.478579] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.478630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.478659] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 > [ 3.484276] lenovo 0003:17EF:6047.0003: input,hidraw2: USB HID v1.00 Keyboard [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input0 > [ 3.484522] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.1/0003:17EF:6047.0004/input/input7 > [ 3.491321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 > [ 3.491337] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 > [ 3.504241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 3.504253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015cf0577 state to 00000000fc0cb429 > [ 3.504264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 > [ 3.504273] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003292b89f state to 00000000fc0cb429 > [ 3.504285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003292b89f > [ 3.504294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009bdf158a state to 00000000fc0cb429 > [ 3.504305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009bdf158a > [ 3.504315] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 > [ 3.504324] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 3.504333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007f2e9b45 state to 00000000fc0cb429 > [ 3.504342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007f2e9b45 > [ 3.504356] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 > [ 3.504366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b > [ 3.504375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005fe5cc2f state to 00000000fc0cb429 > [ 3.504384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000091b367b1 state to 00000000fc0cb429 > [ 3.504393] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000091b367b1 > [ 3.504402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000a6369fc8 state to 00000000fc0cb429 > [ 3.504411] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000a6369fc8 > [ 3.504422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015cf0577 > [ 3.504431] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 3.504443] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000bd54c871 state to 00000000fc0cb429 > [ 3.504453] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [NOCRTC] > [ 3.504462] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [CRTC:51:pipe A] > [ 3.504472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 > [ 3.504481] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 3.504491] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000309bb6f5 state to 00000000fc0cb429 > [ 3.504500] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [NOCRTC] > [ 3.504510] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [CRTC:72:pipe B] > [ 3.504519] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 > [ 3.504529] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 3.504538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005fe5cc2f > [ 3.504547] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 3.504558] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 3.504571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.504576] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.504581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.504586] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.504640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.504682] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.504701] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 3.513214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 3.513230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 3.527601] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.527620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002938b22d state to 00000000f3200e59 > [ 3.527632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000022f73fd2 state to 00000000f3200e59 > [ 3.527643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000041c6228e state to 00000000f3200e59 > [ 3.527656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000041c6228e > [ 3.527667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000f3200e59 > [ 3.527679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be > [ 3.527692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000071f245df state to 00000000f3200e59 > [ 3.527705] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 > [ 3.527716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 00000000f3200e59 > [ 3.527728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a > [ 3.527738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000d9e36170 state to 00000000f3200e59 > [ 3.527749] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000d9e36170 > [ 3.527760] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bf357c4b state to 00000000f3200e59 > [ 3.527776] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000059814b3a state to 00000000f3200e59 > [ 3.527787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000059814b3a > [ 3.527798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 > [ 3.527809] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd > [ 3.527828] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002938b22d > [ 3.527839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.527850] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000300c269e state to 00000000f3200e59 > [ 3.527862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [NOCRTC] > [ 3.527873] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [CRTC:51:pipe A] > [ 3.527884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000071f245df > [ 3.527894] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.527907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000000afdf5db state to 00000000f3200e59 > [ 3.527917] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [NOCRTC] > [ 3.527928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [CRTC:72:pipe B] > [ 3.527939] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 > [ 3.527949] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e > [ 3.527959] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bf357c4b > [ 3.527970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.527981] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.527993] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.528000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.528005] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.528010] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.528081] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.528130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.528155] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.532011] usb 1-14: new full-speed USB device number 8 using xhci_hcd > [ 3.541291] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.541309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.544126] lenovo 0003:17EF:6047.0004: input,hiddev0,hidraw3: USB HID v1.00 Mouse [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input1 > [ 3.556564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.556581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000023110e55 state to 00000000c6c933d1 > [ 3.556594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 > [ 3.556605] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b9dd800a state to 00000000c6c933d1 > [ 3.556617] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b9dd800a > [ 3.556628] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000edf72591 state to 00000000c6c933d1 > [ 3.556640] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000edf72591 > [ 3.556651] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009869db1d state to 00000000c6c933d1 > [ 3.556661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 3.556671] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bd903151 state to 00000000c6c933d1 > [ 3.556682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bd903151 > [ 3.556692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c282abaf state to 00000000c6c933d1 > [ 3.556703] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c282abaf > [ 3.556713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000009f04fd17 state to 00000000c6c933d1 > [ 3.556723] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c31f7fa4 state to 00000000c6c933d1 > [ 3.556734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c31f7fa4 > [ 3.556744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000eac50bee state to 00000000c6c933d1 > [ 3.556754] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000eac50bee > [ 3.556766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000023110e55 > [ 3.556777] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.556793] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000dddcb6a7 state to 00000000c6c933d1 > [ 3.556804] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [NOCRTC] > [ 3.556814] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [CRTC:51:pipe A] > [ 3.556825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009869db1d > [ 3.556836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.556846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 > [ 3.556857] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] > [ 3.556867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] > [ 3.556878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 > [ 3.556889] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 > [ 3.556899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000009f04fd17 > [ 3.556909] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.556920] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.556932] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.556938] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.556944] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.556949] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.557021] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.557068] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.557089] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.563101] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.563118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.577479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.577503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003073c677 state to 00000000f3200e59 > [ 3.577514] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 00000000f3200e59 > [ 3.577525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e5892e4f state to 00000000f3200e59 > [ 3.577537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e5892e4f > [ 3.577548] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c3b3ca94 state to 00000000f3200e59 > [ 3.577559] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c3b3ca94 > [ 3.577570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000015579631 state to 00000000f3200e59 > [ 3.577580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 00000000f3200e59 > [ 3.577590] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000083fdb4aa state to 00000000f3200e59 > [ 3.577602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000083fdb4aa > [ 3.577614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000087dc1fd8 state to 00000000f3200e59 > [ 3.577624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000087dc1fd8 > [ 3.577635] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ada87627 state to 00000000f3200e59 > [ 3.577644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e7bdd2e4 state to 00000000f3200e59 > [ 3.577655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e7bdd2e4 > [ 3.577666] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 > [ 3.577676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd > [ 3.577687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000003073c677 > [ 3.577698] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.577711] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000f3200e59 > [ 3.577725] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] > [ 3.577735] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] > [ 3.577746] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000015579631 > [ 3.577756] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.577766] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000f3200e59 > [ 3.577777] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 3.577787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 3.577798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 > [ 3.577808] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e > [ 3.577818] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ada87627 > [ 3.577828] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.577839] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.577852] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.577858] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.577863] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.577868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.577941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.577988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.578009] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.591295] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.591314] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.605686] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.605699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003494222 state to 00000000c6c933d1 > [ 3.605711] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 > [ 3.605722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010343cf4 state to 00000000c6c933d1 > [ 3.605736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010343cf4 > [ 3.605747] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e6ce87e3 state to 00000000c6c933d1 > [ 3.605758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e6ce87e3 > [ 3.605769] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac0b8286 state to 00000000c6c933d1 > [ 3.605779] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 3.605789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007ba2cc3a state to 00000000c6c933d1 > [ 3.605801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007ba2cc3a > [ 3.605811] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000071cce0a state to 00000000c6c933d1 > [ 3.605822] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000071cce0a > [ 3.605832] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008fde4998 state to 00000000c6c933d1 > [ 3.605842] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ad384e88 state to 00000000c6c933d1 > [ 3.605852] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ad384e88 > [ 3.605862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f7870136 state to 00000000c6c933d1 > [ 3.605872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f7870136 > [ 3.605884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003494222 > [ 3.605895] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.605907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 > [ 3.605918] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] > [ 3.605928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] > [ 3.605943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000ac0b8286 > [ 3.605953] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.605964] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 > [ 3.605975] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] > [ 3.605985] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] > [ 3.605996] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 > [ 3.606007] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f > [ 3.606016] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008fde4998 > [ 3.606027] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.606038] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.606061] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.606067] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.606072] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.606078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.606138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.606184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.606205] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.613058] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.613075] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.626981] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.626992] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002a1c343e state to 00000000c6c933d1 > [ 3.627002] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 > [ 3.627011] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 > [ 3.627022] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be > [ 3.627031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008af22ea7 state to 00000000c6c933d1 > [ 3.627042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008af22ea7 > [ 3.627051] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b777cf9c state to 00000000c6c933d1 > [ 3.627060] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 3.627074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fcdab79b state to 00000000c6c933d1 > [ 3.627083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fcdab79b > [ 3.627092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000031a1a724 state to 00000000c6c933d1 > [ 3.627102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000031a1a724 > [ 3.627111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008f0802a0 state to 00000000c6c933d1 > [ 3.627119] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000098e2986c state to 00000000c6c933d1 > [ 3.627128] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000098e2986c > [ 3.627137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000859ae2da state to 00000000c6c933d1 > [ 3.627146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000859ae2da > [ 3.627156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002a1c343e > [ 3.627166] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.627184] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003d8ac4de state to 00000000c6c933d1 > [ 3.627198] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [NOCRTC] > [ 3.627207] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [CRTC:51:pipe A] > [ 3.627217] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b777cf9c > [ 3.627226] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.627235] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006c42b361 state to 00000000c6c933d1 > [ 3.627244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [NOCRTC] > [ 3.627253] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [CRTC:72:pipe B] > [ 3.627263] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 > [ 3.627272] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 > [ 3.627280] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008f0802a0 > [ 3.627289] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.627298] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.627309] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.627315] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.627319] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.627324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.627377] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.627418] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.627437] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.641307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.641321] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.641349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.641359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b5c379f5 state to 00000000c6c933d1 > [ 3.641368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 > [ 3.641376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f7870136 state to 00000000c6c933d1 > [ 3.641387] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f7870136 > [ 3.641396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ad384e88 state to 00000000c6c933d1 > [ 3.641405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ad384e88 > [ 3.641414] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008fde4998 state to 00000000c6c933d1 > [ 3.641422] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 3.641430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000071cce0a state to 00000000c6c933d1 > [ 3.641439] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000071cce0a > [ 3.641448] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007ba2cc3a state to 00000000c6c933d1 > [ 3.641457] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007ba2cc3a > [ 3.641465] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ac0b8286 state to 00000000c6c933d1 > [ 3.641473] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e6ce87e3 state to 00000000c6c933d1 > [ 3.641482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e6ce87e3 > [ 3.641490] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010343cf4 state to 00000000c6c933d1 > [ 3.641498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010343cf4 > [ 3.641508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000b5c379f5 > [ 3.641517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.641530] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000091d2cf4c state to 00000000c6c933d1 > [ 3.641539] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [NOCRTC] > [ 3.641547] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [CRTC:51:pipe A] > [ 3.641556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008fde4998 > [ 3.641564] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.641573] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000706e661a state to 00000000c6c933d1 > [ 3.641582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [NOCRTC] > [ 3.641590] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [CRTC:72:pipe B] > [ 3.641599] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 > [ 3.641607] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 > [ 3.641615] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ac0b8286 > [ 3.641624] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.641634] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.641652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.641657] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.641662] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.641666] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.641717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.641755] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.641773] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.657984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.658001] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.672900] i915 0000:00:02.0: fb1: i915drmfb frame buffer device > [ 3.672952] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] > [ 3.672975] [drm:drm_client_modeset_probe [drm]] > [ 3.672989] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 3.673056] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 3.673077] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 3.673087] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 3.673141] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 3.673439] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.673482] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.674059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.674108] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.674144] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.674179] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 3.676928] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.676971] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 3.677594] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.677624] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.677924] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.677959] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.677966] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 3.677973] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 3.678004] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 3.678433] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.678800] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.680367] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.680395] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.680424] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.680717] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 3.681517] usb 1-14: New USB device found, idVendor=045e, idProduct=028e, bcdDevice= 1.10 > [ 3.681519] usb 1-14: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 3.681521] usb 1-14: Product: TGZ Controller > [ 3.681522] usb 1-14: Manufacturer: D > [ 3.681523] usb 1-14: SerialNumber: 3E5296A0 > [ 3.687203] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.687816] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.687827] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.687847] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.687853] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.688062] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.688070] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.688077] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.688084] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.688090] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688097] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688104] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688110] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688116] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688122] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688129] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688135] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688143] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 3.688150] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.688157] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.688163] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.688169] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.688176] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.688182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.688188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.688195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.688201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.688208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.688214] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.688220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.688227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.688233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.688239] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.688246] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.688252] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.688258] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.688264] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.688271] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.688277] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.688283] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.688290] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.688296] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.688302] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.688309] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.688315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.688321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.688330] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688337] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688344] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688350] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688357] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.688363] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.688369] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.688375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.688382] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.688386] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 3.688411] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 3.688721] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.688741] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.689059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.689088] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.689107] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.689125] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 3.691950] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.691968] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 3.692263] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.692279] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.692557] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.692584] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.692588] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 3.692592] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 3.692612] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 3.693013] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.693367] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.694886] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.694906] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.694925] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.695202] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 3.701116] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.701642] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.701650] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.701657] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.701664] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.701855] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.701862] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.701870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.701877] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.701884] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701891] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701898] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701904] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701911] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701918] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701925] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701931] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701938] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 3.701945] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.701952] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.701959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.701965] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.701972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.701979] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.701986] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.701992] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.701999] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.702006] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.702013] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.702019] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.702026] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.702033] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.702039] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.702046] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.702053] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.702060] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.702066] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.702073] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.702080] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.702086] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.702093] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.702100] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.702106] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.702113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.702120] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.702127] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.702133] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702160] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.702167] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.702173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.702180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.702187] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.702191] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 3.702219] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 3.702518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.702538] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.702817] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.702840] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.702858] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.702876] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 3.705524] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.705544] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 3.705839] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.705857] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.706135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.706154] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.706159] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 3.706163] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 3.706183] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 3.706193] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 3.706203] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no > [ 3.706211] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no > [ 3.706219] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes > [ 3.706226] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no > [ 3.706234] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes > [ 3.706241] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no > [ 3.706248] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no > [ 3.706256] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 3.706264] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 > [ 3.706271] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 > [ 3.706277] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.706284] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 > [ 3.706291] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 > [ 3.706298] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.706304] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config > [ 3.706313] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) > [ 3.706320] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) > [ 3.706338] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 3.706348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000092327a12 state to 00000000fc0cb429 > [ 3.706357] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ca6e974 state to 00000000fc0cb429 > [ 3.706365] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000aea8f107 state to 00000000fc0cb429 > [ 3.706373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000aea8f107 > [ 3.706382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000e4b6e50 state to 00000000fc0cb429 > [ 3.706389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000e4b6e50 > [ 3.706397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000098d0b1b state to 00000000fc0cb429 > [ 3.706405] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000374f38f state to 00000000fc0cb429 > [ 3.706413] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ba689a33 state to 00000000fc0cb429 > [ 3.706420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ba689a33 > [ 3.706428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ae016691 state to 00000000fc0cb429 > [ 3.706435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ae016691 > [ 3.706443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002012d358 state to 00000000fc0cb429 > [ 3.706451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000eb42cb6c state to 00000000fc0cb429 > [ 3.706458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000eb42cb6c > [ 3.706466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac043c4a state to 00000000fc0cb429 > [ 3.706473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac043c4a > [ 3.706481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000092327a12 > [ 3.706489] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 3.706497] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000005b4f258 state to 00000000fc0cb429 > [ 3.706505] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [NOCRTC] > [ 3.706513] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [CRTC:51:pipe A] > [ 3.706520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000098d0b1b > [ 3.706528] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 3.706536] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ee6ef05 state to 00000000fc0cb429 > [ 3.706543] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [NOCRTC] > [ 3.706551] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [CRTC:72:pipe B] > [ 3.706559] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 > [ 3.706566] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 3.706573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000002012d358 > [ 3.706581] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 3.706589] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 3.706597] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.706601] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.706605] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.706609] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.706636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.706659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.706675] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 3.713140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 3.713154] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 3.713179] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] > [ 3.713188] [drm:drm_client_modeset_probe [drm]] > [ 3.713202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 3.713233] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 3.713246] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 3.713251] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 3.713275] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 3.713582] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.713608] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.713894] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.713919] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.713941] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.713961] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 3.716582] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.716601] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 3.716897] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.716914] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.717193] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.717219] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.717223] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 3.717228] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 3.717250] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 3.717659] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.718014] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.719533] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.719553] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.719572] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.719697] sr 2:0:0:0: [sr0] scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray > [ 3.719699] cdrom: Uniform CD-ROM driver Revision: 3.20 > [ 3.719853] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 3.725765] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.726292] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.726302] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.726310] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.726317] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.726526] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.726533] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.726540] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.726547] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.726554] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726561] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726574] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726581] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726587] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726594] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726600] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726606] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 3.726613] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.726620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.726626] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.726633] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.726639] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.726646] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.726652] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.726659] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.726666] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.726672] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.726679] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.726685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.726692] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.726698] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.726705] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.726711] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.726718] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.726724] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.726731] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.726737] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.726744] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.726750] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.726757] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.726763] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.726770] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.726776] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.726783] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.726789] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.726796] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726802] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726809] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726815] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726822] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.726828] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.726835] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.726841] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.726848] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.726852] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 3.726874] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 3.727171] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.727191] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.727470] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.727492] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.727511] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.727530] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 3.730191] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.730209] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 3.730502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.730519] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.730796] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.730814] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.730818] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 3.730822] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 3.730841] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 3.731245] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.731600] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.733115] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.733135] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.733153] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.733432] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 3.735981] sr 2:0:0:0: Attached scsi CD-ROM sr0 > [ 3.739342] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.739867] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.739875] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.739883] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.739889] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.740070] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.740077] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.740085] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.740092] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.740099] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740106] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740119] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740133] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740152] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 3.740159] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.740166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.740173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.740180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.740186] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.740193] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.740200] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.740206] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.740213] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.740220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.740227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.740233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.740240] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.740247] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.740254] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.740260] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.740267] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.740274] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.740280] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.740287] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.740294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.740301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.740307] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.740314] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.740321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.740328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.740334] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.740341] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.740348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740361] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.740381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.740388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.740395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.740401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.740405] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 3.740428] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 3.740726] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.740746] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.741027] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.741049] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.741068] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.741086] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 3.743693] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.743712] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 3.744007] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.744024] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.744301] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.744320] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.744324] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 3.744328] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 3.744346] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 3.744356] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 3.744365] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no > [ 3.744373] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no > [ 3.744380] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes > [ 3.744387] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no > [ 3.744394] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes > [ 3.744400] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no > [ 3.744407] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no > [ 3.744415] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 3.744422] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 > [ 3.744428] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 > [ 3.744434] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.744441] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 > [ 3.744447] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 > [ 3.744453] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.744460] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config > [ 3.744468] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) > [ 3.744475] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) > [ 3.744485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 3.744494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062abf8d7 state to 00000000fc0cb429 > [ 3.744503] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 3.744510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059907653 state to 00000000fc0cb429 > [ 3.744518] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059907653 > [ 3.744526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002b958a81 state to 00000000fc0cb429 > [ 3.744533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002b958a81 > [ 3.744541] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dff2ac2f state to 00000000fc0cb429 > [ 3.744548] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 > [ 3.744557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005ed6e442 state to 00000000fc0cb429 > [ 3.744564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005ed6e442 > [ 3.744571] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006d13a46c state to 00000000fc0cb429 > [ 3.744578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006d13a46c > [ 3.744586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000dc86a4bd state to 00000000fc0cb429 > [ 3.744597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000002f6b4ed state to 00000000fc0cb429 > [ 3.744604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000002f6b4ed > [ 3.744611] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000009db6fe1 state to 00000000fc0cb429 > [ 3.744618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000009db6fe1 > [ 3.744626] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000062abf8d7 > [ 3.744633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 3.744641] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 00000000fc0cb429 > [ 3.744648] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] > [ 3.744656] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] > [ 3.744662] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000dff2ac2f > [ 3.744670] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 3.744677] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000057c6efeb state to 00000000fc0cb429 > [ 3.744685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [NOCRTC] > [ 3.744692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [CRTC:72:pipe B] > [ 3.744706] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000422ac28a state to 00000000fc0cb429 > [ 3.744713] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000422ac28a > [ 3.744719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000dc86a4bd > [ 3.744727] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 3.744734] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 3.744741] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.744746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.744749] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.744753] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.744786] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.744808] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.744823] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 3.757962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 3.758007] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 3.760005] usb 1-11.3: new full-speed USB device number 9 using xhci_hcd > [ 3.863221] usb 1-11.3: New USB device found, idVendor=056a, idProduct=0392, bcdDevice= 1.07 > [ 3.863226] usb 1-11.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 3.863230] usb 1-11.3: Product: Wacom Intuos Pro S > [ 3.863232] usb 1-11.3: Manufacturer: Wacom Co.,Ltd. > [ 3.863235] usb 1-11.3: SerialNumber: 9IQ0111006826 > [ 3.875163] hid-generic 0003:056A:0392.0005: hiddev1,hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 > [ 3.878106] hid-generic 0003:056A:0392.0006: hiddev2,hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 > [ 3.901638] input: Wacom Intuos Pro S Pen as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input8 > [ 3.901775] input: Wacom Intuos Pro S Pad as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input10 > [ 3.901851] wacom 0003:056A:0392.0005: hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 > [ 3.902858] input: Wacom Intuos Pro S Finger as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.1/0003:056A:0392.0006/input/input12 > [ 3.902979] wacom 0003:056A:0392.0006: hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 > [ 3.943873] usb 1-12.1: new high-speed USB device number 10 using xhci_hcd > [ 4.045574] usb 1-12.1: New USB device found, idVendor=16d0, idProduct=071a, bcdDevice= 1.96 > [ 4.045583] usb 1-12.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 4.045586] usb 1-12.1: Product: Combo384 Amanero > [ 4.045589] usb 1-12.1: Manufacturer: Amanero Technologies > [ 4.045592] usb 1-12.1: SerialNumber: 413-001 > [ 4.136728] process '/usr/bin/fstype' started with executable stack > [ 4.149281] PM: Image not found (code -22) > [ 4.267305] SGI XFS with ACLs, security attributes, realtime, quota, no debug enabled > [ 4.270230] XFS (sda1): Mounting V5 Filesystem > [ 4.283488] XFS (sda1): Ending clean mount > [ 4.381935] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist. > [ 4.466746] systemd[1]: Inserted module 'autofs4' > [ 4.493716] systemd[1]: systemd 245.5-3 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=hybrid) > [ 4.512168] systemd[1]: Detected architecture x86-64. > [ 4.541853] systemd[1]: Set hostname to <hirez>. > [ 4.676468] systemd[1]: /lib/systemd/system/dbus.socket:5: ListenStream= references a path below legacy directory /var/run/, updating /var/run/dbus/system_bus_socket ? /run/dbus/system_bus_socket; please update the unit file accordingly. > [ 4.732617] systemd[1]: Created slice system-getty.slice. > [ 4.732826] systemd[1]: Created slice system-modprobe.slice. > [ 4.733006] systemd[1]: Created slice system-postfix.slice. > [ 4.733241] systemd[1]: Created slice User and Session Slice. > [ 4.733308] systemd[1]: Started Forward Password Requests to Wall Directory Watch. > [ 4.733466] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. > [ 4.733508] systemd[1]: Reached target User and Group Name Lookups. > [ 4.733523] systemd[1]: Reached target Slices. > [ 4.736775] systemd[1]: Listening on RPCbind Server Activation Socket. > [ 4.737370] systemd[1]: Listening on Syslog Socket. > [ 4.737434] systemd[1]: Listening on initctl Compatibility Named Pipe. > [ 4.737838] systemd[1]: Listening on Journal Audit Socket. > [ 4.737907] systemd[1]: Listening on Journal Socket (/dev/log). > [ 4.737992] systemd[1]: Listening on Journal Socket. > [ 4.738085] systemd[1]: Listening on udev Control Socket. > [ 4.738133] systemd[1]: Listening on udev Kernel Socket. > [ 4.738771] systemd[1]: Mounting Huge Pages File System... > [ 4.739449] systemd[1]: Mounting POSIX Message Queue File System... > [ 4.740120] systemd[1]: Mounting RPC Pipe File System... > [ 4.741130] systemd[1]: Mounting Kernel Debug File System... > [ 4.742089] systemd[1]: Mounting Kernel Trace File System... > [ 4.742177] systemd[1]: Condition check resulted in Kernel Module supporting RPCSEC_GSS being skipped. > [ 4.743057] systemd[1]: Starting Wait for network to be configured by ifupdown... > [ 4.744088] systemd[1]: Starting Set the console keyboard layout... > [ 4.744753] systemd[1]: Starting Create list of static device nodes for the current kernel... > [ 4.744784] systemd[1]: Condition check resulted in Load Kernel Module drm being skipped. > [ 4.745130] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped. > [ 4.746296] systemd[1]: Starting Journal Service... > [ 4.748422] systemd[1]: Starting Load Kernel Modules... > [ 4.749115] systemd[1]: Starting Remount Root and Kernel File Systems... > [ 4.749944] systemd[1]: Starting udev Coldplug all Devices... > [ 4.751645] systemd[1]: Mounted Huge Pages File System. > [ 4.751832] systemd[1]: Mounted POSIX Message Queue File System. > [ 4.751979] systemd[1]: Mounted Kernel Debug File System. > [ 4.752111] systemd[1]: Mounted Kernel Trace File System. > [ 4.752618] systemd[1]: Finished Wait for network to be configured by ifupdown. > [ 4.753157] systemd[1]: Finished Create list of static device nodes for the current kernel. > [ 4.761518] lp: driver loaded but no devices found > [ 4.763837] ppdev: user-space parallel port driver > [ 4.771880] systemd[1]: Finished Load Kernel Modules. > [ 4.772256] systemd[1]: Condition check resulted in FUSE Control File System being skipped. > [ 4.772353] systemd[1]: Condition check resulted in Kernel Configuration File System being skipped. > [ 4.772373] xfs filesystem being remounted at / supports timestamps until 2038 (0x7fffffff) > [ 4.773269] systemd[1]: Starting Apply Kernel Variables... > [ 4.773401] RPC: Registered named UNIX socket transport module. > [ 4.773402] RPC: Registered udp transport module. > [ 4.773402] RPC: Registered tcp transport module. > [ 4.773403] RPC: Registered tcp NFSv4.1 backchannel transport module. > [ 4.775228] systemd[1]: Mounted RPC Pipe File System. > [ 4.775747] systemd[1]: Finished Remount Root and Kernel File Systems. > [ 4.776247] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped. > [ 4.776285] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped. > [ 4.777070] systemd[1]: Starting Load/Save Random Seed... > [ 4.777955] systemd[1]: Starting Create System Users... > [ 4.780674] systemd[1]: Finished Apply Kernel Variables. > [ 4.793614] systemd[1]: Finished Load/Save Random Seed. > [ 4.796908] systemd[1]: Finished Create System Users. > [ 4.797598] systemd[1]: Starting Create Static Device Nodes in /dev... > [ 4.802675] systemd[1]: Finished Set the console keyboard layout. > [ 4.808929] systemd[1]: Finished Create Static Device Nodes in /dev. > [ 4.809034] systemd[1]: Reached target Local File Systems (Pre). > [ 4.809044] systemd[1]: Reached target Local File Systems. > [ 4.809658] systemd[1]: Starting Load AppArmor profiles... > [ 4.810278] systemd[1]: Starting Enable support for additional executable binary formats... > [ 4.811095] systemd[1]: Starting Set console font and keymap... > [ 4.811940] systemd[1]: Starting Preprocess NFS configuration... > [ 4.812829] systemd[1]: Starting Tell Plymouth To Write Out Runtime Data... > [ 4.812857] systemd[1]: Condition check resulted in Store a System Token in an EFI Variable being skipped. > [ 4.812897] systemd[1]: Condition check resulted in Commit a transient machine-id on disk being skipped. > [ 4.813667] systemd[1]: Starting udev Kernel Device Manager... > [ 4.813843] systemd[1]: proc-sys-fs-binfmt_misc.automount: Got automount request for /proc/sys/fs/binfmt_misc, triggered by 350 (update-binfmts) > [ 4.814689] systemd[1]: Mounting Arbitrary Executable File Formats File System... > [ 4.815333] systemd[1]: Finished Set console font and keymap. > [ 4.815579] systemd[1]: nfs-config.service: Succeeded. > [ 4.815929] systemd[1]: Finished Preprocess NFS configuration. > [ 4.816074] systemd[1]: Condition check resulted in RPC security service for NFS client and server being skipped. > [ 4.816102] systemd[1]: Condition check resulted in RPC security service for NFS server being skipped. > [ 4.816118] systemd[1]: Reached target NFS client services. > [ 4.820384] systemd[1]: Mounted Arbitrary Executable File Formats File System. > [ 4.824947] systemd[1]: Finished Enable support for additional executable binary formats. > [ 4.825708] systemd[1]: Received SIGRTMIN+20 from PID 243 (plymouthd). > [ 4.828330] systemd[1]: Finished Tell Plymouth To Write Out Runtime Data. > [ 4.840263] audit: type=1400 audit(1591264850.416:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="firejail-default" pid=368 comm="apparmor_parser" > [ 4.840263] systemd[1]: Finished udev Coldplug all Devices. > [ 4.841296] systemd[1]: Starting Helper to synchronize boot up for ifupdown... > [ 4.841705] audit: type=1400 audit(1591264850.416:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-senddoc" pid=372 comm="apparmor_parser" > [ 4.843324] audit: type=1400 audit(1591264850.416:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="postgresql_akonadi" pid=370 comm="apparmor_parser" > [ 4.843644] audit: type=1400 audit(1591264850.416:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-oopslash" pid=371 comm="apparmor_parser" > [ 4.843772] systemd[1]: Finished Helper to synchronize boot up for ifupdown. > [ 4.843977] audit: type=1400 audit(1591264850.420:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=369 comm="apparmor_parser" > [ 4.843989] audit: type=1400 audit(1591264850.420:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=369 comm="apparmor_parser" > [ 4.843990] audit: type=1400 audit(1591264850.420:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=369 comm="apparmor_parser" > [ 4.844372] audit: type=1400 audit(1591264850.420:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-xpdfimport" pid=375 comm="apparmor_parser" > [ 4.845764] audit: type=1400 audit(1591264850.420:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cups-browsed" pid=365 comm="apparmor_parser" > [ 4.911836] systemd[1]: Finished Load AppArmor profiles. > [ 4.912675] systemd[1]: Starting Raise network interfaces... > [ 4.952184] systemd[1]: Finished Raise network interfaces. > [ 4.954977] systemd[1]: Started udev Kernel Device Manager. > [ 4.955663] systemd[1]: Starting Show Plymouth Boot Screen... > [ 4.981642] systemd[1]: Started Show Plymouth Boot Screen. > [ 4.981868] systemd[1]: Condition check resulted in Dispatch Password Requests to Console Directory Watch being skipped. > [ 4.981983] systemd[1]: Started Forward Password Requests to Plymouth Directory Watch. > [ 4.982014] systemd[1]: Reached target Local Encrypted Volumes. > [ 5.003794] IPMI message handler: version 39.2 > [ 5.007344] ipmi device interface > [ 5.014857] ipmi_si: IPMI System Interface driver > [ 5.014872] ipmi_si dmi-ipmi-si.0: ipmi_platform: probing via SMBIOS > [ 5.014874] ipmi_platform: ipmi_si: SMBIOS: io 0xca2 regsize 1 spacing 1 irq 0 > [ 5.014875] ipmi_si: Adding SMBIOS-specified kcs state machine > [ 5.015655] ipmi_si IPI0001:00: ipmi_platform: probing via ACPI > [ 5.015806] ipmi_si IPI0001:00: ipmi_platform: [io 0x0ca4] regsize 1 spacing 1 irq 0 > [ 5.015807] ipmi_si: Adding ACPI-specified kcs state machine > [ 5.015884] ipmi_si: Trying SMBIOS-specified kcs state machine at i/o address 0xca2, slave address 0x20, irq 0 > [ 5.088154] EDAC MC0: Giving out device to module ie31200_edac controller IE31200: DEV 0000:00:00.0 (POLLED) > [ 5.089876] sd 1:0:0:0: Attached scsi generic sg0 type 0 > [ 5.090024] sr 2:0:0:0: Attached scsi generic sg1 type 5 > [ 5.090192] sd 4:0:0:0: Attached scsi generic sg2 type 0 > [ 5.090241] sd 4:0:0:1: Attached scsi generic sg3 type 0 > [ 5.090266] sd 4:0:0:2: Attached scsi generic sg4 type 0 > [ 5.090320] sd 4:0:0:3: Attached scsi generic sg5 type 0 > [ 5.090373] sd 4:0:0:4: Attached scsi generic sg6 type 0 > [ 5.091437] iTCO_vendor_support: vendor-support=0 > [ 5.092650] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11 > [ 5.092707] mei_me 0000:00:16.0: enabling device (0000 -> 0002) > [ 5.092778] input: Microsoft X-Box 360 pad as /devices/pci0000:00/0000:00:14.0/usb1/1-14/1-14:1.0/input/input14 > [ 5.092783] iTCO_wdt: unable to reset NO_REBOOT flag, device disabled by hardware/BIOS > [ 5.092866] usbcore: registered new interface driver xpad > [ 5.116588] mc: Linux media interface: v0.10 > [ 5.141208] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer > [ 5.141209] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules > [ 5.141210] RAPL PMU: hw unit of domain package 2^-14 Joules > [ 5.141211] RAPL PMU: hw unit of domain dram 2^-14 Joules > [ 5.141211] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules > [ 5.150008] systemd[1]: Found device Samsung_SSD_850_PRO_512GB 5. > [ 5.159157] systemd[1]: Activating swap /dev/disk/by-uuid/602df9e6-40fb-41aa-b0df-96a9088df593... > [ 5.186454] systemd[1]: Started Journal Service. > [ 5.189868] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) > [ 5.192407] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. > [ 5.192408] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 2, val = -32767/0/1 > [ 5.193209] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ef6f2003 > [ 5.193220] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ea16da3d state to 00000000ef6f2003 > [ 5.193230] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000088487cf7 state to 00000000ef6f2003 > [ 5.193238] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028b01bfa state to 00000000ef6f2003 > [ 5.193247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028b01bfa > [ 5.193255] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008a2f3e8a state to 00000000ef6f2003 > [ 5.193264] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008a2f3e8a > [ 5.193294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000eb2a745f state to 00000000ef6f2003 > [ 5.193315] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000faa616df state to 00000000ef6f2003 > [ 5.193324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cbb299c1 state to 00000000ef6f2003 > [ 5.193332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cbb299c1 > [ 5.193353] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000079bcaa7c state to 00000000ef6f2003 > [ 5.193361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000079bcaa7c > [ 5.193369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000fb71ed5 state to 00000000ef6f2003 > [ 5.193376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9cfd0f1 state to 00000000ef6f2003 > [ 5.193384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9cfd0f1 > [ 5.193393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007908e825 state to 00000000ef6f2003 > [ 5.193401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007908e825 > [ 5.193414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000ea16da3d > [ 5.193422] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ef6f2003 > [ 5.193431] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000018b0a306 state to 00000000ef6f2003 > [ 5.193440] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [NOCRTC] > [ 5.193447] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [CRTC:51:pipe A] > [ 5.193463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000eb2a745f > [ 5.193472] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ef6f2003 > [ 5.193481] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000008dfecd46 state to 00000000ef6f2003 > [ 5.193488] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [NOCRTC] > [ 5.193496] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [CRTC:72:pipe B] > [ 5.193507] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000fd253e01 state to 00000000ef6f2003 > [ 5.193515] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000fd253e01 > [ 5.193522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000fb71ed5 > [ 5.193530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ef6f2003 > [ 5.193538] [drm:drm_atomic_check_only [drm]] checking 00000000ef6f2003 > [ 5.193549] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 5.193553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 5.193557] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 5.193561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 5.193595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.193618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.193635] [drm:drm_atomic_commit [drm]] committing 00000000ef6f2003 > [ 5.196839] cryptd: max_cpu_qlen set to 1000 > [ 5.196865] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. > [ 5.196867] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 1, val = -32767/0/1 > [ 5.197058] usbcore: registered new interface driver snd-usb-audio > [ 5.208924] Adding 33442812k swap on /dev/sda5. Priority:-2 extents:1 across:33442812k SSFS > [ 5.209024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ef6f2003 > [ 5.209049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ef6f2003 > [ 5.214980] systemd-journald[324]: Received client request to flush runtime journal. > [ 5.232082] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9f8f61b > [ 5.232093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d30af224 state to 00000000f9f8f61b > [ 5.232103] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 00000000f9f8f61b > [ 5.232112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a3a0e390 state to 00000000f9f8f61b > [ 5.232121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a3a0e390 > [ 5.232129] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000050c6aee state to 00000000f9f8f61b > [ 5.232138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000050c6aee > [ 5.232151] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000330ef6e state to 00000000f9f8f61b > [ 5.232159] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a16f6bc3 state to 00000000f9f8f61b > [ 5.232166] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bb4d02e2 state to 00000000f9f8f61b > [ 5.232174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bb4d02e2 > [ 5.232182] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a99d3259 state to 00000000f9f8f61b > [ 5.232192] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a99d3259 > [ 5.232200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c8e13b43 state to 00000000f9f8f61b > [ 5.232207] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ece028f4 state to 00000000f9f8f61b > [ 5.232215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ece028f4 > [ 5.232222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000c21cbeb state to 00000000f9f8f61b > [ 5.232232] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000c21cbeb > [ 5.232240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000d30af224 > [ 5.232250] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f9f8f61b > [ 5.232264] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004431baab state to 00000000f9f8f61b > [ 5.232274] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [NOCRTC] > [ 5.232282] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [CRTC:51:pipe A] > [ 5.232289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000330ef6e > [ 5.232297] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f9f8f61b > [ 5.232305] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000641aa27e state to 00000000f9f8f61b > [ 5.232314] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [NOCRTC] > [ 5.232322] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [CRTC:72:pipe B] > [ 5.232331] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e1c94e20 state to 00000000f9f8f61b > [ 5.232338] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e1c94e20 > [ 5.232345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c8e13b43 > [ 5.232353] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f9f8f61b > [ 5.232362] [drm:drm_atomic_check_only [drm]] checking 00000000f9f8f61b > [ 5.232373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 5.232377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 5.232381] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 5.232385] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 5.232421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.232445] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.232472] [drm:drm_atomic_commit [drm]] committing 00000000f9f8f61b > [ 5.246294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9f8f61b > [ 5.246308] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9f8f61b > [ 5.268023] AVX2 version of gcm_enc/dec engaged. > [ 5.268024] AES CTR mode by8 optimization enabled > [ 5.278985] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC888-VD: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:line > [ 5.278986] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) > [ 5.278987] snd_hda_codec_realtek hdaudioC0D0: hp_outs=0 (0x0/0x0/0x0/0x0/0x0) > [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 > [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: inputs: > [ 5.278989] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 > [ 5.293862] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 5.293885] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 5.293906] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 5.293928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 5.293948] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 5.293970] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 5.293988] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 5.295775] ipmi_si dmi-ipmi-si.0: The BMC does not support clearing the recv irq bit, compensating, but the BMC needs to be fixed. > [ 5.312401] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1f.3/sound/card0/input15 > [ 5.312465] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input16 > [ 5.312514] input: HDA Intel PCH Front Line Out as /devices/pci0000:00/0000:00:1f.3/sound/card0/input17 > [ 5.312560] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input18 > [ 5.312604] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input19 > [ 5.312651] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input20 > [ 5.312690] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input21 > [ 5.312737] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input22 > [ 5.388997] ipmi_si dmi-ipmi-si.0: IPMI message handler: Found new BMC (man_id: 0x002a7c, prod_id: 0x0888, dev_id: 0x20) > [ 5.430745] ipmi_si dmi-ipmi-si.0: IPMI kcs interface initialized > [ 5.442072] ipmi_ssif: IPMI SSIF Interface driver > [ 5.690895] intel_rapl_common: Found RAPL domain package > [ 5.690897] intel_rapl_common: Found RAPL domain core > [ 5.690899] intel_rapl_common: Found RAPL domain uncore > [ 5.690900] intel_rapl_common: Found RAPL domain dram > [ 6.053475] alg: No test for fips(ansi_cprng) (fips_ansi_cprng) > [ 6.145869] Bluetooth: Core ver 2.22 > [ 6.145879] NET: Registered protocol family 31 > [ 6.145880] Bluetooth: HCI device and connection manager initialized > [ 6.145883] Bluetooth: HCI socket layer initialized > [ 6.145884] Bluetooth: L2CAP socket layer initialized > [ 6.145886] Bluetooth: SCO socket layer initialized > [ 6.256918] kauditd_printk_skb: 16 callbacks suppressed > [ 6.256919] audit: type=1400 audit(1591264851.832:27): apparmor="DENIED" operation="capable" profile="/usr/sbin/cups-browsed" pid=724 comm="cups-browsed" capability=23 capname="sys_nice" > [ 10.310500] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx > [ 10.310581] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready > [ 14.126521] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx > [ 14.914834] FS-Cache: Loaded > [ 14.953494] FS-Cache: Netfs 'nfs' registered for caching > [ 14.956761] Key type dns_resolver registered > [ 15.082476] NFS: Registering the id_resolver key type > [ 15.082496] Key type id_resolver registered > [ 15.082497] Key type id_legacy registered > [ 15.296934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d166d111 > [ 15.296974] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008bf5b86d state to 00000000d166d111 > [ 15.297001] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 00000000bd8bd551 state to 00000000d166d111 > [ 15.297024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000835fb348 state to 00000000d166d111 > [ 15.297051] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000835fb348 > [ 15.297077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008bf5b86d > [ 15.297103] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d166d111 > [ 15.297127] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000f4bb3954 state to 00000000d166d111 > [ 15.297151] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [NOCRTC] > [ 15.297173] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [CRTC:33:crtc-0] > [ 15.297196] [drm:drm_atomic_check_only [drm]] checking 00000000d166d111 > [ 15.297215] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 15.297228] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 15.297255] [drm:drm_atomic_commit [drm]] committing 00000000d166d111 > [ 15.297321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d166d111 > [ 15.297345] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d166d111 > [ 15.297375] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 > [ 15.297451] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004b92744e > [ 15.297477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 000000004b92744e > [ 15.297500] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed9cb119 state to 000000004b92744e > [ 15.297522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000046234f6 state to 000000004b92744e > [ 15.297547] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000046234f6 > [ 15.297570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a35c929d state to 000000004b92744e > [ 15.297594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a35c929d > [ 15.297618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009d539ce0 state to 000000004b92744e > [ 15.297640] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed29f6c9 state to 000000004b92744e > [ 15.297662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 000000004b92744e > [ 15.297685] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f > [ 15.297707] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 000000004b92744e > [ 15.297730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 15.297753] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000e89c017 state to 000000004b92744e > [ 15.297774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000029001d73 state to 000000004b92744e > [ 15.297797] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000029001d73 > [ 15.297820] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000708b01e5 state to 000000004b92744e > [ 15.297853] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000708b01e5 > [ 15.297871] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f3527d8e > [ 15.297888] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000004b92744e > [ 15.297908] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000efae517b state to 000000004b92744e > [ 15.297927] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [NOCRTC] > [ 15.297944] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [CRTC:51:pipe A] > [ 15.297961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009d539ce0 > [ 15.297978] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000004b92744e > [ 15.297996] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000033858fd0 state to 000000004b92744e > [ 15.298013] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [NOCRTC] > [ 15.298030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [CRTC:72:pipe B] > [ 15.298048] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d397071c state to 000000004b92744e > [ 15.298065] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d397071c > [ 15.298081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000e89c017 > [ 15.298098] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000004b92744e > [ 15.298115] [drm:drm_atomic_check_only [drm]] checking 000000004b92744e > [ 15.298143] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 15.298153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 15.298161] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 15.298170] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 15.298248] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.298299] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.298333] [drm:drm_atomic_commit [drm]] committing 000000004b92744e > [ 15.313540] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004b92744e > [ 15.313557] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004b92744e > [ 15.330791] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 > [ 15.330803] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000033ce3db8 > [ 15.330813] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000008fdc242 state to 0000000033ce3db8 > [ 15.330826] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000024c9c604 state to 0000000033ce3db8 > [ 15.330836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000024c9c604 > [ 15.330845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000063a0901f state to 0000000033ce3db8 > [ 15.330854] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000063a0901f > [ 15.330862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f9f236ad state to 0000000033ce3db8 > [ 15.330870] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e1c94e20 state to 0000000033ce3db8 > [ 15.330879] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001976c542 state to 0000000033ce3db8 > [ 15.330887] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001976c542 > [ 15.330895] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000023bce10 state to 0000000033ce3db8 > [ 15.330903] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000023bce10 > [ 15.330912] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d3ee8271 state to 0000000033ce3db8 > [ 15.330919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000026db81c9 state to 0000000033ce3db8 > [ 15.330927] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000026db81c9 > [ 15.330940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003685cc7f state to 0000000033ce3db8 > [ 15.330948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003685cc7f > [ 15.330956] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f > [ 15.330965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 > [ 15.330974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009eadb78e state to 0000000033ce3db8 > [ 15.330982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [NOCRTC] > [ 15.330990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [CRTC:51:pipe A] > [ 15.330998] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f9f236ad > [ 15.331006] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 > [ 15.331014] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ef54c858 state to 0000000033ce3db8 > [ 15.331022] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [NOCRTC] > [ 15.331030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [CRTC:72:pipe B] > [ 15.331049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a16f6bc3 state to 0000000033ce3db8 > [ 15.331057] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a16f6bc3 > [ 15.331064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d3ee8271 > [ 15.331072] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 > [ 15.331080] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 > [ 15.331092] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 15.331096] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 15.331100] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 15.331104] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 15.331140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.331173] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.331191] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 > [ 15.346869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 > [ 15.346883] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 > [ 15.347242] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009bf2742d > [ 15.347253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008c267a81 state to 000000009bf2742d > [ 15.347264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 0000000042ba191e state to 000000009bf2742d > [ 15.347275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000050ba9058 state to 000000009bf2742d > [ 15.347285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000050ba9058 > [ 15.347294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008c267a81 > [ 15.347303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 000000009bf2742d > [ 15.347311] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000002bd5700a state to 000000009bf2742d > [ 15.347320] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [NOCRTC] > [ 15.347328] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [CRTC:33:crtc-0] > [ 15.347337] [drm:drm_atomic_check_only [drm]] checking 000000009bf2742d > [ 15.347344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 15.347349] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 15.347359] [drm:drm_atomic_commit [drm]] committing 000000009bf2742d > [ 15.347396] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009bf2742d > [ 15.347405] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009bf2742d > [ 15.347415] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 > [ 15.358909] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 > [ 15.358920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f6bb1f5 state to 0000000033ce3db8 > [ 15.358931] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 0000000033ce3db8 > [ 15.358939] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000002749498f state to 0000000033ce3db8 > [ 15.358949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000002749498f > [ 15.358961] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000006153d5d9 state to 0000000033ce3db8 > [ 15.358980] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000006153d5d9 > [ 15.358996] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006a05b5f7 state to 0000000033ce3db8 > [ 15.359012] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d397071c state to 0000000033ce3db8 > [ 15.359027] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cca4b9f0 state to 0000000033ce3db8 > [ 15.359042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cca4b9f0 > [ 15.359058] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009e05e90a state to 0000000033ce3db8 > [ 15.359072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009e05e90a > [ 15.359091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bc644261 state to 0000000033ce3db8 > [ 15.359109] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000000e16ac42 state to 0000000033ce3db8 > [ 15.359124] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000000e16ac42 > [ 15.359140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ed4faf45 state to 0000000033ce3db8 > [ 15.359155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ed4faf45 > [ 15.359171] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008f6bb1f5 > [ 15.359186] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 > [ 15.359203] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000025aaf842 state to 0000000033ce3db8 > [ 15.359223] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [NOCRTC] > [ 15.359238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [CRTC:51:pipe A] > [ 15.359254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006a05b5f7 > [ 15.359270] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 > [ 15.359285] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000a470917a state to 0000000033ce3db8 > [ 15.359302] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [NOCRTC] > [ 15.359323] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [CRTC:72:pipe B] > [ 15.359340] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ed29f6c9 state to 0000000033ce3db8 > [ 15.359358] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ed29f6c9 > [ 15.359372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bc644261 > [ 15.359388] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 > [ 15.359403] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 > [ 15.359433] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 15.359441] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 15.359449] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 15.359456] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 15.359505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.359557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.359583] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 > [ 15.375008] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 > [ 15.375022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 > [ 15.405098] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.405480] [drm:intel_framebuffer_init [i915]] No Y tiling for legacy addfb > [ 15.405515] [drm:drm_internal_framebuffer_create [drm]] could not create framebuffer > [ 15.405547] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.405606] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.405820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 > [ 15.405829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000053cd4a56 state to 00000000403c96a5 > [ 15.405838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000053cd4a56 > [ 15.405847] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 > [ 15.405873] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 > [ 15.405892] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 > [ 15.405899] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 > [ 15.405949] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 > [ 15.405957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007a41a1eb state to 00000000403c96a5 > [ 15.405965] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007a41a1eb > [ 15.405972] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 > [ 15.405980] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 > [ 15.405991] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 > [ 15.405998] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 > [ 15.406048] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 > [ 15.406055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000746efc3b state to 00000000403c96a5 > [ 15.406064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000746efc3b > [ 15.406071] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 > [ 15.406078] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 > [ 15.406089] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 > [ 15.406095] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 > [ 15.485516] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.486080] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a > [ 15.486117] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040560145 state to 000000005e0e4b0a > [ 15.486145] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a > [ 15.486179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000044e6fdf state to 000000005e0e4b0a > [ 15.486215] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a > [ 15.491766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a > [ 15.491810] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a > [ 15.491933] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a > [ 15.491973] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000577ba344 state to 000000005e0e4b0a > [ 15.491999] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a > [ 15.492030] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c21eb74a state to 000000005e0e4b0a > [ 15.492064] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a > [ 15.496975] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a > [ 15.497010] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a > [ 16.356678] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] > [ 16.356693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] > [ 16.356708] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.356722] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000548ffd9d state to 000000006e858879 > [ 16.356739] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e1f1c0f1 state to 000000006e858879 > [ 16.356764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000548ffd9d > [ 16.356783] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000e1f1c0f1 > [ 16.356800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006e858879 > [ 16.356811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000030b3daa1 state to 000000006e858879 > [ 16.356822] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [NOCRTC] > [ 16.356832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [CRTC:51:pipe A] > [ 16.356859] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.356868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 16.356874] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 16.356915] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 16.356943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm > [ 16.356968] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 > [ 16.356988] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 > [ 16.357008] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 > [ 16.357022] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.375313] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.375339] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 16.375389] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] > [ 16.375408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] > [ 16.375426] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.375445] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000040560145 state to 000000006e858879 > [ 16.375461] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c8047799 state to 000000006e858879 > [ 16.375481] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 0000000040560145 > [ 16.375498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 00000000c8047799 > [ 16.375514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006e858879 > [ 16.375531] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000679f9f9c state to 000000006e858879 > [ 16.375548] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [NOCRTC] > [ 16.375564] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [CRTC:72:pipe B] > [ 16.375583] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.375603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 16.375612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 16.375678] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 16.375718] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm > [ 16.375749] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 > [ 16.375779] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 > [ 16.375838] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 > [ 16.375862] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.380403] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.380432] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 16.466326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.466379] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c21eb74a state to 000000006e858879 > [ 16.466420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000577ba344 state to 000000006e858879 > [ 16.466461] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c21eb74a to [CRTC:51:pipe A] > [ 16.466499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c21eb74a > [ 16.466536] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.466670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 16.466727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c8a5ea85 state to 000000006e858879 > [ 16.466807] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 16.466878] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 16.466943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 16.467007] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 16.467049] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.467221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.467261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 16.467316] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.467354] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e1f1c0f1 state to 000000006e858879 > [ 16.467390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000548ffd9d state to 000000006e858879 > [ 16.467430] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000e1f1c0f1 to [CRTC:72:pipe B] > [ 16.467467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1f1c0f1 > [ 16.467502] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.467614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 > [ 16.467660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002570d1d3 state to 000000006e858879 > [ 16.467736] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 16.467826] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 16.467926] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 16.467996] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 16.468047] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.468167] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.468223] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 17.212714] [drm:drm_mode_addfb2 [drm]] [FB:143] > [ 17.262341] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 17.262375] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 17.262413] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 17.262454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 17.262494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 17.262529] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 17.262568] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 17.309802] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 17.325138] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 17.363673] [drm:drm_mode_addfb2 [drm]] [FB:144] > [ 17.389030] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 17.389043] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e83b417b state to 000000004c5d43a8 > [ 17.389056] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c7c74428 state to 000000004c5d43a8 > [ 17.389066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000c7c74428 > [ 17.389074] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 17.389129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.389159] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking > [ 17.389353] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 17.389363] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004440fec8 state to 00000000ad3ae327 > [ 17.389375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000339eee21 state to 00000000ad3ae327 > [ 17.389384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000339eee21 > [ 17.389392] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 17.389436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.389452] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking > [ 17.391197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000000e9d0b2a > [ 17.391354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.391422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1364291 > [ 17.391485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.397162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 17.397187] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 17.405872] [drm:drm_mode_addfb2 [drm]] [FB:145] > [ 17.407506] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 17.408550] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 17.408565] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a > [ 17.408580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a > [ 17.408590] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 17.408600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a > [ 17.408611] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000246ed832 > [ 17.408621] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a > [ 17.408716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.408748] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking > [ 17.408968] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 17.408980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 00000000505d8d8e > [ 17.408990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae9d6619 state to 00000000505d8d8e > [ 17.409000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000ae9d6619 > [ 17.409009] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 17.409053] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.409068] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 17.413297] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 17.413439] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 17.413467] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 17.413503] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 17.413565] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 17.414011] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 17.414382] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 17.415995] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 17.416021] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 17.416045] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 17.416334] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 17.422310] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 17.422857] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.422873] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 17.422882] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 17.422890] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.423105] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.423116] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.423125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.423133] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.423147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423156] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423172] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423187] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423214] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423243] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423259] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 17.423276] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 17.423294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 17.423312] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 17.423329] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 17.423347] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 17.423364] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.423383] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.423398] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.423410] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.423424] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 17.423439] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 17.423448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.423456] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.423464] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 17.423473] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 17.423481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.423493] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.423500] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 17.423508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.423515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.423523] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.423530] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 17.423538] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 17.423545] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 17.423553] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 17.423560] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 17.423568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.423575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.423582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423590] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423597] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423605] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423612] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 17.423620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.423627] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.423635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.423642] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 17.423723] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 17.423770] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 17.424191] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 17.424555] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 17.425122] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a > [ 17.425141] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a > [ 17.426094] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 17.426117] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 17.426138] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 17.426420] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 17.430296] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 17.430309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 17.432359] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 17.432885] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.432895] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 17.432902] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 17.432909] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.433097] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.433104] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.433112] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.433119] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.433126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433132] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433139] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433159] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433173] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433181] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 17.433188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 17.433195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 17.433201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 17.433208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 17.433215] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 17.433221] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.433228] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.433235] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.433241] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.433248] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 17.433255] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 17.433261] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.433268] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.433275] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 17.433282] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 17.433288] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.433295] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.433301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 17.433308] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.433315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.433321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.433328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 17.433335] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 17.433342] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 17.433348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 17.433355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 17.433362] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.433368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.433375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 17.433408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.433414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.433421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.433428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 17.433471] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 17.433509] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 17.433520] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 17.433527] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 17.433550] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 17.433849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 17.433869] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 17.434149] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 17.434171] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 17.434191] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 17.434211] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 17.436907] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 17.436928] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 17.437223] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 17.437240] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 17.437518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 17.437537] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 17.437542] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 17.437550] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 17.437568] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 17.437863] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 17.437881] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 17.438159] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 17.438181] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 17.438199] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 17.438217] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 17.441061] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 17.441079] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 17.441325] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 17.441343] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 17.441621] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 17.441640] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 17.441644] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 17.441651] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 17.441669] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 17.441962] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 17.441979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 17.442257] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 17.442279] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 17.442296] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 17.442313] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 17.445210] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 17.445228] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 17.445474] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 17.445491] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 17.445708] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 17.445727] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 17.445731] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 19.033461] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 19.033498] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 0000000014564192 > [ 19.033528] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003a6df13b state to 0000000014564192 > [ 19.033539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000003a6df13b > [ 19.033550] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 19.033613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 19.033632] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 19.033658] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 19.033668] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000cb785d4f > [ 19.033699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000cb785d4f > [ 19.033708] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005752a175 > [ 19.033715] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 19.033841] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 19.033872] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 19.041962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 19.041981] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 19.047276] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 19.047303] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 20.006109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000009e366e46 > [ 20.006141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.006159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004fa5331c > [ 20.006182] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.016139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.016171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.016190] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.016223] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.026083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.026110] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.026125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.026148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.036073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.036098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.036113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.036136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.046072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.046097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.046112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.046135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.056072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.056097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.056112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.056135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.066083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.066108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.066123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.066146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.076072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.076096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.076111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.076134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.096072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.096097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.096112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.096135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.104071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.104096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.104110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.104134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.114071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.114096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.114111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.114134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.124071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.124097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.124111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.124135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.134070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.134095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.134109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.134133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.144072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.144097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.144112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.144136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.154070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.154095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.154110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.154133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.164071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.164095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.164110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.164133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.174076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.174101] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.174115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.174139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.184071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.184095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.184110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.184133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.194072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.194096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.194111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.194134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.204074] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.204099] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.204114] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.204138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.214071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.214095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.214110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.214133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.234073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.234098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.234112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.234135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.274070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.274096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.274111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.274135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.314088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.314124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.314142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.314166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.334077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.334104] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.334119] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.334142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.354068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.354093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.354108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.354130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.376068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.376093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.376108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.376131] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.394073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.394098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.394113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.394135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.416078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.416114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.416129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.416152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.422661] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 > [ 20.422673] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000017b31376 state to 00000000c58cae11 > [ 20.422683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000009d80489d state to 00000000c58cae11 > [ 20.422695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000009d80489d > [ 20.422710] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 > [ 20.422856] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.422898] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking > [ 20.422943] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 > [ 20.422952] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c88e1744 state to 000000003fe34687 > [ 20.422963] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a3a0e390 state to 000000003fe34687 > [ 20.422972] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000a3a0e390 > [ 20.422979] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 > [ 20.423027] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.423038] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking > [ 20.442150] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 > [ 20.442172] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 > [ 20.444199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 > [ 20.444330] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.444367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 > [ 20.444407] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.447302] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 > [ 20.447322] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 > [ 20.447342] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c > [ 20.447364] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005a9a925a state to 0000000072b4047c > [ 20.447382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000072b4047c > [ 20.447401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000000f06e049 > [ 20.447415] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c > [ 20.447562] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.447597] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking > [ 20.447635] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f12def7f > [ 20.447648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000019eb48a0 state to 00000000f12def7f > [ 20.447661] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000f12def7f > [ 20.447672] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 > [ 20.447682] [drm:drm_atomic_check_only [drm]] checking 00000000f12def7f > [ 20.447804] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.447847] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f12def7f nonblocking > [ 20.458776] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c > [ 20.458805] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c > [ 20.464009] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f12def7f > [ 20.464033] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c > [ 20.464062] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f12def7f > [ 20.464080] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d5af1617 state to 0000000072b4047c > [ 20.464097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008416fa19 state to 0000000072b4047c > [ 20.464113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000008416fa19 > [ 20.464129] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c > [ 20.464285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.464318] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking > [ 20.464369] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 20.464382] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 00000000cb785d4f > [ 20.464393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac1a10e7 state to 00000000cb785d4f > [ 20.464405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000ac1a10e7 > [ 20.464417] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 20.464521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.464539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 20.475453] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c > [ 20.475483] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c > [ 20.476153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 > [ 20.476220] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.476244] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 > [ 20.476294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.480583] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 20.480602] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 20.480623] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 20.480648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ff2d6d95 state to 0000000014564192 > [ 20.480667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ae9d6619 state to 0000000014564192 > [ 20.480684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000ae9d6619 > [ 20.480699] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 20.480847] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.480875] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 20.480904] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 20.480917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000505d8d8e > [ 20.480932] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003a6df13b state to 00000000505d8d8e > [ 20.480944] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003a6df13b > [ 20.480955] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 20.481001] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.481025] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 20.492049] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 20.492073] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 20.497297] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 20.497326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a > [ 20.497344] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 20.497358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a > [ 20.497371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008112a9e3 state to 00000000ae0bb06a > [ 20.497384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000008112a9e3 > [ 20.497397] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a > [ 20.497510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.497533] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking > [ 20.497566] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff > [ 20.497580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 0000000094adecff > [ 20.497593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 0000000094adecff > [ 20.497606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 > [ 20.497616] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff > [ 20.497695] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.497714] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking > [ 20.506275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000010080940 > [ 20.506427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.506500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000002603cbe2 > [ 20.506557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.508755] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a > [ 20.508773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a > [ 20.513913] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff > [ 20.513934] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff > [ 20.513955] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a > [ 20.513980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000ae0bb06a > [ 20.513997] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a > [ 20.514015] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000246ed832 > [ 20.514028] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a > [ 20.514142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.514173] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking > [ 20.514201] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 20.514212] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000505d8d8e > [ 20.514223] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000638906d4 state to 00000000505d8d8e > [ 20.514235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000638906d4 > [ 20.514247] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 20.514285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.514301] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 20.525405] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a > [ 20.525425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a > [ 20.530631] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 20.530656] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 20.530680] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 0000000014564192 > [ 20.530693] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 20.530711] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000014564192 > [ 20.530728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000000f06e049 > [ 20.530743] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 20.530859] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.530884] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 20.530917] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 20.530930] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000cb785d4f > [ 20.530941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008416fa19 state to 00000000cb785d4f > [ 20.530953] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000008416fa19 > [ 20.530963] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 20.531011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.531031] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 20.536073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 > [ 20.536114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.536134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 > [ 20.536168] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.542007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 20.542022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 20.547157] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 20.547169] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 20.554047] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 > [ 20.554089] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.554106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 > [ 20.554133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.947422] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f09b7a6e > [ 20.947449] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f1af5452 state to 00000000f09b7a6e > [ 20.947459] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057d750db state to 00000000f09b7a6e > [ 20.947469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000057d750db > [ 20.947479] [drm:drm_atomic_check_only [drm]] checking 00000000f09b7a6e > [ 20.947522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.947539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f09b7a6e nonblocking > [ 20.947567] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000b295a68 > [ 20.947578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000fe6b27d8 state to 000000000b295a68 > [ 20.947586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3db559a state to 000000000b295a68 > [ 20.947595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000f3db559a > [ 20.947602] [drm:drm_atomic_check_only [drm]] checking 000000000b295a68 > [ 20.947692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.947707] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000b295a68 nonblocking > [ 20.958693] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f09b7a6e > [ 20.958709] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f09b7a6e > [ 20.963851] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000b295a68 > [ 20.963860] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000b295a68 > [ 21.143151] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 21.143174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000046499d3 > [ 21.143186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b830a5b4 state to 00000000046499d3 > [ 21.143195] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000b830a5b4 > [ 21.143205] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 21.143259] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.143281] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 21.143326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.143336] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf > [ 21.143346] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 0000000064a524bf > [ 21.143356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000fe3c3ec4 > [ 21.143363] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.143448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.143465] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.158722] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 21.158733] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 21.163865] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.163876] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.317441] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 > [ 21.317452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000590d9307 > [ 21.317460] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 00000000590d9307 > [ 21.317469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000005ba888f4 > [ 21.317477] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 > [ 21.317520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.317539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking > [ 21.317562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.317578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e2607dec state to 0000000064a524bf > [ 21.317588] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 0000000064a524bf > [ 21.317598] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 > [ 21.317606] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.317634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.317682] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.325356] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 > [ 21.325365] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 > [ 21.330594] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.330605] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.453357] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 21.453368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 000000008bd3a823 > [ 21.453377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 > [ 21.453386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000419d8fd6 > [ 21.453428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 21.453462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.453476] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 21.453492] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 21.453532] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 > [ 21.453560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 > [ 21.453568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c > [ 21.453577] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 21.453622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.453635] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 21.463882] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 21.463892] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 21.475399] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 21.475425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 21.637365] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 21.637400] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000008bd3a823 > [ 21.637411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 > [ 21.637420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 > [ 21.637428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 21.637463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.637477] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 21.637525] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 21.637560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 > [ 21.637575] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007ae821d2 state to 00000000cff3fe76 > [ 21.637586] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000007ae821d2 > [ 21.637596] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 21.637625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.637639] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 21.647227] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 21.647237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 21.658762] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 21.658773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 21.781319] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 21.781359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 00000000046499d3 > [ 21.781367] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 00000000046499d3 > [ 21.781375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 > [ 21.781383] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 21.781435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.781450] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 21.781490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.781518] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf > [ 21.781529] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 0000000064a524bf > [ 21.781539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 > [ 21.781547] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.781576] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.781612] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.792098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 21.792109] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 21.797229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.797242] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.941164] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.941174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf > [ 21.941206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 0000000064a524bf > [ 21.941215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000010080940 > [ 21.941223] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.941263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.941280] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.941298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 21.941307] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 > [ 21.941322] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 > [ 21.941337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 > [ 21.941345] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 21.941375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.941387] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 21.958730] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.958740] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.963967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 21.963978] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 22.037360] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 22.037370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000008bd3a823 > [ 22.037402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 > [ 22.037414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000f4690955 > [ 22.037422] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 22.037456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.037470] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 22.037494] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 22.037552] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 > [ 22.037560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 > [ 22.037569] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c > [ 22.037583] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 22.037620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.037633] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 22.047250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 22.047261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 22.058781] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 22.058792] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 22.237345] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 22.237355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 000000008bd3a823 > [ 22.237363] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 > [ 22.237372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000419d8fd6 > [ 22.237380] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 22.237430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.237444] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 22.237460] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 22.237469] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 > [ 22.237503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005ba888f4 state to 00000000cff3fe76 > [ 22.237533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005ba888f4 > [ 22.237550] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 22.237580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.237609] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 22.247260] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 22.247270] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 22.258795] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 22.258806] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 22.349362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 > [ 22.349402] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000009f1364b2 > [ 22.349412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007ae821d2 state to 000000009f1364b2 > [ 22.349421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000007ae821d2 > [ 22.349429] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 > [ 22.349478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.349492] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking > [ 22.349527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 22.349560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000046499d3 > [ 22.349568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 00000000046499d3 > [ 22.349578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 > [ 22.349587] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 22.349614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.349638] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 22.358789] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 > [ 22.358802] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 > [ 22.363927] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 22.363940] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 22.429393] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 22.429406] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf > [ 22.429440] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 0000000064a524bf > [ 22.429449] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 > [ 22.429456] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 22.429498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.429511] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 22.429532] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 22.429540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 > [ 22.429547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 > [ 22.429556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 > [ 22.429563] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 22.429597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.429616] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 22.442367] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 22.442417] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 22.447561] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 22.447614] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 22.528747] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 > [ 22.528805] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000009f1364b2 > [ 22.528847] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000009f1364b2 > [ 22.528891] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 0000000010080940 > [ 22.528932] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 > [ 22.529197] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.529272] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking > [ 22.529370] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 > [ 22.529413] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed110662 state to 00000000590d9307 > [ 22.529452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000590d9307 > [ 22.529494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c > [ 22.529530] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 > [ 22.529653] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.529710] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking > [ 22.542364] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 > [ 22.542414] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 > [ 22.547589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 > [ 22.547653] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 > [ 23.009536] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000397d0932 > [ 23.009568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000397d0932 > [ 23.009587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 00000000397d0932 > [ 23.009616] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 > [ 23.009643] [drm:drm_atomic_check_only [drm]] checking 00000000397d0932 > [ 23.009799] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.009865] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000397d0932 nonblocking > [ 23.009938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 23.009955] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000008bd3a823 > [ 23.009972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000419d8fd6 state to 000000008bd3a823 > [ 23.009988] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000419d8fd6 > [ 23.010003] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 23.010108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.010143] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 23.025518] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000397d0932 > [ 23.025539] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000397d0932 > [ 23.030677] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 23.030696] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 23.071823] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000050c6aee > [ 23.071864] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.071900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c8e13b43 > [ 23.071924] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.392525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000e59e4cfa > [ 23.392582] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.392624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000057d750db > [ 23.392689] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.607003] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 23.607025] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000003ce8e850 state to 00000000ad3ae327 > [ 23.607036] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000ad3ae327 > [ 23.607047] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000003ce8e850 to [NOCRTC] > [ 23.607056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000003ce8e850 > [ 23.607065] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 23.607134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 23.607157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000233ad802 state to 00000000ad3ae327 > [ 23.607179] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 23.607195] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.607210] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.607229] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.607244] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 > [ 23.624682] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 23.624698] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 23.624736] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 23.624745] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000024c9c604 state to 00000000ad3ae327 > [ 23.624757] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 00000000ad3ae327 > [ 23.624766] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 0000000024c9c604 to [NOCRTC] > [ 23.624774] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000024c9c604 > [ 23.624782] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 23.624840] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 > [ 23.624868] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 00000000ad3ae327 > [ 23.624886] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 23.624901] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.624933] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.624947] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.624957] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 > [ 23.624984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 23.624993] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 23.736690] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 23.736728] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 23.736759] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 23.736792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 23.736817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 23.736845] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 23.736873] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 23.778545] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 23.800425] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 23.881716] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 25.150487] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 25.150587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007ede24bf state to 000000006e858879 > [ 25.150641] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000006e858879 > [ 25.150670] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007ede24bf to [CRTC:51:pipe A] > [ 25.150717] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007ede24bf > [ 25.150772] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 25.151167] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.151358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000caa1c353 state to 000000006e858879 > [ 25.151721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.152004] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.152367] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.152468] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.152618] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 25.152866] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 25.152887] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 25.152974] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 25.152988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000bda1a70 state to 000000006e858879 > [ 25.153008] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ea06c3a state to 000000006e858879 > [ 25.153028] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 000000000bda1a70 to [CRTC:72:pipe B] > [ 25.153048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:68:cursor B] state 000000000bda1a70 > [ 25.153060] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 25.153217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.153252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d5e0ab1c state to 000000006e858879 > [ 25.153289] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.153313] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.153339] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.153361] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.153383] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 25.153438] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 25.153449] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 25.153980] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c > [ 25.153999] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b830a5b4 state to 000000004178cf0c > [ 25.154024] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 000000004178cf0c > [ 25.154041] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000b830a5b4 to [NOCRTC] > [ 25.154061] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b830a5b4 > [ 25.154077] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c > [ 25.154166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 25.154206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057b81693 state to 000000004178cf0c > [ 25.154259] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 25.154300] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154379] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c > [ 25.154444] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c > [ 25.154460] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c > [ 25.154493] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c > [ 25.154515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000708b01e5 state to 000000004178cf0c > [ 25.154536] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 000000004178cf0c > [ 25.154560] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000708b01e5 to [NOCRTC] > [ 25.154576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000708b01e5 > [ 25.154587] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c > [ 25.154631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 > [ 25.154655] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ce0e84b state to 000000004178cf0c > [ 25.154695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 25.154722] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154748] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154769] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154792] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c > [ 25.154835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c > [ 25.154848] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c > [ 25.273763] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 > [ 25.273802] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040a74b19 state to 00000000383de8b5 > [ 25.273827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000303042be state to 00000000383de8b5 > [ 25.273843] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000303042be > [ 25.273859] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 > [ 25.274049] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.274099] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking > [ 25.274159] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 > [ 25.274183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000f55d2354 > [ 25.274209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009ff1aeec state to 00000000f55d2354 > [ 25.274223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000009ff1aeec > [ 25.274237] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 > [ 25.274352] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.274385] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking > [ 25.292269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 > [ 25.292288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 > [ 25.297446] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 > [ 25.297472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 > [ 25.297764] [drm:drm_mode_addfb2 [drm]] [FB:133] > [ 25.309363] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 > [ 25.309501] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000086edd36c state to 00000000590d9307 > [ 25.309726] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007d32f8a2 state to 00000000590d9307 > [ 25.309825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:31:plane 1A] state 000000007d32f8a2 > [ 25.309919] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 > [ 25.310337] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.310572] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking > [ 25.311148] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 > [ 25.311195] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 000000009f1364b2 > [ 25.311226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000da8e7b56 state to 000000009f1364b2 > [ 25.311247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:52:plane 1B] state 00000000da8e7b56 > [ 25.311272] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 > [ 25.311530] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.311615] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking > [ 25.313976] audit: type=1400 audit(1591264870.888:28): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 > [ 25.325815] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 > [ 25.325907] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 > [ 25.330935] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 > [ 25.330979] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 > [ 25.348755] audit: type=1400 audit(1591264870.924:29): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 > [ 25.370627] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 > [ 25.370629] Bluetooth: BNEP filters: protocol multicast > [ 25.370633] Bluetooth: BNEP socket layer initialized > [ 25.375033] [drm:drm_mode_addfb2 [drm]] [FB:138] > [ 25.375312] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] > [ 25.375341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] > [ 25.375361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 > [ 25.375375] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004b47c821 state to 0000000033ce3db8 > [ 25.375387] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006ac09869 state to 0000000033ce3db8 > [ 25.375404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000006ac09869 > [ 25.375420] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 > [ 25.375436] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000001f8dd32 state to 0000000033ce3db8 > [ 25.375454] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [NOCRTC] > [ 25.375474] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [CRTC:51:pipe A] > [ 25.375497] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 > [ 25.375537] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 25.375552] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 25.375686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.375746] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 > [ 25.392250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 > [ 25.392268] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 > [ 25.392303] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] > [ 25.392323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] > [ 25.392335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.392348] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 > [ 25.392359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 > [ 25.392372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 > [ 25.392384] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 > [ 25.392396] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000034523972 state to 000000009a35bdf3 > [ 25.392410] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [NOCRTC] > [ 25.392421] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [CRTC:72:pipe B] > [ 25.392434] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.392444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 25.392450] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 25.392498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.392518] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 > [ 25.397429] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.397444] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.397934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.397958] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005cff5841 state to 000000009a35bdf3 > [ 25.397971] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.397987] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fa10941b state to 000000009a35bdf3 > [ 25.398000] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 > [ 25.414143] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.414156] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.414191] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] > [ 25.414202] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] > [ 25.414212] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.414223] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 > [ 25.414232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 > [ 25.414244] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:] for [CRTC:72:pipe B] state 00000000a5b8210f > [ 25.414253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 > [ 25.414265] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 > [ 25.414277] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000083c2e296 state to 000000009a35bdf3 > [ 25.414286] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [NOCRTC] > [ 25.414295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [CRTC:72:pipe B] > [ 25.414307] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.414316] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 25.414321] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 25.414366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.414381] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 > [ 25.430771] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.430790] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.587615] [drm:drm_mode_addfb2 [drm]] [FB:137] > [ 25.588562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000607204c5 > [ 25.588594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 00000000607204c5 > [ 25.588614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005aa8cfac state to 00000000607204c5 > [ 25.588633] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000005aa8cfac > [ 25.588649] [drm:drm_atomic_check_only [drm]] checking 00000000607204c5 > [ 25.588824] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.588864] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000607204c5 nonblocking > [ 25.589160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000006db89b4 > [ 25.589182] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 0000000006db89b4 > [ 25.589198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000ca4c9ba state to 0000000006db89b4 > [ 25.589216] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000000ca4c9ba > [ 25.589231] [drm:drm_atomic_check_only [drm]] checking 0000000006db89b4 > [ 25.589319] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.589346] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000006db89b4 nonblocking > [ 25.609114] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000607204c5 > [ 25.609175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000607204c5 > [ 25.614340] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000006db89b4 > [ 25.614399] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000006db89b4 > [ 25.631657] [drm:drm_mode_addfb2 [drm]] [FB:147] > [ 25.632478] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a82a142d > [ 25.632494] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000bfbd51fd state to 00000000a82a142d > [ 25.632510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004b6af36c state to 00000000a82a142d > [ 25.632526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004b6af36c > [ 25.632545] [drm:drm_atomic_check_only [drm]] checking 00000000a82a142d > [ 25.632706] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.632837] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a82a142d nonblocking > [ 25.633235] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a9357def > [ 25.633289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000780eaeb2 state to 00000000a9357def > [ 25.633327] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ce7ebae0 state to 00000000a9357def > [ 25.633378] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 00000000ce7ebae0 > [ 25.633406] [drm:drm_atomic_check_only [drm]] checking 00000000a9357def > [ 25.633671] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.633810] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a9357def nonblocking > [ 25.659221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a82a142d > [ 25.659354] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a82a142d > [ 25.664414] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a9357def > [ 25.664483] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 25.664520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000cb785d4f > [ 25.664540] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a9357def > [ 25.664556] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000024c9c604 state to 00000000cb785d4f > [ 25.664570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000024c9c604 > [ 25.664595] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 25.664849] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.664952] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 25.665286] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c > [ 25.665325] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 0000000072b4047c > [ 25.665373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 0000000072b4047c > [ 25.665410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000002fdb83bd > [ 25.665470] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c > [ 25.665744] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.665883] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking > [ 25.681106] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c > [ 25.681311] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c > [ 25.692362] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 25.692394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c329590e > [ 25.692419] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 25.692437] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 00000000c329590e > [ 25.692453] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002592f0c5 state to 00000000c329590e > [ 25.692466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002592f0c5 > [ 25.692479] [drm:drm_atomic_check_only [drm]] checking 00000000c329590e > [ 25.692638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.692670] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c329590e nonblocking > [ 25.692784] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.692797] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 000000009a35bdf3 > [ 25.692808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000044e6fdf state to 000000009a35bdf3 > [ 25.692820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000044e6fdf > [ 25.692830] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.692941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.692966] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009a35bdf3 nonblocking > [ 25.709084] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c329590e > [ 25.709105] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c329590e > [ 25.714310] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.714357] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.732545] [drm:drm_mode_addfb2 [drm]] [FB:148] > [ 25.732641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 > [ 25.732658] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cee74316 state to 000000003fe34687 > [ 25.732679] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004ceca9e7 state to 000000003fe34687 > [ 25.732693] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004ceca9e7 > [ 25.732715] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 > [ 25.732769] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.732802] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking > [ 25.733102] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 > [ 25.733225] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a7e0ad69 state to 00000000c58cae11 > [ 25.733274] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002b75481e state to 00000000c58cae11 > [ 25.733300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 000000002b75481e > [ 25.733353] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 > [ 25.733574] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.733722] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking > [ 25.742433] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 > [ 25.742504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 > [ 25.747591] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 > [ 25.747612] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 > [ 25.747631] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 > [ 25.747646] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 0000000033635145 > [ 25.747660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000a08190f state to 0000000033635145 > [ 25.747674] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:31:plane 1A] state 000000000a08190f > [ 25.747686] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 > [ 25.747857] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.747911] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking > [ 25.748026] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f > [ 25.748049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c56546ad state to 00000000e7507c6f > [ 25.748062] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008ef93bc9 state to 00000000e7507c6f > [ 25.748078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:52:plane 1B] state 000000008ef93bc9 > [ 25.748091] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f > [ 25.748209] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.748234] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e7507c6f nonblocking > [ 25.759225] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 > [ 25.759284] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 > [ 25.764229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f > [ 25.764250] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 > [ 25.764265] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f > [ 25.764284] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d304b4ce state to 00000000a72ea9e2 > [ 25.764297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007150ba46 state to 00000000a72ea9e2 > [ 25.764311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000007150ba46 > [ 25.764322] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 > [ 25.764463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.764494] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking > [ 25.764530] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 25.764542] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7bb92f2 state to 000000004c5d43a8 > [ 25.764552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a4812a5a state to 000000004c5d43a8 > [ 25.764564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000a4812a5a > [ 25.764574] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 25.764643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.764660] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking > [ 25.792509] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 > [ 25.792625] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 > [ 25.797616] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 25.797650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 25.800508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 > [ 25.800567] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000859f7d52 state to 0000000033635145 > [ 25.800618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000065e53c0c state to 0000000033635145 > [ 25.800656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000065e53c0c > [ 25.800702] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 > [ 25.800976] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.801119] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking > [ 25.801505] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 > [ 25.801543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 00000000f55d2354 > [ 25.801584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a1a9a3bd state to 00000000f55d2354 > [ 25.801609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000a1a9a3bd > [ 25.801638] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 > [ 25.801969] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.802166] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking > [ 25.825728] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 > [ 25.825748] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 > [ 25.830902] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 > [ 25.830932] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 > [ 25.837586] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 25.837660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 00000000a7c3d9eb > [ 25.837689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000de4c477a state to 00000000a7c3d9eb > [ 25.837726] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000de4c477a > [ 25.837761] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 25.837997] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.838175] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking > [ 25.838378] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 25.838452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000006e8a3f03 > [ 25.838489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c00467ed state to 000000006e8a3f03 > [ 25.838516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000c00467ed > [ 25.838580] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 25.838855] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.839042] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking > [ 25.864311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 25.864356] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 25.875747] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 25.875867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 25.876790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9b8f040 > [ 25.876815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ea06c3a state to 00000000f9b8f040 > [ 25.876837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cc7821e8 state to 00000000f9b8f040 > [ 25.876856] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000cc7821e8 > [ 25.876876] [drm:drm_atomic_check_only [drm]] checking 00000000f9b8f040 > [ 25.877085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.877133] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f9b8f040 nonblocking > [ 25.877191] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 > [ 25.877221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 000000005795e3f4 > [ 25.877240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000466fb708 state to 000000005795e3f4 > [ 25.877257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000466fb708 > [ 25.877271] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 > [ 25.877359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.877378] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking > [ 25.909168] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9b8f040 > [ 25.909283] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9b8f040 > [ 25.914266] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 > [ 25.914289] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 > [ 25.933490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b > [ 25.933516] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040ff38e3 state to 00000000d223d21b > [ 25.933535] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002062a680 state to 00000000d223d21b > [ 25.933551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002062a680 > [ 25.933566] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b > [ 25.933717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.933757] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking > [ 25.933867] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 > [ 25.933906] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005ea21f1d state to 000000005795e3f4 > [ 25.933940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000038b73e52 state to 000000005795e3f4 > [ 25.933995] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000038b73e52 > [ 25.934034] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 > [ 25.934359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.934554] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking > [ 25.959269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b > [ 25.959471] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b > [ 25.964230] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 > [ 25.964288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 > [ 25.965190] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 > [ 25.965227] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000383de8b5 > [ 25.965252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a1a9a3bd state to 00000000383de8b5 > [ 25.965276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000a1a9a3bd > [ 25.965293] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 > [ 25.965486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.965520] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking > [ 25.965577] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 > [ 25.965598] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000f55d2354 > [ 25.965625] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3527d8e state to 00000000f55d2354 > [ 25.965654] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000f3527d8e > [ 25.965674] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 > [ 25.965862] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.965959] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking > [ 25.966673] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 > [ 25.966697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bbab38cb state to 0000000033635145 > [ 25.966723] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000033635145 > [ 25.966747] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000bbab38cb to [CRTC:51:pipe A] > [ 25.966765] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000bbab38cb > [ 25.966785] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 > [ 25.966981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.967029] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 0000000033635145 > [ 25.967093] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.967142] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.967186] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.967233] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.967258] [drm:drm_atomic_commit [drm]] committing 0000000033635145 > [ 25.970239] audit: type=1400 audit(1591264871.544:30): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 > [ 25.971457] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f > [ 25.971516] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ffb1c30d state to 00000000e7507c6f > [ 25.971540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c56546ad state to 00000000e7507c6f > [ 25.971557] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ffb1c30d to [CRTC:51:pipe A] > [ 25.971574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:150] for [PLANE:47:cursor A] state 00000000ffb1c30d > [ 25.971595] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f > [ 25.971816] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.971916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035459c5a state to 00000000e7507c6f > [ 25.972107] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.972162] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.972196] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.972235] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.972271] [drm:drm_atomic_commit [drm]] committing 00000000e7507c6f > [ 25.976346] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d > [ 25.976369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000056d83168 state to 000000000949282d > [ 25.976387] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 000000000949282d > [ 25.976401] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000056d83168 to [CRTC:51:pipe A] > [ 25.976412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:151] for [PLANE:47:cursor A] state 0000000056d83168 > [ 25.976424] [drm:drm_atomic_check_only [drm]] checking 000000000949282d > [ 25.976565] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.976600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000000949282d > [ 25.976650] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.976680] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.976701] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.976729] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.976744] [drm:drm_atomic_commit [drm]] committing 000000000949282d > [ 25.981361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059bcf2ab > [ 25.981377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000048a2243e state to 0000000059bcf2ab > [ 25.981395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000059bcf2ab > [ 25.981415] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000048a2243e to [CRTC:51:pipe A] > [ 25.981427] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:152] for [PLANE:47:cursor A] state 0000000048a2243e > [ 25.981439] [drm:drm_atomic_check_only [drm]] checking 0000000059bcf2ab > [ 25.981587] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.981634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035f866f8 state to 0000000059bcf2ab > [ 25.981732] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.981763] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.981793] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.981814] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.981833] [drm:drm_atomic_commit [drm]] committing 0000000059bcf2ab > [ 25.986335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 > [ 25.986358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 > [ 25.986378] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 > [ 25.986391] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] > [ 25.986405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:153] for [PLANE:47:cursor A] state 000000007d32f8a2 > [ 25.986419] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 > [ 25.986566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.986601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 > [ 25.986671] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.986697] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.986721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.986745] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.986760] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 > [ 25.990116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059bcf2ab > [ 25.990136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059bcf2ab > [ 25.990147] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d > [ 25.990160] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d > [ 25.990183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f > [ 25.990214] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f > [ 25.990233] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 > [ 25.990250] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 > [ 25.991475] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 > [ 25.991566] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 > [ 25.991821] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 > [ 25.992024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 > [ 25.992099] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 > [ 25.992156] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] > [ 25.992212] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 000000007d32f8a2 > [ 25.992229] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 > [ 25.992294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.992311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 > [ 25.992332] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 > [ 25.992348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 > [ 25.992378] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.992399] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.992427] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.992446] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.992459] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 > [ 25.992502] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 > [ 25.992514] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 > [ 25.997491] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 > [ 25.997513] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 > [ 26.001019] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cd3e6c30 > [ 26.001079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000cd3e6c30 > [ 26.001104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000efc3561e state to 00000000cd3e6c30 > [ 26.001122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000efc3561e > [ 26.001139] [drm:drm_atomic_check_only [drm]] checking 00000000cd3e6c30 > [ 26.001381] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.001424] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cd3e6c30 nonblocking > [ 26.001502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 > [ 26.001517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 00000000fb7b81d0 > [ 26.001539] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000fb7b81d0 > [ 26.001553] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000008a19b957 > [ 26.001564] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 > [ 26.001663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.001718] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fb7b81d0 nonblocking > [ 26.025633] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cd3e6c30 > [ 26.025657] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cd3e6c30 > [ 26.031038] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 > [ 26.031111] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 > [ 26.032140] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d > [ 26.032186] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002822e6ce state to 000000000949282d > [ 26.032214] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 000000000949282d > [ 26.032242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005ba888f4 > [ 26.032278] [drm:drm_atomic_check_only [drm]] checking 000000000949282d > [ 26.032460] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.032551] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000949282d nonblocking > [ 26.032715] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 > [ 26.032747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000048287824 > [ 26.032774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000010080940 state to 0000000048287824 > [ 26.032814] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000010080940 > [ 26.032843] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 > [ 26.033033] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.033133] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking > [ 26.058971] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d > [ 26.058986] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d > [ 26.064135] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 > [ 26.064151] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 > [ 26.065142] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f > [ 26.065161] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000db144c3f > [ 26.065176] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003338987c state to 00000000db144c3f > [ 26.065189] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003338987c > [ 26.065202] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f > [ 26.065341] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.065389] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking > [ 26.065427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 > [ 26.065439] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 0000000048287824 > [ 26.065452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003d3598b9 state to 0000000048287824 > [ 26.065464] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003d3598b9 > [ 26.065477] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 > [ 26.065545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.065571] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking > [ 26.092355] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f > [ 26.092369] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f > [ 26.097513] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 > [ 26.097527] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 > [ 26.098050] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 26.098064] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7bb92f2 state to 000000004c5d43a8 > [ 26.098076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f17f63d state to 000000004c5d43a8 > [ 26.098088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000008f17f63d > [ 26.098098] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 26.098144] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.098173] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking > [ 26.098205] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 > [ 26.098216] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d304b4ce state to 00000000a72ea9e2 > [ 26.098226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000001a43d2f state to 00000000a72ea9e2 > [ 26.098237] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000001a43d2f > [ 26.098247] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 > [ 26.098291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.098309] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking > [ 26.125651] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 26.125679] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 26.130834] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 > [ 26.130867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 > [ 26.131366] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 26.131383] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 00000000ad3ae327 > [ 26.131396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062957589 state to 00000000ad3ae327 > [ 26.131409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000062957589 > [ 26.131421] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 26.131472] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.131499] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking > [ 26.131531] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 > [ 26.131543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 000000009ab7d7a2 > [ 26.131553] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e42a1bac state to 000000009ab7d7a2 > [ 26.131565] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000e42a1bac > [ 26.131577] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 > [ 26.131662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.131685] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking > [ 26.158952] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 26.158972] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 26.164140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 > [ 26.164157] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 > [ 26.164688] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 > [ 26.164707] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c88e1744 state to 000000009ab7d7a2 > [ 26.164721] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002b4570b0 state to 000000009ab7d7a2 > [ 26.164732] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000002b4570b0 > [ 26.164741] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 > [ 26.164779] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.164794] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking > [ 26.164817] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 26.164828] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cfd8c976 state to 00000000ad3ae327 > [ 26.164837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000217fb779 state to 00000000ad3ae327 > [ 26.164846] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000217fb779 > [ 26.164854] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 26.164902] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.164925] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking > [ 26.192294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 > [ 26.192316] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 > [ 26.197558] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 26.197586] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 26.198086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 > [ 26.198107] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000005795e3f4 > [ 26.198125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d5e0ab1c state to 000000005795e3f4 > [ 26.198142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000d5e0ab1c > [ 26.198161] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 > [ 26.198224] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.198254] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking > [ 26.198298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b > [ 26.198316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 00000000d223d21b > [ 26.198334] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001aa4b64b state to 00000000d223d21b > [ 26.198353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001aa4b64b > [ 26.198369] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b > [ 26.198496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.198527] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking > [ 26.214153] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b > [ 26.214175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b > [ 26.225632] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 > [ 26.225662] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 > [ 26.462632] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 > [ 26.462656] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007d558a50 state to 00000000e7804b44 > [ 26.462673] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 > [ 26.462708] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006d587bbb state to 00000000e7804b44 > [ 26.462727] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 > [ 26.475706] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 > [ 26.475726] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 > [ 26.475759] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 > [ 26.475794] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008598d75f state to 00000000e7804b44 > [ 26.475808] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 > [ 26.475829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 00000000e7804b44 > [ 26.475857] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 > [ 26.480907] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 > [ 26.480929] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 > [ 26.490104] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b > [ 26.490125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000d223d21b > [ 26.490143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000bda1a70 state to 00000000d223d21b > [ 26.490160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000000bda1a70 > [ 26.490174] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b > [ 26.490263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.490296] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking > [ 26.490379] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005b4fe663 > [ 26.490395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 000000005b4fe663 > [ 26.490412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ad4d2a9 state to 000000005b4fe663 > [ 26.490432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000004ad4d2a9 > [ 26.490446] [drm:drm_atomic_check_only [drm]] checking 000000005b4fe663 > [ 26.490577] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.490612] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005b4fe663 nonblocking > [ 26.508990] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b > [ 26.509012] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b > [ 26.514166] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005b4fe663 > [ 26.514193] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005b4fe663 > [ 27.203105] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 > [ 27.203118] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 0000000048287824 > [ 27.203128] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003d3598b9 state to 0000000048287824 > [ 27.203138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003d3598b9 > [ 27.203147] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 > [ 27.203191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.203207] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking > [ 27.203239] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f > [ 27.203248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000db144c3f > [ 27.203257] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006225429c state to 00000000db144c3f > [ 27.203266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000006225429c > [ 27.203274] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f > [ 27.203327] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.203340] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking > [ 27.214214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f > [ 27.214237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f > [ 27.225708] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 > [ 27.225729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 > [ 27.559248] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 27.559266] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000a7c3d9eb > [ 27.559287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000048a2243e state to 00000000a7c3d9eb > [ 27.559302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000048a2243e > [ 27.559317] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 27.559457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.559500] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking > [ 27.559579] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 > [ 27.559595] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000073a3fc87 > [ 27.559614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c26d3cf7 state to 0000000073a3fc87 > [ 27.559630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000c26d3cf7 > [ 27.559644] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 > [ 27.559875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.559954] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking > [ 27.564240] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 > [ 27.564260] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 > [ 27.575734] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 27.575758] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 27.673875] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006fb947e5 > [ 27.673893] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000006fb947e5 > [ 27.673907] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003def6fcc state to 000000006fb947e5 > [ 27.673919] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003def6fcc > [ 27.673930] [drm:drm_atomic_check_only [drm]] checking 000000006fb947e5 > [ 27.674063] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.674111] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006fb947e5 nonblocking > [ 27.674162] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000022edf81f > [ 27.674180] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bfbd51fd state to 0000000022edf81f > [ 27.674205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ba74e4f8 state to 0000000022edf81f > [ 27.674221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000ba74e4f8 > [ 27.674236] [drm:drm_atomic_check_only [drm]] checking 0000000022edf81f > [ 27.674351] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.674383] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000022edf81f nonblocking > [ 27.692395] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006fb947e5 > [ 27.692416] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006fb947e5 > [ 27.697567] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000022edf81f > [ 27.697587] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000022edf81f > [ 28.369864] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 > [ 28.369881] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f4595bbc state to 00000000a72ea9e2 > [ 28.369892] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e0f8f74a state to 00000000a72ea9e2 > [ 28.369905] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000e0f8f74a > [ 28.369917] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 > [ 28.370044] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.370094] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking > [ 28.370128] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e2245646 > [ 28.370140] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000080a25d5d state to 00000000e2245646 > [ 28.370155] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ec8b7f51 state to 00000000e2245646 > [ 28.370165] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000ec8b7f51 > [ 28.370173] [drm:drm_atomic_check_only [drm]] checking 00000000e2245646 > [ 28.370236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.370259] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e2245646 nonblocking > [ 28.392441] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 > [ 28.392456] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 > [ 28.397627] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e2245646 > [ 28.397645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e2245646 > [ 28.441580] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007c7bef8b > [ 28.441593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 000000007c7bef8b > [ 28.441602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 000000007c7bef8b > [ 28.441619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000919acba8 > [ 28.441636] [drm:drm_atomic_check_only [drm]] checking 000000007c7bef8b > [ 28.441807] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.441857] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007c7bef8b nonblocking > [ 28.441895] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e4cb9fa > [ 28.441926] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004f0788b2 state to 000000009e4cb9fa > [ 28.441949] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003cdbbe01 state to 000000009e4cb9fa > [ 28.441966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003cdbbe01 > [ 28.441983] [drm:drm_atomic_check_only [drm]] checking 000000009e4cb9fa > [ 28.442129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.442151] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e4cb9fa nonblocking > [ 28.459102] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007c7bef8b > [ 28.459118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007c7bef8b > [ 28.464290] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e4cb9fa > [ 28.464312] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e4cb9fa > [ 28.722641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 28.722655] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007b516bb0 state to 00000000cb785d4f > [ 28.722664] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dfbf1324 state to 00000000cb785d4f > [ 28.722675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000dfbf1324 > [ 28.722684] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 28.722813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.722835] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 28.722882] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff > [ 28.722908] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003cd98772 state to 0000000094adecff > [ 28.722916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009beb6a90 state to 0000000094adecff > [ 28.722941] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000009beb6a90 > [ 28.722949] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff > [ 28.723029] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.723064] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking > [ 28.742477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 28.742503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 28.747618] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff > [ 28.747633] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff > [ 31.314482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 31.314504] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 33.564502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff > [ 33.564557] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001450a92b state to 0000000094adecff > [ 33.564599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fb9c3f95 state to 0000000094adecff > [ 33.564642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000fb9c3f95 > [ 33.564680] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff > [ 33.564830] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 33.564895] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking > [ 33.564991] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 33.565033] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d785a3ff state to 00000000cb785d4f > [ 33.565068] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001694423a state to 00000000cb785d4f > [ 33.565110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001694423a > [ 33.565145] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 33.565280] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 33.565331] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 33.581360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 33.581410] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 33.592967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff > [ 33.593018] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff > [ 38.906236] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 38.906257] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fbb9145a state to 00000000a7c3d9eb > [ 38.906277] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 38.906300] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031040ef6 state to 00000000a7c3d9eb > [ 38.906317] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb > [ 38.909717] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 38.909729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 38.909751] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 38.909763] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000036e370a5 state to 00000000a7c3d9eb > [ 38.909772] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 38.909789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000021d5013d state to 00000000a7c3d9eb > [ 38.909799] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb > [ 38.914888] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 38.914897] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 38.919179] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 38.919191] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000dbca7270 state to 00000000a7c3d9eb > [ 38.919200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f5920396 state to 00000000a7c3d9eb > [ 38.919210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000f5920396 > [ 38.919219] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 38.919269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 38.919283] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking > [ 38.919307] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3b84e34 > [ 38.919316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007a397cd1 state to 00000000d3b84e34 > [ 38.919324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000d3b84e34 > [ 38.919333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000008a19b957 > [ 38.919340] [drm:drm_atomic_check_only [drm]] checking 00000000d3b84e34 > [ 38.919369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 38.919380] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3b84e34 nonblocking > [ 38.943037] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 38.943049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 38.948213] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3b84e34 > [ 38.948227] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3b84e34 > [ 41.313990] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 41.314011] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000dffa3a5 state to 000000006e8a3f03 > [ 41.314024] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 41.314044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000311fb5cc state to 000000006e8a3f03 > [ 41.314058] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 > [ 41.326599] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 41.326616] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 41.326650] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 41.326666] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000006e8a3f03 > [ 41.326677] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 41.326694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f678ed03 state to 000000006e8a3f03 > [ 41.326708] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 > [ 41.331765] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 41.331799] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 41.340881] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 41.340898] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b35cdb13 state to 0000000014564192 > [ 41.340911] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002bd9f19b state to 0000000014564192 > [ 41.340924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002bd9f19b > [ 41.340936] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 41.341000] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.341031] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 41.341070] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 41.341083] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000505d8d8e > [ 41.341093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000628b1791 state to 00000000505d8d8e > [ 41.341106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000628b1791 > [ 41.341117] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 41.341171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.341187] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 41.359835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 41.359858] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 41.365024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 41.365048] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 41.615782] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000336440de > [ 41.615833] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.617086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 > [ 41.617101] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000029690ea0 > [ 41.617111] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 > [ 41.617127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000043ec3708 state to 0000000029690ea0 > [ 41.617139] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 > [ 41.626562] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 > [ 41.626572] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 > [ 41.626602] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 > [ 41.626612] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000029690ea0 > [ 41.626620] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 > [ 41.626634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dd5969b1 state to 0000000029690ea0 > [ 41.626644] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 > [ 41.631801] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 > [ 41.631813] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 > [ 41.636417] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 41.636431] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005cff5841 state to 000000006e8a3f03 > [ 41.636443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f261da0 state to 000000006e8a3f03 > [ 41.636455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005f261da0 > [ 41.636465] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 41.636505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.636529] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking > [ 41.636564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 > [ 41.636574] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004b47c821 state to 0000000073a3fc87 > [ 41.636583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005b73df2f state to 0000000073a3fc87 > [ 41.636593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000005b73df2f > [ 41.636601] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 > [ 41.636649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.636661] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking > [ 41.659846] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 41.659868] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 41.665021] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 > [ 41.665038] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 > [ 41.694775] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000b6d87631 > [ 41.694823] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 42.188680] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 42.188751] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000568d4c state to 00000000ad3ae327 > [ 42.188815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000041d1b185 state to 00000000ad3ae327 > [ 42.188876] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000000568d4c to [NOCRTC] > [ 42.188938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000568d4c > [ 42.188994] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 42.189140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 42.189200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ccaa86bb state to 00000000ad3ae327 > [ 42.189327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 42.189398] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 42.189464] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 42.189528] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 42.189570] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 > [ 42.189702] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 42.189745] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 1.187465] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported > [ 1.187661] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.06 > [ 1.187663] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 > [ 1.187664] usb usb1: Product: xHCI Host Controller > [ 1.187665] usb usb1: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd > [ 1.187666] usb usb1: SerialNumber: 0000:00:14.0 > [ 1.187773] hub 1-0:1.0: USB hub found > [ 1.187790] hub 1-0:1.0: 16 ports detected > [ 1.187842] libata version 3.00 loaded. > [ 1.191212] ahci 0000:00:17.0: version 3.0 > [ 1.192724] ast 0000:06:00.0: enabling device (0140 -> 0143) > [ 1.199510] pps pps0: new PPS source ptp0 > [ 1.199542] igb 0000:04:00.0: added PHC on eth0 > [ 1.199543] igb 0000:04:00.0: Intel(R) Gigabit Ethernet Network Connection > [ 1.199545] igb 0000:04:00.0: eth0: (PCIe:2.5Gb/s:Width x1) 0c:c4:7a:cf:6c:d7 > [ 1.199618] igb 0000:04:00.0: eth0: PBA No: 010B00-000 > [ 1.199619] igb 0000:04:00.0: Using MSI-X interrupts. 4 rx queue(s), 4 tx queue(s) > [ 1.200298] igb 0000:04:00.0 eno2: renamed from eth0 > [ 1.209686] [drm] Using P2A bridge for configuration > [ 1.209701] [drm] AST 2400 detected > [ 1.209713] [drm] Analog VGA only > [ 1.209731] [drm] dram MCLK=408 Mhz type=1 bus_width=16 size=01000000 > [ 1.209763] [TTM] Zone kernel: Available graphics memory: 16423934 KiB > [ 1.209765] ahci 0000:00:17.0: AHCI 0001.0301 32 slots 4 ports 6 Gbps 0xf impl SATA mode > [ 1.209765] [TTM] Zone dma32: Available graphics memory: 2097152 KiB > [ 1.209766] ahci 0000:00:17.0: flags: 64bit ncq sntf led clo only pio slum part ems deso sadm sds apst > [ 1.209767] [TTM] Initializing pool allocator > [ 1.209775] [TTM] Initializing DMA pool allocator > [ 1.210535] [drm:drm_client_modeset_probe [drm]] > [ 1.210544] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] > [ 1.210551] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] status updated from unknown to connected > [ 1.214089] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter AST i2c bit bus > [ 1.214125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "848x480": 0 33750 848 864 976 1088 480 486 494 517 0x40 0x5 > [ 1.214137] [drm:drm_mode_prune_invalid [drm]] Not using 848x480 mode: NOMODE > [ 1.214145] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:35:VGA-1] probed modes : > [ 1.214158] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 1.214170] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 1.214182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5 > [ 1.214195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.214209] [drm:drm_client_modeset_probe [drm]] connector 35 enabled? yes > [ 1.214223] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 1.214236] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 35 > [ 1.214248] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 35 0 > [ 1.214261] [drm:drm_client_modeset_probe [drm]] found mode 1024x768 > [ 1.214273] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 1920x2048 config > [ 1.214286] [drm:drm_client_modeset_probe [drm]] desired mode 1024x768 set on crtc 33 (0,0) > [ 1.214294] ast 0000:06:00.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane > [ 1.214302] ast 0000:06:00.0: [drm:drm_fb_helper_generic_probe [drm_kms_helper]] surface width(1024), height(768) and bpp(32) > [ 1.214322] [drm:drm_mode_addfb2 [drm]] [FB:36] > [ 1.216083] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 > [ 1.216098] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000706e661a state to 00000000d3c00277 > [ 1.216111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000b376c70b state to 00000000d3c00277 > [ 1.216125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000b376c70b > [ 1.216139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 > [ 1.216153] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1024x768] for [CRTC:33:crtc-0] state 000000000505a613 > [ 1.216166] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane-0] state 00000000706e661a to [CRTC:33:crtc-0] > [ 1.216179] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000706e661a > [ 1.216192] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.216205] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000007c015743 state to 00000000d3c00277 > [ 1.216219] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000007c015743 to [CRTC:33:crtc-0] > [ 1.216231] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 > [ 1.216240] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] mode changed > [ 1.216246] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] enable changed > [ 1.216252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] active changed > [ 1.216258] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 1.216265] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] using [ENCODER:34:DAC-34] on [CRTC:33:crtc-0] > [ 1.216271] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:33:crtc-0] needs all connectors, enable: y, active: y > [ 1.216284] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.216296] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.216310] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 > [ 1.317254] [drm:drm_atomic_helper_commit_modeset_disables [drm_kms_helper]] modeset on [ENCODER:34:DAC-34] > [ 1.317708] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [CRTC:33:crtc-0] > [ 1.321530] [drm:drm_atomic_helper_commit_modeset_enables [drm_kms_helper]] enabling [ENCODER:34:DAC-34] > [ 1.321546] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 > [ 1.321559] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 > [ 1.321591] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 > [ 1.321604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000009f032e5a state to 00000000d3c00277 > [ 1.321616] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000005efad0e6 state to 00000000d3c00277 > [ 1.321629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000033f48d87 state to 00000000d3c00277 > [ 1.321642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000033f48d87 > [ 1.321656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000009f032e5a > [ 1.321669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.321682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000004014674f state to 00000000d3c00277 > [ 1.321695] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [NOCRTC] > [ 1.321708] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000004014674f to [CRTC:33:crtc-0] > [ 1.321720] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 > [ 1.321728] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 1.321734] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 1.321747] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 > [ 1.321805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 > [ 1.321818] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 > [ 1.324095] e1000e 0000:00:1f.6 0000:00:1f.6 (uninitialized): registered PHC clock > [ 1.324820] Console: switching to colour frame buffer device 128x48 > [ 1.341554] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c00277 > [ 1.341567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 00000000f7eff311 state to 00000000d3c00277 > [ 1.341579] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 000000000505a613 state to 00000000d3c00277 > [ 1.341591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000d2da0efa state to 00000000d3c00277 > [ 1.341605] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000d2da0efa > [ 1.341619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 00000000f7eff311 > [ 1.341631] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d3c00277 > [ 1.341644] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000cebac407 state to 00000000d3c00277 > [ 1.341657] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [NOCRTC] > [ 1.341670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000cebac407 to [CRTC:33:crtc-0] > [ 1.341682] [drm:drm_atomic_check_only [drm]] checking 00000000d3c00277 > [ 1.341690] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 1.341696] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 1.341709] [drm:drm_atomic_commit [drm]] committing 00000000d3c00277 > [ 1.341749] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c00277 > [ 1.341761] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c00277 > [ 1.344652] ast 0000:06:00.0: fb0: astdrmfb frame buffer device > [ 1.366247] xhci_hcd 0000:00:14.0: xHCI Host Controller > [ 1.366250] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 > [ 1.366253] xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed > [ 1.366292] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.06 > [ 1.366293] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 > [ 1.366294] usb usb2: Product: xHCI Host Controller > [ 1.366295] usb usb2: Manufacturer: Linux 5.6.0-2-amd64 xhci-hcd > [ 1.366296] usb usb2: SerialNumber: 0000:00:14.0 > [ 1.366371] scsi host0: ahci > [ 1.366512] hub 2-0:1.0: USB hub found > [ 1.366540] hub 2-0:1.0: 10 ports detected > [ 1.366542] scsi host1: ahci > [ 1.366632] scsi host2: ahci > [ 1.366704] scsi host3: ahci > [ 1.366744] ata1: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c100 irq 134 > [ 1.366746] ata2: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c180 irq 134 > [ 1.366747] ata3: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c200 irq 134 > [ 1.366748] ata4: SATA max UDMA/133 abar m2048 at 0xdf24c000 port 0xdf24c280 irq 134 > [ 1.367439] usb: port power management may be unreliable > [ 1.390078] i915 0000:00:02.0: [drm:i915_driver_probe [i915]] WOPCM: 1024K > [ 1.390116] i915 0000:00:02.0: [drm:intel_uc_init_early [i915]] enable_guc=0 (guc:no submission:no huc:no) > [ 1.390147] [drm:i915_gem_init_early [i915]] fake context support initialized > [ 1.390174] i915 0000:00:02.0: [drm:intel_pch_type [i915]] Found SunrisePoint PCH > [ 1.390207] [drm:intel_power_domains_init [i915]] Allowed DC state mask 02 > [ 1.390244] i915 0000:00:02.0: [drm:intel_uncore_init_mmio [i915]] unclaimed mmio detected on uncore init, clearing > [ 1.390619] [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M > [ 1.390645] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M > [ 1.390669] [drm:i915_ggtt_probe_hw [i915]] DSM size = 32M > [ 1.390670] i915 0000:00:02.0: VT-d active for gfx access > [ 1.390671] i915 0000:00:02.0: vgaarb: deactivate vga console > [ 1.390754] [drm:init_stolen [i915]] GEN6_STOLEN_RESERVED = 8f700047 > [ 1.390788] [drm:init_stolen [i915]] Memory reserved for graphics device: 32768K, usable: 31744K > [ 1.390818] [drm:intel_gt_init_workarounds [i915]] Initialized 4 GT workarounds on global > [ 1.390868] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params > [ 1.390899] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8b82a018 > [ 1.390933] [drm:intel_opregion_setup [i915]] ACPI OpRegion version 2.0.0 > [ 1.390962] [drm:intel_opregion_setup [i915]] Public ACPI methods supported > [ 1.390989] [drm:intel_opregion_setup [i915]] SWSCI supported > [ 1.392097] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483 > [ 1.392125] [drm:intel_opregion_setup [i915]] ASLE supported > [ 1.392152] [drm:intel_opregion_setup [i915]] ASLE extension supported > [ 1.392179] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4) > [ 1.392203] [drm:i915_driver_probe [i915]] DRAM type: DDR4 > [ 1.392227] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no > [ 1.392249] [drm:skl_dram_get_dimm_info [i915]] CH0 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no > [ 1.392271] [drm:skl_dram_get_channel_info [i915]] CH0 ranks: 2, 16Gb DIMMs: no > [ 1.392292] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM L size: 16 GB, width: X8, ranks: 2, 16Gb DIMMs: no > [ 1.392313] [drm:skl_dram_get_dimm_info [i915]] CH1 DIMM S size: 0 GB, width: X0, ranks: 0, 16Gb DIMMs: no > [ 1.392332] [drm:skl_dram_get_channel_info [i915]] CH1 ranks: 2, 16Gb DIMMs: no > [ 1.392352] [drm:i915_driver_probe [i915]] Memory configuration is symmetric? yes > [ 1.392371] [drm:i915_driver_probe [i915]] DRAM bandwidth: 34133344 kBps, channels: 2 > [ 1.392391] [drm:i915_driver_probe [i915]] DRAM ranks: 2, 16Gb DIMMs: no > [ 1.392391] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [ 1.392392] [drm] Driver supports precise vblank timestamp query. > [ 1.392424] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz > [ 1.392456] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE ", BDB version 205 > [ 1.392487] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0 > [ 1.392517] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2 > [ 1.392547] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68d6 > [ 1.392575] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 > [ 1.392604] [drm:intel_bios_init [i915]] Found VBT child device with type 0x60d6 > [ 1.392632] [drm:intel_bios_init [i915]] Found VBT child device with type 0x68c6 > [ 1.392985] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0) > [ 1.393028] [drm:intel_bios_init [i915]] Panel type: 2 (VBT) > [ 1.393056] [drm:intel_bios_init [i915]] DRRS supported mode is static > [ 1.393085] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT legacy lfp table: > [ 1.393098] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa > [ 1.393126] [drm:intel_bios_init [i915]] VBT initial LVDS value 300 > [ 1.393154] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0 > [ 1.393181] [drm:intel_bios_init [i915]] DRRS State Enabled:1 > [ 1.393209] [drm:intel_bios_init [i915]] Skipping SDVO device mapping > [ 1.393237] [drm:intel_bios_init [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393264] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8 > [ 1.393292] [drm:intel_bios_init [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393318] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8 > [ 1.393346] [drm:intel_bios_init [i915]] Port D VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393373] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8 > [ 1.393400] [drm:intel_bios_init [i915]] Port E VBT info: CRT:0 DVI:0 HDMI:0 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 > [ 1.393427] [drm:intel_bios_init [i915]] VBT HDMI level shift for port E: 0 > [ 1.393534] [drm:intel_dsm_detect [i915]] no _DSM method for intel device > [ 1.393577] [drm:intel_power_domains_init_hw [i915]] rawclk rate: 24000 kHz > [ 1.393610] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 > [ 1.393643] [drm:intel_power_well_enable [i915]] enabling power well 1 > [ 1.393675] [drm:intel_power_well_enable [i915]] enabling MISC IO power well > [ 1.393708] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 > [ 1.393740] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz > [ 1.393770] [drm:intel_cdclk_init [i915]] Max dotclock rate: 675000 kHz > [ 1.393813] [drm:intel_power_well_enable [i915]] enabling always-on > [ 1.393843] [drm:intel_power_well_enable [i915]] enabling DC off > [ 1.393873] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00 > [ 1.393906] [drm:intel_power_well_enable [i915]] enabling power well 2 > [ 1.393909] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=io+mem > [ 1.393964] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well > [ 1.394014] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well > [ 1.394042] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well > [ 1.394069] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well > [ 1.394113] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_27.bin > [ 1.394155] i915 0000:00:02.0: firmware: direct-loading firmware i915/skl_dmc_ver1_27.bin > [ 1.394459] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_27.bin (v1.27) > [ 1.394625] [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled > [ 1.394695] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0 > [ 1.394722] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec) > [ 1.394745] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec) > [ 1.394767] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec) > [ 1.394788] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec) > [ 1.394808] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec) > [ 1.394828] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec) > [ 1.394848] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec) > [ 1.394867] i915 0000:00:02.0: [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec) > [ 1.394988] [drm:intel_modeset_init [i915]] 3 display pipes available. > [ 1.395056] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3 > [ 1.395385] [drm:intel_modeset_init [i915]] VBT says port A is not DVI/HDMI/DP compatible, respect it > [ 1.395421] [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (VBT) > [ 1.395451] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:94:DDI B] > [ 1.395488] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:94:DDI B] > [ 1.395516] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (VBT) > [ 1.395550] [drm:intel_bios_port_aux_ch [i915]] using AUX C for port C (VBT) > [ 1.395578] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:109:DDI C] > [ 1.395609] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:109:DDI C] > [ 1.395636] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT) > [ 1.395669] [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT) > [ 1.395697] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:119:DDI D] > [ 1.395727] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:119:DDI D] > [ 1.395754] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT) > [ 1.395816] [drm:intel_bios_port_aux_ch [i915]] using AUX A for port E (VBT) > [ 1.395862] [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:129:DDI E] > [ 1.395917] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:51:pipe A] hw state readout: enabled > [ 1.395960] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:72:pipe B] hw state readout: disabled > [ 1.396018] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:93:pipe C] hw state readout: disabled > [ 1.396064] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] hw state readout: disabled, pipe A > [ 1.396065] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 0c:c4:7a:cf:6c:d6 > [ 1.396066] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection > [ 1.396107] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] hw state readout: disabled, pipe A > [ 1.396162] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] hw state readout: disabled, pipe A > [ 1.396213] e1000e 0000:00:1f.6 eth0: MAC: 12, PHY: 12, PBA No: 010BFF-0FF > [ 1.396274] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] hw state readout: disabled, pipe B > [ 1.396309] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] hw state readout: disabled, pipe B > [ 1.396355] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] hw state readout: disabled, pipe B > [ 1.396437] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] hw state readout: disabled, pipe C > [ 1.396511] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] hw state readout: disabled, pipe C > [ 1.396559] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] hw state readout: disabled, pipe C > [ 1.396597] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1 > [ 1.396641] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000001, on 1 > [ 1.396695] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0 > [ 1.396736] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0 > [ 1.396777] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:94:DDI B] hw state readout: disabled, pipe A > [ 1.396820] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:96:DP-MST A] hw state readout: disabled, pipe A > [ 1.396861] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:97:DP-MST B] hw state readout: disabled, pipe B > [ 1.396907] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:98:DP-MST C] hw state readout: disabled, pipe C > [ 1.396908] e1000e 0000:00:1f.6 eno1: renamed from eth0 > [ 1.396988] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:109:DDI C] hw state readout: enabled, pipe A > [ 1.397033] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:111:DP-MST A] hw state readout: disabled, pipe A > [ 1.397083] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:112:DP-MST B] hw state readout: disabled, pipe B > [ 1.397134] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:113:DP-MST C] hw state readout: disabled, pipe C > [ 1.397184] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:119:DDI D] hw state readout: disabled, pipe A > [ 1.397234] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:121:DP-MST A] hw state readout: disabled, pipe A > [ 1.397284] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:122:DP-MST B] hw state readout: disabled, pipe B > [ 1.397333] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:123:DP-MST C] hw state readout: disabled, pipe C > [ 1.397383] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:129:DDI E] hw state readout: disabled, pipe A > [ 1.397433] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:95:DP-1] hw state readout: disabled > [ 1.397484] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:104:HDMI-A-1] hw state readout: disabled > [ 1.397536] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:110:DP-2] hw state readout: enabled > [ 1.397588] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:116:HDMI-A-2] hw state readout: disabled > [ 1.397638] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:120:DP-3] hw state readout: disabled > [ 1.397688] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:126:HDMI-A-3] hw state readout: disabled > [ 1.397737] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:130:DP-4] hw state readout: disabled > [ 1.397764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 0000000016992e5d > [ 1.397814] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:31:plane 1A] min_cdclk 0 kHz > [ 1.397864] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:39:plane 2A] min_cdclk 0 kHz > [ 1.397913] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:47:cursor A] min_cdclk 0 kHz > [ 1.397964] [drm:intel_modeset_setup_hw_state [i915]] pipe A data rate 0 num active planes 0 > [ 1.398014] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:52:plane 1B] min_cdclk 0 kHz > [ 1.398063] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:plane 2B] min_cdclk 0 kHz > [ 1.398112] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:68:cursor B] min_cdclk 0 kHz > [ 1.398161] [drm:intel_modeset_setup_hw_state [i915]] pipe B data rate 0 num active planes 0 > [ 1.398211] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:73:plane 1C] min_cdclk 0 kHz > [ 1.398259] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:81:plane 2C] min_cdclk 0 kHz > [ 1.398308] [drm:intel_modeset_setup_hw_state [i915]] [PLANE:89:cursor C] min_cdclk 0 kHz > [ 1.398357] [drm:intel_modeset_setup_hw_state [i915]] pipe C data rate 0 num active planes 0 > [ 1.398413] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [setup_hw_state] > [ 1.398465] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB > [ 1.398516] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 > [ 1.398568] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 517734, link_n: 524288, tu: 64 > [ 1.398618] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0 > [ 1.398667] [drm:intel_dump_pipe_config [i915]] requested mode: > [ 1.398685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 720 3902 3950 4000 400 2163 2168 2222 0x40 0x9 > [ 1.398735] [drm:intel_dump_pipe_config [i915]] adjusted mode: > [ 1.398752] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533249 3840 3902 3950 4000 2160 2163 2168 2222 0x40 0x9 > [ 1.398803] [drm:intel_dump_pipe_config [i915]] crtc timings: 533249 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x40 flags: 0x9 > [ 1.398853] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 720x400, pixel rate 533249 > [ 1.398903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0 > [ 1.398952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0f000870, enabled, force thru: no > [ 1.399001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 > [ 1.399051] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 > [ 1.399100] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > [ 1.399149] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> > [ 1.399199] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: no [setup_hw_state] > [ 1.399248] [drm:intel_dump_pipe_config [i915]] [CRTC:93:pipe C] enable: no [setup_hw_state] > [ 1.399299] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling > [ 1.399340] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff7e1cca > [ 1.399359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000197e100e state to 00000000ff7e1cca > [ 1.399376] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000ff7e1cca > [ 1.399393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000aef36d99 state to 00000000ff7e1cca > [ 1.399410] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000069886caf state to 00000000ff7e1cca > [ 1.399426] [drm:drm_atomic_check_only [drm]] checking 00000000ff7e1cca > [ 1.399485] [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:51 > [ 1.399504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002ca0145a state to 00000000ff7e1cca > [ 1.399520] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a93965e7 state to 00000000ff7e1cca > [ 1.399536] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008fa1e3fc state to 00000000ff7e1cca > [ 1.399552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae2843ea state to 00000000ff7e1cca > [ 1.399567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000afe69d21 state to 00000000ff7e1cca > [ 1.399582] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a4be912 state to 00000000ff7e1cca > [ 1.399597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002017bf88 state to 00000000ff7e1cca > [ 1.399612] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000977f527e state to 00000000ff7e1cca > [ 1.399627] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000059814b3a state to 00000000ff7e1cca > [ 1.399679] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 > [ 1.399727] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.399773] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.399867] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.399911] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.399954] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.399997] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400039] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400082] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:39:plane 2A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400123] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400165] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400206] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400247] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400288] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400329] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400370] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400411] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400451] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400492] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400533] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400573] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:60:plane 2B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400613] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400654] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400735] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400775] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400816] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400857] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400897] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:73:plane 1C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.400936] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.400977] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401017] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401057] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:81:plane 2C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401096] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 1.401137] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] lines 1, 1, 1, 1, 1, 1, 1, 1, 1 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401177] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] blocks 7, 7, 7, 7, 7, 7, 7, 7, 7 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401217] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:89:cursor C] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 1.401236] [drm:drm_atomic_commit [drm]] committing 00000000ff7e1cca > [ 1.403979] [drm] Initialized ast 0.1.0 20120228 for 0000:06:00.0 on minor 0 > [ 1.417469] [drm:i915_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000] > [ 1.419056] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff7e1cca > [ 1.419076] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff7e1cca > [ 1.419161] [drm:intel_engine_init_workarounds [i915]] Initialized 5 engine workarounds on rcs'0 > [ 1.419213] [drm:intel_engine_init_whitelist [i915]] Initialized 5 whitelist workarounds on rcs'0 > [ 1.419264] [drm:intel_engine_init_ctx_wa [i915]] Initialized 12 context workarounds on rcs'0 > [ 1.420147] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping > [ 1.420202] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping > [ 1.420253] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping > [ 1.420305] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config > [ 1.420418] [drm:intel_engines_driver_register [i915]] renamed rcs'0 to rcs0 > [ 1.420466] [drm:intel_engines_driver_register [i915]] renamed bcs'0 to bcs0 > [ 1.420513] [drm:intel_engines_driver_register [i915]] renamed vcs'0 to vcs0 > [ 1.420558] [drm:intel_engines_driver_register [i915]] renamed vecs'0 to vecs0 > [ 1.421101] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card1-DP-1 > [ 1.421269] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card1-DP-2 > [ 1.421470] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card1-DP-3 > [ 1.421665] [drm:intel_dp_connector_register [i915]] registering DPDDC-E bus for card1-DP-4 > [ 1.421746] [drm] Initialized i915 1.6.0 20200114 for 0000:00:02.0 on minor 1 > [ 1.421881] [drm:intel_opregion_resume [i915]] 7 outputs detected > [ 1.424122] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) > [ 1.424463] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3 > [ 1.424632] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well > [ 1.424650] [drm:drm_client_modeset_probe [drm]] > [ 1.424733] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well > [ 1.424743] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 1.424798] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 1.424851] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well > [ 1.424855] i915 device info: pciid=0x191d rev=0x06 platform=SKYLAKE (subplatform=0x0) gen=9 > [ 1.424857] i915 device info: engines: 47 > [ 1.424857] i915 device info: gen: 9 > [ 1.424858] i915 device info: gt: 2 > [ 1.424859] i915 device info: iommu: enabled > [ 1.424860] i915 device info: memory-regions: 5 > [ 1.424861] i915 device info: page-sizes: 11000 > [ 1.424861] i915 device info: platform: SKYLAKE > [ 1.424869] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] status updated from unknown to disconnected > [ 1.424869] i915 device info: ppgtt-size: 48 > [ 1.424870] i915 device info: ppgtt-type: 2 > [ 1.424871] i915 device info: is_mobile: no > [ 1.424872] i915 device info: is_lp: no > [ 1.424873] i915 device info: require_force_probe: no > [ 1.424879] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 1.424880] i915 device info: is_dgfx: no > [ 1.424900] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 1.424901] i915 device info: has_64bit_reloc: yes > [ 1.424902] i915 device info: gpu_reset_clobbers_display: no > [ 1.424903] i915 device info: has_reset_engine: yes > [ 1.424904] i915 device info: has_fpga_dbg: yes > [ 1.424905] i915 device info: has_global_mocs: no > [ 1.424919] i915 device info: has_gt_uc: yes > [ 1.424920] i915 device info: has_l3_dpf: no > [ 1.424921] i915 device info: has_llc: yes > [ 1.424922] i915 device info: has_logical_ring_contexts: yes > [ 1.424923] i915 device info: has_logical_ring_elsq: no > [ 1.424959] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 1.424960] i915 device info: has_logical_ring_preemption: yes > [ 1.424961] i915 device info: has_pooled_eu: no > [ 1.424962] i915 device info: has_rc6: yes > [ 1.424963] i915 device info: has_rc6p: no > [ 1.424963] i915 device info: has_rps: yes > [ 1.424964] i915 device info: has_runtime_pm: yes > [ 1.424965] i915 device info: has_snoop: no > [ 1.424966] i915 device info: has_coherent_ggtt: yes > [ 1.424967] i915 device info: unfenced_needs_alignment: no > [ 1.424968] i915 device info: hws_needs_physical: no > [ 1.424969] i915 device info: cursor_needs_physical: no > [ 1.424970] i915 device info: has_csr: yes > [ 1.424970] i915 device info: has_ddi: yes > [ 1.424971] i915 device info: has_dp_mst: yes > [ 1.424972] i915 device info: has_dsb: no > [ 1.424973] i915 device info: has_dsc: no > [ 1.424974] i915 device info: has_fbc: no > [ 1.424974] i915 device info: has_gmch: no > [ 1.424975] i915 device info: has_hdcp: yes > [ 1.424976] i915 device info: has_hotplug: yes > [ 1.424977] i915 device info: has_ipc: yes > [ 1.424978] i915 device info: has_modular_fia: no > [ 1.424979] i915 device info: has_overlay: no > [ 1.424980] i915 device info: has_psr: yes > [ 1.424981] i915 device info: overlay_needs_physical: no > [ 1.424981] i915 device info: supports_tv: no > [ 1.424982] i915 device info: slice total: 1, mask=0001 > [ 1.424983] i915 device info: subslice total: 3 > [ 1.424985] i915 device info: slice0: 3 subslices, mask=00000007 > [ 1.424986] i915 device info: slice1: 0 subslices, mask=00000000 > [ 1.424987] i915 device info: slice2: 0 subslices, mask=00000000 > [ 1.424987] i915 device info: EU total: 24 > [ 1.424988] i915 device info: EU per subslice: 8 > [ 1.424989] i915 device info: has slice power gating: no > [ 1.424990] i915 device info: has subslice power gating: no > [ 1.424991] i915 device info: has EU power gating: yes > [ 1.424992] i915 device info: CS timestamp frequency: 12000 kHz > [ 1.425215] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 1.425265] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 1.425502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 1.425525] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 1.425552] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 1.425579] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 1.428627] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 1.428673] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 1.428929] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 1.428956] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 1.429243] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 1.429262] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 1.429267] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] status updated from unknown to disconnected > [ 1.429271] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 1.429275] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 1.429304] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 1.429716] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 1.430070] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 1.431595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 1.431624] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 1.431652] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 1.431941] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 1.437548] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 1.438071] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] status updated from unknown to connected > [ 1.438083] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.438095] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 1.438105] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 1.438114] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.438303] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.438311] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.438318] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.438325] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.438333] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438339] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438346] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438353] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438360] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438366] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438373] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.438379] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.438387] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 1.438394] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.438401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 1.438408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 1.438414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 1.438421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 1.438428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.438434] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.438441] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.438448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.438454] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 1.438461] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 1.438468] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.438475] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.438481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 1.438488] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 1.438495] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.438501] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.438508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 1.438515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.438521] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.438528] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.438535] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 1.438541] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 1.438548] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 1.438555] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 1.438562] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 1.438568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.438575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.438582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438588] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438595] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438602] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.438608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 1.438615] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.438621] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.438628] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.438635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 1.438639] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 1.438670] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 1.438979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 1.439008] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 1.439309] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 1.439332] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 1.439360] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 1.439388] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 1.442034] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 1.442060] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 1.442363] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 1.442389] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 1.442674] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 1.442693] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 1.442697] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] status updated from unknown to disconnected > [ 1.442701] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 1.442704] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 1.442731] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 1.443143] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 1.443498] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 1.445026] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 1.445055] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 1.445083] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 1.445371] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 1.450984] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 1.451505] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] status updated from unknown to connected > [ 1.451514] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.451523] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 1.451530] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 1.451537] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 1.451717] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.451724] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.451732] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 1.451738] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 1.451746] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451752] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451760] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451772] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451779] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451785] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451792] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 1.451798] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 1.451806] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 1.451813] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.451832] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 1.451839] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 1.451845] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 1.451851] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 1.451858] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.451864] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 1.451870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.451877] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 1.451883] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 1.451890] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 1.451896] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.451902] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 1.451909] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 1.451915] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 1.451921] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.451928] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 1.451934] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 1.451940] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.451947] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.451953] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 1.451959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 1.451966] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 1.451972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 1.451978] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 1.451985] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 1.451991] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.451997] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 1.452004] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452010] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452016] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452023] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 1.452029] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 1.452035] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.452042] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.452048] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 1.452054] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 1.452058] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 1.452153] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 1.452459] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 1.452487] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 1.452774] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 1.452796] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 1.452823] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 1.452849] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 1.455460] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 1.455486] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 1.455821] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 1.455849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 1.456135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 1.456153] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 1.456158] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] status updated from unknown to disconnected > [ 1.456161] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 1.456165] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 1.456192] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 1.456202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] status updated from unknown to disconnected > [ 1.456205] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 1.456214] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no > [ 1.456223] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no > [ 1.456230] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes > [ 1.456237] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no > [ 1.456244] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes > [ 1.456250] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no > [ 1.456257] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no > [ 1.456264] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 1.456271] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 > [ 1.456278] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 > [ 1.456285] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 1.456291] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 > [ 1.456297] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 > [ 1.456304] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 1.456310] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 16384x16384 config > [ 1.456319] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) > [ 1.456325] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) > [ 1.456331] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 0 primary plane > [ 1.456335] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 1 primary plane > [ 1.456339] i915 0000:00:02.0: [drm:__drm_fb_helper_initial_config_and_unlock [drm_kms_helper]] test CRTC 2 primary plane > [ 1.456368] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one > [ 1.461444] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000 > [ 1.461492] fbcon: i915drmfb (fb1) is primary device > [ 1.461493] fbcon: Remapping primary device, fb1, to tty 1-63 > [ 1.461508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 1.461518] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002dfe43fd state to 00000000fc0cb429 > [ 1.461526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000000bf01569 state to 00000000fc0cb429 > [ 1.461535] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000000bf01569 > [ 1.461543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ab6fdf3f state to 00000000fc0cb429 > [ 1.461550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ab6fdf3f > [ 1.461558] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d93e8df3 state to 00000000fc0cb429 > [ 1.461566] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000015cf0577 state to 00000000fc0cb429 > [ 1.461573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000015cf0577 > [ 1.461580] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003292b89f state to 00000000fc0cb429 > [ 1.461588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003292b89f > [ 1.461595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f4491376 state to 00000000fc0cb429 > [ 1.461602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e2798a03 state to 00000000fc0cb429 > [ 1.461609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e2798a03 > [ 1.461616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007f2e9b45 state to 00000000fc0cb429 > [ 1.461624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007f2e9b45 > [ 1.461632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 > [ 1.461640] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000de3ff82c > [ 1.461648] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:31:plane 1A] state 000000002dfe43fd to [CRTC:51:pipe A] > [ 1.461655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002dfe43fd > [ 1.461662] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 1.461670] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034523972 state to 00000000fc0cb429 > [ 1.461678] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [NOCRTC] > [ 1.461685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034523972 to [CRTC:51:pipe A] > [ 1.461693] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 00000000fc0cb429 > [ 1.461700] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 00000000dd2a82ac > [ 1.461707] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:52:plane 1B] state 00000000d93e8df3 to [CRTC:72:pipe B] > [ 1.461714] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d93e8df3 > [ 1.461721] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 1.461730] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000de1711cf state to 00000000fc0cb429 > [ 1.461736] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000de1711cf to [CRTC:72:pipe B] > [ 1.461744] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e46349dc state to 00000000fc0cb429 > [ 1.461751] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e46349dc > [ 1.461758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f4491376 > [ 1.461765] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 1.461772] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 1.461779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] mode changed > [ 1.461783] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] mode changed > [ 1.461786] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] enable changed > [ 1.461790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] active changed > [ 1.461795] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.461798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.461802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.461805] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] using [ENCODER:119:DDI D] on [CRTC:72:pipe B] > [ 1.461808] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:51:pipe A] needs all connectors, enable: y, active: y > [ 1.461816] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 1.461823] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 1.461827] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:72:pipe B] needs all connectors, enable: y, active: y > [ 1.461834] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 1.461841] [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 1.461874] [drm:intel_atomic_check [i915]] [CONNECTOR:110:DP-2] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 > [ 1.461911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz > [ 1.461941] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > [ 1.461968] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 > [ 1.461996] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 > [ 1.462030] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 > [ 1.462061] [drm:pipe_config_mismatch [i915]] [CRTC:51:pipe A] fastset mismatch in has_audio unable to verify whether state matches exactly, forcing modeset (expected no, found yes) > [ 1.462091] [drm:intel_atomic_check [i915]] [CONNECTOR:120:DP-3] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 > [ 1.462124] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 540000 max bpp 24 pixel clock 533250KHz > [ 1.462151] [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > [ 1.462178] [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 540000 bpp 24 > [ 1.462204] [drm:intel_dp_compute_config [i915]] DP link rate required 1599750 available 2160000 > [ 1.462236] [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 > [ 1.462265] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in lane_count (expected 0, found 4) > [ 1.462294] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in dp_m_n (expected tu 0 gmch 0/0 link 0/0, or tu 0 gmch 0/0 link 0/0, found tu 64, gmch 6212812/8388608 link 1035468/1048576) > [ 1.462321] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_types (expected 0x00000000, found 0x00000080) > [ 1.462349] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hdisplay (expected 0, found 3840) > [ 1.462376] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_htotal (expected 0, found 4000) > [ 1.462402] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_start (expected 0, found 3840) > [ 1.462429] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hblank_end (expected 0, found 4000) > [ 1.462455] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_start (expected 0, found 3902) > [ 1.462481] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_hsync_end (expected 0, found 3950) > [ 1.462507] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vdisplay (expected 0, found 2160) > [ 1.462533] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vtotal (expected 0, found 2222) > [ 1.462559] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_start (expected 0, found 2160) > [ 1.462584] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vblank_end (expected 0, found 2222) > [ 1.462610] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_start (expected 0, found 2163) > [ 1.462636] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_vsync_end (expected 0, found 2168) > [ 1.462662] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pixel_multiplier (expected 0, found 1) > [ 1.462688] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in output_format (expected 0, found 1) > [ 1.462714] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in has_audio (expected no, found yes) > [ 1.462740] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (1) (expected 0, found 1) > [ 1.462766] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.flags (8) (expected 0, found 8) > [ 1.462792] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in pipe_bpp (expected 0, found 24) > [ 1.462818] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in hw.adjusted_mode.crtc_clock (expected 0, found 533250) > [ 1.462843] [drm:pipe_config_mismatch [i915]] [CRTC:72:pipe B] fastset mismatch in port_clock (expected 0, found 540000) > [ 1.462875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 0 -> 1, off 0, on 1, ms 1 > [ 1.462904] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 0 -> 1, off 0, on 1, ms 1 > [ 1.462933] [drm:intel_modeset_calc_cdclk [i915]] Modeset required for cdclk change > [ 1.462960] [drm:intel_modeset_calc_cdclk [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz > [ 1.462986] [drm:intel_modeset_calc_cdclk [i915]] New voltage level calculated to be logical 2, actual 2 > [ 1.463015] [drm:intel_find_shared_dpll [i915]] [CRTC:51:pipe A] allocated DPLL 1 > [ 1.463043] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe A > [ 1.463071] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0 > [ 1.463099] [drm:intel_find_shared_dpll [i915]] [CRTC:72:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 1) > [ 1.463126] [drm:intel_reference_shared_dpll.isra.0 [i915]] using DPLL 1 for pipe B > [ 1.463157] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] ddb ( 0 - 0) -> ( 0 - 401), size 0 -> 401 > [ 1.463181] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] ddb ( 847 - 892) -> ( 401 - 446), size 45 -> 45 > [ 1.463204] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm > [ 1.463227] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 > [ 1.463249] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 > [ 1.463271] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 > [ 1.463292] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] ddb ( 0 - 0) -> ( 446 - 847), size 0 -> 401 > [ 1.463312] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] ddb ( 0 - 0) -> ( 847 - 892), size 0 -> 45 > [ 1.463332] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm > [ 1.463353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 0, 0 > [ 1.463373] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 82, 119, 136, 265, 323, 348, 0, 0 > [ 1.463392] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 83, 120, 137, 266, 324, 349, 0, 0 > [ 1.463423] [drm:intel_dump_pipe_config [i915]] [CRTC:51:pipe A] enable: yes [modeset] > [ 1.463453] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB > [ 1.463482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0 > [ 1.463510] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 > [ 1.463537] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 > [ 1.463564] [drm:intel_dump_pipe_config [i915]] requested mode: > [ 1.463573] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.463600] [drm:intel_dump_pipe_config [i915]] adjusted mode: > [ 1.463608] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.463636] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 > [ 1.463662] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 > [ 1.463689] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 > [ 1.463715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no > [ 1.463741] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 > [ 1.463768] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 > [ 1.463831] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > [ 1.463857] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> > [ 1.463883] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes > [ 1.463909] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 > [ 1.463935] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 > [ 1.463961] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2A] fb: [NOFB], visible: no > [ 1.463987] [drm:intel_dump_pipe_config [i915]] [PLANE:47:cursor A] fb: [NOFB], visible: no > [ 1.464013] [drm:intel_dump_pipe_config [i915]] [CRTC:72:pipe B] enable: yes [modeset] > [ 1.464039] [drm:intel_dump_pipe_config [i915]] active: yes, output_types: DP (0x80), output format: RGB > [ 1.464064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0 > [ 1.464090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64 > [ 1.464115] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0, infoframes enabled: 0x0 > [ 1.464140] [drm:intel_dump_pipe_config [i915]] requested mode: > [ 1.464148] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.464174] [drm:intel_dump_pipe_config [i915]] adjusted mode: > [ 1.464182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 1.464209] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3902 3950 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9 > [ 1.464234] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250 > [ 1.464260] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 > [ 1.464286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no > [ 1.464311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 > [ 1.464336] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0 > [ 1.464362] [drm:intel_dump_pipe_config [i915]] csc_mode: 0x2 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > [ 1.464387] [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> > [ 1.464414] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 1B] fb: [FB:136] 3840x2160 format = XR24 little-endian (0x34325258), visible: yes > [ 1.464439] [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 > [ 1.464465] [drm:intel_dump_pipe_config [i915]] src: 3840.000000x2160.000000+0.000000+0.000000 dst: 3840x2160+0+0 > [ 1.464491] [drm:intel_dump_pipe_config [i915]] [PLANE:60:plane 2B] fb: [NOFB], visible: no > [ 1.464516] [drm:intel_dump_pipe_config [i915]] [PLANE:68:cursor B] fb: [NOFB], visible: no > [ 1.464526] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 1.464573] [drm:intel_disable_pipe [i915]] disabling pipe A > [ 1.467843] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well > [ 1.467878] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 51 > [ 1.467923] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1 > [ 1.467957] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 2 > [ 1.467991] i915 0000:00:02.0: [drm:intel_disable_sagv [i915]] Disabling SAGV > [ 1.468025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI B] > [ 1.468055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:96:DP-MST A] > [ 1.468085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:97:DP-MST B] > [ 1.468114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:98:DP-MST C] > [ 1.468143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:109:DDI C] > [ 1.468172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:111:DP-MST A] > [ 1.468200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:112:DP-MST B] > [ 1.468228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:113:DP-MST C] > [ 1.468256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:119:DDI D] > [ 1.468284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:121:DP-MST A] > [ 1.468312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:122:DP-MST B] > [ 1.468340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:123:DP-MST C] > [ 1.468367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:129:DDI E] > [ 1.468396] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 0 > [ 1.468424] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 > [ 1.468452] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 2 > [ 1.468481] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 3 > [ 1.468512] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 51 > [ 1.468542] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1 > [ 1.468641] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well > [ 1.469400] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 > [ 1.469709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 > [ 1.469737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 > [ 1.469765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 > [ 1.469793] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 > [ 1.470489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 > [ 1.470517] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 > [ 1.470544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.471230] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 > [ 1.471257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 > [ 1.471284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.471974] [drm:intel_dp_start_link_train [i915]] clock recovery OK > [ 1.472002] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 > [ 1.473297] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful > [ 1.473473] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:110:DP-2] Link Training Passed at Link Rate = 540000, Lane count = 4 > [ 1.473640] [drm:intel_enable_pipe [i915]] enabling pipe A > [ 1.473675] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS > [ 1.473705] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:110:DP-2], [ENCODER:109:DDI C] > [ 1.473735] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder A, 36 bytes ELD > [ 1.473767] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud > [ 1.473810] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 72 > [ 1.473841] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well > [ 1.474602] [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 14 > [ 1.474908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000 > [ 1.474936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0 > [ 1.474964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0 > [ 1.474992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1 > [ 1.475686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000 > [ 1.475714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1 > [ 1.475740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.476426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000 > [ 1.476454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2 > [ 1.476481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1 > [ 1.477166] [drm:intel_dp_start_link_train [i915]] clock recovery OK > [ 1.477193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3 > [ 1.478488] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful > [ 1.478664] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:120:DP-3] Link Training Passed at Link Rate = 540000, Lane count = 4 > [ 1.478830] [drm:intel_enable_pipe [i915]] enabling pipe B > [ 1.478862] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS > [ 1.478897] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe B FIFO underrun > [ 1.478928] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:120:DP-3], [ENCODER:119:DDI D] > [ 1.478957] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on transcoder B, 36 bytes ELD > [ 1.478988] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud > [ 1.495987] [drm:verify_connector_state [i915]] [CONNECTOR:110:DP-2] > [ 1.496025] [drm:intel_atomic_commit_tail [i915]] [CRTC:51:pipe A] > [ 1.496067] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 > [ 1.496104] [drm:verify_connector_state [i915]] [CONNECTOR:120:DP-3] > [ 1.496135] [drm:intel_atomic_commit_tail [i915]] [CRTC:72:pipe B] > [ 1.496171] [drm:verify_single_dpll_state.isra.0 [i915]] DPLL 1 > [ 1.496241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 > [ 1.496252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a8e00a70 state to 000000002a70fa07 > [ 1.496261] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 000000002a70fa07 > [ 1.496285] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c4a0e3a state to 000000002a70fa07 > [ 1.496310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c4a0e3a > [ 1.496324] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 1.496335] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 1.496350] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 000000002a70fa07 > [ 1.496359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f > [ 1.496366] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000062109416 state to 000000002a70fa07 > [ 1.496374] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 000000002a70fa07 > [ 1.496381] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f97067cf state to 000000002a70fa07 > [ 1.496389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f97067cf > [ 1.496397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a6369fc8 state to 000000002a70fa07 > [ 1.496404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a6369fc8 > [ 1.496412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000091b367b1 state to 000000002a70fa07 > [ 1.496421] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000009bdf158a state to 000000002a70fa07 > [ 1.496428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000009bdf158a > [ 1.496435] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fb662b09 state to 000000002a70fa07 > [ 1.496443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fb662b09 > [ 1.496455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a8e00a70 > [ 1.496463] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 > [ 1.496471] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 000000002a70fa07 > [ 1.496479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] > [ 1.496486] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] > [ 1.496494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000062109416 > [ 1.496501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 > [ 1.496509] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000860da491 state to 000000002a70fa07 > [ 1.496516] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [NOCRTC] > [ 1.496523] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000860da491 to [CRTC:72:pipe B] > [ 1.496531] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 000000002a70fa07 > [ 1.496538] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 1.496545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000091b367b1 > [ 1.496552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 > [ 1.496560] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 > [ 1.496570] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.496574] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.496578] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.496581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.496625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.496658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.496675] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 > [ 1.512640] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 > [ 1.512654] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 > [ 1.524341] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 1.524352] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 > [ 1.524362] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 1.524370] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 > [ 1.524382] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f > [ 1.524394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 > [ 1.524403] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 > [ 1.524412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 1.524420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 1.524428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 > [ 1.524437] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 1.524446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 > [ 1.524454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 1.524463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 > [ 1.524471] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 > [ 1.524479] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 > [ 1.524489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 > [ 1.524497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a > [ 1.524506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c > [ 1.524515] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 1.524524] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003979f4ee state to 0000000098df4bf3 > [ 1.524533] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [NOCRTC] > [ 1.524542] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003979f4ee to [CRTC:51:pipe A] > [ 1.524551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 1.524559] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 1.524568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 > [ 1.524576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] > [ 1.524585] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] > [ 1.524593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 1.524602] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 1.524610] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f > [ 1.524619] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 1.524628] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 1.524638] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.524643] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.524648] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.524652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.524716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.524754] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.524771] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 1.553743] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 1.553761] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 > [ 1.553774] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 1.553786] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015579631 state to 00000000482d1aa4 > [ 1.553798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 00000000482d1aa4 > [ 1.553808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000482d1aa4 > [ 1.553819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b > [ 1.553830] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000482d1aa4 > [ 1.553840] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 > [ 1.553850] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000041c6228e state to 00000000482d1aa4 > [ 1.553860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000022f73fd2 state to 00000000482d1aa4 > [ 1.553869] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001f82d691 state to 00000000482d1aa4 > [ 1.553879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001f82d691 > [ 1.553889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 > [ 1.553899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 > [ 1.553909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e5892e4f state to 00000000482d1aa4 > [ 1.553921] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c3b3ca94 state to 00000000482d1aa4 > [ 1.553931] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c3b3ca94 > [ 1.553940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000074f436be state to 00000000482d1aa4 > [ 1.553950] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000074f436be > [ 1.553960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015579631 > [ 1.553970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 > [ 1.553981] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000482d1aa4 > [ 1.553991] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] > [ 1.554000] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] > [ 1.554010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000041c6228e > [ 1.554020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 > [ 1.554030] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000482d1aa4 > [ 1.554039] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 1.554048] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 1.554058] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000006ede65dd state to 00000000482d1aa4 > [ 1.554067] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000006ede65dd > [ 1.554076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e5892e4f > [ 1.554086] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 > [ 1.554096] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 > [ 1.554108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.554113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.554118] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.554123] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.554190] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.554233] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.554259] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 > [ 1.562628] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 > [ 1.562645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 > [ 1.575634] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c > [ 1.575648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 00000000fcb1012c > [ 1.575660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000fcb1012c > [ 1.575670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ccf8507 state to 00000000fcb1012c > [ 1.575681] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ccf8507 > [ 1.575691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bb3d8d45 state to 00000000fcb1012c > [ 1.575702] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bb3d8d45 > [ 1.575716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000485c2b88 state to 00000000fcb1012c > [ 1.575725] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002ba4f36a state to 00000000fcb1012c > [ 1.575735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004e08d13d state to 00000000fcb1012c > [ 1.575745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004e08d13d > [ 1.575754] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b2b055b6 state to 00000000fcb1012c > [ 1.575767] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b2b055b6 > [ 1.575798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000010a446a8 state to 00000000fcb1012c > [ 1.575807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c > [ 1.575817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf > [ 1.575854] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d365bfc5 state to 00000000fcb1012c > [ 1.575863] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d365bfc5 > [ 1.575874] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a > [ 1.575884] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c > [ 1.575894] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001d9bfafc state to 00000000fcb1012c > [ 1.575904] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [NOCRTC] > [ 1.575914] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001d9bfafc to [CRTC:51:pipe A] > [ 1.575924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000485c2b88 > [ 1.575933] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c > [ 1.575943] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000514f7582 state to 00000000fcb1012c > [ 1.575952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [NOCRTC] > [ 1.575961] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000514f7582 to [CRTC:72:pipe B] > [ 1.575971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c > [ 1.575980] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 > [ 1.575989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000010a446a8 > [ 1.575999] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c > [ 1.576008] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c > [ 1.576020] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.576025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.576030] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.576035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.576097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.576139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.576167] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c > [ 1.610983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bb4d667a > [ 1.611007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c > [ 1.611032] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e9b5f5ed state to 00000000bb4d667a > [ 1.611054] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c > [ 1.611079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000bb4d667a > [ 1.611096] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000122a804f state to 00000000bb4d667a > [ 1.611115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000122a804f > [ 1.611131] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005d690c84 state to 00000000bb4d667a > [ 1.611149] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005d690c84 > [ 1.611165] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c775be6 state to 00000000bb4d667a > [ 1.611183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000bb4d667a > [ 1.611198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000b5f6abf5 state to 00000000bb4d667a > [ 1.611214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000b5f6abf5 > [ 1.611230] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000281af025 state to 00000000bb4d667a > [ 1.611246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000281af025 > [ 1.611261] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053454233 state to 00000000bb4d667a > [ 1.611276] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b2cdb294 state to 00000000bb4d667a > [ 1.611292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b2cdb294 > [ 1.611308] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000555d146c state to 00000000bb4d667a > [ 1.611323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000555d146c > [ 1.611341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e9b5f5ed > [ 1.611358] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000bb4d667a > [ 1.611375] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000084c59d5f state to 00000000bb4d667a > [ 1.611396] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [NOCRTC] > [ 1.611412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000084c59d5f to [CRTC:51:pipe A] > [ 1.611428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c775be6 > [ 1.611444] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000bb4d667a > [ 1.611460] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000adc2b291 state to 00000000bb4d667a > [ 1.611476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [NOCRTC] > [ 1.611491] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000adc2b291 to [CRTC:72:pipe B] > [ 1.611508] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000bb4d667a > [ 1.611524] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d > [ 1.611539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053454233 > [ 1.611560] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000bb4d667a > [ 1.611577] [drm:drm_atomic_check_only [drm]] checking 00000000bb4d667a > [ 1.611603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.611612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.611620] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.611628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.611728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.611798] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.611840] [drm:drm_atomic_commit [drm]] committing 00000000bb4d667a > [ 1.645601] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bb4d667a > [ 1.645625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000482d1aa4 > [ 1.645642] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bb4d667a > [ 1.645659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000060d5862a state to 00000000482d1aa4 > [ 1.645675] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000482d1aa4 > [ 1.645689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000071f245df state to 00000000482d1aa4 > [ 1.645705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000071f245df > [ 1.645722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000482d1aa4 > [ 1.645736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be > [ 1.645752] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 00000000482d1aa4 > [ 1.645767] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000669bfcd7 state to 00000000482d1aa4 > [ 1.645779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5892e4f state to 00000000482d1aa4 > [ 1.645794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5892e4f > [ 1.645807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003073c677 state to 00000000482d1aa4 > [ 1.645820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003073c677 > [ 1.645834] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001f82d691 state to 00000000482d1aa4 > [ 1.645846] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 00000000482d1aa4 > [ 1.645860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e > [ 1.645874] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 00000000482d1aa4 > [ 1.645888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 > [ 1.645902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000060d5862a > [ 1.645916] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000482d1aa4 > [ 1.645930] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 00000000482d1aa4 > [ 1.645945] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 1.645958] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 1.645971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 > [ 1.645984] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000482d1aa4 > [ 1.645998] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 00000000482d1aa4 > [ 1.646011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 1.646024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 1.646037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d7f71e60 state to 00000000482d1aa4 > [ 1.646050] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d7f71e60 > [ 1.646063] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001f82d691 > [ 1.646076] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000482d1aa4 > [ 1.646090] [drm:drm_atomic_check_only [drm]] checking 00000000482d1aa4 > [ 1.646105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.646113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.646120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.646126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.646207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.646267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.646298] [drm:drm_atomic_commit [drm]] committing 00000000482d1aa4 > [ 1.662741] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000482d1aa4 > [ 1.662763] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000482d1aa4 > [ 1.682625] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 1.682648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f101de7e state to 0000000098df4bf3 > [ 1.682667] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 1.682683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e81eafbe state to 0000000098df4bf3 > [ 1.682701] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e81eafbe > [ 1.682718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000026a13e4f state to 0000000098df4bf3 > [ 1.682735] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000026a13e4f > [ 1.682755] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 > [ 1.682770] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 1.682784] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005342f7e7 state to 0000000098df4bf3 > [ 1.682801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005342f7e7 > [ 1.682816] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fb96f9d3 state to 0000000098df4bf3 > [ 1.682832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fb96f9d3 > [ 1.682848] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000003eec9b7 state to 0000000098df4bf3 > [ 1.682863] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 > [ 1.682879] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a > [ 1.682894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 > [ 1.682909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 > [ 1.682926] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f101de7e > [ 1.682942] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 1.682962] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000064c4b21e state to 0000000098df4bf3 > [ 1.682979] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [NOCRTC] > [ 1.682994] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000064c4b21e to [CRTC:51:pipe A] > [ 1.683010] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe > [ 1.683025] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 1.683041] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 > [ 1.683056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] > [ 1.683072] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] > [ 1.683088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 1.683103] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 1.683118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000003eec9b7 > [ 1.683133] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 1.683149] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 1.683178] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.683187] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.683196] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.683203] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.683302] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.683372] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.683406] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 1.683650] ata1: SATA link down (SStatus 4 SControl 300) > [ 1.683668] ata4: SATA link down (SStatus 4 SControl 300) > [ 1.683686] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300) > [ 1.683711] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) > [ 1.685953] ata2.00: supports DRM functions and may not be fully accessible > [ 1.686212] ata3.00: ATAPI: TSSTcorp CDDVDW SH-224GB, SB00, max UDMA/100 > [ 1.687451] ata3.00: configured for UDMA/100 > [ 1.692177] ata2.00: disabling queued TRIM support > [ 1.692194] ata2.00: ATA-9: Samsung SSD 850 PRO 512GB, EXM02B6Q, max UDMA/133 > [ 1.692196] ata2.00: 1000215216 sectors, multi 1: LBA48 NCQ (depth 32), AA > [ 1.696183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 1.696209] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 1.698509] ata2.00: supports DRM functions and may not be fully accessible > [ 1.699829] usb 1-7: new high-speed USB device number 2 using xhci_hcd > [ 1.704324] ata2.00: disabling queued TRIM support > [ 1.710263] ata2.00: configured for UDMA/133 > [ 1.710469] scsi 1:0:0:0: Direct-Access ATA Samsung SSD 850 2B6Q PQ: 0 ANSI: 5 > [ 1.713317] scsi 2:0:0:0: CD-ROM TSSTcorp CDDVDW SH-224GB SB00 PQ: 0 ANSI: 5 > [ 1.725160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fcb1012c > [ 1.725192] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000c8bd6dc state to 00000000fcb1012c > [ 1.725221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 00000000fcb1012c > [ 1.725245] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000083c05b3d state to 00000000fcb1012c > [ 1.725273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000083c05b3d > [ 1.725297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008409a024 state to 00000000fcb1012c > [ 1.725322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008409a024 > [ 1.725347] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006164f3e3 state to 00000000fcb1012c > [ 1.725370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 00000000fcb1012c > [ 1.725394] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000382acb58 state to 00000000fcb1012c > [ 1.725418] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000382acb58 > [ 1.725442] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009a9a5a77 state to 00000000fcb1012c > [ 1.725466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009a9a5a77 > [ 1.725489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d365bfc5 state to 00000000fcb1012c > [ 1.725510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c23288bf state to 00000000fcb1012c > [ 1.725534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c23288bf > [ 1.725557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010a446a8 state to 00000000fcb1012c > [ 1.725580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010a446a8 > [ 1.725608] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000c8bd6dc > [ 1.725633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fcb1012c > [ 1.725662] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000008c0081a2 state to 00000000fcb1012c > [ 1.725687] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [NOCRTC] > [ 1.725712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000008c0081a2 to [CRTC:51:pipe A] > [ 1.725736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006164f3e3 > [ 1.725759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fcb1012c > [ 1.725783] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 00000000fcb1012c > [ 1.725806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] > [ 1.725828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] > [ 1.725853] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 00000000fcb1012c > [ 1.725876] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 > [ 1.725898] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d365bfc5 > [ 1.725921] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fcb1012c > [ 1.725945] [drm:drm_atomic_check_only [drm]] checking 00000000fcb1012c > [ 1.725977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.725990] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.726002] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.726013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.726148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.726252] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.726302] [drm:drm_atomic_commit [drm]] committing 00000000fcb1012c > [ 1.740953] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fcb1012c > [ 1.740990] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fcb1012c > [ 1.776024] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000895e0f29 > [ 1.776052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000bf89eae0 state to 00000000895e0f29 > [ 1.776075] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002aa6a9f8 state to 00000000895e0f29 > [ 1.776097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f454a2f1 state to 00000000895e0f29 > [ 1.776121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f454a2f1 > [ 1.776142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000895e0f29 > [ 1.776163] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 > [ 1.776185] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001e3a4a97 state to 00000000895e0f29 > [ 1.776208] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 00000000895e0f29 > [ 1.776228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000f80a3c5 state to 00000000895e0f29 > [ 1.776249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000f80a3c5 > [ 1.776269] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000002f5f5ecb state to 00000000895e0f29 > [ 1.776289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000002f5f5ecb > [ 1.776311] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000082c8a15 state to 00000000895e0f29 > [ 1.776330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000017301ddd state to 00000000895e0f29 > [ 1.776350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000017301ddd > [ 1.776369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000bd98ba2f state to 00000000895e0f29 > [ 1.776389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000bd98ba2f > [ 1.776415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000bf89eae0 > [ 1.776436] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000895e0f29 > [ 1.776458] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002f3cb69d state to 00000000895e0f29 > [ 1.776479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [NOCRTC] > [ 1.776499] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002f3cb69d to [CRTC:51:pipe A] > [ 1.776522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001e3a4a97 > [ 1.776542] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000895e0f29 > [ 1.776562] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001bc59558 state to 00000000895e0f29 > [ 1.776582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [NOCRTC] > [ 1.776601] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001bc59558 to [CRTC:72:pipe B] > [ 1.776621] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e59c9ea1 state to 00000000895e0f29 > [ 1.776641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e59c9ea1 > [ 1.776659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000082c8a15 > [ 1.776679] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000895e0f29 > [ 1.776700] [drm:drm_atomic_check_only [drm]] checking 00000000895e0f29 > [ 1.776735] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.776746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.776757] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.776766] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.776890] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.776981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.777022] [drm:drm_atomic_commit [drm]] committing 00000000895e0f29 > [ 1.804096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 > [ 1.804107] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000895e0f29 > [ 1.804118] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001e6f8dac state to 00000000548834f9 > [ 1.804128] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000895e0f29 > [ 1.804139] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005b7d8c1d state to 00000000548834f9 > [ 1.804146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b0a2562b state to 00000000548834f9 > [ 1.804155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b0a2562b > [ 1.804162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000210ee201 state to 00000000548834f9 > [ 1.804172] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000210ee201 > [ 1.804179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074e96990 state to 00000000548834f9 > [ 1.804190] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000085f180bd state to 00000000548834f9 > [ 1.804196] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018d44f01 state to 00000000548834f9 > [ 1.804204] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018d44f01 > [ 1.804211] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c0bd820d state to 00000000548834f9 > [ 1.804218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c0bd820d > [ 1.804225] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c73eec69 state to 00000000548834f9 > [ 1.804232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000080dfd757 state to 00000000548834f9 > [ 1.804239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000080dfd757 > [ 1.804246] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f141c893 state to 00000000548834f9 > [ 1.804253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f141c893 > [ 1.804261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001e6f8dac > [ 1.804268] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 > [ 1.804281] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000f3f263f3 state to 00000000548834f9 > [ 1.804291] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [NOCRTC] > [ 1.804298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000f3f263f3 to [CRTC:51:pipe A] > [ 1.804306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000074e96990 > [ 1.804313] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 > [ 1.804320] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000af6800c9 state to 00000000548834f9 > [ 1.804327] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [NOCRTC] > [ 1.804334] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000af6800c9 to [CRTC:72:pipe B] > [ 1.804341] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 > [ 1.804348] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 > [ 1.804355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c73eec69 > [ 1.804362] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 > [ 1.804369] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 > [ 1.804388] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.804392] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.804398] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.804401] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.804446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.804478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.804499] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 > [ 1.823766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 > [ 1.823787] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 > [ 1.823804] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 1.823818] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 000000006432a660 > [ 1.823827] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 > [ 1.823835] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c471465 state to 000000006432a660 > [ 1.823845] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c471465 > [ 1.823853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5b7e29b state to 000000006432a660 > [ 1.823862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5b7e29b > [ 1.823870] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 > [ 1.823878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 > [ 1.823885] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e7bdd2e4 state to 000000006432a660 > [ 1.823893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e7bdd2e4 > [ 1.823901] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 > [ 1.823909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 > [ 1.823917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000087dc1fd8 state to 000000006432a660 > [ 1.823925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 000000006432a660 > [ 1.823933] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d > [ 1.823941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000df34b7b3 state to 000000006432a660 > [ 1.823949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000df34b7b3 > [ 1.823957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a > [ 1.823965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 1.823974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 > [ 1.823982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] > [ 1.823990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] > [ 1.824001] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa > [ 1.824009] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 1.824017] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 > [ 1.824025] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] > [ 1.824032] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] > [ 1.824041] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 1.824048] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 1.824056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000087dc1fd8 > [ 1.824063] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 1.824071] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 1.824082] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.824099] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.824106] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.824110] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.824157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.824191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.824208] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 1.841121] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 1.841136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 1.854405] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 1.854418] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057ed1a51 state to 00000000c6c933d1 > [ 1.854430] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 > [ 1.854441] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008ffba3f3 state to 00000000c6c933d1 > [ 1.854453] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008ffba3f3 > [ 1.854464] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 > [ 1.854476] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 > [ 1.854489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 > [ 1.854499] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 1.854509] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 > [ 1.854520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 > [ 1.854530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 1.854541] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 1.854552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 > [ 1.854561] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 > [ 1.854572] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab > [ 1.854584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 > [ 1.854594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 > [ 1.854606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000057ed1a51 > [ 1.854617] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 1.854628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 > [ 1.854640] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] > [ 1.854650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] > [ 1.854661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 > [ 1.854671] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 1.854682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 > [ 1.854692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] > [ 1.854703] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] > [ 1.854714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 > [ 1.854724] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 > [ 1.854734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 > [ 1.854744] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 1.854755] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 1.854767] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.854773] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.854779] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.854784] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.854860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.854907] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.854927] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 1.879165] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 1.879183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 1.879202] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 > [ 1.879217] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 1.879236] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 > [ 1.879248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 > [ 1.879265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 > [ 1.879281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 > [ 1.879294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 > [ 1.879306] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 > [ 1.879317] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 > [ 1.879328] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 > [ 1.879346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 > [ 1.879357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 > [ 1.879369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd > [ 1.879382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 > [ 1.879393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 > [ 1.879405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 > [ 1.879416] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 1.879428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 1.879440] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 > [ 1.879453] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 1.879465] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 > [ 1.879478] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] > [ 1.879490] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] > [ 1.879502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 > [ 1.879514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 1.879526] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 1.879538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 1.879549] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 1.879561] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 1.879573] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 1.879584] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 > [ 1.879596] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 1.879608] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 1.879622] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.879629] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.879635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.879641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.879713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.879765] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.879801] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 1.896360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 1.896381] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 1.912612] tsc: Refined TSC clocksource calibration: 3503.999 MHz > [ 1.912618] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x3282124c47b, max_idle_ns: 440795239402 ns > [ 1.912658] clocksource: Switched to clocksource tsc > [ 1.912681] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 1.912697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 > [ 1.912714] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 1.912729] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 > [ 1.912743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe > [ 1.912756] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 > [ 1.912769] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 > [ 1.912781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 1.912793] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 1.912804] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 > [ 1.912817] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 > [ 1.912829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 > [ 1.912841] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f > [ 1.912853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 > [ 1.912866] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 1.912878] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 > [ 1.912889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 > [ 1.912901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e > [ 1.912914] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f > [ 1.912926] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 1.912939] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000095845c0a state to 0000000098df4bf3 > [ 1.912952] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [NOCRTC] > [ 1.912964] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000095845c0a to [CRTC:51:pipe A] > [ 1.912976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 1.912987] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 1.912999] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 > [ 1.913011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] > [ 1.913023] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] > [ 1.913035] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 1.913047] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 1.913058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c > [ 1.913070] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 1.913082] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 1.913095] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.913102] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.913108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.913114] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.913187] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.913239] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.913263] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 1.929772] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 1.929793] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 1.949476] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a70fa07 > [ 1.949495] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006a25a70b state to 000000002a70fa07 > [ 1.949513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e46349dc state to 000000002a70fa07 > [ 1.949530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f2e9b45 state to 000000002a70fa07 > [ 1.949549] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f2e9b45 > [ 1.949565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e2798a03 state to 000000002a70fa07 > [ 1.949583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e2798a03 > [ 1.949599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f4491376 state to 000000002a70fa07 > [ 1.949615] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000dd2a82ac state to 000000002a70fa07 > [ 1.949630] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003292b89f state to 000000002a70fa07 > [ 1.949647] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003292b89f > [ 1.949662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000015cf0577 state to 000000002a70fa07 > [ 1.949679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000015cf0577 > [ 1.949694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 000000002a70fa07 > [ 1.949709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ab6fdf3f state to 000000002a70fa07 > [ 1.949725] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ab6fdf3f > [ 1.949744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bf01569 state to 000000002a70fa07 > [ 1.949760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bf01569 > [ 1.949777] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006a25a70b > [ 1.949793] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000002a70fa07 > [ 1.949811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003a5f3d7f state to 000000002a70fa07 > [ 1.949828] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [NOCRTC] > [ 1.949844] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003a5f3d7f to [CRTC:51:pipe A] > [ 1.949862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f4491376 > [ 1.949879] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000002a70fa07 > [ 1.949895] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000bd54c871 state to 000000002a70fa07 > [ 1.949911] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [NOCRTC] > [ 1.949926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000bd54c871 to [CRTC:72:pipe B] > [ 1.949943] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000de3ff82c state to 000000002a70fa07 > [ 1.949959] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000de3ff82c > [ 1.949974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 > [ 1.949990] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000002a70fa07 > [ 1.950007] [drm:drm_atomic_check_only [drm]] checking 000000002a70fa07 > [ 1.950024] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.950034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.950042] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.950050] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.950146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.950217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.950249] [drm:drm_atomic_commit [drm]] committing 000000002a70fa07 > [ 1.963116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a70fa07 > [ 1.963143] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a70fa07 > [ 1.975843] usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd > [ 1.982659] usb 1-7: New USB device found, idVendor=1307, idProduct=0330, bcdDevice= 1.00 > [ 1.982661] usb 1-7: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 1.982663] usb 1-7: Product: Mass Storage Device > [ 1.982664] usb 1-7: Manufacturer: Generic > [ 1.982665] usb 1-7: SerialNumber: 00000000000006 > [ 1.984947] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 1.984976] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000087dc1fd8 state to 000000006432a660 > [ 1.985005] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 > [ 1.985028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ada87627 state to 000000006432a660 > [ 1.985054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ada87627 > [ 1.985077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e7bdd2e4 state to 000000006432a660 > [ 1.985102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e7bdd2e4 > [ 1.985125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000083fdb4aa state to 000000006432a660 > [ 1.985148] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 > [ 1.985170] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e5b7e29b state to 000000006432a660 > [ 1.985194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e5b7e29b > [ 1.985218] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001c471465 state to 000000006432a660 > [ 1.985242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001c471465 > [ 1.985264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 > [ 1.985286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000bf357c4b state to 000000006432a660 > [ 1.985309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000bf357c4b > [ 1.985332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d9e36170 state to 000000006432a660 > [ 1.985355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d9e36170 > [ 1.985380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000087dc1fd8 > [ 1.985403] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 1.985435] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 > [ 1.985459] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] > [ 1.985483] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] > [ 1.985507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000083fdb4aa > [ 1.985530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 1.985553] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 > [ 1.985576] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 1.985600] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 1.985623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 1.985646] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 1.985668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a > [ 1.985691] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 1.985714] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 1.985747] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 1.985759] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 1.985771] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 1.985782] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 1.985898] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.985980] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 1.986020] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 1.988961] usb-storage 1-7:1.0: USB Mass Storage device detected > [ 1.989364] scsi host4: usb-storage 1-7:1.0 > [ 1.989455] usbcore: registered new interface driver usb-storage > [ 1.991210] usbcore: registered new interface driver uas > [ 1.996109] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 1.996129] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 1.999995] usb 2-1: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 > [ 1.999996] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.000778] hub 2-1:1.0: USB hub found > [ 2.000960] hub 2-1:1.0: 4 ports detected > [ 2.013903] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.013919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 > [ 2.013933] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 > [ 2.013946] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 > [ 2.013961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 > [ 2.013975] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.013989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000183fcb7 > [ 2.014002] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000aff706ab state to 00000000c6c933d1 > [ 2.014015] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 2.014028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.014042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fc1d1694 > [ 2.014055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 2.014068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 2.014080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.014092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.014105] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001964fcb3 > [ 2.014117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000dd33f136 state to 00000000c6c933d1 > [ 2.014129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000dd33f136 > [ 2.014143] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 > [ 2.014156] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.014169] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 > [ 2.014182] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] > [ 2.014195] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] > [ 2.014208] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000aff706ab > [ 2.014221] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.014234] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 > [ 2.014247] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] > [ 2.014260] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] > [ 2.014273] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 > [ 2.014286] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 > [ 2.014299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003e7fb927 > [ 2.014312] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.014325] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.014340] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.014348] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.014354] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.014361] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.014425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.014482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.014507] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.029646] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.029666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.047486] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000246f13a6 > [ 2.047504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f80a3c5 state to 00000000246f13a6 > [ 2.047520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ad566469 state to 00000000246f13a6 > [ 2.047534] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001e3a4a97 state to 00000000246f13a6 > [ 2.047550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001e3a4a97 > [ 2.047567] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000021449556 state to 00000000246f13a6 > [ 2.047581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000021449556 > [ 2.047595] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f454a2f1 state to 00000000246f13a6 > [ 2.047608] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 00000000246f13a6 > [ 2.047620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bf89eae0 state to 00000000246f13a6 > [ 2.047634] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bf89eae0 > [ 2.047648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000082c8a15 state to 00000000246f13a6 > [ 2.047661] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000082c8a15 > [ 2.047674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000017301ddd state to 00000000246f13a6 > [ 2.047690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9473c9b state to 00000000246f13a6 > [ 2.047704] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9473c9b > [ 2.047717] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000fdc091c8 state to 00000000246f13a6 > [ 2.047730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000fdc091c8 > [ 2.047744] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000000f80a3c5 > [ 2.047758] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000246f13a6 > [ 2.047779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000079f595ad state to 00000000246f13a6 > [ 2.047793] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [NOCRTC] > [ 2.047806] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000079f595ad to [CRTC:51:pipe A] > [ 2.047819] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f454a2f1 > [ 2.047833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000246f13a6 > [ 2.047846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005876474e state to 00000000246f13a6 > [ 2.047860] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [NOCRTC] > [ 2.047872] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005876474e to [CRTC:72:pipe B] > [ 2.047886] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000009be30044 state to 00000000246f13a6 > [ 2.047899] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000009be30044 > [ 2.047912] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000017301ddd > [ 2.047925] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000246f13a6 > [ 2.047938] [drm:drm_atomic_check_only [drm]] checking 00000000246f13a6 > [ 2.047954] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.047962] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.047968] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.047975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.048064] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.048124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.048152] [drm:drm_atomic_commit [drm]] committing 00000000246f13a6 > [ 2.063067] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000246f13a6 > [ 2.063089] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000246f13a6 > [ 2.084698] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000548834f9 > [ 2.084727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f1595a5f state to 00000000548834f9 > [ 2.084747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ca8a0e1e state to 00000000548834f9 > [ 2.084765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f97cb978 state to 00000000548834f9 > [ 2.084787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f97cb978 > [ 2.084806] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e88acfd1 state to 00000000548834f9 > [ 2.084826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e88acfd1 > [ 2.084845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000c2abb21 state to 00000000548834f9 > [ 2.084864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000ff2cde6 state to 00000000548834f9 > [ 2.084881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009f37190d state to 00000000548834f9 > [ 2.084900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009f37190d > [ 2.084918] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008793e16f state to 00000000548834f9 > [ 2.084937] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008793e16f > [ 2.084955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a71ddeb0 state to 00000000548834f9 > [ 2.084972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005371ffea state to 00000000548834f9 > [ 2.084990] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005371ffea > [ 2.085008] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000757b68ad state to 00000000548834f9 > [ 2.085026] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000757b68ad > [ 2.085045] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f1595a5f > [ 2.085064] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000548834f9 > [ 2.085084] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000e808d856 state to 00000000548834f9 > [ 2.085103] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [NOCRTC] > [ 2.085121] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000e808d856 to [CRTC:51:pipe A] > [ 2.085139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000c2abb21 > [ 2.085157] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000548834f9 > [ 2.085175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000004ac112a0 state to 00000000548834f9 > [ 2.085194] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [NOCRTC] > [ 2.085211] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000004ac112a0 to [CRTC:72:pipe B] > [ 2.085231] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d5d4f8b5 state to 00000000548834f9 > [ 2.085249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d5d4f8b5 > [ 2.085265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a71ddeb0 > [ 2.085283] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000548834f9 > [ 2.085303] [drm:drm_atomic_check_only [drm]] checking 00000000548834f9 > [ 2.085324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.085335] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.085344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.085353] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.085466] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.085547] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.085583] [drm:drm_atomic_commit [drm]] committing 00000000548834f9 > [ 2.096461] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000548834f9 > [ 2.096491] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000548834f9 > [ 2.119701] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.119718] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 > [ 2.119732] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 > [ 2.119746] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 > [ 2.119761] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be > [ 2.119781] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 > [ 2.119794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df > [ 2.119807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 > [ 2.119819] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 > [ 2.119831] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 > [ 2.119844] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 > [ 2.119858] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 > [ 2.119870] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b > [ 2.119882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 > [ 2.119893] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 > [ 2.119906] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 > [ 2.119917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.119930] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.119943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e > [ 2.119956] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.119971] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 > [ 2.119984] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 2.119996] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 2.120008] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a > [ 2.120020] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.120033] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.120045] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.120056] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.120073] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.120085] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.120096] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a > [ 2.120108] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.120120] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.120134] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.120141] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.120147] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.120153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.120236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.120291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.120315] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.129725] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.129746] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.143811] usb 1-10: new high-speed USB device number 3 using xhci_hcd > [ 2.146032] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.146049] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000053155f00 state to 0000000098df4bf3 > [ 2.146065] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.146077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007f5e6213 state to 0000000098df4bf3 > [ 2.146093] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007f5e6213 > [ 2.146107] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000515dc00f state to 0000000098df4bf3 > [ 2.146120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000515dc00f > [ 2.146133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 > [ 2.146145] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.146156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009d539ce0 state to 0000000098df4bf3 > [ 2.146170] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009d539ce0 > [ 2.146181] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a35c929d state to 0000000098df4bf3 > [ 2.146194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a35c929d > [ 2.146205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000046234f6 state to 0000000098df4bf3 > [ 2.146217] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 > [ 2.146229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e > [ 2.146240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 2.146252] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 > [ 2.146265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000053155f00 > [ 2.146278] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.146292] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000b34fddb1 state to 0000000098df4bf3 > [ 2.146305] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [NOCRTC] > [ 2.146317] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000b34fddb1 to [CRTC:51:pipe A] > [ 2.146329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d > [ 2.146341] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.146354] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000416eca0f state to 0000000098df4bf3 > [ 2.146366] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [NOCRTC] > [ 2.146377] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000416eca0f to [CRTC:72:pipe B] > [ 2.146390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.146402] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 2.146413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000046234f6 > [ 2.146425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.146438] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.146451] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.146458] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.146465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.146470] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.146546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.146602] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.146626] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.163065] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.163088] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.192362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 2.192398] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000091b367b1 state to 00000000fc0cb429 > [ 2.192425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 2.192450] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a6369fc8 state to 00000000fc0cb429 > [ 2.192481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a6369fc8 > [ 2.192510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000062109416 state to 00000000fc0cb429 > [ 2.192537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000062109416 > [ 2.192562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005fe5cc2f state to 00000000fc0cb429 > [ 2.192586] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 00000000fc0cb429 > [ 2.192609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000000bf01569 state to 00000000fc0cb429 > [ 2.192636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000000bf01569 > [ 2.192659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ab6fdf3f state to 00000000fc0cb429 > [ 2.192686] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ab6fdf3f > [ 2.192709] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 > [ 2.192731] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 > [ 2.192756] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 > [ 2.192779] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 > [ 2.192804] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f > [ 2.192830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000091b367b1 > [ 2.192855] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 2.192882] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000168ff23b state to 00000000fc0cb429 > [ 2.192908] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [NOCRTC] > [ 2.192933] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000168ff23b to [CRTC:51:pipe A] > [ 2.192960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005fe5cc2f > [ 2.192986] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 2.193011] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000da9b77f0 state to 00000000fc0cb429 > [ 2.193036] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [NOCRTC] > [ 2.193061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000da9b77f0 to [CRTC:72:pipe B] > [ 2.193088] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ca6e974 state to 00000000fc0cb429 > [ 2.193113] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ca6e974 > [ 2.193137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 > [ 2.193161] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 2.193187] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 2.193212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.193227] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.193239] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.193252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.193403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.193510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.193559] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 2.207959] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 2.207999] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 2.235181] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.235205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e536e28a state to 000000001ff947e6 > [ 2.235220] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 > [ 2.235233] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010a446a8 state to 000000001ff947e6 > [ 2.235247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010a446a8 > [ 2.235260] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c23288bf state to 000000001ff947e6 > [ 2.235274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c23288bf > [ 2.235287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d365bfc5 state to 000000001ff947e6 > [ 2.235301] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001775ba6b state to 000000001ff947e6 > [ 2.235316] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000009a9a5a77 state to 000000001ff947e6 > [ 2.235328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000009a9a5a77 > [ 2.235340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000382acb58 state to 000000001ff947e6 > [ 2.235352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000382acb58 > [ 2.235364] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006164f3e3 state to 000000001ff947e6 > [ 2.235376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000008409a024 state to 000000001ff947e6 > [ 2.235388] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000008409a024 > [ 2.235400] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000083c05b3d state to 000000001ff947e6 > [ 2.235412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000083c05b3d > [ 2.235425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000e536e28a > [ 2.235438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.235451] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000fc47d714 state to 000000001ff947e6 > [ 2.235464] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [NOCRTC] > [ 2.235476] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000fc47d714 to [CRTC:51:pipe A] > [ 2.235489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d365bfc5 > [ 2.235501] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.235514] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d05a5c4c state to 000000001ff947e6 > [ 2.235526] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [NOCRTC] > [ 2.235538] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d05a5c4c to [CRTC:72:pipe B] > [ 2.235551] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000048e8a8c4 state to 000000001ff947e6 > [ 2.235563] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000048e8a8c4 > [ 2.235575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006164f3e3 > [ 2.235587] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.235599] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.235628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.235635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.235641] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.235647] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.235730] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.235784] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.235815] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.246467] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.246485] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.258018] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.258028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 > [ 2.258037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 000000006432a660 > [ 2.258045] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.258054] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 > [ 2.258061] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 > [ 2.258069] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 > [ 2.258077] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.258084] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 000000006432a660 > [ 2.258092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.258100] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 > [ 2.258110] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 > [ 2.258118] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f > [ 2.258125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 > [ 2.258132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 > [ 2.258139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 > [ 2.258146] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.258153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.258161] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa > [ 2.258169] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.258178] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000227e02b1 state to 000000006432a660 > [ 2.258186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [NOCRTC] > [ 2.258193] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000227e02b1 to [CRTC:51:pipe A] > [ 2.258203] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 > [ 2.258210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.258219] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 > [ 2.258226] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] > [ 2.258233] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] > [ 2.258242] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.258249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.258256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 > [ 2.258263] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.258271] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.258281] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.258285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.258289] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.258293] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.258354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.258387] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.258403] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.274508] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.274524] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.287455] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.287470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 > [ 2.287483] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.287494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 > [ 2.287508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f > [ 2.287519] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 > [ 2.287531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 > [ 2.287542] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 2.287553] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.287563] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 > [ 2.287574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 2.287585] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 > [ 2.287595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 2.287610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 > [ 2.287624] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 > [ 2.287635] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 > [ 2.287645] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 > [ 2.287656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a > [ 2.287667] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c > [ 2.287678] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.287690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009b609533 state to 0000000098df4bf3 > [ 2.287701] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [NOCRTC] > [ 2.287712] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009b609533 to [CRTC:51:pipe A] > [ 2.287723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 2.287734] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.287744] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000050cb1035 state to 0000000098df4bf3 > [ 2.287755] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [NOCRTC] > [ 2.287765] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000050cb1035 to [CRTC:72:pipe B] > [ 2.287782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.287792] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 2.287803] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f > [ 2.287813] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.287825] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.287839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.287846] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.287851] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.287856] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.287928] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.287977] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.287999] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.292557] usb 1-10: New USB device found, idVendor=0557, idProduct=7000, bcdDevice= 0.00 > [ 2.292559] usb 1-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.293488] hub 1-10:1.0: USB hub found > [ 2.293604] hub 1-10:1.0: 4 ports detected > [ 2.296162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.296181] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.314444] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 2.314463] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c4a0e3a state to 00000000fc0cb429 > [ 2.314480] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000374f38f state to 00000000fc0cb429 > [ 2.314494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a8e00a70 state to 00000000fc0cb429 > [ 2.314511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a8e00a70 > [ 2.314525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007f2e9b45 state to 00000000fc0cb429 > [ 2.314540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000007f2e9b45 > [ 2.314554] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 > [ 2.314568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000001ca6e974 state to 00000000fc0cb429 > [ 2.314581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000f4491376 state to 00000000fc0cb429 > [ 2.314596] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000f4491376 > [ 2.314609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009bdf158a state to 00000000fc0cb429 > [ 2.314623] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009bdf158a > [ 2.314636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003292b89f state to 00000000fc0cb429 > [ 2.314649] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 > [ 2.314663] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 > [ 2.314677] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000d93e8df3 state to 00000000fc0cb429 > [ 2.314690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000d93e8df3 > [ 2.314705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c4a0e3a > [ 2.314719] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 2.314734] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000309bb6f5 state to 00000000fc0cb429 > [ 2.314749] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [NOCRTC] > [ 2.314763] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000309bb6f5 to [CRTC:51:pipe A] > [ 2.314776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 > [ 2.314791] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 2.314805] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000005b4f258 state to 00000000fc0cb429 > [ 2.314818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [NOCRTC] > [ 2.314832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000005b4f258 to [CRTC:72:pipe B] > [ 2.314846] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 > [ 2.314859] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 2.314872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003292b89f > [ 2.314886] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 2.314900] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 2.314915] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.314923] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.314930] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.314936] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.315024] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.315085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.315120] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 2.329803] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 2.329826] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 2.348527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.348550] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000df34b7b3 state to 000000006432a660 > [ 2.348569] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 > [ 2.348583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ed11a5b9 state to 000000006432a660 > [ 2.348600] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ed11a5b9 > [ 2.348615] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000f8d239cd state to 000000006432a660 > [ 2.348630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000f8d239cd > [ 2.348644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005f11c147 state to 000000006432a660 > [ 2.348661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 > [ 2.348674] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000457aaa57 state to 000000006432a660 > [ 2.348689] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000457aaa57 > [ 2.348702] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b1ca1c71 state to 000000006432a660 > [ 2.348716] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b1ca1c71 > [ 2.348730] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b4343291 state to 000000006432a660 > [ 2.348743] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000067db6375 state to 000000006432a660 > [ 2.348758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000067db6375 > [ 2.348777] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.348791] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.348806] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000df34b7b3 > [ 2.348821] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.348836] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 > [ 2.348851] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] > [ 2.348865] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] > [ 2.348883] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000005f11c147 > [ 2.348897] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.348911] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.348926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.348939] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.348954] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.348969] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.348982] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b4343291 > [ 2.348996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.349010] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.349026] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.349034] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.349041] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.349048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.349141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.349203] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.349231] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.363033] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.363056] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.381721] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.381738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008ffba3f3 state to 00000000c6c933d1 > [ 2.381754] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 > [ 2.381767] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 > [ 2.381784] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 > [ 2.381798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000dd33f136 state to 00000000c6c933d1 > [ 2.381813] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000dd33f136 > [ 2.381827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.381841] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 2.381853] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.381868] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 > [ 2.381882] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 2.381896] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 2.381909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.381922] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 > [ 2.381935] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab > [ 2.381948] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.381962] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 > [ 2.381976] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008ffba3f3 > [ 2.381992] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.382007] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000046dc0413 state to 00000000c6c933d1 > [ 2.382021] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [NOCRTC] > [ 2.382035] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000046dc0413 to [CRTC:51:pipe A] > [ 2.382048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 > [ 2.382062] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.382075] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000002e396b94 state to 00000000c6c933d1 > [ 2.382089] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [NOCRTC] > [ 2.382101] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000002e396b94 to [CRTC:72:pipe B] > [ 2.382115] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 > [ 2.382129] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f > [ 2.382142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 > [ 2.382155] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.382169] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.382186] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.382194] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.382206] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.382212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.382288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.382348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.382376] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.396184] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.396207] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.414905] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.414925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003eec9b7 state to 0000000098df4bf3 > [ 2.414942] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.414957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fb96f9d3 state to 0000000098df4bf3 > [ 2.414973] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fb96f9d3 > [ 2.414988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005342f7e7 state to 0000000098df4bf3 > [ 2.415003] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005342f7e7 > [ 2.415020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006ea264fe state to 0000000098df4bf3 > [ 2.415034] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.415047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000026a13e4f state to 0000000098df4bf3 > [ 2.415062] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000026a13e4f > [ 2.415076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e81eafbe state to 0000000098df4bf3 > [ 2.415090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e81eafbe > [ 2.415103] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f101de7e state to 0000000098df4bf3 > [ 2.415123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 0000000098df4bf3 > [ 2.415137] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a > [ 2.415150] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000025544875 state to 0000000098df4bf3 > [ 2.415164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000025544875 > [ 2.415180] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003eec9b7 > [ 2.415194] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.415209] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009e77ee4b state to 0000000098df4bf3 > [ 2.415227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [NOCRTC] > [ 2.415241] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009e77ee4b to [CRTC:51:pipe A] > [ 2.415255] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006ea264fe > [ 2.415269] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.415284] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006fd04029 state to 0000000098df4bf3 > [ 2.415298] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [NOCRTC] > [ 2.415311] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006fd04029 to [CRTC:72:pipe B] > [ 2.415328] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.415342] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 2.415355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f101de7e > [ 2.415369] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.415383] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.415399] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.415407] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.415414] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.415423] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.415506] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.415569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.415598] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.420197] usb 2-2: new SuperSpeed Gen 1 USB device number 3 using xhci_hcd > [ 2.429805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.429829] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.440080] usb 2-2: New USB device found, idVendor=0451, idProduct=8140, bcdDevice= 1.00 > [ 2.440081] usb 2-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.441055] hub 2-2:1.0: USB hub found > [ 2.441232] hub 2-2:1.0: 4 ports detected > [ 2.451314] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 2.451340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a6369fc8 state to 00000000fc0cb429 > [ 2.451359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 2.451375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000091b367b1 state to 00000000fc0cb429 > [ 2.451395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000091b367b1 > [ 2.451412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000005fe5cc2f state to 00000000fc0cb429 > [ 2.451429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000005fe5cc2f > [ 2.451446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bf01569 state to 00000000fc0cb429 > [ 2.451462] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 > [ 2.451477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ab6fdf3f state to 00000000fc0cb429 > [ 2.451494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ab6fdf3f > [ 2.451510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 > [ 2.451526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b > [ 2.451543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d93e8df3 state to 00000000fc0cb429 > [ 2.451559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000015cf0577 state to 00000000fc0cb429 > [ 2.451575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000015cf0577 > [ 2.451591] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003292b89f state to 00000000fc0cb429 > [ 2.451607] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003292b89f > [ 2.451624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000a6369fc8 > [ 2.451641] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 2.451660] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ee6ef05 state to 00000000fc0cb429 > [ 2.451677] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [NOCRTC] > [ 2.451693] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ee6ef05 to [CRTC:51:pipe A] > [ 2.451710] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bf01569 > [ 2.451726] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 2.451743] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009647804d state to 00000000fc0cb429 > [ 2.451760] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [NOCRTC] > [ 2.451784] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009647804d to [CRTC:72:pipe B] > [ 2.451801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000dd2a82ac state to 00000000fc0cb429 > [ 2.451817] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000dd2a82ac > [ 2.451832] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d93e8df3 > [ 2.451848] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 2.451865] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 2.451883] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.451892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.451900] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.451908] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.452011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.452082] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.452114] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 2.463087] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 2.463114] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 2.484902] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.484925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 > [ 2.484941] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 000000006432a660 > [ 2.484955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 > [ 2.484971] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 > [ 2.484985] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 > [ 2.485000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f > [ 2.485015] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.485028] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 000000006432a660 > [ 2.485041] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.485055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 > [ 2.485067] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 > [ 2.485081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 > [ 2.485094] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.485106] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 > [ 2.485120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa > [ 2.485132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.485146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.485160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 > [ 2.485174] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.485189] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 000000006432a660 > [ 2.485203] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] > [ 2.485216] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] > [ 2.485229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 > [ 2.485243] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.485257] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 > [ 2.485270] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 2.485283] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 2.485297] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.485310] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.485322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 > [ 2.485336] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.485349] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.485365] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.485373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.485380] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.485386] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.485476] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.485536] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.485568] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.496321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.496343] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.514099] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.514115] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000086e6c525 state to 00000000c6c933d1 > [ 2.514130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 > [ 2.514143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000076facd10 state to 00000000c6c933d1 > [ 2.514159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000076facd10 > [ 2.514173] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000900779b1 state to 00000000c6c933d1 > [ 2.514187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000900779b1 > [ 2.514201] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.514214] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 2.514227] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 > [ 2.514241] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab > [ 2.514254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.514267] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 > [ 2.514281] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 > [ 2.514293] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.514306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 > [ 2.514319] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.514332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 > [ 2.514346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000086e6c525 > [ 2.514359] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.514373] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000006978e08c state to 00000000c6c933d1 > [ 2.514389] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [NOCRTC] > [ 2.514402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000006978e08c to [CRTC:51:pipe A] > [ 2.514415] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 > [ 2.514429] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.514442] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009efdc675 state to 00000000c6c933d1 > [ 2.514455] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [NOCRTC] > [ 2.514467] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009efdc675 to [CRTC:72:pipe B] > [ 2.514485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 > [ 2.514499] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 > [ 2.514511] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f > [ 2.514523] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.514537] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.514551] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.514559] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.514566] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.514572] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.514659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.514717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.514743] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.529754] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.529779] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.550511] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.550530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001c471465 state to 000000006432a660 > [ 2.550547] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 > [ 2.550562] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059814b3a state to 000000006432a660 > [ 2.550581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059814b3a > [ 2.550597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bf357c4b state to 000000006432a660 > [ 2.550614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000bf357c4b > [ 2.550629] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d9e36170 state to 000000006432a660 > [ 2.550644] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 > [ 2.550658] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 000000006432a660 > [ 2.550675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a > [ 2.550690] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000071f245df state to 000000006432a660 > [ 2.550705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000071f245df > [ 2.550720] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000074f436be state to 000000006432a660 > [ 2.550735] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000041c6228e state to 000000006432a660 > [ 2.550750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000041c6228e > [ 2.550765] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.550780] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.550798] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001c471465 > [ 2.550814] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.550831] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 > [ 2.550847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 2.550862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 2.550876] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000d9e36170 > [ 2.550891] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.550907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.550922] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.550937] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.550953] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.550967] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.550981] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000074f436be > [ 2.550996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.551012] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.551029] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.551037] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.551045] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.551053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.551151] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.551217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.551247] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.563034] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.563060] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.567816] usb 1-11: new high-speed USB device number 4 using xhci_hcd > [ 2.582973] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.582995] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000098df4bf3 > [ 2.583010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.583024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000483335fe state to 0000000098df4bf3 > [ 2.583039] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000483335fe > [ 2.583052] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000fcc975 state to 0000000098df4bf3 > [ 2.583066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000fcc975 > [ 2.583080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 2.583096] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.583108] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001c64fec3 state to 0000000098df4bf3 > [ 2.583121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001c64fec3 > [ 2.583133] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000001726835f state to 0000000098df4bf3 > [ 2.583146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000001726835f > [ 2.583159] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000006011267c state to 0000000098df4bf3 > [ 2.583171] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 2.583184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 > [ 2.583197] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f3527d8e state to 0000000098df4bf3 > [ 2.583210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f3527d8e > [ 2.583224] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f > [ 2.583237] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.583251] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 0000000098df4bf3 > [ 2.583265] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] > [ 2.583278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] > [ 2.583290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 2.583303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.583317] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d45c24f4 state to 0000000098df4bf3 > [ 2.583329] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [NOCRTC] > [ 2.583342] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d45c24f4 to [CRTC:72:pipe B] > [ 2.583355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.583368] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 2.583380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000006011267c > [ 2.583392] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.583406] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.583424] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.583432] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.583438] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.583444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.583528] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.583585] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.583612] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.596477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.596495] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.610890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.610906] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000382acb58 state to 000000001ff947e6 > [ 2.610919] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 000000001ff947e6 > [ 2.610930] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009a9a5a77 state to 000000001ff947e6 > [ 2.610943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009a9a5a77 > [ 2.610955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d365bfc5 state to 000000001ff947e6 > [ 2.610966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d365bfc5 > [ 2.610978] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c23288bf state to 000000001ff947e6 > [ 2.610989] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 000000001ff947e6 > [ 2.611000] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000010a446a8 state to 000000001ff947e6 > [ 2.611012] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000010a446a8 > [ 2.611022] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e536e28a state to 000000001ff947e6 > [ 2.611033] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e536e28a > [ 2.611044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fac02d29 state to 000000001ff947e6 > [ 2.611054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e23783d2 state to 000000001ff947e6 > [ 2.611065] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e23783d2 > [ 2.611075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000009ecd9d0a state to 000000001ff947e6 > [ 2.611086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000009ecd9d0a > [ 2.611097] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000382acb58 > [ 2.611109] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.611121] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000949ef34b state to 000000001ff947e6 > [ 2.611132] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [NOCRTC] > [ 2.611143] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000949ef34b to [CRTC:51:pipe A] > [ 2.611153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c23288bf > [ 2.611164] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.611175] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000025f34563 state to 000000001ff947e6 > [ 2.611186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [NOCRTC] > [ 2.611196] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000025f34563 to [CRTC:72:pipe B] > [ 2.611213] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 000000001ff947e6 > [ 2.611224] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b > [ 2.611234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fac02d29 > [ 2.611244] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.611255] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.611268] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.611274] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.611280] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.611285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.611363] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.611411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.611436] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.624544] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.624568] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.648394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.648422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000083fdb4aa state to 000000006432a660 > [ 2.648448] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000f048a61 state to 000000006432a660 > [ 2.648470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.648494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e7bdd2e4 > [ 2.648515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ada87627 state to 000000006432a660 > [ 2.648536] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ada87627 > [ 2.648557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.648577] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7f71e60 state to 000000006432a660 > [ 2.648596] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.648618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000c3b3ca94 > [ 2.648637] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e5892e4f state to 000000006432a660 > [ 2.648657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000e5892e4f > [ 2.648680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000003073c677 state to 000000006432a660 > [ 2.648699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001f82d691 state to 000000006432a660 > [ 2.648719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001f82d691 > [ 2.648738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.648758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.648785] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000083fdb4aa > [ 2.648805] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.648826] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ddd4fdd state to 000000006432a660 > [ 2.648848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [NOCRTC] > [ 2.648867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ddd4fdd to [CRTC:51:pipe A] > [ 2.648892] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000087dc1fd8 > [ 2.648912] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.648933] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000140b0238 state to 000000006432a660 > [ 2.648953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [NOCRTC] > [ 2.648972] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000140b0238 to [CRTC:72:pipe B] > [ 2.648999] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 2.649018] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 2.649037] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000003073c677 > [ 2.649057] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.649077] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.649105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.649116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.649126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.649136] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.649258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.649348] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.649388] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.663045] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.663078] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.695073] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.695099] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000046234f6 state to 0000000098df4bf3 > [ 2.695121] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.695139] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a35c929d state to 0000000098df4bf3 > [ 2.695164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a35c929d > [ 2.695189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 0000000098df4bf3 > [ 2.695210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 > [ 2.695229] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008cab647d state to 0000000098df4bf3 > [ 2.695248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.695265] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 0000000098df4bf3 > [ 2.695284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f > [ 2.695303] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007f5e6213 state to 0000000098df4bf3 > [ 2.695322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007f5e6213 > [ 2.695340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000053155f00 state to 0000000098df4bf3 > [ 2.695357] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000f3527d8e state to 0000000098df4bf3 > [ 2.695376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000f3527d8e > [ 2.695396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000b538e2a8 state to 0000000098df4bf3 > [ 2.695414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000b538e2a8 > [ 2.695435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000046234f6 > [ 2.695454] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.695474] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 0000000098df4bf3 > [ 2.695494] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] > [ 2.695512] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] > [ 2.695531] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008cab647d > [ 2.695550] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.695569] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000c182e4a6 state to 0000000098df4bf3 > [ 2.695587] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [NOCRTC] > [ 2.695604] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000c182e4a6 to [CRTC:72:pipe B] > [ 2.695623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.695641] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e8d04c58 > [ 2.695658] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000053155f00 > [ 2.695676] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.695695] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.695725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.695736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.695745] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.695755] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.695886] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.695968] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.696005] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.713154] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.713185] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.716173] usb 1-11: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 > [ 2.716176] usb 1-11: New USB device strings: Mfr=0, Product=0, SerialNumber=1 > [ 2.716179] usb 1-11: SerialNumber: DC0F18713FF2 > [ 2.717025] hub 1-11:1.0: USB hub found > [ 2.717053] hub 1-11:1.0: 4 ports detected > [ 2.744349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.744373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000098081998 state to 000000001ff947e6 > [ 2.744393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002ba4f36a state to 000000001ff947e6 > [ 2.744411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000007284ebf4 state to 000000001ff947e6 > [ 2.744433] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000007284ebf4 > [ 2.744451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000092bd7e4c state to 000000001ff947e6 > [ 2.744470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000092bd7e4c > [ 2.744488] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000687f38c3 state to 000000001ff947e6 > [ 2.744505] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003eebba06 state to 000000001ff947e6 > [ 2.744522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000072a9793c state to 000000001ff947e6 > [ 2.744540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000072a9793c > [ 2.744559] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 000000001ff947e6 > [ 2.744577] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac > [ 2.744593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 000000001ff947e6 > [ 2.744609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 000000001ff947e6 > [ 2.744627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 > [ 2.744643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 000000001ff947e6 > [ 2.744660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c > [ 2.744678] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000098081998 > [ 2.744696] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.744715] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000007ebbd72c state to 000000001ff947e6 > [ 2.744734] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [NOCRTC] > [ 2.744751] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000007ebbd72c to [CRTC:51:pipe A] > [ 2.744773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000687f38c3 > [ 2.744790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.744808] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001175f931 state to 000000001ff947e6 > [ 2.744825] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [NOCRTC] > [ 2.744842] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001175f931 to [CRTC:72:pipe B] > [ 2.744860] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000053a23bd6 state to 000000001ff947e6 > [ 2.744877] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000053a23bd6 > [ 2.744893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e > [ 2.744911] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.744928] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.744948] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.744958] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.744969] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.744977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.745085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.745164] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.745209] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.757894] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.757923] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.781266] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.781290] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000067db6375 state to 000000006432a660 > [ 2.781313] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 000000006432a660 > [ 2.781332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b4343291 state to 000000006432a660 > [ 2.781353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b4343291 > [ 2.781371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 000000006432a660 > [ 2.781390] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 > [ 2.781409] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000457aaa57 state to 000000006432a660 > [ 2.781426] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 000000006432a660 > [ 2.781443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005f11c147 state to 000000006432a660 > [ 2.781462] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005f11c147 > [ 2.781478] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000f8d239cd state to 000000006432a660 > [ 2.781496] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000f8d239cd > [ 2.781514] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ed11a5b9 state to 000000006432a660 > [ 2.781530] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000df34b7b3 state to 000000006432a660 > [ 2.781548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000df34b7b3 > [ 2.781565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002938b22d state to 000000006432a660 > [ 2.781583] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002938b22d > [ 2.781602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000067db6375 > [ 2.781620] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.781639] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004712a1c7 state to 000000006432a660 > [ 2.781658] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [NOCRTC] > [ 2.781675] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004712a1c7 to [CRTC:51:pipe A] > [ 2.781694] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000457aaa57 > [ 2.781712] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.781729] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 2.781747] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 2.781764] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 2.781782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.781800] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.781816] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ed11a5b9 > [ 2.781833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.781851] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.781869] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.781879] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.781888] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.781897] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.782005] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.782084] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.782120] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.796434] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.796463] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.815843] usb 1-10.1: new low-speed USB device number 5 using xhci_hcd > [ 2.830298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.830323] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dd33f136 state to 00000000c6c933d1 > [ 2.830358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 > [ 2.830378] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000057ed1a51 state to 00000000c6c933d1 > [ 2.830401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000057ed1a51 > [ 2.830422] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008ffba3f3 state to 00000000c6c933d1 > [ 2.830443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008ffba3f3 > [ 2.830466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.830485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 2.830504] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.830525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000003e7fb927 > [ 2.830544] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000068c6126f state to 00000000c6c933d1 > [ 2.830564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000068c6126f > [ 2.830583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.830601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000aff706ab state to 00000000c6c933d1 > [ 2.830621] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000aff706ab > [ 2.830640] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.830659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000183fcb7 > [ 2.830684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000dd33f136 > [ 2.830704] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.830725] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000002e396b94 state to 00000000c6c933d1 > [ 2.830746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [NOCRTC] > [ 2.830766] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000002e396b94 to [CRTC:51:pipe A] > [ 2.830788] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000001964fcb3 > [ 2.830808] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.830828] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000046dc0413 state to 00000000c6c933d1 > [ 2.830848] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [NOCRTC] > [ 2.830867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000046dc0413 to [CRTC:72:pipe B] > [ 2.830890] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 > [ 2.830910] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 > [ 2.830928] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000fc1d1694 > [ 2.830948] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.830968] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.831004] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.831015] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.831025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.831035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.831156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.831242] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.831281] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.846410] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.846458] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 2.877085] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000098df4bf3 > [ 2.877104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006011267c state to 0000000098df4bf3 > [ 2.877120] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e8d04c58 state to 0000000098df4bf3 > [ 2.877135] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001726835f state to 0000000098df4bf3 > [ 2.877153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001726835f > [ 2.877167] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000001c64fec3 state to 0000000098df4bf3 > [ 2.877181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000001c64fec3 > [ 2.877195] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000865de88c state to 0000000098df4bf3 > [ 2.877209] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004fb57322 state to 0000000098df4bf3 > [ 2.877222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 0000000098df4bf3 > [ 2.877236] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 2.877248] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 0000000098df4bf3 > [ 2.877262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 2.877275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008c95634f state to 0000000098df4bf3 > [ 2.877287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000025544875 state to 0000000098df4bf3 > [ 2.877301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000025544875 > [ 2.877313] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000002f4e481a state to 0000000098df4bf3 > [ 2.877327] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000002f4e481a > [ 2.877344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000006011267c > [ 2.877357] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000098df4bf3 > [ 2.877372] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 0000000098df4bf3 > [ 2.877386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] > [ 2.877399] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] > [ 2.877412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000865de88c > [ 2.877426] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000098df4bf3 > [ 2.877439] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000768d9213 state to 0000000098df4bf3 > [ 2.877452] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [NOCRTC] > [ 2.877465] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000768d9213 to [CRTC:72:pipe B] > [ 2.877479] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000027b33ee1 state to 0000000098df4bf3 > [ 2.877492] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000027b33ee1 > [ 2.877504] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008c95634f > [ 2.877517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000098df4bf3 > [ 2.877531] [drm:drm_atomic_check_only [drm]] checking 0000000098df4bf3 > [ 2.877553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.877561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.877571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.877577] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.877659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.877719] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.877747] [drm:drm_atomic_commit [drm]] committing 0000000098df4bf3 > [ 2.891314] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000098df4bf3 > [ 2.891333] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000098df4bf3 > [ 2.906312] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ff947e6 > [ 2.906333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000918919b3 state to 000000001ff947e6 > [ 2.906347] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a4f0e9bc state to 000000001ff947e6 > [ 2.906358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000005a00270 state to 000000001ff947e6 > [ 2.906372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000005a00270 > [ 2.906384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000512c7fb3 state to 000000001ff947e6 > [ 2.906396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000512c7fb3 > [ 2.906408] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000063c0bfb2 state to 000000001ff947e6 > [ 2.906419] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000053a23bd6 state to 000000001ff947e6 > [ 2.906433] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000004acae8d3 state to 000000001ff947e6 > [ 2.906445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000004acae8d3 > [ 2.906456] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 000000001ff947e6 > [ 2.906468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 > [ 2.906479] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 000000001ff947e6 > [ 2.906489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a4c468ad state to 000000001ff947e6 > [ 2.906500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a4c468ad > [ 2.906511] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000320b468c state to 000000001ff947e6 > [ 2.906522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000320b468c > [ 2.906542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000918919b3 > [ 2.906555] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000001ff947e6 > [ 2.906568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ba4c5dc3 state to 000000001ff947e6 > [ 2.906580] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [NOCRTC] > [ 2.906591] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ba4c5dc3 to [CRTC:51:pipe A] > [ 2.906602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000063c0bfb2 > [ 2.906613] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000001ff947e6 > [ 2.906625] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ae0223f3 state to 000000001ff947e6 > [ 2.906636] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [NOCRTC] > [ 2.906646] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ae0223f3 to [CRTC:72:pipe B] > [ 2.906661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000003eebba06 state to 000000001ff947e6 > [ 2.906672] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000003eebba06 > [ 2.906682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d > [ 2.906693] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000001ff947e6 > [ 2.906705] [drm:drm_atomic_check_only [drm]] checking 000000001ff947e6 > [ 2.906718] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.906725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.906731] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.906736] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.906813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.906863] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.906886] [drm:drm_atomic_commit [drm]] committing 000000001ff947e6 > [ 2.913164] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ff947e6 > [ 2.913183] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ff947e6 > [ 2.933406] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 2.933430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001f82d691 state to 000000006432a660 > [ 2.933451] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002719d414 state to 000000006432a660 > [ 2.933468] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003073c677 state to 000000006432a660 > [ 2.933490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003073c677 > [ 2.933508] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e5892e4f state to 000000006432a660 > [ 2.933527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e5892e4f > [ 2.933545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c3b3ca94 state to 000000006432a660 > [ 2.933563] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000069886caf state to 000000006432a660 > [ 2.933583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000087dc1fd8 state to 000000006432a660 > [ 2.933601] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000087dc1fd8 > [ 2.933618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ada87627 state to 000000006432a660 > [ 2.933636] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ada87627 > [ 2.933653] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000e7bdd2e4 state to 000000006432a660 > [ 2.933670] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000083fdb4aa state to 000000006432a660 > [ 2.933687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000083fdb4aa > [ 2.933705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 2.933723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 2.933741] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001f82d691 > [ 2.933759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 2.933778] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000052663e8f state to 000000006432a660 > [ 2.933800] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [NOCRTC] > [ 2.933818] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000052663e8f to [CRTC:51:pipe A] > [ 2.933836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000c3b3ca94 > [ 2.933853] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 2.933871] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 000000006432a660 > [ 2.933888] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 2.933905] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 2.933923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 000000006432a660 > [ 2.933940] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 2.933957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000e7bdd2e4 > [ 2.933974] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 2.933992] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 2.934021] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.934031] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.934039] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.934048] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.934156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.934235] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.934270] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 2.945099] usb 1-10.1: New USB device found, idVendor=0557, idProduct=2419, bcdDevice= 1.00 > [ 2.945102] usb 1-10.1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.946202] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 2.946230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 2.969637] hid: raw HID events driver (C) Jiri Kosina > [ 2.980218] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 2.980244] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000076facd10 state to 00000000c6c933d1 > [ 2.980267] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 > [ 2.980286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000086e6c525 state to 00000000c6c933d1 > [ 2.980309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000086e6c525 > [ 2.980330] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000097efae80 state to 00000000c6c933d1 > [ 2.980351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000097efae80 > [ 2.980372] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000183fcb7 state to 00000000c6c933d1 > [ 2.980391] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 2.980410] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000aff706ab state to 00000000c6c933d1 > [ 2.980431] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000aff706ab > [ 2.980449] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000fc1d1694 state to 00000000c6c933d1 > [ 2.980470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000fc1d1694 > [ 2.980489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000068c6126f state to 00000000c6c933d1 > [ 2.980507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000003e7fb927 state to 00000000c6c933d1 > [ 2.980527] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000003e7fb927 > [ 2.980547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001964fcb3 state to 00000000c6c933d1 > [ 2.980566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001964fcb3 > [ 2.980587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000076facd10 > [ 2.980607] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 2.980628] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 > [ 2.980650] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] > [ 2.980670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] > [ 2.980690] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000183fcb7 > [ 2.980709] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 2.980728] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 > [ 2.980748] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] > [ 2.980767] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] > [ 2.980792] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 > [ 2.980812] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 > [ 2.980830] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000068c6126f > [ 2.980850] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 2.980871] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 2.980898] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 2.980910] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 2.980920] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 2.980929] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 2.981048] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.981050] usbcore: registered new interface driver usbhid > [ 2.981135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 2.981135] usbhid: USB HID core driver > [ 2.981182] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 2.983750] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.0/0003:0557:2419.0001/input/input4 > [ 2.996172] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 2.996195] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.016364] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006432a660 > [ 3.016380] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000041c6228e state to 000000006432a660 > [ 3.016393] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006ede65dd state to 000000006432a660 > [ 3.016405] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000074f436be state to 000000006432a660 > [ 3.016419] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000074f436be > [ 3.016432] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000071f245df state to 000000006432a660 > [ 3.016445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000071f245df > [ 3.016458] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 000000006432a660 > [ 3.016470] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a48ebd6e state to 000000006432a660 > [ 3.016481] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000d9e36170 state to 000000006432a660 > [ 3.016494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000d9e36170 > [ 3.016507] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000bf357c4b state to 000000006432a660 > [ 3.016519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000bf357c4b > [ 3.016531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000059814b3a state to 000000006432a660 > [ 3.016543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001c471465 state to 000000006432a660 > [ 3.016556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001c471465 > [ 3.016568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e5b7e29b state to 000000006432a660 > [ 3.016580] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e5b7e29b > [ 3.016593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000041c6228e > [ 3.016606] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006432a660 > [ 3.016619] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001b5c4b62 state to 000000006432a660 > [ 3.016632] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [NOCRTC] > [ 3.016644] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001b5c4b62 to [CRTC:51:pipe A] > [ 3.016657] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a > [ 3.016669] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006432a660 > [ 3.016682] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ce20e5c8 state to 000000006432a660 > [ 3.016694] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [NOCRTC] > [ 3.016706] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ce20e5c8 to [CRTC:72:pipe B] > [ 3.016719] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 000000006432a660 > [ 3.016731] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 3.016743] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000059814b3a > [ 3.016755] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006432a660 > [ 3.016767] [drm:drm_atomic_check_only [drm]] checking 000000006432a660 > [ 3.016778] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.016785] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.016791] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.016798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.016860] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.016917] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.016940] [drm:drm_atomic_commit [drm]] committing 000000006432a660 > [ 3.020983] scsi 4:0:0:0: Direct-Access Generic Compact Flash 0.00 PQ: 0 ANSI: 2 > [ 3.021765] scsi 4:0:0:1: Direct-Access Generic SD/MMC 0.00 PQ: 0 ANSI: 2 > [ 3.022194] scsi 4:0:0:2: Direct-Access Generic microSD 0.00 PQ: 0 ANSI: 2 > [ 3.022768] scsi 4:0:0:3: Direct-Access Generic MS/MS-PRO 0.00 PQ: 0 ANSI: 2 > [ 3.023138] scsi 4:0:0:4: Direct-Access Generic SM/xD-Picture 0.00 PQ: 0 ANSI: 2 > [ 3.029581] sd 1:0:0:0: [sda] 1000215216 512-byte logical blocks: (512 GB/477 GiB) > [ 3.029588] sd 1:0:0:0: [sda] Write Protect is off > [ 3.029589] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00 > [ 3.029597] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA > [ 3.043978] hid-generic 0003:0557:2419.0001: input,hidraw0: USB HID v1.00 Keyboard [HID 0557:2419] on usb-0000:00:14.0-10.1/input0 > [ 3.044084] input: HID 0557:2419 as /devices/pci0000:00/0000:00:14.0/usb1/1-10/1-10.1/1-10.1:1.1/0003:0557:2419.0002/input/input5 > [ 3.044277] hid-generic 0003:0557:2419.0002: input,hidraw1: USB HID v1.00 Mouse [HID 0557:2419] on usb-0000:00:14.0-10.1/input1 > [ 3.044891] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006432a660 > [ 3.044908] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 > [ 3.044928] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006432a660 > [ 3.044945] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007b36813f state to 00000000c29bd936 > [ 3.044964] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ec014e4 state to 00000000c29bd936 > [ 3.044984] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000555d146c state to 00000000c29bd936 > [ 3.045005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000555d146c > [ 3.045023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b2cdb294 state to 00000000c29bd936 > [ 3.045041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b2cdb294 > [ 3.045060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000053454233 state to 00000000c29bd936 > [ 3.045079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a746018c state to 00000000c29bd936 > [ 3.045097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 > [ 3.045113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 > [ 3.045123] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000b5f6abf5 state to 00000000c29bd936 > [ 3.045134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000b5f6abf5 > [ 3.045147] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000c775be6 state to 00000000c29bd936 > [ 3.045156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005d690c84 state to 00000000c29bd936 > [ 3.045167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005d690c84 > [ 3.045177] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000122a804f state to 00000000c29bd936 > [ 3.045188] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000122a804f > [ 3.045200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007b36813f > [ 3.045211] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 > [ 3.045222] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004edc31e9 state to 00000000c29bd936 > [ 3.045238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [NOCRTC] > [ 3.045256] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004edc31e9 to [CRTC:51:pipe A] > [ 3.045274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000053454233 > [ 3.045294] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 > [ 3.045312] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000005d1fe044 state to 00000000c29bd936 > [ 3.045325] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [NOCRTC] > [ 3.045335] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000005d1fe044 to [CRTC:72:pipe B] > [ 3.045350] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001ef13faa state to 00000000c29bd936 > [ 3.045360] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001ef13faa > [ 3.045369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000c775be6 > [ 3.045380] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 > [ 3.045390] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 > [ 3.045403] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.045410] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.045415] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.045420] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.045496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.045543] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.045577] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 > [ 3.052647] sd 4:0:0:4: [sdf] Attached SCSI removable disk > [ 3.054117] sda: sda1 sda2 < sda5 > > [ 3.054604] sd 1:0:0:0: [sda] supports TCG Opal > [ 3.054605] sd 1:0:0:0: [sda] Attached SCSI disk > [ 3.056264] sd 4:0:0:3: [sde] Attached SCSI removable disk > [ 3.057329] sd 4:0:0:1: [sdc] Attached SCSI removable disk > [ 3.057645] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 > [ 3.057661] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 > [ 3.060799] sd 4:0:0:0: [sdb] Attached SCSI removable disk > [ 3.071802] usb 1-12: new high-speed USB device number 6 using xhci_hcd > [ 3.072920] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 > [ 3.072942] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fac02d29 state to 00000000ffbe70d8 > [ 3.072961] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001775ba6b state to 00000000ffbe70d8 > [ 3.072980] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000009ecd9d0a state to 00000000ffbe70d8 > [ 3.072992] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000009ecd9d0a > [ 3.073004] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000098081998 state to 00000000ffbe70d8 > [ 3.073017] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000098081998 > [ 3.073035] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007284ebf4 state to 00000000ffbe70d8 > [ 3.073054] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 > [ 3.073071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000092bd7e4c state to 00000000ffbe70d8 > [ 3.073089] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000092bd7e4c > [ 3.073105] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000003b9a39ac state to 00000000ffbe70d8 > [ 3.073123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000003b9a39ac > [ 3.073140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df7d816e state to 00000000ffbe70d8 > [ 3.073157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001261a608 state to 00000000ffbe70d8 > [ 3.073175] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001261a608 > [ 3.073189] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000e3b8d12c state to 00000000ffbe70d8 > [ 3.073199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000e3b8d12c > [ 3.073211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000fac02d29 > [ 3.073222] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 > [ 3.073233] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000be46149d state to 00000000ffbe70d8 > [ 3.073244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [NOCRTC] > [ 3.073254] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000be46149d to [CRTC:51:pipe A] > [ 3.073265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000007284ebf4 > [ 3.073276] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 > [ 3.073286] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000068a1fb01 state to 00000000ffbe70d8 > [ 3.073297] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [NOCRTC] > [ 3.073307] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000068a1fb01 to [CRTC:72:pipe B] > [ 3.073318] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000cf23fbdd state to 00000000ffbe70d8 > [ 3.073328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000cf23fbdd > [ 3.073338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df7d816e > [ 3.073348] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 > [ 3.073359] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 > [ 3.073371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.073377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.073382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.073387] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.073458] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.073505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.073529] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 > [ 3.073552] sd 4:0:0:2: [sdd] Attached SCSI removable disk > [ 3.079604] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 > [ 3.079650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 > [ 3.108427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 > [ 3.108443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000122a804f state to 00000000c29bd936 > [ 3.108457] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000228f716d state to 00000000c29bd936 > [ 3.108470] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000005d690c84 state to 00000000c29bd936 > [ 3.108486] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000005d690c84 > [ 3.108499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000c775be6 state to 00000000c29bd936 > [ 3.108513] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000c775be6 > [ 3.108527] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b5f6abf5 state to 00000000c29bd936 > [ 3.108540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 > [ 3.108552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000281af025 state to 00000000c29bd936 > [ 3.108566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000281af025 > [ 3.108578] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053454233 state to 00000000c29bd936 > [ 3.108592] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053454233 > [ 3.108604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000b2cdb294 state to 00000000c29bd936 > [ 3.108616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000555d146c state to 00000000c29bd936 > [ 3.108630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000555d146c > [ 3.108642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007b36813f state to 00000000c29bd936 > [ 3.108655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007b36813f > [ 3.108668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000122a804f > [ 3.108682] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 > [ 3.108695] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eee09833 state to 00000000c29bd936 > [ 3.108709] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [NOCRTC] > [ 3.108722] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eee09833 to [CRTC:51:pipe A] > [ 3.108736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b5f6abf5 > [ 3.108749] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 > [ 3.108761] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000898e3e27 state to 00000000c29bd936 > [ 3.108774] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [NOCRTC] > [ 3.108787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000898e3e27 to [CRTC:72:pipe B] > [ 3.108801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d0e256d1 state to 00000000c29bd936 > [ 3.108814] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d0e256d1 > [ 3.108826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000b2cdb294 > [ 3.108839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 > [ 3.108865] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 > [ 3.108875] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.108882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.108887] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.108892] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.108956] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.109003] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.109025] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 > [ 3.124527] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 > [ 3.124544] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 > [ 3.137517] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a6b51f > [ 3.137531] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000012530223 state to 0000000073a6b51f > [ 3.137543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000009be30044 state to 0000000073a6b51f > [ 3.137555] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000ffe00c37 state to 0000000073a6b51f > [ 3.137567] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000ffe00c37 > [ 3.137577] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000023a9a422 state to 0000000073a6b51f > [ 3.137587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000023a9a422 > [ 3.137598] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000bdb8d82 state to 0000000073a6b51f > [ 3.137607] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e91d807e state to 0000000073a6b51f > [ 3.137617] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e3147659 state to 0000000073a6b51f > [ 3.137627] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e3147659 > [ 3.137636] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000004825b29a state to 0000000073a6b51f > [ 3.137646] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000004825b29a > [ 3.137657] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005788f64c state to 0000000073a6b51f > [ 3.137667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000032e38a43 state to 0000000073a6b51f > [ 3.137676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000032e38a43 > [ 3.137685] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000089408e5f state to 0000000073a6b51f > [ 3.137695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000089408e5f > [ 3.137705] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000012530223 > [ 3.137715] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000073a6b51f > [ 3.137726] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000748c93aa state to 0000000073a6b51f > [ 3.137737] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [NOCRTC] > [ 3.137746] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000748c93aa to [CRTC:51:pipe A] > [ 3.137760] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000bdb8d82 > [ 3.137769] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000073a6b51f > [ 3.137779] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f1b6922b state to 0000000073a6b51f > [ 3.137789] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [NOCRTC] > [ 3.137798] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f1b6922b to [CRTC:72:pipe B] > [ 3.137808] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ad566469 state to 0000000073a6b51f > [ 3.137818] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ad566469 > [ 3.137827] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005788f64c > [ 3.137836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000073a6b51f > [ 3.137846] [drm:drm_atomic_check_only [drm]] checking 0000000073a6b51f > [ 3.137866] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.137872] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.137882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.137886] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.137944] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.137988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.138008] [drm:drm_atomic_commit [drm]] committing 0000000073a6b51f > [ 3.146528] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a6b51f > [ 3.146545] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a6b51f > [ 3.157850] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 > [ 3.157860] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002f4e481a state to 00000000619b20f5 > [ 3.157869] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001b7eae74 state to 00000000619b20f5 > [ 3.157877] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000025544875 state to 00000000619b20f5 > [ 3.157886] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000025544875 > [ 3.157894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008c95634f state to 00000000619b20f5 > [ 3.157902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008c95634f > [ 3.157910] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000483335fe state to 00000000619b20f5 > [ 3.157917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ae874d06 state to 00000000619b20f5 > [ 3.157925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000000fcc975 state to 00000000619b20f5 > [ 3.157932] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000000fcc975 > [ 3.157941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000865de88c state to 00000000619b20f5 > [ 3.157948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000865de88c > [ 3.157955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000001c64fec3 state to 00000000619b20f5 > [ 3.157962] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000001726835f state to 00000000619b20f5 > [ 3.157970] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000001726835f > [ 3.157977] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006011267c state to 00000000619b20f5 > [ 3.157984] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006011267c > [ 3.157993] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002f4e481a > [ 3.158001] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 > [ 3.158009] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000034ee835b state to 00000000619b20f5 > [ 3.158017] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [NOCRTC] > [ 3.158024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000034ee835b to [CRTC:51:pipe A] > [ 3.158031] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000483335fe > [ 3.158039] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 > [ 3.158046] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000b34fddb1 state to 00000000619b20f5 > [ 3.158054] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [NOCRTC] > [ 3.158061] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000b34fddb1 to [CRTC:72:pipe B] > [ 3.158069] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000904bdb49 state to 00000000619b20f5 > [ 3.158076] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000904bdb49 > [ 3.158083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000001c64fec3 > [ 3.158090] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 > [ 3.158098] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 > [ 3.158108] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.158112] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.158116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.158119] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.158180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.158213] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.158229] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 > [ 3.174683] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 > [ 3.174697] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 > [ 3.186485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.186502] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f11c147 state to 00000000f3200e59 > [ 3.186513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7f71e60 state to 00000000f3200e59 > [ 3.186523] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000457aaa57 state to 00000000f3200e59 > [ 3.186534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000457aaa57 > [ 3.186545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b1ca1c71 state to 00000000f3200e59 > [ 3.186555] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b1ca1c71 > [ 3.186565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b4343291 state to 00000000f3200e59 > [ 3.186575] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000f048a61 state to 00000000f3200e59 > [ 3.186584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000067db6375 state to 00000000f3200e59 > [ 3.186594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000067db6375 > [ 3.186604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ed11a5b9 state to 00000000f3200e59 > [ 3.186614] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ed11a5b9 > [ 3.186623] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000df34b7b3 state to 00000000f3200e59 > [ 3.186632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e5b7e29b state to 00000000f3200e59 > [ 3.186641] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e5b7e29b > [ 3.186650] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001c471465 state to 00000000f3200e59 > [ 3.186659] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001c471465 > [ 3.186670] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000005f11c147 > [ 3.186680] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.186690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000140b0238 state to 00000000f3200e59 > [ 3.186704] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [NOCRTC] > [ 3.186714] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000140b0238 to [CRTC:51:pipe A] > [ 3.186723] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b4343291 > [ 3.186733] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.186742] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001ddd4fdd state to 00000000f3200e59 > [ 3.186752] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [NOCRTC] > [ 3.186761] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001ddd4fdd to [CRTC:72:pipe B] > [ 3.186772] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000669bfcd7 state to 00000000f3200e59 > [ 3.186781] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000669bfcd7 > [ 3.186790] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000df34b7b3 > [ 3.186800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.186810] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.186829] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.186834] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.186839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.186844] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.186901] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.186949] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.186968] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.196452] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.196472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.216790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 > [ 3.216813] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000063c0bfb2 state to 00000000ffbe70d8 > [ 3.216833] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf23fbdd state to 00000000ffbe70d8 > [ 3.216851] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000918919b3 state to 00000000ffbe70d8 > [ 3.216872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000918919b3 > [ 3.216889] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000005a00270 state to 00000000ffbe70d8 > [ 3.216907] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000005a00270 > [ 3.216924] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000512c7fb3 state to 00000000ffbe70d8 > [ 3.216940] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000048e8a8c4 state to 00000000ffbe70d8 > [ 3.216956] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000018dbb82d state to 00000000ffbe70d8 > [ 3.216974] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000018dbb82d > [ 3.216990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 > [ 3.217006] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 > [ 3.217023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000a4c468ad state to 00000000ffbe70d8 > [ 3.217038] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000320b468c state to 00000000ffbe70d8 > [ 3.217055] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000320b468c > [ 3.217074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000063ec03c state to 00000000ffbe70d8 > [ 3.217090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000063ec03c > [ 3.217108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000063c0bfb2 > [ 3.217125] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 > [ 3.217143] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d05a5c4c state to 00000000ffbe70d8 > [ 3.217161] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [NOCRTC] > [ 3.217177] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d05a5c4c to [CRTC:51:pipe A] > [ 3.217193] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000512c7fb3 > [ 3.217210] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 > [ 3.217227] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000fc47d714 state to 00000000ffbe70d8 > [ 3.217243] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [NOCRTC] > [ 3.217259] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000fc47d714 to [CRTC:72:pipe B] > [ 3.217276] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 > [ 3.217293] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b > [ 3.217308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000a4c468ad > [ 3.217325] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 > [ 3.217342] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 > [ 3.217360] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.217371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.217382] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.217390] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.217495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.217569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.217604] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 > [ 3.220944] usb 1-12: New USB device found, idVendor=0451, idProduct=8142, bcdDevice= 1.00 > [ 3.220946] usb 1-12: New USB device strings: Mfr=0, Product=0, SerialNumber=1 > [ 3.220948] usb 1-12: SerialNumber: CD0F18513FF2 > [ 3.221863] hub 1-12:1.0: USB hub found > [ 3.221920] hub 1-12:1.0: 4 ports detected > [ 3.229639] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 > [ 3.229666] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 > [ 3.259936] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c29bd936 > [ 3.259967] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007835ad2c state to 00000000c29bd936 > [ 3.259995] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d0e256d1 state to 00000000c29bd936 > [ 3.260020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a0e4907f state to 00000000c29bd936 > [ 3.260049] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a0e4907f > [ 3.260075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c342e8b6 state to 00000000c29bd936 > [ 3.260102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c342e8b6 > [ 3.260127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f85c23ef state to 00000000c29bd936 > [ 3.260151] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000030447c79 state to 00000000c29bd936 > [ 3.260174] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000e025482e state to 00000000c29bd936 > [ 3.260200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000e025482e > [ 3.260224] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000fcc8f6c state to 00000000c29bd936 > [ 3.260249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000000fcc8f6c > [ 3.260275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000093fc8e4 state to 00000000c29bd936 > [ 3.260299] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000005f84ed88 state to 00000000c29bd936 > [ 3.260324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000005f84ed88 > [ 3.260348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000006115325a state to 00000000c29bd936 > [ 3.260373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000006115325a > [ 3.260399] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000007835ad2c > [ 3.260425] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c29bd936 > [ 3.260452] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000093f6ce9d state to 00000000c29bd936 > [ 3.260479] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [NOCRTC] > [ 3.260503] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000093f6ce9d to [CRTC:51:pipe A] > [ 3.260528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f85c23ef > [ 3.260552] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c29bd936 > [ 3.260578] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000074011bcd state to 00000000c29bd936 > [ 3.260602] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [NOCRTC] > [ 3.260626] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000074011bcd to [CRTC:72:pipe B] > [ 3.260651] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000228f716d state to 00000000c29bd936 > [ 3.260677] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000228f716d > [ 3.260700] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000093fc8e4 > [ 3.260725] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c29bd936 > [ 3.260750] [drm:drm_atomic_check_only [drm]] checking 00000000c29bd936 > [ 3.260776] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.260790] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.260802] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.260815] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.260951] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.261061] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.261109] [drm:drm_atomic_commit [drm]] committing 00000000c29bd936 > [ 3.274626] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c29bd936 > [ 3.274674] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c29bd936 > [ 3.299821] usb 1-11.2: new full-speed USB device number 7 using xhci_hcd > [ 3.303479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006379f080 > [ 3.303499] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000559c57fd state to 000000006379f080 > [ 3.303517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e59c9ea1 state to 000000006379f080 > [ 3.303532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000fdc091c8 state to 000000006379f080 > [ 3.303551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000fdc091c8 > [ 3.303572] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a9473c9b state to 000000006379f080 > [ 3.303588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a9473c9b > [ 3.303604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000089408e5f state to 000000006379f080 > [ 3.303618] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008f4ce9b8 state to 000000006379f080 > [ 3.303632] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000032e38a43 state to 000000006379f080 > [ 3.303648] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000032e38a43 > [ 3.303662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005788f64c state to 000000006379f080 > [ 3.303677] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005788f64c > [ 3.303691] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000004825b29a state to 000000006379f080 > [ 3.303705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e3147659 state to 000000006379f080 > [ 3.303720] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e3147659 > [ 3.303734] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000bdb8d82 state to 000000006379f080 > [ 3.303750] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000bdb8d82 > [ 3.303766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000559c57fd > [ 3.303790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006379f080 > [ 3.303807] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000000e02d6ba state to 000000006379f080 > [ 3.303835] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [NOCRTC] > [ 3.303847] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000000e02d6ba to [CRTC:51:pipe A] > [ 3.303860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000089408e5f > [ 3.303872] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006379f080 > [ 3.303886] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000f298f57c state to 000000006379f080 > [ 3.303898] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [NOCRTC] > [ 3.303910] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000f298f57c to [CRTC:72:pipe B] > [ 3.303923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000002aa6a9f8 state to 000000006379f080 > [ 3.303935] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000002aa6a9f8 > [ 3.303947] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000004825b29a > [ 3.303959] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000006379f080 > [ 3.303971] [drm:drm_atomic_check_only [drm]] checking 000000006379f080 > [ 3.304000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.304007] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.304013] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.304019] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.304102] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.304157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.304182] [drm:drm_atomic_commit [drm]] committing 000000006379f080 > [ 3.313100] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006379f080 > [ 3.313118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006379f080 > [ 3.326983] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 > [ 3.326998] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000515dc00f state to 00000000619b20f5 > [ 3.327010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b7f89a8d state to 00000000619b20f5 > [ 3.327021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000008cab647d state to 00000000619b20f5 > [ 3.327036] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000008cab647d > [ 3.327047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009d539ce0 state to 00000000619b20f5 > [ 3.327058] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009d539ce0 > [ 3.327071] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a35c929d state to 00000000619b20f5 > [ 3.327081] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000347fbd12 state to 00000000619b20f5 > [ 3.327091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000046234f6 state to 00000000619b20f5 > [ 3.327102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000046234f6 > [ 3.327112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000053155f00 state to 00000000619b20f5 > [ 3.327122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000053155f00 > [ 3.327132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000f3527d8e state to 00000000619b20f5 > [ 3.327141] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000b538e2a8 state to 00000000619b20f5 > [ 3.327152] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000b538e2a8 > [ 3.327163] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000022fc4ece state to 00000000619b20f5 > [ 3.327173] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000022fc4ece > [ 3.327184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000515dc00f > [ 3.327195] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 > [ 3.327206] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eba32a93 state to 00000000619b20f5 > [ 3.327217] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [NOCRTC] > [ 3.327227] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eba32a93 to [CRTC:51:pipe A] > [ 3.327238] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000a35c929d > [ 3.327248] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 > [ 3.327258] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009b609533 state to 00000000619b20f5 > [ 3.327268] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [NOCRTC] > [ 3.327278] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009b609533 to [CRTC:72:pipe B] > [ 3.327289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 > [ 3.327299] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce > [ 3.327308] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000f3527d8e > [ 3.327318] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 > [ 3.327329] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 > [ 3.327341] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.327346] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.327352] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.327356] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.327430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.327475] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.327501] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 > [ 3.341307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 > [ 3.341359] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 > [ 3.379822] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.379844] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059814b3a state to 00000000f3200e59 > [ 3.379864] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000a48ebd6e state to 00000000f3200e59 > [ 3.379881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000bf357c4b state to 00000000f3200e59 > [ 3.379901] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000bf357c4b > [ 3.379920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000d9e36170 state to 00000000f3200e59 > [ 3.379938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000d9e36170 > [ 3.379955] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000060d5862a state to 00000000f3200e59 > [ 3.379972] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 > [ 3.379988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000071f245df state to 00000000f3200e59 > [ 3.380005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000071f245df > [ 3.380021] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000074f436be state to 00000000f3200e59 > [ 3.380038] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000074f436be > [ 3.380054] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000041c6228e state to 00000000f3200e59 > [ 3.380069] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002938b22d state to 00000000f3200e59 > [ 3.380086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002938b22d > [ 3.380101] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000001f82d691 state to 00000000f3200e59 > [ 3.380117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000001f82d691 > [ 3.380135] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000059814b3a > [ 3.380153] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.380174] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000ce20e5c8 state to 00000000f3200e59 > [ 3.380192] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [NOCRTC] > [ 3.380208] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000ce20e5c8 to [CRTC:51:pipe A] > [ 3.380225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000060d5862a > [ 3.380242] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.380263] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000001b5c4b62 state to 00000000f3200e59 > [ 3.380279] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [NOCRTC] > [ 3.380295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000001b5c4b62 to [CRTC:72:pipe B] > [ 3.380312] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000022f73fd2 state to 00000000f3200e59 > [ 3.380328] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000022f73fd2 > [ 3.380344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000041c6228e > [ 3.380360] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.380376] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.380402] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.380411] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.380419] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.380427] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.380529] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.380604] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.380646] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.396469] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.396503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.410062] usb 1-11.2: New USB device found, idVendor=17ef, idProduct=6047, bcdDevice= 3.00 > [ 3.410064] usb 1-11.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 > [ 3.410065] usb 1-11.2: Product: ThinkPad Compact USB Keyboard with TrackPoint > [ 3.410067] usb 1-11.2: Manufacturer: Lenovo > [ 3.418473] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ffbe70d8 > [ 3.418496] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001090afab state to 00000000ffbe70d8 > [ 3.418515] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000053a23bd6 state to 00000000ffbe70d8 > [ 3.418532] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028cdc562 state to 00000000ffbe70d8 > [ 3.418552] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028cdc562 > [ 3.418574] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000063ec03c state to 00000000ffbe70d8 > [ 3.418593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000063ec03c > [ 3.418610] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000320b468c state to 00000000ffbe70d8 > [ 3.418627] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a4f0e9bc state to 00000000ffbe70d8 > [ 3.418642] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000a4c468ad state to 00000000ffbe70d8 > [ 3.418660] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000a4c468ad > [ 3.418680] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000005179c8b5 state to 00000000ffbe70d8 > [ 3.418697] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000005179c8b5 > [ 3.418713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000018dbb82d state to 00000000ffbe70d8 > [ 3.418728] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000512c7fb3 state to 00000000ffbe70d8 > [ 3.418745] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000512c7fb3 > [ 3.418761] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000005a00270 state to 00000000ffbe70d8 > [ 3.418778] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000005a00270 > [ 3.418800] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001090afab > [ 3.418817] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ffbe70d8 > [ 3.418835] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001175f931 state to 00000000ffbe70d8 > [ 3.418853] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [NOCRTC] > [ 3.418869] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001175f931 to [CRTC:51:pipe A] > [ 3.418888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000320b468c > [ 3.418905] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ffbe70d8 > [ 3.418922] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ebbd72c state to 00000000ffbe70d8 > [ 3.418938] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [NOCRTC] > [ 3.418953] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ebbd72c to [CRTC:72:pipe B] > [ 3.418971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000001775ba6b state to 00000000ffbe70d8 > [ 3.418987] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000001775ba6b > [ 3.419002] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000018dbb82d > [ 3.419018] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ffbe70d8 > [ 3.419035] [drm:drm_atomic_check_only [drm]] checking 00000000ffbe70d8 > [ 3.419053] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.419062] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.419070] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.419078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.419184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.419258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.419291] [drm:drm_atomic_commit [drm]] committing 00000000ffbe70d8 > [ 3.425539] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.0/0003:17EF:6047.0003/input/input6 > [ 3.429543] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ffbe70d8 > [ 3.429570] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ffbe70d8 > [ 3.451015] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.451031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008af22ea7 state to 00000000c6c933d1 > [ 3.451046] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 > [ 3.451060] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 > [ 3.451076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be > [ 3.451089] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002a1c343e state to 00000000c6c933d1 > [ 3.451104] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002a1c343e > [ 3.451117] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f7870136 state to 00000000c6c933d1 > [ 3.451130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 3.451142] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ad384e88 state to 00000000c6c933d1 > [ 3.451156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ad384e88 > [ 3.451172] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008fde4998 state to 00000000c6c933d1 > [ 3.451186] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008fde4998 > [ 3.451198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000071cce0a state to 00000000c6c933d1 > [ 3.451210] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000007ba2cc3a state to 00000000c6c933d1 > [ 3.451223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000007ba2cc3a > [ 3.451236] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac0b8286 state to 00000000c6c933d1 > [ 3.451249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac0b8286 > [ 3.451262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008af22ea7 > [ 3.451280] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.451294] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000eb0da826 state to 00000000c6c933d1 > [ 3.451308] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [NOCRTC] > [ 3.451321] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000eb0da826 to [CRTC:51:pipe A] > [ 3.451334] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f7870136 > [ 3.451347] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.451361] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 > [ 3.451373] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] > [ 3.451386] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] > [ 3.451399] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 > [ 3.451412] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 > [ 3.451425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000071cce0a > [ 3.451438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.451451] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.451465] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.451473] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.451481] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.451487] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.451560] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.451617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.451643] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.463098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.463116] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.478096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000619b20f5 > [ 3.478112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001726835f state to 00000000619b20f5 > [ 3.478125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000be800543 state to 00000000619b20f5 > [ 3.478137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000001c64fec3 state to 00000000619b20f5 > [ 3.478150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000001c64fec3 > [ 3.478162] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000865de88c state to 00000000619b20f5 > [ 3.478174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000865de88c > [ 3.478186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000000fcc975 state to 00000000619b20f5 > [ 3.478197] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000068c99925 state to 00000000619b20f5 > [ 3.478209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000483335fe state to 00000000619b20f5 > [ 3.478220] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000483335fe > [ 3.478231] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000008c95634f state to 00000000619b20f5 > [ 3.478243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000008c95634f > [ 3.478254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 0000000025544875 state to 00000000619b20f5 > [ 3.478264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000002f4e481a state to 00000000619b20f5 > [ 3.478276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000002f4e481a > [ 3.478286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f101de7e state to 00000000619b20f5 > [ 3.478297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f101de7e > [ 3.478309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000001726835f > [ 3.478321] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000619b20f5 > [ 3.478334] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000d41bf332 state to 00000000619b20f5 > [ 3.478346] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [NOCRTC] > [ 3.478357] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000d41bf332 to [CRTC:51:pipe A] > [ 3.478368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000000fcc975 > [ 3.478379] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000619b20f5 > [ 3.478390] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000009e77ee4b state to 00000000619b20f5 > [ 3.478402] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [NOCRTC] > [ 3.478412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000009e77ee4b to [CRTC:72:pipe B] > [ 3.478425] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000004bc31ce state to 00000000619b20f5 > [ 3.478436] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000004bc31ce > [ 3.478446] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 0000000025544875 > [ 3.478457] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000619b20f5 > [ 3.478469] [drm:drm_atomic_check_only [drm]] checking 00000000619b20f5 > [ 3.478482] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.478488] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.478494] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.478500] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.478579] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.478630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.478659] [drm:drm_atomic_commit [drm]] committing 00000000619b20f5 > [ 3.484276] lenovo 0003:17EF:6047.0003: input,hidraw2: USB HID v1.00 Keyboard [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input0 > [ 3.484522] input: Lenovo ThinkPad Compact USB Keyboard with TrackPoint as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.2/1-11.2:1.1/0003:17EF:6047.0004/input/input7 > [ 3.491321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000619b20f5 > [ 3.491337] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000619b20f5 > [ 3.504241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 3.504253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000015cf0577 state to 00000000fc0cb429 > [ 3.504264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000de3ff82c state to 00000000fc0cb429 > [ 3.504273] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000003292b89f state to 00000000fc0cb429 > [ 3.504285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000003292b89f > [ 3.504294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009bdf158a state to 00000000fc0cb429 > [ 3.504305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000009bdf158a > [ 3.504315] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e2798a03 state to 00000000fc0cb429 > [ 3.504324] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 3.504333] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007f2e9b45 state to 00000000fc0cb429 > [ 3.504342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007f2e9b45 > [ 3.504356] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006a25a70b state to 00000000fc0cb429 > [ 3.504366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006a25a70b > [ 3.504375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000005fe5cc2f state to 00000000fc0cb429 > [ 3.504384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000091b367b1 state to 00000000fc0cb429 > [ 3.504393] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000091b367b1 > [ 3.504402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000a6369fc8 state to 00000000fc0cb429 > [ 3.504411] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000a6369fc8 > [ 3.504422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000015cf0577 > [ 3.504431] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 3.504443] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000bd54c871 state to 00000000fc0cb429 > [ 3.504453] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [NOCRTC] > [ 3.504462] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000bd54c871 to [CRTC:51:pipe A] > [ 3.504472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000e2798a03 > [ 3.504481] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 3.504491] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000309bb6f5 state to 00000000fc0cb429 > [ 3.504500] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [NOCRTC] > [ 3.504510] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000309bb6f5 to [CRTC:72:pipe B] > [ 3.504519] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 > [ 3.504529] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 3.504538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000005fe5cc2f > [ 3.504547] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 3.504558] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 3.504571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.504576] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.504581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.504586] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.504640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.504682] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.504701] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 3.513214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 3.513230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 3.527601] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.527620] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002938b22d state to 00000000f3200e59 > [ 3.527632] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000022f73fd2 state to 00000000f3200e59 > [ 3.527643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000041c6228e state to 00000000f3200e59 > [ 3.527656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000041c6228e > [ 3.527667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000074f436be state to 00000000f3200e59 > [ 3.527679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000074f436be > [ 3.527692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000071f245df state to 00000000f3200e59 > [ 3.527705] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006ede65dd state to 00000000f3200e59 > [ 3.527716] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000060d5862a state to 00000000f3200e59 > [ 3.527728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000060d5862a > [ 3.527738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000d9e36170 state to 00000000f3200e59 > [ 3.527749] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000d9e36170 > [ 3.527760] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bf357c4b state to 00000000f3200e59 > [ 3.527776] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000059814b3a state to 00000000f3200e59 > [ 3.527787] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000059814b3a > [ 3.527798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 > [ 3.527809] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd > [ 3.527828] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002938b22d > [ 3.527839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.527850] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000300c269e state to 00000000f3200e59 > [ 3.527862] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [NOCRTC] > [ 3.527873] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000300c269e to [CRTC:51:pipe A] > [ 3.527884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000071f245df > [ 3.527894] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.527907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000000afdf5db state to 00000000f3200e59 > [ 3.527917] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [NOCRTC] > [ 3.527928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000000afdf5db to [CRTC:72:pipe B] > [ 3.527939] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 > [ 3.527949] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e > [ 3.527959] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bf357c4b > [ 3.527970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.527981] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.527993] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.528000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.528005] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.528010] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.528081] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.528130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.528155] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.532011] usb 1-14: new full-speed USB device number 8 using xhci_hcd > [ 3.541291] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.541309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.544126] lenovo 0003:17EF:6047.0004: input,hiddev0,hidraw3: USB HID v1.00 Mouse [Lenovo ThinkPad Compact USB Keyboard with TrackPoint] on usb-0000:00:14.0-11.2/input1 > [ 3.556564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.556581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000023110e55 state to 00000000c6c933d1 > [ 3.556594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005898a128 state to 00000000c6c933d1 > [ 3.556605] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000b9dd800a state to 00000000c6c933d1 > [ 3.556617] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000b9dd800a > [ 3.556628] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000edf72591 state to 00000000c6c933d1 > [ 3.556640] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000edf72591 > [ 3.556651] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009869db1d state to 00000000c6c933d1 > [ 3.556661] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 3.556671] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bd903151 state to 00000000c6c933d1 > [ 3.556682] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bd903151 > [ 3.556692] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c282abaf state to 00000000c6c933d1 > [ 3.556703] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c282abaf > [ 3.556713] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000009f04fd17 state to 00000000c6c933d1 > [ 3.556723] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000c31f7fa4 state to 00000000c6c933d1 > [ 3.556734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000c31f7fa4 > [ 3.556744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000eac50bee state to 00000000c6c933d1 > [ 3.556754] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000eac50bee > [ 3.556766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000023110e55 > [ 3.556777] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.556793] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000dddcb6a7 state to 00000000c6c933d1 > [ 3.556804] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [NOCRTC] > [ 3.556814] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000dddcb6a7 to [CRTC:51:pipe A] > [ 3.556825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009869db1d > [ 3.556836] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.556846] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006978e08c state to 00000000c6c933d1 > [ 3.556857] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [NOCRTC] > [ 3.556867] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006978e08c to [CRTC:72:pipe B] > [ 3.556878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d9533f22 state to 00000000c6c933d1 > [ 3.556889] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d9533f22 > [ 3.556899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000009f04fd17 > [ 3.556909] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.556920] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.556932] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.556938] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.556944] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.556949] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.557021] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.557068] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.557089] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.563101] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.563118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.577479] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f3200e59 > [ 3.577503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003073c677 state to 00000000f3200e59 > [ 3.577514] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000069886caf state to 00000000f3200e59 > [ 3.577525] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000e5892e4f state to 00000000f3200e59 > [ 3.577537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000e5892e4f > [ 3.577548] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c3b3ca94 state to 00000000f3200e59 > [ 3.577559] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c3b3ca94 > [ 3.577570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000015579631 state to 00000000f3200e59 > [ 3.577580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002719d414 state to 00000000f3200e59 > [ 3.577590] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 0000000083fdb4aa state to 00000000f3200e59 > [ 3.577602] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 0000000083fdb4aa > [ 3.577614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000087dc1fd8 state to 00000000f3200e59 > [ 3.577624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000087dc1fd8 > [ 3.577635] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ada87627 state to 00000000f3200e59 > [ 3.577644] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e7bdd2e4 state to 00000000f3200e59 > [ 3.577655] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e7bdd2e4 > [ 3.577666] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f8d239cd state to 00000000f3200e59 > [ 3.577676] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f8d239cd > [ 3.577687] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000003073c677 > [ 3.577698] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f3200e59 > [ 3.577711] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000001ec8650a state to 00000000f3200e59 > [ 3.577725] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [NOCRTC] > [ 3.577735] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000001ec8650a to [CRTC:51:pipe A] > [ 3.577746] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 0000000015579631 > [ 3.577756] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f3200e59 > [ 3.577766] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000939e1171 state to 00000000f3200e59 > [ 3.577777] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [NOCRTC] > [ 3.577787] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000939e1171 to [CRTC:72:pipe B] > [ 3.577798] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a48ebd6e state to 00000000f3200e59 > [ 3.577808] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a48ebd6e > [ 3.577818] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ada87627 > [ 3.577828] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f3200e59 > [ 3.577839] [drm:drm_atomic_check_only [drm]] checking 00000000f3200e59 > [ 3.577852] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.577858] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.577863] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.577868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.577941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.577988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.578009] [drm:drm_atomic_commit [drm]] committing 00000000f3200e59 > [ 3.591295] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f3200e59 > [ 3.591314] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f3200e59 > [ 3.605686] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.605699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000003494222 state to 00000000c6c933d1 > [ 3.605711] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000091ceca83 state to 00000000c6c933d1 > [ 3.605722] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000010343cf4 state to 00000000c6c933d1 > [ 3.605736] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000010343cf4 > [ 3.605747] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000e6ce87e3 state to 00000000c6c933d1 > [ 3.605758] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000e6ce87e3 > [ 3.605769] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac0b8286 state to 00000000c6c933d1 > [ 3.605779] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 3.605789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000007ba2cc3a state to 00000000c6c933d1 > [ 3.605801] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000007ba2cc3a > [ 3.605811] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000071cce0a state to 00000000c6c933d1 > [ 3.605822] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000071cce0a > [ 3.605832] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008fde4998 state to 00000000c6c933d1 > [ 3.605842] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ad384e88 state to 00000000c6c933d1 > [ 3.605852] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ad384e88 > [ 3.605862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000f7870136 state to 00000000c6c933d1 > [ 3.605872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000f7870136 > [ 3.605884] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000003494222 > [ 3.605895] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.605907] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009efdc675 state to 00000000c6c933d1 > [ 3.605918] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [NOCRTC] > [ 3.605928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009efdc675 to [CRTC:51:pipe A] > [ 3.605943] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000ac0b8286 > [ 3.605953] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.605964] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000d5a43570 state to 00000000c6c933d1 > [ 3.605975] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [NOCRTC] > [ 3.605985] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000d5a43570 to [CRTC:72:pipe B] > [ 3.605996] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000473d634f state to 00000000c6c933d1 > [ 3.606007] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000473d634f > [ 3.606016] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008fde4998 > [ 3.606027] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.606038] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.606061] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.606067] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.606072] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.606078] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.606138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.606184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.606205] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.613058] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.613075] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.626981] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.626992] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002a1c343e state to 00000000c6c933d1 > [ 3.627002] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d9533f22 state to 00000000c6c933d1 > [ 3.627011] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000abdcc5be state to 00000000c6c933d1 > [ 3.627022] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000abdcc5be > [ 3.627031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008af22ea7 state to 00000000c6c933d1 > [ 3.627042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008af22ea7 > [ 3.627051] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b777cf9c state to 00000000c6c933d1 > [ 3.627060] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bd109b54 state to 00000000c6c933d1 > [ 3.627074] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000fcdab79b state to 00000000c6c933d1 > [ 3.627083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000fcdab79b > [ 3.627092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000031a1a724 state to 00000000c6c933d1 > [ 3.627102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000031a1a724 > [ 3.627111] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000008f0802a0 state to 00000000c6c933d1 > [ 3.627119] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000098e2986c state to 00000000c6c933d1 > [ 3.627128] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000098e2986c > [ 3.627137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000859ae2da state to 00000000c6c933d1 > [ 3.627146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000859ae2da > [ 3.627156] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000002a1c343e > [ 3.627166] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.627184] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000003d8ac4de state to 00000000c6c933d1 > [ 3.627198] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [NOCRTC] > [ 3.627207] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000003d8ac4de to [CRTC:51:pipe A] > [ 3.627217] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000b777cf9c > [ 3.627226] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.627235] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000006c42b361 state to 00000000c6c933d1 > [ 3.627244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [NOCRTC] > [ 3.627253] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000006c42b361 to [CRTC:72:pipe B] > [ 3.627263] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000005898a128 state to 00000000c6c933d1 > [ 3.627272] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000005898a128 > [ 3.627280] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000008f0802a0 > [ 3.627289] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.627298] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.627309] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.627315] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.627319] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.627324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.627377] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.627418] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.627437] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.641307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.641321] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.641349] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6c933d1 > [ 3.641359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b5c379f5 state to 00000000c6c933d1 > [ 3.641368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000473d634f state to 00000000c6c933d1 > [ 3.641376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000f7870136 state to 00000000c6c933d1 > [ 3.641387] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000f7870136 > [ 3.641396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ad384e88 state to 00000000c6c933d1 > [ 3.641405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ad384e88 > [ 3.641414] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008fde4998 state to 00000000c6c933d1 > [ 3.641422] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000090c926a4 state to 00000000c6c933d1 > [ 3.641430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000071cce0a state to 00000000c6c933d1 > [ 3.641439] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000071cce0a > [ 3.641448] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007ba2cc3a state to 00000000c6c933d1 > [ 3.641457] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007ba2cc3a > [ 3.641465] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000ac0b8286 state to 00000000c6c933d1 > [ 3.641473] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000e6ce87e3 state to 00000000c6c933d1 > [ 3.641482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000e6ce87e3 > [ 3.641490] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000010343cf4 state to 00000000c6c933d1 > [ 3.641498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000010343cf4 > [ 3.641508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000b5c379f5 > [ 3.641517] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000c6c933d1 > [ 3.641530] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000091d2cf4c state to 00000000c6c933d1 > [ 3.641539] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [NOCRTC] > [ 3.641547] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000091d2cf4c to [CRTC:51:pipe A] > [ 3.641556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000008fde4998 > [ 3.641564] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000c6c933d1 > [ 3.641573] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000706e661a state to 00000000c6c933d1 > [ 3.641582] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [NOCRTC] > [ 3.641590] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000706e661a to [CRTC:72:pipe B] > [ 3.641599] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 0000000091ceca83 state to 00000000c6c933d1 > [ 3.641607] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 0000000091ceca83 > [ 3.641615] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000ac0b8286 > [ 3.641624] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000c6c933d1 > [ 3.641634] [drm:drm_atomic_check_only [drm]] checking 00000000c6c933d1 > [ 3.641652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.641657] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.641662] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.641666] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.641717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.641755] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.641773] [drm:drm_atomic_commit [drm]] committing 00000000c6c933d1 > [ 3.657984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6c933d1 > [ 3.658001] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6c933d1 > [ 3.672900] i915 0000:00:02.0: fb1: i915drmfb frame buffer device > [ 3.672952] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] > [ 3.672975] [drm:drm_client_modeset_probe [drm]] > [ 3.672989] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 3.673056] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 3.673077] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 3.673087] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 3.673141] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 3.673439] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.673482] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.674059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.674108] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.674144] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.674179] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 3.676928] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.676971] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 3.677594] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.677624] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.677924] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.677959] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.677966] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 3.677973] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 3.678004] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 3.678433] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.678800] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.680367] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.680395] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.680424] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.680717] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 3.681517] usb 1-14: New USB device found, idVendor=045e, idProduct=028e, bcdDevice= 1.10 > [ 3.681519] usb 1-14: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 3.681521] usb 1-14: Product: TGZ Controller > [ 3.681522] usb 1-14: Manufacturer: D > [ 3.681523] usb 1-14: SerialNumber: 3E5296A0 > [ 3.687203] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.687816] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.687827] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.687847] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.687853] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.688062] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.688070] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.688077] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.688084] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.688090] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688097] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688104] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688110] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688116] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688122] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688129] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.688135] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.688143] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 3.688150] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.688157] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.688163] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.688169] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.688176] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.688182] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.688188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.688195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.688201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.688208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.688214] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.688220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.688227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.688233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.688239] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.688246] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.688252] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.688258] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.688264] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.688271] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.688277] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.688283] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.688290] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.688296] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.688302] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.688309] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.688315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.688321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.688330] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688337] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688344] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688350] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.688357] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.688363] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.688369] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.688375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.688382] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.688386] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 3.688411] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 3.688721] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.688741] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.689059] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.689088] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.689107] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.689125] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 3.691950] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.691968] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 3.692263] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.692279] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.692557] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.692584] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.692588] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 3.692592] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 3.692612] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 3.693013] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.693367] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.694886] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.694906] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.694925] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.695202] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 3.701116] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.701642] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.701650] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.701657] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.701664] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.701855] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.701862] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.701870] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.701877] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.701884] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701891] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701898] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701904] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701911] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701918] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701925] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.701931] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.701938] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 3.701945] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.701952] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.701959] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.701965] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.701972] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.701979] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.701986] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.701992] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.701999] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.702006] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.702013] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.702019] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.702026] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.702033] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.702039] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.702046] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.702053] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.702060] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.702066] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.702073] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.702080] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.702086] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.702093] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.702100] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.702106] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.702113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.702120] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.702127] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.702133] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.702160] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.702167] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.702173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.702180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.702187] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.702191] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 3.702219] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 3.702518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.702538] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.702817] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.702840] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.702858] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.702876] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 3.705524] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.705544] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 3.705839] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.705857] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.706135] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.706154] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.706159] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 3.706163] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 3.706183] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 3.706193] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 3.706203] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no > [ 3.706211] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no > [ 3.706219] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes > [ 3.706226] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no > [ 3.706234] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes > [ 3.706241] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no > [ 3.706248] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no > [ 3.706256] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 3.706264] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 > [ 3.706271] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 > [ 3.706277] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.706284] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 > [ 3.706291] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 > [ 3.706298] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.706304] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config > [ 3.706313] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) > [ 3.706320] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) > [ 3.706338] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 3.706348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000092327a12 state to 00000000fc0cb429 > [ 3.706357] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ca6e974 state to 00000000fc0cb429 > [ 3.706365] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000aea8f107 state to 00000000fc0cb429 > [ 3.706373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000aea8f107 > [ 3.706382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000e4b6e50 state to 00000000fc0cb429 > [ 3.706389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000000e4b6e50 > [ 3.706397] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000098d0b1b state to 00000000fc0cb429 > [ 3.706405] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000374f38f state to 00000000fc0cb429 > [ 3.706413] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000ba689a33 state to 00000000fc0cb429 > [ 3.706420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000ba689a33 > [ 3.706428] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000ae016691 state to 00000000fc0cb429 > [ 3.706435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000ae016691 > [ 3.706443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000002012d358 state to 00000000fc0cb429 > [ 3.706451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000eb42cb6c state to 00000000fc0cb429 > [ 3.706458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000eb42cb6c > [ 3.706466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ac043c4a state to 00000000fc0cb429 > [ 3.706473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ac043c4a > [ 3.706481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000092327a12 > [ 3.706489] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 3.706497] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000005b4f258 state to 00000000fc0cb429 > [ 3.706505] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [NOCRTC] > [ 3.706513] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000005b4f258 to [CRTC:51:pipe A] > [ 3.706520] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000098d0b1b > [ 3.706528] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 3.706536] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000007ee6ef05 state to 00000000fc0cb429 > [ 3.706543] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [NOCRTC] > [ 3.706551] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000007ee6ef05 to [CRTC:72:pipe B] > [ 3.706559] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 000000007ce87400 state to 00000000fc0cb429 > [ 3.706566] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 000000007ce87400 > [ 3.706573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000002012d358 > [ 3.706581] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 3.706589] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 3.706597] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.706601] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.706605] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.706609] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.706636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.706659] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.706675] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 3.713140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 3.713154] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 3.713179] i915 0000:00:02.0: [drm:drm_fb_helper_hotplug_event.part.0 [drm_kms_helper]] > [ 3.713188] [drm:drm_client_modeset_probe [drm]] > [ 3.713202] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 3.713233] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 3.713246] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 3.713251] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 3.713275] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 3.713582] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.713608] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.713894] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 3.713919] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.713941] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.713961] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 3.716582] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 3.716601] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 3.716897] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.716914] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 3.717193] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 3.717219] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.717223] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 3.717228] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 3.717250] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 3.717659] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.718014] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.719533] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.719553] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.719572] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.719697] sr 2:0:0:0: [sr0] scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray > [ 3.719699] cdrom: Uniform CD-ROM driver Revision: 3.20 > [ 3.719853] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 3.725765] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.726292] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.726302] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.726310] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.726317] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.726526] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.726533] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.726540] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.726547] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.726554] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726561] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726574] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726581] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726587] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726594] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.726600] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.726606] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 3.726613] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.726620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.726626] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.726633] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.726639] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.726646] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.726652] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.726659] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.726666] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.726672] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.726679] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.726685] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.726692] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.726698] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.726705] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.726711] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.726718] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.726724] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.726731] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.726737] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.726744] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.726750] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.726757] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.726763] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.726770] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.726776] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.726783] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.726789] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.726796] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726802] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726809] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726815] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.726822] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.726828] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.726835] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.726841] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.726848] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.726852] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 3.726874] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 3.727171] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.727191] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.727470] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 3.727492] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.727511] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.727530] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 3.730191] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 3.730209] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 3.730502] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.730519] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 3.730796] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 3.730814] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.730818] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 3.730822] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 3.730841] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 3.731245] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 3.731600] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 3.733115] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 3.733135] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 3.733153] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 3.733432] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 3.735981] sr 2:0:0:0: Attached scsi CD-ROM sr0 > [ 3.739342] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 3.739867] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.739875] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 3.739883] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 3.739889] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 3.740070] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.740077] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.740085] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 3.740092] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 3.740099] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740106] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740113] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740119] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740133] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740140] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 3.740146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 3.740152] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 3.740159] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 3.740166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 3.740173] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 3.740180] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 3.740186] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 3.740193] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.740200] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 3.740206] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.740213] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 3.740220] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 3.740227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 3.740233] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.740240] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 3.740247] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 3.740254] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 3.740260] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.740267] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 3.740274] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 3.740280] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.740287] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.740294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 3.740301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 3.740307] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 3.740314] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 3.740321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 3.740328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 3.740334] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.740341] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 3.740348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740361] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 3.740375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 3.740381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.740388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.740395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 3.740401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 3.740405] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 3.740428] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 3.740726] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.740746] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.741027] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 3.741049] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.741068] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 3.741086] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 3.743693] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 3.743712] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 3.744007] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.744024] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 3.744301] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 3.744320] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 3.744324] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 3.744328] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 3.744346] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 3.744356] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 3.744365] [drm:drm_client_modeset_probe [drm]] connector 95 enabled? no > [ 3.744373] [drm:drm_client_modeset_probe [drm]] connector 104 enabled? no > [ 3.744380] [drm:drm_client_modeset_probe [drm]] connector 110 enabled? yes > [ 3.744387] [drm:drm_client_modeset_probe [drm]] connector 116 enabled? no > [ 3.744394] [drm:drm_client_modeset_probe [drm]] connector 120 enabled? yes > [ 3.744400] [drm:drm_client_modeset_probe [drm]] connector 126 enabled? no > [ 3.744407] [drm:drm_client_modeset_probe [drm]] connector 130 enabled? no > [ 3.744415] [drm:drm_client_modeset_probe [drm]] Not using firmware configuration > [ 3.744422] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 110 > [ 3.744428] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 110 0 > [ 3.744434] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.744441] [drm:drm_client_modeset_probe [drm]] looking for cmdline mode on connector 120 > [ 3.744447] [drm:drm_client_modeset_probe [drm]] looking for preferred mode on connector 120 0 > [ 3.744453] [drm:drm_client_modeset_probe [drm]] found mode 3840x2160 > [ 3.744460] [drm:drm_client_modeset_probe [drm]] picking CRTCs for 3840x2160 config > [ 3.744468] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 51 (0,0) > [ 3.744475] [drm:drm_client_modeset_probe [drm]] desired mode 3840x2160 set on crtc 72 (0,0) > [ 3.744485] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc0cb429 > [ 3.744494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062abf8d7 state to 00000000fc0cb429 > [ 3.744503] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cf9cfc99 state to 00000000fc0cb429 > [ 3.744510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000059907653 state to 00000000fc0cb429 > [ 3.744518] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000059907653 > [ 3.744526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002b958a81 state to 00000000fc0cb429 > [ 3.744533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002b958a81 > [ 3.744541] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dff2ac2f state to 00000000fc0cb429 > [ 3.744548] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000de3ff82c state to 00000000fc0cb429 > [ 3.744557] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000005ed6e442 state to 00000000fc0cb429 > [ 3.744564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000005ed6e442 > [ 3.744571] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000006d13a46c state to 00000000fc0cb429 > [ 3.744578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000006d13a46c > [ 3.744586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000dc86a4bd state to 00000000fc0cb429 > [ 3.744597] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000002f6b4ed state to 00000000fc0cb429 > [ 3.744604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000002f6b4ed > [ 3.744611] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 0000000009db6fe1 state to 00000000fc0cb429 > [ 3.744618] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 0000000009db6fe1 > [ 3.744626] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 0000000062abf8d7 > [ 3.744633] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000fc0cb429 > [ 3.744641] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009647804d state to 00000000fc0cb429 > [ 3.744648] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [NOCRTC] > [ 3.744656] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009647804d to [CRTC:51:pipe A] > [ 3.744662] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000dff2ac2f > [ 3.744670] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000fc0cb429 > [ 3.744677] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000057c6efeb state to 00000000fc0cb429 > [ 3.744685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [NOCRTC] > [ 3.744692] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000057c6efeb to [CRTC:72:pipe B] > [ 3.744706] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000422ac28a state to 00000000fc0cb429 > [ 3.744713] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000422ac28a > [ 3.744719] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000dc86a4bd > [ 3.744727] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000fc0cb429 > [ 3.744734] [drm:drm_atomic_check_only [drm]] checking 00000000fc0cb429 > [ 3.744741] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 3.744746] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 3.744749] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 3.744753] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 3.744786] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.744808] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 3.744823] [drm:drm_atomic_commit [drm]] committing 00000000fc0cb429 > [ 3.757962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc0cb429 > [ 3.758007] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc0cb429 > [ 3.760005] usb 1-11.3: new full-speed USB device number 9 using xhci_hcd > [ 3.863221] usb 1-11.3: New USB device found, idVendor=056a, idProduct=0392, bcdDevice= 1.07 > [ 3.863226] usb 1-11.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 3.863230] usb 1-11.3: Product: Wacom Intuos Pro S > [ 3.863232] usb 1-11.3: Manufacturer: Wacom Co.,Ltd. > [ 3.863235] usb 1-11.3: SerialNumber: 9IQ0111006826 > [ 3.875163] hid-generic 0003:056A:0392.0005: hiddev1,hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 > [ 3.878106] hid-generic 0003:056A:0392.0006: hiddev2,hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 > [ 3.901638] input: Wacom Intuos Pro S Pen as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input8 > [ 3.901775] input: Wacom Intuos Pro S Pad as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.0/0003:056A:0392.0005/input/input10 > [ 3.901851] wacom 0003:056A:0392.0005: hidraw4: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input0 > [ 3.902858] input: Wacom Intuos Pro S Finger as /devices/pci0000:00/0000:00:14.0/usb1/1-11/1-11.3/1-11.3:1.1/0003:056A:0392.0006/input/input12 > [ 3.902979] wacom 0003:056A:0392.0006: hidraw5: USB HID v1.10 Device [Wacom Co.,Ltd. Wacom Intuos Pro S] on usb-0000:00:14.0-11.3/input1 > [ 3.943873] usb 1-12.1: new high-speed USB device number 10 using xhci_hcd > [ 4.045574] usb 1-12.1: New USB device found, idVendor=16d0, idProduct=071a, bcdDevice= 1.96 > [ 4.045583] usb 1-12.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 4.045586] usb 1-12.1: Product: Combo384 Amanero > [ 4.045589] usb 1-12.1: Manufacturer: Amanero Technologies > [ 4.045592] usb 1-12.1: SerialNumber: 413-001 > [ 4.136728] process '/usr/bin/fstype' started with executable stack > [ 4.149281] PM: Image not found (code -22) > [ 4.267305] SGI XFS with ACLs, security attributes, realtime, quota, no debug enabled > [ 4.270230] XFS (sda1): Mounting V5 Filesystem > [ 4.283488] XFS (sda1): Ending clean mount > [ 4.381935] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist. > [ 4.466746] systemd[1]: Inserted module 'autofs4' > [ 4.493716] systemd[1]: systemd 245.5-3 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=hybrid) > [ 4.512168] systemd[1]: Detected architecture x86-64. > [ 4.541853] systemd[1]: Set hostname to <hirez>. > [ 4.676468] systemd[1]: /lib/systemd/system/dbus.socket:5: ListenStream= references a path below legacy directory /var/run/, updating /var/run/dbus/system_bus_socket ? /run/dbus/system_bus_socket; please update the unit file accordingly. > [ 4.732617] systemd[1]: Created slice system-getty.slice. > [ 4.732826] systemd[1]: Created slice system-modprobe.slice. > [ 4.733006] systemd[1]: Created slice system-postfix.slice. > [ 4.733241] systemd[1]: Created slice User and Session Slice. > [ 4.733308] systemd[1]: Started Forward Password Requests to Wall Directory Watch. > [ 4.733466] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. > [ 4.733508] systemd[1]: Reached target User and Group Name Lookups. > [ 4.733523] systemd[1]: Reached target Slices. > [ 4.736775] systemd[1]: Listening on RPCbind Server Activation Socket. > [ 4.737370] systemd[1]: Listening on Syslog Socket. > [ 4.737434] systemd[1]: Listening on initctl Compatibility Named Pipe. > [ 4.737838] systemd[1]: Listening on Journal Audit Socket. > [ 4.737907] systemd[1]: Listening on Journal Socket (/dev/log). > [ 4.737992] systemd[1]: Listening on Journal Socket. > [ 4.738085] systemd[1]: Listening on udev Control Socket. > [ 4.738133] systemd[1]: Listening on udev Kernel Socket. > [ 4.738771] systemd[1]: Mounting Huge Pages File System... > [ 4.739449] systemd[1]: Mounting POSIX Message Queue File System... > [ 4.740120] systemd[1]: Mounting RPC Pipe File System... > [ 4.741130] systemd[1]: Mounting Kernel Debug File System... > [ 4.742089] systemd[1]: Mounting Kernel Trace File System... > [ 4.742177] systemd[1]: Condition check resulted in Kernel Module supporting RPCSEC_GSS being skipped. > [ 4.743057] systemd[1]: Starting Wait for network to be configured by ifupdown... > [ 4.744088] systemd[1]: Starting Set the console keyboard layout... > [ 4.744753] systemd[1]: Starting Create list of static device nodes for the current kernel... > [ 4.744784] systemd[1]: Condition check resulted in Load Kernel Module drm being skipped. > [ 4.745130] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped. > [ 4.746296] systemd[1]: Starting Journal Service... > [ 4.748422] systemd[1]: Starting Load Kernel Modules... > [ 4.749115] systemd[1]: Starting Remount Root and Kernel File Systems... > [ 4.749944] systemd[1]: Starting udev Coldplug all Devices... > [ 4.751645] systemd[1]: Mounted Huge Pages File System. > [ 4.751832] systemd[1]: Mounted POSIX Message Queue File System. > [ 4.751979] systemd[1]: Mounted Kernel Debug File System. > [ 4.752111] systemd[1]: Mounted Kernel Trace File System. > [ 4.752618] systemd[1]: Finished Wait for network to be configured by ifupdown. > [ 4.753157] systemd[1]: Finished Create list of static device nodes for the current kernel. > [ 4.761518] lp: driver loaded but no devices found > [ 4.763837] ppdev: user-space parallel port driver > [ 4.771880] systemd[1]: Finished Load Kernel Modules. > [ 4.772256] systemd[1]: Condition check resulted in FUSE Control File System being skipped. > [ 4.772353] systemd[1]: Condition check resulted in Kernel Configuration File System being skipped. > [ 4.772373] xfs filesystem being remounted at / supports timestamps until 2038 (0x7fffffff) > [ 4.773269] systemd[1]: Starting Apply Kernel Variables... > [ 4.773401] RPC: Registered named UNIX socket transport module. > [ 4.773402] RPC: Registered udp transport module. > [ 4.773402] RPC: Registered tcp transport module. > [ 4.773403] RPC: Registered tcp NFSv4.1 backchannel transport module. > [ 4.775228] systemd[1]: Mounted RPC Pipe File System. > [ 4.775747] systemd[1]: Finished Remount Root and Kernel File Systems. > [ 4.776247] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped. > [ 4.776285] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped. > [ 4.777070] systemd[1]: Starting Load/Save Random Seed... > [ 4.777955] systemd[1]: Starting Create System Users... > [ 4.780674] systemd[1]: Finished Apply Kernel Variables. > [ 4.793614] systemd[1]: Finished Load/Save Random Seed. > [ 4.796908] systemd[1]: Finished Create System Users. > [ 4.797598] systemd[1]: Starting Create Static Device Nodes in /dev... > [ 4.802675] systemd[1]: Finished Set the console keyboard layout. > [ 4.808929] systemd[1]: Finished Create Static Device Nodes in /dev. > [ 4.809034] systemd[1]: Reached target Local File Systems (Pre). > [ 4.809044] systemd[1]: Reached target Local File Systems. > [ 4.809658] systemd[1]: Starting Load AppArmor profiles... > [ 4.810278] systemd[1]: Starting Enable support for additional executable binary formats... > [ 4.811095] systemd[1]: Starting Set console font and keymap... > [ 4.811940] systemd[1]: Starting Preprocess NFS configuration... > [ 4.812829] systemd[1]: Starting Tell Plymouth To Write Out Runtime Data... > [ 4.812857] systemd[1]: Condition check resulted in Store a System Token in an EFI Variable being skipped. > [ 4.812897] systemd[1]: Condition check resulted in Commit a transient machine-id on disk being skipped. > [ 4.813667] systemd[1]: Starting udev Kernel Device Manager... > [ 4.813843] systemd[1]: proc-sys-fs-binfmt_misc.automount: Got automount request for /proc/sys/fs/binfmt_misc, triggered by 350 (update-binfmts) > [ 4.814689] systemd[1]: Mounting Arbitrary Executable File Formats File System... > [ 4.815333] systemd[1]: Finished Set console font and keymap. > [ 4.815579] systemd[1]: nfs-config.service: Succeeded. > [ 4.815929] systemd[1]: Finished Preprocess NFS configuration. > [ 4.816074] systemd[1]: Condition check resulted in RPC security service for NFS client and server being skipped. > [ 4.816102] systemd[1]: Condition check resulted in RPC security service for NFS server being skipped. > [ 4.816118] systemd[1]: Reached target NFS client services. > [ 4.820384] systemd[1]: Mounted Arbitrary Executable File Formats File System. > [ 4.824947] systemd[1]: Finished Enable support for additional executable binary formats. > [ 4.825708] systemd[1]: Received SIGRTMIN+20 from PID 243 (plymouthd). > [ 4.828330] systemd[1]: Finished Tell Plymouth To Write Out Runtime Data. > [ 4.840263] audit: type=1400 audit(1591264850.416:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="firejail-default" pid=368 comm="apparmor_parser" > [ 4.840263] systemd[1]: Finished udev Coldplug all Devices. > [ 4.841296] systemd[1]: Starting Helper to synchronize boot up for ifupdown... > [ 4.841705] audit: type=1400 audit(1591264850.416:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-senddoc" pid=372 comm="apparmor_parser" > [ 4.843324] audit: type=1400 audit(1591264850.416:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="postgresql_akonadi" pid=370 comm="apparmor_parser" > [ 4.843644] audit: type=1400 audit(1591264850.416:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-oopslash" pid=371 comm="apparmor_parser" > [ 4.843772] systemd[1]: Finished Helper to synchronize boot up for ifupdown. > [ 4.843977] audit: type=1400 audit(1591264850.420:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=369 comm="apparmor_parser" > [ 4.843989] audit: type=1400 audit(1591264850.420:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=369 comm="apparmor_parser" > [ 4.843990] audit: type=1400 audit(1591264850.420:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=369 comm="apparmor_parser" > [ 4.844372] audit: type=1400 audit(1591264850.420:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="libreoffice-xpdfimport" pid=375 comm="apparmor_parser" > [ 4.845764] audit: type=1400 audit(1591264850.420:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cups-browsed" pid=365 comm="apparmor_parser" > [ 4.911836] systemd[1]: Finished Load AppArmor profiles. > [ 4.912675] systemd[1]: Starting Raise network interfaces... > [ 4.952184] systemd[1]: Finished Raise network interfaces. > [ 4.954977] systemd[1]: Started udev Kernel Device Manager. > [ 4.955663] systemd[1]: Starting Show Plymouth Boot Screen... > [ 4.981642] systemd[1]: Started Show Plymouth Boot Screen. > [ 4.981868] systemd[1]: Condition check resulted in Dispatch Password Requests to Console Directory Watch being skipped. > [ 4.981983] systemd[1]: Started Forward Password Requests to Plymouth Directory Watch. > [ 4.982014] systemd[1]: Reached target Local Encrypted Volumes. > [ 5.003794] IPMI message handler: version 39.2 > [ 5.007344] ipmi device interface > [ 5.014857] ipmi_si: IPMI System Interface driver > [ 5.014872] ipmi_si dmi-ipmi-si.0: ipmi_platform: probing via SMBIOS > [ 5.014874] ipmi_platform: ipmi_si: SMBIOS: io 0xca2 regsize 1 spacing 1 irq 0 > [ 5.014875] ipmi_si: Adding SMBIOS-specified kcs state machine > [ 5.015655] ipmi_si IPI0001:00: ipmi_platform: probing via ACPI > [ 5.015806] ipmi_si IPI0001:00: ipmi_platform: [io 0x0ca4] regsize 1 spacing 1 irq 0 > [ 5.015807] ipmi_si: Adding ACPI-specified kcs state machine > [ 5.015884] ipmi_si: Trying SMBIOS-specified kcs state machine at i/o address 0xca2, slave address 0x20, irq 0 > [ 5.088154] EDAC MC0: Giving out device to module ie31200_edac controller IE31200: DEV 0000:00:00.0 (POLLED) > [ 5.089876] sd 1:0:0:0: Attached scsi generic sg0 type 0 > [ 5.090024] sr 2:0:0:0: Attached scsi generic sg1 type 5 > [ 5.090192] sd 4:0:0:0: Attached scsi generic sg2 type 0 > [ 5.090241] sd 4:0:0:1: Attached scsi generic sg3 type 0 > [ 5.090266] sd 4:0:0:2: Attached scsi generic sg4 type 0 > [ 5.090320] sd 4:0:0:3: Attached scsi generic sg5 type 0 > [ 5.090373] sd 4:0:0:4: Attached scsi generic sg6 type 0 > [ 5.091437] iTCO_vendor_support: vendor-support=0 > [ 5.092650] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11 > [ 5.092707] mei_me 0000:00:16.0: enabling device (0000 -> 0002) > [ 5.092778] input: Microsoft X-Box 360 pad as /devices/pci0000:00/0000:00:14.0/usb1/1-14/1-14:1.0/input/input14 > [ 5.092783] iTCO_wdt: unable to reset NO_REBOOT flag, device disabled by hardware/BIOS > [ 5.092866] usbcore: registered new interface driver xpad > [ 5.116588] mc: Linux media interface: v0.10 > [ 5.141208] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer > [ 5.141209] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules > [ 5.141210] RAPL PMU: hw unit of domain package 2^-14 Joules > [ 5.141211] RAPL PMU: hw unit of domain dram 2^-14 Joules > [ 5.141211] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules > [ 5.150008] systemd[1]: Found device Samsung_SSD_850_PRO_512GB 5. > [ 5.159157] systemd[1]: Activating swap /dev/disk/by-uuid/602df9e6-40fb-41aa-b0df-96a9088df593... > [ 5.186454] systemd[1]: Started Journal Service. > [ 5.189868] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) > [ 5.192407] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. > [ 5.192408] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 2, val = -32767/0/1 > [ 5.193209] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ef6f2003 > [ 5.193220] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ea16da3d state to 00000000ef6f2003 > [ 5.193230] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000088487cf7 state to 00000000ef6f2003 > [ 5.193238] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000028b01bfa state to 00000000ef6f2003 > [ 5.193247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000028b01bfa > [ 5.193255] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000008a2f3e8a state to 00000000ef6f2003 > [ 5.193264] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000008a2f3e8a > [ 5.193294] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000eb2a745f state to 00000000ef6f2003 > [ 5.193315] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000faa616df state to 00000000ef6f2003 > [ 5.193324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cbb299c1 state to 00000000ef6f2003 > [ 5.193332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cbb299c1 > [ 5.193353] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000079bcaa7c state to 00000000ef6f2003 > [ 5.193361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000079bcaa7c > [ 5.193369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000fb71ed5 state to 00000000ef6f2003 > [ 5.193376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000a9cfd0f1 state to 00000000ef6f2003 > [ 5.193384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000a9cfd0f1 > [ 5.193393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000007908e825 state to 00000000ef6f2003 > [ 5.193401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000007908e825 > [ 5.193414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000ea16da3d > [ 5.193422] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000ef6f2003 > [ 5.193431] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000018b0a306 state to 00000000ef6f2003 > [ 5.193440] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [NOCRTC] > [ 5.193447] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000018b0a306 to [CRTC:51:pipe A] > [ 5.193463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000eb2a745f > [ 5.193472] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000ef6f2003 > [ 5.193481] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 000000008dfecd46 state to 00000000ef6f2003 > [ 5.193488] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [NOCRTC] > [ 5.193496] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 000000008dfecd46 to [CRTC:72:pipe B] > [ 5.193507] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000fd253e01 state to 00000000ef6f2003 > [ 5.193515] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000fd253e01 > [ 5.193522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000fb71ed5 > [ 5.193530] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000ef6f2003 > [ 5.193538] [drm:drm_atomic_check_only [drm]] checking 00000000ef6f2003 > [ 5.193549] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 5.193553] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 5.193557] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 5.193561] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 5.193595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.193618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.193635] [drm:drm_atomic_commit [drm]] committing 00000000ef6f2003 > [ 5.196839] cryptd: max_cpu_qlen set to 1000 > [ 5.196865] usb 1-12.1: Warning! Unlikely big volume range (=32767), cval->res is probably wrong. > [ 5.196867] usb 1-12.1: [10] FU [PCM Playback Volume] ch = 1, val = -32767/0/1 > [ 5.197058] usbcore: registered new interface driver snd-usb-audio > [ 5.208924] Adding 33442812k swap on /dev/sda5. Priority:-2 extents:1 across:33442812k SSFS > [ 5.209024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ef6f2003 > [ 5.209049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ef6f2003 > [ 5.214980] systemd-journald[324]: Received client request to flush runtime journal. > [ 5.232082] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9f8f61b > [ 5.232093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d30af224 state to 00000000f9f8f61b > [ 5.232103] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 00000000f9f8f61b > [ 5.232112] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000a3a0e390 state to 00000000f9f8f61b > [ 5.232121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000a3a0e390 > [ 5.232129] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000050c6aee state to 00000000f9f8f61b > [ 5.232138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000050c6aee > [ 5.232151] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000330ef6e state to 00000000f9f8f61b > [ 5.232159] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a16f6bc3 state to 00000000f9f8f61b > [ 5.232166] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000bb4d02e2 state to 00000000f9f8f61b > [ 5.232174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000bb4d02e2 > [ 5.232182] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000a99d3259 state to 00000000f9f8f61b > [ 5.232192] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000a99d3259 > [ 5.232200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000c8e13b43 state to 00000000f9f8f61b > [ 5.232207] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 00000000ece028f4 state to 00000000f9f8f61b > [ 5.232215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 00000000ece028f4 > [ 5.232222] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000000c21cbeb state to 00000000f9f8f61b > [ 5.232232] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000000c21cbeb > [ 5.232240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000d30af224 > [ 5.232250] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 00000000f9f8f61b > [ 5.232264] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000004431baab state to 00000000f9f8f61b > [ 5.232274] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [NOCRTC] > [ 5.232282] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000004431baab to [CRTC:51:pipe A] > [ 5.232289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000000330ef6e > [ 5.232297] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 00000000f9f8f61b > [ 5.232305] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000641aa27e state to 00000000f9f8f61b > [ 5.232314] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [NOCRTC] > [ 5.232322] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000641aa27e to [CRTC:72:pipe B] > [ 5.232331] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000e1c94e20 state to 00000000f9f8f61b > [ 5.232338] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000e1c94e20 > [ 5.232345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000c8e13b43 > [ 5.232353] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 00000000f9f8f61b > [ 5.232362] [drm:drm_atomic_check_only [drm]] checking 00000000f9f8f61b > [ 5.232373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 5.232377] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 5.232381] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 5.232385] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 5.232421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.232445] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 5.232472] [drm:drm_atomic_commit [drm]] committing 00000000f9f8f61b > [ 5.246294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9f8f61b > [ 5.246308] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9f8f61b > [ 5.268023] AVX2 version of gcm_enc/dec engaged. > [ 5.268024] AES CTR mode by8 optimization enabled > [ 5.278985] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC888-VD: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:line > [ 5.278986] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) > [ 5.278987] snd_hda_codec_realtek hdaudioC0D0: hp_outs=0 (0x0/0x0/0x0/0x0/0x0) > [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 > [ 5.278988] snd_hda_codec_realtek hdaudioC0D0: inputs: > [ 5.278989] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 > [ 5.293862] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 5.293885] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 5.293906] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 5.293928] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 5.293948] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 5.293970] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 5.293988] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 5.295775] ipmi_si dmi-ipmi-si.0: The BMC does not support clearing the recv irq bit, compensating, but the BMC needs to be fixed. > [ 5.312401] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1f.3/sound/card0/input15 > [ 5.312465] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input16 > [ 5.312514] input: HDA Intel PCH Front Line Out as /devices/pci0000:00/0000:00:1f.3/sound/card0/input17 > [ 5.312560] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input18 > [ 5.312604] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input19 > [ 5.312651] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input20 > [ 5.312690] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input21 > [ 5.312737] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input22 > [ 5.388997] ipmi_si dmi-ipmi-si.0: IPMI message handler: Found new BMC (man_id: 0x002a7c, prod_id: 0x0888, dev_id: 0x20) > [ 5.430745] ipmi_si dmi-ipmi-si.0: IPMI kcs interface initialized > [ 5.442072] ipmi_ssif: IPMI SSIF Interface driver > [ 5.690895] intel_rapl_common: Found RAPL domain package > [ 5.690897] intel_rapl_common: Found RAPL domain core > [ 5.690899] intel_rapl_common: Found RAPL domain uncore > [ 5.690900] intel_rapl_common: Found RAPL domain dram > [ 6.053475] alg: No test for fips(ansi_cprng) (fips_ansi_cprng) > [ 6.145869] Bluetooth: Core ver 2.22 > [ 6.145879] NET: Registered protocol family 31 > [ 6.145880] Bluetooth: HCI device and connection manager initialized > [ 6.145883] Bluetooth: HCI socket layer initialized > [ 6.145884] Bluetooth: L2CAP socket layer initialized > [ 6.145886] Bluetooth: SCO socket layer initialized > [ 6.256918] kauditd_printk_skb: 16 callbacks suppressed > [ 6.256919] audit: type=1400 audit(1591264851.832:27): apparmor="DENIED" operation="capable" profile="/usr/sbin/cups-browsed" pid=724 comm="cups-browsed" capability=23 capname="sys_nice" > [ 10.310500] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx > [ 10.310581] IPv6: ADDRCONF(NETDEV_CHANGE): eno1: link becomes ready > [ 14.126521] e1000e 0000:00:1f.6 eno1: NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx > [ 14.914834] FS-Cache: Loaded > [ 14.953494] FS-Cache: Netfs 'nfs' registered for caching > [ 14.956761] Key type dns_resolver registered > [ 15.082476] NFS: Registering the id_resolver key type > [ 15.082496] Key type id_resolver registered > [ 15.082497] Key type id_legacy registered > [ 15.296934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d166d111 > [ 15.296974] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008bf5b86d state to 00000000d166d111 > [ 15.297001] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 00000000bd8bd551 state to 00000000d166d111 > [ 15.297024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 00000000835fb348 state to 00000000d166d111 > [ 15.297051] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 00000000835fb348 > [ 15.297077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008bf5b86d > [ 15.297103] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 00000000d166d111 > [ 15.297127] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 00000000f4bb3954 state to 00000000d166d111 > [ 15.297151] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [NOCRTC] > [ 15.297173] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 00000000f4bb3954 to [CRTC:33:crtc-0] > [ 15.297196] [drm:drm_atomic_check_only [drm]] checking 00000000d166d111 > [ 15.297215] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 15.297228] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 15.297255] [drm:drm_atomic_commit [drm]] committing 00000000d166d111 > [ 15.297321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d166d111 > [ 15.297345] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d166d111 > [ 15.297375] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 > [ 15.297451] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004b92744e > [ 15.297477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 000000004b92744e > [ 15.297500] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed9cb119 state to 000000004b92744e > [ 15.297522] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 00000000046234f6 state to 000000004b92744e > [ 15.297547] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 00000000046234f6 > [ 15.297570] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a35c929d state to 000000004b92744e > [ 15.297594] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000a35c929d > [ 15.297618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009d539ce0 state to 000000004b92744e > [ 15.297640] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed29f6c9 state to 000000004b92744e > [ 15.297662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000515dc00f state to 000000004b92744e > [ 15.297685] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000515dc00f > [ 15.297707] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000483335fe state to 000000004b92744e > [ 15.297730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000483335fe > [ 15.297753] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 000000000e89c017 state to 000000004b92744e > [ 15.297774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000029001d73 state to 000000004b92744e > [ 15.297797] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000029001d73 > [ 15.297820] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000708b01e5 state to 000000004b92744e > [ 15.297853] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000708b01e5 > [ 15.297871] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 00000000f3527d8e > [ 15.297888] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000004b92744e > [ 15.297908] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 00000000efae517b state to 000000004b92744e > [ 15.297927] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [NOCRTC] > [ 15.297944] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 00000000efae517b to [CRTC:51:pipe A] > [ 15.297961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000009d539ce0 > [ 15.297978] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000004b92744e > [ 15.297996] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000033858fd0 state to 000000004b92744e > [ 15.298013] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [NOCRTC] > [ 15.298030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000033858fd0 to [CRTC:72:pipe B] > [ 15.298048] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000d397071c state to 000000004b92744e > [ 15.298065] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000d397071c > [ 15.298081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 000000000e89c017 > [ 15.298098] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 000000004b92744e > [ 15.298115] [drm:drm_atomic_check_only [drm]] checking 000000004b92744e > [ 15.298143] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 15.298153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 15.298161] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 15.298170] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 15.298248] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.298299] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.298333] [drm:drm_atomic_commit [drm]] committing 000000004b92744e > [ 15.313540] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004b92744e > [ 15.313557] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004b92744e > [ 15.330791] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 > [ 15.330803] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008c95634f state to 0000000033ce3db8 > [ 15.330813] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000008fdc242 state to 0000000033ce3db8 > [ 15.330826] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 0000000024c9c604 state to 0000000033ce3db8 > [ 15.330836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 0000000024c9c604 > [ 15.330845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000063a0901f state to 0000000033ce3db8 > [ 15.330854] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000063a0901f > [ 15.330862] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f9f236ad state to 0000000033ce3db8 > [ 15.330870] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e1c94e20 state to 0000000033ce3db8 > [ 15.330879] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 000000001976c542 state to 0000000033ce3db8 > [ 15.330887] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 000000001976c542 > [ 15.330895] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000023bce10 state to 0000000033ce3db8 > [ 15.330903] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000023bce10 > [ 15.330912] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000d3ee8271 state to 0000000033ce3db8 > [ 15.330919] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 0000000026db81c9 state to 0000000033ce3db8 > [ 15.330927] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 0000000026db81c9 > [ 15.330940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 000000003685cc7f state to 0000000033ce3db8 > [ 15.330948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 000000003685cc7f > [ 15.330956] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008c95634f > [ 15.330965] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 > [ 15.330974] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 000000009eadb78e state to 0000000033ce3db8 > [ 15.330982] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [NOCRTC] > [ 15.330990] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 000000009eadb78e to [CRTC:51:pipe A] > [ 15.330998] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 00000000f9f236ad > [ 15.331006] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 > [ 15.331014] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000ef54c858 state to 0000000033ce3db8 > [ 15.331022] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [NOCRTC] > [ 15.331030] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000ef54c858 to [CRTC:72:pipe B] > [ 15.331049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000a16f6bc3 state to 0000000033ce3db8 > [ 15.331057] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000a16f6bc3 > [ 15.331064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000d3ee8271 > [ 15.331072] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 > [ 15.331080] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 > [ 15.331092] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 15.331096] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 15.331100] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 15.331104] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 15.331140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.331173] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.331191] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 > [ 15.346869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 > [ 15.346883] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 > [ 15.347242] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009bf2742d > [ 15.347253] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane-0] 000000008c267a81 state to 000000009bf2742d > [ 15.347264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:33:crtc-0] 0000000042ba191e state to 000000009bf2742d > [ 15.347275] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:32:plane-1] 0000000050ba9058 state to 000000009bf2742d > [ 15.347285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:32:plane-1] state 0000000050ba9058 > [ 15.347294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:36] for [PLANE:31:plane-0] state 000000008c267a81 > [ 15.347303] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:33:crtc-0] to 000000009bf2742d > [ 15.347311] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:35:VGA-1] 000000002bd5700a state to 000000009bf2742d > [ 15.347320] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [NOCRTC] > [ 15.347328] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:35:VGA-1] state 000000002bd5700a to [CRTC:33:crtc-0] > [ 15.347337] [drm:drm_atomic_check_only [drm]] checking 000000009bf2742d > [ 15.347344] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:35:VGA-1] > [ 15.347349] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:35:VGA-1] keeps [ENCODER:34:DAC-34], now on [CRTC:33:crtc-0] > [ 15.347359] [drm:drm_atomic_commit [drm]] committing 000000009bf2742d > [ 15.347396] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009bf2742d > [ 15.347405] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009bf2742d > [ 15.347415] ast 0000:06:00.0: [drm:drm_client_dev_restore [drm]] fbdev: ret=0 > [ 15.358909] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 > [ 15.358920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f6bb1f5 state to 0000000033ce3db8 > [ 15.358931] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c7e04220 state to 0000000033ce3db8 > [ 15.358939] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:39:plane 2A] 000000002749498f state to 0000000033ce3db8 > [ 15.358949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:39:plane 2A] state 000000002749498f > [ 15.358961] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000006153d5d9 state to 0000000033ce3db8 > [ 15.358980] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000006153d5d9 > [ 15.358996] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006a05b5f7 state to 0000000033ce3db8 > [ 15.359012] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d397071c state to 0000000033ce3db8 > [ 15.359027] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:plane 2B] 00000000cca4b9f0 state to 0000000033ce3db8 > [ 15.359042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:plane 2B] state 00000000cca4b9f0 > [ 15.359058] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000009e05e90a state to 0000000033ce3db8 > [ 15.359072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000009e05e90a > [ 15.359091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:73:plane 1C] 00000000bc644261 state to 0000000033ce3db8 > [ 15.359109] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:81:plane 2C] 000000000e16ac42 state to 0000000033ce3db8 > [ 15.359124] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:81:plane 2C] state 000000000e16ac42 > [ 15.359140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000ed4faf45 state to 0000000033ce3db8 > [ 15.359155] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000ed4faf45 > [ 15.359171] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:31:plane 1A] state 000000008f6bb1f5 > [ 15.359186] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 > [ 15.359203] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000025aaf842 state to 0000000033ce3db8 > [ 15.359223] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [NOCRTC] > [ 15.359238] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000025aaf842 to [CRTC:51:pipe A] > [ 15.359254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:136] for [PLANE:52:plane 1B] state 000000006a05b5f7 > [ 15.359270] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 0000000033ce3db8 > [ 15.359285] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000a470917a state to 0000000033ce3db8 > [ 15.359302] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [NOCRTC] > [ 15.359323] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000a470917a to [CRTC:72:pipe B] > [ 15.359340] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:93:pipe C] 00000000ed29f6c9 state to 0000000033ce3db8 > [ 15.359358] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:93:pipe C] state 00000000ed29f6c9 > [ 15.359372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:73:plane 1C] state 00000000bc644261 > [ 15.359388] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:93:pipe C] to 0000000033ce3db8 > [ 15.359403] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 > [ 15.359433] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 15.359441] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 15.359449] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 15.359456] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 15.359505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.359557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 15.359583] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 > [ 15.375008] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 > [ 15.375022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 > [ 15.405098] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.405480] [drm:intel_framebuffer_init [i915]] No Y tiling for legacy addfb > [ 15.405515] [drm:drm_internal_framebuffer_create [drm]] could not create framebuffer > [ 15.405547] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.405606] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.405820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 > [ 15.405829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000053cd4a56 state to 00000000403c96a5 > [ 15.405838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000053cd4a56 > [ 15.405847] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 > [ 15.405873] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 > [ 15.405892] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 > [ 15.405899] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 > [ 15.405949] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 > [ 15.405957] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000007a41a1eb state to 00000000403c96a5 > [ 15.405965] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 000000007a41a1eb > [ 15.405972] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 > [ 15.405980] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 > [ 15.405991] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 > [ 15.405998] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 > [ 15.406048] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000403c96a5 > [ 15.406055] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:89:cursor C] 00000000746efc3b state to 00000000403c96a5 > [ 15.406064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:89:cursor C] state 00000000746efc3b > [ 15.406071] [drm:drm_atomic_check_only [drm]] checking 00000000403c96a5 > [ 15.406078] [drm:drm_atomic_commit [drm]] committing 00000000403c96a5 > [ 15.406089] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000403c96a5 > [ 15.406095] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000403c96a5 > [ 15.485516] [drm:drm_mode_addfb2 [drm]] [FB:134] > [ 15.486080] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a > [ 15.486117] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040560145 state to 000000005e0e4b0a > [ 15.486145] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a > [ 15.486179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000044e6fdf state to 000000005e0e4b0a > [ 15.486215] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a > [ 15.491766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a > [ 15.491810] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a > [ 15.491933] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005e0e4b0a > [ 15.491973] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000577ba344 state to 000000005e0e4b0a > [ 15.491999] [drm:drm_atomic_check_only [drm]] checking 000000005e0e4b0a > [ 15.492030] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c21eb74a state to 000000005e0e4b0a > [ 15.492064] [drm:drm_atomic_commit [drm]] committing 000000005e0e4b0a > [ 15.496975] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005e0e4b0a > [ 15.497010] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005e0e4b0a > [ 16.356678] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] > [ 16.356693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] > [ 16.356708] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.356722] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000548ffd9d state to 000000006e858879 > [ 16.356739] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e1f1c0f1 state to 000000006e858879 > [ 16.356764] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:51:pipe A] state 00000000548ffd9d > [ 16.356783] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000e1f1c0f1 > [ 16.356800] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 000000006e858879 > [ 16.356811] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000030b3daa1 state to 000000006e858879 > [ 16.356822] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [NOCRTC] > [ 16.356832] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000030b3daa1 to [CRTC:51:pipe A] > [ 16.356859] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.356868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 16.356874] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 16.356915] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 16.356943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm > [ 16.356968] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 > [ 16.356988] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 > [ 16.357008] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:31:plane 1A] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 > [ 16.357022] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.375313] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.375339] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 16.375389] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] > [ 16.375408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] > [ 16.375426] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.375445] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000040560145 state to 000000006e858879 > [ 16.375461] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c8047799 state to 000000006e858879 > [ 16.375481] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:3840x2160] for [CRTC:72:pipe B] state 0000000040560145 > [ 16.375498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 00000000c8047799 > [ 16.375514] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000006e858879 > [ 16.375531] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 00000000679f9f9c state to 000000006e858879 > [ 16.375548] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [NOCRTC] > [ 16.375564] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 00000000679f9f9c to [CRTC:72:pipe B] > [ 16.375583] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.375603] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 16.375612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 16.375678] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 16.375718] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5, wm6, wm7, twm > [ 16.375749] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] lines 0, 3, 4, 5, 9, 11, 12, 0, 0 -> 0, 5, 6, 7, 11, 13, 0, 0, 0 > [ 16.375779] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] blocks 10, 82, 119, 136, 265, 323, 348, 0, 0 -> 72, 144, 182, 198, 327, 386, 0, 0, 0 > [ 16.375838] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:52:plane 1B] min_ddb 11, 83, 120, 137, 266, 324, 349, 0, 0 -> 73, 145, 183, 199, 328, 387, 0, 0, 0 > [ 16.375862] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.380403] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.380432] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 16.466326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.466379] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c21eb74a state to 000000006e858879 > [ 16.466420] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000577ba344 state to 000000006e858879 > [ 16.466461] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c21eb74a to [CRTC:51:pipe A] > [ 16.466499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c21eb74a > [ 16.466536] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.466670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 16.466727] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c8a5ea85 state to 000000006e858879 > [ 16.466807] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 16.466878] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 16.466943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 16.467007] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 16.467049] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.467221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.467261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 16.467316] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 16.467354] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000e1f1c0f1 state to 000000006e858879 > [ 16.467390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000548ffd9d state to 000000006e858879 > [ 16.467430] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000e1f1c0f1 to [CRTC:72:pipe B] > [ 16.467467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1f1c0f1 > [ 16.467502] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 16.467614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 > [ 16.467660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002570d1d3 state to 000000006e858879 > [ 16.467736] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 16.467826] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 16.467926] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 16.467996] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 16.468047] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 16.468167] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 16.468223] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 17.212714] [drm:drm_mode_addfb2 [drm]] [FB:143] > [ 17.262341] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 17.262375] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 17.262413] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 17.262454] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 17.262494] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 17.262529] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 17.262568] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 17.309802] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 17.325138] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 17.363673] [drm:drm_mode_addfb2 [drm]] [FB:144] > [ 17.389030] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 17.389043] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e83b417b state to 000000004c5d43a8 > [ 17.389056] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c7c74428 state to 000000004c5d43a8 > [ 17.389066] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000c7c74428 > [ 17.389074] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 17.389129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.389159] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking > [ 17.389353] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 17.389363] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004440fec8 state to 00000000ad3ae327 > [ 17.389375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000339eee21 state to 00000000ad3ae327 > [ 17.389384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000339eee21 > [ 17.389392] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 17.389436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.389452] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking > [ 17.391197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000000e9d0b2a > [ 17.391354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.391422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000e1364291 > [ 17.391485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.397162] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 17.397187] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 17.405872] [drm:drm_mode_addfb2 [drm]] [FB:145] > [ 17.407506] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 17.408550] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 17.408565] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a > [ 17.408580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a > [ 17.408590] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 17.408600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a > [ 17.408611] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000246ed832 > [ 17.408621] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a > [ 17.408716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.408748] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking > [ 17.408968] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 17.408980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 00000000505d8d8e > [ 17.408990] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ae9d6619 state to 00000000505d8d8e > [ 17.409000] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000ae9d6619 > [ 17.409009] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 17.409053] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 17.409068] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 17.413297] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] > [ 17.413439] [drm:intel_dp_detect [i915]] [CONNECTOR:95:DP-1] > [ 17.413467] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:95:DP-1] disconnected > [ 17.413503] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] > [ 17.413565] [drm:intel_dp_detect [i915]] [CONNECTOR:110:DP-2] > [ 17.414011] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 17.414382] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 17.415995] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 17.416021] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 17.416045] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 17.416334] [drm:intel_dp_detect [i915]] [ENCODER:109:DDI C] MST support: port: yes, sink: no, modparam: yes > [ 17.422310] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 17.422857] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.422873] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 17.422882] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 17.422890] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.423105] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.423116] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.423125] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.423133] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.423147] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423156] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423172] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423187] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423214] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423227] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.423243] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.423259] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:110:DP-2] probed modes : > [ 17.423276] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 17.423294] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 17.423312] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 17.423329] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 17.423347] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 17.423364] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.423383] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.423398] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.423410] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.423424] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 17.423439] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 17.423448] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.423456] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.423464] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 17.423473] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 17.423481] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.423493] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.423500] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 17.423508] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.423515] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.423523] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.423530] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 17.423538] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 17.423545] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 17.423553] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 17.423560] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 17.423568] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.423575] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.423582] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423590] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423597] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423605] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.423612] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 17.423620] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.423627] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.423635] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.423642] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 17.423723] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] > [ 17.423770] [drm:intel_dp_detect [i915]] [CONNECTOR:120:DP-3] > [ 17.424191] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 01 01 81 02 02 06 00 00 00 00 > [ 17.424555] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-00-00 dev-ID HW-rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 17.425122] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a > [ 17.425141] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a > [ 17.426094] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000 > [ 17.426117] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000 > [ 17.426138] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000 > [ 17.426420] [drm:intel_dp_detect [i915]] [ENCODER:119:DDI D] MST support: port: yes, sink: no, modparam: yes > [ 17.430296] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 17.430309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 17.432359] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support > [ 17.432885] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.432895] [drm:drm_add_edid_modes [drm]] ELD monitor DELL P2415Q > [ 17.432902] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1 > [ 17.432909] [drm:drm_add_display_info [drm]] non_desktop set to 0 > [ 17.433097] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.433104] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.433112] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576i": 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a > [ 17.433119] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL > [ 17.433126] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433132] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433139] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433146] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433153] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433159] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433166] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480i": 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a > [ 17.433173] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL > [ 17.433181] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:120:DP-3] probed modes : > [ 17.433188] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 60 533250 3840 3902 3950 4000 2160 2163 2168 2222 0x48 0x9 > [ 17.433195] [drm:drm_mode_debug_printmodeline [drm]] Modeline "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9 > [ 17.433201] [drm:drm_mode_debug_printmodeline [drm]] Modeline "2560x1440": 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9 > [ 17.433208] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1200": 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6 > [ 17.433215] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5 > [ 17.433221] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.433228] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5 > [ 17.433235] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.433241] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15 > [ 17.433248] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5 > [ 17.433255] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080i": 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15 > [ 17.433261] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.433268] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1920x1080": 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5 > [ 17.433275] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x1200": 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5 > [ 17.433282] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1600x900": 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5 > [ 17.433288] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.433295] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x1024": 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5 > [ 17.433301] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1152x864": 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5 > [ 17.433308] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.433315] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.433321] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5 > [ 17.433328] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1280x720": 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5 > [ 17.433335] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5 > [ 17.433342] [drm:drm_mode_debug_printmodeline [drm]] Modeline "1024x768": 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa > [ 17.433348] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5 > [ 17.433355] [drm:drm_mode_debug_printmodeline [drm]] Modeline "800x600": 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 > [ 17.433362] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.433368] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x576": 50 27000 720 732 796 864 576 581 586 625 0x40 0xa > [ 17.433375] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433381] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27027 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433388] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433395] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x480": 60 27000 720 736 798 858 480 489 495 525 0x40 0xa > [ 17.433401] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 75 31500 640 656 720 840 480 481 484 500 0x40 0xa > [ 17.433408] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25200 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.433414] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.433421] [drm:drm_mode_debug_printmodeline [drm]] Modeline "640x480": 60 25175 640 656 752 800 480 490 492 525 0x40 0xa > [ 17.433428] [drm:drm_mode_debug_printmodeline [drm]] Modeline "720x400": 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 > [ 17.433471] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] > [ 17.433509] [drm:intel_dp_detect [i915]] [CONNECTOR:130:DP-4] > [ 17.433520] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:130:DP-4] disconnected > [ 17.433527] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] > [ 17.433550] [drm:intel_hdmi_detect [i915]] [CONNECTOR:104:HDMI-A-1] > [ 17.433849] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 17.433869] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 17.434149] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) > [ 17.434171] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 17.434191] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 17.434211] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpb. force bit now 1 > [ 17.436907] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb > [ 17.436928] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpb. force bit now 0 > [ 17.437223] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 17.437240] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry > [ 17.437518] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) > [ 17.437537] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 17.437542] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:104:HDMI-A-1] disconnected > [ 17.437550] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] > [ 17.437568] [drm:intel_hdmi_detect [i915]] [CONNECTOR:116:HDMI-A-2] > [ 17.437863] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 17.437881] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 17.438159] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1) > [ 17.438181] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 17.438199] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 17.438217] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1 > [ 17.441061] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc > [ 17.441079] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0 > [ 17.441325] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 17.441343] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry > [ 17.441621] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1) > [ 17.441640] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 17.441644] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:116:HDMI-A-2] disconnected > [ 17.441651] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] > [ 17.441669] [drm:intel_hdmi_detect [i915]] [CONNECTOR:126:HDMI-A-3] > [ 17.441962] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 17.441979] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 17.442257] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1) > [ 17.442279] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 17.442296] [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging > [ 17.442313] [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1 > [ 17.445210] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd > [ 17.445228] [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0 > [ 17.445474] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 17.445491] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry > [ 17.445708] [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1) > [ 17.445727] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: (err -6) > [ 17.445731] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:126:HDMI-A-3] disconnected > [ 19.033461] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 19.033498] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 0000000014564192 > [ 19.033528] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003a6df13b state to 0000000014564192 > [ 19.033539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000003a6df13b > [ 19.033550] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 19.033613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 19.033632] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 19.033658] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 19.033668] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000cb785d4f > [ 19.033699] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000cb785d4f > [ 19.033708] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005752a175 > [ 19.033715] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 19.033841] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 19.033872] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 19.041962] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 19.041981] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 19.047276] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 19.047303] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 20.006109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000009e366e46 > [ 20.006141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.006159] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004fa5331c > [ 20.006182] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.016139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.016171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.016190] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.016223] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.026083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.026110] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.026125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.026148] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.036073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.036098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.036113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.036136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.046072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.046097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.046112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.046135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.056072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.056097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.056112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.056135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.066083] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.066108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.066123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.066146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.076072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.076096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.076111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.076134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.096072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.096097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.096112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.096135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.104071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.104096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.104110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.104134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.114071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.114096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.114111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.114134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.124071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.124097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.124111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.124135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.134070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.134095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.134109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.134133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.144072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.144097] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.144112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.144136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.154070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.154095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.154110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.154133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.164071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.164095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.164110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.164133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.174076] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.174101] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.174115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.174139] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.184071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.184095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.184110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.184133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.194072] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.194096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.194111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.194134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.204074] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.204099] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.204114] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.204138] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.214071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.214095] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.214110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.214133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.234073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.234098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.234112] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.234135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.274070] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.274096] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.274111] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.274135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.314088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.314124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.314142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.314166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.334077] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.334104] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.334119] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.334142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.354068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.354093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.354108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.354130] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.376068] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000c53e6df6 > [ 20.376093] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.376108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fa9f5100 > [ 20.376131] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.394073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000d1ad0452 > [ 20.394098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.394113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c53e6df6 > [ 20.394135] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.416078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000fa9f5100 > [ 20.416114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.416129] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d1ad0452 > [ 20.416152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.422661] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 > [ 20.422673] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000017b31376 state to 00000000c58cae11 > [ 20.422683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000009d80489d state to 00000000c58cae11 > [ 20.422695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000009d80489d > [ 20.422710] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 > [ 20.422856] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.422898] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking > [ 20.422943] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 > [ 20.422952] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c88e1744 state to 000000003fe34687 > [ 20.422963] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a3a0e390 state to 000000003fe34687 > [ 20.422972] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000a3a0e390 > [ 20.422979] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 > [ 20.423027] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.423038] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking > [ 20.442150] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 > [ 20.442172] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 > [ 20.444199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 > [ 20.444330] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.444367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 > [ 20.444407] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.447302] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 > [ 20.447322] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 > [ 20.447342] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c > [ 20.447364] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005a9a925a state to 0000000072b4047c > [ 20.447382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000072b4047c > [ 20.447401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000000f06e049 > [ 20.447415] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c > [ 20.447562] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.447597] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking > [ 20.447635] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f12def7f > [ 20.447648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000019eb48a0 state to 00000000f12def7f > [ 20.447661] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 00000000f12def7f > [ 20.447672] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 > [ 20.447682] [drm:drm_atomic_check_only [drm]] checking 00000000f12def7f > [ 20.447804] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.447847] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f12def7f nonblocking > [ 20.458776] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c > [ 20.458805] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c > [ 20.464009] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f12def7f > [ 20.464033] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c > [ 20.464062] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f12def7f > [ 20.464080] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d5af1617 state to 0000000072b4047c > [ 20.464097] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008416fa19 state to 0000000072b4047c > [ 20.464113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000008416fa19 > [ 20.464129] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c > [ 20.464285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.464318] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking > [ 20.464369] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 20.464382] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 00000000cb785d4f > [ 20.464393] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ac1a10e7 state to 00000000cb785d4f > [ 20.464405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000ac1a10e7 > [ 20.464417] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 20.464521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.464539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 20.475453] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c > [ 20.475483] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c > [ 20.476153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 > [ 20.476220] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.476244] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 > [ 20.476294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.480583] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 20.480602] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 20.480623] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 20.480648] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ff2d6d95 state to 0000000014564192 > [ 20.480667] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ae9d6619 state to 0000000014564192 > [ 20.480684] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000ae9d6619 > [ 20.480699] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 20.480847] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.480875] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 20.480904] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 20.480917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000505d8d8e > [ 20.480932] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003a6df13b state to 00000000505d8d8e > [ 20.480944] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003a6df13b > [ 20.480955] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 20.481001] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.481025] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 20.492049] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 20.492073] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 20.497297] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 20.497326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a > [ 20.497344] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 20.497358] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 00000000ae0bb06a > [ 20.497371] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008112a9e3 state to 00000000ae0bb06a > [ 20.497384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 000000008112a9e3 > [ 20.497397] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a > [ 20.497510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.497533] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking > [ 20.497566] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff > [ 20.497580] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d5af1617 state to 0000000094adecff > [ 20.497593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005752a175 state to 0000000094adecff > [ 20.497606] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000005752a175 > [ 20.497616] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff > [ 20.497695] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.497714] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking > [ 20.506275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000010080940 > [ 20.506427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.506500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000002603cbe2 > [ 20.506557] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.508755] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a > [ 20.508773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a > [ 20.513913] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff > [ 20.513934] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff > [ 20.513955] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae0bb06a > [ 20.513980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000ae0bb06a > [ 20.513997] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000246ed832 state to 00000000ae0bb06a > [ 20.514015] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000246ed832 > [ 20.514028] [drm:drm_atomic_check_only [drm]] checking 00000000ae0bb06a > [ 20.514142] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.514173] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae0bb06a nonblocking > [ 20.514201] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 20.514212] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005a9a925a state to 00000000505d8d8e > [ 20.514223] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000638906d4 state to 00000000505d8d8e > [ 20.514235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000638906d4 > [ 20.514247] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 20.514285] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.514301] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 20.525405] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae0bb06a > [ 20.525425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae0bb06a > [ 20.530631] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 20.530656] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 20.530680] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d89fb7fb state to 0000000014564192 > [ 20.530693] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 20.530711] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000f06e049 state to 0000000014564192 > [ 20.530728] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000000f06e049 > [ 20.530743] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 20.530859] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.530884] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 20.530917] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 20.530930] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f063ce8d state to 00000000cb785d4f > [ 20.530941] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008416fa19 state to 00000000cb785d4f > [ 20.530953] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000008416fa19 > [ 20.530963] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 20.531011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.531031] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 20.536073] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 0000000005fe4369 > [ 20.536114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.536134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000010080940 > [ 20.536168] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.542007] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 20.542022] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 20.547157] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 20.547169] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 20.554047] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 000000002603cbe2 > [ 20.554089] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.554106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000005fe4369 > [ 20.554133] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.947422] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f09b7a6e > [ 20.947449] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f1af5452 state to 00000000f09b7a6e > [ 20.947459] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057d750db state to 00000000f09b7a6e > [ 20.947469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000057d750db > [ 20.947479] [drm:drm_atomic_check_only [drm]] checking 00000000f09b7a6e > [ 20.947522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.947539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f09b7a6e nonblocking > [ 20.947567] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000b295a68 > [ 20.947578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000fe6b27d8 state to 000000000b295a68 > [ 20.947586] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3db559a state to 000000000b295a68 > [ 20.947595] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000f3db559a > [ 20.947602] [drm:drm_atomic_check_only [drm]] checking 000000000b295a68 > [ 20.947692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 20.947707] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000b295a68 nonblocking > [ 20.958693] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f09b7a6e > [ 20.958709] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f09b7a6e > [ 20.963851] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000b295a68 > [ 20.963860] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000b295a68 > [ 21.143151] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 21.143174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000046499d3 > [ 21.143186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b830a5b4 state to 00000000046499d3 > [ 21.143195] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000b830a5b4 > [ 21.143205] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 21.143259] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.143281] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 21.143326] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.143336] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf > [ 21.143346] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 0000000064a524bf > [ 21.143356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000fe3c3ec4 > [ 21.143363] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.143448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.143465] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.158722] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 21.158733] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 21.163865] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.163876] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.317441] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 > [ 21.317452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000590d9307 > [ 21.317460] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 00000000590d9307 > [ 21.317469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 000000005ba888f4 > [ 21.317477] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 > [ 21.317520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.317539] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking > [ 21.317562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.317578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e2607dec state to 0000000064a524bf > [ 21.317588] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 0000000064a524bf > [ 21.317598] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 > [ 21.317606] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.317634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.317682] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.325356] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 > [ 21.325365] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 > [ 21.330594] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.330605] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.453357] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 21.453368] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 000000008bd3a823 > [ 21.453377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 > [ 21.453386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000419d8fd6 > [ 21.453428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 21.453462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.453476] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 21.453492] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 21.453532] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 > [ 21.453560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 > [ 21.453568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c > [ 21.453577] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 21.453622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.453635] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 21.463882] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 21.463892] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 21.475399] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 21.475425] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 21.637365] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 21.637400] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000008bd3a823 > [ 21.637411] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 > [ 21.637420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 > [ 21.637428] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 21.637463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.637477] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 21.637525] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 21.637560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 > [ 21.637575] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007ae821d2 state to 00000000cff3fe76 > [ 21.637586] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000007ae821d2 > [ 21.637596] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 21.637625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.637639] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 21.647227] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 21.647237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 21.658762] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 21.658773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 21.781319] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 21.781359] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ed110662 state to 00000000046499d3 > [ 21.781367] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 00000000046499d3 > [ 21.781375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 > [ 21.781383] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 21.781435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.781450] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 21.781490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.781518] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000064a524bf > [ 21.781529] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 0000000064a524bf > [ 21.781539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 > [ 21.781547] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.781576] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.781612] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.792098] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 21.792109] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 21.797229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.797242] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.941164] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 21.941174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf > [ 21.941206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 0000000064a524bf > [ 21.941215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 0000000010080940 > [ 21.941223] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 21.941263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.941280] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 21.941298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 21.941307] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 > [ 21.941322] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 > [ 21.941337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 > [ 21.941345] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 21.941375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 21.941387] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 21.958730] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 21.958740] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 21.963967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 21.963978] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 22.037360] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 22.037370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000008bd3a823 > [ 22.037402] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 000000008bd3a823 > [ 22.037414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 00000000f4690955 > [ 22.037422] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 22.037456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.037470] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 22.037494] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 22.037552] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000cff3fe76 > [ 22.037560] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000cff3fe76 > [ 22.037569] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c > [ 22.037583] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 22.037620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.037633] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 22.047250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 22.047261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 22.058781] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 22.058792] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 22.237345] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 22.237355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 000000008bd3a823 > [ 22.237363] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000419d8fd6 state to 000000008bd3a823 > [ 22.237372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000419d8fd6 > [ 22.237380] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 22.237430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.237444] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 22.237460] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cff3fe76 > [ 22.237469] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 00000000cff3fe76 > [ 22.237503] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005ba888f4 state to 00000000cff3fe76 > [ 22.237533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 000000005ba888f4 > [ 22.237550] [drm:drm_atomic_check_only [drm]] checking 00000000cff3fe76 > [ 22.237580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.237609] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cff3fe76 nonblocking > [ 22.247260] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cff3fe76 > [ 22.247270] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cff3fe76 > [ 22.258795] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 22.258806] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 22.349362] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 > [ 22.349402] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e2607dec state to 000000009f1364b2 > [ 22.349412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007ae821d2 state to 000000009f1364b2 > [ 22.349421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 000000007ae821d2 > [ 22.349429] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 > [ 22.349478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.349492] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking > [ 22.349527] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 22.349560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 00000000046499d3 > [ 22.349568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b830a5b4 state to 00000000046499d3 > [ 22.349578] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 00000000b830a5b4 > [ 22.349587] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 22.349614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.349638] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 22.358789] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 > [ 22.358802] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 > [ 22.363927] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 22.363940] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 22.429393] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000064a524bf > [ 22.429406] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000064a524bf > [ 22.429440] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fe3c3ec4 state to 0000000064a524bf > [ 22.429449] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000fe3c3ec4 > [ 22.429456] [drm:drm_atomic_check_only [drm]] checking 0000000064a524bf > [ 22.429498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.429511] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000064a524bf nonblocking > [ 22.429532] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000046499d3 > [ 22.429540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000e5db7584 state to 00000000046499d3 > [ 22.429547] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000057b81693 state to 00000000046499d3 > [ 22.429556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 0000000057b81693 > [ 22.429563] [drm:drm_atomic_check_only [drm]] checking 00000000046499d3 > [ 22.429597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.429616] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000046499d3 nonblocking > [ 22.442367] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000064a524bf > [ 22.442417] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000064a524bf > [ 22.447561] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000046499d3 > [ 22.447614] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000046499d3 > [ 22.528747] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 > [ 22.528805] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 000000009f1364b2 > [ 22.528847] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000009f1364b2 > [ 22.528891] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:31:plane 1A] state 0000000010080940 > [ 22.528932] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 > [ 22.529197] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.529272] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking > [ 22.529370] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 > [ 22.529413] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ed110662 state to 00000000590d9307 > [ 22.529452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003338987c state to 00000000590d9307 > [ 22.529494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:145] for [PLANE:52:plane 1B] state 000000003338987c > [ 22.529530] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 > [ 22.529653] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 22.529710] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking > [ 22.542364] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 > [ 22.542414] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 > [ 22.547589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 > [ 22.547653] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 > [ 23.009536] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000397d0932 > [ 23.009568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000397d0932 > [ 23.009587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f4690955 state to 00000000397d0932 > [ 23.009616] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:31:plane 1A] state 00000000f4690955 > [ 23.009643] [drm:drm_atomic_check_only [drm]] checking 00000000397d0932 > [ 23.009799] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.009865] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000397d0932 nonblocking > [ 23.009938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bd3a823 > [ 23.009955] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000008bd3a823 > [ 23.009972] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000419d8fd6 state to 000000008bd3a823 > [ 23.009988] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:144] for [PLANE:52:plane 1B] state 00000000419d8fd6 > [ 23.010003] [drm:drm_atomic_check_only [drm]] checking 000000008bd3a823 > [ 23.010108] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.010143] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bd3a823 nonblocking > [ 23.025518] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000397d0932 > [ 23.025539] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000397d0932 > [ 23.030677] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bd3a823 > [ 23.030696] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bd3a823 > [ 23.071823] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000050c6aee > [ 23.071864] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.071900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c8e13b43 > [ 23.071924] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.392525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:47:cursor A] state 00000000e59e4cfa > [ 23.392582] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.392624] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000057d750db > [ 23.392689] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 23.607003] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 23.607025] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000003ce8e850 state to 00000000ad3ae327 > [ 23.607036] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000ad3ae327 > [ 23.607047] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000003ce8e850 to [NOCRTC] > [ 23.607056] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000003ce8e850 > [ 23.607065] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 23.607134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 23.607157] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000233ad802 state to 00000000ad3ae327 > [ 23.607179] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 23.607195] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.607210] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.607229] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.607244] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 > [ 23.624682] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 23.624698] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 23.624736] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 23.624745] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 0000000024c9c604 state to 00000000ad3ae327 > [ 23.624757] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 00000000ad3ae327 > [ 23.624766] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 0000000024c9c604 to [NOCRTC] > [ 23.624774] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 0000000024c9c604 > [ 23.624782] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 23.624840] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 > [ 23.624868] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 00000000ad3ae327 > [ 23.624886] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 23.624901] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.624933] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.624947] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 23.624957] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 > [ 23.624984] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 23.624993] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 23.736690] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 23.736728] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 23.736759] [drm:i915_audio_component_get_eld [i915]] Not valid for port B > [ 23.736792] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 23.736817] [drm:i915_audio_component_get_eld [i915]] Not valid for port C > [ 23.736845] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 23.736873] [drm:i915_audio_component_get_eld [i915]] Not valid for port D > [ 23.778545] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 23.800425] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 23.881716] [drm:hsw_audio_config_update [i915]] using Maud 784, Naud 18750 > [ 25.150487] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 25.150587] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007ede24bf state to 000000006e858879 > [ 25.150641] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000006e858879 > [ 25.150670] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007ede24bf to [CRTC:51:pipe A] > [ 25.150717] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007ede24bf > [ 25.150772] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 25.151167] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.151358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000caa1c353 state to 000000006e858879 > [ 25.151721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.152004] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.152367] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.152468] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.152618] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 25.152866] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 25.152887] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 25.152974] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e858879 > [ 25.152988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 000000000bda1a70 state to 000000006e858879 > [ 25.153008] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ea06c3a state to 000000006e858879 > [ 25.153028] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 000000000bda1a70 to [CRTC:72:pipe B] > [ 25.153048] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:68:cursor B] state 000000000bda1a70 > [ 25.153060] [drm:drm_atomic_check_only [drm]] checking 000000006e858879 > [ 25.153217] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.153252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000d5e0ab1c state to 000000006e858879 > [ 25.153289] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.153313] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.153339] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.153361] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.153383] [drm:drm_atomic_commit [drm]] committing 000000006e858879 > [ 25.153438] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e858879 > [ 25.153449] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e858879 > [ 25.153980] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c > [ 25.153999] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000b830a5b4 state to 000000004178cf0c > [ 25.154024] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 000000004178cf0c > [ 25.154041] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000b830a5b4 to [NOCRTC] > [ 25.154061] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000b830a5b4 > [ 25.154077] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c > [ 25.154166] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 25.154206] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000057b81693 state to 000000004178cf0c > [ 25.154259] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 25.154300] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154353] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154379] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c > [ 25.154444] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c > [ 25.154460] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c > [ 25.154493] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004178cf0c > [ 25.154515] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000708b01e5 state to 000000004178cf0c > [ 25.154536] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 000000004178cf0c > [ 25.154560] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000708b01e5 to [NOCRTC] > [ 25.154576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000708b01e5 > [ 25.154587] [drm:drm_atomic_check_only [drm]] checking 000000004178cf0c > [ 25.154631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 > [ 25.154655] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ce0e84b state to 000000004178cf0c > [ 25.154695] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 25.154722] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154748] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154769] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 25.154792] [drm:drm_atomic_commit [drm]] committing 000000004178cf0c > [ 25.154835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004178cf0c > [ 25.154848] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004178cf0c > [ 25.273763] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 > [ 25.273802] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040a74b19 state to 00000000383de8b5 > [ 25.273827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000303042be state to 00000000383de8b5 > [ 25.273843] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:31:plane 1A] state 00000000303042be > [ 25.273859] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 > [ 25.274049] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.274099] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking > [ 25.274159] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 > [ 25.274183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000f55d2354 > [ 25.274209] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009ff1aeec state to 00000000f55d2354 > [ 25.274223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:52:plane 1B] state 000000009ff1aeec > [ 25.274237] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 > [ 25.274352] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.274385] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking > [ 25.292269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 > [ 25.292288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 > [ 25.297446] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 > [ 25.297472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 > [ 25.297764] [drm:drm_mode_addfb2 [drm]] [FB:133] > [ 25.309363] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000590d9307 > [ 25.309501] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000086edd36c state to 00000000590d9307 > [ 25.309726] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007d32f8a2 state to 00000000590d9307 > [ 25.309825] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:31:plane 1A] state 000000007d32f8a2 > [ 25.309919] [drm:drm_atomic_check_only [drm]] checking 00000000590d9307 > [ 25.310337] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.310572] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000590d9307 nonblocking > [ 25.311148] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009f1364b2 > [ 25.311195] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000000e91ff59 state to 000000009f1364b2 > [ 25.311226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000da8e7b56 state to 000000009f1364b2 > [ 25.311247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:52:plane 1B] state 00000000da8e7b56 > [ 25.311272] [drm:drm_atomic_check_only [drm]] checking 000000009f1364b2 > [ 25.311530] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.311615] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009f1364b2 nonblocking > [ 25.313976] audit: type=1400 audit(1591264870.888:28): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 > [ 25.325815] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000590d9307 > [ 25.325907] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000590d9307 > [ 25.330935] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009f1364b2 > [ 25.330979] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009f1364b2 > [ 25.348755] audit: type=1400 audit(1591264870.924:29): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 > [ 25.370627] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 > [ 25.370629] Bluetooth: BNEP filters: protocol multicast > [ 25.370633] Bluetooth: BNEP socket layer initialized > [ 25.375033] [drm:drm_mode_addfb2 [drm]] [FB:138] > [ 25.375312] [drm:drm_mode_setcrtc [drm]] [CRTC:51:pipe A] > [ 25.375341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:110:DP-2] > [ 25.375361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033ce3db8 > [ 25.375375] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004b47c821 state to 0000000033ce3db8 > [ 25.375387] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006ac09869 state to 0000000033ce3db8 > [ 25.375404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000006ac09869 > [ 25.375420] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:51:pipe A] to 0000000033ce3db8 > [ 25.375436] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:110:DP-2] 0000000001f8dd32 state to 0000000033ce3db8 > [ 25.375454] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [NOCRTC] > [ 25.375474] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:110:DP-2] state 0000000001f8dd32 to [CRTC:51:pipe A] > [ 25.375497] [drm:drm_atomic_check_only [drm]] checking 0000000033ce3db8 > [ 25.375537] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:110:DP-2] > [ 25.375552] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:110:DP-2] keeps [ENCODER:109:DDI C], now on [CRTC:51:pipe A] > [ 25.375686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.375746] [drm:drm_atomic_commit [drm]] committing 0000000033ce3db8 > [ 25.392250] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033ce3db8 > [ 25.392268] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033ce3db8 > [ 25.392303] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] > [ 25.392323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] > [ 25.392335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.392348] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 > [ 25.392359] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 > [ 25.392372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 > [ 25.392384] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 > [ 25.392396] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000034523972 state to 000000009a35bdf3 > [ 25.392410] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [NOCRTC] > [ 25.392421] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000034523972 to [CRTC:72:pipe B] > [ 25.392434] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.392444] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 25.392450] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 25.392498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.392518] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 > [ 25.397429] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.397444] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.397934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.397958] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005cff5841 state to 000000009a35bdf3 > [ 25.397971] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.397987] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fa10941b state to 000000009a35bdf3 > [ 25.398000] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 > [ 25.414143] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.414156] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.414191] [drm:drm_mode_setcrtc [drm]] [CRTC:72:pipe B] > [ 25.414202] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:120:DP-3] > [ 25.414212] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.414223] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000009a35bdf3 > [ 25.414232] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000074389209 state to 000000009a35bdf3 > [ 25.414244] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:] for [CRTC:72:pipe B] state 00000000a5b8210f > [ 25.414253] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000074389209 > [ 25.414265] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:72:pipe B] to 000000009a35bdf3 > [ 25.414277] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:120:DP-3] 0000000083c2e296 state to 000000009a35bdf3 > [ 25.414286] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [NOCRTC] > [ 25.414295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:120:DP-3] state 0000000083c2e296 to [CRTC:72:pipe B] > [ 25.414307] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.414316] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:120:DP-3] > [ 25.414321] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:120:DP-3] keeps [ENCODER:119:DDI D], now on [CRTC:72:pipe B] > [ 25.414366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.414381] [drm:drm_atomic_commit [drm]] committing 000000009a35bdf3 > [ 25.430771] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.430790] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.587615] [drm:drm_mode_addfb2 [drm]] [FB:137] > [ 25.588562] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000607204c5 > [ 25.588594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 00000000607204c5 > [ 25.588614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005aa8cfac state to 00000000607204c5 > [ 25.588633] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000005aa8cfac > [ 25.588649] [drm:drm_atomic_check_only [drm]] checking 00000000607204c5 > [ 25.588824] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.588864] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000607204c5 nonblocking > [ 25.589160] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000006db89b4 > [ 25.589182] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 0000000006db89b4 > [ 25.589198] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000000ca4c9ba state to 0000000006db89b4 > [ 25.589216] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000000ca4c9ba > [ 25.589231] [drm:drm_atomic_check_only [drm]] checking 0000000006db89b4 > [ 25.589319] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.589346] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000006db89b4 nonblocking > [ 25.609114] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000607204c5 > [ 25.609175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000607204c5 > [ 25.614340] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000006db89b4 > [ 25.614399] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000006db89b4 > [ 25.631657] [drm:drm_mode_addfb2 [drm]] [FB:147] > [ 25.632478] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a82a142d > [ 25.632494] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000bfbd51fd state to 00000000a82a142d > [ 25.632510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004b6af36c state to 00000000a82a142d > [ 25.632526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004b6af36c > [ 25.632545] [drm:drm_atomic_check_only [drm]] checking 00000000a82a142d > [ 25.632706] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.632837] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a82a142d nonblocking > [ 25.633235] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a9357def > [ 25.633289] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000780eaeb2 state to 00000000a9357def > [ 25.633327] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ce7ebae0 state to 00000000a9357def > [ 25.633378] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 00000000ce7ebae0 > [ 25.633406] [drm:drm_atomic_check_only [drm]] checking 00000000a9357def > [ 25.633671] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.633810] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a9357def nonblocking > [ 25.659221] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a82a142d > [ 25.659354] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a82a142d > [ 25.664414] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a9357def > [ 25.664483] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 25.664520] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 00000000cb785d4f > [ 25.664540] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a9357def > [ 25.664556] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000024c9c604 state to 00000000cb785d4f > [ 25.664570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000024c9c604 > [ 25.664595] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 25.664849] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.664952] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 25.665286] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072b4047c > [ 25.665325] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d89fb7fb state to 0000000072b4047c > [ 25.665373] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002fdb83bd state to 0000000072b4047c > [ 25.665410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000002fdb83bd > [ 25.665470] [drm:drm_atomic_check_only [drm]] checking 0000000072b4047c > [ 25.665744] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.665883] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072b4047c nonblocking > [ 25.681106] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072b4047c > [ 25.681311] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072b4047c > [ 25.692362] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 25.692394] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c329590e > [ 25.692419] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 25.692437] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 00000000c329590e > [ 25.692453] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002592f0c5 state to 00000000c329590e > [ 25.692466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002592f0c5 > [ 25.692479] [drm:drm_atomic_check_only [drm]] checking 00000000c329590e > [ 25.692638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.692670] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c329590e nonblocking > [ 25.692784] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009a35bdf3 > [ 25.692797] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000009aab836c state to 000000009a35bdf3 > [ 25.692808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000044e6fdf state to 000000009a35bdf3 > [ 25.692820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000044e6fdf > [ 25.692830] [drm:drm_atomic_check_only [drm]] checking 000000009a35bdf3 > [ 25.692941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.692966] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009a35bdf3 nonblocking > [ 25.709084] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c329590e > [ 25.709105] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c329590e > [ 25.714310] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009a35bdf3 > [ 25.714357] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009a35bdf3 > [ 25.732545] [drm:drm_mode_addfb2 [drm]] [FB:148] > [ 25.732641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003fe34687 > [ 25.732658] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000cee74316 state to 000000003fe34687 > [ 25.732679] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000004ceca9e7 state to 000000003fe34687 > [ 25.732693] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:31:plane 1A] state 000000004ceca9e7 > [ 25.732715] [drm:drm_atomic_check_only [drm]] checking 000000003fe34687 > [ 25.732769] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.732802] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003fe34687 nonblocking > [ 25.733102] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c58cae11 > [ 25.733225] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a7e0ad69 state to 00000000c58cae11 > [ 25.733274] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002b75481e state to 00000000c58cae11 > [ 25.733300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:147] for [PLANE:52:plane 1B] state 000000002b75481e > [ 25.733353] [drm:drm_atomic_check_only [drm]] checking 00000000c58cae11 > [ 25.733574] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.733722] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c58cae11 nonblocking > [ 25.742433] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003fe34687 > [ 25.742504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003fe34687 > [ 25.747591] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c58cae11 > [ 25.747612] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 > [ 25.747631] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c58cae11 > [ 25.747646] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 0000000033635145 > [ 25.747660] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000a08190f state to 0000000033635145 > [ 25.747674] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:31:plane 1A] state 000000000a08190f > [ 25.747686] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 > [ 25.747857] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.747911] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking > [ 25.748026] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f > [ 25.748049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c56546ad state to 00000000e7507c6f > [ 25.748062] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008ef93bc9 state to 00000000e7507c6f > [ 25.748078] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:148] for [PLANE:52:plane 1B] state 000000008ef93bc9 > [ 25.748091] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f > [ 25.748209] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.748234] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e7507c6f nonblocking > [ 25.759225] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 > [ 25.759284] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 > [ 25.764229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f > [ 25.764250] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 > [ 25.764265] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f > [ 25.764284] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d304b4ce state to 00000000a72ea9e2 > [ 25.764297] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007150ba46 state to 00000000a72ea9e2 > [ 25.764311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000007150ba46 > [ 25.764322] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 > [ 25.764463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.764494] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking > [ 25.764530] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 25.764542] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d7bb92f2 state to 000000004c5d43a8 > [ 25.764552] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a4812a5a state to 000000004c5d43a8 > [ 25.764564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000a4812a5a > [ 25.764574] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 25.764643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.764660] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking > [ 25.792509] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 > [ 25.792625] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 > [ 25.797616] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 25.797650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 25.800508] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 > [ 25.800567] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000859f7d52 state to 0000000033635145 > [ 25.800618] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000065e53c0c state to 0000000033635145 > [ 25.800656] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000065e53c0c > [ 25.800702] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 > [ 25.800976] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.801119] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000033635145 nonblocking > [ 25.801505] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 > [ 25.801543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 00000000f55d2354 > [ 25.801584] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a1a9a3bd state to 00000000f55d2354 > [ 25.801609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000a1a9a3bd > [ 25.801638] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 > [ 25.801969] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.802166] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking > [ 25.825728] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 > [ 25.825748] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 > [ 25.830902] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 > [ 25.830932] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 > [ 25.837586] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 25.837660] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fd3aa8d0 state to 00000000a7c3d9eb > [ 25.837689] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000de4c477a state to 00000000a7c3d9eb > [ 25.837726] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000de4c477a > [ 25.837761] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 25.837997] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.838175] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking > [ 25.838378] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 25.838452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 000000006e8a3f03 > [ 25.838489] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c00467ed state to 000000006e8a3f03 > [ 25.838516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000c00467ed > [ 25.838580] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 25.838855] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.839042] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking > [ 25.864311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 25.864356] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 25.875747] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 25.875867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 25.876790] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9b8f040 > [ 25.876815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007ea06c3a state to 00000000f9b8f040 > [ 25.876837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cc7821e8 state to 00000000f9b8f040 > [ 25.876856] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000cc7821e8 > [ 25.876876] [drm:drm_atomic_check_only [drm]] checking 00000000f9b8f040 > [ 25.877085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.877133] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f9b8f040 nonblocking > [ 25.877191] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 > [ 25.877221] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007ce87400 state to 000000005795e3f4 > [ 25.877240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000466fb708 state to 000000005795e3f4 > [ 25.877257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000466fb708 > [ 25.877271] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 > [ 25.877359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.877378] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking > [ 25.909168] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9b8f040 > [ 25.909283] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9b8f040 > [ 25.914266] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 > [ 25.914289] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 > [ 25.933490] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b > [ 25.933516] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000040ff38e3 state to 00000000d223d21b > [ 25.933535] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002062a680 state to 00000000d223d21b > [ 25.933551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002062a680 > [ 25.933566] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b > [ 25.933717] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.933757] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking > [ 25.933867] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 > [ 25.933906] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005ea21f1d state to 000000005795e3f4 > [ 25.933940] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000038b73e52 state to 000000005795e3f4 > [ 25.933995] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000038b73e52 > [ 25.934034] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 > [ 25.934359] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.934554] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking > [ 25.959269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b > [ 25.959471] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b > [ 25.964230] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 > [ 25.964288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 > [ 25.965190] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000383de8b5 > [ 25.965227] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000383de8b5 > [ 25.965252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000a1a9a3bd state to 00000000383de8b5 > [ 25.965276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000a1a9a3bd > [ 25.965293] [drm:drm_atomic_check_only [drm]] checking 00000000383de8b5 > [ 25.965486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.965520] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000383de8b5 nonblocking > [ 25.965577] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f55d2354 > [ 25.965598] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000f55d2354 > [ 25.965625] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f3527d8e state to 00000000f55d2354 > [ 25.965654] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000f3527d8e > [ 25.965674] [drm:drm_atomic_check_only [drm]] checking 00000000f55d2354 > [ 25.965862] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 25.965959] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f55d2354 nonblocking > [ 25.966673] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000033635145 > [ 25.966697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000bbab38cb state to 0000000033635145 > [ 25.966723] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000033635145 > [ 25.966747] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000bbab38cb to [CRTC:51:pipe A] > [ 25.966765] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000bbab38cb > [ 25.966785] [drm:drm_atomic_check_only [drm]] checking 0000000033635145 > [ 25.966981] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.967029] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 0000000033635145 > [ 25.967093] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.967142] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.967186] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.967233] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.967258] [drm:drm_atomic_commit [drm]] committing 0000000033635145 > [ 25.970239] audit: type=1400 audit(1591264871.544:30): apparmor="DENIED" operation="mkdir" profile="/usr/bin/akonadiserver" name="/run/user/1000/akonadi/" pid=1699 comm="akonadiserver" requested_mask="c" denied_mask="c" fsuid=1000 ouid=1000 > [ 25.971457] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7507c6f > [ 25.971516] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ffb1c30d state to 00000000e7507c6f > [ 25.971540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c56546ad state to 00000000e7507c6f > [ 25.971557] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ffb1c30d to [CRTC:51:pipe A] > [ 25.971574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:150] for [PLANE:47:cursor A] state 00000000ffb1c30d > [ 25.971595] [drm:drm_atomic_check_only [drm]] checking 00000000e7507c6f > [ 25.971816] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.971916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035459c5a state to 00000000e7507c6f > [ 25.972107] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.972162] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.972196] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.972235] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.972271] [drm:drm_atomic_commit [drm]] committing 00000000e7507c6f > [ 25.976346] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d > [ 25.976369] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000056d83168 state to 000000000949282d > [ 25.976387] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fe1414f8 state to 000000000949282d > [ 25.976401] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000056d83168 to [CRTC:51:pipe A] > [ 25.976412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:151] for [PLANE:47:cursor A] state 0000000056d83168 > [ 25.976424] [drm:drm_atomic_check_only [drm]] checking 000000000949282d > [ 25.976565] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.976600] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000000949282d > [ 25.976650] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.976680] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.976701] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.976729] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.976744] [drm:drm_atomic_commit [drm]] committing 000000000949282d > [ 25.981361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059bcf2ab > [ 25.981377] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000048a2243e state to 0000000059bcf2ab > [ 25.981395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 0000000059bcf2ab > [ 25.981415] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000048a2243e to [CRTC:51:pipe A] > [ 25.981427] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:152] for [PLANE:47:cursor A] state 0000000048a2243e > [ 25.981439] [drm:drm_atomic_check_only [drm]] checking 0000000059bcf2ab > [ 25.981587] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.981634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000035f866f8 state to 0000000059bcf2ab > [ 25.981732] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.981763] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.981793] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.981814] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.981833] [drm:drm_atomic_commit [drm]] committing 0000000059bcf2ab > [ 25.986335] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 > [ 25.986358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 > [ 25.986378] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 > [ 25.986391] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] > [ 25.986405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:153] for [PLANE:47:cursor A] state 000000007d32f8a2 > [ 25.986419] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 > [ 25.986566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.986601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 > [ 25.986671] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.986697] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.986721] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.986745] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.986760] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 > [ 25.990116] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059bcf2ab > [ 25.990136] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059bcf2ab > [ 25.990147] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d > [ 25.990160] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d > [ 25.990183] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7507c6f > [ 25.990214] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7507c6f > [ 25.990233] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000033635145 > [ 25.990250] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000033635145 > [ 25.991475] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 > [ 25.991566] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 > [ 25.991821] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 > [ 25.992024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007d32f8a2 state to 00000000fb7b81d0 > [ 25.992099] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005824fd38 state to 00000000fb7b81d0 > [ 25.992156] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007d32f8a2 to [CRTC:51:pipe A] > [ 25.992212] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 000000007d32f8a2 > [ 25.992229] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 > [ 25.992294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 25.992311] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000383de8b5 > [ 25.992332] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000383de8b5 > [ 25.992348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c00467ed state to 00000000fb7b81d0 > [ 25.992378] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 25.992399] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 25.992427] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 25.992446] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 25.992459] [drm:drm_atomic_commit [drm]] committing 00000000fb7b81d0 > [ 25.992502] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 > [ 25.992514] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 > [ 25.997491] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f55d2354 > [ 25.997513] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f55d2354 > [ 26.001019] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cd3e6c30 > [ 26.001079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000e5db7584 state to 00000000cd3e6c30 > [ 26.001104] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000efc3561e state to 00000000cd3e6c30 > [ 26.001122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000efc3561e > [ 26.001139] [drm:drm_atomic_check_only [drm]] checking 00000000cd3e6c30 > [ 26.001381] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.001424] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cd3e6c30 nonblocking > [ 26.001502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fb7b81d0 > [ 26.001517] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008a796f17 state to 00000000fb7b81d0 > [ 26.001539] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000fb7b81d0 > [ 26.001553] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000008a19b957 > [ 26.001564] [drm:drm_atomic_check_only [drm]] checking 00000000fb7b81d0 > [ 26.001663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.001718] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fb7b81d0 nonblocking > [ 26.025633] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cd3e6c30 > [ 26.025657] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cd3e6c30 > [ 26.031038] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fb7b81d0 > [ 26.031111] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fb7b81d0 > [ 26.032140] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000949282d > [ 26.032186] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002822e6ce state to 000000000949282d > [ 26.032214] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005ba888f4 state to 000000000949282d > [ 26.032242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005ba888f4 > [ 26.032278] [drm:drm_atomic_check_only [drm]] checking 000000000949282d > [ 26.032460] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.032551] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000949282d nonblocking > [ 26.032715] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 > [ 26.032747] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000048287824 > [ 26.032774] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000010080940 state to 0000000048287824 > [ 26.032814] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000010080940 > [ 26.032843] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 > [ 26.033033] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.033133] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking > [ 26.058971] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000949282d > [ 26.058986] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000949282d > [ 26.064135] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 > [ 26.064151] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 > [ 26.065142] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f > [ 26.065161] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 00000000db144c3f > [ 26.065176] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003338987c state to 00000000db144c3f > [ 26.065189] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003338987c > [ 26.065202] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f > [ 26.065341] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.065389] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking > [ 26.065427] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 > [ 26.065439] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000564ca5d1 state to 0000000048287824 > [ 26.065452] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003d3598b9 state to 0000000048287824 > [ 26.065464] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003d3598b9 > [ 26.065477] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 > [ 26.065545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.065571] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking > [ 26.092355] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f > [ 26.092369] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f > [ 26.097513] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 > [ 26.097527] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 > [ 26.098050] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 26.098064] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7bb92f2 state to 000000004c5d43a8 > [ 26.098076] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000008f17f63d state to 000000004c5d43a8 > [ 26.098088] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000008f17f63d > [ 26.098098] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 26.098144] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.098173] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004c5d43a8 nonblocking > [ 26.098205] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 > [ 26.098216] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d304b4ce state to 00000000a72ea9e2 > [ 26.098226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000001a43d2f state to 00000000a72ea9e2 > [ 26.098237] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 0000000001a43d2f > [ 26.098247] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 > [ 26.098291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.098309] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking > [ 26.125651] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 26.125679] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 26.130834] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 > [ 26.130867] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 > [ 26.131366] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 26.131383] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 00000000ad3ae327 > [ 26.131396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000062957589 state to 00000000ad3ae327 > [ 26.131409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000062957589 > [ 26.131421] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 26.131472] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.131499] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking > [ 26.131531] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 > [ 26.131543] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 000000009ab7d7a2 > [ 26.131553] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000e42a1bac state to 000000009ab7d7a2 > [ 26.131565] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000e42a1bac > [ 26.131577] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 > [ 26.131662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.131685] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking > [ 26.158952] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 26.158972] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 26.164140] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 > [ 26.164157] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 > [ 26.164688] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 > [ 26.164707] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c88e1744 state to 000000009ab7d7a2 > [ 26.164721] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002b4570b0 state to 000000009ab7d7a2 > [ 26.164732] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000002b4570b0 > [ 26.164741] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 > [ 26.164779] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.164794] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ab7d7a2 nonblocking > [ 26.164817] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 26.164828] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000cfd8c976 state to 00000000ad3ae327 > [ 26.164837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000217fb779 state to 00000000ad3ae327 > [ 26.164846] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000217fb779 > [ 26.164854] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 26.164902] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.164925] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ad3ae327 nonblocking > [ 26.192294] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 > [ 26.192316] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 > [ 26.197558] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 26.197586] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 26.198086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005795e3f4 > [ 26.198107] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000005795e3f4 > [ 26.198125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000d5e0ab1c state to 000000005795e3f4 > [ 26.198142] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000d5e0ab1c > [ 26.198161] [drm:drm_atomic_check_only [drm]] checking 000000005795e3f4 > [ 26.198224] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.198254] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005795e3f4 nonblocking > [ 26.198298] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b > [ 26.198316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c2f83703 state to 00000000d223d21b > [ 26.198334] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001aa4b64b state to 00000000d223d21b > [ 26.198353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001aa4b64b > [ 26.198369] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b > [ 26.198496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.198527] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking > [ 26.214153] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b > [ 26.214175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b > [ 26.225632] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005795e3f4 > [ 26.225662] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005795e3f4 > [ 26.462632] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 > [ 26.462656] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007d558a50 state to 00000000e7804b44 > [ 26.462673] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 > [ 26.462708] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006d587bbb state to 00000000e7804b44 > [ 26.462727] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 > [ 26.475706] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 > [ 26.475726] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 > [ 26.475759] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e7804b44 > [ 26.475794] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000008598d75f state to 00000000e7804b44 > [ 26.475808] [drm:drm_atomic_check_only [drm]] checking 00000000e7804b44 > [ 26.475829] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000fe3c3ec4 state to 00000000e7804b44 > [ 26.475857] [drm:drm_atomic_commit [drm]] committing 00000000e7804b44 > [ 26.480907] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e7804b44 > [ 26.480929] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e7804b44 > [ 26.490104] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d223d21b > [ 26.490125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c2f83703 state to 00000000d223d21b > [ 26.490143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000bda1a70 state to 00000000d223d21b > [ 26.490160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000000bda1a70 > [ 26.490174] [drm:drm_atomic_check_only [drm]] checking 00000000d223d21b > [ 26.490263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.490296] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d223d21b nonblocking > [ 26.490379] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005b4fe663 > [ 26.490395] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 000000005b4fe663 > [ 26.490412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000004ad4d2a9 state to 000000005b4fe663 > [ 26.490432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000004ad4d2a9 > [ 26.490446] [drm:drm_atomic_check_only [drm]] checking 000000005b4fe663 > [ 26.490577] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 26.490612] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005b4fe663 nonblocking > [ 26.508990] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d223d21b > [ 26.509012] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d223d21b > [ 26.514166] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005b4fe663 > [ 26.514193] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005b4fe663 > [ 27.203105] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048287824 > [ 27.203118] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001ff21e1e state to 0000000048287824 > [ 27.203128] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003d3598b9 state to 0000000048287824 > [ 27.203138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003d3598b9 > [ 27.203147] [drm:drm_atomic_check_only [drm]] checking 0000000048287824 > [ 27.203191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.203207] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048287824 nonblocking > [ 27.203239] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db144c3f > [ 27.203248] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 00000000db144c3f > [ 27.203257] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000006225429c state to 00000000db144c3f > [ 27.203266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000006225429c > [ 27.203274] [drm:drm_atomic_check_only [drm]] checking 00000000db144c3f > [ 27.203327] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.203340] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000db144c3f nonblocking > [ 27.214214] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db144c3f > [ 27.214237] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db144c3f > [ 27.225708] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048287824 > [ 27.225729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048287824 > [ 27.559248] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 27.559266] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008a796f17 state to 00000000a7c3d9eb > [ 27.559287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000048a2243e state to 00000000a7c3d9eb > [ 27.559302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000048a2243e > [ 27.559317] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 27.559457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.559500] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking > [ 27.559579] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 > [ 27.559595] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000086edd36c state to 0000000073a3fc87 > [ 27.559614] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000c26d3cf7 state to 0000000073a3fc87 > [ 27.559630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000c26d3cf7 > [ 27.559644] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 > [ 27.559875] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.559954] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking > [ 27.564240] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 > [ 27.564260] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 > [ 27.575734] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 27.575758] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 27.673875] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006fb947e5 > [ 27.673893] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005ea21f1d state to 000000006fb947e5 > [ 27.673907] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000003def6fcc state to 000000006fb947e5 > [ 27.673919] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000003def6fcc > [ 27.673930] [drm:drm_atomic_check_only [drm]] checking 000000006fb947e5 > [ 27.674063] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.674111] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006fb947e5 nonblocking > [ 27.674162] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000022edf81f > [ 27.674180] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bfbd51fd state to 0000000022edf81f > [ 27.674205] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ba74e4f8 state to 0000000022edf81f > [ 27.674221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000ba74e4f8 > [ 27.674236] [drm:drm_atomic_check_only [drm]] checking 0000000022edf81f > [ 27.674351] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 27.674383] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000022edf81f nonblocking > [ 27.692395] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006fb947e5 > [ 27.692416] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006fb947e5 > [ 27.697567] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000022edf81f > [ 27.697587] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000022edf81f > [ 28.369864] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a72ea9e2 > [ 28.369881] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f4595bbc state to 00000000a72ea9e2 > [ 28.369892] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e0f8f74a state to 00000000a72ea9e2 > [ 28.369905] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000e0f8f74a > [ 28.369917] [drm:drm_atomic_check_only [drm]] checking 00000000a72ea9e2 > [ 28.370044] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.370094] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a72ea9e2 nonblocking > [ 28.370128] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e2245646 > [ 28.370140] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000080a25d5d state to 00000000e2245646 > [ 28.370155] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ec8b7f51 state to 00000000e2245646 > [ 28.370165] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000ec8b7f51 > [ 28.370173] [drm:drm_atomic_check_only [drm]] checking 00000000e2245646 > [ 28.370236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.370259] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e2245646 nonblocking > [ 28.392441] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a72ea9e2 > [ 28.392456] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a72ea9e2 > [ 28.397627] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e2245646 > [ 28.397645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e2245646 > [ 28.441580] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007c7bef8b > [ 28.441593] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f275b54 state to 000000007c7bef8b > [ 28.441602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000919acba8 state to 000000007c7bef8b > [ 28.441619] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000919acba8 > [ 28.441636] [drm:drm_atomic_check_only [drm]] checking 000000007c7bef8b > [ 28.441807] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.441857] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007c7bef8b nonblocking > [ 28.441895] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e4cb9fa > [ 28.441926] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004f0788b2 state to 000000009e4cb9fa > [ 28.441949] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000003cdbbe01 state to 000000009e4cb9fa > [ 28.441966] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000003cdbbe01 > [ 28.441983] [drm:drm_atomic_check_only [drm]] checking 000000009e4cb9fa > [ 28.442129] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.442151] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e4cb9fa nonblocking > [ 28.459102] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007c7bef8b > [ 28.459118] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007c7bef8b > [ 28.464290] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e4cb9fa > [ 28.464312] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e4cb9fa > [ 28.722641] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 28.722655] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007b516bb0 state to 00000000cb785d4f > [ 28.722664] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000dfbf1324 state to 00000000cb785d4f > [ 28.722675] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000dfbf1324 > [ 28.722684] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 28.722813] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.722835] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 28.722882] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff > [ 28.722908] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003cd98772 state to 0000000094adecff > [ 28.722916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009beb6a90 state to 0000000094adecff > [ 28.722941] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000009beb6a90 > [ 28.722949] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff > [ 28.723029] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 28.723064] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking > [ 28.742477] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 28.742503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 28.747618] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff > [ 28.747633] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff > [ 31.314482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 31.314504] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 33.564502] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000094adecff > [ 33.564557] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001450a92b state to 0000000094adecff > [ 33.564599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000fb9c3f95 state to 0000000094adecff > [ 33.564642] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 00000000fb9c3f95 > [ 33.564680] [drm:drm_atomic_check_only [drm]] checking 0000000094adecff > [ 33.564830] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 33.564895] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000094adecff nonblocking > [ 33.564991] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cb785d4f > [ 33.565033] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d785a3ff state to 00000000cb785d4f > [ 33.565068] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000001694423a state to 00000000cb785d4f > [ 33.565110] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000001694423a > [ 33.565145] [drm:drm_atomic_check_only [drm]] checking 00000000cb785d4f > [ 33.565280] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 33.565331] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cb785d4f nonblocking > [ 33.581360] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cb785d4f > [ 33.581410] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cb785d4f > [ 33.592967] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000094adecff > [ 33.593018] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000094adecff > [ 38.906236] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 38.906257] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000fbb9145a state to 00000000a7c3d9eb > [ 38.906277] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 38.906300] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031040ef6 state to 00000000a7c3d9eb > [ 38.906317] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb > [ 38.909717] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 38.909729] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 38.909751] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 38.909763] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000036e370a5 state to 00000000a7c3d9eb > [ 38.909772] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 38.909789] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000021d5013d state to 00000000a7c3d9eb > [ 38.909799] [drm:drm_atomic_commit [drm]] committing 00000000a7c3d9eb > [ 38.914888] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 38.914897] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 38.919179] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7c3d9eb > [ 38.919191] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000dbca7270 state to 00000000a7c3d9eb > [ 38.919200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f5920396 state to 00000000a7c3d9eb > [ 38.919210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000f5920396 > [ 38.919219] [drm:drm_atomic_check_only [drm]] checking 00000000a7c3d9eb > [ 38.919269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 38.919283] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7c3d9eb nonblocking > [ 38.919307] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3b84e34 > [ 38.919316] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007a397cd1 state to 00000000d3b84e34 > [ 38.919324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000008a19b957 state to 00000000d3b84e34 > [ 38.919333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000008a19b957 > [ 38.919340] [drm:drm_atomic_check_only [drm]] checking 00000000d3b84e34 > [ 38.919369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 38.919380] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3b84e34 nonblocking > [ 38.943037] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7c3d9eb > [ 38.943049] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7c3d9eb > [ 38.948213] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3b84e34 > [ 38.948227] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3b84e34 > [ 41.313990] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 41.314011] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000dffa3a5 state to 000000006e8a3f03 > [ 41.314024] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 41.314044] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000311fb5cc state to 000000006e8a3f03 > [ 41.314058] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 > [ 41.326599] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 41.326616] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 41.326650] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 41.326666] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000a5b8210f state to 000000006e8a3f03 > [ 41.326677] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 41.326694] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000f678ed03 state to 000000006e8a3f03 > [ 41.326708] [drm:drm_atomic_commit [drm]] committing 000000006e8a3f03 > [ 41.331765] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 41.331799] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 41.340881] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000014564192 > [ 41.340898] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b35cdb13 state to 0000000014564192 > [ 41.340911] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002bd9f19b state to 0000000014564192 > [ 41.340924] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002bd9f19b > [ 41.340936] [drm:drm_atomic_check_only [drm]] checking 0000000014564192 > [ 41.341000] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.341031] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000014564192 nonblocking > [ 41.341070] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000505d8d8e > [ 41.341083] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007b516bb0 state to 00000000505d8d8e > [ 41.341093] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000628b1791 state to 00000000505d8d8e > [ 41.341106] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000628b1791 > [ 41.341117] [drm:drm_atomic_check_only [drm]] checking 00000000505d8d8e > [ 41.341171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.341187] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000505d8d8e nonblocking > [ 41.359835] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000014564192 > [ 41.359858] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000014564192 > [ 41.365024] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000505d8d8e > [ 41.365048] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000505d8d8e > [ 41.615782] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000336440de > [ 41.615833] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.617086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 > [ 41.617101] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000564ca5d1 state to 0000000029690ea0 > [ 41.617111] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 > [ 41.617127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000043ec3708 state to 0000000029690ea0 > [ 41.617139] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 > [ 41.626562] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 > [ 41.626572] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 > [ 41.626602] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000029690ea0 > [ 41.626612] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000859f7d52 state to 0000000029690ea0 > [ 41.626620] [drm:drm_atomic_check_only [drm]] checking 0000000029690ea0 > [ 41.626634] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000dd5969b1 state to 0000000029690ea0 > [ 41.626644] [drm:drm_atomic_commit [drm]] committing 0000000029690ea0 > [ 41.631801] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000029690ea0 > [ 41.631813] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000029690ea0 > [ 41.636417] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006e8a3f03 > [ 41.636431] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005cff5841 state to 000000006e8a3f03 > [ 41.636443] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000005f261da0 state to 000000006e8a3f03 > [ 41.636455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 000000005f261da0 > [ 41.636465] [drm:drm_atomic_check_only [drm]] checking 000000006e8a3f03 > [ 41.636505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.636529] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006e8a3f03 nonblocking > [ 41.636564] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073a3fc87 > [ 41.636574] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000004b47c821 state to 0000000073a3fc87 > [ 41.636583] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000005b73df2f state to 0000000073a3fc87 > [ 41.636593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000005b73df2f > [ 41.636601] [drm:drm_atomic_check_only [drm]] checking 0000000073a3fc87 > [ 41.636649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 41.636661] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073a3fc87 nonblocking > [ 41.659846] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006e8a3f03 > [ 41.659868] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006e8a3f03 > [ 41.665021] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073a3fc87 > [ 41.665038] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073a3fc87 > [ 41.694775] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:149] for [PLANE:47:cursor A] state 00000000b6d87631 > [ 41.694823] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 42.188680] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ad3ae327 > [ 42.188751] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000568d4c state to 00000000ad3ae327 > [ 42.188815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000041d1b185 state to 00000000ad3ae327 > [ 42.188876] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000000568d4c to [NOCRTC] > [ 42.188938] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000000568d4c > [ 42.188994] [drm:drm_atomic_check_only [drm]] checking 00000000ad3ae327 > [ 42.189140] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 42.189200] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ccaa86bb state to 00000000ad3ae327 > [ 42.189327] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 42.189398] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 42.189464] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 42.189528] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 42.189570] [drm:drm_atomic_commit [drm]] committing 00000000ad3ae327 > [ 42.189702] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ad3ae327 > [ 42.189745] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ad3ae327 > [ 75.712241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000607204c5 > [ 75.712254] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000576bf63 state to 00000000607204c5 > [ 75.712264] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000143dcc1f state to 00000000607204c5 > [ 75.712276] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000000576bf63 to [CRTC:51:pipe A] > [ 75.712285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000576bf63 > [ 75.712296] [drm:drm_atomic_check_only [drm]] checking 00000000607204c5 > [ 75.712332] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 75.712348] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000ffcd5de state to 00000000607204c5 > [ 75.712381] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 75.712399] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 75.712415] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 75.712431] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 75.712442] [drm:drm_atomic_commit [drm]] committing 00000000607204c5 > [ 75.712495] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000607204c5 > [ 75.712504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000607204c5 > [ 75.781357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ad4520e1 > [ 75.781395] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.791429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 > [ 75.791470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.801366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ad4520e1 > [ 75.801416] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.811455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 > [ 75.811526] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.821420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ad4520e1 > [ 75.821537] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.822025] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004f41ae90 > [ 75.822160] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.828890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000111517e > [ 75.828945] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004474ffb0 state to 000000000111517e > [ 75.828985] [drm:drm_atomic_check_only [drm]] checking 000000000111517e > [ 75.829049] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001dbce9c7 state to 000000000111517e > [ 75.829094] [drm:drm_atomic_commit [drm]] committing 000000000111517e > [ 75.845350] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000111517e > [ 75.845405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 > [ 75.845533] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.845576] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000111517e > [ 75.845662] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000111517e > [ 75.845711] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000f252405b state to 000000000111517e > [ 75.845747] [drm:drm_atomic_check_only [drm]] checking 000000000111517e > [ 75.845797] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000065cb5608 state to 000000000111517e > [ 75.845840] [drm:drm_atomic_commit [drm]] committing 000000000111517e > [ 75.850710] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000111517e > [ 75.850765] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.850899] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.850942] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000111517e > [ 75.851263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007b475b53 > [ 75.851378] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.852514] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c16485eb > [ 75.852646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.861172] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.861226] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.871150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 75.871191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.881240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.881355] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.893221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 75.893271] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.903314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.903439] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.913297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 75.913425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.923441] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.923656] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.933291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 75.933421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.943379] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.943566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.953281] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 75.953413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.963369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.963556] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.973333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 75.973559] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.983300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 75.983431] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 75.993401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 75.993546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.003301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e5535449 > [ 76.003435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.013376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c6b9e7dd > [ 76.013646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.023314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004f41ae90 > [ 76.023453] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.033435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f > [ 76.033571] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.043538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001f6da878 > [ 76.043679] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.048401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eb35d02a > [ 76.048532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.053296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f > [ 76.053412] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.063269] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.063388] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.083545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f > [ 76.083684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.223546] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.223683] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.233482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f > [ 76.233614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.243500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.243637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.253466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f > [ 76.253601] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.263265] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.263394] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.273468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f > [ 76.273600] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.275225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 76.275358] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.283228] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.283340] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.293214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.293326] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.303554] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.303690] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.313316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.313448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.323542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.323679] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.333455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.333591] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.343258] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.343390] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.353459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.353594] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.363280] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.363411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.373466] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.373593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.383343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.383482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.393463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.393597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.403300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.403426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.413475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.413603] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.423544] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.423680] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.433472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.433605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.443555] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.443734] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.453483] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.453624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.463485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.463630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.473481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.473620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.493468] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000347a6df5 > [ 76.493600] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.545324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.545445] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.595519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 > [ 76.595647] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.623497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.623629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.643494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 > [ 76.643630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.663554] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.663713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.683463] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 > [ 76.683597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.703310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.703442] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.723290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 > [ 76.723417] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.743544] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.743720] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.783547] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 > [ 76.783725] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.843532] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.843662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.905560] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 > [ 76.905699] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 76.965472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 76.965607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 77.025455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009314a5c3 > [ 77.025591] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 77.074419] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009658a4c3 > [ 77.074439] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 000000009658a4c3 > [ 77.074457] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000ffcd5de state to 000000009658a4c3 > [ 77.074472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000000ffcd5de > [ 77.074485] [drm:drm_atomic_check_only [drm]] checking 000000009658a4c3 > [ 77.074568] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 77.074593] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009658a4c3 nonblocking > [ 77.074640] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 > [ 77.074656] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c6de3170 state to 00000000a311e694 > [ 77.074668] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000000568d4c state to 00000000a311e694 > [ 77.074683] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000000568d4c > [ 77.074695] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 > [ 77.074751] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 77.074769] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a311e694 nonblocking > [ 77.095355] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009658a4c3 > [ 77.095391] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009658a4c3 > [ 77.100625] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 > [ 77.100677] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 > [ 77.585381] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 > [ 77.585398] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d29c2cef state to 00000000a311e694 > [ 77.585407] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 > [ 77.585424] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 00000000a311e694 > [ 77.585434] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 > [ 77.595300] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 > [ 77.595322] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 > [ 77.595350] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 > [ 77.595363] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000df3dd718 state to 00000000a311e694 > [ 77.595371] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 > [ 77.595384] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a35c929d state to 00000000a311e694 > [ 77.595395] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 > [ 77.600480] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 > [ 77.600493] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 > [ 77.603245] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 > [ 77.603259] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000ba1edb00 state to 00000000a311e694 > [ 77.603269] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 > [ 77.603287] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000000568d4c state to 00000000a311e694 > [ 77.603297] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 > [ 77.611945] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 > [ 77.611956] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 > [ 77.611976] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 > [ 77.611986] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000065c69239 state to 00000000a311e694 > [ 77.611994] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 > [ 77.612005] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000046234f6 state to 00000000a311e694 > [ 77.612015] [drm:drm_atomic_commit [drm]] committing 00000000a311e694 > [ 77.617129] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 > [ 77.617140] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 > [ 77.622988] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 > [ 77.623007] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000df3dd718 state to 00000000a311e694 > [ 77.623020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000f3527d8e state to 00000000a311e694 > [ 77.623030] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000f3527d8e > [ 77.623039] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 > [ 77.623136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 77.623170] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a311e694 nonblocking > [ 77.623230] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009658a4c3 > [ 77.623242] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005e067cfa state to 000000009658a4c3 > [ 77.623252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000009b956d2f state to 000000009658a4c3 > [ 77.623261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000009b956d2f > [ 77.623271] [drm:drm_atomic_check_only [drm]] checking 000000009658a4c3 > [ 77.623350] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 77.623373] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009658a4c3 nonblocking > [ 77.624696] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 77.624912] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 77.645249] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 > [ 77.645275] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 > [ 77.650421] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009658a4c3 > [ 77.650436] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009658a4c3 > [ 79.835317] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cf2f853c > [ 79.835486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.845507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d > [ 79.845624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.855334] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba > [ 79.855448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.865484] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d > [ 79.865622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.875475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba > [ 79.875613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.885352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d > [ 79.885532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.895528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba > [ 79.895690] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.905325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d > [ 79.905461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.915469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e44a15ba > [ 79.915615] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.925302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000091d4ac2d > [ 79.925433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.935312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 79.935454] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.945282] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 79.945405] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.955494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 79.955663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.965460] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 79.965593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.975471] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 79.975609] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.985296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 79.985441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 79.995529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 79.995681] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.005487] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 80.005627] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.015327] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 80.015464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.025288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 80.025420] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.035299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 80.035437] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.045482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 80.045611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.055317] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 80.055457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.065490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 80.065624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.075462] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004b38277d > [ 80.075610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.125351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000325dd604 > [ 80.125485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.135356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.135496] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.145284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.145413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.155461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.155609] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.165266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.165398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.177475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.177613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.183287] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.183415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.193307] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.193441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.203311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.203450] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.217262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.217388] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.227279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.227401] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.237310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.237448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.247500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.247655] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.257333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.257473] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.267469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.267601] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.277467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.277607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.285323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.285464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.295452] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.295588] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.305318] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.305470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.315543] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.315696] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.335338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.335468] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.385288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000154a4b83 > [ 80.385430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 80.445465] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eadbf13f > [ 80.445594] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 82.028033] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 82.028049] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000004c5d43a8 > [ 82.028060] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 82.028080] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000154a4b83 state to 000000004c5d43a8 > [ 82.028092] [drm:drm_atomic_commit [drm]] committing 000000004c5d43a8 > [ 82.028824] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 82.028834] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 82.028849] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004c5d43a8 > [ 82.028878] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000008fdc242 state to 000000004c5d43a8 > [ 82.028886] [drm:drm_atomic_check_only [drm]] checking 000000004c5d43a8 > [ 82.028898] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007a36128c state to 000000004c5d43a8 > [ 82.028909] [drm:drm_atomic_commit [drm]] committing 000000004c5d43a8 > [ 82.034056] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004c5d43a8 > [ 82.034069] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004c5d43a8 > [ 82.037311] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004eb6a0eb > [ 82.037326] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000002d5bfaf4 state to 000000004eb6a0eb > [ 82.037337] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010080940 state to 000000004eb6a0eb > [ 82.037348] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000010080940 > [ 82.037359] [drm:drm_atomic_check_only [drm]] checking 000000004eb6a0eb > [ 82.037416] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 82.037436] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004eb6a0eb nonblocking > [ 82.037464] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000093e3499b > [ 82.037476] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006047c305 state to 0000000093e3499b > [ 82.037488] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a7136fb4 state to 0000000093e3499b > [ 82.037499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000a7136fb4 > [ 82.037509] [drm:drm_atomic_check_only [drm]] checking 0000000093e3499b > [ 82.037544] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 82.037558] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000093e3499b nonblocking > [ 82.062210] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004eb6a0eb > [ 82.062236] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004eb6a0eb > [ 82.067378] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093e3499b > [ 82.067394] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000093e3499b > [ 84.543578] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ed46affd > [ 84.543602] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004b47c821 state to 00000000ed46affd > [ 84.543618] [drm:drm_atomic_check_only [drm]] checking 00000000ed46affd > [ 84.543648] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002603cbe2 state to 00000000ed46affd > [ 84.543666] [drm:drm_atomic_commit [drm]] committing 00000000ed46affd > [ 84.545657] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ed46affd > [ 84.545673] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ed46affd > [ 84.545701] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ed46affd > [ 84.545718] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002d5bfaf4 state to 00000000ed46affd > [ 84.545731] [drm:drm_atomic_check_only [drm]] checking 00000000ed46affd > [ 84.545748] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000010080940 state to 00000000ed46affd > [ 84.545763] [drm:drm_atomic_commit [drm]] committing 00000000ed46affd > [ 84.550847] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ed46affd > [ 84.550860] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ed46affd > [ 84.557572] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006d11616c > [ 84.557590] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000049283a72 state to 000000006d11616c > [ 84.557608] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000069618bd2 state to 000000006d11616c > [ 84.557623] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000069618bd2 > [ 84.557634] [drm:drm_atomic_check_only [drm]] checking 000000006d11616c > [ 84.557741] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 84.557765] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006d11616c nonblocking > [ 84.557820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000072283c24 > [ 84.557834] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000006746a59a state to 0000000072283c24 > [ 84.557845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b4d7ac94 state to 0000000072283c24 > [ 84.557857] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000b4d7ac94 > [ 84.557867] [drm:drm_atomic_check_only [drm]] checking 0000000072283c24 > [ 84.557936] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 84.557952] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000072283c24 nonblocking > [ 84.578982] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006d11616c > [ 84.579000] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006d11616c > [ 84.584154] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000072283c24 > [ 84.584177] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000072283c24 > [ 84.810041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009e7e27ec > [ 84.810134] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 84.813702] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a92e964 > [ 84.813718] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000004f0788b2 state to 000000002a92e964 > [ 84.813728] [drm:drm_atomic_check_only [drm]] checking 000000002a92e964 > [ 84.813749] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000010343cf4 state to 000000002a92e964 > [ 84.813760] [drm:drm_atomic_commit [drm]] committing 000000002a92e964 > [ 84.829128] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a92e964 > [ 84.829143] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a92e964 > [ 84.829191] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002a92e964 > [ 84.829204] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000b35e8fe1 state to 000000002a92e964 > [ 84.829214] [drm:drm_atomic_check_only [drm]] checking 000000002a92e964 > [ 84.829228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000a24a2bb2 state to 000000002a92e964 > [ 84.829240] [drm:drm_atomic_commit [drm]] committing 000000002a92e964 > [ 84.834375] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002a92e964 > [ 84.834390] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002a92e964 > [ 84.837643] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ed46affd > [ 84.837657] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d304b4ce state to 00000000ed46affd > [ 84.837668] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002603cbe2 state to 00000000ed46affd > [ 84.837680] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000002603cbe2 > [ 84.837691] [drm:drm_atomic_check_only [drm]] checking 00000000ed46affd > [ 84.837740] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 84.837767] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ed46affd nonblocking > [ 84.837799] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000093e3499b > [ 84.837810] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000ba1edb00 state to 0000000093e3499b > [ 84.837820] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007ae821d2 state to 0000000093e3499b > [ 84.837831] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 000000007ae821d2 > [ 84.837840] [drm:drm_atomic_check_only [drm]] checking 0000000093e3499b > [ 84.837885] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 84.837905] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000093e3499b nonblocking > [ 84.862321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ed46affd > [ 84.862340] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ed46affd > [ 84.867503] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093e3499b > [ 84.867515] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000093e3499b > [ 84.896014] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000f1c75f07 > [ 84.896056] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 87.939190] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009bdf158a > [ 87.939238] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 87.949179] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 > [ 87.949242] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 87.959161] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009bdf158a > [ 87.959214] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 87.969364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 > [ 87.969408] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 87.979229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 > [ 87.979284] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 87.989350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c > [ 87.989426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 87.999240] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 > [ 87.999345] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.009303] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c > [ 88.009432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.019315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 > [ 88.019497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.031529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c > [ 88.031666] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.037250] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 > [ 88.037398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.047541] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c > [ 88.047682] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.057296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a20c8f02 > [ 88.057434] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.057767] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ba74e4f8 > [ 88.057883] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.058961] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003def6fcc > [ 88.059085] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.059176] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ba74e4f8 > [ 88.059286] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.059361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003def6fcc > [ 88.059483] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.067549] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c > [ 88.067677] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.068174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000ba74e4f8 > [ 88.068333] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.070123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003def6fcc > [ 88.070245] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.077300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000011d500be > [ 88.077477] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.087298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000158adbaf > [ 88.087482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.097298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000011d500be > [ 88.097475] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.107169] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000158adbaf > [ 88.107272] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.117202] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000011d500be > [ 88.117301] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.127203] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007445155b > [ 88.127307] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.137297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 88.137440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.147296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007445155b > [ 88.147444] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.157417] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 88.157677] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.167323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007445155b > [ 88.167508] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.177435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 88.177607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.187310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 > [ 88.187456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.197418] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e0498636 > [ 88.197627] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.207404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 > [ 88.207631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.217445] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e0498636 > [ 88.217669] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.227381] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 > [ 88.227606] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.237296] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e0498636 > [ 88.237426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.247467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000419d8fd6 > [ 88.247674] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 88.601051] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 88.601084] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 88.815597] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b436c25 > [ 88.815609] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ddf8aae9 state to 000000001b436c25 > [ 88.815619] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000019eb48a0 state to 000000001b436c25 > [ 88.815629] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ddf8aae9 to [NOCRTC] > [ 88.815637] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ddf8aae9 > [ 88.815646] [drm:drm_atomic_check_only [drm]] checking 000000001b436c25 > [ 88.815710] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 88.815730] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000080184d54 state to 000000001b436c25 > [ 88.815750] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 88.815779] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 88.815808] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 88.815824] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 88.815833] [drm:drm_atomic_commit [drm]] committing 000000001b436c25 > [ 88.815877] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b436c25 > [ 88.815887] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b436c25 > [ 88.817733] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 88.817767] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 89.801101] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 89.801125] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 94.868102] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 94.868146] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 96.201520] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 96.201544] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 98.735069] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 98.735183] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 100.606232] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ab7d7a2 > [ 100.606285] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000009ad673f7 state to 000000009ab7d7a2 > [ 100.606333] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006047c305 state to 000000009ab7d7a2 > [ 100.606377] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000009ad673f7 to [CRTC:51:pipe A] > [ 100.606417] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009ad673f7 > [ 100.606456] [drm:drm_atomic_check_only [drm]] checking 000000009ab7d7a2 > [ 100.606598] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 100.606651] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000444592af state to 000000009ab7d7a2 > [ 100.606734] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 100.606807] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 100.606875] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 100.606943] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 100.606985] [drm:drm_atomic_commit [drm]] committing 000000009ab7d7a2 > [ 100.607113] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ab7d7a2 > [ 100.607152] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ab7d7a2 > [ 100.655506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 > [ 100.655644] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.665498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000092fcae0b > [ 100.665636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.679509] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 > [ 100.679646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.685421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000092fcae0b > [ 100.685553] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.695279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 > [ 100.695410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.705491] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000092fcae0b > [ 100.705621] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.715556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001fb03d75 > [ 100.715694] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.716246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004a0693b5 > [ 100.716379] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.725283] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 > [ 100.725478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.735276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.735410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.746365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 > [ 100.746523] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.755234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.755310] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.765226] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 > [ 100.765298] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.775291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.775412] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.785333] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cd4f0d17 > [ 100.785497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.792131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb > [ 100.792223] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.795223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.795321] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.805337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c > [ 100.805517] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.815332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.815555] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.825362] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c > [ 100.825538] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.835433] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.835644] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.845319] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c > [ 100.845456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.855444] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.855641] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.865347] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c > [ 100.865484] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.875405] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.875586] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.885342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c > [ 100.885486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.895475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.895647] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.905451] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c > [ 100.905587] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.915225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007d78e9f2 > [ 100.915349] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.925461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000033b8e22c > [ 100.925595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.935324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 100.935498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.945484] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 100.945616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.955553] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 100.955687] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.965499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 100.965634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.975545] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 100.975681] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 100.985336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 100.985468] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 101.005483] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 101.005619] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 101.035325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 101.035479] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 101.075556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 101.075692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 101.127499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 101.127634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 101.674425] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000034d78fc > [ 101.674497] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c83bd8e4 state to 00000000034d78fc > [ 101.674558] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000379a654d state to 00000000034d78fc > [ 101.674624] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c83bd8e4 to [NOCRTC] > [ 101.674681] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 101.674738] [drm:drm_atomic_check_only [drm]] checking 00000000034d78fc > [ 101.674869] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 101.674948] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007b42b813 state to 00000000034d78fc > [ 101.675042] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 101.675113] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 101.675180] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 101.675244] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 101.675287] [drm:drm_atomic_commit [drm]] committing 00000000034d78fc > [ 101.675456] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000034d78fc > [ 101.675502] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000034d78fc > [ 103.335218] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 103.335242] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 106.809611] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e4cb9fa > [ 106.809627] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000a4ba128e state to 000000009e4cb9fa > [ 106.809641] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f53352ac state to 000000009e4cb9fa > [ 106.809654] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000a4ba128e to [CRTC:51:pipe A] > [ 106.809666] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000a4ba128e > [ 106.809682] [drm:drm_atomic_check_only [drm]] checking 000000009e4cb9fa > [ 106.809728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 106.809748] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000006506bed9 state to 000000009e4cb9fa > [ 106.809786] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 106.809809] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 106.809830] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 106.809851] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 106.809864] [drm:drm_atomic_commit [drm]] committing 000000009e4cb9fa > [ 106.809912] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e4cb9fa > [ 106.809924] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e4cb9fa > [ 106.849138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 106.849192] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.859127] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 106.859181] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.869117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 106.869157] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.879122] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 106.879161] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.889116] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 106.889168] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.901127] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000077bb1be > [ 106.901174] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.907187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1034bb8 > [ 106.907228] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.917130] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 106.917175] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.927128] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 > [ 106.927179] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.937134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 106.937188] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.947131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 > [ 106.947175] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.957270] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 106.957396] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.967192] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 > [ 106.967302] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.977266] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 106.977384] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.987258] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 > [ 106.987375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 106.997153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 106.997219] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.007115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 > [ 107.007163] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.017131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 107.017170] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.027157] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 > [ 107.027207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.037124] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 > [ 107.037163] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.047167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 107.047207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.057182] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 > [ 107.057220] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.067150] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 107.067189] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.077139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 > [ 107.077188] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.087207] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 107.087243] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.097162] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 > [ 107.097194] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.107134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 107.107180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.117148] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 > [ 107.117184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.127131] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 107.127176] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.137117] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 > [ 107.137152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.147141] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 107.147178] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.147365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000035459c5a > [ 107.147421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.149200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bbab38cb > [ 107.149262] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.157134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 107.157186] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.167144] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.167207] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.177139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c739c83e > [ 107.177180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.187196] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000bd3cbac4 > [ 107.187274] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.197185] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.197235] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.207211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.207307] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.217287] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.217411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.227218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.227311] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.237176] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.237228] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.247200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.247267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.257213] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.257290] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.267196] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.267248] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.277184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.277241] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.287191] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.287262] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.297243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.297291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.309162] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.309214] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.319196] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.319256] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.329219] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.329288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.339184] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.339252] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.349153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.349191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.359123] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.359171] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.369136] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cde16ff8 > [ 107.369170] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.379109] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 107.379152] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.998833] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000056590bd0 > [ 107.998848] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000080cfc270 state to 0000000056590bd0 > [ 107.998859] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000158adbaf state to 0000000056590bd0 > [ 107.998871] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000158adbaf > [ 107.998882] [drm:drm_atomic_check_only [drm]] checking 0000000056590bd0 > [ 107.998938] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.998958] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000056590bd0 nonblocking > [ 107.998993] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006886a344 > [ 107.999004] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000bae29b57 state to 000000006886a344 > [ 107.999013] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002901bd51 state to 000000006886a344 > [ 107.999024] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000002901bd51 > [ 107.999034] [drm:drm_atomic_check_only [drm]] checking 000000006886a344 > [ 107.999072] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 107.999090] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006886a344 nonblocking > [ 108.030368] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000056590bd0 > [ 108.030383] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000056590bd0 > [ 108.035497] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006886a344 > [ 108.035511] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006886a344 > [ 112.219065] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 112.219103] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 113.003417] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e437d9b1 > [ 113.003430] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000ffeb4101 state to 00000000e437d9b1 > [ 113.003440] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c6c81551 state to 00000000e437d9b1 > [ 113.003450] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000ffeb4101 to [NOCRTC] > [ 113.003459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000ffeb4101 > [ 113.003470] [drm:drm_atomic_check_only [drm]] checking 00000000e437d9b1 > [ 113.003514] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 113.003528] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000027864345 state to 00000000e437d9b1 > [ 113.003549] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 113.003566] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 113.003582] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 113.003598] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 113.003608] [drm:drm_atomic_commit [drm]] committing 00000000e437d9b1 > [ 113.003647] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e437d9b1 > [ 113.003663] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e437d9b1 > [ 118.152150] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006ab1917d > [ 118.152201] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007f2e9b45 state to 000000006ab1917d > [ 118.152243] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000614b5ce state to 000000006ab1917d > [ 118.152286] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007f2e9b45 to [CRTC:51:pipe A] > [ 118.152323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 > [ 118.152362] [drm:drm_atomic_check_only [drm]] checking 000000006ab1917d > [ 118.152506] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 118.152561] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000e2798a03 state to 000000006ab1917d > [ 118.152644] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 118.152717] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 118.152785] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 118.152852] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 118.152896] [drm:drm_atomic_commit [drm]] committing 000000006ab1917d > [ 118.153029] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006ab1917d > [ 118.153068] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006ab1917d > [ 118.211570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 118.211702] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.221496] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fe3a22f0 > [ 118.221630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.231475] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 118.231610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.241492] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fe3a22f0 > [ 118.241626] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.251361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fb0c0a50 > [ 118.251500] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.261486] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000fe3a22f0 > [ 118.261624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.271461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.271591] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.281458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.281594] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.291544] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.291670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.301470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.301610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.311473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.311605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.321455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.321595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.331448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.331575] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.341472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.341608] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.351430] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.351563] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.361455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.361597] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.371478] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.371609] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.381444] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.381580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.391455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.391584] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.401319] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.401459] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.411530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.411658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.421455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.421593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.431467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000db85fe38 > [ 118.431595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.432097] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000009bdf158a > [ 118.432246] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.436826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f2e9b45 > [ 118.436961] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.441244] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.441371] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.451290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.451442] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.461385] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.461544] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.471242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.471340] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.481218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.481297] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.491325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.491469] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.501336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.501464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.511201] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.511286] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.521282] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.521422] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.531256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.531363] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.541365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.541527] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.551421] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.551612] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.561422] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.561626] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.571460] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.571668] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.581305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.581436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.591429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.591614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.601286] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.601427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.611450] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.611595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.621470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 118.621606] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 118.631489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 118.631623] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 119.225511] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000685c0b37 > [ 119.225580] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000007880e175 state to 00000000685c0b37 > [ 119.225622] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000005a9a925a state to 00000000685c0b37 > [ 119.225664] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000007880e175 to [NOCRTC] > [ 119.225701] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000007880e175 > [ 119.225739] [drm:drm_atomic_check_only [drm]] checking 00000000685c0b37 > [ 119.225870] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 119.225921] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001da1458b state to 00000000685c0b37 > [ 119.226002] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 119.226072] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 119.226138] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 119.226202] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 119.226243] [drm:drm_atomic_commit [drm]] committing 00000000685c0b37 > [ 119.226379] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000685c0b37 > [ 119.226421] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000685c0b37 > [ 122.315481] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006886a344 > [ 122.315493] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000000568d4c state to 000000006886a344 > [ 122.315503] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000c0a9ee8 state to 000000006886a344 > [ 122.315525] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000000568d4c to [CRTC:51:pipe A] > [ 122.315533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000000568d4c > [ 122.315541] [drm:drm_atomic_check_only [drm]] checking 000000006886a344 > [ 122.315580] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 122.315596] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000009bed8e52 state to 000000006886a344 > [ 122.315616] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 122.315631] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 122.315646] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 122.315660] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 122.315669] [drm:drm_atomic_commit [drm]] committing 000000006886a344 > [ 122.315710] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006886a344 > [ 122.315722] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006886a344 > [ 122.375447] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.375512] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.385420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.385514] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.395457] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.395593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.405500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.405638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.415533] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.415670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.425503] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.425638] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.435376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.435507] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.445489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.445628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.455488] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.455625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.465493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.465631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.475551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.475684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.485474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.485611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.495551] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.495684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.505507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.505645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.515543] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.515675] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.525494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.525624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.535385] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.535515] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.545498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000b4820d38 > [ 122.545633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.546132] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000004af5af33 > [ 122.546275] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.550766] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e272cbfd > [ 122.550966] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.555297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.555491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.565289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.565468] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.575437] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.575649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.585311] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.585474] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.595309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.595486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.605288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.605465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.615395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.615532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.625404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.625565] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.635310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.635442] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.645367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.645525] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.655318] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.655370] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.665309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.665417] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.675298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.675415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.685454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.685679] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.695368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.695517] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.705448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.705645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.715392] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.715588] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.725438] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.725646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.735369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.735505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.745500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.745640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.755529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.755663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.765337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.765470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.775249] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.775378] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.785251] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.785375] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.805153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000059a22abe > [ 122.805208] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 122.825138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 122.825177] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 123.640446] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000daeee49c > [ 123.640511] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000002bd9c591 state to 00000000daeee49c > [ 123.640555] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007c9cb52f state to 00000000daeee49c > [ 123.640597] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000002bd9c591 to [NOCRTC] > [ 123.640633] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 000000002bd9c591 > [ 123.640671] [drm:drm_atomic_check_only [drm]] checking 00000000daeee49c > [ 123.640810] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 123.640865] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000c94fae9e state to 00000000daeee49c > [ 123.640957] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 123.641028] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 123.641095] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 123.641172] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 123.641213] [drm:drm_atomic_commit [drm]] committing 00000000daeee49c > [ 123.641343] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000daeee49c > [ 123.641384] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000daeee49c > [ 141.078241] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005f403807 > [ 141.078301] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000037fd6bb5 state to 000000005f403807 > [ 141.078343] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d785a3ff state to 000000005f403807 > [ 141.078387] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000037fd6bb5 to [CRTC:51:pipe A] > [ 141.078425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000037fd6bb5 > [ 141.078464] [drm:drm_atomic_check_only [drm]] checking 000000005f403807 > [ 141.078605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 141.078659] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cf223f59 state to 000000005f403807 > [ 141.078742] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 141.078815] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 141.078884] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 141.078951] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 141.078994] [drm:drm_atomic_commit [drm]] committing 000000005f403807 > [ 141.079121] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005f403807 > [ 141.079161] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005f403807 > [ 141.107538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.107620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.117497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.117630] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.127474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.127612] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.137491] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.137625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.147568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.147705] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.157364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.157499] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.167567] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.167705] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.177487] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.177624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.187485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.187617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.193485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.193628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.203485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.203622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.214506] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.214643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.223478] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.223611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.233209] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.233263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.243516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.243588] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.253441] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.253542] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.263521] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.263656] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.275556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.275692] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.285356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.285495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.295568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.295709] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.305494] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.305633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.315515] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.315648] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.325495] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000347b066 > [ 141.325631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.335367] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cea88f98 > [ 141.335505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.345454] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000007f9d2c54 > [ 141.345586] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.346101] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e7418dfc > [ 141.346276] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.355141] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cea88f98 > [ 141.355189] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.365147] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb > [ 141.365194] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.375197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000cea88f98 > [ 141.375275] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.380369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000001c7ca7f0 > [ 141.380409] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.385246] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb > [ 141.385295] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.395288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 141.395358] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.405301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb > [ 141.405362] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.415276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000002a4c0c42 > [ 141.415341] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.425309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000010907adb > [ 141.425390] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.435298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e > [ 141.435413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.445404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 > [ 141.445562] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.455423] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e > [ 141.455581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.465409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 > [ 141.465566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.475410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e > [ 141.475566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.485376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 > [ 141.485535] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.495337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e > [ 141.495482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.505402] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 > [ 141.505569] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.515416] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e > [ 141.515598] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.525379] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 > [ 141.525533] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.535346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 0000000062c10d1e > [ 141.535521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.545387] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000d1345d52 > [ 141.545546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 141.616461] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 > [ 141.616535] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000036a79273 state to 00000000f9a25c26 > [ 141.616600] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001a688f4f state to 00000000f9a25c26 > [ 141.616671] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000036a79273 to [NOCRTC] > [ 141.616734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000036a79273 > [ 141.616797] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 > [ 141.616990] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 141.617070] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000000347b066 state to 00000000f9a25c26 > [ 141.617214] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 141.617361] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 141.617502] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 141.617642] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 141.617718] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 > [ 141.617930] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 > [ 141.618018] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 > [ 142.420971] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 142.421067] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 162.373184] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 > [ 162.373240] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 000000000446d08f state to 00000000f9a25c26 > [ 162.373284] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000f53352ac state to 00000000f9a25c26 > [ 162.373326] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 000000000446d08f to [CRTC:51:pipe A] > [ 162.373364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000000446d08f > [ 162.373405] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 > [ 162.373543] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 162.373604] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031204d92 state to 00000000f9a25c26 > [ 162.373687] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 162.373759] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 162.373828] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 162.373895] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 162.373938] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 > [ 162.374065] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 > [ 162.374105] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 > [ 162.412539] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.412677] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.422500] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.422637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.432369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.432523] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.442503] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.442633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.452374] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.452534] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.462502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.462639] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.472522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.472657] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.482493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.482629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.492573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.492706] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.502330] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.502470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.512587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.512722] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.524571] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.524709] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.534493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.534628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.544376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.544545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.554495] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.554628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.564566] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000e8729617 > [ 162.564705] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.565166] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000587edb49 > [ 162.565305] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.569116] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000eb35d02a > [ 162.569249] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.574136] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.574187] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.584146] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.584195] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.594234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.594303] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.604214] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.604270] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.614257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.614315] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.624366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.624535] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.634314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.634358] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.644386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.644533] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.654324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.654411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.664456] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.664686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.674345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.674484] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.684450] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.684647] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.696485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.696691] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.702435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.702636] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.712353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.712616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.722404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.722602] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.732474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.732733] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.742357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.742494] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.752401] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.752654] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.762467] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.762603] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.772538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.772670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.782490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 000000003471b0c5 > [ 162.782619] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.792604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:47:cursor A] state 00000000c83bd8e4 > [ 162.792735] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.792821] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039732f38 > [ 162.792870] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000077bb1be state to 0000000039732f38 > [ 162.792916] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000005e067cfa state to 0000000039732f38 > [ 162.792960] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000077bb1be to [CRTC:72:pipe B] > [ 162.793002] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000077bb1be > [ 162.793047] [drm:drm_atomic_check_only [drm]] checking 0000000039732f38 > [ 162.793170] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 0 -> 1, off 0, on 1, ms 0 > [ 162.793229] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000024b64037 state to 0000000039732f38 > [ 162.793312] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 162.793386] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 162.793457] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 162.793529] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 162.793574] [drm:drm_atomic_commit [drm]] committing 0000000039732f38 > [ 162.793714] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039732f38 > [ 162.793764] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039732f38 > [ 162.794202] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005fdb65d > [ 162.794252] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 00000000c739c83e state to 0000000005fdb65d > [ 162.794296] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b35cdb13 state to 0000000005fdb65d > [ 162.794338] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 00000000c739c83e to [NOCRTC] > [ 162.794375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 00000000c739c83e > [ 162.794414] [drm:drm_atomic_check_only [drm]] checking 0000000005fdb65d > [ 162.794531] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 162.794581] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000cf223f59 state to 0000000005fdb65d > [ 162.794662] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 162.794735] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 162.794802] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 162.794869] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 162.794912] [drm:drm_atomic_commit [drm]] committing 0000000005fdb65d > [ 162.795027] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005fdb65d > [ 162.795069] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005fdb65d > [ 162.795125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 > [ 162.795237] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.802263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 162.802383] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.812558] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 > [ 162.812693] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.826474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 162.826607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.836357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 > [ 162.836524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.837177] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000ffeb4101 > [ 162.837329] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.841039] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 > [ 162.841094] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000006723bfc6 state to 00000000f9a25c26 > [ 162.841132] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 > [ 162.841187] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031204d92 state to 00000000f9a25c26 > [ 162.841230] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 > [ 162.850260] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 > [ 162.850315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 162.850349] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 > [ 162.850478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 162.850548] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a25c26 > [ 162.850590] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000164d9b7a state to 00000000f9a25c26 > [ 162.850622] [drm:drm_atomic_check_only [drm]] checking 00000000f9a25c26 > [ 162.850668] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000eb35d02a state to 00000000f9a25c26 > [ 162.850706] [drm:drm_atomic_commit [drm]] committing 00000000f9a25c26 > [ 162.855668] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a25c26 > [ 162.855724] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a25c26 > [ 163.084554] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.084691] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.094298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 163.094430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.104289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.104429] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.114472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 163.114610] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.124320] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.124457] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.134242] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 163.134366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.144247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.144371] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.154294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 163.154423] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.164304] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.164446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.174288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:133] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 163.174420] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.174937] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000209127dd > [ 163.175089] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.179030] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.179083] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000010dc5853 state to 00000000be7b5d5a > [ 163.179121] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.179173] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007bfc2d05 state to 00000000be7b5d5a > [ 163.179219] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.183630] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.183680] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.183762] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.183810] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c0b4aeaa state to 00000000be7b5d5a > [ 163.183846] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.183895] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002901bd51 state to 00000000be7b5d5a > [ 163.183938] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.188875] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.188930] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.189059] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.189102] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.190572] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.190623] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000000c0a9ee8 state to 00000000be7b5d5a > [ 163.190661] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.190712] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000bd435351 state to 00000000be7b5d5a > [ 163.190754] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.200278] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.200329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 163.200462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.200504] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.200614] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.200675] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000025c16090 state to 00000000be7b5d5a > [ 163.200708] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.200755] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007bfc2d05 state to 00000000be7b5d5a > [ 163.200795] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.205520] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.205574] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.205697] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.205740] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.214356] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 163.214554] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.224571] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.224821] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.234254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 163.234361] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.244345] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.244519] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.254382] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 163.254560] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.264229] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 163.264326] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.280340] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b4820d38 > [ 163.280404] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.282204] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000001da1458b > [ 163.282256] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.284167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 163.284205] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.344181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.344296] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.364377] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.364426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.384493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.384575] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.394307] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.394438] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.404254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.404369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.414256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.414374] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.424270] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.424393] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.434269] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.434392] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.444299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.444435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.454316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.454440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.464222] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.464313] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.474216] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.474278] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.484241] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.484286] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.494263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.494347] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.504245] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.504314] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.514209] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.514276] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.524212] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.524268] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.534243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.534290] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.544309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:139] for [PLANE:68:cursor B] state 00000000012b5110 > [ 163.544448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.552285] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007b42b813 > [ 163.552334] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.554208] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.554281] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.564224] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 163.564295] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.574166] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.574229] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.584233] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 163.584288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.594160] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.594238] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.604200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 163.604269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.614168] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.614216] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.616918] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.616952] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000bae29b57 state to 00000000be7b5d5a > [ 163.616971] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.617000] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002901bd51 state to 00000000be7b5d5a > [ 163.617023] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.633795] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.633819] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.633836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 163.633879] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.633938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.633954] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 0000000080cfc270 state to 00000000be7b5d5a > [ 163.633966] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.633988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000bd435351 state to 00000000be7b5d5a > [ 163.634002] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.638759] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.638776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.638830] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.638849] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.641820] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.641848] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000010dc5853 state to 00000000be7b5d5a > [ 163.641866] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.641894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007bfc2d05 state to 00000000be7b5d5a > [ 163.641919] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.650229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.650244] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.650260] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 163.650301] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.650356] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000be7b5d5a > [ 163.650372] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c0b4aeaa state to 00000000be7b5d5a > [ 163.650384] [drm:drm_atomic_check_only [drm]] checking 00000000be7b5d5a > [ 163.650401] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000002901bd51 state to 00000000be7b5d5a > [ 163.650414] [drm:drm_atomic_commit [drm]] committing 00000000be7b5d5a > [ 163.655440] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000be7b5d5a > [ 163.655459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000c82f2a13 > [ 163.655472] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000be7b5d5a > [ 163.655522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.664185] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 > [ 163.664267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.674174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 163.674227] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.684271] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 > [ 163.684368] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.694235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 163.694314] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.716235] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 > [ 163.716316] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.746263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 163.746311] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.786322] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 163.786444] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.796558] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 163.796732] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.806376] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 163.806516] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.816289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 163.816430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.824360] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 163.824500] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.834302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 163.834431] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.844210] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 163.844334] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.854306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 163.854429] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.864293] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 163.864421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.874316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cea88f98 > [ 163.874446] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.894337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cde16ff8 > [ 163.894471] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.904283] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 163.904433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.914493] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 163.914633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.924325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 163.924456] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.934489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 163.934625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.944593] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 163.944734] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.953688] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bd435351 > [ 163.953820] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.954247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 163.954361] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.974321] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f > [ 163.974458] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 163.994386] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 163.994437] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.002341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000825c5808 > [ 164.002399] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.014429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 164.014487] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.044329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 164.044410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.214575] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 164.214713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.264599] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 164.264739] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.374516] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 164.374649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.393776] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb > [ 164.393946] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.394313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000db85fe38 > [ 164.394431] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.434448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000002a4c0c42 > [ 164.434584] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.554295] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000db85fe38 > [ 164.554421] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 164.564820] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bbab38cb > [ 164.564985] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 165.034734] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005fdb65d > [ 165.034787] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000001450a92b state to 0000000005fdb65d > [ 165.034827] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000007a36128c state to 0000000005fdb65d > [ 165.034869] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000007a36128c > [ 165.034909] [drm:drm_atomic_check_only [drm]] checking 0000000005fdb65d > [ 165.035059] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 165.035120] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000005fdb65d nonblocking > [ 165.035217] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000023b91fcc > [ 165.035276] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000003cd98772 state to 0000000023b91fcc > [ 165.035334] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000db85fe38 state to 0000000023b91fcc > [ 165.035381] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000db85fe38 > [ 165.035417] [drm:drm_atomic_check_only [drm]] checking 0000000023b91fcc > [ 165.035581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 165.035648] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000023b91fcc nonblocking > [ 165.066992] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005fdb65d > [ 165.067043] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005fdb65d > [ 165.072198] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000023b91fcc > [ 165.072271] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000023b91fcc > [ 165.186505] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 165.186637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 165.193125] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d4543e4a > [ 165.193254] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 165.226330] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006506bed9 > [ 165.226461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 165.559366] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000922e52d2 > [ 165.559409] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.198591] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.198728] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.208274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.208427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.218301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.218420] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.228529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.228668] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.238482] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.238613] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.248312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.248448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.258354] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.258495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.268277] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.268411] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.278371] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.278499] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.288245] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.288379] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.298279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.298399] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.308485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.308661] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.318507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.318641] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.328332] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.328470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.338492] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.338629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.348315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.348443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.358336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.358482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.368340] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.368476] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.378281] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.378408] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.388609] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.388746] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.398501] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.398637] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.408591] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.408735] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.418335] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.418467] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.428298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.428427] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.438508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.438645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.448320] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.448451] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.458413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.458546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.468336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.468471] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.478286] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.478413] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.488310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.488437] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.498485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.498618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.508309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 166.508436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.510409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000009ad673f7 > [ 166.510568] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.518309] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.518443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.528202] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.528279] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.538201] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f > [ 166.538251] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.548174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 166.548225] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.558268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 166.558443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.568325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 166.568466] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.578325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 166.578461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.588292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 166.588425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.598243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 166.598339] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.608234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 166.608325] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.618305] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 166.618440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.628243] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 166.628370] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.638472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 166.638607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.648346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 166.648472] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.658304] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007f9d2c54 > [ 166.658435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.668200] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.668266] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.678440] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 166.678510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.688538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.688612] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.698392] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 166.698462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.718507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.718644] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.738502] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 166.738635] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.798352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.798491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.918347] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 166.918485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.928302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.928430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.938357] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 166.938493] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.948336] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.948520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.958328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 166.958461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.968326] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.968512] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.980579] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 166.980746] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 166.990348] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 166.990503] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.000335] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.000513] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.010297] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 167.010432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.020339] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.020482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.030319] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 167.030478] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.040275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.040405] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.048710] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000009bed8e52 > [ 167.048845] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.050289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 167.050415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.060268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.060398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.070294] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 167.070384] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.080251] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.080344] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.088239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a2ffc292 > [ 167.088330] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.098201] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001da1458b > [ 167.098336] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.098523] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.098643] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.108239] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f > [ 167.108334] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.118273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.118405] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.128501] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004b4b904f > [ 167.128614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.131207] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000009aed900f > [ 167.131301] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.138279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.138369] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.148267] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 167.148366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.158284] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.158410] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.168298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 167.168438] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.178446] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 167.178586] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.188561] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 167.188697] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.198352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 167.198491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.208264] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 167.208388] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.218455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 167.218593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.228299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 167.228428] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.238268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 167.238390] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.248278] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 167.248403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.258438] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 167.258577] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.268293] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 167.268425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.278483] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 167.278616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.288588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 167.288718] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.298353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 167.298492] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.305607] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 167.305696] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 167.308291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.308419] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.318288] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 167.318416] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.338474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000004f41ae90 > [ 167.338607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.358489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000006506bed9 > [ 167.358625] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 167.418431] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 167.418566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 169.189257] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 169.189356] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 170.722681] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 170.722781] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 174.105940] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 174.105971] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 177.239718] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 177.239826] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 179.073151] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 179.073248] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 179.539621] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 179.539709] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 180.939876] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 181.556405] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 181.556493] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 183.573184] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 183.573274] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 184.723475] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 184.723574] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 185.023495] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 185.023591] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 186.190028] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 186.190120] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 186.806925] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 186.807022] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 187.140278] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 187.140374] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 188.556970] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 188.557072] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 196.710472] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.710606] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.720275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.720400] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.730361] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.730503] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.740292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.740426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.750290] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.750418] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.760164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.760206] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.770148] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.770206] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.780499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.780634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.790477] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.790611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.810349] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.810482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.820270] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.820399] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.830365] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.830507] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.840325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.840459] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.850300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.850424] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.860274] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.860395] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.870281] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.870401] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.880273] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.880397] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.890286] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.890412] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.900295] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.900423] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.910278] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.910406] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.920282] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.920403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.940275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.940403] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.960275] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 196.960398] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 196.980269] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 196.980395] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 197.000256] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 197.000379] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 197.020490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 197.020629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 197.030324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 197.030452] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 197.490874] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 197.490997] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 198.357316] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 198.357343] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 198.840664] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 198.840681] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 199.324033] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 199.324062] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 199.354350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b9b497e2 > [ 199.354389] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 201.057610] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 201.057742] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 202.691169] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 202.691299] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 204.448344] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 > [ 204.448482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.458388] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c > [ 204.458526] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.465902] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 > [ 204.466039] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.468343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f62f4859 > [ 204.468525] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.478222] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b30bcde6 > [ 204.478278] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.488310] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f62f4859 > [ 204.488357] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.498181] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b30bcde6 > [ 204.498258] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.498534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000a3057dc4 > [ 204.498581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.508268] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 > [ 204.508329] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.518263] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b30bcde6 > [ 204.518345] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.528507] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 > [ 204.528590] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.538373] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b30bcde6 > [ 204.538504] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.548353] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000f62f4859 > [ 204.548526] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.548878] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007696cdb5 > [ 204.548996] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.558432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b30bcde6 > [ 204.558479] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.565739] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000004ca3e431 > [ 204.565873] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.568331] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c > [ 204.568454] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.578458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006912db03 > [ 204.578593] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.588351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c > [ 204.588486] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.598370] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006912db03 > [ 204.598509] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.608300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000e0be749c > [ 204.608432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.615008] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fe3a22f0 > [ 204.615136] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.618338] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cf223f59 > [ 204.618500] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.628289] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000037fd6bb5 > [ 204.628417] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.632195] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffeb4101 > [ 204.632327] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.648396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 > [ 204.648566] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.658313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 204.658447] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.678279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 > [ 204.678409] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.698323] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 204.698464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.718329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 > [ 204.718469] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.738316] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000dcf9b2a1 > [ 204.738448] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.748362] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 204.748492] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.768326] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000922e52d2 > [ 204.768453] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.778287] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 204.778414] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.788473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000922e52d2 > [ 204.788600] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.798291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001acc1fa3 > [ 204.798419] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.808487] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000922e52d2 > [ 204.808618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.815138] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 0000000092affbec > [ 204.815294] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.818341] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cf223f59 > [ 204.818524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.828359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b9f6ed2f > [ 204.828545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.838330] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000cf223f59 > [ 204.838469] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.848390] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b9f6ed2f > [ 204.848541] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.848960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cd4c0663 > [ 204.849109] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.858312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000006912db03 > [ 204.858447] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.868343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cf223f59 > [ 204.868480] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.878307] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007445155b > [ 204.878441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.881982] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 204.882116] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.888331] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b > [ 204.888465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.898303] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 204.898440] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.908318] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b > [ 204.908451] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.918320] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 204.918450] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.938328] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b > [ 204.938465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.958470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 204.958605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.978352] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b > [ 204.978491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 204.998371] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 204.998556] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.001389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 205.001522] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.018351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000007445155b > [ 205.018532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.038351] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000444592af > [ 205.038481] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.068339] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.068479] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.088481] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf > [ 205.088617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.108530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.108662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.128532] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf > [ 205.128669] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.148343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.148521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.168306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf > [ 205.168443] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.188473] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.188611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.208542] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf > [ 205.208683] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.230360] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.230498] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.246443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d5a342cf > [ 205.246622] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.265397] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000a3057dc4 > [ 205.265563] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.266346] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.266465] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.286348] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003cdbbe01 > [ 205.286489] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.306389] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.306531] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.330329] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003cdbbe01 > [ 205.330464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.348313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ffb1c30d > [ 205.348467] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.348956] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bd435351 > [ 205.349098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.379469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003cdbbe01 > [ 205.379605] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.418302] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000919acba8 > [ 205.418470] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.468395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003cdbbe01 > [ 205.468531] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.481838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007a57587a > [ 205.481983] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.798479] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000919acba8 > [ 205.798617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.803775] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000209127dd > [ 205.803902] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.858576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 > [ 205.858713] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.891292] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 205.891418] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 205.898383] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb > [ 205.898521] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 205.958585] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 > [ 205.958718] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 206.098587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb > [ 206.098727] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 206.640585] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 > [ 206.640683] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 206.700510] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000bbab38cb > [ 206.700648] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 206.770448] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000701cb2c7 > [ 206.770585] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 207.053512] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 207.053611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 207.310459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000007445155b > [ 207.310589] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 209.041306] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 209.041387] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 209.124871] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 209.125001] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 209.241320] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 209.241452] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 211.658353] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 211.658482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 213.091482] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 213.091505] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 213.625128] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 213.625263] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 217.492020] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 217.492164] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 223.609034] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 223.609177] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 226.792505] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 226.792643] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 231.176075] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 231.176218] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 231.542819] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 231.542950] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 231.976181] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 231.976317] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 237.426491] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 237.426628] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 238.293205] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 238.293327] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 239.576613] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 239.576751] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 242.443341] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 242.443474] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 244.510032] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 246.593680] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 246.593814] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 247.943758] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 247.943891] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 248.310445] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 248.310575] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 257.060944] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 257.061081] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 264.077820] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 264.077959] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 266.428065] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 266.428196] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 270.261496] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 270.261629] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 271.428241] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 275.562001] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 275.562106] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 276.595394] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 276.595493] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 281.612158] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 281.612255] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 288.579413] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 288.579517] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 292.596309] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 292.596419] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 296.546344] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 296.546450] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 297.446586] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 297.446682] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 299.696715] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 299.696817] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 300.246745] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 300.246841] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 301.763500] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 301.763596] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 302.113314] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 302.113407] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 303.296919] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 303.297018] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 304.513662] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 304.513760] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 307.330490] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 307.330600] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 310.580465] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 310.580565] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 316.297662] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 316.297769] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 317.047628] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 317.047703] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 319.697854] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 319.697958] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 321.647745] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 321.647843] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 322.764591] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 322.764694] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 323.781427] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 323.781524] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 323.831427] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 323.831523] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 326.231565] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 326.231663] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 329.281738] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 329.281845] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 329.948253] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 329.948347] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 331.298519] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 331.298616] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 333.331975] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 333.332082] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 334.795068] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000072ce196 > [ 334.795080] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007b516bb0 state to 00000000072ce196 > [ 334.795091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000b9f6ed2f state to 00000000072ce196 > [ 334.795101] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 00000000b9f6ed2f > [ 334.795110] [drm:drm_atomic_check_only [drm]] checking 00000000072ce196 > [ 334.795147] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 334.795163] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000072ce196 nonblocking > [ 334.795210] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000030d0d581 > [ 334.795220] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000d785a3ff state to 0000000030d0d581 > [ 334.795228] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 000000007c47dfc7 state to 0000000030d0d581 > [ 334.795237] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 000000007c47dfc7 > [ 334.795246] [drm:drm_atomic_check_only [drm]] checking 0000000030d0d581 > [ 334.795312] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 334.795325] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000030d0d581 nonblocking > [ 334.815151] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000030d0d581 > [ 334.815167] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000030d0d581 > [ 334.826605] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000072ce196 > [ 334.826620] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000072ce196 > [ 335.194808] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a311e694 > [ 335.194821] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000c56546ad state to 00000000a311e694 > [ 335.194830] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000031204d92 state to 00000000a311e694 > [ 335.194840] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 0000000031204d92 > [ 335.194848] [drm:drm_atomic_check_only [drm]] checking 00000000a311e694 > [ 335.194907] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 335.194924] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a311e694 nonblocking > [ 335.194961] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ca04647c > [ 335.194970] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000002822e6ce state to 00000000ca04647c > [ 335.194978] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000bd3cbac4 state to 00000000ca04647c > [ 335.194987] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 00000000bd3cbac4 > [ 335.194995] [drm:drm_atomic_check_only [drm]] checking 00000000ca04647c > [ 335.195025] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 335.195043] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ca04647c nonblocking > [ 335.215172] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ca04647c > [ 335.215186] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ca04647c > [ 335.226657] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a311e694 > [ 335.226670] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a311e694 > [ 338.015377] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 338.015451] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 339.415470] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 339.944709] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055a34068 > [ 339.944724] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 0000000080cfc270 state to 0000000055a34068 > [ 339.944736] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000059907653 state to 0000000055a34068 > [ 339.944748] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:31:plane 1A] state 0000000059907653 > [ 339.944762] [drm:drm_atomic_check_only [drm]] checking 0000000055a34068 > [ 339.944816] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 339.944835] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000055a34068 nonblocking > [ 339.944878] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005d1b0ba1 > [ 339.944889] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000c0b4aeaa state to 000000005d1b0ba1 > [ 339.944900] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000b467cabb state to 000000005d1b0ba1 > [ 339.944911] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:138] for [PLANE:52:plane 1B] state 00000000b467cabb > [ 339.944921] [drm:drm_atomic_check_only [drm]] checking 000000005d1b0ba1 > [ 339.944970] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 339.944985] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005d1b0ba1 nonblocking > [ 339.965419] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005d1b0ba1 > [ 339.965435] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005d1b0ba1 > [ 339.976869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055a34068 > [ 339.976882] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055a34068 > [ 340.092434] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fd9f3f13 > [ 340.092486] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000007c9cb52f state to 00000000fd9f3f13 > [ 340.092526] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000001fb03d75 state to 00000000fd9f3f13 > [ 340.092568] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:31:plane 1A] state 000000001fb03d75 > [ 340.092607] [drm:drm_atomic_check_only [drm]] checking 00000000fd9f3f13 > [ 340.092794] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:31:plane 1A] visible 1 -> 1, off 0, on 0, ms 0 > [ 340.092869] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fd9f3f13 nonblocking > [ 340.092992] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000026cdbbf8 > [ 340.093031] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000b21b516a state to 0000000026cdbbf8 > [ 340.093066] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000068ed95b2 state to 0000000026cdbbf8 > [ 340.093105] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:137] for [PLANE:52:plane 1B] state 0000000068ed95b2 > [ 340.093140] [drm:drm_atomic_check_only [drm]] checking 0000000026cdbbf8 > [ 340.093266] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:52:plane 1B] visible 1 -> 1, off 0, on 0, ms 0 > [ 340.093323] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000026cdbbf8 nonblocking > [ 340.110397] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fd9f3f13 > [ 340.110444] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fd9f3f13 > [ 340.115690] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000026cdbbf8 > [ 340.115773] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000026cdbbf8 > [ 342.565703] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 342.565827] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 344.599279] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 344.599405] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 345.965958] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 345.966085] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 348.116149] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 348.116281] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 350.132928] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 350.133053] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 353.932944] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 353.933067] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 355.183111] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 355.183235] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 357.383343] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 357.383471] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 357.516488] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 357.516606] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 360.083402] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 360.083527] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 360.333317] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 360.333438] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 360.666861] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 360.666983] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 362.883659] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 362.883789] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 376.551105] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 376.551238] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 377.984452] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 377.984580] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 380.084572] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 380.084705] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 380.817966] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 380.818094] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 380.934689] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 380.934810] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 381.668065] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 381.668189] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 383.218154] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 383.218287] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 383.684846] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 383.684968] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 384.183653] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000000b4adf6f > [ 384.183785] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.193259] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f5a85039 > [ 384.193310] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.203350] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000000b4adf6f > [ 384.203414] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.213293] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f5a85039 > [ 384.213382] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.223412] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.223549] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.234408] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 384.234546] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.243375] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.243509] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.253548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 384.253686] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.263372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.263503] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.273419] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 384.273558] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.283420] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.283559] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.303397] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 384.303525] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.323391] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.323524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.333300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 384.333424] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.343528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.343663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.353374] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 384.353505] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.363343] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.363467] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.373404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000fd13abdd > [ 384.373544] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 384.383515] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000bd3cbac4 > [ 384.383652] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 386.118054] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 386.118095] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 386.368064] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 386.368086] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 386.534738] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 386.534760] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 386.851505] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 386.851579] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 387.034830] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 387.034903] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 387.201648] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 387.201751] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 388.535123] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 388.535222] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080 > [ 389.151261] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003441ac2c > [ 389.151332] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.161368] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d5b9564c > [ 389.161497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.171380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003441ac2c > [ 389.171520] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.181354] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d5b9564c > [ 389.181483] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.191360] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 000000003441ac2c > [ 389.191491] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.201291] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000d5b9564c > [ 389.201415] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.204571] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cde16ff8 > [ 389.204695] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.211441] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003441ac2c > [ 389.211573] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.221362] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ac527557 > [ 389.221497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.231523] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003441ac2c > [ 389.231660] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.241534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000ac527557 > [ 389.241670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.251526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000003441ac2c > [ 389.251654] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.255414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000f4b6c622 > [ 389.255545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.262582] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ac527557 > [ 389.262716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.271369] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000b9b497e2 > [ 389.271499] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.281579] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:68:cursor B] state 00000000ac527557 > [ 389.281715] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.282180] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000001e50d1f1 > [ 389.282317] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.291370] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b9b497e2 > [ 389.291497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.301572] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d269f013 > [ 389.301701] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.311529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000b9b497e2 > [ 389.311664] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.321434] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000d269f013 > [ 389.321571] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.331543] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db481eed > [ 389.331593] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000060e05122 state to 00000000db481eed > [ 389.331636] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 000000008ce8e041 state to 00000000db481eed > [ 389.331678] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000060e05122 to [CRTC:51:pipe A] > [ 389.331717] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 0000000060e05122 > [ 389.331756] [drm:drm_atomic_check_only [drm]] checking 00000000db481eed > [ 389.331893] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 0 -> 1, off 0, on 1, ms 0 > [ 389.331947] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 000000002bd9c591 state to 00000000db481eed > [ 389.332030] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm -> *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm > [ 389.332103] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 0, 3, 4, 5, 9, 11, 12, 14, 0 > [ 389.332171] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 10, 10, 10, 12, 20, 24, 26, 30, 0 > [ 389.332238] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 0, 0, 0, 0, 0, 0, 0, 0, 0 -> 11, 11, 11, 13, 21, 25, 27, 31, 0 > [ 389.332281] [drm:drm_atomic_commit [drm]] committing 00000000db481eed > [ 389.332422] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db481eed > [ 389.332462] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db481eed > [ 389.332519] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 00000000cd4c0663 > [ 389.332629] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.333062] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000c13c0ab2 > [ 389.333180] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.333247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:134] for [PLANE:68:cursor B] state 000000009ad771e5 > [ 389.333357] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.335824] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006ab1917d > [ 389.335880] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000d7bb92f2 state to 000000006ab1917d > [ 389.335918] [drm:drm_atomic_check_only [drm]] checking 000000006ab1917d > [ 389.335975] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 00000000ed23d599 state to 000000006ab1917d > [ 389.336020] [drm:drm_atomic_commit [drm]] committing 000000006ab1917d > [ 389.346611] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006ab1917d > [ 389.346667] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000d269f013 > [ 389.346799] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.346842] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006ab1917d > [ 389.346940] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db481eed > [ 389.346985] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:68:cursor B] 00000000c94fae9e state to 00000000db481eed > [ 389.347024] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 000000007c9cb52f state to 00000000db481eed > [ 389.347066] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:68:cursor B] state 00000000c94fae9e to [NOCRTC] > [ 389.347102] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:68:cursor B] state 00000000c94fae9e > [ 389.347142] [drm:drm_atomic_check_only [drm]] checking 00000000db481eed > [ 389.347272] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:72:pipe B] with [PLANE:68:cursor B] visible 1 -> 0, off 1, on 0, ms 0 > [ 389.347323] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 00000000ffeb4101 state to 00000000db481eed > [ 389.347412] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 389.347484] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 389.347552] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 389.347620] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:68:cursor B] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 389.347663] [drm:drm_atomic_commit [drm]] committing 00000000db481eed > [ 389.347798] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db481eed > [ 389.347857] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fd4b06be > [ 389.347893] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db481eed > [ 389.347949] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:72:pipe B] 00000000925d662a state to 00000000fd4b06be > [ 389.347989] [drm:drm_atomic_check_only [drm]] checking 00000000fd4b06be > [ 389.348040] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:52:plane 1B] 0000000007ebffa5 state to 00000000fd4b06be > [ 389.348083] [drm:drm_atomic_commit [drm]] committing 00000000fd4b06be > [ 389.351742] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fd4b06be > [ 389.351790] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fd4b06be > [ 389.353402] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.353595] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.360773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 0000000067b08824 > [ 389.360912] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.363314] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.363441] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.373413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.373563] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.383342] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.383433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.393312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.393383] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.403313] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.403384] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.413444] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.413617] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.423299] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.423376] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.433429] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.433579] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.443324] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.443433] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.453396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.453524] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.463485] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.463715] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.473438] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.473575] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.483524] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.483759] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.493424] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.493554] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.503451] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.503650] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.513409] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.513542] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.523461] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.523649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.533584] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.533720] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.543529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.543665] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.553561] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.553691] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.563508] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.563642] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.573564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.573700] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.583443] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.583581] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.593579] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.593715] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.603525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.603661] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.613565] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.613694] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.623535] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.623669] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.633570] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.633699] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.643522] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.643655] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.653590] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.653773] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.663513] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.663650] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.673585] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 00000000b30bcde6 > [ 389.673721] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 389.733576] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:142] for [PLANE:47:cursor A] state 000000006912db03 > [ 389.733708] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 1, off 0, on 0, ms 0 > [ 390.576434] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000db481eed > [ 390.576484] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:47:cursor A] 0000000068ed95b2 state to 00000000db481eed > [ 390.576527] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:51:pipe A] 00000000b21b516a state to 00000000db481eed > [ 390.576569] [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:47:cursor A] state 0000000068ed95b2 to [NOCRTC] > [ 390.576607] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:47:cursor A] state 0000000068ed95b2 > [ 390.576645] [drm:drm_atomic_check_only [drm]] checking 00000000db481eed > [ 390.576784] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:51:pipe A] with [PLANE:47:cursor A] visible 1 -> 0, off 1, on 0, ms 0 > [ 390.576837] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 1A] 0000000039b49928 state to 00000000db481eed > [ 390.576921] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] level *wm0,*wm1,*wm2,*wm3,*wm4,*wm5,*wm6,*wm7, twm -> wm0, wm1, wm2, wm3, wm4, wm5, wm6, wm7, twm > [ 390.576993] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] lines 0, 3, 4, 5, 9, 11, 12, 14, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 390.577061] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] blocks 10, 10, 10, 12, 20, 24, 26, 30, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 390.577128] i915 0000:00:02.0: [drm:skl_compute_wm [i915]] [PLANE:47:cursor A] min_ddb 11, 11, 11, 13, 21, 25, 27, 31, 0 -> 0, 0, 0, 0, 0, 0, 0, 0, 0 > [ 390.577170] [drm:drm_atomic_commit [drm]] committing 00000000db481eed > [ 390.577307] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000db481eed > [ 390.577351] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000db481eed From patchwork at emeril.freedesktop.org Sat Jun 6 01:03:54 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 06 Jun 2020 01:03:54 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Delete_unused_code?= In-Reply-To: <20200605200357.13069-1-chris@chris-wilson.co.uk> References: <20200605200357.13069-1-chris@chris-wilson.co.uk> Message-ID: <159140543427.20631.10408132748726398416@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Delete unused code URL : https://patchwork.freedesktop.org/series/78055/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8594_full -> Patchwork_17894_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17894_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17894_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17894_full: ### IGT changes ### #### Possible regressions #### * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-snb4/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-snb5/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html #### Warnings #### * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [SKIP][3] ([fdo#109271]) -> [TIMEOUT][4] +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-snb4/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-snb5/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_endless@dispatch at rcs0}: - shard-iclb: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb5/igt at gem_exec_endless@dispatch at rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb5/igt at gem_exec_endless@dispatch at rcs0.html * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [FAIL][7] ([i915#1930]) -> [TIMEOUT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html * {igt at kms_chamelium@vga-hpd-enable-disable-mode}: - shard-snb: [SKIP][9] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-snb4/igt at kms_chamelium@vga-hpd-enable-disable-mode.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-snb5/igt at kms_chamelium@vga-hpd-enable-disable-mode.html Known issues ------------ Here are the changes found in Patchwork_17894_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118] / [i915#95]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-glk4/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl2/igt at i915_suspend@forcewake.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl1/igt at i915_suspend@forcewake.html - shard-glk: [PASS][15] -> [INCOMPLETE][16] ([i915#58] / [k.org#198133]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-glk6/igt at i915_suspend@forcewake.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-glk7/igt at i915_suspend@forcewake.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl7/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][19] -> [DMESG-FAIL][20] ([i915#118] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-glk1/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [PASS][21] -> [DMESG-FAIL][22] ([i915#54] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#128]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl7/igt at kms_cursor_legacy@pipe-c-torture-move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl2/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#95]) +17 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#1188]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl10/igt at kms_hdr@bpc-switch.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl6/igt at kms_hdr@bpc-switch.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][37] -> [FAIL][38] ([i915#173]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb4/igt at kms_psr@no_drrs.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_suspend: - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb2/igt at kms_psr@psr2_suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb8/igt at kms_psr@psr2_suspend.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-d: - shard-tglb: [PASS][41] -> [DMESG-WARN][42] ([i915#1982]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-tglb5/igt at kms_universal_plane@universal-plane-gen9-features-pipe-d.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-tglb5/igt at kms_universal_plane@universal-plane-gen9-features-pipe-d.html * igt at prime_vgem@basic-fence-flip: - shard-skl: [PASS][43] -> [DMESG-WARN][44] ([i915#1982]) +5 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl9/igt at prime_vgem@basic-fence-flip.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl8/igt at prime_vgem@basic-fence-flip.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][45] ([i915#1930]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html * igt at i915_module_load@reload-with-fault-injection: - shard-skl: [INCOMPLETE][47] ([i915#198]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl8/igt at i915_module_load@reload-with-fault-injection.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl2/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_rpm@system-suspend-modeset: - shard-skl: [INCOMPLETE][49] ([i915#151] / [i915#69]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl4/igt at i915_pm_rpm@system-suspend-modeset.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl1/igt at i915_pm_rpm@system-suspend-modeset.html * igt at i915_pm_rps@reset: - shard-apl: [DMESG-WARN][51] ([i915#95]) -> [PASS][52] +13 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl1/igt at i915_pm_rps@reset.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl8/igt at i915_pm_rps@reset.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-glk4/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][55] ([i915#118] / [i915#95]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-glk9/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +8 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl7/igt at kms_color@pipe-c-ctm-0-25.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl10/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl4/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][61] ([i915#54]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl7/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-iclb: [DMESG-WARN][63] ([i915#128]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb5/igt at kms_cursor_legacy@pipe-c-torture-bo.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb4/igt at kms_cursor_legacy@pipe-c-torture-bo.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1}: - shard-skl: [FAIL][65] ([i915#79]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl9/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl3/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-apl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl7/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-skl: [FAIL][69] ([i915#49]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl4/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][71] ([i915#1188]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb3/igt at kms_psr@psr2_primary_mmap_cpu.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-iclb: [INCOMPLETE][77] ([i915#1078] / [i915#1185]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb3/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb3/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80] +4 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at kms_vblank@pipe-b-wait-busy: - shard-iclb: [DMESG-WARN][81] ([i915#1982]) -> [PASS][82] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb6/igt at kms_vblank@pipe-b-wait-busy.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb1/igt at kms_vblank@pipe-b-wait-busy.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][83] ([i915#658]) -> [SKIP][84] ([i915#588]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-iclb3/igt at i915_pm_dc@dc3co-vpb-simulation.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [INCOMPLETE][85] ([i915#155]) -> [DMESG-WARN][86] ([i915#180]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl2/igt at i915_suspend@debugfs-reader.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl7/igt at i915_suspend@debugfs-reader.html * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [SKIP][87] ([fdo#109271] / [fdo#111827]) -> [INCOMPLETE][88] ([CI#80] / [i915#82]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-snb4/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-snb5/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][89] ([i915#1319] / [i915#1635]) -> [FAIL][90] ([fdo#110321] / [fdo#110336]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl3/igt at kms_content_protection@atomic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl1/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][91] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][92] ([i915#1319] / [i915#1635]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl1/igt at kms_content_protection@legacy.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl7/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][93] ([i915#1319]) -> [TIMEOUT][94] ([i915#1319] / [i915#1958]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-kbl3/igt at kms_content_protection@srm.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-kbl4/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][95] ([i915#95]) -> [DMESG-WARN][96] ([i915#180] / [i915#95]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8594/shard-apl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1078]: https://gitlab.freedesktop.org/drm/intel/issues/1078 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8594 -> Patchwork_17894 CI-20190529: 20190529 CI_DRM_8594: 6d6b387f9c60b269a434f75fe9b859a7aa6feb88 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17894: 7b2f658eb02da85bb09391b95d3b556fc9e7d997 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17894/index.html From matthew.d.roper at intel.com Sat Jun 6 02:57:33 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:33 -0700 Subject: [Intel-gfx] [PATCH v4 0/7] Remaining RKL patches Message-ID: <20200606025740.3308880-1-matthew.d.roper@intel.com> Key deltas from v3: - Squashed ABOX_CTL and BW_BUDDY patches into a single patch that uses a single abox_mask field in the device_info structure. A special case is added to also program the abox0 instance of ABOX_CTL on gen12, even on platforms that use abox1+abox2 instead. - Fixed DSI transcoder avoidance logic - Set a custom hpd_pin value for RKL+TGP at initialization rather than using a separate mapping table for that platform+pch combo. Aditya Swarup (1): drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper (6): drm/i915/rkl: RKL uses ABOX0 for pixel transfers drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout drm/i915/rkl: Update TGP's pin mapping when paired with RKL drm/i915/rkl: Add DPLL4 support drm/i915/rkl: Handle HTI drm/i915/rkl: Add initial workarounds drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++- drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++--- .../drm/i915/display/intel_display_power.c | 55 ++++++------ drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++++++- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/display/intel_hotplug.c | 9 ++ drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++++++++++++------- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_pci.c | 3 + drivers/gpu/drm/i915/i915_reg.h | 36 ++++++-- drivers/gpu/drm/i915/intel_device_info.h | 2 + 12 files changed, 239 insertions(+), 86 deletions(-) -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 02:57:39 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:39 -0700 Subject: [Intel-gfx] [PATCH v4 6/7] drm/i915/rkl: Handle HTI In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <20200606025740.3308880-7-matthew.d.roper@intel.com> If HTI (also sometimes called HDPORT) is enabled at startup, it may be using some of the PHYs and DPLLs making them unavailable for general usage. Let's read out the HDPORT_STATE register and avoid making use of resources that HTI is already using. v2: - Fix minor checkpatch warnings Bspec: 49189 Bspec: 53707 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++ 5 files changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6c2bb3354b86..f16512eddc58 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -46,6 +46,7 @@ #include "display/intel_ddi.h" #include "display/intel_dp.h" #include "display/intel_dp_mst.h" +#include "display/intel_dpll_mgr.h" #include "display/intel_dsi.h" #include "display/intel_dvo.h" #include "display/intel_gmbus.h" @@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } +static bool hti_uses_phy(u32 hdport_state, enum phy phy) +{ + return hdport_state & HDPORT_ENABLED && + (hdport_state & HDPORT_PHY_USED_DP(phy) || + hdport_state & HDPORT_PHY_USED_HDMI(phy)); +} + static void intel_setup_outputs(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; @@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_ROCKETLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + /* + * If HTI (aka HDPORT) is enabled at boot, it may have taken + * over some of the PHYs and made them unavailable to the + * driver. In that case we should skip initializing the + * corresponding outputs. + */ + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + + if (!hti_uses_phy(hdport_state, PHY_A)) + intel_ddi_init(dev_priv, PORT_A); + if (!hti_uses_phy(hdport_state, PHY_B)) + intel_ddi_init(dev_priv, PORT_B); + if (!hti_uses_phy(hdport_state, PHY_C)) + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + if (!hti_uses_phy(hdport_state, PHY_D)) + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); @@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) intel_dpll_readout_hw_state(dev_priv); + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); + for_each_intel_encoder(dev, encoder) { pipe = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b5f4d4cef682..6f59f9ec453b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) mutex_unlock(&dev_priv->dpll.lock); } +/* + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them + * unavailable for use. + */ +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) +{ + u32 hdport_state; + + if (!IS_ROCKETLAKE(dev_priv)) + return 0; + + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + if (!(hdport_state & HDPORT_ENABLED)) + return 0; + + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); +} + static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + /* Eliminate DPLLs from consideration if reserved by HTI */ + dpll_mask &= ~dev_priv->hti_pll_mask; + for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { pll = &dev_priv->dpll.shared_dplls[i]; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 5d9a2bc371e7..ac2238646fe7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device *dev); void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..b836032fa0de 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1037,6 +1037,9 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ + u32 hti_pll_mask; + /* * edram size in MB. * Cannot be determined by PCIID. You must always read a register. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 75304626f5d4..5b032fd0ef6d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2909,6 +2909,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) +#define HDPORT_STATE _MMIO(0x45050) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) +#define HDPORT_ENABLED REG_BIT(0) + /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 02:57:34 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:34 -0700 Subject: [Intel-gfx] [PATCH v4 1/7] drm/i915/rkl: RKL uses ABOX0 for pixel transfers In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <20200606025740.3308880-2-matthew.d.roper@intel.com> Rocket Lake uses the same 'abox0' mechanism to handle pixel data transfers from memory that gen11 platforms used, rather than the abox1/abox2 interfaces used by TGL/DG1. For the most part this is a hardware implementation detail that's transparent to driver software, but we do have to program a couple of tuning registers (MBUS_ABOX_CTL and BW_BUDDY registers) according to which ABOX instances are used by a platform. Let's track the platform's ABOX usage in the device info structure and use that to determine which instances of these registers to program. As an exception to this rule is that even though TGL/DG1 use ABOX1+ABOX2 for data transfers, we're still directed to program the ABOX_CTL register for ABOX0; so we'll handle that as a special case. v2: - Store the mask of platform-specific abox registers in the device info structure. - Add a TLB_REQ_TIMER() helper macro. (Aditya) v3: - Squash ABOX and BW_BUDDY patches together and use a single mask for both of them, plus a special-case for programming the ABOX0 instance on all gen12. (Ville) Bspec: 50096 Bspec: 49218 Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- .../drm/i915/display/intel_display_power.c | 55 ++++++++++--------- drivers/gpu/drm/i915/i915_pci.c | 3 + drivers/gpu/drm/i915/i915_reg.h | 24 +++++--- drivers/gpu/drm/i915/intel_device_info.h | 2 + 4 files changed, 52 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 72312b67b57a..24a2aa1fdc9c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4760,7 +4760,8 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) static void icl_mbus_init(struct drm_i915_private *dev_priv) { - u32 mask, val; + unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; + u32 mask, val, i; mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | MBUS_ABOX_BT_CREDIT_POOL2_MASK | @@ -4771,11 +4772,16 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) MBUS_ABOX_B_CREDIT(1) | MBUS_ABOX_BW_CREDIT(1); - intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val); - if (INTEL_GEN(dev_priv) >= 12) { - intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val); - intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val); - } + /* + * gen12 platforms that use abox1 and abox2 for pixel data reads still + * expect us to program the abox_ctl0 register as well, even though + * we don't have to program other instance-0 registers like BW_BUDDY. + */ + if (IS_GEN(dev_priv, 12)) + abox_regs |= BIT(0); + + for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) + intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); } static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) @@ -5254,7 +5260,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) enum intel_dram_type type = dev_priv->dram_info.type; u8 num_channels = dev_priv->dram_info.num_channels; const struct buddy_page_mask *table; - int i; + unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask; + int config, i; if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) /* Wa_1409767108: tgl */ @@ -5262,29 +5269,27 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) else table = tgl_buddy_page_masks; - for (i = 0; table[i].page_mask != 0; i++) - if (table[i].num_channels == num_channels && - table[i].type == type) + for (config = 0; table[config].page_mask != 0; config++) + if (table[config].num_channels == num_channels && + table[config].type == type) break; - if (table[i].page_mask == 0) { + if (table[config].page_mask == 0) { drm_dbg(&dev_priv->drm, "Unknown memory configuration; disabling address buddy logic.\n"); - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); + for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) + intel_de_write(dev_priv, BW_BUDDY_CTL(i), + BW_BUDDY_DISABLE); } else { - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, - table[i].page_mask); - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, - table[i].page_mask); - - /* Wa_22010178259:tgl */ - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, - BW_BUDDY_TLB_REQ_TIMER_MASK, - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, - BW_BUDDY_TLB_REQ_TIMER_MASK, - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); + for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), + table[config].page_mask); + + /* Wa_22010178259:tgl,rkl */ + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), + BW_BUDDY_TLB_REQ_TIMER_MASK, + BW_BUDDY_TLB_REQ_TIMER(0x8)); + } } } diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 192f1cd172b8..e5fdf17cd9cd 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -804,6 +804,7 @@ static const struct intel_device_info cnl_info = { #define GEN11_FEATURES \ GEN10_FEATURES, \ GEN11_DEFAULT_PAGE_SIZES, \ + .abox_mask = BIT(0), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ @@ -847,6 +848,7 @@ static const struct intel_device_info ehl_info = { #define GEN12_FEATURES \ GEN11_FEATURES, \ GEN(12), \ + .abox_mask = GENMASK(2, 1), \ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ @@ -882,6 +884,7 @@ static const struct intel_device_info tgl_info = { static const struct intel_device_info rkl_info = { GEN12_FEATURES, PLATFORM(INTEL_ROCKETLAKE), + .abox_mask = BIT(0), .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 814a70945468..4c3e822e1024 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2879,9 +2879,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ -#define MBUS_ABOX_CTL _MMIO(0x45038) -#define MBUS_ABOX1_CTL _MMIO(0x45048) -#define MBUS_ABOX2_CTL _MMIO(0x4504C) +#define _MBUS_ABOX0_CTL 0x45038 +#define _MBUS_ABOX1_CTL 0x45048 +#define _MBUS_ABOX2_CTL 0x4504C +#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ + _MBUS_ABOX1_CTL, \ + _MBUS_ABOX2_CTL)) #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) @@ -7839,13 +7842,20 @@ enum { #define WAIT_FOR_PCH_RESET_ACK (1 << 1) #define WAIT_FOR_PCH_FLR_ACK (1 << 0) -#define BW_BUDDY1_CTL _MMIO(0x45140) -#define BW_BUDDY2_CTL _MMIO(0x45150) +#define _BW_BUDDY0_CTL 0x45130 +#define _BW_BUDDY1_CTL 0x45140 +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_CTL, \ + _BW_BUDDY1_CTL)) #define BW_BUDDY_DISABLE REG_BIT(31) #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) +#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) +#define _BW_BUDDY0_PAGE_MASK 0x45134 +#define _BW_BUDDY1_PAGE_MASK 0x45144 +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ + _BW_BUDDY0_PAGE_MASK, \ + _BW_BUDDY1_PAGE_MASK)) #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 34dbffd65bad..8d62b8538585 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -175,6 +175,8 @@ struct intel_device_info { u8 pipe_mask; u8 cpu_transcoder_mask; + u8 abox_mask; + #define DEFINE_FLAG(name) u8 name:1 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); #undef DEFINE_FLAG -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 02:57:36 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:36 -0700 Subject: [Intel-gfx] [PATCH v4 3/7] drm/i915/rkl: Update TGP's pin mapping when paired with RKL In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <20200606025740.3308880-4-matthew.d.roper@intel.com> HPD pin handling for RKL+TGP is a special case; we effectively select the HPD pin based on the DDI (A,B,D,E) rather than the PHY (A,B,C,D). This differs from the regular behavior of RKL+CMP (and also TGL+TGP). v2: - Rather than providing a custom hpd_pin mapping table, just assign encoder->hpd_pin in a custom manner for this setup. (Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_hotplug.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 4f6f560e093e..d794dd5f170c 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -89,6 +89,15 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, { enum phy phy = intel_port_to_phy(dev_priv, port); + /* + * RKL + TGP PCH is a special case; we effectively choose the hpd_pin + * based on the DDI rather than the PHY (i.e., the last two outputs + * shold be HPD_PORT_{D,E} rather than {C,D}. Note that this differs + * from the behavior of both TGL+TGP and RKL+CMP. + */ + if (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)) + return HPD_PORT_A + port - PORT_A; + switch (phy) { case PHY_F: return IS_CNL_WITH_PORT_F(dev_priv) ? HPD_PORT_E : HPD_PORT_F; -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 02:57:38 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:38 -0700 Subject: [Intel-gfx] [PATCH v4 5/7] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <20200606025740.3308880-6-matthew.d.roper@intel.com> Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were DPLL2, so no extra offset handling is needed either. v2: - Add new .update_ref_clks() hook. Bspec: 49202 Bspec: 49443 Bspec: 50288 Bspec: 50289 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b45185b80bec..b5f4d4cef682 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, return false; } - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) + if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - else + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { + dpll_mask = + BIT(DPLL_ID_EHL_DPLL4) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else { dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); + } port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info rkl_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, + { }, +}; + +static const struct intel_dpll_mgr rkl_pll_mgr = { + .dpll_info = rkl_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (INTEL_GEN(dev_priv) >= 12) + if (IS_ROCKETLAKE(dev_priv)) + dpll_mgr = &rkl_pll_mgr; + else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr; else if (IS_ELKHARTLAKE(dev_priv)) dpll_mgr = &ehl_pll_mgr; -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 02:57:40 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:40 -0700 Subject: [Intel-gfx] [PATCH v4 7/7] drm/i915/rkl: Add initial workarounds In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <20200606025740.3308880-8-matthew.d.roper@intel.com> RKL and TGL share some general gen12 workarounds, but each platform also has its own platform-specific workarounds. Cc: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++-------- 2 files changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3cd461bf9131..63ac79f88fa2 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0] */ - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) + /* Wa_14010477008:tgl[a0..c0],rkl[all] */ + if (IS_ROCKETLAKE(dev_priv) || + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3eec31c5a714..5e77ae73e9dd 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -590,8 +590,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) { /* * Wa_1409142259:tgl @@ -601,12 +601,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1409207793:tgl * Wa_1409178076:tgl * Wa_1408979724:tgl + * Wa_14010443199:rkl + * Wa_14010698770:rkl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); + /* WaDisableGPGPUMidThreadPreemption:gen12 */ + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, + GEN9_PREEMPT_GPGPU_LEVEL_MASK, + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); +} + +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + /* - * Wa_1604555607:gen12 and Wa_1608008084:gen12 + * Wa_1604555607:tgl + * + * Note that the implementation of this workaround is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit * masks. So instead of doing a RMW we should just write the GS Timer @@ -617,11 +633,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 0); - - /* WaDisableGPGPUMidThreadPreemption:tgl */ - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, - GEN9_PREEMPT_GPGPU_LEVEL_MASK, - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); } static void @@ -636,8 +647,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 12)) + gen12_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 11)) icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) @@ -949,9 +962,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen12_gt_workarounds_init(struct drm_i915_private *i915, + struct i915_wa_list *wal) { wa_init_mcr(i915, wal); +} + +static void +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) @@ -969,8 +989,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 12)) + gen12_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 11)) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) @@ -1388,18 +1410,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); - /* - * Wa_1607030317:tgl - * Wa_1607186500:tgl - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 - * of then says it is fixed on B0 the other one says it is - * permanent - */ - wa_masked_en(wal, - GEN6_RC_SLEEP_PSMI_CONTROL, - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE); - /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1418,24 +1428,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl */ + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); - /* Wa_1409804808:tgl */ + /* Wa_1409804808:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); - /* Wa_1606700617:tgl */ - wa_masked_en(wal, - GEN9_CS_DEBUG_MODE1, - FF_DOP_CLOCK_GATE_DISABLE); - /* * Wa_1409085225:tgl - * Wa_14010229206:tgl + * Wa_14010229206:tgl,rkl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); + + /* + * Wa_1607030317:tgl + * Wa_1607186500:tgl + * Wa_1607297627:tgl,rkl there are multiple entries for this + * WA in the BSpec; some indicate this is an A0-only WA, + * others indicate it applies to all steppings. + */ + wa_masked_en(wal, + GEN6_RC_SLEEP_PSMI_CONTROL, + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + } + + if (IS_TIGERLAKE(i915)) { + /* Wa_1606700617:tgl */ + wa_masked_en(wal, + GEN9_CS_DEBUG_MODE1, + FF_DOP_CLOCK_GATE_DISABLE); } if (IS_GEN(i915, 11)) { -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 02:57:37 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:37 -0700 Subject: [Intel-gfx] [PATCH v4 4/7] drm/i915/rkl: Don't try to read out DSI transcoders In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <20200606025740.3308880-5-matthew.d.roper@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI transcoder registers. v2(MattR): - Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask against the platform's cpu_transcoder_mask to filter out the ones that don't exist on a given platform. (Ville) v3(MattR): - Only include DSI transcoders on gen11+ again. (Ville) - Use for_each_cpu_transcoder_masked() for loop. (Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9820874d3ea2..6c2bb3354b86 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10904,7 +10904,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum intel_display_power_domain power_domain; - unsigned long panel_transcoder_mask = 0; + unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP); unsigned long enabled_panel_transcoders = 0; enum transcoder panel_transcoder; intel_wakeref_t wf; @@ -10914,9 +10914,6 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP)) - panel_transcoder_mask |= BIT(TRANSCODER_EDP); - /* * The pipe->transcoder mapping is fixed with the exception of the eDP * and DSI transcoders handled below. @@ -10927,9 +10924,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, * XXX: Do intel_display_power_get_if_enabled before reading this (for * consistency and less surprising code; it's in always on power). */ - for_each_set_bit(panel_transcoder, - &panel_transcoder_mask, - ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) { + for_each_cpu_transcoder_masked(dev_priv, panel_transcoder, + panel_transcoder_mask) { bool force_thru = false; enum pipe trans_pipe; -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 02:57:35 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 19:57:35 -0700 Subject: [Intel-gfx] [PATCH v4 2/7] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <20200606025740.3308880-3-matthew.d.roper@intel.com> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. v2: - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 - Checkpatch style fixes Bspec: 50287 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 96eaa4b39c68..0a944a1e3f20 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, enum phy phy) { - if (intel_phy_is_combo(dev_priv, phy)) { + if (IS_ROCKETLAKE(dev_priv)) { + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + } else if (intel_phy_is_combo(dev_priv, phy)) { return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } else if (intel_phy_is_tc(dev_priv, phy)) { enum tc_port tc_port = intel_port_to_tc(dev_priv, @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { + u32 mask, sel; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } + /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + val &= ~mask; + val |= sel; intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b16aca0fe5f0..9820874d3ea2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + u32 mask, shift; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } + + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; + id = temp >> shift; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4c3e822e1024..75304626f5d4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10181,12 +10181,18 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ (tc_port) + 12 : \ (tc_port) - PORT_TC4 + 21)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) /* CNL PLL */ #define DPLL0_ENABLE 0x46010 -- 2.24.1 From patchwork at emeril.freedesktop.org Sat Jun 6 03:12:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 06 Jun 2020 03:12:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Remaining_RKL_patches_=28rev2=29?= In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <159141312046.20629.13885094047328115833@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev2) URL : https://patchwork.freedesktop.org/series/77971/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From matthew.d.roper at intel.com Sat Jun 6 03:18:03 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 20:18:03 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Restore DP-E to VBT mapping table Message-ID: <20200606031803.3309624-1-matthew.d.roper@intel.com> We accidentally dropped matching for DVO_PORT_DPE from the VBT mapping table when we refactored the function. Restore it. Fixes: 4628142aeccc ("drm/i915/rkl: provide port/phy mapping for vbt") Cc: Lucas De Marchi <lucas.demarchi at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Chris Wilson <chris at chris-wilson.co.uk> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4f1a72a90b8f..c974c716f859 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1650,7 +1650,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, - [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 }, + [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, }; -- 2.24.1 From matthew.d.roper at intel.com Sat Jun 6 03:21:37 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 5 Jun 2020 20:21:37 -0700 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogIHN1Y2Nlc3MgZm9yIFJl?= =?utf-8?q?maining_RKL_patches?= In-Reply-To: <159139508324.22562.3240839281624363557@build.alporthouse.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <159125964432.14555.14975271091238919132@emeril.freedesktop.org> <20200604163916.GA3023929@mdroper-desk1.amr.corp.intel.com> <159139508324.22562.3240839281624363557@build.alporthouse.com> Message-ID: <20200606032137.GA3210209@mdroper-desk1.amr.corp.intel.com> On Fri, Jun 05, 2020 at 11:11:23PM +0100, Chris Wilson wrote: > Quoting Matt Roper (2020-06-04 17:39:16) > > On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote: > > > == Series Details == > > > > > > Series: Remaining RKL patches > > > URL : https://patchwork.freedesktop.org/series/77971/ > > > State : success > > > > > > == Summary == > > > > > > CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full > > > ==================================================== > > > > > > Summary > > > ------- > > > > > > **SUCCESS** > > > > > > No regressions found. > > > > Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's. > > This seems to have introduced > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-skl-guc/igt at runner@aborted.html Thanks for pointing that out. I think it's because we lost DP-E matching in the VBT mapping table during the refactor. If so, https://patchwork.freedesktop.org/patch/368948/?series=78060&rev=1 should fix it. Was there a gitlab bug for this failure? Matt > > <4>[ 3.422515] i915 0000:00:02.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(dev)) > <4>[ 3.422528] WARNING: CPU: 4 PID: 372 at drivers/gpu/drm/drm_vblank.c:719 drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370 > <4>[ 3.422529] Modules linked in: i915(+) mei_hdcp x86_pkg_temp_thermal coretemp snd_hda_intel snd_intel_dspcfg crct10dif_pclmul snd_hda_codec crc32_pclmul snd_hwdep snd_hda_core ghash_clmulni_intel snd_pcm mei_me e1000e mei ptp prime_numbers pps_core > <4>[ 3.422540] CPU: 4 PID: 372 Comm: systemd-udevd Tainted: G U 5.7.0-CI-CI_DRM_8584+ #1 > <4>[ 3.422542] Hardware name: System manufacturer System Product Name/Z170 PRO GAMING, BIOS 3402 04/26/2017 > <4>[ 3.422544] RIP: 0010:drm_crtc_vblank_helper_get_vblank_timestamp_internal+0x264/0x370 > <4>[ 3.422547] Code: 8b 5f 50 48 85 db 0f 84 e8 00 00 00 e8 65 62 01 00 48 c7 c1 08 90 35 82 48 89 da 48 89 c6 48 c7 c7 c8 95 35 82 e8 ec d6 9c ff <0f> 0b 45 31 d2 e9 32 ff ff ff 48 8b 7b 18 8b 4d 9c 48 c7 c2 40 90 > <4>[ 3.422548] RSP: 0018:ffffc9000050b808 EFLAGS: 00010082 > <4>[ 3.422550] RAX: 0000000000000000 RBX: ffff88822ba975a0 RCX: 0000000000000003 > <4>[ 3.422552] RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffffffff82383f0a > <4>[ 3.422554] RBP: ffffc9000050b878 R08: 0000000000000000 R09: 0000000000000001 > <4>[ 3.422555] R10: 0000000000000000 R11: 00000000e5a843ae R12: ffff8882193eb800 > <4>[ 3.422557] R13: ffffc9000050b8c8 R14: 0000000000000000 R15: ffff88820c1fd350 > <4>[ 3.422559] FS: 00007f3e6ef07680(0000) GS:ffff88822ec00000(0000) knlGS:0000000000000000 > <4>[ 3.422561] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > <4>[ 3.422562] CR2: 00007f91492aa290 CR3: 000000022368a004 CR4: 00000000003606e0 > <4>[ 3.422564] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > <4>[ 3.422565] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 > <4>[ 3.422567] Call Trace: > <4>[ 3.422604] ? fwtable_read32+0x83/0x310 [i915] > <4>[ 3.422611] drm_get_last_vbltimestamp+0xb2/0xc0 > <4>[ 3.422616] drm_reset_vblank_timestamp+0x54/0xc0 > <4>[ 3.422621] drm_crtc_vblank_on+0x83/0x140 > <4>[ 3.422670] intel_modeset_setup_hw_state+0x8f7/0x16c0 [i915] > <4>[ 3.422676] ? drm_modeset_lock+0xad/0x120 > <4>[ 3.422727] intel_modeset_init+0x582/0x1c50 [i915] > <4>[ 3.422731] ? _raw_spin_unlock_irqrestore+0x34/0x60 > <4>[ 3.422764] ? intel_irq_postinstall+0x284/0x610 [i915] > <4>[ 3.422799] i915_driver_probe+0x778/0xf90 [i915] > <4>[ 3.422805] ? __pm_runtime_resume+0x4f/0x80 > <4>[ 3.422840] i915_pci_probe+0x3b/0x1d0 [i915] > <4>[ 3.422843] ? _raw_spin_unlock_irqrestore+0x34/0x60 > <4>[ 3.422849] pci_device_probe+0x9e/0x120 > <4>[ 3.422853] really_probe+0xea/0x430 > <4>[ 3.422858] driver_probe_device+0x10b/0x120 > <4>[ 3.422861] device_driver_attach+0x4a/0x50 > <4>[ 3.422865] __driver_attach+0x97/0x130 > <4>[ 3.422868] ? device_driver_attach+0x50/0x50 > <4>[ 3.422871] bus_for_each_dev+0x74/0xc0 > <4>[ 3.422875] bus_add_driver+0x142/0x220 > <4>[ 3.422879] driver_register+0x56/0xf0 > <4>[ 3.422913] i915_init+0x6c/0x7c [i915] > <4>[ 3.422916] ? 0xffffffffa08c9000 > <4>[ 3.422918] do_one_initcall+0x58/0x300 > <4>[ 3.422921] ? do_init_module+0x1d/0x1f2 > <4>[ 3.422924] ? rcu_read_lock_sched_held+0x4d/0x80 > <4>[ 3.422928] ? kmem_cache_alloc_trace+0x2a6/0x2d0 > <4>[ 3.422933] do_init_module+0x56/0x1f2 > <4>[ 3.422936] load_module+0x2339/0x2a20 > <4>[ 3.422953] ? __do_sys_finit_module+0xe9/0x110 > <4>[ 3.422955] __do_sys_finit_module+0xe9/0x110 > <4>[ 3.422966] do_syscall_64+0x4f/0x220 > <4>[ 3.422969] entry_SYSCALL_64_after_hwframe+0x49/0xb3 > <4>[ 3.422971] RIP: 0033:0x7f3e6ea28839 > <4>[ 3.422973] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48 > <4>[ 3.422975] RSP: 002b:00007ffebbc0c118 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 > <4>[ 3.422977] RAX: ffffffffffffffda RBX: 0000557f8afde730 RCX: 00007f3e6ea28839 > <4>[ 3.422979] RDX: 0000000000000000 RSI: 0000557f8afd62c0 RDI: 000000000000000f > <4>[ 3.422980] RBP: 0000557f8afd62c0 R08: 0000000000000000 R09: 00007ffebbc0c230 > <4>[ 3.422982] R10: 000000000000000f R11: 0000000000000246 R12: 0000000000000000 > <4>[ 3.422984] R13: 0000557f8afb99e0 R14: 0000000000020000 R15: 0000000000000000 > <4>[ 3.422993] irq event stamp: 603166 > <4>[ 3.422996] hardirqs last enabled at (603165): [<ffffffff81a4dfd7>] _raw_spin_unlock_irqrestore+0x47/0x60 > <4>[ 3.422998] hardirqs last disabled at (603166): [<ffffffff81a4dd5d>] _raw_spin_lock_irqsave+0xd/0x50 > <4>[ 3.423000] softirqs last enabled at (603132): [<ffffffff81e00395>] __do_softirq+0x395/0x > -Chris -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From patchwork at emeril.freedesktop.org Sat Jun 6 03:33:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 06 Jun 2020 03:33:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev2=29?= In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <159141439205.20631.4475377041972707933@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev2) URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8595 -> Patchwork_17895 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/index.html Known issues ------------ Here are the changes found in Patchwork_17895 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at execlists: - fi-icl-guc: [INCOMPLETE][5] ([i915#1871]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-icl-guc/igt at i915_selftest@live at execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/fi-icl-guc/igt at i915_selftest@live at execlists.html #### Warnings #### * igt at i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][7] ([i915#289]) -> [DMESG-WARN][8] ([i915#1982] / [i915#289]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-icl-u2/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/fi-icl-u2/igt at i915_module_load@reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1871]: https://gitlab.freedesktop.org/drm/intel/issues/1871 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8595 -> Patchwork_17895 CI-20190529: 20190529 CI_DRM_8595: 4f882c61c3ac2e1481b2d9099f1188969d973335 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17895: 4bbbf214679314e4fc692bf4ae810863139e0c76 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4bbbf2146793 drm/i915/rkl: Add initial workarounds f8cdb83c4d96 drm/i915/rkl: Handle HTI c9195aae9c12 drm/i915/rkl: Add DPLL4 support 78f785947c7d drm/i915/rkl: Don't try to read out DSI transcoders bb8e3baffe21 drm/i915/rkl: Update TGP's pin mapping when paired with RKL 336577d97303 drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout 0034c94adf4e drm/i915/rkl: RKL uses ABOX0 for pixel transfers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/index.html From patchwork at emeril.freedesktop.org Sat Jun 6 03:59:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 06 Jun 2020 03:59:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Restore_DP-E_to_VBT_mapping_table?= In-Reply-To: <20200606031803.3309624-1-matthew.d.roper@intel.com> References: <20200606031803.3309624-1-matthew.d.roper@intel.com> Message-ID: <159141596886.20629.12706033336769120125@emeril.freedesktop.org> == Series Details == Series: drm/i915: Restore DP-E to VBT mapping table URL : https://patchwork.freedesktop.org/series/78060/ State : success == Summary == CI Bug Log - changes from CI_DRM_8595 -> Patchwork_17896 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/index.html Known issues ------------ Here are the changes found in Patchwork_17896 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at execlists: - fi-icl-guc: [INCOMPLETE][3] ([i915#1871]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-icl-guc/igt at i915_selftest@live at execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/fi-icl-guc/igt at i915_selftest@live at execlists.html * {igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1}: - fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][8] ([i915#62] / [i915#92]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1871]: https://gitlab.freedesktop.org/drm/intel/issues/1871 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8595 -> Patchwork_17896 CI-20190529: 20190529 CI_DRM_8595: 4f882c61c3ac2e1481b2d9099f1188969d973335 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17896: 0951c84cc94cd180db6d968e185dde435885fff2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0951c84cc94c drm/i915: Restore DP-E to VBT mapping table == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/index.html From patchwork at emeril.freedesktop.org Sat Jun 6 04:31:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 06 Jun 2020 04:31:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev2=29?= In-Reply-To: <20200606025740.3308880-1-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> Message-ID: <159141789595.20628.14561745891980444778@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev2) URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8595_full -> Patchwork_17895_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17895_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_suspend@debugfs-reader: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#69]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl9/igt at i915_suspend@debugfs-reader.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl9/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk4/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-glk1/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +19 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl6/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [i915#265]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109441]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-iclb7/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at kms_vblank@pipe-b-wait-busy: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb6/igt at kms_vblank@pipe-b-wait-busy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-iclb7/igt at kms_vblank@pipe-b-wait-busy.html * igt at prime_vgem@basic-fence-flip: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl6/igt at prime_vgem@basic-fence-flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl1/igt at prime_vgem@basic-fence-flip.html #### Possible fixes #### * {igt at gem_exec_schedule@preempt at bcs0}: - shard-tglb: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-tglb7/igt at gem_exec_schedule@preempt at bcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-tglb7/igt at gem_exec_schedule@preempt at bcs0.html * igt at gem_exec_whisper@basic-contexts-priority: - shard-glk: [DMESG-WARN][23] ([i915#118] / [i915#95]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk7/igt at gem_exec_whisper@basic-contexts-priority.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-glk6/igt at gem_exec_whisper@basic-contexts-priority.html * igt at i915_pm_rps@reset: - shard-apl: [DMESG-WARN][25] ([i915#95]) -> [PASS][26] +17 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl1/igt at i915_pm_rps@reset.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-apl2/igt at i915_pm_rps@reset.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][27] ([i915#118] / [i915#95]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-b-ctm-negative: - shard-skl: [DMESG-WARN][29] ([i915#1982]) -> [PASS][30] +4 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_color@pipe-b-ctm-negative.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl8/igt at kms_color@pipe-b-ctm-negative.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][31] ([i915#93] / [i915#95]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl3/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_color@pipe-d-ctm-0-5: - shard-tglb: [DMESG-WARN][33] ([i915#1149] / [i915#402]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-tglb3/igt at kms_color@pipe-d-ctm-0-5.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-tglb2/igt at kms_color@pipe-d-ctm-0-5.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [DMESG-FAIL][35] ([i915#54] / [i915#95]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] +7 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge: - shard-glk: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk7/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-glk7/igt at kms_cursor_edge_walk@pipe-b-256x256-left-edge.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-snb: [TIMEOUT][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-snb2/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-snb1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [FAIL][43] ([i915#49]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl1/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [FAIL][45] ([i915#1188]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][47] ([CI#80] / [i915#69]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl5/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-apl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html #### Warnings #### * igt at i915_suspend@debugfs-reader: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [INCOMPLETE][58] ([i915#155]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl7/igt at i915_suspend@debugfs-reader.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl4/igt at i915_suspend@debugfs-reader.html * igt at kms_color_chamelium@pipe-c-ctm-limited-range: - shard-snb: [INCOMPLETE][59] ([CI#80] / [i915#82]) -> [SKIP][60] ([fdo#109271] / [fdo#111827]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-snb2/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-snb1/igt at kms_color_chamelium@pipe-c-ctm-limited-range.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][61] ([i915#1319] / [i915#1958]) -> [TIMEOUT][62] ([i915#1319]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at kms_content_protection@atomic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl6/igt at kms_content_protection@atomic.html - shard-apl: [FAIL][63] ([fdo#110321] / [fdo#110336]) -> [DMESG-FAIL][64] ([fdo#110321]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl4/igt at kms_content_protection@atomic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-apl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][65] ([i915#1319]) -> [TIMEOUT][66] ([i915#1319] / [i915#1958]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl2/igt at kms_content_protection@atomic-dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [FAIL][68] ([fdo#110321] / [fdo#110336]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl3/igt at kms_content_protection@legacy.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][69] ([fdo#110321] / [i915#95]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl7/igt at kms_content_protection@lic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-apl6/igt at kms_content_protection@lic.html - shard-kbl: [DMESG-FAIL][71] ([fdo#110321] / [i915#95]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl2/igt at kms_content_protection@lic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-kbl3/igt at kms_content_protection@lic.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-snb: [TIMEOUT][73] -> [SKIP][74] ([fdo#109271]) +2 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-snb2/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/shard-snb1/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8595 -> Patchwork_17895 CI-20190529: 20190529 CI_DRM_8595: 4f882c61c3ac2e1481b2d9099f1188969d973335 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17895: 4bbbf214679314e4fc692bf4ae810863139e0c76 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17895/index.html From patchwork at emeril.freedesktop.org Sat Jun 6 05:14:36 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 06 Jun 2020 05:14:36 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Restore_DP-E_to_VBT_mapping_table?= In-Reply-To: <20200606031803.3309624-1-matthew.d.roper@intel.com> References: <20200606031803.3309624-1-matthew.d.roper@intel.com> Message-ID: <159142047627.20629.14843163935733006083@emeril.freedesktop.org> == Series Details == Series: drm/i915: Restore DP-E to VBT mapping table URL : https://patchwork.freedesktop.org/series/78060/ State : success == Summary == CI Bug Log - changes from CI_DRM_8595_full -> Patchwork_17896_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17896_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-normal: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk1/igt at gem_exec_whisper@basic-normal.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-glk6/igt at gem_exec_whisper@basic-normal.html * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at gem_workarounds@suspend-resume-fd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl7/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb2/igt at i915_pm_dc@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-iclb8/igt at i915_pm_dc@dc6-psr.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl6/igt at i915_suspend@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl4/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-32bpp-rotate-180: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +9 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl9/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl4/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +14 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#173]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb4/igt at kms_psr@no_drrs.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-iclb3/igt at kms_psr@psr2_cursor_render.html #### Possible fixes #### * {igt at gem_exec_schedule@preempt at bcs0}: - shard-tglb: [DMESG-WARN][25] ([i915#402]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-tglb7/igt at gem_exec_schedule@preempt at bcs0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-tglb3/igt at gem_exec_schedule@preempt at bcs0.html * igt at gem_exec_whisper@basic-contexts-priority: - shard-glk: [DMESG-WARN][27] ([i915#118] / [i915#95]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk7/igt at gem_exec_whisper@basic-contexts-priority.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-glk7/igt at gem_exec_whisper@basic-contexts-priority.html * igt at i915_suspend@fence-restore-untiled: - shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl4/igt at i915_suspend@fence-restore-untiled.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl6/igt at i915_suspend@fence-restore-untiled.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][31] ([i915#118] / [i915#95]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-glk4/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-b-ctm-negative: - shard-skl: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_color@pipe-b-ctm-negative.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl2/igt at kms_color@pipe-b-ctm-negative.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][35] ([i915#93] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl6/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][37] ([i915#54]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl8/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [DMESG-FAIL][39] ([i915#54] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +4 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-glk: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk8/igt at kms_fbcon_fbt@fbc-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-glk1/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][45] ([i915#95]) -> [PASS][46] +12 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl4/igt at kms_flip_tiling@flip-x-tiled.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl2/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [FAIL][47] ([i915#49]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [FAIL][49] ([i915#1188]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl1/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][51] ([CI#80] / [i915#69]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl5/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl9/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][53] ([i915#69]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb7/igt at kms_psr@psr2_primary_mmap_cpu.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_setmode@basic: - shard-glk: [FAIL][59] ([i915#31]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-glk1/igt at kms_setmode@basic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-glk2/igt at kms_setmode@basic.html - shard-kbl: [FAIL][61] ([i915#31]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at kms_setmode@basic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl7/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb8/igt at perf@blocking-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-iclb2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][65] ([i915#658]) -> [SKIP][66] ([i915#588]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-iclb7/igt at i915_pm_dc@dc3co-vpb-simulation.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][67] ([i915#1319] / [i915#1958]) -> [TIMEOUT][68] ([i915#1319]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl4/igt at kms_content_protection@atomic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][69] ([i915#1319] / [i915#1635]) -> [TIMEOUT][70] ([i915#1319]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl3/igt at kms_content_protection@legacy.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl7/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [DMESG-FAIL][71] ([fdo#110321] / [i915#95]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl7/igt at kms_content_protection@lic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl3/igt at kms_content_protection@lic.html - shard-kbl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl2/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl6/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][75] ([i915#1319]) -> [TIMEOUT][76] ([i915#1319] / [i915#1958]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-kbl3/igt at kms_content_protection@srm.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-kbl4/igt at kms_content_protection@srm.html - shard-apl: [TIMEOUT][77] ([i915#1319]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8595/shard-apl6/igt at kms_content_protection@srm.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/shard-apl2/igt at kms_content_protection@srm.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8595 -> Patchwork_17896 CI-20190529: 20190529 CI_DRM_8595: 4f882c61c3ac2e1481b2d9099f1188969d973335 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17896: 0951c84cc94cd180db6d968e185dde435885fff2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17896/index.html From chris at chris-wilson.co.uk Sat Jun 6 08:58:39 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sat, 06 Jun 2020 09:58:39 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Restore DP-E to VBT mapping table In-Reply-To: <20200606031803.3309624-1-matthew.d.roper@intel.com> References: <20200606031803.3309624-1-matthew.d.roper@intel.com> Message-ID: <159143391956.22562.4532580926711902889@build.alporthouse.com> Quoting Matt Roper (2020-06-06 04:18:03) > We accidentally dropped matching for DVO_PORT_DPE from the VBT mapping > table when we refactored the function. Restore it. > > Fixes: 4628142aeccc ("drm/i915/rkl: provide port/phy mapping for vbt") > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > Cc: Matt Roper <matthew.d.roper at intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index 4f1a72a90b8f..c974c716f859 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -1650,7 +1650,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, > [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, > [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, > [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, > - [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 }, > + [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, Ah, yes. That was an easy to overlook change in the table, Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> Is there a way we can compute a HW coverage matrix for this table? And see if we need to get more machines/connectors for CI? -Chris From chris at chris-wilson.co.uk Sat Jun 6 09:01:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sat, 06 Jun 2020 10:01:17 +0100 Subject: [Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches In-Reply-To: <20200606032137.GA3210209@mdroper-desk1.amr.corp.intel.com> References: <20200603211529.3005059-1-matthew.d.roper@intel.com> <159125964432.14555.14975271091238919132@emeril.freedesktop.org> <20200604163916.GA3023929@mdroper-desk1.amr.corp.intel.com> <159139508324.22562.3240839281624363557@build.alporthouse.com> <20200606032137.GA3210209@mdroper-desk1.amr.corp.intel.com> Message-ID: <159143407710.22562.14616951365539550947@build.alporthouse.com> Quoting Matt Roper (2020-06-06 04:21:37) > On Fri, Jun 05, 2020 at 11:11:23PM +0100, Chris Wilson wrote: > > Quoting Matt Roper (2020-06-04 17:39:16) > > > On Thu, Jun 04, 2020 at 08:34:04AM +0000, Patchwork wrote: > > > > == Series Details == > > > > > > > > Series: Remaining RKL patches > > > > URL : https://patchwork.freedesktop.org/series/77971/ > > > > State : success > > > > > > > > == Summary == > > > > > > > > CI Bug Log - changes from CI_DRM_8579_full -> Patchwork_17859_full > > > > ==================================================== > > > > > > > > Summary > > > > ------- > > > > > > > > **SUCCESS** > > > > > > > > No regressions found. > > > > > > Patches #1, 6, 8, and 11 from this series applied to dinq since they have r-b's. > > > > This seems to have introduced > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8584/fi-skl-guc/igt at runner@aborted.html > > Thanks for pointing that out. I think it's because we lost DP-E > matching in the VBT mapping table during the refactor. If so, > > https://patchwork.freedesktop.org/patch/368948/?series=78060&rev=1 > > should fix it. It did indeed. > Was there a gitlab bug for this failure? Not yet. -Chris From hdegoede at redhat.com Sat Jun 6 20:25:45 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:45 +0200 Subject: [Intel-gfx] pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Message-ID: <20200606202601.48410-1-hdegoede@redhat.com> Hi All, This patch series converts the i915 driver's cpde for controlling the panel's backlight with an external PWM controller to use the atomic PWM API. Initially the plan was for this series to consist of 2 parts: 1. convert the pwm-crc driver to support the atomic PWM API and 2. convert the i915 driver's PWM code to use the atomic PWM API. But during testing I've found a number of bugs in the pwm-lpss and I found that the acpi_lpss code needs some special handling because of some ugliness found in most Cherry Trail DSDTs. So now this series has grown somewhat large and consists of 4 parts: 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness 2. various fixes to the pwm-lpss driver 3. convert the pwm-crc driver to support the atomic PWM API and 4. convert the i915 driver's PWM code to use the atomic PWM API So we need to discuss how to merge this (once it passes review). Although the inter-dependencies are only runtime I still think we should make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before merging the i915 changes. Both to make sure that the intel-gfx CI system does not become unhappy and for bisecting reasons. The involved acpi_lpss and pwm drivers do not see a whole lot of churn, so we could just merge everything through dinq, or we could use immutable branch and merge those into dinq. So Rafael and Thierry, can I either get your Acked-by for directly merging this into dinq, or can you provide an immutable branch with these patches? This series has been tested (and re-tested after adding various bug-fixes) extensively. It has been tested on the following devices: -Asus T100TA BYT + CRC-PMIC PWM -Toshiba WT8-A BYT + CRC-PMIC PWM -Thundersoft TS178 BYT + CRC-PMIC PWM, inverse PWM -Asus T100HA CHT + CRC-PMIC PWM -Terra Pad 1061 BYT + LPSS PWM -Trekstor Twin 10.1 BYT + LPSS PWM -Asus T101HA CHT + CRC-PMIC PWM -GPD Pocket CHT + CRC-PMIC PWM Regards, Hans From hdegoede at redhat.com Sat Jun 6 20:25:46 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:46 +0200 Subject: [Intel-gfx] [PATCH 01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-2-hdegoede@redhat.com> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM controller gets poked from the _PS0 method of the graphics-card device: Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ If (((Local0 & 0x03) == 0x03)) { PSAT &= 0xFFFFFFFC Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ RSTA = Zero RSTF = Zero RSTA = One RSTF = One PWMB |= 0xC0000000 PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */ } Where PSAT is the power-status register of the PWM controller, so if it is in D3 when the GFX0 device's PS0 method runs then it will turn it on and restore the PWM ctrl register value it saved from its PS3 handler. Note not only does it restore it, it ors it with 0xC0000000 turning it on at a time where we may not want it to get turned on at all. The pwm_get call which the i915 driver does to get a reference to the PWM controller, already adds a device-link making the GFX0 device a consumer of the PWM device. So it should already have been resumed when the above AML runs and the AML should thus not do its undesirable poking of the PWM controller register. But the PCI core powers on PCI devices in the no-irq resume phase and thus calls the troublesome PS0 method in the no-irq resume phase. Where as LPSS devices by default are resumed in the early resume phase. This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc struct, so that Cherry Trail PWM controllers will be resumed in the no-irq phase. Together with the device-link added by the pwm-get this ensures that the PWM controller will be on when the troublesome PS0 method runs, which stops it from poking the PWM controller. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/acpi/acpi_lpss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 5e2bfbcf526f..67892fc0b822 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = { .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, .prv_offset = 0x800, .setup = bsw_pwm_setup, + .resume_from_noirq = true, }; static const struct lpss_device_desc byt_uart_dev_desc = { -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:47 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:47 +0200 Subject: [Intel-gfx] [PATCH 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-3-hdegoede@redhat.com> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM controller gets turned off from the _PS3 method of the graphics-card dev: Method (_PS3, 0, Serialized) // _PS3: Power State 3 { ... PWMB = PWMC /* \_SB_.PCI0.GFX0.PWMC */ PSAT |= 0x03 Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ ... } Where PSAT is the power-status register of the PWM controller. Since the i915 driver will do a pwm_get on the pwm device as it uses it to control the LCD panel backlight, there is a device-link marking the i915 device as a consumer of the pwm device. So that the PWM controller will always be suspended after the i915 driver suspends (which is the right thing to do). This causes the above GFX0 PS3 AML code to run before acpi_lpss.c calls acpi_lpss_save_ctx(). So on these devices the PWM controller will already be off when acpi_lpss_save_ctx() runs. This causes it to read/save all 1-s (0xffffffff) as ctx register values. When these bogus values get restored on resume the PWM controller actually keeps working, since most bits are reserved, but this does set bit 3 of the LPSS General purpose register, which for the PWM controller has the following function: "This bit is re-used to support 32kHz slow mode. Default is 19.2MHz as PWM source clock". This causes the clock of the PWM controller to switch from 19.2MHz to 32KHz, which is a slow-down of a factor 600. Suprisingly enough so far there have been few bug reports about this. This is likely because the i915 driver was hardcoding the PWM frequency to 46 KHz, which divided by 600 would result in a PWM frequency of aprox. 78 Hz, which mostly still works fine. There are some bug reports about the LCD backlight flickering after suspend/resume which are likely caused by this issue. But with the upcoming patch-series to finally switch the i915 drivers code for external PWM controllers to use the atomic API and to honor the PWM frequency specified in the video BIOS (VBT), this becomes a much bigger problem. On most cases the VBT specifies either 200 Hz or 20 KHz as PWM frequency, which with the mentioned issue ends up being either 1/3 Hz, where the backlight actually visible blinks on and off every 3s, or in 33 Hz and horrible flickering of the backlight. There are a number of possible solutions to this problem: 1. Make acpi_lpss_save_ctx() run before GFX0._PS3 Pro: Clean solution from pov of not medling with save/restore ctx code Con: As mentioned the current ordering is the right thing to do Con: Requires assymmetry in at what suspend/resume phase we do the save vs restore, requiring more suspend/resume ordering hacks in already convoluted acpi_lpss.c suspend/resume code. 2. Do some sort of save once mode for the LPSS ctx Pro: Reasonably clean Con: Needs a new LPSS flag + code changes to handle the flag 3. Detect we have failed to save the ctx registers and do not restore them Pro: Not PWM specific, might help with issues on other LPSS devices too Con: If we can get away with not restoring the ctx why bother with it at all? 4. Do not save the ctx for CHT PWM controllers Pro: Clean, as simple as dropping a flag? Con: Not so simple as dropping a flag, needs a new flag to ensure that we still do lpss_deassert_reset() on device activation. 5. Make the pwm-lpss code fixup the LPSS-context registers Pro: Keeps acpi_lpss.c code clean Con: Moves knowledge of LPSS-context into the pwm-lpss.c code 1 and 5 both do not seem to be a desirable way forward. 3 and 4 seem ok, but they both assume that restoring the LPSS-context registers is not necessary. I have done a couple of test and those do show that restoring the LPSS-context indeed does not seem to be necessary on devices using s2idle suspend (and successfully reaching S0i3). But I have no hardware to test deep / S3 suspend. So I'm not sure that not restoring the context is safe. That leaves solution 2, which is about as simple / clean as 3 and 4, so this commit fixes the described problem by implementing a new LPSS_SAVE_CTX_ONCE flag and setting that for the CHT PWM controllers. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/acpi/acpi_lpss.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 67892fc0b822..26933e6b7b8c 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -68,6 +68,14 @@ ACPI_MODULE_NAME("acpi_lpss"); #define LPSS_LTR BIT(3) #define LPSS_SAVE_CTX BIT(4) #define LPSS_NO_D3_DELAY BIT(5) +/* + * For some devices the DSDT AML code for another device turns off the device + * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) + * as ctx register values. + * Luckily these devices always use the same ctx register values, so we can + * work around this by saving the ctx registers once on activation. + */ +#define LPSS_SAVE_CTX_ONCE BIT(6) struct lpss_private_data; @@ -254,7 +262,7 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { }; static const struct lpss_device_desc bsw_pwm_dev_desc = { - .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, + .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, .prv_offset = 0x800, .setup = bsw_pwm_setup, .resume_from_noirq = true, @@ -885,9 +893,14 @@ static int acpi_lpss_activate(struct device *dev) * we have to deassert reset line to be sure that ->probe() will * recognize the device. */ - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) lpss_deassert_reset(pdata); +#ifdef CONFIG_PM + if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) + acpi_lpss_save_ctx(dev, pdata); +#endif + return 0; } @@ -1031,7 +1044,7 @@ static int acpi_lpss_resume(struct device *dev) acpi_lpss_d3_to_d0_delay(pdata); - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) acpi_lpss_restore_ctx(dev, pdata); return 0; -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:48 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:48 +0200 Subject: [Intel-gfx] [PATCH 03/16] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-4-hdegoede@redhat.com> When the user requests a high enough period ns value, then the calculations in pwm_lpss_prepare() might result in a base_unit value of 0. But according to the data-sheet the way the PWM controller works is that each input clock-cycle the base_unit gets added to a N bit counter and that counter overflowing determines the PWM output frequency. Adding 0 to the counter is a no-op. The data-sheet even explicitly states that writing 0 to the base_unit bits will result in the PWM outputting a continuous 0 signal. base_unit values > (base_unit_range / 256), or iow base_unit values using the 8 most significant bits, cause loss of resolution of the duty-cycle. E.g. assuming a base_unit_range of 65536 steps, then a base_unit value of 768 (256 * 3), limits the duty-cycle resolution to 65536 / 768 = 85 steps. Clamp the max base_unit value to base_unit_range / 32 to ensure a duty-cycle resolution of at least 32 steps. This limits the maximum output frequency to 600 KHz / 780 KHz depending on the base clock. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-lpss.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 9d965ffe66d1..cae74ce61654 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -97,6 +97,14 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, freq *= base_unit_range; base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); + /* + * base_unit must not be 0 and for values > (base_unit_range / 256) + * (values using the 8 most significant bits) the duty-cycle resolution + * degrades. Clamp the maximum value to base_unit_range / 32 which + * leaves a duty-cycle resolution of 32 steps. + */ + base_unit = clamp_t(unsigned long long, base_unit, 1, + base_unit_range / 32); on_time_div = 255ULL * duty_ns; do_div(on_time_div, period_ns); @@ -105,7 +113,6 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, orig_ctrl = ctrl = pwm_lpss_read(pwm); ctrl &= ~PWM_ON_TIME_DIV_MASK; ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); - base_unit &= base_unit_range; ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:49 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:49 +0200 Subject: [Intel-gfx] [PATCH 04/16] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-5-hdegoede@redhat.com> According to the data-sheet the way the PWM controller works is that each input clock-cycle the base_unit gets added to a N bit counter and that counter overflowing determines the PWM output frequency. So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, after 65535 input clock-cycles the counter has been increased from 0 to 65535 and it will overflow on the next cycle, so it will overflow after every 65536 clock cycles and thus the calculations done in pwm_lpss_prepare() should use 65536 and not 65535. This commit fixes this. Note this also aligns the calculations in pwm_lpss_prepare() with those in pwm_lpss_get_state(). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-lpss.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index cae74ce61654..a764e062103b 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -93,7 +93,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, * The equation is: * base_unit = round(base_unit_range * freq / c) */ - base_unit_range = BIT(lpwm->info->base_unit_bits) - 1; + base_unit_range = BIT(lpwm->info->base_unit_bits); freq *= base_unit_range; base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); @@ -112,7 +112,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, orig_ctrl = ctrl = pwm_lpss_read(pwm); ctrl &= ~PWM_ON_TIME_DIV_MASK; - ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); + ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:50 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:50 +0200 Subject: [Intel-gfx] [PATCH 05/16] pwm: lpss: Set SW_UPDATE bit when enabling the PWM In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-6-hdegoede@redhat.com> On the LPSS PWM controller found on Bay Trail (BYT) and Cherry Trail (CHT) platforms, the following sequence results in an output duty-cycle of 100% independent of what the duty-cycle requested in the ctrl-reg is: 1. Clear ENABLE bit in ctrl register 2. Let the machine reach a S0i3 low power state 3. Set the ENABLE bit in the ctrl register The LPSS PWM controller has a mechanism where the ctrl register value and the actual base-unit and on-time-div values used are latched. When software sets the SW_UPDATE bit then at the end of the current PWM cycle, the new values from the ctrl-register will be latched into the actual registers, and the SW_UPDATE bit will be cleared. Note on BYT and CHT the ENABLE bit must be set before waiting for the SW_UPDATE bit to clear, otherwise the SW_UPDATE bit will never clear (this is indicated in the pwm-lpss.c code by lpwm->info->bypass being false). My theory about why this is happening is that when we hit S0i3 the part which holds the latched values gets turned off and when its turned back on again at least the on-time-div value has been lost and gets reset to 0 which corresponds to an output duty-cycle of 100%. Testing has shown that setting the SW_UPDATE bit to request latching the ctrl-register values into the actual registers (again) fixes this, confirming this theory. In the past there have been issues where setting the SW_UPDATE bit when nothing has changed would lead to the next ctrl register changing being ignored, see commit 2153bbc12f77 ("pwm: lpss: Only set update bit if we are actually changing the settings"), so we should only set the SW_UPDATE bit when actually changing the ENABLE bit from 0 to 1. When looking into how to fix this I noticed that on platforms where lpwm->info->bypass == false we unnecessarily do 2 read-modify-write cycles of the ctrl register, one to set the base-unit and on-time-div, immediately followed by another to set the ENABLE bit. This commit fixes the 100% duty cycle issue by folding the setting of the ENABLE bit into pwm_lpss_prepare(), which already checks if any bits in the ctrl-register have actually changed and if that is the case then sets the SW_UPDATE bit. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-lpss.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index a764e062103b..2cb0e2a9c08c 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -80,7 +80,7 @@ static inline int pwm_lpss_is_updating(struct pwm_device *pwm) } static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, - int duty_ns, int period_ns) + int duty_ns, int period_ns, bool enable) { unsigned long long on_time_div; unsigned long c = lpwm->info->clk_rate, base_unit_range; @@ -115,6 +115,8 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; + if (enable) + ctrl |= PWM_ENABLE; if (orig_ctrl != ctrl) { pwm_lpss_write(pwm, ctrl); @@ -142,8 +144,9 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, pm_runtime_put(chip->dev); return ret; } - pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); - pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); + pwm_lpss_prepare(lpwm, pwm, + state->duty_cycle, state->period, + lpwm->info->bypass == false); ret = pwm_lpss_wait_for_update(pwm); if (ret) { pm_runtime_put(chip->dev); @@ -154,7 +157,8 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, ret = pwm_lpss_is_updating(pwm); if (ret) return ret; - pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); + pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, + state->period, false); return pwm_lpss_wait_for_update(pwm); } } else if (pwm_is_enabled(pwm)) { -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:51 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:51 +0200 Subject: [Intel-gfx] [PATCH 06/16] pwm: lpss: Add debug prints, test patch for moving i915 to atomic PWM In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-7-hdegoede@redhat.com> Add debug prints, test patch for moving i915 to atomic PWM. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-lpss.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 2cb0e2a9c08c..c1f8e6da0cd7 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -119,6 +119,8 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, ctrl |= PWM_ENABLE; if (orig_ctrl != ctrl) { + dev_err(pwm->chip->dev, "prepare 0x%08x -> 0x%08lx\n", + orig_ctrl, ctrl | PWM_SW_UPDATE); pwm_lpss_write(pwm, ctrl); pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE); } @@ -126,8 +128,15 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond) { - if (cond) - pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); + if (cond) { + u32 orig_ctrl, ctrl; + + orig_ctrl = ctrl = pwm_lpss_read(pwm); + ctrl |= PWM_ENABLE; + dev_err(pwm->chip->dev, "enable 0x%08x -> 0x%08x\n", + orig_ctrl, ctrl); + pwm_lpss_write(pwm, ctrl); + } } static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, @@ -200,6 +209,9 @@ static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm, state->enabled = !!(ctrl & PWM_ENABLE); pm_runtime_put(chip->dev); + + dev_err(pwm->chip->dev, "initial state 0x%08x period %d duty_cycle %d enabled %d\n", + ctrl, state->period, state->duty_cycle, state->enabled); } static const struct pwm_ops pwm_lpss_ops = { -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:53 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:53 +0200 Subject: [Intel-gfx] [PATCH 08/16] pwm: crc: Fix off-by-one error in the clock-divider calculations In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-9-hdegoede@redhat.com> The CRC PWM controller has a clock-divider which divides the clock with a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx defines, this range maps to a register value of 0-127. So after calculating the clock-divider we must subtract 1 to get the register value, unless the requested frequency was so high that the calculation has already resulted in a (rounded) divider value of 0. Note that before this fix, setting a period of PWM_MAX_PERIOD_NS which corresponds to the max. divider value of 128 could have resulted in a bug where the code would use 128 as divider-register value which would have resulted in an actual divider value of 0 (and the enable bit being set). A rounding error stopped this bug from actually happen. This same rounding error means that after the subtraction of 1 it is impossible to set the divider to 128. Also bump PWM_MAX_PERIOD_NS by 1 ns to allow setting a divider of 128 (register-value 127). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 43fc912c1fe9..5ba2a65c524c 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -22,7 +22,7 @@ #define PWM_MAX_LEVEL 0xFF #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ -#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ +#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */ #define NSEC_PER_MHZ 1000 @@ -75,6 +75,9 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, /* changing the clk divisor, need to disable fisrt */ crc_pwm_disable(c, pwm); clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:55 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:55 +0200 Subject: [Intel-gfx] [PATCH 10/16] pwm: crc: Enable/disable PWM output on enable/disable In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-11-hdegoede@redhat.com> The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, this commit makes crc_pwm_disable() clear it on disable and makes crc_pwm_enable() set it again on re-enable. This should disable the internal (divided) PWM clock and tri-state the PWM output pin when disabled, saving some power. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index ef49a6e3c4d6..53734bcf67e1 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -41,10 +41,24 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) return container_of(pc, struct crystalcove_pwm, chip); } +static int crc_pwm_calc_clk_div(int period_ns) +{ + int clk_div; + + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; + + return clk_div; +} + static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div | PWM_OUTPUT_ENABLE); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); return 0; @@ -53,8 +67,10 @@ static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div); } static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, @@ -70,16 +86,10 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, } if (pwm_get_period(pwm) != period_ns) { - int clk_div; + int clk_div = crc_pwm_calc_clk_div(period_ns); /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); - - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); - /* clk_div 1 - 128, maps to register values 0-127 */ - if (clk_div > 0) - clk_div--; - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); } -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:52 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:52 +0200 Subject: [Intel-gfx] [PATCH 07/16] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-8-hdegoede@redhat.com> While looking into adding atomic-pwm support to the pwm-crc driver I noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and there is a clock-divider which divides this with a value between 1-128, and there are 256 duty-cycle steps. The pwm-crc code before this commit assumed that a clock-divider setting of 1 means that the PWM output is running at 6 MHZ, if that is true, where do these 256 duty-cycle steps come from? This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that seems unlikely for a PMIC which is using a silicon process optimized for power-switching transistors. It is way more likely that there is an 8 bit counter for the duty cycle which acts as an extra fixed divider wrt the PWM output frequency. The main user of the pwm-crc driver is the i915 GPU driver which uses it for backlight control. Lets compare the PWM register values set by the video-BIOS (the GOP), assuming the extra fixed divider is present versus the PWM frequency specified in the Video-BIOS-Tables: Device: PWM Hz set by BIOS PWM Hz specified in VBT Asus T100TA 200 200 Asus T100HA 200 200 Lenovo Miix 2 8 23437 20000 Toshiba WT8-A 23437 20000 So as we can see if we assume the extra division by 256 then the register values set by the GOP are an exact match for the VBT values, where as otherwise the values would be of by a factor of 256. This commit fixes the period / duty_cycle calculations to take the extra division by 256 into account. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 272eeb071147..43fc912c1fe9 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -21,8 +21,10 @@ #define PWM_MAX_LEVEL 0xFF -#define PWM_BASE_CLK 6000000 /* 6 MHz */ -#define PWM_MAX_PERIOD_NS 21333 /* 46.875KHz */ +#define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ +#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ + +#define NSEC_PER_MHZ 1000 /** * struct crystalcove_pwm - Crystal Cove PWM controller @@ -72,7 +74,7 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, /* changing the clk divisor, need to disable fisrt */ crc_pwm_disable(c, pwm); - clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC; + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:54 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:54 +0200 Subject: [Intel-gfx] [PATCH 09/16] pwm: crc: Fix period changes not having any effect In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-10-hdegoede@redhat.com> The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register I strongly suspect that the BACKLIGHT_EN register at address 0x51 really controls a separate output-only GPIO which is connected to the LCD panels backlight-enable input. Like how the PANEL_EN register at address 0x52 controls an output-only GPIO which is earmarked for the LCD panel's enable pin. If this is correct then this GPIO should really be added to the gpio-crystalcove.c driver and the PWM driver should stop poking it. But I've been unable to come up with a definitive answer here, so I'm keeping this as is for now. As the comment in the old code already indicates we must disable the PWM before we can change the clock divider. But the crc_pwm_disable() and crc_pwm_enable() calls the old code make for this only change the BACKLIGHT_EN register; and the value of that register does not matter for changing the period / the divider. What does matter is that the PWM_OUTPUT_ENABLE bit must be cleared before a new value can be written. This commit modifies crc_pwm_config() to clear PWM_OUTPUT_ENABLE instead when changing the period, so that period changes actually work. Note this fix will cause a significant behavior change on some devices using the CRC PWM output to drive their backlight. Before the PWM would always run with the output frequency configured by the BIOS at boot, now the period time specified by the i915 driver will actually be honored. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 5ba2a65c524c..ef49a6e3c4d6 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -72,8 +72,9 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, if (pwm_get_period(pwm) != period_ns) { int clk_div; - /* changing the clk divisor, need to disable fisrt */ - crc_pwm_disable(c, pwm); + /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); /* clk_div 1 - 128, maps to register values 0-127 */ if (clk_div > 0) @@ -81,9 +82,6 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); - - /* enable back */ - crc_pwm_enable(c, pwm); } /* change the pwm duty cycle */ -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:56 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:56 +0200 Subject: [Intel-gfx] [PATCH 11/16] pwm: crc: Implement apply() method to support the new atomic PWM API In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-12-hdegoede@redhat.com> Replace the enable, disable and config pwm_ops with an apply op, to support the new atomic PWM API. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 107 +++++++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 48 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 53734bcf67e1..58c7e9ef7278 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -41,70 +41,81 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) return container_of(pc, struct crystalcove_pwm, chip); } -static int crc_pwm_calc_clk_div(int period_ns) +static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) { - int clk_div; - - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); - /* clk_div 1 - 128, maps to register values 0-127 */ - if (clk_div > 0) - clk_div--; - - return clk_div; -} - -static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); - int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); - - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div | PWM_OUTPUT_ENABLE); - regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); - - return 0; -} - -static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); - int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); - - regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div); -} - -static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, - int duty_ns, int period_ns) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); + int err, clk_div, level, pwm_output_enable; struct device *dev = crc_pwm->chip.dev; - int level; - if (period_ns > PWM_MAX_PERIOD_NS) { + if (state->period > PWM_MAX_PERIOD_NS) { dev_err(dev, "un-supported period_ns\n"); return -EINVAL; } - if (pwm_get_period(pwm) != period_ns) { - int clk_div = crc_pwm_calc_clk_div(period_ns); + if (state->polarity != PWM_POLARITY_NORMAL) + return -ENOTSUPP; + + if (pwm_is_enabled(pwm) && !state->enabled) { + err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); + if (err) { + dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err); + return err; + } + } + + if (pwm_get_duty_cycle(pwm) != state->duty_cycle || + pwm_get_period(pwm) != state->period) { + level = state->duty_cycle * PWM_MAX_LEVEL / state->period; + err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level); + if (err) { + dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err); + return err; + } + } + + if (pwm_is_enabled(pwm) && state->enabled && + pwm_get_period(pwm) != state->period) { /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, - clk_div | PWM_OUTPUT_ENABLE); + err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); + if (err) { + dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err); + return err; + } } - /* change the pwm duty cycle */ - level = duty_ns * PWM_MAX_LEVEL / period_ns; - regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level); + if (pwm_get_period(pwm) != state->period || + pwm_is_enabled(pwm) != state->enabled) { + clk_div = PWM_BASE_CLK_MHZ * state->period / + (256 * NSEC_PER_MHZ); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; + + pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0; + + err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, + clk_div | pwm_output_enable); + if (err) { + dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err); + return err; + } + } + + if (!pwm_is_enabled(pwm) && state->enabled) { + err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); + if (err) { + dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err); + return err; + } + } return 0; } static const struct pwm_ops crc_pwm_ops = { - .config = crc_pwm_config, - .enable = crc_pwm_enable, - .disable = crc_pwm_disable, + .apply = crc_pwm_apply, }; static int crystalcove_pwm_probe(struct platform_device *pdev) -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:57 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:57 +0200 Subject: [Intel-gfx] [PATCH 12/16] pwm: crc: Implement get_state() method In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-13-hdegoede@redhat.com> Implement the pwm_ops.get_state() method to complete the support for the new atomic PWM API. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 58c7e9ef7278..6c75a3470bc8 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -114,8 +114,37 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return 0; } +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); + struct device *dev = crc_pwm->chip.dev; + unsigned int clk_div, clk_div_reg, duty_cycle_reg; + int error; + + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); + if (error) { + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); + return; + } + + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); + if (error) { + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); + return; + } + + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; + + state->period = clk_div * NSEC_PER_MHZ * 256 / PWM_BASE_CLK_MHZ; + state->duty_cycle = duty_cycle_reg * state->period / PWM_MAX_LEVEL; + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); +} + static const struct pwm_ops crc_pwm_ops = { .apply = crc_pwm_apply, + .get_state = crc_pwm_get_state, }; static int crystalcove_pwm_probe(struct platform_device *pdev) -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:58 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:58 +0200 Subject: [Intel-gfx] [PATCH 13/16] drm/i915: panel: Add get_vbt_pwm_freq() helper In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-14-hdegoede@redhat.com> Factor the code which checks and drm_dbg_kms-s the VBT PWM frequency out of get_backlight_max_vbt(). This is a preparation patch for honering the VBT PWM frequency for devices which use an external PWM controller (devices using pwm_setup_backlight()). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/gpu/drm/i915/display/intel_panel.c | 27 ++++++++++++++-------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 3c5056dbf607..8efdd9f08a08 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1543,18 +1543,9 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul); } -static u32 get_backlight_max_vbt(struct intel_connector *connector) +static u16 get_vbt_pwm_freq(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_panel *panel = &connector->panel; u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz; - u32 pwm; - - if (!panel->backlight.hz_to_pwm) { - drm_dbg_kms(&dev_priv->drm, - "backlight frequency conversion not supported\n"); - return 0; - } if (pwm_freq_hz) { drm_dbg_kms(&dev_priv->drm, @@ -1567,6 +1558,22 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector) pwm_freq_hz); } + return pwm_freq_hz; +} + +static u32 get_backlight_max_vbt(struct intel_connector *connector) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + u16 pwm_freq_hz = get_vbt_pwm_freq(dev_priv); + u32 pwm; + + if (!panel->backlight.hz_to_pwm) { + drm_dbg_kms(&dev_priv->drm, + "backlight frequency conversion not supported\n"); + return 0; + } + pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz); if (!pwm) { drm_dbg_kms(&dev_priv->drm, -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:25:59 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:25:59 +0200 Subject: [Intel-gfx] [PATCH 14/16] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-15-hdegoede@redhat.com> So far for devices using an external PWM controller (devices using pwm_setup_backlight()), we have been hardcoding the period-time passed to pwm_config() to 21333 ns. I suspect this was done because many VBTs set the PWM frequency to 200 which corresponds to a period-time of 5000000 ns, which greatly exceeds the PWM_MAX_PERIOD_NS define in the Crystal Cove PMIC PWM driver, which used to be 21333. This PWM_MAX_PERIOD_NS define was actually based on a bug in the PWM driver where its period and duty-cycle times where off by a factor of 256. Due to this bug the hardcoded CRC_PMIC_PWM_PERIOD_NS value of 21333 would result in the PWM driver using its divider of 128, which would result in a PWM output frequency of 6000000 Hz / 256 / 128 = 183 Hz. So actually pretty close to the default VBT value of 200 Hz. Now that this bug in the pwm-crc driver is fixed, we can actually use the VBT defined frequency. This is important because: a) With the pwm-crc driver fixed it will now translate the hardcoded CRC_PMIC_PWM_PERIOD_NS value of 21333 ns / 46 Khz to a PWM output frequency of 23 KHz (the max it can do). b) The pwm-lpss driver used on many models has always honored the 21333 ns / 46 Khz request Some panels do not like such high output frequencies. E.g. on a Terra Pad 1061 tablet, using the LPSS PWM controller, the backlight would go from off to max, when changing the sysfs backlight brightness value from 90-100%, anything under aprox. 90% would turn the backlight fully off. Honoring the VBT specified PWM frequency will also hopefully fix the various bug reports which we have received about users perceiving the backlight to flicker after a suspend/resume cycle. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_panel.c | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index b24266c624fa..24ea4a7b6dde 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -223,6 +223,7 @@ struct intel_panel { bool util_pin_active_low; /* bxt+ */ u8 controller; /* bxt+ only */ struct pwm_device *pwm; + int pwm_period_ns; /* DPCD backlight */ u8 pwmgen_bit_count; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 8efdd9f08a08..14e611c92194 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -40,8 +40,6 @@ #include "intel_dsi_dcs_backlight.h" #include "intel_panel.h" -#define CRC_PMIC_PWM_PERIOD_NS 21333 - void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, struct drm_display_mode *adjusted_mode) @@ -597,7 +595,7 @@ static u32 pwm_get_backlight(struct intel_connector *connector) int duty_ns; duty_ns = pwm_get_duty_cycle(panel->backlight.pwm); - return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS); + return DIV_ROUND_UP(duty_ns * 100, panel->backlight.pwm_period_ns); } static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -671,9 +669,10 @@ static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; - int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); + int duty_ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - pwm_config(panel->backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS); + pwm_config(panel->backlight.pwm, duty_ns, + panel->backlight.pwm_period_ns); } static void @@ -1917,6 +1916,9 @@ static int pwm_setup_backlight(struct intel_connector *connector, return -ENODEV; } + panel->backlight.pwm_period_ns = NSEC_PER_SEC / + get_vbt_pwm_freq(dev_priv); + /* * FIXME: pwm_apply_args() should be removed when switching to * the atomic PWM API. @@ -1926,9 +1928,10 @@ static int pwm_setup_backlight(struct intel_connector *connector, panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ level = intel_panel_compute_brightness(connector, 100); - ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); + ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - retval = pwm_config(panel->backlight.pwm, ns, CRC_PMIC_PWM_PERIOD_NS); + retval = pwm_config(panel->backlight.pwm, ns, + panel->backlight.pwm_period_ns); if (retval < 0) { drm_err(&dev_priv->drm, "Failed to configure the pwm chip\n"); pwm_put(panel->backlight.pwm); @@ -1937,7 +1940,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, } level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, - CRC_PMIC_PWM_PERIOD_NS); + panel->backlight.pwm_period_ns); panel->backlight.level = intel_panel_compute_brightness(connector, level); panel->backlight.enabled = panel->backlight.level != 0; -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:26:00 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:26:00 +0200 Subject: [Intel-gfx] [PATCH 15/16] drm/i915: panel: Honor the VBT PWM min setting for devs with an external PWM controller In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-16-hdegoede@redhat.com> So far for devices using an external PWM controller (devices using pwm_setup_backlight()), we have been hardcoding the minimum allowed PWM level to 0. But several of these devices specify a non 0 minimum setting in their VBT. Change pwm_setup_backlight() to use get_backlight_min_vbt() to get the minimum level. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/gpu/drm/i915/display/intel_panel.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 14e611c92194..cb28b9908ca4 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1925,8 +1925,8 @@ static int pwm_setup_backlight(struct intel_connector *connector, */ pwm_apply_args(panel->backlight.pwm); - panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ + panel->backlight.min = get_backlight_min_vbt(connector); level = intel_panel_compute_brightness(connector, 100); ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); @@ -1941,8 +1941,9 @@ static int pwm_setup_backlight(struct intel_connector *connector, level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, panel->backlight.pwm_period_ns); - panel->backlight.level = - intel_panel_compute_brightness(connector, level); + level = intel_panel_compute_brightness(connector, level); + panel->backlight.level = clamp(level, panel->backlight.min, + panel->backlight.max); panel->backlight.enabled = panel->backlight.level != 0; drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n", -- 2.26.2 From hdegoede at redhat.com Sat Jun 6 20:26:01 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 6 Jun 2020 22:26:01 +0200 Subject: [Intel-gfx] [PATCH 16/16] drm/i915: panel: Use atomic PWM API for devs with an external PWM controller In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200606202601.48410-17-hdegoede@redhat.com> Now that the PWM drivers which we use have been converted to the atomic PWM API, we can move the i915 panel code over to using the atomic PWM API. The removes a long standing FIXME and this removes a flicker where the backlight brightness would jump to 100% when i915 loads even if using the fastset path. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- .../drm/i915/display/intel_display_types.h | 3 +- drivers/gpu/drm/i915/display/intel_panel.c | 73 +++++++++---------- 2 files changed, 37 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 24ea4a7b6dde..48afb2925271 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -28,6 +28,7 @@ #include <linux/async.h> #include <linux/i2c.h> +#include <linux/pwm.h> #include <linux/sched/clock.h> #include <drm/drm_atomic.h> @@ -223,7 +224,7 @@ struct intel_panel { bool util_pin_active_low; /* bxt+ */ u8 controller; /* bxt+ only */ struct pwm_device *pwm; - int pwm_period_ns; + struct pwm_state pwm_state; /* DPCD backlight */ u8 pwmgen_bit_count; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index cb28b9908ca4..a0f76343f381 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -592,10 +592,11 @@ static u32 bxt_get_backlight(struct intel_connector *connector) static u32 pwm_get_backlight(struct intel_connector *connector) { struct intel_panel *panel = &connector->panel; - int duty_ns; + int duty_ns, period_ns; duty_ns = pwm_get_duty_cycle(panel->backlight.pwm); - return DIV_ROUND_UP(duty_ns * 100, panel->backlight.pwm_period_ns); + period_ns = pwm_get_period(panel->backlight.pwm); + return DIV_ROUND_UP(duty_ns * 100, period_ns); } static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -669,10 +670,10 @@ static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; - int duty_ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - pwm_config(panel->backlight.pwm, duty_ns, - panel->backlight.pwm_period_ns); + panel->backlight.pwm_state.duty_cycle = + DIV_ROUND_UP(level * panel->backlight.pwm_state.period, 100); + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } static void @@ -841,10 +842,8 @@ static void pwm_disable_backlight(const struct drm_connector_state *old_conn_sta struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct intel_panel *panel = &connector->panel; - /* Disable the backlight */ - intel_panel_actually_set_backlight(old_conn_state, 0); - usleep_range(2000, 3000); - pwm_disable(panel->backlight.pwm); + panel->backlight.pwm_state.enabled = false; + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -1176,9 +1175,14 @@ static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state, { struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_panel *panel = &connector->panel; + int level = panel->backlight.level; - pwm_enable(panel->backlight.pwm); - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + level = intel_panel_compute_brightness(connector, level); + + panel->backlight.pwm_state.duty_cycle = + DIV_ROUND_UP(level * panel->backlight.pwm_state.period, 100); + panel->backlight.pwm_state.enabled = true; + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } static void __intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -1897,8 +1901,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_panel *panel = &connector->panel; const char *desc; - u32 level, ns; - int retval; + u32 level; /* Get the right PWM chip for DSI backlight according to VBT */ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { @@ -1916,36 +1919,30 @@ static int pwm_setup_backlight(struct intel_connector *connector, return -ENODEV; } - panel->backlight.pwm_period_ns = NSEC_PER_SEC / - get_vbt_pwm_freq(dev_priv); - - /* - * FIXME: pwm_apply_args() should be removed when switching to - * the atomic PWM API. - */ - pwm_apply_args(panel->backlight.pwm); - panel->backlight.max = 100; /* 100% */ panel->backlight.min = get_backlight_min_vbt(connector); - level = intel_panel_compute_brightness(connector, 100); - ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - retval = pwm_config(panel->backlight.pwm, ns, - panel->backlight.pwm_period_ns); - if (retval < 0) { - drm_err(&dev_priv->drm, "Failed to configure the pwm chip\n"); - pwm_put(panel->backlight.pwm); - panel->backlight.pwm = NULL; - return retval; + if (pwm_is_enabled(panel->backlight.pwm) && + pwm_get_period(panel->backlight.pwm)) { + /* PWM is already enabled, use existing settings */ + pwm_get_state(panel->backlight.pwm, &panel->backlight.pwm_state); + + level = DIV_ROUND_UP(panel->backlight.pwm_state.duty_cycle * + 100, panel->backlight.pwm_state.period); + level = intel_panel_compute_brightness(connector, level); + panel->backlight.level = clamp(level, panel->backlight.min, + panel->backlight.max); + panel->backlight.enabled = true; + + drm_dbg_kms(&dev_priv->drm, "PWM already enabled at freq %ld, VBT freq %d, level %d\n", + NSEC_PER_SEC / panel->backlight.pwm_state.period, + get_vbt_pwm_freq(dev_priv), level); + } else { + /* Set period from VBT frequency, leave other setting at 0. */ + panel->backlight.pwm_state.period = + NSEC_PER_SEC / get_vbt_pwm_freq(dev_priv); } - level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, - panel->backlight.pwm_period_ns); - level = intel_panel_compute_brightness(connector, level); - panel->backlight.level = clamp(level, panel->backlight.min, - panel->backlight.max); - panel->backlight.enabled = panel->backlight.level != 0; - drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n", desc); return 0; -- 2.26.2 From patchwork at emeril.freedesktop.org Sat Jun 6 20:47:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 06 Jun 2020 20:47:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBz?= =?utf-8?q?eries_starting_with_=5B01/16=5D_ACPI_/_LPSS=3A_Resume_Cherry_Tr?= =?utf-8?q?ail_PWM_controller_in_no-irq_phase?= In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <159147644811.20628.11733720867934347075@emeril.freedesktop.org> == Series Details == Series: series starting with [01/16] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase URL : https://patchwork.freedesktop.org/series/78071/ State : failure == Summary == Applying: ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase Applying: ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) Applying: pwm: lpss: Add range limit check for the base_unit register value Applying: pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() Applying: pwm: lpss: Set SW_UPDATE bit when enabling the PWM Applying: pwm: lpss: Add debug prints, test patch for moving i915 to atomic PWM error: sha1 information is lacking or useless (drivers/pwm/pwm-lpss.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0006 pwm: lpss: Add debug prints, test patch for moving i915 to atomic PWM When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From dhowells at redhat.com Sun Jun 7 01:06:24 2020 From: dhowells at redhat.com (David Howells) Date: Sun, 07 Jun 2020 02:06:24 +0100 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver Message-ID: <2136072.1591491984@warthog.procyon.org.uk> Hi, I'm seeing the attached oops and panic from the i915 drm driver. I've tried bisecting it, but there's a problem in that one of the merged branches causes the machine to hang without output. The oops for commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 looks like: BUG: kernel NULL pointer dereference, address: 0000000000000000 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 0 P4D 0 Oops: 0000 [#1] SMP PTI CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.7.0-rc2-fscache+ #883 Hardware name: ASUS All Series/H97-PLUS, BIOS 2306 10/09/2014 RIP: 0010:intel_psr_enabled+0xb/0x6e Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 00 20 75 05 45 31 e4 eb 44 80 RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 Call Trace: intel_read_dp_sdp+0x71/0x2c5 hsw_crt_get_config+0x18/0x41 intel_modeset_readout_hw_state+0x24d/0x662 ? do_raw_spin_lock+0x8b/0xcd ? _raw_spin_lock_irqsave+0x10/0x16 intel_modeset_setup_hw_state+0xa8/0xb59 ? __next_node_in+0x39/0x42 ? ww_mutex_lock+0x3d/0x1da ? modeset_lock+0xd4/0x114 ? drm_modeset_lock_all_ctx+0x86/0xcc intel_modeset_init+0x285/0x5bf ? intel_irq_postinstall+0x485/0x4d1 i915_driver_probe+0x1b4/0x49c ? __kernfs_new_node+0x161/0x1b2 ? rpm_resume+0x45e/0x485 i915_pci_probe+0xfd/0x11d ? __pm_runtime_resume+0x51/0x5e local_pci_probe+0x39/0x7a pci_device_probe+0xf5/0x14f ? sysfs_do_create_link_sd.isra.0+0x77/0xa3 really_probe+0x140/0x2a9 driver_probe_device+0x9c/0xd1 device_driver_attach+0x3c/0x55 __driver_attach+0x97/0x9f ? device_driver_attach+0x55/0x55 bus_for_each_dev+0x72/0xa8 bus_add_driver+0x108/0x1b9 driver_register+0x9e/0xd7 ? mipi_dsi_bus_init+0x11/0x11 i915_init+0x58/0x6b do_one_initcall+0x83/0x18a kernel_init_freeable+0x19b/0x1fd ? rest_init+0x9f/0x9f kernel_init+0xa/0xfa ret_from_fork+0x1f/0x30 Modules linked in: CR2: 0000000000000000 ---[ end trace d0c4f561618aeb37 ]--- RIP: 0010:intel_psr_enabled+0xb/0x6e Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 00 20 75 05 45 31 e4 eb 44 80 RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 Kernel Offset: disabled ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 ]--- Decoding the RIP gives: RIP: 0010:intel_psr_enabled (/data/fs/linux-fs/build3/../drivers/gpu/drm/i915/display/intel_display_types.h:1595 /data/fs/linux-fs/build3/../drivers/gpu/drm/i915/display/intel_psr.c:1598) Commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 ("Merge tag 'drm-intel-next-fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next") is definitely bad and logs an oops to the console and panics, but it's a merge. On one side is e20bb857dea2f620ff37ae541ed8aee70e3c89f1 ("Merge tag 'exynos-drm-next-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next"), which hangs. This is also a merge. One side of e20bb is f84e1ba336a4f47ae251e4d2d8a694902571b0df ("drm/exynos-vidi: convert platform driver to use dev_groups") which is good. The other side of c4121 and e20bb derive from the same line of commits, with three patches between. All of these, down to at least 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 ("drm/i915: Update DRIVER_DATE to 20200430") cause the machine to hang without any sort of console output. Commit bfbe1744e4417986419236719922a9a7fda224d1 ("Merge tag 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux into drm-next") is good. Commit 47e51832ae93534d872511ba557115722582d94c ("drm/i915/gvt: use context lrc_reg_state for shadow ppgtt override") is good. I've attached the git log and the config file. David -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: bisect.log URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200607/783048c4/attachment-0002.ksh> -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: .config URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200607/783048c4/attachment-0003.ksh> From dhowells at redhat.com Sun Jun 7 01:17:34 2020 From: dhowells at redhat.com (David Howells) Date: Sun, 07 Jun 2020 02:17:34 +0100 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver In-Reply-To: <2136072.1591491984@warthog.procyon.org.uk> References: <2136072.1591491984@warthog.procyon.org.uk> Message-ID: <2147272.1591492654@warthog.procyon.org.uk> Here's the dmesg from a successful boot (commit f84e1ba336a4f47ae251e4d2d8a694902571b0df). David --- [ 0.007455] Normal [mem 0x0000000100000000-0x000000041fdfffff] [ 0.007456] Movable zone start for each node [ 0.007456] Early memory node ranges [ 0.007457] node 0: [mem 0x0000000000001000-0x0000000000057fff] [ 0.007458] node 0: [mem 0x0000000000059000-0x000000000009efff] [ 0.007459] node 0: [mem 0x0000000000100000-0x00000000af304fff] [ 0.007460] node 0: [mem 0x00000000af30c000-0x00000000af774fff] [ 0.007460] node 0: [mem 0x00000000afbbd000-0x00000000d8b7bfff] [ 0.007461] node 0: [mem 0x00000000d9fff000-0x00000000d9ffffff] [ 0.007461] node 0: [mem 0x0000000100000000-0x000000041fdfffff] [ 0.007845] Zeroed struct page in unavailable ranges: 31541 pages [ 0.007846] Initmem setup node 0 [mem 0x0000000000001000-0x000000041fdfffff] [ 0.007848] On node 0 totalpages: 4162763 [ 0.007849] DMA zone: 64 pages used for memmap [ 0.007849] DMA zone: 24 pages reserved [ 0.007850] DMA zone: 3997 pages, LIFO batch:0 [ 0.007901] DMA32 zone: 13789 pages used for memmap [ 0.007901] DMA32 zone: 882478 pages, LIFO batch:63 [ 0.020153] Normal zone: 51192 pages used for memmap [ 0.020155] Normal zone: 3276288 pages, LIFO batch:63 [ 0.064070] Reserving Intel graphics memory at [mem 0xdb200000-0xdf1fffff] [ 0.064144] ACPI: PM-Timer IO Port: 0x1808 [ 0.064146] ACPI: Local APIC address 0xfee00000 [ 0.064150] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) [ 0.064159] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23 [ 0.064161] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.064162] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [ 0.064163] ACPI: IRQ0 used by override. [ 0.064164] ACPI: IRQ9 used by override. [ 0.064166] Using ACPI (MADT) for SMP configuration information [ 0.064167] ACPI: HPET id: 0x8086a701 base: 0xfed00000 [ 0.064171] [Firmware Bug]: TSC_DEADLINE disabled due to Errata; please update microcode to version: 0x22 (or later) [ 0.064172] smpboot: Allowing 4 CPUs, 0 hotplug CPUs [ 0.064198] [mem 0xdf200000-0xf7ffffff] available for PCI devices [ 0.064204] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns [ 0.077227] setup_percpu: NR_CPUS:4 nr_cpumask_bits:4 nr_cpu_ids:4 nr_node_ids:1 [ 0.077563] percpu: Embedded 54 pages/cpu s181200 r8192 d31792 u524288 [ 0.077569] pcpu-alloc: s181200 r8192 d31792 u524288 alloc=1*2097152 [ 0.077570] pcpu-alloc: [0] 0 1 2 3 [ 0.077588] Built 1 zonelists, mobility grouping on. Total pages: 4097694 [ 0.077588] Policy zone: Normal [ 0.077590] Kernel command line: BOOT_IMAGE=/data/tftp/andromeda-vmlinuz ip=enp3s0:dhcp console=tty0 console=ttyS0,115200 ro root=/dev/sdb2 [ 0.079327] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear) [ 0.080136] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear) [ 0.080167] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.159182] Memory: 16016000K/16651052K available (12290K kernel code, 1927K rwdata, 5372K rodata, 1608K init, 1296K bss, 635052K reserved, 0K cma-reserved) [ 0.159242] Kernel/User page tables isolation: enabled [ 0.159256] ftrace: allocating 47297 entries in 185 pages [ 0.172236] ftrace: allocated 185 pages with 5 groups [ 0.172293] rcu: Hierarchical RCU implementation. [ 0.172294] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.175046] NR_IRQS: 4352, nr_irqs: 456, preallocated irqs: 16 [ 0.175193] rcu: Offload RCU callbacks from CPUs: (none). [ 0.175244] random: get_random_bytes called from start_kernel+0x3f5/0x5c0 with crng_init=0 [ 0.175342] Console: colour dummy device 80x25 [ 0.175458] printk: console [tty0] enabled [ 0.957870] printk: console [ttyS0] enabled [ 0.960753] ACPI: Core revision 20200326 [ 0.963468] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484882848 ns [ 0.971296] APIC: Switch to symmetric I/O mode setup [ 0.975260] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0 [ 0.999294] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x6a6cab8f549, max_idle_ns: 881590883366 ns [ 1.008503] Calibrating delay loop (skipped), value calculated using timer frequency.. 7383.19 BogoMIPS (lpj=14766392) [ 1.012503] pid_max: default: 32768 minimum: 301 [ 1.024069] LSM: Security Framework initializing [ 1.024510] Yama: becoming mindful. [ 1.028507] SELinux: Initializing. [ 1.030772] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear) [ 1.032558] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear) [ 1.036710] mce: CPU0: Thermal monitoring enabled (TM1) [ 1.040511] process: using mwait in idle threads [ 1.043830] Last level iTLB entries: 4KB 1024, 2MB 1024, 4MB 1024 [ 1.044502] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 1024, 1GB 4 [ 1.048505] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization [ 1.052503] Spectre V2 : Spectre mitigation: kernel not compiled with retpoline; no mitigation available! [ 1.052503] Speculative Store Bypass: Vulnerable [ 1.060503] MDS: Vulnerable: Clear CPU buffers attempted, no microcode [ 1.064625] Freeing SMP alternatives memory: 20K [ 1.178187] smpboot: CPU0: Intel(R) Core(TM) i3-4170 CPU @ 3.70GHz (family: 0x6, model: 0x3c, stepping: 0x3) [ 1.180565] Performance Events: PEBS fmt2+, Haswell events, 16-deep LBR, full-width counters, Intel PMU driver. [ 1.184503] ... version: 3 [ 1.188502] ... bit width: 48 [ 1.191292] ... generic registers: 4 [ 1.192502] ... value mask: 0000ffffffffffff [ 1.196502] ... max period: 00007fffffffffff [ 1.200502] ... fixed-purpose events: 3 [ 1.204502] ... event mask: 000000070000000f [ 1.208533] rcu: Hierarchical SRCU implementation. [ 1.212577] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter. [ 1.216539] smp: Bringing up secondary CPUs ... [ 1.220566] x86: Booting SMP configuration: [ 1.223447] .... node #0, CPUs: #1 #2 [ 1.224922] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details. [ 1.228581] #3 [ 1.228891] smp: Brought up 1 node, 4 CPUs [ 1.231764] smpboot: Max logical packages: 1 [ 1.232504] smpboot: Total of 4 processors activated (29532.78 BogoMIPS) [ 1.237746] devtmpfs: initialized [ 1.238667] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 1.248506] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) [ 1.252550] xor: automatically using best checksumming function avx [ 1.256508] thermal_sys: Registered thermal governor 'step_wise' [ 1.256509] thermal_sys: Registered thermal governor 'user_space' [ 1.264534] NET: Registered protocol family 16 [ 1.272557] audit: initializing netlink subsys (disabled) [ 1.276507] audit: type=2000 audit(1591492487.292:1): state=initialized audit_enabled=0 res=1 [ 1.280505] cpuidle: using governor ladder [ 1.284508] cpuidle: using governor menu [ 1.288569] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it [ 1.292503] ACPI: bus type PCI registered [ 1.296538] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf8000000-0xfbffffff] (base 0xf8000000) [ 1.304504] PCI: MMCONFIG at [mem 0xf8000000-0xfbffffff] reserved in E820 [ 1.308507] pmd_set_huge: Cannot satisfy [mem 0xf8000000-0xf8200000] with a huge-page mapping due to MTRR override. [ 1.320528] PCI: Using configuration type 1 for base access [ 1.324555] core: PMU erratum BJ122, BV98, HSD29 worked around, HT is on [ 1.328598] ENERGY_PERF_BIAS: Set to 'normal', was 'performance' [ 1.337943] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages [ 1.672051] raid6: avx2x4 gen() 35252 MB/s [ 1.740050] raid6: avx2x4 xor() 9138 MB/s [ 1.808050] raid6: avx2x2 gen() 32271 MB/s [ 1.876050] raid6: avx2x2 xor() 20587 MB/s [ 1.944050] raid6: avx2x1 gen() 28431 MB/s [ 2.012050] raid6: avx2x1 xor() 16505 MB/s [ 2.080050] raid6: sse2x4 gen() 18324 MB/s [ 2.148050] raid6: sse2x4 xor() 8936 MB/s [ 2.216051] raid6: sse2x2 gen() 16730 MB/s [ 2.284050] raid6: sse2x2 xor() 10417 MB/s [ 2.352050] raid6: sse2x1 gen() 13939 MB/s [ 2.420051] raid6: sse2x1 xor() 8368 MB/s [ 2.420503] raid6: using algorithm avx2x4 gen() 35252 MB/s [ 2.424502] raid6: .... xor() 9138 MB/s, rmw enabled [ 2.428503] raid6: using avx2x2 recovery algorithm [ 2.432530] ACPI: Added _OSI(Module Device) [ 2.436503] ACPI: Added _OSI(Processor Device) [ 2.440506] ACPI: Added _OSI(3.0 _SCP Extensions) [ 2.440506] ACPI: Added _OSI(Processor Aggregator Device) [ 2.444503] ACPI: Added _OSI(Linux-Dell-Video) [ 2.448504] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) [ 2.452503] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics) [ 2.470763] ACPI: 6 ACPI AML tables successfully acquired and loaded [ 2.477867] ACPI: Dynamic OEM Table Load: [ 2.480507] ACPI: SSDT 0xFFFF88840D189400 0003D3 (v01 PmRef Cpu0Cst 00003001 INTL 20051117) [ 2.488608] ACPI: Dynamic OEM Table Load: [ 2.491316] ACPI: SSDT 0xFFFF88840D153000 0005AA (v01 PmRef ApIst 00003000 INTL 20051117) [ 2.497383] ACPI: Dynamic OEM Table Load: [ 2.500506] ACPI: SSDT 0xFFFF88840D185800 000119 (v01 PmRef ApCst 00003000 INTL 20051117) [ 2.509943] ACPI: Interpreter enabled [ 2.512510] ACPI: (supports S0 S5) [ 2.514606] ACPI: Using IOAPIC for interrupt routing [ 2.516531] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 2.524784] ACPI: Enabled 10 GPEs in block 00 to 3F [ 2.529162] ACPI: Power Resource [PG00] (on) [ 2.532789] ACPI: Power Resource [PG01] (on) [ 2.536780] ACPI: Power Resource [PG02] (on) [ 2.548508] ACPI: Power Resource [FN00] (off) [ 2.548575] ACPI: Power Resource [FN01] (off) [ 2.552576] ACPI: Power Resource [FN02] (off) [ 2.556576] ACPI: Power Resource [FN03] (off) [ 2.560574] ACPI: Power Resource [FN04] (off) [ 2.564695] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-3e]) [ 2.568507] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] [ 2.576752] acpi PNP0A08:00: _OSC: platform does not support [PME] [ 2.580671] acpi PNP0A08:00: _OSC: OS now controls [AER PCIeCapability LTR] [ 2.588503] acpi PNP0A08:00: FADT indicates ASPM is unsupported, using BIOS configuration [ 2.592818] PCI host bridge to bus 0000:00 [ 2.596504] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] [ 2.600503] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 2.608503] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] [ 2.612503] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window] [ 2.620503] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window] [ 2.624503] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window] [ 2.632504] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window] [ 2.636503] pci_bus 0000:00: root bus resource [mem 0xdf200000-0xfeafffff window] [ 2.644503] pci_bus 0000:00: root bus resource [bus 00-3e] [ 2.648510] pci 0000:00:00.0: [8086:0c00] type 00 class 0x060000 [ 2.652584] pci 0000:00:01.0: [8086:0c01] type 01 class 0x060400 [ 2.656532] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold [ 2.664616] pci 0000:00:02.0: [8086:041e] type 00 class 0x030000 [ 2.668510] pci 0000:00:02.0: reg 0x10: [mem 0xf7400000-0xf77fffff 64bit] [ 2.672506] pci 0000:00:02.0: reg 0x18: [mem 0xe0000000-0xefffffff 64bit pref] [ 2.680505] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f] [ 2.684576] pci 0000:00:03.0: [8086:0c0c] type 00 class 0x040300 [ 2.688508] pci 0000:00:03.0: reg 0x10: [mem 0xf7c10000-0xf7c13fff 64bit] [ 2.692593] pci 0000:00:14.0: [8086:8cb1] type 00 class 0x0c0330 [ 2.700521] pci 0000:00:14.0: reg 0x10: [mem 0xf7c00000-0xf7c0ffff 64bit] [ 2.704554] pci 0000:00:14.0: PME# supported from D3hot D3cold [ 2.708571] pci 0000:00:16.0: [8086:8cba] type 00 class 0x078000 [ 2.712519] pci 0000:00:16.0: reg 0x10: [mem 0xf7c19000-0xf7c1900f 64bit] [ 2.720554] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold [ 2.724593] pci 0000:00:1a.0: [8086:8cad] type 00 class 0x0c0320 [ 2.728520] pci 0000:00:1a.0: reg 0x10: [mem 0xf7c17000-0xf7c173ff] [ 2.732573] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold [ 2.740572] pci 0000:00:1c.0: [8086:8c90] type 01 class 0x060400 [ 2.744567] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold [ 2.748618] pci 0000:00:1c.2: [8086:8c94] type 01 class 0x060400 [ 2.752568] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold [ 2.756616] pci 0000:00:1c.3: [8086:244e] type 01 class 0x060401 [ 2.764569] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold [ 2.768616] pci 0000:00:1c.4: [8086:8c98] type 01 class 0x060400 [ 2.772567] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold [ 2.776619] pci 0000:00:1d.0: [8086:8ca6] type 00 class 0x0c0320 [ 2.780520] pci 0000:00:1d.0: reg 0x10: [mem 0xf7c16000-0xf7c163ff] [ 2.788558] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold [ 2.792574] pci 0000:00:1f.0: [8086:8cc6] type 00 class 0x060100 [ 2.796657] pci 0000:00:1f.2: [8086:8c82] type 00 class 0x010601 [ 2.800515] pci 0000:00:1f.2: reg 0x10: [io 0xf0b0-0xf0b7] [ 2.804507] pci 0000:00:1f.2: reg 0x14: [io 0xf0a0-0xf0a3] [ 2.808511] pci 0000:00:1f.2: reg 0x18: [io 0xf090-0xf097] [ 2.812507] pci 0000:00:1f.2: reg 0x1c: [io 0xf080-0xf083] [ 2.820507] pci 0000:00:1f.2: reg 0x20: [io 0xf060-0xf07f] [ 2.824507] pci 0000:00:1f.2: reg 0x24: [mem 0xf7c15000-0xf7c157ff] [ 2.828531] pci 0000:00:1f.2: PME# supported from D3hot [ 2.832565] pci 0000:00:1f.3: [8086:8ca2] type 00 class 0x0c0500 [ 2.836516] pci 0000:00:1f.3: reg 0x10: [mem 0xf7c14000-0xf7c140ff 64bit] [ 2.840518] pci 0000:00:1f.3: reg 0x20: [io 0xf040-0xf05f] [ 2.844591] pci 0000:00:01.0: PCI bridge to [bus 01] [ 2.848542] pci 0000:02:00.0: [144d:a801] type 00 class 0x010601 [ 2.856564] pci 0000:02:00.0: reg 0x24: [mem 0xf7b00000-0xf7b01fff] [ 2.860611] pci 0000:02:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x2 link at 0000:00:1c.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link) [ 2.872586] pci 0000:00:1c.0: PCI bridge to [bus 02] [ 2.876506] pci 0000:00:1c.0: bridge window [mem 0xf7b00000-0xf7bfffff] [ 2.884546] pci 0000:03:00.0: [10ec:8168] type 00 class 0x020000 [ 2.888530] pci 0000:03:00.0: reg 0x10: [io 0xe000-0xe0ff] [ 2.892528] pci 0000:03:00.0: reg 0x18: [mem 0xf7a00000-0xf7a00fff 64bit] [ 2.896517] pci 0000:03:00.0: reg 0x20: [mem 0xf0000000-0xf0003fff 64bit pref] [ 2.904598] pci 0000:03:00.0: supports D1 D2 [ 2.907562] pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 2.912630] pci 0000:00:1c.2: PCI bridge to [bus 03] [ 2.916505] pci 0000:00:1c.2: bridge window [io 0xe000-0xefff] [ 2.920505] pci 0000:00:1c.2: bridge window [mem 0xf7a00000-0xf7afffff] [ 2.924505] pci 0000:00:1c.2: bridge window [mem 0xf0000000-0xf00fffff 64bit pref] [ 2.932539] pci 0000:04:00.0: [1b21:1080] type 01 class 0x060401 [ 2.936660] pci 0000:00:1c.3: PCI bridge to [bus 04-05] (subtractive decode) [ 2.944509] pci 0000:00:1c.3: bridge window [io 0x0000-0x0cf7 window] (subtractive decode) [ 2.948503] pci 0000:00:1c.3: bridge window [io 0x0d00-0xffff window] (subtractive decode) [ 2.956503] pci 0000:00:1c.3: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode) [ 2.964503] pci 0000:00:1c.3: bridge window [mem 0x000d0000-0x000d3fff window] (subtractive decode) [ 2.972503] pci 0000:00:1c.3: bridge window [mem 0x000d4000-0x000d7fff window] (subtractive decode) [ 2.980503] pci 0000:00:1c.3: bridge window [mem 0x000d8000-0x000dbfff window] (subtractive decode) [ 2.988503] pci 0000:00:1c.3: bridge window [mem 0x000dc000-0x000dffff window] (subtractive decode) [ 2.996503] pci 0000:00:1c.3: bridge window [mem 0xdf200000-0xfeafffff window] (subtractive decode) [ 3.004527] pci_bus 0000:05: extended config space not accessible [ 3.008570] pci 0000:04:00.0: PCI bridge to [bus 05] (subtractive decode) [ 3.016518] pci 0000:04:00.0: bridge window [io 0x0000-0x0cf7 window] (subtractive decode) [ 3.020504] pci 0000:04:00.0: bridge window [io 0x0d00-0xffff window] (subtractive decode) [ 3.028503] pci 0000:04:00.0: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode) [ 3.036504] pci 0000:04:00.0: bridge window [mem 0x000d0000-0x000d3fff window] (subtractive decode) [ 3.044503] pci 0000:04:00.0: bridge window [mem 0x000d4000-0x000d7fff window] (subtractive decode) [ 3.052503] pci 0000:04:00.0: bridge window [mem 0x000d8000-0x000dbfff window] (subtractive decode) [ 3.060503] pci 0000:04:00.0: bridge window [mem 0x000dc000-0x000dffff window] (subtractive decode) [ 3.068503] pci 0000:04:00.0: bridge window [mem 0xdf200000-0xfeafffff window] (subtractive decode) [ 3.076549] pci 0000:06:00.0: [8086:10fb] type 00 class 0x020000 [ 3.080528] pci 0000:06:00.0: reg 0x10: [mem 0xf7880000-0xf78fffff 64bit] [ 3.088510] pci 0000:06:00.0: reg 0x18: [io 0xd000-0xd01f] [ 3.092522] pci 0000:06:00.0: reg 0x20: [mem 0xf7900000-0xf7903fff 64bit] [ 3.096510] pci 0000:06:00.0: reg 0x30: [mem 0xf7800000-0xf787ffff pref] [ 3.100568] pci 0000:06:00.0: PME# supported from D0 D3hot [ 3.108502] pci 0000:06:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x2 link at 0000:00:1c.4 (capable of 32.000 Gb/s with 5.0 GT/s PCIe x8 link) [ 3.120573] pci 0000:00:1c.4: PCI bridge to [bus 06] [ 3.124504] pci 0000:00:1c.4: bridge window [io 0xd000-0xdfff] [ 3.128505] pci 0000:00:1c.4: bridge window [mem 0xf7800000-0xf79fffff] [ 3.136510] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15) [ 3.140557] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled. [ 3.148557] ACPI: PCI Interrupt Link [LNKC] (IRQs *3 4 5 6 7 10 11 12 14 15) [ 3.152556] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 11 12 14 *15) [ 3.160556] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 *5 6 7 10 11 12 14 15) [ 3.164555] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *10 11 12 14 15) [ 3.172555] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled. [ 3.176556] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 10 11 12 *14 15) [ 3.184849] iommu: Default domain type: Translated [ 3.188515] pci 0000:00:02.0: vgaarb: setting as boot VGA device [ 3.192501] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none [ 3.200505] pci 0000:00:02.0: vgaarb: bridge control possible [ 3.204502] vgaarb: loaded [ 3.205969] SCSI subsystem initialized [ 3.208514] libata version 3.00 loaded. [ 3.208547] ACPI: bus type USB registered [ 3.211270] usbcore: registered new interface driver usbfs [ 3.216511] usbcore: registered new interface driver hub [ 3.220514] usbcore: registered new device driver usb [ 3.220525] pps_core: LinuxPPS API ver. 1 registered [ 3.224505] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti at linux.it> [ 3.232506] PTP clock support registered [ 3.236533] Registered efivars operations [ 3.240551] PCI: Using ACPI for IRQ routing [ 3.244808] PCI: pci_cache_line_size set to 64 bytes [ 3.244851] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff] [ 3.244852] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff] [ 3.244853] e820: reserve RAM buffer [mem 0xaf089018-0xafffffff] [ 3.244854] e820: reserve RAM buffer [mem 0xaf0bc018-0xafffffff] [ 3.244855] e820: reserve RAM buffer [mem 0xaf0ca018-0xafffffff] [ 3.244856] e820: reserve RAM buffer [mem 0xaf305000-0xafffffff] [ 3.244856] e820: reserve RAM buffer [mem 0xaf775000-0xafffffff] [ 3.244857] e820: reserve RAM buffer [mem 0xd8b7c000-0xdbffffff] [ 3.244858] e820: reserve RAM buffer [mem 0xda000000-0xdbffffff] [ 3.244859] e820: reserve RAM buffer [mem 0x41fe00000-0x41fffffff] [ 3.244955] NetLabel: Initializing [ 3.247052] NetLabel: domain hash size = 128 [ 3.248506] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO [ 3.252512] NetLabel: unlabeled traffic allowed by default [ 3.256714] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 [ 3.260504] hpet0: 8 comparators, 64-bit 14.318180 MHz counter [ 3.269516] clocksource: Switched to clocksource tsc-early [ 3.383101] FS-Cache: Loaded [ 3.384737] CacheFiles: Loaded [ 3.386503] pnp: PnP ACPI init [ 3.388461] system 00:00: [io 0x0800-0x087f] has been reserved [ 3.393083] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) [ 3.393108] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active) [ 3.393147] system 00:02: [io 0x1854-0x1857] has been reserved [ 3.397770] system 00:02: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) [ 3.397869] system 00:03: [io 0x0290-0x029f] has been reserved [ 3.402482] system 00:03: [io 0x02a0-0x02af] has been reserved [ 3.407101] system 00:03: [io 0x0a00-0x0aff] has been reserved [ 3.411720] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) [ 3.411768] system 00:04: [io 0x04d0-0x04d1] has been reserved [ 3.416384] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active) [ 3.416625] pnp 00:05: [dma 0 disabled] [ 3.416656] pnp 00:05: Plug and Play ACPI device, IDs PNP0501 (active) [ 3.416710] pnp 00:06: Plug and Play ACPI device, IDs IFX0102 PNP0c31 (active) [ 3.416979] system 00:07: [mem 0xfed1c000-0xfed1ffff] has been reserved [ 3.422291] system 00:07: [mem 0xfed10000-0xfed17fff] has been reserved [ 3.427602] system 00:07: [mem 0xfed18000-0xfed18fff] has been reserved [ 3.432908] system 00:07: [mem 0xfed19000-0xfed19fff] has been reserved [ 3.438219] system 00:07: [mem 0xf8000000-0xfbffffff] has been reserved [ 3.443523] system 00:07: [mem 0xfed20000-0xfed3ffff] has been reserved [ 3.448828] system 00:07: [mem 0xfed90000-0xfed93fff] has been reserved [ 3.454139] system 00:07: [mem 0xfed45000-0xfed8ffff] has been reserved [ 3.459443] system 00:07: [mem 0xff000000-0xffffffff] has been reserved [ 3.464747] system 00:07: [mem 0xfee00000-0xfeefffff] could not be reserved [ 3.470398] system 00:07: [mem 0xf7fe0000-0xf7feffff] has been reserved [ 3.475701] system 00:07: [mem 0xf7ff0000-0xf7ffffff] has been reserved [ 3.481007] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active) [ 3.481204] pnp: PnP ACPI: found 8 devices [ 3.489528] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns [ 3.497098] pci 0000:00:01.0: PCI bridge to [bus 01] [ 3.500758] pci 0000:00:1c.0: PCI bridge to [bus 02] [ 3.504423] pci 0000:00:1c.0: bridge window [mem 0xf7b00000-0xf7bfffff] [ 3.509912] pci 0000:00:1c.2: PCI bridge to [bus 03] [ 3.513575] pci 0000:00:1c.2: bridge window [io 0xe000-0xefff] [ 3.518368] pci 0000:00:1c.2: bridge window [mem 0xf7a00000-0xf7afffff] [ 3.523853] pci 0000:00:1c.2: bridge window [mem 0xf0000000-0xf00fffff 64bit pref] [ 3.530292] pci 0000:04:00.0: PCI bridge to [bus 05] [ 3.533970] pci 0000:00:1c.3: PCI bridge to [bus 04-05] [ 3.537898] pci 0000:00:1c.4: PCI bridge to [bus 06] [ 3.541557] pci 0000:00:1c.4: bridge window [io 0xd000-0xdfff] [ 3.546342] pci 0000:00:1c.4: bridge window [mem 0xf7800000-0xf79fffff] [ 3.551833] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] [ 3.556706] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] [ 3.561577] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] [ 3.567148] pci_bus 0000:00: resource 7 [mem 0x000d0000-0x000d3fff window] [ 3.572711] pci_bus 0000:00: resource 8 [mem 0x000d4000-0x000d7fff window] [ 3.578275] pci_bus 0000:00: resource 9 [mem 0x000d8000-0x000dbfff window] [ 3.583840] pci_bus 0000:00: resource 10 [mem 0x000dc000-0x000dffff window] [ 3.589490] pci_bus 0000:00: resource 11 [mem 0xdf200000-0xfeafffff window] [ 3.595140] pci_bus 0000:02: resource 1 [mem 0xf7b00000-0xf7bfffff] [ 3.600098] pci_bus 0000:03: resource 0 [io 0xe000-0xefff] [ 3.604360] pci_bus 0000:03: resource 1 [mem 0xf7a00000-0xf7afffff] [ 3.609318] pci_bus 0000:03: resource 2 [mem 0xf0000000-0xf00fffff 64bit pref] [ 3.615230] pci_bus 0000:04: resource 4 [io 0x0000-0x0cf7 window] [ 3.620099] pci_bus 0000:04: resource 5 [io 0x0d00-0xffff window] [ 3.624970] pci_bus 0000:04: resource 6 [mem 0x000a0000-0x000bffff window] [ 3.630534] pci_bus 0000:04: resource 7 [mem 0x000d0000-0x000d3fff window] [ 3.636096] pci_bus 0000:04: resource 8 [mem 0x000d4000-0x000d7fff window] [ 3.641662] pci_bus 0000:04: resource 9 [mem 0x000d8000-0x000dbfff window] [ 3.647225] pci_bus 0000:04: resource 10 [mem 0x000dc000-0x000dffff window] [ 3.652875] pci_bus 0000:04: resource 11 [mem 0xdf200000-0xfeafffff window] [ 3.658527] pci_bus 0000:05: resource 4 [io 0x0000-0x0cf7 window] [ 3.663396] pci_bus 0000:05: resource 5 [io 0x0d00-0xffff window] [ 3.668268] pci_bus 0000:05: resource 6 [mem 0x000a0000-0x000bffff window] [ 3.673830] pci_bus 0000:05: resource 7 [mem 0x000d0000-0x000d3fff window] [ 3.679394] pci_bus 0000:05: resource 8 [mem 0x000d4000-0x000d7fff window] [ 3.684959] pci_bus 0000:05: resource 9 [mem 0x000d8000-0x000dbfff window] [ 3.690530] pci_bus 0000:05: resource 10 [mem 0x000dc000-0x000dffff window] [ 3.696182] pci_bus 0000:05: resource 11 [mem 0xdf200000-0xfeafffff window] [ 3.701831] pci_bus 0000:06: resource 0 [io 0xd000-0xdfff] [ 3.706097] pci_bus 0000:06: resource 1 [mem 0xf7800000-0xf79fffff] [ 3.711162] NET: Registered protocol family 2 [ 3.714368] tcp_listen_portaddr_hash hash table entries: 8192 (order: 6, 327680 bytes, linear) [ 3.721733] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear) [ 3.728717] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear) [ 3.735208] TCP: Hash tables configured (established 131072 bind 65536) [ 3.740558] UDP hash table entries: 8192 (order: 7, 786432 bytes, linear) [ 3.746203] UDP-Lite hash table entries: 8192 (order: 7, 786432 bytes, linear) [ 3.752305] NET: Registered protocol family 1 [ 3.755452] RPC: Registered named UNIX socket transport module. [ 3.760071] RPC: Registered udp transport module. [ 3.763475] RPC: Registered tcp transport module. [ 3.766871] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 3.772010] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] [ 3.800593] pci 0000:00:1a.0: quirk_usb_early_handoff+0x0/0x603 took 20830 usecs [ 3.828587] pci 0000:00:1d.0: quirk_usb_early_handoff+0x0/0x603 took 21383 usecs [ 3.834697] PCI: CLS 64 bytes, default 64 [ 3.837441] Unpacking initramfs... [ 4.030087] Freeing initrd memory: 18924K [ 4.032806] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 4.037939] software IO TLB: mapped [mem 0xc6875000-0xca875000] (64MB) [ 4.043257] RAPL PMU: API unit is 2^-32 Joules, 4 fixed counters, 655360 ms ovfl timer [ 4.049866] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules [ 4.054307] RAPL PMU: hw unit of domain package 2^-14 Joules [ 4.058660] RAPL PMU: hw unit of domain dram 2^-14 Joules [ 4.062748] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules [ 4.067860] Initialise system trusted keyrings [ 4.071011] Key type blacklist registered [ 4.073747] workingset: timestamp_bits=40 max_order=22 bucket_order=0 [ 4.079010] DLM installed [ 4.080436] NFS: Registering the id_resolver key type [ 4.084187] Key type id_resolver registered [ 4.087068] Key type id_legacy registered [ 4.089805] SGI XFS with ACLs, security attributes, quota, no debug enabled [ 4.099126] NET: Registered protocol family 38 [ 4.102274] Key type asymmetric registered [ 4.105067] Asymmetric key parser 'x509' registered [ 4.108638] Key type pkcs7_test registered [ 4.111434] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) [ 4.117521] io scheduler mq-deadline registered [ 4.120745] io scheduler kyber registered [ 4.124417] intel_idle: MWAIT substates: 0x42120 [ 4.124418] intel_idle: v0.5.1 model 0x3C [ 4.124542] intel_idle: Local APIC timer is reliable in all C-states [ 4.124543] IPMI message handler: version 39.2 [ 4.127693] ipmi device interface [ 4.129719] ipmi_si: IPMI System Interface driver [ 4.133162] ipmi_si: Unable to find any System Interface(s) [ 4.137429] ipmi_ssif: IPMI SSIF Interface driver [ 4.140969] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 4.148013] ACPI: Power Button [PWRB] [ 4.150405] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 4.156497] ACPI: Power Button [PWRF] [ 4.159618] thermal LNXTHERM:00: registered as thermal_zone0 [ 4.163977] ACPI: Thermal Zone [TZ00] (28 C) [ 4.167199] thermal LNXTHERM:01: registered as thermal_zone1 [ 4.171557] ACPI: Thermal Zone [TZ01] (30 C) [ 4.174589] EINJ: EINJ table not found. [ 4.184064] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 4.189113] 00:05: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A [ 4.195804] i915 0000:00:02.0: vgaarb: deactivate vga console [ 4.201050] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 4.206693] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem [ 4.226176] [drm] Initialized i915 1.6.0 20200430 for 0000:00:02.0 on minor 0 [ 4.233345] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 4.239141] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input2 [ 4.248274] loop: module loaded [ 4.250269] ACPI Warning: SystemIO range 0x0000000000001828-0x000000000000182F conflicts with OpRegion 0x0000000000001800-0x000000000000187F (\PMIO) (20200326/utaddress-204) [ 4.260568] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes [ 4.264448] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 4.278156] ACPI Warning: SystemIO range 0x0000000000001C40-0x0000000000001C4F conflicts with OpRegion 0x0000000000001C00-0x0000000000001FFF (\GPR) (20200326/utaddress-204) [ 4.292218] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 4.301081] ACPI Warning: SystemIO range 0x0000000000001C30-0x0000000000001C3F conflicts with OpRegion 0x0000000000001C00-0x0000000000001C3F (\GPRL) (20200326/utaddress-204) [ 4.307503] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes [ 4.315249] ACPI Warning: SystemIO range 0x0000000000001C30-0x0000000000001C3F conflicts with OpRegion 0x0000000000001C00-0x0000000000001FFF (\GPR) (20200326/utaddress-204) [ 4.324146] i915 0000:00:02.0: [drm] Cannot find any crtc or sizes [ 4.334185] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 4.347899] ACPI Warning: SystemIO range 0x0000000000001C00-0x0000000000001C2F conflicts with OpRegion 0x0000000000001C00-0x0000000000001C3F (\GPRL) (20200326/utaddress-204) [ 4.362051] ACPI Warning: SystemIO range 0x0000000000001C00-0x0000000000001C2F conflicts with OpRegion 0x0000000000001C00-0x0000000000001FFF (\GPR) (20200326/utaddress-204) [ 4.376115] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 4.384972] lpc_ich: Resource conflict(s) found affecting gpio_ich [ 4.389960] ahci 0000:00:1f.2: version 3.0 [ 4.390085] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 4 ports 6 Gbps 0xf impl SATA mode [ 4.396864] ahci 0000:00:1f.2: flags: 64bit ncq led clo pio slum part ems apst [ 4.436923] scsi host0: ahci [ 4.438569] scsi host1: ahci [ 4.440207] scsi host2: ahci [ 4.441869] scsi host3: ahci [ 4.443488] ata1: SATA max UDMA/133 abar m2048 at 0xf7c15000 port 0xf7c15100 irq 31 [ 4.449575] ata2: SATA max UDMA/133 abar m2048 at 0xf7c15000 port 0xf7c15180 irq 31 [ 4.455664] ata3: SATA max UDMA/133 abar m2048 at 0xf7c15000 port 0xf7c15200 irq 31 [ 4.461748] ata4: SATA max UDMA/133 abar m2048 at 0xf7c15000 port 0xf7c15280 irq 31 [ 4.478234] ahci 0000:02:00.0: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode [ 4.485020] ahci 0000:02:00.0: flags: 64bit ncq led clo only pio ccc [ 4.490352] scsi host4: ahci [ 4.491989] ata5: SATA max UDMA/133 abar m8192 at 0xf7b00000 port 0xf7b00100 irq 32 [ 4.498189] tun: Universal TUN/TAP device driver, 1.6 [ 4.502030] ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 5.1.0-k [ 4.508394] ixgbe: Copyright (c) 1999-2016 Intel Corporation. [ 4.679612] ixgbe 0000:06:00.0: Multiqueue Enabled: Rx Queue count = 4, Tx Queue count = 4 XDP Queue count = 0 [ 4.688584] ixgbe 0000:06:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x2 link at 0000:00:1c.4 (capable of 32.000 Gb/s with 5.0 GT/s PCIe x8 link) [ 4.702503] ixgbe 0000:06:00.0: MAC: 2, PHY: 14, SFP+: 3, PBA No: Unknown [ 4.707985] ixgbe 0000:06:00.0: 00:1b:21:bb:e6:30 [ 4.713008] ixgbe 0000:06:00.0: Intel(R) 10 Gigabit Network Connection [ 4.718330] libphy: ixgbe-mdio: probed [ 4.720807] r8169 0000:03:00.0: can't disable ASPM; OS doesn't have ASPM control [ 4.737408] libphy: r8169: probed [ 4.739557] r8169 0000:03:00.0 eth1: RTL8168g/8111g, f0:79:59:65:de:78, XID 4c0, IRQ 38 [ 4.746257] r8169 0000:03:00.0 eth1: jumbo features [frames: 9200 bytes, tx checksumming: ko] [ 4.753492] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 4.758718] ehci-pci: EHCI PCI platform driver [ 4.761968] ehci-pci 0000:00:1a.0: EHCI Host Controller [ 4.765898] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1 [ 4.771993] ehci-pci 0000:00:1a.0: debug port 2 [ 4.779123] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported [ 4.782715] ata3: SATA link down (SStatus 0 SControl 300) [ 4.784614] ehci-pci 0000:00:1a.0: irq 20, io mem 0xf7c17000 [ 4.788727] ata4: SATA link down (SStatus 0 SControl 300) [ 4.797168] ata2: SATA link down (SStatus 0 SControl 300) [ 4.801321] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 4.807007] ata1.00: ATA-9: ST1000DM003-1CH162, CC49, max UDMA/133 [ 4.811555] ata5: SATA link up 6.0 Gbps (SStatus 133 SControl 300) [ 4.811891] ata1.00: 1953525168 sectors, multi 16: LBA48 NCQ (depth 32), AA [ 4.816783] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00 [ 4.818118] ata5.00: ATA-9: SAMSUNG MZHPV128HDGM-00000, BXW2500Q, max UDMA/133 [ 4.818119] ata5.00: 250069680 sectors, multi 1: LBA48 NCQ (depth 32), AA [ 4.818329] ata5.00: configured for UDMA/133 [ 4.823220] ata1.00: configured for UDMA/133 [ 4.826983] hub 1-0:1.0: USB hub found [ 4.832838] scsi 0:0:0:0: Direct-Access ATA ST1000DM003-1CH1 CC49 PQ: 0 ANSI: 5 [ 4.838266] hub 1-0:1.0: 2 ports detected [ 4.838498] ehci-pci 0000:00:1d.0: EHCI Host Controller [ 4.841353] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 4.841384] sd 0:0:0:0: [sda] 1953525168 512-byte logical blocks: (1.00 TB/932 GiB) [ 4.841385] sd 0:0:0:0: [sda] 4096-byte physical blocks [ 4.841389] sd 0:0:0:0: [sda] Write Protect is off [ 4.841390] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 4.841396] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 4.844215] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2 [ 4.846742] scsi 4:0:0:0: Direct-Access ATA SAMSUNG MZHPV128 500Q PQ: 0 ANSI: 5 [ 4.853453] ehci-pci 0000:00:1d.0: debug port 2 [ 4.856260] sd 4:0:0:0: Attached scsi generic sg1 type 0 [ 4.856280] sd 4:0:0:0: [sdb] 250069680 512-byte logical blocks: (128 GB/119 GiB) [ 4.856288] sd 4:0:0:0: [sdb] Write Protect is off [ 4.856289] sd 4:0:0:0: [sdb] Mode Sense: 00 3a 00 00 [ 4.856300] sd 4:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 4.863965] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported [ 4.928515] ehci-pci 0000:00:1d.0: irq 23, io mem 0xf7c16000 [ 4.934299] sdb: sdb1 sdb2 sdb3 < sdb5 > [ 4.937255] sd 4:0:0:0: [sdb] Attached SCSI disk [ 4.948547] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00 [ 4.953161] hub 2-0:1.0: USB hub found [ 4.955610] hub 2-0:1.0: 2 ports detected [ 4.958433] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 4.963318] ohci-pci: OHCI PCI platform driver [ 4.966467] uhci_hcd: USB Universal Host Controller Interface driver [ 4.966588] sda: sda1 sda2 sda3 sda4 < sda5 > [ 4.971642] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 4.974905] sd 0:0:0:0: [sda] Attached SCSI disk [ 4.978594] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 3 [ 4.989035] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x0000000000009810 [ 4.996865] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported [ 5.002617] hub 3-0:1.0: USB hub found [ 5.005085] hub 3-0:1.0: 14 ports detected [ 5.008431] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 5.012356] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 4 [ 5.018449] xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed [ 5.023589] hub 4-0:1.0: USB hub found [ 5.026053] hub 4-0:1.0: 6 ports detected [ 5.029204] usbcore: registered new interface driver usb-storage [ 5.033935] i8042: PNP: No PS/2 controller found. [ 5.037464] mousedev: PS/2 mouse device common for all mice [ 5.041842] rtc_cmos 00:01: RTC can wake from S4 [ 5.045292] rtc_cmos 00:01: registered as rtc0 [ 5.048465] rtc_cmos 00:01: setting system clock to 2020-06-07T01:14:52 UTC (1591492492) [ 5.055257] rtc_cmos 00:01: alarms up to one month, y3k, 242 bytes nvram, hpet irqs [ 5.061627] i2c /dev entries driver [ 5.064050] i801_smbus 0000:00:1f.3: SPD Write Disable is set [ 5.068519] i801_smbus 0000:00:1f.3: SMBus using PCI interrupt [ 5.073564] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11 [ 5.077851] iTCO_wdt: Found a 9 Series TCO device (Version=2, TCOBASE=0x1860) [ 5.083707] tsc: Refined TSC clocksource calibration: 3691.451 MHz [ 5.083757] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0) [ 5.088589] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x6a6b9449ba6, max_idle_ns: 881590891201 ns [ 5.093302] iTCO_vendor_support: vendor-support=0 [ 5.105394] device-mapper: uevent: version 1.0.3 [ 5.108737] clocksource: Switched to clocksource tsc [ 5.108762] device-mapper: ioctl: 4.42.0-ioctl (2020-02-27) initialised: dm-devel at redhat.com [ 5.119529] intel_pstate: Intel P-state driver initializing [ 5.124307] usbcore: registered new interface driver usbhid [ 5.128600] usbhid: USB HID core driver [ 5.131690] NET: Registered protocol family 10 [ 5.135597] Segment Routing with IPv6 [ 5.138056] mip6: Mobile IPv6 [ 5.139729] NET: Registered protocol family 17 [ 5.144935] NET: Registered protocol family 33 [ 5.148079] Key type rxrpc registered [ 5.150445] Key type rxrpc_s registered [ 5.152988] sctp: Hash tables configured (bind 128/128) [ 5.157059] NET: Registered protocol family 21 [ 5.160210] Key type dns_resolver registered [ 5.163437] IPI shorthand broadcast: enabled [ 5.166421] sched_clock: Marking stable (4357120504, 809288175)->(5217185576, -50776897) [ 5.173363] registered taskstats version 1 [ 5.176158] Loading compiled-in X.509 certificates [ 5.180509] usb 1-1: new high-speed USB device number 2 using ehci-pci [ 5.206707] Loaded X.509 cert 'Build time autogenerated kernel key: c0aa0c87903d5a43603e1674589edab2dd4eb1a6' [ 5.215321] kAFS: Red Hat AFS client v0.1 registering. [ 5.219256] FS-Cache: Netfs 'afs' registered for caching [ 5.223479] Btrfs loaded, crc32c=crc32c-generic, debug=on, integrity-checker=on, ref-verify=on [ 5.231106] hub 1-1:1.0: USB hub found [ 5.233829] hub 1-1:1.0: 6 ports detected [ 5.235068] Key type big_key registered [ 5.241258] Key type encrypted registered [ 5.245471] Freeing unused kernel image (initmem) memory: 1608K [ 5.260549] Write protecting the kernel read-only data: 20480k [ 5.265592] Freeing unused kernel image (text/rodata gap) memory: 2044K [ 5.271093] Freeing unused kernel image (rodata/data gap) memory: 772K [ 5.276343] Run /init as init process [ 5.278703] with arguments: [ 5.278703] /init [ 5.278704] with environment: [ 5.278704] HOME=/ [ 5.278704] TERM=linux [ 5.278705] BOOT_IMAGE=/data/tftp/andromeda-vmlinuz [ 5.278705] ip=enp3s0:dhcp [ 5.292497] systemd[1]: systemd 239 running in system mode. (+PAM +AUDIT +SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=hybrid) [ 5.312463] usb 2-1: new high-speed USB device number 2 using ehci-pci [ 5.336576] systemd[1]: Detected architecture x86-64. [ 5.340324] systemd[1]: Running in initial RAM disk. [ 5.345327] hub 2-1:1.0: USB hub found [ 5.347906] hub 2-1:1.0: 8 ports detected [ 5.380585] systemd[1]: Set hostname to <andromeda.procyon.org.uk>. [ 5.422009] systemd[1]: File /usr/lib/systemd/system/systemd-journald.service:26 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling. [ 5.438102] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.) [ 5.456109] random: systemd: uninitialized urandom read (16 bytes read) [ 5.461438] systemd[1]: Reached target Slices. [ 5.476586] random: systemd: uninitialized urandom read (16 bytes read) [ 5.481909] systemd[1]: Reached target Local File Systems. [ 5.500585] random: systemd: uninitialized urandom read (16 bytes read) [ 5.506032] systemd[1]: Listening on Journal Socket (/dev/log). [ 5.524597] systemd[1]: Reached target Timers. [ 5.704833] audit: type=1130 audit(1591492493.152:2): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-journald comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 5.740600] audit: type=1130 audit(1591492493.188:3): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 5.759627] audit: type=1131 audit(1591492493.188:4): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 5.792571] audit: type=1130 audit(1591492493.240:5): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup-dev comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 5.824597] audit: type=1130 audit(1591492493.272:6): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-sysctl comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 5.888651] audit: type=1130 audit(1591492493.336:7): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 5.920619] audit: type=1130 audit(1591492493.368:8): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-cmdline comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 5.968699] audit: type=1130 audit(1591492493.416:9): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-pre-udev comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 6.020600] audit: type=1130 audit(1591492493.468:10): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-udevd comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 6.144574] r8169 0000:03:00.0 enp3s0: renamed from eth1 [ 6.177109] ixgbe 0000:06:00.0 enp6s0: renamed from eth0 [ 6.272741] random: fast init done [ 6.564043] EXT4-fs (sdb2): mounted filesystem with ordered data mode. Opts: (null) [ 6.724445] kauditd_printk_skb: 4 callbacks suppressed [ 6.724447] audit: type=1130 audit(1591492494.168:15): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=initrd-parse-etc comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 6.748244] audit: type=1131 audit(1591492494.168:16): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=initrd-parse-etc comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 6.926226] audit: type=1130 audit(1591492494.372:17): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-pre-pivot comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 6.949110] audit: type=1131 audit(1591492494.396:18): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-pre-pivot comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 6.969876] audit: type=1130 audit(1591492494.416:19): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 6.989403] audit: type=1131 audit(1591492494.416:20): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 7.010288] audit: type=1130 audit(1591492494.460:21): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-initqueue comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 7.029843] audit: type=1131 audit(1591492494.460:22): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-initqueue comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 7.029933] audit: type=1130 audit(1591492494.476:23): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-sysctl comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 7.068200] audit: type=1131 audit(1591492494.476:24): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-sysctl comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success' [ 7.199317] systemd-journald[1910]: Received SIGTERM from PID 1 (systemd). [ 7.218785] printk: systemd: 11 output lines suppressed due to ratelimiting [ 7.375860] SELinux: Permission watch in class filesystem not defined in policy. [ 7.382044] SELinux: Permission watch in class file not defined in policy. [ 7.387694] SELinux: Permission watch_mount in class file not defined in policy. [ 7.393866] SELinux: Permission watch_sb in class file not defined in policy. [ 7.399777] SELinux: Permission watch_with_perm in class file not defined in policy. [ 7.406293] SELinux: Permission watch_reads in class file not defined in policy. [ 7.412466] SELinux: Permission watch in class dir not defined in policy. [ 7.418037] SELinux: Permission watch_mount in class dir not defined in policy. [ 7.424122] SELinux: Permission watch_sb in class dir not defined in policy. [ 7.429947] SELinux: Permission watch_with_perm in class dir not defined in policy. [ 7.436385] SELinux: Permission watch_reads in class dir not defined in policy. [ 7.442473] SELinux: Permission watch in class lnk_file not defined in policy. [ 7.448475] SELinux: Permission watch_mount in class lnk_file not defined in policy. [ 7.454991] SELinux: Permission watch_sb in class lnk_file not defined in policy. [ 7.461250] SELinux: Permission watch_with_perm in class lnk_file not defined in policy. [ 7.468112] SELinux: Permission watch_reads in class lnk_file not defined in policy. [ 7.474632] SELinux: Permission watch in class chr_file not defined in policy. [ 7.480636] SELinux: Permission watch_mount in class chr_file not defined in policy. [ 7.487153] SELinux: Permission watch_sb in class chr_file not defined in policy. [ 7.493411] SELinux: Permission watch_with_perm in class chr_file not defined in policy. [ 7.500274] SELinux: Permission watch_reads in class chr_file not defined in policy. [ 7.506795] SELinux: Permission watch in class blk_file not defined in policy. [ 7.512798] SELinux: Permission watch_mount in class blk_file not defined in policy. [ 7.519316] SELinux: Permission watch_sb in class blk_file not defined in policy. [ 7.525572] SELinux: Permission watch_with_perm in class blk_file not defined in policy. [ 7.532438] SELinux: Permission watch_reads in class blk_file not defined in policy. [ 7.538955] SELinux: Permission watch in class sock_file not defined in policy. [ 7.545038] SELinux: Permission watch_mount in class sock_file not defined in policy. [ 7.551643] SELinux: Permission watch_sb in class sock_file not defined in policy. [ 7.557988] SELinux: Permission watch_with_perm in class sock_file not defined in policy. [ 7.564946] SELinux: Permission watch_reads in class sock_file not defined in policy. [ 7.571553] SELinux: Permission watch in class fifo_file not defined in policy. [ 7.577643] SELinux: Permission watch_mount in class fifo_file not defined in policy. [ 7.584245] SELinux: Permission watch_sb in class fifo_file not defined in policy. [ 7.590591] SELinux: Permission watch_with_perm in class fifo_file not defined in policy. [ 7.597542] SELinux: Permission watch_reads in class fifo_file not defined in policy. [ 7.604239] SELinux: Class xdp_socket not defined in policy. [ 7.608678] SELinux: Class perf_event not defined in policy. [ 7.613115] SELinux: Class lockdown not defined in policy. [ 7.617379] SELinux: the above unknown classes and permissions will be allowed [ 7.623300] SELinux: policy capability network_peer_controls=1 [ 7.627908] SELinux: policy capability open_perms=1 [ 7.631566] SELinux: policy capability extended_socket_class=1 [ 7.636177] SELinux: policy capability always_check_network=0 [ 7.640701] SELinux: policy capability cgroup_seclabel=1 [ 7.644791] SELinux: policy capability nnp_nosuid_transition=1 [ 7.649402] SELinux: policy capability genfs_seclabel_symlinks=0 [ 7.684944] systemd[1]: Successfully loaded SELinux policy in 416.158ms. [ 7.754705] systemd[1]: Relabelled /dev, /run and /sys/fs/cgroup in 52.855ms. [ 7.762864] systemd[1]: systemd 239 running in system mode. (+PAM +AUDIT +SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=hybrid) [ 7.800637] systemd[1]: Detected architecture x86-64. [ 7.805413] systemd[1]: Set hostname to <andromeda.procyon.org.uk>. [ 7.871918] systemd[1]: File /usr/lib/systemd/system/systemd-journald.service:26 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling. [ 7.887999] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.) [ 8.011700] systemd[1]: Stopped Switch Root. [ 8.014934] systemd[1]: systemd-journald.service: Service has no hold-off time (RestartSec=0), scheduling restart. [ 8.025363] systemd[1]: systemd-journald.service: Scheduled restart job, restart counter is at 1. [ 8.034702] systemd[1]: Stopped Journal Service. [ 8.039155] systemd[1]: Starting Journal Service... [ 8.082722] EXT4-fs (sdb2): re-mounted. Opts: (null) [ 8.126253] systemd-journald[3397]: Received request to flush runtime journal from PID 1 [ 8.140536] Adding 67108860k swap on /dev/sda1. Priority:-2 extents:1 across:67108860k [ 8.660947] EXT4-fs (sdb1): mounted filesystem with ordered data mode. Opts: (null) [ 8.665412] EXT4-fs (sdb5): mounted filesystem with ordered data mode. Opts: (null) [ 8.667800] ext4 filesystem being mounted at /boot supports timestamps until 2038 (0x7fffffff) [ 9.311410] Generic FE-GE Realtek PHY r8169-300:00: attached PHY driver [Generic FE-GE Realtek PHY] (mii_bus:phy_addr=r8169-300:00, irq=IGNORE) [ 9.433402] r8169 0000:03:00.0 enp3s0: Link is Down [ 9.462639] ixgbe 0000:06:00.0: registered PHC device on enp6s0 [ 9.648542] ixgbe 0000:06:00.0 enp6s0: detected SFP+: 3 [ 9.996542] ixgbe 0000:06:00.0 enp6s0: NIC Link is Up 10 Gbps, Flow Control: RX/TX [ 10.003072] IPv6: ADDRCONF(NETDEV_CHANGE): enp6s0: link becomes ready [ 10.047533] random: crng init done [ 10.049646] random: 7 urandom warning(s) missed due to ratelimiting [ 10.288558] ixgbe 0000:06:00.0 enp6s0: detected SFP+: 3 [ 10.333072] virbr0: port 1(virbr0-nic) entered blocking state [ 10.337526] virbr0: port 1(virbr0-nic) entered disabled state [ 10.342031] device virbr0-nic entered promiscuous mode [ 10.421249] ixgbe 0000:06:00.0 enp6s0: NIC Link is Up 10 Gbps, Flow Control: RX/TX [ 10.457505] device virbr0-nic left promiscuous mode [ 10.461093] virbr0: port 1(virbr0-nic) entered disabled state [ 12.185669] r8169 0000:03:00.0 enp3s0: Link is Up - 1Gbps/Full - flow control rx/tx [ 12.192099] IPv6: ADDRCONF(NETDEV_CHANGE): enp3s0: link becomes ready From gwan-gyeong.mun at intel.com Sun Jun 7 14:01:02 2020 From: gwan-gyeong.mun at intel.com (Gwan-gyeong Mun) Date: Sun, 7 Jun 2020 17:01:02 +0300 Subject: [Intel-gfx] [PATCH v3] drm/i915/psr: Program default IO buffer Wake and Fast Wake Message-ID: <20200607140102.172240-1-gwan-gyeong.mun@intel.com> The IO buffer Wake and Fast Wake bit size and value have been changed from Gen12+. It programs the default value of IO buffer Wake and Fast Wake on Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 and Gen12+. And it aligns PSR2 definition macros. v2: Fix macro definitions. (Jos?) v3: Addressed review comments from Jos? - Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+ - Change a style of macro naming in order to use lines as input. - Update Todo comments. Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++--------- 2 files changed, 49 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7a0011e42e00..ab380e6dc674 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -537,6 +537,22 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); val |= intel_psr2_get_tp_time(intel_dp); + if (INTEL_GEN(dev_priv) >= 12) { + /* + * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default + * values from BSpec. In order to setting an optimal power + * consumption, lower than 4k resoluition mode needs to decrese + * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution + * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. + */ + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); + val |= TGL_EDP_PSR2_FAST_WAKE(7); + } else if (INTEL_GEN(dev_priv) >= 9) { + val |= EDP_PSR2_IO_BUFFER_WAKE(7); + val |= EDP_PSR2_FAST_WAKE(7); + } + /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 814a70945468..080ff728d047 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4511,25 +4511,39 @@ enum { #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ -#define _PSR2_CTL_A 0x60900 -#define _PSR2_CTL_EDP 0x6f900 -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) -#define EDP_PSR2_ENABLE (1 << 31) -#define EDP_SU_TRACK_ENABLE (1 << 30) -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ -#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) -#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) -#define EDP_PSR2_TP2_TIME_500us (0 << 8) -#define EDP_PSR2_TP2_TIME_100us (1 << 8) -#define EDP_PSR2_TP2_TIME_2500us (2 << 8) -#define EDP_PSR2_TP2_TIME_50us (3 << 8) -#define EDP_PSR2_TP2_TIME_MASK (3 << 8) -#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 -#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) -#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) -#define EDP_PSR2_IDLE_FRAME_MASK 0xf -#define EDP_PSR2_IDLE_FRAME_SHIFT 0 +#define _PSR2_CTL_A 0x60900 +#define _PSR2_CTL_EDP 0x6f900 +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) +#define EDP_PSR2_ENABLE (1 << 31) +#define EDP_SU_TRACK_ENABLE (1 << 30) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) +#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ +#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ +#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) +#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 +#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - lines) << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) ((lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) +#define EDP_PSR2_FAST_WAKE_MAX_LINES 8 +#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - lines) << 11) +#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) +#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 +#define TGL_EDP_PSR2_FAST_WAKE(lines) ((lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) +#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) +#define EDP_PSR2_TP2_TIME_500us (0 << 8) +#define EDP_PSR2_TP2_TIME_100us (1 << 8) +#define EDP_PSR2_TP2_TIME_2500us (2 << 8) +#define EDP_PSR2_TP2_TIME_50us (3 << 8) +#define EDP_PSR2_TP2_TIME_MASK (3 << 8) +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) +#define EDP_PSR2_IDLE_FRAME_MASK 0xf +#define EDP_PSR2_IDLE_FRAME_SHIFT 0 #define _PSR_EVENT_TRANS_A 0x60848 #define _PSR_EVENT_TRANS_B 0x61848 -- 2.25.0 From patchwork at emeril.freedesktop.org Sun Jun 7 14:20:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 14:20:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wak?= =?utf-8?q?e_=28rev3=29?= In-Reply-To: <20200607140102.172240-1-gwan-gyeong.mun@intel.com> References: <20200607140102.172240-1-gwan-gyeong.mun@intel.com> Message-ID: <159153965331.15986.12871202322506931167@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3) URL : https://patchwork.freedesktop.org/series/78019/ State : warning == Summary == $ dim checkpatch origin/drm-tip ffef3ca6c982 drm/i915/psr: Program default IO buffer Wake and Fast Wake -:89: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues #89: FILE: drivers/gpu/drm/i915/i915_reg.h:4526: +#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - lines) << 13) -:92: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #92: FILE: drivers/gpu/drm/i915/i915_reg.h:4529: +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) ((lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) -:92: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues #92: FILE: drivers/gpu/drm/i915/i915_reg.h:4529: +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) ((lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) -:95: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues #95: FILE: drivers/gpu/drm/i915/i915_reg.h:4532: +#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - lines) << 11) -:98: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'lines' may be better as '(lines)' to avoid precedence issues #98: FILE: drivers/gpu/drm/i915/i915_reg.h:4535: +#define TGL_EDP_PSR2_FAST_WAKE(lines) ((lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) total: 0 errors, 1 warnings, 4 checks, 80 lines checked From gwan-gyeong.mun at intel.com Sun Jun 7 14:36:14 2020 From: gwan-gyeong.mun at intel.com (Gwan-gyeong Mun) Date: Sun, 7 Jun 2020 17:36:14 +0300 Subject: [Intel-gfx] [PATCH v4] drm/i915/psr: Program default IO buffer Wake and Fast Wake Message-ID: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> The IO buffer Wake and Fast Wake bit size and value have been changed from Gen12+. It programs the default value of IO buffer Wake and Fast Wake on Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 and Gen12+. And it aligns PSR2 definition macros. v2: Fix macro definitions. (Jos?) v3: Addressed review comments from Jos? - Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+ - Change a style of macro naming in order to use lines as input. - Update Todo comments. v4: Add parentheses to macros to avoid precedence issues. Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++--------- 2 files changed, 49 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7a0011e42e00..ab380e6dc674 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -537,6 +537,22 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); val |= intel_psr2_get_tp_time(intel_dp); + if (INTEL_GEN(dev_priv) >= 12) { + /* + * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default + * values from BSpec. In order to setting an optimal power + * consumption, lower than 4k resoluition mode needs to decrese + * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution + * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. + */ + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); + val |= TGL_EDP_PSR2_FAST_WAKE(7); + } else if (INTEL_GEN(dev_priv) >= 9) { + val |= EDP_PSR2_IO_BUFFER_WAKE(7); + val |= EDP_PSR2_FAST_WAKE(7); + } + /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 814a70945468..4066f67175dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4511,25 +4511,39 @@ enum { #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ -#define _PSR2_CTL_A 0x60900 -#define _PSR2_CTL_EDP 0x6f900 -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) -#define EDP_PSR2_ENABLE (1 << 31) -#define EDP_SU_TRACK_ENABLE (1 << 30) -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ -#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) -#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) -#define EDP_PSR2_TP2_TIME_500us (0 << 8) -#define EDP_PSR2_TP2_TIME_100us (1 << 8) -#define EDP_PSR2_TP2_TIME_2500us (2 << 8) -#define EDP_PSR2_TP2_TIME_50us (3 << 8) -#define EDP_PSR2_TP2_TIME_MASK (3 << 8) -#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 -#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) -#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) -#define EDP_PSR2_IDLE_FRAME_MASK 0xf -#define EDP_PSR2_IDLE_FRAME_SHIFT 0 +#define _PSR2_CTL_A 0x60900 +#define _PSR2_CTL_EDP 0x6f900 +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) +#define EDP_PSR2_ENABLE (1 << 31) +#define EDP_SU_TRACK_ENABLE (1 << 30) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) +#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ +#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ +#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) +#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 +#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) +#define EDP_PSR2_FAST_WAKE_MAX_LINES 8 +#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) +#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) +#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 +#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) +#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) +#define EDP_PSR2_TP2_TIME_500us (0 << 8) +#define EDP_PSR2_TP2_TIME_100us (1 << 8) +#define EDP_PSR2_TP2_TIME_2500us (2 << 8) +#define EDP_PSR2_TP2_TIME_50us (3 << 8) +#define EDP_PSR2_TP2_TIME_MASK (3 << 8) +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) +#define EDP_PSR2_IDLE_FRAME_MASK 0xf +#define EDP_PSR2_IDLE_FRAME_SHIFT 0 #define _PSR_EVENT_TRANS_A 0x60848 #define _PSR_EVENT_TRANS_B 0x61848 -- 2.25.0 From patchwork at emeril.freedesktop.org Sun Jun 7 14:41:30 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 14:41:30 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake_=28re?= =?utf-8?b?djMp?= In-Reply-To: <20200607140102.172240-1-gwan-gyeong.mun@intel.com> References: <20200607140102.172240-1-gwan-gyeong.mun@intel.com> Message-ID: <159154089075.15989.17990076076908931127@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev3) URL : https://patchwork.freedesktop.org/series/78019/ State : success == Summary == CI Bug Log - changes from CI_DRM_8596 -> Patchwork_17898 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/index.html Known issues ------------ Here are the changes found in Patchwork_17898 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-tgl-dsi/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html - fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92]) -> [DMESG-WARN][8] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 41) ------------------------------ Missing (8): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8596 -> Patchwork_17898 CI-20190529: 20190529 CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17898: ffef3ca6c9829bcbb8086649350ba11085e3aa55 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ffef3ca6c982 drm/i915/psr: Program default IO buffer Wake and Fast Wake == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17898/index.html From patchwork at emeril.freedesktop.org Sun Jun 7 14:48:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 14:48:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wak?= =?utf-8?q?e_=28rev4=29?= In-Reply-To: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> References: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> Message-ID: <159154128093.15986.6170451046520214739@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev4) URL : https://patchwork.freedesktop.org/series/78019/ State : warning == Summary == $ dim checkpatch origin/drm-tip c063779ca557 drm/i915/psr: Program default IO buffer Wake and Fast Wake -:90: WARNING:LONG_LINE: line length of 101 exceeds 100 columns #90: FILE: drivers/gpu/drm/i915/i915_reg.h:4526: +#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) -:93: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #93: FILE: drivers/gpu/drm/i915/i915_reg.h:4529: +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) total: 0 errors, 2 warnings, 0 checks, 80 lines checked From patchwork at emeril.freedesktop.org Sun Jun 7 15:09:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 15:09:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake_=28re?= =?utf-8?b?djQp?= In-Reply-To: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> References: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> Message-ID: <159154258056.15989.126946693692016181@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev4) URL : https://patchwork.freedesktop.org/series/78019/ State : success == Summary == CI Bug Log - changes from CI_DRM_8596 -> Patchwork_17899 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/index.html Known issues ------------ Here are the changes found in Patchwork_17899 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-byt-n2820/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-tgl-dsi/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 41) ------------------------------ Missing (8): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8596 -> Patchwork_17899 CI-20190529: 20190529 CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17899: c063779ca55740c59aacc4d6ae5ee0ed9a4488e5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c063779ca557 drm/i915/psr: Program default IO buffer Wake and Fast Wake == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/index.html From patchwork at emeril.freedesktop.org Sun Jun 7 16:08:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 16:08:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake_=28re?= =?utf-8?b?djQp?= In-Reply-To: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> References: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> Message-ID: <159154609812.15986.11963873325616919071@emeril.freedesktop.org> == Series Details == Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev4) URL : https://patchwork.freedesktop.org/series/78019/ State : success == Summary == CI Bug Log - changes from CI_DRM_8596_full -> Patchwork_17899_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17899_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_partial_pwrite_pread@reads-snoop: - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +7 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl8/igt at gem_partial_pwrite_pread@reads-snoop.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl2/igt at gem_partial_pwrite_pread@reads-snoop.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([i915#155]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl6/igt at i915_suspend@debugfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl2/igt at i915_suspend@debugfs-reader.html * igt at i915_suspend@forcewake: - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([i915#1630]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl7/igt at i915_suspend@forcewake.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl3/igt at i915_suspend@forcewake.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk7/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +14 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt at kms_color@pipe-c-ctm-blue-to-red.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#300]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl10/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-bo.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw5/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][27] -> [DMESG-FAIL][28] ([fdo#108145] / [i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109642] / [fdo#111068]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb6/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb8/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html #### Possible fixes #### * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-normal: - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk7/igt at gem_exec_whisper@basic-normal.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk8/igt at gem_exec_whisper@basic-normal.html * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +5 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl7/igt at gem_workarounds@suspend-resume-fd.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl4/igt at gem_workarounds@suspend-resume-fd.html * igt at kms_big_fb@x-tiled-16bpp-rotate-0: - shard-glk: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk9/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +6 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl7/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-move.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw4/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: - shard-apl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl6/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl2/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +17 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-skl: [FAIL][57] ([i915#49]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb3/igt at kms_psr@psr2_sprite_render.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb2/igt at kms_psr@psr2_sprite_render.html * igt at kms_setmode@basic: - shard-apl: [FAIL][63] ([i915#31]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt at kms_setmode@basic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-a-wait-forked-hang: - shard-hsw: [INCOMPLETE][65] ([i915#61]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw4/igt at kms_vblank@pipe-a-wait-forked-hang.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw8/igt at kms_vblank@pipe-a-wait-forked-hang.html #### Warnings #### * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [WARN][67] ([i915#1515]) -> [FAIL][68] ([i915#1515]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb5/igt at i915_pm_rc6_residency@rc6-idle.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][69] ([i915#1319] / [i915#1958]) -> [TIMEOUT][70] ([i915#1319]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl4/igt at kms_content_protection@atomic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl7/igt at kms_content_protection@atomic.html - shard-apl: [TIMEOUT][71] ([i915#1319]) -> [FAIL][72] ([fdo#110321] / [fdo#110336]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt at kms_content_protection@atomic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_content_protection@atomic.html * igt at kms_content_protection@lic: - shard-kbl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl6/igt at kms_content_protection@srm.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl2/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][77] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#93] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1630]: https://gitlab.freedesktop.org/drm/intel/issues/1630 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8596 -> Patchwork_17899 CI-20190529: 20190529 CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17899: c063779ca55740c59aacc4d6ae5ee0ed9a4488e5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/index.html From andriy.shevchenko at linux.intel.com Sun Jun 7 17:03:37 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Sun, 7 Jun 2020 20:03:37 +0300 Subject: [Intel-gfx] [PATCH 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) In-Reply-To: <20200606202601.48410-3-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> <20200606202601.48410-3-hdegoede@redhat.com> Message-ID: <20200607170337.GY2428291@smile.fi.intel.com> On Sat, Jun 06, 2020 at 10:25:47PM +0200, Hans de Goede wrote: > The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM > controller gets turned off from the _PS3 method of the graphics-card dev: > > Method (_PS3, 0, Serialized) // _PS3: Power State 3 > { > ... > PWMB = PWMC /* \_SB_.PCI0.GFX0.PWMC */ > PSAT |= 0x03 > Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ > ... > } > > Where PSAT is the power-status register of the PWM controller. > > Since the i915 driver will do a pwm_get on the pwm device as it uses it to > control the LCD panel backlight, there is a device-link marking the i915 > device as a consumer of the pwm device. So that the PWM controller will > always be suspended after the i915 driver suspends (which is the right > thing to do). This causes the above GFX0 PS3 AML code to run before > acpi_lpss.c calls acpi_lpss_save_ctx(). > > So on these devices the PWM controller will already be off when > acpi_lpss_save_ctx() runs. This causes it to read/save all 1-s (0xffffffff) > as ctx register values. > > When these bogus values get restored on resume the PWM controller actually > keeps working, since most bits are reserved, but this does set bit 3 of > the LPSS General purpose register, which for the PWM controller has the > following function: "This bit is re-used to support 32kHz slow mode. > Default is 19.2MHz as PWM source clock". > > This causes the clock of the PWM controller to switch from 19.2MHz to > 32KHz, which is a slow-down of a factor 600. Suprisingly enough so far > there have been few bug reports about this. This is likely because the > i915 driver was hardcoding the PWM frequency to 46 KHz, which divided > by 600 would result in a PWM frequency of aprox. 78 Hz, which mostly > still works fine. There are some bug reports about the LCD backlight > flickering after suspend/resume which are likely caused by this issue. > > But with the upcoming patch-series to finally switch the i915 drivers > code for external PWM controllers to use the atomic API and to honor > the PWM frequency specified in the video BIOS (VBT), this becomes a much > bigger problem. On most cases the VBT specifies either 200 Hz or 20 > KHz as PWM frequency, which with the mentioned issue ends up being either > 1/3 Hz, where the backlight actually visible blinks on and off every 3s, > or in 33 Hz and horrible flickering of the backlight. > > There are a number of possible solutions to this problem: > > 1. Make acpi_lpss_save_ctx() run before GFX0._PS3 > Pro: Clean solution from pov of not medling with save/restore ctx code > Con: As mentioned the current ordering is the right thing to do > Con: Requires assymmetry in at what suspend/resume phase we do the save vs > restore, requiring more suspend/resume ordering hacks in already > convoluted acpi_lpss.c suspend/resume code. > 2. Do some sort of save once mode for the LPSS ctx > Pro: Reasonably clean > Con: Needs a new LPSS flag + code changes to handle the flag > 3. Detect we have failed to save the ctx registers and do not restore them > Pro: Not PWM specific, might help with issues on other LPSS devices too > Con: If we can get away with not restoring the ctx why bother with it at > all? > 4. Do not save the ctx for CHT PWM controllers > Pro: Clean, as simple as dropping a flag? > Con: Not so simple as dropping a flag, needs a new flag to ensure that > we still do lpss_deassert_reset() on device activation. > 5. Make the pwm-lpss code fixup the LPSS-context registers > Pro: Keeps acpi_lpss.c code clean > Con: Moves knowledge of LPSS-context into the pwm-lpss.c code > > 1 and 5 both do not seem to be a desirable way forward. > > 3 and 4 seem ok, but they both assume that restoring the LPSS-context > registers is not necessary. I have done a couple of test and those do > show that restoring the LPSS-context indeed does not seem to be necessary > on devices using s2idle suspend (and successfully reaching S0i3). But I > have no hardware to test deep / S3 suspend. So I'm not sure that not > restoring the context is safe. > > That leaves solution 2, which is about as simple / clean as 3 and 4, > so this commit fixes the described problem by implementing a new > LPSS_SAVE_CTX_ONCE flag and setting that for the CHT PWM controllers. > > Signed-off-by: Hans de Goede <hdegoede at redhat.com> > --- > drivers/acpi/acpi_lpss.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c > index 67892fc0b822..26933e6b7b8c 100644 > --- a/drivers/acpi/acpi_lpss.c > +++ b/drivers/acpi/acpi_lpss.c > @@ -68,6 +68,14 @@ ACPI_MODULE_NAME("acpi_lpss"); > #define LPSS_LTR BIT(3) > #define LPSS_SAVE_CTX BIT(4) > #define LPSS_NO_D3_DELAY BIT(5) > +/* > + * For some devices the DSDT AML code for another device turns off the device > + * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) > + * as ctx register values. > + * Luckily these devices always use the same ctx register values, so we can > + * work around this by saving the ctx registers once on activation. > + */ > +#define LPSS_SAVE_CTX_ONCE BIT(6) A nit: I would group SAVE_CTX and CTX_ONCE in the list, i.e. make this BIT(5) and move NO_D3_DELAY to BIT(6). > struct lpss_private_data; > > @@ -254,7 +262,7 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { > }; > > static const struct lpss_device_desc bsw_pwm_dev_desc = { > - .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, > + .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, > .prv_offset = 0x800, > .setup = bsw_pwm_setup, > .resume_from_noirq = true, > @@ -885,9 +893,14 @@ static int acpi_lpss_activate(struct device *dev) > * we have to deassert reset line to be sure that ->probe() will > * recognize the device. > */ > - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) > + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) > lpss_deassert_reset(pdata); > > +#ifdef CONFIG_PM > + if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) > + acpi_lpss_save_ctx(dev, pdata); > +#endif > + > return 0; > } > > @@ -1031,7 +1044,7 @@ static int acpi_lpss_resume(struct device *dev) > > acpi_lpss_d3_to_d0_delay(pdata); > > - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) > + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) > acpi_lpss_restore_ctx(dev, pdata); > > return 0; > -- > 2.26.2 > -- With Best Regards, Andy Shevchenko From jose.souza at intel.com Sun Jun 7 17:26:19 2020 From: jose.souza at intel.com (Souza, Jose) Date: Sun, 7 Jun 2020 17:26:19 +0000 Subject: [Intel-gfx] [PATCH v4] drm/i915/psr: Program default IO buffer Wake and Fast Wake In-Reply-To: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> References: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> Message-ID: <b8bc6d46ec07080129138820315af3dd6acd5d3f.camel@intel.com> On Sun, 2020-06-07 at 17:36 +0300, Gwan-gyeong Mun wrote: > The IO buffer Wake and Fast Wake bit size and value have been changed from > Gen12+. It programs the default value of IO buffer Wake and Fast Wake on > Gen12+. It adds definitions of IO buffer Wake and Fast Wake for pre Gen12 > and Gen12+. And it aligns PSR2 definition macros. > > v2: Fix macro definitions. (Jos?) > v3: Addressed review comments from Jos? > - Add missing default values of IO_BUFFER_WAKE and FAST_WAKE for GEN9+ > - Change a style of macro naming in order to use lines as input. > - Update Todo comments. > v4: Add parentheses to macros to avoid precedence issues. > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++ > drivers/gpu/drm/i915/i915_reg.h | 52 +++++++++++++++--------- > 2 files changed, 49 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 7a0011e42e00..ab380e6dc674 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -537,6 +537,22 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); > val |= intel_psr2_get_tp_time(intel_dp); > > + if (INTEL_GEN(dev_priv) >= 12) { > + /* > + * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default > + * values from BSpec. In order to setting an optimal power > + * consumption, lower than 4k resoluition mode needs to decrese > + * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution > + * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. > + */ > + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; > + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); > + val |= TGL_EDP_PSR2_FAST_WAKE(7); > + } else if (INTEL_GEN(dev_priv) >= 9) { > + val |= EDP_PSR2_IO_BUFFER_WAKE(7); > + val |= EDP_PSR2_FAST_WAKE(7); > + } > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > * recommending keep this bit unset while PSR2 is enabled. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 814a70945468..4066f67175dc 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4511,25 +4511,39 @@ enum { > #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ > #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ > > -#define _PSR2_CTL_A 0x60900 > -#define _PSR2_CTL_EDP 0x6f900 > -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > -#define EDP_PSR2_ENABLE (1 << 31) > -#define EDP_SU_TRACK_ENABLE (1 << 30) > -#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > -#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > -#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > -#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > -#define EDP_PSR2_TP2_TIME_500us (0 << 8) > -#define EDP_PSR2_TP2_TIME_100us (1 << 8) > -#define EDP_PSR2_TP2_TIME_2500us (2 << 8) > -#define EDP_PSR2_TP2_TIME_50us (3 << 8) > -#define EDP_PSR2_TP2_TIME_MASK (3 << 8) > -#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > -#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) > -#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) > -#define EDP_PSR2_IDLE_FRAME_MASK 0xf > -#define EDP_PSR2_IDLE_FRAME_SHIFT 0 > +#define _PSR2_CTL_A 0x60900 > +#define _PSR2_CTL_EDP 0x6f900 > +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) > +#define EDP_PSR2_ENABLE (1 << 31) > +#define EDP_SU_TRACK_ENABLE (1 << 30) > +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) > +#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) > +#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ > +#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ > +#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) > +#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) > +#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 > +#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) > +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) > +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) > +#define EDP_PSR2_FAST_WAKE_MAX_LINES 8 > +#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) > +#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) > +#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 > +#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) > +#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) > +#define EDP_PSR2_TP2_TIME_500us (0 << 8) > +#define EDP_PSR2_TP2_TIME_100us (1 << 8) > +#define EDP_PSR2_TP2_TIME_2500us (2 << 8) > +#define EDP_PSR2_TP2_TIME_50us (3 << 8) > +#define EDP_PSR2_TP2_TIME_MASK (3 << 8) > +#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > +#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) > +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) > +#define EDP_PSR2_IDLE_FRAME_MASK 0xf > +#define EDP_PSR2_IDLE_FRAME_SHIFT 0 > > #define _PSR_EVENT_TRANS_A 0x60848 > #define _PSR_EVENT_TRANS_B 0x61848 From hdegoede at redhat.com Sun Jun 7 18:14:21 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:14:21 +0200 Subject: [Intel-gfx] [PATCH 02/16] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) In-Reply-To: <20200607170337.GY2428291@smile.fi.intel.com> References: <20200606202601.48410-1-hdegoede@redhat.com> <20200606202601.48410-3-hdegoede@redhat.com> <20200607170337.GY2428291@smile.fi.intel.com> Message-ID: <56c5bc07-0b44-82a2-3cd5-e325546c538f@redhat.com> Hi, On 6/7/20 7:03 PM, Andy Shevchenko wrote: > On Sat, Jun 06, 2020 at 10:25:47PM +0200, Hans de Goede wrote: >> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM >> controller gets turned off from the _PS3 method of the graphics-card dev: >> >> Method (_PS3, 0, Serialized) // _PS3: Power State 3 >> { >> ... >> PWMB = PWMC /* \_SB_.PCI0.GFX0.PWMC */ >> PSAT |= 0x03 >> Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ >> ... >> } >> >> Where PSAT is the power-status register of the PWM controller. >> >> Since the i915 driver will do a pwm_get on the pwm device as it uses it to >> control the LCD panel backlight, there is a device-link marking the i915 >> device as a consumer of the pwm device. So that the PWM controller will >> always be suspended after the i915 driver suspends (which is the right >> thing to do). This causes the above GFX0 PS3 AML code to run before >> acpi_lpss.c calls acpi_lpss_save_ctx(). >> >> So on these devices the PWM controller will already be off when >> acpi_lpss_save_ctx() runs. This causes it to read/save all 1-s (0xffffffff) >> as ctx register values. >> >> When these bogus values get restored on resume the PWM controller actually >> keeps working, since most bits are reserved, but this does set bit 3 of >> the LPSS General purpose register, which for the PWM controller has the >> following function: "This bit is re-used to support 32kHz slow mode. >> Default is 19.2MHz as PWM source clock". >> >> This causes the clock of the PWM controller to switch from 19.2MHz to >> 32KHz, which is a slow-down of a factor 600. Suprisingly enough so far >> there have been few bug reports about this. This is likely because the >> i915 driver was hardcoding the PWM frequency to 46 KHz, which divided >> by 600 would result in a PWM frequency of approx. 78 Hz, which mostly >> still works fine. There are some bug reports about the LCD backlight >> flickering after suspend/resume which are likely caused by this issue. >> >> But with the upcoming patch-series to finally switch the i915 drivers >> code for external PWM controllers to use the atomic API and to honor >> the PWM frequency specified in the video BIOS (VBT), this becomes a much >> bigger problem. On most cases the VBT specifies either 200 Hz or 20 >> KHz as PWM frequency, which with the mentioned issue ends up being either >> 1/3 Hz, where the backlight actually visible blinks on and off every 3s, >> or in 33 Hz and horrible flickering of the backlight. >> >> There are a number of possible solutions to this problem: >> >> 1. Make acpi_lpss_save_ctx() run before GFX0._PS3 >> Pro: Clean solution from pov of not medling with save/restore ctx code >> Con: As mentioned the current ordering is the right thing to do >> Con: Requires assymmetry in at what suspend/resume phase we do the save vs >> restore, requiring more suspend/resume ordering hacks in already >> convoluted acpi_lpss.c suspend/resume code. >> 2. Do some sort of save once mode for the LPSS ctx >> Pro: Reasonably clean >> Con: Needs a new LPSS flag + code changes to handle the flag >> 3. Detect we have failed to save the ctx registers and do not restore them >> Pro: Not PWM specific, might help with issues on other LPSS devices too >> Con: If we can get away with not restoring the ctx why bother with it at >> all? >> 4. Do not save the ctx for CHT PWM controllers >> Pro: Clean, as simple as dropping a flag? >> Con: Not so simple as dropping a flag, needs a new flag to ensure that >> we still do lpss_deassert_reset() on device activation. >> 5. Make the pwm-lpss code fixup the LPSS-context registers >> Pro: Keeps acpi_lpss.c code clean >> Con: Moves knowledge of LPSS-context into the pwm-lpss.c code >> >> 1 and 5 both do not seem to be a desirable way forward. >> >> 3 and 4 seem ok, but they both assume that restoring the LPSS-context >> registers is not necessary. I have done a couple of test and those do >> show that restoring the LPSS-context indeed does not seem to be necessary >> on devices using s2idle suspend (and successfully reaching S0i3). But I >> have no hardware to test deep / S3 suspend. So I'm not sure that not >> restoring the context is safe. >> >> That leaves solution 2, which is about as simple / clean as 3 and 4, >> so this commit fixes the described problem by implementing a new >> LPSS_SAVE_CTX_ONCE flag and setting that for the CHT PWM controllers. >> >> Signed-off-by: Hans de Goede <hdegoede at redhat.com> >> --- >> drivers/acpi/acpi_lpss.c | 19 ++++++++++++++++--- >> 1 file changed, 16 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c >> index 67892fc0b822..26933e6b7b8c 100644 >> --- a/drivers/acpi/acpi_lpss.c >> +++ b/drivers/acpi/acpi_lpss.c >> @@ -68,6 +68,14 @@ ACPI_MODULE_NAME("acpi_lpss"); >> #define LPSS_LTR BIT(3) >> #define LPSS_SAVE_CTX BIT(4) >> #define LPSS_NO_D3_DELAY BIT(5) >> +/* >> + * For some devices the DSDT AML code for another device turns off the device >> + * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) >> + * as ctx register values. >> + * Luckily these devices always use the same ctx register values, so we can >> + * work around this by saving the ctx registers once on activation. >> + */ >> +#define LPSS_SAVE_CTX_ONCE BIT(6) > > A nit: I would group SAVE_CTX and CTX_ONCE in the list, i.e. make this BIT(5) > and move NO_D3_DELAY to BIT(6). Ok, I've fixed this for v2 which I will send out shortly, as I needed to do a v2 anyways because I accidentally left a debugging patch in the v1 series. Regards, Hans > >> struct lpss_private_data; >> >> @@ -254,7 +262,7 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { >> }; >> >> static const struct lpss_device_desc bsw_pwm_dev_desc = { >> - .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, >> + .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, >> .prv_offset = 0x800, >> .setup = bsw_pwm_setup, >> .resume_from_noirq = true, >> @@ -885,9 +893,14 @@ static int acpi_lpss_activate(struct device *dev) >> * we have to deassert reset line to be sure that ->probe() will >> * recognize the device. >> */ >> - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) >> + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) >> lpss_deassert_reset(pdata); >> >> +#ifdef CONFIG_PM >> + if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) >> + acpi_lpss_save_ctx(dev, pdata); >> +#endif >> + >> return 0; >> } >> >> @@ -1031,7 +1044,7 @@ static int acpi_lpss_resume(struct device *dev) >> >> acpi_lpss_d3_to_d0_delay(pdata); >> >> - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) >> + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) >> acpi_lpss_restore_ctx(dev, pdata); >> >> return 0; >> -- >> 2.26.2 >> > From hdegoede at redhat.com Sun Jun 7 18:15:46 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:15:46 +0200 Subject: [Intel-gfx] pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <606dd687-f560-3798-afec-fbab8418d212@redhat.com> Hi All, I forgot the [PATCH 0/16] part of the subject here and I accidentally left a patch adding some debugging printk-s in the series. I will send out a v2 addressing this. Regards, Hans On 6/6/20 10:25 PM, Hans de Goede wrote: > Hi All, > > This patch series converts the i915 driver's cpde for controlling the > panel's backlight with an external PWM controller to use the atomic PWM API. > > Initially the plan was for this series to consist of 2 parts: > 1. convert the pwm-crc driver to support the atomic PWM API and > 2. convert the i915 driver's PWM code to use the atomic PWM API. > > But during testing I've found a number of bugs in the pwm-lpss and I > found that the acpi_lpss code needs some special handling because of > some ugliness found in most Cherry Trail DSDTs. > > So now this series has grown somewhat large and consists of 4 parts: > > 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness > 2. various fixes to the pwm-lpss driver > 3. convert the pwm-crc driver to support the atomic PWM API and > 4. convert the i915 driver's PWM code to use the atomic PWM API > > So we need to discuss how to merge this (once it passes review). > Although the inter-dependencies are only runtime I still think we should > make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before > merging the i915 changes. Both to make sure that the intel-gfx CI system > does not become unhappy and for bisecting reasons. > > The involved acpi_lpss and pwm drivers do not see a whole lot of churn, > so we could just merge everything through dinq, or we could use immutable > branch and merge those into dinq. > > So Rafael and Thierry, can I either get your Acked-by for directly merging > this into dinq, or can you provide an immutable branch with these patches? > > This series has been tested (and re-tested after adding various bug-fixes) > extensively. It has been tested on the following devices: > > -Asus T100TA BYT + CRC-PMIC PWM > -Toshiba WT8-A BYT + CRC-PMIC PWM > -Thundersoft TS178 BYT + CRC-PMIC PWM, inverse PWM > -Asus T100HA CHT + CRC-PMIC PWM > -Terra Pad 1061 BYT + LPSS PWM > -Trekstor Twin 10.1 BYT + LPSS PWM > -Asus T101HA CHT + CRC-PMIC PWM > -GPD Pocket CHT + CRC-PMIC PWM > > Regards, > > Hans > From hdegoede at redhat.com Sun Jun 7 18:18:25 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:25 +0200 Subject: [Intel-gfx] [PATCH v2 00/15] pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Message-ID: <20200607181840.13536-1-hdegoede@redhat.com> Hi All, Here is v2 dropping a debugging-patch which I accidentally kept for v1 and addressing a minor review remark from Andy for the 2nd patch. This patch series converts the i915 driver's code for controlling the panel's backlight with an external PWM controller to use the atomic PWM API. Initially the plan was for this series to consist of 2 parts: 1. convert the pwm-crc driver to support the atomic PWM API and 2. convert the i915 driver's PWM code to use the atomic PWM API. But during testing I've found a number of bugs in the pwm-lpss and I found that the acpi_lpss code needs some special handling because of some ugliness found in most Cherry Trail DSDTs. So now this series has grown somewhat large and consists of 4 parts: 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness 2. various fixes to the pwm-lpss driver 3. convert the pwm-crc driver to support the atomic PWM API and 4. convert the i915 driver's PWM code to use the atomic PWM API So we need to discuss how to merge this (once it passes review). Although the inter-dependencies are only runtime I still think we should make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before merging the i915 changes. Both to make sure that the intel-gfx CI system does not become unhappy and for bisecting reasons. The involved acpi_lpss and pwm drivers do not see a whole lot of churn, so we could just merge everything through dinq, or we could use immutable branch and merge those into dinq. So Rafael and Thierry, can I either get your Acked-by for directly merging this into dinq, or can you provide an immutable branch with these patches? This series has been tested (and re-tested after adding various bug-fixes) extensively. It has been tested on the following devices: -Asus T100TA BYT + CRC-PMIC PWM -Toshiba WT8-A BYT + CRC-PMIC PWM -Thundersoft TS178 BYT + CRC-PMIC PWM, inverse PWM -Asus T100HA CHT + CRC-PMIC PWM -Terra Pad 1061 BYT + LPSS PWM -Trekstor Twin 10.1 BYT + LPSS PWM -Asus T101HA CHT + CRC-PMIC PWM -GPD Pocket CHT + CRC-PMIC PWM Regards, Hans From hdegoede at redhat.com Sun Jun 7 18:18:26 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:26 +0200 Subject: [Intel-gfx] [PATCH v2 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-2-hdegoede@redhat.com> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM controller gets poked from the _PS0 method of the graphics-card device: Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ If (((Local0 & 0x03) == 0x03)) { PSAT &= 0xFFFFFFFC Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ RSTA = Zero RSTF = Zero RSTA = One RSTF = One PWMB |= 0xC0000000 PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */ } Where PSAT is the power-status register of the PWM controller, so if it is in D3 when the GFX0 device's PS0 method runs then it will turn it on and restore the PWM ctrl register value it saved from its PS3 handler. Note not only does it restore it, it ors it with 0xC0000000 turning it on at a time where we may not want it to get turned on at all. The pwm_get call which the i915 driver does to get a reference to the PWM controller, already adds a device-link making the GFX0 device a consumer of the PWM device. So it should already have been resumed when the above AML runs and the AML should thus not do its undesirable poking of the PWM controller register. But the PCI core powers on PCI devices in the no-irq resume phase and thus calls the troublesome PS0 method in the no-irq resume phase. Where as LPSS devices by default are resumed in the early resume phase. This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc struct, so that Cherry Trail PWM controllers will be resumed in the no-irq phase. Together with the device-link added by the pwm-get this ensures that the PWM controller will be on when the troublesome PS0 method runs, which stops it from poking the PWM controller. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/acpi/acpi_lpss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 5e2bfbcf526f..67892fc0b822 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = { .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, .prv_offset = 0x800, .setup = bsw_pwm_setup, + .resume_from_noirq = true, }; static const struct lpss_device_desc byt_uart_dev_desc = { -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:27 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:27 +0200 Subject: [Intel-gfx] [PATCH v2 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-3-hdegoede@redhat.com> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM controller gets turned off from the _PS3 method of the graphics-card dev: Method (_PS3, 0, Serialized) // _PS3: Power State 3 { ... PWMB = PWMC /* \_SB_.PCI0.GFX0.PWMC */ PSAT |= 0x03 Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ ... } Where PSAT is the power-status register of the PWM controller. Since the i915 driver will do a pwm_get on the pwm device as it uses it to control the LCD panel backlight, there is a device-link marking the i915 device as a consumer of the pwm device. So that the PWM controller will always be suspended after the i915 driver suspends (which is the right thing to do). This causes the above GFX0 PS3 AML code to run before acpi_lpss.c calls acpi_lpss_save_ctx(). So on these devices the PWM controller will already be off when acpi_lpss_save_ctx() runs. This causes it to read/save all 1-s (0xffffffff) as ctx register values. When these bogus values get restored on resume the PWM controller actually keeps working, since most bits are reserved, but this does set bit 3 of the LPSS General purpose register, which for the PWM controller has the following function: "This bit is re-used to support 32kHz slow mode. Default is 19.2MHz as PWM source clock". This causes the clock of the PWM controller to switch from 19.2MHz to 32KHz, which is a slow-down of a factor 600. Surprisingly enough so far there have been few bug reports about this. This is likely because the i915 driver was hardcoding the PWM frequency to 46 KHz, which divided by 600 would result in a PWM frequency of approx. 78 Hz, which mostly still works fine. There are some bug reports about the LCD backlight flickering after suspend/resume which are likely caused by this issue. But with the upcoming patch-series to finally switch the i915 drivers code for external PWM controllers to use the atomic API and to honor the PWM frequency specified in the video BIOS (VBT), this becomes a much bigger problem. On most cases the VBT specifies either 200 Hz or 20 KHz as PWM frequency, which with the mentioned issue ends up being either 1/3 Hz, where the backlight actually visible blinks on and off every 3s, or in 33 Hz and horrible flickering of the backlight. There are a number of possible solutions to this problem: 1. Make acpi_lpss_save_ctx() run before GFX0._PS3 Pro: Clean solution from pov of not medling with save/restore ctx code Con: As mentioned the current ordering is the right thing to do Con: Requires assymmetry in at what suspend/resume phase we do the save vs restore, requiring more suspend/resume ordering hacks in already convoluted acpi_lpss.c suspend/resume code. 2. Do some sort of save once mode for the LPSS ctx Pro: Reasonably clean Con: Needs a new LPSS flag + code changes to handle the flag 3. Detect we have failed to save the ctx registers and do not restore them Pro: Not PWM specific, might help with issues on other LPSS devices too Con: If we can get away with not restoring the ctx why bother with it at all? 4. Do not save the ctx for CHT PWM controllers Pro: Clean, as simple as dropping a flag? Con: Not so simple as dropping a flag, needs a new flag to ensure that we still do lpss_deassert_reset() on device activation. 5. Make the pwm-lpss code fixup the LPSS-context registers Pro: Keeps acpi_lpss.c code clean Con: Moves knowledge of LPSS-context into the pwm-lpss.c code 1 and 5 both do not seem to be a desirable way forward. 3 and 4 seem ok, but they both assume that restoring the LPSS-context registers is not necessary. I have done a couple of test and those do show that restoring the LPSS-context indeed does not seem to be necessary on devices using s2idle suspend (and successfully reaching S0i3). But I have no hardware to test deep / S3 suspend. So I'm not sure that not restoring the context is safe. That leaves solution 2, which is about as simple / clean as 3 and 4, so this commit fixes the described problem by implementing a new LPSS_SAVE_CTX_ONCE flag and setting that for the CHT PWM controllers. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v2: - Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX --- drivers/acpi/acpi_lpss.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 67892fc0b822..a8d7d83ac761 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -67,7 +67,15 @@ ACPI_MODULE_NAME("acpi_lpss"); #define LPSS_CLK_DIVIDER BIT(2) #define LPSS_LTR BIT(3) #define LPSS_SAVE_CTX BIT(4) -#define LPSS_NO_D3_DELAY BIT(5) +/* + * For some devices the DSDT AML code for another device turns off the device + * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) + * as ctx register values. + * Luckily these devices always use the same ctx register values, so we can + * work around this by saving the ctx registers once on activation. + */ +#define LPSS_SAVE_CTX_ONCE BIT(5) +#define LPSS_NO_D3_DELAY BIT(6) struct lpss_private_data; @@ -254,7 +262,7 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { }; static const struct lpss_device_desc bsw_pwm_dev_desc = { - .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, + .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, .prv_offset = 0x800, .setup = bsw_pwm_setup, .resume_from_noirq = true, @@ -885,9 +893,14 @@ static int acpi_lpss_activate(struct device *dev) * we have to deassert reset line to be sure that ->probe() will * recognize the device. */ - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) lpss_deassert_reset(pdata); +#ifdef CONFIG_PM + if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) + acpi_lpss_save_ctx(dev, pdata); +#endif + return 0; } @@ -1031,7 +1044,7 @@ static int acpi_lpss_resume(struct device *dev) acpi_lpss_d3_to_d0_delay(pdata); - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) acpi_lpss_restore_ctx(dev, pdata); return 0; -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:28 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:28 +0200 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-4-hdegoede@redhat.com> When the user requests a high enough period ns value, then the calculations in pwm_lpss_prepare() might result in a base_unit value of 0. But according to the data-sheet the way the PWM controller works is that each input clock-cycle the base_unit gets added to a N bit counter and that counter overflowing determines the PWM output frequency. Adding 0 to the counter is a no-op. The data-sheet even explicitly states that writing 0 to the base_unit bits will result in the PWM outputting a continuous 0 signal. base_unit values > (base_unit_range / 256), or iow base_unit values using the 8 most significant bits, cause loss of resolution of the duty-cycle. E.g. assuming a base_unit_range of 65536 steps, then a base_unit value of 768 (256 * 3), limits the duty-cycle resolution to 65536 / 768 = 85 steps. Clamp the max base_unit value to base_unit_range / 32 to ensure a duty-cycle resolution of at least 32 steps. This limits the maximum output frequency to 600 KHz / 780 KHz depending on the base clock. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-lpss.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 9d965ffe66d1..cae74ce61654 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -97,6 +97,14 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, freq *= base_unit_range; base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); + /* + * base_unit must not be 0 and for values > (base_unit_range / 256) + * (values using the 8 most significant bits) the duty-cycle resolution + * degrades. Clamp the maximum value to base_unit_range / 32 which + * leaves a duty-cycle resolution of 32 steps. + */ + base_unit = clamp_t(unsigned long long, base_unit, 1, + base_unit_range / 32); on_time_div = 255ULL * duty_ns; do_div(on_time_div, period_ns); @@ -105,7 +113,6 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, orig_ctrl = ctrl = pwm_lpss_read(pwm); ctrl &= ~PWM_ON_TIME_DIV_MASK; ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); - base_unit &= base_unit_range; ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:29 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:29 +0200 Subject: [Intel-gfx] [PATCH v2 04/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-5-hdegoede@redhat.com> According to the data-sheet the way the PWM controller works is that each input clock-cycle the base_unit gets added to a N bit counter and that counter overflowing determines the PWM output frequency. So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, after 65535 input clock-cycles the counter has been increased from 0 to 65535 and it will overflow on the next cycle, so it will overflow after every 65536 clock cycles and thus the calculations done in pwm_lpss_prepare() should use 65536 and not 65535. This commit fixes this. Note this also aligns the calculations in pwm_lpss_prepare() with those in pwm_lpss_get_state(). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-lpss.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index cae74ce61654..a764e062103b 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -93,7 +93,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, * The equation is: * base_unit = round(base_unit_range * freq / c) */ - base_unit_range = BIT(lpwm->info->base_unit_bits) - 1; + base_unit_range = BIT(lpwm->info->base_unit_bits); freq *= base_unit_range; base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); @@ -112,7 +112,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, orig_ctrl = ctrl = pwm_lpss_read(pwm); ctrl &= ~PWM_ON_TIME_DIV_MASK; - ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); + ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:30 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:30 +0200 Subject: [Intel-gfx] [PATCH v2 05/15] pwm: lpss: Set SW_UPDATE bit when enabling the PWM In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-6-hdegoede@redhat.com> On the LPSS PWM controller found on Bay Trail (BYT) and Cherry Trail (CHT) platforms, the following sequence results in an output duty-cycle of 100% independent of what the duty-cycle requested in the ctrl-reg is: 1. Clear ENABLE bit in ctrl register 2. Let the machine reach a S0i3 low power state 3. Set the ENABLE bit in the ctrl register The LPSS PWM controller has a mechanism where the ctrl register value and the actual base-unit and on-time-div values used are latched. When software sets the SW_UPDATE bit then at the end of the current PWM cycle, the new values from the ctrl-register will be latched into the actual registers, and the SW_UPDATE bit will be cleared. Note on BYT and CHT the ENABLE bit must be set before waiting for the SW_UPDATE bit to clear, otherwise the SW_UPDATE bit will never clear (this is indicated in the pwm-lpss.c code by lpwm->info->bypass being false). My theory about why this is happening is that when we hit S0i3 the part which holds the latched values gets turned off and when its turned back on again at least the on-time-div value has been lost and gets reset to 0 which corresponds to an output duty-cycle of 100%. Testing has shown that setting the SW_UPDATE bit to request latching the ctrl-register values into the actual registers (again) fixes this, confirming this theory. In the past there have been issues where setting the SW_UPDATE bit when nothing has changed would lead to the next ctrl register changing being ignored, see commit 2153bbc12f77 ("pwm: lpss: Only set update bit if we are actually changing the settings"), so we should only set the SW_UPDATE bit when actually changing the ENABLE bit from 0 to 1. When looking into how to fix this I noticed that on platforms where lpwm->info->bypass == false we unnecessarily do 2 read-modify-write cycles of the ctrl register, one to set the base-unit and on-time-div, immediately followed by another to set the ENABLE bit. This commit fixes the 100% duty cycle issue by folding the setting of the ENABLE bit into pwm_lpss_prepare(), which already checks if any bits in the ctrl-register have actually changed and if that is the case then sets the SW_UPDATE bit. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-lpss.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index a764e062103b..2cb0e2a9c08c 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -80,7 +80,7 @@ static inline int pwm_lpss_is_updating(struct pwm_device *pwm) } static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, - int duty_ns, int period_ns) + int duty_ns, int period_ns, bool enable) { unsigned long long on_time_div; unsigned long c = lpwm->info->clk_rate, base_unit_range; @@ -115,6 +115,8 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; + if (enable) + ctrl |= PWM_ENABLE; if (orig_ctrl != ctrl) { pwm_lpss_write(pwm, ctrl); @@ -142,8 +144,9 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, pm_runtime_put(chip->dev); return ret; } - pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); - pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); + pwm_lpss_prepare(lpwm, pwm, + state->duty_cycle, state->period, + lpwm->info->bypass == false); ret = pwm_lpss_wait_for_update(pwm); if (ret) { pm_runtime_put(chip->dev); @@ -154,7 +157,8 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, ret = pwm_lpss_is_updating(pwm); if (ret) return ret; - pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); + pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, + state->period, false); return pwm_lpss_wait_for_update(pwm); } } else if (pwm_is_enabled(pwm)) { -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:31 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:31 +0200 Subject: [Intel-gfx] [PATCH v2 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-7-hdegoede@redhat.com> While looking into adding atomic-pwm support to the pwm-crc driver I noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and there is a clock-divider which divides this with a value between 1-128, and there are 256 duty-cycle steps. The pwm-crc code before this commit assumed that a clock-divider setting of 1 means that the PWM output is running at 6 MHZ, if that is true, where do these 256 duty-cycle steps come from? This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that seems unlikely for a PMIC which is using a silicon process optimized for power-switching transistors. It is way more likely that there is an 8 bit counter for the duty cycle which acts as an extra fixed divider wrt the PWM output frequency. The main user of the pwm-crc driver is the i915 GPU driver which uses it for backlight control. Lets compare the PWM register values set by the video-BIOS (the GOP), assuming the extra fixed divider is present versus the PWM frequency specified in the Video-BIOS-Tables: Device: PWM Hz set by BIOS PWM Hz specified in VBT Asus T100TA 200 200 Asus T100HA 200 200 Lenovo Miix 2 8 23437 20000 Toshiba WT8-A 23437 20000 So as we can see if we assume the extra division by 256 then the register values set by the GOP are an exact match for the VBT values, where as otherwise the values would be of by a factor of 256. This commit fixes the period / duty_cycle calculations to take the extra division by 256 into account. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 272eeb071147..43fc912c1fe9 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -21,8 +21,10 @@ #define PWM_MAX_LEVEL 0xFF -#define PWM_BASE_CLK 6000000 /* 6 MHz */ -#define PWM_MAX_PERIOD_NS 21333 /* 46.875KHz */ +#define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ +#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ + +#define NSEC_PER_MHZ 1000 /** * struct crystalcove_pwm - Crystal Cove PWM controller @@ -72,7 +74,7 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, /* changing the clk divisor, need to disable fisrt */ crc_pwm_disable(c, pwm); - clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC; + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:32 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:32 +0200 Subject: [Intel-gfx] [PATCH v2 07/15] pwm: crc: Fix off-by-one error in the clock-divider calculations In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-8-hdegoede@redhat.com> The CRC PWM controller has a clock-divider which divides the clock with a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx defines, this range maps to a register value of 0-127. So after calculating the clock-divider we must subtract 1 to get the register value, unless the requested frequency was so high that the calculation has already resulted in a (rounded) divider value of 0. Note that before this fix, setting a period of PWM_MAX_PERIOD_NS which corresponds to the max. divider value of 128 could have resulted in a bug where the code would use 128 as divider-register value which would have resulted in an actual divider value of 0 (and the enable bit being set). A rounding error stopped this bug from actually happen. This same rounding error means that after the subtraction of 1 it is impossible to set the divider to 128. Also bump PWM_MAX_PERIOD_NS by 1 ns to allow setting a divider of 128 (register-value 127). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 43fc912c1fe9..5ba2a65c524c 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -22,7 +22,7 @@ #define PWM_MAX_LEVEL 0xFF #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ -#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ +#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */ #define NSEC_PER_MHZ 1000 @@ -75,6 +75,9 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, /* changing the clk divisor, need to disable fisrt */ crc_pwm_disable(c, pwm); clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:33 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:33 +0200 Subject: [Intel-gfx] [PATCH v2 08/15] pwm: crc: Fix period changes not having any effect In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-9-hdegoede@redhat.com> The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register I strongly suspect that the BACKLIGHT_EN register at address 0x51 really controls a separate output-only GPIO which is connected to the LCD panels backlight-enable input. Like how the PANEL_EN register at address 0x52 controls an output-only GPIO which is earmarked for the LCD panel's enable pin. If this is correct then this GPIO should really be added to the gpio-crystalcove.c driver and the PWM driver should stop poking it. But I've been unable to come up with a definitive answer here, so I'm keeping this as is for now. As the comment in the old code already indicates we must disable the PWM before we can change the clock divider. But the crc_pwm_disable() and crc_pwm_enable() calls the old code make for this only change the BACKLIGHT_EN register; and the value of that register does not matter for changing the period / the divider. What does matter is that the PWM_OUTPUT_ENABLE bit must be cleared before a new value can be written. This commit modifies crc_pwm_config() to clear PWM_OUTPUT_ENABLE instead when changing the period, so that period changes actually work. Note this fix will cause a significant behavior change on some devices using the CRC PWM output to drive their backlight. Before the PWM would always run with the output frequency configured by the BIOS at boot, now the period time specified by the i915 driver will actually be honored. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 5ba2a65c524c..ef49a6e3c4d6 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -72,8 +72,9 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, if (pwm_get_period(pwm) != period_ns) { int clk_div; - /* changing the clk divisor, need to disable fisrt */ - crc_pwm_disable(c, pwm); + /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); /* clk_div 1 - 128, maps to register values 0-127 */ if (clk_div > 0) @@ -81,9 +82,6 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); - - /* enable back */ - crc_pwm_enable(c, pwm); } /* change the pwm duty cycle */ -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:34 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:34 +0200 Subject: [Intel-gfx] [PATCH v2 09/15] pwm: crc: Enable/disable PWM output on enable/disable In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-10-hdegoede@redhat.com> The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, this commit makes crc_pwm_disable() clear it on disable and makes crc_pwm_enable() set it again on re-enable. This should disable the internal (divided) PWM clock and tri-state the PWM output pin when disabled, saving some power. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index ef49a6e3c4d6..53734bcf67e1 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -41,10 +41,24 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) return container_of(pc, struct crystalcove_pwm, chip); } +static int crc_pwm_calc_clk_div(int period_ns) +{ + int clk_div; + + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; + + return clk_div; +} + static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div | PWM_OUTPUT_ENABLE); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); return 0; @@ -53,8 +67,10 @@ static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div); } static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, @@ -70,16 +86,10 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, } if (pwm_get_period(pwm) != period_ns) { - int clk_div; + int clk_div = crc_pwm_calc_clk_div(period_ns); /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); - - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); - /* clk_div 1 - 128, maps to register values 0-127 */ - if (clk_div > 0) - clk_div--; - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); } -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:35 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:35 +0200 Subject: [Intel-gfx] [PATCH v2 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-11-hdegoede@redhat.com> Replace the enable, disable and config pwm_ops with an apply op, to support the new atomic PWM API. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 107 +++++++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 48 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 53734bcf67e1..58c7e9ef7278 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -41,70 +41,81 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) return container_of(pc, struct crystalcove_pwm, chip); } -static int crc_pwm_calc_clk_div(int period_ns) +static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) { - int clk_div; - - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); - /* clk_div 1 - 128, maps to register values 0-127 */ - if (clk_div > 0) - clk_div--; - - return clk_div; -} - -static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); - int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); - - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div | PWM_OUTPUT_ENABLE); - regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); - - return 0; -} - -static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); - int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); - - regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div); -} - -static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, - int duty_ns, int period_ns) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); + int err, clk_div, level, pwm_output_enable; struct device *dev = crc_pwm->chip.dev; - int level; - if (period_ns > PWM_MAX_PERIOD_NS) { + if (state->period > PWM_MAX_PERIOD_NS) { dev_err(dev, "un-supported period_ns\n"); return -EINVAL; } - if (pwm_get_period(pwm) != period_ns) { - int clk_div = crc_pwm_calc_clk_div(period_ns); + if (state->polarity != PWM_POLARITY_NORMAL) + return -ENOTSUPP; + + if (pwm_is_enabled(pwm) && !state->enabled) { + err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); + if (err) { + dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err); + return err; + } + } + + if (pwm_get_duty_cycle(pwm) != state->duty_cycle || + pwm_get_period(pwm) != state->period) { + level = state->duty_cycle * PWM_MAX_LEVEL / state->period; + err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level); + if (err) { + dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err); + return err; + } + } + + if (pwm_is_enabled(pwm) && state->enabled && + pwm_get_period(pwm) != state->period) { /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, - clk_div | PWM_OUTPUT_ENABLE); + err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); + if (err) { + dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err); + return err; + } } - /* change the pwm duty cycle */ - level = duty_ns * PWM_MAX_LEVEL / period_ns; - regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level); + if (pwm_get_period(pwm) != state->period || + pwm_is_enabled(pwm) != state->enabled) { + clk_div = PWM_BASE_CLK_MHZ * state->period / + (256 * NSEC_PER_MHZ); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; + + pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0; + + err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, + clk_div | pwm_output_enable); + if (err) { + dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err); + return err; + } + } + + if (!pwm_is_enabled(pwm) && state->enabled) { + err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); + if (err) { + dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err); + return err; + } + } return 0; } static const struct pwm_ops crc_pwm_ops = { - .config = crc_pwm_config, - .enable = crc_pwm_enable, - .disable = crc_pwm_disable, + .apply = crc_pwm_apply, }; static int crystalcove_pwm_probe(struct platform_device *pdev) -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:36 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:36 +0200 Subject: [Intel-gfx] [PATCH v2 11/15] pwm: crc: Implement get_state() method In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-12-hdegoede@redhat.com> Implement the pwm_ops.get_state() method to complete the support for the new atomic PWM API. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 58c7e9ef7278..6c75a3470bc8 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -114,8 +114,37 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return 0; } +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); + struct device *dev = crc_pwm->chip.dev; + unsigned int clk_div, clk_div_reg, duty_cycle_reg; + int error; + + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); + if (error) { + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); + return; + } + + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); + if (error) { + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); + return; + } + + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; + + state->period = clk_div * NSEC_PER_MHZ * 256 / PWM_BASE_CLK_MHZ; + state->duty_cycle = duty_cycle_reg * state->period / PWM_MAX_LEVEL; + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); +} + static const struct pwm_ops crc_pwm_ops = { .apply = crc_pwm_apply, + .get_state = crc_pwm_get_state, }; static int crystalcove_pwm_probe(struct platform_device *pdev) -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:37 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:37 +0200 Subject: [Intel-gfx] [PATCH v2 12/15] drm/i915: panel: Add get_vbt_pwm_freq() helper In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-13-hdegoede@redhat.com> Factor the code which checks and drm_dbg_kms-s the VBT PWM frequency out of get_backlight_max_vbt(). This is a preparation patch for honering the VBT PWM frequency for devices which use an external PWM controller (devices using pwm_setup_backlight()). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/gpu/drm/i915/display/intel_panel.c | 27 ++++++++++++++-------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 3c5056dbf607..8efdd9f08a08 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1543,18 +1543,9 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul); } -static u32 get_backlight_max_vbt(struct intel_connector *connector) +static u16 get_vbt_pwm_freq(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_panel *panel = &connector->panel; u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz; - u32 pwm; - - if (!panel->backlight.hz_to_pwm) { - drm_dbg_kms(&dev_priv->drm, - "backlight frequency conversion not supported\n"); - return 0; - } if (pwm_freq_hz) { drm_dbg_kms(&dev_priv->drm, @@ -1567,6 +1558,22 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector) pwm_freq_hz); } + return pwm_freq_hz; +} + +static u32 get_backlight_max_vbt(struct intel_connector *connector) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + u16 pwm_freq_hz = get_vbt_pwm_freq(dev_priv); + u32 pwm; + + if (!panel->backlight.hz_to_pwm) { + drm_dbg_kms(&dev_priv->drm, + "backlight frequency conversion not supported\n"); + return 0; + } + pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz); if (!pwm) { drm_dbg_kms(&dev_priv->drm, -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:38 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:38 +0200 Subject: [Intel-gfx] [PATCH v2 13/15] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-14-hdegoede@redhat.com> So far for devices using an external PWM controller (devices using pwm_setup_backlight()), we have been hardcoding the period-time passed to pwm_config() to 21333 ns. I suspect this was done because many VBTs set the PWM frequency to 200 which corresponds to a period-time of 5000000 ns, which greatly exceeds the PWM_MAX_PERIOD_NS define in the Crystal Cove PMIC PWM driver, which used to be 21333. This PWM_MAX_PERIOD_NS define was actually based on a bug in the PWM driver where its period and duty-cycle times where off by a factor of 256. Due to this bug the hardcoded CRC_PMIC_PWM_PERIOD_NS value of 21333 would result in the PWM driver using its divider of 128, which would result in a PWM output frequency of 6000000 Hz / 256 / 128 = 183 Hz. So actually pretty close to the default VBT value of 200 Hz. Now that this bug in the pwm-crc driver is fixed, we can actually use the VBT defined frequency. This is important because: a) With the pwm-crc driver fixed it will now translate the hardcoded CRC_PMIC_PWM_PERIOD_NS value of 21333 ns / 46 Khz to a PWM output frequency of 23 KHz (the max it can do). b) The pwm-lpss driver used on many models has always honored the 21333 ns / 46 Khz request Some panels do not like such high output frequencies. E.g. on a Terra Pad 1061 tablet, using the LPSS PWM controller, the backlight would go from off to max, when changing the sysfs backlight brightness value from 90-100%, anything under aprox. 90% would turn the backlight fully off. Honoring the VBT specified PWM frequency will also hopefully fix the various bug reports which we have received about users perceiving the backlight to flicker after a suspend/resume cycle. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_panel.c | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index b24266c624fa..24ea4a7b6dde 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -223,6 +223,7 @@ struct intel_panel { bool util_pin_active_low; /* bxt+ */ u8 controller; /* bxt+ only */ struct pwm_device *pwm; + int pwm_period_ns; /* DPCD backlight */ u8 pwmgen_bit_count; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 8efdd9f08a08..14e611c92194 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -40,8 +40,6 @@ #include "intel_dsi_dcs_backlight.h" #include "intel_panel.h" -#define CRC_PMIC_PWM_PERIOD_NS 21333 - void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, struct drm_display_mode *adjusted_mode) @@ -597,7 +595,7 @@ static u32 pwm_get_backlight(struct intel_connector *connector) int duty_ns; duty_ns = pwm_get_duty_cycle(panel->backlight.pwm); - return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS); + return DIV_ROUND_UP(duty_ns * 100, panel->backlight.pwm_period_ns); } static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -671,9 +669,10 @@ static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; - int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); + int duty_ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - pwm_config(panel->backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS); + pwm_config(panel->backlight.pwm, duty_ns, + panel->backlight.pwm_period_ns); } static void @@ -1917,6 +1916,9 @@ static int pwm_setup_backlight(struct intel_connector *connector, return -ENODEV; } + panel->backlight.pwm_period_ns = NSEC_PER_SEC / + get_vbt_pwm_freq(dev_priv); + /* * FIXME: pwm_apply_args() should be removed when switching to * the atomic PWM API. @@ -1926,9 +1928,10 @@ static int pwm_setup_backlight(struct intel_connector *connector, panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ level = intel_panel_compute_brightness(connector, 100); - ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); + ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - retval = pwm_config(panel->backlight.pwm, ns, CRC_PMIC_PWM_PERIOD_NS); + retval = pwm_config(panel->backlight.pwm, ns, + panel->backlight.pwm_period_ns); if (retval < 0) { drm_err(&dev_priv->drm, "Failed to configure the pwm chip\n"); pwm_put(panel->backlight.pwm); @@ -1937,7 +1940,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, } level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, - CRC_PMIC_PWM_PERIOD_NS); + panel->backlight.pwm_period_ns); panel->backlight.level = intel_panel_compute_brightness(connector, level); panel->backlight.enabled = panel->backlight.level != 0; -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:39 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:39 +0200 Subject: [Intel-gfx] [PATCH v2 14/15] drm/i915: panel: Honor the VBT PWM min setting for devs with an external PWM controller In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-15-hdegoede@redhat.com> So far for devices using an external PWM controller (devices using pwm_setup_backlight()), we have been hardcoding the minimum allowed PWM level to 0. But several of these devices specify a non 0 minimum setting in their VBT. Change pwm_setup_backlight() to use get_backlight_min_vbt() to get the minimum level. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/gpu/drm/i915/display/intel_panel.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 14e611c92194..cb28b9908ca4 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1925,8 +1925,8 @@ static int pwm_setup_backlight(struct intel_connector *connector, */ pwm_apply_args(panel->backlight.pwm); - panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ + panel->backlight.min = get_backlight_min_vbt(connector); level = intel_panel_compute_brightness(connector, 100); ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); @@ -1941,8 +1941,9 @@ static int pwm_setup_backlight(struct intel_connector *connector, level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, panel->backlight.pwm_period_ns); - panel->backlight.level = - intel_panel_compute_brightness(connector, level); + level = intel_panel_compute_brightness(connector, level); + panel->backlight.level = clamp(level, panel->backlight.min, + panel->backlight.max); panel->backlight.enabled = panel->backlight.level != 0; drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n", -- 2.26.2 From hdegoede at redhat.com Sun Jun 7 18:18:40 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sun, 7 Jun 2020 20:18:40 +0200 Subject: [Intel-gfx] [PATCH v2 15/15] drm/i915: panel: Use atomic PWM API for devs with an external PWM controller In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <20200607181840.13536-16-hdegoede@redhat.com> Now that the PWM drivers which we use have been converted to the atomic PWM API, we can move the i915 panel code over to using the atomic PWM API. The removes a long standing FIXME and this removes a flicker where the backlight brightness would jump to 100% when i915 loads even if using the fastset path. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- .../drm/i915/display/intel_display_types.h | 3 +- drivers/gpu/drm/i915/display/intel_panel.c | 73 +++++++++---------- 2 files changed, 37 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 24ea4a7b6dde..48afb2925271 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -28,6 +28,7 @@ #include <linux/async.h> #include <linux/i2c.h> +#include <linux/pwm.h> #include <linux/sched/clock.h> #include <drm/drm_atomic.h> @@ -223,7 +224,7 @@ struct intel_panel { bool util_pin_active_low; /* bxt+ */ u8 controller; /* bxt+ only */ struct pwm_device *pwm; - int pwm_period_ns; + struct pwm_state pwm_state; /* DPCD backlight */ u8 pwmgen_bit_count; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index cb28b9908ca4..a0f76343f381 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -592,10 +592,11 @@ static u32 bxt_get_backlight(struct intel_connector *connector) static u32 pwm_get_backlight(struct intel_connector *connector) { struct intel_panel *panel = &connector->panel; - int duty_ns; + int duty_ns, period_ns; duty_ns = pwm_get_duty_cycle(panel->backlight.pwm); - return DIV_ROUND_UP(duty_ns * 100, panel->backlight.pwm_period_ns); + period_ns = pwm_get_period(panel->backlight.pwm); + return DIV_ROUND_UP(duty_ns * 100, period_ns); } static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -669,10 +670,10 @@ static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; - int duty_ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - pwm_config(panel->backlight.pwm, duty_ns, - panel->backlight.pwm_period_ns); + panel->backlight.pwm_state.duty_cycle = + DIV_ROUND_UP(level * panel->backlight.pwm_state.period, 100); + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } static void @@ -841,10 +842,8 @@ static void pwm_disable_backlight(const struct drm_connector_state *old_conn_sta struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct intel_panel *panel = &connector->panel; - /* Disable the backlight */ - intel_panel_actually_set_backlight(old_conn_state, 0); - usleep_range(2000, 3000); - pwm_disable(panel->backlight.pwm); + panel->backlight.pwm_state.enabled = false; + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -1176,9 +1175,14 @@ static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state, { struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_panel *panel = &connector->panel; + int level = panel->backlight.level; - pwm_enable(panel->backlight.pwm); - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + level = intel_panel_compute_brightness(connector, level); + + panel->backlight.pwm_state.duty_cycle = + DIV_ROUND_UP(level * panel->backlight.pwm_state.period, 100); + panel->backlight.pwm_state.enabled = true; + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } static void __intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -1897,8 +1901,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_panel *panel = &connector->panel; const char *desc; - u32 level, ns; - int retval; + u32 level; /* Get the right PWM chip for DSI backlight according to VBT */ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { @@ -1916,36 +1919,30 @@ static int pwm_setup_backlight(struct intel_connector *connector, return -ENODEV; } - panel->backlight.pwm_period_ns = NSEC_PER_SEC / - get_vbt_pwm_freq(dev_priv); - - /* - * FIXME: pwm_apply_args() should be removed when switching to - * the atomic PWM API. - */ - pwm_apply_args(panel->backlight.pwm); - panel->backlight.max = 100; /* 100% */ panel->backlight.min = get_backlight_min_vbt(connector); - level = intel_panel_compute_brightness(connector, 100); - ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - retval = pwm_config(panel->backlight.pwm, ns, - panel->backlight.pwm_period_ns); - if (retval < 0) { - drm_err(&dev_priv->drm, "Failed to configure the pwm chip\n"); - pwm_put(panel->backlight.pwm); - panel->backlight.pwm = NULL; - return retval; + if (pwm_is_enabled(panel->backlight.pwm) && + pwm_get_period(panel->backlight.pwm)) { + /* PWM is already enabled, use existing settings */ + pwm_get_state(panel->backlight.pwm, &panel->backlight.pwm_state); + + level = DIV_ROUND_UP(panel->backlight.pwm_state.duty_cycle * + 100, panel->backlight.pwm_state.period); + level = intel_panel_compute_brightness(connector, level); + panel->backlight.level = clamp(level, panel->backlight.min, + panel->backlight.max); + panel->backlight.enabled = true; + + drm_dbg_kms(&dev_priv->drm, "PWM already enabled at freq %ld, VBT freq %d, level %d\n", + NSEC_PER_SEC / panel->backlight.pwm_state.period, + get_vbt_pwm_freq(dev_priv), level); + } else { + /* Set period from VBT frequency, leave other setting at 0. */ + panel->backlight.pwm_state.period = + NSEC_PER_SEC / get_vbt_pwm_freq(dev_priv); } - level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, - panel->backlight.pwm_period_ns); - level = intel_panel_compute_brightness(connector, level); - panel->backlight.level = clamp(level, panel->backlight.min, - panel->backlight.max); - panel->backlight.enabled = panel->backlight.level != 0; - drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n", desc); return 0; -- 2.26.2 From patchwork at emeril.freedesktop.org Sun Jun 7 18:28:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 18:28:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_pwm/i915=3A_Convert_pwm-crc_and_i915_driver=27s_PWM_code_to?= =?utf-8?q?_use_the_atomic_PWM_API?= In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <159155449374.15986.5218940914735022313@emeril.freedesktop.org> == Series Details == Series: pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API URL : https://patchwork.freedesktop.org/series/78089/ State : warning == Summary == $ dim checkpatch origin/drm-tip e5cf553c0dcc ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase e4c217421240 ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) 50130652086f pwm: lpss: Add range limit check for the base_unit register value cb9922913f55 pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() dba8a9e355db pwm: lpss: Set SW_UPDATE bit when enabling the PWM -:78: CHECK:BOOL_COMPARISON: Using comparison to false is error prone #78: FILE: drivers/pwm/pwm-lpss.c:149: + lpwm->info->bypass == false); total: 0 errors, 0 warnings, 1 checks, 36 lines checked 84fd73d0b37e pwm: crc: Fix period / duty_cycle times being off by a factor of 256 9e2eaeacdf15 pwm: crc: Fix off-by-one error in the clock-divider calculations 8b1bbb8e9bc0 pwm: crc: Fix period changes not having any effect a08d7c7752b8 pwm: crc: Enable/disable PWM output on enable/disable 989f50988bff pwm: crc: Implement apply() method to support the new atomic PWM API 2c6d747e89fe pwm: crc: Implement get_state() method -:20: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #20: FILE: drivers/pwm/pwm-crc.c:118: +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) total: 0 errors, 0 warnings, 1 checks, 37 lines checked 13ddb5bbc283 drm/i915: panel: Add get_vbt_pwm_freq() helper a5b8e319f197 drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller 61594a403a5c drm/i915: panel: Honor the VBT PWM min setting for devs with an external PWM controller dc3969b82041 drm/i915: panel: Use atomic PWM API for devs with an external PWM controller From patchwork at emeril.freedesktop.org Sun Jun 7 18:48:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 18:48:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgcHdt?= =?utf-8?q?/i915=3A_Convert_pwm-crc_and_i915_driver=27s_PWM_code_to_use_th?= =?utf-8?q?e_atomic_PWM_API?= In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <159155570244.15989.10892965241262465668@emeril.freedesktop.org> == Series Details == Series: pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API URL : https://patchwork.freedesktop.org/series/78089/ State : success == Summary == CI Bug Log - changes from CI_DRM_8596 -> Patchwork_17900 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/index.html Known issues ------------ Here are the changes found in Patchwork_17900 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-guc/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-icl-guc/igt at i915_module_load@reload.html - fi-byt-n2820: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_selftest@live at active: - fi-bsw-kefka: [PASS][5] -> [DMESG-FAIL][6] ([i915#541]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-bsw-kefka/igt at i915_selftest@live at active.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-bsw-kefka/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-tgl-dsi/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * {igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1}: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 42) ------------------------------ Missing (7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8596 -> Patchwork_17900 CI-20190529: 20190529 CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17900: dc3969b8204100c0773d5cb805040c0ba47f1ebc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dc3969b82041 drm/i915: panel: Use atomic PWM API for devs with an external PWM controller 61594a403a5c drm/i915: panel: Honor the VBT PWM min setting for devs with an external PWM controller a5b8e319f197 drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller 13ddb5bbc283 drm/i915: panel: Add get_vbt_pwm_freq() helper 2c6d747e89fe pwm: crc: Implement get_state() method 989f50988bff pwm: crc: Implement apply() method to support the new atomic PWM API a08d7c7752b8 pwm: crc: Enable/disable PWM output on enable/disable 8b1bbb8e9bc0 pwm: crc: Fix period changes not having any effect 9e2eaeacdf15 pwm: crc: Fix off-by-one error in the clock-divider calculations 84fd73d0b37e pwm: crc: Fix period / duty_cycle times being off by a factor of 256 dba8a9e355db pwm: lpss: Set SW_UPDATE bit when enabling the PWM cb9922913f55 pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() 50130652086f pwm: lpss: Add range limit check for the base_unit register value e4c217421240 ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) e5cf553c0dcc ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/index.html From jose.souza at intel.com Sun Jun 7 19:44:00 2020 From: jose.souza at intel.com (Souza, Jose) Date: Sun, 7 Jun 2020 19:44:00 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/psr=3A_Program_default_IO_buffer_Wake_and_Fast_Wake_=28re?= =?utf-8?b?djQp?= In-Reply-To: <159154609812.15986.11963873325616919071@emeril.freedesktop.org> References: <20200607143614.185246-1-gwan-gyeong.mun@intel.com> <159154609812.15986.11963873325616919071@emeril.freedesktop.org> Message-ID: <02f6c7cf5833eb85da10ad40b7dd77104ca93132.camel@intel.com> On Sun, 2020-06-07 at 16:08 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev4) > URL : https://patchwork.freedesktop.org/series/78019/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_8596_full -> Patchwork_17899_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. Pushed, thanks for the patch. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17899_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_partial_pwrite_pread@reads-snoop: > - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +7 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl8/igt at gem_partial_pwrite_pread@reads-snoop.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl2/igt at gem_partial_pwrite_pread@reads-snoop.html > > * igt at i915_suspend@debugfs-reader: > - shard-kbl: [PASS][3] -> [INCOMPLETE][4] ([i915#155]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl6/igt at i915_suspend@debugfs-reader.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl2/igt at i915_suspend@debugfs-reader.html > > * igt at i915_suspend@forcewake: > - shard-apl: [PASS][5] -> [INCOMPLETE][6] ([i915#1630]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl7/igt at i915_suspend@forcewake.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl3/igt at i915_suspend@forcewake.html > > * igt at kms_big_fb@x-tiled-8bpp-rotate-0: > - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html > - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk6/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html > > * igt at kms_big_fb@y-tiled-64bpp-rotate-0: > - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk7/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > > * igt at kms_color@pipe-c-ctm-blue-to-red: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +14 similar issues > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt at kms_color@pipe-c-ctm-blue-to-red.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_color@pipe-c-ctm-blue-to-red.html > > * igt at kms_cursor_crc@pipe-b-cursor-suspend: > - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#300]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl10/igt at kms_cursor_crc@pipe-b-cursor-suspend.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html > > * igt at kms_cursor_legacy@pipe-c-torture-bo: > - shard-hsw: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-bo.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw5/igt at kms_cursor_legacy@pipe-c-torture-bo.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: > - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html > > * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: > - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][27] -> [DMESG-FAIL][28] ([fdo#108145] / [i915#1982]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_psr2_su@frontbuffer: > - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109642] / [fdo#111068]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt at kms_psr2_su@frontbuffer.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb6/igt at kms_psr2_su@frontbuffer.html > > * igt at kms_psr@psr2_cursor_render: > - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt at kms_psr@psr2_cursor_render.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb8/igt at kms_psr@psr2_cursor_render.html > > * igt at kms_vblank@pipe-c-ts-continuation-suspend: > - shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +1 similar issue > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt at kms_vblank@pipe-c-ts-continuation-suspend.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html > > > #### Possible fixes #### > > * {igt at gem_exec_schedule@implicit-write-read at rcs0}: > - shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html > > * igt at gem_exec_whisper@basic-normal: > - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk7/igt at gem_exec_whisper@basic-normal.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk8/igt at gem_exec_whisper@basic-normal.html > > * igt at gem_workarounds@suspend-resume-fd: > - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +5 similar issues > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl7/igt at gem_workarounds@suspend-resume-fd.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl4/igt at gem_workarounds@suspend-resume-fd.html > > * igt at kms_big_fb@x-tiled-16bpp-rotate-0: > - shard-glk: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-glk9/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: > - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +6 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > > * igt at kms_color@pipe-c-ctm-red-to-blue: > - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt at kms_color@pipe-c-ctm-red-to-blue.html > > * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: > - shard-skl: [FAIL][47] ([i915#54]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > > * igt at kms_cursor_crc@pipe-b-cursor-suspend: > - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl7/igt at kms_cursor_crc@pipe-b-cursor-suspend.html > > * igt at kms_cursor_legacy@pipe-c-torture-move: > - shard-hsw: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-move.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw4/igt at kms_cursor_legacy@pipe-c-torture-move.html > > * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size: > - shard-apl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl6/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl2/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size.html > > * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu: > - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +17 similar issues > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: > - shard-skl: [FAIL][57] ([i915#49]) -> [PASS][58] +1 similar issue > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt at kms_psr@psr2_sprite_render: > - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb3/igt at kms_psr@psr2_sprite_render.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb2/igt at kms_psr@psr2_sprite_render.html > > * igt at kms_setmode@basic: > - shard-apl: [FAIL][63] ([i915#31]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt at kms_setmode@basic.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_setmode@basic.html > > * igt at kms_vblank@pipe-a-wait-forked-hang: > - shard-hsw: [INCOMPLETE][65] ([i915#61]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw4/igt at kms_vblank@pipe-a-wait-forked-hang.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-hsw8/igt at kms_vblank@pipe-a-wait-forked-hang.html > > > #### Warnings #### > > * igt at i915_pm_rc6_residency@rc6-idle: > - shard-iclb: [WARN][67] ([i915#1515]) -> [FAIL][68] ([i915#1515]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb5/igt at i915_pm_rc6_residency@rc6-idle.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html > > * igt at kms_content_protection@atomic: > - shard-kbl: [TIMEOUT][69] ([i915#1319] / [i915#1958]) -> [TIMEOUT][70] ([i915#1319]) +1 similar issue > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl4/igt at kms_content_protection@atomic.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl7/igt at kms_content_protection@atomic.html > - shard-apl: [TIMEOUT][71] ([i915#1319]) -> [FAIL][72] ([fdo#110321] / [fdo#110336]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt at kms_content_protection@atomic.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl1/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@lic: > - shard-kbl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_content_protection@lic.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl6/igt at kms_content_protection@lic.html > > * igt at kms_content_protection@srm: > - shard-apl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl6/igt at kms_content_protection@srm.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-apl2/igt at kms_content_protection@srm.html > > * igt at kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][77] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#93] / [i915#95]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1630]: https://gitlab.freedesktop.org/drm/intel/issues/1630 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8596 -> Patchwork_17899 > > CI-20190529: 20190529 > CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17899: c063779ca55740c59aacc4d6ae5ee0ed9a4488e5 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17899/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Sun Jun 7 19:44:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 19:44:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgcHdt?= =?utf-8?q?/i915=3A_Convert_pwm-crc_and_i915_driver=27s_PWM_code_to_use_th?= =?utf-8?q?e_atomic_PWM_API?= In-Reply-To: <20200607181840.13536-1-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> Message-ID: <159155905816.15987.2460269927591879895@emeril.freedesktop.org> == Series Details == Series: pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API URL : https://patchwork.freedesktop.org/series/78089/ State : success == Summary == CI Bug Log - changes from CI_DRM_8596_full -> Patchwork_17900_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17900_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk5/igt at gem_exec_whisper@basic-contexts-forked.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-glk6/igt at gem_exec_whisper@basic-contexts-forked.html * igt at gem_partial_pwrite_pread@reads-snoop: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +9 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl8/igt at gem_partial_pwrite_pread@reads-snoop.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl6/igt at gem_partial_pwrite_pread@reads-snoop.html * igt at gem_workarounds@suspend-resume: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl4/igt at gem_workarounds@suspend-resume.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-apl6/igt at gem_workarounds@suspend-resume.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl6/igt at gen9_exec_parse@allowed-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl2/igt at gen9_exec_parse@allowed-all.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-tglb8/igt at i915_module_load@reload-with-fault-injection.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_suspend@forcewake: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#636] / [i915#69]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl6/igt at i915_suspend@forcewake.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl2/igt at i915_suspend@forcewake.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk9/igt at kms_big_fb@linear-64bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([i915#54] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([i915#1185] / [i915#250]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-iclb3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#69]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl9/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][27] -> [DMESG-FAIL][28] ([fdo#108145] / [i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#95]) +5 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt at kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-apl6/igt at kms_plane_alpha_blend@pipe-b-coverage-vs-premult-vs-constant.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109642] / [fdo#111068]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-iclb4/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][33] -> [FAIL][34] ([i915#173]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt at kms_psr@no_drrs.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-iclb5/igt at kms_psr@psr2_cursor_render.html #### Possible fixes #### * {igt at gem_exec_schedule@implicit-write-read at rcs0}: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-normal: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk7/igt at gem_exec_whisper@basic-normal.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-glk5/igt at gem_exec_whisper@basic-normal.html * igt at gem_tiled_pread_basic: - shard-apl: [DMESG-WARN][41] ([i915#95]) -> [PASS][42] +13 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl4/igt at gem_tiled_pread_basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-apl3/igt at gem_tiled_pread_basic.html * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl7/igt at gem_workarounds@suspend-resume-fd.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl6/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_suspend@forcewake: - shard-glk: [INCOMPLETE][45] ([i915#58] / [k.org#198133]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-glk9/igt at i915_suspend@forcewake.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-glk8/igt at i915_suspend@forcewake.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +8 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-red-to-blue: - shard-kbl: [DMESG-WARN][49] ([i915#93] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_color@pipe-c-ctm-red-to-blue.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl1/igt at kms_color@pipe-c-ctm-red-to-blue.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-hsw: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-move.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-hsw6/igt at kms_cursor_legacy@pipe-c-torture-move.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-apl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-apl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: - shard-skl: [FAIL][55] ([i915#49]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl7/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl5/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-iclb5/igt at kms_psr@psr2_sprite_plane_move.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-wait-forked-hang: - shard-hsw: [INCOMPLETE][61] ([i915#61]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-hsw4/igt at kms_vblank@pipe-a-wait-forked-hang.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-hsw6/igt at kms_vblank@pipe-a-wait-forked-hang.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][63] ([i915#1319] / [i915#1958]) -> [TIMEOUT][64] ([i915#1319]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl4/igt at kms_content_protection@atomic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl2/igt at kms_content_protection@atomic.html - shard-apl: [TIMEOUT][65] ([i915#1319]) -> [DMESG-FAIL][66] ([fdo#110321]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl2/igt at kms_content_protection@atomic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-apl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][67] ([i915#1319]) -> [TIMEOUT][68] ([i915#1319] / [i915#1958]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl3/igt at kms_content_protection@legacy.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][69] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][70] ([fdo#110321] / [i915#95]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl4/igt at kms_content_protection@lic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-apl6/igt at kms_content_protection@lic.html - shard-kbl: [DMESG-FAIL][71] ([fdo#110321] / [i915#95]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl2/igt at kms_content_protection@lic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl1/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][73] ([i915#1319] / [i915#1958]) -> [DMESG-FAIL][74] ([fdo#110321] / [i915#95]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-kbl4/igt at kms_content_protection@srm.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-kbl2/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-apl6/igt at kms_content_protection@srm.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-apl1/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-snb: [TIMEOUT][77] ([i915#1958]) -> [INCOMPLETE][78] ([i915#82]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8596/shard-snb5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/shard-snb1/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8596 -> Patchwork_17900 CI-20190529: 20190529 CI_DRM_8596: ac91b8351ce380da73dbe8b87d1e4f95aa0c4409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17900: dc3969b8204100c0773d5cb805040c0ba47f1ebc @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17900/index.html From imre.deak at intel.com Sun Jun 7 21:25:20 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 8 Jun 2020 00:25:20 +0300 Subject: [Intel-gfx] [PATCH 1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port Message-ID: <20200607212522.16935-1-imre.deak@intel.com> The WARN below triggers during the removal of an MST port. The problem is that the parent device's (the connector's kdev) sysfs directory is removed recursively when the connector is unregistered (even though the I2C device holds a reference on the parent device). To fix this set first the Peer Device Type to none which will remove the I2C device. Note that atm, inconsistently, the parent of the I2C device is initially set to the DRM kdev and after a Connection Status Notification the parent may be reset to be the connector's kdev. This problem is addressed by the next patch. [ 4462.989299] ------------[ cut here ]------------ [ 4463.014940] sysfs group 'power' not found for kobject 'i2c-24' [ 4463.034664] WARNING: CPU: 0 PID: 970 at fs/sysfs/group.c:281 sysfs_remove_group+0x71/0x80 [ 4463.044357] Modules linked in: snd_hda_intel i915 drm_kms_helper(O) drm netconsole snd_hda_codec_hdmi mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul snd_intel_dspcf g crc32_pclmul snd_hda_codec snd_hwdep ghash_clmulni_intel snd_hda_core asix usbnet kvm_intel mii i2c_algo_bit snd_pcm syscopyarea sysfillrect e1000e sysimgblt fb_sys_fops prim e_numbers ptp pps_core i2c_i801 r8169 mei_me realtek mei [last unloaded: drm] [ 4463.044399] CPU: 0 PID: 970 Comm: kworker/0:2 Tainted: G O 5.7.0+ #172 [ 4463.044402] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP [ 4463.044423] Workqueue: events drm_dp_delayed_destroy_work [drm_kms_helper] [ 4463.044428] RIP: 0010:sysfs_remove_group+0x71/0x80 [ 4463.044431] Code: 48 89 df 5b 5d 41 5c e9 cd b6 ff ff 48 89 df e8 95 b4 ff ff eb cb 49 8b 14 24 48 8b 75 00 48 c7 c7 20 0f 3f 82 e8 9f c5 d7 ff <0f> 0b 5b 5d 41 5c c3 0f 1f 84 00 00 00 00 00 48 85 f6 74 31 41 54 [ 4463.044433] RSP: 0018:ffffc900018bfbf0 EFLAGS: 00010282 [ 4463.044436] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000001 [ 4463.044439] RDX: 0000000080000001 RSI: ffff88849e828f38 RDI: 00000000ffffffff [ 4463.052970] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:100:plane 2B] 00000000c2160caa state to 00000000d172564a [ 4463.070533] RBP: ffffffff820cea20 R08: ffff88847f4b8958 R09: 0000000000000000 [ 4463.070535] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848a725018 [ 4463.070537] R13: 0000000000000000 R14: ffffffff827090e0 R15: 0000000000000002 [ 4463.070539] FS: 0000000000000000(0000) GS:ffff88849e800000(0000) knlGS:0000000000000000 [ 4463.070541] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 4463.070543] CR2: 00007fdf8a756538 CR3: 0000000489684001 CR4: 0000000000760ef0 [ 4463.070545] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 4463.070547] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 4463.070549] PKRU: 55555554 [ 4463.070551] Call Trace: [ 4463.070560] device_del+0x84/0x400 [ 4463.070571] cdev_device_del+0x10/0x30 [ 4463.070578] put_i2c_dev+0x69/0x80 [ 4463.070584] i2cdev_detach_adapter+0x2e/0x60 [ 4463.070591] notifier_call_chain+0x34/0x90 [ 4463.070599] blocking_notifier_call_chain+0x3f/0x60 [ 4463.070606] device_del+0x7c/0x400 [ 4463.087817] ? lockdep_init_map_waits+0x57/0x210 [ 4463.087825] device_unregister+0x11/0x60 [ 4463.087829] i2c_del_adapter+0x249/0x310 [ 4463.087846] drm_dp_port_set_pdt+0x6b/0x2c0 [drm_kms_helper] [ 4463.087862] drm_dp_delayed_destroy_work+0x2af/0x350 [drm_kms_helper] [ 4463.087876] process_one_work+0x268/0x600 [ 4463.105438] ? __schedule+0x30c/0x920 [ 4463.105451] worker_thread+0x37/0x380 [ 4463.105457] ? process_one_work+0x600/0x600 [ 4463.105462] kthread+0x140/0x160 [ 4463.105466] ? kthread_park+0x80/0x80 [ 4463.105474] ret_from_fork+0x24/0x50 Cc: <stable at vger.kernel.org> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 2a309fb2c4cc..02c800b8199f 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -4669,12 +4669,13 @@ static void drm_dp_tx_work(struct work_struct *work) static inline void drm_dp_delayed_destroy_port(struct drm_dp_mst_port *port) { + drm_dp_port_set_pdt(port, DP_PEER_DEVICE_NONE, port->mcs); + if (port->connector) { drm_connector_unregister(port->connector); drm_connector_put(port->connector); } - drm_dp_port_set_pdt(port, DP_PEER_DEVICE_NONE, port->mcs); drm_dp_mst_put_port_malloc(port); } -- 2.23.1 From imre.deak at intel.com Sun Jun 7 21:25:21 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 8 Jun 2020 00:25:21 +0300 Subject: [Intel-gfx] [PATCH 2/3] drm/dp_mst: Fix the DDC I2C device registration of an MST port In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <20200607212522.16935-2-imre.deak@intel.com> During the initial MST probing an MST port's I2C device will be registered using the kdev of the DRM device as a parent. Later after MST Connection Status Notifications this I2C device will be re-registered with the kdev of the port's connector. This will also move inconsistently the I2C device's sysfs entry from the DRM device's sysfs dir to the connector's dir. Fix the above by keeping the DRM kdev as the parent of the I2C device. Ideally the connector's kdev would be used as a parent, similarly to non-MST connectors, however that needs some more refactoring to ensure the connector's kdev is already available early enough. So keep the existing (initial) behavior for now. Cc: <stable at vger.kernel.org> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 02c800b8199f..083255c33ee0 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -88,8 +88,8 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, u8 *guid); -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux); -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux); +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port); +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port); static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr); #define DBG_PREFIX "[dp_mst]" @@ -1993,7 +1993,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, } /* remove i2c over sideband */ - drm_dp_mst_unregister_i2c_bus(&port->aux); + drm_dp_mst_unregister_i2c_bus(port); } else { mutex_lock(&mgr->lock); drm_dp_mst_topology_put_mstb(port->mstb); @@ -2008,7 +2008,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, if (port->pdt != DP_PEER_DEVICE_NONE) { if (drm_dp_mst_is_end_device(port->pdt, port->mcs)) { /* add i2c over sideband */ - ret = drm_dp_mst_register_i2c_bus(&port->aux); + ret = drm_dp_mst_register_i2c_bus(port); } else { lct = drm_dp_calculate_rad(port, rad); mstb = drm_dp_add_mst_branch_device(lct, rad); @@ -5375,22 +5375,26 @@ static const struct i2c_algorithm drm_dp_mst_i2c_algo = { /** * drm_dp_mst_register_i2c_bus() - register an I2C adapter for I2C-over-AUX - * @aux: DisplayPort AUX channel + * @port: The port to add the I2C bus on * * Returns 0 on success or a negative error code on failure. */ -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port) { + struct drm_dp_aux *aux = &port->aux; + struct device *parent_dev = port->mgr->dev->dev; + aux->ddc.algo = &drm_dp_mst_i2c_algo; aux->ddc.algo_data = aux; aux->ddc.retries = 3; aux->ddc.class = I2C_CLASS_DDC; aux->ddc.owner = THIS_MODULE; - aux->ddc.dev.parent = aux->dev; - aux->ddc.dev.of_node = aux->dev->of_node; + /* FIXME: set the kdev of the port's connector as parent */ + aux->ddc.dev.parent = parent_dev; + aux->ddc.dev.of_node = parent_dev->of_node; - strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), + strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(parent_dev), sizeof(aux->ddc.name)); return i2c_add_adapter(&aux->ddc); @@ -5398,11 +5402,11 @@ static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) /** * drm_dp_mst_unregister_i2c_bus() - unregister an I2C-over-AUX adapter - * @aux: DisplayPort AUX channel + * @port: The port to remove the I2C bus from */ -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux) +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port) { - i2c_del_adapter(&aux->ddc); + i2c_del_adapter(&port->aux.ddc); } /** -- 2.23.1 From imre.deak at intel.com Sun Jun 7 21:25:22 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 8 Jun 2020 00:25:22 +0300 Subject: [Intel-gfx] [PATCH 3/3] drm/dp_mst: Fix flushing the delayed port/mstb destroy work In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <20200607212522.16935-3-imre.deak@intel.com> Atm, a pending delayed destroy work during module removal will be canceled, leaving behind MST ports, mstbs. Fix this by using a dedicated workqueue which will be drained of requeued items as well when destroying it. Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 17 ++++++++++++++--- include/drm/drm_dp_mst_helper.h | 8 ++++++++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 083255c33ee0..075fb5ac9264 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1630,7 +1630,7 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) mutex_lock(&mgr->delayed_destroy_lock); list_add(&mstb->destroy_next, &mgr->destroy_branch_device_list); mutex_unlock(&mgr->delayed_destroy_lock); - schedule_work(&mgr->delayed_destroy_work); + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); } /** @@ -1747,7 +1747,7 @@ static void drm_dp_destroy_port(struct kref *kref) mutex_lock(&mgr->delayed_destroy_lock); list_add(&port->next, &mgr->destroy_port_list); mutex_unlock(&mgr->delayed_destroy_lock); - schedule_work(&mgr->delayed_destroy_work); + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); } /** @@ -5208,6 +5208,15 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, INIT_LIST_HEAD(&mgr->destroy_port_list); INIT_LIST_HEAD(&mgr->destroy_branch_device_list); INIT_LIST_HEAD(&mgr->up_req_list); + + /* + * delayed_destroy_work will be queued on a dedicated WQ, so that any + * requeuing will be also flushed when deiniting the topology manager. + */ + mgr->delayed_destroy_wq = alloc_ordered_workqueue("drm_dp_mst_wq", 0); + if (mgr->delayed_destroy_wq == NULL) + return -ENOMEM; + INIT_WORK(&mgr->work, drm_dp_mst_link_probe_work); INIT_WORK(&mgr->tx_work, drm_dp_tx_work); INIT_WORK(&mgr->delayed_destroy_work, drm_dp_delayed_destroy_work); @@ -5252,7 +5261,9 @@ void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr) { drm_dp_mst_topology_mgr_set_mst(mgr, false); flush_work(&mgr->work); - cancel_work_sync(&mgr->delayed_destroy_work); + /* The following will also drain any requeued work on the WQ. */ + destroy_workqueue(mgr->delayed_destroy_wq); + mgr->delayed_destroy_wq = NULL; mutex_lock(&mgr->payload_lock); kfree(mgr->payloads); mgr->payloads = NULL; diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index b230ff6f7081..8b9eb4db3381 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -681,6 +681,14 @@ struct drm_dp_mst_topology_mgr { * @destroy_branch_device_list. */ struct mutex delayed_destroy_lock; + + /** + * @delayed_destroy_wq: Workqueue used for delayed_destroy_work items. + * A dedicated WQ makes it possible to drain any requeued work items + * on it. + */ + struct workqueue_struct *delayed_destroy_wq; + /** * @delayed_destroy_work: Work item to destroy MST port and branch * devices, needed to avoid locking inversion. -- 2.23.1 From patchwork at emeril.freedesktop.org Sun Jun 7 21:59:34 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 21:59:34 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/3=5D_drm/dp=5Fmst=3A_Fix_the_DDC_?= =?utf-8?q?I2C_device_unregistration_of_an_MST_port?= In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <159156717442.15986.4268397518812956628@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port URL : https://patchwork.freedesktop.org/series/78100/ State : warning == Summary == $ dim checkpatch origin/drm-tip be4cb6213842 drm/dp_mst: Fix the DDC I2C device unregistration of an MST port -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: Note that atm, inconsistently, the parent of the I2C device is initially set to total: 0 errors, 1 warnings, 0 checks, 14 lines checked f183ac475a8b drm/dp_mst: Fix the DDC I2C device registration of an MST port c3019da98129 drm/dp_mst: Fix flushing the delayed port/mstb destroy work -:45: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!mgr->delayed_destroy_wq" #45: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:5191: + if (mgr->delayed_destroy_wq == NULL) total: 0 errors, 0 warnings, 1 checks, 55 lines checked From jose.souza at intel.com Sun Jun 7 22:11:44 2020 From: jose.souza at intel.com (Souza, Jose) Date: Sun, 7 Jun 2020 22:11:44 +0000 Subject: [Intel-gfx] [PATCH RESEND v3 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <20200605094801.17709-1-imre.deak@intel.com> References: <20200604184500.23730-1-imre.deak@intel.com> <20200605094801.17709-1-imre.deak@intel.com> Message-ID: <854f3594de3a7531eb4e4fa1cf4449bcd7b02dea.camel@intel.com> On Fri, 2020-06-05 at 12:48 +0300, Imre Deak wrote: > Currently MST on a port can get enabled/disabled from the hotplug work > and get disabled from the short pulse work in a racy way. Fix this by > relying on the MST state checking in the hotplug work and just schedule > a hotplug work from the short pulse handler if some problem happened > during the MST interrupt handling. > > This removes the explicit MST disabling in case of an AUX failure, but > if AUX fails, then probably the detection will also fail during the > scheduled hotplug work and it's not guaranteed that we'll see > intermittent errors anyway. > > While at it also simplify the error checking of the MST interrupt > handler. > > v2: > - Convert intel_dp_check_mst_status() to return bool. (Ville) > - Change the intel_dp->is_mst check to an assert, since after this patch > the condition can't change after we checked it previously. > - Document the return value from intel_dp_check_mst_status(). > v3: > - Remove the intel_dp->is_mst check from intel_dp_check_mst_status(). > There is no point in checking the same condition twice, even though > there is a chance that the hotplug work running concurrently changes > it. > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> (v1) > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++--------------- > 1 file changed, 26 insertions(+), 40 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 55fda074c0ad..42589cae766d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5556,35 +5556,46 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) > "Could not write test response to sink\n"); > } > > -static int > +/** > + * intel_dp_check_mst_status - service any pending MST interrupts, check link status > + * @intel_dp: Intel DP struct > + * > + * Read any pending MST interrupts, call MST core to handle these and ack the > + * interrupts. Check if the main and AUX link state is ok. > + * > + * Returns: > + * - %true if pending interrupts were serviced (or no interrupts were > + * pending) w/o detecting an error condition. > + * - %false if an error condition - like AUX failure or a loss of link - is > + * detected, which needs servicing from the hotplug work. > + */ > +static bool > intel_dp_check_mst_status(struct intel_dp *intel_dp) > { > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > - bool need_retrain = false; > - > - if (!intel_dp->is_mst) > - return -EINVAL; > + bool link_ok = true; > > drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); > > for (;;) { > u8 esi[DP_DPRX_ESI_LEN] = {}; > - bool bret, handled; > + bool handled; > int retry; > > - bret = intel_dp_get_sink_irq_esi(intel_dp, esi); > - if (!bret) { > + if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { > drm_dbg_kms(&i915->drm, > "failed to get ESI - device may have failed\n"); > - return -EINVAL; > + link_ok = false; > + > + break; > } > > /* check link status - esi[10] = 0x200c */ > - if (intel_dp->active_mst_links > 0 && !need_retrain && > + if (intel_dp->active_mst_links > 0 && link_ok && > !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { > drm_dbg_kms(&i915->drm, > "channel EQ not ok, retraining\n"); > - need_retrain = true; > + link_ok = false; > } > > drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); > @@ -5604,7 +5615,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) > } > } > > - return need_retrain; > + return link_ok; > } > > static bool > @@ -7255,35 +7266,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > } > > if (intel_dp->is_mst) { > - switch (intel_dp_check_mst_status(intel_dp)) { > - case -EINVAL: > - /* > - * If we were in MST mode, and device is not > - * there, get out of MST mode > - */ > - drm_dbg_kms(&i915->drm, > - "MST device may have disappeared %d vs %d\n", > - intel_dp->is_mst, > - intel_dp->mst_mgr.mst_state); > - intel_dp->is_mst = false; > - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > - intel_dp->is_mst); > - > - return IRQ_NONE; > - case 1: > - return IRQ_NONE; > - default: > - break; > - } > - } > - > - if (!intel_dp->is_mst) { > - bool handled; > - > - handled = intel_dp_short_pulse(intel_dp); > - > - if (!handled) > + if (!intel_dp_check_mst_status(intel_dp)) > return IRQ_NONE; > + } else if (!intel_dp_short_pulse(intel_dp)) { > + return IRQ_NONE; > } > Now it don't need the braces but this is minor. Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > return IRQ_HANDLED; From chris at chris-wilson.co.uk Sun Jun 7 22:20:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:46 +0100 Subject: [Intel-gfx] [PATCH 06/28] drm/i915/gt: Use virtual_engine during execlists_dequeue In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-6-chris@chris-wilson.co.uk> Rather than going back and forth between the rb_node entry and the virtual_engine type, store the ve local and reuse it. As the container_of conversion from rb_node to virtual_engine requires a variable offset, performing that conversion just once shaves off a bit of code. v2: Keep a single virtual engine lookup, for typical use. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 217 +++++++++++++--------------- 1 file changed, 104 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index db8a170b0e5c..ab1f3131b357 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -454,7 +454,7 @@ static int queue_prio(const struct intel_engine_execlists *execlists) static inline bool need_preempt(const struct intel_engine_cs *engine, const struct i915_request *rq, - struct rb_node *rb) + struct virtual_engine *ve) { int last_prio; @@ -491,9 +491,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, rq_prio(list_next_entry(rq, sched.link)) > last_prio) return true; - if (rb) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { bool preempt = false; if (engine == ve->siblings[0]) { /* only preempt one sibling */ @@ -1811,6 +1809,35 @@ static bool virtual_matches(const struct virtual_engine *ve, return true; } +static struct virtual_engine * +first_virtual_engine(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists *el = &engine->execlists; + struct rb_node *rb = rb_first_cached(&el->virtual); + + while (rb) { + struct virtual_engine *ve = + rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + struct i915_request *rq = READ_ONCE(ve->request); + + if (!rq) { /* lazily cleanup after another engine handled rq */ + rb_erase_cached(rb, &el->virtual); + RB_CLEAR_NODE(rb); + rb = rb_first_cached(&el->virtual); + continue; + } + + if (!virtual_matches(ve, rq, engine)) { + rb = rb_next(rb); + continue; + } + + return ve; + } + + return NULL; +} + static void virtual_xfer_breadcrumbs(struct virtual_engine *ve) { /* @@ -1895,7 +1922,7 @@ static void defer_active(struct intel_engine_cs *engine) static bool need_timeslice(const struct intel_engine_cs *engine, const struct i915_request *rq, - const struct rb_node *rb) + struct virtual_engine *ve) { int hint; @@ -1904,9 +1931,7 @@ need_timeslice(const struct intel_engine_cs *engine, hint = engine->execlists.queue_priority_hint; - if (rb) { - const struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { const struct intel_engine_cs *inflight = intel_context_inflight(&ve->context); @@ -2057,7 +2082,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = READ_ONCE(execlists->active); + struct virtual_engine *ve = first_virtual_engine(engine); struct i915_request *last; struct rb_node *rb; bool submit = false; @@ -2084,26 +2110,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * and context switches) submission. */ - for (rb = rb_first_cached(&execlists->virtual); rb; ) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); - struct i915_request *rq = READ_ONCE(ve->request); - - if (!rq) { /* lazily cleanup after another engine handled rq */ - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } - - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - - break; - } - /* * If the queue is higher priority than the last * request in the currently active context, submit afresh. @@ -2111,10 +2117,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2125,9 +2128,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * find itself trying to jump back into a context it has just * completed and barf. */ - if ((last = *active)) { - if (need_preempt(engine, last, rb)) { + if (need_preempt(engine, last, ve)) { if (i915_request_completed(last)) { tasklet_hi_schedule(&execlists->tasklet); return; @@ -2158,7 +2160,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) __unwind_incomplete_requests(engine); last = NULL; - } else if (need_timeslice(engine, last, rb) && + } else if (need_timeslice(engine, last, ve) && timeslice_expired(execlists, last)) { if (i915_request_completed(last)) { tasklet_hi_schedule(&execlists->tasklet); @@ -2212,110 +2214,99 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } } - while (rb) { /* XXX virtual is always taking precedence */ - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + while (ve) { /* XXX virtual is always taking precedence */ struct i915_request *rq; spin_lock(&ve->base.active.lock); rq = ve->request; - if (unlikely(!rq)) { /* lost the race to a sibling */ - spin_unlock(&ve->base.active.lock); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } + if (unlikely(!rq)) /* lost the race to a sibling */ + goto unlock; GEM_BUG_ON(rq != ve->request); GEM_BUG_ON(rq->engine != &ve->base); GEM_BUG_ON(rq->context != &ve->context); - if (rq_prio(rq) >= queue_prio(execlists)) { - if (!virtual_matches(ve, rq, engine)) { - spin_unlock(&ve->base.active.lock); - rb = rb_next(rb); - continue; - } + if (unlikely(rq_prio(rq) < queue_prio(execlists))) { + spin_unlock(&ve->base.active.lock); + break; + } - if (last && !can_merge_rq(last, rq)) { - spin_unlock(&ve->base.active.lock); - start_timeslice(engine, rq_prio(rq)); - return; /* leave this for another sibling */ - } + GEM_BUG_ON(!virtual_matches(ve, rq, engine)); - ENGINE_TRACE(engine, - "virtual rq=%llx:%lld%s, new engine? %s\n", - rq->fence.context, - rq->fence.seqno, - i915_request_completed(rq) ? "!" : - i915_request_started(rq) ? "*" : - "", - yesno(engine != ve->siblings[0])); - - WRITE_ONCE(ve->request, NULL); - WRITE_ONCE(ve->base.execlists.queue_priority_hint, - INT_MIN); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); + if (last && !can_merge_rq(last, rq)) { + spin_unlock(&ve->base.active.lock); + start_timeslice(engine, rq_prio(rq)); + return; /* leave this for another sibling */ + } - GEM_BUG_ON(!(rq->execution_mask & engine->mask)); - WRITE_ONCE(rq->engine, engine); + ENGINE_TRACE(engine, + "virtual rq=%llx:%lld%s, new engine? %s\n", + rq->fence.context, + rq->fence.seqno, + i915_request_completed(rq) ? "!" : + i915_request_started(rq) ? "*" : + "", + yesno(engine != ve->siblings[0])); - if (engine != ve->siblings[0]) { - u32 *regs = ve->context.lrc_reg_state; - unsigned int n; + WRITE_ONCE(ve->request, NULL); + WRITE_ONCE(ve->base.execlists.queue_priority_hint, + INT_MIN); - GEM_BUG_ON(READ_ONCE(ve->context.inflight)); + rb = &ve->nodes[engine->id].rb; + rb_erase_cached(rb, &execlists->virtual); + RB_CLEAR_NODE(rb); - if (!intel_engine_has_relative_mmio(engine)) - virtual_update_register_offsets(regs, - engine); + GEM_BUG_ON(!(rq->execution_mask & engine->mask)); + WRITE_ONCE(rq->engine, engine); - if (!list_empty(&ve->context.signals)) - virtual_xfer_breadcrumbs(ve); + if (engine != ve->siblings[0]) { + u32 *regs = ve->context.lrc_reg_state; + unsigned int n; - /* - * Move the bound engine to the top of the list - * for future execution. We then kick this - * tasklet first before checking others, so that - * we preferentially reuse this set of bound - * registers. - */ - for (n = 1; n < ve->num_siblings; n++) { - if (ve->siblings[n] == engine) { - swap(ve->siblings[n], - ve->siblings[0]); - break; - } - } + GEM_BUG_ON(READ_ONCE(ve->context.inflight)); - GEM_BUG_ON(ve->siblings[0] != engine); - } + if (!intel_engine_has_relative_mmio(engine)) + virtual_update_register_offsets(regs, + engine); - if (__i915_request_submit(rq)) { - submit = true; - last = rq; - } - i915_request_put(rq); + if (!list_empty(&ve->context.signals)) + virtual_xfer_breadcrumbs(ve); /* - * Hmm, we have a bunch of virtual engine requests, - * but the first one was already completed (thanks - * preempt-to-busy!). Keep looking at the veng queue - * until we have no more relevant requests (i.e. - * the normal submit queue has higher priority). + * Move the bound engine to the top of the list for + * future execution. We then kick this tasklet first + * before checking others, so that we preferentially + * reuse this set of bound registers. */ - if (!submit) { - spin_unlock(&ve->base.active.lock); - rb = rb_first_cached(&execlists->virtual); - continue; + for (n = 1; n < ve->num_siblings; n++) { + if (ve->siblings[n] == engine) { + swap(ve->siblings[n], + ve->siblings[0]); + break; + } } + + GEM_BUG_ON(ve->siblings[0] != engine); } + if (__i915_request_submit(rq)) { + submit = true; + last = rq; + } + + i915_request_put(rq); +unlock: spin_unlock(&ve->base.active.lock); - break; + + /* + * Hmm, we have a bunch of virtual engine requests, + * but the first one was already completed (thanks + * preempt-to-busy!). Keep looking at the veng queue + * until we have no more relevant requests (i.e. + * the normal submit queue has higher priority). + */ + ve = submit ? NULL : first_virtual_engine(engine); } while ((rb = rb_first_cached(&execlists->queue))) { -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:47 +0100 Subject: [Intel-gfx] [PATCH 07/28] drm/i915/gt: Decouple inflight virtual engines In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-7-chris@chris-wilson.co.uk> Once a virtual engine has been bound to a sibling, it will remain bound until we finally schedule out the last active request. We can not rebind the context to a new sibling while it is inflight as the context save will conflict, hence we wait. As we cannot then use any other sibliing while the context is inflight, only kick the bound sibling while it inflight and upon scheduling out the kick the rest (so that we can swap engines on timeslicing if the previously bound engine becomes oversubscribed). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +++++++++++++---------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index ab1f3131b357..d98e37900171 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1403,9 +1403,8 @@ execlists_schedule_in(struct i915_request *rq, int idx) static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); - struct i915_request *next = READ_ONCE(ve->request); - if (next == rq || (next && next->execution_mask & ~rq->execution_mask)) + if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); } @@ -1820,18 +1819,14 @@ first_virtual_engine(struct intel_engine_cs *engine) rb_entry(rb, typeof(*ve), nodes[engine->id].rb); struct i915_request *rq = READ_ONCE(ve->request); - if (!rq) { /* lazily cleanup after another engine handled rq */ + /* lazily cleanup after another engine handled rq */ + if (!rq || !virtual_matches(ve, rq, engine)) { rb_erase_cached(rb, &el->virtual); RB_CLEAR_NODE(rb); rb = rb_first_cached(&el->virtual); continue; } - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - return ve; } @@ -5469,7 +5464,6 @@ static void virtual_submission_tasklet(unsigned long data) if (unlikely(!mask)) return; - local_irq_disable(); for (n = 0; n < ve->num_siblings; n++) { struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]); struct ve_node * const node = &ve->nodes[sibling->id]; @@ -5479,20 +5473,19 @@ static void virtual_submission_tasklet(unsigned long data) if (!READ_ONCE(ve->request)) break; /* already handled by a sibling's tasklet */ + spin_lock_irq(&sibling->active.lock); + if (unlikely(!(mask & sibling->mask))) { if (!RB_EMPTY_NODE(&node->rb)) { - spin_lock(&sibling->active.lock); rb_erase_cached(&node->rb, &sibling->execlists.virtual); RB_CLEAR_NODE(&node->rb); - spin_unlock(&sibling->active.lock); } - continue; - } - spin_lock(&sibling->active.lock); + goto unlock_engine; + } - if (!RB_EMPTY_NODE(&node->rb)) { + if (unlikely(!RB_EMPTY_NODE(&node->rb))) { /* * Cheat and avoid rebalancing the tree if we can * reuse this node in situ. @@ -5532,9 +5525,12 @@ static void virtual_submission_tasklet(unsigned long data) if (first && prio > sibling->execlists.queue_priority_hint) tasklet_hi_schedule(&sibling->execlists.tasklet); - spin_unlock(&sibling->active.lock); +unlock_engine: + spin_unlock_irq(&sibling->active.lock); + + if (intel_context_inflight(&ve->context)) + break; } - local_irq_enable(); } static void virtual_submit_request(struct i915_request *rq) -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:03 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:03 +0100 Subject: [Intel-gfx] [PATCH 23/28] drm/i915: Restructure priority inheritance In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-23-chris@chris-wilson.co.uk> In anticipation of wanting to be able to call pi from underneath an engine's active.lock, rework the priority inheritance to primarily work along an engine's priority queue, delegating any other engine that the chain may traverse to a worker. This reduces the global spinlock from governing the entire priority inheritance depth-first search, to a small lock around a single list. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_scheduler.c | 236 ++++++++++---------- drivers/gpu/drm/i915/i915_scheduler_types.h | 6 +- 2 files changed, 121 insertions(+), 121 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index f9cd8baaefcd..320d3720ba34 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -17,7 +17,46 @@ static struct i915_global_scheduler { struct kmem_cache *slab_priorities; } global; -static DEFINE_SPINLOCK(schedule_lock); +static DEFINE_SPINLOCK(ipi_lock); +static LIST_HEAD(ipi_list); + +static inline int rq_prio(const struct i915_request *rq) +{ + return READ_ONCE(rq->sched.attr.priority); +} + +static void ipi_schedule(struct irq_work *wrk) +{ + rcu_read_lock(); + do { + struct i915_dependency *p; + struct i915_request *rq; + unsigned long flags; + int prio; + + spin_lock_irqsave(&ipi_lock, flags); + p = list_first_entry_or_null(&ipi_list, typeof(*p), ipi_link); + if (p) { + rq = container_of(p->signaler, typeof(*rq), sched); + list_del_init(&p->ipi_link); + + prio = p->ipi_priority; + p->ipi_priority = I915_PRIORITY_INVALID; + } + spin_unlock_irqrestore(&ipi_lock, flags); + if (!p) + break; + + if (i915_request_completed(rq)) + continue; + + if (prio > rq_prio(rq)) + i915_request_set_priority(rq, prio); + } while (1); + rcu_read_unlock(); +} + +static DEFINE_IRQ_WORK(ipi_work, ipi_schedule); static const struct i915_request * node_to_request(const struct i915_sched_node *node) @@ -126,42 +165,6 @@ void __i915_priolist_free(struct i915_priolist *p) kmem_cache_free(global.slab_priorities, p); } -struct sched_cache { - struct list_head *priolist; -}; - -static struct intel_engine_cs * -sched_lock_engine(const struct i915_sched_node *node, - struct intel_engine_cs *locked, - struct sched_cache *cache) -{ - const struct i915_request *rq = node_to_request(node); - struct intel_engine_cs *engine; - - GEM_BUG_ON(!locked); - - /* - * Virtual engines complicate acquiring the engine timeline lock, - * as their rq->engine pointer is not stable until under that - * engine lock. The simple ploy we use is to take the lock then - * check that the rq still belongs to the newly locked engine. - */ - while (locked != (engine = READ_ONCE(rq->engine))) { - spin_unlock(&locked->active.lock); - memset(cache, 0, sizeof(*cache)); - spin_lock(&engine->active.lock); - locked = engine; - } - - GEM_BUG_ON(locked != engine); - return locked; -} - -static inline int rq_prio(const struct i915_request *rq) -{ - return rq->sched.attr.priority; -} - static inline bool need_preempt(int prio, int active) { /* @@ -216,25 +219,15 @@ static void kick_submission(struct intel_engine_cs *engine, rcu_read_unlock(); } -static void __i915_schedule(struct i915_sched_node *node, int prio) +static void __i915_request_set_priority(struct i915_request *rq, int prio) { - struct intel_engine_cs *engine; - struct i915_dependency *dep, *p; - struct i915_dependency stack; - struct sched_cache cache; + struct intel_engine_cs *engine = rq->engine; + struct i915_request *rn; + struct list_head *plist; LIST_HEAD(dfs); - /* Needed in order to use the temporary link inside i915_dependency */ - lockdep_assert_held(&schedule_lock); - GEM_BUG_ON(prio == I915_PRIORITY_INVALID); - - if (node_signaled(node)) - return; - - prio = max(prio, node->attr.priority); - - stack.signaler = node; - list_add(&stack.dfs_link, &dfs); + lockdep_assert_held(&engine->active.lock); + list_add(&rq->sched.dfs, &dfs); /* * Recursively bump all dependent priorities to match the new request. @@ -254,66 +247,47 @@ static void __i915_schedule(struct i915_sched_node *node, int prio) * end result is a topological list of requests in reverse order, the * last element in the list is the request we must execute first. */ - list_for_each_entry(dep, &dfs, dfs_link) { - struct i915_sched_node *node = dep->signaler; + list_for_each_entry(rq, &dfs, sched.dfs) { + struct i915_dependency *p; - /* If we are already flying, we know we have no signalers */ - if (node_started(node)) - continue; + /* Also release any children on this engine that are ready */ + GEM_BUG_ON(rq->engine != engine); - /* - * Within an engine, there can be no cycle, but we may - * refer to the same dependency chain multiple times - * (redundant dependencies are not eliminated) and across - * engines. - */ - list_for_each_entry(p, &node->signalers_list, signal_link) { - GEM_BUG_ON(p == dep); /* no cycles! */ + for_each_signaler(p, rq) { + struct i915_request *s = + container_of(p->signaler, typeof(*s), sched); - if (node_signaled(p->signaler)) - continue; + GEM_BUG_ON(s == rq); - if (prio > READ_ONCE(p->signaler->attr.priority)) - list_move_tail(&p->dfs_link, &dfs); - } - } + if (rq_prio(s) >= prio) + continue; - /* - * If we didn't need to bump any existing priorities, and we haven't - * yet submitted this request (i.e. there is no potential race with - * execlists_submit_request()), we can set our own priority and skip - * acquiring the engine locks. - */ - if (node->attr.priority == I915_PRIORITY_INVALID) { - GEM_BUG_ON(!list_empty(&node->link)); - node->attr.priority = prio; + if (i915_request_completed(s)) + continue; - if (stack.dfs_link.next == stack.dfs_link.prev) - return; + if (s->engine != rq->engine) { + spin_lock(&ipi_lock); + if (prio > p->ipi_priority) { + p->ipi_priority = prio; + list_move(&p->ipi_link, &ipi_list); + irq_work_queue(&ipi_work); + } + spin_unlock(&ipi_lock); + continue; + } - __list_del_entry(&stack.dfs_link); + list_move_tail(&s->sched.dfs, &dfs); + } } - memset(&cache, 0, sizeof(cache)); - engine = node_to_request(node)->engine; - spin_lock(&engine->active.lock); - - /* Fifo and depth-first replacement ensure our deps execute before us */ - engine = sched_lock_engine(node, engine, &cache); - list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { - INIT_LIST_HEAD(&dep->dfs_link); - - node = dep->signaler; - engine = sched_lock_engine(node, engine, &cache); - lockdep_assert_held(&engine->active.lock); - - /* Recheck after acquiring the engine->timeline.lock */ - if (prio <= node->attr.priority || node_signaled(node)) - continue; + plist = i915_sched_lookup_priolist(engine, prio); - GEM_BUG_ON(node_to_request(node)->engine != engine); + /* Fifo and depth-first replacement ensure our deps execute first */ + list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) { + GEM_BUG_ON(rq->engine != engine); - WRITE_ONCE(node->attr.priority, prio); + INIT_LIST_HEAD(&rq->sched.dfs); + WRITE_ONCE(rq->sched.attr.priority, prio); /* * Once the request is ready, it will be placed into the @@ -323,32 +297,48 @@ static void __i915_schedule(struct i915_sched_node *node, int prio) * any preemption required, be dealt with upon submission. * See engine->submit_request() */ - if (list_empty(&node->link)) + if (!i915_request_is_ready(rq)) continue; - if (i915_request_in_priority_queue(node_to_request(node))) { - if (!cache.priolist) - cache.priolist = - i915_sched_lookup_priolist(engine, - prio); - list_move_tail(&node->link, cache.priolist); - } + if (i915_request_in_priority_queue(rq)) + list_move_tail(&rq->sched.link, plist); - /* Defer (tasklet) submission until after all of our updates. */ - kick_submission(engine, node_to_request(node), prio); + /* Defer (tasklet) submission until after all updates. */ + kick_submission(engine, rq, prio); } - - spin_unlock(&engine->active.lock); } void i915_request_set_priority(struct i915_request *rq, int prio) { - if (!intel_engine_has_scheduler(rq->engine)) + struct intel_engine_cs *engine = READ_ONCE(rq->engine); + unsigned long flags; + + if (!intel_engine_has_scheduler(engine)) return; - spin_lock_irq(&schedule_lock); - __i915_schedule(&rq->sched, prio); - spin_unlock_irq(&schedule_lock); + /* + * Virtual engines complicate acquiring the engine timeline lock, + * as their rq->engine pointer is not stable until under that + * engine lock. The simple ploy we use is to take the lock then + * check that the rq still belongs to the newly locked engine. + */ + spin_lock_irqsave(&engine->active.lock, flags); + while (engine != READ_ONCE(rq->engine)) { + spin_unlock(&engine->active.lock); + engine = READ_ONCE(rq->engine); + spin_lock(&engine->active.lock); + } + + if (i915_request_completed(rq)) + goto unlock; + + if (prio <= rq_prio(rq)) + goto unlock; + + __i915_request_set_priority(rq, prio); + +unlock: + spin_unlock_irqrestore(&engine->active.lock, flags); } void i915_sched_node_init(struct i915_sched_node *node) @@ -358,6 +348,7 @@ void i915_sched_node_init(struct i915_sched_node *node) INIT_LIST_HEAD(&node->signalers_list); INIT_LIST_HEAD(&node->waiters_list); INIT_LIST_HEAD(&node->link); + INIT_LIST_HEAD(&node->dfs); i915_sched_node_reinit(node); } @@ -396,7 +387,8 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node, spin_lock_irq(&signal->lock); if (!node_signaled(signal)) { - INIT_LIST_HEAD(&dep->dfs_link); + INIT_LIST_HEAD(&dep->ipi_link); + dep->ipi_priority = I915_PRIORITY_INVALID; dep->signaler = signal; dep->waiter = node; dep->flags = flags; @@ -505,6 +497,12 @@ void i915_sched_node_retire(struct i915_sched_node *node) GEM_BUG_ON(dep->signaler != node); + if (unlikely(!list_empty(&dep->ipi_link))) { + spin_lock(&ipi_lock); + list_del(&dep->ipi_link); + spin_unlock(&ipi_lock); + } + w = READ_ONCE(dep->waiter); if (w) { spin_lock_nested(&w->lock, SINGLE_DEPTH_NESTING); diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h index 3246430eb1c1..ce60577df2bf 100644 --- a/drivers/gpu/drm/i915/i915_scheduler_types.h +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h @@ -63,7 +63,8 @@ struct i915_sched_node { spinlock_t lock; /* protect the lists */ struct list_head signalers_list; /* those before us, we depend upon */ struct list_head waiters_list; /* those after us, they depend upon us */ - struct list_head link; + struct list_head link; /* guarded by engine->active.lock */ + struct list_head dfs; /* guarded by engine->active.lock */ struct i915_sched_attr attr; unsigned int flags; #define I915_SCHED_HAS_EXTERNAL_CHAIN BIT(0) @@ -75,11 +76,12 @@ struct i915_dependency { struct i915_sched_node *waiter; struct list_head signal_link; struct list_head wait_link; - struct list_head dfs_link; + struct list_head ipi_link; unsigned long flags; #define I915_DEPENDENCY_ALLOC BIT(0) #define I915_DEPENDENCY_EXTERNAL BIT(1) #define I915_DEPENDENCY_WEAK BIT(2) + int ipi_priority; }; #define for_each_waiter(p__, rq__) \ -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:45 +0100 Subject: [Intel-gfx] [PATCH 05/28] drm/i915/selftests: Trim execlists runtime In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-5-chris@chris-wilson.co.uk> Reduce the smoke depth by trimming the number of contexts, repetitions and wait times. This is in preparation for a less greedy scheduler that tries to be fair across contexts, resulting in a great many more context switches. A thousand context switches may be 50-100ms, causing us to timeout as the HW is not fast enough to complete the deep smoketests. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 66 ++++++-------------- drivers/gpu/drm/i915/selftests/igt_spinner.c | 4 +- 2 files changed, 21 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index e838e38a262c..f651bdf7f191 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -845,10 +845,11 @@ static int live_timeslice_preempt(void *arg) { struct intel_gt *gt = arg; struct drm_i915_gem_object *obj; + struct intel_engine_cs *engine; + enum intel_engine_id id; struct i915_vma *vma; void *vaddr; int err = 0; - int count; /* * If a request takes too long, we would like to give other users @@ -885,26 +886,21 @@ static int live_timeslice_preempt(void *arg) if (err) goto err_pin; - for_each_prime_number_from(count, 1, 16) { - struct intel_engine_cs *engine; - enum intel_engine_id id; - - for_each_engine(engine, gt, id) { - if (!intel_engine_has_preemption(engine)) - continue; + for_each_engine(engine, gt, id) { + if (!intel_engine_has_preemption(engine)) + continue; - memset(vaddr, 0, PAGE_SIZE); + memset(vaddr, 0, PAGE_SIZE); - engine_heartbeat_disable(engine); - err = slice_semaphore_queue(engine, vma, count); - engine_heartbeat_enable(engine); - if (err) - goto err_pin; + engine_heartbeat_disable(engine); + err = slice_semaphore_queue(engine, vma, 5); + engine_heartbeat_enable(engine); + if (err) + goto err_pin; - if (igt_flush_test(gt->i915)) { - err = -EIO; - goto err_pin; - } + if (igt_flush_test(gt->i915)) { + err = -EIO; + goto err_pin; } } @@ -1251,22 +1247,6 @@ static int live_timeslice_queue(void *arg) intel_engine_flush_submission(engine); } while (READ_ONCE(engine->execlists.pending[0])); - if (!READ_ONCE(engine->execlists.timer.expires) && - execlists_active(&engine->execlists) == rq && - !i915_request_completed(rq)) { - struct drm_printer p = - drm_info_printer(gt->i915->drm.dev); - - GEM_TRACE_ERR("%s: Failed to enable timeslicing!\n", - engine->name); - intel_engine_dump(engine, &p, - "%s\n", engine->name); - GEM_TRACE_DUMP(); - - memset(vaddr, 0xff, PAGE_SIZE); - err = -EINVAL; - } - /* Timeslice every jiffy, so within 2 we should signal */ if (i915_request_wait(rq, 0, slice_timeout(engine)) < 0) { struct drm_printer p = @@ -2671,16 +2651,8 @@ static int live_preempt_gang(void *arg) /* Submit each spinner at increasing priority */ engine->schedule(rq, &attr); - - if (prio < attr.priority) - break; - - if (prio <= I915_PRIORITY_MAX) - continue; - - if (__igt_timeout(end_time, NULL)) - break; - } while (1); + } while (prio <= I915_PRIORITY_MAX && + !__igt_timeout(end_time, NULL)); pr_debug("%s: Preempt chain of %d requests\n", engine->name, prio); @@ -3248,7 +3220,7 @@ static int smoke_crescendo_thread(void *arg) return err; count++; - } while (!__igt_timeout(end_time, NULL)); + } while (count < smoke->ncontext && !__igt_timeout(end_time, NULL)); smoke->count = count; return 0; @@ -3324,7 +3296,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags) count++; } - } while (!__igt_timeout(end_time, NULL)); + } while (count < smoke->ncontext && !__igt_timeout(end_time, NULL)); pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n", count, flags, @@ -3337,7 +3309,7 @@ static int live_preempt_smoke(void *arg) struct preempt_smoke smoke = { .gt = arg, .prng = I915_RND_STATE_INITIALIZER(i915_selftest.random_seed), - .ncontext = 1024, + .ncontext = 256, }; const unsigned int phase[] = { 0, BATCH }; struct igt_live_test t; diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c index 699bfe0328fb..ec0ecb4e4ca6 100644 --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c @@ -221,8 +221,8 @@ bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq) { return !(wait_for_us(i915_seqno_passed(hws_seqno(spin, rq), rq->fence.seqno), - 10) && + 100) && wait_for(i915_seqno_passed(hws_seqno(spin, rq), rq->fence.seqno), - 1000)); + 50)); } -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:42 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:42 +0100 Subject: [Intel-gfx] [PATCH 02/28] drm/i915/selftests: Make the hanging request non-preemptible In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-2-chris@chris-wilson.co.uk> In some of our hangtests, we try to reset an active engine while it is spinning inside the recursive spinner. However, we also try to flood the engine with requests that preempt the hang, and so should disable the preemption to be sure that we reset the right request. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 36 ++++++++++++++------ 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 4aa4cc917d8b..035f363fb0f8 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -203,12 +203,12 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = upper_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; memset(batch, 0, 1024); batch += 1024 / sizeof(*batch); - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; *batch++ = lower_32_bits(vma->node.start); *batch++ = upper_32_bits(vma->node.start); @@ -217,12 +217,12 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) *batch++ = 0; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; memset(batch, 0, 1024); batch += 1024 / sizeof(*batch); - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; *batch++ = MI_BATCH_BUFFER_START | 1 << 8; *batch++ = lower_32_bits(vma->node.start); } else if (INTEL_GEN(gt->i915) >= 4) { @@ -230,24 +230,24 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) *batch++ = 0; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; memset(batch, 0, 1024); batch += 1024 / sizeof(*batch); - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; *batch++ = MI_BATCH_BUFFER_START | 2 << 6; *batch++ = lower_32_bits(vma->node.start); } else { *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = rq->fence.seqno; - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; memset(batch, 0, 1024); batch += 1024 / sizeof(*batch); - *batch++ = MI_ARB_CHECK; + *batch++ = MI_NOOP; *batch++ = MI_BATCH_BUFFER_START | 2 << 6; *batch++ = lower_32_bits(vma->node.start); } @@ -866,13 +866,29 @@ static int __igt_reset_engines(struct intel_gt *gt, count++; if (rq) { + if (rq->fence.error != -EIO) { + pr_err("i915_reset_engine(%s:%s):" + " failed to reset request %llx:%lld\n", + engine->name, test_name, + rq->fence.context, + rq->fence.seqno); + i915_request_put(rq); + + GEM_TRACE_DUMP(); + intel_gt_set_wedged(gt); + err = -EIO; + break; + } + if (i915_request_wait(rq, 0, HZ / 5) < 0) { struct drm_printer p = drm_info_printer(gt->i915->drm.dev); pr_err("i915_reset_engine(%s:%s):" - " failed to complete request after reset\n", - engine->name, test_name); + " failed to complete request %llx:%lld after reset\n", + engine->name, test_name, + rq->fence.context, + rq->fence.seqno); intel_engine_dump(engine, &p, "%s\n", engine->name); i915_request_put(rq); -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:52 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:52 +0100 Subject: [Intel-gfx] [PATCH 12/28] drm/i915/gem: Build the reloc request first In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-12-chris@chris-wilson.co.uk> If we get interrupted in the middle of chaining up the relocation entries, we will fail to submit the relocation batch. However, we will report having already completed some of the relocations, and so the reloc.presumed_offset will no longer match the batch contents, causing confusion and invalid future batches. If we build the relocation request packet first, we can always emit as far as we get up in the relocation chain. Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 49 ++++++++++--------- .../i915/gem/selftests/i915_gem_execbuffer.c | 8 +-- 2 files changed, 30 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index e012857be129..83cea2ea7c61 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1002,11 +1002,27 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) return cache->gen > 5 ? 0 : I915_DISPATCH_SECURE; } -static int reloc_gpu_flush(struct reloc_cache *cache) +static int reloc_gpu_emit(struct reloc_cache *cache) { struct i915_request *rq = cache->rq; int err; + err = 0; + if (rq->engine->emit_init_breadcrumb) + err = rq->engine->emit_init_breadcrumb(rq); + if (!err) + err = rq->engine->emit_bb_start(rq, + rq->batch->node.start, + PAGE_SIZE, + reloc_bb_flags(cache)); + + return err; +} + +static void reloc_gpu_flush(struct reloc_cache *cache) +{ + struct i915_request *rq = cache->rq; + if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1018,21 +1034,8 @@ static int reloc_gpu_flush(struct reloc_cache *cache) i915_gem_object_unpin_map(obj); } - err = 0; - if (rq->engine->emit_init_breadcrumb) - err = rq->engine->emit_init_breadcrumb(rq); - if (!err) - err = rq->engine->emit_bb_start(rq, - rq->batch->node.start, - PAGE_SIZE, - reloc_bb_flags(cache)); - if (err) - i915_request_set_error_once(rq, err); - intel_gt_chipset_flush(rq->engine->gt); i915_request_add(rq); - - return err; } static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) @@ -1120,7 +1123,7 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) err = i915_vma_move_to_active(batch, rq, 0); i915_vma_unlock(batch); if (err) - goto skip_request; + goto err_request; rq->batch = batch; i915_vma_unpin(batch); @@ -1133,8 +1136,6 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) /* Return with batch mapping (cmd) still pinned */ goto out_pool; -skip_request: - i915_request_set_error_once(rq, err); err_request: i915_request_add(rq); err_unpin: @@ -1167,10 +1168,8 @@ static u32 *reloc_batch_grow(struct i915_execbuffer *eb, if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); + if (unlikely(err)) return ERR_PTR(err); - } } GEM_BUG_ON(cache->rq_size + len >= PAGE_SIZE / sizeof(u32)); @@ -1493,13 +1492,17 @@ static int reloc_gpu_alloc(struct i915_execbuffer *eb) static int reloc_gpu(struct i915_execbuffer *eb) { struct eb_vma *ev; - int flush, err; + int err; err = reloc_gpu_alloc(eb); if (err) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto out; + list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_reloc_vma(eb, ev, eb_reloc_entry); if (err < 0) @@ -1507,9 +1510,7 @@ static int reloc_gpu(struct i915_execbuffer *eb) } out: - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; + reloc_gpu_flush(&eb->reloc_cache); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 50fe22d87ae1..faed6480a792 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -40,6 +40,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -64,9 +68,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); - err = reloc_gpu_flush(&eb->reloc_cache); - if (err) - goto put_rq; + reloc_gpu_flush(&eb->reloc_cache); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:06 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:06 +0100 Subject: [Intel-gfx] [PATCH 26/28] drm/i915: Fair low-latency scheduling In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-26-chris@chris-wilson.co.uk> The first "scheduler" was a topographical sorting of requests into priority order. The execution order was deterministic, the earliest submitted, highest priority request would be executed first. Priority inherited ensured that inversions were kept at bay, and allowed us to dynamically boost priorities (e.g. for interactive pageflips). The minimalistic timeslicing scheme was an attempt to introduce fairness between long running requests, by evicting the active request at the end of a timeslice and moving it to the back of its priority queue (while ensuring that dependencies were kept in order). For short running requests from many clients of equal priority, the scheme is still very much FIFO submission ordering, and as unfair as before. To impose fairness, we need an external metric that ensures that clients are interpersed, we don't execute one long chain from client A before executing any of client B. This could be imposed by the clients by using a fences based on an external clock, that is they only submit work for a "frame" at frame-interval, instead of submitting as much work as they are able to. The standard SwapBuffers approach is akin to double bufferring, where as one frame is being executed, the next is being submitted, such that there is always a maximum of two frames per client in the pipeline. Even this scheme exhibits unfairness under load as a single client will execute two frames back to back before the next, and with enough clients, deadlines will be missed. The idea introduced by BFS/MuQSS is that fairness is introduced by metering with an external clock. Every request, when it becomes ready to execute is assigned a virtual deadline, and execution order is then determined by earliest deadline. Priority is used as a hint, rather than strict ordering, where high priority requests have earlier deadlines, but not necessarily earlier than outstanding work. Thus work is executed in order of 'readiness', with timeslicing to demote long running work. The Achille's heel of this scheduler is its strong preference for low-latency and favouring of new queues. Whereas it was easy to dominate the old scheduler by flooding it with many requests over a short period of time, the new scheduler can be dominated by a 'synchronous' client that waits for each of its requests to complete before submitting the next. As such a client has no history, it is always considered ready-to-run and receives an earlier deadline than the long running requests. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 1 + drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 24 -- drivers/gpu/drm/i915/gt/intel_lrc.c | 328 +++++++----------- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 5 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 43 ++- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- drivers/gpu/drm/i915/i915_priolist_types.h | 7 +- drivers/gpu/drm/i915/i915_request.h | 4 +- drivers/gpu/drm/i915/i915_scheduler.c | 322 ++++++++++++----- drivers/gpu/drm/i915/i915_scheduler.h | 22 +- drivers/gpu/drm/i915/i915_scheduler_types.h | 17 + .../drm/i915/selftests/i915_mock_selftests.h | 1 + drivers/gpu/drm/i915/selftests/i915_request.c | 1 + .../gpu/drm/i915/selftests/i915_scheduler.c | 49 +++ 16 files changed, 484 insertions(+), 362 deletions(-) create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index d79307d790da..b99b3332467d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -513,7 +513,6 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine) execlists->active = memset(execlists->inflight, 0, sizeof(execlists->inflight)); - execlists->queue_priority_hint = INT_MIN; execlists->queue = RB_ROOT_CACHED; } @@ -1188,14 +1187,15 @@ bool intel_engine_can_store_dword(struct intel_engine_cs *engine) } } -static int print_sched_attr(const struct i915_sched_attr *attr, - char *buf, int x, int len) +static int print_sched(const struct i915_sched_node *node, + char *buf, int x, int len) { - if (attr->priority == I915_PRIORITY_INVALID) + if (node->attr.priority == I915_PRIORITY_INVALID) return x; x += snprintf(buf + x, len - x, - " prio=%d", attr->priority); + " prio=%d, dl=%llu", + node->attr.priority, node->deadline); return x; } @@ -1208,7 +1208,7 @@ static void print_request(struct drm_printer *m, char buf[80] = ""; int x = 0; - x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf)); + x = print_sched(&rq->sched, buf, x, sizeof(buf)); drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n", prefix, diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index 5251860e952d..ba778c7b5d2b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -214,6 +214,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); idle_pulse(engine, rq); + rq->sched.deadline = 0; __i915_request_commit(rq); __i915_request_queue(rq, &attr); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c index d0a1078ef632..ac9c777a6592 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c @@ -188,6 +188,7 @@ static bool switch_to_kernel_context(struct intel_engine_cs *engine) i915_request_add_active_barriers(rq); /* Install ourselves as a preemption barrier */ + rq->sched.deadline = 0; rq->sched.attr.priority = I915_PRIORITY_BARRIER; if (likely(!__i915_request_commit(rq))) { /* engine should be idle! */ /* @@ -248,9 +249,6 @@ static int __engine_park(struct intel_wakeref *wf) intel_engine_park_heartbeat(engine); intel_engine_disarm_breadcrumbs(engine); - /* Must be reset upon idling, or we may miss the busy wakeup. */ - GEM_BUG_ON(engine->execlists.queue_priority_hint != INT_MIN); - if (engine->park) engine->park(engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 48e111f16dc5..a3c60038244c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -231,30 +231,6 @@ struct intel_engine_execlists { */ unsigned int port_mask; - /** - * @switch_priority_hint: Second context priority. - * - * We submit multiple contexts to the HW simultaneously and would - * like to occasionally switch between them to emulate timeslicing. - * To know when timeslicing is suitable, we track the priority of - * the context submitted second. - */ - int switch_priority_hint; - - /** - * @queue_priority_hint: Highest pending priority. - * - * When we add requests into the queue, or adjust the priority of - * executing requests, we compute the maximum priority of those - * pending requests. We can then use this value to determine if - * we need to preempt the executing requests to service the queue. - * However, since the we may have recorded the priority of an inflight - * request we wanted to preempt but since completed, at the time of - * dequeuing the priority hint may no longer may match the highest - * available request priority. - */ - int queue_priority_hint; - /** * @queue: queue of requests, in priority lists */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index f9c095c79874..0678dbb9b9fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -200,7 +200,7 @@ struct virtual_engine { */ struct ve_node { struct rb_node rb; - int prio; + u64 deadline; } nodes[I915_NUM_ENGINES]; /* @@ -411,12 +411,17 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb) static inline int rq_prio(const struct i915_request *rq) { - return READ_ONCE(rq->sched.attr.priority); + return rq->sched.attr.priority; } -static int effective_prio(const struct i915_request *rq) +static inline u64 rq_deadline(const struct i915_request *rq) { - int prio = rq_prio(rq); + return rq->sched.deadline; +} + +static u64 effective_deadline(const struct i915_request *rq) +{ + u64 deadline = rq_deadline(rq); /* * If this request is special and must not be interrupted at any @@ -427,27 +432,27 @@ static int effective_prio(const struct i915_request *rq) * nopreempt for as long as desired). */ if (i915_request_has_nopreempt(rq)) - prio = I915_PRIORITY_UNPREEMPTABLE; + deadline = 0; - return prio; + return deadline; } -static int queue_prio(const struct intel_engine_execlists *execlists) +static u64 queue_deadline(const struct intel_engine_execlists *execlists) { struct rb_node *rb; rb = rb_first_cached(&execlists->queue); if (!rb) - return INT_MIN; + return I915_DEADLINE_NEVER; - return to_priolist(rb)->priority; + return to_priolist(rb)->deadline; } static inline bool need_preempt(const struct intel_engine_cs *engine, const struct i915_request *rq, struct virtual_engine *ve) { - int last_prio; + u64 last_deadline; if (!intel_engine_has_semaphores(engine)) return false; @@ -470,16 +475,14 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, * priority level: the task that is running should remain running * to preserve FIFO ordering of dependencies. */ - last_prio = max(effective_prio(rq), I915_PRIORITY_NORMAL - 1); - if (engine->execlists.queue_priority_hint <= last_prio) - return false; + last_deadline = effective_deadline(rq); /* * Check against the first request in ELSP[1], it will, thanks to the * power of PI, be the highest priority of that context. */ if (!list_is_last(&rq->sched.link, &engine->active.requests) && - rq_prio(list_next_entry(rq, sched.link)) > last_prio) + rq_deadline(list_next_entry(rq, sched.link)) < last_deadline) return true; if (ve) { @@ -491,7 +494,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, rcu_read_lock(); next = READ_ONCE(ve->request); if (next) - preempt = rq_prio(next) > last_prio; + preempt = rq_deadline(next) < last_deadline; rcu_read_unlock(); } @@ -509,7 +512,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, * ELSP[0] or ELSP[1] as, thanks again to PI, if it was the same * context, it's priority would not exceed ELSP[0] aka last_prio. */ - return queue_prio(&engine->execlists) > last_prio; + return queue_deadline(&engine->execlists) < last_deadline; } __maybe_unused static inline bool @@ -526,7 +529,7 @@ assert_priority_queue(const struct i915_request *prev, if (i915_request_is_active(prev)) return true; - return rq_prio(prev) >= rq_prio(next); + return rq_deadline(prev) <= rq_deadline(next); } /* @@ -1096,22 +1099,30 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) { struct i915_request *rq, *rn, *active = NULL; struct list_head *uninitialized_var(pl); - int prio = I915_PRIORITY_INVALID; + u64 deadline = I915_DEADLINE_NEVER; lockdep_assert_held(&engine->active.lock); list_for_each_entry_safe_reverse(rq, rn, &engine->active.requests, sched.link) { - if (i915_request_completed(rq)) + if (i915_request_completed(rq)) { + list_del_init(&rq->sched.link); continue; /* XXX */ + } __i915_request_unsubmit(rq); - GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); - if (rq_prio(rq) != prio) { - prio = rq_prio(rq); - pl = i915_sched_lookup_priolist(engine, prio); + if (i915_request_started(rq)) { + u64 deadline = + i915_scheduler_next_virtual_deadline(rq_prio(rq)); + rq->sched.deadline = min(rq_deadline(rq), deadline); + } + + if (rq_deadline(rq) != deadline) { + deadline = rq_deadline(rq); + pl = i915_sched_lookup_priolist(engine, deadline); + } GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); @@ -1546,14 +1557,14 @@ dump_port(char *buf, int buflen, const char *prefix, struct i915_request *rq) if (!rq) return ""; - snprintf(buf, buflen, "%sccid:%x %llx:%lld%s prio %d", + snprintf(buf, buflen, "%sccid:%x %llx:%lld%s dl %llu", prefix, rq->context->lrc.ccid, rq->fence.context, rq->fence.seqno, i915_request_completed(rq) ? "!" : i915_request_started(rq) ? "*" : "", - rq_prio(rq)); + rq_deadline(rq)); return buf; } @@ -1863,7 +1874,9 @@ static void virtual_xfer_breadcrumbs(struct virtual_engine *ve) intel_engine_transfer_stale_breadcrumbs(ve->siblings[0], &ve->context); } -static void defer_request(struct i915_request *rq, struct list_head * const pl) +static void defer_request(struct i915_request *rq, + struct list_head * const pl, + u64 deadline) { LIST_HEAD(list); @@ -1878,6 +1891,7 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl) struct i915_dependency *p; GEM_BUG_ON(i915_request_is_active(rq)); + rq->sched.deadline = deadline; list_move_tail(&rq->sched.link, pl); for_each_waiter(p, rq) { @@ -1900,10 +1914,9 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl) if (!i915_request_is_ready(w)) continue; - if (rq_prio(w) < rq_prio(rq)) + if (rq_deadline(w) > deadline) continue; - GEM_BUG_ON(rq_prio(w) > rq_prio(rq)); list_move_tail(&w->sched.link, &list); } @@ -1914,46 +1927,21 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl) static void defer_active(struct intel_engine_cs *engine) { struct i915_request *rq; + u64 deadline; rq = __unwind_incomplete_requests(engine); if (!rq) return; - defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq))); -} - -static bool -need_timeslice(const struct intel_engine_cs *engine, - const struct i915_request *rq, - struct virtual_engine *ve) -{ - int hint; - - if (!intel_engine_has_timeslices(engine)) - return false; - - hint = engine->execlists.queue_priority_hint; - - if (ve) { - const struct intel_engine_cs *inflight = - intel_context_inflight(&ve->context); - - if (!inflight || inflight == engine) { - struct i915_request *next; - - rcu_read_lock(); - next = READ_ONCE(ve->request); - if (next) - hint = max(hint, rq_prio(next)); - rcu_read_unlock(); - } - } - - if (!list_is_last(&rq->sched.link, &engine->active.requests)) - hint = max(hint, rq_prio(list_next_entry(rq, sched.link))); + deadline = max(rq_deadline(rq), + i915_scheduler_next_virtual_deadline(rq_prio(rq))); + ENGINE_TRACE(engine, "defer %llx:%lld, dl:%llu -> %llu\n", + rq->fence.context, rq->fence.seqno, + rq_deadline(rq), deadline); - GEM_BUG_ON(hint >= I915_PRIORITY_UNPREEMPTABLE); - return hint >= effective_prio(rq); + defer_request(rq, + i915_sched_lookup_priolist(engine, deadline), + deadline); } static bool @@ -1976,42 +1964,56 @@ timeslice_yield(const struct intel_engine_execlists *el, } static bool -timeslice_expired(const struct intel_engine_execlists *el, - const struct i915_request *rq) +timeslice_expired(struct intel_engine_cs *engine, const struct i915_request *rq) { - return timer_expired(&el->timer) || timeslice_yield(el, rq); -} + const struct intel_engine_execlists *el = &engine->execlists; -static int -switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq) -{ - if (list_is_last(&rq->sched.link, &engine->active.requests)) - return engine->execlists.queue_priority_hint; + if (!intel_engine_has_timeslices(engine)) + return false; + + if (i915_request_has_nopreempt(rq) && i915_request_started(rq)) + return false; - return rq_prio(list_next_entry(rq, sched.link)); + return timer_expired(&el->timer) || timeslice_yield(el, rq); } -static inline unsigned long -timeslice(const struct intel_engine_cs *engine) +static unsigned long timeslice(const struct intel_engine_cs *engine) { return READ_ONCE(engine->props.timeslice_duration_ms); } -static unsigned long active_timeslice(const struct intel_engine_cs *engine) +static bool needs_timeslice(const struct intel_engine_cs *engine, + const struct i915_request *rq) { - const struct intel_engine_execlists *execlists = &engine->execlists; - const struct i915_request *rq = *execlists->active; - + /* If not currently active, or about to switch, wait for next event */ if (!rq || i915_request_completed(rq)) - return 0; + return false; + + /* We do not need to start the timeslice until after the ACK */ + if (READ_ONCE(engine->execlists.pending[0])) + return false; + + /* If ELSP[1] is occupied, always check to see if worth slicing */ + if (!list_is_last(&rq->sched.link, &engine->active.requests)) + return true; + + /* Otherwise, ELSP[0] is by itself, but may be waiting in the queue */ + if (rb_first_cached(&engine->execlists.queue)) + return true; - if (READ_ONCE(execlists->switch_priority_hint) < effective_prio(rq)) + return rb_first_cached(&engine->execlists.virtual); +} + +static unsigned long active_timeslice(const struct intel_engine_cs *engine) +{ + /* Disable the timer if there is nothing to switch to */ + if (!needs_timeslice(engine, execlists_active(&engine->execlists))) return 0; return timeslice(engine); } -static void set_timeslice(struct intel_engine_cs *engine) +static void start_timeslice(struct intel_engine_cs *engine) { unsigned long duration; @@ -2024,29 +2026,6 @@ static void set_timeslice(struct intel_engine_cs *engine) set_timer_ms(&engine->execlists.timer, duration); } -static void start_timeslice(struct intel_engine_cs *engine, int prio) -{ - struct intel_engine_execlists *execlists = &engine->execlists; - unsigned long duration; - - if (!intel_engine_has_timeslices(engine)) - return; - - WRITE_ONCE(execlists->switch_priority_hint, prio); - if (prio == INT_MIN) - return; - - if (timer_pending(&execlists->timer)) - return; - - duration = timeslice(engine); - ENGINE_TRACE(engine, - "start timeslicing, prio:%d, interval:%lu", - prio, duration); - - set_timer_ms(&execlists->timer, duration); -} - static void record_preemption(struct intel_engine_execlists *execlists) { (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++); @@ -2138,11 +2117,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (need_preempt(engine, last, ve)) { ENGINE_TRACE(engine, - "preempting last=%llx:%lld, prio=%d, hint=%d\n", + "preempting last=%llx:%llu, dl=%llu\n", last->fence.context, last->fence.seqno, - last->sched.attr.priority, - execlists->queue_priority_hint); + rq_deadline(last)); record_preemption(execlists); /* @@ -2162,14 +2140,13 @@ static void execlists_dequeue(struct intel_engine_cs *engine) __unwind_incomplete_requests(engine); last = NULL; - } else if (need_timeslice(engine, last, ve) && - timeslice_expired(execlists, last)) { + } else if (timeslice_expired(engine, last)) { ENGINE_TRACE(engine, - "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n", - last->fence.context, - last->fence.seqno, - last->sched.attr.priority, - execlists->queue_priority_hint, + "expired:%s last=%llx:%llu, deadline=%llu, now=%llu, yield?=%s\n", + yesno(timer_expired(&execlists->timer)), + last->fence.context, last->fence.seqno, + rq_deadline(last), + i915_sched_to_ticks(ktime_get()), yesno(timeslice_yield(execlists, last))); ring_set_paused(engine, 1); @@ -2205,7 +2182,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ - start_timeslice(engine, queue_prio(execlists)); return; } } @@ -2224,7 +2200,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) GEM_BUG_ON(rq->engine != &ve->base); GEM_BUG_ON(rq->context != &ve->context); - if (unlikely(rq_prio(rq) < queue_prio(execlists))) { + if (unlikely(rq_deadline(rq) > queue_deadline(execlists))) { spin_unlock(&ve->base.active.lock); break; } @@ -2233,7 +2209,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); - start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2245,10 +2220,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) i915_request_started(rq) ? "*" : "", yesno(engine != ve->siblings[0])); - WRITE_ONCE(ve->request, NULL); - WRITE_ONCE(ve->base.execlists.queue_priority_hint, - INT_MIN); rb = &ve->nodes[engine->id].rb; rb_erase_cached(rb, &execlists->virtual); @@ -2391,28 +2363,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } done: - /* - * Here be a bit of magic! Or sleight-of-hand, whichever you prefer. - * - * We choose the priority hint such that if we add a request of greater - * priority than this, we kick the submission tasklet to decide on - * the right order of submitting the requests to hardware. We must - * also be prepared to reorder requests as they are in-flight on the - * HW. We derive the priority hint then as the first "hole" in - * the HW submission ports and if there are no available slots, - * the priority of the lowest executing request, i.e. last. - * - * When we do receive a higher priority request ready to run from the - * user, see queue_request(), the priority hint is bumped to that - * request triggering preemption on the next dequeue (or subsequent - * interrupt for secondary ports). - */ - execlists->queue_priority_hint = queue_prio(execlists); - if (submit) { *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); /* * Skip if we ended up with exactly the same set of requests, @@ -2432,7 +2384,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) set_preempt_timeout(engine, *active); execlists_submit_ports(engine); } else { - start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); } @@ -2675,7 +2626,6 @@ static void process_csb(struct intel_engine_cs *engine) } while (head != tail); execlists->csb_head = head; - set_timeslice(engine); /* * Gen11 has proven to fail wrt global observation point between @@ -2824,9 +2774,10 @@ static bool hold_request(const struct i915_request *rq) return result; } -static void __execlists_unhold(struct i915_request *rq) +static bool __execlists_unhold(struct i915_request *rq) { LIST_HEAD(list); + bool submit = false; do { struct i915_dependency *p; @@ -2837,10 +2788,7 @@ static void __execlists_unhold(struct i915_request *rq) GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); i915_request_clear_hold(rq); - list_move_tail(&rq->sched.link, - i915_sched_lookup_priolist(rq->engine, - rq_prio(rq))); - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + submit |= intel_engine_queue_request(rq->engine, rq); /* Also release any children on this engine that are ready */ for_each_waiter(p, rq) { @@ -2869,6 +2817,8 @@ static void __execlists_unhold(struct i915_request *rq) rq = list_first_entry_or_null(&list, typeof(*rq), sched.link); } while (rq); + + return submit; } static void execlists_unhold(struct intel_engine_cs *engine, @@ -2880,12 +2830,8 @@ static void execlists_unhold(struct intel_engine_cs *engine, * Move this request back to the priority queue, and all of its * children and grandchildren that were suspended along with it. */ - __execlists_unhold(rq); - - if (rq_prio(rq) > engine->execlists.queue_priority_hint) { - engine->execlists.queue_priority_hint = rq_prio(rq); + if (__execlists_unhold(rq)) tasklet_hi_schedule(&engine->execlists.tasklet); - } spin_unlock_irq(&engine->active.lock); } @@ -3127,6 +3073,8 @@ static void execlists_submission_tasklet(unsigned long data) if (unlikely(timeout && preempt_timeout(engine))) execlists_reset(engine, "preemption time out"); } + + start_timeslice(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3148,15 +3096,6 @@ static void execlists_preempt(struct timer_list *timer) execlists_kick(timer, preempt); } -static void queue_request(struct intel_engine_cs *engine, - struct i915_request *rq) -{ - GEM_BUG_ON(!list_empty(&rq->sched.link)); - list_add_tail(&rq->sched.link, - i915_sched_lookup_priolist(engine, rq_prio(rq))); - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); -} - static void __submit_queue_imm(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; @@ -3167,18 +3106,6 @@ static void __submit_queue_imm(struct intel_engine_cs *engine) __execlists_submission_tasklet(engine); } -static void submit_queue(struct intel_engine_cs *engine, - const struct i915_request *rq) -{ - struct intel_engine_execlists *execlists = &engine->execlists; - - if (rq_prio(rq) <= execlists->queue_priority_hint) - return; - - execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); -} - static bool ancestor_on_hold(const struct intel_engine_cs *engine, const struct i915_request *rq) { @@ -3213,12 +3140,9 @@ static void execlists_submit_request(struct i915_request *request) list_add_tail(&request->sched.link, &engine->active.hold); i915_request_set_hold(request); } else { - queue_request(engine, request); - - GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - GEM_BUG_ON(list_empty(&request->sched.link)); - - submit_queue(engine, request); + if (intel_engine_queue_request(engine, request)) + __submit_queue_imm(engine); + start_timeslice(engine); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4273,10 +4197,6 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled) static void nop_submission_tasklet(unsigned long data) { - struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - - /* The driver is wedged; don't process any more events. */ - WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN); } static void execlists_reset_cancel(struct intel_engine_cs *engine) @@ -4322,6 +4242,7 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) rb_erase_cached(&p->node, &execlists->queue); i915_priolist_free(p); } + GEM_BUG_ON(!RB_EMPTY_ROOT(&execlists->queue.rb_root)); /* On-hold requests will be flushed to timeline upon their release */ list_for_each_entry(rq, &engine->active.hold, sched.link) @@ -4343,17 +4264,12 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) rq->engine = engine; __i915_request_submit(rq); i915_request_put(rq); - - ve->base.execlists.queue_priority_hint = INT_MIN; } spin_unlock(&ve->base.active.lock); } /* Remaining _unready_ requests will be nop'ed when submitted */ - execlists->queue_priority_hint = INT_MIN; - execlists->queue = RB_ROOT_CACHED; - GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet)); execlists->tasklet.func = nop_submission_tasklet; @@ -5449,7 +5365,8 @@ static const struct intel_context_ops virtual_context_ops = { .destroy = virtual_context_destroy, }; -static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve) +static intel_engine_mask_t +virtual_submission_mask(struct virtual_engine *ve, u64 *deadline) { struct i915_request *rq; intel_engine_mask_t mask; @@ -5466,9 +5383,11 @@ static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve) mask = ve->siblings[0]->mask; } - ENGINE_TRACE(&ve->base, "rq=%llx:%lld, mask=%x, prio=%d\n", + *deadline = rq_deadline(rq); + + ENGINE_TRACE(&ve->base, "rq=%llx:%llu, mask=%x, dl=%llu\n", rq->fence.context, rq->fence.seqno, - mask, ve->base.execlists.queue_priority_hint); + mask, *deadline); return mask; } @@ -5476,12 +5395,12 @@ static intel_engine_mask_t virtual_submission_mask(struct virtual_engine *ve) static void virtual_submission_tasklet(unsigned long data) { struct virtual_engine * const ve = (struct virtual_engine *)data; - const int prio = READ_ONCE(ve->base.execlists.queue_priority_hint); intel_engine_mask_t mask; + u64 deadline; unsigned int n; rcu_read_lock(); - mask = virtual_submission_mask(ve); + mask = virtual_submission_mask(ve, &deadline); rcu_read_unlock(); if (unlikely(!mask)) return; @@ -5514,7 +5433,8 @@ static void virtual_submission_tasklet(unsigned long data) */ first = rb_first_cached(&sibling->execlists.virtual) == &node->rb; - if (prio == node->prio || (prio > node->prio && first)) + if (deadline == node->deadline || + (deadline < node->deadline && first)) goto submit_engine; rb_erase_cached(&node->rb, &sibling->execlists.virtual); @@ -5528,7 +5448,7 @@ static void virtual_submission_tasklet(unsigned long data) rb = *parent; other = rb_entry(rb, typeof(*other), rb); - if (prio > other->prio) { + if (deadline < other->deadline) { parent = &rb->rb_left; } else { parent = &rb->rb_right; @@ -5543,8 +5463,8 @@ static void virtual_submission_tasklet(unsigned long data) submit_engine: GEM_BUG_ON(RB_EMPTY_NODE(&node->rb)); - node->prio = prio; - if (first && prio > sibling->execlists.queue_priority_hint) + node->deadline = deadline; + if (first) tasklet_hi_schedule(&sibling->execlists.tasklet); unlock_engine: @@ -5578,11 +5498,11 @@ static void virtual_submit_request(struct i915_request *rq) if (i915_request_completed(rq)) { __i915_request_submit(rq); - - ve->base.execlists.queue_priority_hint = INT_MIN; ve->request = NULL; } else { - ve->base.execlists.queue_priority_hint = rq_prio(rq); + rq->sched.deadline = + min(rq->sched.deadline, + i915_scheduler_next_virtual_deadline(rq_prio(rq))); ve->request = i915_request_get(rq); GEM_BUG_ON(!list_empty(virtual_queue(ve))); @@ -5686,7 +5606,6 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings, ve->base.bond_execute = virtual_bond_execute; INIT_LIST_HEAD(virtual_queue(ve)); - ve->base.execlists.queue_priority_hint = INT_MIN; tasklet_init(&ve->base.execlists.tasklet, virtual_submission_tasklet, (unsigned long)ve); @@ -5873,13 +5792,6 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine, show_request(m, last, "\t\tE "); } - if (execlists->switch_priority_hint != INT_MIN) - drm_printf(m, "\t\tSwitch priority hint: %d\n", - READ_ONCE(execlists->switch_priority_hint)); - if (execlists->queue_priority_hint != INT_MIN) - drm_printf(m, "\t\tQueue priority hint: %d\n", - READ_ONCE(execlists->queue_priority_hint)); - last = NULL; count = 0; for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index afa4f88035ac..01fca8acd4c4 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -879,7 +879,10 @@ static int __igt_reset_engines(struct intel_gt *gt, break; } - if (i915_request_wait(rq, 0, HZ / 5) < 0) { + /* With deadlines, no strict priority */ + i915_request_set_deadline(rq, 0); + + if (i915_request_wait(rq, 0, HZ / 2) < 0) { struct drm_printer p = drm_info_printer(gt->i915->drm.dev); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 052dcc59fcc5..b18276cf30ed 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -85,6 +85,9 @@ static int wait_for_submit(struct intel_engine_cs *engine, struct i915_request *rq, unsigned long timeout) { + /* Ignore our own attempts to suppress excess tasklets */ + tasklet_hi_schedule(&engine->execlists.tasklet); + timeout += jiffies; do { bool done = time_after(jiffies, timeout); @@ -754,7 +757,7 @@ semaphore_queue(struct intel_engine_cs *engine, struct i915_vma *vma, int idx) static int release_queue(struct intel_engine_cs *engine, struct i915_vma *vma, - int idx, int prio) + int idx, u64 deadline) { struct i915_request *rq; u32 *cs; @@ -779,10 +782,7 @@ release_queue(struct intel_engine_cs *engine, i915_request_get(rq); i915_request_add(rq); - local_bh_disable(); - i915_request_set_priority(rq, prio); - local_bh_enable(); /* kick tasklet */ - + i915_request_set_deadline(rq, deadline); i915_request_put(rq); return 0; @@ -796,6 +796,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer, struct intel_engine_cs *engine; struct i915_request *head; enum intel_engine_id id; + long timeout; int err, i, n = 0; head = semaphore_queue(outer, vma, n++); @@ -816,12 +817,16 @@ slice_semaphore_queue(struct intel_engine_cs *outer, } } - err = release_queue(outer, vma, n, I915_PRIORITY_BARRIER); + err = release_queue(outer, vma, n, 0); if (err) goto out; - if (i915_request_wait(head, 0, - 2 * RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3)) < 0) { + /* Expected number of pessimal slices required */ + timeout = RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3); + timeout *= 4; /* safety factor, including bucketing */ + timeout += HZ / 2; /* and include the request completion */ + + if (i915_request_wait(head, 0, timeout) < 0) { pr_err("Failed to slice along semaphore chain of length (%d, %d)!\n", count, n); GEM_TRACE_DUMP(); @@ -926,6 +931,8 @@ create_rewinder(struct intel_context *ce, err = i915_request_await_dma_fence(rq, &wait->fence); if (err) goto err; + + i915_request_set_deadline(rq, rq_deadline(wait)); } cs = intel_ring_begin(rq, 14); @@ -1200,7 +1207,7 @@ static int live_timeslice_queue(void *arg) err = PTR_ERR(rq); goto err_heartbeat; } - i915_request_set_priority(rq, I915_PRIORITY_MAX); + i915_request_set_deadline(rq, 0); err = wait_for_submit(engine, rq, HZ / 2); if (err) { pr_err("%s: Timed out trying to submit semaphores\n", @@ -1223,10 +1230,9 @@ static int live_timeslice_queue(void *arg) } GEM_BUG_ON(i915_request_completed(rq)); - GEM_BUG_ON(execlists_active(&engine->execlists) != rq); /* Queue: semaphore signal, matching priority as semaphore */ - err = release_queue(engine, vma, 1, effective_prio(rq)); + err = release_queue(engine, vma, 1, effective_deadline(rq)); if (err) goto err_rq; @@ -1326,7 +1332,7 @@ static int live_timeslice_nopreempt(void *arg) ce = intel_context_create(engine); if (IS_ERR(ce)) { - err = PTR_ERR(rq); + err = PTR_ERR(ce); goto out_spin; } @@ -1337,6 +1343,7 @@ static int live_timeslice_nopreempt(void *arg) goto out_spin; } + rq->sched.deadline = 0; rq->sched.attr.priority = I915_PRIORITY_BARRIER; i915_request_get(rq); i915_request_add(rq); @@ -1709,6 +1716,7 @@ static int live_late_preempt(void *arg) /* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */ ctx_lo->sched.priority = 1; + ctx_hi->sched.priority = I915_PRIORITY_MIN; for_each_engine(engine, gt, id) { struct igt_live_test t; @@ -2648,6 +2656,9 @@ static int live_preempt_gang(void *arg) struct i915_request *n = list_next_entry(rq, client_link); + /* With deadlines, no strict priority ordering */ + i915_request_set_deadline(rq, 0); + if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0) { struct drm_printer p = drm_info_printer(engine->i915->drm.dev); @@ -2869,7 +2880,7 @@ static int preempt_user(struct intel_engine_cs *engine, i915_request_get(rq); i915_request_add(rq); - i915_request_set_priority(rq, I915_PRIORITY_MAX); + i915_request_set_deadline(rq, 0); if (i915_request_wait(rq, 0, HZ / 2) < 0) err = -ETIME; @@ -4402,6 +4413,7 @@ static int emit_semaphore_signal(struct intel_context *ce, void *slot) intel_ring_advance(rq, cs); + rq->sched.deadline = 0; rq->sched.attr.priority = I915_PRIORITY_BARRIER; i915_request_add(rq); return 0; @@ -4911,6 +4923,10 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine, err = emit_semaphore_signal(engine->kernel_context, slot); if (err) goto err_rq; + + err = wait_for_submit(engine, rq, HZ / 2); + if (err) + goto err_rq; } else { slot[0] = 1; wmb(); @@ -5468,6 +5484,7 @@ static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema) intel_ring_advance(rq, cs); + rq->sched.deadline = 0; rq->sched.attr.priority = I915_PRIORITY_BARRIER; err_rq: i915_request_add(rq); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 0c42e8b0c211..6da465c7c4f5 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -333,8 +333,6 @@ static void __guc_dequeue(struct intel_engine_cs *engine) i915_priolist_free(p); } done: - execlists->queue_priority_hint = - rb ? to_priolist(rb)->priority : INT_MIN; if (submit) { *port = schedule_in(last, port - execlists->inflight); *++port = NULL; @@ -473,12 +471,10 @@ static void guc_reset_cancel(struct intel_engine_cs *engine) rb_erase_cached(&p->node, &execlists->queue); i915_priolist_free(p); } + GEM_BUG_ON(!RB_EMPTY_ROOT(&execlists->queue.rb_root)); /* Remaining _unready_ requests will be nop'ed when submitted */ - execlists->queue_priority_hint = INT_MIN; - execlists->queue = RB_ROOT_CACHED; - spin_unlock_irqrestore(&engine->active.lock, flags); } diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h index bc2fa84f98a8..43a0ac45295f 100644 --- a/drivers/gpu/drm/i915/i915_priolist_types.h +++ b/drivers/gpu/drm/i915/i915_priolist_types.h @@ -22,6 +22,8 @@ enum { /* Interactive workload, scheduled for immediate pageflipping */ I915_PRIORITY_DISPLAY, + + __I915_PRIORITY_KERNEL__ }; /* Smallest priority value that cannot be bumped. */ @@ -35,13 +37,12 @@ enum { * i.e. nothing can have higher priority and force us to usurp the * active request. */ -#define I915_PRIORITY_UNPREEMPTABLE INT_MAX -#define I915_PRIORITY_BARRIER (I915_PRIORITY_UNPREEMPTABLE - 1) +#define I915_PRIORITY_BARRIER INT_MAX struct i915_priolist { struct list_head requests; struct rb_node node; - int priority; + u64 deadline; }; #endif /* _I915_PRIOLIST_TYPES_H_ */ diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index 118ab6650d1f..23594e712292 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -561,7 +561,7 @@ static inline void i915_request_clear_hold(struct i915_request *rq) } static inline struct intel_timeline * -i915_request_timeline(struct i915_request *rq) +i915_request_timeline(const struct i915_request *rq) { /* Valid only while the request is being constructed (or retired). */ return rcu_dereference_protected(rq->timeline, @@ -576,7 +576,7 @@ i915_request_gem_context(struct i915_request *rq) } static inline struct intel_timeline * -i915_request_active_timeline(struct i915_request *rq) +i915_request_active_timeline(const struct i915_request *rq) { /* * When in use during submission, we are protected by a guarantee that diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 4c189b81cc62..30bcb6f9d99f 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -20,6 +20,11 @@ static struct i915_global_scheduler { static DEFINE_SPINLOCK(ipi_lock); static LIST_HEAD(ipi_list); +static inline u64 rq_deadline(const struct i915_request *rq) +{ + return READ_ONCE(rq->sched.deadline); +} + static inline int rq_prio(const struct i915_request *rq) { return READ_ONCE(rq->sched.attr.priority); @@ -32,6 +37,7 @@ static void ipi_schedule(struct irq_work *wrk) struct i915_dependency *p; struct i915_request *rq; unsigned long flags; + u64 deadline; int prio; spin_lock_irqsave(&ipi_lock, flags); @@ -40,7 +46,10 @@ static void ipi_schedule(struct irq_work *wrk) rq = container_of(p->signaler, typeof(*rq), sched); list_del_init(&p->ipi_link); + deadline = p->ipi_deadline; prio = p->ipi_priority; + + p->ipi_deadline = I915_DEADLINE_NEVER; p->ipi_priority = I915_PRIORITY_INVALID; } spin_unlock_irqrestore(&ipi_lock, flags); @@ -52,6 +61,8 @@ static void ipi_schedule(struct irq_work *wrk) if (prio > rq_prio(rq)) i915_request_set_priority(rq, prio); + if (deadline < rq_deadline(rq)) + i915_request_set_deadline(rq, deadline); } while (1); rcu_read_unlock(); } @@ -79,28 +90,8 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb) return rb_entry(rb, struct i915_priolist, node); } -static void assert_priolists(struct intel_engine_execlists * const execlists) -{ - struct rb_node *rb; - long last_prio; - - if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) - return; - - GEM_BUG_ON(rb_first_cached(&execlists->queue) != - rb_first(&execlists->queue.rb_root)); - - last_prio = INT_MAX; - for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { - const struct i915_priolist *p = to_priolist(rb); - - GEM_BUG_ON(p->priority > last_prio); - last_prio = p->priority; - } -} - struct list_head * -i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) +i915_sched_lookup_priolist(struct intel_engine_cs *engine, u64 deadline) { struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_priolist *p; @@ -108,10 +99,9 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) bool first = true; lockdep_assert_held(&engine->active.lock); - assert_priolists(execlists); if (unlikely(execlists->no_priolist)) - prio = I915_PRIORITY_NORMAL; + deadline = 0; find_priolist: /* most positive priority is scheduled first, equal priorities fifo */ @@ -120,9 +110,9 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) while (*parent) { rb = *parent; p = to_priolist(rb); - if (prio > p->priority) { + if (deadline < p->deadline) { parent = &rb->rb_left; - } else if (prio < p->priority) { + } else if (deadline > p->deadline) { parent = &rb->rb_right; first = false; } else { @@ -130,13 +120,13 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) } } - if (prio == I915_PRIORITY_NORMAL) { + if (!deadline) { p = &execlists->default_priolist; } else { p = kmem_cache_alloc(global.slab_priorities, GFP_ATOMIC); /* Convert an allocation failure to a priority bump */ if (unlikely(!p)) { - prio = I915_PRIORITY_NORMAL; /* recurses just once */ + deadline = 0; /* recurses just once */ /* To maintain ordering with all rendering, after an * allocation failure we have to disable all scheduling. @@ -151,7 +141,7 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) } } - p->priority = prio; + p->deadline = deadline; INIT_LIST_HEAD(&p->requests); rb_link_node(&p->node, rb, parent); @@ -160,70 +150,221 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) return &p->requests; } -void __i915_priolist_free(struct i915_priolist *p) +void i915_priolist_free(struct i915_priolist *p) +{ + if (p->deadline) + kmem_cache_free(global.slab_priorities, p); +} + +static bool kick_submission(const struct intel_engine_cs *engine, u64 deadline) { - kmem_cache_free(global.slab_priorities, p); + const struct i915_request *inflight; + bool kick = true; + + rcu_read_lock(); + inflight = execlists_active(&engine->execlists); + if (inflight) + kick = deadline < rq_deadline(inflight); + rcu_read_unlock(); + + return kick; +} + +static bool __i915_request_set_deadline(struct i915_request *rq, u64 deadline) +{ + struct intel_engine_cs *engine = rq->engine; + struct i915_request *rn; + struct list_head *plist; + LIST_HEAD(dfs); + + lockdep_assert_held(&engine->active.lock); + list_add(&rq->sched.dfs, &dfs); + + list_for_each_entry(rq, &dfs, sched.dfs) { + struct i915_dependency *p; + + GEM_BUG_ON(rq->engine != engine); + + for_each_signaler(p, rq) { + struct i915_request *s = + container_of(p->signaler, typeof(*s), sched); + + GEM_BUG_ON(s == rq); + + if (rq_deadline(s) <= deadline) + continue; + + if (i915_request_completed(s)) + continue; + + if (s->engine != rq->engine) { + spin_lock(&ipi_lock); + if (deadline < p->ipi_deadline) { + p->ipi_deadline = deadline; + list_move(&p->ipi_link, &ipi_list); + irq_work_queue(&ipi_work); + } + spin_unlock(&ipi_lock); + continue; + } + + list_move_tail(&s->sched.dfs, &dfs); + } + } + + plist = i915_sched_lookup_priolist(engine, deadline); + + /* Fifo and depth-first replacement ensure our deps execute first */ + list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) { + GEM_BUG_ON(rq->engine != engine); + GEM_BUG_ON(deadline > rq_deadline(rq)); + + INIT_LIST_HEAD(&rq->sched.dfs); + WRITE_ONCE(rq->sched.deadline, deadline); + RQ_TRACE(rq, "set-deadline:%llu\n", deadline); + + /* + * Once the request is ready, it will be placed into the + * priority lists and then onto the HW runlist. Before the + * request is ready, it does not contribute to our preemption + * decisions and we can safely ignore it, as it will, and + * any preemption required, be dealt with upon submission. + * See engine->submit_request() + */ + + if (i915_request_in_priority_queue(rq)) + list_move_tail(&rq->sched.link, plist); + } + + return kick_submission(engine, deadline); } -static inline bool need_preempt(int prio, int active) +void i915_request_set_deadline(struct i915_request *rq, u64 deadline) { + struct intel_engine_cs *engine = READ_ONCE(rq->engine); + unsigned long flags; + + if (!intel_engine_has_scheduler(engine)) + return; + /* - * Allow preemption of low -> normal -> high, but we do - * not allow low priority tasks to preempt other low priority - * tasks under the impression that latency for low priority - * tasks does not matter (as much as background throughput), - * so kiss. + * Virtual engines complicate acquiring the engine timeline lock, + * as their rq->engine pointer is not stable until under that + * engine lock. The simple ploy we use is to take the lock then + * check that the rq still belongs to the newly locked engine. */ - return prio >= max(I915_PRIORITY_NORMAL, active); + spin_lock_irqsave(&engine->active.lock, flags); + while (engine != READ_ONCE(rq->engine)) { + spin_unlock(&engine->active.lock); + engine = READ_ONCE(rq->engine); + spin_lock(&engine->active.lock); + } + + if (i915_request_completed(rq)) + goto unlock; + + if (deadline >= rq_deadline(rq)) + goto unlock; + + if (__i915_request_set_deadline(rq, deadline)) + tasklet_hi_schedule(&engine->execlists.tasklet); + +unlock: + spin_unlock_irqrestore(&engine->active.lock, flags); } -static void kick_submission(struct intel_engine_cs *engine, - const struct i915_request *rq, - int prio) +static u64 prio_slice(int prio) { - const struct i915_request *inflight; + u64 slice; + int sf; /* - * We only need to kick the tasklet once for the high priority - * new context we add into the queue. + * With a 1ms scheduling quantum: + * + * MAX USER: ~32us deadline + * 0: ~16ms deadline + * MIN_USER: 1000ms deadline */ - if (prio <= engine->execlists.queue_priority_hint) - return; - rcu_read_lock(); + if (prio >= __I915_PRIORITY_KERNEL__) + return INT_MAX - prio; - /* Nothing currently active? We're overdue for a submission! */ - inflight = execlists_active(&engine->execlists); - if (!inflight) - goto unlock; + slice = __I915_PRIORITY_KERNEL__ - prio; + if (prio >= 0) + sf = 20 - 6; + else + sf = 20 - 1; + + return slice << sf; +} + +u64 i915_scheduler_virtual_deadline(u64 kt, int priority) +{ + return i915_sched_to_ticks(kt + prio_slice(priority)); +} + +u64 i915_scheduler_next_virtual_deadline(int priority) +{ + return i915_scheduler_virtual_deadline(ktime_get(), priority); +} + +static u64 signal_deadline(const struct i915_request *rq) +{ + u64 last = ktime_to_ns(ktime_get()); + const struct i915_dependency *p; /* - * If we are already the currently executing context, don't - * bother evaluating if we should preempt ourselves. + * Find the earliest point at which we will become 'ready', + * which we infer from the deadline of all active signalers. + * We will position ourselves at the end of that chain of work. */ - if (inflight->context == rq->context) - goto unlock; - ENGINE_TRACE(engine, - "bumping queue-priority-hint:%d for rq:%llx:%lld, inflight:%llx:%lld prio %d\n", - prio, - rq->fence.context, rq->fence.seqno, - inflight->fence.context, inflight->fence.seqno, - inflight->sched.attr.priority); + rcu_read_lock(); + for_each_signaler(p, rq) { + const struct i915_request *s = + container_of(p->signaler, typeof(*s), sched); + u64 deadline; - engine->execlists.queue_priority_hint = prio; - if (need_preempt(prio, rq_prio(inflight))) - tasklet_hi_schedule(&engine->execlists.tasklet); + if (i915_request_completed(s)) + continue; -unlock: + if (rq_prio(s) < rq_prio(rq)) + continue; + + deadline = i915_sched_to_ns(rq_deadline(s)); + if (p->flags & I915_DEPENDENCY_WEAK) + deadline -= prio_slice(rq_prio(s)); + + last = max(last, deadline); + } rcu_read_unlock(); + + return last; } -static void __i915_request_set_priority(struct i915_request *rq, int prio) +static u64 earliest_deadline(const struct i915_request *rq) +{ + return i915_scheduler_virtual_deadline(signal_deadline(rq), + rq_prio(rq)); +} + +static bool set_earliest_deadline(struct i915_request *rq, u64 old) +{ + u64 dl; + + /* Recompute our deadlines and promote after a priority change */ + dl = min(earliest_deadline(rq), rq_deadline(rq)); + if (dl >= old) + return false; + + return __i915_request_set_deadline(rq, dl); +} + +static bool __i915_request_set_priority(struct i915_request *rq, int prio) { struct intel_engine_cs *engine = rq->engine; struct i915_request *rn; - struct list_head *plist; + bool kick = false; LIST_HEAD(dfs); lockdep_assert_held(&engine->active.lock); @@ -280,32 +421,20 @@ static void __i915_request_set_priority(struct i915_request *rq, int prio) } } - plist = i915_sched_lookup_priolist(engine, prio); - - /* Fifo and depth-first replacement ensure our deps execute first */ list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) { GEM_BUG_ON(rq->engine != engine); + GEM_BUG_ON(prio < rq_prio(rq)); INIT_LIST_HEAD(&rq->sched.dfs); WRITE_ONCE(rq->sched.attr.priority, prio); + RQ_TRACE(rq, "set-priority:%d\n", prio); - /* - * Once the request is ready, it will be placed into the - * priority lists and then onto the HW runlist. Before the - * request is ready, it does not contribute to our preemption - * decisions and we can safely ignore it, as it will, and - * any preemption required, be dealt with upon submission. - * See engine->submit_request() - */ - if (!i915_request_is_ready(rq)) - continue; - - if (i915_request_in_priority_queue(rq)) - list_move_tail(&rq->sched.link, plist); - - /* Defer (tasklet) submission until after all updates. */ - kick_submission(engine, rq, prio); + if (i915_request_is_ready(rq) && + set_earliest_deadline(rq, rq_deadline(rq))) + kick = true; } + + return kick; } void i915_request_set_priority(struct i915_request *rq, int prio) @@ -316,12 +445,6 @@ void i915_request_set_priority(struct i915_request *rq, int prio) if (!intel_engine_has_scheduler(engine)) return; - /* - * Virtual engines complicate acquiring the engine timeline lock, - * as their rq->engine pointer is not stable until under that - * engine lock. The simple ploy we use is to take the lock then - * check that the rq still belongs to the newly locked engine. - */ spin_lock_irqsave(&engine->active.lock, flags); while (engine != READ_ONCE(rq->engine)) { spin_unlock(&engine->active.lock); @@ -335,12 +458,21 @@ void i915_request_set_priority(struct i915_request *rq, int prio) if (prio <= rq_prio(rq)) goto unlock; - __i915_request_set_priority(rq, prio); + if (__i915_request_set_priority(rq, prio)) + tasklet_hi_schedule(&engine->execlists.tasklet); unlock: spin_unlock_irqrestore(&engine->active.lock, flags); } +bool intel_engine_queue_request(struct intel_engine_cs *engine, + struct i915_request *rq) +{ + lockdep_assert_held(&engine->active.lock); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + return set_earliest_deadline(rq, I915_DEADLINE_NEVER); +} + void i915_sched_node_init(struct i915_sched_node *node) { spin_lock_init(&node->lock); @@ -356,6 +488,7 @@ void i915_sched_node_init(struct i915_sched_node *node) void i915_sched_node_reinit(struct i915_sched_node *node) { node->attr.priority = I915_PRIORITY_INVALID; + node->deadline = I915_DEADLINE_NEVER; node->semaphores = 0; node->flags = 0; @@ -388,6 +521,7 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node, if (!node_signaled(signal)) { INIT_LIST_HEAD(&dep->ipi_link); + dep->ipi_deadline = I915_DEADLINE_NEVER; dep->ipi_priority = I915_PRIORITY_INVALID; dep->signaler = signal; dep->waiter = node; @@ -519,6 +653,10 @@ void i915_sched_node_retire(struct i915_sched_node *node) spin_unlock_irq(&node->lock); } +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) +#include "selftests/i915_scheduler.c" +#endif + static void i915_global_scheduler_shrink(void) { kmem_cache_shrink(global.slab_dependencies); diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index b26a13ef6feb..62265108230f 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -37,15 +37,27 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node, void i915_sched_node_retire(struct i915_sched_node *node); void i915_request_set_priority(struct i915_request *request, int prio); +void i915_request_set_deadline(struct i915_request *request, u64 deadline); + +u64 i915_scheduler_virtual_deadline(u64 kt, int priority); +u64 i915_scheduler_next_virtual_deadline(int priority); + +bool intel_engine_queue_request(struct intel_engine_cs *engine, + struct i915_request *rq); struct list_head * -i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio); +i915_sched_lookup_priolist(struct intel_engine_cs *engine, u64 deadline); + +void i915_priolist_free(struct i915_priolist *p); + +static inline u64 i915_sched_to_ticks(ktime_t kt) +{ + return ktime_to_ns(kt) >> I915_SCHED_DEADLINE_SHIFT; +} -void __i915_priolist_free(struct i915_priolist *p); -static inline void i915_priolist_free(struct i915_priolist *p) +static inline u64 i915_sched_to_ns(u64 deadline) { - if (p->priority != I915_PRIORITY_NORMAL) - __i915_priolist_free(p); + return deadline << I915_SCHED_DEADLINE_SHIFT; } #endif /* _I915_SCHEDULER_H_ */ diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h index ce60577df2bf..ae7ca78a88c8 100644 --- a/drivers/gpu/drm/i915/i915_scheduler_types.h +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h @@ -69,6 +69,22 @@ struct i915_sched_node { unsigned int flags; #define I915_SCHED_HAS_EXTERNAL_CHAIN BIT(0) intel_engine_mask_t semaphores; + + /** + * @deadline: [virtual] deadline + * + * When the request is ready for execution, it is given a quota + * (the engine's timeslice) and a virtual deadline. The virtual + * deadline is derived from the current time: + * ktime_get() + (prio_ratio * timeslice) + * + * Requests are then executed in order of deadline completion. + * Requests with earlier deadlines than currently executing on + * the engine will preempt the active requests. + */ + u64 deadline; +#define I915_SCHED_DEADLINE_SHIFT 19 /* i.e. roughly 500us buckets */ +#define I915_DEADLINE_NEVER U64_MAX }; struct i915_dependency { @@ -81,6 +97,7 @@ struct i915_dependency { #define I915_DEPENDENCY_ALLOC BIT(0) #define I915_DEPENDENCY_EXTERNAL BIT(1) #define I915_DEPENDENCY_WEAK BIT(2) + u64 ipi_deadline; int ipi_priority; }; diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h index 1929feba4e8e..29ff6b669cc2 100644 --- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h +++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h @@ -24,6 +24,7 @@ selftest(uncore, intel_uncore_mock_selftests) selftest(engine, intel_engine_cs_mock_selftests) selftest(timelines, intel_timeline_mock_selftests) selftest(requests, i915_request_mock_selftests) +selftest(scheduler, i915_scheduler_mock_selftests) selftest(objects, i915_gem_object_mock_selftests) selftest(phys, i915_gem_phys_mock_selftests) selftest(dmabuf, i915_gem_dmabuf_mock_selftests) diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 92c628f18c60..db91e639918e 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -2124,6 +2124,7 @@ static int measure_preemption(struct intel_context *ce) intel_ring_advance(rq, cs); rq->sched.attr.priority = I915_PRIORITY_BARRIER; + rq->sched.deadline = 0; elapsed[i - 1] = ENGINE_READ_FW(ce->engine, RING_TIMESTAMP); i915_request_add(rq); diff --git a/drivers/gpu/drm/i915/selftests/i915_scheduler.c b/drivers/gpu/drm/i915/selftests/i915_scheduler.c new file mode 100644 index 000000000000..9ca50db81034 --- /dev/null +++ b/drivers/gpu/drm/i915/selftests/i915_scheduler.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +#include "i915_selftest.h" + +static int mock_scheduler_slices(void *dummy) +{ + u64 min, max, normal, kernel; + + min = prio_slice(I915_PRIORITY_MIN); + pr_info("%8s slice: %lluus\n", "min", min >> 10); + + normal = prio_slice(0); + pr_info("%8s slice: %lluus\n", "normal", normal >> 10); + + max = prio_slice(I915_PRIORITY_MAX); + pr_info("%8s slice: %lluus\n", "max", max >> 10); + + kernel = prio_slice(I915_PRIORITY_BARRIER); + pr_info("%8s slice: %lluus\n", "kernel", kernel >> 10); + + if (kernel != 0) { + pr_err("kernel prio slice should be 0\n"); + return -EINVAL; + } + + if (max >= normal) { + pr_err("maximum prio slice should be shorter than normal\n"); + return -EINVAL; + } + + if (min <= normal) { + pr_err("minimum prio slice should be longer than normal\n"); + return -EINVAL; + } + + return 0; +} + +int i915_scheduler_mock_selftests(void) +{ + static const struct i915_subtest tests[] = { + SUBTEST(mock_scheduler_slices), + }; + + return i915_subtests(tests, NULL); +} -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:01 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:01 +0100 Subject: [Intel-gfx] [PATCH 21/28] drm/i915/gt: Do not suspend bonded requests if one hangs In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-21-chris@chris-wilson.co.uk> Treat the dependency between bonded requests as weak and leave the remainder of the pair on the GPU if one hangs. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 3199c65fa7e8..af6f78eca9ad 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2726,6 +2726,9 @@ static void __execlists_hold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); + if (p->flags & I915_DEPENDENCY_WEAK) + continue; + /* Leave semaphores spinning on the other engines */ if (w->engine != rq->engine) continue; @@ -2850,6 +2853,9 @@ static void __execlists_unhold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); + if (p->flags & I915_DEPENDENCY_WEAK) + continue; + /* Propagate any change in error status */ if (rq->fence.error) i915_request_set_error_once(w, rq->fence.error); -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:44 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:44 +0100 Subject: [Intel-gfx] [PATCH 04/28] drm/i915/selftests: Remove live_suppress_wait_preempt In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-4-chris@chris-wilson.co.uk> With the removal of the internal wait-priority boosting, we can also remove the selftest to ensure that those waits were being suppressed from causing preemptions. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 178 ------------------------- 1 file changed, 178 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 67d74e6432a8..e838e38a262c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2379,183 +2379,6 @@ static int live_suppress_self_preempt(void *arg) goto err_client_b; } -static int __i915_sw_fence_call -dummy_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) -{ - return NOTIFY_DONE; -} - -static struct i915_request *dummy_request(struct intel_engine_cs *engine) -{ - struct i915_request *rq; - - rq = kzalloc(sizeof(*rq), GFP_KERNEL); - if (!rq) - return NULL; - - rq->engine = engine; - - spin_lock_init(&rq->lock); - INIT_LIST_HEAD(&rq->fence.cb_list); - rq->fence.lock = &rq->lock; - rq->fence.ops = &i915_fence_ops; - - i915_sched_node_init(&rq->sched); - - /* mark this request as permanently incomplete */ - rq->fence.seqno = 1; - BUILD_BUG_ON(sizeof(rq->fence.seqno) != 8); /* upper 32b == 0 */ - rq->hwsp_seqno = (u32 *)&rq->fence.seqno + 1; - GEM_BUG_ON(i915_request_completed(rq)); - - i915_sw_fence_init(&rq->submit, dummy_notify); - set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); - - spin_lock_init(&rq->lock); - rq->fence.lock = &rq->lock; - INIT_LIST_HEAD(&rq->fence.cb_list); - - return rq; -} - -static void dummy_request_free(struct i915_request *dummy) -{ - /* We have to fake the CS interrupt to kick the next request */ - i915_sw_fence_commit(&dummy->submit); - - i915_request_mark_complete(dummy); - dma_fence_signal(&dummy->fence); - - i915_sched_node_fini(&dummy->sched); - i915_sw_fence_fini(&dummy->submit); - - dma_fence_free(&dummy->fence); -} - -static int live_suppress_wait_preempt(void *arg) -{ - struct intel_gt *gt = arg; - struct preempt_client client[4]; - struct i915_request *rq[ARRAY_SIZE(client)] = {}; - struct intel_engine_cs *engine; - enum intel_engine_id id; - int err = -ENOMEM; - int i; - - /* - * Waiters are given a little priority nudge, but not enough - * to actually cause any preemption. Double check that we do - * not needlessly generate preempt-to-idle cycles. - */ - - if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915)) - return 0; - - if (preempt_client_init(gt, &client[0])) /* ELSP[0] */ - return -ENOMEM; - if (preempt_client_init(gt, &client[1])) /* ELSP[1] */ - goto err_client_0; - if (preempt_client_init(gt, &client[2])) /* head of queue */ - goto err_client_1; - if (preempt_client_init(gt, &client[3])) /* bystander */ - goto err_client_2; - - for_each_engine(engine, gt, id) { - int depth; - - if (!intel_engine_has_preemption(engine)) - continue; - - if (!engine->emit_init_breadcrumb) - continue; - - for (depth = 0; depth < ARRAY_SIZE(client); depth++) { - struct i915_request *dummy; - - engine->execlists.preempt_hang.count = 0; - - dummy = dummy_request(engine); - if (!dummy) - goto err_client_3; - - for (i = 0; i < ARRAY_SIZE(client); i++) { - struct i915_request *this; - - this = spinner_create_request(&client[i].spin, - client[i].ctx, engine, - MI_NOOP); - if (IS_ERR(this)) { - err = PTR_ERR(this); - goto err_wedged; - } - - /* Disable NEWCLIENT promotion */ - __i915_active_fence_set(&i915_request_timeline(this)->last_request, - &dummy->fence); - - rq[i] = i915_request_get(this); - i915_request_add(this); - } - - dummy_request_free(dummy); - - GEM_BUG_ON(i915_request_completed(rq[0])); - if (!igt_wait_for_spinner(&client[0].spin, rq[0])) { - pr_err("%s: First client failed to start\n", - engine->name); - goto err_wedged; - } - GEM_BUG_ON(!i915_request_started(rq[0])); - - if (i915_request_wait(rq[depth], - I915_WAIT_PRIORITY, - 1) != -ETIME) { - pr_err("%s: Waiter depth:%d completed!\n", - engine->name, depth); - goto err_wedged; - } - - for (i = 0; i < ARRAY_SIZE(client); i++) { - igt_spinner_end(&client[i].spin); - i915_request_put(rq[i]); - rq[i] = NULL; - } - - if (igt_flush_test(gt->i915)) - goto err_wedged; - - if (engine->execlists.preempt_hang.count) { - pr_err("%s: Preemption recorded x%d, depth %d; should have been suppressed!\n", - engine->name, - engine->execlists.preempt_hang.count, - depth); - err = -EINVAL; - goto err_client_3; - } - } - } - - err = 0; -err_client_3: - preempt_client_fini(&client[3]); -err_client_2: - preempt_client_fini(&client[2]); -err_client_1: - preempt_client_fini(&client[1]); -err_client_0: - preempt_client_fini(&client[0]); - return err; - -err_wedged: - for (i = 0; i < ARRAY_SIZE(client); i++) { - igt_spinner_end(&client[i].spin); - i915_request_put(rq[i]); - } - intel_gt_set_wedged(gt); - err = -EIO; - goto err_client_3; -} - static int live_chain_preempt(void *arg) { struct intel_gt *gt = arg; @@ -4592,7 +4415,6 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_nopreempt), SUBTEST(live_preempt_cancel), SUBTEST(live_suppress_self_preempt), - SUBTEST(live_suppress_wait_preempt), SUBTEST(live_chain_preempt), SUBTEST(live_preempt_gang), SUBTEST(live_preempt_timeout), -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:57 +0100 Subject: [Intel-gfx] [PATCH 17/28] drm/i915/gem: Make relocations atomic within execbuf In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-17-chris@chris-wilson.co.uk> Although we may chide userspace for reusing the same batches concurrently from multiple threads, at the same time we must be very careful to only execute the batch and its relocations as supplied by the user. If we are not careful, we may allow another thread to rewrite the current batch with its own relocations. We must order the relocations and their batch such that they are an atomic pair on the GPU, and that the ioctl itself appears atomic to userspace. The order of execution may be undetermined, but it will not be subverted. We could do this by moving the relocations into the main request, if it were not for the situation where we need a second engine to perform the relocations for us. Instead, we use the dependency tracking to only publish the write fence on the main request and not on the relocation request, so that concurrent updates are queued after the batch has consumed its relocations. Testcase: igt/gem_exec_reloc/basic-concurrent Fixes: ef398881d27d ("drm/i915/gem: Limit struct_mutex to eb_reserve") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 92 ++++++++++++++----- .../i915/gem/selftests/i915_gem_execbuffer.c | 11 ++- 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 8f3c1cf5af31..4a50371fe6e5 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -5,6 +5,7 @@ */ #include <linux/intel-iommu.h> +#include <linux/dma-fence-proxy.h> #include <linux/dma-resv.h> #include <linux/sync_file.h> #include <linux/uaccess.h> @@ -259,6 +260,8 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; + struct dma_fence *fence; + struct i915_request *rq; struct i915_vma *rq_vma; u32 *rq_cmd; @@ -555,16 +558,6 @@ eb_add_vma(struct i915_execbuffer *eb, ev->exec = entry; ev->flags = entry->flags; - if (eb->lut_size > 0) { - ev->handle = entry->handle; - hlist_add_head(&ev->node, - &eb->buckets[hash_32(entry->handle, - eb->lut_size)]); - } - - if (entry->relocation_count) - list_add_tail(&ev->reloc_link, &eb->relocs); - /* * SNA is doing fancy tricks with compressing batch buffers, which leads * to negative relocation deltas. Usually that works out ok since the @@ -581,9 +574,21 @@ eb_add_vma(struct i915_execbuffer *eb, if (eb->reloc_cache.has_fence) ev->flags |= EXEC_OBJECT_NEEDS_FENCE; + INIT_LIST_HEAD(&ev->reloc_link); + eb->batch = ev; } + if (entry->relocation_count) + list_add_tail(&ev->reloc_link, &eb->relocs); + + if (eb->lut_size > 0) { + ev->handle = entry->handle; + hlist_add_head(&ev->node, + &eb->buckets[hash_32(entry->handle, + eb->lut_size)]); + } + if (eb_pin_vma(eb, entry, ev)) { if (entry->offset != vma->node.start) { entry->offset = vma->node.start | UPDATE; @@ -923,6 +928,7 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; + cache->fence = NULL; } #define RELOC_TAIL 4 @@ -1033,6 +1039,7 @@ static void reloc_gpu_flush(struct reloc_cache *cache) } intel_gt_chipset_flush(rq->engine->gt); + i915_request_get(rq); i915_request_add(rq); } @@ -1338,16 +1345,6 @@ eb_reloc_entry(struct i915_execbuffer *eb, if (offset == reloc->presumed_offset) return 0; - /* - * If we write into the object, we need to force the synchronisation - * barrier, either with an asynchronous clflush or if we executed the - * patching using the GPU (though that should be serialised by the - * timeline). To be completely sure, and since we are required to - * do relocations we are already stalling, disable the user's opt - * out of our synchronisation. - */ - ev->flags &= ~EXEC_OBJECT_ASYNC; - err = __reloc_entry_gpu(eb, ev->vma, reloc->offset, relocation_target(reloc, offset)); if (err) @@ -1449,6 +1446,11 @@ static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) obj->write_domain = I915_GEM_DOMAIN_RENDER; obj->read_domains = I915_GEM_DOMAIN_RENDER; + ev->flags |= EXEC_OBJECT_ASYNC; + + err = dma_resv_reserve_shared(vma->resv, 1); + if (err) + return err; err = i915_request_await_object(rq, obj, true); if (err) @@ -1459,6 +1461,7 @@ static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) return err; dma_resv_add_excl_fence(vma->resv, &rq->fence); + dma_resv_add_shared_fence(vma->resv, cache->fence); return 0; } @@ -1527,14 +1530,28 @@ static int reloc_gpu_alloc(struct i915_execbuffer *eb) return __reloc_gpu_alloc(eb, engine); } +static void free_reloc_fence(struct i915_execbuffer *eb) +{ + struct dma_fence *f = fetch_and_zero(&eb->reloc_cache.fence); + + dma_fence_signal(f); + dma_fence_put(f); +} + static int reloc_gpu(struct i915_execbuffer *eb) { struct eb_vma *ev; int err; + eb->reloc_cache.fence = __dma_fence_create_proxy(0, 0); + if (!eb->reloc_cache.fence) + return -ENOMEM; + err = reloc_gpu_alloc(eb); - if (err) + if (err) { + free_reloc_fence(eb); return err; + } GEM_BUG_ON(!eb->reloc_cache.rq); err = lock_relocs(eb); @@ -1593,6 +1610,15 @@ static int eb_relocate(struct i915_execbuffer *eb) return 0; } +static void eb_reloc_signal(struct i915_execbuffer *eb, struct i915_request *rq) +{ + dma_fence_proxy_set_real(eb->reloc_cache.fence, &rq->fence); + i915_request_put(eb->reloc_cache.rq); + + dma_fence_put(eb->reloc_cache.fence); + eb->reloc_cache.fence = NULL; +} + static int eb_move_to_gpu(struct i915_execbuffer *eb) { const unsigned int count = eb->buffer_count; @@ -1873,10 +1899,15 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, if (err) goto err_commit_unlock; - /* Wait for all writes (and relocs) into the batch to complete */ - err = i915_sw_fence_await_reservation(&pw->base.chain, - pw->batch->resv, NULL, false, - 0, I915_FENCE_GFP); + /* Wait for all writes (or relocs) into the batch to complete */ + if (!eb->reloc_cache.fence || list_empty(&eb->batch->reloc_link)) + err = i915_sw_fence_await_reservation(&pw->base.chain, + pw->batch->resv, NULL, + false, 0, I915_FENCE_GFP); + else + err = i915_sw_fence_await_dma_fence(&pw->base.chain, + &eb->reloc_cache.rq->fence, + 0, I915_FENCE_GFP); if (err < 0) goto err_commit_unlock; @@ -2004,6 +2035,15 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) { int err; + if (eb->reloc_cache.fence) { + err = i915_request_await_dma_fence(eb->request, + &eb->reloc_cache.rq->fence); + if (err) + return err; + + eb_reloc_signal(eb, eb->request); + } + err = eb_move_to_gpu(eb); if (err) return err; @@ -2663,6 +2703,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (batch->private) intel_gt_buffer_pool_put(batch->private); err_vma: + if (eb.reloc_cache.fence) + eb_reloc_signal(&eb, eb.reloc_cache.rq); if (eb.trampoline) i915_vma_unpin(eb.trampoline); eb_unpin_engine(&eb); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 4f10b51f9a7e..62bba179b455 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -23,7 +23,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, const u64 mask = GENMASK_ULL(eb->reloc_cache.use_64bit_reloc ? 63 : 31, 0); const u32 *map = page_mask_bits(obj->mm.mapping); - struct i915_request *rq; struct eb_vma ev; int err; int i; @@ -40,6 +39,9 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + /* Single stage pipeline in the selftest */ + eb->reloc_cache.fence = &eb->reloc_cache.rq->fence; + list_add(&ev.reloc_link, &eb->relocs); err = lock_relocs(eb); if (err) @@ -71,8 +73,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; - GEM_BUG_ON(!eb->reloc_cache.rq); - rq = i915_request_get(eb->reloc_cache.rq); reloc_gpu_flush(&eb->reloc_cache); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); @@ -81,7 +81,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, goto put_rq; } - if (!i915_request_completed(rq)) { + if (!i915_request_completed(eb->reloc_cache.rq)) { pr_err("%s: did not wait for relocations!\n", eb->engine->name); err = -EINVAL; goto put_rq; @@ -100,7 +100,8 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, igt_hexdump(map, 4096); put_rq: - i915_request_put(rq); + i915_request_put(eb->reloc_cache.rq); + eb->reloc_cache.rq = NULL; unpin_vma: i915_vma_unpin(ev.vma); return err; -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:54 +0100 Subject: [Intel-gfx] [PATCH 14/28] dma-buf: Proxy fence, an unsignaled fence placeholder In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-14-chris@chris-wilson.co.uk> Often we need to create a fence for a future event that has not yet been associated with a fence. We can store a proxy fence, a placeholder, in the timeline and replace it later when the real fence is known. Any listeners that attach to the proxy fence will automatically be signaled when the real fence completes, and any future listeners will instead be attach directly to the real fence avoiding any indirection overhead. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com> --- drivers/dma-buf/Makefile | 13 +- drivers/dma-buf/dma-fence-private.h | 20 + drivers/dma-buf/dma-fence-proxy.c | 306 +++++++++++ drivers/dma-buf/dma-fence.c | 4 +- drivers/dma-buf/selftests.h | 1 + drivers/dma-buf/st-dma-fence-proxy.c | 752 +++++++++++++++++++++++++++ include/linux/dma-fence-proxy.h | 38 ++ 7 files changed, 1130 insertions(+), 4 deletions(-) create mode 100644 drivers/dma-buf/dma-fence-private.h create mode 100644 drivers/dma-buf/dma-fence-proxy.c create mode 100644 drivers/dma-buf/st-dma-fence-proxy.c create mode 100644 include/linux/dma-fence-proxy.h diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile index 995e05f609ff..afaf6dadd9a3 100644 --- a/drivers/dma-buf/Makefile +++ b/drivers/dma-buf/Makefile @@ -1,6 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \ - dma-resv.o seqno-fence.o +obj-y := \ + dma-buf.o \ + dma-fence.o \ + dma-fence-array.o \ + dma-fence-chain.o \ + dma-fence-proxy.o \ + dma-resv.o \ + seqno-fence.o obj-$(CONFIG_DMABUF_HEAPS) += dma-heap.o obj-$(CONFIG_DMABUF_HEAPS) += heaps/ obj-$(CONFIG_SYNC_FILE) += sync_file.o @@ -10,6 +16,7 @@ obj-$(CONFIG_UDMABUF) += udmabuf.o dmabuf_selftests-y := \ selftest.o \ st-dma-fence.o \ - st-dma-fence-chain.o + st-dma-fence-chain.o \ + st-dma-fence-proxy.o obj-$(CONFIG_DMABUF_SELFTESTS) += dmabuf_selftests.o diff --git a/drivers/dma-buf/dma-fence-private.h b/drivers/dma-buf/dma-fence-private.h new file mode 100644 index 000000000000..6924d28af0fa --- /dev/null +++ b/drivers/dma-buf/dma-fence-private.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf and to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark <robdclark at gmail.com> + * Maarten Lankhorst <maarten.lankhorst at canonical.com> + */ + +#ifndef DMA_FENCE_PRIVATE_H +#define DMA_FENCE_PRIAVTE_H + +struct dma_fence; + +bool __dma_fence_enable_signaling(struct dma_fence *fence); + +#endif /* DMA_FENCE_PRIAVTE_H */ diff --git a/drivers/dma-buf/dma-fence-proxy.c b/drivers/dma-buf/dma-fence-proxy.c new file mode 100644 index 000000000000..42674e92b0f9 --- /dev/null +++ b/drivers/dma-buf/dma-fence-proxy.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dma-fence-proxy: placeholder unsignaled fence + * + * Copyright (C) 2017-2019 Intel Corporation + */ + +#include <linux/dma-fence.h> +#include <linux/dma-fence-proxy.h> +#include <linux/export.h> +#include <linux/irq_work.h> +#include <linux/slab.h> + +#include "dma-fence-private.h" + +struct dma_fence_proxy { + struct dma_fence base; + + struct dma_fence *real; + struct dma_fence_cb cb; + struct irq_work work; + + wait_queue_head_t wq; +}; + +#ifdef CONFIG_DEBUG_LOCK_ALLOC +#define same_lockclass(A, B) (A)->dep_map.key == (B)->dep_map.key +#else +#define same_lockclass(A, B) 0 +#endif + +static const char *proxy_get_driver_name(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + + return real ? real->ops->get_driver_name(real) : "proxy"; +} + +static const char *proxy_get_timeline_name(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + + return real ? real->ops->get_timeline_name(real) : "unset"; +} + +static void proxy_irq_work(struct irq_work *work) +{ + struct dma_fence_proxy *p = container_of(work, typeof(*p), work); + + dma_fence_signal(&p->base); + dma_fence_put(&p->base); +} + +static void proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb) +{ + struct dma_fence_proxy *p = container_of(cb, typeof(*p), cb); + + /* Signaled before enabling signalling callbacks? */ + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &p->base.flags)) { + dma_fence_put(&p->base); + return; + } + + if (real->error) + dma_fence_set_error(&p->base, real->error); + + /* Lower the height of the proxy chain -> single stack frame */ + irq_work_queue(&p->work); +} + +static bool proxy_enable_signaling(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + struct dma_fence *real = READ_ONCE(p->real); + bool ret = true; + + if (real) { + spin_lock_nested(real->lock, + same_lockclass(&p->wq.lock, real->lock)); + ret = __dma_fence_enable_signaling(real); + if (!ret && real->error) + dma_fence_set_error(&p->base, real->error); + spin_unlock(real->lock); + } + + return ret; +} + +static void proxy_release(struct dma_fence *fence) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + + dma_fence_put(p->real); + dma_fence_free(&p->base); +} + +const struct dma_fence_ops dma_fence_proxy_ops = { + .get_driver_name = proxy_get_driver_name, + .get_timeline_name = proxy_get_timeline_name, + .enable_signaling = proxy_enable_signaling, + .wait = dma_fence_default_wait, + .release = proxy_release, +}; +EXPORT_SYMBOL_GPL(dma_fence_proxy_ops); + +/** + * __dma_fence_create_proxy - Create an unset dma-fence + * @context: context number to use for proxy fence + * @seqno: sequence number to use for proxy fence + * + * __dma_fence_create_proxy() creates a new dma_fence stub that is initially + * unsignaled and may later be replaced with a real fence. Any listeners + * to the proxy fence will be signaled when the target fence signals its + * completion. + */ +struct dma_fence *__dma_fence_create_proxy(u64 context, u64 seqno) +{ + struct dma_fence_proxy *p; + + p = kzalloc(sizeof(*p), GFP_KERNEL); + if (!p) + return NULL; + + init_waitqueue_head(&p->wq); + dma_fence_init(&p->base, &dma_fence_proxy_ops, &p->wq.lock, + context, seqno); + init_irq_work(&p->work, proxy_irq_work); + + return &p->base; +} +EXPORT_SYMBOL(__dma_fence_create_proxy); + +/** + * dma_fence_create_proxy - Create an unset dma-fence + * + * Wraps __dma_fence_create_proxy() to create a new proxy fence with the + * next available (unique) context id. + */ +struct dma_fence *dma_fence_create_proxy(void) +{ + return __dma_fence_create_proxy(dma_fence_context_alloc(1), 0); +} +EXPORT_SYMBOL(dma_fence_create_proxy); + +static void __wake_up_listeners(struct dma_fence_proxy *p) +{ + struct wait_queue_entry *wait, *next; + + list_for_each_entry_safe(wait, next, &p->wq.head, entry) { + INIT_LIST_HEAD(&wait->entry); + wait->func(wait, TASK_NORMAL, 0, p->real); + } +} + +static void set_proxy_callback(struct dma_fence *real, struct dma_fence_cb *cb) +{ + cb->func = proxy_callback; + list_add_tail(&cb->node, &real->cb_list); +} + +static void proxy_assign(struct dma_fence *fence, struct dma_fence *real) +{ + struct dma_fence_proxy *p = container_of(fence, typeof(*p), base); + unsigned long flags; + + if (WARN_ON(fence == real)) + return; + + if (WARN_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) + return; + + if (WARN_ON(p->real)) + return; + + spin_lock_irqsave(&p->wq.lock, flags); + + if (unlikely(!real)) { + dma_fence_signal_locked(&p->base); + goto unlock; + } + + p->real = dma_fence_get(real); + + dma_fence_get(&p->base); + spin_lock_nested(real->lock, same_lockclass(&p->wq.lock, real->lock)); + if (dma_fence_is_signaled_locked(real)) + proxy_callback(real, &p->cb); + else if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &p->base.flags) && + !__dma_fence_enable_signaling(real)) + proxy_callback(real, &p->cb); + else + set_proxy_callback(real, &p->cb); + spin_unlock(real->lock); + +unlock: + __wake_up_listeners(p); + spin_unlock_irqrestore(&p->wq.lock, flags); +} + +/** + * dma_fence_replace_proxy - Replace the proxy fence with the real target + * @slot: pointer to location of fence to update + * @fence: the new fence to store in @slot + * + * Once the real dma_fence is known, we can replace the proxy fence holder + * with a pointer to the real dma fence. Future listeners will attach to + * the real fence, avoiding any indirection overhead. Previous listeners + * will remain attached to the proxy fence, and be signaled in turn when + * the target fence completes. + */ +struct dma_fence * +dma_fence_replace_proxy(struct dma_fence __rcu **slot, struct dma_fence *fence) +{ + struct dma_fence *old; + + if (fence) + dma_fence_get(fence); + + old = rcu_replace_pointer(*slot, fence, true); + if (old && dma_fence_is_proxy(old)) + proxy_assign(old, fence); + + return old; +} +EXPORT_SYMBOL(dma_fence_replace_proxy); + +/** + * dma_fence_proxy_set_real - Set the target of a proxy fence + * @fence: the proxy fence + * @real: the target fence. + * + */ +void dma_fence_proxy_set_real(struct dma_fence *fence, struct dma_fence *real) +{ + if (dma_fence_is_proxy(fence)) + proxy_assign(fence, real); +} +EXPORT_SYMBOL(dma_fence_proxy_set_real); + +/** + * dma_fence_proxy_get_real - Query the target of a proxy fence + * @fence: the proxy fence + * + * Unpeel the proxy fence to see if it has been replaced with a real fence. + */ +struct dma_fence *dma_fence_proxy_get_real(struct dma_fence *fence) +{ + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + + if (p->real) + fence = p->real; + } + + return fence; +} +EXPORT_SYMBOL(dma_fence_proxy_get_real); + +void dma_fence_add_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait) +{ + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + unsigned long flags; + + spin_lock_irqsave(&p->wq.lock, flags); + if (!p->real) { + list_add_tail(&wait->entry, &p->wq.head); + wait = NULL; + } + fence = p->real; + spin_unlock_irqrestore(&p->wq.lock, flags); + } + + if (wait) { + INIT_LIST_HEAD(&wait->entry); + wait->func(wait, TASK_NORMAL, 0, fence); + } +} +EXPORT_SYMBOL(dma_fence_add_proxy_listener); + +bool dma_fence_remove_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait) +{ + bool ret = false; + + if (dma_fence_is_proxy(fence)) { + struct dma_fence_proxy *p = + container_of(fence, typeof(*p), base); + unsigned long flags; + + spin_lock_irqsave(&p->wq.lock, flags); + if (!list_empty(&wait->entry)) { + list_del_init(&wait->entry); + ret = true; + } + spin_unlock_irqrestore(&p->wq.lock, flags); + } + + return ret; +} +EXPORT_SYMBOL(dma_fence_remove_proxy_listener); diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 656e9ac2d028..329bd033059f 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -19,6 +19,8 @@ #define CREATE_TRACE_POINTS #include <trace/events/dma_fence.h> +#include "dma-fence-private.h" + EXPORT_TRACEPOINT_SYMBOL(dma_fence_emit); EXPORT_TRACEPOINT_SYMBOL(dma_fence_enable_signal); EXPORT_TRACEPOINT_SYMBOL(dma_fence_signaled); @@ -275,7 +277,7 @@ void dma_fence_free(struct dma_fence *fence) } EXPORT_SYMBOL(dma_fence_free); -static bool __dma_fence_enable_signaling(struct dma_fence *fence) +bool __dma_fence_enable_signaling(struct dma_fence *fence) { bool was_set; diff --git a/drivers/dma-buf/selftests.h b/drivers/dma-buf/selftests.h index bc8cea67bf1e..92d15bf50f64 100644 --- a/drivers/dma-buf/selftests.h +++ b/drivers/dma-buf/selftests.h @@ -12,3 +12,4 @@ selftest(sanitycheck, __sanitycheck__) /* keep first (igt selfcheck) */ selftest(dma_fence, dma_fence) selftest(dma_fence_chain, dma_fence_chain) +selftest(dma_fence_proxy, dma_fence_proxy) diff --git a/drivers/dma-buf/st-dma-fence-proxy.c b/drivers/dma-buf/st-dma-fence-proxy.c new file mode 100644 index 000000000000..c3f210bc4e60 --- /dev/null +++ b/drivers/dma-buf/st-dma-fence-proxy.c @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2019 Intel Corporation + */ + +#include <linux/delay.h> +#include <linux/dma-fence.h> +#include <linux/dma-fence-proxy.h> +#include <linux/kernel.h> +#include <linux/sched/signal.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#include "selftest.h" + +static struct kmem_cache *slab_fences; + +static struct mock_fence { + struct dma_fence base; + spinlock_t lock; +} *to_mock_fence(struct dma_fence *f) { + return container_of(f, struct mock_fence, base); +} + +static const char *mock_name(struct dma_fence *f) +{ + return "mock"; +} + +static void mock_fence_release(struct dma_fence *f) +{ + kmem_cache_free(slab_fences, to_mock_fence(f)); +} + +static const struct dma_fence_ops mock_ops = { + .get_driver_name = mock_name, + .get_timeline_name = mock_name, + .release = mock_fence_release, +}; + +static struct dma_fence *mock_fence(void) +{ + struct mock_fence *f; + + f = kmem_cache_alloc(slab_fences, GFP_KERNEL); + if (!f) + return NULL; + + spin_lock_init(&f->lock); + dma_fence_init(&f->base, &mock_ops, &f->lock, 0, 0); + + return &f->base; +} + +static int sanitycheck(void *arg) +{ + struct dma_fence *f; + + f = dma_fence_create_proxy(); + if (!f) + return -ENOMEM; + + dma_fence_signal(f); + dma_fence_put(f); + + return 0; +} + +struct fences { + struct dma_fence *real; + struct dma_fence *proxy; + struct dma_fence __rcu *slot; +}; + +static int create_fences(struct fences *f, bool attach) +{ + f->proxy = dma_fence_create_proxy(); + if (!f->proxy) + return -ENOMEM; + + RCU_INIT_POINTER(f->slot, f->proxy); + + f->real = mock_fence(); + if (!f->real) { + dma_fence_put(f->proxy); + return -ENOMEM; + } + + if (attach) + dma_fence_replace_proxy(&f->slot, f->real); + + return 0; +} + +static void free_fences(struct fences *f) +{ + dma_fence_put(dma_fence_replace_proxy(&f->slot, NULL)); + + dma_fence_signal(f->real); + dma_fence_put(f->real); + + dma_fence_signal(f->proxy); + dma_fence_put(f->proxy); +} + +static int wrap_target(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_proxy_get_real(f.proxy) != f.proxy) { + pr_err("Unwrapped proxy fenced reported a target fence!\n"); + goto err_free; + } + + dma_fence_proxy_set_real(f.proxy, f.real); + rcu_assign_pointer(f.slot, dma_fence_get(f.real)); /* free_fences() */ + + if (dma_fence_proxy_get_real(f.proxy) != f.real) { + pr_err("Wrapped proxy fenced did not report the target fence!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_proxy(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_proxy_get_real(f.proxy) != f.real) { + pr_err("Wrapped proxy fenced did not report the target fence!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_signaling(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_is_signaled(f.proxy)) { + pr_err("Fence unexpectedly signaled on creation\n"); + goto err_free; + } + + if (dma_fence_signal(f.real)) { + pr_err("Fence reported being already signaled\n"); + goto err_free; + } + + if (!dma_fence_is_signaled(f.proxy)) { + pr_err("Fence not reporting signaled\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_signaling_recurse(void *arg) +{ + struct fences f; + struct dma_fence *chain; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + chain = dma_fence_create_proxy(); + if (!chain) { + err = -ENOMEM; + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, chain); + dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real)); + dma_fence_put(chain); + + /* f.real <- chain <- f.proxy */ + + if (dma_fence_is_signaled(f.proxy)) { + pr_err("Fence unexpectedly signaled on creation\n"); + goto err_free; + } + + if (dma_fence_signal(f.real)) { + pr_err("Fence reported being already signaled\n"); + goto err_free; + } + + if (!dma_fence_is_signaled(f.proxy)) { + pr_err("Fence not reporting signaled\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +struct simple_cb { + struct dma_fence_cb cb; + bool seen; +}; + +static void simple_callback(struct dma_fence *f, struct dma_fence_cb *cb) +{ + /* Ensure the callback marker is visible, no excuses for missing it! */ + smp_store_mb(container_of(cb, struct simple_cb, cb)->seen, true); +} + +static int wrap_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_add_callback_recurse(void *arg) +{ + struct simple_cb cb = {}; + struct dma_fence *chain; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + chain = dma_fence_create_proxy(); + if (!chain) { + err = -ENOMEM; + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, chain); + dma_fence_put(dma_fence_replace_proxy(&f.slot, f.real)); + dma_fence_put(chain); + + /* f.real <- chain <- f.proxy */ + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_late_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + dma_fence_signal(f.real); + + if (!dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Added callback, but fence was already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (cb.seen) { + pr_err("Callback called after failed attachment!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback_late(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_signal(f.real); + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_early_add_callback_early(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_rm_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + if (!dma_fence_remove_callback(f.proxy, &cb.cb)) { + pr_err("Failed to remove callback!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (cb.seen) { + pr_err("Callback still signaled after removal!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_late_rm_callback(void *arg) +{ + struct simple_cb cb = {}; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_add_callback(f.proxy, &cb.cb, simple_callback)) { + pr_err("Failed to add callback, fence already signaled!\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!cb.seen) { + pr_err("Callback failed!\n"); + goto err_free; + } + + if (dma_fence_remove_callback(f.proxy, &cb.cb)) { + pr_err("Callback removal succeed after being executed!\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_status(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_get_status(f.proxy)) { + pr_err("Fence unexpectedly has signaled status on creation\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (!dma_fence_get_status(f.proxy)) { + pr_err("Fence not reporting signaled status\n"); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_error(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + dma_fence_set_error(f.real, -EIO); + + if (dma_fence_get_status(f.proxy)) { + pr_err("Fence unexpectedly has error status before signal\n"); + goto err_free; + } + + dma_fence_signal(f.real); + if (dma_fence_get_status(f.proxy) != -EIO) { + pr_err("Fence not reporting error status, got %d\n", + dma_fence_get_status(f.proxy)); + goto err_free; + } + + err = 0; +err_free: + free_fences(&f); + return err; +} + +static int wrap_wait(void *arg) +{ + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, true)) + return -ENOMEM; + + if (dma_fence_wait_timeout(f.proxy, false, 0) != 0) { + pr_err("Wait reported complete before being signaled\n"); + goto err_free; + } + + dma_fence_signal(f.real); + + if (dma_fence_wait_timeout(f.proxy, false, 0) == 0) { + pr_err("Wait reported incomplete after being signaled\n"); + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +struct wait_timer { + struct timer_list timer; + struct fences f; +}; + +static void wait_timer(struct timer_list *timer) +{ + struct wait_timer *wt = from_timer(wt, timer, timer); + + dma_fence_signal(wt->f.real); +} + +static int wrap_wait_timeout(void *arg) +{ + struct wait_timer wt; + int err = -EINVAL; + + if (create_fences(&wt.f, true)) + return -ENOMEM; + + timer_setup_on_stack(&wt.timer, wait_timer, 0); + + if (dma_fence_wait_timeout(wt.f.proxy, false, 1) != 0) { + pr_err("Wait reported complete before being signaled\n"); + goto err_free; + } + + mod_timer(&wt.timer, jiffies + 1); + + if (dma_fence_wait_timeout(wt.f.proxy, false, 2) != 0) { + if (timer_pending(&wt.timer)) { + pr_notice("Timer did not fire within the jiffie!\n"); + err = 0; /* not our fault! */ + } else { + pr_err("Wait reported incomplete after timeout\n"); + } + goto err_free; + } + + err = 0; +err_free: + del_timer_sync(&wt.timer); + destroy_timer_on_stack(&wt.timer); + dma_fence_signal(wt.f.real); + free_fences(&wt.f); + return err; +} + +struct proxy_wait { + struct wait_queue_entry base; + struct dma_fence *fence; + bool seen; +}; + +static int proxy_wait_cb(struct wait_queue_entry *entry, + unsigned int mode, int flags, void *key) +{ + struct proxy_wait *p = container_of(entry, typeof(*p), base); + + p->fence = key; + p->seen = true; + + return 0; +} + +static int wrap_listen_early(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_replace_proxy(&f.slot, f.real); + dma_fence_add_proxy_listener(f.proxy, &wait.base); + + if (!wait.seen) { + pr_err("Proxy listener was not called after replace!\n"); + err = -EINVAL; + goto err_free; + } + + if (wait.fence != f.real) { + pr_err("Proxy listener was not passed the real fence!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +static int wrap_listen_late(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_add_proxy_listener(f.proxy, &wait.base); + dma_fence_replace_proxy(&f.slot, f.real); + + if (!wait.seen) { + pr_err("Proxy listener was not called on replace!\n"); + err = -EINVAL; + goto err_free; + } + + if (wait.fence != f.real) { + pr_err("Proxy listener was not passed the real fence!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +static int wrap_listen_cancel(void *arg) +{ + struct proxy_wait wait = { .base.func = proxy_wait_cb }; + struct fences f; + int err = -EINVAL; + + if (create_fences(&f, false)) + return -ENOMEM; + + dma_fence_add_proxy_listener(f.proxy, &wait.base); + if (!dma_fence_remove_proxy_listener(f.proxy, &wait.base)) { + pr_err("Cancelling listener, already detached?\n"); + err = -EINVAL; + goto err_free; + } + dma_fence_replace_proxy(&f.slot, f.real); + + if (wait.seen) { + pr_err("Proxy listener was called after being removed!\n"); + err = -EINVAL; + goto err_free; + } + + if (dma_fence_remove_proxy_listener(f.proxy, &wait.base)) { + pr_err("Double listener cancellation!\n"); + err = -EINVAL; + goto err_free; + } + + err = 0; +err_free: + dma_fence_signal(f.real); + free_fences(&f); + return err; +} + +int dma_fence_proxy(void) +{ + static const struct subtest tests[] = { + SUBTEST(sanitycheck), + SUBTEST(wrap_target), + SUBTEST(wrap_proxy), + SUBTEST(wrap_signaling), + SUBTEST(wrap_signaling_recurse), + SUBTEST(wrap_add_callback), + SUBTEST(wrap_add_callback_recurse), + SUBTEST(wrap_late_add_callback), + SUBTEST(wrap_early_add_callback), + SUBTEST(wrap_early_add_callback_late), + SUBTEST(wrap_early_add_callback_early), + SUBTEST(wrap_rm_callback), + SUBTEST(wrap_late_rm_callback), + SUBTEST(wrap_status), + SUBTEST(wrap_error), + SUBTEST(wrap_wait), + SUBTEST(wrap_wait_timeout), + SUBTEST(wrap_listen_early), + SUBTEST(wrap_listen_late), + SUBTEST(wrap_listen_cancel), + }; + int ret; + + slab_fences = KMEM_CACHE(mock_fence, + SLAB_TYPESAFE_BY_RCU | + SLAB_HWCACHE_ALIGN); + if (!slab_fences) + return -ENOMEM; + + ret = subtests(tests, NULL); + + kmem_cache_destroy(slab_fences); + + return ret; +} diff --git a/include/linux/dma-fence-proxy.h b/include/linux/dma-fence-proxy.h new file mode 100644 index 000000000000..6a986b5bb009 --- /dev/null +++ b/include/linux/dma-fence-proxy.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * dma-fence-proxy: allows waiting upon unset and future fences + * + * Copyright (C) 2017 Intel Corporation + */ + +#ifndef __LINUX_DMA_FENCE_PROXY_H +#define __LINUX_DMA_FENCE_PROXY_H + +#include <linux/kernel.h> +#include <linux/dma-fence.h> + +struct wait_queue_entry; + +extern const struct dma_fence_ops dma_fence_proxy_ops; + +struct dma_fence *__dma_fence_create_proxy(u64 context, u64 seqno); +struct dma_fence *dma_fence_create_proxy(void); + +static inline bool dma_fence_is_proxy(struct dma_fence *fence) +{ + return fence->ops == &dma_fence_proxy_ops; +} + +void dma_fence_proxy_set_real(struct dma_fence *fence, struct dma_fence *real); +struct dma_fence *dma_fence_proxy_get_real(struct dma_fence *fence); + +struct dma_fence * +dma_fence_replace_proxy(struct dma_fence __rcu **slot, + struct dma_fence *fence); + +void dma_fence_add_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait); +bool dma_fence_remove_proxy_listener(struct dma_fence *fence, + struct wait_queue_entry *wait); + +#endif /* __LINUX_DMA_FENCE_PROXY_H */ -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:51 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:51 +0100 Subject: [Intel-gfx] [PATCH 11/28] drm/i915/gem: Lift GPU relocation allocation In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-11-chris@chris-wilson.co.uk> Since we have reduced the relocations paths to just use the async GPU, we can lift the request allocation to the start of the relocations. Knowing that we use one request for all relocations will simplify tracking the relocation fence. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 100 ++++++++++-------- .../i915/gem/selftests/i915_gem_execbuffer.c | 5 +- 2 files changed, 57 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 01ab1e15a142..e012857be129 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -900,8 +900,6 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) static void eb_destroy(const struct i915_execbuffer *eb) { - GEM_BUG_ON(eb->reloc_cache.rq); - if (eb->array) eb_vma_array_put(eb->array); @@ -926,7 +924,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->rq = NULL; cache->target = NULL; } @@ -1007,13 +1004,9 @@ static unsigned int reloc_bb_flags(const struct reloc_cache *cache) static int reloc_gpu_flush(struct reloc_cache *cache) { - struct i915_request *rq; + struct i915_request *rq = cache->rq; int err; - rq = fetch_and_zero(&cache->rq); - if (!rq) - return 0; - if (cache->rq_vma) { struct drm_i915_gem_object *obj = cache->rq_vma->obj; @@ -1062,9 +1055,8 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) return err; } -static int __reloc_gpu_alloc(struct i915_execbuffer *eb, - struct intel_engine_cs *engine, - unsigned int len) +static int +__reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { struct reloc_cache *cache = &eb->reloc_cache; struct intel_gt_buffer_pool_node *pool; @@ -1154,33 +1146,14 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, return err; } -static bool reloc_can_use_engine(const struct intel_engine_cs *engine) -{ - return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); -} - -static u32 *reloc_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, + struct i915_vma *vma, + unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (unlikely(!cache->rq)) { - struct intel_engine_cs *engine = eb->engine; - - if (!reloc_can_use_engine(engine)) { - engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; - if (!engine) - return ERR_PTR(-ENODEV); - } - - err = __reloc_gpu_alloc(eb, engine, len); - if (unlikely(err)) - return ERR_PTR(err); - } - if (vma != cache->target) { err = reloc_move_to_gpu(cache->rq, vma); if (unlikely(err)) { @@ -1238,7 +1211,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_gpu(eb, vma, len); + batch = reloc_batch_grow(eb, vma, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1499,6 +1472,47 @@ static long eb_reloc_vma(struct i915_execbuffer *eb, struct eb_vma *ev, return required; } +static bool reloc_can_use_engine(const struct intel_engine_cs *engine) +{ + return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); +} + +static int reloc_gpu_alloc(struct i915_execbuffer *eb) +{ + struct intel_engine_cs *engine = eb->engine; + + if (!reloc_can_use_engine(engine)) { + engine = engine->gt->engine_class[COPY_ENGINE_CLASS][0]; + if (!engine) + return -ENODEV; + } + + return __reloc_gpu_alloc(eb, engine); +} + +static int reloc_gpu(struct i915_execbuffer *eb) +{ + struct eb_vma *ev; + int flush, err; + + err = reloc_gpu_alloc(eb); + if (err) + return err; + GEM_BUG_ON(!eb->reloc_cache.rq); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + err = eb_reloc_vma(eb, ev, eb_reloc_entry); + if (err < 0) + goto out; + } + +out: + flush = reloc_gpu_flush(&eb->reloc_cache); + if (!err) + err = flush; + return err; +} + static int eb_relocate(struct i915_execbuffer *eb) { int err; @@ -1516,7 +1530,6 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { struct eb_vma *ev, *en; - int flush; list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { err = eb_reloc_vma(eb, ev, eb_reloc_prepare); @@ -1527,18 +1540,14 @@ static int eb_relocate(struct i915_execbuffer *eb) list_del_init(&ev->reloc_link); } - list_for_each_entry(ev, &eb->relocs, reloc_link) { - err = eb_reloc_vma(eb, ev, eb_reloc_entry); - if (err < 0) - break; + if (!list_empty(&eb->relocs)) { + err = reloc_gpu(eb); + if (err) + return err; } - - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; } - return err; + return 0; } static int eb_move_to_gpu(struct i915_execbuffer *eb) @@ -2538,9 +2547,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, batch = vma; } - /* All GPU relocation batches must be submitted prior to the user rq */ - GEM_BUG_ON(eb.reloc_cache.rq); - /* Allocate a request for this batch buffer nice and early. */ eb.request = i915_request_create(eb.context); if (IS_ERR(eb.request)) { diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 57c14d3340cd..50fe22d87ae1 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -36,6 +36,10 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) return err; + err = reloc_gpu_alloc(eb); + if (err) + goto unpin_vma; + /* 8-Byte aligned */ err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); if (err) @@ -63,7 +67,6 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, err = reloc_gpu_flush(&eb->reloc_cache); if (err) goto put_rq; - GEM_BUG_ON(eb->reloc_cache.rq); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); if (err) { -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:08 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:08 +0100 Subject: [Intel-gfx] [PATCH 28/28] drm/i915: Replace the priority boosting for the display with a deadline In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-28-chris@chris-wilson.co.uk> For a modeset/pageflip, there is a very precise deadline by which the frame must be completed in order to hit the vblank and be shown. While we don't pass along that exact information, we can at least inform the scheduler that this request-chain needs to be completed asap. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 ++-- drivers/gpu/drm/i915/gem/i915_gem_wait.c | 21 ++++++++++---------- drivers/gpu/drm/i915/i915_priolist_types.h | 3 --- 4 files changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 797e3573d392..5bb20f701a44 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15964,7 +15964,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, if (ret) return ret; - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); + i915_gem_object_wait_deadline(obj, 0, ktime_get() /* next vblank? */); i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB); if (!new_plane_state->uapi.fence) { /* implicit fencing */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 876c34982555..7bcd2661de4c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -474,9 +474,9 @@ static inline void __start_cpu_write(struct drm_i915_gem_object *obj) int i915_gem_object_wait(struct drm_i915_gem_object *obj, unsigned int flags, long timeout); -int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, +int i915_gem_object_wait_deadline(struct drm_i915_gem_object *obj, unsigned int flags, - int prio); + ktime_t deadline); void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj, enum fb_op_origin origin); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c b/drivers/gpu/drm/i915/gem/i915_gem_wait.c index cefbbb3d9b52..5224d4363ea3 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c @@ -93,17 +93,18 @@ i915_gem_object_wait_reservation(struct dma_resv *resv, return timeout; } -static void __fence_set_priority(struct dma_fence *fence, int prio) +static void __fence_set_deadline(struct dma_fence *fence, ktime_t deadline) { if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence)) return; local_bh_disable(); - i915_request_set_priority(to_request(fence), prio); + i915_request_set_deadline(to_request(fence), + i915_sched_to_ticks(deadline)); local_bh_enable(); /* kick the tasklets if queues were reprioritised */ } -static void fence_set_priority(struct dma_fence *fence, int prio) +static void fence_set_deadline(struct dma_fence *fence, ktime_t deadline) { /* Recurse once into a fence-array */ if (dma_fence_is_array(fence)) { @@ -111,16 +112,16 @@ static void fence_set_priority(struct dma_fence *fence, int prio) int i; for (i = 0; i < array->num_fences; i++) - __fence_set_priority(array->fences[i], prio); + __fence_set_deadline(array->fences[i], deadline); } else { - __fence_set_priority(fence, prio); + __fence_set_deadline(fence, deadline); } } int -i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, +i915_gem_object_wait_deadline(struct drm_i915_gem_object *obj, unsigned int flags, - int prio) + ktime_t deadline) { struct dma_fence *excl; @@ -130,12 +131,12 @@ i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, int ret; ret = dma_resv_get_fences_rcu(obj->base.resv, - &excl, &count, &shared); + &excl, &count, &shared); if (ret) return ret; for (i = 0; i < count; i++) { - fence_set_priority(shared[i], prio); + fence_set_deadline(shared[i], deadline); dma_fence_put(shared[i]); } @@ -145,7 +146,7 @@ i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, } if (excl) { - fence_set_priority(excl, prio); + fence_set_deadline(excl, deadline); dma_fence_put(excl); } return 0; diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h index 43a0ac45295f..ac6d9614ea23 100644 --- a/drivers/gpu/drm/i915/i915_priolist_types.h +++ b/drivers/gpu/drm/i915/i915_priolist_types.h @@ -20,9 +20,6 @@ enum { /* A preemptive pulse used to monitor the health of each engine */ I915_PRIORITY_HEARTBEAT, - /* Interactive workload, scheduled for immediate pageflipping */ - I915_PRIORITY_DISPLAY, - __I915_PRIORITY_KERNEL__ }; -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:43 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:43 +0100 Subject: [Intel-gfx] [PATCH 03/28] drm/i915/selftests: Teach hang-self to target only itself In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-3-chris@chris-wilson.co.uk> We have a test case to exercise resetting an engine while the other engines are busy, all the TEST_SELF adds on top is that the target engine also has background activity. In this case it is useful to first test resetting the engine while there is background activity, as a separate flag from exercising all others. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 035f363fb0f8..2af66f8ffbd2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -805,10 +805,10 @@ static int __igt_reset_engines(struct intel_gt *gt, threads[tmp].resets = i915_reset_engine_count(global, other); - if (!(flags & TEST_OTHERS)) + if (other == engine && !(flags & TEST_SELF)) continue; - if (other == engine && !(flags & TEST_SELF)) + if (other != engine && !(flags & TEST_OTHERS)) continue; threads[tmp].engine = other; @@ -999,7 +999,7 @@ static int igt_reset_engines(void *arg) }, { "self-priority", - TEST_OTHERS | TEST_ACTIVE | TEST_PRIORITY | TEST_SELF, + TEST_ACTIVE | TEST_PRIORITY | TEST_SELF, }, { } }; -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:56 +0100 Subject: [Intel-gfx] [PATCH 16/28] drm/i915: Unpeel awaits on a proxy fence In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-16-chris@chris-wilson.co.uk> If the real target for a proxy fence is known at the time we are attaching our awaits, use the real target in preference to hooking up to the proxy. If use the real target instead, we can optimize the awaits, e.g. if it along the same engine, we can order the submission and avoid the wait-for-completion. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_request.c | 155 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_scheduler.c | 41 +++++++ drivers/gpu/drm/i915/i915_scheduler.h | 3 + 3 files changed, 199 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..f04f91b4d879 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -24,6 +24,7 @@ #include <linux/dma-fence-array.h> #include <linux/dma-fence-chain.h> +#include <linux/dma-fence-proxy.h> #include <linux/irq_work.h> #include <linux/prefetch.h> #include <linux/sched.h> @@ -461,6 +462,7 @@ static bool fatal_error(int error) case 0: /* not an error! */ case -EAGAIN: /* innocent victim of a GT reset (__i915_request_reset) */ case -ETIMEDOUT: /* waiting for Godot (timer_i915_sw_fence_wake) */ + case -EDEADLK: /* cyclic fence lockup (await_proxy) */ return false; default: return true; @@ -1241,6 +1243,136 @@ i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) return err; } +struct await_proxy { + struct wait_queue_entry base; + struct i915_request *request; + struct dma_fence *fence; + struct timer_list timer; + struct work_struct work; + int (*attach)(struct await_proxy *ap); + void *data; +}; + +static void await_proxy_work(struct work_struct *work) +{ + struct await_proxy *ap = container_of(work, typeof(*ap), work); + struct i915_request *rq = ap->request; + + del_timer_sync(&ap->timer); + + if (ap->fence) { + int err = 0; + + /* + * If the fence is external, we impose a 10s timeout. + * However, if the fence is internal, we skip a timeout in + * the belief that all fences are in-order (DAG, no cycles) + * and we can enforce forward progress by reset the GPU if + * necessary. A future fence, provided userspace, can trivially + * generate a cycle in the dependency graph, and so cause + * that entire cycle to become deadlocked and for no forward + * progress to either be made, and the driver being kept + * eternally awake. + */ + if (dma_fence_is_i915(ap->fence) && + !i915_sched_node_verify_dag(&rq->sched, + &to_request(ap->fence)->sched)) + err = -EDEADLK; + + if (!err) { + mutex_lock(&rq->context->timeline->mutex); + err = ap->attach(ap); + mutex_unlock(&rq->context->timeline->mutex); + } + + /* Don't flag an error for co-dependent scheduling */ + if (err == -EDEADLK) { + struct i915_sched_node *waiter = + &to_request(ap->fence)->sched; + struct i915_dependency *p; + + for_each_waiter(p, rq) { + if (p->waiter == waiter && + p->flags & I915_DEPENDENCY_WEAK) { + err = 0; + break; + } + } + } + + if (err < 0) + i915_sw_fence_set_error_once(&rq->submit, err); + } + + i915_sw_fence_complete(&rq->submit); + + dma_fence_put(ap->fence); + kfree(ap); +} + +static int +await_proxy_wake(struct wait_queue_entry *entry, + unsigned int mode, + int flags, + void *fence) +{ + struct await_proxy *ap = container_of(entry, typeof(*ap), base); + + ap->fence = dma_fence_get(fence); + schedule_work(&ap->work); + + return 0; +} + +static void +await_proxy_timer(struct timer_list *t) +{ + struct await_proxy *ap = container_of(t, typeof(*ap), timer); + + if (dma_fence_remove_proxy_listener(ap->base.private, &ap->base)) { + struct i915_request *rq = ap->request; + + pr_notice("Asynchronous wait on unset proxy fence by %s:%s:%llx timed out\n", + rq->fence.ops->get_driver_name(&rq->fence), + rq->fence.ops->get_timeline_name(&rq->fence), + rq->fence.seqno); + i915_sw_fence_set_error_once(&rq->submit, -ETIMEDOUT); + + schedule_work(&ap->work); + } +} + +static int +__i915_request_await_proxy(struct i915_request *rq, + struct dma_fence *fence, + unsigned long timeout, + int (*attach)(struct await_proxy *ap), + void *data) +{ + struct await_proxy *ap; + + ap = kzalloc(sizeof(*ap), I915_FENCE_GFP); + if (!ap) + return -ENOMEM; + + i915_sw_fence_await(&rq->submit); + mark_external(rq); + + ap->base.private = fence; + ap->base.func = await_proxy_wake; + ap->request = rq; + INIT_WORK(&ap->work, await_proxy_work); + ap->attach = attach; + ap->data = data; + + timer_setup(&ap->timer, await_proxy_timer, 0); + if (timeout) + mod_timer(&ap->timer, round_jiffies_up(jiffies + timeout)); + + dma_fence_add_proxy_listener(fence, &ap->base); + return 0; +} + int i915_request_await_execution(struct i915_request *rq, struct dma_fence *fence, @@ -1339,6 +1471,24 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from) return 0; } +static int await_proxy(struct await_proxy *ap) +{ + return i915_request_await_dma_fence(ap->request, ap->fence); +} + +static int +i915_request_await_proxy(struct i915_request *rq, struct dma_fence *fence) +{ + /* + * Wait until we know the real fence so that can optimise the + * inter-fence synchronisation. + */ + return __i915_request_await_proxy(rq, fence, + i915_fence_context_timeout(rq->engine->i915, + fence->context), + await_proxy, NULL); +} + int i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) { @@ -1346,6 +1496,9 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) unsigned int nchild = 1; int ret; + /* Unpeel the proxy fence if the real target is already known */ + fence = dma_fence_proxy_get_real(fence); + /* * Note that if the fence-array was created in signal-on-any mode, * we should *not* decompose it into its individual fences. However, @@ -1385,6 +1538,8 @@ i915_request_await_dma_fence(struct i915_request *rq, struct dma_fence *fence) if (dma_fence_is_i915(fence)) ret = i915_request_await_request(rq, to_request(fence)); + else if (dma_fence_is_proxy(fence)) + ret = i915_request_await_proxy(rq, fence); else ret = i915_request_await_external(rq, fence); if (ret < 0) diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index cbb880b10c65..250832768279 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -469,6 +469,47 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node, return 0; } +bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, + struct i915_sched_node *signaler) +{ + struct i915_dependency *dep, *p; + struct i915_dependency stack; + bool result = false; + LIST_HEAD(dfs); + + if (list_empty(&waiter->waiters_list)) + return true; + + spin_lock_irq(&schedule_lock); + + stack.signaler = signaler; + list_add(&stack.dfs_link, &dfs); + + list_for_each_entry(dep, &dfs, dfs_link) { + struct i915_sched_node *node = dep->signaler; + + if (node_signaled(node)) + continue; + + list_for_each_entry(p, &node->signalers_list, signal_link) { + if (p->signaler == waiter) + goto out; + + if (list_empty(&p->dfs_link)) + list_add_tail(&p->dfs_link, &dfs); + } + } + + result = true; +out: + list_for_each_entry_safe(dep, p, &dfs, dfs_link) + INIT_LIST_HEAD(&dep->dfs_link); + + spin_unlock_irq(&schedule_lock); + + return result; +} + void i915_sched_node_fini(struct i915_sched_node *node) { struct i915_dependency *dep, *tmp; diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 6f0bf00fc569..13432add8929 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -28,6 +28,9 @@ void i915_sched_node_init(struct i915_sched_node *node); void i915_sched_node_reinit(struct i915_sched_node *node); +bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, + struct i915_sched_node *signal); + bool __i915_sched_node_add_dependency(struct i915_sched_node *node, struct i915_sched_node *signal, struct i915_dependency *dep, -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:04 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:04 +0100 Subject: [Intel-gfx] [PATCH 24/28] ipi-dag In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-24-chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_scheduler.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 320d3720ba34..4c189b81cc62 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -436,17 +436,17 @@ bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, struct i915_dependency *dep, *p; struct i915_dependency stack; bool result = false; - LIST_HEAD(dfs); + LIST_HEAD(ipi); if (list_empty(&waiter->waiters_list)) return true; - spin_lock_irq(&schedule_lock); + spin_lock_irq(&ipi_lock); stack.signaler = signaler; - list_add(&stack.dfs_link, &dfs); + list_add(&stack.ipi_link, &ipi); - list_for_each_entry(dep, &dfs, dfs_link) { + list_for_each_entry(dep, &ipi, ipi_link) { struct i915_sched_node *node = dep->signaler; if (node_signaled(node)) @@ -456,17 +456,17 @@ bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, if (p->signaler == waiter) goto out; - if (list_empty(&p->dfs_link)) - list_add_tail(&p->dfs_link, &dfs); + if (list_empty(&p->ipi_link)) + list_add_tail(&p->ipi_link, &ipi); } } result = true; out: - list_for_each_entry_safe(dep, p, &dfs, dfs_link) - INIT_LIST_HEAD(&dep->dfs_link); + list_for_each_entry_safe(dep, p, &ipi, ipi_link) + INIT_LIST_HEAD(&dep->ipi_link); - spin_unlock_irq(&schedule_lock); + spin_unlock_irq(&ipi_lock); return result; } -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:59 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:59 +0100 Subject: [Intel-gfx] [PATCH 19/28] drm/i915: Remove I915_USER_PRIORITY_SHIFT In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-19-chris@chris-wilson.co.uk> As we do not have any internal priority levels, the priority can be set directed from the user values. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/display/intel_display.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +-- .../i915/gem/selftests/i915_gem_object_blt.c | 4 +- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 6 +-- drivers/gpu/drm/i915/gt/selftest_lrc.c | 44 +++++++------------ drivers/gpu/drm/i915/i915_priolist_types.h | 3 -- drivers/gpu/drm/i915/i915_scheduler.c | 1 - 7 files changed, 23 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b16aca0fe5f0..511555d444e5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15890,9 +15890,7 @@ static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY }; i915_gem_object_wait_priority(obj, 0, &attr); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index f5d59d18cd5b..ef76dff0e255 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -712,7 +712,7 @@ __create_context(struct drm_i915_private *i915) kref_init(&ctx->ref); ctx->i915 = i915; - ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_NORMAL); + ctx->sched.priority = I915_PRIORITY_NORMAL; mutex_init(&ctx->mutex); spin_lock_init(&ctx->stale.lock); @@ -1999,7 +1999,7 @@ static int set_priority(struct i915_gem_context *ctx, !capable(CAP_SYS_NICE)) return -EPERM; - ctx->sched.priority = I915_USER_PRIORITY(priority); + ctx->sched.priority = priority; context_apply_all(ctx, __apply_priority, ctx); return 0; @@ -2502,7 +2502,7 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, case I915_CONTEXT_PARAM_PRIORITY: args->size = 0; - args->value = ctx->sched.priority >> I915_USER_PRIORITY_SHIFT; + args->value = ctx->sched.priority; break; case I915_CONTEXT_PARAM_SSEU: diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c index 23b6e11bbc3e..c4c04fb97d14 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c @@ -220,7 +220,7 @@ static int igt_fill_blt_thread(void *arg) return PTR_ERR(ctx); prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng); - ctx->sched.priority = I915_USER_PRIORITY(prio); + ctx->sched.priority = prio; } ce = i915_gem_context_get_engine(ctx, 0); @@ -338,7 +338,7 @@ static int igt_copy_blt_thread(void *arg) return PTR_ERR(ctx); prio = i915_prandom_u32_max_state(I915_PRIORITY_MAX, prng); - ctx->sched.priority = I915_USER_PRIORITY(prio); + ctx->sched.priority = prio; } ce = i915_gem_context_get_engine(ctx, 0); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index eecf666c772d..ee002eb796cb 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -57,9 +57,7 @@ static void show_heartbeat(const struct i915_request *rq, static void heartbeat(struct work_struct *wrk) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MIN), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MIN }; struct intel_engine_cs *engine = container_of(wrk, typeof(*engine), heartbeat.work.work); struct intel_context *ce = engine->kernel_context; @@ -99,7 +97,7 @@ static void heartbeat(struct work_struct *wrk) */ attr.priority = 0; if (rq->sched.attr.priority >= attr.priority) - attr.priority |= I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT); + attr.priority = I915_PRIORITY_HEARTBEAT; if (rq->sched.attr.priority >= attr.priority) attr.priority = I915_PRIORITY_BARRIER; diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index a0248c47d7bd..15aaa1bf8943 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -360,7 +360,7 @@ static int live_unlite_switch(void *arg) static int live_unlite_preempt(void *arg) { - return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); + return live_unlite_restore(arg, I915_PRIORITY_MAX); } static int live_pin_rewind(void *arg) @@ -1193,9 +1193,7 @@ static int live_timeslice_queue(void *arg) goto err_pin; for_each_engine(engine, gt, id) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct i915_request *rq, *nop; if (!intel_engine_has_preemption(engine)) @@ -1410,14 +1408,12 @@ static int live_busywait_preempt(void *arg) ctx_hi = kernel_context(gt->i915); if (!ctx_hi) return -ENOMEM; - ctx_hi->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY); + ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY; ctx_lo = kernel_context(gt->i915); if (!ctx_lo) goto err_ctx_hi; - ctx_lo->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY); + ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY; obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); if (IS_ERR(obj)) { @@ -1620,14 +1616,12 @@ static int live_preempt(void *arg) ctx_hi = kernel_context(gt->i915); if (!ctx_hi) goto err_spin_lo; - ctx_hi->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY); + ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY; ctx_lo = kernel_context(gt->i915); if (!ctx_lo) goto err_ctx_hi; - ctx_lo->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY); + ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY; for_each_engine(engine, gt, id) { struct igt_live_test t; @@ -1723,7 +1717,7 @@ static int live_late_preempt(void *arg) goto err_ctx_hi; /* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */ - ctx_lo->sched.priority = I915_USER_PRIORITY(1); + ctx_lo->sched.priority = 1; for_each_engine(engine, gt, id) { struct igt_live_test t; @@ -1764,7 +1758,7 @@ static int live_late_preempt(void *arg) goto err_wedged; } - attr.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX); + attr.priority = I915_PRIORITY_MAX; engine->schedule(rq, &attr); if (!igt_wait_for_spinner(&spin_hi, rq)) { @@ -1848,7 +1842,7 @@ static int live_nopreempt(void *arg) return -ENOMEM; if (preempt_client_init(gt, &b)) goto err_client_a; - b.ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX); + b.ctx->sched.priority = I915_PRIORITY_MAX; for_each_engine(engine, gt, id) { struct i915_request *rq_a, *rq_b; @@ -2241,11 +2235,9 @@ static int live_preempt_cancel(void *arg) static int live_suppress_self_preempt(void *arg) { + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct intel_gt *gt = arg; struct intel_engine_cs *engine; - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX) - }; struct preempt_client a, b; enum intel_engine_id id; int err = -ENOMEM; @@ -2382,9 +2374,7 @@ static int live_chain_preempt(void *arg) goto err_client_hi; for_each_engine(engine, gt, id) { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(I915_PRIORITY_MAX), - }; + struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct igt_live_test t; struct i915_request *rq; int ring_size, count, i; @@ -2640,9 +2630,7 @@ static int live_preempt_gang(void *arg) return -EIO; do { - struct i915_sched_attr attr = { - .priority = I915_USER_PRIORITY(prio++), - }; + struct i915_sched_attr attr = { .priority = prio++ }; err = create_gang(engine, &rq); if (err) @@ -2679,7 +2667,7 @@ static int live_preempt_gang(void *arg) drm_info_printer(engine->i915->drm.dev); pr_err("Failed to flush chain of %d requests, at %d\n", - prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT); + prio, rq_prio(rq)); intel_engine_dump(engine, &p, "%s\n", engine->name); @@ -3053,14 +3041,12 @@ static int live_preempt_timeout(void *arg) ctx_hi = kernel_context(gt->i915); if (!ctx_hi) goto err_spin_lo; - ctx_hi->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MAX_USER_PRIORITY); + ctx_hi->sched.priority = I915_CONTEXT_MAX_USER_PRIORITY; ctx_lo = kernel_context(gt->i915); if (!ctx_lo) goto err_ctx_hi; - ctx_lo->sched.priority = - I915_USER_PRIORITY(I915_CONTEXT_MIN_USER_PRIORITY); + ctx_lo->sched.priority = I915_CONTEXT_MIN_USER_PRIORITY; for_each_engine(engine, gt, id) { unsigned long saved_timeout; diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h index 9a7657bb002e..bc2fa84f98a8 100644 --- a/drivers/gpu/drm/i915/i915_priolist_types.h +++ b/drivers/gpu/drm/i915/i915_priolist_types.h @@ -24,9 +24,6 @@ enum { I915_PRIORITY_DISPLAY, }; -#define I915_USER_PRIORITY_SHIFT 0 -#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) - /* Smallest priority value that cannot be bumped. */ #define I915_PRIORITY_INVALID (INT_MIN) diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 7945cc161a12..7246ffbb3e33 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -71,7 +71,6 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) lockdep_assert_held(&engine->active.lock); assert_priolists(execlists); - prio >>= I915_USER_PRIORITY_SHIFT; if (unlikely(execlists->no_priolist)) prio = I915_PRIORITY_NORMAL; -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:58 +0100 Subject: [Intel-gfx] [PATCH 18/28] drm/i915: Strip out internal priorities In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-18-chris@chris-wilson.co.uk> Since we are not using any internal priority levels, and in the next few patches will introduce a new index for which the optimisation is not so lear cut, discard the small table within the priolist. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 22 ++------ drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 - .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +-- drivers/gpu/drm/i915/i915_priolist_types.h | 8 +-- drivers/gpu/drm/i915/i915_scheduler.c | 51 +++---------------- drivers/gpu/drm/i915/i915_scheduler.h | 18 ++----- 7 files changed, 21 insertions(+), 88 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index f67ad937eefb..eecf666c772d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -97,7 +97,7 @@ static void heartbeat(struct work_struct *wrk) * low latency and no jitter] the chance to naturally * complete before being preempted. */ - attr.priority = I915_PRIORITY_MASK; + attr.priority = 0; if (rq->sched.attr.priority >= attr.priority) attr.priority |= I915_USER_PRIORITY(I915_PRIORITY_HEARTBEAT); if (rq->sched.attr.priority >= attr.priority) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 5f5ac05ccbe4..0ca3604ab846 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -434,22 +434,13 @@ static int effective_prio(const struct i915_request *rq) static int queue_prio(const struct intel_engine_execlists *execlists) { - struct i915_priolist *p; struct rb_node *rb; rb = rb_first_cached(&execlists->queue); if (!rb) return INT_MIN; - /* - * As the priolist[] are inverted, with the highest priority in [0], - * we have to flip the index value to become priority. - */ - p = to_priolist(rb); - if (!I915_USER_PRIORITY_SHIFT) - return p->priority; - - return ((p->priority + 1) << I915_USER_PRIORITY_SHIFT) - ffs(p->used); + return to_priolist(rb)->priority; } static inline bool need_preempt(const struct intel_engine_cs *engine, @@ -2324,9 +2315,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); struct i915_request *rq, *rn; - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { bool merge = true; /* @@ -4323,9 +4313,8 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) /* Flush the queued requests to the timeline list (for retiring). */ while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { mark_eio(rq); __i915_request_submit(rq); } @@ -5337,7 +5326,7 @@ static int __execlists_context_alloc(struct intel_context *ce, static struct list_head *virtual_queue(struct virtual_engine *ve) { - return &ve->base.execlists.default_priolist.requests[0]; + return &ve->base.execlists.default_priolist.requests; } static void virtual_context_destroy(struct kref *kref) @@ -5896,9 +5885,8 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine, count = 0; for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { struct i915_priolist *p = rb_entry(rb, typeof(*p), node); - int i; - priolist_for_each_request(rq, p, i) { + priolist_for_each_request(rq, p) { if (count++ < max - 1) show_request(m, rq, "\t\tQ "); else diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index a8bcea8aa1b4..a0248c47d7bd 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -964,7 +964,6 @@ create_rewinder(struct intel_context *ce, intel_ring_advance(rq, cs); - rq->sched.attr.priority = I915_PRIORITY_MASK; err = 0; err: i915_request_get(rq); @@ -5059,7 +5058,6 @@ create_timestamp(struct intel_context *ce, void *slot, int idx) intel_ring_advance(rq, cs); - rq->sched.attr.priority = I915_PRIORITY_MASK; err = 0; err: i915_request_get(rq); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 94eb63f309ce..0c42e8b0c211 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -312,9 +312,8 @@ static void __guc_dequeue(struct intel_engine_cs *engine) while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); struct i915_request *rq, *rn; - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { if (last && rq->context != last->context) { if (port == last_port) goto done; @@ -463,9 +462,8 @@ static void guc_reset_cancel(struct intel_engine_cs *engine) /* Flush the queued requests to the timeline list (for retiring). */ while ((rb = rb_first_cached(&execlists->queue))) { struct i915_priolist *p = to_priolist(rb); - int i; - priolist_for_each_request_consume(rq, rn, p, i) { + priolist_for_each_request_consume(rq, rn, p) { list_del_init(&rq->sched.link); __i915_request_submit(rq); dma_fence_set_error(&rq->fence, -EIO); diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h index 8aa7866ec6b6..9a7657bb002e 100644 --- a/drivers/gpu/drm/i915/i915_priolist_types.h +++ b/drivers/gpu/drm/i915/i915_priolist_types.h @@ -27,11 +27,8 @@ enum { #define I915_USER_PRIORITY_SHIFT 0 #define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) -#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT) -#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1) - /* Smallest priority value that cannot be bumped. */ -#define I915_PRIORITY_INVALID (INT_MIN | (u8)I915_PRIORITY_MASK) +#define I915_PRIORITY_INVALID (INT_MIN) /* * Requests containing performance queries must not be preempted by @@ -45,9 +42,8 @@ enum { #define I915_PRIORITY_BARRIER (I915_PRIORITY_UNPREEMPTABLE - 1) struct i915_priolist { - struct list_head requests[I915_PRIORITY_COUNT]; + struct list_head requests; struct rb_node node; - unsigned long used; int priority; }; diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 250832768279..7945cc161a12 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -43,7 +43,7 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb) static void assert_priolists(struct intel_engine_execlists * const execlists) { struct rb_node *rb; - long last_prio, i; + long last_prio; if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) return; @@ -57,14 +57,6 @@ static void assert_priolists(struct intel_engine_execlists * const execlists) GEM_BUG_ON(p->priority > last_prio); last_prio = p->priority; - - GEM_BUG_ON(!p->used); - for (i = 0; i < ARRAY_SIZE(p->requests); i++) { - if (list_empty(&p->requests[i])) - continue; - - GEM_BUG_ON(!(p->used & BIT(i))); - } } } @@ -75,13 +67,10 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) struct i915_priolist *p; struct rb_node **parent, *rb; bool first = true; - int idx, i; lockdep_assert_held(&engine->active.lock); assert_priolists(execlists); - /* buckets sorted from highest [in slot 0] to lowest priority */ - idx = I915_PRIORITY_COUNT - (prio & I915_PRIORITY_MASK) - 1; prio >>= I915_USER_PRIORITY_SHIFT; if (unlikely(execlists->no_priolist)) prio = I915_PRIORITY_NORMAL; @@ -99,7 +88,7 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) parent = &rb->rb_right; first = false; } else { - goto out; + return &p->requests; } } @@ -125,15 +114,12 @@ i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio) } p->priority = prio; - for (i = 0; i < ARRAY_SIZE(p->requests); i++) - INIT_LIST_HEAD(&p->requests[i]); + INIT_LIST_HEAD(&p->requests); + rb_link_node(&p->node, rb, parent); rb_insert_color_cached(&p->node, &execlists->queue, first); - p->used = 0; -out: - p->used |= BIT(idx); - return &p->requests[idx]; + return &p->requests; } void __i915_priolist_free(struct i915_priolist *p) @@ -363,30 +349,6 @@ void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr) spin_unlock_irq(&schedule_lock); } -static void __bump_priority(struct i915_sched_node *node, unsigned int bump) -{ - struct i915_sched_attr attr = node->attr; - - if (attr.priority & bump) - return; - - attr.priority |= bump; - __i915_schedule(node, &attr); -} - -void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump) -{ - unsigned long flags; - - GEM_BUG_ON(bump & ~I915_PRIORITY_MASK); - if (READ_ONCE(rq->sched.attr.priority) & bump) - return; - - spin_lock_irqsave(&schedule_lock, flags); - __bump_priority(&rq->sched, bump); - spin_unlock_irqrestore(&schedule_lock, flags); -} - void i915_sched_node_init(struct i915_sched_node *node) { INIT_LIST_HEAD(&node->signalers_list); @@ -570,8 +532,7 @@ int __init i915_global_scheduler_init(void) if (!global.slab_dependencies) return -ENOMEM; - global.slab_priorities = KMEM_CACHE(i915_priolist, - SLAB_HWCACHE_ALIGN); + global.slab_priorities = KMEM_CACHE(i915_priolist, 0); if (!global.slab_priorities) goto err_priorities; diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 13432add8929..1b3c1e1a6ec5 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -13,17 +13,11 @@ #include "i915_scheduler_types.h" -#define priolist_for_each_request(it, plist, idx) \ - for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \ - list_for_each_entry(it, &(plist)->requests[idx], sched.link) - -#define priolist_for_each_request_consume(it, n, plist, idx) \ - for (; \ - (plist)->used ? (idx = __ffs((plist)->used)), 1 : 0; \ - (plist)->used &= ~BIT(idx)) \ - list_for_each_entry_safe(it, n, \ - &(plist)->requests[idx], \ - sched.link) +#define priolist_for_each_request(it, plist) \ + list_for_each_entry(it, &(plist)->requests, sched.link) + +#define priolist_for_each_request_consume(it, n, plist) \ + list_for_each_entry_safe(it, n, &(plist)->requests, sched.link) void i915_sched_node_init(struct i915_sched_node *node); void i915_sched_node_reinit(struct i915_sched_node *node); @@ -45,8 +39,6 @@ void i915_sched_node_fini(struct i915_sched_node *node); void i915_schedule(struct i915_request *request, const struct i915_sched_attr *attr); -void i915_schedule_bump_priority(struct i915_request *rq, unsigned int bump); - struct list_head * i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio); -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:07 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:07 +0100 Subject: [Intel-gfx] [PATCH 27/28] drm/i915/gt: Specify a deadline for the heartbeat In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-27-chris@chris-wilson.co.uk> As we know when we expect the heartbeat to be checked for completion, pass this information along as its deadline. We still do not complain if the deadline is missed, at least until we have tried a few times, but it will allow for quicker hang detection on systems where deadlines are adhered to. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index ba778c7b5d2b..4e5b8146bee0 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,16 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void set_heartbeat_deadline(struct intel_engine_cs *engine, + struct i915_request *rq) +{ + unsigned long interval; + + interval = READ_ONCE(engine->props.heartbeat_interval_ms); + if (interval) + i915_request_set_deadline(rq, ktime_get() + (interval << 20)); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -103,6 +113,8 @@ static void heartbeat(struct work_struct *wrk) local_bh_disable(); i915_request_set_priority(rq, attr.priority); + if (attr.priority == I915_PRIORITY_BARRIER) + i915_request_set_deadline(rq, 0); local_bh_enable(); } else { if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) @@ -133,6 +145,7 @@ static void heartbeat(struct work_struct *wrk) __i915_request_commit(rq); __i915_request_queue(rq, &attr); + set_heartbeat_deadline(engine, rq); unlock: mutex_unlock(&ce->timeline->mutex); -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:49 +0100 Subject: [Intel-gfx] [PATCH 09/28] drm/i915: Add list_for_each_entry_safe_continue_reverse In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-9-chris@chris-wilson.co.uk> One more list iterator variant, for when we want to unwind from inside one list iterator with the intention of restarting from the current entry as the new head of the list. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/i915_utils.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h index 03a73d2bd50d..6ebccdd12d4c 100644 --- a/drivers/gpu/drm/i915/i915_utils.h +++ b/drivers/gpu/drm/i915/i915_utils.h @@ -266,6 +266,12 @@ static inline int list_is_last_rcu(const struct list_head *list, return READ_ONCE(list->next) == head; } +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) + /* * Wait until the work is finally complete, even if it tries to postpone * by requeueing itself. Note, that if the worker never cancels itself, -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:05 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:05 +0100 Subject: [Intel-gfx] [PATCH 25/28] drm/i915/gt: Check for a completed last request once In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-25-chris@chris-wilson.co.uk> Pull the repeated check for the last active request being completed to a single spot, when deciding whether or not execlist preemption is required. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 3fb1b4c67adb..f9c095c79874 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2132,12 +2132,11 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * completed and barf. */ if ((last = *active)) { - if (need_preempt(engine, last, ve)) { - if (i915_request_completed(last)) { - tasklet_hi_schedule(&execlists->tasklet); - return; - } + if (i915_request_completed(last) && + !list_is_last(&last->sched.link, &engine->active.requests)) + return; + if (need_preempt(engine, last, ve)) { ENGINE_TRACE(engine, "preempting last=%llx:%lld, prio=%d, hint=%d\n", last->fence.context, @@ -2165,11 +2164,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) last = NULL; } else if (need_timeslice(engine, last, ve) && timeslice_expired(execlists, last)) { - if (i915_request_completed(last)) { - tasklet_hi_schedule(&execlists->tasklet); - return; - } - ENGINE_TRACE(engine, "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n", last->fence.context, -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:02 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:02 +0100 Subject: [Intel-gfx] [PATCH 22/28] drm/i915: Teach the i915_dependency to use a double-lock In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-22-chris@chris-wilson.co.uk> Currently, we construct and teardown the i915_dependency chains using a global spinlock. As the lists are entirely local, it should be possible to use an double-lock with an explicit nesting [signaler -> waiter, always] and so avoid the costly convenience of a global spinlock. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +-- drivers/gpu/drm/i915/i915_request.c | 2 +- drivers/gpu/drm/i915/i915_scheduler.c | 44 +++++++++++++-------- drivers/gpu/drm/i915/i915_scheduler.h | 2 +- drivers/gpu/drm/i915/i915_scheduler_types.h | 1 + 5 files changed, 34 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index af6f78eca9ad..3fb1b4c67adb 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1884,7 +1884,7 @@ static void defer_request(struct i915_request *rq, struct list_head * const pl) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); - if (p->flags & I915_DEPENDENCY_WEAK) + if (!p->waiter || p->flags & I915_DEPENDENCY_WEAK) continue; /* Leave semaphores spinning on the other engines */ @@ -2726,7 +2726,7 @@ static void __execlists_hold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); - if (p->flags & I915_DEPENDENCY_WEAK) + if (!p->waiter || p->flags & I915_DEPENDENCY_WEAK) continue; /* Leave semaphores spinning on the other engines */ @@ -2853,7 +2853,7 @@ static void __execlists_unhold(struct i915_request *rq) struct i915_request *w = container_of(p->waiter, typeof(*w), sched); - if (p->flags & I915_DEPENDENCY_WEAK) + if (!p->waiter || p->flags & I915_DEPENDENCY_WEAK) continue; /* Propagate any change in error status */ diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 6c602b29026d..a09fe74bb818 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -338,7 +338,7 @@ bool i915_request_retire(struct i915_request *rq) intel_context_unpin(rq->context); free_capture_list(rq); - i915_sched_node_fini(&rq->sched); + i915_sched_node_retire(&rq->sched); i915_request_put(rq); return true; diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 9437e9d1d445..f9cd8baaefcd 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -353,6 +353,8 @@ void i915_request_set_priority(struct i915_request *rq, int prio) void i915_sched_node_init(struct i915_sched_node *node) { + spin_lock_init(&node->lock); + INIT_LIST_HEAD(&node->signalers_list); INIT_LIST_HEAD(&node->waiters_list); INIT_LIST_HEAD(&node->link); @@ -390,7 +392,8 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node, { bool ret = false; - spin_lock_irq(&schedule_lock); + /* The signal->lock is always the outer lock in this double-lock. */ + spin_lock_irq(&signal->lock); if (!node_signaled(signal)) { INIT_LIST_HEAD(&dep->dfs_link); @@ -399,15 +402,17 @@ bool __i915_sched_node_add_dependency(struct i915_sched_node *node, dep->flags = flags; /* All set, now publish. Beware the lockless walkers. */ + spin_lock_nested(&node->lock, SINGLE_DEPTH_NESTING); list_add_rcu(&dep->signal_link, &node->signalers_list); list_add_rcu(&dep->wait_link, &signal->waiters_list); + spin_unlock(&node->lock); /* Propagate the chains */ node->flags |= signal->flags; ret = true; } - spin_unlock_irq(&schedule_lock); + spin_unlock_irq(&signal->lock); return ret; } @@ -474,39 +479,46 @@ bool i915_sched_node_verify_dag(struct i915_sched_node *waiter, return result; } -void i915_sched_node_fini(struct i915_sched_node *node) +void i915_sched_node_retire(struct i915_sched_node *node) { struct i915_dependency *dep, *tmp; - spin_lock_irq(&schedule_lock); + spin_lock_irq(&node->lock); /* * Everyone we depended upon (the fences we wait to be signaled) * should retire before us and remove themselves from our list. * However, retirement is run independently on each timeline and - * so we may be called out-of-order. + * so we may be called out-of-order. As we need to avoid taking + * the signaler's lock, just mark up our completion and be wary + * in traversing the signalers->waiters_list. */ - list_for_each_entry_safe(dep, tmp, &node->signalers_list, signal_link) { - GEM_BUG_ON(!list_empty(&dep->dfs_link)); - - list_del_rcu(&dep->wait_link); - if (dep->flags & I915_DEPENDENCY_ALLOC) - i915_dependency_free(dep); + list_for_each_entry(dep, &node->signalers_list, signal_link) { + GEM_BUG_ON(dep->waiter != node); + WRITE_ONCE(dep->waiter, NULL); } - INIT_LIST_HEAD(&node->signalers_list); + INIT_LIST_HEAD_RCU(&node->signalers_list); /* Remove ourselves from everyone who depends upon us */ list_for_each_entry_safe(dep, tmp, &node->waiters_list, wait_link) { + struct i915_sched_node *w; + GEM_BUG_ON(dep->signaler != node); - GEM_BUG_ON(!list_empty(&dep->dfs_link)); - list_del_rcu(&dep->signal_link); + w = READ_ONCE(dep->waiter); + if (w) { + spin_lock_nested(&w->lock, SINGLE_DEPTH_NESTING); + if (READ_ONCE(dep->waiter)) + list_del_rcu(&dep->signal_link); + spin_unlock(&w->lock); + } + if (dep->flags & I915_DEPENDENCY_ALLOC) i915_dependency_free(dep); } - INIT_LIST_HEAD(&node->waiters_list); + INIT_LIST_HEAD_RCU(&node->waiters_list); - spin_unlock_irq(&schedule_lock); + spin_unlock_irq(&node->lock); } static void i915_global_scheduler_shrink(void) diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index b8696edef446..b26a13ef6feb 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -34,7 +34,7 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node, struct i915_sched_node *signal, unsigned long flags); -void i915_sched_node_fini(struct i915_sched_node *node); +void i915_sched_node_retire(struct i915_sched_node *node); void i915_request_set_priority(struct i915_request *request, int prio); diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h index 343ed44d5ed4..3246430eb1c1 100644 --- a/drivers/gpu/drm/i915/i915_scheduler_types.h +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h @@ -60,6 +60,7 @@ struct i915_sched_attr { * others. */ struct i915_sched_node { + spinlock_t lock; /* protect the lists */ struct list_head signalers_list; /* those before us, we depend upon */ struct list_head waiters_list; /* those after us, they depend upon us */ struct list_head link; -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:53 +0100 Subject: [Intel-gfx] [PATCH 13/28] drm/i915/gem: Add all GPU reloc awaits/signals en masse In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-13-chris@chris-wilson.co.uk> Asynchronous waits and signaling form a traditional semaphore with all the usual ordering problems with taking multiple locks. If we want to add more than one wait on a shared resource by the GPU, we must ensure that all the associated timelines are advanced atomically, ergo we must lock all the timelines en masse. Testcase: igt/gem_exec_reloc/basic-concurrent16 Fixes: 0e97fbb08055 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf") References: https://gitlab.freedesktop.org/drm/intel/-/issues/1889 Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 114 ++++++++++++------ .../i915/gem/selftests/i915_gem_execbuffer.c | 24 ++-- 2 files changed, 93 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 83cea2ea7c61..8f3c1cf5af31 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -259,7 +259,6 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; - struct i915_vma *target; struct i915_request *rq; struct i915_vma *rq_vma; u32 *rq_cmd; @@ -924,7 +923,6 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->target = NULL; } #define RELOC_TAIL 4 @@ -1038,26 +1036,6 @@ static void reloc_gpu_flush(struct reloc_cache *cache) i915_request_add(rq); } -static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) -{ - struct drm_i915_gem_object *obj = vma->obj; - int err; - - i915_vma_lock(vma); - - if (obj->cache_dirty & ~obj->cache_coherent) - i915_gem_clflush_object(obj, 0); - obj->write_domain = 0; - - err = i915_request_await_object(rq, vma->obj, true); - if (err == 0) - err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - - i915_vma_unlock(vma); - - return err; -} - static int __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) { @@ -1147,24 +1125,12 @@ __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine) return err; } -static u32 *reloc_batch_grow(struct i915_execbuffer *eb, - struct i915_vma *vma, - unsigned int len) +static u32 *reloc_batch_grow(struct i915_execbuffer *eb, unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; int err; - if (vma != cache->target) { - err = reloc_move_to_gpu(cache->rq, vma); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); - return ERR_PTR(err); - } - - cache->target = vma; - } - if (unlikely(cache->rq_size + len > PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { err = reloc_gpu_chain(cache); @@ -1210,7 +1176,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, else len = 3; - batch = reloc_batch_grow(eb, vma, len); + batch = reloc_batch_grow(eb, len); if (IS_ERR(batch)) return PTR_ERR(batch); @@ -1471,6 +1437,78 @@ static long eb_reloc_vma(struct i915_execbuffer *eb, struct eb_vma *ev, return required; } +static int reloc_move_to_gpu(struct reloc_cache *cache, struct eb_vma *ev) +{ + struct i915_request *rq = cache->rq; + struct i915_vma *vma = ev->vma; + struct drm_i915_gem_object *obj = vma->obj; + int err; + + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, 0); + + obj->write_domain = I915_GEM_DOMAIN_RENDER; + obj->read_domains = I915_GEM_DOMAIN_RENDER; + + err = i915_request_await_object(rq, obj, true); + if (err) + return err; + + err = __i915_vma_move_to_active(vma, rq); + if (err) + return err; + + dma_resv_add_excl_fence(vma->resv, &rq->fence); + + return 0; +} + +static int +lock_relocs(struct i915_execbuffer *eb) +{ + struct ww_acquire_ctx acquire; + struct eb_vma *ev; + int err = 0; + + ww_acquire_init(&acquire, &reservation_ww_class); + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + struct i915_vma *vma = ev->vma; + + err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); + if (err == -EDEADLK) { + struct eb_vma *unlock = ev, *en; + + list_for_each_entry_safe_continue_reverse(unlock, en, + &eb->relocs, + reloc_link) { + ww_mutex_unlock(&unlock->vma->resv->lock); + list_move_tail(&unlock->reloc_link, + &eb->relocs); + } + + GEM_BUG_ON(!list_is_first(&ev->reloc_link, + &eb->relocs)); + err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, + &acquire); + } + if (err) + break; + } + + ww_acquire_done(&acquire); + + list_for_each_entry_continue_reverse(ev, &eb->relocs, reloc_link) { + if (err == 0) + err = reloc_move_to_gpu(&eb->reloc_cache, ev); + ww_mutex_unlock(&ev->vma->resv->lock); + } + + ww_acquire_fini(&acquire); + + return err; +} + static bool reloc_can_use_engine(const struct intel_engine_cs *engine) { return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6); @@ -1499,6 +1537,10 @@ static int reloc_gpu(struct i915_execbuffer *eb) return err; GEM_BUG_ON(!eb->reloc_cache.rq); + err = lock_relocs(eb); + if (err) + goto out; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index faed6480a792..4f10b51f9a7e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -24,15 +24,15 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GENMASK_ULL(eb->reloc_cache.use_64bit_reloc ? 63 : 31, 0); const u32 *map = page_mask_bits(obj->mm.mapping); struct i915_request *rq; - struct i915_vma *vma; + struct eb_vma ev; int err; int i; - vma = i915_vma_instance(obj, eb->context->vm, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + ev.vma = i915_vma_instance(obj, eb->context->vm, NULL); + if (IS_ERR(ev.vma)) + return PTR_ERR(ev.vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + err = i915_vma_pin(ev.vma, 0, 0, PIN_USER | PIN_HIGH); if (err) return err; @@ -40,17 +40,22 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (err) goto unpin_vma; + list_add(&ev.reloc_link, &eb->relocs); + err = lock_relocs(eb); + if (err) + goto unpin_vma; + err = reloc_gpu_emit(&eb->reloc_cache); if (err) goto unpin_vma; /* 8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + err = __reloc_entry_gpu(eb, ev.vma, offsets[0] * sizeof(u32), 0); if (err) goto unpin_vma; /* !8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + err = __reloc_entry_gpu(eb, ev.vma, offsets[1] * sizeof(u32), 1); if (err) goto unpin_vma; @@ -62,7 +67,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + err = __reloc_entry_gpu(eb, ev.vma, offsets[2] * sizeof(u32), 2); if (err) goto unpin_vma; @@ -97,7 +102,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, put_rq: i915_request_put(rq); unpin_vma: - i915_vma_unpin(vma); + i915_vma_unpin(ev.vma); return err; } @@ -121,6 +126,7 @@ static int igt_gpu_reloc(void *arg) } for_each_uabi_engine(eb.engine, eb.i915) { + INIT_LIST_HEAD(&eb.relocs); reloc_cache_init(&eb.reloc_cache, eb.i915); memset(map, POISON_INUSE, 4096); -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:50 +0100 Subject: [Intel-gfx] [PATCH 10/28] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-10-chris@chris-wilson.co.uk> Over the next couple of patches, we will want to lock all the modified vma for relocation processing under a single ww_mutex. We neither want to have to include the vma that are skipped (due to no modifications required) nor do we want those to be marked as written too. So separate out the reloc validation into an early step, which we can use both to reject the execbuf before committing to making our changes, and to filter out the unmodified vma. This does introduce a second pass through the reloc[], but only if we need to emit relocations. v2: reuse the outer loop, not cut'n'paste. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 145 +++++++++++------- 1 file changed, 86 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 23db79b806db..01ab1e15a142 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -911,9 +911,9 @@ static void eb_destroy(const struct i915_execbuffer *eb) static inline u64 relocation_target(const struct drm_i915_gem_relocation_entry *reloc, - const struct i915_vma *target) + u64 target) { - return gen8_canonical_addr((int)reloc->delta + target->node.start); + return gen8_canonical_addr((int)reloc->delta + target); } static void reloc_cache_init(struct reloc_cache *cache, @@ -1292,26 +1292,11 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, return 0; } -static u64 -relocate_entry(struct i915_execbuffer *eb, - struct i915_vma *vma, - const struct drm_i915_gem_relocation_entry *reloc, - const struct i915_vma *target) -{ - u64 target_addr = relocation_target(reloc, target); - int err; - - err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); - if (err) - return err; - - return target->node.start | UPDATE; -} - -static u64 -eb_relocate_entry(struct i915_execbuffer *eb, - struct eb_vma *ev, - const struct drm_i915_gem_relocation_entry *reloc) +static int +eb_reloc_prepare(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc, + struct drm_i915_gem_relocation_entry __user *user) { struct drm_i915_private *i915 = eb->i915; struct eb_vma *target; @@ -1389,6 +1374,32 @@ eb_relocate_entry(struct i915_execbuffer *eb, return -EINVAL; } + return 1; +} + +static int +eb_reloc_entry(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc, + struct drm_i915_gem_relocation_entry __user *user) +{ + struct eb_vma *target; + u64 offset; + int err; + + /* we've already hold a reference to all valid objects */ + target = eb_get_vma(eb, reloc->target_handle); + if (unlikely(!target)) + return -ENOENT; + + /* + * If the relocation already has the right value in it, no + * more work needs to be done. + */ + offset = gen8_canonical_addr(target->vma->node.start); + if (offset == reloc->presumed_offset) + return 0; + /* * If we write into the object, we need to force the synchronisation * barrier, either with an asynchronous clflush or if we executed the @@ -1399,11 +1410,41 @@ eb_relocate_entry(struct i915_execbuffer *eb, */ ev->flags &= ~EXEC_OBJECT_ASYNC; - /* and update the user's relocation entry */ - return relocate_entry(eb, ev->vma, reloc, target->vma); + err = __reloc_entry_gpu(eb, ev->vma, reloc->offset, + relocation_target(reloc, offset)); + if (err) + return err; + + /* + * Note that reporting an error now + * leaves everything in an inconsistent + * state as we have *already* changed + * the relocation value inside the + * object. As we have not changed the + * reloc.presumed_offset or will not + * change the execobject.offset, on the + * call we may not rewrite the value + * inside the object, leaving it + * dangling and causing a GPU hang. Unless + * userspace dynamically rebuilds the + * relocations on each execbuf rather than + * presume a static tree. + * + * We did previously check if the relocations + * were writable (access_ok), an error now + * would be a strange race with mprotect, + * having already demonstrated that we + * can read from this userspace address. + */ + __put_user(offset, &user->presumed_offset); + return 0; } -static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) +static long eb_reloc_vma(struct i915_execbuffer *eb, struct eb_vma *ev, + int (*fn)(struct i915_execbuffer *eb, + struct eb_vma *ev, + const struct drm_i915_gem_relocation_entry *reloc, + struct drm_i915_gem_relocation_entry __user *user)) { #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; @@ -1411,6 +1452,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) struct drm_i915_gem_relocation_entry __user *urelocs = u64_to_user_ptr(entry->relocs_ptr); unsigned long remain = entry->relocation_count; + int required = 0; if (unlikely(remain > N_RELOC(ULONG_MAX))) return -EINVAL; @@ -1443,42 +1485,18 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) remain -= count; do { - u64 offset = eb_relocate_entry(eb, ev, r); + int ret; - if (likely(offset == 0)) { - } else if ((s64)offset < 0) { - return (int)offset; - } else { - /* - * Note that reporting an error now - * leaves everything in an inconsistent - * state as we have *already* changed - * the relocation value inside the - * object. As we have not changed the - * reloc.presumed_offset or will not - * change the execobject.offset, on the - * call we may not rewrite the value - * inside the object, leaving it - * dangling and causing a GPU hang. Unless - * userspace dynamically rebuilds the - * relocations on each execbuf rather than - * presume a static tree. - * - * We did previously check if the relocations - * were writable (access_ok), an error now - * would be a strange race with mprotect, - * having already demonstrated that we - * can read from this userspace address. - */ - offset = gen8_canonical_addr(offset & ~UPDATE); - __put_user(offset, - &urelocs[r - stack].presumed_offset); - } + ret = fn(eb, ev, r, &urelocs[r - stack]); + if (ret < 0) + return ret; + + required |= ret; } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); - return 0; + return required; } static int eb_relocate(struct i915_execbuffer *eb) @@ -1497,12 +1515,21 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { - struct eb_vma *ev; + struct eb_vma *ev, *en; int flush; + list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { + err = eb_reloc_vma(eb, ev, eb_reloc_prepare); + if (err < 0) + return err; + + if (err == 0) + list_del_init(&ev->reloc_link); + } + list_for_each_entry(ev, &eb->relocs, reloc_link) { - err = eb_relocate_vma(eb, ev); - if (err) + err = eb_reloc_vma(eb, ev, eb_reloc_entry); + if (err < 0) break; } -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:41 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation Message-ID: <20200607222108.14401-1-chris@chris-wilson.co.uk> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Sentinels are supposed to be last reqeusts in the elsp queue, not the only one, so adjust the assert accordingly. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d55a5e0466e5..db8a170b0e5c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, ccid = ce->lrc.ccid; /* - * Sentinels are supposed to be lonely so they flush the - * current exection off the HW. Check that they are the - * only request in the pending submission. + * Sentinels are supposed to be the last request so they flush + * the current exection off the HW. Check that they are the only + * request in the pending submission. */ if (sentinel) { GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, port - execlists->pending); return false; } - sentinel = i915_request_has_sentinel(rq); - if (sentinel && port != execlists->pending) { - GEM_TRACE_ERR("%s: sentinel context:%llx not in prime position[%zd]\n", - engine->name, - ce->timeline->fence_context, - port - execlists->pending); - return false; - } /* Hold tightly onto the lock to prevent concurrent retires! */ if (!spin_trylock_irqsave(&rq->lock, flags)) -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:21:00 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:21:00 +0100 Subject: [Intel-gfx] [PATCH 20/28] drm/i915: Replace engine->schedule() with a known request operation In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-20-chris@chris-wilson.co.uk> Looking to the future, we want to set the scheduling attributes explicitly and so replace the generic engine->schedule() with the more direct i915_request_set_priority() What it loses in removing the 'schedule' name from the function, it gains in having an explicit entry point with a stated goal. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/display/intel_display.c | 9 +---- drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 +- drivers/gpu/drm/i915/gem/i915_gem_wait.c | 27 +++++---------- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 -- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 4 +-- drivers/gpu/drm/i915/gt/intel_engine_types.h | 29 ++++++++-------- drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 11 +++---- drivers/gpu/drm/i915/gt/selftest_lrc.c | 33 +++++-------------- drivers/gpu/drm/i915/i915_request.c | 11 ++++--- drivers/gpu/drm/i915/i915_scheduler.c | 15 +++++---- drivers/gpu/drm/i915/i915_scheduler.h | 3 +- 13 files changed, 57 insertions(+), 95 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 511555d444e5..797e3573d392 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15888,13 +15888,6 @@ static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) intel_unpin_fb_vma(vma, old_plane_state->flags); } -static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj) -{ - struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY }; - - i915_gem_object_wait_priority(obj, 0, &attr); -} - /** * intel_prepare_plane_fb - Prepare fb for usage on plane * @_plane: drm plane to prepare for @@ -15971,7 +15964,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, if (ret) return ret; - fb_obj_bump_render_priority(obj); + i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB); if (!new_plane_state->uapi.fence) { /* implicit fencing */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 2faa481cc18f..876c34982555 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -476,7 +476,7 @@ int i915_gem_object_wait(struct drm_i915_gem_object *obj, long timeout); int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, unsigned int flags, - const struct i915_sched_attr *attr); + int prio); void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj, enum fb_op_origin origin); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_wait.c b/drivers/gpu/drm/i915/gem/i915_gem_wait.c index 8af55cd3e690..cefbbb3d9b52 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_wait.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_wait.c @@ -93,28 +93,17 @@ i915_gem_object_wait_reservation(struct dma_resv *resv, return timeout; } -static void __fence_set_priority(struct dma_fence *fence, - const struct i915_sched_attr *attr) +static void __fence_set_priority(struct dma_fence *fence, int prio) { - struct i915_request *rq; - struct intel_engine_cs *engine; - if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence)) return; - rq = to_request(fence); - engine = rq->engine; - local_bh_disable(); - rcu_read_lock(); /* RCU serialisation for set-wedged protection */ - if (engine->schedule) - engine->schedule(rq, attr); - rcu_read_unlock(); + i915_request_set_priority(to_request(fence), prio); local_bh_enable(); /* kick the tasklets if queues were reprioritised */ } -static void fence_set_priority(struct dma_fence *fence, - const struct i915_sched_attr *attr) +static void fence_set_priority(struct dma_fence *fence, int prio) { /* Recurse once into a fence-array */ if (dma_fence_is_array(fence)) { @@ -122,16 +111,16 @@ static void fence_set_priority(struct dma_fence *fence, int i; for (i = 0; i < array->num_fences; i++) - __fence_set_priority(array->fences[i], attr); + __fence_set_priority(array->fences[i], prio); } else { - __fence_set_priority(fence, attr); + __fence_set_priority(fence, prio); } } int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, unsigned int flags, - const struct i915_sched_attr *attr) + int prio) { struct dma_fence *excl; @@ -146,7 +135,7 @@ i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, return ret; for (i = 0; i < count; i++) { - fence_set_priority(shared[i], attr); + fence_set_priority(shared[i], prio); dma_fence_put(shared[i]); } @@ -156,7 +145,7 @@ i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, } if (excl) { - fence_set_priority(excl, attr); + fence_set_priority(excl, prio); dma_fence_put(excl); } return 0; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e5141a897786..d79307d790da 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -334,9 +334,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) if (engine->context_size) DRIVER_CAPS(i915)->has_logical_contexts = true; - /* Nothing to do here, execute in order of dependencies */ - engine->schedule = NULL; - ewma__engine_latency_init(&engine->latency); seqlock_init(&engine->stats.lock); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index ee002eb796cb..5251860e952d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -87,7 +87,7 @@ static void heartbeat(struct work_struct *wrk) * but all other contexts, including the kernel * context are stuck waiting for the signal. */ - } else if (engine->schedule && + } else if (intel_engine_has_scheduler(engine) && rq->sched.attr.priority < I915_PRIORITY_BARRIER) { /* * Gradually raise the priority of the heartbeat to @@ -102,7 +102,7 @@ static void heartbeat(struct work_struct *wrk) attr.priority = I915_PRIORITY_BARRIER; local_bh_disable(); - engine->schedule(rq, &attr); + i915_request_set_priority(rq, attr.priority); local_bh_enable(); } else { if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 073c3769e8cc..48e111f16dc5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -482,14 +482,6 @@ struct intel_engine_cs { void (*bond_execute)(struct i915_request *rq, struct dma_fence *signal); - /* - * Call when the priority on a request has changed and it and its - * dependencies may need rescheduling. Note the request itself may - * not be ready to run! - */ - void (*schedule)(struct i915_request *request, - const struct i915_sched_attr *attr); - void (*release)(struct intel_engine_cs *engine); struct intel_engine_execlists execlists; @@ -507,13 +499,14 @@ struct intel_engine_cs { #define I915_ENGINE_USING_CMD_PARSER BIT(0) #define I915_ENGINE_SUPPORTS_STATS BIT(1) -#define I915_ENGINE_HAS_PREEMPTION BIT(2) -#define I915_ENGINE_HAS_SEMAPHORES BIT(3) -#define I915_ENGINE_HAS_TIMESLICES BIT(4) -#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5) -#define I915_ENGINE_IS_VIRTUAL BIT(6) -#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7) -#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8) +#define I915_ENGINE_HAS_SCHEDULER BIT(2) +#define I915_ENGINE_HAS_PREEMPTION BIT(3) +#define I915_ENGINE_HAS_SEMAPHORES BIT(4) +#define I915_ENGINE_HAS_TIMESLICES BIT(5) +#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(6) +#define I915_ENGINE_IS_VIRTUAL BIT(7) +#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(8) +#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(9) unsigned int flags; /* @@ -599,6 +592,12 @@ intel_engine_supports_stats(const struct intel_engine_cs *engine) return engine->flags & I915_ENGINE_SUPPORTS_STATS; } +static inline bool +intel_engine_has_scheduler(const struct intel_engine_cs *engine) +{ + return engine->flags & I915_ENGINE_HAS_SCHEDULER; +} + static inline bool intel_engine_has_preemption(const struct intel_engine_cs *engine) { diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 848decee9066..1c0a7f3ec0bd 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -108,7 +108,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) for_each_uabi_engine(engine, i915) { /* all engines must agree! */ int i; - if (engine->schedule) + if (intel_engine_has_scheduler(engine)) enabled |= (I915_SCHEDULER_CAP_ENABLED | I915_SCHEDULER_CAP_PRIORITY); else diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 0ca3604ab846..3199c65fa7e8 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -4938,7 +4938,6 @@ static void execlists_park(struct intel_engine_cs *engine) void intel_execlists_set_default_submission(struct intel_engine_cs *engine) { engine->submit_request = execlists_submit_request; - engine->schedule = i915_schedule; engine->execlists.tasklet.func = execlists_submission_tasklet; engine->reset.prepare = execlists_reset_prepare; @@ -4949,6 +4948,7 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine) engine->park = execlists_park; engine->unpark = NULL; + engine->flags |= I915_ENGINE_HAS_SCHEDULER; engine->flags |= I915_ENGINE_SUPPORTS_STATS; if (!intel_vgpu_active(engine->i915)) { engine->flags |= I915_ENGINE_HAS_SEMAPHORES; @@ -5682,7 +5682,6 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings, ve->base.cops = &virtual_context_ops; ve->base.request_alloc = execlists_request_alloc; - ve->base.schedule = i915_schedule; ve->base.submit_request = virtual_submit_request; ve->base.bond_execute = virtual_bond_execute; diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 2af66f8ffbd2..afa4f88035ac 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -727,12 +727,11 @@ static int active_engine(void *data) rq[idx] = i915_request_get(new); i915_request_add(new); - if (engine->schedule && arg->flags & TEST_PRIORITY) { - struct i915_sched_attr attr = { - .priority = - i915_prandom_u32_max_state(512, &prng), - }; - engine->schedule(rq[idx], &attr); + if (intel_engine_has_scheduler(engine) && + arg->flags & TEST_PRIORITY) { + int prio = i915_prandom_u32_max_state(512, &prng); + + i915_request_set_priority(rq[idx], prio); } err = active_request_put(old); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 15aaa1bf8943..052dcc59fcc5 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -308,12 +308,8 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) i915_request_put(rq[0]); if (prio) { - struct i915_sched_attr attr = { - .priority = prio, - }; - /* Alternatively preempt the spinner with ce[1] */ - engine->schedule(rq[1], &attr); + i915_request_set_priority(rq[1], prio); } /* And switch back to ce[0] for good measure */ @@ -760,9 +756,6 @@ release_queue(struct intel_engine_cs *engine, struct i915_vma *vma, int idx, int prio) { - struct i915_sched_attr attr = { - .priority = prio, - }; struct i915_request *rq; u32 *cs; @@ -787,7 +780,7 @@ release_queue(struct intel_engine_cs *engine, i915_request_add(rq); local_bh_disable(); - engine->schedule(rq, &attr); + i915_request_set_priority(rq, prio); local_bh_enable(); /* kick tasklet */ i915_request_put(rq); @@ -1193,7 +1186,6 @@ static int live_timeslice_queue(void *arg) goto err_pin; for_each_engine(engine, gt, id) { - struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct i915_request *rq, *nop; if (!intel_engine_has_preemption(engine)) @@ -1208,7 +1200,7 @@ static int live_timeslice_queue(void *arg) err = PTR_ERR(rq); goto err_heartbeat; } - engine->schedule(rq, &attr); + i915_request_set_priority(rq, I915_PRIORITY_MAX); err = wait_for_submit(engine, rq, HZ / 2); if (err) { pr_err("%s: Timed out trying to submit semaphores\n", @@ -1695,7 +1687,6 @@ static int live_late_preempt(void *arg) struct i915_gem_context *ctx_hi, *ctx_lo; struct igt_spinner spin_hi, spin_lo; struct intel_engine_cs *engine; - struct i915_sched_attr attr = {}; enum intel_engine_id id; int err = -ENOMEM; @@ -1758,8 +1749,7 @@ static int live_late_preempt(void *arg) goto err_wedged; } - attr.priority = I915_PRIORITY_MAX; - engine->schedule(rq, &attr); + i915_request_set_priority(rq, I915_PRIORITY_MAX); if (!igt_wait_for_spinner(&spin_hi, rq)) { pr_err("High priority context failed to preempt the low priority context\n"); @@ -2235,7 +2225,6 @@ static int live_preempt_cancel(void *arg) static int live_suppress_self_preempt(void *arg) { - struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct intel_gt *gt = arg; struct intel_engine_cs *engine; struct preempt_client a, b; @@ -2306,7 +2295,7 @@ static int live_suppress_self_preempt(void *arg) i915_request_add(rq_b); GEM_BUG_ON(i915_request_completed(rq_a)); - engine->schedule(rq_a, &attr); + i915_request_set_priority(rq_a, I915_PRIORITY_MAX); igt_spinner_end(&a.spin); if (!igt_wait_for_spinner(&b.spin, rq_b)) { @@ -2374,7 +2363,6 @@ static int live_chain_preempt(void *arg) goto err_client_hi; for_each_engine(engine, gt, id) { - struct i915_sched_attr attr = { .priority = I915_PRIORITY_MAX }; struct igt_live_test t; struct i915_request *rq; int ring_size, count, i; @@ -2441,7 +2429,7 @@ static int live_chain_preempt(void *arg) i915_request_get(rq); i915_request_add(rq); - engine->schedule(rq, &attr); + i915_request_set_priority(rq, I915_PRIORITY_MAX); igt_spinner_end(&hi.spin); if (i915_request_wait(rq, 0, HZ / 5) < 0) { @@ -2630,14 +2618,12 @@ static int live_preempt_gang(void *arg) return -EIO; do { - struct i915_sched_attr attr = { .priority = prio++ }; - err = create_gang(engine, &rq); if (err) break; /* Submit each spinner at increasing priority */ - engine->schedule(rq, &attr); + i915_request_set_priority(rq, prio++); } while (prio <= I915_PRIORITY_MAX && !__igt_timeout(end_time, NULL)); pr_debug("%s: Preempt chain of %d requests\n", @@ -2859,9 +2845,6 @@ static int preempt_user(struct intel_engine_cs *engine, struct i915_vma *global, int id) { - struct i915_sched_attr attr = { - .priority = I915_PRIORITY_MAX - }; struct i915_request *rq; int err = 0; u32 *cs; @@ -2886,7 +2869,7 @@ static int preempt_user(struct intel_engine_cs *engine, i915_request_get(rq); i915_request_add(rq); - engine->schedule(rq, &attr); + i915_request_set_priority(rq, I915_PRIORITY_MAX); if (i915_request_wait(rq, 0, HZ / 2) < 0) err = -ETIME; diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index f04f91b4d879..6c602b29026d 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1182,7 +1182,7 @@ __i915_request_await_execution(struct i915_request *to, } /* Couple the dependency tree for PI on this exposed to->fence */ - if (to->engine->schedule) { + if (intel_engine_has_scheduler(to->engine)) { err = i915_sched_node_add_dependency(&to->sched, &from->sched, I915_DEPENDENCY_WEAK); @@ -1453,7 +1453,7 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from) return 0; } - if (to->engine->schedule) { + if (intel_engine_has_scheduler(to->engine)) { ret = i915_sched_node_add_dependency(&to->sched, &from->sched, I915_DEPENDENCY_EXTERNAL); @@ -1663,7 +1663,7 @@ __i915_request_add_to_timeline(struct i915_request *rq) __i915_sw_fence_await_dma_fence(&rq->submit, &prev->fence, &rq->dmaq); - if (rq->engine->schedule) + if (intel_engine_has_scheduler(rq->engine)) __i915_sched_node_add_dependency(&rq->sched, &prev->sched, &rq->dep, @@ -1729,8 +1729,9 @@ void __i915_request_queue(struct i915_request *rq, * decide whether to preempt the entire chain so that it is ready to * run at the earliest possible convenience. */ - if (attr && rq->engine->schedule) - rq->engine->schedule(rq, attr); + if (attr) + i915_request_set_priority(rq, attr->priority); + i915_sw_fence_commit(&rq->semaphore); i915_sw_fence_commit(&rq->submit); } diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c index 7246ffbb3e33..9437e9d1d445 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.c +++ b/drivers/gpu/drm/i915/i915_scheduler.c @@ -216,10 +216,8 @@ static void kick_submission(struct intel_engine_cs *engine, rcu_read_unlock(); } -static void __i915_schedule(struct i915_sched_node *node, - const struct i915_sched_attr *attr) +static void __i915_schedule(struct i915_sched_node *node, int prio) { - const int prio = max(attr->priority, node->attr.priority); struct intel_engine_cs *engine; struct i915_dependency *dep, *p; struct i915_dependency stack; @@ -233,6 +231,8 @@ static void __i915_schedule(struct i915_sched_node *node, if (node_signaled(node)) return; + prio = max(prio, node->attr.priority); + stack.signaler = node; list_add(&stack.dfs_link, &dfs); @@ -286,7 +286,7 @@ static void __i915_schedule(struct i915_sched_node *node, */ if (node->attr.priority == I915_PRIORITY_INVALID) { GEM_BUG_ON(!list_empty(&node->link)); - node->attr = *attr; + node->attr.priority = prio; if (stack.dfs_link.next == stack.dfs_link.prev) return; @@ -341,10 +341,13 @@ static void __i915_schedule(struct i915_sched_node *node, spin_unlock(&engine->active.lock); } -void i915_schedule(struct i915_request *rq, const struct i915_sched_attr *attr) +void i915_request_set_priority(struct i915_request *rq, int prio) { + if (!intel_engine_has_scheduler(rq->engine)) + return; + spin_lock_irq(&schedule_lock); - __i915_schedule(&rq->sched, attr); + __i915_schedule(&rq->sched, prio); spin_unlock_irq(&schedule_lock); } diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 1b3c1e1a6ec5..b8696edef446 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -36,8 +36,7 @@ int i915_sched_node_add_dependency(struct i915_sched_node *node, void i915_sched_node_fini(struct i915_sched_node *node); -void i915_schedule(struct i915_request *request, - const struct i915_sched_attr *attr); +void i915_request_set_priority(struct i915_request *request, int prio); struct list_head * i915_sched_lookup_priolist(struct intel_engine_cs *engine, int prio); -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:55 +0100 Subject: [Intel-gfx] [PATCH 15/28] drm/i915: Lift waiter/signaler iterators In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-15-chris@chris-wilson.co.uk> Lift the list iteration defines for traversing the signaler/waiter lists into i915_scheduler.h for reuse. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 10 ---------- drivers/gpu/drm/i915/i915_scheduler_types.h | 10 ++++++++++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index cbcbe694f931..5f5ac05ccbe4 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1872,16 +1872,6 @@ static void virtual_xfer_breadcrumbs(struct virtual_engine *ve) intel_engine_transfer_stale_breadcrumbs(ve->siblings[0], &ve->context); } -#define for_each_waiter(p__, rq__) \ - list_for_each_entry_lockless(p__, \ - &(rq__)->sched.waiters_list, \ - wait_link) - -#define for_each_signaler(p__, rq__) \ - list_for_each_entry_rcu(p__, \ - &(rq__)->sched.signalers_list, \ - signal_link) - static void defer_request(struct i915_request *rq, struct list_head * const pl) { LIST_HEAD(list); diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h index f72e6c397b08..343ed44d5ed4 100644 --- a/drivers/gpu/drm/i915/i915_scheduler_types.h +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h @@ -81,4 +81,14 @@ struct i915_dependency { #define I915_DEPENDENCY_WEAK BIT(2) }; +#define for_each_waiter(p__, rq__) \ + list_for_each_entry_lockless(p__, \ + &(rq__)->sched.waiters_list, \ + wait_link) + +#define for_each_signaler(p__, rq__) \ + list_for_each_entry_rcu(p__, \ + &(rq__)->sched.signalers_list, \ + signal_link) + #endif /* _I915_SCHEDULER_TYPES_H_ */ -- 2.20.1 From chris at chris-wilson.co.uk Sun Jun 7 22:20:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sun, 7 Jun 2020 23:20:48 +0100 Subject: [Intel-gfx] [PATCH 08/28] drm/i915/gt: Resubmit the virtual engine on schedule-out In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <20200607222108.14401-8-chris@chris-wilson.co.uk> Having recognised that we do not change the sibling until we schedule out, we can then defer the decision to resubmit the virtual engine from the unwind of the active queue to scheduling out of the virtual context. By keeping the unwind order intact on the local engine, we can preserve data dependency ordering while doing a preempt-to-busy pass until we have determined the new ELSP. This means that if we try to timeslice between a virtual engine and a data-dependent ordinary request, the pair will maintain their relative ordering and we will avoid the resubmission, cancelling the timeslicing until further change. The dilemma though is that we then may end up in a situation where the 'demotion' of the virtual request to an ordinary request in the engine queue results in filling the ELSP[] with virtual requests instead of spreading the load across the engines. To compensate for this, we mark each virtual request and refuse to resubmit a virtual request in the secondary ELSP slots, thus forcing subsequent virtual requests to be scheduled out after timeslicing. By delaying the decision until we schedule out, we will avoid unnecessary resubmission. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 133 ++++++++++++++++--------- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 2 files changed, 89 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d98e37900171..cbcbe694f931 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1117,46 +1117,17 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) __i915_request_unsubmit(rq); - /* - * Push the request back into the queue for later resubmission. - * If this request is not native to this physical engine (i.e. - * it came from a virtual source), push it back onto the virtual - * engine so that it can be moved across onto another physical - * engine as load dictates. - */ - if (likely(rq->execution_mask == engine->mask)) { - GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); - if (rq_prio(rq) != prio) { - prio = rq_prio(rq); - pl = i915_sched_lookup_priolist(engine, prio); - } - GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - - list_move(&rq->sched.link, pl); - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); + if (rq_prio(rq) != prio) { + prio = rq_prio(rq); + pl = i915_sched_lookup_priolist(engine, prio); + } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - active = rq; - } else { - struct intel_engine_cs *owner = rq->context->engine; + list_move(&rq->sched.link, pl); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); - /* - * Decouple the virtual breadcrumb before moving it - * back to the virtual engine -- we don't want the - * request to complete in the background and try - * and cancel the breadcrumb on the virtual engine - * (instead of the old engine where it is linked)! - */ - if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &rq->fence.flags)) { - spin_lock_nested(&rq->lock, - SINGLE_DEPTH_NESTING); - i915_request_cancel_breadcrumb(rq); - spin_unlock(&rq->lock); - } - WRITE_ONCE(rq->engine, owner); - owner->submit_request(rq); - active = NULL; - } + active = rq; } return active; @@ -1400,12 +1371,54 @@ execlists_schedule_in(struct i915_request *rq, int idx) return i915_request_get(rq); } +static void +resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve) +{ + struct intel_engine_cs *engine = rq->engine; + + /* + * Note that although __execlists_schedule_out() may be called from + * inside execlists_dequeue (under the spinlock), it can only do so + * as a result of request completion, and a completed request is + * not resubmitted. + */ + spin_lock_irq(&engine->active.lock); + + /* + * Decouple the virtual breadcrumb before moving it back to the virtual + * engine -- we don't want the request to complete in the background + * and then try and cancel the breadcrumb on the virtual engine + * (instead of the old engine where it is linked)! + */ + if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) { + spin_lock_nested(&rq->lock, SINGLE_DEPTH_NESTING); + i915_request_cancel_breadcrumb(rq); + spin_unlock(&rq->lock); + } + + clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + WRITE_ONCE(rq->engine, &ve->base); + ve->base.submit_request(rq); + + spin_unlock_irq(&engine->active.lock); +} + static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); + + /* + * This engine is now too busy to run this virtual request, so + * see if we can find an alternative engine for it to execute on. + * Once a request has become bonded to this engine, we treat it the + * same as other native request. + */ + if (i915_request_in_priority_queue(rq) && + rq->execution_mask != rq->engine->mask) + resubmit_virtual_request(rq, ve); } static inline void @@ -1645,6 +1658,20 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, } sentinel = i915_request_has_sentinel(rq); + /* + * We want virtual requests to only be in the first slot so + * that they are never stuck behind a hog and can be immediately + * transferred onto the next idle engine. + */ + if (rq->execution_mask != engine->mask && + port != execlists->pending) { + GEM_TRACE_ERR("%s: virtual engine:%llx not in prime position[%zd]\n", + engine->name, + ce->timeline->fence_context, + port - execlists->pending); + return false; + } + /* Hold tightly onto the lock to prevent concurrent retires! */ if (!spin_trylock_irqsave(&rq->lock, flags)) continue; @@ -2343,6 +2370,15 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (i915_request_has_sentinel(last)) goto done; + /* + * We avoid submitting virtual requests into + * the secondary ports so that we can migrate + * the request immediately to another engine + * rather than wait for the primary request. + */ + if (rq->execution_mask != engine->mask) + goto done; + /* * If GVT overrides us we only ever submit * port[0], leaving port[1] empty. Note that we @@ -3148,13 +3184,6 @@ static void __submit_queue_imm(struct intel_engine_cs *engine) if (reset_in_progress(execlists)) return; /* defer until we restart the engine following reset */ - /* Hopefully we clear execlists->pending[] to let us through */ - if (READ_ONCE(execlists->pending[0]) && - tasklet_trylock(&execlists->tasklet)) { - process_csb(engine); - tasklet_unlock(&execlists->tasklet); - } - __execlists_submission_tasklet(engine); } @@ -3177,11 +3206,25 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } +static void flush_csb(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists *el = &engine->execlists; + + if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { + if (!reset_in_progress(el)) + process_csb(engine); + tasklet_unlock(&el->tasklet); + } +} + static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; + /* Hopefully we clear execlists->pending[] to let us through */ + flush_csb(engine); + /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index f651bdf7f191..a8bcea8aa1b4 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -4289,7 +4289,7 @@ static int reset_virtual_engine(struct intel_gt *gt, spin_lock_irq(&engine->active.lock); __unwind_incomplete_requests(engine); spin_unlock_irq(&engine->active.lock); - GEM_BUG_ON(rq->engine != ve->engine); + GEM_BUG_ON(rq->engine != engine); /* Reset the engine while keeping our active request on hold */ execlists_hold(engine, rq); -- 2.20.1 From patchwork at emeril.freedesktop.org Sun Jun 7 22:22:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 22:22:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/dp=5Fmst=3A_Fix_the_DDC_I2C_dev?= =?utf-8?q?ice_unregistration_of_an_MST_port?= In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <159156852202.15986.9222281965180343483@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port URL : https://patchwork.freedesktop.org/series/78100/ State : success == Summary == CI Bug Log - changes from CI_DRM_8597 -> Patchwork_17901 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/index.html Known issues ------------ Here are the changes found in Patchwork_17901 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-tgl-dsi/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-tgl-dsi/igt at i915_module_load@reload.html - fi-icl-y: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-icl-y/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-icl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-icl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-icl-guc/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-icl-guc/igt at i915_pm_rpm@module-reload.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8597 -> Patchwork_17901 CI-20190529: 20190529 CI_DRM_8597: aadd3cf12a7c515bca8752da797ded56a003617b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5696: 8d1744239f4300eb12d5bab14a30b79d9c8dd364 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17901: c3019da98129f263800477ae0cd767c2179fc034 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c3019da98129 drm/dp_mst: Fix flushing the delayed port/mstb destroy work f183ac475a8b drm/dp_mst: Fix the DDC I2C device registration of an MST port be4cb6213842 drm/dp_mst: Fix the DDC I2C device unregistration of an MST port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/index.html From patchwork at emeril.freedesktop.org Sun Jun 7 22:49:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 22:49:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/28=5D_drm/i915=3A_Adjust_the_sen?= =?utf-8?q?tinel_assert_to_match_implementation?= In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <159157019876.15988.17284161377327166555@emeril.freedesktop.org> == Series Details == Series: series starting with [01/28] drm/i915: Adjust the sentinel assert to match implementation URL : https://patchwork.freedesktop.org/series/78103/ State : warning == Summary == $ dim checkpatch origin/drm-tip f23f25433228 drm/i915: Adjust the sentinel assert to match implementation b94a954251d4 drm/i915/selftests: Make the hanging request non-preemptible 854873908649 drm/i915/selftests: Teach hang-self to target only itself f2f769eafd3d drm/i915/selftests: Remove live_suppress_wait_preempt a4fea0425495 drm/i915/selftests: Trim execlists runtime 7253a1d1220b drm/i915/gt: Use virtual_engine during execlists_dequeue 61f3b28c89b9 drm/i915/gt: Decouple inflight virtual engines 7e90a16cc7ce drm/i915/gt: Resubmit the virtual engine on schedule-out 85be36e07c69 drm/i915: Add list_for_each_entry_safe_continue_reverse -:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible side-effects? #21: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects? #21: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) -:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible side-effects? #21: FILE: drivers/gpu/drm/i915/i915_utils.h:269: +#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \ + for (pos = list_prev_entry(pos, member), \ + n = list_prev_entry(pos, member); \ + &pos->member != (head); \ + pos = n, n = list_prev_entry(n, member)) total: 0 errors, 0 warnings, 3 checks, 12 lines checked 3fa210c03e00 drm/i915/gem: Separate reloc validation into an earlier step 6e281d4c956c drm/i915/gem: Lift GPU relocation allocation 06166bdaf5a2 drm/i915/gem: Build the reloc request first b03d9c429a48 drm/i915/gem: Add all GPU reloc awaits/signals en masse 78cb8746679e dma-buf: Proxy fence, an unsignaled fence placeholder -:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 -:438: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #438: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20: + spinlock_t lock; total: 0 errors, 1 warnings, 1 checks, 1158 lines checked 0cf43f808ad7 drm/i915: Lift waiter/signaler iterators 54c54ac54e10 drm/i915: Unpeel awaits on a proxy fence 097cde1f158a drm/i915/gem: Make relocations atomic within execbuf 50d452bcc3eb drm/i915: Strip out internal priorities 40a48b3a4cd5 drm/i915: Remove I915_USER_PRIORITY_SHIFT e82c48f763c2 drm/i915: Replace engine->schedule() with a known request operation 95ddc88b38ef drm/i915/gt: Do not suspend bonded requests if one hangs f9a12aff6156 drm/i915: Teach the i915_dependency to use a double-lock 2084c4ff504b drm/i915: Restructure priority inheritance 36de84a8bd2b ipi-dag -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one -:55: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 1 warnings, 0 checks, 43 lines checked 956673f1ee95 drm/i915/gt: Check for a completed last request once 62d3790caaf1 drm/i915: Fair low-latency scheduling -:1728: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #1728: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 1571 lines checked 29754bd08fd1 drm/i915/gt: Specify a deadline for the heartbeat 1dad2fcca4f7 drm/i915: Replace the priority boosting for the display with a deadline From patchwork at emeril.freedesktop.org Sun Jun 7 22:51:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 22:51:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/28=5D_drm/i915=3A_Adjust_the_sentine?= =?utf-8?q?l_assert_to_match_implementation?= In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <159157028368.15986.8597656285969470360@emeril.freedesktop.org> == Series Details == Series: series starting with [01/28] drm/i915: Adjust the sentinel assert to match implementation URL : https://patchwork.freedesktop.org/series/78103/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y From patchwork at emeril.freedesktop.org Sun Jun 7 23:12:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 23:12:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/28=5D_drm/i915=3A_Adjust_the_sentinel_a?= =?utf-8?q?ssert_to_match_implementation?= In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <159157152718.15987.7294706311004882491@emeril.freedesktop.org> == Series Details == Series: series starting with [01/28] drm/i915: Adjust the sentinel assert to match implementation URL : https://patchwork.freedesktop.org/series/78103/ State : success == Summary == CI Bug Log - changes from CI_DRM_8597 -> Patchwork_17902 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/index.html New tests --------- New tests have been introduced between CI_DRM_8597 and Patchwork_17902: ### New IGT tests (1) ### * igt at dmabuf@all at dma_fence_proxy: - Statuses : 40 pass(s) - Exec time: [0.03, 0.11] s Known issues ------------ Here are the changes found in Patchwork_17902 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-kbl-x1275/igt at kms_busy@basic at flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-tgl-dsi/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-tgl-dsi/igt at i915_module_load@reload.html - fi-icl-y: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-icl-y/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-icl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-icl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-icl-guc/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-icl-guc/igt at i915_pm_rpm@module-reload.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][15] ([fdo#109271]) -> [DMESG-FAIL][16] ([i915#62]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8597 -> Patchwork_17902 CI-20190529: 20190529 CI_DRM_8597: aadd3cf12a7c515bca8752da797ded56a003617b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5696: 8d1744239f4300eb12d5bab14a30b79d9c8dd364 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17902: 1dad2fcca4f707aa870be1a45bb28bfb4c2b0f73 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1dad2fcca4f7 drm/i915: Replace the priority boosting for the display with a deadline 29754bd08fd1 drm/i915/gt: Specify a deadline for the heartbeat 62d3790caaf1 drm/i915: Fair low-latency scheduling 956673f1ee95 drm/i915/gt: Check for a completed last request once 36de84a8bd2b ipi-dag 2084c4ff504b drm/i915: Restructure priority inheritance f9a12aff6156 drm/i915: Teach the i915_dependency to use a double-lock 95ddc88b38ef drm/i915/gt: Do not suspend bonded requests if one hangs e82c48f763c2 drm/i915: Replace engine->schedule() with a known request operation 40a48b3a4cd5 drm/i915: Remove I915_USER_PRIORITY_SHIFT 50d452bcc3eb drm/i915: Strip out internal priorities 097cde1f158a drm/i915/gem: Make relocations atomic within execbuf 54c54ac54e10 drm/i915: Unpeel awaits on a proxy fence 0cf43f808ad7 drm/i915: Lift waiter/signaler iterators 78cb8746679e dma-buf: Proxy fence, an unsignaled fence placeholder b03d9c429a48 drm/i915/gem: Add all GPU reloc awaits/signals en masse 06166bdaf5a2 drm/i915/gem: Build the reloc request first 6e281d4c956c drm/i915/gem: Lift GPU relocation allocation 3fa210c03e00 drm/i915/gem: Separate reloc validation into an earlier step 85be36e07c69 drm/i915: Add list_for_each_entry_safe_continue_reverse 7e90a16cc7ce drm/i915/gt: Resubmit the virtual engine on schedule-out 61f3b28c89b9 drm/i915/gt: Decouple inflight virtual engines 7253a1d1220b drm/i915/gt: Use virtual_engine during execlists_dequeue a4fea0425495 drm/i915/selftests: Trim execlists runtime f2f769eafd3d drm/i915/selftests: Remove live_suppress_wait_preempt 854873908649 drm/i915/selftests: Teach hang-self to target only itself b94a954251d4 drm/i915/selftests: Make the hanging request non-preemptible f23f25433228 drm/i915: Adjust the sentinel assert to match implementation == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/index.html From imre.deak at intel.com Sun Jun 7 23:15:05 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 8 Jun 2020 02:15:05 +0300 Subject: [Intel-gfx] [PATCH RESEND v3 1/3] drm/i915/dp_mst: Fix disabling MST on a port In-Reply-To: <854f3594de3a7531eb4e4fa1cf4449bcd7b02dea.camel@intel.com> References: <20200604184500.23730-1-imre.deak@intel.com> <20200605094801.17709-1-imre.deak@intel.com> <854f3594de3a7531eb4e4fa1cf4449bcd7b02dea.camel@intel.com> Message-ID: <20200607231505.GA18231@ideak-desk.fi.intel.com> On Mon, Jun 08, 2020 at 01:11:44AM +0300, Souza, Jose wrote: > On Fri, 2020-06-05 at 12:48 +0300, Imre Deak wrote: > > Currently MST on a port can get enabled/disabled from the hotplug work > > and get disabled from the short pulse work in a racy way. Fix this by > > relying on the MST state checking in the hotplug work and just schedule > > a hotplug work from the short pulse handler if some problem happened > > during the MST interrupt handling. > > > > This removes the explicit MST disabling in case of an AUX failure, but > > if AUX fails, then probably the detection will also fail during the > > scheduled hotplug work and it's not guaranteed that we'll see > > intermittent errors anyway. > > > > While at it also simplify the error checking of the MST interrupt > > handler. > > > > v2: > > - Convert intel_dp_check_mst_status() to return bool. (Ville) > > - Change the intel_dp->is_mst check to an assert, since after this patch > > the condition can't change after we checked it previously. > > - Document the return value from intel_dp_check_mst_status(). > > v3: > > - Remove the intel_dp->is_mst check from intel_dp_check_mst_status(). > > There is no point in checking the same condition twice, even though > > there is a chance that the hotplug work running concurrently changes > > it. > > > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> (v1) > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 66 ++++++++++--------------- > > 1 file changed, 26 insertions(+), 40 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 55fda074c0ad..42589cae766d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5556,35 +5556,46 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) > > "Could not write test response to sink\n"); > > } > > > > -static int > > +/** > > + * intel_dp_check_mst_status - service any pending MST interrupts, check link status > > + * @intel_dp: Intel DP struct > > + * > > + * Read any pending MST interrupts, call MST core to handle these and ack the > > + * interrupts. Check if the main and AUX link state is ok. > > + * > > + * Returns: > > + * - %true if pending interrupts were serviced (or no interrupts were > > + * pending) w/o detecting an error condition. > > + * - %false if an error condition - like AUX failure or a loss of link - is > > + * detected, which needs servicing from the hotplug work. > > + */ > > +static bool > > intel_dp_check_mst_status(struct intel_dp *intel_dp) > > { > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > - bool need_retrain = false; > > - > > - if (!intel_dp->is_mst) > > - return -EINVAL; > > + bool link_ok = true; > > > > drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); > > > > for (;;) { > > u8 esi[DP_DPRX_ESI_LEN] = {}; > > - bool bret, handled; > > + bool handled; > > int retry; > > > > - bret = intel_dp_get_sink_irq_esi(intel_dp, esi); > > - if (!bret) { > > + if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { > > drm_dbg_kms(&i915->drm, > > "failed to get ESI - device may have failed\n"); > > - return -EINVAL; > > + link_ok = false; > > + > > + break; > > } > > > > /* check link status - esi[10] = 0x200c */ > > - if (intel_dp->active_mst_links > 0 && !need_retrain && > > + if (intel_dp->active_mst_links > 0 && link_ok && > > !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { > > drm_dbg_kms(&i915->drm, > > "channel EQ not ok, retraining\n"); > > - need_retrain = true; > > + link_ok = false; > > } > > > > drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); > > @@ -5604,7 +5615,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) > > } > > } > > > > - return need_retrain; > > + return link_ok; > > } > > > > static bool > > @@ -7255,35 +7266,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > > } > > > > if (intel_dp->is_mst) { > > - switch (intel_dp_check_mst_status(intel_dp)) { > > - case -EINVAL: > > - /* > > - * If we were in MST mode, and device is not > > - * there, get out of MST mode > > - */ > > - drm_dbg_kms(&i915->drm, > > - "MST device may have disappeared %d vs %d\n", > > - intel_dp->is_mst, > > - intel_dp->mst_mgr.mst_state); > > - intel_dp->is_mst = false; > > - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > > - intel_dp->is_mst); > > - > > - return IRQ_NONE; > > - case 1: > > - return IRQ_NONE; > > - default: > > - break; > > - } > > - } > > - > > - if (!intel_dp->is_mst) { > > - bool handled; > > - > > - handled = intel_dp_short_pulse(intel_dp); > > - > > - if (!handled) > > + if (!intel_dp_check_mst_status(intel_dp)) > > return IRQ_NONE; > > + } else if (!intel_dp_short_pulse(intel_dp)) { > > + return IRQ_NONE; > > } > > > > Now it don't need the braces but this is minor. Without the braces it wouldn't be correct. > > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > return IRQ_HANDLED; From patchwork at emeril.freedesktop.org Sun Jun 7 23:22:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sun, 07 Jun 2020 23:22:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/dp=5Fmst=3A_Fix_the_DDC_I2C_dev?= =?utf-8?q?ice_unregistration_of_an_MST_port?= In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <159157213719.15989.9015253662299268978@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port URL : https://patchwork.freedesktop.org/series/78100/ State : success == Summary == CI Bug Log - changes from CI_DRM_8597_full -> Patchwork_17901_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17901_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][1] -> [INCOMPLETE][2] ([i915#58] / [i915#95] / [k.org#198133]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk2/igt at gem_ctx_persistence@close-replace-race.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-glk5/igt at gem_ctx_persistence@close-replace-race.html * igt at gem_exec_create@basic: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl2/igt at gem_exec_create@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-kbl6/igt at gem_exec_create@basic.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl6/igt at gem_exec_suspend@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-kbl2/igt at gem_exec_suspend@basic-s3.html * igt at gem_exec_whisper@basic-queues-priority: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk6/igt at gem_exec_whisper@basic-queues-priority.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-glk9/igt at gem_exec_whisper@basic-queues-priority.html * igt at kms_concurrent@pipe-b: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl9/igt at kms_concurrent@pipe-b.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl6/igt at kms_concurrent@pipe-b.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#300]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +19 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl8/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl7/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl6/igt at kms_fbcon_fbt@fbc-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl4/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-iclb: [PASS][23] -> [INCOMPLETE][24] ([i915#1185] / [i915#250]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-iclb3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-iclb1/igt at kms_psr@psr2_cursor_plane_onoff.html #### Possible fixes #### * igt at gem_exec_whisper@basic-fds-forked-all: - shard-glk: [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk2/igt at gem_exec_whisper@basic-fds-forked-all.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-glk2/igt at gem_exec_whisper@basic-fds-forked-all.html * igt at i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +3 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl6/igt at i915_suspend@sysfs-reader.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl8/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][33] ([i915#118] / [i915#95]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-glk5/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-a-ctm-0-75: - shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl6/igt at kms_color@pipe-a-ctm-0-75.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl3/igt at kms_color@pipe-a-ctm-0-75.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen: - shard-skl: [FAIL][37] ([i915#54]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl5/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl9/igt at kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html * igt at kms_cursor_legacy@pipe-b-torture-bo: - shard-kbl: [DMESG-WARN][39] ([i915#93] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl1/igt at kms_cursor_legacy@pipe-b-torture-bo.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-kbl7/igt at kms_cursor_legacy@pipe-b-torture-bo.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1}: - shard-skl: [FAIL][41] ([i915#1928]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl4/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [FAIL][43] ([i915#699]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl5/igt at kms_flip_tiling@flip-changes-tiling-yf.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl9/igt at kms_flip_tiling@flip-changes-tiling-yf.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk7/igt at kms_frontbuffer_tracking@fbc-badstride.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-glk2/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][47] ([i915#1188]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl3/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][49] ([fdo#108145] / [i915#265]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb7/igt at kms_psr@psr2_sprite_blt.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +4 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at kms_vblank@pipe-d-wait-busy: - shard-tglb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb1/igt at kms_vblank@pipe-d-wait-busy.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-tglb5/igt at kms_vblank@pipe-d-wait-busy.html * igt at syncobj_wait@single-wait-for-submit-unsubmitted: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +27 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl7/igt at syncobj_wait@single-wait-for-submit-unsubmitted.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl2/igt at syncobj_wait@single-wait-for-submit-unsubmitted.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][59] ([i915#454]) -> [SKIP][60] ([i915#468]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb7/igt at i915_pm_dc@dc6-psr.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-kbl: [DMESG-FAIL][61] ([fdo#110321] / [i915#95]) -> [TIMEOUT][62] ([i915#1319]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl2/igt at kms_content_protection@atomic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-kbl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][63] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][64] ([i915#1319] / [i915#1635]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl3/igt at kms_content_protection@atomic-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][65] ([i915#1319] / [i915#1635]) -> [FAIL][66] ([fdo#110321]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl7/igt at kms_content_protection@srm.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl2/igt at kms_content_protection@srm.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [FAIL][67] ([IGT#5]) -> [DMESG-WARN][68] ([i915#1982]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl7/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][69] ([fdo#108145] / [i915#265]) -> [DMESG-WARN][70] ([i915#1982]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_setmode@basic: - shard-apl: [FAIL][71] ([i915#31]) -> [DMESG-FAIL][72] ([i915#31] / [i915#95]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl3/igt at kms_setmode@basic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/shard-apl1/igt at kms_setmode@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8597 -> Patchwork_17901 CI-20190529: 20190529 CI_DRM_8597: aadd3cf12a7c515bca8752da797ded56a003617b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5696: 8d1744239f4300eb12d5bab14a30b79d9c8dd364 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17901: c3019da98129f263800477ae0cd767c2179fc034 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17901/index.html From patchwork at emeril.freedesktop.org Mon Jun 8 00:58:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 00:58:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/28=5D_drm/i915=3A_Adjust_the_sentinel_a?= =?utf-8?q?ssert_to_match_implementation?= In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <159157790688.14461.346273860418862137@emeril.freedesktop.org> == Series Details == Series: series starting with [01/28] drm/i915: Adjust the sentinel assert to match implementation URL : https://patchwork.freedesktop.org/series/78103/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8597_full -> Patchwork_17902_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17902_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17902_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17902_full: ### IGT changes ### #### Possible regressions #### * igt at gem_ctx_exec@basic-nohangcheck: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk1/igt at gem_ctx_exec@basic-nohangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk2/igt at gem_ctx_exec@basic-nohangcheck.html - shard-tglb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb8/igt at gem_ctx_exec@basic-nohangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-tglb8/igt at gem_ctx_exec@basic-nohangcheck.html - shard-iclb: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb5/igt at gem_ctx_exec@basic-nohangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb8/igt at gem_ctx_exec@basic-nohangcheck.html - shard-skl: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl7/igt at gem_ctx_exec@basic-nohangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl9/igt at gem_ctx_exec@basic-nohangcheck.html * igt at gem_exec_balancer@smoke: - shard-iclb: [PASS][9] -> [TIMEOUT][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb6/igt at gem_exec_balancer@smoke.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb2/igt at gem_exec_balancer@smoke.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-tglb2/igt at i915_module_load@reload-with-fault-injection.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_params@invalid-batch-start-offset}: - shard-iclb: [PASS][13] -> [TIMEOUT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb6/igt at gem_exec_params@invalid-batch-start-offset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb2/igt at gem_exec_params@invalid-batch-start-offset.html * {igt at gem_exec_schedule@preempt-engines at bcs0}: - shard-kbl: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl7/igt at gem_exec_schedule@preempt-engines at bcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl2/igt at gem_exec_schedule@preempt-engines at bcs0.html * {igt at gem_exec_schedule@preempt-engines at rcs0}: - shard-skl: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl7/igt at gem_exec_schedule@preempt-engines at rcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl9/igt at gem_exec_schedule@preempt-engines at rcs0.html * {igt at gem_exec_schedule@reorder-wide at bcs0}: - shard-skl: [PASS][19] -> [FAIL][20] +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl3/igt at gem_exec_schedule@reorder-wide at bcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl5/igt at gem_exec_schedule@reorder-wide at bcs0.html * {igt at gem_exec_schedule@reorder-wide at rcs0}: - shard-apl: [PASS][21] -> [FAIL][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl2/igt at gem_exec_schedule@reorder-wide at rcs0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl1/igt at gem_exec_schedule@reorder-wide at rcs0.html - shard-glk: [PASS][23] -> [FAIL][24] +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk5/igt at gem_exec_schedule@reorder-wide at rcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk5/igt at gem_exec_schedule@reorder-wide at rcs0.html * {igt at gem_exec_schedule@reorder-wide at vcs0}: - shard-iclb: [PASS][25] -> [FAIL][26] +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb1/igt at gem_exec_schedule@reorder-wide at vcs0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb1/igt at gem_exec_schedule@reorder-wide at vcs0.html * {igt at gem_exec_schedule@reorder-wide at vcs1}: - shard-kbl: [PASS][27] -> [FAIL][28] +4 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl6/igt at gem_exec_schedule@reorder-wide at vcs1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl1/igt at gem_exec_schedule@reorder-wide at vcs1.html - shard-tglb: [PASS][29] -> [FAIL][30] +4 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb5/igt at gem_exec_schedule@reorder-wide at vcs1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-tglb6/igt at gem_exec_schedule@reorder-wide at vcs1.html * {igt at gem_userptr_blits@invalid-mmap-offset-unsync}: - shard-iclb: NOTRUN -> [TIMEOUT][31] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb2/igt at gem_userptr_blits@invalid-mmap-offset-unsync.html New tests --------- New tests have been introduced between CI_DRM_8597_full and Patchwork_17902_full: ### New IGT tests (2) ### * igt at dmabuf@all at dma_fence_proxy: - Statuses : 8 pass(s) - Exec time: [0.03, 0.10] s * igt at i915_selftest@mock at scheduler: - Statuses : 7 pass(s) - Exec time: [0.11, 1.08] s Known issues ------------ Here are the changes found in Patchwork_17902_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-apl: [PASS][32] -> [FAIL][33] ([i915#1528]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl3/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl1/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_create@basic: - shard-kbl: [PASS][34] -> [DMESG-WARN][35] ([i915#93] / [i915#95]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl2/igt at gem_exec_create@basic.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl7/igt at gem_exec_create@basic.html * igt at gem_exec_whisper@basic-queues-forked: - shard-glk: [PASS][36] -> [DMESG-WARN][37] ([i915#118] / [i915#95]) +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk1/igt at gem_exec_whisper@basic-queues-forked.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk2/igt at gem_exec_whisper@basic-queues-forked.html * igt at gem_workarounds@suspend-resume: - shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#69]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl3/igt at gem_workarounds@suspend-resume.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl4/igt at gem_workarounds@suspend-resume.html * igt at i915_pm_rps@waitboost: - shard-hsw: [PASS][40] -> [FAIL][41] ([i915#39]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-hsw1/igt at i915_pm_rps@waitboost.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-hsw8/igt at i915_pm_rps@waitboost.html * igt at kms_big_fb@x-tiled-32bpp-rotate-0: - shard-apl: [PASS][42] -> [DMESG-WARN][43] ([i915#1982]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl3/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl8/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html * igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions: - shard-kbl: [PASS][44] -> [DMESG-WARN][45] ([i915#1982]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl1/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl4/igt at kms_cursor_legacy@short-flip-after-cursor-atomic-transitions.html * igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled: - shard-apl: [PASS][46] -> [DMESG-WARN][47] ([i915#95]) +20 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl8/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl1/igt at kms_draw_crc@draw-method-xrgb8888-pwrite-xtiled.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc: - shard-iclb: [PASS][48] -> [DMESG-WARN][49] ([i915#1982]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][52] -> [DMESG-WARN][53] ([i915#180]) +5 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][54] -> [SKIP][55] ([fdo#109441]) +2 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb8/igt at kms_psr@psr2_cursor_plane_onoff.html * igt at kms_universal_plane@disable-primary-vs-flip-pipe-b: - shard-skl: [PASS][56] -> [DMESG-WARN][57] ([i915#1982]) +9 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl6/igt at kms_universal_plane@disable-primary-vs-flip-pipe-b.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl2/igt at kms_universal_plane@disable-primary-vs-flip-pipe-b.html * igt at kms_vblank@pipe-b-wait-forked: - shard-hsw: [PASS][58] -> [INCOMPLETE][59] ([i915#61]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-hsw6/igt at kms_vblank@pipe-b-wait-forked.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-hsw7/igt at kms_vblank@pipe-b-wait-forked.html * igt at syncobj_wait@invalid-multi-wait-all-unsubmitted-signaled: - shard-tglb: [PASS][60] -> [DMESG-WARN][61] ([i915#402]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-all-unsubmitted-signaled.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-all-unsubmitted-signaled.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-tglb: [FAIL][62] ([i915#1930]) -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb8/igt at gem_exec_reloc@basic-concurrent0.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-tglb8/igt at gem_exec_reloc@basic-concurrent0.html - shard-glk: [FAIL][64] ([i915#1930]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html - shard-apl: [FAIL][66] ([i915#1930]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl1/igt at gem_exec_reloc@basic-concurrent0.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl4/igt at gem_exec_reloc@basic-concurrent0.html - shard-kbl: [FAIL][68] ([i915#1930]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl3/igt at gem_exec_reloc@basic-concurrent0.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl6/igt at gem_exec_reloc@basic-concurrent0.html - shard-hsw: [FAIL][70] ([i915#1930]) -> [PASS][71] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-hsw2/igt at gem_exec_reloc@basic-concurrent0.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-hsw4/igt at gem_exec_reloc@basic-concurrent0.html - shard-iclb: [FAIL][72] ([i915#1930]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb3/igt at gem_exec_reloc@basic-concurrent0.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb7/igt at gem_exec_reloc@basic-concurrent0.html - shard-snb: [FAIL][74] ([i915#1930]) -> [PASS][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-snb5/igt at gem_exec_reloc@basic-concurrent0.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-snb2/igt at gem_exec_reloc@basic-concurrent0.html - shard-skl: [FAIL][76] ([i915#1930]) -> [PASS][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl6/igt at gem_exec_reloc@basic-concurrent0.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl10/igt at gem_exec_reloc@basic-concurrent0.html * {igt at gem_exec_reloc@basic-concurrent16}: - shard-snb: [TIMEOUT][78] ([i915#1958]) -> [PASS][79] +2 similar issues [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html - shard-iclb: [INCOMPLETE][80] ([i915#1958]) -> [PASS][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb7/igt at gem_exec_reloc@basic-concurrent16.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb3/igt at gem_exec_reloc@basic-concurrent16.html - shard-hsw: [TIMEOUT][82] ([i915#1958]) -> [PASS][83] +3 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-hsw8/igt at gem_exec_reloc@basic-concurrent16.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-hsw8/igt at gem_exec_reloc@basic-concurrent16.html - shard-skl: [INCOMPLETE][84] ([i915#1958]) -> [PASS][85] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl2/igt at gem_exec_reloc@basic-concurrent16.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl1/igt at gem_exec_reloc@basic-concurrent16.html - shard-kbl: [INCOMPLETE][86] ([i915#1958]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl1/igt at gem_exec_reloc@basic-concurrent16.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl4/igt at gem_exec_reloc@basic-concurrent16.html - shard-apl: [INCOMPLETE][88] ([i915#1635] / [i915#1958]) -> [PASS][89] [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl8/igt at gem_exec_reloc@basic-concurrent16.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl7/igt at gem_exec_reloc@basic-concurrent16.html - shard-tglb: [INCOMPLETE][90] ([i915#1958]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb3/igt at gem_exec_reloc@basic-concurrent16.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-tglb5/igt at gem_exec_reloc@basic-concurrent16.html - shard-glk: [INCOMPLETE][92] ([i915#1958] / [i915#58] / [k.org#198133]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk2/igt at gem_exec_reloc@basic-concurrent16.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk4/igt at gem_exec_reloc@basic-concurrent16.html * igt at gem_exec_whisper@basic-contexts-all: - shard-glk: [DMESG-WARN][94] ([i915#118] / [i915#95]) -> [PASS][95] +1 similar issue [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk8/igt at gem_exec_whisper@basic-contexts-all.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk4/igt at gem_exec_whisper@basic-contexts-all.html * igt at i915_suspend@sysfs-reader: - shard-apl: [DMESG-WARN][96] ([i915#180]) -> [PASS][97] +3 similar issues [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl6/igt at i915_suspend@sysfs-reader.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl2/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][98] ([i915#118] / [i915#95]) -> [PASS][99] +2 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk6/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [FAIL][100] ([i915#72]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk6/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk8/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt at kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size: - shard-skl: [DMESG-WARN][102] ([i915#1982]) -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl9/igt at kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl1/igt at kms_cursor_legacy@cursora-vs-flipa-atomic-transitions-varying-size.html * igt at kms_draw_crc@draw-method-rgb565-blt-untiled: - shard-apl: [DMESG-WARN][104] ([i915#95]) -> [PASS][105] +22 similar issues [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl6/igt at kms_draw_crc@draw-method-rgb565-blt-untiled.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl2/igt at kms_draw_crc@draw-method-rgb565-blt-untiled.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1}: - shard-glk: [FAIL][106] ([i915#79]) -> [PASS][107] [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-glk6/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-glk8/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html * {igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1}: - shard-skl: [FAIL][108] ([i915#1928]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl4/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl4/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling-yf: - shard-skl: [FAIL][110] ([i915#699]) -> [PASS][111] [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl5/igt at kms_flip_tiling@flip-changes-tiling-yf.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl3/igt at kms_flip_tiling@flip-changes-tiling-yf.html * igt at kms_frontbuffer_tracking@fbc-indfb-scaledprimary: - shard-tglb: [DMESG-WARN][112] ([i915#1982]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-tglb6/igt at kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-tglb3/igt at kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][114] ([fdo#109441]) -> [PASS][115] +1 similar issue [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-iclb6/igt at kms_psr@psr2_sprite_plane_move.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +4 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-hsw: [FAIL][118] ([i915#1542]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-hsw6/igt at perf@blocking-parameterized.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-hsw1/igt at perf@blocking-parameterized.html #### Warnings #### * igt at gem_ctx_exec@basic-nohangcheck: - shard-kbl: [DMESG-WARN][120] ([i915#93] / [i915#95]) -> [DMESG-FAIL][121] ([i915#95]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl2/igt at gem_ctx_exec@basic-nohangcheck.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl3/igt at gem_ctx_exec@basic-nohangcheck.html - shard-apl: [DMESG-WARN][122] ([i915#95]) -> [DMESG-FAIL][123] ([i915#95]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl1/igt at gem_ctx_exec@basic-nohangcheck.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl4/igt at gem_ctx_exec@basic-nohangcheck.html * igt at kms_content_protection@atomic: - shard-kbl: [DMESG-FAIL][124] ([fdo#110321] / [i915#95]) -> [TIMEOUT][125] ([i915#1319]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl2/igt at kms_content_protection@atomic.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][126] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][127] ([i915#1319] / [i915#1635]) +1 similar issue [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl3/igt at kms_content_protection@atomic-dpms.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl8/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][128] ([i915#1319]) -> [TIMEOUT][129] ([i915#1319] / [i915#1958]) [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl1/igt at kms_content_protection@legacy.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][130] ([i915#1319] / [i915#1635]) -> [FAIL][131] ([fdo#110321]) +1 similar issue [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-apl6/igt at kms_content_protection@lic.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-apl2/igt at kms_content_protection@lic.html - shard-kbl: [TIMEOUT][132] ([i915#1319] / [i915#1958]) -> [TIMEOUT][133] ([i915#1319]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl4/igt at kms_content_protection@lic.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl3/igt at kms_content_protection@lic.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][134] ([i915#93] / [i915#95]) -> [DMESG-WARN][135] ([i915#180] / [i915#93] / [i915#95]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [FAIL][136] ([IGT#5]) -> [DMESG-WARN][137] ([i915#1982]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-skl7/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-skl9/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt: - shard-snb: [TIMEOUT][138] ([i915#1958]) -> [SKIP][139] ([fdo#109271]) +2 similar issues [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-snb2/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-snb2/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html - shard-hsw: [TIMEOUT][140] ([i915#1958]) -> [SKIP][141] ([fdo#109271]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8597/shard-hsw8/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/shard-hsw8/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8597 -> Patchwork_17902 CI-20190529: 20190529 CI_DRM_8597: aadd3cf12a7c515bca8752da797ded56a003617b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5696: 8d1744239f4300eb12d5bab14a30b79d9c8dd364 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17902: 1dad2fcca4f707aa870be1a45bb28bfb4c2b0f73 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17902/index.html From andriy.shevchenko at linux.intel.com Mon Jun 8 03:50:23 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Mon, 8 Jun 2020 06:50:23 +0300 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200607181840.13536-4-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-4-hdegoede@redhat.com> Message-ID: <20200608035023.GZ2428291@smile.fi.intel.com> On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote: > When the user requests a high enough period ns value, then the > calculations in pwm_lpss_prepare() might result in a base_unit value of 0. > > But according to the data-sheet the way the PWM controller works is that > each input clock-cycle the base_unit gets added to a N bit counter and > that counter overflowing determines the PWM output frequency. Adding 0 > to the counter is a no-op. The data-sheet even explicitly states that > writing 0 to the base_unit bits will result in the PWM outputting a > continuous 0 signal. So, and why it's a problem? > base_unit values > (base_unit_range / 256), or iow base_unit values using > the 8 most significant bits, cause loss of resolution of the duty-cycle. > E.g. assuming a base_unit_range of 65536 steps, then a base_unit value of > 768 (256 * 3), limits the duty-cycle resolution to 65536 / 768 = 85 steps. > Clamp the max base_unit value to base_unit_range / 32 to ensure a > duty-cycle resolution of at least 32 steps. This limits the maximum > output frequency to 600 KHz / 780 KHz depending on the base clock. This part I don't understand. Why we limiting base unit? I seems like a deliberate regression. -- With Best Regards, Andy Shevchenko From andriy.shevchenko at linux.intel.com Mon Jun 8 03:55:12 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Mon, 8 Jun 2020 06:55:12 +0300 Subject: [Intel-gfx] [PATCH v2 04/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() In-Reply-To: <20200607181840.13536-5-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-5-hdegoede@redhat.com> Message-ID: <20200608035512.GA2428291@smile.fi.intel.com> On Sun, Jun 07, 2020 at 08:18:29PM +0200, Hans de Goede wrote: > According to the data-sheet the way the PWM controller works is that > each input clock-cycle the base_unit gets added to a N bit counter and > that counter overflowing determines the PWM output frequency. > > So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, > after 65535 input clock-cycles the counter has been increased from 0 to > 65535 and it will overflow on the next cycle, so it will overflow after > every 65536 clock cycles and thus the calculations done in > pwm_lpss_prepare() should use 65536 and not 65535. > > This commit fixes this. Note this also aligns the calculations in > pwm_lpss_prepare() with those in pwm_lpss_get_state(). This one sounds like a bug which I have noticed on Broxton (but thought as a hardware issue). In any case it has to be tested on various platforms to see how it affects on them. -- With Best Regards, Andy Shevchenko From stanislav.lisovskiy at intel.com Mon Jun 8 06:55:52 2020 From: stanislav.lisovskiy at intel.com (Stanislav Lisovskiy) Date: Mon, 8 Jun 2020 09:55:52 +0300 Subject: [Intel-gfx] [PATCH] Revert "drm/i915: Remove unneeded hack now for CDCLK" Message-ID: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> This reverts commit 82ea174dc5425d4e85e25d0c4ba961a2e494392a. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs") --- drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 08468b121d02..45f7f33d1144 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2071,6 +2071,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) /* Account for additional needs from the planes */ min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); + /* + * HACK. Currently for TGL platforms we calculate + * min_cdclk initially based on pixel_rate divided + * by 2, accounting for also plane requirements, + * however in some cases the lowest possible CDCLK + * doesn't work and causing the underruns. + * Explicitly stating here that this seems to be currently + * rather a Hack, than final solution. + */ + if (IS_TIGERLAKE(dev_priv)) + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + if (min_cdclk > dev_priv->max_cdclk_freq) { drm_dbg_kms(&dev_priv->drm, "required cdclk (%d kHz) exceeds max (%d kHz)\n", -- 2.24.1.485.gad05a3d8e5 From jason.v.le at intel.com Mon Jun 8 06:56:35 2020 From: jason.v.le at intel.com (Jason Le) Date: Sun, 7 Jun 2020 23:56:35 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/display: Avoid PSR and FBC features concurently. Message-ID: <20200608065635.11652-1-jason.v.le@intel.com> Issue: Enble both PSR and FBC caused some fickers on some eDP panels (eg. Panel GIS 13.5" QHD Glare NE135FBM-N41/NC135GFL02). Disbling either PSR or FBC will solve this flicker issue. Both PSR and FBC features save power when render is not busy. When PSR is active, saving power achieved by source turning off source transmitter and main link, putting memory on self-refresh mode. Therefore with PSR enabled, FBC role is minimized since PSR power saving already covers most what FBC does. Disabling FBC in case to avoid conflict between PSR and FBC which causes display anomaly in some scenarios. Tests: Booted system with PSR enabled, verified FBC disabled. Disabled PSR with disabled (i915.enable_psr=0), verified FBC enabled. --- drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1c26673acb2d..52bc7483adb5 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1419,6 +1419,12 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", i915_modparams.enable_fbc); + if (i915_modparams.enable_psr) { + i915_modparams.enable_fbc = 0; + DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n"); + } + + if (!HAS_FBC(dev_priv)) { fbc->no_fbc_reason = "unsupported by this chipset"; return; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b7a2c102648a..25accfdd5ad3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1439,8 +1439,10 @@ void intel_psr_init(struct drm_i915_private *dev_priv) if (!HAS_PSR(dev_priv)) return; - if (!dev_priv->psr.sink_support) + if (!dev_priv->psr.sink_support) { + i915_modparams.enable_psr = 0; return; + } if (IS_HASWELL(dev_priv)) /* -- 2.17.1 From patchwork at emeril.freedesktop.org Mon Jun 8 07:30:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 07:30:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgUmV2?= =?utf-8?q?ert_=22drm/i915=3A_Remove_unneeded_hack_now_for_CDCLK=22?= In-Reply-To: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> References: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> Message-ID: <159160142913.14460.3636329240717288605@emeril.freedesktop.org> == Series Details == Series: Revert "drm/i915: Remove unneeded hack now for CDCLK" URL : https://patchwork.freedesktop.org/series/78106/ State : success == Summary == CI Bug Log - changes from CI_DRM_8599 -> Patchwork_17903 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/index.html Known issues ------------ Here are the changes found in Patchwork_17903 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 41) ------------------------------ Additional (1): fi-kbl-7560u Missing (6): fi-ilk-m540 fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8599 -> Patchwork_17903 CI-20190529: 20190529 CI_DRM_8599: 41ca9ea98b74c926c923e84931b9b4a4c3955e08 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5697: 5b8be04285ded1201fac5a2c2b50a7d70fa332d8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17903: c2441c67163365c1e27cf62805b377392b66feb6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c2441c671633 Revert "drm/i915: Remove unneeded hack now for CDCLK" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/index.html From patchwork at emeril.freedesktop.org Mon Jun 8 07:35:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 07:35:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/display=3A_Avoid_PSR_and_FBC_features_concurently?= =?utf-8?q?=2E?= In-Reply-To: <20200608065635.11652-1-jason.v.le@intel.com> References: <20200608065635.11652-1-jason.v.le@intel.com> Message-ID: <159160171892.14463.15984988829846214547@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Avoid PSR and FBC features concurently. URL : https://patchwork.freedesktop.org/series/78107/ State : warning == Summary == $ dim checkpatch origin/drm-tip dee7c897c6ed drm/i915/display: Avoid PSR and FBC features concurently. -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: Issue: Enble both PSR and FBC caused some fickers on some eDP panels (eg. Panel GIS -:6: WARNING:TYPO_SPELLING: 'Enble' may be misspelled - perhaps 'Enable'? #6: Issue: Enble both PSR and FBC caused some fickers on some eDP panels (eg. Panel GIS -:29: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 15) #29: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1422: + if (i915_modparams.enable_psr) { + i915_modparams.enable_fbc = 0; -:30: ERROR:CODE_INDENT: code indent should use tabs where possible #30: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1423: + i915_modparams.enable_fbc = 0;$ -:30: WARNING:LEADING_SPACE: please, no spaces at the start of a line #30: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1423: + i915_modparams.enable_fbc = 0;$ -:31: ERROR:CODE_INDENT: code indent should use tabs where possible #31: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1424: + DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n");$ -:31: WARNING:LEADING_SPACE: please, no spaces at the start of a line #31: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1424: + DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n");$ -:31: WARNING:QUOTED_WHITESPACE_BEFORE_NEWLINE: unnecessary whitespace before a quoted newline #31: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1424: + DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n"); -:34: CHECK:LINE_SPACING: Please don't use multiple blank lines #34: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:1427: + + -:53: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 3 errors, 6 warnings, 1 checks, 23 lines checked From tvrtko.ursulin at linux.intel.com Mon Jun 8 07:44:01 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 8 Jun 2020 08:44:01 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> On 07/06/2020 23:20, Chris Wilson wrote: > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Sentinels are supposed to be last reqeusts in the elsp queue, not the > only one, so adjust the assert accordingly. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- > 1 file changed, 3 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index d55a5e0466e5..db8a170b0e5c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > ccid = ce->lrc.ccid; > > /* > - * Sentinels are supposed to be lonely so they flush the > - * current exection off the HW. Check that they are the > - * only request in the pending submission. > + * Sentinels are supposed to be the last request so they flush > + * the current exection off the HW. Check that they are the only > + * request in the pending submission. > */ > if (sentinel) { > GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", > @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > port - execlists->pending); > return false; > } > - > sentinel = i915_request_has_sentinel(rq); FWIW I was changing it to "sentinel |= ..." so it keeps working if we decide to use more than 2 elsp ports on Icelake one day. Regards, Tvrtko > - if (sentinel && port != execlists->pending) { > - GEM_TRACE_ERR("%s: sentinel context:%llx not in prime position[%zd]\n", > - engine->name, > - ce->timeline->fence_context, > - port - execlists->pending); > - return false; > - } > > /* Hold tightly onto the lock to prevent concurrent retires! */ > if (!spin_trylock_irqsave(&rq->lock, flags)) > From jani.nikula at linux.intel.com Mon Jun 8 07:48:30 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Mon, 08 Jun 2020 10:48:30 +0300 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver In-Reply-To: <2136072.1591491984@warthog.procyon.org.uk> References: <2136072.1591491984@warthog.procyon.org.uk> Message-ID: <87o8puxak1.fsf@intel.com> On Sun, 07 Jun 2020, David Howells <dhowells at redhat.com> wrote: > Hi, > > I'm seeing the attached oops and panic from the i915 drm driver. I've tried > bisecting it, but there's a problem in that one of the merged branches causes > the machine to hang without output. Cc: Ville and GG, I thought this was fixed (reverted) already. BR, Jani. > > The oops for commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 looks like: > > BUG: kernel NULL pointer dereference, address: 0000000000000000 > #PF: supervisor read access in kernel mode > #PF: error_code(0x0000) - not-present page > PGD 0 P4D 0 > Oops: 0000 [#1] SMP PTI > CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.7.0-rc2-fscache+ #883 > Hardware name: ASUS All Series/H97-PLUS, BIOS 2306 10/09/2014 > RIP: 0010:intel_psr_enabled+0xb/0x6e > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 00 20 75 05 45 31 e4 eb 44 80 > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) knlGS:0000000000000000 > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 > Call Trace: > intel_read_dp_sdp+0x71/0x2c5 > hsw_crt_get_config+0x18/0x41 > intel_modeset_readout_hw_state+0x24d/0x662 > ? do_raw_spin_lock+0x8b/0xcd > ? _raw_spin_lock_irqsave+0x10/0x16 > intel_modeset_setup_hw_state+0xa8/0xb59 > ? __next_node_in+0x39/0x42 > ? ww_mutex_lock+0x3d/0x1da > ? modeset_lock+0xd4/0x114 > ? drm_modeset_lock_all_ctx+0x86/0xcc > intel_modeset_init+0x285/0x5bf > ? intel_irq_postinstall+0x485/0x4d1 > i915_driver_probe+0x1b4/0x49c > ? __kernfs_new_node+0x161/0x1b2 > ? rpm_resume+0x45e/0x485 > i915_pci_probe+0xfd/0x11d > ? __pm_runtime_resume+0x51/0x5e > local_pci_probe+0x39/0x7a > pci_device_probe+0xf5/0x14f > ? sysfs_do_create_link_sd.isra.0+0x77/0xa3 > really_probe+0x140/0x2a9 > driver_probe_device+0x9c/0xd1 > device_driver_attach+0x3c/0x55 > __driver_attach+0x97/0x9f > ? device_driver_attach+0x55/0x55 > bus_for_each_dev+0x72/0xa8 > bus_add_driver+0x108/0x1b9 > driver_register+0x9e/0xd7 > ? mipi_dsi_bus_init+0x11/0x11 > i915_init+0x58/0x6b > do_one_initcall+0x83/0x18a > kernel_init_freeable+0x19b/0x1fd > ? rest_init+0x9f/0x9f > kernel_init+0xa/0xfa > ret_from_fork+0x1f/0x30 > Modules linked in: > CR2: 0000000000000000 > ---[ end trace d0c4f561618aeb37 ]--- > RIP: 0010:intel_psr_enabled+0xb/0x6e > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 00 20 75 05 45 31 e4 eb 44 80 > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) knlGS:0000000000000000 > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 > Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 > Kernel Offset: disabled > ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 ]--- > > > Decoding the RIP gives: > > RIP: 0010:intel_psr_enabled (/data/fs/linux-fs/build3/../drivers/gpu/drm/i915/display/intel_display_types.h:1595 /data/fs/linux-fs/build3/../drivers/gpu/drm/i915/display/intel_psr.c:1598) > > > > Commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 ("Merge tag > 'drm-intel-next-fixes-2020-05-20' of > git://anongit.freedesktop.org/drm/drm-intel into drm-next") is definitely bad > and logs an oops to the console and panics, but it's a merge. > > On one side is e20bb857dea2f620ff37ae541ed8aee70e3c89f1 ("Merge tag > 'exynos-drm-next-for-v5.8' of > git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into > drm-next"), which hangs. This is also a merge. > > One side of e20bb is f84e1ba336a4f47ae251e4d2d8a694902571b0df > ("drm/exynos-vidi: convert platform driver to use dev_groups") which is good. > > The other side of c4121 and e20bb derive from the same line of commits, with > three patches between. All of these, down to at least > 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 ("drm/i915: Update DRIVER_DATE to > 20200430") cause the machine to hang without any sort of console output. > > Commit bfbe1744e4417986419236719922a9a7fda224d1 ("Merge tag > 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux > into drm-next") is good. > > Commit 47e51832ae93534d872511ba557115722582d94c > ("drm/i915/gvt: use context lrc_reg_state for shadow ppgtt override") is good. > > I've attached the git log and the config file. > > David > > git bisect start > # bad: [ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d] afs: Fix file locking > git bisect bad ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d > # good: [3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162] Linux 5.7 > git bisect good 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162 > # bad: [2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63] Merge branch 'uaccess.comedi' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs > git bisect bad 2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63 > # good: [cfa3b8068b09f25037146bfd5eed041b78878bee] Merge tag 'for-linus-hmm' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma > git bisect good cfa3b8068b09f25037146bfd5eed041b78878bee > # bad: [c41219fda6e04255c44d37fd2c0d898c1c46abf1] Merge tag 'drm-intel-next-fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next > git bisect bad c41219fda6e04255c44d37fd2c0d898c1c46abf1 > # good: [937eea297e26effac6809a0bf8c20e6ca9d90b9a] Merge tag 'amd-drm-next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-next > git bisect good 937eea297e26effac6809a0bf8c20e6ca9d90b9a > # good: [a1fb548962397bb8609bb46e566809a9a1b30044] Merge tag 'drm-intel-next-2020-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next > git bisect good a1fb548962397bb8609bb46e566809a9a1b30044 > # good: [f84e1ba336a4f47ae251e4d2d8a694902571b0df] drm/exynos-vidi: convert platform driver to use dev_groups > git bisect good f84e1ba336a4f47ae251e4d2d8a694902571b0df > # skip: [d9162348db12487754e61f73497bdcfcea753590] drm/i915: Introduce skl_plane_wm_level accessor. > git bisect skip d9162348db12487754e61f73497bdcfcea753590 > # skip: [84eac0c65940d9633247b0c8c826d4bcb7307351] drm/i915/gt: Force pte cacheline to main memory > git bisect skip 84eac0c65940d9633247b0c8c826d4bcb7307351 > # skip: [802a5820fc0c0f12b40280db3dbaaf8359b07243] drm/i915: Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}() > git bisect skip 802a5820fc0c0f12b40280db3dbaaf8359b07243 > # skip: [1c8ee8b92fb6ac9d5975147cc902e8c142eca338] drm/i915/gt: Restore Cherryview back to full-ppgtt > git bisect skip 1c8ee8b92fb6ac9d5975147cc902e8c142eca338 > # skip: [2e2701582a8039b2f8a2fa811237ac8ec98355fa] drm/i915: Nuke pointless div by 64bit > git bisect skip 2e2701582a8039b2f8a2fa811237ac8ec98355fa > # skip: [4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc] drm/i915/gt: Suspend tasklets before resume sanitization > git bisect skip 4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc > # skip: [20f505f2253106f695ba6fa0a415159145a8fb2a] drm/i915: Restrict qgv points which don't have enough bandwidth. > git bisect skip 20f505f2253106f695ba6fa0a415159145a8fb2a > # skip: [d8d5afe35e3f88f73436f79f974d96a67e879637] drm/i915: Make active_pipes check skl specific > git bisect skip d8d5afe35e3f88f73436f79f974d96a67e879637 > # skip: [1be8f347d70b5027b7b223c665756d85feaf36b6] Merge tag 'gvt-next-2020-05-12' of https://github.com/intel/gvt-linux into drm-intel-next-queued > git bisect skip 1be8f347d70b5027b7b223c665756d85feaf36b6 > # skip: [b428d57006663d18e3f6f98644ff9e8702a33ca4] drm/i915/gt: Reset execlists registers before HWSP > git bisect skip b428d57006663d18e3f6f98644ff9e8702a33ca4 > # skip: [6b6cd2ebd8d071e55998e32b648bb8081f7f02bb] drm/i915: Mark concurrent submissions with a weak-dependency > git bisect skip 6b6cd2ebd8d071e55998e32b648bb8081f7f02bb > # skip: [1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0] drm/i915: Extract skl SAGV checking > git bisect skip 1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0 > # skip: [cafac5a983619944afa639c53f0d5d885616a3d2] drm/i915/dp: Add compute routine for DP PSR VSC SDP > git bisect skip cafac5a983619944afa639c53f0d5d885616a3d2 > # skip: [61b088c5374a9f886efa1edbb49ce552bd1f9cba] drm/i915/ehl: Restrict w/a 1607087056 for EHL/JSL > git bisect skip 61b088c5374a9f886efa1edbb49ce552bd1f9cba > # skip: [2045d666ae634f1676660acfb864bcba0e9f86ca] drm/i915: Ignore submit-fences on the same timeline > git bisect skip 2045d666ae634f1676660acfb864bcba0e9f86ca > # skip: [16e87459673a5cbef35cc0f2e15c664b10a4cdb6] drm/i915/gt: Move the batch buffer pool from the engine to the gt > git bisect skip 16e87459673a5cbef35cc0f2e15c664b10a4cdb6 > # skip: [ce58867ee17afecda7917e74a0d10afd7138c6d4] drm/i915: Fix enabled infoframe states of lspcon > git bisect skip ce58867ee17afecda7917e74a0d10afd7138c6d4 > # skip: [a211da9c771bf97395a3ced83a3aa383372b13a7] drm/i915/gt: Make timeslicing an explicit engine property > git bisect skip a211da9c771bf97395a3ced83a3aa383372b13a7 > # skip: [dee66f3e071b394de16da18e2807f371b789b1be] drm/i915: Add state readout for DP HDR Metadata Infoframe SDP > git bisect skip dee66f3e071b394de16da18e2807f371b789b1be > # skip: [964a9b0f611ee7fedc90641bfcc2efe6ce6206aa] drm/i915/gem: Use chained reloc batches > git bisect skip 964a9b0f611ee7fedc90641bfcc2efe6ce6206aa > # skip: [f1e79c7e183c8e35def44b07ff7ac221fa87bf04] drm/i915: Replace zero-length array with flexible-array > git bisect skip f1e79c7e183c8e35def44b07ff7ac221fa87bf04 > # good: [ab9c21124d6e03460c9c59006a61cc076fefa82e] drm/amdgpu: Add cmd to control XGMI link sleep > git bisect good ab9c21124d6e03460c9c59006a61cc076fefa82e > # skip: [e31fe02eff2610f40ac8d7efe57ec0b881b75508] drm/i915: Make intel_timeline_init static > git bisect skip e31fe02eff2610f40ac8d7efe57ec0b881b75508 > # skip: [d96536f0fe699729a0974eb5b65eb0d87cc747e1] drm/i915: Fix AUX power domain toggling across TypeC mode resets > git bisect skip d96536f0fe699729a0974eb5b65eb0d87cc747e1 > # skip: [a80d73673bc7676d0bab7f7ab51d00c5e461992d] drm/i915: Tidy awaiting on dma-fences > git bisect skip a80d73673bc7676d0bab7f7ab51d00c5e461992d > # skip: [25444ca6cbb9fe375aa9bba58784a735efe2a649] drm/i915/fbc: Require linear fb stride to be multiple of 512 bytes on gen9/glk > git bisect skip 25444ca6cbb9fe375aa9bba58784a735efe2a649 > # skip: [795d4d7fa34154fc621c1048f8b92e4f6bd3926f] drm/i915: Mark the addition of the initial-breadcrumb in the request > git bisect skip 795d4d7fa34154fc621c1048f8b92e4f6bd3926f > # skip: [d19b29be653691a179e54aafc84fc40667a63ee7] drm/i915: Nuke mode.vrefresh usage > git bisect skip d19b29be653691a179e54aafc84fc40667a63ee7 > # skip: [260a6c1bdf1e072ae4d96f0d1ec2917237f1b627] drm/i915: Fix glk watermark calculations > git bisect skip 260a6c1bdf1e072ae4d96f0d1ec2917237f1b627 > # skip: [56f1b31f1dd60db4b02024a13eea45b5bbccc44e] drm/i915: Store CS timestamp frequency in Hz > git bisect skip 56f1b31f1dd60db4b02024a13eea45b5bbccc44e > # skip: [b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d] drm/i915: Remove duplicate inline specifier on write_pte > git bisect skip b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d > # skip: [0065e5f5cc56136da0be900c4a3121b38a82f37d] drm/i915/display: Warn if the FBC is still writing to stolen on removal > git bisect skip 0065e5f5cc56136da0be900c4a3121b38a82f37d > # skip: [0398993b82f40ad02d88da7c894e3faae2da3b0a] drm/i915: Stash hpd status bits under dev_priv > git bisect skip 0398993b82f40ad02d88da7c894e3faae2da3b0a > # skip: [7241c57d3140ad3b613777a8515ffe1f653d4800] drm/i915: Add TGL+ SAGV support > git bisect skip 7241c57d3140ad3b613777a8515ffe1f653d4800 > # skip: [c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5] drm/i915: Use stashed away hpd isr bits in intel_digital_port_connected() > git bisect skip c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5 > # skip: [f136c58a0de98e1b56483b7fc8c209dba0a496d9] drm/i915: Added required new PCode commands > git bisect skip f136c58a0de98e1b56483b7fc8c209dba0a496d9 > # skip: [9bad40a27dac1f88012a1e2db0bfc5ae58fa0370] drm/i915/selftests: Always flush before unpining after writing > git bisect skip 9bad40a27dac1f88012a1e2db0bfc5ae58fa0370 > # skip: [977253df6433f85d5e2cb3ab0f8eb4127f8173dd] drm/i915/gt: Stop holding onto the pinned_default_state > git bisect skip 977253df6433f85d5e2cb3ab0f8eb4127f8173dd > # skip: [a1b2eeacbc55573afc56341e08b506aee6451c3d] drm/i915: Remove unused HAS_FWTABLE macro > git bisect skip a1b2eeacbc55573afc56341e08b506aee6451c3d > # skip: [24fe5f2ab2478053d50a3bc629ada895903a5cbc] drm/i915: Propagate error from completed fences > git bisect skip 24fe5f2ab2478053d50a3bc629ada895903a5cbc > # skip: [73e28cc40bf00b5d168cb8f5cff1ae63e9097446] drm/i915: Handle idling during i915_gem_evict_something busy loops > git bisect skip 73e28cc40bf00b5d168cb8f5cff1ae63e9097446 > # skip: [f02ac414ba9497d1887b1de7fe69954284f157ac] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" > git bisect skip f02ac414ba9497d1887b1de7fe69954284f157ac > # skip: [b0a997ae5248b293b6f6d1996ea49c57f7b94227] drm/i915: Emit await(batch) before MI_BB_START > git bisect skip b0a997ae5248b293b6f6d1996ea49c57f7b94227 > # skip: [32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa] drm/i915/gen12: Fix HDC pipeline flush > git bisect skip 32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa > # good: [5e7067b24fcf1549c72988dd92de6d17ff3d2077] drm/amdgpu: Add DPM function for XGMI link power down control > git bisect good 5e7067b24fcf1549c72988dd92de6d17ff3d2077 > # skip: [d248b371f7479a99caccf91da2ec6adee85e5e70] drm/i915/gen12: Invalidate aux table entries forcibly > git bisect skip d248b371f7479a99caccf91da2ec6adee85e5e70 > # good: [b7f0656a25467fc26eb7fc375caf38ee99f5d004] drm/amdgpu: Updated XGMI power down control support check > git bisect good b7f0656a25467fc26eb7fc375caf38ee99f5d004 > # good: [4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240] drm/amdgpu: optimize amdgpu device attribute code > git bisect good 4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240 > # skip: [f45ce9336ff0640e491c642a84ea02f21daac3a4] video/hdmi: Add Unpack only function for DRM infoframe > git bisect skip f45ce9336ff0640e491c642a84ea02f21daac3a4 > # good: [bfbe1744e4417986419236719922a9a7fda224d1] Merge tag 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux into drm-next > git bisect good bfbe1744e4417986419236719922a9a7fda224d1 > # skip: [701f026521980dd0151130f818558e17c608ed2e] drm/i915: Drop I915_RESET_TIMEOUT and friends > git bisect skip 701f026521980dd0151130f818558e17c608ed2e > # skip: [378974f7f9754acfd5630327917c6b813495f1a9] drm/i915: Allow some leniency in PCU reads > git bisect skip 378974f7f9754acfd5630327917c6b813495f1a9 > # good: [47e51832ae93534d872511ba557115722582d94c] drm/i915/gvt: use context lrc_reg_state for shadow ppgtt override > git bisect good 47e51832ae93534d872511ba557115722582d94c > # skip: [230982d8d8df7f9d9aa216840ea2db1df6ad5d37] drm/i915: Update DRIVER_DATE to 20200430 > git bisect skip 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 > # > # Automatically generated file; DO NOT EDIT. > # Linux/x86_64 5.7.0-rc2 Kernel Configuration > # > > # > # Compiler: x86_64-linux-gnu-gcc (GCC) 9.2.1 20190827 (Red Hat Cross 9.2.1-3) > # > CONFIG_CC_IS_GCC=y > CONFIG_GCC_VERSION=90201 > CONFIG_LD_VERSION=234000000 > CONFIG_CLANG_VERSION=0 > CONFIG_CC_HAS_ASM_GOTO=y > CONFIG_CC_HAS_ASM_INLINE=y > CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y > CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y > CONFIG_IRQ_WORK=y > CONFIG_BUILDTIME_TABLE_SORT=y > CONFIG_THREAD_INFO_IN_TASK=y > > # > # General setup > # > CONFIG_INIT_ENV_ARG_LIMIT=32 > # CONFIG_COMPILE_TEST is not set > CONFIG_LOCALVERSION="-fscache" > # CONFIG_LOCALVERSION_AUTO is not set > CONFIG_BUILD_SALT="" > CONFIG_HAVE_KERNEL_GZIP=y > CONFIG_HAVE_KERNEL_BZIP2=y > CONFIG_HAVE_KERNEL_LZMA=y > CONFIG_HAVE_KERNEL_XZ=y > CONFIG_HAVE_KERNEL_LZO=y > CONFIG_HAVE_KERNEL_LZ4=y > # CONFIG_KERNEL_GZIP is not set > # CONFIG_KERNEL_BZIP2 is not set > # CONFIG_KERNEL_LZMA is not set > CONFIG_KERNEL_XZ=y > # CONFIG_KERNEL_LZO is not set > # CONFIG_KERNEL_LZ4 is not set > CONFIG_DEFAULT_HOSTNAME="(none)" > CONFIG_SWAP=y > CONFIG_SYSVIPC=y > CONFIG_SYSVIPC_SYSCTL=y > CONFIG_POSIX_MQUEUE=y > CONFIG_POSIX_MQUEUE_SYSCTL=y > CONFIG_CROSS_MEMORY_ATTACH=y > # CONFIG_USELIB is not set > CONFIG_AUDIT=y > CONFIG_HAVE_ARCH_AUDITSYSCALL=y > CONFIG_AUDITSYSCALL=y > > # > # IRQ subsystem > # > CONFIG_GENERIC_IRQ_PROBE=y > CONFIG_GENERIC_IRQ_SHOW=y > CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y > CONFIG_GENERIC_PENDING_IRQ=y > CONFIG_GENERIC_IRQ_MIGRATION=y > CONFIG_HARDIRQS_SW_RESEND=y > CONFIG_IRQ_DOMAIN=y > CONFIG_IRQ_DOMAIN_HIERARCHY=y > CONFIG_GENERIC_MSI_IRQ=y > CONFIG_GENERIC_MSI_IRQ_DOMAIN=y > CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y > CONFIG_GENERIC_IRQ_RESERVATION_MODE=y > CONFIG_IRQ_FORCED_THREADING=y > CONFIG_SPARSE_IRQ=y > # CONFIG_GENERIC_IRQ_DEBUGFS is not set > # end of IRQ subsystem > > CONFIG_CLOCKSOURCE_WATCHDOG=y > CONFIG_ARCH_CLOCKSOURCE_INIT=y > CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y > CONFIG_GENERIC_TIME_VSYSCALL=y > CONFIG_GENERIC_CLOCKEVENTS=y > CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y > CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y > CONFIG_GENERIC_CMOS_UPDATE=y > > # > # Timers subsystem > # > CONFIG_TICK_ONESHOT=y > CONFIG_NO_HZ_COMMON=y > # CONFIG_HZ_PERIODIC is not set > # CONFIG_NO_HZ_IDLE is not set > CONFIG_NO_HZ_FULL=y > CONFIG_CONTEXT_TRACKING=y > CONFIG_CONTEXT_TRACKING_FORCE=y > # CONFIG_NO_HZ is not set > CONFIG_HIGH_RES_TIMERS=y > # end of Timers subsystem > > CONFIG_PREEMPT_NONE=y > # CONFIG_PREEMPT_VOLUNTARY is not set > # CONFIG_PREEMPT is not set > > # > # CPU/Task time and stats accounting > # > CONFIG_VIRT_CPU_ACCOUNTING=y > CONFIG_VIRT_CPU_ACCOUNTING_GEN=y > # CONFIG_IRQ_TIME_ACCOUNTING is not set > # CONFIG_SCHED_THERMAL_PRESSURE is not set > CONFIG_BSD_PROCESS_ACCT=y > CONFIG_BSD_PROCESS_ACCT_V3=y > CONFIG_TASKSTATS=y > CONFIG_TASK_DELAY_ACCT=y > CONFIG_TASK_XACCT=y > CONFIG_TASK_IO_ACCOUNTING=y > # CONFIG_PSI is not set > # end of CPU/Task time and stats accounting > > CONFIG_CPU_ISOLATION=y > > # > # RCU Subsystem > # > CONFIG_TREE_RCU=y > # CONFIG_RCU_EXPERT is not set > CONFIG_SRCU=y > CONFIG_TREE_SRCU=y > CONFIG_RCU_STALL_COMMON=y > CONFIG_RCU_NEED_SEGCBLIST=y > CONFIG_RCU_NOCB_CPU=y > # end of RCU Subsystem > > CONFIG_BUILD_BIN2C=y > # CONFIG_IKCONFIG is not set > # CONFIG_IKHEADERS is not set > CONFIG_LOG_BUF_SHIFT=16 > CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 > CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 > CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y > > # > # Scheduler features > # > # CONFIG_UCLAMP_TASK is not set > # end of Scheduler features > > CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y > CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y > CONFIG_CC_HAS_INT128=y > CONFIG_ARCH_SUPPORTS_INT128=y > # CONFIG_NUMA_BALANCING is not set > CONFIG_CGROUPS=y > CONFIG_PAGE_COUNTER=y > CONFIG_MEMCG=y > CONFIG_MEMCG_SWAP=y > CONFIG_MEMCG_SWAP_ENABLED=y > CONFIG_MEMCG_KMEM=y > CONFIG_BLK_CGROUP=y > CONFIG_CGROUP_WRITEBACK=y > CONFIG_CGROUP_SCHED=y > CONFIG_FAIR_GROUP_SCHED=y > # CONFIG_CFS_BANDWIDTH is not set > # CONFIG_RT_GROUP_SCHED is not set > # CONFIG_CGROUP_PIDS is not set > CONFIG_CGROUP_RDMA=y > CONFIG_CGROUP_FREEZER=y > CONFIG_CGROUP_HUGETLB=y > CONFIG_CPUSETS=y > CONFIG_PROC_PID_CPUSET=y > CONFIG_CGROUP_DEVICE=y > CONFIG_CGROUP_CPUACCT=y > CONFIG_CGROUP_PERF=y > # CONFIG_CGROUP_BPF is not set > # CONFIG_CGROUP_DEBUG is not set > CONFIG_SOCK_CGROUP_DATA=y > CONFIG_NAMESPACES=y > CONFIG_UTS_NS=y > CONFIG_TIME_NS=y > CONFIG_IPC_NS=y > CONFIG_USER_NS=y > CONFIG_PID_NS=y > CONFIG_NET_NS=y > # CONFIG_CHECKPOINT_RESTORE is not set > # CONFIG_SCHED_AUTOGROUP is not set > # CONFIG_SYSFS_DEPRECATED is not set > CONFIG_RELAY=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_INITRAMFS_SOURCE="" > CONFIG_RD_GZIP=y > # CONFIG_RD_BZIP2 is not set > # CONFIG_RD_LZMA is not set > # CONFIG_RD_XZ is not set > # CONFIG_RD_LZO is not set > # CONFIG_RD_LZ4 is not set > # CONFIG_BOOT_CONFIG is not set > # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set > CONFIG_CC_OPTIMIZE_FOR_SIZE=y > CONFIG_SYSCTL=y > CONFIG_HAVE_UID16=y > CONFIG_SYSCTL_EXCEPTION_TRACE=y > CONFIG_HAVE_PCSPKR_PLATFORM=y > CONFIG_BPF=y > CONFIG_EXPERT=y > CONFIG_UID16=y > CONFIG_MULTIUSER=y > # CONFIG_SGETMASK_SYSCALL is not set > # CONFIG_SYSFS_SYSCALL is not set > CONFIG_FHANDLE=y > CONFIG_POSIX_TIMERS=y > CONFIG_PRINTK=y > CONFIG_PRINTK_NMI=y > CONFIG_BUG=y > CONFIG_ELF_CORE=y > CONFIG_PCSPKR_PLATFORM=y > CONFIG_BASE_FULL=y > CONFIG_FUTEX=y > CONFIG_FUTEX_PI=y > CONFIG_EPOLL=y > CONFIG_SIGNALFD=y > CONFIG_TIMERFD=y > CONFIG_EVENTFD=y > CONFIG_SHMEM=y > CONFIG_AIO=y > # CONFIG_IO_URING is not set > CONFIG_ADVISE_SYSCALLS=y > CONFIG_MEMBARRIER=y > CONFIG_KALLSYMS=y > CONFIG_KALLSYMS_ALL=y > CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y > CONFIG_KALLSYMS_BASE_RELATIVE=y > CONFIG_BPF_SYSCALL=y > CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y > # CONFIG_USERFAULTFD is not set > CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y > CONFIG_RSEQ=y > # CONFIG_DEBUG_RSEQ is not set > # CONFIG_EMBEDDED is not set > CONFIG_HAVE_PERF_EVENTS=y > # CONFIG_PC104 is not set > > # > # Kernel Performance Events And Counters > # > CONFIG_PERF_EVENTS=y > # CONFIG_DEBUG_PERF_USE_VMALLOC is not set > # end of Kernel Performance Events And Counters > > CONFIG_VM_EVENT_COUNTERS=y > CONFIG_COMPAT_BRK=y > CONFIG_SLAB=y > # CONFIG_SLUB is not set > # CONFIG_SLOB is not set > CONFIG_SLAB_MERGE_DEFAULT=y > # CONFIG_SLAB_FREELIST_RANDOM is not set > # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set > CONFIG_SYSTEM_DATA_VERIFICATION=y > # CONFIG_PROFILING is not set > CONFIG_TRACEPOINTS=y > # end of General setup > > CONFIG_64BIT=y > CONFIG_X86_64=y > CONFIG_X86=y > CONFIG_INSTRUCTION_DECODER=y > CONFIG_OUTPUT_FORMAT="elf64-x86-64" > CONFIG_LOCKDEP_SUPPORT=y > CONFIG_STACKTRACE_SUPPORT=y > CONFIG_MMU=y > CONFIG_ARCH_MMAP_RND_BITS_MIN=28 > CONFIG_ARCH_MMAP_RND_BITS_MAX=32 > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 > CONFIG_GENERIC_ISA_DMA=y > CONFIG_GENERIC_BUG=y > CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y > CONFIG_ARCH_MAY_HAVE_PC_FDC=y > CONFIG_GENERIC_CALIBRATE_DELAY=y > CONFIG_ARCH_HAS_CPU_RELAX=y > CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y > CONFIG_ARCH_HAS_FILTER_PGPROT=y > CONFIG_HAVE_SETUP_PER_CPU_AREA=y > CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y > CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y > CONFIG_ARCH_HIBERNATION_POSSIBLE=y > CONFIG_ARCH_SUSPEND_POSSIBLE=y > CONFIG_ARCH_WANT_GENERAL_HUGETLB=y > CONFIG_ZONE_DMA32=y > CONFIG_AUDIT_ARCH=y > CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y > CONFIG_HAVE_INTEL_TXT=y > CONFIG_X86_64_SMP=y > CONFIG_ARCH_SUPPORTS_UPROBES=y > CONFIG_FIX_EARLYCON_MEM=y > CONFIG_PGTABLE_LEVELS=4 > CONFIG_CC_HAS_SANE_STACKPROTECTOR=y > > # > # Processor type and features > # > CONFIG_ZONE_DMA=y > CONFIG_SMP=y > CONFIG_X86_FEATURE_NAMES=y > CONFIG_X86_MPPARSE=y > # CONFIG_GOLDFISH is not set > # CONFIG_RETPOLINE is not set > CONFIG_X86_CPU_RESCTRL=y > # CONFIG_X86_EXTENDED_PLATFORM is not set > # CONFIG_X86_INTEL_LPSS is not set > # CONFIG_X86_AMD_PLATFORM_DEVICE is not set > CONFIG_IOSF_MBI=y > # CONFIG_IOSF_MBI_DEBUG is not set > CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y > # CONFIG_SCHED_OMIT_FRAME_POINTER is not set > # CONFIG_HYPERVISOR_GUEST is not set > # CONFIG_MK8 is not set > # CONFIG_MPSC is not set > CONFIG_MCORE2=y > # CONFIG_MATOM is not set > # CONFIG_GENERIC_CPU is not set > CONFIG_X86_INTERNODE_CACHE_SHIFT=6 > CONFIG_X86_L1_CACHE_SHIFT=6 > CONFIG_X86_INTEL_USERCOPY=y > CONFIG_X86_USE_PPRO_CHECKSUM=y > CONFIG_X86_P6_NOP=y > CONFIG_X86_TSC=y > CONFIG_X86_CMPXCHG64=y > CONFIG_X86_CMOV=y > CONFIG_X86_MINIMUM_CPU_FAMILY=64 > CONFIG_X86_DEBUGCTLMSR=y > CONFIG_IA32_FEAT_CTL=y > CONFIG_X86_VMX_FEATURE_NAMES=y > # CONFIG_PROCESSOR_SELECT is not set > CONFIG_CPU_SUP_INTEL=y > CONFIG_CPU_SUP_AMD=y > CONFIG_CPU_SUP_HYGON=y > CONFIG_CPU_SUP_CENTAUR=y > CONFIG_CPU_SUP_ZHAOXIN=y > CONFIG_HPET_TIMER=y > CONFIG_HPET_EMULATE_RTC=y > CONFIG_DMI=y > CONFIG_GART_IOMMU=y > # CONFIG_MAXSMP is not set > CONFIG_NR_CPUS_RANGE_BEGIN=2 > CONFIG_NR_CPUS_RANGE_END=512 > CONFIG_NR_CPUS_DEFAULT=64 > CONFIG_NR_CPUS=4 > CONFIG_SCHED_SMT=y > CONFIG_SCHED_MC=y > CONFIG_SCHED_MC_PRIO=y > CONFIG_X86_LOCAL_APIC=y > CONFIG_X86_IO_APIC=y > # CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set > CONFIG_X86_MCE=y > # CONFIG_X86_MCELOG_LEGACY is not set > CONFIG_X86_MCE_INTEL=y > # CONFIG_X86_MCE_AMD is not set > CONFIG_X86_MCE_THRESHOLD=y > # CONFIG_X86_MCE_INJECT is not set > CONFIG_X86_THERMAL_VECTOR=y > > # > # Performance monitoring > # > CONFIG_PERF_EVENTS_INTEL_UNCORE=y > CONFIG_PERF_EVENTS_INTEL_RAPL=y > CONFIG_PERF_EVENTS_INTEL_CSTATE=y > # CONFIG_PERF_EVENTS_AMD_POWER is not set > # end of Performance monitoring > > CONFIG_X86_16BIT=y > CONFIG_X86_ESPFIX64=y > CONFIG_X86_VSYSCALL_EMULATION=y > # CONFIG_X86_IOPL_IOPERM is not set > # CONFIG_I8K is not set > # CONFIG_MICROCODE is not set > CONFIG_X86_MSR=y > CONFIG_X86_CPUID=y > # CONFIG_X86_5LEVEL is not set > CONFIG_X86_DIRECT_GBPAGES=y > # CONFIG_X86_CPA_STATISTICS is not set > # CONFIG_AMD_MEM_ENCRYPT is not set > CONFIG_NUMA=y > # CONFIG_AMD_NUMA is not set > CONFIG_X86_64_ACPI_NUMA=y > CONFIG_NODES_SPAN_OTHER_NODES=y > # CONFIG_NUMA_EMU is not set > CONFIG_NODES_SHIFT=6 > CONFIG_ARCH_SPARSEMEM_ENABLE=y > CONFIG_ARCH_SPARSEMEM_DEFAULT=y > CONFIG_ARCH_SELECT_MEMORY_MODEL=y > CONFIG_ARCH_PROC_KCORE_TEXT=y > CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 > # CONFIG_X86_PMEM_LEGACY is not set > # CONFIG_X86_CHECK_BIOS_CORRUPTION is not set > CONFIG_X86_RESERVE_LOW=64 > CONFIG_MTRR=y > # CONFIG_MTRR_SANITIZER is not set > CONFIG_X86_PAT=y > CONFIG_ARCH_USES_PG_UNCACHED=y > CONFIG_ARCH_RANDOM=y > CONFIG_X86_SMAP=y > CONFIG_X86_UMIP=y > CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y > CONFIG_X86_INTEL_TSX_MODE_OFF=y > # CONFIG_X86_INTEL_TSX_MODE_ON is not set > # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set > CONFIG_EFI=y > CONFIG_EFI_STUB=y > # CONFIG_EFI_MIXED is not set > CONFIG_SECCOMP=y > # CONFIG_HZ_100 is not set > CONFIG_HZ_250=y > # CONFIG_HZ_300 is not set > # CONFIG_HZ_1000 is not set > CONFIG_HZ=250 > CONFIG_SCHED_HRTICK=y > CONFIG_KEXEC=y > CONFIG_KEXEC_FILE=y > CONFIG_ARCH_HAS_KEXEC_PURGATORY=y > # CONFIG_KEXEC_SIG is not set > # CONFIG_CRASH_DUMP is not set > CONFIG_PHYSICAL_START=0x1000000 > CONFIG_RELOCATABLE=y > # CONFIG_RANDOMIZE_BASE is not set > CONFIG_PHYSICAL_ALIGN=0x1000000 > CONFIG_HOTPLUG_CPU=y > # CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set > # CONFIG_DEBUG_HOTPLUG_CPU0 is not set > CONFIG_COMPAT_VDSO=y > # CONFIG_LEGACY_VSYSCALL_EMULATE is not set > CONFIG_LEGACY_VSYSCALL_XONLY=y > # CONFIG_LEGACY_VSYSCALL_NONE is not set > # CONFIG_CMDLINE_BOOL is not set > CONFIG_MODIFY_LDT_SYSCALL=y > CONFIG_HAVE_LIVEPATCH=y > CONFIG_LIVEPATCH=y > # end of Processor type and features > > CONFIG_ARCH_HAS_ADD_PAGES=y > CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y > CONFIG_USE_PERCPU_NUMA_NODE_ID=y > CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y > CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y > > # > # Power management and ACPI options > # > # CONFIG_SUSPEND is not set > # CONFIG_HIBERNATION is not set > CONFIG_PM=y > # CONFIG_PM_DEBUG is not set > CONFIG_PM_CLK=y > CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y > CONFIG_ENERGY_MODEL=y > CONFIG_ARCH_SUPPORTS_ACPI=y > CONFIG_ACPI=y > CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y > CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y > CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y > # CONFIG_ACPI_DEBUGGER is not set > CONFIG_ACPI_SPCR_TABLE=y > CONFIG_ACPI_LPIT=y > # CONFIG_ACPI_PROCFS_POWER is not set > CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y > # CONFIG_ACPI_EC_DEBUGFS is not set > CONFIG_ACPI_AC=y > # CONFIG_ACPI_BATTERY is not set > CONFIG_ACPI_BUTTON=y > CONFIG_ACPI_VIDEO=y > CONFIG_ACPI_FAN=y > CONFIG_ACPI_DOCK=y > CONFIG_ACPI_CPU_FREQ_PSS=y > CONFIG_ACPI_PROCESSOR_CSTATE=y > CONFIG_ACPI_PROCESSOR_IDLE=y > CONFIG_ACPI_CPPC_LIB=y > CONFIG_ACPI_PROCESSOR=y > # CONFIG_ACPI_IPMI is not set > CONFIG_ACPI_HOTPLUG_CPU=y > CONFIG_ACPI_PROCESSOR_AGGREGATOR=y > CONFIG_ACPI_THERMAL=y > CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y > CONFIG_ACPI_TABLE_UPGRADE=y > CONFIG_ACPI_DEBUG=y > # CONFIG_ACPI_PCI_SLOT is not set > CONFIG_ACPI_CONTAINER=y > CONFIG_ACPI_HOTPLUG_IOAPIC=y > # CONFIG_ACPI_SBS is not set > CONFIG_ACPI_HED=y > # CONFIG_ACPI_CUSTOM_METHOD is not set > # CONFIG_ACPI_BGRT is not set > # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set > # CONFIG_ACPI_NFIT is not set > CONFIG_ACPI_NUMA=y > # CONFIG_ACPI_HMAT is not set > CONFIG_HAVE_ACPI_APEI=y > CONFIG_HAVE_ACPI_APEI_NMI=y > CONFIG_ACPI_APEI=y > CONFIG_ACPI_APEI_GHES=y > # CONFIG_ACPI_APEI_PCIEAER is not set > CONFIG_ACPI_APEI_EINJ=y > # CONFIG_ACPI_APEI_ERST_DEBUG is not set > # CONFIG_DPTF_POWER is not set > # CONFIG_PMIC_OPREGION is not set > # CONFIG_ACPI_CONFIGFS is not set > CONFIG_X86_PM_TIMER=y > # CONFIG_SFI is not set > > # > # CPU Frequency scaling > # > CONFIG_CPU_FREQ=y > CONFIG_CPU_FREQ_GOV_ATTR_SET=y > CONFIG_CPU_FREQ_GOV_COMMON=y > CONFIG_CPU_FREQ_STAT=y > # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set > # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set > # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set > # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set > CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y > # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set > CONFIG_CPU_FREQ_GOV_PERFORMANCE=y > CONFIG_CPU_FREQ_GOV_POWERSAVE=y > CONFIG_CPU_FREQ_GOV_USERSPACE=y > CONFIG_CPU_FREQ_GOV_ONDEMAND=y > CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y > CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y > > # > # CPU frequency scaling drivers > # > CONFIG_X86_INTEL_PSTATE=y > CONFIG_X86_PCC_CPUFREQ=y > CONFIG_X86_ACPI_CPUFREQ=y > # CONFIG_X86_ACPI_CPUFREQ_CPB is not set > # CONFIG_X86_POWERNOW_K8 is not set > # CONFIG_X86_AMD_FREQ_SENSITIVITY is not set > # CONFIG_X86_SPEEDSTEP_CENTRINO is not set > # CONFIG_X86_P4_CLOCKMOD is not set > > # > # shared options > # > # end of CPU Frequency scaling > > # > # CPU Idle > # > CONFIG_CPU_IDLE=y > CONFIG_CPU_IDLE_GOV_LADDER=y > CONFIG_CPU_IDLE_GOV_MENU=y > # CONFIG_CPU_IDLE_GOV_TEO is not set > # end of CPU Idle > > CONFIG_INTEL_IDLE=y > # end of Power management and ACPI options > > # > # Bus options (PCI etc.) > # > CONFIG_PCI_DIRECT=y > CONFIG_PCI_MMCONFIG=y > CONFIG_MMCONF_FAM10H=y > # CONFIG_PCI_CNB20LE_QUIRK is not set > # CONFIG_ISA_BUS is not set > CONFIG_ISA_DMA_API=y > CONFIG_AMD_NB=y > # CONFIG_X86_SYSFB is not set > # end of Bus options (PCI etc.) > > # > # Binary Emulations > # > CONFIG_IA32_EMULATION=y > # CONFIG_X86_X32 is not set > CONFIG_COMPAT_32=y > CONFIG_COMPAT=y > CONFIG_COMPAT_FOR_U64_ALIGNMENT=y > CONFIG_SYSVIPC_COMPAT=y > # end of Binary Emulations > > # > # Firmware Drivers > # > # CONFIG_EDD is not set > CONFIG_FIRMWARE_MEMMAP=y > CONFIG_DMIID=y > # CONFIG_DMI_SYSFS is not set > CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y > # CONFIG_FW_CFG_SYSFS is not set > # CONFIG_GOOGLE_FIRMWARE is not set > > # > # EFI (Extensible Firmware Interface) Support > # > # CONFIG_EFI_VARS is not set > CONFIG_EFI_ESRT=y > CONFIG_EFI_RUNTIME_MAP=y > # CONFIG_EFI_FAKE_MEMMAP is not set > CONFIG_EFI_RUNTIME_WRAPPERS=y > # CONFIG_EFI_CAPSULE_LOADER is not set > # CONFIG_EFI_TEST is not set > # CONFIG_APPLE_PROPERTIES is not set > # CONFIG_RESET_ATTACK_MITIGATION is not set > # CONFIG_EFI_RCI2_TABLE is not set > # CONFIG_EFI_DISABLE_PCI_DMA is not set > # end of EFI (Extensible Firmware Interface) Support > > CONFIG_UEFI_CPER=y > CONFIG_UEFI_CPER_X86=y > CONFIG_EFI_EARLYCON=y > > # > # Tegra firmware driver > # > # end of Tegra firmware driver > # end of Firmware Drivers > > CONFIG_HAVE_KVM=y > # CONFIG_VIRTUALIZATION is not set > CONFIG_AS_AVX512=y > CONFIG_AS_SHA1_NI=y > CONFIG_AS_SHA256_NI=y > > # > # General architecture-dependent options > # > CONFIG_CRASH_CORE=y > CONFIG_KEXEC_CORE=y > CONFIG_HOTPLUG_SMT=y > CONFIG_HAVE_OPROFILE=y > CONFIG_OPROFILE_NMI_TIMER=y > CONFIG_KPROBES=y > CONFIG_JUMP_LABEL=y > # CONFIG_STATIC_KEYS_SELFTEST is not set > CONFIG_OPTPROBES=y > CONFIG_KPROBES_ON_FTRACE=y > CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y > CONFIG_ARCH_USE_BUILTIN_BSWAP=y > CONFIG_KRETPROBES=y > CONFIG_HAVE_IOREMAP_PROT=y > CONFIG_HAVE_KPROBES=y > CONFIG_HAVE_KRETPROBES=y > CONFIG_HAVE_OPTPROBES=y > CONFIG_HAVE_KPROBES_ON_FTRACE=y > CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y > CONFIG_HAVE_NMI=y > CONFIG_HAVE_ARCH_TRACEHOOK=y > CONFIG_HAVE_DMA_CONTIGUOUS=y > CONFIG_GENERIC_SMP_IDLE_THREAD=y > CONFIG_ARCH_HAS_FORTIFY_SOURCE=y > CONFIG_ARCH_HAS_SET_MEMORY=y > CONFIG_ARCH_HAS_SET_DIRECT_MAP=y > CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y > CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y > CONFIG_HAVE_ASM_MODVERSIONS=y > CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y > CONFIG_HAVE_RSEQ=y > CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y > CONFIG_HAVE_CLK=y > CONFIG_HAVE_HW_BREAKPOINT=y > CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y > CONFIG_HAVE_USER_RETURN_NOTIFIER=y > CONFIG_HAVE_PERF_EVENTS_NMI=y > CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y > CONFIG_HAVE_PERF_REGS=y > CONFIG_HAVE_PERF_USER_STACK_DUMP=y > CONFIG_HAVE_ARCH_JUMP_LABEL=y > CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y > CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y > CONFIG_HAVE_CMPXCHG_LOCAL=y > CONFIG_HAVE_CMPXCHG_DOUBLE=y > CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y > CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y > CONFIG_HAVE_ARCH_SECCOMP_FILTER=y > CONFIG_SECCOMP_FILTER=y > CONFIG_HAVE_ARCH_STACKLEAK=y > CONFIG_HAVE_STACKPROTECTOR=y > CONFIG_CC_HAS_STACKPROTECTOR_NONE=y > CONFIG_STACKPROTECTOR=y > CONFIG_STACKPROTECTOR_STRONG=y > CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y > CONFIG_HAVE_CONTEXT_TRACKING=y > CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y > CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y > CONFIG_HAVE_MOVE_PMD=y > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y > CONFIG_HAVE_ARCH_HUGE_VMAP=y > CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y > CONFIG_HAVE_ARCH_SOFT_DIRTY=y > CONFIG_HAVE_MOD_ARCH_SPECIFIC=y > CONFIG_MODULES_USE_ELF_RELA=y > CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y > CONFIG_ARCH_HAS_ELF_RANDOMIZE=y > CONFIG_HAVE_ARCH_MMAP_RND_BITS=y > CONFIG_HAVE_EXIT_THREAD=y > CONFIG_ARCH_MMAP_RND_BITS=28 > CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y > CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 > CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y > CONFIG_HAVE_COPY_THREAD_TLS=y > CONFIG_HAVE_STACK_VALIDATION=y > CONFIG_HAVE_RELIABLE_STACKTRACE=y > CONFIG_OLD_SIGSUSPEND3=y > CONFIG_COMPAT_OLD_SIGACTION=y > CONFIG_COMPAT_32BIT_TIME=y > CONFIG_HAVE_ARCH_VMAP_STACK=y > # CONFIG_VMAP_STACK is not set > CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y > CONFIG_STRICT_KERNEL_RWX=y > CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y > CONFIG_STRICT_MODULE_RWX=y > CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y > CONFIG_ARCH_USE_MEMREMAP_PROT=y > # CONFIG_LOCK_EVENT_COUNTS is not set > CONFIG_ARCH_HAS_MEM_ENCRYPT=y > > # > # GCOV-based kernel profiling > # > # CONFIG_GCOV_KERNEL is not set > CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y > # end of GCOV-based kernel profiling > > CONFIG_HAVE_GCC_PLUGINS=y > CONFIG_GCC_PLUGINS=y > # CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set > # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set > # CONFIG_GCC_PLUGIN_RANDSTRUCT is not set > # end of General architecture-dependent options > > CONFIG_RT_MUTEXES=y > CONFIG_BASE_SMALL=0 > CONFIG_MODULE_SIG_FORMAT=y > CONFIG_MODULES=y > # CONFIG_MODULE_FORCE_LOAD is not set > CONFIG_MODULE_UNLOAD=y > # CONFIG_MODULE_FORCE_UNLOAD is not set > # CONFIG_MODVERSIONS is not set > # CONFIG_MODULE_SRCVERSION_ALL is not set > CONFIG_MODULE_SIG=y > # CONFIG_MODULE_SIG_FORCE is not set > CONFIG_MODULE_SIG_ALL=y > # CONFIG_MODULE_SIG_SHA1 is not set > # CONFIG_MODULE_SIG_SHA224 is not set > CONFIG_MODULE_SIG_SHA256=y > # CONFIG_MODULE_SIG_SHA384 is not set > # CONFIG_MODULE_SIG_SHA512 is not set > CONFIG_MODULE_SIG_HASH="sha256" > # CONFIG_MODULE_COMPRESS is not set > # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set > CONFIG_UNUSED_SYMBOLS=y > CONFIG_MODULES_TREE_LOOKUP=y > CONFIG_BLOCK=y > CONFIG_BLK_SCSI_REQUEST=y > CONFIG_BLK_DEV_BSG=y > # CONFIG_BLK_DEV_BSGLIB is not set > # CONFIG_BLK_DEV_INTEGRITY is not set > # CONFIG_BLK_DEV_ZONED is not set > # CONFIG_BLK_DEV_THROTTLING is not set > # CONFIG_BLK_CMDLINE_PARSER is not set > # CONFIG_BLK_WBT is not set > # CONFIG_BLK_CGROUP_IOLATENCY is not set > # CONFIG_BLK_CGROUP_IOCOST is not set > CONFIG_BLK_DEBUG_FS=y > # CONFIG_BLK_SED_OPAL is not set > > # > # Partition Types > # > # CONFIG_PARTITION_ADVANCED is not set > CONFIG_MSDOS_PARTITION=y > CONFIG_EFI_PARTITION=y > # end of Partition Types > > CONFIG_BLOCK_COMPAT=y > CONFIG_BLK_MQ_PCI=y > CONFIG_BLK_PM=y > > # > # IO Schedulers > # > CONFIG_MQ_IOSCHED_DEADLINE=y > CONFIG_MQ_IOSCHED_KYBER=y > # CONFIG_IOSCHED_BFQ is not set > # end of IO Schedulers > > CONFIG_ASN1=y > CONFIG_UNINLINE_SPIN_UNLOCK=y > CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y > CONFIG_MUTEX_SPIN_ON_OWNER=y > CONFIG_RWSEM_SPIN_ON_OWNER=y > CONFIG_LOCK_SPIN_ON_OWNER=y > CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y > CONFIG_QUEUED_SPINLOCKS=y > CONFIG_ARCH_USE_QUEUED_RWLOCKS=y > CONFIG_QUEUED_RWLOCKS=y > CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y > CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y > CONFIG_FREEZER=y > > # > # Executable file formats > # > CONFIG_BINFMT_ELF=y > CONFIG_COMPAT_BINFMT_ELF=y > CONFIG_ELFCORE=y > # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set > CONFIG_BINFMT_SCRIPT=y > CONFIG_BINFMT_MISC=y > CONFIG_COREDUMP=y > # end of Executable file formats > > # > # Memory Management options > # > CONFIG_SELECT_MEMORY_MODEL=y > CONFIG_SPARSEMEM_MANUAL=y > CONFIG_SPARSEMEM=y > CONFIG_NEED_MULTIPLE_NODES=y > CONFIG_HAVE_MEMORY_PRESENT=y > CONFIG_SPARSEMEM_EXTREME=y > CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y > CONFIG_SPARSEMEM_VMEMMAP=y > CONFIG_HAVE_MEMBLOCK_NODE_MAP=y > CONFIG_HAVE_FAST_GUP=y > # CONFIG_MEMORY_HOTPLUG is not set > CONFIG_SPLIT_PTLOCK_CPUS=4 > # CONFIG_COMPACTION is not set > # CONFIG_PAGE_REPORTING is not set > CONFIG_MIGRATION=y > CONFIG_PHYS_ADDR_T_64BIT=y > CONFIG_BOUNCE=y > CONFIG_VIRT_TO_BUS=y > CONFIG_MMU_NOTIFIER=y > # CONFIG_KSM is not set > CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 > CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y > # CONFIG_MEMORY_FAILURE is not set > # CONFIG_TRANSPARENT_HUGEPAGE is not set > CONFIG_ARCH_WANTS_THP_SWAP=y > # CONFIG_CLEANCACHE is not set > # CONFIG_FRONTSWAP is not set > # CONFIG_CMA is not set > CONFIG_ZPOOL=m > CONFIG_ZBUD=m > CONFIG_Z3FOLD=m > CONFIG_ZSMALLOC=m > # CONFIG_PGTABLE_MAPPING is not set > # CONFIG_ZSMALLOC_STAT is not set > CONFIG_GENERIC_EARLY_IOREMAP=y > # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set > # CONFIG_IDLE_PAGE_TRACKING is not set > CONFIG_ARCH_HAS_PTE_DEVMAP=y > CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y > CONFIG_ARCH_HAS_PKEYS=y > # CONFIG_PERCPU_STATS is not set > # CONFIG_GUP_BENCHMARK is not set > CONFIG_ARCH_HAS_PTE_SPECIAL=y > # end of Memory Management options > > CONFIG_NET=y > CONFIG_SKB_EXTENSIONS=y > > # > # Networking options > # > CONFIG_PACKET=y > # CONFIG_PACKET_DIAG is not set > CONFIG_UNIX=y > CONFIG_UNIX_SCM=y > # CONFIG_UNIX_DIAG is not set > # CONFIG_TLS is not set > CONFIG_XFRM=y > CONFIG_XFRM_ALGO=y > # CONFIG_XFRM_USER is not set > # CONFIG_XFRM_INTERFACE is not set > # CONFIG_XFRM_SUB_POLICY is not set > # CONFIG_XFRM_MIGRATE is not set > # CONFIG_XFRM_STATISTICS is not set > CONFIG_XFRM_IPCOMP=y > # CONFIG_NET_KEY is not set > # CONFIG_XDP_SOCKETS is not set > CONFIG_INET=y > CONFIG_IP_MULTICAST=y > CONFIG_IP_ADVANCED_ROUTER=y > CONFIG_IP_FIB_TRIE_STATS=y > CONFIG_IP_MULTIPLE_TABLES=y > CONFIG_IP_ROUTE_MULTIPATH=y > CONFIG_IP_ROUTE_VERBOSE=y > # CONFIG_IP_PNP is not set > # CONFIG_NET_IPIP is not set > # CONFIG_NET_IPGRE_DEMUX is not set > # CONFIG_IP_MROUTE is not set > # CONFIG_SYN_COOKIES is not set > # CONFIG_NET_IPVTI is not set > # CONFIG_NET_FOU is not set > # CONFIG_INET_AH is not set > # CONFIG_INET_ESP is not set > # CONFIG_INET_IPCOMP is not set > CONFIG_INET_DIAG=y > CONFIG_INET_TCP_DIAG=y > # CONFIG_INET_UDP_DIAG is not set > # CONFIG_INET_RAW_DIAG is not set > # CONFIG_INET_DIAG_DESTROY is not set > # CONFIG_TCP_CONG_ADVANCED is not set > CONFIG_TCP_CONG_CUBIC=y > CONFIG_DEFAULT_TCP_CONG="cubic" > # CONFIG_TCP_MD5SIG is not set > CONFIG_IPV6=y > CONFIG_IPV6_ROUTER_PREF=y > CONFIG_IPV6_ROUTE_INFO=y > CONFIG_IPV6_OPTIMISTIC_DAD=y > CONFIG_INET6_AH=y > CONFIG_INET6_ESP=y > # CONFIG_INET6_ESP_OFFLOAD is not set > CONFIG_INET6_IPCOMP=y > CONFIG_IPV6_MIP6=y > CONFIG_INET6_XFRM_TUNNEL=y > CONFIG_INET6_TUNNEL=y > # CONFIG_IPV6_VTI is not set > # CONFIG_IPV6_SIT is not set > # CONFIG_IPV6_TUNNEL is not set > CONFIG_IPV6_MULTIPLE_TABLES=y > CONFIG_IPV6_SUBTREES=y > # CONFIG_IPV6_MROUTE is not set > # CONFIG_IPV6_SEG6_LWTUNNEL is not set > # CONFIG_IPV6_SEG6_HMAC is not set > # CONFIG_IPV6_RPL_LWTUNNEL is not set > CONFIG_NETLABEL=y > # CONFIG_MPTCP is not set > CONFIG_NETWORK_SECMARK=y > CONFIG_NET_PTP_CLASSIFY=y > # CONFIG_NETWORK_PHY_TIMESTAMPING is not set > # CONFIG_NETFILTER is not set > # CONFIG_BPFILTER is not set > # CONFIG_IP_DCCP is not set > CONFIG_IP_SCTP=y > # CONFIG_SCTP_DBG_OBJCNT is not set > CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set > CONFIG_SCTP_COOKIE_HMAC_MD5=y > # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set > CONFIG_INET_SCTP_DIAG=y > CONFIG_RDS=y > CONFIG_RDS_TCP=m > # CONFIG_RDS_DEBUG is not set > # CONFIG_TIPC is not set > # CONFIG_ATM is not set > # CONFIG_L2TP is not set > CONFIG_STP=y > CONFIG_BRIDGE=y > CONFIG_BRIDGE_IGMP_SNOOPING=y > CONFIG_HAVE_NET_DSA=y > # CONFIG_NET_DSA is not set > # CONFIG_VLAN_8021Q is not set > # CONFIG_DECNET is not set > CONFIG_LLC=y > # CONFIG_LLC2 is not set > # CONFIG_ATALK is not set > # CONFIG_X25 is not set > # CONFIG_LAPB is not set > # CONFIG_PHONET is not set > # CONFIG_6LOWPAN is not set > # CONFIG_IEEE802154 is not set > # CONFIG_NET_SCHED is not set > # CONFIG_DCB is not set > CONFIG_DNS_RESOLVER=y > # CONFIG_BATMAN_ADV is not set > # CONFIG_OPENVSWITCH is not set > # CONFIG_VSOCKETS is not set > CONFIG_NETLINK_DIAG=y > # CONFIG_MPLS is not set > # CONFIG_NET_NSH is not set > # CONFIG_HSR is not set > # CONFIG_NET_SWITCHDEV is not set > # CONFIG_NET_L3_MASTER_DEV is not set > # CONFIG_NET_NCSI is not set > CONFIG_RPS=y > CONFIG_RFS_ACCEL=y > CONFIG_XPS=y > CONFIG_CGROUP_NET_PRIO=y > CONFIG_CGROUP_NET_CLASSID=y > CONFIG_NET_RX_BUSY_POLL=y > CONFIG_BQL=y > # CONFIG_BPF_JIT is not set > CONFIG_NET_FLOW_LIMIT=y > > # > # Network testing > # > # CONFIG_NET_PKTGEN is not set > # CONFIG_NET_DROP_MONITOR is not set > # end of Network testing > # end of Networking options > > # CONFIG_HAMRADIO is not set > # CONFIG_CAN is not set > # CONFIG_BT is not set > CONFIG_AF_RXRPC=y > CONFIG_AF_RXRPC_IPV6=y > # CONFIG_AF_RXRPC_INJECT_LOSS is not set > CONFIG_AF_RXRPC_DEBUG=y > CONFIG_RXKAD=y > # CONFIG_AF_KCM is not set > CONFIG_FIB_RULES=y > # CONFIG_WIRELESS is not set > # CONFIG_WIMAX is not set > # CONFIG_RFKILL is not set > # CONFIG_NET_9P is not set > # CONFIG_CAIF is not set > CONFIG_CEPH_LIB=m > # CONFIG_CEPH_LIB_PRETTYDEBUG is not set > CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y > # CONFIG_NFC is not set > # CONFIG_PSAMPLE is not set > # CONFIG_NET_IFE is not set > # CONFIG_LWTUNNEL is not set > CONFIG_GRO_CELLS=y > # CONFIG_FAILOVER is not set > CONFIG_ETHTOOL_NETLINK=y > CONFIG_HAVE_EBPF_JIT=y > > # > # Device Drivers > # > CONFIG_HAVE_EISA=y > # CONFIG_EISA is not set > CONFIG_HAVE_PCI=y > CONFIG_PCI=y > CONFIG_PCI_DOMAINS=y > CONFIG_PCIEPORTBUS=y > CONFIG_PCIEAER=y > # CONFIG_PCIEAER_INJECT is not set > # CONFIG_PCIE_ECRC is not set > CONFIG_PCIEASPM=y > CONFIG_PCIEASPM_DEFAULT=y > # CONFIG_PCIEASPM_POWERSAVE is not set > # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set > # CONFIG_PCIEASPM_PERFORMANCE is not set > CONFIG_PCIE_PME=y > # CONFIG_PCIE_DPC is not set > # CONFIG_PCIE_PTM is not set > # CONFIG_PCIE_BW is not set > CONFIG_PCI_MSI=y > CONFIG_PCI_MSI_IRQ_DOMAIN=y > CONFIG_PCI_QUIRKS=y > # CONFIG_PCI_DEBUG is not set > # CONFIG_PCI_STUB is not set > CONFIG_PCI_ATS=y > CONFIG_PCI_LOCKLESS_CONFIG=y > # CONFIG_PCI_IOV is not set > CONFIG_PCI_PRI=y > CONFIG_PCI_PASID=y > CONFIG_PCI_LABEL=y > # CONFIG_HOTPLUG_PCI is not set > > # > # PCI controller drivers > # > # CONFIG_VMD is not set > > # > # DesignWare PCI Core Support > # > # CONFIG_PCIE_DW_PLAT_HOST is not set > # CONFIG_PCI_MESON is not set > # end of DesignWare PCI Core Support > > # > # Mobiveil PCIe Core Support > # > # end of Mobiveil PCIe Core Support > > # > # Cadence PCIe controllers support > # > # end of Cadence PCIe controllers support > # end of PCI controller drivers > > # > # PCI Endpoint > # > # CONFIG_PCI_ENDPOINT is not set > # end of PCI Endpoint > > # > # PCI switch controller drivers > # > # CONFIG_PCI_SW_SWITCHTEC is not set > # end of PCI switch controller drivers > > # CONFIG_PCCARD is not set > # CONFIG_RAPIDIO is not set > > # > # Generic Driver Options > # > CONFIG_UEVENT_HELPER=y > CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" > CONFIG_DEVTMPFS=y > CONFIG_DEVTMPFS_MOUNT=y > CONFIG_STANDALONE=y > CONFIG_PREVENT_FIRMWARE_BUILD=y > > # > # Firmware loader > # > CONFIG_FW_LOADER=y > CONFIG_FW_LOADER_PAGED_BUF=y > CONFIG_EXTRA_FIRMWARE="" > # CONFIG_FW_LOADER_USER_HELPER is not set > CONFIG_FW_LOADER_COMPRESS=y > # end of Firmware loader > > CONFIG_ALLOW_DEV_COREDUMP=y > # CONFIG_DEBUG_DRIVER is not set > # CONFIG_DEBUG_DEVRES is not set > # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set > # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set > CONFIG_GENERIC_CPU_AUTOPROBE=y > CONFIG_GENERIC_CPU_VULNERABILITIES=y > CONFIG_DMA_SHARED_BUFFER=y > # CONFIG_DMA_FENCE_TRACE is not set > # end of Generic Driver Options > > # > # Bus devices > # > # CONFIG_MHI_BUS is not set > # end of Bus devices > > # CONFIG_CONNECTOR is not set > # CONFIG_GNSS is not set > # CONFIG_MTD is not set > # CONFIG_OF is not set > CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y > # CONFIG_PARPORT is not set > CONFIG_PNP=y > # CONFIG_PNP_DEBUG_MESSAGES is not set > > # > # Protocols > # > CONFIG_PNPACPI=y > CONFIG_BLK_DEV=y > # CONFIG_BLK_DEV_NULL_BLK is not set > # CONFIG_BLK_DEV_FD is not set > # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set > # CONFIG_ZRAM is not set > # CONFIG_BLK_DEV_UMEM is not set > CONFIG_BLK_DEV_LOOP=y > CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 > # CONFIG_BLK_DEV_CRYPTOLOOP is not set > # CONFIG_BLK_DEV_DRBD is not set > # CONFIG_BLK_DEV_NBD is not set > # CONFIG_BLK_DEV_SKD is not set > # CONFIG_BLK_DEV_SX8 is not set > # CONFIG_BLK_DEV_RAM is not set > # CONFIG_CDROM_PKTCDVD is not set > # CONFIG_ATA_OVER_ETH is not set > CONFIG_BLK_DEV_RBD=m > # CONFIG_BLK_DEV_RSXX is not set > > # > # NVME Support > # > # CONFIG_BLK_DEV_NVME is not set > # CONFIG_NVME_FC is not set > # CONFIG_NVME_TARGET is not set > # end of NVME Support > > # > # Misc devices > # > # CONFIG_AD525X_DPOT is not set > # CONFIG_DUMMY_IRQ is not set > # CONFIG_IBM_ASM is not set > # CONFIG_PHANTOM is not set > # CONFIG_TIFM_CORE is not set > # CONFIG_ICS932S401 is not set > CONFIG_ENCLOSURE_SERVICES=y > # CONFIG_HP_ILO is not set > # CONFIG_APDS9802ALS is not set > # CONFIG_ISL29003 is not set > # CONFIG_ISL29020 is not set > # CONFIG_SENSORS_TSL2550 is not set > # CONFIG_SENSORS_BH1770 is not set > # CONFIG_SENSORS_APDS990X is not set > # CONFIG_HMC6352 is not set > # CONFIG_DS1682 is not set > # CONFIG_SRAM is not set > # CONFIG_PCI_ENDPOINT_TEST is not set > # CONFIG_XILINX_SDFEC is not set > # CONFIG_PVPANIC is not set > CONFIG_C2PORT=m > # CONFIG_C2PORT_DURAMAR_2150 is not set > > # > # EEPROM support > # > # CONFIG_EEPROM_AT24 is not set > # CONFIG_EEPROM_LEGACY is not set > # CONFIG_EEPROM_MAX6875 is not set > # CONFIG_EEPROM_93CX6 is not set > # CONFIG_EEPROM_IDT_89HPESX is not set > # CONFIG_EEPROM_EE1004 is not set > # end of EEPROM support > > # CONFIG_CB710_CORE is not set > > # > # Texas Instruments shared transport line discipline > # > # end of Texas Instruments shared transport line discipline > > # CONFIG_SENSORS_LIS3_I2C is not set > # CONFIG_ALTERA_STAPL is not set > CONFIG_INTEL_MEI=y > CONFIG_INTEL_MEI_ME=y > # CONFIG_INTEL_MEI_TXE is not set > # CONFIG_INTEL_MEI_HDCP is not set > # CONFIG_VMWARE_VMCI is not set > > # > # Intel MIC & related support > # > # CONFIG_INTEL_MIC_BUS is not set > # CONFIG_SCIF_BUS is not set > # CONFIG_VOP_BUS is not set > # end of Intel MIC & related support > > # CONFIG_GENWQE is not set > # CONFIG_ECHO is not set > # CONFIG_MISC_ALCOR_PCI is not set > # CONFIG_MISC_RTSX_PCI is not set > # CONFIG_MISC_RTSX_USB is not set > # CONFIG_HABANA_AI is not set > # CONFIG_UACCE is not set > # end of Misc devices > > CONFIG_HAVE_IDE=y > # CONFIG_IDE is not set > > # > # SCSI device support > # > CONFIG_SCSI_MOD=y > # CONFIG_RAID_ATTRS is not set > CONFIG_SCSI=y > CONFIG_SCSI_DMA=y > CONFIG_SCSI_PROC_FS=y > > # > # SCSI support type (disk, tape, CD-ROM) > # > CONFIG_BLK_DEV_SD=y > # CONFIG_CHR_DEV_ST is not set > # CONFIG_BLK_DEV_SR is not set > CONFIG_CHR_DEV_SG=y > # CONFIG_CHR_DEV_SCH is not set > # CONFIG_SCSI_ENCLOSURE is not set > CONFIG_SCSI_CONSTANTS=y > # CONFIG_SCSI_LOGGING is not set > # CONFIG_SCSI_SCAN_ASYNC is not set > > # > # SCSI Transports > # > CONFIG_SCSI_SPI_ATTRS=y > # CONFIG_SCSI_FC_ATTRS is not set > # CONFIG_SCSI_ISCSI_ATTRS is not set > # CONFIG_SCSI_SAS_ATTRS is not set > # CONFIG_SCSI_SAS_LIBSAS is not set > # CONFIG_SCSI_SRP_ATTRS is not set > # end of SCSI Transports > > # CONFIG_SCSI_LOWLEVEL is not set > # CONFIG_SCSI_DH is not set > # end of SCSI device support > > CONFIG_ATA=y > CONFIG_SATA_HOST=y > CONFIG_PATA_TIMINGS=y > CONFIG_ATA_VERBOSE_ERROR=y > CONFIG_ATA_FORCE=y > CONFIG_ATA_ACPI=y > # CONFIG_SATA_ZPODD is not set > # CONFIG_SATA_PMP is not set > > # > # Controllers with non-SFF native interface > # > CONFIG_SATA_AHCI=y > CONFIG_SATA_MOBILE_LPM_POLICY=0 > CONFIG_SATA_AHCI_PLATFORM=y > # CONFIG_SATA_INIC162X is not set > # CONFIG_SATA_ACARD_AHCI is not set > # CONFIG_SATA_SIL24 is not set > # CONFIG_ATA_SFF is not set > CONFIG_MD=y > # CONFIG_BLK_DEV_MD is not set > # CONFIG_BCACHE is not set > CONFIG_BLK_DEV_DM_BUILTIN=y > CONFIG_BLK_DEV_DM=y > # CONFIG_DM_DEBUG is not set > # CONFIG_DM_UNSTRIPED is not set > # CONFIG_DM_CRYPT is not set > # CONFIG_DM_SNAPSHOT is not set > # CONFIG_DM_THIN_PROVISIONING is not set > # CONFIG_DM_CACHE is not set > # CONFIG_DM_WRITECACHE is not set > # CONFIG_DM_ERA is not set > # CONFIG_DM_CLONE is not set > # CONFIG_DM_MIRROR is not set > # CONFIG_DM_RAID is not set > # CONFIG_DM_ZERO is not set > # CONFIG_DM_MULTIPATH is not set > # CONFIG_DM_DELAY is not set > # CONFIG_DM_DUST is not set > # CONFIG_DM_INIT is not set > CONFIG_DM_UEVENT=y > # CONFIG_DM_FLAKEY is not set > # CONFIG_DM_VERITY is not set > # CONFIG_DM_SWITCH is not set > # CONFIG_DM_LOG_WRITES is not set > # CONFIG_DM_INTEGRITY is not set > # CONFIG_TARGET_CORE is not set > # CONFIG_FUSION is not set > > # > # IEEE 1394 (FireWire) support > # > # CONFIG_FIREWIRE is not set > # CONFIG_FIREWIRE_NOSY is not set > # end of IEEE 1394 (FireWire) support > > # CONFIG_MACINTOSH_DRIVERS is not set > CONFIG_NETDEVICES=y > CONFIG_NET_CORE=y > # CONFIG_BONDING is not set > # CONFIG_DUMMY is not set > # CONFIG_WIREGUARD is not set > # CONFIG_EQUALIZER is not set > # CONFIG_NET_FC is not set > # CONFIG_NET_TEAM is not set > # CONFIG_MACVLAN is not set > # CONFIG_IPVLAN is not set > # CONFIG_VXLAN is not set > # CONFIG_GENEVE is not set > # CONFIG_BAREUDP is not set > # CONFIG_GTP is not set > # CONFIG_MACSEC is not set > # CONFIG_NETCONSOLE is not set > CONFIG_TUN=y > # CONFIG_TUN_VNET_CROSS_LE is not set > CONFIG_VETH=y > # CONFIG_NLMON is not set > # CONFIG_ARCNET is not set > > # > # Distributed Switch Architecture drivers > # > # end of Distributed Switch Architecture drivers > > CONFIG_ETHERNET=y > CONFIG_MDIO=y > # CONFIG_NET_VENDOR_3COM is not set > # CONFIG_NET_VENDOR_ADAPTEC is not set > # CONFIG_NET_VENDOR_AGERE is not set > # CONFIG_NET_VENDOR_ALACRITECH is not set > # CONFIG_NET_VENDOR_ALTEON is not set > # CONFIG_ALTERA_TSE is not set > # CONFIG_NET_VENDOR_AMAZON is not set > # CONFIG_NET_VENDOR_AMD is not set > # CONFIG_NET_VENDOR_AQUANTIA is not set > # CONFIG_NET_VENDOR_ARC is not set > # CONFIG_NET_VENDOR_ATHEROS is not set > # CONFIG_NET_VENDOR_AURORA is not set > # CONFIG_NET_VENDOR_BROADCOM is not set > # CONFIG_NET_VENDOR_BROCADE is not set > # CONFIG_NET_VENDOR_CADENCE is not set > # CONFIG_NET_VENDOR_CAVIUM is not set > # CONFIG_NET_VENDOR_CHELSIO is not set > # CONFIG_NET_VENDOR_CISCO is not set > # CONFIG_NET_VENDOR_CORTINA is not set > # CONFIG_CX_ECAT is not set > # CONFIG_DNET is not set > # CONFIG_NET_VENDOR_DEC is not set > # CONFIG_NET_VENDOR_DLINK is not set > # CONFIG_NET_VENDOR_EMULEX is not set > # CONFIG_NET_VENDOR_EZCHIP is not set > # CONFIG_NET_VENDOR_GOOGLE is not set > # CONFIG_NET_VENDOR_HUAWEI is not set > CONFIG_NET_VENDOR_I825XX=y > CONFIG_NET_VENDOR_INTEL=y > # CONFIG_E100 is not set > # CONFIG_E1000 is not set > # CONFIG_E1000E is not set > # CONFIG_IGB is not set > # CONFIG_IGBVF is not set > # CONFIG_IXGB is not set > CONFIG_IXGBE=y > CONFIG_IXGBE_HWMON=y > # CONFIG_IXGBEVF is not set > # CONFIG_I40E is not set > # CONFIG_I40EVF is not set > # CONFIG_ICE is not set > # CONFIG_FM10K is not set > # CONFIG_IGC is not set > # CONFIG_JME is not set > # CONFIG_NET_VENDOR_MARVELL is not set > # CONFIG_NET_VENDOR_MELLANOX is not set > # CONFIG_NET_VENDOR_MICREL is not set > # CONFIG_NET_VENDOR_MICROCHIP is not set > # CONFIG_NET_VENDOR_MICROSEMI is not set > # CONFIG_NET_VENDOR_MYRI is not set > # CONFIG_FEALNX is not set > # CONFIG_NET_VENDOR_NATSEMI is not set > # CONFIG_NET_VENDOR_NETERION is not set > # CONFIG_NET_VENDOR_NETRONOME is not set > # CONFIG_NET_VENDOR_NI is not set > # CONFIG_NET_VENDOR_NVIDIA is not set > # CONFIG_NET_VENDOR_OKI is not set > # CONFIG_ETHOC is not set > # CONFIG_NET_VENDOR_PACKET_ENGINES is not set > # CONFIG_NET_VENDOR_PENSANDO is not set > # CONFIG_NET_VENDOR_QLOGIC is not set > # CONFIG_NET_VENDOR_QUALCOMM is not set > # CONFIG_NET_VENDOR_RDC is not set > CONFIG_NET_VENDOR_REALTEK=y > # CONFIG_8139CP is not set > # CONFIG_8139TOO is not set > CONFIG_R8169=y > # CONFIG_NET_VENDOR_RENESAS is not set > # CONFIG_NET_VENDOR_ROCKER is not set > # CONFIG_NET_VENDOR_SAMSUNG is not set > # CONFIG_NET_VENDOR_SEEQ is not set > # CONFIG_NET_VENDOR_SOLARFLARE is not set > # CONFIG_NET_VENDOR_SILAN is not set > # CONFIG_NET_VENDOR_SIS is not set > # CONFIG_NET_VENDOR_SMSC is not set > # CONFIG_NET_VENDOR_SOCIONEXT is not set > # CONFIG_NET_VENDOR_STMICRO is not set > # CONFIG_NET_VENDOR_SUN is not set > # CONFIG_NET_VENDOR_SYNOPSYS is not set > # CONFIG_NET_VENDOR_TEHUTI is not set > # CONFIG_NET_VENDOR_TI is not set > # CONFIG_NET_VENDOR_VIA is not set > # CONFIG_NET_VENDOR_WIZNET is not set > # CONFIG_NET_VENDOR_XILINX is not set > # CONFIG_FDDI is not set > # CONFIG_HIPPI is not set > # CONFIG_NET_SB1000 is not set > CONFIG_MDIO_DEVICE=y > CONFIG_MDIO_BUS=y > # CONFIG_MDIO_BCM_UNIMAC is not set > # CONFIG_MDIO_BITBANG is not set > # CONFIG_MDIO_MSCC_MIIM is not set > # CONFIG_MDIO_MVUSB is not set > # CONFIG_MDIO_THUNDER is not set > # CONFIG_MDIO_XPCS is not set > CONFIG_PHYLIB=y > > # > # MII PHY device drivers > # > # CONFIG_ADIN_PHY is not set > # CONFIG_AMD_PHY is not set > # CONFIG_AQUANTIA_PHY is not set > # CONFIG_AX88796B_PHY is not set > # CONFIG_BCM7XXX_PHY is not set > # CONFIG_BCM87XX_PHY is not set > # CONFIG_BROADCOM_PHY is not set > # CONFIG_BCM84881_PHY is not set > # CONFIG_CICADA_PHY is not set > # CONFIG_CORTINA_PHY is not set > # CONFIG_DAVICOM_PHY is not set > # CONFIG_DP83822_PHY is not set > # CONFIG_DP83TC811_PHY is not set > # CONFIG_DP83848_PHY is not set > # CONFIG_DP83867_PHY is not set > # CONFIG_DP83869_PHY is not set > # CONFIG_FIXED_PHY is not set > # CONFIG_ICPLUS_PHY is not set > # CONFIG_INTEL_XWAY_PHY is not set > # CONFIG_LSI_ET1011C_PHY is not set > # CONFIG_LXT_PHY is not set > # CONFIG_MARVELL_PHY is not set > # CONFIG_MARVELL_10G_PHY is not set > # CONFIG_MICREL_PHY is not set > # CONFIG_MICROCHIP_PHY is not set > # CONFIG_MICROCHIP_T1_PHY is not set > # CONFIG_MICROSEMI_PHY is not set > # CONFIG_NATIONAL_PHY is not set > # CONFIG_NXP_TJA11XX_PHY is not set > # CONFIG_QSEMI_PHY is not set > CONFIG_REALTEK_PHY=y > # CONFIG_RENESAS_PHY is not set > # CONFIG_ROCKCHIP_PHY is not set > # CONFIG_SMSC_PHY is not set > # CONFIG_STE10XP is not set > # CONFIG_TERANETICS_PHY is not set > # CONFIG_VITESSE_PHY is not set > # CONFIG_XILINX_GMII2RGMII is not set > # CONFIG_PPP is not set > # CONFIG_SLIP is not set > # CONFIG_USB_NET_DRIVERS is not set > # CONFIG_WLAN is not set > > # > # Enable WiMAX (Networking options) to see the WiMAX drivers > # > # CONFIG_WAN is not set > # CONFIG_VMXNET3 is not set > # CONFIG_FUJITSU_ES is not set > # CONFIG_NETDEVSIM is not set > # CONFIG_NET_FAILOVER is not set > # CONFIG_ISDN is not set > # CONFIG_NVM is not set > > # > # Input device support > # > CONFIG_INPUT=y > # CONFIG_INPUT_FF_MEMLESS is not set > # CONFIG_INPUT_POLLDEV is not set > # CONFIG_INPUT_SPARSEKMAP is not set > # CONFIG_INPUT_MATRIXKMAP is not set > > # > # Userland interfaces > # > CONFIG_INPUT_MOUSEDEV=y > CONFIG_INPUT_MOUSEDEV_PSAUX=y > CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 > CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 > # CONFIG_INPUT_JOYDEV is not set > CONFIG_INPUT_EVDEV=y > # CONFIG_INPUT_EVBUG is not set > > # > # Input Device Drivers > # > CONFIG_INPUT_KEYBOARD=y > # CONFIG_KEYBOARD_ADP5588 is not set > # CONFIG_KEYBOARD_ADP5589 is not set > CONFIG_KEYBOARD_ATKBD=y > # CONFIG_KEYBOARD_QT1050 is not set > # CONFIG_KEYBOARD_QT1070 is not set > # CONFIG_KEYBOARD_QT2160 is not set > # CONFIG_KEYBOARD_DLINK_DIR685 is not set > # CONFIG_KEYBOARD_LKKBD is not set > # CONFIG_KEYBOARD_TCA6416 is not set > # CONFIG_KEYBOARD_TCA8418 is not set > # CONFIG_KEYBOARD_LM8333 is not set > # CONFIG_KEYBOARD_MAX7359 is not set > # CONFIG_KEYBOARD_MCS is not set > # CONFIG_KEYBOARD_MPR121 is not set > # CONFIG_KEYBOARD_NEWTON is not set > # CONFIG_KEYBOARD_OPENCORES is not set > # CONFIG_KEYBOARD_SAMSUNG is not set > # CONFIG_KEYBOARD_STOWAWAY is not set > # CONFIG_KEYBOARD_SUNKBD is not set > # CONFIG_KEYBOARD_XTKBD is not set > CONFIG_INPUT_MOUSE=y > CONFIG_MOUSE_PS2=y > # CONFIG_MOUSE_PS2_ALPS is not set > # CONFIG_MOUSE_PS2_BYD is not set > # CONFIG_MOUSE_PS2_LOGIPS2PP is not set > # CONFIG_MOUSE_PS2_SYNAPTICS is not set > CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y > # CONFIG_MOUSE_PS2_CYPRESS is not set > # CONFIG_MOUSE_PS2_LIFEBOOK is not set > # CONFIG_MOUSE_PS2_TRACKPOINT is not set > # CONFIG_MOUSE_PS2_ELANTECH is not set > # CONFIG_MOUSE_PS2_SENTELIC is not set > # CONFIG_MOUSE_PS2_TOUCHKIT is not set > # CONFIG_MOUSE_PS2_FOCALTECH is not set > CONFIG_MOUSE_PS2_SMBUS=y > # CONFIG_MOUSE_SERIAL is not set > # CONFIG_MOUSE_APPLETOUCH is not set > # CONFIG_MOUSE_BCM5974 is not set > # CONFIG_MOUSE_CYAPA is not set > # CONFIG_MOUSE_ELAN_I2C is not set > # CONFIG_MOUSE_VSXXXAA is not set > # CONFIG_MOUSE_SYNAPTICS_I2C is not set > # CONFIG_MOUSE_SYNAPTICS_USB is not set > # CONFIG_INPUT_JOYSTICK is not set > # CONFIG_INPUT_TABLET is not set > # CONFIG_INPUT_TOUCHSCREEN is not set > # CONFIG_INPUT_MISC is not set > # CONFIG_RMI4_CORE is not set > > # > # Hardware I/O ports > # > CONFIG_SERIO=y > CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y > CONFIG_SERIO_I8042=y > # CONFIG_SERIO_SERPORT is not set > # CONFIG_SERIO_CT82C710 is not set > # CONFIG_SERIO_PCIPS2 is not set > CONFIG_SERIO_LIBPS2=y > # CONFIG_SERIO_RAW is not set > # CONFIG_SERIO_ALTERA_PS2 is not set > # CONFIG_SERIO_PS2MULT is not set > # CONFIG_SERIO_ARC_PS2 is not set > # CONFIG_USERIO is not set > # CONFIG_GAMEPORT is not set > # end of Hardware I/O ports > # end of Input device support > > # > # Character devices > # > CONFIG_TTY=y > CONFIG_VT=y > CONFIG_CONSOLE_TRANSLATIONS=y > CONFIG_VT_CONSOLE=y > CONFIG_HW_CONSOLE=y > # CONFIG_VT_HW_CONSOLE_BINDING is not set > CONFIG_UNIX98_PTYS=y > CONFIG_LEGACY_PTYS=y > CONFIG_LEGACY_PTY_COUNT=256 > CONFIG_LDISC_AUTOLOAD=y > > # > # Serial drivers > # > CONFIG_SERIAL_EARLYCON=y > CONFIG_SERIAL_8250=y > CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y > CONFIG_SERIAL_8250_PNP=y > # CONFIG_SERIAL_8250_16550A_VARIANTS is not set > # CONFIG_SERIAL_8250_FINTEK is not set > CONFIG_SERIAL_8250_CONSOLE=y > CONFIG_SERIAL_8250_PCI=y > # CONFIG_SERIAL_8250_EXAR is not set > CONFIG_SERIAL_8250_NR_UARTS=4 > CONFIG_SERIAL_8250_RUNTIME_UARTS=4 > CONFIG_SERIAL_8250_EXTENDED=y > # CONFIG_SERIAL_8250_MANY_PORTS is not set > CONFIG_SERIAL_8250_SHARE_IRQ=y > # CONFIG_SERIAL_8250_DETECT_IRQ is not set > # CONFIG_SERIAL_8250_RSA is not set > CONFIG_SERIAL_8250_DWLIB=y > # CONFIG_SERIAL_8250_DW is not set > # CONFIG_SERIAL_8250_RT288X is not set > CONFIG_SERIAL_8250_LPSS=y > CONFIG_SERIAL_8250_MID=y > > # > # Non-8250 serial port support > # > # CONFIG_SERIAL_UARTLITE is not set > CONFIG_SERIAL_CORE=y > CONFIG_SERIAL_CORE_CONSOLE=y > # CONFIG_SERIAL_JSM is not set > # CONFIG_SERIAL_SCCNXP is not set > # CONFIG_SERIAL_SC16IS7XX is not set > # CONFIG_SERIAL_ALTERA_JTAGUART is not set > # CONFIG_SERIAL_ALTERA_UART is not set > # CONFIG_SERIAL_ARC is not set > # CONFIG_SERIAL_RP2 is not set > # CONFIG_SERIAL_FSL_LPUART is not set > # CONFIG_SERIAL_FSL_LINFLEXUART is not set > # CONFIG_SERIAL_SPRD is not set > # end of Serial drivers > > # CONFIG_SERIAL_NONSTANDARD is not set > # CONFIG_N_GSM is not set > # CONFIG_NOZOMI is not set > # CONFIG_NULL_TTY is not set > # CONFIG_TRACE_SINK is not set > # CONFIG_SERIAL_DEV_BUS is not set > # CONFIG_TTY_PRINTK is not set > CONFIG_IPMI_HANDLER=y > CONFIG_IPMI_DMI_DECODE=y > CONFIG_IPMI_PLAT_DATA=y > # CONFIG_IPMI_PANIC_EVENT is not set > CONFIG_IPMI_DEVICE_INTERFACE=y > CONFIG_IPMI_SI=y > CONFIG_IPMI_SSIF=y > # CONFIG_IPMI_WATCHDOG is not set > # CONFIG_IPMI_POWEROFF is not set > # CONFIG_HW_RANDOM is not set > # CONFIG_APPLICOM is not set > # CONFIG_MWAVE is not set > # CONFIG_DEVMEM is not set > CONFIG_DEVKMEM=y > # CONFIG_NVRAM is not set > # CONFIG_RAW_DRIVER is not set > CONFIG_DEVPORT=y > CONFIG_HPET=y > CONFIG_HPET_MMAP=y > CONFIG_HPET_MMAP_DEFAULT=y > # CONFIG_HANGCHECK_TIMER is not set > CONFIG_TCG_TPM=y > # CONFIG_TCG_TIS is not set > # CONFIG_TCG_TIS_I2C_ATMEL is not set > # CONFIG_TCG_TIS_I2C_INFINEON is not set > # CONFIG_TCG_TIS_I2C_NUVOTON is not set > # CONFIG_TCG_NSC is not set > # CONFIG_TCG_ATMEL is not set > # CONFIG_TCG_INFINEON is not set > # CONFIG_TCG_CRB is not set > CONFIG_TCG_VTPM_PROXY=y > # CONFIG_TCG_TIS_ST33ZP24_I2C is not set > # CONFIG_TELCLOCK is not set > # CONFIG_XILLYBUS is not set > # end of Character devices > > # CONFIG_RANDOM_TRUST_CPU is not set > # CONFIG_RANDOM_TRUST_BOOTLOADER is not set > > # > # I2C support > # > CONFIG_I2C=y > CONFIG_ACPI_I2C_OPREGION=y > CONFIG_I2C_BOARDINFO=y > CONFIG_I2C_COMPAT=y > CONFIG_I2C_CHARDEV=y > CONFIG_I2C_MUX=y > > # > # Multiplexer I2C Chip support > # > # CONFIG_I2C_MUX_LTC4306 is not set > # CONFIG_I2C_MUX_PCA9541 is not set > # CONFIG_I2C_MUX_REG is not set > # CONFIG_I2C_MUX_MLXCPLD is not set > # end of Multiplexer I2C Chip support > > CONFIG_I2C_HELPER_AUTO=y > CONFIG_I2C_SMBUS=y > CONFIG_I2C_ALGOBIT=y > > # > # I2C Hardware Bus support > # > > # > # PC SMBus host controller drivers > # > # CONFIG_I2C_ALI1535 is not set > # CONFIG_I2C_ALI1563 is not set > # CONFIG_I2C_ALI15X3 is not set > # CONFIG_I2C_AMD756 is not set > # CONFIG_I2C_AMD8111 is not set > # CONFIG_I2C_AMD_MP2 is not set > CONFIG_I2C_I801=y > # CONFIG_I2C_ISCH is not set > # CONFIG_I2C_ISMT is not set > # CONFIG_I2C_PIIX4 is not set > # CONFIG_I2C_NFORCE2 is not set > # CONFIG_I2C_NVIDIA_GPU is not set > # CONFIG_I2C_SIS5595 is not set > # CONFIG_I2C_SIS630 is not set > # CONFIG_I2C_SIS96X is not set > # CONFIG_I2C_VIA is not set > # CONFIG_I2C_VIAPRO is not set > > # > # ACPI drivers > # > CONFIG_I2C_SCMI=y > > # > # I2C system bus drivers (mostly embedded / system-on-chip) > # > # CONFIG_I2C_DESIGNWARE_PLATFORM is not set > # CONFIG_I2C_DESIGNWARE_PCI is not set > # CONFIG_I2C_EMEV2 is not set > # CONFIG_I2C_OCORES is not set > # CONFIG_I2C_PCA_PLATFORM is not set > # CONFIG_I2C_SIMTEC is not set > # CONFIG_I2C_XILINX is not set > > # > # External I2C/SMBus adapter drivers > # > # CONFIG_I2C_DIOLAN_U2C is not set > # CONFIG_I2C_ROBOTFUZZ_OSIF is not set > # CONFIG_I2C_TAOS_EVM is not set > # CONFIG_I2C_TINY_USB is not set > > # > # Other I2C/SMBus bus drivers > # > # CONFIG_I2C_MLXCPLD is not set > # end of I2C Hardware Bus support > > # CONFIG_I2C_STUB is not set > # CONFIG_I2C_SLAVE is not set > # CONFIG_I2C_DEBUG_CORE is not set > # CONFIG_I2C_DEBUG_ALGO is not set > # CONFIG_I2C_DEBUG_BUS is not set > # end of I2C support > > # CONFIG_I3C is not set > # CONFIG_SPI is not set > # CONFIG_SPMI is not set > # CONFIG_HSI is not set > CONFIG_PPS=y > # CONFIG_PPS_DEBUG is not set > > # > # PPS clients support > # > # CONFIG_PPS_CLIENT_KTIMER is not set > # CONFIG_PPS_CLIENT_LDISC is not set > # CONFIG_PPS_CLIENT_GPIO is not set > > # > # PPS generators support > # > > # > # PTP clock support > # > CONFIG_PTP_1588_CLOCK=y > > # > # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. > # > # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set > # CONFIG_PTP_1588_CLOCK_IDTCM is not set > # end of PTP clock support > > # CONFIG_PINCTRL is not set > # CONFIG_GPIOLIB is not set > # CONFIG_W1 is not set > # CONFIG_POWER_AVS is not set > # CONFIG_POWER_RESET is not set > CONFIG_POWER_SUPPLY=y > # CONFIG_POWER_SUPPLY_DEBUG is not set > CONFIG_POWER_SUPPLY_HWMON=y > # CONFIG_PDA_POWER is not set > # CONFIG_TEST_POWER is not set > # CONFIG_CHARGER_ADP5061 is not set > # CONFIG_BATTERY_DS2780 is not set > # CONFIG_BATTERY_DS2781 is not set > # CONFIG_BATTERY_DS2782 is not set > # CONFIG_BATTERY_SBS is not set > # CONFIG_CHARGER_SBS is not set > # CONFIG_BATTERY_BQ27XXX is not set > # CONFIG_BATTERY_MAX17040 is not set > # CONFIG_BATTERY_MAX17042 is not set > # CONFIG_CHARGER_MAX8903 is not set > # CONFIG_CHARGER_LP8727 is not set > # CONFIG_CHARGER_BQ2415X is not set > # CONFIG_CHARGER_SMB347 is not set > # CONFIG_BATTERY_GAUGE_LTC2941 is not set > CONFIG_HWMON=y > # CONFIG_HWMON_DEBUG_CHIP is not set > > # > # Native drivers > # > # CONFIG_SENSORS_ABITUGURU is not set > # CONFIG_SENSORS_ABITUGURU3 is not set > # CONFIG_SENSORS_AD7414 is not set > # CONFIG_SENSORS_AD7418 is not set > # CONFIG_SENSORS_ADM1021 is not set > # CONFIG_SENSORS_ADM1025 is not set > # CONFIG_SENSORS_ADM1026 is not set > # CONFIG_SENSORS_ADM1029 is not set > # CONFIG_SENSORS_ADM1031 is not set > # CONFIG_SENSORS_ADM1177 is not set > # CONFIG_SENSORS_ADM9240 is not set > # CONFIG_SENSORS_ADT7410 is not set > # CONFIG_SENSORS_ADT7411 is not set > # CONFIG_SENSORS_ADT7462 is not set > # CONFIG_SENSORS_ADT7470 is not set > # CONFIG_SENSORS_ADT7475 is not set > # CONFIG_SENSORS_AS370 is not set > # CONFIG_SENSORS_ASC7621 is not set > # CONFIG_SENSORS_AXI_FAN_CONTROL is not set > # CONFIG_SENSORS_K8TEMP is not set > # CONFIG_SENSORS_K10TEMP is not set > # CONFIG_SENSORS_FAM15H_POWER is not set > # CONFIG_SENSORS_APPLESMC is not set > # CONFIG_SENSORS_ASB100 is not set > # CONFIG_SENSORS_ASPEED is not set > # CONFIG_SENSORS_ATXP1 is not set > # CONFIG_SENSORS_DRIVETEMP is not set > # CONFIG_SENSORS_DS620 is not set > # CONFIG_SENSORS_DS1621 is not set > # CONFIG_SENSORS_DELL_SMM is not set > # CONFIG_SENSORS_I5K_AMB is not set > # CONFIG_SENSORS_F71805F is not set > # CONFIG_SENSORS_F71882FG is not set > # CONFIG_SENSORS_F75375S is not set > # CONFIG_SENSORS_FSCHMD is not set > # CONFIG_SENSORS_FTSTEUTATES is not set > # CONFIG_SENSORS_GL518SM is not set > # CONFIG_SENSORS_GL520SM is not set > # CONFIG_SENSORS_G760A is not set > # CONFIG_SENSORS_G762 is not set > # CONFIG_SENSORS_HIH6130 is not set > # CONFIG_SENSORS_IBMAEM is not set > # CONFIG_SENSORS_IBMPEX is not set > # CONFIG_SENSORS_I5500 is not set > CONFIG_SENSORS_CORETEMP=y > # CONFIG_SENSORS_IT87 is not set > # CONFIG_SENSORS_JC42 is not set > # CONFIG_SENSORS_POWR1220 is not set > # CONFIG_SENSORS_LINEAGE is not set > # CONFIG_SENSORS_LTC2945 is not set > # CONFIG_SENSORS_LTC2947_I2C is not set > # CONFIG_SENSORS_LTC2990 is not set > # CONFIG_SENSORS_LTC4151 is not set > # CONFIG_SENSORS_LTC4215 is not set > # CONFIG_SENSORS_LTC4222 is not set > # CONFIG_SENSORS_LTC4245 is not set > # CONFIG_SENSORS_LTC4260 is not set > # CONFIG_SENSORS_LTC4261 is not set > # CONFIG_SENSORS_MAX16065 is not set > # CONFIG_SENSORS_MAX1619 is not set > # CONFIG_SENSORS_MAX1668 is not set > # CONFIG_SENSORS_MAX197 is not set > # CONFIG_SENSORS_MAX31730 is not set > # CONFIG_SENSORS_MAX6621 is not set > # CONFIG_SENSORS_MAX6639 is not set > # CONFIG_SENSORS_MAX6642 is not set > # CONFIG_SENSORS_MAX6650 is not set > # CONFIG_SENSORS_MAX6697 is not set > # CONFIG_SENSORS_MAX31790 is not set > # CONFIG_SENSORS_MCP3021 is not set > # CONFIG_SENSORS_TC654 is not set > # CONFIG_SENSORS_LM63 is not set > # CONFIG_SENSORS_LM73 is not set > # CONFIG_SENSORS_LM75 is not set > # CONFIG_SENSORS_LM77 is not set > # CONFIG_SENSORS_LM78 is not set > # CONFIG_SENSORS_LM80 is not set > # CONFIG_SENSORS_LM83 is not set > # CONFIG_SENSORS_LM85 is not set > # CONFIG_SENSORS_LM87 is not set > # CONFIG_SENSORS_LM90 is not set > # CONFIG_SENSORS_LM92 is not set > # CONFIG_SENSORS_LM93 is not set > # CONFIG_SENSORS_LM95234 is not set > # CONFIG_SENSORS_LM95241 is not set > # CONFIG_SENSORS_LM95245 is not set > # CONFIG_SENSORS_PC87360 is not set > # CONFIG_SENSORS_PC87427 is not set > # CONFIG_SENSORS_NTC_THERMISTOR is not set > # CONFIG_SENSORS_NCT6683 is not set > # CONFIG_SENSORS_NCT6775 is not set > # CONFIG_SENSORS_NCT7802 is not set > # CONFIG_SENSORS_NCT7904 is not set > # CONFIG_SENSORS_NPCM7XX is not set > # CONFIG_SENSORS_PCF8591 is not set > CONFIG_PMBUS=y > CONFIG_SENSORS_PMBUS=y > # CONFIG_SENSORS_ADM1275 is not set > # CONFIG_SENSORS_BEL_PFE is not set > # CONFIG_SENSORS_INSPUR_IPSPS is not set > # CONFIG_SENSORS_IR35221 is not set > # CONFIG_SENSORS_IR38064 is not set > # CONFIG_SENSORS_IRPS5401 is not set > # CONFIG_SENSORS_ISL68137 is not set > # CONFIG_SENSORS_LM25066 is not set > # CONFIG_SENSORS_LTC2978 is not set > # CONFIG_SENSORS_LTC3815 is not set > # CONFIG_SENSORS_MAX16064 is not set > # CONFIG_SENSORS_MAX20730 is not set > # CONFIG_SENSORS_MAX20751 is not set > # CONFIG_SENSORS_MAX31785 is not set > # CONFIG_SENSORS_MAX34440 is not set > # CONFIG_SENSORS_MAX8688 is not set > # CONFIG_SENSORS_PXE1610 is not set > # CONFIG_SENSORS_TPS40422 is not set > # CONFIG_SENSORS_TPS53679 is not set > # CONFIG_SENSORS_UCD9000 is not set > # CONFIG_SENSORS_UCD9200 is not set > # CONFIG_SENSORS_XDPE122 is not set > # CONFIG_SENSORS_ZL6100 is not set > # CONFIG_SENSORS_SHT21 is not set > # CONFIG_SENSORS_SHT3x is not set > # CONFIG_SENSORS_SHTC1 is not set > # CONFIG_SENSORS_SIS5595 is not set > # CONFIG_SENSORS_DME1737 is not set > # CONFIG_SENSORS_EMC1403 is not set > # CONFIG_SENSORS_EMC2103 is not set > # CONFIG_SENSORS_EMC6W201 is not set > # CONFIG_SENSORS_SMSC47M1 is not set > # CONFIG_SENSORS_SMSC47M192 is not set > # CONFIG_SENSORS_SMSC47B397 is not set > # CONFIG_SENSORS_SCH5627 is not set > # CONFIG_SENSORS_SCH5636 is not set > # CONFIG_SENSORS_STTS751 is not set > # CONFIG_SENSORS_SMM665 is not set > # CONFIG_SENSORS_ADC128D818 is not set > # CONFIG_SENSORS_ADS7828 is not set > # CONFIG_SENSORS_AMC6821 is not set > # CONFIG_SENSORS_INA209 is not set > # CONFIG_SENSORS_INA2XX is not set > # CONFIG_SENSORS_INA3221 is not set > # CONFIG_SENSORS_TC74 is not set > # CONFIG_SENSORS_THMC50 is not set > # CONFIG_SENSORS_TMP102 is not set > # CONFIG_SENSORS_TMP103 is not set > # CONFIG_SENSORS_TMP108 is not set > # CONFIG_SENSORS_TMP401 is not set > # CONFIG_SENSORS_TMP421 is not set > # CONFIG_SENSORS_TMP513 is not set > # CONFIG_SENSORS_VIA_CPUTEMP is not set > # CONFIG_SENSORS_VIA686A is not set > # CONFIG_SENSORS_VT1211 is not set > # CONFIG_SENSORS_VT8231 is not set > # CONFIG_SENSORS_W83773G is not set > # CONFIG_SENSORS_W83781D is not set > # CONFIG_SENSORS_W83791D is not set > # CONFIG_SENSORS_W83792D is not set > # CONFIG_SENSORS_W83793 is not set > # CONFIG_SENSORS_W83795 is not set > # CONFIG_SENSORS_W83L785TS is not set > # CONFIG_SENSORS_W83L786NG is not set > # CONFIG_SENSORS_W83627HF is not set > # CONFIG_SENSORS_W83627EHF is not set > # CONFIG_SENSORS_XGENE is not set > > # > # ACPI drivers > # > CONFIG_SENSORS_ACPI_POWER=y > CONFIG_SENSORS_ATK0110=y > CONFIG_THERMAL=y > # CONFIG_THERMAL_STATISTICS is not set > CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 > CONFIG_THERMAL_HWMON=y > CONFIG_THERMAL_WRITABLE_TRIPS=y > CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y > # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set > # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set > # CONFIG_THERMAL_GOV_FAIR_SHARE is not set > CONFIG_THERMAL_GOV_STEP_WISE=y > # CONFIG_THERMAL_GOV_BANG_BANG is not set > CONFIG_THERMAL_GOV_USER_SPACE=y > # CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set > # CONFIG_THERMAL_EMULATION is not set > > # > # Intel thermal drivers > # > # CONFIG_INTEL_POWERCLAMP is not set > CONFIG_X86_PKG_TEMP_THERMAL=y > # CONFIG_INTEL_SOC_DTS_THERMAL is not set > > # > # ACPI INT340X thermal drivers > # > # CONFIG_INT340X_THERMAL is not set > # end of ACPI INT340X thermal drivers > > CONFIG_INTEL_PCH_THERMAL=y > # end of Intel thermal drivers > > CONFIG_WATCHDOG=y > CONFIG_WATCHDOG_CORE=y > # CONFIG_WATCHDOG_NOWAYOUT is not set > CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y > CONFIG_WATCHDOG_OPEN_TIMEOUT=0 > # CONFIG_WATCHDOG_SYSFS is not set > > # > # Watchdog Pretimeout Governors > # > # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set > > # > # Watchdog Device Drivers > # > # CONFIG_SOFT_WATCHDOG is not set > # CONFIG_WDAT_WDT is not set > # CONFIG_XILINX_WATCHDOG is not set > # CONFIG_ZIIRAVE_WATCHDOG is not set > # CONFIG_CADENCE_WATCHDOG is not set > # CONFIG_DW_WATCHDOG is not set > # CONFIG_MAX63XX_WATCHDOG is not set > # CONFIG_ACQUIRE_WDT is not set > # CONFIG_ADVANTECH_WDT is not set > # CONFIG_ALIM1535_WDT is not set > # CONFIG_ALIM7101_WDT is not set > # CONFIG_EBC_C384_WDT is not set > # CONFIG_F71808E_WDT is not set > # CONFIG_SP5100_TCO is not set > # CONFIG_SBC_FITPC2_WATCHDOG is not set > # CONFIG_EUROTECH_WDT is not set > # CONFIG_IB700_WDT is not set > # CONFIG_IBMASR is not set > # CONFIG_WAFER_WDT is not set > # CONFIG_I6300ESB_WDT is not set > # CONFIG_IE6XX_WDT is not set > CONFIG_ITCO_WDT=y > CONFIG_ITCO_VENDOR_SUPPORT=y > # CONFIG_IT8712F_WDT is not set > # CONFIG_IT87_WDT is not set > # CONFIG_HP_WATCHDOG is not set > # CONFIG_SC1200_WDT is not set > # CONFIG_PC87413_WDT is not set > # CONFIG_NV_TCO is not set > # CONFIG_60XX_WDT is not set > # CONFIG_CPU5_WDT is not set > # CONFIG_SMSC_SCH311X_WDT is not set > # CONFIG_SMSC37B787_WDT is not set > # CONFIG_TQMX86_WDT is not set > # CONFIG_VIA_WDT is not set > # CONFIG_W83627HF_WDT is not set > # CONFIG_W83877F_WDT is not set > # CONFIG_W83977F_WDT is not set > # CONFIG_MACHZ_WDT is not set > # CONFIG_SBC_EPX_C3_WATCHDOG is not set > CONFIG_INTEL_MEI_WDT=y > # CONFIG_NI903X_WDT is not set > # CONFIG_NIC7018_WDT is not set > > # > # PCI-based Watchdog Cards > # > # CONFIG_PCIPCWATCHDOG is not set > # CONFIG_WDTPCI is not set > > # > # USB-based Watchdog Cards > # > # CONFIG_USBPCWATCHDOG is not set > CONFIG_SSB_POSSIBLE=y > # CONFIG_SSB is not set > CONFIG_BCMA_POSSIBLE=y > # CONFIG_BCMA is not set > > # > # Multifunction device drivers > # > CONFIG_MFD_CORE=y > # CONFIG_MFD_AS3711 is not set > # CONFIG_PMIC_ADP5520 is not set > # CONFIG_MFD_BCM590XX is not set > # CONFIG_MFD_BD9571MWV is not set > # CONFIG_MFD_AXP20X_I2C is not set > # CONFIG_MFD_MADERA is not set > # CONFIG_PMIC_DA903X is not set > # CONFIG_MFD_DA9052_I2C is not set > # CONFIG_MFD_DA9055 is not set > # CONFIG_MFD_DA9062 is not set > # CONFIG_MFD_DA9063 is not set > # CONFIG_MFD_DA9150 is not set > # CONFIG_MFD_DLN2 is not set > # CONFIG_MFD_MC13XXX_I2C is not set > # CONFIG_HTC_PASIC3 is not set > # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set > CONFIG_LPC_ICH=y > # CONFIG_LPC_SCH is not set > CONFIG_MFD_INTEL_LPSS=y > CONFIG_MFD_INTEL_LPSS_ACPI=y > CONFIG_MFD_INTEL_LPSS_PCI=y > # CONFIG_MFD_IQS62X is not set > # CONFIG_MFD_JANZ_CMODIO is not set > # CONFIG_MFD_KEMPLD is not set > # CONFIG_MFD_88PM800 is not set > # CONFIG_MFD_88PM805 is not set > # CONFIG_MFD_88PM860X is not set > # CONFIG_MFD_MAX14577 is not set > # CONFIG_MFD_MAX77693 is not set > # CONFIG_MFD_MAX77843 is not set > # CONFIG_MFD_MAX8907 is not set > # CONFIG_MFD_MAX8925 is not set > # CONFIG_MFD_MAX8997 is not set > # CONFIG_MFD_MAX8998 is not set > # CONFIG_MFD_MT6397 is not set > # CONFIG_MFD_MENF21BMC is not set > # CONFIG_MFD_VIPERBOARD is not set > # CONFIG_MFD_RETU is not set > # CONFIG_MFD_PCF50633 is not set > # CONFIG_MFD_RDC321X is not set > # CONFIG_MFD_RT5033 is not set > # CONFIG_MFD_RC5T583 is not set > # CONFIG_MFD_SEC_CORE is not set > # CONFIG_MFD_SI476X_CORE is not set > # CONFIG_MFD_SM501 is not set > # CONFIG_MFD_SKY81452 is not set > # CONFIG_MFD_SMSC is not set > # CONFIG_ABX500_CORE is not set > # CONFIG_MFD_SYSCON is not set > # CONFIG_MFD_TI_AM335X_TSCADC is not set > # CONFIG_MFD_LP3943 is not set > # CONFIG_MFD_LP8788 is not set > # CONFIG_MFD_TI_LMU is not set > # CONFIG_MFD_PALMAS is not set > # CONFIG_TPS6105X is not set > # CONFIG_TPS6507X is not set > # CONFIG_MFD_TPS65086 is not set > # CONFIG_MFD_TPS65090 is not set > # CONFIG_MFD_TI_LP873X is not set > # CONFIG_MFD_TPS6586X is not set > # CONFIG_MFD_TPS65912_I2C is not set > # CONFIG_MFD_TPS80031 is not set > # CONFIG_TWL4030_CORE is not set > # CONFIG_TWL6040_CORE is not set > # CONFIG_MFD_WL1273_CORE is not set > # CONFIG_MFD_LM3533 is not set > # CONFIG_MFD_TQMX86 is not set > # CONFIG_MFD_VX855 is not set > # CONFIG_MFD_ARIZONA_I2C is not set > # CONFIG_MFD_WM8400 is not set > # CONFIG_MFD_WM831X_I2C is not set > # CONFIG_MFD_WM8350_I2C is not set > # CONFIG_MFD_WM8994 is not set > # end of Multifunction device drivers > > # CONFIG_REGULATOR is not set > # CONFIG_RC_CORE is not set > # CONFIG_MEDIA_SUPPORT is not set > > # > # Graphics support > # > # CONFIG_AGP is not set > CONFIG_INTEL_GTT=y > CONFIG_VGA_ARB=y > CONFIG_VGA_ARB_MAX_GPUS=16 > # CONFIG_VGA_SWITCHEROO is not set > CONFIG_DRM=y > CONFIG_DRM_MIPI_DSI=y > # CONFIG_DRM_DP_AUX_CHARDEV is not set > # CONFIG_DRM_DEBUG_MM is not set > # CONFIG_DRM_DEBUG_SELFTEST is not set > CONFIG_DRM_KMS_HELPER=y > CONFIG_DRM_KMS_FB_HELPER=y > # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set > CONFIG_DRM_FBDEV_EMULATION=y > CONFIG_DRM_FBDEV_OVERALLOC=100 > # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set > # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set > # CONFIG_DRM_DP_CEC is not set > > # > # I2C encoder or helper chips > # > # CONFIG_DRM_I2C_CH7006 is not set > # CONFIG_DRM_I2C_SIL164 is not set > # CONFIG_DRM_I2C_NXP_TDA998X is not set > # CONFIG_DRM_I2C_NXP_TDA9950 is not set > # end of I2C encoder or helper chips > > # > # ARM devices > # > # end of ARM devices > > # CONFIG_DRM_RADEON is not set > # CONFIG_DRM_AMDGPU is not set > # CONFIG_DRM_NOUVEAU is not set > CONFIG_DRM_I915=y > CONFIG_DRM_I915_FORCE_PROBE="" > CONFIG_DRM_I915_CAPTURE_ERROR=y > CONFIG_DRM_I915_COMPRESS_ERROR=y > CONFIG_DRM_I915_USERPTR=y > # CONFIG_DRM_I915_GVT is not set > > # > # drm/i915 Debugging > # > # CONFIG_DRM_I915_WERROR is not set > # CONFIG_DRM_I915_DEBUG is not set > # CONFIG_DRM_I915_DEBUG_MMIO is not set > # CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set > # CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set > # CONFIG_DRM_I915_DEBUG_GUC is not set > # CONFIG_DRM_I915_SELFTEST is not set > # CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set > # CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set > # CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set > # end of drm/i915 Debugging > > # > # drm/i915 Profile Guided Optimisation > # > CONFIG_DRM_I915_FENCE_TIMEOUT=10000 > CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 > CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 > CONFIG_DRM_I915_PREEMPT_TIMEOUT=100 > CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 > CONFIG_DRM_I915_STOP_TIMEOUT=100 > CONFIG_DRM_I915_TIMESLICE_DURATION=1 > # end of drm/i915 Profile Guided Optimisation > > # CONFIG_DRM_VGEM is not set > # CONFIG_DRM_VKMS is not set > # CONFIG_DRM_VMWGFX is not set > # CONFIG_DRM_GMA500 is not set > # CONFIG_DRM_UDL is not set > # CONFIG_DRM_AST is not set > # CONFIG_DRM_MGAG200 is not set > # CONFIG_DRM_QXL is not set > # CONFIG_DRM_BOCHS is not set > CONFIG_DRM_PANEL=y > > # > # Display Panels > # > # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set > # end of Display Panels > > CONFIG_DRM_BRIDGE=y > CONFIG_DRM_PANEL_BRIDGE=y > > # > # Display Interface Bridges > # > # CONFIG_DRM_ANALOGIX_ANX78XX is not set > # end of Display Interface Bridges > > # CONFIG_DRM_ETNAVIV is not set > # CONFIG_DRM_CIRRUS_QEMU is not set > # CONFIG_DRM_GM12U320 is not set > # CONFIG_DRM_VBOXVIDEO is not set > # CONFIG_DRM_LEGACY is not set > CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y > > # > # Frame buffer Devices > # > CONFIG_FB_CMDLINE=y > CONFIG_FB_NOTIFY=y > CONFIG_FB=y > CONFIG_FIRMWARE_EDID=y > CONFIG_FB_CFB_FILLRECT=y > CONFIG_FB_CFB_COPYAREA=y > CONFIG_FB_CFB_IMAGEBLIT=y > CONFIG_FB_SYS_FILLRECT=y > CONFIG_FB_SYS_COPYAREA=y > CONFIG_FB_SYS_IMAGEBLIT=y > # CONFIG_FB_FOREIGN_ENDIAN is not set > CONFIG_FB_SYS_FOPS=y > CONFIG_FB_DEFERRED_IO=y > CONFIG_FB_MODE_HELPERS=y > # CONFIG_FB_TILEBLITTING is not set > > # > # Frame buffer hardware drivers > # > # CONFIG_FB_CIRRUS is not set > # CONFIG_FB_PM2 is not set > # CONFIG_FB_CYBER2000 is not set > # CONFIG_FB_ARC is not set > # CONFIG_FB_ASILIANT is not set > # CONFIG_FB_IMSTT is not set > # CONFIG_FB_VGA16 is not set > # CONFIG_FB_VESA is not set > # CONFIG_FB_EFI is not set > # CONFIG_FB_N411 is not set > # CONFIG_FB_HGA is not set > # CONFIG_FB_OPENCORES is not set > # CONFIG_FB_S1D13XXX is not set > # CONFIG_FB_NVIDIA is not set > # CONFIG_FB_RIVA is not set > # CONFIG_FB_I740 is not set > # CONFIG_FB_LE80578 is not set > # CONFIG_FB_MATROX is not set > # CONFIG_FB_RADEON is not set > # CONFIG_FB_ATY128 is not set > # CONFIG_FB_ATY is not set > # CONFIG_FB_S3 is not set > # CONFIG_FB_SAVAGE is not set > # CONFIG_FB_SIS is not set > # CONFIG_FB_NEOMAGIC is not set > # CONFIG_FB_KYRO is not set > # CONFIG_FB_3DFX is not set > # CONFIG_FB_VOODOO1 is not set > # CONFIG_FB_VT8623 is not set > # CONFIG_FB_TRIDENT is not set > # CONFIG_FB_ARK is not set > # CONFIG_FB_PM3 is not set > # CONFIG_FB_CARMINE is not set > # CONFIG_FB_SMSCUFX is not set > # CONFIG_FB_UDL is not set > # CONFIG_FB_IBM_GXT4500 is not set > # CONFIG_FB_VIRTUAL is not set > # CONFIG_FB_METRONOME is not set > # CONFIG_FB_MB862XX is not set > # CONFIG_FB_SIMPLE is not set > # CONFIG_FB_SM712 is not set > # end of Frame buffer Devices > > # > # Backlight & LCD device support > # > # CONFIG_LCD_CLASS_DEVICE is not set > CONFIG_BACKLIGHT_CLASS_DEVICE=y > # CONFIG_BACKLIGHT_GENERIC is not set > # CONFIG_BACKLIGHT_APPLE is not set > # CONFIG_BACKLIGHT_QCOM_WLED is not set > # CONFIG_BACKLIGHT_SAHARA is not set > # CONFIG_BACKLIGHT_ADP8860 is not set > # CONFIG_BACKLIGHT_ADP8870 is not set > # CONFIG_BACKLIGHT_LM3639 is not set > # CONFIG_BACKLIGHT_LV5207LP is not set > # CONFIG_BACKLIGHT_BD6107 is not set > # CONFIG_BACKLIGHT_ARCXCNN is not set > # end of Backlight & LCD device support > > CONFIG_HDMI=y > > # > # Console display driver support > # > CONFIG_VGA_CONSOLE=y > # CONFIG_VGACON_SOFT_SCROLLBACK is not set > CONFIG_DUMMY_CONSOLE=y > CONFIG_DUMMY_CONSOLE_COLUMNS=80 > CONFIG_DUMMY_CONSOLE_ROWS=25 > # CONFIG_FRAMEBUFFER_CONSOLE is not set > # end of Console display driver support > > CONFIG_LOGO=y > CONFIG_LOGO_LINUX_MONO=y > CONFIG_LOGO_LINUX_VGA16=y > CONFIG_LOGO_LINUX_CLUT224=y > # end of Graphics support > > # CONFIG_SOUND is not set > > # > # HID support > # > CONFIG_HID=y > # CONFIG_HID_BATTERY_STRENGTH is not set > # CONFIG_HIDRAW is not set > # CONFIG_UHID is not set > CONFIG_HID_GENERIC=y > > # > # Special HID drivers > # > # CONFIG_HID_A4TECH is not set > # CONFIG_HID_ACCUTOUCH is not set > # CONFIG_HID_ACRUX is not set > # CONFIG_HID_APPLE is not set > # CONFIG_HID_APPLEIR is not set > # CONFIG_HID_AUREAL is not set > # CONFIG_HID_BELKIN is not set > # CONFIG_HID_BETOP_FF is not set > # CONFIG_HID_CHERRY is not set > # CONFIG_HID_CHICONY is not set > # CONFIG_HID_COUGAR is not set > # CONFIG_HID_MACALLY is not set > # CONFIG_HID_CMEDIA is not set > # CONFIG_HID_CREATIVE_SB0540 is not set > # CONFIG_HID_CYPRESS is not set > # CONFIG_HID_DRAGONRISE is not set > # CONFIG_HID_EMS_FF is not set > # CONFIG_HID_ELECOM is not set > # CONFIG_HID_ELO is not set > # CONFIG_HID_EZKEY is not set > # CONFIG_HID_GEMBIRD is not set > # CONFIG_HID_GFRM is not set > # CONFIG_HID_GLORIOUS is not set > # CONFIG_HID_HOLTEK is not set > # CONFIG_HID_KEYTOUCH is not set > # CONFIG_HID_KYE is not set > # CONFIG_HID_UCLOGIC is not set > # CONFIG_HID_WALTOP is not set > # CONFIG_HID_VIEWSONIC is not set > # CONFIG_HID_GYRATION is not set > # CONFIG_HID_ICADE is not set > # CONFIG_HID_ITE is not set > # CONFIG_HID_JABRA is not set > # CONFIG_HID_TWINHAN is not set > # CONFIG_HID_KENSINGTON is not set > # CONFIG_HID_LCPOWER is not set > # CONFIG_HID_LENOVO is not set > # CONFIG_HID_MAGICMOUSE is not set > # CONFIG_HID_MALTRON is not set > # CONFIG_HID_MAYFLASH is not set > # CONFIG_HID_REDRAGON is not set > # CONFIG_HID_MICROSOFT is not set > # CONFIG_HID_MONTEREY is not set > # CONFIG_HID_MULTITOUCH is not set > # CONFIG_HID_NTI is not set > # CONFIG_HID_NTRIG is not set > # CONFIG_HID_ORTEK is not set > # CONFIG_HID_PANTHERLORD is not set > # CONFIG_HID_PENMOUNT is not set > # CONFIG_HID_PETALYNX is not set > # CONFIG_HID_PICOLCD is not set > # CONFIG_HID_PLANTRONICS is not set > # CONFIG_HID_PRIMAX is not set > # CONFIG_HID_RETRODE is not set > # CONFIG_HID_ROCCAT is not set > # CONFIG_HID_SAITEK is not set > # CONFIG_HID_SAMSUNG is not set > # CONFIG_HID_SPEEDLINK is not set > # CONFIG_HID_STEAM is not set > # CONFIG_HID_STEELSERIES is not set > # CONFIG_HID_SUNPLUS is not set > # CONFIG_HID_RMI is not set > # CONFIG_HID_GREENASIA is not set > # CONFIG_HID_SMARTJOYPLUS is not set > # CONFIG_HID_TIVO is not set > # CONFIG_HID_TOPSEED is not set > # CONFIG_HID_THRUSTMASTER is not set > # CONFIG_HID_UDRAW_PS3 is not set > # CONFIG_HID_WACOM is not set > # CONFIG_HID_XINMO is not set > # CONFIG_HID_ZEROPLUS is not set > # CONFIG_HID_ZYDACRON is not set > # CONFIG_HID_SENSOR_HUB is not set > # CONFIG_HID_ALPS is not set > # CONFIG_HID_MCP2221 is not set > # end of Special HID drivers > > # > # USB HID support > # > CONFIG_USB_HID=y > # CONFIG_HID_PID is not set > # CONFIG_USB_HIDDEV is not set > # end of USB HID support > > # > # I2C HID support > # > # CONFIG_I2C_HID is not set > # end of I2C HID support > > # > # Intel ISH HID support > # > CONFIG_INTEL_ISH_HID=y > # CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER is not set > # end of Intel ISH HID support > # end of HID support > > CONFIG_USB_OHCI_LITTLE_ENDIAN=y > CONFIG_USB_SUPPORT=y > CONFIG_USB_COMMON=y > # CONFIG_USB_ULPI_BUS is not set > CONFIG_USB_ARCH_HAS_HCD=y > CONFIG_USB=y > CONFIG_USB_PCI=y > # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set > > # > # Miscellaneous USB options > # > CONFIG_USB_DEFAULT_PERSIST=y > CONFIG_USB_DYNAMIC_MINORS=y > # CONFIG_USB_OTG is not set > # CONFIG_USB_OTG_WHITELIST is not set > # CONFIG_USB_OTG_BLACKLIST_HUB is not set > CONFIG_USB_AUTOSUSPEND_DELAY=2 > # CONFIG_USB_MON is not set > > # > # USB Host Controller Drivers > # > # CONFIG_USB_C67X00_HCD is not set > CONFIG_USB_XHCI_HCD=y > # CONFIG_USB_XHCI_DBGCAP is not set > CONFIG_USB_XHCI_PCI=y > # CONFIG_USB_XHCI_PLATFORM is not set > CONFIG_USB_EHCI_HCD=y > # CONFIG_USB_EHCI_ROOT_HUB_TT is not set > CONFIG_USB_EHCI_TT_NEWSCHED=y > CONFIG_USB_EHCI_PCI=y > # CONFIG_USB_EHCI_FSL is not set > # CONFIG_USB_EHCI_HCD_PLATFORM is not set > # CONFIG_USB_OXU210HP_HCD is not set > # CONFIG_USB_ISP116X_HCD is not set > # CONFIG_USB_FOTG210_HCD is not set > CONFIG_USB_OHCI_HCD=y > CONFIG_USB_OHCI_HCD_PCI=y > # CONFIG_USB_OHCI_HCD_PLATFORM is not set > CONFIG_USB_UHCI_HCD=y > # CONFIG_USB_SL811_HCD is not set > # CONFIG_USB_R8A66597_HCD is not set > # CONFIG_USB_HCD_TEST_MODE is not set > > # > # USB Device Class drivers > # > # CONFIG_USB_ACM is not set > # CONFIG_USB_PRINTER is not set > # CONFIG_USB_WDM is not set > # CONFIG_USB_TMC is not set > > # > # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may > # > > # > # also be needed; see USB_STORAGE Help for more info > # > CONFIG_USB_STORAGE=y > # CONFIG_USB_STORAGE_DEBUG is not set > # CONFIG_USB_STORAGE_REALTEK is not set > # CONFIG_USB_STORAGE_DATAFAB is not set > # CONFIG_USB_STORAGE_FREECOM is not set > # CONFIG_USB_STORAGE_ISD200 is not set > # CONFIG_USB_STORAGE_USBAT is not set > # CONFIG_USB_STORAGE_SDDR09 is not set > # CONFIG_USB_STORAGE_SDDR55 is not set > # CONFIG_USB_STORAGE_JUMPSHOT is not set > # CONFIG_USB_STORAGE_ALAUDA is not set > # CONFIG_USB_STORAGE_ONETOUCH is not set > # CONFIG_USB_STORAGE_KARMA is not set > # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set > # CONFIG_USB_STORAGE_ENE_UB6250 is not set > # CONFIG_USB_UAS is not set > > # > # USB Imaging devices > # > # CONFIG_USB_MDC800 is not set > # CONFIG_USB_MICROTEK is not set > # CONFIG_USBIP_CORE is not set > # CONFIG_USB_CDNS3 is not set > # CONFIG_USB_MUSB_HDRC is not set > # CONFIG_USB_DWC3 is not set > # CONFIG_USB_DWC2 is not set > # CONFIG_USB_CHIPIDEA is not set > # CONFIG_USB_ISP1760 is not set > > # > # USB port drivers > # > # CONFIG_USB_SERIAL is not set > > # > # USB Miscellaneous drivers > # > # CONFIG_USB_EMI62 is not set > # CONFIG_USB_EMI26 is not set > # CONFIG_USB_ADUTUX is not set > # CONFIG_USB_SEVSEG is not set > # CONFIG_USB_LEGOTOWER is not set > # CONFIG_USB_LCD is not set > # CONFIG_USB_CYPRESS_CY7C63 is not set > # CONFIG_USB_CYTHERM is not set > # CONFIG_USB_IDMOUSE is not set > # CONFIG_USB_FTDI_ELAN is not set > # CONFIG_USB_APPLEDISPLAY is not set > # CONFIG_APPLE_MFI_FASTCHARGE is not set > # CONFIG_USB_SISUSBVGA is not set > # CONFIG_USB_LD is not set > # CONFIG_USB_TRANCEVIBRATOR is not set > # CONFIG_USB_IOWARRIOR is not set > # CONFIG_USB_TEST is not set > # CONFIG_USB_EHSET_TEST_FIXTURE is not set > # CONFIG_USB_ISIGHTFW is not set > # CONFIG_USB_YUREX is not set > # CONFIG_USB_EZUSB_FX2 is not set > # CONFIG_USB_HUB_USB251XB is not set > # CONFIG_USB_HSIC_USB3503 is not set > # CONFIG_USB_HSIC_USB4604 is not set > # CONFIG_USB_LINK_LAYER_TEST is not set > > # > # USB Physical Layer drivers > # > # CONFIG_NOP_USB_XCEIV is not set > # CONFIG_USB_ISP1301 is not set > # end of USB Physical Layer drivers > > CONFIG_USB_GADGET=m > # CONFIG_USB_GADGET_DEBUG is not set > # CONFIG_USB_GADGET_DEBUG_FILES is not set > # CONFIG_USB_GADGET_DEBUG_FS is not set > CONFIG_USB_GADGET_VBUS_DRAW=2 > CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 > > # > # USB Peripheral Controller > # > # CONFIG_USB_FOTG210_UDC is not set > # CONFIG_USB_GR_UDC is not set > # CONFIG_USB_R8A66597 is not set > # CONFIG_USB_PXA27X is not set > # CONFIG_USB_MV_UDC is not set > # CONFIG_USB_MV_U3D is not set > # CONFIG_USB_M66592 is not set > # CONFIG_USB_BDC_UDC is not set > # CONFIG_USB_AMD5536UDC is not set > # CONFIG_USB_NET2272 is not set > # CONFIG_USB_NET2280 is not set > # CONFIG_USB_GOKU is not set > # CONFIG_USB_EG20T is not set > # CONFIG_USB_DUMMY_HCD is not set > # end of USB Peripheral Controller > > CONFIG_USB_LIBCOMPOSITE=m > CONFIG_USB_F_FS=m > CONFIG_USB_CONFIGFS=m > # CONFIG_USB_CONFIGFS_SERIAL is not set > # CONFIG_USB_CONFIGFS_ACM is not set > # CONFIG_USB_CONFIGFS_OBEX is not set > # CONFIG_USB_CONFIGFS_NCM is not set > # CONFIG_USB_CONFIGFS_ECM is not set > # CONFIG_USB_CONFIGFS_ECM_SUBSET is not set > # CONFIG_USB_CONFIGFS_RNDIS is not set > # CONFIG_USB_CONFIGFS_EEM is not set > # CONFIG_USB_CONFIGFS_MASS_STORAGE is not set > # CONFIG_USB_CONFIGFS_F_LB_SS is not set > CONFIG_USB_CONFIGFS_F_FS=y > # CONFIG_USB_CONFIGFS_F_HID is not set > # CONFIG_USB_CONFIGFS_F_PRINTER is not set > > # > # USB Gadget precomposed configurations > # > # CONFIG_USB_ZERO is not set > # CONFIG_USB_ETH is not set > # CONFIG_USB_G_NCM is not set > # CONFIG_USB_GADGETFS is not set > # CONFIG_USB_FUNCTIONFS is not set > # CONFIG_USB_MASS_STORAGE is not set > # CONFIG_USB_G_SERIAL is not set > # CONFIG_USB_G_PRINTER is not set > # CONFIG_USB_CDC_COMPOSITE is not set > # CONFIG_USB_G_ACM_MS is not set > # CONFIG_USB_G_MULTI is not set > # CONFIG_USB_G_HID is not set > # CONFIG_USB_G_DBGP is not set > # CONFIG_USB_RAW_GADGET is not set > # end of USB Gadget precomposed configurations > > # CONFIG_TYPEC is not set > # CONFIG_USB_ROLE_SWITCH is not set > # CONFIG_MMC is not set > # CONFIG_MEMSTICK is not set > # CONFIG_NEW_LEDS is not set > # CONFIG_ACCESSIBILITY is not set > # CONFIG_INFINIBAND is not set > CONFIG_EDAC_ATOMIC_SCRUB=y > CONFIG_EDAC_SUPPORT=y > # CONFIG_EDAC is not set > CONFIG_RTC_LIB=y > CONFIG_RTC_MC146818_LIB=y > CONFIG_RTC_CLASS=y > CONFIG_RTC_HCTOSYS=y > CONFIG_RTC_HCTOSYS_DEVICE="rtc0" > CONFIG_RTC_SYSTOHC=y > CONFIG_RTC_SYSTOHC_DEVICE="rtc0" > # CONFIG_RTC_DEBUG is not set > CONFIG_RTC_NVMEM=y > > # > # RTC interfaces > # > CONFIG_RTC_INTF_SYSFS=y > CONFIG_RTC_INTF_PROC=y > CONFIG_RTC_INTF_DEV=y > # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set > # CONFIG_RTC_DRV_TEST is not set > > # > # I2C RTC drivers > # > # CONFIG_RTC_DRV_ABB5ZES3 is not set > # CONFIG_RTC_DRV_ABEOZ9 is not set > # CONFIG_RTC_DRV_ABX80X is not set > # CONFIG_RTC_DRV_DS1307 is not set > # CONFIG_RTC_DRV_DS1374 is not set > # CONFIG_RTC_DRV_DS1672 is not set > # CONFIG_RTC_DRV_MAX6900 is not set > # CONFIG_RTC_DRV_RS5C372 is not set > # CONFIG_RTC_DRV_ISL1208 is not set > # CONFIG_RTC_DRV_ISL12022 is not set > # CONFIG_RTC_DRV_X1205 is not set > # CONFIG_RTC_DRV_PCF8523 is not set > # CONFIG_RTC_DRV_PCF85063 is not set > # CONFIG_RTC_DRV_PCF85363 is not set > # CONFIG_RTC_DRV_PCF8563 is not set > # CONFIG_RTC_DRV_PCF8583 is not set > # CONFIG_RTC_DRV_M41T80 is not set > # CONFIG_RTC_DRV_BQ32K is not set > # CONFIG_RTC_DRV_S35390A is not set > # CONFIG_RTC_DRV_FM3130 is not set > # CONFIG_RTC_DRV_RX8010 is not set > # CONFIG_RTC_DRV_RX8581 is not set > # CONFIG_RTC_DRV_RX8025 is not set > # CONFIG_RTC_DRV_EM3027 is not set > # CONFIG_RTC_DRV_RV3028 is not set > # CONFIG_RTC_DRV_RV8803 is not set > # CONFIG_RTC_DRV_SD3078 is not set > > # > # SPI RTC drivers > # > CONFIG_RTC_I2C_AND_SPI=y > > # > # SPI and I2C RTC drivers > # > # CONFIG_RTC_DRV_DS3232 is not set > # CONFIG_RTC_DRV_PCF2127 is not set > # CONFIG_RTC_DRV_RV3029C2 is not set > > # > # Platform RTC drivers > # > CONFIG_RTC_DRV_CMOS=y > # CONFIG_RTC_DRV_DS1286 is not set > # CONFIG_RTC_DRV_DS1511 is not set > # CONFIG_RTC_DRV_DS1553 is not set > # CONFIG_RTC_DRV_DS1685_FAMILY is not set > # CONFIG_RTC_DRV_DS1742 is not set > # CONFIG_RTC_DRV_DS2404 is not set > # CONFIG_RTC_DRV_STK17TA8 is not set > # CONFIG_RTC_DRV_M48T86 is not set > # CONFIG_RTC_DRV_M48T35 is not set > # CONFIG_RTC_DRV_M48T59 is not set > # CONFIG_RTC_DRV_MSM6242 is not set > # CONFIG_RTC_DRV_BQ4802 is not set > # CONFIG_RTC_DRV_RP5C01 is not set > # CONFIG_RTC_DRV_V3020 is not set > > # > # on-CPU RTC drivers > # > # CONFIG_RTC_DRV_FTRTC010 is not set > > # > # HID Sensor RTC drivers > # > # CONFIG_DMADEVICES is not set > > # > # DMABUF options > # > CONFIG_SYNC_FILE=y > # CONFIG_SW_SYNC is not set > # CONFIG_UDMABUF is not set > # CONFIG_DMABUF_MOVE_NOTIFY is not set > # CONFIG_DMABUF_SELFTESTS is not set > # CONFIG_DMABUF_HEAPS is not set > # end of DMABUF options > > # CONFIG_AUXDISPLAY is not set > # CONFIG_UIO is not set > # CONFIG_VFIO is not set > # CONFIG_VIRT_DRIVERS is not set > # CONFIG_VIRTIO_MENU is not set > # CONFIG_VDPA_MENU is not set > CONFIG_VHOST_MENU=y > # CONFIG_VHOST_NET is not set > # CONFIG_VHOST_VDPA is not set > # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set > > # > # Microsoft Hyper-V guest support > # > # end of Microsoft Hyper-V guest support > > # CONFIG_GREYBUS is not set > # CONFIG_STAGING is not set > CONFIG_X86_PLATFORM_DEVICES=y > CONFIG_ACPI_WMI=y > CONFIG_WMI_BMOF=y > # CONFIG_INTEL_WMI_THUNDERBOLT is not set > CONFIG_MXM_WMI=y > # CONFIG_PEAQ_WMI is not set > # CONFIG_XIAOMI_WMI is not set > # CONFIG_ACERHDF is not set > # CONFIG_ACER_WIRELESS is not set > # CONFIG_ACER_WMI is not set > # CONFIG_APPLE_GMUX is not set > # CONFIG_ASUS_LAPTOP is not set > # CONFIG_ASUS_WIRELESS is not set > # CONFIG_DCDBAS is not set > # CONFIG_DELL_SMBIOS is not set > # CONFIG_DELL_RBU is not set > # CONFIG_DELL_SMO8800 is not set > # CONFIG_DELL_WMI_AIO is not set > # CONFIG_FUJITSU_LAPTOP is not set > # CONFIG_FUJITSU_TABLET is not set > # CONFIG_GPD_POCKET_FAN is not set > # CONFIG_HP_ACCEL is not set > # CONFIG_HP_WIRELESS is not set > # CONFIG_HP_WMI is not set > # CONFIG_IBM_RTL is not set > # CONFIG_SENSORS_HDAPS is not set > # CONFIG_INTEL_ATOMISP2_PM is not set > # CONFIG_INTEL_HID_EVENT is not set > # CONFIG_INTEL_MENLOW is not set > # CONFIG_INTEL_VBTN is not set > # CONFIG_SURFACE_3_POWER_OPREGION is not set > # CONFIG_SURFACE_PRO3_BUTTON is not set > # CONFIG_MSI_WMI is not set > # CONFIG_SAMSUNG_LAPTOP is not set > # CONFIG_SAMSUNG_Q10 is not set > # CONFIG_TOSHIBA_BT_RFKILL is not set > # CONFIG_TOSHIBA_HAPS is not set > # CONFIG_TOSHIBA_WMI is not set > # CONFIG_ACPI_CMPC is not set > # CONFIG_LG_LAPTOP is not set > # CONFIG_PANASONIC_LAPTOP is not set > # CONFIG_SYSTEM76_ACPI is not set > # CONFIG_TOPSTAR_LAPTOP is not set > # CONFIG_I2C_MULTI_INSTANTIATE is not set > # CONFIG_INTEL_IPS is not set > # CONFIG_INTEL_RST is not set > # CONFIG_INTEL_SMARTCONNECT is not set > > # > # Intel Speed Select Technology interface support > # > CONFIG_INTEL_SPEED_SELECT_INTERFACE=y > # end of Intel Speed Select Technology interface support > > # CONFIG_INTEL_TURBO_MAX_3 is not set > # CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set > # CONFIG_INTEL_PMC_CORE is not set > # CONFIG_INTEL_PMC_IPC is not set > # CONFIG_INTEL_PUNIT_IPC is not set > CONFIG_PMC_ATOM=y > # CONFIG_MFD_CROS_EC is not set > # CONFIG_CHROME_PLATFORMS is not set > # CONFIG_MELLANOX_PLATFORM is not set > CONFIG_CLKDEV_LOOKUP=y > CONFIG_HAVE_CLK_PREPARE=y > CONFIG_COMMON_CLK=y > > # > # Common Clock Framework > # > # CONFIG_COMMON_CLK_MAX9485 is not set > # CONFIG_COMMON_CLK_SI5341 is not set > # CONFIG_COMMON_CLK_SI5351 is not set > # CONFIG_COMMON_CLK_SI544 is not set > # CONFIG_COMMON_CLK_CDCE706 is not set > # CONFIG_COMMON_CLK_CS2000_CP is not set > # end of Common Clock Framework > > # CONFIG_HWSPINLOCK is not set > > # > # Clock Source drivers > # > CONFIG_CLKEVT_I8253=y > CONFIG_I8253_LOCK=y > CONFIG_CLKBLD_I8253=y > # end of Clock Source drivers > > CONFIG_MAILBOX=y > CONFIG_PCC=y > # CONFIG_ALTERA_MBOX is not set > CONFIG_IOMMU_IOVA=y > CONFIG_IOASID=y > CONFIG_IOMMU_API=y > CONFIG_IOMMU_SUPPORT=y > > # > # Generic IOMMU Pagetable Support > # > # end of Generic IOMMU Pagetable Support > > # CONFIG_IOMMU_DEBUGFS is not set > # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set > # CONFIG_AMD_IOMMU is not set > CONFIG_DMAR_TABLE=y > CONFIG_INTEL_IOMMU=y > CONFIG_INTEL_IOMMU_SVM=y > CONFIG_INTEL_IOMMU_DEFAULT_ON=y > CONFIG_INTEL_IOMMU_FLOPPY_WA=y > # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set > # CONFIG_IRQ_REMAP is not set > > # > # Remoteproc drivers > # > # CONFIG_REMOTEPROC is not set > # end of Remoteproc drivers > > # > # Rpmsg drivers > # > # CONFIG_RPMSG_QCOM_GLINK_RPM is not set > # CONFIG_RPMSG_VIRTIO is not set > # end of Rpmsg drivers > > # CONFIG_SOUNDWIRE is not set > > # > # SOC (System On Chip) specific Drivers > # > > # > # Amlogic SoC drivers > # > # end of Amlogic SoC drivers > > # > # Aspeed SoC drivers > # > # end of Aspeed SoC drivers > > # > # Broadcom SoC drivers > # > # end of Broadcom SoC drivers > > # > # NXP/Freescale QorIQ SoC drivers > # > # end of NXP/Freescale QorIQ SoC drivers > > # > # i.MX SoC drivers > # > # end of i.MX SoC drivers > > # > # Qualcomm SoC drivers > # > # end of Qualcomm SoC drivers > > # CONFIG_SOC_TI is not set > > # > # Xilinx SoC drivers > # > # CONFIG_XILINX_VCU is not set > # end of Xilinx SoC drivers > # end of SOC (System On Chip) specific Drivers > > # CONFIG_PM_DEVFREQ is not set > # CONFIG_EXTCON is not set > # CONFIG_MEMORY is not set > # CONFIG_IIO is not set > # CONFIG_NTB is not set > # CONFIG_VME_BUS is not set > # CONFIG_PWM is not set > > # > # IRQ chip support > # > # end of IRQ chip support > > # CONFIG_IPACK_BUS is not set > # CONFIG_RESET_CONTROLLER is not set > > # > # PHY Subsystem > # > # CONFIG_GENERIC_PHY is not set > # CONFIG_BCM_KONA_USB2_PHY is not set > # CONFIG_PHY_PXA_28NM_HSIC is not set > # CONFIG_PHY_PXA_28NM_USB2 is not set > # CONFIG_PHY_INTEL_EMMC is not set > # end of PHY Subsystem > > # CONFIG_POWERCAP is not set > # CONFIG_MCB is not set > > # > # Performance monitor support > # > # end of Performance monitor support > > CONFIG_RAS=y > # CONFIG_USB4 is not set > > # > # Android > # > # CONFIG_ANDROID is not set > # end of Android > > # CONFIG_LIBNVDIMM is not set > # CONFIG_DAX is not set > CONFIG_NVMEM=y > # CONFIG_NVMEM_SYSFS is not set > > # > # HW tracing support > # > # CONFIG_STM is not set > # CONFIG_INTEL_TH is not set > # end of HW tracing support > > # CONFIG_FPGA is not set > # CONFIG_TEE is not set > # CONFIG_UNISYS_VISORBUS is not set > # CONFIG_SIOX is not set > # CONFIG_SLIMBUS is not set > # CONFIG_INTERCONNECT is not set > # CONFIG_COUNTER is not set > # CONFIG_MOST is not set > # end of Device Drivers > > # > # File systems > # > CONFIG_DCACHE_WORD_ACCESS=y > CONFIG_VALIDATE_FS_PARSER=y > CONFIG_FS_IOMAP=y > # CONFIG_EXT2_FS is not set > # CONFIG_EXT3_FS is not set > CONFIG_EXT4_FS=y > CONFIG_EXT4_USE_FOR_EXT2=y > CONFIG_EXT4_FS_POSIX_ACL=y > CONFIG_EXT4_FS_SECURITY=y > # CONFIG_EXT4_DEBUG is not set > CONFIG_JBD2=y > # CONFIG_JBD2_DEBUG is not set > CONFIG_FS_MBCACHE=y > # CONFIG_REISERFS_FS is not set > # CONFIG_JFS_FS is not set > CONFIG_XFS_FS=y > CONFIG_XFS_QUOTA=y > CONFIG_XFS_POSIX_ACL=y > # CONFIG_XFS_RT is not set > # CONFIG_XFS_ONLINE_SCRUB is not set > # CONFIG_XFS_WARN is not set > # CONFIG_XFS_DEBUG is not set > # CONFIG_GFS2_FS is not set > # CONFIG_OCFS2_FS is not set > CONFIG_BTRFS_FS=y > CONFIG_BTRFS_FS_POSIX_ACL=y > CONFIG_BTRFS_FS_CHECK_INTEGRITY=y > # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set > CONFIG_BTRFS_DEBUG=y > # CONFIG_BTRFS_ASSERT is not set > CONFIG_BTRFS_FS_REF_VERIFY=y > CONFIG_NILFS2_FS=m > CONFIG_F2FS_FS=m > CONFIG_F2FS_STAT_FS=y > CONFIG_F2FS_FS_XATTR=y > CONFIG_F2FS_FS_POSIX_ACL=y > CONFIG_F2FS_FS_SECURITY=y > # CONFIG_F2FS_CHECK_FS is not set > # CONFIG_F2FS_IO_TRACE is not set > # CONFIG_F2FS_FAULT_INJECTION is not set > # CONFIG_F2FS_FS_COMPRESSION is not set > # CONFIG_FS_DAX is not set > CONFIG_FS_POSIX_ACL=y > CONFIG_EXPORTFS=y > CONFIG_EXPORTFS_BLOCK_OPS=y > CONFIG_FILE_LOCKING=y > CONFIG_MANDATORY_FILE_LOCKING=y > # CONFIG_FS_ENCRYPTION is not set > # CONFIG_FS_VERITY is not set > CONFIG_FSNOTIFY=y > CONFIG_DNOTIFY=y > CONFIG_INOTIFY_USER=y > CONFIG_FANOTIFY=y > CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y > # CONFIG_QUOTA is not set > # CONFIG_QUOTA_NETLINK_INTERFACE is not set > CONFIG_QUOTACTL=y > CONFIG_QUOTACTL_COMPAT=y > CONFIG_AUTOFS4_FS=y > CONFIG_AUTOFS_FS=y > CONFIG_FUSE_FS=m > # CONFIG_CUSE is not set > # CONFIG_VIRTIO_FS is not set > # CONFIG_OVERLAY_FS is not set > > # > # Caches > # > CONFIG_FSCACHE=y > CONFIG_FSCACHE_STATS=y > # CONFIG_FSCACHE_HISTOGRAM is not set > # CONFIG_FSCACHE_DEBUG is not set > CONFIG_FSCACHE_OBJECT_LIST=y > CONFIG_CACHEFILES=y > # CONFIG_CACHEFILES_DEBUG is not set > # CONFIG_CACHEFILES_HISTOGRAM is not set > # end of Caches > > # > # CD-ROM/DVD Filesystems > # > # CONFIG_ISO9660_FS is not set > # CONFIG_UDF_FS is not set > # end of CD-ROM/DVD Filesystems > > # > # DOS/FAT/EXFAT/NT Filesystems > # > # CONFIG_MSDOS_FS is not set > # CONFIG_VFAT_FS is not set > # CONFIG_EXFAT_FS is not set > # CONFIG_NTFS_FS is not set > # end of DOS/FAT/EXFAT/NT Filesystems > > # > # Pseudo filesystems > # > CONFIG_PROC_FS=y > CONFIG_PROC_KCORE=y > CONFIG_PROC_SYSCTL=y > CONFIG_PROC_PAGE_MONITOR=y > # CONFIG_PROC_CHILDREN is not set > CONFIG_PROC_PID_ARCH_STATUS=y > CONFIG_PROC_CPU_RESCTRL=y > CONFIG_KERNFS=y > CONFIG_SYSFS=y > CONFIG_TMPFS=y > CONFIG_TMPFS_POSIX_ACL=y > CONFIG_TMPFS_XATTR=y > CONFIG_HUGETLBFS=y > CONFIG_HUGETLB_PAGE=y > CONFIG_MEMFD_CREATE=y > CONFIG_ARCH_HAS_GIGANTIC_PAGE=y > CONFIG_CONFIGFS_FS=y > CONFIG_EFIVAR_FS=y > # end of Pseudo filesystems > > CONFIG_MISC_FILESYSTEMS=y > # CONFIG_ORANGEFS_FS is not set > # CONFIG_ADFS_FS is not set > # CONFIG_AFFS_FS is not set > # CONFIG_ECRYPT_FS is not set > # CONFIG_HFS_FS is not set > # CONFIG_HFSPLUS_FS is not set > # CONFIG_BEFS_FS is not set > # CONFIG_BFS_FS is not set > # CONFIG_EFS_FS is not set > # CONFIG_CRAMFS is not set > # CONFIG_SQUASHFS is not set > # CONFIG_VXFS_FS is not set > # CONFIG_MINIX_FS is not set > # CONFIG_OMFS_FS is not set > # CONFIG_HPFS_FS is not set > # CONFIG_QNX4FS_FS is not set > # CONFIG_QNX6FS_FS is not set > # CONFIG_ROMFS_FS is not set > CONFIG_PSTORE=y > CONFIG_PSTORE_DEFLATE_COMPRESS=y > # CONFIG_PSTORE_LZO_COMPRESS is not set > # CONFIG_PSTORE_LZ4_COMPRESS is not set > # CONFIG_PSTORE_LZ4HC_COMPRESS is not set > # CONFIG_PSTORE_842_COMPRESS is not set > # CONFIG_PSTORE_ZSTD_COMPRESS is not set > CONFIG_PSTORE_COMPRESS=y > CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y > CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" > # CONFIG_PSTORE_CONSOLE is not set > # CONFIG_PSTORE_PMSG is not set > # CONFIG_PSTORE_FTRACE is not set > # CONFIG_PSTORE_RAM is not set > # CONFIG_SYSV_FS is not set > # CONFIG_UFS_FS is not set > # CONFIG_EROFS_FS is not set > CONFIG_NETWORK_FILESYSTEMS=y > CONFIG_NFS_FS=y > # CONFIG_NFS_V2 is not set > # CONFIG_NFS_V3 is not set > CONFIG_NFS_V4=y > # CONFIG_NFS_SWAP is not set > # CONFIG_NFS_V4_1 is not set > # CONFIG_NFS_FSCACHE is not set > # CONFIG_NFS_USE_LEGACY_DNS is not set > CONFIG_NFS_USE_KERNEL_DNS=y > CONFIG_NFS_DEBUG=y > CONFIG_NFS_DISABLE_UDP_SUPPORT=y > # CONFIG_NFSD is not set > CONFIG_GRACE_PERIOD=y > CONFIG_LOCKD=y > CONFIG_NFS_COMMON=y > CONFIG_SUNRPC=y > CONFIG_SUNRPC_GSS=y > CONFIG_SUNRPC_DEBUG=y > # CONFIG_CEPH_FS is not set > # CONFIG_CIFS is not set > # CONFIG_CODA_FS is not set > CONFIG_AFS_FS=y > CONFIG_AFS_DEBUG=y > CONFIG_AFS_FSCACHE=y > CONFIG_AFS_DEBUG_CURSOR=y > CONFIG_NLS=y > CONFIG_NLS_DEFAULT="iso8859-1" > # CONFIG_NLS_CODEPAGE_437 is not set > # CONFIG_NLS_CODEPAGE_737 is not set > # CONFIG_NLS_CODEPAGE_775 is not set > # CONFIG_NLS_CODEPAGE_850 is not set > # CONFIG_NLS_CODEPAGE_852 is not set > # CONFIG_NLS_CODEPAGE_855 is not set > # CONFIG_NLS_CODEPAGE_857 is not set > # CONFIG_NLS_CODEPAGE_860 is not set > # CONFIG_NLS_CODEPAGE_861 is not set > # CONFIG_NLS_CODEPAGE_862 is not set > # CONFIG_NLS_CODEPAGE_863 is not set > # CONFIG_NLS_CODEPAGE_864 is not set > # CONFIG_NLS_CODEPAGE_865 is not set > # CONFIG_NLS_CODEPAGE_866 is not set > # CONFIG_NLS_CODEPAGE_869 is not set > # CONFIG_NLS_CODEPAGE_936 is not set > # CONFIG_NLS_CODEPAGE_950 is not set > # CONFIG_NLS_CODEPAGE_932 is not set > # CONFIG_NLS_CODEPAGE_949 is not set > # CONFIG_NLS_CODEPAGE_874 is not set > # CONFIG_NLS_ISO8859_8 is not set > # CONFIG_NLS_CODEPAGE_1250 is not set > # CONFIG_NLS_CODEPAGE_1251 is not set > # CONFIG_NLS_ASCII is not set > # CONFIG_NLS_ISO8859_1 is not set > # CONFIG_NLS_ISO8859_2 is not set > # CONFIG_NLS_ISO8859_3 is not set > # CONFIG_NLS_ISO8859_4 is not set > # CONFIG_NLS_ISO8859_5 is not set > # CONFIG_NLS_ISO8859_6 is not set > # CONFIG_NLS_ISO8859_7 is not set > # CONFIG_NLS_ISO8859_9 is not set > # CONFIG_NLS_ISO8859_13 is not set > # CONFIG_NLS_ISO8859_14 is not set > # CONFIG_NLS_ISO8859_15 is not set > # CONFIG_NLS_KOI8_R is not set > # CONFIG_NLS_KOI8_U is not set > # CONFIG_NLS_MAC_ROMAN is not set > # CONFIG_NLS_MAC_CELTIC is not set > # CONFIG_NLS_MAC_CENTEURO is not set > # CONFIG_NLS_MAC_CROATIAN is not set > # CONFIG_NLS_MAC_CYRILLIC is not set > # CONFIG_NLS_MAC_GAELIC is not set > # CONFIG_NLS_MAC_GREEK is not set > # CONFIG_NLS_MAC_ICELAND is not set > # CONFIG_NLS_MAC_INUIT is not set > # CONFIG_NLS_MAC_ROMANIAN is not set > # CONFIG_NLS_MAC_TURKISH is not set > # CONFIG_NLS_UTF8 is not set > CONFIG_DLM=y > # CONFIG_DLM_DEBUG is not set > # CONFIG_UNICODE is not set > # end of File systems > > # > # Security options > # > CONFIG_KEYS=y > CONFIG_KEYS_REQUEST_CACHE=y > CONFIG_PERSISTENT_KEYRINGS=y > CONFIG_BIG_KEYS=y > CONFIG_TRUSTED_KEYS=y > CONFIG_ENCRYPTED_KEYS=y > CONFIG_KEY_DH_OPERATIONS=y > # CONFIG_SECURITY_DMESG_RESTRICT is not set > CONFIG_SECURITY=y > CONFIG_SECURITY_WRITABLE_HOOKS=y > CONFIG_SECURITYFS=y > CONFIG_SECURITY_NETWORK=y > CONFIG_PAGE_TABLE_ISOLATION=y > CONFIG_SECURITY_NETWORK_XFRM=y > CONFIG_SECURITY_PATH=y > # CONFIG_INTEL_TXT is not set > CONFIG_LSM_MMAP_MIN_ADDR=65536 > CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y > # CONFIG_HARDENED_USERCOPY is not set > # CONFIG_FORTIFY_SOURCE is not set > # CONFIG_STATIC_USERMODEHELPER is not set > CONFIG_SECURITY_SELINUX=y > CONFIG_SECURITY_SELINUX_BOOTPARAM=y > CONFIG_SECURITY_SELINUX_DISABLE=y > CONFIG_SECURITY_SELINUX_DEVELOP=y > CONFIG_SECURITY_SELINUX_AVC_STATS=y > CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 > CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 > CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 > # CONFIG_SECURITY_SMACK is not set > # CONFIG_SECURITY_TOMOYO is not set > # CONFIG_SECURITY_APPARMOR is not set > # CONFIG_SECURITY_LOADPIN is not set > CONFIG_SECURITY_YAMA=y > # CONFIG_SECURITY_SAFESETID is not set > # CONFIG_SECURITY_LOCKDOWN_LSM is not set > # CONFIG_INTEGRITY is not set > # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set > CONFIG_DEFAULT_SECURITY_SELINUX=y > # CONFIG_DEFAULT_SECURITY_DAC is not set > CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" > > # > # Kernel hardening options > # > > # > # Memory initialization > # > CONFIG_INIT_STACK_NONE=y > # CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set > # CONFIG_GCC_PLUGIN_STACKLEAK is not set > # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set > # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set > # end of Memory initialization > # end of Kernel hardening options > # end of Security options > > CONFIG_XOR_BLOCKS=y > CONFIG_CRYPTO=y > > # > # Crypto core or helper > # > # CONFIG_CRYPTO_FIPS is not set > CONFIG_CRYPTO_ALGAPI=y > CONFIG_CRYPTO_ALGAPI2=y > CONFIG_CRYPTO_AEAD=y > CONFIG_CRYPTO_AEAD2=y > CONFIG_CRYPTO_SKCIPHER=y > CONFIG_CRYPTO_SKCIPHER2=y > CONFIG_CRYPTO_HASH=y > CONFIG_CRYPTO_HASH2=y > CONFIG_CRYPTO_RNG=y > CONFIG_CRYPTO_RNG2=y > CONFIG_CRYPTO_RNG_DEFAULT=y > CONFIG_CRYPTO_AKCIPHER2=y > CONFIG_CRYPTO_AKCIPHER=y > CONFIG_CRYPTO_KPP2=y > CONFIG_CRYPTO_KPP=y > CONFIG_CRYPTO_ACOMP2=y > CONFIG_CRYPTO_MANAGER=y > CONFIG_CRYPTO_MANAGER2=y > # CONFIG_CRYPTO_USER is not set > # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set > # CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set > CONFIG_CRYPTO_GF128MUL=y > CONFIG_CRYPTO_NULL=y > CONFIG_CRYPTO_NULL2=y > # CONFIG_CRYPTO_PCRYPT is not set > # CONFIG_CRYPTO_CRYPTD is not set > CONFIG_CRYPTO_AUTHENC=y > # CONFIG_CRYPTO_TEST is not set > > # > # Public-key cryptography > # > CONFIG_CRYPTO_RSA=y > CONFIG_CRYPTO_DH=y > # CONFIG_CRYPTO_ECDH is not set > # CONFIG_CRYPTO_ECRDSA is not set > # CONFIG_CRYPTO_CURVE25519 is not set > # CONFIG_CRYPTO_CURVE25519_X86 is not set > > # > # Authenticated Encryption with Associated Data > # > CONFIG_CRYPTO_CCM=m > CONFIG_CRYPTO_GCM=y > # CONFIG_CRYPTO_CHACHA20POLY1305 is not set > # CONFIG_CRYPTO_AEGIS128 is not set > # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set > CONFIG_CRYPTO_SEQIV=y > CONFIG_CRYPTO_ECHAINIV=y > > # > # Block modes > # > CONFIG_CRYPTO_CBC=y > # CONFIG_CRYPTO_CFB is not set > CONFIG_CRYPTO_CTR=y > # CONFIG_CRYPTO_CTS is not set > CONFIG_CRYPTO_ECB=y > # CONFIG_CRYPTO_LRW is not set > # CONFIG_CRYPTO_OFB is not set > CONFIG_CRYPTO_PCBC=y > # CONFIG_CRYPTO_XTS is not set > # CONFIG_CRYPTO_KEYWRAP is not set > # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set > # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set > # CONFIG_CRYPTO_ADIANTUM is not set > # CONFIG_CRYPTO_ESSIV is not set > > # > # Hash modes > # > CONFIG_CRYPTO_CMAC=m > CONFIG_CRYPTO_HMAC=y > # CONFIG_CRYPTO_XCBC is not set > # CONFIG_CRYPTO_VMAC is not set > > # > # Digest > # > CONFIG_CRYPTO_CRC32C=y > # CONFIG_CRYPTO_CRC32C_INTEL is not set > CONFIG_CRYPTO_CRC32=m > # CONFIG_CRYPTO_CRC32_PCLMUL is not set > CONFIG_CRYPTO_XXHASH=y > CONFIG_CRYPTO_BLAKE2B=y > # CONFIG_CRYPTO_BLAKE2S is not set > # CONFIG_CRYPTO_BLAKE2S_X86 is not set > CONFIG_CRYPTO_CRCT10DIF=y > # CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set > CONFIG_CRYPTO_GHASH=y > # CONFIG_CRYPTO_POLY1305 is not set > # CONFIG_CRYPTO_POLY1305_X86_64 is not set > CONFIG_CRYPTO_MD4=m > CONFIG_CRYPTO_MD5=y > # CONFIG_CRYPTO_MICHAEL_MIC is not set > # CONFIG_CRYPTO_RMD128 is not set > # CONFIG_CRYPTO_RMD160 is not set > # CONFIG_CRYPTO_RMD256 is not set > # CONFIG_CRYPTO_RMD320 is not set > CONFIG_CRYPTO_SHA1=y > # CONFIG_CRYPTO_SHA1_SSSE3 is not set > # CONFIG_CRYPTO_SHA256_SSSE3 is not set > # CONFIG_CRYPTO_SHA512_SSSE3 is not set > CONFIG_CRYPTO_SHA256=y > CONFIG_CRYPTO_SHA512=m > # CONFIG_CRYPTO_SHA3 is not set > # CONFIG_CRYPTO_SM3 is not set > # CONFIG_CRYPTO_STREEBOG is not set > # CONFIG_CRYPTO_TGR192 is not set > # CONFIG_CRYPTO_WP512 is not set > # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set > > # > # Ciphers > # > CONFIG_CRYPTO_AES=y > # CONFIG_CRYPTO_AES_TI is not set > # CONFIG_CRYPTO_AES_NI_INTEL is not set > # CONFIG_CRYPTO_ANUBIS is not set > CONFIG_CRYPTO_ARC4=m > # CONFIG_CRYPTO_BLOWFISH is not set > # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set > # CONFIG_CRYPTO_CAMELLIA is not set > # CONFIG_CRYPTO_CAMELLIA_X86_64 is not set > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set > # CONFIG_CRYPTO_CAST5 is not set > # CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set > # CONFIG_CRYPTO_CAST6 is not set > # CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set > CONFIG_CRYPTO_DES=y > # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set > CONFIG_CRYPTO_FCRYPT=y > # CONFIG_CRYPTO_KHAZAD is not set > # CONFIG_CRYPTO_SALSA20 is not set > # CONFIG_CRYPTO_CHACHA20 is not set > # CONFIG_CRYPTO_CHACHA20_X86_64 is not set > # CONFIG_CRYPTO_SEED is not set > # CONFIG_CRYPTO_SERPENT is not set > # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set > # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set > # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set > # CONFIG_CRYPTO_SM4 is not set > # CONFIG_CRYPTO_TEA is not set > # CONFIG_CRYPTO_TWOFISH is not set > # CONFIG_CRYPTO_TWOFISH_X86_64 is not set > # CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set > # CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set > > # > # Compression > # > CONFIG_CRYPTO_DEFLATE=y > CONFIG_CRYPTO_LZO=m > # CONFIG_CRYPTO_842 is not set > # CONFIG_CRYPTO_LZ4 is not set > # CONFIG_CRYPTO_LZ4HC is not set > # CONFIG_CRYPTO_ZSTD is not set > > # > # Random Number Generation > # > # CONFIG_CRYPTO_ANSI_CPRNG is not set > CONFIG_CRYPTO_DRBG_MENU=y > CONFIG_CRYPTO_DRBG_HMAC=y > # CONFIG_CRYPTO_DRBG_HASH is not set > # CONFIG_CRYPTO_DRBG_CTR is not set > CONFIG_CRYPTO_DRBG=y > CONFIG_CRYPTO_JITTERENTROPY=y > CONFIG_CRYPTO_USER_API=y > CONFIG_CRYPTO_USER_API_HASH=y > # CONFIG_CRYPTO_USER_API_SKCIPHER is not set > # CONFIG_CRYPTO_USER_API_RNG is not set > # CONFIG_CRYPTO_USER_API_AEAD is not set > CONFIG_CRYPTO_HASH_INFO=y > > # > # Crypto library routines > # > CONFIG_CRYPTO_LIB_AES=y > CONFIG_CRYPTO_LIB_ARC4=m > # CONFIG_CRYPTO_LIB_BLAKE2S is not set > CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y > CONFIG_CRYPTO_LIB_CHACHA=y > # CONFIG_CRYPTO_LIB_CURVE25519 is not set > CONFIG_CRYPTO_LIB_DES=y > CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 > CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y > CONFIG_CRYPTO_LIB_POLY1305=y > CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y > CONFIG_CRYPTO_LIB_SHA256=y > # CONFIG_CRYPTO_HW is not set > CONFIG_ASYMMETRIC_KEY_TYPE=y > CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y > # CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set > CONFIG_X509_CERTIFICATE_PARSER=y > # CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set > CONFIG_PKCS7_MESSAGE_PARSER=y > CONFIG_PKCS7_TEST_KEY=y > CONFIG_SIGNED_PE_FILE_VERIFICATION=y > > # > # Certificates for signature checking > # > CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" > CONFIG_SYSTEM_TRUSTED_KEYRING=y > CONFIG_SYSTEM_TRUSTED_KEYS="" > CONFIG_SYSTEM_EXTRA_CERTIFICATE=y > CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 > CONFIG_SECONDARY_TRUSTED_KEYRING=y > CONFIG_SYSTEM_BLACKLIST_KEYRING=y > CONFIG_SYSTEM_BLACKLIST_HASH_LIST="/data/modsign/blacklist" > # end of Certificates for signature checking > > CONFIG_BINARY_PRINTF=y > > # > # Library routines > # > CONFIG_RAID6_PQ=y > CONFIG_RAID6_PQ_BENCHMARK=y > # CONFIG_PACKING is not set > CONFIG_BITREVERSE=y > CONFIG_GENERIC_STRNCPY_FROM_USER=y > CONFIG_GENERIC_STRNLEN_USER=y > CONFIG_GENERIC_NET_UTILS=y > CONFIG_GENERIC_FIND_FIRST_BIT=y > # CONFIG_CORDIC is not set > CONFIG_RATIONAL=y > CONFIG_GENERIC_PCI_IOMAP=y > CONFIG_GENERIC_IOMAP=y > CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y > CONFIG_ARCH_HAS_FAST_MULTIPLIER=y > CONFIG_CRC_CCITT=y > CONFIG_CRC16=y > CONFIG_CRC_T10DIF=y > CONFIG_CRC_ITU_T=y > CONFIG_CRC32=y > # CONFIG_CRC32_SELFTEST is not set > CONFIG_CRC32_SLICEBY8=y > # CONFIG_CRC32_SLICEBY4 is not set > # CONFIG_CRC32_SARWATE is not set > # CONFIG_CRC32_BIT is not set > # CONFIG_CRC64 is not set > # CONFIG_CRC4 is not set > # CONFIG_CRC7 is not set > CONFIG_LIBCRC32C=y > # CONFIG_CRC8 is not set > CONFIG_XXHASH=y > # CONFIG_RANDOM32_SELFTEST is not set > CONFIG_ZLIB_INFLATE=y > CONFIG_ZLIB_DEFLATE=y > CONFIG_LZO_COMPRESS=y > CONFIG_LZO_DECOMPRESS=y > CONFIG_ZSTD_COMPRESS=y > CONFIG_ZSTD_DECOMPRESS=y > CONFIG_XZ_DEC=y > CONFIG_XZ_DEC_X86=y > # CONFIG_XZ_DEC_POWERPC is not set > # CONFIG_XZ_DEC_IA64 is not set > # CONFIG_XZ_DEC_ARM is not set > # CONFIG_XZ_DEC_ARMTHUMB is not set > # CONFIG_XZ_DEC_SPARC is not set > CONFIG_XZ_DEC_BCJ=y > # CONFIG_XZ_DEC_TEST is not set > CONFIG_DECOMPRESS_GZIP=y > CONFIG_GENERIC_ALLOCATOR=y > CONFIG_INTERVAL_TREE=y > CONFIG_ASSOCIATIVE_ARRAY=y > CONFIG_HAS_IOMEM=y > CONFIG_HAS_IOPORT_MAP=y > CONFIG_HAS_DMA=y > CONFIG_NEED_SG_DMA_LENGTH=y > CONFIG_NEED_DMA_MAP_STATE=y > CONFIG_ARCH_DMA_ADDR_T_64BIT=y > CONFIG_SWIOTLB=y > # CONFIG_DMA_API_DEBUG is not set > CONFIG_SGL_ALLOC=y > CONFIG_IOMMU_HELPER=y > CONFIG_CHECK_SIGNATURE=y > CONFIG_CPU_RMAP=y > CONFIG_DQL=y > CONFIG_GLOB=y > # CONFIG_GLOB_SELFTEST is not set > CONFIG_NLATTR=y > CONFIG_CLZ_TAB=y > # CONFIG_IRQ_POLL is not set > CONFIG_MPILIB=y > CONFIG_OID_REGISTRY=y > CONFIG_UCS2_STRING=y > CONFIG_HAVE_GENERIC_VDSO=y > CONFIG_GENERIC_GETTIMEOFDAY=y > CONFIG_GENERIC_VDSO_TIME_NS=y > CONFIG_FONT_SUPPORT=y > CONFIG_FONT_8x16=y > CONFIG_FONT_AUTOSELECT=y > CONFIG_SG_POOL=y > CONFIG_ARCH_HAS_PMEM_API=y > CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y > CONFIG_ARCH_HAS_UACCESS_MCSAFE=y > CONFIG_ARCH_STACKWALK=y > CONFIG_SBITMAP=y > # CONFIG_STRING_SELFTEST is not set > # end of Library routines > > # > # Kernel hacking > # > > # > # printk and dmesg options > # > # CONFIG_PRINTK_TIME is not set > # CONFIG_PRINTK_CALLER is not set > CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 > CONFIG_CONSOLE_LOGLEVEL_QUIET=4 > CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 > # CONFIG_BOOT_PRINTK_DELAY is not set > # CONFIG_DYNAMIC_DEBUG is not set > CONFIG_SYMBOLIC_ERRNAME=y > CONFIG_DEBUG_BUGVERBOSE=y > # end of printk and dmesg options > > # > # Compile-time checks and compiler options > # > CONFIG_DEBUG_INFO=y > # CONFIG_DEBUG_INFO_REDUCED is not set > # CONFIG_DEBUG_INFO_SPLIT is not set > # CONFIG_DEBUG_INFO_DWARF4 is not set > # CONFIG_DEBUG_INFO_BTF is not set > # CONFIG_GDB_SCRIPTS is not set > # CONFIG_ENABLE_MUST_CHECK is not set > CONFIG_FRAME_WARN=2048 > # CONFIG_STRIP_ASM_SYMS is not set > # CONFIG_READABLE_ASM is not set > CONFIG_HEADERS_INSTALL=y > CONFIG_DEBUG_SECTION_MISMATCH=y > CONFIG_SECTION_MISMATCH_WARN_ONLY=y > CONFIG_STACK_VALIDATION=y > # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set > # end of Compile-time checks and compiler options > > # > # Generic Kernel Debugging Instruments > # > CONFIG_MAGIC_SYSRQ=y > CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 > CONFIG_MAGIC_SYSRQ_SERIAL=y > CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" > CONFIG_DEBUG_FS=y > CONFIG_HAVE_ARCH_KGDB=y > # CONFIG_KGDB is not set > CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y > # CONFIG_UBSAN is not set > # end of Generic Kernel Debugging Instruments > > CONFIG_DEBUG_KERNEL=y > CONFIG_DEBUG_MISC=y > > # > # Memory Debugging > # > # CONFIG_PAGE_EXTENSION is not set > # CONFIG_DEBUG_PAGEALLOC is not set > # CONFIG_PAGE_OWNER is not set > # CONFIG_PAGE_POISONING is not set > # CONFIG_DEBUG_PAGE_REF is not set > # CONFIG_DEBUG_RODATA_TEST is not set > CONFIG_GENERIC_PTDUMP=y > # CONFIG_PTDUMP_DEBUGFS is not set > # CONFIG_DEBUG_OBJECTS is not set > # CONFIG_DEBUG_SLAB is not set > CONFIG_HAVE_DEBUG_KMEMLEAK=y > # CONFIG_DEBUG_KMEMLEAK is not set > # CONFIG_DEBUG_STACK_USAGE is not set > # CONFIG_SCHED_STACK_END_CHECK is not set > # CONFIG_DEBUG_VM is not set > CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y > # CONFIG_DEBUG_VIRTUAL is not set > # CONFIG_DEBUG_MEMORY_INIT is not set > # CONFIG_DEBUG_PER_CPU_MAPS is not set > CONFIG_HAVE_ARCH_KASAN=y > CONFIG_HAVE_ARCH_KASAN_VMALLOC=y > CONFIG_CC_HAS_KASAN_GENERIC=y > # CONFIG_KASAN is not set > CONFIG_KASAN_STACK=1 > # end of Memory Debugging > > # CONFIG_DEBUG_SHIRQ is not set > > # > # Debug Oops, Lockups and Hangs > # > # CONFIG_PANIC_ON_OOPS is not set > CONFIG_PANIC_ON_OOPS_VALUE=0 > CONFIG_PANIC_TIMEOUT=0 > CONFIG_LOCKUP_DETECTOR=y > CONFIG_SOFTLOCKUP_DETECTOR=y > # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set > CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 > CONFIG_HARDLOCKUP_DETECTOR_PERF=y > CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y > CONFIG_HARDLOCKUP_DETECTOR=y > # CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set > CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 > CONFIG_DETECT_HUNG_TASK=y > CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 > # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set > CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 > CONFIG_WQ_WATCHDOG=y > # CONFIG_TEST_LOCKUP is not set > # end of Debug Oops, Lockups and Hangs > > # > # Scheduler Debugging > # > # CONFIG_SCHED_DEBUG is not set > CONFIG_SCHED_INFO=y > # CONFIG_SCHEDSTATS is not set > # end of Scheduler Debugging > > # CONFIG_DEBUG_TIMEKEEPING is not set > > # > # Lock Debugging (spinlocks, mutexes, etc...) > # > CONFIG_LOCK_DEBUGGING_SUPPORT=y > # CONFIG_PROVE_LOCKING is not set > # CONFIG_LOCK_STAT is not set > CONFIG_DEBUG_RT_MUTEXES=y > CONFIG_DEBUG_SPINLOCK=y > CONFIG_DEBUG_MUTEXES=y > # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set > # CONFIG_DEBUG_RWSEMS is not set > # CONFIG_DEBUG_LOCK_ALLOC is not set > # CONFIG_DEBUG_ATOMIC_SLEEP is not set > # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set > # CONFIG_LOCK_TORTURE_TEST is not set > # CONFIG_WW_MUTEX_SELFTEST is not set > # end of Lock Debugging (spinlocks, mutexes, etc...) > > CONFIG_STACKTRACE=y > # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set > # CONFIG_DEBUG_KOBJECT is not set > > # > # Debug kernel data structures > # > # CONFIG_DEBUG_LIST is not set > # CONFIG_DEBUG_PLIST is not set > # CONFIG_DEBUG_SG is not set > # CONFIG_DEBUG_NOTIFIERS is not set > # CONFIG_BUG_ON_DATA_CORRUPTION is not set > # end of Debug kernel data structures > > # CONFIG_DEBUG_CREDENTIALS is not set > > # > # RCU Debugging > # > # CONFIG_RCU_PERF_TEST is not set > # CONFIG_RCU_TORTURE_TEST is not set > CONFIG_RCU_CPU_STALL_TIMEOUT=60 > # CONFIG_RCU_TRACE is not set > # CONFIG_RCU_EQS_DEBUG is not set > # end of RCU Debugging > > # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set > # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set > # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set > # CONFIG_LATENCYTOP is not set > CONFIG_USER_STACKTRACE_SUPPORT=y > CONFIG_NOP_TRACER=y > CONFIG_HAVE_FUNCTION_TRACER=y > CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y > CONFIG_HAVE_DYNAMIC_FTRACE=y > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y > CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y > CONFIG_HAVE_SYSCALL_TRACEPOINTS=y > CONFIG_HAVE_FENTRY=y > CONFIG_HAVE_C_RECORDMCOUNT=y > CONFIG_TRACE_CLOCK=y > CONFIG_RING_BUFFER=y > CONFIG_EVENT_TRACING=y > CONFIG_CONTEXT_SWITCH_TRACER=y > CONFIG_TRACING=y > CONFIG_GENERIC_TRACER=y > CONFIG_TRACING_SUPPORT=y > CONFIG_FTRACE=y > # CONFIG_BOOTTIME_TRACING is not set > CONFIG_FUNCTION_TRACER=y > CONFIG_FUNCTION_GRAPH_TRACER=y > CONFIG_DYNAMIC_FTRACE=y > CONFIG_DYNAMIC_FTRACE_WITH_REGS=y > CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y > # CONFIG_FUNCTION_PROFILER is not set > # CONFIG_STACK_TRACER is not set > # CONFIG_PREEMPTIRQ_EVENTS is not set > # CONFIG_IRQSOFF_TRACER is not set > # CONFIG_SCHED_TRACER is not set > # CONFIG_HWLAT_TRACER is not set > # CONFIG_MMIOTRACE is not set > CONFIG_FTRACE_SYSCALLS=y > # CONFIG_TRACER_SNAPSHOT is not set > CONFIG_BRANCH_PROFILE_NONE=y > # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set > # CONFIG_PROFILE_ALL_BRANCHES is not set > # CONFIG_BLK_DEV_IO_TRACE is not set > CONFIG_KPROBE_EVENTS=y > # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set > # CONFIG_UPROBE_EVENTS is not set > CONFIG_BPF_EVENTS=y > CONFIG_DYNAMIC_EVENTS=y > CONFIG_PROBE_EVENTS=y > # CONFIG_BPF_KPROBE_OVERRIDE is not set > CONFIG_FTRACE_MCOUNT_RECORD=y > # CONFIG_HIST_TRIGGERS is not set > # CONFIG_TRACE_EVENT_INJECT is not set > # CONFIG_TRACEPOINT_BENCHMARK is not set > # CONFIG_RING_BUFFER_BENCHMARK is not set > # CONFIG_TRACE_EVAL_MAP_FILE is not set > # CONFIG_FTRACE_STARTUP_TEST is not set > # CONFIG_RING_BUFFER_STARTUP_TEST is not set > # CONFIG_PREEMPTIRQ_DELAY_TEST is not set > # CONFIG_KPROBE_EVENT_GEN_TEST is not set > # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set > CONFIG_SAMPLES=y > # CONFIG_SAMPLE_TRACE_EVENTS is not set > # CONFIG_SAMPLE_TRACE_PRINTK is not set > # CONFIG_SAMPLE_FTRACE_DIRECT is not set > # CONFIG_SAMPLE_TRACE_ARRAY is not set > # CONFIG_SAMPLE_KOBJECT is not set > # CONFIG_SAMPLE_KPROBES is not set > # CONFIG_SAMPLE_HW_BREAKPOINT is not set > # CONFIG_SAMPLE_KFIFO is not set > # CONFIG_SAMPLE_LIVEPATCH is not set > # CONFIG_SAMPLE_CONFIGFS is not set > # CONFIG_SAMPLE_HIDRAW is not set > # CONFIG_SAMPLE_PIDFD is not set > # CONFIG_SAMPLE_SECCOMP is not set > # CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set > CONFIG_SAMPLE_VFS=y > # CONFIG_SAMPLE_INTEL_MEI is not set > CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y > > # > # x86 Debugging > # > CONFIG_TRACE_IRQFLAGS_SUPPORT=y > CONFIG_X86_VERBOSE_BOOTUP=y > CONFIG_EARLY_PRINTK=y > # CONFIG_EARLY_PRINTK_DBGP is not set > # CONFIG_EARLY_PRINTK_USB_XDBC is not set > # CONFIG_EFI_PGT_DUMP is not set > # CONFIG_DEBUG_WX is not set > CONFIG_DOUBLEFAULT=y > # CONFIG_DEBUG_TLBFLUSH is not set > # CONFIG_IOMMU_DEBUG is not set > CONFIG_HAVE_MMIOTRACE_SUPPORT=y > # CONFIG_X86_DECODER_SELFTEST is not set > CONFIG_IO_DELAY_0X80=y > # CONFIG_IO_DELAY_0XED is not set > # CONFIG_IO_DELAY_UDELAY is not set > # CONFIG_IO_DELAY_NONE is not set > # CONFIG_DEBUG_BOOT_PARAMS is not set > # CONFIG_CPA_DEBUG is not set > # CONFIG_DEBUG_ENTRY is not set > # CONFIG_DEBUG_NMI_SELFTEST is not set > # CONFIG_X86_DEBUG_FPU is not set > # CONFIG_PUNIT_ATOM_DEBUG is not set > CONFIG_UNWINDER_ORC=y > # CONFIG_UNWINDER_FRAME_POINTER is not set > # CONFIG_UNWINDER_GUESS is not set > # end of x86 Debugging > > # > # Kernel Testing and Coverage > # > # CONFIG_KUNIT is not set > # CONFIG_NOTIFIER_ERROR_INJECTION is not set > CONFIG_FUNCTION_ERROR_INJECTION=y > # CONFIG_FAULT_INJECTION is not set > CONFIG_ARCH_HAS_KCOV=y > CONFIG_CC_HAS_SANCOV_TRACE_PC=y > # CONFIG_KCOV is not set > # CONFIG_RUNTIME_TESTING_MENU is not set > # CONFIG_MEMTEST is not set > # end of Kernel Testing and Coverage > # end of Kernel hacking -- Jani Nikula, Intel Open Source Graphics Center From patchwork at emeril.freedesktop.org Mon Jun 8 07:56:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 07:56:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_Avoid_PSR_and_FBC_features_concurently=2E?= In-Reply-To: <20200608065635.11652-1-jason.v.le@intel.com> References: <20200608065635.11652-1-jason.v.le@intel.com> Message-ID: <159160299313.14461.3561681849537142533@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Avoid PSR and FBC features concurently. URL : https://patchwork.freedesktop.org/series/78107/ State : success == Summary == CI Bug Log - changes from CI_DRM_8599 -> Patchwork_17904 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/index.html Known issues ------------ Here are the changes found in Patchwork_17904 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-byt-n2820/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-kbl-x1275/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 41) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8599 -> Patchwork_17904 CI-20190529: 20190529 CI_DRM_8599: 41ca9ea98b74c926c923e84931b9b4a4c3955e08 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5697: 5b8be04285ded1201fac5a2c2b50a7d70fa332d8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17904: dee7c897c6ed8262b5655c110352e85c7e13e8c1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == dee7c897c6ed drm/i915/display: Avoid PSR and FBC features concurently. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/index.html From jani.nikula at linux.intel.com Mon Jun 8 08:21:14 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Mon, 08 Jun 2020 11:21:14 +0300 Subject: [Intel-gfx] [PATCH] Revert "drm/i915: Remove unneeded hack now for CDCLK" In-Reply-To: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> References: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> Message-ID: <87img2x91h.fsf@intel.com> On Mon, 08 Jun 2020, Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> wrote: > This reverts commit 82ea174dc5425d4e85e25d0c4ba961a2e494392a. > Please explain why. What's going on, why we need the revert. It's fine to reply here, the commit message can be amended by whoever applies the patch. BR, Jani. > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs") > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 08468b121d02..45f7f33d1144 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2071,6 +2071,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > /* Account for additional needs from the planes */ > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); > > + /* > + * HACK. Currently for TGL platforms we calculate > + * min_cdclk initially based on pixel_rate divided > + * by 2, accounting for also plane requirements, > + * however in some cases the lowest possible CDCLK > + * doesn't work and causing the underruns. > + * Explicitly stating here that this seems to be currently > + * rather a Hack, than final solution. > + */ > + if (IS_TIGERLAKE(dev_priv)) > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > + > if (min_cdclk > dev_priv->max_cdclk_freq) { > drm_dbg_kms(&dev_priv->drm, > "required cdclk (%d kHz) exceeds max (%d kHz)\n", -- Jani Nikula, Intel Open Source Graphics Center From patchwork at emeril.freedesktop.org Mon Jun 8 08:30:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 08:30:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgUmV2?= =?utf-8?q?ert_=22drm/i915=3A_Remove_unneeded_hack_now_for_CDCLK=22?= In-Reply-To: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> References: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> Message-ID: <159160503780.14463.4040658759822327212@emeril.freedesktop.org> == Series Details == Series: Revert "drm/i915: Remove unneeded hack now for CDCLK" URL : https://patchwork.freedesktop.org/series/78106/ State : success == Summary == CI Bug Log - changes from CI_DRM_8599_full -> Patchwork_17903_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17903_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl8/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl7/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl3/igt at gem_exec_suspend@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-kbl1/igt at gem_exec_suspend@basic-s3.html * igt at gem_exec_whisper@basic-contexts-priority: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk1/igt at gem_exec_whisper@basic-contexts-priority.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-glk7/igt at gem_exec_whisper@basic-contexts-priority.html * igt at gem_mmap_offset@basic-uaf: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#95]) +19 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl2/igt at gem_mmap_offset@basic-uaf.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl1/igt at gem_mmap_offset@basic-uaf.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl8/igt at i915_suspend@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl4/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl3/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk7/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +9 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#699]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl8/igt at kms_flip_tiling@flip-changes-tiling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl2/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-glk8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109642] / [fdo#111068]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb2/igt at kms_psr2_su@page_flip.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-iclb6/igt at kms_psr2_su@page_flip.html * igt at kms_vblank@pipe-a-query-forked-busy: - shard-snb: [PASS][29] -> [SKIP][30] ([fdo#109271]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-snb5/igt at kms_vblank@pipe-a-query-forked-busy.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-snb2/igt at kms_vblank@pipe-a-query-forked-busy.html * igt at vgem_basic@create: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#402]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-tglb2/igt at vgem_basic@create.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-tglb7/igt at vgem_basic@create.html #### Possible fixes #### * igt at gem_exec_schedule@smoketest-all: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk1/igt at gem_exec_schedule@smoketest-all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-glk7/igt at gem_exec_schedule@smoketest-all.html * igt at gem_pread@display: - shard-hsw: [INCOMPLETE][35] ([i915#61]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-hsw4/igt at gem_pread@display.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-hsw1/igt at gem_pread@display.html * igt at gen9_exec_parse@allowed-all: - shard-glk: [DMESG-WARN][37] ([i915#1436] / [i915#716]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk8/igt at gen9_exec_parse@allowed-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-glk7/igt at gen9_exec_parse@allowed-all.html * igt at i915_pm_rpm@modeset-lpsp-stress: - shard-skl: [DMESG-WARN][39] -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at i915_pm_rpm@modeset-lpsp-stress.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl7/igt at i915_pm_rpm@modeset-lpsp-stress.html * igt at kms_atomic@test-only: - shard-apl: [DMESG-WARN][41] ([i915#95]) -> [PASS][42] +23 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl1/igt at kms_atomic@test-only.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl3/igt at kms_atomic@test-only.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl2/igt at kms_big_fb@linear-64bpp-rotate-180.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +9 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl10/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl9/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [FAIL][47] ([i915#57]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-hsw1/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-tglb: [DMESG-WARN][49] ([i915#402]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-tglb1/igt at kms_dp_dsc@basic-dsc-enable-edp.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-tglb5/igt at kms_dp_dsc@basic-dsc-enable-edp.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +4 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +3 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render: - shard-glk: [INCOMPLETE][55] ([i915#58] / [k.org#198133]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-glk9/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-tglb3/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-iclb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [DMESG-WARN][63] ([i915#180] / [i915#95]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb7/igt at kms_psr@psr2_suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_vblank@pipe-c-wait-idle: - shard-kbl: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl3/igt at kms_vblank@pipe-c-wait-idle.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-kbl1/igt at kms_vblank@pipe-c-wait-idle.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb1/igt at perf@blocking-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-iclb6/igt at perf@blocking-parameterized.html * {igt at sysfs_preempt_timeout@idempotent at vecs0}: - shard-kbl: [DMESG-WARN][73] ([i915#93] / [i915#95]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl4/igt at sysfs_preempt_timeout@idempotent at vecs0.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-kbl3/igt at sysfs_preempt_timeout@idempotent at vecs0.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][75] ([i915#658]) -> [SKIP][76] ([i915#588]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb7/igt at i915_pm_dc@dc3co-vpb-simulation.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][77] ([i915#1319]) -> [TIMEOUT][78] ([i915#1319] / [i915#1958]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl6/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-kbl4/igt at kms_content_protection@atomic.html - shard-apl: [FAIL][79] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl2/igt at kms_content_protection@atomic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-apl1/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][81] ([i915#1319] / [i915#1958]) -> [TIMEOUT][82] ([i915#1319]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl4/igt at kms_content_protection@atomic-dpms.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/shard-kbl3/igt at kms_content_protection@atomic-dpms.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8599 -> Patchwork_17903 CI-20190529: 20190529 CI_DRM_8599: 41ca9ea98b74c926c923e84931b9b4a4c3955e08 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5697: 5b8be04285ded1201fac5a2c2b50a7d70fa332d8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17903: c2441c67163365c1e27cf62805b377392b66feb6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17903/index.html From stanislav.lisovskiy at intel.com Mon Jun 8 08:35:40 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Mon, 8 Jun 2020 11:35:40 +0300 Subject: [Intel-gfx] [PATCH] Revert "drm/i915: Remove unneeded hack now for CDCLK" In-Reply-To: <87img2x91h.fsf@intel.com> References: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> <87img2x91h.fsf@intel.com> Message-ID: <20200608083540.GA22223@intel.com> On Mon, Jun 08, 2020 at 11:21:14AM +0300, Jani Nikula wrote: > On Mon, 08 Jun 2020, Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> wrote: > > This reverts commit 82ea174dc5425d4e85e25d0c4ba961a2e494392a. > > > > Please explain why. What's going on, why we need the revert. > > It's fine to reply here, the commit message can be amended by whoever > applies the patch. Yes, Unfortunately according to our recent findings there is still some unidentified factor, requiring CDCLK to be set higher - otherwise we still get underruns on some multipipe configurations, despite CDCLK being set according to BSpec formula. So getting again back into debug mode to indentify the cause, meanwhile setting CDCLK=Pixel rate back in order to remove regression in 10% of the cases due to FIFO underruns. Stan > > BR, > Jani. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs") > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index 08468b121d02..45f7f33d1144 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -2071,6 +2071,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > > /* Account for additional needs from the planes */ > > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); > > > > + /* > > + * HACK. Currently for TGL platforms we calculate > > + * min_cdclk initially based on pixel_rate divided > > + * by 2, accounting for also plane requirements, > > + * however in some cases the lowest possible CDCLK > > + * doesn't work and causing the underruns. > > + * Explicitly stating here that this seems to be currently > > + * rather a Hack, than final solution. > > + */ > > + if (IS_TIGERLAKE(dev_priv)) > > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > > + > > if (min_cdclk > dev_priv->max_cdclk_freq) { > > drm_dbg_kms(&dev_priv->drm, > > "required cdclk (%d kHz) exceeds max (%d kHz)\n", > > -- > Jani Nikula, Intel Open Source Graphics Center From jani.saarinen at intel.com Mon Jun 8 08:44:42 2020 From: jani.saarinen at intel.com (Saarinen, Jani) Date: Mon, 8 Jun 2020 08:44:42 +0000 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver In-Reply-To: <87o8puxak1.fsf@intel.com> References: <2136072.1591491984@warthog.procyon.org.uk> <87o8puxak1.fsf@intel.com> Message-ID: <4ff2445aff8d44c5961a6d194a8f4663@intel.com> HI, > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Jani Nikula > Sent: maanantai 8. kes?kuuta 2020 10.49 > To: David Howells <dhowells at redhat.com>; Joonas Lahtinen > <joonas.lahtinen at linux.intel.com>; Vivi, Rodrigo <rodrigo.vivi at intel.com> > Cc: intel-gfx at lists.freedesktop.org; linux-kernel at vger.kernel.org; dri- > devel at lists.freedesktop.org; dhowells at redhat.com; airlied at redhat.com > Subject: Re: [Intel-gfx] A panic and a hang in the i915 drm driver > > On Sun, 07 Jun 2020, David Howells <dhowells at redhat.com> wrote: > > Hi, > > > > I'm seeing the attached oops and panic from the i915 drm driver. I've tried > > bisecting it, but there's a problem in that one of the merged branches causes > > the machine to hang without output. It was not this one? https://gitlab.freedesktop.org/drm/intel/-/issues/1892 > > Cc: Ville and GG, I thought this was fixed (reverted) already. > > BR, > Jani. > > > > > > The oops for commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 looks like: > > > > BUG: kernel NULL pointer dereference, address: 0000000000000000 > > #PF: supervisor read access in kernel mode > > #PF: error_code(0x0000) - not-present page > > PGD 0 P4D 0 > > Oops: 0000 [#1] SMP PTI > > CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.7.0-rc2-fscache+ #883 > > Hardware name: ASUS All Series/H97-PLUS, BIOS 2306 10/09/2014 > > RIP: 0010:intel_psr_enabled+0xb/0x6e > > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d > 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 > 00 20 75 05 45 31 e4 eb 44 80 > > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 > > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 > > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 > > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 > > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 > > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 > > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) > knlGS:0000000000000000 > > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 > > Call Trace: > > intel_read_dp_sdp+0x71/0x2c5 > > hsw_crt_get_config+0x18/0x41 > > intel_modeset_readout_hw_state+0x24d/0x662 > > ? do_raw_spin_lock+0x8b/0xcd > > ? _raw_spin_lock_irqsave+0x10/0x16 > > intel_modeset_setup_hw_state+0xa8/0xb59 > > ? __next_node_in+0x39/0x42 > > ? ww_mutex_lock+0x3d/0x1da > > ? modeset_lock+0xd4/0x114 > > ? drm_modeset_lock_all_ctx+0x86/0xcc > > intel_modeset_init+0x285/0x5bf > > ? intel_irq_postinstall+0x485/0x4d1 > > i915_driver_probe+0x1b4/0x49c > > ? __kernfs_new_node+0x161/0x1b2 > > ? rpm_resume+0x45e/0x485 > > i915_pci_probe+0xfd/0x11d > > ? __pm_runtime_resume+0x51/0x5e > > local_pci_probe+0x39/0x7a > > pci_device_probe+0xf5/0x14f > > ? sysfs_do_create_link_sd.isra.0+0x77/0xa3 > > really_probe+0x140/0x2a9 > > driver_probe_device+0x9c/0xd1 > > device_driver_attach+0x3c/0x55 > > __driver_attach+0x97/0x9f > > ? device_driver_attach+0x55/0x55 > > bus_for_each_dev+0x72/0xa8 > > bus_add_driver+0x108/0x1b9 > > driver_register+0x9e/0xd7 > > ? mipi_dsi_bus_init+0x11/0x11 > > i915_init+0x58/0x6b > > do_one_initcall+0x83/0x18a > > kernel_init_freeable+0x19b/0x1fd > > ? rest_init+0x9f/0x9f > > kernel_init+0xa/0xfa > > ret_from_fork+0x1f/0x30 > > Modules linked in: > > CR2: 0000000000000000 > > ---[ end trace d0c4f561618aeb37 ]--- > > RIP: 0010:intel_psr_enabled+0xb/0x6e > > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d > 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 > 00 20 75 05 45 31 e4 eb 44 80 > > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 > > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 > > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 > > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 > > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 > > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 > > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) > knlGS:0000000000000000 > > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 > > Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 > > Kernel Offset: disabled > > ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 ]--- > > > > > > Decoding the RIP gives: > > > > RIP: 0010:intel_psr_enabled (/data/fs/linux- > fs/build3/../drivers/gpu/drm/i915/display/intel_display_types.h:1595 /data/fs/linux- > fs/build3/../drivers/gpu/drm/i915/display/intel_psr.c:1598) > > > > > > > > Commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 ("Merge tag > > 'drm-intel-next-fixes-2020-05-20' of > > git://anongit.freedesktop.org/drm/drm-intel into drm-next") is definitely bad > > and logs an oops to the console and panics, but it's a merge. > > > > On one side is e20bb857dea2f620ff37ae541ed8aee70e3c89f1 ("Merge tag > > 'exynos-drm-next-for-v5.8' of > > git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into > > drm-next"), which hangs. This is also a merge. > > > > One side of e20bb is f84e1ba336a4f47ae251e4d2d8a694902571b0df > > ("drm/exynos-vidi: convert platform driver to use dev_groups") which is good. > > > > The other side of c4121 and e20bb derive from the same line of commits, with > > three patches between. All of these, down to at least > > 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 ("drm/i915: Update DRIVER_DATE > to > > 20200430") cause the machine to hang without any sort of console output. > > > > Commit bfbe1744e4417986419236719922a9a7fda224d1 ("Merge tag > > 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux > > into drm-next") is good. > > > > Commit 47e51832ae93534d872511ba557115722582d94c > > ("drm/i915/gvt: use context lrc_reg_state for shadow ppgtt override") is good. > > > > I've attached the git log and the config file. > > > > David > > > > git bisect start > > # bad: [ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d] afs: Fix file locking > > git bisect bad ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d > > # good: [3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162] Linux 5.7 > > git bisect good 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162 > > # bad: [2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63] Merge branch > 'uaccess.comedi' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs > > git bisect bad 2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63 > > # good: [cfa3b8068b09f25037146bfd5eed041b78878bee] Merge tag 'for-linus- > hmm' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma > > git bisect good cfa3b8068b09f25037146bfd5eed041b78878bee > > # bad: [c41219fda6e04255c44d37fd2c0d898c1c46abf1] Merge tag 'drm-intel-next- > fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next > > git bisect bad c41219fda6e04255c44d37fd2c0d898c1c46abf1 > > # good: [937eea297e26effac6809a0bf8c20e6ca9d90b9a] Merge tag 'amd-drm- > next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-next > > git bisect good 937eea297e26effac6809a0bf8c20e6ca9d90b9a > > # good: [a1fb548962397bb8609bb46e566809a9a1b30044] Merge tag 'drm-intel- > next-2020-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next > > git bisect good a1fb548962397bb8609bb46e566809a9a1b30044 > > # good: [f84e1ba336a4f47ae251e4d2d8a694902571b0df] drm/exynos-vidi: > convert platform driver to use dev_groups > > git bisect good f84e1ba336a4f47ae251e4d2d8a694902571b0df > > # skip: [d9162348db12487754e61f73497bdcfcea753590] drm/i915: Introduce > skl_plane_wm_level accessor. > > git bisect skip d9162348db12487754e61f73497bdcfcea753590 > > # skip: [84eac0c65940d9633247b0c8c826d4bcb7307351] drm/i915/gt: Force pte > cacheline to main memory > > git bisect skip 84eac0c65940d9633247b0c8c826d4bcb7307351 > > # skip: [802a5820fc0c0f12b40280db3dbaaf8359b07243] drm/i915: Extract > i915_cs_timestamp_{ns_to_ticks,tick_to_ns}() > > git bisect skip 802a5820fc0c0f12b40280db3dbaaf8359b07243 > > # skip: [1c8ee8b92fb6ac9d5975147cc902e8c142eca338] drm/i915/gt: Restore > Cherryview back to full-ppgtt > > git bisect skip 1c8ee8b92fb6ac9d5975147cc902e8c142eca338 > > # skip: [2e2701582a8039b2f8a2fa811237ac8ec98355fa] drm/i915: Nuke pointless > div by 64bit > > git bisect skip 2e2701582a8039b2f8a2fa811237ac8ec98355fa > > # skip: [4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc] drm/i915/gt: Suspend > tasklets before resume sanitization > > git bisect skip 4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc > > # skip: [20f505f2253106f695ba6fa0a415159145a8fb2a] drm/i915: Restrict qgv > points which don't have enough bandwidth. > > git bisect skip 20f505f2253106f695ba6fa0a415159145a8fb2a > > # skip: [d8d5afe35e3f88f73436f79f974d96a67e879637] drm/i915: Make > active_pipes check skl specific > > git bisect skip d8d5afe35e3f88f73436f79f974d96a67e879637 > > # skip: [1be8f347d70b5027b7b223c665756d85feaf36b6] Merge tag 'gvt-next- > 2020-05-12' of https://github.com/intel/gvt-linux into drm-intel-next-queued > > git bisect skip 1be8f347d70b5027b7b223c665756d85feaf36b6 > > # skip: [b428d57006663d18e3f6f98644ff9e8702a33ca4] drm/i915/gt: Reset > execlists registers before HWSP > > git bisect skip b428d57006663d18e3f6f98644ff9e8702a33ca4 > > # skip: [6b6cd2ebd8d071e55998e32b648bb8081f7f02bb] drm/i915: Mark > concurrent submissions with a weak-dependency > > git bisect skip 6b6cd2ebd8d071e55998e32b648bb8081f7f02bb > > # skip: [1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0] drm/i915: Extract skl SAGV > checking > > git bisect skip 1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0 > > # skip: [cafac5a983619944afa639c53f0d5d885616a3d2] drm/i915/dp: Add > compute routine for DP PSR VSC SDP > > git bisect skip cafac5a983619944afa639c53f0d5d885616a3d2 > > # skip: [61b088c5374a9f886efa1edbb49ce552bd1f9cba] drm/i915/ehl: Restrict > w/a 1607087056 for EHL/JSL > > git bisect skip 61b088c5374a9f886efa1edbb49ce552bd1f9cba > > # skip: [2045d666ae634f1676660acfb864bcba0e9f86ca] drm/i915: Ignore submit- > fences on the same timeline > > git bisect skip 2045d666ae634f1676660acfb864bcba0e9f86ca > > # skip: [16e87459673a5cbef35cc0f2e15c664b10a4cdb6] drm/i915/gt: Move the > batch buffer pool from the engine to the gt > > git bisect skip 16e87459673a5cbef35cc0f2e15c664b10a4cdb6 > > # skip: [ce58867ee17afecda7917e74a0d10afd7138c6d4] drm/i915: Fix enabled > infoframe states of lspcon > > git bisect skip ce58867ee17afecda7917e74a0d10afd7138c6d4 > > # skip: [a211da9c771bf97395a3ced83a3aa383372b13a7] drm/i915/gt: Make > timeslicing an explicit engine property > > git bisect skip a211da9c771bf97395a3ced83a3aa383372b13a7 > > # skip: [dee66f3e071b394de16da18e2807f371b789b1be] drm/i915: Add state > readout for DP HDR Metadata Infoframe SDP > > git bisect skip dee66f3e071b394de16da18e2807f371b789b1be > > # skip: [964a9b0f611ee7fedc90641bfcc2efe6ce6206aa] drm/i915/gem: Use > chained reloc batches > > git bisect skip 964a9b0f611ee7fedc90641bfcc2efe6ce6206aa > > # skip: [f1e79c7e183c8e35def44b07ff7ac221fa87bf04] drm/i915: Replace zero- > length array with flexible-array > > git bisect skip f1e79c7e183c8e35def44b07ff7ac221fa87bf04 > > # good: [ab9c21124d6e03460c9c59006a61cc076fefa82e] drm/amdgpu: Add cmd > to control XGMI link sleep > > git bisect good ab9c21124d6e03460c9c59006a61cc076fefa82e > > # skip: [e31fe02eff2610f40ac8d7efe57ec0b881b75508] drm/i915: Make > intel_timeline_init static > > git bisect skip e31fe02eff2610f40ac8d7efe57ec0b881b75508 > > # skip: [d96536f0fe699729a0974eb5b65eb0d87cc747e1] drm/i915: Fix AUX power > domain toggling across TypeC mode resets > > git bisect skip d96536f0fe699729a0974eb5b65eb0d87cc747e1 > > # skip: [a80d73673bc7676d0bab7f7ab51d00c5e461992d] drm/i915: Tidy awaiting > on dma-fences > > git bisect skip a80d73673bc7676d0bab7f7ab51d00c5e461992d > > # skip: [25444ca6cbb9fe375aa9bba58784a735efe2a649] drm/i915/fbc: Require > linear fb stride to be multiple of 512 bytes on gen9/glk > > git bisect skip 25444ca6cbb9fe375aa9bba58784a735efe2a649 > > # skip: [795d4d7fa34154fc621c1048f8b92e4f6bd3926f] drm/i915: Mark the > addition of the initial-breadcrumb in the request > > git bisect skip 795d4d7fa34154fc621c1048f8b92e4f6bd3926f > > # skip: [d19b29be653691a179e54aafc84fc40667a63ee7] drm/i915: Nuke > mode.vrefresh usage > > git bisect skip d19b29be653691a179e54aafc84fc40667a63ee7 > > # skip: [260a6c1bdf1e072ae4d96f0d1ec2917237f1b627] drm/i915: Fix glk > watermark calculations > > git bisect skip 260a6c1bdf1e072ae4d96f0d1ec2917237f1b627 > > # skip: [56f1b31f1dd60db4b02024a13eea45b5bbccc44e] drm/i915: Store CS > timestamp frequency in Hz > > git bisect skip 56f1b31f1dd60db4b02024a13eea45b5bbccc44e > > # skip: [b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d] drm/i915: Remove > duplicate inline specifier on write_pte > > git bisect skip b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d > > # skip: [0065e5f5cc56136da0be900c4a3121b38a82f37d] drm/i915/display: Warn if > the FBC is still writing to stolen on removal > > git bisect skip 0065e5f5cc56136da0be900c4a3121b38a82f37d > > # skip: [0398993b82f40ad02d88da7c894e3faae2da3b0a] drm/i915: Stash hpd > status bits under dev_priv > > git bisect skip 0398993b82f40ad02d88da7c894e3faae2da3b0a > > # skip: [7241c57d3140ad3b613777a8515ffe1f653d4800] drm/i915: Add TGL+ SAGV > support > > git bisect skip 7241c57d3140ad3b613777a8515ffe1f653d4800 > > # skip: [c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5] drm/i915: Use stashed > away hpd isr bits in intel_digital_port_connected() > > git bisect skip c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5 > > # skip: [f136c58a0de98e1b56483b7fc8c209dba0a496d9] drm/i915: Added required > new PCode commands > > git bisect skip f136c58a0de98e1b56483b7fc8c209dba0a496d9 > > # skip: [9bad40a27dac1f88012a1e2db0bfc5ae58fa0370] drm/i915/selftests: > Always flush before unpining after writing > > git bisect skip 9bad40a27dac1f88012a1e2db0bfc5ae58fa0370 > > # skip: [977253df6433f85d5e2cb3ab0f8eb4127f8173dd] drm/i915/gt: Stop holding > onto the pinned_default_state > > git bisect skip 977253df6433f85d5e2cb3ab0f8eb4127f8173dd > > # skip: [a1b2eeacbc55573afc56341e08b506aee6451c3d] drm/i915: Remove > unused HAS_FWTABLE macro > > git bisect skip a1b2eeacbc55573afc56341e08b506aee6451c3d > > # skip: [24fe5f2ab2478053d50a3bc629ada895903a5cbc] drm/i915: Propagate > error from completed fences > > git bisect skip 24fe5f2ab2478053d50a3bc629ada895903a5cbc > > # skip: [73e28cc40bf00b5d168cb8f5cff1ae63e9097446] drm/i915: Handle idling > during i915_gem_evict_something busy loops > > git bisect skip 73e28cc40bf00b5d168cb8f5cff1ae63e9097446 > > # skip: [f02ac414ba9497d1887b1de7fe69954284f157ac] Revert "drm/i915/tgl: > Include ro parts of l3 to invalidate" > > git bisect skip f02ac414ba9497d1887b1de7fe69954284f157ac > > # skip: [b0a997ae5248b293b6f6d1996ea49c57f7b94227] drm/i915: Emit > await(batch) before MI_BB_START > > git bisect skip b0a997ae5248b293b6f6d1996ea49c57f7b94227 > > # skip: [32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa] drm/i915/gen12: Fix HDC > pipeline flush > > git bisect skip 32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa > > # good: [5e7067b24fcf1549c72988dd92de6d17ff3d2077] drm/amdgpu: Add DPM > function for XGMI link power down control > > git bisect good 5e7067b24fcf1549c72988dd92de6d17ff3d2077 > > # skip: [d248b371f7479a99caccf91da2ec6adee85e5e70] drm/i915/gen12: > Invalidate aux table entries forcibly > > git bisect skip d248b371f7479a99caccf91da2ec6adee85e5e70 > > # good: [b7f0656a25467fc26eb7fc375caf38ee99f5d004] drm/amdgpu: Updated > XGMI power down control support check > > git bisect good b7f0656a25467fc26eb7fc375caf38ee99f5d004 > > # good: [4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240] drm/amdgpu: optimize > amdgpu device attribute code > > git bisect good 4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240 > > # skip: [f45ce9336ff0640e491c642a84ea02f21daac3a4] video/hdmi: Add Unpack > only function for DRM infoframe > > git bisect skip f45ce9336ff0640e491c642a84ea02f21daac3a4 > > # good: [bfbe1744e4417986419236719922a9a7fda224d1] Merge tag 'amd-drm- > next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux into drm-next > > git bisect good bfbe1744e4417986419236719922a9a7fda224d1 > > # skip: [701f026521980dd0151130f818558e17c608ed2e] drm/i915: Drop > I915_RESET_TIMEOUT and friends > > git bisect skip 701f026521980dd0151130f818558e17c608ed2e > > # skip: [378974f7f9754acfd5630327917c6b813495f1a9] drm/i915: Allow some > leniency in PCU reads > > git bisect skip 378974f7f9754acfd5630327917c6b813495f1a9 > > # good: [47e51832ae93534d872511ba557115722582d94c] drm/i915/gvt: use > context lrc_reg_state for shadow ppgtt override > > git bisect good 47e51832ae93534d872511ba557115722582d94c > > # skip: [230982d8d8df7f9d9aa216840ea2db1df6ad5d37] drm/i915: Update > DRIVER_DATE to 20200430 > > git bisect skip 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 > > # > > # Automatically generated file; DO NOT EDIT. > > # Linux/x86_64 5.7.0-rc2 Kernel Configuration > > # > > > > # > > # Compiler: x86_64-linux-gnu-gcc (GCC) 9.2.1 20190827 (Red Hat Cross 9.2.1-3) > > # > > CONFIG_CC_IS_GCC=y > > CONFIG_GCC_VERSION=90201 > > CONFIG_LD_VERSION=234000000 > > CONFIG_CLANG_VERSION=0 > > CONFIG_CC_HAS_ASM_GOTO=y > > CONFIG_CC_HAS_ASM_INLINE=y > > CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y > > CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y > > CONFIG_IRQ_WORK=y > > CONFIG_BUILDTIME_TABLE_SORT=y > > CONFIG_THREAD_INFO_IN_TASK=y > > > > # > > # General setup > > # > > CONFIG_INIT_ENV_ARG_LIMIT=32 > > # CONFIG_COMPILE_TEST is not set > > CONFIG_LOCALVERSION="-fscache" > > # CONFIG_LOCALVERSION_AUTO is not set > > CONFIG_BUILD_SALT="" > > CONFIG_HAVE_KERNEL_GZIP=y > > CONFIG_HAVE_KERNEL_BZIP2=y > > CONFIG_HAVE_KERNEL_LZMA=y > > CONFIG_HAVE_KERNEL_XZ=y > > CONFIG_HAVE_KERNEL_LZO=y > > CONFIG_HAVE_KERNEL_LZ4=y > > # CONFIG_KERNEL_GZIP is not set > > # CONFIG_KERNEL_BZIP2 is not set > > # CONFIG_KERNEL_LZMA is not set > > CONFIG_KERNEL_XZ=y > > # CONFIG_KERNEL_LZO is not set > > # CONFIG_KERNEL_LZ4 is not set > > CONFIG_DEFAULT_HOSTNAME="(none)" > > CONFIG_SWAP=y > > CONFIG_SYSVIPC=y > > CONFIG_SYSVIPC_SYSCTL=y > > CONFIG_POSIX_MQUEUE=y > > CONFIG_POSIX_MQUEUE_SYSCTL=y > > CONFIG_CROSS_MEMORY_ATTACH=y > > # CONFIG_USELIB is not set > > CONFIG_AUDIT=y > > CONFIG_HAVE_ARCH_AUDITSYSCALL=y > > CONFIG_AUDITSYSCALL=y > > > > # > > # IRQ subsystem > > # > > CONFIG_GENERIC_IRQ_PROBE=y > > CONFIG_GENERIC_IRQ_SHOW=y > > CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y > > CONFIG_GENERIC_PENDING_IRQ=y > > CONFIG_GENERIC_IRQ_MIGRATION=y > > CONFIG_HARDIRQS_SW_RESEND=y > > CONFIG_IRQ_DOMAIN=y > > CONFIG_IRQ_DOMAIN_HIERARCHY=y > > CONFIG_GENERIC_MSI_IRQ=y > > CONFIG_GENERIC_MSI_IRQ_DOMAIN=y > > CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y > > CONFIG_GENERIC_IRQ_RESERVATION_MODE=y > > CONFIG_IRQ_FORCED_THREADING=y > > CONFIG_SPARSE_IRQ=y > > # CONFIG_GENERIC_IRQ_DEBUGFS is not set > > # end of IRQ subsystem > > > > CONFIG_CLOCKSOURCE_WATCHDOG=y > > CONFIG_ARCH_CLOCKSOURCE_INIT=y > > CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y > > CONFIG_GENERIC_TIME_VSYSCALL=y > > CONFIG_GENERIC_CLOCKEVENTS=y > > CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y > > CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y > > CONFIG_GENERIC_CMOS_UPDATE=y > > > > # > > # Timers subsystem > > # > > CONFIG_TICK_ONESHOT=y > > CONFIG_NO_HZ_COMMON=y > > # CONFIG_HZ_PERIODIC is not set > > # CONFIG_NO_HZ_IDLE is not set > > CONFIG_NO_HZ_FULL=y > > CONFIG_CONTEXT_TRACKING=y > > CONFIG_CONTEXT_TRACKING_FORCE=y > > # CONFIG_NO_HZ is not set > > CONFIG_HIGH_RES_TIMERS=y > > # end of Timers subsystem > > > > CONFIG_PREEMPT_NONE=y > > # CONFIG_PREEMPT_VOLUNTARY is not set > > # CONFIG_PREEMPT is not set > > > > # > > # CPU/Task time and stats accounting > > # > > CONFIG_VIRT_CPU_ACCOUNTING=y > > CONFIG_VIRT_CPU_ACCOUNTING_GEN=y > > # CONFIG_IRQ_TIME_ACCOUNTING is not set > > # CONFIG_SCHED_THERMAL_PRESSURE is not set > > CONFIG_BSD_PROCESS_ACCT=y > > CONFIG_BSD_PROCESS_ACCT_V3=y > > CONFIG_TASKSTATS=y > > CONFIG_TASK_DELAY_ACCT=y > > CONFIG_TASK_XACCT=y > > CONFIG_TASK_IO_ACCOUNTING=y > > # CONFIG_PSI is not set > > # end of CPU/Task time and stats accounting > > > > CONFIG_CPU_ISOLATION=y > > > > # > > # RCU Subsystem > > # > > CONFIG_TREE_RCU=y > > # CONFIG_RCU_EXPERT is not set > > CONFIG_SRCU=y > > CONFIG_TREE_SRCU=y > > CONFIG_RCU_STALL_COMMON=y > > CONFIG_RCU_NEED_SEGCBLIST=y > > CONFIG_RCU_NOCB_CPU=y > > # end of RCU Subsystem > > > > CONFIG_BUILD_BIN2C=y > > # CONFIG_IKCONFIG is not set > > # CONFIG_IKHEADERS is not set > > CONFIG_LOG_BUF_SHIFT=16 > > CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 > > CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 > > CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y > > > > # > > # Scheduler features > > # > > # CONFIG_UCLAMP_TASK is not set > > # end of Scheduler features > > > > CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y > > CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y > > CONFIG_CC_HAS_INT128=y > > CONFIG_ARCH_SUPPORTS_INT128=y > > # CONFIG_NUMA_BALANCING is not set > > CONFIG_CGROUPS=y > > CONFIG_PAGE_COUNTER=y > > CONFIG_MEMCG=y > > CONFIG_MEMCG_SWAP=y > > CONFIG_MEMCG_SWAP_ENABLED=y > > CONFIG_MEMCG_KMEM=y > > CONFIG_BLK_CGROUP=y > > CONFIG_CGROUP_WRITEBACK=y > > CONFIG_CGROUP_SCHED=y > > CONFIG_FAIR_GROUP_SCHED=y > > # CONFIG_CFS_BANDWIDTH is not set > > # CONFIG_RT_GROUP_SCHED is not set > > # CONFIG_CGROUP_PIDS is not set > > CONFIG_CGROUP_RDMA=y > > CONFIG_CGROUP_FREEZER=y > > CONFIG_CGROUP_HUGETLB=y > > CONFIG_CPUSETS=y > > CONFIG_PROC_PID_CPUSET=y > > CONFIG_CGROUP_DEVICE=y > > CONFIG_CGROUP_CPUACCT=y > > CONFIG_CGROUP_PERF=y > > # CONFIG_CGROUP_BPF is not set > > # CONFIG_CGROUP_DEBUG is not set > > CONFIG_SOCK_CGROUP_DATA=y > > CONFIG_NAMESPACES=y > > CONFIG_UTS_NS=y > > CONFIG_TIME_NS=y > > CONFIG_IPC_NS=y > > CONFIG_USER_NS=y > > CONFIG_PID_NS=y > > CONFIG_NET_NS=y > > # CONFIG_CHECKPOINT_RESTORE is not set > > # CONFIG_SCHED_AUTOGROUP is not set > > # CONFIG_SYSFS_DEPRECATED is not set > > CONFIG_RELAY=y > > CONFIG_BLK_DEV_INITRD=y > > CONFIG_INITRAMFS_SOURCE="" > > CONFIG_RD_GZIP=y > > # CONFIG_RD_BZIP2 is not set > > # CONFIG_RD_LZMA is not set > > # CONFIG_RD_XZ is not set > > # CONFIG_RD_LZO is not set > > # CONFIG_RD_LZ4 is not set > > # CONFIG_BOOT_CONFIG is not set > > # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set > > CONFIG_CC_OPTIMIZE_FOR_SIZE=y > > CONFIG_SYSCTL=y > > CONFIG_HAVE_UID16=y > > CONFIG_SYSCTL_EXCEPTION_TRACE=y > > CONFIG_HAVE_PCSPKR_PLATFORM=y > > CONFIG_BPF=y > > CONFIG_EXPERT=y > > CONFIG_UID16=y > > CONFIG_MULTIUSER=y > > # CONFIG_SGETMASK_SYSCALL is not set > > # CONFIG_SYSFS_SYSCALL is not set > > CONFIG_FHANDLE=y > > CONFIG_POSIX_TIMERS=y > > CONFIG_PRINTK=y > > CONFIG_PRINTK_NMI=y > > CONFIG_BUG=y > > CONFIG_ELF_CORE=y > > CONFIG_PCSPKR_PLATFORM=y > > CONFIG_BASE_FULL=y > > CONFIG_FUTEX=y > > CONFIG_FUTEX_PI=y > > CONFIG_EPOLL=y > > CONFIG_SIGNALFD=y > > CONFIG_TIMERFD=y > > CONFIG_EVENTFD=y > > CONFIG_SHMEM=y > > CONFIG_AIO=y > > # CONFIG_IO_URING is not set > > CONFIG_ADVISE_SYSCALLS=y > > CONFIG_MEMBARRIER=y > > CONFIG_KALLSYMS=y > > CONFIG_KALLSYMS_ALL=y > > CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y > > CONFIG_KALLSYMS_BASE_RELATIVE=y > > CONFIG_BPF_SYSCALL=y > > CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y > > # CONFIG_USERFAULTFD is not set > > CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y > > CONFIG_RSEQ=y > > # CONFIG_DEBUG_RSEQ is not set > > # CONFIG_EMBEDDED is not set > > CONFIG_HAVE_PERF_EVENTS=y > > # CONFIG_PC104 is not set > > > > # > > # Kernel Performance Events And Counters > > # > > CONFIG_PERF_EVENTS=y > > # CONFIG_DEBUG_PERF_USE_VMALLOC is not set > > # end of Kernel Performance Events And Counters > > > > CONFIG_VM_EVENT_COUNTERS=y > > CONFIG_COMPAT_BRK=y > > CONFIG_SLAB=y > > # CONFIG_SLUB is not set > > # CONFIG_SLOB is not set > > CONFIG_SLAB_MERGE_DEFAULT=y > > # CONFIG_SLAB_FREELIST_RANDOM is not set > > # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set > > CONFIG_SYSTEM_DATA_VERIFICATION=y > > # CONFIG_PROFILING is not set > > CONFIG_TRACEPOINTS=y > > # end of General setup > > > > CONFIG_64BIT=y > > CONFIG_X86_64=y > > CONFIG_X86=y > > CONFIG_INSTRUCTION_DECODER=y > > CONFIG_OUTPUT_FORMAT="elf64-x86-64" > > CONFIG_LOCKDEP_SUPPORT=y > > CONFIG_STACKTRACE_SUPPORT=y > > CONFIG_MMU=y > > CONFIG_ARCH_MMAP_RND_BITS_MIN=28 > > CONFIG_ARCH_MMAP_RND_BITS_MAX=32 > > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 > > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 > > CONFIG_GENERIC_ISA_DMA=y > > CONFIG_GENERIC_BUG=y > > CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y > > CONFIG_ARCH_MAY_HAVE_PC_FDC=y > > CONFIG_GENERIC_CALIBRATE_DELAY=y > > CONFIG_ARCH_HAS_CPU_RELAX=y > > CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y > > CONFIG_ARCH_HAS_FILTER_PGPROT=y > > CONFIG_HAVE_SETUP_PER_CPU_AREA=y > > CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y > > CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y > > CONFIG_ARCH_HIBERNATION_POSSIBLE=y > > CONFIG_ARCH_SUSPEND_POSSIBLE=y > > CONFIG_ARCH_WANT_GENERAL_HUGETLB=y > > CONFIG_ZONE_DMA32=y > > CONFIG_AUDIT_ARCH=y > > CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y > > CONFIG_HAVE_INTEL_TXT=y > > CONFIG_X86_64_SMP=y > > CONFIG_ARCH_SUPPORTS_UPROBES=y > > CONFIG_FIX_EARLYCON_MEM=y > > CONFIG_PGTABLE_LEVELS=4 > > CONFIG_CC_HAS_SANE_STACKPROTECTOR=y > > > > # > > # Processor type and features > > # > > CONFIG_ZONE_DMA=y > > CONFIG_SMP=y > > CONFIG_X86_FEATURE_NAMES=y > > CONFIG_X86_MPPARSE=y > > # CONFIG_GOLDFISH is not set > > # CONFIG_RETPOLINE is not set > > CONFIG_X86_CPU_RESCTRL=y > > # CONFIG_X86_EXTENDED_PLATFORM is not set > > # CONFIG_X86_INTEL_LPSS is not set > > # CONFIG_X86_AMD_PLATFORM_DEVICE is not set > > CONFIG_IOSF_MBI=y > > # CONFIG_IOSF_MBI_DEBUG is not set > > CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y > > # CONFIG_SCHED_OMIT_FRAME_POINTER is not set > > # CONFIG_HYPERVISOR_GUEST is not set > > # CONFIG_MK8 is not set > > # CONFIG_MPSC is not set > > CONFIG_MCORE2=y > > # CONFIG_MATOM is not set > > # CONFIG_GENERIC_CPU is not set > > CONFIG_X86_INTERNODE_CACHE_SHIFT=6 > > CONFIG_X86_L1_CACHE_SHIFT=6 > > CONFIG_X86_INTEL_USERCOPY=y > > CONFIG_X86_USE_PPRO_CHECKSUM=y > > CONFIG_X86_P6_NOP=y > > CONFIG_X86_TSC=y > > CONFIG_X86_CMPXCHG64=y > > CONFIG_X86_CMOV=y > > CONFIG_X86_MINIMUM_CPU_FAMILY=64 > > CONFIG_X86_DEBUGCTLMSR=y > > CONFIG_IA32_FEAT_CTL=y > > CONFIG_X86_VMX_FEATURE_NAMES=y > > # CONFIG_PROCESSOR_SELECT is not set > > CONFIG_CPU_SUP_INTEL=y > > CONFIG_CPU_SUP_AMD=y > > CONFIG_CPU_SUP_HYGON=y > > CONFIG_CPU_SUP_CENTAUR=y > > CONFIG_CPU_SUP_ZHAOXIN=y > > CONFIG_HPET_TIMER=y > > CONFIG_HPET_EMULATE_RTC=y > > CONFIG_DMI=y > > CONFIG_GART_IOMMU=y > > # CONFIG_MAXSMP is not set > > CONFIG_NR_CPUS_RANGE_BEGIN=2 > > CONFIG_NR_CPUS_RANGE_END=512 > > CONFIG_NR_CPUS_DEFAULT=64 > > CONFIG_NR_CPUS=4 > > CONFIG_SCHED_SMT=y > > CONFIG_SCHED_MC=y > > CONFIG_SCHED_MC_PRIO=y > > CONFIG_X86_LOCAL_APIC=y > > CONFIG_X86_IO_APIC=y > > # CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set > > CONFIG_X86_MCE=y > > # CONFIG_X86_MCELOG_LEGACY is not set > > CONFIG_X86_MCE_INTEL=y > > # CONFIG_X86_MCE_AMD is not set > > CONFIG_X86_MCE_THRESHOLD=y > > # CONFIG_X86_MCE_INJECT is not set > > CONFIG_X86_THERMAL_VECTOR=y > > > > # > > # Performance monitoring > > # > > CONFIG_PERF_EVENTS_INTEL_UNCORE=y > > CONFIG_PERF_EVENTS_INTEL_RAPL=y > > CONFIG_PERF_EVENTS_INTEL_CSTATE=y > > # CONFIG_PERF_EVENTS_AMD_POWER is not set > > # end of Performance monitoring > > > > CONFIG_X86_16BIT=y > > CONFIG_X86_ESPFIX64=y > > CONFIG_X86_VSYSCALL_EMULATION=y > > # CONFIG_X86_IOPL_IOPERM is not set > > # CONFIG_I8K is not set > > # CONFIG_MICROCODE is not set > > CONFIG_X86_MSR=y > > CONFIG_X86_CPUID=y > > # CONFIG_X86_5LEVEL is not set > > CONFIG_X86_DIRECT_GBPAGES=y > > # CONFIG_X86_CPA_STATISTICS is not set > > # CONFIG_AMD_MEM_ENCRYPT is not set > > CONFIG_NUMA=y > > # CONFIG_AMD_NUMA is not set > > CONFIG_X86_64_ACPI_NUMA=y > > CONFIG_NODES_SPAN_OTHER_NODES=y > > # CONFIG_NUMA_EMU is not set > > CONFIG_NODES_SHIFT=6 > > CONFIG_ARCH_SPARSEMEM_ENABLE=y > > CONFIG_ARCH_SPARSEMEM_DEFAULT=y > > CONFIG_ARCH_SELECT_MEMORY_MODEL=y > > CONFIG_ARCH_PROC_KCORE_TEXT=y > > CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 > > # CONFIG_X86_PMEM_LEGACY is not set > > # CONFIG_X86_CHECK_BIOS_CORRUPTION is not set > > CONFIG_X86_RESERVE_LOW=64 > > CONFIG_MTRR=y > > # CONFIG_MTRR_SANITIZER is not set > > CONFIG_X86_PAT=y > > CONFIG_ARCH_USES_PG_UNCACHED=y > > CONFIG_ARCH_RANDOM=y > > CONFIG_X86_SMAP=y > > CONFIG_X86_UMIP=y > > CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y > > CONFIG_X86_INTEL_TSX_MODE_OFF=y > > # CONFIG_X86_INTEL_TSX_MODE_ON is not set > > # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set > > CONFIG_EFI=y > > CONFIG_EFI_STUB=y > > # CONFIG_EFI_MIXED is not set > > CONFIG_SECCOMP=y > > # CONFIG_HZ_100 is not set > > CONFIG_HZ_250=y > > # CONFIG_HZ_300 is not set > > # CONFIG_HZ_1000 is not set > > CONFIG_HZ=250 > > CONFIG_SCHED_HRTICK=y > > CONFIG_KEXEC=y > > CONFIG_KEXEC_FILE=y > > CONFIG_ARCH_HAS_KEXEC_PURGATORY=y > > # CONFIG_KEXEC_SIG is not set > > # CONFIG_CRASH_DUMP is not set > > CONFIG_PHYSICAL_START=0x1000000 > > CONFIG_RELOCATABLE=y > > # CONFIG_RANDOMIZE_BASE is not set > > CONFIG_PHYSICAL_ALIGN=0x1000000 > > CONFIG_HOTPLUG_CPU=y > > # CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set > > # CONFIG_DEBUG_HOTPLUG_CPU0 is not set > > CONFIG_COMPAT_VDSO=y > > # CONFIG_LEGACY_VSYSCALL_EMULATE is not set > > CONFIG_LEGACY_VSYSCALL_XONLY=y > > # CONFIG_LEGACY_VSYSCALL_NONE is not set > > # CONFIG_CMDLINE_BOOL is not set > > CONFIG_MODIFY_LDT_SYSCALL=y > > CONFIG_HAVE_LIVEPATCH=y > > CONFIG_LIVEPATCH=y > > # end of Processor type and features > > > > CONFIG_ARCH_HAS_ADD_PAGES=y > > CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y > > CONFIG_USE_PERCPU_NUMA_NODE_ID=y > > CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y > > CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y > > > > # > > # Power management and ACPI options > > # > > # CONFIG_SUSPEND is not set > > # CONFIG_HIBERNATION is not set > > CONFIG_PM=y > > # CONFIG_PM_DEBUG is not set > > CONFIG_PM_CLK=y > > CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y > > CONFIG_ENERGY_MODEL=y > > CONFIG_ARCH_SUPPORTS_ACPI=y > > CONFIG_ACPI=y > > CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y > > CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y > > CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y > > # CONFIG_ACPI_DEBUGGER is not set > > CONFIG_ACPI_SPCR_TABLE=y > > CONFIG_ACPI_LPIT=y > > # CONFIG_ACPI_PROCFS_POWER is not set > > CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y > > # CONFIG_ACPI_EC_DEBUGFS is not set > > CONFIG_ACPI_AC=y > > # CONFIG_ACPI_BATTERY is not set > > CONFIG_ACPI_BUTTON=y > > CONFIG_ACPI_VIDEO=y > > CONFIG_ACPI_FAN=y > > CONFIG_ACPI_DOCK=y > > CONFIG_ACPI_CPU_FREQ_PSS=y > > CONFIG_ACPI_PROCESSOR_CSTATE=y > > CONFIG_ACPI_PROCESSOR_IDLE=y > > CONFIG_ACPI_CPPC_LIB=y > > CONFIG_ACPI_PROCESSOR=y > > # CONFIG_ACPI_IPMI is not set > > CONFIG_ACPI_HOTPLUG_CPU=y > > CONFIG_ACPI_PROCESSOR_AGGREGATOR=y > > CONFIG_ACPI_THERMAL=y > > CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y > > CONFIG_ACPI_TABLE_UPGRADE=y > > CONFIG_ACPI_DEBUG=y > > # CONFIG_ACPI_PCI_SLOT is not set > > CONFIG_ACPI_CONTAINER=y > > CONFIG_ACPI_HOTPLUG_IOAPIC=y > > # CONFIG_ACPI_SBS is not set > > CONFIG_ACPI_HED=y > > # CONFIG_ACPI_CUSTOM_METHOD is not set > > # CONFIG_ACPI_BGRT is not set > > # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set > > # CONFIG_ACPI_NFIT is not set > > CONFIG_ACPI_NUMA=y > > # CONFIG_ACPI_HMAT is not set > > CONFIG_HAVE_ACPI_APEI=y > > CONFIG_HAVE_ACPI_APEI_NMI=y > > CONFIG_ACPI_APEI=y > > CONFIG_ACPI_APEI_GHES=y > > # CONFIG_ACPI_APEI_PCIEAER is not set > > CONFIG_ACPI_APEI_EINJ=y > > # CONFIG_ACPI_APEI_ERST_DEBUG is not set > > # CONFIG_DPTF_POWER is not set > > # CONFIG_PMIC_OPREGION is not set > > # CONFIG_ACPI_CONFIGFS is not set > > CONFIG_X86_PM_TIMER=y > > # CONFIG_SFI is not set > > > > # > > # CPU Frequency scaling > > # > > CONFIG_CPU_FREQ=y > > CONFIG_CPU_FREQ_GOV_ATTR_SET=y > > CONFIG_CPU_FREQ_GOV_COMMON=y > > CONFIG_CPU_FREQ_STAT=y > > # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set > > # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set > > # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set > > # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set > > CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y > > # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set > > CONFIG_CPU_FREQ_GOV_PERFORMANCE=y > > CONFIG_CPU_FREQ_GOV_POWERSAVE=y > > CONFIG_CPU_FREQ_GOV_USERSPACE=y > > CONFIG_CPU_FREQ_GOV_ONDEMAND=y > > CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y > > CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y > > > > # > > # CPU frequency scaling drivers > > # > > CONFIG_X86_INTEL_PSTATE=y > > CONFIG_X86_PCC_CPUFREQ=y > > CONFIG_X86_ACPI_CPUFREQ=y > > # CONFIG_X86_ACPI_CPUFREQ_CPB is not set > > # CONFIG_X86_POWERNOW_K8 is not set > > # CONFIG_X86_AMD_FREQ_SENSITIVITY is not set > > # CONFIG_X86_SPEEDSTEP_CENTRINO is not set > > # CONFIG_X86_P4_CLOCKMOD is not set > > > > # > > # shared options > > # > > # end of CPU Frequency scaling > > > > # > > # CPU Idle > > # > > CONFIG_CPU_IDLE=y > > CONFIG_CPU_IDLE_GOV_LADDER=y > > CONFIG_CPU_IDLE_GOV_MENU=y > > # CONFIG_CPU_IDLE_GOV_TEO is not set > > # end of CPU Idle > > > > CONFIG_INTEL_IDLE=y > > # end of Power management and ACPI options > > > > # > > # Bus options (PCI etc.) > > # > > CONFIG_PCI_DIRECT=y > > CONFIG_PCI_MMCONFIG=y > > CONFIG_MMCONF_FAM10H=y > > # CONFIG_PCI_CNB20LE_QUIRK is not set > > # CONFIG_ISA_BUS is not set > > CONFIG_ISA_DMA_API=y > > CONFIG_AMD_NB=y > > # CONFIG_X86_SYSFB is not set > > # end of Bus options (PCI etc.) > > > > # > > # Binary Emulations > > # > > CONFIG_IA32_EMULATION=y > > # CONFIG_X86_X32 is not set > > CONFIG_COMPAT_32=y > > CONFIG_COMPAT=y > > CONFIG_COMPAT_FOR_U64_ALIGNMENT=y > > CONFIG_SYSVIPC_COMPAT=y > > # end of Binary Emulations > > > > # > > # Firmware Drivers > > # > > # CONFIG_EDD is not set > > CONFIG_FIRMWARE_MEMMAP=y > > CONFIG_DMIID=y > > # CONFIG_DMI_SYSFS is not set > > CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y > > # CONFIG_FW_CFG_SYSFS is not set > > # CONFIG_GOOGLE_FIRMWARE is not set > > > > # > > # EFI (Extensible Firmware Interface) Support > > # > > # CONFIG_EFI_VARS is not set > > CONFIG_EFI_ESRT=y > > CONFIG_EFI_RUNTIME_MAP=y > > # CONFIG_EFI_FAKE_MEMMAP is not set > > CONFIG_EFI_RUNTIME_WRAPPERS=y > > # CONFIG_EFI_CAPSULE_LOADER is not set > > # CONFIG_EFI_TEST is not set > > # CONFIG_APPLE_PROPERTIES is not set > > # CONFIG_RESET_ATTACK_MITIGATION is not set > > # CONFIG_EFI_RCI2_TABLE is not set > > # CONFIG_EFI_DISABLE_PCI_DMA is not set > > # end of EFI (Extensible Firmware Interface) Support > > > > CONFIG_UEFI_CPER=y > > CONFIG_UEFI_CPER_X86=y > > CONFIG_EFI_EARLYCON=y > > > > # > > # Tegra firmware driver > > # > > # end of Tegra firmware driver > > # end of Firmware Drivers > > > > CONFIG_HAVE_KVM=y > > # CONFIG_VIRTUALIZATION is not set > > CONFIG_AS_AVX512=y > > CONFIG_AS_SHA1_NI=y > > CONFIG_AS_SHA256_NI=y > > > > # > > # General architecture-dependent options > > # > > CONFIG_CRASH_CORE=y > > CONFIG_KEXEC_CORE=y > > CONFIG_HOTPLUG_SMT=y > > CONFIG_HAVE_OPROFILE=y > > CONFIG_OPROFILE_NMI_TIMER=y > > CONFIG_KPROBES=y > > CONFIG_JUMP_LABEL=y > > # CONFIG_STATIC_KEYS_SELFTEST is not set > > CONFIG_OPTPROBES=y > > CONFIG_KPROBES_ON_FTRACE=y > > CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y > > CONFIG_ARCH_USE_BUILTIN_BSWAP=y > > CONFIG_KRETPROBES=y > > CONFIG_HAVE_IOREMAP_PROT=y > > CONFIG_HAVE_KPROBES=y > > CONFIG_HAVE_KRETPROBES=y > > CONFIG_HAVE_OPTPROBES=y > > CONFIG_HAVE_KPROBES_ON_FTRACE=y > > CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y > > CONFIG_HAVE_NMI=y > > CONFIG_HAVE_ARCH_TRACEHOOK=y > > CONFIG_HAVE_DMA_CONTIGUOUS=y > > CONFIG_GENERIC_SMP_IDLE_THREAD=y > > CONFIG_ARCH_HAS_FORTIFY_SOURCE=y > > CONFIG_ARCH_HAS_SET_MEMORY=y > > CONFIG_ARCH_HAS_SET_DIRECT_MAP=y > > CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y > > CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y > > CONFIG_HAVE_ASM_MODVERSIONS=y > > CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y > > CONFIG_HAVE_RSEQ=y > > CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y > > CONFIG_HAVE_CLK=y > > CONFIG_HAVE_HW_BREAKPOINT=y > > CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y > > CONFIG_HAVE_USER_RETURN_NOTIFIER=y > > CONFIG_HAVE_PERF_EVENTS_NMI=y > > CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y > > CONFIG_HAVE_PERF_REGS=y > > CONFIG_HAVE_PERF_USER_STACK_DUMP=y > > CONFIG_HAVE_ARCH_JUMP_LABEL=y > > CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y > > CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y > > CONFIG_HAVE_CMPXCHG_LOCAL=y > > CONFIG_HAVE_CMPXCHG_DOUBLE=y > > CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y > > CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y > > CONFIG_HAVE_ARCH_SECCOMP_FILTER=y > > CONFIG_SECCOMP_FILTER=y > > CONFIG_HAVE_ARCH_STACKLEAK=y > > CONFIG_HAVE_STACKPROTECTOR=y > > CONFIG_CC_HAS_STACKPROTECTOR_NONE=y > > CONFIG_STACKPROTECTOR=y > > CONFIG_STACKPROTECTOR_STRONG=y > > CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y > > CONFIG_HAVE_CONTEXT_TRACKING=y > > CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y > > CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y > > CONFIG_HAVE_MOVE_PMD=y > > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y > > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y > > CONFIG_HAVE_ARCH_HUGE_VMAP=y > > CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y > > CONFIG_HAVE_ARCH_SOFT_DIRTY=y > > CONFIG_HAVE_MOD_ARCH_SPECIFIC=y > > CONFIG_MODULES_USE_ELF_RELA=y > > CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y > > CONFIG_ARCH_HAS_ELF_RANDOMIZE=y > > CONFIG_HAVE_ARCH_MMAP_RND_BITS=y > > CONFIG_HAVE_EXIT_THREAD=y > > CONFIG_ARCH_MMAP_RND_BITS=28 > > CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y > > CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 > > CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y > > CONFIG_HAVE_COPY_THREAD_TLS=y > > CONFIG_HAVE_STACK_VALIDATION=y > > CONFIG_HAVE_RELIABLE_STACKTRACE=y > > CONFIG_OLD_SIGSUSPEND3=y > > CONFIG_COMPAT_OLD_SIGACTION=y > > CONFIG_COMPAT_32BIT_TIME=y > > CONFIG_HAVE_ARCH_VMAP_STACK=y > > # CONFIG_VMAP_STACK is not set > > CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y > > CONFIG_STRICT_KERNEL_RWX=y > > CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y > > CONFIG_STRICT_MODULE_RWX=y > > CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y > > CONFIG_ARCH_USE_MEMREMAP_PROT=y > > # CONFIG_LOCK_EVENT_COUNTS is not set > > CONFIG_ARCH_HAS_MEM_ENCRYPT=y > > > > # > > # GCOV-based kernel profiling > > # > > # CONFIG_GCOV_KERNEL is not set > > CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y > > # end of GCOV-based kernel profiling > > > > CONFIG_HAVE_GCC_PLUGINS=y > > CONFIG_GCC_PLUGINS=y > > # CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set > > # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set > > # CONFIG_GCC_PLUGIN_RANDSTRUCT is not set > > # end of General architecture-dependent options > > > > CONFIG_RT_MUTEXES=y > > CONFIG_BASE_SMALL=0 > > CONFIG_MODULE_SIG_FORMAT=y > > CONFIG_MODULES=y > > # CONFIG_MODULE_FORCE_LOAD is not set > > CONFIG_MODULE_UNLOAD=y > > # CONFIG_MODULE_FORCE_UNLOAD is not set > > # CONFIG_MODVERSIONS is not set > > # CONFIG_MODULE_SRCVERSION_ALL is not set > > CONFIG_MODULE_SIG=y > > # CONFIG_MODULE_SIG_FORCE is not set > > CONFIG_MODULE_SIG_ALL=y > > # CONFIG_MODULE_SIG_SHA1 is not set > > # CONFIG_MODULE_SIG_SHA224 is not set > > CONFIG_MODULE_SIG_SHA256=y > > # CONFIG_MODULE_SIG_SHA384 is not set > > # CONFIG_MODULE_SIG_SHA512 is not set > > CONFIG_MODULE_SIG_HASH="sha256" > > # CONFIG_MODULE_COMPRESS is not set > > # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set > > CONFIG_UNUSED_SYMBOLS=y > > CONFIG_MODULES_TREE_LOOKUP=y > > CONFIG_BLOCK=y > > CONFIG_BLK_SCSI_REQUEST=y > > CONFIG_BLK_DEV_BSG=y > > # CONFIG_BLK_DEV_BSGLIB is not set > > # CONFIG_BLK_DEV_INTEGRITY is not set > > # CONFIG_BLK_DEV_ZONED is not set > > # CONFIG_BLK_DEV_THROTTLING is not set > > # CONFIG_BLK_CMDLINE_PARSER is not set > > # CONFIG_BLK_WBT is not set > > # CONFIG_BLK_CGROUP_IOLATENCY is not set > > # CONFIG_BLK_CGROUP_IOCOST is not set > > CONFIG_BLK_DEBUG_FS=y > > # CONFIG_BLK_SED_OPAL is not set > > > > # > > # Partition Types > > # > > # CONFIG_PARTITION_ADVANCED is not set > > CONFIG_MSDOS_PARTITION=y > > CONFIG_EFI_PARTITION=y > > # end of Partition Types > > > > CONFIG_BLOCK_COMPAT=y > > CONFIG_BLK_MQ_PCI=y > > CONFIG_BLK_PM=y > > > > # > > # IO Schedulers > > # > > CONFIG_MQ_IOSCHED_DEADLINE=y > > CONFIG_MQ_IOSCHED_KYBER=y > > # CONFIG_IOSCHED_BFQ is not set > > # end of IO Schedulers > > > > CONFIG_ASN1=y > > CONFIG_UNINLINE_SPIN_UNLOCK=y > > CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y > > CONFIG_MUTEX_SPIN_ON_OWNER=y > > CONFIG_RWSEM_SPIN_ON_OWNER=y > > CONFIG_LOCK_SPIN_ON_OWNER=y > > CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y > > CONFIG_QUEUED_SPINLOCKS=y > > CONFIG_ARCH_USE_QUEUED_RWLOCKS=y > > CONFIG_QUEUED_RWLOCKS=y > > CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y > > CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y > > CONFIG_FREEZER=y > > > > # > > # Executable file formats > > # > > CONFIG_BINFMT_ELF=y > > CONFIG_COMPAT_BINFMT_ELF=y > > CONFIG_ELFCORE=y > > # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set > > CONFIG_BINFMT_SCRIPT=y > > CONFIG_BINFMT_MISC=y > > CONFIG_COREDUMP=y > > # end of Executable file formats > > > > # > > # Memory Management options > > # > > CONFIG_SELECT_MEMORY_MODEL=y > > CONFIG_SPARSEMEM_MANUAL=y > > CONFIG_SPARSEMEM=y > > CONFIG_NEED_MULTIPLE_NODES=y > > CONFIG_HAVE_MEMORY_PRESENT=y > > CONFIG_SPARSEMEM_EXTREME=y > > CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y > > CONFIG_SPARSEMEM_VMEMMAP=y > > CONFIG_HAVE_MEMBLOCK_NODE_MAP=y > > CONFIG_HAVE_FAST_GUP=y > > # CONFIG_MEMORY_HOTPLUG is not set > > CONFIG_SPLIT_PTLOCK_CPUS=4 > > # CONFIG_COMPACTION is not set > > # CONFIG_PAGE_REPORTING is not set > > CONFIG_MIGRATION=y > > CONFIG_PHYS_ADDR_T_64BIT=y > > CONFIG_BOUNCE=y > > CONFIG_VIRT_TO_BUS=y > > CONFIG_MMU_NOTIFIER=y > > # CONFIG_KSM is not set > > CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 > > CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y > > # CONFIG_MEMORY_FAILURE is not set > > # CONFIG_TRANSPARENT_HUGEPAGE is not set > > CONFIG_ARCH_WANTS_THP_SWAP=y > > # CONFIG_CLEANCACHE is not set > > # CONFIG_FRONTSWAP is not set > > # CONFIG_CMA is not set > > CONFIG_ZPOOL=m > > CONFIG_ZBUD=m > > CONFIG_Z3FOLD=m > > CONFIG_ZSMALLOC=m > > # CONFIG_PGTABLE_MAPPING is not set > > # CONFIG_ZSMALLOC_STAT is not set > > CONFIG_GENERIC_EARLY_IOREMAP=y > > # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set > > # CONFIG_IDLE_PAGE_TRACKING is not set > > CONFIG_ARCH_HAS_PTE_DEVMAP=y > > CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y > > CONFIG_ARCH_HAS_PKEYS=y > > # CONFIG_PERCPU_STATS is not set > > # CONFIG_GUP_BENCHMARK is not set > > CONFIG_ARCH_HAS_PTE_SPECIAL=y > > # end of Memory Management options > > > > CONFIG_NET=y > > CONFIG_SKB_EXTENSIONS=y > > > > # > > # Networking options > > # > > CONFIG_PACKET=y > > # CONFIG_PACKET_DIAG is not set > > CONFIG_UNIX=y > > CONFIG_UNIX_SCM=y > > # CONFIG_UNIX_DIAG is not set > > # CONFIG_TLS is not set > > CONFIG_XFRM=y > > CONFIG_XFRM_ALGO=y > > # CONFIG_XFRM_USER is not set > > # CONFIG_XFRM_INTERFACE is not set > > # CONFIG_XFRM_SUB_POLICY is not set > > # CONFIG_XFRM_MIGRATE is not set > > # CONFIG_XFRM_STATISTICS is not set > > CONFIG_XFRM_IPCOMP=y > > # CONFIG_NET_KEY is not set > > # CONFIG_XDP_SOCKETS is not set > > CONFIG_INET=y > > CONFIG_IP_MULTICAST=y > > CONFIG_IP_ADVANCED_ROUTER=y > > CONFIG_IP_FIB_TRIE_STATS=y > > CONFIG_IP_MULTIPLE_TABLES=y > > CONFIG_IP_ROUTE_MULTIPATH=y > > CONFIG_IP_ROUTE_VERBOSE=y > > # CONFIG_IP_PNP is not set > > # CONFIG_NET_IPIP is not set > > # CONFIG_NET_IPGRE_DEMUX is not set > > # CONFIG_IP_MROUTE is not set > > # CONFIG_SYN_COOKIES is not set > > # CONFIG_NET_IPVTI is not set > > # CONFIG_NET_FOU is not set > > # CONFIG_INET_AH is not set > > # CONFIG_INET_ESP is not set > > # CONFIG_INET_IPCOMP is not set > > CONFIG_INET_DIAG=y > > CONFIG_INET_TCP_DIAG=y > > # CONFIG_INET_UDP_DIAG is not set > > # CONFIG_INET_RAW_DIAG is not set > > # CONFIG_INET_DIAG_DESTROY is not set > > # CONFIG_TCP_CONG_ADVANCED is not set > > CONFIG_TCP_CONG_CUBIC=y > > CONFIG_DEFAULT_TCP_CONG="cubic" > > # CONFIG_TCP_MD5SIG is not set > > CONFIG_IPV6=y > > CONFIG_IPV6_ROUTER_PREF=y > > CONFIG_IPV6_ROUTE_INFO=y > > CONFIG_IPV6_OPTIMISTIC_DAD=y > > CONFIG_INET6_AH=y > > CONFIG_INET6_ESP=y > > # CONFIG_INET6_ESP_OFFLOAD is not set > > CONFIG_INET6_IPCOMP=y > > CONFIG_IPV6_MIP6=y > > CONFIG_INET6_XFRM_TUNNEL=y > > CONFIG_INET6_TUNNEL=y > > # CONFIG_IPV6_VTI is not set > > # CONFIG_IPV6_SIT is not set > > # CONFIG_IPV6_TUNNEL is not set > > CONFIG_IPV6_MULTIPLE_TABLES=y > > CONFIG_IPV6_SUBTREES=y > > # CONFIG_IPV6_MROUTE is not set > > # CONFIG_IPV6_SEG6_LWTUNNEL is not set > > # CONFIG_IPV6_SEG6_HMAC is not set > > # CONFIG_IPV6_RPL_LWTUNNEL is not set > > CONFIG_NETLABEL=y > > # CONFIG_MPTCP is not set > > CONFIG_NETWORK_SECMARK=y > > CONFIG_NET_PTP_CLASSIFY=y > > # CONFIG_NETWORK_PHY_TIMESTAMPING is not set > > # CONFIG_NETFILTER is not set > > # CONFIG_BPFILTER is not set > > # CONFIG_IP_DCCP is not set > > CONFIG_IP_SCTP=y > > # CONFIG_SCTP_DBG_OBJCNT is not set > > CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y > > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set > > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set > > CONFIG_SCTP_COOKIE_HMAC_MD5=y > > # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set > > CONFIG_INET_SCTP_DIAG=y > > CONFIG_RDS=y > > CONFIG_RDS_TCP=m > > # CONFIG_RDS_DEBUG is not set > > # CONFIG_TIPC is not set > > # CONFIG_ATM is not set > > # CONFIG_L2TP is not set > > CONFIG_STP=y > > CONFIG_BRIDGE=y > > CONFIG_BRIDGE_IGMP_SNOOPING=y > > CONFIG_HAVE_NET_DSA=y > > # CONFIG_NET_DSA is not set > > # CONFIG_VLAN_8021Q is not set > > # CONFIG_DECNET is not set > > CONFIG_LLC=y > > # CONFIG_LLC2 is not set > > # CONFIG_ATALK is not set > > # CONFIG_X25 is not set > > # CONFIG_LAPB is not set > > # CONFIG_PHONET is not set > > # CONFIG_6LOWPAN is not set > > # CONFIG_IEEE802154 is not set > > # CONFIG_NET_SCHED is not set > > # CONFIG_DCB is not set > > CONFIG_DNS_RESOLVER=y > > # CONFIG_BATMAN_ADV is not set > > # CONFIG_OPENVSWITCH is not set > > # CONFIG_VSOCKETS is not set > > CONFIG_NETLINK_DIAG=y > > # CONFIG_MPLS is not set > > # CONFIG_NET_NSH is not set > > # CONFIG_HSR is not set > > # CONFIG_NET_SWITCHDEV is not set > > # CONFIG_NET_L3_MASTER_DEV is not set > > # CONFIG_NET_NCSI is not set > > CONFIG_RPS=y > > CONFIG_RFS_ACCEL=y > > CONFIG_XPS=y > > CONFIG_CGROUP_NET_PRIO=y > > CONFIG_CGROUP_NET_CLASSID=y > > CONFIG_NET_RX_BUSY_POLL=y > > CONFIG_BQL=y > > # CONFIG_BPF_JIT is not set > > CONFIG_NET_FLOW_LIMIT=y > > > > # > > # Network testing > > # > > # CONFIG_NET_PKTGEN is not set > > # CONFIG_NET_DROP_MONITOR is not set > > # end of Network testing > > # end of Networking options > > > > # CONFIG_HAMRADIO is not set > > # CONFIG_CAN is not set > > # CONFIG_BT is not set > > CONFIG_AF_RXRPC=y > > CONFIG_AF_RXRPC_IPV6=y > > # CONFIG_AF_RXRPC_INJECT_LOSS is not set > > CONFIG_AF_RXRPC_DEBUG=y > > CONFIG_RXKAD=y > > # CONFIG_AF_KCM is not set > > CONFIG_FIB_RULES=y > > # CONFIG_WIRELESS is not set > > # CONFIG_WIMAX is not set > > # CONFIG_RFKILL is not set > > # CONFIG_NET_9P is not set > > # CONFIG_CAIF is not set > > CONFIG_CEPH_LIB=m > > # CONFIG_CEPH_LIB_PRETTYDEBUG is not set > > CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y > > # CONFIG_NFC is not set > > # CONFIG_PSAMPLE is not set > > # CONFIG_NET_IFE is not set > > # CONFIG_LWTUNNEL is not set > > CONFIG_GRO_CELLS=y > > # CONFIG_FAILOVER is not set > > CONFIG_ETHTOOL_NETLINK=y > > CONFIG_HAVE_EBPF_JIT=y > > > > # > > # Device Drivers > > # > > CONFIG_HAVE_EISA=y > > # CONFIG_EISA is not set > > CONFIG_HAVE_PCI=y > > CONFIG_PCI=y > > CONFIG_PCI_DOMAINS=y > > CONFIG_PCIEPORTBUS=y > > CONFIG_PCIEAER=y > > # CONFIG_PCIEAER_INJECT is not set > > # CONFIG_PCIE_ECRC is not set > > CONFIG_PCIEASPM=y > > CONFIG_PCIEASPM_DEFAULT=y > > # CONFIG_PCIEASPM_POWERSAVE is not set > > # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set > > # CONFIG_PCIEASPM_PERFORMANCE is not set > > CONFIG_PCIE_PME=y > > # CONFIG_PCIE_DPC is not set > > # CONFIG_PCIE_PTM is not set > > # CONFIG_PCIE_BW is not set > > CONFIG_PCI_MSI=y > > CONFIG_PCI_MSI_IRQ_DOMAIN=y > > CONFIG_PCI_QUIRKS=y > > # CONFIG_PCI_DEBUG is not set > > # CONFIG_PCI_STUB is not set > > CONFIG_PCI_ATS=y > > CONFIG_PCI_LOCKLESS_CONFIG=y > > # CONFIG_PCI_IOV is not set > > CONFIG_PCI_PRI=y > > CONFIG_PCI_PASID=y > > CONFIG_PCI_LABEL=y > > # CONFIG_HOTPLUG_PCI is not set > > > > # > > # PCI controller drivers > > # > > # CONFIG_VMD is not set > > > > # > > # DesignWare PCI Core Support > > # > > # CONFIG_PCIE_DW_PLAT_HOST is not set > > # CONFIG_PCI_MESON is not set > > # end of DesignWare PCI Core Support > > > > # > > # Mobiveil PCIe Core Support > > # > > # end of Mobiveil PCIe Core Support > > > > # > > # Cadence PCIe controllers support > > # > > # end of Cadence PCIe controllers support > > # end of PCI controller drivers > > > > # > > # PCI Endpoint > > # > > # CONFIG_PCI_ENDPOINT is not set > > # end of PCI Endpoint > > > > # > > # PCI switch controller drivers > > # > > # CONFIG_PCI_SW_SWITCHTEC is not set > > # end of PCI switch controller drivers > > > > # CONFIG_PCCARD is not set > > # CONFIG_RAPIDIO is not set > > > > # > > # Generic Driver Options > > # > > CONFIG_UEVENT_HELPER=y > > CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" > > CONFIG_DEVTMPFS=y > > CONFIG_DEVTMPFS_MOUNT=y > > CONFIG_STANDALONE=y > > CONFIG_PREVENT_FIRMWARE_BUILD=y > > > > # > > # Firmware loader > > # > > CONFIG_FW_LOADER=y > > CONFIG_FW_LOADER_PAGED_BUF=y > > CONFIG_EXTRA_FIRMWARE="" > > # CONFIG_FW_LOADER_USER_HELPER is not set > > CONFIG_FW_LOADER_COMPRESS=y > > # end of Firmware loader > > > > CONFIG_ALLOW_DEV_COREDUMP=y > > # CONFIG_DEBUG_DRIVER is not set > > # CONFIG_DEBUG_DEVRES is not set > > # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set > > # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set > > CONFIG_GENERIC_CPU_AUTOPROBE=y > > CONFIG_GENERIC_CPU_VULNERABILITIES=y > > CONFIG_DMA_SHARED_BUFFER=y > > # CONFIG_DMA_FENCE_TRACE is not set > > # end of Generic Driver Options > > > > # > > # Bus devices > > # > > # CONFIG_MHI_BUS is not set > > # end of Bus devices > > > > # CONFIG_CONNECTOR is not set > > # CONFIG_GNSS is not set > > # CONFIG_MTD is not set > > # CONFIG_OF is not set > > CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y > > # CONFIG_PARPORT is not set > > CONFIG_PNP=y > > # CONFIG_PNP_DEBUG_MESSAGES is not set > > > > # > > # Protocols > > # > > CONFIG_PNPACPI=y > > CONFIG_BLK_DEV=y > > # CONFIG_BLK_DEV_NULL_BLK is not set > > # CONFIG_BLK_DEV_FD is not set > > # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set > > # CONFIG_ZRAM is not set > > # CONFIG_BLK_DEV_UMEM is not set > > CONFIG_BLK_DEV_LOOP=y > > CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 > > # CONFIG_BLK_DEV_CRYPTOLOOP is not set > > # CONFIG_BLK_DEV_DRBD is not set > > # CONFIG_BLK_DEV_NBD is not set > > # CONFIG_BLK_DEV_SKD is not set > > # CONFIG_BLK_DEV_SX8 is not set > > # CONFIG_BLK_DEV_RAM is not set > > # CONFIG_CDROM_PKTCDVD is not set > > # CONFIG_ATA_OVER_ETH is not set > > CONFIG_BLK_DEV_RBD=m > > # CONFIG_BLK_DEV_RSXX is not set > > > > # > > # NVME Support > > # > > # CONFIG_BLK_DEV_NVME is not set > > # CONFIG_NVME_FC is not set > > # CONFIG_NVME_TARGET is not set > > # end of NVME Support > > > > # > > # Misc devices > > # > > # CONFIG_AD525X_DPOT is not set > > # CONFIG_DUMMY_IRQ is not set > > # CONFIG_IBM_ASM is not set > > # CONFIG_PHANTOM is not set > > # CONFIG_TIFM_CORE is not set > > # CONFIG_ICS932S401 is not set > > CONFIG_ENCLOSURE_SERVICES=y > > # CONFIG_HP_ILO is not set > > # CONFIG_APDS9802ALS is not set > > # CONFIG_ISL29003 is not set > > # CONFIG_ISL29020 is not set > > # CONFIG_SENSORS_TSL2550 is not set > > # CONFIG_SENSORS_BH1770 is not set > > # CONFIG_SENSORS_APDS990X is not set > > # CONFIG_HMC6352 is not set > > # CONFIG_DS1682 is not set > > # CONFIG_SRAM is not set > > # CONFIG_PCI_ENDPOINT_TEST is not set > > # CONFIG_XILINX_SDFEC is not set > > # CONFIG_PVPANIC is not set > > CONFIG_C2PORT=m > > # CONFIG_C2PORT_DURAMAR_2150 is not set > > > > # > > # EEPROM support > > # > > # CONFIG_EEPROM_AT24 is not set > > # CONFIG_EEPROM_LEGACY is not set > > # CONFIG_EEPROM_MAX6875 is not set > > # CONFIG_EEPROM_93CX6 is not set > > # CONFIG_EEPROM_IDT_89HPESX is not set > > # CONFIG_EEPROM_EE1004 is not set > > # end of EEPROM support > > > > # CONFIG_CB710_CORE is not set > > > > # > > # Texas Instruments shared transport line discipline > > # > > # end of Texas Instruments shared transport line discipline > > > > # CONFIG_SENSORS_LIS3_I2C is not set > > # CONFIG_ALTERA_STAPL is not set > > CONFIG_INTEL_MEI=y > > CONFIG_INTEL_MEI_ME=y > > # CONFIG_INTEL_MEI_TXE is not set > > # CONFIG_INTEL_MEI_HDCP is not set > > # CONFIG_VMWARE_VMCI is not set > > > > # > > # Intel MIC & related support > > # > > # CONFIG_INTEL_MIC_BUS is not set > > # CONFIG_SCIF_BUS is not set > > # CONFIG_VOP_BUS is not set > > # end of Intel MIC & related support > > > > # CONFIG_GENWQE is not set > > # CONFIG_ECHO is not set > > # CONFIG_MISC_ALCOR_PCI is not set > > # CONFIG_MISC_RTSX_PCI is not set > > # CONFIG_MISC_RTSX_USB is not set > > # CONFIG_HABANA_AI is not set > > # CONFIG_UACCE is not set > > # end of Misc devices > > > > CONFIG_HAVE_IDE=y > > # CONFIG_IDE is not set > > > > # > > # SCSI device support > > # > > CONFIG_SCSI_MOD=y > > # CONFIG_RAID_ATTRS is not set > > CONFIG_SCSI=y > > CONFIG_SCSI_DMA=y > > CONFIG_SCSI_PROC_FS=y > > > > # > > # SCSI support type (disk, tape, CD-ROM) > > # > > CONFIG_BLK_DEV_SD=y > > # CONFIG_CHR_DEV_ST is not set > > # CONFIG_BLK_DEV_SR is not set > > CONFIG_CHR_DEV_SG=y > > # CONFIG_CHR_DEV_SCH is not set > > # CONFIG_SCSI_ENCLOSURE is not set > > CONFIG_SCSI_CONSTANTS=y > > # CONFIG_SCSI_LOGGING is not set > > # CONFIG_SCSI_SCAN_ASYNC is not set > > > > # > > # SCSI Transports > > # > > CONFIG_SCSI_SPI_ATTRS=y > > # CONFIG_SCSI_FC_ATTRS is not set > > # CONFIG_SCSI_ISCSI_ATTRS is not set > > # CONFIG_SCSI_SAS_ATTRS is not set > > # CONFIG_SCSI_SAS_LIBSAS is not set > > # CONFIG_SCSI_SRP_ATTRS is not set > > # end of SCSI Transports > > > > # CONFIG_SCSI_LOWLEVEL is not set > > # CONFIG_SCSI_DH is not set > > # end of SCSI device support > > > > CONFIG_ATA=y > > CONFIG_SATA_HOST=y > > CONFIG_PATA_TIMINGS=y > > CONFIG_ATA_VERBOSE_ERROR=y > > CONFIG_ATA_FORCE=y > > CONFIG_ATA_ACPI=y > > # CONFIG_SATA_ZPODD is not set > > # CONFIG_SATA_PMP is not set > > > > # > > # Controllers with non-SFF native interface > > # > > CONFIG_SATA_AHCI=y > > CONFIG_SATA_MOBILE_LPM_POLICY=0 > > CONFIG_SATA_AHCI_PLATFORM=y > > # CONFIG_SATA_INIC162X is not set > > # CONFIG_SATA_ACARD_AHCI is not set > > # CONFIG_SATA_SIL24 is not set > > # CONFIG_ATA_SFF is not set > > CONFIG_MD=y > > # CONFIG_BLK_DEV_MD is not set > > # CONFIG_BCACHE is not set > > CONFIG_BLK_DEV_DM_BUILTIN=y > > CONFIG_BLK_DEV_DM=y > > # CONFIG_DM_DEBUG is not set > > # CONFIG_DM_UNSTRIPED is not set > > # CONFIG_DM_CRYPT is not set > > # CONFIG_DM_SNAPSHOT is not set > > # CONFIG_DM_THIN_PROVISIONING is not set > > # CONFIG_DM_CACHE is not set > > # CONFIG_DM_WRITECACHE is not set > > # CONFIG_DM_ERA is not set > > # CONFIG_DM_CLONE is not set > > # CONFIG_DM_MIRROR is not set > > # CONFIG_DM_RAID is not set > > # CONFIG_DM_ZERO is not set > > # CONFIG_DM_MULTIPATH is not set > > # CONFIG_DM_DELAY is not set > > # CONFIG_DM_DUST is not set > > # CONFIG_DM_INIT is not set > > CONFIG_DM_UEVENT=y > > # CONFIG_DM_FLAKEY is not set > > # CONFIG_DM_VERITY is not set > > # CONFIG_DM_SWITCH is not set > > # CONFIG_DM_LOG_WRITES is not set > > # CONFIG_DM_INTEGRITY is not set > > # CONFIG_TARGET_CORE is not set > > # CONFIG_FUSION is not set > > > > # > > # IEEE 1394 (FireWire) support > > # > > # CONFIG_FIREWIRE is not set > > # CONFIG_FIREWIRE_NOSY is not set > > # end of IEEE 1394 (FireWire) support > > > > # CONFIG_MACINTOSH_DRIVERS is not set > > CONFIG_NETDEVICES=y > > CONFIG_NET_CORE=y > > # CONFIG_BONDING is not set > > # CONFIG_DUMMY is not set > > # CONFIG_WIREGUARD is not set > > # CONFIG_EQUALIZER is not set > > # CONFIG_NET_FC is not set > > # CONFIG_NET_TEAM is not set > > # CONFIG_MACVLAN is not set > > # CONFIG_IPVLAN is not set > > # CONFIG_VXLAN is not set > > # CONFIG_GENEVE is not set > > # CONFIG_BAREUDP is not set > > # CONFIG_GTP is not set > > # CONFIG_MACSEC is not set > > # CONFIG_NETCONSOLE is not set > > CONFIG_TUN=y > > # CONFIG_TUN_VNET_CROSS_LE is not set > > CONFIG_VETH=y > > # CONFIG_NLMON is not set > > # CONFIG_ARCNET is not set > > > > # > > # Distributed Switch Architecture drivers > > # > > # end of Distributed Switch Architecture drivers > > > > CONFIG_ETHERNET=y > > CONFIG_MDIO=y > > # CONFIG_NET_VENDOR_3COM is not set > > # CONFIG_NET_VENDOR_ADAPTEC is not set > > # CONFIG_NET_VENDOR_AGERE is not set > > # CONFIG_NET_VENDOR_ALACRITECH is not set > > # CONFIG_NET_VENDOR_ALTEON is not set > > # CONFIG_ALTERA_TSE is not set > > # CONFIG_NET_VENDOR_AMAZON is not set > > # CONFIG_NET_VENDOR_AMD is not set > > # CONFIG_NET_VENDOR_AQUANTIA is not set > > # CONFIG_NET_VENDOR_ARC is not set > > # CONFIG_NET_VENDOR_ATHEROS is not set > > # CONFIG_NET_VENDOR_AURORA is not set > > # CONFIG_NET_VENDOR_BROADCOM is not set > > # CONFIG_NET_VENDOR_BROCADE is not set > > # CONFIG_NET_VENDOR_CADENCE is not set > > # CONFIG_NET_VENDOR_CAVIUM is not set > > # CONFIG_NET_VENDOR_CHELSIO is not set > > # CONFIG_NET_VENDOR_CISCO is not set > > # CONFIG_NET_VENDOR_CORTINA is not set > > # CONFIG_CX_ECAT is not set > > # CONFIG_DNET is not set > > # CONFIG_NET_VENDOR_DEC is not set > > # CONFIG_NET_VENDOR_DLINK is not set > > # CONFIG_NET_VENDOR_EMULEX is not set > > # CONFIG_NET_VENDOR_EZCHIP is not set > > # CONFIG_NET_VENDOR_GOOGLE is not set > > # CONFIG_NET_VENDOR_HUAWEI is not set > > CONFIG_NET_VENDOR_I825XX=y > > CONFIG_NET_VENDOR_INTEL=y > > # CONFIG_E100 is not set > > # CONFIG_E1000 is not set > > # CONFIG_E1000E is not set > > # CONFIG_IGB is not set > > # CONFIG_IGBVF is not set > > # CONFIG_IXGB is not set > > CONFIG_IXGBE=y > > CONFIG_IXGBE_HWMON=y > > # CONFIG_IXGBEVF is not set > > # CONFIG_I40E is not set > > # CONFIG_I40EVF is not set > > # CONFIG_ICE is not set > > # CONFIG_FM10K is not set > > # CONFIG_IGC is not set > > # CONFIG_JME is not set > > # CONFIG_NET_VENDOR_MARVELL is not set > > # CONFIG_NET_VENDOR_MELLANOX is not set > > # CONFIG_NET_VENDOR_MICREL is not set > > # CONFIG_NET_VENDOR_MICROCHIP is not set > > # CONFIG_NET_VENDOR_MICROSEMI is not set > > # CONFIG_NET_VENDOR_MYRI is not set > > # CONFIG_FEALNX is not set > > # CONFIG_NET_VENDOR_NATSEMI is not set > > # CONFIG_NET_VENDOR_NETERION is not set > > # CONFIG_NET_VENDOR_NETRONOME is not set > > # CONFIG_NET_VENDOR_NI is not set > > # CONFIG_NET_VENDOR_NVIDIA is not set > > # CONFIG_NET_VENDOR_OKI is not set > > # CONFIG_ETHOC is not set > > # CONFIG_NET_VENDOR_PACKET_ENGINES is not set > > # CONFIG_NET_VENDOR_PENSANDO is not set > > # CONFIG_NET_VENDOR_QLOGIC is not set > > # CONFIG_NET_VENDOR_QUALCOMM is not set > > # CONFIG_NET_VENDOR_RDC is not set > > CONFIG_NET_VENDOR_REALTEK=y > > # CONFIG_8139CP is not set > > # CONFIG_8139TOO is not set > > CONFIG_R8169=y > > # CONFIG_NET_VENDOR_RENESAS is not set > > # CONFIG_NET_VENDOR_ROCKER is not set > > # CONFIG_NET_VENDOR_SAMSUNG is not set > > # CONFIG_NET_VENDOR_SEEQ is not set > > # CONFIG_NET_VENDOR_SOLARFLARE is not set > > # CONFIG_NET_VENDOR_SILAN is not set > > # CONFIG_NET_VENDOR_SIS is not set > > # CONFIG_NET_VENDOR_SMSC is not set > > # CONFIG_NET_VENDOR_SOCIONEXT is not set > > # CONFIG_NET_VENDOR_STMICRO is not set > > # CONFIG_NET_VENDOR_SUN is not set > > # CONFIG_NET_VENDOR_SYNOPSYS is not set > > # CONFIG_NET_VENDOR_TEHUTI is not set > > # CONFIG_NET_VENDOR_TI is not set > > # CONFIG_NET_VENDOR_VIA is not set > > # CONFIG_NET_VENDOR_WIZNET is not set > > # CONFIG_NET_VENDOR_XILINX is not set > > # CONFIG_FDDI is not set > > # CONFIG_HIPPI is not set > > # CONFIG_NET_SB1000 is not set > > CONFIG_MDIO_DEVICE=y > > CONFIG_MDIO_BUS=y > > # CONFIG_MDIO_BCM_UNIMAC is not set > > # CONFIG_MDIO_BITBANG is not set > > # CONFIG_MDIO_MSCC_MIIM is not set > > # CONFIG_MDIO_MVUSB is not set > > # CONFIG_MDIO_THUNDER is not set > > # CONFIG_MDIO_XPCS is not set > > CONFIG_PHYLIB=y > > > > # > > # MII PHY device drivers > > # > > # CONFIG_ADIN_PHY is not set > > # CONFIG_AMD_PHY is not set > > # CONFIG_AQUANTIA_PHY is not set > > # CONFIG_AX88796B_PHY is not set > > # CONFIG_BCM7XXX_PHY is not set > > # CONFIG_BCM87XX_PHY is not set > > # CONFIG_BROADCOM_PHY is not set > > # CONFIG_BCM84881_PHY is not set > > # CONFIG_CICADA_PHY is not set > > # CONFIG_CORTINA_PHY is not set > > # CONFIG_DAVICOM_PHY is not set > > # CONFIG_DP83822_PHY is not set > > # CONFIG_DP83TC811_PHY is not set > > # CONFIG_DP83848_PHY is not set > > # CONFIG_DP83867_PHY is not set > > # CONFIG_DP83869_PHY is not set > > # CONFIG_FIXED_PHY is not set > > # CONFIG_ICPLUS_PHY is not set > > # CONFIG_INTEL_XWAY_PHY is not set > > # CONFIG_LSI_ET1011C_PHY is not set > > # CONFIG_LXT_PHY is not set > > # CONFIG_MARVELL_PHY is not set > > # CONFIG_MARVELL_10G_PHY is not set > > # CONFIG_MICREL_PHY is not set > > # CONFIG_MICROCHIP_PHY is not set > > # CONFIG_MICROCHIP_T1_PHY is not set > > # CONFIG_MICROSEMI_PHY is not set > > # CONFIG_NATIONAL_PHY is not set > > # CONFIG_NXP_TJA11XX_PHY is not set > > # CONFIG_QSEMI_PHY is not set > > CONFIG_REALTEK_PHY=y > > # CONFIG_RENESAS_PHY is not set > > # CONFIG_ROCKCHIP_PHY is not set > > # CONFIG_SMSC_PHY is not set > > # CONFIG_STE10XP is not set > > # CONFIG_TERANETICS_PHY is not set > > # CONFIG_VITESSE_PHY is not set > > # CONFIG_XILINX_GMII2RGMII is not set > > # CONFIG_PPP is not set > > # CONFIG_SLIP is not set > > # CONFIG_USB_NET_DRIVERS is not set > > # CONFIG_WLAN is not set > > > > # > > # Enable WiMAX (Networking options) to see the WiMAX drivers > > # > > # CONFIG_WAN is not set > > # CONFIG_VMXNET3 is not set > > # CONFIG_FUJITSU_ES is not set > > # CONFIG_NETDEVSIM is not set > > # CONFIG_NET_FAILOVER is not set > > # CONFIG_ISDN is not set > > # CONFIG_NVM is not set > > > > # > > # Input device support > > # > > CONFIG_INPUT=y > > # CONFIG_INPUT_FF_MEMLESS is not set > > # CONFIG_INPUT_POLLDEV is not set > > # CONFIG_INPUT_SPARSEKMAP is not set > > # CONFIG_INPUT_MATRIXKMAP is not set > > > > # > > # Userland interfaces > > # > > CONFIG_INPUT_MOUSEDEV=y > > CONFIG_INPUT_MOUSEDEV_PSAUX=y > > CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 > > CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 > > # CONFIG_INPUT_JOYDEV is not set > > CONFIG_INPUT_EVDEV=y > > # CONFIG_INPUT_EVBUG is not set > > > > # > > # Input Device Drivers > > # > > CONFIG_INPUT_KEYBOARD=y > > # CONFIG_KEYBOARD_ADP5588 is not set > > # CONFIG_KEYBOARD_ADP5589 is not set > > CONFIG_KEYBOARD_ATKBD=y > > # CONFIG_KEYBOARD_QT1050 is not set > > # CONFIG_KEYBOARD_QT1070 is not set > > # CONFIG_KEYBOARD_QT2160 is not set > > # CONFIG_KEYBOARD_DLINK_DIR685 is not set > > # CONFIG_KEYBOARD_LKKBD is not set > > # CONFIG_KEYBOARD_TCA6416 is not set > > # CONFIG_KEYBOARD_TCA8418 is not set > > # CONFIG_KEYBOARD_LM8333 is not set > > # CONFIG_KEYBOARD_MAX7359 is not set > > # CONFIG_KEYBOARD_MCS is not set > > # CONFIG_KEYBOARD_MPR121 is not set > > # CONFIG_KEYBOARD_NEWTON is not set > > # CONFIG_KEYBOARD_OPENCORES is not set > > # CONFIG_KEYBOARD_SAMSUNG is not set > > # CONFIG_KEYBOARD_STOWAWAY is not set > > # CONFIG_KEYBOARD_SUNKBD is not set > > # CONFIG_KEYBOARD_XTKBD is not set > > CONFIG_INPUT_MOUSE=y > > CONFIG_MOUSE_PS2=y > > # CONFIG_MOUSE_PS2_ALPS is not set > > # CONFIG_MOUSE_PS2_BYD is not set > > # CONFIG_MOUSE_PS2_LOGIPS2PP is not set > > # CONFIG_MOUSE_PS2_SYNAPTICS is not set > > CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y > > # CONFIG_MOUSE_PS2_CYPRESS is not set > > # CONFIG_MOUSE_PS2_LIFEBOOK is not set > > # CONFIG_MOUSE_PS2_TRACKPOINT is not set > > # CONFIG_MOUSE_PS2_ELANTECH is not set > > # CONFIG_MOUSE_PS2_SENTELIC is not set > > # CONFIG_MOUSE_PS2_TOUCHKIT is not set > > # CONFIG_MOUSE_PS2_FOCALTECH is not set > > CONFIG_MOUSE_PS2_SMBUS=y > > # CONFIG_MOUSE_SERIAL is not set > > # CONFIG_MOUSE_APPLETOUCH is not set > > # CONFIG_MOUSE_BCM5974 is not set > > # CONFIG_MOUSE_CYAPA is not set > > # CONFIG_MOUSE_ELAN_I2C is not set > > # CONFIG_MOUSE_VSXXXAA is not set > > # CONFIG_MOUSE_SYNAPTICS_I2C is not set > > # CONFIG_MOUSE_SYNAPTICS_USB is not set > > # CONFIG_INPUT_JOYSTICK is not set > > # CONFIG_INPUT_TABLET is not set > > # CONFIG_INPUT_TOUCHSCREEN is not set > > # CONFIG_INPUT_MISC is not set > > # CONFIG_RMI4_CORE is not set > > > > # > > # Hardware I/O ports > > # > > CONFIG_SERIO=y > > CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y > > CONFIG_SERIO_I8042=y > > # CONFIG_SERIO_SERPORT is not set > > # CONFIG_SERIO_CT82C710 is not set > > # CONFIG_SERIO_PCIPS2 is not set > > CONFIG_SERIO_LIBPS2=y > > # CONFIG_SERIO_RAW is not set > > # CONFIG_SERIO_ALTERA_PS2 is not set > > # CONFIG_SERIO_PS2MULT is not set > > # CONFIG_SERIO_ARC_PS2 is not set > > # CONFIG_USERIO is not set > > # CONFIG_GAMEPORT is not set > > # end of Hardware I/O ports > > # end of Input device support > > > > # > > # Character devices > > # > > CONFIG_TTY=y > > CONFIG_VT=y > > CONFIG_CONSOLE_TRANSLATIONS=y > > CONFIG_VT_CONSOLE=y > > CONFIG_HW_CONSOLE=y > > # CONFIG_VT_HW_CONSOLE_BINDING is not set > > CONFIG_UNIX98_PTYS=y > > CONFIG_LEGACY_PTYS=y > > CONFIG_LEGACY_PTY_COUNT=256 > > CONFIG_LDISC_AUTOLOAD=y > > > > # > > # Serial drivers > > # > > CONFIG_SERIAL_EARLYCON=y > > CONFIG_SERIAL_8250=y > > CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y > > CONFIG_SERIAL_8250_PNP=y > > # CONFIG_SERIAL_8250_16550A_VARIANTS is not set > > # CONFIG_SERIAL_8250_FINTEK is not set > > CONFIG_SERIAL_8250_CONSOLE=y > > CONFIG_SERIAL_8250_PCI=y > > # CONFIG_SERIAL_8250_EXAR is not set > > CONFIG_SERIAL_8250_NR_UARTS=4 > > CONFIG_SERIAL_8250_RUNTIME_UARTS=4 > > CONFIG_SERIAL_8250_EXTENDED=y > > # CONFIG_SERIAL_8250_MANY_PORTS is not set > > CONFIG_SERIAL_8250_SHARE_IRQ=y > > # CONFIG_SERIAL_8250_DETECT_IRQ is not set > > # CONFIG_SERIAL_8250_RSA is not set > > CONFIG_SERIAL_8250_DWLIB=y > > # CONFIG_SERIAL_8250_DW is not set > > # CONFIG_SERIAL_8250_RT288X is not set > > CONFIG_SERIAL_8250_LPSS=y > > CONFIG_SERIAL_8250_MID=y > > > > # > > # Non-8250 serial port support > > # > > # CONFIG_SERIAL_UARTLITE is not set > > CONFIG_SERIAL_CORE=y > > CONFIG_SERIAL_CORE_CONSOLE=y > > # CONFIG_SERIAL_JSM is not set > > # CONFIG_SERIAL_SCCNXP is not set > > # CONFIG_SERIAL_SC16IS7XX is not set > > # CONFIG_SERIAL_ALTERA_JTAGUART is not set > > # CONFIG_SERIAL_ALTERA_UART is not set > > # CONFIG_SERIAL_ARC is not set > > # CONFIG_SERIAL_RP2 is not set > > # CONFIG_SERIAL_FSL_LPUART is not set > > # CONFIG_SERIAL_FSL_LINFLEXUART is not set > > # CONFIG_SERIAL_SPRD is not set > > # end of Serial drivers > > > > # CONFIG_SERIAL_NONSTANDARD is not set > > # CONFIG_N_GSM is not set > > # CONFIG_NOZOMI is not set > > # CONFIG_NULL_TTY is not set > > # CONFIG_TRACE_SINK is not set > > # CONFIG_SERIAL_DEV_BUS is not set > > # CONFIG_TTY_PRINTK is not set > > CONFIG_IPMI_HANDLER=y > > CONFIG_IPMI_DMI_DECODE=y > > CONFIG_IPMI_PLAT_DATA=y > > # CONFIG_IPMI_PANIC_EVENT is not set > > CONFIG_IPMI_DEVICE_INTERFACE=y > > CONFIG_IPMI_SI=y > > CONFIG_IPMI_SSIF=y > > # CONFIG_IPMI_WATCHDOG is not set > > # CONFIG_IPMI_POWEROFF is not set > > # CONFIG_HW_RANDOM is not set > > # CONFIG_APPLICOM is not set > > # CONFIG_MWAVE is not set > > # CONFIG_DEVMEM is not set > > CONFIG_DEVKMEM=y > > # CONFIG_NVRAM is not set > > # CONFIG_RAW_DRIVER is not set > > CONFIG_DEVPORT=y > > CONFIG_HPET=y > > CONFIG_HPET_MMAP=y > > CONFIG_HPET_MMAP_DEFAULT=y > > # CONFIG_HANGCHECK_TIMER is not set > > CONFIG_TCG_TPM=y > > # CONFIG_TCG_TIS is not set > > # CONFIG_TCG_TIS_I2C_ATMEL is not set > > # CONFIG_TCG_TIS_I2C_INFINEON is not set > > # CONFIG_TCG_TIS_I2C_NUVOTON is not set > > # CONFIG_TCG_NSC is not set > > # CONFIG_TCG_ATMEL is not set > > # CONFIG_TCG_INFINEON is not set > > # CONFIG_TCG_CRB is not set > > CONFIG_TCG_VTPM_PROXY=y > > # CONFIG_TCG_TIS_ST33ZP24_I2C is not set > > # CONFIG_TELCLOCK is not set > > # CONFIG_XILLYBUS is not set > > # end of Character devices > > > > # CONFIG_RANDOM_TRUST_CPU is not set > > # CONFIG_RANDOM_TRUST_BOOTLOADER is not set > > > > # > > # I2C support > > # > > CONFIG_I2C=y > > CONFIG_ACPI_I2C_OPREGION=y > > CONFIG_I2C_BOARDINFO=y > > CONFIG_I2C_COMPAT=y > > CONFIG_I2C_CHARDEV=y > > CONFIG_I2C_MUX=y > > > > # > > # Multiplexer I2C Chip support > > # > > # CONFIG_I2C_MUX_LTC4306 is not set > > # CONFIG_I2C_MUX_PCA9541 is not set > > # CONFIG_I2C_MUX_REG is not set > > # CONFIG_I2C_MUX_MLXCPLD is not set > > # end of Multiplexer I2C Chip support > > > > CONFIG_I2C_HELPER_AUTO=y > > CONFIG_I2C_SMBUS=y > > CONFIG_I2C_ALGOBIT=y > > > > # > > # I2C Hardware Bus support > > # > > > > # > > # PC SMBus host controller drivers > > # > > # CONFIG_I2C_ALI1535 is not set > > # CONFIG_I2C_ALI1563 is not set > > # CONFIG_I2C_ALI15X3 is not set > > # CONFIG_I2C_AMD756 is not set > > # CONFIG_I2C_AMD8111 is not set > > # CONFIG_I2C_AMD_MP2 is not set > > CONFIG_I2C_I801=y > > # CONFIG_I2C_ISCH is not set > > # CONFIG_I2C_ISMT is not set > > # CONFIG_I2C_PIIX4 is not set > > # CONFIG_I2C_NFORCE2 is not set > > # CONFIG_I2C_NVIDIA_GPU is not set > > # CONFIG_I2C_SIS5595 is not set > > # CONFIG_I2C_SIS630 is not set > > # CONFIG_I2C_SIS96X is not set > > # CONFIG_I2C_VIA is not set > > # CONFIG_I2C_VIAPRO is not set > > > > # > > # ACPI drivers > > # > > CONFIG_I2C_SCMI=y > > > > # > > # I2C system bus drivers (mostly embedded / system-on-chip) > > # > > # CONFIG_I2C_DESIGNWARE_PLATFORM is not set > > # CONFIG_I2C_DESIGNWARE_PCI is not set > > # CONFIG_I2C_EMEV2 is not set > > # CONFIG_I2C_OCORES is not set > > # CONFIG_I2C_PCA_PLATFORM is not set > > # CONFIG_I2C_SIMTEC is not set > > # CONFIG_I2C_XILINX is not set > > > > # > > # External I2C/SMBus adapter drivers > > # > > # CONFIG_I2C_DIOLAN_U2C is not set > > # CONFIG_I2C_ROBOTFUZZ_OSIF is not set > > # CONFIG_I2C_TAOS_EVM is not set > > # CONFIG_I2C_TINY_USB is not set > > > > # > > # Other I2C/SMBus bus drivers > > # > > # CONFIG_I2C_MLXCPLD is not set > > # end of I2C Hardware Bus support > > > > # CONFIG_I2C_STUB is not set > > # CONFIG_I2C_SLAVE is not set > > # CONFIG_I2C_DEBUG_CORE is not set > > # CONFIG_I2C_DEBUG_ALGO is not set > > # CONFIG_I2C_DEBUG_BUS is not set > > # end of I2C support > > > > # CONFIG_I3C is not set > > # CONFIG_SPI is not set > > # CONFIG_SPMI is not set > > # CONFIG_HSI is not set > > CONFIG_PPS=y > > # CONFIG_PPS_DEBUG is not set > > > > # > > # PPS clients support > > # > > # CONFIG_PPS_CLIENT_KTIMER is not set > > # CONFIG_PPS_CLIENT_LDISC is not set > > # CONFIG_PPS_CLIENT_GPIO is not set > > > > # > > # PPS generators support > > # > > > > # > > # PTP clock support > > # > > CONFIG_PTP_1588_CLOCK=y > > > > # > > # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. > > # > > # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set > > # CONFIG_PTP_1588_CLOCK_IDTCM is not set > > # end of PTP clock support > > > > # CONFIG_PINCTRL is not set > > # CONFIG_GPIOLIB is not set > > # CONFIG_W1 is not set > > # CONFIG_POWER_AVS is not set > > # CONFIG_POWER_RESET is not set > > CONFIG_POWER_SUPPLY=y > > # CONFIG_POWER_SUPPLY_DEBUG is not set > > CONFIG_POWER_SUPPLY_HWMON=y > > # CONFIG_PDA_POWER is not set > > # CONFIG_TEST_POWER is not set > > # CONFIG_CHARGER_ADP5061 is not set > > # CONFIG_BATTERY_DS2780 is not set > > # CONFIG_BATTERY_DS2781 is not set > > # CONFIG_BATTERY_DS2782 is not set > > # CONFIG_BATTERY_SBS is not set > > # CONFIG_CHARGER_SBS is not set > > # CONFIG_BATTERY_BQ27XXX is not set > > # CONFIG_BATTERY_MAX17040 is not set > > # CONFIG_BATTERY_MAX17042 is not set > > # CONFIG_CHARGER_MAX8903 is not set > > # CONFIG_CHARGER_LP8727 is not set > > # CONFIG_CHARGER_BQ2415X is not set > > # CONFIG_CHARGER_SMB347 is not set > > # CONFIG_BATTERY_GAUGE_LTC2941 is not set > > CONFIG_HWMON=y > > # CONFIG_HWMON_DEBUG_CHIP is not set > > > > # > > # Native drivers > > # > > # CONFIG_SENSORS_ABITUGURU is not set > > # CONFIG_SENSORS_ABITUGURU3 is not set > > # CONFIG_SENSORS_AD7414 is not set > > # CONFIG_SENSORS_AD7418 is not set > > # CONFIG_SENSORS_ADM1021 is not set > > # CONFIG_SENSORS_ADM1025 is not set > > # CONFIG_SENSORS_ADM1026 is not set > > # CONFIG_SENSORS_ADM1029 is not set > > # CONFIG_SENSORS_ADM1031 is not set > > # CONFIG_SENSORS_ADM1177 is not set > > # CONFIG_SENSORS_ADM9240 is not set > > # CONFIG_SENSORS_ADT7410 is not set > > # CONFIG_SENSORS_ADT7411 is not set > > # CONFIG_SENSORS_ADT7462 is not set > > # CONFIG_SENSORS_ADT7470 is not set > > # CONFIG_SENSORS_ADT7475 is not set > > # CONFIG_SENSORS_AS370 is not set > > # CONFIG_SENSORS_ASC7621 is not set > > # CONFIG_SENSORS_AXI_FAN_CONTROL is not set > > # CONFIG_SENSORS_K8TEMP is not set > > # CONFIG_SENSORS_K10TEMP is not set > > # CONFIG_SENSORS_FAM15H_POWER is not set > > # CONFIG_SENSORS_APPLESMC is not set > > # CONFIG_SENSORS_ASB100 is not set > > # CONFIG_SENSORS_ASPEED is not set > > # CONFIG_SENSORS_ATXP1 is not set > > # CONFIG_SENSORS_DRIVETEMP is not set > > # CONFIG_SENSORS_DS620 is not set > > # CONFIG_SENSORS_DS1621 is not set > > # CONFIG_SENSORS_DELL_SMM is not set > > # CONFIG_SENSORS_I5K_AMB is not set > > # CONFIG_SENSORS_F71805F is not set > > # CONFIG_SENSORS_F71882FG is not set > > # CONFIG_SENSORS_F75375S is not set > > # CONFIG_SENSORS_FSCHMD is not set > > # CONFIG_SENSORS_FTSTEUTATES is not set > > # CONFIG_SENSORS_GL518SM is not set > > # CONFIG_SENSORS_GL520SM is not set > > # CONFIG_SENSORS_G760A is not set > > # CONFIG_SENSORS_G762 is not set > > # CONFIG_SENSORS_HIH6130 is not set > > # CONFIG_SENSORS_IBMAEM is not set > > # CONFIG_SENSORS_IBMPEX is not set > > # CONFIG_SENSORS_I5500 is not set > > CONFIG_SENSORS_CORETEMP=y > > # CONFIG_SENSORS_IT87 is not set > > # CONFIG_SENSORS_JC42 is not set > > # CONFIG_SENSORS_POWR1220 is not set > > # CONFIG_SENSORS_LINEAGE is not set > > # CONFIG_SENSORS_LTC2945 is not set > > # CONFIG_SENSORS_LTC2947_I2C is not set > > # CONFIG_SENSORS_LTC2990 is not set > > # CONFIG_SENSORS_LTC4151 is not set > > # CONFIG_SENSORS_LTC4215 is not set > > # CONFIG_SENSORS_LTC4222 is not set > > # CONFIG_SENSORS_LTC4245 is not set > > # CONFIG_SENSORS_LTC4260 is not set > > # CONFIG_SENSORS_LTC4261 is not set > > # CONFIG_SENSORS_MAX16065 is not set > > # CONFIG_SENSORS_MAX1619 is not set > > # CONFIG_SENSORS_MAX1668 is not set > > # CONFIG_SENSORS_MAX197 is not set > > # CONFIG_SENSORS_MAX31730 is not set > > # CONFIG_SENSORS_MAX6621 is not set > > # CONFIG_SENSORS_MAX6639 is not set > > # CONFIG_SENSORS_MAX6642 is not set > > # CONFIG_SENSORS_MAX6650 is not set > > # CONFIG_SENSORS_MAX6697 is not set > > # CONFIG_SENSORS_MAX31790 is not set > > # CONFIG_SENSORS_MCP3021 is not set > > # CONFIG_SENSORS_TC654 is not set > > # CONFIG_SENSORS_LM63 is not set > > # CONFIG_SENSORS_LM73 is not set > > # CONFIG_SENSORS_LM75 is not set > > # CONFIG_SENSORS_LM77 is not set > > # CONFIG_SENSORS_LM78 is not set > > # CONFIG_SENSORS_LM80 is not set > > # CONFIG_SENSORS_LM83 is not set > > # CONFIG_SENSORS_LM85 is not set > > # CONFIG_SENSORS_LM87 is not set > > # CONFIG_SENSORS_LM90 is not set > > # CONFIG_SENSORS_LM92 is not set > > # CONFIG_SENSORS_LM93 is not set > > # CONFIG_SENSORS_LM95234 is not set > > # CONFIG_SENSORS_LM95241 is not set > > # CONFIG_SENSORS_LM95245 is not set > > # CONFIG_SENSORS_PC87360 is not set > > # CONFIG_SENSORS_PC87427 is not set > > # CONFIG_SENSORS_NTC_THERMISTOR is not set > > # CONFIG_SENSORS_NCT6683 is not set > > # CONFIG_SENSORS_NCT6775 is not set > > # CONFIG_SENSORS_NCT7802 is not set > > # CONFIG_SENSORS_NCT7904 is not set > > # CONFIG_SENSORS_NPCM7XX is not set > > # CONFIG_SENSORS_PCF8591 is not set > > CONFIG_PMBUS=y > > CONFIG_SENSORS_PMBUS=y > > # CONFIG_SENSORS_ADM1275 is not set > > # CONFIG_SENSORS_BEL_PFE is not set > > # CONFIG_SENSORS_INSPUR_IPSPS is not set > > # CONFIG_SENSORS_IR35221 is not set > > # CONFIG_SENSORS_IR38064 is not set > > # CONFIG_SENSORS_IRPS5401 is not set > > # CONFIG_SENSORS_ISL68137 is not set > > # CONFIG_SENSORS_LM25066 is not set > > # CONFIG_SENSORS_LTC2978 is not set > > # CONFIG_SENSORS_LTC3815 is not set > > # CONFIG_SENSORS_MAX16064 is not set > > # CONFIG_SENSORS_MAX20730 is not set > > # CONFIG_SENSORS_MAX20751 is not set > > # CONFIG_SENSORS_MAX31785 is not set > > # CONFIG_SENSORS_MAX34440 is not set > > # CONFIG_SENSORS_MAX8688 is not set > > # CONFIG_SENSORS_PXE1610 is not set > > # CONFIG_SENSORS_TPS40422 is not set > > # CONFIG_SENSORS_TPS53679 is not set > > # CONFIG_SENSORS_UCD9000 is not set > > # CONFIG_SENSORS_UCD9200 is not set > > # CONFIG_SENSORS_XDPE122 is not set > > # CONFIG_SENSORS_ZL6100 is not set > > # CONFIG_SENSORS_SHT21 is not set > > # CONFIG_SENSORS_SHT3x is not set > > # CONFIG_SENSORS_SHTC1 is not set > > # CONFIG_SENSORS_SIS5595 is not set > > # CONFIG_SENSORS_DME1737 is not set > > # CONFIG_SENSORS_EMC1403 is not set > > # CONFIG_SENSORS_EMC2103 is not set > > # CONFIG_SENSORS_EMC6W201 is not set > > # CONFIG_SENSORS_SMSC47M1 is not set > > # CONFIG_SENSORS_SMSC47M192 is not set > > # CONFIG_SENSORS_SMSC47B397 is not set > > # CONFIG_SENSORS_SCH5627 is not set > > # CONFIG_SENSORS_SCH5636 is not set > > # CONFIG_SENSORS_STTS751 is not set > > # CONFIG_SENSORS_SMM665 is not set > > # CONFIG_SENSORS_ADC128D818 is not set > > # CONFIG_SENSORS_ADS7828 is not set > > # CONFIG_SENSORS_AMC6821 is not set > > # CONFIG_SENSORS_INA209 is not set > > # CONFIG_SENSORS_INA2XX is not set > > # CONFIG_SENSORS_INA3221 is not set > > # CONFIG_SENSORS_TC74 is not set > > # CONFIG_SENSORS_THMC50 is not set > > # CONFIG_SENSORS_TMP102 is not set > > # CONFIG_SENSORS_TMP103 is not set > > # CONFIG_SENSORS_TMP108 is not set > > # CONFIG_SENSORS_TMP401 is not set > > # CONFIG_SENSORS_TMP421 is not set > > # CONFIG_SENSORS_TMP513 is not set > > # CONFIG_SENSORS_VIA_CPUTEMP is not set > > # CONFIG_SENSORS_VIA686A is not set > > # CONFIG_SENSORS_VT1211 is not set > > # CONFIG_SENSORS_VT8231 is not set > > # CONFIG_SENSORS_W83773G is not set > > # CONFIG_SENSORS_W83781D is not set > > # CONFIG_SENSORS_W83791D is not set > > # CONFIG_SENSORS_W83792D is not set > > # CONFIG_SENSORS_W83793 is not set > > # CONFIG_SENSORS_W83795 is not set > > # CONFIG_SENSORS_W83L785TS is not set > > # CONFIG_SENSORS_W83L786NG is not set > > # CONFIG_SENSORS_W83627HF is not set > > # CONFIG_SENSORS_W83627EHF is not set > > # CONFIG_SENSORS_XGENE is not set > > > > # > > # ACPI drivers > > # > > CONFIG_SENSORS_ACPI_POWER=y > > CONFIG_SENSORS_ATK0110=y > > CONFIG_THERMAL=y > > # CONFIG_THERMAL_STATISTICS is not set > > CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 > > CONFIG_THERMAL_HWMON=y > > CONFIG_THERMAL_WRITABLE_TRIPS=y > > CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y > > # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set > > # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set > > # CONFIG_THERMAL_GOV_FAIR_SHARE is not set > > CONFIG_THERMAL_GOV_STEP_WISE=y > > # CONFIG_THERMAL_GOV_BANG_BANG is not set > > CONFIG_THERMAL_GOV_USER_SPACE=y > > # CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set > > # CONFIG_THERMAL_EMULATION is not set > > > > # > > # Intel thermal drivers > > # > > # CONFIG_INTEL_POWERCLAMP is not set > > CONFIG_X86_PKG_TEMP_THERMAL=y > > # CONFIG_INTEL_SOC_DTS_THERMAL is not set > > > > # > > # ACPI INT340X thermal drivers > > # > > # CONFIG_INT340X_THERMAL is not set > > # end of ACPI INT340X thermal drivers > > > > CONFIG_INTEL_PCH_THERMAL=y > > # end of Intel thermal drivers > > > > CONFIG_WATCHDOG=y > > CONFIG_WATCHDOG_CORE=y > > # CONFIG_WATCHDOG_NOWAYOUT is not set > > CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y > > CONFIG_WATCHDOG_OPEN_TIMEOUT=0 > > # CONFIG_WATCHDOG_SYSFS is not set > > > > # > > # Watchdog Pretimeout Governors > > # > > # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set > > > > # > > # Watchdog Device Drivers > > # > > # CONFIG_SOFT_WATCHDOG is not set > > # CONFIG_WDAT_WDT is not set > > # CONFIG_XILINX_WATCHDOG is not set > > # CONFIG_ZIIRAVE_WATCHDOG is not set > > # CONFIG_CADENCE_WATCHDOG is not set > > # CONFIG_DW_WATCHDOG is not set > > # CONFIG_MAX63XX_WATCHDOG is not set > > # CONFIG_ACQUIRE_WDT is not set > > # CONFIG_ADVANTECH_WDT is not set > > # CONFIG_ALIM1535_WDT is not set > > # CONFIG_ALIM7101_WDT is not set > > # CONFIG_EBC_C384_WDT is not set > > # CONFIG_F71808E_WDT is not set > > # CONFIG_SP5100_TCO is not set > > # CONFIG_SBC_FITPC2_WATCHDOG is not set > > # CONFIG_EUROTECH_WDT is not set > > # CONFIG_IB700_WDT is not set > > # CONFIG_IBMASR is not set > > # CONFIG_WAFER_WDT is not set > > # CONFIG_I6300ESB_WDT is not set > > # CONFIG_IE6XX_WDT is not set > > CONFIG_ITCO_WDT=y > > CONFIG_ITCO_VENDOR_SUPPORT=y > > # CONFIG_IT8712F_WDT is not set > > # CONFIG_IT87_WDT is not set > > # CONFIG_HP_WATCHDOG is not set > > # CONFIG_SC1200_WDT is not set > > # CONFIG_PC87413_WDT is not set > > # CONFIG_NV_TCO is not set > > # CONFIG_60XX_WDT is not set > > # CONFIG_CPU5_WDT is not set > > # CONFIG_SMSC_SCH311X_WDT is not set > > # CONFIG_SMSC37B787_WDT is not set > > # CONFIG_TQMX86_WDT is not set > > # CONFIG_VIA_WDT is not set > > # CONFIG_W83627HF_WDT is not set > > # CONFIG_W83877F_WDT is not set > > # CONFIG_W83977F_WDT is not set > > # CONFIG_MACHZ_WDT is not set > > # CONFIG_SBC_EPX_C3_WATCHDOG is not set > > CONFIG_INTEL_MEI_WDT=y > > # CONFIG_NI903X_WDT is not set > > # CONFIG_NIC7018_WDT is not set > > > > # > > # PCI-based Watchdog Cards > > # > > # CONFIG_PCIPCWATCHDOG is not set > > # CONFIG_WDTPCI is not set > > > > # > > # USB-based Watchdog Cards > > # > > # CONFIG_USBPCWATCHDOG is not set > > CONFIG_SSB_POSSIBLE=y > > # CONFIG_SSB is not set > > CONFIG_BCMA_POSSIBLE=y > > # CONFIG_BCMA is not set > > > > # > > # Multifunction device drivers > > # > > CONFIG_MFD_CORE=y > > # CONFIG_MFD_AS3711 is not set > > # CONFIG_PMIC_ADP5520 is not set > > # CONFIG_MFD_BCM590XX is not set > > # CONFIG_MFD_BD9571MWV is not set > > # CONFIG_MFD_AXP20X_I2C is not set > > # CONFIG_MFD_MADERA is not set > > # CONFIG_PMIC_DA903X is not set > > # CONFIG_MFD_DA9052_I2C is not set > > # CONFIG_MFD_DA9055 is not set > > # CONFIG_MFD_DA9062 is not set > > # CONFIG_MFD_DA9063 is not set > > # CONFIG_MFD_DA9150 is not set > > # CONFIG_MFD_DLN2 is not set > > # CONFIG_MFD_MC13XXX_I2C is not set > > # CONFIG_HTC_PASIC3 is not set > > # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set > > CONFIG_LPC_ICH=y > > # CONFIG_LPC_SCH is not set > > CONFIG_MFD_INTEL_LPSS=y > > CONFIG_MFD_INTEL_LPSS_ACPI=y > > CONFIG_MFD_INTEL_LPSS_PCI=y > > # CONFIG_MFD_IQS62X is not set > > # CONFIG_MFD_JANZ_CMODIO is not set > > # CONFIG_MFD_KEMPLD is not set > > # CONFIG_MFD_88PM800 is not set > > # CONFIG_MFD_88PM805 is not set > > # CONFIG_MFD_88PM860X is not set > > # CONFIG_MFD_MAX14577 is not set > > # CONFIG_MFD_MAX77693 is not set > > # CONFIG_MFD_MAX77843 is not set > > # CONFIG_MFD_MAX8907 is not set > > # CONFIG_MFD_MAX8925 is not set > > # CONFIG_MFD_MAX8997 is not set > > # CONFIG_MFD_MAX8998 is not set > > # CONFIG_MFD_MT6397 is not set > > # CONFIG_MFD_MENF21BMC is not set > > # CONFIG_MFD_VIPERBOARD is not set > > # CONFIG_MFD_RETU is not set > > # CONFIG_MFD_PCF50633 is not set > > # CONFIG_MFD_RDC321X is not set > > # CONFIG_MFD_RT5033 is not set > > # CONFIG_MFD_RC5T583 is not set > > # CONFIG_MFD_SEC_CORE is not set > > # CONFIG_MFD_SI476X_CORE is not set > > # CONFIG_MFD_SM501 is not set > > # CONFIG_MFD_SKY81452 is not set > > # CONFIG_MFD_SMSC is not set > > # CONFIG_ABX500_CORE is not set > > # CONFIG_MFD_SYSCON is not set > > # CONFIG_MFD_TI_AM335X_TSCADC is not set > > # CONFIG_MFD_LP3943 is not set > > # CONFIG_MFD_LP8788 is not set > > # CONFIG_MFD_TI_LMU is not set > > # CONFIG_MFD_PALMAS is not set > > # CONFIG_TPS6105X is not set > > # CONFIG_TPS6507X is not set > > # CONFIG_MFD_TPS65086 is not set > > # CONFIG_MFD_TPS65090 is not set > > # CONFIG_MFD_TI_LP873X is not set > > # CONFIG_MFD_TPS6586X is not set > > # CONFIG_MFD_TPS65912_I2C is not set > > # CONFIG_MFD_TPS80031 is not set > > # CONFIG_TWL4030_CORE is not set > > # CONFIG_TWL6040_CORE is not set > > # CONFIG_MFD_WL1273_CORE is not set > > # CONFIG_MFD_LM3533 is not set > > # CONFIG_MFD_TQMX86 is not set > > # CONFIG_MFD_VX855 is not set > > # CONFIG_MFD_ARIZONA_I2C is not set > > # CONFIG_MFD_WM8400 is not set > > # CONFIG_MFD_WM831X_I2C is not set > > # CONFIG_MFD_WM8350_I2C is not set > > # CONFIG_MFD_WM8994 is not set > > # end of Multifunction device drivers > > > > # CONFIG_REGULATOR is not set > > # CONFIG_RC_CORE is not set > > # CONFIG_MEDIA_SUPPORT is not set > > > > # > > # Graphics support > > # > > # CONFIG_AGP is not set > > CONFIG_INTEL_GTT=y > > CONFIG_VGA_ARB=y > > CONFIG_VGA_ARB_MAX_GPUS=16 > > # CONFIG_VGA_SWITCHEROO is not set > > CONFIG_DRM=y > > CONFIG_DRM_MIPI_DSI=y > > # CONFIG_DRM_DP_AUX_CHARDEV is not set > > # CONFIG_DRM_DEBUG_MM is not set > > # CONFIG_DRM_DEBUG_SELFTEST is not set > > CONFIG_DRM_KMS_HELPER=y > > CONFIG_DRM_KMS_FB_HELPER=y > > # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set > > CONFIG_DRM_FBDEV_EMULATION=y > > CONFIG_DRM_FBDEV_OVERALLOC=100 > > # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set > > # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set > > # CONFIG_DRM_DP_CEC is not set > > > > # > > # I2C encoder or helper chips > > # > > # CONFIG_DRM_I2C_CH7006 is not set > > # CONFIG_DRM_I2C_SIL164 is not set > > # CONFIG_DRM_I2C_NXP_TDA998X is not set > > # CONFIG_DRM_I2C_NXP_TDA9950 is not set > > # end of I2C encoder or helper chips > > > > # > > # ARM devices > > # > > # end of ARM devices > > > > # CONFIG_DRM_RADEON is not set > > # CONFIG_DRM_AMDGPU is not set > > # CONFIG_DRM_NOUVEAU is not set > > CONFIG_DRM_I915=y > > CONFIG_DRM_I915_FORCE_PROBE="" > > CONFIG_DRM_I915_CAPTURE_ERROR=y > > CONFIG_DRM_I915_COMPRESS_ERROR=y > > CONFIG_DRM_I915_USERPTR=y > > # CONFIG_DRM_I915_GVT is not set > > > > # > > # drm/i915 Debugging > > # > > # CONFIG_DRM_I915_WERROR is not set > > # CONFIG_DRM_I915_DEBUG is not set > > # CONFIG_DRM_I915_DEBUG_MMIO is not set > > # CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set > > # CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set > > # CONFIG_DRM_I915_DEBUG_GUC is not set > > # CONFIG_DRM_I915_SELFTEST is not set > > # CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set > > # CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set > > # CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set > > # end of drm/i915 Debugging > > > > # > > # drm/i915 Profile Guided Optimisation > > # > > CONFIG_DRM_I915_FENCE_TIMEOUT=10000 > > CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 > > CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 > > CONFIG_DRM_I915_PREEMPT_TIMEOUT=100 > > CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 > > CONFIG_DRM_I915_STOP_TIMEOUT=100 > > CONFIG_DRM_I915_TIMESLICE_DURATION=1 > > # end of drm/i915 Profile Guided Optimisation > > > > # CONFIG_DRM_VGEM is not set > > # CONFIG_DRM_VKMS is not set > > # CONFIG_DRM_VMWGFX is not set > > # CONFIG_DRM_GMA500 is not set > > # CONFIG_DRM_UDL is not set > > # CONFIG_DRM_AST is not set > > # CONFIG_DRM_MGAG200 is not set > > # CONFIG_DRM_QXL is not set > > # CONFIG_DRM_BOCHS is not set > > CONFIG_DRM_PANEL=y > > > > # > > # Display Panels > > # > > # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set > > # end of Display Panels > > > > CONFIG_DRM_BRIDGE=y > > CONFIG_DRM_PANEL_BRIDGE=y > > > > # > > # Display Interface Bridges > > # > > # CONFIG_DRM_ANALOGIX_ANX78XX is not set > > # end of Display Interface Bridges > > > > # CONFIG_DRM_ETNAVIV is not set > > # CONFIG_DRM_CIRRUS_QEMU is not set > > # CONFIG_DRM_GM12U320 is not set > > # CONFIG_DRM_VBOXVIDEO is not set > > # CONFIG_DRM_LEGACY is not set > > CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y > > > > # > > # Frame buffer Devices > > # > > CONFIG_FB_CMDLINE=y > > CONFIG_FB_NOTIFY=y > > CONFIG_FB=y > > CONFIG_FIRMWARE_EDID=y > > CONFIG_FB_CFB_FILLRECT=y > > CONFIG_FB_CFB_COPYAREA=y > > CONFIG_FB_CFB_IMAGEBLIT=y > > CONFIG_FB_SYS_FILLRECT=y > > CONFIG_FB_SYS_COPYAREA=y > > CONFIG_FB_SYS_IMAGEBLIT=y > > # CONFIG_FB_FOREIGN_ENDIAN is not set > > CONFIG_FB_SYS_FOPS=y > > CONFIG_FB_DEFERRED_IO=y > > CONFIG_FB_MODE_HELPERS=y > > # CONFIG_FB_TILEBLITTING is not set > > > > # > > # Frame buffer hardware drivers > > # > > # CONFIG_FB_CIRRUS is not set > > # CONFIG_FB_PM2 is not set > > # CONFIG_FB_CYBER2000 is not set > > # CONFIG_FB_ARC is not set > > # CONFIG_FB_ASILIANT is not set > > # CONFIG_FB_IMSTT is not set > > # CONFIG_FB_VGA16 is not set > > # CONFIG_FB_VESA is not set > > # CONFIG_FB_EFI is not set > > # CONFIG_FB_N411 is not set > > # CONFIG_FB_HGA is not set > > # CONFIG_FB_OPENCORES is not set > > # CONFIG_FB_S1D13XXX is not set > > # CONFIG_FB_NVIDIA is not set > > # CONFIG_FB_RIVA is not set > > # CONFIG_FB_I740 is not set > > # CONFIG_FB_LE80578 is not set > > # CONFIG_FB_MATROX is not set > > # CONFIG_FB_RADEON is not set > > # CONFIG_FB_ATY128 is not set > > # CONFIG_FB_ATY is not set > > # CONFIG_FB_S3 is not set > > # CONFIG_FB_SAVAGE is not set > > # CONFIG_FB_SIS is not set > > # CONFIG_FB_NEOMAGIC is not set > > # CONFIG_FB_KYRO is not set > > # CONFIG_FB_3DFX is not set > > # CONFIG_FB_VOODOO1 is not set > > # CONFIG_FB_VT8623 is not set > > # CONFIG_FB_TRIDENT is not set > > # CONFIG_FB_ARK is not set > > # CONFIG_FB_PM3 is not set > > # CONFIG_FB_CARMINE is not set > > # CONFIG_FB_SMSCUFX is not set > > # CONFIG_FB_UDL is not set > > # CONFIG_FB_IBM_GXT4500 is not set > > # CONFIG_FB_VIRTUAL is not set > > # CONFIG_FB_METRONOME is not set > > # CONFIG_FB_MB862XX is not set > > # CONFIG_FB_SIMPLE is not set > > # CONFIG_FB_SM712 is not set > > # end of Frame buffer Devices > > > > # > > # Backlight & LCD device support > > # > > # CONFIG_LCD_CLASS_DEVICE is not set > > CONFIG_BACKLIGHT_CLASS_DEVICE=y > > # CONFIG_BACKLIGHT_GENERIC is not set > > # CONFIG_BACKLIGHT_APPLE is not set > > # CONFIG_BACKLIGHT_QCOM_WLED is not set > > # CONFIG_BACKLIGHT_SAHARA is not set > > # CONFIG_BACKLIGHT_ADP8860 is not set > > # CONFIG_BACKLIGHT_ADP8870 is not set > > # CONFIG_BACKLIGHT_LM3639 is not set > > # CONFIG_BACKLIGHT_LV5207LP is not set > > # CONFIG_BACKLIGHT_BD6107 is not set > > # CONFIG_BACKLIGHT_ARCXCNN is not set > > # end of Backlight & LCD device support > > > > CONFIG_HDMI=y > > > > # > > # Console display driver support > > # > > CONFIG_VGA_CONSOLE=y > > # CONFIG_VGACON_SOFT_SCROLLBACK is not set > > CONFIG_DUMMY_CONSOLE=y > > CONFIG_DUMMY_CONSOLE_COLUMNS=80 > > CONFIG_DUMMY_CONSOLE_ROWS=25 > > # CONFIG_FRAMEBUFFER_CONSOLE is not set > > # end of Console display driver support > > > > CONFIG_LOGO=y > > CONFIG_LOGO_LINUX_MONO=y > > CONFIG_LOGO_LINUX_VGA16=y > > CONFIG_LOGO_LINUX_CLUT224=y > > # end of Graphics support > > > > # CONFIG_SOUND is not set > > > > # > > # HID support > > # > > CONFIG_HID=y > > # CONFIG_HID_BATTERY_STRENGTH is not set > > # CONFIG_HIDRAW is not set > > # CONFIG_UHID is not set > > CONFIG_HID_GENERIC=y > > > > # > > # Special HID drivers > > # > > # CONFIG_HID_A4TECH is not set > > # CONFIG_HID_ACCUTOUCH is not set > > # CONFIG_HID_ACRUX is not set > > # CONFIG_HID_APPLE is not set > > # CONFIG_HID_APPLEIR is not set > > # CONFIG_HID_AUREAL is not set > > # CONFIG_HID_BELKIN is not set > > # CONFIG_HID_BETOP_FF is not set > > # CONFIG_HID_CHERRY is not set > > # CONFIG_HID_CHICONY is not set > > # CONFIG_HID_COUGAR is not set > > # CONFIG_HID_MACALLY is not set > > # CONFIG_HID_CMEDIA is not set > > # CONFIG_HID_CREATIVE_SB0540 is not set > > # CONFIG_HID_CYPRESS is not set > > # CONFIG_HID_DRAGONRISE is not set > > # CONFIG_HID_EMS_FF is not set > > # CONFIG_HID_ELECOM is not set > > # CONFIG_HID_ELO is not set > > # CONFIG_HID_EZKEY is not set > > # CONFIG_HID_GEMBIRD is not set > > # CONFIG_HID_GFRM is not set > > # CONFIG_HID_GLORIOUS is not set > > # CONFIG_HID_HOLTEK is not set > > # CONFIG_HID_KEYTOUCH is not set > > # CONFIG_HID_KYE is not set > > # CONFIG_HID_UCLOGIC is not set > > # CONFIG_HID_WALTOP is not set > > # CONFIG_HID_VIEWSONIC is not set > > # CONFIG_HID_GYRATION is not set > > # CONFIG_HID_ICADE is not set > > # CONFIG_HID_ITE is not set > > # CONFIG_HID_JABRA is not set > > # CONFIG_HID_TWINHAN is not set > > # CONFIG_HID_KENSINGTON is not set > > # CONFIG_HID_LCPOWER is not set > > # CONFIG_HID_LENOVO is not set > > # CONFIG_HID_MAGICMOUSE is not set > > # CONFIG_HID_MALTRON is not set > > # CONFIG_HID_MAYFLASH is not set > > # CONFIG_HID_REDRAGON is not set > > # CONFIG_HID_MICROSOFT is not set > > # CONFIG_HID_MONTEREY is not set > > # CONFIG_HID_MULTITOUCH is not set > > # CONFIG_HID_NTI is not set > > # CONFIG_HID_NTRIG is not set > > # CONFIG_HID_ORTEK is not set > > # CONFIG_HID_PANTHERLORD is not set > > # CONFIG_HID_PENMOUNT is not set > > # CONFIG_HID_PETALYNX is not set > > # CONFIG_HID_PICOLCD is not set > > # CONFIG_HID_PLANTRONICS is not set > > # CONFIG_HID_PRIMAX is not set > > # CONFIG_HID_RETRODE is not set > > # CONFIG_HID_ROCCAT is not set > > # CONFIG_HID_SAITEK is not set > > # CONFIG_HID_SAMSUNG is not set > > # CONFIG_HID_SPEEDLINK is not set > > # CONFIG_HID_STEAM is not set > > # CONFIG_HID_STEELSERIES is not set > > # CONFIG_HID_SUNPLUS is not set > > # CONFIG_HID_RMI is not set > > # CONFIG_HID_GREENASIA is not set > > # CONFIG_HID_SMARTJOYPLUS is not set > > # CONFIG_HID_TIVO is not set > > # CONFIG_HID_TOPSEED is not set > > # CONFIG_HID_THRUSTMASTER is not set > > # CONFIG_HID_UDRAW_PS3 is not set > > # CONFIG_HID_WACOM is not set > > # CONFIG_HID_XINMO is not set > > # CONFIG_HID_ZEROPLUS is not set > > # CONFIG_HID_ZYDACRON is not set > > # CONFIG_HID_SENSOR_HUB is not set > > # CONFIG_HID_ALPS is not set > > # CONFIG_HID_MCP2221 is not set > > # end of Special HID drivers > > > > # > > # USB HID support > > # > > CONFIG_USB_HID=y > > # CONFIG_HID_PID is not set > > # CONFIG_USB_HIDDEV is not set > > # end of USB HID support > > > > # > > # I2C HID support > > # > > # CONFIG_I2C_HID is not set > > # end of I2C HID support > > > > # > > # Intel ISH HID support > > # > > CONFIG_INTEL_ISH_HID=y > > # CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER is not set > > # end of Intel ISH HID support > > # end of HID support > > > > CONFIG_USB_OHCI_LITTLE_ENDIAN=y > > CONFIG_USB_SUPPORT=y > > CONFIG_USB_COMMON=y > > # CONFIG_USB_ULPI_BUS is not set > > CONFIG_USB_ARCH_HAS_HCD=y > > CONFIG_USB=y > > CONFIG_USB_PCI=y > > # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set > > > > # > > # Miscellaneous USB options > > # > > CONFIG_USB_DEFAULT_PERSIST=y > > CONFIG_USB_DYNAMIC_MINORS=y > > # CONFIG_USB_OTG is not set > > # CONFIG_USB_OTG_WHITELIST is not set > > # CONFIG_USB_OTG_BLACKLIST_HUB is not set > > CONFIG_USB_AUTOSUSPEND_DELAY=2 > > # CONFIG_USB_MON is not set > > > > # > > # USB Host Controller Drivers > > # > > # CONFIG_USB_C67X00_HCD is not set > > CONFIG_USB_XHCI_HCD=y > > # CONFIG_USB_XHCI_DBGCAP is not set > > CONFIG_USB_XHCI_PCI=y > > # CONFIG_USB_XHCI_PLATFORM is not set > > CONFIG_USB_EHCI_HCD=y > > # CONFIG_USB_EHCI_ROOT_HUB_TT is not set > > CONFIG_USB_EHCI_TT_NEWSCHED=y > > CONFIG_USB_EHCI_PCI=y > > # CONFIG_USB_EHCI_FSL is not set > > # CONFIG_USB_EHCI_HCD_PLATFORM is not set > > # CONFIG_USB_OXU210HP_HCD is not set > > # CONFIG_USB_ISP116X_HCD is not set > > # CONFIG_USB_FOTG210_HCD is not set > > CONFIG_USB_OHCI_HCD=y > > CONFIG_USB_OHCI_HCD_PCI=y > > # CONFIG_USB_OHCI_HCD_PLATFORM is not set > > CONFIG_USB_UHCI_HCD=y > > # CONFIG_USB_SL811_HCD is not set > > # CONFIG_USB_R8A66597_HCD is not set > > # CONFIG_USB_HCD_TEST_MODE is not set > > > > # > > # USB Device Class drivers > > # > > # CONFIG_USB_ACM is not set > > # CONFIG_USB_PRINTER is not set > > # CONFIG_USB_WDM is not set > > # CONFIG_USB_TMC is not set > > > > # > > # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may > > # > > > > # > > # also be needed; see USB_STORAGE Help for more info > > # > > CONFIG_USB_STORAGE=y > > # CONFIG_USB_STORAGE_DEBUG is not set > > # CONFIG_USB_STORAGE_REALTEK is not set > > # CONFIG_USB_STORAGE_DATAFAB is not set > > # CONFIG_USB_STORAGE_FREECOM is not set > > # CONFIG_USB_STORAGE_ISD200 is not set > > # CONFIG_USB_STORAGE_USBAT is not set > > # CONFIG_USB_STORAGE_SDDR09 is not set > > # CONFIG_USB_STORAGE_SDDR55 is not set > > # CONFIG_USB_STORAGE_JUMPSHOT is not set > > # CONFIG_USB_STORAGE_ALAUDA is not set > > # CONFIG_USB_STORAGE_ONETOUCH is not set > > # CONFIG_USB_STORAGE_KARMA is not set > > # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set > > # CONFIG_USB_STORAGE_ENE_UB6250 is not set > > # CONFIG_USB_UAS is not set > > > > # > > # USB Imaging devices > > # > > # CONFIG_USB_MDC800 is not set > > # CONFIG_USB_MICROTEK is not set > > # CONFIG_USBIP_CORE is not set > > # CONFIG_USB_CDNS3 is not set > > # CONFIG_USB_MUSB_HDRC is not set > > # CONFIG_USB_DWC3 is not set > > # CONFIG_USB_DWC2 is not set > > # CONFIG_USB_CHIPIDEA is not set > > # CONFIG_USB_ISP1760 is not set > > > > # > > # USB port drivers > > # > > # CONFIG_USB_SERIAL is not set > > > > # > > # USB Miscellaneous drivers > > # > > # CONFIG_USB_EMI62 is not set > > # CONFIG_USB_EMI26 is not set > > # CONFIG_USB_ADUTUX is not set > > # CONFIG_USB_SEVSEG is not set > > # CONFIG_USB_LEGOTOWER is not set > > # CONFIG_USB_LCD is not set > > # CONFIG_USB_CYPRESS_CY7C63 is not set > > # CONFIG_USB_CYTHERM is not set > > # CONFIG_USB_IDMOUSE is not set > > # CONFIG_USB_FTDI_ELAN is not set > > # CONFIG_USB_APPLEDISPLAY is not set > > # CONFIG_APPLE_MFI_FASTCHARGE is not set > > # CONFIG_USB_SISUSBVGA is not set > > # CONFIG_USB_LD is not set > > # CONFIG_USB_TRANCEVIBRATOR is not set > > # CONFIG_USB_IOWARRIOR is not set > > # CONFIG_USB_TEST is not set > > # CONFIG_USB_EHSET_TEST_FIXTURE is not set > > # CONFIG_USB_ISIGHTFW is not set > > # CONFIG_USB_YUREX is not set > > # CONFIG_USB_EZUSB_FX2 is not set > > # CONFIG_USB_HUB_USB251XB is not set > > # CONFIG_USB_HSIC_USB3503 is not set > > # CONFIG_USB_HSIC_USB4604 is not set > > # CONFIG_USB_LINK_LAYER_TEST is not set > > > > # > > # USB Physical Layer drivers > > # > > # CONFIG_NOP_USB_XCEIV is not set > > # CONFIG_USB_ISP1301 is not set > > # end of USB Physical Layer drivers > > > > CONFIG_USB_GADGET=m > > # CONFIG_USB_GADGET_DEBUG is not set > > # CONFIG_USB_GADGET_DEBUG_FILES is not set > > # CONFIG_USB_GADGET_DEBUG_FS is not set > > CONFIG_USB_GADGET_VBUS_DRAW=2 > > CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 > > > > # > > # USB Peripheral Controller > > # > > # CONFIG_USB_FOTG210_UDC is not set > > # CONFIG_USB_GR_UDC is not set > > # CONFIG_USB_R8A66597 is not set > > # CONFIG_USB_PXA27X is not set > > # CONFIG_USB_MV_UDC is not set > > # CONFIG_USB_MV_U3D is not set > > # CONFIG_USB_M66592 is not set > > # CONFIG_USB_BDC_UDC is not set > > # CONFIG_USB_AMD5536UDC is not set > > # CONFIG_USB_NET2272 is not set > > # CONFIG_USB_NET2280 is not set > > # CONFIG_USB_GOKU is not set > > # CONFIG_USB_EG20T is not set > > # CONFIG_USB_DUMMY_HCD is not set > > # end of USB Peripheral Controller > > > > CONFIG_USB_LIBCOMPOSITE=m > > CONFIG_USB_F_FS=m > > CONFIG_USB_CONFIGFS=m > > # CONFIG_USB_CONFIGFS_SERIAL is not set > > # CONFIG_USB_CONFIGFS_ACM is not set > > # CONFIG_USB_CONFIGFS_OBEX is not set > > # CONFIG_USB_CONFIGFS_NCM is not set > > # CONFIG_USB_CONFIGFS_ECM is not set > > # CONFIG_USB_CONFIGFS_ECM_SUBSET is not set > > # CONFIG_USB_CONFIGFS_RNDIS is not set > > # CONFIG_USB_CONFIGFS_EEM is not set > > # CONFIG_USB_CONFIGFS_MASS_STORAGE is not set > > # CONFIG_USB_CONFIGFS_F_LB_SS is not set > > CONFIG_USB_CONFIGFS_F_FS=y > > # CONFIG_USB_CONFIGFS_F_HID is not set > > # CONFIG_USB_CONFIGFS_F_PRINTER is not set > > > > # > > # USB Gadget precomposed configurations > > # > > # CONFIG_USB_ZERO is not set > > # CONFIG_USB_ETH is not set > > # CONFIG_USB_G_NCM is not set > > # CONFIG_USB_GADGETFS is not set > > # CONFIG_USB_FUNCTIONFS is not set > > # CONFIG_USB_MASS_STORAGE is not set > > # CONFIG_USB_G_SERIAL is not set > > # CONFIG_USB_G_PRINTER is not set > > # CONFIG_USB_CDC_COMPOSITE is not set > > # CONFIG_USB_G_ACM_MS is not set > > # CONFIG_USB_G_MULTI is not set > > # CONFIG_USB_G_HID is not set > > # CONFIG_USB_G_DBGP is not set > > # CONFIG_USB_RAW_GADGET is not set > > # end of USB Gadget precomposed configurations > > > > # CONFIG_TYPEC is not set > > # CONFIG_USB_ROLE_SWITCH is not set > > # CONFIG_MMC is not set > > # CONFIG_MEMSTICK is not set > > # CONFIG_NEW_LEDS is not set > > # CONFIG_ACCESSIBILITY is not set > > # CONFIG_INFINIBAND is not set > > CONFIG_EDAC_ATOMIC_SCRUB=y > > CONFIG_EDAC_SUPPORT=y > > # CONFIG_EDAC is not set > > CONFIG_RTC_LIB=y > > CONFIG_RTC_MC146818_LIB=y > > CONFIG_RTC_CLASS=y > > CONFIG_RTC_HCTOSYS=y > > CONFIG_RTC_HCTOSYS_DEVICE="rtc0" > > CONFIG_RTC_SYSTOHC=y > > CONFIG_RTC_SYSTOHC_DEVICE="rtc0" > > # CONFIG_RTC_DEBUG is not set > > CONFIG_RTC_NVMEM=y > > > > # > > # RTC interfaces > > # > > CONFIG_RTC_INTF_SYSFS=y > > CONFIG_RTC_INTF_PROC=y > > CONFIG_RTC_INTF_DEV=y > > # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set > > # CONFIG_RTC_DRV_TEST is not set > > > > # > > # I2C RTC drivers > > # > > # CONFIG_RTC_DRV_ABB5ZES3 is not set > > # CONFIG_RTC_DRV_ABEOZ9 is not set > > # CONFIG_RTC_DRV_ABX80X is not set > > # CONFIG_RTC_DRV_DS1307 is not set > > # CONFIG_RTC_DRV_DS1374 is not set > > # CONFIG_RTC_DRV_DS1672 is not set > > # CONFIG_RTC_DRV_MAX6900 is not set > > # CONFIG_RTC_DRV_RS5C372 is not set > > # CONFIG_RTC_DRV_ISL1208 is not set > > # CONFIG_RTC_DRV_ISL12022 is not set > > # CONFIG_RTC_DRV_X1205 is not set > > # CONFIG_RTC_DRV_PCF8523 is not set > > # CONFIG_RTC_DRV_PCF85063 is not set > > # CONFIG_RTC_DRV_PCF85363 is not set > > # CONFIG_RTC_DRV_PCF8563 is not set > > # CONFIG_RTC_DRV_PCF8583 is not set > > # CONFIG_RTC_DRV_M41T80 is not set > > # CONFIG_RTC_DRV_BQ32K is not set > > # CONFIG_RTC_DRV_S35390A is not set > > # CONFIG_RTC_DRV_FM3130 is not set > > # CONFIG_RTC_DRV_RX8010 is not set > > # CONFIG_RTC_DRV_RX8581 is not set > > # CONFIG_RTC_DRV_RX8025 is not set > > # CONFIG_RTC_DRV_EM3027 is not set > > # CONFIG_RTC_DRV_RV3028 is not set > > # CONFIG_RTC_DRV_RV8803 is not set > > # CONFIG_RTC_DRV_SD3078 is not set > > > > # > > # SPI RTC drivers > > # > > CONFIG_RTC_I2C_AND_SPI=y > > > > # > > # SPI and I2C RTC drivers > > # > > # CONFIG_RTC_DRV_DS3232 is not set > > # CONFIG_RTC_DRV_PCF2127 is not set > > # CONFIG_RTC_DRV_RV3029C2 is not set > > > > # > > # Platform RTC drivers > > # > > CONFIG_RTC_DRV_CMOS=y > > # CONFIG_RTC_DRV_DS1286 is not set > > # CONFIG_RTC_DRV_DS1511 is not set > > # CONFIG_RTC_DRV_DS1553 is not set > > # CONFIG_RTC_DRV_DS1685_FAMILY is not set > > # CONFIG_RTC_DRV_DS1742 is not set > > # CONFIG_RTC_DRV_DS2404 is not set > > # CONFIG_RTC_DRV_STK17TA8 is not set > > # CONFIG_RTC_DRV_M48T86 is not set > > # CONFIG_RTC_DRV_M48T35 is not set > > # CONFIG_RTC_DRV_M48T59 is not set > > # CONFIG_RTC_DRV_MSM6242 is not set > > # CONFIG_RTC_DRV_BQ4802 is not set > > # CONFIG_RTC_DRV_RP5C01 is not set > > # CONFIG_RTC_DRV_V3020 is not set > > > > # > > # on-CPU RTC drivers > > # > > # CONFIG_RTC_DRV_FTRTC010 is not set > > > > # > > # HID Sensor RTC drivers > > # > > # CONFIG_DMADEVICES is not set > > > > # > > # DMABUF options > > # > > CONFIG_SYNC_FILE=y > > # CONFIG_SW_SYNC is not set > > # CONFIG_UDMABUF is not set > > # CONFIG_DMABUF_MOVE_NOTIFY is not set > > # CONFIG_DMABUF_SELFTESTS is not set > > # CONFIG_DMABUF_HEAPS is not set > > # end of DMABUF options > > > > # CONFIG_AUXDISPLAY is not set > > # CONFIG_UIO is not set > > # CONFIG_VFIO is not set > > # CONFIG_VIRT_DRIVERS is not set > > # CONFIG_VIRTIO_MENU is not set > > # CONFIG_VDPA_MENU is not set > > CONFIG_VHOST_MENU=y > > # CONFIG_VHOST_NET is not set > > # CONFIG_VHOST_VDPA is not set > > # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set > > > > # > > # Microsoft Hyper-V guest support > > # > > # end of Microsoft Hyper-V guest support > > > > # CONFIG_GREYBUS is not set > > # CONFIG_STAGING is not set > > CONFIG_X86_PLATFORM_DEVICES=y > > CONFIG_ACPI_WMI=y > > CONFIG_WMI_BMOF=y > > # CONFIG_INTEL_WMI_THUNDERBOLT is not set > > CONFIG_MXM_WMI=y > > # CONFIG_PEAQ_WMI is not set > > # CONFIG_XIAOMI_WMI is not set > > # CONFIG_ACERHDF is not set > > # CONFIG_ACER_WIRELESS is not set > > # CONFIG_ACER_WMI is not set > > # CONFIG_APPLE_GMUX is not set > > # CONFIG_ASUS_LAPTOP is not set > > # CONFIG_ASUS_WIRELESS is not set > > # CONFIG_DCDBAS is not set > > # CONFIG_DELL_SMBIOS is not set > > # CONFIG_DELL_RBU is not set > > # CONFIG_DELL_SMO8800 is not set > > # CONFIG_DELL_WMI_AIO is not set > > # CONFIG_FUJITSU_LAPTOP is not set > > # CONFIG_FUJITSU_TABLET is not set > > # CONFIG_GPD_POCKET_FAN is not set > > # CONFIG_HP_ACCEL is not set > > # CONFIG_HP_WIRELESS is not set > > # CONFIG_HP_WMI is not set > > # CONFIG_IBM_RTL is not set > > # CONFIG_SENSORS_HDAPS is not set > > # CONFIG_INTEL_ATOMISP2_PM is not set > > # CONFIG_INTEL_HID_EVENT is not set > > # CONFIG_INTEL_MENLOW is not set > > # CONFIG_INTEL_VBTN is not set > > # CONFIG_SURFACE_3_POWER_OPREGION is not set > > # CONFIG_SURFACE_PRO3_BUTTON is not set > > # CONFIG_MSI_WMI is not set > > # CONFIG_SAMSUNG_LAPTOP is not set > > # CONFIG_SAMSUNG_Q10 is not set > > # CONFIG_TOSHIBA_BT_RFKILL is not set > > # CONFIG_TOSHIBA_HAPS is not set > > # CONFIG_TOSHIBA_WMI is not set > > # CONFIG_ACPI_CMPC is not set > > # CONFIG_LG_LAPTOP is not set > > # CONFIG_PANASONIC_LAPTOP is not set > > # CONFIG_SYSTEM76_ACPI is not set > > # CONFIG_TOPSTAR_LAPTOP is not set > > # CONFIG_I2C_MULTI_INSTANTIATE is not set > > # CONFIG_INTEL_IPS is not set > > # CONFIG_INTEL_RST is not set > > # CONFIG_INTEL_SMARTCONNECT is not set > > > > # > > # Intel Speed Select Technology interface support > > # > > CONFIG_INTEL_SPEED_SELECT_INTERFACE=y > > # end of Intel Speed Select Technology interface support > > > > # CONFIG_INTEL_TURBO_MAX_3 is not set > > # CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set > > # CONFIG_INTEL_PMC_CORE is not set > > # CONFIG_INTEL_PMC_IPC is not set > > # CONFIG_INTEL_PUNIT_IPC is not set > > CONFIG_PMC_ATOM=y > > # CONFIG_MFD_CROS_EC is not set > > # CONFIG_CHROME_PLATFORMS is not set > > # CONFIG_MELLANOX_PLATFORM is not set > > CONFIG_CLKDEV_LOOKUP=y > > CONFIG_HAVE_CLK_PREPARE=y > > CONFIG_COMMON_CLK=y > > > > # > > # Common Clock Framework > > # > > # CONFIG_COMMON_CLK_MAX9485 is not set > > # CONFIG_COMMON_CLK_SI5341 is not set > > # CONFIG_COMMON_CLK_SI5351 is not set > > # CONFIG_COMMON_CLK_SI544 is not set > > # CONFIG_COMMON_CLK_CDCE706 is not set > > # CONFIG_COMMON_CLK_CS2000_CP is not set > > # end of Common Clock Framework > > > > # CONFIG_HWSPINLOCK is not set > > > > # > > # Clock Source drivers > > # > > CONFIG_CLKEVT_I8253=y > > CONFIG_I8253_LOCK=y > > CONFIG_CLKBLD_I8253=y > > # end of Clock Source drivers > > > > CONFIG_MAILBOX=y > > CONFIG_PCC=y > > # CONFIG_ALTERA_MBOX is not set > > CONFIG_IOMMU_IOVA=y > > CONFIG_IOASID=y > > CONFIG_IOMMU_API=y > > CONFIG_IOMMU_SUPPORT=y > > > > # > > # Generic IOMMU Pagetable Support > > # > > # end of Generic IOMMU Pagetable Support > > > > # CONFIG_IOMMU_DEBUGFS is not set > > # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set > > # CONFIG_AMD_IOMMU is not set > > CONFIG_DMAR_TABLE=y > > CONFIG_INTEL_IOMMU=y > > CONFIG_INTEL_IOMMU_SVM=y > > CONFIG_INTEL_IOMMU_DEFAULT_ON=y > > CONFIG_INTEL_IOMMU_FLOPPY_WA=y > > # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set > > # CONFIG_IRQ_REMAP is not set > > > > # > > # Remoteproc drivers > > # > > # CONFIG_REMOTEPROC is not set > > # end of Remoteproc drivers > > > > # > > # Rpmsg drivers > > # > > # CONFIG_RPMSG_QCOM_GLINK_RPM is not set > > # CONFIG_RPMSG_VIRTIO is not set > > # end of Rpmsg drivers > > > > # CONFIG_SOUNDWIRE is not set > > > > # > > # SOC (System On Chip) specific Drivers > > # > > > > # > > # Amlogic SoC drivers > > # > > # end of Amlogic SoC drivers > > > > # > > # Aspeed SoC drivers > > # > > # end of Aspeed SoC drivers > > > > # > > # Broadcom SoC drivers > > # > > # end of Broadcom SoC drivers > > > > # > > # NXP/Freescale QorIQ SoC drivers > > # > > # end of NXP/Freescale QorIQ SoC drivers > > > > # > > # i.MX SoC drivers > > # > > # end of i.MX SoC drivers > > > > # > > # Qualcomm SoC drivers > > # > > # end of Qualcomm SoC drivers > > > > # CONFIG_SOC_TI is not set > > > > # > > # Xilinx SoC drivers > > # > > # CONFIG_XILINX_VCU is not set > > # end of Xilinx SoC drivers > > # end of SOC (System On Chip) specific Drivers > > > > # CONFIG_PM_DEVFREQ is not set > > # CONFIG_EXTCON is not set > > # CONFIG_MEMORY is not set > > # CONFIG_IIO is not set > > # CONFIG_NTB is not set > > # CONFIG_VME_BUS is not set > > # CONFIG_PWM is not set > > > > # > > # IRQ chip support > > # > > # end of IRQ chip support > > > > # CONFIG_IPACK_BUS is not set > > # CONFIG_RESET_CONTROLLER is not set > > > > # > > # PHY Subsystem > > # > > # CONFIG_GENERIC_PHY is not set > > # CONFIG_BCM_KONA_USB2_PHY is not set > > # CONFIG_PHY_PXA_28NM_HSIC is not set > > # CONFIG_PHY_PXA_28NM_USB2 is not set > > # CONFIG_PHY_INTEL_EMMC is not set > > # end of PHY Subsystem > > > > # CONFIG_POWERCAP is not set > > # CONFIG_MCB is not set > > > > # > > # Performance monitor support > > # > > # end of Performance monitor support > > > > CONFIG_RAS=y > > # CONFIG_USB4 is not set > > > > # > > # Android > > # > > # CONFIG_ANDROID is not set > > # end of Android > > > > # CONFIG_LIBNVDIMM is not set > > # CONFIG_DAX is not set > > CONFIG_NVMEM=y > > # CONFIG_NVMEM_SYSFS is not set > > > > # > > # HW tracing support > > # > > # CONFIG_STM is not set > > # CONFIG_INTEL_TH is not set > > # end of HW tracing support > > > > # CONFIG_FPGA is not set > > # CONFIG_TEE is not set > > # CONFIG_UNISYS_VISORBUS is not set > > # CONFIG_SIOX is not set > > # CONFIG_SLIMBUS is not set > > # CONFIG_INTERCONNECT is not set > > # CONFIG_COUNTER is not set > > # CONFIG_MOST is not set > > # end of Device Drivers > > > > # > > # File systems > > # > > CONFIG_DCACHE_WORD_ACCESS=y > > CONFIG_VALIDATE_FS_PARSER=y > > CONFIG_FS_IOMAP=y > > # CONFIG_EXT2_FS is not set > > # CONFIG_EXT3_FS is not set > > CONFIG_EXT4_FS=y > > CONFIG_EXT4_USE_FOR_EXT2=y > > CONFIG_EXT4_FS_POSIX_ACL=y > > CONFIG_EXT4_FS_SECURITY=y > > # CONFIG_EXT4_DEBUG is not set > > CONFIG_JBD2=y > > # CONFIG_JBD2_DEBUG is not set > > CONFIG_FS_MBCACHE=y > > # CONFIG_REISERFS_FS is not set > > # CONFIG_JFS_FS is not set > > CONFIG_XFS_FS=y > > CONFIG_XFS_QUOTA=y > > CONFIG_XFS_POSIX_ACL=y > > # CONFIG_XFS_RT is not set > > # CONFIG_XFS_ONLINE_SCRUB is not set > > # CONFIG_XFS_WARN is not set > > # CONFIG_XFS_DEBUG is not set > > # CONFIG_GFS2_FS is not set > > # CONFIG_OCFS2_FS is not set > > CONFIG_BTRFS_FS=y > > CONFIG_BTRFS_FS_POSIX_ACL=y > > CONFIG_BTRFS_FS_CHECK_INTEGRITY=y > > # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set > > CONFIG_BTRFS_DEBUG=y > > # CONFIG_BTRFS_ASSERT is not set > > CONFIG_BTRFS_FS_REF_VERIFY=y > > CONFIG_NILFS2_FS=m > > CONFIG_F2FS_FS=m > > CONFIG_F2FS_STAT_FS=y > > CONFIG_F2FS_FS_XATTR=y > > CONFIG_F2FS_FS_POSIX_ACL=y > > CONFIG_F2FS_FS_SECURITY=y > > # CONFIG_F2FS_CHECK_FS is not set > > # CONFIG_F2FS_IO_TRACE is not set > > # CONFIG_F2FS_FAULT_INJECTION is not set > > # CONFIG_F2FS_FS_COMPRESSION is not set > > # CONFIG_FS_DAX is not set > > CONFIG_FS_POSIX_ACL=y > > CONFIG_EXPORTFS=y > > CONFIG_EXPORTFS_BLOCK_OPS=y > > CONFIG_FILE_LOCKING=y > > CONFIG_MANDATORY_FILE_LOCKING=y > > # CONFIG_FS_ENCRYPTION is not set > > # CONFIG_FS_VERITY is not set > > CONFIG_FSNOTIFY=y > > CONFIG_DNOTIFY=y > > CONFIG_INOTIFY_USER=y > > CONFIG_FANOTIFY=y > > CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y > > # CONFIG_QUOTA is not set > > # CONFIG_QUOTA_NETLINK_INTERFACE is not set > > CONFIG_QUOTACTL=y > > CONFIG_QUOTACTL_COMPAT=y > > CONFIG_AUTOFS4_FS=y > > CONFIG_AUTOFS_FS=y > > CONFIG_FUSE_FS=m > > # CONFIG_CUSE is not set > > # CONFIG_VIRTIO_FS is not set > > # CONFIG_OVERLAY_FS is not set > > > > # > > # Caches > > # > > CONFIG_FSCACHE=y > > CONFIG_FSCACHE_STATS=y > > # CONFIG_FSCACHE_HISTOGRAM is not set > > # CONFIG_FSCACHE_DEBUG is not set > > CONFIG_FSCACHE_OBJECT_LIST=y > > CONFIG_CACHEFILES=y > > # CONFIG_CACHEFILES_DEBUG is not set > > # CONFIG_CACHEFILES_HISTOGRAM is not set > > # end of Caches > > > > # > > # CD-ROM/DVD Filesystems > > # > > # CONFIG_ISO9660_FS is not set > > # CONFIG_UDF_FS is not set > > # end of CD-ROM/DVD Filesystems > > > > # > > # DOS/FAT/EXFAT/NT Filesystems > > # > > # CONFIG_MSDOS_FS is not set > > # CONFIG_VFAT_FS is not set > > # CONFIG_EXFAT_FS is not set > > # CONFIG_NTFS_FS is not set > > # end of DOS/FAT/EXFAT/NT Filesystems > > > > # > > # Pseudo filesystems > > # > > CONFIG_PROC_FS=y > > CONFIG_PROC_KCORE=y > > CONFIG_PROC_SYSCTL=y > > CONFIG_PROC_PAGE_MONITOR=y > > # CONFIG_PROC_CHILDREN is not set > > CONFIG_PROC_PID_ARCH_STATUS=y > > CONFIG_PROC_CPU_RESCTRL=y > > CONFIG_KERNFS=y > > CONFIG_SYSFS=y > > CONFIG_TMPFS=y > > CONFIG_TMPFS_POSIX_ACL=y > > CONFIG_TMPFS_XATTR=y > > CONFIG_HUGETLBFS=y > > CONFIG_HUGETLB_PAGE=y > > CONFIG_MEMFD_CREATE=y > > CONFIG_ARCH_HAS_GIGANTIC_PAGE=y > > CONFIG_CONFIGFS_FS=y > > CONFIG_EFIVAR_FS=y > > # end of Pseudo filesystems > > > > CONFIG_MISC_FILESYSTEMS=y > > # CONFIG_ORANGEFS_FS is not set > > # CONFIG_ADFS_FS is not set > > # CONFIG_AFFS_FS is not set > > # CONFIG_ECRYPT_FS is not set > > # CONFIG_HFS_FS is not set > > # CONFIG_HFSPLUS_FS is not set > > # CONFIG_BEFS_FS is not set > > # CONFIG_BFS_FS is not set > > # CONFIG_EFS_FS is not set > > # CONFIG_CRAMFS is not set > > # CONFIG_SQUASHFS is not set > > # CONFIG_VXFS_FS is not set > > # CONFIG_MINIX_FS is not set > > # CONFIG_OMFS_FS is not set > > # CONFIG_HPFS_FS is not set > > # CONFIG_QNX4FS_FS is not set > > # CONFIG_QNX6FS_FS is not set > > # CONFIG_ROMFS_FS is not set > > CONFIG_PSTORE=y > > CONFIG_PSTORE_DEFLATE_COMPRESS=y > > # CONFIG_PSTORE_LZO_COMPRESS is not set > > # CONFIG_PSTORE_LZ4_COMPRESS is not set > > # CONFIG_PSTORE_LZ4HC_COMPRESS is not set > > # CONFIG_PSTORE_842_COMPRESS is not set > > # CONFIG_PSTORE_ZSTD_COMPRESS is not set > > CONFIG_PSTORE_COMPRESS=y > > CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y > > CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" > > # CONFIG_PSTORE_CONSOLE is not set > > # CONFIG_PSTORE_PMSG is not set > > # CONFIG_PSTORE_FTRACE is not set > > # CONFIG_PSTORE_RAM is not set > > # CONFIG_SYSV_FS is not set > > # CONFIG_UFS_FS is not set > > # CONFIG_EROFS_FS is not set > > CONFIG_NETWORK_FILESYSTEMS=y > > CONFIG_NFS_FS=y > > # CONFIG_NFS_V2 is not set > > # CONFIG_NFS_V3 is not set > > CONFIG_NFS_V4=y > > # CONFIG_NFS_SWAP is not set > > # CONFIG_NFS_V4_1 is not set > > # CONFIG_NFS_FSCACHE is not set > > # CONFIG_NFS_USE_LEGACY_DNS is not set > > CONFIG_NFS_USE_KERNEL_DNS=y > > CONFIG_NFS_DEBUG=y > > CONFIG_NFS_DISABLE_UDP_SUPPORT=y > > # CONFIG_NFSD is not set > > CONFIG_GRACE_PERIOD=y > > CONFIG_LOCKD=y > > CONFIG_NFS_COMMON=y > > CONFIG_SUNRPC=y > > CONFIG_SUNRPC_GSS=y > > CONFIG_SUNRPC_DEBUG=y > > # CONFIG_CEPH_FS is not set > > # CONFIG_CIFS is not set > > # CONFIG_CODA_FS is not set > > CONFIG_AFS_FS=y > > CONFIG_AFS_DEBUG=y > > CONFIG_AFS_FSCACHE=y > > CONFIG_AFS_DEBUG_CURSOR=y > > CONFIG_NLS=y > > CONFIG_NLS_DEFAULT="iso8859-1" > > # CONFIG_NLS_CODEPAGE_437 is not set > > # CONFIG_NLS_CODEPAGE_737 is not set > > # CONFIG_NLS_CODEPAGE_775 is not set > > # CONFIG_NLS_CODEPAGE_850 is not set > > # CONFIG_NLS_CODEPAGE_852 is not set > > # CONFIG_NLS_CODEPAGE_855 is not set > > # CONFIG_NLS_CODEPAGE_857 is not set > > # CONFIG_NLS_CODEPAGE_860 is not set > > # CONFIG_NLS_CODEPAGE_861 is not set > > # CONFIG_NLS_CODEPAGE_862 is not set > > # CONFIG_NLS_CODEPAGE_863 is not set > > # CONFIG_NLS_CODEPAGE_864 is not set > > # CONFIG_NLS_CODEPAGE_865 is not set > > # CONFIG_NLS_CODEPAGE_866 is not set > > # CONFIG_NLS_CODEPAGE_869 is not set > > # CONFIG_NLS_CODEPAGE_936 is not set > > # CONFIG_NLS_CODEPAGE_950 is not set > > # CONFIG_NLS_CODEPAGE_932 is not set > > # CONFIG_NLS_CODEPAGE_949 is not set > > # CONFIG_NLS_CODEPAGE_874 is not set > > # CONFIG_NLS_ISO8859_8 is not set > > # CONFIG_NLS_CODEPAGE_1250 is not set > > # CONFIG_NLS_CODEPAGE_1251 is not set > > # CONFIG_NLS_ASCII is not set > > # CONFIG_NLS_ISO8859_1 is not set > > # CONFIG_NLS_ISO8859_2 is not set > > # CONFIG_NLS_ISO8859_3 is not set > > # CONFIG_NLS_ISO8859_4 is not set > > # CONFIG_NLS_ISO8859_5 is not set > > # CONFIG_NLS_ISO8859_6 is not set > > # CONFIG_NLS_ISO8859_7 is not set > > # CONFIG_NLS_ISO8859_9 is not set > > # CONFIG_NLS_ISO8859_13 is not set > > # CONFIG_NLS_ISO8859_14 is not set > > # CONFIG_NLS_ISO8859_15 is not set > > # CONFIG_NLS_KOI8_R is not set > > # CONFIG_NLS_KOI8_U is not set > > # CONFIG_NLS_MAC_ROMAN is not set > > # CONFIG_NLS_MAC_CELTIC is not set > > # CONFIG_NLS_MAC_CENTEURO is not set > > # CONFIG_NLS_MAC_CROATIAN is not set > > # CONFIG_NLS_MAC_CYRILLIC is not set > > # CONFIG_NLS_MAC_GAELIC is not set > > # CONFIG_NLS_MAC_GREEK is not set > > # CONFIG_NLS_MAC_ICELAND is not set > > # CONFIG_NLS_MAC_INUIT is not set > > # CONFIG_NLS_MAC_ROMANIAN is not set > > # CONFIG_NLS_MAC_TURKISH is not set > > # CONFIG_NLS_UTF8 is not set > > CONFIG_DLM=y > > # CONFIG_DLM_DEBUG is not set > > # CONFIG_UNICODE is not set > > # end of File systems > > > > # > > # Security options > > # > > CONFIG_KEYS=y > > CONFIG_KEYS_REQUEST_CACHE=y > > CONFIG_PERSISTENT_KEYRINGS=y > > CONFIG_BIG_KEYS=y > > CONFIG_TRUSTED_KEYS=y > > CONFIG_ENCRYPTED_KEYS=y > > CONFIG_KEY_DH_OPERATIONS=y > > # CONFIG_SECURITY_DMESG_RESTRICT is not set > > CONFIG_SECURITY=y > > CONFIG_SECURITY_WRITABLE_HOOKS=y > > CONFIG_SECURITYFS=y > > CONFIG_SECURITY_NETWORK=y > > CONFIG_PAGE_TABLE_ISOLATION=y > > CONFIG_SECURITY_NETWORK_XFRM=y > > CONFIG_SECURITY_PATH=y > > # CONFIG_INTEL_TXT is not set > > CONFIG_LSM_MMAP_MIN_ADDR=65536 > > CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y > > # CONFIG_HARDENED_USERCOPY is not set > > # CONFIG_FORTIFY_SOURCE is not set > > # CONFIG_STATIC_USERMODEHELPER is not set > > CONFIG_SECURITY_SELINUX=y > > CONFIG_SECURITY_SELINUX_BOOTPARAM=y > > CONFIG_SECURITY_SELINUX_DISABLE=y > > CONFIG_SECURITY_SELINUX_DEVELOP=y > > CONFIG_SECURITY_SELINUX_AVC_STATS=y > > CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 > > CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 > > CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 > > # CONFIG_SECURITY_SMACK is not set > > # CONFIG_SECURITY_TOMOYO is not set > > # CONFIG_SECURITY_APPARMOR is not set > > # CONFIG_SECURITY_LOADPIN is not set > > CONFIG_SECURITY_YAMA=y > > # CONFIG_SECURITY_SAFESETID is not set > > # CONFIG_SECURITY_LOCKDOWN_LSM is not set > > # CONFIG_INTEGRITY is not set > > # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set > > CONFIG_DEFAULT_SECURITY_SELINUX=y > > # CONFIG_DEFAULT_SECURITY_DAC is not set > > CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" > > > > # > > # Kernel hardening options > > # > > > > # > > # Memory initialization > > # > > CONFIG_INIT_STACK_NONE=y > > # CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set > > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set > > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set > > # CONFIG_GCC_PLUGIN_STACKLEAK is not set > > # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set > > # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set > > # end of Memory initialization > > # end of Kernel hardening options > > # end of Security options > > > > CONFIG_XOR_BLOCKS=y > > CONFIG_CRYPTO=y > > > > # > > # Crypto core or helper > > # > > # CONFIG_CRYPTO_FIPS is not set > > CONFIG_CRYPTO_ALGAPI=y > > CONFIG_CRYPTO_ALGAPI2=y > > CONFIG_CRYPTO_AEAD=y > > CONFIG_CRYPTO_AEAD2=y > > CONFIG_CRYPTO_SKCIPHER=y > > CONFIG_CRYPTO_SKCIPHER2=y > > CONFIG_CRYPTO_HASH=y > > CONFIG_CRYPTO_HASH2=y > > CONFIG_CRYPTO_RNG=y > > CONFIG_CRYPTO_RNG2=y > > CONFIG_CRYPTO_RNG_DEFAULT=y > > CONFIG_CRYPTO_AKCIPHER2=y > > CONFIG_CRYPTO_AKCIPHER=y > > CONFIG_CRYPTO_KPP2=y > > CONFIG_CRYPTO_KPP=y > > CONFIG_CRYPTO_ACOMP2=y > > CONFIG_CRYPTO_MANAGER=y > > CONFIG_CRYPTO_MANAGER2=y > > # CONFIG_CRYPTO_USER is not set > > # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set > > # CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set > > CONFIG_CRYPTO_GF128MUL=y > > CONFIG_CRYPTO_NULL=y > > CONFIG_CRYPTO_NULL2=y > > # CONFIG_CRYPTO_PCRYPT is not set > > # CONFIG_CRYPTO_CRYPTD is not set > > CONFIG_CRYPTO_AUTHENC=y > > # CONFIG_CRYPTO_TEST is not set > > > > # > > # Public-key cryptography > > # > > CONFIG_CRYPTO_RSA=y > > CONFIG_CRYPTO_DH=y > > # CONFIG_CRYPTO_ECDH is not set > > # CONFIG_CRYPTO_ECRDSA is not set > > # CONFIG_CRYPTO_CURVE25519 is not set > > # CONFIG_CRYPTO_CURVE25519_X86 is not set > > > > # > > # Authenticated Encryption with Associated Data > > # > > CONFIG_CRYPTO_CCM=m > > CONFIG_CRYPTO_GCM=y > > # CONFIG_CRYPTO_CHACHA20POLY1305 is not set > > # CONFIG_CRYPTO_AEGIS128 is not set > > # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set > > CONFIG_CRYPTO_SEQIV=y > > CONFIG_CRYPTO_ECHAINIV=y > > > > # > > # Block modes > > # > > CONFIG_CRYPTO_CBC=y > > # CONFIG_CRYPTO_CFB is not set > > CONFIG_CRYPTO_CTR=y > > # CONFIG_CRYPTO_CTS is not set > > CONFIG_CRYPTO_ECB=y > > # CONFIG_CRYPTO_LRW is not set > > # CONFIG_CRYPTO_OFB is not set > > CONFIG_CRYPTO_PCBC=y > > # CONFIG_CRYPTO_XTS is not set > > # CONFIG_CRYPTO_KEYWRAP is not set > > # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set > > # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set > > # CONFIG_CRYPTO_ADIANTUM is not set > > # CONFIG_CRYPTO_ESSIV is not set > > > > # > > # Hash modes > > # > > CONFIG_CRYPTO_CMAC=m > > CONFIG_CRYPTO_HMAC=y > > # CONFIG_CRYPTO_XCBC is not set > > # CONFIG_CRYPTO_VMAC is not set > > > > # > > # Digest > > # > > CONFIG_CRYPTO_CRC32C=y > > # CONFIG_CRYPTO_CRC32C_INTEL is not set > > CONFIG_CRYPTO_CRC32=m > > # CONFIG_CRYPTO_CRC32_PCLMUL is not set > > CONFIG_CRYPTO_XXHASH=y > > CONFIG_CRYPTO_BLAKE2B=y > > # CONFIG_CRYPTO_BLAKE2S is not set > > # CONFIG_CRYPTO_BLAKE2S_X86 is not set > > CONFIG_CRYPTO_CRCT10DIF=y > > # CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set > > CONFIG_CRYPTO_GHASH=y > > # CONFIG_CRYPTO_POLY1305 is not set > > # CONFIG_CRYPTO_POLY1305_X86_64 is not set > > CONFIG_CRYPTO_MD4=m > > CONFIG_CRYPTO_MD5=y > > # CONFIG_CRYPTO_MICHAEL_MIC is not set > > # CONFIG_CRYPTO_RMD128 is not set > > # CONFIG_CRYPTO_RMD160 is not set > > # CONFIG_CRYPTO_RMD256 is not set > > # CONFIG_CRYPTO_RMD320 is not set > > CONFIG_CRYPTO_SHA1=y > > # CONFIG_CRYPTO_SHA1_SSSE3 is not set > > # CONFIG_CRYPTO_SHA256_SSSE3 is not set > > # CONFIG_CRYPTO_SHA512_SSSE3 is not set > > CONFIG_CRYPTO_SHA256=y > > CONFIG_CRYPTO_SHA512=m > > # CONFIG_CRYPTO_SHA3 is not set > > # CONFIG_CRYPTO_SM3 is not set > > # CONFIG_CRYPTO_STREEBOG is not set > > # CONFIG_CRYPTO_TGR192 is not set > > # CONFIG_CRYPTO_WP512 is not set > > # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set > > > > # > > # Ciphers > > # > > CONFIG_CRYPTO_AES=y > > # CONFIG_CRYPTO_AES_TI is not set > > # CONFIG_CRYPTO_AES_NI_INTEL is not set > > # CONFIG_CRYPTO_ANUBIS is not set > > CONFIG_CRYPTO_ARC4=m > > # CONFIG_CRYPTO_BLOWFISH is not set > > # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set > > # CONFIG_CRYPTO_CAMELLIA is not set > > # CONFIG_CRYPTO_CAMELLIA_X86_64 is not set > > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set > > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set > > # CONFIG_CRYPTO_CAST5 is not set > > # CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set > > # CONFIG_CRYPTO_CAST6 is not set > > # CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set > > CONFIG_CRYPTO_DES=y > > # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set > > CONFIG_CRYPTO_FCRYPT=y > > # CONFIG_CRYPTO_KHAZAD is not set > > # CONFIG_CRYPTO_SALSA20 is not set > > # CONFIG_CRYPTO_CHACHA20 is not set > > # CONFIG_CRYPTO_CHACHA20_X86_64 is not set > > # CONFIG_CRYPTO_SEED is not set > > # CONFIG_CRYPTO_SERPENT is not set > > # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set > > # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set > > # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set > > # CONFIG_CRYPTO_SM4 is not set > > # CONFIG_CRYPTO_TEA is not set > > # CONFIG_CRYPTO_TWOFISH is not set > > # CONFIG_CRYPTO_TWOFISH_X86_64 is not set > > # CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set > > # CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set > > > > # > > # Compression > > # > > CONFIG_CRYPTO_DEFLATE=y > > CONFIG_CRYPTO_LZO=m > > # CONFIG_CRYPTO_842 is not set > > # CONFIG_CRYPTO_LZ4 is not set > > # CONFIG_CRYPTO_LZ4HC is not set > > # CONFIG_CRYPTO_ZSTD is not set > > > > # > > # Random Number Generation > > # > > # CONFIG_CRYPTO_ANSI_CPRNG is not set > > CONFIG_CRYPTO_DRBG_MENU=y > > CONFIG_CRYPTO_DRBG_HMAC=y > > # CONFIG_CRYPTO_DRBG_HASH is not set > > # CONFIG_CRYPTO_DRBG_CTR is not set > > CONFIG_CRYPTO_DRBG=y > > CONFIG_CRYPTO_JITTERENTROPY=y > > CONFIG_CRYPTO_USER_API=y > > CONFIG_CRYPTO_USER_API_HASH=y > > # CONFIG_CRYPTO_USER_API_SKCIPHER is not set > > # CONFIG_CRYPTO_USER_API_RNG is not set > > # CONFIG_CRYPTO_USER_API_AEAD is not set > > CONFIG_CRYPTO_HASH_INFO=y > > > > # > > # Crypto library routines > > # > > CONFIG_CRYPTO_LIB_AES=y > > CONFIG_CRYPTO_LIB_ARC4=m > > # CONFIG_CRYPTO_LIB_BLAKE2S is not set > > CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y > > CONFIG_CRYPTO_LIB_CHACHA=y > > # CONFIG_CRYPTO_LIB_CURVE25519 is not set > > CONFIG_CRYPTO_LIB_DES=y > > CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 > > CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y > > CONFIG_CRYPTO_LIB_POLY1305=y > > CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y > > CONFIG_CRYPTO_LIB_SHA256=y > > # CONFIG_CRYPTO_HW is not set > > CONFIG_ASYMMETRIC_KEY_TYPE=y > > CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y > > # CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set > > CONFIG_X509_CERTIFICATE_PARSER=y > > # CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set > > CONFIG_PKCS7_MESSAGE_PARSER=y > > CONFIG_PKCS7_TEST_KEY=y > > CONFIG_SIGNED_PE_FILE_VERIFICATION=y > > > > # > > # Certificates for signature checking > > # > > CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" > > CONFIG_SYSTEM_TRUSTED_KEYRING=y > > CONFIG_SYSTEM_TRUSTED_KEYS="" > > CONFIG_SYSTEM_EXTRA_CERTIFICATE=y > > CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 > > CONFIG_SECONDARY_TRUSTED_KEYRING=y > > CONFIG_SYSTEM_BLACKLIST_KEYRING=y > > CONFIG_SYSTEM_BLACKLIST_HASH_LIST="/data/modsign/blacklist" > > # end of Certificates for signature checking > > > > CONFIG_BINARY_PRINTF=y > > > > # > > # Library routines > > # > > CONFIG_RAID6_PQ=y > > CONFIG_RAID6_PQ_BENCHMARK=y > > # CONFIG_PACKING is not set > > CONFIG_BITREVERSE=y > > CONFIG_GENERIC_STRNCPY_FROM_USER=y > > CONFIG_GENERIC_STRNLEN_USER=y > > CONFIG_GENERIC_NET_UTILS=y > > CONFIG_GENERIC_FIND_FIRST_BIT=y > > # CONFIG_CORDIC is not set > > CONFIG_RATIONAL=y > > CONFIG_GENERIC_PCI_IOMAP=y > > CONFIG_GENERIC_IOMAP=y > > CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y > > CONFIG_ARCH_HAS_FAST_MULTIPLIER=y > > CONFIG_CRC_CCITT=y > > CONFIG_CRC16=y > > CONFIG_CRC_T10DIF=y > > CONFIG_CRC_ITU_T=y > > CONFIG_CRC32=y > > # CONFIG_CRC32_SELFTEST is not set > > CONFIG_CRC32_SLICEBY8=y > > # CONFIG_CRC32_SLICEBY4 is not set > > # CONFIG_CRC32_SARWATE is not set > > # CONFIG_CRC32_BIT is not set > > # CONFIG_CRC64 is not set > > # CONFIG_CRC4 is not set > > # CONFIG_CRC7 is not set > > CONFIG_LIBCRC32C=y > > # CONFIG_CRC8 is not set > > CONFIG_XXHASH=y > > # CONFIG_RANDOM32_SELFTEST is not set > > CONFIG_ZLIB_INFLATE=y > > CONFIG_ZLIB_DEFLATE=y > > CONFIG_LZO_COMPRESS=y > > CONFIG_LZO_DECOMPRESS=y > > CONFIG_ZSTD_COMPRESS=y > > CONFIG_ZSTD_DECOMPRESS=y > > CONFIG_XZ_DEC=y > > CONFIG_XZ_DEC_X86=y > > # CONFIG_XZ_DEC_POWERPC is not set > > # CONFIG_XZ_DEC_IA64 is not set > > # CONFIG_XZ_DEC_ARM is not set > > # CONFIG_XZ_DEC_ARMTHUMB is not set > > # CONFIG_XZ_DEC_SPARC is not set > > CONFIG_XZ_DEC_BCJ=y > > # CONFIG_XZ_DEC_TEST is not set > > CONFIG_DECOMPRESS_GZIP=y > > CONFIG_GENERIC_ALLOCATOR=y > > CONFIG_INTERVAL_TREE=y > > CONFIG_ASSOCIATIVE_ARRAY=y > > CONFIG_HAS_IOMEM=y > > CONFIG_HAS_IOPORT_MAP=y > > CONFIG_HAS_DMA=y > > CONFIG_NEED_SG_DMA_LENGTH=y > > CONFIG_NEED_DMA_MAP_STATE=y > > CONFIG_ARCH_DMA_ADDR_T_64BIT=y > > CONFIG_SWIOTLB=y > > # CONFIG_DMA_API_DEBUG is not set > > CONFIG_SGL_ALLOC=y > > CONFIG_IOMMU_HELPER=y > > CONFIG_CHECK_SIGNATURE=y > > CONFIG_CPU_RMAP=y > > CONFIG_DQL=y > > CONFIG_GLOB=y > > # CONFIG_GLOB_SELFTEST is not set > > CONFIG_NLATTR=y > > CONFIG_CLZ_TAB=y > > # CONFIG_IRQ_POLL is not set > > CONFIG_MPILIB=y > > CONFIG_OID_REGISTRY=y > > CONFIG_UCS2_STRING=y > > CONFIG_HAVE_GENERIC_VDSO=y > > CONFIG_GENERIC_GETTIMEOFDAY=y > > CONFIG_GENERIC_VDSO_TIME_NS=y > > CONFIG_FONT_SUPPORT=y > > CONFIG_FONT_8x16=y > > CONFIG_FONT_AUTOSELECT=y > > CONFIG_SG_POOL=y > > CONFIG_ARCH_HAS_PMEM_API=y > > CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y > > CONFIG_ARCH_HAS_UACCESS_MCSAFE=y > > CONFIG_ARCH_STACKWALK=y > > CONFIG_SBITMAP=y > > # CONFIG_STRING_SELFTEST is not set > > # end of Library routines > > > > # > > # Kernel hacking > > # > > > > # > > # printk and dmesg options > > # > > # CONFIG_PRINTK_TIME is not set > > # CONFIG_PRINTK_CALLER is not set > > CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 > > CONFIG_CONSOLE_LOGLEVEL_QUIET=4 > > CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 > > # CONFIG_BOOT_PRINTK_DELAY is not set > > # CONFIG_DYNAMIC_DEBUG is not set > > CONFIG_SYMBOLIC_ERRNAME=y > > CONFIG_DEBUG_BUGVERBOSE=y > > # end of printk and dmesg options > > > > # > > # Compile-time checks and compiler options > > # > > CONFIG_DEBUG_INFO=y > > # CONFIG_DEBUG_INFO_REDUCED is not set > > # CONFIG_DEBUG_INFO_SPLIT is not set > > # CONFIG_DEBUG_INFO_DWARF4 is not set > > # CONFIG_DEBUG_INFO_BTF is not set > > # CONFIG_GDB_SCRIPTS is not set > > # CONFIG_ENABLE_MUST_CHECK is not set > > CONFIG_FRAME_WARN=2048 > > # CONFIG_STRIP_ASM_SYMS is not set > > # CONFIG_READABLE_ASM is not set > > CONFIG_HEADERS_INSTALL=y > > CONFIG_DEBUG_SECTION_MISMATCH=y > > CONFIG_SECTION_MISMATCH_WARN_ONLY=y > > CONFIG_STACK_VALIDATION=y > > # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set > > # end of Compile-time checks and compiler options > > > > # > > # Generic Kernel Debugging Instruments > > # > > CONFIG_MAGIC_SYSRQ=y > > CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 > > CONFIG_MAGIC_SYSRQ_SERIAL=y > > CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" > > CONFIG_DEBUG_FS=y > > CONFIG_HAVE_ARCH_KGDB=y > > # CONFIG_KGDB is not set > > CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y > > # CONFIG_UBSAN is not set > > # end of Generic Kernel Debugging Instruments > > > > CONFIG_DEBUG_KERNEL=y > > CONFIG_DEBUG_MISC=y > > > > # > > # Memory Debugging > > # > > # CONFIG_PAGE_EXTENSION is not set > > # CONFIG_DEBUG_PAGEALLOC is not set > > # CONFIG_PAGE_OWNER is not set > > # CONFIG_PAGE_POISONING is not set > > # CONFIG_DEBUG_PAGE_REF is not set > > # CONFIG_DEBUG_RODATA_TEST is not set > > CONFIG_GENERIC_PTDUMP=y > > # CONFIG_PTDUMP_DEBUGFS is not set > > # CONFIG_DEBUG_OBJECTS is not set > > # CONFIG_DEBUG_SLAB is not set > > CONFIG_HAVE_DEBUG_KMEMLEAK=y > > # CONFIG_DEBUG_KMEMLEAK is not set > > # CONFIG_DEBUG_STACK_USAGE is not set > > # CONFIG_SCHED_STACK_END_CHECK is not set > > # CONFIG_DEBUG_VM is not set > > CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y > > # CONFIG_DEBUG_VIRTUAL is not set > > # CONFIG_DEBUG_MEMORY_INIT is not set > > # CONFIG_DEBUG_PER_CPU_MAPS is not set > > CONFIG_HAVE_ARCH_KASAN=y > > CONFIG_HAVE_ARCH_KASAN_VMALLOC=y > > CONFIG_CC_HAS_KASAN_GENERIC=y > > # CONFIG_KASAN is not set > > CONFIG_KASAN_STACK=1 > > # end of Memory Debugging > > > > # CONFIG_DEBUG_SHIRQ is not set > > > > # > > # Debug Oops, Lockups and Hangs > > # > > # CONFIG_PANIC_ON_OOPS is not set > > CONFIG_PANIC_ON_OOPS_VALUE=0 > > CONFIG_PANIC_TIMEOUT=0 > > CONFIG_LOCKUP_DETECTOR=y > > CONFIG_SOFTLOCKUP_DETECTOR=y > > # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set > > CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 > > CONFIG_HARDLOCKUP_DETECTOR_PERF=y > > CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y > > CONFIG_HARDLOCKUP_DETECTOR=y > > # CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set > > CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 > > CONFIG_DETECT_HUNG_TASK=y > > CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 > > # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set > > CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 > > CONFIG_WQ_WATCHDOG=y > > # CONFIG_TEST_LOCKUP is not set > > # end of Debug Oops, Lockups and Hangs > > > > # > > # Scheduler Debugging > > # > > # CONFIG_SCHED_DEBUG is not set > > CONFIG_SCHED_INFO=y > > # CONFIG_SCHEDSTATS is not set > > # end of Scheduler Debugging > > > > # CONFIG_DEBUG_TIMEKEEPING is not set > > > > # > > # Lock Debugging (spinlocks, mutexes, etc...) > > # > > CONFIG_LOCK_DEBUGGING_SUPPORT=y > > # CONFIG_PROVE_LOCKING is not set > > # CONFIG_LOCK_STAT is not set > > CONFIG_DEBUG_RT_MUTEXES=y > > CONFIG_DEBUG_SPINLOCK=y > > CONFIG_DEBUG_MUTEXES=y > > # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set > > # CONFIG_DEBUG_RWSEMS is not set > > # CONFIG_DEBUG_LOCK_ALLOC is not set > > # CONFIG_DEBUG_ATOMIC_SLEEP is not set > > # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set > > # CONFIG_LOCK_TORTURE_TEST is not set > > # CONFIG_WW_MUTEX_SELFTEST is not set > > # end of Lock Debugging (spinlocks, mutexes, etc...) > > > > CONFIG_STACKTRACE=y > > # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set > > # CONFIG_DEBUG_KOBJECT is not set > > > > # > > # Debug kernel data structures > > # > > # CONFIG_DEBUG_LIST is not set > > # CONFIG_DEBUG_PLIST is not set > > # CONFIG_DEBUG_SG is not set > > # CONFIG_DEBUG_NOTIFIERS is not set > > # CONFIG_BUG_ON_DATA_CORRUPTION is not set > > # end of Debug kernel data structures > > > > # CONFIG_DEBUG_CREDENTIALS is not set > > > > # > > # RCU Debugging > > # > > # CONFIG_RCU_PERF_TEST is not set > > # CONFIG_RCU_TORTURE_TEST is not set > > CONFIG_RCU_CPU_STALL_TIMEOUT=60 > > # CONFIG_RCU_TRACE is not set > > # CONFIG_RCU_EQS_DEBUG is not set > > # end of RCU Debugging > > > > # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set > > # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set > > # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set > > # CONFIG_LATENCYTOP is not set > > CONFIG_USER_STACKTRACE_SUPPORT=y > > CONFIG_NOP_TRACER=y > > CONFIG_HAVE_FUNCTION_TRACER=y > > CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y > > CONFIG_HAVE_DYNAMIC_FTRACE=y > > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y > > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y > > CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y > > CONFIG_HAVE_SYSCALL_TRACEPOINTS=y > > CONFIG_HAVE_FENTRY=y > > CONFIG_HAVE_C_RECORDMCOUNT=y > > CONFIG_TRACE_CLOCK=y > > CONFIG_RING_BUFFER=y > > CONFIG_EVENT_TRACING=y > > CONFIG_CONTEXT_SWITCH_TRACER=y > > CONFIG_TRACING=y > > CONFIG_GENERIC_TRACER=y > > CONFIG_TRACING_SUPPORT=y > > CONFIG_FTRACE=y > > # CONFIG_BOOTTIME_TRACING is not set > > CONFIG_FUNCTION_TRACER=y > > CONFIG_FUNCTION_GRAPH_TRACER=y > > CONFIG_DYNAMIC_FTRACE=y > > CONFIG_DYNAMIC_FTRACE_WITH_REGS=y > > CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y > > # CONFIG_FUNCTION_PROFILER is not set > > # CONFIG_STACK_TRACER is not set > > # CONFIG_PREEMPTIRQ_EVENTS is not set > > # CONFIG_IRQSOFF_TRACER is not set > > # CONFIG_SCHED_TRACER is not set > > # CONFIG_HWLAT_TRACER is not set > > # CONFIG_MMIOTRACE is not set > > CONFIG_FTRACE_SYSCALLS=y > > # CONFIG_TRACER_SNAPSHOT is not set > > CONFIG_BRANCH_PROFILE_NONE=y > > # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set > > # CONFIG_PROFILE_ALL_BRANCHES is not set > > # CONFIG_BLK_DEV_IO_TRACE is not set > > CONFIG_KPROBE_EVENTS=y > > # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set > > # CONFIG_UPROBE_EVENTS is not set > > CONFIG_BPF_EVENTS=y > > CONFIG_DYNAMIC_EVENTS=y > > CONFIG_PROBE_EVENTS=y > > # CONFIG_BPF_KPROBE_OVERRIDE is not set > > CONFIG_FTRACE_MCOUNT_RECORD=y > > # CONFIG_HIST_TRIGGERS is not set > > # CONFIG_TRACE_EVENT_INJECT is not set > > # CONFIG_TRACEPOINT_BENCHMARK is not set > > # CONFIG_RING_BUFFER_BENCHMARK is not set > > # CONFIG_TRACE_EVAL_MAP_FILE is not set > > # CONFIG_FTRACE_STARTUP_TEST is not set > > # CONFIG_RING_BUFFER_STARTUP_TEST is not set > > # CONFIG_PREEMPTIRQ_DELAY_TEST is not set > > # CONFIG_KPROBE_EVENT_GEN_TEST is not set > > # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set > > CONFIG_SAMPLES=y > > # CONFIG_SAMPLE_TRACE_EVENTS is not set > > # CONFIG_SAMPLE_TRACE_PRINTK is not set > > # CONFIG_SAMPLE_FTRACE_DIRECT is not set > > # CONFIG_SAMPLE_TRACE_ARRAY is not set > > # CONFIG_SAMPLE_KOBJECT is not set > > # CONFIG_SAMPLE_KPROBES is not set > > # CONFIG_SAMPLE_HW_BREAKPOINT is not set > > # CONFIG_SAMPLE_KFIFO is not set > > # CONFIG_SAMPLE_LIVEPATCH is not set > > # CONFIG_SAMPLE_CONFIGFS is not set > > # CONFIG_SAMPLE_HIDRAW is not set > > # CONFIG_SAMPLE_PIDFD is not set > > # CONFIG_SAMPLE_SECCOMP is not set > > # CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set > > CONFIG_SAMPLE_VFS=y > > # CONFIG_SAMPLE_INTEL_MEI is not set > > CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y > > > > # > > # x86 Debugging > > # > > CONFIG_TRACE_IRQFLAGS_SUPPORT=y > > CONFIG_X86_VERBOSE_BOOTUP=y > > CONFIG_EARLY_PRINTK=y > > # CONFIG_EARLY_PRINTK_DBGP is not set > > # CONFIG_EARLY_PRINTK_USB_XDBC is not set > > # CONFIG_EFI_PGT_DUMP is not set > > # CONFIG_DEBUG_WX is not set > > CONFIG_DOUBLEFAULT=y > > # CONFIG_DEBUG_TLBFLUSH is not set > > # CONFIG_IOMMU_DEBUG is not set > > CONFIG_HAVE_MMIOTRACE_SUPPORT=y > > # CONFIG_X86_DECODER_SELFTEST is not set > > CONFIG_IO_DELAY_0X80=y > > # CONFIG_IO_DELAY_0XED is not set > > # CONFIG_IO_DELAY_UDELAY is not set > > # CONFIG_IO_DELAY_NONE is not set > > # CONFIG_DEBUG_BOOT_PARAMS is not set > > # CONFIG_CPA_DEBUG is not set > > # CONFIG_DEBUG_ENTRY is not set > > # CONFIG_DEBUG_NMI_SELFTEST is not set > > # CONFIG_X86_DEBUG_FPU is not set > > # CONFIG_PUNIT_ATOM_DEBUG is not set > > CONFIG_UNWINDER_ORC=y > > # CONFIG_UNWINDER_FRAME_POINTER is not set > > # CONFIG_UNWINDER_GUESS is not set > > # end of x86 Debugging > > > > # > > # Kernel Testing and Coverage > > # > > # CONFIG_KUNIT is not set > > # CONFIG_NOTIFIER_ERROR_INJECTION is not set > > CONFIG_FUNCTION_ERROR_INJECTION=y > > # CONFIG_FAULT_INJECTION is not set > > CONFIG_ARCH_HAS_KCOV=y > > CONFIG_CC_HAS_SANCOV_TRACE_PC=y > > # CONFIG_KCOV is not set > > # CONFIG_RUNTIME_TESTING_MENU is not set > > # CONFIG_MEMTEST is not set > > # end of Kernel Testing and Coverage > > # end of Kernel hacking > > -- > Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From jani.nikula at linux.intel.com Mon Jun 8 08:56:33 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Mon, 08 Jun 2020 11:56:33 +0300 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver In-Reply-To: <4ff2445aff8d44c5961a6d194a8f4663@intel.com> References: <2136072.1591491984@warthog.procyon.org.uk> <87o8puxak1.fsf@intel.com> <4ff2445aff8d44c5961a6d194a8f4663@intel.com> Message-ID: <87ftb6x7em.fsf@intel.com> On Mon, 08 Jun 2020, "Saarinen, Jani" <jani.saarinen at intel.com> wrote: > HI, >> -----Original Message----- >> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Jani Nikula >> Sent: maanantai 8. kes?kuuta 2020 10.49 >> To: David Howells <dhowells at redhat.com>; Joonas Lahtinen >> <joonas.lahtinen at linux.intel.com>; Vivi, Rodrigo <rodrigo.vivi at intel.com> >> Cc: intel-gfx at lists.freedesktop.org; linux-kernel at vger.kernel.org; dri- >> devel at lists.freedesktop.org; dhowells at redhat.com; airlied at redhat.com >> Subject: Re: [Intel-gfx] A panic and a hang in the i915 drm driver >> >> On Sun, 07 Jun 2020, David Howells <dhowells at redhat.com> wrote: >> > Hi, >> > >> > I'm seeing the attached oops and panic from the i915 drm driver. I've tried >> > bisecting it, but there's a problem in that one of the merged branches causes >> > the machine to hang without output. > It was not this one? > https://gitlab.freedesktop.org/drm/intel/-/issues/1892 David, please try [1]. Joonas, I think it would be good to have a pull request with that before -rc1 is out. I think the bug is in Linus' tree already but the fix didn't have the annotation. :( BR, Jani. [1] https://cgit.freedesktop.org/drm/drm-tip/commit/?id=22da5d846d54dd13183b57874b9d5611d583d7c8 > > >> >> Cc: Ville and GG, I thought this was fixed (reverted) already. >> >> BR, >> Jani. >> >> >> > >> > The oops for commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 looks like: >> > >> > BUG: kernel NULL pointer dereference, address: 0000000000000000 >> > #PF: supervisor read access in kernel mode >> > #PF: error_code(0x0000) - not-present page >> > PGD 0 P4D 0 >> > Oops: 0000 [#1] SMP PTI >> > CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.7.0-rc2-fscache+ #883 >> > Hardware name: ASUS All Series/H97-PLUS, BIOS 2306 10/09/2014 >> > RIP: 0010:intel_psr_enabled+0xb/0x6e >> > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d >> 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 >> 00 20 75 05 45 31 e4 eb 44 80 >> > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 >> > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 >> > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 >> > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 >> > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 >> > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 >> > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) >> knlGS:0000000000000000 >> > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 >> > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 >> > Call Trace: >> > intel_read_dp_sdp+0x71/0x2c5 >> > hsw_crt_get_config+0x18/0x41 >> > intel_modeset_readout_hw_state+0x24d/0x662 >> > ? do_raw_spin_lock+0x8b/0xcd >> > ? _raw_spin_lock_irqsave+0x10/0x16 >> > intel_modeset_setup_hw_state+0xa8/0xb59 >> > ? __next_node_in+0x39/0x42 >> > ? ww_mutex_lock+0x3d/0x1da >> > ? modeset_lock+0xd4/0x114 >> > ? drm_modeset_lock_all_ctx+0x86/0xcc >> > intel_modeset_init+0x285/0x5bf >> > ? intel_irq_postinstall+0x485/0x4d1 >> > i915_driver_probe+0x1b4/0x49c >> > ? __kernfs_new_node+0x161/0x1b2 >> > ? rpm_resume+0x45e/0x485 >> > i915_pci_probe+0xfd/0x11d >> > ? __pm_runtime_resume+0x51/0x5e >> > local_pci_probe+0x39/0x7a >> > pci_device_probe+0xf5/0x14f >> > ? sysfs_do_create_link_sd.isra.0+0x77/0xa3 >> > really_probe+0x140/0x2a9 >> > driver_probe_device+0x9c/0xd1 >> > device_driver_attach+0x3c/0x55 >> > __driver_attach+0x97/0x9f >> > ? device_driver_attach+0x55/0x55 >> > bus_for_each_dev+0x72/0xa8 >> > bus_add_driver+0x108/0x1b9 >> > driver_register+0x9e/0xd7 >> > ? mipi_dsi_bus_init+0x11/0x11 >> > i915_init+0x58/0x6b >> > do_one_initcall+0x83/0x18a >> > kernel_init_freeable+0x19b/0x1fd >> > ? rest_init+0x9f/0x9f >> > kernel_init+0xa/0xfa >> > ret_from_fork+0x1f/0x30 >> > Modules linked in: >> > CR2: 0000000000000000 >> > ---[ end trace d0c4f561618aeb37 ]--- >> > RIP: 0010:intel_psr_enabled+0xb/0x6e >> > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d >> 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 >> 00 20 75 05 45 31 e4 eb 44 80 >> > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 >> > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 >> > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 >> > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 >> > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 >> > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 >> > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) >> knlGS:0000000000000000 >> > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 >> > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 >> > Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 >> > Kernel Offset: disabled >> > ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 ]--- >> > >> > >> > Decoding the RIP gives: >> > >> > RIP: 0010:intel_psr_enabled (/data/fs/linux- >> fs/build3/../drivers/gpu/drm/i915/display/intel_display_types.h:1595 /data/fs/linux- >> fs/build3/../drivers/gpu/drm/i915/display/intel_psr.c:1598) >> > >> > >> > >> > Commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 ("Merge tag >> > 'drm-intel-next-fixes-2020-05-20' of >> > git://anongit.freedesktop.org/drm/drm-intel into drm-next") is definitely bad >> > and logs an oops to the console and panics, but it's a merge. >> > >> > On one side is e20bb857dea2f620ff37ae541ed8aee70e3c89f1 ("Merge tag >> > 'exynos-drm-next-for-v5.8' of >> > git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into >> > drm-next"), which hangs. This is also a merge. >> > >> > One side of e20bb is f84e1ba336a4f47ae251e4d2d8a694902571b0df >> > ("drm/exynos-vidi: convert platform driver to use dev_groups") which is good. >> > >> > The other side of c4121 and e20bb derive from the same line of commits, with >> > three patches between. All of these, down to at least >> > 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 ("drm/i915: Update DRIVER_DATE >> to >> > 20200430") cause the machine to hang without any sort of console output. >> > >> > Commit bfbe1744e4417986419236719922a9a7fda224d1 ("Merge tag >> > 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux >> > into drm-next") is good. >> > >> > Commit 47e51832ae93534d872511ba557115722582d94c >> > ("drm/i915/gvt: use context lrc_reg_state for shadow ppgtt override") is good. >> > >> > I've attached the git log and the config file. >> > >> > David >> > >> > git bisect start >> > # bad: [ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d] afs: Fix file locking >> > git bisect bad ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d >> > # good: [3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162] Linux 5.7 >> > git bisect good 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162 >> > # bad: [2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63] Merge branch >> 'uaccess.comedi' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs >> > git bisect bad 2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63 >> > # good: [cfa3b8068b09f25037146bfd5eed041b78878bee] Merge tag 'for-linus- >> hmm' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma >> > git bisect good cfa3b8068b09f25037146bfd5eed041b78878bee >> > # bad: [c41219fda6e04255c44d37fd2c0d898c1c46abf1] Merge tag 'drm-intel-next- >> fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next >> > git bisect bad c41219fda6e04255c44d37fd2c0d898c1c46abf1 >> > # good: [937eea297e26effac6809a0bf8c20e6ca9d90b9a] Merge tag 'amd-drm- >> next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-next >> > git bisect good 937eea297e26effac6809a0bf8c20e6ca9d90b9a >> > # good: [a1fb548962397bb8609bb46e566809a9a1b30044] Merge tag 'drm-intel- >> next-2020-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next >> > git bisect good a1fb548962397bb8609bb46e566809a9a1b30044 >> > # good: [f84e1ba336a4f47ae251e4d2d8a694902571b0df] drm/exynos-vidi: >> convert platform driver to use dev_groups >> > git bisect good f84e1ba336a4f47ae251e4d2d8a694902571b0df >> > # skip: [d9162348db12487754e61f73497bdcfcea753590] drm/i915: Introduce >> skl_plane_wm_level accessor. >> > git bisect skip d9162348db12487754e61f73497bdcfcea753590 >> > # skip: [84eac0c65940d9633247b0c8c826d4bcb7307351] drm/i915/gt: Force pte >> cacheline to main memory >> > git bisect skip 84eac0c65940d9633247b0c8c826d4bcb7307351 >> > # skip: [802a5820fc0c0f12b40280db3dbaaf8359b07243] drm/i915: Extract >> i915_cs_timestamp_{ns_to_ticks,tick_to_ns}() >> > git bisect skip 802a5820fc0c0f12b40280db3dbaaf8359b07243 >> > # skip: [1c8ee8b92fb6ac9d5975147cc902e8c142eca338] drm/i915/gt: Restore >> Cherryview back to full-ppgtt >> > git bisect skip 1c8ee8b92fb6ac9d5975147cc902e8c142eca338 >> > # skip: [2e2701582a8039b2f8a2fa811237ac8ec98355fa] drm/i915: Nuke pointless >> div by 64bit >> > git bisect skip 2e2701582a8039b2f8a2fa811237ac8ec98355fa >> > # skip: [4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc] drm/i915/gt: Suspend >> tasklets before resume sanitization >> > git bisect skip 4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc >> > # skip: [20f505f2253106f695ba6fa0a415159145a8fb2a] drm/i915: Restrict qgv >> points which don't have enough bandwidth. >> > git bisect skip 20f505f2253106f695ba6fa0a415159145a8fb2a >> > # skip: [d8d5afe35e3f88f73436f79f974d96a67e879637] drm/i915: Make >> active_pipes check skl specific >> > git bisect skip d8d5afe35e3f88f73436f79f974d96a67e879637 >> > # skip: [1be8f347d70b5027b7b223c665756d85feaf36b6] Merge tag 'gvt-next- >> 2020-05-12' of https://github.com/intel/gvt-linux into drm-intel-next-queued >> > git bisect skip 1be8f347d70b5027b7b223c665756d85feaf36b6 >> > # skip: [b428d57006663d18e3f6f98644ff9e8702a33ca4] drm/i915/gt: Reset >> execlists registers before HWSP >> > git bisect skip b428d57006663d18e3f6f98644ff9e8702a33ca4 >> > # skip: [6b6cd2ebd8d071e55998e32b648bb8081f7f02bb] drm/i915: Mark >> concurrent submissions with a weak-dependency >> > git bisect skip 6b6cd2ebd8d071e55998e32b648bb8081f7f02bb >> > # skip: [1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0] drm/i915: Extract skl SAGV >> checking >> > git bisect skip 1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0 >> > # skip: [cafac5a983619944afa639c53f0d5d885616a3d2] drm/i915/dp: Add >> compute routine for DP PSR VSC SDP >> > git bisect skip cafac5a983619944afa639c53f0d5d885616a3d2 >> > # skip: [61b088c5374a9f886efa1edbb49ce552bd1f9cba] drm/i915/ehl: Restrict >> w/a 1607087056 for EHL/JSL >> > git bisect skip 61b088c5374a9f886efa1edbb49ce552bd1f9cba >> > # skip: [2045d666ae634f1676660acfb864bcba0e9f86ca] drm/i915: Ignore submit- >> fences on the same timeline >> > git bisect skip 2045d666ae634f1676660acfb864bcba0e9f86ca >> > # skip: [16e87459673a5cbef35cc0f2e15c664b10a4cdb6] drm/i915/gt: Move the >> batch buffer pool from the engine to the gt >> > git bisect skip 16e87459673a5cbef35cc0f2e15c664b10a4cdb6 >> > # skip: [ce58867ee17afecda7917e74a0d10afd7138c6d4] drm/i915: Fix enabled >> infoframe states of lspcon >> > git bisect skip ce58867ee17afecda7917e74a0d10afd7138c6d4 >> > # skip: [a211da9c771bf97395a3ced83a3aa383372b13a7] drm/i915/gt: Make >> timeslicing an explicit engine property >> > git bisect skip a211da9c771bf97395a3ced83a3aa383372b13a7 >> > # skip: [dee66f3e071b394de16da18e2807f371b789b1be] drm/i915: Add state >> readout for DP HDR Metadata Infoframe SDP >> > git bisect skip dee66f3e071b394de16da18e2807f371b789b1be >> > # skip: [964a9b0f611ee7fedc90641bfcc2efe6ce6206aa] drm/i915/gem: Use >> chained reloc batches >> > git bisect skip 964a9b0f611ee7fedc90641bfcc2efe6ce6206aa >> > # skip: [f1e79c7e183c8e35def44b07ff7ac221fa87bf04] drm/i915: Replace zero- >> length array with flexible-array >> > git bisect skip f1e79c7e183c8e35def44b07ff7ac221fa87bf04 >> > # good: [ab9c21124d6e03460c9c59006a61cc076fefa82e] drm/amdgpu: Add cmd >> to control XGMI link sleep >> > git bisect good ab9c21124d6e03460c9c59006a61cc076fefa82e >> > # skip: [e31fe02eff2610f40ac8d7efe57ec0b881b75508] drm/i915: Make >> intel_timeline_init static >> > git bisect skip e31fe02eff2610f40ac8d7efe57ec0b881b75508 >> > # skip: [d96536f0fe699729a0974eb5b65eb0d87cc747e1] drm/i915: Fix AUX power >> domain toggling across TypeC mode resets >> > git bisect skip d96536f0fe699729a0974eb5b65eb0d87cc747e1 >> > # skip: [a80d73673bc7676d0bab7f7ab51d00c5e461992d] drm/i915: Tidy awaiting >> on dma-fences >> > git bisect skip a80d73673bc7676d0bab7f7ab51d00c5e461992d >> > # skip: [25444ca6cbb9fe375aa9bba58784a735efe2a649] drm/i915/fbc: Require >> linear fb stride to be multiple of 512 bytes on gen9/glk >> > git bisect skip 25444ca6cbb9fe375aa9bba58784a735efe2a649 >> > # skip: [795d4d7fa34154fc621c1048f8b92e4f6bd3926f] drm/i915: Mark the >> addition of the initial-breadcrumb in the request >> > git bisect skip 795d4d7fa34154fc621c1048f8b92e4f6bd3926f >> > # skip: [d19b29be653691a179e54aafc84fc40667a63ee7] drm/i915: Nuke >> mode.vrefresh usage >> > git bisect skip d19b29be653691a179e54aafc84fc40667a63ee7 >> > # skip: [260a6c1bdf1e072ae4d96f0d1ec2917237f1b627] drm/i915: Fix glk >> watermark calculations >> > git bisect skip 260a6c1bdf1e072ae4d96f0d1ec2917237f1b627 >> > # skip: [56f1b31f1dd60db4b02024a13eea45b5bbccc44e] drm/i915: Store CS >> timestamp frequency in Hz >> > git bisect skip 56f1b31f1dd60db4b02024a13eea45b5bbccc44e >> > # skip: [b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d] drm/i915: Remove >> duplicate inline specifier on write_pte >> > git bisect skip b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d >> > # skip: [0065e5f5cc56136da0be900c4a3121b38a82f37d] drm/i915/display: Warn if >> the FBC is still writing to stolen on removal >> > git bisect skip 0065e5f5cc56136da0be900c4a3121b38a82f37d >> > # skip: [0398993b82f40ad02d88da7c894e3faae2da3b0a] drm/i915: Stash hpd >> status bits under dev_priv >> > git bisect skip 0398993b82f40ad02d88da7c894e3faae2da3b0a >> > # skip: [7241c57d3140ad3b613777a8515ffe1f653d4800] drm/i915: Add TGL+ SAGV >> support >> > git bisect skip 7241c57d3140ad3b613777a8515ffe1f653d4800 >> > # skip: [c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5] drm/i915: Use stashed >> away hpd isr bits in intel_digital_port_connected() >> > git bisect skip c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5 >> > # skip: [f136c58a0de98e1b56483b7fc8c209dba0a496d9] drm/i915: Added required >> new PCode commands >> > git bisect skip f136c58a0de98e1b56483b7fc8c209dba0a496d9 >> > # skip: [9bad40a27dac1f88012a1e2db0bfc5ae58fa0370] drm/i915/selftests: >> Always flush before unpining after writing >> > git bisect skip 9bad40a27dac1f88012a1e2db0bfc5ae58fa0370 >> > # skip: [977253df6433f85d5e2cb3ab0f8eb4127f8173dd] drm/i915/gt: Stop holding >> onto the pinned_default_state >> > git bisect skip 977253df6433f85d5e2cb3ab0f8eb4127f8173dd >> > # skip: [a1b2eeacbc55573afc56341e08b506aee6451c3d] drm/i915: Remove >> unused HAS_FWTABLE macro >> > git bisect skip a1b2eeacbc55573afc56341e08b506aee6451c3d >> > # skip: [24fe5f2ab2478053d50a3bc629ada895903a5cbc] drm/i915: Propagate >> error from completed fences >> > git bisect skip 24fe5f2ab2478053d50a3bc629ada895903a5cbc >> > # skip: [73e28cc40bf00b5d168cb8f5cff1ae63e9097446] drm/i915: Handle idling >> during i915_gem_evict_something busy loops >> > git bisect skip 73e28cc40bf00b5d168cb8f5cff1ae63e9097446 >> > # skip: [f02ac414ba9497d1887b1de7fe69954284f157ac] Revert "drm/i915/tgl: >> Include ro parts of l3 to invalidate" >> > git bisect skip f02ac414ba9497d1887b1de7fe69954284f157ac >> > # skip: [b0a997ae5248b293b6f6d1996ea49c57f7b94227] drm/i915: Emit >> await(batch) before MI_BB_START >> > git bisect skip b0a997ae5248b293b6f6d1996ea49c57f7b94227 >> > # skip: [32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa] drm/i915/gen12: Fix HDC >> pipeline flush >> > git bisect skip 32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa >> > # good: [5e7067b24fcf1549c72988dd92de6d17ff3d2077] drm/amdgpu: Add DPM >> function for XGMI link power down control >> > git bisect good 5e7067b24fcf1549c72988dd92de6d17ff3d2077 >> > # skip: [d248b371f7479a99caccf91da2ec6adee85e5e70] drm/i915/gen12: >> Invalidate aux table entries forcibly >> > git bisect skip d248b371f7479a99caccf91da2ec6adee85e5e70 >> > # good: [b7f0656a25467fc26eb7fc375caf38ee99f5d004] drm/amdgpu: Updated >> XGMI power down control support check >> > git bisect good b7f0656a25467fc26eb7fc375caf38ee99f5d004 >> > # good: [4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240] drm/amdgpu: optimize >> amdgpu device attribute code >> > git bisect good 4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240 >> > # skip: [f45ce9336ff0640e491c642a84ea02f21daac3a4] video/hdmi: Add Unpack >> only function for DRM infoframe >> > git bisect skip f45ce9336ff0640e491c642a84ea02f21daac3a4 >> > # good: [bfbe1744e4417986419236719922a9a7fda224d1] Merge tag 'amd-drm- >> next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux into drm-next >> > git bisect good bfbe1744e4417986419236719922a9a7fda224d1 >> > # skip: [701f026521980dd0151130f818558e17c608ed2e] drm/i915: Drop >> I915_RESET_TIMEOUT and friends >> > git bisect skip 701f026521980dd0151130f818558e17c608ed2e >> > # skip: [378974f7f9754acfd5630327917c6b813495f1a9] drm/i915: Allow some >> leniency in PCU reads >> > git bisect skip 378974f7f9754acfd5630327917c6b813495f1a9 >> > # good: [47e51832ae93534d872511ba557115722582d94c] drm/i915/gvt: use >> context lrc_reg_state for shadow ppgtt override >> > git bisect good 47e51832ae93534d872511ba557115722582d94c >> > # skip: [230982d8d8df7f9d9aa216840ea2db1df6ad5d37] drm/i915: Update >> DRIVER_DATE to 20200430 >> > git bisect skip 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 >> > # >> > # Automatically generated file; DO NOT EDIT. >> > # Linux/x86_64 5.7.0-rc2 Kernel Configuration >> > # >> > >> > # >> > # Compiler: x86_64-linux-gnu-gcc (GCC) 9.2.1 20190827 (Red Hat Cross 9.2.1-3) >> > # >> > CONFIG_CC_IS_GCC=y >> > CONFIG_GCC_VERSION=90201 >> > CONFIG_LD_VERSION=234000000 >> > CONFIG_CLANG_VERSION=0 >> > CONFIG_CC_HAS_ASM_GOTO=y >> > CONFIG_CC_HAS_ASM_INLINE=y >> > CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y >> > CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y >> > CONFIG_IRQ_WORK=y >> > CONFIG_BUILDTIME_TABLE_SORT=y >> > CONFIG_THREAD_INFO_IN_TASK=y >> > >> > # >> > # General setup >> > # >> > CONFIG_INIT_ENV_ARG_LIMIT=32 >> > # CONFIG_COMPILE_TEST is not set >> > CONFIG_LOCALVERSION="-fscache" >> > # CONFIG_LOCALVERSION_AUTO is not set >> > CONFIG_BUILD_SALT="" >> > CONFIG_HAVE_KERNEL_GZIP=y >> > CONFIG_HAVE_KERNEL_BZIP2=y >> > CONFIG_HAVE_KERNEL_LZMA=y >> > CONFIG_HAVE_KERNEL_XZ=y >> > CONFIG_HAVE_KERNEL_LZO=y >> > CONFIG_HAVE_KERNEL_LZ4=y >> > # CONFIG_KERNEL_GZIP is not set >> > # CONFIG_KERNEL_BZIP2 is not set >> > # CONFIG_KERNEL_LZMA is not set >> > CONFIG_KERNEL_XZ=y >> > # CONFIG_KERNEL_LZO is not set >> > # CONFIG_KERNEL_LZ4 is not set >> > CONFIG_DEFAULT_HOSTNAME="(none)" >> > CONFIG_SWAP=y >> > CONFIG_SYSVIPC=y >> > CONFIG_SYSVIPC_SYSCTL=y >> > CONFIG_POSIX_MQUEUE=y >> > CONFIG_POSIX_MQUEUE_SYSCTL=y >> > CONFIG_CROSS_MEMORY_ATTACH=y >> > # CONFIG_USELIB is not set >> > CONFIG_AUDIT=y >> > CONFIG_HAVE_ARCH_AUDITSYSCALL=y >> > CONFIG_AUDITSYSCALL=y >> > >> > # >> > # IRQ subsystem >> > # >> > CONFIG_GENERIC_IRQ_PROBE=y >> > CONFIG_GENERIC_IRQ_SHOW=y >> > CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y >> > CONFIG_GENERIC_PENDING_IRQ=y >> > CONFIG_GENERIC_IRQ_MIGRATION=y >> > CONFIG_HARDIRQS_SW_RESEND=y >> > CONFIG_IRQ_DOMAIN=y >> > CONFIG_IRQ_DOMAIN_HIERARCHY=y >> > CONFIG_GENERIC_MSI_IRQ=y >> > CONFIG_GENERIC_MSI_IRQ_DOMAIN=y >> > CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y >> > CONFIG_GENERIC_IRQ_RESERVATION_MODE=y >> > CONFIG_IRQ_FORCED_THREADING=y >> > CONFIG_SPARSE_IRQ=y >> > # CONFIG_GENERIC_IRQ_DEBUGFS is not set >> > # end of IRQ subsystem >> > >> > CONFIG_CLOCKSOURCE_WATCHDOG=y >> > CONFIG_ARCH_CLOCKSOURCE_INIT=y >> > CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y >> > CONFIG_GENERIC_TIME_VSYSCALL=y >> > CONFIG_GENERIC_CLOCKEVENTS=y >> > CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y >> > CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y >> > CONFIG_GENERIC_CMOS_UPDATE=y >> > >> > # >> > # Timers subsystem >> > # >> > CONFIG_TICK_ONESHOT=y >> > CONFIG_NO_HZ_COMMON=y >> > # CONFIG_HZ_PERIODIC is not set >> > # CONFIG_NO_HZ_IDLE is not set >> > CONFIG_NO_HZ_FULL=y >> > CONFIG_CONTEXT_TRACKING=y >> > CONFIG_CONTEXT_TRACKING_FORCE=y >> > # CONFIG_NO_HZ is not set >> > CONFIG_HIGH_RES_TIMERS=y >> > # end of Timers subsystem >> > >> > CONFIG_PREEMPT_NONE=y >> > # CONFIG_PREEMPT_VOLUNTARY is not set >> > # CONFIG_PREEMPT is not set >> > >> > # >> > # CPU/Task time and stats accounting >> > # >> > CONFIG_VIRT_CPU_ACCOUNTING=y >> > CONFIG_VIRT_CPU_ACCOUNTING_GEN=y >> > # CONFIG_IRQ_TIME_ACCOUNTING is not set >> > # CONFIG_SCHED_THERMAL_PRESSURE is not set >> > CONFIG_BSD_PROCESS_ACCT=y >> > CONFIG_BSD_PROCESS_ACCT_V3=y >> > CONFIG_TASKSTATS=y >> > CONFIG_TASK_DELAY_ACCT=y >> > CONFIG_TASK_XACCT=y >> > CONFIG_TASK_IO_ACCOUNTING=y >> > # CONFIG_PSI is not set >> > # end of CPU/Task time and stats accounting >> > >> > CONFIG_CPU_ISOLATION=y >> > >> > # >> > # RCU Subsystem >> > # >> > CONFIG_TREE_RCU=y >> > # CONFIG_RCU_EXPERT is not set >> > CONFIG_SRCU=y >> > CONFIG_TREE_SRCU=y >> > CONFIG_RCU_STALL_COMMON=y >> > CONFIG_RCU_NEED_SEGCBLIST=y >> > CONFIG_RCU_NOCB_CPU=y >> > # end of RCU Subsystem >> > >> > CONFIG_BUILD_BIN2C=y >> > # CONFIG_IKCONFIG is not set >> > # CONFIG_IKHEADERS is not set >> > CONFIG_LOG_BUF_SHIFT=16 >> > CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 >> > CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 >> > CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y >> > >> > # >> > # Scheduler features >> > # >> > # CONFIG_UCLAMP_TASK is not set >> > # end of Scheduler features >> > >> > CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y >> > CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y >> > CONFIG_CC_HAS_INT128=y >> > CONFIG_ARCH_SUPPORTS_INT128=y >> > # CONFIG_NUMA_BALANCING is not set >> > CONFIG_CGROUPS=y >> > CONFIG_PAGE_COUNTER=y >> > CONFIG_MEMCG=y >> > CONFIG_MEMCG_SWAP=y >> > CONFIG_MEMCG_SWAP_ENABLED=y >> > CONFIG_MEMCG_KMEM=y >> > CONFIG_BLK_CGROUP=y >> > CONFIG_CGROUP_WRITEBACK=y >> > CONFIG_CGROUP_SCHED=y >> > CONFIG_FAIR_GROUP_SCHED=y >> > # CONFIG_CFS_BANDWIDTH is not set >> > # CONFIG_RT_GROUP_SCHED is not set >> > # CONFIG_CGROUP_PIDS is not set >> > CONFIG_CGROUP_RDMA=y >> > CONFIG_CGROUP_FREEZER=y >> > CONFIG_CGROUP_HUGETLB=y >> > CONFIG_CPUSETS=y >> > CONFIG_PROC_PID_CPUSET=y >> > CONFIG_CGROUP_DEVICE=y >> > CONFIG_CGROUP_CPUACCT=y >> > CONFIG_CGROUP_PERF=y >> > # CONFIG_CGROUP_BPF is not set >> > # CONFIG_CGROUP_DEBUG is not set >> > CONFIG_SOCK_CGROUP_DATA=y >> > CONFIG_NAMESPACES=y >> > CONFIG_UTS_NS=y >> > CONFIG_TIME_NS=y >> > CONFIG_IPC_NS=y >> > CONFIG_USER_NS=y >> > CONFIG_PID_NS=y >> > CONFIG_NET_NS=y >> > # CONFIG_CHECKPOINT_RESTORE is not set >> > # CONFIG_SCHED_AUTOGROUP is not set >> > # CONFIG_SYSFS_DEPRECATED is not set >> > CONFIG_RELAY=y >> > CONFIG_BLK_DEV_INITRD=y >> > CONFIG_INITRAMFS_SOURCE="" >> > CONFIG_RD_GZIP=y >> > # CONFIG_RD_BZIP2 is not set >> > # CONFIG_RD_LZMA is not set >> > # CONFIG_RD_XZ is not set >> > # CONFIG_RD_LZO is not set >> > # CONFIG_RD_LZ4 is not set >> > # CONFIG_BOOT_CONFIG is not set >> > # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set >> > CONFIG_CC_OPTIMIZE_FOR_SIZE=y >> > CONFIG_SYSCTL=y >> > CONFIG_HAVE_UID16=y >> > CONFIG_SYSCTL_EXCEPTION_TRACE=y >> > CONFIG_HAVE_PCSPKR_PLATFORM=y >> > CONFIG_BPF=y >> > CONFIG_EXPERT=y >> > CONFIG_UID16=y >> > CONFIG_MULTIUSER=y >> > # CONFIG_SGETMASK_SYSCALL is not set >> > # CONFIG_SYSFS_SYSCALL is not set >> > CONFIG_FHANDLE=y >> > CONFIG_POSIX_TIMERS=y >> > CONFIG_PRINTK=y >> > CONFIG_PRINTK_NMI=y >> > CONFIG_BUG=y >> > CONFIG_ELF_CORE=y >> > CONFIG_PCSPKR_PLATFORM=y >> > CONFIG_BASE_FULL=y >> > CONFIG_FUTEX=y >> > CONFIG_FUTEX_PI=y >> > CONFIG_EPOLL=y >> > CONFIG_SIGNALFD=y >> > CONFIG_TIMERFD=y >> > CONFIG_EVENTFD=y >> > CONFIG_SHMEM=y >> > CONFIG_AIO=y >> > # CONFIG_IO_URING is not set >> > CONFIG_ADVISE_SYSCALLS=y >> > CONFIG_MEMBARRIER=y >> > CONFIG_KALLSYMS=y >> > CONFIG_KALLSYMS_ALL=y >> > CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y >> > CONFIG_KALLSYMS_BASE_RELATIVE=y >> > CONFIG_BPF_SYSCALL=y >> > CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y >> > # CONFIG_USERFAULTFD is not set >> > CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y >> > CONFIG_RSEQ=y >> > # CONFIG_DEBUG_RSEQ is not set >> > # CONFIG_EMBEDDED is not set >> > CONFIG_HAVE_PERF_EVENTS=y >> > # CONFIG_PC104 is not set >> > >> > # >> > # Kernel Performance Events And Counters >> > # >> > CONFIG_PERF_EVENTS=y >> > # CONFIG_DEBUG_PERF_USE_VMALLOC is not set >> > # end of Kernel Performance Events And Counters >> > >> > CONFIG_VM_EVENT_COUNTERS=y >> > CONFIG_COMPAT_BRK=y >> > CONFIG_SLAB=y >> > # CONFIG_SLUB is not set >> > # CONFIG_SLOB is not set >> > CONFIG_SLAB_MERGE_DEFAULT=y >> > # CONFIG_SLAB_FREELIST_RANDOM is not set >> > # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set >> > CONFIG_SYSTEM_DATA_VERIFICATION=y >> > # CONFIG_PROFILING is not set >> > CONFIG_TRACEPOINTS=y >> > # end of General setup >> > >> > CONFIG_64BIT=y >> > CONFIG_X86_64=y >> > CONFIG_X86=y >> > CONFIG_INSTRUCTION_DECODER=y >> > CONFIG_OUTPUT_FORMAT="elf64-x86-64" >> > CONFIG_LOCKDEP_SUPPORT=y >> > CONFIG_STACKTRACE_SUPPORT=y >> > CONFIG_MMU=y >> > CONFIG_ARCH_MMAP_RND_BITS_MIN=28 >> > CONFIG_ARCH_MMAP_RND_BITS_MAX=32 >> > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 >> > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 >> > CONFIG_GENERIC_ISA_DMA=y >> > CONFIG_GENERIC_BUG=y >> > CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y >> > CONFIG_ARCH_MAY_HAVE_PC_FDC=y >> > CONFIG_GENERIC_CALIBRATE_DELAY=y >> > CONFIG_ARCH_HAS_CPU_RELAX=y >> > CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y >> > CONFIG_ARCH_HAS_FILTER_PGPROT=y >> > CONFIG_HAVE_SETUP_PER_CPU_AREA=y >> > CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y >> > CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y >> > CONFIG_ARCH_HIBERNATION_POSSIBLE=y >> > CONFIG_ARCH_SUSPEND_POSSIBLE=y >> > CONFIG_ARCH_WANT_GENERAL_HUGETLB=y >> > CONFIG_ZONE_DMA32=y >> > CONFIG_AUDIT_ARCH=y >> > CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y >> > CONFIG_HAVE_INTEL_TXT=y >> > CONFIG_X86_64_SMP=y >> > CONFIG_ARCH_SUPPORTS_UPROBES=y >> > CONFIG_FIX_EARLYCON_MEM=y >> > CONFIG_PGTABLE_LEVELS=4 >> > CONFIG_CC_HAS_SANE_STACKPROTECTOR=y >> > >> > # >> > # Processor type and features >> > # >> > CONFIG_ZONE_DMA=y >> > CONFIG_SMP=y >> > CONFIG_X86_FEATURE_NAMES=y >> > CONFIG_X86_MPPARSE=y >> > # CONFIG_GOLDFISH is not set >> > # CONFIG_RETPOLINE is not set >> > CONFIG_X86_CPU_RESCTRL=y >> > # CONFIG_X86_EXTENDED_PLATFORM is not set >> > # CONFIG_X86_INTEL_LPSS is not set >> > # CONFIG_X86_AMD_PLATFORM_DEVICE is not set >> > CONFIG_IOSF_MBI=y >> > # CONFIG_IOSF_MBI_DEBUG is not set >> > CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y >> > # CONFIG_SCHED_OMIT_FRAME_POINTER is not set >> > # CONFIG_HYPERVISOR_GUEST is not set >> > # CONFIG_MK8 is not set >> > # CONFIG_MPSC is not set >> > CONFIG_MCORE2=y >> > # CONFIG_MATOM is not set >> > # CONFIG_GENERIC_CPU is not set >> > CONFIG_X86_INTERNODE_CACHE_SHIFT=6 >> > CONFIG_X86_L1_CACHE_SHIFT=6 >> > CONFIG_X86_INTEL_USERCOPY=y >> > CONFIG_X86_USE_PPRO_CHECKSUM=y >> > CONFIG_X86_P6_NOP=y >> > CONFIG_X86_TSC=y >> > CONFIG_X86_CMPXCHG64=y >> > CONFIG_X86_CMOV=y >> > CONFIG_X86_MINIMUM_CPU_FAMILY=64 >> > CONFIG_X86_DEBUGCTLMSR=y >> > CONFIG_IA32_FEAT_CTL=y >> > CONFIG_X86_VMX_FEATURE_NAMES=y >> > # CONFIG_PROCESSOR_SELECT is not set >> > CONFIG_CPU_SUP_INTEL=y >> > CONFIG_CPU_SUP_AMD=y >> > CONFIG_CPU_SUP_HYGON=y >> > CONFIG_CPU_SUP_CENTAUR=y >> > CONFIG_CPU_SUP_ZHAOXIN=y >> > CONFIG_HPET_TIMER=y >> > CONFIG_HPET_EMULATE_RTC=y >> > CONFIG_DMI=y >> > CONFIG_GART_IOMMU=y >> > # CONFIG_MAXSMP is not set >> > CONFIG_NR_CPUS_RANGE_BEGIN=2 >> > CONFIG_NR_CPUS_RANGE_END=512 >> > CONFIG_NR_CPUS_DEFAULT=64 >> > CONFIG_NR_CPUS=4 >> > CONFIG_SCHED_SMT=y >> > CONFIG_SCHED_MC=y >> > CONFIG_SCHED_MC_PRIO=y >> > CONFIG_X86_LOCAL_APIC=y >> > CONFIG_X86_IO_APIC=y >> > # CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set >> > CONFIG_X86_MCE=y >> > # CONFIG_X86_MCELOG_LEGACY is not set >> > CONFIG_X86_MCE_INTEL=y >> > # CONFIG_X86_MCE_AMD is not set >> > CONFIG_X86_MCE_THRESHOLD=y >> > # CONFIG_X86_MCE_INJECT is not set >> > CONFIG_X86_THERMAL_VECTOR=y >> > >> > # >> > # Performance monitoring >> > # >> > CONFIG_PERF_EVENTS_INTEL_UNCORE=y >> > CONFIG_PERF_EVENTS_INTEL_RAPL=y >> > CONFIG_PERF_EVENTS_INTEL_CSTATE=y >> > # CONFIG_PERF_EVENTS_AMD_POWER is not set >> > # end of Performance monitoring >> > >> > CONFIG_X86_16BIT=y >> > CONFIG_X86_ESPFIX64=y >> > CONFIG_X86_VSYSCALL_EMULATION=y >> > # CONFIG_X86_IOPL_IOPERM is not set >> > # CONFIG_I8K is not set >> > # CONFIG_MICROCODE is not set >> > CONFIG_X86_MSR=y >> > CONFIG_X86_CPUID=y >> > # CONFIG_X86_5LEVEL is not set >> > CONFIG_X86_DIRECT_GBPAGES=y >> > # CONFIG_X86_CPA_STATISTICS is not set >> > # CONFIG_AMD_MEM_ENCRYPT is not set >> > CONFIG_NUMA=y >> > # CONFIG_AMD_NUMA is not set >> > CONFIG_X86_64_ACPI_NUMA=y >> > CONFIG_NODES_SPAN_OTHER_NODES=y >> > # CONFIG_NUMA_EMU is not set >> > CONFIG_NODES_SHIFT=6 >> > CONFIG_ARCH_SPARSEMEM_ENABLE=y >> > CONFIG_ARCH_SPARSEMEM_DEFAULT=y >> > CONFIG_ARCH_SELECT_MEMORY_MODEL=y >> > CONFIG_ARCH_PROC_KCORE_TEXT=y >> > CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 >> > # CONFIG_X86_PMEM_LEGACY is not set >> > # CONFIG_X86_CHECK_BIOS_CORRUPTION is not set >> > CONFIG_X86_RESERVE_LOW=64 >> > CONFIG_MTRR=y >> > # CONFIG_MTRR_SANITIZER is not set >> > CONFIG_X86_PAT=y >> > CONFIG_ARCH_USES_PG_UNCACHED=y >> > CONFIG_ARCH_RANDOM=y >> > CONFIG_X86_SMAP=y >> > CONFIG_X86_UMIP=y >> > CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y >> > CONFIG_X86_INTEL_TSX_MODE_OFF=y >> > # CONFIG_X86_INTEL_TSX_MODE_ON is not set >> > # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set >> > CONFIG_EFI=y >> > CONFIG_EFI_STUB=y >> > # CONFIG_EFI_MIXED is not set >> > CONFIG_SECCOMP=y >> > # CONFIG_HZ_100 is not set >> > CONFIG_HZ_250=y >> > # CONFIG_HZ_300 is not set >> > # CONFIG_HZ_1000 is not set >> > CONFIG_HZ=250 >> > CONFIG_SCHED_HRTICK=y >> > CONFIG_KEXEC=y >> > CONFIG_KEXEC_FILE=y >> > CONFIG_ARCH_HAS_KEXEC_PURGATORY=y >> > # CONFIG_KEXEC_SIG is not set >> > # CONFIG_CRASH_DUMP is not set >> > CONFIG_PHYSICAL_START=0x1000000 >> > CONFIG_RELOCATABLE=y >> > # CONFIG_RANDOMIZE_BASE is not set >> > CONFIG_PHYSICAL_ALIGN=0x1000000 >> > CONFIG_HOTPLUG_CPU=y >> > # CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set >> > # CONFIG_DEBUG_HOTPLUG_CPU0 is not set >> > CONFIG_COMPAT_VDSO=y >> > # CONFIG_LEGACY_VSYSCALL_EMULATE is not set >> > CONFIG_LEGACY_VSYSCALL_XONLY=y >> > # CONFIG_LEGACY_VSYSCALL_NONE is not set >> > # CONFIG_CMDLINE_BOOL is not set >> > CONFIG_MODIFY_LDT_SYSCALL=y >> > CONFIG_HAVE_LIVEPATCH=y >> > CONFIG_LIVEPATCH=y >> > # end of Processor type and features >> > >> > CONFIG_ARCH_HAS_ADD_PAGES=y >> > CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y >> > CONFIG_USE_PERCPU_NUMA_NODE_ID=y >> > CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y >> > CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y >> > >> > # >> > # Power management and ACPI options >> > # >> > # CONFIG_SUSPEND is not set >> > # CONFIG_HIBERNATION is not set >> > CONFIG_PM=y >> > # CONFIG_PM_DEBUG is not set >> > CONFIG_PM_CLK=y >> > CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y >> > CONFIG_ENERGY_MODEL=y >> > CONFIG_ARCH_SUPPORTS_ACPI=y >> > CONFIG_ACPI=y >> > CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y >> > CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y >> > CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y >> > # CONFIG_ACPI_DEBUGGER is not set >> > CONFIG_ACPI_SPCR_TABLE=y >> > CONFIG_ACPI_LPIT=y >> > # CONFIG_ACPI_PROCFS_POWER is not set >> > CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y >> > # CONFIG_ACPI_EC_DEBUGFS is not set >> > CONFIG_ACPI_AC=y >> > # CONFIG_ACPI_BATTERY is not set >> > CONFIG_ACPI_BUTTON=y >> > CONFIG_ACPI_VIDEO=y >> > CONFIG_ACPI_FAN=y >> > CONFIG_ACPI_DOCK=y >> > CONFIG_ACPI_CPU_FREQ_PSS=y >> > CONFIG_ACPI_PROCESSOR_CSTATE=y >> > CONFIG_ACPI_PROCESSOR_IDLE=y >> > CONFIG_ACPI_CPPC_LIB=y >> > CONFIG_ACPI_PROCESSOR=y >> > # CONFIG_ACPI_IPMI is not set >> > CONFIG_ACPI_HOTPLUG_CPU=y >> > CONFIG_ACPI_PROCESSOR_AGGREGATOR=y >> > CONFIG_ACPI_THERMAL=y >> > CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y >> > CONFIG_ACPI_TABLE_UPGRADE=y >> > CONFIG_ACPI_DEBUG=y >> > # CONFIG_ACPI_PCI_SLOT is not set >> > CONFIG_ACPI_CONTAINER=y >> > CONFIG_ACPI_HOTPLUG_IOAPIC=y >> > # CONFIG_ACPI_SBS is not set >> > CONFIG_ACPI_HED=y >> > # CONFIG_ACPI_CUSTOM_METHOD is not set >> > # CONFIG_ACPI_BGRT is not set >> > # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set >> > # CONFIG_ACPI_NFIT is not set >> > CONFIG_ACPI_NUMA=y >> > # CONFIG_ACPI_HMAT is not set >> > CONFIG_HAVE_ACPI_APEI=y >> > CONFIG_HAVE_ACPI_APEI_NMI=y >> > CONFIG_ACPI_APEI=y >> > CONFIG_ACPI_APEI_GHES=y >> > # CONFIG_ACPI_APEI_PCIEAER is not set >> > CONFIG_ACPI_APEI_EINJ=y >> > # CONFIG_ACPI_APEI_ERST_DEBUG is not set >> > # CONFIG_DPTF_POWER is not set >> > # CONFIG_PMIC_OPREGION is not set >> > # CONFIG_ACPI_CONFIGFS is not set >> > CONFIG_X86_PM_TIMER=y >> > # CONFIG_SFI is not set >> > >> > # >> > # CPU Frequency scaling >> > # >> > CONFIG_CPU_FREQ=y >> > CONFIG_CPU_FREQ_GOV_ATTR_SET=y >> > CONFIG_CPU_FREQ_GOV_COMMON=y >> > CONFIG_CPU_FREQ_STAT=y >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set >> > CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set >> > CONFIG_CPU_FREQ_GOV_PERFORMANCE=y >> > CONFIG_CPU_FREQ_GOV_POWERSAVE=y >> > CONFIG_CPU_FREQ_GOV_USERSPACE=y >> > CONFIG_CPU_FREQ_GOV_ONDEMAND=y >> > CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y >> > CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y >> > >> > # >> > # CPU frequency scaling drivers >> > # >> > CONFIG_X86_INTEL_PSTATE=y >> > CONFIG_X86_PCC_CPUFREQ=y >> > CONFIG_X86_ACPI_CPUFREQ=y >> > # CONFIG_X86_ACPI_CPUFREQ_CPB is not set >> > # CONFIG_X86_POWERNOW_K8 is not set >> > # CONFIG_X86_AMD_FREQ_SENSITIVITY is not set >> > # CONFIG_X86_SPEEDSTEP_CENTRINO is not set >> > # CONFIG_X86_P4_CLOCKMOD is not set >> > >> > # >> > # shared options >> > # >> > # end of CPU Frequency scaling >> > >> > # >> > # CPU Idle >> > # >> > CONFIG_CPU_IDLE=y >> > CONFIG_CPU_IDLE_GOV_LADDER=y >> > CONFIG_CPU_IDLE_GOV_MENU=y >> > # CONFIG_CPU_IDLE_GOV_TEO is not set >> > # end of CPU Idle >> > >> > CONFIG_INTEL_IDLE=y >> > # end of Power management and ACPI options >> > >> > # >> > # Bus options (PCI etc.) >> > # >> > CONFIG_PCI_DIRECT=y >> > CONFIG_PCI_MMCONFIG=y >> > CONFIG_MMCONF_FAM10H=y >> > # CONFIG_PCI_CNB20LE_QUIRK is not set >> > # CONFIG_ISA_BUS is not set >> > CONFIG_ISA_DMA_API=y >> > CONFIG_AMD_NB=y >> > # CONFIG_X86_SYSFB is not set >> > # end of Bus options (PCI etc.) >> > >> > # >> > # Binary Emulations >> > # >> > CONFIG_IA32_EMULATION=y >> > # CONFIG_X86_X32 is not set >> > CONFIG_COMPAT_32=y >> > CONFIG_COMPAT=y >> > CONFIG_COMPAT_FOR_U64_ALIGNMENT=y >> > CONFIG_SYSVIPC_COMPAT=y >> > # end of Binary Emulations >> > >> > # >> > # Firmware Drivers >> > # >> > # CONFIG_EDD is not set >> > CONFIG_FIRMWARE_MEMMAP=y >> > CONFIG_DMIID=y >> > # CONFIG_DMI_SYSFS is not set >> > CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y >> > # CONFIG_FW_CFG_SYSFS is not set >> > # CONFIG_GOOGLE_FIRMWARE is not set >> > >> > # >> > # EFI (Extensible Firmware Interface) Support >> > # >> > # CONFIG_EFI_VARS is not set >> > CONFIG_EFI_ESRT=y >> > CONFIG_EFI_RUNTIME_MAP=y >> > # CONFIG_EFI_FAKE_MEMMAP is not set >> > CONFIG_EFI_RUNTIME_WRAPPERS=y >> > # CONFIG_EFI_CAPSULE_LOADER is not set >> > # CONFIG_EFI_TEST is not set >> > # CONFIG_APPLE_PROPERTIES is not set >> > # CONFIG_RESET_ATTACK_MITIGATION is not set >> > # CONFIG_EFI_RCI2_TABLE is not set >> > # CONFIG_EFI_DISABLE_PCI_DMA is not set >> > # end of EFI (Extensible Firmware Interface) Support >> > >> > CONFIG_UEFI_CPER=y >> > CONFIG_UEFI_CPER_X86=y >> > CONFIG_EFI_EARLYCON=y >> > >> > # >> > # Tegra firmware driver >> > # >> > # end of Tegra firmware driver >> > # end of Firmware Drivers >> > >> > CONFIG_HAVE_KVM=y >> > # CONFIG_VIRTUALIZATION is not set >> > CONFIG_AS_AVX512=y >> > CONFIG_AS_SHA1_NI=y >> > CONFIG_AS_SHA256_NI=y >> > >> > # >> > # General architecture-dependent options >> > # >> > CONFIG_CRASH_CORE=y >> > CONFIG_KEXEC_CORE=y >> > CONFIG_HOTPLUG_SMT=y >> > CONFIG_HAVE_OPROFILE=y >> > CONFIG_OPROFILE_NMI_TIMER=y >> > CONFIG_KPROBES=y >> > CONFIG_JUMP_LABEL=y >> > # CONFIG_STATIC_KEYS_SELFTEST is not set >> > CONFIG_OPTPROBES=y >> > CONFIG_KPROBES_ON_FTRACE=y >> > CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y >> > CONFIG_ARCH_USE_BUILTIN_BSWAP=y >> > CONFIG_KRETPROBES=y >> > CONFIG_HAVE_IOREMAP_PROT=y >> > CONFIG_HAVE_KPROBES=y >> > CONFIG_HAVE_KRETPROBES=y >> > CONFIG_HAVE_OPTPROBES=y >> > CONFIG_HAVE_KPROBES_ON_FTRACE=y >> > CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y >> > CONFIG_HAVE_NMI=y >> > CONFIG_HAVE_ARCH_TRACEHOOK=y >> > CONFIG_HAVE_DMA_CONTIGUOUS=y >> > CONFIG_GENERIC_SMP_IDLE_THREAD=y >> > CONFIG_ARCH_HAS_FORTIFY_SOURCE=y >> > CONFIG_ARCH_HAS_SET_MEMORY=y >> > CONFIG_ARCH_HAS_SET_DIRECT_MAP=y >> > CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y >> > CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y >> > CONFIG_HAVE_ASM_MODVERSIONS=y >> > CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y >> > CONFIG_HAVE_RSEQ=y >> > CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y >> > CONFIG_HAVE_CLK=y >> > CONFIG_HAVE_HW_BREAKPOINT=y >> > CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y >> > CONFIG_HAVE_USER_RETURN_NOTIFIER=y >> > CONFIG_HAVE_PERF_EVENTS_NMI=y >> > CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y >> > CONFIG_HAVE_PERF_REGS=y >> > CONFIG_HAVE_PERF_USER_STACK_DUMP=y >> > CONFIG_HAVE_ARCH_JUMP_LABEL=y >> > CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y >> > CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y >> > CONFIG_HAVE_CMPXCHG_LOCAL=y >> > CONFIG_HAVE_CMPXCHG_DOUBLE=y >> > CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y >> > CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y >> > CONFIG_HAVE_ARCH_SECCOMP_FILTER=y >> > CONFIG_SECCOMP_FILTER=y >> > CONFIG_HAVE_ARCH_STACKLEAK=y >> > CONFIG_HAVE_STACKPROTECTOR=y >> > CONFIG_CC_HAS_STACKPROTECTOR_NONE=y >> > CONFIG_STACKPROTECTOR=y >> > CONFIG_STACKPROTECTOR_STRONG=y >> > CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y >> > CONFIG_HAVE_CONTEXT_TRACKING=y >> > CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y >> > CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y >> > CONFIG_HAVE_MOVE_PMD=y >> > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y >> > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y >> > CONFIG_HAVE_ARCH_HUGE_VMAP=y >> > CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y >> > CONFIG_HAVE_ARCH_SOFT_DIRTY=y >> > CONFIG_HAVE_MOD_ARCH_SPECIFIC=y >> > CONFIG_MODULES_USE_ELF_RELA=y >> > CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y >> > CONFIG_ARCH_HAS_ELF_RANDOMIZE=y >> > CONFIG_HAVE_ARCH_MMAP_RND_BITS=y >> > CONFIG_HAVE_EXIT_THREAD=y >> > CONFIG_ARCH_MMAP_RND_BITS=28 >> > CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y >> > CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 >> > CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y >> > CONFIG_HAVE_COPY_THREAD_TLS=y >> > CONFIG_HAVE_STACK_VALIDATION=y >> > CONFIG_HAVE_RELIABLE_STACKTRACE=y >> > CONFIG_OLD_SIGSUSPEND3=y >> > CONFIG_COMPAT_OLD_SIGACTION=y >> > CONFIG_COMPAT_32BIT_TIME=y >> > CONFIG_HAVE_ARCH_VMAP_STACK=y >> > # CONFIG_VMAP_STACK is not set >> > CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y >> > CONFIG_STRICT_KERNEL_RWX=y >> > CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y >> > CONFIG_STRICT_MODULE_RWX=y >> > CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y >> > CONFIG_ARCH_USE_MEMREMAP_PROT=y >> > # CONFIG_LOCK_EVENT_COUNTS is not set >> > CONFIG_ARCH_HAS_MEM_ENCRYPT=y >> > >> > # >> > # GCOV-based kernel profiling >> > # >> > # CONFIG_GCOV_KERNEL is not set >> > CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y >> > # end of GCOV-based kernel profiling >> > >> > CONFIG_HAVE_GCC_PLUGINS=y >> > CONFIG_GCC_PLUGINS=y >> > # CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set >> > # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set >> > # CONFIG_GCC_PLUGIN_RANDSTRUCT is not set >> > # end of General architecture-dependent options >> > >> > CONFIG_RT_MUTEXES=y >> > CONFIG_BASE_SMALL=0 >> > CONFIG_MODULE_SIG_FORMAT=y >> > CONFIG_MODULES=y >> > # CONFIG_MODULE_FORCE_LOAD is not set >> > CONFIG_MODULE_UNLOAD=y >> > # CONFIG_MODULE_FORCE_UNLOAD is not set >> > # CONFIG_MODVERSIONS is not set >> > # CONFIG_MODULE_SRCVERSION_ALL is not set >> > CONFIG_MODULE_SIG=y >> > # CONFIG_MODULE_SIG_FORCE is not set >> > CONFIG_MODULE_SIG_ALL=y >> > # CONFIG_MODULE_SIG_SHA1 is not set >> > # CONFIG_MODULE_SIG_SHA224 is not set >> > CONFIG_MODULE_SIG_SHA256=y >> > # CONFIG_MODULE_SIG_SHA384 is not set >> > # CONFIG_MODULE_SIG_SHA512 is not set >> > CONFIG_MODULE_SIG_HASH="sha256" >> > # CONFIG_MODULE_COMPRESS is not set >> > # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set >> > CONFIG_UNUSED_SYMBOLS=y >> > CONFIG_MODULES_TREE_LOOKUP=y >> > CONFIG_BLOCK=y >> > CONFIG_BLK_SCSI_REQUEST=y >> > CONFIG_BLK_DEV_BSG=y >> > # CONFIG_BLK_DEV_BSGLIB is not set >> > # CONFIG_BLK_DEV_INTEGRITY is not set >> > # CONFIG_BLK_DEV_ZONED is not set >> > # CONFIG_BLK_DEV_THROTTLING is not set >> > # CONFIG_BLK_CMDLINE_PARSER is not set >> > # CONFIG_BLK_WBT is not set >> > # CONFIG_BLK_CGROUP_IOLATENCY is not set >> > # CONFIG_BLK_CGROUP_IOCOST is not set >> > CONFIG_BLK_DEBUG_FS=y >> > # CONFIG_BLK_SED_OPAL is not set >> > >> > # >> > # Partition Types >> > # >> > # CONFIG_PARTITION_ADVANCED is not set >> > CONFIG_MSDOS_PARTITION=y >> > CONFIG_EFI_PARTITION=y >> > # end of Partition Types >> > >> > CONFIG_BLOCK_COMPAT=y >> > CONFIG_BLK_MQ_PCI=y >> > CONFIG_BLK_PM=y >> > >> > # >> > # IO Schedulers >> > # >> > CONFIG_MQ_IOSCHED_DEADLINE=y >> > CONFIG_MQ_IOSCHED_KYBER=y >> > # CONFIG_IOSCHED_BFQ is not set >> > # end of IO Schedulers >> > >> > CONFIG_ASN1=y >> > CONFIG_UNINLINE_SPIN_UNLOCK=y >> > CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y >> > CONFIG_MUTEX_SPIN_ON_OWNER=y >> > CONFIG_RWSEM_SPIN_ON_OWNER=y >> > CONFIG_LOCK_SPIN_ON_OWNER=y >> > CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y >> > CONFIG_QUEUED_SPINLOCKS=y >> > CONFIG_ARCH_USE_QUEUED_RWLOCKS=y >> > CONFIG_QUEUED_RWLOCKS=y >> > CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y >> > CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y >> > CONFIG_FREEZER=y >> > >> > # >> > # Executable file formats >> > # >> > CONFIG_BINFMT_ELF=y >> > CONFIG_COMPAT_BINFMT_ELF=y >> > CONFIG_ELFCORE=y >> > # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set >> > CONFIG_BINFMT_SCRIPT=y >> > CONFIG_BINFMT_MISC=y >> > CONFIG_COREDUMP=y >> > # end of Executable file formats >> > >> > # >> > # Memory Management options >> > # >> > CONFIG_SELECT_MEMORY_MODEL=y >> > CONFIG_SPARSEMEM_MANUAL=y >> > CONFIG_SPARSEMEM=y >> > CONFIG_NEED_MULTIPLE_NODES=y >> > CONFIG_HAVE_MEMORY_PRESENT=y >> > CONFIG_SPARSEMEM_EXTREME=y >> > CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y >> > CONFIG_SPARSEMEM_VMEMMAP=y >> > CONFIG_HAVE_MEMBLOCK_NODE_MAP=y >> > CONFIG_HAVE_FAST_GUP=y >> > # CONFIG_MEMORY_HOTPLUG is not set >> > CONFIG_SPLIT_PTLOCK_CPUS=4 >> > # CONFIG_COMPACTION is not set >> > # CONFIG_PAGE_REPORTING is not set >> > CONFIG_MIGRATION=y >> > CONFIG_PHYS_ADDR_T_64BIT=y >> > CONFIG_BOUNCE=y >> > CONFIG_VIRT_TO_BUS=y >> > CONFIG_MMU_NOTIFIER=y >> > # CONFIG_KSM is not set >> > CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 >> > CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y >> > # CONFIG_MEMORY_FAILURE is not set >> > # CONFIG_TRANSPARENT_HUGEPAGE is not set >> > CONFIG_ARCH_WANTS_THP_SWAP=y >> > # CONFIG_CLEANCACHE is not set >> > # CONFIG_FRONTSWAP is not set >> > # CONFIG_CMA is not set >> > CONFIG_ZPOOL=m >> > CONFIG_ZBUD=m >> > CONFIG_Z3FOLD=m >> > CONFIG_ZSMALLOC=m >> > # CONFIG_PGTABLE_MAPPING is not set >> > # CONFIG_ZSMALLOC_STAT is not set >> > CONFIG_GENERIC_EARLY_IOREMAP=y >> > # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set >> > # CONFIG_IDLE_PAGE_TRACKING is not set >> > CONFIG_ARCH_HAS_PTE_DEVMAP=y >> > CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y >> > CONFIG_ARCH_HAS_PKEYS=y >> > # CONFIG_PERCPU_STATS is not set >> > # CONFIG_GUP_BENCHMARK is not set >> > CONFIG_ARCH_HAS_PTE_SPECIAL=y >> > # end of Memory Management options >> > >> > CONFIG_NET=y >> > CONFIG_SKB_EXTENSIONS=y >> > >> > # >> > # Networking options >> > # >> > CONFIG_PACKET=y >> > # CONFIG_PACKET_DIAG is not set >> > CONFIG_UNIX=y >> > CONFIG_UNIX_SCM=y >> > # CONFIG_UNIX_DIAG is not set >> > # CONFIG_TLS is not set >> > CONFIG_XFRM=y >> > CONFIG_XFRM_ALGO=y >> > # CONFIG_XFRM_USER is not set >> > # CONFIG_XFRM_INTERFACE is not set >> > # CONFIG_XFRM_SUB_POLICY is not set >> > # CONFIG_XFRM_MIGRATE is not set >> > # CONFIG_XFRM_STATISTICS is not set >> > CONFIG_XFRM_IPCOMP=y >> > # CONFIG_NET_KEY is not set >> > # CONFIG_XDP_SOCKETS is not set >> > CONFIG_INET=y >> > CONFIG_IP_MULTICAST=y >> > CONFIG_IP_ADVANCED_ROUTER=y >> > CONFIG_IP_FIB_TRIE_STATS=y >> > CONFIG_IP_MULTIPLE_TABLES=y >> > CONFIG_IP_ROUTE_MULTIPATH=y >> > CONFIG_IP_ROUTE_VERBOSE=y >> > # CONFIG_IP_PNP is not set >> > # CONFIG_NET_IPIP is not set >> > # CONFIG_NET_IPGRE_DEMUX is not set >> > # CONFIG_IP_MROUTE is not set >> > # CONFIG_SYN_COOKIES is not set >> > # CONFIG_NET_IPVTI is not set >> > # CONFIG_NET_FOU is not set >> > # CONFIG_INET_AH is not set >> > # CONFIG_INET_ESP is not set >> > # CONFIG_INET_IPCOMP is not set >> > CONFIG_INET_DIAG=y >> > CONFIG_INET_TCP_DIAG=y >> > # CONFIG_INET_UDP_DIAG is not set >> > # CONFIG_INET_RAW_DIAG is not set >> > # CONFIG_INET_DIAG_DESTROY is not set >> > # CONFIG_TCP_CONG_ADVANCED is not set >> > CONFIG_TCP_CONG_CUBIC=y >> > CONFIG_DEFAULT_TCP_CONG="cubic" >> > # CONFIG_TCP_MD5SIG is not set >> > CONFIG_IPV6=y >> > CONFIG_IPV6_ROUTER_PREF=y >> > CONFIG_IPV6_ROUTE_INFO=y >> > CONFIG_IPV6_OPTIMISTIC_DAD=y >> > CONFIG_INET6_AH=y >> > CONFIG_INET6_ESP=y >> > # CONFIG_INET6_ESP_OFFLOAD is not set >> > CONFIG_INET6_IPCOMP=y >> > CONFIG_IPV6_MIP6=y >> > CONFIG_INET6_XFRM_TUNNEL=y >> > CONFIG_INET6_TUNNEL=y >> > # CONFIG_IPV6_VTI is not set >> > # CONFIG_IPV6_SIT is not set >> > # CONFIG_IPV6_TUNNEL is not set >> > CONFIG_IPV6_MULTIPLE_TABLES=y >> > CONFIG_IPV6_SUBTREES=y >> > # CONFIG_IPV6_MROUTE is not set >> > # CONFIG_IPV6_SEG6_LWTUNNEL is not set >> > # CONFIG_IPV6_SEG6_HMAC is not set >> > # CONFIG_IPV6_RPL_LWTUNNEL is not set >> > CONFIG_NETLABEL=y >> > # CONFIG_MPTCP is not set >> > CONFIG_NETWORK_SECMARK=y >> > CONFIG_NET_PTP_CLASSIFY=y >> > # CONFIG_NETWORK_PHY_TIMESTAMPING is not set >> > # CONFIG_NETFILTER is not set >> > # CONFIG_BPFILTER is not set >> > # CONFIG_IP_DCCP is not set >> > CONFIG_IP_SCTP=y >> > # CONFIG_SCTP_DBG_OBJCNT is not set >> > CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y >> > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set >> > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set >> > CONFIG_SCTP_COOKIE_HMAC_MD5=y >> > # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set >> > CONFIG_INET_SCTP_DIAG=y >> > CONFIG_RDS=y >> > CONFIG_RDS_TCP=m >> > # CONFIG_RDS_DEBUG is not set >> > # CONFIG_TIPC is not set >> > # CONFIG_ATM is not set >> > # CONFIG_L2TP is not set >> > CONFIG_STP=y >> > CONFIG_BRIDGE=y >> > CONFIG_BRIDGE_IGMP_SNOOPING=y >> > CONFIG_HAVE_NET_DSA=y >> > # CONFIG_NET_DSA is not set >> > # CONFIG_VLAN_8021Q is not set >> > # CONFIG_DECNET is not set >> > CONFIG_LLC=y >> > # CONFIG_LLC2 is not set >> > # CONFIG_ATALK is not set >> > # CONFIG_X25 is not set >> > # CONFIG_LAPB is not set >> > # CONFIG_PHONET is not set >> > # CONFIG_6LOWPAN is not set >> > # CONFIG_IEEE802154 is not set >> > # CONFIG_NET_SCHED is not set >> > # CONFIG_DCB is not set >> > CONFIG_DNS_RESOLVER=y >> > # CONFIG_BATMAN_ADV is not set >> > # CONFIG_OPENVSWITCH is not set >> > # CONFIG_VSOCKETS is not set >> > CONFIG_NETLINK_DIAG=y >> > # CONFIG_MPLS is not set >> > # CONFIG_NET_NSH is not set >> > # CONFIG_HSR is not set >> > # CONFIG_NET_SWITCHDEV is not set >> > # CONFIG_NET_L3_MASTER_DEV is not set >> > # CONFIG_NET_NCSI is not set >> > CONFIG_RPS=y >> > CONFIG_RFS_ACCEL=y >> > CONFIG_XPS=y >> > CONFIG_CGROUP_NET_PRIO=y >> > CONFIG_CGROUP_NET_CLASSID=y >> > CONFIG_NET_RX_BUSY_POLL=y >> > CONFIG_BQL=y >> > # CONFIG_BPF_JIT is not set >> > CONFIG_NET_FLOW_LIMIT=y >> > >> > # >> > # Network testing >> > # >> > # CONFIG_NET_PKTGEN is not set >> > # CONFIG_NET_DROP_MONITOR is not set >> > # end of Network testing >> > # end of Networking options >> > >> > # CONFIG_HAMRADIO is not set >> > # CONFIG_CAN is not set >> > # CONFIG_BT is not set >> > CONFIG_AF_RXRPC=y >> > CONFIG_AF_RXRPC_IPV6=y >> > # CONFIG_AF_RXRPC_INJECT_LOSS is not set >> > CONFIG_AF_RXRPC_DEBUG=y >> > CONFIG_RXKAD=y >> > # CONFIG_AF_KCM is not set >> > CONFIG_FIB_RULES=y >> > # CONFIG_WIRELESS is not set >> > # CONFIG_WIMAX is not set >> > # CONFIG_RFKILL is not set >> > # CONFIG_NET_9P is not set >> > # CONFIG_CAIF is not set >> > CONFIG_CEPH_LIB=m >> > # CONFIG_CEPH_LIB_PRETTYDEBUG is not set >> > CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y >> > # CONFIG_NFC is not set >> > # CONFIG_PSAMPLE is not set >> > # CONFIG_NET_IFE is not set >> > # CONFIG_LWTUNNEL is not set >> > CONFIG_GRO_CELLS=y >> > # CONFIG_FAILOVER is not set >> > CONFIG_ETHTOOL_NETLINK=y >> > CONFIG_HAVE_EBPF_JIT=y >> > >> > # >> > # Device Drivers >> > # >> > CONFIG_HAVE_EISA=y >> > # CONFIG_EISA is not set >> > CONFIG_HAVE_PCI=y >> > CONFIG_PCI=y >> > CONFIG_PCI_DOMAINS=y >> > CONFIG_PCIEPORTBUS=y >> > CONFIG_PCIEAER=y >> > # CONFIG_PCIEAER_INJECT is not set >> > # CONFIG_PCIE_ECRC is not set >> > CONFIG_PCIEASPM=y >> > CONFIG_PCIEASPM_DEFAULT=y >> > # CONFIG_PCIEASPM_POWERSAVE is not set >> > # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set >> > # CONFIG_PCIEASPM_PERFORMANCE is not set >> > CONFIG_PCIE_PME=y >> > # CONFIG_PCIE_DPC is not set >> > # CONFIG_PCIE_PTM is not set >> > # CONFIG_PCIE_BW is not set >> > CONFIG_PCI_MSI=y >> > CONFIG_PCI_MSI_IRQ_DOMAIN=y >> > CONFIG_PCI_QUIRKS=y >> > # CONFIG_PCI_DEBUG is not set >> > # CONFIG_PCI_STUB is not set >> > CONFIG_PCI_ATS=y >> > CONFIG_PCI_LOCKLESS_CONFIG=y >> > # CONFIG_PCI_IOV is not set >> > CONFIG_PCI_PRI=y >> > CONFIG_PCI_PASID=y >> > CONFIG_PCI_LABEL=y >> > # CONFIG_HOTPLUG_PCI is not set >> > >> > # >> > # PCI controller drivers >> > # >> > # CONFIG_VMD is not set >> > >> > # >> > # DesignWare PCI Core Support >> > # >> > # CONFIG_PCIE_DW_PLAT_HOST is not set >> > # CONFIG_PCI_MESON is not set >> > # end of DesignWare PCI Core Support >> > >> > # >> > # Mobiveil PCIe Core Support >> > # >> > # end of Mobiveil PCIe Core Support >> > >> > # >> > # Cadence PCIe controllers support >> > # >> > # end of Cadence PCIe controllers support >> > # end of PCI controller drivers >> > >> > # >> > # PCI Endpoint >> > # >> > # CONFIG_PCI_ENDPOINT is not set >> > # end of PCI Endpoint >> > >> > # >> > # PCI switch controller drivers >> > # >> > # CONFIG_PCI_SW_SWITCHTEC is not set >> > # end of PCI switch controller drivers >> > >> > # CONFIG_PCCARD is not set >> > # CONFIG_RAPIDIO is not set >> > >> > # >> > # Generic Driver Options >> > # >> > CONFIG_UEVENT_HELPER=y >> > CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" >> > CONFIG_DEVTMPFS=y >> > CONFIG_DEVTMPFS_MOUNT=y >> > CONFIG_STANDALONE=y >> > CONFIG_PREVENT_FIRMWARE_BUILD=y >> > >> > # >> > # Firmware loader >> > # >> > CONFIG_FW_LOADER=y >> > CONFIG_FW_LOADER_PAGED_BUF=y >> > CONFIG_EXTRA_FIRMWARE="" >> > # CONFIG_FW_LOADER_USER_HELPER is not set >> > CONFIG_FW_LOADER_COMPRESS=y >> > # end of Firmware loader >> > >> > CONFIG_ALLOW_DEV_COREDUMP=y >> > # CONFIG_DEBUG_DRIVER is not set >> > # CONFIG_DEBUG_DEVRES is not set >> > # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set >> > # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set >> > CONFIG_GENERIC_CPU_AUTOPROBE=y >> > CONFIG_GENERIC_CPU_VULNERABILITIES=y >> > CONFIG_DMA_SHARED_BUFFER=y >> > # CONFIG_DMA_FENCE_TRACE is not set >> > # end of Generic Driver Options >> > >> > # >> > # Bus devices >> > # >> > # CONFIG_MHI_BUS is not set >> > # end of Bus devices >> > >> > # CONFIG_CONNECTOR is not set >> > # CONFIG_GNSS is not set >> > # CONFIG_MTD is not set >> > # CONFIG_OF is not set >> > CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y >> > # CONFIG_PARPORT is not set >> > CONFIG_PNP=y >> > # CONFIG_PNP_DEBUG_MESSAGES is not set >> > >> > # >> > # Protocols >> > # >> > CONFIG_PNPACPI=y >> > CONFIG_BLK_DEV=y >> > # CONFIG_BLK_DEV_NULL_BLK is not set >> > # CONFIG_BLK_DEV_FD is not set >> > # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set >> > # CONFIG_ZRAM is not set >> > # CONFIG_BLK_DEV_UMEM is not set >> > CONFIG_BLK_DEV_LOOP=y >> > CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 >> > # CONFIG_BLK_DEV_CRYPTOLOOP is not set >> > # CONFIG_BLK_DEV_DRBD is not set >> > # CONFIG_BLK_DEV_NBD is not set >> > # CONFIG_BLK_DEV_SKD is not set >> > # CONFIG_BLK_DEV_SX8 is not set >> > # CONFIG_BLK_DEV_RAM is not set >> > # CONFIG_CDROM_PKTCDVD is not set >> > # CONFIG_ATA_OVER_ETH is not set >> > CONFIG_BLK_DEV_RBD=m >> > # CONFIG_BLK_DEV_RSXX is not set >> > >> > # >> > # NVME Support >> > # >> > # CONFIG_BLK_DEV_NVME is not set >> > # CONFIG_NVME_FC is not set >> > # CONFIG_NVME_TARGET is not set >> > # end of NVME Support >> > >> > # >> > # Misc devices >> > # >> > # CONFIG_AD525X_DPOT is not set >> > # CONFIG_DUMMY_IRQ is not set >> > # CONFIG_IBM_ASM is not set >> > # CONFIG_PHANTOM is not set >> > # CONFIG_TIFM_CORE is not set >> > # CONFIG_ICS932S401 is not set >> > CONFIG_ENCLOSURE_SERVICES=y >> > # CONFIG_HP_ILO is not set >> > # CONFIG_APDS9802ALS is not set >> > # CONFIG_ISL29003 is not set >> > # CONFIG_ISL29020 is not set >> > # CONFIG_SENSORS_TSL2550 is not set >> > # CONFIG_SENSORS_BH1770 is not set >> > # CONFIG_SENSORS_APDS990X is not set >> > # CONFIG_HMC6352 is not set >> > # CONFIG_DS1682 is not set >> > # CONFIG_SRAM is not set >> > # CONFIG_PCI_ENDPOINT_TEST is not set >> > # CONFIG_XILINX_SDFEC is not set >> > # CONFIG_PVPANIC is not set >> > CONFIG_C2PORT=m >> > # CONFIG_C2PORT_DURAMAR_2150 is not set >> > >> > # >> > # EEPROM support >> > # >> > # CONFIG_EEPROM_AT24 is not set >> > # CONFIG_EEPROM_LEGACY is not set >> > # CONFIG_EEPROM_MAX6875 is not set >> > # CONFIG_EEPROM_93CX6 is not set >> > # CONFIG_EEPROM_IDT_89HPESX is not set >> > # CONFIG_EEPROM_EE1004 is not set >> > # end of EEPROM support >> > >> > # CONFIG_CB710_CORE is not set >> > >> > # >> > # Texas Instruments shared transport line discipline >> > # >> > # end of Texas Instruments shared transport line discipline >> > >> > # CONFIG_SENSORS_LIS3_I2C is not set >> > # CONFIG_ALTERA_STAPL is not set >> > CONFIG_INTEL_MEI=y >> > CONFIG_INTEL_MEI_ME=y >> > # CONFIG_INTEL_MEI_TXE is not set >> > # CONFIG_INTEL_MEI_HDCP is not set >> > # CONFIG_VMWARE_VMCI is not set >> > >> > # >> > # Intel MIC & related support >> > # >> > # CONFIG_INTEL_MIC_BUS is not set >> > # CONFIG_SCIF_BUS is not set >> > # CONFIG_VOP_BUS is not set >> > # end of Intel MIC & related support >> > >> > # CONFIG_GENWQE is not set >> > # CONFIG_ECHO is not set >> > # CONFIG_MISC_ALCOR_PCI is not set >> > # CONFIG_MISC_RTSX_PCI is not set >> > # CONFIG_MISC_RTSX_USB is not set >> > # CONFIG_HABANA_AI is not set >> > # CONFIG_UACCE is not set >> > # end of Misc devices >> > >> > CONFIG_HAVE_IDE=y >> > # CONFIG_IDE is not set >> > >> > # >> > # SCSI device support >> > # >> > CONFIG_SCSI_MOD=y >> > # CONFIG_RAID_ATTRS is not set >> > CONFIG_SCSI=y >> > CONFIG_SCSI_DMA=y >> > CONFIG_SCSI_PROC_FS=y >> > >> > # >> > # SCSI support type (disk, tape, CD-ROM) >> > # >> > CONFIG_BLK_DEV_SD=y >> > # CONFIG_CHR_DEV_ST is not set >> > # CONFIG_BLK_DEV_SR is not set >> > CONFIG_CHR_DEV_SG=y >> > # CONFIG_CHR_DEV_SCH is not set >> > # CONFIG_SCSI_ENCLOSURE is not set >> > CONFIG_SCSI_CONSTANTS=y >> > # CONFIG_SCSI_LOGGING is not set >> > # CONFIG_SCSI_SCAN_ASYNC is not set >> > >> > # >> > # SCSI Transports >> > # >> > CONFIG_SCSI_SPI_ATTRS=y >> > # CONFIG_SCSI_FC_ATTRS is not set >> > # CONFIG_SCSI_ISCSI_ATTRS is not set >> > # CONFIG_SCSI_SAS_ATTRS is not set >> > # CONFIG_SCSI_SAS_LIBSAS is not set >> > # CONFIG_SCSI_SRP_ATTRS is not set >> > # end of SCSI Transports >> > >> > # CONFIG_SCSI_LOWLEVEL is not set >> > # CONFIG_SCSI_DH is not set >> > # end of SCSI device support >> > >> > CONFIG_ATA=y >> > CONFIG_SATA_HOST=y >> > CONFIG_PATA_TIMINGS=y >> > CONFIG_ATA_VERBOSE_ERROR=y >> > CONFIG_ATA_FORCE=y >> > CONFIG_ATA_ACPI=y >> > # CONFIG_SATA_ZPODD is not set >> > # CONFIG_SATA_PMP is not set >> > >> > # >> > # Controllers with non-SFF native interface >> > # >> > CONFIG_SATA_AHCI=y >> > CONFIG_SATA_MOBILE_LPM_POLICY=0 >> > CONFIG_SATA_AHCI_PLATFORM=y >> > # CONFIG_SATA_INIC162X is not set >> > # CONFIG_SATA_ACARD_AHCI is not set >> > # CONFIG_SATA_SIL24 is not set >> > # CONFIG_ATA_SFF is not set >> > CONFIG_MD=y >> > # CONFIG_BLK_DEV_MD is not set >> > # CONFIG_BCACHE is not set >> > CONFIG_BLK_DEV_DM_BUILTIN=y >> > CONFIG_BLK_DEV_DM=y >> > # CONFIG_DM_DEBUG is not set >> > # CONFIG_DM_UNSTRIPED is not set >> > # CONFIG_DM_CRYPT is not set >> > # CONFIG_DM_SNAPSHOT is not set >> > # CONFIG_DM_THIN_PROVISIONING is not set >> > # CONFIG_DM_CACHE is not set >> > # CONFIG_DM_WRITECACHE is not set >> > # CONFIG_DM_ERA is not set >> > # CONFIG_DM_CLONE is not set >> > # CONFIG_DM_MIRROR is not set >> > # CONFIG_DM_RAID is not set >> > # CONFIG_DM_ZERO is not set >> > # CONFIG_DM_MULTIPATH is not set >> > # CONFIG_DM_DELAY is not set >> > # CONFIG_DM_DUST is not set >> > # CONFIG_DM_INIT is not set >> > CONFIG_DM_UEVENT=y >> > # CONFIG_DM_FLAKEY is not set >> > # CONFIG_DM_VERITY is not set >> > # CONFIG_DM_SWITCH is not set >> > # CONFIG_DM_LOG_WRITES is not set >> > # CONFIG_DM_INTEGRITY is not set >> > # CONFIG_TARGET_CORE is not set >> > # CONFIG_FUSION is not set >> > >> > # >> > # IEEE 1394 (FireWire) support >> > # >> > # CONFIG_FIREWIRE is not set >> > # CONFIG_FIREWIRE_NOSY is not set >> > # end of IEEE 1394 (FireWire) support >> > >> > # CONFIG_MACINTOSH_DRIVERS is not set >> > CONFIG_NETDEVICES=y >> > CONFIG_NET_CORE=y >> > # CONFIG_BONDING is not set >> > # CONFIG_DUMMY is not set >> > # CONFIG_WIREGUARD is not set >> > # CONFIG_EQUALIZER is not set >> > # CONFIG_NET_FC is not set >> > # CONFIG_NET_TEAM is not set >> > # CONFIG_MACVLAN is not set >> > # CONFIG_IPVLAN is not set >> > # CONFIG_VXLAN is not set >> > # CONFIG_GENEVE is not set >> > # CONFIG_BAREUDP is not set >> > # CONFIG_GTP is not set >> > # CONFIG_MACSEC is not set >> > # CONFIG_NETCONSOLE is not set >> > CONFIG_TUN=y >> > # CONFIG_TUN_VNET_CROSS_LE is not set >> > CONFIG_VETH=y >> > # CONFIG_NLMON is not set >> > # CONFIG_ARCNET is not set >> > >> > # >> > # Distributed Switch Architecture drivers >> > # >> > # end of Distributed Switch Architecture drivers >> > >> > CONFIG_ETHERNET=y >> > CONFIG_MDIO=y >> > # CONFIG_NET_VENDOR_3COM is not set >> > # CONFIG_NET_VENDOR_ADAPTEC is not set >> > # CONFIG_NET_VENDOR_AGERE is not set >> > # CONFIG_NET_VENDOR_ALACRITECH is not set >> > # CONFIG_NET_VENDOR_ALTEON is not set >> > # CONFIG_ALTERA_TSE is not set >> > # CONFIG_NET_VENDOR_AMAZON is not set >> > # CONFIG_NET_VENDOR_AMD is not set >> > # CONFIG_NET_VENDOR_AQUANTIA is not set >> > # CONFIG_NET_VENDOR_ARC is not set >> > # CONFIG_NET_VENDOR_ATHEROS is not set >> > # CONFIG_NET_VENDOR_AURORA is not set >> > # CONFIG_NET_VENDOR_BROADCOM is not set >> > # CONFIG_NET_VENDOR_BROCADE is not set >> > # CONFIG_NET_VENDOR_CADENCE is not set >> > # CONFIG_NET_VENDOR_CAVIUM is not set >> > # CONFIG_NET_VENDOR_CHELSIO is not set >> > # CONFIG_NET_VENDOR_CISCO is not set >> > # CONFIG_NET_VENDOR_CORTINA is not set >> > # CONFIG_CX_ECAT is not set >> > # CONFIG_DNET is not set >> > # CONFIG_NET_VENDOR_DEC is not set >> > # CONFIG_NET_VENDOR_DLINK is not set >> > # CONFIG_NET_VENDOR_EMULEX is not set >> > # CONFIG_NET_VENDOR_EZCHIP is not set >> > # CONFIG_NET_VENDOR_GOOGLE is not set >> > # CONFIG_NET_VENDOR_HUAWEI is not set >> > CONFIG_NET_VENDOR_I825XX=y >> > CONFIG_NET_VENDOR_INTEL=y >> > # CONFIG_E100 is not set >> > # CONFIG_E1000 is not set >> > # CONFIG_E1000E is not set >> > # CONFIG_IGB is not set >> > # CONFIG_IGBVF is not set >> > # CONFIG_IXGB is not set >> > CONFIG_IXGBE=y >> > CONFIG_IXGBE_HWMON=y >> > # CONFIG_IXGBEVF is not set >> > # CONFIG_I40E is not set >> > # CONFIG_I40EVF is not set >> > # CONFIG_ICE is not set >> > # CONFIG_FM10K is not set >> > # CONFIG_IGC is not set >> > # CONFIG_JME is not set >> > # CONFIG_NET_VENDOR_MARVELL is not set >> > # CONFIG_NET_VENDOR_MELLANOX is not set >> > # CONFIG_NET_VENDOR_MICREL is not set >> > # CONFIG_NET_VENDOR_MICROCHIP is not set >> > # CONFIG_NET_VENDOR_MICROSEMI is not set >> > # CONFIG_NET_VENDOR_MYRI is not set >> > # CONFIG_FEALNX is not set >> > # CONFIG_NET_VENDOR_NATSEMI is not set >> > # CONFIG_NET_VENDOR_NETERION is not set >> > # CONFIG_NET_VENDOR_NETRONOME is not set >> > # CONFIG_NET_VENDOR_NI is not set >> > # CONFIG_NET_VENDOR_NVIDIA is not set >> > # CONFIG_NET_VENDOR_OKI is not set >> > # CONFIG_ETHOC is not set >> > # CONFIG_NET_VENDOR_PACKET_ENGINES is not set >> > # CONFIG_NET_VENDOR_PENSANDO is not set >> > # CONFIG_NET_VENDOR_QLOGIC is not set >> > # CONFIG_NET_VENDOR_QUALCOMM is not set >> > # CONFIG_NET_VENDOR_RDC is not set >> > CONFIG_NET_VENDOR_REALTEK=y >> > # CONFIG_8139CP is not set >> > # CONFIG_8139TOO is not set >> > CONFIG_R8169=y >> > # CONFIG_NET_VENDOR_RENESAS is not set >> > # CONFIG_NET_VENDOR_ROCKER is not set >> > # CONFIG_NET_VENDOR_SAMSUNG is not set >> > # CONFIG_NET_VENDOR_SEEQ is not set >> > # CONFIG_NET_VENDOR_SOLARFLARE is not set >> > # CONFIG_NET_VENDOR_SILAN is not set >> > # CONFIG_NET_VENDOR_SIS is not set >> > # CONFIG_NET_VENDOR_SMSC is not set >> > # CONFIG_NET_VENDOR_SOCIONEXT is not set >> > # CONFIG_NET_VENDOR_STMICRO is not set >> > # CONFIG_NET_VENDOR_SUN is not set >> > # CONFIG_NET_VENDOR_SYNOPSYS is not set >> > # CONFIG_NET_VENDOR_TEHUTI is not set >> > # CONFIG_NET_VENDOR_TI is not set >> > # CONFIG_NET_VENDOR_VIA is not set >> > # CONFIG_NET_VENDOR_WIZNET is not set >> > # CONFIG_NET_VENDOR_XILINX is not set >> > # CONFIG_FDDI is not set >> > # CONFIG_HIPPI is not set >> > # CONFIG_NET_SB1000 is not set >> > CONFIG_MDIO_DEVICE=y >> > CONFIG_MDIO_BUS=y >> > # CONFIG_MDIO_BCM_UNIMAC is not set >> > # CONFIG_MDIO_BITBANG is not set >> > # CONFIG_MDIO_MSCC_MIIM is not set >> > # CONFIG_MDIO_MVUSB is not set >> > # CONFIG_MDIO_THUNDER is not set >> > # CONFIG_MDIO_XPCS is not set >> > CONFIG_PHYLIB=y >> > >> > # >> > # MII PHY device drivers >> > # >> > # CONFIG_ADIN_PHY is not set >> > # CONFIG_AMD_PHY is not set >> > # CONFIG_AQUANTIA_PHY is not set >> > # CONFIG_AX88796B_PHY is not set >> > # CONFIG_BCM7XXX_PHY is not set >> > # CONFIG_BCM87XX_PHY is not set >> > # CONFIG_BROADCOM_PHY is not set >> > # CONFIG_BCM84881_PHY is not set >> > # CONFIG_CICADA_PHY is not set >> > # CONFIG_CORTINA_PHY is not set >> > # CONFIG_DAVICOM_PHY is not set >> > # CONFIG_DP83822_PHY is not set >> > # CONFIG_DP83TC811_PHY is not set >> > # CONFIG_DP83848_PHY is not set >> > # CONFIG_DP83867_PHY is not set >> > # CONFIG_DP83869_PHY is not set >> > # CONFIG_FIXED_PHY is not set >> > # CONFIG_ICPLUS_PHY is not set >> > # CONFIG_INTEL_XWAY_PHY is not set >> > # CONFIG_LSI_ET1011C_PHY is not set >> > # CONFIG_LXT_PHY is not set >> > # CONFIG_MARVELL_PHY is not set >> > # CONFIG_MARVELL_10G_PHY is not set >> > # CONFIG_MICREL_PHY is not set >> > # CONFIG_MICROCHIP_PHY is not set >> > # CONFIG_MICROCHIP_T1_PHY is not set >> > # CONFIG_MICROSEMI_PHY is not set >> > # CONFIG_NATIONAL_PHY is not set >> > # CONFIG_NXP_TJA11XX_PHY is not set >> > # CONFIG_QSEMI_PHY is not set >> > CONFIG_REALTEK_PHY=y >> > # CONFIG_RENESAS_PHY is not set >> > # CONFIG_ROCKCHIP_PHY is not set >> > # CONFIG_SMSC_PHY is not set >> > # CONFIG_STE10XP is not set >> > # CONFIG_TERANETICS_PHY is not set >> > # CONFIG_VITESSE_PHY is not set >> > # CONFIG_XILINX_GMII2RGMII is not set >> > # CONFIG_PPP is not set >> > # CONFIG_SLIP is not set >> > # CONFIG_USB_NET_DRIVERS is not set >> > # CONFIG_WLAN is not set >> > >> > # >> > # Enable WiMAX (Networking options) to see the WiMAX drivers >> > # >> > # CONFIG_WAN is not set >> > # CONFIG_VMXNET3 is not set >> > # CONFIG_FUJITSU_ES is not set >> > # CONFIG_NETDEVSIM is not set >> > # CONFIG_NET_FAILOVER is not set >> > # CONFIG_ISDN is not set >> > # CONFIG_NVM is not set >> > >> > # >> > # Input device support >> > # >> > CONFIG_INPUT=y >> > # CONFIG_INPUT_FF_MEMLESS is not set >> > # CONFIG_INPUT_POLLDEV is not set >> > # CONFIG_INPUT_SPARSEKMAP is not set >> > # CONFIG_INPUT_MATRIXKMAP is not set >> > >> > # >> > # Userland interfaces >> > # >> > CONFIG_INPUT_MOUSEDEV=y >> > CONFIG_INPUT_MOUSEDEV_PSAUX=y >> > CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 >> > CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 >> > # CONFIG_INPUT_JOYDEV is not set >> > CONFIG_INPUT_EVDEV=y >> > # CONFIG_INPUT_EVBUG is not set >> > >> > # >> > # Input Device Drivers >> > # >> > CONFIG_INPUT_KEYBOARD=y >> > # CONFIG_KEYBOARD_ADP5588 is not set >> > # CONFIG_KEYBOARD_ADP5589 is not set >> > CONFIG_KEYBOARD_ATKBD=y >> > # CONFIG_KEYBOARD_QT1050 is not set >> > # CONFIG_KEYBOARD_QT1070 is not set >> > # CONFIG_KEYBOARD_QT2160 is not set >> > # CONFIG_KEYBOARD_DLINK_DIR685 is not set >> > # CONFIG_KEYBOARD_LKKBD is not set >> > # CONFIG_KEYBOARD_TCA6416 is not set >> > # CONFIG_KEYBOARD_TCA8418 is not set >> > # CONFIG_KEYBOARD_LM8333 is not set >> > # CONFIG_KEYBOARD_MAX7359 is not set >> > # CONFIG_KEYBOARD_MCS is not set >> > # CONFIG_KEYBOARD_MPR121 is not set >> > # CONFIG_KEYBOARD_NEWTON is not set >> > # CONFIG_KEYBOARD_OPENCORES is not set >> > # CONFIG_KEYBOARD_SAMSUNG is not set >> > # CONFIG_KEYBOARD_STOWAWAY is not set >> > # CONFIG_KEYBOARD_SUNKBD is not set >> > # CONFIG_KEYBOARD_XTKBD is not set >> > CONFIG_INPUT_MOUSE=y >> > CONFIG_MOUSE_PS2=y >> > # CONFIG_MOUSE_PS2_ALPS is not set >> > # CONFIG_MOUSE_PS2_BYD is not set >> > # CONFIG_MOUSE_PS2_LOGIPS2PP is not set >> > # CONFIG_MOUSE_PS2_SYNAPTICS is not set >> > CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y >> > # CONFIG_MOUSE_PS2_CYPRESS is not set >> > # CONFIG_MOUSE_PS2_LIFEBOOK is not set >> > # CONFIG_MOUSE_PS2_TRACKPOINT is not set >> > # CONFIG_MOUSE_PS2_ELANTECH is not set >> > # CONFIG_MOUSE_PS2_SENTELIC is not set >> > # CONFIG_MOUSE_PS2_TOUCHKIT is not set >> > # CONFIG_MOUSE_PS2_FOCALTECH is not set >> > CONFIG_MOUSE_PS2_SMBUS=y >> > # CONFIG_MOUSE_SERIAL is not set >> > # CONFIG_MOUSE_APPLETOUCH is not set >> > # CONFIG_MOUSE_BCM5974 is not set >> > # CONFIG_MOUSE_CYAPA is not set >> > # CONFIG_MOUSE_ELAN_I2C is not set >> > # CONFIG_MOUSE_VSXXXAA is not set >> > # CONFIG_MOUSE_SYNAPTICS_I2C is not set >> > # CONFIG_MOUSE_SYNAPTICS_USB is not set >> > # CONFIG_INPUT_JOYSTICK is not set >> > # CONFIG_INPUT_TABLET is not set >> > # CONFIG_INPUT_TOUCHSCREEN is not set >> > # CONFIG_INPUT_MISC is not set >> > # CONFIG_RMI4_CORE is not set >> > >> > # >> > # Hardware I/O ports >> > # >> > CONFIG_SERIO=y >> > CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y >> > CONFIG_SERIO_I8042=y >> > # CONFIG_SERIO_SERPORT is not set >> > # CONFIG_SERIO_CT82C710 is not set >> > # CONFIG_SERIO_PCIPS2 is not set >> > CONFIG_SERIO_LIBPS2=y >> > # CONFIG_SERIO_RAW is not set >> > # CONFIG_SERIO_ALTERA_PS2 is not set >> > # CONFIG_SERIO_PS2MULT is not set >> > # CONFIG_SERIO_ARC_PS2 is not set >> > # CONFIG_USERIO is not set >> > # CONFIG_GAMEPORT is not set >> > # end of Hardware I/O ports >> > # end of Input device support >> > >> > # >> > # Character devices >> > # >> > CONFIG_TTY=y >> > CONFIG_VT=y >> > CONFIG_CONSOLE_TRANSLATIONS=y >> > CONFIG_VT_CONSOLE=y >> > CONFIG_HW_CONSOLE=y >> > # CONFIG_VT_HW_CONSOLE_BINDING is not set >> > CONFIG_UNIX98_PTYS=y >> > CONFIG_LEGACY_PTYS=y >> > CONFIG_LEGACY_PTY_COUNT=256 >> > CONFIG_LDISC_AUTOLOAD=y >> > >> > # >> > # Serial drivers >> > # >> > CONFIG_SERIAL_EARLYCON=y >> > CONFIG_SERIAL_8250=y >> > CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y >> > CONFIG_SERIAL_8250_PNP=y >> > # CONFIG_SERIAL_8250_16550A_VARIANTS is not set >> > # CONFIG_SERIAL_8250_FINTEK is not set >> > CONFIG_SERIAL_8250_CONSOLE=y >> > CONFIG_SERIAL_8250_PCI=y >> > # CONFIG_SERIAL_8250_EXAR is not set >> > CONFIG_SERIAL_8250_NR_UARTS=4 >> > CONFIG_SERIAL_8250_RUNTIME_UARTS=4 >> > CONFIG_SERIAL_8250_EXTENDED=y >> > # CONFIG_SERIAL_8250_MANY_PORTS is not set >> > CONFIG_SERIAL_8250_SHARE_IRQ=y >> > # CONFIG_SERIAL_8250_DETECT_IRQ is not set >> > # CONFIG_SERIAL_8250_RSA is not set >> > CONFIG_SERIAL_8250_DWLIB=y >> > # CONFIG_SERIAL_8250_DW is not set >> > # CONFIG_SERIAL_8250_RT288X is not set >> > CONFIG_SERIAL_8250_LPSS=y >> > CONFIG_SERIAL_8250_MID=y >> > >> > # >> > # Non-8250 serial port support >> > # >> > # CONFIG_SERIAL_UARTLITE is not set >> > CONFIG_SERIAL_CORE=y >> > CONFIG_SERIAL_CORE_CONSOLE=y >> > # CONFIG_SERIAL_JSM is not set >> > # CONFIG_SERIAL_SCCNXP is not set >> > # CONFIG_SERIAL_SC16IS7XX is not set >> > # CONFIG_SERIAL_ALTERA_JTAGUART is not set >> > # CONFIG_SERIAL_ALTERA_UART is not set >> > # CONFIG_SERIAL_ARC is not set >> > # CONFIG_SERIAL_RP2 is not set >> > # CONFIG_SERIAL_FSL_LPUART is not set >> > # CONFIG_SERIAL_FSL_LINFLEXUART is not set >> > # CONFIG_SERIAL_SPRD is not set >> > # end of Serial drivers >> > >> > # CONFIG_SERIAL_NONSTANDARD is not set >> > # CONFIG_N_GSM is not set >> > # CONFIG_NOZOMI is not set >> > # CONFIG_NULL_TTY is not set >> > # CONFIG_TRACE_SINK is not set >> > # CONFIG_SERIAL_DEV_BUS is not set >> > # CONFIG_TTY_PRINTK is not set >> > CONFIG_IPMI_HANDLER=y >> > CONFIG_IPMI_DMI_DECODE=y >> > CONFIG_IPMI_PLAT_DATA=y >> > # CONFIG_IPMI_PANIC_EVENT is not set >> > CONFIG_IPMI_DEVICE_INTERFACE=y >> > CONFIG_IPMI_SI=y >> > CONFIG_IPMI_SSIF=y >> > # CONFIG_IPMI_WATCHDOG is not set >> > # CONFIG_IPMI_POWEROFF is not set >> > # CONFIG_HW_RANDOM is not set >> > # CONFIG_APPLICOM is not set >> > # CONFIG_MWAVE is not set >> > # CONFIG_DEVMEM is not set >> > CONFIG_DEVKMEM=y >> > # CONFIG_NVRAM is not set >> > # CONFIG_RAW_DRIVER is not set >> > CONFIG_DEVPORT=y >> > CONFIG_HPET=y >> > CONFIG_HPET_MMAP=y >> > CONFIG_HPET_MMAP_DEFAULT=y >> > # CONFIG_HANGCHECK_TIMER is not set >> > CONFIG_TCG_TPM=y >> > # CONFIG_TCG_TIS is not set >> > # CONFIG_TCG_TIS_I2C_ATMEL is not set >> > # CONFIG_TCG_TIS_I2C_INFINEON is not set >> > # CONFIG_TCG_TIS_I2C_NUVOTON is not set >> > # CONFIG_TCG_NSC is not set >> > # CONFIG_TCG_ATMEL is not set >> > # CONFIG_TCG_INFINEON is not set >> > # CONFIG_TCG_CRB is not set >> > CONFIG_TCG_VTPM_PROXY=y >> > # CONFIG_TCG_TIS_ST33ZP24_I2C is not set >> > # CONFIG_TELCLOCK is not set >> > # CONFIG_XILLYBUS is not set >> > # end of Character devices >> > >> > # CONFIG_RANDOM_TRUST_CPU is not set >> > # CONFIG_RANDOM_TRUST_BOOTLOADER is not set >> > >> > # >> > # I2C support >> > # >> > CONFIG_I2C=y >> > CONFIG_ACPI_I2C_OPREGION=y >> > CONFIG_I2C_BOARDINFO=y >> > CONFIG_I2C_COMPAT=y >> > CONFIG_I2C_CHARDEV=y >> > CONFIG_I2C_MUX=y >> > >> > # >> > # Multiplexer I2C Chip support >> > # >> > # CONFIG_I2C_MUX_LTC4306 is not set >> > # CONFIG_I2C_MUX_PCA9541 is not set >> > # CONFIG_I2C_MUX_REG is not set >> > # CONFIG_I2C_MUX_MLXCPLD is not set >> > # end of Multiplexer I2C Chip support >> > >> > CONFIG_I2C_HELPER_AUTO=y >> > CONFIG_I2C_SMBUS=y >> > CONFIG_I2C_ALGOBIT=y >> > >> > # >> > # I2C Hardware Bus support >> > # >> > >> > # >> > # PC SMBus host controller drivers >> > # >> > # CONFIG_I2C_ALI1535 is not set >> > # CONFIG_I2C_ALI1563 is not set >> > # CONFIG_I2C_ALI15X3 is not set >> > # CONFIG_I2C_AMD756 is not set >> > # CONFIG_I2C_AMD8111 is not set >> > # CONFIG_I2C_AMD_MP2 is not set >> > CONFIG_I2C_I801=y >> > # CONFIG_I2C_ISCH is not set >> > # CONFIG_I2C_ISMT is not set >> > # CONFIG_I2C_PIIX4 is not set >> > # CONFIG_I2C_NFORCE2 is not set >> > # CONFIG_I2C_NVIDIA_GPU is not set >> > # CONFIG_I2C_SIS5595 is not set >> > # CONFIG_I2C_SIS630 is not set >> > # CONFIG_I2C_SIS96X is not set >> > # CONFIG_I2C_VIA is not set >> > # CONFIG_I2C_VIAPRO is not set >> > >> > # >> > # ACPI drivers >> > # >> > CONFIG_I2C_SCMI=y >> > >> > # >> > # I2C system bus drivers (mostly embedded / system-on-chip) >> > # >> > # CONFIG_I2C_DESIGNWARE_PLATFORM is not set >> > # CONFIG_I2C_DESIGNWARE_PCI is not set >> > # CONFIG_I2C_EMEV2 is not set >> > # CONFIG_I2C_OCORES is not set >> > # CONFIG_I2C_PCA_PLATFORM is not set >> > # CONFIG_I2C_SIMTEC is not set >> > # CONFIG_I2C_XILINX is not set >> > >> > # >> > # External I2C/SMBus adapter drivers >> > # >> > # CONFIG_I2C_DIOLAN_U2C is not set >> > # CONFIG_I2C_ROBOTFUZZ_OSIF is not set >> > # CONFIG_I2C_TAOS_EVM is not set >> > # CONFIG_I2C_TINY_USB is not set >> > >> > # >> > # Other I2C/SMBus bus drivers >> > # >> > # CONFIG_I2C_MLXCPLD is not set >> > # end of I2C Hardware Bus support >> > >> > # CONFIG_I2C_STUB is not set >> > # CONFIG_I2C_SLAVE is not set >> > # CONFIG_I2C_DEBUG_CORE is not set >> > # CONFIG_I2C_DEBUG_ALGO is not set >> > # CONFIG_I2C_DEBUG_BUS is not set >> > # end of I2C support >> > >> > # CONFIG_I3C is not set >> > # CONFIG_SPI is not set >> > # CONFIG_SPMI is not set >> > # CONFIG_HSI is not set >> > CONFIG_PPS=y >> > # CONFIG_PPS_DEBUG is not set >> > >> > # >> > # PPS clients support >> > # >> > # CONFIG_PPS_CLIENT_KTIMER is not set >> > # CONFIG_PPS_CLIENT_LDISC is not set >> > # CONFIG_PPS_CLIENT_GPIO is not set >> > >> > # >> > # PPS generators support >> > # >> > >> > # >> > # PTP clock support >> > # >> > CONFIG_PTP_1588_CLOCK=y >> > >> > # >> > # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. >> > # >> > # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set >> > # CONFIG_PTP_1588_CLOCK_IDTCM is not set >> > # end of PTP clock support >> > >> > # CONFIG_PINCTRL is not set >> > # CONFIG_GPIOLIB is not set >> > # CONFIG_W1 is not set >> > # CONFIG_POWER_AVS is not set >> > # CONFIG_POWER_RESET is not set >> > CONFIG_POWER_SUPPLY=y >> > # CONFIG_POWER_SUPPLY_DEBUG is not set >> > CONFIG_POWER_SUPPLY_HWMON=y >> > # CONFIG_PDA_POWER is not set >> > # CONFIG_TEST_POWER is not set >> > # CONFIG_CHARGER_ADP5061 is not set >> > # CONFIG_BATTERY_DS2780 is not set >> > # CONFIG_BATTERY_DS2781 is not set >> > # CONFIG_BATTERY_DS2782 is not set >> > # CONFIG_BATTERY_SBS is not set >> > # CONFIG_CHARGER_SBS is not set >> > # CONFIG_BATTERY_BQ27XXX is not set >> > # CONFIG_BATTERY_MAX17040 is not set >> > # CONFIG_BATTERY_MAX17042 is not set >> > # CONFIG_CHARGER_MAX8903 is not set >> > # CONFIG_CHARGER_LP8727 is not set >> > # CONFIG_CHARGER_BQ2415X is not set >> > # CONFIG_CHARGER_SMB347 is not set >> > # CONFIG_BATTERY_GAUGE_LTC2941 is not set >> > CONFIG_HWMON=y >> > # CONFIG_HWMON_DEBUG_CHIP is not set >> > >> > # >> > # Native drivers >> > # >> > # CONFIG_SENSORS_ABITUGURU is not set >> > # CONFIG_SENSORS_ABITUGURU3 is not set >> > # CONFIG_SENSORS_AD7414 is not set >> > # CONFIG_SENSORS_AD7418 is not set >> > # CONFIG_SENSORS_ADM1021 is not set >> > # CONFIG_SENSORS_ADM1025 is not set >> > # CONFIG_SENSORS_ADM1026 is not set >> > # CONFIG_SENSORS_ADM1029 is not set >> > # CONFIG_SENSORS_ADM1031 is not set >> > # CONFIG_SENSORS_ADM1177 is not set >> > # CONFIG_SENSORS_ADM9240 is not set >> > # CONFIG_SENSORS_ADT7410 is not set >> > # CONFIG_SENSORS_ADT7411 is not set >> > # CONFIG_SENSORS_ADT7462 is not set >> > # CONFIG_SENSORS_ADT7470 is not set >> > # CONFIG_SENSORS_ADT7475 is not set >> > # CONFIG_SENSORS_AS370 is not set >> > # CONFIG_SENSORS_ASC7621 is not set >> > # CONFIG_SENSORS_AXI_FAN_CONTROL is not set >> > # CONFIG_SENSORS_K8TEMP is not set >> > # CONFIG_SENSORS_K10TEMP is not set >> > # CONFIG_SENSORS_FAM15H_POWER is not set >> > # CONFIG_SENSORS_APPLESMC is not set >> > # CONFIG_SENSORS_ASB100 is not set >> > # CONFIG_SENSORS_ASPEED is not set >> > # CONFIG_SENSORS_ATXP1 is not set >> > # CONFIG_SENSORS_DRIVETEMP is not set >> > # CONFIG_SENSORS_DS620 is not set >> > # CONFIG_SENSORS_DS1621 is not set >> > # CONFIG_SENSORS_DELL_SMM is not set >> > # CONFIG_SENSORS_I5K_AMB is not set >> > # CONFIG_SENSORS_F71805F is not set >> > # CONFIG_SENSORS_F71882FG is not set >> > # CONFIG_SENSORS_F75375S is not set >> > # CONFIG_SENSORS_FSCHMD is not set >> > # CONFIG_SENSORS_FTSTEUTATES is not set >> > # CONFIG_SENSORS_GL518SM is not set >> > # CONFIG_SENSORS_GL520SM is not set >> > # CONFIG_SENSORS_G760A is not set >> > # CONFIG_SENSORS_G762 is not set >> > # CONFIG_SENSORS_HIH6130 is not set >> > # CONFIG_SENSORS_IBMAEM is not set >> > # CONFIG_SENSORS_IBMPEX is not set >> > # CONFIG_SENSORS_I5500 is not set >> > CONFIG_SENSORS_CORETEMP=y >> > # CONFIG_SENSORS_IT87 is not set >> > # CONFIG_SENSORS_JC42 is not set >> > # CONFIG_SENSORS_POWR1220 is not set >> > # CONFIG_SENSORS_LINEAGE is not set >> > # CONFIG_SENSORS_LTC2945 is not set >> > # CONFIG_SENSORS_LTC2947_I2C is not set >> > # CONFIG_SENSORS_LTC2990 is not set >> > # CONFIG_SENSORS_LTC4151 is not set >> > # CONFIG_SENSORS_LTC4215 is not set >> > # CONFIG_SENSORS_LTC4222 is not set >> > # CONFIG_SENSORS_LTC4245 is not set >> > # CONFIG_SENSORS_LTC4260 is not set >> > # CONFIG_SENSORS_LTC4261 is not set >> > # CONFIG_SENSORS_MAX16065 is not set >> > # CONFIG_SENSORS_MAX1619 is not set >> > # CONFIG_SENSORS_MAX1668 is not set >> > # CONFIG_SENSORS_MAX197 is not set >> > # CONFIG_SENSORS_MAX31730 is not set >> > # CONFIG_SENSORS_MAX6621 is not set >> > # CONFIG_SENSORS_MAX6639 is not set >> > # CONFIG_SENSORS_MAX6642 is not set >> > # CONFIG_SENSORS_MAX6650 is not set >> > # CONFIG_SENSORS_MAX6697 is not set >> > # CONFIG_SENSORS_MAX31790 is not set >> > # CONFIG_SENSORS_MCP3021 is not set >> > # CONFIG_SENSORS_TC654 is not set >> > # CONFIG_SENSORS_LM63 is not set >> > # CONFIG_SENSORS_LM73 is not set >> > # CONFIG_SENSORS_LM75 is not set >> > # CONFIG_SENSORS_LM77 is not set >> > # CONFIG_SENSORS_LM78 is not set >> > # CONFIG_SENSORS_LM80 is not set >> > # CONFIG_SENSORS_LM83 is not set >> > # CONFIG_SENSORS_LM85 is not set >> > # CONFIG_SENSORS_LM87 is not set >> > # CONFIG_SENSORS_LM90 is not set >> > # CONFIG_SENSORS_LM92 is not set >> > # CONFIG_SENSORS_LM93 is not set >> > # CONFIG_SENSORS_LM95234 is not set >> > # CONFIG_SENSORS_LM95241 is not set >> > # CONFIG_SENSORS_LM95245 is not set >> > # CONFIG_SENSORS_PC87360 is not set >> > # CONFIG_SENSORS_PC87427 is not set >> > # CONFIG_SENSORS_NTC_THERMISTOR is not set >> > # CONFIG_SENSORS_NCT6683 is not set >> > # CONFIG_SENSORS_NCT6775 is not set >> > # CONFIG_SENSORS_NCT7802 is not set >> > # CONFIG_SENSORS_NCT7904 is not set >> > # CONFIG_SENSORS_NPCM7XX is not set >> > # CONFIG_SENSORS_PCF8591 is not set >> > CONFIG_PMBUS=y >> > CONFIG_SENSORS_PMBUS=y >> > # CONFIG_SENSORS_ADM1275 is not set >> > # CONFIG_SENSORS_BEL_PFE is not set >> > # CONFIG_SENSORS_INSPUR_IPSPS is not set >> > # CONFIG_SENSORS_IR35221 is not set >> > # CONFIG_SENSORS_IR38064 is not set >> > # CONFIG_SENSORS_IRPS5401 is not set >> > # CONFIG_SENSORS_ISL68137 is not set >> > # CONFIG_SENSORS_LM25066 is not set >> > # CONFIG_SENSORS_LTC2978 is not set >> > # CONFIG_SENSORS_LTC3815 is not set >> > # CONFIG_SENSORS_MAX16064 is not set >> > # CONFIG_SENSORS_MAX20730 is not set >> > # CONFIG_SENSORS_MAX20751 is not set >> > # CONFIG_SENSORS_MAX31785 is not set >> > # CONFIG_SENSORS_MAX34440 is not set >> > # CONFIG_SENSORS_MAX8688 is not set >> > # CONFIG_SENSORS_PXE1610 is not set >> > # CONFIG_SENSORS_TPS40422 is not set >> > # CONFIG_SENSORS_TPS53679 is not set >> > # CONFIG_SENSORS_UCD9000 is not set >> > # CONFIG_SENSORS_UCD9200 is not set >> > # CONFIG_SENSORS_XDPE122 is not set >> > # CONFIG_SENSORS_ZL6100 is not set >> > # CONFIG_SENSORS_SHT21 is not set >> > # CONFIG_SENSORS_SHT3x is not set >> > # CONFIG_SENSORS_SHTC1 is not set >> > # CONFIG_SENSORS_SIS5595 is not set >> > # CONFIG_SENSORS_DME1737 is not set >> > # CONFIG_SENSORS_EMC1403 is not set >> > # CONFIG_SENSORS_EMC2103 is not set >> > # CONFIG_SENSORS_EMC6W201 is not set >> > # CONFIG_SENSORS_SMSC47M1 is not set >> > # CONFIG_SENSORS_SMSC47M192 is not set >> > # CONFIG_SENSORS_SMSC47B397 is not set >> > # CONFIG_SENSORS_SCH5627 is not set >> > # CONFIG_SENSORS_SCH5636 is not set >> > # CONFIG_SENSORS_STTS751 is not set >> > # CONFIG_SENSORS_SMM665 is not set >> > # CONFIG_SENSORS_ADC128D818 is not set >> > # CONFIG_SENSORS_ADS7828 is not set >> > # CONFIG_SENSORS_AMC6821 is not set >> > # CONFIG_SENSORS_INA209 is not set >> > # CONFIG_SENSORS_INA2XX is not set >> > # CONFIG_SENSORS_INA3221 is not set >> > # CONFIG_SENSORS_TC74 is not set >> > # CONFIG_SENSORS_THMC50 is not set >> > # CONFIG_SENSORS_TMP102 is not set >> > # CONFIG_SENSORS_TMP103 is not set >> > # CONFIG_SENSORS_TMP108 is not set >> > # CONFIG_SENSORS_TMP401 is not set >> > # CONFIG_SENSORS_TMP421 is not set >> > # CONFIG_SENSORS_TMP513 is not set >> > # CONFIG_SENSORS_VIA_CPUTEMP is not set >> > # CONFIG_SENSORS_VIA686A is not set >> > # CONFIG_SENSORS_VT1211 is not set >> > # CONFIG_SENSORS_VT8231 is not set >> > # CONFIG_SENSORS_W83773G is not set >> > # CONFIG_SENSORS_W83781D is not set >> > # CONFIG_SENSORS_W83791D is not set >> > # CONFIG_SENSORS_W83792D is not set >> > # CONFIG_SENSORS_W83793 is not set >> > # CONFIG_SENSORS_W83795 is not set >> > # CONFIG_SENSORS_W83L785TS is not set >> > # CONFIG_SENSORS_W83L786NG is not set >> > # CONFIG_SENSORS_W83627HF is not set >> > # CONFIG_SENSORS_W83627EHF is not set >> > # CONFIG_SENSORS_XGENE is not set >> > >> > # >> > # ACPI drivers >> > # >> > CONFIG_SENSORS_ACPI_POWER=y >> > CONFIG_SENSORS_ATK0110=y >> > CONFIG_THERMAL=y >> > # CONFIG_THERMAL_STATISTICS is not set >> > CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 >> > CONFIG_THERMAL_HWMON=y >> > CONFIG_THERMAL_WRITABLE_TRIPS=y >> > CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y >> > # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set >> > # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set >> > # CONFIG_THERMAL_GOV_FAIR_SHARE is not set >> > CONFIG_THERMAL_GOV_STEP_WISE=y >> > # CONFIG_THERMAL_GOV_BANG_BANG is not set >> > CONFIG_THERMAL_GOV_USER_SPACE=y >> > # CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set >> > # CONFIG_THERMAL_EMULATION is not set >> > >> > # >> > # Intel thermal drivers >> > # >> > # CONFIG_INTEL_POWERCLAMP is not set >> > CONFIG_X86_PKG_TEMP_THERMAL=y >> > # CONFIG_INTEL_SOC_DTS_THERMAL is not set >> > >> > # >> > # ACPI INT340X thermal drivers >> > # >> > # CONFIG_INT340X_THERMAL is not set >> > # end of ACPI INT340X thermal drivers >> > >> > CONFIG_INTEL_PCH_THERMAL=y >> > # end of Intel thermal drivers >> > >> > CONFIG_WATCHDOG=y >> > CONFIG_WATCHDOG_CORE=y >> > # CONFIG_WATCHDOG_NOWAYOUT is not set >> > CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y >> > CONFIG_WATCHDOG_OPEN_TIMEOUT=0 >> > # CONFIG_WATCHDOG_SYSFS is not set >> > >> > # >> > # Watchdog Pretimeout Governors >> > # >> > # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set >> > >> > # >> > # Watchdog Device Drivers >> > # >> > # CONFIG_SOFT_WATCHDOG is not set >> > # CONFIG_WDAT_WDT is not set >> > # CONFIG_XILINX_WATCHDOG is not set >> > # CONFIG_ZIIRAVE_WATCHDOG is not set >> > # CONFIG_CADENCE_WATCHDOG is not set >> > # CONFIG_DW_WATCHDOG is not set >> > # CONFIG_MAX63XX_WATCHDOG is not set >> > # CONFIG_ACQUIRE_WDT is not set >> > # CONFIG_ADVANTECH_WDT is not set >> > # CONFIG_ALIM1535_WDT is not set >> > # CONFIG_ALIM7101_WDT is not set >> > # CONFIG_EBC_C384_WDT is not set >> > # CONFIG_F71808E_WDT is not set >> > # CONFIG_SP5100_TCO is not set >> > # CONFIG_SBC_FITPC2_WATCHDOG is not set >> > # CONFIG_EUROTECH_WDT is not set >> > # CONFIG_IB700_WDT is not set >> > # CONFIG_IBMASR is not set >> > # CONFIG_WAFER_WDT is not set >> > # CONFIG_I6300ESB_WDT is not set >> > # CONFIG_IE6XX_WDT is not set >> > CONFIG_ITCO_WDT=y >> > CONFIG_ITCO_VENDOR_SUPPORT=y >> > # CONFIG_IT8712F_WDT is not set >> > # CONFIG_IT87_WDT is not set >> > # CONFIG_HP_WATCHDOG is not set >> > # CONFIG_SC1200_WDT is not set >> > # CONFIG_PC87413_WDT is not set >> > # CONFIG_NV_TCO is not set >> > # CONFIG_60XX_WDT is not set >> > # CONFIG_CPU5_WDT is not set >> > # CONFIG_SMSC_SCH311X_WDT is not set >> > # CONFIG_SMSC37B787_WDT is not set >> > # CONFIG_TQMX86_WDT is not set >> > # CONFIG_VIA_WDT is not set >> > # CONFIG_W83627HF_WDT is not set >> > # CONFIG_W83877F_WDT is not set >> > # CONFIG_W83977F_WDT is not set >> > # CONFIG_MACHZ_WDT is not set >> > # CONFIG_SBC_EPX_C3_WATCHDOG is not set >> > CONFIG_INTEL_MEI_WDT=y >> > # CONFIG_NI903X_WDT is not set >> > # CONFIG_NIC7018_WDT is not set >> > >> > # >> > # PCI-based Watchdog Cards >> > # >> > # CONFIG_PCIPCWATCHDOG is not set >> > # CONFIG_WDTPCI is not set >> > >> > # >> > # USB-based Watchdog Cards >> > # >> > # CONFIG_USBPCWATCHDOG is not set >> > CONFIG_SSB_POSSIBLE=y >> > # CONFIG_SSB is not set >> > CONFIG_BCMA_POSSIBLE=y >> > # CONFIG_BCMA is not set >> > >> > # >> > # Multifunction device drivers >> > # >> > CONFIG_MFD_CORE=y >> > # CONFIG_MFD_AS3711 is not set >> > # CONFIG_PMIC_ADP5520 is not set >> > # CONFIG_MFD_BCM590XX is not set >> > # CONFIG_MFD_BD9571MWV is not set >> > # CONFIG_MFD_AXP20X_I2C is not set >> > # CONFIG_MFD_MADERA is not set >> > # CONFIG_PMIC_DA903X is not set >> > # CONFIG_MFD_DA9052_I2C is not set >> > # CONFIG_MFD_DA9055 is not set >> > # CONFIG_MFD_DA9062 is not set >> > # CONFIG_MFD_DA9063 is not set >> > # CONFIG_MFD_DA9150 is not set >> > # CONFIG_MFD_DLN2 is not set >> > # CONFIG_MFD_MC13XXX_I2C is not set >> > # CONFIG_HTC_PASIC3 is not set >> > # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set >> > CONFIG_LPC_ICH=y >> > # CONFIG_LPC_SCH is not set >> > CONFIG_MFD_INTEL_LPSS=y >> > CONFIG_MFD_INTEL_LPSS_ACPI=y >> > CONFIG_MFD_INTEL_LPSS_PCI=y >> > # CONFIG_MFD_IQS62X is not set >> > # CONFIG_MFD_JANZ_CMODIO is not set >> > # CONFIG_MFD_KEMPLD is not set >> > # CONFIG_MFD_88PM800 is not set >> > # CONFIG_MFD_88PM805 is not set >> > # CONFIG_MFD_88PM860X is not set >> > # CONFIG_MFD_MAX14577 is not set >> > # CONFIG_MFD_MAX77693 is not set >> > # CONFIG_MFD_MAX77843 is not set >> > # CONFIG_MFD_MAX8907 is not set >> > # CONFIG_MFD_MAX8925 is not set >> > # CONFIG_MFD_MAX8997 is not set >> > # CONFIG_MFD_MAX8998 is not set >> > # CONFIG_MFD_MT6397 is not set >> > # CONFIG_MFD_MENF21BMC is not set >> > # CONFIG_MFD_VIPERBOARD is not set >> > # CONFIG_MFD_RETU is not set >> > # CONFIG_MFD_PCF50633 is not set >> > # CONFIG_MFD_RDC321X is not set >> > # CONFIG_MFD_RT5033 is not set >> > # CONFIG_MFD_RC5T583 is not set >> > # CONFIG_MFD_SEC_CORE is not set >> > # CONFIG_MFD_SI476X_CORE is not set >> > # CONFIG_MFD_SM501 is not set >> > # CONFIG_MFD_SKY81452 is not set >> > # CONFIG_MFD_SMSC is not set >> > # CONFIG_ABX500_CORE is not set >> > # CONFIG_MFD_SYSCON is not set >> > # CONFIG_MFD_TI_AM335X_TSCADC is not set >> > # CONFIG_MFD_LP3943 is not set >> > # CONFIG_MFD_LP8788 is not set >> > # CONFIG_MFD_TI_LMU is not set >> > # CONFIG_MFD_PALMAS is not set >> > # CONFIG_TPS6105X is not set >> > # CONFIG_TPS6507X is not set >> > # CONFIG_MFD_TPS65086 is not set >> > # CONFIG_MFD_TPS65090 is not set >> > # CONFIG_MFD_TI_LP873X is not set >> > # CONFIG_MFD_TPS6586X is not set >> > # CONFIG_MFD_TPS65912_I2C is not set >> > # CONFIG_MFD_TPS80031 is not set >> > # CONFIG_TWL4030_CORE is not set >> > # CONFIG_TWL6040_CORE is not set >> > # CONFIG_MFD_WL1273_CORE is not set >> > # CONFIG_MFD_LM3533 is not set >> > # CONFIG_MFD_TQMX86 is not set >> > # CONFIG_MFD_VX855 is not set >> > # CONFIG_MFD_ARIZONA_I2C is not set >> > # CONFIG_MFD_WM8400 is not set >> > # CONFIG_MFD_WM831X_I2C is not set >> > # CONFIG_MFD_WM8350_I2C is not set >> > # CONFIG_MFD_WM8994 is not set >> > # end of Multifunction device drivers >> > >> > # CONFIG_REGULATOR is not set >> > # CONFIG_RC_CORE is not set >> > # CONFIG_MEDIA_SUPPORT is not set >> > >> > # >> > # Graphics support >> > # >> > # CONFIG_AGP is not set >> > CONFIG_INTEL_GTT=y >> > CONFIG_VGA_ARB=y >> > CONFIG_VGA_ARB_MAX_GPUS=16 >> > # CONFIG_VGA_SWITCHEROO is not set >> > CONFIG_DRM=y >> > CONFIG_DRM_MIPI_DSI=y >> > # CONFIG_DRM_DP_AUX_CHARDEV is not set >> > # CONFIG_DRM_DEBUG_MM is not set >> > # CONFIG_DRM_DEBUG_SELFTEST is not set >> > CONFIG_DRM_KMS_HELPER=y >> > CONFIG_DRM_KMS_FB_HELPER=y >> > # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set >> > CONFIG_DRM_FBDEV_EMULATION=y >> > CONFIG_DRM_FBDEV_OVERALLOC=100 >> > # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set >> > # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set >> > # CONFIG_DRM_DP_CEC is not set >> > >> > # >> > # I2C encoder or helper chips >> > # >> > # CONFIG_DRM_I2C_CH7006 is not set >> > # CONFIG_DRM_I2C_SIL164 is not set >> > # CONFIG_DRM_I2C_NXP_TDA998X is not set >> > # CONFIG_DRM_I2C_NXP_TDA9950 is not set >> > # end of I2C encoder or helper chips >> > >> > # >> > # ARM devices >> > # >> > # end of ARM devices >> > >> > # CONFIG_DRM_RADEON is not set >> > # CONFIG_DRM_AMDGPU is not set >> > # CONFIG_DRM_NOUVEAU is not set >> > CONFIG_DRM_I915=y >> > CONFIG_DRM_I915_FORCE_PROBE="" >> > CONFIG_DRM_I915_CAPTURE_ERROR=y >> > CONFIG_DRM_I915_COMPRESS_ERROR=y >> > CONFIG_DRM_I915_USERPTR=y >> > # CONFIG_DRM_I915_GVT is not set >> > >> > # >> > # drm/i915 Debugging >> > # >> > # CONFIG_DRM_I915_WERROR is not set >> > # CONFIG_DRM_I915_DEBUG is not set >> > # CONFIG_DRM_I915_DEBUG_MMIO is not set >> > # CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set >> > # CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set >> > # CONFIG_DRM_I915_DEBUG_GUC is not set >> > # CONFIG_DRM_I915_SELFTEST is not set >> > # CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set >> > # CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set >> > # CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set >> > # end of drm/i915 Debugging >> > >> > # >> > # drm/i915 Profile Guided Optimisation >> > # >> > CONFIG_DRM_I915_FENCE_TIMEOUT=10000 >> > CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 >> > CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 >> > CONFIG_DRM_I915_PREEMPT_TIMEOUT=100 >> > CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 >> > CONFIG_DRM_I915_STOP_TIMEOUT=100 >> > CONFIG_DRM_I915_TIMESLICE_DURATION=1 >> > # end of drm/i915 Profile Guided Optimisation >> > >> > # CONFIG_DRM_VGEM is not set >> > # CONFIG_DRM_VKMS is not set >> > # CONFIG_DRM_VMWGFX is not set >> > # CONFIG_DRM_GMA500 is not set >> > # CONFIG_DRM_UDL is not set >> > # CONFIG_DRM_AST is not set >> > # CONFIG_DRM_MGAG200 is not set >> > # CONFIG_DRM_QXL is not set >> > # CONFIG_DRM_BOCHS is not set >> > CONFIG_DRM_PANEL=y >> > >> > # >> > # Display Panels >> > # >> > # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set >> > # end of Display Panels >> > >> > CONFIG_DRM_BRIDGE=y >> > CONFIG_DRM_PANEL_BRIDGE=y >> > >> > # >> > # Display Interface Bridges >> > # >> > # CONFIG_DRM_ANALOGIX_ANX78XX is not set >> > # end of Display Interface Bridges >> > >> > # CONFIG_DRM_ETNAVIV is not set >> > # CONFIG_DRM_CIRRUS_QEMU is not set >> > # CONFIG_DRM_GM12U320 is not set >> > # CONFIG_DRM_VBOXVIDEO is not set >> > # CONFIG_DRM_LEGACY is not set >> > CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y >> > >> > # >> > # Frame buffer Devices >> > # >> > CONFIG_FB_CMDLINE=y >> > CONFIG_FB_NOTIFY=y >> > CONFIG_FB=y >> > CONFIG_FIRMWARE_EDID=y >> > CONFIG_FB_CFB_FILLRECT=y >> > CONFIG_FB_CFB_COPYAREA=y >> > CONFIG_FB_CFB_IMAGEBLIT=y >> > CONFIG_FB_SYS_FILLRECT=y >> > CONFIG_FB_SYS_COPYAREA=y >> > CONFIG_FB_SYS_IMAGEBLIT=y >> > # CONFIG_FB_FOREIGN_ENDIAN is not set >> > CONFIG_FB_SYS_FOPS=y >> > CONFIG_FB_DEFERRED_IO=y >> > CONFIG_FB_MODE_HELPERS=y >> > # CONFIG_FB_TILEBLITTING is not set >> > >> > # >> > # Frame buffer hardware drivers >> > # >> > # CONFIG_FB_CIRRUS is not set >> > # CONFIG_FB_PM2 is not set >> > # CONFIG_FB_CYBER2000 is not set >> > # CONFIG_FB_ARC is not set >> > # CONFIG_FB_ASILIANT is not set >> > # CONFIG_FB_IMSTT is not set >> > # CONFIG_FB_VGA16 is not set >> > # CONFIG_FB_VESA is not set >> > # CONFIG_FB_EFI is not set >> > # CONFIG_FB_N411 is not set >> > # CONFIG_FB_HGA is not set >> > # CONFIG_FB_OPENCORES is not set >> > # CONFIG_FB_S1D13XXX is not set >> > # CONFIG_FB_NVIDIA is not set >> > # CONFIG_FB_RIVA is not set >> > # CONFIG_FB_I740 is not set >> > # CONFIG_FB_LE80578 is not set >> > # CONFIG_FB_MATROX is not set >> > # CONFIG_FB_RADEON is not set >> > # CONFIG_FB_ATY128 is not set >> > # CONFIG_FB_ATY is not set >> > # CONFIG_FB_S3 is not set >> > # CONFIG_FB_SAVAGE is not set >> > # CONFIG_FB_SIS is not set >> > # CONFIG_FB_NEOMAGIC is not set >> > # CONFIG_FB_KYRO is not set >> > # CONFIG_FB_3DFX is not set >> > # CONFIG_FB_VOODOO1 is not set >> > # CONFIG_FB_VT8623 is not set >> > # CONFIG_FB_TRIDENT is not set >> > # CONFIG_FB_ARK is not set >> > # CONFIG_FB_PM3 is not set >> > # CONFIG_FB_CARMINE is not set >> > # CONFIG_FB_SMSCUFX is not set >> > # CONFIG_FB_UDL is not set >> > # CONFIG_FB_IBM_GXT4500 is not set >> > # CONFIG_FB_VIRTUAL is not set >> > # CONFIG_FB_METRONOME is not set >> > # CONFIG_FB_MB862XX is not set >> > # CONFIG_FB_SIMPLE is not set >> > # CONFIG_FB_SM712 is not set >> > # end of Frame buffer Devices >> > >> > # >> > # Backlight & LCD device support >> > # >> > # CONFIG_LCD_CLASS_DEVICE is not set >> > CONFIG_BACKLIGHT_CLASS_DEVICE=y >> > # CONFIG_BACKLIGHT_GENERIC is not set >> > # CONFIG_BACKLIGHT_APPLE is not set >> > # CONFIG_BACKLIGHT_QCOM_WLED is not set >> > # CONFIG_BACKLIGHT_SAHARA is not set >> > # CONFIG_BACKLIGHT_ADP8860 is not set >> > # CONFIG_BACKLIGHT_ADP8870 is not set >> > # CONFIG_BACKLIGHT_LM3639 is not set >> > # CONFIG_BACKLIGHT_LV5207LP is not set >> > # CONFIG_BACKLIGHT_BD6107 is not set >> > # CONFIG_BACKLIGHT_ARCXCNN is not set >> > # end of Backlight & LCD device support >> > >> > CONFIG_HDMI=y >> > >> > # >> > # Console display driver support >> > # >> > CONFIG_VGA_CONSOLE=y >> > # CONFIG_VGACON_SOFT_SCROLLBACK is not set >> > CONFIG_DUMMY_CONSOLE=y >> > CONFIG_DUMMY_CONSOLE_COLUMNS=80 >> > CONFIG_DUMMY_CONSOLE_ROWS=25 >> > # CONFIG_FRAMEBUFFER_CONSOLE is not set >> > # end of Console display driver support >> > >> > CONFIG_LOGO=y >> > CONFIG_LOGO_LINUX_MONO=y >> > CONFIG_LOGO_LINUX_VGA16=y >> > CONFIG_LOGO_LINUX_CLUT224=y >> > # end of Graphics support >> > >> > # CONFIG_SOUND is not set >> > >> > # >> > # HID support >> > # >> > CONFIG_HID=y >> > # CONFIG_HID_BATTERY_STRENGTH is not set >> > # CONFIG_HIDRAW is not set >> > # CONFIG_UHID is not set >> > CONFIG_HID_GENERIC=y >> > >> > # >> > # Special HID drivers >> > # >> > # CONFIG_HID_A4TECH is not set >> > # CONFIG_HID_ACCUTOUCH is not set >> > # CONFIG_HID_ACRUX is not set >> > # CONFIG_HID_APPLE is not set >> > # CONFIG_HID_APPLEIR is not set >> > # CONFIG_HID_AUREAL is not set >> > # CONFIG_HID_BELKIN is not set >> > # CONFIG_HID_BETOP_FF is not set >> > # CONFIG_HID_CHERRY is not set >> > # CONFIG_HID_CHICONY is not set >> > # CONFIG_HID_COUGAR is not set >> > # CONFIG_HID_MACALLY is not set >> > # CONFIG_HID_CMEDIA is not set >> > # CONFIG_HID_CREATIVE_SB0540 is not set >> > # CONFIG_HID_CYPRESS is not set >> > # CONFIG_HID_DRAGONRISE is not set >> > # CONFIG_HID_EMS_FF is not set >> > # CONFIG_HID_ELECOM is not set >> > # CONFIG_HID_ELO is not set >> > # CONFIG_HID_EZKEY is not set >> > # CONFIG_HID_GEMBIRD is not set >> > # CONFIG_HID_GFRM is not set >> > # CONFIG_HID_GLORIOUS is not set >> > # CONFIG_HID_HOLTEK is not set >> > # CONFIG_HID_KEYTOUCH is not set >> > # CONFIG_HID_KYE is not set >> > # CONFIG_HID_UCLOGIC is not set >> > # CONFIG_HID_WALTOP is not set >> > # CONFIG_HID_VIEWSONIC is not set >> > # CONFIG_HID_GYRATION is not set >> > # CONFIG_HID_ICADE is not set >> > # CONFIG_HID_ITE is not set >> > # CONFIG_HID_JABRA is not set >> > # CONFIG_HID_TWINHAN is not set >> > # CONFIG_HID_KENSINGTON is not set >> > # CONFIG_HID_LCPOWER is not set >> > # CONFIG_HID_LENOVO is not set >> > # CONFIG_HID_MAGICMOUSE is not set >> > # CONFIG_HID_MALTRON is not set >> > # CONFIG_HID_MAYFLASH is not set >> > # CONFIG_HID_REDRAGON is not set >> > # CONFIG_HID_MICROSOFT is not set >> > # CONFIG_HID_MONTEREY is not set >> > # CONFIG_HID_MULTITOUCH is not set >> > # CONFIG_HID_NTI is not set >> > # CONFIG_HID_NTRIG is not set >> > # CONFIG_HID_ORTEK is not set >> > # CONFIG_HID_PANTHERLORD is not set >> > # CONFIG_HID_PENMOUNT is not set >> > # CONFIG_HID_PETALYNX is not set >> > # CONFIG_HID_PICOLCD is not set >> > # CONFIG_HID_PLANTRONICS is not set >> > # CONFIG_HID_PRIMAX is not set >> > # CONFIG_HID_RETRODE is not set >> > # CONFIG_HID_ROCCAT is not set >> > # CONFIG_HID_SAITEK is not set >> > # CONFIG_HID_SAMSUNG is not set >> > # CONFIG_HID_SPEEDLINK is not set >> > # CONFIG_HID_STEAM is not set >> > # CONFIG_HID_STEELSERIES is not set >> > # CONFIG_HID_SUNPLUS is not set >> > # CONFIG_HID_RMI is not set >> > # CONFIG_HID_GREENASIA is not set >> > # CONFIG_HID_SMARTJOYPLUS is not set >> > # CONFIG_HID_TIVO is not set >> > # CONFIG_HID_TOPSEED is not set >> > # CONFIG_HID_THRUSTMASTER is not set >> > # CONFIG_HID_UDRAW_PS3 is not set >> > # CONFIG_HID_WACOM is not set >> > # CONFIG_HID_XINMO is not set >> > # CONFIG_HID_ZEROPLUS is not set >> > # CONFIG_HID_ZYDACRON is not set >> > # CONFIG_HID_SENSOR_HUB is not set >> > # CONFIG_HID_ALPS is not set >> > # CONFIG_HID_MCP2221 is not set >> > # end of Special HID drivers >> > >> > # >> > # USB HID support >> > # >> > CONFIG_USB_HID=y >> > # CONFIG_HID_PID is not set >> > # CONFIG_USB_HIDDEV is not set >> > # end of USB HID support >> > >> > # >> > # I2C HID support >> > # >> > # CONFIG_I2C_HID is not set >> > # end of I2C HID support >> > >> > # >> > # Intel ISH HID support >> > # >> > CONFIG_INTEL_ISH_HID=y >> > # CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER is not set >> > # end of Intel ISH HID support >> > # end of HID support >> > >> > CONFIG_USB_OHCI_LITTLE_ENDIAN=y >> > CONFIG_USB_SUPPORT=y >> > CONFIG_USB_COMMON=y >> > # CONFIG_USB_ULPI_BUS is not set >> > CONFIG_USB_ARCH_HAS_HCD=y >> > CONFIG_USB=y >> > CONFIG_USB_PCI=y >> > # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set >> > >> > # >> > # Miscellaneous USB options >> > # >> > CONFIG_USB_DEFAULT_PERSIST=y >> > CONFIG_USB_DYNAMIC_MINORS=y >> > # CONFIG_USB_OTG is not set >> > # CONFIG_USB_OTG_WHITELIST is not set >> > # CONFIG_USB_OTG_BLACKLIST_HUB is not set >> > CONFIG_USB_AUTOSUSPEND_DELAY=2 >> > # CONFIG_USB_MON is not set >> > >> > # >> > # USB Host Controller Drivers >> > # >> > # CONFIG_USB_C67X00_HCD is not set >> > CONFIG_USB_XHCI_HCD=y >> > # CONFIG_USB_XHCI_DBGCAP is not set >> > CONFIG_USB_XHCI_PCI=y >> > # CONFIG_USB_XHCI_PLATFORM is not set >> > CONFIG_USB_EHCI_HCD=y >> > # CONFIG_USB_EHCI_ROOT_HUB_TT is not set >> > CONFIG_USB_EHCI_TT_NEWSCHED=y >> > CONFIG_USB_EHCI_PCI=y >> > # CONFIG_USB_EHCI_FSL is not set >> > # CONFIG_USB_EHCI_HCD_PLATFORM is not set >> > # CONFIG_USB_OXU210HP_HCD is not set >> > # CONFIG_USB_ISP116X_HCD is not set >> > # CONFIG_USB_FOTG210_HCD is not set >> > CONFIG_USB_OHCI_HCD=y >> > CONFIG_USB_OHCI_HCD_PCI=y >> > # CONFIG_USB_OHCI_HCD_PLATFORM is not set >> > CONFIG_USB_UHCI_HCD=y >> > # CONFIG_USB_SL811_HCD is not set >> > # CONFIG_USB_R8A66597_HCD is not set >> > # CONFIG_USB_HCD_TEST_MODE is not set >> > >> > # >> > # USB Device Class drivers >> > # >> > # CONFIG_USB_ACM is not set >> > # CONFIG_USB_PRINTER is not set >> > # CONFIG_USB_WDM is not set >> > # CONFIG_USB_TMC is not set >> > >> > # >> > # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may >> > # >> > >> > # >> > # also be needed; see USB_STORAGE Help for more info >> > # >> > CONFIG_USB_STORAGE=y >> > # CONFIG_USB_STORAGE_DEBUG is not set >> > # CONFIG_USB_STORAGE_REALTEK is not set >> > # CONFIG_USB_STORAGE_DATAFAB is not set >> > # CONFIG_USB_STORAGE_FREECOM is not set >> > # CONFIG_USB_STORAGE_ISD200 is not set >> > # CONFIG_USB_STORAGE_USBAT is not set >> > # CONFIG_USB_STORAGE_SDDR09 is not set >> > # CONFIG_USB_STORAGE_SDDR55 is not set >> > # CONFIG_USB_STORAGE_JUMPSHOT is not set >> > # CONFIG_USB_STORAGE_ALAUDA is not set >> > # CONFIG_USB_STORAGE_ONETOUCH is not set >> > # CONFIG_USB_STORAGE_KARMA is not set >> > # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set >> > # CONFIG_USB_STORAGE_ENE_UB6250 is not set >> > # CONFIG_USB_UAS is not set >> > >> > # >> > # USB Imaging devices >> > # >> > # CONFIG_USB_MDC800 is not set >> > # CONFIG_USB_MICROTEK is not set >> > # CONFIG_USBIP_CORE is not set >> > # CONFIG_USB_CDNS3 is not set >> > # CONFIG_USB_MUSB_HDRC is not set >> > # CONFIG_USB_DWC3 is not set >> > # CONFIG_USB_DWC2 is not set >> > # CONFIG_USB_CHIPIDEA is not set >> > # CONFIG_USB_ISP1760 is not set >> > >> > # >> > # USB port drivers >> > # >> > # CONFIG_USB_SERIAL is not set >> > >> > # >> > # USB Miscellaneous drivers >> > # >> > # CONFIG_USB_EMI62 is not set >> > # CONFIG_USB_EMI26 is not set >> > # CONFIG_USB_ADUTUX is not set >> > # CONFIG_USB_SEVSEG is not set >> > # CONFIG_USB_LEGOTOWER is not set >> > # CONFIG_USB_LCD is not set >> > # CONFIG_USB_CYPRESS_CY7C63 is not set >> > # CONFIG_USB_CYTHERM is not set >> > # CONFIG_USB_IDMOUSE is not set >> > # CONFIG_USB_FTDI_ELAN is not set >> > # CONFIG_USB_APPLEDISPLAY is not set >> > # CONFIG_APPLE_MFI_FASTCHARGE is not set >> > # CONFIG_USB_SISUSBVGA is not set >> > # CONFIG_USB_LD is not set >> > # CONFIG_USB_TRANCEVIBRATOR is not set >> > # CONFIG_USB_IOWARRIOR is not set >> > # CONFIG_USB_TEST is not set >> > # CONFIG_USB_EHSET_TEST_FIXTURE is not set >> > # CONFIG_USB_ISIGHTFW is not set >> > # CONFIG_USB_YUREX is not set >> > # CONFIG_USB_EZUSB_FX2 is not set >> > # CONFIG_USB_HUB_USB251XB is not set >> > # CONFIG_USB_HSIC_USB3503 is not set >> > # CONFIG_USB_HSIC_USB4604 is not set >> > # CONFIG_USB_LINK_LAYER_TEST is not set >> > >> > # >> > # USB Physical Layer drivers >> > # >> > # CONFIG_NOP_USB_XCEIV is not set >> > # CONFIG_USB_ISP1301 is not set >> > # end of USB Physical Layer drivers >> > >> > CONFIG_USB_GADGET=m >> > # CONFIG_USB_GADGET_DEBUG is not set >> > # CONFIG_USB_GADGET_DEBUG_FILES is not set >> > # CONFIG_USB_GADGET_DEBUG_FS is not set >> > CONFIG_USB_GADGET_VBUS_DRAW=2 >> > CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 >> > >> > # >> > # USB Peripheral Controller >> > # >> > # CONFIG_USB_FOTG210_UDC is not set >> > # CONFIG_USB_GR_UDC is not set >> > # CONFIG_USB_R8A66597 is not set >> > # CONFIG_USB_PXA27X is not set >> > # CONFIG_USB_MV_UDC is not set >> > # CONFIG_USB_MV_U3D is not set >> > # CONFIG_USB_M66592 is not set >> > # CONFIG_USB_BDC_UDC is not set >> > # CONFIG_USB_AMD5536UDC is not set >> > # CONFIG_USB_NET2272 is not set >> > # CONFIG_USB_NET2280 is not set >> > # CONFIG_USB_GOKU is not set >> > # CONFIG_USB_EG20T is not set >> > # CONFIG_USB_DUMMY_HCD is not set >> > # end of USB Peripheral Controller >> > >> > CONFIG_USB_LIBCOMPOSITE=m >> > CONFIG_USB_F_FS=m >> > CONFIG_USB_CONFIGFS=m >> > # CONFIG_USB_CONFIGFS_SERIAL is not set >> > # CONFIG_USB_CONFIGFS_ACM is not set >> > # CONFIG_USB_CONFIGFS_OBEX is not set >> > # CONFIG_USB_CONFIGFS_NCM is not set >> > # CONFIG_USB_CONFIGFS_ECM is not set >> > # CONFIG_USB_CONFIGFS_ECM_SUBSET is not set >> > # CONFIG_USB_CONFIGFS_RNDIS is not set >> > # CONFIG_USB_CONFIGFS_EEM is not set >> > # CONFIG_USB_CONFIGFS_MASS_STORAGE is not set >> > # CONFIG_USB_CONFIGFS_F_LB_SS is not set >> > CONFIG_USB_CONFIGFS_F_FS=y >> > # CONFIG_USB_CONFIGFS_F_HID is not set >> > # CONFIG_USB_CONFIGFS_F_PRINTER is not set >> > >> > # >> > # USB Gadget precomposed configurations >> > # >> > # CONFIG_USB_ZERO is not set >> > # CONFIG_USB_ETH is not set >> > # CONFIG_USB_G_NCM is not set >> > # CONFIG_USB_GADGETFS is not set >> > # CONFIG_USB_FUNCTIONFS is not set >> > # CONFIG_USB_MASS_STORAGE is not set >> > # CONFIG_USB_G_SERIAL is not set >> > # CONFIG_USB_G_PRINTER is not set >> > # CONFIG_USB_CDC_COMPOSITE is not set >> > # CONFIG_USB_G_ACM_MS is not set >> > # CONFIG_USB_G_MULTI is not set >> > # CONFIG_USB_G_HID is not set >> > # CONFIG_USB_G_DBGP is not set >> > # CONFIG_USB_RAW_GADGET is not set >> > # end of USB Gadget precomposed configurations >> > >> > # CONFIG_TYPEC is not set >> > # CONFIG_USB_ROLE_SWITCH is not set >> > # CONFIG_MMC is not set >> > # CONFIG_MEMSTICK is not set >> > # CONFIG_NEW_LEDS is not set >> > # CONFIG_ACCESSIBILITY is not set >> > # CONFIG_INFINIBAND is not set >> > CONFIG_EDAC_ATOMIC_SCRUB=y >> > CONFIG_EDAC_SUPPORT=y >> > # CONFIG_EDAC is not set >> > CONFIG_RTC_LIB=y >> > CONFIG_RTC_MC146818_LIB=y >> > CONFIG_RTC_CLASS=y >> > CONFIG_RTC_HCTOSYS=y >> > CONFIG_RTC_HCTOSYS_DEVICE="rtc0" >> > CONFIG_RTC_SYSTOHC=y >> > CONFIG_RTC_SYSTOHC_DEVICE="rtc0" >> > # CONFIG_RTC_DEBUG is not set >> > CONFIG_RTC_NVMEM=y >> > >> > # >> > # RTC interfaces >> > # >> > CONFIG_RTC_INTF_SYSFS=y >> > CONFIG_RTC_INTF_PROC=y >> > CONFIG_RTC_INTF_DEV=y >> > # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set >> > # CONFIG_RTC_DRV_TEST is not set >> > >> > # >> > # I2C RTC drivers >> > # >> > # CONFIG_RTC_DRV_ABB5ZES3 is not set >> > # CONFIG_RTC_DRV_ABEOZ9 is not set >> > # CONFIG_RTC_DRV_ABX80X is not set >> > # CONFIG_RTC_DRV_DS1307 is not set >> > # CONFIG_RTC_DRV_DS1374 is not set >> > # CONFIG_RTC_DRV_DS1672 is not set >> > # CONFIG_RTC_DRV_MAX6900 is not set >> > # CONFIG_RTC_DRV_RS5C372 is not set >> > # CONFIG_RTC_DRV_ISL1208 is not set >> > # CONFIG_RTC_DRV_ISL12022 is not set >> > # CONFIG_RTC_DRV_X1205 is not set >> > # CONFIG_RTC_DRV_PCF8523 is not set >> > # CONFIG_RTC_DRV_PCF85063 is not set >> > # CONFIG_RTC_DRV_PCF85363 is not set >> > # CONFIG_RTC_DRV_PCF8563 is not set >> > # CONFIG_RTC_DRV_PCF8583 is not set >> > # CONFIG_RTC_DRV_M41T80 is not set >> > # CONFIG_RTC_DRV_BQ32K is not set >> > # CONFIG_RTC_DRV_S35390A is not set >> > # CONFIG_RTC_DRV_FM3130 is not set >> > # CONFIG_RTC_DRV_RX8010 is not set >> > # CONFIG_RTC_DRV_RX8581 is not set >> > # CONFIG_RTC_DRV_RX8025 is not set >> > # CONFIG_RTC_DRV_EM3027 is not set >> > # CONFIG_RTC_DRV_RV3028 is not set >> > # CONFIG_RTC_DRV_RV8803 is not set >> > # CONFIG_RTC_DRV_SD3078 is not set >> > >> > # >> > # SPI RTC drivers >> > # >> > CONFIG_RTC_I2C_AND_SPI=y >> > >> > # >> > # SPI and I2C RTC drivers >> > # >> > # CONFIG_RTC_DRV_DS3232 is not set >> > # CONFIG_RTC_DRV_PCF2127 is not set >> > # CONFIG_RTC_DRV_RV3029C2 is not set >> > >> > # >> > # Platform RTC drivers >> > # >> > CONFIG_RTC_DRV_CMOS=y >> > # CONFIG_RTC_DRV_DS1286 is not set >> > # CONFIG_RTC_DRV_DS1511 is not set >> > # CONFIG_RTC_DRV_DS1553 is not set >> > # CONFIG_RTC_DRV_DS1685_FAMILY is not set >> > # CONFIG_RTC_DRV_DS1742 is not set >> > # CONFIG_RTC_DRV_DS2404 is not set >> > # CONFIG_RTC_DRV_STK17TA8 is not set >> > # CONFIG_RTC_DRV_M48T86 is not set >> > # CONFIG_RTC_DRV_M48T35 is not set >> > # CONFIG_RTC_DRV_M48T59 is not set >> > # CONFIG_RTC_DRV_MSM6242 is not set >> > # CONFIG_RTC_DRV_BQ4802 is not set >> > # CONFIG_RTC_DRV_RP5C01 is not set >> > # CONFIG_RTC_DRV_V3020 is not set >> > >> > # >> > # on-CPU RTC drivers >> > # >> > # CONFIG_RTC_DRV_FTRTC010 is not set >> > >> > # >> > # HID Sensor RTC drivers >> > # >> > # CONFIG_DMADEVICES is not set >> > >> > # >> > # DMABUF options >> > # >> > CONFIG_SYNC_FILE=y >> > # CONFIG_SW_SYNC is not set >> > # CONFIG_UDMABUF is not set >> > # CONFIG_DMABUF_MOVE_NOTIFY is not set >> > # CONFIG_DMABUF_SELFTESTS is not set >> > # CONFIG_DMABUF_HEAPS is not set >> > # end of DMABUF options >> > >> > # CONFIG_AUXDISPLAY is not set >> > # CONFIG_UIO is not set >> > # CONFIG_VFIO is not set >> > # CONFIG_VIRT_DRIVERS is not set >> > # CONFIG_VIRTIO_MENU is not set >> > # CONFIG_VDPA_MENU is not set >> > CONFIG_VHOST_MENU=y >> > # CONFIG_VHOST_NET is not set >> > # CONFIG_VHOST_VDPA is not set >> > # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set >> > >> > # >> > # Microsoft Hyper-V guest support >> > # >> > # end of Microsoft Hyper-V guest support >> > >> > # CONFIG_GREYBUS is not set >> > # CONFIG_STAGING is not set >> > CONFIG_X86_PLATFORM_DEVICES=y >> > CONFIG_ACPI_WMI=y >> > CONFIG_WMI_BMOF=y >> > # CONFIG_INTEL_WMI_THUNDERBOLT is not set >> > CONFIG_MXM_WMI=y >> > # CONFIG_PEAQ_WMI is not set >> > # CONFIG_XIAOMI_WMI is not set >> > # CONFIG_ACERHDF is not set >> > # CONFIG_ACER_WIRELESS is not set >> > # CONFIG_ACER_WMI is not set >> > # CONFIG_APPLE_GMUX is not set >> > # CONFIG_ASUS_LAPTOP is not set >> > # CONFIG_ASUS_WIRELESS is not set >> > # CONFIG_DCDBAS is not set >> > # CONFIG_DELL_SMBIOS is not set >> > # CONFIG_DELL_RBU is not set >> > # CONFIG_DELL_SMO8800 is not set >> > # CONFIG_DELL_WMI_AIO is not set >> > # CONFIG_FUJITSU_LAPTOP is not set >> > # CONFIG_FUJITSU_TABLET is not set >> > # CONFIG_GPD_POCKET_FAN is not set >> > # CONFIG_HP_ACCEL is not set >> > # CONFIG_HP_WIRELESS is not set >> > # CONFIG_HP_WMI is not set >> > # CONFIG_IBM_RTL is not set >> > # CONFIG_SENSORS_HDAPS is not set >> > # CONFIG_INTEL_ATOMISP2_PM is not set >> > # CONFIG_INTEL_HID_EVENT is not set >> > # CONFIG_INTEL_MENLOW is not set >> > # CONFIG_INTEL_VBTN is not set >> > # CONFIG_SURFACE_3_POWER_OPREGION is not set >> > # CONFIG_SURFACE_PRO3_BUTTON is not set >> > # CONFIG_MSI_WMI is not set >> > # CONFIG_SAMSUNG_LAPTOP is not set >> > # CONFIG_SAMSUNG_Q10 is not set >> > # CONFIG_TOSHIBA_BT_RFKILL is not set >> > # CONFIG_TOSHIBA_HAPS is not set >> > # CONFIG_TOSHIBA_WMI is not set >> > # CONFIG_ACPI_CMPC is not set >> > # CONFIG_LG_LAPTOP is not set >> > # CONFIG_PANASONIC_LAPTOP is not set >> > # CONFIG_SYSTEM76_ACPI is not set >> > # CONFIG_TOPSTAR_LAPTOP is not set >> > # CONFIG_I2C_MULTI_INSTANTIATE is not set >> > # CONFIG_INTEL_IPS is not set >> > # CONFIG_INTEL_RST is not set >> > # CONFIG_INTEL_SMARTCONNECT is not set >> > >> > # >> > # Intel Speed Select Technology interface support >> > # >> > CONFIG_INTEL_SPEED_SELECT_INTERFACE=y >> > # end of Intel Speed Select Technology interface support >> > >> > # CONFIG_INTEL_TURBO_MAX_3 is not set >> > # CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set >> > # CONFIG_INTEL_PMC_CORE is not set >> > # CONFIG_INTEL_PMC_IPC is not set >> > # CONFIG_INTEL_PUNIT_IPC is not set >> > CONFIG_PMC_ATOM=y >> > # CONFIG_MFD_CROS_EC is not set >> > # CONFIG_CHROME_PLATFORMS is not set >> > # CONFIG_MELLANOX_PLATFORM is not set >> > CONFIG_CLKDEV_LOOKUP=y >> > CONFIG_HAVE_CLK_PREPARE=y >> > CONFIG_COMMON_CLK=y >> > >> > # >> > # Common Clock Framework >> > # >> > # CONFIG_COMMON_CLK_MAX9485 is not set >> > # CONFIG_COMMON_CLK_SI5341 is not set >> > # CONFIG_COMMON_CLK_SI5351 is not set >> > # CONFIG_COMMON_CLK_SI544 is not set >> > # CONFIG_COMMON_CLK_CDCE706 is not set >> > # CONFIG_COMMON_CLK_CS2000_CP is not set >> > # end of Common Clock Framework >> > >> > # CONFIG_HWSPINLOCK is not set >> > >> > # >> > # Clock Source drivers >> > # >> > CONFIG_CLKEVT_I8253=y >> > CONFIG_I8253_LOCK=y >> > CONFIG_CLKBLD_I8253=y >> > # end of Clock Source drivers >> > >> > CONFIG_MAILBOX=y >> > CONFIG_PCC=y >> > # CONFIG_ALTERA_MBOX is not set >> > CONFIG_IOMMU_IOVA=y >> > CONFIG_IOASID=y >> > CONFIG_IOMMU_API=y >> > CONFIG_IOMMU_SUPPORT=y >> > >> > # >> > # Generic IOMMU Pagetable Support >> > # >> > # end of Generic IOMMU Pagetable Support >> > >> > # CONFIG_IOMMU_DEBUGFS is not set >> > # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set >> > # CONFIG_AMD_IOMMU is not set >> > CONFIG_DMAR_TABLE=y >> > CONFIG_INTEL_IOMMU=y >> > CONFIG_INTEL_IOMMU_SVM=y >> > CONFIG_INTEL_IOMMU_DEFAULT_ON=y >> > CONFIG_INTEL_IOMMU_FLOPPY_WA=y >> > # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set >> > # CONFIG_IRQ_REMAP is not set >> > >> > # >> > # Remoteproc drivers >> > # >> > # CONFIG_REMOTEPROC is not set >> > # end of Remoteproc drivers >> > >> > # >> > # Rpmsg drivers >> > # >> > # CONFIG_RPMSG_QCOM_GLINK_RPM is not set >> > # CONFIG_RPMSG_VIRTIO is not set >> > # end of Rpmsg drivers >> > >> > # CONFIG_SOUNDWIRE is not set >> > >> > # >> > # SOC (System On Chip) specific Drivers >> > # >> > >> > # >> > # Amlogic SoC drivers >> > # >> > # end of Amlogic SoC drivers >> > >> > # >> > # Aspeed SoC drivers >> > # >> > # end of Aspeed SoC drivers >> > >> > # >> > # Broadcom SoC drivers >> > # >> > # end of Broadcom SoC drivers >> > >> > # >> > # NXP/Freescale QorIQ SoC drivers >> > # >> > # end of NXP/Freescale QorIQ SoC drivers >> > >> > # >> > # i.MX SoC drivers >> > # >> > # end of i.MX SoC drivers >> > >> > # >> > # Qualcomm SoC drivers >> > # >> > # end of Qualcomm SoC drivers >> > >> > # CONFIG_SOC_TI is not set >> > >> > # >> > # Xilinx SoC drivers >> > # >> > # CONFIG_XILINX_VCU is not set >> > # end of Xilinx SoC drivers >> > # end of SOC (System On Chip) specific Drivers >> > >> > # CONFIG_PM_DEVFREQ is not set >> > # CONFIG_EXTCON is not set >> > # CONFIG_MEMORY is not set >> > # CONFIG_IIO is not set >> > # CONFIG_NTB is not set >> > # CONFIG_VME_BUS is not set >> > # CONFIG_PWM is not set >> > >> > # >> > # IRQ chip support >> > # >> > # end of IRQ chip support >> > >> > # CONFIG_IPACK_BUS is not set >> > # CONFIG_RESET_CONTROLLER is not set >> > >> > # >> > # PHY Subsystem >> > # >> > # CONFIG_GENERIC_PHY is not set >> > # CONFIG_BCM_KONA_USB2_PHY is not set >> > # CONFIG_PHY_PXA_28NM_HSIC is not set >> > # CONFIG_PHY_PXA_28NM_USB2 is not set >> > # CONFIG_PHY_INTEL_EMMC is not set >> > # end of PHY Subsystem >> > >> > # CONFIG_POWERCAP is not set >> > # CONFIG_MCB is not set >> > >> > # >> > # Performance monitor support >> > # >> > # end of Performance monitor support >> > >> > CONFIG_RAS=y >> > # CONFIG_USB4 is not set >> > >> > # >> > # Android >> > # >> > # CONFIG_ANDROID is not set >> > # end of Android >> > >> > # CONFIG_LIBNVDIMM is not set >> > # CONFIG_DAX is not set >> > CONFIG_NVMEM=y >> > # CONFIG_NVMEM_SYSFS is not set >> > >> > # >> > # HW tracing support >> > # >> > # CONFIG_STM is not set >> > # CONFIG_INTEL_TH is not set >> > # end of HW tracing support >> > >> > # CONFIG_FPGA is not set >> > # CONFIG_TEE is not set >> > # CONFIG_UNISYS_VISORBUS is not set >> > # CONFIG_SIOX is not set >> > # CONFIG_SLIMBUS is not set >> > # CONFIG_INTERCONNECT is not set >> > # CONFIG_COUNTER is not set >> > # CONFIG_MOST is not set >> > # end of Device Drivers >> > >> > # >> > # File systems >> > # >> > CONFIG_DCACHE_WORD_ACCESS=y >> > CONFIG_VALIDATE_FS_PARSER=y >> > CONFIG_FS_IOMAP=y >> > # CONFIG_EXT2_FS is not set >> > # CONFIG_EXT3_FS is not set >> > CONFIG_EXT4_FS=y >> > CONFIG_EXT4_USE_FOR_EXT2=y >> > CONFIG_EXT4_FS_POSIX_ACL=y >> > CONFIG_EXT4_FS_SECURITY=y >> > # CONFIG_EXT4_DEBUG is not set >> > CONFIG_JBD2=y >> > # CONFIG_JBD2_DEBUG is not set >> > CONFIG_FS_MBCACHE=y >> > # CONFIG_REISERFS_FS is not set >> > # CONFIG_JFS_FS is not set >> > CONFIG_XFS_FS=y >> > CONFIG_XFS_QUOTA=y >> > CONFIG_XFS_POSIX_ACL=y >> > # CONFIG_XFS_RT is not set >> > # CONFIG_XFS_ONLINE_SCRUB is not set >> > # CONFIG_XFS_WARN is not set >> > # CONFIG_XFS_DEBUG is not set >> > # CONFIG_GFS2_FS is not set >> > # CONFIG_OCFS2_FS is not set >> > CONFIG_BTRFS_FS=y >> > CONFIG_BTRFS_FS_POSIX_ACL=y >> > CONFIG_BTRFS_FS_CHECK_INTEGRITY=y >> > # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set >> > CONFIG_BTRFS_DEBUG=y >> > # CONFIG_BTRFS_ASSERT is not set >> > CONFIG_BTRFS_FS_REF_VERIFY=y >> > CONFIG_NILFS2_FS=m >> > CONFIG_F2FS_FS=m >> > CONFIG_F2FS_STAT_FS=y >> > CONFIG_F2FS_FS_XATTR=y >> > CONFIG_F2FS_FS_POSIX_ACL=y >> > CONFIG_F2FS_FS_SECURITY=y >> > # CONFIG_F2FS_CHECK_FS is not set >> > # CONFIG_F2FS_IO_TRACE is not set >> > # CONFIG_F2FS_FAULT_INJECTION is not set >> > # CONFIG_F2FS_FS_COMPRESSION is not set >> > # CONFIG_FS_DAX is not set >> > CONFIG_FS_POSIX_ACL=y >> > CONFIG_EXPORTFS=y >> > CONFIG_EXPORTFS_BLOCK_OPS=y >> > CONFIG_FILE_LOCKING=y >> > CONFIG_MANDATORY_FILE_LOCKING=y >> > # CONFIG_FS_ENCRYPTION is not set >> > # CONFIG_FS_VERITY is not set >> > CONFIG_FSNOTIFY=y >> > CONFIG_DNOTIFY=y >> > CONFIG_INOTIFY_USER=y >> > CONFIG_FANOTIFY=y >> > CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y >> > # CONFIG_QUOTA is not set >> > # CONFIG_QUOTA_NETLINK_INTERFACE is not set >> > CONFIG_QUOTACTL=y >> > CONFIG_QUOTACTL_COMPAT=y >> > CONFIG_AUTOFS4_FS=y >> > CONFIG_AUTOFS_FS=y >> > CONFIG_FUSE_FS=m >> > # CONFIG_CUSE is not set >> > # CONFIG_VIRTIO_FS is not set >> > # CONFIG_OVERLAY_FS is not set >> > >> > # >> > # Caches >> > # >> > CONFIG_FSCACHE=y >> > CONFIG_FSCACHE_STATS=y >> > # CONFIG_FSCACHE_HISTOGRAM is not set >> > # CONFIG_FSCACHE_DEBUG is not set >> > CONFIG_FSCACHE_OBJECT_LIST=y >> > CONFIG_CACHEFILES=y >> > # CONFIG_CACHEFILES_DEBUG is not set >> > # CONFIG_CACHEFILES_HISTOGRAM is not set >> > # end of Caches >> > >> > # >> > # CD-ROM/DVD Filesystems >> > # >> > # CONFIG_ISO9660_FS is not set >> > # CONFIG_UDF_FS is not set >> > # end of CD-ROM/DVD Filesystems >> > >> > # >> > # DOS/FAT/EXFAT/NT Filesystems >> > # >> > # CONFIG_MSDOS_FS is not set >> > # CONFIG_VFAT_FS is not set >> > # CONFIG_EXFAT_FS is not set >> > # CONFIG_NTFS_FS is not set >> > # end of DOS/FAT/EXFAT/NT Filesystems >> > >> > # >> > # Pseudo filesystems >> > # >> > CONFIG_PROC_FS=y >> > CONFIG_PROC_KCORE=y >> > CONFIG_PROC_SYSCTL=y >> > CONFIG_PROC_PAGE_MONITOR=y >> > # CONFIG_PROC_CHILDREN is not set >> > CONFIG_PROC_PID_ARCH_STATUS=y >> > CONFIG_PROC_CPU_RESCTRL=y >> > CONFIG_KERNFS=y >> > CONFIG_SYSFS=y >> > CONFIG_TMPFS=y >> > CONFIG_TMPFS_POSIX_ACL=y >> > CONFIG_TMPFS_XATTR=y >> > CONFIG_HUGETLBFS=y >> > CONFIG_HUGETLB_PAGE=y >> > CONFIG_MEMFD_CREATE=y >> > CONFIG_ARCH_HAS_GIGANTIC_PAGE=y >> > CONFIG_CONFIGFS_FS=y >> > CONFIG_EFIVAR_FS=y >> > # end of Pseudo filesystems >> > >> > CONFIG_MISC_FILESYSTEMS=y >> > # CONFIG_ORANGEFS_FS is not set >> > # CONFIG_ADFS_FS is not set >> > # CONFIG_AFFS_FS is not set >> > # CONFIG_ECRYPT_FS is not set >> > # CONFIG_HFS_FS is not set >> > # CONFIG_HFSPLUS_FS is not set >> > # CONFIG_BEFS_FS is not set >> > # CONFIG_BFS_FS is not set >> > # CONFIG_EFS_FS is not set >> > # CONFIG_CRAMFS is not set >> > # CONFIG_SQUASHFS is not set >> > # CONFIG_VXFS_FS is not set >> > # CONFIG_MINIX_FS is not set >> > # CONFIG_OMFS_FS is not set >> > # CONFIG_HPFS_FS is not set >> > # CONFIG_QNX4FS_FS is not set >> > # CONFIG_QNX6FS_FS is not set >> > # CONFIG_ROMFS_FS is not set >> > CONFIG_PSTORE=y >> > CONFIG_PSTORE_DEFLATE_COMPRESS=y >> > # CONFIG_PSTORE_LZO_COMPRESS is not set >> > # CONFIG_PSTORE_LZ4_COMPRESS is not set >> > # CONFIG_PSTORE_LZ4HC_COMPRESS is not set >> > # CONFIG_PSTORE_842_COMPRESS is not set >> > # CONFIG_PSTORE_ZSTD_COMPRESS is not set >> > CONFIG_PSTORE_COMPRESS=y >> > CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y >> > CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" >> > # CONFIG_PSTORE_CONSOLE is not set >> > # CONFIG_PSTORE_PMSG is not set >> > # CONFIG_PSTORE_FTRACE is not set >> > # CONFIG_PSTORE_RAM is not set >> > # CONFIG_SYSV_FS is not set >> > # CONFIG_UFS_FS is not set >> > # CONFIG_EROFS_FS is not set >> > CONFIG_NETWORK_FILESYSTEMS=y >> > CONFIG_NFS_FS=y >> > # CONFIG_NFS_V2 is not set >> > # CONFIG_NFS_V3 is not set >> > CONFIG_NFS_V4=y >> > # CONFIG_NFS_SWAP is not set >> > # CONFIG_NFS_V4_1 is not set >> > # CONFIG_NFS_FSCACHE is not set >> > # CONFIG_NFS_USE_LEGACY_DNS is not set >> > CONFIG_NFS_USE_KERNEL_DNS=y >> > CONFIG_NFS_DEBUG=y >> > CONFIG_NFS_DISABLE_UDP_SUPPORT=y >> > # CONFIG_NFSD is not set >> > CONFIG_GRACE_PERIOD=y >> > CONFIG_LOCKD=y >> > CONFIG_NFS_COMMON=y >> > CONFIG_SUNRPC=y >> > CONFIG_SUNRPC_GSS=y >> > CONFIG_SUNRPC_DEBUG=y >> > # CONFIG_CEPH_FS is not set >> > # CONFIG_CIFS is not set >> > # CONFIG_CODA_FS is not set >> > CONFIG_AFS_FS=y >> > CONFIG_AFS_DEBUG=y >> > CONFIG_AFS_FSCACHE=y >> > CONFIG_AFS_DEBUG_CURSOR=y >> > CONFIG_NLS=y >> > CONFIG_NLS_DEFAULT="iso8859-1" >> > # CONFIG_NLS_CODEPAGE_437 is not set >> > # CONFIG_NLS_CODEPAGE_737 is not set >> > # CONFIG_NLS_CODEPAGE_775 is not set >> > # CONFIG_NLS_CODEPAGE_850 is not set >> > # CONFIG_NLS_CODEPAGE_852 is not set >> > # CONFIG_NLS_CODEPAGE_855 is not set >> > # CONFIG_NLS_CODEPAGE_857 is not set >> > # CONFIG_NLS_CODEPAGE_860 is not set >> > # CONFIG_NLS_CODEPAGE_861 is not set >> > # CONFIG_NLS_CODEPAGE_862 is not set >> > # CONFIG_NLS_CODEPAGE_863 is not set >> > # CONFIG_NLS_CODEPAGE_864 is not set >> > # CONFIG_NLS_CODEPAGE_865 is not set >> > # CONFIG_NLS_CODEPAGE_866 is not set >> > # CONFIG_NLS_CODEPAGE_869 is not set >> > # CONFIG_NLS_CODEPAGE_936 is not set >> > # CONFIG_NLS_CODEPAGE_950 is not set >> > # CONFIG_NLS_CODEPAGE_932 is not set >> > # CONFIG_NLS_CODEPAGE_949 is not set >> > # CONFIG_NLS_CODEPAGE_874 is not set >> > # CONFIG_NLS_ISO8859_8 is not set >> > # CONFIG_NLS_CODEPAGE_1250 is not set >> > # CONFIG_NLS_CODEPAGE_1251 is not set >> > # CONFIG_NLS_ASCII is not set >> > # CONFIG_NLS_ISO8859_1 is not set >> > # CONFIG_NLS_ISO8859_2 is not set >> > # CONFIG_NLS_ISO8859_3 is not set >> > # CONFIG_NLS_ISO8859_4 is not set >> > # CONFIG_NLS_ISO8859_5 is not set >> > # CONFIG_NLS_ISO8859_6 is not set >> > # CONFIG_NLS_ISO8859_7 is not set >> > # CONFIG_NLS_ISO8859_9 is not set >> > # CONFIG_NLS_ISO8859_13 is not set >> > # CONFIG_NLS_ISO8859_14 is not set >> > # CONFIG_NLS_ISO8859_15 is not set >> > # CONFIG_NLS_KOI8_R is not set >> > # CONFIG_NLS_KOI8_U is not set >> > # CONFIG_NLS_MAC_ROMAN is not set >> > # CONFIG_NLS_MAC_CELTIC is not set >> > # CONFIG_NLS_MAC_CENTEURO is not set >> > # CONFIG_NLS_MAC_CROATIAN is not set >> > # CONFIG_NLS_MAC_CYRILLIC is not set >> > # CONFIG_NLS_MAC_GAELIC is not set >> > # CONFIG_NLS_MAC_GREEK is not set >> > # CONFIG_NLS_MAC_ICELAND is not set >> > # CONFIG_NLS_MAC_INUIT is not set >> > # CONFIG_NLS_MAC_ROMANIAN is not set >> > # CONFIG_NLS_MAC_TURKISH is not set >> > # CONFIG_NLS_UTF8 is not set >> > CONFIG_DLM=y >> > # CONFIG_DLM_DEBUG is not set >> > # CONFIG_UNICODE is not set >> > # end of File systems >> > >> > # >> > # Security options >> > # >> > CONFIG_KEYS=y >> > CONFIG_KEYS_REQUEST_CACHE=y >> > CONFIG_PERSISTENT_KEYRINGS=y >> > CONFIG_BIG_KEYS=y >> > CONFIG_TRUSTED_KEYS=y >> > CONFIG_ENCRYPTED_KEYS=y >> > CONFIG_KEY_DH_OPERATIONS=y >> > # CONFIG_SECURITY_DMESG_RESTRICT is not set >> > CONFIG_SECURITY=y >> > CONFIG_SECURITY_WRITABLE_HOOKS=y >> > CONFIG_SECURITYFS=y >> > CONFIG_SECURITY_NETWORK=y >> > CONFIG_PAGE_TABLE_ISOLATION=y >> > CONFIG_SECURITY_NETWORK_XFRM=y >> > CONFIG_SECURITY_PATH=y >> > # CONFIG_INTEL_TXT is not set >> > CONFIG_LSM_MMAP_MIN_ADDR=65536 >> > CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y >> > # CONFIG_HARDENED_USERCOPY is not set >> > # CONFIG_FORTIFY_SOURCE is not set >> > # CONFIG_STATIC_USERMODEHELPER is not set >> > CONFIG_SECURITY_SELINUX=y >> > CONFIG_SECURITY_SELINUX_BOOTPARAM=y >> > CONFIG_SECURITY_SELINUX_DISABLE=y >> > CONFIG_SECURITY_SELINUX_DEVELOP=y >> > CONFIG_SECURITY_SELINUX_AVC_STATS=y >> > CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 >> > CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 >> > CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 >> > # CONFIG_SECURITY_SMACK is not set >> > # CONFIG_SECURITY_TOMOYO is not set >> > # CONFIG_SECURITY_APPARMOR is not set >> > # CONFIG_SECURITY_LOADPIN is not set >> > CONFIG_SECURITY_YAMA=y >> > # CONFIG_SECURITY_SAFESETID is not set >> > # CONFIG_SECURITY_LOCKDOWN_LSM is not set >> > # CONFIG_INTEGRITY is not set >> > # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set >> > CONFIG_DEFAULT_SECURITY_SELINUX=y >> > # CONFIG_DEFAULT_SECURITY_DAC is not set >> > CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" >> > >> > # >> > # Kernel hardening options >> > # >> > >> > # >> > # Memory initialization >> > # >> > CONFIG_INIT_STACK_NONE=y >> > # CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set >> > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set >> > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set >> > # CONFIG_GCC_PLUGIN_STACKLEAK is not set >> > # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set >> > # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set >> > # end of Memory initialization >> > # end of Kernel hardening options >> > # end of Security options >> > >> > CONFIG_XOR_BLOCKS=y >> > CONFIG_CRYPTO=y >> > >> > # >> > # Crypto core or helper >> > # >> > # CONFIG_CRYPTO_FIPS is not set >> > CONFIG_CRYPTO_ALGAPI=y >> > CONFIG_CRYPTO_ALGAPI2=y >> > CONFIG_CRYPTO_AEAD=y >> > CONFIG_CRYPTO_AEAD2=y >> > CONFIG_CRYPTO_SKCIPHER=y >> > CONFIG_CRYPTO_SKCIPHER2=y >> > CONFIG_CRYPTO_HASH=y >> > CONFIG_CRYPTO_HASH2=y >> > CONFIG_CRYPTO_RNG=y >> > CONFIG_CRYPTO_RNG2=y >> > CONFIG_CRYPTO_RNG_DEFAULT=y >> > CONFIG_CRYPTO_AKCIPHER2=y >> > CONFIG_CRYPTO_AKCIPHER=y >> > CONFIG_CRYPTO_KPP2=y >> > CONFIG_CRYPTO_KPP=y >> > CONFIG_CRYPTO_ACOMP2=y >> > CONFIG_CRYPTO_MANAGER=y >> > CONFIG_CRYPTO_MANAGER2=y >> > # CONFIG_CRYPTO_USER is not set >> > # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set >> > # CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set >> > CONFIG_CRYPTO_GF128MUL=y >> > CONFIG_CRYPTO_NULL=y >> > CONFIG_CRYPTO_NULL2=y >> > # CONFIG_CRYPTO_PCRYPT is not set >> > # CONFIG_CRYPTO_CRYPTD is not set >> > CONFIG_CRYPTO_AUTHENC=y >> > # CONFIG_CRYPTO_TEST is not set >> > >> > # >> > # Public-key cryptography >> > # >> > CONFIG_CRYPTO_RSA=y >> > CONFIG_CRYPTO_DH=y >> > # CONFIG_CRYPTO_ECDH is not set >> > # CONFIG_CRYPTO_ECRDSA is not set >> > # CONFIG_CRYPTO_CURVE25519 is not set >> > # CONFIG_CRYPTO_CURVE25519_X86 is not set >> > >> > # >> > # Authenticated Encryption with Associated Data >> > # >> > CONFIG_CRYPTO_CCM=m >> > CONFIG_CRYPTO_GCM=y >> > # CONFIG_CRYPTO_CHACHA20POLY1305 is not set >> > # CONFIG_CRYPTO_AEGIS128 is not set >> > # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set >> > CONFIG_CRYPTO_SEQIV=y >> > CONFIG_CRYPTO_ECHAINIV=y >> > >> > # >> > # Block modes >> > # >> > CONFIG_CRYPTO_CBC=y >> > # CONFIG_CRYPTO_CFB is not set >> > CONFIG_CRYPTO_CTR=y >> > # CONFIG_CRYPTO_CTS is not set >> > CONFIG_CRYPTO_ECB=y >> > # CONFIG_CRYPTO_LRW is not set >> > # CONFIG_CRYPTO_OFB is not set >> > CONFIG_CRYPTO_PCBC=y >> > # CONFIG_CRYPTO_XTS is not set >> > # CONFIG_CRYPTO_KEYWRAP is not set >> > # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set >> > # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set >> > # CONFIG_CRYPTO_ADIANTUM is not set >> > # CONFIG_CRYPTO_ESSIV is not set >> > >> > # >> > # Hash modes >> > # >> > CONFIG_CRYPTO_CMAC=m >> > CONFIG_CRYPTO_HMAC=y >> > # CONFIG_CRYPTO_XCBC is not set >> > # CONFIG_CRYPTO_VMAC is not set >> > >> > # >> > # Digest >> > # >> > CONFIG_CRYPTO_CRC32C=y >> > # CONFIG_CRYPTO_CRC32C_INTEL is not set >> > CONFIG_CRYPTO_CRC32=m >> > # CONFIG_CRYPTO_CRC32_PCLMUL is not set >> > CONFIG_CRYPTO_XXHASH=y >> > CONFIG_CRYPTO_BLAKE2B=y >> > # CONFIG_CRYPTO_BLAKE2S is not set >> > # CONFIG_CRYPTO_BLAKE2S_X86 is not set >> > CONFIG_CRYPTO_CRCT10DIF=y >> > # CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set >> > CONFIG_CRYPTO_GHASH=y >> > # CONFIG_CRYPTO_POLY1305 is not set >> > # CONFIG_CRYPTO_POLY1305_X86_64 is not set >> > CONFIG_CRYPTO_MD4=m >> > CONFIG_CRYPTO_MD5=y >> > # CONFIG_CRYPTO_MICHAEL_MIC is not set >> > # CONFIG_CRYPTO_RMD128 is not set >> > # CONFIG_CRYPTO_RMD160 is not set >> > # CONFIG_CRYPTO_RMD256 is not set >> > # CONFIG_CRYPTO_RMD320 is not set >> > CONFIG_CRYPTO_SHA1=y >> > # CONFIG_CRYPTO_SHA1_SSSE3 is not set >> > # CONFIG_CRYPTO_SHA256_SSSE3 is not set >> > # CONFIG_CRYPTO_SHA512_SSSE3 is not set >> > CONFIG_CRYPTO_SHA256=y >> > CONFIG_CRYPTO_SHA512=m >> > # CONFIG_CRYPTO_SHA3 is not set >> > # CONFIG_CRYPTO_SM3 is not set >> > # CONFIG_CRYPTO_STREEBOG is not set >> > # CONFIG_CRYPTO_TGR192 is not set >> > # CONFIG_CRYPTO_WP512 is not set >> > # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set >> > >> > # >> > # Ciphers >> > # >> > CONFIG_CRYPTO_AES=y >> > # CONFIG_CRYPTO_AES_TI is not set >> > # CONFIG_CRYPTO_AES_NI_INTEL is not set >> > # CONFIG_CRYPTO_ANUBIS is not set >> > CONFIG_CRYPTO_ARC4=m >> > # CONFIG_CRYPTO_BLOWFISH is not set >> > # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set >> > # CONFIG_CRYPTO_CAMELLIA is not set >> > # CONFIG_CRYPTO_CAMELLIA_X86_64 is not set >> > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set >> > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set >> > # CONFIG_CRYPTO_CAST5 is not set >> > # CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set >> > # CONFIG_CRYPTO_CAST6 is not set >> > # CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set >> > CONFIG_CRYPTO_DES=y >> > # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set >> > CONFIG_CRYPTO_FCRYPT=y >> > # CONFIG_CRYPTO_KHAZAD is not set >> > # CONFIG_CRYPTO_SALSA20 is not set >> > # CONFIG_CRYPTO_CHACHA20 is not set >> > # CONFIG_CRYPTO_CHACHA20_X86_64 is not set >> > # CONFIG_CRYPTO_SEED is not set >> > # CONFIG_CRYPTO_SERPENT is not set >> > # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set >> > # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set >> > # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set >> > # CONFIG_CRYPTO_SM4 is not set >> > # CONFIG_CRYPTO_TEA is not set >> > # CONFIG_CRYPTO_TWOFISH is not set >> > # CONFIG_CRYPTO_TWOFISH_X86_64 is not set >> > # CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set >> > # CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set >> > >> > # >> > # Compression >> > # >> > CONFIG_CRYPTO_DEFLATE=y >> > CONFIG_CRYPTO_LZO=m >> > # CONFIG_CRYPTO_842 is not set >> > # CONFIG_CRYPTO_LZ4 is not set >> > # CONFIG_CRYPTO_LZ4HC is not set >> > # CONFIG_CRYPTO_ZSTD is not set >> > >> > # >> > # Random Number Generation >> > # >> > # CONFIG_CRYPTO_ANSI_CPRNG is not set >> > CONFIG_CRYPTO_DRBG_MENU=y >> > CONFIG_CRYPTO_DRBG_HMAC=y >> > # CONFIG_CRYPTO_DRBG_HASH is not set >> > # CONFIG_CRYPTO_DRBG_CTR is not set >> > CONFIG_CRYPTO_DRBG=y >> > CONFIG_CRYPTO_JITTERENTROPY=y >> > CONFIG_CRYPTO_USER_API=y >> > CONFIG_CRYPTO_USER_API_HASH=y >> > # CONFIG_CRYPTO_USER_API_SKCIPHER is not set >> > # CONFIG_CRYPTO_USER_API_RNG is not set >> > # CONFIG_CRYPTO_USER_API_AEAD is not set >> > CONFIG_CRYPTO_HASH_INFO=y >> > >> > # >> > # Crypto library routines >> > # >> > CONFIG_CRYPTO_LIB_AES=y >> > CONFIG_CRYPTO_LIB_ARC4=m >> > # CONFIG_CRYPTO_LIB_BLAKE2S is not set >> > CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y >> > CONFIG_CRYPTO_LIB_CHACHA=y >> > # CONFIG_CRYPTO_LIB_CURVE25519 is not set >> > CONFIG_CRYPTO_LIB_DES=y >> > CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 >> > CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y >> > CONFIG_CRYPTO_LIB_POLY1305=y >> > CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y >> > CONFIG_CRYPTO_LIB_SHA256=y >> > # CONFIG_CRYPTO_HW is not set >> > CONFIG_ASYMMETRIC_KEY_TYPE=y >> > CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y >> > # CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set >> > CONFIG_X509_CERTIFICATE_PARSER=y >> > # CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set >> > CONFIG_PKCS7_MESSAGE_PARSER=y >> > CONFIG_PKCS7_TEST_KEY=y >> > CONFIG_SIGNED_PE_FILE_VERIFICATION=y >> > >> > # >> > # Certificates for signature checking >> > # >> > CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" >> > CONFIG_SYSTEM_TRUSTED_KEYRING=y >> > CONFIG_SYSTEM_TRUSTED_KEYS="" >> > CONFIG_SYSTEM_EXTRA_CERTIFICATE=y >> > CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 >> > CONFIG_SECONDARY_TRUSTED_KEYRING=y >> > CONFIG_SYSTEM_BLACKLIST_KEYRING=y >> > CONFIG_SYSTEM_BLACKLIST_HASH_LIST="/data/modsign/blacklist" >> > # end of Certificates for signature checking >> > >> > CONFIG_BINARY_PRINTF=y >> > >> > # >> > # Library routines >> > # >> > CONFIG_RAID6_PQ=y >> > CONFIG_RAID6_PQ_BENCHMARK=y >> > # CONFIG_PACKING is not set >> > CONFIG_BITREVERSE=y >> > CONFIG_GENERIC_STRNCPY_FROM_USER=y >> > CONFIG_GENERIC_STRNLEN_USER=y >> > CONFIG_GENERIC_NET_UTILS=y >> > CONFIG_GENERIC_FIND_FIRST_BIT=y >> > # CONFIG_CORDIC is not set >> > CONFIG_RATIONAL=y >> > CONFIG_GENERIC_PCI_IOMAP=y >> > CONFIG_GENERIC_IOMAP=y >> > CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y >> > CONFIG_ARCH_HAS_FAST_MULTIPLIER=y >> > CONFIG_CRC_CCITT=y >> > CONFIG_CRC16=y >> > CONFIG_CRC_T10DIF=y >> > CONFIG_CRC_ITU_T=y >> > CONFIG_CRC32=y >> > # CONFIG_CRC32_SELFTEST is not set >> > CONFIG_CRC32_SLICEBY8=y >> > # CONFIG_CRC32_SLICEBY4 is not set >> > # CONFIG_CRC32_SARWATE is not set >> > # CONFIG_CRC32_BIT is not set >> > # CONFIG_CRC64 is not set >> > # CONFIG_CRC4 is not set >> > # CONFIG_CRC7 is not set >> > CONFIG_LIBCRC32C=y >> > # CONFIG_CRC8 is not set >> > CONFIG_XXHASH=y >> > # CONFIG_RANDOM32_SELFTEST is not set >> > CONFIG_ZLIB_INFLATE=y >> > CONFIG_ZLIB_DEFLATE=y >> > CONFIG_LZO_COMPRESS=y >> > CONFIG_LZO_DECOMPRESS=y >> > CONFIG_ZSTD_COMPRESS=y >> > CONFIG_ZSTD_DECOMPRESS=y >> > CONFIG_XZ_DEC=y >> > CONFIG_XZ_DEC_X86=y >> > # CONFIG_XZ_DEC_POWERPC is not set >> > # CONFIG_XZ_DEC_IA64 is not set >> > # CONFIG_XZ_DEC_ARM is not set >> > # CONFIG_XZ_DEC_ARMTHUMB is not set >> > # CONFIG_XZ_DEC_SPARC is not set >> > CONFIG_XZ_DEC_BCJ=y >> > # CONFIG_XZ_DEC_TEST is not set >> > CONFIG_DECOMPRESS_GZIP=y >> > CONFIG_GENERIC_ALLOCATOR=y >> > CONFIG_INTERVAL_TREE=y >> > CONFIG_ASSOCIATIVE_ARRAY=y >> > CONFIG_HAS_IOMEM=y >> > CONFIG_HAS_IOPORT_MAP=y >> > CONFIG_HAS_DMA=y >> > CONFIG_NEED_SG_DMA_LENGTH=y >> > CONFIG_NEED_DMA_MAP_STATE=y >> > CONFIG_ARCH_DMA_ADDR_T_64BIT=y >> > CONFIG_SWIOTLB=y >> > # CONFIG_DMA_API_DEBUG is not set >> > CONFIG_SGL_ALLOC=y >> > CONFIG_IOMMU_HELPER=y >> > CONFIG_CHECK_SIGNATURE=y >> > CONFIG_CPU_RMAP=y >> > CONFIG_DQL=y >> > CONFIG_GLOB=y >> > # CONFIG_GLOB_SELFTEST is not set >> > CONFIG_NLATTR=y >> > CONFIG_CLZ_TAB=y >> > # CONFIG_IRQ_POLL is not set >> > CONFIG_MPILIB=y >> > CONFIG_OID_REGISTRY=y >> > CONFIG_UCS2_STRING=y >> > CONFIG_HAVE_GENERIC_VDSO=y >> > CONFIG_GENERIC_GETTIMEOFDAY=y >> > CONFIG_GENERIC_VDSO_TIME_NS=y >> > CONFIG_FONT_SUPPORT=y >> > CONFIG_FONT_8x16=y >> > CONFIG_FONT_AUTOSELECT=y >> > CONFIG_SG_POOL=y >> > CONFIG_ARCH_HAS_PMEM_API=y >> > CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y >> > CONFIG_ARCH_HAS_UACCESS_MCSAFE=y >> > CONFIG_ARCH_STACKWALK=y >> > CONFIG_SBITMAP=y >> > # CONFIG_STRING_SELFTEST is not set >> > # end of Library routines >> > >> > # >> > # Kernel hacking >> > # >> > >> > # >> > # printk and dmesg options >> > # >> > # CONFIG_PRINTK_TIME is not set >> > # CONFIG_PRINTK_CALLER is not set >> > CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 >> > CONFIG_CONSOLE_LOGLEVEL_QUIET=4 >> > CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 >> > # CONFIG_BOOT_PRINTK_DELAY is not set >> > # CONFIG_DYNAMIC_DEBUG is not set >> > CONFIG_SYMBOLIC_ERRNAME=y >> > CONFIG_DEBUG_BUGVERBOSE=y >> > # end of printk and dmesg options >> > >> > # >> > # Compile-time checks and compiler options >> > # >> > CONFIG_DEBUG_INFO=y >> > # CONFIG_DEBUG_INFO_REDUCED is not set >> > # CONFIG_DEBUG_INFO_SPLIT is not set >> > # CONFIG_DEBUG_INFO_DWARF4 is not set >> > # CONFIG_DEBUG_INFO_BTF is not set >> > # CONFIG_GDB_SCRIPTS is not set >> > # CONFIG_ENABLE_MUST_CHECK is not set >> > CONFIG_FRAME_WARN=2048 >> > # CONFIG_STRIP_ASM_SYMS is not set >> > # CONFIG_READABLE_ASM is not set >> > CONFIG_HEADERS_INSTALL=y >> > CONFIG_DEBUG_SECTION_MISMATCH=y >> > CONFIG_SECTION_MISMATCH_WARN_ONLY=y >> > CONFIG_STACK_VALIDATION=y >> > # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set >> > # end of Compile-time checks and compiler options >> > >> > # >> > # Generic Kernel Debugging Instruments >> > # >> > CONFIG_MAGIC_SYSRQ=y >> > CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 >> > CONFIG_MAGIC_SYSRQ_SERIAL=y >> > CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" >> > CONFIG_DEBUG_FS=y >> > CONFIG_HAVE_ARCH_KGDB=y >> > # CONFIG_KGDB is not set >> > CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y >> > # CONFIG_UBSAN is not set >> > # end of Generic Kernel Debugging Instruments >> > >> > CONFIG_DEBUG_KERNEL=y >> > CONFIG_DEBUG_MISC=y >> > >> > # >> > # Memory Debugging >> > # >> > # CONFIG_PAGE_EXTENSION is not set >> > # CONFIG_DEBUG_PAGEALLOC is not set >> > # CONFIG_PAGE_OWNER is not set >> > # CONFIG_PAGE_POISONING is not set >> > # CONFIG_DEBUG_PAGE_REF is not set >> > # CONFIG_DEBUG_RODATA_TEST is not set >> > CONFIG_GENERIC_PTDUMP=y >> > # CONFIG_PTDUMP_DEBUGFS is not set >> > # CONFIG_DEBUG_OBJECTS is not set >> > # CONFIG_DEBUG_SLAB is not set >> > CONFIG_HAVE_DEBUG_KMEMLEAK=y >> > # CONFIG_DEBUG_KMEMLEAK is not set >> > # CONFIG_DEBUG_STACK_USAGE is not set >> > # CONFIG_SCHED_STACK_END_CHECK is not set >> > # CONFIG_DEBUG_VM is not set >> > CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y >> > # CONFIG_DEBUG_VIRTUAL is not set >> > # CONFIG_DEBUG_MEMORY_INIT is not set >> > # CONFIG_DEBUG_PER_CPU_MAPS is not set >> > CONFIG_HAVE_ARCH_KASAN=y >> > CONFIG_HAVE_ARCH_KASAN_VMALLOC=y >> > CONFIG_CC_HAS_KASAN_GENERIC=y >> > # CONFIG_KASAN is not set >> > CONFIG_KASAN_STACK=1 >> > # end of Memory Debugging >> > >> > # CONFIG_DEBUG_SHIRQ is not set >> > >> > # >> > # Debug Oops, Lockups and Hangs >> > # >> > # CONFIG_PANIC_ON_OOPS is not set >> > CONFIG_PANIC_ON_OOPS_VALUE=0 >> > CONFIG_PANIC_TIMEOUT=0 >> > CONFIG_LOCKUP_DETECTOR=y >> > CONFIG_SOFTLOCKUP_DETECTOR=y >> > # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set >> > CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 >> > CONFIG_HARDLOCKUP_DETECTOR_PERF=y >> > CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y >> > CONFIG_HARDLOCKUP_DETECTOR=y >> > # CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set >> > CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 >> > CONFIG_DETECT_HUNG_TASK=y >> > CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 >> > # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set >> > CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 >> > CONFIG_WQ_WATCHDOG=y >> > # CONFIG_TEST_LOCKUP is not set >> > # end of Debug Oops, Lockups and Hangs >> > >> > # >> > # Scheduler Debugging >> > # >> > # CONFIG_SCHED_DEBUG is not set >> > CONFIG_SCHED_INFO=y >> > # CONFIG_SCHEDSTATS is not set >> > # end of Scheduler Debugging >> > >> > # CONFIG_DEBUG_TIMEKEEPING is not set >> > >> > # >> > # Lock Debugging (spinlocks, mutexes, etc...) >> > # >> > CONFIG_LOCK_DEBUGGING_SUPPORT=y >> > # CONFIG_PROVE_LOCKING is not set >> > # CONFIG_LOCK_STAT is not set >> > CONFIG_DEBUG_RT_MUTEXES=y >> > CONFIG_DEBUG_SPINLOCK=y >> > CONFIG_DEBUG_MUTEXES=y >> > # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set >> > # CONFIG_DEBUG_RWSEMS is not set >> > # CONFIG_DEBUG_LOCK_ALLOC is not set >> > # CONFIG_DEBUG_ATOMIC_SLEEP is not set >> > # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set >> > # CONFIG_LOCK_TORTURE_TEST is not set >> > # CONFIG_WW_MUTEX_SELFTEST is not set >> > # end of Lock Debugging (spinlocks, mutexes, etc...) >> > >> > CONFIG_STACKTRACE=y >> > # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set >> > # CONFIG_DEBUG_KOBJECT is not set >> > >> > # >> > # Debug kernel data structures >> > # >> > # CONFIG_DEBUG_LIST is not set >> > # CONFIG_DEBUG_PLIST is not set >> > # CONFIG_DEBUG_SG is not set >> > # CONFIG_DEBUG_NOTIFIERS is not set >> > # CONFIG_BUG_ON_DATA_CORRUPTION is not set >> > # end of Debug kernel data structures >> > >> > # CONFIG_DEBUG_CREDENTIALS is not set >> > >> > # >> > # RCU Debugging >> > # >> > # CONFIG_RCU_PERF_TEST is not set >> > # CONFIG_RCU_TORTURE_TEST is not set >> > CONFIG_RCU_CPU_STALL_TIMEOUT=60 >> > # CONFIG_RCU_TRACE is not set >> > # CONFIG_RCU_EQS_DEBUG is not set >> > # end of RCU Debugging >> > >> > # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set >> > # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set >> > # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set >> > # CONFIG_LATENCYTOP is not set >> > CONFIG_USER_STACKTRACE_SUPPORT=y >> > CONFIG_NOP_TRACER=y >> > CONFIG_HAVE_FUNCTION_TRACER=y >> > CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y >> > CONFIG_HAVE_DYNAMIC_FTRACE=y >> > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y >> > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y >> > CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y >> > CONFIG_HAVE_SYSCALL_TRACEPOINTS=y >> > CONFIG_HAVE_FENTRY=y >> > CONFIG_HAVE_C_RECORDMCOUNT=y >> > CONFIG_TRACE_CLOCK=y >> > CONFIG_RING_BUFFER=y >> > CONFIG_EVENT_TRACING=y >> > CONFIG_CONTEXT_SWITCH_TRACER=y >> > CONFIG_TRACING=y >> > CONFIG_GENERIC_TRACER=y >> > CONFIG_TRACING_SUPPORT=y >> > CONFIG_FTRACE=y >> > # CONFIG_BOOTTIME_TRACING is not set >> > CONFIG_FUNCTION_TRACER=y >> > CONFIG_FUNCTION_GRAPH_TRACER=y >> > CONFIG_DYNAMIC_FTRACE=y >> > CONFIG_DYNAMIC_FTRACE_WITH_REGS=y >> > CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y >> > # CONFIG_FUNCTION_PROFILER is not set >> > # CONFIG_STACK_TRACER is not set >> > # CONFIG_PREEMPTIRQ_EVENTS is not set >> > # CONFIG_IRQSOFF_TRACER is not set >> > # CONFIG_SCHED_TRACER is not set >> > # CONFIG_HWLAT_TRACER is not set >> > # CONFIG_MMIOTRACE is not set >> > CONFIG_FTRACE_SYSCALLS=y >> > # CONFIG_TRACER_SNAPSHOT is not set >> > CONFIG_BRANCH_PROFILE_NONE=y >> > # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set >> > # CONFIG_PROFILE_ALL_BRANCHES is not set >> > # CONFIG_BLK_DEV_IO_TRACE is not set >> > CONFIG_KPROBE_EVENTS=y >> > # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set >> > # CONFIG_UPROBE_EVENTS is not set >> > CONFIG_BPF_EVENTS=y >> > CONFIG_DYNAMIC_EVENTS=y >> > CONFIG_PROBE_EVENTS=y >> > # CONFIG_BPF_KPROBE_OVERRIDE is not set >> > CONFIG_FTRACE_MCOUNT_RECORD=y >> > # CONFIG_HIST_TRIGGERS is not set >> > # CONFIG_TRACE_EVENT_INJECT is not set >> > # CONFIG_TRACEPOINT_BENCHMARK is not set >> > # CONFIG_RING_BUFFER_BENCHMARK is not set >> > # CONFIG_TRACE_EVAL_MAP_FILE is not set >> > # CONFIG_FTRACE_STARTUP_TEST is not set >> > # CONFIG_RING_BUFFER_STARTUP_TEST is not set >> > # CONFIG_PREEMPTIRQ_DELAY_TEST is not set >> > # CONFIG_KPROBE_EVENT_GEN_TEST is not set >> > # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set >> > CONFIG_SAMPLES=y >> > # CONFIG_SAMPLE_TRACE_EVENTS is not set >> > # CONFIG_SAMPLE_TRACE_PRINTK is not set >> > # CONFIG_SAMPLE_FTRACE_DIRECT is not set >> > # CONFIG_SAMPLE_TRACE_ARRAY is not set >> > # CONFIG_SAMPLE_KOBJECT is not set >> > # CONFIG_SAMPLE_KPROBES is not set >> > # CONFIG_SAMPLE_HW_BREAKPOINT is not set >> > # CONFIG_SAMPLE_KFIFO is not set >> > # CONFIG_SAMPLE_LIVEPATCH is not set >> > # CONFIG_SAMPLE_CONFIGFS is not set >> > # CONFIG_SAMPLE_HIDRAW is not set >> > # CONFIG_SAMPLE_PIDFD is not set >> > # CONFIG_SAMPLE_SECCOMP is not set >> > # CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set >> > CONFIG_SAMPLE_VFS=y >> > # CONFIG_SAMPLE_INTEL_MEI is not set >> > CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y >> > >> > # >> > # x86 Debugging >> > # >> > CONFIG_TRACE_IRQFLAGS_SUPPORT=y >> > CONFIG_X86_VERBOSE_BOOTUP=y >> > CONFIG_EARLY_PRINTK=y >> > # CONFIG_EARLY_PRINTK_DBGP is not set >> > # CONFIG_EARLY_PRINTK_USB_XDBC is not set >> > # CONFIG_EFI_PGT_DUMP is not set >> > # CONFIG_DEBUG_WX is not set >> > CONFIG_DOUBLEFAULT=y >> > # CONFIG_DEBUG_TLBFLUSH is not set >> > # CONFIG_IOMMU_DEBUG is not set >> > CONFIG_HAVE_MMIOTRACE_SUPPORT=y >> > # CONFIG_X86_DECODER_SELFTEST is not set >> > CONFIG_IO_DELAY_0X80=y >> > # CONFIG_IO_DELAY_0XED is not set >> > # CONFIG_IO_DELAY_UDELAY is not set >> > # CONFIG_IO_DELAY_NONE is not set >> > # CONFIG_DEBUG_BOOT_PARAMS is not set >> > # CONFIG_CPA_DEBUG is not set >> > # CONFIG_DEBUG_ENTRY is not set >> > # CONFIG_DEBUG_NMI_SELFTEST is not set >> > # CONFIG_X86_DEBUG_FPU is not set >> > # CONFIG_PUNIT_ATOM_DEBUG is not set >> > CONFIG_UNWINDER_ORC=y >> > # CONFIG_UNWINDER_FRAME_POINTER is not set >> > # CONFIG_UNWINDER_GUESS is not set >> > # end of x86 Debugging >> > >> > # >> > # Kernel Testing and Coverage >> > # >> > # CONFIG_KUNIT is not set >> > # CONFIG_NOTIFIER_ERROR_INJECTION is not set >> > CONFIG_FUNCTION_ERROR_INJECTION=y >> > # CONFIG_FAULT_INJECTION is not set >> > CONFIG_ARCH_HAS_KCOV=y >> > CONFIG_CC_HAS_SANCOV_TRACE_PC=y >> > # CONFIG_KCOV is not set >> > # CONFIG_RUNTIME_TESTING_MENU is not set >> > # CONFIG_MEMTEST is not set >> > # end of Kernel Testing and Coverage >> > # end of Kernel hacking >> >> -- >> Jani Nikula, Intel Open Source Graphics Center >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center From kai.heng.feng at canonical.com Mon Jun 8 09:04:58 2020 From: kai.heng.feng at canonical.com (Kai-Heng Feng) Date: Mon, 08 Jun 2020 09:04:58 -0000 Subject: [Intel-gfx] [PATCH v5] drm/i915: Init lspcon chip dynamically Message-ID: <20200506102844.26596-1-kai.heng.feng@canonical.com> On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port becomes useless and never responds to cable hotplugging: [ 3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon [ 3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D Seems like the lspcon chip on the system only gets powered after the cable is plugged. Consolidate lspcon_init() into lspcon_resume() to dynamically init lspcon chip, and make HDMI port work. Closes: https://gitlab.freedesktop.org/drm/intel/issues/203 Signed-off-by: Kai-Heng Feng <kai.heng.feng at canonical.com> --- v5: - Consolidate lspcon_resume() with lspcon_init(). - Move more logic into lspcon code. v4: - Trust VBT in intel_infoframe_init(). - Init lspcon in intel_dp_detect(). v3: - Make sure it's handled under long HPD case. v2: - Move lspcon_init() inside of intel_dp_hpd_pulse(). drivers/gpu/drm/i915/display/intel_ddi.c | 19 +------ drivers/gpu/drm/i915/display/intel_dp.c | 10 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 63 ++++++++++++--------- drivers/gpu/drm/i915/display/intel_lspcon.h | 3 +- 5 files changed, 43 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5601673c3f30..798fd640da54 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4770,7 +4770,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) { struct intel_digital_port *intel_dig_port; struct intel_encoder *encoder; - bool init_hdmi, init_dp, init_lspcon = false; + bool init_hdmi, init_dp; enum phy phy = intel_port_to_phy(dev_priv, port); init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || @@ -4784,7 +4784,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) * is initialized before lspcon. */ init_dp = true; - init_lspcon = true; init_hdmi = false; drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", port_name(port)); @@ -4869,22 +4868,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) goto err; } - if (init_lspcon) { - if (lspcon_init(intel_dig_port)) - /* TODO: handle hdmi info frame part */ - drm_dbg_kms(&dev_priv->drm, - "LSPCON init success on port %c\n", - port_name(port)); - else - /* - * LSPCON init faied, but DP init was success, so - * lets try to drive as DP++ port. - */ - drm_err(&dev_priv->drm, - "LSPCON init failed on port %c\n", - port_name(port)); - } - intel_infoframe_init(intel_dig_port); return; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6952b0295096..e26aa35d6e37 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5938,15 +5938,14 @@ static enum drm_connector_status intel_dp_detect_dpcd(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u8 *dpcd = intel_dp->dpcd; u8 type; if (WARN_ON(intel_dp_is_edp(intel_dp))) return connector_status_connected; - if (lspcon->active) - lspcon_resume(lspcon); + lspcon_resume(dig_port); if (!intel_dp_get_dpcd(intel_dp)) return connector_status_disconnected; @@ -7198,14 +7197,13 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); intel_wakeref_t wakeref; if (!HAS_DDI(dev_priv)) intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); - if (lspcon->active) - lspcon_resume(lspcon); + lspcon_resume(dig_port); intel_dp->reset_link_params = true; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 010f37240710..643ad2127931 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3155,7 +3155,8 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port) intel_dig_port->set_infoframes = g4x_set_infoframes; intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; } else if (HAS_DDI(dev_priv)) { - if (intel_dig_port->lspcon.active) { + if (intel_bios_is_lspcon_present(dev_priv, + intel_dig_port->base.port)) { intel_dig_port->write_infoframe = lspcon_write_infoframe; intel_dig_port->read_infoframe = lspcon_read_infoframe; intel_dig_port->set_infoframes = lspcon_set_infoframes; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index d807c5648c87..f5f06d2a839a 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -525,44 +525,17 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, return enc_to_intel_lspcon(encoder)->active; } -void lspcon_resume(struct intel_lspcon *lspcon) -{ - enum drm_lspcon_mode expected_mode; - - if (lspcon_wake_native_aux_ch(lspcon)) { - expected_mode = DRM_LSPCON_MODE_PCON; - lspcon_resume_in_pcon_wa(lspcon); - } else { - expected_mode = DRM_LSPCON_MODE_LS; - } - - if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) - return; - - if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) - DRM_ERROR("LSPCON resume failed\n"); - else - DRM_DEBUG_KMS("LSPCON resume success\n"); -} - void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) { lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); } -bool lspcon_init(struct intel_digital_port *intel_dig_port) +static bool lspcon_init(struct intel_digital_port *intel_dig_port) { struct intel_dp *dp = &intel_dig_port->dp; struct intel_lspcon *lspcon = &intel_dig_port->lspcon; - struct drm_device *dev = intel_dig_port->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); struct drm_connector *connector = &dp->attached_connector->base; - if (!HAS_LSPCON(dev_priv)) { - DRM_ERROR("LSPCON is not supported on this platform\n"); - return false; - } - lspcon->active = false; lspcon->mode = DRM_LSPCON_MODE_INVALID; @@ -586,3 +559,37 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) DRM_DEBUG_KMS("Success: LSPCON init\n"); return true; } + +void lspcon_resume(struct intel_digital_port *intel_dig_port) +{ + struct intel_lspcon *lspcon = &intel_dig_port->lspcon; + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum drm_lspcon_mode expected_mode; + + if (!intel_bios_is_lspcon_present(dev_priv, intel_dig_port->base.port)) + return; + + if (!lspcon->active) { + if (!lspcon_init(intel_dig_port)) { + DRM_ERROR("LSPCON init failed on port %c\n", + port_name(intel_dig_port->base.port)); + return; + } + } + + if (lspcon_wake_native_aux_ch(lspcon)) { + expected_mode = DRM_LSPCON_MODE_PCON; + lspcon_resume_in_pcon_wa(lspcon); + } else { + expected_mode = DRM_LSPCON_MODE_LS; + } + + if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) + return; + + if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) + DRM_ERROR("LSPCON resume failed\n"); + else + DRM_DEBUG_KMS("LSPCON resume success\n"); +} diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 37cfddf8a9c5..169db35db13e 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -15,8 +15,7 @@ struct intel_digital_port; struct intel_encoder; struct intel_lspcon; -bool lspcon_init(struct intel_digital_port *intel_dig_port); -void lspcon_resume(struct intel_lspcon *lspcon); +void lspcon_resume(struct intel_digital_port *intel_dig_port); void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); void lspcon_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, -- 2.17.1 From patchwork at emeril.freedesktop.org Mon Jun 8 09:16:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 09:16:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_Avoid_PSR_and_FBC_features_concurently=2E?= In-Reply-To: <20200608065635.11652-1-jason.v.le@intel.com> References: <20200608065635.11652-1-jason.v.le@intel.com> Message-ID: <159160776085.14463.12185795708270224212@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Avoid PSR and FBC features concurently. URL : https://patchwork.freedesktop.org/series/78107/ State : success == Summary == CI Bug Log - changes from CI_DRM_8599_full -> Patchwork_17904_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17904_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl4/igt at gem_workarounds@suspend-resume-fd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl7/igt at gem_workarounds@suspend-resume-fd.html * igt at gen9_exec_parse@allowed-all: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl2/igt at gen9_exec_parse@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl7/igt at gen9_exec_parse@allowed-all.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +6 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl10/igt at kms_color@pipe-a-ctm-0-5.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl2/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_legacy@all-pipes-torture-bo: - shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([i915#128]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-hsw1/igt at kms_cursor_legacy@all-pipes-torture-bo.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-hsw2/igt at kms_cursor_legacy@all-pipes-torture-bo.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-tglb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr2_su@page_flip: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109642] / [fdo#111068]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb2/igt at kms_psr2_su@page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-iclb8/igt at kms_psr2_su@page_flip.html * igt at kms_psr@suspend: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([i915#1185]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb3/igt at kms_psr@suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-iclb3/igt at kms_psr@suspend.html * igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#69]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl10/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html #### Possible fixes #### * igt at gem_exec_schedule@smoketest-all: - shard-glk: [DMESG-WARN][21] ([i915#118] / [i915#95]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk1/igt at gem_exec_schedule@smoketest-all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-glk8/igt at gem_exec_schedule@smoketest-all.html * igt at gem_pread@display: - shard-hsw: [INCOMPLETE][23] ([i915#61]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-hsw4/igt at gem_pread@display.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-hsw7/igt at gem_pread@display.html * igt at gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][25] ([i915#1436] / [i915#716]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl7/igt at gen9_exec_parse@allowed-all.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl2/igt at gen9_exec_parse@allowed-all.html - shard-glk: [DMESG-WARN][27] ([i915#1436] / [i915#716]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk8/igt at gen9_exec_parse@allowed-all.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-glk2/igt at gen9_exec_parse@allowed-all.html * igt at i915_pm_rpm@modeset-lpsp-stress: - shard-skl: [DMESG-WARN][29] -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at i915_pm_rpm@modeset-lpsp-stress.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl5/igt at i915_pm_rpm@modeset-lpsp-stress.html * igt at kms_atomic@test-only: - shard-apl: [DMESG-WARN][31] ([i915#95]) -> [PASS][32] +45 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl1/igt at kms_atomic@test-only.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl4/igt at kms_atomic@test-only.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-onscreen: - shard-kbl: [DMESG-FAIL][33] ([i915#54] / [i915#95]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [FAIL][35] ([i915#57]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-hsw4/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: - shard-apl: [DMESG-FAIL][37] ([i915#54] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl3/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html * igt at kms_fbcon_fbt@fbc: - shard-kbl: [FAIL][39] ([i915#64]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl6/igt at kms_fbcon_fbt@fbc.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl1/igt at kms_fbcon_fbt@fbc.html - shard-apl: [FAIL][41] ([i915#1525]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl2/igt at kms_fbcon_fbt@fbc.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl8/igt at kms_fbcon_fbt@fbc.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +4 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at c-dp1}: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +3 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render: - shard-glk: [INCOMPLETE][47] ([i915#58] / [k.org#198133]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-glk5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-glk7/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][49] ([i915#93] / [i915#95]) -> [PASS][50] +46 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-iclb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-iclb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - shard-apl: [DMESG-FAIL][55] ([i915#95]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl1/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl4/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html - shard-kbl: [DMESG-FAIL][57] ([i915#95]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl4/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl3/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [DMESG-WARN][59] ([i915#180] / [i915#95]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-position-covered-pipe-c-planes: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +11 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl8/igt at kms_plane@plane-position-covered-pipe-c-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl6/igt at kms_plane@plane-position-covered-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb5/igt at kms_psr2_su@frontbuffer.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb5/igt at kms_psr@psr2_sprite_blt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][69] ([i915#1542]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-iclb1/igt at perf@blocking-parameterized.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-iclb4/igt at perf@blocking-parameterized.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-apl: [FAIL][71] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl2/igt at kms_content_protection@atomic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][73] ([i915#1319] / [i915#1958]) -> [TIMEOUT][74] ([i915#1319]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl4/igt at kms_content_protection@atomic-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][75] ([i915#1319]) -> [FAIL][76] ([fdo#110321] / [fdo#110336]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-kbl2/igt at kms_content_protection@legacy.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-kbl2/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][77] ([i915#1319]) -> [FAIL][78] ([fdo#110321]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8599/shard-apl8/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/shard-apl7/igt at kms_content_protection@lic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8599 -> Patchwork_17904 CI-20190529: 20190529 CI_DRM_8599: 41ca9ea98b74c926c923e84931b9b4a4c3955e08 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5697: 5b8be04285ded1201fac5a2c2b50a7d70fa332d8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17904: dee7c897c6ed8262b5655c110352e85c7e13e8c1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17904/index.html From chris at chris-wilson.co.uk Mon Jun 8 09:33:25 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 08 Jun 2020 10:33:25 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> Message-ID: <159160880517.15126.3134918011284478228@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-08 08:44:01) > > On 07/06/2020 23:20, Chris Wilson wrote: > > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > > > Sentinels are supposed to be last reqeusts in the elsp queue, not the > > only one, so adjust the assert accordingly. > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- > > 1 file changed, 3 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > > index d55a5e0466e5..db8a170b0e5c 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > > @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > > ccid = ce->lrc.ccid; > > > > /* > > - * Sentinels are supposed to be lonely so they flush the > > - * current exection off the HW. Check that they are the > > - * only request in the pending submission. > > + * Sentinels are supposed to be the last request so they flush > > + * the current exection off the HW. Check that they are the only > > + * request in the pending submission. > > */ > > if (sentinel) { > > GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", > > @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > > port - execlists->pending); > > return false; > > } > > - > > sentinel = i915_request_has_sentinel(rq); > > FWIW I was changing it to "sentinel |= ..." so it keeps working if we > decide to use more than 2 elsp ports on Icelake one day. But it will always fail on the next port... -Chris From jani.nikula at linux.intel.com Mon Jun 8 09:37:05 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Mon, 08 Jun 2020 12:37:05 +0300 Subject: [Intel-gfx] [PATCH] Revert "drm/i915: Remove unneeded hack now for CDCLK" In-Reply-To: <20200608083540.GA22223@intel.com> References: <20200608065552.21728-1-stanislav.lisovskiy@intel.com> <87img2x91h.fsf@intel.com> <20200608083540.GA22223@intel.com> Message-ID: <878sgxyk3i.fsf@intel.com> On Mon, 08 Jun 2020, "Lisovskiy, Stanislav" <stanislav.lisovskiy at intel.com> wrote: > On Mon, Jun 08, 2020 at 11:21:14AM +0300, Jani Nikula wrote: >> On Mon, 08 Jun 2020, Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> wrote: >> > This reverts commit 82ea174dc5425d4e85e25d0c4ba961a2e494392a. >> > >> >> Please explain why. What's going on, why we need the revert. >> >> It's fine to reply here, the commit message can be amended by whoever >> applies the patch. > > Yes, > > Unfortunately according to our recent findings there is still some > unidentified factor, requiring CDCLK to be set higher - otherwise we > still get underruns on some multipipe configurations, despite CDCLK being set > according to BSpec formula. So getting again back into debug mode to > indentify the cause, meanwhile setting CDCLK=Pixel rate back in order > to remove regression in 10% of the cases due to FIFO underruns. Thanks, pushed. BR, Jani. > > Stan > >> >> BR, >> Jani. >> >> >> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> >> > Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs") >> > --- >> > drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ++++++++++++ >> > 1 file changed, 12 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c >> > index 08468b121d02..45f7f33d1144 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c >> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c >> > @@ -2071,6 +2071,18 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) >> > /* Account for additional needs from the planes */ >> > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); >> > >> > + /* >> > + * HACK. Currently for TGL platforms we calculate >> > + * min_cdclk initially based on pixel_rate divided >> > + * by 2, accounting for also plane requirements, >> > + * however in some cases the lowest possible CDCLK >> > + * doesn't work and causing the underruns. >> > + * Explicitly stating here that this seems to be currently >> > + * rather a Hack, than final solution. >> > + */ >> > + if (IS_TIGERLAKE(dev_priv)) >> > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); >> > + >> > if (min_cdclk > dev_priv->max_cdclk_freq) { >> > drm_dbg_kms(&dev_priv->drm, >> > "required cdclk (%d kHz) exceeds max (%d kHz)\n", >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center From joonas.lahtinen at linux.intel.com Mon Jun 8 09:47:57 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Mon, 08 Jun 2020 12:47:57 +0300 Subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices In-Reply-To: <87eequpla6.fsf@riseup.net> References: <20200604182658.878417-1-ayaz.siddiqui@intel.com> <87eequpla6.fsf@riseup.net> Message-ID: <159160967766.60481.16392357667625923690@jlahtine-desk.ger.corp.intel.com> + Jason and Ken Quoting Francisco Jerez (2020-06-05 00:34:57) > Ayaz A Siddiqui <ayaz.siddiqui at intel.com> writes: > > > In order to avoid functional breakage of mis-programmed applications that > > have grown to depend on unused MOCS entries, we are programming > > those entries to be equal to fully cached ("L3 + LLC") entry as per the > > recommendation from architecture team. > > > > These reserved and unspecified entries should not be used as they may be > > changed to less performant variants with better coherency in the future > > if more entries are needed. This patch message needs reworking. It should just standalone describe the technical reasoning behind the patch completely, without referring to elsewhere or to some other decision. The patch should also Cc: relevant developers who have previously been working on the MOCS code and the userspace driver folks (Mesa, compute and media). > This change seems highly questionable to me... If a future kernel > release introduces a new MOCS entry with more strict coherency > semantics, and an application starts relying on it, that application > won't work when run on an older kernel version with this patch is > applied. IOW setting uninitialized entries to the most strict caching > setting available (UC) ensures forwards compatibility with future > userspace, which seems like a more important design principle than > giving full caching to broken userspace that accidentally makes use of > an undefined MOCS entry not part of the kernel ABI. Both choices were considered, and ultimately Ken and Jason were more in favor of 'worst coherency' if using reserved MOCS entry. Your concern about newer software on older kernel is valid. But the starting point of the decision is the no-regression policy of Linux. If we have some application developed on an older kernel where the MOCS entry is unused and would be UC (best coherency), we would have no choice but to keep that entry unused indefinitely not to break the mis-programmed application. Now we have the worst coherency by default if an application is using reserved entry, making it more likely to be noticed at develop time. And even if it would not be noticed, modifying the entry for better coherency should not functionally break the application. Regards, Joonas > > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com> > > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- > > 1 file changed, 89 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > > index 632e08a4592b..1089bd5fdba2 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > > @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > > L3_1_UC) > > > > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > > - /* Base - Error (Reserved for Non-Use) */ > > - MOCS_ENTRY(0, 0x0, 0x0), > > - /* Base - Reserved */ > > - MOCS_ENTRY(1, 0x0, 0x0), > > > > GEN11_MOCS_ENTRIES, > > > > @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > > MOCS_ENTRY(61, > > LE_1_UC | LE_TC_1_LLC, > > L3_3_WB), > > + > > + /* NOTE: > > + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). > > + * These reserved entry should never be used, they may be chanaged > > + * to low performant variants with better coherency in the future if > > + * more entries are needed. > > + */ > > + > > + /* Reserved index 0 and 1 */ > > + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Reserved index 16 and 17 */ > > + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Reserved index 24 and 25 */ > > + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Unspecified indices 26 to 47 */ > > + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + > > + /* Unspecified indices 52 to 59 */ > > + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB), > > + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), > > + L3_3_WB) > > }; > > > > static const struct drm_i915_mocs_entry icl_mocs_table[] = { > > -- > > 2.26.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From ankit.k.nautiyal at intel.com Mon Jun 8 10:01:01 2020 From: ankit.k.nautiyal at intel.com (Ankit Nautiyal) Date: Mon, 8 Jun 2020 15:31:01 +0530 Subject: [Intel-gfx] [PATCH v2 0/2] Add debugfs for requesting HDCP version Message-ID: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> Currently, for a given content-protection request, the kernel selects the highest version of HDCP supported by the panel and the platform. This makes the testing/debugging difficult for lower versions of HDCP. E.g. In case both the lower and the higher HDCP versions are supported then the higher version of HDCP will always be selected and the lower HDCP version cannot be tested without changing the setup. A solution for this was proposed in an IGT patch [1] by removing "mei_hdcp" module, but a need for a generic future-proof solution was identified. As suggested by the community members, this patch attempts to add a new debugfs per connector for requesting a specific version of HDCP for debug/testing environment. The test can request for a specific HDCP version and set the appropriate content-protection connector properties to test the required version. The kernel will consider the request if the HDCP version is sufficient for the requested content-protection. [1] https://patchwork.freedesktop.org/patch/358240/ Ankit Nautiyal (2): drm/i915: Add support for considering HDCP ver requested via debugfs drm/i915: Add a new debugfs to request HDCP version .../drm/i915/display/intel_display_debugfs.c | 68 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 10 +++ drivers/gpu/drm/i915/display/intel_hdcp.c | 16 ++++- 3 files changed, 92 insertions(+), 2 deletions(-) -- 2.17.1 From ankit.k.nautiyal at intel.com Mon Jun 8 10:01:02 2020 From: ankit.k.nautiyal at intel.com (Ankit Nautiyal) Date: Mon, 8 Jun 2020 15:31:02 +0530 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add support for considering HDCP ver requested via debugfs In-Reply-To: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> Message-ID: <20200608100103.19472-2-ankit.k.nautiyal@intel.com> For testing and debugging each HDCP version separately, a debugfs entry for requesting a specific version is required. The version requested via debugfs needs to be stored in hdcp structure. This can then be considered while enabling HDCP, provided the platform and the display supports the requested version. This patch adds the support for storing the version requested as a 32bit flag. It also adds a helper function to check if a version is requested. If a specific HDCP version is requested through the debugfs, the driver chooses that version, instead of policy of choosing the highest HDCP version supported. v2: Initialize debugfs_ver_request flag with 0. (Jani Nikula) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com> --- .../gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_hdcp.c | 16 ++++++++++++++-- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9488449e4b94..cfa641c70717 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -408,6 +408,16 @@ struct intel_hdcp { * Hence caching the transcoder here. */ enum transcoder cpu_transcoder; + + /* + * HDCP version requested from debugfs i915_hdcp_ver_request. + * Kernel will read these bits and entertain the request, as per + * the HDCP capability of the panel and platform. + */ +#define HDCP_VERSION_1_4 0x01 +#define HDCP_VERSION_2_2 0x02 +#define HDCP_VERSION_MASK 0x03 + u32 debugfs_ver_request; }; struct intel_connector { diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 2cbc4619b4ce..a21ea9c2e9a7 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -1977,6 +1977,8 @@ int intel_hdcp_init(struct intel_connector *connector, if (!shim) return -EINVAL; + hdcp->debugfs_ver_request = 0; + if (is_hdcp2_supported(dev_priv)) intel_hdcp2_init(connector, shim); @@ -1998,6 +2000,14 @@ int intel_hdcp_init(struct intel_connector *connector, return 0; } +static bool hdcp_debugfs_requested(struct intel_hdcp *hdcp, u32 hdcp_version) +{ + if (!hdcp->debugfs_ver_request) + return true; + + return hdcp->debugfs_ver_request & hdcp_version ? true : false; +} + int intel_hdcp_enable(struct intel_connector *connector, enum transcoder cpu_transcoder, u8 content_type) { @@ -2023,7 +2033,8 @@ int intel_hdcp_enable(struct intel_connector *connector, * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup * is capable of HDCP2.2, it is preferred to use HDCP2.2. */ - if (intel_hdcp2_capable(connector)) { + if (hdcp_debugfs_requested(hdcp, HDCP_VERSION_2_2) && + intel_hdcp2_capable(connector)) { ret = _intel_hdcp2_enable(connector); if (!ret) check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS; @@ -2033,7 +2044,8 @@ int intel_hdcp_enable(struct intel_connector *connector, * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will * be attempted. */ - if (ret && intel_hdcp_capable(connector) && + if (ret && hdcp_debugfs_requested(hdcp, HDCP_VERSION_1_4) && + intel_hdcp_capable(connector) && hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { ret = _intel_hdcp_enable(connector); } -- 2.17.1 From ankit.k.nautiyal at intel.com Mon Jun 8 10:01:03 2020 From: ankit.k.nautiyal at intel.com (Ankit Nautiyal) Date: Mon, 8 Jun 2020 15:31:03 +0530 Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add a new debugfs to request HDCP version In-Reply-To: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> Message-ID: <20200608100103.19472-3-ankit.k.nautiyal@intel.com> As per the current HDCP design, the driver selects the highest version of HDCP that can be used to satisfy the content-protection requirements of the user. Due to this, the content-protection tests cannot test a lower version of HDCP, if the platform and the display panel, both support higher HDCP version. To provide some support for testing and debugging, a per-connector debugfs is required to set the HDCP version via debugfs that the kernel can consider, while enabling HDCP. This patch adds a new debugfs entry for each connector that supports HDCP. For enforcing a particular HDCP version for a connector, the user can write into the debugfs for that connector. v2: As suggested by Jani Nikula: -used kstrtouint_from_user() to directly read as uint from user buffer. -used 32 bit flag instead of 64 bit for hdcp_ver flag. -removed unnecessary prints and fixed other minor formatting issues. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com> --- .../drm/i915/display/intel_display_debugfs.c | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 70525623bcdf..c01653d412e7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2185,6 +2185,72 @@ static const struct file_operations i915_dsc_fec_support_fops = { .write = i915_dsc_fec_support_write }; +static int i915_hdcp_ver_request_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct intel_connector *intel_connector = to_intel_connector(connector); + u32 hdcp_ver_flag; + + if (connector->status != connector_status_connected) + return -ENODEV; + + /* HDCP is supported by connector */ + if (!intel_connector->hdcp.shim) + return -EINVAL; + + hdcp_ver_flag = intel_connector->hdcp.debugfs_ver_request; + seq_printf(m, "HDCP_VER_FLAGS: %u\n", hdcp_ver_flag); + + return 0; +} + +static int i915_hdcp_ver_request_open(struct inode *inode, + struct file *file) +{ + return single_open(file, i915_hdcp_ver_request_show, + inode->i_private); +} + +static ssize_t i915_hdcp_ver_request_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + unsigned int hdcp_ver = 0; + int ret; + struct drm_connector *connector = + ((struct seq_file *)file->private_data)->private; + struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_hdcp *hdcp = &intel_connector->hdcp; + + if (!hdcp->shim) + return -EINVAL; + + if (len == 0) + return 0; + + ret = kstrtouint_from_user(ubuf, len, 0, &hdcp_ver); + if (ret < 0) + return ret; + + if (hdcp_ver > HDCP_VERSION_MASK) + return -EINVAL; + + hdcp->debugfs_ver_request = hdcp_ver; + + *offp += len; + + return len; +} + +static const struct file_operations i915_hdcp_ver_request_fops = { + .owner = THIS_MODULE, + .open = i915_hdcp_ver_request_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_hdcp_ver_request_write +}; + /** * intel_connector_debugfs_add - add i915 specific connector debugfs files * @connector: pointer to a registered drm_connector @@ -2215,6 +2281,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector) connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, connector, &i915_hdcp_sink_capability_fops); + debugfs_create_file("i915_hdcp_version_request", 0444, root, + connector, &i915_hdcp_ver_request_fops); } if (INTEL_GEN(dev_priv) >= 10 && -- 2.17.1 From chris at chris-wilson.co.uk Mon Jun 8 10:28:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 8 Jun 2020 11:28:45 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Prevent enabling breadcrumbs on the virtual engine Message-ID: <20200608102845.26194-1-chris@chris-wilson.co.uk> The virtual engines are not connected directly to hardware, so do not generate interrupts themselves, nor do we expect to enable breadcrumb tracking on them. However, if we clear out a stale virtual request, we will process the breadcrumbs on the current virtual engine. Here, we only need to add the delayed signal onto the stale signal queue, and send the signal once clear of the engine locks. In the meantime, this may be transferred onto the next sibling if we execute the next virtual request before the work is completed. The effect of losing tracking of the virtual breadcrumb interrupt is that we leak the GT wakeref, keeping the device awake. Reported-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Fixes: b647c7df01b7 ("drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: <stable at vger.kernel.org> # v5.5+ --- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 6 ++++++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +++ drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++ 3 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c index d907d538176e..a6ab1c1dc2cd 100644 --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c @@ -225,6 +225,9 @@ static bool __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b) struct intel_engine_cs *engine = container_of(b, struct intel_engine_cs, breadcrumbs); + if (intel_engine_is_virtual(engine)) + return true; + lockdep_assert_held(&b->irq_lock); if (b->irq_armed) return true; @@ -308,6 +311,9 @@ void intel_engine_transfer_stale_breadcrumbs(struct intel_engine_cs *engine, void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine) { + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + irq_work_sync(&b->irq_work); } bool i915_request_enable_breadcrumb(struct i915_request *rq) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e5141a897786..4f2c348aa32c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1515,6 +1515,9 @@ void intel_engine_dump(struct intel_engine_cs *engine, drm_printf(m, "*** WEDGED ***\n"); drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); + drm_printf(m, "\tBreadcrumbs? armed:%s, signalers:%s\n", + yesno(engine->breadcrumbs.irq_armed), + yesno(!list_empty(&engine->breadcrumbs.signalers))); drm_printf(m, "\tBarriers?: %s\n", yesno(!llist_empty(&engine->barrier_tasks))); drm_printf(m, "\tLatency: %luus\n", diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d55a5e0466e5..9d932e985d96 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -5339,6 +5339,8 @@ static void virtual_context_destroy(struct kref *kref) GEM_BUG_ON(ve->request); GEM_BUG_ON(ve->context.inflight); + intel_engine_fini_breadcrumbs(&ve->base); + for (n = 0; n < ve->num_siblings; n++) { struct intel_engine_cs *sibling = ve->siblings[n]; struct rb_node *node = &ve->nodes[sibling->id].rb; -- 2.20.1 From hdegoede at redhat.com Mon Jun 8 11:07:12 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Mon, 8 Jun 2020 13:07:12 +0200 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200608035023.GZ2428291@smile.fi.intel.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-4-hdegoede@redhat.com> <20200608035023.GZ2428291@smile.fi.intel.com> Message-ID: <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> Hi, On 6/8/20 5:50 AM, Andy Shevchenko wrote: > On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote: >> When the user requests a high enough period ns value, then the >> calculations in pwm_lpss_prepare() might result in a base_unit value of 0. >> >> But according to the data-sheet the way the PWM controller works is that >> each input clock-cycle the base_unit gets added to a N bit counter and >> that counter overflowing determines the PWM output frequency. Adding 0 >> to the counter is a no-op. The data-sheet even explicitly states that >> writing 0 to the base_unit bits will result in the PWM outputting a >> continuous 0 signal. > > So, and why it's a problem? Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 = 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will now get a pin which is always outputting low. OTOH if we clamp to 1 as lowest value, the user will get 192000000 / 65536 = 292 Hz as output frequency which is as close to the requested value as we can get while actually still working as a PWM controller. >> base_unit values > (base_unit_range / 256), or iow base_unit values using >> the 8 most significant bits, cause loss of resolution of the duty-cycle. >> E.g. assuming a base_unit_range of 65536 steps, then a base_unit value of >> 768 (256 * 3), limits the duty-cycle resolution to 65536 / 768 = 85 steps. >> Clamp the max base_unit value to base_unit_range / 32 to ensure a >> duty-cycle resolution of at least 32 steps. This limits the maximum >> output frequency to 600 KHz / 780 KHz depending on the base clock. > > This part I don't understand. Why we limiting base unit? I seems like a > deliberate regression. The way the PWM controller works is that the base-unit gets added to say a 16 bit (on CHT) counter each input clock and then the highest 8 bits of that counter get compared to the value programmed into the ON_TIME_DIV bits. Lets say we do not clamp and allow any value and lets say the user selects an output frequency of half the input clock, so base-unit value is 32768, then the counter will only have 2 values: 0 and 32768 after that it will wrap around again. So any on time-div value < 128 will result in the output being always high and any value > 128 will result in the output being high/low 50% of the time and a value of 255 will make the output always low. So in essence we now only have 3 duty cycle levels, which seems like a bad idea to me / not what a pwm controller is supposed to do. So I decided to put a cut of at having at least 32 steps. The mean reason I wrote this patch though is to avoid a base-unit value of 0 which really results in a completely non working PWM output. I personally believe clamping on the high side is a good idea too. But if you are against that I can drop that part. Note that the clamping on the high side will not affect the primary user of the LPSS-pwm driver which is the i915 backlight code, that never asks for such high frequencies. But it could help to avoid an user shooting themselves in the foot when using the PWM on a dev board through the sysfs interface. Regards, Hans From hdegoede at redhat.com Mon Jun 8 11:13:01 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Mon, 8 Jun 2020 13:13:01 +0200 Subject: [Intel-gfx] [PATCH v2 04/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() In-Reply-To: <20200608035512.GA2428291@smile.fi.intel.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-5-hdegoede@redhat.com> <20200608035512.GA2428291@smile.fi.intel.com> Message-ID: <c8a8d466-9b4a-9021-ca74-01d315e99117@redhat.com> Hi, On 6/8/20 5:55 AM, Andy Shevchenko wrote: > On Sun, Jun 07, 2020 at 08:18:29PM +0200, Hans de Goede wrote: >> According to the data-sheet the way the PWM controller works is that >> each input clock-cycle the base_unit gets added to a N bit counter and >> that counter overflowing determines the PWM output frequency. >> >> So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, >> after 65535 input clock-cycles the counter has been increased from 0 to >> 65535 and it will overflow on the next cycle, so it will overflow after >> every 65536 clock cycles and thus the calculations done in >> pwm_lpss_prepare() should use 65536 and not 65535. >> >> This commit fixes this. Note this also aligns the calculations in >> pwm_lpss_prepare() with those in pwm_lpss_get_state(). > > This one sounds like a bug which I have noticed on Broxton (but thought as a > hardware issue). In any case it has to be tested on various platforms to see > how it affects on them. If you like at the datasheet / read my commit description then it becomes obvious that because of the way the PWM controller works that it takes the full 2^(base-unit-bits) for the counter to overflow, not 2^(base-unit-bits) - 1. This will make a difference of a factor 65535/65536 in the output frequency which will be tricky to measure. IOW I'm not sure we can really test if this helps, but it is obviously the right thing to do and it aligns the pwm_apply code with the pwm_get_state code which already does not have the - 1. Regards, Hans From patchwork at emeril.freedesktop.org Mon Jun 8 11:45:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 11:45:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBk?= =?utf-8?q?rm/i915=3A_Init_lspcon_chip_dynamically?= In-Reply-To: <20200506102844.26596-1-kai.heng.feng@canonical.com> References: <20200506102844.26596-1-kai.heng.feng@canonical.com> Message-ID: <159161673121.14463.9337776016580685827@emeril.freedesktop.org> == Series Details == Series: drm/i915: Init lspcon chip dynamically URL : https://patchwork.freedesktop.org/series/78114/ State : failure == Summary == Applying: drm/i915: Init lspcon chip dynamically Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_ddi.c M drivers/gpu/drm/i915/display/intel_dp.c M drivers/gpu/drm/i915/display/intel_hdmi.c M drivers/gpu/drm/i915/display/intel_lspcon.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_lspcon.c Auto-merging drivers/gpu/drm/i915/display/intel_hdmi.c Auto-merging drivers/gpu/drm/i915/display/intel_dp.c Auto-merging drivers/gpu/drm/i915/display/intel_ddi.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_ddi.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915: Init lspcon chip dynamically When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Mon Jun 8 11:52:47 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 11:52:47 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Add_debugfs_for_requesting_HDCP_version?= In-Reply-To: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> Message-ID: <159161716737.14462.14211708457935388783@emeril.freedesktop.org> == Series Details == Series: Add debugfs for requesting HDCP version URL : https://patchwork.freedesktop.org/series/78115/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Mon Jun 8 12:13:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 12:13:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgQWRk?= =?utf-8?q?_debugfs_for_requesting_HDCP_version?= In-Reply-To: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> Message-ID: <159161843367.14460.9985170755045706372@emeril.freedesktop.org> == Series Details == Series: Add debugfs for requesting HDCP version URL : https://patchwork.freedesktop.org/series/78115/ State : success == Summary == CI Bug Log - changes from CI_DRM_8600 -> Patchwork_17906 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/index.html Known issues ------------ Here are the changes found in Patchwork_17906 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-glk-dsi: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-whl-u: [DMESG-WARN][5] ([i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 41) ------------------------------ Missing (8): fi-ilk-m540 fi-bdw-samus fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-skl-6700k2 Build changes ------------- * Linux: CI_DRM_8600 -> Patchwork_17906 CI-20190529: 20190529 CI_DRM_8600: 9232911f67be3d072e5bd6ff0eb4d8e8281f5c5f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17906: e9aea7c387bfa3af005fbd439f664d6e902b3cf6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e9aea7c387bf drm/i915: Add a new debugfs to request HDCP version b610d6ebbfb3 drm/i915: Add support for considering HDCP ver requested via debugfs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/index.html From patchwork at emeril.freedesktop.org Mon Jun 8 12:41:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 12:41:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Prevent_enabling_breadcrumbs_on_the_virtual_engine?= In-Reply-To: <20200608102845.26194-1-chris@chris-wilson.co.uk> References: <20200608102845.26194-1-chris@chris-wilson.co.uk> Message-ID: <159162007126.14461.10250252616496160406@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Prevent enabling breadcrumbs on the virtual engine URL : https://patchwork.freedesktop.org/series/78117/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8600 -> Patchwork_17907 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17907 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17907, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17907: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-cfl-8109u/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-cfl-8109u/igt at i915_selftest@live at execlists.html - fi-skl-lmem: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-skl-lmem/igt at i915_selftest@live at execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-skl-lmem/igt at i915_selftest@live at execlists.html - fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-icl-u2/igt at i915_selftest@live at execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-icl-u2/igt at i915_selftest@live at execlists.html - fi-icl-y: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-icl-y/igt at i915_selftest@live at execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-icl-y/igt at i915_selftest@live at execlists.html - fi-bdw-5557u: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-bdw-5557u/igt at i915_selftest@live at execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-bdw-5557u/igt at i915_selftest@live at execlists.html - fi-icl-guc: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-icl-guc/igt at i915_selftest@live at execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-icl-guc/igt at i915_selftest@live at execlists.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at execlists: - {fi-tgl-u}: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-tgl-u/igt at i915_selftest@live at execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-tgl-u/igt at i915_selftest@live at execlists.html - {fi-kbl-7560u}: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-7560u/igt at i915_selftest@live at execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-kbl-7560u/igt at i915_selftest@live at execlists.html - {fi-tgl-dsi}: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-tgl-dsi/igt at i915_selftest@live at execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-tgl-dsi/igt at i915_selftest@live at execlists.html Known issues ------------ Here are the changes found in Patchwork_17907 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_selftest@live at active: - fi-cfl-8109u: [PASS][19] -> [DMESG-FAIL][20] ([i915#666]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-cfl-8109u/igt at i915_selftest@live at active.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-cfl-8109u/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][21] -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-x1275/igt at kms_busy@basic at flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-glk-dsi: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][29] ([i915#1982]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-icl-u2: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][33] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][34] ([i915#62] / [i915#92]) +3 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][35] ([i915#62] / [i915#92]) -> [DMESG-WARN][36] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8600 -> Patchwork_17907 CI-20190529: 20190529 CI_DRM_8600: 9232911f67be3d072e5bd6ff0eb4d8e8281f5c5f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17907: 8ff9f0d4f8c57c785111e79dfa298255fcae0b0b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8ff9f0d4f8c5 drm/i915/gt: Prevent enabling breadcrumbs on the virtual engine == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17907/index.html From andriy.shevchenko at linux.intel.com Mon Jun 8 12:51:56 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Mon, 8 Jun 2020 15:51:56 +0300 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-4-hdegoede@redhat.com> <20200608035023.GZ2428291@smile.fi.intel.com> <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> Message-ID: <20200608125156.GL2428291@smile.fi.intel.com> On Mon, Jun 08, 2020 at 01:07:12PM +0200, Hans de Goede wrote: > On 6/8/20 5:50 AM, Andy Shevchenko wrote: > > On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote: > > > When the user requests a high enough period ns value, then the > > > calculations in pwm_lpss_prepare() might result in a base_unit value of 0. > > > > > > But according to the data-sheet the way the PWM controller works is that > > > each input clock-cycle the base_unit gets added to a N bit counter and > > > that counter overflowing determines the PWM output frequency. Adding 0 > > > to the counter is a no-op. The data-sheet even explicitly states that > > > writing 0 to the base_unit bits will result in the PWM outputting a > > > continuous 0 signal. > > > > So, and why it's a problem? > > Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail > which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 = > 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will > now get a pin which is always outputting low. > > OTOH if we clamp to 1 as lowest value, the user will get 192000000 / 65536 > = 292 Hz as output frequency which is as close to the requested value as > we can get while actually still working as a PWM controller. So, we should basically divide and round up, no? At least for 0 we will get 0. > > > base_unit values > (base_unit_range / 256), or iow base_unit values using > > > the 8 most significant bits, cause loss of resolution of the duty-cycle. > > > E.g. assuming a base_unit_range of 65536 steps, then a base_unit value of > > > 768 (256 * 3), limits the duty-cycle resolution to 65536 / 768 = 85 steps. > > > Clamp the max base_unit value to base_unit_range / 32 to ensure a > > > duty-cycle resolution of at least 32 steps. This limits the maximum > > > output frequency to 600 KHz / 780 KHz depending on the base clock. > > > > This part I don't understand. Why we limiting base unit? I seems like a > > deliberate regression. > > The way the PWM controller works is that the base-unit gets added to > say a 16 bit (on CHT) counter each input clock and then the highest 8 > bits of that counter get compared to the value programmed into the > ON_TIME_DIV bits. > > Lets say we do not clamp and allow any value and lets say the user > selects an output frequency of half the input clock, so base-unit > value is 32768, then the counter will only have 2 values: > 0 and 32768 after that it will wrap around again. So any on time-div > value < 128 will result in the output being always high and any > value > 128 will result in the output being high/low 50% of the time > and a value of 255 will make the output always low. > > So in essence we now only have 3 duty cycle levels, which seems like > a bad idea to me / not what a pwm controller is supposed to do. It's exactly what is written in the documentation. I can't buy base unit clamp. Though, I can buy, perhaps, on time divisor granularity, i.e. 1/ 0% - 25%-1 (0%) 2/ 25% - 50% - 75% (50%) 3/ 75%+1 - 100% (100%) And so on till we got a maximum resolution (8 bits). -- With Best Regards, Andy Shevchenko From chris at chris-wilson.co.uk Mon Jun 8 12:54:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 8 Jun 2020 13:54:38 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Prevent enabling breadcrumbs on the virtual engine In-Reply-To: <20200608102845.26194-1-chris@chris-wilson.co.uk> References: <20200608102845.26194-1-chris@chris-wilson.co.uk> Message-ID: <20200608125438.28700-1-chris@chris-wilson.co.uk> The virtual engines are not connected directly to hardware, so do not generate interrupts themselves, nor do we expect to enable breadcrumb tracking on them. However, if we clear out a stale virtual request, we will process the breadcrumbs on the current virtual engine. Here, we only need to add the delayed signal onto the stale signal queue, and send the signal once clear of the engine locks. In the meantime, this may be transferred onto the next sibling if we execute the next virtual request before the work is completed. The effect of losing tracking of the virtual breadcrumb interrupt is that we leak the GT wakeref, keeping the device awake. Reported-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Fixes: b647c7df01b7 ("drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: <stable at vger.kernel.org> # v5.5+ --- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 6 ++++++ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +++ drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++ 3 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c index d907d538176e..9eaf3dc17c99 100644 --- a/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/gt/intel_breadcrumbs.c @@ -225,6 +225,9 @@ static bool __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b) struct intel_engine_cs *engine = container_of(b, struct intel_engine_cs, breadcrumbs); + if (intel_engine_is_virtual(engine)) + return true; + lockdep_assert_held(&b->irq_lock); if (b->irq_armed) return true; @@ -308,6 +311,9 @@ void intel_engine_transfer_stale_breadcrumbs(struct intel_engine_cs *engine, void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine) { + struct intel_breadcrumbs *b = &engine->breadcrumbs; + + GEM_BUG_ON(atomic_read(&b->irq_work.flags)); } bool i915_request_enable_breadcrumb(struct i915_request *rq) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e5141a897786..4f2c348aa32c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1515,6 +1515,9 @@ void intel_engine_dump(struct intel_engine_cs *engine, drm_printf(m, "*** WEDGED ***\n"); drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count)); + drm_printf(m, "\tBreadcrumbs? armed:%s, signalers:%s\n", + yesno(engine->breadcrumbs.irq_armed), + yesno(!list_empty(&engine->breadcrumbs.signalers))); drm_printf(m, "\tBarriers?: %s\n", yesno(!llist_empty(&engine->barrier_tasks))); drm_printf(m, "\tLatency: %luus\n", diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index d55a5e0466e5..9d932e985d96 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -5339,6 +5339,8 @@ static void virtual_context_destroy(struct kref *kref) GEM_BUG_ON(ve->request); GEM_BUG_ON(ve->context.inflight); + intel_engine_fini_breadcrumbs(&ve->base); + for (n = 0; n < ve->num_siblings; n++) { struct intel_engine_cs *sibling = ve->siblings[n]; struct rb_node *node = &ve->nodes[sibling->id].rb; -- 2.20.1 From andriy.shevchenko at linux.intel.com Mon Jun 8 12:55:42 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Mon, 8 Jun 2020 15:55:42 +0300 Subject: [Intel-gfx] [PATCH v2 04/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() In-Reply-To: <c8a8d466-9b4a-9021-ca74-01d315e99117@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-5-hdegoede@redhat.com> <20200608035512.GA2428291@smile.fi.intel.com> <c8a8d466-9b4a-9021-ca74-01d315e99117@redhat.com> Message-ID: <20200608125542.GM2428291@smile.fi.intel.com> On Mon, Jun 08, 2020 at 01:13:01PM +0200, Hans de Goede wrote: > On 6/8/20 5:55 AM, Andy Shevchenko wrote: > > On Sun, Jun 07, 2020 at 08:18:29PM +0200, Hans de Goede wrote: > > > According to the data-sheet the way the PWM controller works is that > > > each input clock-cycle the base_unit gets added to a N bit counter and > > > that counter overflowing determines the PWM output frequency. > > > > > > So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, > > > after 65535 input clock-cycles the counter has been increased from 0 to > > > 65535 and it will overflow on the next cycle, so it will overflow after > > > every 65536 clock cycles and thus the calculations done in > > > pwm_lpss_prepare() should use 65536 and not 65535. > > > > > > This commit fixes this. Note this also aligns the calculations in > > > pwm_lpss_prepare() with those in pwm_lpss_get_state(). > > > > This one sounds like a bug which I have noticed on Broxton (but thought as a > > hardware issue). In any case it has to be tested on various platforms to see > > how it affects on them. > > If you like at the datasheet / read my commit description then it > becomes obvious that because of the way the PWM controller works that > it takes the full 2^(base-unit-bits) for the counter to overflow, > not 2^(base-unit-bits) - 1. This will make a difference of a factor > 65535/65536 in the output frequency which will be tricky to measure. > > IOW I'm not sure we can really test if this helps, but it is > obviously the right thing to do and it aligns the pwm_apply code > with the pwm_get_state code which already does not have the - 1. Yes. It seems I did a mistake in the commit 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit") when missed multiplication. For this one Reviewed-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com> -- With Best Regards, Andy Shevchenko From patchwork at emeril.freedesktop.org Mon Jun 8 13:29:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 13:29:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Prevent_enabling_breadcrumbs_on_the_virtual_engine_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200608102845.26194-1-chris@chris-wilson.co.uk> References: <20200608102845.26194-1-chris@chris-wilson.co.uk> Message-ID: <159162297846.14463.11147241051382851777@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Prevent enabling breadcrumbs on the virtual engine (rev2) URL : https://patchwork.freedesktop.org/series/78117/ State : success == Summary == CI Bug Log - changes from CI_DRM_8600 -> Patchwork_17908 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/index.html Known issues ------------ Here are the changes found in Patchwork_17908 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-byt-j1900/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/fi-byt-j1900/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-glk-dsi: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8600 -> Patchwork_17908 CI-20190529: 20190529 CI_DRM_8600: 9232911f67be3d072e5bd6ff0eb4d8e8281f5c5f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17908: 0ed9d466630faf01b7a04c422587332f71fc9615 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0ed9d466630f drm/i915/gt: Prevent enabling breadcrumbs on the virtual engine == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/index.html From hdegoede at redhat.com Mon Jun 8 14:19:08 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Mon, 8 Jun 2020 16:19:08 +0200 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200608125156.GL2428291@smile.fi.intel.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-4-hdegoede@redhat.com> <20200608035023.GZ2428291@smile.fi.intel.com> <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> <20200608125156.GL2428291@smile.fi.intel.com> Message-ID: <ecb5ca16-91eb-d7b9-dbaf-ee18cb85d9f3@redhat.com> Hi, On 6/8/20 2:51 PM, Andy Shevchenko wrote: > On Mon, Jun 08, 2020 at 01:07:12PM +0200, Hans de Goede wrote: >> On 6/8/20 5:50 AM, Andy Shevchenko wrote: >>> On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote: >>>> When the user requests a high enough period ns value, then the >>>> calculations in pwm_lpss_prepare() might result in a base_unit value of 0. >>>> >>>> But according to the data-sheet the way the PWM controller works is that >>>> each input clock-cycle the base_unit gets added to a N bit counter and >>>> that counter overflowing determines the PWM output frequency. Adding 0 >>>> to the counter is a no-op. The data-sheet even explicitly states that >>>> writing 0 to the base_unit bits will result in the PWM outputting a >>>> continuous 0 signal. >>> >>> So, and why it's a problem? >> >> Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail >> which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 = >> 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will >> now get a pin which is always outputting low. >> >> OTOH if we clamp to 1 as lowest value, the user will get 192000000 / 65536 >> = 292 Hz as output frequency which is as close to the requested value as >> we can get while actually still working as a PWM controller. > > So, we should basically divide and round up, no? Yes, that will work for the low limit of base_unit but it will make all the other requested period values less accurate. > At least for 0 we will get 0. We're dealing with frequency here, but the API is dealing with period, so to get 0 HZ the API user would have to request a period of > 1s e.g. request 2s / 0.5 Hz but then the user is still not really requesting 0Hz (that would correspond with a period of infinity which integers cannot represent. >>>> base_unit values > (base_unit_range / 256), or iow base_unit values using >>>> the 8 most significant bits, cause loss of resolution of the duty-cycle. >>>> E.g. assuming a base_unit_range of 65536 steps, then a base_unit value of >>>> 768 (256 * 3), limits the duty-cycle resolution to 65536 / 768 = 85 steps. >>>> Clamp the max base_unit value to base_unit_range / 32 to ensure a >>>> duty-cycle resolution of at least 32 steps. This limits the maximum >>>> output frequency to 600 KHz / 780 KHz depending on the base clock. >>> >>> This part I don't understand. Why we limiting base unit? I seems like a >>> deliberate regression. >> >> The way the PWM controller works is that the base-unit gets added to >> say a 16 bit (on CHT) counter each input clock and then the highest 8 >> bits of that counter get compared to the value programmed into the >> ON_TIME_DIV bits. >> >> Lets say we do not clamp and allow any value and lets say the user >> selects an output frequency of half the input clock, so base-unit >> value is 32768, then the counter will only have 2 values: >> 0 and 32768 after that it will wrap around again. So any on time-div >> value < 128 will result in the output being always high and any >> value > 128 will result in the output being high/low 50% of the time >> and a value of 255 will make the output always low. >> >> So in essence we now only have 3 duty cycle levels, which seems like >> a bad idea to me / not what a pwm controller is supposed to do. > > It's exactly what is written in the documentation. I can't buy base unit clamp. > Though, I can buy, perhaps, on time divisor granularity, i.e. > 1/ 0% - 25%-1 (0%) > 2/ 25% - 50% - 75% (50%) > 3/ 75%+1 - 100% (100%) > And so on till we got a maximum resolution (8 bits). Note that the PWM API does not expose the granularity to the API user, which is why I went with just putting a minimum on it of 32 steps. Anyways I don't have a strong opinion on this, so I'm fine with not clamping the base-unit to preserve granularity. We should still clamp it to avoid overflow if the user us requesting a really high frequency though! The old code had: base_unit &= base_unit_range; Which means that if the user requests a too high value, then we first overflow base_unit and then truncate it to fit leading to a random frequency. So if we forget my minimal granularity argument, then at a minimum we need to replace the above line with: base_unit = clamp_t(unsigned long long, base_unit, 1, base_unit_range - 1); And since we need the clamp anyways we can then keep the current round-closest behavior. Regards, Hans From daniel at ffwll.ch Mon Jun 8 14:35:00 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Mon, 8 Jun 2020 16:35:00 +0200 Subject: [Intel-gfx] pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API In-Reply-To: <20200606202601.48410-1-hdegoede@redhat.com> References: <20200606202601.48410-1-hdegoede@redhat.com> Message-ID: <20200608143500.GX20149@phenom.ffwll.local> On Sat, Jun 06, 2020 at 10:25:45PM +0200, Hans de Goede wrote: > Hi All, > > This patch series converts the i915 driver's cpde for controlling the > panel's backlight with an external PWM controller to use the atomic PWM API. > > Initially the plan was for this series to consist of 2 parts: > 1. convert the pwm-crc driver to support the atomic PWM API and > 2. convert the i915 driver's PWM code to use the atomic PWM API. > > But during testing I've found a number of bugs in the pwm-lpss and I > found that the acpi_lpss code needs some special handling because of > some ugliness found in most Cherry Trail DSDTs. > > So now this series has grown somewhat large and consists of 4 parts: > > 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness > 2. various fixes to the pwm-lpss driver > 3. convert the pwm-crc driver to support the atomic PWM API and > 4. convert the i915 driver's PWM code to use the atomic PWM API > > So we need to discuss how to merge this (once it passes review). > Although the inter-dependencies are only runtime I still think we should > make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before > merging the i915 changes. Both to make sure that the intel-gfx CI system > does not become unhappy and for bisecting reasons. Simplest is if acpi acks the acpi patches for merging through drm-intel.git. Second simplest is topic branch (drm-intel maintainers can do that) with the entire pile, which then acpi and drm-intel can both pull in. Up to the two maintainer teams to figure this one out. /me out Cheers, Daniel > > The involved acpi_lpss and pwm drivers do not see a whole lot of churn, > so we could just merge everything through dinq, or we could use immutable > branch and merge those into dinq. > > So Rafael and Thierry, can I either get your Acked-by for directly merging > this into dinq, or can you provide an immutable branch with these patches? > > This series has been tested (and re-tested after adding various bug-fixes) > extensively. It has been tested on the following devices: > > -Asus T100TA BYT + CRC-PMIC PWM > -Toshiba WT8-A BYT + CRC-PMIC PWM > -Thundersoft TS178 BYT + CRC-PMIC PWM, inverse PWM > -Asus T100HA CHT + CRC-PMIC PWM > -Terra Pad 1061 BYT + LPSS PWM > -Trekstor Twin 10.1 BYT + LPSS PWM > -Asus T101HA CHT + CRC-PMIC PWM > -GPD Pocket CHT + CRC-PMIC PWM > > Regards, > > Hans > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From tzimmermann at suse.de Mon Jun 8 14:40:26 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Mon, 8 Jun 2020 16:40:26 +0200 Subject: [Intel-gfx] [PATCH 8/9] drm/shmem-helpers: Ensure get_pages is not called on imported dma-buf In-Reply-To: <20200603131209.GN20149@phenom.ffwll.local> References: <20200511093554.211493-1-daniel.vetter@ffwll.ch> <20200511093554.211493-9-daniel.vetter@ffwll.ch> <41b3f24c-de0c-9390-6b8c-e71ceadb6d07@suse.de> <20200603131209.GN20149@phenom.ffwll.local> Message-ID: <37f561a1-c0fc-57c9-4759-9fca5ae46a4d@suse.de> Hi Am 03.06.20 um 15:12 schrieb Daniel Vetter: > On Thu, May 14, 2020 at 09:30:04AM +0200, Thomas Zimmermann wrote: >> Hi >> >> Am 11.05.20 um 11:35 schrieb Daniel Vetter: >>> Just a bit of light paranoia. Also sprinkle this check over >>> drm_gem_shmem_get_sg_table, which should only be called when >>> exporting, same for the pin/unpin functions, on which it relies to >>> work correctly. >>> >>> Cc: Gerd Hoffmann <kraxel at redhat.com> >>> Cc: Rob Herring <robh at kernel.org> >>> Cc: Noralf Tr?nnes <noralf at tronnes.org> >>> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> >>> --- >>> drivers/gpu/drm/drm_gem_shmem_helper.c | 10 ++++++++++ >>> 1 file changed, 10 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c >>> index 117a7841e284..f7011338813e 100644 >>> --- a/drivers/gpu/drm/drm_gem_shmem_helper.c >>> +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c >>> @@ -170,6 +170,8 @@ int drm_gem_shmem_get_pages(struct drm_gem_shmem_object *shmem) >>> { >>> int ret; >>> >>> + WARN_ON(shmem->base.import_attach); >>> + >>> ret = mutex_lock_interruptible(&shmem->pages_lock); >>> if (ret) >>> return ret; >>> @@ -225,6 +227,8 @@ int drm_gem_shmem_pin(struct drm_gem_object *obj) >>> { >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); >>> >>> + WARN_ON(shmem->base.import_attach); >>> + >> >> I don't understand this change. If a driver pins pages it now has to >> check that the pages are not imported? > > Nope. There's two classes of functions in the helpers, and I'm trying to > unconfuse them: > > - stuff used to implement gem_funcs. These are obviously only ever used on > native objects, never on imported ones (on imported ones we try to > forward through the dma-buf layer to the exporter). drm_gem_shmem_pin is > only used in that role to implement gem_funcs->pin. Calling it on an > imported buffer is indeed a bug. > > - the other set of functions are for drivers to do their stuff. The > interface which (implicitly) pins stuff into places is various set of > get_pages, which do have different paths for native and imported > objects. Thanks for explaining. Patch is Acked-by: Thomas Zimmermann <tzimmermann at suse.de> > > Apologies that I missed your question here, I merged all the patches > leading up to this one for now. > > Thanks, Daniel > >> >> >>> return drm_gem_shmem_get_pages(shmem); >>> } >>> EXPORT_SYMBOL(drm_gem_shmem_pin); >>> @@ -240,6 +244,8 @@ void drm_gem_shmem_unpin(struct drm_gem_object *obj) >>> { >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); >>> >>> + WARN_ON(shmem->base.import_attach); >>> + >>> drm_gem_shmem_put_pages(shmem); >>> } >>> EXPORT_SYMBOL(drm_gem_shmem_unpin); >>> @@ -510,6 +516,8 @@ static void drm_gem_shmem_vm_open(struct vm_area_struct *vma) >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); >>> int ret; >>> >>> + WARN_ON(shmem->base.import_attach); >>> + >>> ret = drm_gem_shmem_get_pages(shmem); >>> WARN_ON_ONCE(ret != 0); >>> >>> @@ -611,6 +619,8 @@ struct sg_table *drm_gem_shmem_get_sg_table(struct drm_gem_object *obj) >>> { >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); >>> >>> + WARN_ON(shmem->base.import_attach); >>> + >>> return drm_prime_pages_to_sg(shmem->pages, obj->size >> PAGE_SHIFT); >>> } >>> EXPORT_SYMBOL_GPL(drm_gem_shmem_get_sg_table); >>> >> >> -- >> Thomas Zimmermann >> Graphics Driver Developer >> SUSE Software Solutions Germany GmbH >> Maxfeldstr. 5, 90409 N?rnberg, Germany >> (HRB 36809, AG N?rnberg) >> Gesch?ftsf?hrer: Felix Imend?rffer >> > > > > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N?rnberg, Germany (HRB 36809, AG N?rnberg) Gesch?ftsf?hrer: Felix Imend?rffer -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200608/b9997a93/attachment-0001.sig> From patchwork at emeril.freedesktop.org Mon Jun 8 14:53:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 14:53:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgQWRk?= =?utf-8?q?_debugfs_for_requesting_HDCP_version?= In-Reply-To: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> Message-ID: <159162800612.14462.12789990534083398144@emeril.freedesktop.org> == Series Details == Series: Add debugfs for requesting HDCP version URL : https://patchwork.freedesktop.org/series/78115/ State : success == Summary == CI Bug Log - changes from CI_DRM_8600_full -> Patchwork_17906_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17906_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_softpin@noreloc-s3: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl6/igt at gem_softpin@noreloc-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-apl4/igt at gem_softpin@noreloc-s3.html * igt at i915_module_load@reload-with-fault-injection: - shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb8/igt at i915_module_load@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-iclb5/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb4/igt at i915_pm_dc@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-iclb4/igt at i915_pm_dc@dc6-psr.html - shard-skl: [PASS][7] -> [DMESG-FAIL][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl6/igt at i915_pm_dc@dc6-psr.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl7/igt at i915_pm_dc@dc6-psr.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl3/igt at kms_color@pipe-c-ctm-blue-to-red.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-kbl3/igt at kms_color@pipe-c-ctm-blue-to-red.html - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#95]) +15 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl4/igt at kms_color@pipe-c-ctm-blue-to-red.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-apl6/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_cursor_legacy@cursora-vs-flipa-atomic-transitions: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl6/igt at kms_cursor_legacy@cursora-vs-flipa-atomic-transitions.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl7/igt at kms_cursor_legacy@cursora-vs-flipa-atomic-transitions.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl2/igt at kms_hdr@bpc-switch.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl10/igt at kms_hdr@bpc-switch.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-kbl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-iclb4/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([i915#155]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-kbl4/igt at kms_vblank@pipe-b-ts-continuation-suspend.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][23] ([i915#1930]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-queues-priority-all: - shard-glk: [DMESG-WARN][25] ([i915#118] / [i915#95]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk2/igt at gem_exec_whisper@basic-queues-priority-all.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-glk5/igt at gem_exec_whisper@basic-queues-priority-all.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [INCOMPLETE][27] ([i915#1436] / [i915#716]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl5/igt at gen9_exec_parse@allowed-single.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl7/igt at gen9_exec_parse@allowed-single.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][29] ([i915#402]) -> [PASS][30] +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb8/igt at i915_module_load@reload.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-tglb2/igt at i915_module_load@reload.html * igt at i915_module_load@reload-with-fault-injection: - shard-skl: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +8 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl7/igt at i915_module_load@reload-with-fault-injection.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl5/igt at i915_module_load@reload-with-fault-injection.html * {igt at kms_flip@2x-flip-vs-expired-vblank at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][33] ([i915#79]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank at bc-hdmi-a1-hdmi-a2.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-edp1}: - shard-skl: [INCOMPLETE][35] ([i915#198]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl1/igt at kms_flip@flip-vs-suspend-interruptible at a-edp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl9/igt at kms_flip@flip-vs-suspend-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-tglb: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][39] ([i915#1188]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][41] ([fdo#108145] / [i915#265]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +7 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][45] ([i915#173]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb1/igt at kms_psr@no_drrs.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-iclb6/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl6/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-apl2/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at kms_vblank@pipe-c-accuracy-idle: - shard-glk: [FAIL][51] ([i915#43]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk5/igt at kms_vblank@pipe-c-accuracy-idle.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-glk9/igt at kms_vblank@pipe-c-accuracy-idle.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl2/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-kbl2/igt at kms_vblank@pipe-c-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][55] ([i915#1542]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb3/igt at perf@blocking-parameterized.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-iclb3/igt at perf@blocking-parameterized.html - shard-tglb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb1/igt at perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-tglb2/igt at perf@blocking-parameterized.html * igt at syncobj_wait@multi-wait-for-submit-unsubmitted: - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-kbl2/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html * igt at testdisplay: - shard-kbl: [DMESG-WARN][61] ([i915#165] / [i915#78]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl2/igt at testdisplay.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-kbl2/igt at testdisplay.html #### Warnings #### * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][63] ([i915#1319]) -> [TIMEOUT][64] ([i915#1319] / [i915#1635]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl2/igt at kms_content_protection@lic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-apl1/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][65] ([i915#1319] / [i915#1635]) -> [FAIL][66] ([fdo#110321]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl4/igt at kms_content_protection@srm.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-apl6/igt at kms_content_protection@srm.html * igt at kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-apl: [DMESG-WARN][67] ([i915#95]) -> [DMESG-FAIL][68] ([i915#54] / [i915#95]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl8/igt at kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/shard-apl8/igt at kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8600 -> Patchwork_17906 CI-20190529: 20190529 CI_DRM_8600: 9232911f67be3d072e5bd6ff0eb4d8e8281f5c5f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17906: e9aea7c387bfa3af005fbd439f664d6e902b3cf6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17906/index.html From daniel at ffwll.ch Mon Jun 8 15:04:10 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Mon, 8 Jun 2020 17:04:10 +0200 Subject: [Intel-gfx] [PATCH 8/9] drm/shmem-helpers: Ensure get_pages is not called on imported dma-buf In-Reply-To: <37f561a1-c0fc-57c9-4759-9fca5ae46a4d@suse.de> References: <20200511093554.211493-1-daniel.vetter@ffwll.ch> <20200511093554.211493-9-daniel.vetter@ffwll.ch> <41b3f24c-de0c-9390-6b8c-e71ceadb6d07@suse.de> <20200603131209.GN20149@phenom.ffwll.local> <37f561a1-c0fc-57c9-4759-9fca5ae46a4d@suse.de> Message-ID: <20200608150410.GY20149@phenom.ffwll.local> On Mon, Jun 08, 2020 at 04:40:26PM +0200, Thomas Zimmermann wrote: > Hi > > Am 03.06.20 um 15:12 schrieb Daniel Vetter: > > On Thu, May 14, 2020 at 09:30:04AM +0200, Thomas Zimmermann wrote: > >> Hi > >> > >> Am 11.05.20 um 11:35 schrieb Daniel Vetter: > >>> Just a bit of light paranoia. Also sprinkle this check over > >>> drm_gem_shmem_get_sg_table, which should only be called when > >>> exporting, same for the pin/unpin functions, on which it relies to > >>> work correctly. > >>> > >>> Cc: Gerd Hoffmann <kraxel at redhat.com> > >>> Cc: Rob Herring <robh at kernel.org> > >>> Cc: Noralf Tr?nnes <noralf at tronnes.org> > >>> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > >>> --- > >>> drivers/gpu/drm/drm_gem_shmem_helper.c | 10 ++++++++++ > >>> 1 file changed, 10 insertions(+) > >>> > >>> diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > >>> index 117a7841e284..f7011338813e 100644 > >>> --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > >>> +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > >>> @@ -170,6 +170,8 @@ int drm_gem_shmem_get_pages(struct drm_gem_shmem_object *shmem) > >>> { > >>> int ret; > >>> > >>> + WARN_ON(shmem->base.import_attach); > >>> + > >>> ret = mutex_lock_interruptible(&shmem->pages_lock); > >>> if (ret) > >>> return ret; > >>> @@ -225,6 +227,8 @@ int drm_gem_shmem_pin(struct drm_gem_object *obj) > >>> { > >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > >>> > >>> + WARN_ON(shmem->base.import_attach); > >>> + > >> > >> I don't understand this change. If a driver pins pages it now has to > >> check that the pages are not imported? > > > > Nope. There's two classes of functions in the helpers, and I'm trying to > > unconfuse them: > > > > - stuff used to implement gem_funcs. These are obviously only ever used on > > native objects, never on imported ones (on imported ones we try to > > forward through the dma-buf layer to the exporter). drm_gem_shmem_pin is > > only used in that role to implement gem_funcs->pin. Calling it on an > > imported buffer is indeed a bug. > > > > - the other set of functions are for drivers to do their stuff. The > > interface which (implicitly) pins stuff into places is various set of > > get_pages, which do have different paths for native and imported > > objects. > > Thanks for explaining. Patch is Thanks for taking a look at all this, last 2 patches now also merged to drm-misc-next. -Daniel > > Acked-by: Thomas Zimmermann <tzimmermann at suse.de> > > > > > Apologies that I missed your question here, I merged all the patches > > leading up to this one for now. > > > > Thanks, Daniel > > > >> > >> > >>> return drm_gem_shmem_get_pages(shmem); > >>> } > >>> EXPORT_SYMBOL(drm_gem_shmem_pin); > >>> @@ -240,6 +244,8 @@ void drm_gem_shmem_unpin(struct drm_gem_object *obj) > >>> { > >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > >>> > >>> + WARN_ON(shmem->base.import_attach); > >>> + > >>> drm_gem_shmem_put_pages(shmem); > >>> } > >>> EXPORT_SYMBOL(drm_gem_shmem_unpin); > >>> @@ -510,6 +516,8 @@ static void drm_gem_shmem_vm_open(struct vm_area_struct *vma) > >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > >>> int ret; > >>> > >>> + WARN_ON(shmem->base.import_attach); > >>> + > >>> ret = drm_gem_shmem_get_pages(shmem); > >>> WARN_ON_ONCE(ret != 0); > >>> > >>> @@ -611,6 +619,8 @@ struct sg_table *drm_gem_shmem_get_sg_table(struct drm_gem_object *obj) > >>> { > >>> struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); > >>> > >>> + WARN_ON(shmem->base.import_attach); > >>> + > >>> return drm_prime_pages_to_sg(shmem->pages, obj->size >> PAGE_SHIFT); > >>> } > >>> EXPORT_SYMBOL_GPL(drm_gem_shmem_get_sg_table); > >>> > >> > >> -- > >> Thomas Zimmermann > >> Graphics Driver Developer > >> SUSE Software Solutions Germany GmbH > >> Maxfeldstr. 5, 90409 N?rnberg, Germany > >> (HRB 36809, AG N?rnberg) > >> Gesch?ftsf?hrer: Felix Imend?rffer > >> > > > > > > > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 N?rnberg, Germany > (HRB 36809, AG N?rnberg) > Gesch?ftsf?hrer: Felix Imend?rffer > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Mon Jun 8 15:38:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 15:38:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Prevent_enabling_breadcrumbs_on_the_virtual_engine_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200608102845.26194-1-chris@chris-wilson.co.uk> References: <20200608102845.26194-1-chris@chris-wilson.co.uk> Message-ID: <159163070515.14461.13450229371225632460@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Prevent enabling breadcrumbs on the virtual engine (rev2) URL : https://patchwork.freedesktop.org/series/78117/ State : success == Summary == CI Bug Log - changes from CI_DRM_8600_full -> Patchwork_17908_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17908_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_create@forked: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk4/igt at gem_exec_create@forked.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-glk5/igt at gem_exec_create@forked.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb4/igt at i915_pm_dc@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-iclb2/igt at i915_pm_dc@dc6-psr.html - shard-skl: [PASS][7] -> [DMESG-FAIL][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl6/igt at i915_pm_dc@dc6-psr.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl4/igt at i915_pm_dc@dc6-psr.html * igt at i915_suspend@fence-restore-untiled: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#69]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl1/igt at i915_suspend@fence-restore-untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl3/igt at i915_suspend@fence-restore-untiled.html * igt at kms_big_fb@y-tiled-32bpp-rotate-180: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +9 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl9/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl2/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl3/igt at kms_color@pipe-c-ctm-blue-to-red.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-kbl1/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl6/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl1/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb1/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-iclb3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html * igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#52] / [i915#54]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl3/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl9/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-glk: [PASS][21] -> [FAIL][22] ([i915#64]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk2/igt at kms_fbcon_fbt@fbc-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-glk9/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#95]) +22 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb5/igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl2/igt at kms_hdr@bpc-switch.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl3/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-iclb4/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][37] -> [INCOMPLETE][38] ([i915#155]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-kbl2/igt at kms_vblank@pipe-b-ts-continuation-suspend.html #### Possible fixes #### * {igt at gem_ctx_isolation@preservation-s3 at bcs0}: - shard-skl: [INCOMPLETE][39] ([i915#198]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl4/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl5/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [INCOMPLETE][41] ([i915#1436] / [i915#716]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl5/igt at gen9_exec_parse@allowed-single.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl4/igt at gen9_exec_parse@allowed-single.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][43] ([i915#402]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb8/igt at i915_module_load@reload.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-tglb1/igt at i915_module_load@reload.html * igt at i915_module_load@reload-with-fault-injection: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +8 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-skl7/igt at i915_module_load@reload-with-fault-injection.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-skl10/igt at i915_module_load@reload-with-fault-injection.html * {igt at kms_flip@2x-flip-vs-expired-vblank at bc-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][47] ([i915#79]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank at bc-hdmi-a1-hdmi-a2.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank at bc-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1}: - shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb6/igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-tglb2/igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][53] ([i915#95]) -> [PASS][54] +20 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-apl3/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][55] ([i915#173]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb1/igt at kms_psr@no_drrs.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-iclb6/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-iclb4/igt at kms_psr@psr2_no_drrs.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-iclb2/igt at kms_psr@psr2_no_drrs.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-apl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl6/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-apl3/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at kms_vblank@pipe-c-accuracy-idle: - shard-glk: [FAIL][61] ([i915#43]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-glk5/igt at kms_vblank@pipe-c-accuracy-idle.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-glk5/igt at kms_vblank@pipe-c-accuracy-idle.html * {igt at perf@blocking-parameterized}: - shard-tglb: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-tglb1/igt at perf@blocking-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-tglb6/igt at perf@blocking-parameterized.html * igt at syncobj_wait@multi-wait-for-submit-unsubmitted: - shard-kbl: [DMESG-WARN][65] ([i915#93] / [i915#95]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-kbl6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html * igt at testdisplay: - shard-kbl: [DMESG-WARN][67] ([i915#165] / [i915#78]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl2/igt at testdisplay.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-kbl4/igt at testdisplay.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][69] ([i915#1319]) -> [DMESG-FAIL][70] ([fdo#110321] / [i915#95]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-kbl7/igt at kms_content_protection@atomic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-kbl2/igt at kms_content_protection@atomic.html - shard-apl: [DMESG-FAIL][71] ([fdo#110321] / [i915#95]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl3/igt at kms_content_protection@atomic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8600/shard-apl4/igt at kms_content_protection@srm.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/shard-apl7/igt at kms_content_protection@srm.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8600 -> Patchwork_17908 CI-20190529: 20190529 CI_DRM_8600: 9232911f67be3d072e5bd6ff0eb4d8e8281f5c5f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17908: 0ed9d466630faf01b7a04c422587332f71fc9615 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17908/index.html From ckoenig.leichtzumerken at gmail.com Mon Jun 8 15:15:50 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?q?Christian=20K=C3=B6nig?=) Date: Mon, 8 Jun 2020 17:15:50 +0200 Subject: [Intel-gfx] [PATCH] drm/mm: remove invalid entry based optimization Message-ID: <20200608151550.1315-1-christian.koenig@amd.com> When the current entry is rejected as candidate for the search it does not mean that we can abort the subtree search. It is perfectly possible that only the alignment, but not the size is the reason for the rejection. Signed-off-by: Christian K?nig <christian.koenig at amd.com> --- drivers/gpu/drm/drm_mm.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 60e9a9c91e9d..82d2888eb7fe 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -406,8 +406,7 @@ next_hole_high_addr(struct drm_mm_node *entry, u64 size) parent_rb_node = rb_parent(rb_node); left_node = rb_entry(left_rb_node, struct drm_mm_node, rb_hole_addr); - if ((left_node->subtree_max_hole < size || - HOLE_SIZE(entry) == entry->subtree_max_hole) && + if (left_node->subtree_max_hole < size && parent_rb_node && parent_rb_node->rb_left != rb_node) return rb_hole_addr_to_node(parent_rb_node); } @@ -446,8 +445,7 @@ next_hole_low_addr(struct drm_mm_node *entry, u64 size) parent_rb_node = rb_parent(rb_node); right_node = rb_entry(right_rb_node, struct drm_mm_node, rb_hole_addr); - if ((right_node->subtree_max_hole < size || - HOLE_SIZE(entry) == entry->subtree_max_hole) && + if (right_node->subtree_max_hole < size && parent_rb_node && parent_rb_node->rb_right != rb_node) return rb_hole_addr_to_node(parent_rb_node); } -- 2.17.1 From dhowells at redhat.com Mon Jun 8 16:52:06 2020 From: dhowells at redhat.com (David Howells) Date: Mon, 08 Jun 2020 17:52:06 +0100 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver In-Reply-To: <87ftb6x7em.fsf@intel.com> References: <87ftb6x7em.fsf@intel.com> <2136072.1591491984@warthog.procyon.org.uk> <87o8puxak1.fsf@intel.com> <4ff2445aff8d44c5961a6d194a8f4663@intel.com> Message-ID: <2715545.1591635126@warthog.procyon.org.uk> Jani Nikula <jani.nikula at linux.intel.com> wrote: > David, please try [1]. Assuming you mean this: https://patchwork.freedesktop.org/patch/366958/?series=77635&rev=1 yes, that works. Tested-by: David Howells <dhowells at redhat.com> From jose.souza at intel.com Mon Jun 8 16:52:15 2020 From: jose.souza at intel.com (Souza, Jose) Date: Mon, 8 Jun 2020 16:52:15 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/display: Avoid PSR and FBC features concurently. In-Reply-To: <20200608065635.11652-1-jason.v.le@intel.com> References: <20200608065635.11652-1-jason.v.le@intel.com> Message-ID: <50226b9506d36031402fa3ba73e90ec9f5a5ad38.camel@intel.com> On Sun, 2020-06-07 at 23:56 -0700, Jason Le wrote: > Issue: Enble both PSR and FBC caused some fickers on some eDP panels (eg. Panel GIS > 13.5" QHD Glare NE135FBM-N41/NC135GFL02). Disbling either PSR or FBC > will solve this flicker issue. > > Both PSR and FBC features save power when render is not busy. When PSR is > active, saving power achieved by source turning off source transmitter and main link, > putting memory on self-refresh mode. Therefore with PSR enabled, > FBC role is minimized since PSR power saving already covers most what > FBC does. Disabling FBC in case to avoid conflict between PSR and FBC > which causes display anomaly in some scenarios. The combination of both saves even more power so no to this, we should fix the issue not disable features because of a single panel having issues. A PSR2 fix was merged yesterday "drm/i915/psr: Program default IO buffer Wake and Fast Wake" try with that, if just that don't fix try set psr_safest_params=1. If this do not helps, please file a bug, add debug information and then we proceed from that. > > Tests: > Booted system with PSR enabled, verified FBC disabled. > Disabled PSR with disabled (i915.enable_psr=0), verified FBC enabled. > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++ > drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index 1c26673acb2d..52bc7483adb5 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1419,6 +1419,12 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) > drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", > i915_modparams.enable_fbc); > > + if (i915_modparams.enable_psr) { > + i915_modparams.enable_fbc = 0; > + DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n"); > + } > + > + > if (!HAS_FBC(dev_priv)) { > fbc->no_fbc_reason = "unsupported by this chipset"; > return; > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index b7a2c102648a..25accfdd5ad3 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1439,8 +1439,10 @@ void intel_psr_init(struct drm_i915_private *dev_priv) > if (!HAS_PSR(dev_priv)) > return; > > - if (!dev_priv->psr.sink_support) > + if (!dev_priv->psr.sink_support) { > + i915_modparams.enable_psr = 0; > return; > + } > > if (IS_HASWELL(dev_priv)) > /* From patchwork at emeril.freedesktop.org Mon Jun 8 16:57:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 16:57:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/mm=3A_remove_invalid_entry_based_optimization?= In-Reply-To: <20200608151550.1315-1-christian.koenig@amd.com> References: <20200608151550.1315-1-christian.koenig@amd.com> Message-ID: <159163543916.14460.3018785943446285355@emeril.freedesktop.org> == Series Details == Series: drm/mm: remove invalid entry based optimization URL : https://patchwork.freedesktop.org/series/78125/ State : warning == Summary == $ dim checkpatch origin/drm-tip 700bb6db2857 drm/mm: remove invalid entry based optimization -:40: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author '"Christian K?nig" <ckoenig.leichtzumerken at gmail.com>' total: 0 errors, 1 warnings, 0 checks, 18 lines checked From patchwork at emeril.freedesktop.org Mon Jun 8 17:18:45 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 17:18:45 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/mm=3A_remove_invalid_entry_based_optimization?= In-Reply-To: <20200608151550.1315-1-christian.koenig@amd.com> References: <20200608151550.1315-1-christian.koenig@amd.com> Message-ID: <159163672541.14461.7463070000831969690@emeril.freedesktop.org> == Series Details == Series: drm/mm: remove invalid entry based optimization URL : https://patchwork.freedesktop.org/series/78125/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601 -> Patchwork_17909 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/index.html Known issues ------------ Here are the changes found in Patchwork_17909 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@basic-rte: - fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][17] ([fdo#109271]) -> [DMESG-FAIL][18] ([i915#62]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-connector-state: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 42) ------------------------------ Missing (7): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17909 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17909: 700bb6db28575c5fa67d7d0ef0597850f4ecaad1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 700bb6db2857 drm/mm: remove invalid entry based optimization == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/index.html From rodrigo.vivi at intel.com Mon Jun 8 17:46:53 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Mon, 8 Jun 2020 10:46:53 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c Message-ID: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Alexandre Oliva has recently removed these files from Linux Libre with concerns that the sources weren't available. The sources are available on IGT repository, and only open source tools are used to generate the {ivb,hsw}_clear_kernel.c files. However, the remaining concern from Alexandre Oliva was around GPL license and the source not been present when distributing the code. So, it looks like 2 alternatives are possible, the use of linux-firmware.git repository to store the blob or making sure that the source is also present in our tree. Since the goal is to limit the i915 firmware to only the micro-controller blobs let's make sure that we do include the asm sources here in our tree. Btw, I tried to have some diligence here and make sure that the asms that these commits are adding are truly the source for the mentioned files: ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm igt$ ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm Output file not specified - using default file "ivb-cb_assembled" Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" for i915 driver... igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c 5c5 < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC --- > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT 61c61 < }; --- > }; \ No newline at end of file igt$ ./scripts/generate_clear_kernel.sh -g hsw -m /hom e/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm Output file not specified - using default file "hsw-cb_assembled" Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" for i915 driver... igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c hsw_clear_kernel.c 5c5 < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC --- > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT 61c61 < }; --- > }; \ No newline at end of file Used IGT and Mesa master repositories from Fri Jun 5 2020) IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging the connector") Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with RADV_DEBUG=shaderstats") Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 -D gallium-drivers=iris -D prefix=/usr -D libdir=/usr/lib64/ -Dtools=intel -Dkulkan-drivers=intel && ninja -C build Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Cc: <stable at vger.kernel.org> # v5.7+ Cc: Alexandre Oliva <lxoliva at fsfla.org> Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula at intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> --- .../drm/i915/gt/shaders/clear_kernel/hsw.asm | 141 ++++++++++++++++++ .../drm/i915/gt/shaders/clear_kernel/ivb.asm | 139 +++++++++++++++++ 2 files changed, 280 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm new file mode 100644 index 000000000000..bc29baf22c61 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +/** + * Kernel name: hsw_clear_buf.asm + * + * Kernel for PAVP buffer clear. + * + * 1. Clear all 64 GRF registers assigned to the kernel with designated value; + * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears + * 512 bytes of Render Cache. + */ + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/** + * Curbe Format + * + * DW 1.0 - Block Offset to write Render Cache + * DW 1.1 [15:0] - Clear Word + * DW 1.2 - Delay iterations + * DW 1.3 - Enable Instrumentation (only for debug) + * DW 1.4 - Rsvd (intended for context ID) + * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount + * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) + * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count) + * + * Binding Table + * + * BTI 0: 2D Surface to help clear L3 (Render/Data Cache) + * BTI 1: Wait/Instrumentation Buffer + * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT) + * Expected to be initialized to 0 by driver/another kernel + * Layout: + * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS] + * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N + */ +add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */ +cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N }; +(+f0.0) jmpi(1) 352D { align1 WE_all 1N }; + +/** + * State Register has info on where this thread is running + * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + */ +mov(8) g3<1>UD 0x00000000UD { align1 1Q }; +shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N }; +and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */ +shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N }; +and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */ +mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N }; +add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */ +shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N }; +and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */ +mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N }; +add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */ + +mov(8) g5<1>UD 0x00000000UD { align1 1Q }; +and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N }; +mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N }; + +mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */ +mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */ +and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N }; + +/* Media block read to fetch current value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x02190001 + + render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q }; +add(1) g5<1>D g5<0,1,0>D 1D { align1 1N }; + +/* Media block write for updated value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q }; + +/* Delay thread for specified parameter */ +add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N }; +(+f0.0) jmpi(1) -32D { align1 WE_all 1N }; + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/* Initialize looping parameters */ +mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */ +mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */ + +/* Write 32x16 all "0" block */ +mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q }; +mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q }; +mov(2) g2<1>UD g1<2,2,1>UW { align1 1N }; +mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */ +and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N }; +mov(16) g3<1>UD 0x00000000UD { align1 1H }; +mov(16) g4<1>UD 0x00000000UD { align1 1H }; +mov(16) g5<1>UD 0x00000000UD { align1 1H }; +mov(16) g6<1>UD 0x00000000UD { align1 1H }; +mov(16) g7<1>UD 0x00000000UD { align1 1H }; +mov(16) g8<1>UD 0x00000000UD { align1 1H }; +mov(16) g9<1>UD 0x00000000UD { align1 1H }; +mov(16) g10<1>UD 0x00000000UD { align1 1H }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; +add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; + +/* Now, clear all GRF registers */ +add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N }; +mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H }; +add(1) a0<1>D a0<0,1,0>D 32D { align1 1N }; +(+f0.0) jmpi(1) -64D { align1 WE_all 1N }; + +/* Terminante the thread */ +sendc(8) null<1>UD g127<8,8,1>F 0x82000010 + thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT }; diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm new file mode 100644 index 000000000000..b21bc9489061 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +/** + * Kernel name: ivb_clear_buf.asm + * + * Kernel for PAVP buffer clear. + * + * 1. Clear all 64 GRF registers assigned to the kernel with designated value; + * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears + * 512 bytes of Render Cache. + */ + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/** + * Curbe Format + * + * DW 1.0 - Block Offset to write Render Cache + * DW 1.1 [15:0] - Clear Word + * DW 1.2 - Delay iterations + * DW 1.3 - Enable Instrumentation (only for debug) + * DW 1.4 - Rsvd (intended for context ID) + * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount + * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) + * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count) + * + * Binding Table + * + * BTI 0: 2D Surface to help clear L3 (Render/Data Cache) + * BTI 1: Wait/Instrumentation Buffer + * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT) + * Expected to be initialized to 0 by driver/another kernel + * Layout : + * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS] + * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N + */ +add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */ +cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N }; +(+f0.0) jmpi(1) 44D { align1 WE_all 1N }; + +/** + * State Register has info on where this thread is running + * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + */ +mov(8) g3<1>UD 0x00000000UD { align1 1Q }; +shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N }; +and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */ +shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N }; +and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */ +mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N }; +add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */ +shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N }; +and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */ +mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N }; +add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */ + +mov(8) g5<1>UD 0x00000000UD { align1 1Q }; +and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N }; +mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N }; + +mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */ +mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */ +and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N }; + +/* Media block read to fetch current value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x02190001 + render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q }; +add(1) g5<1>D g5<0,1,0>D 1D { align1 1N }; + +/* Media block write for updated value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q }; +/* Delay thread for specified parameter */ +add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N }; +(+f0.0) jmpi(1) -4D { align1 WE_all 1N }; + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/* Initialize looping parameters */ +mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */ +mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */ + +/* Write 32x16 all "0" block */ +mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q }; +mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q }; +mov(2) g2<1>UD g1<2,2,1>UW { align1 1N }; +mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */ +and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N }; +mov(16) g3<1>UD 0x00000000UD { align1 1H }; +mov(16) g4<1>UD 0x00000000UD { align1 1H }; +mov(16) g5<1>UD 0x00000000UD { align1 1H }; +mov(16) g6<1>UD 0x00000000UD { align1 1H }; +mov(16) g7<1>UD 0x00000000UD { align1 1H }; +mov(16) g8<1>UD 0x00000000UD { align1 1H }; +mov(16) g9<1>UD 0x00000000UD { align1 1H }; +mov(16) g10<1>UD 0x00000000UD { align1 1H }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; +add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; + +/* Now, clear all GRF registers */ +add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N }; +mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H }; +add(1) a0<1>D a0<0,1,0>D 32D { align1 1N }; +(+f0.0) jmpi(1) -8D { align1 WE_all 1N }; + +/* Terminante the thread */ +sendc(8) null<1>UD g127<8,8,1>F 0x82000010 + thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT }; -- 2.24.1 From patchwork at emeril.freedesktop.org Mon Jun 8 18:10:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 18:10:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915=3A_Include_asm_sources_for_=7Bivb=2C_hsw=7D=5Fclea?= =?utf-8?q?r=5Fkernel=2Ec?= In-Reply-To: <20200608174654.1400710-1-rodrigo.vivi@intel.com> References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Message-ID: <159163982023.14460.15899242034864996303@emeril.freedesktop.org> == Series Details == Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c URL : https://patchwork.freedesktop.org/series/78126/ State : warning == Summary == $ dim checkpatch origin/drm-tip 62de4aea38dc drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c -:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #26: ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm -:33: WARNING:USE_RELATIVE_PATH: use relative pathname instead of absolute in changelog text #33: igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c -:38: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #38: new file mode 100644 -:328: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s) total: 1 errors, 3 warnings, 0 checks, 280 lines checked From imre.deak at intel.com Mon Jun 8 18:10:23 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 8 Jun 2020 21:10:23 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors Message-ID: <20200608181023.11503-1-imre.deak@intel.com> DSC is not supported on DP MST streams so just return -EINVAL when reading/writing the i915_dsc_fec_support debugfs file for such connectors. This also fixes an OOPS, caused by the encoder->digport cast, which is not valid for MST encoders. Signed-off-by: Imre Deak <imre.deak at intel.com> --- .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 2b640d8ab9d2..ebca8e488d03 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); do { + struct intel_encoder *encoder; + try_again = false; ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) } else if (ret) { break; } - intel_dp = intel_attached_dp(to_intel_connector(connector)); + + encoder = intel_attached_encoder(to_intel_connector(connector)); + /* TODO: Add DSC support for MST streams */ + if (encoder->type == INTEL_OUTPUT_DP_MST) { + ret = -EINVAL; + break; + } + + intel_dp = &enc_to_dig_port(encoder)->dp; crtc_state = to_intel_crtc_state(crtc->state); + seq_printf(m, "DSC_Enabled: %s\n", yesno(crtc_state->dsc.compression_enable)); seq_printf(m, "DSC_Sink_Support: %s\n", @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, int ret; struct drm_connector *connector = ((struct seq_file *)file->private_data)->private; - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_encoder *encoder; if (len == 0) return 0; @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, drm_dbg(&i915->drm, "Got %s for DSC Enable\n", (dsc_enable) ? "true" : "false"); - intel_dp->force_dsc_en = dsc_enable; - *offp += len; - return len; + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); + + encoder = intel_attached_encoder(to_intel_connector(connector)); + /* TODO: Add DSC support for MST streams */ + if (encoder->type == INTEL_OUTPUT_DP_MST) { + ret = -EINVAL; + } else { + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; + *offp += len; + ret = len; + } + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return ret; } static int i915_dsc_fec_support_open(struct inode *inode, -- 2.23.1 From chris at chris-wilson.co.uk Mon Jun 8 18:11:28 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 08 Jun 2020 19:11:28 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c In-Reply-To: <20200608174654.1400710-1-rodrigo.vivi@intel.com> References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Message-ID: <159163988890.30073.8976615673203599761@build.alporthouse.com> Quoting Rodrigo Vivi (2020-06-08 18:46:53) > Alexandre Oliva has recently removed these files from Linux Libre > with concerns that the sources weren't available. > > The sources are available on IGT repository, and only open source > tools are used to generate the {ivb,hsw}_clear_kernel.c files. > > However, the remaining concern from Alexandre Oliva was around > GPL license and the source not been present when distributing > the code. > > So, it looks like 2 alternatives are possible, the use of > linux-firmware.git repository to store the blob or making sure > that the source is also present in our tree. Since the goal > is to limit the i915 firmware to only the micro-controller blobs > let's make sure that we do include the asm sources here in our tree. > > Btw, I tried to have some diligence here and make sure that the > asms that these commits are adding are truly the source for > the mentioned files: > > ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm > > igt$ ./scripts/generate_clear_kernel.sh -g ivb -m /home/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm > Output file not specified - using default file "ivb-cb_assembled" > > Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" for i915 driver... > > igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c ivb_clear_kernel.c > 5c5 > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC > --- > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT > 61c61 > < }; > --- > > }; > \ No newline at end of file > > igt$ ./scripts/generate_clear_kernel.sh -g hsw -m /hom > e/vivijim/intel/freedesktop.org/mesa/mesa/build/src/intel/tools/i965_asm > Output file not specified - using default file "hsw-cb_assembled" > > Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" for i915 driver... > > igt$ diff /home/vivijim/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c hsw_clear_kernel.c > 5c5 > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC > --- > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT > 61c61 > < }; > --- > > }; > \ No newline at end of file > > Used IGT and Mesa master repositories from Fri Jun 5 2020) > IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging the connector") > Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with RADV_DEBUG=shaderstats") > Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 -D gallium-drivers=iris -D prefix=/usr -D libdir=/usr/lib64/ -Dtools=intel -Dkulkan-drivers=intel && ninja -C build > > Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html > Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > Cc: <stable at vger.kernel.org> # v5.7+ > Cc: Alexandre Oliva <lxoliva at fsfla.org> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com> > Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Jani Nikula <jani.nikula at intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> > --- > .../drm/i915/gt/shaders/clear_kernel/hsw.asm | 141 ++++++++++++++++++ > .../drm/i915/gt/shaders/clear_kernel/ivb.asm | 139 +++++++++++++++++ > 2 files changed, 280 insertions(+) > create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm > create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm > > diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm > new file mode 100644 > index 000000000000..bc29baf22c61 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm > @@ -0,0 +1,141 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright ? 2020 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice (including the next > + * paragraph) shall be included in all copies or substantial portions of the > + * Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > + * DEALINGS IN THE SOFTWARE. You already said it was MIT, you don't need to duplicate the copyright statement. Should there not be instructions on how to generate the object code? shaders/readme? -Chris From patchwork at emeril.freedesktop.org Mon Jun 8 18:25:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 18:25:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/mm=3A_remove_invalid_entry_based_optimization?= In-Reply-To: <20200608151550.1315-1-christian.koenig@amd.com> References: <20200608151550.1315-1-christian.koenig@amd.com> Message-ID: <159164071835.14460.5444734701290930641@emeril.freedesktop.org> == Series Details == Series: drm/mm: remove invalid entry based optimization URL : https://patchwork.freedesktop.org/series/78125/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601_full -> Patchwork_17909_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17909_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@processes: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl5/igt at gem_ctx_persistence@processes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl6/igt at gem_ctx_persistence@processes.html * igt at gem_exec_whisper@basic-queues-priority-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk4/igt at gem_exec_whisper@basic-queues-priority-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-glk1/igt at gem_exec_whisper@basic-queues-priority-all.html * igt at gem_sync@basic-store-each: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +14 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at gem_sync@basic-store-each.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl1/igt at gem_sync@basic-store-each.html * igt at i915_module_load@reload: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb5/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-tglb6/igt at i915_module_load@reload.html * igt at i915_pm_dc@dc6-psr: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#454]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt at i915_pm_dc@dc6-psr.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl5/igt at i915_pm_dc@dc6-psr.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at i915_suspend@forcewake.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-kbl2/igt at i915_suspend@forcewake.html * igt at kms_big_fb@linear-16bpp-rotate-0: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl2/igt at kms_big_fb@linear-16bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl2/igt at kms_big_fb@linear-16bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-a-ctm-blue-to-red: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_color@pipe-a-ctm-blue-to-red.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl10/igt at kms_color@pipe-a-ctm-blue-to-red.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_color@pipe-c-ctm-blue-to-red.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-kbl1/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#173]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_psr@no_drrs.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-iclb3/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#165]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html #### Possible fixes #### * igt at gem_mmap_gtt@fault-concurrent: - shard-skl: [CRASH][31] -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at gem_mmap_gtt@fault-concurrent.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl2/igt at gem_mmap_gtt@fault-concurrent.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][33] ([i915#118] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-glk9/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions: - shard-hsw: [SKIP][37] ([fdo#109271]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw1/igt at kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-hsw6/igt at kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html * igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled: - shard-skl: [FAIL][39] ([i915#52] / [i915#54]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl9/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html * {igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][41] ([i915#1928]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-glk1/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1}: - shard-kbl: [FAIL][43] ([i915#79]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-kbl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * {igt at kms_flip@flip-vs-suspend at a-edp1}: - shard-skl: [INCOMPLETE][47] ([i915#198]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl8/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip_tiling@flip-y-tiled: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +5 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt at kms_flip_tiling@flip-y-tiled.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl10/igt at kms_flip_tiling@flip-y-tiled.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +17 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][57] ([fdo#109642] / [fdo#111068]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb8/igt at kms_psr2_su@page_flip.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][61] ([i915#1542]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at perf@blocking-parameterized.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-iclb3/igt at perf@blocking-parameterized.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw6/igt at perf@polling-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-hsw2/igt at perf@polling-parameterized.html * igt at syncobj_wait@multi-wait-all-for-submit-signaled: - shard-tglb: [DMESG-WARN][65] ([i915#402]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb3/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-tglb8/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html * igt at syncobj_wait@multi-wait-for-submit-unsubmitted: - shard-kbl: [DMESG-WARN][67] ([i915#93] / [i915#95]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-kbl1/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][69] ([i915#588]) -> [SKIP][70] ([i915#658]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-iclb3/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][71] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at kms_content_protection@atomic-dpms.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [FAIL][74] ([fdo#110321]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl6/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][75] ([i915#1319] / [i915#1635]) -> [TIMEOUT][76] ([i915#1319]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at kms_content_protection@srm.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-apl1/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][77] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#93] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17909 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17909: 700bb6db28575c5fa67d7d0ef0597850f4ecaad1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17909/index.html From imre.deak at intel.com Mon Jun 8 18:26:50 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 8 Jun 2020 21:26:50 +0300 Subject: [Intel-gfx] [PATCH v2] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200608181023.11503-1-imre.deak@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> Message-ID: <20200608182650.13642-1-imre.deak@intel.com> DSC is not supported on DP MST streams so just return -EINVAL when reading/writing the i915_dsc_fec_support debugfs file for such connectors. This also fixes an OOPS, caused by the encoder->digport cast, which is not valid for MST encoders. v2: - Check encoder, which is unset for an MST connector, before it gets enabled. Signed-off-by: Imre Deak <imre.deak at intel.com> --- .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 2b640d8ab9d2..9db6f7e0ccaa 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); do { + struct intel_encoder *encoder; + try_again = false; ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) } else if (ret) { break; } - intel_dp = intel_attached_dp(to_intel_connector(connector)); + + encoder = intel_attached_encoder(to_intel_connector(connector)); + /* TODO: Add DSC support for MST streams */ + if (encoder->type == INTEL_OUTPUT_DP_MST) { + ret = -EINVAL; + break; + } + + intel_dp = &enc_to_dig_port(encoder)->dp; crtc_state = to_intel_crtc_state(crtc->state); + seq_printf(m, "DSC_Enabled: %s\n", yesno(crtc_state->dsc.compression_enable)); seq_printf(m, "DSC_Sink_Support: %s\n", @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, int ret; struct drm_connector *connector = ((struct seq_file *)file->private_data)->private; - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_encoder *encoder; if (len == 0) return 0; @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, drm_dbg(&i915->drm, "Got %s for DSC Enable\n", (dsc_enable) ? "true" : "false"); - intel_dp->force_dsc_en = dsc_enable; - *offp += len; - return len; + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); + + encoder = intel_attached_encoder(to_intel_connector(connector)); + /* TODO: Add DSC support for MST streams */ + if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) { + ret = -EINVAL; + } else { + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; + *offp += len; + ret = len; + } + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return ret; } static int i915_dsc_fec_support_open(struct inode *inode, -- 2.23.1 From patchwork at emeril.freedesktop.org Mon Jun 8 18:32:01 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 18:32:01 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Include_asm_sources_for_=7Bivb=2C_hsw=7D=5Fclear=5Fker?= =?utf-8?q?nel=2Ec?= In-Reply-To: <20200608174654.1400710-1-rodrigo.vivi@intel.com> References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Message-ID: <159164112156.14461.14900445626245816367@emeril.freedesktop.org> == Series Details == Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c URL : https://patchwork.freedesktop.org/series/78126/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601 -> Patchwork_17910 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/index.html Known issues ------------ Here are the changes found in Patchwork_17910 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_busy@basic at flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-glk-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-glk-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@basic-rte: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][15] ([fdo#109271]) -> [FAIL][16] ([i915#665] / [i915#704]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-guc/igt at i915_pm_rpm@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-guc/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][17] ([fdo#109271]) -> [DMESG-FAIL][18] ([i915#62]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@force-connector-state: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17910 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17910: 62de4aea38dc75f707a33f6e1efc4d2a07498d33 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 62de4aea38dc drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/index.html From patchwork at emeril.freedesktop.org Mon Jun 8 18:58:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 18:58:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_the_i915=5Fdsc=5Ffec=5Fsupport_debugfs_file_for_DP?= =?utf-8?q?_MST_connectors_=28rev2=29?= In-Reply-To: <20200608181023.11503-1-imre.deak@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> Message-ID: <159164273779.14460.7000970053144125211@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors (rev2) URL : https://patchwork.freedesktop.org/series/78128/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601 -> Patchwork_17911 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/index.html Known issues ------------ Here are the changes found in Patchwork_17911 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-n2820/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@basic-rte: - fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@force-connector-state: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17911 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17911: 2c4524628e2260caff58cb7020b91497c3091394 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2c4524628e22 drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/index.html From patchwork at emeril.freedesktop.org Mon Jun 8 19:31:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 19:31:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Include_asm_sources_for_=7Bivb=2C_hsw=7D=5Fclear=5Fker?= =?utf-8?q?nel=2Ec?= In-Reply-To: <20200608174654.1400710-1-rodrigo.vivi@intel.com> References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Message-ID: <159164467038.14461.17451902862367673388@emeril.freedesktop.org> == Series Details == Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c URL : https://patchwork.freedesktop.org/series/78126/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601_full -> Patchwork_17910_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17910_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at rcs0: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl8/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl6/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html * igt at gem_exec_create@forked: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at gem_exec_create@forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk8/igt at gem_exec_create@forked.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb5/igt at i915_pm_dc@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb2/igt at i915_pm_dc@dc6-psr.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +7 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at i915_suspend@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl4/igt at i915_suspend@sysfs-reader.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl3/igt at kms_color@pipe-c-ctm-0-25.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_color@pipe-c-ctm-blue-to-red.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl7/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-hsw: [PASS][13] -> [INCOMPLETE][14] ([i915#61]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw8/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-hsw8/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +11 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb7/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_rmfb@rmfb-ioctl: - shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb1/igt at kms_rmfb@rmfb-ioctl.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-snb2/igt at kms_rmfb@rmfb-ioctl.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][23] ([i915#1930]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-queues-forked: - shard-glk: [DMESG-WARN][25] ([i915#118] / [i915#95]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk9/igt at gem_exec_whisper@basic-queues-forked.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk5/igt at gem_exec_whisper@basic-queues-forked.html * igt at gem_mmap_gtt@fault-concurrent: - shard-skl: [CRASH][27] -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at gem_mmap_gtt@fault-concurrent.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt at gem_mmap_gtt@fault-concurrent.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][29] ([i915#118] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk7/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-skl: [FAIL][31] ([i915#54]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +3 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * {igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][35] ([i915#1928]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-glk9/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1}: - shard-kbl: [FAIL][37] ([i915#79]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html * {igt at kms_flip@flip-vs-suspend at a-edp1}: - shard-skl: [INCOMPLETE][39] ([i915#198]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl2/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip_tiling@flip-y-tiled: - shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +9 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt at kms_flip_tiling@flip-y-tiled.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl4/igt at kms_flip_tiling@flip-y-tiled.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb8/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][45] ([i915#1188]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_lease@page_flip_implicit_plane: - shard-snb: [TIMEOUT][47] ([i915#1958]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt at kms_lease@page_flip_implicit_plane.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-snb2/igt at kms_lease@page_flip_implicit_plane.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +16 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl3/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +3 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb5/igt at kms_psr@psr2_primary_page_flip.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl2/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl6/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb8/igt at perf@blocking-parameterized.html * igt at syncobj_wait@multi-wait-all-for-submit-signaled: - shard-tglb: [DMESG-WARN][59] ([i915#402]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb3/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-tglb8/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][61] ([i915#588]) -> [SKIP][62] ([i915#658]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-iclb7/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_color@pipe-a-degamma: - shard-tglb: [FAIL][63] ([i915#1149] / [i915#1897]) -> [DMESG-FAIL][64] ([i915#1149] / [i915#402]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb7/igt at kms_color@pipe-a-degamma.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-tglb8/igt at kms_color@pipe-a-degamma.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][65] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][66] ([fdo#110321] / [i915#95]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_content_protection@atomic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][67] ([i915#1319]) -> [TIMEOUT][68] ([i915#1319] / [i915#1958]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_content_protection@legacy.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-kbl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][69] ([i915#1319] / [i915#1635]) -> [TIMEOUT][70] ([i915#1319]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at kms_content_protection@srm.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-skl: [FAIL][71] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][72] ([fdo#108145] / [i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt at kms_psr@suspend: - shard-snb: [TIMEOUT][73] ([i915#1958]) -> [SKIP][74] ([fdo#109271]) +2 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt at kms_psr@suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/shard-snb2/igt at kms_psr@suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17910 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17910: 62de4aea38dc75f707a33f6e1efc4d2a07498d33 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17910/index.html From patchwork at emeril.freedesktop.org Mon Jun 8 20:14:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 20:14:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_the_i915=5Fdsc=5Ffec=5Fsupport_debugfs_file_for_DP?= =?utf-8?q?_MST_connectors_=28rev2=29?= In-Reply-To: <20200608181023.11503-1-imre.deak@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> Message-ID: <159164729685.14460.7631286722864688615@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors (rev2) URL : https://patchwork.freedesktop.org/series/78128/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601_full -> Patchwork_17911_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17911_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_engines@idempotent: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb6/igt at gem_ctx_engines@idempotent.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-tglb2/igt at gem_ctx_engines@idempotent.html * igt at gem_exec_whisper@basic-queues-priority-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk4/igt at gem_exec_whisper@basic-queues-priority-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-glk7/igt at gem_exec_whisper@basic-queues-priority-all.html * igt at gem_sync@basic-store-each: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +11 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at gem_sync@basic-store-each.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-apl4/igt at gem_sync@basic-store-each.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at i915_suspend@forcewake.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-kbl2/igt at i915_suspend@forcewake.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-5: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl5/igt at kms_color@pipe-c-ctm-0-5.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl8/igt at kms_color@pipe-c-ctm-0-5.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_color@pipe-c-ctm-blue-to-red.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-kbl2/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][15] -> [FAIL][16] ([IGT#5]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl3/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl4/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt: - shard-snb: [PASS][19] -> [SKIP][20] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-snb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html * igt at kms_frontbuffer_tracking@fbc-stridechange: - shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk4/igt at kms_frontbuffer_tracking@fbc-stridechange.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-glk6/igt at kms_frontbuffer_tracking@fbc-stridechange.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl7/igt at kms_hdr@bpc-switch.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl6/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#69]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][33] -> [FAIL][34] ([i915#173]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_psr@no_drrs.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-iclb3/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-tglb: [PASS][37] -> [SKIP][38] ([i915#668]) +6 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb8/igt at kms_psr@psr2_cursor_plane_onoff.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-tglb6/igt at kms_psr@psr2_cursor_plane_onoff.html #### Possible fixes #### * igt at gem_mmap_gtt@fault-concurrent: - shard-skl: [CRASH][39] -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at gem_mmap_gtt@fault-concurrent.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl9/igt at gem_mmap_gtt@fault-concurrent.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-glk4/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-a-128x128-right-edge: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +10 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl3/igt at kms_cursor_edge_walk@pipe-a-128x128-right-edge.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl4/igt at kms_cursor_edge_walk@pipe-a-128x128-right-edge.html * igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled: - shard-skl: [FAIL][47] ([i915#52] / [i915#54]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl4/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html * {igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][49] ([i915#1928]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-glk9/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1}: - shard-kbl: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-kbl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-apl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-apl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * {igt at kms_flip@flip-vs-suspend at a-edp1}: - shard-skl: [INCOMPLETE][55] ([i915#198]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl1/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-iclb2/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [PASS][64] +12 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_psr@psr2_dpms: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb7/igt at kms_psr@psr2_dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-iclb2/igt at kms_psr@psr2_dpms.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [INCOMPLETE][67] ([i915#155]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl2/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-kbl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][69] ([i915#1542]) -> [PASS][70] +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at perf@blocking-parameterized.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-iclb2/igt at perf@blocking-parameterized.html * {igt at perf@polling-parameterized}: - shard-hsw: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw6/igt at perf@polling-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-hsw2/igt at perf@polling-parameterized.html * igt at syncobj_wait@multi-wait-all-for-submit-signaled: - shard-tglb: [DMESG-WARN][73] ([i915#402]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb3/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-tglb7/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][75] ([i915#588]) -> [SKIP][76] ([i915#658]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-iclb3/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][77] ([i915#454]) -> [SKIP][78] ([i915#468]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb3/igt at i915_pm_dc@dc6-psr.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][80] ([fdo#110321] / [i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_content_protection@atomic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-apl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][81] ([fdo#110321] / [fdo#110336]) -> [DMESG-FAIL][82] ([fdo#110321]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at kms_content_protection@atomic-dpms.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-apl1/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][83] ([i915#1319] / [i915#1635]) -> [TIMEOUT][84] ([i915#1319]) +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_content_protection@lic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][85] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][86] ([i915#93] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17911 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17911: 2c4524628e2260caff58cb7020b91497c3091394 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17911/index.html From khaled.almahallawy at intel.com Mon Jun 8 20:45:37 2020 From: khaled.almahallawy at intel.com (Khaled Almahallawy) Date: Mon, 8 Jun 2020 13:45:37 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/tc: fix the reset of ln0 Message-ID: <20200608204537.28468-1-khaled.almahallawy@intel.com> Setting ln0 similar to ln1 Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 96eaa4b39c68..1c0c369573e7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3025,7 +3025,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); } - ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); + ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); /* DPPATC */ -- 2.17.1 From mika.kuoppala at linux.intel.com Mon Jun 8 20:43:53 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 08 Jun 2020 23:43:53 +0300 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <20200607222108.14401-1-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> Message-ID: <87ftb59tkm.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Sentinels are supposed to be last reqeusts in the elsp queue, not the > only one, so adjust the assert accordingly. s/reqeusts/requests > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- > 1 file changed, 3 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index d55a5e0466e5..db8a170b0e5c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > ccid = ce->lrc.ccid; > > /* > - * Sentinels are supposed to be lonely so they flush the > - * current exection off the HW. Check that they are the > - * only request in the pending submission. > + * Sentinels are supposed to be the last request so they flush > + * the current exection off the HW. Check that they are the only s/exection/exeqution Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > + * request in the pending submission. > */ > if (sentinel) { > GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", > @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > port - execlists->pending); > return false; > } > - > sentinel = i915_request_has_sentinel(rq); > - if (sentinel && port != execlists->pending) { > - GEM_TRACE_ERR("%s: sentinel context:%llx not in prime position[%zd]\n", > - engine->name, > - ce->timeline->fence_context, > - port - execlists->pending); > - return false; > - } > > /* Hold tightly onto the lock to prevent concurrent retires! */ > if (!spin_trylock_irqsave(&rq->lock, flags)) > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From jose.souza at intel.com Mon Jun 8 20:53:14 2020 From: jose.souza at intel.com (Souza, Jose) Date: Mon, 8 Jun 2020 20:53:14 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/tc: fix the reset of ln0 In-Reply-To: <20200608204537.28468-1-khaled.almahallawy@intel.com> References: <20200608204537.28468-1-khaled.almahallawy@intel.com> Message-ID: <f45396c86bf9f0409a26ab543f253289db1acc3d.camel@intel.com> On Mon, 2020-06-08 at 13:45 -0700, Khaled Almahallawy wrote: > Setting ln0 similar to ln1 Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 96eaa4b39c68..1c0c369573e7 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3025,7 +3025,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, > ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); > } > > - ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); > + ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); > ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); > > /* DPPATC */ From mika.kuoppala at linux.intel.com Mon Jun 8 20:58:43 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 08 Jun 2020 23:58:43 +0300 Subject: [Intel-gfx] [PATCH 02/28] drm/i915/selftests: Make the hanging request non-preemptible In-Reply-To: <20200607222108.14401-2-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-2-chris@chris-wilson.co.uk> Message-ID: <87d0699svw.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > In some of our hangtests, we try to reset an active engine while it is > spinning inside the recursive spinner. However, we also try to flood the > engine with requests that preempt the hang, and so should disable the > preemption to be sure that we reset the right request. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 36 ++++++++++++++------ > 1 file changed, 26 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > index 4aa4cc917d8b..035f363fb0f8 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > @@ -203,12 +203,12 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) > *batch++ = lower_32_bits(hws_address(hws, rq)); > *batch++ = upper_32_bits(hws_address(hws, rq)); > *batch++ = rq->fence.seqno; > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > > memset(batch, 0, 1024); > batch += 1024 / sizeof(*batch); > > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; > *batch++ = lower_32_bits(vma->node.start); > *batch++ = upper_32_bits(vma->node.start); > @@ -217,12 +217,12 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) > *batch++ = 0; > *batch++ = lower_32_bits(hws_address(hws, rq)); > *batch++ = rq->fence.seqno; > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > > memset(batch, 0, 1024); > batch += 1024 / sizeof(*batch); > > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > *batch++ = MI_BATCH_BUFFER_START | 1 << 8; > *batch++ = lower_32_bits(vma->node.start); > } else if (INTEL_GEN(gt->i915) >= 4) { > @@ -230,24 +230,24 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine) > *batch++ = 0; > *batch++ = lower_32_bits(hws_address(hws, rq)); > *batch++ = rq->fence.seqno; > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > > memset(batch, 0, 1024); > batch += 1024 / sizeof(*batch); > > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > *batch++ = MI_BATCH_BUFFER_START | 2 << 6; > *batch++ = lower_32_bits(vma->node.start); > } else { > *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > *batch++ = lower_32_bits(hws_address(hws, rq)); > *batch++ = rq->fence.seqno; > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > > memset(batch, 0, 1024); > batch += 1024 / sizeof(*batch); > > - *batch++ = MI_ARB_CHECK; > + *batch++ = MI_NOOP; > *batch++ = MI_BATCH_BUFFER_START | 2 << 6; > *batch++ = lower_32_bits(vma->node.start); > } > @@ -866,13 +866,29 @@ static int __igt_reset_engines(struct intel_gt *gt, > count++; > > if (rq) { > + if (rq->fence.error != -EIO) { > + pr_err("i915_reset_engine(%s:%s):" > + " failed to reset request %llx:%lld\n", > + engine->name, test_name, > + rq->fence.context, > + rq->fence.seqno); > + i915_request_put(rq); > + > + GEM_TRACE_DUMP(); > + intel_gt_set_wedged(gt); > + err = -EIO; > + break; > + } > + > if (i915_request_wait(rq, 0, HZ / 5) < 0) { > struct drm_printer p = > drm_info_printer(gt->i915->drm.dev); > > pr_err("i915_reset_engine(%s:%s):" > - " failed to complete request after reset\n", > - engine->name, test_name); > + " failed to complete request %llx:%lld after reset\n", > + engine->name, test_name, > + rq->fence.context, > + rq->fence.seqno); > intel_engine_dump(engine, &p, > "%s\n", engine->name); > i915_request_put(rq); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From jose.souza at intel.com Mon Jun 8 21:05:29 2020 From: jose.souza at intel.com (Souza, Jose) Date: Mon, 8 Jun 2020 21:05:29 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/tc: fix the reset of ln0 In-Reply-To: <f45396c86bf9f0409a26ab543f253289db1acc3d.camel@intel.com> References: <20200608204537.28468-1-khaled.almahallawy@intel.com> <f45396c86bf9f0409a26ab543f253289db1acc3d.camel@intel.com> Message-ID: <5c975d8148a37edcd0627035d079aabb148f374b.camel@intel.com> On Mon, 2020-06-08 at 13:54 -0700, Jos? Roberto de Souza wrote: > On Mon, 2020-06-08 at 13:45 -0700, Khaled Almahallawy wrote: > > Setting ln0 similar to ln1 > Hum guess would good to have a Fixes tag to the patch adding the line fixed. > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 96eaa4b39c68..1c0c369573e7 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -3025,7 +3025,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, > > ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); > > } > > > > - ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); > > + ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); > > ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); > > > > /* DPPATC */ From sean at poorly.run Mon Jun 8 21:04:53 2020 From: sean at poorly.run (Sean Paul) Date: Mon, 8 Jun 2020 17:04:53 -0400 Subject: [Intel-gfx] [PATCH v5 03/13] drm/i915/utils: Replace dev_printk with drm helpers In-Reply-To: <20200608210505.48519-1-sean@poorly.run> References: <20200608210505.48519-1-sean@poorly.run> Message-ID: <20200608210505.48519-4-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Use drm logging helpers to add support for the upcoming tracefs implementation. Signed-off-by: Sean Paul <seanpaul at chromium.org> Changes in v5: -Added to the set --- drivers/gpu/drm/i915/i915_utils.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c index f42a9e9a0b4f..99499c0885cf 100644 --- a/drivers/gpu/drm/i915/i915_utils.c +++ b/drivers/gpu/drm/i915/i915_utils.c @@ -30,10 +30,9 @@ __i915_printk(struct drm_i915_private *dev_priv, const char *level, vaf.va = &args; if (is_error) - dev_printk(level, kdev, "%pV", &vaf); + drm_dev_printk(kdev, level, "%pV", &vaf); else - dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV", - __builtin_return_address(0), &vaf); + drm_err(&dev_priv->drm, "%pV", &vaf); va_end(args); -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Mon Jun 8 21:04:59 2020 From: sean at poorly.run (Sean Paul) Date: Mon, 8 Jun 2020 17:04:59 -0400 Subject: [Intel-gfx] [PATCH v5 09/13] drm/i915: Change infoframe debug checks to specify syslog In-Reply-To: <20200608210505.48519-1-sean@poorly.run> References: <20200608210505.48519-1-sean@poorly.run> Message-ID: <20200608210505.48519-10-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Since the logs protected by these checks specifically target syslog, use the new drm_debug_syslog_enabled() call to avoid triggering these prints when only trace is enabled. Signed-off-by: Sean Paul <seanpaul at chromium.org> Changes in v5: -Added to the set --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b16aca0fe5f0..de449755d1e5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -12876,7 +12876,7 @@ static void intel_dump_infoframe(struct drm_i915_private *dev_priv, const union hdmi_infoframe *frame) { - if (!drm_debug_enabled(DRM_UT_KMS)) + if (!drm_debug_syslog_enabled(DRM_UT_KMS)) return; hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame); @@ -13519,7 +13519,7 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, const union hdmi_infoframe *b) { if (fastset) { - if (!drm_debug_enabled(DRM_UT_KMS)) + if (!drm_debug_syslog_enabled(DRM_UT_KMS)) return; drm_dbg_kms(&dev_priv->drm, -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Mon Jun 8 21:05:02 2020 From: sean at poorly.run (Sean Paul) Date: Mon, 8 Jun 2020 17:05:02 -0400 Subject: [Intel-gfx] [PATCH v5 12/13] drm/i915: Use debug category printer for welcome message In-Reply-To: <20200608210505.48519-1-sean@poorly.run> References: <20200608210505.48519-1-sean@poorly.run> Message-ID: <20200608210505.48519-13-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> The welcome printer is meant to be gated on DRM_UT_DRIVER, so use the debug category printer to avoid dumping the message in the wrong place. Signed-off-by: Sean Paul <seanpaul at chromium.org> Changes in v5: -Added to the set --- drivers/gpu/drm/i915/i915_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 34ee12f3f02d..966212805ef7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -876,7 +876,8 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) static void i915_welcome_messages(struct drm_i915_private *dev_priv) { if (drm_debug_enabled(DRM_UT_DRIVER)) { - struct drm_printer p = drm_debug_printer("i915 device info:"); + struct drm_printer p = drm_debug_category_printer(DRM_UT_DRIVER, + "i915 device info:"); drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", INTEL_DEVID(dev_priv), -- Sean Paul, Software Engineer, Google / Chromium OS From patchwork at emeril.freedesktop.org Mon Jun 8 21:18:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 21:18:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tc=3A_fix_the_reset_of_ln0?= In-Reply-To: <20200608204537.28468-1-khaled.almahallawy@intel.com> References: <20200608204537.28468-1-khaled.almahallawy@intel.com> Message-ID: <159165111126.14461.2675349981492389486@emeril.freedesktop.org> == Series Details == Series: drm/i915/tc: fix the reset of ln0 URL : https://patchwork.freedesktop.org/series/78132/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601 -> Patchwork_17912 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/index.html Known issues ------------ Here are the changes found in Patchwork_17912 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] ([i915#62] / [i915#92] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_busy@basic at flip.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * igt at debugfs_test@read_all_entries: - fi-skl-6700k2: [{ABORT}][3] ([i915#1814]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-skl-6700k2/igt at debugfs_test@read_all_entries.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-skl-6700k2/igt at debugfs_test@read_all_entries.html * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@basic-rte: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-byt-j1900/igt at i915_pm_rpm@basic-rte.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17912 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17912: 737e451d926089f1b4b060add1c9ee07650074df @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 737e451d9260 drm/i915/tc: fix the reset of ln0 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/index.html From patchwork at emeril.freedesktop.org Mon Jun 8 22:17:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 08 Jun 2020 22:17:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/tc=3A_fix_the_reset_of_ln0?= In-Reply-To: <20200608204537.28468-1-khaled.almahallawy@intel.com> References: <20200608204537.28468-1-khaled.almahallawy@intel.com> Message-ID: <159165462706.14460.10339190541202498686@emeril.freedesktop.org> == Series Details == Series: drm/i915/tc: fix the reset of ln0 URL : https://patchwork.freedesktop.org/series/78132/ State : success == Summary == CI Bug Log - changes from CI_DRM_8601_full -> Patchwork_17912_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17912_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_create@forked: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at gem_exec_create@forked.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk6/igt at gem_exec_create@forked.html * igt at gem_sync@basic-store-each: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +11 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at gem_sync@basic-store-each.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl7/igt at gem_sync@basic-store-each.html * igt at i915_module_load@reload: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb5/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-tglb1/igt at i915_module_load@reload.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl3/igt at i915_suspend@debugfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@linear-16bpp-rotate-0: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl2/igt at kms_big_fb@linear-16bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl8/igt at kms_big_fb@linear-16bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb5/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_color@pipe-c-ctm-blue-to-red.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_draw_crc@draw-method-rgb565-blt-ytiled: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt at kms_draw_crc@draw-method-rgb565-blt-ytiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl8/igt at kms_draw_crc@draw-method-rgb565-blt-ytiled.html * igt at kms_frontbuffer_tracking@fbc-stridechange: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk4/igt at kms_frontbuffer_tracking@fbc-stridechange.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk6/igt at kms_frontbuffer_tracking@fbc-stridechange.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb4/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#69]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl3/igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend.html #### Possible fixes #### * {igt at gem_exec_reloc@basic-concurrent0}: - shard-glk: [FAIL][27] ([i915#1930]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-queues-forked: - shard-glk: [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk9/igt at gem_exec_whisper@basic-queues-forked.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk9/igt at gem_exec_whisper@basic-queues-forked.html * igt at gem_mmap_gtt@fault-concurrent: - shard-skl: [CRASH][31] -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at gem_mmap_gtt@fault-concurrent.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl4/igt at gem_mmap_gtt@fault-concurrent.html * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-skl: [FAIL][33] ([i915#54]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * {igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2}: - shard-glk: [FAIL][37] ([i915#1928]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk5/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1}: - shard-kbl: [FAIL][39] ([i915#79]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: - shard-apl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * {igt at kms_flip@flip-vs-suspend at a-edp1}: - shard-skl: [INCOMPLETE][43] ([i915#198]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl10/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip_tiling@flip-y-tiled: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +8 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt at kms_flip_tiling@flip-y-tiled.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl8/igt at kms_flip_tiling@flip-y-tiled.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb8/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_lease@page_flip_implicit_plane: - shard-snb: [TIMEOUT][49] ([i915#1958]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt at kms_lease@page_flip_implicit_plane.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-snb2/igt at kms_lease@page_flip_implicit_plane.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: - shard-apl: [DMESG-WARN][51] ([i915#95]) -> [PASS][52] +16 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_setmode@basic: - shard-hsw: [FAIL][57] ([i915#31]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw6/igt at kms_setmode@basic.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-hsw8/igt at kms_setmode@basic.html * {igt at perf@blocking-parameterized}: - shard-iclb: [FAIL][59] ([i915#1542]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at perf@blocking-parameterized.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb8/igt at perf@blocking-parameterized.html - shard-hsw: [FAIL][61] ([i915#1542]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw8/igt at perf@blocking-parameterized.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-hsw1/igt at perf@blocking-parameterized.html * igt at syncobj_wait@multi-wait-all-for-submit-signaled: - shard-tglb: [DMESG-WARN][63] ([i915#402]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb3/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-tglb8/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html * igt at syncobj_wait@multi-wait-for-submit-unsubmitted: - shard-kbl: [DMESG-WARN][65] ([i915#93] / [i915#95]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl2/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][67] ([i915#588]) -> [SKIP][68] ([i915#658]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb4/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at kms_content_protection@atomic-dpms.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][71] ([i915#1319]) -> [TIMEOUT][72] ([i915#1319] / [i915#1958]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_content_protection@legacy.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [FAIL][74] ([fdo#110321]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][75] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][76] ([i915#93] / [i915#95]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_psr@suspend: - shard-snb: [TIMEOUT][77] ([i915#1958]) -> [SKIP][78] ([fdo#109271]) +2 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt at kms_psr@suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-snb2/igt at kms_psr@suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8601 -> Patchwork_17912 CI-20190529: 20190529 CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17912: 737e451d926089f1b4b060add1c9ee07650074df @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/index.html From jason.v.le at intel.com Mon Jun 8 23:09:28 2020 From: jason.v.le at intel.com (Le, Jason V) Date: Mon, 8 Jun 2020 23:09:28 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/display: Avoid PSR and FBC features concurently. In-Reply-To: <50226b9506d36031402fa3ba73e90ec9f5a5ad38.camel@intel.com> References: <20200608065635.11652-1-jason.v.le@intel.com> <50226b9506d36031402fa3ba73e90ec9f5a5ad38.camel@intel.com> Message-ID: <BY5PR11MB44197EC1B9BE7B02E6C2F614C9850@BY5PR11MB4419.namprd11.prod.outlook.com> I had a meeting with an Intel Display Architect. The expected behavior for the driver is PSR2-SU enabling should disable FBC. I will update the patch to limit fbc disabling for PSR2-SU only, not PSR1. Please look at the HSD below for expected driver implementation. https://hsdes.intel.com/appstore/article/#/14010265390 Thanks, Jason -----Original Message----- From: Souza, Jose <jose.souza at intel.com> Sent: Monday, June 08, 2020 9:52 AM To: Le, Jason V <jason.v.le at intel.com>; intel-gfx at lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Avoid PSR and FBC features concurently. On Sun, 2020-06-07 at 23:56 -0700, Jason Le wrote: > Issue: Enble both PSR and FBC caused some fickers on some eDP panels > (eg. Panel GIS 13.5" QHD Glare NE135FBM-N41/NC135GFL02). Disbling > either PSR or FBC will solve this flicker issue. > > Both PSR and FBC features save power when render is not busy. When PSR > is active, saving power achieved by source turning off source > transmitter and main link, putting memory on self-refresh mode. > Therefore with PSR enabled, FBC role is minimized since PSR power > saving already covers most what FBC does. Disabling FBC in case to > avoid conflict between PSR and FBC which causes display anomaly in some scenarios. The combination of both saves even more power so no to this, we should fix the issue not disable features because of a single panel having issues. A PSR2 fix was merged yesterday "drm/i915/psr: Program default IO buffer Wake and Fast Wake" try with that, if just that don't fix try set psr_safest_params=1. If this do not helps, please file a bug, add debug information and then we proceed from that. > > Tests: > Booted system with PSR enabled, verified FBC disabled. > Disabled PSR with disabled (i915.enable_psr=0), verified FBC enabled. > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++ > drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index 1c26673acb2d..52bc7483adb5 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1419,6 +1419,12 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) > drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", > i915_modparams.enable_fbc); > > + if (i915_modparams.enable_psr) { > + i915_modparams.enable_fbc = 0; > + DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n"); > + } > + > + > if (!HAS_FBC(dev_priv)) { > fbc->no_fbc_reason = "unsupported by this chipset"; > return; > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index b7a2c102648a..25accfdd5ad3 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1439,8 +1439,10 @@ void intel_psr_init(struct drm_i915_private *dev_priv) > if (!HAS_PSR(dev_priv)) > return; > > - if (!dev_priv->psr.sink_support) > + if (!dev_priv->psr.sink_support) { > + i915_modparams.enable_psr = 0; > return; > + } > > if (IS_HASWELL(dev_priv)) > /* From sashal at kernel.org Mon Jun 8 23:02:08 2020 From: sashal at kernel.org (Sasha Levin) Date: Mon, 8 Jun 2020 19:02:08 -0400 Subject: [Intel-gfx] [PATCH AUTOSEL 5.6 003/606] drm/i915: Handle idling during i915_gem_evict_something busy loops In-Reply-To: <20200608231211.3363633-1-sashal@kernel.org> References: <20200608231211.3363633-1-sashal@kernel.org> Message-ID: <20200608231211.3363633-3-sashal@kernel.org> From: Chris Wilson <chris at chris-wilson.co.uk> [ Upstream commit 955da9d77435acac066139e9d7f7723ce7204a1d ] i915_gem_evict_something() is charged with finding a slot within the GTT that we may reuse. Since our goal is not to stall, we first look for a slot that only overlaps idle vma. To this end, on the first pass we move any active vma to the end of the search list. However, we only stopped moving active vma after we see the first active vma twice. If during the search, that first active vma completed, we would not notice and keep on extending the search list. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1746 Fixes: 2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm->mutex") Fixes: b1e3177bd1d8 ("drm/i915: Coordinate i915_active with its own mutex") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: <stable at vger.kernel.org> # v5.5+ Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200509115217.26853-1-chris at chris-wilson.co.uk (cherry picked from commit 73e28cc40bf00b5d168cb8f5cff1ae63e9097446) Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Sasha Levin <sashal at kernel.org> --- drivers/gpu/drm/i915/i915_gem_evict.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c index 0697bedebeef..d99df9c33708 100644 --- a/drivers/gpu/drm/i915/i915_gem_evict.c +++ b/drivers/gpu/drm/i915/i915_gem_evict.c @@ -130,6 +130,13 @@ i915_gem_evict_something(struct i915_address_space *vm, active = NULL; INIT_LIST_HEAD(&eviction_list); list_for_each_entry_safe(vma, next, &vm->bound_list, vm_link) { + if (vma == active) { /* now seen this vma twice */ + if (flags & PIN_NONBLOCK) + break; + + active = ERR_PTR(-EAGAIN); + } + /* * We keep this list in a rough least-recently scanned order * of active elements (inactive elements are cheap to reap). @@ -145,21 +152,12 @@ i915_gem_evict_something(struct i915_address_space *vm, * To notice when we complete one full cycle, we record the * first active element seen, before moving it to the tail. */ - if (i915_vma_is_active(vma)) { - if (vma == active) { - if (flags & PIN_NONBLOCK) - break; - - active = ERR_PTR(-EAGAIN); - } - - if (active != ERR_PTR(-EAGAIN)) { - if (!active) - active = vma; + if (active != ERR_PTR(-EAGAIN) && i915_vma_is_active(vma)) { + if (!active) + active = vma; - list_move_tail(&vma->vm_link, &vm->bound_list); - continue; - } + list_move_tail(&vma->vm_link, &vm->bound_list); + continue; } if (mark_free(&scan, vma, flags, &eviction_list)) -- 2.25.1 From sashal at kernel.org Mon Jun 8 23:02:36 2020 From: sashal at kernel.org (Sasha Levin) Date: Mon, 8 Jun 2020 19:02:36 -0400 Subject: [Intel-gfx] [PATCH AUTOSEL 5.6 031/606] Make the "Reducing compressed framebufer size" message be DRM_INFO_ONCE() In-Reply-To: <20200608231211.3363633-1-sashal@kernel.org> References: <20200608231211.3363633-1-sashal@kernel.org> Message-ID: <20200608231211.3363633-31-sashal@kernel.org> From: Peter Jones <pjones at redhat.com> commit 82152d424b6cb6fc1ede7d03d69c04e786688740 upstream. This was sort of annoying me: random:~$ dmesg | tail -1 [523884.039227] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. random:~$ dmesg | grep -c "Reducing the compressed" 47 This patch makes it DRM_INFO_ONCE() just like the similar message farther down in that function is pr_info_once(). Cc: stable at vger.kernel.org Signed-off-by: Peter Jones <pjones at redhat.com> Acked-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1745 Link: https://patchwork.freedesktop.org/patch/msgid/20180706190424.29194-1-pjones at redhat.com [vsyrjala: Rebase due to per-device logging] Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> (cherry picked from commit 6b7fc6a3e6af4ff5773949d0fed70d8e7f68d5ce) [Rodrigo: port back to DRM_INFO_ONCE] Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org> --- drivers/gpu/drm/i915/display/intel_fbc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index a1048ece541e..b6d5e7defa5b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -478,8 +478,7 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, if (!ret) goto err_llb; else if (ret > 1) { - DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); - + DRM_INFO_ONCE("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); } fbc->threshold = ret; -- 2.25.1 From sashal at kernel.org Mon Jun 8 23:02:42 2020 From: sashal at kernel.org (Sasha Levin) Date: Mon, 8 Jun 2020 19:02:42 -0400 Subject: [Intel-gfx] [PATCH AUTOSEL 5.6 037/606] drm/i915/tgl+: Fix interrupt handling for DP AUX transactions In-Reply-To: <20200608231211.3363633-1-sashal@kernel.org> References: <20200608231211.3363633-1-sashal@kernel.org> Message-ID: <20200608231211.3363633-37-sashal@kernel.org> From: Imre Deak <imre.deak at intel.com> commit 4457a9db2bdec2360ddb15242341696108167886 upstream. Unmask/enable AUX interrupts on all ports on TGL+. So far the interrupts worked only on port A, which meant each transaction on other ports took 10ms. Cc: <stable at vger.kernel.org> # v5.4+ Signed-off-by: Imre Deak <imre.deak at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200504075828.20348-1-imre.deak at intel.com (cherry picked from commit 054318c7e35f1d7d06b216143fff5f32405047ee) Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org> --- drivers/gpu/drm/i915/i915_irq.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index c6f02b0b6c7a..52825ae8301b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3324,7 +3324,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | GEN8_PIPE_CDCLK_CRC_DONE; u32 de_pipe_enables; - u32 de_port_masked = GEN8_AUX_CHANNEL_A; + u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; u32 de_misc_masked = GEN8_DE_EDP_PSR; enum pipe pipe; @@ -3332,18 +3332,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) <= 10) de_misc_masked |= GEN8_DE_MISC_GSE; - if (INTEL_GEN(dev_priv) >= 9) { - de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | - GEN9_AUX_CHANNEL_D; - if (IS_GEN9_LP(dev_priv)) - de_port_masked |= BXT_DE_PORT_GMBUS; - } - - if (INTEL_GEN(dev_priv) >= 11) - de_port_masked |= ICL_AUX_CHANNEL_E; - - if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11) - de_port_masked |= CNL_AUX_CHANNEL_F; + if (IS_GEN9_LP(dev_priv)) + de_port_masked |= BXT_DE_PORT_GMBUS; de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; -- 2.25.1 From sashal at kernel.org Mon Jun 8 23:04:47 2020 From: sashal at kernel.org (Sasha Levin) Date: Mon, 8 Jun 2020 19:04:47 -0400 Subject: [Intel-gfx] [PATCH AUTOSEL 5.6 162/606] drm/i915/gvt: Init DPLL/DDI vreg for virtual display instead of inheritance. In-Reply-To: <20200608231211.3363633-1-sashal@kernel.org> References: <20200608231211.3363633-1-sashal@kernel.org> Message-ID: <20200608231211.3363633-162-sashal@kernel.org> From: Colin Xu <colin.xu at intel.com> commit f965b68188ab59a40a421ced1b05a2fea638465c upstream. Init value of some display vregs rea inherited from host pregs. When host display in different status, i.e. all monitors unpluged, different display configurations, etc., GVT virtual display setup don't consistent thus may lead to guest driver consider display goes malfunctional. The added init vreg values are based on PRMs and fixed by calcuation from current configuration (only PIPE_A) and the virtual EDID. Fixes: 04d348ae3f0a ("drm/i915/gvt: vGPU display virtualization") Acked-by: Zhenyu Wang <zhenyuw at linux.intel.com> Signed-off-by: Colin Xu <colin.xu at intel.com> Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20200508060506.216250-1-colin.xu at intel.com Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org> --- drivers/gpu/drm/i915/gvt/display.c | 49 +++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index a62bdf9be682..59aa5e64acb0 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -207,14 +207,41 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) SKL_FUSE_PG_DIST_STATUS(SKL_PG0) | SKL_FUSE_PG_DIST_STATUS(SKL_PG1) | SKL_FUSE_PG_DIST_STATUS(SKL_PG2); - vgpu_vreg_t(vgpu, LCPLL1_CTL) |= - LCPLL_PLL_ENABLE | - LCPLL_PLL_LOCK; - vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE; - + /* + * Only 1 PIPE enabled in current vGPU display and PIPE_A is + * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A, + * TRANSCODER_A can be enabled. PORT_x depends on the input of + * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x + * so we fixed to DPLL0 here. + * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode + */ + vgpu_vreg_t(vgpu, DPLL_CTRL1) = + DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0); + vgpu_vreg_t(vgpu, DPLL_CTRL1) |= + DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0); + vgpu_vreg_t(vgpu, LCPLL1_CTL) = + LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK; + vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0); + /* + * Golden M/N are calculated based on: + * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID), + * DP link clk 1620 MHz and non-constant_n. + * TODO: calculate DP link symbol clk and stream clk m/n. + */ + vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; + vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; + vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; + vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; + vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; } if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { + vgpu_vreg_t(vgpu, DPLL_CTRL2) &= + ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); + vgpu_vreg_t(vgpu, DPLL_CTRL2) |= + DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B); + vgpu_vreg_t(vgpu, DPLL_CTRL2) |= + DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | @@ -235,6 +262,12 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) } if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) { + vgpu_vreg_t(vgpu, DPLL_CTRL2) &= + ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C); + vgpu_vreg_t(vgpu, DPLL_CTRL2) |= + DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C); + vgpu_vreg_t(vgpu, DPLL_CTRL2) |= + DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | @@ -255,6 +288,12 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) } if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) { + vgpu_vreg_t(vgpu, DPLL_CTRL2) &= + ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D); + vgpu_vreg_t(vgpu, DPLL_CTRL2) |= + DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D); + vgpu_vreg_t(vgpu, DPLL_CTRL2) |= + DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | -- 2.25.1 From sashal at kernel.org Mon Jun 8 23:04:48 2020 From: sashal at kernel.org (Sasha Levin) Date: Mon, 8 Jun 2020 19:04:48 -0400 Subject: [Intel-gfx] [PATCH AUTOSEL 5.6 163/606] drm/i915: Propagate error from completed fences In-Reply-To: <20200608231211.3363633-1-sashal@kernel.org> References: <20200608231211.3363633-1-sashal@kernel.org> Message-ID: <20200608231211.3363633-163-sashal@kernel.org> From: Chris Wilson <chris at chris-wilson.co.uk> commit bc850943486887e3859597a266767f95db90aa72 upstream. We need to preserve fatal errors from fences that are being terminated as we hook them up. Fixes: ef4688497512 ("drm/i915: Propagate fence errors") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Matthew Auld <matthew.auld at intel.com> Reviewed-by: Matthew Auld <matthew.auld at intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200506162136.3325-1-chris at chris-wilson.co.uk (cherry picked from commit 24fe5f2ab2478053d50a3bc629ada895903a5cbc) Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org> --- drivers/gpu/drm/i915/i915_request.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 32ab154db788..1f50fc8bcebf 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -947,8 +947,10 @@ i915_request_await_request(struct i915_request *to, struct i915_request *from) GEM_BUG_ON(to == from); GEM_BUG_ON(to->timeline == from->timeline); - if (i915_request_completed(from)) + if (i915_request_completed(from)) { + i915_sw_fence_set_error_once(&to->submit, from->fence.error); return 0; + } if (to->engine->schedule) { ret = i915_sched_node_add_dependency(&to->sched, -- 2.25.1 From jason.v.le at intel.com Tue Jun 9 00:37:29 2020 From: jason.v.le at intel.com (Jason Le) Date: Mon, 8 Jun 2020 17:37:29 -0700 Subject: [Intel-gfx] [PATCH v2] Disabling FBC when PSR2 SU update enabled Message-ID: <20200609003729.28437-1-jason.v.le@intel.com> --- drivers/gpu/drm/i915/display/intel_fbc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 52bc7483adb5..1505d93c6685 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1419,9 +1419,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", i915_modparams.enable_fbc); - if (i915_modparams.enable_psr) { - i915_modparams.enable_fbc = 0; - DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n"); + if (i915_modparams.enable_psr && dev_priv->psr.sink_psr2_support) { + i915_modparams.enable_fbc = 0; + DRM_DEBUG_KMS("PSR enabled. FBC no longer needed. Disable FBC. \n"); } -- 2.17.1 From patchwork at emeril.freedesktop.org Tue Jun 9 00:47:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 00:47:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBE?= =?utf-8?q?isabling_FBC_when_PSR2_SU_update_enabled?= In-Reply-To: <20200609003729.28437-1-jason.v.le@intel.com> References: <20200609003729.28437-1-jason.v.le@intel.com> Message-ID: <159166363011.17063.14650818009784401224@emeril.freedesktop.org> == Series Details == Series: Disabling FBC when PSR2 SU update enabled URL : https://patchwork.freedesktop.org/series/78138/ State : failure == Summary == Applying: Disabling FBC when PSR2 SU update enabled Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_fbc.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/display/intel_fbc.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_fbc.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 Disabling FBC when PSR2 SU update enabled When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From currojerez at riseup.net Tue Jun 9 01:39:17 2020 From: currojerez at riseup.net (Francisco Jerez) Date: Mon, 08 Jun 2020 18:39:17 -0700 Subject: [Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices In-Reply-To: <159160967766.60481.16392357667625923690@jlahtine-desk.ger.corp.intel.com> References: <20200604182658.878417-1-ayaz.siddiqui@intel.com> <87eequpla6.fsf@riseup.net> <159160967766.60481.16392357667625923690@jlahtine-desk.ger.corp.intel.com> Message-ID: <87blltow56.fsf@riseup.net> Joonas Lahtinen <joonas.lahtinen at linux.intel.com> writes: > + Jason and Ken > > Quoting Francisco Jerez (2020-06-05 00:34:57) >> Ayaz A Siddiqui <ayaz.siddiqui at intel.com> writes: >> >> > In order to avoid functional breakage of mis-programmed applications that >> > have grown to depend on unused MOCS entries, we are programming >> > those entries to be equal to fully cached ("L3 + LLC") entry as per the >> > recommendation from architecture team. >> > >> > These reserved and unspecified entries should not be used as they may be >> > changed to less performant variants with better coherency in the future >> > if more entries are needed. > > This patch message needs reworking. It should just standalone describe > the technical reasoning behind the patch completely, without referring > to elsewhere or to some other decision. > > The patch should also Cc: relevant developers who have previously been > working on the MOCS code and the userspace driver folks (Mesa, compute > and media). > >> This change seems highly questionable to me... If a future kernel >> release introduces a new MOCS entry with more strict coherency >> semantics, and an application starts relying on it, that application >> won't work when run on an older kernel version with this patch is >> applied. IOW setting uninitialized entries to the most strict caching >> setting available (UC) ensures forwards compatibility with future >> userspace, which seems like a more important design principle than >> giving full caching to broken userspace that accidentally makes use of >> an undefined MOCS entry not part of the kernel ABI. > > Both choices were considered, and ultimately Ken and Jason were more in > favor of 'worst coherency' if using reserved MOCS entry. n> > Your concern about newer software on older kernel is valid. But the > starting point of the decision is the no-regression policy of Linux. > > If we have some application developed on an older kernel where the MOCS > entry is unused and would be UC (best coherency), we would have no > choice but to keep that entry unused indefinitely not to break the > mis-programmed application. > That's a valid concern too, however it didn't seem like much an issue with the original Gen9 workflow that gave i915 the freedom to assign MOCS indices as it would see fit. If some broken userspace starts relying on the caching semantics of a random MOCS index not part of the currently exposed kernel ABI, and that userspace isn't some proprietary blob broken beyond repair, the kernel has the possibility (or the obligation?) to give that application the semantics it expected for that MOCS entry alone -- Which would likely improve the performance of the application beyond the original behavior unless UC was what it was actually expecting. IOW it seems to me that this conflict between forwards and backwards ABI compatibility is created by the rather artificial imperative to follow the reference MOCS tables without modification, which could conceivably tie our hands in the future and give us no choice but to break the no-regression policy if the reference MOCS tables change in a non-backwards-compatible way as has happened in the past (though luckily before any software started relying on it AFAIA), and largely defeats the point of having programmable MOCS tables IMO. Not really thrilled about that decision :P. > Now we have the worst coherency by default if an application is using > reserved entry, making it more likely to be noticed at develop time. And > even if it would not be noticed, modifying the entry for better > coherency should not functionally break the application. > > Regards, Joonas > >> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com> >> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> >> > --- >> > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- >> > 1 file changed, 89 insertions(+), 4 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c >> > index 632e08a4592b..1089bd5fdba2 100644 >> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c >> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c >> > @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { >> > L3_1_UC) >> > >> > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { >> > - /* Base - Error (Reserved for Non-Use) */ >> > - MOCS_ENTRY(0, 0x0, 0x0), >> > - /* Base - Reserved */ >> > - MOCS_ENTRY(1, 0x0, 0x0), >> > >> > GEN11_MOCS_ENTRIES, >> > >> > @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { >> > MOCS_ENTRY(61, >> > LE_1_UC | LE_TC_1_LLC, >> > L3_3_WB), >> > + >> > + /* NOTE: >> > + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). >> > + * These reserved entry should never be used, they may be chanaged >> > + * to low performant variants with better coherency in the future if >> > + * more entries are needed. >> > + */ >> > + >> > + /* Reserved index 0 and 1 */ >> > + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Reserved index 16 and 17 */ >> > + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Reserved index 24 and 25 */ >> > + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Unspecified indices 26 to 47 */ >> > + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + >> > + /* Unspecified indices 52 to 59 */ >> > + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB), >> > + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >> > + L3_3_WB) >> > }; >> > >> > static const struct drm_i915_mocs_entry icl_mocs_table[] = { >> > -- >> > 2.26.2 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx at lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 227 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200608/cf03419e/attachment.sig> From tvrtko.ursulin at linux.intel.com Tue Jun 9 06:59:27 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Tue, 9 Jun 2020 07:59:27 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <159160880517.15126.3134918011284478228@build.alporthouse.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> <159160880517.15126.3134918011284478228@build.alporthouse.com> Message-ID: <77acd2e3-86cc-7c78-22a0-8d8263510aa2@linux.intel.com> 666 On 08/06/2020 10:33, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-08 08:44:01) >> >> On 07/06/2020 23:20, Chris Wilson wrote: >>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>> >>> Sentinels are supposed to be last reqeusts in the elsp queue, not the >>> only one, so adjust the assert accordingly. >>> >>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>> --- >>> drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- >>> 1 file changed, 3 insertions(+), 11 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c >>> index d55a5e0466e5..db8a170b0e5c 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >>> @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, >>> ccid = ce->lrc.ccid; >>> >>> /* >>> - * Sentinels are supposed to be lonely so they flush the >>> - * current exection off the HW. Check that they are the >>> - * only request in the pending submission. >>> + * Sentinels are supposed to be the last request so they flush >>> + * the current exection off the HW. Check that they are the only >>> + * request in the pending submission. >>> */ >>> if (sentinel) { >>> GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", >>> @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, >>> port - execlists->pending); >>> return false; >>> } >>> - >>> sentinel = i915_request_has_sentinel(rq); >> >> FWIW I was changing it to "sentinel |= ..." so it keeps working if we >> decide to use more than 2 elsp ports on Icelake one day. > > But it will always fail on the next port... I don't follow. Sentinel has to be last so if it fails on the next port it is correct to do so, no? Regards, Tvrtko From tvrtko.ursulin at linux.intel.com Tue Jun 9 07:47:00 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Tue, 9 Jun 2020 08:47:00 +0100 Subject: [Intel-gfx] [PATCH 10/28] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <20200607222108.14401-10-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-10-chris@chris-wilson.co.uk> Message-ID: <ae303541-7df8-6966-95ea-ed46942acb06@linux.intel.com> On 07/06/2020 23:20, Chris Wilson wrote: > Over the next couple of patches, we will want to lock all the modified > vma for relocation processing under a single ww_mutex. We neither want > to have to include the vma that are skipped (due to no modifications > required) nor do we want those to be marked as written too. So separate > out the reloc validation into an early step, which we can use both to > reject the execbuf before committing to making our changes, and to > filter out the unmodified vma. > > This does introduce a second pass through the reloc[], but only if we > need to emit relocations. > > v2: reuse the outer loop, not cut'n'paste. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 145 +++++++++++------- > 1 file changed, 86 insertions(+), 59 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 23db79b806db..01ab1e15a142 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -911,9 +911,9 @@ static void eb_destroy(const struct i915_execbuffer *eb) > > static inline u64 > relocation_target(const struct drm_i915_gem_relocation_entry *reloc, > - const struct i915_vma *target) > + u64 target) > { > - return gen8_canonical_addr((int)reloc->delta + target->node.start); > + return gen8_canonical_addr((int)reloc->delta + target); > } > > static void reloc_cache_init(struct reloc_cache *cache, > @@ -1292,26 +1292,11 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, > return 0; > } > > -static u64 > -relocate_entry(struct i915_execbuffer *eb, > - struct i915_vma *vma, > - const struct drm_i915_gem_relocation_entry *reloc, > - const struct i915_vma *target) > -{ > - u64 target_addr = relocation_target(reloc, target); > - int err; > - > - err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); > - if (err) > - return err; > - > - return target->node.start | UPDATE; > -} > - > -static u64 > -eb_relocate_entry(struct i915_execbuffer *eb, > - struct eb_vma *ev, > - const struct drm_i915_gem_relocation_entry *reloc) > +static int > +eb_reloc_prepare(struct i915_execbuffer *eb, > + struct eb_vma *ev, > + const struct drm_i915_gem_relocation_entry *reloc, > + struct drm_i915_gem_relocation_entry __user *user) > { > struct drm_i915_private *i915 = eb->i915; > struct eb_vma *target; > @@ -1389,6 +1374,32 @@ eb_relocate_entry(struct i915_execbuffer *eb, > return -EINVAL; > } > > + return 1; > +} > + > +static int > +eb_reloc_entry(struct i915_execbuffer *eb, > + struct eb_vma *ev, > + const struct drm_i915_gem_relocation_entry *reloc, > + struct drm_i915_gem_relocation_entry __user *user) > +{ > + struct eb_vma *target; > + u64 offset; > + int err; > + > + /* we've already hold a reference to all valid objects */ > + target = eb_get_vma(eb, reloc->target_handle); > + if (unlikely(!target)) > + return -ENOENT; > + > + /* > + * If the relocation already has the right value in it, no > + * more work needs to be done. > + */ > + offset = gen8_canonical_addr(target->vma->node.start); > + if (offset == reloc->presumed_offset) > + return 0; > + Haven't these reloc entries been removed from the list in the prepare phase? Regards, Tvrtko > /* > * If we write into the object, we need to force the synchronisation > * barrier, either with an asynchronous clflush or if we executed the > @@ -1399,11 +1410,41 @@ eb_relocate_entry(struct i915_execbuffer *eb, > */ > ev->flags &= ~EXEC_OBJECT_ASYNC; > > - /* and update the user's relocation entry */ > - return relocate_entry(eb, ev->vma, reloc, target->vma); > + err = __reloc_entry_gpu(eb, ev->vma, reloc->offset, > + relocation_target(reloc, offset)); > + if (err) > + return err; > + > + /* > + * Note that reporting an error now > + * leaves everything in an inconsistent > + * state as we have *already* changed > + * the relocation value inside the > + * object. As we have not changed the > + * reloc.presumed_offset or will not > + * change the execobject.offset, on the > + * call we may not rewrite the value > + * inside the object, leaving it > + * dangling and causing a GPU hang. Unless > + * userspace dynamically rebuilds the > + * relocations on each execbuf rather than > + * presume a static tree. > + * > + * We did previously check if the relocations > + * were writable (access_ok), an error now > + * would be a strange race with mprotect, > + * having already demonstrated that we > + * can read from this userspace address. > + */ > + __put_user(offset, &user->presumed_offset); > + return 0; > } > > -static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > +static long eb_reloc_vma(struct i915_execbuffer *eb, struct eb_vma *ev, > + int (*fn)(struct i915_execbuffer *eb, > + struct eb_vma *ev, > + const struct drm_i915_gem_relocation_entry *reloc, > + struct drm_i915_gem_relocation_entry __user *user)) > { > #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) > struct drm_i915_gem_relocation_entry stack[N_RELOC(512)]; > @@ -1411,6 +1452,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > struct drm_i915_gem_relocation_entry __user *urelocs = > u64_to_user_ptr(entry->relocs_ptr); > unsigned long remain = entry->relocation_count; > + int required = 0; > > if (unlikely(remain > N_RELOC(ULONG_MAX))) > return -EINVAL; > @@ -1443,42 +1485,18 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) > > remain -= count; > do { > - u64 offset = eb_relocate_entry(eb, ev, r); > + int ret; > > - if (likely(offset == 0)) { > - } else if ((s64)offset < 0) { > - return (int)offset; > - } else { > - /* > - * Note that reporting an error now > - * leaves everything in an inconsistent > - * state as we have *already* changed > - * the relocation value inside the > - * object. As we have not changed the > - * reloc.presumed_offset or will not > - * change the execobject.offset, on the > - * call we may not rewrite the value > - * inside the object, leaving it > - * dangling and causing a GPU hang. Unless > - * userspace dynamically rebuilds the > - * relocations on each execbuf rather than > - * presume a static tree. > - * > - * We did previously check if the relocations > - * were writable (access_ok), an error now > - * would be a strange race with mprotect, > - * having already demonstrated that we > - * can read from this userspace address. > - */ > - offset = gen8_canonical_addr(offset & ~UPDATE); > - __put_user(offset, > - &urelocs[r - stack].presumed_offset); > - } > + ret = fn(eb, ev, r, &urelocs[r - stack]); > + if (ret < 0) > + return ret; > + > + required |= ret; > } while (r++, --count); > urelocs += ARRAY_SIZE(stack); > } while (remain); > > - return 0; > + return required; > } > > static int eb_relocate(struct i915_execbuffer *eb) > @@ -1497,12 +1515,21 @@ static int eb_relocate(struct i915_execbuffer *eb) > > /* The objects are in their final locations, apply the relocations. */ > if (eb->args->flags & __EXEC_HAS_RELOC) { > - struct eb_vma *ev; > + struct eb_vma *ev, *en; > int flush; > > + list_for_each_entry_safe(ev, en, &eb->relocs, reloc_link) { > + err = eb_reloc_vma(eb, ev, eb_reloc_prepare); > + if (err < 0) > + return err; > + > + if (err == 0) > + list_del_init(&ev->reloc_link); > + } > + > list_for_each_entry(ev, &eb->relocs, reloc_link) { > - err = eb_relocate_vma(eb, ev); > - if (err) > + err = eb_reloc_vma(eb, ev, eb_reloc_entry); > + if (err < 0) > break; > } > > From chris at chris-wilson.co.uk Tue Jun 9 10:29:10 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 09 Jun 2020 11:29:10 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <77acd2e3-86cc-7c78-22a0-8d8263510aa2@linux.intel.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> <159160880517.15126.3134918011284478228@build.alporthouse.com> <77acd2e3-86cc-7c78-22a0-8d8263510aa2@linux.intel.com> Message-ID: <159169855088.24308.3785883777038202508@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-09 07:59:27) > 666 > On 08/06/2020 10:33, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-08 08:44:01) > >> > >> On 07/06/2020 23:20, Chris Wilson wrote: > >>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >>> > >>> Sentinels are supposed to be last reqeusts in the elsp queue, not the > >>> only one, so adjust the assert accordingly. > >>> > >>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >>> --- > >>> drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- > >>> 1 file changed, 3 insertions(+), 11 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > >>> index d55a5e0466e5..db8a170b0e5c 100644 > >>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > >>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > >>> @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > >>> ccid = ce->lrc.ccid; > >>> > >>> /* > >>> - * Sentinels are supposed to be lonely so they flush the > >>> - * current exection off the HW. Check that they are the > >>> - * only request in the pending submission. > >>> + * Sentinels are supposed to be the last request so they flush > >>> + * the current exection off the HW. Check that they are the only > >>> + * request in the pending submission. > >>> */ > >>> if (sentinel) { > >>> GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", > >>> @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > >>> port - execlists->pending); > >>> return false; > >>> } > >>> - > >>> sentinel = i915_request_has_sentinel(rq); > >> > >> FWIW I was changing it to "sentinel |= ..." so it keeps working if we > >> decide to use more than 2 elsp ports on Icelake one day. > > > > But it will always fail on the next port... > > I don't follow. Sentinel has to be last so if it fails on the next port > it is correct to do so, no? Exactly. We only check the first port after setting sentinel, if that port is occupied we fail. Hence why we don't need |=, since there is no continuation. -Chris From tvrtko.ursulin at linux.intel.com Tue Jun 9 10:39:11 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Tue, 9 Jun 2020 11:39:11 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <159169855088.24308.3785883777038202508@build.alporthouse.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> <159160880517.15126.3134918011284478228@build.alporthouse.com> <77acd2e3-86cc-7c78-22a0-8d8263510aa2@linux.intel.com> <159169855088.24308.3785883777038202508@build.alporthouse.com> Message-ID: <195aefb1-128e-cfdb-cdeb-3a4e2c0248f8@linux.intel.com> On 09/06/2020 11:29, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-09 07:59:27) >> 666 >> On 08/06/2020 10:33, Chris Wilson wrote: >>> Quoting Tvrtko Ursulin (2020-06-08 08:44:01) >>>> >>>> On 07/06/2020 23:20, Chris Wilson wrote: >>>>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>>>> >>>>> Sentinels are supposed to be last reqeusts in the elsp queue, not the >>>>> only one, so adjust the assert accordingly. >>>>> >>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>>>> --- >>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- >>>>> 1 file changed, 3 insertions(+), 11 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c >>>>> index d55a5e0466e5..db8a170b0e5c 100644 >>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >>>>> @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, >>>>> ccid = ce->lrc.ccid; >>>>> >>>>> /* >>>>> - * Sentinels are supposed to be lonely so they flush the >>>>> - * current exection off the HW. Check that they are the >>>>> - * only request in the pending submission. >>>>> + * Sentinels are supposed to be the last request so they flush >>>>> + * the current exection off the HW. Check that they are the only >>>>> + * request in the pending submission. >>>>> */ >>>>> if (sentinel) { >>>>> GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", >>>>> @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, >>>>> port - execlists->pending); >>>>> return false; >>>>> } >>>>> - >>>>> sentinel = i915_request_has_sentinel(rq); >>>> >>>> FWIW I was changing it to "sentinel |= ..." so it keeps working if we >>>> decide to use more than 2 elsp ports on Icelake one day. >>> >>> But it will always fail on the next port... >> >> I don't follow. Sentinel has to be last so if it fails on the next port >> it is correct to do so, no? > > Exactly. We only check the first port after setting sentinel, if that > port is occupied we fail. Hence why we don't need |=, since there is no > continuation. But if more than two ports we also overwrite the bools so: sentinel, non-sentinel, sentinel would not catch. I was just future proofing it. :) Regards, Tvrtko From chris at chris-wilson.co.uk Tue Jun 9 10:47:05 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 09 Jun 2020 11:47:05 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <195aefb1-128e-cfdb-cdeb-3a4e2c0248f8@linux.intel.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> <159160880517.15126.3134918011284478228@build.alporthouse.com> <77acd2e3-86cc-7c78-22a0-8d8263510aa2@linux.intel.com> <159169855088.24308.3785883777038202508@build.alporthouse.com> <195aefb1-128e-cfdb-cdeb-3a4e2c0248f8@linux.intel.com> Message-ID: <159169962594.24308.17590896872287208474@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-09 11:39:11) > > On 09/06/2020 11:29, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-09 07:59:27) > >> 666 > >> On 08/06/2020 10:33, Chris Wilson wrote: > >>> Quoting Tvrtko Ursulin (2020-06-08 08:44:01) > >>>> > >>>> On 07/06/2020 23:20, Chris Wilson wrote: > >>>>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >>>>> > >>>>> Sentinels are supposed to be last reqeusts in the elsp queue, not the > >>>>> only one, so adjust the assert accordingly. > >>>>> > >>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >>>>> --- > >>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- > >>>>> 1 file changed, 3 insertions(+), 11 deletions(-) > >>>>> > >>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > >>>>> index d55a5e0466e5..db8a170b0e5c 100644 > >>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > >>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > >>>>> @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > >>>>> ccid = ce->lrc.ccid; > >>>>> > >>>>> /* > >>>>> - * Sentinels are supposed to be lonely so they flush the > >>>>> - * current exection off the HW. Check that they are the > >>>>> - * only request in the pending submission. > >>>>> + * Sentinels are supposed to be the last request so they flush > >>>>> + * the current exection off the HW. Check that they are the only > >>>>> + * request in the pending submission. > >>>>> */ > >>>>> if (sentinel) { > >>>>> GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", > >>>>> @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, > >>>>> port - execlists->pending); > >>>>> return false; > >>>>> } > >>>>> - > >>>>> sentinel = i915_request_has_sentinel(rq); > >>>> > >>>> FWIW I was changing it to "sentinel |= ..." so it keeps working if we > >>>> decide to use more than 2 elsp ports on Icelake one day. > >>> > >>> But it will always fail on the next port... > >> > >> I don't follow. Sentinel has to be last so if it fails on the next port > >> it is correct to do so, no? > > > > Exactly. We only check the first port after setting sentinel, if that > > port is occupied we fail. Hence why we don't need |=, since there is no > > continuation. > > But if more than two ports we also overwrite the bools so: sentinel, > non-sentinel, sentinel would not catch. I was just future proofing it. :) [0] -> sentinel [1] != NULL -> ERROR [0] -> not sentinel [1] -> sentinel [2] != NULL -> ERROR We fail if anything comes after a sentinel. -Chris From chris at chris-wilson.co.uk Tue Jun 9 10:48:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 09 Jun 2020 11:48:16 +0100 Subject: [Intel-gfx] [PATCH 10/28] drm/i915/gem: Separate reloc validation into an earlier step In-Reply-To: <ae303541-7df8-6966-95ea-ed46942acb06@linux.intel.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-10-chris@chris-wilson.co.uk> <ae303541-7df8-6966-95ea-ed46942acb06@linux.intel.com> Message-ID: <159169969604.24308.16289911444825302624@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-09 08:47:00) > > On 07/06/2020 23:20, Chris Wilson wrote: > > Over the next couple of patches, we will want to lock all the modified > > vma for relocation processing under a single ww_mutex. We neither want > > to have to include the vma that are skipped (due to no modifications > > required) nor do we want those to be marked as written too. So separate > > out the reloc validation into an early step, which we can use both to > > reject the execbuf before committing to making our changes, and to > > filter out the unmodified vma. > > > > This does introduce a second pass through the reloc[], but only if we > > need to emit relocations. > > > > v2: reuse the outer loop, not cut'n'paste. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 145 +++++++++++------- > > 1 file changed, 86 insertions(+), 59 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > index 23db79b806db..01ab1e15a142 100644 > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > @@ -911,9 +911,9 @@ static void eb_destroy(const struct i915_execbuffer *eb) > > > > static inline u64 > > relocation_target(const struct drm_i915_gem_relocation_entry *reloc, > > - const struct i915_vma *target) > > + u64 target) > > { > > - return gen8_canonical_addr((int)reloc->delta + target->node.start); > > + return gen8_canonical_addr((int)reloc->delta + target); > > } > > > > static void reloc_cache_init(struct reloc_cache *cache, > > @@ -1292,26 +1292,11 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, > > return 0; > > } > > > > -static u64 > > -relocate_entry(struct i915_execbuffer *eb, > > - struct i915_vma *vma, > > - const struct drm_i915_gem_relocation_entry *reloc, > > - const struct i915_vma *target) > > -{ > > - u64 target_addr = relocation_target(reloc, target); > > - int err; > > - > > - err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); > > - if (err) > > - return err; > > - > > - return target->node.start | UPDATE; > > -} > > - > > -static u64 > > -eb_relocate_entry(struct i915_execbuffer *eb, > > - struct eb_vma *ev, > > - const struct drm_i915_gem_relocation_entry *reloc) > > +static int > > +eb_reloc_prepare(struct i915_execbuffer *eb, > > + struct eb_vma *ev, > > + const struct drm_i915_gem_relocation_entry *reloc, > > + struct drm_i915_gem_relocation_entry __user *user) > > { > > struct drm_i915_private *i915 = eb->i915; > > struct eb_vma *target; > > @@ -1389,6 +1374,32 @@ eb_relocate_entry(struct i915_execbuffer *eb, > > return -EINVAL; > > } > > > > + return 1; > > +} > > + > > +static int > > +eb_reloc_entry(struct i915_execbuffer *eb, > > + struct eb_vma *ev, > > + const struct drm_i915_gem_relocation_entry *reloc, > > + struct drm_i915_gem_relocation_entry __user *user) > > +{ > > + struct eb_vma *target; > > + u64 offset; > > + int err; > > + > > + /* we've already hold a reference to all valid objects */ > > + target = eb_get_vma(eb, reloc->target_handle); > > + if (unlikely(!target)) > > + return -ENOENT; > > + > > + /* > > + * If the relocation already has the right value in it, no > > + * more work needs to be done. > > + */ > > + offset = gen8_canonical_addr(target->vma->node.start); > > + if (offset == reloc->presumed_offset) > + return 0; > > + > > Haven't these reloc entries been removed from the list in the prepare phase? No, we don't adjust the user reloc arrays, we only skip entire objects that do not require relocs. -Chris From andriy.shevchenko at linux.intel.com Tue Jun 9 11:29:05 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Tue, 9 Jun 2020 14:29:05 +0300 Subject: [Intel-gfx] [PATCH v2 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 In-Reply-To: <20200607181840.13536-7-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-7-hdegoede@redhat.com> Message-ID: <20200609112905.GK2428291@smile.fi.intel.com> On Sun, Jun 07, 2020 at 08:18:31PM +0200, Hans de Goede wrote: > While looking into adding atomic-pwm support to the pwm-crc driver I > noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and > there is a clock-divider which divides this with a value between 1-128, > and there are 256 duty-cycle steps. > > The pwm-crc code before this commit assumed that a clock-divider > setting of 1 means that the PWM output is running at 6 MHZ, if that > is true, where do these 256 duty-cycle steps come from? > > This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that > seems unlikely for a PMIC which is using a silicon process optimized for > power-switching transistors. It is way more likely that there is an 8 > bit counter for the duty cycle which acts as an extra fixed divider > wrt the PWM output frequency. > > The main user of the pwm-crc driver is the i915 GPU driver which uses it > for backlight control. Lets compare the PWM register values set by the > video-BIOS (the GOP), assuming the extra fixed divider is present versus > the PWM frequency specified in the Video-BIOS-Tables: > > Device: PWM Hz set by BIOS PWM Hz specified in VBT > Asus T100TA 200 200 > Asus T100HA 200 200 > Lenovo Miix 2 8 23437 20000 > Toshiba WT8-A 23437 20000 > > So as we can see if we assume the extra division by 256 then the register > values set by the GOP are an exact match for the VBT values, where as > otherwise the values would be of by a factor of 256. > > This commit fixes the period / duty_cycle calculations to take the > extra division by 256 into account. ... > +#define NSEC_PER_MHZ 1000 This is against physics. What this cryptic name means actually? Existing NSEC_PER_USEC ? -- With Best Regards, Andy Shevchenko From andriy.shevchenko at linux.intel.com Tue Jun 9 11:31:12 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Tue, 9 Jun 2020 14:31:12 +0300 Subject: [Intel-gfx] [PATCH v2 09/15] pwm: crc: Enable/disable PWM output on enable/disable In-Reply-To: <20200607181840.13536-10-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-10-hdegoede@redhat.com> Message-ID: <20200609113112.GL2428291@smile.fi.intel.com> On Sun, Jun 07, 2020 at 08:18:34PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, > this commit makes crc_pwm_disable() clear it on disable and makes > crc_pwm_enable() set it again on re-enable. > > This should disable the internal (divided) PWM clock and tri-state the > PWM output pin when disabled, saving some power. ... > +static int crc_pwm_calc_clk_div(int period_ns) > +{ > + int clk_div; > + > + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); > + /* clk_div 1 - 128, maps to register values 0-127 */ > + if (clk_div > 0) > + clk_div--; > + > + return clk_div; > +} You can reduce ping-pong format of the series if you introduced this helper in the patch that adds -1 to clock divisor. -- With Best Regards, Andy Shevchenko From andriy.shevchenko at linux.intel.com Tue Jun 9 11:32:20 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Tue, 9 Jun 2020 14:32:20 +0300 Subject: [Intel-gfx] [PATCH v2 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API In-Reply-To: <20200607181840.13536-11-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-11-hdegoede@redhat.com> Message-ID: <20200609113220.GM2428291@smile.fi.intel.com> On Sun, Jun 07, 2020 at 08:18:35PM +0200, Hans de Goede wrote: > Replace the enable, disable and config pwm_ops with an apply op, > to support the new atomic PWM API. ... > -static int crc_pwm_calc_clk_div(int period_ns) > +static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) > { > - int clk_div; > - > - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); > - /* clk_div 1 - 128, maps to register values 0-127 */ > - if (clk_div > 0) > - clk_div--; > - > - return clk_div; > -} ... > + clk_div = PWM_BASE_CLK_MHZ * state->period / > + (256 * NSEC_PER_MHZ); > + /* clk_div 1 - 128, maps to register values 0-127 */ > + if (clk_div > 0) > + clk_div--; And again... :-( -- With Best Regards, Andy Shevchenko From andriy.shevchenko at linux.intel.com Tue Jun 9 11:32:54 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Tue, 9 Jun 2020 14:32:54 +0300 Subject: [Intel-gfx] [PATCH v2 11/15] pwm: crc: Implement get_state() method In-Reply-To: <20200607181840.13536-12-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-12-hdegoede@redhat.com> Message-ID: <20200609113254.GN2428291@smile.fi.intel.com> On Sun, Jun 07, 2020 at 08:18:36PM +0200, Hans de Goede wrote: > Implement the pwm_ops.get_state() method to complete the support for the > new atomic PWM API. This one is good. Reviewed-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com> > Signed-off-by: Hans de Goede <hdegoede at redhat.com> > --- > drivers/pwm/pwm-crc.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c > index 58c7e9ef7278..6c75a3470bc8 100644 > --- a/drivers/pwm/pwm-crc.c > +++ b/drivers/pwm/pwm-crc.c > @@ -114,8 +114,37 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > return 0; > } > > +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, > + struct pwm_state *state) > +{ > + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); > + struct device *dev = crc_pwm->chip.dev; > + unsigned int clk_div, clk_div_reg, duty_cycle_reg; > + int error; > + > + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); > + if (error) { > + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); > + return; > + } > + > + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); > + if (error) { > + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); > + return; > + } > + > + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; > + > + state->period = clk_div * NSEC_PER_MHZ * 256 / PWM_BASE_CLK_MHZ; > + state->duty_cycle = duty_cycle_reg * state->period / PWM_MAX_LEVEL; > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); > +} > + > static const struct pwm_ops crc_pwm_ops = { > .apply = crc_pwm_apply, > + .get_state = crc_pwm_get_state, > }; > > static int crystalcove_pwm_probe(struct platform_device *pdev) > -- > 2.26.2 > -- With Best Regards, Andy Shevchenko From tvrtko.ursulin at linux.intel.com Tue Jun 9 11:45:29 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Tue, 9 Jun 2020 12:45:29 +0100 Subject: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation In-Reply-To: <159169962594.24308.17590896872287208474@build.alporthouse.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <9f995ee6-5f93-088d-47d6-5431076de596@linux.intel.com> <159160880517.15126.3134918011284478228@build.alporthouse.com> <77acd2e3-86cc-7c78-22a0-8d8263510aa2@linux.intel.com> <159169855088.24308.3785883777038202508@build.alporthouse.com> <195aefb1-128e-cfdb-cdeb-3a4e2c0248f8@linux.intel.com> <159169962594.24308.17590896872287208474@build.alporthouse.com> Message-ID: <6d257ff7-5699-8a46-63fe-dc4805a876e7@linux.intel.com> On 09/06/2020 11:47, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-09 11:39:11) >> >> On 09/06/2020 11:29, Chris Wilson wrote: >>> Quoting Tvrtko Ursulin (2020-06-09 07:59:27) >>>> 666 >>>> On 08/06/2020 10:33, Chris Wilson wrote: >>>>> Quoting Tvrtko Ursulin (2020-06-08 08:44:01) >>>>>> >>>>>> On 07/06/2020 23:20, Chris Wilson wrote: >>>>>>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>>>>>> >>>>>>> Sentinels are supposed to be last reqeusts in the elsp queue, not the >>>>>>> only one, so adjust the assert accordingly. >>>>>>> >>>>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>>>>>> --- >>>>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++----------- >>>>>>> 1 file changed, 3 insertions(+), 11 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c >>>>>>> index d55a5e0466e5..db8a170b0e5c 100644 >>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >>>>>>> @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, >>>>>>> ccid = ce->lrc.ccid; >>>>>>> >>>>>>> /* >>>>>>> - * Sentinels are supposed to be lonely so they flush the >>>>>>> - * current exection off the HW. Check that they are the >>>>>>> - * only request in the pending submission. >>>>>>> + * Sentinels are supposed to be the last request so they flush >>>>>>> + * the current exection off the HW. Check that they are the only >>>>>>> + * request in the pending submission. >>>>>>> */ >>>>>>> if (sentinel) { >>>>>>> GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n", >>>>>>> @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, >>>>>>> port - execlists->pending); >>>>>>> return false; >>>>>>> } >>>>>>> - >>>>>>> sentinel = i915_request_has_sentinel(rq); >>>>>> >>>>>> FWIW I was changing it to "sentinel |= ..." so it keeps working if we >>>>>> decide to use more than 2 elsp ports on Icelake one day. >>>>> >>>>> But it will always fail on the next port... >>>> >>>> I don't follow. Sentinel has to be last so if it fails on the next port >>>> it is correct to do so, no? >>> >>> Exactly. We only check the first port after setting sentinel, if that >>> port is occupied we fail. Hence why we don't need |=, since there is no >>> continuation. >> >> But if more than two ports we also overwrite the bools so: sentinel, >> non-sentinel, sentinel would not catch. I was just future proofing it. :) > > [0] -> sentinel > [1] != NULL -> ERROR > > [0] -> not sentinel > [1] -> sentinel > [2] != NULL -> ERROR > > We fail if anything comes after a sentinel. :) Joke is on me. Regards, Tvrtko From Eugeniy.Paltsev at synopsys.com Tue Jun 9 12:08:11 2020 From: Eugeniy.Paltsev at synopsys.com (Eugeniy Paltsev) Date: Tue, 9 Jun 2020 12:08:11 +0000 Subject: [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny In-Reply-To: <CAKMK7uESUnLR1N07T513RjGUAp8FA6oHaO1Y+uvTKpFuM_8+gQ@mail.gmail.com> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-54-daniel.vetter@ffwll.ch> <20200415094512.GA30444@ravnborg.org> <MWHPR12MB14532DA5713E3B579ABFE1F4A1DB0@MWHPR12MB1453.namprd12.prod.outlook.com> <CAKMK7uGDGgt8Cm_bFoyzeoP2CWyiUNdUwb7GL6Ohu3k0rP0p1w@mail.gmail.com> <20200428140842.GL3456981@phenom.ffwll.local> <CH2PR12MB3894B40C6D71435D3E759A34A1A20@CH2PR12MB3894.namprd12.prod.outlook.com> <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com> <20200604080507.GT20149@phenom.ffwll.local> <CY4PR1201MB01363EB95985A2C64ADA6841DE890@CY4PR1201MB0136.namprd12.prod.outlook.com> <CAKMK7uFLvV3=uhfnf=MreKBM==-gzXqx3NrV8KDA2D5sTAn2SQ@mail.gmail.com> <CY4PR1201MB013642EB94E07AED91813A5FDE890@CY4PR1201MB0136.namprd12.prod.outlook.com>, <CAKMK7uESUnLR1N07T513RjGUAp8FA6oHaO1Y+uvTKpFuM_8+gQ@mail.gmail.com> Message-ID: <CY4PR1201MB013654230A216EE7EB3C0E9BDE820@CY4PR1201MB0136.namprd12.prod.outlook.com> Hi Daniel, I've got pretty strange results so I need some time to investigate it and probably retest. I'll send you update in a few days. --- Eugeniy Paltsev ________________________________________ From: Daniel Vetter <daniel at ffwll.ch> Sent: Friday, June 5, 2020 22:55 To: Eugeniy Paltsev Cc: Intel Graphics Development; DRI Development; Daniel Vetter; Sam Ravnborg; Alexey Brodkin; snps-arc at lists.infradead.org Subject: Re: [PATCH 53/59] drm/arc: Move to drm/tiny Hi Eugeniy, Thanks for testing. I looked at the second one (I hoped it would just magically disappear) and I still don't understand what's going on there. My patch series isn't touching that area at all, so really confused. I squashed in the bugfix from the previous round into the right patches, and pushed a branch with just the arcpgu changes here: https://urldefense.com/v3/__https://cgit.freedesktop.org/*danvet/drm/log/?h=for-eugeniy__;fg!!A4F2R9G_pg!IJ1o4XiXVdStPu--Q-SCTUpRbsbqrjX255R34nuD7L7ptPywOy4SKr21dwSpfOkXIVqH5pM$ Maybe it's something in my pile of not-so-tested stuff :-) Can you pls test this? And if it still fails, try to bisect where it breaks? Thanks, Daniel On Thu, Jun 4, 2020 at 9:00 PM Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> wrote: > > I've tested your change and one issue gone. > > However I still see kernel crash (due to invalid read in kernel mode by 0x0 address) on weston stop: > ----------------------------------->8------------------------------------------- > Oops > Path: (null) > CPU: 0 PID: 12 Comm: kworker/0:1 Not tainted 5.7.0-rc6-01594-g4ceda91a4176-dirty #6 > Workqueue: events drm_mode_rmfb_work_fn > Invalid Read @ 0x00000000 by insn @ drm_gem_fb_destroy+0x32/0x130 > ECR: 0x00050100 EFA: 0x00000000 ERET: 0x813b9a76 > STAT32: 0x80080602 [IE K ] BTA: 0x813b9a72 > BLK: drm_gem_fb_destroy+0xc0/0x130 > SP: 0x9f055ea4 FP: 0x00000000 > LPS: 0x813560ec LPE: 0x813560f0 LPC: 0x00000000 > r00: 0x00000000 r01: 0x9f6a6100 r02: 0x00000001 > r03: 0x9fd5dde8 r04: 0x810f5de8 r05: 0x00000000 > r06: 0x00000000 r07: 0x00000000 r08: 0x000000e1 > r09: 0x00000000 r10: 0x00000000 r11: 0x000000e1 > r12: 0x813b9b04 > > Stack Trace: > drm_gem_fb_destroy+0x32/0x130 > drm_framebuffer_remove+0x1d2/0x358 > drm_mode_rmfb_work_fn+0x28/0x38 > process_one_work+0x19a/0x358 > worker_thread+0x2c4/0x494 > kthread+0xec/0x100 > ret_from_fork+0x18/0x1c > ----------------------------------->8------------------------------------------- > > > The stack traces may vary but always end in drm_gem_fb_destroy: > ----------------------------------->8------------------------------------------- > Stack Trace: > drm_gem_fb_destroy+0x32/0x130 > drm_mode_rmfb+0x10e/0x148 > drm_ioctl_kernel+0x70/0xa0 > drm_ioctl+0x284/0x410 > ksys_ioctl+0xea/0xa3c > EV_Trap+0xcc/0xd0 > ----------------------------------->8------------------------------------------- > Stack Trace: > drm_gem_fb_destroy+0x32/0x130 > drm_fb_release+0x66/0xb0 > drm_file_free.part.11+0x112/0x1bc > drm_release+0x80/0x120 > __fput+0x98/0x1bc > task_work_run+0x6e/0xa8 > do_exit+0x2b4/0x7fc > do_group_exit+0x2a/0x8c > get_signal+0x9a/0x5f0 > do_signal+0x86/0x23c > resume_user_mode_begin+0x88/0xd0 > ----------------------------------->8------------------------------------------- > > > --- > Eugeniy Paltsev > > > ________________________________________ > From: Daniel Vetter <daniel at ffwll.ch> > Sent: Thursday, June 4, 2020 14:19 > To: Eugeniy Paltsev > Cc: Intel Graphics Development; DRI Development; Daniel Vetter; Sam Ravnborg; Alexey Brodkin > Subject: Re: [PATCH 53/59] drm/arc: Move to drm/tiny > > Hi Eugeniy, > > Apologies, somehow I missed your mail. I looked at the code again, and I > think I fumbled something. Does the below diff help to prevent the issues? > > Thanks, Daniel > > > diff --git a/drivers/gpu/drm/tiny/arcpgu.c b/drivers/gpu/drm/tiny/arcpgu.c > index 857812f25bec..33d812a5ad7f 100644 > --- a/drivers/gpu/drm/tiny/arcpgu.c > +++ b/drivers/gpu/drm/tiny/arcpgu.c > @@ -228,6 +228,9 @@ static void arc_pgu_update(struct drm_simple_display_pipe *pipe, > struct arcpgu_drm_private *arcpgu; > struct drm_gem_cma_object *gem; > > + if (!pipe->plane.state->fb) > + return; > + > arcpgu = pipe_to_arcpgu_priv(pipe); > gem = drm_fb_cma_get_gem_obj(pipe->plane.state->fb, 0); > arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr); > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - https://urldefense.com/v3/__http://blog.ffwll.ch__;!!A4F2R9G_pg!P0EvyJfMuDwqbeZmHZM5S9po30QWr4KgGrggRirNfgo7wrRXfnUO-8iq0AA4fQCW2WGPlDc$ -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - https://urldefense.com/v3/__http://blog.ffwll.ch__;!!A4F2R9G_pg!IJ1o4XiXVdStPu--Q-SCTUpRbsbqrjX255R34nuD7L7ptPywOy4SKr21dwSpfOkXpn86Q20$ From imre.deak at intel.com Tue Jun 9 12:15:56 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 9 Jun 2020 15:15:56 +0300 Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200604184500.23730-2-imre.deak@intel.com> References: <20200603211040.8190-3-imre.deak@intel.com> <20200604184500.23730-2-imre.deak@intel.com> Message-ID: <20200609121556.GF22647@ideak-desk.fi.intel.com> Hi Dave, Lyude, are you ok to merge this patchset via the drm-intel-next-queued tree? --Imre On Thu, Jun 04, 2020 at 09:45:00PM +0300, Imre Deak wrote: > Some TypeC -> native DP adapters, at least the Club 3D CAC-1557 adapter, > incorrectly filter out HPD short pulses with a duration less than > ~540 usec, leading to MST probe failures. > > According to the DP Standard 2.0 section 5.1.4: > - DP sinks should generate short pulses in the 500 usec -> 1 msec range > - DP sources should detect short pulses in the 250 usec -> 2 msec range > > According to the DP Alt Mode on TypeC Standard section 3.9.2, adapters > should detect and forward short pulses according to how sources should > detect them as specified in the DP Standard (250 usec -> 2 msec). > > Based on the above filtering out short pulses with a duration less than > 540 usec is incorrect. > > To make such adapters work add support for a driver polling on MST > inerrupt flags, and wire this up in the i915 driver. The sink can clear > an interrupt it raised after 110 msec if the source doesn't respond, so > use a 50 msec poll period to avoid missing an interrupt. Polling of the > MST interrupt flags is explicitly allowed by the DP Standard. > > This fixes MST probe failures I saw using this adapter and a DELL U2515H > monitor. > > v2: > - Fix the wait event timeout for the no-poll case. > v3 (Ville): > - Fix the short pulse duration limits in the commit log prescribed by the > DP Standard. > - Add code comment explaining why/how polling is used. > - Factor out a helper to schedule the port's hpd irq handler and move it > to the rest of hotplug handlers. > - Document the new MST callback. > - s/update_hpd_irq_state/poll_hpd_irq/ > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 32 ++++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++ > drivers/gpu/drm/i915/display/intel_hotplug.c | 18 +++++++++++ > drivers/gpu/drm/i915/display/intel_hotplug.h | 2 ++ > include/drm/drm_dp_mst_helper.h | 9 ++++++ > 5 files changed, 68 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 5bc72e800b85..2a309fb2c4cc 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -1178,11 +1178,37 @@ static int drm_dp_mst_wait_tx_reply(struct drm_dp_mst_branch *mstb, > struct drm_dp_sideband_msg_tx *txmsg) > { > struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; > + unsigned long wait_timeout = msecs_to_jiffies(4000); > + unsigned long wait_expires = jiffies + wait_timeout; > int ret; > > - ret = wait_event_timeout(mgr->tx_waitq, > - check_txmsg_state(mgr, txmsg), > - (4 * HZ)); > + for (;;) { > + /* > + * If the driver provides a way for this, change to > + * poll-waiting for the MST reply interrupt if we didn't receive > + * it for 50 msec. This would cater for cases where the HPD > + * pulse signal got lost somewhere, even though the sink raised > + * the corresponding MST interrupt correctly. One example is the > + * Club 3D CAC-1557 TypeC -> DP adapter which for some reason > + * filters out short pulses with a duration less than ~540 usec. > + * > + * The poll period is 50 msec to avoid missing an interrupt > + * after the sink has cleared it (after a 110msec timeout > + * since it raised the interrupt). > + */ > + ret = wait_event_timeout(mgr->tx_waitq, > + check_txmsg_state(mgr, txmsg), > + mgr->cbs->poll_hpd_irq ? > + msecs_to_jiffies(50) : > + wait_timeout); > + > + if (ret || !mgr->cbs->poll_hpd_irq || > + time_after(jiffies, wait_expires)) > + break; > + > + mgr->cbs->poll_hpd_irq(mgr); > + } > + > mutex_lock(&mgr->qlock); > if (ret > 0) { > if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d18b406f2a7d..9be52643205d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -33,6 +33,7 @@ > #include "intel_connector.h" > #include "intel_ddi.h" > #include "intel_display_types.h" > +#include "intel_hotplug.h" > #include "intel_dp.h" > #include "intel_dp_mst.h" > #include "intel_dpio_phy.h" > @@ -765,8 +766,17 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo > return NULL; > } > > +static void > +intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) > +{ > + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); > + > + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); > +} > + > static const struct drm_dp_mst_topology_cbs mst_cbs = { > .add_connector = intel_dp_add_mst_connector, > + .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, > }; > > static struct intel_dp_mst_encoder * > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c > index 4f6f560e093e..664f88354101 100644 > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c > @@ -347,6 +347,24 @@ static void i915_digport_work_func(struct work_struct *work) > } > } > > +/** > + * intel_hpd_trigger_irq - trigger an hpd irq event for a port > + * @dig_port: digital port > + * > + * Trigger an HPD interrupt event for the given port, emulating a short pulse > + * generated by the sink, and schedule the dig port work to handle it. > + */ > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + > + spin_lock_irq(&i915->irq_lock); > + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); > + spin_unlock_irq(&i915->irq_lock); > + > + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); > +} > + > /* > * Handle hotplug events outside the interrupt handler proper. > */ > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h > index 777b0743257e..a704d7c94d16 100644 > --- a/drivers/gpu/drm/i915/display/intel_hotplug.h > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h > @@ -10,6 +10,7 @@ > > struct drm_i915_private; > struct intel_connector; > +struct intel_digital_port; > struct intel_encoder; > enum port; > > @@ -18,6 +19,7 @@ enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder, > struct intel_connector *connector); > void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, > u32 pin_mask, u32 long_mask); > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port); > void intel_hpd_init(struct drm_i915_private *dev_priv); > void intel_hpd_init_work(struct drm_i915_private *dev_priv); > void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 9e1ffcd7cb68..b230ff6f7081 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -475,6 +475,15 @@ struct drm_dp_mst_topology_mgr; > struct drm_dp_mst_topology_cbs { > /* create a connector for a port */ > struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); > + /* > + * Checks for any pending MST interrupts, passing them to MST core for > + * processing, the same way an HPD IRQ pulse handler would do this. > + * If provided MST core calls this callback from a poll-waiting loop > + * when waiting for MST down message replies. The driver is expected > + * to guard against a race between this callback and the driver's HPD > + * IRQ pulse handler. > + */ > + void (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *mgr); > }; > > #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Tue Jun 9 12:28:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 9 Jun 2020 13:28:56 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Incrementally check for rewinding Message-ID: <20200609122856.10207-1-chris@chris-wilson.co.uk> In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL"), we placed the check for rewinding a context on actually submitting the next request in that context. This was so that we only had to check once, and could do so with precision avoiding as many forced restores as possible. For example, to ensure that we can resubmit the same request a couple of times, we include a small wa_tail such that on the next submission, the ring->tail will appear to move forwards when resubmitting the same request. This is very common as it will happen for every lite-restore to fill the second port after a context switch. However, intel_ring_direction() is limited in precision to movements of upto half the ring size. The consequence being that if we tried to unwind many requests, we could exceed half the ring and flip the sense of the direction, so missing a force restore. As no request can be greater than half the ring (i.e. 2048 bytes in the smallest case), we can check for rollback incrementally. As we check against the tail that would be submitted, we do not lose any sensitivity and allow lite restores for the simple case. We still need to double check upon submitting the context, to allow for multiple preemptions and resubmissions. Fixes: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: <stable at vger.kernel.org> # v5.4+ --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++- drivers/gpu/drm/i915/gt/intel_ring.c | 4 + drivers/gpu/drm/i915/gt/selftest_mocs.c | 18 ++- drivers/gpu/drm/i915/gt/selftest_ring.c | 110 ++++++++++++++++++ .../drm/i915/selftests/i915_mock_selftests.h | 1 + 6 files changed, 154 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_ring.c diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e5141a897786..0a05301e00fb 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -646,7 +646,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) struct measure_breadcrumb { struct i915_request rq; struct intel_ring ring; - u32 cs[1024]; + u32 cs[2048]; }; static int measure_breadcrumb_dw(struct intel_context *ce) @@ -667,6 +667,8 @@ static int measure_breadcrumb_dw(struct intel_context *ce) frame->ring.vaddr = frame->cs; frame->ring.size = sizeof(frame->cs); + frame->ring.wrap = + BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); frame->ring.effective_size = frame->ring.size; intel_ring_update_space(&frame->ring); frame->rq.ring = &frame->ring; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index a057f7a2a521..f66274e60bb6 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1137,6 +1137,13 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) list_move(&rq->sched.link, pl); set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + /* Check for rollback incrementally */ + if (intel_ring_direction(rq->ring, + intel_ring_wrap(rq->ring, + rq->tail), + rq->ring->tail) <= 0) + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; + active = rq; } else { struct intel_engine_cs *owner = rq->context->engine; @@ -1505,8 +1512,9 @@ static u64 execlists_update_context(struct i915_request *rq) * HW has a tendency to ignore us rewinding the TAIL to the end of * an earlier request. */ + GEM_BUG_ON(ce->lrc_reg_state[CTX_RING_TAIL] != rq->ring->tail); + prev = rq->ring->tail; tail = intel_ring_set_tail(rq->ring, rq->tail); - prev = ce->lrc_reg_state[CTX_RING_TAIL]; if (unlikely(intel_ring_direction(rq->ring, tail, prev) <= 0)) desc |= CTX_DESC_FORCE_RESTORE; ce->lrc_reg_state[CTX_RING_TAIL] = tail; @@ -4758,6 +4766,14 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode) return 0; } +static void assert_request_valid(struct i915_request *rq) +{ + struct intel_ring *ring __maybe_unused = rq->ring; + + /* Can we unwind this request without appearing to go forwards? */ + GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0); +} + /* * Reserve space for 2 NOOPs at the end of each request to be * used as a workaround for not being allowed to do lite @@ -4770,6 +4786,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) *cs++ = MI_NOOP; request->wa_tail = intel_ring_offset(request, cs); + /* Check that entire request is less than half the ring */ + assert_request_valid(request); + return cs; } diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 8cda1b7e17ba..bdb324167ef3 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -315,3 +315,7 @@ int intel_ring_cacheline_align(struct i915_request *rq) GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); return 0; } + +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) +#include "selftest_ring.c" +#endif diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index 7bae64018ad9..b25eba50c88e 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -18,6 +18,20 @@ struct live_mocs { void *vaddr; }; +static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) +{ + struct intel_context *ce; + + ce = intel_context_create(engine); + if (IS_ERR(ce)) + return ce; + + /* We build large requests to read the registers from the ring */ + ce->ring = __intel_context_ring_size(SZ_16K); + + return ce; +} + static int request_add_sync(struct i915_request *rq, int err) { i915_request_get(rq); @@ -301,7 +315,7 @@ static int live_mocs_clean(void *arg) for_each_engine(engine, gt, id) { struct intel_context *ce; - ce = intel_context_create(engine); + ce = mocs_context_create(engine); if (IS_ERR(ce)) { err = PTR_ERR(ce); break; @@ -395,7 +409,7 @@ static int live_mocs_reset(void *arg) for_each_engine(engine, gt, id) { struct intel_context *ce; - ce = intel_context_create(engine); + ce = mocs_context_create(engine); if (IS_ERR(ce)) { err = PTR_ERR(ce); break; diff --git a/drivers/gpu/drm/i915/gt/selftest_ring.c b/drivers/gpu/drm/i915/gt/selftest_ring.c new file mode 100644 index 000000000000..2a8c534dc125 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/selftest_ring.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright ? 2020 Intel Corporation + */ + +static struct intel_ring *mock_ring(unsigned long sz) +{ + struct intel_ring *ring; + + ring = kzalloc(sizeof(*ring) + sz, GFP_KERNEL); + if (!ring) + return NULL; + + kref_init(&ring->ref); + ring->size = sz; + ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(sz); + ring->effective_size = sz; + ring->vaddr = (void *)(ring + 1); + atomic_set(&ring->pin_count, 1); + + intel_ring_update_space(ring); + + return ring; +} + +static void mock_ring_free(struct intel_ring *ring) +{ + kfree(ring); +} + +static int check_ring_direction(struct intel_ring *ring, + u32 next, u32 prev, + int expected) +{ + int result; + + result = intel_ring_direction(ring, next, prev); + if (result < 0) + result = -1; + else if (result > 0) + result = 1; + + if (result != expected) { + pr_err("intel_ring_direction(%u, %u):%d != %d\n", + next, prev, result, expected); + return -EINVAL; + } + + return 0; +} + +static int check_ring_step(struct intel_ring *ring, u32 x, u32 step) +{ + u32 prev = x, next = intel_ring_wrap(ring, x + step); + int err = 0; + + err |= check_ring_direction(ring, next, next, 0); + err |= check_ring_direction(ring, prev, prev, 0); + err |= check_ring_direction(ring, next, prev, 1); + err |= check_ring_direction(ring, prev, next, -1); + + return err; +} + +static int check_ring_offset(struct intel_ring *ring, u32 x, u32 step) +{ + int err = 0; + + err |= check_ring_step(ring, x, step); + err |= check_ring_step(ring, intel_ring_wrap(ring, x + 1), step); + err |= check_ring_step(ring, intel_ring_wrap(ring, x - 1), step); + + return err; +} + +static int igt_ring_direction(void *dummy) +{ + struct intel_ring *ring; + unsigned int half = 2048; + int step, err = 0; + + ring = mock_ring(2 * half); + if (!ring) + return -ENOMEM; + + GEM_BUG_ON(ring->size != 2 * half); + + /* Precision of wrap detection is limited to ring->size / 2 */ + for (step = 1; step < half; step <<= 1) { + err |= check_ring_offset(ring, 0, step); + err |= check_ring_offset(ring, half, step); + } + err |= check_ring_step(ring, 0, half - 64); + + /* And check unwrapped handling for good measure */ + err |= check_ring_offset(ring, 0, 2 * half + 64); + err |= check_ring_offset(ring, 3 * half, 1); + + mock_ring_free(ring); + return err; +} + +int intel_ring_mock_selftests(void) +{ + static const struct i915_subtest tests[] = { + SUBTEST(igt_ring_direction), + }; + + return i915_subtests(tests, NULL); +} diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h index 1929feba4e8e..3db34d3eea58 100644 --- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h +++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h @@ -21,6 +21,7 @@ selftest(fence, i915_sw_fence_mock_selftests) selftest(scatterlist, scatterlist_mock_selftests) selftest(syncmap, i915_syncmap_mock_selftests) selftest(uncore, intel_uncore_mock_selftests) +selftest(ring, intel_ring_mock_selftests) selftest(engine, intel_engine_cs_mock_selftests) selftest(timelines, intel_timeline_mock_selftests) selftest(requests, i915_request_mock_selftests) -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 9 12:45:34 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 9 Jun 2020 13:45:34 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200609124534.2322481-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Ramalingam C <ramalingam.c at intel.com> --- tests/i915/gem_exec_schedule.c | 699 +++++++++++++++++++++++++++++++++ 1 file changed, 699 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 56c638833..b3a1fedaa 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -29,6 +29,7 @@ #include <sys/poll.h> #include <sys/ioctl.h> #include <sys/mman.h> +#include <sys/resource.h> #include <sys/syscall.h> #include <sched.h> #include <signal.h> @@ -2495,6 +2496,666 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define RUNTIME (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(START_TS); + + while (offset_in_page(cs) & 63) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(NOW_TS); + + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + *cs++ = MI_STORE_DWORD_IMM; + if (use_64b) { + *cs++ = addr + 4064; + *cs++ = addr >> 32; + } else { + *cs++ = 0; + *cs++ = addr + 4064; + } + *cs++ = 0; + } + + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { ONE, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ONE) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ONE)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const uint32_t *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static struct intel_execution_engine2 +pick_random_engine(int i915, const struct intel_execution_engine2 *not) +{ + const struct intel_execution_engine2 *e; + unsigned int count = 0; + + __for_each_physical_engine(i915, e) { + if (e->flags == not->flags) + continue; + if (!gem_class_has_mutable_submission(i915, e->class)) + continue; + count++; + } + if (!count) + return *not; + + count = rand() % count; + __for_each_physical_engine(i915, e) { + if (e->flags == not->flags) + continue; + if (!gem_class_has_mutable_submission(i915, e->class)) + continue; + if (!count--) + break; + } + + return *e; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeline, + uint32_t common, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +#define F_SPARE (1 << 5) +#define F_NEXT (1 << 6) +#define F_VIP (1 << 7) +#define F_RRUL (1 << 8) +#define F_SHARE (1 << 9) +#define F_PING (1 << 10) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 obj[4] = { + {}, + { + .handle = common ?: gem_create(i915, 4096), + }, + delay_create(i915, ctx, e, frame_ns / batches_per_frame), + delay_create(i915, ctx, e, frame_ns / batches_per_frame), + }; + struct intel_execution_engine2 ping = *e; + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + int n; + + srandom(getpid()); + if (flags & F_PING) + ping = pick_random_engine(i915, e); + obj[0] = tslog_create(i915, ctx, &ping); + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(obj), + .buffer_count = 4, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_FLOW) { + unsigned int seq; + + seq = count; + if (flags & F_NEXT) + seq++; + + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, seq); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + close(execbuf.rsvd2); + + execbuf.buffer_count = 1; + execbuf.batch_start_offset = 2048; + execbuf.flags = ping.flags | I915_EXEC_FENCE_IN; + execbuf.rsvd2 = n_fence; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + igt_swap(obj[2], obj[3]); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, obj[3].handle); + gem_close(i915, obj[2].handle); + if (obj[1].handle != common) + gem_close(i915, obj[1].handle); + + gem_sync(i915, obj[0].handle); + if (out) { + uint32_t *map; + + map = gem_mmap__device_coherent(i915, obj[0].handle, + 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + } + gem_close(i915, obj[0].handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static uint64_t d_cpu_time(const struct rusage *a, const struct rusage *b) +{ + uint64_t cpu_time = 0; + + cpu_time += (a->ru_utime.tv_sec - b->ru_utime.tv_sec) * NSEC_PER_SEC; + cpu_time += (a->ru_utime.tv_usec - b->ru_utime.tv_usec) * 1000; + + cpu_time += (a->ru_stime.tv_sec - b->ru_stime.tv_sec) * NSEC_PER_SEC; + cpu_time += (a->ru_stime.tv_usec - b->ru_stime.tv_usec) * 1000; + + return cpu_time; +} + +static void timeline_advance(int timeline, int delay_ns) +{ + struct timespec tv = { .tv_nsec = delay_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + uint32_t common = 0; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + if (flags & F_SHARE) + common = gem_create(i915, 4095); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 64; n <<= 1) { /* 32 == 500us per client */ + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE)); + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct rusage old_usage, usage; + uint64_t cpu_time, d_time; + unsigned long vip = -1; + struct timespec tv; + struct igt_mean m; + + if (flags & F_PING) { + struct intel_execution_engine2 *ping; + + __for_each_physical_engine(i915, ping) { + if (ping->flags == e->flags) + continue; + + igt_fork(child, 1) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + fair_child(i915, ctx, ping, + child_ns / 8, + -1, common, + F_SOLO | F_PACE | F_SHARE, + &result[nchild], + NULL); + + gem_context_destroy(i915, ctx); + } + } + } + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + getrusage(RUSAGE_CHILDREN, &old_usage); + igt_nsec_elapsed(memset(&tv, 0, sizeof(tv))); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + if (flags & F_VIP && child == 0) { + gem_context_set_priority(i915, ctx, MAX_PRIO); + flags |= F_FLOW; + } + if (flags & F_RRUL && child == 0) + flags |= F_SOLO | F_FLOW | F_SYNC; + + fair_child(i915, ctx, e, child_ns, + timeline, common, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) + timeline_advance(timeline, fence_ns); + + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) + timeline_advance(timeline, fence_ns); + } + + igt_waitchildren(); + close(timeline); + + d_time = igt_nsec_elapsed(&tv); + getrusage(RUSAGE_CHILDREN, &usage); + cpu_time = d_cpu_time(&usage, &old_usage); + if (10 * cpu_time > 9 * d_time) { + if (nchild > 7) + break; + + igt_skip_on_f(10 * cpu_time > 9 * d_time, + "%.0f%% CPU usage, presuming capacity exceeded\n", + 100.* cpu_time / d_time); + } + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + if (flags & (F_VIP | F_RRUL)) + vip = result[0]; + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + + if (vip != -1) { + igt_info("VIP interval %.2f ms\n", 1e-6 * vip); + igt_assert(4 * vip > 3 * fence_ns && + 3 * vip < 4 * fence_ns); + } + + /* May be slowed due to sheer volume of context switches */ + igt_assert(4 * igt_mean_get(&m) > 3 * fence_ns && + igt_mean_get(&m) < 3 * fence_ns); + + igt_assert(4 * igt_mean_get(&m) > 3 * result[nchild / 2] && + 3 * igt_mean_get(&m) < 4 * result[nchild / 2]); + + igt_assert(2 * (result[hi] - result[lo]) < result[nchild / 2]); + } + + munmap(result, 4096); + if (common) + gem_close(i915, common); +} + +static uint32_t read_ctx_timestamp(int i915, + uint32_t ctx, + const struct intel_execution_engine2 *e) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); + struct drm_i915_gem_relocation_entry reloc; + struct drm_i915_gem_exec_object2 obj = { + .handle = gem_create(i915, 4096), + .offset = 32 << 20, + .relocs_ptr = to_user_pointer(&reloc), + .relocation_count = 1, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .flags = e->flags, + .rsvd1 = ctx, + }; +#define RUNTIME (base + 0x3a8) + uint32_t *map, *cs; + uint32_t ts; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, obj.handle, + 0, 4096, PROT_WRITE); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = RUNTIME; + memset(&reloc, 0, sizeof(reloc)); + reloc.target_handle = obj.handle; + reloc.presumed_offset = obj.offset; + reloc.offset = offset_in_page(cs); + reloc.delta = 4000; + *cs++ = obj.offset + 4000; + *cs++ = obj.offset >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + gem_close(i915, obj.handle); + + ts = map[1000]; + munmap(map, 4096); + + return ts; +} + +static void fairslice(int i915, const struct intel_execution_engine2 *e) +{ + igt_spin_t *spin[3]; + uint32_t ctx[3]; + uint32_t ts[3]; + + igt_require(gem_scheduler_has_semaphores(i915)); + igt_require(gem_scheduler_has_preemption(i915)); + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + + for (int i = 0; i < ARRAY_SIZE(ctx); i++) { + ctx[i] = gem_context_clone_with_engines(i915, 0); + spin[i] = igt_spin_new(i915, .ctx = ctx[i], .engine = e->flags); + } + + sleep(2); /* over the course of many timeslices */ + + for (int i = 0; i < ARRAY_SIZE(ctx); i++) { + igt_assert(gem_bo_busy(i915, spin[i]->handle)); + igt_spin_end(spin[i]); + + ts[i] = read_ctx_timestamp(i915, ctx[i], e); + } + + for (int i = 0; i < ARRAY_SIZE(ctx); i++) { + igt_spin_free(i915, spin[i]); + gem_context_destroy(i915, ctx[i]); + } + + qsort(ts, 3, sizeof(*ts), cmp_u32); + igt_info("%s: [%.1f, %.1f] ms\n", e->name, + 1e-6 * ticks_to_ns(i915, ts[0]), + 1e-6 * ticks_to_ns(i915, ts[2])); + + igt_assert(ts[0] && ts[2] > ts[0]); + igt_assert(4 * ts[0] > 3 * ts[2]); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2561,6 +3222,9 @@ igt_main test_each_engine("lateslice", fd, e) lateslice(fd, e->flags); + test_each_engine("fairslice", fd, e) + fairslice(fd, e); + test_each_engine("submit-early-slice", fd, e) submit_slice(fd, e, EARLY_SUBMIT); test_each_engine("submit-golden-slice", fd, e) @@ -2589,6 +3253,41 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_each_engine_store("fair-none", fd, e) + fairness(fd, e, 2, 0); + test_each_engine_store("fair-none-vip", fd, e) + fairness(fd, e, 2, F_VIP); + test_each_engine_store("fair-none-share", fd, e) + fairness(fd, e, 2, F_SHARE); + test_each_engine_store("fair-none-rrul", fd, e) + fairness(fd, e, 2, F_RRUL); + test_each_engine_store("fair-none-ping", fd, e) + fairness(fd, e, 2, F_PING); + test_each_engine_store("fair-pace", fd, e) + fairness(fd, e, 2, F_PACE); + test_each_engine_store("fair-pace-share", fd, e) + fairness(fd, e, 2, F_PACE | F_SHARE); + test_each_engine_store("fair-pace-ping", fd, e) + fairness(fd, e, 2, F_PACE | F_SHARE | F_PING); + test_each_engine_store("fair-sync", fd, e) + fairness(fd, e, 2, F_SYNC); + test_each_engine_store("fair-sync-vip", fd, e) + fairness(fd, e, 2, F_SYNC | F_VIP); + test_each_engine_store("fair-solo", fd, e) + fairness(fd, e, 2, F_SYNC | F_SOLO); + test_each_engine_store("fair-flow", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW); + test_each_engine_store("fair-flow-ping", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_PING); + test_each_engine_store("fair-next", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_NEXT); + test_each_engine_store("fair-next-share", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_NEXT | F_SHARE); + test_each_engine_store("fair-spare", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_SPARE); + test_each_engine_store("fair-half", fd, e) + fairness(fd, e, 2, F_PACE | F_FLOW | F_HALF); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0 From patchwork at emeril.freedesktop.org Tue Jun 9 12:47:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 12:47:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gt=3A_Incrementally_check_for_rewinding?= In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <159170686652.17060.18319086847110725343@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Incrementally check for rewinding URL : https://patchwork.freedesktop.org/series/78163/ State : warning == Summary == $ dim checkpatch origin/drm-tip e9fc78f4bfec drm/i915/gt: Incrementally check for rewinding -:165: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #165: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 222 lines checked From daniel at ffwll.ch Tue Jun 9 13:02:14 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 9 Jun 2020 15:02:14 +0200 Subject: [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny In-Reply-To: <CY4PR1201MB013654230A216EE7EB3C0E9BDE820@CY4PR1201MB0136.namprd12.prod.outlook.com> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-54-daniel.vetter@ffwll.ch> <20200415094512.GA30444@ravnborg.org> <MWHPR12MB14532DA5713E3B579ABFE1F4A1DB0@MWHPR12MB1453.namprd12.prod.outlook.com> <CAKMK7uGDGgt8Cm_bFoyzeoP2CWyiUNdUwb7GL6Ohu3k0rP0p1w@mail.gmail.com> <20200428140842.GL3456981@phenom.ffwll.local> <CH2PR12MB3894B40C6D71435D3E759A34A1A20@CH2PR12MB3894.namprd12.prod.outlook.com> <CAKMK7uFRt14m24ajYygdRZz=fUMhA9u6=590R2jjhXGq=VtwNA@mail.gmail.com> <20200604080507.GT20149@phenom.ffwll.local> <CY4PR1201MB01363EB95985A2C64ADA6841DE890@CY4PR1201MB0136.namprd12.prod.outlook.com> <CAKMK7uFLvV3=uhfnf=MreKBM==-gzXqx3NrV8KDA2D5sTAn2SQ@mail.gmail.com> <CY4PR1201MB013642EB94E07AED91813A5FDE890@CY4PR1201MB0136.namprd12.prod.outlook.com> <CAKMK7uESUnLR1N07T513RjGUAp8FA6oHaO1Y+uvTKpFuM_8+gQ@mail.gmail.com> <CY4PR1201MB013654230A216EE7EB3C0E9BDE820@CY4PR1201MB0136.namprd12.prod.outlook.com> Message-ID: <CAKMK7uFHCTkqoMGBW3QMjhJZaaakC_zYxxVW_C-LYRj0Yjt2gg@mail.gmail.com> Hi Eugeniy, Very much appreciated, and kinda expected. That 2nd backtrace really confuses me, so "something strange is going on" and the bisect looks funny is within expectations. Hopefully we can track down what's going on. Thanks, Daniel On Tue, Jun 9, 2020 at 2:08 PM Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com> wrote: > > Hi Daniel, > > I've got pretty strange results so I need some time to investigate it and probably retest. > I'll send you update in a few days. > > --- > Eugeniy Paltsev > > > ________________________________________ > From: Daniel Vetter <daniel at ffwll.ch> > Sent: Friday, June 5, 2020 22:55 > To: Eugeniy Paltsev > Cc: Intel Graphics Development; DRI Development; Daniel Vetter; Sam Ravnborg; Alexey Brodkin; snps-arc at lists.infradead.org > Subject: Re: [PATCH 53/59] drm/arc: Move to drm/tiny > > Hi Eugeniy, > > Thanks for testing. I looked at the second one (I hoped it would just > magically disappear) and I still don't understand what's going on > there. My patch series isn't touching that area at all, so really > confused. > > I squashed in the bugfix from the previous round into the right > patches, and pushed a branch with just the arcpgu changes here: > https://urldefense.com/v3/__https://cgit.freedesktop.org/*danvet/drm/log/?h=for-eugeniy__;fg!!A4F2R9G_pg!IJ1o4XiXVdStPu--Q-SCTUpRbsbqrjX255R34nuD7L7ptPywOy4SKr21dwSpfOkXIVqH5pM$ > > Maybe it's something in my pile of not-so-tested stuff :-) > > Can you pls test this? And if it still fails, try to bisect where it breaks? > > Thanks, Daniel > > On Thu, Jun 4, 2020 at 9:00 PM Eugeniy Paltsev > <Eugeniy.Paltsev at synopsys.com> wrote: > > > > I've tested your change and one issue gone. > > > > However I still see kernel crash (due to invalid read in kernel mode by 0x0 address) on weston stop: > > ----------------------------------->8------------------------------------------- > > Oops > > Path: (null) > > CPU: 0 PID: 12 Comm: kworker/0:1 Not tainted 5.7.0-rc6-01594-g4ceda91a4176-dirty #6 > > Workqueue: events drm_mode_rmfb_work_fn > > Invalid Read @ 0x00000000 by insn @ drm_gem_fb_destroy+0x32/0x130 > > ECR: 0x00050100 EFA: 0x00000000 ERET: 0x813b9a76 > > STAT32: 0x80080602 [IE K ] BTA: 0x813b9a72 > > BLK: drm_gem_fb_destroy+0xc0/0x130 > > SP: 0x9f055ea4 FP: 0x00000000 > > LPS: 0x813560ec LPE: 0x813560f0 LPC: 0x00000000 > > r00: 0x00000000 r01: 0x9f6a6100 r02: 0x00000001 > > r03: 0x9fd5dde8 r04: 0x810f5de8 r05: 0x00000000 > > r06: 0x00000000 r07: 0x00000000 r08: 0x000000e1 > > r09: 0x00000000 r10: 0x00000000 r11: 0x000000e1 > > r12: 0x813b9b04 > > > > Stack Trace: > > drm_gem_fb_destroy+0x32/0x130 > > drm_framebuffer_remove+0x1d2/0x358 > > drm_mode_rmfb_work_fn+0x28/0x38 > > process_one_work+0x19a/0x358 > > worker_thread+0x2c4/0x494 > > kthread+0xec/0x100 > > ret_from_fork+0x18/0x1c > > ----------------------------------->8------------------------------------------- > > > > > > The stack traces may vary but always end in drm_gem_fb_destroy: > > ----------------------------------->8------------------------------------------- > > Stack Trace: > > drm_gem_fb_destroy+0x32/0x130 > > drm_mode_rmfb+0x10e/0x148 > > drm_ioctl_kernel+0x70/0xa0 > > drm_ioctl+0x284/0x410 > > ksys_ioctl+0xea/0xa3c > > EV_Trap+0xcc/0xd0 > > ----------------------------------->8------------------------------------------- > > Stack Trace: > > drm_gem_fb_destroy+0x32/0x130 > > drm_fb_release+0x66/0xb0 > > drm_file_free.part.11+0x112/0x1bc > > drm_release+0x80/0x120 > > __fput+0x98/0x1bc > > task_work_run+0x6e/0xa8 > > do_exit+0x2b4/0x7fc > > do_group_exit+0x2a/0x8c > > get_signal+0x9a/0x5f0 > > do_signal+0x86/0x23c > > resume_user_mode_begin+0x88/0xd0 > > ----------------------------------->8------------------------------------------- > > > > > > --- > > Eugeniy Paltsev > > > > > > ________________________________________ > > From: Daniel Vetter <daniel at ffwll.ch> > > Sent: Thursday, June 4, 2020 14:19 > > To: Eugeniy Paltsev > > Cc: Intel Graphics Development; DRI Development; Daniel Vetter; Sam Ravnborg; Alexey Brodkin > > Subject: Re: [PATCH 53/59] drm/arc: Move to drm/tiny > > > > Hi Eugeniy, > > > > Apologies, somehow I missed your mail. I looked at the code again, and I > > think I fumbled something. Does the below diff help to prevent the issues? > > > > Thanks, Daniel > > > > > > diff --git a/drivers/gpu/drm/tiny/arcpgu.c b/drivers/gpu/drm/tiny/arcpgu.c > > index 857812f25bec..33d812a5ad7f 100644 > > --- a/drivers/gpu/drm/tiny/arcpgu.c > > +++ b/drivers/gpu/drm/tiny/arcpgu.c > > @@ -228,6 +228,9 @@ static void arc_pgu_update(struct drm_simple_display_pipe *pipe, > > struct arcpgu_drm_private *arcpgu; > > struct drm_gem_cma_object *gem; > > > > + if (!pipe->plane.state->fb) > > + return; > > + > > arcpgu = pipe_to_arcpgu_priv(pipe); > > gem = drm_fb_cma_get_gem_obj(pipe->plane.state->fb, 0); > > arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr); > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > +41 (0) 79 365 57 48 - https://urldefense.com/v3/__http://blog.ffwll.ch__;!!A4F2R9G_pg!P0EvyJfMuDwqbeZmHZM5S9po30QWr4KgGrggRirNfgo7wrRXfnUO-8iq0AA4fQCW2WGPlDc$ > > > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - https://urldefense.com/v3/__http://blog.ffwll.ch__;!!A4F2R9G_pg!IJ1o4XiXVdStPu--Q-SCTUpRbsbqrjX255R34nuD7L7ptPywOy4SKr21dwSpfOkXpn86Q20$ -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From joonas.lahtinen at linux.intel.com Tue Jun 9 13:06:07 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Tue, 09 Jun 2020 16:06:07 +0300 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver In-Reply-To: <87ftb6x7em.fsf@intel.com> References: <2136072.1591491984@warthog.procyon.org.uk> <87o8puxak1.fsf@intel.com> <4ff2445aff8d44c5961a6d194a8f4663@intel.com> <87ftb6x7em.fsf@intel.com> Message-ID: <159170796747.14701.11248955335455539280@jlahtine-desk.ger.corp.intel.com> Quoting Jani Nikula (2020-06-08 11:56:33) > On Mon, 08 Jun 2020, "Saarinen, Jani" <jani.saarinen at intel.com> wrote: > > HI, > >> -----Original Message----- > >> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Jani Nikula > >> Sent: maanantai 8. kes?kuuta 2020 10.49 > >> To: David Howells <dhowells at redhat.com>; Joonas Lahtinen > >> <joonas.lahtinen at linux.intel.com>; Vivi, Rodrigo <rodrigo.vivi at intel.com> > >> Cc: intel-gfx at lists.freedesktop.org; linux-kernel at vger.kernel.org; dri- > >> devel at lists.freedesktop.org; dhowells at redhat.com; airlied at redhat.com > >> Subject: Re: [Intel-gfx] A panic and a hang in the i915 drm driver > >> > >> On Sun, 07 Jun 2020, David Howells <dhowells at redhat.com> wrote: > >> > Hi, > >> > > >> > I'm seeing the attached oops and panic from the i915 drm driver. I've tried > >> > bisecting it, but there's a problem in that one of the merged branches causes > >> > the machine to hang without output. > > It was not this one? > > https://gitlab.freedesktop.org/drm/intel/-/issues/1892 > > David, please try [1]. > > Joonas, I think it would be good to have a pull request with that before > -rc1 is out. I think the bug is in Linus' tree already but the fix > didn't have the annotation. :( Cherry-picked the fix now. Thanks for highlighting this. I'll send the PR tomorrow when CI results have arrived. Regards, Joonas > BR, > Jani. > > > > [1] https://cgit.freedesktop.org/drm/drm-tip/commit/?id=22da5d846d54dd13183b57874b9d5611d583d7c8 > > > > > > > >> > >> Cc: Ville and GG, I thought this was fixed (reverted) already. > >> > >> BR, > >> Jani. > >> > >> > >> > > >> > The oops for commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 looks like: > >> > > >> > BUG: kernel NULL pointer dereference, address: 0000000000000000 > >> > #PF: supervisor read access in kernel mode > >> > #PF: error_code(0x0000) - not-present page > >> > PGD 0 P4D 0 > >> > Oops: 0000 [#1] SMP PTI > >> > CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.7.0-rc2-fscache+ #883 > >> > Hardware name: ASUS All Series/H97-PLUS, BIOS 2306 10/09/2014 > >> > RIP: 0010:intel_psr_enabled+0xb/0x6e > >> > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d > >> 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 > >> 00 20 75 05 45 31 e4 eb 44 80 > >> > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 > >> > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 > >> > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 > >> > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 > >> > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 > >> > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 > >> > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) > >> knlGS:0000000000000000 > >> > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > >> > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 > >> > Call Trace: > >> > intel_read_dp_sdp+0x71/0x2c5 > >> > hsw_crt_get_config+0x18/0x41 > >> > intel_modeset_readout_hw_state+0x24d/0x662 > >> > ? do_raw_spin_lock+0x8b/0xcd > >> > ? _raw_spin_lock_irqsave+0x10/0x16 > >> > intel_modeset_setup_hw_state+0xa8/0xb59 > >> > ? __next_node_in+0x39/0x42 > >> > ? ww_mutex_lock+0x3d/0x1da > >> > ? modeset_lock+0xd4/0x114 > >> > ? drm_modeset_lock_all_ctx+0x86/0xcc > >> > intel_modeset_init+0x285/0x5bf > >> > ? intel_irq_postinstall+0x485/0x4d1 > >> > i915_driver_probe+0x1b4/0x49c > >> > ? __kernfs_new_node+0x161/0x1b2 > >> > ? rpm_resume+0x45e/0x485 > >> > i915_pci_probe+0xfd/0x11d > >> > ? __pm_runtime_resume+0x51/0x5e > >> > local_pci_probe+0x39/0x7a > >> > pci_device_probe+0xf5/0x14f > >> > ? sysfs_do_create_link_sd.isra.0+0x77/0xa3 > >> > really_probe+0x140/0x2a9 > >> > driver_probe_device+0x9c/0xd1 > >> > device_driver_attach+0x3c/0x55 > >> > __driver_attach+0x97/0x9f > >> > ? device_driver_attach+0x55/0x55 > >> > bus_for_each_dev+0x72/0xa8 > >> > bus_add_driver+0x108/0x1b9 > >> > driver_register+0x9e/0xd7 > >> > ? mipi_dsi_bus_init+0x11/0x11 > >> > i915_init+0x58/0x6b > >> > do_one_initcall+0x83/0x18a > >> > kernel_init_freeable+0x19b/0x1fd > >> > ? rest_init+0x9f/0x9f > >> > kernel_init+0xa/0xfa > >> > ret_from_fork+0x1f/0x30 > >> > Modules linked in: > >> > CR2: 0000000000000000 > >> > ---[ end trace d0c4f561618aeb37 ]--- > >> > RIP: 0010:intel_psr_enabled+0xb/0x6e > >> > Code: 8b 44 24 08 65 48 33 04 25 28 00 00 00 74 05 e8 7e ff 97 ff 48 83 c4 10 5b 5d > >> 41 5c 41 5d c3 0f 1f 44 00 00 41 55 41 54 55 53 <48> 8b 9f d8 fe ff ff f6 83 5e 08 00 > >> 00 20 75 05 45 31 e4 eb 44 80 > >> > RSP: 0000:ffff88840dedfa18 EFLAGS: 00010246 > >> > RAX: 0000000000000000 RBX: ffff8884086f9000 RCX: 0000000000000000 > >> > RDX: 0000000000000001 RSI: ffff8884086f9000 RDI: 0000000000000128 > >> > RBP: ffff8884086fb000 R08: 0000000000000000 R09: 0000000000000001 > >> > R10: 0000000000000001 R11: 00000000000000ff R12: ffff888408680000 > >> > R13: 0000000000000000 R14: 0000000000000000 R15: ffff8884086fb200 > >> > FS: 0000000000000000(0000) GS:ffff88840fb00000(0000) > >> knlGS:0000000000000000 > >> > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > >> > CR2: 0000000000000000 CR3: 000000000440c001 CR4: 00000000001606e0 > >> > Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 > >> > Kernel Offset: disabled > >> > ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 ]--- > >> > > >> > > >> > Decoding the RIP gives: > >> > > >> > RIP: 0010:intel_psr_enabled (/data/fs/linux- > >> fs/build3/../drivers/gpu/drm/i915/display/intel_display_types.h:1595 /data/fs/linux- > >> fs/build3/../drivers/gpu/drm/i915/display/intel_psr.c:1598) > >> > > >> > > >> > > >> > Commit c41219fda6e04255c44d37fd2c0d898c1c46abf1 ("Merge tag > >> > 'drm-intel-next-fixes-2020-05-20' of > >> > git://anongit.freedesktop.org/drm/drm-intel into drm-next") is definitely bad > >> > and logs an oops to the console and panics, but it's a merge. > >> > > >> > On one side is e20bb857dea2f620ff37ae541ed8aee70e3c89f1 ("Merge tag > >> > 'exynos-drm-next-for-v5.8' of > >> > git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into > >> > drm-next"), which hangs. This is also a merge. > >> > > >> > One side of e20bb is f84e1ba336a4f47ae251e4d2d8a694902571b0df > >> > ("drm/exynos-vidi: convert platform driver to use dev_groups") which is good. > >> > > >> > The other side of c4121 and e20bb derive from the same line of commits, with > >> > three patches between. All of these, down to at least > >> > 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 ("drm/i915: Update DRIVER_DATE > >> to > >> > 20200430") cause the machine to hang without any sort of console output. > >> > > >> > Commit bfbe1744e4417986419236719922a9a7fda224d1 ("Merge tag > >> > 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux > >> > into drm-next") is good. > >> > > >> > Commit 47e51832ae93534d872511ba557115722582d94c > >> > ("drm/i915/gvt: use context lrc_reg_state for shadow ppgtt override") is good. > >> > > >> > I've attached the git log and the config file. > >> > > >> > David > >> > > >> > git bisect start > >> > # bad: [ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d] afs: Fix file locking > >> > git bisect bad ad09aeb7d10d8003cb208a7d2d8e5c7fa63b767d > >> > # good: [3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162] Linux 5.7 > >> > git bisect good 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162 > >> > # bad: [2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63] Merge branch > >> 'uaccess.comedi' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs > >> > git bisect bad 2e63f6ce7ed2c4ff83ba30ad9ccad422289a6c63 > >> > # good: [cfa3b8068b09f25037146bfd5eed041b78878bee] Merge tag 'for-linus- > >> hmm' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma > >> > git bisect good cfa3b8068b09f25037146bfd5eed041b78878bee > >> > # bad: [c41219fda6e04255c44d37fd2c0d898c1c46abf1] Merge tag 'drm-intel-next- > >> fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next > >> > git bisect bad c41219fda6e04255c44d37fd2c0d898c1c46abf1 > >> > # good: [937eea297e26effac6809a0bf8c20e6ca9d90b9a] Merge tag 'amd-drm- > >> next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-next > >> > git bisect good 937eea297e26effac6809a0bf8c20e6ca9d90b9a > >> > # good: [a1fb548962397bb8609bb46e566809a9a1b30044] Merge tag 'drm-intel- > >> next-2020-04-30' of git://anongit.freedesktop.org/drm/drm-intel into drm-next > >> > git bisect good a1fb548962397bb8609bb46e566809a9a1b30044 > >> > # good: [f84e1ba336a4f47ae251e4d2d8a694902571b0df] drm/exynos-vidi: > >> convert platform driver to use dev_groups > >> > git bisect good f84e1ba336a4f47ae251e4d2d8a694902571b0df > >> > # skip: [d9162348db12487754e61f73497bdcfcea753590] drm/i915: Introduce > >> skl_plane_wm_level accessor. > >> > git bisect skip d9162348db12487754e61f73497bdcfcea753590 > >> > # skip: [84eac0c65940d9633247b0c8c826d4bcb7307351] drm/i915/gt: Force pte > >> cacheline to main memory > >> > git bisect skip 84eac0c65940d9633247b0c8c826d4bcb7307351 > >> > # skip: [802a5820fc0c0f12b40280db3dbaaf8359b07243] drm/i915: Extract > >> i915_cs_timestamp_{ns_to_ticks,tick_to_ns}() > >> > git bisect skip 802a5820fc0c0f12b40280db3dbaaf8359b07243 > >> > # skip: [1c8ee8b92fb6ac9d5975147cc902e8c142eca338] drm/i915/gt: Restore > >> Cherryview back to full-ppgtt > >> > git bisect skip 1c8ee8b92fb6ac9d5975147cc902e8c142eca338 > >> > # skip: [2e2701582a8039b2f8a2fa811237ac8ec98355fa] drm/i915: Nuke pointless > >> div by 64bit > >> > git bisect skip 2e2701582a8039b2f8a2fa811237ac8ec98355fa > >> > # skip: [4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc] drm/i915/gt: Suspend > >> tasklets before resume sanitization > >> > git bisect skip 4a0ca47a8e2fdfb7c9f5b23bba79fa632a5cd8fc > >> > # skip: [20f505f2253106f695ba6fa0a415159145a8fb2a] drm/i915: Restrict qgv > >> points which don't have enough bandwidth. > >> > git bisect skip 20f505f2253106f695ba6fa0a415159145a8fb2a > >> > # skip: [d8d5afe35e3f88f73436f79f974d96a67e879637] drm/i915: Make > >> active_pipes check skl specific > >> > git bisect skip d8d5afe35e3f88f73436f79f974d96a67e879637 > >> > # skip: [1be8f347d70b5027b7b223c665756d85feaf36b6] Merge tag 'gvt-next- > >> 2020-05-12' of https://github.com/intel/gvt-linux into drm-intel-next-queued > >> > git bisect skip 1be8f347d70b5027b7b223c665756d85feaf36b6 > >> > # skip: [b428d57006663d18e3f6f98644ff9e8702a33ca4] drm/i915/gt: Reset > >> execlists registers before HWSP > >> > git bisect skip b428d57006663d18e3f6f98644ff9e8702a33ca4 > >> > # skip: [6b6cd2ebd8d071e55998e32b648bb8081f7f02bb] drm/i915: Mark > >> concurrent submissions with a weak-dependency > >> > git bisect skip 6b6cd2ebd8d071e55998e32b648bb8081f7f02bb > >> > # skip: [1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0] drm/i915: Extract skl SAGV > >> checking > >> > git bisect skip 1d0a6c8486aa53f7545e80f5f0293ed99e48ffc0 > >> > # skip: [cafac5a983619944afa639c53f0d5d885616a3d2] drm/i915/dp: Add > >> compute routine for DP PSR VSC SDP > >> > git bisect skip cafac5a983619944afa639c53f0d5d885616a3d2 > >> > # skip: [61b088c5374a9f886efa1edbb49ce552bd1f9cba] drm/i915/ehl: Restrict > >> w/a 1607087056 for EHL/JSL > >> > git bisect skip 61b088c5374a9f886efa1edbb49ce552bd1f9cba > >> > # skip: [2045d666ae634f1676660acfb864bcba0e9f86ca] drm/i915: Ignore submit- > >> fences on the same timeline > >> > git bisect skip 2045d666ae634f1676660acfb864bcba0e9f86ca > >> > # skip: [16e87459673a5cbef35cc0f2e15c664b10a4cdb6] drm/i915/gt: Move the > >> batch buffer pool from the engine to the gt > >> > git bisect skip 16e87459673a5cbef35cc0f2e15c664b10a4cdb6 > >> > # skip: [ce58867ee17afecda7917e74a0d10afd7138c6d4] drm/i915: Fix enabled > >> infoframe states of lspcon > >> > git bisect skip ce58867ee17afecda7917e74a0d10afd7138c6d4 > >> > # skip: [a211da9c771bf97395a3ced83a3aa383372b13a7] drm/i915/gt: Make > >> timeslicing an explicit engine property > >> > git bisect skip a211da9c771bf97395a3ced83a3aa383372b13a7 > >> > # skip: [dee66f3e071b394de16da18e2807f371b789b1be] drm/i915: Add state > >> readout for DP HDR Metadata Infoframe SDP > >> > git bisect skip dee66f3e071b394de16da18e2807f371b789b1be > >> > # skip: [964a9b0f611ee7fedc90641bfcc2efe6ce6206aa] drm/i915/gem: Use > >> chained reloc batches > >> > git bisect skip 964a9b0f611ee7fedc90641bfcc2efe6ce6206aa > >> > # skip: [f1e79c7e183c8e35def44b07ff7ac221fa87bf04] drm/i915: Replace zero- > >> length array with flexible-array > >> > git bisect skip f1e79c7e183c8e35def44b07ff7ac221fa87bf04 > >> > # good: [ab9c21124d6e03460c9c59006a61cc076fefa82e] drm/amdgpu: Add cmd > >> to control XGMI link sleep > >> > git bisect good ab9c21124d6e03460c9c59006a61cc076fefa82e > >> > # skip: [e31fe02eff2610f40ac8d7efe57ec0b881b75508] drm/i915: Make > >> intel_timeline_init static > >> > git bisect skip e31fe02eff2610f40ac8d7efe57ec0b881b75508 > >> > # skip: [d96536f0fe699729a0974eb5b65eb0d87cc747e1] drm/i915: Fix AUX power > >> domain toggling across TypeC mode resets > >> > git bisect skip d96536f0fe699729a0974eb5b65eb0d87cc747e1 > >> > # skip: [a80d73673bc7676d0bab7f7ab51d00c5e461992d] drm/i915: Tidy awaiting > >> on dma-fences > >> > git bisect skip a80d73673bc7676d0bab7f7ab51d00c5e461992d > >> > # skip: [25444ca6cbb9fe375aa9bba58784a735efe2a649] drm/i915/fbc: Require > >> linear fb stride to be multiple of 512 bytes on gen9/glk > >> > git bisect skip 25444ca6cbb9fe375aa9bba58784a735efe2a649 > >> > # skip: [795d4d7fa34154fc621c1048f8b92e4f6bd3926f] drm/i915: Mark the > >> addition of the initial-breadcrumb in the request > >> > git bisect skip 795d4d7fa34154fc621c1048f8b92e4f6bd3926f > >> > # skip: [d19b29be653691a179e54aafc84fc40667a63ee7] drm/i915: Nuke > >> mode.vrefresh usage > >> > git bisect skip d19b29be653691a179e54aafc84fc40667a63ee7 > >> > # skip: [260a6c1bdf1e072ae4d96f0d1ec2917237f1b627] drm/i915: Fix glk > >> watermark calculations > >> > git bisect skip 260a6c1bdf1e072ae4d96f0d1ec2917237f1b627 > >> > # skip: [56f1b31f1dd60db4b02024a13eea45b5bbccc44e] drm/i915: Store CS > >> timestamp frequency in Hz > >> > git bisect skip 56f1b31f1dd60db4b02024a13eea45b5bbccc44e > >> > # skip: [b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d] drm/i915: Remove > >> duplicate inline specifier on write_pte > >> > git bisect skip b2379ba2b9c207f6a76b4b8c3d7252a82cfd8f7d > >> > # skip: [0065e5f5cc56136da0be900c4a3121b38a82f37d] drm/i915/display: Warn if > >> the FBC is still writing to stolen on removal > >> > git bisect skip 0065e5f5cc56136da0be900c4a3121b38a82f37d > >> > # skip: [0398993b82f40ad02d88da7c894e3faae2da3b0a] drm/i915: Stash hpd > >> status bits under dev_priv > >> > git bisect skip 0398993b82f40ad02d88da7c894e3faae2da3b0a > >> > # skip: [7241c57d3140ad3b613777a8515ffe1f653d4800] drm/i915: Add TGL+ SAGV > >> support > >> > git bisect skip 7241c57d3140ad3b613777a8515ffe1f653d4800 > >> > # skip: [c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5] drm/i915: Use stashed > >> away hpd isr bits in intel_digital_port_connected() > >> > git bisect skip c7e8a3d674fbaa5b12ddc681bdf46c34a27e55d5 > >> > # skip: [f136c58a0de98e1b56483b7fc8c209dba0a496d9] drm/i915: Added required > >> new PCode commands > >> > git bisect skip f136c58a0de98e1b56483b7fc8c209dba0a496d9 > >> > # skip: [9bad40a27dac1f88012a1e2db0bfc5ae58fa0370] drm/i915/selftests: > >> Always flush before unpining after writing > >> > git bisect skip 9bad40a27dac1f88012a1e2db0bfc5ae58fa0370 > >> > # skip: [977253df6433f85d5e2cb3ab0f8eb4127f8173dd] drm/i915/gt: Stop holding > >> onto the pinned_default_state > >> > git bisect skip 977253df6433f85d5e2cb3ab0f8eb4127f8173dd > >> > # skip: [a1b2eeacbc55573afc56341e08b506aee6451c3d] drm/i915: Remove > >> unused HAS_FWTABLE macro > >> > git bisect skip a1b2eeacbc55573afc56341e08b506aee6451c3d > >> > # skip: [24fe5f2ab2478053d50a3bc629ada895903a5cbc] drm/i915: Propagate > >> error from completed fences > >> > git bisect skip 24fe5f2ab2478053d50a3bc629ada895903a5cbc > >> > # skip: [73e28cc40bf00b5d168cb8f5cff1ae63e9097446] drm/i915: Handle idling > >> during i915_gem_evict_something busy loops > >> > git bisect skip 73e28cc40bf00b5d168cb8f5cff1ae63e9097446 > >> > # skip: [f02ac414ba9497d1887b1de7fe69954284f157ac] Revert "drm/i915/tgl: > >> Include ro parts of l3 to invalidate" > >> > git bisect skip f02ac414ba9497d1887b1de7fe69954284f157ac > >> > # skip: [b0a997ae5248b293b6f6d1996ea49c57f7b94227] drm/i915: Emit > >> await(batch) before MI_BB_START > >> > git bisect skip b0a997ae5248b293b6f6d1996ea49c57f7b94227 > >> > # skip: [32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa] drm/i915/gen12: Fix HDC > >> pipeline flush > >> > git bisect skip 32d7171ee2ae6e19c63b826904cf62d3d5a7f6fa > >> > # good: [5e7067b24fcf1549c72988dd92de6d17ff3d2077] drm/amdgpu: Add DPM > >> function for XGMI link power down control > >> > git bisect good 5e7067b24fcf1549c72988dd92de6d17ff3d2077 > >> > # skip: [d248b371f7479a99caccf91da2ec6adee85e5e70] drm/i915/gen12: > >> Invalidate aux table entries forcibly > >> > git bisect skip d248b371f7479a99caccf91da2ec6adee85e5e70 > >> > # good: [b7f0656a25467fc26eb7fc375caf38ee99f5d004] drm/amdgpu: Updated > >> XGMI power down control support check > >> > git bisect good b7f0656a25467fc26eb7fc375caf38ee99f5d004 > >> > # good: [4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240] drm/amdgpu: optimize > >> amdgpu device attribute code > >> > git bisect good 4e01847c38f7a5e2b0ffa8ff74d6bf0e85924240 > >> > # skip: [f45ce9336ff0640e491c642a84ea02f21daac3a4] video/hdmi: Add Unpack > >> only function for DRM infoframe > >> > git bisect skip f45ce9336ff0640e491c642a84ea02f21daac3a4 > >> > # good: [bfbe1744e4417986419236719922a9a7fda224d1] Merge tag 'amd-drm- > >> next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux into drm-next > >> > git bisect good bfbe1744e4417986419236719922a9a7fda224d1 > >> > # skip: [701f026521980dd0151130f818558e17c608ed2e] drm/i915: Drop > >> I915_RESET_TIMEOUT and friends > >> > git bisect skip 701f026521980dd0151130f818558e17c608ed2e > >> > # skip: [378974f7f9754acfd5630327917c6b813495f1a9] drm/i915: Allow some > >> leniency in PCU reads > >> > git bisect skip 378974f7f9754acfd5630327917c6b813495f1a9 > >> > # good: [47e51832ae93534d872511ba557115722582d94c] drm/i915/gvt: use > >> context lrc_reg_state for shadow ppgtt override > >> > git bisect good 47e51832ae93534d872511ba557115722582d94c > >> > # skip: [230982d8d8df7f9d9aa216840ea2db1df6ad5d37] drm/i915: Update > >> DRIVER_DATE to 20200430 > >> > git bisect skip 230982d8d8df7f9d9aa216840ea2db1df6ad5d37 > >> > # > >> > # Automatically generated file; DO NOT EDIT. > >> > # Linux/x86_64 5.7.0-rc2 Kernel Configuration > >> > # > >> > > >> > # > >> > # Compiler: x86_64-linux-gnu-gcc (GCC) 9.2.1 20190827 (Red Hat Cross 9.2.1-3) > >> > # > >> > CONFIG_CC_IS_GCC=y > >> > CONFIG_GCC_VERSION=90201 > >> > CONFIG_LD_VERSION=234000000 > >> > CONFIG_CLANG_VERSION=0 > >> > CONFIG_CC_HAS_ASM_GOTO=y > >> > CONFIG_CC_HAS_ASM_INLINE=y > >> > CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y > >> > CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y > >> > CONFIG_IRQ_WORK=y > >> > CONFIG_BUILDTIME_TABLE_SORT=y > >> > CONFIG_THREAD_INFO_IN_TASK=y > >> > > >> > # > >> > # General setup > >> > # > >> > CONFIG_INIT_ENV_ARG_LIMIT=32 > >> > # CONFIG_COMPILE_TEST is not set > >> > CONFIG_LOCALVERSION="-fscache" > >> > # CONFIG_LOCALVERSION_AUTO is not set > >> > CONFIG_BUILD_SALT="" > >> > CONFIG_HAVE_KERNEL_GZIP=y > >> > CONFIG_HAVE_KERNEL_BZIP2=y > >> > CONFIG_HAVE_KERNEL_LZMA=y > >> > CONFIG_HAVE_KERNEL_XZ=y > >> > CONFIG_HAVE_KERNEL_LZO=y > >> > CONFIG_HAVE_KERNEL_LZ4=y > >> > # CONFIG_KERNEL_GZIP is not set > >> > # CONFIG_KERNEL_BZIP2 is not set > >> > # CONFIG_KERNEL_LZMA is not set > >> > CONFIG_KERNEL_XZ=y > >> > # CONFIG_KERNEL_LZO is not set > >> > # CONFIG_KERNEL_LZ4 is not set > >> > CONFIG_DEFAULT_HOSTNAME="(none)" > >> > CONFIG_SWAP=y > >> > CONFIG_SYSVIPC=y > >> > CONFIG_SYSVIPC_SYSCTL=y > >> > CONFIG_POSIX_MQUEUE=y > >> > CONFIG_POSIX_MQUEUE_SYSCTL=y > >> > CONFIG_CROSS_MEMORY_ATTACH=y > >> > # CONFIG_USELIB is not set > >> > CONFIG_AUDIT=y > >> > CONFIG_HAVE_ARCH_AUDITSYSCALL=y > >> > CONFIG_AUDITSYSCALL=y > >> > > >> > # > >> > # IRQ subsystem > >> > # > >> > CONFIG_GENERIC_IRQ_PROBE=y > >> > CONFIG_GENERIC_IRQ_SHOW=y > >> > CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y > >> > CONFIG_GENERIC_PENDING_IRQ=y > >> > CONFIG_GENERIC_IRQ_MIGRATION=y > >> > CONFIG_HARDIRQS_SW_RESEND=y > >> > CONFIG_IRQ_DOMAIN=y > >> > CONFIG_IRQ_DOMAIN_HIERARCHY=y > >> > CONFIG_GENERIC_MSI_IRQ=y > >> > CONFIG_GENERIC_MSI_IRQ_DOMAIN=y > >> > CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y > >> > CONFIG_GENERIC_IRQ_RESERVATION_MODE=y > >> > CONFIG_IRQ_FORCED_THREADING=y > >> > CONFIG_SPARSE_IRQ=y > >> > # CONFIG_GENERIC_IRQ_DEBUGFS is not set > >> > # end of IRQ subsystem > >> > > >> > CONFIG_CLOCKSOURCE_WATCHDOG=y > >> > CONFIG_ARCH_CLOCKSOURCE_INIT=y > >> > CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y > >> > CONFIG_GENERIC_TIME_VSYSCALL=y > >> > CONFIG_GENERIC_CLOCKEVENTS=y > >> > CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y > >> > CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y > >> > CONFIG_GENERIC_CMOS_UPDATE=y > >> > > >> > # > >> > # Timers subsystem > >> > # > >> > CONFIG_TICK_ONESHOT=y > >> > CONFIG_NO_HZ_COMMON=y > >> > # CONFIG_HZ_PERIODIC is not set > >> > # CONFIG_NO_HZ_IDLE is not set > >> > CONFIG_NO_HZ_FULL=y > >> > CONFIG_CONTEXT_TRACKING=y > >> > CONFIG_CONTEXT_TRACKING_FORCE=y > >> > # CONFIG_NO_HZ is not set > >> > CONFIG_HIGH_RES_TIMERS=y > >> > # end of Timers subsystem > >> > > >> > CONFIG_PREEMPT_NONE=y > >> > # CONFIG_PREEMPT_VOLUNTARY is not set > >> > # CONFIG_PREEMPT is not set > >> > > >> > # > >> > # CPU/Task time and stats accounting > >> > # > >> > CONFIG_VIRT_CPU_ACCOUNTING=y > >> > CONFIG_VIRT_CPU_ACCOUNTING_GEN=y > >> > # CONFIG_IRQ_TIME_ACCOUNTING is not set > >> > # CONFIG_SCHED_THERMAL_PRESSURE is not set > >> > CONFIG_BSD_PROCESS_ACCT=y > >> > CONFIG_BSD_PROCESS_ACCT_V3=y > >> > CONFIG_TASKSTATS=y > >> > CONFIG_TASK_DELAY_ACCT=y > >> > CONFIG_TASK_XACCT=y > >> > CONFIG_TASK_IO_ACCOUNTING=y > >> > # CONFIG_PSI is not set > >> > # end of CPU/Task time and stats accounting > >> > > >> > CONFIG_CPU_ISOLATION=y > >> > > >> > # > >> > # RCU Subsystem > >> > # > >> > CONFIG_TREE_RCU=y > >> > # CONFIG_RCU_EXPERT is not set > >> > CONFIG_SRCU=y > >> > CONFIG_TREE_SRCU=y > >> > CONFIG_RCU_STALL_COMMON=y > >> > CONFIG_RCU_NEED_SEGCBLIST=y > >> > CONFIG_RCU_NOCB_CPU=y > >> > # end of RCU Subsystem > >> > > >> > CONFIG_BUILD_BIN2C=y > >> > # CONFIG_IKCONFIG is not set > >> > # CONFIG_IKHEADERS is not set > >> > CONFIG_LOG_BUF_SHIFT=16 > >> > CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 > >> > CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 > >> > CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y > >> > > >> > # > >> > # Scheduler features > >> > # > >> > # CONFIG_UCLAMP_TASK is not set > >> > # end of Scheduler features > >> > > >> > CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y > >> > CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y > >> > CONFIG_CC_HAS_INT128=y > >> > CONFIG_ARCH_SUPPORTS_INT128=y > >> > # CONFIG_NUMA_BALANCING is not set > >> > CONFIG_CGROUPS=y > >> > CONFIG_PAGE_COUNTER=y > >> > CONFIG_MEMCG=y > >> > CONFIG_MEMCG_SWAP=y > >> > CONFIG_MEMCG_SWAP_ENABLED=y > >> > CONFIG_MEMCG_KMEM=y > >> > CONFIG_BLK_CGROUP=y > >> > CONFIG_CGROUP_WRITEBACK=y > >> > CONFIG_CGROUP_SCHED=y > >> > CONFIG_FAIR_GROUP_SCHED=y > >> > # CONFIG_CFS_BANDWIDTH is not set > >> > # CONFIG_RT_GROUP_SCHED is not set > >> > # CONFIG_CGROUP_PIDS is not set > >> > CONFIG_CGROUP_RDMA=y > >> > CONFIG_CGROUP_FREEZER=y > >> > CONFIG_CGROUP_HUGETLB=y > >> > CONFIG_CPUSETS=y > >> > CONFIG_PROC_PID_CPUSET=y > >> > CONFIG_CGROUP_DEVICE=y > >> > CONFIG_CGROUP_CPUACCT=y > >> > CONFIG_CGROUP_PERF=y > >> > # CONFIG_CGROUP_BPF is not set > >> > # CONFIG_CGROUP_DEBUG is not set > >> > CONFIG_SOCK_CGROUP_DATA=y > >> > CONFIG_NAMESPACES=y > >> > CONFIG_UTS_NS=y > >> > CONFIG_TIME_NS=y > >> > CONFIG_IPC_NS=y > >> > CONFIG_USER_NS=y > >> > CONFIG_PID_NS=y > >> > CONFIG_NET_NS=y > >> > # CONFIG_CHECKPOINT_RESTORE is not set > >> > # CONFIG_SCHED_AUTOGROUP is not set > >> > # CONFIG_SYSFS_DEPRECATED is not set > >> > CONFIG_RELAY=y > >> > CONFIG_BLK_DEV_INITRD=y > >> > CONFIG_INITRAMFS_SOURCE="" > >> > CONFIG_RD_GZIP=y > >> > # CONFIG_RD_BZIP2 is not set > >> > # CONFIG_RD_LZMA is not set > >> > # CONFIG_RD_XZ is not set > >> > # CONFIG_RD_LZO is not set > >> > # CONFIG_RD_LZ4 is not set > >> > # CONFIG_BOOT_CONFIG is not set > >> > # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set > >> > CONFIG_CC_OPTIMIZE_FOR_SIZE=y > >> > CONFIG_SYSCTL=y > >> > CONFIG_HAVE_UID16=y > >> > CONFIG_SYSCTL_EXCEPTION_TRACE=y > >> > CONFIG_HAVE_PCSPKR_PLATFORM=y > >> > CONFIG_BPF=y > >> > CONFIG_EXPERT=y > >> > CONFIG_UID16=y > >> > CONFIG_MULTIUSER=y > >> > # CONFIG_SGETMASK_SYSCALL is not set > >> > # CONFIG_SYSFS_SYSCALL is not set > >> > CONFIG_FHANDLE=y > >> > CONFIG_POSIX_TIMERS=y > >> > CONFIG_PRINTK=y > >> > CONFIG_PRINTK_NMI=y > >> > CONFIG_BUG=y > >> > CONFIG_ELF_CORE=y > >> > CONFIG_PCSPKR_PLATFORM=y > >> > CONFIG_BASE_FULL=y > >> > CONFIG_FUTEX=y > >> > CONFIG_FUTEX_PI=y > >> > CONFIG_EPOLL=y > >> > CONFIG_SIGNALFD=y > >> > CONFIG_TIMERFD=y > >> > CONFIG_EVENTFD=y > >> > CONFIG_SHMEM=y > >> > CONFIG_AIO=y > >> > # CONFIG_IO_URING is not set > >> > CONFIG_ADVISE_SYSCALLS=y > >> > CONFIG_MEMBARRIER=y > >> > CONFIG_KALLSYMS=y > >> > CONFIG_KALLSYMS_ALL=y > >> > CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y > >> > CONFIG_KALLSYMS_BASE_RELATIVE=y > >> > CONFIG_BPF_SYSCALL=y > >> > CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y > >> > # CONFIG_USERFAULTFD is not set > >> > CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y > >> > CONFIG_RSEQ=y > >> > # CONFIG_DEBUG_RSEQ is not set > >> > # CONFIG_EMBEDDED is not set > >> > CONFIG_HAVE_PERF_EVENTS=y > >> > # CONFIG_PC104 is not set > >> > > >> > # > >> > # Kernel Performance Events And Counters > >> > # > >> > CONFIG_PERF_EVENTS=y > >> > # CONFIG_DEBUG_PERF_USE_VMALLOC is not set > >> > # end of Kernel Performance Events And Counters > >> > > >> > CONFIG_VM_EVENT_COUNTERS=y > >> > CONFIG_COMPAT_BRK=y > >> > CONFIG_SLAB=y > >> > # CONFIG_SLUB is not set > >> > # CONFIG_SLOB is not set > >> > CONFIG_SLAB_MERGE_DEFAULT=y > >> > # CONFIG_SLAB_FREELIST_RANDOM is not set > >> > # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set > >> > CONFIG_SYSTEM_DATA_VERIFICATION=y > >> > # CONFIG_PROFILING is not set > >> > CONFIG_TRACEPOINTS=y > >> > # end of General setup > >> > > >> > CONFIG_64BIT=y > >> > CONFIG_X86_64=y > >> > CONFIG_X86=y > >> > CONFIG_INSTRUCTION_DECODER=y > >> > CONFIG_OUTPUT_FORMAT="elf64-x86-64" > >> > CONFIG_LOCKDEP_SUPPORT=y > >> > CONFIG_STACKTRACE_SUPPORT=y > >> > CONFIG_MMU=y > >> > CONFIG_ARCH_MMAP_RND_BITS_MIN=28 > >> > CONFIG_ARCH_MMAP_RND_BITS_MAX=32 > >> > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 > >> > CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 > >> > CONFIG_GENERIC_ISA_DMA=y > >> > CONFIG_GENERIC_BUG=y > >> > CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y > >> > CONFIG_ARCH_MAY_HAVE_PC_FDC=y > >> > CONFIG_GENERIC_CALIBRATE_DELAY=y > >> > CONFIG_ARCH_HAS_CPU_RELAX=y > >> > CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y > >> > CONFIG_ARCH_HAS_FILTER_PGPROT=y > >> > CONFIG_HAVE_SETUP_PER_CPU_AREA=y > >> > CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y > >> > CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y > >> > CONFIG_ARCH_HIBERNATION_POSSIBLE=y > >> > CONFIG_ARCH_SUSPEND_POSSIBLE=y > >> > CONFIG_ARCH_WANT_GENERAL_HUGETLB=y > >> > CONFIG_ZONE_DMA32=y > >> > CONFIG_AUDIT_ARCH=y > >> > CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y > >> > CONFIG_HAVE_INTEL_TXT=y > >> > CONFIG_X86_64_SMP=y > >> > CONFIG_ARCH_SUPPORTS_UPROBES=y > >> > CONFIG_FIX_EARLYCON_MEM=y > >> > CONFIG_PGTABLE_LEVELS=4 > >> > CONFIG_CC_HAS_SANE_STACKPROTECTOR=y > >> > > >> > # > >> > # Processor type and features > >> > # > >> > CONFIG_ZONE_DMA=y > >> > CONFIG_SMP=y > >> > CONFIG_X86_FEATURE_NAMES=y > >> > CONFIG_X86_MPPARSE=y > >> > # CONFIG_GOLDFISH is not set > >> > # CONFIG_RETPOLINE is not set > >> > CONFIG_X86_CPU_RESCTRL=y > >> > # CONFIG_X86_EXTENDED_PLATFORM is not set > >> > # CONFIG_X86_INTEL_LPSS is not set > >> > # CONFIG_X86_AMD_PLATFORM_DEVICE is not set > >> > CONFIG_IOSF_MBI=y > >> > # CONFIG_IOSF_MBI_DEBUG is not set > >> > CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y > >> > # CONFIG_SCHED_OMIT_FRAME_POINTER is not set > >> > # CONFIG_HYPERVISOR_GUEST is not set > >> > # CONFIG_MK8 is not set > >> > # CONFIG_MPSC is not set > >> > CONFIG_MCORE2=y > >> > # CONFIG_MATOM is not set > >> > # CONFIG_GENERIC_CPU is not set > >> > CONFIG_X86_INTERNODE_CACHE_SHIFT=6 > >> > CONFIG_X86_L1_CACHE_SHIFT=6 > >> > CONFIG_X86_INTEL_USERCOPY=y > >> > CONFIG_X86_USE_PPRO_CHECKSUM=y > >> > CONFIG_X86_P6_NOP=y > >> > CONFIG_X86_TSC=y > >> > CONFIG_X86_CMPXCHG64=y > >> > CONFIG_X86_CMOV=y > >> > CONFIG_X86_MINIMUM_CPU_FAMILY=64 > >> > CONFIG_X86_DEBUGCTLMSR=y > >> > CONFIG_IA32_FEAT_CTL=y > >> > CONFIG_X86_VMX_FEATURE_NAMES=y > >> > # CONFIG_PROCESSOR_SELECT is not set > >> > CONFIG_CPU_SUP_INTEL=y > >> > CONFIG_CPU_SUP_AMD=y > >> > CONFIG_CPU_SUP_HYGON=y > >> > CONFIG_CPU_SUP_CENTAUR=y > >> > CONFIG_CPU_SUP_ZHAOXIN=y > >> > CONFIG_HPET_TIMER=y > >> > CONFIG_HPET_EMULATE_RTC=y > >> > CONFIG_DMI=y > >> > CONFIG_GART_IOMMU=y > >> > # CONFIG_MAXSMP is not set > >> > CONFIG_NR_CPUS_RANGE_BEGIN=2 > >> > CONFIG_NR_CPUS_RANGE_END=512 > >> > CONFIG_NR_CPUS_DEFAULT=64 > >> > CONFIG_NR_CPUS=4 > >> > CONFIG_SCHED_SMT=y > >> > CONFIG_SCHED_MC=y > >> > CONFIG_SCHED_MC_PRIO=y > >> > CONFIG_X86_LOCAL_APIC=y > >> > CONFIG_X86_IO_APIC=y > >> > # CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set > >> > CONFIG_X86_MCE=y > >> > # CONFIG_X86_MCELOG_LEGACY is not set > >> > CONFIG_X86_MCE_INTEL=y > >> > # CONFIG_X86_MCE_AMD is not set > >> > CONFIG_X86_MCE_THRESHOLD=y > >> > # CONFIG_X86_MCE_INJECT is not set > >> > CONFIG_X86_THERMAL_VECTOR=y > >> > > >> > # > >> > # Performance monitoring > >> > # > >> > CONFIG_PERF_EVENTS_INTEL_UNCORE=y > >> > CONFIG_PERF_EVENTS_INTEL_RAPL=y > >> > CONFIG_PERF_EVENTS_INTEL_CSTATE=y > >> > # CONFIG_PERF_EVENTS_AMD_POWER is not set > >> > # end of Performance monitoring > >> > > >> > CONFIG_X86_16BIT=y > >> > CONFIG_X86_ESPFIX64=y > >> > CONFIG_X86_VSYSCALL_EMULATION=y > >> > # CONFIG_X86_IOPL_IOPERM is not set > >> > # CONFIG_I8K is not set > >> > # CONFIG_MICROCODE is not set > >> > CONFIG_X86_MSR=y > >> > CONFIG_X86_CPUID=y > >> > # CONFIG_X86_5LEVEL is not set > >> > CONFIG_X86_DIRECT_GBPAGES=y > >> > # CONFIG_X86_CPA_STATISTICS is not set > >> > # CONFIG_AMD_MEM_ENCRYPT is not set > >> > CONFIG_NUMA=y > >> > # CONFIG_AMD_NUMA is not set > >> > CONFIG_X86_64_ACPI_NUMA=y > >> > CONFIG_NODES_SPAN_OTHER_NODES=y > >> > # CONFIG_NUMA_EMU is not set > >> > CONFIG_NODES_SHIFT=6 > >> > CONFIG_ARCH_SPARSEMEM_ENABLE=y > >> > CONFIG_ARCH_SPARSEMEM_DEFAULT=y > >> > CONFIG_ARCH_SELECT_MEMORY_MODEL=y > >> > CONFIG_ARCH_PROC_KCORE_TEXT=y > >> > CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 > >> > # CONFIG_X86_PMEM_LEGACY is not set > >> > # CONFIG_X86_CHECK_BIOS_CORRUPTION is not set > >> > CONFIG_X86_RESERVE_LOW=64 > >> > CONFIG_MTRR=y > >> > # CONFIG_MTRR_SANITIZER is not set > >> > CONFIG_X86_PAT=y > >> > CONFIG_ARCH_USES_PG_UNCACHED=y > >> > CONFIG_ARCH_RANDOM=y > >> > CONFIG_X86_SMAP=y > >> > CONFIG_X86_UMIP=y > >> > CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y > >> > CONFIG_X86_INTEL_TSX_MODE_OFF=y > >> > # CONFIG_X86_INTEL_TSX_MODE_ON is not set > >> > # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set > >> > CONFIG_EFI=y > >> > CONFIG_EFI_STUB=y > >> > # CONFIG_EFI_MIXED is not set > >> > CONFIG_SECCOMP=y > >> > # CONFIG_HZ_100 is not set > >> > CONFIG_HZ_250=y > >> > # CONFIG_HZ_300 is not set > >> > # CONFIG_HZ_1000 is not set > >> > CONFIG_HZ=250 > >> > CONFIG_SCHED_HRTICK=y > >> > CONFIG_KEXEC=y > >> > CONFIG_KEXEC_FILE=y > >> > CONFIG_ARCH_HAS_KEXEC_PURGATORY=y > >> > # CONFIG_KEXEC_SIG is not set > >> > # CONFIG_CRASH_DUMP is not set > >> > CONFIG_PHYSICAL_START=0x1000000 > >> > CONFIG_RELOCATABLE=y > >> > # CONFIG_RANDOMIZE_BASE is not set > >> > CONFIG_PHYSICAL_ALIGN=0x1000000 > >> > CONFIG_HOTPLUG_CPU=y > >> > # CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set > >> > # CONFIG_DEBUG_HOTPLUG_CPU0 is not set > >> > CONFIG_COMPAT_VDSO=y > >> > # CONFIG_LEGACY_VSYSCALL_EMULATE is not set > >> > CONFIG_LEGACY_VSYSCALL_XONLY=y > >> > # CONFIG_LEGACY_VSYSCALL_NONE is not set > >> > # CONFIG_CMDLINE_BOOL is not set > >> > CONFIG_MODIFY_LDT_SYSCALL=y > >> > CONFIG_HAVE_LIVEPATCH=y > >> > CONFIG_LIVEPATCH=y > >> > # end of Processor type and features > >> > > >> > CONFIG_ARCH_HAS_ADD_PAGES=y > >> > CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y > >> > CONFIG_USE_PERCPU_NUMA_NODE_ID=y > >> > CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y > >> > CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y > >> > > >> > # > >> > # Power management and ACPI options > >> > # > >> > # CONFIG_SUSPEND is not set > >> > # CONFIG_HIBERNATION is not set > >> > CONFIG_PM=y > >> > # CONFIG_PM_DEBUG is not set > >> > CONFIG_PM_CLK=y > >> > CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y > >> > CONFIG_ENERGY_MODEL=y > >> > CONFIG_ARCH_SUPPORTS_ACPI=y > >> > CONFIG_ACPI=y > >> > CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y > >> > CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y > >> > CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y > >> > # CONFIG_ACPI_DEBUGGER is not set > >> > CONFIG_ACPI_SPCR_TABLE=y > >> > CONFIG_ACPI_LPIT=y > >> > # CONFIG_ACPI_PROCFS_POWER is not set > >> > CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y > >> > # CONFIG_ACPI_EC_DEBUGFS is not set > >> > CONFIG_ACPI_AC=y > >> > # CONFIG_ACPI_BATTERY is not set > >> > CONFIG_ACPI_BUTTON=y > >> > CONFIG_ACPI_VIDEO=y > >> > CONFIG_ACPI_FAN=y > >> > CONFIG_ACPI_DOCK=y > >> > CONFIG_ACPI_CPU_FREQ_PSS=y > >> > CONFIG_ACPI_PROCESSOR_CSTATE=y > >> > CONFIG_ACPI_PROCESSOR_IDLE=y > >> > CONFIG_ACPI_CPPC_LIB=y > >> > CONFIG_ACPI_PROCESSOR=y > >> > # CONFIG_ACPI_IPMI is not set > >> > CONFIG_ACPI_HOTPLUG_CPU=y > >> > CONFIG_ACPI_PROCESSOR_AGGREGATOR=y > >> > CONFIG_ACPI_THERMAL=y > >> > CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y > >> > CONFIG_ACPI_TABLE_UPGRADE=y > >> > CONFIG_ACPI_DEBUG=y > >> > # CONFIG_ACPI_PCI_SLOT is not set > >> > CONFIG_ACPI_CONTAINER=y > >> > CONFIG_ACPI_HOTPLUG_IOAPIC=y > >> > # CONFIG_ACPI_SBS is not set > >> > CONFIG_ACPI_HED=y > >> > # CONFIG_ACPI_CUSTOM_METHOD is not set > >> > # CONFIG_ACPI_BGRT is not set > >> > # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set > >> > # CONFIG_ACPI_NFIT is not set > >> > CONFIG_ACPI_NUMA=y > >> > # CONFIG_ACPI_HMAT is not set > >> > CONFIG_HAVE_ACPI_APEI=y > >> > CONFIG_HAVE_ACPI_APEI_NMI=y > >> > CONFIG_ACPI_APEI=y > >> > CONFIG_ACPI_APEI_GHES=y > >> > # CONFIG_ACPI_APEI_PCIEAER is not set > >> > CONFIG_ACPI_APEI_EINJ=y > >> > # CONFIG_ACPI_APEI_ERST_DEBUG is not set > >> > # CONFIG_DPTF_POWER is not set > >> > # CONFIG_PMIC_OPREGION is not set > >> > # CONFIG_ACPI_CONFIGFS is not set > >> > CONFIG_X86_PM_TIMER=y > >> > # CONFIG_SFI is not set > >> > > >> > # > >> > # CPU Frequency scaling > >> > # > >> > CONFIG_CPU_FREQ=y > >> > CONFIG_CPU_FREQ_GOV_ATTR_SET=y > >> > CONFIG_CPU_FREQ_GOV_COMMON=y > >> > CONFIG_CPU_FREQ_STAT=y > >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set > >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set > >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set > >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set > >> > CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y > >> > # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set > >> > CONFIG_CPU_FREQ_GOV_PERFORMANCE=y > >> > CONFIG_CPU_FREQ_GOV_POWERSAVE=y > >> > CONFIG_CPU_FREQ_GOV_USERSPACE=y > >> > CONFIG_CPU_FREQ_GOV_ONDEMAND=y > >> > CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y > >> > CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y > >> > > >> > # > >> > # CPU frequency scaling drivers > >> > # > >> > CONFIG_X86_INTEL_PSTATE=y > >> > CONFIG_X86_PCC_CPUFREQ=y > >> > CONFIG_X86_ACPI_CPUFREQ=y > >> > # CONFIG_X86_ACPI_CPUFREQ_CPB is not set > >> > # CONFIG_X86_POWERNOW_K8 is not set > >> > # CONFIG_X86_AMD_FREQ_SENSITIVITY is not set > >> > # CONFIG_X86_SPEEDSTEP_CENTRINO is not set > >> > # CONFIG_X86_P4_CLOCKMOD is not set > >> > > >> > # > >> > # shared options > >> > # > >> > # end of CPU Frequency scaling > >> > > >> > # > >> > # CPU Idle > >> > # > >> > CONFIG_CPU_IDLE=y > >> > CONFIG_CPU_IDLE_GOV_LADDER=y > >> > CONFIG_CPU_IDLE_GOV_MENU=y > >> > # CONFIG_CPU_IDLE_GOV_TEO is not set > >> > # end of CPU Idle > >> > > >> > CONFIG_INTEL_IDLE=y > >> > # end of Power management and ACPI options > >> > > >> > # > >> > # Bus options (PCI etc.) > >> > # > >> > CONFIG_PCI_DIRECT=y > >> > CONFIG_PCI_MMCONFIG=y > >> > CONFIG_MMCONF_FAM10H=y > >> > # CONFIG_PCI_CNB20LE_QUIRK is not set > >> > # CONFIG_ISA_BUS is not set > >> > CONFIG_ISA_DMA_API=y > >> > CONFIG_AMD_NB=y > >> > # CONFIG_X86_SYSFB is not set > >> > # end of Bus options (PCI etc.) > >> > > >> > # > >> > # Binary Emulations > >> > # > >> > CONFIG_IA32_EMULATION=y > >> > # CONFIG_X86_X32 is not set > >> > CONFIG_COMPAT_32=y > >> > CONFIG_COMPAT=y > >> > CONFIG_COMPAT_FOR_U64_ALIGNMENT=y > >> > CONFIG_SYSVIPC_COMPAT=y > >> > # end of Binary Emulations > >> > > >> > # > >> > # Firmware Drivers > >> > # > >> > # CONFIG_EDD is not set > >> > CONFIG_FIRMWARE_MEMMAP=y > >> > CONFIG_DMIID=y > >> > # CONFIG_DMI_SYSFS is not set > >> > CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y > >> > # CONFIG_FW_CFG_SYSFS is not set > >> > # CONFIG_GOOGLE_FIRMWARE is not set > >> > > >> > # > >> > # EFI (Extensible Firmware Interface) Support > >> > # > >> > # CONFIG_EFI_VARS is not set > >> > CONFIG_EFI_ESRT=y > >> > CONFIG_EFI_RUNTIME_MAP=y > >> > # CONFIG_EFI_FAKE_MEMMAP is not set > >> > CONFIG_EFI_RUNTIME_WRAPPERS=y > >> > # CONFIG_EFI_CAPSULE_LOADER is not set > >> > # CONFIG_EFI_TEST is not set > >> > # CONFIG_APPLE_PROPERTIES is not set > >> > # CONFIG_RESET_ATTACK_MITIGATION is not set > >> > # CONFIG_EFI_RCI2_TABLE is not set > >> > # CONFIG_EFI_DISABLE_PCI_DMA is not set > >> > # end of EFI (Extensible Firmware Interface) Support > >> > > >> > CONFIG_UEFI_CPER=y > >> > CONFIG_UEFI_CPER_X86=y > >> > CONFIG_EFI_EARLYCON=y > >> > > >> > # > >> > # Tegra firmware driver > >> > # > >> > # end of Tegra firmware driver > >> > # end of Firmware Drivers > >> > > >> > CONFIG_HAVE_KVM=y > >> > # CONFIG_VIRTUALIZATION is not set > >> > CONFIG_AS_AVX512=y > >> > CONFIG_AS_SHA1_NI=y > >> > CONFIG_AS_SHA256_NI=y > >> > > >> > # > >> > # General architecture-dependent options > >> > # > >> > CONFIG_CRASH_CORE=y > >> > CONFIG_KEXEC_CORE=y > >> > CONFIG_HOTPLUG_SMT=y > >> > CONFIG_HAVE_OPROFILE=y > >> > CONFIG_OPROFILE_NMI_TIMER=y > >> > CONFIG_KPROBES=y > >> > CONFIG_JUMP_LABEL=y > >> > # CONFIG_STATIC_KEYS_SELFTEST is not set > >> > CONFIG_OPTPROBES=y > >> > CONFIG_KPROBES_ON_FTRACE=y > >> > CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y > >> > CONFIG_ARCH_USE_BUILTIN_BSWAP=y > >> > CONFIG_KRETPROBES=y > >> > CONFIG_HAVE_IOREMAP_PROT=y > >> > CONFIG_HAVE_KPROBES=y > >> > CONFIG_HAVE_KRETPROBES=y > >> > CONFIG_HAVE_OPTPROBES=y > >> > CONFIG_HAVE_KPROBES_ON_FTRACE=y > >> > CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y > >> > CONFIG_HAVE_NMI=y > >> > CONFIG_HAVE_ARCH_TRACEHOOK=y > >> > CONFIG_HAVE_DMA_CONTIGUOUS=y > >> > CONFIG_GENERIC_SMP_IDLE_THREAD=y > >> > CONFIG_ARCH_HAS_FORTIFY_SOURCE=y > >> > CONFIG_ARCH_HAS_SET_MEMORY=y > >> > CONFIG_ARCH_HAS_SET_DIRECT_MAP=y > >> > CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y > >> > CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y > >> > CONFIG_HAVE_ASM_MODVERSIONS=y > >> > CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y > >> > CONFIG_HAVE_RSEQ=y > >> > CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y > >> > CONFIG_HAVE_CLK=y > >> > CONFIG_HAVE_HW_BREAKPOINT=y > >> > CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y > >> > CONFIG_HAVE_USER_RETURN_NOTIFIER=y > >> > CONFIG_HAVE_PERF_EVENTS_NMI=y > >> > CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y > >> > CONFIG_HAVE_PERF_REGS=y > >> > CONFIG_HAVE_PERF_USER_STACK_DUMP=y > >> > CONFIG_HAVE_ARCH_JUMP_LABEL=y > >> > CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y > >> > CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y > >> > CONFIG_HAVE_CMPXCHG_LOCAL=y > >> > CONFIG_HAVE_CMPXCHG_DOUBLE=y > >> > CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y > >> > CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y > >> > CONFIG_HAVE_ARCH_SECCOMP_FILTER=y > >> > CONFIG_SECCOMP_FILTER=y > >> > CONFIG_HAVE_ARCH_STACKLEAK=y > >> > CONFIG_HAVE_STACKPROTECTOR=y > >> > CONFIG_CC_HAS_STACKPROTECTOR_NONE=y > >> > CONFIG_STACKPROTECTOR=y > >> > CONFIG_STACKPROTECTOR_STRONG=y > >> > CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y > >> > CONFIG_HAVE_CONTEXT_TRACKING=y > >> > CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y > >> > CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y > >> > CONFIG_HAVE_MOVE_PMD=y > >> > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y > >> > CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y > >> > CONFIG_HAVE_ARCH_HUGE_VMAP=y > >> > CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y > >> > CONFIG_HAVE_ARCH_SOFT_DIRTY=y > >> > CONFIG_HAVE_MOD_ARCH_SPECIFIC=y > >> > CONFIG_MODULES_USE_ELF_RELA=y > >> > CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y > >> > CONFIG_ARCH_HAS_ELF_RANDOMIZE=y > >> > CONFIG_HAVE_ARCH_MMAP_RND_BITS=y > >> > CONFIG_HAVE_EXIT_THREAD=y > >> > CONFIG_ARCH_MMAP_RND_BITS=28 > >> > CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y > >> > CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 > >> > CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y > >> > CONFIG_HAVE_COPY_THREAD_TLS=y > >> > CONFIG_HAVE_STACK_VALIDATION=y > >> > CONFIG_HAVE_RELIABLE_STACKTRACE=y > >> > CONFIG_OLD_SIGSUSPEND3=y > >> > CONFIG_COMPAT_OLD_SIGACTION=y > >> > CONFIG_COMPAT_32BIT_TIME=y > >> > CONFIG_HAVE_ARCH_VMAP_STACK=y > >> > # CONFIG_VMAP_STACK is not set > >> > CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y > >> > CONFIG_STRICT_KERNEL_RWX=y > >> > CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y > >> > CONFIG_STRICT_MODULE_RWX=y > >> > CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y > >> > CONFIG_ARCH_USE_MEMREMAP_PROT=y > >> > # CONFIG_LOCK_EVENT_COUNTS is not set > >> > CONFIG_ARCH_HAS_MEM_ENCRYPT=y > >> > > >> > # > >> > # GCOV-based kernel profiling > >> > # > >> > # CONFIG_GCOV_KERNEL is not set > >> > CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y > >> > # end of GCOV-based kernel profiling > >> > > >> > CONFIG_HAVE_GCC_PLUGINS=y > >> > CONFIG_GCC_PLUGINS=y > >> > # CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set > >> > # CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set > >> > # CONFIG_GCC_PLUGIN_RANDSTRUCT is not set > >> > # end of General architecture-dependent options > >> > > >> > CONFIG_RT_MUTEXES=y > >> > CONFIG_BASE_SMALL=0 > >> > CONFIG_MODULE_SIG_FORMAT=y > >> > CONFIG_MODULES=y > >> > # CONFIG_MODULE_FORCE_LOAD is not set > >> > CONFIG_MODULE_UNLOAD=y > >> > # CONFIG_MODULE_FORCE_UNLOAD is not set > >> > # CONFIG_MODVERSIONS is not set > >> > # CONFIG_MODULE_SRCVERSION_ALL is not set > >> > CONFIG_MODULE_SIG=y > >> > # CONFIG_MODULE_SIG_FORCE is not set > >> > CONFIG_MODULE_SIG_ALL=y > >> > # CONFIG_MODULE_SIG_SHA1 is not set > >> > # CONFIG_MODULE_SIG_SHA224 is not set > >> > CONFIG_MODULE_SIG_SHA256=y > >> > # CONFIG_MODULE_SIG_SHA384 is not set > >> > # CONFIG_MODULE_SIG_SHA512 is not set > >> > CONFIG_MODULE_SIG_HASH="sha256" > >> > # CONFIG_MODULE_COMPRESS is not set > >> > # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set > >> > CONFIG_UNUSED_SYMBOLS=y > >> > CONFIG_MODULES_TREE_LOOKUP=y > >> > CONFIG_BLOCK=y > >> > CONFIG_BLK_SCSI_REQUEST=y > >> > CONFIG_BLK_DEV_BSG=y > >> > # CONFIG_BLK_DEV_BSGLIB is not set > >> > # CONFIG_BLK_DEV_INTEGRITY is not set > >> > # CONFIG_BLK_DEV_ZONED is not set > >> > # CONFIG_BLK_DEV_THROTTLING is not set > >> > # CONFIG_BLK_CMDLINE_PARSER is not set > >> > # CONFIG_BLK_WBT is not set > >> > # CONFIG_BLK_CGROUP_IOLATENCY is not set > >> > # CONFIG_BLK_CGROUP_IOCOST is not set > >> > CONFIG_BLK_DEBUG_FS=y > >> > # CONFIG_BLK_SED_OPAL is not set > >> > > >> > # > >> > # Partition Types > >> > # > >> > # CONFIG_PARTITION_ADVANCED is not set > >> > CONFIG_MSDOS_PARTITION=y > >> > CONFIG_EFI_PARTITION=y > >> > # end of Partition Types > >> > > >> > CONFIG_BLOCK_COMPAT=y > >> > CONFIG_BLK_MQ_PCI=y > >> > CONFIG_BLK_PM=y > >> > > >> > # > >> > # IO Schedulers > >> > # > >> > CONFIG_MQ_IOSCHED_DEADLINE=y > >> > CONFIG_MQ_IOSCHED_KYBER=y > >> > # CONFIG_IOSCHED_BFQ is not set > >> > # end of IO Schedulers > >> > > >> > CONFIG_ASN1=y > >> > CONFIG_UNINLINE_SPIN_UNLOCK=y > >> > CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y > >> > CONFIG_MUTEX_SPIN_ON_OWNER=y > >> > CONFIG_RWSEM_SPIN_ON_OWNER=y > >> > CONFIG_LOCK_SPIN_ON_OWNER=y > >> > CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y > >> > CONFIG_QUEUED_SPINLOCKS=y > >> > CONFIG_ARCH_USE_QUEUED_RWLOCKS=y > >> > CONFIG_QUEUED_RWLOCKS=y > >> > CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y > >> > CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y > >> > CONFIG_FREEZER=y > >> > > >> > # > >> > # Executable file formats > >> > # > >> > CONFIG_BINFMT_ELF=y > >> > CONFIG_COMPAT_BINFMT_ELF=y > >> > CONFIG_ELFCORE=y > >> > # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set > >> > CONFIG_BINFMT_SCRIPT=y > >> > CONFIG_BINFMT_MISC=y > >> > CONFIG_COREDUMP=y > >> > # end of Executable file formats > >> > > >> > # > >> > # Memory Management options > >> > # > >> > CONFIG_SELECT_MEMORY_MODEL=y > >> > CONFIG_SPARSEMEM_MANUAL=y > >> > CONFIG_SPARSEMEM=y > >> > CONFIG_NEED_MULTIPLE_NODES=y > >> > CONFIG_HAVE_MEMORY_PRESENT=y > >> > CONFIG_SPARSEMEM_EXTREME=y > >> > CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y > >> > CONFIG_SPARSEMEM_VMEMMAP=y > >> > CONFIG_HAVE_MEMBLOCK_NODE_MAP=y > >> > CONFIG_HAVE_FAST_GUP=y > >> > # CONFIG_MEMORY_HOTPLUG is not set > >> > CONFIG_SPLIT_PTLOCK_CPUS=4 > >> > # CONFIG_COMPACTION is not set > >> > # CONFIG_PAGE_REPORTING is not set > >> > CONFIG_MIGRATION=y > >> > CONFIG_PHYS_ADDR_T_64BIT=y > >> > CONFIG_BOUNCE=y > >> > CONFIG_VIRT_TO_BUS=y > >> > CONFIG_MMU_NOTIFIER=y > >> > # CONFIG_KSM is not set > >> > CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 > >> > CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y > >> > # CONFIG_MEMORY_FAILURE is not set > >> > # CONFIG_TRANSPARENT_HUGEPAGE is not set > >> > CONFIG_ARCH_WANTS_THP_SWAP=y > >> > # CONFIG_CLEANCACHE is not set > >> > # CONFIG_FRONTSWAP is not set > >> > # CONFIG_CMA is not set > >> > CONFIG_ZPOOL=m > >> > CONFIG_ZBUD=m > >> > CONFIG_Z3FOLD=m > >> > CONFIG_ZSMALLOC=m > >> > # CONFIG_PGTABLE_MAPPING is not set > >> > # CONFIG_ZSMALLOC_STAT is not set > >> > CONFIG_GENERIC_EARLY_IOREMAP=y > >> > # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set > >> > # CONFIG_IDLE_PAGE_TRACKING is not set > >> > CONFIG_ARCH_HAS_PTE_DEVMAP=y > >> > CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y > >> > CONFIG_ARCH_HAS_PKEYS=y > >> > # CONFIG_PERCPU_STATS is not set > >> > # CONFIG_GUP_BENCHMARK is not set > >> > CONFIG_ARCH_HAS_PTE_SPECIAL=y > >> > # end of Memory Management options > >> > > >> > CONFIG_NET=y > >> > CONFIG_SKB_EXTENSIONS=y > >> > > >> > # > >> > # Networking options > >> > # > >> > CONFIG_PACKET=y > >> > # CONFIG_PACKET_DIAG is not set > >> > CONFIG_UNIX=y > >> > CONFIG_UNIX_SCM=y > >> > # CONFIG_UNIX_DIAG is not set > >> > # CONFIG_TLS is not set > >> > CONFIG_XFRM=y > >> > CONFIG_XFRM_ALGO=y > >> > # CONFIG_XFRM_USER is not set > >> > # CONFIG_XFRM_INTERFACE is not set > >> > # CONFIG_XFRM_SUB_POLICY is not set > >> > # CONFIG_XFRM_MIGRATE is not set > >> > # CONFIG_XFRM_STATISTICS is not set > >> > CONFIG_XFRM_IPCOMP=y > >> > # CONFIG_NET_KEY is not set > >> > # CONFIG_XDP_SOCKETS is not set > >> > CONFIG_INET=y > >> > CONFIG_IP_MULTICAST=y > >> > CONFIG_IP_ADVANCED_ROUTER=y > >> > CONFIG_IP_FIB_TRIE_STATS=y > >> > CONFIG_IP_MULTIPLE_TABLES=y > >> > CONFIG_IP_ROUTE_MULTIPATH=y > >> > CONFIG_IP_ROUTE_VERBOSE=y > >> > # CONFIG_IP_PNP is not set > >> > # CONFIG_NET_IPIP is not set > >> > # CONFIG_NET_IPGRE_DEMUX is not set > >> > # CONFIG_IP_MROUTE is not set > >> > # CONFIG_SYN_COOKIES is not set > >> > # CONFIG_NET_IPVTI is not set > >> > # CONFIG_NET_FOU is not set > >> > # CONFIG_INET_AH is not set > >> > # CONFIG_INET_ESP is not set > >> > # CONFIG_INET_IPCOMP is not set > >> > CONFIG_INET_DIAG=y > >> > CONFIG_INET_TCP_DIAG=y > >> > # CONFIG_INET_UDP_DIAG is not set > >> > # CONFIG_INET_RAW_DIAG is not set > >> > # CONFIG_INET_DIAG_DESTROY is not set > >> > # CONFIG_TCP_CONG_ADVANCED is not set > >> > CONFIG_TCP_CONG_CUBIC=y > >> > CONFIG_DEFAULT_TCP_CONG="cubic" > >> > # CONFIG_TCP_MD5SIG is not set > >> > CONFIG_IPV6=y > >> > CONFIG_IPV6_ROUTER_PREF=y > >> > CONFIG_IPV6_ROUTE_INFO=y > >> > CONFIG_IPV6_OPTIMISTIC_DAD=y > >> > CONFIG_INET6_AH=y > >> > CONFIG_INET6_ESP=y > >> > # CONFIG_INET6_ESP_OFFLOAD is not set > >> > CONFIG_INET6_IPCOMP=y > >> > CONFIG_IPV6_MIP6=y > >> > CONFIG_INET6_XFRM_TUNNEL=y > >> > CONFIG_INET6_TUNNEL=y > >> > # CONFIG_IPV6_VTI is not set > >> > # CONFIG_IPV6_SIT is not set > >> > # CONFIG_IPV6_TUNNEL is not set > >> > CONFIG_IPV6_MULTIPLE_TABLES=y > >> > CONFIG_IPV6_SUBTREES=y > >> > # CONFIG_IPV6_MROUTE is not set > >> > # CONFIG_IPV6_SEG6_LWTUNNEL is not set > >> > # CONFIG_IPV6_SEG6_HMAC is not set > >> > # CONFIG_IPV6_RPL_LWTUNNEL is not set > >> > CONFIG_NETLABEL=y > >> > # CONFIG_MPTCP is not set > >> > CONFIG_NETWORK_SECMARK=y > >> > CONFIG_NET_PTP_CLASSIFY=y > >> > # CONFIG_NETWORK_PHY_TIMESTAMPING is not set > >> > # CONFIG_NETFILTER is not set > >> > # CONFIG_BPFILTER is not set > >> > # CONFIG_IP_DCCP is not set > >> > CONFIG_IP_SCTP=y > >> > # CONFIG_SCTP_DBG_OBJCNT is not set > >> > CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y > >> > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set > >> > # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set > >> > CONFIG_SCTP_COOKIE_HMAC_MD5=y > >> > # CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set > >> > CONFIG_INET_SCTP_DIAG=y > >> > CONFIG_RDS=y > >> > CONFIG_RDS_TCP=m > >> > # CONFIG_RDS_DEBUG is not set > >> > # CONFIG_TIPC is not set > >> > # CONFIG_ATM is not set > >> > # CONFIG_L2TP is not set > >> > CONFIG_STP=y > >> > CONFIG_BRIDGE=y > >> > CONFIG_BRIDGE_IGMP_SNOOPING=y > >> > CONFIG_HAVE_NET_DSA=y > >> > # CONFIG_NET_DSA is not set > >> > # CONFIG_VLAN_8021Q is not set > >> > # CONFIG_DECNET is not set > >> > CONFIG_LLC=y > >> > # CONFIG_LLC2 is not set > >> > # CONFIG_ATALK is not set > >> > # CONFIG_X25 is not set > >> > # CONFIG_LAPB is not set > >> > # CONFIG_PHONET is not set > >> > # CONFIG_6LOWPAN is not set > >> > # CONFIG_IEEE802154 is not set > >> > # CONFIG_NET_SCHED is not set > >> > # CONFIG_DCB is not set > >> > CONFIG_DNS_RESOLVER=y > >> > # CONFIG_BATMAN_ADV is not set > >> > # CONFIG_OPENVSWITCH is not set > >> > # CONFIG_VSOCKETS is not set > >> > CONFIG_NETLINK_DIAG=y > >> > # CONFIG_MPLS is not set > >> > # CONFIG_NET_NSH is not set > >> > # CONFIG_HSR is not set > >> > # CONFIG_NET_SWITCHDEV is not set > >> > # CONFIG_NET_L3_MASTER_DEV is not set > >> > # CONFIG_NET_NCSI is not set > >> > CONFIG_RPS=y > >> > CONFIG_RFS_ACCEL=y > >> > CONFIG_XPS=y > >> > CONFIG_CGROUP_NET_PRIO=y > >> > CONFIG_CGROUP_NET_CLASSID=y > >> > CONFIG_NET_RX_BUSY_POLL=y > >> > CONFIG_BQL=y > >> > # CONFIG_BPF_JIT is not set > >> > CONFIG_NET_FLOW_LIMIT=y > >> > > >> > # > >> > # Network testing > >> > # > >> > # CONFIG_NET_PKTGEN is not set > >> > # CONFIG_NET_DROP_MONITOR is not set > >> > # end of Network testing > >> > # end of Networking options > >> > > >> > # CONFIG_HAMRADIO is not set > >> > # CONFIG_CAN is not set > >> > # CONFIG_BT is not set > >> > CONFIG_AF_RXRPC=y > >> > CONFIG_AF_RXRPC_IPV6=y > >> > # CONFIG_AF_RXRPC_INJECT_LOSS is not set > >> > CONFIG_AF_RXRPC_DEBUG=y > >> > CONFIG_RXKAD=y > >> > # CONFIG_AF_KCM is not set > >> > CONFIG_FIB_RULES=y > >> > # CONFIG_WIRELESS is not set > >> > # CONFIG_WIMAX is not set > >> > # CONFIG_RFKILL is not set > >> > # CONFIG_NET_9P is not set > >> > # CONFIG_CAIF is not set > >> > CONFIG_CEPH_LIB=m > >> > # CONFIG_CEPH_LIB_PRETTYDEBUG is not set > >> > CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y > >> > # CONFIG_NFC is not set > >> > # CONFIG_PSAMPLE is not set > >> > # CONFIG_NET_IFE is not set > >> > # CONFIG_LWTUNNEL is not set > >> > CONFIG_GRO_CELLS=y > >> > # CONFIG_FAILOVER is not set > >> > CONFIG_ETHTOOL_NETLINK=y > >> > CONFIG_HAVE_EBPF_JIT=y > >> > > >> > # > >> > # Device Drivers > >> > # > >> > CONFIG_HAVE_EISA=y > >> > # CONFIG_EISA is not set > >> > CONFIG_HAVE_PCI=y > >> > CONFIG_PCI=y > >> > CONFIG_PCI_DOMAINS=y > >> > CONFIG_PCIEPORTBUS=y > >> > CONFIG_PCIEAER=y > >> > # CONFIG_PCIEAER_INJECT is not set > >> > # CONFIG_PCIE_ECRC is not set > >> > CONFIG_PCIEASPM=y > >> > CONFIG_PCIEASPM_DEFAULT=y > >> > # CONFIG_PCIEASPM_POWERSAVE is not set > >> > # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set > >> > # CONFIG_PCIEASPM_PERFORMANCE is not set > >> > CONFIG_PCIE_PME=y > >> > # CONFIG_PCIE_DPC is not set > >> > # CONFIG_PCIE_PTM is not set > >> > # CONFIG_PCIE_BW is not set > >> > CONFIG_PCI_MSI=y > >> > CONFIG_PCI_MSI_IRQ_DOMAIN=y > >> > CONFIG_PCI_QUIRKS=y > >> > # CONFIG_PCI_DEBUG is not set > >> > # CONFIG_PCI_STUB is not set > >> > CONFIG_PCI_ATS=y > >> > CONFIG_PCI_LOCKLESS_CONFIG=y > >> > # CONFIG_PCI_IOV is not set > >> > CONFIG_PCI_PRI=y > >> > CONFIG_PCI_PASID=y > >> > CONFIG_PCI_LABEL=y > >> > # CONFIG_HOTPLUG_PCI is not set > >> > > >> > # > >> > # PCI controller drivers > >> > # > >> > # CONFIG_VMD is not set > >> > > >> > # > >> > # DesignWare PCI Core Support > >> > # > >> > # CONFIG_PCIE_DW_PLAT_HOST is not set > >> > # CONFIG_PCI_MESON is not set > >> > # end of DesignWare PCI Core Support > >> > > >> > # > >> > # Mobiveil PCIe Core Support > >> > # > >> > # end of Mobiveil PCIe Core Support > >> > > >> > # > >> > # Cadence PCIe controllers support > >> > # > >> > # end of Cadence PCIe controllers support > >> > # end of PCI controller drivers > >> > > >> > # > >> > # PCI Endpoint > >> > # > >> > # CONFIG_PCI_ENDPOINT is not set > >> > # end of PCI Endpoint > >> > > >> > # > >> > # PCI switch controller drivers > >> > # > >> > # CONFIG_PCI_SW_SWITCHTEC is not set > >> > # end of PCI switch controller drivers > >> > > >> > # CONFIG_PCCARD is not set > >> > # CONFIG_RAPIDIO is not set > >> > > >> > # > >> > # Generic Driver Options > >> > # > >> > CONFIG_UEVENT_HELPER=y > >> > CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" > >> > CONFIG_DEVTMPFS=y > >> > CONFIG_DEVTMPFS_MOUNT=y > >> > CONFIG_STANDALONE=y > >> > CONFIG_PREVENT_FIRMWARE_BUILD=y > >> > > >> > # > >> > # Firmware loader > >> > # > >> > CONFIG_FW_LOADER=y > >> > CONFIG_FW_LOADER_PAGED_BUF=y > >> > CONFIG_EXTRA_FIRMWARE="" > >> > # CONFIG_FW_LOADER_USER_HELPER is not set > >> > CONFIG_FW_LOADER_COMPRESS=y > >> > # end of Firmware loader > >> > > >> > CONFIG_ALLOW_DEV_COREDUMP=y > >> > # CONFIG_DEBUG_DRIVER is not set > >> > # CONFIG_DEBUG_DEVRES is not set > >> > # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set > >> > # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set > >> > CONFIG_GENERIC_CPU_AUTOPROBE=y > >> > CONFIG_GENERIC_CPU_VULNERABILITIES=y > >> > CONFIG_DMA_SHARED_BUFFER=y > >> > # CONFIG_DMA_FENCE_TRACE is not set > >> > # end of Generic Driver Options > >> > > >> > # > >> > # Bus devices > >> > # > >> > # CONFIG_MHI_BUS is not set > >> > # end of Bus devices > >> > > >> > # CONFIG_CONNECTOR is not set > >> > # CONFIG_GNSS is not set > >> > # CONFIG_MTD is not set > >> > # CONFIG_OF is not set > >> > CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y > >> > # CONFIG_PARPORT is not set > >> > CONFIG_PNP=y > >> > # CONFIG_PNP_DEBUG_MESSAGES is not set > >> > > >> > # > >> > # Protocols > >> > # > >> > CONFIG_PNPACPI=y > >> > CONFIG_BLK_DEV=y > >> > # CONFIG_BLK_DEV_NULL_BLK is not set > >> > # CONFIG_BLK_DEV_FD is not set > >> > # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set > >> > # CONFIG_ZRAM is not set > >> > # CONFIG_BLK_DEV_UMEM is not set > >> > CONFIG_BLK_DEV_LOOP=y > >> > CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 > >> > # CONFIG_BLK_DEV_CRYPTOLOOP is not set > >> > # CONFIG_BLK_DEV_DRBD is not set > >> > # CONFIG_BLK_DEV_NBD is not set > >> > # CONFIG_BLK_DEV_SKD is not set > >> > # CONFIG_BLK_DEV_SX8 is not set > >> > # CONFIG_BLK_DEV_RAM is not set > >> > # CONFIG_CDROM_PKTCDVD is not set > >> > # CONFIG_ATA_OVER_ETH is not set > >> > CONFIG_BLK_DEV_RBD=m > >> > # CONFIG_BLK_DEV_RSXX is not set > >> > > >> > # > >> > # NVME Support > >> > # > >> > # CONFIG_BLK_DEV_NVME is not set > >> > # CONFIG_NVME_FC is not set > >> > # CONFIG_NVME_TARGET is not set > >> > # end of NVME Support > >> > > >> > # > >> > # Misc devices > >> > # > >> > # CONFIG_AD525X_DPOT is not set > >> > # CONFIG_DUMMY_IRQ is not set > >> > # CONFIG_IBM_ASM is not set > >> > # CONFIG_PHANTOM is not set > >> > # CONFIG_TIFM_CORE is not set > >> > # CONFIG_ICS932S401 is not set > >> > CONFIG_ENCLOSURE_SERVICES=y > >> > # CONFIG_HP_ILO is not set > >> > # CONFIG_APDS9802ALS is not set > >> > # CONFIG_ISL29003 is not set > >> > # CONFIG_ISL29020 is not set > >> > # CONFIG_SENSORS_TSL2550 is not set > >> > # CONFIG_SENSORS_BH1770 is not set > >> > # CONFIG_SENSORS_APDS990X is not set > >> > # CONFIG_HMC6352 is not set > >> > # CONFIG_DS1682 is not set > >> > # CONFIG_SRAM is not set > >> > # CONFIG_PCI_ENDPOINT_TEST is not set > >> > # CONFIG_XILINX_SDFEC is not set > >> > # CONFIG_PVPANIC is not set > >> > CONFIG_C2PORT=m > >> > # CONFIG_C2PORT_DURAMAR_2150 is not set > >> > > >> > # > >> > # EEPROM support > >> > # > >> > # CONFIG_EEPROM_AT24 is not set > >> > # CONFIG_EEPROM_LEGACY is not set > >> > # CONFIG_EEPROM_MAX6875 is not set > >> > # CONFIG_EEPROM_93CX6 is not set > >> > # CONFIG_EEPROM_IDT_89HPESX is not set > >> > # CONFIG_EEPROM_EE1004 is not set > >> > # end of EEPROM support > >> > > >> > # CONFIG_CB710_CORE is not set > >> > > >> > # > >> > # Texas Instruments shared transport line discipline > >> > # > >> > # end of Texas Instruments shared transport line discipline > >> > > >> > # CONFIG_SENSORS_LIS3_I2C is not set > >> > # CONFIG_ALTERA_STAPL is not set > >> > CONFIG_INTEL_MEI=y > >> > CONFIG_INTEL_MEI_ME=y > >> > # CONFIG_INTEL_MEI_TXE is not set > >> > # CONFIG_INTEL_MEI_HDCP is not set > >> > # CONFIG_VMWARE_VMCI is not set > >> > > >> > # > >> > # Intel MIC & related support > >> > # > >> > # CONFIG_INTEL_MIC_BUS is not set > >> > # CONFIG_SCIF_BUS is not set > >> > # CONFIG_VOP_BUS is not set > >> > # end of Intel MIC & related support > >> > > >> > # CONFIG_GENWQE is not set > >> > # CONFIG_ECHO is not set > >> > # CONFIG_MISC_ALCOR_PCI is not set > >> > # CONFIG_MISC_RTSX_PCI is not set > >> > # CONFIG_MISC_RTSX_USB is not set > >> > # CONFIG_HABANA_AI is not set > >> > # CONFIG_UACCE is not set > >> > # end of Misc devices > >> > > >> > CONFIG_HAVE_IDE=y > >> > # CONFIG_IDE is not set > >> > > >> > # > >> > # SCSI device support > >> > # > >> > CONFIG_SCSI_MOD=y > >> > # CONFIG_RAID_ATTRS is not set > >> > CONFIG_SCSI=y > >> > CONFIG_SCSI_DMA=y > >> > CONFIG_SCSI_PROC_FS=y > >> > > >> > # > >> > # SCSI support type (disk, tape, CD-ROM) > >> > # > >> > CONFIG_BLK_DEV_SD=y > >> > # CONFIG_CHR_DEV_ST is not set > >> > # CONFIG_BLK_DEV_SR is not set > >> > CONFIG_CHR_DEV_SG=y > >> > # CONFIG_CHR_DEV_SCH is not set > >> > # CONFIG_SCSI_ENCLOSURE is not set > >> > CONFIG_SCSI_CONSTANTS=y > >> > # CONFIG_SCSI_LOGGING is not set > >> > # CONFIG_SCSI_SCAN_ASYNC is not set > >> > > >> > # > >> > # SCSI Transports > >> > # > >> > CONFIG_SCSI_SPI_ATTRS=y > >> > # CONFIG_SCSI_FC_ATTRS is not set > >> > # CONFIG_SCSI_ISCSI_ATTRS is not set > >> > # CONFIG_SCSI_SAS_ATTRS is not set > >> > # CONFIG_SCSI_SAS_LIBSAS is not set > >> > # CONFIG_SCSI_SRP_ATTRS is not set > >> > # end of SCSI Transports > >> > > >> > # CONFIG_SCSI_LOWLEVEL is not set > >> > # CONFIG_SCSI_DH is not set > >> > # end of SCSI device support > >> > > >> > CONFIG_ATA=y > >> > CONFIG_SATA_HOST=y > >> > CONFIG_PATA_TIMINGS=y > >> > CONFIG_ATA_VERBOSE_ERROR=y > >> > CONFIG_ATA_FORCE=y > >> > CONFIG_ATA_ACPI=y > >> > # CONFIG_SATA_ZPODD is not set > >> > # CONFIG_SATA_PMP is not set > >> > > >> > # > >> > # Controllers with non-SFF native interface > >> > # > >> > CONFIG_SATA_AHCI=y > >> > CONFIG_SATA_MOBILE_LPM_POLICY=0 > >> > CONFIG_SATA_AHCI_PLATFORM=y > >> > # CONFIG_SATA_INIC162X is not set > >> > # CONFIG_SATA_ACARD_AHCI is not set > >> > # CONFIG_SATA_SIL24 is not set > >> > # CONFIG_ATA_SFF is not set > >> > CONFIG_MD=y > >> > # CONFIG_BLK_DEV_MD is not set > >> > # CONFIG_BCACHE is not set > >> > CONFIG_BLK_DEV_DM_BUILTIN=y > >> > CONFIG_BLK_DEV_DM=y > >> > # CONFIG_DM_DEBUG is not set > >> > # CONFIG_DM_UNSTRIPED is not set > >> > # CONFIG_DM_CRYPT is not set > >> > # CONFIG_DM_SNAPSHOT is not set > >> > # CONFIG_DM_THIN_PROVISIONING is not set > >> > # CONFIG_DM_CACHE is not set > >> > # CONFIG_DM_WRITECACHE is not set > >> > # CONFIG_DM_ERA is not set > >> > # CONFIG_DM_CLONE is not set > >> > # CONFIG_DM_MIRROR is not set > >> > # CONFIG_DM_RAID is not set > >> > # CONFIG_DM_ZERO is not set > >> > # CONFIG_DM_MULTIPATH is not set > >> > # CONFIG_DM_DELAY is not set > >> > # CONFIG_DM_DUST is not set > >> > # CONFIG_DM_INIT is not set > >> > CONFIG_DM_UEVENT=y > >> > # CONFIG_DM_FLAKEY is not set > >> > # CONFIG_DM_VERITY is not set > >> > # CONFIG_DM_SWITCH is not set > >> > # CONFIG_DM_LOG_WRITES is not set > >> > # CONFIG_DM_INTEGRITY is not set > >> > # CONFIG_TARGET_CORE is not set > >> > # CONFIG_FUSION is not set > >> > > >> > # > >> > # IEEE 1394 (FireWire) support > >> > # > >> > # CONFIG_FIREWIRE is not set > >> > # CONFIG_FIREWIRE_NOSY is not set > >> > # end of IEEE 1394 (FireWire) support > >> > > >> > # CONFIG_MACINTOSH_DRIVERS is not set > >> > CONFIG_NETDEVICES=y > >> > CONFIG_NET_CORE=y > >> > # CONFIG_BONDING is not set > >> > # CONFIG_DUMMY is not set > >> > # CONFIG_WIREGUARD is not set > >> > # CONFIG_EQUALIZER is not set > >> > # CONFIG_NET_FC is not set > >> > # CONFIG_NET_TEAM is not set > >> > # CONFIG_MACVLAN is not set > >> > # CONFIG_IPVLAN is not set > >> > # CONFIG_VXLAN is not set > >> > # CONFIG_GENEVE is not set > >> > # CONFIG_BAREUDP is not set > >> > # CONFIG_GTP is not set > >> > # CONFIG_MACSEC is not set > >> > # CONFIG_NETCONSOLE is not set > >> > CONFIG_TUN=y > >> > # CONFIG_TUN_VNET_CROSS_LE is not set > >> > CONFIG_VETH=y > >> > # CONFIG_NLMON is not set > >> > # CONFIG_ARCNET is not set > >> > > >> > # > >> > # Distributed Switch Architecture drivers > >> > # > >> > # end of Distributed Switch Architecture drivers > >> > > >> > CONFIG_ETHERNET=y > >> > CONFIG_MDIO=y > >> > # CONFIG_NET_VENDOR_3COM is not set > >> > # CONFIG_NET_VENDOR_ADAPTEC is not set > >> > # CONFIG_NET_VENDOR_AGERE is not set > >> > # CONFIG_NET_VENDOR_ALACRITECH is not set > >> > # CONFIG_NET_VENDOR_ALTEON is not set > >> > # CONFIG_ALTERA_TSE is not set > >> > # CONFIG_NET_VENDOR_AMAZON is not set > >> > # CONFIG_NET_VENDOR_AMD is not set > >> > # CONFIG_NET_VENDOR_AQUANTIA is not set > >> > # CONFIG_NET_VENDOR_ARC is not set > >> > # CONFIG_NET_VENDOR_ATHEROS is not set > >> > # CONFIG_NET_VENDOR_AURORA is not set > >> > # CONFIG_NET_VENDOR_BROADCOM is not set > >> > # CONFIG_NET_VENDOR_BROCADE is not set > >> > # CONFIG_NET_VENDOR_CADENCE is not set > >> > # CONFIG_NET_VENDOR_CAVIUM is not set > >> > # CONFIG_NET_VENDOR_CHELSIO is not set > >> > # CONFIG_NET_VENDOR_CISCO is not set > >> > # CONFIG_NET_VENDOR_CORTINA is not set > >> > # CONFIG_CX_ECAT is not set > >> > # CONFIG_DNET is not set > >> > # CONFIG_NET_VENDOR_DEC is not set > >> > # CONFIG_NET_VENDOR_DLINK is not set > >> > # CONFIG_NET_VENDOR_EMULEX is not set > >> > # CONFIG_NET_VENDOR_EZCHIP is not set > >> > # CONFIG_NET_VENDOR_GOOGLE is not set > >> > # CONFIG_NET_VENDOR_HUAWEI is not set > >> > CONFIG_NET_VENDOR_I825XX=y > >> > CONFIG_NET_VENDOR_INTEL=y > >> > # CONFIG_E100 is not set > >> > # CONFIG_E1000 is not set > >> > # CONFIG_E1000E is not set > >> > # CONFIG_IGB is not set > >> > # CONFIG_IGBVF is not set > >> > # CONFIG_IXGB is not set > >> > CONFIG_IXGBE=y > >> > CONFIG_IXGBE_HWMON=y > >> > # CONFIG_IXGBEVF is not set > >> > # CONFIG_I40E is not set > >> > # CONFIG_I40EVF is not set > >> > # CONFIG_ICE is not set > >> > # CONFIG_FM10K is not set > >> > # CONFIG_IGC is not set > >> > # CONFIG_JME is not set > >> > # CONFIG_NET_VENDOR_MARVELL is not set > >> > # CONFIG_NET_VENDOR_MELLANOX is not set > >> > # CONFIG_NET_VENDOR_MICREL is not set > >> > # CONFIG_NET_VENDOR_MICROCHIP is not set > >> > # CONFIG_NET_VENDOR_MICROSEMI is not set > >> > # CONFIG_NET_VENDOR_MYRI is not set > >> > # CONFIG_FEALNX is not set > >> > # CONFIG_NET_VENDOR_NATSEMI is not set > >> > # CONFIG_NET_VENDOR_NETERION is not set > >> > # CONFIG_NET_VENDOR_NETRONOME is not set > >> > # CONFIG_NET_VENDOR_NI is not set > >> > # CONFIG_NET_VENDOR_NVIDIA is not set > >> > # CONFIG_NET_VENDOR_OKI is not set > >> > # CONFIG_ETHOC is not set > >> > # CONFIG_NET_VENDOR_PACKET_ENGINES is not set > >> > # CONFIG_NET_VENDOR_PENSANDO is not set > >> > # CONFIG_NET_VENDOR_QLOGIC is not set > >> > # CONFIG_NET_VENDOR_QUALCOMM is not set > >> > # CONFIG_NET_VENDOR_RDC is not set > >> > CONFIG_NET_VENDOR_REALTEK=y > >> > # CONFIG_8139CP is not set > >> > # CONFIG_8139TOO is not set > >> > CONFIG_R8169=y > >> > # CONFIG_NET_VENDOR_RENESAS is not set > >> > # CONFIG_NET_VENDOR_ROCKER is not set > >> > # CONFIG_NET_VENDOR_SAMSUNG is not set > >> > # CONFIG_NET_VENDOR_SEEQ is not set > >> > # CONFIG_NET_VENDOR_SOLARFLARE is not set > >> > # CONFIG_NET_VENDOR_SILAN is not set > >> > # CONFIG_NET_VENDOR_SIS is not set > >> > # CONFIG_NET_VENDOR_SMSC is not set > >> > # CONFIG_NET_VENDOR_SOCIONEXT is not set > >> > # CONFIG_NET_VENDOR_STMICRO is not set > >> > # CONFIG_NET_VENDOR_SUN is not set > >> > # CONFIG_NET_VENDOR_SYNOPSYS is not set > >> > # CONFIG_NET_VENDOR_TEHUTI is not set > >> > # CONFIG_NET_VENDOR_TI is not set > >> > # CONFIG_NET_VENDOR_VIA is not set > >> > # CONFIG_NET_VENDOR_WIZNET is not set > >> > # CONFIG_NET_VENDOR_XILINX is not set > >> > # CONFIG_FDDI is not set > >> > # CONFIG_HIPPI is not set > >> > # CONFIG_NET_SB1000 is not set > >> > CONFIG_MDIO_DEVICE=y > >> > CONFIG_MDIO_BUS=y > >> > # CONFIG_MDIO_BCM_UNIMAC is not set > >> > # CONFIG_MDIO_BITBANG is not set > >> > # CONFIG_MDIO_MSCC_MIIM is not set > >> > # CONFIG_MDIO_MVUSB is not set > >> > # CONFIG_MDIO_THUNDER is not set > >> > # CONFIG_MDIO_XPCS is not set > >> > CONFIG_PHYLIB=y > >> > > >> > # > >> > # MII PHY device drivers > >> > # > >> > # CONFIG_ADIN_PHY is not set > >> > # CONFIG_AMD_PHY is not set > >> > # CONFIG_AQUANTIA_PHY is not set > >> > # CONFIG_AX88796B_PHY is not set > >> > # CONFIG_BCM7XXX_PHY is not set > >> > # CONFIG_BCM87XX_PHY is not set > >> > # CONFIG_BROADCOM_PHY is not set > >> > # CONFIG_BCM84881_PHY is not set > >> > # CONFIG_CICADA_PHY is not set > >> > # CONFIG_CORTINA_PHY is not set > >> > # CONFIG_DAVICOM_PHY is not set > >> > # CONFIG_DP83822_PHY is not set > >> > # CONFIG_DP83TC811_PHY is not set > >> > # CONFIG_DP83848_PHY is not set > >> > # CONFIG_DP83867_PHY is not set > >> > # CONFIG_DP83869_PHY is not set > >> > # CONFIG_FIXED_PHY is not set > >> > # CONFIG_ICPLUS_PHY is not set > >> > # CONFIG_INTEL_XWAY_PHY is not set > >> > # CONFIG_LSI_ET1011C_PHY is not set > >> > # CONFIG_LXT_PHY is not set > >> > # CONFIG_MARVELL_PHY is not set > >> > # CONFIG_MARVELL_10G_PHY is not set > >> > # CONFIG_MICREL_PHY is not set > >> > # CONFIG_MICROCHIP_PHY is not set > >> > # CONFIG_MICROCHIP_T1_PHY is not set > >> > # CONFIG_MICROSEMI_PHY is not set > >> > # CONFIG_NATIONAL_PHY is not set > >> > # CONFIG_NXP_TJA11XX_PHY is not set > >> > # CONFIG_QSEMI_PHY is not set > >> > CONFIG_REALTEK_PHY=y > >> > # CONFIG_RENESAS_PHY is not set > >> > # CONFIG_ROCKCHIP_PHY is not set > >> > # CONFIG_SMSC_PHY is not set > >> > # CONFIG_STE10XP is not set > >> > # CONFIG_TERANETICS_PHY is not set > >> > # CONFIG_VITESSE_PHY is not set > >> > # CONFIG_XILINX_GMII2RGMII is not set > >> > # CONFIG_PPP is not set > >> > # CONFIG_SLIP is not set > >> > # CONFIG_USB_NET_DRIVERS is not set > >> > # CONFIG_WLAN is not set > >> > > >> > # > >> > # Enable WiMAX (Networking options) to see the WiMAX drivers > >> > # > >> > # CONFIG_WAN is not set > >> > # CONFIG_VMXNET3 is not set > >> > # CONFIG_FUJITSU_ES is not set > >> > # CONFIG_NETDEVSIM is not set > >> > # CONFIG_NET_FAILOVER is not set > >> > # CONFIG_ISDN is not set > >> > # CONFIG_NVM is not set > >> > > >> > # > >> > # Input device support > >> > # > >> > CONFIG_INPUT=y > >> > # CONFIG_INPUT_FF_MEMLESS is not set > >> > # CONFIG_INPUT_POLLDEV is not set > >> > # CONFIG_INPUT_SPARSEKMAP is not set > >> > # CONFIG_INPUT_MATRIXKMAP is not set > >> > > >> > # > >> > # Userland interfaces > >> > # > >> > CONFIG_INPUT_MOUSEDEV=y > >> > CONFIG_INPUT_MOUSEDEV_PSAUX=y > >> > CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 > >> > CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 > >> > # CONFIG_INPUT_JOYDEV is not set > >> > CONFIG_INPUT_EVDEV=y > >> > # CONFIG_INPUT_EVBUG is not set > >> > > >> > # > >> > # Input Device Drivers > >> > # > >> > CONFIG_INPUT_KEYBOARD=y > >> > # CONFIG_KEYBOARD_ADP5588 is not set > >> > # CONFIG_KEYBOARD_ADP5589 is not set > >> > CONFIG_KEYBOARD_ATKBD=y > >> > # CONFIG_KEYBOARD_QT1050 is not set > >> > # CONFIG_KEYBOARD_QT1070 is not set > >> > # CONFIG_KEYBOARD_QT2160 is not set > >> > # CONFIG_KEYBOARD_DLINK_DIR685 is not set > >> > # CONFIG_KEYBOARD_LKKBD is not set > >> > # CONFIG_KEYBOARD_TCA6416 is not set > >> > # CONFIG_KEYBOARD_TCA8418 is not set > >> > # CONFIG_KEYBOARD_LM8333 is not set > >> > # CONFIG_KEYBOARD_MAX7359 is not set > >> > # CONFIG_KEYBOARD_MCS is not set > >> > # CONFIG_KEYBOARD_MPR121 is not set > >> > # CONFIG_KEYBOARD_NEWTON is not set > >> > # CONFIG_KEYBOARD_OPENCORES is not set > >> > # CONFIG_KEYBOARD_SAMSUNG is not set > >> > # CONFIG_KEYBOARD_STOWAWAY is not set > >> > # CONFIG_KEYBOARD_SUNKBD is not set > >> > # CONFIG_KEYBOARD_XTKBD is not set > >> > CONFIG_INPUT_MOUSE=y > >> > CONFIG_MOUSE_PS2=y > >> > # CONFIG_MOUSE_PS2_ALPS is not set > >> > # CONFIG_MOUSE_PS2_BYD is not set > >> > # CONFIG_MOUSE_PS2_LOGIPS2PP is not set > >> > # CONFIG_MOUSE_PS2_SYNAPTICS is not set > >> > CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y > >> > # CONFIG_MOUSE_PS2_CYPRESS is not set > >> > # CONFIG_MOUSE_PS2_LIFEBOOK is not set > >> > # CONFIG_MOUSE_PS2_TRACKPOINT is not set > >> > # CONFIG_MOUSE_PS2_ELANTECH is not set > >> > # CONFIG_MOUSE_PS2_SENTELIC is not set > >> > # CONFIG_MOUSE_PS2_TOUCHKIT is not set > >> > # CONFIG_MOUSE_PS2_FOCALTECH is not set > >> > CONFIG_MOUSE_PS2_SMBUS=y > >> > # CONFIG_MOUSE_SERIAL is not set > >> > # CONFIG_MOUSE_APPLETOUCH is not set > >> > # CONFIG_MOUSE_BCM5974 is not set > >> > # CONFIG_MOUSE_CYAPA is not set > >> > # CONFIG_MOUSE_ELAN_I2C is not set > >> > # CONFIG_MOUSE_VSXXXAA is not set > >> > # CONFIG_MOUSE_SYNAPTICS_I2C is not set > >> > # CONFIG_MOUSE_SYNAPTICS_USB is not set > >> > # CONFIG_INPUT_JOYSTICK is not set > >> > # CONFIG_INPUT_TABLET is not set > >> > # CONFIG_INPUT_TOUCHSCREEN is not set > >> > # CONFIG_INPUT_MISC is not set > >> > # CONFIG_RMI4_CORE is not set > >> > > >> > # > >> > # Hardware I/O ports > >> > # > >> > CONFIG_SERIO=y > >> > CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y > >> > CONFIG_SERIO_I8042=y > >> > # CONFIG_SERIO_SERPORT is not set > >> > # CONFIG_SERIO_CT82C710 is not set > >> > # CONFIG_SERIO_PCIPS2 is not set > >> > CONFIG_SERIO_LIBPS2=y > >> > # CONFIG_SERIO_RAW is not set > >> > # CONFIG_SERIO_ALTERA_PS2 is not set > >> > # CONFIG_SERIO_PS2MULT is not set > >> > # CONFIG_SERIO_ARC_PS2 is not set > >> > # CONFIG_USERIO is not set > >> > # CONFIG_GAMEPORT is not set > >> > # end of Hardware I/O ports > >> > # end of Input device support > >> > > >> > # > >> > # Character devices > >> > # > >> > CONFIG_TTY=y > >> > CONFIG_VT=y > >> > CONFIG_CONSOLE_TRANSLATIONS=y > >> > CONFIG_VT_CONSOLE=y > >> > CONFIG_HW_CONSOLE=y > >> > # CONFIG_VT_HW_CONSOLE_BINDING is not set > >> > CONFIG_UNIX98_PTYS=y > >> > CONFIG_LEGACY_PTYS=y > >> > CONFIG_LEGACY_PTY_COUNT=256 > >> > CONFIG_LDISC_AUTOLOAD=y > >> > > >> > # > >> > # Serial drivers > >> > # > >> > CONFIG_SERIAL_EARLYCON=y > >> > CONFIG_SERIAL_8250=y > >> > CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y > >> > CONFIG_SERIAL_8250_PNP=y > >> > # CONFIG_SERIAL_8250_16550A_VARIANTS is not set > >> > # CONFIG_SERIAL_8250_FINTEK is not set > >> > CONFIG_SERIAL_8250_CONSOLE=y > >> > CONFIG_SERIAL_8250_PCI=y > >> > # CONFIG_SERIAL_8250_EXAR is not set > >> > CONFIG_SERIAL_8250_NR_UARTS=4 > >> > CONFIG_SERIAL_8250_RUNTIME_UARTS=4 > >> > CONFIG_SERIAL_8250_EXTENDED=y > >> > # CONFIG_SERIAL_8250_MANY_PORTS is not set > >> > CONFIG_SERIAL_8250_SHARE_IRQ=y > >> > # CONFIG_SERIAL_8250_DETECT_IRQ is not set > >> > # CONFIG_SERIAL_8250_RSA is not set > >> > CONFIG_SERIAL_8250_DWLIB=y > >> > # CONFIG_SERIAL_8250_DW is not set > >> > # CONFIG_SERIAL_8250_RT288X is not set > >> > CONFIG_SERIAL_8250_LPSS=y > >> > CONFIG_SERIAL_8250_MID=y > >> > > >> > # > >> > # Non-8250 serial port support > >> > # > >> > # CONFIG_SERIAL_UARTLITE is not set > >> > CONFIG_SERIAL_CORE=y > >> > CONFIG_SERIAL_CORE_CONSOLE=y > >> > # CONFIG_SERIAL_JSM is not set > >> > # CONFIG_SERIAL_SCCNXP is not set > >> > # CONFIG_SERIAL_SC16IS7XX is not set > >> > # CONFIG_SERIAL_ALTERA_JTAGUART is not set > >> > # CONFIG_SERIAL_ALTERA_UART is not set > >> > # CONFIG_SERIAL_ARC is not set > >> > # CONFIG_SERIAL_RP2 is not set > >> > # CONFIG_SERIAL_FSL_LPUART is not set > >> > # CONFIG_SERIAL_FSL_LINFLEXUART is not set > >> > # CONFIG_SERIAL_SPRD is not set > >> > # end of Serial drivers > >> > > >> > # CONFIG_SERIAL_NONSTANDARD is not set > >> > # CONFIG_N_GSM is not set > >> > # CONFIG_NOZOMI is not set > >> > # CONFIG_NULL_TTY is not set > >> > # CONFIG_TRACE_SINK is not set > >> > # CONFIG_SERIAL_DEV_BUS is not set > >> > # CONFIG_TTY_PRINTK is not set > >> > CONFIG_IPMI_HANDLER=y > >> > CONFIG_IPMI_DMI_DECODE=y > >> > CONFIG_IPMI_PLAT_DATA=y > >> > # CONFIG_IPMI_PANIC_EVENT is not set > >> > CONFIG_IPMI_DEVICE_INTERFACE=y > >> > CONFIG_IPMI_SI=y > >> > CONFIG_IPMI_SSIF=y > >> > # CONFIG_IPMI_WATCHDOG is not set > >> > # CONFIG_IPMI_POWEROFF is not set > >> > # CONFIG_HW_RANDOM is not set > >> > # CONFIG_APPLICOM is not set > >> > # CONFIG_MWAVE is not set > >> > # CONFIG_DEVMEM is not set > >> > CONFIG_DEVKMEM=y > >> > # CONFIG_NVRAM is not set > >> > # CONFIG_RAW_DRIVER is not set > >> > CONFIG_DEVPORT=y > >> > CONFIG_HPET=y > >> > CONFIG_HPET_MMAP=y > >> > CONFIG_HPET_MMAP_DEFAULT=y > >> > # CONFIG_HANGCHECK_TIMER is not set > >> > CONFIG_TCG_TPM=y > >> > # CONFIG_TCG_TIS is not set > >> > # CONFIG_TCG_TIS_I2C_ATMEL is not set > >> > # CONFIG_TCG_TIS_I2C_INFINEON is not set > >> > # CONFIG_TCG_TIS_I2C_NUVOTON is not set > >> > # CONFIG_TCG_NSC is not set > >> > # CONFIG_TCG_ATMEL is not set > >> > # CONFIG_TCG_INFINEON is not set > >> > # CONFIG_TCG_CRB is not set > >> > CONFIG_TCG_VTPM_PROXY=y > >> > # CONFIG_TCG_TIS_ST33ZP24_I2C is not set > >> > # CONFIG_TELCLOCK is not set > >> > # CONFIG_XILLYBUS is not set > >> > # end of Character devices > >> > > >> > # CONFIG_RANDOM_TRUST_CPU is not set > >> > # CONFIG_RANDOM_TRUST_BOOTLOADER is not set > >> > > >> > # > >> > # I2C support > >> > # > >> > CONFIG_I2C=y > >> > CONFIG_ACPI_I2C_OPREGION=y > >> > CONFIG_I2C_BOARDINFO=y > >> > CONFIG_I2C_COMPAT=y > >> > CONFIG_I2C_CHARDEV=y > >> > CONFIG_I2C_MUX=y > >> > > >> > # > >> > # Multiplexer I2C Chip support > >> > # > >> > # CONFIG_I2C_MUX_LTC4306 is not set > >> > # CONFIG_I2C_MUX_PCA9541 is not set > >> > # CONFIG_I2C_MUX_REG is not set > >> > # CONFIG_I2C_MUX_MLXCPLD is not set > >> > # end of Multiplexer I2C Chip support > >> > > >> > CONFIG_I2C_HELPER_AUTO=y > >> > CONFIG_I2C_SMBUS=y > >> > CONFIG_I2C_ALGOBIT=y > >> > > >> > # > >> > # I2C Hardware Bus support > >> > # > >> > > >> > # > >> > # PC SMBus host controller drivers > >> > # > >> > # CONFIG_I2C_ALI1535 is not set > >> > # CONFIG_I2C_ALI1563 is not set > >> > # CONFIG_I2C_ALI15X3 is not set > >> > # CONFIG_I2C_AMD756 is not set > >> > # CONFIG_I2C_AMD8111 is not set > >> > # CONFIG_I2C_AMD_MP2 is not set > >> > CONFIG_I2C_I801=y > >> > # CONFIG_I2C_ISCH is not set > >> > # CONFIG_I2C_ISMT is not set > >> > # CONFIG_I2C_PIIX4 is not set > >> > # CONFIG_I2C_NFORCE2 is not set > >> > # CONFIG_I2C_NVIDIA_GPU is not set > >> > # CONFIG_I2C_SIS5595 is not set > >> > # CONFIG_I2C_SIS630 is not set > >> > # CONFIG_I2C_SIS96X is not set > >> > # CONFIG_I2C_VIA is not set > >> > # CONFIG_I2C_VIAPRO is not set > >> > > >> > # > >> > # ACPI drivers > >> > # > >> > CONFIG_I2C_SCMI=y > >> > > >> > # > >> > # I2C system bus drivers (mostly embedded / system-on-chip) > >> > # > >> > # CONFIG_I2C_DESIGNWARE_PLATFORM is not set > >> > # CONFIG_I2C_DESIGNWARE_PCI is not set > >> > # CONFIG_I2C_EMEV2 is not set > >> > # CONFIG_I2C_OCORES is not set > >> > # CONFIG_I2C_PCA_PLATFORM is not set > >> > # CONFIG_I2C_SIMTEC is not set > >> > # CONFIG_I2C_XILINX is not set > >> > > >> > # > >> > # External I2C/SMBus adapter drivers > >> > # > >> > # CONFIG_I2C_DIOLAN_U2C is not set > >> > # CONFIG_I2C_ROBOTFUZZ_OSIF is not set > >> > # CONFIG_I2C_TAOS_EVM is not set > >> > # CONFIG_I2C_TINY_USB is not set > >> > > >> > # > >> > # Other I2C/SMBus bus drivers > >> > # > >> > # CONFIG_I2C_MLXCPLD is not set > >> > # end of I2C Hardware Bus support > >> > > >> > # CONFIG_I2C_STUB is not set > >> > # CONFIG_I2C_SLAVE is not set > >> > # CONFIG_I2C_DEBUG_CORE is not set > >> > # CONFIG_I2C_DEBUG_ALGO is not set > >> > # CONFIG_I2C_DEBUG_BUS is not set > >> > # end of I2C support > >> > > >> > # CONFIG_I3C is not set > >> > # CONFIG_SPI is not set > >> > # CONFIG_SPMI is not set > >> > # CONFIG_HSI is not set > >> > CONFIG_PPS=y > >> > # CONFIG_PPS_DEBUG is not set > >> > > >> > # > >> > # PPS clients support > >> > # > >> > # CONFIG_PPS_CLIENT_KTIMER is not set > >> > # CONFIG_PPS_CLIENT_LDISC is not set > >> > # CONFIG_PPS_CLIENT_GPIO is not set > >> > > >> > # > >> > # PPS generators support > >> > # > >> > > >> > # > >> > # PTP clock support > >> > # > >> > CONFIG_PTP_1588_CLOCK=y > >> > > >> > # > >> > # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. > >> > # > >> > # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set > >> > # CONFIG_PTP_1588_CLOCK_IDTCM is not set > >> > # end of PTP clock support > >> > > >> > # CONFIG_PINCTRL is not set > >> > # CONFIG_GPIOLIB is not set > >> > # CONFIG_W1 is not set > >> > # CONFIG_POWER_AVS is not set > >> > # CONFIG_POWER_RESET is not set > >> > CONFIG_POWER_SUPPLY=y > >> > # CONFIG_POWER_SUPPLY_DEBUG is not set > >> > CONFIG_POWER_SUPPLY_HWMON=y > >> > # CONFIG_PDA_POWER is not set > >> > # CONFIG_TEST_POWER is not set > >> > # CONFIG_CHARGER_ADP5061 is not set > >> > # CONFIG_BATTERY_DS2780 is not set > >> > # CONFIG_BATTERY_DS2781 is not set > >> > # CONFIG_BATTERY_DS2782 is not set > >> > # CONFIG_BATTERY_SBS is not set > >> > # CONFIG_CHARGER_SBS is not set > >> > # CONFIG_BATTERY_BQ27XXX is not set > >> > # CONFIG_BATTERY_MAX17040 is not set > >> > # CONFIG_BATTERY_MAX17042 is not set > >> > # CONFIG_CHARGER_MAX8903 is not set > >> > # CONFIG_CHARGER_LP8727 is not set > >> > # CONFIG_CHARGER_BQ2415X is not set > >> > # CONFIG_CHARGER_SMB347 is not set > >> > # CONFIG_BATTERY_GAUGE_LTC2941 is not set > >> > CONFIG_HWMON=y > >> > # CONFIG_HWMON_DEBUG_CHIP is not set > >> > > >> > # > >> > # Native drivers > >> > # > >> > # CONFIG_SENSORS_ABITUGURU is not set > >> > # CONFIG_SENSORS_ABITUGURU3 is not set > >> > # CONFIG_SENSORS_AD7414 is not set > >> > # CONFIG_SENSORS_AD7418 is not set > >> > # CONFIG_SENSORS_ADM1021 is not set > >> > # CONFIG_SENSORS_ADM1025 is not set > >> > # CONFIG_SENSORS_ADM1026 is not set > >> > # CONFIG_SENSORS_ADM1029 is not set > >> > # CONFIG_SENSORS_ADM1031 is not set > >> > # CONFIG_SENSORS_ADM1177 is not set > >> > # CONFIG_SENSORS_ADM9240 is not set > >> > # CONFIG_SENSORS_ADT7410 is not set > >> > # CONFIG_SENSORS_ADT7411 is not set > >> > # CONFIG_SENSORS_ADT7462 is not set > >> > # CONFIG_SENSORS_ADT7470 is not set > >> > # CONFIG_SENSORS_ADT7475 is not set > >> > # CONFIG_SENSORS_AS370 is not set > >> > # CONFIG_SENSORS_ASC7621 is not set > >> > # CONFIG_SENSORS_AXI_FAN_CONTROL is not set > >> > # CONFIG_SENSORS_K8TEMP is not set > >> > # CONFIG_SENSORS_K10TEMP is not set > >> > # CONFIG_SENSORS_FAM15H_POWER is not set > >> > # CONFIG_SENSORS_APPLESMC is not set > >> > # CONFIG_SENSORS_ASB100 is not set > >> > # CONFIG_SENSORS_ASPEED is not set > >> > # CONFIG_SENSORS_ATXP1 is not set > >> > # CONFIG_SENSORS_DRIVETEMP is not set > >> > # CONFIG_SENSORS_DS620 is not set > >> > # CONFIG_SENSORS_DS1621 is not set > >> > # CONFIG_SENSORS_DELL_SMM is not set > >> > # CONFIG_SENSORS_I5K_AMB is not set > >> > # CONFIG_SENSORS_F71805F is not set > >> > # CONFIG_SENSORS_F71882FG is not set > >> > # CONFIG_SENSORS_F75375S is not set > >> > # CONFIG_SENSORS_FSCHMD is not set > >> > # CONFIG_SENSORS_FTSTEUTATES is not set > >> > # CONFIG_SENSORS_GL518SM is not set > >> > # CONFIG_SENSORS_GL520SM is not set > >> > # CONFIG_SENSORS_G760A is not set > >> > # CONFIG_SENSORS_G762 is not set > >> > # CONFIG_SENSORS_HIH6130 is not set > >> > # CONFIG_SENSORS_IBMAEM is not set > >> > # CONFIG_SENSORS_IBMPEX is not set > >> > # CONFIG_SENSORS_I5500 is not set > >> > CONFIG_SENSORS_CORETEMP=y > >> > # CONFIG_SENSORS_IT87 is not set > >> > # CONFIG_SENSORS_JC42 is not set > >> > # CONFIG_SENSORS_POWR1220 is not set > >> > # CONFIG_SENSORS_LINEAGE is not set > >> > # CONFIG_SENSORS_LTC2945 is not set > >> > # CONFIG_SENSORS_LTC2947_I2C is not set > >> > # CONFIG_SENSORS_LTC2990 is not set > >> > # CONFIG_SENSORS_LTC4151 is not set > >> > # CONFIG_SENSORS_LTC4215 is not set > >> > # CONFIG_SENSORS_LTC4222 is not set > >> > # CONFIG_SENSORS_LTC4245 is not set > >> > # CONFIG_SENSORS_LTC4260 is not set > >> > # CONFIG_SENSORS_LTC4261 is not set > >> > # CONFIG_SENSORS_MAX16065 is not set > >> > # CONFIG_SENSORS_MAX1619 is not set > >> > # CONFIG_SENSORS_MAX1668 is not set > >> > # CONFIG_SENSORS_MAX197 is not set > >> > # CONFIG_SENSORS_MAX31730 is not set > >> > # CONFIG_SENSORS_MAX6621 is not set > >> > # CONFIG_SENSORS_MAX6639 is not set > >> > # CONFIG_SENSORS_MAX6642 is not set > >> > # CONFIG_SENSORS_MAX6650 is not set > >> > # CONFIG_SENSORS_MAX6697 is not set > >> > # CONFIG_SENSORS_MAX31790 is not set > >> > # CONFIG_SENSORS_MCP3021 is not set > >> > # CONFIG_SENSORS_TC654 is not set > >> > # CONFIG_SENSORS_LM63 is not set > >> > # CONFIG_SENSORS_LM73 is not set > >> > # CONFIG_SENSORS_LM75 is not set > >> > # CONFIG_SENSORS_LM77 is not set > >> > # CONFIG_SENSORS_LM78 is not set > >> > # CONFIG_SENSORS_LM80 is not set > >> > # CONFIG_SENSORS_LM83 is not set > >> > # CONFIG_SENSORS_LM85 is not set > >> > # CONFIG_SENSORS_LM87 is not set > >> > # CONFIG_SENSORS_LM90 is not set > >> > # CONFIG_SENSORS_LM92 is not set > >> > # CONFIG_SENSORS_LM93 is not set > >> > # CONFIG_SENSORS_LM95234 is not set > >> > # CONFIG_SENSORS_LM95241 is not set > >> > # CONFIG_SENSORS_LM95245 is not set > >> > # CONFIG_SENSORS_PC87360 is not set > >> > # CONFIG_SENSORS_PC87427 is not set > >> > # CONFIG_SENSORS_NTC_THERMISTOR is not set > >> > # CONFIG_SENSORS_NCT6683 is not set > >> > # CONFIG_SENSORS_NCT6775 is not set > >> > # CONFIG_SENSORS_NCT7802 is not set > >> > # CONFIG_SENSORS_NCT7904 is not set > >> > # CONFIG_SENSORS_NPCM7XX is not set > >> > # CONFIG_SENSORS_PCF8591 is not set > >> > CONFIG_PMBUS=y > >> > CONFIG_SENSORS_PMBUS=y > >> > # CONFIG_SENSORS_ADM1275 is not set > >> > # CONFIG_SENSORS_BEL_PFE is not set > >> > # CONFIG_SENSORS_INSPUR_IPSPS is not set > >> > # CONFIG_SENSORS_IR35221 is not set > >> > # CONFIG_SENSORS_IR38064 is not set > >> > # CONFIG_SENSORS_IRPS5401 is not set > >> > # CONFIG_SENSORS_ISL68137 is not set > >> > # CONFIG_SENSORS_LM25066 is not set > >> > # CONFIG_SENSORS_LTC2978 is not set > >> > # CONFIG_SENSORS_LTC3815 is not set > >> > # CONFIG_SENSORS_MAX16064 is not set > >> > # CONFIG_SENSORS_MAX20730 is not set > >> > # CONFIG_SENSORS_MAX20751 is not set > >> > # CONFIG_SENSORS_MAX31785 is not set > >> > # CONFIG_SENSORS_MAX34440 is not set > >> > # CONFIG_SENSORS_MAX8688 is not set > >> > # CONFIG_SENSORS_PXE1610 is not set > >> > # CONFIG_SENSORS_TPS40422 is not set > >> > # CONFIG_SENSORS_TPS53679 is not set > >> > # CONFIG_SENSORS_UCD9000 is not set > >> > # CONFIG_SENSORS_UCD9200 is not set > >> > # CONFIG_SENSORS_XDPE122 is not set > >> > # CONFIG_SENSORS_ZL6100 is not set > >> > # CONFIG_SENSORS_SHT21 is not set > >> > # CONFIG_SENSORS_SHT3x is not set > >> > # CONFIG_SENSORS_SHTC1 is not set > >> > # CONFIG_SENSORS_SIS5595 is not set > >> > # CONFIG_SENSORS_DME1737 is not set > >> > # CONFIG_SENSORS_EMC1403 is not set > >> > # CONFIG_SENSORS_EMC2103 is not set > >> > # CONFIG_SENSORS_EMC6W201 is not set > >> > # CONFIG_SENSORS_SMSC47M1 is not set > >> > # CONFIG_SENSORS_SMSC47M192 is not set > >> > # CONFIG_SENSORS_SMSC47B397 is not set > >> > # CONFIG_SENSORS_SCH5627 is not set > >> > # CONFIG_SENSORS_SCH5636 is not set > >> > # CONFIG_SENSORS_STTS751 is not set > >> > # CONFIG_SENSORS_SMM665 is not set > >> > # CONFIG_SENSORS_ADC128D818 is not set > >> > # CONFIG_SENSORS_ADS7828 is not set > >> > # CONFIG_SENSORS_AMC6821 is not set > >> > # CONFIG_SENSORS_INA209 is not set > >> > # CONFIG_SENSORS_INA2XX is not set > >> > # CONFIG_SENSORS_INA3221 is not set > >> > # CONFIG_SENSORS_TC74 is not set > >> > # CONFIG_SENSORS_THMC50 is not set > >> > # CONFIG_SENSORS_TMP102 is not set > >> > # CONFIG_SENSORS_TMP103 is not set > >> > # CONFIG_SENSORS_TMP108 is not set > >> > # CONFIG_SENSORS_TMP401 is not set > >> > # CONFIG_SENSORS_TMP421 is not set > >> > # CONFIG_SENSORS_TMP513 is not set > >> > # CONFIG_SENSORS_VIA_CPUTEMP is not set > >> > # CONFIG_SENSORS_VIA686A is not set > >> > # CONFIG_SENSORS_VT1211 is not set > >> > # CONFIG_SENSORS_VT8231 is not set > >> > # CONFIG_SENSORS_W83773G is not set > >> > # CONFIG_SENSORS_W83781D is not set > >> > # CONFIG_SENSORS_W83791D is not set > >> > # CONFIG_SENSORS_W83792D is not set > >> > # CONFIG_SENSORS_W83793 is not set > >> > # CONFIG_SENSORS_W83795 is not set > >> > # CONFIG_SENSORS_W83L785TS is not set > >> > # CONFIG_SENSORS_W83L786NG is not set > >> > # CONFIG_SENSORS_W83627HF is not set > >> > # CONFIG_SENSORS_W83627EHF is not set > >> > # CONFIG_SENSORS_XGENE is not set > >> > > >> > # > >> > # ACPI drivers > >> > # > >> > CONFIG_SENSORS_ACPI_POWER=y > >> > CONFIG_SENSORS_ATK0110=y > >> > CONFIG_THERMAL=y > >> > # CONFIG_THERMAL_STATISTICS is not set > >> > CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 > >> > CONFIG_THERMAL_HWMON=y > >> > CONFIG_THERMAL_WRITABLE_TRIPS=y > >> > CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y > >> > # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set > >> > # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set > >> > # CONFIG_THERMAL_GOV_FAIR_SHARE is not set > >> > CONFIG_THERMAL_GOV_STEP_WISE=y > >> > # CONFIG_THERMAL_GOV_BANG_BANG is not set > >> > CONFIG_THERMAL_GOV_USER_SPACE=y > >> > # CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set > >> > # CONFIG_THERMAL_EMULATION is not set > >> > > >> > # > >> > # Intel thermal drivers > >> > # > >> > # CONFIG_INTEL_POWERCLAMP is not set > >> > CONFIG_X86_PKG_TEMP_THERMAL=y > >> > # CONFIG_INTEL_SOC_DTS_THERMAL is not set > >> > > >> > # > >> > # ACPI INT340X thermal drivers > >> > # > >> > # CONFIG_INT340X_THERMAL is not set > >> > # end of ACPI INT340X thermal drivers > >> > > >> > CONFIG_INTEL_PCH_THERMAL=y > >> > # end of Intel thermal drivers > >> > > >> > CONFIG_WATCHDOG=y > >> > CONFIG_WATCHDOG_CORE=y > >> > # CONFIG_WATCHDOG_NOWAYOUT is not set > >> > CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y > >> > CONFIG_WATCHDOG_OPEN_TIMEOUT=0 > >> > # CONFIG_WATCHDOG_SYSFS is not set > >> > > >> > # > >> > # Watchdog Pretimeout Governors > >> > # > >> > # CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set > >> > > >> > # > >> > # Watchdog Device Drivers > >> > # > >> > # CONFIG_SOFT_WATCHDOG is not set > >> > # CONFIG_WDAT_WDT is not set > >> > # CONFIG_XILINX_WATCHDOG is not set > >> > # CONFIG_ZIIRAVE_WATCHDOG is not set > >> > # CONFIG_CADENCE_WATCHDOG is not set > >> > # CONFIG_DW_WATCHDOG is not set > >> > # CONFIG_MAX63XX_WATCHDOG is not set > >> > # CONFIG_ACQUIRE_WDT is not set > >> > # CONFIG_ADVANTECH_WDT is not set > >> > # CONFIG_ALIM1535_WDT is not set > >> > # CONFIG_ALIM7101_WDT is not set > >> > # CONFIG_EBC_C384_WDT is not set > >> > # CONFIG_F71808E_WDT is not set > >> > # CONFIG_SP5100_TCO is not set > >> > # CONFIG_SBC_FITPC2_WATCHDOG is not set > >> > # CONFIG_EUROTECH_WDT is not set > >> > # CONFIG_IB700_WDT is not set > >> > # CONFIG_IBMASR is not set > >> > # CONFIG_WAFER_WDT is not set > >> > # CONFIG_I6300ESB_WDT is not set > >> > # CONFIG_IE6XX_WDT is not set > >> > CONFIG_ITCO_WDT=y > >> > CONFIG_ITCO_VENDOR_SUPPORT=y > >> > # CONFIG_IT8712F_WDT is not set > >> > # CONFIG_IT87_WDT is not set > >> > # CONFIG_HP_WATCHDOG is not set > >> > # CONFIG_SC1200_WDT is not set > >> > # CONFIG_PC87413_WDT is not set > >> > # CONFIG_NV_TCO is not set > >> > # CONFIG_60XX_WDT is not set > >> > # CONFIG_CPU5_WDT is not set > >> > # CONFIG_SMSC_SCH311X_WDT is not set > >> > # CONFIG_SMSC37B787_WDT is not set > >> > # CONFIG_TQMX86_WDT is not set > >> > # CONFIG_VIA_WDT is not set > >> > # CONFIG_W83627HF_WDT is not set > >> > # CONFIG_W83877F_WDT is not set > >> > # CONFIG_W83977F_WDT is not set > >> > # CONFIG_MACHZ_WDT is not set > >> > # CONFIG_SBC_EPX_C3_WATCHDOG is not set > >> > CONFIG_INTEL_MEI_WDT=y > >> > # CONFIG_NI903X_WDT is not set > >> > # CONFIG_NIC7018_WDT is not set > >> > > >> > # > >> > # PCI-based Watchdog Cards > >> > # > >> > # CONFIG_PCIPCWATCHDOG is not set > >> > # CONFIG_WDTPCI is not set > >> > > >> > # > >> > # USB-based Watchdog Cards > >> > # > >> > # CONFIG_USBPCWATCHDOG is not set > >> > CONFIG_SSB_POSSIBLE=y > >> > # CONFIG_SSB is not set > >> > CONFIG_BCMA_POSSIBLE=y > >> > # CONFIG_BCMA is not set > >> > > >> > # > >> > # Multifunction device drivers > >> > # > >> > CONFIG_MFD_CORE=y > >> > # CONFIG_MFD_AS3711 is not set > >> > # CONFIG_PMIC_ADP5520 is not set > >> > # CONFIG_MFD_BCM590XX is not set > >> > # CONFIG_MFD_BD9571MWV is not set > >> > # CONFIG_MFD_AXP20X_I2C is not set > >> > # CONFIG_MFD_MADERA is not set > >> > # CONFIG_PMIC_DA903X is not set > >> > # CONFIG_MFD_DA9052_I2C is not set > >> > # CONFIG_MFD_DA9055 is not set > >> > # CONFIG_MFD_DA9062 is not set > >> > # CONFIG_MFD_DA9063 is not set > >> > # CONFIG_MFD_DA9150 is not set > >> > # CONFIG_MFD_DLN2 is not set > >> > # CONFIG_MFD_MC13XXX_I2C is not set > >> > # CONFIG_HTC_PASIC3 is not set > >> > # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set > >> > CONFIG_LPC_ICH=y > >> > # CONFIG_LPC_SCH is not set > >> > CONFIG_MFD_INTEL_LPSS=y > >> > CONFIG_MFD_INTEL_LPSS_ACPI=y > >> > CONFIG_MFD_INTEL_LPSS_PCI=y > >> > # CONFIG_MFD_IQS62X is not set > >> > # CONFIG_MFD_JANZ_CMODIO is not set > >> > # CONFIG_MFD_KEMPLD is not set > >> > # CONFIG_MFD_88PM800 is not set > >> > # CONFIG_MFD_88PM805 is not set > >> > # CONFIG_MFD_88PM860X is not set > >> > # CONFIG_MFD_MAX14577 is not set > >> > # CONFIG_MFD_MAX77693 is not set > >> > # CONFIG_MFD_MAX77843 is not set > >> > # CONFIG_MFD_MAX8907 is not set > >> > # CONFIG_MFD_MAX8925 is not set > >> > # CONFIG_MFD_MAX8997 is not set > >> > # CONFIG_MFD_MAX8998 is not set > >> > # CONFIG_MFD_MT6397 is not set > >> > # CONFIG_MFD_MENF21BMC is not set > >> > # CONFIG_MFD_VIPERBOARD is not set > >> > # CONFIG_MFD_RETU is not set > >> > # CONFIG_MFD_PCF50633 is not set > >> > # CONFIG_MFD_RDC321X is not set > >> > # CONFIG_MFD_RT5033 is not set > >> > # CONFIG_MFD_RC5T583 is not set > >> > # CONFIG_MFD_SEC_CORE is not set > >> > # CONFIG_MFD_SI476X_CORE is not set > >> > # CONFIG_MFD_SM501 is not set > >> > # CONFIG_MFD_SKY81452 is not set > >> > # CONFIG_MFD_SMSC is not set > >> > # CONFIG_ABX500_CORE is not set > >> > # CONFIG_MFD_SYSCON is not set > >> > # CONFIG_MFD_TI_AM335X_TSCADC is not set > >> > # CONFIG_MFD_LP3943 is not set > >> > # CONFIG_MFD_LP8788 is not set > >> > # CONFIG_MFD_TI_LMU is not set > >> > # CONFIG_MFD_PALMAS is not set > >> > # CONFIG_TPS6105X is not set > >> > # CONFIG_TPS6507X is not set > >> > # CONFIG_MFD_TPS65086 is not set > >> > # CONFIG_MFD_TPS65090 is not set > >> > # CONFIG_MFD_TI_LP873X is not set > >> > # CONFIG_MFD_TPS6586X is not set > >> > # CONFIG_MFD_TPS65912_I2C is not set > >> > # CONFIG_MFD_TPS80031 is not set > >> > # CONFIG_TWL4030_CORE is not set > >> > # CONFIG_TWL6040_CORE is not set > >> > # CONFIG_MFD_WL1273_CORE is not set > >> > # CONFIG_MFD_LM3533 is not set > >> > # CONFIG_MFD_TQMX86 is not set > >> > # CONFIG_MFD_VX855 is not set > >> > # CONFIG_MFD_ARIZONA_I2C is not set > >> > # CONFIG_MFD_WM8400 is not set > >> > # CONFIG_MFD_WM831X_I2C is not set > >> > # CONFIG_MFD_WM8350_I2C is not set > >> > # CONFIG_MFD_WM8994 is not set > >> > # end of Multifunction device drivers > >> > > >> > # CONFIG_REGULATOR is not set > >> > # CONFIG_RC_CORE is not set > >> > # CONFIG_MEDIA_SUPPORT is not set > >> > > >> > # > >> > # Graphics support > >> > # > >> > # CONFIG_AGP is not set > >> > CONFIG_INTEL_GTT=y > >> > CONFIG_VGA_ARB=y > >> > CONFIG_VGA_ARB_MAX_GPUS=16 > >> > # CONFIG_VGA_SWITCHEROO is not set > >> > CONFIG_DRM=y > >> > CONFIG_DRM_MIPI_DSI=y > >> > # CONFIG_DRM_DP_AUX_CHARDEV is not set > >> > # CONFIG_DRM_DEBUG_MM is not set > >> > # CONFIG_DRM_DEBUG_SELFTEST is not set > >> > CONFIG_DRM_KMS_HELPER=y > >> > CONFIG_DRM_KMS_FB_HELPER=y > >> > # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set > >> > CONFIG_DRM_FBDEV_EMULATION=y > >> > CONFIG_DRM_FBDEV_OVERALLOC=100 > >> > # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set > >> > # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set > >> > # CONFIG_DRM_DP_CEC is not set > >> > > >> > # > >> > # I2C encoder or helper chips > >> > # > >> > # CONFIG_DRM_I2C_CH7006 is not set > >> > # CONFIG_DRM_I2C_SIL164 is not set > >> > # CONFIG_DRM_I2C_NXP_TDA998X is not set > >> > # CONFIG_DRM_I2C_NXP_TDA9950 is not set > >> > # end of I2C encoder or helper chips > >> > > >> > # > >> > # ARM devices > >> > # > >> > # end of ARM devices > >> > > >> > # CONFIG_DRM_RADEON is not set > >> > # CONFIG_DRM_AMDGPU is not set > >> > # CONFIG_DRM_NOUVEAU is not set > >> > CONFIG_DRM_I915=y > >> > CONFIG_DRM_I915_FORCE_PROBE="" > >> > CONFIG_DRM_I915_CAPTURE_ERROR=y > >> > CONFIG_DRM_I915_COMPRESS_ERROR=y > >> > CONFIG_DRM_I915_USERPTR=y > >> > # CONFIG_DRM_I915_GVT is not set > >> > > >> > # > >> > # drm/i915 Debugging > >> > # > >> > # CONFIG_DRM_I915_WERROR is not set > >> > # CONFIG_DRM_I915_DEBUG is not set > >> > # CONFIG_DRM_I915_DEBUG_MMIO is not set > >> > # CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set > >> > # CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set > >> > # CONFIG_DRM_I915_DEBUG_GUC is not set > >> > # CONFIG_DRM_I915_SELFTEST is not set > >> > # CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set > >> > # CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set > >> > # CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set > >> > # end of drm/i915 Debugging > >> > > >> > # > >> > # drm/i915 Profile Guided Optimisation > >> > # > >> > CONFIG_DRM_I915_FENCE_TIMEOUT=10000 > >> > CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250 > >> > CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500 > >> > CONFIG_DRM_I915_PREEMPT_TIMEOUT=100 > >> > CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 > >> > CONFIG_DRM_I915_STOP_TIMEOUT=100 > >> > CONFIG_DRM_I915_TIMESLICE_DURATION=1 > >> > # end of drm/i915 Profile Guided Optimisation > >> > > >> > # CONFIG_DRM_VGEM is not set > >> > # CONFIG_DRM_VKMS is not set > >> > # CONFIG_DRM_VMWGFX is not set > >> > # CONFIG_DRM_GMA500 is not set > >> > # CONFIG_DRM_UDL is not set > >> > # CONFIG_DRM_AST is not set > >> > # CONFIG_DRM_MGAG200 is not set > >> > # CONFIG_DRM_QXL is not set > >> > # CONFIG_DRM_BOCHS is not set > >> > CONFIG_DRM_PANEL=y > >> > > >> > # > >> > # Display Panels > >> > # > >> > # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set > >> > # end of Display Panels > >> > > >> > CONFIG_DRM_BRIDGE=y > >> > CONFIG_DRM_PANEL_BRIDGE=y > >> > > >> > # > >> > # Display Interface Bridges > >> > # > >> > # CONFIG_DRM_ANALOGIX_ANX78XX is not set > >> > # end of Display Interface Bridges > >> > > >> > # CONFIG_DRM_ETNAVIV is not set > >> > # CONFIG_DRM_CIRRUS_QEMU is not set > >> > # CONFIG_DRM_GM12U320 is not set > >> > # CONFIG_DRM_VBOXVIDEO is not set > >> > # CONFIG_DRM_LEGACY is not set > >> > CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y > >> > > >> > # > >> > # Frame buffer Devices > >> > # > >> > CONFIG_FB_CMDLINE=y > >> > CONFIG_FB_NOTIFY=y > >> > CONFIG_FB=y > >> > CONFIG_FIRMWARE_EDID=y > >> > CONFIG_FB_CFB_FILLRECT=y > >> > CONFIG_FB_CFB_COPYAREA=y > >> > CONFIG_FB_CFB_IMAGEBLIT=y > >> > CONFIG_FB_SYS_FILLRECT=y > >> > CONFIG_FB_SYS_COPYAREA=y > >> > CONFIG_FB_SYS_IMAGEBLIT=y > >> > # CONFIG_FB_FOREIGN_ENDIAN is not set > >> > CONFIG_FB_SYS_FOPS=y > >> > CONFIG_FB_DEFERRED_IO=y > >> > CONFIG_FB_MODE_HELPERS=y > >> > # CONFIG_FB_TILEBLITTING is not set > >> > > >> > # > >> > # Frame buffer hardware drivers > >> > # > >> > # CONFIG_FB_CIRRUS is not set > >> > # CONFIG_FB_PM2 is not set > >> > # CONFIG_FB_CYBER2000 is not set > >> > # CONFIG_FB_ARC is not set > >> > # CONFIG_FB_ASILIANT is not set > >> > # CONFIG_FB_IMSTT is not set > >> > # CONFIG_FB_VGA16 is not set > >> > # CONFIG_FB_VESA is not set > >> > # CONFIG_FB_EFI is not set > >> > # CONFIG_FB_N411 is not set > >> > # CONFIG_FB_HGA is not set > >> > # CONFIG_FB_OPENCORES is not set > >> > # CONFIG_FB_S1D13XXX is not set > >> > # CONFIG_FB_NVIDIA is not set > >> > # CONFIG_FB_RIVA is not set > >> > # CONFIG_FB_I740 is not set > >> > # CONFIG_FB_LE80578 is not set > >> > # CONFIG_FB_MATROX is not set > >> > # CONFIG_FB_RADEON is not set > >> > # CONFIG_FB_ATY128 is not set > >> > # CONFIG_FB_ATY is not set > >> > # CONFIG_FB_S3 is not set > >> > # CONFIG_FB_SAVAGE is not set > >> > # CONFIG_FB_SIS is not set > >> > # CONFIG_FB_NEOMAGIC is not set > >> > # CONFIG_FB_KYRO is not set > >> > # CONFIG_FB_3DFX is not set > >> > # CONFIG_FB_VOODOO1 is not set > >> > # CONFIG_FB_VT8623 is not set > >> > # CONFIG_FB_TRIDENT is not set > >> > # CONFIG_FB_ARK is not set > >> > # CONFIG_FB_PM3 is not set > >> > # CONFIG_FB_CARMINE is not set > >> > # CONFIG_FB_SMSCUFX is not set > >> > # CONFIG_FB_UDL is not set > >> > # CONFIG_FB_IBM_GXT4500 is not set > >> > # CONFIG_FB_VIRTUAL is not set > >> > # CONFIG_FB_METRONOME is not set > >> > # CONFIG_FB_MB862XX is not set > >> > # CONFIG_FB_SIMPLE is not set > >> > # CONFIG_FB_SM712 is not set > >> > # end of Frame buffer Devices > >> > > >> > # > >> > # Backlight & LCD device support > >> > # > >> > # CONFIG_LCD_CLASS_DEVICE is not set > >> > CONFIG_BACKLIGHT_CLASS_DEVICE=y > >> > # CONFIG_BACKLIGHT_GENERIC is not set > >> > # CONFIG_BACKLIGHT_APPLE is not set > >> > # CONFIG_BACKLIGHT_QCOM_WLED is not set > >> > # CONFIG_BACKLIGHT_SAHARA is not set > >> > # CONFIG_BACKLIGHT_ADP8860 is not set > >> > # CONFIG_BACKLIGHT_ADP8870 is not set > >> > # CONFIG_BACKLIGHT_LM3639 is not set > >> > # CONFIG_BACKLIGHT_LV5207LP is not set > >> > # CONFIG_BACKLIGHT_BD6107 is not set > >> > # CONFIG_BACKLIGHT_ARCXCNN is not set > >> > # end of Backlight & LCD device support > >> > > >> > CONFIG_HDMI=y > >> > > >> > # > >> > # Console display driver support > >> > # > >> > CONFIG_VGA_CONSOLE=y > >> > # CONFIG_VGACON_SOFT_SCROLLBACK is not set > >> > CONFIG_DUMMY_CONSOLE=y > >> > CONFIG_DUMMY_CONSOLE_COLUMNS=80 > >> > CONFIG_DUMMY_CONSOLE_ROWS=25 > >> > # CONFIG_FRAMEBUFFER_CONSOLE is not set > >> > # end of Console display driver support > >> > > >> > CONFIG_LOGO=y > >> > CONFIG_LOGO_LINUX_MONO=y > >> > CONFIG_LOGO_LINUX_VGA16=y > >> > CONFIG_LOGO_LINUX_CLUT224=y > >> > # end of Graphics support > >> > > >> > # CONFIG_SOUND is not set > >> > > >> > # > >> > # HID support > >> > # > >> > CONFIG_HID=y > >> > # CONFIG_HID_BATTERY_STRENGTH is not set > >> > # CONFIG_HIDRAW is not set > >> > # CONFIG_UHID is not set > >> > CONFIG_HID_GENERIC=y > >> > > >> > # > >> > # Special HID drivers > >> > # > >> > # CONFIG_HID_A4TECH is not set > >> > # CONFIG_HID_ACCUTOUCH is not set > >> > # CONFIG_HID_ACRUX is not set > >> > # CONFIG_HID_APPLE is not set > >> > # CONFIG_HID_APPLEIR is not set > >> > # CONFIG_HID_AUREAL is not set > >> > # CONFIG_HID_BELKIN is not set > >> > # CONFIG_HID_BETOP_FF is not set > >> > # CONFIG_HID_CHERRY is not set > >> > # CONFIG_HID_CHICONY is not set > >> > # CONFIG_HID_COUGAR is not set > >> > # CONFIG_HID_MACALLY is not set > >> > # CONFIG_HID_CMEDIA is not set > >> > # CONFIG_HID_CREATIVE_SB0540 is not set > >> > # CONFIG_HID_CYPRESS is not set > >> > # CONFIG_HID_DRAGONRISE is not set > >> > # CONFIG_HID_EMS_FF is not set > >> > # CONFIG_HID_ELECOM is not set > >> > # CONFIG_HID_ELO is not set > >> > # CONFIG_HID_EZKEY is not set > >> > # CONFIG_HID_GEMBIRD is not set > >> > # CONFIG_HID_GFRM is not set > >> > # CONFIG_HID_GLORIOUS is not set > >> > # CONFIG_HID_HOLTEK is not set > >> > # CONFIG_HID_KEYTOUCH is not set > >> > # CONFIG_HID_KYE is not set > >> > # CONFIG_HID_UCLOGIC is not set > >> > # CONFIG_HID_WALTOP is not set > >> > # CONFIG_HID_VIEWSONIC is not set > >> > # CONFIG_HID_GYRATION is not set > >> > # CONFIG_HID_ICADE is not set > >> > # CONFIG_HID_ITE is not set > >> > # CONFIG_HID_JABRA is not set > >> > # CONFIG_HID_TWINHAN is not set > >> > # CONFIG_HID_KENSINGTON is not set > >> > # CONFIG_HID_LCPOWER is not set > >> > # CONFIG_HID_LENOVO is not set > >> > # CONFIG_HID_MAGICMOUSE is not set > >> > # CONFIG_HID_MALTRON is not set > >> > # CONFIG_HID_MAYFLASH is not set > >> > # CONFIG_HID_REDRAGON is not set > >> > # CONFIG_HID_MICROSOFT is not set > >> > # CONFIG_HID_MONTEREY is not set > >> > # CONFIG_HID_MULTITOUCH is not set > >> > # CONFIG_HID_NTI is not set > >> > # CONFIG_HID_NTRIG is not set > >> > # CONFIG_HID_ORTEK is not set > >> > # CONFIG_HID_PANTHERLORD is not set > >> > # CONFIG_HID_PENMOUNT is not set > >> > # CONFIG_HID_PETALYNX is not set > >> > # CONFIG_HID_PICOLCD is not set > >> > # CONFIG_HID_PLANTRONICS is not set > >> > # CONFIG_HID_PRIMAX is not set > >> > # CONFIG_HID_RETRODE is not set > >> > # CONFIG_HID_ROCCAT is not set > >> > # CONFIG_HID_SAITEK is not set > >> > # CONFIG_HID_SAMSUNG is not set > >> > # CONFIG_HID_SPEEDLINK is not set > >> > # CONFIG_HID_STEAM is not set > >> > # CONFIG_HID_STEELSERIES is not set > >> > # CONFIG_HID_SUNPLUS is not set > >> > # CONFIG_HID_RMI is not set > >> > # CONFIG_HID_GREENASIA is not set > >> > # CONFIG_HID_SMARTJOYPLUS is not set > >> > # CONFIG_HID_TIVO is not set > >> > # CONFIG_HID_TOPSEED is not set > >> > # CONFIG_HID_THRUSTMASTER is not set > >> > # CONFIG_HID_UDRAW_PS3 is not set > >> > # CONFIG_HID_WACOM is not set > >> > # CONFIG_HID_XINMO is not set > >> > # CONFIG_HID_ZEROPLUS is not set > >> > # CONFIG_HID_ZYDACRON is not set > >> > # CONFIG_HID_SENSOR_HUB is not set > >> > # CONFIG_HID_ALPS is not set > >> > # CONFIG_HID_MCP2221 is not set > >> > # end of Special HID drivers > >> > > >> > # > >> > # USB HID support > >> > # > >> > CONFIG_USB_HID=y > >> > # CONFIG_HID_PID is not set > >> > # CONFIG_USB_HIDDEV is not set > >> > # end of USB HID support > >> > > >> > # > >> > # I2C HID support > >> > # > >> > # CONFIG_I2C_HID is not set > >> > # end of I2C HID support > >> > > >> > # > >> > # Intel ISH HID support > >> > # > >> > CONFIG_INTEL_ISH_HID=y > >> > # CONFIG_INTEL_ISH_FIRMWARE_DOWNLOADER is not set > >> > # end of Intel ISH HID support > >> > # end of HID support > >> > > >> > CONFIG_USB_OHCI_LITTLE_ENDIAN=y > >> > CONFIG_USB_SUPPORT=y > >> > CONFIG_USB_COMMON=y > >> > # CONFIG_USB_ULPI_BUS is not set > >> > CONFIG_USB_ARCH_HAS_HCD=y > >> > CONFIG_USB=y > >> > CONFIG_USB_PCI=y > >> > # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set > >> > > >> > # > >> > # Miscellaneous USB options > >> > # > >> > CONFIG_USB_DEFAULT_PERSIST=y > >> > CONFIG_USB_DYNAMIC_MINORS=y > >> > # CONFIG_USB_OTG is not set > >> > # CONFIG_USB_OTG_WHITELIST is not set > >> > # CONFIG_USB_OTG_BLACKLIST_HUB is not set > >> > CONFIG_USB_AUTOSUSPEND_DELAY=2 > >> > # CONFIG_USB_MON is not set > >> > > >> > # > >> > # USB Host Controller Drivers > >> > # > >> > # CONFIG_USB_C67X00_HCD is not set > >> > CONFIG_USB_XHCI_HCD=y > >> > # CONFIG_USB_XHCI_DBGCAP is not set > >> > CONFIG_USB_XHCI_PCI=y > >> > # CONFIG_USB_XHCI_PLATFORM is not set > >> > CONFIG_USB_EHCI_HCD=y > >> > # CONFIG_USB_EHCI_ROOT_HUB_TT is not set > >> > CONFIG_USB_EHCI_TT_NEWSCHED=y > >> > CONFIG_USB_EHCI_PCI=y > >> > # CONFIG_USB_EHCI_FSL is not set > >> > # CONFIG_USB_EHCI_HCD_PLATFORM is not set > >> > # CONFIG_USB_OXU210HP_HCD is not set > >> > # CONFIG_USB_ISP116X_HCD is not set > >> > # CONFIG_USB_FOTG210_HCD is not set > >> > CONFIG_USB_OHCI_HCD=y > >> > CONFIG_USB_OHCI_HCD_PCI=y > >> > # CONFIG_USB_OHCI_HCD_PLATFORM is not set > >> > CONFIG_USB_UHCI_HCD=y > >> > # CONFIG_USB_SL811_HCD is not set > >> > # CONFIG_USB_R8A66597_HCD is not set > >> > # CONFIG_USB_HCD_TEST_MODE is not set > >> > > >> > # > >> > # USB Device Class drivers > >> > # > >> > # CONFIG_USB_ACM is not set > >> > # CONFIG_USB_PRINTER is not set > >> > # CONFIG_USB_WDM is not set > >> > # CONFIG_USB_TMC is not set > >> > > >> > # > >> > # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may > >> > # > >> > > >> > # > >> > # also be needed; see USB_STORAGE Help for more info > >> > # > >> > CONFIG_USB_STORAGE=y > >> > # CONFIG_USB_STORAGE_DEBUG is not set > >> > # CONFIG_USB_STORAGE_REALTEK is not set > >> > # CONFIG_USB_STORAGE_DATAFAB is not set > >> > # CONFIG_USB_STORAGE_FREECOM is not set > >> > # CONFIG_USB_STORAGE_ISD200 is not set > >> > # CONFIG_USB_STORAGE_USBAT is not set > >> > # CONFIG_USB_STORAGE_SDDR09 is not set > >> > # CONFIG_USB_STORAGE_SDDR55 is not set > >> > # CONFIG_USB_STORAGE_JUMPSHOT is not set > >> > # CONFIG_USB_STORAGE_ALAUDA is not set > >> > # CONFIG_USB_STORAGE_ONETOUCH is not set > >> > # CONFIG_USB_STORAGE_KARMA is not set > >> > # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set > >> > # CONFIG_USB_STORAGE_ENE_UB6250 is not set > >> > # CONFIG_USB_UAS is not set > >> > > >> > # > >> > # USB Imaging devices > >> > # > >> > # CONFIG_USB_MDC800 is not set > >> > # CONFIG_USB_MICROTEK is not set > >> > # CONFIG_USBIP_CORE is not set > >> > # CONFIG_USB_CDNS3 is not set > >> > # CONFIG_USB_MUSB_HDRC is not set > >> > # CONFIG_USB_DWC3 is not set > >> > # CONFIG_USB_DWC2 is not set > >> > # CONFIG_USB_CHIPIDEA is not set > >> > # CONFIG_USB_ISP1760 is not set > >> > > >> > # > >> > # USB port drivers > >> > # > >> > # CONFIG_USB_SERIAL is not set > >> > > >> > # > >> > # USB Miscellaneous drivers > >> > # > >> > # CONFIG_USB_EMI62 is not set > >> > # CONFIG_USB_EMI26 is not set > >> > # CONFIG_USB_ADUTUX is not set > >> > # CONFIG_USB_SEVSEG is not set > >> > # CONFIG_USB_LEGOTOWER is not set > >> > # CONFIG_USB_LCD is not set > >> > # CONFIG_USB_CYPRESS_CY7C63 is not set > >> > # CONFIG_USB_CYTHERM is not set > >> > # CONFIG_USB_IDMOUSE is not set > >> > # CONFIG_USB_FTDI_ELAN is not set > >> > # CONFIG_USB_APPLEDISPLAY is not set > >> > # CONFIG_APPLE_MFI_FASTCHARGE is not set > >> > # CONFIG_USB_SISUSBVGA is not set > >> > # CONFIG_USB_LD is not set > >> > # CONFIG_USB_TRANCEVIBRATOR is not set > >> > # CONFIG_USB_IOWARRIOR is not set > >> > # CONFIG_USB_TEST is not set > >> > # CONFIG_USB_EHSET_TEST_FIXTURE is not set > >> > # CONFIG_USB_ISIGHTFW is not set > >> > # CONFIG_USB_YUREX is not set > >> > # CONFIG_USB_EZUSB_FX2 is not set > >> > # CONFIG_USB_HUB_USB251XB is not set > >> > # CONFIG_USB_HSIC_USB3503 is not set > >> > # CONFIG_USB_HSIC_USB4604 is not set > >> > # CONFIG_USB_LINK_LAYER_TEST is not set > >> > > >> > # > >> > # USB Physical Layer drivers > >> > # > >> > # CONFIG_NOP_USB_XCEIV is not set > >> > # CONFIG_USB_ISP1301 is not set > >> > # end of USB Physical Layer drivers > >> > > >> > CONFIG_USB_GADGET=m > >> > # CONFIG_USB_GADGET_DEBUG is not set > >> > # CONFIG_USB_GADGET_DEBUG_FILES is not set > >> > # CONFIG_USB_GADGET_DEBUG_FS is not set > >> > CONFIG_USB_GADGET_VBUS_DRAW=2 > >> > CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 > >> > > >> > # > >> > # USB Peripheral Controller > >> > # > >> > # CONFIG_USB_FOTG210_UDC is not set > >> > # CONFIG_USB_GR_UDC is not set > >> > # CONFIG_USB_R8A66597 is not set > >> > # CONFIG_USB_PXA27X is not set > >> > # CONFIG_USB_MV_UDC is not set > >> > # CONFIG_USB_MV_U3D is not set > >> > # CONFIG_USB_M66592 is not set > >> > # CONFIG_USB_BDC_UDC is not set > >> > # CONFIG_USB_AMD5536UDC is not set > >> > # CONFIG_USB_NET2272 is not set > >> > # CONFIG_USB_NET2280 is not set > >> > # CONFIG_USB_GOKU is not set > >> > # CONFIG_USB_EG20T is not set > >> > # CONFIG_USB_DUMMY_HCD is not set > >> > # end of USB Peripheral Controller > >> > > >> > CONFIG_USB_LIBCOMPOSITE=m > >> > CONFIG_USB_F_FS=m > >> > CONFIG_USB_CONFIGFS=m > >> > # CONFIG_USB_CONFIGFS_SERIAL is not set > >> > # CONFIG_USB_CONFIGFS_ACM is not set > >> > # CONFIG_USB_CONFIGFS_OBEX is not set > >> > # CONFIG_USB_CONFIGFS_NCM is not set > >> > # CONFIG_USB_CONFIGFS_ECM is not set > >> > # CONFIG_USB_CONFIGFS_ECM_SUBSET is not set > >> > # CONFIG_USB_CONFIGFS_RNDIS is not set > >> > # CONFIG_USB_CONFIGFS_EEM is not set > >> > # CONFIG_USB_CONFIGFS_MASS_STORAGE is not set > >> > # CONFIG_USB_CONFIGFS_F_LB_SS is not set > >> > CONFIG_USB_CONFIGFS_F_FS=y > >> > # CONFIG_USB_CONFIGFS_F_HID is not set > >> > # CONFIG_USB_CONFIGFS_F_PRINTER is not set > >> > > >> > # > >> > # USB Gadget precomposed configurations > >> > # > >> > # CONFIG_USB_ZERO is not set > >> > # CONFIG_USB_ETH is not set > >> > # CONFIG_USB_G_NCM is not set > >> > # CONFIG_USB_GADGETFS is not set > >> > # CONFIG_USB_FUNCTIONFS is not set > >> > # CONFIG_USB_MASS_STORAGE is not set > >> > # CONFIG_USB_G_SERIAL is not set > >> > # CONFIG_USB_G_PRINTER is not set > >> > # CONFIG_USB_CDC_COMPOSITE is not set > >> > # CONFIG_USB_G_ACM_MS is not set > >> > # CONFIG_USB_G_MULTI is not set > >> > # CONFIG_USB_G_HID is not set > >> > # CONFIG_USB_G_DBGP is not set > >> > # CONFIG_USB_RAW_GADGET is not set > >> > # end of USB Gadget precomposed configurations > >> > > >> > # CONFIG_TYPEC is not set > >> > # CONFIG_USB_ROLE_SWITCH is not set > >> > # CONFIG_MMC is not set > >> > # CONFIG_MEMSTICK is not set > >> > # CONFIG_NEW_LEDS is not set > >> > # CONFIG_ACCESSIBILITY is not set > >> > # CONFIG_INFINIBAND is not set > >> > CONFIG_EDAC_ATOMIC_SCRUB=y > >> > CONFIG_EDAC_SUPPORT=y > >> > # CONFIG_EDAC is not set > >> > CONFIG_RTC_LIB=y > >> > CONFIG_RTC_MC146818_LIB=y > >> > CONFIG_RTC_CLASS=y > >> > CONFIG_RTC_HCTOSYS=y > >> > CONFIG_RTC_HCTOSYS_DEVICE="rtc0" > >> > CONFIG_RTC_SYSTOHC=y > >> > CONFIG_RTC_SYSTOHC_DEVICE="rtc0" > >> > # CONFIG_RTC_DEBUG is not set > >> > CONFIG_RTC_NVMEM=y > >> > > >> > # > >> > # RTC interfaces > >> > # > >> > CONFIG_RTC_INTF_SYSFS=y > >> > CONFIG_RTC_INTF_PROC=y > >> > CONFIG_RTC_INTF_DEV=y > >> > # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set > >> > # CONFIG_RTC_DRV_TEST is not set > >> > > >> > # > >> > # I2C RTC drivers > >> > # > >> > # CONFIG_RTC_DRV_ABB5ZES3 is not set > >> > # CONFIG_RTC_DRV_ABEOZ9 is not set > >> > # CONFIG_RTC_DRV_ABX80X is not set > >> > # CONFIG_RTC_DRV_DS1307 is not set > >> > # CONFIG_RTC_DRV_DS1374 is not set > >> > # CONFIG_RTC_DRV_DS1672 is not set > >> > # CONFIG_RTC_DRV_MAX6900 is not set > >> > # CONFIG_RTC_DRV_RS5C372 is not set > >> > # CONFIG_RTC_DRV_ISL1208 is not set > >> > # CONFIG_RTC_DRV_ISL12022 is not set > >> > # CONFIG_RTC_DRV_X1205 is not set > >> > # CONFIG_RTC_DRV_PCF8523 is not set > >> > # CONFIG_RTC_DRV_PCF85063 is not set > >> > # CONFIG_RTC_DRV_PCF85363 is not set > >> > # CONFIG_RTC_DRV_PCF8563 is not set > >> > # CONFIG_RTC_DRV_PCF8583 is not set > >> > # CONFIG_RTC_DRV_M41T80 is not set > >> > # CONFIG_RTC_DRV_BQ32K is not set > >> > # CONFIG_RTC_DRV_S35390A is not set > >> > # CONFIG_RTC_DRV_FM3130 is not set > >> > # CONFIG_RTC_DRV_RX8010 is not set > >> > # CONFIG_RTC_DRV_RX8581 is not set > >> > # CONFIG_RTC_DRV_RX8025 is not set > >> > # CONFIG_RTC_DRV_EM3027 is not set > >> > # CONFIG_RTC_DRV_RV3028 is not set > >> > # CONFIG_RTC_DRV_RV8803 is not set > >> > # CONFIG_RTC_DRV_SD3078 is not set > >> > > >> > # > >> > # SPI RTC drivers > >> > # > >> > CONFIG_RTC_I2C_AND_SPI=y > >> > > >> > # > >> > # SPI and I2C RTC drivers > >> > # > >> > # CONFIG_RTC_DRV_DS3232 is not set > >> > # CONFIG_RTC_DRV_PCF2127 is not set > >> > # CONFIG_RTC_DRV_RV3029C2 is not set > >> > > >> > # > >> > # Platform RTC drivers > >> > # > >> > CONFIG_RTC_DRV_CMOS=y > >> > # CONFIG_RTC_DRV_DS1286 is not set > >> > # CONFIG_RTC_DRV_DS1511 is not set > >> > # CONFIG_RTC_DRV_DS1553 is not set > >> > # CONFIG_RTC_DRV_DS1685_FAMILY is not set > >> > # CONFIG_RTC_DRV_DS1742 is not set > >> > # CONFIG_RTC_DRV_DS2404 is not set > >> > # CONFIG_RTC_DRV_STK17TA8 is not set > >> > # CONFIG_RTC_DRV_M48T86 is not set > >> > # CONFIG_RTC_DRV_M48T35 is not set > >> > # CONFIG_RTC_DRV_M48T59 is not set > >> > # CONFIG_RTC_DRV_MSM6242 is not set > >> > # CONFIG_RTC_DRV_BQ4802 is not set > >> > # CONFIG_RTC_DRV_RP5C01 is not set > >> > # CONFIG_RTC_DRV_V3020 is not set > >> > > >> > # > >> > # on-CPU RTC drivers > >> > # > >> > # CONFIG_RTC_DRV_FTRTC010 is not set > >> > > >> > # > >> > # HID Sensor RTC drivers > >> > # > >> > # CONFIG_DMADEVICES is not set > >> > > >> > # > >> > # DMABUF options > >> > # > >> > CONFIG_SYNC_FILE=y > >> > # CONFIG_SW_SYNC is not set > >> > # CONFIG_UDMABUF is not set > >> > # CONFIG_DMABUF_MOVE_NOTIFY is not set > >> > # CONFIG_DMABUF_SELFTESTS is not set > >> > # CONFIG_DMABUF_HEAPS is not set > >> > # end of DMABUF options > >> > > >> > # CONFIG_AUXDISPLAY is not set > >> > # CONFIG_UIO is not set > >> > # CONFIG_VFIO is not set > >> > # CONFIG_VIRT_DRIVERS is not set > >> > # CONFIG_VIRTIO_MENU is not set > >> > # CONFIG_VDPA_MENU is not set > >> > CONFIG_VHOST_MENU=y > >> > # CONFIG_VHOST_NET is not set > >> > # CONFIG_VHOST_VDPA is not set > >> > # CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set > >> > > >> > # > >> > # Microsoft Hyper-V guest support > >> > # > >> > # end of Microsoft Hyper-V guest support > >> > > >> > # CONFIG_GREYBUS is not set > >> > # CONFIG_STAGING is not set > >> > CONFIG_X86_PLATFORM_DEVICES=y > >> > CONFIG_ACPI_WMI=y > >> > CONFIG_WMI_BMOF=y > >> > # CONFIG_INTEL_WMI_THUNDERBOLT is not set > >> > CONFIG_MXM_WMI=y > >> > # CONFIG_PEAQ_WMI is not set > >> > # CONFIG_XIAOMI_WMI is not set > >> > # CONFIG_ACERHDF is not set > >> > # CONFIG_ACER_WIRELESS is not set > >> > # CONFIG_ACER_WMI is not set > >> > # CONFIG_APPLE_GMUX is not set > >> > # CONFIG_ASUS_LAPTOP is not set > >> > # CONFIG_ASUS_WIRELESS is not set > >> > # CONFIG_DCDBAS is not set > >> > # CONFIG_DELL_SMBIOS is not set > >> > # CONFIG_DELL_RBU is not set > >> > # CONFIG_DELL_SMO8800 is not set > >> > # CONFIG_DELL_WMI_AIO is not set > >> > # CONFIG_FUJITSU_LAPTOP is not set > >> > # CONFIG_FUJITSU_TABLET is not set > >> > # CONFIG_GPD_POCKET_FAN is not set > >> > # CONFIG_HP_ACCEL is not set > >> > # CONFIG_HP_WIRELESS is not set > >> > # CONFIG_HP_WMI is not set > >> > # CONFIG_IBM_RTL is not set > >> > # CONFIG_SENSORS_HDAPS is not set > >> > # CONFIG_INTEL_ATOMISP2_PM is not set > >> > # CONFIG_INTEL_HID_EVENT is not set > >> > # CONFIG_INTEL_MENLOW is not set > >> > # CONFIG_INTEL_VBTN is not set > >> > # CONFIG_SURFACE_3_POWER_OPREGION is not set > >> > # CONFIG_SURFACE_PRO3_BUTTON is not set > >> > # CONFIG_MSI_WMI is not set > >> > # CONFIG_SAMSUNG_LAPTOP is not set > >> > # CONFIG_SAMSUNG_Q10 is not set > >> > # CONFIG_TOSHIBA_BT_RFKILL is not set > >> > # CONFIG_TOSHIBA_HAPS is not set > >> > # CONFIG_TOSHIBA_WMI is not set > >> > # CONFIG_ACPI_CMPC is not set > >> > # CONFIG_LG_LAPTOP is not set > >> > # CONFIG_PANASONIC_LAPTOP is not set > >> > # CONFIG_SYSTEM76_ACPI is not set > >> > # CONFIG_TOPSTAR_LAPTOP is not set > >> > # CONFIG_I2C_MULTI_INSTANTIATE is not set > >> > # CONFIG_INTEL_IPS is not set > >> > # CONFIG_INTEL_RST is not set > >> > # CONFIG_INTEL_SMARTCONNECT is not set > >> > > >> > # > >> > # Intel Speed Select Technology interface support > >> > # > >> > CONFIG_INTEL_SPEED_SELECT_INTERFACE=y > >> > # end of Intel Speed Select Technology interface support > >> > > >> > # CONFIG_INTEL_TURBO_MAX_3 is not set > >> > # CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set > >> > # CONFIG_INTEL_PMC_CORE is not set > >> > # CONFIG_INTEL_PMC_IPC is not set > >> > # CONFIG_INTEL_PUNIT_IPC is not set > >> > CONFIG_PMC_ATOM=y > >> > # CONFIG_MFD_CROS_EC is not set > >> > # CONFIG_CHROME_PLATFORMS is not set > >> > # CONFIG_MELLANOX_PLATFORM is not set > >> > CONFIG_CLKDEV_LOOKUP=y > >> > CONFIG_HAVE_CLK_PREPARE=y > >> > CONFIG_COMMON_CLK=y > >> > > >> > # > >> > # Common Clock Framework > >> > # > >> > # CONFIG_COMMON_CLK_MAX9485 is not set > >> > # CONFIG_COMMON_CLK_SI5341 is not set > >> > # CONFIG_COMMON_CLK_SI5351 is not set > >> > # CONFIG_COMMON_CLK_SI544 is not set > >> > # CONFIG_COMMON_CLK_CDCE706 is not set > >> > # CONFIG_COMMON_CLK_CS2000_CP is not set > >> > # end of Common Clock Framework > >> > > >> > # CONFIG_HWSPINLOCK is not set > >> > > >> > # > >> > # Clock Source drivers > >> > # > >> > CONFIG_CLKEVT_I8253=y > >> > CONFIG_I8253_LOCK=y > >> > CONFIG_CLKBLD_I8253=y > >> > # end of Clock Source drivers > >> > > >> > CONFIG_MAILBOX=y > >> > CONFIG_PCC=y > >> > # CONFIG_ALTERA_MBOX is not set > >> > CONFIG_IOMMU_IOVA=y > >> > CONFIG_IOASID=y > >> > CONFIG_IOMMU_API=y > >> > CONFIG_IOMMU_SUPPORT=y > >> > > >> > # > >> > # Generic IOMMU Pagetable Support > >> > # > >> > # end of Generic IOMMU Pagetable Support > >> > > >> > # CONFIG_IOMMU_DEBUGFS is not set > >> > # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set > >> > # CONFIG_AMD_IOMMU is not set > >> > CONFIG_DMAR_TABLE=y > >> > CONFIG_INTEL_IOMMU=y > >> > CONFIG_INTEL_IOMMU_SVM=y > >> > CONFIG_INTEL_IOMMU_DEFAULT_ON=y > >> > CONFIG_INTEL_IOMMU_FLOPPY_WA=y > >> > # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set > >> > # CONFIG_IRQ_REMAP is not set > >> > > >> > # > >> > # Remoteproc drivers > >> > # > >> > # CONFIG_REMOTEPROC is not set > >> > # end of Remoteproc drivers > >> > > >> > # > >> > # Rpmsg drivers > >> > # > >> > # CONFIG_RPMSG_QCOM_GLINK_RPM is not set > >> > # CONFIG_RPMSG_VIRTIO is not set > >> > # end of Rpmsg drivers > >> > > >> > # CONFIG_SOUNDWIRE is not set > >> > > >> > # > >> > # SOC (System On Chip) specific Drivers > >> > # > >> > > >> > # > >> > # Amlogic SoC drivers > >> > # > >> > # end of Amlogic SoC drivers > >> > > >> > # > >> > # Aspeed SoC drivers > >> > # > >> > # end of Aspeed SoC drivers > >> > > >> > # > >> > # Broadcom SoC drivers > >> > # > >> > # end of Broadcom SoC drivers > >> > > >> > # > >> > # NXP/Freescale QorIQ SoC drivers > >> > # > >> > # end of NXP/Freescale QorIQ SoC drivers > >> > > >> > # > >> > # i.MX SoC drivers > >> > # > >> > # end of i.MX SoC drivers > >> > > >> > # > >> > # Qualcomm SoC drivers > >> > # > >> > # end of Qualcomm SoC drivers > >> > > >> > # CONFIG_SOC_TI is not set > >> > > >> > # > >> > # Xilinx SoC drivers > >> > # > >> > # CONFIG_XILINX_VCU is not set > >> > # end of Xilinx SoC drivers > >> > # end of SOC (System On Chip) specific Drivers > >> > > >> > # CONFIG_PM_DEVFREQ is not set > >> > # CONFIG_EXTCON is not set > >> > # CONFIG_MEMORY is not set > >> > # CONFIG_IIO is not set > >> > # CONFIG_NTB is not set > >> > # CONFIG_VME_BUS is not set > >> > # CONFIG_PWM is not set > >> > > >> > # > >> > # IRQ chip support > >> > # > >> > # end of IRQ chip support > >> > > >> > # CONFIG_IPACK_BUS is not set > >> > # CONFIG_RESET_CONTROLLER is not set > >> > > >> > # > >> > # PHY Subsystem > >> > # > >> > # CONFIG_GENERIC_PHY is not set > >> > # CONFIG_BCM_KONA_USB2_PHY is not set > >> > # CONFIG_PHY_PXA_28NM_HSIC is not set > >> > # CONFIG_PHY_PXA_28NM_USB2 is not set > >> > # CONFIG_PHY_INTEL_EMMC is not set > >> > # end of PHY Subsystem > >> > > >> > # CONFIG_POWERCAP is not set > >> > # CONFIG_MCB is not set > >> > > >> > # > >> > # Performance monitor support > >> > # > >> > # end of Performance monitor support > >> > > >> > CONFIG_RAS=y > >> > # CONFIG_USB4 is not set > >> > > >> > # > >> > # Android > >> > # > >> > # CONFIG_ANDROID is not set > >> > # end of Android > >> > > >> > # CONFIG_LIBNVDIMM is not set > >> > # CONFIG_DAX is not set > >> > CONFIG_NVMEM=y > >> > # CONFIG_NVMEM_SYSFS is not set > >> > > >> > # > >> > # HW tracing support > >> > # > >> > # CONFIG_STM is not set > >> > # CONFIG_INTEL_TH is not set > >> > # end of HW tracing support > >> > > >> > # CONFIG_FPGA is not set > >> > # CONFIG_TEE is not set > >> > # CONFIG_UNISYS_VISORBUS is not set > >> > # CONFIG_SIOX is not set > >> > # CONFIG_SLIMBUS is not set > >> > # CONFIG_INTERCONNECT is not set > >> > # CONFIG_COUNTER is not set > >> > # CONFIG_MOST is not set > >> > # end of Device Drivers > >> > > >> > # > >> > # File systems > >> > # > >> > CONFIG_DCACHE_WORD_ACCESS=y > >> > CONFIG_VALIDATE_FS_PARSER=y > >> > CONFIG_FS_IOMAP=y > >> > # CONFIG_EXT2_FS is not set > >> > # CONFIG_EXT3_FS is not set > >> > CONFIG_EXT4_FS=y > >> > CONFIG_EXT4_USE_FOR_EXT2=y > >> > CONFIG_EXT4_FS_POSIX_ACL=y > >> > CONFIG_EXT4_FS_SECURITY=y > >> > # CONFIG_EXT4_DEBUG is not set > >> > CONFIG_JBD2=y > >> > # CONFIG_JBD2_DEBUG is not set > >> > CONFIG_FS_MBCACHE=y > >> > # CONFIG_REISERFS_FS is not set > >> > # CONFIG_JFS_FS is not set > >> > CONFIG_XFS_FS=y > >> > CONFIG_XFS_QUOTA=y > >> > CONFIG_XFS_POSIX_ACL=y > >> > # CONFIG_XFS_RT is not set > >> > # CONFIG_XFS_ONLINE_SCRUB is not set > >> > # CONFIG_XFS_WARN is not set > >> > # CONFIG_XFS_DEBUG is not set > >> > # CONFIG_GFS2_FS is not set > >> > # CONFIG_OCFS2_FS is not set > >> > CONFIG_BTRFS_FS=y > >> > CONFIG_BTRFS_FS_POSIX_ACL=y > >> > CONFIG_BTRFS_FS_CHECK_INTEGRITY=y > >> > # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set > >> > CONFIG_BTRFS_DEBUG=y > >> > # CONFIG_BTRFS_ASSERT is not set > >> > CONFIG_BTRFS_FS_REF_VERIFY=y > >> > CONFIG_NILFS2_FS=m > >> > CONFIG_F2FS_FS=m > >> > CONFIG_F2FS_STAT_FS=y > >> > CONFIG_F2FS_FS_XATTR=y > >> > CONFIG_F2FS_FS_POSIX_ACL=y > >> > CONFIG_F2FS_FS_SECURITY=y > >> > # CONFIG_F2FS_CHECK_FS is not set > >> > # CONFIG_F2FS_IO_TRACE is not set > >> > # CONFIG_F2FS_FAULT_INJECTION is not set > >> > # CONFIG_F2FS_FS_COMPRESSION is not set > >> > # CONFIG_FS_DAX is not set > >> > CONFIG_FS_POSIX_ACL=y > >> > CONFIG_EXPORTFS=y > >> > CONFIG_EXPORTFS_BLOCK_OPS=y > >> > CONFIG_FILE_LOCKING=y > >> > CONFIG_MANDATORY_FILE_LOCKING=y > >> > # CONFIG_FS_ENCRYPTION is not set > >> > # CONFIG_FS_VERITY is not set > >> > CONFIG_FSNOTIFY=y > >> > CONFIG_DNOTIFY=y > >> > CONFIG_INOTIFY_USER=y > >> > CONFIG_FANOTIFY=y > >> > CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y > >> > # CONFIG_QUOTA is not set > >> > # CONFIG_QUOTA_NETLINK_INTERFACE is not set > >> > CONFIG_QUOTACTL=y > >> > CONFIG_QUOTACTL_COMPAT=y > >> > CONFIG_AUTOFS4_FS=y > >> > CONFIG_AUTOFS_FS=y > >> > CONFIG_FUSE_FS=m > >> > # CONFIG_CUSE is not set > >> > # CONFIG_VIRTIO_FS is not set > >> > # CONFIG_OVERLAY_FS is not set > >> > > >> > # > >> > # Caches > >> > # > >> > CONFIG_FSCACHE=y > >> > CONFIG_FSCACHE_STATS=y > >> > # CONFIG_FSCACHE_HISTOGRAM is not set > >> > # CONFIG_FSCACHE_DEBUG is not set > >> > CONFIG_FSCACHE_OBJECT_LIST=y > >> > CONFIG_CACHEFILES=y > >> > # CONFIG_CACHEFILES_DEBUG is not set > >> > # CONFIG_CACHEFILES_HISTOGRAM is not set > >> > # end of Caches > >> > > >> > # > >> > # CD-ROM/DVD Filesystems > >> > # > >> > # CONFIG_ISO9660_FS is not set > >> > # CONFIG_UDF_FS is not set > >> > # end of CD-ROM/DVD Filesystems > >> > > >> > # > >> > # DOS/FAT/EXFAT/NT Filesystems > >> > # > >> > # CONFIG_MSDOS_FS is not set > >> > # CONFIG_VFAT_FS is not set > >> > # CONFIG_EXFAT_FS is not set > >> > # CONFIG_NTFS_FS is not set > >> > # end of DOS/FAT/EXFAT/NT Filesystems > >> > > >> > # > >> > # Pseudo filesystems > >> > # > >> > CONFIG_PROC_FS=y > >> > CONFIG_PROC_KCORE=y > >> > CONFIG_PROC_SYSCTL=y > >> > CONFIG_PROC_PAGE_MONITOR=y > >> > # CONFIG_PROC_CHILDREN is not set > >> > CONFIG_PROC_PID_ARCH_STATUS=y > >> > CONFIG_PROC_CPU_RESCTRL=y > >> > CONFIG_KERNFS=y > >> > CONFIG_SYSFS=y > >> > CONFIG_TMPFS=y > >> > CONFIG_TMPFS_POSIX_ACL=y > >> > CONFIG_TMPFS_XATTR=y > >> > CONFIG_HUGETLBFS=y > >> > CONFIG_HUGETLB_PAGE=y > >> > CONFIG_MEMFD_CREATE=y > >> > CONFIG_ARCH_HAS_GIGANTIC_PAGE=y > >> > CONFIG_CONFIGFS_FS=y > >> > CONFIG_EFIVAR_FS=y > >> > # end of Pseudo filesystems > >> > > >> > CONFIG_MISC_FILESYSTEMS=y > >> > # CONFIG_ORANGEFS_FS is not set > >> > # CONFIG_ADFS_FS is not set > >> > # CONFIG_AFFS_FS is not set > >> > # CONFIG_ECRYPT_FS is not set > >> > # CONFIG_HFS_FS is not set > >> > # CONFIG_HFSPLUS_FS is not set > >> > # CONFIG_BEFS_FS is not set > >> > # CONFIG_BFS_FS is not set > >> > # CONFIG_EFS_FS is not set > >> > # CONFIG_CRAMFS is not set > >> > # CONFIG_SQUASHFS is not set > >> > # CONFIG_VXFS_FS is not set > >> > # CONFIG_MINIX_FS is not set > >> > # CONFIG_OMFS_FS is not set > >> > # CONFIG_HPFS_FS is not set > >> > # CONFIG_QNX4FS_FS is not set > >> > # CONFIG_QNX6FS_FS is not set > >> > # CONFIG_ROMFS_FS is not set > >> > CONFIG_PSTORE=y > >> > CONFIG_PSTORE_DEFLATE_COMPRESS=y > >> > # CONFIG_PSTORE_LZO_COMPRESS is not set > >> > # CONFIG_PSTORE_LZ4_COMPRESS is not set > >> > # CONFIG_PSTORE_LZ4HC_COMPRESS is not set > >> > # CONFIG_PSTORE_842_COMPRESS is not set > >> > # CONFIG_PSTORE_ZSTD_COMPRESS is not set > >> > CONFIG_PSTORE_COMPRESS=y > >> > CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y > >> > CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" > >> > # CONFIG_PSTORE_CONSOLE is not set > >> > # CONFIG_PSTORE_PMSG is not set > >> > # CONFIG_PSTORE_FTRACE is not set > >> > # CONFIG_PSTORE_RAM is not set > >> > # CONFIG_SYSV_FS is not set > >> > # CONFIG_UFS_FS is not set > >> > # CONFIG_EROFS_FS is not set > >> > CONFIG_NETWORK_FILESYSTEMS=y > >> > CONFIG_NFS_FS=y > >> > # CONFIG_NFS_V2 is not set > >> > # CONFIG_NFS_V3 is not set > >> > CONFIG_NFS_V4=y > >> > # CONFIG_NFS_SWAP is not set > >> > # CONFIG_NFS_V4_1 is not set > >> > # CONFIG_NFS_FSCACHE is not set > >> > # CONFIG_NFS_USE_LEGACY_DNS is not set > >> > CONFIG_NFS_USE_KERNEL_DNS=y > >> > CONFIG_NFS_DEBUG=y > >> > CONFIG_NFS_DISABLE_UDP_SUPPORT=y > >> > # CONFIG_NFSD is not set > >> > CONFIG_GRACE_PERIOD=y > >> > CONFIG_LOCKD=y > >> > CONFIG_NFS_COMMON=y > >> > CONFIG_SUNRPC=y > >> > CONFIG_SUNRPC_GSS=y > >> > CONFIG_SUNRPC_DEBUG=y > >> > # CONFIG_CEPH_FS is not set > >> > # CONFIG_CIFS is not set > >> > # CONFIG_CODA_FS is not set > >> > CONFIG_AFS_FS=y > >> > CONFIG_AFS_DEBUG=y > >> > CONFIG_AFS_FSCACHE=y > >> > CONFIG_AFS_DEBUG_CURSOR=y > >> > CONFIG_NLS=y > >> > CONFIG_NLS_DEFAULT="iso8859-1" > >> > # CONFIG_NLS_CODEPAGE_437 is not set > >> > # CONFIG_NLS_CODEPAGE_737 is not set > >> > # CONFIG_NLS_CODEPAGE_775 is not set > >> > # CONFIG_NLS_CODEPAGE_850 is not set > >> > # CONFIG_NLS_CODEPAGE_852 is not set > >> > # CONFIG_NLS_CODEPAGE_855 is not set > >> > # CONFIG_NLS_CODEPAGE_857 is not set > >> > # CONFIG_NLS_CODEPAGE_860 is not set > >> > # CONFIG_NLS_CODEPAGE_861 is not set > >> > # CONFIG_NLS_CODEPAGE_862 is not set > >> > # CONFIG_NLS_CODEPAGE_863 is not set > >> > # CONFIG_NLS_CODEPAGE_864 is not set > >> > # CONFIG_NLS_CODEPAGE_865 is not set > >> > # CONFIG_NLS_CODEPAGE_866 is not set > >> > # CONFIG_NLS_CODEPAGE_869 is not set > >> > # CONFIG_NLS_CODEPAGE_936 is not set > >> > # CONFIG_NLS_CODEPAGE_950 is not set > >> > # CONFIG_NLS_CODEPAGE_932 is not set > >> > # CONFIG_NLS_CODEPAGE_949 is not set > >> > # CONFIG_NLS_CODEPAGE_874 is not set > >> > # CONFIG_NLS_ISO8859_8 is not set > >> > # CONFIG_NLS_CODEPAGE_1250 is not set > >> > # CONFIG_NLS_CODEPAGE_1251 is not set > >> > # CONFIG_NLS_ASCII is not set > >> > # CONFIG_NLS_ISO8859_1 is not set > >> > # CONFIG_NLS_ISO8859_2 is not set > >> > # CONFIG_NLS_ISO8859_3 is not set > >> > # CONFIG_NLS_ISO8859_4 is not set > >> > # CONFIG_NLS_ISO8859_5 is not set > >> > # CONFIG_NLS_ISO8859_6 is not set > >> > # CONFIG_NLS_ISO8859_7 is not set > >> > # CONFIG_NLS_ISO8859_9 is not set > >> > # CONFIG_NLS_ISO8859_13 is not set > >> > # CONFIG_NLS_ISO8859_14 is not set > >> > # CONFIG_NLS_ISO8859_15 is not set > >> > # CONFIG_NLS_KOI8_R is not set > >> > # CONFIG_NLS_KOI8_U is not set > >> > # CONFIG_NLS_MAC_ROMAN is not set > >> > # CONFIG_NLS_MAC_CELTIC is not set > >> > # CONFIG_NLS_MAC_CENTEURO is not set > >> > # CONFIG_NLS_MAC_CROATIAN is not set > >> > # CONFIG_NLS_MAC_CYRILLIC is not set > >> > # CONFIG_NLS_MAC_GAELIC is not set > >> > # CONFIG_NLS_MAC_GREEK is not set > >> > # CONFIG_NLS_MAC_ICELAND is not set > >> > # CONFIG_NLS_MAC_INUIT is not set > >> > # CONFIG_NLS_MAC_ROMANIAN is not set > >> > # CONFIG_NLS_MAC_TURKISH is not set > >> > # CONFIG_NLS_UTF8 is not set > >> > CONFIG_DLM=y > >> > # CONFIG_DLM_DEBUG is not set > >> > # CONFIG_UNICODE is not set > >> > # end of File systems > >> > > >> > # > >> > # Security options > >> > # > >> > CONFIG_KEYS=y > >> > CONFIG_KEYS_REQUEST_CACHE=y > >> > CONFIG_PERSISTENT_KEYRINGS=y > >> > CONFIG_BIG_KEYS=y > >> > CONFIG_TRUSTED_KEYS=y > >> > CONFIG_ENCRYPTED_KEYS=y > >> > CONFIG_KEY_DH_OPERATIONS=y > >> > # CONFIG_SECURITY_DMESG_RESTRICT is not set > >> > CONFIG_SECURITY=y > >> > CONFIG_SECURITY_WRITABLE_HOOKS=y > >> > CONFIG_SECURITYFS=y > >> > CONFIG_SECURITY_NETWORK=y > >> > CONFIG_PAGE_TABLE_ISOLATION=y > >> > CONFIG_SECURITY_NETWORK_XFRM=y > >> > CONFIG_SECURITY_PATH=y > >> > # CONFIG_INTEL_TXT is not set > >> > CONFIG_LSM_MMAP_MIN_ADDR=65536 > >> > CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y > >> > # CONFIG_HARDENED_USERCOPY is not set > >> > # CONFIG_FORTIFY_SOURCE is not set > >> > # CONFIG_STATIC_USERMODEHELPER is not set > >> > CONFIG_SECURITY_SELINUX=y > >> > CONFIG_SECURITY_SELINUX_BOOTPARAM=y > >> > CONFIG_SECURITY_SELINUX_DISABLE=y > >> > CONFIG_SECURITY_SELINUX_DEVELOP=y > >> > CONFIG_SECURITY_SELINUX_AVC_STATS=y > >> > CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 > >> > CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 > >> > CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 > >> > # CONFIG_SECURITY_SMACK is not set > >> > # CONFIG_SECURITY_TOMOYO is not set > >> > # CONFIG_SECURITY_APPARMOR is not set > >> > # CONFIG_SECURITY_LOADPIN is not set > >> > CONFIG_SECURITY_YAMA=y > >> > # CONFIG_SECURITY_SAFESETID is not set > >> > # CONFIG_SECURITY_LOCKDOWN_LSM is not set > >> > # CONFIG_INTEGRITY is not set > >> > # CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set > >> > CONFIG_DEFAULT_SECURITY_SELINUX=y > >> > # CONFIG_DEFAULT_SECURITY_DAC is not set > >> > CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" > >> > > >> > # > >> > # Kernel hardening options > >> > # > >> > > >> > # > >> > # Memory initialization > >> > # > >> > CONFIG_INIT_STACK_NONE=y > >> > # CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set > >> > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set > >> > # CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set > >> > # CONFIG_GCC_PLUGIN_STACKLEAK is not set > >> > # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set > >> > # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set > >> > # end of Memory initialization > >> > # end of Kernel hardening options > >> > # end of Security options > >> > > >> > CONFIG_XOR_BLOCKS=y > >> > CONFIG_CRYPTO=y > >> > > >> > # > >> > # Crypto core or helper > >> > # > >> > # CONFIG_CRYPTO_FIPS is not set > >> > CONFIG_CRYPTO_ALGAPI=y > >> > CONFIG_CRYPTO_ALGAPI2=y > >> > CONFIG_CRYPTO_AEAD=y > >> > CONFIG_CRYPTO_AEAD2=y > >> > CONFIG_CRYPTO_SKCIPHER=y > >> > CONFIG_CRYPTO_SKCIPHER2=y > >> > CONFIG_CRYPTO_HASH=y > >> > CONFIG_CRYPTO_HASH2=y > >> > CONFIG_CRYPTO_RNG=y > >> > CONFIG_CRYPTO_RNG2=y > >> > CONFIG_CRYPTO_RNG_DEFAULT=y > >> > CONFIG_CRYPTO_AKCIPHER2=y > >> > CONFIG_CRYPTO_AKCIPHER=y > >> > CONFIG_CRYPTO_KPP2=y > >> > CONFIG_CRYPTO_KPP=y > >> > CONFIG_CRYPTO_ACOMP2=y > >> > CONFIG_CRYPTO_MANAGER=y > >> > CONFIG_CRYPTO_MANAGER2=y > >> > # CONFIG_CRYPTO_USER is not set > >> > # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set > >> > # CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set > >> > CONFIG_CRYPTO_GF128MUL=y > >> > CONFIG_CRYPTO_NULL=y > >> > CONFIG_CRYPTO_NULL2=y > >> > # CONFIG_CRYPTO_PCRYPT is not set > >> > # CONFIG_CRYPTO_CRYPTD is not set > >> > CONFIG_CRYPTO_AUTHENC=y > >> > # CONFIG_CRYPTO_TEST is not set > >> > > >> > # > >> > # Public-key cryptography > >> > # > >> > CONFIG_CRYPTO_RSA=y > >> > CONFIG_CRYPTO_DH=y > >> > # CONFIG_CRYPTO_ECDH is not set > >> > # CONFIG_CRYPTO_ECRDSA is not set > >> > # CONFIG_CRYPTO_CURVE25519 is not set > >> > # CONFIG_CRYPTO_CURVE25519_X86 is not set > >> > > >> > # > >> > # Authenticated Encryption with Associated Data > >> > # > >> > CONFIG_CRYPTO_CCM=m > >> > CONFIG_CRYPTO_GCM=y > >> > # CONFIG_CRYPTO_CHACHA20POLY1305 is not set > >> > # CONFIG_CRYPTO_AEGIS128 is not set > >> > # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set > >> > CONFIG_CRYPTO_SEQIV=y > >> > CONFIG_CRYPTO_ECHAINIV=y > >> > > >> > # > >> > # Block modes > >> > # > >> > CONFIG_CRYPTO_CBC=y > >> > # CONFIG_CRYPTO_CFB is not set > >> > CONFIG_CRYPTO_CTR=y > >> > # CONFIG_CRYPTO_CTS is not set > >> > CONFIG_CRYPTO_ECB=y > >> > # CONFIG_CRYPTO_LRW is not set > >> > # CONFIG_CRYPTO_OFB is not set > >> > CONFIG_CRYPTO_PCBC=y > >> > # CONFIG_CRYPTO_XTS is not set > >> > # CONFIG_CRYPTO_KEYWRAP is not set > >> > # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set > >> > # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set > >> > # CONFIG_CRYPTO_ADIANTUM is not set > >> > # CONFIG_CRYPTO_ESSIV is not set > >> > > >> > # > >> > # Hash modes > >> > # > >> > CONFIG_CRYPTO_CMAC=m > >> > CONFIG_CRYPTO_HMAC=y > >> > # CONFIG_CRYPTO_XCBC is not set > >> > # CONFIG_CRYPTO_VMAC is not set > >> > > >> > # > >> > # Digest > >> > # > >> > CONFIG_CRYPTO_CRC32C=y > >> > # CONFIG_CRYPTO_CRC32C_INTEL is not set > >> > CONFIG_CRYPTO_CRC32=m > >> > # CONFIG_CRYPTO_CRC32_PCLMUL is not set > >> > CONFIG_CRYPTO_XXHASH=y > >> > CONFIG_CRYPTO_BLAKE2B=y > >> > # CONFIG_CRYPTO_BLAKE2S is not set > >> > # CONFIG_CRYPTO_BLAKE2S_X86 is not set > >> > CONFIG_CRYPTO_CRCT10DIF=y > >> > # CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set > >> > CONFIG_CRYPTO_GHASH=y > >> > # CONFIG_CRYPTO_POLY1305 is not set > >> > # CONFIG_CRYPTO_POLY1305_X86_64 is not set > >> > CONFIG_CRYPTO_MD4=m > >> > CONFIG_CRYPTO_MD5=y > >> > # CONFIG_CRYPTO_MICHAEL_MIC is not set > >> > # CONFIG_CRYPTO_RMD128 is not set > >> > # CONFIG_CRYPTO_RMD160 is not set > >> > # CONFIG_CRYPTO_RMD256 is not set > >> > # CONFIG_CRYPTO_RMD320 is not set > >> > CONFIG_CRYPTO_SHA1=y > >> > # CONFIG_CRYPTO_SHA1_SSSE3 is not set > >> > # CONFIG_CRYPTO_SHA256_SSSE3 is not set > >> > # CONFIG_CRYPTO_SHA512_SSSE3 is not set > >> > CONFIG_CRYPTO_SHA256=y > >> > CONFIG_CRYPTO_SHA512=m > >> > # CONFIG_CRYPTO_SHA3 is not set > >> > # CONFIG_CRYPTO_SM3 is not set > >> > # CONFIG_CRYPTO_STREEBOG is not set > >> > # CONFIG_CRYPTO_TGR192 is not set > >> > # CONFIG_CRYPTO_WP512 is not set > >> > # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set > >> > > >> > # > >> > # Ciphers > >> > # > >> > CONFIG_CRYPTO_AES=y > >> > # CONFIG_CRYPTO_AES_TI is not set > >> > # CONFIG_CRYPTO_AES_NI_INTEL is not set > >> > # CONFIG_CRYPTO_ANUBIS is not set > >> > CONFIG_CRYPTO_ARC4=m > >> > # CONFIG_CRYPTO_BLOWFISH is not set > >> > # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set > >> > # CONFIG_CRYPTO_CAMELLIA is not set > >> > # CONFIG_CRYPTO_CAMELLIA_X86_64 is not set > >> > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set > >> > # CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set > >> > # CONFIG_CRYPTO_CAST5 is not set > >> > # CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set > >> > # CONFIG_CRYPTO_CAST6 is not set > >> > # CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set > >> > CONFIG_CRYPTO_DES=y > >> > # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set > >> > CONFIG_CRYPTO_FCRYPT=y > >> > # CONFIG_CRYPTO_KHAZAD is not set > >> > # CONFIG_CRYPTO_SALSA20 is not set > >> > # CONFIG_CRYPTO_CHACHA20 is not set > >> > # CONFIG_CRYPTO_CHACHA20_X86_64 is not set > >> > # CONFIG_CRYPTO_SEED is not set > >> > # CONFIG_CRYPTO_SERPENT is not set > >> > # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set > >> > # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set > >> > # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set > >> > # CONFIG_CRYPTO_SM4 is not set > >> > # CONFIG_CRYPTO_TEA is not set > >> > # CONFIG_CRYPTO_TWOFISH is not set > >> > # CONFIG_CRYPTO_TWOFISH_X86_64 is not set > >> > # CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set > >> > # CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set > >> > > >> > # > >> > # Compression > >> > # > >> > CONFIG_CRYPTO_DEFLATE=y > >> > CONFIG_CRYPTO_LZO=m > >> > # CONFIG_CRYPTO_842 is not set > >> > # CONFIG_CRYPTO_LZ4 is not set > >> > # CONFIG_CRYPTO_LZ4HC is not set > >> > # CONFIG_CRYPTO_ZSTD is not set > >> > > >> > # > >> > # Random Number Generation > >> > # > >> > # CONFIG_CRYPTO_ANSI_CPRNG is not set > >> > CONFIG_CRYPTO_DRBG_MENU=y > >> > CONFIG_CRYPTO_DRBG_HMAC=y > >> > # CONFIG_CRYPTO_DRBG_HASH is not set > >> > # CONFIG_CRYPTO_DRBG_CTR is not set > >> > CONFIG_CRYPTO_DRBG=y > >> > CONFIG_CRYPTO_JITTERENTROPY=y > >> > CONFIG_CRYPTO_USER_API=y > >> > CONFIG_CRYPTO_USER_API_HASH=y > >> > # CONFIG_CRYPTO_USER_API_SKCIPHER is not set > >> > # CONFIG_CRYPTO_USER_API_RNG is not set > >> > # CONFIG_CRYPTO_USER_API_AEAD is not set > >> > CONFIG_CRYPTO_HASH_INFO=y > >> > > >> > # > >> > # Crypto library routines > >> > # > >> > CONFIG_CRYPTO_LIB_AES=y > >> > CONFIG_CRYPTO_LIB_ARC4=m > >> > # CONFIG_CRYPTO_LIB_BLAKE2S is not set > >> > CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y > >> > CONFIG_CRYPTO_LIB_CHACHA=y > >> > # CONFIG_CRYPTO_LIB_CURVE25519 is not set > >> > CONFIG_CRYPTO_LIB_DES=y > >> > CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 > >> > CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y > >> > CONFIG_CRYPTO_LIB_POLY1305=y > >> > CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y > >> > CONFIG_CRYPTO_LIB_SHA256=y > >> > # CONFIG_CRYPTO_HW is not set > >> > CONFIG_ASYMMETRIC_KEY_TYPE=y > >> > CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y > >> > # CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set > >> > CONFIG_X509_CERTIFICATE_PARSER=y > >> > # CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set > >> > CONFIG_PKCS7_MESSAGE_PARSER=y > >> > CONFIG_PKCS7_TEST_KEY=y > >> > CONFIG_SIGNED_PE_FILE_VERIFICATION=y > >> > > >> > # > >> > # Certificates for signature checking > >> > # > >> > CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" > >> > CONFIG_SYSTEM_TRUSTED_KEYRING=y > >> > CONFIG_SYSTEM_TRUSTED_KEYS="" > >> > CONFIG_SYSTEM_EXTRA_CERTIFICATE=y > >> > CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 > >> > CONFIG_SECONDARY_TRUSTED_KEYRING=y > >> > CONFIG_SYSTEM_BLACKLIST_KEYRING=y > >> > CONFIG_SYSTEM_BLACKLIST_HASH_LIST="/data/modsign/blacklist" > >> > # end of Certificates for signature checking > >> > > >> > CONFIG_BINARY_PRINTF=y > >> > > >> > # > >> > # Library routines > >> > # > >> > CONFIG_RAID6_PQ=y > >> > CONFIG_RAID6_PQ_BENCHMARK=y > >> > # CONFIG_PACKING is not set > >> > CONFIG_BITREVERSE=y > >> > CONFIG_GENERIC_STRNCPY_FROM_USER=y > >> > CONFIG_GENERIC_STRNLEN_USER=y > >> > CONFIG_GENERIC_NET_UTILS=y > >> > CONFIG_GENERIC_FIND_FIRST_BIT=y > >> > # CONFIG_CORDIC is not set > >> > CONFIG_RATIONAL=y > >> > CONFIG_GENERIC_PCI_IOMAP=y > >> > CONFIG_GENERIC_IOMAP=y > >> > CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y > >> > CONFIG_ARCH_HAS_FAST_MULTIPLIER=y > >> > CONFIG_CRC_CCITT=y > >> > CONFIG_CRC16=y > >> > CONFIG_CRC_T10DIF=y > >> > CONFIG_CRC_ITU_T=y > >> > CONFIG_CRC32=y > >> > # CONFIG_CRC32_SELFTEST is not set > >> > CONFIG_CRC32_SLICEBY8=y > >> > # CONFIG_CRC32_SLICEBY4 is not set > >> > # CONFIG_CRC32_SARWATE is not set > >> > # CONFIG_CRC32_BIT is not set > >> > # CONFIG_CRC64 is not set > >> > # CONFIG_CRC4 is not set > >> > # CONFIG_CRC7 is not set > >> > CONFIG_LIBCRC32C=y > >> > # CONFIG_CRC8 is not set > >> > CONFIG_XXHASH=y > >> > # CONFIG_RANDOM32_SELFTEST is not set > >> > CONFIG_ZLIB_INFLATE=y > >> > CONFIG_ZLIB_DEFLATE=y > >> > CONFIG_LZO_COMPRESS=y > >> > CONFIG_LZO_DECOMPRESS=y > >> > CONFIG_ZSTD_COMPRESS=y > >> > CONFIG_ZSTD_DECOMPRESS=y > >> > CONFIG_XZ_DEC=y > >> > CONFIG_XZ_DEC_X86=y > >> > # CONFIG_XZ_DEC_POWERPC is not set > >> > # CONFIG_XZ_DEC_IA64 is not set > >> > # CONFIG_XZ_DEC_ARM is not set > >> > # CONFIG_XZ_DEC_ARMTHUMB is not set > >> > # CONFIG_XZ_DEC_SPARC is not set > >> > CONFIG_XZ_DEC_BCJ=y > >> > # CONFIG_XZ_DEC_TEST is not set > >> > CONFIG_DECOMPRESS_GZIP=y > >> > CONFIG_GENERIC_ALLOCATOR=y > >> > CONFIG_INTERVAL_TREE=y > >> > CONFIG_ASSOCIATIVE_ARRAY=y > >> > CONFIG_HAS_IOMEM=y > >> > CONFIG_HAS_IOPORT_MAP=y > >> > CONFIG_HAS_DMA=y > >> > CONFIG_NEED_SG_DMA_LENGTH=y > >> > CONFIG_NEED_DMA_MAP_STATE=y > >> > CONFIG_ARCH_DMA_ADDR_T_64BIT=y > >> > CONFIG_SWIOTLB=y > >> > # CONFIG_DMA_API_DEBUG is not set > >> > CONFIG_SGL_ALLOC=y > >> > CONFIG_IOMMU_HELPER=y > >> > CONFIG_CHECK_SIGNATURE=y > >> > CONFIG_CPU_RMAP=y > >> > CONFIG_DQL=y > >> > CONFIG_GLOB=y > >> > # CONFIG_GLOB_SELFTEST is not set > >> > CONFIG_NLATTR=y > >> > CONFIG_CLZ_TAB=y > >> > # CONFIG_IRQ_POLL is not set > >> > CONFIG_MPILIB=y > >> > CONFIG_OID_REGISTRY=y > >> > CONFIG_UCS2_STRING=y > >> > CONFIG_HAVE_GENERIC_VDSO=y > >> > CONFIG_GENERIC_GETTIMEOFDAY=y > >> > CONFIG_GENERIC_VDSO_TIME_NS=y > >> > CONFIG_FONT_SUPPORT=y > >> > CONFIG_FONT_8x16=y > >> > CONFIG_FONT_AUTOSELECT=y > >> > CONFIG_SG_POOL=y > >> > CONFIG_ARCH_HAS_PMEM_API=y > >> > CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y > >> > CONFIG_ARCH_HAS_UACCESS_MCSAFE=y > >> > CONFIG_ARCH_STACKWALK=y > >> > CONFIG_SBITMAP=y > >> > # CONFIG_STRING_SELFTEST is not set > >> > # end of Library routines > >> > > >> > # > >> > # Kernel hacking > >> > # > >> > > >> > # > >> > # printk and dmesg options > >> > # > >> > # CONFIG_PRINTK_TIME is not set > >> > # CONFIG_PRINTK_CALLER is not set > >> > CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 > >> > CONFIG_CONSOLE_LOGLEVEL_QUIET=4 > >> > CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 > >> > # CONFIG_BOOT_PRINTK_DELAY is not set > >> > # CONFIG_DYNAMIC_DEBUG is not set > >> > CONFIG_SYMBOLIC_ERRNAME=y > >> > CONFIG_DEBUG_BUGVERBOSE=y > >> > # end of printk and dmesg options > >> > > >> > # > >> > # Compile-time checks and compiler options > >> > # > >> > CONFIG_DEBUG_INFO=y > >> > # CONFIG_DEBUG_INFO_REDUCED is not set > >> > # CONFIG_DEBUG_INFO_SPLIT is not set > >> > # CONFIG_DEBUG_INFO_DWARF4 is not set > >> > # CONFIG_DEBUG_INFO_BTF is not set > >> > # CONFIG_GDB_SCRIPTS is not set > >> > # CONFIG_ENABLE_MUST_CHECK is not set > >> > CONFIG_FRAME_WARN=2048 > >> > # CONFIG_STRIP_ASM_SYMS is not set > >> > # CONFIG_READABLE_ASM is not set > >> > CONFIG_HEADERS_INSTALL=y > >> > CONFIG_DEBUG_SECTION_MISMATCH=y > >> > CONFIG_SECTION_MISMATCH_WARN_ONLY=y > >> > CONFIG_STACK_VALIDATION=y > >> > # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set > >> > # end of Compile-time checks and compiler options > >> > > >> > # > >> > # Generic Kernel Debugging Instruments > >> > # > >> > CONFIG_MAGIC_SYSRQ=y > >> > CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 > >> > CONFIG_MAGIC_SYSRQ_SERIAL=y > >> > CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" > >> > CONFIG_DEBUG_FS=y > >> > CONFIG_HAVE_ARCH_KGDB=y > >> > # CONFIG_KGDB is not set > >> > CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y > >> > # CONFIG_UBSAN is not set > >> > # end of Generic Kernel Debugging Instruments > >> > > >> > CONFIG_DEBUG_KERNEL=y > >> > CONFIG_DEBUG_MISC=y > >> > > >> > # > >> > # Memory Debugging > >> > # > >> > # CONFIG_PAGE_EXTENSION is not set > >> > # CONFIG_DEBUG_PAGEALLOC is not set > >> > # CONFIG_PAGE_OWNER is not set > >> > # CONFIG_PAGE_POISONING is not set > >> > # CONFIG_DEBUG_PAGE_REF is not set > >> > # CONFIG_DEBUG_RODATA_TEST is not set > >> > CONFIG_GENERIC_PTDUMP=y > >> > # CONFIG_PTDUMP_DEBUGFS is not set > >> > # CONFIG_DEBUG_OBJECTS is not set > >> > # CONFIG_DEBUG_SLAB is not set > >> > CONFIG_HAVE_DEBUG_KMEMLEAK=y > >> > # CONFIG_DEBUG_KMEMLEAK is not set > >> > # CONFIG_DEBUG_STACK_USAGE is not set > >> > # CONFIG_SCHED_STACK_END_CHECK is not set > >> > # CONFIG_DEBUG_VM is not set > >> > CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y > >> > # CONFIG_DEBUG_VIRTUAL is not set > >> > # CONFIG_DEBUG_MEMORY_INIT is not set > >> > # CONFIG_DEBUG_PER_CPU_MAPS is not set > >> > CONFIG_HAVE_ARCH_KASAN=y > >> > CONFIG_HAVE_ARCH_KASAN_VMALLOC=y > >> > CONFIG_CC_HAS_KASAN_GENERIC=y > >> > # CONFIG_KASAN is not set > >> > CONFIG_KASAN_STACK=1 > >> > # end of Memory Debugging > >> > > >> > # CONFIG_DEBUG_SHIRQ is not set > >> > > >> > # > >> > # Debug Oops, Lockups and Hangs > >> > # > >> > # CONFIG_PANIC_ON_OOPS is not set > >> > CONFIG_PANIC_ON_OOPS_VALUE=0 > >> > CONFIG_PANIC_TIMEOUT=0 > >> > CONFIG_LOCKUP_DETECTOR=y > >> > CONFIG_SOFTLOCKUP_DETECTOR=y > >> > # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set > >> > CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 > >> > CONFIG_HARDLOCKUP_DETECTOR_PERF=y > >> > CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y > >> > CONFIG_HARDLOCKUP_DETECTOR=y > >> > # CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set > >> > CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 > >> > CONFIG_DETECT_HUNG_TASK=y > >> > CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 > >> > # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set > >> > CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 > >> > CONFIG_WQ_WATCHDOG=y > >> > # CONFIG_TEST_LOCKUP is not set > >> > # end of Debug Oops, Lockups and Hangs > >> > > >> > # > >> > # Scheduler Debugging > >> > # > >> > # CONFIG_SCHED_DEBUG is not set > >> > CONFIG_SCHED_INFO=y > >> > # CONFIG_SCHEDSTATS is not set > >> > # end of Scheduler Debugging > >> > > >> > # CONFIG_DEBUG_TIMEKEEPING is not set > >> > > >> > # > >> > # Lock Debugging (spinlocks, mutexes, etc...) > >> > # > >> > CONFIG_LOCK_DEBUGGING_SUPPORT=y > >> > # CONFIG_PROVE_LOCKING is not set > >> > # CONFIG_LOCK_STAT is not set > >> > CONFIG_DEBUG_RT_MUTEXES=y > >> > CONFIG_DEBUG_SPINLOCK=y > >> > CONFIG_DEBUG_MUTEXES=y > >> > # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set > >> > # CONFIG_DEBUG_RWSEMS is not set > >> > # CONFIG_DEBUG_LOCK_ALLOC is not set > >> > # CONFIG_DEBUG_ATOMIC_SLEEP is not set > >> > # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set > >> > # CONFIG_LOCK_TORTURE_TEST is not set > >> > # CONFIG_WW_MUTEX_SELFTEST is not set > >> > # end of Lock Debugging (spinlocks, mutexes, etc...) > >> > > >> > CONFIG_STACKTRACE=y > >> > # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set > >> > # CONFIG_DEBUG_KOBJECT is not set > >> > > >> > # > >> > # Debug kernel data structures > >> > # > >> > # CONFIG_DEBUG_LIST is not set > >> > # CONFIG_DEBUG_PLIST is not set > >> > # CONFIG_DEBUG_SG is not set > >> > # CONFIG_DEBUG_NOTIFIERS is not set > >> > # CONFIG_BUG_ON_DATA_CORRUPTION is not set > >> > # end of Debug kernel data structures > >> > > >> > # CONFIG_DEBUG_CREDENTIALS is not set > >> > > >> > # > >> > # RCU Debugging > >> > # > >> > # CONFIG_RCU_PERF_TEST is not set > >> > # CONFIG_RCU_TORTURE_TEST is not set > >> > CONFIG_RCU_CPU_STALL_TIMEOUT=60 > >> > # CONFIG_RCU_TRACE is not set > >> > # CONFIG_RCU_EQS_DEBUG is not set > >> > # end of RCU Debugging > >> > > >> > # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set > >> > # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set > >> > # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set > >> > # CONFIG_LATENCYTOP is not set > >> > CONFIG_USER_STACKTRACE_SUPPORT=y > >> > CONFIG_NOP_TRACER=y > >> > CONFIG_HAVE_FUNCTION_TRACER=y > >> > CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y > >> > CONFIG_HAVE_DYNAMIC_FTRACE=y > >> > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y > >> > CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y > >> > CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y > >> > CONFIG_HAVE_SYSCALL_TRACEPOINTS=y > >> > CONFIG_HAVE_FENTRY=y > >> > CONFIG_HAVE_C_RECORDMCOUNT=y > >> > CONFIG_TRACE_CLOCK=y > >> > CONFIG_RING_BUFFER=y > >> > CONFIG_EVENT_TRACING=y > >> > CONFIG_CONTEXT_SWITCH_TRACER=y > >> > CONFIG_TRACING=y > >> > CONFIG_GENERIC_TRACER=y > >> > CONFIG_TRACING_SUPPORT=y > >> > CONFIG_FTRACE=y > >> > # CONFIG_BOOTTIME_TRACING is not set > >> > CONFIG_FUNCTION_TRACER=y > >> > CONFIG_FUNCTION_GRAPH_TRACER=y > >> > CONFIG_DYNAMIC_FTRACE=y > >> > CONFIG_DYNAMIC_FTRACE_WITH_REGS=y > >> > CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y > >> > # CONFIG_FUNCTION_PROFILER is not set > >> > # CONFIG_STACK_TRACER is not set > >> > # CONFIG_PREEMPTIRQ_EVENTS is not set > >> > # CONFIG_IRQSOFF_TRACER is not set > >> > # CONFIG_SCHED_TRACER is not set > >> > # CONFIG_HWLAT_TRACER is not set > >> > # CONFIG_MMIOTRACE is not set > >> > CONFIG_FTRACE_SYSCALLS=y > >> > # CONFIG_TRACER_SNAPSHOT is not set > >> > CONFIG_BRANCH_PROFILE_NONE=y > >> > # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set > >> > # CONFIG_PROFILE_ALL_BRANCHES is not set > >> > # CONFIG_BLK_DEV_IO_TRACE is not set > >> > CONFIG_KPROBE_EVENTS=y > >> > # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set > >> > # CONFIG_UPROBE_EVENTS is not set > >> > CONFIG_BPF_EVENTS=y > >> > CONFIG_DYNAMIC_EVENTS=y > >> > CONFIG_PROBE_EVENTS=y > >> > # CONFIG_BPF_KPROBE_OVERRIDE is not set > >> > CONFIG_FTRACE_MCOUNT_RECORD=y > >> > # CONFIG_HIST_TRIGGERS is not set > >> > # CONFIG_TRACE_EVENT_INJECT is not set > >> > # CONFIG_TRACEPOINT_BENCHMARK is not set > >> > # CONFIG_RING_BUFFER_BENCHMARK is not set > >> > # CONFIG_TRACE_EVAL_MAP_FILE is not set > >> > # CONFIG_FTRACE_STARTUP_TEST is not set > >> > # CONFIG_RING_BUFFER_STARTUP_TEST is not set > >> > # CONFIG_PREEMPTIRQ_DELAY_TEST is not set > >> > # CONFIG_KPROBE_EVENT_GEN_TEST is not set > >> > # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set > >> > CONFIG_SAMPLES=y > >> > # CONFIG_SAMPLE_TRACE_EVENTS is not set > >> > # CONFIG_SAMPLE_TRACE_PRINTK is not set > >> > # CONFIG_SAMPLE_FTRACE_DIRECT is not set > >> > # CONFIG_SAMPLE_TRACE_ARRAY is not set > >> > # CONFIG_SAMPLE_KOBJECT is not set > >> > # CONFIG_SAMPLE_KPROBES is not set > >> > # CONFIG_SAMPLE_HW_BREAKPOINT is not set > >> > # CONFIG_SAMPLE_KFIFO is not set > >> > # CONFIG_SAMPLE_LIVEPATCH is not set > >> > # CONFIG_SAMPLE_CONFIGFS is not set > >> > # CONFIG_SAMPLE_HIDRAW is not set > >> > # CONFIG_SAMPLE_PIDFD is not set > >> > # CONFIG_SAMPLE_SECCOMP is not set > >> > # CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set > >> > CONFIG_SAMPLE_VFS=y > >> > # CONFIG_SAMPLE_INTEL_MEI is not set > >> > CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y > >> > > >> > # > >> > # x86 Debugging > >> > # > >> > CONFIG_TRACE_IRQFLAGS_SUPPORT=y > >> > CONFIG_X86_VERBOSE_BOOTUP=y > >> > CONFIG_EARLY_PRINTK=y > >> > # CONFIG_EARLY_PRINTK_DBGP is not set > >> > # CONFIG_EARLY_PRINTK_USB_XDBC is not set > >> > # CONFIG_EFI_PGT_DUMP is not set > >> > # CONFIG_DEBUG_WX is not set > >> > CONFIG_DOUBLEFAULT=y > >> > # CONFIG_DEBUG_TLBFLUSH is not set > >> > # CONFIG_IOMMU_DEBUG is not set > >> > CONFIG_HAVE_MMIOTRACE_SUPPORT=y > >> > # CONFIG_X86_DECODER_SELFTEST is not set > >> > CONFIG_IO_DELAY_0X80=y > >> > # CONFIG_IO_DELAY_0XED is not set > >> > # CONFIG_IO_DELAY_UDELAY is not set > >> > # CONFIG_IO_DELAY_NONE is not set > >> > # CONFIG_DEBUG_BOOT_PARAMS is not set > >> > # CONFIG_CPA_DEBUG is not set > >> > # CONFIG_DEBUG_ENTRY is not set > >> > # CONFIG_DEBUG_NMI_SELFTEST is not set > >> > # CONFIG_X86_DEBUG_FPU is not set > >> > # CONFIG_PUNIT_ATOM_DEBUG is not set > >> > CONFIG_UNWINDER_ORC=y > >> > # CONFIG_UNWINDER_FRAME_POINTER is not set > >> > # CONFIG_UNWINDER_GUESS is not set > >> > # end of x86 Debugging > >> > > >> > # > >> > # Kernel Testing and Coverage > >> > # > >> > # CONFIG_KUNIT is not set > >> > # CONFIG_NOTIFIER_ERROR_INJECTION is not set > >> > CONFIG_FUNCTION_ERROR_INJECTION=y > >> > # CONFIG_FAULT_INJECTION is not set > >> > CONFIG_ARCH_HAS_KCOV=y > >> > CONFIG_CC_HAS_SANCOV_TRACE_PC=y > >> > # CONFIG_KCOV is not set > >> > # CONFIG_RUNTIME_TESTING_MENU is not set > >> > # CONFIG_MEMTEST is not set > >> > # end of Kernel Testing and Coverage > >> > # end of Kernel hacking > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx at lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Graphics Center From patchwork at emeril.freedesktop.org Tue Jun 9 13:08:59 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 13:08:59 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Incrementally_check_for_rewinding?= In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <159170813953.17061.9710110462093972296@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Incrementally check for rewinding URL : https://patchwork.freedesktop.org/series/78163/ State : success == Summary == CI Bug Log - changes from CI_DRM_8602 -> Patchwork_17914 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/index.html Known issues ------------ Here are the changes found in Patchwork_17914 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html * {igt at kms_flip@basic-flip-vs-modeset at b-dsi1}: - {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at b-dsi1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at b-dsi1.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][13] ([i915#62]) -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8602 -> Patchwork_17914 CI-20190529: 20190529 CI_DRM_8602: 8b5dcdfb116246ecc8e676961bb1cf82ec75e33f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17914: e9fc78f4bfec134476a0eed02ee2b2241c4f206b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e9fc78f4bfec drm/i915/gt: Incrementally check for rewinding == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/index.html From hdegoede at redhat.com Tue Jun 9 13:44:18 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Tue, 9 Jun 2020 15:44:18 +0200 Subject: [Intel-gfx] [PATCH v2 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API In-Reply-To: <20200609113220.GM2428291@smile.fi.intel.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-11-hdegoede@redhat.com> <20200609113220.GM2428291@smile.fi.intel.com> Message-ID: <93c7843d-1225-c8c6-9eb7-1f11b44bec34@redhat.com> Hi, On 6/9/20 1:32 PM, Andy Shevchenko wrote: > On Sun, Jun 07, 2020 at 08:18:35PM +0200, Hans de Goede wrote: >> Replace the enable, disable and config pwm_ops with an apply op, >> to support the new atomic PWM API. > > ... > >> -static int crc_pwm_calc_clk_div(int period_ns) >> +static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, >> + const struct pwm_state *state) >> { >> - int clk_div; >> - >> - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_MHZ); >> - /* clk_div 1 - 128, maps to register values 0-127 */ >> - if (clk_div > 0) >> - clk_div--; >> - >> - return clk_div; >> -} > > ... > >> + clk_div = PWM_BASE_CLK_MHZ * state->period / >> + (256 * NSEC_PER_MHZ); >> + /* clk_div 1 - 128, maps to register values 0-127 */ >> + if (clk_div > 0) >> + clk_div--; > > And again... :-( Well yes I cannot help it that the original code, as submitted by Intel, was of very questionable quality, so instead of just converting it to the atomic PWM API I had to do a ton of bugfixes first... I tried to do this all in small bits rather then in a single big rewrite the buggy <beep> commit to make life easier for reviewers. I can introduce the crc_pwm_calc_clk_div helper earlier as you suggested in an earlier mail. I guess I could also keep the helper here, and then fold it into the function in a later commit (*). Would that work for you ? Regards, Hans *) Because having a helper for 3 lines of code when it is used only once is not helpful IMHO, it only makes it harder to figure out what the code is exactly doing when readin the code. From hdegoede at redhat.com Tue Jun 9 13:45:25 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Tue, 9 Jun 2020 15:45:25 +0200 Subject: [Intel-gfx] [PATCH v2 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 In-Reply-To: <20200609112905.GK2428291@smile.fi.intel.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-7-hdegoede@redhat.com> <20200609112905.GK2428291@smile.fi.intel.com> Message-ID: <fd839acc-9e25-14aa-d1ac-dbc262c7860e@redhat.com> Hi, On 6/9/20 1:29 PM, Andy Shevchenko wrote: > On Sun, Jun 07, 2020 at 08:18:31PM +0200, Hans de Goede wrote: >> While looking into adding atomic-pwm support to the pwm-crc driver I >> noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and >> there is a clock-divider which divides this with a value between 1-128, >> and there are 256 duty-cycle steps. >> >> The pwm-crc code before this commit assumed that a clock-divider >> setting of 1 means that the PWM output is running at 6 MHZ, if that >> is true, where do these 256 duty-cycle steps come from? >> >> This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that >> seems unlikely for a PMIC which is using a silicon process optimized for >> power-switching transistors. It is way more likely that there is an 8 >> bit counter for the duty cycle which acts as an extra fixed divider >> wrt the PWM output frequency. >> >> The main user of the pwm-crc driver is the i915 GPU driver which uses it >> for backlight control. Lets compare the PWM register values set by the >> video-BIOS (the GOP), assuming the extra fixed divider is present versus >> the PWM frequency specified in the Video-BIOS-Tables: >> >> Device: PWM Hz set by BIOS PWM Hz specified in VBT >> Asus T100TA 200 200 >> Asus T100HA 200 200 >> Lenovo Miix 2 8 23437 20000 >> Toshiba WT8-A 23437 20000 >> >> So as we can see if we assume the extra division by 256 then the register >> values set by the GOP are an exact match for the VBT values, where as >> otherwise the values would be of by a factor of 256. >> >> This commit fixes the period / duty_cycle calculations to take the >> extra division by 256 into account. > > ... > >> +#define NSEC_PER_MHZ 1000 > > This is against physics. What this cryptic name means actually? > Existing NSEC_PER_USEC ? Yes, using existing NSEC_PER_USEC is better I will use that for the next version. Regards, Hans From andriy.shevchenko at linux.intel.com Tue Jun 9 13:50:20 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Tue, 9 Jun 2020 16:50:20 +0300 Subject: [Intel-gfx] [PATCH v2 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API In-Reply-To: <93c7843d-1225-c8c6-9eb7-1f11b44bec34@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-11-hdegoede@redhat.com> <20200609113220.GM2428291@smile.fi.intel.com> <93c7843d-1225-c8c6-9eb7-1f11b44bec34@redhat.com> Message-ID: <20200609135020.GP2428291@smile.fi.intel.com> On Tue, Jun 09, 2020 at 03:44:18PM +0200, Hans de Goede wrote: > On 6/9/20 1:32 PM, Andy Shevchenko wrote: > > On Sun, Jun 07, 2020 at 08:18:35PM +0200, Hans de Goede wrote: ... > > And again... :-( > > Well yes I cannot help it that the original code, as submitted by Intel, > was of very questionable quality, so instead of just converting it to the > atomic PWM API I had to do a ton of bugfixes first... I tried to do > this all in small bits rather then in a single big rewrite the buggy > <beep> commit to make life easier for reviewers. Yes, I know about that old code quality, sorry, we were not at Intel that time (or were just right-less newbies). > I can introduce the crc_pwm_calc_clk_div helper earlier as you suggested > in an earlier mail. I guess I could also keep the helper here, and then > fold it into the function in a later commit (*). > > Would that work for you ? Definitely. > *) Because having a helper for 3 lines of code when it is used only > once is not helpful IMHO, it only makes it harder to figure out what > the code is exactly doing when readin the code. At least it will reduce churn to just 1) introduce foo(); 2) do many changes with foo() being used; 3) drop foo() *if* it's not needed / makes little sense. -- With Best Regards, Andy Shevchenko From patchwork at emeril.freedesktop.org Tue Jun 9 14:10:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 14:10:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Incrementally_check_for_rewinding?= In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <159171181017.17062.913213310997023142@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Incrementally check for rewinding URL : https://patchwork.freedesktop.org/series/78163/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8602_full -> Patchwork_17914_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17914_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17914_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17914_full: ### IGT changes ### #### Possible regressions #### * igt at kms_flip@flip-vs-absolute-wf_vblank at a-dp1: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-kbl6/igt at kms_flip@flip-vs-absolute-wf_vblank at a-dp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-kbl1/igt at kms_flip@flip-vs-absolute-wf_vblank at a-dp1.html New tests --------- New tests have been introduced between CI_DRM_8602_full and Patchwork_17914_full: ### New IGT tests (1) ### * igt at i915_selftest@mock at ring: - Statuses : 8 pass(s) - Exec time: [0.11, 1.13] s Known issues ------------ Here are the changes found in Patchwork_17914_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-queues-priority-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-glk8/igt at gem_exec_whisper@basic-queues-priority-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-glk8/igt at gem_exec_whisper@basic-queues-priority-all.html * igt at kms_big_fb@linear-16bpp-rotate-0: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-apl8/igt at kms_big_fb@linear-16bpp-rotate-0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-apl6/igt at kms_big_fb@linear-16bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl8/igt at kms_color@pipe-c-ctm-0-25.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl5/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-kbl3/igt at kms_color@pipe-c-ctm-blue-to-red.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-kbl3/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl6/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-apl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_lease@page_flip_implicit_plane: - shard-snb: [PASS][19] -> [TIMEOUT][20] ([i915#1958]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-snb2/igt at kms_lease@page_flip_implicit_plane.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-snb4/igt at kms_lease@page_flip_implicit_plane.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-iclb8/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#69]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at syncobj_wait@multi-wait-for-submit-submitted-signaled: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#95]) +20 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-apl8/igt at syncobj_wait@multi-wait-for-submit-submitted-signaled.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-apl7/igt at syncobj_wait@multi-wait-for-submit-submitted-signaled.html #### Possible fixes #### * igt at gem_ctx_persistence@engines-mixed-process at vecs0: - shard-skl: [FAIL][29] ([i915#1528]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl8/igt at gem_ctx_persistence@engines-mixed-process at vecs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl6/igt at gem_ctx_persistence@engines-mixed-process at vecs0.html * igt at i915_pm_dc@dc5-dpms: - shard-skl: [INCOMPLETE][31] ([i915#198]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl2/igt at i915_pm_dc@dc5-dpms.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl10/igt at i915_pm_dc@dc5-dpms.html * igt at i915_pm_dc@dc6-psr: - shard-skl: [FAIL][33] ([i915#454]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl6/igt at i915_pm_dc@dc6-psr.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl2/igt at i915_pm_dc@dc6-psr.html * igt at kms_addfb_basic@bad-pitch-999: - shard-apl: [DMESG-WARN][35] ([i915#95]) -> [PASS][36] +18 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-apl1/igt at kms_addfb_basic@bad-pitch-999.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-apl8/igt at kms_addfb_basic@bad-pitch-999.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [FAIL][37] ([IGT#5]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl8/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_flip@2x-flip-vs-blocking-wf-vblank at ab-vga1-hdmi-a1: - shard-hsw: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-hsw6/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at ab-vga1-hdmi-a1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-hsw2/igt at kms_flip@2x-flip-vs-blocking-wf-vblank at ab-vga1-hdmi-a1.html * igt at kms_flip@basic-flip-vs-dpms at a-edp1: - shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +4 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl10/igt at kms_flip@basic-flip-vs-dpms at a-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl10/igt at kms_flip@basic-flip-vs-dpms at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank at c-hdmi-a1: - shard-glk: [FAIL][43] ([i915#79]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-glk4/igt at kms_flip@flip-vs-expired-vblank at c-hdmi-a1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-glk9/igt at kms_flip@flip-vs-expired-vblank at c-hdmi-a1.html * igt at kms_flip@flip-vs-suspend at b-dp1: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-apl8/igt at kms_flip@flip-vs-suspend at b-dp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-apl7/igt at kms_flip@flip-vs-suspend at b-dp1.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][47] ([fdo#108145] / [i915#265]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][49] ([fdo#109441]) -> [PASS][50] +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-iclb6/igt at kms_psr@psr2_sprite_plane_move.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [INCOMPLETE][53] ([i915#155]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-kbl1/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-kbl2/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at perf@polling-parameterized: - shard-hsw: [FAIL][55] ([i915#1542]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-hsw6/igt at perf@polling-parameterized.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-hsw7/igt at perf@polling-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][57] ([i915#1930]) -> [TIMEOUT][58] ([i915#1958]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][59] ([i915#588]) -> [SKIP][60] ([i915#658]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-iclb8/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-snb: [INCOMPLETE][61] ([i915#82]) -> [SKIP][62] ([fdo#109271]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-snb5/igt at i915_pm_dc@dc6-psr.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-snb6/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][63] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][64] ([fdo#110321] / [i915#95]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-apl6/igt at kms_content_protection@atomic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][65] ([i915#1319] / [i915#1958]) -> [TIMEOUT][66] ([i915#1319]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-kbl4/igt at kms_content_protection@legacy.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-kbl7/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [TIMEOUT][68] ([i915#1319]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-apl3/igt at kms_content_protection@srm.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-apl3/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][69] ([i915#93] / [i915#95]) -> [DMESG-WARN][70] ([i915#180] / [i915#93] / [i915#95]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-skl: [FAIL][71] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][72] ([fdo#108145] / [i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html * igt at kms_psr@suspend: - shard-snb: [SKIP][73] ([fdo#109271]) -> [TIMEOUT][74] ([i915#1958]) +2 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8602/shard-snb2/igt at kms_psr@suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/shard-snb4/igt at kms_psr@suspend.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8602 -> Patchwork_17914 CI-20190529: 20190529 CI_DRM_8602: 8b5dcdfb116246ecc8e676961bb1cf82ec75e33f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17914: e9fc78f4bfec134476a0eed02ee2b2241c4f206b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17914/index.html From ville.syrjala at linux.intel.com Tue Jun 9 15:05:25 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 9 Jun 2020 18:05:25 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200608181023.11503-1-imre.deak@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> Message-ID: <20200609150525.GP6112@intel.com> On Mon, Jun 08, 2020 at 09:10:23PM +0300, Imre Deak wrote: > DSC is not supported on DP MST streams so just return -EINVAL when > reading/writing the i915_dsc_fec_support debugfs file for such > connectors. > > This also fixes an OOPS, caused by the encoder->digport cast, which is > not valid for MST encoders. > > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- > 1 file changed, 29 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 2b640d8ab9d2..ebca8e488d03 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); > > do { > + struct intel_encoder *encoder; > + > try_again = false; > ret = drm_modeset_lock(&dev->mode_config.connection_mutex, > &ctx); > @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > } else if (ret) { > break; > } > - intel_dp = intel_attached_dp(to_intel_connector(connector)); > + > + encoder = intel_attached_encoder(to_intel_connector(connector)); > + /* TODO: Add DSC support for MST streams */ > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > + ret = -EINVAL; > + break; > + } > + > + intel_dp = &enc_to_dig_port(encoder)->dp; > crtc_state = to_intel_crtc_state(crtc->state); > + > seq_printf(m, "DSC_Enabled: %s\n", > yesno(crtc_state->dsc.compression_enable)); > seq_printf(m, "DSC_Sink_Support: %s\n", > @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > int ret; > struct drm_connector *connector = > ((struct seq_file *)file->private_data)->private; > - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); > - struct drm_i915_private *i915 = to_i915(encoder->base.dev); > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + struct drm_i915_private *i915 = to_i915(connector->dev); > + struct intel_encoder *encoder; > > if (len == 0) > return 0; > @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > drm_dbg(&i915->drm, "Got %s for DSC Enable\n", > (dsc_enable) ? "true" : "false"); > - intel_dp->force_dsc_en = dsc_enable; > > - *offp += len; > - return len; > + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); > + > + encoder = intel_attached_encoder(to_intel_connector(connector)); > + /* TODO: Add DSC support for MST streams */ > + if (encoder->type == INTEL_OUTPUT_DP_MST) { The attached encoder can be NULL for MST. Can't we just not add this debugfs file for MST connectors? > + ret = -EINVAL; > + } else { > + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; > + *offp += len; > + ret = len; > + } > + > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); > + > + return ret; > } > > static int i915_dsc_fec_support_open(struct inode *inode, > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 9 15:14:01 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 9 Jun 2020 18:14:01 +0300 Subject: [Intel-gfx] [PATCH v4 1/7] drm/i915/rkl: RKL uses ABOX0 for pixel transfers In-Reply-To: <20200606025740.3308880-2-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> <20200606025740.3308880-2-matthew.d.roper@intel.com> Message-ID: <20200609151401.GQ6112@intel.com> On Fri, Jun 05, 2020 at 07:57:34PM -0700, Matt Roper wrote: > Rocket Lake uses the same 'abox0' mechanism to handle pixel data > transfers from memory that gen11 platforms used, rather than the > abox1/abox2 interfaces used by TGL/DG1. For the most part this is a > hardware implementation detail that's transparent to driver software, > but we do have to program a couple of tuning registers (MBUS_ABOX_CTL > and BW_BUDDY registers) according to which ABOX instances are used by a > platform. Let's track the platform's ABOX usage in the device info > structure and use that to determine which instances of these registers > to program. > > As an exception to this rule is that even though TGL/DG1 use ABOX1+ABOX2 > for data transfers, we're still directed to program the ABOX_CTL > register for ABOX0; so we'll handle that as a special case. > > v2: > - Store the mask of platform-specific abox registers in the device > info structure. > - Add a TLB_REQ_TIMER() helper macro. (Aditya) > > v3: > - Squash ABOX and BW_BUDDY patches together and use a single mask for > both of them, plus a special-case for programming the ABOX0 instance > on all gen12. (Ville) > > Bspec: 50096 > Bspec: 49218 > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Aditya Swarup <aditya.swarup at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > .../drm/i915/display/intel_display_power.c | 55 ++++++++++--------- > drivers/gpu/drm/i915/i915_pci.c | 3 + > drivers/gpu/drm/i915/i915_reg.h | 24 +++++--- > drivers/gpu/drm/i915/intel_device_info.h | 2 + > 4 files changed, 52 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 72312b67b57a..24a2aa1fdc9c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -4760,7 +4760,8 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) > > static void icl_mbus_init(struct drm_i915_private *dev_priv) > { > - u32 mask, val; > + unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask; > + u32 mask, val, i; > > mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | > MBUS_ABOX_BT_CREDIT_POOL2_MASK | > @@ -4771,11 +4772,16 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) > MBUS_ABOX_B_CREDIT(1) | > MBUS_ABOX_BW_CREDIT(1); > > - intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val); > - if (INTEL_GEN(dev_priv) >= 12) { > - intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val); > - intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val); > - } > + /* > + * gen12 platforms that use abox1 and abox2 for pixel data reads still > + * expect us to program the abox_ctl0 register as well, even though > + * we don't have to program other instance-0 registers like BW_BUDDY. > + */ > + if (IS_GEN(dev_priv, 12)) > + abox_regs |= BIT(0); > + > + for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) > + intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); > } > > static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) > @@ -5254,7 +5260,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > enum intel_dram_type type = dev_priv->dram_info.type; > u8 num_channels = dev_priv->dram_info.num_channels; > const struct buddy_page_mask *table; > - int i; > + unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask; > + int config, i; > > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) > /* Wa_1409767108: tgl */ > @@ -5262,29 +5269,27 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > else > table = tgl_buddy_page_masks; > > - for (i = 0; table[i].page_mask != 0; i++) > - if (table[i].num_channels == num_channels && > - table[i].type == type) > + for (config = 0; table[config].page_mask != 0; config++) > + if (table[config].num_channels == num_channels && > + table[config].type == type) > break; > > - if (table[i].page_mask == 0) { > + if (table[config].page_mask == 0) { > drm_dbg(&dev_priv->drm, > "Unknown memory configuration; disabling address buddy logic.\n"); > - intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); > - intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); > + for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) > + intel_de_write(dev_priv, BW_BUDDY_CTL(i), > + BW_BUDDY_DISABLE); > } else { > - intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, > - table[i].page_mask); > - intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, > - table[i].page_mask); > - > - /* Wa_22010178259:tgl */ > - intel_de_rmw(dev_priv, BW_BUDDY1_CTL, > - BW_BUDDY_TLB_REQ_TIMER_MASK, > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > - intel_de_rmw(dev_priv, BW_BUDDY2_CTL, > - BW_BUDDY_TLB_REQ_TIMER_MASK, > - REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); > + for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { > + intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), > + table[config].page_mask); > + > + /* Wa_22010178259:tgl,rkl */ > + intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), > + BW_BUDDY_TLB_REQ_TIMER_MASK, > + BW_BUDDY_TLB_REQ_TIMER(0x8)); > + } > } > } > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 192f1cd172b8..e5fdf17cd9cd 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -804,6 +804,7 @@ static const struct intel_device_info cnl_info = { > #define GEN11_FEATURES \ > GEN10_FEATURES, \ > GEN11_DEFAULT_PAGE_SIZES, \ > + .abox_mask = BIT(0), \ > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ > BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ > @@ -847,6 +848,7 @@ static const struct intel_device_info ehl_info = { > #define GEN12_FEATURES \ > GEN11_FEATURES, \ > GEN(12), \ > + .abox_mask = GENMASK(2, 1), \ > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ > @@ -882,6 +884,7 @@ static const struct intel_device_info tgl_info = { > static const struct intel_device_info rkl_info = { > GEN12_FEATURES, > PLATFORM(INTEL_ROCKETLAKE), > + .abox_mask = BIT(0), > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | > BIT(TRANSCODER_C), > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 814a70945468..4c3e822e1024 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2879,9 +2879,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define LM_FIFO_WATERMARK 0x0000001F > #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ > > -#define MBUS_ABOX_CTL _MMIO(0x45038) > -#define MBUS_ABOX1_CTL _MMIO(0x45048) > -#define MBUS_ABOX2_CTL _MMIO(0x4504C) > +#define _MBUS_ABOX0_CTL 0x45038 > +#define _MBUS_ABOX1_CTL 0x45048 > +#define _MBUS_ABOX2_CTL 0x4504C > +#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ > + _MBUS_ABOX1_CTL, \ > + _MBUS_ABOX2_CTL)) > #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) > #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) > #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) > @@ -7839,13 +7842,20 @@ enum { > #define WAIT_FOR_PCH_RESET_ACK (1 << 1) > #define WAIT_FOR_PCH_FLR_ACK (1 << 0) > > -#define BW_BUDDY1_CTL _MMIO(0x45140) > -#define BW_BUDDY2_CTL _MMIO(0x45150) > +#define _BW_BUDDY0_CTL 0x45130 > +#define _BW_BUDDY1_CTL 0x45140 > +#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ > + _BW_BUDDY0_CTL, \ > + _BW_BUDDY1_CTL)) > #define BW_BUDDY_DISABLE REG_BIT(31) > #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) > +#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) > > -#define BW_BUDDY1_PAGE_MASK _MMIO(0x45144) > -#define BW_BUDDY2_PAGE_MASK _MMIO(0x45154) > +#define _BW_BUDDY0_PAGE_MASK 0x45134 > +#define _BW_BUDDY1_PAGE_MASK 0x45144 > +#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ > + _BW_BUDDY0_PAGE_MASK, \ > + _BW_BUDDY1_PAGE_MASK)) > > #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) > #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 34dbffd65bad..8d62b8538585 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -175,6 +175,8 @@ struct intel_device_info { > u8 pipe_mask; > u8 cpu_transcoder_mask; > > + u8 abox_mask; > + > #define DEFINE_FLAG(name) u8 name:1 > DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); > #undef DEFINE_FLAG > -- > 2.24.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 9 15:14:34 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 9 Jun 2020 18:14:34 +0300 Subject: [Intel-gfx] [PATCH v4 3/7] drm/i915/rkl: Update TGP's pin mapping when paired with RKL In-Reply-To: <20200606025740.3308880-4-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> <20200606025740.3308880-4-matthew.d.roper@intel.com> Message-ID: <20200609151433.GR6112@intel.com> On Fri, Jun 05, 2020 at 07:57:36PM -0700, Matt Roper wrote: > HPD pin handling for RKL+TGP is a special case; we effectively select > the HPD pin based on the DDI (A,B,D,E) rather than the PHY (A,B,C,D). > This differs from the regular behavior of RKL+CMP (and also TGL+TGP). > > v2: > - Rather than providing a custom hpd_pin mapping table, just assign > encoder->hpd_pin in a custom manner for this setup. (Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_hotplug.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c > index 4f6f560e093e..d794dd5f170c 100644 > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c > @@ -89,6 +89,15 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, > { > enum phy phy = intel_port_to_phy(dev_priv, port); > > + /* > + * RKL + TGP PCH is a special case; we effectively choose the hpd_pin > + * based on the DDI rather than the PHY (i.e., the last two outputs > + * shold be HPD_PORT_{D,E} rather than {C,D}. Note that this differs > + * from the behavior of both TGL+TGP and RKL+CMP. > + */ > + if (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)) > + return HPD_PORT_A + port - PORT_A; > + > switch (phy) { > case PHY_F: > return IS_CNL_WITH_PORT_F(dev_priv) ? HPD_PORT_E : HPD_PORT_F; > -- > 2.24.1 -- Ville Syrj?l? Intel From chris at chris-wilson.co.uk Tue Jun 9 15:15:28 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 09 Jun 2020 16:15:28 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Incrementally check for rewinding In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <159171572885.24308.5160778009299838490@build.alporthouse.com> Quoting Chris Wilson (2020-06-09 13:28:56) > In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context > reload when rewinding RING_TAIL"), we placed the check for rewinding a > context on actually submitting the next request in that context. This > was so that we only had to check once, and could do so with precision > avoiding as many forced restores as possible. For example, to ensure > that we can resubmit the same request a couple of times, we include a > small wa_tail such that on the next submission, the ring->tail will > appear to move forwards when resubmitting the same request. This is very > common as it will happen for every lite-restore to fill the second port > after a context switch. > > However, intel_ring_direction() is limited in precision to movements of > upto half the ring size. The consequence being that if we tried to > unwind many requests, we could exceed half the ring and flip the sense > of the direction, so missing a force restore. As no request can be > greater than half the ring (i.e. 2048 bytes in the smallest case), we > can check for rollback incrementally. As we check against the tail that > would be submitted, we do not lose any sensitivity and allow lite > restores for the simple case. We still need to double check upon > submitting the context, to allow for multiple preemptions and > resubmissions. > > Fixes: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: <stable at vger.kernel.org> # v5.4+ > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++- > drivers/gpu/drm/i915/gt/intel_ring.c | 4 + > drivers/gpu/drm/i915/gt/selftest_mocs.c | 18 ++- > drivers/gpu/drm/i915/gt/selftest_ring.c | 110 ++++++++++++++++++ > .../drm/i915/selftests/i915_mock_selftests.h | 1 + > 6 files changed, 154 insertions(+), 4 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/selftest_ring.c > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index e5141a897786..0a05301e00fb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -646,7 +646,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) > struct measure_breadcrumb { > struct i915_request rq; > struct intel_ring ring; > - u32 cs[1024]; > + u32 cs[2048]; > }; > > static int measure_breadcrumb_dw(struct intel_context *ce) > @@ -667,6 +667,8 @@ static int measure_breadcrumb_dw(struct intel_context *ce) > > frame->ring.vaddr = frame->cs; > frame->ring.size = sizeof(frame->cs); > + frame->ring.wrap = > + BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); > frame->ring.effective_size = frame->ring.size; > intel_ring_update_space(&frame->ring); > frame->rq.ring = &frame->ring; > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index a057f7a2a521..f66274e60bb6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1137,6 +1137,13 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) > list_move(&rq->sched.link, pl); > set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); > > + /* Check for rollback incrementally */ > + if (intel_ring_direction(rq->ring, > + intel_ring_wrap(rq->ring, > + rq->tail), > + rq->ring->tail) <= 0) > + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; We could be a bit more cheeky in that the problem only occurs if we rollback far enough that there is a danger is mistaking the rollback for a forward update. -Chris From ville.syrjala at linux.intel.com Tue Jun 9 15:15:41 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 9 Jun 2020 18:15:41 +0300 Subject: [Intel-gfx] [PATCH v4 4/7] drm/i915/rkl: Don't try to read out DSI transcoders In-Reply-To: <20200606025740.3308880-5-matthew.d.roper@intel.com> References: <20200606025740.3308880-1-matthew.d.roper@intel.com> <20200606025740.3308880-5-matthew.d.roper@intel.com> Message-ID: <20200609151541.GS6112@intel.com> On Fri, Jun 05, 2020 at 07:57:37PM -0700, Matt Roper wrote: > From: Aditya Swarup <aditya.swarup at intel.com> > > RKL doesn't have DSI outputs, so we shouldn't try to read out the DSI > transcoder registers. > > v2(MattR): > - Just set the 'extra panel mask' to edp | dsi0 | dsi1 and then mask > against the platform's cpu_transcoder_mask to filter out the ones > that don't exist on a given platform. (Ville) > > v3(MattR): > - Only include DSI transcoders on gen11+ again. (Ville) > - Use for_each_cpu_transcoder_masked() for loop. (Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 10 +++------- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 9820874d3ea2..6c2bb3354b86 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -10904,7 +10904,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > enum intel_display_power_domain power_domain; > - unsigned long panel_transcoder_mask = 0; > + unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP); > unsigned long enabled_panel_transcoders = 0; Could get rid of the longs now that we're no longer using for_each_set_bit() Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > enum transcoder panel_transcoder; > intel_wakeref_t wf; > @@ -10914,9 +10914,6 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, > panel_transcoder_mask |= > BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); > > - if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP)) > - panel_transcoder_mask |= BIT(TRANSCODER_EDP); > - > /* > * The pipe->transcoder mapping is fixed with the exception of the eDP > * and DSI transcoders handled below. > @@ -10927,9 +10924,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, > * XXX: Do intel_display_power_get_if_enabled before reading this (for > * consistency and less surprising code; it's in always on power). > */ > - for_each_set_bit(panel_transcoder, > - &panel_transcoder_mask, > - ARRAY_SIZE(INTEL_INFO(dev_priv)->trans_offsets)) { > + for_each_cpu_transcoder_masked(dev_priv, panel_transcoder, > + panel_transcoder_mask) { > bool force_thru = false; > enum pipe trans_pipe; > > -- > 2.24.1 -- Ville Syrj?l? Intel From chris at chris-wilson.co.uk Tue Jun 9 15:17:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 9 Jun 2020 16:17:23 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Incrementally check for rewinding In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <20200609151723.12971-1-chris@chris-wilson.co.uk> In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL"), we placed the check for rewinding a context on actually submitting the next request in that context. This was so that we only had to check once, and could do so with precision avoiding as many forced restores as possible. For example, to ensure that we can resubmit the same request a couple of times, we include a small wa_tail such that on the next submission, the ring->tail will appear to move forwards when resubmitting the same request. This is very common as it will happen for every lite-restore to fill the second port after a context switch. However, intel_ring_direction() is limited in precision to movements of upto half the ring size. The consequence being that if we tried to unwind many requests, we could exceed half the ring and flip the sense of the direction, so missing a force restore. As no request can be greater than half the ring (i.e. 2048 bytes in the smallest case), we can check for rollback incrementally. As we check against the tail that would be submitted, we do not lose any sensitivity and allow lite restores for the simple case. We still need to double check upon submitting the context, to allow for multiple preemptions and resubmissions. Fixes: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: <stable at vger.kernel.org> # v5.4+ --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++- drivers/gpu/drm/i915/gt/intel_ring.c | 4 + drivers/gpu/drm/i915/gt/selftest_mocs.c | 18 ++- drivers/gpu/drm/i915/gt/selftest_ring.c | 110 ++++++++++++++++++ .../drm/i915/selftests/i915_mock_selftests.h | 1 + 6 files changed, 154 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_ring.c diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index e5141a897786..0a05301e00fb 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -646,7 +646,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) struct measure_breadcrumb { struct i915_request rq; struct intel_ring ring; - u32 cs[1024]; + u32 cs[2048]; }; static int measure_breadcrumb_dw(struct intel_context *ce) @@ -667,6 +667,8 @@ static int measure_breadcrumb_dw(struct intel_context *ce) frame->ring.vaddr = frame->cs; frame->ring.size = sizeof(frame->cs); + frame->ring.wrap = + BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); frame->ring.effective_size = frame->ring.size; intel_ring_update_space(&frame->ring); frame->rq.ring = &frame->ring; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index a057f7a2a521..5f33342c15e2 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1137,6 +1137,13 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) list_move(&rq->sched.link, pl); set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + /* Check in case rollback so far, we wrap [size/2] */ + if (intel_ring_direction(rq->ring, + intel_ring_wrap(rq->ring, + rq->tail), + rq->ring->tail) > 0) + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; + active = rq; } else { struct intel_engine_cs *owner = rq->context->engine; @@ -1505,8 +1512,9 @@ static u64 execlists_update_context(struct i915_request *rq) * HW has a tendency to ignore us rewinding the TAIL to the end of * an earlier request. */ + GEM_BUG_ON(ce->lrc_reg_state[CTX_RING_TAIL] != rq->ring->tail); + prev = rq->ring->tail; tail = intel_ring_set_tail(rq->ring, rq->tail); - prev = ce->lrc_reg_state[CTX_RING_TAIL]; if (unlikely(intel_ring_direction(rq->ring, tail, prev) <= 0)) desc |= CTX_DESC_FORCE_RESTORE; ce->lrc_reg_state[CTX_RING_TAIL] = tail; @@ -4758,6 +4766,14 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode) return 0; } +static void assert_request_valid(struct i915_request *rq) +{ + struct intel_ring *ring __maybe_unused = rq->ring; + + /* Can we unwind this request without appearing to go forwards? */ + GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0); +} + /* * Reserve space for 2 NOOPs at the end of each request to be * used as a workaround for not being allowed to do lite @@ -4770,6 +4786,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) *cs++ = MI_NOOP; request->wa_tail = intel_ring_offset(request, cs); + /* Check that entire request is less than half the ring */ + assert_request_valid(request); + return cs; } diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index 8cda1b7e17ba..bdb324167ef3 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -315,3 +315,7 @@ int intel_ring_cacheline_align(struct i915_request *rq) GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); return 0; } + +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) +#include "selftest_ring.c" +#endif diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index 7bae64018ad9..b25eba50c88e 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -18,6 +18,20 @@ struct live_mocs { void *vaddr; }; +static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) +{ + struct intel_context *ce; + + ce = intel_context_create(engine); + if (IS_ERR(ce)) + return ce; + + /* We build large requests to read the registers from the ring */ + ce->ring = __intel_context_ring_size(SZ_16K); + + return ce; +} + static int request_add_sync(struct i915_request *rq, int err) { i915_request_get(rq); @@ -301,7 +315,7 @@ static int live_mocs_clean(void *arg) for_each_engine(engine, gt, id) { struct intel_context *ce; - ce = intel_context_create(engine); + ce = mocs_context_create(engine); if (IS_ERR(ce)) { err = PTR_ERR(ce); break; @@ -395,7 +409,7 @@ static int live_mocs_reset(void *arg) for_each_engine(engine, gt, id) { struct intel_context *ce; - ce = intel_context_create(engine); + ce = mocs_context_create(engine); if (IS_ERR(ce)) { err = PTR_ERR(ce); break; diff --git a/drivers/gpu/drm/i915/gt/selftest_ring.c b/drivers/gpu/drm/i915/gt/selftest_ring.c new file mode 100644 index 000000000000..2a8c534dc125 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/selftest_ring.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright ? 2020 Intel Corporation + */ + +static struct intel_ring *mock_ring(unsigned long sz) +{ + struct intel_ring *ring; + + ring = kzalloc(sizeof(*ring) + sz, GFP_KERNEL); + if (!ring) + return NULL; + + kref_init(&ring->ref); + ring->size = sz; + ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(sz); + ring->effective_size = sz; + ring->vaddr = (void *)(ring + 1); + atomic_set(&ring->pin_count, 1); + + intel_ring_update_space(ring); + + return ring; +} + +static void mock_ring_free(struct intel_ring *ring) +{ + kfree(ring); +} + +static int check_ring_direction(struct intel_ring *ring, + u32 next, u32 prev, + int expected) +{ + int result; + + result = intel_ring_direction(ring, next, prev); + if (result < 0) + result = -1; + else if (result > 0) + result = 1; + + if (result != expected) { + pr_err("intel_ring_direction(%u, %u):%d != %d\n", + next, prev, result, expected); + return -EINVAL; + } + + return 0; +} + +static int check_ring_step(struct intel_ring *ring, u32 x, u32 step) +{ + u32 prev = x, next = intel_ring_wrap(ring, x + step); + int err = 0; + + err |= check_ring_direction(ring, next, next, 0); + err |= check_ring_direction(ring, prev, prev, 0); + err |= check_ring_direction(ring, next, prev, 1); + err |= check_ring_direction(ring, prev, next, -1); + + return err; +} + +static int check_ring_offset(struct intel_ring *ring, u32 x, u32 step) +{ + int err = 0; + + err |= check_ring_step(ring, x, step); + err |= check_ring_step(ring, intel_ring_wrap(ring, x + 1), step); + err |= check_ring_step(ring, intel_ring_wrap(ring, x - 1), step); + + return err; +} + +static int igt_ring_direction(void *dummy) +{ + struct intel_ring *ring; + unsigned int half = 2048; + int step, err = 0; + + ring = mock_ring(2 * half); + if (!ring) + return -ENOMEM; + + GEM_BUG_ON(ring->size != 2 * half); + + /* Precision of wrap detection is limited to ring->size / 2 */ + for (step = 1; step < half; step <<= 1) { + err |= check_ring_offset(ring, 0, step); + err |= check_ring_offset(ring, half, step); + } + err |= check_ring_step(ring, 0, half - 64); + + /* And check unwrapped handling for good measure */ + err |= check_ring_offset(ring, 0, 2 * half + 64); + err |= check_ring_offset(ring, 3 * half, 1); + + mock_ring_free(ring); + return err; +} + +int intel_ring_mock_selftests(void) +{ + static const struct i915_subtest tests[] = { + SUBTEST(igt_ring_direction), + }; + + return i915_subtests(tests, NULL); +} diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h index 1929feba4e8e..3db34d3eea58 100644 --- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h +++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h @@ -21,6 +21,7 @@ selftest(fence, i915_sw_fence_mock_selftests) selftest(scatterlist, scatterlist_mock_selftests) selftest(syncmap, i915_syncmap_mock_selftests) selftest(uncore, intel_uncore_mock_selftests) +selftest(ring, intel_ring_mock_selftests) selftest(engine, intel_engine_cs_mock_selftests) selftest(timelines, intel_timeline_mock_selftests) selftest(requests, i915_request_mock_selftests) -- 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 9 15:37:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 15:37:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gt=3A_Incrementally_check_for_rewinding_=28rev2=29?= In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <159171703081.17061.2360080513485287241@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Incrementally check for rewinding (rev2) URL : https://patchwork.freedesktop.org/series/78163/ State : warning == Summary == $ dim checkpatch origin/drm-tip 729184acbb94 drm/i915/gt: Incrementally check for rewinding -:165: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #165: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 222 lines checked From lyude at redhat.com Tue Jun 9 15:58:18 2020 From: lyude at redhat.com (Lyude Paul) Date: Tue, 09 Jun 2020 11:58:18 -0400 Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <20200609121556.GF22647@ideak-desk.fi.intel.com> References: <20200603211040.8190-3-imre.deak@intel.com> <20200604184500.23730-2-imre.deak@intel.com> <20200609121556.GF22647@ideak-desk.fi.intel.com> Message-ID: <3ac3e3d05dab3ebb83023e35bb0f5c5b15b0fbd6.camel@redhat.com> Hi! Awesome patch series! Reviewed-by: Lyude Paul <lyude at redhat.com> Also re merging via drm-intel-next-queued - I think that should be fine, fwiw merging via drm-misc-next might be another option (I've definitely done this in the past for series that touched MST and drivers, but I don't have a hard preference either way). On Tue, 2020-06-09 at 15:15 +0300, Imre Deak wrote: > Hi Dave, Lyude, > > are you ok to merge this patchset via the drm-intel-next-queued tree? > > --Imre > > On Thu, Jun 04, 2020 at 09:45:00PM +0300, Imre Deak wrote: > > Some TypeC -> native DP adapters, at least the Club 3D CAC-1557 adapter, > > incorrectly filter out HPD short pulses with a duration less than > > ~540 usec, leading to MST probe failures. > > > > According to the DP Standard 2.0 section 5.1.4: > > - DP sinks should generate short pulses in the 500 usec -> 1 msec range > > - DP sources should detect short pulses in the 250 usec -> 2 msec range > > > > According to the DP Alt Mode on TypeC Standard section 3.9.2, adapters > > should detect and forward short pulses according to how sources should > > detect them as specified in the DP Standard (250 usec -> 2 msec). > > > > Based on the above filtering out short pulses with a duration less than > > 540 usec is incorrect. > > > > To make such adapters work add support for a driver polling on MST > > inerrupt flags, and wire this up in the i915 driver. The sink can clear > > an interrupt it raised after 110 msec if the source doesn't respond, so > > use a 50 msec poll period to avoid missing an interrupt. Polling of the > > MST interrupt flags is explicitly allowed by the DP Standard. > > > > This fixes MST probe failures I saw using this adapter and a DELL U2515H > > monitor. > > > > v2: > > - Fix the wait event timeout for the no-poll case. > > v3 (Ville): > > - Fix the short pulse duration limits in the commit log prescribed by the > > DP Standard. > > - Add code comment explaining why/how polling is used. > > - Factor out a helper to schedule the port's hpd irq handler and move it > > to the rest of hotplug handlers. > > - Document the new MST callback. > > - s/update_hpd_irq_state/poll_hpd_irq/ > > > > Cc: Ville Syrj????l???? <ville.syrjala at linux.intel.com> > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 32 ++++++++++++++++++-- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++ > > drivers/gpu/drm/i915/display/intel_hotplug.c | 18 +++++++++++ > > drivers/gpu/drm/i915/display/intel_hotplug.h | 2 ++ > > include/drm/drm_dp_mst_helper.h | 9 ++++++ > > 5 files changed, 68 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > > b/drivers/gpu/drm/drm_dp_mst_topology.c > > index 5bc72e800b85..2a309fb2c4cc 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -1178,11 +1178,37 @@ static int drm_dp_mst_wait_tx_reply(struct > > drm_dp_mst_branch *mstb, > > struct drm_dp_sideband_msg_tx *txmsg) > > { > > struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; > > + unsigned long wait_timeout = msecs_to_jiffies(4000); > > + unsigned long wait_expires = jiffies + wait_timeout; > > int ret; > > > > - ret = wait_event_timeout(mgr->tx_waitq, > > - check_txmsg_state(mgr, txmsg), > > - (4 * HZ)); > > + for (;;) { > > + /* > > + * If the driver provides a way for this, change to > > + * poll-waiting for the MST reply interrupt if we didn't receive > > + * it for 50 msec. This would cater for cases where the HPD > > + * pulse signal got lost somewhere, even though the sink raised > > + * the corresponding MST interrupt correctly. One example is the > > + * Club 3D CAC-1557 TypeC -> DP adapter which for some reason > > + * filters out short pulses with a duration less than ~540 usec. > > + * > > + * The poll period is 50 msec to avoid missing an interrupt > > + * after the sink has cleared it (after a 110msec timeout > > + * since it raised the interrupt). > > + */ > > + ret = wait_event_timeout(mgr->tx_waitq, > > + check_txmsg_state(mgr, txmsg), > > + mgr->cbs->poll_hpd_irq ? > > + msecs_to_jiffies(50) : > > + wait_timeout); > > + > > + if (ret || !mgr->cbs->poll_hpd_irq || > > + time_after(jiffies, wait_expires)) > > + break; > > + > > + mgr->cbs->poll_hpd_irq(mgr); > > + } > > + > > mutex_lock(&mgr->qlock); > > if (ret > 0) { > > if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index d18b406f2a7d..9be52643205d 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -33,6 +33,7 @@ > > #include "intel_connector.h" > > #include "intel_ddi.h" > > #include "intel_display_types.h" > > +#include "intel_hotplug.h" > > #include "intel_dp.h" > > #include "intel_dp_mst.h" > > #include "intel_dpio_phy.h" > > @@ -765,8 +766,17 @@ static struct drm_connector > > *intel_dp_add_mst_connector(struct drm_dp_mst_topolo > > return NULL; > > } > > > > +static void > > +intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) > > +{ > > + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); > > + > > + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); > > +} > > + > > static const struct drm_dp_mst_topology_cbs mst_cbs = { > > .add_connector = intel_dp_add_mst_connector, > > + .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, > > }; > > > > static struct intel_dp_mst_encoder * > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c > > b/drivers/gpu/drm/i915/display/intel_hotplug.c > > index 4f6f560e093e..664f88354101 100644 > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c > > @@ -347,6 +347,24 @@ static void i915_digport_work_func(struct work_struct > > *work) > > } > > } > > > > +/** > > + * intel_hpd_trigger_irq - trigger an hpd irq event for a port > > + * @dig_port: digital port > > + * > > + * Trigger an HPD interrupt event for the given port, emulating a short > > pulse > > + * generated by the sink, and schedule the dig port work to handle it. > > + */ > > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port) > > +{ > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > + > > + spin_lock_irq(&i915->irq_lock); > > + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); > > + spin_unlock_irq(&i915->irq_lock); > > + > > + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); > > +} > > + > > /* > > * Handle hotplug events outside the interrupt handler proper. > > */ > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h > > b/drivers/gpu/drm/i915/display/intel_hotplug.h > > index 777b0743257e..a704d7c94d16 100644 > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.h > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h > > @@ -10,6 +10,7 @@ > > > > struct drm_i915_private; > > struct intel_connector; > > +struct intel_digital_port; > > struct intel_encoder; > > enum port; > > > > @@ -18,6 +19,7 @@ enum intel_hotplug_state intel_encoder_hotplug(struct > > intel_encoder *encoder, > > struct intel_connector > > *connector); > > void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, > > u32 pin_mask, u32 long_mask); > > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port); > > void intel_hpd_init(struct drm_i915_private *dev_priv); > > void intel_hpd_init_work(struct drm_i915_private *dev_priv); > > void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); > > diff --git a/include/drm/drm_dp_mst_helper.h > > b/include/drm/drm_dp_mst_helper.h > > index 9e1ffcd7cb68..b230ff6f7081 100644 > > --- a/include/drm/drm_dp_mst_helper.h > > +++ b/include/drm/drm_dp_mst_helper.h > > @@ -475,6 +475,15 @@ struct drm_dp_mst_topology_mgr; > > struct drm_dp_mst_topology_cbs { > > /* create a connector for a port */ > > struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr > > *mgr, struct drm_dp_mst_port *port, const char *path); > > + /* > > + * Checks for any pending MST interrupts, passing them to MST core for > > + * processing, the same way an HPD IRQ pulse handler would do this. > > + * If provided MST core calls this callback from a poll-waiting loop > > + * when waiting for MST down message replies. The driver is expected > > + * to guard against a race between this callback and the driver's HPD > > + * IRQ pulse handler. > > + */ > > + void (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *mgr); > > }; > > > > #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) > > -- > > 2.23.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Tue Jun 9 15:58:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 15:58:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Incrementally_check_for_rewinding_=28rev2=29?= In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <159171832168.17061.13972587822906054794@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Incrementally check for rewinding (rev2) URL : https://patchwork.freedesktop.org/series/78163/ State : success == Summary == CI Bug Log - changes from CI_DRM_8603 -> Patchwork_17915 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/index.html Known issues ------------ Here are the changes found in Patchwork_17915 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/fi-icl-guc/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/fi-icl-guc/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][5] -> [DMESG-WARN][6] ([i915#62] / [i915#92] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * igt at kms_flip@basic-flip-vs-dpms at d-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-dpms at d-dsi1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-dpms at d-dsi1.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8603 -> Patchwork_17915 CI-20190529: 20190529 CI_DRM_8603: 03f5a3d90ccfb2f1bb13e293a83d48a0b7da8af0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17915: 729184acbb949babd103b9a1ae59de9a6c4918b1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 729184acbb94 drm/i915/gt: Incrementally check for rewinding == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/index.html From nirmodas at amd.com Mon Jun 8 16:42:01 2020 From: nirmodas at amd.com (Nirmoy) Date: Mon, 8 Jun 2020 18:42:01 +0200 Subject: [Intel-gfx] [PATCH] drm/mm: remove invalid entry based optimization In-Reply-To: <20200608151550.1315-1-christian.koenig@amd.com> References: <20200608151550.1315-1-christian.koenig@amd.com> Message-ID: <58d0d2cf-5365-d5e5-3338-dcd6c7b3a786@amd.com> On 6/8/20 5:15 PM, Christian K?nig wrote: > When the current entry is rejected as candidate for the search > it does not mean that we can abort the subtree search. > > It is perfectly possible that only the alignment, but not the > size is the reason for the rejection. I know why I? did that, I was testing with 8k alignment. So this was biased to optimize my test case. > > Signed-off-by: Christian K?nig <christian.koenig at amd.com> Reviewed-by: Nirmoy Das <nirmoy.das at amd.com> > --- > drivers/gpu/drm/drm_mm.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c > index 60e9a9c91e9d..82d2888eb7fe 100644 > --- a/drivers/gpu/drm/drm_mm.c > +++ b/drivers/gpu/drm/drm_mm.c > @@ -406,8 +406,7 @@ next_hole_high_addr(struct drm_mm_node *entry, u64 size) > parent_rb_node = rb_parent(rb_node); > left_node = rb_entry(left_rb_node, > struct drm_mm_node, rb_hole_addr); > - if ((left_node->subtree_max_hole < size || > - HOLE_SIZE(entry) == entry->subtree_max_hole) && > + if (left_node->subtree_max_hole < size && > parent_rb_node && parent_rb_node->rb_left != rb_node) > return rb_hole_addr_to_node(parent_rb_node); > } > @@ -446,8 +445,7 @@ next_hole_low_addr(struct drm_mm_node *entry, u64 size) > parent_rb_node = rb_parent(rb_node); > right_node = rb_entry(right_rb_node, > struct drm_mm_node, rb_hole_addr); > - if ((right_node->subtree_max_hole < size || > - HOLE_SIZE(entry) == entry->subtree_max_hole) && > + if (right_node->subtree_max_hole < size && > parent_rb_node && parent_rb_node->rb_right != rb_node) > return rb_hole_addr_to_node(parent_rb_node); > } From imre.deak at intel.com Tue Jun 9 17:40:35 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 9 Jun 2020 20:40:35 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200609150525.GP6112@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> <20200609150525.GP6112@intel.com> Message-ID: <20200609174035.GG22647@ideak-desk.fi.intel.com> On Tue, Jun 09, 2020 at 06:05:25PM +0300, Ville Syrj?l? wrote: > On Mon, Jun 08, 2020 at 09:10:23PM +0300, Imre Deak wrote: > > DSC is not supported on DP MST streams so just return -EINVAL when > > reading/writing the i915_dsc_fec_support debugfs file for such > > connectors. > > > > This also fixes an OOPS, caused by the encoder->digport cast, which is > > not valid for MST encoders. > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- > > 1 file changed, 29 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > index 2b640d8ab9d2..ebca8e488d03 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); > > > > do { > > + struct intel_encoder *encoder; > > + > > try_again = false; > > ret = drm_modeset_lock(&dev->mode_config.connection_mutex, > > &ctx); > > @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > } else if (ret) { > > break; > > } > > - intel_dp = intel_attached_dp(to_intel_connector(connector)); > > + > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > + /* TODO: Add DSC support for MST streams */ > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > + ret = -EINVAL; > > + break; > > + } > > + > > + intel_dp = &enc_to_dig_port(encoder)->dp; > > crtc_state = to_intel_crtc_state(crtc->state); > > + > > seq_printf(m, "DSC_Enabled: %s\n", > > yesno(crtc_state->dsc.compression_enable)); > > seq_printf(m, "DSC_Sink_Support: %s\n", > > @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > int ret; > > struct drm_connector *connector = > > ((struct seq_file *)file->private_data)->private; > > - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); > > - struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > + struct drm_i915_private *i915 = to_i915(connector->dev); > > + struct intel_encoder *encoder; > > > > if (len == 0) > > return 0; > > @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > drm_dbg(&i915->drm, "Got %s for DSC Enable\n", > > (dsc_enable) ? "true" : "false"); > > - intel_dp->force_dsc_en = dsc_enable; > > > > - *offp += len; > > - return len; > > + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); > > + > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > + /* TODO: Add DSC support for MST streams */ > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > The attached encoder can be NULL for MST. Yes, I also sent v2 with that fixed. > Can't we just not add this debugfs file for MST connectors? Won't we have per MST connector DSC at one point? In that case we'd need something like this anyway. If this is never needed then yes, better not to add it. I can't use connector_type which is the same for MST and SST connectors so is it ok to differentiate based on a intel_attached_encoder() == NULL check? > > > + ret = -EINVAL; > > + } else { > > + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; > > + *offp += len; > > + ret = len; > > + } > > + > > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); > > + > > + return ret; > > } > > > > static int i915_dsc_fec_support_open(struct inode *inode, > > -- > > 2.23.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Tue Jun 9 17:59:23 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 9 Jun 2020 20:59:23 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200609174035.GG22647@ideak-desk.fi.intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> <20200609150525.GP6112@intel.com> <20200609174035.GG22647@ideak-desk.fi.intel.com> Message-ID: <20200609175923.GU6112@intel.com> On Tue, Jun 09, 2020 at 08:40:35PM +0300, Imre Deak wrote: > On Tue, Jun 09, 2020 at 06:05:25PM +0300, Ville Syrj?l? wrote: > > On Mon, Jun 08, 2020 at 09:10:23PM +0300, Imre Deak wrote: > > > DSC is not supported on DP MST streams so just return -EINVAL when > > > reading/writing the i915_dsc_fec_support debugfs file for such > > > connectors. > > > > > > This also fixes an OOPS, caused by the encoder->digport cast, which is > > > not valid for MST encoders. > > > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > --- > > > .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- > > > 1 file changed, 29 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > index 2b640d8ab9d2..ebca8e488d03 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); > > > > > > do { > > > + struct intel_encoder *encoder; > > > + > > > try_again = false; > > > ret = drm_modeset_lock(&dev->mode_config.connection_mutex, > > > &ctx); > > > @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > } else if (ret) { > > > break; > > > } > > > - intel_dp = intel_attached_dp(to_intel_connector(connector)); > > > + > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > + /* TODO: Add DSC support for MST streams */ > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > > + ret = -EINVAL; > > > + break; > > > + } > > > + > > > + intel_dp = &enc_to_dig_port(encoder)->dp; > > > crtc_state = to_intel_crtc_state(crtc->state); > > > + > > > seq_printf(m, "DSC_Enabled: %s\n", > > > yesno(crtc_state->dsc.compression_enable)); > > > seq_printf(m, "DSC_Sink_Support: %s\n", > > > @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > int ret; > > > struct drm_connector *connector = > > > ((struct seq_file *)file->private_data)->private; > > > - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); > > > - struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > + struct drm_i915_private *i915 = to_i915(connector->dev); > > > + struct intel_encoder *encoder; > > > > > > if (len == 0) > > > return 0; > > > @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > > > drm_dbg(&i915->drm, "Got %s for DSC Enable\n", > > > (dsc_enable) ? "true" : "false"); > > > - intel_dp->force_dsc_en = dsc_enable; > > > > > > - *offp += len; > > > - return len; > > > + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); > > > + > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > + /* TODO: Add DSC support for MST streams */ > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > > > The attached encoder can be NULL for MST. > > Yes, I also sent v2 with that fixed. > > > Can't we just not add this debugfs file for MST connectors? > > Won't we have per MST connector DSC at one point? In that case we'd need > something like this anyway. The problem is that it doesn't work until the encoder has been attached. So the behaviour of the interface would be rather inconsistent when applied to MST connectors. No idea what current tests are doing with this stuff so can't say whether it would be a problem in practice. > If this is never needed then yes, better not > to add it. I can't use connector_type which is the same for MST and SST > connectors so is it ok to differentiate based on a > intel_attached_encoder() == NULL check? IIRC some other places use connector.mst_port to tell the two apart. > > > > > > + ret = -EINVAL; > > > + } else { > > > + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; > > > + *offp += len; > > > + ret = len; > > > + } > > > + > > > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); > > > + > > > + return ret; > > > } > > > > > > static int i915_dsc_fec_support_open(struct inode *inode, > > > -- > > > 2.23.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From imre.deak at intel.com Tue Jun 9 18:03:51 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 9 Jun 2020 21:03:51 +0300 Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses In-Reply-To: <3ac3e3d05dab3ebb83023e35bb0f5c5b15b0fbd6.camel@redhat.com> References: <20200603211040.8190-3-imre.deak@intel.com> <20200604184500.23730-2-imre.deak@intel.com> <20200609121556.GF22647@ideak-desk.fi.intel.com> <3ac3e3d05dab3ebb83023e35bb0f5c5b15b0fbd6.camel@redhat.com> Message-ID: <20200609180351.GH22647@ideak-desk.fi.intel.com> On Tue, Jun 09, 2020 at 11:58:18AM -0400, Lyude Paul wrote: > Hi! Awesome patch series! > > Reviewed-by: Lyude Paul <lyude at redhat.com> Thanks. > Also re merging via drm-intel-next-queued - I think that should be fine, fwiw > merging via drm-misc-next might be another option (I've definitely done this in > the past for series that touched MST and drivers, but I don't have a hard > preference either way). Ok, if no objections I'll merge 2/3 via drm-misc-next, that seems to make more sense. Could you also take a look at https://patchwork.freedesktop.org/series/78100/ I should've CC'd you. > On Tue, 2020-06-09 at 15:15 +0300, Imre Deak wrote: > > Hi Dave, Lyude, > > > > are you ok to merge this patchset via the drm-intel-next-queued tree? > > > > --Imre > > > > On Thu, Jun 04, 2020 at 09:45:00PM +0300, Imre Deak wrote: > > > Some TypeC -> native DP adapters, at least the Club 3D CAC-1557 adapter, > > > incorrectly filter out HPD short pulses with a duration less than > > > ~540 usec, leading to MST probe failures. > > > > > > According to the DP Standard 2.0 section 5.1.4: > > > - DP sinks should generate short pulses in the 500 usec -> 1 msec range > > > - DP sources should detect short pulses in the 250 usec -> 2 msec range > > > > > > According to the DP Alt Mode on TypeC Standard section 3.9.2, adapters > > > should detect and forward short pulses according to how sources should > > > detect them as specified in the DP Standard (250 usec -> 2 msec). > > > > > > Based on the above filtering out short pulses with a duration less than > > > 540 usec is incorrect. > > > > > > To make such adapters work add support for a driver polling on MST > > > inerrupt flags, and wire this up in the i915 driver. The sink can clear > > > an interrupt it raised after 110 msec if the source doesn't respond, so > > > use a 50 msec poll period to avoid missing an interrupt. Polling of the > > > MST interrupt flags is explicitly allowed by the DP Standard. > > > > > > This fixes MST probe failures I saw using this adapter and a DELL U2515H > > > monitor. > > > > > > v2: > > > - Fix the wait event timeout for the no-poll case. > > > v3 (Ville): > > > - Fix the short pulse duration limits in the commit log prescribed by the > > > DP Standard. > > > - Add code comment explaining why/how polling is used. > > > - Factor out a helper to schedule the port's hpd irq handler and move it > > > to the rest of hotplug handlers. > > > - Document the new MST callback. > > > - s/update_hpd_irq_state/poll_hpd_irq/ > > > > > > Cc: Ville Syrj????l???? <ville.syrjala at linux.intel.com> > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > --- > > > drivers/gpu/drm/drm_dp_mst_topology.c | 32 ++++++++++++++++++-- > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++ > > > drivers/gpu/drm/i915/display/intel_hotplug.c | 18 +++++++++++ > > > drivers/gpu/drm/i915/display/intel_hotplug.h | 2 ++ > > > include/drm/drm_dp_mst_helper.h | 9 ++++++ > > > 5 files changed, 68 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > > > b/drivers/gpu/drm/drm_dp_mst_topology.c > > > index 5bc72e800b85..2a309fb2c4cc 100644 > > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > > @@ -1178,11 +1178,37 @@ static int drm_dp_mst_wait_tx_reply(struct > > > drm_dp_mst_branch *mstb, > > > struct drm_dp_sideband_msg_tx *txmsg) > > > { > > > struct drm_dp_mst_topology_mgr *mgr = mstb->mgr; > > > + unsigned long wait_timeout = msecs_to_jiffies(4000); > > > + unsigned long wait_expires = jiffies + wait_timeout; > > > int ret; > > > > > > - ret = wait_event_timeout(mgr->tx_waitq, > > > - check_txmsg_state(mgr, txmsg), > > > - (4 * HZ)); > > > + for (;;) { > > > + /* > > > + * If the driver provides a way for this, change to > > > + * poll-waiting for the MST reply interrupt if we didn't receive > > > + * it for 50 msec. This would cater for cases where the HPD > > > + * pulse signal got lost somewhere, even though the sink raised > > > + * the corresponding MST interrupt correctly. One example is the > > > + * Club 3D CAC-1557 TypeC -> DP adapter which for some reason > > > + * filters out short pulses with a duration less than ~540 usec. > > > + * > > > + * The poll period is 50 msec to avoid missing an interrupt > > > + * after the sink has cleared it (after a 110msec timeout > > > + * since it raised the interrupt). > > > + */ > > > + ret = wait_event_timeout(mgr->tx_waitq, > > > + check_txmsg_state(mgr, txmsg), > > > + mgr->cbs->poll_hpd_irq ? > > > + msecs_to_jiffies(50) : > > > + wait_timeout); > > > + > > > + if (ret || !mgr->cbs->poll_hpd_irq || > > > + time_after(jiffies, wait_expires)) > > > + break; > > > + > > > + mgr->cbs->poll_hpd_irq(mgr); > > > + } > > > + > > > mutex_lock(&mgr->qlock); > > > if (ret > 0) { > > > if (txmsg->state == DRM_DP_SIDEBAND_TX_TIMEOUT) { > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > index d18b406f2a7d..9be52643205d 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > @@ -33,6 +33,7 @@ > > > #include "intel_connector.h" > > > #include "intel_ddi.h" > > > #include "intel_display_types.h" > > > +#include "intel_hotplug.h" > > > #include "intel_dp.h" > > > #include "intel_dp_mst.h" > > > #include "intel_dpio_phy.h" > > > @@ -765,8 +766,17 @@ static struct drm_connector > > > *intel_dp_add_mst_connector(struct drm_dp_mst_topolo > > > return NULL; > > > } > > > > > > +static void > > > +intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) > > > +{ > > > + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); > > > + > > > + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); > > > +} > > > + > > > static const struct drm_dp_mst_topology_cbs mst_cbs = { > > > .add_connector = intel_dp_add_mst_connector, > > > + .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, > > > }; > > > > > > static struct intel_dp_mst_encoder * > > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c > > > b/drivers/gpu/drm/i915/display/intel_hotplug.c > > > index 4f6f560e093e..664f88354101 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c > > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c > > > @@ -347,6 +347,24 @@ static void i915_digport_work_func(struct work_struct > > > *work) > > > } > > > } > > > > > > +/** > > > + * intel_hpd_trigger_irq - trigger an hpd irq event for a port > > > + * @dig_port: digital port > > > + * > > > + * Trigger an HPD interrupt event for the given port, emulating a short > > > pulse > > > + * generated by the sink, and schedule the dig port work to handle it. > > > + */ > > > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port) > > > +{ > > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > > + > > > + spin_lock_irq(&i915->irq_lock); > > > + i915->hotplug.short_port_mask |= BIT(dig_port->base.port); > > > + spin_unlock_irq(&i915->irq_lock); > > > + > > > + queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work); > > > +} > > > + > > > /* > > > * Handle hotplug events outside the interrupt handler proper. > > > */ > > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h > > > b/drivers/gpu/drm/i915/display/intel_hotplug.h > > > index 777b0743257e..a704d7c94d16 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.h > > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h > > > @@ -10,6 +10,7 @@ > > > > > > struct drm_i915_private; > > > struct intel_connector; > > > +struct intel_digital_port; > > > struct intel_encoder; > > > enum port; > > > > > > @@ -18,6 +19,7 @@ enum intel_hotplug_state intel_encoder_hotplug(struct > > > intel_encoder *encoder, > > > struct intel_connector > > > *connector); > > > void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, > > > u32 pin_mask, u32 long_mask); > > > +void intel_hpd_trigger_irq(struct intel_digital_port *dig_port); > > > void intel_hpd_init(struct drm_i915_private *dev_priv); > > > void intel_hpd_init_work(struct drm_i915_private *dev_priv); > > > void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); > > > diff --git a/include/drm/drm_dp_mst_helper.h > > > b/include/drm/drm_dp_mst_helper.h > > > index 9e1ffcd7cb68..b230ff6f7081 100644 > > > --- a/include/drm/drm_dp_mst_helper.h > > > +++ b/include/drm/drm_dp_mst_helper.h > > > @@ -475,6 +475,15 @@ struct drm_dp_mst_topology_mgr; > > > struct drm_dp_mst_topology_cbs { > > > /* create a connector for a port */ > > > struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr > > > *mgr, struct drm_dp_mst_port *port, const char *path); > > > + /* > > > + * Checks for any pending MST interrupts, passing them to MST core for > > > + * processing, the same way an HPD IRQ pulse handler would do this. > > > + * If provided MST core calls this callback from a poll-waiting loop > > > + * when waiting for MST down message replies. The driver is expected > > > + * to guard against a race between this callback and the driver's HPD > > > + * IRQ pulse handler. > > > + */ > > > + void (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *mgr); > > > }; > > > > > > #define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) > > > -- > > > 2.23.1 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > From imre.deak at intel.com Tue Jun 9 18:08:52 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 9 Jun 2020 21:08:52 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200609175923.GU6112@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> <20200609150525.GP6112@intel.com> <20200609174035.GG22647@ideak-desk.fi.intel.com> <20200609175923.GU6112@intel.com> Message-ID: <20200609180852.GI22647@ideak-desk.fi.intel.com> On Tue, Jun 09, 2020 at 08:59:23PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 09, 2020 at 08:40:35PM +0300, Imre Deak wrote: > > On Tue, Jun 09, 2020 at 06:05:25PM +0300, Ville Syrj?l? wrote: > > > On Mon, Jun 08, 2020 at 09:10:23PM +0300, Imre Deak wrote: > > > > DSC is not supported on DP MST streams so just return -EINVAL when > > > > reading/writing the i915_dsc_fec_support debugfs file for such > > > > connectors. > > > > > > > > This also fixes an OOPS, caused by the encoder->digport cast, which is > > > > not valid for MST encoders. > > > > > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > --- > > > > .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- > > > > 1 file changed, 29 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > index 2b640d8ab9d2..ebca8e488d03 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > > drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); > > > > > > > > do { > > > > + struct intel_encoder *encoder; > > > > + > > > > try_again = false; > > > > ret = drm_modeset_lock(&dev->mode_config.connection_mutex, > > > > &ctx); > > > > @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > > } else if (ret) { > > > > break; > > > > } > > > > - intel_dp = intel_attached_dp(to_intel_connector(connector)); > > > > + > > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > + /* TODO: Add DSC support for MST streams */ > > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > > > + ret = -EINVAL; > > > > + break; > > > > + } > > > > + > > > > + intel_dp = &enc_to_dig_port(encoder)->dp; > > > > crtc_state = to_intel_crtc_state(crtc->state); > > > > + > > > > seq_printf(m, "DSC_Enabled: %s\n", > > > > yesno(crtc_state->dsc.compression_enable)); > > > > seq_printf(m, "DSC_Sink_Support: %s\n", > > > > @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > int ret; > > > > struct drm_connector *connector = > > > > ((struct seq_file *)file->private_data)->private; > > > > - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > - struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > + struct drm_i915_private *i915 = to_i915(connector->dev); > > > > + struct intel_encoder *encoder; > > > > > > > > if (len == 0) > > > > return 0; > > > > @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > > > > > drm_dbg(&i915->drm, "Got %s for DSC Enable\n", > > > > (dsc_enable) ? "true" : "false"); > > > > - intel_dp->force_dsc_en = dsc_enable; > > > > > > > > - *offp += len; > > > > - return len; > > > > + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); > > > > + > > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > + /* TODO: Add DSC support for MST streams */ > > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > > > > > The attached encoder can be NULL for MST. > > > > Yes, I also sent v2 with that fixed. > > > > > Can't we just not add this debugfs file for MST connectors? > > > > Won't we have per MST connector DSC at one point? In that case we'd need > > something like this anyway. > > The problem is that it doesn't work until the encoder has been attached. > So the behaviour of the interface would be rather inconsistent when > applied to MST connectors. No idea what current tests are doing with > this stuff so can't say whether it would be a problem in practice. It's used to force DSC by writing to it before commit, so yes then it wouldn't work anyway. > > If this is never needed then yes, better not > > to add it. I can't use connector_type which is the same for MST and SST > > connectors so is it ok to differentiate based on a > > intel_attached_encoder() == NULL check? > > IIRC some other places use connector.mst_port to tell the two > apart. Ok, will use that. > > > > > > > > > > + ret = -EINVAL; > > > > + } else { > > > > + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; > > > > + *offp += len; > > > > + ret = len; > > > > + } > > > > + > > > > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); > > > > + > > > > + return ret; > > > > } > > > > > > > > static int i915_dsc_fec_support_open(struct inode *inode, > > > > -- > > > > 2.23.1 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx at lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Tue Jun 9 18:30:44 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 18:30:44 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Incrementally_check_for_rewinding_=28rev2=29?= In-Reply-To: <20200609122856.10207-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> Message-ID: <159172744477.17061.1275628820473655653@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Incrementally check for rewinding (rev2) URL : https://patchwork.freedesktop.org/series/78163/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8603_full -> Patchwork_17915_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17915_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17915_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17915_full: ### IGT changes ### #### Possible regressions #### * igt at kms_cursor_crc@pipe-d-cursor-64x64-random: - shard-tglb: [PASS][1] -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-tglb5/igt at kms_cursor_crc@pipe-d-cursor-64x64-random.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-tglb3/igt at kms_cursor_crc@pipe-d-cursor-64x64-random.html * igt at kms_flip@bo-too-big: - shard-tglb: NOTRUN -> [TIMEOUT][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-tglb3/igt at kms_flip@bo-too-big.html New tests --------- New tests have been introduced between CI_DRM_8603_full and Patchwork_17915_full: ### New IGT tests (1) ### * igt at i915_selftest@mock at ring: - Statuses : 7 pass(s) - Exec time: [0.10, 1.18] s Known issues ------------ Here are the changes found in Patchwork_17915_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-glk: [PASS][4] -> [FAIL][5] ([i915#1528]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-glk4/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-glk8/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_balancer@sliced: - shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#1936]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-tglb5/igt at gem_exec_balancer@sliced.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-tglb3/igt at gem_exec_balancer@sliced.html * igt at gem_exec_whisper@basic-contexts-forked-all: - shard-tglb: [PASS][8] -> [INCOMPLETE][9] ([i915#750]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-tglb1/igt at gem_exec_whisper@basic-contexts-forked-all.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-tglb2/igt at gem_exec_whisper@basic-contexts-forked-all.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][10] -> [DMESG-WARN][11] ([i915#402]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-tglb8/igt at i915_module_load@reload-with-fault-injection.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-tglb2/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][12] -> [WARN][13] ([i915#1519]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-hsw7/igt at i915_pm_rc6_residency@rc6-fence.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-hsw2/igt at i915_pm_rc6_residency@rc6-fence.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][14] -> [DMESG-WARN][15] ([i915#180]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_addfb_basic@bad-pitch-999: - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#95]) +18 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl2/igt at kms_addfb_basic@bad-pitch-999.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl7/igt at kms_addfb_basic@bad-pitch-999.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][18] -> [DMESG-FAIL][19] ([i915#118] / [i915#95]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-glk4/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +4 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-skl9/igt at kms_color@pipe-c-ctm-0-25.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-skl5/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_color@pipe-c-ctm-blue-to-red: - shard-kbl: [PASS][22] -> [DMESG-WARN][23] ([i915#93] / [i915#95]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-kbl6/igt at kms_color@pipe-c-ctm-blue-to-red.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-kbl6/igt at kms_color@pipe-c-ctm-blue-to-red.html * igt at kms_flip@2x-modeset-vs-vblank-race-interruptible at ab-vga1-hdmi-a1: - shard-hsw: [PASS][24] -> [DMESG-WARN][25] ([i915#1982]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-hsw4/igt at kms_flip@2x-modeset-vs-vblank-race-interruptible at ab-vga1-hdmi-a1.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-hsw8/igt at kms_flip@2x-modeset-vs-vblank-race-interruptible at ab-vga1-hdmi-a1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [PASS][26] -> [DMESG-WARN][27] ([i915#180]) +3 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-kbl7/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@wf_vblank-ts-check-interruptible at a-dp1: - shard-kbl: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-kbl7/igt at kms_flip@wf_vblank-ts-check-interruptible at a-dp1.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-kbl6/igt at kms_flip@wf_vblank-ts-check-interruptible at a-dp1.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][30] -> [FAIL][31] ([fdo#108145] / [i915#265]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-iclb: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-iclb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_basic: - shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#109441]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-iclb2/igt at kms_psr@psr2_basic.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-iclb4/igt at kms_psr@psr2_basic.html * igt at perf@polling-parameterized: - shard-hsw: [PASS][36] -> [FAIL][37] ([i915#1542]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-hsw1/igt at perf@polling-parameterized.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-hsw6/igt at perf@polling-parameterized.html #### Possible fixes #### * igt at gem_ctx_persistence@processes: - shard-skl: [FAIL][38] ([i915#1528]) -> [PASS][39] [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-skl1/igt at gem_ctx_persistence@processes.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-skl3/igt at gem_ctx_persistence@processes.html * igt at gem_flink_basic@double-flink: - shard-kbl: [DMESG-WARN][40] ([i915#93] / [i915#95]) -> [PASS][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-kbl2/igt at gem_flink_basic@double-flink.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-kbl3/igt at gem_flink_basic@double-flink.html * igt at gem_sync@basic-store-each: - shard-apl: [DMESG-WARN][42] ([i915#95]) -> [PASS][43] +18 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl7/igt at gem_sync@basic-store-each.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl2/igt at gem_sync@basic-store-each.html * igt at gem_wait@await at vecs0: - shard-hsw: [INCOMPLETE][44] ([i915#61]) -> [PASS][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-hsw4/igt at gem_wait@await at vecs0.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-hsw4/igt at gem_wait@await at vecs0.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][46] ([i915#402]) -> [PASS][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-tglb5/igt at i915_module_load@reload.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-tglb3/igt at i915_module_load@reload.html * igt at kms_atomic_transition@plane-use-after-nonblocking-unbind at pipe-a: - shard-apl: [DMESG-WARN][48] ([i915#1982]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl2/igt at kms_atomic_transition@plane-use-after-nonblocking-unbind at pipe-a.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl7/igt at kms_atomic_transition@plane-use-after-nonblocking-unbind at pipe-a.html * igt at kms_color@pipe-a-ctm-0-75: - shard-skl: [DMESG-WARN][50] ([i915#1982]) -> [PASS][51] +3 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-skl9/igt at kms_color@pipe-a-ctm-0-75.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-skl9/igt at kms_color@pipe-a-ctm-0-75.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][52] ([IGT#5]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-skl9/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-skl10/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-kbl: [DMESG-WARN][54] ([i915#180]) -> [PASS][55] +5 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-kbl6/igt at kms_flip@flip-vs-suspend at a-dp1.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-kbl7/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_flip@flip-vs-suspend at b-dp1: - shard-apl: [DMESG-WARN][56] ([i915#180]) -> [PASS][57] +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl8/igt at kms_flip@flip-vs-suspend at b-dp1.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl2/igt at kms_flip@flip-vs-suspend at b-dp1.html * igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1: - shard-skl: [FAIL][58] ([i915#1928]) -> [PASS][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-skl5/igt at kms_flip@plain-flip-ts-check-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-snb: [SKIP][60] ([fdo#109271]) -> [PASS][61] +3 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-snb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-snb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][62] ([i915#1188]) -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_psr@psr2_dpms: - shard-iclb: [SKIP][64] ([fdo#109441]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-iclb7/igt at kms_psr@psr2_dpms.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-iclb2/igt at kms_psr@psr2_dpms.html #### Warnings #### * igt at kms_color@pipe-a-degamma: - shard-tglb: [DMESG-FAIL][66] ([i915#1149] / [i915#402]) -> [FAIL][67] ([i915#1149] / [i915#1897]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-tglb3/igt at kms_color@pipe-a-degamma.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-tglb8/igt at kms_color@pipe-a-degamma.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][68] ([i915#1319]) -> [DMESG-FAIL][69] ([fdo#110321] / [i915#95]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-kbl3/igt at kms_content_protection@atomic.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-kbl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][70] ([i915#1319]) -> [TIMEOUT][71] ([i915#1319] / [i915#1635]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl2/igt at kms_content_protection@atomic-dpms.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][72] ([i915#1319] / [i915#1635]) -> [TIMEOUT][73] ([i915#1319]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl4/igt at kms_content_protection@lic.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl7/igt at kms_content_protection@lic.html - shard-kbl: [TIMEOUT][74] ([i915#1319]) -> [TIMEOUT][75] ([i915#1319] / [i915#1958]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-kbl1/igt at kms_content_protection@lic.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-kbl4/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][76] ([i915#1319] / [i915#1635]) -> [FAIL][77] ([fdo#110321]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8603/shard-apl7/igt at kms_content_protection@srm.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/shard-apl2/igt at kms_content_protection@srm.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8603 -> Patchwork_17915 CI-20190529: 20190529 CI_DRM_8603: 03f5a3d90ccfb2f1bb13e293a83d48a0b7da8af0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17915: 729184acbb949babd103b9a1ae59de9a6c4918b1 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17915/index.html From imre.deak at intel.com Tue Jun 9 18:41:40 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 9 Jun 2020 21:41:40 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200608182650.13642-1-imre.deak@intel.com> References: <20200608182650.13642-1-imre.deak@intel.com> Message-ID: <20200609184140.4937-1-imre.deak@intel.com> DSC is not supported on DP MST streams so just don't add this entry for MST connectors. This also fixes an OOPS, caused by the encoder->digport cast, which is not valid for MST encoders. v2: - Check encoder, which is unset for an MST connector, before it gets enabled. v3: - Just don't add this debugfs file for MST connectors. (Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 2b640d8ab9d2..28dd717e943a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2218,7 +2218,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector) } if (INTEL_GEN(dev_priv) >= 10 && - (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || + ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && + !to_intel_connector(connector)->mst_port) || connector->connector_type == DRM_MODE_CONNECTOR_eDP)) debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, connector, &i915_dsc_fec_support_fops); -- 2.23.1 From manasi.d.navare at intel.com Tue Jun 9 18:56:56 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 9 Jun 2020 11:56:56 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200609180852.GI22647@ideak-desk.fi.intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> <20200609150525.GP6112@intel.com> <20200609174035.GG22647@ideak-desk.fi.intel.com> <20200609175923.GU6112@intel.com> <20200609180852.GI22647@ideak-desk.fi.intel.com> Message-ID: <20200609185656.GA26705@intel.com> On Tue, Jun 09, 2020 at 09:08:52PM +0300, Imre Deak wrote: > On Tue, Jun 09, 2020 at 08:59:23PM +0300, Ville Syrj?l? wrote: > > On Tue, Jun 09, 2020 at 08:40:35PM +0300, Imre Deak wrote: > > > On Tue, Jun 09, 2020 at 06:05:25PM +0300, Ville Syrj?l? wrote: > > > > On Mon, Jun 08, 2020 at 09:10:23PM +0300, Imre Deak wrote: > > > > > DSC is not supported on DP MST streams so just return -EINVAL when > > > > > reading/writing the i915_dsc_fec_support debugfs file for such > > > > > connectors. > > > > > > > > > > This also fixes an OOPS, caused by the encoder->digport cast, which is > > > > > not valid for MST encoders. > > > > > > > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > > --- > > > > > .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- > > > > > 1 file changed, 29 insertions(+), 7 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > index 2b640d8ab9d2..ebca8e488d03 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > > > drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); > > > > > > > > > > do { > > > > > + struct intel_encoder *encoder; > > > > > + > > > > > try_again = false; > > > > > ret = drm_modeset_lock(&dev->mode_config.connection_mutex, > > > > > &ctx); > > > > > @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > > > } else if (ret) { > > > > > break; > > > > > } > > > > > - intel_dp = intel_attached_dp(to_intel_connector(connector)); > > > > > + > > > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > > + /* TODO: Add DSC support for MST streams */ > > > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > > > > + ret = -EINVAL; > > > > > + break; > > > > > + } > > > > > + > > > > > + intel_dp = &enc_to_dig_port(encoder)->dp; > > > > > crtc_state = to_intel_crtc_state(crtc->state); > > > > > + > > > > > seq_printf(m, "DSC_Enabled: %s\n", > > > > > yesno(crtc_state->dsc.compression_enable)); > > > > > seq_printf(m, "DSC_Sink_Support: %s\n", > > > > > @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > > int ret; > > > > > struct drm_connector *connector = > > > > > ((struct seq_file *)file->private_data)->private; > > > > > - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > > - struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > > > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > + struct drm_i915_private *i915 = to_i915(connector->dev); > > > > > + struct intel_encoder *encoder; > > > > > > > > > > if (len == 0) > > > > > return 0; > > > > > @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > > > > > > > drm_dbg(&i915->drm, "Got %s for DSC Enable\n", > > > > > (dsc_enable) ? "true" : "false"); > > > > > - intel_dp->force_dsc_en = dsc_enable; > > > > > > > > > > - *offp += len; > > > > > - return len; > > > > > + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); > > > > > + > > > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > > + /* TODO: Add DSC support for MST streams */ > > > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { even after we force dsc en from IGT through this debugfs node, the actual enabling checks if dsc supported, so may be since we currently dont support on MST, can we add some condition in this function: intel_dsc_source_support() to not support on MST encoders? Also, currently since we dont even call intel_dp_dsc_compute_config in MST codepath, how does it even make a difference if we set force_dsc_en through this debugfs or not for MST? Manasi > > > > > > > > The attached encoder can be NULL for MST. > > > > > > Yes, I also sent v2 with that fixed. > > > > > > > Can't we just not add this debugfs file for MST connectors? > > > > > > Won't we have per MST connector DSC at one point? In that case we'd need > > > something like this anyway. > > > > The problem is that it doesn't work until the encoder has been attached. > > So the behaviour of the interface would be rather inconsistent when > > applied to MST connectors. No idea what current tests are doing with > > this stuff so can't say whether it would be a problem in practice. > > It's used to force DSC by writing to it before commit, so yes then it > wouldn't work anyway. > > > > If this is never needed then yes, better not > > > to add it. I can't use connector_type which is the same for MST and SST > > > connectors so is it ok to differentiate based on a > > > intel_attached_encoder() == NULL check? > > > > IIRC some other places use connector.mst_port to tell the two > > apart. > > Ok, will use that. > > > > > > > > > > > > > > > + ret = -EINVAL; > > > > > + } else { > > > > > + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; > > > > > + *offp += len; > > > > > + ret = len; > > > > > + } > > > > > + > > > > > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); > > > > > + > > > > > + return ret; > > > > > } > > > > > > > > > > static int i915_dsc_fec_support_open(struct inode *inode, > > > > > -- > > > > > 2.23.1 > > > > > > > > > > _______________________________________________ > > > > > Intel-gfx mailing list > > > > > Intel-gfx at lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > > > -- > > Ville Syrj?l? > > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From manasi.d.navare at intel.com Tue Jun 9 19:00:14 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 9 Jun 2020 12:00:14 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200609184140.4937-1-imre.deak@intel.com> References: <20200608182650.13642-1-imre.deak@intel.com> <20200609184140.4937-1-imre.deak@intel.com> Message-ID: <20200609190014.GB26705@intel.com> On Tue, Jun 09, 2020 at 09:41:40PM +0300, Imre Deak wrote: > DSC is not supported on DP MST streams so just don't add this entry for > MST connectors. > > This also fixes an OOPS, caused by the encoder->digport cast, which is > not valid for MST encoders. > > v2: > - Check encoder, which is unset for an MST connector, before it gets > enabled. > v3: > - Just don't add this debugfs file for MST connectors. (Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> Yes now just not having this debugfs entry for MST connectors makes sense once we support it on MST we can expose it the right way Reviewed-by: Manasi Navare <manasi.d.navare at intel.com> Manasi > --- > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 2b640d8ab9d2..28dd717e943a 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -2218,7 +2218,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector) > } > > if (INTEL_GEN(dev_priv) >= 10 && > - (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || > + ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && > + !to_intel_connector(connector)->mst_port) || > connector->connector_type == DRM_MODE_CONNECTOR_eDP)) > debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, > connector, &i915_dsc_fec_support_fops); > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From imre.deak at intel.com Tue Jun 9 19:13:54 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 9 Jun 2020 22:13:54 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors In-Reply-To: <20200609185656.GA26705@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> <20200609150525.GP6112@intel.com> <20200609174035.GG22647@ideak-desk.fi.intel.com> <20200609175923.GU6112@intel.com> <20200609180852.GI22647@ideak-desk.fi.intel.com> <20200609185656.GA26705@intel.com> Message-ID: <20200609191354.GJ22647@ideak-desk.fi.intel.com> On Tue, Jun 09, 2020 at 11:56:56AM -0700, Manasi Navare wrote: > On Tue, Jun 09, 2020 at 09:08:52PM +0300, Imre Deak wrote: > > On Tue, Jun 09, 2020 at 08:59:23PM +0300, Ville Syrj?l? wrote: > > > On Tue, Jun 09, 2020 at 08:40:35PM +0300, Imre Deak wrote: > > > > On Tue, Jun 09, 2020 at 06:05:25PM +0300, Ville Syrj?l? wrote: > > > > > On Mon, Jun 08, 2020 at 09:10:23PM +0300, Imre Deak wrote: > > > > > > DSC is not supported on DP MST streams so just return -EINVAL when > > > > > > reading/writing the i915_dsc_fec_support debugfs file for such > > > > > > connectors. > > > > > > > > > > > > This also fixes an OOPS, caused by the encoder->digport cast, which is > > > > > > not valid for MST encoders. > > > > > > > > > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > > > --- > > > > > > .../drm/i915/display/intel_display_debugfs.c | 36 +++++++++++++++---- > > > > > > 1 file changed, 29 insertions(+), 7 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > index 2b640d8ab9d2..ebca8e488d03 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > @@ -2094,6 +2094,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > > > > drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); > > > > > > > > > > > > do { > > > > > > + struct intel_encoder *encoder; > > > > > > + > > > > > > try_again = false; > > > > > > ret = drm_modeset_lock(&dev->mode_config.connection_mutex, > > > > > > &ctx); > > > > > > @@ -2120,8 +2122,17 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) > > > > > > } else if (ret) { > > > > > > break; > > > > > > } > > > > > > - intel_dp = intel_attached_dp(to_intel_connector(connector)); > > > > > > + > > > > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > > > + /* TODO: Add DSC support for MST streams */ > > > > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > > > > > + ret = -EINVAL; > > > > > > + break; > > > > > > + } > > > > > > + > > > > > > + intel_dp = &enc_to_dig_port(encoder)->dp; > > > > > > crtc_state = to_intel_crtc_state(crtc->state); > > > > > > + > > > > > > seq_printf(m, "DSC_Enabled: %s\n", > > > > > > yesno(crtc_state->dsc.compression_enable)); > > > > > > seq_printf(m, "DSC_Sink_Support: %s\n", > > > > > > @@ -2147,9 +2158,8 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > > > int ret; > > > > > > struct drm_connector *connector = > > > > > > ((struct seq_file *)file->private_data)->private; > > > > > > - struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > > > - struct drm_i915_private *i915 = to_i915(encoder->base.dev); > > > > > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > + struct drm_i915_private *i915 = to_i915(connector->dev); > > > > > > + struct intel_encoder *encoder; > > > > > > > > > > > > if (len == 0) > > > > > > return 0; > > > > > > @@ -2163,10 +2173,22 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, > > > > > > > > > > > > drm_dbg(&i915->drm, "Got %s for DSC Enable\n", > > > > > > (dsc_enable) ? "true" : "false"); > > > > > > - intel_dp->force_dsc_en = dsc_enable; > > > > > > > > > > > > - *offp += len; > > > > > > - return len; > > > > > > + drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); > > > > > > + > > > > > > + encoder = intel_attached_encoder(to_intel_connector(connector)); > > > > > > + /* TODO: Add DSC support for MST streams */ > > > > > > + if (encoder->type == INTEL_OUTPUT_DP_MST) { > > even after we force dsc en from IGT through this debugfs node, the > actual enabling checks if dsc supported, so may be since we currently > dont support on MST, can we add some condition in this function: > intel_dsc_source_support() to not support on MST encoders? I think the final API is not yeat clear for MST, so since it's not used either I agree that it's better to remove it. > Also, currently since we dont even call intel_dp_dsc_compute_config in > MST codepath, how does it even make a difference if we set > force_dsc_en through this debugfs or not for MST? The difference is that intel_attached_dp() can't be used on MST connectors. > > Manasi > > > > > > > > > > > The attached encoder can be NULL for MST. > > > > > > > > Yes, I also sent v2 with that fixed. > > > > > > > > > Can't we just not add this debugfs file for MST connectors? > > > > > > > > Won't we have per MST connector DSC at one point? In that case we'd need > > > > something like this anyway. > > > > > > The problem is that it doesn't work until the encoder has been attached. > > > So the behaviour of the interface would be rather inconsistent when > > > applied to MST connectors. No idea what current tests are doing with > > > this stuff so can't say whether it would be a problem in practice. > > > > It's used to force DSC by writing to it before commit, so yes then it > > wouldn't work anyway. > > > > > > If this is never needed then yes, better not > > > > to add it. I can't use connector_type which is the same for MST and SST > > > > connectors so is it ok to differentiate based on a > > > > intel_attached_encoder() == NULL check? > > > > > > IIRC some other places use connector.mst_port to tell the two > > > apart. > > > > Ok, will use that. > > > > > > > > > > > > > > > > > > > > + ret = -EINVAL; > > > > > > + } else { > > > > > > + enc_to_intel_dp(encoder)->force_dsc_en = dsc_enable; > > > > > > + *offp += len; > > > > > > + ret = len; > > > > > > + } > > > > > > + > > > > > > + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); > > > > > > + > > > > > > + return ret; > > > > > > } > > > > > > > > > > > > static int i915_dsc_fec_support_open(struct inode *inode, > > > > > > -- > > > > > > 2.23.1 > > > > > > > > > > > > _______________________________________________ > > > > > > Intel-gfx mailing list > > > > > > Intel-gfx at lists.freedesktop.org > > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > > > -- > > > > > Ville Syrj?l? > > > > > Intel > > > > > > -- > > > Ville Syrj?l? > > > Intel > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Tue Jun 9 19:17:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 19:17:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_the_i915=5Fdsc=5Ffec=5Fsupport_debugfs_file_for_DP?= =?utf-8?q?_MST_connectors_=28rev3=29?= In-Reply-To: <20200608181023.11503-1-imre.deak@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> Message-ID: <159173025282.17060.8043804600924297267@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors (rev3) URL : https://patchwork.freedesktop.org/series/78128/ State : success == Summary == CI Bug Log - changes from CI_DRM_8604 -> Patchwork_17916 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/index.html Known issues ------------ Here are the changes found in Patchwork_17916 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@dp-crc-fast: - fi-icl-u2: [FAIL][11] ([i915#262]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 42) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8604 -> Patchwork_17916 CI-20190529: 20190529 CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17916: b4af214db886283d6bc416bb70d95623c8c47ff6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b4af214db886 drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/index.html From stanislav.lisovskiy at intel.com Tue Jun 9 20:45:12 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Tue, 9 Jun 2020 23:45:12 +0300 Subject: [Intel-gfx] [PATCH 1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <20200609204512.GA8525@intel.com> On Mon, Jun 08, 2020 at 12:25:20AM +0300, Imre Deak wrote: > The WARN below triggers during the removal of an MST port. The problem > is that the parent device's (the connector's kdev) sysfs directory is > removed recursively when the connector is unregistered (even though the > I2C device holds a reference on the parent device). To fix this set > first the Peer Device Type to none which will remove the I2C device. > > Note that atm, inconsistently, the parent of the I2C device is initially set to > the DRM kdev and after a Connection Status Notification the parent may be reset > to be the connector's kdev. This problem is addressed by the next patch. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > [ 4462.989299] ------------[ cut here ]------------ > [ 4463.014940] sysfs group 'power' not found for kobject 'i2c-24' > [ 4463.034664] WARNING: CPU: 0 PID: 970 at fs/sysfs/group.c:281 sysfs_remove_group+0x71/0x80 > [ 4463.044357] Modules linked in: snd_hda_intel i915 drm_kms_helper(O) drm netconsole snd_hda_codec_hdmi mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul snd_intel_dspcf > g crc32_pclmul snd_hda_codec snd_hwdep ghash_clmulni_intel snd_hda_core asix usbnet kvm_intel mii i2c_algo_bit snd_pcm syscopyarea sysfillrect e1000e sysimgblt fb_sys_fops prim > e_numbers ptp pps_core i2c_i801 r8169 mei_me realtek mei [last unloaded: drm] > [ 4463.044399] CPU: 0 PID: 970 Comm: kworker/0:2 Tainted: G O 5.7.0+ #172 > [ 4463.044402] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP > [ 4463.044423] Workqueue: events drm_dp_delayed_destroy_work [drm_kms_helper] > [ 4463.044428] RIP: 0010:sysfs_remove_group+0x71/0x80 > [ 4463.044431] Code: 48 89 df 5b 5d 41 5c e9 cd b6 ff ff 48 89 df e8 95 b4 ff ff eb cb 49 8b 14 24 48 8b 75 00 48 c7 c7 20 0f 3f 82 e8 9f c5 d7 ff <0f> 0b 5b 5d 41 5c c3 0f 1f > 84 00 00 00 00 00 48 85 f6 74 31 41 54 > [ 4463.044433] RSP: 0018:ffffc900018bfbf0 EFLAGS: 00010282 > [ 4463.044436] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000001 > [ 4463.044439] RDX: 0000000080000001 RSI: ffff88849e828f38 RDI: 00000000ffffffff > [ 4463.052970] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:100:plane 2B] 00000000c2160caa state to 00000000d172564a > [ 4463.070533] RBP: ffffffff820cea20 R08: ffff88847f4b8958 R09: 0000000000000000 > [ 4463.070535] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848a725018 > [ 4463.070537] R13: 0000000000000000 R14: ffffffff827090e0 R15: 0000000000000002 > [ 4463.070539] FS: 0000000000000000(0000) GS:ffff88849e800000(0000) knlGS:0000000000000000 > [ 4463.070541] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 4463.070543] CR2: 00007fdf8a756538 CR3: 0000000489684001 CR4: 0000000000760ef0 > [ 4463.070545] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > [ 4463.070547] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 > [ 4463.070549] PKRU: 55555554 > [ 4463.070551] Call Trace: > [ 4463.070560] device_del+0x84/0x400 > [ 4463.070571] cdev_device_del+0x10/0x30 > [ 4463.070578] put_i2c_dev+0x69/0x80 > [ 4463.070584] i2cdev_detach_adapter+0x2e/0x60 > [ 4463.070591] notifier_call_chain+0x34/0x90 > [ 4463.070599] blocking_notifier_call_chain+0x3f/0x60 > [ 4463.070606] device_del+0x7c/0x400 > [ 4463.087817] ? lockdep_init_map_waits+0x57/0x210 > [ 4463.087825] device_unregister+0x11/0x60 > [ 4463.087829] i2c_del_adapter+0x249/0x310 > [ 4463.087846] drm_dp_port_set_pdt+0x6b/0x2c0 [drm_kms_helper] > [ 4463.087862] drm_dp_delayed_destroy_work+0x2af/0x350 [drm_kms_helper] > [ 4463.087876] process_one_work+0x268/0x600 > [ 4463.105438] ? __schedule+0x30c/0x920 > [ 4463.105451] worker_thread+0x37/0x380 > [ 4463.105457] ? process_one_work+0x600/0x600 > [ 4463.105462] kthread+0x140/0x160 > [ 4463.105466] ? kthread_park+0x80/0x80 > [ 4463.105474] ret_from_fork+0x24/0x50 > > Cc: <stable at vger.kernel.org> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 2a309fb2c4cc..02c800b8199f 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -4669,12 +4669,13 @@ static void drm_dp_tx_work(struct work_struct *work) > static inline void > drm_dp_delayed_destroy_port(struct drm_dp_mst_port *port) > { > + drm_dp_port_set_pdt(port, DP_PEER_DEVICE_NONE, port->mcs); > + > if (port->connector) { > drm_connector_unregister(port->connector); > drm_connector_put(port->connector); > } > > - drm_dp_port_set_pdt(port, DP_PEER_DEVICE_NONE, port->mcs); > drm_dp_mst_put_port_malloc(port); > } > > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Tue Jun 9 20:58:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 20:58:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_the_i915=5Fdsc=5Ffec=5Fsupport_debugfs_file_for_DP?= =?utf-8?q?_MST_connectors_=28rev3=29?= In-Reply-To: <20200608181023.11503-1-imre.deak@intel.com> References: <20200608181023.11503-1-imre.deak@intel.com> Message-ID: <159173632185.17060.7305715607581242818@emeril.freedesktop.org> == Series Details == Series: drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors (rev3) URL : https://patchwork.freedesktop.org/series/78128/ State : success == Summary == CI Bug Log - changes from CI_DRM_8604_full -> Patchwork_17916_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17916_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_shared@q-independent at bcs0: - shard-kbl: [PASS][1] -> [FAIL][2] ([i915#2013]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl6/igt at gem_ctx_shared@q-independent at bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl1/igt at gem_ctx_shared@q-independent at bcs0.html * igt at gem_exec_create@forked: - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([i915#61]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-hsw7/igt at gem_exec_create@forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-hsw2/igt at gem_exec_create@forked.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-snb6/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk8/igt at gem_exec_whisper@basic-forked-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-glk4/igt at gem_exec_whisper@basic-forked-all.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at gem_workarounds@suspend-resume-context.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl4/igt at gem_workarounds@suspend-resume-context.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_rps@reset: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#39]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl10/igt at i915_pm_rps@reset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl5/igt at i915_pm_rps@reset.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl1/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([i915#54] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-a-cursor-64x64-onscreen: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-kbl: [PASS][25] -> [DMESG-FAIL][26] ([i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl4/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt at kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [PASS][27] -> [FAIL][28] ([IGT#5]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html * igt at kms_cursor_legacy@pipe-c-torture-move: - shard-iclb: [PASS][29] -> [DMESG-WARN][30] ([i915#128]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb4/igt at kms_cursor_legacy@pipe-c-torture-move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at kms_cursor_legacy@pipe-c-torture-move.html * igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl6/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled: - shard-skl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +10 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl10/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html * igt at kms_fbcon_fbt@psr-suspend: - shard-iclb: [PASS][35] -> [INCOMPLETE][36] ([i915#1185]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb5/igt at kms_fbcon_fbt@psr-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb3/igt at kms_fbcon_fbt@psr-suspend.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][39] -> [FAIL][40] ([i915#1188]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_hdr@bpc-switch.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265]) +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109642] / [fdo#111068]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441]) +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_setmode@basic: - shard-skl: [PASS][47] -> [FAIL][48] ([i915#31]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_setmode@basic.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl2/igt at kms_setmode@basic.html * igt at perf_pmu@module-unload: - shard-iclb: [PASS][49] -> [DMESG-WARN][50] ([i915#1982]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb8/igt at perf_pmu@module-unload.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb3/igt at perf_pmu@module-unload.html * igt at syncobj_wait@invalid-wait-illegal-handle: - shard-apl: [PASS][51] -> [DMESG-WARN][52] ([i915#95]) +25 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at syncobj_wait@invalid-wait-illegal-handle.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl8/igt at syncobj_wait@invalid-wait-illegal-handle.html #### Possible fixes #### * igt at gem_ctx_shared@q-independent at bcs0: - shard-apl: [FAIL][53] ([i915#2013]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at gem_ctx_shared@q-independent at bcs0.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl1/igt at gem_ctx_shared@q-independent at bcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [DMESG-WARN][55] ([i915#93] / [i915#95]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at gem_exec_suspend@basic-s3.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl2/igt at gem_exec_suspend@basic-s3.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][57] ([i915#118] / [i915#95]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-glk4/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-90: - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-90.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl1/igt at kms_big_fb@yf-tiled-32bpp-rotate-90.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +5 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_color@pipe-a-ctm-0-5.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl8/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-apl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend at a-edp1: - shard-skl: [INCOMPLETE][65] ([i915#198]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_flip@flip-vs-suspend at a-edp1.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl5/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +5 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl7/igt at kms_flip@flip-vs-suspend at c-dp1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-kbl: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl2/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-skl: [FAIL][71] ([i915#49]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][73] ([i915#1188]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence: - shard-skl: [FAIL][75] ([i915#53]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl6/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][77] ([fdo#108145] / [i915#265]) -> [PASS][78] +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][79] ([fdo#108145] / [i915#1982]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][81] ([fdo#109441]) -> [PASS][82] +2 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb3/igt at kms_psr@psr2_primary_mmap_cpu.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][83] ([i915#31]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_setmode@basic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl6/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-query-busy-hang: - shard-tglb: [DMESG-WARN][85] ([i915#402]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb1/igt at kms_vblank@pipe-c-query-busy-hang.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb7/igt at kms_vblank@pipe-c-query-busy-hang.html * igt at sw_sync@sync_merge_same: - shard-apl: [DMESG-WARN][87] ([i915#95]) -> [PASS][88] +19 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at sw_sync@sync_merge_same.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl8/igt at sw_sync@sync_merge_same.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][89] ([i915#588]) -> [SKIP][90] ([i915#658]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][91] ([i915#454]) -> [SKIP][92] ([i915#468]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at i915_pm_dc@dc6-dpms.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at i915_pm_dc@dc6-psr: - shard-skl: [FAIL][93] ([i915#454]) -> [DMESG-FAIL][94] ([i915#1982]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at i915_pm_dc@dc6-psr.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl9/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][95] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][96] ([i915#1319] / [i915#1635]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_content_protection@atomic.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl8/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][97] ([i915#1319]) -> [TIMEOUT][98] ([i915#1319] / [i915#1635]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl3/igt at kms_content_protection@atomic-dpms.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][99] ([i915#1319] / [i915#1635]) -> [FAIL][100] ([fdo#110321] / [fdo#110336]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at kms_content_protection@legacy.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][101] ([i915#1319] / [i915#1635]) -> [TIMEOUT][102] ([i915#1319]) +1 similar issue [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at kms_content_protection@lic.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_draw_crc@fill-fb: - shard-apl: [DMESG-WARN][103] ([i915#95]) -> [DMESG-FAIL][104] ([i915#95]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at kms_draw_crc@fill-fb.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl2/igt at kms_draw_crc@fill-fb.html * igt at kms_fbcon_fbt@fbc: - shard-kbl: [FAIL][105] ([i915#64]) -> [DMESG-FAIL][106] ([i915#95]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl6/igt at kms_fbcon_fbt@fbc.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl1/igt at kms_fbcon_fbt@fbc.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2013]: https://gitlab.freedesktop.org/drm/intel/issues/2013 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8604 -> Patchwork_17916 CI-20190529: 20190529 CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17916: b4af214db886283d6bc416bb70d95623c8c47ff6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/index.html From imre.deak at intel.com Tue Jun 9 22:06:16 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 10 Jun 2020 01:06:16 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on Message-ID: <20200609220616.6015-1-imre.deak@intel.com> According to BSpec the Data Island Packet should be disabled after disabling the transcoder, but before the transcoder clock select is set to none. On an ICL RVP, daisy-chained MST config not following this leads to a hang with the following MCE when disabling the output: [ 870.948739] mce: [Hardware Error]: CPU 0: Machine Check Exception: 5 Bank 6: ba00000011000402 [ 871.019212] mce: [Hardware Error]: RIP !INEXACT! 10:<ffffffff81aca652> {poll_idle+0x92/0xb0} [ 871.019212] mce: [Hardware Error]: TSC 135a261fe61 [ 871.019212] mce: [Hardware Error]: PROCESSOR 0:706e5 TIME 1591739604 SOCKET 0 APIC 0 microcode 20 [ 871.019212] mce: [Hardware Error]: Run the above through 'mcelog --ascii' [ 871.019212] mce: [Hardware Error]: Machine check: Processor context corrupt [ 871.019212] Kernel panic - not syncing: Fatal machine check [ 871.019212] Kernel Offset: disabled Bspec: 4287 Fixes: fa37a213275c ("drm/i915: Stop sending DP SDPs on ddi disable") Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> Cc: Uma Shankar <uma.shankar at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 96eaa4b39c68..50ccc6e30dc1 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3510,7 +3510,9 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, INTEL_OUTPUT_DP_MST); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); + if (!is_mst) + intel_dp_set_infoframes(encoder, false, + old_crtc_state, old_conn_state); /* * Power down sink before disabling the port, otherwise we end diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d18b406f2a7d..f29e51ce489c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -397,6 +397,14 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, */ drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, false); + + /* + * BSpec 4287: disable DIP after the transcoder is disabled and before + * the transcoder clock select is set to none. + */ + if (last_mst_stream) + intel_dp_set_infoframes(&intel_dig_port->base, false, + old_crtc_state, NULL); /* * From TGL spec: "If multi-stream slave transcoder: Configure * Transcoder Clock Select to direct no clock to the transcoder" -- 2.23.1 From patchwork at emeril.freedesktop.org Tue Jun 9 22:48:45 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 22:48:45 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/icl=3A_Disable_DIP_on_MST_ports_with_the_transcoder_clock?= =?utf-8?q?_still_on?= In-Reply-To: <20200609220616.6015-1-imre.deak@intel.com> References: <20200609220616.6015-1-imre.deak@intel.com> Message-ID: <159174292522.17062.18274486842907684637@emeril.freedesktop.org> == Series Details == Series: drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on URL : https://patchwork.freedesktop.org/series/78172/ State : success == Summary == CI Bug Log - changes from CI_DRM_8604 -> Patchwork_17917 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/index.html Known issues ------------ Here are the changes found in Patchwork_17917 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-byt-j1900/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-byt-n2820/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@dp-crc-fast: - fi-icl-u2: [FAIL][11] ([i915#262]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8604 -> Patchwork_17917 CI-20190529: 20190529 CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17917: 28cda6a9ac5e59753727007e79807876b33d43ac @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 28cda6a9ac5e drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/index.html From lxoliva at fsfla.org Tue Jun 9 22:18:06 2020 From: lxoliva at fsfla.org (Alexandre Oliva) Date: Tue, 09 Jun 2020 19:18:06 -0300 Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c In-Reply-To: <159163988890.30073.8976615673203599761@build.alporthouse.com> (Chris Wilson's message of "Mon, 08 Jun 2020 19:11:28 +0100") References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> <159163988890.30073.8976615673203599761@build.alporthouse.com> Message-ID: <ortuzjx4rl.fsf@livre.home> On Jun 8, 2020, Chris Wilson <chris at chris-wilson.co.uk> wrote: > Quoting Rodrigo Vivi (2020-06-08 18:46:53) >> Alexandre Oliva has recently removed these files from Linux Libre >> with concerns that the sources weren't available. >> >> The sources are available on IGT repository, and only open source >> tools are used to generate the {ivb,hsw}_clear_kernel.c files. >> >> However, the remaining concern from Alexandre Oliva was around >> GPL license and the source not been present when distributing >> the code. Thanks for looking into this, and for addressing the potential issues so promptly. >> let's make sure that we do include the asm sources here in our tree. +1 having sources handy is good! >> Btw, I tried to have some diligence here and make sure that the >> asms that these commits are adding are truly the source for >> the mentioned files: Excellent! > Should there not be instructions on how to generate the object code? Considering that a script is used to generate it, to the point of adding some of the comments in the output, it might be a good idea to include it too, especially considering that scripts that control compilation are part of the complete corresponding source code under the GNU GPL. IMHO, a link to help users locate the assembler, as comments in the script, would be welcome, though not mandatory IIUC. Even though such links tend to rot over time, they at least offer encouragement to start or carry on a search ;-) Thanks again, -- Alexandre Oliva, freedom fighter he/him https://FSFLA.org/blogs/lxo/ Free Software Evangelist Stallman was right, but he's left :( GNU Toolchain Engineer Live long and free, and prosper ethically From patchwork at emeril.freedesktop.org Tue Jun 9 23:56:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 09 Jun 2020 23:56:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/icl=3A_Disable_DIP_on_MST_ports_with_the_transcoder_clock?= =?utf-8?q?_still_on?= In-Reply-To: <20200609220616.6015-1-imre.deak@intel.com> References: <20200609220616.6015-1-imre.deak@intel.com> Message-ID: <159174697260.17060.16481357416186052848@emeril.freedesktop.org> == Series Details == Series: drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on URL : https://patchwork.freedesktop.org/series/78172/ State : success == Summary == CI Bug Log - changes from CI_DRM_8604_full -> Patchwork_17917_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17917_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_create@madvise: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk6/igt at gem_exec_create@madvise.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk4/igt at gem_exec_create@madvise.html * igt at gem_exec_whisper@basic-normal: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at gem_exec_whisper@basic-normal.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at gem_exec_whisper@basic-normal.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-kbl: [PASS][7] -> [DMESG-FAIL][8] ([i915#54] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl10/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-kbl: [PASS][11] -> [DMESG-FAIL][12] ([i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl10/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at kms_flip@flip-vs-suspend at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl4/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1928]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_hdr@bpc-switch.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl1/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] / [fdo#111068]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb7/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb6/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_setmode@basic: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#31]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_setmode@basic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl8/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-a-ts-continuation-idle-hang: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_vblank@pipe-a-ts-continuation-idle-hang.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl2/igt at kms_vblank@pipe-a-ts-continuation-idle-hang.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +6 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#1542]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb8/igt at perf@blocking-parameterized.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb7/igt at perf@blocking-parameterized.html * igt at syncobj_wait@invalid-wait-illegal-handle: - shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#95]) +17 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at syncobj_wait@invalid-wait-illegal-handle.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl8/igt at syncobj_wait@invalid-wait-illegal-handle.html #### Possible fixes #### * igt at drm_read@short-buffer-block: - shard-kbl: [DMESG-WARN][39] ([i915#93] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at drm_read@short-buffer-block.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at drm_read@short-buffer-block.html * igt at gem_ctx_shared@q-independent at bcs0: - shard-apl: [FAIL][41] ([i915#2013]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at gem_ctx_shared@q-independent at bcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl2/igt at gem_ctx_shared@q-independent at bcs0.html * igt at gem_workarounds@suspend-resume: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl7/igt at gem_workarounds@suspend-resume.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at gem_workarounds@suspend-resume.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk7/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-glk: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk9/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk4/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_color@pipe-a-ctm-0-5.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl6/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-apl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend at a-edp1: - shard-skl: [INCOMPLETE][53] ([i915#198]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_flip@flip-vs-suspend at a-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-tglb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb1/igt at kms_psr@psr2_primary_page_flip.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html * igt at sw_sync@sync_merge_same: - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [PASS][64] +17 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at sw_sync@sync_merge_same.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl3/igt at sw_sync@sync_merge_same.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [INCOMPLETE][65] ([i915#1635] / [i915#1958]) -> [TIMEOUT][66] ([i915#1635]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at gem_exec_reloc@basic-concurrent16.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl1/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][67] ([i915#588]) -> [SKIP][68] ([i915#658]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@atomic: - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_content_protection@atomic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][71] ([i915#1319] / [i915#1635]) -> [FAIL][72] ([fdo#110321] / [fdo#110336]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at kms_content_protection@legacy.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl7/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at kms_content_protection@lic.html * igt at kms_draw_crc@fill-fb: - shard-apl: [DMESG-WARN][75] ([i915#95]) -> [DMESG-FAIL][76] ([i915#95]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at kms_draw_crc@fill-fb.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl8/igt at kms_draw_crc@fill-fb.html * igt at kms_fbcon_fbt@fbc: - shard-kbl: [FAIL][77] ([i915#64]) -> [DMESG-FAIL][78] ([i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl6/igt at kms_fbcon_fbt@fbc.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl2/igt at kms_fbcon_fbt@fbc.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][79] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][80] ([i915#1982]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2013]: https://gitlab.freedesktop.org/drm/intel/issues/2013 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8604 -> Patchwork_17917 CI-20190529: 20190529 CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17917: 28cda6a9ac5e59753727007e79807876b33d43ac @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/index.html From yu.bruce.chang at intel.com Wed Jun 10 04:25:39 2020 From: yu.bruce.chang at intel.com (Chang, Bruce) Date: Tue, 9 Jun 2020 21:25:39 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Incrementally check for rewinding In-Reply-To: <20200609151723.12971-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> <20200609151723.12971-1-chris@chris-wilson.co.uk> Message-ID: <bf5c088a-731a-7bc4-ff90-492f18e55045@intel.com> On 6/9/2020 8:17 AM, Chris Wilson wrote: > In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context > reload when rewinding RING_TAIL"), we placed the check for rewinding a > context on actually submitting the next request in that context. This > was so that we only had to check once, and could do so with precision > avoiding as many forced restores as possible. For example, to ensure > that we can resubmit the same request a couple of times, we include a > small wa_tail such that on the next submission, the ring->tail will > appear to move forwards when resubmitting the same request. This is very > common as it will happen for every lite-restore to fill the second port > after a context switch. > > However, intel_ring_direction() is limited in precision to movements of > upto half the ring size. The consequence being that if we tried to > unwind many requests, we could exceed half the ring and flip the sense > of the direction, so missing a force restore. As no request can be > greater than half the ring (i.e. 2048 bytes in the smallest case), we > can check for rollback incrementally. As we check against the tail that > would be submitted, we do not lose any sensitivity and allow lite > restores for the simple case. We still need to double check upon > submitting the context, to allow for multiple preemptions and > resubmissions. > > Fixes: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: <stable at vger.kernel.org> # v5.4+ Verified this has fixed the issue regarding the GPU hang with incomplete error state. reviewed by: Bruce Chang <yu.bruce.chang at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++- > drivers/gpu/drm/i915/gt/intel_ring.c | 4 + > drivers/gpu/drm/i915/gt/selftest_mocs.c | 18 ++- > drivers/gpu/drm/i915/gt/selftest_ring.c | 110 ++++++++++++++++++ > .../drm/i915/selftests/i915_mock_selftests.h | 1 + > 6 files changed, 154 insertions(+), 4 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/selftest_ring.c > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index e5141a897786..0a05301e00fb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -646,7 +646,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) > struct measure_breadcrumb { > struct i915_request rq; > struct intel_ring ring; > - u32 cs[1024]; > + u32 cs[2048]; > }; > > static int measure_breadcrumb_dw(struct intel_context *ce) > @@ -667,6 +667,8 @@ static int measure_breadcrumb_dw(struct intel_context *ce) > > frame->ring.vaddr = frame->cs; > frame->ring.size = sizeof(frame->cs); > + frame->ring.wrap = > + BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); Not sure if this? frame->ring.wrap being used anywhere > frame->ring.effective_size = frame->ring.size; > intel_ring_update_space(&frame->ring); > frame->rq.ring = &frame->ring; > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index a057f7a2a521..5f33342c15e2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1137,6 +1137,13 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) > list_move(&rq->sched.link, pl); > set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); > > + /* Check in case rollback so far, we wrap [size/2] */ > + if (intel_ring_direction(rq->ring, > + intel_ring_wrap(rq->ring, > + rq->tail), > + rq->ring->tail) > 0) > + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; > + minor: maybe just me, "so far" -> "too far"? > active = rq; > } else { > struct intel_engine_cs *owner = rq->context->engine; > @@ -1505,8 +1512,9 @@ static u64 execlists_update_context(struct i915_request *rq) > * HW has a tendency to ignore us rewinding the TAIL to the end of > * an earlier request. > */ > + GEM_BUG_ON(ce->lrc_reg_state[CTX_RING_TAIL] != rq->ring->tail); > + prev = rq->ring->tail; > tail = intel_ring_set_tail(rq->ring, rq->tail); > - prev = ce->lrc_reg_state[CTX_RING_TAIL]; > if (unlikely(intel_ring_direction(rq->ring, tail, prev) <= 0)) > desc |= CTX_DESC_FORCE_RESTORE; > ce->lrc_reg_state[CTX_RING_TAIL] = tail; > @@ -4758,6 +4766,14 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode) > return 0; > } > > +static void assert_request_valid(struct i915_request *rq) > +{ > + struct intel_ring *ring __maybe_unused = rq->ring; > + > + /* Can we unwind this request without appearing to go forwards? */ > + GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0); > +} > + > /* > * Reserve space for 2 NOOPs at the end of each request to be > * used as a workaround for not being allowed to do lite > @@ -4770,6 +4786,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) > *cs++ = MI_NOOP; > request->wa_tail = intel_ring_offset(request, cs); > > + /* Check that entire request is less than half the ring */ > + assert_request_valid(request); > + > return cs; > } > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c > index 8cda1b7e17ba..bdb324167ef3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring.c > @@ -315,3 +315,7 @@ int intel_ring_cacheline_align(struct i915_request *rq) > GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); > return 0; > } > + > +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > +#include "selftest_ring.c" > +#endif > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c > index 7bae64018ad9..b25eba50c88e 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c > @@ -18,6 +18,20 @@ struct live_mocs { > void *vaddr; > }; > > +static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) > +{ > + struct intel_context *ce; > + > + ce = intel_context_create(engine); > + if (IS_ERR(ce)) > + return ce; > + > + /* We build large requests to read the registers from the ring */ > + ce->ring = __intel_context_ring_size(SZ_16K); > + > + return ce; > +} > + > static int request_add_sync(struct i915_request *rq, int err) > { > i915_request_get(rq); > @@ -301,7 +315,7 @@ static int live_mocs_clean(void *arg) > for_each_engine(engine, gt, id) { > struct intel_context *ce; > > - ce = intel_context_create(engine); > + ce = mocs_context_create(engine); > if (IS_ERR(ce)) { > err = PTR_ERR(ce); > break; > @@ -395,7 +409,7 @@ static int live_mocs_reset(void *arg) > for_each_engine(engine, gt, id) { > struct intel_context *ce; > > - ce = intel_context_create(engine); > + ce = mocs_context_create(engine); > if (IS_ERR(ce)) { > err = PTR_ERR(ce); > break; > diff --git a/drivers/gpu/drm/i915/gt/selftest_ring.c b/drivers/gpu/drm/i915/gt/selftest_ring.c > new file mode 100644 > index 000000000000..2a8c534dc125 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/selftest_ring.c > @@ -0,0 +1,110 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright ? 2020 Intel Corporation > + */ > + > +static struct intel_ring *mock_ring(unsigned long sz) > +{ > + struct intel_ring *ring; > + > + ring = kzalloc(sizeof(*ring) + sz, GFP_KERNEL); > + if (!ring) > + return NULL; > + > + kref_init(&ring->ref); > + ring->size = sz; > + ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(sz); > + ring->effective_size = sz; > + ring->vaddr = (void *)(ring + 1); > + atomic_set(&ring->pin_count, 1); > + > + intel_ring_update_space(ring); > + > + return ring; > +} > + > +static void mock_ring_free(struct intel_ring *ring) > +{ > + kfree(ring); > +} > + > +static int check_ring_direction(struct intel_ring *ring, > + u32 next, u32 prev, > + int expected) > +{ > + int result; > + > + result = intel_ring_direction(ring, next, prev); > + if (result < 0) > + result = -1; > + else if (result > 0) > + result = 1; > + > + if (result != expected) { > + pr_err("intel_ring_direction(%u, %u):%d != %d\n", > + next, prev, result, expected); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int check_ring_step(struct intel_ring *ring, u32 x, u32 step) > +{ > + u32 prev = x, next = intel_ring_wrap(ring, x + step); > + int err = 0; > + > + err |= check_ring_direction(ring, next, next, 0); > + err |= check_ring_direction(ring, prev, prev, 0); > + err |= check_ring_direction(ring, next, prev, 1); > + err |= check_ring_direction(ring, prev, next, -1); > + > + return err; > +} > + > +static int check_ring_offset(struct intel_ring *ring, u32 x, u32 step) > +{ > + int err = 0; > + > + err |= check_ring_step(ring, x, step); > + err |= check_ring_step(ring, intel_ring_wrap(ring, x + 1), step); > + err |= check_ring_step(ring, intel_ring_wrap(ring, x - 1), step); > + > + return err; > +} > + > +static int igt_ring_direction(void *dummy) > +{ > + struct intel_ring *ring; > + unsigned int half = 2048; > + int step, err = 0; > + > + ring = mock_ring(2 * half); > + if (!ring) > + return -ENOMEM; > + > + GEM_BUG_ON(ring->size != 2 * half); > + > + /* Precision of wrap detection is limited to ring->size / 2 */ > + for (step = 1; step < half; step <<= 1) { > + err |= check_ring_offset(ring, 0, step); > + err |= check_ring_offset(ring, half, step); > + } > + err |= check_ring_step(ring, 0, half - 64); > + > + /* And check unwrapped handling for good measure */ > + err |= check_ring_offset(ring, 0, 2 * half + 64); > + err |= check_ring_offset(ring, 3 * half, 1); > + > + mock_ring_free(ring); > + return err; > +} > + > +int intel_ring_mock_selftests(void) > +{ > + static const struct i915_subtest tests[] = { > + SUBTEST(igt_ring_direction), > + }; > + > + return i915_subtests(tests, NULL); > +} > diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > index 1929feba4e8e..3db34d3eea58 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > +++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > @@ -21,6 +21,7 @@ selftest(fence, i915_sw_fence_mock_selftests) > selftest(scatterlist, scatterlist_mock_selftests) > selftest(syncmap, i915_syncmap_mock_selftests) > selftest(uncore, intel_uncore_mock_selftests) > +selftest(ring, intel_ring_mock_selftests) > selftest(engine, intel_engine_cs_mock_selftests) > selftest(timelines, intel_timeline_mock_selftests) > selftest(requests, i915_request_mock_selftests) From stanislav.lisovskiy at intel.com Wed Jun 10 07:29:54 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Wed, 10 Jun 2020 10:29:54 +0300 Subject: [Intel-gfx] [PATCH 3/3] drm/dp_mst: Fix flushing the delayed port/mstb destroy work In-Reply-To: <20200607212522.16935-3-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> <20200607212522.16935-3-imre.deak@intel.com> Message-ID: <20200610072954.GA10678@intel.com> On Mon, Jun 08, 2020 at 12:25:22AM +0300, Imre Deak wrote: > Atm, a pending delayed destroy work during module removal will be > canceled, leaving behind MST ports, mstbs. Fix this by using a dedicated > workqueue which will be drained of requeued items as well when > destroying it. > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 17 ++++++++++++++--- > include/drm/drm_dp_mst_helper.h | 8 ++++++++ > 2 files changed, 22 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 083255c33ee0..075fb5ac9264 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -1630,7 +1630,7 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) > mutex_lock(&mgr->delayed_destroy_lock); > list_add(&mstb->destroy_next, &mgr->destroy_branch_device_list); > mutex_unlock(&mgr->delayed_destroy_lock); > - schedule_work(&mgr->delayed_destroy_work); > + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); > } > > /** > @@ -1747,7 +1747,7 @@ static void drm_dp_destroy_port(struct kref *kref) > mutex_lock(&mgr->delayed_destroy_lock); > list_add(&port->next, &mgr->destroy_port_list); > mutex_unlock(&mgr->delayed_destroy_lock); > - schedule_work(&mgr->delayed_destroy_work); > + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); > } > > /** > @@ -5208,6 +5208,15 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, > INIT_LIST_HEAD(&mgr->destroy_port_list); > INIT_LIST_HEAD(&mgr->destroy_branch_device_list); > INIT_LIST_HEAD(&mgr->up_req_list); > + > + /* > + * delayed_destroy_work will be queued on a dedicated WQ, so that any > + * requeuing will be also flushed when deiniting the topology manager. > + */ > + mgr->delayed_destroy_wq = alloc_ordered_workqueue("drm_dp_mst_wq", 0); > + if (mgr->delayed_destroy_wq == NULL) > + return -ENOMEM; > + > INIT_WORK(&mgr->work, drm_dp_mst_link_probe_work); > INIT_WORK(&mgr->tx_work, drm_dp_tx_work); > INIT_WORK(&mgr->delayed_destroy_work, drm_dp_delayed_destroy_work); > @@ -5252,7 +5261,9 @@ void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr) > { > drm_dp_mst_topology_mgr_set_mst(mgr, false); > flush_work(&mgr->work); > - cancel_work_sync(&mgr->delayed_destroy_work); > + /* The following will also drain any requeued work on the WQ. */ > + destroy_workqueue(mgr->delayed_destroy_wq); > + mgr->delayed_destroy_wq = NULL; > mutex_lock(&mgr->payload_lock); > kfree(mgr->payloads); > mgr->payloads = NULL; > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index b230ff6f7081..8b9eb4db3381 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -681,6 +681,14 @@ struct drm_dp_mst_topology_mgr { > * @destroy_branch_device_list. > */ > struct mutex delayed_destroy_lock; > + > + /** > + * @delayed_destroy_wq: Workqueue used for delayed_destroy_work items. > + * A dedicated WQ makes it possible to drain any requeued work items > + * on it. > + */ > + struct workqueue_struct *delayed_destroy_wq; > + > /** > * @delayed_destroy_work: Work item to destroy MST port and branch > * devices, needed to avoid locking inversion. > -- > 2.23.1 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From kai.heng.feng at canonical.com Wed Jun 10 07:55:10 2020 From: kai.heng.feng at canonical.com (Kai-Heng Feng) Date: Wed, 10 Jun 2020 15:55:10 +0800 Subject: [Intel-gfx] [PATCH v6] drm/i915: Init lspcon after HPD in intel_dp_detect() Message-ID: <20200610075542.12882-1-kai.heng.feng@canonical.com> On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port becomes useless and never responds to cable hotplugging: [ 3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon [ 3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D Seems like the lspcon chip on the system only gets powered after the cable is plugged. Consilidate lspcon_init() into lspcon_resume() to dynamically init lspcon chip, and make HDMI port work. Signed-off-by: Kai-Heng Feng <kai.heng.feng at canonical.com> --- v6: - Rebase on latest for-linux-next. v5: - Consolidate lspcon_resume() with lspcon_init(). - Move more logic into lspcon code. v4: - Trust VBT in intel_infoframe_init(). - Init lspcon in intel_dp_detect(). v3: - Make sure it's handled under long HPD case. v2: - Move lspcon_init() inside of intel_dp_hpd_pulse(). drivers/gpu/drm/i915/display/intel_ddi.c | 19 +------ drivers/gpu/drm/i915/display/intel_dp.c | 10 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 63 ++++++++++++--------- drivers/gpu/drm/i915/display/intel_lspcon.h | 3 +- 5 files changed, 43 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index aa22465bb56e..af755b1aa24b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4805,7 +4805,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) { struct intel_digital_port *intel_dig_port; struct intel_encoder *encoder; - bool init_hdmi, init_dp, init_lspcon = false; + bool init_hdmi, init_dp; enum phy phy = intel_port_to_phy(dev_priv, port); init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || @@ -4819,7 +4819,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) * is initialized before lspcon. */ init_dp = true; - init_lspcon = true; init_hdmi = false; drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", port_name(port)); @@ -4904,22 +4903,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) goto err; } - if (init_lspcon) { - if (lspcon_init(intel_dig_port)) - /* TODO: handle hdmi info frame part */ - drm_dbg_kms(&dev_priv->drm, - "LSPCON init success on port %c\n", - port_name(port)); - else - /* - * LSPCON init faied, but DP init was success, so - * lets try to drive as DP++ port. - */ - drm_err(&dev_priv->drm, - "LSPCON init failed on port %c\n", - port_name(port)); - } - if (INTEL_GEN(dev_priv) >= 11) { if (intel_phy_is_tc(dev_priv, phy)) intel_dig_port->connected = intel_tc_port_connected; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ed9e53c373a7..398a104158a8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5962,15 +5962,14 @@ static enum drm_connector_status intel_dp_detect_dpcd(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u8 *dpcd = intel_dp->dpcd; u8 type; if (WARN_ON(intel_dp_is_edp(intel_dp))) return connector_status_connected; - if (lspcon->active) - lspcon_resume(lspcon); + lspcon_resume(dig_port); if (!intel_dp_get_dpcd(intel_dp)) return connector_status_disconnected; @@ -7056,14 +7055,13 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); intel_wakeref_t wakeref; if (!HAS_DDI(dev_priv)) intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); - if (lspcon->active) - lspcon_resume(lspcon); + lspcon_resume(dig_port); intel_dp->reset_link_params = true; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 010f37240710..643ad2127931 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3155,7 +3155,8 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port) intel_dig_port->set_infoframes = g4x_set_infoframes; intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; } else if (HAS_DDI(dev_priv)) { - if (intel_dig_port->lspcon.active) { + if (intel_bios_is_lspcon_present(dev_priv, + intel_dig_port->base.port)) { intel_dig_port->write_infoframe = lspcon_write_infoframe; intel_dig_port->read_infoframe = lspcon_read_infoframe; intel_dig_port->set_infoframes = lspcon_set_infoframes; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 6ff7b226f0a1..e3dde4c25604 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -525,44 +525,17 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, return 0; } -void lspcon_resume(struct intel_lspcon *lspcon) -{ - enum drm_lspcon_mode expected_mode; - - if (lspcon_wake_native_aux_ch(lspcon)) { - expected_mode = DRM_LSPCON_MODE_PCON; - lspcon_resume_in_pcon_wa(lspcon); - } else { - expected_mode = DRM_LSPCON_MODE_LS; - } - - if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) - return; - - if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) - DRM_ERROR("LSPCON resume failed\n"); - else - DRM_DEBUG_KMS("LSPCON resume success\n"); -} - void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) { lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); } -bool lspcon_init(struct intel_digital_port *intel_dig_port) +static bool lspcon_init(struct intel_digital_port *intel_dig_port) { struct intel_dp *dp = &intel_dig_port->dp; struct intel_lspcon *lspcon = &intel_dig_port->lspcon; - struct drm_device *dev = intel_dig_port->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); struct drm_connector *connector = &dp->attached_connector->base; - if (!HAS_LSPCON(dev_priv)) { - DRM_ERROR("LSPCON is not supported on this platform\n"); - return false; - } - lspcon->active = false; lspcon->mode = DRM_LSPCON_MODE_INVALID; @@ -586,3 +559,37 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) DRM_DEBUG_KMS("Success: LSPCON init\n"); return true; } + +void lspcon_resume(struct intel_digital_port *intel_dig_port) +{ + struct intel_lspcon *lspcon = &intel_dig_port->lspcon; + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + enum drm_lspcon_mode expected_mode; + + if (!intel_bios_is_lspcon_present(dev_priv, intel_dig_port->base.port)) + return; + + if (!lspcon->active) { + if (!lspcon_init(intel_dig_port)) { + DRM_ERROR("LSPCON init failed on port %c\n", + port_name(intel_dig_port->base.port)); + return; + } + } + + if (lspcon_wake_native_aux_ch(lspcon)) { + expected_mode = DRM_LSPCON_MODE_PCON; + lspcon_resume_in_pcon_wa(lspcon); + } else { + expected_mode = DRM_LSPCON_MODE_LS; + } + + if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) + return; + + if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) + DRM_ERROR("LSPCON resume failed\n"); + else + DRM_DEBUG_KMS("LSPCON resume success\n"); +} diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 37cfddf8a9c5..169db35db13e 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -15,8 +15,7 @@ struct intel_digital_port; struct intel_encoder; struct intel_lspcon; -bool lspcon_init(struct intel_digital_port *intel_dig_port); -void lspcon_resume(struct intel_lspcon *lspcon); +void lspcon_resume(struct intel_digital_port *intel_dig_port); void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); void lspcon_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, -- 2.17.1 From stanislav.lisovskiy at intel.com Wed Jun 10 08:03:04 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Wed, 10 Jun 2020 11:03:04 +0300 Subject: [Intel-gfx] [PATCH 2/3] drm/dp_mst: Fix the DDC I2C device registration of an MST port In-Reply-To: <20200607212522.16935-2-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> <20200607212522.16935-2-imre.deak@intel.com> Message-ID: <20200610080304.GA10787@intel.com> On Mon, Jun 08, 2020 at 12:25:21AM +0300, Imre Deak wrote: > During the initial MST probing an MST port's I2C device will be > registered using the kdev of the DRM device as a parent. Later after MST > Connection Status Notifications this I2C device will be re-registered > with the kdev of the port's connector. This will also move > inconsistently the I2C device's sysfs entry from the DRM device's sysfs > dir to the connector's dir. > > Fix the above by keeping the DRM kdev as the parent of the I2C device. > > Ideally the connector's kdev would be used as a parent, similarly to > non-MST connectors, however that needs some more refactoring to ensure > the connector's kdev is already available early enough. So keep the > existing (initial) behavior for now. > > Cc: <stable at vger.kernel.org> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 28 +++++++++++++++------------ > 1 file changed, 16 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 02c800b8199f..083255c33ee0 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -88,8 +88,8 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, > static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, > u8 *guid); > > -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux); > -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux); > +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port); > +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port); > static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr); > > #define DBG_PREFIX "[dp_mst]" > @@ -1993,7 +1993,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, > } > > /* remove i2c over sideband */ > - drm_dp_mst_unregister_i2c_bus(&port->aux); > + drm_dp_mst_unregister_i2c_bus(port); > } else { > mutex_lock(&mgr->lock); > drm_dp_mst_topology_put_mstb(port->mstb); > @@ -2008,7 +2008,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, > if (port->pdt != DP_PEER_DEVICE_NONE) { > if (drm_dp_mst_is_end_device(port->pdt, port->mcs)) { > /* add i2c over sideband */ > - ret = drm_dp_mst_register_i2c_bus(&port->aux); > + ret = drm_dp_mst_register_i2c_bus(port); > } else { > lct = drm_dp_calculate_rad(port, rad); > mstb = drm_dp_add_mst_branch_device(lct, rad); > @@ -5375,22 +5375,26 @@ static const struct i2c_algorithm drm_dp_mst_i2c_algo = { > > /** > * drm_dp_mst_register_i2c_bus() - register an I2C adapter for I2C-over-AUX > - * @aux: DisplayPort AUX channel > + * @port: The port to add the I2C bus on > * > * Returns 0 on success or a negative error code on failure. > */ > -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) > +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port) > { > + struct drm_dp_aux *aux = &port->aux; > + struct device *parent_dev = port->mgr->dev->dev; > + So are we sure that this will always give us thr kdev of the drm device? I mean could there be more complex hierarchy? Just wondering if there is a way to get drm device kdev in a more explicit way. > aux->ddc.algo = &drm_dp_mst_i2c_algo; > aux->ddc.algo_data = aux; > aux->ddc.retries = 3; > > aux->ddc.class = I2C_CLASS_DDC; > aux->ddc.owner = THIS_MODULE; > - aux->ddc.dev.parent = aux->dev; > - aux->ddc.dev.of_node = aux->dev->of_node; > + /* FIXME: set the kdev of the port's connector as parent */ > + aux->ddc.dev.parent = parent_dev; > + aux->ddc.dev.of_node = parent_dev->of_node; > > - strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), > + strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(parent_dev), > sizeof(aux->ddc.name)); > > return i2c_add_adapter(&aux->ddc); > @@ -5398,11 +5402,11 @@ static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) > > /** > * drm_dp_mst_unregister_i2c_bus() - unregister an I2C-over-AUX adapter > - * @aux: DisplayPort AUX channel > + * @port: The port to remove the I2C bus from > */ > -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux) > +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port) > { > - i2c_del_adapter(&aux->ddc); > + i2c_del_adapter(&port->aux.ddc); > } > > /** > -- > 2.23.1 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From patchwork at emeril.freedesktop.org Wed Jun 10 08:25:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 08:25:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Init_lspcon_after_HPD_in_intel=5Fdp=5Fdetect=28=29_=28?= =?utf-8?q?rev2=29?= In-Reply-To: <20200610075542.12882-1-kai.heng.feng@canonical.com> References: <20200610075542.12882-1-kai.heng.feng@canonical.com> Message-ID: <159177750767.20176.10423305937071348202@emeril.freedesktop.org> == Series Details == Series: drm/i915: Init lspcon after HPD in intel_dp_detect() (rev2) URL : https://patchwork.freedesktop.org/series/73480/ State : success == Summary == CI Bug Log - changes from CI_DRM_8604 -> Patchwork_17918 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/index.html Known issues ------------ Here are the changes found in Patchwork_17918 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-byt-j1900/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-byt-j1900/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-byt-n2820/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@dp-crc-fast: - fi-icl-u2: [FAIL][15] ([i915#262]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8604 -> Patchwork_17918 CI-20190529: 20190529 CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17918: abe9efda047415736cc8faf7ff2abb094fc9039c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == abe9efda0474 drm/i915: Init lspcon after HPD in intel_dp_detect() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/index.html From patchwork at emeril.freedesktop.org Wed Jun 10 09:33:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 09:33:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Init_lspcon_after_HPD_in_intel=5Fdp=5Fdetect=28=29_=28?= =?utf-8?q?rev2=29?= In-Reply-To: <20200610075542.12882-1-kai.heng.feng@canonical.com> References: <20200610075542.12882-1-kai.heng.feng@canonical.com> Message-ID: <159178162047.20176.17870581075044085491@emeril.freedesktop.org> == Series Details == Series: drm/i915: Init lspcon after HPD in intel_dp_detect() (rev2) URL : https://patchwork.freedesktop.org/series/73480/ State : success == Summary == CI Bug Log - changes from CI_DRM_8604_full -> Patchwork_17918_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17918_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vecs0: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at gem_ctx_persistence@engines-mixed-process at vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl6/igt at gem_ctx_persistence@engines-mixed-process at vecs0.html * igt at gem_eio@kms: - shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +10 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl6/igt at gem_eio@kms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl7/igt at gem_eio@kms.html * igt at gem_exec_create@forked: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] ([i915#61]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-hsw7/igt at gem_exec_create@forked.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-hsw8/igt at gem_exec_create@forked.html * igt at i915_selftest@perf at request: - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([i915#1823]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb7/igt at i915_selftest@perf at request.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-tglb7/igt at i915_selftest@perf at request.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-kbl: [PASS][9] -> [DMESG-FAIL][10] ([i915#54] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl10/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl5/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl4/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#93] / [i915#95]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl2/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#95]) +25 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_hdr@bpc-switch.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl8/igt at kms_hdr@bpc-switch.html * igt at kms_invalid_dotclock: - shard-snb: [PASS][23] -> [SKIP][24] ([fdo#109271]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-snb5/igt at kms_invalid_dotclock.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-snb2/igt at kms_invalid_dotclock.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109642] / [fdo#111068]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-iclb8/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-iclb8/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_setmode@basic: - shard-skl: [PASS][33] -> [FAIL][34] ([i915#31]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_setmode@basic.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl5/igt at kms_setmode@basic.html * igt at syncobj_wait@single-wait-submitted: - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#402]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb7/igt at syncobj_wait@single-wait-submitted.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-tglb5/igt at syncobj_wait@single-wait-submitted.html #### Possible fixes #### * igt at gem_ctx_shared@q-independent at bcs0: - shard-apl: [FAIL][37] ([i915#2013]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at gem_ctx_shared@q-independent at bcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl7/igt at gem_ctx_shared@q-independent at bcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [DMESG-WARN][39] ([i915#93] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at gem_exec_suspend@basic-s3.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl7/igt at gem_exec_suspend@basic-s3.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-glk7/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_color@pipe-a-ctm-0-5.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl2/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend at a-edp1: - shard-skl: [INCOMPLETE][47] ([i915#198]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_flip@flip-vs-suspend at a-edp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +4 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl7/igt at kms_flip@flip-vs-suspend at c-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-kbl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc: - shard-apl: [DMESG-WARN][53] ([i915#95]) -> [PASS][54] +11 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl6/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-skl: [FAIL][55] ([i915#49]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl1/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl1/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][61] ([fdo#108145] / [i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +3 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb7/igt at kms_psr@psr2_sprite_mmap_gtt.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][65] ([i915#31]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_setmode@basic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl2/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-query-busy-hang: - shard-tglb: [DMESG-WARN][67] ([i915#402]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb1/igt at kms_vblank@pipe-c-query-busy-hang.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-tglb7/igt at kms_vblank@pipe-c-query-busy-hang.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][69] ([i915#588]) -> [SKIP][70] ([i915#658]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-iclb8/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-skl: [FAIL][71] ([i915#454]) -> [DMESG-FAIL][72] ([i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at i915_pm_dc@dc6-psr.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-skl2/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1958]) +2 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_content_protection@atomic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl4/igt at kms_content_protection@atomic.html - shard-apl: [FAIL][75] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][76] ([i915#1319] / [i915#1635]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_content_protection@atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl1/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][77] ([i915#1319]) -> [FAIL][78] ([fdo#110321] / [fdo#110336]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl3/igt at kms_content_protection@atomic-dpms.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [FAIL][80] ([fdo#110321]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at kms_content_protection@lic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl6/igt at kms_content_protection@lic.html * igt at kms_draw_crc@fill-fb: - shard-apl: [DMESG-WARN][81] ([i915#95]) -> [DMESG-FAIL][82] ([i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at kms_draw_crc@fill-fb.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl8/igt at kms_draw_crc@fill-fb.html * igt at kms_fbcon_fbt@fbc: - shard-kbl: [FAIL][83] ([i915#64]) -> [DMESG-FAIL][84] ([i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl6/igt at kms_fbcon_fbt@fbc.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl3/igt at kms_fbcon_fbt@fbc.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][85] ([i915#93] / [i915#95]) -> [DMESG-WARN][86] ([i915#180] / [i915#93] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-c-alpha-basic: - shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#95]) -> [FAIL][88] ([fdo#108145] / [i915#265]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2013]: https://gitlab.freedesktop.org/drm/intel/issues/2013 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8604 -> Patchwork_17918 CI-20190529: 20190529 CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17918: abe9efda047415736cc8faf7ff2abb094fc9039c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17918/index.html From joonas.lahtinen at linux.intel.com Wed Jun 10 09:37:00 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Wed, 10 Jun 2020 12:37:00 +0300 Subject: [Intel-gfx] [PULL] drm-intel-next-fixes Message-ID: <20200610093700.GA8599@jlahtine-desk.ger.corp.intel.com> Hi Dave & Daniel, Sending this one early for it to hopefully make it in before -rc1. Two important fixes: OOPS fix that was missing "Fixes:" tag and not picked up earlier. Also fix for a use-after-free in cmdparser. Additional fixup to module param types. Regards, Joonas *** drm-intel-next-fixes-2020-06-10: - Avoid use after free in cmdparser - Avoid NULL dereference when probing all display encoders - Fixup to module parameter type The following changes since commit 8d286e2ff4400d313955b4203fc640ca6fd9228b: Merge tag 'drm-intel-next-fixes-2020-06-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2020-06-08 11:59:57 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2020-06-10 for you to fetch changes up to 3680c2e9f4254d1f033bf00f540e47a51f8f996b: drm/i915/display: Only query DP state of a DDI encoder (2020-06-09 14:47:05 +0300) ---------------------------------------------------------------- - Avoid use after free in cmdparser - Avoid NULL dereference when probing all display encoders - Fixup to module parameter type ---------------------------------------------------------------- Chris Wilson (2): drm/i915/gem: Mark the buffer pool as active for the cmdparser drm/i915/display: Only query DP state of a DDI encoder Jani Nikula (1): drm/i915/params: fix i915.reset module param type drivers/gpu/drm/i915/display/intel_dp.c | 3 ++ drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 56 ++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_params.c | 2 +- 3 files changed, 52 insertions(+), 9 deletions(-) From imre.deak at intel.com Wed Jun 10 10:09:36 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 10 Jun 2020 13:09:36 +0300 Subject: [Intel-gfx] [PATCH 2/3] drm/dp_mst: Fix the DDC I2C device registration of an MST port In-Reply-To: <20200610080304.GA10787@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> <20200607212522.16935-2-imre.deak@intel.com> <20200610080304.GA10787@intel.com> Message-ID: <20200610100936.GB10200@ideak-desk.fi.intel.com> On Wed, Jun 10, 2020 at 11:03:04AM +0300, Lisovskiy, Stanislav wrote: > On Mon, Jun 08, 2020 at 12:25:21AM +0300, Imre Deak wrote: > > During the initial MST probing an MST port's I2C device will be > > registered using the kdev of the DRM device as a parent. Later after MST > > Connection Status Notifications this I2C device will be re-registered > > with the kdev of the port's connector. This will also move > > inconsistently the I2C device's sysfs entry from the DRM device's sysfs > > dir to the connector's dir. > > > > Fix the above by keeping the DRM kdev as the parent of the I2C device. > > > > Ideally the connector's kdev would be used as a parent, similarly to > > non-MST connectors, however that needs some more refactoring to ensure > > the connector's kdev is already available early enough. So keep the > > existing (initial) behavior for now. > > > > Cc: <stable at vger.kernel.org> > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 28 +++++++++++++++------------ > > 1 file changed, 16 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > index 02c800b8199f..083255c33ee0 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -88,8 +88,8 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, > > static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, > > u8 *guid); > > > > -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux); > > -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux); > > +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port); > > +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port); > > static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr); > > > > #define DBG_PREFIX "[dp_mst]" > > @@ -1993,7 +1993,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, > > } > > > > /* remove i2c over sideband */ > > - drm_dp_mst_unregister_i2c_bus(&port->aux); > > + drm_dp_mst_unregister_i2c_bus(port); > > } else { > > mutex_lock(&mgr->lock); > > drm_dp_mst_topology_put_mstb(port->mstb); > > @@ -2008,7 +2008,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, > > if (port->pdt != DP_PEER_DEVICE_NONE) { > > if (drm_dp_mst_is_end_device(port->pdt, port->mcs)) { > > /* add i2c over sideband */ > > - ret = drm_dp_mst_register_i2c_bus(&port->aux); > > + ret = drm_dp_mst_register_i2c_bus(port); > > } else { > > lct = drm_dp_calculate_rad(port, rad); > > mstb = drm_dp_add_mst_branch_device(lct, rad); > > @@ -5375,22 +5375,26 @@ static const struct i2c_algorithm drm_dp_mst_i2c_algo = { > > > > /** > > * drm_dp_mst_register_i2c_bus() - register an I2C adapter for I2C-over-AUX > > - * @aux: DisplayPort AUX channel > > + * @port: The port to add the I2C bus on > > * > > * Returns 0 on success or a negative error code on failure. > > */ > > -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) > > +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port) > > { > > + struct drm_dp_aux *aux = &port->aux; > > + struct device *parent_dev = port->mgr->dev->dev; > > + > > So are we sure that this will always give us thr kdev of the drm device? > I mean could there be more complex hierarchy? Just wondering if there is > a way to get drm device kdev in a more explicit way. There is a single mgr per DRM driver (kdev) and port objects created by a given DRM driver will stay owned by the same DRM driver. So the kdev->port association is static. > > aux->ddc.algo = &drm_dp_mst_i2c_algo; > > aux->ddc.algo_data = aux; > > aux->ddc.retries = 3; > > > > aux->ddc.class = I2C_CLASS_DDC; > > aux->ddc.owner = THIS_MODULE; > > - aux->ddc.dev.parent = aux->dev; > > - aux->ddc.dev.of_node = aux->dev->of_node; > > + /* FIXME: set the kdev of the port's connector as parent */ > > + aux->ddc.dev.parent = parent_dev; > > + aux->ddc.dev.of_node = parent_dev->of_node; > > > > - strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), > > + strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(parent_dev), > > sizeof(aux->ddc.name)); > > > > return i2c_add_adapter(&aux->ddc); > > @@ -5398,11 +5402,11 @@ static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) > > > > /** > > * drm_dp_mst_unregister_i2c_bus() - unregister an I2C-over-AUX adapter > > - * @aux: DisplayPort AUX channel > > + * @port: The port to remove the I2C bus from > > */ > > -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux) > > +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port) > > { > > - i2c_del_adapter(&aux->ddc); > > + i2c_del_adapter(&port->aux.ddc); > > } > > > > /** > > -- > > 2.23.1 > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel From stanislav.lisovskiy at intel.com Wed Jun 10 10:59:13 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Wed, 10 Jun 2020 13:59:13 +0300 Subject: [Intel-gfx] [PATCH 2/3] drm/dp_mst: Fix the DDC I2C device registration of an MST port In-Reply-To: <20200610100936.GB10200@ideak-desk.fi.intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> <20200607212522.16935-2-imre.deak@intel.com> <20200610080304.GA10787@intel.com> <20200610100936.GB10200@ideak-desk.fi.intel.com> Message-ID: <20200610105913.GA11750@intel.com> On Wed, Jun 10, 2020 at 01:09:36PM +0300, Imre Deak wrote: > On Wed, Jun 10, 2020 at 11:03:04AM +0300, Lisovskiy, Stanislav wrote: > > On Mon, Jun 08, 2020 at 12:25:21AM +0300, Imre Deak wrote: > > > During the initial MST probing an MST port's I2C device will be > > > registered using the kdev of the DRM device as a parent. Later after MST > > > Connection Status Notifications this I2C device will be re-registered > > > with the kdev of the port's connector. This will also move > > > inconsistently the I2C device's sysfs entry from the DRM device's sysfs > > > dir to the connector's dir. > > > > > > Fix the above by keeping the DRM kdev as the parent of the I2C device. > > > > > > Ideally the connector's kdev would be used as a parent, similarly to > > > non-MST connectors, however that needs some more refactoring to ensure > > > the connector's kdev is already available early enough. So keep the > > > existing (initial) behavior for now. > > > > > > Cc: <stable at vger.kernel.org> > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > --- > > > drivers/gpu/drm/drm_dp_mst_topology.c | 28 +++++++++++++++------------ > > > 1 file changed, 16 insertions(+), 12 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > > index 02c800b8199f..083255c33ee0 100644 > > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > > @@ -88,8 +88,8 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, > > > static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, > > > u8 *guid); > > > > > > -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux); > > > -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux); > > > +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port); > > > +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port); > > > static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr); > > > > > > #define DBG_PREFIX "[dp_mst]" > > > @@ -1993,7 +1993,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, > > > } > > > > > > /* remove i2c over sideband */ > > > - drm_dp_mst_unregister_i2c_bus(&port->aux); > > > + drm_dp_mst_unregister_i2c_bus(port); > > > } else { > > > mutex_lock(&mgr->lock); > > > drm_dp_mst_topology_put_mstb(port->mstb); > > > @@ -2008,7 +2008,7 @@ drm_dp_port_set_pdt(struct drm_dp_mst_port *port, u8 new_pdt, > > > if (port->pdt != DP_PEER_DEVICE_NONE) { > > > if (drm_dp_mst_is_end_device(port->pdt, port->mcs)) { > > > /* add i2c over sideband */ > > > - ret = drm_dp_mst_register_i2c_bus(&port->aux); > > > + ret = drm_dp_mst_register_i2c_bus(port); > > > } else { > > > lct = drm_dp_calculate_rad(port, rad); > > > mstb = drm_dp_add_mst_branch_device(lct, rad); > > > @@ -5375,22 +5375,26 @@ static const struct i2c_algorithm drm_dp_mst_i2c_algo = { > > > > > > /** > > > * drm_dp_mst_register_i2c_bus() - register an I2C adapter for I2C-over-AUX > > > - * @aux: DisplayPort AUX channel > > > + * @port: The port to add the I2C bus on > > > * > > > * Returns 0 on success or a negative error code on failure. > > > */ > > > -static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) > > > +static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port) > > > { > > > + struct drm_dp_aux *aux = &port->aux; > > > + struct device *parent_dev = port->mgr->dev->dev; > > > + > > > > So are we sure that this will always give us thr kdev of the drm device? > > I mean could there be more complex hierarchy? Just wondering if there is > > a way to get drm device kdev in a more explicit way. > > There is a single mgr per DRM driver (kdev) and port objects created by > a given DRM driver will stay owned by the same DRM driver. So the > kdev->port association is static. Ok, thanks for clarification. lgtm then. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > aux->ddc.algo = &drm_dp_mst_i2c_algo; > > > aux->ddc.algo_data = aux; > > > aux->ddc.retries = 3; > > > > > > aux->ddc.class = I2C_CLASS_DDC; > > > aux->ddc.owner = THIS_MODULE; > > > - aux->ddc.dev.parent = aux->dev; > > > - aux->ddc.dev.of_node = aux->dev->of_node; > > > + /* FIXME: set the kdev of the port's connector as parent */ > > > + aux->ddc.dev.parent = parent_dev; > > > + aux->ddc.dev.of_node = parent_dev->of_node; > > > > > > - strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), > > > + strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(parent_dev), > > > sizeof(aux->ddc.name)); > > > > > > return i2c_add_adapter(&aux->ddc); > > > @@ -5398,11 +5402,11 @@ static int drm_dp_mst_register_i2c_bus(struct drm_dp_aux *aux) > > > > > > /** > > > * drm_dp_mst_unregister_i2c_bus() - unregister an I2C-over-AUX adapter > > > - * @aux: DisplayPort AUX channel > > > + * @port: The port to remove the I2C bus from > > > */ > > > -static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_aux *aux) > > > +static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port) > > > { > > > - i2c_del_adapter(&aux->ddc); > > > + i2c_del_adapter(&port->aux.ddc); > > > } > > > > > > /** > > > -- > > > 2.23.1 > > > > > > _______________________________________________ > > > dri-devel mailing list > > > dri-devel at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel From joonas.lahtinen at linux.intel.com Wed Jun 10 11:19:54 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Wed, 10 Jun 2020 14:19:54 +0300 Subject: [Intel-gfx] [PULL] drm-intel-next-fixes In-Reply-To: <20200610093700.GA8599@jlahtine-desk.ger.corp.intel.com> References: <20200610093700.GA8599@jlahtine-desk.ger.corp.intel.com> Message-ID: <159178799449.10895.1314682153738530580@jlahtine-desk.ger.corp.intel.com> Quoting Joonas Lahtinen (2020-06-10 12:37:00) > Hi Dave & Daniel, > > Sending this one early for it to hopefully make it in before -rc1. > > Two important fixes: OOPS fix that was missing "Fixes:" tag and > not picked up earlier. Also fix for a use-after-free in cmdparser. > > Additional fixup to module param types. Oh, the CI results: https://intel-gfx-ci.01.org/tree/drm-intel-next-fixes/combined-alt.html? CI_DINF_195 was drm-next CI_DINF_197 is this PR The extra yellow cells due to FIFO underruns are due to a concurrent CI update that started flagging the issues. So no regression, just existing long-running issue being highlighted. Regards, Joonas > Regards, Joonas > > *** > > drm-intel-next-fixes-2020-06-10: > > - Avoid use after free in cmdparser > - Avoid NULL dereference when probing all display encoders > - Fixup to module parameter type > > The following changes since commit 8d286e2ff4400d313955b4203fc640ca6fd9228b: > > Merge tag 'drm-intel-next-fixes-2020-06-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2020-06-08 11:59:57 +1000) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-fixes-2020-06-10 > > for you to fetch changes up to 3680c2e9f4254d1f033bf00f540e47a51f8f996b: > > drm/i915/display: Only query DP state of a DDI encoder (2020-06-09 14:47:05 +0300) > > ---------------------------------------------------------------- > - Avoid use after free in cmdparser > - Avoid NULL dereference when probing all display encoders > - Fixup to module parameter type > > ---------------------------------------------------------------- > Chris Wilson (2): > drm/i915/gem: Mark the buffer pool as active for the cmdparser > drm/i915/display: Only query DP state of a DDI encoder > > Jani Nikula (1): > drm/i915/params: fix i915.reset module param type > > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++ > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 56 ++++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_params.c | 2 +- > 3 files changed, 52 insertions(+), 9 deletions(-) From imre.deak at intel.com Wed Jun 10 11:33:01 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 10 Jun 2020 14:33:01 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogIHN1Y2Nlc3MgZm9yIGRy?= =?utf-8?q?m/i915/tc=3A_fix_the_reset_of_ln0?= In-Reply-To: <159165462706.14460.10339190541202498686@emeril.freedesktop.org> References: <20200608204537.28468-1-khaled.almahallawy@intel.com> <159165462706.14460.10339190541202498686@emeril.freedesktop.org> Message-ID: <20200610113301.GD10200@ideak-desk.fi.intel.com> On Mon, Jun 08, 2020 at 10:17:07PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/tc: fix the reset of ln0 > URL : https://patchwork.freedesktop.org/series/78132/ > State : success Thanks for the fix (my review botch-up) and the review, pushed to -dinq Cc-ing stable and adding Fixes: 3b51be4e4061b ("drm/i915/tc: Update DP_MODE programming") > > == Summary == > > CI Bug Log - changes from CI_DRM_8601_full -> Patchwork_17912_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17912_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_create@forked: > - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at gem_exec_create@forked.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk6/igt at gem_exec_create@forked.html > > * igt at gem_sync@basic-store-each: > - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +11 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at gem_sync@basic-store-each.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl7/igt at gem_sync@basic-store-each.html > > * igt at i915_module_load@reload: > - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb5/igt at i915_module_load@reload.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-tglb1/igt at i915_module_load@reload.html > > * igt at i915_suspend@debugfs-reader: > - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl3/igt at i915_suspend@debugfs-reader.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at i915_suspend@debugfs-reader.html > > * igt at kms_big_fb@linear-16bpp-rotate-0: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl2/igt at kms_big_fb@linear-16bpp-rotate-0.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl8/igt at kms_big_fb@linear-16bpp-rotate-0.html > > * igt at kms_big_fb@y-tiled-64bpp-rotate-0: > - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb5/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > > * igt at kms_color@pipe-c-ctm-blue-to-red: > - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +1 similar issue > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_color@pipe-c-ctm-blue-to-red.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at kms_color@pipe-c-ctm-blue-to-red.html > > * igt at kms_draw_crc@draw-method-rgb565-blt-ytiled: > - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +4 similar issues > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt at kms_draw_crc@draw-method-rgb565-blt-ytiled.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl8/igt at kms_draw_crc@draw-method-rgb565-blt-ytiled.html > > * igt at kms_frontbuffer_tracking@fbc-stridechange: > - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk4/igt at kms_frontbuffer_tracking@fbc-stridechange.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk6/igt at kms_frontbuffer_tracking@fbc-stridechange.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite: > - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt at kms_psr@psr2_cursor_plane_move: > - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb4/igt at kms_psr@psr2_cursor_plane_move.html > > * igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend: > - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#69]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl3/igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend.html > > > #### Possible fixes #### > > * {igt at gem_exec_reloc@basic-concurrent0}: > - shard-glk: [FAIL][27] ([i915#1930]) -> [PASS][28] > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html > > * igt at gem_exec_whisper@basic-queues-forked: > - shard-glk: [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30] > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk9/igt at gem_exec_whisper@basic-queues-forked.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk9/igt at gem_exec_whisper@basic-queues-forked.html > > * igt at gem_mmap_gtt@fault-concurrent: > - shard-skl: [CRASH][31] -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at gem_mmap_gtt@fault-concurrent.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl4/igt at gem_mmap_gtt@fault-concurrent.html > > * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: > - shard-skl: [FAIL][33] ([i915#54]) -> [PASS][34] > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html > > * igt at kms_cursor_crc@pipe-c-cursor-suspend: > - shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > > * {igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2}: > - shard-glk: [FAIL][37] ([i915#1928]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-glk5/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-glk5/igt at kms_flip@2x-blocking-wf_vblank at ab-hdmi-a1-hdmi-a2.html > > * {igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1}: > - shard-kbl: [FAIL][39] ([i915#79]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html > > * {igt at kms_flip@flip-vs-suspend-interruptible at a-dp1}: > - shard-apl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * {igt at kms_flip@flip-vs-suspend at a-edp1}: > - shard-skl: [INCOMPLETE][43] ([i915#198]) -> [PASS][44] +1 similar issue > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl10/igt at kms_flip@flip-vs-suspend at a-edp1.html > > * igt at kms_flip_tiling@flip-y-tiled: > - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +8 similar issues > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl9/igt at kms_flip_tiling@flip-y-tiled.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl8/igt at kms_flip_tiling@flip-y-tiled.html > > * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: > - shard-iclb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +1 similar issue > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb8/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > > * igt at kms_lease@page_flip_implicit_plane: > - shard-snb: [TIMEOUT][49] ([i915#1958]) -> [PASS][50] +1 similar issue > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt at kms_lease@page_flip_implicit_plane.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-snb2/igt at kms_lease@page_flip_implicit_plane.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid: > - shard-apl: [DMESG-WARN][51] ([i915#95]) -> [PASS][52] +16 similar issues > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-mid.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +2 similar issues > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_psr@psr2_primary_mmap_cpu: > - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html > > * igt at kms_setmode@basic: > - shard-hsw: [FAIL][57] ([i915#31]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw6/igt at kms_setmode@basic.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-hsw8/igt at kms_setmode@basic.html > > * {igt at perf@blocking-parameterized}: > - shard-iclb: [FAIL][59] ([i915#1542]) -> [PASS][60] +1 similar issue > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb3/igt at perf@blocking-parameterized.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb8/igt at perf@blocking-parameterized.html > - shard-hsw: [FAIL][61] ([i915#1542]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-hsw8/igt at perf@blocking-parameterized.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-hsw1/igt at perf@blocking-parameterized.html > > * igt at syncobj_wait@multi-wait-all-for-submit-signaled: > - shard-tglb: [DMESG-WARN][63] ([i915#402]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-tglb3/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-tglb8/igt at syncobj_wait@multi-wait-all-for-submit-signaled.html > > * igt at syncobj_wait@multi-wait-for-submit-unsubmitted: > - shard-kbl: [DMESG-WARN][65] ([i915#93] / [i915#95]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl2/igt at syncobj_wait@multi-wait-for-submit-unsubmitted.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][67] ([i915#588]) -> [SKIP][68] ([i915#658]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-iclb4/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at kms_content_protection@atomic-dpms: > - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl3/igt at kms_content_protection@atomic-dpms.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl7/igt at kms_content_protection@atomic-dpms.html > > * igt at kms_content_protection@legacy: > - shard-kbl: [TIMEOUT][71] ([i915#1319]) -> [TIMEOUT][72] ([i915#1319] / [i915#1958]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl1/igt at kms_content_protection@legacy.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl4/igt at kms_content_protection@legacy.html > > * igt at kms_content_protection@lic: > - shard-apl: [TIMEOUT][73] ([i915#1319] / [i915#1635]) -> [FAIL][74] ([fdo#110321]) +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-apl4/igt at kms_content_protection@lic.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-apl7/igt at kms_content_protection@lic.html > > * igt at kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][75] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][76] ([i915#93] / [i915#95]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html > > * igt at kms_psr@suspend: > - shard-snb: [TIMEOUT][77] ([i915#1958]) -> [SKIP][78] ([fdo#109271]) +2 similar issues > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8601/shard-snb5/igt at kms_psr@suspend.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/shard-snb2/igt at kms_psr@suspend.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8601 -> Patchwork_17912 > > CI-20190529: 20190529 > CI_DRM_8601: c801ab3a923b2436d765bd7a97888715f68451cb @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5699: 201da47cb57b8fadd9bc45be16b82617b32a2c01 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17912: 737e451d926089f1b4b060add1c9ee07650074df @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17912/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From jani.nikula at linux.intel.com Wed Jun 10 11:54:32 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Wed, 10 Jun 2020 14:54:32 +0300 Subject: [Intel-gfx] A panic and a hang in the i915 drm driver In-Reply-To: <2715545.1591635126@warthog.procyon.org.uk> References: <87ftb6x7em.fsf@intel.com> <2136072.1591491984@warthog.procyon.org.uk> <87o8puxak1.fsf@intel.com> <4ff2445aff8d44c5961a6d194a8f4663@intel.com> <2715545.1591635126@warthog.procyon.org.uk> Message-ID: <87pna7w2yv.fsf@intel.com> On Mon, 08 Jun 2020, David Howells <dhowells at redhat.com> wrote: > Jani Nikula <jani.nikula at linux.intel.com> wrote: > >> David, please try [1]. > > Assuming you mean this: > > https://patchwork.freedesktop.org/patch/366958/?series=77635&rev=1 > > yes, that works. > > Tested-by: David Howells <dhowells at redhat.com> Many thanks, Jani. -- Jani Nikula, Intel Open Source Graphics Center From thomas_os at shipmail.org Wed Jun 10 12:01:44 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Wed, 10 Jun 2020 14:01:44 +0200 Subject: [Intel-gfx] [PATCH 01/18] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200604081224.863494-2-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-2-daniel.vetter@ffwll.ch> Message-ID: <15bcdddd-b560-e98b-eaec-62277b5ab4af@shipmail.org> Hi, Daniel, Please see below. On 6/4/20 10:12 AM, Daniel Vetter wrote: > fs_reclaim_acquire/release nicely catch recursion issues when > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > to use to keep the excessive caches in check). For mmu notifier > recursions we do have lockdep annotations since 23b68395c7c7 > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > But these only fire if a path actually results in some pte > invalidation - for most small allocations that's very rarely the case. > The other trouble is that pte invalidation can happen any time when > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > recursion. > > I was pondering whether we should just do the general annotation, but > there's always the risk for false positives. Plus I'm assuming that > the core fs and io code is a lot better reviewed and tested than > random mmu notifier code in drivers. Hence why I decide to only > annotate for that specific case. > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > still need to explicit pull in the mmu notifier map - there's a lot > more places that do pte invalidation than just direct reclaim, these > two contexts arent the same. > > Note that the mmu notifiers needing their own independent lockdep map > is also the reason we can't hold them from fs_reclaim_acquire to > fs_reclaim_release - it would nest with the acquistion in the pte > invalidation code, causing a lockdep splat. And we can't remove the > annotations from pte invalidation and all the other places since > they're called from many other places than page reclaim. Hence we can > only do the equivalent of might_lock, but on the raw lockdep map. > > With this we can also remove the lockdep priming added in 66204f1d2d1b > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > strictly more powerful. > > Cc: Andrew Morton <akpm at linux-foundation.org> > Cc: Jason Gunthorpe <jgg at mellanox.com> > Cc: linux-mm at kvack.org > Cc: linux-rdma at vger.kernel.org > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > This is part of a gpu lockdep annotation series simply because it > really helps to catch issues where gpu subsystem locks and primitives > can deadlock with themselves through allocations and mmu notifiers. > But aside from that motivation it should be completely free-standing, > and can land through -mm/-rdma/-hmm or any other tree really whenever. > -Daniel > --- > mm/mmu_notifier.c | 7 ------- > mm/page_alloc.c | 23 ++++++++++++++--------- > 2 files changed, 14 insertions(+), 16 deletions(-) > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c > index 06852b896fa6..5d578b9122f8 100644 > --- a/mm/mmu_notifier.c > +++ b/mm/mmu_notifier.c > @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, > lockdep_assert_held_write(&mm->mmap_sem); > BUG_ON(atomic_read(&mm->mm_users) <= 0); > > - if (IS_ENABLED(CONFIG_LOCKDEP)) { > - fs_reclaim_acquire(GFP_KERNEL); > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > - fs_reclaim_release(GFP_KERNEL); > - } > - > if (!mm->notifier_subscriptions) { > /* > * kmalloc cannot be called under mm_take_all_locks(), but we > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > index 13cc653122b7..f8a222db4a53 100644 > --- a/mm/page_alloc.c > +++ b/mm/page_alloc.c > @@ -57,6 +57,7 @@ > #include <trace/events/oom.h> > #include <linux/prefetch.h> > #include <linux/mm_inline.h> > +#include <linux/mmu_notifier.h> > #include <linux/migrate.h> > #include <linux/hugetlb.h> > #include <linux/sched/rt.h> > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > static struct lockdep_map __fs_reclaim_map = > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > +static bool __need_reclaim(gfp_t gfp_mask) > { > gfp_mask = current_gfp_context(gfp_mask); > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > if (current->flags & PF_MEMALLOC) > return false; > > - /* We're only interested __GFP_FS allocations for now */ > - if (!(gfp_mask & __GFP_FS)) > - return false; > - > if (gfp_mask & __GFP_NOLOCKDEP) > return false; > > @@ -4158,15 +4155,23 @@ void __fs_reclaim_release(void) > > void fs_reclaim_acquire(gfp_t gfp_mask) > { > - if (__need_fs_reclaim(gfp_mask)) > - __fs_reclaim_acquire(); > + if (__need_reclaim(gfp_mask)) { > + if (!(gfp_mask & __GFP_FS)) Hmm. Shouldn't this be "if (gfp_mask & __GFP_FS)" or am I misunderstanding? > + __fs_reclaim_acquire(); #ifdef CONFIG_MMU_NOTIFIER? > + > + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > + lock_map_release(&__mmu_notifier_invalidate_range_start_map); > + > + } > } > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > void fs_reclaim_release(gfp_t gfp_mask) > { > - if (__need_fs_reclaim(gfp_mask)) > - __fs_reclaim_release(); > + if (__need_reclaim(gfp_mask)) { > + if (!(gfp_mask & __GFP_FS)) Same here? > + __fs_reclaim_release(); > + } > } > EXPORT_SYMBOL_GPL(fs_reclaim_release); > #endif One suggested test case would perhaps be to call madvise(madv_dontneed) on a subpart of a transhuge page. That would IIRC trigger a page split and interesting mmu notifier calls.... Thanks, Thomas From daniel.vetter at ffwll.ch Wed Jun 10 12:25:59 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Wed, 10 Jun 2020 14:25:59 +0200 Subject: [Intel-gfx] [PATCH 01/18] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <15bcdddd-b560-e98b-eaec-62277b5ab4af@shipmail.org> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-2-daniel.vetter@ffwll.ch> <15bcdddd-b560-e98b-eaec-62277b5ab4af@shipmail.org> Message-ID: <CAKMK7uGF_ghH-3hT5QMKHuzToP50xj3OaDzAtdjO-d8H9svdjQ@mail.gmail.com> On Wed, Jun 10, 2020 at 2:01 PM Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> wrote: > > Hi, Daniel, > > Please see below. > > On 6/4/20 10:12 AM, Daniel Vetter wrote: > > fs_reclaim_acquire/release nicely catch recursion issues when > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > to use to keep the excessive caches in check). For mmu notifier > > recursions we do have lockdep annotations since 23b68395c7c7 > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > But these only fire if a path actually results in some pte > > invalidation - for most small allocations that's very rarely the case. > > The other trouble is that pte invalidation can happen any time when > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > recursion. > > > > I was pondering whether we should just do the general annotation, but > > there's always the risk for false positives. Plus I'm assuming that > > the core fs and io code is a lot better reviewed and tested than > > random mmu notifier code in drivers. Hence why I decide to only > > annotate for that specific case. > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > still need to explicit pull in the mmu notifier map - there's a lot > > more places that do pte invalidation than just direct reclaim, these > > two contexts arent the same. > > > > Note that the mmu notifiers needing their own independent lockdep map > > is also the reason we can't hold them from fs_reclaim_acquire to > > fs_reclaim_release - it would nest with the acquistion in the pte > > invalidation code, causing a lockdep splat. And we can't remove the > > annotations from pte invalidation and all the other places since > > they're called from many other places than page reclaim. Hence we can > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > strictly more powerful. > > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > Cc: linux-mm at kvack.org > > Cc: linux-rdma at vger.kernel.org > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > --- > > This is part of a gpu lockdep annotation series simply because it > > really helps to catch issues where gpu subsystem locks and primitives > > can deadlock with themselves through allocations and mmu notifiers. > > But aside from that motivation it should be completely free-standing, > > and can land through -mm/-rdma/-hmm or any other tree really whenever. > > -Daniel > > --- > > mm/mmu_notifier.c | 7 ------- > > mm/page_alloc.c | 23 ++++++++++++++--------- > > 2 files changed, 14 insertions(+), 16 deletions(-) > > > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c > > index 06852b896fa6..5d578b9122f8 100644 > > --- a/mm/mmu_notifier.c > > +++ b/mm/mmu_notifier.c > > @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, > > lockdep_assert_held_write(&mm->mmap_sem); > > BUG_ON(atomic_read(&mm->mm_users) <= 0); > > > > - if (IS_ENABLED(CONFIG_LOCKDEP)) { > > - fs_reclaim_acquire(GFP_KERNEL); > > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > - fs_reclaim_release(GFP_KERNEL); > > - } > > - > > if (!mm->notifier_subscriptions) { > > /* > > * kmalloc cannot be called under mm_take_all_locks(), but we > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > > index 13cc653122b7..f8a222db4a53 100644 > > --- a/mm/page_alloc.c > > +++ b/mm/page_alloc.c > > @@ -57,6 +57,7 @@ > > #include <trace/events/oom.h> > > #include <linux/prefetch.h> > > #include <linux/mm_inline.h> > > +#include <linux/mmu_notifier.h> > > #include <linux/migrate.h> > > #include <linux/hugetlb.h> > > #include <linux/sched/rt.h> > > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > > static struct lockdep_map __fs_reclaim_map = > > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > > +static bool __need_reclaim(gfp_t gfp_mask) > > { > > gfp_mask = current_gfp_context(gfp_mask); > > > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > > if (current->flags & PF_MEMALLOC) > > return false; > > > > - /* We're only interested __GFP_FS allocations for now */ > > - if (!(gfp_mask & __GFP_FS)) > > - return false; > > - > > if (gfp_mask & __GFP_NOLOCKDEP) > > return false; > > > > @@ -4158,15 +4155,23 @@ void __fs_reclaim_release(void) > > > > void fs_reclaim_acquire(gfp_t gfp_mask) > > { > > - if (__need_fs_reclaim(gfp_mask)) > > - __fs_reclaim_acquire(); > > + if (__need_reclaim(gfp_mask)) { > > + if (!(gfp_mask & __GFP_FS)) > Hmm. Shouldn't this be "if (gfp_mask & __GFP_FS)" or am I misunderstanding? Uh yes :-( I guess what saved me is that I immediately went for the lockdep splat in drivers/gpu. And I guess there's not any obvious inversions for GFP_NOFS/GFP_NOIO, and since I made the mistake consintely the GFP_FS annotation was still consistent, but simply for GFP_NOFS. Oops. Will fix in the next version. > > + __fs_reclaim_acquire(); > > > #ifdef CONFIG_MMU_NOTIFIER? Hm indeed. Will fix too. Thanks for your review. > > > + > > + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > + lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > + > > + } > > } > > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > > > void fs_reclaim_release(gfp_t gfp_mask) > > { > > - if (__need_fs_reclaim(gfp_mask)) > > - __fs_reclaim_release(); > > + if (__need_reclaim(gfp_mask)) { > > + if (!(gfp_mask & __GFP_FS)) > Same here? > > + __fs_reclaim_release(); > > + } > > } > > EXPORT_SYMBOL_GPL(fs_reclaim_release); > > #endif > > One suggested test case would perhaps be to call madvise(madv_dontneed) > on a subpart of a transhuge page. That would IIRC trigger a page split > and interesting mmu notifier calls.... The neat thing about the mmu notifier lockdep key is that we take it whether there's notifiers or not - it's called outside of any of these paths. So as long as you have ever hit a hugepage split somewhen since boot, and you've hit your driver's mmu_notifier paths, lockdep will connect the dots. Explicit testcases for all combinations not needed anymore. This patch here just makes sure that the same holds for memory allocations and direct reclaim (which is a lot harder to trigger intentionally in testcases). That was at least the idea, seems to have caught a few things already. -Daniel > > Thanks, > Thomas > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mika.kuoppala at linux.intel.com Wed Jun 10 12:39:34 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Wed, 10 Jun 2020 15:39:34 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Incrementally check for rewinding In-Reply-To: <20200609151723.12971-1-chris@chris-wilson.co.uk> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> <20200609151723.12971-1-chris@chris-wilson.co.uk> Message-ID: <87a71b9jsp.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context > reload when rewinding RING_TAIL"), we placed the check for rewinding a > context on actually submitting the next request in that context. This > was so that we only had to check once, and could do so with precision > avoiding as many forced restores as possible. For example, to ensure > that we can resubmit the same request a couple of times, we include a > small wa_tail such that on the next submission, the ring->tail will > appear to move forwards when resubmitting the same request. This is very > common as it will happen for every lite-restore to fill the second port > after a context switch. > > However, intel_ring_direction() is limited in precision to movements of > upto half the ring size. The consequence being that if we tried to > unwind many requests, we could exceed half the ring and flip the sense > of the direction, so missing a force restore. As no request can be > greater than half the ring (i.e. 2048 bytes in the smallest case), we > can check for rollback incrementally. As we check against the tail that > would be submitted, we do not lose any sensitivity and allow lite > restores for the simple case. We still need to double check upon > submitting the context, to allow for multiple preemptions and > resubmissions. > > Fixes: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: <stable at vger.kernel.org> # v5.4+ > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++- > drivers/gpu/drm/i915/gt/intel_ring.c | 4 + > drivers/gpu/drm/i915/gt/selftest_mocs.c | 18 ++- > drivers/gpu/drm/i915/gt/selftest_ring.c | 110 ++++++++++++++++++ > .../drm/i915/selftests/i915_mock_selftests.h | 1 + > 6 files changed, 154 insertions(+), 4 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/selftest_ring.c > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index e5141a897786..0a05301e00fb 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -646,7 +646,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) > struct measure_breadcrumb { > struct i915_request rq; > struct intel_ring ring; > - u32 cs[1024]; > + u32 cs[2048]; > }; > > static int measure_breadcrumb_dw(struct intel_context *ce) > @@ -667,6 +667,8 @@ static int measure_breadcrumb_dw(struct intel_context *ce) > > frame->ring.vaddr = frame->cs; > frame->ring.size = sizeof(frame->cs); > + frame->ring.wrap = > + BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size); > frame->ring.effective_size = frame->ring.size; > intel_ring_update_space(&frame->ring); > frame->rq.ring = &frame->ring; > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index a057f7a2a521..5f33342c15e2 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1137,6 +1137,13 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) > list_move(&rq->sched.link, pl); > set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); > > + /* Check in case rollback so far, we wrap [size/2] */ This could be ammended a little as why it is not always the case that on the rewind the direction is not positive. > + if (intel_ring_direction(rq->ring, > + intel_ring_wrap(rq->ring, > + rq->tail), > + rq->ring->tail) > 0) > + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; > + > active = rq; > } else { > struct intel_engine_cs *owner = rq->context->engine; > @@ -1505,8 +1512,9 @@ static u64 execlists_update_context(struct i915_request *rq) > * HW has a tendency to ignore us rewinding the TAIL to the end of > * an earlier request. > */ > + GEM_BUG_ON(ce->lrc_reg_state[CTX_RING_TAIL] != rq->ring->tail); > + prev = rq->ring->tail; > tail = intel_ring_set_tail(rq->ring, rq->tail); > - prev = ce->lrc_reg_state[CTX_RING_TAIL]; > if (unlikely(intel_ring_direction(rq->ring, tail, prev) <= 0)) > desc |= CTX_DESC_FORCE_RESTORE; > ce->lrc_reg_state[CTX_RING_TAIL] = tail; > @@ -4758,6 +4766,14 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode) > return 0; > } > > +static void assert_request_valid(struct i915_request *rq) > +{ > + struct intel_ring *ring __maybe_unused = rq->ring; > + > + /* Can we unwind this request without appearing to go forwards? */ > + GEM_BUG_ON(intel_ring_direction(ring, rq->wa_tail, rq->head) <= 0); Chris explained in irc that as the wa_tail is reserved for next resubmit, the nondirection is also possible. > +} > + > /* > * Reserve space for 2 NOOPs at the end of each request to be > * used as a workaround for not being allowed to do lite > @@ -4770,6 +4786,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) > *cs++ = MI_NOOP; > request->wa_tail = intel_ring_offset(request, cs); > > + /* Check that entire request is less than half the ring */ > + assert_request_valid(request); I was thinking about adding the check in the advance part but that is too early. And also the tail validation is too early. This is so tricky with the wrap handling. But it is easier to stand behind the broad shoulders of the really appreciated selftests. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > + > return cs; > } > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c > index 8cda1b7e17ba..bdb324167ef3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring.c > @@ -315,3 +315,7 @@ int intel_ring_cacheline_align(struct i915_request *rq) > GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); > return 0; > } > + > +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > +#include "selftest_ring.c" > +#endif > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c > index 7bae64018ad9..b25eba50c88e 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c > @@ -18,6 +18,20 @@ struct live_mocs { > void *vaddr; > }; > > +static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) > +{ > + struct intel_context *ce; > + > + ce = intel_context_create(engine); > + if (IS_ERR(ce)) > + return ce; > + > + /* We build large requests to read the registers from the ring */ > + ce->ring = __intel_context_ring_size(SZ_16K); > + > + return ce; > +} > + > static int request_add_sync(struct i915_request *rq, int err) > { > i915_request_get(rq); > @@ -301,7 +315,7 @@ static int live_mocs_clean(void *arg) > for_each_engine(engine, gt, id) { > struct intel_context *ce; > > - ce = intel_context_create(engine); > + ce = mocs_context_create(engine); > if (IS_ERR(ce)) { > err = PTR_ERR(ce); > break; > @@ -395,7 +409,7 @@ static int live_mocs_reset(void *arg) > for_each_engine(engine, gt, id) { > struct intel_context *ce; > > - ce = intel_context_create(engine); > + ce = mocs_context_create(engine); > if (IS_ERR(ce)) { > err = PTR_ERR(ce); > break; > diff --git a/drivers/gpu/drm/i915/gt/selftest_ring.c b/drivers/gpu/drm/i915/gt/selftest_ring.c > new file mode 100644 > index 000000000000..2a8c534dc125 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gt/selftest_ring.c > @@ -0,0 +1,110 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright ? 2020 Intel Corporation > + */ > + > +static struct intel_ring *mock_ring(unsigned long sz) > +{ > + struct intel_ring *ring; > + > + ring = kzalloc(sizeof(*ring) + sz, GFP_KERNEL); > + if (!ring) > + return NULL; > + > + kref_init(&ring->ref); > + ring->size = sz; > + ring->wrap = BITS_PER_TYPE(ring->size) - ilog2(sz); > + ring->effective_size = sz; > + ring->vaddr = (void *)(ring + 1); > + atomic_set(&ring->pin_count, 1); > + > + intel_ring_update_space(ring); > + > + return ring; > +} > + > +static void mock_ring_free(struct intel_ring *ring) > +{ > + kfree(ring); > +} > + > +static int check_ring_direction(struct intel_ring *ring, > + u32 next, u32 prev, > + int expected) > +{ > + int result; > + > + result = intel_ring_direction(ring, next, prev); > + if (result < 0) > + result = -1; > + else if (result > 0) > + result = 1; > + > + if (result != expected) { > + pr_err("intel_ring_direction(%u, %u):%d != %d\n", > + next, prev, result, expected); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int check_ring_step(struct intel_ring *ring, u32 x, u32 step) > +{ > + u32 prev = x, next = intel_ring_wrap(ring, x + step); > + int err = 0; > + > + err |= check_ring_direction(ring, next, next, 0); > + err |= check_ring_direction(ring, prev, prev, 0); > + err |= check_ring_direction(ring, next, prev, 1); > + err |= check_ring_direction(ring, prev, next, -1); > + > + return err; > +} > + > +static int check_ring_offset(struct intel_ring *ring, u32 x, u32 step) > +{ > + int err = 0; > + > + err |= check_ring_step(ring, x, step); > + err |= check_ring_step(ring, intel_ring_wrap(ring, x + 1), step); > + err |= check_ring_step(ring, intel_ring_wrap(ring, x - 1), step); > + > + return err; > +} > + > +static int igt_ring_direction(void *dummy) > +{ > + struct intel_ring *ring; > + unsigned int half = 2048; > + int step, err = 0; > + > + ring = mock_ring(2 * half); > + if (!ring) > + return -ENOMEM; > + > + GEM_BUG_ON(ring->size != 2 * half); > + > + /* Precision of wrap detection is limited to ring->size / 2 */ > + for (step = 1; step < half; step <<= 1) { > + err |= check_ring_offset(ring, 0, step); > + err |= check_ring_offset(ring, half, step); > + } > + err |= check_ring_step(ring, 0, half - 64); > + > + /* And check unwrapped handling for good measure */ > + err |= check_ring_offset(ring, 0, 2 * half + 64); > + err |= check_ring_offset(ring, 3 * half, 1); > + > + mock_ring_free(ring); > + return err; > +} > + > +int intel_ring_mock_selftests(void) > +{ > + static const struct i915_subtest tests[] = { > + SUBTEST(igt_ring_direction), > + }; > + > + return i915_subtests(tests, NULL); > +} > diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > index 1929feba4e8e..3db34d3eea58 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > +++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h > @@ -21,6 +21,7 @@ selftest(fence, i915_sw_fence_mock_selftests) > selftest(scatterlist, scatterlist_mock_selftests) > selftest(syncmap, i915_syncmap_mock_selftests) > selftest(uncore, intel_uncore_mock_selftests) > +selftest(ring, intel_ring_mock_selftests) > selftest(engine, intel_engine_cs_mock_selftests) > selftest(timelines, intel_timeline_mock_selftests) > selftest(requests, i915_request_mock_selftests) > -- > 2.20.1 From thomas_os at shipmail.org Wed Jun 10 13:07:29 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Wed, 10 Jun 2020 15:07:29 +0200 Subject: [Intel-gfx] [PATCH 02/18] dma-buf: minor doc touch-ups In-Reply-To: <20200604081224.863494-3-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-3-daniel.vetter@ffwll.ch> Message-ID: <f5ffe0bf-e050-90c1-b83b-1f11fcf55012@shipmail.org> On 6/4/20 10:12 AM, Daniel Vetter wrote: > Just some tiny edits: > - fix link to struct dma_fence > - give slightly more meaningful title - the polling here is about > implicit fences, explicit fences (in sync_file or drm_syncobj) also > have their own polling > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Reviewed-by: Thomas Hellstrom <thomas.hellstrom at intel.com> From mika.kuoppala at linux.intel.com Wed Jun 10 13:21:12 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Wed, 10 Jun 2020 16:21:12 +0300 Subject: [Intel-gfx] [PATCH 03/28] drm/i915/selftests: Teach hang-self to target only itself In-Reply-To: <20200607222108.14401-3-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-3-chris@chris-wilson.co.uk> Message-ID: <877dwf9hvb.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > We have a test case to exercise resetting an engine while the other > engines are busy, all the TEST_SELF adds on top is that the target > engine also has background activity. In this case it is useful to first > test resetting the engine while there is background activity, as a > separate flag from exercising all others. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > index 035f363fb0f8..2af66f8ffbd2 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > @@ -805,10 +805,10 @@ static int __igt_reset_engines(struct intel_gt *gt, > threads[tmp].resets = > i915_reset_engine_count(global, other); > > - if (!(flags & TEST_OTHERS)) > + if (other == engine && !(flags & TEST_SELF)) > continue; > > - if (other == engine && !(flags & TEST_SELF)) > + if (other != engine && !(flags & TEST_OTHERS)) > continue; > > threads[tmp].engine = other; > @@ -999,7 +999,7 @@ static int igt_reset_engines(void *arg) > }, > { > "self-priority", > - TEST_OTHERS | TEST_ACTIVE | TEST_PRIORITY | TEST_SELF, > + TEST_ACTIVE | TEST_PRIORITY | TEST_SELF, > }, > { } > }; > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From imre.deak at intel.com Wed Jun 10 13:47:04 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 10 Jun 2020 16:47:04 +0300 Subject: [Intel-gfx] [PATCH v2 3/3] drm/dp_mst: Fix flushing the delayed port/mstb destroy work In-Reply-To: <20200607212522.16935-3-imre.deak@intel.com> References: <20200607212522.16935-3-imre.deak@intel.com> Message-ID: <20200610134704.25270-1-imre.deak@intel.com> Atm, a pending delayed destroy work during module removal will be canceled, leaving behind MST ports, mstbs. Fix this by using a dedicated workqueue which will be drained of requeued items as well when destroying it. v2: - Check if wq is NULL before calling destroy_workqueue(). Cc: Lyude Paul <lyude at redhat.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 19 ++++++++++++++++--- include/drm/drm_dp_mst_helper.h | 8 ++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index eff8d6ac0273..a5f67b9db7fa 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1604,7 +1604,7 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) mutex_lock(&mgr->delayed_destroy_lock); list_add(&mstb->destroy_next, &mgr->destroy_branch_device_list); mutex_unlock(&mgr->delayed_destroy_lock); - schedule_work(&mgr->delayed_destroy_work); + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); } /** @@ -1721,7 +1721,7 @@ static void drm_dp_destroy_port(struct kref *kref) mutex_lock(&mgr->delayed_destroy_lock); list_add(&port->next, &mgr->destroy_port_list); mutex_unlock(&mgr->delayed_destroy_lock); - schedule_work(&mgr->delayed_destroy_work); + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); } /** @@ -5182,6 +5182,15 @@ int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, INIT_LIST_HEAD(&mgr->destroy_port_list); INIT_LIST_HEAD(&mgr->destroy_branch_device_list); INIT_LIST_HEAD(&mgr->up_req_list); + + /* + * delayed_destroy_work will be queued on a dedicated WQ, so that any + * requeuing will be also flushed when deiniting the topology manager. + */ + mgr->delayed_destroy_wq = alloc_ordered_workqueue("drm_dp_mst_wq", 0); + if (mgr->delayed_destroy_wq == NULL) + return -ENOMEM; + INIT_WORK(&mgr->work, drm_dp_mst_link_probe_work); INIT_WORK(&mgr->tx_work, drm_dp_tx_work); INIT_WORK(&mgr->delayed_destroy_work, drm_dp_delayed_destroy_work); @@ -5226,7 +5235,11 @@ void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr) { drm_dp_mst_topology_mgr_set_mst(mgr, false); flush_work(&mgr->work); - cancel_work_sync(&mgr->delayed_destroy_work); + /* The following will also drain any requeued work on the WQ. */ + if (mgr->delayed_destroy_wq) { + destroy_workqueue(mgr->delayed_destroy_wq); + mgr->delayed_destroy_wq = NULL; + } mutex_lock(&mgr->payload_lock); kfree(mgr->payloads); mgr->payloads = NULL; diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 9e1ffcd7cb68..17b568c6f4f8 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -672,6 +672,14 @@ struct drm_dp_mst_topology_mgr { * @destroy_branch_device_list. */ struct mutex delayed_destroy_lock; + + /** + * @delayed_destroy_wq: Workqueue used for delayed_destroy_work items. + * A dedicated WQ makes it possible to drain any requeued work items + * on it. + */ + struct workqueue_struct *delayed_destroy_wq; + /** * @delayed_destroy_work: Work item to destroy MST port and branch * devices, needed to avoid locking inversion. -- 2.23.1 From patchwork at emeril.freedesktop.org Wed Jun 10 13:56:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 13:56:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/3=5D_drm/dp=5Fmst=3A_Fix_the_DDC_?= =?utf-8?q?I2C_device_unregistration_of_an_MST_port_=28rev2=29?= In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <159179741291.20177.10216029220599398910@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port (rev2) URL : https://patchwork.freedesktop.org/series/78100/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1a8e3c0e3676 drm/dp_mst: Fix the DDC I2C device unregistration of an MST port -:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #13: Note that atm, inconsistently, the parent of the I2C device is initially set to total: 0 errors, 1 warnings, 0 checks, 14 lines checked 8be818a9eda8 drm/dp_mst: Fix the DDC I2C device registration of an MST port ae88a71f3c39 drm/dp_mst: Fix flushing the delayed port/mstb destroy work -:51: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!mgr->delayed_destroy_wq" #51: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:5191: + if (mgr->delayed_destroy_wq == NULL) total: 0 errors, 0 warnings, 1 checks, 57 lines checked From chris at chris-wilson.co.uk Wed Jun 10 14:03:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 10 Jun 2020 15:03:58 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Incrementally check for rewinding In-Reply-To: <bf5c088a-731a-7bc4-ff90-492f18e55045@intel.com> References: <20200609122856.10207-1-chris@chris-wilson.co.uk> <20200609151723.12971-1-chris@chris-wilson.co.uk> <bf5c088a-731a-7bc4-ff90-492f18e55045@intel.com> Message-ID: <159179783861.19008.3331899086436292993@build.alporthouse.com> Quoting Chang, Bruce (2020-06-10 05:25:39) > On 6/9/2020 8:17 AM, Chris Wilson wrote: > > In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context > > reload when rewinding RING_TAIL"), we placed the check for rewinding a > > context on actually submitting the next request in that context. This > > was so that we only had to check once, and could do so with precision > > avoiding as many forced restores as possible. For example, to ensure > > that we can resubmit the same request a couple of times, we include a > > small wa_tail such that on the next submission, the ring->tail will > > appear to move forwards when resubmitting the same request. This is very > > common as it will happen for every lite-restore to fill the second port > > after a context switch. > > > > However, intel_ring_direction() is limited in precision to movements of > > upto half the ring size. The consequence being that if we tried to > > unwind many requests, we could exceed half the ring and flip the sense > > of the direction, so missing a force restore. As no request can be > > greater than half the ring (i.e. 2048 bytes in the smallest case), we > > can check for rollback incrementally. As we check against the tail that > > would be submitted, we do not lose any sensitivity and allow lite > > restores for the simple case. We still need to double check upon > > submitting the context, to allow for multiple preemptions and > > resubmissions. > > > > Fixes: 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL") > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > > Cc: <stable at vger.kernel.org> # v5.4+ > > Verified this has fixed the issue regarding the GPU hang with incomplete > error state. But it does not entirely... tgl b0 still has the issue of a lite restore being processed while it is doing an [implicit] semaphore wait at just the wrong time, dies (or something that looks suspiciously like that). That can be reproduced without any preemption rollback, so I suspect a placebo effect. -Chris From patchwork at emeril.freedesktop.org Wed Jun 10 14:18:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 14:18:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/dp=5Fmst=3A_Fix_the_DDC_I2C_dev?= =?utf-8?q?ice_unregistration_of_an_MST_port_=28rev2=29?= In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <159179869806.20176.15788112645960398286@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port (rev2) URL : https://patchwork.freedesktop.org/series/78100/ State : success == Summary == CI Bug Log - changes from CI_DRM_8608 -> Patchwork_17919 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/index.html Known issues ------------ Here are the changes found in Patchwork_17919 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-byt-n2820/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][9] ([i915#95]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +6 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#1982] / [i915#62] / [i915#92]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8608 -> Patchwork_17919 CI-20190529: 20190529 CI_DRM_8608: e7b23e6cc4cdd7ad191bb039f803a2f13e4a0e40 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17919: ae88a71f3c396ee528050ee86509f65af8509303 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ae88a71f3c39 drm/dp_mst: Fix flushing the delayed port/mstb destroy work 8be818a9eda8 drm/dp_mst: Fix the DDC I2C device registration of an MST port 1a8e3c0e3676 drm/dp_mst: Fix the DDC I2C device unregistration of an MST port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/index.html From tvrtko.ursulin at linux.intel.com Wed Jun 10 14:21:53 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 10 Jun 2020 15:21:53 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <20200604081224.863494-4-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> Message-ID: <be3526aa-07db-adc0-9291-1b5aeb0d1613@linux.intel.com> On 04/06/2020 09:12, Daniel Vetter wrote: > Design is similar to the lockdep annotations for workers, but with > some twists: > > - We use a read-lock for the execution/worker/completion side, so that > this explicit annotation can be more liberally sprinkled around. > With read locks lockdep isn't going to complain if the read-side > isn't nested the same way under all circumstances, so ABBA deadlocks > are ok. Which they are, since this is an annotation only. > > - We're using non-recursive lockdep read lock mode, since in recursive > read lock mode lockdep does not catch read side hazards. And we > _very_ much want read side hazards to be caught. For full details of > this limitation see > > commit e91498589746065e3ae95d9a00b068e525eec34f > Author: Peter Zijlstra <peterz at infradead.org> > Date: Wed Aug 23 13:13:11 2017 +0200 > > locking/lockdep/selftests: Add mixed read-write ABBA tests > > - To allow nesting of the read-side explicit annotations we explicitly > keep track of the nesting. lock_is_held() allows us to do that. > > - The wait-side annotation is a write lock, and entirely done within > dma_fence_wait() for everyone by default. > > - To be able to freely annotate helper functions I want to make it ok > to call dma_fence_begin/end_signalling from soft/hardirq context. > First attempt was using the hardirq locking context for the write > side in lockdep, but this forces all normal spinlocks nested within > dma_fence_begin/end_signalling to be spinlocks. That bollocks. > > The approach now is to simple check in_atomic(), and for these cases > entirely rely on the might_sleep() check in dma_fence_wait(). That > will catch any wrong nesting against spinlocks from soft/hardirq > contexts. > > The idea here is that every code path that's critical for eventually > signalling a dma_fence should be annotated with > dma_fence_begin/end_signalling. The annotation ideally starts right > after a dma_fence is published (added to a dma_resv, exposed as a > sync_file fd, attached to a drm_syncobj fd, or anything else that > makes the dma_fence visible to other kernel threads), up to and > including the dma_fence_wait(). Examples are irq handlers, the > scheduler rt threads, the tail of execbuf (after the corresponding > fences are visible), any workers that end up signalling dma_fences and > really anything else. Not annotated should be code paths that only > complete fences opportunistically as the gpu progresses, like e.g. > shrinker/eviction code. > > The main class of deadlocks this is supposed to catch are: > > Thread A: > > mutex_lock(A); > mutex_unlock(A); > > dma_fence_signal(); > > Thread B: > > mutex_lock(A); > dma_fence_wait(); > mutex_unlock(A); > > Thread B is blocked on A signalling the fence, but A never gets around > to that because it cannot acquire the lock A. > > Note that dma_fence_wait() is allowed to be nested within > dma_fence_begin/end_signalling sections. To allow this to happen the > read lock needs to be upgraded to a write lock, which means that any > other lock is acquired between the dma_fence_begin_signalling() call and > the call to dma_fence_wait(), and still held, this will result in an > immediate lockdep complaint. The only other option would be to not > annotate such calls, defeating the point. Therefore these annotations > cannot be sprinkled over the code entirely mindless to avoid false > positives. > > v2: handle soft/hardirq ctx better against write side and dont forget > EXPORT_SYMBOL, drivers can't use this otherwise. > > v3: Kerneldoc. > > v4: Some spelling fixes from Mika > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > Cc: linux-media at vger.kernel.org > Cc: linaro-mm-sig at lists.linaro.org > Cc: linux-rdma at vger.kernel.org > Cc: amd-gfx at lists.freedesktop.org > Cc: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > Documentation/driver-api/dma-buf.rst | 12 +- > drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ > include/linux/dma-fence.h | 12 ++ > 3 files changed, 182 insertions(+), 3 deletions(-) > > diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > index 63dec76d1d8d..05d856131140 100644 > --- a/Documentation/driver-api/dma-buf.rst > +++ b/Documentation/driver-api/dma-buf.rst > @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > .. kernel-doc:: drivers/dma-buf/dma-buf.c > :doc: cpu access > > -Fence Poll Support > -~~~~~~~~~~~~~~~~~~ > +Implicit Fence Poll Support > +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > - :doc: fence polling > + :doc: implicit fence polling > > Kernel Functions and Structures Reference > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > @@ -133,6 +133,12 @@ DMA Fences > .. kernel-doc:: drivers/dma-buf/dma-fence.c > :doc: DMA fences overview > > +DMA Fence Signalling Annotations > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +.. kernel-doc:: drivers/dma-buf/dma-fence.c > + :doc: fence signalling annotation > + > DMA Fences Functions Reference > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > index 656e9ac2d028..0005bc002529 100644 > --- a/drivers/dma-buf/dma-fence.c > +++ b/drivers/dma-buf/dma-fence.c > @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) > } > EXPORT_SYMBOL(dma_fence_context_alloc); > > +/** > + * DOC: fence signalling annotation > + * > + * Proving correctness of all the kernel code around &dma_fence through code > + * review and testing is tricky for a few reasons: > + * > + * * It is a cross-driver contract, and therefore all drivers must follow the > + * same rules for lock nesting order, calling contexts for various functions > + * and anything else significant for in-kernel interfaces. But it is also > + * impossible to test all drivers in a single machine, hence brute-force N vs. > + * N testing of all combinations is impossible. Even just limiting to the > + * possible combinations is infeasible. > + * > + * * There is an enormous amount of driver code involved. For render drivers > + * there's the tail of command submission, after fences are published, > + * scheduler code, interrupt and workers to process job completion, > + * and timeout, gpu reset and gpu hang recovery code. Plus for integration > + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, > + * and &shrinker. For modesetting drivers there's the commit tail functions > + * between when fences for an atomic modeset are published, and when the > + * corresponding vblank completes, including any interrupt processing and > + * related workers. Auditing all that code, across all drivers, is not > + * feasible. > + * > + * * Due to how many other subsystems are involved and the locking hierarchies > + * this pulls in there is extremely thin wiggle-room for driver-specific > + * differences. &dma_fence interacts with almost all of the core memory > + * handling through page fault handlers via &dma_resv, dma_resv_lock() and > + * dma_resv_unlock(). On the other side it also interacts through all > + * allocation sites through &mmu_notifier and &shrinker. > + * > + * Furthermore lockdep does not handle cross-release dependencies, which means > + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught > + * at runtime with some quick testing. The simplest example is one thread > + * waiting on a &dma_fence while holding a lock:: > + * > + * lock(A); > + * dma_fence_wait(B); > + * unlock(A); > + * > + * while the other thread is stuck trying to acquire the same lock, which > + * prevents it from signalling the fence the previous thread is stuck waiting > + * on:: > + * > + * lock(A); > + * unlock(A); > + * dma_fence_signal(B); > + * > + * By manually annotating all code relevant to signalling a &dma_fence we can > + * teach lockdep about these dependencies, which also helps with the validation > + * headache since now lockdep can check all the rules for us:: > + * > + * cookie = dma_fence_begin_signalling(); > + * lock(A); > + * unlock(A); > + * dma_fence_signal(B); > + * dma_fence_end_signalling(cookie); > + * > + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to > + * annotate critical sections the following rules need to be observed: > + * > + * * All code necessary to complete a &dma_fence must be annotated, from the > + * point where a fence is accessible to other threads, to the point where > + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, > + * and due to the very strict rules and many corner cases it is infeasible to > + * catch these just with review or normal stress testing. > + * > + * * &struct dma_resv deserves a special note, since the readers are only > + * protected by rcu. This means the signalling critical section starts as soon > + * as the new fences are installed, even before dma_resv_unlock() is called. > + * > + * * The only exception are fast paths and opportunistic signalling code, which > + * calls dma_fence_signal() purely as an optimization, but is not required to > + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL > + * which calls dma_fence_signal(), while the mandatory completion path goes > + * through a hardware interrupt and possible job completion worker. > + * > + * * To aid composability of code, the annotations can be freely nested, as long > + * as the overall locking hierarchy is consistent. The annotations also work > + * both in interrupt and process context. Due to implementation details this > + * requires that callers pass an opaque cookie from > + * dma_fence_begin_signalling() to dma_fence_end_signalling(). > + * > + * * Validation against the cross driver contract is implemented by priming > + * lockdep with the relevant hierarchy at boot-up. This means even just > + * testing with a single device is enough to validate a driver, at least as > + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are > + * concerned. > + */ > +#ifdef CONFIG_LOCKDEP > +struct lockdep_map dma_fence_lockdep_map = { > + .name = "dma_fence_map" > +}; Maybe a stupid question because this is definitely complicated, but.. If you have a single/static/global lockdep map, doesn't this mean _all_ locks, from _all_ drivers happening to use dma-fences will get recorded in it. Will this work and not cause false positives? Sounds like it could create a common link between two completely unconnected usages. Because below you do add annotations to generic dma_fence_signal and dma_fence_wait. > + > +/** > + * dma_fence_begin_signalling - begin a critical DMA fence signalling section > + * > + * Drivers should use this to annotate the beginning of any code section > + * required to eventually complete &dma_fence by calling dma_fence_signal(). > + * > + * The end of these critical sections are annotated with > + * dma_fence_end_signalling(). > + * > + * Returns: > + * > + * Opaque cookie needed by the implementation, which needs to be passed to > + * dma_fence_end_signalling(). > + */ > +bool dma_fence_begin_signalling(void) > +{ > + /* explicitly nesting ... */ > + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) > + return true; > + > + /* rely on might_sleep check for soft/hardirq locks */ > + if (in_atomic()) > + return true; > + > + /* ... and non-recursive readlock */ > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); Would it work if signalling path would mark itself as a write lock? I am thinking it would be nice to see in lockdep splats what are signals and what are waits. The recursive usage wouldn't work then right? Would write annotation on the wait path work? Regards, Tvrtko > + > + return false; > +} > +EXPORT_SYMBOL(dma_fence_begin_signalling); > + > +/** > + * dma_fence_end_signalling - end a critical DMA fence signalling section > + * > + * Closes a critical section annotation opened by dma_fence_begin_signalling(). > + */ > +void dma_fence_end_signalling(bool cookie) > +{ > + if (cookie) > + return; > + > + lock_release(&dma_fence_lockdep_map, _RET_IP_); > +} > +EXPORT_SYMBOL(dma_fence_end_signalling); > + > +void __dma_fence_might_wait(void) > +{ > + bool tmp; > + > + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); > + if (tmp) > + lock_release(&dma_fence_lockdep_map, _THIS_IP_); > + lock_map_acquire(&dma_fence_lockdep_map); > + lock_map_release(&dma_fence_lockdep_map); > + if (tmp) > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > +} > +#endif > + > + > /** > * dma_fence_signal_locked - signal completion of a fence > * @fence: the fence to signal > @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) > { > unsigned long flags; > int ret; > + bool tmp; > > if (!fence) > return -EINVAL; > > + tmp = dma_fence_begin_signalling(); > + > spin_lock_irqsave(fence->lock, flags); > ret = dma_fence_signal_locked(fence); > spin_unlock_irqrestore(fence->lock, flags); > > + dma_fence_end_signalling(tmp); > + > return ret; > } > EXPORT_SYMBOL(dma_fence_signal); > @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) > > might_sleep(); > > + __dma_fence_might_wait(); > + > trace_dma_fence_wait_start(fence); > if (fence->ops->wait) > ret = fence->ops->wait(fence, intr, timeout); > diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h > index 3347c54f3a87..3f288f7db2ef 100644 > --- a/include/linux/dma-fence.h > +++ b/include/linux/dma-fence.h > @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) > } while (1); > } > > +#ifdef CONFIG_LOCKDEP > +bool dma_fence_begin_signalling(void); > +void dma_fence_end_signalling(bool cookie); > +#else > +static inline bool dma_fence_begin_signalling(void) > +{ > + return true; > +} > +static inline void dma_fence_end_signalling(bool cookie) {} > +static inline void __dma_fence_might_wait(void) {} > +#endif > + > int dma_fence_signal(struct dma_fence *fence); > int dma_fence_signal_locked(struct dma_fence *fence); > signed long dma_fence_default_wait(struct dma_fence *fence, > From daniel.vetter at ffwll.ch Wed Jun 10 15:17:02 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Wed, 10 Jun 2020 17:17:02 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <be3526aa-07db-adc0-9291-1b5aeb0d1613@linux.intel.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <be3526aa-07db-adc0-9291-1b5aeb0d1613@linux.intel.com> Message-ID: <CAKMK7uE4ak=gaKNJziaLg1qN1mE1FKLW1MGFkmUz2tR2y0ArAA@mail.gmail.com> On Wed, Jun 10, 2020 at 4:22 PM Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> wrote: > > > On 04/06/2020 09:12, Daniel Vetter wrote: > > Design is similar to the lockdep annotations for workers, but with > > some twists: > > > > - We use a read-lock for the execution/worker/completion side, so that > > this explicit annotation can be more liberally sprinkled around. > > With read locks lockdep isn't going to complain if the read-side > > isn't nested the same way under all circumstances, so ABBA deadlocks > > are ok. Which they are, since this is an annotation only. > > > > - We're using non-recursive lockdep read lock mode, since in recursive > > read lock mode lockdep does not catch read side hazards. And we > > _very_ much want read side hazards to be caught. For full details of > > this limitation see > > > > commit e91498589746065e3ae95d9a00b068e525eec34f > > Author: Peter Zijlstra <peterz at infradead.org> > > Date: Wed Aug 23 13:13:11 2017 +0200 > > > > locking/lockdep/selftests: Add mixed read-write ABBA tests > > > > - To allow nesting of the read-side explicit annotations we explicitly > > keep track of the nesting. lock_is_held() allows us to do that. > > > > - The wait-side annotation is a write lock, and entirely done within > > dma_fence_wait() for everyone by default. > > > > - To be able to freely annotate helper functions I want to make it ok > > to call dma_fence_begin/end_signalling from soft/hardirq context. > > First attempt was using the hardirq locking context for the write > > side in lockdep, but this forces all normal spinlocks nested within > > dma_fence_begin/end_signalling to be spinlocks. That bollocks. > > > > The approach now is to simple check in_atomic(), and for these cases > > entirely rely on the might_sleep() check in dma_fence_wait(). That > > will catch any wrong nesting against spinlocks from soft/hardirq > > contexts. > > > > The idea here is that every code path that's critical for eventually > > signalling a dma_fence should be annotated with > > dma_fence_begin/end_signalling. The annotation ideally starts right > > after a dma_fence is published (added to a dma_resv, exposed as a > > sync_file fd, attached to a drm_syncobj fd, or anything else that > > makes the dma_fence visible to other kernel threads), up to and > > including the dma_fence_wait(). Examples are irq handlers, the > > scheduler rt threads, the tail of execbuf (after the corresponding > > fences are visible), any workers that end up signalling dma_fences and > > really anything else. Not annotated should be code paths that only > > complete fences opportunistically as the gpu progresses, like e.g. > > shrinker/eviction code. > > > > The main class of deadlocks this is supposed to catch are: > > > > Thread A: > > > > mutex_lock(A); > > mutex_unlock(A); > > > > dma_fence_signal(); > > > > Thread B: > > > > mutex_lock(A); > > dma_fence_wait(); > > mutex_unlock(A); > > > > Thread B is blocked on A signalling the fence, but A never gets around > > to that because it cannot acquire the lock A. > > > > Note that dma_fence_wait() is allowed to be nested within > > dma_fence_begin/end_signalling sections. To allow this to happen the > > read lock needs to be upgraded to a write lock, which means that any > > other lock is acquired between the dma_fence_begin_signalling() call and > > the call to dma_fence_wait(), and still held, this will result in an > > immediate lockdep complaint. The only other option would be to not > > annotate such calls, defeating the point. Therefore these annotations > > cannot be sprinkled over the code entirely mindless to avoid false > > positives. > > > > v2: handle soft/hardirq ctx better against write side and dont forget > > EXPORT_SYMBOL, drivers can't use this otherwise. > > > > v3: Kerneldoc. > > > > v4: Some spelling fixes from Mika > > > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > > Cc: linux-media at vger.kernel.org > > Cc: linaro-mm-sig at lists.linaro.org > > Cc: linux-rdma at vger.kernel.org > > Cc: amd-gfx at lists.freedesktop.org > > Cc: intel-gfx at lists.freedesktop.org > > Cc: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > --- > > Documentation/driver-api/dma-buf.rst | 12 +- > > drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ > > include/linux/dma-fence.h | 12 ++ > > 3 files changed, 182 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > > index 63dec76d1d8d..05d856131140 100644 > > --- a/Documentation/driver-api/dma-buf.rst > > +++ b/Documentation/driver-api/dma-buf.rst > > @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > > :doc: cpu access > > > > -Fence Poll Support > > -~~~~~~~~~~~~~~~~~~ > > +Implicit Fence Poll Support > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > > - :doc: fence polling > > + :doc: implicit fence polling > > > > Kernel Functions and Structures Reference > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > @@ -133,6 +133,12 @@ DMA Fences > > .. kernel-doc:: drivers/dma-buf/dma-fence.c > > :doc: DMA fences overview > > > > +DMA Fence Signalling Annotations > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > + > > +.. kernel-doc:: drivers/dma-buf/dma-fence.c > > + :doc: fence signalling annotation > > + > > DMA Fences Functions Reference > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > > index 656e9ac2d028..0005bc002529 100644 > > --- a/drivers/dma-buf/dma-fence.c > > +++ b/drivers/dma-buf/dma-fence.c > > @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) > > } > > EXPORT_SYMBOL(dma_fence_context_alloc); > > > > +/** > > + * DOC: fence signalling annotation > > + * > > + * Proving correctness of all the kernel code around &dma_fence through code > > + * review and testing is tricky for a few reasons: > > + * > > + * * It is a cross-driver contract, and therefore all drivers must follow the > > + * same rules for lock nesting order, calling contexts for various functions > > + * and anything else significant for in-kernel interfaces. But it is also > > + * impossible to test all drivers in a single machine, hence brute-force N vs. > > + * N testing of all combinations is impossible. Even just limiting to the > > + * possible combinations is infeasible. > > + * > > + * * There is an enormous amount of driver code involved. For render drivers > > + * there's the tail of command submission, after fences are published, > > + * scheduler code, interrupt and workers to process job completion, > > + * and timeout, gpu reset and gpu hang recovery code. Plus for integration > > + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, > > + * and &shrinker. For modesetting drivers there's the commit tail functions > > + * between when fences for an atomic modeset are published, and when the > > + * corresponding vblank completes, including any interrupt processing and > > + * related workers. Auditing all that code, across all drivers, is not > > + * feasible. > > + * > > + * * Due to how many other subsystems are involved and the locking hierarchies > > + * this pulls in there is extremely thin wiggle-room for driver-specific > > + * differences. &dma_fence interacts with almost all of the core memory > > + * handling through page fault handlers via &dma_resv, dma_resv_lock() and > > + * dma_resv_unlock(). On the other side it also interacts through all > > + * allocation sites through &mmu_notifier and &shrinker. > > + * > > + * Furthermore lockdep does not handle cross-release dependencies, which means > > + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught > > + * at runtime with some quick testing. The simplest example is one thread > > + * waiting on a &dma_fence while holding a lock:: > > + * > > + * lock(A); > > + * dma_fence_wait(B); > > + * unlock(A); > > + * > > + * while the other thread is stuck trying to acquire the same lock, which > > + * prevents it from signalling the fence the previous thread is stuck waiting > > + * on:: > > + * > > + * lock(A); > > + * unlock(A); > > + * dma_fence_signal(B); > > + * > > + * By manually annotating all code relevant to signalling a &dma_fence we can > > + * teach lockdep about these dependencies, which also helps with the validation > > + * headache since now lockdep can check all the rules for us:: > > + * > > + * cookie = dma_fence_begin_signalling(); > > + * lock(A); > > + * unlock(A); > > + * dma_fence_signal(B); > > + * dma_fence_end_signalling(cookie); > > + * > > + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to > > + * annotate critical sections the following rules need to be observed: > > + * > > + * * All code necessary to complete a &dma_fence must be annotated, from the > > + * point where a fence is accessible to other threads, to the point where > > + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, > > + * and due to the very strict rules and many corner cases it is infeasible to > > + * catch these just with review or normal stress testing. > > + * > > + * * &struct dma_resv deserves a special note, since the readers are only > > + * protected by rcu. This means the signalling critical section starts as soon > > + * as the new fences are installed, even before dma_resv_unlock() is called. > > + * > > + * * The only exception are fast paths and opportunistic signalling code, which > > + * calls dma_fence_signal() purely as an optimization, but is not required to > > + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL > > + * which calls dma_fence_signal(), while the mandatory completion path goes > > + * through a hardware interrupt and possible job completion worker. > > + * > > + * * To aid composability of code, the annotations can be freely nested, as long > > + * as the overall locking hierarchy is consistent. The annotations also work > > + * both in interrupt and process context. Due to implementation details this > > + * requires that callers pass an opaque cookie from > > + * dma_fence_begin_signalling() to dma_fence_end_signalling(). > > + * > > + * * Validation against the cross driver contract is implemented by priming > > + * lockdep with the relevant hierarchy at boot-up. This means even just > > + * testing with a single device is enough to validate a driver, at least as > > + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are > > + * concerned. > > + */ > > +#ifdef CONFIG_LOCKDEP > > +struct lockdep_map dma_fence_lockdep_map = { > > + .name = "dma_fence_map" > > +}; > > Maybe a stupid question because this is definitely complicated, but.. If > you have a single/static/global lockdep map, doesn't this mean _all_ > locks, from _all_ drivers happening to use dma-fences will get recorded > in it. Will this work and not cause false positives? > > Sounds like it could create a common link between two completely > unconnected usages. Because below you do add annotations to generic > dma_fence_signal and dma_fence_wait. This is fully intentional. dma-fence is a cross-driver interface, if every driver invents its own rules about how this should work we have an unmaintainable and unreviewable mess. I've typed up the full length rant already here: https://lore.kernel.org/dri-devel/CAKMK7uGnFhbpuurRsnZ4dvRV9gQ_3-rmSJaoqSFY=+Kvepz_CA at mail.gmail.com/ > > + > > +/** > > + * dma_fence_begin_signalling - begin a critical DMA fence signalling section > > + * > > + * Drivers should use this to annotate the beginning of any code section > > + * required to eventually complete &dma_fence by calling dma_fence_signal(). > > + * > > + * The end of these critical sections are annotated with > > + * dma_fence_end_signalling(). > > + * > > + * Returns: > > + * > > + * Opaque cookie needed by the implementation, which needs to be passed to > > + * dma_fence_end_signalling(). > > + */ > > +bool dma_fence_begin_signalling(void) > > +{ > > + /* explicitly nesting ... */ > > + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) > > + return true; > > + > > + /* rely on might_sleep check for soft/hardirq locks */ > > + if (in_atomic()) > > + return true; > > + > > + /* ... and non-recursive readlock */ > > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > > Would it work if signalling path would mark itself as a write lock? I am > thinking it would be nice to see in lockdep splats what are signals and > what are waits. Yeah it'd be nice to have a read vs write name for the lock. But we already have this problem for e.g. flush_work(), from which I've stolen this idea. So it's not really new. Essentially look at the backtraces lockdep gives you, and reconstruct the deadlock. I'm hoping that people will notice the special functions on the backtrace, e.g. dma_fence_begin_signalling will be listed as offending function/lock holder, and then read the kerneldoc. > The recursive usage wouldn't work then right? Would write annotation on > the wait path work? Wait path is write annotations already, but yeah annotating the signalling side as write would cause endless amounts of alse positives. Also it makes composability of these e.g. what I've done in amdgpu with annotations in tdr work in drm/scheduler, annotations in the amdgpu gpu reset code and then also annotations in atomic code, which all nest within each other in some call chains, but not others. Dropping the recursion would break that and make it really awkward to annotate such cases correctly. And the recursion only works if it's read locks, otherwise lockdep complains if you have inconsistent annotations on the signalling side (which again would make it more or less impossible to annotate the above case fully). Cheers, Daniel > > Regards, > > Tvrtko > > > + > > + return false; > > +} > > +EXPORT_SYMBOL(dma_fence_begin_signalling); > > + > > +/** > > + * dma_fence_end_signalling - end a critical DMA fence signalling section > > + * > > + * Closes a critical section annotation opened by dma_fence_begin_signalling(). > > + */ > > +void dma_fence_end_signalling(bool cookie) > > +{ > > + if (cookie) > > + return; > > + > > + lock_release(&dma_fence_lockdep_map, _RET_IP_); > > +} > > +EXPORT_SYMBOL(dma_fence_end_signalling); > > + > > +void __dma_fence_might_wait(void) > > +{ > > + bool tmp; > > + > > + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); > > + if (tmp) > > + lock_release(&dma_fence_lockdep_map, _THIS_IP_); > > + lock_map_acquire(&dma_fence_lockdep_map); > > + lock_map_release(&dma_fence_lockdep_map); > > + if (tmp) > > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > > +} > > +#endif > > + > > + > > /** > > * dma_fence_signal_locked - signal completion of a fence > > * @fence: the fence to signal > > @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) > > { > > unsigned long flags; > > int ret; > > + bool tmp; > > > > if (!fence) > > return -EINVAL; > > > > + tmp = dma_fence_begin_signalling(); > > + > > spin_lock_irqsave(fence->lock, flags); > > ret = dma_fence_signal_locked(fence); > > spin_unlock_irqrestore(fence->lock, flags); > > > > + dma_fence_end_signalling(tmp); > > + > > return ret; > > } > > EXPORT_SYMBOL(dma_fence_signal); > > @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) > > > > might_sleep(); > > > > + __dma_fence_might_wait(); > > + > > trace_dma_fence_wait_start(fence); > > if (fence->ops->wait) > > ret = fence->ops->wait(fence, intr, timeout); > > diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h > > index 3347c54f3a87..3f288f7db2ef 100644 > > --- a/include/linux/dma-fence.h > > +++ b/include/linux/dma-fence.h > > @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) > > } while (1); > > } > > > > +#ifdef CONFIG_LOCKDEP > > +bool dma_fence_begin_signalling(void); > > +void dma_fence_end_signalling(bool cookie); > > +#else > > +static inline bool dma_fence_begin_signalling(void) > > +{ > > + return true; > > +} > > +static inline void dma_fence_end_signalling(bool cookie) {} > > +static inline void __dma_fence_might_wait(void) {} > > +#endif > > + > > int dma_fence_signal(struct dma_fence *fence); > > int dma_fence_signal_locked(struct dma_fence *fence); > > signed long dma_fence_default_wait(struct dma_fence *fence, > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From chris at chris-wilson.co.uk Wed Jun 10 15:40:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 10 Jun 2020 16:40:46 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Include context status in debug dumps Message-ID: <20200610154046.22449-1-chris@chris-wilson.co.uk> This may be useful to identify contexts that are running even though they are supposed to be closed or banned. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 72f0029d490b..6d0a8ac02fb4 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1423,9 +1423,11 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, int len; len = scnprintf(hdr, sizeof(hdr), - "\t\tActive[%d]: ccid:%08x, ", + "\t\tActive[%d]: ccid:%08x%s%s, ", (int)(port - execlists->active), - rq->context->lrc.ccid); + rq->context->lrc.ccid, + intel_context_is_closed(rq->context) ? "!" : "", + intel_context_is_banned(rq->context) ? "*" : ""); len += print_ring(hdr + len, sizeof(hdr) - len, rq); scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); print_request(m, rq, hdr); @@ -1435,9 +1437,11 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, int len; len = scnprintf(hdr, sizeof(hdr), - "\t\tPending[%d]: ccid:%08x, ", + "\t\tPending[%d]: ccid:%08x%s%s, ", (int)(port - execlists->pending), - rq->context->lrc.ccid); + rq->context->lrc.ccid, + intel_context_is_closed(rq->context) ? "!" : "", + intel_context_is_banned(rq->context) ? "*" : ""); len += print_ring(hdr + len, sizeof(hdr) - len, rq); scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); print_request(m, rq, hdr); -- 2.20.1 From mika.kuoppala at linux.intel.com Wed Jun 10 15:39:59 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Wed, 10 Jun 2020 18:39:59 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Include context status in debug dumps In-Reply-To: <20200610154046.22449-1-chris@chris-wilson.co.uk> References: <20200610154046.22449-1-chris@chris-wilson.co.uk> Message-ID: <874krj9bg0.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > This may be useful to identify contexts that are running even though > they are supposed to be closed or banned. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 72f0029d490b..6d0a8ac02fb4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1423,9 +1423,11 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, > int len; > > len = scnprintf(hdr, sizeof(hdr), > - "\t\tActive[%d]: ccid:%08x, ", > + "\t\tActive[%d]: ccid:%08x%s%s, ", > (int)(port - execlists->active), > - rq->context->lrc.ccid); > + rq->context->lrc.ccid, > + intel_context_is_closed(rq->context) ? "!" : "", > + intel_context_is_banned(rq->context) ? "*" : ""); > len += print_ring(hdr + len, sizeof(hdr) - len, rq); > scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); > print_request(m, rq, hdr); > @@ -1435,9 +1437,11 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, > int len; > > len = scnprintf(hdr, sizeof(hdr), > - "\t\tPending[%d]: ccid:%08x, ", > + "\t\tPending[%d]: ccid:%08x%s%s, ", > (int)(port - execlists->pending), > - rq->context->lrc.ccid); > + rq->context->lrc.ccid, > + intel_context_is_closed(rq->context) ? "!" : "", > + intel_context_is_banned(rq->context) ? "*" : ""); > len += print_ring(hdr + len, sizeof(hdr) - len, rq); > scnprintf(hdr + len, sizeof(hdr) - len, "rq: "); > print_request(m, rq, hdr); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From lyude at redhat.com Wed Jun 10 15:54:30 2020 From: lyude at redhat.com (Lyude Paul) Date: Wed, 10 Jun 2020 11:54:30 -0400 Subject: [Intel-gfx] [PATCH v2 3/3] drm/dp_mst: Fix flushing the delayed port/mstb destroy work In-Reply-To: <20200610134704.25270-1-imre.deak@intel.com> References: <20200607212522.16935-3-imre.deak@intel.com> <20200610134704.25270-1-imre.deak@intel.com> Message-ID: <b7e474f0e80026565e7c7ad60a967f167e518536.camel@redhat.com> my crunch time is over so I can review these on time now :) one small comment below, although it doesn't stop me from giving my R-B here: Reviewed-by: Lyude Paul <lyude at redhat.com> On Wed, 2020-06-10 at 16:47 +0300, Imre Deak wrote: > Atm, a pending delayed destroy work during module removal will be > canceled, leaving behind MST ports, mstbs. Fix this by using a dedicated > workqueue which will be drained of requeued items as well when > destroying it. > > v2: > - Check if wq is NULL before calling destroy_workqueue(). > > Cc: Lyude Paul <lyude at redhat.com> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 19 ++++++++++++++++--- > include/drm/drm_dp_mst_helper.h | 8 ++++++++ > 2 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index eff8d6ac0273..a5f67b9db7fa 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -1604,7 +1604,7 @@ static void drm_dp_destroy_mst_branch_device(struct kref > *kref) > mutex_lock(&mgr->delayed_destroy_lock); > list_add(&mstb->destroy_next, &mgr->destroy_branch_device_list); > mutex_unlock(&mgr->delayed_destroy_lock); > - schedule_work(&mgr->delayed_destroy_work); > + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); > } > > /** > @@ -1721,7 +1721,7 @@ static void drm_dp_destroy_port(struct kref *kref) > mutex_lock(&mgr->delayed_destroy_lock); > list_add(&port->next, &mgr->destroy_port_list); > mutex_unlock(&mgr->delayed_destroy_lock); > - schedule_work(&mgr->delayed_destroy_work); > + queue_work(mgr->delayed_destroy_wq, &mgr->delayed_destroy_work); > } > > /** > @@ -5182,6 +5182,15 @@ int drm_dp_mst_topology_mgr_init(struct > drm_dp_mst_topology_mgr *mgr, > INIT_LIST_HEAD(&mgr->destroy_port_list); > INIT_LIST_HEAD(&mgr->destroy_branch_device_list); > INIT_LIST_HEAD(&mgr->up_req_list); > + > + /* > + * delayed_destroy_work will be queued on a dedicated WQ, so that any > + * requeuing will be also flushed when deiniting the topology manager. > + */ > + mgr->delayed_destroy_wq = alloc_ordered_workqueue("drm_dp_mst_wq", 0); > + if (mgr->delayed_destroy_wq == NULL) > + return -ENOMEM; > + > INIT_WORK(&mgr->work, drm_dp_mst_link_probe_work); > INIT_WORK(&mgr->tx_work, drm_dp_tx_work); > INIT_WORK(&mgr->delayed_destroy_work, drm_dp_delayed_destroy_work); > @@ -5226,7 +5235,11 @@ void drm_dp_mst_topology_mgr_destroy(struct > drm_dp_mst_topology_mgr *mgr) > { > drm_dp_mst_topology_mgr_set_mst(mgr, false); > flush_work(&mgr->work); > - cancel_work_sync(&mgr->delayed_destroy_work); > + /* The following will also drain any requeued work on the WQ. */ > + if (mgr->delayed_destroy_wq) { > + destroy_workqueue(mgr->delayed_destroy_wq); > + mgr->delayed_destroy_wq = NULL; > + } We should definitely cleanup the cleanup in this function, I don't mind submitting some patches to do it today if you poke me on IRC once you've got this pushed to drm-misc-next > mutex_lock(&mgr->payload_lock); > kfree(mgr->payloads); > mgr->payloads = NULL; > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 9e1ffcd7cb68..17b568c6f4f8 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -672,6 +672,14 @@ struct drm_dp_mst_topology_mgr { > * @destroy_branch_device_list. > */ > struct mutex delayed_destroy_lock; > + > + /** > + * @delayed_destroy_wq: Workqueue used for delayed_destroy_work items. > + * A dedicated WQ makes it possible to drain any requeued work items > + * on it. > + */ > + struct workqueue_struct *delayed_destroy_wq; > + > /** > * @delayed_destroy_work: Work item to destroy MST port and branch > * devices, needed to avoid locking inversion. From michael.j.ruhl at intel.com Wed Jun 10 16:16:55 2020 From: michael.j.ruhl at intel.com (Ruhl, Michael J) Date: Wed, 10 Jun 2020 16:16:55 +0000 Subject: [Intel-gfx] [PATCH 02/24] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <20200603145713.3835124-2-maarten.lankhorst@linux.intel.com> References: <20200603145713.3835124-1-maarten.lankhorst@linux.intel.com> <20200603145713.3835124-2-maarten.lankhorst@linux.intel.com> Message-ID: <14063C7AD467DE4B82DEDB5C278E8663010F35CE30@fmsmsx107.amr.corp.intel.com> >-----Original Message----- >From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of >Maarten Lankhorst >Sent: Wednesday, June 3, 2020 10:57 AM >To: intel-gfx at lists.freedesktop.org >Subject: [Intel-gfx] [PATCH 02/24] drm/i915: Add an implementation for >i915_gem_ww_ctx locking, v2. > >i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory >eviction. We don't use it yet, but lets start adding the definition >first. > >To use it, we have to pass a non-NULL ww to gem_object_lock, and don't >unlock directly. It is done in i915_gem_ww_ctx_fini. > >Changes since v1: >- Change ww_ctx and obj order in locking functions (Jonas Lahtinen) Not to add more patches to this patch set, but this really seems like two patches: 1) pre-work: add the new parameter to the locking (and add NULL to all the calls) 2) add the new functionality, i.e. updates to the locking code (including the test code) Finding the new functionality amongst the noise of the parameter update is a bit difficult. Splitting into makes the first patch mechanical and compile checked, and the second patch reviewable. Other than that, this looks pretty reasonable. Acked-by: Michael J. Ruhl <michael.j.ruhl at intel.com> m >Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> >--- > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- > .../gpu/drm/i915/gem/i915_gem_object_blt.c | 2 +- > .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- > .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- > .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- > .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- > .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- > .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- > drivers/gpu/drm/i915/i915_gem.h | 11 ++++ > drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ > drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- > .../drm/i915/selftests/intel_memory_region.c | 2 +- > 25 files changed, 174 insertions(+), 43 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_display.c >b/drivers/gpu/drm/i915/display/intel_display.c >index a9f752d26b4e..afa4328c3f54 100644 >--- a/drivers/gpu/drm/i915/display/intel_display.c >+++ b/drivers/gpu/drm/i915/display/intel_display.c >@@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct >drm_framebuffer *fb, > > void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) > { >- i915_gem_object_lock(vma->obj); >+ i915_gem_object_lock(vma->obj, NULL); > if (flags & PLANE_HAS_FENCE) > i915_vma_unpin_fence(vma); > i915_gem_object_unpin_from_display_plane(vma); >@@ -17112,7 +17112,7 @@ static int intel_framebuffer_init(struct >intel_framebuffer *intel_fb, > if (!intel_fb->frontbuffer) > return -ENOMEM; > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > tiling = i915_gem_object_get_tiling(obj); > stride = i915_gem_object_get_stride(obj); > i915_gem_object_unlock(obj); >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c >b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c >index d3a86a4d5c04..c182091c00ff 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c >@@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct >drm_i915_gem_object *obj, > dma_fence_init(&work->dma, &clear_pages_work_ops, >&fence_lock, 0, 0); > i915_sw_fence_init(&work->wait, clear_pages_work_notify); > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_sw_fence_await_reservation(&work->wait, > obj->base.resv, NULL, true, 0, > I915_FENCE_GFP); >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c >b/drivers/gpu/drm/i915/gem/i915_gem_context.c >index f5d59d18cd5b..46abf903dc8a 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c >@@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx) > continue; > > rcu_read_unlock(); >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > list_for_each_entry(lut, &obj->lut_list, obj_link) { > if (lut->ctx != ctx) > continue; >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c >b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c >index 2679380159fc..27fddc22a7c6 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c >@@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf >*dma_buf, enum dma_data_dire > if (err) > return err; > >- err = i915_gem_object_lock_interruptible(obj); >+ err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out; > >@@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf >*dma_buf, enum dma_data_direct > if (err) > return err; > >- err = i915_gem_object_lock_interruptible(obj); >+ err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out; > >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c >b/drivers/gpu/drm/i915/gem/i915_gem_domain.c >index 7f76fc68f498..c0acfc97fae3 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c >@@ -32,7 +32,7 @@ void i915_gem_object_flush_if_display(struct >drm_i915_gem_object *obj) > if (!i915_gem_object_is_framebuffer(obj)) > return; > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > __i915_gem_object_flush_for_display(obj); > i915_gem_object_unlock(obj); > } >@@ -197,7 +197,7 @@ int i915_gem_object_set_cache_level(struct >drm_i915_gem_object *obj, > if (ret) > return ret; > >- ret = i915_gem_object_lock_interruptible(obj); >+ ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > >@@ -536,7 +536,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, >void *data, > if (err) > goto out; > >- err = i915_gem_object_lock_interruptible(obj); >+ err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out_unpin; > >@@ -576,7 +576,7 @@ int i915_gem_object_prepare_read(struct >drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > >- ret = i915_gem_object_lock_interruptible(obj); >+ ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > >@@ -630,7 +630,7 @@ int i915_gem_object_prepare_write(struct >drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > >- ret = i915_gem_object_lock_interruptible(obj); >+ ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >index c141ce1156d7..b00b2e49a362 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >@@ -815,7 +815,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > if (err == 0) { /* And nor has this handle */ > struct drm_i915_gem_object *obj = vma->obj; > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > if (idr_find(&eb->file->object_idr, handle) == obj) { > list_add(&lut->obj_link, &obj->lut_list); > } else { >@@ -1178,7 +1178,7 @@ static void *reloc_iomap(struct >drm_i915_gem_object *obj, > if (use_cpu_reloc(cache, obj)) > return NULL; > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c >b/drivers/gpu/drm/i915/gem/i915_gem_object.c >index b6ec5b50d93b..b59e2d40c347 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c >@@ -108,7 +108,7 @@ void i915_gem_close_object(struct drm_gem_object >*gem, struct drm_file *file) > struct i915_lut_handle *lut, *ln; > LIST_HEAD(close); > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { > struct i915_gem_context *ctx = lut->ctx; > >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h >b/drivers/gpu/drm/i915/gem/i915_gem_object.h >index 2faa481cc18f..5103067269b0 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h >+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h >@@ -110,20 +110,44 @@ i915_gem_object_put(struct drm_i915_gem_object >*obj) > > #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv) > >-static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj) >+static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj, >+ struct i915_gem_ww_ctx *ww, >+ bool intr) > { >- dma_resv_lock(obj->base.resv, NULL); >+ int ret; >+ >+ if (intr) >+ ret = dma_resv_lock_interruptible(obj->base.resv, ww ? >&ww->ctx : NULL); >+ else >+ ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL); >+ >+ if (!ret && ww) >+ list_add_tail(&obj->obj_link, &ww->obj_list); >+ if (ret == -EALREADY) >+ ret = 0; >+ >+ if (ret == -EDEADLK) >+ ww->contended = obj; >+ >+ return ret; > } > >-static inline bool i915_gem_object_trylock(struct drm_i915_gem_object >*obj) >+static inline int i915_gem_object_lock(struct drm_i915_gem_object *obj, >+ struct i915_gem_ww_ctx *ww) > { >- return dma_resv_trylock(obj->base.resv); >+ return __i915_gem_object_lock(obj, ww, ww && ww->intr); > } > >-static inline int >-i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj) >+static inline int i915_gem_object_lock_interruptible(struct >drm_i915_gem_object *obj, >+ struct i915_gem_ww_ctx >*ww) > { >- return dma_resv_lock_interruptible(obj->base.resv, NULL); >+ WARN_ON(ww && !ww->intr); >+ return __i915_gem_object_lock(obj, ww, true); >+} >+ >+static inline bool i915_gem_object_trylock(struct drm_i915_gem_object >*obj) >+{ >+ return dma_resv_trylock(obj->base.resv); > } > > static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj) >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >index f457d7130491..65abc7784009 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >@@ -144,7 +144,7 @@ int i915_gem_object_fill_blt(struct >drm_i915_gem_object *obj, > return err; > > if (obj->cache_dirty & ~obj->cache_coherent) { >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > i915_gem_clflush_object(obj, 0); > i915_gem_object_unlock(obj); > } >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >index b1f82a11aef2..3740c0080e38 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >@@ -122,6 +122,15 @@ struct drm_i915_gem_object { > */ > struct list_head lut_list; > >+ /** >+ * @obj_link: Link into @i915_gem_ww_ctx.obj_list >+ * >+ * When we lock this object through i915_gem_object_lock() with a >+ * context, we add it to the list to ensure we can unlock everything >+ * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are >called. >+ */ >+ struct list_head obj_link; >+ > /** Stolen memory for this object, instead of being backed by >shmem. */ > struct drm_mm_node *stolen; > union { >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c >b/drivers/gpu/drm/i915/gem/i915_gem_pm.c >index 3d215164dd5a..40d3e40500fa 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c >@@ -84,7 +84,7 @@ void i915_gem_suspend_late(struct drm_i915_private >*i915) > > spin_unlock_irqrestore(&i915->mm.obj_lock, flags); > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > drm_WARN_ON(&i915->drm, > i915_gem_object_set_to_gtt_domain(obj, false)); > i915_gem_object_unlock(obj); >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c >b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c >index 0158e49bf9bb..65fbf29c4852 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c >@@ -249,7 +249,7 @@ i915_gem_object_set_tiling(struct >drm_i915_gem_object *obj, > * whilst executing a fenced command for an untiled object. > */ > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > if (i915_gem_object_is_framebuffer(obj)) { > i915_gem_object_unlock(obj); > return -EBUSY; >diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c >b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c >index 8291ede6902c..eb2011ccb92b 100644 >--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c >+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c >@@ -947,7 +947,7 @@ static int gpu_write(struct intel_context *ce, > { > int err; > >- i915_gem_object_lock(vma->obj); >+ i915_gem_object_lock(vma->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(vma->obj, true); > i915_gem_object_unlock(vma->obj); > if (err) >diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >index 8fe3ad2ee34e..efaa77010d6d 100644 >--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >@@ -75,7 +75,7 @@ static int __igt_client_fill(struct intel_engine_cs *engine) > if (err) > goto err_unpin; > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) >diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c >b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c >index 87d7d8aa080f..1de2959b153c 100644 >--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c >+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c >@@ -82,7 +82,7 @@ static int gtt_set(struct context *ctx, unsigned long >offset, u32 v) > u32 __iomem *map; > int err = 0; > >- i915_gem_object_lock(ctx->obj); >+ i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) >@@ -115,7 +115,7 @@ static int gtt_get(struct context *ctx, unsigned long >offset, u32 *v) > u32 __iomem *map; > int err = 0; > >- i915_gem_object_lock(ctx->obj); >+ i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); > i915_gem_object_unlock(ctx->obj); > if (err) >@@ -147,7 +147,7 @@ static int wc_set(struct context *ctx, unsigned long >offset, u32 v) > u32 *map; > int err; > >- i915_gem_object_lock(ctx->obj); >+ i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_wc_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) >@@ -170,7 +170,7 @@ static int wc_get(struct context *ctx, unsigned long >offset, u32 *v) > u32 *map; > int err; > >- i915_gem_object_lock(ctx->obj); >+ i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_wc_domain(ctx->obj, false); > i915_gem_object_unlock(ctx->obj); > if (err) >@@ -193,7 +193,7 @@ static int gpu_set(struct context *ctx, unsigned long >offset, u32 v) > u32 *cs; > int err; > >- i915_gem_object_lock(ctx->obj); >+ i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) >diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >index b81978890641..438c15ef2184 100644 >--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >@@ -950,7 +950,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, > if (IS_ERR(vma)) > return PTR_ERR(vma); > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) >@@ -1706,7 +1706,7 @@ static int read_from_scratch(struct >i915_gem_context *ctx, > > i915_request_add(rq); > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) >diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c >b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c >index 9c7402ce5bf9..9fb95a45bcad 100644 >--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c >+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c >@@ -103,7 +103,7 @@ static int check_partial_mapping(struct >drm_i915_gem_object *obj, > GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); > GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { >@@ -188,7 +188,7 @@ static int check_partial_mappings(struct >drm_i915_gem_object *obj, > GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); > GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { >diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c >b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c >index 34932871b3a5..a94243dc4c5c 100644 >--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c >+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c >@@ -44,7 +44,7 @@ static int mock_phys_object(void *arg) > } > > /* Make the object dirty so that put_pages must do copy back the >data */ >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { >diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c >b/drivers/gpu/drm/i915/gt/selftest_workarounds.c >index 32785463ec9e..6e4f7a9099d5 100644 >--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c >@@ -214,7 +214,7 @@ static int check_whitelist(struct i915_gem_context >*ctx, > return PTR_ERR(results); > > err = 0; >- i915_gem_object_lock(results); >+ i915_gem_object_lock(results, NULL); > intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! >*/ > err = i915_gem_object_set_to_cpu_domain(results, false); > i915_gem_object_unlock(results); >diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c >b/drivers/gpu/drm/i915/gvt/cmd_parser.c >index 8b87f130f7f1..b20db0d965ff 100644 >--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c >+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c >@@ -2994,7 +2994,7 @@ static int shadow_indirect_ctx(struct >intel_shadow_wa_ctx *wa_ctx) > goto put_obj; > } > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > ret = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (ret) { >diff --git a/drivers/gpu/drm/i915/i915_gem.c >b/drivers/gpu/drm/i915/i915_gem.c >index 0cbcb9f54e7d..3eedd4e0ebab 100644 >--- a/drivers/gpu/drm/i915/i915_gem.c >+++ b/drivers/gpu/drm/i915/i915_gem.c >@@ -420,7 +420,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object >*obj, > GEM_BUG_ON(!drm_mm_node_allocated(&node)); > } > >- ret = i915_gem_object_lock_interruptible(obj); >+ ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > goto out_unpin; > >@@ -619,7 +619,7 @@ i915_gem_gtt_pwrite_fast(struct >drm_i915_gem_object *obj, > GEM_BUG_ON(!drm_mm_node_allocated(&node)); > } > >- ret = i915_gem_object_lock_interruptible(obj); >+ ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > goto out_unpin; > >@@ -1272,7 +1272,7 @@ int i915_gem_freeze_late(struct drm_i915_private >*i915) > i915_gem_drain_freed_objects(i915); > > list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) { >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > drm_WARN_ON(&i915->drm, > i915_gem_object_set_to_cpu_domain(obj, true)); > i915_gem_object_unlock(obj); >@@ -1326,6 +1326,52 @@ int i915_gem_open(struct drm_i915_private *i915, >struct drm_file *file) > return ret; > } > >+void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr) >+{ >+ ww_acquire_init(&ww->ctx, &reservation_ww_class); >+ INIT_LIST_HEAD(&ww->obj_list); >+ ww->intr = intr; >+ ww->contended = NULL; >+} >+ >+static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) >+{ >+ struct drm_i915_gem_object *obj; >+ >+ while ((obj = list_first_entry_or_null(&ww->obj_list, struct >drm_i915_gem_object, obj_link))) { >+ list_del(&obj->obj_link); >+ i915_gem_object_unlock(obj); >+ } >+} >+ >+void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) >+{ >+ i915_gem_ww_ctx_unlock_all(ww); >+ WARN_ON(ww->contended); >+ ww_acquire_fini(&ww->ctx); >+} >+ >+int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx >*ww) >+{ >+ int ret = 0; >+ >+ if (WARN_ON(!ww->contended)) >+ return -EINVAL; >+ >+ i915_gem_ww_ctx_unlock_all(ww); >+ if (ww->intr) >+ ret = dma_resv_lock_slow_interruptible(ww->contended- >>base.resv, &ww->ctx); >+ else >+ dma_resv_lock_slow(ww->contended->base.resv, &ww- >>ctx); >+ >+ if (!ret) >+ list_add_tail(&ww->contended->obj_link, &ww->obj_list); >+ >+ ww->contended = NULL; >+ >+ return ret; >+} >+ > #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > #include "selftests/mock_gem_device.c" > #include "selftests/i915_gem.c" >diff --git a/drivers/gpu/drm/i915/i915_gem.h >b/drivers/gpu/drm/i915/i915_gem.h >index 1753c84d6c0d..988755dbf4be 100644 >--- a/drivers/gpu/drm/i915/i915_gem.h >+++ b/drivers/gpu/drm/i915/i915_gem.h >@@ -116,4 +116,15 @@ static inline bool __tasklet_is_scheduled(struct >tasklet_struct *t) > return test_bit(TASKLET_STATE_SCHED, &t->state); > } > >+struct i915_gem_ww_ctx { >+ struct ww_acquire_ctx ctx; >+ struct list_head obj_list; >+ bool intr; >+ struct drm_i915_gem_object *contended; >+}; >+ >+void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); >+void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); >+int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx >*ctx); >+ > #endif /* __I915_GEM_H__ */ >diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c >b/drivers/gpu/drm/i915/selftests/i915_gem.c >index 88d400b9df88..23a6132c5f4e 100644 >--- a/drivers/gpu/drm/i915/selftests/i915_gem.c >+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c >@@ -199,11 +199,52 @@ static int igt_gem_hibernate(void *arg) > return err; > } > >+static int igt_gem_ww_ctx(void *arg) >+{ >+ struct drm_i915_private *i915 = arg; >+ struct drm_i915_gem_object *obj, *obj2; >+ struct i915_gem_ww_ctx ww; >+ int err = 0; >+ >+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE); >+ if (IS_ERR(obj)) >+ return PTR_ERR(obj); >+ >+ obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE); >+ if (IS_ERR(obj)) { >+ err = PTR_ERR(obj); >+ goto put1; >+ } >+ >+ i915_gem_ww_ctx_init(&ww, true); >+retry: >+ /* Lock the objects, twice for good measure (-EALREADY handling) */ >+ err = i915_gem_object_lock(obj, &ww); >+ if (!err) >+ err = i915_gem_object_lock_interruptible(obj, &ww); >+ if (!err) >+ err = i915_gem_object_lock_interruptible(obj2, &ww); >+ if (!err) >+ err = i915_gem_object_lock(obj2, &ww); >+ >+ if (err == -EDEADLK) { >+ err = i915_gem_ww_ctx_backoff(&ww); >+ if (!err) >+ goto retry; >+ } >+ i915_gem_ww_ctx_fini(&ww); >+ i915_gem_object_put(obj2); >+put1: >+ i915_gem_object_put(obj); >+ return err; >+} >+ > int i915_gem_live_selftests(struct drm_i915_private *i915) > { > static const struct i915_subtest tests[] = { > SUBTEST(igt_gem_suspend), > SUBTEST(igt_gem_hibernate), >+ SUBTEST(igt_gem_ww_ctx), > }; > > if (intel_gt_is_wedged(&i915->gt)) >diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c >b/drivers/gpu/drm/i915/selftests/i915_vma.c >index af89c7fc8f59..88c5e9acb84c 100644 >--- a/drivers/gpu/drm/i915/selftests/i915_vma.c >+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c >@@ -892,7 +892,7 @@ static int igt_vma_remapped_gtt(void *arg) > unsigned int x, y; > int err; > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) >diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c >b/drivers/gpu/drm/i915/selftests/intel_memory_region.c >index 6e80d99048e4..957a7a52def7 100644 >--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c >+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c >@@ -509,7 +509,7 @@ static int igt_lmem_write_cpu(void *arg) > if (err) > goto out_unpin; > >- i915_gem_object_lock(obj); >+ i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_wc_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) >-- >2.26.2 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx at lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Wed Jun 10 17:15:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 17:15:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Include_context_status_in_debug_dumps?= In-Reply-To: <20200610154046.22449-1-chris@chris-wilson.co.uk> References: <20200610154046.22449-1-chris@chris-wilson.co.uk> Message-ID: <159180930765.20174.2697084476469087775@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Include context status in debug dumps URL : https://patchwork.freedesktop.org/series/78188/ State : success == Summary == CI Bug Log - changes from CI_DRM_8610 -> Patchwork_17920 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/index.html Known issues ------------ Here are the changes found in Patchwork_17920 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-bxt-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-bxt-dsi/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-bxt-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-kbl-x1275/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8610 -> Patchwork_17920 CI-20190529: 20190529 CI_DRM_8610: 5a778c71b283ff1a2af242f02e602c11b9490e3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17920: af201da28116f5b1b2ce11c9db8b5ebd1343dcd6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == af201da28116 drm/i915/gt: Include context status in debug dumps == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/index.html From imre.deak at intel.com Wed Jun 10 18:31:31 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 10 Jun 2020 21:31:31 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix DP MST ACT status handling Message-ID: <20200610183132.13341-1-imre.deak@intel.com> On TGL+ the master transcoder's DP_TP_STATUS register should be used for the MST ACT status handling, so make sure we do that even in case of mulitple streams. This fixes an ACT timeout problem during disabling when using multiple streams. Not sure why this was not a problem during enabling (even the slave's DP_TP_STATUS signaled ACT correctly), but following the spec works in that case too, so let's do that. There is one more place using DP_TP_STATUS, FEC enabling, but I haven't found in BSpec which register to use in that case, so I leave the clarification of that for later. BSpec: 49190 Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++---- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d18b406f2a7d..1c3654a117a9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -316,6 +316,40 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, return ret; } +static i915_reg_t +master_dp_tp_status_reg(const struct intel_crtc_state *crtc_state, + const struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + + if (INTEL_GEN(dev_priv) >= 12) + return TGL_DP_TP_STATUS(crtc_state->mst_master_transcoder); + + return intel_dp->regs.dp_tp_status; +} + +static void clear_act_sent(const struct intel_crtc_state *crtc_state, + const struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + i915_reg_t dp_tp_status_reg = + master_dp_tp_status_reg(crtc_state, intel_dp); + + intel_de_write(i915, dp_tp_status_reg, + intel_de_read(i915, dp_tp_status_reg)); +} + +static bool wait_for_act_sent(const struct intel_crtc_state *crtc_state, + const struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + i915_reg_t dp_tp_status_reg = + master_dp_tp_status_reg(crtc_state, intel_dp); + + return intel_de_wait_for_set(i915, dp_tp_status_reg, + DP_TP_STATUS_ACT_SENT, 1) == 0; +} + static void intel_mst_disable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, @@ -376,8 +410,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), val); - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, - DP_TP_STATUS_ACT_SENT, 1)) + if (!wait_for_act_sent(old_crtc_state, intel_dp)) drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when disabling\n"); drm_dp_check_act_status(&intel_dp->mst_mgr); @@ -443,7 +476,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, struct intel_connector *connector = to_intel_connector(conn_state->connector); int ret; - u32 temp; bool first_mst_stream; /* MST encoders are bound to a crtc, not to a connector, @@ -476,8 +508,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); intel_dp->active_mst_links++; - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); + + clear_act_sent(pipe_config, intel_dp); ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); @@ -513,9 +545,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_dbg_kms(&dev_priv->drm, "active links %d\n", intel_dp->active_mst_links); - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, - DP_TP_STATUS_ACT_SENT, 1)) - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); + if (!wait_for_act_sent(pipe_config, intel_dp)) + drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when enabling\n"); drm_dp_check_act_status(&intel_dp->mst_mgr); -- 2.23.1 From imre.deak at intel.com Wed Jun 10 18:31:32 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 10 Jun 2020 21:31:32 +0300 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/dp_mst: Clear ACT sent flag before waiting for it In-Reply-To: <20200610183132.13341-1-imre.deak@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> Message-ID: <20200610183132.13341-2-imre.deak@intel.com> We do this during enabling, but not during disabling. BSpec doesn't require this explicitly in either case, however based on my tests nothing clears it after it gets set, so let's do this during disabling as well. Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1c3654a117a9..566fe469940d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -368,6 +368,8 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port); + clear_act_sent(old_crtc_state, intel_dp); + ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); if (ret) { drm_dbg_kms(&i915->drm, "failed to update payload %d\n", ret); -- 2.23.1 From uma.shankar at intel.com Wed Jun 10 19:12:24 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:24 +0530 Subject: [Intel-gfx] [v3 0/8] Enable HDR on MCA LSPCON based Gen9 devices Message-ID: <20200610191232.11620-1-uma.shankar@intel.com> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR support for MCA and Parade LSPCON based GEN9 devices. SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP packets. LSPCON will be set to operate in PCON mode, will receive the metadata and create Dynamic Range and Mastering Infoframe (DRM packets) and send it to HDR capable HDMI sink devices. v2: Fixed Ville's review comments. Suppressed some warnings. Patch 8 of the series is marked "Not for Merge" and is just for reference to userspace people to incorporate in order to support 10bit content with 4K at 60 resolutions. v3: Added Infoframe readout support for DRM infoframes. Addressed Jani Nikula's review comments. Note: Patch 8 of the series is for reference to userspace, not to be merged to driver. Uma Shankar (8): drm/i915/display: Add HDR Capability detection for LSPCON drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon drm/i915/display: Attach HDR property for capable Gen9 devices drm/i915/display: Enable BT2020 for HDR on LSPCON devices drm/i915/display: Enable HDR for Parade based lspcon drm/i915/display: Implement infoframes readback for LSPCON drm/i915/display: Implement DRM infoframe read for LSPCON drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60 at 10bpp for LSPCON .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 17 ++ drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++ drivers/gpu/drm/i915/display/intel_lspcon.c | 158 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_lspcon.h | 9 +- 5 files changed, 189 insertions(+), 16 deletions(-) -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:25 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:25 +0530 Subject: [Intel-gfx] [v3 1/8] drm/i915/display: Add HDR Capability detection for LSPCON In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-2-uma.shankar@intel.com> LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES DPCD register. LSPCON implementations capable of supporting HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch reads the same, detects the HDR capability and adds this to intel_lspcon struct. v2: Addressed Jani Nikula's review comment and fixed the HDR capability detection logic Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_lspcon.c | 30 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..ca99a05f52da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1386,6 +1386,7 @@ struct intel_lspcon { bool active; enum drm_lspcon_mode mode; enum lspcon_vendor vendor; + bool hdr_supported; }; struct intel_digital_port { diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 6ff7b226f0a1..70bd564cae46 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -35,6 +35,8 @@ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 #define LSPCON_VENDOR_MCA_OUI 0x0060AD +#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 + /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF @@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) return true; } +static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_digital_port *intel_dig_port = + container_of(lspcon, struct intel_digital_port, lspcon); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* Enable HDR for MCA based LSPCON devices */ + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, + &hdr_caps, 1); + else + return; + + if (ret < 0) { + drm_dbg_kms(dev, "hdr capability detection failed\n"); + lspcon->hdr_supported = false; + return; + } else if (hdr_caps & 0x1) { + drm_dbg_kms(dev, "lspcon capable of HDR\n"); + lspcon->hdr_supported = true; + } +} + static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) { enum drm_lspcon_mode current_mode; @@ -581,6 +609,8 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) return false; } + lspcon_detect_hdr_capability(lspcon); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n"); -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:26 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:26 +0530 Subject: [Intel-gfx] [v3 2/8] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-3-uma.shankar@intel.com> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR support for MCA LSPCON based GEN9 devices. SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP packets. LSPCON will be set to operate in PCON mode, will receive the metadata and create Dynamic Range and Mastering Infoframe (DRM packets) and send it to HDR capable HDMI sink devices. v2: Re-used hsw infoframe write implementation for HDR metadata for LSPCON as per Ville's suggestion. v3: Addressed Jani Nikula's review comments. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++ drivers/gpu/drm/i915/display/intel_lspcon.c | 37 +++++++++++++++------ drivers/gpu/drm/i915/display/intel_lspcon.h | 5 ++- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a31a98d26882..53103ef72a58 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -590,6 +590,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, return val & mask; } +void lspcon_drm_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len) +{ + drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n"); + /* It uses the legacy hsw implementation for the same */ + hsw_write_infoframe(encoder, crtc_state, type, frame, len); +} + static const u8 infoframe_type_to_idx[] = { HDMI_PACKET_TYPE_GENERAL_CONTROL, HDMI_PACKET_TYPE_GAMUT_METADATA, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 70bd564cae46..95d29c379076 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -461,27 +461,42 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, unsigned int type, const void *frame, ssize_t len) { - bool ret; + bool ret = true; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); - /* LSPCON only needs AVI IF */ - if (type != HDMI_INFOFRAME_TYPE_AVI) + /* + * Supporting HDR on MCA LSPCON + * Todo: Add support for Parade later + */ + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA && + lspcon->vendor != LSPCON_VENDOR_MCA) return; - if (lspcon->vendor == LSPCON_VENDOR_MCA) - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, - frame, len); - else - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, - frame, len); + switch (type) { + case HDMI_INFOFRAME_TYPE_AVI: + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, + frame, len); + else + ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, + frame, len); + break; + case HDMI_PACKET_TYPE_GAMUT_METADATA: + lspcon_drm_write_infoframe(encoder, crtc_state, + HDMI_PACKET_TYPE_GAMUT_METADATA, + frame, VIDEO_DIP_DATA_SIZE); + break; + default: + return; + } if (!ret) { - DRM_ERROR("Failed to write AVI infoframes\n"); + DRM_ERROR("Failed to write infoframes\n"); return; } - DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n"); + DRM_DEBUG_DRIVER("Infoframes updated successfully\n"); } void lspcon_read_infoframe(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 37cfddf8a9c5..b2051f236223 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config); void lspcon_ycbcr420_config(struct drm_connector *connector, struct intel_crtc_state *crtc_state); - +void lspcon_drm_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len); #endif /* __INTEL_LSPCON_H__ */ -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:27 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:27 +0530 Subject: [Intel-gfx] [v3 3/8] drm/i915/display: Attach HDR property for capable Gen9 devices In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-4-uma.shankar@intel.com> Attach HDR property for Gen9 devices with MCA LSPCON chips. v2: Cleaned HDR property attachment logic based on capability as per Jani Nikula's suggestion. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 95d29c379076..7113c2efdab4 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) lspcon_detect_hdr_capability(lspcon); + if (lspcon->hdr_supported) + drm_object_attach_property(&connector->base, + connector->dev->mode_config.hdr_output_metadata_property, + 0); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n"); -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:28 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:28 +0530 Subject: [Intel-gfx] [v3 4/8] drm/i915/display: Enable BT2020 for HDR on LSPCON devices In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-5-uma.shankar@intel.com> Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry data for HDR using AVI infoframe. LSPCON firmware expects this and though SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device which transfers the same to HDMI sink. v2: Dropped state managed in drm core as per Jani Nikula's suggestion. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 7113c2efdab4..10e2823bf1ae 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -507,6 +507,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder, /* FIXME implement this */ } +/* HDMI HDR Colorspace Spec Definitions */ +#define NORMAL_COLORIMETRY_MASK 0x3 +#define EXTENDED_COLORIMETRY_MASK 0x7 +#define HDMI_COLORIMETRY_BT2020_YCC ((3 << 0) | (6 << 2) | (0 << 5)) + void lspcon_set_infoframes(struct intel_encoder *encoder, bool enable, const struct intel_crtc_state *crtc_state, @@ -551,6 +556,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL); + /* + * Set BT2020 colorspace if driving HDR data + * ToDo: Make this generic and expose all colorspaces for lspcon + */ + if (lspcon->active && lspcon->hdr_supported) { + frame.avi.colorimetry = + HDMI_COLORIMETRY_BT2020_YCC & + NORMAL_COLORIMETRY_MASK; + frame.avi.extended_colorimetry = + (HDMI_COLORIMETRY_BT2020_YCC >> 2) & + EXTENDED_COLORIMETRY_MASK; + } + ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf)); if (ret < 0) { DRM_ERROR("Failed to pack AVI IF\n"); -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:29 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:29 +0530 Subject: [Intel-gfx] [v3 5/8] drm/i915/display: Enable HDR for Parade based lspcon In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-6-uma.shankar@intel.com> Enable HDR for LSPCON based on Parade along with MCA. Signed-off-by: Uma Shankar <uma.shankar at intel.com> Signed-off-by: Vipin Anand <vipin.anand at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 10e2823bf1ae..9034ce6f20b9 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -36,6 +36,7 @@ #define LSPCON_VENDOR_MCA_OUI 0x0060AD #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 +#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511 /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 @@ -112,16 +113,20 @@ static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) container_of(lspcon, struct intel_digital_port, lspcon); struct drm_device *dev = intel_dig_port->base.base.dev; struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u32 lspcon_hdr_status_reg; u8 hdr_caps; int ret; - /* Enable HDR for MCA based LSPCON devices */ if (lspcon->vendor == LSPCON_VENDOR_MCA) - ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, - &hdr_caps, 1); + lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS; + else if (lspcon->vendor == LSPCON_VENDOR_PARADE) + lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS; else return; + ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg, + &hdr_caps, 1); + if (ret < 0) { drm_dbg_kms(dev, "hdr capability detection failed\n"); lspcon->hdr_supported = false; @@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); - /* - * Supporting HDR on MCA LSPCON - * Todo: Add support for Parade later - */ - if (type == HDMI_PACKET_TYPE_GAMUT_METADATA && - lspcon->vendor != LSPCON_VENDOR_MCA) - return; - switch (type) { case HDMI_INFOFRAME_TYPE_AVI: if (lspcon->vendor == LSPCON_VENDOR_MCA) -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:30 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:30 +0530 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-7-uma.shankar@intel.com> Implemented Infoframes enabled readback for LSPCON devices. This will help align the implementation with state readback infrastructure. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 63 ++++++++++++++++++++- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 9034ce6f20b9..0ebe9a700291 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, buf, ret); } +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = LSPCON_MCA_AVI_IF_CTRL; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); + return false; + } + + if (val & LSPCON_MCA_AVI_IF_KICKOFF) + return true; + + return false; +} + +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); + return false; + } + + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) + return true; + + return false; +} + u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { - /* FIXME actually read this from the hw */ - return 0; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + bool infoframes_enabled; + u32 mask = 0; + u32 val; + + if (lspcon->vendor == LSPCON_VENDOR_MCA) + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); + else + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); + + if (infoframes_enabled) + return true; + + if (lspcon->hdr_supported) { + val = intel_de_read(dev_priv, + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); + mask |= VIDEO_DIP_ENABLE_GMP_HSW; + + if (val & mask) + return val & mask; + } + + return false; } void lspcon_resume(struct intel_lspcon *lspcon) -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:31 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:31 +0530 Subject: [Intel-gfx] [v3 7/8] drm/i915/display: Implement DRM infoframe read for LSPCON In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-8-uma.shankar@intel.com> Implement Read back of HDR metadata infoframes i.e Dynamic Range and Mastering Infoframe for LSPCON devices. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_lspcon.c | 6 +++++- drivers/gpu/drm/i915/display/intel_lspcon.h | 4 ++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 53103ef72a58..786378442dd2 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -600,6 +600,16 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder, hsw_write_infoframe(encoder, crtc_state, type, frame, len); } +void lspcon_drm_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len) +{ + drm_dbg_kms(encoder->base.dev, "Read HDR metadata for lspcon\n"); + /* It uses the legacy hsw implementation for the same */ + hsw_read_infoframe(encoder, crtc_state, type, frame, len); +} + static const u8 infoframe_type_to_idx[] = { HDMI_PACKET_TYPE_GENERAL_CONTROL, HDMI_PACKET_TYPE_GAMUT_METADATA, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 0ebe9a700291..8d1bd2da1e73 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -501,7 +501,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder, unsigned int type, void *frame, ssize_t len) { - /* FIXME implement this */ + /* FIXME implement for AVI Infoframe as well */ + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA) + lspcon_drm_read_infoframe(encoder, crtc_state, + HDMI_PACKET_TYPE_GAMUT_METADATA, + frame, VIDEO_DIP_DATA_SIZE); } /* HDMI HDR Colorspace Spec Definitions */ diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index b2051f236223..68d2d835bd86 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -38,4 +38,8 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type, const void *frame, ssize_t len); +void lspcon_drm_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len); #endif /* __INTEL_LSPCON_H__ */ -- 2.22.0 From uma.shankar at intel.com Wed Jun 10 19:12:32 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Thu, 11 Jun 2020 00:42:32 +0530 Subject: [Intel-gfx] [v3 8/8] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <20200610191232.11620-9-uma.shankar@intel.com> Blanking needs to be reduced to incorporate DP and HDMI timing/link bandwidth limitations for CEA modes (4k at 60 at 10 bpp). DP can drive 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will cause mode to blank out. Reduced Htotal by shortening the back porch and front porch within permissible limits. Note: This is for reference for userspace, not to be merged in kernel. v2: This is marked as Not for merge and the responsibilty to program these custom timings will be on userspace. This patch is just for reference purposes. This is based on Ville's recommendation. v3: updated commit message. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 55fda074c0ad..45dbe4388742 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -632,8 +632,10 @@ intel_dp_mode_valid(struct drm_connector *connector, { struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; struct drm_i915_private *dev_priv = to_i915(connector->dev); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder); int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk; @@ -655,6 +657,21 @@ intel_dp_mode_valid(struct drm_connector *connector, target_clock = fixed_mode->clock; } + /* + * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth + * limitations for CEA modes (4k at 60 at 10 bpp). DP can drive 17.28Gbs + * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will + * cause mode to blank out. Reduced Htotal by shortening the back porch + * and front porch within permissible limits. + */ + if (lspcon->active && lspcon->hdr_supported && + mode->clock > 570000) { + mode->clock = 570000; + mode->htotal -= 180; + mode->hsync_start -= 72; + mode->hsync_end -= 72; + } + max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); -- 2.22.0 From patchwork at emeril.freedesktop.org Wed Jun 10 19:22:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 19:22:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl+=3A_Fix_DP_MST_ACT_sta?= =?utf-8?q?tus_handling?= In-Reply-To: <20200610183132.13341-1-imre.deak@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> Message-ID: <159181694977.20176.15295093639042527592@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/tgl+: Fix DP MST ACT status handling URL : https://patchwork.freedesktop.org/series/78193/ State : success == Summary == CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17921 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/index.html Known issues ------------ Here are the changes found in Patchwork_17921 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][3] -> [FAIL][4] ([i915#227]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-cml-s: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml-s/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-cml-s/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Warnings #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-kbl-x1275/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17921 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17921: 77a732d46697f75e67997a7b5f8a94b21ab8e556 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 77a732d46697 drm/i915/dp_mst: Clear ACT sent flag before waiting for it 34a2e794d60b drm/i915/tgl+: Fix DP MST ACT status handling == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/index.html From patchwork at emeril.freedesktop.org Wed Jun 10 19:30:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 19:30:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Enable_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev3=29?= In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <159181745167.20174.5586487185304895886@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev3) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From daniel.vetter at ffwll.ch Wed Jun 10 19:41:01 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Wed, 10 Jun 2020 21:41:01 +0200 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200604081224.863494-2-daniel.vetter@ffwll.ch> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> Message-ID: <20200610194101.1668038-1-daniel.vetter@ffwll.ch> fs_reclaim_acquire/release nicely catch recursion issues when allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend to use to keep the excessive caches in check). For mmu notifier recursions we do have lockdep annotations since 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). But these only fire if a path actually results in some pte invalidation - for most small allocations that's very rarely the case. The other trouble is that pte invalidation can happen any time when __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe choice, GFP_NOIO isn't good enough to avoid potential mmu notifier recursion. I was pondering whether we should just do the general annotation, but there's always the risk for false positives. Plus I'm assuming that the core fs and io code is a lot better reviewed and tested than random mmu notifier code in drivers. Hence why I decide to only annotate for that specific case. Furthermore even if we'd create a lockdep map for direct reclaim, we'd still need to explicit pull in the mmu notifier map - there's a lot more places that do pte invalidation than just direct reclaim, these two contexts arent the same. Note that the mmu notifiers needing their own independent lockdep map is also the reason we can't hold them from fs_reclaim_acquire to fs_reclaim_release - it would nest with the acquistion in the pte invalidation code, causing a lockdep splat. And we can't remove the annotations from pte invalidation and all the other places since they're called from many other places than page reclaim. Hence we can only do the equivalent of might_lock, but on the raw lockdep map. With this we can also remove the lockdep priming added in 66204f1d2d1b ("mm/mmu_notifiers: prime lockdep") since the new annotations are strictly more powerful. v2: Review from Thomas Hellstrom: - unbotch the fs_reclaim context check, I accidentally inverted it, but it didn't blow up because I inverted it immediately - fix compiling for !CONFIG_MMU_NOTIFIER Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> Cc: Andrew Morton <akpm at linux-foundation.org> Cc: Jason Gunthorpe <jgg at mellanox.com> Cc: linux-mm at kvack.org Cc: linux-rdma at vger.kernel.org Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- This is part of a gpu lockdep annotation series simply because it really helps to catch issues where gpu subsystem locks and primitives can deadlock with themselves through allocations and mmu notifiers. But aside from that motivation it should be completely free-standing, and can land through -mm/-rdma/-hmm or any other tree really whenever. -Daniel --- mm/mmu_notifier.c | 7 ------- mm/page_alloc.c | 25 ++++++++++++++++--------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c index 06852b896fa6..5d578b9122f8 100644 --- a/mm/mmu_notifier.c +++ b/mm/mmu_notifier.c @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, lockdep_assert_held_write(&mm->mmap_sem); BUG_ON(atomic_read(&mm->mm_users) <= 0); - if (IS_ENABLED(CONFIG_LOCKDEP)) { - fs_reclaim_acquire(GFP_KERNEL); - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); - lock_map_release(&__mmu_notifier_invalidate_range_start_map); - fs_reclaim_release(GFP_KERNEL); - } - if (!mm->notifier_subscriptions) { /* * kmalloc cannot be called under mm_take_all_locks(), but we diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 13cc653122b7..7536faaaa0fd 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -57,6 +57,7 @@ #include <trace/events/oom.h> #include <linux/prefetch.h> #include <linux/mm_inline.h> +#include <linux/mmu_notifier.h> #include <linux/migrate.h> #include <linux/hugetlb.h> #include <linux/sched/rt.h> @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla static struct lockdep_map __fs_reclaim_map = STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); -static bool __need_fs_reclaim(gfp_t gfp_mask) +static bool __need_reclaim(gfp_t gfp_mask) { gfp_mask = current_gfp_context(gfp_mask); @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) if (current->flags & PF_MEMALLOC) return false; - /* We're only interested __GFP_FS allocations for now */ - if (!(gfp_mask & __GFP_FS)) - return false; - if (gfp_mask & __GFP_NOLOCKDEP) return false; @@ -4158,15 +4155,25 @@ void __fs_reclaim_release(void) void fs_reclaim_acquire(gfp_t gfp_mask) { - if (__need_fs_reclaim(gfp_mask)) - __fs_reclaim_acquire(); + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_acquire(); + +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#endif + + } } EXPORT_SYMBOL_GPL(fs_reclaim_acquire); void fs_reclaim_release(gfp_t gfp_mask) { - if (__need_fs_reclaim(gfp_mask)) - __fs_reclaim_release(); + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_release(); + } } EXPORT_SYMBOL_GPL(fs_reclaim_release); #endif -- 2.26.2 From uma.shankar at intel.com Wed Jun 10 19:45:35 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Wed, 10 Jun 2020 19:45:35 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on In-Reply-To: <20200609220616.6015-1-imre.deak@intel.com> References: <20200609220616.6015-1-imre.deak@intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F82521F76@BGSMSX104.gar.corp.intel.com> > -----Original Message----- > From: Deak, Imre <imre.deak at intel.com> > Sent: Wednesday, June 10, 2020 3:36 AM > To: intel-gfx at lists.freedesktop.org > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun at intel.com>; Shankar, Uma > <uma.shankar at intel.com> > Subject: [PATCH] drm/i915/icl: Disable DIP on MST ports with the transcoder > clock still on > > According to BSpec the Data Island Packet should be disabled after disabling the > transcoder, but before the transcoder clock select is set to none. On an ICL RVP, > daisy-chained MST config not following this leads to a hang with the following > MCE when disabling the output: > > [ 870.948739] mce: [Hardware Error]: CPU 0: Machine Check Exception: 5 Bank 6: > ba00000011000402 [ 871.019212] mce: [Hardware Error]: RIP !INEXACT! > 10:<ffffffff81aca652> {poll_idle+0x92/0xb0} [ 871.019212] mce: [Hardware Error]: > TSC 135a261fe61 [ 871.019212] mce: [Hardware Error]: PROCESSOR 0:706e5 TIME > 1591739604 SOCKET 0 APIC 0 microcode 20 [ 871.019212] mce: [Hardware Error]: > Run the above through 'mcelog --ascii' > [ 871.019212] mce: [Hardware Error]: Machine check: Processor context corrupt [ > 871.019212] Kernel panic - not syncing: Fatal machine check [ 871.019212] Kernel > Offset: disabled > > Bspec: 4287 > > Fixes: fa37a213275c ("drm/i915: Stop sending DP SDPs on ddi disable") > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > Cc: Uma Shankar <uma.shankar at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> This is a good catch Imre. Would be good to know how you suspected this. Reviewed-by: Uma Shankar <uma.shankar at intel.com> > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 96eaa4b39c68..50ccc6e30dc1 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3510,7 +3510,9 @@ static void intel_ddi_post_disable_dp(struct > intel_atomic_state *state, > INTEL_OUTPUT_DP_MST); > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > - intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); > + if (!is_mst) > + intel_dp_set_infoframes(encoder, false, > + old_crtc_state, old_conn_state); > > /* > * Power down sink before disabling the port, otherwise we end diff --git > a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d18b406f2a7d..f29e51ce489c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -397,6 +397,14 @@ static void intel_mst_post_disable_dp(struct > intel_atomic_state *state, > */ > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector- > >port, > false); > + > + /* > + * BSpec 4287: disable DIP after the transcoder is disabled and before > + * the transcoder clock select is set to none. > + */ > + if (last_mst_stream) > + intel_dp_set_infoframes(&intel_dig_port->base, false, > + old_crtc_state, NULL); > /* > * From TGL spec: "If multi-stream slave transcoder: Configure > * Transcoder Clock Select to direct no clock to the transcoder" > -- > 2.23.1 From patchwork at emeril.freedesktop.org Wed Jun 10 19:52:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 19:52:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev3=29?= In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <159181872292.20175.12513317211904900319@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev3) URL : https://patchwork.freedesktop.org/series/68081/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17922 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17922 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17922, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17922: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html Known issues ------------ Here are the changes found in Patchwork_17922 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-cml-s: [DMESG-WARN][4] ([i915#1982]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml-s/igt at i915_pm_rpm@module-reload.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-cml-s/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][10] ([i915#62] / [i915#92]) -> [DMESG-WARN][11] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][12] ([i915#62] / [i915#92]) -> [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][15] ([i915#62] / [i915#92]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 43) ------------------------------ Additional (2): fi-kbl-7560u fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17922 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17922: 0903ebe28a8fb9c912916613977b2e77d83eac8c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0903ebe28a8f drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60 at 10bpp for LSPCON e67c4219c55f drm/i915/display: Implement DRM infoframe read for LSPCON 90fe2351734a drm/i915/display: Implement infoframes readback for LSPCON 7aab4641b28f drm/i915/display: Enable HDR for Parade based lspcon e71a13eb3147 drm/i915/display: Enable BT2020 for HDR on LSPCON devices 5940d801abf4 drm/i915/display: Attach HDR property for capable Gen9 devices ae1436b72a1c drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon 292e80f577e6 drm/i915/display: Add HDR Capability detection for LSPCON == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/index.html From imre.deak at intel.com Wed Jun 10 19:56:20 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 10 Jun 2020 22:56:20 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F82521F76@BGSMSX104.gar.corp.intel.com> References: <20200609220616.6015-1-imre.deak@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F82521F76@BGSMSX104.gar.corp.intel.com> Message-ID: <20200610195620.GA13917@ideak-desk.fi.intel.com> On Wed, Jun 10, 2020 at 10:45:35PM +0300, Shankar, Uma wrote: > > > > -----Original Message----- > > From: Deak, Imre <imre.deak at intel.com> > > Sent: Wednesday, June 10, 2020 3:36 AM > > To: intel-gfx at lists.freedesktop.org > > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun at intel.com>; Shankar, Uma > > <uma.shankar at intel.com> > > Subject: [PATCH] drm/i915/icl: Disable DIP on MST ports with the transcoder > > clock still on > > > > According to BSpec the Data Island Packet should be disabled after disabling the > > transcoder, but before the transcoder clock select is set to none. On an ICL RVP, > > daisy-chained MST config not following this leads to a hang with the following > > MCE when disabling the output: > > > > [ 870.948739] mce: [Hardware Error]: CPU 0: Machine Check Exception: 5 Bank 6: > > ba00000011000402 [ 871.019212] mce: [Hardware Error]: RIP !INEXACT! > > 10:<ffffffff81aca652> {poll_idle+0x92/0xb0} [ 871.019212] mce: [Hardware Error]: > > TSC 135a261fe61 [ 871.019212] mce: [Hardware Error]: PROCESSOR 0:706e5 TIME > > 1591739604 SOCKET 0 APIC 0 microcode 20 [ 871.019212] mce: [Hardware Error]: > > Run the above through 'mcelog --ascii' > > [ 871.019212] mce: [Hardware Error]: Machine check: Processor context corrupt [ > > 871.019212] Kernel panic - not syncing: Fatal machine check [ 871.019212] Kernel > > Offset: disabled > > > > Bspec: 4287 > > > > Fixes: fa37a213275c ("drm/i915: Stop sending DP SDPs on ddi disable") > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > Cc: Uma Shankar <uma.shankar at intel.com> > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > This is a good catch Imre. Would be good to know how you suspected this. The MCE happens just when accessing a register without the required clock for it being on. In this case when reading/writing the SDP registers. We had to fix the same problem in the past around HDMI infoframe programming. > Reviewed-by: Uma Shankar <uma.shankar at intel.com> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ > > 2 files changed, 11 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 96eaa4b39c68..50ccc6e30dc1 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -3510,7 +3510,9 @@ static void intel_ddi_post_disable_dp(struct > > intel_atomic_state *state, > > INTEL_OUTPUT_DP_MST); > > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > > > - intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); > > + if (!is_mst) > > + intel_dp_set_infoframes(encoder, false, > > + old_crtc_state, old_conn_state); > > > > /* > > * Power down sink before disabling the port, otherwise we end diff --git > > a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index d18b406f2a7d..f29e51ce489c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -397,6 +397,14 @@ static void intel_mst_post_disable_dp(struct > > intel_atomic_state *state, > > */ > > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector- > > >port, > > false); > > + > > + /* > > + * BSpec 4287: disable DIP after the transcoder is disabled and before > > + * the transcoder clock select is set to none. > > + */ > > + if (last_mst_stream) > > + intel_dp_set_infoframes(&intel_dig_port->base, false, > > + old_crtc_state, NULL); > > /* > > * From TGL spec: "If multi-stream slave transcoder: Configure > > * Transcoder Clock Select to direct no clock to the transcoder" > > -- > > 2.23.1 > From uma.shankar at intel.com Wed Jun 10 19:59:27 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Wed, 10 Jun 2020 19:59:27 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on In-Reply-To: <20200610195620.GA13917@ideak-desk.fi.intel.com> References: <20200609220616.6015-1-imre.deak@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F82521F76@BGSMSX104.gar.corp.intel.com> <20200610195620.GA13917@ideak-desk.fi.intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F82521FBD@BGSMSX104.gar.corp.intel.com> > -----Original Message----- > From: Imre Deak <imre.deak at intel.com> > Sent: Thursday, June 11, 2020 1:26 AM > To: Shankar, Uma <uma.shankar at intel.com> > Cc: intel-gfx at lists.freedesktop.org; Mun, Gwan-gyeong <gwan- > gyeong.mun at intel.com> > Subject: Re: [PATCH] drm/i915/icl: Disable DIP on MST ports with the transcoder > clock still on > > On Wed, Jun 10, 2020 at 10:45:35PM +0300, Shankar, Uma wrote: > > > > > > > -----Original Message----- > > > From: Deak, Imre <imre.deak at intel.com> > > > Sent: Wednesday, June 10, 2020 3:36 AM > > > To: intel-gfx at lists.freedesktop.org > > > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun at intel.com>; Shankar, Uma > > > <uma.shankar at intel.com> > > > Subject: [PATCH] drm/i915/icl: Disable DIP on MST ports with the > > > transcoder clock still on > > > > > > According to BSpec the Data Island Packet should be disabled after > > > disabling the transcoder, but before the transcoder clock select is > > > set to none. On an ICL RVP, daisy-chained MST config not following > > > this leads to a hang with the following MCE when disabling the output: > > > > > > [ 870.948739] mce: [Hardware Error]: CPU 0: Machine Check Exception: 5 > Bank 6: > > > ba00000011000402 [ 871.019212] mce: [Hardware Error]: RIP !INEXACT! > > > 10:<ffffffff81aca652> {poll_idle+0x92/0xb0} [ 871.019212] mce: [Hardware > Error]: > > > TSC 135a261fe61 [ 871.019212] mce: [Hardware Error]: PROCESSOR > > > 0:706e5 TIME > > > 1591739604 SOCKET 0 APIC 0 microcode 20 [ 871.019212] mce: [Hardware > Error]: > > > Run the above through 'mcelog --ascii' > > > [ 871.019212] mce: [Hardware Error]: Machine check: Processor > > > context corrupt [ 871.019212] Kernel panic - not syncing: Fatal > > > machine check [ 871.019212] Kernel > > > Offset: disabled > > > > > > Bspec: 4287 > > > > > > Fixes: fa37a213275c ("drm/i915: Stop sending DP SDPs on ddi > > > disable") > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > > Cc: Uma Shankar <uma.shankar at intel.com> > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > > > This is a good catch Imre. Would be good to know how you suspected this. > > The MCE happens just when accessing a register without the required clock for it > being on. In this case when reading/writing the SDP registers. We had to fix the > same problem in the past around HDMI infoframe programming. Oh ok, thanks Imre for the info. Regards, Uma Shankar > > Reviewed-by: Uma Shankar <uma.shankar at intel.com> > > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++- > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ > > > 2 files changed, 11 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > > > b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 96eaa4b39c68..50ccc6e30dc1 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -3510,7 +3510,9 @@ static void intel_ddi_post_disable_dp(struct > > > intel_atomic_state *state, > > > INTEL_OUTPUT_DP_MST); > > > enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > > > > > - intel_dp_set_infoframes(encoder, false, old_crtc_state, old_conn_state); > > > + if (!is_mst) > > > + intel_dp_set_infoframes(encoder, false, > > > + old_crtc_state, old_conn_state); > > > > > > /* > > > * Power down sink before disabling the port, otherwise we end > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > index d18b406f2a7d..f29e51ce489c 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > @@ -397,6 +397,14 @@ static void intel_mst_post_disable_dp(struct > > > intel_atomic_state *state, > > > */ > > > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector- > > > >port, > > > false); > > > + > > > + /* > > > + * BSpec 4287: disable DIP after the transcoder is disabled and before > > > + * the transcoder clock select is set to none. > > > + */ > > > + if (last_mst_stream) > > > + intel_dp_set_infoframes(&intel_dig_port->base, false, > > > + old_crtc_state, NULL); > > > /* > > > * From TGL spec: "If multi-stream slave transcoder: Configure > > > * Transcoder Clock Select to direct no clock to the transcoder" > > > -- > > > 2.23.1 > > From patchwork at emeril.freedesktop.org Wed Jun 10 20:20:03 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 20:20:03 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_dma-fence_lockdep_annotations=2C_round_2_=28rev3=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159182040398.20177.11390937103101000155@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev3) URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim checkpatch origin/drm-tip b91d6e9b2219 mm: Track mmu notifiers in fs_reclaim_acquire/release -:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #12: recursions we do have lockdep annotations since 23b68395c7c7 -:41: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 66204f1d2d1b ("mm/mmu_notifiers: prime lockdep")' #41: With this we can also remove the lockdep priming added in 66204f1d2d1b -:124: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #124: FILE: mm/page_alloc.c:4167: + + } -:138: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 2 errors, 1 warnings, 1 checks, 67 lines checked 464bebc66202 dma-buf: minor doc touch-ups -:33: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 14 lines checked 4a356e005b80 dma-fence: basic lockdep annotations -:23: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e91498589746 ("locking/lockdep/selftests: Add mixed read-write ABBA tests")' #23: commit e91498589746065e3ae95d9a00b068e525eec34f -:97: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e966eaeeb623 ("locking/lockdep: Remove the cross-release locking checks")' #97: commit e966eaeeb623f09975ef362c2866fae6f86844f9 -:103: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #103: This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), -:314: ERROR:IN_ATOMIC: do not use in_atomic in drivers #314: FILE: drivers/dma-buf/dma-fence.c:228: + if (in_atomic()) -:352: CHECK:LINE_SPACING: Please don't use multiple blank lines #352: FILE: drivers/dma-buf/dma-fence.c:266: + + -:401: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #401: FILE: include/linux/dma-fence.h:368: +} +static inline void dma_fence_end_signalling(bool cookie) {} -:407: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 3 errors, 2 warnings, 2 checks, 231 lines checked e85757129eef dma-fence: prime lockdep annotations -:31: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #31: commit 23b68395c7c78a764e8963fc15a7cfd318bf187f -:169: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 1 errors, 1 warnings, 0 checks, 82 lines checked abea167ccc2c drm/vkms: Annotate vblank timer -:59: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 25 lines checked 74cf66d0c736 drm/vblank: Annotate with dma-fence signalling section -:71: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 38 lines checked 49852bebf34d drm/atomic-helper: Add dma-fence annotations -:119: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 76 lines checked 812e8d183ea1 drm/amdgpu: add dma-fence annotations to atomic commit path -:52: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 24 lines checked e86ec566effc drm/scheduler: use dma-fence annotations in main thread -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 21 lines checked d05e15f8ad27 drm/amdgpu: use dma-fence annotations in cs_submit() -:65: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 29 lines checked 805637835bf6 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code -:82: WARNING:ALLOC_ARRAY_ARGS: kmalloc_array uses number as first arg, sizeof is generally wrong #82: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:211: + fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_ATOMIC); -:98: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 24 lines checked 18403b85aff4 drm/amdgpu: DC also loves to allocate stuff where it shouldn't -:70: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #70: FILE: drivers/gpu/drm/amd/display/dc/core/dc.c:1436: + * atomic_commit_tail. */ -:76: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 27 lines checked 2dbc37297b21 drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail -:39: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif #39: FILE: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6914: +#if 0 -:55: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 23 lines checked d1361c491f79 drm/scheduler: use dma-fence annotations in tdr work -:28: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'? #28: Hence split out as a seperate patch. -:114: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 20 lines checked 718c082d14cb drm/amdgpu: use dma-fence annotations for gpu reset code f08fc8bb8383 Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" -:145: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 16 lines checked c40ab1c8276b drm/amdgpu: gpu recovery does full modesets -:186: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 14 lines checked c8130cec52d5 drm/i915: Annotate dma_fence_work -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 15 lines checked From rodrigo.vivi at intel.com Wed Jun 10 20:18:07 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Wed, 10 Jun 2020 13:18:07 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c In-Reply-To: <159163988890.30073.8976615673203599761@build.alporthouse.com> References: <159163988890.30073.8976615673203599761@build.alporthouse.com> Message-ID: <20200610201807.191440-1-rodrigo.vivi@intel.com> Alexandre Oliva has recently removed these files from Linux Libre with concerns that the sources weren't available. The sources are available on IGT repository, and only open source tools are used to generate the {ivb,hsw}_clear_kernel.c files. However, the remaining concern from Alexandre Oliva was around GPL license and the source not been present when distributing the code. So, it looks like 2 alternatives are possible, the use of linux-firmware.git repository to store the blob or making sure that the source is also present in our tree. Since the goal is to limit the i915 firmware to only the micro-controller blobs let's make sure that we do include the asm sources here in our tree. Btw, I tried to have some diligence here and make sure that the asms that these commits are adding are truly the source for the mentioned files: igt$ ./scripts/generate_clear_kernel.sh -g ivb \ -m ~/mesa/build/src/intel/tools/i965_asm Output file not specified - using default file "ivb-cb_assembled" Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" for i915 driver... igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \ ivb_clear_kernel.c < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT 61c61 < }; > }; \ No newline at end of file igt$ ./scripts/generate_clear_kernel.sh -g hsw \ -m ~/mesa/build/src/intel/tools/i965_asm Output file not specified - using default file "hsw-cb_assembled" Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" for i915 driver... igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \ hsw_clear_kernel.c 5c5 < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT 61c61 < }; > }; \ No newline at end of file Used IGT and Mesa master repositories from Fri Jun 5 2020) IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging the connector") Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with RADV_DEBUG=shaderstats") Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \ -D gallium-drivers=iris -D prefix=/usr \ -D libdir=/usr/lib64/ -Dtools=intel \ -Dkulkan-drivers=intel && ninja -C build v2: Header clean-up and include build instructions in a readme (Chris) Modified commit message to respect check-patch Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003374.html Reference: http://www.fsfla.org/pipermail/linux-libre/2020-June/003375.html Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") Cc: <stable at vger.kernel.org> # v5.7+ Cc: Alexandre Oliva <lxoliva at fsfla.org> Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com> Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula at intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> --- drivers/gpu/drm/i915/gt/shaders/README | 46 +++++++ .../drm/i915/gt/shaders/clear_kernel/hsw.asm | 119 ++++++++++++++++++ .../drm/i915/gt/shaders/clear_kernel/ivb.asm | 117 +++++++++++++++++ 3 files changed, 282 insertions(+) create mode 100644 drivers/gpu/drm/i915/gt/shaders/README create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm create mode 100644 drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm diff --git a/drivers/gpu/drm/i915/gt/shaders/README b/drivers/gpu/drm/i915/gt/shaders/README new file mode 100644 index 000000000000..e7e96d7073c7 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/shaders/README @@ -0,0 +1,46 @@ +ASM sources for auto generated shaders +====================================== + +The i915/gt/hsw_clear_kernel.c and i915/gt/ivb_clear_kernel.c files contain +pre-compiled batch chunks that will clear any residual render cache during +context switch. + +They are generated from their respective platform ASM files present on +i915/gt/shaders/clear_kernel directory. + +The generated .c files should never be modified directly. Instead, any modification +needs to be done on the on their respective ASM files and build instructions below +needes to be followed. + +Building +======== + +Environment +----------- + +IGT GPU tool scripts and the Mesa's i965 instruction assembler tool are used +on building. + +Please make sure your Mesa tool is compiled with "-Dtools=intel" and +"-Ddri-drivers=i965", and run this script from IGT source root directory" + +The instructions bellow assume: + * IGT gpu tools source code is located on your home directory (~) as ~/igt + * Mesa source code is located on your home directory (~) as ~/mesa + and built under the ~/mesa/build directory + * Linux kernel source code is under your home directory (~) as ~/linux + +Instructions +------------ + +~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm \ + ~/igt/lib/i915/shaders/clear_kernel/ivb.asm +~ $ cd ~/igt +igt $ ./scripts/generate_clear_kernel.sh -g ivb \ + -m ~/mesa/build/src/intel/tools/i965_asm + +~ $ cp ~/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm \ + ~/igt/lib/i915/shaders/clear_kernel/hsw.asm +~ $ cd ~/igt +igt $ ./scripts/generate_clear_kernel.sh -g hsw \ + -m ~/mesa/build/src/intel/tools/i965_asm \ No newline at end of file diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm new file mode 100644 index 000000000000..5fdf384bb621 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +/* + * Kernel for PAVP buffer clear. + * + * 1. Clear all 64 GRF registers assigned to the kernel with designated value; + * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears + * 512 bytes of Render Cache. + */ + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/** + * Curbe Format + * + * DW 1.0 - Block Offset to write Render Cache + * DW 1.1 [15:0] - Clear Word + * DW 1.2 - Delay iterations + * DW 1.3 - Enable Instrumentation (only for debug) + * DW 1.4 - Rsvd (intended for context ID) + * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount + * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) + * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count) + * + * Binding Table + * + * BTI 0: 2D Surface to help clear L3 (Render/Data Cache) + * BTI 1: Wait/Instrumentation Buffer + * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT) + * Expected to be initialized to 0 by driver/another kernel + * Layout: + * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS] + * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N + */ +add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */ +cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N }; +(+f0.0) jmpi(1) 352D { align1 WE_all 1N }; + +/** + * State Register has info on where this thread is running + * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + */ +mov(8) g3<1>UD 0x00000000UD { align1 1Q }; +shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N }; +and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */ +shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N }; +and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */ +mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N }; +add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */ +shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N }; +and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */ +mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N }; +add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */ + +mov(8) g5<1>UD 0x00000000UD { align1 1Q }; +and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N }; +mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N }; + +mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */ +mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */ +and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N }; + +/* Media block read to fetch current value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x02190001 + + render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q }; +add(1) g5<1>D g5<0,1,0>D 1D { align1 1N }; + +/* Media block write for updated value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q }; + +/* Delay thread for specified parameter */ +add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N }; +(+f0.0) jmpi(1) -32D { align1 WE_all 1N }; + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/* Initialize looping parameters */ +mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */ +mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */ + +/* Write 32x16 all "0" block */ +mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q }; +mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q }; +mov(2) g2<1>UD g1<2,2,1>UW { align1 1N }; +mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */ +and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N }; +mov(16) g3<1>UD 0x00000000UD { align1 1H }; +mov(16) g4<1>UD 0x00000000UD { align1 1H }; +mov(16) g5<1>UD 0x00000000UD { align1 1H }; +mov(16) g6<1>UD 0x00000000UD { align1 1H }; +mov(16) g7<1>UD 0x00000000UD { align1 1H }; +mov(16) g8<1>UD 0x00000000UD { align1 1H }; +mov(16) g9<1>UD 0x00000000UD { align1 1H }; +mov(16) g10<1>UD 0x00000000UD { align1 1H }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; +add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; + +/* Now, clear all GRF registers */ +add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N }; +mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H }; +add(1) a0<1>D a0<0,1,0>D 32D { align1 1N }; +(+f0.0) jmpi(1) -64D { align1 WE_all 1N }; + +/* Terminante the thread */ +sendc(8) null<1>UD g127<8,8,1>F 0x82000010 + thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT }; diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm new file mode 100644 index 000000000000..97c7ac9e3854 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright ? 2020 Intel Corporation + */ + +/* + * Kernel for PAVP buffer clear. + * + * 1. Clear all 64 GRF registers assigned to the kernel with designated value; + * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears + * 512 bytes of Render Cache. + */ + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/** + * Curbe Format + * + * DW 1.0 - Block Offset to write Render Cache + * DW 1.1 [15:0] - Clear Word + * DW 1.2 - Delay iterations + * DW 1.3 - Enable Instrumentation (only for debug) + * DW 1.4 - Rsvd (intended for context ID) + * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount + * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) + * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count) + * + * Binding Table + * + * BTI 0: 2D Surface to help clear L3 (Render/Data Cache) + * BTI 1: Wait/Instrumentation Buffer + * Size : (SliceCount * SubSliceCount * 16 EUs/SubSlice) rows * (16 threads/EU) cols (Format R32_UINT) + * Expected to be initialized to 0 by driver/another kernel + * Layout : + * RowN: Histogram for EU-N: (SliceID*SubSlicePerSliceCount + SSID)*16 + EUID [assume max 16 EUs / SS] + * Col-k[DW-k]: Threads Executed on ThreadID-k for EU-N + */ +add(1) g1.2<1>UD g1.2<0,1,0>UD 0x00000001UD { align1 1N }; /* Loop count to delay kernel: Init to (g1.2 + 1) */ +cmp.z.f0.0(1) null<1>UD g1.3<0,1,0>UD 0x00000000UD { align1 1N }; +(+f0.0) jmpi(1) 44D { align1 WE_all 1N }; + +/** + * State Register has info on where this thread is running + * IVB: sr0.0 :: [15:13]: MBZ, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + * HSW: sr0.0 :: 15: MBZ, [14:13]: SliceID, 12: HSID (Half-Slice ID), [11:8]EUID, [2:0] ThreadSlotID + */ +mov(8) g3<1>UD 0x00000000UD { align1 1Q }; +shr(1) g3<1>D sr0<0,1,0>D 12D { align1 1N }; +and(1) g3<1>D g3<0,1,0>D 1D { align1 1N }; /* g3 has HSID */ +shr(1) g3.1<1>D sr0<0,1,0>D 13D { align1 1N }; +and(1) g3.1<1>D g3.1<0,1,0>D 3D { align1 1N }; /* g3.1 has sliceID */ +mul(1) g3.5<1>D g3.1<0,1,0>D g1.10<0,1,0>UW { align1 1N }; +add(1) g3<1>D g3<0,1,0>D g3.5<0,1,0>D { align1 1N }; /* g3 = sliceID * SubSlicePerSliceCount + HSID */ +shr(1) g3.2<1>D sr0<0,1,0>D 8D { align1 1N }; +and(1) g3.2<1>D g3.2<0,1,0>D 15D { align1 1N }; /* g3.2 = EUID */ +mul(1) g3.4<1>D g3<0,1,0>D 16D { align1 1N }; +add(1) g3.2<1>D g3.2<0,1,0>D g3.4<0,1,0>D { align1 1N }; /* g3.2 now points to EU row number (Y-pixel = V address ) in instrumentation surf */ + +mov(8) g5<1>UD 0x00000000UD { align1 1Q }; +and(1) g3.3<1>D sr0<0,1,0>D 7D { align1 1N }; +mul(1) g3.3<1>D g3.3<0,1,0>D 4D { align1 1N }; + +mov(8) g4<1>UD g0<8,8,1>UD { align1 1Q }; /* Initialize message header with g0 */ +mov(1) g4<1>UD g3.3<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.1<1>UD g3.2<0,1,0>UD { align1 1N }; /* Block offset */ +mov(1) g4.2<1>UD 0x00000003UD { align1 1N }; /* Block size (1 row x 4 bytes) */ +and(1) g4.3<1>UD g4.3<0,1,0>UW 0xffffffffUD { align1 1N }; + +/* Media block read to fetch current value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x02190001 + render MsgDesc: media block read MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align1 1Q }; +add(1) g5<1>D g5<0,1,0>D 1D { align1 1N }; + +/* Media block write for updated value at specified location in instrumentation buffer */ +sendc(8) g5<1>UD g4<8,8,1>F 0x040a8001 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 0 { align1 1Q }; +/* Delay thread for specified parameter */ +add.nz.f0.0(1) g1.2<1>UD g1.2<0,1,0>UD -1D { align1 1N }; +(+f0.0) jmpi(1) -4D { align1 WE_all 1N }; + +/* Store designated "clear GRF" value */ +mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; + +/* Initialize looping parameters */ +mov(1) a0<1>D 0D { align1 1N }; /* Initialize a0.0:w=0 */ +mov(1) a0.4<1>W 127W { align1 1N }; /* Loop count. Each loop contains 16 GRF's */ + +/* Write 32x16 all "0" block */ +mov(8) g2<1>UD g0<8,8,1>UD { align1 1Q }; +mov(8) g127<1>UD g0<8,8,1>UD { align1 1Q }; +mov(2) g2<1>UD g1<2,2,1>UW { align1 1N }; +mov(1) g2.2<1>UD 0x000f000fUD { align1 1N }; /* Block size (16x16) */ +and(1) g2.3<1>UD g2.3<0,1,0>UW 0xffffffefUD { align1 1N }; +mov(16) g3<1>UD 0x00000000UD { align1 1H }; +mov(16) g4<1>UD 0x00000000UD { align1 1H }; +mov(16) g5<1>UD 0x00000000UD { align1 1H }; +mov(16) g6<1>UD 0x00000000UD { align1 1H }; +mov(16) g7<1>UD 0x00000000UD { align1 1H }; +mov(16) g8<1>UD 0x00000000UD { align1 1H }; +mov(16) g9<1>UD 0x00000000UD { align1 1H }; +mov(16) g10<1>UD 0x00000000UD { align1 1H }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; +add(1) g2<1>UD g1<0,1,0>UW 0x0010UW { align1 1N }; +sendc(8) null<1>UD g2<8,8,1>F 0x120a8000 + render MsgDesc: media block write MsgCtrl = 0x0 Surface = 0 mlen 9 rlen 0 { align1 1Q }; + +/* Now, clear all GRF registers */ +add.nz.f0.0(1) a0.4<1>W a0.4<0,1,0>W -1W { align1 1N }; +mov(16) g[a0]<1>UW f0.1<0,1,0>UW { align1 1H }; +add(1) a0<1>D a0<0,1,0>D 32D { align1 1N }; +(+f0.0) jmpi(1) -8D { align1 WE_all 1N }; + +/* Terminante the thread */ +sendc(8) null<1>UD g127<8,8,1>F 0x82000010 + thread_spawner MsgDesc: mlen 1 rlen 0 { align1 1Q EOT }; -- 2.24.1 From patchwork at emeril.freedesktop.org Wed Jun 10 20:21:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 20:21:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?dma-fence_lockdep_annotations=2C_round_2_=28rev3=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159182051047.20177.8332099715802811499@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev3) URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '<asn:2>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '<asn:2> From viro at zeniv.linux.org.uk Wed Jun 10 20:28:37 2020 From: viro at zeniv.linux.org.uk (Al Viro) Date: Wed, 10 Jun 2020 21:28:37 +0100 Subject: [Intel-gfx] [git pull] uaccess i915 Message-ID: <20200610202837.GV23230@ZenIV.linux.org.uk> Low-hanging fruit in i915; there are several trickier followups, but that'll wait for the next cycle. The following changes since commit b44f687386875b714dae2afa768e73401e45c21c: drm/i915/gem: Replace user_access_begin by user_write_access_begin (2020-05-01 12:35:22 +1000) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git uaccess.i915 for you to fetch changes up to 7b3f0c4c56b08a86f890cad3599242c78c683aa9: i915:get_engines(): get rid of pointless access_ok() (2020-05-01 20:35:42 -0400) ---------------------------------------------------------------- Al Viro (5): i915: switch query_{topology,engine}_info() to copy_to_user() i915: switch copy_perf_config_registers_or_number() to unsafe_put_user() i915 compat ioctl(): just use drm_ioctl_kernel() i915: alloc_oa_regs(): get rid of pointless access_ok() i915:get_engines(): get rid of pointless access_ok() drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 --- drivers/gpu/drm/i915/i915_ioc32.c | 14 +++---- drivers/gpu/drm/i915/i915_perf.c | 3 -- drivers/gpu/drm/i915/i915_query.c | 62 ++++++++++------------------- drivers/gpu/drm/i915/i915_reg.h | 2 +- 5 files changed, 28 insertions(+), 58 deletions(-) From patchwork at emeril.freedesktop.org Wed Jun 10 20:35:36 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 20:35:36 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZG1h?= =?utf-8?q?-fence_lockdep_annotations=2C_round_2_=28rev3=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159182133615.20176.7157278350431313834@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev3) URL : https://patchwork.freedesktop.org/series/77986/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17923 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17923 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17923, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17923: ### IGT changes ### #### Possible regressions #### * igt at gem_busy@busy at all: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at gem_busy@busy at all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-kbl-x1275/igt at gem_busy@busy at all.html - fi-cfl-8700k: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cfl-8700k/igt at gem_busy@busy at all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cfl-8700k/igt at gem_busy@busy at all.html - fi-skl-6600u: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-skl-6600u/igt at gem_busy@busy at all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-skl-6600u/igt at gem_busy@busy at all.html - fi-cfl-8109u: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cfl-8109u/igt at gem_busy@busy at all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cfl-8109u/igt at gem_busy@busy at all.html - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-icl-u2/igt at gem_busy@busy at all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-icl-u2/igt at gem_busy@busy at all.html - fi-glk-dsi: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-glk-dsi/igt at gem_busy@busy at all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-glk-dsi/igt at gem_busy@busy at all.html - fi-skl-lmem: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-skl-lmem/igt at gem_busy@busy at all.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-skl-lmem/igt at gem_busy@busy at all.html - fi-kbl-r: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-r/igt at gem_busy@busy at all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-kbl-r/igt at gem_busy@busy at all.html - fi-bdw-5557u: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bdw-5557u/igt at gem_busy@busy at all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-bdw-5557u/igt at gem_busy@busy at all.html - fi-icl-guc: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-icl-guc/igt at gem_busy@busy at all.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-icl-guc/igt at gem_busy@busy at all.html - fi-kbl-soraka: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-soraka/igt at gem_busy@busy at all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-kbl-soraka/igt at gem_busy@busy at all.html - fi-kbl-7500u: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-7500u/igt at gem_busy@busy at all.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-kbl-7500u/igt at gem_busy@busy at all.html - fi-kbl-guc: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-guc/igt at gem_busy@busy at all.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-kbl-guc/igt at gem_busy@busy at all.html - fi-whl-u: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-whl-u/igt at gem_busy@busy at all.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-whl-u/igt at gem_busy@busy at all.html - fi-cml-u2: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml-u2/igt at gem_busy@busy at all.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cml-u2/igt at gem_busy@busy at all.html - fi-bxt-dsi: [PASS][31] -> [DMESG-WARN][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bxt-dsi/igt at gem_busy@busy at all.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-bxt-dsi/igt at gem_busy@busy at all.html - fi-cml-s: [PASS][33] -> [DMESG-WARN][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml-s/igt at gem_busy@busy at all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cml-s/igt at gem_busy@busy at all.html - fi-cfl-guc: [PASS][35] -> [DMESG-WARN][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cfl-guc/igt at gem_busy@busy at all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cfl-guc/igt at gem_busy@busy at all.html - fi-icl-y: [PASS][37] -> [DMESG-WARN][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-icl-y/igt at gem_busy@busy at all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-icl-y/igt at gem_busy@busy at all.html - fi-skl-guc: [PASS][39] -> [DMESG-WARN][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-skl-guc/igt at gem_busy@busy at all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-skl-guc/igt at gem_busy@busy at all.html - fi-skl-6700k2: [PASS][41] -> [DMESG-WARN][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-skl-6700k2/igt at gem_busy@busy at all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-skl-6700k2/igt at gem_busy@busy at all.html - fi-tgl-u2: NOTRUN -> [DMESG-WARN][43] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-tgl-u2/igt at gem_busy@busy at all.html * igt at gem_close_race@basic-process: - fi-ivb-3770: [PASS][44] -> [DMESG-WARN][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-ivb-3770/igt at gem_close_race@basic-process.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-ivb-3770/igt at gem_close_race@basic-process.html - fi-byt-j1900: [PASS][46] -> [DMESG-WARN][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-byt-j1900/igt at gem_close_race@basic-process.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-byt-j1900/igt at gem_close_race@basic-process.html - fi-hsw-4770: [PASS][48] -> [DMESG-WARN][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-hsw-4770/igt at gem_close_race@basic-process.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-hsw-4770/igt at gem_close_race@basic-process.html - fi-byt-n2820: [PASS][50] -> [DMESG-WARN][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-byt-n2820/igt at gem_close_race@basic-process.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-byt-n2820/igt at gem_close_race@basic-process.html * igt at kms_busy@basic at flip: - fi-snb-2600: [PASS][52] -> [DMESG-WARN][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-snb-2600/igt at kms_busy@basic at flip.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-snb-2600/igt at kms_busy@basic at flip.html - fi-snb-2520m: [PASS][54] -> [DMESG-WARN][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-snb-2520m/igt at kms_busy@basic at flip.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-snb-2520m/igt at kms_busy@basic at flip.html * igt at kms_frontbuffer_tracking@basic: - fi-ilk-650: [PASS][56] -> [DMESG-WARN][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html * igt at runner@aborted: - fi-cfl-8700k: NOTRUN -> [FAIL][58] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cfl-8700k/igt at runner@aborted.html - fi-cfl-8109u: NOTRUN -> [FAIL][59] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cfl-8109u/igt at runner@aborted.html - fi-icl-u2: NOTRUN -> [FAIL][60] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-icl-u2/igt at runner@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][61] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-snb-2520m/igt at runner@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][62] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-bdw-5557u/igt at runner@aborted.html - fi-byt-n2820: NOTRUN -> [FAIL][63] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-byt-n2820/igt at runner@aborted.html - fi-icl-guc: NOTRUN -> [FAIL][64] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-icl-guc/igt at runner@aborted.html - fi-hsw-4770: NOTRUN -> [FAIL][65] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-hsw-4770/igt at runner@aborted.html - fi-snb-2600: NOTRUN -> [FAIL][66] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-snb-2600/igt at runner@aborted.html - fi-whl-u: NOTRUN -> [FAIL][67] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-whl-u/igt at runner@aborted.html - fi-cml-u2: NOTRUN -> [FAIL][68] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cml-u2/igt at runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][69] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-ivb-3770/igt at runner@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][70] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-bxt-dsi/igt at runner@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][71] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-byt-j1900/igt at runner@aborted.html - fi-cml-s: NOTRUN -> [FAIL][72] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cml-s/igt at runner@aborted.html - fi-cfl-guc: NOTRUN -> [FAIL][73] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-cfl-guc/igt at runner@aborted.html - fi-icl-y: NOTRUN -> [FAIL][74] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-icl-y/igt at runner@aborted.html - fi-tgl-u2: NOTRUN -> [FAIL][75] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-tgl-u2/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at gem_busy@busy at all: - {fi-tgl-dsi}: [PASS][76] -> [DMESG-WARN][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-tgl-dsi/igt at gem_busy@busy at all.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-tgl-dsi/igt at gem_busy@busy at all.html - {fi-ehl-1}: [PASS][78] -> [DMESG-WARN][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-ehl-1/igt at gem_busy@busy at all.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-ehl-1/igt at gem_busy@busy at all.html * igt at runner@aborted: - {fi-tgl-dsi}: NOTRUN -> [FAIL][80] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-tgl-dsi/igt at runner@aborted.html - {fi-ehl-1}: NOTRUN -> [FAIL][81] [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-ehl-1/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17923 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-kbl-soraka: [PASS][82] -> [DMESG-WARN][83] ([i915#1982]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-soraka/igt at debugfs_test@read_all_entries.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/fi-kbl-soraka/igt at debugfs_test@read_all_entries.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 Participating hosts (48 -> 42) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17923 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17923: c8130cec52d56bce2b4f09cd005c0f7d68806ac0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c8130cec52d5 drm/i915: Annotate dma_fence_work c40ab1c8276b drm/amdgpu: gpu recovery does full modesets f08fc8bb8383 Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" 718c082d14cb drm/amdgpu: use dma-fence annotations for gpu reset code d1361c491f79 drm/scheduler: use dma-fence annotations in tdr work 2dbc37297b21 drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail 18403b85aff4 drm/amdgpu: DC also loves to allocate stuff where it shouldn't 805637835bf6 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code d05e15f8ad27 drm/amdgpu: use dma-fence annotations in cs_submit() e86ec566effc drm/scheduler: use dma-fence annotations in main thread 812e8d183ea1 drm/amdgpu: add dma-fence annotations to atomic commit path 49852bebf34d drm/atomic-helper: Add dma-fence annotations 74cf66d0c736 drm/vblank: Annotate with dma-fence signalling section abea167ccc2c drm/vkms: Annotate vblank timer e85757129eef dma-fence: prime lockdep annotations 4a356e005b80 dma-fence: basic lockdep annotations 464bebc66202 dma-buf: minor doc touch-ups b91d6e9b2219 mm: Track mmu notifiers in fs_reclaim_acquire/release == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17923/index.html From patchwork at emeril.freedesktop.org Wed Jun 10 20:47:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 20:47:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915=3A_Include_asm_sources_for_=7Bivb=2C_hsw=7D=5Fclea?= =?utf-8?b?cl9rZXJuZWwuYyAocmV2Mik=?= In-Reply-To: <20200608174654.1400710-1-rodrigo.vivi@intel.com> References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Message-ID: <159182206246.20176.9853943734965813787@emeril.freedesktop.org> == Series Details == Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2) URL : https://patchwork.freedesktop.org/series/78126/ State : warning == Summary == $ dim checkpatch origin/drm-tip fbdbc3448e1c drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c -:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #87: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 282 lines checked From patchwork at emeril.freedesktop.org Wed Jun 10 21:08:14 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 10 Jun 2020 21:08:14 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Include_asm_sources_for_=7Bivb=2C_hsw=7D=5Fclear=5Fker?= =?utf-8?b?bmVsLmMgKHJldjIp?= In-Reply-To: <20200608174654.1400710-1-rodrigo.vivi@intel.com> References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Message-ID: <159182329437.20177.4020546159133202191@emeril.freedesktop.org> == Series Details == Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2) URL : https://patchwork.freedesktop.org/series/78126/ State : success == Summary == CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17924 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/index.html Known issues ------------ Here are the changes found in Patchwork_17924 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-cml-s: [DMESG-WARN][1] ([i915#1982]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml-s/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-cml-s/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][3] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][9] ([fdo#109271]) -> [DMESG-FAIL][10] ([i915#62] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17924 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17924: fbdbc3448e1c3c404e07c2aa64e972f31fad7652 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fbdbc3448e1c drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/index.html From paulo.r.zanoni at intel.com Wed Jun 10 22:33:06 2020 From: paulo.r.zanoni at intel.com (Paulo Zanoni) Date: Wed, 10 Jun 2020 15:33:06 -0700 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <20200528053931.29282-2-karthik.b.s@intel.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> Message-ID: <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: > Add enable/disable flip done functions and the flip done handler > function which handles the flip done interrupt. > > Enable the flip done interrupt in IER. > > Enable flip done function is called before writing the > surface address register as the write to this register triggers > the flip done interrupt > > Flip done handler is used to send the page flip event as soon as the > surface address is written as per the requirement of async flips. > The interrupt is disabled after the event is sent. > > v2: -Change function name from icl_* to skl_* (Paulo) > -Move flip handler to this patch (Paulo) > -Remove vblank_put() (Paulo) > -Enable flip done interrupt for gen9+ only (Paulo) > -Enable flip done interrupt in power_well_post_enable hook (Paulo) > -Removed the event check in flip done handler to handle async > flips without pageflip events. > > v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) > -Make the pending vblank event NULL in the begining of > flip_done_handler to remove sporadic WARN_ON that is seen. > > Signed-off-by: Karthik B S <karthik.b.s at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ > drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ > drivers/gpu/drm/i915/i915_irq.h | 2 + > 3 files changed, 64 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f40b909952cc..48cc1fc9bc5a 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > intel_dbuf_pre_plane_update(state); > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > + if (new_crtc_state->uapi.async_flip) { > + skl_enable_flip_done(&crtc->base); > + break; > + } > + } > + > /* Now enable the clocks, plane, pipe, and connectors that we set up. */ > dev_priv->display.commit_modeset_enables(state); > > @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > drm_atomic_helper_wait_for_flip_done(dev, &state->base); > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > + if (new_crtc_state->uapi.async_flip) > + skl_disable_flip_done(&crtc->base); > + > if (new_crtc_state->hw.active && > !needs_modeset(new_crtc_state) && > !new_crtc_state->preload_luts && > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index efdd4c7b8e92..632e7b1deb87 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > u32 crc4) {} > #endif > > +static void flip_done_handler(struct drm_i915_private *dev_priv, > + unsigned int pipe) > +{ > + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); > + struct drm_crtc_state *crtc_state = crtc->base.state; > + struct drm_pending_vblank_event *e = crtc_state->event; > + struct drm_device *dev = &dev_priv->drm; > + unsigned long irqflags; > + > + crtc_state->event = NULL; > + > + spin_lock_irqsave(&dev->event_lock, irqflags); > + > + drm_crtc_send_vblank_event(&crtc->base, e); I don't think this is what we want. With this, the events the Kernel sends us all have the same sequence and timestamp. In fact, the IGT test you submitted fails because of this. In my original hackish proof-of-concept patch I had changed drm_update_vblank_count() to force diff=1 in order to always send events and I also changed g4x_get_vblank_counter() to get the counter from FLIPCOUNT (which updates every time there's a flip) instead of FRMCOUNT (which doesn't seem to increment when you do async flips). That is a drastic change, but the patch was just a PoC so I didn't care about keeping anything else working. One thing that confused me a little bit when dealing the the vblank/flip event interface from drm.ko is that "flips" and "vblanks" seem to be changed interchangeably, which is confusing for async flips: if you keep forever doing async flips in the very first few scanlines you never actually reach the "vblank" period, yet you keep flipping your frame. Then, what should your expectation regarding events be? I think we may need to check how the other drivers handle async vblanks (or how drm.ko wants us to handle async vblanks). Should we increment sequence on every async flip? What about the timestamp? Daniel, Ville, do you happen to know the proper semantics here? There's certainly some adjustment to do to both this patch and the IGT. > + > + spin_unlock_irqrestore(&dev->event_lock, irqflags); > +} > > static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > enum pipe pipe) > @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > if (iir & GEN8_PIPE_VBLANK) > intel_handle_vblank(dev_priv, pipe); > > + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) > + flip_done_handler(dev_priv, pipe); > + > if (iir & GEN8_PIPE_CDCLK_CRC_DONE) > hsw_pipe_crc_irq_handler(dev_priv, pipe); > > @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) > return 0; > } > > +void skl_enable_flip_done(struct drm_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->dev); > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > + unsigned long irqflags; > + > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > + > + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); > + > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > +} > + > /* Called from drm generic code, passed 'crtc' which > * we use as a pipe index > */ > @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) > spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > } > > +void skl_disable_flip_done(struct drm_crtc *crtc) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->dev); > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > + unsigned long irqflags; > + > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > + > + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); > + > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > +} > + > static void ibx_irq_reset(struct drm_i915_private *dev_priv) > { > struct intel_uncore *uncore = &dev_priv->uncore; > @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; > enum pipe pipe; > > + if (INTEL_GEN(dev_priv) >= 9) > + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; > + > spin_lock_irq(&dev_priv->irq_lock); > > if (!intel_irqs_enabled(dev_priv)) { > @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | > GEN8_PIPE_FIFO_UNDERRUN; > > + if (INTEL_GEN(dev_priv) >= 9) > + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; > + > de_port_enables = de_port_masked; > if (IS_GEN9_LP(dev_priv)) > de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; > diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h > index 25f25cd95818..2f10c8135116 100644 > --- a/drivers/gpu/drm/i915/i915_irq.h > +++ b/drivers/gpu/drm/i915/i915_irq.h > @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); > int i965_enable_vblank(struct drm_crtc *crtc); > int ilk_enable_vblank(struct drm_crtc *crtc); > int bdw_enable_vblank(struct drm_crtc *crtc); > +void skl_enable_flip_done(struct drm_crtc *crtc); > void i8xx_disable_vblank(struct drm_crtc *crtc); > void i915gm_disable_vblank(struct drm_crtc *crtc); > void i965_disable_vblank(struct drm_crtc *crtc); > void ilk_disable_vblank(struct drm_crtc *crtc); > void bdw_disable_vblank(struct drm_crtc *crtc); > +void skl_disable_flip_done(struct drm_crtc *crtc); > > void gen2_irq_reset(struct intel_uncore *uncore); > void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, From uma.shankar at intel.com Thu Jun 11 05:08:26 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Thu, 11 Jun 2020 05:08:26 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev3=29?= In-Reply-To: <159181872292.20175.12513317211904900319@emeril.freedesktop.org> References: <20200610191232.11620-1-uma.shankar@intel.com> <159181872292.20175.12513317211904900319@emeril.freedesktop.org> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F825222C2@BGSMSX104.gar.corp.intel.com> > -----Original Message----- > From: Patchwork <patchwork at emeril.freedesktop.org> > Sent: Thursday, June 11, 2020 1:22 AM > To: Shankar, Uma <uma.shankar at intel.com> > Cc: intel-gfx at lists.freedesktop.org > Subject: ? Fi.CI.BAT: failure for Enable HDR on MCA LSPCON based Gen9 devices > (rev3) > > == Series Details == > > Series: Enable HDR on MCA LSPCON based Gen9 devices (rev3) > URL : https://patchwork.freedesktop.org/series/68081/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17922 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17922 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17922, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_17922/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in > Patchwork_17922: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at gem_exec_suspend@basic-s3: > - fi-tgl-u2: NOTRUN -> [FAIL][1] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-tgl- > u2/igt at gem_exec_suspend@basic-s3.html Hi Lakshmi, This failure doesn't seem to be related to my changes. Can you please check and help report. Regards, Uma Shankar > > Known issues > ------------ > > Here are the changes found in Patchwork_17922 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at i915_pm_rpm@module-reload: > - fi-byt-j1900: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-byt- > j1900/igt at i915_pm_rpm@module-reload.html > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-byt- > j1900/igt at i915_pm_rpm@module-reload.html > > > #### Possible fixes #### > > * igt at i915_pm_rpm@module-reload: > - fi-cml-s: [DMESG-WARN][4] ([i915#1982]) -> [PASS][5] > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml- > s/igt at i915_pm_rpm@module-reload.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-cml- > s/igt at i915_pm_rpm@module-reload.html > > * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-bsw-n3050: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw- > n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw- > n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > - fi-bsw-kefka: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9] > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw- > kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw- > kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > > #### Warnings #### > > * igt at gem_exec_suspend@basic-s0: > - fi-kbl-x1275: [DMESG-WARN][10] ([i915#62] / [i915#92]) -> [DMESG- > WARN][11] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl- > x1275/igt at gem_exec_suspend@basic-s0.html > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl- > x1275/igt at gem_exec_suspend@basic-s0.html > > * igt at kms_flip@basic-flip-vs-modeset at a-dp1: > - fi-kbl-x1275: [DMESG-WARN][12] ([i915#62] / [i915#92]) -> [DMESG- > WARN][13] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl- > x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl- > x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > > * igt at kms_force_connector_basic@force-edid: > - fi-kbl-x1275: [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) -> > [DMESG-WARN][15] ([i915#62] / [i915#92]) +8 similar issues > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl- > x1275/igt at kms_force_connector_basic@force-edid.html > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl- > x1275/igt at kms_force_connector_basic@force-edid.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (48 -> 43) > ------------------------------ > > Additional (2): fi-kbl-7560u fi-tgl-u2 > Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi- > byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * Linux: CI_DRM_8611 -> Patchwork_17922 > > CI-20190529: 20190529 > CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17922: 0903ebe28a8fb9c912916613977b2e77d83eac8c @ > git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > 0903ebe28a8f drm/i915/display: [NOT FOR MERGE] Reduce blanking to support > 4k60 at 10bpp for LSPCON e67c4219c55f drm/i915/display: Implement DRM > infoframe read for LSPCON 90fe2351734a drm/i915/display: Implement > infoframes readback for LSPCON 7aab4641b28f drm/i915/display: Enable HDR for > Parade based lspcon > e71a13eb3147 drm/i915/display: Enable BT2020 for HDR on LSPCON devices > 5940d801abf4 drm/i915/display: Attach HDR property for capable Gen9 devices > ae1436b72a1c drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon > 292e80f577e6 drm/i915/display: Add HDR Capability detection for LSPCON > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_17922/index.html From patchwork at emeril.freedesktop.org Thu Jun 11 05:43:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 05:43:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev3=29?= In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <159185421736.22714.13394861558378645759@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev3) URL : https://patchwork.freedesktop.org/series/68081/ State : success == Summary == CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17922 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/index.html Known issues ------------ Here are the changes found in Patchwork_17922 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-cml-s: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml-s/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-cml-s/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 43) ------------------------------ Additional (2): fi-kbl-7560u fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17922 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17922: 0903ebe28a8fb9c912916613977b2e77d83eac8c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 0903ebe28a8f drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60 at 10bpp for LSPCON e67c4219c55f drm/i915/display: Implement DRM infoframe read for LSPCON 90fe2351734a drm/i915/display: Implement infoframes readback for LSPCON 7aab4641b28f drm/i915/display: Enable HDR for Parade based lspcon e71a13eb3147 drm/i915/display: Enable BT2020 for HDR on LSPCON devices 5940d801abf4 drm/i915/display: Attach HDR property for capable Gen9 devices ae1436b72a1c drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon 292e80f577e6 drm/i915/display: Add HDR Capability detection for LSPCON == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/index.html From lakshminarayana.vudum at intel.com Thu Jun 11 05:51:57 2020 From: lakshminarayana.vudum at intel.com (Vudum, Lakshminarayana) Date: Thu, 11 Jun 2020 05:51:57 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev3=29?= In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F825222C2@BGSMSX104.gar.corp.intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <159181872292.20175.12513317211904900319@emeril.freedesktop.org> <E7C9878FBA1C6D42A1CA3F62AEB6945F825222C2@BGSMSX104.gar.corp.intel.com> Message-ID: <bf6386e5712a443eae2cf64c7a46c472@intel.com> Results are re-reported. -----Original Message----- From: Shankar, Uma <uma.shankar at intel.com> Sent: Thursday, June 11, 2020 8:08 AM To: intel-gfx at lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum at intel.com> Subject: RE: ? Fi.CI.BAT: failure for Enable HDR on MCA LSPCON based Gen9 devices (rev3) > -----Original Message----- > From: Patchwork <patchwork at emeril.freedesktop.org> > Sent: Thursday, June 11, 2020 1:22 AM > To: Shankar, Uma <uma.shankar at intel.com> > Cc: intel-gfx at lists.freedesktop.org > Subject: ? Fi.CI.BAT: failure for Enable HDR on MCA LSPCON based Gen9 > devices > (rev3) > > == Series Details == > > Series: Enable HDR on MCA LSPCON based Gen9 devices (rev3) > URL : https://patchwork.freedesktop.org/series/68081/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8611 -> Patchwork_17922 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17922 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17922, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_17922/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in > Patchwork_17922: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at gem_exec_suspend@basic-s3: > - fi-tgl-u2: NOTRUN -> [FAIL][1] > [1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-tgl- > u2/igt at gem_exec_suspend@basic-s3.html Hi Lakshmi, This failure doesn't seem to be related to my changes. Can you please check and help report. Regards, Uma Shankar > > Known issues > ------------ > > Here are the changes found in Patchwork_17922 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at i915_pm_rpm@module-reload: > - fi-byt-j1900: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-byt- > j1900/igt at i915_pm_rpm@module-reload.html > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-byt- > j1900/igt at i915_pm_rpm@module-reload.html > > > #### Possible fixes #### > > * igt at i915_pm_rpm@module-reload: > - fi-cml-s: [DMESG-WARN][4] ([i915#1982]) -> [PASS][5] > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-cml- > s/igt at i915_pm_rpm@module-reload.html > [5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-cml- > s/igt at i915_pm_rpm@module-reload.html > > * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-bsw-n3050: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw- > n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw- > n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > - fi-bsw-kefka: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9] > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-bsw- > kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-bsw- > kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > > #### Warnings #### > > * igt at gem_exec_suspend@basic-s0: > - fi-kbl-x1275: [DMESG-WARN][10] ([i915#62] / [i915#92]) -> [DMESG- > WARN][11] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl- > x1275/igt at gem_exec_suspend@basic-s0.html > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl- > x1275/igt at gem_exec_suspend@basic-s0.html > > * igt at kms_flip@basic-flip-vs-modeset at a-dp1: > - fi-kbl-x1275: [DMESG-WARN][12] ([i915#62] / [i915#92]) -> [DMESG- > WARN][13] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl- > x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > [13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl- > x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > > * igt at kms_force_connector_basic@force-edid: > - fi-kbl-x1275: [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) -> > [DMESG-WARN][15] ([i915#62] / [i915#92]) +8 similar issues > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/fi-kbl- > x1275/igt at kms_force_connector_basic@force-edid.html > [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/fi-kbl- > x1275/igt at kms_force_connector_basic@force-edid.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (48 -> 43) > ------------------------------ > > Additional (2): fi-kbl-7560u fi-tgl-u2 > Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi- > byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * Linux: CI_DRM_8611 -> Patchwork_17922 > > CI-20190529: 20190529 > CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17922: 0903ebe28a8fb9c912916613977b2e77d83eac8c @ > git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > 0903ebe28a8f drm/i915/display: [NOT FOR MERGE] Reduce blanking to > support 4k60 at 10bpp for LSPCON e67c4219c55f drm/i915/display: Implement > DRM infoframe read for LSPCON 90fe2351734a drm/i915/display: Implement > infoframes readback for LSPCON 7aab4641b28f drm/i915/display: Enable > HDR for Parade based lspcon > e71a13eb3147 drm/i915/display: Enable BT2020 for HDR on LSPCON devices > 5940d801abf4 drm/i915/display: Attach HDR property for capable Gen9 > devices ae1436b72a1c drm/i915/display: Enable HDR on gen9 devices with > MCA Lspcon > 292e80f577e6 drm/i915/display: Add HDR Capability detection for LSPCON > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_17922/index.html --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From thomas_os at shipmail.org Thu Jun 11 07:30:12 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Thu, 11 Jun 2020 09:30:12 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200604081224.863494-5-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> Message-ID: <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> On 6/4/20 10:12 AM, Daniel Vetter wrote: > Two in one go: > - it is allowed to call dma_fence_wait() while holding a > dma_resv_lock(). This is fundamental to how eviction works with ttm, > so required. > > - it is allowed to call dma_fence_wait() from memory reclaim contexts, > specifically from shrinker callbacks (which i915 does), and from mmu > notifier callbacks (which amdgpu does, and which i915 sometimes also > does, and probably always should, but that's kinda a debate). Also > for stuff like HMM we really need to be able to do this, or things > get real dicey. > > Consequence is that any critical path necessary to get to a > dma_fence_signal for a fence must never a) call dma_resv_lock nor b) > allocate memory with GFP_KERNEL. Also by implication of > dma_resv_lock(), no userspace faulting allowed. That's some supremely > obnoxious limitations, which is why we need to sprinkle the right > annotations to all relevant paths. > > The one big locking context we're leaving out here is mmu notifiers, > added in > > commit 23b68395c7c78a764e8963fc15a7cfd318bf187f > Author: Daniel Vetter <daniel.vetter at ffwll.ch> > Date: Mon Aug 26 22:14:21 2019 +0200 > > mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end > > that one covers a lot of other callsites, and it's also allowed to > wait on dma-fences from mmu notifiers. But there's no ready-made > functions exposed to prime this, so I've left it out for now. > > v2: Also track against mmu notifier context. > > v3: kerneldoc to spec the cross-driver contract. Note that currently > i915 throws in a hard-coded 10s timeout on foreign fences (not sure > why that was done, but it's there), which is why that rule is worded > with SHOULD instead of MUST. > > Also some of the mmu_notifier/shrinker rules might surprise SoC > drivers, I haven't fully audited them all. Which is infeasible anyway, > we'll need to run them with lockdep and dma-fence annotations and see > what goes boom. > > v4: A spelling fix from Mika > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > Cc: linux-media at vger.kernel.org > Cc: linaro-mm-sig at lists.linaro.org > Cc: linux-rdma at vger.kernel.org > Cc: amd-gfx at lists.freedesktop.org > Cc: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > Documentation/driver-api/dma-buf.rst | 6 ++++ > drivers/dma-buf/dma-fence.c | 41 ++++++++++++++++++++++++++++ > drivers/dma-buf/dma-resv.c | 4 +++ > include/linux/dma-fence.h | 1 + > 4 files changed, 52 insertions(+) I still have my doubts about allowing fence waiting from within shrinkers. IMO ideally they should use a trywait approach, in order to allow memory allocation during command submission for drivers that publish fences before command submission. (Since early reservation object release requires that). But since drivers are already waiting from within shrinkers and I take your word for HMM requiring this, Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> From tzimmermann at suse.de Thu Jun 11 07:50:07 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Thu, 11 Jun 2020 09:50:07 +0200 Subject: [Intel-gfx] [PULL] drm-misc-next-fixes Message-ID: <20200611075007.GA15098@linux-uq9g> Hi Dave and Daniel, here's the PR for the latest fixes in drm-misc-next-fixes. Best regards Thomas drm-misc-next-fixes-2020-06-11: In core, DRM connectors now notify userspace of hotplug events via sysfs. In drivers, sun4i now uses 4 bits to store the clock's m divider; ast sets up 24/32-bit color mode correctly. The following changes since commit 9ca1f474cea0edc14a1d7ec933e5472c0ff115d3: Merge tag 'amd-drm-next-5.8-2020-05-27' of git://people.freedesktop.org/~agd5f/linux into drm-next (2020-05-28 16:10:17 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2020-06-11 for you to fetch changes up to 291ddeb621e4a9f1ced8302a777fbd7fbda058c6: drm/ast: fix missing break in switch statement for format->cpp[0] case 4 (2020-06-11 09:05:31 +0200) ---------------------------------------------------------------- In core, DRM connectors now notify userspace of hotplug events via sysfs. In drivers, sun4i now uses 4 bits to store the clock's m divider; ast sets up 24/32-bit color mode correctly. ---------------------------------------------------------------- Colin Ian King (1): drm/ast: fix missing break in switch statement for format->cpp[0] case 4 Jernej Skrabec (1): drm/sun4i: hdmi ddc clk: Fix size of m divider Jeykumar Sankaran (1): drm/connector: notify userspace on hotplug after register complete drivers/gpu/drm/ast/ast_mode.c | 1 + drivers/gpu/drm/drm_connector.c | 5 +++++ drivers/gpu/drm/drm_sysfs.c | 3 --- drivers/gpu/drm/sun4i/sun4i_hdmi.h | 2 +- drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 2 +- 5 files changed, 8 insertions(+), 5 deletions(-) From chris at chris-wilson.co.uk Thu Jun 11 08:00:36 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 09:00:36 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <20200604081224.863494-4-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> Message-ID: <159186243606.1506.4437341616828968890@build.alporthouse.com> Quoting Daniel Vetter (2020-06-04 09:12:09) > Design is similar to the lockdep annotations for workers, but with > some twists: > > - We use a read-lock for the execution/worker/completion side, so that > this explicit annotation can be more liberally sprinkled around. > With read locks lockdep isn't going to complain if the read-side > isn't nested the same way under all circumstances, so ABBA deadlocks > are ok. Which they are, since this is an annotation only. > > - We're using non-recursive lockdep read lock mode, since in recursive > read lock mode lockdep does not catch read side hazards. And we > _very_ much want read side hazards to be caught. For full details of > this limitation see > > commit e91498589746065e3ae95d9a00b068e525eec34f > Author: Peter Zijlstra <peterz at infradead.org> > Date: Wed Aug 23 13:13:11 2017 +0200 > > locking/lockdep/selftests: Add mixed read-write ABBA tests > > - To allow nesting of the read-side explicit annotations we explicitly > keep track of the nesting. lock_is_held() allows us to do that. > > - The wait-side annotation is a write lock, and entirely done within > dma_fence_wait() for everyone by default. > > - To be able to freely annotate helper functions I want to make it ok > to call dma_fence_begin/end_signalling from soft/hardirq context. > First attempt was using the hardirq locking context for the write > side in lockdep, but this forces all normal spinlocks nested within > dma_fence_begin/end_signalling to be spinlocks. That bollocks. > > The approach now is to simple check in_atomic(), and for these cases > entirely rely on the might_sleep() check in dma_fence_wait(). That > will catch any wrong nesting against spinlocks from soft/hardirq > contexts. > > The idea here is that every code path that's critical for eventually > signalling a dma_fence should be annotated with > dma_fence_begin/end_signalling. The annotation ideally starts right > after a dma_fence is published (added to a dma_resv, exposed as a > sync_file fd, attached to a drm_syncobj fd, or anything else that > makes the dma_fence visible to other kernel threads), up to and > including the dma_fence_wait(). Examples are irq handlers, the > scheduler rt threads, the tail of execbuf (after the corresponding > fences are visible), any workers that end up signalling dma_fences and > really anything else. Not annotated should be code paths that only > complete fences opportunistically as the gpu progresses, like e.g. > shrinker/eviction code. > > The main class of deadlocks this is supposed to catch are: > > Thread A: > > mutex_lock(A); > mutex_unlock(A); > > dma_fence_signal(); > > Thread B: > > mutex_lock(A); > dma_fence_wait(); > mutex_unlock(A); > > Thread B is blocked on A signalling the fence, but A never gets around > to that because it cannot acquire the lock A. > > Note that dma_fence_wait() is allowed to be nested within > dma_fence_begin/end_signalling sections. To allow this to happen the > read lock needs to be upgraded to a write lock, which means that any > other lock is acquired between the dma_fence_begin_signalling() call and > the call to dma_fence_wait(), and still held, this will result in an > immediate lockdep complaint. The only other option would be to not > annotate such calls, defeating the point. Therefore these annotations > cannot be sprinkled over the code entirely mindless to avoid false > positives. > > v2: handle soft/hardirq ctx better against write side and dont forget > EXPORT_SYMBOL, drivers can't use this otherwise. > > v3: Kerneldoc. > > v4: Some spelling fixes from Mika > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > Cc: linux-media at vger.kernel.org > Cc: linaro-mm-sig at lists.linaro.org > Cc: linux-rdma at vger.kernel.org > Cc: amd-gfx at lists.freedesktop.org > Cc: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Introducing a global lockmap that cannot capture the rules correctly, Nacked-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Thu Jun 11 08:01:39 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 09:01:39 +0100 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <20200611080140.30228-5-chris@chris-wilson.co.uk> Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 10 ---------- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 7b4f3434eb6b..f8b9e104378e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -714,6 +714,18 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) return 0; } +static void +ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); + + /* WaDisableRenderCachePipelinedFlush:ilk */ + wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); + + /* WaDisable_RenderCache_OperationalFlush:ilk */ + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); +} + static void snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { @@ -1195,6 +1207,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) ivb_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 6)) snb_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 5)) + ilk_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b4bea6451418..7d82a7144a13 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6921,16 +6921,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(ILK_DISPLAY_CHICKEN2, I915_READ(ILK_DISPLAY_CHICKEN2) | ILK_ELPIN_409_SELECT); - I915_WRITE(_3D_CHICKEN2, - _3D_CHICKEN2_WM_READ_PIPELINED << 16 | - _3D_CHICKEN2_WM_READ_PIPELINED); - - /* WaDisableRenderCachePipelinedFlush:ilk */ - I915_WRITE(CACHE_MODE_0, - _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); - - /* WaDisable_RenderCache_OperationalFlush:ilk */ - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); g4x_disable_trickle_feed(dev_priv); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 11 08:01:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 09:01:35 +0100 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds Message-ID: <20200611080140.30228-1-chris@chris-wilson.co.uk> Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011 Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 39 +---------------- 2 files changed, 50 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3eec31c5a714..39f070bff09d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) wa_write_masked_or(wal, reg, set, set); } +static void +wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) +{ + wa_write_masked_or(wal, reg, clr, 0); +} + static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { @@ -708,6 +714,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) return 0; } +static void +hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + /* L3 caching of data atomics doesn't work -- disable it. */ + wa_write_or(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); + + wa_add(wal, + HSW_ROW_CHICKEN3, 0, + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), + 0 /* XXX does this reg exist? */); + + /* WaVSRefCountFullforceMissDisable:hsw */ + wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); + + wa_masked_dis(wal, + CACHE_MODE_0_GEN7, + /* WaDisable_RenderCache_OperationalFlush:hsw */ + RC_OP_FLUSH_ENABLE | + /* enable HiZ Raw Stall Optimization */ + HIZ_RAW_STALL_OPT_DISABLE); + + /* WaDisable4x2SubspanOptimization:hsw */ + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); + + /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). + */ + wa_add(wal, GEN7_GT_MODE, 0, + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), + GEN6_WIZ_HASHING_16x4); + + /* WaSampleCChickenBitEnable:hsw */ + wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); +} + static void gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { @@ -985,6 +1031,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) bxt_gt_workarounds_init(i915, wal); else if (IS_SKYLAKE(i915)) skl_gt_workarounds_init(i915, wal); + else if (IS_HASWELL(i915)) + hsw_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 26b670fa3f88..249ee720874c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7321,45 +7321,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) { - /* L3 caching of data atomics doesn't work -- disable it. */ - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); - I915_WRITE(HSW_ROW_CHICKEN3, - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); - /* This is required by WaCatErrorRejectionIssue:hsw */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - - /* WaVSRefCountFullforceMissDisable:hsw */ - I915_WRITE(GEN7_FF_THREAD_MODE, - I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); - - /* WaDisable_RenderCache_OperationalFlush:hsw */ - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - - /* enable HiZ Raw Stall Optimization */ - I915_WRITE(CACHE_MODE_0_GEN7, - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); - - /* WaDisable4x2SubspanOptimization:hsw */ - I915_WRITE(CACHE_MODE_1, - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); - - /* - * BSpec recommends 8x4 when MSAA is used, - * however in practice 16x4 seems fastest. - * - * Note that PS/WM thread counts depend on the WIZ hashing - * disable bit, which we don't touch here, but it's good - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). - */ - I915_WRITE(GEN7_GT_MODE, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); - - /* WaSampleCChickenBitEnable:hsw */ - I915_WRITE(HALF_SLICE_CHICKEN3, - _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); /* WaSwitchSolVfFArbitrationPriority:hsw */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 11 08:01:40 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 09:01:40 +0100 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <20200611080140.30228-6-chris@chris-wilson.co.uk> Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++++++++++++++---- drivers/gpu/drm/i915/intel_pm.c | 15 ------------ 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f8b9e104378e..7b4be64585c3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -715,15 +715,28 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) } static void -ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen4_gt_workarounds_init(struct drm_i915_private *i915, + struct i915_wa_list *wal) { - wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); + /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); +} + +static void +g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen4_gt_workarounds_init(i915, wal); - /* WaDisableRenderCachePipelinedFlush:ilk */ + /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); +} - /* WaDisable_RenderCache_OperationalFlush:ilk */ - wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); +static void +ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + g4x_gt_workarounds_init(i915, wal); + + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); } static void @@ -1209,6 +1222,10 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) snb_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 5)) ilk_gt_workarounds_init(i915, wal); + else if (IS_G4X(i915)) + g4x_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 4)) + gen4_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7d82a7144a13..2a32d6230795 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7399,13 +7399,6 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; I915_WRITE(DSPCLK_GATE_D, dspclk_gate); - /* WaDisableRenderCachePipelinedFlush */ - I915_WRITE(CACHE_MODE_0, - _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); - - /* WaDisable_RenderCache_OperationalFlush:g4x */ - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - g4x_disable_trickle_feed(dev_priv); } @@ -7421,11 +7414,6 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv) intel_uncore_write(uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); - - /* WaDisable_RenderCache_OperationalFlush:gen4 */ - intel_uncore_write(uncore, - CACHE_MODE_0, - _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); } static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) @@ -7438,9 +7426,6 @@ static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(RENCLK_GATE_D2, 0); I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); - - /* WaDisable_RenderCache_OperationalFlush:gen4 */ - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); } static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 11 08:01:37 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 09:01:37 +0100 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <20200611080140.30228-3-chris@chris-wilson.co.uk> Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 61 --------------------- 2 files changed, 59 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index a5ba3ea8d45a..688ca25d79d0 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -774,6 +774,63 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) GEN6_WIZ_HASHING_16x4); } +static void +vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + /* WaDisableEarlyCull:vlv */ + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); + + /* WaPsdDispatchEnable:vlv */ + /* WaDisablePSDDualDispatchEnable:vlv */ + wa_masked_en(wal, + GEN7_HALF_SLICE_CHICKEN1, + GEN7_MAX_PS_THREAD_DEP | + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); + + /* WaDisable_RenderCache_OperationalFlush:vlv */ + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); + + /* WaForceL3Serialization:vlv */ + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); + + /* + * WaVSThreadDispatchOverride:ivb,vlv + * + * This actually overrides the dispatch + * mode for all thread types. + */ + wa_write_masked_or(wal, + GEN7_FF_THREAD_MODE, + GEN7_FF_SCHED_MASK, + GEN7_FF_TS_SCHED_HW | + GEN7_FF_VS_SCHED_HW | + GEN7_FF_DS_SCHED_HW); + + /* + * BSpec says this must be set, even though + * WaDisable4x2SubspanOptimization isn't listed for VLV. + */ + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); + + /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). + */ + wa_add(wal, GEN7_GT_MODE, 0, + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), + GEN6_WIZ_HASHING_16x4); + + /* + * WaIncreaseL3CreditsForVLVB0:vlv + * This is the hardware default actually. + */ + wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); +} + static void hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { @@ -1093,6 +1150,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) skl_gt_workarounds_init(i915, wal); else if (IS_HASWELL(i915)) hsw_gt_workarounds_init(i915, wal); + else if (IS_VALLEYVIEW(i915)) + vlv_gt_workarounds_init(i915, wal); else if (IS_IVYBRIDGE(i915)) ivb_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b835e5e97515..29abde47e987 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7077,24 +7077,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) gen6_check_mch_setup(dev_priv); } -static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) -{ - u32 reg = I915_READ(GEN7_FF_THREAD_MODE); - - /* - * WaVSThreadDispatchOverride:ivb,vlv - * - * This actually overrides the dispatch - * mode for all thread types. - */ - reg &= ~GEN7_FF_SCHED_MASK; - reg |= GEN7_FF_TS_SCHED_HW; - reg |= GEN7_FF_VS_SCHED_HW; - reg |= GEN7_FF_DS_SCHED_HW; - - I915_WRITE(GEN7_FF_THREAD_MODE, reg); -} - static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) { /* @@ -7381,28 +7363,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) { - /* WaDisableEarlyCull:vlv */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); - /* WaDisableBackToBackFlipFix:vlv */ I915_WRITE(IVB_CHICKEN3, CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); - /* WaPsdDispatchEnable:vlv */ - /* WaDisablePSDDualDispatchEnable:vlv */ - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, - _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | - GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); - - /* WaDisable_RenderCache_OperationalFlush:vlv */ - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - - /* WaForceL3Serialization:vlv */ - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & - ~L3SQ_URB_READ_CAM_MATCH_DISABLE); - /* WaDisableDopClockGating:vlv */ I915_WRITE(GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); @@ -7412,8 +7377,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - gen7_setup_fixed_func_scheduler(dev_priv); - /* * According to the spec, bit 13 (RCZUNIT) must be set on IVB. * This implements the WaDisableRCZUnitClockGating:vlv workaround. @@ -7427,30 +7390,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(GEN7_UCGCTL4, I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); - /* - * BSpec says this must be set, even though - * WaDisable4x2SubspanOptimization isn't listed for VLV. - */ - I915_WRITE(CACHE_MODE_1, - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); - - /* - * BSpec recommends 8x4 when MSAA is used, - * however in practice 16x4 seems fastest. - * - * Note that PS/WM thread counts depend on the WIZ hashing - * disable bit, which we don't touch here, but it's good - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). - */ - I915_WRITE(GEN7_GT_MODE, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); - - /* - * WaIncreaseL3CreditsForVLVB0:vlv - * This is the hardware default actually. - */ - I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); - /* * WaDisableVLVClockGating_VBIIssue:vlv * Disable clock gating on th GCFG unit to prevent a delay -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 11 08:01:36 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 09:01:36 +0100 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <20200611080140.30228-2-chris@chris-wilson.co.uk> Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 48 ---------------- 3 files changed, 63 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 39f070bff09d..a5ba3ea8d45a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -714,6 +714,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) return 0; } +static void +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + /* WaDisableEarlyCull:ivb */ + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); + + /* WaDisablePSDDualDispatchEnable:ivb */ + if (IS_IVB_GT1(i915)) + wa_masked_en(wal, + GEN7_HALF_SLICE_CHICKEN1, + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); + + /* WaDisable_RenderCache_OperationalFlush:ivb */ + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); + + /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ + wa_masked_dis(wal, + GEN7_COMMON_SLICE_CHICKEN1, + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); + + /* WaApplyL3ControlAndL3ChickenMode:ivb */ + wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); + wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); + + /* WaForceL3Serialization:ivb */ + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); + + /* + * WaVSThreadDispatchOverride:ivb,vlv + * + * This actually overrides the dispatch + * mode for all thread types. + */ + wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, + GEN7_FF_SCHED_MASK, + GEN7_FF_TS_SCHED_HW | + GEN7_FF_VS_SCHED_HW | + GEN7_FF_DS_SCHED_HW); + + if (0) { /* causes HiZ corruption on ivb:gt1 */ + /* enable HiZ Raw Stall Optimization */ + wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); + } + + /* WaDisable4x2SubspanOptimization:ivb */ + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); + + /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). + */ + wa_add(wal, GEN7_GT_MODE, 0, + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), + GEN6_WIZ_HASHING_16x4); +} + static void hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { @@ -1033,6 +1093,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) skl_gt_workarounds_init(i915, wal); else if (IS_HASWELL(i915)) hsw_gt_workarounds_init(i915, wal); + else if (IS_IVYBRIDGE(i915)) + ivb_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9aca6d778220..19e1fed198c3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7924,7 +7924,7 @@ enum { /* GEN7 chicken */ #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) - #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) + #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 249ee720874c..b835e5e97515 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7338,32 +7338,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); - /* WaDisableEarlyCull:ivb */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); - /* WaDisableBackToBackFlipFix:ivb */ I915_WRITE(IVB_CHICKEN3, CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | CHICKEN3_DGMG_DONE_FIX_DISABLE); - /* WaDisablePSDDualDispatchEnable:ivb */ - if (IS_IVB_GT1(dev_priv)) - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); - - /* WaDisable_RenderCache_OperationalFlush:ivb */ - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - - /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ - I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, - GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); - - /* WaApplyL3ControlAndL3ChickenMode:ivb */ - I915_WRITE(GEN7_L3CNTLREG1, - GEN7_WA_FOR_GEN7_L3_CONTROL); - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, - GEN7_WA_L3_CHICKEN_MODE); if (IS_IVB_GT1(dev_priv)) I915_WRITE(GEN7_ROW_CHICKEN2, _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); @@ -7375,10 +7354,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); } - /* WaForceL3Serialization:ivb */ - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & - ~L3SQ_URB_READ_CAM_MATCH_DISABLE); - /* * According to the spec, bit 13 (RCZUNIT) must be set on IVB. * This implements the WaDisableRCZUnitClockGating:ivb workaround. @@ -7393,29 +7368,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) g4x_disable_trickle_feed(dev_priv); - gen7_setup_fixed_func_scheduler(dev_priv); - - if (0) { /* causes HiZ corruption on ivb:gt1 */ - /* enable HiZ Raw Stall Optimization */ - I915_WRITE(CACHE_MODE_0_GEN7, - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); - } - - /* WaDisable4x2SubspanOptimization:ivb */ - I915_WRITE(CACHE_MODE_1, - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); - - /* - * BSpec recommends 8x4 when MSAA is used, - * however in practice 16x4 seems fastest. - * - * Note that PS/WM thread counts depend on the WIZ hashing - * disable bit, which we don't touch here, but it's good - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). - */ - I915_WRITE(GEN7_GT_MODE, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); - snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); snpcr &= ~GEN6_MBC_SNPCR_MASK; snpcr |= GEN6_MBC_SNPCR_MED; -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 11 08:01:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 09:01:38 +0100 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <20200611080140.30228-4-chris@chris-wilson.co.uk> Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 41 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 33 ----------------- 2 files changed, 41 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 688ca25d79d0..7b4f3434eb6b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -714,6 +714,45 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) return 0; } +static void +snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ + wa_masked_en(wal, + _3D_CHICKEN, + _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); + + /* WaDisable_RenderCache_OperationalFlush:snb */ + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); + + /* + * BSpec recoomends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). + */ + wa_add(wal, + GEN6_GT_MODE, 0, + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), + GEN6_WIZ_HASHING_16x4); + + wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB); + + wa_masked_en(wal, + _3D_CHICKEN3, + /* WaStripsFansDisableFastClipPerformanceFix:snb */ + _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | + /* + * Bspec says: + * "This bit must be set if 3DSTATE_CLIP clip mode is set + * to normal and 3DSTATE_SF number of SF output attributes + * is more than 16." + */ + _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); +} + static void ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { @@ -1154,6 +1193,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) vlv_gt_workarounds_init(i915, wal); else if (IS_IVYBRIDGE(i915)) ivb_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 6)) + snb_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 29abde47e987..b4bea6451418 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6993,27 +6993,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) I915_READ(ILK_DISPLAY_CHICKEN2) | ILK_ELPIN_409_SELECT); - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ - I915_WRITE(_3D_CHICKEN, - _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); - - /* WaDisable_RenderCache_OperationalFlush:snb */ - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - - /* - * BSpec recoomends 8x4 when MSAA is used, - * however in practice 16x4 seems fastest. - * - * Note that PS/WM thread counts depend on the WIZ hashing - * disable bit, which we don't touch here, but it's good - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). - */ - I915_WRITE(GEN6_GT_MODE, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); - - I915_WRITE(CACHE_MODE_0, - _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); - I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | @@ -7036,18 +7015,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); - /* WaStripsFansDisableFastClipPerformanceFix:snb */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); - - /* - * Bspec says: - * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and - * 3DSTATE_SF number of SF output attributes is more than 16." - */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); - /* * According to the spec the following bits should be * set in order to enable memory self-refresh and fbc: -- 2.20.1 From daniel at ffwll.ch Thu Jun 11 08:34:30 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Thu, 11 Jun 2020 10:34:30 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> Message-ID: <20200611083430.GD20149@phenom.ffwll.local> On Thu, Jun 11, 2020 at 09:30:12AM +0200, Thomas Hellstr?m (Intel) wrote: > > On 6/4/20 10:12 AM, Daniel Vetter wrote: > > Two in one go: > > - it is allowed to call dma_fence_wait() while holding a > > dma_resv_lock(). This is fundamental to how eviction works with ttm, > > so required. > > > > - it is allowed to call dma_fence_wait() from memory reclaim contexts, > > specifically from shrinker callbacks (which i915 does), and from mmu > > notifier callbacks (which amdgpu does, and which i915 sometimes also > > does, and probably always should, but that's kinda a debate). Also > > for stuff like HMM we really need to be able to do this, or things > > get real dicey. > > > > Consequence is that any critical path necessary to get to a > > dma_fence_signal for a fence must never a) call dma_resv_lock nor b) > > allocate memory with GFP_KERNEL. Also by implication of > > dma_resv_lock(), no userspace faulting allowed. That's some supremely > > obnoxious limitations, which is why we need to sprinkle the right > > annotations to all relevant paths. > > > > The one big locking context we're leaving out here is mmu notifiers, > > added in > > > > commit 23b68395c7c78a764e8963fc15a7cfd318bf187f > > Author: Daniel Vetter <daniel.vetter at ffwll.ch> > > Date: Mon Aug 26 22:14:21 2019 +0200 > > > > mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end > > > > that one covers a lot of other callsites, and it's also allowed to > > wait on dma-fences from mmu notifiers. But there's no ready-made > > functions exposed to prime this, so I've left it out for now. > > > > v2: Also track against mmu notifier context. > > > > v3: kerneldoc to spec the cross-driver contract. Note that currently > > i915 throws in a hard-coded 10s timeout on foreign fences (not sure > > why that was done, but it's there), which is why that rule is worded > > with SHOULD instead of MUST. > > > > Also some of the mmu_notifier/shrinker rules might surprise SoC > > drivers, I haven't fully audited them all. Which is infeasible anyway, > > we'll need to run them with lockdep and dma-fence annotations and see > > what goes boom. > > > > v4: A spelling fix from Mika > > > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > > Cc: linux-media at vger.kernel.org > > Cc: linaro-mm-sig at lists.linaro.org > > Cc: linux-rdma at vger.kernel.org > > Cc: amd-gfx at lists.freedesktop.org > > Cc: intel-gfx at lists.freedesktop.org > > Cc: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > --- > > Documentation/driver-api/dma-buf.rst | 6 ++++ > > drivers/dma-buf/dma-fence.c | 41 ++++++++++++++++++++++++++++ > > drivers/dma-buf/dma-resv.c | 4 +++ > > include/linux/dma-fence.h | 1 + > > 4 files changed, 52 insertions(+) > > I still have my doubts about allowing fence waiting from within shrinkers. > IMO ideally they should use a trywait approach, in order to allow memory > allocation during command submission for drivers that > publish fences before command submission. (Since early reservation object > release requires that). Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up with a mempool to make sure it can handle it's allocations. > But since drivers are already waiting from within shrinkers and I take your > word for HMM requiring this, Yeah the big trouble is HMM and mmu notifiers. That's the really awkward one, the shrinker one is a lot less established. I do wonder whether the mmu notifier constraint should only be set when mmu notifiers are enabled, since on a bunch of arm-soc gpu drivers that stuff just doesn't matter. But I expect that sooner or later these arm gpus will show up in bigger arm cores, where you might want to have kvm and maybe device virtualization and stuff, and then you need mmu notifiers. Plus having a very clear and consistent cross-driver api contract is imo better than leaving this up to drivers and then having incompatible assumptions. I've pinged a bunch of armsoc gpu driver people and ask them how much this hurts, so that we have a clear answer. On x86 I don't think we have much of a choice on this, with userptr in amd and i915 and hmm work in nouveau (but nouveau I think doesn't use dma_fence in there). I think it'll take us a while to really bottom out on this specific question here. -Daniel > > Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From airlied at gmail.com Thu Jun 11 08:44:26 2020 From: airlied at gmail.com (Dave Airlie) Date: Thu, 11 Jun 2020 18:44:26 +1000 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <159186243606.1506.4437341616828968890@build.alporthouse.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> Message-ID: <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> On Thu, 11 Jun 2020 at 18:01, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Quoting Daniel Vetter (2020-06-04 09:12:09) > > Design is similar to the lockdep annotations for workers, but with > > some twists: > > > > - We use a read-lock for the execution/worker/completion side, so that > > this explicit annotation can be more liberally sprinkled around. > > With read locks lockdep isn't going to complain if the read-side > > isn't nested the same way under all circumstances, so ABBA deadlocks > > are ok. Which they are, since this is an annotation only. > > > > - We're using non-recursive lockdep read lock mode, since in recursive > > read lock mode lockdep does not catch read side hazards. And we > > _very_ much want read side hazards to be caught. For full details of > > this limitation see > > > > commit e91498589746065e3ae95d9a00b068e525eec34f > > Author: Peter Zijlstra <peterz at infradead.org> > > Date: Wed Aug 23 13:13:11 2017 +0200 > > > > locking/lockdep/selftests: Add mixed read-write ABBA tests > > > > - To allow nesting of the read-side explicit annotations we explicitly > > keep track of the nesting. lock_is_held() allows us to do that. > > > > - The wait-side annotation is a write lock, and entirely done within > > dma_fence_wait() for everyone by default. > > > > - To be able to freely annotate helper functions I want to make it ok > > to call dma_fence_begin/end_signalling from soft/hardirq context. > > First attempt was using the hardirq locking context for the write > > side in lockdep, but this forces all normal spinlocks nested within > > dma_fence_begin/end_signalling to be spinlocks. That bollocks. > > > > The approach now is to simple check in_atomic(), and for these cases > > entirely rely on the might_sleep() check in dma_fence_wait(). That > > will catch any wrong nesting against spinlocks from soft/hardirq > > contexts. > > > > The idea here is that every code path that's critical for eventually > > signalling a dma_fence should be annotated with > > dma_fence_begin/end_signalling. The annotation ideally starts right > > after a dma_fence is published (added to a dma_resv, exposed as a > > sync_file fd, attached to a drm_syncobj fd, or anything else that > > makes the dma_fence visible to other kernel threads), up to and > > including the dma_fence_wait(). Examples are irq handlers, the > > scheduler rt threads, the tail of execbuf (after the corresponding > > fences are visible), any workers that end up signalling dma_fences and > > really anything else. Not annotated should be code paths that only > > complete fences opportunistically as the gpu progresses, like e.g. > > shrinker/eviction code. > > > > The main class of deadlocks this is supposed to catch are: > > > > Thread A: > > > > mutex_lock(A); > > mutex_unlock(A); > > > > dma_fence_signal(); > > > > Thread B: > > > > mutex_lock(A); > > dma_fence_wait(); > > mutex_unlock(A); > > > > Thread B is blocked on A signalling the fence, but A never gets around > > to that because it cannot acquire the lock A. > > > > Note that dma_fence_wait() is allowed to be nested within > > dma_fence_begin/end_signalling sections. To allow this to happen the > > read lock needs to be upgraded to a write lock, which means that any > > other lock is acquired between the dma_fence_begin_signalling() call and > > the call to dma_fence_wait(), and still held, this will result in an > > immediate lockdep complaint. The only other option would be to not > > annotate such calls, defeating the point. Therefore these annotations > > cannot be sprinkled over the code entirely mindless to avoid false > > positives. > > > > v2: handle soft/hardirq ctx better against write side and dont forget > > EXPORT_SYMBOL, drivers can't use this otherwise. > > > > v3: Kerneldoc. > > > > v4: Some spelling fixes from Mika > > > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > > Cc: linux-media at vger.kernel.org > > Cc: linaro-mm-sig at lists.linaro.org > > Cc: linux-rdma at vger.kernel.org > > Cc: amd-gfx at lists.freedesktop.org > > Cc: intel-gfx at lists.freedesktop.org > > Cc: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Introducing a global lockmap that cannot capture the rules correctly, Can you document the rules all drivers should be following then, because from here it looks to get refactored every version of i915, and it would be nice if we could all aim for the same set of things roughly. We've already had enough problems with amdgpu vs i915 vs everyone else with fences, if this stops that in the future then I'd rather we have that than just some unwritten rules per driver and untestable. Dave. From patchwork at emeril.freedesktop.org Thu Jun 11 08:46:16 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 08:46:16 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/dp=5Fmst=3A_Fix_the_DDC_I2C_dev?= =?utf-8?q?ice_unregistration_of_an_MST_port_=28rev2=29?= In-Reply-To: <20200607212522.16935-1-imre.deak@intel.com> References: <20200607212522.16935-1-imre.deak@intel.com> Message-ID: <159186517668.22716.10635471487472572534@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port (rev2) URL : https://patchwork.freedesktop.org/series/78100/ State : success == Summary == CI Bug Log - changes from CI_DRM_8608_full -> Patchwork_17919_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17919_full: ### Piglit changes ### #### Possible regressions #### * spec at glsl-4.20@execution at conversion@frag-conversion-implicit-mat4-dmat4-zero-sign (NEW): - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/pig-icl-1065g7/spec at glsl-4.20@execution at conversion@frag-conversion-implicit-mat4-dmat4-zero-sign.html * spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3-dmat3-zero-sign (NEW): - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/pig-icl-1065g7/spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3-dmat3-zero-sign.html New tests --------- New tests have been introduced between CI_DRM_8608_full and Patchwork_17919_full: ### New Piglit tests (6) ### * spec at glsl-4.00@execution at built-in-functions@gs-op-div-dmat4x3-dmat4x3: - Statuses : 1 crash(s) - Exec time: [98.33] s * spec at glsl-4.20@execution at conversion@frag-conversion-implicit-mat4-dmat4-zero-sign: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at glsl-4.20@execution at conversion@geom-conversion-implicit-mat3-dmat3-zero-sign: - Statuses : 1 crash(s) - Exec time: [15.54] s * spec at glsl-4.20@execution at conversion@geom-conversion-implicit-mat4-dmat4-zero-sign: - Statuses : 1 crash(s) - Exec time: [57.24] s * spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3-dmat3-zero-sign: - Statuses : 1 crash(s) - Exec time: [3.59] s * spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3x4-dmat3x4-zero-sign: - Statuses : 1 crash(s) - Exec time: [25.06] s Known issues ------------ Here are the changes found in Patchwork_17919_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_schedule@implicit-boths at bcs0: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-snb4/igt at gem_exec_schedule@implicit-boths at bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-snb2/igt at gem_exec_schedule@implicit-boths at bcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at gem_exec_suspend@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl2/igt at gem_exec_suspend@basic-s3.html * igt at gem_exec_whisper@basic-forked-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk4/igt at gem_exec_whisper@basic-forked-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk9/igt at gem_exec_whisper@basic-forked-all.html * igt at i915_suspend@sysfs-reader: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#69]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl2/igt at i915_suspend@sysfs-reader.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl6/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk2/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +16 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([i915#54] / [i915#95]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#1928]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +10 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl4/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl10/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb7/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb5/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-hsw: [PASS][37] -> [INCOMPLETE][38] ([i915#61]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-hsw6/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-hsw2/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at perf@blocking-parameterized: - shard-tglb: [PASS][39] -> [FAIL][40] ([i915#1542]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb3/igt at perf@blocking-parameterized.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb8/igt at perf@blocking-parameterized.html * igt at sw_sync@sync_multi_consumer: - shard-tglb: [PASS][41] -> [DMESG-WARN][42] ([i915#402]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb2/igt at sw_sync@sync_multi_consumer.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb1/igt at sw_sync@sync_multi_consumer.html #### Possible fixes #### * igt at gem_exec_create@madvise: - shard-glk: [DMESG-WARN][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk1/igt at gem_exec_create@madvise.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk7/igt at gem_exec_create@madvise.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][45] ([i915#1930]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_mmap_gtt@basic-small-copy-xy: - shard-iclb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb2/igt at gem_mmap_gtt@basic-small-copy-xy.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb5/igt at gem_mmap_gtt@basic-small-copy-xy.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][49] ([i915#1436] / [i915#716]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl10/igt at gen9_exec_parse@allowed-single.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl2/igt at gen9_exec_parse@allowed-single.html * igt at i915_suspend@fence-restore-untiled: - shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl1/igt at i915_suspend@fence-restore-untiled.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl7/igt at i915_suspend@fence-restore-untiled.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-kbl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html - shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk1/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk7/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-c-64x64-top-edge: - shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +3 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl1/igt at kms_cursor_edge_walk@pipe-c-64x64-top-edge.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl2/igt at kms_cursor_edge_walk@pipe-c-64x64-top-edge.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-apl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62] +3 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [INCOMPLETE][63] ([i915#123] / [i915#69]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl8/igt at kms_frontbuffer_tracking@psr-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl10/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb6/igt at kms_psr@psr2_cursor_plane_onoff.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html * igt at kms_setmode@basic: - shard-glk: [FAIL][69] ([i915#31]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk9/igt at kms_setmode@basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-query-busy-hang: - shard-tglb: [DMESG-WARN][71] ([i915#402]) -> [PASS][72] +2 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb2/igt at kms_vblank@pipe-c-query-busy-hang.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb1/igt at kms_vblank@pipe-c-query-busy-hang.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][73] ([i915#1542]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb4/igt at perf@blocking-parameterized.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb8/igt at perf@blocking-parameterized.html - shard-hsw: [FAIL][75] ([i915#1542]) -> [PASS][76] +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-hsw6/igt at perf@blocking-parameterized.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-hsw1/igt at perf@blocking-parameterized.html * igt at syncobj_wait@invalid-wait-illegal-handle: - shard-apl: [DMESG-WARN][77] ([i915#95]) -> [PASS][78] +10 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl2/igt at syncobj_wait@invalid-wait-illegal-handle.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl2/igt at syncobj_wait@invalid-wait-illegal-handle.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][79] ([i915#1930]) -> [TIMEOUT][80] ([i915#1958]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][81] ([i915#454]) -> [SKIP][82] ([i915#468]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb3/igt at i915_pm_dc@dc6-psr.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb2/igt at i915_pm_dc@dc6-psr.html - shard-skl: [DMESG-FAIL][83] ([i915#1982]) -> [FAIL][84] ([i915#454]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl8/igt at i915_pm_dc@dc6-psr.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl1/igt at i915_pm_dc@dc6-psr.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][85] ([i915#1515]) -> [WARN][86] ([i915#1515]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb8/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_big_fb@yf-tiled-addfb: - shard-snb: [SKIP][87] ([fdo#109271]) -> [TIMEOUT][88] ([i915#1958]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-snb2/igt at kms_big_fb@yf-tiled-addfb.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-snb6/igt at kms_big_fb@yf-tiled-addfb.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][89] ([i915#1319] / [i915#1635]) -> [FAIL][90] ([fdo#110321] / [fdo#110336]) +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl7/igt at kms_content_protection@atomic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [DMESG-FAIL][91] ([fdo#110321]) -> [TIMEOUT][92] ([i915#1319]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl2/igt at kms_content_protection@atomic-dpms.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl8/igt at kms_content_protection@atomic-dpms.html - shard-kbl: [TIMEOUT][93] ([i915#1319] / [i915#1958]) -> [TIMEOUT][94] ([i915#1319]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl4/igt at kms_content_protection@atomic-dpms.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_draw_crc@fill-fb: - shard-apl: [DMESG-WARN][95] ([i915#95]) -> [DMESG-FAIL][96] ([i915#95]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl6/igt at kms_draw_crc@fill-fb.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl2/igt at kms_draw_crc@fill-fb.html * igt at kms_sysfs_edid_timing: - shard-apl: [FAIL][97] ([IGT#2]) -> [DMESG-FAIL][98] ([IGT#2] / [i915#95]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl3/igt at kms_sysfs_edid_timing.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl7/igt at kms_sysfs_edid_timing.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8608 -> Patchwork_17919 CI-20190529: 20190529 CI_DRM_8608: e7b23e6cc4cdd7ad191bb039f803a2f13e4a0e40 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17919: ae88a71f3c396ee528050ee86509f65af8509303 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/index.html From daniel at fooishbar.org Thu Jun 11 09:01:46 2020 From: daniel at fooishbar.org (Daniel Stone) Date: Thu, 11 Jun 2020 10:01:46 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> Message-ID: <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> Hi, On Thu, 11 Jun 2020 at 09:44, Dave Airlie <airlied at gmail.com> wrote: > On Thu, 11 Jun 2020 at 18:01, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Introducing a global lockmap that cannot capture the rules correctly, > > Can you document the rules all drivers should be following then, > because from here it looks to get refactored every version of i915, > and it would be nice if we could all aim for the same set of things > roughly. We've already had enough problems with amdgpu vs i915 vs > everyone else with fences, if this stops that in the future then I'd > rather we have that than just some unwritten rules per driver and > untestable. As someone who has sunk a bunch of work into explicit-fencing awareness in my compositor so I can never be blocked, I'd be disappointed if the infrastructure was ultimately pointless because the documented fencing rules were \_o_/ or thereabouts. Lockdep definitely isn't my area of expertise so I can't comment on the patch per se, but having something to ensure we don't hit deadlocks sure seems a lot better than nothing. Cheers, Daniel From patchwork at emeril.freedesktop.org Thu Jun 11 09:06:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 09:06:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/6=5D_drm/i915/gt=3A_Move_hsw_GT_w?= =?utf-8?q?orkarounds_from_init=5Fclock=5Fgating_to_workarounds?= In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <159186638400.22713.13810420738799166127@emeril.freedesktop.org> == Series Details == Series: series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds URL : https://patchwork.freedesktop.org/series/78214/ State : warning == Summary == $ dim checkpatch origin/drm-tip d733ff00e147 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds e66a89d1b959 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds -:25: ERROR:SPACING: space required after that ',' (ctx:VxV) #25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:721: + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); ^ total: 1 errors, 0 warnings, 0 checks, 153 lines checked a5568a200839 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds -:25: ERROR:SPACING: space required after that ',' (ctx:VxV) #25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:781: + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); ^ total: 1 errors, 0 warnings, 0 checks, 161 lines checked 2bb63f1a6887 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds 04d5cd5657aa drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds -:24: ERROR:SPACING: space required after that ',' (ctx:VxV) #24: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:720: + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); ^ total: 1 errors, 0 warnings, 0 checks, 42 lines checked bb704549ca19 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds -:47: ERROR:SPACING: space required after that ',' (ctx:VxV) #47: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:739: + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); ^ total: 1 errors, 0 warnings, 0 checks, 76 lines checked From patchwork at emeril.freedesktop.org Thu Jun 11 09:07:36 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 09:07:36 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/6=5D_drm/i915/gt=3A_Move_hsw_GT_worka?= =?utf-8?q?rounds_from_init=5Fclock=5Fgating_to_workarounds?= In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <159186645697.22714.13594277616311442546@emeril.freedesktop.org> == Series Details == Series: series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds URL : https://patchwork.freedesktop.org/series/78214/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From mika.kuoppala at linux.intel.com Thu Jun 11 09:25:36 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 12:25:36 +0300 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <871rmm9cof.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rescue the GT workarounds from being buried inside init_clock_gating so > that we remember to apply them after a GT reset, and that they are > included in our verification that the workarounds are applied. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011 > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 +++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 39 +---------------- > 2 files changed, 50 insertions(+), 37 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 3eec31c5a714..39f070bff09d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) > wa_write_masked_or(wal, reg, set, set); > } > > +static void > +wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) > +{ > + wa_write_masked_or(wal, reg, clr, 0); > +} > + > static void > wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) > { > @@ -708,6 +714,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) > return 0; > } > > +static void > +hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + /* L3 caching of data atomics doesn't work -- disable it. */ > + wa_write_or(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); Just noted here is a change. We cleared everything else but this previously. -Mika > + > + wa_add(wal, > + HSW_ROW_CHICKEN3, 0, > + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), > + 0 /* XXX does this reg exist? */); > + > + /* WaVSRefCountFullforceMissDisable:hsw */ > + wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); > + > + wa_masked_dis(wal, > + CACHE_MODE_0_GEN7, > + /* WaDisable_RenderCache_OperationalFlush:hsw */ > + RC_OP_FLUSH_ENABLE | > + /* enable HiZ Raw Stall Optimization */ > + HIZ_RAW_STALL_OPT_DISABLE); > + > + /* WaDisable4x2SubspanOptimization:hsw */ > + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); > + > + /* > + * BSpec recommends 8x4 when MSAA is used, > + * however in practice 16x4 seems fastest. > + * > + * Note that PS/WM thread counts depend on the WIZ hashing > + * disable bit, which we don't touch here, but it's good > + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > + */ > + wa_add(wal, GEN7_GT_MODE, 0, > + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), > + GEN6_WIZ_HASHING_16x4); > + > + /* WaSampleCChickenBitEnable:hsw */ > + wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); > +} > + > static void > gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > @@ -985,6 +1031,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > bxt_gt_workarounds_init(i915, wal); > else if (IS_SKYLAKE(i915)) > skl_gt_workarounds_init(i915, wal); > + else if (IS_HASWELL(i915)) > + hsw_gt_workarounds_init(i915, wal); > else if (INTEL_GEN(i915) <= 8) > return; > else > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 26b670fa3f88..249ee720874c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7321,45 +7321,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) > > static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) > { > - /* L3 caching of data atomics doesn't work -- disable it. */ > - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); > - I915_WRITE(HSW_ROW_CHICKEN3, > - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); > - > /* This is required by WaCatErrorRejectionIssue:hsw */ > I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, > - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > - > - /* WaVSRefCountFullforceMissDisable:hsw */ > - I915_WRITE(GEN7_FF_THREAD_MODE, > - I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); > - > - /* WaDisable_RenderCache_OperationalFlush:hsw */ > - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > - > - /* enable HiZ Raw Stall Optimization */ > - I915_WRITE(CACHE_MODE_0_GEN7, > - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); > - > - /* WaDisable4x2SubspanOptimization:hsw */ > - I915_WRITE(CACHE_MODE_1, > - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > - > - /* > - * BSpec recommends 8x4 when MSAA is used, > - * however in practice 16x4 seems fastest. > - * > - * Note that PS/WM thread counts depend on the WIZ hashing > - * disable bit, which we don't touch here, but it's good > - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > - */ > - I915_WRITE(GEN7_GT_MODE, > - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); > - > - /* WaSampleCChickenBitEnable:hsw */ > - I915_WRITE(HALF_SLICE_CHICKEN3, > - _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); > + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > > /* WaSwitchSolVfFArbitrationPriority:hsw */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Thu Jun 11 09:28:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 09:28:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/6=5D_drm/i915/gt=3A_Move_hsw_GT_workarou?= =?utf-8?q?nds_from_init=5Fclock=5Fgating_to_workarounds?= In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <159186773340.22713.3308931494480360805@emeril.freedesktop.org> == Series Details == Series: series starting with [1/6] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds URL : https://patchwork.freedesktop.org/series/78214/ State : success == Summary == CI Bug Log - changes from CI_DRM_8614 -> Patchwork_17925 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17925: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at runner@aborted: - {fi-kbl-7560u}: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-7560u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17925 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-byt-j1900/igt at i915_module_load@reload.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-byt-j1900/igt at i915_module_load@reload.html - fi-icl-guc: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-guc/igt at i915_module_load@reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-icl-guc/igt at i915_module_load@reload.html - fi-icl-y: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-y/igt at i915_module_load@reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-icl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][14] -> [DMESG-WARN][15] ([i915#402]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-apl-guc: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-apl-guc/igt at i915_module_load@reload.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-apl-guc/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][18] ([i915#1982]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt at kms_busy@basic at flip.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][22] ([i915#1982]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][25] ([i915#62] / [i915#92]) +4 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-flip-vs-dpms at a-dp1: - fi-kbl-x1275: [DMESG-WARN][26] ([i915#62] / [i915#92]) -> [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8614 -> Patchwork_17925 CI-20190529: 20190529 CI_DRM_8614: 207862f18909166ffcf9e288ff796b756ae82d1c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17925: bb704549ca1937377b3595b79d74f18f875942c9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bb704549ca19 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds 04d5cd5657aa drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds 2bb63f1a6887 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds a5568a200839 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds e66a89d1b959 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds d733ff00e147 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17925/index.html From chris at chris-wilson.co.uk Thu Jun 11 09:30:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 10:30:15 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <20200611093015.11370-1-chris@chris-wilson.co.uk> Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied. v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable bit. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011 Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 39 +---------------- 2 files changed, 50 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3eec31c5a714..fb337e2d8a27 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) wa_write_masked_or(wal, reg, set, set); } +static void +wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) +{ + wa_write_masked_or(wal, reg, clr, 0); +} + static void wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) { @@ -708,6 +714,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) return 0; } +static void +hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + /* L3 caching of data atomics doesn't work -- disable it. */ + wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); + + wa_add(wal, + HSW_ROW_CHICKEN3, 0, + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), + 0 /* XXX does this reg exist? */); + + /* WaVSRefCountFullforceMissDisable:hsw */ + wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); + + wa_masked_dis(wal, + CACHE_MODE_0_GEN7, + /* WaDisable_RenderCache_OperationalFlush:hsw */ + RC_OP_FLUSH_ENABLE | + /* enable HiZ Raw Stall Optimization */ + HIZ_RAW_STALL_OPT_DISABLE); + + /* WaDisable4x2SubspanOptimization:hsw */ + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); + + /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + * + * Note that PS/WM thread counts depend on the WIZ hashing + * disable bit, which we don't touch here, but it's good + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). + */ + wa_add(wal, GEN7_GT_MODE, 0, + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), + GEN6_WIZ_HASHING_16x4); + + /* WaSampleCChickenBitEnable:hsw */ + wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); +} + static void gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) { @@ -985,6 +1031,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) bxt_gt_workarounds_init(i915, wal); else if (IS_SKYLAKE(i915)) skl_gt_workarounds_init(i915, wal); + else if (IS_HASWELL(i915)) + hsw_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 26b670fa3f88..249ee720874c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7321,45 +7321,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) { - /* L3 caching of data atomics doesn't work -- disable it. */ - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); - I915_WRITE(HSW_ROW_CHICKEN3, - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); - /* This is required by WaCatErrorRejectionIssue:hsw */ I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - - /* WaVSRefCountFullforceMissDisable:hsw */ - I915_WRITE(GEN7_FF_THREAD_MODE, - I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); - - /* WaDisable_RenderCache_OperationalFlush:hsw */ - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - - /* enable HiZ Raw Stall Optimization */ - I915_WRITE(CACHE_MODE_0_GEN7, - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); - - /* WaDisable4x2SubspanOptimization:hsw */ - I915_WRITE(CACHE_MODE_1, - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); - - /* - * BSpec recommends 8x4 when MSAA is used, - * however in practice 16x4 seems fastest. - * - * Note that PS/WM thread counts depend on the WIZ hashing - * disable bit, which we don't touch here, but it's good - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). - */ - I915_WRITE(GEN7_GT_MODE, - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); - - /* WaSampleCChickenBitEnable:hsw */ - I915_WRITE(HALF_SLICE_CHICKEN3, - _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); /* WaSwitchSolVfFArbitrationPriority:hsw */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); -- 2.20.1 From mika.kuoppala at linux.intel.com Thu Jun 11 09:52:41 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 12:52:41 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611093015.11370-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611093015.11370-1-chris@chris-wilson.co.uk> Message-ID: <87y2ou7wuu.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rescue the GT workarounds from being buried inside init_clock_gating so > that we remember to apply them after a GT reset, and that they are > included in our verification that the workarounds are applied. > > v2: Leave HSW_SCRATCH to set an explicit value, not or in our disable > bit. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2011 > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 +++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 39 +---------------- > 2 files changed, 50 insertions(+), 37 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 3eec31c5a714..fb337e2d8a27 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -178,6 +178,12 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) > wa_write_masked_or(wal, reg, set, set); > } > > +static void > +wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) > +{ > + wa_write_masked_or(wal, reg, clr, 0); > +} > + > static void > wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) > { > @@ -708,6 +714,46 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) > return 0; > } > > +static void > +hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + /* L3 caching of data atomics doesn't work -- disable it. */ > + wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); > + Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > + wa_add(wal, > + HSW_ROW_CHICKEN3, 0, > + _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), > + 0 /* XXX does this reg exist? */); > + > + /* WaVSRefCountFullforceMissDisable:hsw */ > + wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); > + > + wa_masked_dis(wal, > + CACHE_MODE_0_GEN7, > + /* WaDisable_RenderCache_OperationalFlush:hsw */ > + RC_OP_FLUSH_ENABLE | > + /* enable HiZ Raw Stall Optimization */ > + HIZ_RAW_STALL_OPT_DISABLE); > + > + /* WaDisable4x2SubspanOptimization:hsw */ > + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); > + > + /* > + * BSpec recommends 8x4 when MSAA is used, > + * however in practice 16x4 seems fastest. > + * > + * Note that PS/WM thread counts depend on the WIZ hashing > + * disable bit, which we don't touch here, but it's good > + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > + */ > + wa_add(wal, GEN7_GT_MODE, 0, > + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), > + GEN6_WIZ_HASHING_16x4); > + > + /* WaSampleCChickenBitEnable:hsw */ > + wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE); > +} > + > static void > gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > @@ -985,6 +1031,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > bxt_gt_workarounds_init(i915, wal); > else if (IS_SKYLAKE(i915)) > skl_gt_workarounds_init(i915, wal); > + else if (IS_HASWELL(i915)) > + hsw_gt_workarounds_init(i915, wal); > else if (INTEL_GEN(i915) <= 8) > return; > else > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 26b670fa3f88..249ee720874c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7321,45 +7321,10 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) > > static void hsw_init_clock_gating(struct drm_i915_private *dev_priv) > { > - /* L3 caching of data atomics doesn't work -- disable it. */ > - I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); > - I915_WRITE(HSW_ROW_CHICKEN3, > - _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); > - > /* This is required by WaCatErrorRejectionIssue:hsw */ > I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, > - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > - > - /* WaVSRefCountFullforceMissDisable:hsw */ > - I915_WRITE(GEN7_FF_THREAD_MODE, > - I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); > - > - /* WaDisable_RenderCache_OperationalFlush:hsw */ > - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > - > - /* enable HiZ Raw Stall Optimization */ > - I915_WRITE(CACHE_MODE_0_GEN7, > - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); > - > - /* WaDisable4x2SubspanOptimization:hsw */ > - I915_WRITE(CACHE_MODE_1, > - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > - > - /* > - * BSpec recommends 8x4 when MSAA is used, > - * however in practice 16x4 seems fastest. > - * > - * Note that PS/WM thread counts depend on the WIZ hashing > - * disable bit, which we don't touch here, but it's good > - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > - */ > - I915_WRITE(GEN7_GT_MODE, > - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); > - > - /* WaSampleCChickenBitEnable:hsw */ > - I915_WRITE(HALF_SLICE_CHICKEN3, > - _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); > + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > > /* WaSwitchSolVfFArbitrationPriority:hsw */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); > -- > 2.20.1 From patchwork at emeril.freedesktop.org Thu Jun 11 09:56:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 09:56:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_drm/i915/gt=3A_Move_hsw_GT_workarounds?= =?utf-8?q?_from_init=5Fclock=5Fgating_to_workarounds_=28rev2=29?= In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <159186941038.22715.323425954490373433@emeril.freedesktop.org> == Series Details == Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2) URL : https://patchwork.freedesktop.org/series/78214/ State : warning == Summary == $ dim checkpatch origin/drm-tip a9a19ef20e69 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds 961e1996e0a8 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds -:25: ERROR:SPACING: space required after that ',' (ctx:VxV) #25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:721: + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); ^ total: 1 errors, 0 warnings, 0 checks, 153 lines checked 68e40d9f98c3 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds -:25: ERROR:SPACING: space required after that ',' (ctx:VxV) #25: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:781: + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); ^ total: 1 errors, 0 warnings, 0 checks, 161 lines checked 79f6193f4ff2 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds 3dde510c6178 drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds -:24: ERROR:SPACING: space required after that ',' (ctx:VxV) #24: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:720: + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); ^ total: 1 errors, 0 warnings, 0 checks, 42 lines checked 66c89c81b814 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds -:47: ERROR:SPACING: space required after that ',' (ctx:VxV) #47: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:739: + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); ^ total: 1 errors, 0 warnings, 0 checks, 76 lines checked From maarten.lankhorst at linux.intel.com Thu Jun 11 09:57:06 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Thu, 11 Jun 2020 11:57:06 +0200 Subject: [Intel-gfx] [PATCH] dma-fence: basic lockdep annotations In-Reply-To: <20200605132953.899664-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-4-daniel.vetter@ffwll.ch> <20200605132953.899664-1-daniel.vetter@ffwll.ch> Message-ID: <2b514d05-bf44-645d-6335-81e140e64e57@linux.intel.com> Op 05-06-2020 om 15:29 schreef Daniel Vetter: > Design is similar to the lockdep annotations for workers, but with > some twists: > > - We use a read-lock for the execution/worker/completion side, so that > this explicit annotation can be more liberally sprinkled around. > With read locks lockdep isn't going to complain if the read-side > isn't nested the same way under all circumstances, so ABBA deadlocks > are ok. Which they are, since this is an annotation only. > > - We're using non-recursive lockdep read lock mode, since in recursive > read lock mode lockdep does not catch read side hazards. And we > _very_ much want read side hazards to be caught. For full details of > this limitation see > > commit e91498589746065e3ae95d9a00b068e525eec34f > Author: Peter Zijlstra <peterz at infradead.org> > Date: Wed Aug 23 13:13:11 2017 +0200 > > locking/lockdep/selftests: Add mixed read-write ABBA tests > > - To allow nesting of the read-side explicit annotations we explicitly > keep track of the nesting. lock_is_held() allows us to do that. > > - The wait-side annotation is a write lock, and entirely done within > dma_fence_wait() for everyone by default. > > - To be able to freely annotate helper functions I want to make it ok > to call dma_fence_begin/end_signalling from soft/hardirq context. > First attempt was using the hardirq locking context for the write > side in lockdep, but this forces all normal spinlocks nested within > dma_fence_begin/end_signalling to be spinlocks. That bollocks. > > The approach now is to simple check in_atomic(), and for these cases > entirely rely on the might_sleep() check in dma_fence_wait(). That > will catch any wrong nesting against spinlocks from soft/hardirq > contexts. > > The idea here is that every code path that's critical for eventually > signalling a dma_fence should be annotated with > dma_fence_begin/end_signalling. The annotation ideally starts right > after a dma_fence is published (added to a dma_resv, exposed as a > sync_file fd, attached to a drm_syncobj fd, or anything else that > makes the dma_fence visible to other kernel threads), up to and > including the dma_fence_wait(). Examples are irq handlers, the > scheduler rt threads, the tail of execbuf (after the corresponding > fences are visible), any workers that end up signalling dma_fences and > really anything else. Not annotated should be code paths that only > complete fences opportunistically as the gpu progresses, like e.g. > shrinker/eviction code. > > The main class of deadlocks this is supposed to catch are: > > Thread A: > > mutex_lock(A); > mutex_unlock(A); > > dma_fence_signal(); > > Thread B: > > mutex_lock(A); > dma_fence_wait(); > mutex_unlock(A); > > Thread B is blocked on A signalling the fence, but A never gets around > to that because it cannot acquire the lock A. > > Note that dma_fence_wait() is allowed to be nested within > dma_fence_begin/end_signalling sections. To allow this to happen the > read lock needs to be upgraded to a write lock, which means that any > other lock is acquired between the dma_fence_begin_signalling() call and > the call to dma_fence_wait(), and still held, this will result in an > immediate lockdep complaint. The only other option would be to not > annotate such calls, defeating the point. Therefore these annotations > cannot be sprinkled over the code entirely mindless to avoid false > positives. > > Originally I hope that the cross-release lockdep extensions would > alleviate the need for explicit annotations: > > https://lwn.net/Articles/709849/ > > But there's a few reasons why that's not an option: > > - It's not happening in upstream, since it got reverted due to too > many false positives: > > commit e966eaeeb623f09975ef362c2866fae6f86844f9 > Author: Ingo Molnar <mingo at kernel.org> > Date: Tue Dec 12 12:31:16 2017 +0100 > > locking/lockdep: Remove the cross-release locking checks > > This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), > while it found a number of old bugs initially, was also causing too many > false positives that caused people to disable lockdep - which is arguably > a worse overall outcome. > > - cross-release uses the complete() call to annotate the end of > critical sections, for dma_fence that would be dma_fence_signal(). > But we do not want all dma_fence_signal() calls to be treated as > critical, since many are opportunistic cleanup of gpu requests. If > these get stuck there's still the main completion interrupt and > workers who can unblock everyone. Automatically annotating all > dma_fence_signal() calls would hence cause false positives. > > - cross-release had some educated guesses for when a critical section > starts, like fresh syscall or fresh work callback. This would again > cause false positives without explicit annotations, since for > dma_fence the critical sections only starts when we publish a fence. > > - Furthermore there can be cases where a thread never does a > dma_fence_signal, but is still critical for reaching completion of > fences. One example would be a scheduler kthread which picks up jobs > and pushes them into hardware, where the interrupt handler or > another completion thread calls dma_fence_signal(). But if the > scheduler thread hangs, then all the fences hang, hence we need to > manually annotate it. cross-release aimed to solve this by chaining > cross-release dependencies, but the dependency from scheduler thread > to the completion interrupt handler goes through hw where > cross-release code can't observe it. > > In short, without manual annotations and careful review of the start > and end of critical sections, cross-relese dependency tracking doesn't > work. We need explicit annotations. > > v2: handle soft/hardirq ctx better against write side and dont forget > EXPORT_SYMBOL, drivers can't use this otherwise. > > v3: Kerneldoc. > > v4: Some spelling fixes from Mika > > v5: Amend commit message to explain in detail why cross-release isn't > the solution. > > Cc: Mika Kuoppala <mika.kuoppala at intel.com> > Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > Cc: linux-media at vger.kernel.org > Cc: linaro-mm-sig at lists.linaro.org > Cc: linux-rdma at vger.kernel.org > Cc: amd-gfx at lists.freedesktop.org > Cc: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > Documentation/driver-api/dma-buf.rst | 12 +- > drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ > include/linux/dma-fence.h | 12 ++ > 3 files changed, 182 insertions(+), 3 deletions(-) > > diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > index 63dec76d1d8d..05d856131140 100644 > --- a/Documentation/driver-api/dma-buf.rst > +++ b/Documentation/driver-api/dma-buf.rst > @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > .. kernel-doc:: drivers/dma-buf/dma-buf.c > :doc: cpu access > > -Fence Poll Support > -~~~~~~~~~~~~~~~~~~ > +Implicit Fence Poll Support > +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > - :doc: fence polling > + :doc: implicit fence polling > > Kernel Functions and Structures Reference > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > @@ -133,6 +133,12 @@ DMA Fences > .. kernel-doc:: drivers/dma-buf/dma-fence.c > :doc: DMA fences overview > > +DMA Fence Signalling Annotations > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +.. kernel-doc:: drivers/dma-buf/dma-fence.c > + :doc: fence signalling annotation > + > DMA Fences Functions Reference > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > index 656e9ac2d028..0005bc002529 100644 > --- a/drivers/dma-buf/dma-fence.c > +++ b/drivers/dma-buf/dma-fence.c > @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) > } > EXPORT_SYMBOL(dma_fence_context_alloc); > > +/** > + * DOC: fence signalling annotation > + * > + * Proving correctness of all the kernel code around &dma_fence through code > + * review and testing is tricky for a few reasons: > + * > + * * It is a cross-driver contract, and therefore all drivers must follow the > + * same rules for lock nesting order, calling contexts for various functions > + * and anything else significant for in-kernel interfaces. But it is also > + * impossible to test all drivers in a single machine, hence brute-force N vs. > + * N testing of all combinations is impossible. Even just limiting to the > + * possible combinations is infeasible. > + * > + * * There is an enormous amount of driver code involved. For render drivers > + * there's the tail of command submission, after fences are published, > + * scheduler code, interrupt and workers to process job completion, > + * and timeout, gpu reset and gpu hang recovery code. Plus for integration > + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, > + * and &shrinker. For modesetting drivers there's the commit tail functions > + * between when fences for an atomic modeset are published, and when the > + * corresponding vblank completes, including any interrupt processing and > + * related workers. Auditing all that code, across all drivers, is not > + * feasible. > + * > + * * Due to how many other subsystems are involved and the locking hierarchies > + * this pulls in there is extremely thin wiggle-room for driver-specific > + * differences. &dma_fence interacts with almost all of the core memory > + * handling through page fault handlers via &dma_resv, dma_resv_lock() and > + * dma_resv_unlock(). On the other side it also interacts through all > + * allocation sites through &mmu_notifier and &shrinker. > + * > + * Furthermore lockdep does not handle cross-release dependencies, which means > + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught > + * at runtime with some quick testing. The simplest example is one thread > + * waiting on a &dma_fence while holding a lock:: > + * > + * lock(A); > + * dma_fence_wait(B); > + * unlock(A); > + * > + * while the other thread is stuck trying to acquire the same lock, which > + * prevents it from signalling the fence the previous thread is stuck waiting > + * on:: > + * > + * lock(A); > + * unlock(A); > + * dma_fence_signal(B); > + * > + * By manually annotating all code relevant to signalling a &dma_fence we can > + * teach lockdep about these dependencies, which also helps with the validation > + * headache since now lockdep can check all the rules for us:: > + * > + * cookie = dma_fence_begin_signalling(); > + * lock(A); > + * unlock(A); > + * dma_fence_signal(B); > + * dma_fence_end_signalling(cookie); > + * > + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to > + * annotate critical sections the following rules need to be observed: > + * > + * * All code necessary to complete a &dma_fence must be annotated, from the > + * point where a fence is accessible to other threads, to the point where > + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, > + * and due to the very strict rules and many corner cases it is infeasible to > + * catch these just with review or normal stress testing. > + * > + * * &struct dma_resv deserves a special note, since the readers are only > + * protected by rcu. This means the signalling critical section starts as soon > + * as the new fences are installed, even before dma_resv_unlock() is called. > + * > + * * The only exception are fast paths and opportunistic signalling code, which > + * calls dma_fence_signal() purely as an optimization, but is not required to > + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL > + * which calls dma_fence_signal(), while the mandatory completion path goes > + * through a hardware interrupt and possible job completion worker. > + * > + * * To aid composability of code, the annotations can be freely nested, as long > + * as the overall locking hierarchy is consistent. The annotations also work > + * both in interrupt and process context. Due to implementation details this > + * requires that callers pass an opaque cookie from > + * dma_fence_begin_signalling() to dma_fence_end_signalling(). > + * > + * * Validation against the cross driver contract is implemented by priming > + * lockdep with the relevant hierarchy at boot-up. This means even just > + * testing with a single device is enough to validate a driver, at least as > + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are > + * concerned. > + */ > +#ifdef CONFIG_LOCKDEP > +struct lockdep_map dma_fence_lockdep_map = { > + .name = "dma_fence_map" > +}; > + > +/** > + * dma_fence_begin_signalling - begin a critical DMA fence signalling section > + * > + * Drivers should use this to annotate the beginning of any code section > + * required to eventually complete &dma_fence by calling dma_fence_signal(). > + * > + * The end of these critical sections are annotated with > + * dma_fence_end_signalling(). > + * > + * Returns: > + * > + * Opaque cookie needed by the implementation, which needs to be passed to > + * dma_fence_end_signalling(). > + */ > +bool dma_fence_begin_signalling(void) > +{ > + /* explicitly nesting ... */ > + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) > + return true; > + > + /* rely on might_sleep check for soft/hardirq locks */ > + if (in_atomic()) > + return true; > + > + /* ... and non-recursive readlock */ > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > + > + return false; > +} > +EXPORT_SYMBOL(dma_fence_begin_signalling); > + > +/** > + * dma_fence_end_signalling - end a critical DMA fence signalling section > + * > + * Closes a critical section annotation opened by dma_fence_begin_signalling(). > + */ > +void dma_fence_end_signalling(bool cookie) > +{ > + if (cookie) > + return; > + > + lock_release(&dma_fence_lockdep_map, _RET_IP_); > +} > +EXPORT_SYMBOL(dma_fence_end_signalling); > + > +void __dma_fence_might_wait(void) > +{ > + bool tmp; > + > + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); > + if (tmp) > + lock_release(&dma_fence_lockdep_map, _THIS_IP_); > + lock_map_acquire(&dma_fence_lockdep_map); > + lock_map_release(&dma_fence_lockdep_map); > + if (tmp) > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > +} > +#endif > + > + > /** > * dma_fence_signal_locked - signal completion of a fence > * @fence: the fence to signal > @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) > { > unsigned long flags; > int ret; > + bool tmp; > > if (!fence) > return -EINVAL; > > + tmp = dma_fence_begin_signalling(); > + > spin_lock_irqsave(fence->lock, flags); > ret = dma_fence_signal_locked(fence); > spin_unlock_irqrestore(fence->lock, flags); > > + dma_fence_end_signalling(tmp); > + > return ret; > } > EXPORT_SYMBOL(dma_fence_signal); > @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) > > might_sleep(); > > + __dma_fence_might_wait(); > + > trace_dma_fence_wait_start(fence); > if (fence->ops->wait) > ret = fence->ops->wait(fence, intr, timeout); > diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h > index 3347c54f3a87..3f288f7db2ef 100644 > --- a/include/linux/dma-fence.h > +++ b/include/linux/dma-fence.h > @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) > } while (1); > } > > +#ifdef CONFIG_LOCKDEP > +bool dma_fence_begin_signalling(void); > +void dma_fence_end_signalling(bool cookie); > +#else > +static inline bool dma_fence_begin_signalling(void) > +{ > + return true; > +} > +static inline void dma_fence_end_signalling(bool cookie) {} > +static inline void __dma_fence_might_wait(void) {} > +#endif > + > int dma_fence_signal(struct dma_fence *fence); > int dma_fence_signal_locked(struct dma_fence *fence); > signed long dma_fence_default_wait(struct dma_fence *fence, As original author of dma-fence, I enjoy seeing more lockdep annotations. Fence was always meant to be cross-driver, so strict driver annotations that can be verified by lockdep are a good thing. Because drivers have to interact with other drivers that use dma-fence, the rules must be the same for everyone, and the above code makes sense. Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> From patchwork at emeril.freedesktop.org Thu Jun 11 09:58:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 09:58:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_drm/i915/gt=3A_Move_hsw_GT_workarounds_fro?= =?utf-8?q?m_init=5Fclock=5Fgating_to_workarounds_=28rev2=29?= In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <159186948427.22713.13407466973206111969@emeril.freedesktop.org> == Series Details == Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2) URL : https://patchwork.freedesktop.org/series/78214/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From mika.kuoppala at linux.intel.com Thu Jun 11 09:59:19 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 12:59:19 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-2-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611080140.30228-2-chris@chris-wilson.co.uk> Message-ID: <87v9jx9b48.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rescue the GT workarounds from being buried inside init_clock_gating so > that we remember to apply them after a GT reset, and that they are > included in our verification that the workarounds are applied. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 +++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 48 ---------------- > 3 files changed, 63 insertions(+), 49 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 39f070bff09d..a5ba3ea8d45a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -714,6 +714,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) > return 0; > } > > +static void > +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + /* WaDisableEarlyCull:ivb */ > + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); > + > + /* WaDisablePSDDualDispatchEnable:ivb */ > + if (IS_IVB_GT1(i915)) > + wa_masked_en(wal, > + GEN7_HALF_SLICE_CHICKEN1, > + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); > + > + /* WaDisable_RenderCache_OperationalFlush:ivb */ > + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); > + > + /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ > + wa_masked_dis(wal, > + GEN7_COMMON_SLICE_CHICKEN1, > + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > + > + /* WaApplyL3ControlAndL3ChickenMode:ivb */ > + wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); > + wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); > + > + /* WaForceL3Serialization:ivb */ > + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); > + > + /* > + * WaVSThreadDispatchOverride:ivb,vlv > + * > + * This actually overrides the dispatch > + * mode for all thread types. > + */ > + wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, > + GEN7_FF_SCHED_MASK, > + GEN7_FF_TS_SCHED_HW | > + GEN7_FF_VS_SCHED_HW | > + GEN7_FF_DS_SCHED_HW); > + > + if (0) { /* causes HiZ corruption on ivb:gt1 */ > + /* enable HiZ Raw Stall Optimization */ > + wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > + } > + > + /* WaDisable4x2SubspanOptimization:ivb */ > + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); > + > + /* > + * BSpec recommends 8x4 when MSAA is used, > + * however in practice 16x4 seems fastest. > + * > + * Note that PS/WM thread counts depend on the WIZ hashing > + * disable bit, which we don't touch here, but it's good > + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > + */ > + wa_add(wal, GEN7_GT_MODE, 0, > + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), > + GEN6_WIZ_HASHING_16x4); > +} > + > static void > hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > @@ -1033,6 +1093,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > skl_gt_workarounds_init(i915, wal); > else if (IS_HASWELL(i915)) > hsw_gt_workarounds_init(i915, wal); > + else if (IS_IVYBRIDGE(i915)) > + ivb_gt_workarounds_init(i915, wal); > else if (INTEL_GEN(i915) <= 8) > return; > else > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9aca6d778220..19e1fed198c3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7924,7 +7924,7 @@ enum { > > /* GEN7 chicken */ > #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) > - #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) > + #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) I dont have bspec but evidence is overwhelming that this is masked reg. > #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) > > #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 249ee720874c..b835e5e97515 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7338,32 +7338,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) > > I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); > > - /* WaDisableEarlyCull:ivb */ > - I915_WRITE(_3D_CHICKEN3, > - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); > - > /* WaDisableBackToBackFlipFix:ivb */ > I915_WRITE(IVB_CHICKEN3, > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > - /* WaDisablePSDDualDispatchEnable:ivb */ > - if (IS_IVB_GT1(dev_priv)) > - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > - > - /* WaDisable_RenderCache_OperationalFlush:ivb */ > - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > - > - /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ > - I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > - GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > - > - /* WaApplyL3ControlAndL3ChickenMode:ivb */ > - I915_WRITE(GEN7_L3CNTLREG1, > - GEN7_WA_FOR_GEN7_L3_CONTROL); > - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, > - GEN7_WA_L3_CHICKEN_MODE); > if (IS_IVB_GT1(dev_priv)) > I915_WRITE(GEN7_ROW_CHICKEN2, > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > @@ -7375,10 +7354,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > } > > - /* WaForceL3Serialization:ivb */ > - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > - ~L3SQ_URB_READ_CAM_MATCH_DISABLE); > - > /* > * According to the spec, bit 13 (RCZUNIT) must be set on IVB. > * This implements the WaDisableRCZUnitClockGating:ivb workaround. > @@ -7393,29 +7368,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) > > g4x_disable_trickle_feed(dev_priv); > > - gen7_setup_fixed_func_scheduler(dev_priv); This just disappears without explanation. -Mika > - > - if (0) { /* causes HiZ corruption on ivb:gt1 */ > - /* enable HiZ Raw Stall Optimization */ > - I915_WRITE(CACHE_MODE_0_GEN7, > - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); > - } > - > - /* WaDisable4x2SubspanOptimization:ivb */ > - I915_WRITE(CACHE_MODE_1, > - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > - > - /* > - * BSpec recommends 8x4 when MSAA is used, > - * however in practice 16x4 seems fastest. > - * > - * Note that PS/WM thread counts depend on the WIZ hashing > - * disable bit, which we don't touch here, but it's good > - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > - */ > - I915_WRITE(GEN7_GT_MODE, > - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); > - > snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); > snpcr &= ~GEN6_MBC_SNPCR_MASK; > snpcr |= GEN6_MBC_SNPCR_MED; > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Thu Jun 11 10:00:47 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 13:00:47 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds In-Reply-To: <87v9jx9b48.fsf@gaia.fi.intel.com> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611080140.30228-2-chris@chris-wilson.co.uk> <87v9jx9b48.fsf@gaia.fi.intel.com> Message-ID: <87sgf19b1s.fsf@gaia.fi.intel.com> Mika Kuoppala <mika.kuoppala at linux.intel.com> writes: > Chris Wilson <chris at chris-wilson.co.uk> writes: > >> Rescue the GT workarounds from being buried inside init_clock_gating so >> that we remember to apply them after a GT reset, and that they are >> included in our verification that the workarounds are applied. >> >> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >> --- >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 +++++++++++++++++++++ >> drivers/gpu/drm/i915/i915_reg.h | 2 +- >> drivers/gpu/drm/i915/intel_pm.c | 48 ---------------- >> 3 files changed, 63 insertions(+), 49 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 39f070bff09d..a5ba3ea8d45a 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -714,6 +714,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) >> return 0; >> } >> >> +static void >> +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) >> +{ >> + /* WaDisableEarlyCull:ivb */ >> + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); >> + >> + /* WaDisablePSDDualDispatchEnable:ivb */ >> + if (IS_IVB_GT1(i915)) >> + wa_masked_en(wal, >> + GEN7_HALF_SLICE_CHICKEN1, >> + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); >> + >> + /* WaDisable_RenderCache_OperationalFlush:ivb */ >> + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); >> + >> + /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ >> + wa_masked_dis(wal, >> + GEN7_COMMON_SLICE_CHICKEN1, >> + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); >> + >> + /* WaApplyL3ControlAndL3ChickenMode:ivb */ >> + wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); >> + wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); >> + >> + /* WaForceL3Serialization:ivb */ >> + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); >> + >> + /* >> + * WaVSThreadDispatchOverride:ivb,vlv >> + * >> + * This actually overrides the dispatch >> + * mode for all thread types. >> + */ >> + wa_write_masked_or(wal, GEN7_FF_THREAD_MODE, >> + GEN7_FF_SCHED_MASK, >> + GEN7_FF_TS_SCHED_HW | >> + GEN7_FF_VS_SCHED_HW | >> + GEN7_FF_DS_SCHED_HW); >> + >> + if (0) { /* causes HiZ corruption on ivb:gt1 */ >> + /* enable HiZ Raw Stall Optimization */ >> + wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); >> + } >> + >> + /* WaDisable4x2SubspanOptimization:ivb */ >> + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); >> + >> + /* >> + * BSpec recommends 8x4 when MSAA is used, >> + * however in practice 16x4 seems fastest. >> + * >> + * Note that PS/WM thread counts depend on the WIZ hashing >> + * disable bit, which we don't touch here, but it's good >> + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). >> + */ >> + wa_add(wal, GEN7_GT_MODE, 0, >> + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), >> + GEN6_WIZ_HASHING_16x4); >> +} >> + >> static void >> hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) >> { >> @@ -1033,6 +1093,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) >> skl_gt_workarounds_init(i915, wal); >> else if (IS_HASWELL(i915)) >> hsw_gt_workarounds_init(i915, wal); >> + else if (IS_IVYBRIDGE(i915)) >> + ivb_gt_workarounds_init(i915, wal); >> else if (INTEL_GEN(i915) <= 8) >> return; >> else >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 9aca6d778220..19e1fed198c3 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -7924,7 +7924,7 @@ enum { >> >> /* GEN7 chicken */ >> #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) >> - #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) >> + #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) > > I dont have bspec but evidence is overwhelming that this is masked reg. > >> #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) >> >> #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index 249ee720874c..b835e5e97515 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -7338,32 +7338,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) >> >> I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); >> >> - /* WaDisableEarlyCull:ivb */ >> - I915_WRITE(_3D_CHICKEN3, >> - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); >> - >> /* WaDisableBackToBackFlipFix:ivb */ >> I915_WRITE(IVB_CHICKEN3, >> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | >> CHICKEN3_DGMG_DONE_FIX_DISABLE); >> >> - /* WaDisablePSDDualDispatchEnable:ivb */ >> - if (IS_IVB_GT1(dev_priv)) >> - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, >> - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); >> - >> - /* WaDisable_RenderCache_OperationalFlush:ivb */ >> - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); >> - >> - /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ >> - I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, >> - GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); >> - >> - /* WaApplyL3ControlAndL3ChickenMode:ivb */ >> - I915_WRITE(GEN7_L3CNTLREG1, >> - GEN7_WA_FOR_GEN7_L3_CONTROL); >> - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, >> - GEN7_WA_L3_CHICKEN_MODE); >> if (IS_IVB_GT1(dev_priv)) >> I915_WRITE(GEN7_ROW_CHICKEN2, >> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); >> @@ -7375,10 +7354,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) >> _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); >> } >> >> - /* WaForceL3Serialization:ivb */ >> - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & >> - ~L3SQ_URB_READ_CAM_MATCH_DISABLE); >> - >> /* >> * According to the spec, bit 13 (RCZUNIT) must be set on IVB. >> * This implements the WaDisableRCZUnitClockGating:ivb workaround. >> @@ -7393,29 +7368,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) >> >> g4x_disable_trickle_feed(dev_priv); >> >> - gen7_setup_fixed_func_scheduler(dev_priv); > > This just disappears without explanation. Oh there is explanation. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > -Mika > >> - >> - if (0) { /* causes HiZ corruption on ivb:gt1 */ >> - /* enable HiZ Raw Stall Optimization */ >> - I915_WRITE(CACHE_MODE_0_GEN7, >> - _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); >> - } >> - >> - /* WaDisable4x2SubspanOptimization:ivb */ >> - I915_WRITE(CACHE_MODE_1, >> - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); >> - >> - /* >> - * BSpec recommends 8x4 when MSAA is used, >> - * however in practice 16x4 seems fastest. >> - * >> - * Note that PS/WM thread counts depend on the WIZ hashing >> - * disable bit, which we don't touch here, but it's good >> - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). >> - */ >> - I915_WRITE(GEN7_GT_MODE, >> - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); >> - >> snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); >> snpcr &= ~GEN6_MBC_SNPCR_MASK; >> snpcr |= GEN6_MBC_SNPCR_MED; >> -- >> 2.20.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Thu Jun 11 10:02:54 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 13:02:54 +0300 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-3-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611080140.30228-3-chris@chris-wilson.co.uk> Message-ID: <87pna59ay9.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rescue the GT workarounds from being buried inside init_clock_gating so > that we remember to apply them after a GT reset, and that they are > included in our verification that the workarounds are applied. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 59 ++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 61 --------------------- > 2 files changed, 59 insertions(+), 61 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index a5ba3ea8d45a..688ca25d79d0 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -774,6 +774,63 @@ ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > GEN6_WIZ_HASHING_16x4); > } > > +static void > +vlv_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + /* WaDisableEarlyCull:vlv */ > + wa_masked_en(wal,_3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); > + > + /* WaPsdDispatchEnable:vlv */ > + /* WaDisablePSDDualDispatchEnable:vlv */ > + wa_masked_en(wal, > + GEN7_HALF_SLICE_CHICKEN1, > + GEN7_MAX_PS_THREAD_DEP | > + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); > + > + /* WaDisable_RenderCache_OperationalFlush:vlv */ > + wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); > + > + /* WaForceL3Serialization:vlv */ > + wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); > + > + /* > + * WaVSThreadDispatchOverride:ivb,vlv > + * > + * This actually overrides the dispatch > + * mode for all thread types. > + */ > + wa_write_masked_or(wal, > + GEN7_FF_THREAD_MODE, > + GEN7_FF_SCHED_MASK, > + GEN7_FF_TS_SCHED_HW | > + GEN7_FF_VS_SCHED_HW | > + GEN7_FF_DS_SCHED_HW); > + > + /* > + * BSpec says this must be set, even though > + * WaDisable4x2SubspanOptimization isn't listed for VLV. > + */ > + wa_masked_en(wal, CACHE_MODE_1, PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); > + > + /* > + * BSpec recommends 8x4 when MSAA is used, > + * however in practice 16x4 seems fastest. > + * > + * Note that PS/WM thread counts depend on the WIZ hashing > + * disable bit, which we don't touch here, but it's good > + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > + */ > + wa_add(wal, GEN7_GT_MODE, 0, > + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), > + GEN6_WIZ_HASHING_16x4); > + > + /* > + * WaIncreaseL3CreditsForVLVB0:vlv > + * This is the hardware default actually. > + */ > + wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); > +} > + > static void > hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > @@ -1093,6 +1150,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > skl_gt_workarounds_init(i915, wal); > else if (IS_HASWELL(i915)) > hsw_gt_workarounds_init(i915, wal); > + else if (IS_VALLEYVIEW(i915)) > + vlv_gt_workarounds_init(i915, wal); > else if (IS_IVYBRIDGE(i915)) > ivb_gt_workarounds_init(i915, wal); > else if (INTEL_GEN(i915) <= 8) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b835e5e97515..29abde47e987 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7077,24 +7077,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) > gen6_check_mch_setup(dev_priv); > } > > -static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) > -{ > - u32 reg = I915_READ(GEN7_FF_THREAD_MODE); > - > - /* > - * WaVSThreadDispatchOverride:ivb,vlv > - * > - * This actually overrides the dispatch > - * mode for all thread types. > - */ > - reg &= ~GEN7_FF_SCHED_MASK; > - reg |= GEN7_FF_TS_SCHED_HW; > - reg |= GEN7_FF_VS_SCHED_HW; > - reg |= GEN7_FF_DS_SCHED_HW; > - > - I915_WRITE(GEN7_FF_THREAD_MODE, reg); > -} > - > static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) > { > /* > @@ -7381,28 +7363,11 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv) > > static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) > { > - /* WaDisableEarlyCull:vlv */ > - I915_WRITE(_3D_CHICKEN3, > - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); > - > /* WaDisableBackToBackFlipFix:vlv */ > I915_WRITE(IVB_CHICKEN3, > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > - /* WaPsdDispatchEnable:vlv */ > - /* WaDisablePSDDualDispatchEnable:vlv */ > - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > - _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | > - GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > - > - /* WaDisable_RenderCache_OperationalFlush:vlv */ > - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > - > - /* WaForceL3Serialization:vlv */ > - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & > - ~L3SQ_URB_READ_CAM_MATCH_DISABLE); > - > /* WaDisableDopClockGating:vlv */ > I915_WRITE(GEN7_ROW_CHICKEN2, > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > @@ -7412,8 +7377,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) > I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > > - gen7_setup_fixed_func_scheduler(dev_priv); > - > /* > * According to the spec, bit 13 (RCZUNIT) must be set on IVB. > * This implements the WaDisableRCZUnitClockGating:vlv workaround. > @@ -7427,30 +7390,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) > I915_WRITE(GEN7_UCGCTL4, > I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > > - /* > - * BSpec says this must be set, even though > - * WaDisable4x2SubspanOptimization isn't listed for VLV. > - */ > - I915_WRITE(CACHE_MODE_1, > - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > - > - /* > - * BSpec recommends 8x4 when MSAA is used, > - * however in practice 16x4 seems fastest. > - * > - * Note that PS/WM thread counts depend on the WIZ hashing > - * disable bit, which we don't touch here, but it's good > - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > - */ > - I915_WRITE(GEN7_GT_MODE, > - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); > - > - /* > - * WaIncreaseL3CreditsForVLVB0:vlv > - * This is the hardware default actually. > - */ > - I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); > - > /* > * WaDisableVLVClockGating_VBIIssue:vlv > * Disable clock gating on th GCFG unit to prevent a delay > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Thu Jun 11 10:04:22 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 13:04:22 +0300 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-4-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611080140.30228-4-chris@chris-wilson.co.uk> Message-ID: <87mu599avt.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rescue the GT workarounds from being buried inside init_clock_gating so > that we remember to apply them after a GT reset, and that they are > included in our verification that the workarounds are applied. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 41 +++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 33 ----------------- > 2 files changed, 41 insertions(+), 33 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 688ca25d79d0..7b4f3434eb6b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -714,6 +714,45 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) > return 0; > } > > +static void > +snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ > + wa_masked_en(wal, > + _3D_CHICKEN, > + _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB); > + > + /* WaDisable_RenderCache_OperationalFlush:snb */ > + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); > + > + /* > + * BSpec recoomends 8x4 when MSAA is used, recommends. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > + * however in practice 16x4 seems fastest. > + * > + * Note that PS/WM thread counts depend on the WIZ hashing > + * disable bit, which we don't touch here, but it's good > + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > + */ > + wa_add(wal, > + GEN6_GT_MODE, 0, > + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), > + GEN6_WIZ_HASHING_16x4); > + > + wa_masked_dis(wal, CACHE_MODE_0, CM0_STC_EVICT_DISABLE_LRA_SNB); > + > + wa_masked_en(wal, > + _3D_CHICKEN3, > + /* WaStripsFansDisableFastClipPerformanceFix:snb */ > + _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL | > + /* > + * Bspec says: > + * "This bit must be set if 3DSTATE_CLIP clip mode is set > + * to normal and 3DSTATE_SF number of SF output attributes > + * is more than 16." > + */ > + _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH); > +} > + > static void > ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > @@ -1154,6 +1193,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > vlv_gt_workarounds_init(i915, wal); > else if (IS_IVYBRIDGE(i915)) > ivb_gt_workarounds_init(i915, wal); > + else if (IS_GEN(i915, 6)) > + snb_gt_workarounds_init(i915, wal); > else if (INTEL_GEN(i915) <= 8) > return; > else > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 29abde47e987..b4bea6451418 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6993,27 +6993,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) > I915_READ(ILK_DISPLAY_CHICKEN2) | > ILK_ELPIN_409_SELECT); > > - /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ > - I915_WRITE(_3D_CHICKEN, > - _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); > - > - /* WaDisable_RenderCache_OperationalFlush:snb */ > - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > - > - /* > - * BSpec recoomends 8x4 when MSAA is used, > - * however in practice 16x4 seems fastest. > - * > - * Note that PS/WM thread counts depend on the WIZ hashing > - * disable bit, which we don't touch here, but it's good > - * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > - */ > - I915_WRITE(GEN6_GT_MODE, > - _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); > - > - I915_WRITE(CACHE_MODE_0, > - _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > - > I915_WRITE(GEN6_UCGCTL1, > I915_READ(GEN6_UCGCTL1) | > GEN6_BLBUNIT_CLOCK_GATE_DISABLE | > @@ -7036,18 +7015,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) > GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | > GEN6_RCCUNIT_CLOCK_GATE_DISABLE); > > - /* WaStripsFansDisableFastClipPerformanceFix:snb */ > - I915_WRITE(_3D_CHICKEN3, > - _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); > - > - /* > - * Bspec says: > - * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and > - * 3DSTATE_SF number of SF output attributes is more than 16." > - */ > - I915_WRITE(_3D_CHICKEN3, > - _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); > - > /* > * According to the spec the following bits should be > * set in order to enable memory self-refresh and fbc: > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Thu Jun 11 10:05:03 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 13:05:03 +0300 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-5-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611080140.30228-5-chris@chris-wilson.co.uk> Message-ID: <87k10d9auo.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rescue the GT workarounds from being buried inside init_clock_gating so > that we remember to apply them after a GT reset, and that they are > included in our verification that the workarounds are applied. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 10 ---------- > 2 files changed, 14 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 7b4f3434eb6b..f8b9e104378e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -714,6 +714,18 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) > return 0; > } > > +static void > +ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); > + > + /* WaDisableRenderCachePipelinedFlush:ilk */ > + wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); > + > + /* WaDisable_RenderCache_OperationalFlush:ilk */ > + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); > +} > + > static void > snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > @@ -1195,6 +1207,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > ivb_gt_workarounds_init(i915, wal); > else if (IS_GEN(i915, 6)) > snb_gt_workarounds_init(i915, wal); > + else if (IS_GEN(i915, 5)) > + ilk_gt_workarounds_init(i915, wal); > else if (INTEL_GEN(i915) <= 8) > return; > else > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b4bea6451418..7d82a7144a13 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6921,16 +6921,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv) > I915_WRITE(ILK_DISPLAY_CHICKEN2, > I915_READ(ILK_DISPLAY_CHICKEN2) | > ILK_ELPIN_409_SELECT); > - I915_WRITE(_3D_CHICKEN2, > - _3D_CHICKEN2_WM_READ_PIPELINED << 16 | > - _3D_CHICKEN2_WM_READ_PIPELINED); > - > - /* WaDisableRenderCachePipelinedFlush:ilk */ > - I915_WRITE(CACHE_MODE_0, > - _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); > - > - /* WaDisable_RenderCache_OperationalFlush:ilk */ > - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > > g4x_disable_trickle_feed(dev_priv); > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Thu Jun 11 10:07:30 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 11 Jun 2020 13:07:30 +0300 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-6-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611080140.30228-6-chris@chris-wilson.co.uk> Message-ID: <87h7vh9aql.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rescue the GT workarounds from being buried inside init_clock_gating so > that we remember to apply them after a GT reset, and that they are > included in our verification that the workarounds are applied. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 +++++++++++++++++---- > drivers/gpu/drm/i915/intel_pm.c | 15 ------------ > 2 files changed, 22 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index f8b9e104378e..7b4be64585c3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -715,15 +715,28 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq) > } > > static void > -ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +gen4_gt_workarounds_init(struct drm_i915_private *i915, > + struct i915_wa_list *wal) > { > - wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); > + /* WaDisable_RenderCache_OperationalFlush:gen4,ilk */ > + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); > +} > + > +static void > +g4x_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + gen4_gt_workarounds_init(i915, wal); > > - /* WaDisableRenderCachePipelinedFlush:ilk */ > + /* WaDisableRenderCachePipelinedFlush:g4x,ilk */ > wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); > +} > > - /* WaDisable_RenderCache_OperationalFlush:ilk */ > - wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); > +static void > +ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + g4x_gt_workarounds_init(i915, wal); > + > + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); > } > > static void > @@ -1209,6 +1222,10 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > snb_gt_workarounds_init(i915, wal); > else if (IS_GEN(i915, 5)) > ilk_gt_workarounds_init(i915, wal); > + else if (IS_G4X(i915)) > + g4x_gt_workarounds_init(i915, wal); > + else if (IS_GEN(i915, 4)) > + gen4_gt_workarounds_init(i915, wal); > else if (INTEL_GEN(i915) <= 8) > return; > else > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 7d82a7144a13..2a32d6230795 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7399,13 +7399,6 @@ static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) > dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; > I915_WRITE(DSPCLK_GATE_D, dspclk_gate); > > - /* WaDisableRenderCachePipelinedFlush */ > - I915_WRITE(CACHE_MODE_0, > - _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); > - > - /* WaDisable_RenderCache_OperationalFlush:g4x */ > - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > - > g4x_disable_trickle_feed(dev_priv); > } > > @@ -7421,11 +7414,6 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv) > intel_uncore_write(uncore, > MI_ARB_STATE, > _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); > - > - /* WaDisable_RenderCache_OperationalFlush:gen4 */ > - intel_uncore_write(uncore, > - CACHE_MODE_0, > - _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > } > > static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) > @@ -7438,9 +7426,6 @@ static void i965g_init_clock_gating(struct drm_i915_private *dev_priv) > I915_WRITE(RENCLK_GATE_D2, 0); > I915_WRITE(MI_ARB_STATE, > _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); > - > - /* WaDisable_RenderCache_OperationalFlush:gen4 */ > - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); > } > > static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Thu Jun 11 10:21:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 10:21:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_drm/i915/gt=3A_Move_hsw_GT_workarounds_from_i?= =?utf-8?q?nit=5Fclock=5Fgating_to_workarounds_=28rev2=29?= In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <159187088804.22713.17597018796328773559@emeril.freedesktop.org> == Series Details == Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2) URL : https://patchwork.freedesktop.org/series/78214/ State : success == Summary == CI Bug Log - changes from CI_DRM_8614 -> Patchwork_17926 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17926: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at runner@aborted: - {fi-kbl-7560u}: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-7560u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17926 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [PASS][6] -> [INCOMPLETE][7] ([i915#1932]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-apl-guc: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-apl-guc/igt at i915_module_load@reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-apl-guc/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][16] ([i915#1233]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt at kms_busy@basic at flip.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][20] ([i915#1982]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][22] ([i915#1982]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][24] ([i915#1982]) -> [PASS][25] +1 similar issue [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][26] ([i915#62] / [i915#92]) -> [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][29] ([i915#62] / [i915#92]) +5 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-kbl-7560u Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8614 -> Patchwork_17926 CI-20190529: 20190529 CI_DRM_8614: 207862f18909166ffcf9e288ff796b756ae82d1c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17926: 66c89c81b8144175aa4d9682e650323658fddcce @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 66c89c81b814 drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds 3dde510c6178 drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds 79f6193f4ff2 drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds 68e40d9f98c3 drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds 961e1996e0a8 drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds a9a19ef20e69 drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/index.html From patchwork at emeril.freedesktop.org Thu Jun 11 10:26:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 10:26:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Include_context_status_in_debug_dumps?= In-Reply-To: <20200610154046.22449-1-chris@chris-wilson.co.uk> References: <20200610154046.22449-1-chris@chris-wilson.co.uk> Message-ID: <159187119283.22716.18377168530772778031@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Include context status in debug dumps URL : https://patchwork.freedesktop.org/series/78188/ State : success == Summary == CI Bug Log - changes from CI_DRM_8610_full -> Patchwork_17920_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17920_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-wc-cpu-active: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +7 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl8/igt at gem_exec_reloc@basic-wc-cpu-active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl1/igt at gem_exec_reloc@basic-wc-cpu-active.html * igt at gen9_exec_parse@allowed-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#1436] / [i915#716]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-glk1/igt at gen9_exec_parse@allowed-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-glk7/igt at gen9_exec_parse@allowed-all.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +16 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-skl6/igt at kms_color@pipe-c-ctm-0-25.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-skl4/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-kbl4/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-kbl2/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html * igt at kms_flip@flip-vs-suspend at b-dp1: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-kbl3/igt at kms_flip@flip-vs-suspend at b-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-kbl4/igt at kms_flip@flip-vs-suspend at b-dp1.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-iclb3/igt at kms_psr@psr2_sprite_blt.html * igt at kms_setmode@basic: - shard-apl: [PASS][19] -> [FAIL][20] ([i915#31]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl7/igt at kms_setmode@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl4/igt at kms_vblank@pipe-b-ts-continuation-suspend.html #### Possible fixes #### * igt at gem_ctx_persistence@processes: - shard-skl: [FAIL][23] ([i915#1528]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-skl3/igt at gem_ctx_persistence@processes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-skl7/igt at gem_ctx_persistence@processes.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [DMESG-WARN][25] ([i915#180]) -> [PASS][26] +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-kbl7/igt at i915_suspend@debugfs-reader.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-kbl6/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-skl: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] +5 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-skl9/igt at kms_big_fb@linear-32bpp-rotate-180.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-skl5/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@linear-8bpp-rotate-180: - shard-kbl: [DMESG-WARN][29] ([i915#1982]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-kbl1/igt at kms_big_fb@linear-8bpp-rotate-180.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-kbl6/igt at kms_big_fb@linear-8bpp-rotate-180.html * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: - shard-tglb: [DMESG-WARN][31] ([i915#402]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-tglb3/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-tglb2/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-apl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl6/igt at kms_flip@flip-vs-suspend at c-dp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl8/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [FAIL][35] ([i915#1928]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [DMESG-WARN][37] ([i915#95]) -> [PASS][38] +6 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][39] ([i915#1188]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-iclb1/igt at kms_psr@psr2_cursor_plane_onoff.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][43] ([i915#1542]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-iclb1/igt at perf@blocking-parameterized.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-iclb2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][45] ([i915#588]) -> [SKIP][46] ([i915#658]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-iclb7/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][47] ([i915#1899]) -> [SKIP][48] ([i915#468]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-tglb3/igt at i915_pm_dc@dc6-psr.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][49] ([i915#1515]) -> [WARN][50] ([i915#1515]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-iclb6/igt at i915_pm_rc6_residency@rc6-idle.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-iclb1/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][51] ([i915#1319]) -> [TIMEOUT][52] ([i915#1319] / [i915#1635]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl4/igt at kms_content_protection@lic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][53] ([fdo#110321] / [i915#95]) -> [TIMEOUT][54] ([i915#1319]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-kbl2/igt at kms_content_protection@srm.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-kbl3/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][55] ([fdo#110321] / [i915#95]) -> [TIMEOUT][56] ([i915#1319]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl6/igt at kms_content_protection@srm.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl8/igt at kms_content_protection@srm.html * igt at kms_flip_tiling@flip-changes-tiling-yf: - shard-kbl: [DMESG-FAIL][57] ([i915#95]) -> [DMESG-WARN][58] ([i915#93] / [i915#95]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-kbl6/igt at kms_flip_tiling@flip-changes-tiling-yf.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling-yf.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [INCOMPLETE][59] ([i915#155]) -> [DMESG-WARN][60] ([i915#180]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-kbl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][62] ([fdo#108145] / [i915#95]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-apl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-apl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [DMESG-WARN][63] ([i915#1982]) -> [FAIL][64] ([fdo#108145] / [i915#265]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8610/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8610 -> Patchwork_17920 CI-20190529: 20190529 CI_DRM_8610: 5a778c71b283ff1a2af242f02e602c11b9490e3a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17920: af201da28116f5b1b2ce11c9db8b5ebd1343dcd6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17920/index.html From imre.deak at intel.com Thu Jun 11 10:33:08 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 11 Jun 2020 13:33:08 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/icl=3A_Disable_DIP_on_MST_ports_with_the_transcoder_clock?= =?utf-8?q?_still_on?= In-Reply-To: <159174697260.17060.16481357416186052848@emeril.freedesktop.org> References: <20200609220616.6015-1-imre.deak@intel.com> <159174697260.17060.16481357416186052848@emeril.freedesktop.org> Message-ID: <20200611103308.GB17512@ideak-desk.fi.intel.com> On Tue, Jun 09, 2020 at 11:56:12PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on > URL : https://patchwork.freedesktop.org/series/78172/ > State : success Thanks for the review, pushed to -dinq. > > == Summary == > > CI Bug Log - changes from CI_DRM_8604_full -> Patchwork_17917_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17917_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_create@madvise: > - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk6/igt at gem_exec_create@madvise.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk4/igt at gem_exec_create@madvise.html > > * igt at gem_exec_whisper@basic-normal: > - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +3 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at gem_exec_whisper@basic-normal.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at gem_exec_whisper@basic-normal.html > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#118] / [i915#95]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html > > * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: > - shard-kbl: [PASS][7] -> [DMESG-FAIL][8] ([i915#54] / [i915#95]) +1 similar issue > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > > * igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding: > - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl10/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-256x256-sliding.html > > * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: > - shard-kbl: [PASS][11] -> [DMESG-FAIL][12] ([i915#95]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html > > * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled: > - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +7 similar issues > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl10/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html > > * igt at kms_flip@flip-vs-suspend at a-dp1: > - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at kms_flip@flip-vs-suspend at a-dp1.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl4/igt at kms_flip@flip-vs-suspend at a-dp1.html > > * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: > - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1928]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc: > - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc.html > > * igt at kms_hdr@bpc-switch: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_hdr@bpc-switch.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl1/igt at kms_hdr@bpc-switch.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_psr2_su@frontbuffer: > - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109642] / [fdo#111068]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr2_su@frontbuffer.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb7/igt at kms_psr2_su@frontbuffer.html > > * igt at kms_psr@psr2_primary_mmap_gtt: > - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb6/igt at kms_psr@psr2_primary_mmap_gtt.html > > * igt at kms_setmode@basic: > - shard-skl: [PASS][29] -> [FAIL][30] ([i915#31]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_setmode@basic.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl8/igt at kms_setmode@basic.html > > * igt at kms_vblank@pipe-a-ts-continuation-idle-hang: > - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_vblank@pipe-a-ts-continuation-idle-hang.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl2/igt at kms_vblank@pipe-a-ts-continuation-idle-hang.html > > * igt at kms_vblank@pipe-a-ts-continuation-suspend: > - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#180]) +6 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > > * igt at perf@blocking-parameterized: > - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#1542]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb8/igt at perf@blocking-parameterized.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb7/igt at perf@blocking-parameterized.html > > * igt at syncobj_wait@invalid-wait-illegal-handle: > - shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#95]) +17 similar issues > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at syncobj_wait@invalid-wait-illegal-handle.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl8/igt at syncobj_wait@invalid-wait-illegal-handle.html > > > #### Possible fixes #### > > * igt at drm_read@short-buffer-block: > - shard-kbl: [DMESG-WARN][39] ([i915#93] / [i915#95]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at drm_read@short-buffer-block.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at drm_read@short-buffer-block.html > > * igt at gem_ctx_shared@q-independent at bcs0: > - shard-apl: [FAIL][41] ([i915#2013]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at gem_ctx_shared@q-independent at bcs0.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl2/igt at gem_ctx_shared@q-independent at bcs0.html > > * igt at gem_workarounds@suspend-resume: > - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl7/igt at gem_workarounds@suspend-resume.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at gem_workarounds@suspend-resume.html > > * igt at kms_big_fb@x-tiled-64bpp-rotate-180: > - shard-glk: [DMESG-FAIL][45] ([i915#118] / [i915#95]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk7/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: > - shard-glk: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk9/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-glk4/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > > * igt at kms_color@pipe-a-ctm-0-5: > - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +3 similar issues > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_color@pipe-a-ctm-0-5.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl6/igt at kms_color@pipe-a-ctm-0-5.html > > * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: > - shard-apl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * igt at kms_flip@flip-vs-suspend at a-edp1: > - shard-skl: [INCOMPLETE][53] ([i915#198]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_flip@flip-vs-suspend at a-edp1.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html > > * igt at kms_flip_tiling@flip-changes-tiling: > - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl3/igt at kms_flip_tiling@flip-changes-tiling.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu: > - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-tglb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html > > * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > > * igt at kms_psr@psr2_primary_page_flip: > - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb1/igt at kms_psr@psr2_primary_page_flip.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html > > * igt at sw_sync@sync_merge_same: > - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [PASS][64] +17 similar issues > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at sw_sync@sync_merge_same.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl3/igt at sw_sync@sync_merge_same.html > > > #### Warnings #### > > * igt at gem_exec_reloc@basic-concurrent16: > - shard-apl: [INCOMPLETE][65] ([i915#1635] / [i915#1958]) -> [TIMEOUT][66] ([i915#1635]) > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at gem_exec_reloc@basic-concurrent16.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl1/igt at gem_exec_reloc@basic-concurrent16.html > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][67] ([i915#588]) -> [SKIP][68] ([i915#658]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at kms_content_protection@atomic: > - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_content_protection@atomic.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl3/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@legacy: > - shard-apl: [TIMEOUT][71] ([i915#1319] / [i915#1635]) -> [FAIL][72] ([fdo#110321] / [fdo#110336]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at kms_content_protection@legacy.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl4/igt at kms_content_protection@legacy.html > > * igt at kms_content_protection@lic: > - shard-kbl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1958]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl7/igt at kms_content_protection@lic.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl4/igt at kms_content_protection@lic.html > > * igt at kms_draw_crc@fill-fb: > - shard-apl: [DMESG-WARN][75] ([i915#95]) -> [DMESG-FAIL][76] ([i915#95]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at kms_draw_crc@fill-fb.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-apl8/igt at kms_draw_crc@fill-fb.html > > * igt at kms_fbcon_fbt@fbc: > - shard-kbl: [FAIL][77] ([i915#64]) -> [DMESG-FAIL][78] ([i915#95]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl6/igt at kms_fbcon_fbt@fbc.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-kbl2/igt at kms_fbcon_fbt@fbc.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [DMESG-FAIL][79] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][80] ([i915#1982]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2013]: https://gitlab.freedesktop.org/drm/intel/issues/2013 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8604 -> Patchwork_17917 > > CI-20190529: 20190529 > CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17917: 28cda6a9ac5e59753727007e79807876b33d43ac @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17917/index.html From tvrtko.ursulin at linux.intel.com Thu Jun 11 10:36:26 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 11 Jun 2020 11:36:26 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <CAKMK7uE4ak=gaKNJziaLg1qN1mE1FKLW1MGFkmUz2tR2y0ArAA@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <be3526aa-07db-adc0-9291-1b5aeb0d1613@linux.intel.com> <CAKMK7uE4ak=gaKNJziaLg1qN1mE1FKLW1MGFkmUz2tR2y0ArAA@mail.gmail.com> Message-ID: <19c6fe47-50ff-869e-d3f0-703b8165d577@linux.intel.com> On 10/06/2020 16:17, Daniel Vetter wrote: > On Wed, Jun 10, 2020 at 4:22 PM Tvrtko Ursulin > <tvrtko.ursulin at linux.intel.com> wrote: >> >> >> On 04/06/2020 09:12, Daniel Vetter wrote: >>> Design is similar to the lockdep annotations for workers, but with >>> some twists: >>> >>> - We use a read-lock for the execution/worker/completion side, so that >>> this explicit annotation can be more liberally sprinkled around. >>> With read locks lockdep isn't going to complain if the read-side >>> isn't nested the same way under all circumstances, so ABBA deadlocks >>> are ok. Which they are, since this is an annotation only. >>> >>> - We're using non-recursive lockdep read lock mode, since in recursive >>> read lock mode lockdep does not catch read side hazards. And we >>> _very_ much want read side hazards to be caught. For full details of >>> this limitation see >>> >>> commit e91498589746065e3ae95d9a00b068e525eec34f >>> Author: Peter Zijlstra <peterz at infradead.org> >>> Date: Wed Aug 23 13:13:11 2017 +0200 >>> >>> locking/lockdep/selftests: Add mixed read-write ABBA tests >>> >>> - To allow nesting of the read-side explicit annotations we explicitly >>> keep track of the nesting. lock_is_held() allows us to do that. >>> >>> - The wait-side annotation is a write lock, and entirely done within >>> dma_fence_wait() for everyone by default. >>> >>> - To be able to freely annotate helper functions I want to make it ok >>> to call dma_fence_begin/end_signalling from soft/hardirq context. >>> First attempt was using the hardirq locking context for the write >>> side in lockdep, but this forces all normal spinlocks nested within >>> dma_fence_begin/end_signalling to be spinlocks. That bollocks. >>> >>> The approach now is to simple check in_atomic(), and for these cases >>> entirely rely on the might_sleep() check in dma_fence_wait(). That >>> will catch any wrong nesting against spinlocks from soft/hardirq >>> contexts. >>> >>> The idea here is that every code path that's critical for eventually >>> signalling a dma_fence should be annotated with >>> dma_fence_begin/end_signalling. The annotation ideally starts right >>> after a dma_fence is published (added to a dma_resv, exposed as a >>> sync_file fd, attached to a drm_syncobj fd, or anything else that >>> makes the dma_fence visible to other kernel threads), up to and >>> including the dma_fence_wait(). Examples are irq handlers, the >>> scheduler rt threads, the tail of execbuf (after the corresponding >>> fences are visible), any workers that end up signalling dma_fences and >>> really anything else. Not annotated should be code paths that only >>> complete fences opportunistically as the gpu progresses, like e.g. >>> shrinker/eviction code. >>> >>> The main class of deadlocks this is supposed to catch are: >>> >>> Thread A: >>> >>> mutex_lock(A); >>> mutex_unlock(A); >>> >>> dma_fence_signal(); >>> >>> Thread B: >>> >>> mutex_lock(A); >>> dma_fence_wait(); >>> mutex_unlock(A); >>> >>> Thread B is blocked on A signalling the fence, but A never gets around >>> to that because it cannot acquire the lock A. >>> >>> Note that dma_fence_wait() is allowed to be nested within >>> dma_fence_begin/end_signalling sections. To allow this to happen the >>> read lock needs to be upgraded to a write lock, which means that any >>> other lock is acquired between the dma_fence_begin_signalling() call and >>> the call to dma_fence_wait(), and still held, this will result in an >>> immediate lockdep complaint. The only other option would be to not >>> annotate such calls, defeating the point. Therefore these annotations >>> cannot be sprinkled over the code entirely mindless to avoid false >>> positives. >>> >>> v2: handle soft/hardirq ctx better against write side and dont forget >>> EXPORT_SYMBOL, drivers can't use this otherwise. >>> >>> v3: Kerneldoc. >>> >>> v4: Some spelling fixes from Mika >>> >>> Cc: Mika Kuoppala <mika.kuoppala at intel.com> >>> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> >>> Cc: linux-media at vger.kernel.org >>> Cc: linaro-mm-sig at lists.linaro.org >>> Cc: linux-rdma at vger.kernel.org >>> Cc: amd-gfx at lists.freedesktop.org >>> Cc: intel-gfx at lists.freedesktop.org >>> Cc: Chris Wilson <chris at chris-wilson.co.uk> >>> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> >>> Cc: Christian K?nig <christian.koenig at amd.com> >>> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> >>> --- >>> Documentation/driver-api/dma-buf.rst | 12 +- >>> drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ >>> include/linux/dma-fence.h | 12 ++ >>> 3 files changed, 182 insertions(+), 3 deletions(-) >>> >>> diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst >>> index 63dec76d1d8d..05d856131140 100644 >>> --- a/Documentation/driver-api/dma-buf.rst >>> +++ b/Documentation/driver-api/dma-buf.rst >>> @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects >>> .. kernel-doc:: drivers/dma-buf/dma-buf.c >>> :doc: cpu access >>> >>> -Fence Poll Support >>> -~~~~~~~~~~~~~~~~~~ >>> +Implicit Fence Poll Support >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>> >>> .. kernel-doc:: drivers/dma-buf/dma-buf.c >>> - :doc: fence polling >>> + :doc: implicit fence polling >>> >>> Kernel Functions and Structures Reference >>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>> @@ -133,6 +133,12 @@ DMA Fences >>> .. kernel-doc:: drivers/dma-buf/dma-fence.c >>> :doc: DMA fences overview >>> >>> +DMA Fence Signalling Annotations >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>> + >>> +.. kernel-doc:: drivers/dma-buf/dma-fence.c >>> + :doc: fence signalling annotation >>> + >>> DMA Fences Functions Reference >>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>> >>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c >>> index 656e9ac2d028..0005bc002529 100644 >>> --- a/drivers/dma-buf/dma-fence.c >>> +++ b/drivers/dma-buf/dma-fence.c >>> @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) >>> } >>> EXPORT_SYMBOL(dma_fence_context_alloc); >>> >>> +/** >>> + * DOC: fence signalling annotation >>> + * >>> + * Proving correctness of all the kernel code around &dma_fence through code >>> + * review and testing is tricky for a few reasons: >>> + * >>> + * * It is a cross-driver contract, and therefore all drivers must follow the >>> + * same rules for lock nesting order, calling contexts for various functions >>> + * and anything else significant for in-kernel interfaces. But it is also >>> + * impossible to test all drivers in a single machine, hence brute-force N vs. >>> + * N testing of all combinations is impossible. Even just limiting to the >>> + * possible combinations is infeasible. >>> + * >>> + * * There is an enormous amount of driver code involved. For render drivers >>> + * there's the tail of command submission, after fences are published, >>> + * scheduler code, interrupt and workers to process job completion, >>> + * and timeout, gpu reset and gpu hang recovery code. Plus for integration >>> + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, >>> + * and &shrinker. For modesetting drivers there's the commit tail functions >>> + * between when fences for an atomic modeset are published, and when the >>> + * corresponding vblank completes, including any interrupt processing and >>> + * related workers. Auditing all that code, across all drivers, is not >>> + * feasible. >>> + * >>> + * * Due to how many other subsystems are involved and the locking hierarchies >>> + * this pulls in there is extremely thin wiggle-room for driver-specific >>> + * differences. &dma_fence interacts with almost all of the core memory >>> + * handling through page fault handlers via &dma_resv, dma_resv_lock() and >>> + * dma_resv_unlock(). On the other side it also interacts through all >>> + * allocation sites through &mmu_notifier and &shrinker. >>> + * >>> + * Furthermore lockdep does not handle cross-release dependencies, which means >>> + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught >>> + * at runtime with some quick testing. The simplest example is one thread >>> + * waiting on a &dma_fence while holding a lock:: >>> + * >>> + * lock(A); >>> + * dma_fence_wait(B); >>> + * unlock(A); >>> + * >>> + * while the other thread is stuck trying to acquire the same lock, which >>> + * prevents it from signalling the fence the previous thread is stuck waiting >>> + * on:: >>> + * >>> + * lock(A); >>> + * unlock(A); >>> + * dma_fence_signal(B); >>> + * >>> + * By manually annotating all code relevant to signalling a &dma_fence we can >>> + * teach lockdep about these dependencies, which also helps with the validation >>> + * headache since now lockdep can check all the rules for us:: >>> + * >>> + * cookie = dma_fence_begin_signalling(); >>> + * lock(A); >>> + * unlock(A); >>> + * dma_fence_signal(B); >>> + * dma_fence_end_signalling(cookie); >>> + * >>> + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to >>> + * annotate critical sections the following rules need to be observed: >>> + * >>> + * * All code necessary to complete a &dma_fence must be annotated, from the >>> + * point where a fence is accessible to other threads, to the point where >>> + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, >>> + * and due to the very strict rules and many corner cases it is infeasible to >>> + * catch these just with review or normal stress testing. >>> + * >>> + * * &struct dma_resv deserves a special note, since the readers are only >>> + * protected by rcu. This means the signalling critical section starts as soon >>> + * as the new fences are installed, even before dma_resv_unlock() is called. >>> + * >>> + * * The only exception are fast paths and opportunistic signalling code, which >>> + * calls dma_fence_signal() purely as an optimization, but is not required to >>> + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL >>> + * which calls dma_fence_signal(), while the mandatory completion path goes >>> + * through a hardware interrupt and possible job completion worker. >>> + * >>> + * * To aid composability of code, the annotations can be freely nested, as long >>> + * as the overall locking hierarchy is consistent. The annotations also work >>> + * both in interrupt and process context. Due to implementation details this >>> + * requires that callers pass an opaque cookie from >>> + * dma_fence_begin_signalling() to dma_fence_end_signalling(). >>> + * >>> + * * Validation against the cross driver contract is implemented by priming >>> + * lockdep with the relevant hierarchy at boot-up. This means even just >>> + * testing with a single device is enough to validate a driver, at least as >>> + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are >>> + * concerned. >>> + */ >>> +#ifdef CONFIG_LOCKDEP >>> +struct lockdep_map dma_fence_lockdep_map = { >>> + .name = "dma_fence_map" >>> +}; >> >> Maybe a stupid question because this is definitely complicated, but.. If >> you have a single/static/global lockdep map, doesn't this mean _all_ >> locks, from _all_ drivers happening to use dma-fences will get recorded >> in it. Will this work and not cause false positives? >> >> Sounds like it could create a common link between two completely >> unconnected usages. Because below you do add annotations to generic >> dma_fence_signal and dma_fence_wait. > > This is fully intentional. dma-fence is a cross-driver interface, if > every driver invents its own rules about how this should work we have > an unmaintainable and unreviewable mess. > > I've typed up the full length rant already here: > > https://lore.kernel.org/dri-devel/CAKMK7uGnFhbpuurRsnZ4dvRV9gQ_3-rmSJaoqSFY=+Kvepz_CA at mail.gmail.com/ But "perfect storm" of: + global fence lockmap + mmu notifiers + fs reclaim + default annotations in dma_fence_signal / dma_fence_wait Equals to anything ever using dma_fence will be in impossible chains with random other drivers, even if neither driver has code to export/share that fence. Example from the CI run: [25.918788] Chain exists of: fs_reclaim --> mmu_notifier_invalidate_range_start --> dma_fence_map [25.918794] Possible unsafe locking scenario: [25.918797] CPU0 CPU1 [25.918799] ---- ---- [25.918801] lock(dma_fence_map); [25.918803] lock(mmu_notifier_invalidate_range_start); [25.918807] lock(dma_fence_map); [25.918809] lock(fs_reclaim); What about a dma_fence_export helper which would "arm" the annotations? It would be called as soon as the fence is exported. Maybe when added to dma_resv, or exported via sync_file, etc. Before that point begin/end_signaling and so would be no-ops. >>> + >>> +/** >>> + * dma_fence_begin_signalling - begin a critical DMA fence signalling section >>> + * >>> + * Drivers should use this to annotate the beginning of any code section >>> + * required to eventually complete &dma_fence by calling dma_fence_signal(). >>> + * >>> + * The end of these critical sections are annotated with >>> + * dma_fence_end_signalling(). >>> + * >>> + * Returns: >>> + * >>> + * Opaque cookie needed by the implementation, which needs to be passed to >>> + * dma_fence_end_signalling(). >>> + */ >>> +bool dma_fence_begin_signalling(void) >>> +{ >>> + /* explicitly nesting ... */ >>> + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) >>> + return true; >>> + >>> + /* rely on might_sleep check for soft/hardirq locks */ >>> + if (in_atomic()) >>> + return true; >>> + >>> + /* ... and non-recursive readlock */ >>> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); >> >> Would it work if signalling path would mark itself as a write lock? I am >> thinking it would be nice to see in lockdep splats what are signals and >> what are waits. > > Yeah it'd be nice to have a read vs write name for the lock. But we > already have this problem for e.g. flush_work(), from which I've > stolen this idea. So it's not really new. Essentially look at the > backtraces lockdep gives you, and reconstruct the deadlock. I'm hoping > that people will notice the special functions on the backtrace, e.g. > dma_fence_begin_signalling will be listed as offending function/lock > holder, and then read the kerneldoc. > >> The recursive usage wouldn't work then right? Would write annotation on >> the wait path work? > > Wait path is write annotations already, but yeah annotating the > signalling side as write would cause endless amounts of alse > positives. Also it makes composability of these e.g. what I've done in > amdgpu with annotations in tdr work in drm/scheduler, annotations in > the amdgpu gpu reset code and then also annotations in atomic code, > which all nest within each other in some call chains, but not others. > Dropping the recursion would break that and make it really awkward to > annotate such cases correctly. > > And the recursion only works if it's read locks, otherwise lockdep > complains if you have inconsistent annotations on the signalling side > (which again would make it more or less impossible to annotate the > above case fully). How do I see in lockdep splats if it was a read or write user? Your patch appears to have: dma_fence_signal: + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); __dma_fence_might_wait: + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); Which both seem like read lock. I don't fully understand the lockdep API so I might be wrong, not sure. But neither I see a difference in splats telling me which path is which. Regards, Tvrtko From chris at chris-wilson.co.uk Thu Jun 11 10:41:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 11:41:30 +0100 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds In-Reply-To: <20200611080140.30228-2-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> <20200611080140.30228-2-chris@chris-wilson.co.uk> Message-ID: <159187209092.1506.14313893821550517148@build.alporthouse.com> Quoting Chris Wilson (2020-06-11 09:01:36) > +static void > +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > + /* > + * BSpec recommends 8x4 when MSAA is used, > + * however in practice 16x4 seems fastest. > + * > + * Note that PS/WM thread counts depend on the WIZ hashing > + * disable bit, which we don't touch here, but it's good > + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > + */ > + wa_add(wal, GEN7_GT_MODE, 0, > + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), > + GEN6_WIZ_HASHING_16x4); Fwiw, from gen8+, we have this in the ctx workarounds. Not sure if that's a better spot or not. An inquiry for later, as it is passing the tests for now :) -Chris From imre.deak at intel.com Thu Jun 11 10:41:46 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 11 Jun 2020 13:41:46 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Fix_the_i915=5Fdsc=5Ffec=5Fsupport_debugfs_file_for_DP?= =?utf-8?q?_MST_connectors_=28rev3=29?= In-Reply-To: <159173632185.17060.7305715607581242818@emeril.freedesktop.org> References: <20200608181023.11503-1-imre.deak@intel.com> <159173632185.17060.7305715607581242818@emeril.freedesktop.org> Message-ID: <20200611104146.GC17512@ideak-desk.fi.intel.com> On Tue, Jun 09, 2020 at 08:58:41PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915: Fix the i915_dsc_fec_support debugfs file for DP MST connectors (rev3) > URL : https://patchwork.freedesktop.org/series/78128/ > State : success Thanks for the review, pushed to -dinq. > > == Summary == > > CI Bug Log - changes from CI_DRM_8604_full -> Patchwork_17916_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17916_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_shared@q-independent at bcs0: > - shard-kbl: [PASS][1] -> [FAIL][2] ([i915#2013]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl6/igt at gem_ctx_shared@q-independent at bcs0.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl1/igt at gem_ctx_shared@q-independent at bcs0.html > > * igt at gem_exec_create@forked: > - shard-hsw: [PASS][3] -> [INCOMPLETE][4] ([i915#61]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-hsw7/igt at gem_exec_create@forked.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-hsw2/igt at gem_exec_create@forked.html > > * igt at gem_exec_schedule@implicit-read-write at rcs0: > - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-snb6/igt at gem_exec_schedule@implicit-read-write at rcs0.html > > * igt at gem_exec_whisper@basic-forked-all: > - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk8/igt at gem_exec_whisper@basic-forked-all.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-glk4/igt at gem_exec_whisper@basic-forked-all.html > > * igt at gem_workarounds@suspend-resume-context: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at gem_workarounds@suspend-resume-context.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl4/igt at gem_workarounds@suspend-resume-context.html > > * igt at i915_module_load@reload-with-fault-injection: > - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +3 similar issues > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html > > * igt at i915_pm_rps@reset: > - shard-skl: [PASS][13] -> [FAIL][14] ([i915#39]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl10/igt at i915_pm_rps@reset.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl5/igt at i915_pm_rps@reset.html > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) +1 similar issue > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: > - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl1/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > > * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: > - shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([i915#54] / [i915#95]) +1 similar issue > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > > * igt at kms_cursor_crc@pipe-a-cursor-64x64-onscreen: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) +1 similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html > > * igt at kms_cursor_crc@pipe-a-cursor-suspend: > - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +2 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html > > * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: > - shard-kbl: [PASS][25] -> [DMESG-FAIL][26] ([i915#95]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl4/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html > > * igt at kms_cursor_legacy@flip-vs-cursor-legacy: > - shard-skl: [PASS][27] -> [FAIL][28] ([IGT#5]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html > > * igt at kms_cursor_legacy@pipe-c-torture-move: > - shard-iclb: [PASS][29] -> [DMESG-WARN][30] ([i915#128]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb4/igt at kms_cursor_legacy@pipe-c-torture-move.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at kms_cursor_legacy@pipe-c-torture-move.html > > * igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled: > - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) +2 similar issues > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl6/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html > > * igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled: > - shard-skl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +10 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl10/igt at kms_draw_crc@draw-method-xrgb2101010-pwrite-ytiled.html > > * igt at kms_fbcon_fbt@psr-suspend: > - shard-iclb: [PASS][35] -> [INCOMPLETE][36] ([i915#1185]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb5/igt at kms_fbcon_fbt@psr-suspend.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb3/igt at kms_fbcon_fbt@psr-suspend.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: > - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html > > * igt at kms_hdr@bpc-switch: > - shard-skl: [PASS][39] -> [FAIL][40] ([i915#1188]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_hdr@bpc-switch.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_hdr@bpc-switch.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265]) +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_psr2_su@frontbuffer: > - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109642] / [fdo#111068]) > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr2_su@frontbuffer.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at kms_psr2_su@frontbuffer.html > > * igt at kms_psr@psr2_primary_mmap_gtt: > - shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109441]) +1 similar issue > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at kms_psr@psr2_primary_mmap_gtt.html > > * igt at kms_setmode@basic: > - shard-skl: [PASS][47] -> [FAIL][48] ([i915#31]) > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_setmode@basic.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl2/igt at kms_setmode@basic.html > > * igt at perf_pmu@module-unload: > - shard-iclb: [PASS][49] -> [DMESG-WARN][50] ([i915#1982]) > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb8/igt at perf_pmu@module-unload.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb3/igt at perf_pmu@module-unload.html > > * igt at syncobj_wait@invalid-wait-illegal-handle: > - shard-apl: [PASS][51] -> [DMESG-WARN][52] ([i915#95]) +25 similar issues > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at syncobj_wait@invalid-wait-illegal-handle.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl8/igt at syncobj_wait@invalid-wait-illegal-handle.html > > > #### Possible fixes #### > > * igt at gem_ctx_shared@q-independent at bcs0: > - shard-apl: [FAIL][53] ([i915#2013]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at gem_ctx_shared@q-independent at bcs0.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl1/igt at gem_ctx_shared@q-independent at bcs0.html > > * igt at gem_exec_suspend@basic-s3: > - shard-kbl: [DMESG-WARN][55] ([i915#93] / [i915#95]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at gem_exec_suspend@basic-s3.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl2/igt at gem_exec_suspend@basic-s3.html > > * igt at kms_big_fb@x-tiled-64bpp-rotate-180: > - shard-glk: [DMESG-FAIL][57] ([i915#118] / [i915#95]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-glk4/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-90: > - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-90.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl1/igt at kms_big_fb@yf-tiled-32bpp-rotate-90.html > > * igt at kms_color@pipe-a-ctm-0-5: > - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +5 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl7/igt at kms_color@pipe-a-ctm-0-5.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl8/igt at kms_color@pipe-a-ctm-0-5.html > > * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: > - shard-apl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * igt at kms_flip@flip-vs-suspend at a-edp1: > - shard-skl: [INCOMPLETE][65] ([i915#198]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl8/igt at kms_flip@flip-vs-suspend at a-edp1.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl5/igt at kms_flip@flip-vs-suspend at a-edp1.html > > * igt at kms_flip@flip-vs-suspend at c-dp1: > - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +5 similar issues > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl7/igt at kms_flip@flip-vs-suspend at c-dp1.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html > > * igt at kms_flip_tiling@flip-changes-tiling: > - shard-kbl: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl2/igt at kms_flip_tiling@flip-changes-tiling.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: > - shard-skl: [FAIL][71] ([i915#49]) -> [PASS][72] > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][73] ([i915#1188]) -> [PASS][74] > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence: > - shard-skl: [FAIL][75] ([i915#53]) -> [PASS][76] > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl6/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html > > * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: [FAIL][77] ([fdo#108145] / [i915#265]) -> [PASS][78] +1 similar issue > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [DMESG-FAIL][79] ([fdo#108145] / [i915#1982]) -> [PASS][80] > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt at kms_psr@psr2_primary_mmap_cpu: > - shard-iclb: [SKIP][81] ([fdo#109441]) -> [PASS][82] +2 similar issues > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb3/igt at kms_psr@psr2_primary_mmap_cpu.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html > > * igt at kms_setmode@basic: > - shard-kbl: [FAIL][83] ([i915#31]) -> [PASS][84] > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl4/igt at kms_setmode@basic.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl6/igt at kms_setmode@basic.html > > * igt at kms_vblank@pipe-c-query-busy-hang: > - shard-tglb: [DMESG-WARN][85] ([i915#402]) -> [PASS][86] > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb1/igt at kms_vblank@pipe-c-query-busy-hang.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb7/igt at kms_vblank@pipe-c-query-busy-hang.html > > * igt at sw_sync@sync_merge_same: > - shard-apl: [DMESG-WARN][87] ([i915#95]) -> [PASS][88] +19 similar issues > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at sw_sync@sync_merge_same.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl8/igt at sw_sync@sync_merge_same.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][89] ([i915#588]) -> [SKIP][90] ([i915#658]) > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-iclb4/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at i915_pm_dc@dc6-dpms: > - shard-tglb: [FAIL][91] ([i915#454]) -> [SKIP][92] ([i915#468]) > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-tglb6/igt at i915_pm_dc@dc6-dpms.html > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html > > * igt at i915_pm_dc@dc6-psr: > - shard-skl: [FAIL][93] ([i915#454]) -> [DMESG-FAIL][94] ([i915#1982]) > [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-skl4/igt at i915_pm_dc@dc6-psr.html > [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-skl9/igt at i915_pm_dc@dc6-psr.html > > * igt at kms_content_protection@atomic: > - shard-apl: [FAIL][95] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][96] ([i915#1319] / [i915#1635]) > [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl1/igt at kms_content_protection@atomic.html > [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl8/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@atomic-dpms: > - shard-apl: [TIMEOUT][97] ([i915#1319]) -> [TIMEOUT][98] ([i915#1319] / [i915#1635]) > [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl3/igt at kms_content_protection@atomic-dpms.html > [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl6/igt at kms_content_protection@atomic-dpms.html > > * igt at kms_content_protection@legacy: > - shard-apl: [TIMEOUT][99] ([i915#1319] / [i915#1635]) -> [FAIL][100] ([fdo#110321] / [fdo#110336]) > [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl4/igt at kms_content_protection@legacy.html > [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl4/igt at kms_content_protection@legacy.html > > * igt at kms_content_protection@lic: > - shard-apl: [TIMEOUT][101] ([i915#1319] / [i915#1635]) -> [TIMEOUT][102] ([i915#1319]) +1 similar issue > [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl2/igt at kms_content_protection@lic.html > [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl7/igt at kms_content_protection@lic.html > > * igt at kms_draw_crc@fill-fb: > - shard-apl: [DMESG-WARN][103] ([i915#95]) -> [DMESG-FAIL][104] ([i915#95]) > [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-apl7/igt at kms_draw_crc@fill-fb.html > [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-apl2/igt at kms_draw_crc@fill-fb.html > > * igt at kms_fbcon_fbt@fbc: > - shard-kbl: [FAIL][105] ([i915#64]) -> [DMESG-FAIL][106] ([i915#95]) > [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8604/shard-kbl6/igt at kms_fbcon_fbt@fbc.html > [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/shard-kbl1/igt at kms_fbcon_fbt@fbc.html > > > [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2013]: https://gitlab.freedesktop.org/drm/intel/issues/2013 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 > [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8604 -> Patchwork_17916 > > CI-20190529: 20190529 > CI_DRM_8604: 24c6364ec0e3c895ec4237d7a8f3516316a761ff @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17916: b4af214db886283d6bc416bb70d95623c8c47ff6 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17916/index.html From chris at chris-wilson.co.uk Thu Jun 11 10:42:08 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 11:42:08 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_reloc: Verify engine isolation Message-ID: <20200611104208.91381-1-chris@chris-wilson.co.uk> Check that when relocating a batch along an engine, we are not forced to wait upon a resource elsewhere that userspace may be holding, or else we are faced with a deadlock that may be injected by another user. That deadlock may be resolved by resetting the hostile context, but in doing so we should not break the relocation processing. Ideally, we would avoid the deadlock. References: https://gitlab.freedesktop.org/drm/intel/-/issues/2021 Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- tests/i915/gem_exec_reloc.c | 105 ++++++++++++++++++++++++++++++------ 1 file changed, 89 insertions(+), 16 deletions(-) diff --git a/tests/i915/gem_exec_reloc.c b/tests/i915/gem_exec_reloc.c index 6490d3a6f..2d4164076 100644 --- a/tests/i915/gem_exec_reloc.c +++ b/tests/i915/gem_exec_reloc.c @@ -43,6 +43,22 @@ static uint32_t find_last_set(uint64_t x) return i; } +static uint32_t __batch_create(int i915, uint32_t offset) +{ + const uint32_t bbe = MI_BATCH_BUFFER_END; + uint32_t handle; + + handle = gem_create(i915, ALIGN(offset + 4, 4096)); + gem_write(i915, handle, offset, &bbe, sizeof(bbe)); + + return handle; +} + +static uint32_t batch_create(int i915) +{ + return __batch_create(i915, 0); +} + static void write_dword(int fd, uint32_t target_handle, uint64_t target_offset, @@ -523,6 +539,72 @@ static void active_spin(int fd, unsigned engine) igt_spin_free(fd, spin); } +static void others_spin(int i915, unsigned engine) +{ + struct drm_i915_gem_relocation_entry reloc = {}; + struct drm_i915_gem_exec_object2 obj = { + .relocs_ptr = to_user_pointer(&reloc), + .relocation_count = 1, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .flags = engine, + }; + const struct intel_execution_engine2 *e; + igt_spin_t *spin = NULL; + uint64_t addr; + int fence; + + __for_each_physical_engine(i915, e) { + if (e->flags == engine) + continue; + + if (!spin) { + spin = igt_spin_new(i915, + .engine = e->flags, + .flags = IGT_SPIN_FENCE_OUT); + fence = dup(spin->out_fence); + } else { + int old_fence; + + spin->execbuf.flags &= ~I915_EXEC_RING_MASK; + spin->execbuf.flags |= e->flags; + gem_execbuf_wr(i915, &spin->execbuf); + + old_fence = fence; + fence = sync_fence_merge(old_fence, + spin->execbuf.rsvd2 >> 32); + close(spin->execbuf.rsvd2 >> 32); + close(old_fence); + } + } + igt_require(spin); + + /* All other engines are busy, let's relocate! */ + obj.handle = batch_create(i915); + reloc.target_handle = obj.handle; + reloc.presumed_offset = -1; + reloc.offset = 64; + gem_execbuf(i915, &execbuf); + + /* Verify the relocation took place */ + gem_read(i915, obj.handle, 64, &addr, sizeof(addr)); + igt_assert_eq_u64(addr, obj.offset); + gem_close(i915, obj.handle); + + /* Even if the spinner was harmed in the process */ + igt_spin_end(spin); + igt_assert_eq(sync_fence_wait(fence, 200), 0); + igt_assert_neq(sync_fence_status(fence), 0); + if (sync_fence_status(fence) < 0) + igt_warn("Spinner was cancelled, %s\n", + strerror(-sync_fence_status(fence))); + close(fence); + + igt_spin_free(i915, spin); +} + static bool has_64b_reloc(int fd) { return intel_gen(intel_get_drm_devid(fd)) >= 8; @@ -881,22 +963,6 @@ parallel_relocs(int count, unsigned long *out) return reloc; } -static uint32_t __batch_create(int i915, uint32_t offset) -{ - const uint32_t bbe = MI_BATCH_BUFFER_END; - uint32_t handle; - - handle = gem_create(i915, ALIGN(offset + 4, 4096)); - gem_write(i915, handle, offset, &bbe, sizeof(bbe)); - - return handle; -} - -static uint32_t batch_create(int i915) -{ - return __batch_create(i915, 0); -} - static int __execbuf(int i915, struct drm_i915_gem_execbuffer2 *execbuf) { int err; @@ -1336,6 +1402,13 @@ igt_main } } + igt_subtest_with_dynamic("basic-spin-others") { + __for_each_physical_engine(fd, e) { + igt_dynamic_f("%s", e->name) + others_spin(fd, e->flags); + } + } + igt_subtest_with_dynamic("basic-many-active") { __for_each_physical_engine(fd, e) { igt_dynamic_f("%s", e->name) -- 2.27.0 From patchwork at emeril.freedesktop.org Thu Jun 11 11:00:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 11:00:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl+=3A_Fix_DP_MST_ACT_sta?= =?utf-8?q?tus_handling?= In-Reply-To: <20200610183132.13341-1-imre.deak@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> Message-ID: <159187321750.22716.17510954788159350568@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/tgl+: Fix DP MST ACT status handling URL : https://patchwork.freedesktop.org/series/78193/ State : success == Summary == CI Bug Log - changes from CI_DRM_8611_full -> Patchwork_17921_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17921_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl6/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk1/igt at gem_exec_whisper@basic-queues-forked-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at gen9_exec_parse@allowed-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk9/igt at gen9_exec_parse@allowed-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-glk1/igt at gen9_exec_parse@allowed-all.html * igt at i915_module_load@reload: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb3/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-tglb6/igt at i915_module_load@reload.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl3/igt at kms_big_fb@linear-32bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl8/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk4/igt at kms_big_fb@linear-64bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl1/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html * igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#95]) +26 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl3/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl7/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl2/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl7/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-glk: [PASS][21] -> [INCOMPLETE][22] ([i915#58] / [k.org#198133]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk7/igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-glk5/igt at kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#123] / [i915#69]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl3/igt at kms_frontbuffer_tracking@psr-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl10/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl7/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][27] -> [INCOMPLETE][28] ([i915#155] / [i915#648]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_multiple@atomic-pipe-c-tiling-y: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +9 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl1/igt at kms_plane_multiple@atomic-pipe-c-tiling-y.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl2/igt at kms_plane_multiple@atomic-pipe-c-tiling-y.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-iclb1/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][33] -> [INCOMPLETE][34] ([i915#69]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl9/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl8/igt at kms_vblank@pipe-a-ts-continuation-suspend.html #### Possible fixes #### * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][35] ([i915#1936]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt at gem_exec_balancer@sliced.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-tglb8/igt at gem_exec_balancer@sliced.html * igt at gem_exec_reloc@basic-wc-cpu-active: - shard-apl: [DMESG-WARN][37] ([i915#95]) -> [PASS][38] +18 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt at gem_exec_reloc@basic-wc-cpu-active.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl3/igt at gem_exec_reloc@basic-wc-cpu-active.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [FAIL][39] ([fdo#103375]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl7/igt at i915_suspend@debugfs-reader.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl6/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@linear-8bpp-rotate-180: - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt at kms_big_fb@linear-8bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl8/igt at kms_big_fb@linear-8bpp-rotate-180.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-glk9/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_legacy@flip-vs-cursor-crc-atomic: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +10 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl2/igt at kms_cursor_legacy@flip-vs-cursor-crc-atomic.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl3/igt at kms_cursor_legacy@flip-vs-cursor-crc-atomic.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-tglb: [DMESG-WARN][47] ([i915#128]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb2/igt at kms_cursor_legacy@pipe-b-torture-move.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-tglb7/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_flip@busy-flip at b-edp1: - shard-skl: [FAIL][49] ([i915#275]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl5/igt at kms_flip@busy-flip at b-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl9/igt at kms_flip@busy-flip at b-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-iclb: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb7/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-iclb2/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@plain-flip-ts-check at a-dp1: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_flip@plain-flip-ts-check at a-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl6/igt at kms_flip@plain-flip-ts-check at a-dp1.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl4/igt at kms_hdr@bpc-switch.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl4/igt at kms_hdr@bpc-switch.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-glk: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-glk6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][63] ([i915#173]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt at kms_psr@no_drrs.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-iclb5/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at perf_pmu@module-unload: - shard-iclb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb5/igt at perf_pmu@module-unload.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-iclb5/igt at perf_pmu@module-unload.html * igt at perf_pmu@other-init-3: - shard-tglb: [DMESG-WARN][69] ([i915#402]) -> [PASS][70] +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb6/igt at perf_pmu@other-init-3.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-tglb6/igt at perf_pmu@other-init-3.html * igt at syncobj_wait@single-wait-all-for-submit-signaled: - shard-tglb: [TIMEOUT][71] -> [PASS][72] +2 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt at syncobj_wait@single-wait-all-for-submit-signaled.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-tglb8/igt at syncobj_wait@single-wait-all-for-submit-signaled.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-glk: [TIMEOUT][73] ([i915#1958]) -> [INCOMPLETE][74] ([i915#1958] / [i915#58] / [k.org#198133]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk5/igt at gem_exec_reloc@basic-concurrent16.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-glk4/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][75] ([i915#1515]) -> [WARN][76] ([i915#1515]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at i915_pm_rc6_residency@rc6-idle.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-iclb1/igt at i915_pm_rc6_residency@rc6-idle.html * igt at i915_suspend@forcewake: - shard-kbl: [DMESG-WARN][77] ([i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#180] / [i915#93] / [i915#95]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl7/igt at i915_suspend@forcewake.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl1/igt at i915_suspend@forcewake.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][79] ([i915#1319] / [i915#1635]) -> [FAIL][80] ([fdo#110321] / [fdo#110336]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt at kms_content_protection@atomic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl7/igt at kms_content_protection@atomic.html * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][81] ([i915#1319] / [i915#1958]) -> [TIMEOUT][82] ([i915#1319]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_content_protection@lic.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl6/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][83] ([i915#1319] / [i915#1958]) -> [DMESG-FAIL][84] ([fdo#110321] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_content_protection@srm.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-kbl2/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][85] ([fdo#110321] / [i915#95]) -> [TIMEOUT][86] ([i915#1319]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt at kms_content_protection@srm.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl2/igt at kms_content_protection@srm.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [FAIL][87] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/shard-apl2/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#275]: https://gitlab.freedesktop.org/drm/intel/issues/275 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17921 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17921: 77a732d46697f75e67997a7b5f8a94b21ab8e556 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17921/index.html From pr-tracker-bot at kernel.org Thu Jun 11 01:50:26 2020 From: pr-tracker-bot at kernel.org (pr-tracker-bot at kernel.org) Date: Thu, 11 Jun 2020 01:50:26 +0000 Subject: [Intel-gfx] [git pull] uaccess i915 In-Reply-To: <20200610202837.GV23230@ZenIV.linux.org.uk> References: <20200610202837.GV23230@ZenIV.linux.org.uk> Message-ID: <159184022602.24802.16565146152387751985.pr-tracker-bot@kernel.org> The pull request you sent on Wed, 10 Jun 2020 21:28:37 +0100: > git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git uaccess.i915 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/3a8557e1aed0043d526f304a1f500108c8976b78 Thank you! -- Deet-doot-dot, I am a bot. https://korg.wiki.kernel.org/userdoc/prtracker From patchwork at emeril.freedesktop.org Thu Jun 11 11:15:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 11:15:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915=3A_Include_asm_sources_for_=7Bivb=2C_hsw=7D=5Fclear=5Fker?= =?utf-8?b?bmVsLmMgKHJldjIp?= In-Reply-To: <20200608174654.1400710-1-rodrigo.vivi@intel.com> References: <20200608174654.1400710-1-rodrigo.vivi@intel.com> Message-ID: <159187413826.22716.11093398519895740643@emeril.freedesktop.org> == Series Details == Series: drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c (rev2) URL : https://patchwork.freedesktop.org/series/78126/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8611_full -> Patchwork_17924_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17924_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17924_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17924_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_endless@dispatch at rcs0: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt at gem_exec_endless@dispatch at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb7/igt at gem_exec_endless@dispatch at rcs0.html Known issues ------------ Here are the changes found in Patchwork_17924_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at rcs0: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#1528]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl3/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl4/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt at gem_exec_suspend@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl4/igt at gem_exec_suspend@basic-s3.html * igt at gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk9/igt at gem_exec_whisper@basic-fds-priority.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk1/igt at gem_exec_whisper@basic-fds-priority.html * igt at gem_workarounds@suspend-resume-context: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl8/igt at gem_workarounds@suspend-resume-context.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl1/igt at gem_workarounds@suspend-resume-context.html * igt at i915_pm_dc@dc5-psr: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#198]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl8/igt at i915_pm_dc@dc5-psr.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl2/igt at i915_pm_dc@dc5-psr.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#300]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#93] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl4/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#72]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk9/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk7/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#128]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at kms_cursor_legacy@all-pipes-torture-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb4/igt at kms_cursor_legacy@all-pipes-torture-move.html * igt at kms_cursor_legacy@cursora-vs-flipa-varying-size: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +7 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl1/igt at kms_cursor_legacy@cursora-vs-flipa-varying-size.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl2/igt at kms_cursor_legacy@cursora-vs-flipa-varying-size.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#95]) +25 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb4/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at perf@polling: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#1542]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl1/igt at perf@polling.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl2/igt at perf@polling.html #### Possible fixes #### * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-kbl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][33] ([i915#1936]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt at gem_exec_balancer@sliced.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb8/igt at gem_exec_balancer@sliced.html * igt at gem_exec_reloc@basic-wc-cpu-active: - shard-apl: [DMESG-WARN][35] ([i915#95]) -> [PASS][36] +18 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt at gem_exec_reloc@basic-wc-cpu-active.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl8/igt at gem_exec_reloc@basic-wc-cpu-active.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [FAIL][39] ([fdo#103375]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl7/igt at i915_suspend@debugfs-reader.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl3/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-skl: [FAIL][43] ([i915#54]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html * igt at kms_cursor_edge_walk@pipe-b-256x256-top-edge: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt at kms_cursor_edge_walk@pipe-b-256x256-top-edge.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl4/igt at kms_cursor_edge_walk@pipe-b-256x256-top-edge.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-tglb: [DMESG-WARN][47] ([i915#128]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb2/igt at kms_cursor_legacy@pipe-b-torture-move.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb2/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +12 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl8/igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl10/igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html * igt at kms_flip@busy-flip at b-edp1: - shard-skl: [FAIL][51] ([i915#275]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl5/igt at kms_flip@busy-flip at b-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl3/igt at kms_flip@busy-flip at b-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-iclb: [FAIL][53] ([i915#79]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb7/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@plain-flip-ts-check at a-dp1: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_flip@plain-flip-ts-check at a-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl2/igt at kms_flip@plain-flip-ts-check at a-dp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][57] ([i915#1188]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl2/igt at kms_hdr@bpc-switch-dpms.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [INCOMPLETE][59] ([i915#155]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-glk: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk5/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb8/igt at kms_psr2_su@page_flip.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][67] ([i915#173]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt at kms_psr@no_drrs.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb7/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb4/igt at kms_psr@psr2_suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at perf_pmu@module-unload: - shard-iclb: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb5/igt at perf_pmu@module-unload.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb5/igt at perf_pmu@module-unload.html * igt at perf_pmu@other-init-3: - shard-tglb: [DMESG-WARN][73] ([i915#402]) -> [PASS][74] +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb6/igt at perf_pmu@other-init-3.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb1/igt at perf_pmu@other-init-3.html * igt at syncobj_wait@single-wait-all-for-submit-signaled: - shard-tglb: [TIMEOUT][75] -> [PASS][76] +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt at syncobj_wait@single-wait-all-for-submit-signaled.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-tglb8/igt at syncobj_wait@single-wait-all-for-submit-signaled.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [INCOMPLETE][77] ([i915#1635] / [i915#1958]) -> [TIMEOUT][78] ([i915#1635]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt at gem_exec_reloc@basic-concurrent16.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html - shard-glk: [TIMEOUT][79] ([i915#1958]) -> [INCOMPLETE][80] ([i915#1958] / [i915#58] / [k.org#198133]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk5/igt at gem_exec_reloc@basic-concurrent16.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-glk7/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][81] ([i915#1515]) -> [WARN][82] ([i915#1515]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at i915_pm_rc6_residency@rc6-idle.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-iclb4/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][83] ([i915#1319]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl1/igt at kms_content_protection@atomic-dpms.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][85] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][86] ([i915#1319] / [i915#1635]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl6/igt at kms_content_protection@legacy.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][87] ([i915#1319] / [i915#1958]) -> [TIMEOUT][88] ([i915#1319]) +1 similar issue [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_content_protection@srm.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-kbl6/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][89] ([fdo#110321] / [i915#95]) -> [TIMEOUT][90] ([i915#1319] / [i915#1635]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt at kms_content_protection@srm.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt at kms_content_protection@srm.html * igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled: - shard-apl: [DMESG-FAIL][91] ([i915#54] / [i915#95]) -> [DMESG-WARN][92] ([i915#95]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl1/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [FAIL][93] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][94] ([fdo#108145] / [i915#95]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/shard-apl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#275]: https://gitlab.freedesktop.org/drm/intel/issues/275 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17924 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17924: fbdbc3448e1c3c404e07c2aa64e972f31fad7652 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17924/index.html From daniel.vetter at ffwll.ch Thu Jun 11 11:29:21 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 11 Jun 2020 13:29:21 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <19c6fe47-50ff-869e-d3f0-703b8165d577@linux.intel.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <be3526aa-07db-adc0-9291-1b5aeb0d1613@linux.intel.com> <CAKMK7uE4ak=gaKNJziaLg1qN1mE1FKLW1MGFkmUz2tR2y0ArAA@mail.gmail.com> <19c6fe47-50ff-869e-d3f0-703b8165d577@linux.intel.com> Message-ID: <CAKMK7uEKYJ1kPrB01yw9A3ZHHZ4jDmzwxMjymn7pxOgs9hpKBA@mail.gmail.com> On Thu, Jun 11, 2020 at 12:36 PM Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> wrote: > > > On 10/06/2020 16:17, Daniel Vetter wrote: > > On Wed, Jun 10, 2020 at 4:22 PM Tvrtko Ursulin > > <tvrtko.ursulin at linux.intel.com> wrote: > >> > >> > >> On 04/06/2020 09:12, Daniel Vetter wrote: > >>> Design is similar to the lockdep annotations for workers, but with > >>> some twists: > >>> > >>> - We use a read-lock for the execution/worker/completion side, so that > >>> this explicit annotation can be more liberally sprinkled around. > >>> With read locks lockdep isn't going to complain if the read-side > >>> isn't nested the same way under all circumstances, so ABBA deadlocks > >>> are ok. Which they are, since this is an annotation only. > >>> > >>> - We're using non-recursive lockdep read lock mode, since in recursive > >>> read lock mode lockdep does not catch read side hazards. And we > >>> _very_ much want read side hazards to be caught. For full details of > >>> this limitation see > >>> > >>> commit e91498589746065e3ae95d9a00b068e525eec34f > >>> Author: Peter Zijlstra <peterz at infradead.org> > >>> Date: Wed Aug 23 13:13:11 2017 +0200 > >>> > >>> locking/lockdep/selftests: Add mixed read-write ABBA tests > >>> > >>> - To allow nesting of the read-side explicit annotations we explicitly > >>> keep track of the nesting. lock_is_held() allows us to do that. > >>> > >>> - The wait-side annotation is a write lock, and entirely done within > >>> dma_fence_wait() for everyone by default. > >>> > >>> - To be able to freely annotate helper functions I want to make it ok > >>> to call dma_fence_begin/end_signalling from soft/hardirq context. > >>> First attempt was using the hardirq locking context for the write > >>> side in lockdep, but this forces all normal spinlocks nested within > >>> dma_fence_begin/end_signalling to be spinlocks. That bollocks. > >>> > >>> The approach now is to simple check in_atomic(), and for these cases > >>> entirely rely on the might_sleep() check in dma_fence_wait(). That > >>> will catch any wrong nesting against spinlocks from soft/hardirq > >>> contexts. > >>> > >>> The idea here is that every code path that's critical for eventually > >>> signalling a dma_fence should be annotated with > >>> dma_fence_begin/end_signalling. The annotation ideally starts right > >>> after a dma_fence is published (added to a dma_resv, exposed as a > >>> sync_file fd, attached to a drm_syncobj fd, or anything else that > >>> makes the dma_fence visible to other kernel threads), up to and > >>> including the dma_fence_wait(). Examples are irq handlers, the > >>> scheduler rt threads, the tail of execbuf (after the corresponding > >>> fences are visible), any workers that end up signalling dma_fences and > >>> really anything else. Not annotated should be code paths that only > >>> complete fences opportunistically as the gpu progresses, like e.g. > >>> shrinker/eviction code. > >>> > >>> The main class of deadlocks this is supposed to catch are: > >>> > >>> Thread A: > >>> > >>> mutex_lock(A); > >>> mutex_unlock(A); > >>> > >>> dma_fence_signal(); > >>> > >>> Thread B: > >>> > >>> mutex_lock(A); > >>> dma_fence_wait(); > >>> mutex_unlock(A); > >>> > >>> Thread B is blocked on A signalling the fence, but A never gets around > >>> to that because it cannot acquire the lock A. > >>> > >>> Note that dma_fence_wait() is allowed to be nested within > >>> dma_fence_begin/end_signalling sections. To allow this to happen the > >>> read lock needs to be upgraded to a write lock, which means that any > >>> other lock is acquired between the dma_fence_begin_signalling() call and > >>> the call to dma_fence_wait(), and still held, this will result in an > >>> immediate lockdep complaint. The only other option would be to not > >>> annotate such calls, defeating the point. Therefore these annotations > >>> cannot be sprinkled over the code entirely mindless to avoid false > >>> positives. > >>> > >>> v2: handle soft/hardirq ctx better against write side and dont forget > >>> EXPORT_SYMBOL, drivers can't use this otherwise. > >>> > >>> v3: Kerneldoc. > >>> > >>> v4: Some spelling fixes from Mika > >>> > >>> Cc: Mika Kuoppala <mika.kuoppala at intel.com> > >>> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > >>> Cc: linux-media at vger.kernel.org > >>> Cc: linaro-mm-sig at lists.linaro.org > >>> Cc: linux-rdma at vger.kernel.org > >>> Cc: amd-gfx at lists.freedesktop.org > >>> Cc: intel-gfx at lists.freedesktop.org > >>> Cc: Chris Wilson <chris at chris-wilson.co.uk> > >>> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > >>> Cc: Christian K?nig <christian.koenig at amd.com> > >>> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > >>> --- > >>> Documentation/driver-api/dma-buf.rst | 12 +- > >>> drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ > >>> include/linux/dma-fence.h | 12 ++ > >>> 3 files changed, 182 insertions(+), 3 deletions(-) > >>> > >>> diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > >>> index 63dec76d1d8d..05d856131140 100644 > >>> --- a/Documentation/driver-api/dma-buf.rst > >>> +++ b/Documentation/driver-api/dma-buf.rst > >>> @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > >>> .. kernel-doc:: drivers/dma-buf/dma-buf.c > >>> :doc: cpu access > >>> > >>> -Fence Poll Support > >>> -~~~~~~~~~~~~~~~~~~ > >>> +Implicit Fence Poll Support > >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>> > >>> .. kernel-doc:: drivers/dma-buf/dma-buf.c > >>> - :doc: fence polling > >>> + :doc: implicit fence polling > >>> > >>> Kernel Functions and Structures Reference > >>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>> @@ -133,6 +133,12 @@ DMA Fences > >>> .. kernel-doc:: drivers/dma-buf/dma-fence.c > >>> :doc: DMA fences overview > >>> > >>> +DMA Fence Signalling Annotations > >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>> + > >>> +.. kernel-doc:: drivers/dma-buf/dma-fence.c > >>> + :doc: fence signalling annotation > >>> + > >>> DMA Fences Functions Reference > >>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>> > >>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > >>> index 656e9ac2d028..0005bc002529 100644 > >>> --- a/drivers/dma-buf/dma-fence.c > >>> +++ b/drivers/dma-buf/dma-fence.c > >>> @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) > >>> } > >>> EXPORT_SYMBOL(dma_fence_context_alloc); > >>> > >>> +/** > >>> + * DOC: fence signalling annotation > >>> + * > >>> + * Proving correctness of all the kernel code around &dma_fence through code > >>> + * review and testing is tricky for a few reasons: > >>> + * > >>> + * * It is a cross-driver contract, and therefore all drivers must follow the > >>> + * same rules for lock nesting order, calling contexts for various functions > >>> + * and anything else significant for in-kernel interfaces. But it is also > >>> + * impossible to test all drivers in a single machine, hence brute-force N vs. > >>> + * N testing of all combinations is impossible. Even just limiting to the > >>> + * possible combinations is infeasible. > >>> + * > >>> + * * There is an enormous amount of driver code involved. For render drivers > >>> + * there's the tail of command submission, after fences are published, > >>> + * scheduler code, interrupt and workers to process job completion, > >>> + * and timeout, gpu reset and gpu hang recovery code. Plus for integration > >>> + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, > >>> + * and &shrinker. For modesetting drivers there's the commit tail functions > >>> + * between when fences for an atomic modeset are published, and when the > >>> + * corresponding vblank completes, including any interrupt processing and > >>> + * related workers. Auditing all that code, across all drivers, is not > >>> + * feasible. > >>> + * > >>> + * * Due to how many other subsystems are involved and the locking hierarchies > >>> + * this pulls in there is extremely thin wiggle-room for driver-specific > >>> + * differences. &dma_fence interacts with almost all of the core memory > >>> + * handling through page fault handlers via &dma_resv, dma_resv_lock() and > >>> + * dma_resv_unlock(). On the other side it also interacts through all > >>> + * allocation sites through &mmu_notifier and &shrinker. > >>> + * > >>> + * Furthermore lockdep does not handle cross-release dependencies, which means > >>> + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught > >>> + * at runtime with some quick testing. The simplest example is one thread > >>> + * waiting on a &dma_fence while holding a lock:: > >>> + * > >>> + * lock(A); > >>> + * dma_fence_wait(B); > >>> + * unlock(A); > >>> + * > >>> + * while the other thread is stuck trying to acquire the same lock, which > >>> + * prevents it from signalling the fence the previous thread is stuck waiting > >>> + * on:: > >>> + * > >>> + * lock(A); > >>> + * unlock(A); > >>> + * dma_fence_signal(B); > >>> + * > >>> + * By manually annotating all code relevant to signalling a &dma_fence we can > >>> + * teach lockdep about these dependencies, which also helps with the validation > >>> + * headache since now lockdep can check all the rules for us:: > >>> + * > >>> + * cookie = dma_fence_begin_signalling(); > >>> + * lock(A); > >>> + * unlock(A); > >>> + * dma_fence_signal(B); > >>> + * dma_fence_end_signalling(cookie); > >>> + * > >>> + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to > >>> + * annotate critical sections the following rules need to be observed: > >>> + * > >>> + * * All code necessary to complete a &dma_fence must be annotated, from the > >>> + * point where a fence is accessible to other threads, to the point where > >>> + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, > >>> + * and due to the very strict rules and many corner cases it is infeasible to > >>> + * catch these just with review or normal stress testing. > >>> + * > >>> + * * &struct dma_resv deserves a special note, since the readers are only > >>> + * protected by rcu. This means the signalling critical section starts as soon > >>> + * as the new fences are installed, even before dma_resv_unlock() is called. > >>> + * > >>> + * * The only exception are fast paths and opportunistic signalling code, which > >>> + * calls dma_fence_signal() purely as an optimization, but is not required to > >>> + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL > >>> + * which calls dma_fence_signal(), while the mandatory completion path goes > >>> + * through a hardware interrupt and possible job completion worker. > >>> + * > >>> + * * To aid composability of code, the annotations can be freely nested, as long > >>> + * as the overall locking hierarchy is consistent. The annotations also work > >>> + * both in interrupt and process context. Due to implementation details this > >>> + * requires that callers pass an opaque cookie from > >>> + * dma_fence_begin_signalling() to dma_fence_end_signalling(). > >>> + * > >>> + * * Validation against the cross driver contract is implemented by priming > >>> + * lockdep with the relevant hierarchy at boot-up. This means even just > >>> + * testing with a single device is enough to validate a driver, at least as > >>> + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are > >>> + * concerned. > >>> + */ > >>> +#ifdef CONFIG_LOCKDEP > >>> +struct lockdep_map dma_fence_lockdep_map = { > >>> + .name = "dma_fence_map" > >>> +}; > >> > >> Maybe a stupid question because this is definitely complicated, but.. If > >> you have a single/static/global lockdep map, doesn't this mean _all_ > >> locks, from _all_ drivers happening to use dma-fences will get recorded > >> in it. Will this work and not cause false positives? > >> > >> Sounds like it could create a common link between two completely > >> unconnected usages. Because below you do add annotations to generic > >> dma_fence_signal and dma_fence_wait. > > > > This is fully intentional. dma-fence is a cross-driver interface, if > > every driver invents its own rules about how this should work we have > > an unmaintainable and unreviewable mess. > > > > I've typed up the full length rant already here: > > > > https://lore.kernel.org/dri-devel/CAKMK7uGnFhbpuurRsnZ4dvRV9gQ_3-rmSJaoqSFY=+Kvepz_CA at mail.gmail.com/ > > But "perfect storm" of: > > + global fence lockmap > + mmu notifiers > + fs reclaim > + default annotations in dma_fence_signal / dma_fence_wait > > Equals to anything ever using dma_fence will be in impossible chains with random other drivers, even if neither driver has code to export/share that fence. > > Example from the CI run: > > [25.918788] Chain exists of: > fs_reclaim --> mmu_notifier_invalidate_range_start --> dma_fence_map > [25.918794] Possible unsafe locking scenario: > [25.918797] CPU0 CPU1 > [25.918799] ---- ---- > [25.918801] lock(dma_fence_map); > [25.918803] lock(mmu_notifier_invalidate_range_start); > [25.918807] lock(dma_fence_map); > [25.918809] lock(fs_reclaim); > > What about a dma_fence_export helper which would "arm" the annotations? It would be called as soon as the fence is exported. Maybe when added to dma_resv, or exported via sync_file, etc. Before that point begin/end_signaling and so would be no-ops. Run CI without the i915 annotation patch, nothing breaks. So we can gradually fix up existing code that doesn't quite get it right and move on. > >>> + > >>> +/** > >>> + * dma_fence_begin_signalling - begin a critical DMA fence signalling section > >>> + * > >>> + * Drivers should use this to annotate the beginning of any code section > >>> + * required to eventually complete &dma_fence by calling dma_fence_signal(). > >>> + * > >>> + * The end of these critical sections are annotated with > >>> + * dma_fence_end_signalling(). > >>> + * > >>> + * Returns: > >>> + * > >>> + * Opaque cookie needed by the implementation, which needs to be passed to > >>> + * dma_fence_end_signalling(). > >>> + */ > >>> +bool dma_fence_begin_signalling(void) > >>> +{ > >>> + /* explicitly nesting ... */ > >>> + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) > >>> + return true; > >>> + > >>> + /* rely on might_sleep check for soft/hardirq locks */ > >>> + if (in_atomic()) > >>> + return true; > >>> + > >>> + /* ... and non-recursive readlock */ > >>> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > >> > >> Would it work if signalling path would mark itself as a write lock? I am > >> thinking it would be nice to see in lockdep splats what are signals and > >> what are waits. > > > > Yeah it'd be nice to have a read vs write name for the lock. But we > > already have this problem for e.g. flush_work(), from which I've > > stolen this idea. So it's not really new. Essentially look at the > > backtraces lockdep gives you, and reconstruct the deadlock. I'm hoping > > that people will notice the special functions on the backtrace, e.g. > > dma_fence_begin_signalling will be listed as offending function/lock > > holder, and then read the kerneldoc. > > > >> The recursive usage wouldn't work then right? Would write annotation on > >> the wait path work? > > > > Wait path is write annotations already, but yeah annotating the > > signalling side as write would cause endless amounts of alse > > positives. Also it makes composability of these e.g. what I've done in > > amdgpu with annotations in tdr work in drm/scheduler, annotations in > > the amdgpu gpu reset code and then also annotations in atomic code, > > which all nest within each other in some call chains, but not others. > > Dropping the recursion would break that and make it really awkward to > > annotate such cases correctly. > > > > And the recursion only works if it's read locks, otherwise lockdep > > complains if you have inconsistent annotations on the signalling side > > (which again would make it more or less impossible to annotate the > > above case fully). > > How do I see in lockdep splats if it was a read or write user? Your patch appears to have: > > dma_fence_signal: > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > > __dma_fence_might_wait: > + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > > Which both seem like read lock. I don't fully understand the lockdep API so I might be wrong, not sure. But neither I see a difference in splats telling me which path is which. I think you got tricked by the implementation, this isn't quite what's going on. There's two things which make the annotations special: - we want a recursive read lock on the signalling critical section. The problem is that lockdep doesn't implement full validation for recursive read locks, only non-recursive read/write locks fully validated. There's some checks for recursive read locks, but exactly the checks we need to catch common dma_fence_wait deadlocks aren't done. That's why we need to implement manual lock recursion on the reader side - now on the write side we additionally need to implement an read2write upgrade, and a write2read downgrade. Lockdep doesn't implement that, so again we have to hand-roll this. Let's go through the code line-by-line: bool tmp; tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); We check whether someone is holding the non-recursive read lock already. if (tmp) lock_release(&dma_fence_lockdep_map, _THIS_IP_); If that's the case, we drop that read lock. lock_map_acquire(&dma_fence_lockdep_map); Then we do the actual might_wait annotation, the above takes the full write lock ... lock_map_release(&dma_fence_lockdep_map); ... and now we release the write lock again. if (tmp) lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); Finally we need to re-acquire the read lock, if we've held that when entering this function. This annotation naturally has to exactly match what begin_signalling would do, otherwise the hand-rolled nesting would fall apart. I hope that explains what's going on here, and assures you that might_wait() is indeed a write lock annotation, but with a big pile of complications. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From tvrtko.ursulin at linux.intel.com Thu Jun 11 11:38:22 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 11 Jun 2020 12:38:22 +0100 Subject: [Intel-gfx] [PATCH 04/28] drm/i915/selftests: Remove live_suppress_wait_preempt In-Reply-To: <20200607222108.14401-4-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-4-chris@chris-wilson.co.uk> Message-ID: <716a37f5-544e-c871-ec31-21b7288337b7@linux.intel.com> On 07/06/2020 23:20, Chris Wilson wrote: > With the removal of the internal wait-priority boosting, we can also > remove the selftest to ensure that those waits were being suppressed > from causing preemptions. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko > --- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 178 ------------------------- > 1 file changed, 178 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index 67d74e6432a8..e838e38a262c 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -2379,183 +2379,6 @@ static int live_suppress_self_preempt(void *arg) > goto err_client_b; > } > > -static int __i915_sw_fence_call > -dummy_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) > -{ > - return NOTIFY_DONE; > -} > - > -static struct i915_request *dummy_request(struct intel_engine_cs *engine) > -{ > - struct i915_request *rq; > - > - rq = kzalloc(sizeof(*rq), GFP_KERNEL); > - if (!rq) > - return NULL; > - > - rq->engine = engine; > - > - spin_lock_init(&rq->lock); > - INIT_LIST_HEAD(&rq->fence.cb_list); > - rq->fence.lock = &rq->lock; > - rq->fence.ops = &i915_fence_ops; > - > - i915_sched_node_init(&rq->sched); > - > - /* mark this request as permanently incomplete */ > - rq->fence.seqno = 1; > - BUILD_BUG_ON(sizeof(rq->fence.seqno) != 8); /* upper 32b == 0 */ > - rq->hwsp_seqno = (u32 *)&rq->fence.seqno + 1; > - GEM_BUG_ON(i915_request_completed(rq)); > - > - i915_sw_fence_init(&rq->submit, dummy_notify); > - set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); > - > - spin_lock_init(&rq->lock); > - rq->fence.lock = &rq->lock; > - INIT_LIST_HEAD(&rq->fence.cb_list); > - > - return rq; > -} > - > -static void dummy_request_free(struct i915_request *dummy) > -{ > - /* We have to fake the CS interrupt to kick the next request */ > - i915_sw_fence_commit(&dummy->submit); > - > - i915_request_mark_complete(dummy); > - dma_fence_signal(&dummy->fence); > - > - i915_sched_node_fini(&dummy->sched); > - i915_sw_fence_fini(&dummy->submit); > - > - dma_fence_free(&dummy->fence); > -} > - > -static int live_suppress_wait_preempt(void *arg) > -{ > - struct intel_gt *gt = arg; > - struct preempt_client client[4]; > - struct i915_request *rq[ARRAY_SIZE(client)] = {}; > - struct intel_engine_cs *engine; > - enum intel_engine_id id; > - int err = -ENOMEM; > - int i; > - > - /* > - * Waiters are given a little priority nudge, but not enough > - * to actually cause any preemption. Double check that we do > - * not needlessly generate preempt-to-idle cycles. > - */ > - > - if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915)) > - return 0; > - > - if (preempt_client_init(gt, &client[0])) /* ELSP[0] */ > - return -ENOMEM; > - if (preempt_client_init(gt, &client[1])) /* ELSP[1] */ > - goto err_client_0; > - if (preempt_client_init(gt, &client[2])) /* head of queue */ > - goto err_client_1; > - if (preempt_client_init(gt, &client[3])) /* bystander */ > - goto err_client_2; > - > - for_each_engine(engine, gt, id) { > - int depth; > - > - if (!intel_engine_has_preemption(engine)) > - continue; > - > - if (!engine->emit_init_breadcrumb) > - continue; > - > - for (depth = 0; depth < ARRAY_SIZE(client); depth++) { > - struct i915_request *dummy; > - > - engine->execlists.preempt_hang.count = 0; > - > - dummy = dummy_request(engine); > - if (!dummy) > - goto err_client_3; > - > - for (i = 0; i < ARRAY_SIZE(client); i++) { > - struct i915_request *this; > - > - this = spinner_create_request(&client[i].spin, > - client[i].ctx, engine, > - MI_NOOP); > - if (IS_ERR(this)) { > - err = PTR_ERR(this); > - goto err_wedged; > - } > - > - /* Disable NEWCLIENT promotion */ > - __i915_active_fence_set(&i915_request_timeline(this)->last_request, > - &dummy->fence); > - > - rq[i] = i915_request_get(this); > - i915_request_add(this); > - } > - > - dummy_request_free(dummy); > - > - GEM_BUG_ON(i915_request_completed(rq[0])); > - if (!igt_wait_for_spinner(&client[0].spin, rq[0])) { > - pr_err("%s: First client failed to start\n", > - engine->name); > - goto err_wedged; > - } > - GEM_BUG_ON(!i915_request_started(rq[0])); > - > - if (i915_request_wait(rq[depth], > - I915_WAIT_PRIORITY, > - 1) != -ETIME) { > - pr_err("%s: Waiter depth:%d completed!\n", > - engine->name, depth); > - goto err_wedged; > - } > - > - for (i = 0; i < ARRAY_SIZE(client); i++) { > - igt_spinner_end(&client[i].spin); > - i915_request_put(rq[i]); > - rq[i] = NULL; > - } > - > - if (igt_flush_test(gt->i915)) > - goto err_wedged; > - > - if (engine->execlists.preempt_hang.count) { > - pr_err("%s: Preemption recorded x%d, depth %d; should have been suppressed!\n", > - engine->name, > - engine->execlists.preempt_hang.count, > - depth); > - err = -EINVAL; > - goto err_client_3; > - } > - } > - } > - > - err = 0; > -err_client_3: > - preempt_client_fini(&client[3]); > -err_client_2: > - preempt_client_fini(&client[2]); > -err_client_1: > - preempt_client_fini(&client[1]); > -err_client_0: > - preempt_client_fini(&client[0]); > - return err; > - > -err_wedged: > - for (i = 0; i < ARRAY_SIZE(client); i++) { > - igt_spinner_end(&client[i].spin); > - i915_request_put(rq[i]); > - } > - intel_gt_set_wedged(gt); > - err = -EIO; > - goto err_client_3; > -} > - > static int live_chain_preempt(void *arg) > { > struct intel_gt *gt = arg; > @@ -4592,7 +4415,6 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) > SUBTEST(live_nopreempt), > SUBTEST(live_preempt_cancel), > SUBTEST(live_suppress_self_preempt), > - SUBTEST(live_suppress_wait_preempt), > SUBTEST(live_chain_preempt), > SUBTEST(live_preempt_gang), > SUBTEST(live_preempt_timeout), > From tzimmermann at suse.de Thu Jun 11 12:04:03 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Thu, 11 Jun 2020 14:04:03 +0200 Subject: [Intel-gfx] [PATCH 57/59] drm/ast: Use managed pci functions In-Reply-To: <20200415074034.175360-58-daniel.vetter@ffwll.ch> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-58-daniel.vetter@ffwll.ch> Message-ID: <b14b78e4-556d-9e52-bdfd-7c4229392ed9@suse.de> Hi Am 15.04.20 um 09:40 schrieb Daniel Vetter: > Allows us to remove a bit of cleanup code. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Dave Airlie <airlied at redhat.com> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: Gerd Hoffmann <kraxel at redhat.com> > Cc: Daniel Vetter <daniel.vetter at ffwll.ch> > Cc: Emil Velikov <emil.velikov at collabora.com> > Cc: "Noralf Tr?nnes" <noralf at tronnes.org> > Cc: Sam Ravnborg <sam at ravnborg.org> > Cc: "Christian K?nig" <christian.koenig at amd.com> > Cc: "Y.C. Chen" <yc_chen at aspeedtech.com> Reviewed-by: Thomas Zimmermann <tzimmermann at suse.de> Thanks for answering my questions. Sorry for never getting back to it. Best regards Thomas > --- > drivers/gpu/drm/ast/ast_drv.c | 10 +++------- > drivers/gpu/drm/ast/ast_main.c | 3 --- > 2 files changed, 3 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c > index b7ba22dddcad..48a9cc4e080a 100644 > --- a/drivers/gpu/drm/ast/ast_drv.c > +++ b/drivers/gpu/drm/ast/ast_drv.c > @@ -91,15 +91,13 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) > > ast_kick_out_firmware_fb(pdev); > > - ret = pci_enable_device(pdev); > + ret = pcim_enable_device(pdev); > if (ret) > return ret; > > dev = drm_dev_alloc(&driver, &pdev->dev); > - if (IS_ERR(dev)) { > - ret = PTR_ERR(dev); > - goto err_pci_disable_device; > - } > + if (IS_ERR(dev)) > + return PTR_ERR(dev); > > dev->pdev = pdev; > pci_set_drvdata(pdev, dev); > @@ -120,8 +118,6 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) > ast_driver_unload(dev); > err_drm_dev_put: > drm_dev_put(dev); > -err_pci_disable_device: > - pci_disable_device(pdev); > return ret; > > } > diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c > index e5398e3dabe7..1b35728ad871 100644 > --- a/drivers/gpu/drm/ast/ast_main.c > +++ b/drivers/gpu/drm/ast/ast_main.c > @@ -531,8 +531,5 @@ void ast_driver_unload(struct drm_device *dev) > drm_mode_config_cleanup(dev); > > ast_mm_fini(ast); > - if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET) > - pci_iounmap(dev->pdev, ast->ioregs); > - pci_iounmap(dev->pdev, ast->regs); > kfree(ast); > } > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N?rnberg, Germany (HRB 36809, AG N?rnberg) Gesch?ftsf?hrer: Felix Imend?rffer -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200611/20b10bfb/attachment.sig> From patchwork at emeril.freedesktop.org Thu Jun 11 12:19:08 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 12:19:08 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev3=29?= In-Reply-To: <20200610191232.11620-1-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> Message-ID: <159187794861.22715.17764705429208843004@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev3) URL : https://patchwork.freedesktop.org/series/68081/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8611_full -> Patchwork_17922_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17922_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17922_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17922_full: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - shard-kbl: NOTRUN -> ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5]) ([i915#1569] / [i915#1611] / [i915#1687] / [i915#192] / [i915#193] / [i915#194]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at runner@aborted.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at runner@aborted.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at runner@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at runner@aborted.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at runner@aborted.html - shard-apl: NOTRUN -> ([FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10]) ([fdo#109271] / [i915#1610] / [i915#1611]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl1/igt at runner@aborted.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl1/igt at runner@aborted.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl4/igt at runner@aborted.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl1/igt at runner@aborted.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl4/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17922_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#1528]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl10/igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd.html * igt at gem_workarounds@suspend-resume: - shard-kbl: [PASS][13] -> [INCOMPLETE][14] ([i915#155] / [i915#180]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt at gem_workarounds@suspend-resume.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at gem_workarounds@suspend-resume.html * igt at gen9_exec_parse@allowed-all: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1436] / [i915#716]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk9/igt at gen9_exec_parse@allowed-all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-glk7/igt at gen9_exec_parse@allowed-all.html * igt at i915_module_load@reload: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#402]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb3/igt at i915_module_load@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-tglb1/igt at i915_module_load@reload.html * igt at i915_pm_rc6_residency@rc6-fence: - shard-hsw: [PASS][19] -> [WARN][20] ([i915#1519]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-hsw1/igt at i915_pm_rc6_residency@rc6-fence.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-hsw6/igt at i915_pm_rc6_residency@rc6-fence.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][21] -> [INCOMPLETE][22] ([i915#180]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl1/igt at i915_suspend@sysfs-reader.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl4/igt at i915_suspend@sysfs-reader.html * igt at kms_atomic@atomic-invalid-params: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#95]) +11 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl8/igt at kms_atomic@atomic-invalid-params.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl7/igt at kms_atomic@atomic-invalid-params.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl1/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#93] / [i915#95]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl3/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at kms_cursor_edge_walk@pipe-a-128x128-bottom-edge.html * igt at kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][29] -> [FAIL][30] ([i915#96]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-hsw4/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-hsw8/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html * igt at kms_cursor_legacy@cursora-vs-flipa-varying-size: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +10 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl1/igt at kms_cursor_legacy@cursora-vs-flipa-varying-size.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl3/igt at kms_cursor_legacy@cursora-vs-flipa-varying-size.html * igt at kms_cursor_legacy@pipe-c-single-bo: - shard-hsw: [PASS][33] -> [INCOMPLETE][34] ([i915#61]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-hsw6/igt at kms_cursor_legacy@pipe-c-single-bo.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-hsw4/igt at kms_cursor_legacy@pipe-c-single-bo.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [PASS][35] -> [FAIL][36] ([i915#79]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl9/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite: - shard-tglb: [PASS][37] -> [SKIP][38] ([i915#668]) +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html * igt at kms_plane_scaling@pipe-c-scaler-with-clipping-clamping: - shard-iclb: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-iclb3/igt at kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441]) +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-iclb3/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend: - shard-skl: [PASS][43] -> [INCOMPLETE][44] ([i915#69]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl6/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl6/igt at kms_vblank@pipe-c-ts-continuation-dpms-suspend.html * igt at perf@blocking-parameterized: - shard-hsw: [PASS][45] -> [FAIL][46] ([i915#1542]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-hsw2/igt at perf@blocking-parameterized.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-hsw6/igt at perf@blocking-parameterized.html * igt at sysfs_heartbeat_interval@mixed at vecs0: - shard-skl: [PASS][47] -> [FAIL][48] ([i915#1731]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl3/igt at sysfs_heartbeat_interval@mixed at vecs0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl1/igt at sysfs_heartbeat_interval@mixed at vecs0.html #### Possible fixes #### * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_ctx_param@root-set: - shard-apl: [DMESG-WARN][51] ([i915#95]) -> [PASS][52] +6 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt at gem_ctx_param@root-set.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl8/igt at gem_ctx_param@root-set.html * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][53] ([i915#1936]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt at gem_exec_balancer@sliced.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-tglb7/igt at gem_exec_balancer@sliced.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][55] ([i915#82]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-snb6/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at i915_suspend@debugfs-reader: - shard-kbl: [FAIL][57] ([fdo#103375]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl7/igt at i915_suspend@debugfs-reader.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl3/igt at i915_suspend@debugfs-reader.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][59] ([i915#118] / [i915#95]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-glk1/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-skl: [FAIL][61] ([i915#54]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl8/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-tglb: [DMESG-WARN][63] ([i915#128]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb2/igt at kms_cursor_legacy@pipe-b-torture-move.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-tglb5/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled: - shard-skl: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +14 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl8/igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl5/igt at kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html * igt at kms_flip@busy-flip at b-edp1: - shard-skl: [FAIL][67] ([i915#275]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl5/igt at kms_flip@busy-flip at b-edp1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl8/igt at kms_flip@busy-flip at b-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-iclb: [FAIL][69] ([i915#79]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb7/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-iclb4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@plain-flip-ts-check at a-dp1: - shard-kbl: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_flip@plain-flip-ts-check at a-dp1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl7/igt at kms_flip@plain-flip-ts-check at a-dp1.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [INCOMPLETE][73] ([i915#155]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-glk: [DMESG-WARN][75] ([i915#1982]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-glk1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][77] ([fdo#108145] / [i915#265]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][79] ([i915#173]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt at kms_psr@no_drrs.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-iclb2/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][81] ([fdo#109441]) -> [PASS][82] +3 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_setmode@basic: - shard-skl: [FAIL][83] ([i915#31]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-skl1/igt at kms_setmode@basic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-skl3/igt at kms_setmode@basic.html * igt at perf@polling-parameterized: - shard-hsw: [FAIL][85] ([i915#1542]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-hsw6/igt at perf@polling-parameterized.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-hsw4/igt at perf@polling-parameterized.html * igt at perf_pmu@module-unload: - shard-iclb: [DMESG-WARN][87] ([i915#1982]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb5/igt at perf_pmu@module-unload.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-iclb7/igt at perf_pmu@module-unload.html * igt at perf_pmu@other-init-3: - shard-tglb: [DMESG-WARN][89] ([i915#402]) -> [PASS][90] +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb6/igt at perf_pmu@other-init-3.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-tglb1/igt at perf_pmu@other-init-3.html * igt at syncobj_wait@single-wait-all-for-submit-signaled: - shard-tglb: [TIMEOUT][91] -> [PASS][92] +2 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb5/igt at syncobj_wait@single-wait-all-for-submit-signaled.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-tglb7/igt at syncobj_wait@single-wait-all-for-submit-signaled.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-glk: [TIMEOUT][93] ([i915#1958]) -> [INCOMPLETE][94] ([i915#1958] / [i915#58] / [k.org#198133]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-glk5/igt at gem_exec_reloc@basic-concurrent16.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-glk8/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][95] ([i915#454]) -> [SKIP][96] ([i915#468]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-tglb7/igt at i915_pm_dc@dc6-dpms.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][97] ([i915#1515]) -> [WARN][98] ([i915#1515]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-iclb2/igt at i915_pm_rc6_residency@rc6-idle.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-iclb1/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic: - shard-apl: [TIMEOUT][99] ([i915#1319] / [i915#1635]) -> [TIMEOUT][100] ([i915#1319]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt at kms_content_protection@atomic.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl1/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][101] ([i915#1319]) -> [FAIL][102] ([fdo#110321] / [fdo#110336]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl1/igt at kms_content_protection@atomic-dpms.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl6/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][103] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][104] ([i915#1319] / [i915#1635]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl6/igt at kms_content_protection@legacy.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl4/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][105] ([i915#1319] / [i915#1958]) -> [TIMEOUT][106] ([i915#1319]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_content_protection@lic.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl7/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][107] ([i915#1319] / [i915#1958]) -> [DMESG-FAIL][108] ([fdo#110321] / [i915#95]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl4/igt at kms_content_protection@srm.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl2/igt at kms_content_protection@srm.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][109] ([i915#180]) -> [INCOMPLETE][110] ([i915#155] / [i915#180]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][111] ([i915#95]) -> [INCOMPLETE][112] ([i915#180]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8611/shard-apl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/shard-apl1/igt at kms_frontbuffer_tracking@fbc-suspend.html [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1519]: https://gitlab.freedesktop.org/drm/intel/issues/1519 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1687]: https://gitlab.freedesktop.org/drm/intel/issues/1687 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#275]: https://gitlab.freedesktop.org/drm/intel/issues/275 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8611 -> Patchwork_17922 CI-20190529: 20190529 CI_DRM_8611: b87354483fa40fef86da19ade9bfe9349f0cf6d5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17922: 0903ebe28a8fb9c912916613977b2e77d83eac8c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17922/index.html From chris at chris-wilson.co.uk Thu Jun 11 12:30:37 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 13:30:37 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/vblank: Estimate sample time Message-ID: <20200611123038.91855-1-chris@chris-wilson.co.uk> Since we have a precise start/end time for the sample, the actual time the HW was read back is within that interval, and more likely closer to the mean of the interval. Use the mean sample time when estimating the vblank time. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/drm_vblank.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index da7b0b0c1090..79a5461d3773 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -710,15 +710,18 @@ drm_crtc_vblank_helper_get_vblank_timestamp_internal( delta_ns = div_s64(1000000LL * (vpos * mode->crtc_htotal + hpos), mode->crtc_clock); + /* Estimate when the sample was taken */ + stime += (etime - stime) >> 2; + /* Subtract time delta from raw timestamp to get final * vblank_time timestamp for end of vblank. */ - *vblank_time = ktime_sub_ns(etime, delta_ns); + *vblank_time = ktime_sub_ns(stime, delta_ns); if (!drm_debug_enabled(DRM_UT_VBL)) return true; - ts_etime = ktime_to_timespec64(etime); + ts_etime = ktime_to_timespec64(stime); ts_vblank_time = ktime_to_timespec64(*vblank_time); DRM_DEBUG_VBL("crtc %u : v p(%d,%d)@ %lld.%06ld -> %lld.%06ld [e %d us, %d rep]\n", -- 2.27.0 From chris at chris-wilson.co.uk Thu Jun 11 12:30:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 13:30:38 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Tighten timestamp around vblank sampling In-Reply-To: <20200611123038.91855-1-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> Message-ID: <20200611123038.91855-2-chris@chris-wilson.co.uk> Tighten the timestamp queries before/after the register read so that we have less uncertainity for when the read actually took place. This is more apt for the older generations where it is not a simple single register read. Whether we are able to discern an improvement in our sampling accuracy remains to be seen. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 57 ++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8e823ba25f5f..9c44df8ecce7 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -713,7 +713,9 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc) * This function will use Framestamp and current * timestamp registers to calculate the scanline. */ -static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) +static u32 +__intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc, + ktime_t *stime, ktime_t *etime) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_vblank_crtc *vblank = @@ -737,6 +739,9 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) * pipe frame time stamp. The time stamp value * is sampled at every start of vertical blank. */ + if (stime) + *stime = ktime_get(); + scan_prev_time = intel_de_read_fw(dev_priv, PIPE_FRMTMSTMP(crtc->pipe)); @@ -746,6 +751,9 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) */ scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); + if (etime) + *etime = ktime_get(); + scan_post_time = intel_de_read_fw(dev_priv, PIPE_FRMTMSTMP(crtc->pipe)); } while (scan_post_time != scan_prev_time); @@ -762,7 +770,8 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) * intel_de_read_fw(), only for fast reads of display block, no need for * forcewake etc. */ -static int __intel_get_crtc_scanline(struct intel_crtc *crtc) +static int __intel_get_crtc_scanline(struct intel_crtc *crtc, + ktime_t *stime, ktime_t *etime) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -771,23 +780,34 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) enum pipe pipe = crtc->pipe; int position, vtotal; - if (!crtc->active) + if (!crtc->active) { + if (stime) + *stime = 0; + if (etime) + *etime = 0; return -1; + } vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; mode = &vblank->hwmode; if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) - return __intel_get_crtc_scanline_from_timestamp(crtc); + return __intel_get_crtc_scanline_from_timestamp(crtc, + stime, + etime); vtotal = mode->crtc_vtotal; if (mode->flags & DRM_MODE_FLAG_INTERLACE) vtotal /= 2; + if (stime) + *stime = ktime_get(); if (IS_GEN(dev_priv, 2)) position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; else position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + if (etime) + *etime = ktime_get(); /* * On HSW, the DSL reg (0x70000) appears to return 0 if we @@ -806,7 +826,13 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) for (i = 0; i < 100; i++) { udelay(1); + + if (stime) + *stime = ktime_get(); temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; + if (etime) + *etime = ktime_get(); + if (temp != position) { position = temp; break; @@ -866,21 +892,25 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ - /* Get optional system timestamp before query. */ - if (stime) - *stime = ktime_get(); - if (use_scanline_counter) { /* No obvious pixelcount register. Only query vertical * scanout position from Display scan line register. */ - position = __intel_get_crtc_scanline(crtc); + position = __intel_get_crtc_scanline(crtc, stime, etime); } else { + /* Get optional system timestamp before query. */ + if (stime) + *stime = ktime_get(); + /* Have access to pixelcount since start of frame. * We can split this into vertical and horizontal * scanout position. */ - position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; + position = intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)); + + /* Get optional system timestamp after query. */ + if (etime) + *etime = ktime_get(); /* convert to pixel counts */ vbl_start *= htotal; @@ -896,6 +926,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, * matches how the scanline counter based position works since * the scanline counter doesn't count the two half lines. */ + position = (position & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; if (position >= vtotal) position = vtotal - 1; @@ -911,10 +942,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, position = (position + htotal - hsync_start) % vtotal; } - /* Get optional system timestamp after query. */ - if (etime) - *etime = ktime_get(); - /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -956,7 +983,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) int position; spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - position = __intel_get_crtc_scanline(crtc); + position = __intel_get_crtc_scanline(crtc, NULL, NULL); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); return position; -- 2.27.0 From chris at chris-wilson.co.uk Thu Jun 11 12:34:28 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 13:34:28 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/vblank: Estimate sample time In-Reply-To: <20200611123038.91855-1-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> Message-ID: <159187886883.1506.13319708113042548833@build.alporthouse.com> Quoting Chris Wilson (2020-06-11 13:30:37) > Since we have a precise start/end time for the sample, the actual time > the HW was read back is within that interval, and more likely closer to > the mean of the interval. Use the mean sample time when estimating the > vblank time. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/drm_vblank.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c > index da7b0b0c1090..79a5461d3773 100644 > --- a/drivers/gpu/drm/drm_vblank.c > +++ b/drivers/gpu/drm/drm_vblank.c > @@ -710,15 +710,18 @@ drm_crtc_vblank_helper_get_vblank_timestamp_internal( > delta_ns = div_s64(1000000LL * (vpos * mode->crtc_htotal + hpos), > mode->crtc_clock); > > + /* Estimate when the sample was taken */ > + stime += (etime - stime) >> 2; /2 != >>2 -Chris From chris at chris-wilson.co.uk Thu Jun 11 12:34:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 13:34:47 +0100 Subject: [Intel-gfx] [PATCH v2] drm/vblank: Estimate sample time In-Reply-To: <20200611123038.91855-1-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> Message-ID: <20200611123447.92171-1-chris@chris-wilson.co.uk> Since we have a precise start/end time for the sample, the actual time the HW was read back is within that interval, and more likely closer to the mean of the interval. Use the mean sample time when estimating the vblank time. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/drm_vblank.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index da7b0b0c1090..a7043d268cca 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -710,15 +710,18 @@ drm_crtc_vblank_helper_get_vblank_timestamp_internal( delta_ns = div_s64(1000000LL * (vpos * mode->crtc_htotal + hpos), mode->crtc_clock); + /* Estimate when the sample was taken */ + stime += (etime - stime) >> 1; + /* Subtract time delta from raw timestamp to get final * vblank_time timestamp for end of vblank. */ - *vblank_time = ktime_sub_ns(etime, delta_ns); + *vblank_time = ktime_sub_ns(stime, delta_ns); if (!drm_debug_enabled(DRM_UT_VBL)) return true; - ts_etime = ktime_to_timespec64(etime); + ts_etime = ktime_to_timespec64(stime); ts_vblank_time = ktime_to_timespec64(*vblank_time); DRM_DEBUG_VBL("crtc %u : v p(%d,%d)@ %lld.%06ld -> %lld.%06ld [e %d us, %d rep]\n", -- 2.27.0 From chris at chris-wilson.co.uk Thu Jun 11 12:36:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 13:36:33 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Tighten timestamp around vblank sampling In-Reply-To: <20200611123038.91855-2-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> <20200611123038.91855-2-chris@chris-wilson.co.uk> Message-ID: <159187899353.1506.17977517184833304797@build.alporthouse.com> Quoting Chris Wilson (2020-06-11 13:30:38) > Tighten the timestamp queries before/after the register read so that we > have less uncertainity for when the read actually took place. This is > more apt for the older generations where it is not a simple single > register read. Whether we are able to discern an improvement in our > sampling accuracy remains to be seen. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 57 ++++++++++++++++++++++++--------- > 1 file changed, 42 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 8e823ba25f5f..9c44df8ecce7 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -713,7 +713,9 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc) > * This function will use Framestamp and current > * timestamp registers to calculate the scanline. > */ > -static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) > +static u32 > +__intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc, > + ktime_t *stime, ktime_t *etime) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct drm_vblank_crtc *vblank = > @@ -737,6 +739,9 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) > * pipe frame time stamp. The time stamp value > * is sampled at every start of vertical blank. > */ > + if (stime) > + *stime = ktime_get(); > + > scan_prev_time = intel_de_read_fw(dev_priv, > PIPE_FRMTMSTMP(crtc->pipe)); > > @@ -746,6 +751,9 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) > */ > scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); > > + if (etime) > + *etime = ktime_get(); I guess with PREEMPT_RT and sleeping spinlocks, these timestamps + intel_de_read_fw deserve to be within preempt_disable(). -Chris From imre.deak at intel.com Thu Jun 11 12:47:39 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 11 Jun 2020 15:47:39 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BRESEND=2Cv3=2C1/3=5D_drm/i915/dp=5Fmst=3A_?= =?utf-8?q?Fix_disabling_MST_on_a_port_=28rev6=29?= In-Reply-To: <159136523293.18507.17008252253062518394@emeril.freedesktop.org> References: <20200603211040.8190-1-imre.deak@intel.com> <159136523293.18507.17008252253062518394@emeril.freedesktop.org> Message-ID: <20200611124739.GD17512@ideak-desk.fi.intel.com> On Fri, Jun 05, 2020 at 01:53:52PM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6) > URL : https://patchwork.freedesktop.org/series/77969/ > State : success Thanks for the reviews, pushed patch 1 to -dinq and patches 2,3 to drm-misc-next. > > == Summary == > > CI Bug Log - changes from CI_DRM_8590_full -> Patchwork_17882_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17882_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_whisper@basic-forked-all: > - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk7/igt at gem_exec_whisper@basic-forked-all.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk2/igt at gem_exec_whisper@basic-forked-all.html > > * igt at gem_mmap_gtt@cpuset-big-copy-odd: > - shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > > * igt at gem_workarounds@suspend-resume: > - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_workarounds@suspend-resume.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_workarounds@suspend-resume.html > > * igt at kms_big_fb@linear-32bpp-rotate-180: > - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +9 similar issues > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_big_fb@linear-32bpp-rotate-180.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_big_fb@linear-32bpp-rotate-180.html > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) +1 similar issue > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html > > * igt at kms_big_fb@x-tiled-16bpp-rotate-0: > - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk5/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk4/igt at kms_big_fb@x-tiled-16bpp-rotate-0.html > > * igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +17 similar issues > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html > > * igt at kms_cursor_crc@pipe-c-cursor-suspend: > - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +4 similar issues > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > > * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: > - shard-snb: [PASS][17] -> [TIMEOUT][18] ([i915#1958]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move: > - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html > > * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#49]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt at kms_plane_lowres@pipe-a-tiling-x: > - shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271]) +1 similar issue > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at kms_plane_lowres@pipe-a-tiling-x.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_lowres@pipe-a-tiling-x.html > > * igt at kms_psr@psr2_cursor_blt: > - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +3 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb4/igt at kms_psr@psr2_cursor_blt.html > > * igt at kms_universal_plane@universal-plane-gen9-features-pipe-c: > - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-c.html > > * igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted: > - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#402]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb6/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb7/igt at syncobj_wait@invalid-multi-wait-unsubmitted-submitted.html > > > #### Possible fixes #### > > * {igt at gem_ctx_isolation@preservation-s3 at rcs0}: > - shard-apl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +2 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html > > * igt at gem_exec_whisper@basic-queues-forked-all: > - shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk9/igt at gem_exec_whisper@basic-queues-forked-all.html > > * igt at gen9_exec_parse@allowed-all: > - shard-kbl: [DMESG-WARN][37] ([i915#1436] / [i915#716]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl1/igt at gen9_exec_parse@allowed-all.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at gen9_exec_parse@allowed-all.html > > * igt at i915_suspend@debugfs-reader: > - shard-kbl: [INCOMPLETE][39] ([i915#155]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at i915_suspend@debugfs-reader.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl6/igt at i915_suspend@debugfs-reader.html > > * igt at kms_color@pipe-c-ctm-red-to-blue: > - shard-kbl: [DMESG-WARN][41] ([i915#93] / [i915#95]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_color@pipe-c-ctm-red-to-blue.html > > * igt at kms_color@pipe-d-ctm-0-5: > - shard-tglb: [DMESG-WARN][43] ([i915#1149] / [i915#402]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-tglb2/igt at kms_color@pipe-d-ctm-0-5.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-tglb1/igt at kms_color@pipe-d-ctm-0-5.html > > * igt at kms_cursor_legacy@all-pipes-torture-move: > - shard-skl: [DMESG-WARN][45] ([i915#128]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_cursor_legacy@all-pipes-torture-move.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_cursor_legacy@all-pipes-torture-move.html > > * {igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2}: > - shard-glk: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-glk6/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-glk8/igt at kms_flip@2x-flip-vs-suspend at ab-hdmi-a1-hdmi-a2.html > > * igt at kms_flip_tiling@flip-x-tiled: > - shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +26 similar issues > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl7/igt at kms_flip_tiling@flip-x-tiled.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_flip_tiling@flip-x-tiled.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: > - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +3 similar issues > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > > * igt at kms_plane@plane-panning-bottom-right-pipe-c-planes: > - shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +2 similar issues > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl6/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl5/igt at kms_plane@plane-panning-bottom-right-pipe-c-planes.html > > * igt at kms_psr@psr2_primary_mmap_cpu: > - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +2 similar issues > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html > > * igt at kms_setmode@basic: > - shard-apl: [FAIL][59] ([i915#31]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_setmode@basic.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_setmode@basic.html > - shard-kbl: [FAIL][61] ([i915#31]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl6/igt at kms_setmode@basic.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_setmode@basic.html > > * {igt at perf@polling-parameterized}: > - shard-hsw: [FAIL][63] ([i915#1542]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-hsw6/igt at perf@polling-parameterized.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-hsw5/igt at perf@polling-parameterized.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-snb: [SKIP][65] ([fdo#109271]) -> [INCOMPLETE][66] ([i915#82]) +1 similar issue > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb5/igt at i915_pm_dc@dc3co-vpb-simulation.html > - shard-iclb: [SKIP][67] ([i915#658]) -> [SKIP][68] ([i915#588]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at kms_content_protection@atomic: > - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl6/igt at kms_content_protection@atomic.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl3/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@legacy: > - shard-kbl: [DMESG-FAIL][71] ([fdo#110321]) -> [TIMEOUT][72] ([i915#1319] / [i915#1958]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl3/igt at kms_content_protection@legacy.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl4/igt at kms_content_protection@legacy.html > > * igt at kms_content_protection@lic: > - shard-apl: [DMESG-FAIL][73] ([fdo#110321] / [i915#95]) -> [TIMEOUT][74] ([i915#1319] / [i915#1635]) +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl2/igt at kms_content_protection@lic.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl1/igt at kms_content_protection@lic.html > > * igt at kms_content_protection@srm: > - shard-kbl: [DMESG-FAIL][75] ([fdo#110321] / [i915#95]) -> [TIMEOUT][76] ([i915#1319]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl2/igt at kms_content_protection@srm.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl3/igt at kms_content_protection@srm.html > > * igt at kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][77] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][78] ([i915#93] / [i915#95]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html > - shard-apl: [DMESG-WARN][79] ([i915#180] / [i915#95]) -> [DMESG-WARN][80] ([i915#95]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [DMESG-WARN][81] ([i915#1982]) -> [DMESG-FAIL][82] ([fdo#108145] / [i915#1982]) > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: > - shard-snb: [SKIP][83] ([fdo#109271]) -> [TIMEOUT][84] ([i915#1958]) +1 similar issue > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8590/shard-snb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/shard-snb1/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8590 -> Patchwork_17882 > > CI-20190529: 20190529 > CI_DRM_8590: 91c6f0274b54c89679cd23f6fc65e9fe5922971f @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5695: 53e8c878a6fb5708e63c99403691e8960b86ea9c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17882: 23fe5e3ae83585e3d4ad9ecdfea368dd42ff6dfb @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17882/index.html From imre.deak at intel.com Thu Jun 11 12:51:24 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 11 Jun 2020 15:51:24 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/dp=5Fmst=3A_Fix_the_DDC_I2C_dev?= =?utf-8?q?ice_unregistration_of_an_MST_port_=28rev2=29?= In-Reply-To: <159186517668.22716.10635471487472572534@emeril.freedesktop.org> References: <20200607212522.16935-1-imre.deak@intel.com> <159186517668.22716.10635471487472572534@emeril.freedesktop.org> Message-ID: <20200611125124.GE17512@ideak-desk.fi.intel.com> On Thu, Jun 11, 2020 at 08:46:16AM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [1/3] drm/dp_mst: Fix the DDC I2C device unregistration of an MST port (rev2) > URL : https://patchwork.freedesktop.org/series/78100/ > State : success Thanks for the review, the patchset is pushed to drm-misc-next. > > == Summary == > > CI Bug Log - changes from CI_DRM_8608_full -> Patchwork_17919_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17919_full: > > ### Piglit changes ### > > #### Possible regressions #### > > * spec at glsl-4.20@execution at conversion@frag-conversion-implicit-mat4-dmat4-zero-sign (NEW): > - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/pig-icl-1065g7/spec at glsl-4.20@execution at conversion@frag-conversion-implicit-mat4-dmat4-zero-sign.html > > * spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3-dmat3-zero-sign (NEW): > - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] +4 similar issues > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/pig-icl-1065g7/spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3-dmat3-zero-sign.html > > > New tests > --------- > > New tests have been introduced between CI_DRM_8608_full and Patchwork_17919_full: > > ### New Piglit tests (6) ### > > * spec at glsl-4.00@execution at built-in-functions@gs-op-div-dmat4x3-dmat4x3: > - Statuses : 1 crash(s) > - Exec time: [98.33] s > > * spec at glsl-4.20@execution at conversion@frag-conversion-implicit-mat4-dmat4-zero-sign: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at glsl-4.20@execution at conversion@geom-conversion-implicit-mat3-dmat3-zero-sign: > - Statuses : 1 crash(s) > - Exec time: [15.54] s > > * spec at glsl-4.20@execution at conversion@geom-conversion-implicit-mat4-dmat4-zero-sign: > - Statuses : 1 crash(s) > - Exec time: [57.24] s > > * spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3-dmat3-zero-sign: > - Statuses : 1 crash(s) > - Exec time: [3.59] s > > * spec at glsl-4.20@execution at conversion@vert-conversion-implicit-mat3x4-dmat3x4-zero-sign: > - Statuses : 1 crash(s) > - Exec time: [25.06] s > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17919_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_schedule@implicit-boths at bcs0: > - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-snb4/igt at gem_exec_schedule@implicit-boths at bcs0.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-snb2/igt at gem_exec_schedule@implicit-boths at bcs0.html > > * igt at gem_exec_suspend@basic-s3: > - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +3 similar issues > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at gem_exec_suspend@basic-s3.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl2/igt at gem_exec_suspend@basic-s3.html > > * igt at gem_exec_whisper@basic-forked-all: > - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk4/igt at gem_exec_whisper@basic-forked-all.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk9/igt at gem_exec_whisper@basic-forked-all.html > > * igt at i915_suspend@sysfs-reader: > - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#69]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl2/igt at i915_suspend@sysfs-reader.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl6/igt at i915_suspend@sysfs-reader.html > > * igt at kms_big_fb@y-tiled-64bpp-rotate-0: > - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk2/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > > * igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +16 similar issues > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([i915#54] / [i915#95]) +1 similar issue > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html > > * igt at kms_cursor_crc@pipe-a-cursor-suspend: > - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +8 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html > > * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: > - shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl3/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html > > * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: > - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > > * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: > - shard-skl: [PASS][23] -> [FAIL][24] ([i915#1928]) > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html > > * igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1: > - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +10 similar issues > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl4/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl10/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: > - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +1 similar issue > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: > - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +1 similar issue > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb7/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html > > * igt at kms_psr@psr2_cursor_render: > - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb2/igt at kms_psr@psr2_cursor_render.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb5/igt at kms_psr@psr2_cursor_render.html > > * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: > - shard-hsw: [PASS][37] -> [INCOMPLETE][38] ([i915#61]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-hsw6/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-hsw2/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html > > * igt at perf@blocking-parameterized: > - shard-tglb: [PASS][39] -> [FAIL][40] ([i915#1542]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb3/igt at perf@blocking-parameterized.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb8/igt at perf@blocking-parameterized.html > > * igt at sw_sync@sync_multi_consumer: > - shard-tglb: [PASS][41] -> [DMESG-WARN][42] ([i915#402]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb2/igt at sw_sync@sync_multi_consumer.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb1/igt at sw_sync@sync_multi_consumer.html > > > #### Possible fixes #### > > * igt at gem_exec_create@madvise: > - shard-glk: [DMESG-WARN][43] ([i915#118] / [i915#95]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk1/igt at gem_exec_create@madvise.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk7/igt at gem_exec_create@madvise.html > > * igt at gem_exec_reloc@basic-concurrent0: > - shard-glk: [FAIL][45] ([i915#1930]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html > > * igt at gem_mmap_gtt@basic-small-copy-xy: > - shard-iclb: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb2/igt at gem_mmap_gtt@basic-small-copy-xy.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb5/igt at gem_mmap_gtt@basic-small-copy-xy.html > > * igt at gen9_exec_parse@allowed-single: > - shard-skl: [DMESG-WARN][49] ([i915#1436] / [i915#716]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl10/igt at gen9_exec_parse@allowed-single.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl2/igt at gen9_exec_parse@allowed-single.html > > * igt at i915_suspend@fence-restore-untiled: > - shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl1/igt at i915_suspend@fence-restore-untiled.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl7/igt at i915_suspend@fence-restore-untiled.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: > - shard-kbl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl6/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > - shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk1/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk7/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html > > * igt at kms_cursor_crc@pipe-c-cursor-suspend: > - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +3 similar issues > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html > > * igt at kms_cursor_edge_walk@pipe-c-64x64-top-edge: > - shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +3 similar issues > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl1/igt at kms_cursor_edge_walk@pipe-c-64x64-top-edge.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl2/igt at kms_cursor_edge_walk@pipe-c-64x64-top-edge.html > > * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: > - shard-apl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62] +3 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * igt at kms_frontbuffer_tracking@psr-suspend: > - shard-skl: [INCOMPLETE][63] ([i915#123] / [i915#69]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl8/igt at kms_frontbuffer_tracking@psr-suspend.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl10/igt at kms_frontbuffer_tracking@psr-suspend.html > > * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] +1 similar issue > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > > * igt at kms_psr@psr2_cursor_plane_onoff: > - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb6/igt at kms_psr@psr2_cursor_plane_onoff.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html > > * igt at kms_setmode@basic: > - shard-glk: [FAIL][69] ([i915#31]) -> [PASS][70] > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-glk9/igt at kms_setmode@basic.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-glk4/igt at kms_setmode@basic.html > > * igt at kms_vblank@pipe-c-query-busy-hang: > - shard-tglb: [DMESG-WARN][71] ([i915#402]) -> [PASS][72] +2 similar issues > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb2/igt at kms_vblank@pipe-c-query-busy-hang.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb1/igt at kms_vblank@pipe-c-query-busy-hang.html > > * igt at perf@blocking-parameterized: > - shard-iclb: [FAIL][73] ([i915#1542]) -> [PASS][74] > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb4/igt at perf@blocking-parameterized.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb8/igt at perf@blocking-parameterized.html > - shard-hsw: [FAIL][75] ([i915#1542]) -> [PASS][76] +1 similar issue > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-hsw6/igt at perf@blocking-parameterized.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-hsw1/igt at perf@blocking-parameterized.html > > * igt at syncobj_wait@invalid-wait-illegal-handle: > - shard-apl: [DMESG-WARN][77] ([i915#95]) -> [PASS][78] +10 similar issues > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl2/igt at syncobj_wait@invalid-wait-illegal-handle.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl2/igt at syncobj_wait@invalid-wait-illegal-handle.html > > > #### Warnings #### > > * igt at gem_exec_reloc@basic-concurrent16: > - shard-snb: [FAIL][79] ([i915#1930]) -> [TIMEOUT][80] ([i915#1958]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html > > * igt at i915_pm_dc@dc6-psr: > - shard-tglb: [FAIL][81] ([i915#454]) -> [SKIP][82] ([i915#468]) > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-tglb3/igt at i915_pm_dc@dc6-psr.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-tglb2/igt at i915_pm_dc@dc6-psr.html > - shard-skl: [DMESG-FAIL][83] ([i915#1982]) -> [FAIL][84] ([i915#454]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-skl8/igt at i915_pm_dc@dc6-psr.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-skl1/igt at i915_pm_dc@dc6-psr.html > > * igt at i915_pm_rc6_residency@rc6-idle: > - shard-iclb: [FAIL][85] ([i915#1515]) -> [WARN][86] ([i915#1515]) > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-iclb8/igt at i915_pm_rc6_residency@rc6-idle.html > > * igt at kms_big_fb@yf-tiled-addfb: > - shard-snb: [SKIP][87] ([fdo#109271]) -> [TIMEOUT][88] ([i915#1958]) > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-snb2/igt at kms_big_fb@yf-tiled-addfb.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-snb6/igt at kms_big_fb@yf-tiled-addfb.html > > * igt at kms_content_protection@atomic: > - shard-apl: [TIMEOUT][89] ([i915#1319] / [i915#1635]) -> [FAIL][90] ([fdo#110321] / [fdo#110336]) +1 similar issue > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl7/igt at kms_content_protection@atomic.html > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl7/igt at kms_content_protection@atomic.html > > * igt at kms_content_protection@atomic-dpms: > - shard-apl: [DMESG-FAIL][91] ([fdo#110321]) -> [TIMEOUT][92] ([i915#1319]) > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl2/igt at kms_content_protection@atomic-dpms.html > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl8/igt at kms_content_protection@atomic-dpms.html > - shard-kbl: [TIMEOUT][93] ([i915#1319] / [i915#1958]) -> [TIMEOUT][94] ([i915#1319]) > [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-kbl4/igt at kms_content_protection@atomic-dpms.html > [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-kbl7/igt at kms_content_protection@atomic-dpms.html > > * igt at kms_draw_crc@fill-fb: > - shard-apl: [DMESG-WARN][95] ([i915#95]) -> [DMESG-FAIL][96] ([i915#95]) > [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl6/igt at kms_draw_crc@fill-fb.html > [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl2/igt at kms_draw_crc@fill-fb.html > > * igt at kms_sysfs_edid_timing: > - shard-apl: [FAIL][97] ([IGT#2]) -> [DMESG-FAIL][98] ([IGT#2] / [i915#95]) > [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8608/shard-apl3/igt at kms_sysfs_edid_timing.html > [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/shard-apl7/igt at kms_sysfs_edid_timing.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 > [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8608 -> Patchwork_17919 > > CI-20190529: 20190529 > CI_DRM_8608: e7b23e6cc4cdd7ad191bb039f803a2f13e4a0e40 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5700: 88e379cef970db3dab020966d5dd117de7cc03ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17919: ae88a71f3c396ee528050ee86509f65af8509303 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17919/index.html From patchwork at emeril.freedesktop.org Thu Jun 11 13:43:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 13:43:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_drm/i915/gt=3A_Move_hsw_GT_workarounds_from_i?= =?utf-8?q?nit=5Fclock=5Fgating_to_workarounds_=28rev2=29?= In-Reply-To: <20200611080140.30228-1-chris@chris-wilson.co.uk> References: <20200611080140.30228-1-chris@chris-wilson.co.uk> Message-ID: <159188300940.22713.4943140657897139220@emeril.freedesktop.org> == Series Details == Series: series starting with drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds (rev2) URL : https://patchwork.freedesktop.org/series/78214/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8614_full -> Patchwork_17926_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17926_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17926_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17926_full: ### IGT changes ### #### Possible regressions #### * igt at gem_mmap_gtt@fault-concurrent: - shard-iclb: [PASS][1] -> [CRASH][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb1/igt at gem_mmap_gtt@fault-concurrent.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb8/igt at gem_mmap_gtt@fault-concurrent.html ### Piglit changes ### #### Possible regressions #### * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-bitand-neg-uint-uint (NEW): - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/pig-icl-1065g7/spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-bitand-neg-uint-uint.html * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-div-float-vec4 (NEW): - {pig-icl-1065g7}: NOTRUN -> [CRASH][4] +1 similar issue [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/pig-icl-1065g7/spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-div-float-vec4.html New tests --------- New tests have been introduced between CI_DRM_8614_full and Patchwork_17926_full: ### New Piglit tests (8) ### * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-assign-bitand-ivec3-ivec3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-assign-bitor-int-int: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-bitand-neg-uint-uint: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-bitxor-neg-ivec3-ivec3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-bitxor-not-int-ivec2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-div-float-vec4: - Statuses : 1 crash(s) - Exec time: [0.28] s * spec at arb_tessellation_shader@execution at built-in-functions@tcs-op-mult-mat3-mat4x3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_tessellation_shader@execution at built-in-functions@tcs-step-float-vec2: - Statuses : 1 crash(s) - Exec time: [0.26] s Known issues ------------ Here are the changes found in Patchwork_17926_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vcs1: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#1528]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb5/igt at gem_ctx_persistence@engines-mixed-process at vcs1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb2/igt at gem_ctx_persistence@engines-mixed-process at vcs1.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#1930]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_fence_thrash@bo-write-verify-y: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl3/igt at gem_fence_thrash@bo-write-verify-y.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl6/igt at gem_fence_thrash@bo-write-verify-y.html * igt at kms_addfb_basic@bad-pitch-32: - shard-snb: [PASS][11] -> [TIMEOUT][12] ([i915#1958]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-snb2/igt at kms_addfb_basic@bad-pitch-32.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-snb4/igt at kms_addfb_basic@bad-pitch-32.html * igt at kms_atomic@atomic-invalid-params: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +15 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl3/igt at kms_atomic@atomic-invalid-params.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl6/igt at kms_atomic@atomic-invalid-params.html * igt at kms_big_fb@linear-8bpp-rotate-180: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl4/igt at kms_big_fb@linear-8bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl2/igt at kms_big_fb@linear-8bpp-rotate-180.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_big_fb@yf-tiled-16bpp-rotate-180: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl3/igt at kms_big_fb@yf-tiled-16bpp-rotate-180.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl6/igt at kms_big_fb@yf-tiled-16bpp-rotate-180.html * igt at kms_color@pipe-b-ctm-negative: - shard-skl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +10 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl2/igt at kms_color@pipe-b-ctm-negative.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl9/igt at kms_color@pipe-b-ctm-negative.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#72]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk6/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk2/igt at kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic: - shard-skl: [PASS][27] -> [FAIL][28] ([IGT#5]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl4/igt at kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic.html * igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2: - shard-glk: [PASS][29] -> [FAIL][30] ([i915#79]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk2/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#180]) +3 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl2/igt at kms_flip@flip-vs-suspend at a-dp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl6/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_psr@psr2_no_drrs: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb2/igt at kms_psr@psr2_no_drrs.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb6/igt at kms_psr@psr2_no_drrs.html * igt at kms_setmode@basic: - shard-skl: [PASS][35] -> [FAIL][36] ([i915#31]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl10/igt at kms_setmode@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl8/igt at kms_setmode@basic.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][37] -> [FAIL][38] ([i915#1542]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb2/igt at perf@blocking-parameterized.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb4/igt at perf@blocking-parameterized.html * igt at perf@polling-parameterized: - shard-tglb: [PASS][39] -> [FAIL][40] ([i915#1542]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb8/igt at perf@polling-parameterized.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb5/igt at perf@polling-parameterized.html #### Possible fixes #### * igt at gem_exec_fence@parallel at rcs0: - shard-tglb: [FAIL][41] ([i915#1893]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb8/igt at gem_exec_fence@parallel at rcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb5/igt at gem_exec_fence@parallel at rcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl7/igt at gem_exec_suspend@basic-s3.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl2/igt at gem_exec_suspend@basic-s3.html * igt at gem_exec_whisper@basic-contexts-forked-all: - shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk2/igt at gem_exec_whisper@basic-contexts-forked-all.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk9/igt at gem_exec_whisper@basic-contexts-forked-all.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][47] ([i915#118] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-glk7/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_legacy@cursor-vs-flip-varying-size: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +9 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl2/igt at kms_cursor_legacy@cursor-vs-flip-varying-size.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl9/igt at kms_cursor_legacy@cursor-vs-flip-varying-size.html * igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite: - shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [INCOMPLETE][55] ([i915#155]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf_pmu@other-init-3: - shard-tglb: [DMESG-WARN][63] ([i915#402]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb7/igt at perf_pmu@other-init-3.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb8/igt at perf_pmu@other-init-3.html * igt at syncobj_wait@wait-all-for-submit-complex: - shard-apl: [DMESG-WARN][65] ([i915#95]) -> [PASS][66] +13 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl7/igt at syncobj_wait@wait-all-for-submit-complex.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl8/igt at syncobj_wait@wait-all-for-submit-complex.html #### Warnings #### * igt at gem_eio@in-flight-suspend: - shard-kbl: [DMESG-WARN][67] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][68] ([i915#93] / [i915#95]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl4/igt at gem_eio@in-flight-suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl4/igt at gem_eio@in-flight-suspend.html * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html - shard-apl: [TIMEOUT][71] ([i915#1635]) -> [INCOMPLETE][72] ([i915#1635] / [i915#1958]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl4/igt at gem_exec_reloc@basic-concurrent16.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][73] ([i915#468]) -> [FAIL][74] ([i915#1899]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-tglb3/igt at i915_pm_dc@dc6-psr.html * igt at i915_suspend@forcewake: - shard-kbl: [DMESG-WARN][75] ([i915#93] / [i915#95]) -> [DMESG-WARN][76] ([i915#180] / [i915#93] / [i915#95]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-kbl1/igt at i915_suspend@forcewake.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-kbl1/igt at i915_suspend@forcewake.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [TIMEOUT][78] ([i915#1319]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-apl3/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-apl2/igt at kms_content_protection@lic.html * igt at kms_plane_alpha_blend@pipe-d-alpha-transparent-fb: - shard-snb: [SKIP][79] ([fdo#109271]) -> [TIMEOUT][80] ([i915#1958]) +3 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8614/shard-snb2/igt at kms_plane_alpha_blend@pipe-d-alpha-transparent-fb.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/shard-snb4/igt at kms_plane_alpha_blend@pipe-d-alpha-transparent-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1893]: https://gitlab.freedesktop.org/drm/intel/issues/1893 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8614 -> Patchwork_17926 CI-20190529: 20190529 CI_DRM_8614: 207862f18909166ffcf9e288ff796b756ae82d1c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17926: 66c89c81b8144175aa4d9682e650323658fddcce @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17926/index.html From patchwork at emeril.freedesktop.org Thu Jun 11 14:00:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 14:00:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=5D_drm/vblank=3A_Estimate_sample_time_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200611123038.91855-1-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> Message-ID: <159188404318.22714.16569202687439359759@emeril.freedesktop.org> == Series Details == Series: series starting with [v2] drm/vblank: Estimate sample time (rev2) URL : https://patchwork.freedesktop.org/series/78223/ State : success == Summary == CI Bug Log - changes from CI_DRM_8617 -> Patchwork_17927 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17927: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at runner@aborted: - {fi-kbl-7560u}: [FAIL][1] ([i915#1569] / [i915#192] / [i915#193] / [i915#194]) -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-kbl-7560u/igt at runner@aborted.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-kbl-7560u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17927 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-kbl-soraka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-kbl-soraka/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-kbl-soraka/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-whl-u: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-whl-u/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][13] ([i915#1888]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [INCOMPLETE][17] ([i915#1932]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-cml-s: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-cml-s/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-cml-s/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92]) -> [DMESG-WARN][26] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8617 -> Patchwork_17927 CI-20190529: 20190529 CI_DRM_8617: 2100025f87587a1dcf07985174c79a68c4a550eb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17927: 5372d180bd94d77cc77bbf902f8479fbf11d2959 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5372d180bd94 drm/i915: Tighten timestamp around vblank sampling beda68ed5040 drm/vblank: Estimate sample time == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/index.html From tvrtko.ursulin at linux.intel.com Thu Jun 11 14:29:18 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 11 Jun 2020 15:29:18 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <CAKMK7uEKYJ1kPrB01yw9A3ZHHZ4jDmzwxMjymn7pxOgs9hpKBA@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <be3526aa-07db-adc0-9291-1b5aeb0d1613@linux.intel.com> <CAKMK7uE4ak=gaKNJziaLg1qN1mE1FKLW1MGFkmUz2tR2y0ArAA@mail.gmail.com> <19c6fe47-50ff-869e-d3f0-703b8165d577@linux.intel.com> <CAKMK7uEKYJ1kPrB01yw9A3ZHHZ4jDmzwxMjymn7pxOgs9hpKBA@mail.gmail.com> Message-ID: <28c18eed-6d03-aeb2-9e0f-39bae84dfb8c@linux.intel.com> On 11/06/2020 12:29, Daniel Vetter wrote: > On Thu, Jun 11, 2020 at 12:36 PM Tvrtko Ursulin > <tvrtko.ursulin at linux.intel.com> wrote: >> On 10/06/2020 16:17, Daniel Vetter wrote: >>> On Wed, Jun 10, 2020 at 4:22 PM Tvrtko Ursulin >>> <tvrtko.ursulin at linux.intel.com> wrote: >>>> >>>> >>>> On 04/06/2020 09:12, Daniel Vetter wrote: >>>>> Design is similar to the lockdep annotations for workers, but with >>>>> some twists: >>>>> >>>>> - We use a read-lock for the execution/worker/completion side, so that >>>>> this explicit annotation can be more liberally sprinkled around. >>>>> With read locks lockdep isn't going to complain if the read-side >>>>> isn't nested the same way under all circumstances, so ABBA deadlocks >>>>> are ok. Which they are, since this is an annotation only. >>>>> >>>>> - We're using non-recursive lockdep read lock mode, since in recursive >>>>> read lock mode lockdep does not catch read side hazards. And we >>>>> _very_ much want read side hazards to be caught. For full details of >>>>> this limitation see >>>>> >>>>> commit e91498589746065e3ae95d9a00b068e525eec34f >>>>> Author: Peter Zijlstra <peterz at infradead.org> >>>>> Date: Wed Aug 23 13:13:11 2017 +0200 >>>>> >>>>> locking/lockdep/selftests: Add mixed read-write ABBA tests >>>>> >>>>> - To allow nesting of the read-side explicit annotations we explicitly >>>>> keep track of the nesting. lock_is_held() allows us to do that. >>>>> >>>>> - The wait-side annotation is a write lock, and entirely done within >>>>> dma_fence_wait() for everyone by default. >>>>> >>>>> - To be able to freely annotate helper functions I want to make it ok >>>>> to call dma_fence_begin/end_signalling from soft/hardirq context. >>>>> First attempt was using the hardirq locking context for the write >>>>> side in lockdep, but this forces all normal spinlocks nested within >>>>> dma_fence_begin/end_signalling to be spinlocks. That bollocks. >>>>> >>>>> The approach now is to simple check in_atomic(), and for these cases >>>>> entirely rely on the might_sleep() check in dma_fence_wait(). That >>>>> will catch any wrong nesting against spinlocks from soft/hardirq >>>>> contexts. >>>>> >>>>> The idea here is that every code path that's critical for eventually >>>>> signalling a dma_fence should be annotated with >>>>> dma_fence_begin/end_signalling. The annotation ideally starts right >>>>> after a dma_fence is published (added to a dma_resv, exposed as a >>>>> sync_file fd, attached to a drm_syncobj fd, or anything else that >>>>> makes the dma_fence visible to other kernel threads), up to and >>>>> including the dma_fence_wait(). Examples are irq handlers, the >>>>> scheduler rt threads, the tail of execbuf (after the corresponding >>>>> fences are visible), any workers that end up signalling dma_fences and >>>>> really anything else. Not annotated should be code paths that only >>>>> complete fences opportunistically as the gpu progresses, like e.g. >>>>> shrinker/eviction code. >>>>> >>>>> The main class of deadlocks this is supposed to catch are: >>>>> >>>>> Thread A: >>>>> >>>>> mutex_lock(A); >>>>> mutex_unlock(A); >>>>> >>>>> dma_fence_signal(); >>>>> >>>>> Thread B: >>>>> >>>>> mutex_lock(A); >>>>> dma_fence_wait(); >>>>> mutex_unlock(A); >>>>> >>>>> Thread B is blocked on A signalling the fence, but A never gets around >>>>> to that because it cannot acquire the lock A. >>>>> >>>>> Note that dma_fence_wait() is allowed to be nested within >>>>> dma_fence_begin/end_signalling sections. To allow this to happen the >>>>> read lock needs to be upgraded to a write lock, which means that any >>>>> other lock is acquired between the dma_fence_begin_signalling() call and >>>>> the call to dma_fence_wait(), and still held, this will result in an >>>>> immediate lockdep complaint. The only other option would be to not >>>>> annotate such calls, defeating the point. Therefore these annotations >>>>> cannot be sprinkled over the code entirely mindless to avoid false >>>>> positives. >>>>> >>>>> v2: handle soft/hardirq ctx better against write side and dont forget >>>>> EXPORT_SYMBOL, drivers can't use this otherwise. >>>>> >>>>> v3: Kerneldoc. >>>>> >>>>> v4: Some spelling fixes from Mika >>>>> >>>>> Cc: Mika Kuoppala <mika.kuoppala at intel.com> >>>>> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> >>>>> Cc: linux-media at vger.kernel.org >>>>> Cc: linaro-mm-sig at lists.linaro.org >>>>> Cc: linux-rdma at vger.kernel.org >>>>> Cc: amd-gfx at lists.freedesktop.org >>>>> Cc: intel-gfx at lists.freedesktop.org >>>>> Cc: Chris Wilson <chris at chris-wilson.co.uk> >>>>> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> >>>>> Cc: Christian K?nig <christian.koenig at amd.com> >>>>> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> >>>>> --- >>>>> Documentation/driver-api/dma-buf.rst | 12 +- >>>>> drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ >>>>> include/linux/dma-fence.h | 12 ++ >>>>> 3 files changed, 182 insertions(+), 3 deletions(-) >>>>> >>>>> diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst >>>>> index 63dec76d1d8d..05d856131140 100644 >>>>> --- a/Documentation/driver-api/dma-buf.rst >>>>> +++ b/Documentation/driver-api/dma-buf.rst >>>>> @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects >>>>> .. kernel-doc:: drivers/dma-buf/dma-buf.c >>>>> :doc: cpu access >>>>> >>>>> -Fence Poll Support >>>>> -~~~~~~~~~~~~~~~~~~ >>>>> +Implicit Fence Poll Support >>>>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>>>> >>>>> .. kernel-doc:: drivers/dma-buf/dma-buf.c >>>>> - :doc: fence polling >>>>> + :doc: implicit fence polling >>>>> >>>>> Kernel Functions and Structures Reference >>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>>>> @@ -133,6 +133,12 @@ DMA Fences >>>>> .. kernel-doc:: drivers/dma-buf/dma-fence.c >>>>> :doc: DMA fences overview >>>>> >>>>> +DMA Fence Signalling Annotations >>>>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>>>> + >>>>> +.. kernel-doc:: drivers/dma-buf/dma-fence.c >>>>> + :doc: fence signalling annotation >>>>> + >>>>> DMA Fences Functions Reference >>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ >>>>> >>>>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c >>>>> index 656e9ac2d028..0005bc002529 100644 >>>>> --- a/drivers/dma-buf/dma-fence.c >>>>> +++ b/drivers/dma-buf/dma-fence.c >>>>> @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) >>>>> } >>>>> EXPORT_SYMBOL(dma_fence_context_alloc); >>>>> >>>>> +/** >>>>> + * DOC: fence signalling annotation >>>>> + * >>>>> + * Proving correctness of all the kernel code around &dma_fence through code >>>>> + * review and testing is tricky for a few reasons: >>>>> + * >>>>> + * * It is a cross-driver contract, and therefore all drivers must follow the >>>>> + * same rules for lock nesting order, calling contexts for various functions >>>>> + * and anything else significant for in-kernel interfaces. But it is also >>>>> + * impossible to test all drivers in a single machine, hence brute-force N vs. >>>>> + * N testing of all combinations is impossible. Even just limiting to the >>>>> + * possible combinations is infeasible. >>>>> + * >>>>> + * * There is an enormous amount of driver code involved. For render drivers >>>>> + * there's the tail of command submission, after fences are published, >>>>> + * scheduler code, interrupt and workers to process job completion, >>>>> + * and timeout, gpu reset and gpu hang recovery code. Plus for integration >>>>> + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, >>>>> + * and &shrinker. For modesetting drivers there's the commit tail functions >>>>> + * between when fences for an atomic modeset are published, and when the >>>>> + * corresponding vblank completes, including any interrupt processing and >>>>> + * related workers. Auditing all that code, across all drivers, is not >>>>> + * feasible. >>>>> + * >>>>> + * * Due to how many other subsystems are involved and the locking hierarchies >>>>> + * this pulls in there is extremely thin wiggle-room for driver-specific >>>>> + * differences. &dma_fence interacts with almost all of the core memory >>>>> + * handling through page fault handlers via &dma_resv, dma_resv_lock() and >>>>> + * dma_resv_unlock(). On the other side it also interacts through all >>>>> + * allocation sites through &mmu_notifier and &shrinker. >>>>> + * >>>>> + * Furthermore lockdep does not handle cross-release dependencies, which means >>>>> + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught >>>>> + * at runtime with some quick testing. The simplest example is one thread >>>>> + * waiting on a &dma_fence while holding a lock:: >>>>> + * >>>>> + * lock(A); >>>>> + * dma_fence_wait(B); >>>>> + * unlock(A); >>>>> + * >>>>> + * while the other thread is stuck trying to acquire the same lock, which >>>>> + * prevents it from signalling the fence the previous thread is stuck waiting >>>>> + * on:: >>>>> + * >>>>> + * lock(A); >>>>> + * unlock(A); >>>>> + * dma_fence_signal(B); >>>>> + * >>>>> + * By manually annotating all code relevant to signalling a &dma_fence we can >>>>> + * teach lockdep about these dependencies, which also helps with the validation >>>>> + * headache since now lockdep can check all the rules for us:: >>>>> + * >>>>> + * cookie = dma_fence_begin_signalling(); >>>>> + * lock(A); >>>>> + * unlock(A); >>>>> + * dma_fence_signal(B); >>>>> + * dma_fence_end_signalling(cookie); >>>>> + * >>>>> + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to >>>>> + * annotate critical sections the following rules need to be observed: >>>>> + * >>>>> + * * All code necessary to complete a &dma_fence must be annotated, from the >>>>> + * point where a fence is accessible to other threads, to the point where >>>>> + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, >>>>> + * and due to the very strict rules and many corner cases it is infeasible to >>>>> + * catch these just with review or normal stress testing. >>>>> + * >>>>> + * * &struct dma_resv deserves a special note, since the readers are only >>>>> + * protected by rcu. This means the signalling critical section starts as soon >>>>> + * as the new fences are installed, even before dma_resv_unlock() is called. >>>>> + * >>>>> + * * The only exception are fast paths and opportunistic signalling code, which >>>>> + * calls dma_fence_signal() purely as an optimization, but is not required to >>>>> + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL >>>>> + * which calls dma_fence_signal(), while the mandatory completion path goes >>>>> + * through a hardware interrupt and possible job completion worker. >>>>> + * >>>>> + * * To aid composability of code, the annotations can be freely nested, as long >>>>> + * as the overall locking hierarchy is consistent. The annotations also work >>>>> + * both in interrupt and process context. Due to implementation details this >>>>> + * requires that callers pass an opaque cookie from >>>>> + * dma_fence_begin_signalling() to dma_fence_end_signalling(). >>>>> + * >>>>> + * * Validation against the cross driver contract is implemented by priming >>>>> + * lockdep with the relevant hierarchy at boot-up. This means even just >>>>> + * testing with a single device is enough to validate a driver, at least as >>>>> + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are >>>>> + * concerned. >>>>> + */ >>>>> +#ifdef CONFIG_LOCKDEP >>>>> +struct lockdep_map dma_fence_lockdep_map = { >>>>> + .name = "dma_fence_map" >>>>> +}; >>>> >>>> Maybe a stupid question because this is definitely complicated, but.. If >>>> you have a single/static/global lockdep map, doesn't this mean _all_ >>>> locks, from _all_ drivers happening to use dma-fences will get recorded >>>> in it. Will this work and not cause false positives? >>>> >>>> Sounds like it could create a common link between two completely >>>> unconnected usages. Because below you do add annotations to generic >>>> dma_fence_signal and dma_fence_wait. >>> >>> This is fully intentional. dma-fence is a cross-driver interface, if >>> every driver invents its own rules about how this should work we have >>> an unmaintainable and unreviewable mess. >>> >>> I've typed up the full length rant already here: >>> >>> https://lore.kernel.org/dri-devel/CAKMK7uGnFhbpuurRsnZ4dvRV9gQ_3-rmSJaoqSFY=+Kvepz_CA at mail.gmail.com/ >> >> But "perfect storm" of: >> >> + global fence lockmap >> + mmu notifiers >> + fs reclaim >> + default annotations in dma_fence_signal / dma_fence_wait >> >> Equals to anything ever using dma_fence will be in impossible chains with random other drivers, even if neither driver has code to export/share that fence. >> >> Example from the CI run: >> >> [25.918788] Chain exists of: >> fs_reclaim --> mmu_notifier_invalidate_range_start --> dma_fence_map >> [25.918794] Possible unsafe locking scenario: >> [25.918797] CPU0 CPU1 >> [25.918799] ---- ---- >> [25.918801] lock(dma_fence_map); >> [25.918803] lock(mmu_notifier_invalidate_range_start); >> [25.918807] lock(dma_fence_map); >> [25.918809] lock(fs_reclaim); >> >> What about a dma_fence_export helper which would "arm" the annotations? It would be called as soon as the fence is exported. Maybe when added to dma_resv, or exported via sync_file, etc. Before that point begin/end_signaling and so would be no-ops. > > Run CI without the i915 annotation patch, nothing breaks. I think some parts of i915 would still break with my idea to only apply annotations on exported fences. What do you dislike about that idea? I thought the point is to enforce rules for _exported_ fences. How you have annotated dma_fence_work you can't say, maybe it is exported maybe it isn't. I think it is btw, so splats would still be there, but I am not sure it is conceptually correct. At least my understanding is GFP_KERNEL allocations are only disallowed by the virtue of the global dma-fence contract. If you want to enforce they are never used for anything but exporting, then that would be a bit harsh, no? Another example from the CI run: [26.585357] CPU0 CPU1 [26.585359] ---- ---- [26.585360] lock(dma_fence_map); [26.585362] lock(mmu_notifier_invalidate_range_start); [26.585365] lock(dma_fence_map); [26.585367] lock(i915_gem_object_internal/1); [26.585369] *** DEADLOCK *** Lets say someone submitted an execbuf using userptr as a batch and then unmapped it immediately. That would explain CPU1 getting into the mmu notifier and waiting on this batch to unbind the object. Meanwhile CPU0 is the async command parser for this request trying to lock the shadow batch buffer. Because it uses the dma_fence_work this is between the begin/end signalling markers. It can be the same dma-fence I think, since we install the async parser fence on the real batch dma-resv, but dma_fence_map is not a real lock, so what is actually preventing progress in this case? CPU1 is waiting on a fence, but CPU0 can obtain the lock(i915_gem_object_internal/1), proceed to parse the batch, and exit the signalling section. At which point CPU1 is still blocked, waiting until the execbuf finishes and then mmu notifier can finish and invalidate the pages. Maybe I am missing something but I don't see how this one is real. > So we can gradually fix up existing code that doesn't quite get it > right and move on. > >>>>> + >>>>> +/** >>>>> + * dma_fence_begin_signalling - begin a critical DMA fence signalling section >>>>> + * >>>>> + * Drivers should use this to annotate the beginning of any code section >>>>> + * required to eventually complete &dma_fence by calling dma_fence_signal(). >>>>> + * >>>>> + * The end of these critical sections are annotated with >>>>> + * dma_fence_end_signalling(). >>>>> + * >>>>> + * Returns: >>>>> + * >>>>> + * Opaque cookie needed by the implementation, which needs to be passed to >>>>> + * dma_fence_end_signalling(). >>>>> + */ >>>>> +bool dma_fence_begin_signalling(void) >>>>> +{ >>>>> + /* explicitly nesting ... */ >>>>> + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) >>>>> + return true; >>>>> + >>>>> + /* rely on might_sleep check for soft/hardirq locks */ >>>>> + if (in_atomic()) >>>>> + return true; >>>>> + >>>>> + /* ... and non-recursive readlock */ >>>>> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); >>>> >>>> Would it work if signalling path would mark itself as a write lock? I am >>>> thinking it would be nice to see in lockdep splats what are signals and >>>> what are waits. >>> >>> Yeah it'd be nice to have a read vs write name for the lock. But we >>> already have this problem for e.g. flush_work(), from which I've >>> stolen this idea. So it's not really new. Essentially look at the >>> backtraces lockdep gives you, and reconstruct the deadlock. I'm hoping >>> that people will notice the special functions on the backtrace, e.g. >>> dma_fence_begin_signalling will be listed as offending function/lock >>> holder, and then read the kerneldoc. >>> >>>> The recursive usage wouldn't work then right? Would write annotation on >>>> the wait path work? >>> >>> Wait path is write annotations already, but yeah annotating the >>> signalling side as write would cause endless amounts of alse >>> positives. Also it makes composability of these e.g. what I've done in >>> amdgpu with annotations in tdr work in drm/scheduler, annotations in >>> the amdgpu gpu reset code and then also annotations in atomic code, >>> which all nest within each other in some call chains, but not others. >>> Dropping the recursion would break that and make it really awkward to >>> annotate such cases correctly. >>> >>> And the recursion only works if it's read locks, otherwise lockdep >>> complains if you have inconsistent annotations on the signalling side >>> (which again would make it more or less impossible to annotate the >>> above case fully). >> >> How do I see in lockdep splats if it was a read or write user? Your patch appears to have: >> >> dma_fence_signal: >> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); >> >> __dma_fence_might_wait: >> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); >> >> Which both seem like read lock. I don't fully understand the lockdep API so I might be wrong, not sure. But neither I see a difference in splats telling me which path is which. > > I think you got tricked by the implementation, this isn't quite what's > going on. There's two things which make the annotations special: > > - we want a recursive read lock on the signalling critical section. > The problem is that lockdep doesn't implement full validation for > recursive read locks, only non-recursive read/write locks fully > validated. There's some checks for recursive read locks, but exactly > the checks we need to catch common dma_fence_wait deadlocks aren't > done. That's why we need to implement manual lock recursion on the > reader side > > - now on the write side we additionally need to implement an > read2write upgrade, and a write2read downgrade. Lockdep doesn't > implement that, so again we have to hand-roll this. > > Let's go through the code line-by-line: > > bool tmp; > > tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); > > We check whether someone is holding the non-recursive read lock already. > > if (tmp) > lock_release(&dma_fence_lockdep_map, _THIS_IP_); > > If that's the case, we drop that read lock. > > lock_map_acquire(&dma_fence_lockdep_map); > > Then we do the actual might_wait annotation, the above takes the full > write lock ... > > lock_map_release(&dma_fence_lockdep_map); > > ... and now we release the write lock again. > > > if (tmp) > lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > > Finally we need to re-acquire the read lock, if we've held that when > entering this function. This annotation naturally has to exactly match > what begin_signalling would do, otherwise the hand-rolled nesting > would fall apart. > > I hope that explains what's going on here, and assures you that > might_wait() is indeed a write lock annotation, but with a big pile of > complications. I am certainly confused by the difference between lock_map_acquire/release and lock_acquire/release. What is the difference between the two? Regards, Tvrtko From daniel.vetter at ffwll.ch Thu Jun 11 15:03:23 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Thu, 11 Jun 2020 17:03:23 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <28c18eed-6d03-aeb2-9e0f-39bae84dfb8c@linux.intel.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <be3526aa-07db-adc0-9291-1b5aeb0d1613@linux.intel.com> <CAKMK7uE4ak=gaKNJziaLg1qN1mE1FKLW1MGFkmUz2tR2y0ArAA@mail.gmail.com> <19c6fe47-50ff-869e-d3f0-703b8165d577@linux.intel.com> <CAKMK7uEKYJ1kPrB01yw9A3ZHHZ4jDmzwxMjymn7pxOgs9hpKBA@mail.gmail.com> <28c18eed-6d03-aeb2-9e0f-39bae84dfb8c@linux.intel.com> Message-ID: <CAKMK7uFkwe8uSsC3DwvyqirdHQkMpF1rLssjDU=oL0OxK01UDw@mail.gmail.com> On Thu, Jun 11, 2020 at 4:29 PM Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> wrote: > > > On 11/06/2020 12:29, Daniel Vetter wrote: > > On Thu, Jun 11, 2020 at 12:36 PM Tvrtko Ursulin > > <tvrtko.ursulin at linux.intel.com> wrote: > >> On 10/06/2020 16:17, Daniel Vetter wrote: > >>> On Wed, Jun 10, 2020 at 4:22 PM Tvrtko Ursulin > >>> <tvrtko.ursulin at linux.intel.com> wrote: > >>>> > >>>> > >>>> On 04/06/2020 09:12, Daniel Vetter wrote: > >>>>> Design is similar to the lockdep annotations for workers, but with > >>>>> some twists: > >>>>> > >>>>> - We use a read-lock for the execution/worker/completion side, so that > >>>>> this explicit annotation can be more liberally sprinkled around. > >>>>> With read locks lockdep isn't going to complain if the read-side > >>>>> isn't nested the same way under all circumstances, so ABBA deadlocks > >>>>> are ok. Which they are, since this is an annotation only. > >>>>> > >>>>> - We're using non-recursive lockdep read lock mode, since in recursive > >>>>> read lock mode lockdep does not catch read side hazards. And we > >>>>> _very_ much want read side hazards to be caught. For full details of > >>>>> this limitation see > >>>>> > >>>>> commit e91498589746065e3ae95d9a00b068e525eec34f > >>>>> Author: Peter Zijlstra <peterz at infradead.org> > >>>>> Date: Wed Aug 23 13:13:11 2017 +0200 > >>>>> > >>>>> locking/lockdep/selftests: Add mixed read-write ABBA tests > >>>>> > >>>>> - To allow nesting of the read-side explicit annotations we explicitly > >>>>> keep track of the nesting. lock_is_held() allows us to do that. > >>>>> > >>>>> - The wait-side annotation is a write lock, and entirely done within > >>>>> dma_fence_wait() for everyone by default. > >>>>> > >>>>> - To be able to freely annotate helper functions I want to make it ok > >>>>> to call dma_fence_begin/end_signalling from soft/hardirq context. > >>>>> First attempt was using the hardirq locking context for the write > >>>>> side in lockdep, but this forces all normal spinlocks nested within > >>>>> dma_fence_begin/end_signalling to be spinlocks. That bollocks. > >>>>> > >>>>> The approach now is to simple check in_atomic(), and for these cases > >>>>> entirely rely on the might_sleep() check in dma_fence_wait(). That > >>>>> will catch any wrong nesting against spinlocks from soft/hardirq > >>>>> contexts. > >>>>> > >>>>> The idea here is that every code path that's critical for eventually > >>>>> signalling a dma_fence should be annotated with > >>>>> dma_fence_begin/end_signalling. The annotation ideally starts right > >>>>> after a dma_fence is published (added to a dma_resv, exposed as a > >>>>> sync_file fd, attached to a drm_syncobj fd, or anything else that > >>>>> makes the dma_fence visible to other kernel threads), up to and > >>>>> including the dma_fence_wait(). Examples are irq handlers, the > >>>>> scheduler rt threads, the tail of execbuf (after the corresponding > >>>>> fences are visible), any workers that end up signalling dma_fences and > >>>>> really anything else. Not annotated should be code paths that only > >>>>> complete fences opportunistically as the gpu progresses, like e.g. > >>>>> shrinker/eviction code. > >>>>> > >>>>> The main class of deadlocks this is supposed to catch are: > >>>>> > >>>>> Thread A: > >>>>> > >>>>> mutex_lock(A); > >>>>> mutex_unlock(A); > >>>>> > >>>>> dma_fence_signal(); > >>>>> > >>>>> Thread B: > >>>>> > >>>>> mutex_lock(A); > >>>>> dma_fence_wait(); > >>>>> mutex_unlock(A); > >>>>> > >>>>> Thread B is blocked on A signalling the fence, but A never gets around > >>>>> to that because it cannot acquire the lock A. > >>>>> > >>>>> Note that dma_fence_wait() is allowed to be nested within > >>>>> dma_fence_begin/end_signalling sections. To allow this to happen the > >>>>> read lock needs to be upgraded to a write lock, which means that any > >>>>> other lock is acquired between the dma_fence_begin_signalling() call and > >>>>> the call to dma_fence_wait(), and still held, this will result in an > >>>>> immediate lockdep complaint. The only other option would be to not > >>>>> annotate such calls, defeating the point. Therefore these annotations > >>>>> cannot be sprinkled over the code entirely mindless to avoid false > >>>>> positives. > >>>>> > >>>>> v2: handle soft/hardirq ctx better against write side and dont forget > >>>>> EXPORT_SYMBOL, drivers can't use this otherwise. > >>>>> > >>>>> v3: Kerneldoc. > >>>>> > >>>>> v4: Some spelling fixes from Mika > >>>>> > >>>>> Cc: Mika Kuoppala <mika.kuoppala at intel.com> > >>>>> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> > >>>>> Cc: linux-media at vger.kernel.org > >>>>> Cc: linaro-mm-sig at lists.linaro.org > >>>>> Cc: linux-rdma at vger.kernel.org > >>>>> Cc: amd-gfx at lists.freedesktop.org > >>>>> Cc: intel-gfx at lists.freedesktop.org > >>>>> Cc: Chris Wilson <chris at chris-wilson.co.uk> > >>>>> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > >>>>> Cc: Christian K?nig <christian.koenig at amd.com> > >>>>> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > >>>>> --- > >>>>> Documentation/driver-api/dma-buf.rst | 12 +- > >>>>> drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ > >>>>> include/linux/dma-fence.h | 12 ++ > >>>>> 3 files changed, 182 insertions(+), 3 deletions(-) > >>>>> > >>>>> diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > >>>>> index 63dec76d1d8d..05d856131140 100644 > >>>>> --- a/Documentation/driver-api/dma-buf.rst > >>>>> +++ b/Documentation/driver-api/dma-buf.rst > >>>>> @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > >>>>> .. kernel-doc:: drivers/dma-buf/dma-buf.c > >>>>> :doc: cpu access > >>>>> > >>>>> -Fence Poll Support > >>>>> -~~~~~~~~~~~~~~~~~~ > >>>>> +Implicit Fence Poll Support > >>>>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>>>> > >>>>> .. kernel-doc:: drivers/dma-buf/dma-buf.c > >>>>> - :doc: fence polling > >>>>> + :doc: implicit fence polling > >>>>> > >>>>> Kernel Functions and Structures Reference > >>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>>>> @@ -133,6 +133,12 @@ DMA Fences > >>>>> .. kernel-doc:: drivers/dma-buf/dma-fence.c > >>>>> :doc: DMA fences overview > >>>>> > >>>>> +DMA Fence Signalling Annotations > >>>>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>>>> + > >>>>> +.. kernel-doc:: drivers/dma-buf/dma-fence.c > >>>>> + :doc: fence signalling annotation > >>>>> + > >>>>> DMA Fences Functions Reference > >>>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>>>> > >>>>> diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > >>>>> index 656e9ac2d028..0005bc002529 100644 > >>>>> --- a/drivers/dma-buf/dma-fence.c > >>>>> +++ b/drivers/dma-buf/dma-fence.c > >>>>> @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) > >>>>> } > >>>>> EXPORT_SYMBOL(dma_fence_context_alloc); > >>>>> > >>>>> +/** > >>>>> + * DOC: fence signalling annotation > >>>>> + * > >>>>> + * Proving correctness of all the kernel code around &dma_fence through code > >>>>> + * review and testing is tricky for a few reasons: > >>>>> + * > >>>>> + * * It is a cross-driver contract, and therefore all drivers must follow the > >>>>> + * same rules for lock nesting order, calling contexts for various functions > >>>>> + * and anything else significant for in-kernel interfaces. But it is also > >>>>> + * impossible to test all drivers in a single machine, hence brute-force N vs. > >>>>> + * N testing of all combinations is impossible. Even just limiting to the > >>>>> + * possible combinations is infeasible. > >>>>> + * > >>>>> + * * There is an enormous amount of driver code involved. For render drivers > >>>>> + * there's the tail of command submission, after fences are published, > >>>>> + * scheduler code, interrupt and workers to process job completion, > >>>>> + * and timeout, gpu reset and gpu hang recovery code. Plus for integration > >>>>> + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, > >>>>> + * and &shrinker. For modesetting drivers there's the commit tail functions > >>>>> + * between when fences for an atomic modeset are published, and when the > >>>>> + * corresponding vblank completes, including any interrupt processing and > >>>>> + * related workers. Auditing all that code, across all drivers, is not > >>>>> + * feasible. > >>>>> + * > >>>>> + * * Due to how many other subsystems are involved and the locking hierarchies > >>>>> + * this pulls in there is extremely thin wiggle-room for driver-specific > >>>>> + * differences. &dma_fence interacts with almost all of the core memory > >>>>> + * handling through page fault handlers via &dma_resv, dma_resv_lock() and > >>>>> + * dma_resv_unlock(). On the other side it also interacts through all > >>>>> + * allocation sites through &mmu_notifier and &shrinker. > >>>>> + * > >>>>> + * Furthermore lockdep does not handle cross-release dependencies, which means > >>>>> + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught > >>>>> + * at runtime with some quick testing. The simplest example is one thread > >>>>> + * waiting on a &dma_fence while holding a lock:: > >>>>> + * > >>>>> + * lock(A); > >>>>> + * dma_fence_wait(B); > >>>>> + * unlock(A); > >>>>> + * > >>>>> + * while the other thread is stuck trying to acquire the same lock, which > >>>>> + * prevents it from signalling the fence the previous thread is stuck waiting > >>>>> + * on:: > >>>>> + * > >>>>> + * lock(A); > >>>>> + * unlock(A); > >>>>> + * dma_fence_signal(B); > >>>>> + * > >>>>> + * By manually annotating all code relevant to signalling a &dma_fence we can > >>>>> + * teach lockdep about these dependencies, which also helps with the validation > >>>>> + * headache since now lockdep can check all the rules for us:: > >>>>> + * > >>>>> + * cookie = dma_fence_begin_signalling(); > >>>>> + * lock(A); > >>>>> + * unlock(A); > >>>>> + * dma_fence_signal(B); > >>>>> + * dma_fence_end_signalling(cookie); > >>>>> + * > >>>>> + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to > >>>>> + * annotate critical sections the following rules need to be observed: > >>>>> + * > >>>>> + * * All code necessary to complete a &dma_fence must be annotated, from the > >>>>> + * point where a fence is accessible to other threads, to the point where > >>>>> + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, > >>>>> + * and due to the very strict rules and many corner cases it is infeasible to > >>>>> + * catch these just with review or normal stress testing. > >>>>> + * > >>>>> + * * &struct dma_resv deserves a special note, since the readers are only > >>>>> + * protected by rcu. This means the signalling critical section starts as soon > >>>>> + * as the new fences are installed, even before dma_resv_unlock() is called. > >>>>> + * > >>>>> + * * The only exception are fast paths and opportunistic signalling code, which > >>>>> + * calls dma_fence_signal() purely as an optimization, but is not required to > >>>>> + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL > >>>>> + * which calls dma_fence_signal(), while the mandatory completion path goes > >>>>> + * through a hardware interrupt and possible job completion worker. > >>>>> + * > >>>>> + * * To aid composability of code, the annotations can be freely nested, as long > >>>>> + * as the overall locking hierarchy is consistent. The annotations also work > >>>>> + * both in interrupt and process context. Due to implementation details this > >>>>> + * requires that callers pass an opaque cookie from > >>>>> + * dma_fence_begin_signalling() to dma_fence_end_signalling(). > >>>>> + * > >>>>> + * * Validation against the cross driver contract is implemented by priming > >>>>> + * lockdep with the relevant hierarchy at boot-up. This means even just > >>>>> + * testing with a single device is enough to validate a driver, at least as > >>>>> + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are > >>>>> + * concerned. > >>>>> + */ > >>>>> +#ifdef CONFIG_LOCKDEP > >>>>> +struct lockdep_map dma_fence_lockdep_map = { > >>>>> + .name = "dma_fence_map" > >>>>> +}; > >>>> > >>>> Maybe a stupid question because this is definitely complicated, but.. If > >>>> you have a single/static/global lockdep map, doesn't this mean _all_ > >>>> locks, from _all_ drivers happening to use dma-fences will get recorded > >>>> in it. Will this work and not cause false positives? > >>>> > >>>> Sounds like it could create a common link between two completely > >>>> unconnected usages. Because below you do add annotations to generic > >>>> dma_fence_signal and dma_fence_wait. > >>> > >>> This is fully intentional. dma-fence is a cross-driver interface, if > >>> every driver invents its own rules about how this should work we have > >>> an unmaintainable and unreviewable mess. > >>> > >>> I've typed up the full length rant already here: > >>> > >>> https://lore.kernel.org/dri-devel/CAKMK7uGnFhbpuurRsnZ4dvRV9gQ_3-rmSJaoqSFY=+Kvepz_CA at mail.gmail.com/ > >> > >> But "perfect storm" of: > >> > >> + global fence lockmap > >> + mmu notifiers > >> + fs reclaim > >> + default annotations in dma_fence_signal / dma_fence_wait > >> > >> Equals to anything ever using dma_fence will be in impossible chains with random other drivers, even if neither driver has code to export/share that fence. > >> > >> Example from the CI run: > >> > >> [25.918788] Chain exists of: > >> fs_reclaim --> mmu_notifier_invalidate_range_start --> dma_fence_map > >> [25.918794] Possible unsafe locking scenario: > >> [25.918797] CPU0 CPU1 > >> [25.918799] ---- ---- > >> [25.918801] lock(dma_fence_map); > >> [25.918803] lock(mmu_notifier_invalidate_range_start); > >> [25.918807] lock(dma_fence_map); > >> [25.918809] lock(fs_reclaim); > >> > >> What about a dma_fence_export helper which would "arm" the annotations? It would be called as soon as the fence is exported. Maybe when added to dma_resv, or exported via sync_file, etc. Before that point begin/end_signaling and so would be no-ops. > > > > Run CI without the i915 annotation patch, nothing breaks. > > I think some parts of i915 would still break with my idea to only apply annotations on exported fences. What do you dislike about that idea? I thought the point is to enforce rules for _exported_ fences. dma_fence is a shared concept, this is upstream, drivers are expected to a) use shared concepts and b) use them in a consistent way. If drivers do whatever they feel like then they're no maintainable in the upstream sense of "maintainable even if the vendor walks away". This was the reason why amd had to spend 2 refactoring from DAL (which used all the helpers they shared with their firmware/windows driver) to DC (which uses all the upstream kms helpers and datastructures directly). > How you have annotated dma_fence_work you can't say, maybe it is exported maybe it isn't. I think it is btw, so splats would still be there, but I am not sure it is conceptually correct. > > At least my understanding is GFP_KERNEL allocations are only disallowed by the virtue of the global dma-fence contract. If you want to enforce they are never used for anything but exporting, then that would be a bit harsh, no? > > Another example from the CI run: > > [26.585357] CPU0 CPU1 > [26.585359] ---- ---- > [26.585360] lock(dma_fence_map); > [26.585362] lock(mmu_notifier_invalidate_range_start); > [26.585365] lock(dma_fence_map); > [26.585367] lock(i915_gem_object_internal/1); > [26.585369] > *** DEADLOCK *** So ime the above deadlock summaries tend to be wrong as soon as you have more than 2 locks involved. Which we have here - they only ever show at most 2 threads, with each thread only taking 2 locks in total, which isn't going to deadlock if you have more than 2 locks involved. Which is the case above. Personally I just ignore the above deadlock scenario and just always look at all the locks and backtraces lockdep gives me, and then reconstruct the dependency graph by hand myself, including deadlock scenario. > Lets say someone submitted an execbuf using userptr as a batch and then unmapped it immediately. That would explain CPU1 getting into the mmu notifier and waiting on this batch to unbind the object. > > Meanwhile CPU0 is the async command parser for this request trying to lock the shadow batch buffer. Because it uses the dma_fence_work this is between the begin/end signalling markers. > > It can be the same dma-fence I think, since we install the async parser fence on the real batch dma-resv, but dma_fence_map is not a real lock, so what is actually preventing progress in this case? > > CPU1 is waiting on a fence, but CPU0 can obtain the lock(i915_gem_object_internal/1), proceed to parse the batch, and exit the signalling section. At which point CPU1 is still blocked, waiting until the execbuf finishes and then mmu notifier can finish and invalidate the pages. > > Maybe I am missing something but I don't see how this one is real. The above doesn't deadlock, and it also shouldn't result in a lockdep splat. The trouble is when the signalling thread also grabs i915_gem_object_internal/1 somewhere. Which if you go through full CI results you see there's more involved (and at least one of the splats is all just lockdep priming and might_lock, so could be an annotation bug on top), and there is indeed a path where we lock the driver private lock in more places, and the wrong way round. That's the thing lockdep is complaining about, it's just not making that clear in the summary because the summary is only ever correct for 2 locks. Not if more is involved. > > So we can gradually fix up existing code that doesn't quite get it > > right and move on. > > > >>>>> + > >>>>> +/** > >>>>> + * dma_fence_begin_signalling - begin a critical DMA fence signalling section > >>>>> + * > >>>>> + * Drivers should use this to annotate the beginning of any code section > >>>>> + * required to eventually complete &dma_fence by calling dma_fence_signal(). > >>>>> + * > >>>>> + * The end of these critical sections are annotated with > >>>>> + * dma_fence_end_signalling(). > >>>>> + * > >>>>> + * Returns: > >>>>> + * > >>>>> + * Opaque cookie needed by the implementation, which needs to be passed to > >>>>> + * dma_fence_end_signalling(). > >>>>> + */ > >>>>> +bool dma_fence_begin_signalling(void) > >>>>> +{ > >>>>> + /* explicitly nesting ... */ > >>>>> + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) > >>>>> + return true; > >>>>> + > >>>>> + /* rely on might_sleep check for soft/hardirq locks */ > >>>>> + if (in_atomic()) > >>>>> + return true; > >>>>> + > >>>>> + /* ... and non-recursive readlock */ > >>>>> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > >>>> > >>>> Would it work if signalling path would mark itself as a write lock? I am > >>>> thinking it would be nice to see in lockdep splats what are signals and > >>>> what are waits. > >>> > >>> Yeah it'd be nice to have a read vs write name for the lock. But we > >>> already have this problem for e.g. flush_work(), from which I've > >>> stolen this idea. So it's not really new. Essentially look at the > >>> backtraces lockdep gives you, and reconstruct the deadlock. I'm hoping > >>> that people will notice the special functions on the backtrace, e.g. > >>> dma_fence_begin_signalling will be listed as offending function/lock > >>> holder, and then read the kerneldoc. > >>> > >>>> The recursive usage wouldn't work then right? Would write annotation on > >>>> the wait path work? > >>> > >>> Wait path is write annotations already, but yeah annotating the > >>> signalling side as write would cause endless amounts of alse > >>> positives. Also it makes composability of these e.g. what I've done in > >>> amdgpu with annotations in tdr work in drm/scheduler, annotations in > >>> the amdgpu gpu reset code and then also annotations in atomic code, > >>> which all nest within each other in some call chains, but not others. > >>> Dropping the recursion would break that and make it really awkward to > >>> annotate such cases correctly. > >>> > >>> And the recursion only works if it's read locks, otherwise lockdep > >>> complains if you have inconsistent annotations on the signalling side > >>> (which again would make it more or less impossible to annotate the > >>> above case fully). > >> > >> How do I see in lockdep splats if it was a read or write user? Your patch appears to have: > >> > >> dma_fence_signal: > >> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); > >> > >> __dma_fence_might_wait: > >> + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > >> > >> Which both seem like read lock. I don't fully understand the lockdep API so I might be wrong, not sure. But neither I see a difference in splats telling me which path is which. > > > > I think you got tricked by the implementation, this isn't quite what's > > going on. There's two things which make the annotations special: > > > > - we want a recursive read lock on the signalling critical section. > > The problem is that lockdep doesn't implement full validation for > > recursive read locks, only non-recursive read/write locks fully > > validated. There's some checks for recursive read locks, but exactly > > the checks we need to catch common dma_fence_wait deadlocks aren't > > done. That's why we need to implement manual lock recursion on the > > reader side > > > > - now on the write side we additionally need to implement an > > read2write upgrade, and a write2read downgrade. Lockdep doesn't > > implement that, so again we have to hand-roll this. > > > > Let's go through the code line-by-line: > > > > bool tmp; > > > > tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); > > > > We check whether someone is holding the non-recursive read lock already. > > > > if (tmp) > > lock_release(&dma_fence_lockdep_map, _THIS_IP_); > > > > If that's the case, we drop that read lock. > > > > lock_map_acquire(&dma_fence_lockdep_map); > > > > Then we do the actual might_wait annotation, the above takes the full > > write lock ... > > > > lock_map_release(&dma_fence_lockdep_map); > > > > ... and now we release the write lock again. > > > > > > if (tmp) > > lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); > > > > Finally we need to re-acquire the read lock, if we've held that when > > entering this function. This annotation naturally has to exactly match > > what begin_signalling would do, otherwise the hand-rolled nesting > > would fall apart. > > > > I hope that explains what's going on here, and assures you that > > might_wait() is indeed a write lock annotation, but with a big pile of > > complications. > > I am certainly confused by the difference between lock_map_acquire/release and lock_acquire/release. What is the difference between the two? lock_acquire/release is a wrapper around lock_map_acquire/release. This is all lockdep internal, it's a completely undocumented maze, so unfortunately only option is to really careful follow all the definitions from various locking primitives. And then compare with lockdep self-test (which use the locking primitives, not the lockdep internals) to see which flag controls which kind of behaviour. That's at least what I do, and it's horrible. But yeah lockdep doesn't have documentation for this. If you think it's better to open code the lock_map/acquire, I guess I can do that. But it's a mess, so I need to carefully retest everything and make sure I've set the right flags and bits - for added fun they also change ordering in some of the wrappers! -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From ville.syrjala at linux.intel.com Thu Jun 11 15:38:11 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 11 Jun 2020 18:38:11 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix DP MST ACT status handling In-Reply-To: <20200610183132.13341-1-imre.deak@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> Message-ID: <20200611153811.GZ6112@intel.com> On Wed, Jun 10, 2020 at 09:31:31PM +0300, Imre Deak wrote: > On TGL+ the master transcoder's DP_TP_STATUS register should be used for > the MST ACT status handling, so make sure we do that even in case of > mulitple streams. > > This fixes an ACT timeout problem during disabling when using multiple > streams. Not sure why this was not a problem during enabling (even the > slave's DP_TP_STATUS signaled ACT correctly), but following the spec > works in that case too, so let's do that. > > There is one more place using DP_TP_STATUS, FEC enabling, but I haven't > found in BSpec which register to use in that case, so I leave the > clarification of that for later. > > BSpec: 49190 > > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++---- > 1 file changed, 39 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d18b406f2a7d..1c3654a117a9 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -316,6 +316,40 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, > return ret; > } > > +static i915_reg_t > +master_dp_tp_status_reg(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > + > + if (INTEL_GEN(dev_priv) >= 12) > + return TGL_DP_TP_STATUS(crtc_state->mst_master_transcoder); Was going to say this needs a mst check, but then I noticed you're only changing the mst paths. So this looks like a partial take on https://patchwork.freedesktop.org/patch/364549/?series=76993&rev=2 Granted, my patch would require the crtc_state plumbing everywhere so not really bug fix material. The main question I have is why are regs.dp_tp* not being populated correctly? Pretty sure they were supposed to be. Also there are a bunch of places where we poke DP_TP_CTL in intel_ddi.c. Why aren't those a problem? > + > + return intel_dp->regs.dp_tp_status; > +} > + > +static void clear_act_sent(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > + i915_reg_t dp_tp_status_reg = > + master_dp_tp_status_reg(crtc_state, intel_dp); > + > + intel_de_write(i915, dp_tp_status_reg, > + intel_de_read(i915, dp_tp_status_reg)); > +} > + > +static bool wait_for_act_sent(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > + i915_reg_t dp_tp_status_reg = > + master_dp_tp_status_reg(crtc_state, intel_dp); > + > + return intel_de_wait_for_set(i915, dp_tp_status_reg, > + DP_TP_STATUS_ACT_SENT, 1) == 0; > +} > + > static void intel_mst_disable_dp(struct intel_atomic_state *state, > struct intel_encoder *encoder, > const struct intel_crtc_state *old_crtc_state, > @@ -376,8 +410,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), > val); > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > + if (!wait_for_act_sent(old_crtc_state, intel_dp)) > drm_err(&dev_priv->drm, > "Timed out waiting for ACT sent when disabling\n"); > drm_dp_check_act_status(&intel_dp->mst_mgr); > @@ -443,7 +476,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > struct intel_connector *connector = > to_intel_connector(conn_state->connector); > int ret; > - u32 temp; > bool first_mst_stream; > > /* MST encoders are bound to a crtc, not to a connector, > @@ -476,8 +508,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); > > intel_dp->active_mst_links++; > - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); > - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); > + > + clear_act_sent(pipe_config, intel_dp); > > ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); > > @@ -513,9 +545,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > intel_dp->active_mst_links); > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); > + if (!wait_for_act_sent(pipe_config, intel_dp)) > + drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when enabling\n"); > > drm_dp_check_act_status(&intel_dp->mst_mgr); > > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 11 15:39:55 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 11 Jun 2020 18:39:55 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix DP MST ACT status handling In-Reply-To: <20200610183132.13341-1-imre.deak@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> Message-ID: <20200611153955.GA6112@intel.com> On Wed, Jun 10, 2020 at 09:31:31PM +0300, Imre Deak wrote: > On TGL+ the master transcoder's DP_TP_STATUS register should be used for > the MST ACT status handling, so make sure we do that even in case of > mulitple streams. > > This fixes an ACT timeout problem during disabling when using multiple > streams. Not sure why this was not a problem during enabling (even the > slave's DP_TP_STATUS signaled ACT correctly), but following the spec > works in that case too, so let's do that. > > There is one more place using DP_TP_STATUS, FEC enabling, but I haven't > found in BSpec which register to use in that case, so I leave the > clarification of that for later. > > BSpec: 49190 > > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++---- > 1 file changed, 39 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d18b406f2a7d..1c3654a117a9 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -316,6 +316,40 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, > return ret; > } > > +static i915_reg_t > +master_dp_tp_status_reg(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > + > + if (INTEL_GEN(dev_priv) >= 12) > + return TGL_DP_TP_STATUS(crtc_state->mst_master_transcoder); > + > + return intel_dp->regs.dp_tp_status; > +} > + > +static void clear_act_sent(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > + i915_reg_t dp_tp_status_reg = > + master_dp_tp_status_reg(crtc_state, intel_dp); > + > + intel_de_write(i915, dp_tp_status_reg, > + intel_de_read(i915, dp_tp_status_reg)); Followup material: Should we actually just clear the bit(s) we care about? No idea what other stuff is in there. > +} > + > +static bool wait_for_act_sent(const struct intel_crtc_state *crtc_state, > + const struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > + i915_reg_t dp_tp_status_reg = > + master_dp_tp_status_reg(crtc_state, intel_dp); > + > + return intel_de_wait_for_set(i915, dp_tp_status_reg, > + DP_TP_STATUS_ACT_SENT, 1) == 0; > +} > + > static void intel_mst_disable_dp(struct intel_atomic_state *state, > struct intel_encoder *encoder, > const struct intel_crtc_state *old_crtc_state, > @@ -376,8 +410,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), > val); > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > + if (!wait_for_act_sent(old_crtc_state, intel_dp)) > drm_err(&dev_priv->drm, > "Timed out waiting for ACT sent when disabling\n"); > drm_dp_check_act_status(&intel_dp->mst_mgr); > @@ -443,7 +476,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > struct intel_connector *connector = > to_intel_connector(conn_state->connector); > int ret; > - u32 temp; > bool first_mst_stream; > > /* MST encoders are bound to a crtc, not to a connector, > @@ -476,8 +508,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); > > intel_dp->active_mst_links++; > - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); > - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); > + > + clear_act_sent(pipe_config, intel_dp); > > ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); > > @@ -513,9 +545,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > intel_dp->active_mst_links); > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); > + if (!wait_for_act_sent(pipe_config, intel_dp)) > + drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when enabling\n"); > > drm_dp_check_act_status(&intel_dp->mst_mgr); > > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 11 15:46:50 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 11 Jun 2020 18:46:50 +0300 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200610191232.11620-7-uma.shankar@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> Message-ID: <20200611154650.GB6112@intel.com> On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > Implemented Infoframes enabled readback for LSPCON devices. > This will help align the implementation with state readback > infrastructure. > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > --- > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 ++++++++++++++++++++- > 1 file changed, 61 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c > index 9034ce6f20b9..0ebe9a700291 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, > buf, ret); > } > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) > +{ > + int ret; > + u32 val = 0; > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > + > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > + if (ret < 0) { > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > + return false; > + } > + > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > + return true; > + > + return false; return val & ...; > +} > + > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) > +{ > + int ret; > + u32 val = 0; > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > + > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > + if (ret < 0) { > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > + return false; > + } > + > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > + return true; > + > + return false; > +} > + > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > const struct intel_crtc_state *pipe_config) > { > - /* FIXME actually read this from the hw */ > - return 0; > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + bool infoframes_enabled; > + u32 mask = 0; > + u32 val; > + > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > + else > + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); > + > + if (infoframes_enabled) > + return true; This is supposed to return a bitmask of all enabled infoframes. Also my question "how do we turn off infoframes once enabled?" from https://patchwork.freedesktop.org/patch/351719/?series=72928&rev=1 still remains unanswered... > + > + if (lspcon->hdr_supported) { > + val = intel_de_read(dev_priv, > + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > + > + if (val & mask) > + return val & mask; > + } > + > + return false; > } > > void lspcon_resume(struct intel_lspcon *lspcon) > -- > 2.22.0 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 11 16:01:12 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 11 Jun 2020 19:01:12 +0300 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200611154650.GB6112@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> Message-ID: <20200611160112.GC6112@intel.com> On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > Implemented Infoframes enabled readback for LSPCON devices. > > This will help align the implementation with state readback > > infrastructure. > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 ++++++++++++++++++++- > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c > > index 9034ce6f20b9..0ebe9a700291 100644 > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, > > buf, ret); > > } > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) > > +{ > > + int ret; > > + u32 val = 0; > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > + > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > + if (ret < 0) { > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > + return false; > > + } > > + > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > + return true; > > + > > + return false; > > return val & ...; > > > +} > > + > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) > > +{ > > + int ret; > > + u32 val = 0; > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > + > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > + if (ret < 0) { > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > + return false; > > + } > > + > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > + return true; > > + > > + return false; > > +} > > + > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > const struct intel_crtc_state *pipe_config) > > { > > - /* FIXME actually read this from the hw */ > > - return 0; > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > + bool infoframes_enabled; > > + u32 mask = 0; > > + u32 val; > > + > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > + else > > + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); > > + > > + if (infoframes_enabled) > > + return true; > > This is supposed to return a bitmask of all enabled infoframes. Actually since we're dealing with both the LSPCON specific stuff and DIP stuff for the DRM infoframe I think we should stop using using intel_hdmi_infoframes_enabled(), and instead provide a LSPCON specific replacement for it. That way we can directly return the abstract bitmask instead of pretending to return a bitmask of the DIP bits. > > Also my question "how do we turn off infoframes once enabled?" > from https://patchwork.freedesktop.org/patch/351719/?series=72928&rev=1 > still remains unanswered... > > > + > > + if (lspcon->hdr_supported) { > > + val = intel_de_read(dev_priv, > > + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > + > > + if (val & mask) > > + return val & mask; > > + } > > + > > + return false; > > } > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > -- > > 2.22.0 > > -- > Ville Syrj?l? > Intel -- Ville Syrj?l? Intel From chris at chris-wilson.co.uk Thu Jun 11 16:05:29 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 17:05:29 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again Message-ID: <20200611160529.9558-1-chris@chris-wilson.co.uk> gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a subsequent read from e.g. the sampler can bypass the store and read the stale value from memory. This is a serious issue when we are using MI stores to rewrite the batches for relocation, as it means that the batch is reading from random user/kernel memory. While it is particularly sensitive [and detectable] for relocations, reading stale data at any time is a worry. Having started with a small number of delaying stores and doubling until no more incoherency was seen over a few hours (with and without background memory pressure), 32 was the magic number. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> --- So gen3 requires a delay after to flush the previous stores, gen5 is assuming it requires a delay between the seqno and the MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I need to verify that it still holds. --- drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++--------------- 1 file changed, 15 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c index 3fb0dc1fb910..342c476ec872 100644 --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c @@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) return 0; } -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count) { GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); *cs++ = MI_FLUSH; + *cs++ = MI_NOOP; + + while (count--) { + *cs++ = MI_STORE_DWORD_INDEX; + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); + *cs++ = rq->fence.seqno; + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; + } *cs++ = MI_STORE_DWORD_INDEX; *cs++ = I915_GEM_HWS_SEQNO_ADDR; *cs++ = rq->fence.seqno; *cs++ = MI_USER_INTERRUPT; - *cs++ = MI_NOOP; rq->tail = intel_ring_offset(rq, cs); assert_ring_tail_valid(rq->ring, rq->tail); @@ -162,31 +169,15 @@ u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) return cs; } -#define GEN5_WA_STORES 8 /* must be at least 1! */ -u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) { - int i; - - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH; - - BUILD_BUG_ON(GEN5_WA_STORES < 1); - for (i = 0; i < GEN5_WA_STORES; i++) { - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; - *cs++ = rq->fence.seqno; - } - - *cs++ = MI_USER_INTERRUPT; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); + return __gen2_emit_breadcrumb(rq, cs, 32); +} - return cs; +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) +{ + return __gen2_emit_breadcrumb(rq, cs, 8); } -#undef GEN5_WA_STORES /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ #define I830_BATCH_LIMIT SZ_256K -- 2.20.1 From ville.syrjala at linux.intel.com Thu Jun 11 16:09:29 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 11 Jun 2020 19:09:29 +0300 Subject: [Intel-gfx] [PATCH v2] drm/vblank: Estimate sample time In-Reply-To: <20200611123447.92171-1-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> <20200611123447.92171-1-chris@chris-wilson.co.uk> Message-ID: <20200611160929.GD6112@intel.com> On Thu, Jun 11, 2020 at 01:34:47PM +0100, Chris Wilson wrote: > Since we have a precise start/end time for the sample, the actual time > the HW was read back is within that interval, and more likely closer to > the mean of the interval. Use the mean sample time when estimating the > vblank time. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Seems reasonable. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/drm_vblank.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c > index da7b0b0c1090..a7043d268cca 100644 > --- a/drivers/gpu/drm/drm_vblank.c > +++ b/drivers/gpu/drm/drm_vblank.c > @@ -710,15 +710,18 @@ drm_crtc_vblank_helper_get_vblank_timestamp_internal( > delta_ns = div_s64(1000000LL * (vpos * mode->crtc_htotal + hpos), > mode->crtc_clock); > > + /* Estimate when the sample was taken */ > + stime += (etime - stime) >> 1; > + > /* Subtract time delta from raw timestamp to get final > * vblank_time timestamp for end of vblank. > */ > - *vblank_time = ktime_sub_ns(etime, delta_ns); > + *vblank_time = ktime_sub_ns(stime, delta_ns); > > if (!drm_debug_enabled(DRM_UT_VBL)) > return true; > > - ts_etime = ktime_to_timespec64(etime); > + ts_etime = ktime_to_timespec64(stime); > ts_vblank_time = ktime_to_timespec64(*vblank_time); > > DRM_DEBUG_VBL("crtc %u : v p(%d,%d)@ %lld.%06ld -> %lld.%06ld [e %d us, %d rep]\n", > -- > 2.27.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 11 16:15:42 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Thu, 11 Jun 2020 19:15:42 +0300 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Tighten timestamp around vblank sampling In-Reply-To: <20200611123038.91855-2-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> <20200611123038.91855-2-chris@chris-wilson.co.uk> Message-ID: <20200611161542.GE6112@intel.com> On Thu, Jun 11, 2020 at 01:30:38PM +0100, Chris Wilson wrote: > Tighten the timestamp queries before/after the register read so that we > have less uncertainity for when the read actually took place. This is > more apt for the older generations where it is not a simple single > register read. Whether we are able to discern an improvement in our > sampling accuracy remains to be seen. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Apart from the code getting a bit uglier can't really think of any downsides at least. Upsides (if any) I guess we shall see from the ci reports. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 57 ++++++++++++++++++++++++--------- > 1 file changed, 42 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 8e823ba25f5f..9c44df8ecce7 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -713,7 +713,9 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc) > * This function will use Framestamp and current > * timestamp registers to calculate the scanline. > */ > -static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) > +static u32 > +__intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc, > + ktime_t *stime, ktime_t *etime) > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct drm_vblank_crtc *vblank = > @@ -737,6 +739,9 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) > * pipe frame time stamp. The time stamp value > * is sampled at every start of vertical blank. > */ > + if (stime) > + *stime = ktime_get(); > + > scan_prev_time = intel_de_read_fw(dev_priv, > PIPE_FRMTMSTMP(crtc->pipe)); > > @@ -746,6 +751,9 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) > */ > scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); > > + if (etime) > + *etime = ktime_get(); > + > scan_post_time = intel_de_read_fw(dev_priv, > PIPE_FRMTMSTMP(crtc->pipe)); > } while (scan_post_time != scan_prev_time); > @@ -762,7 +770,8 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) > * intel_de_read_fw(), only for fast reads of display block, no need for > * forcewake etc. > */ > -static int __intel_get_crtc_scanline(struct intel_crtc *crtc) > +static int __intel_get_crtc_scanline(struct intel_crtc *crtc, > + ktime_t *stime, ktime_t *etime) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > @@ -771,23 +780,34 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) > enum pipe pipe = crtc->pipe; > int position, vtotal; > > - if (!crtc->active) > + if (!crtc->active) { > + if (stime) > + *stime = 0; > + if (etime) > + *etime = 0; > return -1; > + } > > vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; > mode = &vblank->hwmode; > > if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) > - return __intel_get_crtc_scanline_from_timestamp(crtc); > + return __intel_get_crtc_scanline_from_timestamp(crtc, > + stime, > + etime); > > vtotal = mode->crtc_vtotal; > if (mode->flags & DRM_MODE_FLAG_INTERLACE) > vtotal /= 2; > > + if (stime) > + *stime = ktime_get(); > if (IS_GEN(dev_priv, 2)) > position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; > else > position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; > + if (etime) > + *etime = ktime_get(); > > /* > * On HSW, the DSL reg (0x70000) appears to return 0 if we > @@ -806,7 +826,13 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) > > for (i = 0; i < 100; i++) { > udelay(1); > + > + if (stime) > + *stime = ktime_get(); > temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; > + if (etime) > + *etime = ktime_get(); > + > if (temp != position) { > position = temp; > break; > @@ -866,21 +892,25 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, > > /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ > > - /* Get optional system timestamp before query. */ > - if (stime) > - *stime = ktime_get(); > - > if (use_scanline_counter) { > /* No obvious pixelcount register. Only query vertical > * scanout position from Display scan line register. > */ > - position = __intel_get_crtc_scanline(crtc); > + position = __intel_get_crtc_scanline(crtc, stime, etime); > } else { > + /* Get optional system timestamp before query. */ > + if (stime) > + *stime = ktime_get(); > + > /* Have access to pixelcount since start of frame. > * We can split this into vertical and horizontal > * scanout position. > */ > - position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; > + position = intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)); > + > + /* Get optional system timestamp after query. */ > + if (etime) > + *etime = ktime_get(); > > /* convert to pixel counts */ > vbl_start *= htotal; > @@ -896,6 +926,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, > * matches how the scanline counter based position works since > * the scanline counter doesn't count the two half lines. > */ > + position = (position & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; > if (position >= vtotal) > position = vtotal - 1; > > @@ -911,10 +942,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, > position = (position + htotal - hsync_start) % vtotal; > } > > - /* Get optional system timestamp after query. */ > - if (etime) > - *etime = ktime_get(); > - > /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ > > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > @@ -956,7 +983,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) > int position; > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); > - position = __intel_get_crtc_scanline(crtc); > + position = __intel_get_crtc_scanline(crtc, NULL, NULL); > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > > return position; > -- > 2.27.0 -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Thu Jun 11 16:29:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 16:29:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gt=3A_Flush_gen3_relocs_harder=2C_again?= In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <159189297594.22713.9802475384252609591@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Flush gen3 relocs harder, again URL : https://patchwork.freedesktop.org/series/78230/ State : warning == Summary == $ dim checkpatch origin/drm-tip c941a56c4805 drm/i915/gt: Flush gen3 relocs harder, again -:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")' #19: References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") total: 1 errors, 0 warnings, 0 checks, 65 lines checked From imre.deak at intel.com Thu Jun 11 16:31:57 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 11 Jun 2020 19:31:57 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix DP MST ACT status handling In-Reply-To: <20200611153811.GZ6112@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> <20200611153811.GZ6112@intel.com> Message-ID: <20200611163157.GJ17512@ideak-desk.fi.intel.com> On Thu, Jun 11, 2020 at 06:38:11PM +0300, Ville Syrj?l? wrote: > On Wed, Jun 10, 2020 at 09:31:31PM +0300, Imre Deak wrote: > > On TGL+ the master transcoder's DP_TP_STATUS register should be used for > > the MST ACT status handling, so make sure we do that even in case of > > mulitple streams. > > > > This fixes an ACT timeout problem during disabling when using multiple > > streams. Not sure why this was not a problem during enabling (even the > > slave's DP_TP_STATUS signaled ACT correctly), but following the spec > > works in that case too, so let's do that. > > > > There is one more place using DP_TP_STATUS, FEC enabling, but I haven't > > found in BSpec which register to use in that case, so I leave the > > clarification of that for later. > > > > BSpec: 49190 > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++---- > > 1 file changed, 39 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index d18b406f2a7d..1c3654a117a9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -316,6 +316,40 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, > > return ret; > > } > > > > +static i915_reg_t > > +master_dp_tp_status_reg(const struct intel_crtc_state *crtc_state, > > + const struct intel_dp *intel_dp) > > +{ > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > > + > > + if (INTEL_GEN(dev_priv) >= 12) > > + return TGL_DP_TP_STATUS(crtc_state->mst_master_transcoder); > > Was going to say this needs a mst check, but then I noticed you're only > changing the mst paths. So this looks like a partial take on > https://patchwork.freedesktop.org/patch/364549/?series=76993&rev=2 > Granted, my patch would require the crtc_state plumbing everywhere > so not really bug fix material. Yes, this would fix the problem. > The main question I have is why are regs.dp_tp* not being populated > correctly? Pretty sure they were supposed to be. Yea, the real problem is in intel_ddi_get_config() corrupting those regs. So an alternative would be to fix that instead.. > Also there are a bunch of places where we poke DP_TP_CTL in > intel_ddi.c. Why aren't those a problem? Those happened to be correct for the actual port enabling/disabling. Only the non-primary streams were screwed up after a get_config() call. I was also a bit confused about which places need the master transcoder version of the dp_tp regs, since the spec requires this explicitly only for the ACT sent status check. But I guess we need to use the master version in all cases. > > > + > > + return intel_dp->regs.dp_tp_status; > > +} > > + > > +static void clear_act_sent(const struct intel_crtc_state *crtc_state, > > + const struct intel_dp *intel_dp) > > +{ > > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > > + i915_reg_t dp_tp_status_reg = > > + master_dp_tp_status_reg(crtc_state, intel_dp); > > + > > + intel_de_write(i915, dp_tp_status_reg, > > + intel_de_read(i915, dp_tp_status_reg)); > > +} > > + > > +static bool wait_for_act_sent(const struct intel_crtc_state *crtc_state, > > + const struct intel_dp *intel_dp) > > +{ > > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > > + i915_reg_t dp_tp_status_reg = > > + master_dp_tp_status_reg(crtc_state, intel_dp); > > + > > + return intel_de_wait_for_set(i915, dp_tp_status_reg, > > + DP_TP_STATUS_ACT_SENT, 1) == 0; > > +} > > + > > static void intel_mst_disable_dp(struct intel_atomic_state *state, > > struct intel_encoder *encoder, > > const struct intel_crtc_state *old_crtc_state, > > @@ -376,8 +410,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > > TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), > > val); > > > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > > - DP_TP_STATUS_ACT_SENT, 1)) > > + if (!wait_for_act_sent(old_crtc_state, intel_dp)) > > drm_err(&dev_priv->drm, > > "Timed out waiting for ACT sent when disabling\n"); > > drm_dp_check_act_status(&intel_dp->mst_mgr); > > @@ -443,7 +476,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > > struct intel_connector *connector = > > to_intel_connector(conn_state->connector); > > int ret; > > - u32 temp; > > bool first_mst_stream; > > > > /* MST encoders are bound to a crtc, not to a connector, > > @@ -476,8 +508,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > > drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); > > > > intel_dp->active_mst_links++; > > - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); > > - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); > > + > > + clear_act_sent(pipe_config, intel_dp); > > > > ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); > > > > @@ -513,9 +545,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > > intel_dp->active_mst_links); > > > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > > - DP_TP_STATUS_ACT_SENT, 1)) > > - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); > > + if (!wait_for_act_sent(pipe_config, intel_dp)) > > + drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when enabling\n"); > > > > drm_dp_check_act_status(&intel_dp->mst_mgr); > > > > -- > > 2.23.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From imre.deak at intel.com Thu Jun 11 16:37:45 2020 From: imre.deak at intel.com (Imre Deak) Date: Thu, 11 Jun 2020 19:37:45 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix DP MST ACT status handling In-Reply-To: <20200611153955.GA6112@intel.com> References: <20200610183132.13341-1-imre.deak@intel.com> <20200611153955.GA6112@intel.com> Message-ID: <20200611163745.GK17512@ideak-desk.fi.intel.com> On Thu, Jun 11, 2020 at 06:39:55PM +0300, Ville Syrj?l? wrote: > On Wed, Jun 10, 2020 at 09:31:31PM +0300, Imre Deak wrote: > > On TGL+ the master transcoder's DP_TP_STATUS register should be used for > > the MST ACT status handling, so make sure we do that even in case of > > mulitple streams. > > > > This fixes an ACT timeout problem during disabling when using multiple > > streams. Not sure why this was not a problem during enabling (even the > > slave's DP_TP_STATUS signaled ACT correctly), but following the spec > > works in that case too, so let's do that. > > > > There is one more place using DP_TP_STATUS, FEC enabling, but I haven't > > found in BSpec which register to use in that case, so I leave the > > clarification of that for later. > > > > BSpec: 49190 > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++++++++++---- > > 1 file changed, 39 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index d18b406f2a7d..1c3654a117a9 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -316,6 +316,40 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, > > return ret; > > } > > > > +static i915_reg_t > > +master_dp_tp_status_reg(const struct intel_crtc_state *crtc_state, > > + const struct intel_dp *intel_dp) > > +{ > > + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > > + > > + if (INTEL_GEN(dev_priv) >= 12) > > + return TGL_DP_TP_STATUS(crtc_state->mst_master_transcoder); > > + > > + return intel_dp->regs.dp_tp_status; > > +} > > + > > +static void clear_act_sent(const struct intel_crtc_state *crtc_state, > > + const struct intel_dp *intel_dp) > > +{ > > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > > + i915_reg_t dp_tp_status_reg = > > + master_dp_tp_status_reg(crtc_state, intel_dp); > > + > > + intel_de_write(i915, dp_tp_status_reg, > > + intel_de_read(i915, dp_tp_status_reg)); > > Followup material: > Should we actually just clear the bit(s) we care about? No idea what > other stuff is in there. Yes, was thinking about that, but thought to leave it as-is for now, since enabling may depend on something that we clear there. Though clearing all the bits may break disabling, so probably better to have this change already now. > > > +} > > + > > +static bool wait_for_act_sent(const struct intel_crtc_state *crtc_state, > > + const struct intel_dp *intel_dp) > > +{ > > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > > + i915_reg_t dp_tp_status_reg = > > + master_dp_tp_status_reg(crtc_state, intel_dp); > > + > > + return intel_de_wait_for_set(i915, dp_tp_status_reg, > > + DP_TP_STATUS_ACT_SENT, 1) == 0; > > +} > > + > > static void intel_mst_disable_dp(struct intel_atomic_state *state, > > struct intel_encoder *encoder, > > const struct intel_crtc_state *old_crtc_state, > > @@ -376,8 +410,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > > TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), > > val); > > > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > > - DP_TP_STATUS_ACT_SENT, 1)) > > + if (!wait_for_act_sent(old_crtc_state, intel_dp)) > > drm_err(&dev_priv->drm, > > "Timed out waiting for ACT sent when disabling\n"); > > drm_dp_check_act_status(&intel_dp->mst_mgr); > > @@ -443,7 +476,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > > struct intel_connector *connector = > > to_intel_connector(conn_state->connector); > > int ret; > > - u32 temp; > > bool first_mst_stream; > > > > /* MST encoders are bound to a crtc, not to a connector, > > @@ -476,8 +508,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > > drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); > > > > intel_dp->active_mst_links++; > > - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); > > - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); > > + > > + clear_act_sent(pipe_config, intel_dp); > > > > ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); > > > > @@ -513,9 +545,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > > intel_dp->active_mst_links); > > > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > > - DP_TP_STATUS_ACT_SENT, 1)) > > - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); > > + if (!wait_for_act_sent(pipe_config, intel_dp)) > > + drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when enabling\n"); > > > > drm_dp_check_act_status(&intel_dp->mst_mgr); > > > > -- > > 2.23.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Thu Jun 11 16:50:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 16:50:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Flush_gen3_relocs_harder=2C_again?= In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <159189425046.22714.10395217085568860311@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Flush gen3 relocs harder, again URL : https://patchwork.freedesktop.org/series/78230/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17928 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/index.html Known issues ------------ Here are the changes found in Patchwork_17928 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17928 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17928: c941a56c4805f053450c96e0c4366f90289b14d3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c941a56c4805 drm/i915/gt: Flush gen3 relocs harder, again == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/index.html From chris at chris-wilson.co.uk Thu Jun 11 17:47:04 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 18:47:04 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Only discard simple GGTT vma Message-ID: <20200611174704.18430-1-chris@chris-wilson.co.uk> Be careful that we do not discard the irregular information used for remapping the planes, and when discarding preserve the partial offset so that the existing users can continue to interpret the old vma correctly. An underlying issue here is that we opting to discard a vma while it is in the process of being bound, because at the time it is not known whether it will be bound suitable for our use. If we didn't discard, we would then try to unbind it even if it were suitable after serialising with the binder. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2012 Fixes: 9bdcaa5e3a2f ("drm/i915: Discard a misplaced GGTT vma") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 41553e9e57a9..cd5aeeb96ca4 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -938,9 +938,13 @@ discard_ggtt_vma(struct i915_vma *vma, const struct i915_ggtt_view *view) { const struct i915_ggtt_view discard = { .type = I915_GGTT_VIEW_PARTIAL, + .partial.offset = view->partial.offset, }; struct drm_i915_gem_object *obj = vma->obj; + if (view->type > I915_GGTT_VIEW_PARTIAL) + return false; + spin_lock(&obj->vma.lock); if (i915_vma_compare(vma, vma->vm, &discard)) { struct rb_node *rb, **p; -- 2.20.1 From patchwork at emeril.freedesktop.org Thu Jun 11 18:02:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 18:02:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=5D_drm/vblank=3A_Estimate_sample_time_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200611123038.91855-1-chris@chris-wilson.co.uk> References: <20200611123038.91855-1-chris@chris-wilson.co.uk> Message-ID: <159189854342.22714.820880482519091336@emeril.freedesktop.org> == Series Details == Series: series starting with [v2] drm/vblank: Estimate sample time (rev2) URL : https://patchwork.freedesktop.org/series/78223/ State : success == Summary == CI Bug Log - changes from CI_DRM_8617_full -> Patchwork_17927_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17927_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-wc-cpu-active: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +20 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl2/igt at gem_exec_reloc@basic-wc-cpu-active.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl4/igt at gem_exec_reloc@basic-wc-cpu-active.html * igt at gem_exec_whisper@basic-fds-priority: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-glk9/igt at gem_exec_whisper@basic-fds-priority.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-glk5/igt at gem_exec_whisper@basic-fds-priority.html * igt at gem_softpin@overlap: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +14 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-skl3/igt at gem_softpin@overlap.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-skl7/igt at gem_softpin@overlap.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl3/igt at i915_suspend@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl1/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_big_fb@linear-8bpp-rotate-180: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl6/igt at kms_big_fb@linear-8bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl7/igt at kms_big_fb@linear-8bpp-rotate-180.html - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl7/igt at kms_big_fb@linear-8bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl3/igt at kms_big_fb@linear-8bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-tglb8/igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-tglb8/igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#93] / [i915#95]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-iclb5/igt at kms_psr@psr2_cursor_render.html #### Possible fixes #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: - shard-apl: [FAIL][23] ([i915#1528]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl6/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl2/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [DMESG-WARN][25] ([i915#402]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-skl4/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-skl3/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html * igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled: - shard-apl: [DMESG-FAIL][29] ([i915#54] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl1/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl8/igt at kms_draw_crc@draw-method-xrgb8888-render-xtiled.html * igt at kms_flip@dpms-off-confusion at a-hdmi-a1: - shard-glk: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-glk9/igt at kms_flip@dpms-off-confusion at a-hdmi-a1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-glk7/igt at kms_flip@dpms-off-confusion at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +10 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl7/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend-interruptible at c-edp1: - shard-skl: [INCOMPLETE][35] ([i915#198]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-skl6/igt at kms_flip@flip-vs-suspend-interruptible at c-edp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-skl5/igt at kms_flip@flip-vs-suspend-interruptible at c-edp1.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-apl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl4/igt at kms_flip@flip-vs-suspend at a-dp1.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl6/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_flip@plain-flip-ts-check at a-dp1: - shard-kbl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl6/igt at kms_flip@plain-flip-ts-check at a-dp1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl7/igt at kms_flip@plain-flip-ts-check at a-dp1.html * igt at kms_flip_tiling@flip-changes-tiling-yf: - shard-kbl: [DMESG-WARN][41] ([i915#93] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling-yf.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl1/igt at kms_flip_tiling@flip-changes-tiling-yf.html * igt at kms_frontbuffer_tracking@psr-slowdraw: - shard-tglb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-tglb1/igt at kms_frontbuffer_tracking@psr-slowdraw.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-tglb2/igt at kms_frontbuffer_tracking@psr-slowdraw.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-iclb8/igt at kms_psr@psr2_suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][47] ([i915#1542]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-iclb7/igt at perf@blocking-parameterized.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-iclb3/igt at perf@blocking-parameterized.html * igt at syncobj_wait@invalid-wait-illegal-handle: - shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +13 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl1/igt at syncobj_wait@invalid-wait-illegal-handle.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl8/igt at syncobj_wait@invalid-wait-illegal-handle.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][51] ([i915#1319]) -> [TIMEOUT][52] ([i915#1319] / [i915#1958]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl2/igt at kms_content_protection@atomic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [FAIL][53] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][54] ([i915#1319] / [i915#1635]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl7/igt at kms_content_protection@legacy.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl3/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-kbl: [DMESG-FAIL][55] ([fdo#110321] / [i915#95]) -> [TIMEOUT][56] ([i915#1319]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl2/igt at kms_content_protection@srm.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl7/igt at kms_content_protection@srm.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [INCOMPLETE][58] ([i915#155]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: [DMESG-FAIL][59] ([fdo#108145] / [i915#95]) -> [FAIL][60] ([fdo#108145] / [i915#265]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-apl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-apl1/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][61] ([i915#1911]) -> [SKIP][62] ([fdo#109642] / [fdo#111068]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8617/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/shard-iclb8/igt at kms_psr2_su@frontbuffer.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8617 -> Patchwork_17927 CI-20190529: 20190529 CI_DRM_8617: 2100025f87587a1dcf07985174c79a68c4a550eb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5702: d16ad07e7f2a028e14d61f570931c87fa5ce404c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17927: 5372d180bd94d77cc77bbf902f8479fbf11d2959 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17927/index.html From chris at chris-wilson.co.uk Thu Jun 11 18:04:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 19:04:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Leave vma intact as they are discarded Message-ID: <20200611180421.23262-1-chris@chris-wilson.co.uk> If we find ourselves trying to reuse a misplaced but active vma, we currently try to discard it to avoid having to wait to unbind it (upsetting the current user fo the vma). An alternative to marking it as a dicarded vma and keeping it in both the obj->vma.list and obj->vma.tree, is to simply remove it from the lookup rbtree. While it remains in the list of vma, it will be unbound under eviction pressure and freed along with the object. We will never reuse it again for new instances. As before, with no pruning, the list may continually grow, but eventually we will have the most constrained version of the ggtt view that meets all requirements -- so the list of vma should not grow without bound. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2012 Fixes: 9bdcaa5e3a2f ("drm/i915: Discard a misplaced GGTT vma") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 38 +++++---------------------------- drivers/gpu/drm/i915/i915_vma.c | 3 ++- 2 files changed, 7 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 41553e9e57a9..9aa3066cb75d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -933,44 +933,16 @@ void i915_gem_runtime_suspend(struct drm_i915_private *i915) } } -static bool -discard_ggtt_vma(struct i915_vma *vma, const struct i915_ggtt_view *view) +static void discard_ggtt_vma(struct i915_vma *vma) { - const struct i915_ggtt_view discard = { - .type = I915_GGTT_VIEW_PARTIAL, - }; struct drm_i915_gem_object *obj = vma->obj; spin_lock(&obj->vma.lock); - if (i915_vma_compare(vma, vma->vm, &discard)) { - struct rb_node *rb, **p; - + if (!RB_EMPTY_NODE(&vma->obj_node)) { rb_erase(&vma->obj_node, &obj->vma.tree); - vma->ggtt_view = discard; - GEM_BUG_ON(i915_vma_compare(vma, vma->vm, &discard)); - GEM_BUG_ON(i915_vma_compare(vma, vma->vm, view) == 0); - - rb = NULL; - p = &obj->vma.tree.rb_node; - while (*p) { - struct i915_vma *pos; - long cmp; - - rb = *p; - pos = rb_entry(rb, struct i915_vma, obj_node); - - cmp = i915_vma_compare(pos, vma->vm, &discard); - if (cmp < 0) - p = &rb->rb_right; - else - p = &rb->rb_left; - } - rb_link_node(&vma->obj_node, rb, p); - rb_insert_color(&vma->obj_node, &obj->vma.tree); + RB_CLEAR_NODE(&vma->obj_node); } spin_unlock(&obj->vma.lock); - - return i915_vma_compare(vma, vma->vm, view); } struct i915_vma * @@ -1035,8 +1007,8 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, } if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) { - if (discard_ggtt_vma(vma, view)) - goto new_vma; + discard_ggtt_vma(vma); + goto new_vma; } ret = i915_vma_unbind(vma); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 9b30ddc49e4b..1f63c4a1f055 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -1087,7 +1087,8 @@ void i915_vma_release(struct kref *ref) spin_lock(&obj->vma.lock); list_del(&vma->obj_link); - rb_erase(&vma->obj_node, &obj->vma.tree); + if (!RB_EMPTY_NODE(&vma->obj_node)) + rb_erase(&vma->obj_node, &obj->vma.tree); spin_unlock(&obj->vma.lock); } -- 2.20.1 From patchwork at emeril.freedesktop.org Thu Jun 11 18:25:36 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 18:25:36 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Only_discard_simple_GGTT_vma?= In-Reply-To: <20200611174704.18430-1-chris@chris-wilson.co.uk> References: <20200611174704.18430-1-chris@chris-wilson.co.uk> Message-ID: <159189993665.22713.9752698888356168393@emeril.freedesktop.org> == Series Details == Series: drm/i915: Only discard simple GGTT vma URL : https://patchwork.freedesktop.org/series/78232/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17929 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/index.html Known issues ------------ Here are the changes found in Patchwork_17929 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-cml-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-cml-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-cml-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +6 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17929 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17929: 17a2d9b0a055cf3cc4e5c93f7ffc7cffb3ec0f6b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 17a2d9b0a055 drm/i915: Only discard simple GGTT vma == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/index.html From patchwork at emeril.freedesktop.org Thu Jun 11 19:15:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 19:15:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Leave_vma_intact_as_they_are_discarded?= In-Reply-To: <20200611180421.23262-1-chris@chris-wilson.co.uk> References: <20200611180421.23262-1-chris@chris-wilson.co.uk> Message-ID: <159190295107.22714.5418667046922351301@emeril.freedesktop.org> == Series Details == Series: drm/i915: Leave vma intact as they are discarded URL : https://patchwork.freedesktop.org/series/78233/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17930 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/index.html Known issues ------------ Here are the changes found in Patchwork_17930 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-tgl-u2/igt at i915_module_load@reload.html - fi-byt-n2820: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][5] -> [FAIL][6] ([i915#579]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at requests: - fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] ([i915#337]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-apl-guc/igt at i915_selftest@live at requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-apl-guc/igt at i915_selftest@live at requests.html #### Possible fixes #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#337]: https://gitlab.freedesktop.org/drm/intel/issues/337 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 42) ------------------------------ Missing (8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17930 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17930: e229d0849fb77a86f00729119a1fb18ae59778b7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e229d0849fb7 drm/i915: Leave vma intact as they are discarded == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/index.html From chris at chris-wilson.co.uk Thu Jun 11 20:40:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 11 Jun 2020 21:40:48 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_ctx_isolation: Verify BB_OFFSET protection Message-ID: <20200611204048.318778-1-chris@chris-wilson.co.uk> BB_OFFSET is used for relative batch buffer jumps, so prime the register and do a jump, but only after a context switch or two. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- tests/i915/gem_ctx_isolation.c | 139 +++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c index 9fdf78bb8..b689d37dd 100644 --- a/tests/i915/gem_ctx_isolation.c +++ b/tests/i915/gem_ctx_isolation.c @@ -24,6 +24,7 @@ #include "i915/gem.h" #include "igt.h" #include "igt_dummyload.h" +#include "sw_sync.h" #define MAX_REG 0x200000 #define NUM_REGS (MAX_REG / sizeof(uint32_t)) @@ -874,6 +875,124 @@ static void preservation(int fd, gem_context_destroy(fd, ctx[num_values]); } +static int sync_fence_wait_status(int fence, int timeout) +{ + int err; + + err = sync_fence_wait(fence, timeout); + if (err) + return err; + + return sync_fence_status(fence); +} + +static int write_register(int i915, uint32_t ctx, unsigned int engine, + uint32_t reg, uint32_t value) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = gem_create(i915, 4096), + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = engine | I915_EXEC_FENCE_OUT, + }; + uint32_t *cs, *map; + + map = gem_mmap__device_coherent(i915, obj.handle, 0, 4096, PROT_WRITE); + + cs = map; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = reg; + *cs++ = value; + *cs++ = MI_BATCH_BUFFER_END; + munmap(map, 4096); + + gem_execbuf_wr(i915, &execbuf); + gem_close(i915, obj.handle); + + return execbuf.rsvd2 >> 32; +} + +static void bb_offset(int i915, + const struct intel_execution_engine2 *e, + unsigned int flags) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = gem_create(i915, 4096 * 3), + .flags = EXEC_OBJECT_PINNED + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = gem_context_create_for_engine(i915, e->class, e->instance), + }; + const uint32_t mmio_base = gem_engine_mmio_base(i915, e->name); + uint32_t *cs, *map; + igt_spin_t *spin; + + igt_require(gem_class_has_mutable_submission(i915, e->class)); /* XXX */ + igt_require(mmio_base); + + gem_quiescent_gpu(i915); + + map = gem_mmap__device_coherent(i915, obj.handle, 0, 4096 * 3, PROT_WRITE); + memset(map, 0xff, 4096 * 3); + + cs = map + 2 * 1024 + 256; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = mmio_base + 0x158; /* BB_OFFSET */ + *cs++ = 4096; + *cs++ = MI_BATCH_BUFFER_END; + + cs = map + 2 * 1024 + 128; + *cs++ = MI_BATCH_BUFFER_START | 1 << 16 | 1 << 8 | 1; /* reljmp */ + *cs++ = 0; /* + BB_OFFSET */ + *cs++ = 0; + + cs = map + 1024; + *cs++ = MI_BATCH_BUFFER_END; + munmap(map, 3 * 4096); + + execbuf.batch_start_offset = 2 * 4096 + 1024; + gem_execbuf(i915, &execbuf); /* prime BB_OFFSET */ + + spin = igt_spin_new(i915, + .ctx = execbuf.rsvd1, + .flags = IGT_SPIN_POLL_RUN); + igt_spin_busywait_until_started(spin); + + if (flags & DIRTY1) { + uint32_t ctx; + int fence; + + ctx = gem_context_create_for_engine(i915, e->class, e->instance); + gem_context_set_priority(i915, ctx, 1023); + + fence = write_register(i915, ctx, 0, + mmio_base + 0x158, 0xdeadbeef); + + gem_context_destroy(i915, ctx); + + igt_assert_eq(sync_fence_wait_status(fence, 500), 1); + close(fence); + } + + if (flags & RESET) + inject_reset_context(i915, e); + + execbuf.batch_start_offset = 2 * 4096 + 512; + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); /* relative jump */ + + igt_spin_free(i915, spin); + igt_assert_eq(sync_fence_wait_status(execbuf.rsvd2 >> 32, 500), 1); + close(execbuf.rsvd2); + + gem_context_destroy(i915, execbuf.rsvd1); +} + static unsigned int __has_context_isolation(int fd) { struct drm_i915_getparam gp; @@ -963,6 +1082,16 @@ igt_main preservation(i915, e, S4); } + igt_subtest_with_dynamic("bb-offset-clean") { + test_each_engine(e, i915, has_context_isolation) + bb_offset(i915, e, 0); + } + igt_subtest_with_dynamic("bb-offset-switch") { + igt_require(gem_scheduler_has_preemption(i915)); + test_each_engine(e, i915, has_context_isolation) + bb_offset(i915, e, DIRTY1); + } + igt_fixture { igt_stop_hang_detector(); } @@ -975,4 +1104,14 @@ igt_main igt_disallow_hang(i915, hang); } + + igt_subtest_with_dynamic("bb-offset-reset") { + igt_hang_t hang = igt_allow_hang(i915, 0, 0); + + igt_require(gem_scheduler_has_preemption(i915)); + test_each_engine(e, i915, has_context_isolation) + bb_offset(i915, e, RESET); + + igt_disallow_hang(i915, hang); + } } -- 2.27.0 From patchwork at emeril.freedesktop.org Thu Jun 11 21:28:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 21:28:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Flush_gen3_relocs_harder=2C_again?= In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <159191090103.22716.15789735040349013412@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Flush gen3 relocs harder, again URL : https://patchwork.freedesktop.org/series/78230/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618_full -> Patchwork_17928_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17928_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-fds-forked-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk1/igt at gem_exec_whisper@basic-fds-forked-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk8/igt at gem_exec_whisper@basic-fds-forked-all.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +21 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at gem_mmap_wc@write-cpu-read-wc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl1/igt at gem_mmap_wc@write-cpu-read-wc.html - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at gem_mmap_wc@write-cpu-read-wc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl4/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk1/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl4/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl7/igt at kms_fbcon_fbt@fbc-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl4/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-fences at a-edp1: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl3/igt at kms_flip@flip-vs-fences at a-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl1/igt at kms_flip@flip-vs-fences at a-edp1.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl6/igt at kms_flip@flip-vs-suspend at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl7/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [PASS][19] -> [DMESG-FAIL][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl2/igt at kms_flip_tiling@flip-yf-tiled.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl7/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl9/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][25] -> [DMESG-FAIL][26] ([fdo#108145] / [i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_plane_multiple@atomic-pipe-c-tiling-none: - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#402]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb5/igt at kms_plane_multiple@atomic-pipe-c-tiling-none.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-tglb1/igt at kms_plane_multiple@atomic-pipe-c-tiling-none.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-iclb1/igt at kms_psr@psr2_cursor_plane_move.html #### Possible fixes #### * igt at gem_exec_await@wide-contexts: - shard-kbl: [DMESG-WARN][31] ([i915#93] / [i915#95]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl4/igt at gem_exec_await@wide-contexts.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl3/igt at gem_exec_await@wide-contexts.html * igt at gem_exec_reloc@basic-wc-read: - shard-apl: [DMESG-WARN][33] ([i915#95]) -> [PASS][34] +23 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl1/igt at gem_exec_reloc@basic-wc-read.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl3/igt at gem_exec_reloc@basic-wc-read.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb1/igt at i915_module_load@reload.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-tglb3/igt at i915_module_load@reload.html * igt at i915_pm_rpm@system-suspend-modeset: - shard-skl: [INCOMPLETE][37] ([i915#151] / [i915#69]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt at i915_pm_rpm@system-suspend-modeset.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl5/igt at i915_pm_rpm@system-suspend-modeset.html * igt at i915_selftest@perf at request: - shard-tglb: [INCOMPLETE][39] ([i915#1823]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb7/igt at i915_selftest@perf at request.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-tglb8/igt at i915_selftest@perf at request.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +8 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-apl: [FAIL][45] ([i915#54]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl4/igt at kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2: - shard-glk: [FAIL][47] ([i915#79]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-glk7/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at b-dp1: - shard-apl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1: - shard-skl: [FAIL][51] ([i915#1928]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +8 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl3/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb5/igt at kms_psr@psr2_cursor_render.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_setmode@basic: - shard-skl: [FAIL][59] ([i915#31]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_setmode@basic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl8/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl6/igt at kms_vblank@pipe-c-wait-busy-hang.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [INCOMPLETE][63] ([i915#1635] / [i915#1958] / [i915#95]) -> [INCOMPLETE][64] ([i915#1635] / [i915#1958]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl6/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][65] ([i915#1515]) -> [WARN][66] ([i915#1515]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-iclb3/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic: - shard-apl: [DMESG-FAIL][67] ([fdo#110321] / [i915#95]) -> [TIMEOUT][68] ([i915#1319]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl6/igt at kms_content_protection@atomic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][69] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][70] ([i915#1319] / [i915#1635]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at kms_content_protection@atomic-dpms.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-apl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][71] ([i915#1319] / [i915#1958]) -> [TIMEOUT][72] ([i915#1319]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl4/igt at kms_content_protection@legacy.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-kbl3/igt at kms_content_protection@legacy.html * igt at kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-alpha-7efc.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-alpha-7efc.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17928 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17928: c941a56c4805f053450c96e0c4366f90289b14d3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17928/index.html From clinton.a.taylor at intel.com Thu Jun 11 23:31:08 2020 From: clinton.a.taylor at intel.com (clinton.a.taylor at intel.com) Date: Thu, 11 Jun 2020 16:31:08 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Implement WA_1406941453 Message-ID: <20200611233108.19205-1-clinton.a.taylor@intel.com> From: Clint Taylor <clinton.a.taylor at intel.com> Enable HW Default flip for small PL. bspec: 52890 bspec: 53508 bspec: 53273 Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..0b9091c05e06 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -628,6 +628,9 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK, GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); + + /* Wa_1406941453:gen12 */ + WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, ENABLE_SMALLPL); } static void @@ -1500,6 +1503,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) whitelist_reg_ext(w, PS_INVOCATION_COUNT, RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4); + + /* Wa_1406941453:gen12 */ + whitelist_reg(w, GEN10_SAMPLER_MODE); break; case VIDEO_DECODE_CLASS: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 19e1fed198c3..fbb095a94b3a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9223,6 +9223,7 @@ enum { #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) #define GEN10_SAMPLER_MODE _MMIO(0xE18C) +#define ENABLE_SMALLPL REG_BIT(15) #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) /* IVYBRIDGE DPF */ -- 2.26.0 From felix.kuehling at amd.com Thu Jun 11 23:35:35 2020 From: felix.kuehling at amd.com (Felix Kuehling) Date: Thu, 11 Jun 2020 19:35:35 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200611141515.GW6578@ziepe.ca> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> Message-ID: <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> Am 2020-06-11 um 10:15 a.m. schrieb Jason Gunthorpe: > On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: >>> I still have my doubts about allowing fence waiting from within shrinkers. >>> IMO ideally they should use a trywait approach, in order to allow memory >>> allocation during command submission for drivers that >>> publish fences before command submission. (Since early reservation object >>> release requires that). >> Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up >> with a mempool to make sure it can handle it's allocations. >> >>> But since drivers are already waiting from within shrinkers and I take your >>> word for HMM requiring this, >> Yeah the big trouble is HMM and mmu notifiers. That's the really awkward >> one, the shrinker one is a lot less established. > I really question if HW that needs something like DMA fence should > even be using mmu notifiers - the best use is HW that can fence the > DMA directly without having to get involved with some command stream > processing. > > Or at the very least it should not be a generic DMA fence but a > narrowed completion tied only into the same GPU driver's command > completion processing which should be able to progress without > blocking. > > The intent of notifiers was never to endlessly block while vast > amounts of SW does work. > > Going around and switching everything in a GPU to GFP_ATOMIC seems > like bad idea. > >> I've pinged a bunch of armsoc gpu driver people and ask them how much this >> hurts, so that we have a clear answer. On x86 I don't think we have much >> of a choice on this, with userptr in amd and i915 and hmm work in nouveau >> (but nouveau I think doesn't use dma_fence in there). Soon nouveau will get company. We're working on a recoverable page fault implementation for HMM in amdgpu where we'll need to update page tables using the GPUs SDMA engine and wait for corresponding fences in MMU notifiers. Regards, ? Felix > Right, nor will RDMA ODP. > > Jason > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx From patchwork at emeril.freedesktop.org Thu Jun 11 23:47:06 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 11 Jun 2020 23:47:06 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Only_discard_simple_GGTT_vma?= In-Reply-To: <20200611174704.18430-1-chris@chris-wilson.co.uk> References: <20200611174704.18430-1-chris@chris-wilson.co.uk> Message-ID: <159191922613.22715.15556264564735168725@emeril.freedesktop.org> == Series Details == Series: drm/i915: Only discard simple GGTT vma URL : https://patchwork.freedesktop.org/series/78232/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618_full -> Patchwork_17929_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17929_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +22 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at gem_mmap_wc@write-cpu-read-wc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl6/igt at gem_mmap_wc@write-cpu-read-wc.html - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at gem_mmap_wc@write-cpu-read-wc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-kbl2/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at kms_big_fb@x-tiled-8bpp-rotate-180: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl2/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-kbl6/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#300]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl8/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-b-cursor-256x256-onscreen: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-snb1/igt at kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-snb4/igt at kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([i915#128]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb7/igt at kms_cursor_legacy@pipe-b-torture-move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-iclb4/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#46]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl7/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl4/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@flip-vs-fences at a-edp1: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl3/igt at kms_flip@flip-vs-fences at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl3/igt at kms_flip@flip-vs-fences at a-edp1.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_plane_multiple@atomic-pipe-c-tiling-none: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#402]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb5/igt at kms_plane_multiple@atomic-pipe-c-tiling-none.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-tglb6/igt at kms_plane_multiple@atomic-pipe-c-tiling-none.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb2/igt at kms_psr@psr2_sprite_render.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-iclb5/igt at kms_psr@psr2_sprite_render.html * igt at perf_pmu@module-unload: - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb1/igt at perf_pmu@module-unload.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-tglb2/igt at perf_pmu@module-unload.html #### Possible fixes #### * igt at gem_exec_reloc@basic-wc-read: - shard-apl: [DMESG-WARN][29] ([i915#95]) -> [PASS][30] +13 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl1/igt at gem_exec_reloc@basic-wc-read.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl8/igt at gem_exec_reloc@basic-wc-read.html * igt at gem_exec_schedule@implicit-read-write at bcs0: - shard-snb: [INCOMPLETE][31] ([i915#82]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-snb5/igt at gem_exec_schedule@implicit-read-write at bcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-snb1/igt at gem_exec_schedule@implicit-read-write at bcs0.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][33] ([i915#402]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb1/igt at i915_module_load@reload.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-tglb6/igt at i915_module_load@reload.html * igt at i915_pm_rpm@system-suspend-modeset: - shard-skl: [INCOMPLETE][35] ([i915#151] / [i915#69]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt at i915_pm_rpm@system-suspend-modeset.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl10/igt at i915_pm_rpm@system-suspend-modeset.html * igt at i915_selftest@perf at request: - shard-tglb: [INCOMPLETE][37] ([i915#1823]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb7/igt at i915_selftest@perf at request.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-tglb8/igt at i915_selftest@perf at request.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +9 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2: - shard-glk: [FAIL][41] ([i915#79]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-glk9/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at b-dp1: - shard-apl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1: - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][47] ([i915#1188]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-top-left-pipe-c-planes: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +5 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl2/igt at kms_plane@plane-panning-top-left-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb6/igt at kms_psr@psr2_sprite_mmap_cpu.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][55] ([i915#31]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl3/igt at kms_setmode@basic.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-kbl6/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl4/igt at kms_vblank@pipe-c-wait-busy-hang.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [INCOMPLETE][59] ([i915#1635] / [i915#1958] / [i915#95]) -> [INCOMPLETE][60] ([i915#1635] / [i915#1958]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl4/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][61] ([i915#1515]) -> [WARN][62] ([i915#1515]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-iclb3/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][63] ([i915#1319]) -> [TIMEOUT][64] ([i915#1319] / [i915#1958]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl1/igt at kms_content_protection@atomic-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-kbl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][65] ([i915#1319] / [i915#1958]) -> [TIMEOUT][66] ([i915#1319]) +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl4/igt at kms_content_protection@legacy.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-kbl2/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][67] ([i915#1319] / [i915#1635]) -> [FAIL][68] ([fdo#110321]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt at kms_content_protection@srm.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl7/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-apl: [DMESG-FAIL][69] ([i915#49] / [i915#95]) -> [FAIL][70] ([i915#49]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt at kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-apl: [FAIL][71] ([i915#265]) -> [DMESG-FAIL][72] ([i915#95]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-apl3/igt at kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt at kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-alpha-7efc.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-alpha-7efc.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17929 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17929: 17a2d9b0a055cf3cc4e5c93f7ffc7cffb3ec0f6b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17929/index.html From patchwork at emeril.freedesktop.org Fri Jun 12 00:04:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 00:04:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Implement_WA=5F1406941453?= In-Reply-To: <20200611233108.19205-1-clinton.a.taylor@intel.com> References: <20200611233108.19205-1-clinton.a.taylor@intel.com> Message-ID: <159192027560.21335.2442323093114834329@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Implement WA_1406941453 URL : https://patchwork.freedesktop.org/series/78243/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17931 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17931 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17931, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17931: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bdw-5557u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17931 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at gem_sync@basic-all: - fi-icl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-guc/igt at gem_sync@basic-all.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-guc/igt at gem_sync@basic-all.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at i915_module_load@reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][17] ([i915#62] / [i915#92]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 42) ------------------------------ Missing (8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17931 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17931: 39466c9ac72e20913b60ada9fdf53b78e4a6f70b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 39466c9ac72e drm/i915/gt: Implement WA_1406941453 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html From patchwork at emeril.freedesktop.org Fri Jun 12 00:31:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 00:31:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Leave_vma_intact_as_they_are_discarded?= In-Reply-To: <20200611180421.23262-1-chris@chris-wilson.co.uk> References: <20200611180421.23262-1-chris@chris-wilson.co.uk> Message-ID: <159192191345.21338.14949694953932886840@emeril.freedesktop.org> == Series Details == Series: drm/i915: Leave vma intact as they are discarded URL : https://patchwork.freedesktop.org/series/78233/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618_full -> Patchwork_17930_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17930_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-kbl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_eio@wait-wedge-10ms: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) +28 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt at gem_eio@wait-wedge-10ms.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl4/igt at gem_eio@wait-wedge-10ms.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at gem_mmap_wc@write-cpu-read-wc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-kbl3/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#454]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb1/igt at i915_pm_dc@dc6-psr.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-iclb2/igt at i915_pm_dc@dc6-psr.html * igt at i915_pm_rpm@system-suspend-execbuf: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#151] / [i915#69]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt at i915_pm_rpm@system-suspend-execbuf.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl4/igt at i915_pm_rpm@system-suspend-execbuf.html * igt at kms_cursor_crc@pipe-c-cursor-128x42-onscreen: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt at kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +12 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl8/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl5/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#1928]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk8/igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at ab-hdmi-a1-hdmi-a2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-glk8/igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-tglb1/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#69]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#173]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb8/igt at kms_psr@no_drrs.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-iclb7/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][31] -> [FAIL][32] ([i915#1542]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb2/igt at perf@blocking-parameterized.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-iclb7/igt at perf@blocking-parameterized.html - shard-hsw: [PASS][33] -> [FAIL][34] ([i915#1542]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-hsw2/igt at perf@blocking-parameterized.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-hsw8/igt at perf@blocking-parameterized.html * igt at perf_pmu@module-unload: - shard-iclb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb5/igt at perf_pmu@module-unload.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-iclb8/igt at perf_pmu@module-unload.html #### Possible fixes #### * igt at gem_exec_fence@basic-busy-all: - shard-snb: [TIMEOUT][37] ([i915#1958]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-snb2/igt at gem_exec_fence@basic-busy-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-snb5/igt at gem_exec_fence@basic-busy-all.html * igt at gem_exec_reloc@basic-wc-cpu-active: - shard-apl: [DMESG-WARN][39] ([i915#95]) -> [PASS][40] +24 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at gem_exec_reloc@basic-wc-cpu-active.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl3/igt at gem_exec_reloc@basic-wc-cpu-active.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][41] ([i915#402]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb1/igt at i915_module_load@reload.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-tglb1/igt at i915_module_load@reload.html * igt at i915_pm_rpm@system-suspend-modeset: - shard-skl: [INCOMPLETE][43] ([i915#151] / [i915#69]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt at i915_pm_rpm@system-suspend-modeset.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl6/igt at i915_pm_rpm@system-suspend-modeset.html * igt at i915_selftest@perf at request: - shard-tglb: [INCOMPLETE][45] ([i915#1823]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb7/igt at i915_selftest@perf at request.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-tglb5/igt at i915_selftest@perf at request.html * igt at kms_big_fb@y-tiled-32bpp-rotate-0: - shard-glk: [FAIL][47] ([i915#1119]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk4/igt at kms_big_fb@y-tiled-32bpp-rotate-0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-glk5/igt at kms_big_fb@y-tiled-32bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +6 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl7/igt at kms_color@pipe-c-ctm-0-25.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl1/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +9 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2: - shard-glk: [FAIL][53] ([i915#79]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-glk2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at b-dp1: - shard-apl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl2/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1: - shard-skl: [FAIL][57] ([i915#1928]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt: - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl2/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl7/igt at kms_vblank@pipe-c-wait-busy-hang.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][69] ([i915#1958]) -> [FAIL][70] ([i915#1930]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html - shard-apl: [INCOMPLETE][71] ([i915#1635] / [i915#1958] / [i915#95]) -> [INCOMPLETE][72] ([i915#1635] / [i915#1958]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][73] ([i915#1515]) -> [WARN][74] ([i915#1515]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-iclb4/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_chamelium@hdmi-hpd-storm-disable: - shard-snb: [TIMEOUT][75] ([i915#1958]) -> [SKIP][76] ([fdo#109271] / [fdo#111827]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-snb2/igt at kms_chamelium@hdmi-hpd-storm-disable.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-snb5/igt at kms_chamelium@hdmi-hpd-storm-disable.html * igt at kms_content_protection@atomic: - shard-apl: [DMESG-FAIL][77] ([fdo#110321] / [i915#95]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl6/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl2/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][79] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at kms_content_protection@atomic-dpms.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][81] ([i915#1319] / [i915#1958]) -> [TIMEOUT][82] ([i915#1319]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl4/igt at kms_content_protection@legacy.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-kbl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][83] ([i915#1319] / [i915#1635]) -> [FAIL][84] ([fdo#110321]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt at kms_content_protection@lic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl4/igt at kms_content_protection@lic.html - shard-kbl: [TIMEOUT][85] ([i915#1319]) -> [TIMEOUT][86] ([i915#1319] / [i915#1958]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl2/igt at kms_content_protection@lic.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-kbl4/igt at kms_content_protection@lic.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-apl: [DMESG-FAIL][87] ([i915#49] / [i915#95]) -> [FAIL][88] ([i915#49]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt: - shard-snb: [TIMEOUT][89] ([i915#1958]) -> [SKIP][90] ([fdo#109271]) +2 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-snb2/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-snb5/igt at kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][91] ([i915#93] / [i915#95]) -> [DMESG-WARN][92] ([i915#180] / [i915#93] / [i915#95]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-c-alpha-7efc: - shard-skl: [FAIL][93] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][94] ([fdo#108145] / [i915#1982]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-alpha-7efc.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-alpha-7efc.html * igt at perf@polling-parameterized: - shard-apl: [DMESG-FAIL][95] ([i915#95]) -> [FAIL][96] ([i915#1542]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl1/igt at perf@polling-parameterized.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/shard-apl8/igt at perf@polling-parameterized.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17930 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17930: e229d0849fb77a86f00729119a1fb18ae59778b7 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17930/index.html From matthew.d.roper at intel.com Fri Jun 12 02:35:29 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 11 Jun 2020 19:35:29 -0700 Subject: [Intel-gfx] [PATCH v5 0/4] Remaining RKL patches Message-ID: <20200612023533.3611774-1-matthew.d.roper@intel.com> Most of the Rocket Lake enablement patches have landed on drm-tip now, but there are still a few left awaiting reviews. Rebasing and resending the ones that still need attention. Matt Roper (4): drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout drm/i915/rkl: Add DPLL4 support drm/i915/rkl: Handle HTI drm/i915/rkl: Add initial workarounds drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++- drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++++++- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++++++++++++------- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 12 +++ 8 files changed, 175 insertions(+), 47 deletions(-) -- 2.24.1 From matthew.d.roper at intel.com Fri Jun 12 02:35:30 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 11 Jun 2020 19:35:30 -0700 Subject: [Intel-gfx] [PATCH v5 1/4] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <20200612023533.3611774-2-matthew.d.roper@intel.com> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. v2: - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 - Checkpatch style fixes Bspec: 50287 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d1acc39cdc11..a8c44ea2a4a2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, enum phy phy) { - if (intel_phy_is_combo(dev_priv, phy)) { + if (IS_ROCKETLAKE(dev_priv)) { + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + } else if (intel_phy_is_combo(dev_priv, phy)) { return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } else if (intel_phy_is_tc(dev_priv, phy)) { enum tc_port tc_port = intel_port_to_tc(dev_priv, @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { + u32 mask, sel; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } + /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + val &= ~mask; + val |= sel; intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7457813ef273..6c2bb3354b86 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + u32 mask, shift; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } + + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; + id = temp >> shift; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 19e1fed198c3..ca46ca8c80ec 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10195,12 +10195,18 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ (tc_port) + 12 : \ (tc_port) - PORT_TC4 + 21)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) /* CNL PLL */ #define DPLL0_ENABLE 0x46010 -- 2.24.1 From matthew.d.roper at intel.com Fri Jun 12 02:35:31 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 11 Jun 2020 19:35:31 -0700 Subject: [Intel-gfx] [PATCH v5 2/4] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <20200612023533.3611774-3-matthew.d.roper@intel.com> Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were DPLL2, so no extra offset handling is needed either. v2: - Add new .update_ref_clks() hook. Bspec: 49202 Bspec: 49443 Bspec: 50288 Bspec: 50289 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b45185b80bec..b5f4d4cef682 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, return false; } - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) + if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - else + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { + dpll_mask = + BIT(DPLL_ID_EHL_DPLL4) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else { dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); + } port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info rkl_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, + { }, +}; + +static const struct intel_dpll_mgr rkl_pll_mgr = { + .dpll_info = rkl_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (INTEL_GEN(dev_priv) >= 12) + if (IS_ROCKETLAKE(dev_priv)) + dpll_mgr = &rkl_pll_mgr; + else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr; else if (IS_ELKHARTLAKE(dev_priv)) dpll_mgr = &ehl_pll_mgr; -- 2.24.1 From matthew.d.roper at intel.com Fri Jun 12 02:35:33 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 11 Jun 2020 19:35:33 -0700 Subject: [Intel-gfx] [PATCH v5 4/4] drm/i915/rkl: Add initial workarounds In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <20200612023533.3611774-5-matthew.d.roper@intel.com> RKL and TGL share some general gen12 workarounds, but each platform also has its own platform-specific workarounds. Cc: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++-------- 2 files changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3cd461bf9131..63ac79f88fa2 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0] */ - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) + /* Wa_14010477008:tgl[a0..c0],rkl[all] */ + if (IS_ROCKETLAKE(dev_priv) || + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..f2136f417896 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) { /* * Wa_1409142259:tgl @@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1409207793:tgl * Wa_1409178076:tgl * Wa_1408979724:tgl + * Wa_14010443199:rkl + * Wa_14010698770:rkl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); + /* WaDisableGPGPUMidThreadPreemption:gen12 */ + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, + GEN9_PREEMPT_GPGPU_LEVEL_MASK, + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); +} + +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + /* - * Wa_1604555607:gen12 and Wa_1608008084:gen12 + * Wa_1604555607:tgl + * + * Note that the implementation of this workaround is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit * masks. So instead of doing a RMW we should just write the GS Timer @@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 0); - - /* WaDisableGPGPUMidThreadPreemption:tgl */ - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, - GEN9_PREEMPT_GPGPU_LEVEL_MASK, - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); } static void @@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 12)) + gen12_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 11)) icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) @@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen12_gt_workarounds_init(struct drm_i915_private *i915, + struct i915_wa_list *wal) { wa_init_mcr(i915, wal); +} + +static void +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) @@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 12)) + gen12_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 11)) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) @@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); - /* - * Wa_1607030317:tgl - * Wa_1607186500:tgl - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 - * of then says it is fixed on B0 the other one says it is - * permanent - */ - wa_masked_en(wal, - GEN6_RC_SLEEP_PSMI_CONTROL, - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE); - /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl */ + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); - /* Wa_1409804808:tgl */ + /* Wa_1409804808:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); - /* Wa_1606700617:tgl */ - wa_masked_en(wal, - GEN9_CS_DEBUG_MODE1, - FF_DOP_CLOCK_GATE_DISABLE); - /* * Wa_1409085225:tgl - * Wa_14010229206:tgl + * Wa_14010229206:tgl,rkl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); + + /* + * Wa_1607030317:tgl + * Wa_1607186500:tgl + * Wa_1607297627:tgl,rkl there are multiple entries for this + * WA in the BSpec; some indicate this is an A0-only WA, + * others indicate it applies to all steppings. + */ + wa_masked_en(wal, + GEN6_RC_SLEEP_PSMI_CONTROL, + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + } + + if (IS_TIGERLAKE(i915)) { + /* Wa_1606700617:tgl */ + wa_masked_en(wal, + GEN9_CS_DEBUG_MODE1, + FF_DOP_CLOCK_GATE_DISABLE); } if (IS_GEN(i915, 11)) { -- 2.24.1 From matthew.d.roper at intel.com Fri Jun 12 02:35:32 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 11 Jun 2020 19:35:32 -0700 Subject: [Intel-gfx] [PATCH v5 3/4] drm/i915/rkl: Handle HTI In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <20200612023533.3611774-4-matthew.d.roper@intel.com> If HTI (also sometimes called HDPORT) is enabled at startup, it may be using some of the PHYs and DPLLs making them unavailable for general usage. Let's read out the HDPORT_STATE register and avoid making use of resources that HTI is already using. v2: - Fix minor checkpatch warnings Bspec: 49189 Bspec: 53707 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++ 5 files changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6c2bb3354b86..f16512eddc58 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -46,6 +46,7 @@ #include "display/intel_ddi.h" #include "display/intel_dp.h" #include "display/intel_dp_mst.h" +#include "display/intel_dpll_mgr.h" #include "display/intel_dsi.h" #include "display/intel_dvo.h" #include "display/intel_gmbus.h" @@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } +static bool hti_uses_phy(u32 hdport_state, enum phy phy) +{ + return hdport_state & HDPORT_ENABLED && + (hdport_state & HDPORT_PHY_USED_DP(phy) || + hdport_state & HDPORT_PHY_USED_HDMI(phy)); +} + static void intel_setup_outputs(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; @@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_ROCKETLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + /* + * If HTI (aka HDPORT) is enabled at boot, it may have taken + * over some of the PHYs and made them unavailable to the + * driver. In that case we should skip initializing the + * corresponding outputs. + */ + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + + if (!hti_uses_phy(hdport_state, PHY_A)) + intel_ddi_init(dev_priv, PORT_A); + if (!hti_uses_phy(hdport_state, PHY_B)) + intel_ddi_init(dev_priv, PORT_B); + if (!hti_uses_phy(hdport_state, PHY_C)) + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + if (!hti_uses_phy(hdport_state, PHY_D)) + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); @@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) intel_dpll_readout_hw_state(dev_priv); + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); + for_each_intel_encoder(dev, encoder) { pipe = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b5f4d4cef682..6f59f9ec453b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) mutex_unlock(&dev_priv->dpll.lock); } +/* + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them + * unavailable for use. + */ +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) +{ + u32 hdport_state; + + if (!IS_ROCKETLAKE(dev_priv)) + return 0; + + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + if (!(hdport_state & HDPORT_ENABLED)) + return 0; + + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); +} + static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + /* Eliminate DPLLs from consideration if reserved by HTI */ + dpll_mask &= ~dev_priv->hti_pll_mask; + for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { pll = &dev_priv->dpll.shared_dplls[i]; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 5d9a2bc371e7..ac2238646fe7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device *dev); void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..b836032fa0de 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1037,6 +1037,9 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ + u32 hti_pll_mask; + /* * edram size in MB. * Cannot be determined by PCIID. You must always read a register. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ca46ca8c80ec..fd54417efc0d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2909,6 +2909,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) +#define HDPORT_STATE _MMIO(0x45050) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) +#define HDPORT_ENABLED REG_BIT(0) + /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -- 2.24.1 From patchwork at emeril.freedesktop.org Fri Jun 12 03:07:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 03:07:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Remaining_RKL_patches_=28rev3=29?= In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <159193126090.21336.3898134695445420129@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev3) URL : https://patchwork.freedesktop.org/series/77971/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Fri Jun 12 03:28:14 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 03:28:14 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev3=29?= In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <159193249476.21335.13842925859605965500@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev3) URL : https://patchwork.freedesktop.org/series/77971/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17932 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17932 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17932, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17932: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-bdw-5557u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17932 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at i915_module_load@reload.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-cml-s: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-cml-s/igt at i915_pm_rpm@module-reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-cml-s/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][16] ([i915#402]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][21] ([i915#62] / [i915#92]) +4 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17932 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17932: c11ae2b393e91e288d680cd44983df3781b5143f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c11ae2b393e9 drm/i915/rkl: Add initial workarounds e01790748ff7 drm/i915/rkl: Handle HTI 92a6f4838ed8 drm/i915/rkl: Add DPLL4 support 51b7d4fad873 drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17932/index.html From daniel at ffwll.ch Fri Jun 12 05:11:07 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 07:11:07 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> Message-ID: <CAKMK7uFE0uc5GNU49dYYQLNWbMFmQPcz_dAHHQT-dNe+Zzva-A@mail.gmail.com> On Fri, Jun 12, 2020 at 1:35 AM Felix Kuehling <felix.kuehling at amd.com> wrote: > > Am 2020-06-11 um 10:15 a.m. schrieb Jason Gunthorpe: > > On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: > >>> I still have my doubts about allowing fence waiting from within shrinkers. > >>> IMO ideally they should use a trywait approach, in order to allow memory > >>> allocation during command submission for drivers that > >>> publish fences before command submission. (Since early reservation object > >>> release requires that). > >> Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up > >> with a mempool to make sure it can handle it's allocations. > >> > >>> But since drivers are already waiting from within shrinkers and I take your > >>> word for HMM requiring this, > >> Yeah the big trouble is HMM and mmu notifiers. That's the really awkward > >> one, the shrinker one is a lot less established. > > I really question if HW that needs something like DMA fence should > > even be using mmu notifiers - the best use is HW that can fence the > > DMA directly without having to get involved with some command stream > > processing. > > > > Or at the very least it should not be a generic DMA fence but a > > narrowed completion tied only into the same GPU driver's command > > completion processing which should be able to progress without > > blocking. > > > > The intent of notifiers was never to endlessly block while vast > > amounts of SW does work. > > > > Going around and switching everything in a GPU to GFP_ATOMIC seems > > like bad idea. > > > >> I've pinged a bunch of armsoc gpu driver people and ask them how much this > >> hurts, so that we have a clear answer. On x86 I don't think we have much > >> of a choice on this, with userptr in amd and i915 and hmm work in nouveau > >> (but nouveau I think doesn't use dma_fence in there). > > Soon nouveau will get company. We're working on a recoverable page fault > implementation for HMM in amdgpu where we'll need to update page tables > using the GPUs SDMA engine and wait for corresponding fences in MMU > notifiers. Well amdgpu already has dma_fence waits in the hmm callbacks, so nothing new. But since you start using these in amdkfd ... perfect opportunity to annotate the amdkfd paths for fence signalling critical sections? Especially the preempt-ctx fence should be an interesting case to annotate and see whether lockdep finds anything. Not sure what else there is. -Daniel > > Regards, > Felix > > > > Right, nor will RDMA ODP. > > > > Jason > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Fri Jun 12 06:01:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 06:01:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Remaining_RKL_patches_=28rev4=29?= In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <159194169846.21337.16819217637788439266@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev4) URL : https://patchwork.freedesktop.org/series/77971/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Fri Jun 12 06:22:44 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 06:22:44 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev4=29?= In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <159194296404.21338.2097340655879133023@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev4) URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17933 ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_17933 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17933, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17933: ### IGT changes ### #### Warnings #### * igt at i915_selftest@live at gt_pm: - fi-tgl-u2: [DMESG-FAIL][1] ([i915#1754]) -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at i915_selftest@live at gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/fi-tgl-u2/igt at i915_selftest@live at gt_pm.html Known issues ------------ Here are the changes found in Patchwork_17933 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1754]: https://gitlab.freedesktop.org/drm/intel/issues/1754 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17933 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17933: c71cca7b9a9f9b18d2511d9fbff97ba523730f8a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c71cca7b9a9f drm/i915/rkl: Add initial workarounds a604ad13c2ad drm/i915/rkl: Handle HTI 1d4ceec6f24a drm/i915/rkl: Add DPLL4 support 1a63a32519fb drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/index.html From daniel.vetter at ffwll.ch Fri Jun 12 07:01:04 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 09:01:04 +0200 Subject: [Intel-gfx] [PATCH] dma-fence: prime lockdep annotations In-Reply-To: <20200604081224.863494-5-daniel.vetter@ffwll.ch> References: <20200604081224.863494-5-daniel.vetter@ffwll.ch> Message-ID: <20200612070104.1777608-1-daniel.vetter@ffwll.ch> Two in one go: - it is allowed to call dma_fence_wait() while holding a dma_resv_lock(). This is fundamental to how eviction works with ttm, so required. - it is allowed to call dma_fence_wait() from memory reclaim contexts, specifically from shrinker callbacks (which i915 does), and from mmu notifier callbacks (which amdgpu does, and which i915 sometimes also does, and probably always should, but that's kinda a debate). Also for stuff like HMM we really need to be able to do this, or things get real dicey. Consequence is that any critical path necessary to get to a dma_fence_signal for a fence must never a) call dma_resv_lock nor b) allocate memory with GFP_KERNEL. Also by implication of dma_resv_lock(), no userspace faulting allowed. That's some supremely obnoxious limitations, which is why we need to sprinkle the right annotations to all relevant paths. The one big locking context we're leaving out here is mmu notifiers, added in commit 23b68395c7c78a764e8963fc15a7cfd318bf187f Author: Daniel Vetter <daniel.vetter at ffwll.ch> Date: Mon Aug 26 22:14:21 2019 +0200 mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end that one covers a lot of other callsites, and it's also allowed to wait on dma-fences from mmu notifiers. But there's no ready-made functions exposed to prime this, so I've left it out for now. v2: Also track against mmu notifier context. v3: kerneldoc to spec the cross-driver contract. Note that currently i915 throws in a hard-coded 10s timeout on foreign fences (not sure why that was done, but it's there), which is why that rule is worded with SHOULD instead of MUST. Also some of the mmu_notifier/shrinker rules might surprise SoC drivers, I haven't fully audited them all. Which is infeasible anyway, we'll need to run them with lockdep and dma-fence annotations and see what goes boom. v4: A spelling fix from Mika v5: #ifdef for CONFIG_MMU_NOTIFIER. Reported by 0day. Unfortunately this means lockdep enforcement is slightly inconsistent, it won't spot GFP_NOIO and GFP_NOFS allocations in the wrong spot if CONFIG_MMU_NOTIFIER is disabled in the kernel config. Oh well. Cc: kernel test robot <lkp at intel.com> Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> (v4) Cc: Mika Kuoppala <mika.kuoppala at intel.com> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- Documentation/driver-api/dma-buf.rst | 6 ++++ drivers/dma-buf/dma-fence.c | 41 ++++++++++++++++++++++++++++ drivers/dma-buf/dma-resv.c | 8 ++++++ include/linux/dma-fence.h | 1 + 4 files changed, 56 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 05d856131140..f8f6decde359 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -133,6 +133,12 @@ DMA Fences .. kernel-doc:: drivers/dma-buf/dma-fence.c :doc: DMA fences overview +DMA Fence Cross-Driver Contract +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence.c + :doc: fence cross-driver contract + DMA Fence Signalling Annotations ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 0005bc002529..754e6fb84fb7 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -64,6 +64,47 @@ static atomic64_t dma_fence_context_counter = ATOMIC64_INIT(1); * &dma_buf.resv pointer. */ +/** + * DOC: fence cross-driver contract + * + * Since &dma_fence provide a cross driver contract, all drivers must follow the + * same rules: + * + * * Fences must complete in a reasonable time. Fences which represent kernels + * and shaders submitted by userspace, which could run forever, must be backed + * up by timeout and gpu hang recovery code. Minimally that code must prevent + * further command submission and force complete all in-flight fences, e.g. + * when the driver or hardware do not support gpu reset, or if the gpu reset + * failed for some reason. Ideally the driver supports gpu recovery which only + * affects the offending userspace context, and no other userspace + * submissions. + * + * * Drivers may have different ideas of what completion within a reasonable + * time means. Some hang recovery code uses a fixed timeout, others a mix + * between observing forward progress and increasingly strict timeouts. + * Drivers should not try to second guess timeout handling of fences from + * other drivers. + * + * * To ensure there's no deadlocks of dma_fence_wait() against other locks + * drivers should annotate all code required to reach dma_fence_signal(), + * which completes the fences, with dma_fence_begin_signalling() and + * dma_fence_end_signalling(). + * + * * Drivers are allowed to call dma_fence_wait() while holding dma_resv_lock(). + * This means any code required for fence completion cannot acquire a + * &dma_resv lock. Note that this also pulls in the entire established + * locking hierarchy around dma_resv_lock() and dma_resv_unlock(). + * + * * Drivers are allowed to call dma_fence_wait() from their &shrinker + * callbacks. This means any code required for fence completion cannot + * allocate memory with GFP_KERNEL. + * + * * Drivers are allowed to call dma_fence_wait() from their &mmu_notifier + * respectively &mmu_interval_notifier callbacks. This means any code required + * for fence completeion cannot allocate memory with GFP_NOFS or GFP_NOIO. + * Only GFP_ATOMIC is permissible, which might fail. + */ + static const char *dma_fence_stub_get_name(struct dma_fence *fence) { return "stub"; diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 99c0a33c918d..51f0583ead19 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -35,6 +35,7 @@ #include <linux/dma-resv.h> #include <linux/export.h> #include <linux/sched/mm.h> +#include <linux/mmu_notifier.h> /** * DOC: Reservation Object Overview @@ -115,6 +116,13 @@ static int __init dma_resv_lockdep(void) if (ret == -EDEADLK) dma_resv_lock_slow(&obj, &ctx); fs_reclaim_acquire(GFP_KERNEL); +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + __dma_fence_might_wait(); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#else + __dma_fence_might_wait(); +#endif fs_reclaim_release(GFP_KERNEL); ww_mutex_unlock(&obj.lock); ww_acquire_fini(&ctx); diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 3f288f7db2ef..09e23adb351d 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -360,6 +360,7 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) #ifdef CONFIG_LOCKDEP bool dma_fence_begin_signalling(void); void dma_fence_end_signalling(bool cookie); +void __dma_fence_might_wait(void); #else static inline bool dma_fence_begin_signalling(void) { -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 07:05:35 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 09:05:35 +0200 Subject: [Intel-gfx] [PATCH] dma-buf: minor doc touch-ups In-Reply-To: <20200604081224.863494-3-daniel.vetter@ffwll.ch> References: <20200604081224.863494-3-daniel.vetter@ffwll.ch> Message-ID: <20200612070535.1778368-1-daniel.vetter@ffwll.ch> Just some tiny edits: - fix link to struct dma_fence - give slightly more meaningful title - the polling here is about implicit fences, explicit fences (in sync_file or drm_syncobj) also have their own polling v2: I misplaced the .rst include change corresponding to this patch. Reviewed-by: Thomas Hellstrom <thomas.hellstrom at intel.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- Documentation/driver-api/dma-buf.rst | 6 +++--- drivers/dma-buf/dma-buf.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 63dec76d1d8d..7fb7b661febd 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects .. kernel-doc:: drivers/dma-buf/dma-buf.c :doc: cpu access -Fence Poll Support -~~~~~~~~~~~~~~~~~~ +Implicit Fence Poll Support +~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. kernel-doc:: drivers/dma-buf/dma-buf.c - :doc: fence polling + :doc: implicit fence polling Kernel Functions and Structures Reference ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 01ce125f8e8d..e018ef80451e 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -161,11 +161,11 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) } /** - * DOC: fence polling + * DOC: implicit fence polling * * To support cross-device and cross-driver synchronization of buffer access - * implicit fences (represented internally in the kernel with &struct fence) can - * be attached to a &dma_buf. The glue for that and a few related things are + * implicit fences (represented internally in the kernel with &struct dma_fence) + * can be attached to a &dma_buf. The glue for that and a few related things are * provided in the &dma_resv structure. * * Userspace can query the state of these implicitly tracked fences using poll() -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 07:06:23 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 09:06:23 +0200 Subject: [Intel-gfx] [PATCH] dma-fence: basic lockdep annotations In-Reply-To: <20200604081224.863494-4-daniel.vetter@ffwll.ch> References: <20200604081224.863494-4-daniel.vetter@ffwll.ch> Message-ID: <20200612070623.1778466-1-daniel.vetter@ffwll.ch> Design is similar to the lockdep annotations for workers, but with some twists: - We use a read-lock for the execution/worker/completion side, so that this explicit annotation can be more liberally sprinkled around. With read locks lockdep isn't going to complain if the read-side isn't nested the same way under all circumstances, so ABBA deadlocks are ok. Which they are, since this is an annotation only. - We're using non-recursive lockdep read lock mode, since in recursive read lock mode lockdep does not catch read side hazards. And we _very_ much want read side hazards to be caught. For full details of this limitation see commit e91498589746065e3ae95d9a00b068e525eec34f Author: Peter Zijlstra <peterz at infradead.org> Date: Wed Aug 23 13:13:11 2017 +0200 locking/lockdep/selftests: Add mixed read-write ABBA tests - To allow nesting of the read-side explicit annotations we explicitly keep track of the nesting. lock_is_held() allows us to do that. - The wait-side annotation is a write lock, and entirely done within dma_fence_wait() for everyone by default. - To be able to freely annotate helper functions I want to make it ok to call dma_fence_begin/end_signalling from soft/hardirq context. First attempt was using the hardirq locking context for the write side in lockdep, but this forces all normal spinlocks nested within dma_fence_begin/end_signalling to be spinlocks. That bollocks. The approach now is to simple check in_atomic(), and for these cases entirely rely on the might_sleep() check in dma_fence_wait(). That will catch any wrong nesting against spinlocks from soft/hardirq contexts. The idea here is that every code path that's critical for eventually signalling a dma_fence should be annotated with dma_fence_begin/end_signalling. The annotation ideally starts right after a dma_fence is published (added to a dma_resv, exposed as a sync_file fd, attached to a drm_syncobj fd, or anything else that makes the dma_fence visible to other kernel threads), up to and including the dma_fence_wait(). Examples are irq handlers, the scheduler rt threads, the tail of execbuf (after the corresponding fences are visible), any workers that end up signalling dma_fences and really anything else. Not annotated should be code paths that only complete fences opportunistically as the gpu progresses, like e.g. shrinker/eviction code. The main class of deadlocks this is supposed to catch are: Thread A: mutex_lock(A); mutex_unlock(A); dma_fence_signal(); Thread B: mutex_lock(A); dma_fence_wait(); mutex_unlock(A); Thread B is blocked on A signalling the fence, but A never gets around to that because it cannot acquire the lock A. Note that dma_fence_wait() is allowed to be nested within dma_fence_begin/end_signalling sections. To allow this to happen the read lock needs to be upgraded to a write lock, which means that any other lock is acquired between the dma_fence_begin_signalling() call and the call to dma_fence_wait(), and still held, this will result in an immediate lockdep complaint. The only other option would be to not annotate such calls, defeating the point. Therefore these annotations cannot be sprinkled over the code entirely mindless to avoid false positives. Originally I hope that the cross-release lockdep extensions would alleviate the need for explicit annotations: https://lwn.net/Articles/709849/ But there's a few reasons why that's not an option: - It's not happening in upstream, since it got reverted due to too many false positives: commit e966eaeeb623f09975ef362c2866fae6f86844f9 Author: Ingo Molnar <mingo at kernel.org> Date: Tue Dec 12 12:31:16 2017 +0100 locking/lockdep: Remove the cross-release locking checks This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), while it found a number of old bugs initially, was also causing too many false positives that caused people to disable lockdep - which is arguably a worse overall outcome. - cross-release uses the complete() call to annotate the end of critical sections, for dma_fence that would be dma_fence_signal(). But we do not want all dma_fence_signal() calls to be treated as critical, since many are opportunistic cleanup of gpu requests. If these get stuck there's still the main completion interrupt and workers who can unblock everyone. Automatically annotating all dma_fence_signal() calls would hence cause false positives. - cross-release had some educated guesses for when a critical section starts, like fresh syscall or fresh work callback. This would again cause false positives without explicit annotations, since for dma_fence the critical sections only starts when we publish a fence. - Furthermore there can be cases where a thread never does a dma_fence_signal, but is still critical for reaching completion of fences. One example would be a scheduler kthread which picks up jobs and pushes them into hardware, where the interrupt handler or another completion thread calls dma_fence_signal(). But if the scheduler thread hangs, then all the fences hang, hence we need to manually annotate it. cross-release aimed to solve this by chaining cross-release dependencies, but the dependency from scheduler thread to the completion interrupt handler goes through hw where cross-release code can't observe it. In short, without manual annotations and careful review of the start and end of critical sections, cross-relese dependency tracking doesn't work. We need explicit annotations. v2: handle soft/hardirq ctx better against write side and dont forget EXPORT_SYMBOL, drivers can't use this otherwise. v3: Kerneldoc. v4: Some spelling fixes from Mika v5: Amend commit message to explain in detail why cross-release isn't the solution. v6: Pull out misplaced .rst hunk. Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala at intel.com> Cc: Thomas Hellstrom <thomas.hellstrom at intel.com> Cc: linux-media at vger.kernel.org Cc: linaro-mm-sig at lists.linaro.org Cc: linux-rdma at vger.kernel.org Cc: amd-gfx at lists.freedesktop.org Cc: intel-gfx at lists.freedesktop.org Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Christian K?nig <christian.koenig at amd.com> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- Documentation/driver-api/dma-buf.rst | 6 + drivers/dma-buf/dma-fence.c | 161 +++++++++++++++++++++++++++ include/linux/dma-fence.h | 12 ++ 3 files changed, 179 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 7fb7b661febd..05d856131140 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -133,6 +133,12 @@ DMA Fences .. kernel-doc:: drivers/dma-buf/dma-fence.c :doc: DMA fences overview +DMA Fence Signalling Annotations +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence.c + :doc: fence signalling annotation + DMA Fences Functions Reference ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 656e9ac2d028..0005bc002529 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -110,6 +110,160 @@ u64 dma_fence_context_alloc(unsigned num) } EXPORT_SYMBOL(dma_fence_context_alloc); +/** + * DOC: fence signalling annotation + * + * Proving correctness of all the kernel code around &dma_fence through code + * review and testing is tricky for a few reasons: + * + * * It is a cross-driver contract, and therefore all drivers must follow the + * same rules for lock nesting order, calling contexts for various functions + * and anything else significant for in-kernel interfaces. But it is also + * impossible to test all drivers in a single machine, hence brute-force N vs. + * N testing of all combinations is impossible. Even just limiting to the + * possible combinations is infeasible. + * + * * There is an enormous amount of driver code involved. For render drivers + * there's the tail of command submission, after fences are published, + * scheduler code, interrupt and workers to process job completion, + * and timeout, gpu reset and gpu hang recovery code. Plus for integration + * with core mm with have &mmu_notifier, respectively &mmu_interval_notifier, + * and &shrinker. For modesetting drivers there's the commit tail functions + * between when fences for an atomic modeset are published, and when the + * corresponding vblank completes, including any interrupt processing and + * related workers. Auditing all that code, across all drivers, is not + * feasible. + * + * * Due to how many other subsystems are involved and the locking hierarchies + * this pulls in there is extremely thin wiggle-room for driver-specific + * differences. &dma_fence interacts with almost all of the core memory + * handling through page fault handlers via &dma_resv, dma_resv_lock() and + * dma_resv_unlock(). On the other side it also interacts through all + * allocation sites through &mmu_notifier and &shrinker. + * + * Furthermore lockdep does not handle cross-release dependencies, which means + * any deadlocks between dma_fence_wait() and dma_fence_signal() can't be caught + * at runtime with some quick testing. The simplest example is one thread + * waiting on a &dma_fence while holding a lock:: + * + * lock(A); + * dma_fence_wait(B); + * unlock(A); + * + * while the other thread is stuck trying to acquire the same lock, which + * prevents it from signalling the fence the previous thread is stuck waiting + * on:: + * + * lock(A); + * unlock(A); + * dma_fence_signal(B); + * + * By manually annotating all code relevant to signalling a &dma_fence we can + * teach lockdep about these dependencies, which also helps with the validation + * headache since now lockdep can check all the rules for us:: + * + * cookie = dma_fence_begin_signalling(); + * lock(A); + * unlock(A); + * dma_fence_signal(B); + * dma_fence_end_signalling(cookie); + * + * For using dma_fence_begin_signalling() and dma_fence_end_signalling() to + * annotate critical sections the following rules need to be observed: + * + * * All code necessary to complete a &dma_fence must be annotated, from the + * point where a fence is accessible to other threads, to the point where + * dma_fence_signal() is called. Un-annotated code can contain deadlock issues, + * and due to the very strict rules and many corner cases it is infeasible to + * catch these just with review or normal stress testing. + * + * * &struct dma_resv deserves a special note, since the readers are only + * protected by rcu. This means the signalling critical section starts as soon + * as the new fences are installed, even before dma_resv_unlock() is called. + * + * * The only exception are fast paths and opportunistic signalling code, which + * calls dma_fence_signal() purely as an optimization, but is not required to + * guarantee completion of a &dma_fence. The usual example is a wait IOCTL + * which calls dma_fence_signal(), while the mandatory completion path goes + * through a hardware interrupt and possible job completion worker. + * + * * To aid composability of code, the annotations can be freely nested, as long + * as the overall locking hierarchy is consistent. The annotations also work + * both in interrupt and process context. Due to implementation details this + * requires that callers pass an opaque cookie from + * dma_fence_begin_signalling() to dma_fence_end_signalling(). + * + * * Validation against the cross driver contract is implemented by priming + * lockdep with the relevant hierarchy at boot-up. This means even just + * testing with a single device is enough to validate a driver, at least as + * far as deadlocks with dma_fence_wait() against dma_fence_signal() are + * concerned. + */ +#ifdef CONFIG_LOCKDEP +struct lockdep_map dma_fence_lockdep_map = { + .name = "dma_fence_map" +}; + +/** + * dma_fence_begin_signalling - begin a critical DMA fence signalling section + * + * Drivers should use this to annotate the beginning of any code section + * required to eventually complete &dma_fence by calling dma_fence_signal(). + * + * The end of these critical sections are annotated with + * dma_fence_end_signalling(). + * + * Returns: + * + * Opaque cookie needed by the implementation, which needs to be passed to + * dma_fence_end_signalling(). + */ +bool dma_fence_begin_signalling(void) +{ + /* explicitly nesting ... */ + if (lock_is_held_type(&dma_fence_lockdep_map, 1)) + return true; + + /* rely on might_sleep check for soft/hardirq locks */ + if (in_atomic()) + return true; + + /* ... and non-recursive readlock */ + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _RET_IP_); + + return false; +} +EXPORT_SYMBOL(dma_fence_begin_signalling); + +/** + * dma_fence_end_signalling - end a critical DMA fence signalling section + * + * Closes a critical section annotation opened by dma_fence_begin_signalling(). + */ +void dma_fence_end_signalling(bool cookie) +{ + if (cookie) + return; + + lock_release(&dma_fence_lockdep_map, _RET_IP_); +} +EXPORT_SYMBOL(dma_fence_end_signalling); + +void __dma_fence_might_wait(void) +{ + bool tmp; + + tmp = lock_is_held_type(&dma_fence_lockdep_map, 1); + if (tmp) + lock_release(&dma_fence_lockdep_map, _THIS_IP_); + lock_map_acquire(&dma_fence_lockdep_map); + lock_map_release(&dma_fence_lockdep_map); + if (tmp) + lock_acquire(&dma_fence_lockdep_map, 0, 0, 1, 1, NULL, _THIS_IP_); +} +#endif + + /** * dma_fence_signal_locked - signal completion of a fence * @fence: the fence to signal @@ -170,14 +324,19 @@ int dma_fence_signal(struct dma_fence *fence) { unsigned long flags; int ret; + bool tmp; if (!fence) return -EINVAL; + tmp = dma_fence_begin_signalling(); + spin_lock_irqsave(fence->lock, flags); ret = dma_fence_signal_locked(fence); spin_unlock_irqrestore(fence->lock, flags); + dma_fence_end_signalling(tmp); + return ret; } EXPORT_SYMBOL(dma_fence_signal); @@ -210,6 +369,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) might_sleep(); + __dma_fence_might_wait(); + trace_dma_fence_wait_start(fence); if (fence->ops->wait) ret = fence->ops->wait(fence, intr, timeout); diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 3347c54f3a87..3f288f7db2ef 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -357,6 +357,18 @@ dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) } while (1); } +#ifdef CONFIG_LOCKDEP +bool dma_fence_begin_signalling(void); +void dma_fence_end_signalling(bool cookie); +#else +static inline bool dma_fence_begin_signalling(void) +{ + return true; +} +static inline void dma_fence_end_signalling(bool cookie) {} +static inline void __dma_fence_might_wait(void) {} +#endif + int dma_fence_signal(struct dma_fence *fence); int dma_fence_signal_locked(struct dma_fence *fence); signed long dma_fence_default_wait(struct dma_fence *fence, -- 2.26.2 From patchwork at emeril.freedesktop.org Fri Jun 12 07:18:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 07:18:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_dma-fence_lockdep_annotations=2C_round_2_=28rev6=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159194628230.21335.5464407945511819969@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev6) URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim checkpatch origin/drm-tip 59ff28b69eed mm: Track mmu notifiers in fs_reclaim_acquire/release -:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #12: recursions we do have lockdep annotations since 23b68395c7c7 -:41: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 66204f1d2d1b ("mm/mmu_notifiers: prime lockdep")' #41: With this we can also remove the lockdep priming added in 66204f1d2d1b -:124: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #124: FILE: mm/page_alloc.c:4167: + + } -:138: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 2 errors, 1 warnings, 1 checks, 67 lines checked ceede5e08eb8 dma-buf: minor doc touch-ups -:54: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 28 lines checked 07c16f051d28 dma-fence: basic lockdep annotations -:23: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e91498589746 ("locking/lockdep/selftests: Add mixed read-write ABBA tests")' #23: commit e91498589746065e3ae95d9a00b068e525eec34f -:97: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e966eaeeb623 ("locking/lockdep: Remove the cross-release locking checks")' #97: commit e966eaeeb623f09975ef362c2866fae6f86844f9 -:103: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #103: This code (CONFIG_LOCKDEP_CROSSRELEASE=y and CONFIG_LOCKDEP_COMPLETIONS=y), -:302: ERROR:IN_ATOMIC: do not use in_atomic in drivers #302: FILE: drivers/dma-buf/dma-fence.c:228: + if (in_atomic()) -:340: CHECK:LINE_SPACING: Please don't use multiple blank lines #340: FILE: drivers/dma-buf/dma-fence.c:266: + + -:389: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #389: FILE: include/linux/dma-fence.h:368: +} +static inline void dma_fence_end_signalling(bool cookie) {} -:395: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 3 errors, 2 warnings, 2 checks, 217 lines checked 6442f8dad95b dma-fence: prime lockdep annotations -:31: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 23b68395c7c7 ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end")' #31: commit 23b68395c7c78a764e8963fc15a7cfd318bf187f -:180: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 1 errors, 1 warnings, 0 checks, 86 lines checked b874c76322b8 drm/vkms: Annotate vblank timer -:59: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 25 lines checked 9f0f8c8303fa drm/vblank: Annotate with dma-fence signalling section -:71: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 38 lines checked d85809aae908 drm/atomic-helper: Add dma-fence annotations -:119: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 76 lines checked b6778d197cf3 drm/amdgpu: add dma-fence annotations to atomic commit path -:52: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 24 lines checked c4ab594ebf4a drm/scheduler: use dma-fence annotations in main thread -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 21 lines checked b4093fcdacd2 drm/amdgpu: use dma-fence annotations in cs_submit() -:65: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 29 lines checked d9ed9c09b946 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code -:82: WARNING:ALLOC_ARRAY_ARGS: kmalloc_array uses number as first arg, sizeof is generally wrong #82: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:211: + fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_ATOMIC); -:98: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 24 lines checked 45b663c70065 drm/amdgpu: DC also loves to allocate stuff where it shouldn't -:70: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #70: FILE: drivers/gpu/drm/amd/display/dc/core/dc.c:1436: + * atomic_commit_tail. */ -:76: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 27 lines checked 7a2bb8a3d251 drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail -:39: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif #39: FILE: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:6914: +#if 0 -:55: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 23 lines checked 36895e1c3363 drm/scheduler: use dma-fence annotations in tdr work -:28: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'? #28: Hence split out as a seperate patch. -:114: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 2 warnings, 0 checks, 20 lines checked e8d515333826 drm/amdgpu: use dma-fence annotations for gpu reset code 823a78e8bd4d Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" -:145: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 16 lines checked 20094f452976 drm/amdgpu: gpu recovery does full modesets -:186: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 14 lines checked 6403c98f95cb drm/i915: Annotate dma_fence_work -:53: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 15 lines checked From patchwork at emeril.freedesktop.org Fri Jun 12 07:19:48 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 07:19:48 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?dma-fence_lockdep_annotations=2C_round_2_=28rev6=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159194638829.21338.7315436620692016849@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev6) URL : https://patchwork.freedesktop.org/series/77986/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1618:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1619:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '<asn:2>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '<asn:2> From patchwork at emeril.freedesktop.org Fri Jun 12 07:32:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 07:32:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZG1h?= =?utf-8?q?-fence_lockdep_annotations=2C_round_2_=28rev6=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159194717213.21336.5659120392109472126@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev6) URL : https://patchwork.freedesktop.org/series/77986/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17934 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17934 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17934, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17934: ### IGT changes ### #### Possible regressions #### * igt at gem_busy@busy at all: - fi-kbl-x1275: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at gem_busy@busy at all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-kbl-x1275/igt at gem_busy@busy at all.html - fi-cfl-8700k: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-cfl-8700k/igt at gem_busy@busy at all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cfl-8700k/igt at gem_busy@busy at all.html - fi-skl-6600u: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-skl-6600u/igt at gem_busy@busy at all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-skl-6600u/igt at gem_busy@busy at all.html - fi-cfl-8109u: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-cfl-8109u/igt at gem_busy@busy at all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cfl-8109u/igt at gem_busy@busy at all.html - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at gem_busy@busy at all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-icl-u2/igt at gem_busy@busy at all.html - fi-glk-dsi: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-glk-dsi/igt at gem_busy@busy at all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-glk-dsi/igt at gem_busy@busy at all.html - fi-skl-lmem: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-skl-lmem/igt at gem_busy@busy at all.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-skl-lmem/igt at gem_busy@busy at all.html - fi-kbl-r: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-r/igt at gem_busy@busy at all.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-kbl-r/igt at gem_busy@busy at all.html - fi-bdw-5557u: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bdw-5557u/igt at gem_busy@busy at all.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-bdw-5557u/igt at gem_busy@busy at all.html - fi-icl-guc: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-guc/igt at gem_busy@busy at all.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-icl-guc/igt at gem_busy@busy at all.html - fi-kbl-soraka: [PASS][21] -> [DMESG-WARN][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-soraka/igt at gem_busy@busy at all.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-kbl-soraka/igt at gem_busy@busy at all.html - fi-kbl-7500u: [PASS][23] -> [DMESG-WARN][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-7500u/igt at gem_busy@busy at all.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-kbl-7500u/igt at gem_busy@busy at all.html - fi-kbl-guc: [PASS][25] -> [DMESG-WARN][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-guc/igt at gem_busy@busy at all.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-kbl-guc/igt at gem_busy@busy at all.html - fi-whl-u: [PASS][27] -> [DMESG-WARN][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-whl-u/igt at gem_busy@busy at all.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-whl-u/igt at gem_busy@busy at all.html - fi-cml-u2: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-cml-u2/igt at gem_busy@busy at all.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cml-u2/igt at gem_busy@busy at all.html - fi-bxt-dsi: [PASS][31] -> [DMESG-WARN][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bxt-dsi/igt at gem_busy@busy at all.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-bxt-dsi/igt at gem_busy@busy at all.html - fi-cml-s: [PASS][33] -> [DMESG-WARN][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-cml-s/igt at gem_busy@busy at all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cml-s/igt at gem_busy@busy at all.html - fi-cfl-guc: [PASS][35] -> [DMESG-WARN][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-cfl-guc/igt at gem_busy@busy at all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cfl-guc/igt at gem_busy@busy at all.html - fi-icl-y: [PASS][37] -> [DMESG-WARN][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-y/igt at gem_busy@busy at all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-icl-y/igt at gem_busy@busy at all.html - fi-skl-guc: [PASS][39] -> [DMESG-WARN][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-skl-guc/igt at gem_busy@busy at all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-skl-guc/igt at gem_busy@busy at all.html - fi-skl-6700k2: [PASS][41] -> [DMESG-WARN][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-skl-6700k2/igt at gem_busy@busy at all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-skl-6700k2/igt at gem_busy@busy at all.html - fi-tgl-u2: [PASS][43] -> [DMESG-WARN][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at gem_busy@busy at all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-tgl-u2/igt at gem_busy@busy at all.html * igt at gem_close_race@basic-process: - fi-ivb-3770: [PASS][45] -> [DMESG-WARN][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-ivb-3770/igt at gem_close_race@basic-process.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-ivb-3770/igt at gem_close_race@basic-process.html - fi-byt-j1900: [PASS][47] -> [DMESG-WARN][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at gem_close_race@basic-process.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-byt-j1900/igt at gem_close_race@basic-process.html - fi-hsw-4770: [PASS][49] -> [DMESG-WARN][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-hsw-4770/igt at gem_close_race@basic-process.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-hsw-4770/igt at gem_close_race@basic-process.html - fi-byt-n2820: [PASS][51] -> [DMESG-WARN][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-n2820/igt at gem_close_race@basic-process.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-byt-n2820/igt at gem_close_race@basic-process.html * igt at gem_tiled_blits@basic: - fi-bwr-2160: [PASS][53] -> [DMESG-WARN][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bwr-2160/igt at gem_tiled_blits@basic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-bwr-2160/igt at gem_tiled_blits@basic.html * igt at kms_busy@basic at flip: - fi-snb-2600: [PASS][55] -> [DMESG-WARN][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-snb-2600/igt at kms_busy@basic at flip.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-snb-2600/igt at kms_busy@basic at flip.html - fi-snb-2520m: [PASS][57] -> [DMESG-WARN][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-snb-2520m/igt at kms_busy@basic at flip.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-snb-2520m/igt at kms_busy@basic at flip.html * igt at kms_frontbuffer_tracking@basic: - fi-ilk-650: [PASS][59] -> [DMESG-WARN][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-ilk-650/igt at kms_frontbuffer_tracking@basic.html * igt at runner@aborted: - fi-cfl-8700k: NOTRUN -> [FAIL][61] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cfl-8700k/igt at runner@aborted.html - fi-cfl-8109u: NOTRUN -> [FAIL][62] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cfl-8109u/igt at runner@aborted.html - fi-icl-u2: NOTRUN -> [FAIL][63] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-icl-u2/igt at runner@aborted.html - fi-snb-2520m: NOTRUN -> [FAIL][64] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-snb-2520m/igt at runner@aborted.html - fi-bdw-5557u: NOTRUN -> [FAIL][65] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-bdw-5557u/igt at runner@aborted.html - fi-bwr-2160: NOTRUN -> [FAIL][66] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-bwr-2160/igt at runner@aborted.html - fi-byt-n2820: NOTRUN -> [FAIL][67] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-byt-n2820/igt at runner@aborted.html - fi-icl-guc: NOTRUN -> [FAIL][68] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-icl-guc/igt at runner@aborted.html - fi-hsw-4770: NOTRUN -> [FAIL][69] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-hsw-4770/igt at runner@aborted.html - fi-snb-2600: NOTRUN -> [FAIL][70] [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-snb-2600/igt at runner@aborted.html - fi-whl-u: NOTRUN -> [FAIL][71] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-whl-u/igt at runner@aborted.html - fi-cml-u2: NOTRUN -> [FAIL][72] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cml-u2/igt at runner@aborted.html - fi-ivb-3770: NOTRUN -> [FAIL][73] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-ivb-3770/igt at runner@aborted.html - fi-bxt-dsi: NOTRUN -> [FAIL][74] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-bxt-dsi/igt at runner@aborted.html - fi-byt-j1900: NOTRUN -> [FAIL][75] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-byt-j1900/igt at runner@aborted.html - fi-cml-s: NOTRUN -> [FAIL][76] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cml-s/igt at runner@aborted.html - fi-cfl-guc: NOTRUN -> [FAIL][77] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-cfl-guc/igt at runner@aborted.html - fi-icl-y: NOTRUN -> [FAIL][78] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-icl-y/igt at runner@aborted.html - fi-tgl-u2: NOTRUN -> [FAIL][79] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-tgl-u2/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at gem_busy@busy at all: - {fi-tgl-dsi}: [PASS][80] -> [DMESG-WARN][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-dsi/igt at gem_busy@busy at all.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-tgl-dsi/igt at gem_busy@busy at all.html - {fi-ehl-1}: [PASS][82] -> [DMESG-WARN][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-ehl-1/igt at gem_busy@busy at all.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-ehl-1/igt at gem_busy@busy at all.html * igt at runner@aborted: - {fi-tgl-dsi}: NOTRUN -> [FAIL][84] [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-tgl-dsi/igt at runner@aborted.html - {fi-ehl-1}: NOTRUN -> [FAIL][85] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/fi-ehl-1/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17934 that come from known issues: ### IGT changes ### {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17934 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17934: 6403c98f95cb651d38c8824b670e1172236e96a3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6403c98f95cb drm/i915: Annotate dma_fence_work 20094f452976 drm/amdgpu: gpu recovery does full modesets 823a78e8bd4d Revert "drm/amdgpu: add fbdev suspend/resume on gpu reset" e8d515333826 drm/amdgpu: use dma-fence annotations for gpu reset code 36895e1c3363 drm/scheduler: use dma-fence annotations in tdr work 7a2bb8a3d251 drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail 45b663c70065 drm/amdgpu: DC also loves to allocate stuff where it shouldn't d9ed9c09b946 drm/amdgpu: s/GFP_KERNEL/GFP_ATOMIC in scheduler code b4093fcdacd2 drm/amdgpu: use dma-fence annotations in cs_submit() c4ab594ebf4a drm/scheduler: use dma-fence annotations in main thread b6778d197cf3 drm/amdgpu: add dma-fence annotations to atomic commit path d85809aae908 drm/atomic-helper: Add dma-fence annotations 9f0f8c8303fa drm/vblank: Annotate with dma-fence signalling section b874c76322b8 drm/vkms: Annotate vblank timer 6442f8dad95b dma-fence: prime lockdep annotations 07c16f051d28 dma-fence: basic lockdep annotations ceede5e08eb8 dma-buf: minor doc touch-ups 59ff28b69eed mm: Track mmu notifiers in fs_reclaim_acquire/release == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17934/index.html From patchwork at emeril.freedesktop.org Fri Jun 12 07:37:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 07:37:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev4=29?= In-Reply-To: <20200612023533.3611774-1-matthew.d.roper@intel.com> References: <20200612023533.3611774-1-matthew.d.roper@intel.com> Message-ID: <159194743962.21335.4873669568996894263@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev4) URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618_full -> Patchwork_17933_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17933_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at bcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#1930]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-fds-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk5/igt at gem_exec_whisper@basic-fds-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-glk9/igt at gem_exec_whisper@basic-fds-all.html * igt at gem_exec_whisper@basic-forked-all: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb3/igt at gem_exec_whisper@basic-forked-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-tglb5/igt at gem_exec_whisper@basic-forked-all.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#95]) +12 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at gem_mmap_wc@write-cpu-read-wc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl4/igt at gem_mmap_wc@write-cpu-read-wc.html - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at gem_mmap_wc@write-cpu-read-wc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-kbl6/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at kms_big_fb@x-tiled-8bpp-rotate-180: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk5/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-glk9/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#46]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank at a-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl7/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl4/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html * igt at kms_flip@flip-vs-fences at a-edp1: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl3/igt at kms_flip@flip-vs-fences at a-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl8/igt at kms_flip@flip-vs-fences at a-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at b-edp1: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#198]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl10/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl9/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [PASS][27] -> [DMESG-FAIL][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#1928]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_flip_tiling@flip-yf-tiled: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl2/igt at kms_flip_tiling@flip-yf-tiled.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-kbl4/igt at kms_flip_tiling@flip-yf-tiled.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite: - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-skl: [PASS][37] -> [FAIL][38] ([i915#49]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl5/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl2/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][39] -> [DMESG-FAIL][40] ([fdo#108145] / [i915#1982]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][41] -> [FAIL][42] ([fdo#108145] / [i915#265]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-iclb7/igt at kms_psr@psr2_cursor_plane_move.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][45] -> [FAIL][46] ([i915#1542]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb2/igt at perf@blocking-parameterized.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-iclb7/igt at perf@blocking-parameterized.html - shard-hsw: [PASS][47] -> [FAIL][48] ([i915#1542]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-hsw2/igt at perf@blocking-parameterized.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-hsw6/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_exec_reloc@basic-wc-cpu-active: - shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +14 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at gem_exec_reloc@basic-wc-cpu-active.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl3/igt at gem_exec_reloc@basic-wc-cpu-active.html * igt at i915_pm_rpm@system-suspend-modeset: - shard-skl: [INCOMPLETE][51] ([i915#151] / [i915#69]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl9/igt at i915_pm_rpm@system-suspend-modeset.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl5/igt at i915_pm_rpm@system-suspend-modeset.html * igt at i915_selftest@perf at request: - shard-tglb: [INCOMPLETE][53] ([i915#1823]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-tglb7/igt at i915_selftest@perf at request.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-tglb5/igt at i915_selftest@perf at request.html * igt at kms_big_fb@x-tiled-32bpp-rotate-0: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl3/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-kbl1/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html * igt at kms_big_fb@y-tiled-32bpp-rotate-0: - shard-glk: [FAIL][57] ([i915#1119]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk4/igt at kms_big_fb@y-tiled-32bpp-rotate-0.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-glk7/igt at kms_big_fb@y-tiled-32bpp-rotate-0.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][59] ([i915#118] / [i915#95]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +4 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl3/igt at kms_color@pipe-a-ctm-0-5.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl8/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +5 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2: - shard-glk: [FAIL][65] ([i915#79]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-glk9/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at b-dp1: - shard-apl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl1/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1: - shard-skl: [FAIL][69] ([i915#1928]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][71] ([i915#1188]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb3/igt at kms_psr@psr2_no_drrs.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-iclb2/igt at kms_psr@psr2_no_drrs.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [DMESG-WARN][77] ([i915#1982]) -> [PASS][78] +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [INCOMPLETE][79] ([i915#1635] / [i915#1958] / [i915#95]) -> [INCOMPLETE][80] ([i915#1635] / [i915#1958]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl1/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rc6_residency@rc6-idle: - shard-iclb: [FAIL][81] ([i915#1515]) -> [WARN][82] ([i915#1515]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-iclb7/igt at i915_pm_rc6_residency@rc6-idle.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-iclb8/igt at i915_pm_rc6_residency@rc6-idle.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [FAIL][83] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl2/igt at kms_content_protection@atomic-dpms.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@legacy: - shard-kbl: [TIMEOUT][85] ([i915#1319] / [i915#1958]) -> [TIMEOUT][86] ([i915#1319]) +1 similar issue [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-kbl4/igt at kms_content_protection@legacy.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-kbl3/igt at kms_content_protection@legacy.html - shard-apl: [FAIL][87] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][88] ([i915#1319]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl4/igt at kms_content_protection@legacy.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl1/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][89] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][90] ([fdo#110321]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl8/igt at kms_content_protection@lic.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl8/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [TIMEOUT][91] ([i915#1319] / [i915#1635]) -> [FAIL][92] ([fdo#110321]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/shard-apl3/igt at kms_content_protection@srm.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/shard-apl7/igt at kms_content_protection@srm.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17933 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17933: c71cca7b9a9f9b18d2511d9fbff97ba523730f8a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17933/index.html From vandita.kulkarni at intel.com Fri Jun 12 08:22:37 2020 From: vandita.kulkarni at intel.com (Vandita Kulkarni) Date: Fri, 12 Jun 2020 13:52:37 +0530 Subject: [Intel-gfx] [PATCH] drm/i915/display: Fix the encoder type check Message-ID: <20200612082237.11886-1-vandita.kulkarni@intel.com> For all ddi, encoder->type holds output type as ddi, assigning it to individual o/p types is no more valid. Fixes: 362bfb995b78 ("drm/i915/tgl: Add DKL PHY vswing table for HDMI") v2: Rebase, no functional change. Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com> Reviewed-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d1acc39cdc11..ca7bb2294d2b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2615,7 +2615,7 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, static void tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, - u32 level) + u32 level, enum intel_output_type type) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); @@ -2623,7 +2623,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; int rate = 0; - if (encoder->type != INTEL_OUTPUT_HDMI) { + if (type == INTEL_OUTPUT_HDMI) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); rate = intel_dp->link_rate; @@ -2676,7 +2676,7 @@ static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, if (intel_phy_is_combo(dev_priv, phy)) icl_combo_phy_ddi_vswing_sequence(encoder, level, type); else - tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); + tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type); } static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels) -- 2.21.0.5.gaeb582a From uma.shankar at intel.com Fri Jun 12 08:38:24 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Fri, 12 Jun 2020 08:38:24 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/display: Fix the encoder type check In-Reply-To: <20200612082237.11886-1-vandita.kulkarni@intel.com> References: <20200612082237.11886-1-vandita.kulkarni@intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F825244D8@BGSMSX104.gar.corp.intel.com> > -----Original Message----- > From: Kulkarni, Vandita <vandita.kulkarni at intel.com> > Sent: Friday, June 12, 2020 1:53 PM > To: intel-gfx at lists.freedesktop.org > Cc: Shankar, Uma <uma.shankar at intel.com>; Kulkarni, Vandita > <vandita.kulkarni at intel.com> > Subject: [PATCH] drm/i915/display: Fix the encoder type check > > For all ddi, encoder->type holds output type as ddi, assigning it to individual o/p > types is no more valid. > > Fixes: 362bfb995b78 ("drm/i915/tgl: Add DKL PHY vswing table for HDMI") > > v2: Rebase, no functional change. Pushed the change to dinq. Thanks for the patch. Regards, Uma Shankar > Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com> > Reviewed-by: Uma Shankar <uma.shankar at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index d1acc39cdc11..ca7bb2294d2b 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2615,7 +2615,7 @@ static void icl_ddi_vswing_sequence(struct > intel_encoder *encoder, > > static void > tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, > - u32 level) > + u32 level, enum intel_output_type type) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); @@ - > 2623,7 +2623,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder > *encoder, int link_clock, > u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; > int rate = 0; > > - if (encoder->type != INTEL_OUTPUT_HDMI) { > + if (type == INTEL_OUTPUT_HDMI) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > rate = intel_dp->link_rate; > @@ -2676,7 +2676,7 @@ static void tgl_ddi_vswing_sequence(struct > intel_encoder *encoder, > if (intel_phy_is_combo(dev_priv, phy)) > icl_combo_phy_ddi_vswing_sequence(encoder, level, type); > else > - tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level); > + tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, > type); > } > > static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels) > -- > 2.21.0.5.gaeb582a From matthew.auld at intel.com Fri Jun 12 09:04:55 2020 From: matthew.auld at intel.com (Matthew Auld) Date: Fri, 12 Jun 2020 10:04:55 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Leave vma intact as they are discarded In-Reply-To: <20200611180421.23262-1-chris@chris-wilson.co.uk> References: <20200611180421.23262-1-chris@chris-wilson.co.uk> Message-ID: <2d5c000f-f35d-d095-93af-0f8e0f39f745@intel.com> On 11/06/2020 19:04, Chris Wilson wrote: > If we find ourselves trying to reuse a misplaced but active vma, we > currently try to discard it to avoid having to wait to unbind it > (upsetting the current user fo the vma). An alternative to marking it as > a dicarded vma and keeping it in both the obj->vma.list and > obj->vma.tree, is to simply remove it from the lookup rbtree. > > While it remains in the list of vma, it will be unbound under eviction > pressure and freed along with the object. We will never reuse it again > for new instances. As before, with no pruning, the list may continually > grow, but eventually we will have the most constrained version of the > ggtt view that meets all requirements -- so the list of vma should not > grow without bound. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2012 > Fixes: 9bdcaa5e3a2f ("drm/i915: Discard a misplaced GGTT vma") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Matthew Auld <matthew.auld at intel.com> Seems much simpler, Reviewed-by: Matthew Auld <matthew.auld at intel.com> From chris at chris-wilson.co.uk Fri Jun 12 09:11:42 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 10:11:42 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Leave vma intact as they are discarded In-Reply-To: <2d5c000f-f35d-d095-93af-0f8e0f39f745@intel.com> References: <20200611180421.23262-1-chris@chris-wilson.co.uk> <2d5c000f-f35d-d095-93af-0f8e0f39f745@intel.com> Message-ID: <159195310296.1506.8748866161247032009@build.alporthouse.com> Quoting Matthew Auld (2020-06-12 10:04:55) > On 11/06/2020 19:04, Chris Wilson wrote: > > If we find ourselves trying to reuse a misplaced but active vma, we > > currently try to discard it to avoid having to wait to unbind it > > (upsetting the current user fo the vma). An alternative to marking it as > > a dicarded vma and keeping it in both the obj->vma.list and > > obj->vma.tree, is to simply remove it from the lookup rbtree. > > > > While it remains in the list of vma, it will be unbound under eviction > > pressure and freed along with the object. We will never reuse it again > > for new instances. As before, with no pruning, the list may continually > > grow, but eventually we will have the most constrained version of the > > ggtt view that meets all requirements -- so the list of vma should not > > grow without bound. > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2012 > > Fixes: 9bdcaa5e3a2f ("drm/i915: Discard a misplaced GGTT vma") > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Matthew Auld <matthew.auld at intel.com> > > Seems much simpler, > Reviewed-by: Matthew Auld <matthew.auld at intel.com> Yeah, the cost being that the rbtree is not complete (and we have to be careful about double removals). But we only use the tree for lookup and walk the list for everything else. My fear is that it will be an unpleasant surprise later. -Chris From mika.kuoppala at linux.intel.com Fri Jun 12 09:14:55 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Fri, 12 Jun 2020 12:14:55 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <87eeqk8x2o.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a > subsequent read from e.g. the sampler can bypass the store and read the > stale value from memory. This is a serious issue when we are using MI > stores to rewrite the batches for relocation, as it means that the batch > is reading from random user/kernel memory. While it is particularly > sensitive [and detectable] for relocations, reading stale data at any > time is a worry. > > Having started with a small number of delaying stores and doubling until > no more incoherency was seen over a few hours (with and without > background memory pressure), 32 was the magic number. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > --- > So gen3 requires a delay after to flush the previous stores, gen5 is > assuming it requires a delay between the seqno and the > MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I > need to verify that it still holds. > --- > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++--------------- > 1 file changed, 15 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > index 3fb0dc1fb910..342c476ec872 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > @@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) > return 0; > } > > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count) > { > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > > *cs++ = MI_FLUSH; > + *cs++ = MI_NOOP; > + > + while (count--) { > + *cs++ = MI_STORE_DWORD_INDEX; > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); > + *cs++ = rq->fence.seqno; > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; Why would you avoid write flush here? -Mika > + } > > *cs++ = MI_STORE_DWORD_INDEX; > *cs++ = I915_GEM_HWS_SEQNO_ADDR; > *cs++ = rq->fence.seqno; > > *cs++ = MI_USER_INTERRUPT; > - *cs++ = MI_NOOP; > > rq->tail = intel_ring_offset(rq, cs); > assert_ring_tail_valid(rq->ring, rq->tail); > @@ -162,31 +169,15 @@ u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > return cs; > } > > -#define GEN5_WA_STORES 8 /* must be at least 1! */ > -u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > { > - int i; > - > - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > - > - *cs++ = MI_FLUSH; > - > - BUILD_BUG_ON(GEN5_WA_STORES < 1); > - for (i = 0; i < GEN5_WA_STORES; i++) { > - *cs++ = MI_STORE_DWORD_INDEX; > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; > - *cs++ = rq->fence.seqno; > - } > - > - *cs++ = MI_USER_INTERRUPT; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > + return __gen2_emit_breadcrumb(rq, cs, 32); > +} > > - return cs; > +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +{ > + return __gen2_emit_breadcrumb(rq, cs, 8); > } > -#undef GEN5_WA_STORES > > /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ > #define I830_BATCH_LIMIT SZ_256K > -- > 2.20.1 From chris at chris-wilson.co.uk Fri Jun 12 09:23:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 10:23:30 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <87eeqk8x2o.fsf@gaia.fi.intel.com> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> <87eeqk8x2o.fsf@gaia.fi.intel.com> Message-ID: <159195381083.1506.15524005315925573285@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-12 10:14:55) > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a > > subsequent read from e.g. the sampler can bypass the store and read the > > stale value from memory. This is a serious issue when we are using MI > > stores to rewrite the batches for relocation, as it means that the batch > > is reading from random user/kernel memory. While it is particularly > > sensitive [and detectable] for relocations, reading stale data at any > > time is a worry. > > > > Having started with a small number of delaying stores and doubling until > > no more incoherency was seen over a few hours (with and without > > background memory pressure), 32 was the magic number. > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 > > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > > --- > > So gen3 requires a delay after to flush the previous stores, gen5 is > > assuming it requires a delay between the seqno and the > > MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I > > need to verify that it still holds. > > --- > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++--------------- > > 1 file changed, 15 insertions(+), 24 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > index 3fb0dc1fb910..342c476ec872 100644 > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > @@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) > > return 0; > > } > > > > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count) > > { > > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > > > > *cs++ = MI_FLUSH; > > + *cs++ = MI_NOOP; > > + > > + while (count--) { > > + *cs++ = MI_STORE_DWORD_INDEX; > > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); > > + *cs++ = rq->fence.seqno; > > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > > Why would you avoid write flush here? It's a flush of the render caches; all I'm using it for here is a delay. As evidenced, MI_FLUSH does not flush the stores by itself. 32 is an awful lot of papering. I should note that for gen5 not only did we have the delay in the breadcrumb but also in the invalidation. Maybe that would help for gen3 -Chris From chris at chris-wilson.co.uk Fri Jun 12 09:40:32 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 10:40:32 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <159195381083.1506.15524005315925573285@build.alporthouse.com> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> <87eeqk8x2o.fsf@gaia.fi.intel.com> <159195381083.1506.15524005315925573285@build.alporthouse.com> Message-ID: <159195483208.1506.5377359247926167271@build.alporthouse.com> Quoting Chris Wilson (2020-06-12 10:23:30) > Quoting Mika Kuoppala (2020-06-12 10:14:55) > > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > > > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a > > > subsequent read from e.g. the sampler can bypass the store and read the > > > stale value from memory. This is a serious issue when we are using MI > > > stores to rewrite the batches for relocation, as it means that the batch > > > is reading from random user/kernel memory. While it is particularly > > > sensitive [and detectable] for relocations, reading stale data at any > > > time is a worry. > > > > > > Having started with a small number of delaying stores and doubling until > > > no more incoherency was seen over a few hours (with and without > > > background memory pressure), 32 was the magic number. > > > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 > > > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > > > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > > > --- > > > So gen3 requires a delay after to flush the previous stores, gen5 is > > > assuming it requires a delay between the seqno and the > > > MI_USER_INTERRUPT. Here I've made gen5 reuse the gen3 approach, but I > > > need to verify that it still holds. > > > --- > > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 39 +++++++++--------------- > > > 1 file changed, 15 insertions(+), 24 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > > index 3fb0dc1fb910..342c476ec872 100644 > > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > > @@ -142,19 +142,26 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) > > > return 0; > > > } > > > > > > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > > > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, int count) > > > { > > > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > > > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > > > > > > *cs++ = MI_FLUSH; > > > + *cs++ = MI_NOOP; > > > + > > > + while (count--) { > > > + *cs++ = MI_STORE_DWORD_INDEX; > > > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); > > > + *cs++ = rq->fence.seqno; > > > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > > > > Why would you avoid write flush here? > > It's a flush of the render caches; all I'm using it for here is a delay. > As evidenced, MI_FLUSH does not flush the stores by itself. > > 32 is an awful lot of papering. I should note that for gen5 not only did > we have the delay in the breadcrumb but also in the invalidation. Maybe > that would help for gen3 Well that was easy. Splitting the w/a between the breadcrumb and the invalidate does not help to reduce the burden [the number of stores required to make the incoherency go away] of the w/a. -Chris From ramadevi.gandi at intel.com Fri Jun 12 10:03:53 2020 From: ramadevi.gandi at intel.com (ramadevi.gandi at intel.com) Date: Fri, 12 Jun 2020 15:33:53 +0530 Subject: [Intel-gfx] [PATCH] intel: sync i915_pciids.h with kernel Message-ID: <20200612100353.14461-1-ramadevi.gandi@intel.com> From: Gandi Ramadevi <ramadevi.gandi at intel.com> Add DG1 PCI ID Signed-off-by: Gandi Ramadevi <ramadevi.gandi at intel.com> --- intel/i915_pciids.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h index 662d8351..3de6e574 100644 --- a/intel/i915_pciids.h +++ b/intel/i915_pciids.h @@ -605,4 +605,8 @@ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) +/* DG1 */ +#define INTEL_DG1_IDS(info) \ + INTEL_VGA_DEVICE(0x4905, info) + #endif /* _I915_PCIIDS_H */ -- 2.25.1 From patchwork at emeril.freedesktop.org Fri Jun 12 10:24:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 10:24:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_Fix_the_encoder_type_check_=28rev2=29?= In-Reply-To: <20200612082237.11886-1-vandita.kulkarni@intel.com> References: <20200612082237.11886-1-vandita.kulkarni@intel.com> Message-ID: <159195744756.21337.11998121159699157318@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Fix the encoder type check (rev2) URL : https://patchwork.freedesktop.org/series/76891/ State : failure == Summary == Applying: drm/i915/display: Fix the encoder type check Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_ddi.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. From patchwork at emeril.freedesktop.org Fri Jun 12 10:25:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 10:25:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBp?= =?utf-8?q?ntel=3A_sync_i915=5Fpciids=2Eh_with_kernel?= In-Reply-To: <20200612100353.14461-1-ramadevi.gandi@intel.com> References: <20200612100353.14461-1-ramadevi.gandi@intel.com> Message-ID: <159195751141.21337.4817390378616420878@emeril.freedesktop.org> == Series Details == Series: intel: sync i915_pciids.h with kernel URL : https://patchwork.freedesktop.org/series/78256/ State : failure == Summary == Applying: intel: sync i915_pciids.h with kernel Using index info to reconstruct a base tree... A intel/i915_pciids.h Falling back to patching base and 3-way merge... Auto-merging include/drm/i915_pciids.h CONFLICT (content): Merge conflict in include/drm/i915_pciids.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 intel: sync i915_pciids.h with kernel When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From andriy.shevchenko at linux.intel.com Fri Jun 12 11:57:32 2020 From: andriy.shevchenko at linux.intel.com (Andy Shevchenko) Date: Fri, 12 Jun 2020 14:57:32 +0300 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-4-hdegoede@redhat.com> <20200608035023.GZ2428291@smile.fi.intel.com> <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> <20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org> Message-ID: <20200612115732.GC2428291@smile.fi.intel.com> On Fri, Jun 12, 2020 at 12:12:42AM +0200, Uwe Kleine-K?nig wrote: > On Mon, Jun 08, 2020 at 01:07:12PM +0200, Hans de Goede wrote: > > On 6/8/20 5:50 AM, Andy Shevchenko wrote: > > > On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote: > > > > When the user requests a high enough period ns value, then the > > > > calculations in pwm_lpss_prepare() might result in a base_unit value of 0. > > > > > > > > But according to the data-sheet the way the PWM controller works is that > > > > each input clock-cycle the base_unit gets added to a N bit counter and > > > > that counter overflowing determines the PWM output frequency. Adding 0 > > > > to the counter is a no-op. The data-sheet even explicitly states that > > > > writing 0 to the base_unit bits will result in the PWM outputting a > > > > continuous 0 signal. > > > > > > So, and why it's a problem? > > > > Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail > > which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 = > > 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will > > now get a pin which is always outputting low. > > I didn't follow the complete discussion but note that the general rule > is: > > round period down to the next possible implementable period > round duty_cycle down to the next possible implementable duty_cycle > > so if a small enough period (and so a small duty_cycle) is requested it > is expected that duty_cycle will be zero. ...which brings me an idea that PWM framework should expose API to get a capabilities, like DMA Engine has. In such capabilities, in particular, caller can get ranges of the correct frequencies of the underneath hardware. -- With Best Regards, Andy Shevchenko From imre.deak at intel.com Fri Jun 12 12:17:31 2020 From: imre.deak at intel.com (Imre Deak) Date: Fri, 12 Jun 2020 15:17:31 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/icl+: Fix hotplug interrupt disabling after storm detection Message-ID: <20200612121731.19596-1-imre.deak@intel.com> Atm, hotplug interrupts on TypeC ports are left enabled after detecting an interrupt storm, fix this. Reported-by: Kunal Joshi <kunal1.joshi at intel.com> References: https://gitlab.freedesktop.org/drm/intel/-/issues/351 Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/1964 Cc: Kunal Joshi <kunal1.joshi at intel.com> Cc: stable at vger.kernel.org Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8e823ba25f5f..710224d930c5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3132,6 +3132,7 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) val = I915_READ(GEN11_DE_HPD_IMR); val &= ~hotplug_irqs; + val |= ~enabled_irqs & hotplug_irqs; I915_WRITE(GEN11_DE_HPD_IMR, val); POSTING_READ(GEN11_DE_HPD_IMR); -- 2.23.1 From chris at chris-wilson.co.uk Fri Jun 12 12:39:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 13:39:49 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <20200612123949.7093-1-chris@chris-wilson.co.uk> gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a subsequent read from e.g. the sampler can bypass the store and read the stale value from memory. This is a serious issue when we are using MI stores to rewrite the batches for relocation, as it means that the batch is reading from random user/kernel memory. While it is particularly sensitive [and detectable] for relocations, reading stale data at any time is a worry. Having started with a small number of delaying stores and doubling until no more incoherency was seen over a few hours (with and without background memory pressure), 32 was the magic number. v2: Follow more closer with the gen5 w/a and include some post-invalidate flushes as well. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> --- drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++-------------- 1 file changed, 25 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c index 3fb0dc1fb910..5400d657f334 100644 --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c @@ -13,28 +13,25 @@ int gen2_emit_flush(struct i915_request *rq, u32 mode) { - unsigned int num_store_dw; + unsigned int num_store_dw = 12; u32 cmd, *cs; cmd = MI_FLUSH; - num_store_dw = 0; if (mode & EMIT_INVALIDATE) cmd |= MI_READ_FLUSH; - if (mode & EMIT_FLUSH) - num_store_dw = 4; - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); if (IS_ERR(cs)) return PTR_ERR(cs); *cs++ = cmd; while (num_store_dw--) { - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; - *cs++ = intel_gt_scratch_offset(rq->engine->gt, - INTEL_GT_SCRATCH_FIELD_DEFAULT); - *cs++ = 0; + *cs++ = MI_STORE_DWORD_INDEX; + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); + *cs++ = rq->fence.seqno - 1; + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; } - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; + *cs++ = cmd; intel_ring_advance(rq, cs); @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) return 0; } -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, + int flush, int post) { GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); *cs++ = MI_FLUSH; - *cs++ = MI_STORE_DWORD_INDEX; - *cs++ = I915_GEM_HWS_SEQNO_ADDR; - *cs++ = rq->fence.seqno; - - *cs++ = MI_USER_INTERRUPT; - *cs++ = MI_NOOP; - - rq->tail = intel_ring_offset(rq, cs); - assert_ring_tail_valid(rq->ring, rq->tail); - - return cs; -} - -#define GEN5_WA_STORES 8 /* must be at least 1! */ -u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) -{ - int i; - - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); - - *cs++ = MI_FLUSH; + while (flush--) { + *cs++ = MI_STORE_DWORD_INDEX; + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); + *cs++ = rq->fence.seqno; + } - BUILD_BUG_ON(GEN5_WA_STORES < 1); - for (i = 0; i < GEN5_WA_STORES; i++) { + while (post--) { *cs++ = MI_STORE_DWORD_INDEX; *cs++ = I915_GEM_HWS_SEQNO_ADDR; *cs++ = rq->fence.seqno; @@ -186,7 +166,16 @@ u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) return cs; } -#undef GEN5_WA_STORES + +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) +{ + return __gen2_emit_breadcrumb(rq, cs, 16, 8); +} + +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) +{ + return __gen2_emit_breadcrumb(rq, cs, 8, 8); +} /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ #define I830_BATCH_LIMIT SZ_256K -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 12 13:04:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 13:04:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/icl+=3A_Fix_hotplug_interrupt_disabling_after_storm_detec?= =?utf-8?q?tion?= In-Reply-To: <20200612121731.19596-1-imre.deak@intel.com> References: <20200612121731.19596-1-imre.deak@intel.com> Message-ID: <159196705993.21336.14083495618624409936@emeril.freedesktop.org> == Series Details == Series: drm/i915/icl+: Fix hotplug interrupt disabling after storm detection URL : https://patchwork.freedesktop.org/series/78258/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17937 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17937 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17937, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17937: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-bdw-5557u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17937 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][4] ([i915#95]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][8] ([i915#1993]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][19] ([i915#62] / [i915#92]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92]) -> [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17937 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17937: a09f4bc8ddb9cfad0f18bdaccada93f9e98d5c54 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a09f4bc8ddb9 drm/i915/icl+: Fix hotplug interrupt disabling after storm detection == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html From patchwork at emeril.freedesktop.org Fri Jun 12 13:07:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 13:07:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gt=3A_Flush_gen3_relocs_harder=2C_again_=28rev2=29?= In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <159196726953.21338.2041406522726074941@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Flush gen3 relocs harder, again (rev2) URL : https://patchwork.freedesktop.org/series/78230/ State : warning == Summary == $ dim checkpatch origin/drm-tip e754040f8747 drm/i915/gt: Flush gen3 relocs harder, again -:22: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit a889580c087a ("drm/i915: Flush GPU relocs harder for gen3")' #22: References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") total: 1 errors, 0 warnings, 0 checks, 98 lines checked From ville.syrjala at linux.intel.com Fri Jun 12 13:18:48 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 16:18:48 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/icl+: Fix hotplug interrupt disabling after storm detection In-Reply-To: <20200612121731.19596-1-imre.deak@intel.com> References: <20200612121731.19596-1-imre.deak@intel.com> Message-ID: <20200612131848.GH6112@intel.com> On Fri, Jun 12, 2020 at 03:17:31PM +0300, Imre Deak wrote: > Atm, hotplug interrupts on TypeC ports are left enabled after detecting > an interrupt storm, fix this. > > Reported-by: Kunal Joshi <kunal1.joshi at intel.com> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/351 > Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/1964 > Cc: Kunal Joshi <kunal1.joshi at intel.com> > Cc: stable at vger.kernel.org > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 8e823ba25f5f..710224d930c5 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3132,6 +3132,7 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) > > val = I915_READ(GEN11_DE_HPD_IMR); > val &= ~hotplug_irqs; > + val |= ~enabled_irqs & hotplug_irqs; > I915_WRITE(GEN11_DE_HPD_IMR, val); > POSTING_READ(GEN11_DE_HPD_IMR); Wondering if we should add a function for this just for consistency with all the other platforms. Alhthough we don't strictly need one since we have no other users of this register. So maybe not. Anyways, patch is Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From imre.deak at intel.com Fri Jun 12 13:20:20 2020 From: imre.deak at intel.com (Imre Deak) Date: Fri, 12 Jun 2020 16:20:20 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/icl+=3A_Fix_hotplug_interrupt_disabling_after_storm_detec?= =?utf-8?q?tion?= In-Reply-To: <159196705993.21336.14083495618624409936@emeril.freedesktop.org> References: <20200612121731.19596-1-imre.deak@intel.com> <159196705993.21336.14083495618624409936@emeril.freedesktop.org> Message-ID: <20200612132020.GC15242@ideak-desk.fi.intel.com> On Fri, Jun 12, 2020 at 01:04:19PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/icl+: Fix hotplug interrupt disabling after storm detection > URL : https://patchwork.freedesktop.org/series/78258/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17937 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17937 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17937, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17937: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at runner@aborted: > - fi-bdw-5557u: NOTRUN -> [FAIL][1] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-bdw-5557u/igt at runner@aborted.html This is on an unrelated platform. It looks like a network problem after resuming: [149.557805] [117/171] (880s left) kms_pipe_crc_basic (suspend-read-crc-pipe-a) Starting subtest: suspend-read-crc-pipe-A Subtest suspend-read-crc-pipe-A: SUCCESS (2.860s) [191.138997] Aborting: Ping host did not respond to ping, network down [191.140340] Closing watchdogs So jenkins timing out after 50 seconds, even though the machine is still up for 5 minutes after suspend-read-crc-pipe-A completes. The network connection seems to be up as well: <7>[ 134.716964] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A ... <7>[ 137.578228] [IGT] kms_pipe_crc_basic: exiting, ret=0 <6>[ 137.588883] Console: switching to colour frame buffer device 240x67 <6>[ 142.597964] e1000e 0000:00:19.0 enp0s25: NIC Link is Up 10 Mbps Full Duplex, Flow Control: None <6>[ 439.818733] kworker/dying (178) used greatest stack depth: 11424 bytes left > Known issues > ------------ > > Here are the changes found in Patchwork_17937 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: > - fi-icl-u2: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html > > > #### Possible fixes #### > > * igt at i915_pm_backlight@basic-brightness: > - fi-whl-u: [DMESG-WARN][4] ([i915#95]) -> [PASS][5] > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html > > * igt at i915_pm_rpm@module-reload: > - fi-glk-dsi: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html > > * igt at i915_selftest@live at execlists: > - fi-icl-y: [DMESG-FAIL][8] ([i915#1993]) -> [PASS][9] > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-y/igt at i915_selftest@live at execlists.html > > * igt at kms_busy@basic at flip: > - fi-kbl-x1275: [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][11] > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_busy@basic at flip.html > > * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-icl-u2: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > - fi-bsw-kefka: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: > - fi-icl-guc: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17] > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html > > > #### Warnings #### > > * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: > - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][19] ([i915#62] / [i915#92]) +4 similar issues > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html > > * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: > - fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92]) -> [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html > > > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (49 -> 43) > ------------------------------ > > Additional (1): fi-tgl-u2 > Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * Linux: CI_DRM_8621 -> Patchwork_17937 > > CI-20190529: 20190529 > CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17937: a09f4bc8ddb9cfad0f18bdaccada93f9e98d5c54 @ git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > a09f4bc8ddb9 drm/i915/icl+: Fix hotplug interrupt disabling after storm detection > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html From patchwork at emeril.freedesktop.org Fri Jun 12 13:30:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 13:30:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Flush_gen3_relocs_harder=2C_again_=28rev2=29?= In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <159196861028.21335.2742318276840499058@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Flush gen3 relocs harder, again (rev2) URL : https://patchwork.freedesktop.org/series/78230/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17938 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/index.html Known issues ------------ Here are the changes found in Patchwork_17938 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-byt-n2820/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-skl-6700k2: [PASS][5] -> [INCOMPLETE][6] ([i915#151]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-skl-6700k2/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-skl-6700k2/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][7] ([i915#1993]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17938 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17938: e754040f87476d5c11086ff3064211105297c0fa @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e754040f8747 drm/i915/gt: Flush gen3 relocs harder, again == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/index.html From chris at chris-wilson.co.uk Fri Jun 12 14:25:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 15:25:49 +0100 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/execlists: Lift opportunistic process_csb to before engine lock Message-ID: <20200612142551.30956-1-chris@chris-wilson.co.uk> Since the process_csb() does not require us to hold the engine->active.lock, we can move the opportunistic flush before direction submission to outside of the lock. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 5ab0ed35af84..e866b8d721ed 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3170,13 +3170,6 @@ static void __submit_queue_imm(struct intel_engine_cs *engine) if (reset_in_progress(execlists)) return; /* defer until we restart the engine following reset */ - /* Hopefully we clear execlists->pending[] to let us through */ - if (READ_ONCE(execlists->pending[0]) && - tasklet_trylock(&execlists->tasklet)) { - process_csb(engine); - tasklet_unlock(&execlists->tasklet); - } - __execlists_submission_tasklet(engine); } @@ -3199,11 +3192,25 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } +static void flush_csb(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists *el = &engine->execlists; + + if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { + if (!reset_in_progress(el)) + process_csb(engine); + tasklet_unlock(&el->tasklet); + } +} + static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; + /* Hopefully we clear execlists->pending[] to let us through */ + flush_csb(engine); + /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 12 14:25:51 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 15:25:51 +0100 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/execlists: Defer schedule_out until after the next dequeue In-Reply-To: <20200612142551.30956-1-chris@chris-wilson.co.uk> References: <20200612142551.30956-1-chris@chris-wilson.co.uk> Message-ID: <20200612142551.30956-3-chris@chris-wilson.co.uk> Inside schedule_out, we do extra work upon idling the context, such as updating the runtime, kicking off retires, kicking virtual engines. However, if we are in a series of processing single requests per contexts, we may find ourselves scheduling out the context, only to immediately schedule it back in during dequeue. This is just extra work that we can avoid if we keep the context marked as inflight across the dequeue. This becomes more significant later on for minimising virtual engine misses. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 35 ++++++++++++++++--- 4 files changed, 48 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 4954b0df4864..b63db45bab7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -45,8 +45,8 @@ struct intel_context { struct intel_engine_cs *engine; struct intel_engine_cs *inflight; -#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2) -#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2) +#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 3) +#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 3) struct i915_address_space *vm; struct i915_gem_context __rcu *gem_context; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 20d0a923f517..3943356adae7 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -515,6 +515,8 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine) memset(execlists->pending, 0, sizeof(execlists->pending)); execlists->active = memset(execlists->inflight, 0, sizeof(execlists->inflight)); + execlists->inactive = + memset(execlists->post, 0, sizeof(execlists->post)); execlists->queue_priority_hint = INT_MIN; execlists->queue = RB_ROOT_CACHED; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 073c3769e8cc..31cf60cef5a8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -208,6 +208,10 @@ struct intel_engine_execlists { * @active: the currently known context executing on HW */ struct i915_request * const *active; + /** + * @inactive: the current vacancy of completed CS + */ + struct i915_request **inactive; /** * @inflight: the set of contexts submitted and acknowleged by HW * @@ -225,6 +229,15 @@ struct intel_engine_execlists { * preemption or idle-to-active event. */ struct i915_request *pending[EXECLIST_MAX_PORTS + 1]; + /** + * @post: the set of completed context switches + * + * Since we may want to stagger the processing of the CS switches + * with the next submission, so that the context are notionally + * kept in flight across the dequeue, we defer scheduling out of + * the completed context switches. + */ + struct i915_request *post[2 * EXECLIST_MAX_PORTS + 1]; /** * @port_mask: number of execlist ports - 1 diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index f2906b9fb508..c91a09f7c259 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1385,6 +1385,8 @@ __execlists_schedule_in(struct i915_request *rq) execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); + CE_TRACE(ce, "schedule-in, ccid:%x\n", ce->lrc.ccid); + return engine; } @@ -1431,6 +1433,8 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ + CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + /* * If we have just completed this context, the engine may now be * idle and we want to re-enter powersaving. @@ -2055,9 +2059,10 @@ static void set_preempt_timeout(struct intel_engine_cs *engine, active_preempt_timeout(engine, rq)); } -static inline void clear_ports(struct i915_request **ports, int count) +static inline struct i915_request ** +clear_ports(struct i915_request **ports, int count) { - memset_p((void **)ports, NULL, count); + return memset_p((void **)ports, NULL, count); } static void execlists_dequeue(struct intel_engine_cs *engine) @@ -2455,6 +2460,11 @@ cancel_port_requests(struct intel_engine_execlists * const execlists) { struct i915_request * const *port; + for (port = execlists->post; *port; port++) + execlists_schedule_out(*port); + execlists->inactive = + clear_ports(execlists->post, ARRAY_SIZE(execlists->post)); + for (port = execlists->pending; *port; port++) execlists_schedule_out(*port); clear_ports(execlists->pending, ARRAY_SIZE(execlists->pending)); @@ -2622,7 +2632,7 @@ static void process_csb(struct intel_engine_cs *engine) /* cancel old inflight, prepare for switch */ trace_ports(execlists, "preempted", old); while (*old) - execlists_schedule_out(*old++); + *execlists->inactive++ = *old++; /* switch pending to inflight */ GEM_BUG_ON(!assert_pending_valid(execlists, "promote")); @@ -2679,7 +2689,7 @@ static void process_csb(struct intel_engine_cs *engine) regs[CTX_RING_TAIL]); } - execlists_schedule_out(*execlists->active++); + *execlists->inactive++ = *execlists->active++; GEM_BUG_ON(execlists->active - execlists->inflight > execlists_num_ports(execlists)); @@ -2703,6 +2713,20 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } +static void post_process_csb(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request **port; + + if (!el->post[0]) + return; + + GEM_BUG_ON(el->post[2 * EXECLIST_MAX_PORTS]); + for (port = el->post; *port; port++) + execlists_schedule_out(*port); + el->inactive = clear_ports(el->post, port - el->post); +} + static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3123,6 +3147,8 @@ static void execlists_submission_tasklet(unsigned long data) spin_unlock_irqrestore(&engine->active.lock, flags); rcu_read_unlock(); } + + post_process_csb(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -4163,6 +4189,7 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) mb(); process_csb(engine); /* drain preemption events */ + post_process_csb(engine); /* Following the reset, we need to reload the CSB read/write pointers */ reset_csb_pointers(engine); -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 12 14:25:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 15:25:50 +0100 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/execlists: Replace direct submit with direct call to tasklet In-Reply-To: <20200612142551.30956-1-chris@chris-wilson.co.uk> References: <20200612142551.30956-1-chris@chris-wilson.co.uk> Message-ID: <20200612142551.30956-2-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 ++++----- drivers/gpu/drm/i915/gt/intel_lrc.c | 70 ++++++++--------------- 3 files changed, 40 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..c77b3c0d2b3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -210,6 +210,7 @@ int intel_engine_resume(struct intel_engine_cs *engine); int intel_ring_submission_setup(struct intel_engine_cs *engine); +void __intel_engine_stop_cs(struct intel_engine_cs *engine); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index d613cf31970c..20d0a923f517 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,33 +903,34 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +void __intel_engine_stop_cs(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); - int err; + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + intel_uncore_posting_read_fw(uncore, mode); +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + __intel_engine_stop_cs(engine); - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, + if (__intel_wait_for_register_fw(engine->uncore, + RING_MI_MODE(engine->mmio_base), + MODE_IDLE, MODE_IDLE, 1000, stop_timeout(engine), NULL)) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); - err = -ETIMEDOUT; + return -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - - return err; + return 0; } void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..f2906b9fb508 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2703,16 +2703,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3102,7 +3092,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3112,7 +3102,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3122,16 +3111,17 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); + + if (!engine->execlists.pending[0]) { unsigned long flags; + rcu_read_lock(); /* protect peeking at execlists->active */ spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); + execlists_dequeue(engine); spin_unlock_irqrestore(&engine->active.lock, flags); - - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); + rcu_read_unlock(); } } @@ -3163,26 +3153,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3196,20 +3176,22 @@ static void flush_csb(struct intel_engine_cs *engine) { struct intel_engine_execlists *el = &engine->execlists; - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); + if (!tasklet_trylock(&el->tasklet)) { + tasklet_hi_schedule(&el->tasklet); + return; } + + if (!reset_in_progress(el)) + execlists_submission_tasklet((unsigned long)engine); + + tasklet_unlock(&el->tasklet); } static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); + bool submit = false; /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3224,10 +3206,13 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + submit = submit_queue(engine, request); } spin_unlock_irqrestore(&engine->active.lock, flags); + + if (submit) + flush_csb(engine); } static void __execlists_context_fini(struct intel_context *ce) @@ -4113,7 +4098,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4130,10 +4114,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4147,7 +4127,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) * FIXME: Wa for more modern gens needs to be validated */ ring_set_paused(engine, 1); - intel_engine_stop_cs(engine); + __intel_engine_stop_cs(engine); engine->execlists.reset_ccid = active_ccid(engine); } -- 2.20.1 From tvrtko.ursulin at linux.intel.com Fri Jun 12 14:44:51 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 12 Jun 2020 15:44:51 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Move test flush to outside vm->mutex Message-ID: <20200612144451.9081-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> As per our locking rules it is not allowed to wait on requests while holding locks. In this case we were trying to idle the GPU while holding the vm->mutex. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c index 028baae9631f..67f4497c8224 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c @@ -498,8 +498,6 @@ static int igt_evict_contexts(void *arg) mutex_lock(&ggtt->vm.mutex); out_locked: - if (igt_flush_test(i915)) - err = -EIO; while (reserved) { struct reserved *next = reserved->next; @@ -513,6 +511,9 @@ static int igt_evict_contexts(void *arg) mutex_unlock(&ggtt->vm.mutex); intel_runtime_pm_put(&i915->runtime_pm, wakeref); + if (igt_flush_test(i915)) + err = -EIO; + return err; } -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 12 14:55:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 15:55:55 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Move test flush to outside vm->mutex In-Reply-To: <20200612144451.9081-1-tvrtko.ursulin@linux.intel.com> References: <20200612144451.9081-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159197375511.30615.9988513440576782142@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-12 15:44:51) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > As per our locking rules it is not allowed to wait on requests while > holding locks. In this case we were trying to idle the GPU while holding > the vm->mutex. Synchronous eviction would like to have a word. > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c > index 028baae9631f..67f4497c8224 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c > @@ -498,8 +498,6 @@ static int igt_evict_contexts(void *arg) > > mutex_lock(&ggtt->vm.mutex); > out_locked: > - if (igt_flush_test(i915)) > - err = -EIO; > while (reserved) { > struct reserved *next = reserved->next; > > @@ -513,6 +511,9 @@ static int igt_evict_contexts(void *arg) > mutex_unlock(&ggtt->vm.mutex); > intel_runtime_pm_put(&i915->runtime_pm, wakeref); > > + if (igt_flush_test(i915)) > + err = -EIO; The patch is ok, since the manual drm_mm_node reservations are not used by the GTT, but the reason is a bit specious. -Chris From patchwork at emeril.freedesktop.org Fri Jun 12 15:01:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 15:01:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/i915/execlists=3A_Lift_opportun?= =?utf-8?q?istic_process=5Fcsb_to_before_engine_lock?= In-Reply-To: <20200612142551.30956-1-chris@chris-wilson.co.uk> References: <20200612142551.30956-1-chris@chris-wilson.co.uk> Message-ID: <159197411631.21335.16225008769485665348@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/execlists: Lift opportunistic process_csb to before engine lock URL : https://patchwork.freedesktop.org/series/78262/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17939 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17939 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17939, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17939: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at hangcheck: - fi-cml-s: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-cml-s/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-cml-s/igt at i915_selftest@live at hangcheck.html - fi-tgl-u2: NOTRUN -> [INCOMPLETE][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-tgl-u2/igt at i915_selftest@live at hangcheck.html Known issues ------------ Here are the changes found in Patchwork_17939 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][8] ([i915#1993]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92]) -> [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][19] ([i915#62] / [i915#92]) +6 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17939 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17939: 40f4da6c47fe80933138e9f62c37a698cf8a0478 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 40f4da6c47fe drm/i915/execlists: Defer schedule_out until after the next dequeue af00d3a11ae9 drm/i915/execlists: Replace direct submit with direct call to tasklet 2fb91b1dcbe9 drm/i915/execlists: Lift opportunistic process_csb to before engine lock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17939/index.html From tvrtko.ursulin at linux.intel.com Fri Jun 12 15:04:15 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 12 Jun 2020 16:04:15 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Move test flush to outside vm->mutex In-Reply-To: <159197375511.30615.9988513440576782142@build.alporthouse.com> References: <20200612144451.9081-1-tvrtko.ursulin@linux.intel.com> <159197375511.30615.9988513440576782142@build.alporthouse.com> Message-ID: <01688915-2e53-5fc2-54df-b8a1411fcc99@linux.intel.com> On 12/06/2020 15:55, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-12 15:44:51) >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> As per our locking rules it is not allowed to wait on requests while >> holding locks. In this case we were trying to idle the GPU while holding >> the vm->mutex. > > Synchronous eviction would like to have a word. > >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> --- >> drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c >> index 028baae9631f..67f4497c8224 100644 >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c >> @@ -498,8 +498,6 @@ static int igt_evict_contexts(void *arg) >> >> mutex_lock(&ggtt->vm.mutex); >> out_locked: >> - if (igt_flush_test(i915)) >> - err = -EIO; >> while (reserved) { >> struct reserved *next = reserved->next; >> >> @@ -513,6 +511,9 @@ static int igt_evict_contexts(void *arg) >> mutex_unlock(&ggtt->vm.mutex); >> intel_runtime_pm_put(&i915->runtime_pm, wakeref); >> >> + if (igt_flush_test(i915)) >> + err = -EIO; > > The patch is ok, since the manual drm_mm_node reservations are not used > by the GTT, but the reason is a bit specious. We have a comment in i915_request_wait which says: /* * We must never wait on the GPU while holding a lock as we * may need to perform a GPU reset. So while we don't need to * serialise wait/reset with an explicit lock, we do want * lockdep to detect potential dependency cycles. */ And then there was a lockdep splat here https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_6595/fi-skl-6700k2/igt at i915_selftest@live at evict.html, which although uses some extra lockdep annotation patches, seemed to connect the two: <4> [258.014638] Chain exists of: >->reset.mutex --> fs_reclaim --> &vm->mutex <4> [258.014640] Possible unsafe locking scenario: <4> [258.014641] CPU0 CPU1 <4> [258.014641] ---- ---- <4> [258.014642] lock(&vm->mutex); <4> [258.014642] lock(fs_reclaim); <4> [258.014643] lock(&vm->mutex); <4> [258.014644] lock(>->reset.mutex); <4> [258.014645] *** DEADLOCK *** <4> [258.014646] 2 locks held by i915_selftest/5153: Why despite the comment in request wait it does not otherwise see this I don't know. Regards, Tvrtko From chris at chris-wilson.co.uk Fri Jun 12 15:11:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 16:11:55 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Move test flush to outside vm->mutex In-Reply-To: <01688915-2e53-5fc2-54df-b8a1411fcc99@linux.intel.com> References: <20200612144451.9081-1-tvrtko.ursulin@linux.intel.com> <159197375511.30615.9988513440576782142@build.alporthouse.com> <01688915-2e53-5fc2-54df-b8a1411fcc99@linux.intel.com> Message-ID: <159197471578.30615.16927267874017676385@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-12 16:04:15) > > On 12/06/2020 15:55, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-12 15:44:51) > >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> > >> As per our locking rules it is not allowed to wait on requests while > >> holding locks. In this case we were trying to idle the GPU while holding > >> the vm->mutex. > > > > Synchronous eviction would like to have a word. > > > >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> --- > >> drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 5 +++-- > >> 1 file changed, 3 insertions(+), 2 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c > >> index 028baae9631f..67f4497c8224 100644 > >> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c > >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c > >> @@ -498,8 +498,6 @@ static int igt_evict_contexts(void *arg) > >> > >> mutex_lock(&ggtt->vm.mutex); > >> out_locked: > >> - if (igt_flush_test(i915)) > >> - err = -EIO; > >> while (reserved) { > >> struct reserved *next = reserved->next; > >> > >> @@ -513,6 +511,9 @@ static int igt_evict_contexts(void *arg) > >> mutex_unlock(&ggtt->vm.mutex); > >> intel_runtime_pm_put(&i915->runtime_pm, wakeref); > >> > >> + if (igt_flush_test(i915)) > >> + err = -EIO; > > > > The patch is ok, since the manual drm_mm_node reservations are not used > > by the GTT, but the reason is a bit specious. > > We have a comment in i915_request_wait which says: > > /* > * We must never wait on the GPU while holding a lock as we > * may need to perform a GPU reset. So while we don't need to > * serialise wait/reset with an explicit lock, we do want > * lockdep to detect potential dependency cycles. > */ That's for a lock used by reset. > And then there was a lockdep splat here > https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_6595/fi-skl-6700k2/igt at i915_selftest@live at evict.html, > which although uses some extra lockdep annotation patches, seemed to > connect the two: > > <4> [258.014638] Chain exists of: > >->reset.mutex --> fs_reclaim --> &vm->mutex > <4> [258.014640] Possible unsafe locking scenario: > <4> [258.014641] CPU0 CPU1 > <4> [258.014641] ---- ---- > <4> [258.014642] lock(&vm->mutex); > <4> [258.014642] lock(fs_reclaim); > <4> [258.014643] lock(&vm->mutex); > <4> [258.014644] lock(>->reset.mutex); > <4> [258.014645] > *** DEADLOCK *** > <4> [258.014646] 2 locks held by i915_selftest/5153: is false. -Chris From gwan-gyeong.mun at intel.com Fri Jun 12 15:15:07 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Fri, 12 Jun 2020 15:15:07 +0000 Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Add plane damage clips property In-Reply-To: <20200526221447.64110-2-jose.souza@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-2-jose.souza@intel.com> Message-ID: <34d9a217f77904894a06bceb9fc4de6925b9c7ee.camel@intel.com> This feature is supported from GEN9+, but this time it focuses on supporting of PSR2 software tracking for GEN12+. Looks good to me. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > This property will be used by PSR2 software tracking, adding it to > GEN12+. > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index f40b909952cc..b69878334040 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -35,6 +35,7 @@ > #include <drm/drm_atomic.h> > #include <drm/drm_atomic_helper.h> > #include <drm/drm_atomic_uapi.h> > +#include <drm/drm_damage_helper.h> > #include <drm/drm_dp_helper.h> > #include <drm/drm_edid.h> > #include <drm/drm_fourcc.h> > @@ -16476,6 +16477,9 @@ intel_cursor_plane_create(struct > drm_i915_private *dev_priv, > zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; > drm_plane_create_zpos_immutable_property(&cursor->base, zpos); > > + if (INTEL_GEN(dev_priv) >= 12) > + drm_plane_enable_fb_damage_clips(&cursor->base); > + > drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); > > return cursor; > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > b/drivers/gpu/drm/i915/display/intel_sprite.c > index 571c36f929bd..8be06cb25999 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -34,6 +34,7 @@ > #include <drm/drm_atomic_helper.h> > #include <drm/drm_color_mgmt.h> > #include <drm/drm_crtc.h> > +#include <drm/drm_damage_helper.h> > #include <drm/drm_fourcc.h> > #include <drm/drm_plane_helper.h> > #include <drm/drm_rect.h> > @@ -3151,6 +3152,9 @@ skl_universal_plane_create(struct > drm_i915_private *dev_priv, > > drm_plane_create_zpos_immutable_property(&plane->base, > plane_id); > > + if (INTEL_GEN(dev_priv) >= 12) > + drm_plane_enable_fb_damage_clips(&plane->base); > + > drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); > > return plane; From ville.syrjala at linux.intel.com Fri Jun 12 15:25:31 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 18:25:31 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Add plane damage clips property In-Reply-To: <20200526221447.64110-2-jose.souza@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-2-jose.souza@intel.com> Message-ID: <20200612152531.GI6112@intel.com> On Tue, May 26, 2020 at 03:14:43PM -0700, Jos? Roberto de Souza wrote: > This property will be used by PSR2 software tracking, adding it to > GEN12+. Is there actual userspace that uses this? > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index f40b909952cc..b69878334040 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -35,6 +35,7 @@ > #include <drm/drm_atomic.h> > #include <drm/drm_atomic_helper.h> > #include <drm/drm_atomic_uapi.h> > +#include <drm/drm_damage_helper.h> > #include <drm/drm_dp_helper.h> > #include <drm/drm_edid.h> > #include <drm/drm_fourcc.h> > @@ -16476,6 +16477,9 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; > drm_plane_create_zpos_immutable_property(&cursor->base, zpos); > > + if (INTEL_GEN(dev_priv) >= 12) > + drm_plane_enable_fb_damage_clips(&cursor->base); > + > drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); > > return cursor; > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > index 571c36f929bd..8be06cb25999 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -34,6 +34,7 @@ > #include <drm/drm_atomic_helper.h> > #include <drm/drm_color_mgmt.h> > #include <drm/drm_crtc.h> > +#include <drm/drm_damage_helper.h> > #include <drm/drm_fourcc.h> > #include <drm/drm_plane_helper.h> > #include <drm/drm_rect.h> > @@ -3151,6 +3152,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > > drm_plane_create_zpos_immutable_property(&plane->base, plane_id); > > + if (INTEL_GEN(dev_priv) >= 12) > + drm_plane_enable_fb_damage_clips(&plane->base); > + > drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); > > return plane; > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Fri Jun 12 15:28:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 15:28:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Move_test_flush_to_outside_vm-=3Emutex?= In-Reply-To: <20200612144451.9081-1-tvrtko.ursulin@linux.intel.com> References: <20200612144451.9081-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159197573009.21336.6248066961397216768@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Move test flush to outside vm->mutex URL : https://patchwork.freedesktop.org/series/78263/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17940 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17940 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17940, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17940: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-bdw-5557u/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17940 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][6] ([i915#1993]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][10] ([i915#1982]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][17] ([i915#62] / [i915#92]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17940 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17940: 8b6f27bd82d1191bf0bd086a8a96b232da034db2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8b6f27bd82d1 drm/i915/selftests: Move test flush to outside vm->mutex == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17940/index.html From patchwork at emeril.freedesktop.org Fri Jun 12 15:28:59 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 15:28:59 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Flush_gen3_relocs_harder=2C_again_=28rev2=29?= In-Reply-To: <20200611160529.9558-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> Message-ID: <159197573966.21337.5107402557734280300@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Flush gen3 relocs harder, again (rev2) URL : https://patchwork.freedesktop.org/series/78230/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621_full -> Patchwork_17938_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17938_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl4/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl6/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#1930]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-glk6/igt at gem_exec_schedule@smoketest-all.html * igt at i915_module_load@reload: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb1/igt at i915_module_load@reload.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@plain-flip-fb-recreate at c-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1928]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at kms_flip@plain-flip-fb-recreate at c-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl6/igt at kms_flip@plain-flip-fb-recreate at c-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb2/igt at kms_psr@psr2_sprite_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-iclb8/igt at kms_psr@psr2_sprite_render.html * igt at kms_universal_plane@disable-primary-vs-flip-pipe-c: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +9 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl1/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html * igt at kms_vblank@pipe-c-accuracy-idle: - shard-glk: [PASS][27] -> [FAIL][28] ([i915#43]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk9/igt at kms_vblank@pipe-c-accuracy-idle.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-glk6/igt at kms_vblank@pipe-c-accuracy-idle.html * igt at kms_vblank@pipe-c-ts-continuation-idle-hang: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_vblank@pipe-c-ts-continuation-idle-hang.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl8/igt at kms_vblank@pipe-c-ts-continuation-idle-hang.html * igt at perf@blocking-parameterized: - shard-hsw: [PASS][31] -> [FAIL][32] ([i915#1542]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw2/igt at perf@blocking-parameterized.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-hsw6/igt at perf@blocking-parameterized.html * igt at syncobj_wait@single-wait-for-submit-unsubmitted: - shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#95]) +13 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at syncobj_wait@single-wait-for-submit-unsubmitted.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl4/igt at syncobj_wait@single-wait-for-submit-unsubmitted.html #### Possible fixes #### * igt at gem_exec_schedule@implicit-read-write at bcs0: - shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb1/igt at gem_exec_schedule@implicit-read-write at bcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-snb5/igt at gem_exec_schedule@implicit-read-write at bcs0.html * igt at i915_selftest@perf at request: - shard-tglb: [DMESG-FAIL][37] ([i915#1823]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt at i915_selftest@perf at request.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb5/igt at i915_selftest@perf at request.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl8/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge: - shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +7 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl6/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl4/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html * igt at kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +16 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl3/igt at kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-hsw: [DMESG-WARN][45] ([i915#128]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw4/igt at kms_cursor_legacy@pipe-c-torture-bo.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +11 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][49] ([i915#1188]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl8/igt at kms_hdr@bpc-switch-dpms.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-skl5/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb4/igt at kms_psr@psr2_cursor_blt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][55] ([i915#1542]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at perf@blocking-parameterized.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-iclb1/igt at perf@blocking-parameterized.html * igt at perf_pmu@module-unload: - shard-tglb: [DMESG-WARN][57] ([i915#402]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at perf_pmu@module-unload.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-tglb2/igt at perf_pmu@module-unload.html #### Warnings #### * igt at kms_content_protection@atomic: - shard-apl: [DMESG-FAIL][59] ([fdo#110321]) -> [TIMEOUT][60] ([i915#1319] / [i915#1635]) +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_content_protection@atomic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][61] ([i915#1319]) -> [TIMEOUT][62] ([i915#1319] / [i915#1635]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl8/igt at kms_content_protection@legacy.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl2/igt at kms_content_protection@legacy.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][63] ([i915#180] / [i915#95]) -> [DMESG-WARN][64] ([i915#95]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17938 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17938: e754040f87476d5c11086ff3064211105297c0fa @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17938/index.html From jose.souza at intel.com Fri Jun 12 15:30:59 2020 From: jose.souza at intel.com (Souza, Jose) Date: Fri, 12 Jun 2020 15:30:59 +0000 Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Add plane damage clips property In-Reply-To: <20200612152531.GI6112@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-2-jose.souza@intel.com> <20200612152531.GI6112@intel.com> Message-ID: <023ae7594ee3fa1e94d51686b778b55c12e99c96.camel@intel.com> On Fri, 2020-06-12 at 18:25 +0300, Ville Syrj?l? wrote: > On Tue, May 26, 2020 at 03:14:43PM -0700, Jos? Roberto de Souza wrote: > > This property will be used by PSR2 software tracking, adding it to > > GEN12+. > > Is there actual userspace that uses this? Only Weston for now: https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > > drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++++ > > 2 files changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index f40b909952cc..b69878334040 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -35,6 +35,7 @@ > > #include <drm/drm_atomic.h> > > #include <drm/drm_atomic_helper.h> > > #include <drm/drm_atomic_uapi.h> > > +#include <drm/drm_damage_helper.h> > > #include <drm/drm_dp_helper.h> > > #include <drm/drm_edid.h> > > #include <drm/drm_fourcc.h> > > @@ -16476,6 +16477,9 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > > zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; > > drm_plane_create_zpos_immutable_property(&cursor->base, zpos); > > > > + if (INTEL_GEN(dev_priv) >= 12) > > + drm_plane_enable_fb_damage_clips(&cursor->base); > > + > > drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); > > > > return cursor; > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > > index 571c36f929bd..8be06cb25999 100644 > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > @@ -34,6 +34,7 @@ > > #include <drm/drm_atomic_helper.h> > > #include <drm/drm_color_mgmt.h> > > #include <drm/drm_crtc.h> > > +#include <drm/drm_damage_helper.h> > > #include <drm/drm_fourcc.h> > > #include <drm/drm_plane_helper.h> > > #include <drm/drm_rect.h> > > @@ -3151,6 +3152,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > > > > drm_plane_create_zpos_immutable_property(&plane->base, plane_id); > > > > + if (INTEL_GEN(dev_priv) >= 12) > > + drm_plane_enable_fb_damage_clips(&plane->base); > > + > > drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); > > > > return plane; > > -- > > 2.26.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From u.kleine-koenig at pengutronix.de Thu Jun 11 22:12:42 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Fri, 12 Jun 2020 00:12:42 +0200 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-4-hdegoede@redhat.com> <20200608035023.GZ2428291@smile.fi.intel.com> <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> Message-ID: <20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org> On Mon, Jun 08, 2020 at 01:07:12PM +0200, Hans de Goede wrote: > Hi, > > On 6/8/20 5:50 AM, Andy Shevchenko wrote: > > On Sun, Jun 07, 2020 at 08:18:28PM +0200, Hans de Goede wrote: > > > When the user requests a high enough period ns value, then the > > > calculations in pwm_lpss_prepare() might result in a base_unit value of 0. > > > > > > But according to the data-sheet the way the PWM controller works is that > > > each input clock-cycle the base_unit gets added to a N bit counter and > > > that counter overflowing determines the PWM output frequency. Adding 0 > > > to the counter is a no-op. The data-sheet even explicitly states that > > > writing 0 to the base_unit bits will result in the PWM outputting a > > > continuous 0 signal. > > > > So, and why it's a problem? > > Lets sya the user requests a PWM output frequency of 100Hz on Cherry Trail > which has a 19200000 Hz clock this will result in 100 * 65536 / 19200000 = > 0.3 -> 0 as base-unit value. So instead of getting 100 Hz the user will > now get a pin which is always outputting low. I didn't follow the complete discussion but note that the general rule is: round period down to the next possible implementable period round duty_cycle down to the next possible implementable duty_cycle so if a small enough period (and so a small duty_cycle) is requested it is expected that duty_cycle will be zero. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200612/9b3037bc/attachment.sig> From u.kleine-koenig at pengutronix.de Thu Jun 11 21:21:44 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Thu, 11 Jun 2020 23:21:44 +0200 Subject: [Intel-gfx] pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API In-Reply-To: <20200608143500.GX20149@phenom.ffwll.local> References: <20200606202601.48410-1-hdegoede@redhat.com> <20200608143500.GX20149@phenom.ffwll.local> Message-ID: <20200611212144.i7ma7kriznidds4r@taurus.defre.kleine-koenig.org> Hello, On Mon, Jun 08, 2020 at 04:35:00PM +0200, Daniel Vetter wrote: > On Sat, Jun 06, 2020 at 10:25:45PM +0200, Hans de Goede wrote: > > Hi All, > > > > This patch series converts the i915 driver's cpde for controlling the > > panel's backlight with an external PWM controller to use the atomic PWM API. > > > > Initially the plan was for this series to consist of 2 parts: > > 1. convert the pwm-crc driver to support the atomic PWM API and > > 2. convert the i915 driver's PWM code to use the atomic PWM API. > > > > But during testing I've found a number of bugs in the pwm-lpss and I > > found that the acpi_lpss code needs some special handling because of > > some ugliness found in most Cherry Trail DSDTs. > > > > So now this series has grown somewhat large and consists of 4 parts: > > > > 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness > > 2. various fixes to the pwm-lpss driver > > 3. convert the pwm-crc driver to support the atomic PWM API and > > 4. convert the i915 driver's PWM code to use the atomic PWM API > > > > So we need to discuss how to merge this (once it passes review). > > Although the inter-dependencies are only runtime I still think we should > > make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before > > merging the i915 changes. Both to make sure that the intel-gfx CI system > > does not become unhappy and for bisecting reasons. > > Simplest is if acpi acks the acpi patches for merging through > drm-intel.git. Second simplest is topic branch (drm-intel maintainers can > do that) with the entire pile, which then acpi and drm-intel can both pull > in. > > Up to the two maintainer teams to figure this one out. I'm unclear about the dependencies, but the changes to drivers/pwm need an ack (or processing) by the PWM team. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200611/79ed84d5/attachment.sig> From u.kleine-koenig at pengutronix.de Thu Jun 11 21:37:44 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Thu, 11 Jun 2020 23:37:44 +0200 Subject: [Intel-gfx] [PATCH v2 11/15] pwm: crc: Implement get_state() method In-Reply-To: <20200607181840.13536-12-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-12-hdegoede@redhat.com> Message-ID: <20200611213744.6gg2oy45cende6ba@taurus.defre.kleine-koenig.org> Hello, On Sun, Jun 07, 2020 at 08:18:36PM +0200, Hans de Goede wrote: > Implement the pwm_ops.get_state() method to complete the support for the > new atomic PWM API. > > Signed-off-by: Hans de Goede <hdegoede at redhat.com> > --- > drivers/pwm/pwm-crc.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c > index 58c7e9ef7278..6c75a3470bc8 100644 > --- a/drivers/pwm/pwm-crc.c > +++ b/drivers/pwm/pwm-crc.c > @@ -114,8 +114,37 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > return 0; > } > > +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, > + struct pwm_state *state) > +{ > + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); > + struct device *dev = crc_pwm->chip.dev; > + unsigned int clk_div, clk_div_reg, duty_cycle_reg; > + int error; > + > + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); > + if (error) { > + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); > + return; > + } > + > + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); > + if (error) { > + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); > + return; > + } I assume that duty_cycle_reg cannot be bigger than 0xff? Would it make sense to mask the value accordingly to get more robust code? > + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; > + > + state->period = clk_div * NSEC_PER_MHZ * 256 / PWM_BASE_CLK_MHZ; > + state->duty_cycle = duty_cycle_reg * state->period / PWM_MAX_LEVEL; > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); These aligned = look strange (IMHO). If you don't feel strong here I'd like to see a single space before a =. Unrelated to your series I think we should change .get_state() to return an error indication. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200611/d81fb51b/attachment.sig> From u.kleine-koenig at pengutronix.de Thu Jun 11 22:20:29 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Fri, 12 Jun 2020 00:20:29 +0200 Subject: [Intel-gfx] [PATCH v2 09/15] pwm: crc: Enable/disable PWM output on enable/disable In-Reply-To: <20200607181840.13536-10-hdegoede@redhat.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-10-hdegoede@redhat.com> Message-ID: <20200611222029.csyo2wxof7nuhjws@taurus.defre.kleine-koenig.org> On Sun, Jun 07, 2020 at 08:18:34PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, > this commit makes crc_pwm_disable() clear it on disable and makes > crc_pwm_enable() set it again on re-enable. > > This should disable the internal (divided) PWM clock and tri-state the > PWM output pin when disabled, saving some power. It would be great if you could also document that disabling the PWM makes the output tri-state. There are a few drivers that have a "Limitations" section at their top. Describing that there (in the same format) would be the right place. Also note that according to Thierry's conception getting a (driven) inactive output is the right thing for a disabled PWM. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200612/cd3df699/attachment.sig> From ville.syrjala at linux.intel.com Fri Jun 12 15:37:56 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 18:37:56 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Add plane damage clips property In-Reply-To: <023ae7594ee3fa1e94d51686b778b55c12e99c96.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-2-jose.souza@intel.com> <20200612152531.GI6112@intel.com> <023ae7594ee3fa1e94d51686b778b55c12e99c96.camel@intel.com> Message-ID: <20200612153756.GJ6112@intel.com> On Fri, Jun 12, 2020 at 03:30:59PM +0000, Souza, Jose wrote: > On Fri, 2020-06-12 at 18:25 +0300, Ville Syrj?l? wrote: > > On Tue, May 26, 2020 at 03:14:43PM -0700, Jos? Roberto de Souza wrote: > > > This property will be used by PSR2 software tracking, adding it to > > > GEN12+. > > > > Is there actual userspace that uses this? > > Only Weston for now: > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 And what happens when userspace doesn't do this stuff? > > > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > > > drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++++ > > > 2 files changed, 8 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index f40b909952cc..b69878334040 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -35,6 +35,7 @@ > > > #include <drm/drm_atomic.h> > > > #include <drm/drm_atomic_helper.h> > > > #include <drm/drm_atomic_uapi.h> > > > +#include <drm/drm_damage_helper.h> > > > #include <drm/drm_dp_helper.h> > > > #include <drm/drm_edid.h> > > > #include <drm/drm_fourcc.h> > > > @@ -16476,6 +16477,9 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > > > zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; > > > drm_plane_create_zpos_immutable_property(&cursor->base, zpos); > > > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > + drm_plane_enable_fb_damage_clips(&cursor->base); > > > + > > > drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); > > > > > > return cursor; > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > > > index 571c36f929bd..8be06cb25999 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > > @@ -34,6 +34,7 @@ > > > #include <drm/drm_atomic_helper.h> > > > #include <drm/drm_color_mgmt.h> > > > #include <drm/drm_crtc.h> > > > +#include <drm/drm_damage_helper.h> > > > #include <drm/drm_fourcc.h> > > > #include <drm/drm_plane_helper.h> > > > #include <drm/drm_rect.h> > > > @@ -3151,6 +3152,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > > > > > > drm_plane_create_zpos_immutable_property(&plane->base, plane_id); > > > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > + drm_plane_enable_fb_damage_clips(&plane->base); > > > + > > > drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); > > > > > > return plane; > > > -- > > > 2.26.2 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From jose.souza at intel.com Fri Jun 12 15:42:38 2020 From: jose.souza at intel.com (Souza, Jose) Date: Fri, 12 Jun 2020 15:42:38 +0000 Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Add plane damage clips property In-Reply-To: <20200612153756.GJ6112@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-2-jose.souza@intel.com> <20200612152531.GI6112@intel.com> <023ae7594ee3fa1e94d51686b778b55c12e99c96.camel@intel.com> <20200612153756.GJ6112@intel.com> Message-ID: <9f850ea63769be659d984cbd934f5eecef4cf37a.camel@intel.com> On Fri, 2020-06-12 at 18:37 +0300, Ville Syrj?l? wrote: > On Fri, Jun 12, 2020 at 03:30:59PM +0000, Souza, Jose wrote: > > On Fri, 2020-06-12 at 18:25 +0300, Ville Syrj?l? wrote: > > > On Tue, May 26, 2020 at 03:14:43PM -0700, Jos? Roberto de Souza wrote: > > > > This property will be used by PSR2 software tracking, adding it to > > > > GEN12+. > > > > > > Is there actual userspace that uses this? > > > > Only Weston for now: > > > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > And what happens when userspace doesn't do this stuff? It updates the whole area of the plane that flipped. > > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > > > > drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++++ > > > > 2 files changed, 8 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > > index f40b909952cc..b69878334040 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > @@ -35,6 +35,7 @@ > > > > #include <drm/drm_atomic.h> > > > > #include <drm/drm_atomic_helper.h> > > > > #include <drm/drm_atomic_uapi.h> > > > > +#include <drm/drm_damage_helper.h> > > > > #include <drm/drm_dp_helper.h> > > > > #include <drm/drm_edid.h> > > > > #include <drm/drm_fourcc.h> > > > > @@ -16476,6 +16477,9 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > > > > zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; > > > > drm_plane_create_zpos_immutable_property(&cursor->base, zpos); > > > > > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > > + drm_plane_enable_fb_damage_clips(&cursor->base); > > > > + > > > > drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); > > > > > > > > return cursor; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > > > > index 571c36f929bd..8be06cb25999 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > > > @@ -34,6 +34,7 @@ > > > > #include <drm/drm_atomic_helper.h> > > > > #include <drm/drm_color_mgmt.h> > > > > #include <drm/drm_crtc.h> > > > > +#include <drm/drm_damage_helper.h> > > > > #include <drm/drm_fourcc.h> > > > > #include <drm/drm_plane_helper.h> > > > > #include <drm/drm_rect.h> > > > > @@ -3151,6 +3152,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > > > > > > > > drm_plane_create_zpos_immutable_property(&plane->base, plane_id); > > > > > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > > + drm_plane_enable_fb_damage_clips(&plane->base); > > > > + > > > > drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); > > > > > > > > return plane; > > > > -- > > > > 2.26.2 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx at lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From gwan-gyeong.mun at intel.com Fri Jun 12 15:42:38 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Fri, 12 Jun 2020 15:42:38 +0000 Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Reorder intel_psr2_config_valid() In-Reply-To: <20200526221447.64110-3-jose.souza@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-3-jose.souza@intel.com> Message-ID: <7ab9eb3561ed00717a9cd3232c3b581dfa636c23.camel@intel.com> Looks good to me. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > Future patches will bring PSR2 selective fetch configuration > validation but most of the configuration checks will be used for HW > tracking and selective fetch so the reoder was necessary. > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 50 ++++++++++++-------- > ---- > 1 file changed, 25 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 714c590b39f5..0c86e9e341a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -646,21 +646,6 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > return false; > } > > - /* > - * Some platforms lack PSR2 HW tracking and instead require > manual > - * tracking by software. In this case, the driver is required > to track > - * the areas that need updates and program hardware to send > selective > - * updates. > - * > - * So until the software tracking is implemented, PSR2 needs to > be > - * disabled for platforms without PSR2 HW tracking. > - */ > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > - drm_dbg_kms(&dev_priv->drm, > - "No PSR2 HW tracking in the platform\n"); > - return false; > - } > - > /* > * DSC and PSR2 cannot be enabled simultaneously. If a > requested > * resolution requires DSC to be enabled, priority is given to > DSC > @@ -672,6 +657,12 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > return false; > } > > + if (crtc_state->crc_enabled) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 not enabled because it would inhibit > pipe CRC calculation\n"); > + return false; > + } > + > if (INTEL_GEN(dev_priv) >= 12) { > psr_max_h = 5120; > psr_max_v = 3200; > @@ -686,14 +677,6 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > max_bpp = 24; > } > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > - drm_dbg_kms(&dev_priv->drm, > - "PSR2 not enabled, resolution %dx%d > max > supported %dx%d\n", > - crtc_hdisplay, crtc_vdisplay, > - psr_max_h, psr_max_v); > - return false; > - } > - > if (crtc_state->pipe_bpp > max_bpp) { > drm_dbg_kms(&dev_priv->drm, > "PSR2 not enabled, pipe bpp %d > max > supported %d\n", > @@ -714,9 +697,26 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > return false; > } > > - if (crtc_state->crc_enabled) { > + /* > + * Some platforms lack PSR2 HW tracking and instead require > manual > + * tracking by software. In this case, the driver is required > to track > + * the areas that need updates and program hardware to send > selective > + * updates. > + * > + * So until the software tracking is implemented, PSR2 needs to > be > + * disabled for platforms without PSR2 HW tracking. > + */ > + if (!HAS_PSR_HW_TRACKING(dev_priv)) { > drm_dbg_kms(&dev_priv->drm, > - "PSR2 not enabled because it would inhibit > pipe CRC calculation\n"); > + "No PSR2 HW tracking in the platform\n"); > + return false; > + } > + > + if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 not enabled, resolution %dx%d > max > supported %dx%d\n", > + crtc_hdisplay, crtc_vdisplay, > + psr_max_h, psr_max_v); > return false; > } > From daniel.vetter at ffwll.ch Fri Jun 12 16:00:49 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:49 +0200 Subject: [Intel-gfx] [PATCH 1/8] drm/atomic-helper: reset vblank on crtc reset Message-ID: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Only when vblanks are supported ofc. Some drivers do this already, but most unfortunately missed it. This opens up bugs after driver load, before the crtc is enabled for the first time. syzbot spotted this when loading vkms as a secondary output. Given how many drivers are buggy it's best to solve this once and for all in shared helper code. Aside from moving the few existing calls to drm_crtc_vblank_reset into helpers (i915 doesn't use helpers, so keeps its own) I think the regression risk is minimal: atomic helpers already rely on drivers calling drm_crtc_vblank_on/off correctly in their hooks when they support vblanks. And driver that's failing to handle vblanks after this is missing those calls already, and vblanks could only work by accident when enabling a CRTC for the first time right after boot. Big thanks to Tetsuo for helping track down what's going wrong here. There's only a few drivers which already had the necessary call and needed some updating: - komeda, atmel and tidss also needed to be changed to call __drm_atomic_helper_crtc_reset() intead of open coding it - tegra and msm even had it in the same place already, just code motion, and malidp already uses __drm_atomic_helper_crtc_reset(). Only call left is in i915, which doesn't use drm_mode_config_reset, but has its own fastboot infrastructure. So that's the only case where we actually want this in the driver still. I've also reviewed all other drivers which set up vblank support with drm_vblank_init. After the previous patch fixing mxsfb all atomic drivers do call drm_crtc_vblank_on/off as they should, the remaining drivers are either legacy kms or legacy dri1 drivers, so not affected by this change to atomic helpers. v2: Use the drm_dev_has_vblank() helper. v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off instead of drm_crtc_vblank_reset. Adjust them too. v4: Laurent noticed that rcar-du and omap open-code their crtc reset and hence would actually be broken by this patch now. So fix them up by reusing the helpers, which brings the drm_crtc_vblank_reset() back. Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com> Reviewed-by: Boris Brezillon <boris.brezillon at collabora.com> Acked-by: Liviu Dudau <liviu.dudau at arm.com> Acked-by: Thierry Reding <treding at nvidia.com> Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb Reported-by: Tetsuo Handa <penguin-kernel at I-love.SAKURA.ne.jp> Reported-by: syzbot+0871b14ca2e2fb64f6e3 at syzkaller.appspotmail.com Cc: Tetsuo Handa <penguin-kernel at I-love.SAKURA.ne.jp> Cc: "James (Qian) Wang" <james.qian.wang at arm.com> Cc: Liviu Dudau <liviu.dudau at arm.com> Cc: Mihail Atanassov <mihail.atanassov at arm.com> Cc: Brian Starkey <brian.starkey at arm.com> Cc: Sam Ravnborg <sam at ravnborg.org> Cc: Boris Brezillon <bbrezillon at kernel.org> Cc: Nicolas Ferre <nicolas.ferre at microchip.com> Cc: Alexandre Belloni <alexandre.belloni at bootlin.com> Cc: Ludovic Desroches <ludovic.desroches at microchip.com> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Maxime Ripard <mripard at kernel.org> Cc: Thomas Zimmermann <tzimmermann at suse.de> Cc: David Airlie <airlied at linux.ie> Cc: Daniel Vetter <daniel at ffwll.ch> Cc: Thierry Reding <thierry.reding at gmail.com> Cc: Jonathan Hunter <jonathanh at nvidia.com> Cc: Jyri Sarha <jsarha at ti.com> Cc: Tomi Valkeinen <tomi.valkeinen at ti.com> Cc: Rob Clark <robdclark at gmail.com> Cc: Sean Paul <seanpaul at chromium.org> Cc: Brian Masney <masneyb at onstation.org> Cc: Emil Velikov <emil.velikov at collabora.com> Cc: zhengbin <zhengbin13 at huawei.com> Cc: Thomas Gleixner <tglx at linutronix.de> Cc: linux-tegra at vger.kernel.org Cc: Kieran Bingham <kieran.bingham+renesas at ideasonboard.com> Cc: linux-arm-kernel at lists.infradead.org Cc: linux-renesas-soc at vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 7 ++----- drivers/gpu/drm/arm/malidp_drv.c | 1 - drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 ++----- drivers/gpu/drm/drm_atomic_state_helper.c | 4 ++++ drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 -- drivers/gpu/drm/omapdrm/omap_crtc.c | 8 +++++--- drivers/gpu/drm/omapdrm/omap_drv.c | 4 ---- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 6 +----- drivers/gpu/drm/tegra/dc.c | 1 - drivers/gpu/drm/tidss/tidss_crtc.c | 3 +-- drivers/gpu/drm/tidss/tidss_kms.c | 4 ---- 11 files changed, 15 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c index 56bd938961ee..f33418d6e1a0 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c @@ -492,10 +492,8 @@ static void komeda_crtc_reset(struct drm_crtc *crtc) crtc->state = NULL; state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state) { - crtc->state = &state->base; - crtc->state->crtc = crtc; - } + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state * @@ -616,7 +614,6 @@ static int komeda_crtc_add(struct komeda_kms_dev *kms, return err; drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs); - drm_crtc_vblank_reset(crtc); crtc->port = kcrtc->master->of_output_port; diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c index 6feda7cb37a6..c9e1ee84b4e8 100644 --- a/drivers/gpu/drm/arm/malidp_drv.c +++ b/drivers/gpu/drm/arm/malidp_drv.c @@ -861,7 +861,6 @@ static int malidp_bind(struct device *dev) drm->irq_enabled = true; ret = drm_vblank_init(drm, drm->mode_config.num_crtc); - drm_crtc_vblank_reset(&malidp->crtc); if (ret < 0) { DRM_ERROR("failed to initialise vblank\n"); goto vblank_fail; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 10985134ce0b..ce246b96330b 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -411,10 +411,8 @@ static void atmel_hlcdc_crtc_reset(struct drm_crtc *crtc) } state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state) { - crtc->state = &state->base; - crtc->state->crtc = crtc; - } + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state * @@ -528,7 +526,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) } drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); - drm_crtc_vblank_reset(&crtc->base); drm_mode_crtc_set_gamma_size(&crtc->base, ATMEL_HLCDC_CLUT_SIZE); drm_crtc_enable_color_mgmt(&crtc->base, 0, false, diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 8fce6a115dfe..9ad74045158e 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -32,6 +32,7 @@ #include <drm/drm_device.h> #include <drm/drm_plane.h> #include <drm/drm_print.h> +#include <drm/drm_vblank.h> #include <drm/drm_writeback.h> #include <linux/slab.h> @@ -93,6 +94,9 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, if (crtc_state) __drm_atomic_helper_crtc_state_reset(crtc_state, crtc); + if (drm_dev_has_vblank(crtc->dev)) + drm_crtc_vblank_reset(crtc); + crtc->state = crtc_state; } EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c index e152016a6a7d..c39dad151bb6 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c @@ -1117,8 +1117,6 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc) mdp5_crtc_destroy_state(crtc, crtc->state); __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); - - drm_crtc_vblank_reset(crtc); } static const struct drm_crtc_funcs mdp5_crtc_funcs = { diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index fce7e944a280..6d40914675da 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -697,14 +697,16 @@ static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, static void omap_crtc_reset(struct drm_crtc *crtc) { + struct omap_crtc_state *state; + if (crtc->state) __drm_atomic_helper_crtc_destroy_state(crtc->state); kfree(crtc->state); - crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL); - if (crtc->state) - crtc->state->crtc = crtc; + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state * diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index 242d28281784..4526967978b7 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -595,7 +595,6 @@ static int omapdrm_init(struct omap_drm_private *priv, struct device *dev) { const struct soc_device_attribute *soc; struct drm_device *ddev; - unsigned int i; int ret; DBG("%s", dev_name(dev)); @@ -642,9 +641,6 @@ static int omapdrm_init(struct omap_drm_private *priv, struct device *dev) goto err_cleanup_modeset; } - for (i = 0; i < priv->num_pipes; i++) - drm_crtc_vblank_off(priv->pipes[i].crtc); - omap_fbdev_init(ddev); drm_kms_helper_poll_init(ddev); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index d73e88ddecd0..fe86a3e67757 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -975,8 +975,7 @@ static void rcar_du_crtc_reset(struct drm_crtc *crtc) state->crc.source = VSP1_DU_CRC_NONE; state->crc.index = 0; - crtc->state = &state->state; - crtc->state->crtc = crtc; + __drm_atomic_helper_crtc_reset(crtc, &state->state); } static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc) @@ -1271,9 +1270,6 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex, drm_crtc_helper_add(crtc, &crtc_helper_funcs); - /* Start with vertical blanking interrupt reporting disabled. */ - drm_crtc_vblank_off(crtc); - /* Register the interrupt handler. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { /* The IRQ's are associated with the CRTC (sw)index. */ diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 83f31c6e891c..9b308b572eac 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1168,7 +1168,6 @@ static void tegra_crtc_reset(struct drm_crtc *crtc) tegra_crtc_atomic_destroy_state(crtc, crtc->state); __drm_atomic_helper_crtc_reset(crtc, &state->base); - drm_crtc_vblank_reset(crtc); } static struct drm_crtc_state * diff --git a/drivers/gpu/drm/tidss/tidss_crtc.c b/drivers/gpu/drm/tidss/tidss_crtc.c index 89a226912de8..4d01c4af61cd 100644 --- a/drivers/gpu/drm/tidss/tidss_crtc.c +++ b/drivers/gpu/drm/tidss/tidss_crtc.c @@ -352,8 +352,7 @@ static void tidss_crtc_reset(struct drm_crtc *crtc) return; } - crtc->state = &tcrtc->base; - crtc->state->crtc = crtc; + __drm_atomic_helper_crtc_reset(crtc, &tcrtc->base); } static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/tidss/tidss_kms.c b/drivers/gpu/drm/tidss/tidss_kms.c index 4b99e9fa84a5..e6ab59eed259 100644 --- a/drivers/gpu/drm/tidss/tidss_kms.c +++ b/drivers/gpu/drm/tidss/tidss_kms.c @@ -278,10 +278,6 @@ int tidss_modeset_init(struct tidss_device *tidss) if (ret) return ret; - /* Start with vertical blanking interrupt reporting disabled. */ - for (i = 0; i < tidss->num_crtcs; ++i) - drm_crtc_vblank_reset(tidss->crtcs[i]); - drm_mode_config_reset(ddev); dev_dbg(tidss->dev, "%s done\n", __func__); -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 16:00:50 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:50 +0200 Subject: [Intel-gfx] [PATCH 2/8] drm/amdgpu: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200612160056.2082681-2-daniel.vetter@ffwll.ch> Now also comes with the added benefit of doing a drm_crtc_vblank_off(), which means vblank state isn't ill-defined and fail-y at driver load before the first modeset on each crtc. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: Alex Deucher <alexander.deucher at amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> Cc: Harry Wentland <harry.wentland at amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com> Cc: Roman Li <roman.li at amd.com> Cc: Mikita Lipski <mikita.lipski at amd.com> Cc: Stylon Wang <stylon.wang at amd.com> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 68a73065b516..36d605a6eb16 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4594,9 +4594,7 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc) if (WARN_ON(!state)) return; - crtc->state = &state->base; - crtc->state->crtc = crtc; - + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state * -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 16:00:51 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:51 +0200 Subject: [Intel-gfx] [PATCH 3/8] drm/imx: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200612160056.2082681-3-daniel.vetter@ffwll.ch> Now also comes with the added benefit of doing a drm_crtc_vblank_off(), which means vblank state isn't ill-defined and fail-y at driver load before the first modeset on each crtc. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: Philipp Zabel <p.zabel at pengutronix.de> Cc: Shawn Guo <shawnguo at kernel.org> Cc: Sascha Hauer <s.hauer at pengutronix.de> Cc: Pengutronix Kernel Team <kernel at pengutronix.de> Cc: Fabio Estevam <festevam at gmail.com> Cc: NXP Linux Team <linux-imx at nxp.com> Cc: linux-arm-kernel at lists.infradead.org --- drivers/gpu/drm/imx/ipuv3-crtc.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index 63c0284f8b3c..02c2f848f2d1 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -109,20 +109,15 @@ static void imx_drm_crtc_reset(struct drm_crtc *crtc) { struct imx_crtc_state *state; - if (crtc->state) { - if (crtc->state->mode_blob) - drm_property_blob_put(crtc->state->mode_blob); - - state = to_imx_crtc_state(crtc->state); - memset(state, 0, sizeof(*state)); - } else { - state = kzalloc(sizeof(*state), GFP_KERNEL); - if (!state) - return; - crtc->state = &state->base; - } + if (crtc->state) + __drm_atomic_helper_crtc_destroy_state(crtc->state); - state->base.crtc = crtc; + kfree(to_imx_crtc_state(crtc->state)); + crtc->state = NULL; + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc) -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 16:00:52 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:52 +0200 Subject: [Intel-gfx] [PATCH 4/8] drm/mtk: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200612160056.2082681-4-daniel.vetter@ffwll.ch> Now also comes with the added benefit of doing a drm_crtc_vblank_off(), which means vblank state isn't ill-defined and fail-y at driver load before the first modeset on each crtc. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: Chun-Kuang Hu <chunkuang.hu at kernel.org> Cc: Philipp Zabel <p.zabel at pengutronix.de> Cc: Matthias Brugger <matthias.bgg at gmail.com> Cc: linux-arm-kernel at lists.infradead.org Cc: linux-mediatek at lists.infradead.org --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index a7dba4ced902..d654c7d514bd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -112,19 +112,15 @@ static void mtk_drm_crtc_reset(struct drm_crtc *crtc) { struct mtk_crtc_state *state; - if (crtc->state) { + if (crtc->state) __drm_atomic_helper_crtc_destroy_state(crtc->state); - state = to_mtk_crtc_state(crtc->state); - memset(state, 0, sizeof(*state)); - } else { - state = kzalloc(sizeof(*state), GFP_KERNEL); - if (!state) - return; - crtc->state = &state->base; - } + kfree(to_mtk_crtc_state(crtc->state)); + crtc->state = NULL; - state->base.crtc = crtc; + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state) + __drm_atomic_helper_crtc_reset(crtc, &state->base); } static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 16:00:53 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:53 +0200 Subject: [Intel-gfx] [PATCH 5/8] drm/vc4: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200612160056.2082681-5-daniel.vetter@ffwll.ch> Now also comes with the added benefit of doing a drm_crtc_vblank_off(), which means vblank state isn't ill-defined and fail-y at driver load before the first modeset on each crtc. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: Eric Anholt <eric at anholt.net> --- drivers/gpu/drm/vc4/vc4_crtc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 29131409a4de..5371e63cf6e2 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -993,10 +993,9 @@ vc4_crtc_reset(struct drm_crtc *crtc) { if (crtc->state) vc4_crtc_destroy_state(crtc, crtc->state); - crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL); if (crtc->state) - crtc->state->crtc = crtc; + __drm_atomic_helper_crtc_reset(crtc, crtc->state); } static const struct drm_crtc_funcs vc4_crtc_funcs = { -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 16:00:55 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:55 +0200 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200612160056.2082681-7-daniel.vetter@ffwll.ch> The atomic helpers try really hard to not lose track of things, duplicating enabled tracking in the driver is at best confusing. Double-enabling or disabling is a bug in atomic helpers. In the fb_dirty function we can just assume that the fb always exists, simple display pipe helpers guarantee that the crtc is only enabled together with the output, so we always have a primary plane around. Now in the update function we need to be a notch more careful, since that can also get called when the crtc is off. And we don't want to upload frames when that's the case, so filter that out too. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Maxime Ripard <mripard at kernel.org> Cc: Thomas Zimmermann <tzimmermann at suse.de> Cc: David Airlie <airlied at linux.ie> Cc: Daniel Vetter <daniel at ffwll.ch> Cc: David Lechner <david at lechnology.com> --- drivers/gpu/drm/drm_mipi_dbi.c | 16 ++++++---------- drivers/gpu/drm/tiny/ili9225.c | 12 +++--------- drivers/gpu/drm/tiny/st7586.c | 11 +++-------- include/drm/drm_mipi_dbi.h | 5 ----- 4 files changed, 12 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c index fd8d672972a9..79532b9a324a 100644 --- a/drivers/gpu/drm/drm_mipi_dbi.c +++ b/drivers/gpu/drm/drm_mipi_dbi.c @@ -268,7 +268,7 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) bool full; void *tr; - if (!dbidev->enabled) + if (WARN_ON(!fb)) return; if (!drm_dev_enter(fb->dev, &idx)) @@ -314,6 +314,9 @@ void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *state = pipe->plane.state; struct drm_rect rect; + if (!pipe->crtc.state->active) + return; + if (drm_atomic_helper_damage_merged(old_state, state, &rect)) mipi_dbi_fb_dirty(state->fb, &rect); } @@ -325,9 +328,8 @@ EXPORT_SYMBOL(mipi_dbi_pipe_update); * @crtc_state: CRTC state * @plane_state: Plane state * - * This function sets &mipi_dbi->enabled, flushes the whole framebuffer and - * enables the backlight. Drivers can use this in their - * &drm_simple_display_pipe_funcs->enable callback. + * Flushes the whole framebuffer and enables the backlight. Drivers can use this + * in their &drm_simple_display_pipe_funcs->enable callback. * * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom * framebuffer flushing, can't use this function since they both use the same @@ -349,7 +351,6 @@ void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev, if (!drm_dev_enter(&dbidev->drm, &idx)) return; - dbidev->enabled = true; mipi_dbi_fb_dirty(fb, &rect); backlight_enable(dbidev->backlight); @@ -390,13 +391,8 @@ void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe) { struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev); - if (!dbidev->enabled) - return; - DRM_DEBUG_KMS("\n"); - dbidev->enabled = false; - if (dbidev->backlight) backlight_disable(dbidev->backlight); else diff --git a/drivers/gpu/drm/tiny/ili9225.c b/drivers/gpu/drm/tiny/ili9225.c index 16400064320f..97a77262d791 100644 --- a/drivers/gpu/drm/tiny/ili9225.c +++ b/drivers/gpu/drm/tiny/ili9225.c @@ -89,9 +89,6 @@ static void ili9225_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) bool full; void *tr; - if (!dbidev->enabled) - return; - if (!drm_dev_enter(fb->dev, &idx)) return; @@ -167,6 +164,9 @@ static void ili9225_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *state = pipe->plane.state; struct drm_rect rect; + if (!pipe->crtc.state->active) + return; + if (drm_atomic_helper_damage_merged(old_state, state, &rect)) ili9225_fb_dirty(state->fb, &rect); } @@ -275,7 +275,6 @@ static void ili9225_pipe_enable(struct drm_simple_display_pipe *pipe, ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x1017); - dbidev->enabled = true; ili9225_fb_dirty(fb, &rect); out_exit: drm_dev_exit(idx); @@ -295,16 +294,11 @@ static void ili9225_pipe_disable(struct drm_simple_display_pipe *pipe) * unplug. */ - if (!dbidev->enabled) - return; - ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x0000); msleep(50); ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x0007); msleep(50); ili9225_command(dbi, ILI9225_POWER_CONTROL_1, 0x0a02); - - dbidev->enabled = false; } static int ili9225_dbi_command(struct mipi_dbi *dbi, u8 *cmd, u8 *par, diff --git a/drivers/gpu/drm/tiny/st7586.c b/drivers/gpu/drm/tiny/st7586.c index 1311e5df8721..d05de03891f8 100644 --- a/drivers/gpu/drm/tiny/st7586.c +++ b/drivers/gpu/drm/tiny/st7586.c @@ -118,9 +118,6 @@ static void st7586_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) struct mipi_dbi *dbi = &dbidev->dbi; int start, end, idx, ret = 0; - if (!dbidev->enabled) - return; - if (!drm_dev_enter(fb->dev, &idx)) return; @@ -161,6 +158,9 @@ static void st7586_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *state = pipe->plane.state; struct drm_rect rect; + if (!pipe->crtc.state->active) + return; + if (drm_atomic_helper_damage_merged(old_state, state, &rect)) st7586_fb_dirty(state->fb, &rect); } @@ -237,7 +237,6 @@ static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe, msleep(100); - dbidev->enabled = true; st7586_fb_dirty(fb, &rect); mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON); @@ -258,11 +257,7 @@ static void st7586_pipe_disable(struct drm_simple_display_pipe *pipe) DRM_DEBUG_KMS("\n"); - if (!dbidev->enabled) - return; - mipi_dbi_command(&dbidev->dbi, MIPI_DCS_SET_DISPLAY_OFF); - dbidev->enabled = false; } static const u32 st7586_formats[] = { diff --git a/include/drm/drm_mipi_dbi.h b/include/drm/drm_mipi_dbi.h index 4d0e49c0ed2c..c2827ceaba0d 100644 --- a/include/drm/drm_mipi_dbi.h +++ b/include/drm/drm_mipi_dbi.h @@ -94,11 +94,6 @@ struct mipi_dbi_dev { */ struct drm_display_mode mode; - /** - * @enabled: Pipeline is enabled - */ - bool enabled; - /** * @tx_buf: Buffer used for transfer (copy clip rect area) */ -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 16:00:54 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:54 +0200 Subject: [Intel-gfx] [PATCH 6/8] drm/vmwgfx: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200612160056.2082681-6-daniel.vetter@ffwll.ch> Now also comes with the added benefit of doing a drm_crtc_vblank_off(), which means vblank state isn't ill-defined and fail-y at driver load before the first modeset on each crtc. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: VMware Graphics <linux-graphics-maintainer at vmware.com> Cc: Roland Scheidegger <sroland at vmware.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 3c97654b5a43..e91dfc65a93f 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -629,8 +629,7 @@ void vmw_du_crtc_reset(struct drm_crtc *crtc) return; } - crtc->state = &vcs->base; - crtc->state->crtc = crtc; + __drm_atomic_helper_crtc_reset(crtc, &state->base); } -- 2.26.2 From daniel.vetter at ffwll.ch Fri Jun 12 16:00:56 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 18:00:56 +0200 Subject: [Intel-gfx] [PATCH 8/8] drm/tiny/repaper: Drop edp->enabled In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200612160056.2082681-8-daniel.vetter@ffwll.ch> Same patch as the mipi-dbi one, atomic tracks this for us already, we just have to check the right thing. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: "Noralf Tr?nnes" <noralf at tronnes.org> --- drivers/gpu/drm/tiny/repaper.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tiny/repaper.c b/drivers/gpu/drm/tiny/repaper.c index 08164e2a2d13..2e01cf0a9876 100644 --- a/drivers/gpu/drm/tiny/repaper.c +++ b/drivers/gpu/drm/tiny/repaper.c @@ -88,7 +88,6 @@ struct repaper_epd { u8 *line_buffer; void *current_frame; - bool enabled; bool cleared; bool partial; }; @@ -538,9 +537,6 @@ static int repaper_fb_dirty(struct drm_framebuffer *fb) int idx, ret = 0; u8 *buf = NULL; - if (!epd->enabled) - return 0; - if (!drm_dev_enter(fb->dev, &idx)) return -ENODEV; @@ -786,7 +782,6 @@ static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe, */ repaper_write_val(spi, 0x02, 0x04); - epd->enabled = true; epd->partial = false; out_exit: drm_dev_exit(idx); @@ -805,13 +800,8 @@ static void repaper_pipe_disable(struct drm_simple_display_pipe *pipe) * unplug. */ - if (!epd->enabled) - return; - DRM_DEBUG_DRIVER("\n"); - epd->enabled = false; - /* Nothing frame */ for (line = 0; line < epd->height; line++) repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL, @@ -859,6 +849,9 @@ static void repaper_pipe_update(struct drm_simple_display_pipe *pipe, struct drm_plane_state *state = pipe->plane.state; struct drm_rect rect; + if (!pipe->crtc.state->active) + return; + if (drm_atomic_helper_damage_merged(old_state, state, &rect)) repaper_fb_dirty(state->fb); } -- 2.26.2 From patchwork at emeril.freedesktop.org Fri Jun 12 16:27:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 16:27:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_v?= =?utf-8?q?blank_on_crtc_reset?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159197922092.21338.7552488707279895957@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset URL : https://patchwork.freedesktop.org/series/78268/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8594ab0d8772 drm/atomic-helper: reset vblank on crtc reset -:295: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 148 lines checked 6b3eb4b7c982 drm/amdgpu: Use __drm_atomic_helper_crtc_reset -:34: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 10 lines checked 28631d9a3c40 drm/imx: Use __drm_atomic_helper_crtc_reset -:51: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 28 lines checked e4d4b48f9eb2 drm/mtk: Use __drm_atomic_helper_crtc_reset -:46: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 25 lines checked fe4a8b62c4cc drm/vc4: Use __drm_atomic_helper_crtc_reset -:28: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 11 lines checked 21eabe3e1ff5 drm/vmwgfx: Use __drm_atomic_helper_crtc_reset -:27: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 9 lines checked 7484cee23943 drm/mipi-dbi: Remove ->enabled -:191: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 136 lines checked e5322455e5a4 drm/tiny/repaper: Drop edp->enabled -:68: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 45 lines checked From patchwork at emeril.freedesktop.org Fri Jun 12 16:27:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 16:27:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_vblan?= =?utf-8?q?k_on_crtc_reset?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159197925335.21335.3506972076082606092@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset URL : https://patchwork.freedesktop.org/series/78268/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1126:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1126:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1126:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1128:36: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1195:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1195:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1195:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1201:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1227:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1229:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1233:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1234:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1237:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1576:16: warning: symbol 'amdgpu_dm_commit_zero_streams' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2696:24: warning: symbol 'dm_atomic_get_new_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2714:24: warning: symbol 'dm_atomic_get_old_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5537:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:699:6: warning: symbol 'amdgpu_dm_audio_eld_notify' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:754:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:758:23: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:759:23: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:762:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:765:28: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8921:6: warning: symbol 'amdgpu_dm_psr_enable' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8925:50: warning: missing braces around initializer From ville.syrjala at linux.intel.com Fri Jun 12 16:30:29 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 19:30:29 +0300 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch In-Reply-To: <20200526221447.64110-5-jose.souza@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-5-jose.souza@intel.com> Message-ID: <20200612163029.GK6112@intel.com> On Tue, May 26, 2020 at 03:14:46PM -0700, Jos? Roberto de Souza wrote: > All GEN12 platforms supports PSR2 selective fetch but not all GEN12 > platforms supports PSR2 hardware tracking(aka RKL). > > This feature consists in software program registers with the damaged > area of each plane this way hardware will only fetch from memory those > areas and sent the PSR2 selective update blocks to panel, saving even > more power but to it actually happen userspace needs to send the > damaged areas otherwise it will still fetch the whole plane as > fallback. > As today Gnome3 do not send damaged areas and the only compositor that > I'm aware that sets the damaged areas is Weston. > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > So here implementing page flip part, it is still completely missing > frontbuffer modifications, that is why the enable_psr2_sel_fetch > parameter was added. > > The plan is to switch all GEN12 platforms to selective fetch when > ready, it will also depend in add some tests sending damaged areas. > I have a hacked version of kms_psr2_su with 3 planes that I can > cleanup and send in a few days(99% of PSR2 selective fetch changes was > done during my free time while bored during quarantine rainy days). > > BSpec: 55229 > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 5 + > .../drm/i915/display/intel_display_debugfs.c | 3 + > .../drm/i915/display/intel_display_types.h | 10 + > drivers/gpu/drm/i915/display/intel_psr.c | 329 +++++++++++++++++- > drivers/gpu/drm/i915/display/intel_psr.h | 10 + > drivers/gpu/drm/i915/display/intel_sprite.c | 2 + > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/i915_params.c | 5 + > drivers/gpu/drm/i915/i915_params.h | 1 + > 9 files changed, 352 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index b69878334040..984809208c29 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -11729,6 +11729,8 @@ static void i9xx_update_cursor(struct intel_plane *plane, > if (INTEL_GEN(dev_priv) >= 9) > skl_write_cursor_wm(plane, crtc_state); > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state); > + > if (plane->cursor.base != base || > plane->cursor.size != fbc_ctl || > plane->cursor.cntl != cntl) { > @@ -15115,6 +15117,8 @@ static void commit_pipe_config(struct intel_atomic_state *state, > > if (new_crtc_state->update_pipe) > intel_pipe_fastset(old_crtc_state, new_crtc_state); > + > + intel_psr2_program_trans_man_trk_ctl(new_crtc_state); > } > > if (dev_priv->display.atomic_update_watermarks) > @@ -15156,6 +15160,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > intel_color_load_luts(new_crtc_state); > > intel_pre_plane_update(state, crtc); > + intel_psr2_sel_fetch_update(state, crtc); > > if (new_crtc_state->update_pipe) > intel_encoders_update_pipe(state, crtc); > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 70525623bcdf..0f600974462b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); > seq_printf(m, "%d\t%d\n", frame, su_blocks); > } > + > + seq_printf(m, "PSR2 selective fetch: %s\n", > + enableddisabled(psr->psr2_sel_fetch_enabled)); > } > > unlock: > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 30b2767578dc..b77a512e5362 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -586,6 +586,13 @@ struct intel_plane_state { > u32 planar_slave; > > struct drm_intel_sprite_colorkey ckey; > + > + struct { > + u32 ctl; > + u32 pos; > + u32 offset; > + u32 size; > + } psr2_sel_fetch; Do we really need all that here? We don't store them for the normal plane updates either. > }; > > struct intel_initial_plane_config { > @@ -931,6 +938,7 @@ struct intel_crtc_state { > > bool has_psr; > bool has_psr2; > + bool enable_psr2_sel_fetch; > u32 dc3co_exitline; > > /* > @@ -1070,6 +1078,8 @@ struct intel_crtc_state { > > /* For DSB related info */ > struct intel_dsb *dsb; > + > + u32 psr2_sw_man_track_ctl; > }; > > enum intel_pipe_crc_source { > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 0c86e9e341a2..bc2a2e64fe2a 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -518,6 +518,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > else > val |= EDP_PSR2_TP2_TIME_2500us; > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > + intel_de_write(dev_priv, > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), > + PSR2_MAN_TRK_CTL_ENABLE); > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > + intel_de_write(dev_priv, > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > * recommending keep this bit unset while PSR2 is enabled. > @@ -628,6 +636,38 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, > crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; > } > > +static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, > + struct intel_crtc_state *crtc_state) > +{ > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + struct intel_plane_state *plane_state; > + struct intel_plane *plane; > + int i; > + > + if (!i915_modparams.enable_psr2_sel_fetch) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 sel fetch not enabled, disabled by parameter\n"); > + return false; > + } > + > + if (crtc_state->uapi.async_flip) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 sel fetch not enabled, async flip enabled\n"); > + return false; > + } Not supported anyway. > + > + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { > + if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 sel fetch not enabled, plane rotated\n"); > + return false; > + } > + } > + > + return crtc_state->enable_psr2_sel_fetch = true; > +} > + > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state) > { > @@ -697,22 +737,17 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > - /* > - * Some platforms lack PSR2 HW tracking and instead require manual > - * tracking by software. In this case, the driver is required to track > - * the areas that need updates and program hardware to send selective > - * updates. > - * > - * So until the software tracking is implemented, PSR2 needs to be > - * disabled for platforms without PSR2 HW tracking. > - */ > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > - drm_dbg_kms(&dev_priv->drm, > - "No PSR2 HW tracking in the platform\n"); > - return false; > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > + if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > + !HAS_PSR_HW_TRACKING(dev_priv)) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); > + return false; > + } > } > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > + if (!crtc_state->enable_psr2_sel_fetch && > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { > drm_dbg_kms(&dev_priv->drm, > "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", > crtc_hdisplay, crtc_vdisplay, > @@ -863,6 +898,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, > val |= EXITLINE_ENABLE; > intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); > } > + > + if (HAS_PSR_HW_TRACKING(dev_priv)) > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, > + dev_priv->psr.psr2_sel_fetch_enabled ? > + IGNORE_PSR2_HW_TRACKING : 0); > } > > static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > @@ -884,7 +924,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > /* DC5/DC6 requires at least 6 idle frames */ > val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > dev_priv->psr.dc3co_exit_delay = val; > - > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; > /* > * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR > * will still keep the error set even after the reset done in the > @@ -1080,6 +1120,265 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) > intel_psr_exit(dev_priv); > } > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, > + const struct intel_crtc_state *crtc_state, > + const struct intel_plane_state *plane_state) > +{ > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); > + enum pipe pipe = plane->pipe; > + > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > + !plane_state || > + !crtc_state->enable_psr2_sel_fetch) > + return; > + > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), > + plane_state->psr2_sel_fetch.ctl); > + if (!plane_state->psr2_sel_fetch.ctl || plane->id == PLANE_CURSOR) > + return; > + > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), > + plane_state->psr2_sel_fetch.pos); > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > + plane_state->psr2_sel_fetch.offset); > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), > + plane_state->psr2_sel_fetch.size); > +} > + > +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + struct i915_psr *psr = &dev_priv->psr; > + > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > + !crtc_state->enable_psr2_sel_fetch) > + return; > + > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), > + crtc_state->psr2_sw_man_track_ctl); > +} > + > +static void intel_psr2_plane_sel_fetch_calc(struct intel_plane_state *plane_state, > + struct drm_rect *clip) > +{ > + int color_plane = plane_state->planar_linked_plane && !plane_state->planar_slave; > + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); > + u32 val; > + > + if (plane->id == PLANE_CURSOR) > + return; > + > + val = (plane_state->color_plane[color_plane].y + clip->y1) << 16; > + val |= plane_state->color_plane[color_plane].x; > + plane_state->psr2_sel_fetch.offset = val; > + > + val = (clip->y1 + plane_state->uapi.crtc_y) << 16; > + val |= plane_state->uapi.crtc_x; > + plane_state->psr2_sel_fetch.pos = val; > + > + /* Sizes are 0 based */ > + val = (clip->y2 - clip->y1 - 1) << 16; > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; > + plane_state->psr2_sel_fetch.size = val; > +} > + > +static void intel_psr2_trans_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, > + struct drm_rect *clip, > + bool full_update) > +{ > + u32 val = PSR2_MAN_TRK_CTL_ENABLE; > + > + if (full_update) { > + val |= PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME; > + goto exit; > + } > + > + if (clip->y1 == -1) > + goto exit; > + > + val |= PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE; > + val |= PSR2_MAN_TRK_CTL_REGION_START_ADDR(clip->y1 / 4 + 1); > + val |= PSR2_MAN_TRK_CTL_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1); > +exit: > + crtc_state->psr2_sw_man_track_ctl = val; > +} > + > +static void intel_psr2_plane_sel_fetch_ctl_calc(struct intel_plane *plane, > + struct intel_plane_state *plane_state, > + bool enable) > +{ > + if (!enable) > + plane_state->psr2_sel_fetch.ctl = 0; > + else if (plane->id == PLANE_CURSOR) > + plane_state->psr2_sel_fetch.ctl = plane->cursor.cntl; > + else > + plane_state->psr2_sel_fetch.ctl = plane_state->ctl; > +} > + > +static void clip_update(struct drm_rect *overlap_damage_area, > + struct drm_rect *damage_area) > +{ > + if (overlap_damage_area->y1 == -1) { > + overlap_damage_area->y1 = damage_area->y1; > + overlap_damage_area->y2 = damage_area->y2; > + return; > + } > + > + if (damage_area->y1 < overlap_damage_area->y1) > + overlap_damage_area->y1 = damage_area->y1; > + > + if (damage_area->y2 > overlap_damage_area->y2) > + overlap_damage_area->y2 = damage_area->y2; > +} > + > +/* Update plane damage area if planes above moved or have alpha */ > +static void intel_psr2_pipe_dirty_areas_set(struct intel_plane_state *plane_state, > + struct intel_plane *plane, > + const struct drm_rect *pipe_dirty_areas, > + struct drm_rect *plane_clip) > +{ > + enum plane_id i; > + > + for (i = PLANE_CURSOR; i > plane->id; i--) { > + int j; > + > + for (j = 0; j < 2; j++) { > + struct drm_rect r = pipe_dirty_areas[i * 2 + j]; > + > + if (!drm_rect_width(&r)) > + continue; > + if (!drm_rect_intersect(&r, &plane_state->uapi.dst)) > + continue; > + > + r.y1 -= plane_state->uapi.crtc_y; > + r.y2 -= plane_state->uapi.crtc_y; > + clip_update(plane_clip, &r); > + } > + } > +} > + > +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > +{ > + struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); > + struct intel_plane_state *new_plane_state, *old_plane_state; > + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = {}; > + struct drm_rect pipe_clip = { .y1 = -1 }; > + struct intel_plane *plane; > + bool full_update = false; > + int i; > + > + if (!crtc_state->enable_psr2_sel_fetch) > + return; > + > + /* > + * Load all the pipes areas where there is a plane with alpha or a plane > + * that moved or plane that the visibility changed in those > + * cases planes bellow it will need to be fetched in those intersection > + * areas even if they are not damaged in those areas. > + */ > + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, > + new_plane_state, i) { > + bool alpha, flip, dirty; > + > + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) > + continue; > + > + alpha = new_plane_state->uapi.alpha != U16_MAX; > + alpha |= old_plane_state->uapi.alpha != U16_MAX; > + flip = new_plane_state->uapi.fb != old_plane_state->uapi.fb; > + dirty = alpha && flip; > + dirty |= !drm_rect_equals(&new_plane_state->uapi.dst, > + &old_plane_state->uapi.dst); > + dirty |= new_plane_state->uapi.visible != > + old_plane_state->uapi.visible; > + if (!dirty) > + continue; > + > + if (old_plane_state->uapi.visible) > + pipe_dirty_areas[plane->id * 2] = old_plane_state->uapi.dst; > + if (new_plane_state->uapi.visible) > + pipe_dirty_areas[plane->id * 2 + 1] = new_plane_state->uapi.dst; > + } > + > + /* > + * Iterate over all planes, compute the damaged clip area also including > + * the pipe_dirty_areas, compute plane registers and update pipe damaged > + * area > + */ > + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, > + new_plane_state, i) { > + struct drm_rect plane_clip = { .y1 = -1 }; > + struct drm_mode_rect *clips; > + u32 num_clips; > + int j; > + > + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) > + continue; > + > + /* > + * TODO: Not clear how to handle planes with negative position, > + * also planes are not updated if they have a negative X > + * position so for now doing a full update in this cases > + */ > + if (new_plane_state->uapi.crtc_y < 0 || > + new_plane_state->uapi.crtc_x < 0) { > + full_update = true; > + break; > + } > + > + intel_psr2_plane_sel_fetch_ctl_calc(plane, new_plane_state, > + new_plane_state->uapi.visible); > + if (!new_plane_state->uapi.visible) > + continue; > + > + clips = drm_plane_get_damage_clips(&new_plane_state->uapi); > + num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); > + > + /* > + * If plane moved mark the whole plane area as damaged so it > + * can be complete draw in the new position > + */ > + if (!drm_rect_equals(&new_plane_state->uapi.dst, > + &old_plane_state->uapi.dst)) { > + num_clips = 0; > + plane_clip.y1 = new_plane_state->uapi.src.y1 >> 16; > + plane_clip.y2 = new_plane_state->uapi.src.y2 >> 16; > + } else if (!num_clips) { > + /* > + * If plane don't have damage areas but the framebuffer > + * changed mark the whole plane as damaged > + */ > + if (new_plane_state->uapi.fb == old_plane_state->uapi.fb) > + continue; > + > + plane_clip.y1 = new_plane_state->uapi.src.y1 >> 16; > + plane_clip.y2 = new_plane_state->uapi.src.y2 >> 16; > + } > + > + for (j = 0; j < num_clips; j++) { > + struct drm_rect damage_area; > + > + damage_area.x1 = clips[j].x1; > + damage_area.x2 = clips[j].x2; > + damage_area.y1 = clips[j].y1; > + damage_area.y2 = clips[j].y2; > + clip_update(&plane_clip, &damage_area); > + } > + > + intel_psr2_pipe_dirty_areas_set(new_plane_state, plane, > + pipe_dirty_areas, &plane_clip); > + intel_psr2_plane_sel_fetch_calc(new_plane_state, &plane_clip); > + > + plane_clip.y1 += new_plane_state->uapi.crtc_y; > + plane_clip.y2 += new_plane_state->uapi.crtc_y; > + clip_update(&pipe_clip, &plane_clip); > + } This whole thing seems rather convoluted. Also using lots of uapi state in places where I don't expect to see any. I would suggest the correct way would be something like: 1) for_each_plane_in_state() hw.damage = translate_to_some_hw_coord_space(union(uapi.damages)) or just use the full plane size if we have scaling i guess 2) need to add all affected planes to the state and set the appropriate bitmask, which may mean we want to track the planes' positions in the crtc state. I think atm we only have it in the plane state 3) translate the damage further into the final plane src coordinate space. Dunno if we have enough state around still to do it cleanly. I was thinking maybe it could be done alongside all the other plane surface calculations, but there might be a chicken vs. egg situation here since we probably want to do the plane check stuff before doing step 1, but plane check is also where we do the surface calculations. Dunno if we may just want to split the plane check into two stages To keep things simple I guess what I'd suggest is to forget about the damage stuff in the first version of the series and just do full plane updates. That way we don't have to worry about so many coordinate space transformations. > + > + intel_psr2_trans_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); > +} > + > /** > * intel_psr_update - Update PSR state > * @intel_dp: Intel DP > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h > index b4515186d5f4..d80bd0e46b21 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.h > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > @@ -13,6 +13,10 @@ struct drm_connector_state; > struct drm_i915_private; > struct intel_crtc_state; > struct intel_dp; > +struct intel_crtc; > +struct intel_atomic_state; > +struct intel_plane_state; > +struct intel_plane; > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) > void intel_psr_init_dpcd(struct intel_dp *intel_dp); > @@ -43,5 +47,11 @@ void intel_psr_atomic_check(struct drm_connector *connector, > struct drm_connector_state *old_state, > struct drm_connector_state *new_state); > void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp); > +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > + struct intel_crtc *crtc); > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, > + const struct intel_crtc_state *crtc_state, > + const struct intel_plane_state *plane_state); > +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); > > #endif /* __INTEL_PSR_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > index 8be06cb25999..afede372ac05 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -690,6 +690,8 @@ skl_program_plane(struct intel_plane *plane, > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), > (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state); > + > /* > * The control register self-arms if the plane was previously > * disabled. Try to make the plane enable atomic by writing > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 146bfd276ce7..ae7efc922393 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -503,6 +503,7 @@ struct i915_psr { > bool link_standby; > bool colorimetry_support; > bool psr2_enabled; > + bool psr2_sel_fetch_enabled; > u8 sink_sync_latency; > ktime_t last_entry_attempt; > ktime_t last_exit; > @@ -1634,6 +1635,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > #define HAS_PSR_HW_TRACKING(dev_priv) \ > (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) > +#define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12) > #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) > > #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) > diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c > index add00ec1f787..3005451c1194 100644 > --- a/drivers/gpu/drm/i915/i915_params.c > +++ b/drivers/gpu/drm/i915/i915_params.c > @@ -88,6 +88,11 @@ i915_param_named_unsafe(enable_psr, int, 0600, > "(0=disabled, 1=enabled) " > "Default: -1 (use per-chip default)"); > > +i915_param_named_unsafe(enable_psr2_sel_fetch, int, 0400, > + "Enable PSR2 selective fetch " > + "(0=disabled, 1=enabled) " > + "Default: 0"); > + > i915_param_named_unsafe(force_probe, charp, 0400, > "Force probe the driver for specified devices. " > "See CONFIG_DRM_I915_FORCE_PROBE for details."); > diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h > index 45323732f099..5a0b16923016 100644 > --- a/drivers/gpu/drm/i915/i915_params.h > +++ b/drivers/gpu/drm/i915/i915_params.h > @@ -53,6 +53,7 @@ struct drm_printer; > param(int, enable_dc, -1, 0400) \ > param(int, enable_fbc, -1, 0600) \ > param(int, enable_psr, -1, 0600) \ > + param(int, enable_psr2_sel_fetch, 0, 0400) \ > param(int, disable_power_well, -1, 0400) \ > param(int, enable_ips, 1, 0600) \ > param(int, invert_brightness, 0, 0600) \ > -- > 2.26.2 -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Fri Jun 12 16:48:05 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 16:48:05 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_vblank_o?= =?utf-8?q?n_crtc_reset?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159198048506.21336.2224248953824410616@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset URL : https://patchwork.freedesktop.org/series/78268/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17941 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/index.html Known issues ------------ Here are the changes found in Patchwork_17941 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_selftest@live at gt_heartbeat: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#337]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-apl-guc/igt at i915_selftest@live at gt_heartbeat.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-apl-guc/igt at i915_selftest@live at gt_heartbeat.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][5] ([i915#1993]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#337]: https://gitlab.freedesktop.org/drm/intel/issues/337 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 42) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17941 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17941: e5322455e5a4c5c50f4d2aebd49b76b46e3153b2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e5322455e5a4 drm/tiny/repaper: Drop edp->enabled 7484cee23943 drm/mipi-dbi: Remove ->enabled 21eabe3e1ff5 drm/vmwgfx: Use __drm_atomic_helper_crtc_reset fe4a8b62c4cc drm/vc4: Use __drm_atomic_helper_crtc_reset e4d4b48f9eb2 drm/mtk: Use __drm_atomic_helper_crtc_reset 28631d9a3c40 drm/imx: Use __drm_atomic_helper_crtc_reset 6b3eb4b7c982 drm/amdgpu: Use __drm_atomic_helper_crtc_reset 8594ab0d8772 drm/atomic-helper: reset vblank on crtc reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/index.html From hdegoede at redhat.com Fri Jun 12 16:59:58 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Fri, 12 Jun 2020 18:59:58 +0200 Subject: [Intel-gfx] [PATCH v2 09/15] pwm: crc: Enable/disable PWM output on enable/disable In-Reply-To: <20200611222029.csyo2wxof7nuhjws@taurus.defre.kleine-koenig.org> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-10-hdegoede@redhat.com> <20200611222029.csyo2wxof7nuhjws@taurus.defre.kleine-koenig.org> Message-ID: <1af668ef-7b42-340a-8aa2-f66c266ac6ef@redhat.com> Hi, On 6/12/20 12:20 AM, Uwe Kleine-K??nig wrote: > On Sun, Jun 07, 2020 at 08:18:34PM +0200, Hans de Goede wrote: >> The pwm-crc code is using 2 different enable bits: >> 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) >> 2. bit 0 of the BACKLIGHT_EN register >> >> So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, >> this commit makes crc_pwm_disable() clear it on disable and makes >> crc_pwm_enable() set it again on re-enable. >> >> This should disable the internal (divided) PWM clock and tri-state the >> PWM output pin when disabled, saving some power. > > It would be great if you could also document that disabling the PWM > makes the output tri-state. There are a few drivers that have a > "Limitations" section at their top. Describing that there (in the same > format) would be the right place. > > Also note that according to Thierry's conception getting a (driven) > inactive output is the right thing for a disabled PWM. Hmm, the tri-state thing is an assumption from my side and we don't have any docs for this PWM controller, so I'm not sure at all if that is true. So I think it will be better to just drop the tri-state bit from the commit msg for the next version. Regards, Hans From hdegoede at redhat.com Fri Jun 12 17:00:42 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Fri, 12 Jun 2020 19:00:42 +0200 Subject: [Intel-gfx] [PATCH v2 11/15] pwm: crc: Implement get_state() method In-Reply-To: <20200611213744.6gg2oy45cende6ba@taurus.defre.kleine-koenig.org> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-12-hdegoede@redhat.com> <20200611213744.6gg2oy45cende6ba@taurus.defre.kleine-koenig.org> Message-ID: <f2a268ef-2b65-d027-0b0c-b83e12a04f20@redhat.com> Hi, On 6/11/20 11:37 PM, Uwe Kleine-K??nig wrote: > Hello, > > On Sun, Jun 07, 2020 at 08:18:36PM +0200, Hans de Goede wrote: >> Implement the pwm_ops.get_state() method to complete the support for the >> new atomic PWM API. >> >> Signed-off-by: Hans de Goede <hdegoede at redhat.com> >> --- >> drivers/pwm/pwm-crc.c | 29 +++++++++++++++++++++++++++++ >> 1 file changed, 29 insertions(+) >> >> diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c >> index 58c7e9ef7278..6c75a3470bc8 100644 >> --- a/drivers/pwm/pwm-crc.c >> +++ b/drivers/pwm/pwm-crc.c >> @@ -114,8 +114,37 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, >> return 0; >> } >> >> +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, >> + struct pwm_state *state) >> +{ >> + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); >> + struct device *dev = crc_pwm->chip.dev; >> + unsigned int clk_div, clk_div_reg, duty_cycle_reg; >> + int error; >> + >> + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); >> + if (error) { >> + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); >> + return; >> + } >> + >> + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); >> + if (error) { >> + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); >> + return; >> + } > > I assume that duty_cycle_reg cannot be bigger than 0xff? Would it make > sense to mask the value accordingly to get more robust code? > >> + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; >> + >> + state->period = clk_div * NSEC_PER_MHZ * 256 / PWM_BASE_CLK_MHZ; >> + state->duty_cycle = duty_cycle_reg * state->period / PWM_MAX_LEVEL; >> + state->polarity = PWM_POLARITY_NORMAL; >> + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); > > These aligned = look strange (IMHO). If you don't feel strong here I'd > like to see a single space before a =. Ok, will change for the next version. Regards, Hans From hdegoede at redhat.com Fri Jun 12 17:04:51 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Fri, 12 Jun 2020 19:04:51 +0200 Subject: [Intel-gfx] pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API In-Reply-To: <20200611212144.i7ma7kriznidds4r@taurus.defre.kleine-koenig.org> References: <20200606202601.48410-1-hdegoede@redhat.com> <20200608143500.GX20149@phenom.ffwll.local> <20200611212144.i7ma7kriznidds4r@taurus.defre.kleine-koenig.org> Message-ID: <58972efb-003d-ca87-0637-ece4c93aeeb5@redhat.com> Hi, On 6/11/20 11:21 PM, Uwe Kleine-K??nig wrote: > Hello, > > On Mon, Jun 08, 2020 at 04:35:00PM +0200, Daniel Vetter wrote: >> On Sat, Jun 06, 2020 at 10:25:45PM +0200, Hans de Goede wrote: >>> Hi All, >>> >>> This patch series converts the i915 driver's cpde for controlling the >>> panel's backlight with an external PWM controller to use the atomic PWM API. >>> >>> Initially the plan was for this series to consist of 2 parts: >>> 1. convert the pwm-crc driver to support the atomic PWM API and >>> 2. convert the i915 driver's PWM code to use the atomic PWM API. >>> >>> But during testing I've found a number of bugs in the pwm-lpss and I >>> found that the acpi_lpss code needs some special handling because of >>> some ugliness found in most Cherry Trail DSDTs. >>> >>> So now this series has grown somewhat large and consists of 4 parts: >>> >>> 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness >>> 2. various fixes to the pwm-lpss driver >>> 3. convert the pwm-crc driver to support the atomic PWM API and >>> 4. convert the i915 driver's PWM code to use the atomic PWM API >>> >>> So we need to discuss how to merge this (once it passes review). >>> Although the inter-dependencies are only runtime I still think we should >>> make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before >>> merging the i915 changes. Both to make sure that the intel-gfx CI system >>> does not become unhappy and for bisecting reasons. >> >> Simplest is if acpi acks the acpi patches for merging through >> drm-intel.git. Second simplest is topic branch (drm-intel maintainers can >> do that) with the entire pile, which then acpi and drm-intel can both pull >> in. >> >> Up to the two maintainer teams to figure this one out. > > I'm unclear about the dependencies There is a runtime dependency of the i915 changes on the PWM changes and since the intel-gfx folks use a lot of CI, we this need to get the PWM changes into the drm-intel tree before the i915 changes can land. > , but the changes to drivers/pwm need > an ack (or processing) by the PWM team. Of course, I asked for an Acked-by from the PWM team (once this passes review) for merging this through the drm-intel tree, as the i915 driver is the main (only AFAIK) consumer of the PWMs controlled by these 2 drivers. Daniel <snip>-ed that bit when he replied. Regards, Hans From alexdeucher at gmail.com Fri Jun 12 17:41:17 2020 From: alexdeucher at gmail.com (Alex Deucher) Date: Fri, 12 Jun 2020 13:41:17 -0400 Subject: [Intel-gfx] [PATCH 2/8] drm/amdgpu: Use __drm_atomic_helper_crtc_reset In-Reply-To: <ad375dbb-760b-b2e9-cfab-94fba61f4eb7@amd.com> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-2-daniel.vetter@ffwll.ch> <ad375dbb-760b-b2e9-cfab-94fba61f4eb7@amd.com> Message-ID: <CADnq5_NY1P8nM9gSL9zb1fpizsFxgRwvztQRg426-fEKMupq+w@mail.gmail.com> On Fri, Jun 12, 2020 at 1:24 PM Harry Wentland <hwentlan at amd.com> wrote: > > On 2020-06-12 12:00 p.m., Daniel Vetter wrote: > > Now also comes with the added benefit of doing a drm_crtc_vblank_off(), > > which means vblank state isn't ill-defined and fail-y at driver load > > before the first modeset on each crtc. > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Cc: Alex Deucher <alexander.deucher at amd.com> > > Cc: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> > > Cc: Harry Wentland <harry.wentland at amd.com> > > Cc: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com> > > Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com> > > Cc: Roman Li <roman.li at amd.com> > > Cc: Mikita Lipski <mikita.lipski at amd.com> > > Cc: Stylon Wang <stylon.wang at amd.com> > > Reviewed-by: Harry Wentland <harry.wentland at amd.com> > Daniel, do you want to take the whole series, or should I pull this in through my tree? Either way works for me. Thanks for the patch! Alex > Harry > > > --- > > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- > > 1 file changed, 1 insertion(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > index 68a73065b516..36d605a6eb16 100644 > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > @@ -4594,9 +4594,7 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc) > > if (WARN_ON(!state)) > > return; > > > > - crtc->state = &state->base; > > - crtc->state->crtc = crtc; > > - > > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > > } > > > > static struct drm_crtc_state * > > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From patchwork at emeril.freedesktop.org Fri Jun 12 18:04:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 18:04:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_vblank_o?= =?utf-8?q?n_crtc_reset?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159198509734.21337.8965740282602185091@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset URL : https://patchwork.freedesktop.org/series/78268/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621_full -> Patchwork_17941_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17941_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17941_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17941_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_balancer@bonded-early: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb7/igt at gem_exec_balancer@bonded-early.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-tglb1/igt at gem_exec_balancer@bonded-early.html * igt at perf_pmu@busy-check-all at rcs0: - shard-snb: [PASS][3] -> [FAIL][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb2/igt at perf_pmu@busy-check-all at rcs0.html Known issues ------------ Here are the changes found in Patchwork_17941_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-concurrent0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#1930]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl1/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-fds-forked-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk7/igt at gem_exec_whisper@basic-fds-forked-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-glk2/igt at gem_exec_whisper@basic-fds-forked-all.html * igt at gem_mmap@bad-size: - shard-snb: [PASS][9] -> [TIMEOUT][10] ([i915#1958]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_mmap@bad-size.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb2/igt at gem_mmap@bad-size.html * igt at i915_module_load@reload: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk5/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html * igt at kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt at kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl2/igt at kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size.html * igt at kms_flip@flip-vs-suspend-interruptible at b-dp1: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl6/igt at kms_flip@flip-vs-suspend-interruptible at b-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) +3 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_basic: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb2/igt at kms_psr@psr2_basic.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-iclb3/igt at kms_psr@psr2_basic.html * igt at kms_universal_plane@disable-primary-vs-flip-pipe-c: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +5 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-skl5/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-kbl4/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at perf_pmu@busy-check-all at vcs0: - shard-snb: [PASS][33] -> [INCOMPLETE][34] ([i915#82]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at vcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb2/igt at perf_pmu@busy-check-all at vcs0.html * igt at syncobj_wait@single-wait-for-submit-unsubmitted: - shard-apl: [PASS][35] -> [DMESG-WARN][36] ([i915#95]) +22 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at syncobj_wait@single-wait-for-submit-unsubmitted.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl6/igt at syncobj_wait@single-wait-for-submit-unsubmitted.html #### Possible fixes #### * igt at gem_exec_schedule@implicit-read-write at bcs0: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb1/igt at gem_exec_schedule@implicit-read-write at bcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb1/igt at gem_exec_schedule@implicit-read-write at bcs0.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [DMESG-WARN][39] ([i915#402]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_selftest@perf at request: - shard-tglb: [DMESG-FAIL][41] ([i915#1823]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt at i915_selftest@perf at request.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-tglb2/igt at i915_selftest@perf at request.html * igt at kms_big_fb@linear-8bpp-rotate-0: - shard-apl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_big_fb@linear-8bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl6/igt at kms_big_fb@linear-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl7/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +5 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl6/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-skl2/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-hsw: [DMESG-WARN][49] ([i915#128]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw4/igt at kms_cursor_legacy@pipe-c-torture-bo.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-hsw2/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1: - shard-hsw: [INCOMPLETE][51] ([i915#61]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw1/igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-hsw6/igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +8 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-kbl1/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][55] ([i915#69]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-skl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb5/igt at kms_psr@psr2_cursor_plane_move.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_setmode@basic: - shard-apl: [FAIL][59] ([i915#31]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_setmode@basic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl4/igt at kms_setmode@basic.html - shard-kbl: [FAIL][61] ([i915#31]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl7/igt at kms_setmode@basic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-kbl7/igt at kms_setmode@basic.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at perf@blocking-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-iclb5/igt at perf@blocking-parameterized.html * igt at perf_pmu@other-read-0: - shard-apl: [DMESG-WARN][65] ([i915#95]) -> [PASS][66] +23 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl4/igt at perf_pmu@other-read-0.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl2/igt at perf_pmu@other-read-0.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][67] ([i915#1820]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: [SKIP][69] ([fdo#109271] / [i915#1099]) -> [INCOMPLETE][70] ([i915#82]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_ctx_persistence@legacy-engines-mixed-process.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb2/igt at gem_ctx_persistence@legacy-engines-mixed-process.html * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][71] ([i915#1930]) -> [TIMEOUT][72] ([i915#1958]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc5-dpms: - shard-snb: [SKIP][73] ([fdo#109271]) -> [INCOMPLETE][74] ([i915#82]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb2/igt at i915_pm_dc@dc5-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb2/igt at i915_pm_dc@dc5-dpms.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][75] ([i915#468]) -> [FAIL][76] ([i915#454]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-tglb8/igt at i915_pm_dc@dc6-dpms.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][77] ([i915#1319] / [i915#1958]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-kbl1/igt at kms_content_protection@atomic.html - shard-apl: [DMESG-FAIL][79] ([fdo#110321]) -> [FAIL][80] ([fdo#110321] / [fdo#110336]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_content_protection@atomic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][81] ([i915#1319]) -> [DMESG-FAIL][82] ([fdo#110321] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl3/igt at kms_content_protection@atomic-dpms.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-kbl2/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][83] ([i915#1319]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_content_protection@lic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl7/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [DMESG-FAIL][85] ([fdo#110321]) -> [TIMEOUT][86] ([i915#1319] / [i915#1635]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_content_protection@srm.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl1/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][87] ([i915#180] / [i915#95]) -> [DMESG-WARN][88] ([i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt: - shard-snb: [SKIP][89] ([fdo#109271]) -> [TIMEOUT][90] ([i915#1958]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/shard-snb2/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17941 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17941: e5322455e5a4c5c50f4d2aebd49b76b46e3153b2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17941/index.html From manasi.d.navare at intel.com Fri Jun 12 18:25:42 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 11:25:42 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200604210319.GJ6112@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> Message-ID: <20200612182542.GA7458@intel.com> On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > ++++++++++++++++++++++++++------- > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > intel_dp *intel_dp) > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > >base.base.crtc); > > > > enum pipe pipe = crtc->pipe; > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > dp_tp_ctl_value; > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > + enum port port = intel_dig_port->base.port; > > > > + i915_reg_t dp_tp_reg; > > > > + > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > + } > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > TRANS_DDI_FUNC_CTL(pip > > > > e)); > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > + trans_ddi_port_mask); > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > trans_ddi_func_ctl_value); > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > have different bugs than the norma modeset paths, so compliance > > > testing > > > this special code proves absolutely nothing about the normal modeset > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > just perform normal modesets. > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > panic when we try to access to_intel_crtc(intel_dig_port- > > >base.base.crtc). > > Yeah, that's a legacy pointer which should no longer be used at all > with atomic drivers. I'm slowly trying to clear out all this legacy > cruft. The next step I had hoped to take was > https://patchwork.freedesktop.org/series/76993/ but then this > compliacnce stuff landed and threw another wrench into the works. We had several discussions on design of DP PHY compliance and the patches were on the M-L for quite some time without anyone giving feedback on the actual design of whether they should happen through modeset or directly from the PHY comp request short pulse. My first feedback was also that this should happen through a complete modeset where after we get PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. But honestly that was just a lot of overhead and The reason we decided to go with this ad hoc approach was that with PHY compliance request, nothing really changes in terms of link parameters so we do not need to go through a complete modeset request unlike link layer compliance where we need to do compute config all over again to do the link params computation. Every PHY comp request first sends a link layer comp request that does a full modeset and sets up the desired link rate/lane count. Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. Now i think if we need to scale this to other platforms, can we add a per platform hook for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and reenables the already set link? We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. Ville, Khaled ? Regards Manasi > > -- > Ville Syrj?l? > Intel > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From manasi.d.navare at intel.com Fri Jun 12 18:33:45 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 11:33:45 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> Message-ID: <20200612183345.GB7458@intel.com> On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > ++++++++++++++++++++++++++------- > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 7223367171d1..44663e8ac9a1 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > intel_dp *intel_dp) > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > >base.base.crtc); > > > enum pipe pipe = crtc->pipe; > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > dp_tp_ctl_value; > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > + enum port port = intel_dig_port->base.port; > > > + i915_reg_t dp_tp_reg; > > > + > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > + dp_tp_reg = DP_TP_CTL(port); > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > + } > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > TRANS_DDI_FUNC_CTL(pip > > > e)); > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > - TGL_TRANS_DDI_PORT_MASK); > > > + trans_ddi_port_mask); > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > trans_ddi_func_ctl_value); > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > All this ad-hoc modeset code really should not exist. It's going to > > have different bugs than the norma modeset paths, so compliance > > testing > > this special code proves absolutely nothing about the normal modeset > > code. IMO someone needs to take up the task of rewrtiting all this to > > just perform normal modesets. But isnt that behaviour of the scope against the compliance spec? The PHY request as per the VESA compliance spec should only come through a short pulse. Yes if it comes through a long pulse, it will reset the link and this whole code will fall apart. Manasi > > Agree. I've just found that we get kernel NULL pointer dereference and > panic when we try to access to_intel_crtc(intel_dig_port- > >base.base.crtc). This is because we didn't realize when we developed > the code that test scope has an option to send PHY test request on Long > HPD. Current desing assume PHY test request on short HPD. Because of > that we got the following error > > > [ 106.810882] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] > digital hpd on [ENCODER:308:DDI F] - long > [ 106.810916] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] > Received HPD interrupt on PIN 9 - cnt: 10 > [ 106.811026] i915 0000:00:02.0: [drm:intel_dp_hpd_pulse [i915]] got > hpd irq on [ENCODER:308:DDI F] - long > [ 106.811095] i915 0000:00:02.0: [drm:i915_hotplug_work_func [i915]] > running encoder hotplug functions > [ 106.811184] i915 0000:00:02.0: [drm:i915_hotplug_work_func [i915]] > Connector DP-3 (pin 9) received hotplug event. (retry 0) > [ 106.811227] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] > [CONNECTOR:309:DP-3] > [ 106.811292] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] > enabling TC cold off > [ 106.811365] i915 0000:00:02.0: [drm:tgl_tc_cold_request [i915]] TC > cold block succeeded > [ 106.811489] i915 0000:00:02.0: [drm:__intel_tc_port_lock [i915]] > Port F/TC#3: TC port mode reset (tbt-alt -> dp-alt) > [ 106.811663] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] > enabling AUX F TC3 > [ 106.812449] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00000 AUX -> > (ret= 15) 12 14 04 80 00 00 01 00 00 00 00 00 00 00 00 > [ 106.812484] i915 0000:00:02.0: [drm:intel_dp_read_dpcd [i915]] DPCD: > 12 14 04 80 00 00 01 00 00 00 00 00 00 00 00 > [ 106.813266] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00400 AUX -> > (ret= 12) 00 00 00 00 00 00 00 00 00 00 00 00 > [ 106.813271] [drm:drm_dp_read_desc] DP sink: OUI 00-00-00 dev-ID HW- > rev 0.0 SW-rev 0.0 quirks 0x0000 > [ 106.813891] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00200 AUX -> > (ret= 1) 01 > [ 106.813940] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] > source rates: 162000, 216000, 270000, 324000, 432000, 540000, 648000, > 810000 > [ 106.813974] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] > sink rates: 162000, 270000, 540000 > [ 106.814007] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] > common rates: 162000, 270000, 540000 > [ 106.814550] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00021 AUX -> > (ret= 1) 00 > [ 106.814583] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] > [ENCODER:308:DDI F] MST support: port: yes, sink: no, modparam: yes > > ..... > > [ 106.927291] i915 0000:00:02.0: [drm:intel_dp_check_service_irq > [i915]] PHY_PATTERN test requested > [ 106.927897] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00219 AUX -> > (ret= 1) 0a > [ 106.928507] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00220 AUX -> > (ret= 1) 04 > [ 106.929143] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00248 AUX -> > (ret= 1) 00 > [ 106.929824] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00202 AUX -> > (ret= 6) 00 00 80 00 00 00 > [ 106.929830] BUG: kernel NULL pointer dereference, address: > 0000000000000578 > [ 106.936809] #PF: supervisor read access in kernel mode > [ 106.941953] #PF: error_code(0x0000) - not-present page > [ 106.947082] PGD 0 P4D 0 > [ 106.949643] Oops: 0000 [#1] PREEMPT SMP NOPTI > [ 106.954010] CPU: 6 PID: 200 Comm: kworker/6:2 Not tainted 5.7.0-rc7- > CI-CI_DRM_8566+ #5 > [ 106.975251] Workqueue: events i915_hotplug_work_func [i915] > [ 106.980887] RIP: 0010:intel_dp_process_phy_request+0x94/0x5a0 [i915] > [ 106.987239] Code: 48 83 c4 20 5b 5d 41 5c 41 5d 41 5e 41 5f c3 48 8d > 74 24 12 4c 89 f7 e8 3a 3e 00 00 49 8b 86 28 ff ff ff 49 8b 9e d8 fe ff > ff <48> 63 80 78 05 00 00 8b 93 54 0d 00 00 48 8d ab e8 0e 00 00 48 89 > [ 107.005890] RSP: 0018:ffffc9000046fb20 EFLAGS: 00010246 > > I plan to temporarily fix this issue by ignoreing scope request on long > HPD, until we have modeset based implementation. > > > > } > > > > > > static void > > > @@ -5497,20 +5507,28 @@ intel_dp_autotest_phy_ddi_enable(struct > > > intel_dp *intel_dp, uint8_t lane_cnt) > > > enum port port = intel_dig_port->base.port; > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > >base.base.crtc); > > > enum pipe pipe = crtc->pipe; > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > dp_tp_ctl_value; > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > dp_tp_ctl_value, trans_ddi_sel_port; > > > + i915_reg_t dp_tp_reg; > > > + > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > + dp_tp_reg = DP_TP_CTL(port); > > > + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); > > > + } > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > TRANS_DDI_FUNC_CTL(pip > > > e)); > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > - > > > trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | > > > - TGL_TRANS_DDI_SELECT_PORT(port); > > > + trans_ddi_sel_port; > > > trans_conf_value |= PIPECONF_ENABLE; > > > dp_tp_ctl_value |= DP_TP_CTL_ENABLE; > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > trans_ddi_func_ctl_value); > > > } > > > @@ -5557,6 +5575,7 @@ static u8 > > > intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) > > > static void intel_dp_handle_test_request(struct intel_dp > > > *intel_dp) > > > { > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > + struct drm_i915_private *dev_priv = i915; > > > u8 response = DP_TEST_NAK; > > > u8 request = 0; > > > int status; > > > @@ -5582,6 +5601,11 @@ static void > > > intel_dp_handle_test_request(struct intel_dp *intel_dp) > > > response = intel_dp_autotest_edid(intel_dp); > > > break; > > > case DP_TEST_LINK_PHY_TEST_PATTERN: > > > + if (!IS_ELKHARTLAKE(dev_priv) || > > > !IS_TIGERLAKE(dev_priv)) { > > > + drm_dbg_kms(&i915->drm, > > > + "PHY compliance for platform not > > > supported\n"); > > > + return; > > > + } > > > drm_dbg_kms(&i915->drm, "PHY_PATTERN test > > > requested\n"); > > > response = intel_dp_autotest_phy_pattern(intel_dp); > > > break; > > > -- > > > 2.7.4 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From ville.syrjala at linux.intel.com Fri Jun 12 18:36:37 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 21:36:37 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612182542.GA7458@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> <20200612182542.GA7458@intel.com> Message-ID: <20200612183637.GL6112@intel.com> On Fri, Jun 12, 2020 at 11:25:42AM -0700, Manasi Navare wrote: > On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > > ++++++++++++++++++++++++++------- > > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > > intel_dp *intel_dp) > > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > > >base.base.crtc); > > > > > enum pipe pipe = crtc->pipe; > > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > dp_tp_ctl_value; > > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > > + enum port port = intel_dig_port->base.port; > > > > > + i915_reg_t dp_tp_reg; > > > > > + > > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > > + } > > > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > > TRANS_DDI_FUNC_CTL(pip > > > > > e)); > > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > > + trans_ddi_port_mask); > > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > > trans_ddi_func_ctl_value); > > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > > have different bugs than the norma modeset paths, so compliance > > > > testing > > > > this special code proves absolutely nothing about the normal modeset > > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > > just perform normal modesets. > > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > > panic when we try to access to_intel_crtc(intel_dig_port- > > > >base.base.crtc). > > > > Yeah, that's a legacy pointer which should no longer be used at all > > with atomic drivers. I'm slowly trying to clear out all this legacy > > cruft. The next step I had hoped to take was > > https://patchwork.freedesktop.org/series/76993/ but then this > > compliacnce stuff landed and threw another wrench into the works. > > We had several discussions on design of DP PHY compliance and the patches were on the M-L > for quite some time without anyone giving feedback on the actual design of whether they should > happen through modeset or directly from the PHY comp request short pulse. > My first feedback was also that this should happen through a complete modeset where after we get > PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. > But honestly that was just a lot of overhead and > The reason we decided to go with this ad hoc approach was that with PHY compliance request, > nothing really changes in terms of link parameters so we do not need to go through > a complete modeset request unlike link layer compliance where we need to do compute config > all over again to do the link params computation. > > Every PHY comp request first sends a link layer comp request that does a full modeset > and sets up the desired link rate/lane count. > Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns > and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. > > Now i think if we need to scale this to other platforms, can we add a per platform hook > for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and > reenables the already set link? > > We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly > with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. > > Ville, Khaled ? You're just multiplying the amount of work and bugs we have for every platform. And as said testing some special compliance paths proves pretty much nothing about the real code paths. So the only point of that code AFAICS it to tick some "we haz compliance code?" checkbox in some random spreadsheet instead of actually providing evidence that our real code works correctly. -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Fri Jun 12 18:39:22 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 21:39:22 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612183345.GB7458@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200612183345.GB7458@intel.com> Message-ID: <20200612183922.GM6112@intel.com> On Fri, Jun 12, 2020 at 11:33:45AM -0700, Manasi Navare wrote: > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > ++++++++++++++++++++++++++------- > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > intel_dp *intel_dp) > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > >base.base.crtc); > > > > enum pipe pipe = crtc->pipe; > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > dp_tp_ctl_value; > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > + enum port port = intel_dig_port->base.port; > > > > + i915_reg_t dp_tp_reg; > > > > + > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > + } > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > TRANS_DDI_FUNC_CTL(pip > > > > e)); > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > + trans_ddi_port_mask); > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > trans_ddi_func_ctl_value); > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > have different bugs than the norma modeset paths, so compliance > > > testing > > > this special code proves absolutely nothing about the normal modeset > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > just perform normal modesets. > > But isnt that behaviour of the scope against the compliance spec? scope? > The PHY request as per the VESA compliance spec should only come through > a short pulse. > Yes if it comes through a long pulse, it will reset the link and this whole > code will fall apart. I am not saying anything about how the sink signals the requests. That's just an implementation detail that doesn't really matter. > > Manasi > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > panic when we try to access to_intel_crtc(intel_dig_port- > > >base.base.crtc). This is because we didn't realize when we developed > > the code that test scope has an option to send PHY test request on Long > > HPD. Current desing assume PHY test request on short HPD. Because of > > that we got the following error > > > > > > [ 106.810882] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] > > digital hpd on [ENCODER:308:DDI F] - long > > [ 106.810916] i915 0000:00:02.0: [drm:intel_hpd_irq_handler [i915]] > > Received HPD interrupt on PIN 9 - cnt: 10 > > [ 106.811026] i915 0000:00:02.0: [drm:intel_dp_hpd_pulse [i915]] got > > hpd irq on [ENCODER:308:DDI F] - long > > [ 106.811095] i915 0000:00:02.0: [drm:i915_hotplug_work_func [i915]] > > running encoder hotplug functions > > [ 106.811184] i915 0000:00:02.0: [drm:i915_hotplug_work_func [i915]] > > Connector DP-3 (pin 9) received hotplug event. (retry 0) > > [ 106.811227] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] > > [CONNECTOR:309:DP-3] > > [ 106.811292] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] > > enabling TC cold off > > [ 106.811365] i915 0000:00:02.0: [drm:tgl_tc_cold_request [i915]] TC > > cold block succeeded > > [ 106.811489] i915 0000:00:02.0: [drm:__intel_tc_port_lock [i915]] > > Port F/TC#3: TC port mode reset (tbt-alt -> dp-alt) > > [ 106.811663] i915 0000:00:02.0: [drm:intel_power_well_enable [i915]] > > enabling AUX F TC3 > > [ 106.812449] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00000 AUX -> > > (ret= 15) 12 14 04 80 00 00 01 00 00 00 00 00 00 00 00 > > [ 106.812484] i915 0000:00:02.0: [drm:intel_dp_read_dpcd [i915]] DPCD: > > 12 14 04 80 00 00 01 00 00 00 00 00 00 00 00 > > [ 106.813266] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00400 AUX -> > > (ret= 12) 00 00 00 00 00 00 00 00 00 00 00 00 > > [ 106.813271] [drm:drm_dp_read_desc] DP sink: OUI 00-00-00 dev-ID HW- > > rev 0.0 SW-rev 0.0 quirks 0x0000 > > [ 106.813891] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00200 AUX -> > > (ret= 1) 01 > > [ 106.813940] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] > > source rates: 162000, 216000, 270000, 324000, 432000, 540000, 648000, > > 810000 > > [ 106.813974] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] > > sink rates: 162000, 270000, 540000 > > [ 106.814007] i915 0000:00:02.0: [drm:intel_dp_print_rates [i915]] > > common rates: 162000, 270000, 540000 > > [ 106.814550] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00021 AUX -> > > (ret= 1) 00 > > [ 106.814583] i915 0000:00:02.0: [drm:intel_dp_detect [i915]] > > [ENCODER:308:DDI F] MST support: port: yes, sink: no, modparam: yes > > > > ..... > > > > [ 106.927291] i915 0000:00:02.0: [drm:intel_dp_check_service_irq > > [i915]] PHY_PATTERN test requested > > [ 106.927897] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00219 AUX -> > > (ret= 1) 0a > > [ 106.928507] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00220 AUX -> > > (ret= 1) 04 > > [ 106.929143] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00248 AUX -> > > (ret= 1) 00 > > [ 106.929824] [drm:drm_dp_dpcd_read] AUX F/port F: 0x00202 AUX -> > > (ret= 6) 00 00 80 00 00 00 > > [ 106.929830] BUG: kernel NULL pointer dereference, address: > > 0000000000000578 > > [ 106.936809] #PF: supervisor read access in kernel mode > > [ 106.941953] #PF: error_code(0x0000) - not-present page > > [ 106.947082] PGD 0 P4D 0 > > [ 106.949643] Oops: 0000 [#1] PREEMPT SMP NOPTI > > [ 106.954010] CPU: 6 PID: 200 Comm: kworker/6:2 Not tainted 5.7.0-rc7- > > CI-CI_DRM_8566+ #5 > > [ 106.975251] Workqueue: events i915_hotplug_work_func [i915] > > [ 106.980887] RIP: 0010:intel_dp_process_phy_request+0x94/0x5a0 [i915] > > [ 106.987239] Code: 48 83 c4 20 5b 5d 41 5c 41 5d 41 5e 41 5f c3 48 8d > > 74 24 12 4c 89 f7 e8 3a 3e 00 00 49 8b 86 28 ff ff ff 49 8b 9e d8 fe ff > > ff <48> 63 80 78 05 00 00 8b 93 54 0d 00 00 48 8d ab e8 0e 00 00 48 89 > > [ 107.005890] RSP: 0018:ffffc9000046fb20 EFLAGS: 00010246 > > > > I plan to temporarily fix this issue by ignoreing scope request on long > > HPD, until we have modeset based implementation. > > > > > > } > > > > > > > > static void > > > > @@ -5497,20 +5507,28 @@ intel_dp_autotest_phy_ddi_enable(struct > > > > intel_dp *intel_dp, uint8_t lane_cnt) > > > > enum port port = intel_dig_port->base.port; > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > >base.base.crtc); > > > > enum pipe pipe = crtc->pipe; > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > dp_tp_ctl_value; > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > dp_tp_ctl_value, trans_ddi_sel_port; > > > > + i915_reg_t dp_tp_reg; > > > > + > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > + trans_ddi_sel_port = TRANS_DDI_SELECT_PORT(port); > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > + trans_ddi_sel_port = TGL_TRANS_DDI_SELECT_PORT(port); > > > > + } > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > TRANS_DDI_FUNC_CTL(pip > > > > e)); > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > - > > > > trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | > > > > - TGL_TRANS_DDI_SELECT_PORT(port); > > > > + trans_ddi_sel_port; > > > > trans_conf_value |= PIPECONF_ENABLE; > > > > dp_tp_ctl_value |= DP_TP_CTL_ENABLE; > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > trans_ddi_func_ctl_value); > > > > } > > > > @@ -5557,6 +5575,7 @@ static u8 > > > > intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) > > > > static void intel_dp_handle_test_request(struct intel_dp > > > > *intel_dp) > > > > { > > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > + struct drm_i915_private *dev_priv = i915; > > > > u8 response = DP_TEST_NAK; > > > > u8 request = 0; > > > > int status; > > > > @@ -5582,6 +5601,11 @@ static void > > > > intel_dp_handle_test_request(struct intel_dp *intel_dp) > > > > response = intel_dp_autotest_edid(intel_dp); > > > > break; > > > > case DP_TEST_LINK_PHY_TEST_PATTERN: > > > > + if (!IS_ELKHARTLAKE(dev_priv) || > > > > !IS_TIGERLAKE(dev_priv)) { > > > > + drm_dbg_kms(&i915->drm, > > > > + "PHY compliance for platform not > > > > supported\n"); > > > > + return; > > > > + } > > > > drm_dbg_kms(&i915->drm, "PHY_PATTERN test > > > > requested\n"); > > > > response = intel_dp_autotest_phy_pattern(intel_dp); > > > > break; > > > > -- > > > > 2.7.4 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx at lists.freedesktop.org > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From manasi.d.navare at intel.com Fri Jun 12 18:44:13 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 11:44:13 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612183637.GL6112@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> <20200612182542.GA7458@intel.com> <20200612183637.GL6112@intel.com> Message-ID: <20200612184413.GC7458@intel.com> On Fri, Jun 12, 2020 at 09:36:37PM +0300, Ville Syrj?l? wrote: > On Fri, Jun 12, 2020 at 11:25:42AM -0700, Manasi Navare wrote: > > On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > > > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > > > ++++++++++++++++++++++++++------- > > > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > > > intel_dp *intel_dp) > > > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > > > >base.base.crtc); > > > > > > enum pipe pipe = crtc->pipe; > > > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > dp_tp_ctl_value; > > > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > > > + enum port port = intel_dig_port->base.port; > > > > > > + i915_reg_t dp_tp_reg; > > > > > > + > > > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > > > + } > > > > > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > > > TRANS_DDI_FUNC_CTL(pip > > > > > > e)); > > > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > > > + trans_ddi_port_mask); > > > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > > > trans_ddi_func_ctl_value); > > > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > > > have different bugs than the norma modeset paths, so compliance > > > > > testing > > > > > this special code proves absolutely nothing about the normal modeset > > > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > > > just perform normal modesets. > > > > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > > > panic when we try to access to_intel_crtc(intel_dig_port- > > > > >base.base.crtc). > > > > > > Yeah, that's a legacy pointer which should no longer be used at all > > > with atomic drivers. I'm slowly trying to clear out all this legacy > > > cruft. The next step I had hoped to take was > > > https://patchwork.freedesktop.org/series/76993/ but then this > > > compliacnce stuff landed and threw another wrench into the works. > > > > We had several discussions on design of DP PHY compliance and the patches were on the M-L > > for quite some time without anyone giving feedback on the actual design of whether they should > > happen through modeset or directly from the PHY comp request short pulse. > > My first feedback was also that this should happen through a complete modeset where after we get > > PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. > > But honestly that was just a lot of overhead and > > The reason we decided to go with this ad hoc approach was that with PHY compliance request, > > nothing really changes in terms of link parameters so we do not need to go through > > a complete modeset request unlike link layer compliance where we need to do compute config > > all over again to do the link params computation. > > > > Every PHY comp request first sends a link layer comp request that does a full modeset > > and sets up the desired link rate/lane count. > > Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns > > and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. > > > > Now i think if we need to scale this to other platforms, can we add a per platform hook > > for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and > > reenables the already set link? > > > > We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly > > with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. > > > > Ville, Khaled ? > > You're just multiplying the amount of work and bugs we have > for every platform. > > And as said testing some special compliance paths proves > pretty much nothing about the real code paths. So the only > point of that code AFAICS it to tick some "we haz > compliance code?" checkbox in some random spreadsheet instead > of actually providing evidence that our real code works > correctly. > I thougt the whole point of PHY compliance is not to be able to see if the driver can do a modeset but just to confirm that driver is able to send the requested patterns out on already enabled link. So shouldnt doing this directly through the phy request handling on short pulse suffice? But if we want to insert this in the modeset what should be the flow: - AFter getting PHY request, store the requested PHY patterns, send a uevent - This will trigger a complete modeset, in this path for atomic check, see if PHY compliance test active then ignore recomputing the parameters and also in the commit tail, only disable the Pipeconf, dp_tp_ctl and send these patterns and then reenable? Manasi > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Fri Jun 12 19:01:19 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 22:01:19 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612184413.GC7458@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> <20200612182542.GA7458@intel.com> <20200612183637.GL6112@intel.com> <20200612184413.GC7458@intel.com> Message-ID: <20200612190119.GN6112@intel.com> On Fri, Jun 12, 2020 at 11:44:13AM -0700, Manasi Navare wrote: > On Fri, Jun 12, 2020 at 09:36:37PM +0300, Ville Syrj?l? wrote: > > On Fri, Jun 12, 2020 at 11:25:42AM -0700, Manasi Navare wrote: > > > On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > > > > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > > > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > > > > ++++++++++++++++++++++++++------- > > > > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > > > > intel_dp *intel_dp) > > > > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > > > > >base.base.crtc); > > > > > > > enum pipe pipe = crtc->pipe; > > > > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > dp_tp_ctl_value; > > > > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > > > > + enum port port = intel_dig_port->base.port; > > > > > > > + i915_reg_t dp_tp_reg; > > > > > > > + > > > > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > > > > + } > > > > > > > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > > > > TRANS_DDI_FUNC_CTL(pip > > > > > > > e)); > > > > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > > > > + trans_ddi_port_mask); > > > > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > > > > trans_ddi_func_ctl_value); > > > > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > > > > have different bugs than the norma modeset paths, so compliance > > > > > > testing > > > > > > this special code proves absolutely nothing about the normal modeset > > > > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > > > > just perform normal modesets. > > > > > > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > > > > panic when we try to access to_intel_crtc(intel_dig_port- > > > > > >base.base.crtc). > > > > > > > > Yeah, that's a legacy pointer which should no longer be used at all > > > > with atomic drivers. I'm slowly trying to clear out all this legacy > > > > cruft. The next step I had hoped to take was > > > > https://patchwork.freedesktop.org/series/76993/ but then this > > > > compliacnce stuff landed and threw another wrench into the works. > > > > > > We had several discussions on design of DP PHY compliance and the patches were on the M-L > > > for quite some time without anyone giving feedback on the actual design of whether they should > > > happen through modeset or directly from the PHY comp request short pulse. > > > My first feedback was also that this should happen through a complete modeset where after we get > > > PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. > > > But honestly that was just a lot of overhead and > > > The reason we decided to go with this ad hoc approach was that with PHY compliance request, > > > nothing really changes in terms of link parameters so we do not need to go through > > > a complete modeset request unlike link layer compliance where we need to do compute config > > > all over again to do the link params computation. > > > > > > Every PHY comp request first sends a link layer comp request that does a full modeset > > > and sets up the desired link rate/lane count. > > > Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns > > > and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. > > > > > > Now i think if we need to scale this to other platforms, can we add a per platform hook > > > for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and > > > reenables the already set link? > > > > > > We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly > > > with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. > > > > > > Ville, Khaled ? > > > > You're just multiplying the amount of work and bugs we have > > for every platform. > > > > And as said testing some special compliance paths proves > > pretty much nothing about the real code paths. So the only > > point of that code AFAICS it to tick some "we haz > > compliance code?" checkbox in some random spreadsheet instead > > of actually providing evidence that our real code works > > correctly. > > > > I thougt the whole point of PHY compliance is not to be able to see if the > driver can do a modeset but just to confirm that driver is able to send > the requested patterns out on already enabled link. So shouldnt doing this > directly through the phy request handling on short pulse suffice? You're not proving the driver proper can transmit the requested stuff, you're only proving the special compliance code can do that. I could easily break the normal codepaths and yet this magic compliance thing could still indicate that everything is hunky dory. > > But if we want to insert this in the modeset what should be the flow: > - AFter getting PHY request, store the requested PHY patterns, send a uevent You don't really need any uevent. We coukd do the stuff directly from the hotplug work. > - This will trigger a complete modeset, in this path for atomic check, see > if PHY compliance test active then ignore recomputing the parameters and > also in the commit tail, only disable the Pipeconf, dp_tp_ctl and send these patterns > and then reenable? We should just do a full modeset if possible. Randomly turning the pipe/etc. on/off without following the proper modeset sequence is dubious at best. -- Ville Syrj?l? Intel From manasi.d.navare at intel.com Fri Jun 12 19:12:25 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 12:12:25 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612190119.GN6112@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> <20200612182542.GA7458@intel.com> <20200612183637.GL6112@intel.com> <20200612184413.GC7458@intel.com> <20200612190119.GN6112@intel.com> Message-ID: <20200612191224.GA7611@intel.com> On Fri, Jun 12, 2020 at 10:01:19PM +0300, Ville Syrj?l? wrote: > On Fri, Jun 12, 2020 at 11:44:13AM -0700, Manasi Navare wrote: > > On Fri, Jun 12, 2020 at 09:36:37PM +0300, Ville Syrj?l? wrote: > > > On Fri, Jun 12, 2020 at 11:25:42AM -0700, Manasi Navare wrote: > > > > On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > > > > > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > > > > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > > > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > > > > > --- > > > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > > > > > ++++++++++++++++++++++++++------- > > > > > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > > > > > intel_dp *intel_dp) > > > > > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > > > > > >base.base.crtc); > > > > > > > > enum pipe pipe = crtc->pipe; > > > > > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > dp_tp_ctl_value; > > > > > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > > > > > + enum port port = intel_dig_port->base.port; > > > > > > > > + i915_reg_t dp_tp_reg; > > > > > > > > + > > > > > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > > > > > + } > > > > > > > > > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > > > > > TRANS_DDI_FUNC_CTL(pip > > > > > > > > e)); > > > > > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > > > > > + trans_ddi_port_mask); > > > > > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > > > > > trans_ddi_func_ctl_value); > > > > > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > > > > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > > > > > have different bugs than the norma modeset paths, so compliance > > > > > > > testing > > > > > > > this special code proves absolutely nothing about the normal modeset > > > > > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > > > > > just perform normal modesets. > > > > > > > > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > > > > > panic when we try to access to_intel_crtc(intel_dig_port- > > > > > > >base.base.crtc). > > > > > > > > > > Yeah, that's a legacy pointer which should no longer be used at all > > > > > with atomic drivers. I'm slowly trying to clear out all this legacy > > > > > cruft. The next step I had hoped to take was > > > > > https://patchwork.freedesktop.org/series/76993/ but then this > > > > > compliacnce stuff landed and threw another wrench into the works. > > > > > > > > We had several discussions on design of DP PHY compliance and the patches were on the M-L > > > > for quite some time without anyone giving feedback on the actual design of whether they should > > > > happen through modeset or directly from the PHY comp request short pulse. > > > > My first feedback was also that this should happen through a complete modeset where after we get > > > > PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. > > > > But honestly that was just a lot of overhead and > > > > The reason we decided to go with this ad hoc approach was that with PHY compliance request, > > > > nothing really changes in terms of link parameters so we do not need to go through > > > > a complete modeset request unlike link layer compliance where we need to do compute config > > > > all over again to do the link params computation. > > > > > > > > Every PHY comp request first sends a link layer comp request that does a full modeset > > > > and sets up the desired link rate/lane count. > > > > Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns > > > > and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. > > > > > > > > Now i think if we need to scale this to other platforms, can we add a per platform hook > > > > for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and > > > > reenables the already set link? > > > > > > > > We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly > > > > with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. > > > > > > > > Ville, Khaled ? > > > > > > You're just multiplying the amount of work and bugs we have > > > for every platform. > > > > > > And as said testing some special compliance paths proves > > > pretty much nothing about the real code paths. So the only > > > point of that code AFAICS it to tick some "we haz > > > compliance code?" checkbox in some random spreadsheet instead > > > of actually providing evidence that our real code works > > > correctly. > > > > > > > I thougt the whole point of PHY compliance is not to be able to see if the > > driver can do a modeset but just to confirm that driver is able to send > > the requested patterns out on already enabled link. So shouldnt doing this > > directly through the phy request handling on short pulse suffice? > > You're not proving the driver proper can transmit the requested stuff, > you're only proving the special compliance code can do that. I could > easily break the normal codepaths and yet this magic compliance thing > could still indicate that everything is hunky dory. > > > > > But if we want to insert this in the modeset what should be the flow: > > - AFter getting PHY request, store the requested PHY patterns, send a uevent > > You don't really need any uevent. We coukd do the stuff directly from > the hotplug work. > > > - This will trigger a complete modeset, in this path for atomic check, see > > if PHY compliance test active then ignore recomputing the parameters and > > also in the commit tail, only disable the Pipeconf, dp_tp_ctl and send these patterns > > and then reenable? > > We should just do a full modeset if possible. Randomly turning the > pipe/etc. on/off without following the proper modeset sequence is > dubious at best. how do we trigger a full modeset directly from the hotplug work just from within the kernel? We faced the same problem with link layer compliance and hence we decided to send the uevent there to trigger a ful modeset. How do you suggest we do otherwise? Manasi > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Fri Jun 12 19:21:31 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 12 Jun 2020 22:21:31 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612191224.GA7611@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> <20200612182542.GA7458@intel.com> <20200612183637.GL6112@intel.com> <20200612184413.GC7458@intel.com> <20200612190119.GN6112@intel.com> <20200612191224.GA7611@intel.com> Message-ID: <20200612192131.GO6112@intel.com> On Fri, Jun 12, 2020 at 12:12:25PM -0700, Manasi Navare wrote: > On Fri, Jun 12, 2020 at 10:01:19PM +0300, Ville Syrj?l? wrote: > > On Fri, Jun 12, 2020 at 11:44:13AM -0700, Manasi Navare wrote: > > > On Fri, Jun 12, 2020 at 09:36:37PM +0300, Ville Syrj?l? wrote: > > > > On Fri, Jun 12, 2020 at 11:25:42AM -0700, Manasi Navare wrote: > > > > > On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > > > > > > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > > > > > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > > > > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > > > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > > > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > > > > > > --- > > > > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > > > > > > ++++++++++++++++++++++++++------- > > > > > > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > > > > > > intel_dp *intel_dp) > > > > > > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > > > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > > > > > > >base.base.crtc); > > > > > > > > > enum pipe pipe = crtc->pipe; > > > > > > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > > dp_tp_ctl_value; > > > > > > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > > > > > > + enum port port = intel_dig_port->base.port; > > > > > > > > > + i915_reg_t dp_tp_reg; > > > > > > > > > + > > > > > > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > > > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > > > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > > > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > > > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > > > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > > > > > > + } > > > > > > > > > > > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > > > > > > TRANS_DDI_FUNC_CTL(pip > > > > > > > > > e)); > > > > > > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > > > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > > > > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > > > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > > > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > > > > > > + trans_ddi_port_mask); > > > > > > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > > > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > > > > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > > > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > > > > > > trans_ddi_func_ctl_value); > > > > > > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > > > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > > > > > > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > > > > > > have different bugs than the norma modeset paths, so compliance > > > > > > > > testing > > > > > > > > this special code proves absolutely nothing about the normal modeset > > > > > > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > > > > > > just perform normal modesets. > > > > > > > > > > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > > > > > > panic when we try to access to_intel_crtc(intel_dig_port- > > > > > > > >base.base.crtc). > > > > > > > > > > > > Yeah, that's a legacy pointer which should no longer be used at all > > > > > > with atomic drivers. I'm slowly trying to clear out all this legacy > > > > > > cruft. The next step I had hoped to take was > > > > > > https://patchwork.freedesktop.org/series/76993/ but then this > > > > > > compliacnce stuff landed and threw another wrench into the works. > > > > > > > > > > We had several discussions on design of DP PHY compliance and the patches were on the M-L > > > > > for quite some time without anyone giving feedback on the actual design of whether they should > > > > > happen through modeset or directly from the PHY comp request short pulse. > > > > > My first feedback was also that this should happen through a complete modeset where after we get > > > > > PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. > > > > > But honestly that was just a lot of overhead and > > > > > The reason we decided to go with this ad hoc approach was that with PHY compliance request, > > > > > nothing really changes in terms of link parameters so we do not need to go through > > > > > a complete modeset request unlike link layer compliance where we need to do compute config > > > > > all over again to do the link params computation. > > > > > > > > > > Every PHY comp request first sends a link layer comp request that does a full modeset > > > > > and sets up the desired link rate/lane count. > > > > > Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns > > > > > and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. > > > > > > > > > > Now i think if we need to scale this to other platforms, can we add a per platform hook > > > > > for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and > > > > > reenables the already set link? > > > > > > > > > > We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly > > > > > with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. > > > > > > > > > > Ville, Khaled ? > > > > > > > > You're just multiplying the amount of work and bugs we have > > > > for every platform. > > > > > > > > And as said testing some special compliance paths proves > > > > pretty much nothing about the real code paths. So the only > > > > point of that code AFAICS it to tick some "we haz > > > > compliance code?" checkbox in some random spreadsheet instead > > > > of actually providing evidence that our real code works > > > > correctly. > > > > > > > > > > I thougt the whole point of PHY compliance is not to be able to see if the > > > driver can do a modeset but just to confirm that driver is able to send > > > the requested patterns out on already enabled link. So shouldnt doing this > > > directly through the phy request handling on short pulse suffice? > > > > You're not proving the driver proper can transmit the requested stuff, > > you're only proving the special compliance code can do that. I could > > easily break the normal codepaths and yet this magic compliance thing > > could still indicate that everything is hunky dory. > > > > > > > > > But if we want to insert this in the modeset what should be the flow: > > > - AFter getting PHY request, store the requested PHY patterns, send a uevent > > > > You don't really need any uevent. We coukd do the stuff directly from > > the hotplug work. > > > > > - This will trigger a complete modeset, in this path for atomic check, see > > > if PHY compliance test active then ignore recomputing the parameters and > > > also in the commit tail, only disable the Pipeconf, dp_tp_ctl and send these patterns > > > and then reenable? > > > > We should just do a full modeset if possible. Randomly turning the > > pipe/etc. on/off without following the proper modeset sequence is > > dubious at best. > > how do we trigger a full modeset directly from the hotplug work just from > within the kernel? We faced the same problem with link layer compliance > and hence we decided to send the uevent there to trigger a ful modeset. The full modeset via userspace route is only needed if the resolution needs to be changed since that's something userspace gets to decide. If the current mode is still OK we can directly trigger the modeset from the kernel. Not sure if we do or not. We do a full modeset for HDMI when the sink forgets that scrambling was supposed to be on, and I'm a bit tempted to do the same for plain old DP retraining to get rid of the special case code for that (and to actually follow the modeset seqeunce properly when doing retraining). -- Ville Syrj?l? Intel From manasi.d.navare at intel.com Fri Jun 12 19:38:59 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 12:38:59 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612192131.GO6112@intel.com> References: <1591247028-5868-1-git-send-email-vidya.srinivas@intel.com> <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> <20200612182542.GA7458@intel.com> <20200612183637.GL6112@intel.com> <20200612184413.GC7458@intel.com> <20200612190119.GN6112@intel.com> <20200612191224.GA7611@intel.com> <20200612192131.GO6112@intel.com> Message-ID: <20200612193859.GB7611@intel.com> On Fri, Jun 12, 2020 at 10:21:31PM +0300, Ville Syrj?l? wrote: > On Fri, Jun 12, 2020 at 12:12:25PM -0700, Manasi Navare wrote: > > On Fri, Jun 12, 2020 at 10:01:19PM +0300, Ville Syrj?l? wrote: > > > On Fri, Jun 12, 2020 at 11:44:13AM -0700, Manasi Navare wrote: > > > > On Fri, Jun 12, 2020 at 09:36:37PM +0300, Ville Syrj?l? wrote: > > > > > On Fri, Jun 12, 2020 at 11:25:42AM -0700, Manasi Navare wrote: > > > > > > On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > > > > > > > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > > > > > > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > > > > > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > > > > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > > > > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > > > > > > > --- > > > > > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > > > > > > > ++++++++++++++++++++++++++------- > > > > > > > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > > > > > > > intel_dp *intel_dp) > > > > > > > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > > > > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > > > > > > > >base.base.crtc); > > > > > > > > > > enum pipe pipe = crtc->pipe; > > > > > > > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > > > dp_tp_ctl_value; > > > > > > > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > > > > > > > + enum port port = intel_dig_port->base.port; > > > > > > > > > > + i915_reg_t dp_tp_reg; > > > > > > > > > > + > > > > > > > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > > > > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > > > > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > > > > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > > > > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > > > > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > > > > > > > + } > > > > > > > > > > > > > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > > > > > > > TRANS_DDI_FUNC_CTL(pip > > > > > > > > > > e)); > > > > > > > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > > > > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > > > > > > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > > > > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > > > > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > > > > > > > + trans_ddi_port_mask); > > > > > > > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > > > > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > > > > > > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > > > > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > > > > > > > trans_ddi_func_ctl_value); > > > > > > > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > > > > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > > > > > > > > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > > > > > > > have different bugs than the norma modeset paths, so compliance > > > > > > > > > testing > > > > > > > > > this special code proves absolutely nothing about the normal modeset > > > > > > > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > > > > > > > just perform normal modesets. > > > > > > > > > > > > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > > > > > > > panic when we try to access to_intel_crtc(intel_dig_port- > > > > > > > > >base.base.crtc). > > > > > > > > > > > > > > Yeah, that's a legacy pointer which should no longer be used at all > > > > > > > with atomic drivers. I'm slowly trying to clear out all this legacy > > > > > > > cruft. The next step I had hoped to take was > > > > > > > https://patchwork.freedesktop.org/series/76993/ but then this > > > > > > > compliacnce stuff landed and threw another wrench into the works. > > > > > > > > > > > > We had several discussions on design of DP PHY compliance and the patches were on the M-L > > > > > > for quite some time without anyone giving feedback on the actual design of whether they should > > > > > > happen through modeset or directly from the PHY comp request short pulse. > > > > > > My first feedback was also that this should happen through a complete modeset where after we get > > > > > > PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. > > > > > > But honestly that was just a lot of overhead and > > > > > > The reason we decided to go with this ad hoc approach was that with PHY compliance request, > > > > > > nothing really changes in terms of link parameters so we do not need to go through > > > > > > a complete modeset request unlike link layer compliance where we need to do compute config > > > > > > all over again to do the link params computation. > > > > > > > > > > > > Every PHY comp request first sends a link layer comp request that does a full modeset > > > > > > and sets up the desired link rate/lane count. > > > > > > Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns > > > > > > and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. > > > > > > > > > > > > Now i think if we need to scale this to other platforms, can we add a per platform hook > > > > > > for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and > > > > > > reenables the already set link? > > > > > > > > > > > > We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly > > > > > > with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. > > > > > > > > > > > > Ville, Khaled ? > > > > > > > > > > You're just multiplying the amount of work and bugs we have > > > > > for every platform. > > > > > > > > > > And as said testing some special compliance paths proves > > > > > pretty much nothing about the real code paths. So the only > > > > > point of that code AFAICS it to tick some "we haz > > > > > compliance code?" checkbox in some random spreadsheet instead > > > > > of actually providing evidence that our real code works > > > > > correctly. > > > > > > > > > > > > > I thougt the whole point of PHY compliance is not to be able to see if the > > > > driver can do a modeset but just to confirm that driver is able to send > > > > the requested patterns out on already enabled link. So shouldnt doing this > > > > directly through the phy request handling on short pulse suffice? > > > > > > You're not proving the driver proper can transmit the requested stuff, > > > you're only proving the special compliance code can do that. I could > > > easily break the normal codepaths and yet this magic compliance thing > > > could still indicate that everything is hunky dory. > > > > > > > > > > > > > But if we want to insert this in the modeset what should be the flow: > > > > - AFter getting PHY request, store the requested PHY patterns, send a uevent > > > > > > You don't really need any uevent. We coukd do the stuff directly from > > > the hotplug work. > > > > > > > - This will trigger a complete modeset, in this path for atomic check, see > > > > if PHY compliance test active then ignore recomputing the parameters and > > > > also in the commit tail, only disable the Pipeconf, dp_tp_ctl and send these patterns > > > > and then reenable? > > > > > > We should just do a full modeset if possible. Randomly turning the > > > pipe/etc. on/off without following the proper modeset sequence is > > > dubious at best. > > > > how do we trigger a full modeset directly from the hotplug work just from > > within the kernel? We faced the same problem with link layer compliance > > and hence we decided to send the uevent there to trigger a ful modeset. > > The full modeset via userspace route is only needed if the resolution > needs to be changed since that's something userspace gets to decide. > If the current mode is still OK we can directly trigger the modeset > from the kernel. Not sure if we do or not. > > We do a full modeset for HDMI when the sink forgets that scrambling > was supposed to be on, and I'm a bit tempted to do the same for > plain old DP retraining to get rid of the special case code for > that (and to actually follow the modeset seqeunce properly when > doing retraining). > For retraining we dont have any special case code right, we just fallback and then send uevent. Oh but do you mean like getting rid of setting the link status and forcing a full modeset etc? So for PHY compliance, we do something similar to calling modeset_pipe() from intel_hdmi_reset_link()? So call this modeset_pipe from intel_dp_autotest_phy_pattern() after storing the requested phy patterns in a compliance struct? Manasi > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Fri Jun 12 20:07:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 20:07:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/icl+=3A_Fix_hotplug_interrupt_disabling_after_storm_detec?= =?utf-8?q?tion?= In-Reply-To: <20200612121731.19596-1-imre.deak@intel.com> References: <20200612121731.19596-1-imre.deak@intel.com> Message-ID: <159199243785.21335.9177201955553895472@emeril.freedesktop.org> == Series Details == Series: drm/i915/icl+: Fix hotplug interrupt disabling after storm detection URL : https://patchwork.freedesktop.org/series/78258/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17937 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html Known issues ------------ Here are the changes found in Patchwork_17937 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][3] ([i915#95]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][7] ([i915#1993]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17937 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17937: a09f4bc8ddb9cfad0f18bdaccada93f9e98d5c54 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a09f4bc8ddb9 drm/i915/icl+: Fix hotplug interrupt disabling after storm detection == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html From lakshminarayana.vudum at intel.com Fri Jun 12 20:13:44 2020 From: lakshminarayana.vudum at intel.com (Vudum, Lakshminarayana) Date: Fri, 12 Jun 2020 20:13:44 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/icl+=3A_Fix_hotplug_interrupt_disabling_after_storm_detec?= =?utf-8?q?tion?= In-Reply-To: <20200612132020.GC15242@ideak-desk.fi.intel.com> References: <20200612121731.19596-1-imre.deak@intel.com> <159196705993.21336.14083495618624409936@emeril.freedesktop.org> <20200612132020.GC15242@ideak-desk.fi.intel.com> Message-ID: <b2d4a626e2f046b8863277a29655e08f@intel.com> Filed https://gitlab.freedesktop.org/drm/intel/-/issues/2029 and re-reported. -----Original Message----- From: Imre Deak <imre.deak at intel.com> Sent: Friday, June 12, 2020 4:20 PM To: intel-gfx at lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum at intel.com>; Sarvela, Tomi P <tomi.p.sarvela at intel.com>; Latvala, Petri <petri.latvala at intel.com> Subject: Re: ? Fi.CI.BAT: failure for drm/i915/icl+: Fix hotplug interrupt disabling after storm detection On Fri, Jun 12, 2020 at 01:04:19PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/icl+: Fix hotplug interrupt disabling after storm detection > URL : https://patchwork.freedesktop.org/series/78258/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17937 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17937 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17937, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17937: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at runner@aborted: > - fi-bdw-5557u: NOTRUN -> [FAIL][1] > [1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-bdw-5557u/ > igt at runner@aborted.html This is on an unrelated platform. It looks like a network problem after resuming: [149.557805] [117/171] (880s left) kms_pipe_crc_basic (suspend-read-crc-pipe-a) Starting subtest: suspend-read-crc-pipe-A Subtest suspend-read-crc-pipe-A: SUCCESS (2.860s) [191.138997] Aborting: Ping host did not respond to ping, network down [191.140340] Closing watchdogs So jenkins timing out after 50 seconds, even though the machine is still up for 5 minutes after suspend-read-crc-pipe-A completes. The network connection seems to be up as well: <7>[ 134.716964] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A ... <7>[ 137.578228] [IGT] kms_pipe_crc_basic: exiting, ret=0 <6>[ 137.588883] Console: switching to colour frame buffer device 240x67 <6>[ 142.597964] e1000e 0000:00:19.0 enp0s25: NIC Link is Up 10 Mbps Full Duplex, Flow Control: None <6>[ 439.818733] kworker/dying (178) used greatest stack depth: 11424 bytes left > Known issues > ------------ > > Here are the changes found in Patchwork_17937 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: > - fi-icl-u2: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt > @kms_cursor_legacy at basic-flip-after-cursor-legacy.html > > > #### Possible fixes #### > > * igt at i915_pm_backlight@basic-brightness: > - fi-whl-u: [DMESG-WARN][4] ([i915#95]) -> [PASS][5] > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html > [5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-whl-u/igt@ > i915_pm_backlight at basic-brightness.html > > * igt at i915_pm_rpm@module-reload: > - fi-glk-dsi: [DMESG-WARN][6] ([i915#1982]) -> [PASS][7] > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html > [7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-glk-dsi/ig > t at i915_pm_rpm@module-reload.html > > * igt at i915_selftest@live at execlists: > - fi-icl-y: [DMESG-FAIL][8] ([i915#1993]) -> [PASS][9] > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-y/igt@ > i915_selftest at live@execlists.html > > * igt at kms_busy@basic at flip: > - fi-kbl-x1275: [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][11] > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/ > igt at kms_busy@basic at flip.html > > * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-icl-u2: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > - fi-bsw-kefka: [DMESG-WARN][14] ([i915#1982]) -> [PASS][15] > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-bsw-kefka/ > igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: > - fi-icl-guc: [DMESG-WARN][16] ([i915#1982]) -> [PASS][17] > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html > [17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-icl-guc/ig > t at kms_cursor_legacy@basic-flip-after-cursor-legacy.html > > > #### Warnings #### > > * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: > - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][19] ([i915#62] / [i915#92]) +4 similar issues > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html > [19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/ > igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html > > * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: > - fi-kbl-x1275: [DMESG-WARN][20] ([i915#62] / [i915#92]) -> [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html > [21]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/fi-kbl-x1275/ > igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html > > > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (49 -> 43) > ------------------------------ > > Additional (1): fi-tgl-u2 > Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * Linux: CI_DRM_8621 -> Patchwork_17937 > > CI-20190529: 20190529 > CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17937: a09f4bc8ddb9cfad0f18bdaccada93f9e98d5c54 @ > git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > a09f4bc8ddb9 drm/i915/icl+: Fix hotplug interrupt disabling after > storm detection > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From lkp at intel.com Fri Jun 12 20:32:39 2020 From: lkp at intel.com (kernel test robot) Date: Sat, 13 Jun 2020 04:32:39 +0800 Subject: [Intel-gfx] [PATCH 6/8] drm/vmwgfx: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-6-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-6-daniel.vetter@ffwll.ch> Message-ID: <202006130424.SOvVOxbj%lkp@intel.com> Hi Daniel, I love your patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.7 next-20200612] [cannot apply to drm/drm-next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/drm-atomic-helper-reset-vblank-on-crtc-reset/20200613-000414 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-allyesconfig (attached as .config) compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 3b43f006294971b8049d4807110032169780e5b8) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): >> drivers/gpu/drm/vmwgfx/vmwgfx_kms.c:632:40: error: use of undeclared identifier 'state' __drm_atomic_helper_crtc_reset(crtc, &state->base); ^ 1 error generated. vim +/state +632 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 604 605 606 /** 607 * vmw_du_crtc_reset - creates a blank vmw crtc state 608 * @crtc: DRM crtc 609 * 610 * Resets the atomic state for @crtc by freeing the state pointer (which 611 * might be NULL, e.g. at driver load time) and allocating a new empty state 612 * object. 613 */ 614 void vmw_du_crtc_reset(struct drm_crtc *crtc) 615 { 616 struct vmw_crtc_state *vcs; 617 618 619 if (crtc->state) { 620 __drm_atomic_helper_crtc_destroy_state(crtc->state); 621 622 kfree(vmw_crtc_state_to_vcs(crtc->state)); 623 } 624 625 vcs = kzalloc(sizeof(*vcs), GFP_KERNEL); 626 627 if (!vcs) { 628 DRM_ERROR("Cannot allocate vmw_crtc_state\n"); 629 return; 630 } 631 > 632 __drm_atomic_helper_crtc_reset(crtc, &state->base); 633 } 634 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 73519 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200613/002a396f/attachment-0001.gz> From jose.souza at intel.com Fri Jun 12 20:33:31 2020 From: jose.souza at intel.com (Souza, Jose) Date: Fri, 12 Jun 2020 20:33:31 +0000 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch In-Reply-To: <20200612163029.GK6112@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-5-jose.souza@intel.com> <20200612163029.GK6112@intel.com> Message-ID: <ee0340f8ea128ed2caa4a6882ded6cb28bf0d8d9.camel@intel.com> On Fri, 2020-06-12 at 19:30 +0300, Ville Syrj?l? wrote: > On Tue, May 26, 2020 at 03:14:46PM -0700, Jos? Roberto de Souza wrote: > > All GEN12 platforms supports PSR2 selective fetch but not all GEN12 > > platforms supports PSR2 hardware tracking(aka RKL). > > > > This feature consists in software program registers with the damaged > > area of each plane this way hardware will only fetch from memory those > > areas and sent the PSR2 selective update blocks to panel, saving even > > more power but to it actually happen userspace needs to send the > > damaged areas otherwise it will still fetch the whole plane as > > fallback. > > As today Gnome3 do not send damaged areas and the only compositor that > > I'm aware that sets the damaged areas is Weston. > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > > > So here implementing page flip part, it is still completely missing > > frontbuffer modifications, that is why the enable_psr2_sel_fetch > > parameter was added. > > > > The plan is to switch all GEN12 platforms to selective fetch when > > ready, it will also depend in add some tests sending damaged areas. > > I have a hacked version of kms_psr2_su with 3 planes that I can > > cleanup and send in a few days(99% of PSR2 selective fetch changes was > > done during my free time while bored during quarantine rainy days). > > > > BSpec: 55229 > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 5 + > > .../drm/i915/display/intel_display_debugfs.c | 3 + > > .../drm/i915/display/intel_display_types.h | 10 + > > drivers/gpu/drm/i915/display/intel_psr.c | 329 +++++++++++++++++- > > drivers/gpu/drm/i915/display/intel_psr.h | 10 + > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 + > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > drivers/gpu/drm/i915/i915_params.c | 5 + > > drivers/gpu/drm/i915/i915_params.h | 1 + > > 9 files changed, 352 insertions(+), 15 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index b69878334040..984809208c29 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -11729,6 +11729,8 @@ static void i9xx_update_cursor(struct intel_plane *plane, > > if (INTEL_GEN(dev_priv) >= 9) > > skl_write_cursor_wm(plane, crtc_state); > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state); > > + > > if (plane->cursor.base != base || > > plane->cursor.size != fbc_ctl || > > plane->cursor.cntl != cntl) { > > @@ -15115,6 +15117,8 @@ static void commit_pipe_config(struct intel_atomic_state *state, > > > > if (new_crtc_state->update_pipe) > > intel_pipe_fastset(old_crtc_state, new_crtc_state); > > + > > + intel_psr2_program_trans_man_trk_ctl(new_crtc_state); > > } > > > > if (dev_priv->display.atomic_update_watermarks) > > @@ -15156,6 +15160,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > intel_color_load_luts(new_crtc_state); > > > > intel_pre_plane_update(state, crtc); > > + intel_psr2_sel_fetch_update(state, crtc); > > > > if (new_crtc_state->update_pipe) > > intel_encoders_update_pipe(state, crtc); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > index 70525623bcdf..0f600974462b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > > su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); > > seq_printf(m, "%d\t%d\n", frame, su_blocks); > > } > > + > > + seq_printf(m, "PSR2 selective fetch: %s\n", > > + enableddisabled(psr->psr2_sel_fetch_enabled)); > > } > > > > unlock: > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 30b2767578dc..b77a512e5362 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -586,6 +586,13 @@ struct intel_plane_state { > > u32 planar_slave; > > > > struct drm_intel_sprite_colorkey ckey; > > + > > + struct { > > + u32 ctl; > > + u32 pos; > > + u32 offset; > > + u32 size; > > + } psr2_sel_fetch; > > Do we really need all that here? We don't store them for the normal > plane updates either. For ctl we do, anyways could be removed if we store overlapping damage are in here so intel_psr2_program_plane_sel_fetch() would incorporate intel_psr2_plane_sel_fetch_calc() code, both looks good to me. > > > }; > > > > struct intel_initial_plane_config { > > @@ -931,6 +938,7 @@ struct intel_crtc_state { > > > > bool has_psr; > > bool has_psr2; > > + bool enable_psr2_sel_fetch; > > u32 dc3co_exitline; > > > > /* > > @@ -1070,6 +1078,8 @@ struct intel_crtc_state { > > > > /* For DSB related info */ > > struct intel_dsb *dsb; > > + > > + u32 psr2_sw_man_track_ctl; > > }; > > > > enum intel_pipe_crc_source { > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > > index 0c86e9e341a2..bc2a2e64fe2a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -518,6 +518,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > > else > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > > + intel_de_write(dev_priv, > > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), > > + PSR2_MAN_TRK_CTL_ENABLE); > > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > > + intel_de_write(dev_priv, > > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); > > + > > /* > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > > * recommending keep this bit unset while PSR2 is enabled. > > @@ -628,6 +636,38 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, > > crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; > > } > > > > +static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, > > + struct intel_crtc_state *crtc_state) > > +{ > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > + struct intel_plane_state *plane_state; > > + struct intel_plane *plane; > > + int i; > > + > > + if (!i915_modparams.enable_psr2_sel_fetch) { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR2 sel fetch not enabled, disabled by parameter\n"); > > + return false; > > + } > > + > > + if (crtc_state->uapi.async_flip) { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR2 sel fetch not enabled, async flip enabled\n"); > > + return false; > > + } > > Not supported anyway. > > > + > > + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { > > + if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR2 sel fetch not enabled, plane rotated\n"); > > + return false; > > + } > > + } > > + > > + return crtc_state->enable_psr2_sel_fetch = true; > > +} > > + > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > struct intel_crtc_state *crtc_state) > > { > > @@ -697,22 +737,17 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > return false; > > } > > > > - /* > > - * Some platforms lack PSR2 HW tracking and instead require manual > > - * tracking by software. In this case, the driver is required to track > > - * the areas that need updates and program hardware to send selective > > - * updates. > > - * > > - * So until the software tracking is implemented, PSR2 needs to be > > - * disabled for platforms without PSR2 HW tracking. > > - */ > > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > > - drm_dbg_kms(&dev_priv->drm, > > - "No PSR2 HW tracking in the platform\n"); > > - return false; > > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > > + if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > > + !HAS_PSR_HW_TRACKING(dev_priv)) { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); > > + return false; > > + } > > } > > > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > > + if (!crtc_state->enable_psr2_sel_fetch && > > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { > > drm_dbg_kms(&dev_priv->drm, > > "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", > > crtc_hdisplay, crtc_vdisplay, > > @@ -863,6 +898,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, > > val |= EXITLINE_ENABLE; > > intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); > > } > > + > > + if (HAS_PSR_HW_TRACKING(dev_priv)) > > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, > > + dev_priv->psr.psr2_sel_fetch_enabled ? > > + IGNORE_PSR2_HW_TRACKING : 0); > > } > > > > static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > > @@ -884,7 +924,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > > /* DC5/DC6 requires at least 6 idle frames */ > > val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > > dev_priv->psr.dc3co_exit_delay = val; > > - > > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; > > /* > > * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR > > * will still keep the error set even after the reset done in the > > @@ -1080,6 +1120,265 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) > > intel_psr_exit(dev_priv); > > } > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, > > + const struct intel_crtc_state *crtc_state, > > + const struct intel_plane_state *plane_state) > > +{ > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); > > + enum pipe pipe = plane->pipe; > > + > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > + !plane_state || > > + !crtc_state->enable_psr2_sel_fetch) > > + return; > > + > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), > > + plane_state->psr2_sel_fetch.ctl); > > + if (!plane_state->psr2_sel_fetch.ctl || plane->id == PLANE_CURSOR) > > + return; > > + > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), > > + plane_state->psr2_sel_fetch.pos); > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > > + plane_state->psr2_sel_fetch.offset); > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), > > + plane_state->psr2_sel_fetch.size); > > +} > > + > > +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) > > +{ > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > + struct i915_psr *psr = &dev_priv->psr; > > + > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > + !crtc_state->enable_psr2_sel_fetch) > > + return; > > + > > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), > > + crtc_state->psr2_sw_man_track_ctl); > > +} > > + > > +static void intel_psr2_plane_sel_fetch_calc(struct intel_plane_state *plane_state, > > + struct drm_rect *clip) > > +{ > > + int color_plane = plane_state->planar_linked_plane && !plane_state->planar_slave; > > + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); > > + u32 val; > > + > > + if (plane->id == PLANE_CURSOR) > > + return; > > + > > + val = (plane_state->color_plane[color_plane].y + clip->y1) << 16; > > + val |= plane_state->color_plane[color_plane].x; > > + plane_state->psr2_sel_fetch.offset = val; > > + > > + val = (clip->y1 + plane_state->uapi.crtc_y) << 16; > > + val |= plane_state->uapi.crtc_x; > > + plane_state->psr2_sel_fetch.pos = val; > > + > > + /* Sizes are 0 based */ > > + val = (clip->y2 - clip->y1 - 1) << 16; > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; > > + plane_state->psr2_sel_fetch.size = val; > > +} > > + > > +static void intel_psr2_trans_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, > > + struct drm_rect *clip, > > + bool full_update) > > +{ > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE; > > + > > + if (full_update) { > > + val |= PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME; > > + goto exit; > > + } > > + > > + if (clip->y1 == -1) > > + goto exit; > > + > > + val |= PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE; > > + val |= PSR2_MAN_TRK_CTL_REGION_START_ADDR(clip->y1 / 4 + 1); > > + val |= PSR2_MAN_TRK_CTL_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1); > > +exit: > > + crtc_state->psr2_sw_man_track_ctl = val; > > +} > > + > > +static void intel_psr2_plane_sel_fetch_ctl_calc(struct intel_plane *plane, > > + struct intel_plane_state *plane_state, > > + bool enable) > > +{ > > + if (!enable) > > + plane_state->psr2_sel_fetch.ctl = 0; > > + else if (plane->id == PLANE_CURSOR) > > + plane_state->psr2_sel_fetch.ctl = plane->cursor.cntl; > > + else > > + plane_state->psr2_sel_fetch.ctl = plane_state->ctl; > > +} > > + > > +static void clip_update(struct drm_rect *overlap_damage_area, > > + struct drm_rect *damage_area) > > +{ > > + if (overlap_damage_area->y1 == -1) { > > + overlap_damage_area->y1 = damage_area->y1; > > + overlap_damage_area->y2 = damage_area->y2; > > + return; > > + } > > + > > + if (damage_area->y1 < overlap_damage_area->y1) > > + overlap_damage_area->y1 = damage_area->y1; > > + > > + if (damage_area->y2 > overlap_damage_area->y2) > > + overlap_damage_area->y2 = damage_area->y2; > > +} > > + > > +/* Update plane damage area if planes above moved or have alpha */ > > +static void intel_psr2_pipe_dirty_areas_set(struct intel_plane_state *plane_state, > > + struct intel_plane *plane, > > + const struct drm_rect *pipe_dirty_areas, > > + struct drm_rect *plane_clip) > > +{ > > + enum plane_id i; > > + > > + for (i = PLANE_CURSOR; i > plane->id; i--) { > > + int j; > > + > > + for (j = 0; j < 2; j++) { > > + struct drm_rect r = pipe_dirty_areas[i * 2 + j]; > > + > > + if (!drm_rect_width(&r)) > > + continue; > > + if (!drm_rect_intersect(&r, &plane_state->uapi.dst)) > > + continue; > > + > > + r.y1 -= plane_state->uapi.crtc_y; > > + r.y2 -= plane_state->uapi.crtc_y; > > + clip_update(plane_clip, &r); > > + } > > + } > > +} > > + > > +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > > + struct intel_crtc *crtc) > > +{ > > + struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); > > + struct intel_plane_state *new_plane_state, *old_plane_state; > > + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = {}; > > + struct drm_rect pipe_clip = { .y1 = -1 }; > > + struct intel_plane *plane; > > + bool full_update = false; > > + int i; > > + > > + if (!crtc_state->enable_psr2_sel_fetch) > > + return; > > + > > + /* > > + * Load all the pipes areas where there is a plane with alpha or a plane > > + * that moved or plane that the visibility changed in those > > + * cases planes bellow it will need to be fetched in those intersection > > + * areas even if they are not damaged in those areas. > > + */ > > + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, > > + new_plane_state, i) { > > + bool alpha, flip, dirty; > > + > > + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) > > + continue; > > + > > + alpha = new_plane_state->uapi.alpha != U16_MAX; > > + alpha |= old_plane_state->uapi.alpha != U16_MAX; > > + flip = new_plane_state->uapi.fb != old_plane_state->uapi.fb; > > + dirty = alpha && flip; > > + dirty |= !drm_rect_equals(&new_plane_state->uapi.dst, > > + &old_plane_state->uapi.dst); > > + dirty |= new_plane_state->uapi.visible != > > + old_plane_state->uapi.visible; > > + if (!dirty) > > + continue; > > + > > + if (old_plane_state->uapi.visible) > > + pipe_dirty_areas[plane->id * 2] = old_plane_state->uapi.dst; > > + if (new_plane_state->uapi.visible) > > + pipe_dirty_areas[plane->id * 2 + 1] = new_plane_state->uapi.dst; > > + } > > + > > + /* > > + * Iterate over all planes, compute the damaged clip area also including > > + * the pipe_dirty_areas, compute plane registers and update pipe damaged > > + * area > > + */ > > + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, > > + new_plane_state, i) { > > + struct drm_rect plane_clip = { .y1 = -1 }; > > + struct drm_mode_rect *clips; > > + u32 num_clips; > > + int j; > > + > > + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) > > + continue; > > + > > + /* > > + * TODO: Not clear how to handle planes with negative position, > > + * also planes are not updated if they have a negative X > > + * position so for now doing a full update in this cases > > + */ > > + if (new_plane_state->uapi.crtc_y < 0 || > > + new_plane_state->uapi.crtc_x < 0) { > > + full_update = true; > > + break; > > + } > > + > > + intel_psr2_plane_sel_fetch_ctl_calc(plane, new_plane_state, > > + new_plane_state->uapi.visible); > > + if (!new_plane_state->uapi.visible) > > + continue; > > + > > + clips = drm_plane_get_damage_clips(&new_plane_state->uapi); > > + num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); > > + > > + /* > > + * If plane moved mark the whole plane area as damaged so it > > + * can be complete draw in the new position > > + */ > > + if (!drm_rect_equals(&new_plane_state->uapi.dst, > > + &old_plane_state->uapi.dst)) { > > + num_clips = 0; > > + plane_clip.y1 = new_plane_state->uapi.src.y1 >> 16; > > + plane_clip.y2 = new_plane_state->uapi.src.y2 >> 16; > > + } else if (!num_clips) { > > + /* > > + * If plane don't have damage areas but the framebuffer > > + * changed mark the whole plane as damaged > > + */ > > + if (new_plane_state->uapi.fb == old_plane_state->uapi.fb) > > + continue; > > + > > + plane_clip.y1 = new_plane_state->uapi.src.y1 >> 16; > > + plane_clip.y2 = new_plane_state->uapi.src.y2 >> 16; > > + } > > + > > + for (j = 0; j < num_clips; j++) { > > + struct drm_rect damage_area; > > + > > + damage_area.x1 = clips[j].x1; > > + damage_area.x2 = clips[j].x2; > > + damage_area.y1 = clips[j].y1; > > + damage_area.y2 = clips[j].y2; > > + clip_update(&plane_clip, &damage_area); > > + } > > + > > + intel_psr2_pipe_dirty_areas_set(new_plane_state, plane, > > + pipe_dirty_areas, &plane_clip); > > + intel_psr2_plane_sel_fetch_calc(new_plane_state, &plane_clip); > > + > > + plane_clip.y1 += new_plane_state->uapi.crtc_y; > > + plane_clip.y2 += new_plane_state->uapi.crtc_y; > > + clip_update(&pipe_clip, &plane_clip); > > + } > > This whole thing seems rather convoluted. Also using lots of uapi state > in places where I don't expect to see any. Not sure from where I should get this information then, intel_plane_state don't have it. > > I would suggest the correct way would be something like: > 1) for_each_plane_in_state() > hw.damage = translate_to_some_hw_coord_space(union(uapi.damages)) > or just use the full plane size if we have scaling i guess 99% of the time the coordinates used are based on pipe coord space, only to calculate the plane overlapping damaged area is used plane coord space. > > 2) need to add all affected planes to the state and set the appropriate > bitmask, which may mean we want to track the planes' positions in the > crtc state. I think atm we only have it in the plane state This looks a "or" to me, have all the planes added to the state when psr2 sel fetch is enabled or add track all the planes position in pipe. Although the second one would avoid us to do plane calculations and plane register sometimes, in some cases where a plane above a non-modified plane moves the non-modified plane bellow will need to be added to the state so the plane sel_fetch registers are written. We could go with the easy one(add all planes to the state) and then move to the second one latter. > > 3) translate the damage further into the final plane src coordinate > space. Dunno if we have enough state around still to do it cleanly. > I was thinking maybe it could be done alongside all the other plane > surface calculations, but there might be a chicken vs. egg situation > here since we probably want to do the plane check stuff before doing > step 1, but plane check is also where we do the surface calculations. > Dunno if we may just want to split the plane check into two stages As right now it depends mostly in uapi this could be moved to the check phase, did not left there because this will never have a error or a conflict that will cause us to reject the state. > > To keep things simple I guess what I'd suggest is to forget about the > damage stuff in the first version of the series and just do full > plane updates. That way we don't have to worry about so many coordinate > space transformations. Do that would only save us the for bellow and the if to check if plane moved: for (j = 0; j < num_clips; j++) { struct drm_rect damage_area; damage_area.x1 = clips[j].x1; damage_area.x2 = clips[j].x2; damage_area.y1 = clips[j].y1; damage_area.y2 = clips[j].y2; clip_update(&plane_clip, &damage_area); } Anyways thanks for the initial feedback. > > > + > > + intel_psr2_trans_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); > > +} > > + > > /** > > * intel_psr_update - Update PSR state > > * @intel_dp: Intel DP > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h > > index b4515186d5f4..d80bd0e46b21 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > > @@ -13,6 +13,10 @@ struct drm_connector_state; > > struct drm_i915_private; > > struct intel_crtc_state; > > struct intel_dp; > > +struct intel_crtc; > > +struct intel_atomic_state; > > +struct intel_plane_state; > > +struct intel_plane; > > > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) > > void intel_psr_init_dpcd(struct intel_dp *intel_dp); > > @@ -43,5 +47,11 @@ void intel_psr_atomic_check(struct drm_connector *connector, > > struct drm_connector_state *old_state, > > struct drm_connector_state *new_state); > > void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp); > > +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > > + struct intel_crtc *crtc); > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, > > + const struct intel_crtc_state *crtc_state, > > + const struct intel_plane_state *plane_state); > > +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); > > > > #endif /* __INTEL_PSR_H__ */ > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > > index 8be06cb25999..afede372ac05 100644 > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > @@ -690,6 +690,8 @@ skl_program_plane(struct intel_plane *plane, > > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), > > (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state); > > + > > /* > > * The control register self-arms if the plane was previously > > * disabled. Try to make the plane enable atomic by writing > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 146bfd276ce7..ae7efc922393 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -503,6 +503,7 @@ struct i915_psr { > > bool link_standby; > > bool colorimetry_support; > > bool psr2_enabled; > > + bool psr2_sel_fetch_enabled; > > u8 sink_sync_latency; > > ktime_t last_entry_attempt; > > ktime_t last_exit; > > @@ -1634,6 +1635,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > > #define HAS_PSR_HW_TRACKING(dev_priv) \ > > (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) > > +#define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12) > > #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) > > > > #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) > > diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c > > index add00ec1f787..3005451c1194 100644 > > --- a/drivers/gpu/drm/i915/i915_params.c > > +++ b/drivers/gpu/drm/i915/i915_params.c > > @@ -88,6 +88,11 @@ i915_param_named_unsafe(enable_psr, int, 0600, > > "(0=disabled, 1=enabled) " > > "Default: -1 (use per-chip default)"); > > > > +i915_param_named_unsafe(enable_psr2_sel_fetch, int, 0400, > > + "Enable PSR2 selective fetch " > > + "(0=disabled, 1=enabled) " > > + "Default: 0"); > > + > > i915_param_named_unsafe(force_probe, charp, 0400, > > "Force probe the driver for specified devices. " > > "See CONFIG_DRM_I915_FORCE_PROBE for details."); > > diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h > > index 45323732f099..5a0b16923016 100644 > > --- a/drivers/gpu/drm/i915/i915_params.h > > +++ b/drivers/gpu/drm/i915/i915_params.h > > @@ -53,6 +53,7 @@ struct drm_printer; > > param(int, enable_dc, -1, 0400) \ > > param(int, enable_fbc, -1, 0600) \ > > param(int, enable_psr, -1, 0600) \ > > + param(int, enable_psr2_sel_fetch, 0, 0400) \ > > param(int, disable_power_well, -1, 0400) \ > > param(int, enable_ips, 1, 0600) \ > > param(int, invert_brightness, 0, 0600) \ > > -- > > 2.26.2 From matthew.d.roper at intel.com Fri Jun 12 20:47:34 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Fri, 12 Jun 2020 13:47:34 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Update bw_buddy pagemask table Message-ID: <20200612204734.3674650-1-matthew.d.roper@intel.com> A recent bspec update removed the LPDDR4 single channel entry from the buddy register table, but added a new four-channel entry. Workaround 1409767108 hasn't been updated with any guidance for four channel configurations, so we leave that alternate table unchanged for now. Bspec 49218 Fixes: 3fa01d642fa7 ("drm/i915/tgl: Program BW_BUDDY registers during display init") Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 24a2aa1fdc9c..a592a7dd71a3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5240,10 +5240,10 @@ struct buddy_page_mask { }; static const struct buddy_page_mask tgl_buddy_page_masks[] = { - { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0xE }, { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF }, { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C }, { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F }, + { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 }, {} }; -- 2.24.1 From daniel.vetter at ffwll.ch Fri Jun 12 20:49:40 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 12 Jun 2020 22:49:40 +0200 Subject: [Intel-gfx] [PATCH] drm/vmwgfx: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-6-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-6-daniel.vetter@ffwll.ch> Message-ID: <20200612204940.2134653-1-daniel.vetter@ffwll.ch> Now also comes with the added benefit of doing a drm_crtc_vblank_off(), which means vblank state isn't ill-defined and fail-y at driver load before the first modeset on each crtc. v2: Compile fix. Oops. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Cc: VMware Graphics <linux-graphics-maintainer at vmware.com> Cc: Roland Scheidegger <sroland at vmware.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 3c97654b5a43..bbce45d142aa 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -629,8 +629,7 @@ void vmw_du_crtc_reset(struct drm_crtc *crtc) return; } - crtc->state = &vcs->base; - crtc->state->crtc = crtc; + __drm_atomic_helper_crtc_reset(crtc, &vcs->base); } -- 2.26.2 From hwentlan at amd.com Fri Jun 12 17:24:21 2020 From: hwentlan at amd.com (Harry Wentland) Date: Fri, 12 Jun 2020 13:24:21 -0400 Subject: [Intel-gfx] [PATCH 2/8] drm/amdgpu: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-2-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-2-daniel.vetter@ffwll.ch> Message-ID: <ad375dbb-760b-b2e9-cfab-94fba61f4eb7@amd.com> On 2020-06-12 12:00 p.m., Daniel Vetter wrote: > Now also comes with the added benefit of doing a drm_crtc_vblank_off(), > which means vblank state isn't ill-defined and fail-y at driver load > before the first modeset on each crtc. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Alex Deucher <alexander.deucher at amd.com> > Cc: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> > Cc: Harry Wentland <harry.wentland at amd.com> > Cc: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com> > Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha at amd.com> > Cc: Roman Li <roman.li at amd.com> > Cc: Mikita Lipski <mikita.lipski at amd.com> > Cc: Stylon Wang <stylon.wang at amd.com> Reviewed-by: Harry Wentland <harry.wentland at amd.com> Harry > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 68a73065b516..36d605a6eb16 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -4594,9 +4594,7 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc) > if (WARN_ON(!state)) > return; > > - crtc->state = &state->base; > - crtc->state->crtc = crtc; > - > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > } > > static struct drm_crtc_state * > From gwan-gyeong.mun at intel.com Fri Jun 12 20:57:31 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Fri, 12 Jun 2020 20:57:31 +0000 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers In-Reply-To: <20200526221447.64110-4-jose.souza@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-4-jose.souza@intel.com> Message-ID: <0cd79dd50c476c01afddea6ca1ee2fe80b0b40c1.camel@intel.com> On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > This registers will be used to implement PSR2 software tracking. > > BSpec: 55229 > BSpec: 50424 > BSpec: 50420 > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++- > -- > 1 file changed, 63 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index e9d50fe0f375..6f547e459d30 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4566,6 +4566,18 @@ enum { > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > PSR2_SU_STATUS_SHIFT(frame)) > #define PSR2_SU_STATUS_FRAMES 8 > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK REG_GENMASK(30, > 21) > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR(val) REG_FIELD_PREP( > PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val) > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK REG_GEN > MASK(20, 11) > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR(val) REG_FIE > LD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val) > +#define PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME REG_BIT(3) > +#define PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME REG_BIT > (2) > +#define PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE REG_BIT > (1) > + As per Bspec, it would be better that the names of bit as below. PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE > /* VGA port control */ > #define ADPA _MMIO(0x61100) > #define PCH_ADPA _MMIO(0xe1100) > @@ -7129,7 +7141,52 @@ enum { > #define PLANE_COLOR_CTL(pipe, plane) \ > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > _PLANE_COLOR_CTL_2(pipe)) > > -#/* SKL new cursor registers */ > +#define _PLANE_SEL_FETCH_BASE_1_A 0x70890 > +#define _PLANE_SEL_FETCH_BASE_2_A 0x708B0 > +#define _PLANE_SEL_FETCH_BASE_3_A 0x708D0 > +#define _PLANE_SEL_FETCH_BASE_4_A 0x708F0 > +#define _PLANE_SEL_FETCH_BASE_5_A 0x70920 > +#define _PLANE_SEL_FETCH_BASE_6_A 0x70940 > +#define _PLANE_SEL_FETCH_BASE_7_A 0x70960 > +#define _PLANE_SEL_FETCH_BASE_CUR_A 0x70880 > +#define _PLANE_SEL_FETCH_BASE_1_B 0x70990 > + And as per Bspec, the prefix _SEL_FETCH_PLANE_ is better than _PLANE_SEL_FETCH_ . > +#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \ > + _PLANE_SEL_FETCH_BASE_1_A, > \ > + _PLANE_SEL_FETCH_BASE_2_A, > \ > + _PLANE_SEL_FETCH_BASE_3_A, > \ > + _PLANE_SEL_FETCH_BASE_4_A, > \ > + _PLANE_SEL_FETCH_BASE_5_A, > \ > + _PLANE_SEL_FETCH_BASE_6_A, > \ > + _PLANE_SEL_FETCH_BASE_7_A, > \ > + _PLANE_SEL_FETCH_BASE_CUR_ > A) > +#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, > _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A) > +#define PLANE_SEL_FETCH_BASE(pipe, plane) > (_PLANE_SEL_FETCH_BASE_1(pipe) - \ > + _PLANE_SEL_FETCH_BASE_1_A + > \ > + _PLANE_SEL_FETCH_BASE_A(plan > e)) > + > +#define _PLANE_SEL_FETCH_CTL_1_A 0x70890 > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > + _PLANE_SEL_FETCH_CTL_1_A > - \ > + _PLANE_SEL_FETCH_BASE_1_ > A) > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) > + > +#define _PLANE_SEL_FETCH_POS_1_A 0x70894 > +#define PLANE_SEL_FETCH_POS(pipe, plane) > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > + _PLANE_SEL_FETCH_POS_1_A > - \ > + _PLANE_SEL_FETCH_BASE_1_ > A) > + > +#define _PLANE_SEL_FETCH_SIZE_1_A 0x70898 > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > + _PLANE_SEL_FETCH_SIZE_1 > _A - \ > + _PLANE_SEL_FETCH_BASE_1 > _A) > + > +#define _PLANE_SEL_FETCH_OFFSET_1_A 0x7089C > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > + _PLANE_SEL_FETCH_OFFS > ET_1_A - \ > + _PLANE_SEL_FETCH_BASE > _1_A) > + > +/* SKL new cursor registers */ > #define _CUR_BUF_CFG_A 0x7017c > #define _CUR_BUF_CFG_B 0x7117c > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, > _CUR_BUF_CFG_B) > @@ -7775,11 +7832,12 @@ enum { > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > -#define DPA_MASK_VBLANK_SRD (1 << 15) > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > +#define DPA_MASK_VBLANK_SRD (1 << 15) > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) From jon.bloomfield at intel.com Fri Jun 12 21:15:02 2020 From: jon.bloomfield at intel.com (Bloomfield, Jon) Date: Fri, 12 Jun 2020 21:15:02 +0000 Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c In-Reply-To: <20200610201807.191440-1-rodrigo.vivi@intel.com> References: <159163988890.30073.8976615673203599761@build.alporthouse.com> <20200610201807.191440-1-rodrigo.vivi@intel.com> Message-ID: <AD48BB7FB99B174FBCC69E228F58B3B6B78F0D73@fmsmsx116.amr.corp.intel.com> > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of > Rodrigo Vivi > Sent: Wednesday, June 10, 2020 1:18 PM > To: intel-gfx at lists.freedesktop.org > Cc: Alexandre Oliva <lxoliva at fsfla.org>; Nikula, Jani <jani.nikula at intel.com>; > stable at vger.kernel.org; Chris Wilson <chris at chris-wilson.co.uk> > Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, > hsw}_clear_kernel.c > > Alexandre Oliva has recently removed these files from Linux Libre > with concerns that the sources weren't available. > > The sources are available on IGT repository, and only open source > tools are used to generate the {ivb,hsw}_clear_kernel.c files. > > However, the remaining concern from Alexandre Oliva was around > GPL license and the source not been present when distributing > the code. > > So, it looks like 2 alternatives are possible, the use of > linux-firmware.git repository to store the blob or making sure > that the source is also present in our tree. Since the goal > is to limit the i915 firmware to only the micro-controller blobs > let's make sure that we do include the asm sources here in our tree. > > Btw, I tried to have some diligence here and make sure that the > asms that these commits are adding are truly the source for > the mentioned files: > > igt$ ./scripts/generate_clear_kernel.sh -g ivb \ > -m ~/mesa/build/src/intel/tools/i965_asm > Output file not specified - using default file "ivb-cb_assembled" > > Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" > for i915 driver... > > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \ > ivb_clear_kernel.c > > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT > 61c61 > < }; > > }; > \ No newline at end of file > > igt$ ./scripts/generate_clear_kernel.sh -g hsw \ > -m ~/mesa/build/src/intel/tools/i965_asm > Output file not specified - using default file "hsw-cb_assembled" > > Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" > for i915 driver... > > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \ > hsw_clear_kernel.c > 5c5 > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT > 61c61 > < }; > > }; > \ No newline at end of file > > Used IGT and Mesa master repositories from Fri Jun 5 2020) > IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging > the connector") > Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with > RADV_DEBUG=shaderstats") > Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \ > -D gallium-drivers=iris -D prefix=/usr \ > -D libdir=/usr/lib64/ -Dtools=intel \ > -Dkulkan-drivers=intel && ninja -C build > > v2: Header clean-up and include build instructions in a readme (Chris) > Modified commit message to respect check-patch > > Reference: http://www.fsfla.org/pipermail/linux-libre/2020- > June/003374.html > Reference: http://www.fsfla.org/pipermail/linux-libre/2020- > June/003375.html > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > Cc: <stable at vger.kernel.org> # v5.7+ > Cc: Alexandre Oliva <lxoliva at fsfla.org> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com> > Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Jani Nikula <jani.nikula at intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Reviewed-by: Jon Bloomfield <jon.bloomfield at intel.com> From jose.souza at intel.com Fri Jun 12 21:18:41 2020 From: jose.souza at intel.com (Souza, Jose) Date: Fri, 12 Jun 2020 21:18:41 +0000 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers In-Reply-To: <0cd79dd50c476c01afddea6ca1ee2fe80b0b40c1.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-4-jose.souza@intel.com> <0cd79dd50c476c01afddea6ca1ee2fe80b0b40c1.camel@intel.com> Message-ID: <a900639aa1065838eb841afbd4d8d3713fe9cf74.camel@intel.com> On Fri, 2020-06-12 at 21:57 +0100, Mun, Gwan-gyeong wrote: > On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > > This registers will be used to implement PSR2 software tracking. > > > > BSpec: 55229 > > BSpec: 50424 > > BSpec: 50420 > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++- > > -- > > 1 file changed, 63 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index e9d50fe0f375..6f547e459d30 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4566,6 +4566,18 @@ enum { > > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > > PSR2_SU_STATUS_SHIFT(frame)) > > #define PSR2_SU_STATUS_FRAMES 8 > > > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK REG_GENMASK(30, > > 21) > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR(val) REG_FIELD_PREP( > > PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val) > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK REG_GEN > > MASK(20, 11) > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR(val) REG_FIE > > LD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val) > > +#define PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME REG_BIT(3) > > +#define PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME REG_BIT > > (2) > > +#define PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE REG_BIT > > (1) > > + > As per Bspec, it would be better that the names of bit as below. > > PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE No problem in naming like this but MAN_TRK and SF is kind of redundant and the name was already big. Your call. > > > /* VGA port control */ > > #define ADPA _MMIO(0x61100) > > #define PCH_ADPA _MMIO(0xe1100) > > @@ -7129,7 +7141,52 @@ enum { > > #define PLANE_COLOR_CTL(pipe, plane) \ > > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > > _PLANE_COLOR_CTL_2(pipe)) > > > > -#/* SKL new cursor registers */ > > +#define _PLANE_SEL_FETCH_BASE_1_A 0x70890 > > +#define _PLANE_SEL_FETCH_BASE_2_A 0x708B0 > > +#define _PLANE_SEL_FETCH_BASE_3_A 0x708D0 > > +#define _PLANE_SEL_FETCH_BASE_4_A 0x708F0 > > +#define _PLANE_SEL_FETCH_BASE_5_A 0x70920 > > +#define _PLANE_SEL_FETCH_BASE_6_A 0x70940 > > +#define _PLANE_SEL_FETCH_BASE_7_A 0x70960 > > +#define _PLANE_SEL_FETCH_BASE_CUR_A 0x70880 > > +#define _PLANE_SEL_FETCH_BASE_1_B 0x70990 > > + > And as per Bspec, the prefix _SEL_FETCH_PLANE_ is better than > _PLANE_SEL_FETCH_ . You mean just for the "internal" ones? For PLANE_SEL_FETCH_CTL, PLANE_SEL_FETCH_SIZE... would be better keep like this to match other plane register names. > > > +#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \ > > + _PLANE_SEL_FETCH_BASE_1_A, > > \ > > + _PLANE_SEL_FETCH_BASE_2_A, > > \ > > + _PLANE_SEL_FETCH_BASE_3_A, > > \ > > + _PLANE_SEL_FETCH_BASE_4_A, > > \ > > + _PLANE_SEL_FETCH_BASE_5_A, > > \ > > + _PLANE_SEL_FETCH_BASE_6_A, > > \ > > + _PLANE_SEL_FETCH_BASE_7_A, > > \ > > + _PLANE_SEL_FETCH_BASE_CUR_ > > A) > > +#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, > > _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A) > > +#define PLANE_SEL_FETCH_BASE(pipe, plane) > > (_PLANE_SEL_FETCH_BASE_1(pipe) - \ > > + _PLANE_SEL_FETCH_BASE_1_A + > > \ > > + _PLANE_SEL_FETCH_BASE_A(plan > > e)) > > + > > +#define _PLANE_SEL_FETCH_CTL_1_A 0x70890 > > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > + _PLANE_SEL_FETCH_CTL_1_A > > - \ > > + _PLANE_SEL_FETCH_BASE_1_ > > A) > > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) > > + > > +#define _PLANE_SEL_FETCH_POS_1_A 0x70894 > > +#define PLANE_SEL_FETCH_POS(pipe, plane) > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > + _PLANE_SEL_FETCH_POS_1_A > > - \ > > + _PLANE_SEL_FETCH_BASE_1_ > > A) > > + > > +#define _PLANE_SEL_FETCH_SIZE_1_A 0x70898 > > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > + _PLANE_SEL_FETCH_SIZE_1 > > _A - \ > > + _PLANE_SEL_FETCH_BASE_1 > > _A) > > + > > +#define _PLANE_SEL_FETCH_OFFSET_1_A 0x7089C > > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > + _PLANE_SEL_FETCH_OFFS > > ET_1_A - \ > > + _PLANE_SEL_FETCH_BASE > > _1_A) > > + > > +/* SKL new cursor registers */ > > #define _CUR_BUF_CFG_A 0x7017c > > #define _CUR_BUF_CFG_B 0x7117c > > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, > > _CUR_BUF_CFG_B) > > @@ -7775,11 +7832,12 @@ enum { > > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) > > > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > > -#define DPA_MASK_VBLANK_SRD (1 << 15) > > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > +#define DPA_MASK_VBLANK_SRD (1 << 15) > > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) From gwan-gyeong.mun at intel.com Fri Jun 12 21:49:16 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Fri, 12 Jun 2020 21:49:16 +0000 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers In-Reply-To: <a900639aa1065838eb841afbd4d8d3713fe9cf74.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-4-jose.souza@intel.com> <0cd79dd50c476c01afddea6ca1ee2fe80b0b40c1.camel@intel.com> <a900639aa1065838eb841afbd4d8d3713fe9cf74.camel@intel.com> Message-ID: <41bec38440596890bea141b564235340709d414e.camel@intel.com> On Fri, 2020-06-12 at 14:18 -0700, Souza, Jose wrote: > On Fri, 2020-06-12 at 21:57 +0100, Mun, Gwan-gyeong wrote: > > On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > > > This registers will be used to implement PSR2 software tracking. > > > > > > BSpec: 55229 > > > BSpec: 50424 > > > BSpec: 50420 > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 68 > > > ++++++++++++++++++++++++++++++- > > > -- > > > 1 file changed, 63 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > b/drivers/gpu/drm/i915/i915_reg.h > > > index e9d50fe0f375..6f547e459d30 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -4566,6 +4566,18 @@ enum { > > > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > > > PSR2_SU_STATUS_SHIFT(frame)) > > > #define PSR2_SU_STATUS_FRAMES 8 > > > > > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > > > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > > > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > > > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > > > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK REG_GENMASK(30, > > > 21) > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR(val) REG_FIELD_PREP( > > > PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val) > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK REG_GEN > > > MASK(20, 11) > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR(val) REG_FIE > > > LD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val) > > > +#define PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME REG_BIT > > > (3) > > > +#define PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME REG_BIT > > > (2) > > > +#define PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE REG_BIT > > > (1) > > > + > > As per Bspec, it would be better that the names of bit as below. > > > > PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > > PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > > PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE > > No problem in naming like this but MAN_TRK and SF is kind of > redundant and the name was already big. > Your call. > > > > /* VGA port control */ > > > #define ADPA _MMIO(0x61100) > > > #define PCH_ADPA _MMIO(0xe1100) > > > @@ -7129,7 +7141,52 @@ enum { > > > #define PLANE_COLOR_CTL(pipe, plane) \ > > > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > > > _PLANE_COLOR_CTL_2(pipe)) > > > > > > -#/* SKL new cursor registers */ > > > +#define _PLANE_SEL_FETCH_BASE_1_A 0x70890 > > > +#define _PLANE_SEL_FETCH_BASE_2_A 0x708B0 > > > +#define _PLANE_SEL_FETCH_BASE_3_A 0x708D0 > > > +#define _PLANE_SEL_FETCH_BASE_4_A 0x708F0 > > > +#define _PLANE_SEL_FETCH_BASE_5_A 0x70920 > > > +#define _PLANE_SEL_FETCH_BASE_6_A 0x70940 > > > +#define _PLANE_SEL_FETCH_BASE_7_A 0x70960 > > > +#define _PLANE_SEL_FETCH_BASE_CUR_A 0x70880 > > > +#define _PLANE_SEL_FETCH_BASE_1_B 0x70990 > > > + > > And as per Bspec, the prefix _SEL_FETCH_PLANE_ is better than > > _PLANE_SEL_FETCH_ . > You mean just for the "internal" ones? For PLANE_SEL_FETCH_CTL, > PLANE_SEL_FETCH_SIZE... would be better keep like this to match other > plane register > names. Internals and externals. I also noticed your intention (match other plane related registers), but when I checked other plane related resiters, they followed bspec names. (But I am not confident on register naming policy; we always have to follow documented register names or not. ) > > > > +#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \ > > > + _PLANE_SEL_FETCH_BASE_1_A, > > > \ > > > + _PLANE_SEL_FETCH_BASE_2_A, > > > \ > > > + _PLANE_SEL_FETCH_BASE_3_A, > > > \ > > > + _PLANE_SEL_FETCH_BASE_4_A, > > > \ > > > + _PLANE_SEL_FETCH_BASE_5_A, > > > \ > > > + _PLANE_SEL_FETCH_BASE_6_A, > > > \ > > > + _PLANE_SEL_FETCH_BASE_7_A, > > > \ > > > + _PLANE_SEL_FETCH_BASE_CUR_ > > > A) > > > +#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, > > > _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A) > > > +#define PLANE_SEL_FETCH_BASE(pipe, plane) > > > (_PLANE_SEL_FETCH_BASE_1(pipe) - \ > > > + _PLANE_SEL_FETCH_BASE_1_A + > > > \ > > > + _PLANE_SEL_FETCH_BASE_A(plan > > > e)) > > > + > > > +#define _PLANE_SEL_FETCH_CTL_1_A 0x70890 > > > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > + _PLANE_SEL_FETCH_CTL_1_A > > > - \ > > > + _PLANE_SEL_FETCH_BASE_1_ > > > A) > > > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) > > > + > > > +#define _PLANE_SEL_FETCH_POS_1_A 0x70894 > > > +#define PLANE_SEL_FETCH_POS(pipe, plane) > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > + _PLANE_SEL_FETCH_POS_1_A > > > - \ > > > + _PLANE_SEL_FETCH_BASE_1_ > > > A) > > > + > > > +#define _PLANE_SEL_FETCH_SIZE_1_A 0x70898 > > > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > + _PLANE_SEL_FETCH_SIZE_1 > > > _A - \ > > > + _PLANE_SEL_FETCH_BASE_1 > > > _A) > > > + > > > +#define _PLANE_SEL_FETCH_OFFSET_1_A 0x7089C > > > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > + _PLANE_SEL_FETCH_OFFS > > > ET_1_A - \ > > > + _PLANE_SEL_FETCH_BASE > > > _1_A) > > > + > > > +/* SKL new cursor registers */ > > > #define _CUR_BUF_CFG_A 0x7017c > > > #define _CUR_BUF_CFG_B 0x7117c > > > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, > > > _CUR_BUF_CFG_A, > > > _CUR_BUF_CFG_B) > > > @@ -7775,11 +7832,12 @@ enum { > > > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) > > > > > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > > > -#define DPA_MASK_VBLANK_SRD (1 << 15) > > > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > +#define DPA_MASK_VBLANK_SRD (1 << 15) > > > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > > > > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > > > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) From patchwork at emeril.freedesktop.org Fri Jun 12 21:57:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 21:57:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Update_bw=5Fbuddy_pagemask_table?= In-Reply-To: <20200612204734.3674650-1-matthew.d.roper@intel.com> References: <20200612204734.3674650-1-matthew.d.roper@intel.com> Message-ID: <159199904665.21337.1490902512564828842@emeril.freedesktop.org> == Series Details == Series: drm/i915: Update bw_buddy pagemask table URL : https://patchwork.freedesktop.org/series/78276/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17942 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/index.html Known issues ------------ Here are the changes found in Patchwork_17942 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@hdmi-crc-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#1372]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-7500u/igt at kms_chamelium@hdmi-crc-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-kbl-7500u/igt at kms_chamelium@hdmi-crc-fast.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-cml-s: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-cml-s/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-cml-s/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][13] ([i915#1993]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 42) ------------------------------ Additional (1): fi-tgl-u2 Missing (8): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17942 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17942: d2b1478a5a609fd6f1ee0711cad56b2a67d4708d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d2b1478a5a60 drm/i915: Update bw_buddy pagemask table == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/index.html From mika.kuoppala at linux.intel.com Fri Jun 12 21:56:20 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Sat, 13 Jun 2020 00:56:20 +0300 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/execlists: Lift opportunistic process_csb to before engine lock In-Reply-To: <20200612142551.30956-1-chris@chris-wilson.co.uk> References: <20200612142551.30956-1-chris@chris-wilson.co.uk> Message-ID: <87imfwrlrv.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Since the process_csb() does not require us to hold the > engine->active.lock, we can move the opportunistic flush before > direction submission to outside of the lock. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 21 ++++++++++++++------- > 1 file changed, 14 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 5ab0ed35af84..e866b8d721ed 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -3170,13 +3170,6 @@ static void __submit_queue_imm(struct intel_engine_cs *engine) > if (reset_in_progress(execlists)) > return; /* defer until we restart the engine following reset */ > > - /* Hopefully we clear execlists->pending[] to let us through */ > - if (READ_ONCE(execlists->pending[0]) && > - tasklet_trylock(&execlists->tasklet)) { > - process_csb(engine); > - tasklet_unlock(&execlists->tasklet); > - } > - > __execlists_submission_tasklet(engine); > } > > @@ -3199,11 +3192,25 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, > return !list_empty(&engine->active.hold) && hold_request(rq); > } > > +static void flush_csb(struct intel_engine_cs *engine) > +{ > + struct intel_engine_execlists *el = &engine->execlists; > + > + if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { > + if (!reset_in_progress(el)) > + process_csb(engine); > + tasklet_unlock(&el->tasklet); > + } > +} > + > static void execlists_submit_request(struct i915_request *request) > { > struct intel_engine_cs *engine = request->engine; > unsigned long flags; > > + /* Hopefully we clear execlists->pending[] to let us through */ > + flush_csb(engine); > + > /* Will be called from irq-context when using foreign fences. */ > spin_lock_irqsave(&engine->active.lock, flags); > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Fri Jun 12 22:02:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 22:02:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_v?= =?utf-8?q?blank_on_crtc_reset_=28rev2=29?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159199933336.21335.16072973506375514396@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset (rev2) URL : https://patchwork.freedesktop.org/series/78268/ State : warning == Summary == $ dim checkpatch origin/drm-tip 459d02ce47b5 drm/atomic-helper: reset vblank on crtc reset -:295: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 148 lines checked c266a8cbabc7 drm/amdgpu: Use __drm_atomic_helper_crtc_reset -:35: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 10 lines checked d584e2e79995 drm/imx: Use __drm_atomic_helper_crtc_reset -:51: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 28 lines checked 580e961d16f9 drm/mtk: Use __drm_atomic_helper_crtc_reset -:46: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 25 lines checked 43fa3b7935a5 drm/vc4: Use __drm_atomic_helper_crtc_reset -:28: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 11 lines checked 484591c27864 drm/vmwgfx: Use __drm_atomic_helper_crtc_reset -:29: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 9 lines checked a5fd563899ea drm/mipi-dbi: Remove ->enabled -:191: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 136 lines checked 923b9ca5f747 drm/tiny/repaper: Drop edp->enabled -:68: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 1 warnings, 0 checks, 45 lines checked From patchwork at emeril.freedesktop.org Fri Jun 12 22:02:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 22:02:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_vblan?= =?utf-8?q?k_on_crtc_reset_=28rev2=29?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159199936672.21335.11184474515650980594@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset (rev2) URL : https://patchwork.freedesktop.org/series/78268/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1121:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1126:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1126:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1126:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1128:36: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1195:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1195:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1195:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1201:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1227:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1229:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1233:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1234:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1237:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:1576:16: warning: symbol 'amdgpu_dm_commit_zero_streams' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2696:24: warning: symbol 'dm_atomic_get_new_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2714:24: warning: symbol 'dm_atomic_get_old_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5537:6: warning: symbol 'dm_drm_plane_destroy_state' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:699:6: warning: symbol 'amdgpu_dm_audio_eld_notify' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:754:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:758:23: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:759:23: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:762:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:765:28: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8921:6: warning: symbol 'amdgpu_dm_psr_enable' was not declared. Should it be static? +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8925:50: warning: missing braces around initializer From patchwork at emeril.freedesktop.org Fri Jun 12 22:07:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 22:07:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/icl+=3A_Fix_hotplug_interrupt_disabling_after_storm_detec?= =?utf-8?q?tion?= In-Reply-To: <20200612121731.19596-1-imre.deak@intel.com> References: <20200612121731.19596-1-imre.deak@intel.com> Message-ID: <159199963940.21336.7090818552184097192@emeril.freedesktop.org> == Series Details == Series: drm/i915/icl+: Fix hotplug interrupt disabling after storm detection URL : https://patchwork.freedesktop.org/series/78258/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621_full -> Patchwork_17937_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17937_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#1930]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-glk5/igt at gem_exec_schedule@smoketest-all.html * igt at gem_tiled_swapping@non-threaded: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#183]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb8/igt at gem_tiled_swapping@non-threaded.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-tglb7/igt at gem_tiled_swapping@non-threaded.html * igt at i915_module_load@reload: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-tglb1/igt at i915_module_load@reload.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk9/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#54]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl8/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html * igt at kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#69]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl1/igt at kms_fbcon_fbt@psr-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl2/igt at kms_fbcon_fbt@psr-suspend.html * igt at kms_flip@basic-plain-flip at c-vga1: - shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([i915#61]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw6/igt at kms_flip@basic-plain-flip at c-vga1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-hsw1/igt at kms_flip@basic-plain-flip at c-vga1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#46]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank at a-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl10/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl7/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl8/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +4 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_basic: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb2/igt at kms_psr@psr2_basic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-iclb5/igt at kms_psr@psr2_basic.html * igt at kms_universal_plane@disable-primary-vs-flip-pipe-c: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl5/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html * igt at perf_pmu@other-init-4: - shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#95]) +14 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at perf_pmu@other-init-4.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl7/igt at perf_pmu@other-init-4.html #### Possible fixes #### * igt at gem_exec_schedule@implicit-read-write at bcs0: - shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb1/igt at gem_exec_schedule@implicit-read-write at bcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-snb4/igt at gem_exec_schedule@implicit-read-write at bcs0.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [DMESG-WARN][37] ([i915#402]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_selftest@perf at request: - shard-tglb: [DMESG-FAIL][39] ([i915#1823]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt at i915_selftest@perf at request.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-tglb8/igt at i915_selftest@perf at request.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +5 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl1/igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-hsw: [DMESG-WARN][45] ([i915#128]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw4/igt at kms_cursor_legacy@pipe-c-torture-bo.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-hsw2/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1: - shard-hsw: [INCOMPLETE][47] ([i915#61]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw1/igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-hsw2/igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +9 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl8/igt at kms_hdr@bpc-switch-dpms.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl1/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][53] ([i915#69]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-skl9/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb4/igt at kms_psr@psr2_suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-iclb7/igt at perf@blocking-parameterized.html * igt at perf_pmu@other-read-0: - shard-apl: [DMESG-WARN][59] ([i915#95]) -> [PASS][60] +17 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl4/igt at perf_pmu@other-read-0.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl3/igt at perf_pmu@other-read-0.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][61] ([i915#1820]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][63] ([i915#658]) -> [SKIP][64] ([i915#588]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb4/igt at i915_pm_dc@dc3co-vpb-simulation.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#454]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-tglb6/igt at i915_pm_dc@dc6-dpms.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][67] ([i915#1319] / [i915#1958]) -> [TIMEOUT][68] ([i915#1319]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_content_protection@atomic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-kbl7/igt at kms_content_protection@atomic.html - shard-apl: [DMESG-FAIL][69] ([fdo#110321]) -> [FAIL][70] ([fdo#110321] / [fdo#110336]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_content_protection@atomic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][71] ([i915#1319]) -> [TIMEOUT][72] ([i915#1319] / [i915#1635]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl8/igt at kms_content_protection@legacy.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@srm: - shard-apl: [DMESG-FAIL][73] ([fdo#110321]) -> [TIMEOUT][74] ([i915#1319] / [i915#1635]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_content_protection@srm.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl7/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][75] ([i915#180] / [i915#95]) -> [DMESG-WARN][76] ([i915#95]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/shard-apl4/igt at kms_frontbuffer_tracking@fbc-suspend.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#183]: https://gitlab.freedesktop.org/drm/intel/issues/183 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17937 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17937: a09f4bc8ddb9cfad0f18bdaccada93f9e98d5c54 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17937/index.html From mika.kuoppala at linux.intel.com Fri Jun 12 22:05:18 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Sat, 13 Jun 2020 01:05:18 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <20200612123949.7093-1-chris@chris-wilson.co.uk> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> <20200612123949.7093-1-chris@chris-wilson.co.uk> Message-ID: <87ftb0rlcx.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a > subsequent read from e.g. the sampler can bypass the store and read the > stale value from memory. This is a serious issue when we are using MI > stores to rewrite the batches for relocation, as it means that the batch > is reading from random user/kernel memory. While it is particularly > sensitive [and detectable] for relocations, reading stale data at any > time is a worry. > > Having started with a small number of delaying stores and doubling until > no more incoherency was seen over a few hours (with and without > background memory pressure), 32 was the magic number. > > v2: Follow more closer with the gen5 w/a and include some > post-invalidate flushes as well. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++-------------- > 1 file changed, 25 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > index 3fb0dc1fb910..5400d657f334 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > @@ -13,28 +13,25 @@ > > int gen2_emit_flush(struct i915_request *rq, u32 mode) > { > - unsigned int num_store_dw; > + unsigned int num_store_dw = 12; > u32 cmd, *cs; > > cmd = MI_FLUSH; > - num_store_dw = 0; > if (mode & EMIT_INVALIDATE) > cmd |= MI_READ_FLUSH; > - if (mode & EMIT_FLUSH) > - num_store_dw = 4; > > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); > + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); > if (IS_ERR(cs)) > return PTR_ERR(cs); > > *cs++ = cmd; > while (num_store_dw--) { > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > - INTEL_GT_SCRATCH_FIELD_DEFAULT); > - *cs++ = 0; > + *cs++ = MI_STORE_DWORD_INDEX; > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); > + *cs++ = rq->fence.seqno - 1; > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > } > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > + *cs++ = cmd; > > intel_ring_advance(rq, cs); > > @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) > return 0; > } > > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, > + int flush, int post) > { > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > > *cs++ = MI_FLUSH; > > - *cs++ = MI_STORE_DWORD_INDEX; > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; > - *cs++ = rq->fence.seqno; > - > - *cs++ = MI_USER_INTERRUPT; How can you throw the interrupt part out? -Mika > - *cs++ = MI_NOOP; > - > - rq->tail = intel_ring_offset(rq, cs); > - assert_ring_tail_valid(rq->ring, rq->tail); > - > - return cs; > -} > - > -#define GEN5_WA_STORES 8 /* must be at least 1! */ > -u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) > -{ > - int i; > - > - GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > - GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > - > - *cs++ = MI_FLUSH; > + while (flush--) { > + *cs++ = MI_STORE_DWORD_INDEX; > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); > + *cs++ = rq->fence.seqno; > + } > > - BUILD_BUG_ON(GEN5_WA_STORES < 1); > - for (i = 0; i < GEN5_WA_STORES; i++) { > + while (post--) { > *cs++ = MI_STORE_DWORD_INDEX; > *cs++ = I915_GEM_HWS_SEQNO_ADDR; > *cs++ = rq->fence.seqno; > @@ -186,7 +166,16 @@ u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) > > return cs; > } > -#undef GEN5_WA_STORES > + > +u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +{ > + return __gen2_emit_breadcrumb(rq, cs, 16, 8); > +} > + > +u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) > +{ > + return __gen2_emit_breadcrumb(rq, cs, 8, 8); > +} > > /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ > #define I830_BATCH_LIMIT SZ_256K > -- > 2.20.1 From chris at chris-wilson.co.uk Fri Jun 12 22:10:18 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 23:10:18 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <87ftb0rlcx.fsf@gaia.fi.intel.com> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> <20200612123949.7093-1-chris@chris-wilson.co.uk> <87ftb0rlcx.fsf@gaia.fi.intel.com> Message-ID: <159199981892.2981.2735577690762279899@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-12 23:05:18) > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a > > subsequent read from e.g. the sampler can bypass the store and read the > > stale value from memory. This is a serious issue when we are using MI > > stores to rewrite the batches for relocation, as it means that the batch > > is reading from random user/kernel memory. While it is particularly > > sensitive [and detectable] for relocations, reading stale data at any > > time is a worry. > > > > Having started with a small number of delaying stores and doubling until > > no more incoherency was seen over a few hours (with and without > > background memory pressure), 32 was the magic number. > > > > v2: Follow more closer with the gen5 w/a and include some > > post-invalidate flushes as well. > > > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 > > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > > --- > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++-------------- > > 1 file changed, 25 insertions(+), 36 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > index 3fb0dc1fb910..5400d657f334 100644 > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > > @@ -13,28 +13,25 @@ > > > > int gen2_emit_flush(struct i915_request *rq, u32 mode) > > { > > - unsigned int num_store_dw; > > + unsigned int num_store_dw = 12; > > u32 cmd, *cs; > > > > cmd = MI_FLUSH; > > - num_store_dw = 0; > > if (mode & EMIT_INVALIDATE) > > cmd |= MI_READ_FLUSH; > > - if (mode & EMIT_FLUSH) > > - num_store_dw = 4; > > > > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); > > + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); > > if (IS_ERR(cs)) > > return PTR_ERR(cs); > > > > *cs++ = cmd; > > while (num_store_dw--) { > > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > > - INTEL_GT_SCRATCH_FIELD_DEFAULT); > > - *cs++ = 0; > > + *cs++ = MI_STORE_DWORD_INDEX; > > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); > > + *cs++ = rq->fence.seqno - 1; > > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > > } > > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > > + *cs++ = cmd; > > > > intel_ring_advance(rq, cs); > > > > @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) > > return 0; > > } > > > > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, > > + int flush, int post) > > { > > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > > > > *cs++ = MI_FLUSH; > > > > - *cs++ = MI_STORE_DWORD_INDEX; > > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; > > - *cs++ = rq->fence.seqno; > > - > > - *cs++ = MI_USER_INTERRUPT; > > How can you throw the interrupt part out? Diff being confusing. gen3_emit_breadcrumb and gen5_emit_breadcrumb merged together. -Chris From chris at chris-wilson.co.uk Fri Jun 12 22:11:13 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 12 Jun 2020 23:11:13 +0100 Subject: [Intel-gfx] [CI] drm/i915/execlists: Lift opportunistic process_csb to before engine lock Message-ID: <20200612221113.9129-1-chris@chris-wilson.co.uk> Since the process_csb() does not require us to hold the engine->active.lock, we can move the opportunistic flush before direction submission to outside of the lock. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 5ab0ed35af84..e866b8d721ed 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3170,13 +3170,6 @@ static void __submit_queue_imm(struct intel_engine_cs *engine) if (reset_in_progress(execlists)) return; /* defer until we restart the engine following reset */ - /* Hopefully we clear execlists->pending[] to let us through */ - if (READ_ONCE(execlists->pending[0]) && - tasklet_trylock(&execlists->tasklet)) { - process_csb(engine); - tasklet_unlock(&execlists->tasklet); - } - __execlists_submission_tasklet(engine); } @@ -3199,11 +3192,25 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } +static void flush_csb(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists *el = &engine->execlists; + + if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { + if (!reset_in_progress(el)) + process_csb(engine); + tasklet_unlock(&el->tasklet); + } +} + static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; + /* Hopefully we clear execlists->pending[] to let us through */ + flush_csb(engine); + /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 12 22:25:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 22:25:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_vblank_o?= =?utf-8?q?n_crtc_reset_=28rev2=29?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159200072197.21338.6855895901230078959@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset (rev2) URL : https://patchwork.freedesktop.org/series/78268/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17943 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/index.html Known issues ------------ Here are the changes found in Patchwork_17943 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_fence@nb-await at vcs0: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-byt-j1900/igt at gem_exec_fence@nb-await at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-byt-j1900/igt at gem_exec_fence@nb-await at vcs0.html * igt at kms_busy@basic at flip: - fi-kbl-soraka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-soraka/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-kbl-soraka/igt at kms_busy@basic at flip.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][7] ([i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 42) ------------------------------ Additional (1): fi-tgl-u2 Missing (8): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17943 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17943: 923b9ca5f747ec1d47686fc47f9c66434763b1ae @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 923b9ca5f747 drm/tiny/repaper: Drop edp->enabled a5fd563899ea drm/mipi-dbi: Remove ->enabled 484591c27864 drm/vmwgfx: Use __drm_atomic_helper_crtc_reset 43fa3b7935a5 drm/vc4: Use __drm_atomic_helper_crtc_reset 580e961d16f9 drm/mtk: Use __drm_atomic_helper_crtc_reset d584e2e79995 drm/imx: Use __drm_atomic_helper_crtc_reset c266a8cbabc7 drm/amdgpu: Use __drm_atomic_helper_crtc_reset 459d02ce47b5 drm/atomic-helper: reset vblank on crtc reset == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/index.html From patchwork at emeril.freedesktop.org Fri Jun 12 22:51:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 22:51:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/execlists=3A_Lift_opportunistic_process=5Fcsb_to_before_e?= =?utf-8?q?ngine_lock?= In-Reply-To: <20200612221113.9129-1-chris@chris-wilson.co.uk> References: <20200612221113.9129-1-chris@chris-wilson.co.uk> Message-ID: <159200228510.21338.13522918552850952042@emeril.freedesktop.org> == Series Details == Series: drm/i915/execlists: Lift opportunistic process_csb to before engine lock URL : https://patchwork.freedesktop.org/series/78277/ State : success == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17944 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/index.html Known issues ------------ Here are the changes found in Patchwork_17944 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([i915#1372]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-kbl-7500u/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [DMESG-FAIL][9] ([i915#1993]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-y/igt at i915_selftest@live at execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][19] ([fdo#109271]) -> [DMESG-FAIL][20] ([i915#62]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#1993]: https://gitlab.freedesktop.org/drm/intel/issues/1993 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 42) ------------------------------ Additional (1): fi-tgl-u2 Missing (8): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17944 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17944: b65fd8af838773f4a38ad5d968db1c90258c113a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b65fd8af8387 drm/i915/execlists: Lift opportunistic process_csb to before engine lock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/index.html From manasi.d.navare at intel.com Fri Jun 12 23:04:42 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 16:04:42 -0700 Subject: [Intel-gfx] [PATCH v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <20200612230444.10121-2-manasi.d.navare@intel.com> DP sink device sets the Ignore MSA bit in its DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to ignore the MSA video timing parameters and its ability to support seamless video timing change over a range of timing exposed by DisplayID and EDID. This is required for the sink to indicate that it is Adaptive sync capable. v3: * Fi the typo in commit message (Manasi) v2: * Rename to describe what the function does (Jani Nikula) Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Harry Wentland <harry.wentland at amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas at amd.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Reviewed-by: Harry Wentland <harry.wentland at amd.com> --- include/drm/drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1165ec105638..e47dc22ebf50 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) DP_ALTERNATE_SCRAMBLER_RESET_CAP; } +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + /* * DisplayPort AUX channel */ -- 2.19.1 From manasi.d.navare at intel.com Fri Jun 12 23:04:41 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 16:04:41 -0700 Subject: [Intel-gfx] [PATCH v6 0/3] VRR capable attach prop in i915, DPCD helper, VRR debugfs Message-ID: <20200612230444.10121-1-manasi.d.navare@intel.com> This is an initial set of patches for enabling VRR support in i915. This series has patches for: 1. adding a drm dpcd helper to read ignore MSA bit in sink's DPCD indicating sink support for VRR 2. Attach and set VRR capable connector prop for Intel DP conn 3. Expose VRR min and max through debugfs Aditya Swarup (1): drm/i915/dp: Attach and set drm connector VRR property Bhanuprakash Modem (1): drm/i915/dp: Expose connector VRR monitor range via debugfs Manasi Navare (1): drm/dp: DRM DP helper for reading Ignore MSA from DPCD .../drm/i915/display/intel_display_debugfs.c | 20 ++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ include/drm/drm_dp_helper.h | 8 ++++++ 4 files changed, 57 insertions(+) -- 2.19.1 From manasi.d.navare at intel.com Fri Jun 12 23:04:43 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 16:04:43 -0700 Subject: [Intel-gfx] [PATCH v6 2/3] drm/i915/dp: Attach and set drm connector VRR property In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <20200612230444.10121-3-manasi.d.navare@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..d0dba81cfb07 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6149,6 +6149,9 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -6256,6 +6259,23 @@ intel_dp_force(struct drm_connector *connector) intel_display_power_put(dev_priv, aux_domain, wakeref); } +bool intel_dp_is_vrr_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + static int intel_dp_get_modes(struct drm_connector *connector) { struct intel_connector *intel_connector = to_intel_connector(connector); @@ -6264,6 +6284,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_dp_is_vrr_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7325,6 +7349,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (INTEL_GEN(dev_priv) >= 12) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..db895a3cd93f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -14,6 +14,7 @@ enum pipe; enum port; struct drm_connector_state; struct drm_encoder; +struct drm_connector; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct drm_dp_vsc_sdp; @@ -120,6 +121,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); void intel_dp_process_phy_request(struct intel_dp *intel_dp); +bool intel_dp_is_vrr_capable(struct drm_connector *connector); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { -- 2.19.1 From manasi.d.navare at intel.com Fri Jun 12 23:04:44 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 16:04:44 -0700 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <20200612230444.10121-4-manasi.d.navare@intel.com> From: Bhanuprakash Modem <bhanuprakash.modem at intel.com> [Why] It's useful to know the min and max vrr range for IGT testing. [How] Expose the min and max vfreq for the connector via a debugfs file on the connector, "vrr_range". Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range v6: * Rebase (manasi) v5: * Rename to vrr_range to match AMD debugfs v4: * Rebase v3: * Remove the unnecessary debug print (Manasi) v2: * Fix the typo in max_vfreq (Manasi) * Change the name of node to i915_vrr_info so we can add other vrr info for more debug info (Manasi) * Change the VRR capable to display Yes or No (Manasi) * Fix indentation checkpatch errors (Manasi) Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Tested-by: Manasi Navare <manasi.d.navare at intel.com> --- .../drm/i915/display/intel_display_debugfs.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 28dd717e943a..fc05d3468a7b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2185,6 +2185,21 @@ static const struct file_operations i915_dsc_fec_support_fops = { .write = i915_dsc_fec_support_write }; +static int vrr_range_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + + if (connector->status != connector_status_connected) + return -ENODEV; + + seq_printf(m, "Vrr_capable: %s\n", yesno(intel_dp_is_vrr_capable(connector))); + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(vrr_range); + /** * intel_connector_debugfs_add - add i915 specific connector debugfs files * @connector: pointer to a registered drm_connector @@ -2224,6 +2239,11 @@ int intel_connector_debugfs_add(struct drm_connector *connector) debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, connector, &i915_dsc_fec_support_fops); + if (INTEL_GEN(dev_priv) >= 12) + debugfs_create_file("vrr_range", S_IRUGO, + root, connector, &vrr_range_fops); + } + /* Legacy panels doesn't lpsp on any platform */ if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && -- 2.19.1 From patchwork at emeril.freedesktop.org Fri Jun 12 23:16:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 12 Jun 2020 23:16:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBW?= =?utf-8?q?RR_capable_attach_prop_in_i915=2C_DPCD_helper=2C_VRR_debugfs?= In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <159200376032.21335.8550410919833174987@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, DPCD helper, VRR debugfs URL : https://patchwork.freedesktop.org/series/78278/ State : failure == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/display/intel_display_debugfs.o drivers/gpu/drm/i915/display/intel_display_debugfs.c: In function ?intel_connector_debugfs_add?: drivers/gpu/drm/i915/display/intel_display_debugfs.c:2235:2: error: this ?if? clause does not guard... [-Werror=misleading-indentation] if (INTEL_GEN(dev_priv) >= 10 && ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c:2242:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ?if? if (INTEL_GEN(dev_priv) >= 12) ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c: At top level: drivers/gpu/drm/i915/display/intel_display_debugfs.c:2248:2: error: expected identifier or ?(? before ?if? if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) || ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c:2258:2: error: expected identifier or ?(? before ?return? return 0; ^~~~~~ drivers/gpu/drm/i915/display/intel_display_debugfs.c:2259:1: error: expected identifier or ?(? before ?}? token } ^ drivers/gpu/drm/i915/display/intel_display_debugfs.c: In function ?intel_connector_debugfs_add?: drivers/gpu/drm/i915/display/intel_display_debugfs.c:2245:2: error: control reaches end of non-void function [-Werror=return-type] } ^ cc1: all warnings being treated as errors scripts/Makefile.build:266: recipe for target 'drivers/gpu/drm/i915/display/intel_display_debugfs.o' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_display_debugfs.o] Error 1 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:488: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1729: recipe for target 'drivers' failed make: *** [drivers] Error 2 From lkp at intel.com Fri Jun 12 23:21:43 2020 From: lkp at intel.com (kernel test robot) Date: Sat, 13 Jun 2020 07:21:43 +0800 Subject: [Intel-gfx] [PATCH 6/8] drm/vmwgfx: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-6-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-6-daniel.vetter@ffwll.ch> Message-ID: <202006130752.WFKm8kxc%lkp@intel.com> Hi Daniel, I love your patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.7 next-20200612] [cannot apply to drm/drm-next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Daniel-Vetter/drm-atomic-helper-reset-vblank-on-crtc-reset/20200613-000414 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-rhel-7.6 (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): # save the attached .config to linux build tree make W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): drivers/gpu/drm/vmwgfx/vmwgfx_kms.c: In function 'vmw_du_primary_plane_atomic_check': drivers/gpu/drm/vmwgfx/vmwgfx_kms.c:460:31: warning: variable 'vcs' set but not used [-Wunused-but-set-variable] 460 | struct vmw_connector_state *vcs; | ^~~ drivers/gpu/drm/vmwgfx/vmwgfx_kms.c: In function 'vmw_du_crtc_reset': << In file included from drivers/gpu/drm/vmwgfx/vmwgfx_kms.c:37: >> drivers/gpu/drm/vmwgfx/vmwgfx_kms.c:632:40: error: 'state' undeclared (first use in this function); did you mean 'statx'? 632 | __drm_atomic_helper_crtc_reset(crtc, &state->base); | ^~~~~ | statx drivers/gpu/drm/vmwgfx/vmwgfx_kms.c:632:40: note: each undeclared identifier is reported only once for each function it appears in In file included from drivers/gpu/drm/vmwgfx/vmwgfx_kms.c:37: At top level: drivers/gpu/drm/vmwgfx/vmwgfx_kms.h:256:23: warning: 'vmw_cursor_plane_formats' defined but not used [-Wunused-const-variable=] 256 | static const uint32_t vmw_cursor_plane_formats[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/vmwgfx/vmwgfx_kms.h:248:23: warning: 'vmw_primary_plane_formats' defined but not used [-Wunused-const-variable=] 248 | static const uint32_t vmw_primary_plane_formats[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~~ vim +632 drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 604 605 606 /** 607 * vmw_du_crtc_reset - creates a blank vmw crtc state 608 * @crtc: DRM crtc 609 * 610 * Resets the atomic state for @crtc by freeing the state pointer (which 611 * might be NULL, e.g. at driver load time) and allocating a new empty state 612 * object. 613 */ 614 void vmw_du_crtc_reset(struct drm_crtc *crtc) 615 { 616 struct vmw_crtc_state *vcs; 617 618 619 if (crtc->state) { 620 __drm_atomic_helper_crtc_destroy_state(crtc->state); 621 622 kfree(vmw_crtc_state_to_vcs(crtc->state)); 623 } 624 625 vcs = kzalloc(sizeof(*vcs), GFP_KERNEL); 626 627 if (!vcs) { 628 DRM_ERROR("Cannot allocate vmw_crtc_state\n"); 629 return; 630 } 631 > 632 __drm_atomic_helper_crtc_reset(crtc, &state->base); 633 } 634 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 48661 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200613/7f3e623a/attachment-0001.gz> From manasi.d.navare at intel.com Fri Jun 12 23:56:06 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 12 Jun 2020 16:56:06 -0700 Subject: [Intel-gfx] [PATCH v7 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <20200612230444.10121-4-manasi.d.navare@intel.com> References: <20200612230444.10121-4-manasi.d.navare@intel.com> Message-ID: <20200612235606.25120-1-manasi.d.navare@intel.com> From: Bhanuprakash Modem <bhanuprakash.modem at intel.com> [Why] It's useful to know the min and max vrr range for IGT testing. [How] Expose the min and max vfreq for the connector via a debugfs file on the connector, "vrr_range". Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range v7: * Fix cmpilation due to rebase v6: * Rebase (manasi) v5: * Rename to vrr_range to match AMD debugfs v4: * Rebase v3: * Remove the unnecessary debug print (Manasi) v2: * Fix the typo in max_vfreq (Manasi) * Change the name of node to i915_vrr_info so we can add other vrr info for more debug info (Manasi) * Change the VRR capable to display Yes or No (Manasi) * Fix indentation checkpatch errors (Manasi) Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Tested-by: Manasi Navare <manasi.d.navare at intel.com> --- .../drm/i915/display/intel_display_debugfs.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 28dd717e943a..2921f7d2a26e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -2185,6 +2185,21 @@ static const struct file_operations i915_dsc_fec_support_fops = { .write = i915_dsc_fec_support_write }; +static int vrr_range_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + + if (connector->status != connector_status_connected) + return -ENODEV; + + seq_printf(m, "Vrr_capable: %s\n", yesno(intel_dp_is_vrr_capable(connector))); + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(vrr_range); + /** * intel_connector_debugfs_add - add i915 specific connector debugfs files * @connector: pointer to a registered drm_connector @@ -2220,10 +2235,15 @@ int intel_connector_debugfs_add(struct drm_connector *connector) if (INTEL_GEN(dev_priv) >= 10 && ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && !to_intel_connector(connector)->mst_port) || - connector->connector_type == DRM_MODE_CONNECTOR_eDP)) + connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, connector, &i915_dsc_fec_support_fops); + if (INTEL_GEN(dev_priv) >= 12) + debugfs_create_file("vrr_range", S_IRUGO, + root, connector, &vrr_range_fops); + } + /* Legacy panels doesn't lpsp on any platform */ if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && -- 2.19.1 From patchwork at emeril.freedesktop.org Sat Jun 13 00:07:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 13 Jun 2020 00:07:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_VRR_capable_attach_prop_in_i915=2C_DPCD_helper=2C_VRR_debug?= =?utf-8?b?ZnMgKHJldjIp?= In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <159200687620.20488.14744381936660250478@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev2) URL : https://patchwork.freedesktop.org/series/78278/ State : warning == Summary == $ dim checkpatch origin/drm-tip 46b7d1d313bd drm/dp: DRM DP helper for reading Ignore MSA from DPCD b0b10c7d0ea5 drm/i915/dp: Attach and set drm connector VRR property bb21c069cdf4 drm/i915/dp: Expose connector VRR monitor range via debugfs -:77: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. #77: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:2243: + debugfs_create_file("vrr_range", S_IRUGO, total: 0 errors, 1 warnings, 0 checks, 37 lines checked From patchwork at emeril.freedesktop.org Sat Jun 13 00:09:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 13 Jun 2020 00:09:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?VRR_capable_attach_prop_in_i915=2C_DPCD_helper=2C_VRR_debugfs_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <159200697869.20487.10611855048160651103@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev2) URL : https://patchwork.freedesktop.org/series/78278/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '<asn:2>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '<asn:2> From patchwork at emeril.freedesktop.org Sat Jun 13 00:14:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 13 Jun 2020 00:14:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915=3A_Update_bw=5Fbuddy_pagemask_table?= In-Reply-To: <20200612204734.3674650-1-matthew.d.roper@intel.com> References: <20200612204734.3674650-1-matthew.d.roper@intel.com> Message-ID: <159200727975.20489.8920529729901655345@emeril.freedesktop.org> == Series Details == Series: drm/i915: Update bw_buddy pagemask table URL : https://patchwork.freedesktop.org/series/78276/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621_full -> Patchwork_17942_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17942_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17942_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17942_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_balancer@bonded-early: - shard-tglb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb7/igt at gem_exec_balancer@bonded-early.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-tglb6/igt at gem_exec_balancer@bonded-early.html * igt at perf_pmu@busy-check-all at rcs0: - shard-snb: [PASS][3] -> [FAIL][4] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-snb2/igt at perf_pmu@busy-check-all at rcs0.html Known issues ------------ Here are the changes found in Patchwork_17942_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at drm_read@short-buffer-wakeup: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +9 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at drm_read@short-buffer-wakeup.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl7/igt at drm_read@short-buffer-wakeup.html * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-kbl3/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-apl: [PASS][9] -> [FAIL][10] ([i915#1930]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl1/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-glk5/igt at gem_exec_schedule@smoketest-all.html * igt at gem_mmap@bad-size: - shard-snb: [PASS][13] -> [TIMEOUT][14] ([i915#1958]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_mmap@bad-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-snb2/igt at gem_mmap@bad-size.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl8/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html * igt at kms_cursor_legacy@all-pipes-torture-bo: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#128]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb3/igt at kms_cursor_legacy@all-pipes-torture-bo.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-tglb5/igt at kms_cursor_legacy@all-pipes-torture-bo.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl10/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl7/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@plain-flip-ts-check at b-edp1: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#1928]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt at kms_flip@plain-flip-ts-check at b-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl8/igt at kms_flip@plain-flip-ts-check at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-farfromfence: - shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#402]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb3/igt at kms_frontbuffer_tracking@fbc-farfromfence.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-tglb5/igt at kms_frontbuffer_tracking@fbc-farfromfence.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_basic: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb2/igt at kms_psr@psr2_basic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-iclb3/igt at kms_psr@psr2_basic.html * igt at kms_universal_plane@disable-primary-vs-flip-pipe-c: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +8 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl2/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html * igt at kms_vblank@pipe-c-wait-forked-hang: - shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_vblank@pipe-c-wait-forked-hang.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl4/igt at kms_vblank@pipe-c-wait-forked-hang.html * igt at perf_pmu@busy-check-all at vcs0: - shard-snb: [PASS][35] -> [INCOMPLETE][36] ([i915#82]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at vcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-snb2/igt at perf_pmu@busy-check-all at vcs0.html #### Possible fixes #### * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [DMESG-WARN][37] ([i915#402]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_selftest@perf at request: - shard-tglb: [DMESG-FAIL][39] ([i915#1823]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt at i915_selftest@perf at request.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-tglb8/igt at i915_selftest@perf at request.html * igt at kms_big_fb@linear-8bpp-rotate-0: - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_big_fb@linear-8bpp-rotate-0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl7/igt at kms_big_fb@linear-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-256x85-random: - shard-kbl: [DMESG-WARN][43] ([i915#93] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_cursor_crc@pipe-b-cursor-256x85-random.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-kbl6/igt at kms_cursor_crc@pipe-b-cursor-256x85-random.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl8/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +7 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl6/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl5/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-hsw: [DMESG-WARN][49] ([i915#128]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw4/igt at kms_cursor_legacy@pipe-c-torture-bo.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-hsw1/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1: - shard-hsw: [INCOMPLETE][51] ([i915#61]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw1/igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-hsw4/igt at kms_flip@2x-flip-vs-suspend-interruptible at bc-vga1-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +11 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-apl: [DMESG-WARN][55] ([i915#95]) -> [PASS][56] +11 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt: - shard-tglb: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl8/igt at kms_hdr@bpc-switch-dpms.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][63] ([i915#69]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-skl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb7/igt at kms_psr@psr2_primary_mmap_cpu.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][67] ([i915#1542]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at perf@blocking-parameterized.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-iclb5/igt at perf@blocking-parameterized.html #### Warnings #### * igt at gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: [SKIP][69] ([fdo#109271] / [i915#1099]) -> [INCOMPLETE][70] ([i915#82]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_ctx_persistence@legacy-engines-mixed-process.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-snb2/igt at gem_ctx_persistence@legacy-engines-mixed-process.html * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][71] ([i915#1930]) -> [TIMEOUT][72] ([i915#1958]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][73] ([i915#468]) -> [FAIL][74] ([i915#454]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-tglb1/igt at i915_pm_dc@dc6-dpms.html * igt at kms_content_protection@atomic: - shard-apl: [DMESG-FAIL][75] ([fdo#110321]) -> [FAIL][76] ([fdo#110321] / [fdo#110336]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_content_protection@atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl4/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-apl: [TIMEOUT][77] ([i915#1319] / [i915#1635]) -> [DMESG-FAIL][78] ([fdo#110321] / [i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl8/igt at kms_content_protection@atomic-dpms.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_content_protection@lic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl8/igt at kms_content_protection@lic.html - shard-kbl: [TIMEOUT][81] ([i915#1319]) -> [DMESG-FAIL][82] ([fdo#110321] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl3/igt at kms_content_protection@lic.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-kbl2/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][83] ([i915#1319]) -> [TIMEOUT][84] ([i915#1319] / [i915#1958]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl1/igt at kms_content_protection@srm.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-kbl4/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][85] ([fdo#110321]) -> [TIMEOUT][86] ([i915#1319] / [i915#1635]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_content_protection@srm.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl7/igt at kms_content_protection@srm.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding: - shard-kbl: [DMESG-WARN][87] ([i915#93] / [i915#95]) -> [DMESG-FAIL][88] ([i915#54] / [i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][89] ([i915#180] / [i915#95]) -> [DMESG-WARN][90] ([i915#95]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt: - shard-snb: [SKIP][91] ([fdo#109271]) -> [TIMEOUT][92] ([i915#1958]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/shard-snb2/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17942 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17942: d2b1478a5a609fd6f1ee0711cad56b2a67d4708d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17942/index.html From andi at etezian.org Fri Jun 12 23:05:07 2020 From: andi at etezian.org (Andi Shyti) Date: Sat, 13 Jun 2020 02:05:07 +0300 Subject: [Intel-gfx] [PATCH 05/28] drm/i915/selftests: Trim execlists runtime In-Reply-To: <20200607222108.14401-5-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-5-chris@chris-wilson.co.uk> Message-ID: <20200612230507.GA35541@jack.zhora.eu> Hi Chris, On Sun, Jun 07, 2020 at 11:20:45PM +0100, Chris Wilson wrote: > Reduce the smoke depth by trimming the number of contexts, repetitions > and wait times. This is in preparation for a less greedy scheduler that > tries to be fair across contexts, resulting in a great many more context > switches. A thousand context switches may be 50-100ms, causing us to > timeout as the HW is not fast enough to complete the deep smoketests. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> looks all right to me: Reviewed-by: Andi Shyti <andi.shyti at intel.com> Andi From patchwork at emeril.freedesktop.org Sat Jun 13 00:24:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 13 Jun 2020 00:24:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/8=5D_drm/atomic-helper=3A_reset_vblank_o?= =?utf-8?q?n_crtc_reset_=28rev2=29?= In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <159200785064.20489.16775138176975621511@emeril.freedesktop.org> == Series Details == Series: series starting with [1/8] drm/atomic-helper: reset vblank on crtc reset (rev2) URL : https://patchwork.freedesktop.org/series/78268/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621_full -> Patchwork_17943_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17943_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17943_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17943_full: ### IGT changes ### #### Possible regressions #### * igt at perf_pmu@busy-check-all at rcs0: - shard-snb: [PASS][1] -> [FAIL][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-snb6/igt at perf_pmu@busy-check-all at rcs0.html New tests --------- New tests have been introduced between CI_DRM_8621_full and Patchwork_17943_full: ### New IGT tests (1) ### * igt at gem_exec_reloc@basic-spin-others: - Statuses : - Exec time: [None] s Known issues ------------ Here are the changes found in Patchwork_17943_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#198]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#1930]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-glk8/igt at gem_exec_schedule@smoketest-all.html * igt at gem_mmap@bad-size: - shard-snb: [PASS][9] -> [TIMEOUT][10] ([i915#1958]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_mmap@bad-size.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-snb6/igt at gem_mmap@bad-size.html * igt at gem_tiled_partial_pwrite_pread@writes-after-reads: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#95]) +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl4/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl7/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html * igt at i915_module_load@reload: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-tglb8/igt at i915_module_load@reload.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl9/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +6 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][21] -> [FAIL][22] ([IGT#5]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl7/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl8/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-kbl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb2/igt at kms_psr@psr2_sprite_render.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-iclb1/igt at kms_psr@psr2_sprite_render.html * igt at kms_universal_plane@disable-primary-vs-flip-pipe-c: - shard-skl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +8 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl10/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html * igt at perf_pmu@busy-check-all at vcs0: - shard-snb: [PASS][35] -> [INCOMPLETE][36] ([i915#82]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at vcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-snb6/igt at perf_pmu@busy-check-all at vcs0.html #### Possible fixes #### * igt at gem_exec_schedule@implicit-read-write at bcs0: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb1/igt at gem_exec_schedule@implicit-read-write at bcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-snb4/igt at gem_exec_schedule@implicit-read-write at bcs0.html * igt at i915_selftest@perf at request: - shard-tglb: [DMESG-FAIL][39] ([i915#1823]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt at i915_selftest@perf at request.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-tglb3/igt at i915_selftest@perf at request.html * igt at kms_addfb_basic@size-max: - shard-kbl: [DMESG-WARN][41] ([i915#93] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl2/igt at kms_addfb_basic@size-max.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-kbl3/igt at kms_addfb_basic@size-max.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl6/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +4 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl6/igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge.html * igt at kms_cursor_legacy@cursor-vs-flip-atomic-transitions: - shard-apl: [DMESG-WARN][47] ([i915#95]) -> [PASS][48] +20 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl8/igt at kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +11 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-badstride: - shard-glk: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk5/igt at kms_frontbuffer_tracking@fbc-badstride.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-glk4/igt at kms_frontbuffer_tracking@fbc-badstride.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl8/igt at kms_hdr@bpc-switch-dpms.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl3/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][55] ([i915#69]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_dpms: - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at kms_psr@psr2_dpms.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-iclb2/igt at kms_psr@psr2_dpms.html * igt at kms_setmode@basic: - shard-apl: [FAIL][61] ([i915#31]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_setmode@basic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl2/igt at kms_setmode@basic.html - shard-glk: [FAIL][63] ([i915#31]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk9/igt at kms_setmode@basic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-glk5/igt at kms_setmode@basic.html - shard-kbl: [FAIL][65] ([i915#31]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl7/igt at kms_setmode@basic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-kbl1/igt at kms_setmode@basic.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][67] ([i915#1542]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at perf@blocking-parameterized.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-iclb2/igt at perf@blocking-parameterized.html * igt at perf_pmu@module-unload: - shard-tglb: [DMESG-WARN][69] ([i915#402]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at perf_pmu@module-unload.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-tglb7/igt at perf_pmu@module-unload.html #### Warnings #### * igt at gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: [SKIP][71] ([fdo#109271] / [i915#1099]) -> [INCOMPLETE][72] ([i915#82]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_ctx_persistence@legacy-engines-mixed-process.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-snb6/igt at gem_ctx_persistence@legacy-engines-mixed-process.html * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][73] ([i915#1930]) -> [TIMEOUT][74] ([i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][75] ([i915#468]) -> [FAIL][76] ([i915#454]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-tglb6/igt at i915_pm_dc@dc6-dpms.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][77] ([i915#1319] / [i915#1958]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_content_protection@atomic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-kbl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1635]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl8/igt at kms_content_protection@legacy.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl6/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-apl: [TIMEOUT][81] ([i915#1319]) -> [DMESG-FAIL][82] ([fdo#110321] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_content_protection@lic.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl6/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-apl: [DMESG-FAIL][83] ([fdo#110321]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_content_protection@srm.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-apl7/igt at kms_content_protection@srm.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][85] ([fdo#109349]) -> [DMESG-WARN][86] ([i915#1226]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at kms_dp_dsc@basic-dsc-enable-edp.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt: - shard-snb: [SKIP][87] ([fdo#109271]) -> [TIMEOUT][88] ([i915#1958]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/shard-snb6/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17943 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17943: 923b9ca5f747ec1d47686fc47f9c66434763b1ae @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17943/index.html From patchwork at emeril.freedesktop.org Sat Jun 13 00:39:47 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 13 Jun 2020 00:39:47 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgVlJS?= =?utf-8?q?_capable_attach_prop_in_i915=2C_DPCD_helper=2C_VRR_debugfs_=28r?= =?utf-8?q?ev2=29?= In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <159200878774.20490.10217291627825078839@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev2) URL : https://patchwork.freedesktop.org/series/78278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621 -> Patchwork_17946 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17946 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17946, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17946/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17946: ### IGT changes ### #### Possible regressions #### * igt at kms_chamelium@dp-hpd-fast: - fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17946/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html - fi-kbl-7500u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/fi-kbl-7500u/igt at kms_chamelium@dp-hpd-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17946/fi-kbl-7500u/igt at kms_chamelium@dp-hpd-fast.html Known issues ------------ Here are the changes found in Patchwork_17946 that come from known issues: ### IGT changes ### {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 Participating hosts (49 -> 12) ------------------------------ ERROR: It appears as if the changes made in Patchwork_17946 prevented too many machines from booting. Additional (1): fi-tgl-u2 Missing (38): fi-kbl-soraka fi-icl-u2 fi-apl-guc fi-snb-2520m fi-icl-y fi-skl-lmem fi-byt-n2820 fi-icl-guc fi-icl-dsi fi-skl-6600u fi-snb-2600 fi-bxt-dsi fi-bdw-5557u fi-cml-s fi-bsw-n3050 fi-byt-j1900 fi-glk-dsi fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-bsw-nick fi-skl-6700k2 fi-kbl-r fi-ilk-m540 fi-ehl-1 fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-whl-u fi-kbl-x1275 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17946 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17946: bb21c069cdf462d6136836633baa6945a5dafc82 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bb21c069cdf4 drm/i915/dp: Expose connector VRR monitor range via debugfs b0b10c7d0ea5 drm/i915/dp: Attach and set drm connector VRR property 46b7d1d313bd drm/dp: DRM DP helper for reading Ignore MSA from DPCD == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17946/index.html From patchwork at emeril.freedesktop.org Sat Jun 13 01:17:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 13 Jun 2020 01:17:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/execlists=3A_Lift_opportunistic_process=5Fcsb_to_before_e?= =?utf-8?q?ngine_lock?= In-Reply-To: <20200612221113.9129-1-chris@chris-wilson.co.uk> References: <20200612221113.9129-1-chris@chris-wilson.co.uk> Message-ID: <159201105924.20488.1850731907771840583@emeril.freedesktop.org> == Series Details == Series: drm/i915/execlists: Lift opportunistic process_csb to before engine lock URL : https://patchwork.freedesktop.org/series/78277/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8621_full -> Patchwork_17944_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17944_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17944_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17944_full: ### IGT changes ### #### Possible regressions #### * igt at perf_pmu@busy-check-all at rcs0: - shard-snb: [PASS][1] -> [FAIL][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-snb5/igt at perf_pmu@busy-check-all at rcs0.html Known issues ------------ Here are the changes found in Patchwork_17944_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][3] -> [INCOMPLETE][4] ([i915#58] / [k.org#198133]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk2/igt at gem_ctx_persistence@close-replace-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-glk8/igt at gem_ctx_persistence@close-replace-race.html * igt at gem_exec_reloc@basic-concurrent0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#1930]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl7/igt at gem_exec_reloc@basic-concurrent0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl4/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-glk5/igt at gem_exec_schedule@smoketest-all.html * igt at gem_mmap@bad-size: - shard-snb: [PASS][9] -> [TIMEOUT][10] ([i915#1958]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_mmap@bad-size.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-snb5/igt at gem_mmap@bad-size.html * igt at gem_tiled_partial_pwrite_pread@writes-after-reads: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#95]) +14 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl4/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl6/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-kbl6/igt at gem_tiled_partial_pwrite_pread@writes-after-reads.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl7/igt at i915_suspend@forcewake.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-kbl4/igt at i915_suspend@forcewake.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk9/igt at kms_big_fb@linear-64bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl7/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-128x42-onscreen.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-hsw: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-hsw6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_cursor_legacy@flip-vs-cursor-legacy: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#402]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-tglb5/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html * igt at kms_flip@2x-flip-vs-expired-vblank at ac-hdmi-a1-hdmi-a2: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#79]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-glk1/igt at kms_flip@2x-flip-vs-expired-vblank at ac-hdmi-a1-hdmi-a2.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank at ac-hdmi-a1-hdmi-a2.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +3 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-iclb2/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_basic: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb2/igt at kms_psr@psr2_basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-iclb6/igt at kms_psr@psr2_basic.html * igt at kms_universal_plane@disable-primary-vs-flip-pipe-c: - shard-skl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) +6 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl9/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-skl6/igt at kms_universal_plane@disable-primary-vs-flip-pipe-c.html * igt at perf_pmu@busy-check-all at vcs0: - shard-snb: [PASS][39] -> [INCOMPLETE][40] ([i915#82]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at perf_pmu@busy-check-all at vcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-snb5/igt at perf_pmu@busy-check-all at vcs0.html #### Possible fixes #### * igt at gem_exec_schedule@implicit-read-write at bcs0: - shard-snb: [INCOMPLETE][41] ([i915#82]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb1/igt at gem_exec_schedule@implicit-read-write at bcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-snb5/igt at gem_exec_schedule@implicit-read-write at bcs0.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [DMESG-WARN][43] ([i915#402]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-tglb8/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_selftest@perf at request: - shard-tglb: [DMESG-FAIL][45] ([i915#1823]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb5/igt at i915_selftest@perf at request.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-tglb1/igt at i915_selftest@perf at request.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-apl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl2/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +5 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl6/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-skl10/igt at kms_cursor_edge_walk@pipe-b-64x64-right-edge.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-hsw: [DMESG-WARN][51] ([i915#128]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-hsw4/igt at kms_cursor_legacy@pipe-c-torture-bo.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-hsw2/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu: - shard-apl: [DMESG-WARN][53] ([i915#95]) -> [PASS][54] +18 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt: - shard-tglb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +10 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-kbl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][59] ([i915#69]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb3/igt at kms_psr@psr2_primary_page_flip.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][65] ([i915#1542]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-iclb8/igt at perf@blocking-parameterized.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-iclb6/igt at perf@blocking-parameterized.html #### Warnings #### * igt at gem_ctx_persistence@legacy-engines-mixed-process: - shard-snb: [SKIP][67] ([fdo#109271] / [i915#1099]) -> [INCOMPLETE][68] ([i915#82]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_ctx_persistence@legacy-engines-mixed-process.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-snb5/igt at gem_ctx_persistence@legacy-engines-mixed-process.html * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][71] ([i915#468]) -> [FAIL][72] ([i915#454]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-tglb5/igt at i915_pm_dc@dc6-dpms.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][73] ([i915#1319] / [i915#1958]) -> [TIMEOUT][74] ([i915#1319]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_content_protection@atomic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-kbl7/igt at kms_content_protection@atomic.html - shard-apl: [DMESG-FAIL][75] ([fdo#110321]) -> [FAIL][76] ([fdo#110321] / [fdo#110336]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl2/igt at kms_content_protection@atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl6/igt at kms_content_protection@atomic.html * igt at kms_content_protection@legacy: - shard-apl: [TIMEOUT][77] ([i915#1319]) -> [TIMEOUT][78] ([i915#1319] / [i915#1635]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl8/igt at kms_content_protection@legacy.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl2/igt at kms_content_protection@legacy.html * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][79] ([i915#1319]) -> [DMESG-FAIL][80] ([fdo#110321] / [i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl3/igt at kms_content_protection@lic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-kbl2/igt at kms_content_protection@lic.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][81] ([i915#1319]) -> [FAIL][82] ([fdo#110321]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl1/igt at kms_content_protection@srm.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-kbl2/igt at kms_content_protection@srm.html - shard-apl: [DMESG-FAIL][83] ([fdo#110321]) -> [TIMEOUT][84] ([i915#1319] / [i915#1635]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl3/igt at kms_content_protection@srm.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl2/igt at kms_content_protection@srm.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding: - shard-kbl: [DMESG-WARN][85] ([i915#93] / [i915#95]) -> [DMESG-FAIL][86] ([i915#54] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-apl: [DMESG-WARN][87] ([i915#180] / [i915#95]) -> [DMESG-WARN][88] ([i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-apl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-apl8/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt: - shard-snb: [SKIP][89] ([fdo#109271]) -> [TIMEOUT][90] ([i915#1958]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8621/shard-snb5/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/shard-snb5/igt at kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321 [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8621 -> Patchwork_17944 CI-20190529: 20190529 CI_DRM_8621: acd803311fbd1e6adc38d10ca382a60c6c190be9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5708: f66c71e29de50bae880bc81ceb0517d4e3e2dfd8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17944: b65fd8af838773f4a38ad5d968db1c90258c113a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17944/index.html From lkp at intel.com Sat Jun 13 02:00:06 2020 From: lkp at intel.com (kernel test robot) Date: Sat, 13 Jun 2020 10:00:06 +0800 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <20200612230444.10121-4-manasi.d.navare@intel.com> References: <20200612230444.10121-4-manasi.d.navare@intel.com> Message-ID: <202006130928.jVl18CFK%lkp@intel.com> Hi Manasi, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next linus/master next-20200612] [cannot apply to tegra-drm/drm/tegra/for-next drm/drm-next v5.7] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Manasi-Navare/VRR-capable-attach-prop-in-i915-DPCD-helper-VRR-debugfs/20200613-070517 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-rhel (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): # save the attached .config to linux build tree make W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All error/warnings (new ones prefixed by >>, old ones prefixed by <<): drivers/gpu/drm/i915/display/intel_display_debugfs.c: In function 'intel_connector_debugfs_add': >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2235:2: warning: this 'if' clause does not guard... [-Wmisleading-indentation] 2235 | if (INTEL_GEN(dev_priv) >= 10 && | ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c:2241:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if' 2241 | if (INTEL_GEN(dev_priv) >= 12) | ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c: At top level: >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2247:2: error: expected identifier or '(' before 'if' 2247 | if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) || | ^~ >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2257:2: error: expected identifier or '(' before 'return' 2257 | return 0; | ^~~~~~ >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2258:1: error: expected identifier or '(' before '}' token 2258 | } | ^ drivers/gpu/drm/i915/display/intel_display_debugfs.c: In function 'intel_connector_debugfs_add': >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2244:2: warning: control reaches end of non-void function [-Wreturn-type] 2244 | } | ^ In file included from include/drm/drm_debugfs.h:36, from drivers/gpu/drm/i915/display/intel_display_debugfs.c:6: At top level: drivers/gpu/drm/i915/display/intel_display_debugfs.c:2081:23: warning: 'i915_lpsp_capability_fops' defined but not used [-Wunused-const-variable=] 2081 | DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); | ^~~~~~~~~~~~~~~~~~~~ include/linux/seq_file.h:154:37: note: in definition of macro 'DEFINE_SHOW_ATTRIBUTE' 154 | static const struct file_operations __name ## _fops = { | ^~~~~~ vim +2247 drivers/gpu/drm/i915/display/intel_display_debugfs.c 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2202 926b005cd8c4e3 Jani Nikula 2020-02-11 2203 /** 926b005cd8c4e3 Jani Nikula 2020-02-11 2204 * intel_connector_debugfs_add - add i915 specific connector debugfs files 926b005cd8c4e3 Jani Nikula 2020-02-11 2205 * @connector: pointer to a registered drm_connector 926b005cd8c4e3 Jani Nikula 2020-02-11 2206 * 926b005cd8c4e3 Jani Nikula 2020-02-11 2207 * Cleanup will be done by drm_connector_unregister() through a call to 926b005cd8c4e3 Jani Nikula 2020-02-11 2208 * drm_debugfs_connector_remove(). 926b005cd8c4e3 Jani Nikula 2020-02-11 2209 * 926b005cd8c4e3 Jani Nikula 2020-02-11 2210 * Returns 0 on success, negative error codes on error. 926b005cd8c4e3 Jani Nikula 2020-02-11 2211 */ 926b005cd8c4e3 Jani Nikula 2020-02-11 2212 int intel_connector_debugfs_add(struct drm_connector *connector) 926b005cd8c4e3 Jani Nikula 2020-02-11 2213 { 926b005cd8c4e3 Jani Nikula 2020-02-11 2214 struct dentry *root = connector->debugfs_entry; 926b005cd8c4e3 Jani Nikula 2020-02-11 2215 struct drm_i915_private *dev_priv = to_i915(connector->dev); 926b005cd8c4e3 Jani Nikula 2020-02-11 2216 926b005cd8c4e3 Jani Nikula 2020-02-11 2217 /* The connector must have been registered beforehands. */ 926b005cd8c4e3 Jani Nikula 2020-02-11 2218 if (!root) 926b005cd8c4e3 Jani Nikula 2020-02-11 2219 return -ENODEV; 926b005cd8c4e3 Jani Nikula 2020-02-11 2220 926b005cd8c4e3 Jani Nikula 2020-02-11 2221 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2222 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2223 connector, &i915_panel_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2224 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2225 connector, &i915_psr_sink_status_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2226 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2227 926b005cd8c4e3 Jani Nikula 2020-02-11 2228 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 926b005cd8c4e3 Jani Nikula 2020-02-11 2229 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 926b005cd8c4e3 Jani Nikula 2020-02-11 2230 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2231 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2232 connector, &i915_hdcp_sink_capability_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2233 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2234 926b005cd8c4e3 Jani Nikula 2020-02-11 @2235 if (INTEL_GEN(dev_priv) >= 10 && 926b005cd8c4e3 Jani Nikula 2020-02-11 2236 (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 926b005cd8c4e3 Jani Nikula 2020-02-11 2237 connector->connector_type == DRM_MODE_CONNECTOR_eDP)) 926b005cd8c4e3 Jani Nikula 2020-02-11 2238 debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2239 connector, &i915_dsc_fec_support_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2240 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 @2241 if (INTEL_GEN(dev_priv) >= 12) 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2242 debugfs_create_file("vrr_range", S_IRUGO, 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2243 root, connector, &vrr_range_fops); 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 @2244 } 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2245 8806211fe7b306 Anshuman Gupta 2020-04-15 2246 /* Legacy panels doesn't lpsp on any platform */ 8806211fe7b306 Anshuman Gupta 2020-04-15 @2247 if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) || 8806211fe7b306 Anshuman Gupta 2020-04-15 2248 IS_BROADWELL(dev_priv)) && 8806211fe7b306 Anshuman Gupta 2020-04-15 2249 (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 8806211fe7b306 Anshuman Gupta 2020-04-15 2250 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 8806211fe7b306 Anshuman Gupta 2020-04-15 2251 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 8806211fe7b306 Anshuman Gupta 2020-04-15 2252 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 8806211fe7b306 Anshuman Gupta 2020-04-15 2253 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)) 8806211fe7b306 Anshuman Gupta 2020-04-15 2254 debugfs_create_file("i915_lpsp_capability", 0444, root, 8806211fe7b306 Anshuman Gupta 2020-04-15 2255 connector, &i915_lpsp_capability_fops); 8806211fe7b306 Anshuman Gupta 2020-04-15 2256 926b005cd8c4e3 Jani Nikula 2020-02-11 @2257 return 0; 926b005cd8c4e3 Jani Nikula 2020-02-11 @2258 } :::::: The code at line 2247 was first introduced by commit :::::: 8806211fe7b30696c1fcae54b73c94abfdf55893 drm/i915: Add i915_lpsp_capability debugfs :::::: TO: Anshuman Gupta <anshuman.gupta at intel.com> :::::: CC: Uma Shankar <uma.shankar at intel.com> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 44816 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200613/e90ffb96/attachment-0001.gz> From lkp at intel.com Sat Jun 13 05:41:01 2020 From: lkp at intel.com (kernel test robot) Date: Sat, 13 Jun 2020 13:41:01 +0800 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <20200612230444.10121-4-manasi.d.navare@intel.com> References: <20200612230444.10121-4-manasi.d.navare@intel.com> Message-ID: <202006131356.BmeTo4Rt%lkp@intel.com> Hi Manasi, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip drm-exynos/exynos-drm-next linus/master next-20200612] [cannot apply to tegra-drm/drm/tegra/for-next drm/drm-next v5.7] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Manasi-Navare/VRR-capable-attach-prop-in-i915-DPCD-helper-VRR-debugfs/20200613-070517 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-a014-20200613 (attached as .config) compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu2) 7.5.0 reproduce (this is a W=1 build): # save the attached .config to linux build tree make W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): drivers/gpu/drm/i915/display/intel_display_debugfs.c: In function 'intel_connector_debugfs_add': >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2235:2: error: this 'if' clause does not guard... [-Werror=misleading-indentation] if (INTEL_GEN(dev_priv) >= 10 && ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c:2241:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if' if (INTEL_GEN(dev_priv) >= 12) ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c: At top level: drivers/gpu/drm/i915/display/intel_display_debugfs.c:2247:2: error: expected identifier or '(' before 'if' if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) || ^~ drivers/gpu/drm/i915/display/intel_display_debugfs.c:2257:2: error: expected identifier or '(' before 'return' return 0; ^~~~~~ drivers/gpu/drm/i915/display/intel_display_debugfs.c:2258:1: error: expected identifier or '(' before '}' token } ^ drivers/gpu/drm/i915/display/intel_display_debugfs.c: In function 'intel_connector_debugfs_add': drivers/gpu/drm/i915/display/intel_display_debugfs.c:2244:2: error: control reaches end of non-void function [-Werror=return-type] } ^ In file included from include/drm/drm_debugfs.h:36:0, from drivers/gpu/drm/i915/display/intel_display_debugfs.c:6: At top level: >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2081:23: error: 'i915_lpsp_capability_fops' defined but not used [-Werror=unused-const-variable=] DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); ^ include/linux/seq_file.h:154:37: note: in definition of macro 'DEFINE_SHOW_ATTRIBUTE' static const struct file_operations __name ## _fops = { ^~~~~~ cc1: all warnings being treated as errors vim +/if +2235 drivers/gpu/drm/i915/display/intel_display_debugfs.c 926b005cd8c4e3 Jani Nikula 2020-02-11 2040 8806211fe7b306 Anshuman Gupta 2020-04-15 2041 #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \ 8806211fe7b306 Anshuman Gupta 2020-04-15 2042 seq_puts(m, "LPSP: incapable\n")) 8806211fe7b306 Anshuman Gupta 2020-04-15 2043 8806211fe7b306 Anshuman Gupta 2020-04-15 2044 static int i915_lpsp_capability_show(struct seq_file *m, void *data) 8806211fe7b306 Anshuman Gupta 2020-04-15 2045 { 8806211fe7b306 Anshuman Gupta 2020-04-15 2046 struct drm_connector *connector = m->private; 8806211fe7b306 Anshuman Gupta 2020-04-15 2047 struct intel_encoder *encoder = 8806211fe7b306 Anshuman Gupta 2020-04-15 2048 intel_attached_encoder(to_intel_connector(connector)); 8806211fe7b306 Anshuman Gupta 2020-04-15 2049 struct drm_i915_private *i915 = to_i915(connector->dev); 8806211fe7b306 Anshuman Gupta 2020-04-15 2050 8806211fe7b306 Anshuman Gupta 2020-04-15 2051 if (connector->status != connector_status_connected) 8806211fe7b306 Anshuman Gupta 2020-04-15 2052 return -ENODEV; 8806211fe7b306 Anshuman Gupta 2020-04-15 2053 8806211fe7b306 Anshuman Gupta 2020-04-15 2054 switch (INTEL_GEN(i915)) { 8806211fe7b306 Anshuman Gupta 2020-04-15 2055 case 12: 8806211fe7b306 Anshuman Gupta 2020-04-15 2056 /* 8806211fe7b306 Anshuman Gupta 2020-04-15 2057 * Actually TGL can drive LPSP on port till DDI_C 8806211fe7b306 Anshuman Gupta 2020-04-15 2058 * but there is no physical connected DDI_C on TGL sku's, 8806211fe7b306 Anshuman Gupta 2020-04-15 2059 * even driver is not initilizing DDI_C port for gen12. 8806211fe7b306 Anshuman Gupta 2020-04-15 2060 */ 8806211fe7b306 Anshuman Gupta 2020-04-15 2061 LPSP_CAPABLE(encoder->port <= PORT_B); 8806211fe7b306 Anshuman Gupta 2020-04-15 2062 break; 8806211fe7b306 Anshuman Gupta 2020-04-15 2063 case 11: 8806211fe7b306 Anshuman Gupta 2020-04-15 2064 LPSP_CAPABLE(connector->connector_type == DRM_MODE_CONNECTOR_DSI || 8806211fe7b306 Anshuman Gupta 2020-04-15 2065 connector->connector_type == DRM_MODE_CONNECTOR_eDP); 8806211fe7b306 Anshuman Gupta 2020-04-15 2066 break; 8806211fe7b306 Anshuman Gupta 2020-04-15 2067 case 10: 8806211fe7b306 Anshuman Gupta 2020-04-15 2068 case 9: 8806211fe7b306 Anshuman Gupta 2020-04-15 2069 LPSP_CAPABLE(encoder->port == PORT_A && 8806211fe7b306 Anshuman Gupta 2020-04-15 2070 (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 8806211fe7b306 Anshuman Gupta 2020-04-15 2071 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 8806211fe7b306 Anshuman Gupta 2020-04-15 2072 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)); 8806211fe7b306 Anshuman Gupta 2020-04-15 2073 break; 8806211fe7b306 Anshuman Gupta 2020-04-15 2074 default: 8806211fe7b306 Anshuman Gupta 2020-04-15 2075 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 8806211fe7b306 Anshuman Gupta 2020-04-15 2076 LPSP_CAPABLE(connector->connector_type == DRM_MODE_CONNECTOR_eDP); 8806211fe7b306 Anshuman Gupta 2020-04-15 2077 } 8806211fe7b306 Anshuman Gupta 2020-04-15 2078 8806211fe7b306 Anshuman Gupta 2020-04-15 2079 return 0; 8806211fe7b306 Anshuman Gupta 2020-04-15 2080 } 8806211fe7b306 Anshuman Gupta 2020-04-15 @2081 DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); 8806211fe7b306 Anshuman Gupta 2020-04-15 2082 926b005cd8c4e3 Jani Nikula 2020-02-11 2083 static int i915_dsc_fec_support_show(struct seq_file *m, void *data) 926b005cd8c4e3 Jani Nikula 2020-02-11 2084 { 926b005cd8c4e3 Jani Nikula 2020-02-11 2085 struct drm_connector *connector = m->private; 926b005cd8c4e3 Jani Nikula 2020-02-11 2086 struct drm_device *dev = connector->dev; 926b005cd8c4e3 Jani Nikula 2020-02-11 2087 struct drm_crtc *crtc; 926b005cd8c4e3 Jani Nikula 2020-02-11 2088 struct intel_dp *intel_dp; 926b005cd8c4e3 Jani Nikula 2020-02-11 2089 struct drm_modeset_acquire_ctx ctx; 926b005cd8c4e3 Jani Nikula 2020-02-11 2090 struct intel_crtc_state *crtc_state = NULL; 926b005cd8c4e3 Jani Nikula 2020-02-11 2091 int ret = 0; 926b005cd8c4e3 Jani Nikula 2020-02-11 2092 bool try_again = false; 926b005cd8c4e3 Jani Nikula 2020-02-11 2093 926b005cd8c4e3 Jani Nikula 2020-02-11 2094 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 926b005cd8c4e3 Jani Nikula 2020-02-11 2095 926b005cd8c4e3 Jani Nikula 2020-02-11 2096 do { 926b005cd8c4e3 Jani Nikula 2020-02-11 2097 try_again = false; 926b005cd8c4e3 Jani Nikula 2020-02-11 2098 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, 926b005cd8c4e3 Jani Nikula 2020-02-11 2099 &ctx); 926b005cd8c4e3 Jani Nikula 2020-02-11 2100 if (ret) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2101 if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2102 try_again = true; 926b005cd8c4e3 Jani Nikula 2020-02-11 2103 continue; 926b005cd8c4e3 Jani Nikula 2020-02-11 2104 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2105 break; 926b005cd8c4e3 Jani Nikula 2020-02-11 2106 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2107 crtc = connector->state->crtc; 926b005cd8c4e3 Jani Nikula 2020-02-11 2108 if (connector->status != connector_status_connected || !crtc) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2109 ret = -ENODEV; 926b005cd8c4e3 Jani Nikula 2020-02-11 2110 break; 926b005cd8c4e3 Jani Nikula 2020-02-11 2111 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2112 ret = drm_modeset_lock(&crtc->mutex, &ctx); 926b005cd8c4e3 Jani Nikula 2020-02-11 2113 if (ret == -EDEADLK) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2114 ret = drm_modeset_backoff(&ctx); 926b005cd8c4e3 Jani Nikula 2020-02-11 2115 if (!ret) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2116 try_again = true; 926b005cd8c4e3 Jani Nikula 2020-02-11 2117 continue; 926b005cd8c4e3 Jani Nikula 2020-02-11 2118 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2119 break; 926b005cd8c4e3 Jani Nikula 2020-02-11 2120 } else if (ret) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2121 break; 926b005cd8c4e3 Jani Nikula 2020-02-11 2122 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2123 intel_dp = intel_attached_dp(to_intel_connector(connector)); 926b005cd8c4e3 Jani Nikula 2020-02-11 2124 crtc_state = to_intel_crtc_state(crtc->state); 926b005cd8c4e3 Jani Nikula 2020-02-11 2125 seq_printf(m, "DSC_Enabled: %s\n", 926b005cd8c4e3 Jani Nikula 2020-02-11 2126 yesno(crtc_state->dsc.compression_enable)); 926b005cd8c4e3 Jani Nikula 2020-02-11 2127 seq_printf(m, "DSC_Sink_Support: %s\n", 926b005cd8c4e3 Jani Nikula 2020-02-11 2128 yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); 926b005cd8c4e3 Jani Nikula 2020-02-11 2129 seq_printf(m, "Force_DSC_Enable: %s\n", 926b005cd8c4e3 Jani Nikula 2020-02-11 2130 yesno(intel_dp->force_dsc_en)); 926b005cd8c4e3 Jani Nikula 2020-02-11 2131 if (!intel_dp_is_edp(intel_dp)) 926b005cd8c4e3 Jani Nikula 2020-02-11 2132 seq_printf(m, "FEC_Sink_Support: %s\n", 926b005cd8c4e3 Jani Nikula 2020-02-11 2133 yesno(drm_dp_sink_supports_fec(intel_dp->fec_capable))); 926b005cd8c4e3 Jani Nikula 2020-02-11 2134 } while (try_again); 926b005cd8c4e3 Jani Nikula 2020-02-11 2135 926b005cd8c4e3 Jani Nikula 2020-02-11 2136 drm_modeset_drop_locks(&ctx); 926b005cd8c4e3 Jani Nikula 2020-02-11 2137 drm_modeset_acquire_fini(&ctx); 926b005cd8c4e3 Jani Nikula 2020-02-11 2138 926b005cd8c4e3 Jani Nikula 2020-02-11 2139 return ret; 926b005cd8c4e3 Jani Nikula 2020-02-11 2140 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2141 926b005cd8c4e3 Jani Nikula 2020-02-11 2142 static ssize_t i915_dsc_fec_support_write(struct file *file, 926b005cd8c4e3 Jani Nikula 2020-02-11 2143 const char __user *ubuf, 926b005cd8c4e3 Jani Nikula 2020-02-11 2144 size_t len, loff_t *offp) 926b005cd8c4e3 Jani Nikula 2020-02-11 2145 { 926b005cd8c4e3 Jani Nikula 2020-02-11 2146 bool dsc_enable = false; 926b005cd8c4e3 Jani Nikula 2020-02-11 2147 int ret; 926b005cd8c4e3 Jani Nikula 2020-02-11 2148 struct drm_connector *connector = 926b005cd8c4e3 Jani Nikula 2020-02-11 2149 ((struct seq_file *)file->private_data)->private; 926b005cd8c4e3 Jani Nikula 2020-02-11 2150 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); 926b005cd8c4e3 Jani Nikula 2020-02-11 2151 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 926b005cd8c4e3 Jani Nikula 2020-02-11 2152 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 926b005cd8c4e3 Jani Nikula 2020-02-11 2153 926b005cd8c4e3 Jani Nikula 2020-02-11 2154 if (len == 0) 926b005cd8c4e3 Jani Nikula 2020-02-11 2155 return 0; 926b005cd8c4e3 Jani Nikula 2020-02-11 2156 926b005cd8c4e3 Jani Nikula 2020-02-11 2157 drm_dbg(&i915->drm, 926b005cd8c4e3 Jani Nikula 2020-02-11 2158 "Copied %zu bytes from user to force DSC\n", len); 926b005cd8c4e3 Jani Nikula 2020-02-11 2159 926b005cd8c4e3 Jani Nikula 2020-02-11 2160 ret = kstrtobool_from_user(ubuf, len, &dsc_enable); 926b005cd8c4e3 Jani Nikula 2020-02-11 2161 if (ret < 0) 926b005cd8c4e3 Jani Nikula 2020-02-11 2162 return ret; 926b005cd8c4e3 Jani Nikula 2020-02-11 2163 926b005cd8c4e3 Jani Nikula 2020-02-11 2164 drm_dbg(&i915->drm, "Got %s for DSC Enable\n", 926b005cd8c4e3 Jani Nikula 2020-02-11 2165 (dsc_enable) ? "true" : "false"); 926b005cd8c4e3 Jani Nikula 2020-02-11 2166 intel_dp->force_dsc_en = dsc_enable; 926b005cd8c4e3 Jani Nikula 2020-02-11 2167 926b005cd8c4e3 Jani Nikula 2020-02-11 2168 *offp += len; 926b005cd8c4e3 Jani Nikula 2020-02-11 2169 return len; 926b005cd8c4e3 Jani Nikula 2020-02-11 2170 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2171 926b005cd8c4e3 Jani Nikula 2020-02-11 2172 static int i915_dsc_fec_support_open(struct inode *inode, 926b005cd8c4e3 Jani Nikula 2020-02-11 2173 struct file *file) 926b005cd8c4e3 Jani Nikula 2020-02-11 2174 { 926b005cd8c4e3 Jani Nikula 2020-02-11 2175 return single_open(file, i915_dsc_fec_support_show, 926b005cd8c4e3 Jani Nikula 2020-02-11 2176 inode->i_private); 926b005cd8c4e3 Jani Nikula 2020-02-11 2177 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2178 926b005cd8c4e3 Jani Nikula 2020-02-11 2179 static const struct file_operations i915_dsc_fec_support_fops = { 926b005cd8c4e3 Jani Nikula 2020-02-11 2180 .owner = THIS_MODULE, 926b005cd8c4e3 Jani Nikula 2020-02-11 2181 .open = i915_dsc_fec_support_open, 926b005cd8c4e3 Jani Nikula 2020-02-11 2182 .read = seq_read, 926b005cd8c4e3 Jani Nikula 2020-02-11 2183 .llseek = seq_lseek, 926b005cd8c4e3 Jani Nikula 2020-02-11 2184 .release = single_release, 926b005cd8c4e3 Jani Nikula 2020-02-11 2185 .write = i915_dsc_fec_support_write 926b005cd8c4e3 Jani Nikula 2020-02-11 2186 }; 926b005cd8c4e3 Jani Nikula 2020-02-11 2187 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2188 static int vrr_range_show(struct seq_file *m, void *data) 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2189 { 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2190 struct drm_connector *connector = m->private; 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2191 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2192 if (connector->status != connector_status_connected) 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2193 return -ENODEV; 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2194 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2195 seq_printf(m, "Vrr_capable: %s\n", yesno(intel_dp_is_vrr_capable(connector))); 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2196 seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2197 seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2198 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2199 return 0; 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2200 } 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2201 DEFINE_SHOW_ATTRIBUTE(vrr_range); 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2202 926b005cd8c4e3 Jani Nikula 2020-02-11 2203 /** 926b005cd8c4e3 Jani Nikula 2020-02-11 2204 * intel_connector_debugfs_add - add i915 specific connector debugfs files 926b005cd8c4e3 Jani Nikula 2020-02-11 2205 * @connector: pointer to a registered drm_connector 926b005cd8c4e3 Jani Nikula 2020-02-11 2206 * 926b005cd8c4e3 Jani Nikula 2020-02-11 2207 * Cleanup will be done by drm_connector_unregister() through a call to 926b005cd8c4e3 Jani Nikula 2020-02-11 2208 * drm_debugfs_connector_remove(). 926b005cd8c4e3 Jani Nikula 2020-02-11 2209 * 926b005cd8c4e3 Jani Nikula 2020-02-11 2210 * Returns 0 on success, negative error codes on error. 926b005cd8c4e3 Jani Nikula 2020-02-11 2211 */ 926b005cd8c4e3 Jani Nikula 2020-02-11 2212 int intel_connector_debugfs_add(struct drm_connector *connector) 926b005cd8c4e3 Jani Nikula 2020-02-11 2213 { 926b005cd8c4e3 Jani Nikula 2020-02-11 2214 struct dentry *root = connector->debugfs_entry; 926b005cd8c4e3 Jani Nikula 2020-02-11 2215 struct drm_i915_private *dev_priv = to_i915(connector->dev); 926b005cd8c4e3 Jani Nikula 2020-02-11 2216 926b005cd8c4e3 Jani Nikula 2020-02-11 2217 /* The connector must have been registered beforehands. */ 926b005cd8c4e3 Jani Nikula 2020-02-11 2218 if (!root) 926b005cd8c4e3 Jani Nikula 2020-02-11 2219 return -ENODEV; 926b005cd8c4e3 Jani Nikula 2020-02-11 2220 926b005cd8c4e3 Jani Nikula 2020-02-11 2221 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2222 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2223 connector, &i915_panel_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2224 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2225 connector, &i915_psr_sink_status_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2226 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2227 926b005cd8c4e3 Jani Nikula 2020-02-11 2228 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 926b005cd8c4e3 Jani Nikula 2020-02-11 2229 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 926b005cd8c4e3 Jani Nikula 2020-02-11 2230 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2231 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2232 connector, &i915_hdcp_sink_capability_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2233 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2234 926b005cd8c4e3 Jani Nikula 2020-02-11 @2235 if (INTEL_GEN(dev_priv) >= 10 && :::::: The code at line 2235 was first introduced by commit :::::: 926b005cd8c4e325ab918edea0fbdd1d25d1ba28 drm/i915: split out display debugfs to a separate file :::::: TO: Jani Nikula <jani.nikula at intel.com> :::::: CC: Jani Nikula <jani.nikula at intel.com> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 31500 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200613/670ee10a/attachment-0001.gz> From mika.kuoppala at linux.intel.com Sat Jun 13 08:44:39 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Sat, 13 Jun 2020 11:44:39 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <159199981892.2981.2735577690762279899@build.alporthouse.com> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> <20200612123949.7093-1-chris@chris-wilson.co.uk> <87ftb0rlcx.fsf@gaia.fi.intel.com> <159199981892.2981.2735577690762279899@build.alporthouse.com> Message-ID: <87d063s6bs.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Quoting Mika Kuoppala (2020-06-12 23:05:18) >> Chris Wilson <chris at chris-wilson.co.uk> writes: >> >> > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a >> > subsequent read from e.g. the sampler can bypass the store and read the >> > stale value from memory. This is a serious issue when we are using MI >> > stores to rewrite the batches for relocation, as it means that the batch >> > is reading from random user/kernel memory. While it is particularly >> > sensitive [and detectable] for relocations, reading stale data at any >> > time is a worry. >> > >> > Having started with a small number of delaying stores and doubling until >> > no more incoherency was seen over a few hours (with and without >> > background memory pressure), 32 was the magic number. >> > >> > v2: Follow more closer with the gen5 w/a and include some >> > post-invalidate flushes as well. >> > >> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 >> > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") >> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> >> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> >> > --- >> > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++-------------- >> > 1 file changed, 25 insertions(+), 36 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c >> > index 3fb0dc1fb910..5400d657f334 100644 >> > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c >> > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c >> > @@ -13,28 +13,25 @@ >> > >> > int gen2_emit_flush(struct i915_request *rq, u32 mode) >> > { >> > - unsigned int num_store_dw; >> > + unsigned int num_store_dw = 12; >> > u32 cmd, *cs; >> > >> > cmd = MI_FLUSH; >> > - num_store_dw = 0; >> > if (mode & EMIT_INVALIDATE) >> > cmd |= MI_READ_FLUSH; >> > - if (mode & EMIT_FLUSH) >> > - num_store_dw = 4; >> > >> > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); >> > + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); >> > if (IS_ERR(cs)) >> > return PTR_ERR(cs); >> > >> > *cs++ = cmd; >> > while (num_store_dw--) { >> > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; >> > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, >> > - INTEL_GT_SCRATCH_FIELD_DEFAULT); >> > - *cs++ = 0; >> > + *cs++ = MI_STORE_DWORD_INDEX; >> > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); >> > + *cs++ = rq->fence.seqno - 1; >> > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; >> > } >> > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; >> > + *cs++ = cmd; >> > >> > intel_ring_advance(rq, cs); >> > >> > @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) >> > return 0; >> > } >> > >> > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) >> > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, >> > + int flush, int post) >> > { >> > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); >> > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); >> > >> > *cs++ = MI_FLUSH; >> > >> > - *cs++ = MI_STORE_DWORD_INDEX; >> > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; >> > - *cs++ = rq->fence.seqno; >> > - >> > - *cs++ = MI_USER_INTERRUPT; >> >> How can you throw the interrupt part out? > > Diff being confusing. gen3_emit_breadcrumb and gen5_emit_breadcrumb > merged together. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> From chris at chris-wilson.co.uk Sat Jun 13 09:17:09 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sat, 13 Jun 2020 10:17:09 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Flush gen3 relocs harder, again In-Reply-To: <87d063s6bs.fsf@gaia.fi.intel.com> References: <20200611160529.9558-1-chris@chris-wilson.co.uk> <20200612123949.7093-1-chris@chris-wilson.co.uk> <87ftb0rlcx.fsf@gaia.fi.intel.com> <159199981892.2981.2735577690762279899@build.alporthouse.com> <87d063s6bs.fsf@gaia.fi.intel.com> Message-ID: <159203982908.2981.13254194538799867604@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-13 09:44:39) > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > Quoting Mika Kuoppala (2020-06-12 23:05:18) > >> Chris Wilson <chris at chris-wilson.co.uk> writes: > >> > >> > gen3 does not fully flush MI stores to memory on MI_FLUSH, such that a > >> > subsequent read from e.g. the sampler can bypass the store and read the > >> > stale value from memory. This is a serious issue when we are using MI > >> > stores to rewrite the batches for relocation, as it means that the batch > >> > is reading from random user/kernel memory. While it is particularly > >> > sensitive [and detectable] for relocations, reading stale data at any > >> > time is a worry. > >> > > >> > Having started with a small number of delaying stores and doubling until > >> > no more incoherency was seen over a few hours (with and without > >> > background memory pressure), 32 was the magic number. > >> > > >> > v2: Follow more closer with the gen5 w/a and include some > >> > post-invalidate flushes as well. > >> > > >> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2018 > >> > References: a889580c087a ("drm/i915: Flush GPU relocs harder for gen3") > >> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > >> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > >> > --- > >> > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 61 ++++++++++-------------- > >> > 1 file changed, 25 insertions(+), 36 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > >> > index 3fb0dc1fb910..5400d657f334 100644 > >> > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > >> > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > >> > @@ -13,28 +13,25 @@ > >> > > >> > int gen2_emit_flush(struct i915_request *rq, u32 mode) > >> > { > >> > - unsigned int num_store_dw; > >> > + unsigned int num_store_dw = 12; > >> > u32 cmd, *cs; > >> > > >> > cmd = MI_FLUSH; > >> > - num_store_dw = 0; > >> > if (mode & EMIT_INVALIDATE) > >> > cmd |= MI_READ_FLUSH; > >> > - if (mode & EMIT_FLUSH) > >> > - num_store_dw = 4; > >> > > >> > - cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); > >> > + cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); > >> > if (IS_ERR(cs)) > >> > return PTR_ERR(cs); > >> > > >> > *cs++ = cmd; > >> > while (num_store_dw--) { > >> > - *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; > >> > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > >> > - INTEL_GT_SCRATCH_FIELD_DEFAULT); > >> > - *cs++ = 0; > >> > + *cs++ = MI_STORE_DWORD_INDEX; > >> > + *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); > >> > + *cs++ = rq->fence.seqno - 1; > >> > + *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > >> > } > >> > - *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; > >> > + *cs++ = cmd; > >> > > >> > intel_ring_advance(rq, cs); > >> > > >> > @@ -142,38 +139,21 @@ int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode) > >> > return 0; > >> > } > >> > > >> > -u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs) > >> > +static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs, > >> > + int flush, int post) > >> > { > >> > GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma); > >> > GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); > >> > > >> > *cs++ = MI_FLUSH; > >> > > >> > - *cs++ = MI_STORE_DWORD_INDEX; > >> > - *cs++ = I915_GEM_HWS_SEQNO_ADDR; > >> > - *cs++ = rq->fence.seqno; > >> > - > >> > - *cs++ = MI_USER_INTERRUPT; > >> > >> How can you throw the interrupt part out? > > > > Diff being confusing. gen3_emit_breadcrumb and gen5_emit_breadcrumb > > merged together. > > Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> It failed eventually, so unfortunately it's still just paper. However increasing the MTBF by a few orders of magnitude should be enough to stop CI complaining on every idle run. -Chris From noralf at tronnes.org Sat Jun 13 13:42:29 2020 From: noralf at tronnes.org (=?UTF-8?Q?Noralf_Tr=c3=b8nnes?=) Date: Sat, 13 Jun 2020 15:42:29 +0200 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <20200612160056.2082681-7-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-7-daniel.vetter@ffwll.ch> Message-ID: <b95e1fa9-36b0-f240-424b-69bb48d5ccb7@tronnes.org> Den 12.06.2020 18.00, skrev Daniel Vetter: > The atomic helpers try really hard to not lose track of things, > duplicating enabled tracking in the driver is at best confusing. > Double-enabling or disabling is a bug in atomic helpers. > > In the fb_dirty function we can just assume that the fb always exists, > simple display pipe helpers guarantee that the crtc is only enabled > together with the output, so we always have a primary plane around. > > Now in the update function we need to be a notch more careful, since > that can also get called when the crtc is off. And we don't want to > upload frames when that's the case, so filter that out too. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Maxime Ripard <mripard at kernel.org> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: David Airlie <airlied at linux.ie> > Cc: Daniel Vetter <daniel at ffwll.ch> > Cc: David Lechner <david at lechnology.com> > --- Thanks for fixing this. Reviewed-by: Noralf Tr?nnes <noralf at tronnes.org> From noralf at tronnes.org Sat Jun 13 13:43:23 2020 From: noralf at tronnes.org (=?UTF-8?Q?Noralf_Tr=c3=b8nnes?=) Date: Sat, 13 Jun 2020 15:43:23 +0200 Subject: [Intel-gfx] [PATCH 8/8] drm/tiny/repaper: Drop edp->enabled In-Reply-To: <20200612160056.2082681-8-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-8-daniel.vetter@ffwll.ch> Message-ID: <bc85bee0-9edf-7e24-9a6f-0a9ce5153fd8@tronnes.org> Den 12.06.2020 18.00, skrev Daniel Vetter: > Same patch as the mipi-dbi one, atomic tracks this for us already, we > just have to check the right thing. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: "Noralf Tr?nnes" <noralf at tronnes.org> > --- Reviewed-by: Noralf Tr?nnes <noralf at tronnes.org> From david at lechnology.com Sat Jun 13 18:47:47 2020 From: david at lechnology.com (David Lechner) Date: Sat, 13 Jun 2020 13:47:47 -0500 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <20200612160056.2082681-7-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-7-daniel.vetter@ffwll.ch> Message-ID: <eb6ffd18-8f2d-3d48-a72e-44bf4e1c8512@lechnology.com> On 6/12/20 11:00 AM, Daniel Vetter wrote: > The atomic helpers try really hard to not lose track of things, > duplicating enabled tracking in the driver is at best confusing. > Double-enabling or disabling is a bug in atomic helpers. > > In the fb_dirty function we can just assume that the fb always exists, > simple display pipe helpers guarantee that the crtc is only enabled > together with the output, so we always have a primary plane around. > > Now in the update function we need to be a notch more careful, since > that can also get called when the crtc is off. And we don't want to > upload frames when that's the case, so filter that out too. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Maxime Ripard <mripard at kernel.org> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: David Airlie <airlied at linux.ie> > Cc: Daniel Vetter <daniel at ffwll.ch> > Cc: David Lechner <david at lechnology.com> > --- Acked-by: David Lechner <david at lechnology.com> From anshuman.gupta at intel.com Mon Jun 15 04:29:27 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Mon, 15 Jun 2020 09:59:27 +0530 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add support for considering HDCP ver requested via debugfs In-Reply-To: <20200608100103.19472-2-ankit.k.nautiyal@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> <20200608100103.19472-2-ankit.k.nautiyal@intel.com> Message-ID: <20200615042926.GC14085@intel.com> On 2020-06-08 at 15:31:02 +0530, Ankit Nautiyal wrote: > For testing and debugging each HDCP version separately, a debugfs > entry for requesting a specific version is required. The version > requested via debugfs needs to be stored in hdcp structure. This can > then be considered while enabling HDCP, provided the platform and the > display supports the requested version. > > This patch adds the support for storing the version requested as a 32bit > flag. It also adds a helper function to check if a version is requested. > > If a specific HDCP version is requested through the debugfs, the driver > chooses that version, instead of policy of choosing the highest HDCP > version supported. > > v2: Initialize debugfs_ver_request flag with 0. (Jani Nikula) > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com> > --- > .../gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++ > drivers/gpu/drm/i915/display/intel_hdcp.c | 16 ++++++++++++++-- > 2 files changed, 24 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 9488449e4b94..cfa641c70717 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -408,6 +408,16 @@ struct intel_hdcp { > * Hence caching the transcoder here. > */ > enum transcoder cpu_transcoder; > + > + /* > + * HDCP version requested from debugfs i915_hdcp_ver_request. > + * Kernel will read these bits and entertain the request, as per > + * the HDCP capability of the panel and platform. > + */ > +#define HDCP_VERSION_1_4 0x01 > +#define HDCP_VERSION_2_2 0x02 > +#define HDCP_VERSION_MASK 0x03 > + u32 debugfs_ver_request; > }; > > struct intel_connector { > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 2cbc4619b4ce..a21ea9c2e9a7 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -1977,6 +1977,8 @@ int intel_hdcp_init(struct intel_connector *connector, > if (!shim) > return -EINVAL; > > + hdcp->debugfs_ver_request = 0; > + > if (is_hdcp2_supported(dev_priv)) > intel_hdcp2_init(connector, shim); > > @@ -1998,6 +2000,14 @@ int intel_hdcp_init(struct intel_connector *connector, > return 0; > } > > +static bool hdcp_debugfs_requested(struct intel_hdcp *hdcp, u32 hdcp_version) > +{ > + if (!hdcp->debugfs_ver_request) > + return true; > + > + return hdcp->debugfs_ver_request & hdcp_version ? true : false; > +} > + > int intel_hdcp_enable(struct intel_connector *connector, > enum transcoder cpu_transcoder, u8 content_type) > { > @@ -2023,7 +2033,8 @@ int intel_hdcp_enable(struct intel_connector *connector, > * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup > * is capable of HDCP2.2, it is preferred to use HDCP2.2. > */ > - if (intel_hdcp2_capable(connector)) { > + if (hdcp_debugfs_requested(hdcp, HDCP_VERSION_2_2) && > + intel_hdcp2_capable(connector)) { > ret = _intel_hdcp2_enable(connector); > if (!ret) > check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS; > @@ -2033,7 +2044,8 @@ int intel_hdcp_enable(struct intel_connector *connector, > * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will > * be attempted. > */ > - if (ret && intel_hdcp_capable(connector) && > + if (ret && hdcp_debugfs_requested(hdcp, HDCP_VERSION_1_4) && IMHO there is no case when both version HDCP 2.2 and HDCP 1.4 version will be set, i believe for IGT if HDCP 2.2 fails and version is HDCP 2.2 it should have returen from above, no need to check a ret value and HDCP 1.4 version. Could we simplify conditions here. Thanks, Anshuman Gupta. > + intel_hdcp_capable(connector) && > hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { > ret = _intel_hdcp_enable(connector); > } > -- > 2.17.1 > From anshuman.gupta at intel.com Mon Jun 15 04:45:43 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Mon, 15 Jun 2020 10:15:43 +0530 Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add a new debugfs to request HDCP version In-Reply-To: <20200608100103.19472-3-ankit.k.nautiyal@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> <20200608100103.19472-3-ankit.k.nautiyal@intel.com> Message-ID: <20200615044542.GD14085@intel.com> On 2020-06-08 at 15:31:03 +0530, Ankit Nautiyal wrote: > As per the current HDCP design, the driver selects the highest > version of HDCP that can be used to satisfy the content-protection > requirements of the user. Due to this, the content-protection > tests cannot test a lower version of HDCP, if the platform and the > display panel, both support higher HDCP version. > > To provide some support for testing and debugging, a per-connector > debugfs is required to set the HDCP version via debugfs that the > kernel can consider, while enabling HDCP. > > This patch adds a new debugfs entry for each connector that supports > HDCP. For enforcing a particular HDCP version for a connector, the user > can write into the debugfs for that connector. IMHO this doesn't feel like a debugfs per connector, even if it is a global singleton resource for all connectors, i don't see any problem in that, may be a global debugfs would make sense here ? > > v2: As suggested by Jani Nikula: > -used kstrtouint_from_user() to directly read as uint from user buffer. > -used 32 bit flag instead of 64 bit for hdcp_ver flag. > -removed unnecessary prints and fixed other minor formatting issues. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com> > --- > .../drm/i915/display/intel_display_debugfs.c | 68 +++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 70525623bcdf..c01653d412e7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -2185,6 +2185,72 @@ static const struct file_operations i915_dsc_fec_support_fops = { > .write = i915_dsc_fec_support_write > }; > > +static int i915_hdcp_ver_request_show(struct seq_file *m, void *data) > +{ > + struct drm_connector *connector = m->private; > + struct intel_connector *intel_connector = to_intel_connector(connector); > + u32 hdcp_ver_flag; > + > + if (connector->status != connector_status_connected) > + return -ENODEV; > + > + /* HDCP is supported by connector */ > + if (!intel_connector->hdcp.shim) > + return -EINVAL; > + > + hdcp_ver_flag = intel_connector->hdcp.debugfs_ver_request; > + seq_printf(m, "HDCP_VER_FLAGS: %u\n", hdcp_ver_flag); > + > + return 0; > +} > + > +static int i915_hdcp_ver_request_open(struct inode *inode, > + struct file *file) > +{ > + return single_open(file, i915_hdcp_ver_request_show, > + inode->i_private); > +} > + > +static ssize_t i915_hdcp_ver_request_write(struct file *file, > + const char __user *ubuf, > + size_t len, loff_t *offp) > +{ > + unsigned int hdcp_ver = 0; > + int ret; > + struct drm_connector *connector = > + ((struct seq_file *)file->private_data)->private; > + struct intel_connector *intel_connector = to_intel_connector(connector); > + struct intel_hdcp *hdcp = &intel_connector->hdcp; > + > + if (!hdcp->shim) > + return -EINVAL; > + > + if (len == 0) > + return 0; > + > + ret = kstrtouint_from_user(ubuf, len, 0, &hdcp_ver); > + if (ret < 0) > + return ret; > + > + if (hdcp_ver > HDCP_VERSION_MASK) > + return -EINVAL; > + > + hdcp->debugfs_ver_request = hdcp_ver; A lockless assignment, this would probably not scale. Could u please add some comment here for current IGT need this is ok, but for any concurrent usgaes proper locking is required. Thanks, Anshuman > + > + *offp += len; > + > + return len; > +} > + > +static const struct file_operations i915_hdcp_ver_request_fops = { > + .owner = THIS_MODULE, > + .open = i915_hdcp_ver_request_open, > + .read = seq_read, > + .llseek = seq_lseek, > + .release = single_release, > + .write = i915_hdcp_ver_request_write > +}; > + > /** > * intel_connector_debugfs_add - add i915 specific connector debugfs files > * @connector: pointer to a registered drm_connector > @@ -2215,6 +2281,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector) > connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { > debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, > connector, &i915_hdcp_sink_capability_fops); > + debugfs_create_file("i915_hdcp_version_request", 0444, root, > + connector, &i915_hdcp_ver_request_fops); > } > > if (INTEL_GEN(dev_priv) >= 10 && > -- > 2.17.1 > From imre.deak at intel.com Mon Jun 15 06:59:01 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 15 Jun 2020 09:59:01 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/icl+: Fix hotplug interrupt disabling after storm detection In-Reply-To: <20200612131848.GH6112@intel.com> References: <20200612121731.19596-1-imre.deak@intel.com> <20200612131848.GH6112@intel.com> Message-ID: <20200615065901.GA16626@ideak-desk.fi.intel.com> On Fri, Jun 12, 2020 at 04:18:48PM +0300, Ville Syrj?l? wrote: > On Fri, Jun 12, 2020 at 03:17:31PM +0300, Imre Deak wrote: > > Atm, hotplug interrupts on TypeC ports are left enabled after detecting > > an interrupt storm, fix this. > > > > Reported-by: Kunal Joshi <kunal1.joshi at intel.com> > > References: https://gitlab.freedesktop.org/drm/intel/-/issues/351 > > Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/1964 > > Cc: Kunal Joshi <kunal1.joshi at intel.com> > > Cc: stable at vger.kernel.org > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/i915/i915_irq.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 8e823ba25f5f..710224d930c5 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -3132,6 +3132,7 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) > > > > val = I915_READ(GEN11_DE_HPD_IMR); > > val &= ~hotplug_irqs; > > + val |= ~enabled_irqs & hotplug_irqs; > > I915_WRITE(GEN11_DE_HPD_IMR, val); > > POSTING_READ(GEN11_DE_HPD_IMR); > > Wondering if we should add a function for this just for consistency > with all the other platforms. Yes makes sense, or even abstract the hpd interrupt enabling using the hpd pin -> interrupt flag table. I think we could even extend that table with the pulse detection bits and register addresses. I'll check if something like this would work for all platforms. > Alhthough we don't strictly need one since we have no other users of > this register. So maybe not. > > Anyways, patch is > Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Thanks, pushed. > > > > > -- > > 2.23.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From tzimmermann at suse.de Mon Jun 15 08:23:34 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Mon, 15 Jun 2020 10:23:34 +0200 Subject: [Intel-gfx] [PATCH 9/9] drm/shmem-helpers: Simplify dma-buf importing In-Reply-To: <20200511093554.211493-10-daniel.vetter@ffwll.ch> References: <20200511093554.211493-1-daniel.vetter@ffwll.ch> <20200511093554.211493-10-daniel.vetter@ffwll.ch> Message-ID: <b29c8109-30e5-83a4-0f98-ddf7637d5436@suse.de> Hi Daniel this patch causes a segmentation fault. Am 11.05.20 um 11:35 schrieb Daniel Vetter: > - Ditch the ->pages array > - Make it a private gem bo, which means no shmem object, which means > fireworks if anyone calls drm_gem_object_get_pages. But we've just > made sure that's all covered. > > Cc: Gerd Hoffmann <kraxel at redhat.com> > Cc: Rob Herring <robh at kernel.org> > Cc: Noralf Tr?nnes <noralf at tronnes.org> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > drivers/gpu/drm/drm_gem_shmem_helper.c | 59 ++++++++++---------------- > 1 file changed, 23 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > index f7011338813e..8c7d4f422b7b 100644 > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > @@ -35,22 +35,12 @@ static const struct drm_gem_object_funcs drm_gem_shmem_funcs = { > .mmap = drm_gem_shmem_mmap, > }; > > -/** > - * drm_gem_shmem_create - Allocate an object with the given size > - * @dev: DRM device > - * @size: Size of the object to allocate > - * > - * This function creates a shmem GEM object. > - * > - * Returns: > - * A struct drm_gem_shmem_object * on success or an ERR_PTR()-encoded negative > - * error code on failure. > - */ > -struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev, size_t size) > +static struct drm_gem_shmem_object * > +__drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private) > { > struct drm_gem_shmem_object *shmem; > struct drm_gem_object *obj; > - int ret; > + int ret = 0; > > size = PAGE_ALIGN(size); > > @@ -64,7 +54,10 @@ struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev, size_t > if (!obj->funcs) > obj->funcs = &drm_gem_shmem_funcs; > > - ret = drm_gem_object_init(dev, obj, size); > + if (private) > + drm_gem_private_object_init(dev, obj, size); This call doesn't set obj->filp, which is dereferenced further below at [1]. This happens from dumb_create(). Best regards Thomas [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/drm_gem_shmem_helper.c?h=v5.8-rc1#n87 > + else > + ret = drm_gem_object_init(dev, obj, size); > if (ret) > goto err_free; > > @@ -96,6 +89,21 @@ struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev, size_t > > return ERR_PTR(ret); > } > +/** > + * drm_gem_shmem_create - Allocate an object with the given size > + * @dev: DRM device > + * @size: Size of the object to allocate > + * > + * This function creates a shmem GEM object. > + * > + * Returns: > + * A struct drm_gem_shmem_object * on success or an ERR_PTR()-encoded negative > + * error code on failure. > + */ > +struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev, size_t size) > +{ > + return __drm_gem_shmem_create(dev, size, false); > +} > EXPORT_SYMBOL_GPL(drm_gem_shmem_create); > > /** > @@ -115,7 +123,6 @@ void drm_gem_shmem_free_object(struct drm_gem_object *obj) > if (obj->import_attach) { > shmem->pages_use_count--; > drm_prime_gem_destroy(obj, shmem->sgt); > - kvfree(shmem->pages); > } else { > if (shmem->sgt) { > dma_unmap_sg(obj->dev->dev, shmem->sgt->sgl, > @@ -371,7 +378,7 @@ drm_gem_shmem_create_with_handle(struct drm_file *file_priv, > struct drm_gem_shmem_object *shmem; > int ret; > > - shmem = drm_gem_shmem_create(dev, size); > + shmem = __drm_gem_shmem_create(dev, size, true); > if (IS_ERR(shmem)) > return shmem; > > @@ -695,36 +702,16 @@ drm_gem_shmem_prime_import_sg_table(struct drm_device *dev, > struct sg_table *sgt) > { > size_t size = PAGE_ALIGN(attach->dmabuf->size); > - size_t npages = size >> PAGE_SHIFT; > struct drm_gem_shmem_object *shmem; > - int ret; > > shmem = drm_gem_shmem_create(dev, size); > if (IS_ERR(shmem)) > return ERR_CAST(shmem); > > - shmem->pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL); > - if (!shmem->pages) { > - ret = -ENOMEM; > - goto err_free_gem; > - } > - > - ret = drm_prime_sg_to_page_addr_arrays(sgt, shmem->pages, NULL, npages); > - if (ret < 0) > - goto err_free_array; > - > shmem->sgt = sgt; > - shmem->pages_use_count = 1; /* Permanently pinned from our point of view */ > > DRM_DEBUG_PRIME("size = %zu\n", size); > > return &shmem->base; > - > -err_free_array: > - kvfree(shmem->pages); > -err_free_gem: > - drm_gem_object_put_unlocked(&shmem->base); > - > - return ERR_PTR(ret); > } > EXPORT_SYMBOL_GPL(drm_gem_shmem_prime_import_sg_table); > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N?rnberg, Germany (HRB 36809, AG N?rnberg) Gesch?ftsf?hrer: Felix Imend?rffer -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200615/94e59bbb/attachment.sig> From ankit.k.nautiyal at intel.com Mon Jun 15 10:06:54 2020 From: ankit.k.nautiyal at intel.com (Nautiyal, Ankit K) Date: Mon, 15 Jun 2020 15:36:54 +0530 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add support for considering HDCP ver requested via debugfs In-Reply-To: <20200615042926.GC14085@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> <20200608100103.19472-2-ankit.k.nautiyal@intel.com> <20200615042926.GC14085@intel.com> Message-ID: <3d842996-5f0a-6a17-8247-42f79dd2786c@intel.com> Hi Anshuman, Thanks for the comments. Please find my response inline: On 6/15/2020 9:59 AM, Anshuman Gupta wrote: > On 2020-06-08 at 15:31:02 +0530, Ankit Nautiyal wrote: >> For testing and debugging each HDCP version separately, a debugfs >> entry for requesting a specific version is required. The version >> requested via debugfs needs to be stored in hdcp structure. This can >> then be considered while enabling HDCP, provided the platform and the >> display supports the requested version. >> >> This patch adds the support for storing the version requested as a 32bit >> flag. It also adds a helper function to check if a version is requested. >> >> If a specific HDCP version is requested through the debugfs, the driver >> chooses that version, instead of policy of choosing the highest HDCP >> version supported. >> >> v2: Initialize debugfs_ver_request flag with 0. (Jani Nikula) >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com> >> --- >> .../gpu/drm/i915/display/intel_display_types.h | 10 ++++++++++ >> drivers/gpu/drm/i915/display/intel_hdcp.c | 16 ++++++++++++++-- >> 2 files changed, 24 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h >> index 9488449e4b94..cfa641c70717 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h >> @@ -408,6 +408,16 @@ struct intel_hdcp { >> * Hence caching the transcoder here. >> */ >> enum transcoder cpu_transcoder; >> + >> + /* >> + * HDCP version requested from debugfs i915_hdcp_ver_request. >> + * Kernel will read these bits and entertain the request, as per >> + * the HDCP capability of the panel and platform. >> + */ >> +#define HDCP_VERSION_1_4 0x01 >> +#define HDCP_VERSION_2_2 0x02 >> +#define HDCP_VERSION_MASK 0x03 >> + u32 debugfs_ver_request; >> }; >> >> struct intel_connector { >> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c >> index 2cbc4619b4ce..a21ea9c2e9a7 100644 >> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c >> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c >> @@ -1977,6 +1977,8 @@ int intel_hdcp_init(struct intel_connector *connector, >> if (!shim) >> return -EINVAL; >> >> + hdcp->debugfs_ver_request = 0; >> + >> if (is_hdcp2_supported(dev_priv)) >> intel_hdcp2_init(connector, shim); >> >> @@ -1998,6 +2000,14 @@ int intel_hdcp_init(struct intel_connector *connector, >> return 0; >> } >> >> +static bool hdcp_debugfs_requested(struct intel_hdcp *hdcp, u32 hdcp_version) >> +{ >> + if (!hdcp->debugfs_ver_request) >> + return true; >> + >> + return hdcp->debugfs_ver_request & hdcp_version ? true : false; >> +} >> + >> int intel_hdcp_enable(struct intel_connector *connector, >> enum transcoder cpu_transcoder, u8 content_type) >> { >> @@ -2023,7 +2033,8 @@ int intel_hdcp_enable(struct intel_connector *connector, >> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup >> * is capable of HDCP2.2, it is preferred to use HDCP2.2. >> */ >> - if (intel_hdcp2_capable(connector)) { >> + if (hdcp_debugfs_requested(hdcp, HDCP_VERSION_2_2) && >> + intel_hdcp2_capable(connector)) { >> ret = _intel_hdcp2_enable(connector); >> if (!ret) >> check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS; >> @@ -2033,7 +2044,8 @@ int intel_hdcp_enable(struct intel_connector *connector, >> * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will >> * be attempted. >> */ >> - if (ret && intel_hdcp_capable(connector) && >> + if (ret && hdcp_debugfs_requested(hdcp, HDCP_VERSION_1_4) && > IMHO there is no case when both version HDCP 2.2 and HDCP 1.4 version > will be set, i believe for IGT if HDCP 2.2 fails and version is HDCP 2.2 > it should have returen from above, no need to check a ret value and > HDCP 1.4 version. Could we simplify conditions here. > Thanks, > Anshuman Gupta. I was trying to have minimum change in the present flow. So I had just added a function hdcp_debugfs_requested(). This will return true if there is no version requested and the flow remains same. In case a specific version is requested say HDCP 2.2, only that version will be chosen. In case the HDCP2.2 fails, the hdcp_debugfs_requested() condition will fail and the flow will skip for HDCP1.4 part. If not like this, we can try to have a separate code-block, for the case where debugfs version is requested, but this will lead to duplication of parts for enabling HDCP2.2/ HDCP1.4. if (hdcp->debugfs_ver_request & HDCP_VERSION_2_2) { /* enable HDCP2.2 */ } else if (hdcp->debugfs_ver_request & HDCP_VERSION_1_4) { /* enable HDCP1.4 */ } else { /* Existing policy of enabling HDCP2.2 if possible, or fall back to HDCP1.4*/ } So to avoid code duplication, IMHO, the current mechanism seems fine. Perhaps the naming of the function hdcp_debugfs_requested can be made better to avoid confusion as it returns true even in case no version is requested. Would it be better to name hdcp_debugfs_allow_version(hdcp, HDCP_VER_#_#) ? Regards, Ankit >> + intel_hdcp_capable(connector) && >> hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { >> ret = _intel_hdcp_enable(connector); >> } >> -- >> 2.17.1 >> From ankit.k.nautiyal at intel.com Mon Jun 15 10:18:25 2020 From: ankit.k.nautiyal at intel.com (Nautiyal, Ankit K) Date: Mon, 15 Jun 2020 15:48:25 +0530 Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add a new debugfs to request HDCP version In-Reply-To: <20200615044542.GD14085@intel.com> References: <20200608100103.19472-1-ankit.k.nautiyal@intel.com> <20200608100103.19472-3-ankit.k.nautiyal@intel.com> <20200615044542.GD14085@intel.com> Message-ID: <88727f19-0c36-39cd-8422-22aca5ad3cff@intel.com> Hi Anshuman, Thanks for the review comments and suggestions. Please find my response inline: On 6/15/2020 10:15 AM, Anshuman Gupta wrote: > On 2020-06-08 at 15:31:03 +0530, Ankit Nautiyal wrote: >> As per the current HDCP design, the driver selects the highest >> version of HDCP that can be used to satisfy the content-protection >> requirements of the user. Due to this, the content-protection >> tests cannot test a lower version of HDCP, if the platform and the >> display panel, both support higher HDCP version. >> >> To provide some support for testing and debugging, a per-connector >> debugfs is required to set the HDCP version via debugfs that the >> kernel can consider, while enabling HDCP. >> >> This patch adds a new debugfs entry for each connector that supports >> HDCP. For enforcing a particular HDCP version for a connector, the user >> can write into the debugfs for that connector. > IMHO this doesn't feel like a debugfs per connector, even if it is a > global singleton resource for all connectors, i don't see any problem in > that, may be a global debugfs would make sense here ? The current solution was inline with the comments in the IGT patch, where the approach for a connector level debugfs was discussed by the community members. But I agree we don't necessarily require per connector debugfs for our use-case here. We can use a global resource for storing the request for HDCP version and use it if it is set, while enabling HDCP. Perhaps will store it in dev_priv, instead of connector->hdcp. I will try that out and send next version. >> v2: As suggested by Jani Nikula: >> -used kstrtouint_from_user() to directly read as uint from user buffer. >> -used 32 bit flag instead of 64 bit for hdcp_ver flag. >> -removed unnecessary prints and fixed other minor formatting issues. >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com> >> --- >> .../drm/i915/display/intel_display_debugfs.c | 68 +++++++++++++++++++ >> 1 file changed, 68 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c >> index 70525623bcdf..c01653d412e7 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c >> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c >> @@ -2185,6 +2185,72 @@ static const struct file_operations i915_dsc_fec_support_fops = { >> .write = i915_dsc_fec_support_write >> }; >> >> +static int i915_hdcp_ver_request_show(struct seq_file *m, void *data) >> +{ >> + struct drm_connector *connector = m->private; >> + struct intel_connector *intel_connector = to_intel_connector(connector); >> + u32 hdcp_ver_flag; >> + >> + if (connector->status != connector_status_connected) >> + return -ENODEV; >> + >> + /* HDCP is supported by connector */ >> + if (!intel_connector->hdcp.shim) >> + return -EINVAL; >> + >> + hdcp_ver_flag = intel_connector->hdcp.debugfs_ver_request; >> + seq_printf(m, "HDCP_VER_FLAGS: %u\n", hdcp_ver_flag); >> + >> + return 0; >> +} >> + >> +static int i915_hdcp_ver_request_open(struct inode *inode, >> + struct file *file) >> +{ >> + return single_open(file, i915_hdcp_ver_request_show, >> + inode->i_private); >> +} >> + >> +static ssize_t i915_hdcp_ver_request_write(struct file *file, >> + const char __user *ubuf, >> + size_t len, loff_t *offp) >> +{ >> + unsigned int hdcp_ver = 0; >> + int ret; >> + struct drm_connector *connector = >> + ((struct seq_file *)file->private_data)->private; >> + struct intel_connector *intel_connector = to_intel_connector(connector); >> + struct intel_hdcp *hdcp = &intel_connector->hdcp; >> + >> + if (!hdcp->shim) >> + return -EINVAL; >> + >> + if (len == 0) >> + return 0; >> + >> + ret = kstrtouint_from_user(ubuf, len, 0, &hdcp_ver); >> + if (ret < 0) >> + return ret; >> + >> + if (hdcp_ver > HDCP_VERSION_MASK) >> + return -EINVAL; >> + >> + hdcp->debugfs_ver_request = hdcp_ver; > A lockless assignment, this would probably not scale. > Could u please add some comment here for current IGT need this is ok, > but for any concurrent usgaes proper locking is required. > Thanks, > Anshuman Agreed. I will add this as a note in comments in next version. Thanks & Regards, Ankit >> + >> + *offp += len; >> + >> + return len; >> +} >> + >> +static const struct file_operations i915_hdcp_ver_request_fops = { >> + .owner = THIS_MODULE, >> + .open = i915_hdcp_ver_request_open, >> + .read = seq_read, >> + .llseek = seq_lseek, >> + .release = single_release, >> + .write = i915_hdcp_ver_request_write >> +}; >> + >> /** >> * intel_connector_debugfs_add - add i915 specific connector debugfs files >> * @connector: pointer to a registered drm_connector >> @@ -2215,6 +2281,8 @@ int intel_connector_debugfs_add(struct drm_connector *connector) >> connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { >> debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, >> connector, &i915_hdcp_sink_capability_fops); >> + debugfs_create_file("i915_hdcp_version_request", 0444, root, >> + connector, &i915_hdcp_ver_request_fops); >> } >> >> if (INTEL_GEN(dev_priv) >= 10 && >> -- >> 2.17.1 >> From chris at chris-wilson.co.uk Mon Jun 15 12:39:11 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:11 +0100 Subject: [Intel-gfx] [PATCH 01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests Message-ID: <20200615123920.17749-1-chris@chris-wilson.co.uk> Since the heartbeat may cause a preemption event, disable it over the preemption suppression tests. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index f651bdf7f191..91543494f595 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2282,7 +2282,7 @@ static int live_suppress_self_preempt(void *arg) if (igt_flush_test(gt->i915)) goto err_wedged; - intel_engine_pm_get(engine); + engine_heartbeat_disable(engine); engine->execlists.preempt_hang.count = 0; rq_a = spinner_create_request(&a.spin, @@ -2290,14 +2290,14 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_a)) { err = PTR_ERR(rq_a); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_a); if (!igt_wait_for_spinner(&a.spin, rq_a)) { pr_err("First client failed to start\n"); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_wedged; } @@ -2309,7 +2309,7 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_b)) { err = PTR_ERR(rq_b); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_b); @@ -2320,7 +2320,7 @@ static int live_suppress_self_preempt(void *arg) if (!igt_wait_for_spinner(&b.spin, rq_b)) { pr_err("Second client failed to start\n"); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_wedged; } @@ -2334,12 +2334,12 @@ static int live_suppress_self_preempt(void *arg) engine->name, engine->execlists.preempt_hang.count, depth); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); err = -EINVAL; goto err_client_b; } - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) goto err_wedged; } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:19 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:19 +0100 Subject: [Intel-gfx] [PATCH 09/10] drm/i915/gt: Decouple inflight virtual engines In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-9-chris@chris-wilson.co.uk> Once a virtual engine has been bound to a sibling, it will remain bound until we finally schedule out the last active request. We can not rebind the context to a new sibling while it is inflight as the context save will conflict, hence we wait. As we cannot then use any other sibliing while the context is inflight, only kick the bound sibling while it inflight and upon scheduling out the kick the rest (so that we can swap engines on timeslicing if the previously bound engine becomes oversubscribed). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +++++++++++++---------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 34a8eadc2de3..4a1e23e51314 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1409,9 +1409,8 @@ execlists_schedule_in(struct i915_request *rq, int idx) static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); - struct i915_request *next = READ_ONCE(ve->request); - if (next == rq || (next && next->execution_mask & ~rq->execution_mask)) + if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); } @@ -1825,18 +1824,14 @@ first_virtual_engine(struct intel_engine_cs *engine) rb_entry(rb, typeof(*ve), nodes[engine->id].rb); struct i915_request *rq = READ_ONCE(ve->request); - if (!rq) { /* lazily cleanup after another engine handled rq */ + /* lazily cleanup after another engine handled rq */ + if (!rq || !virtual_matches(ve, rq, engine)) { rb_erase_cached(rb, &el->virtual); RB_CLEAR_NODE(rb); rb = rb_first_cached(&el->virtual); continue; } - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - return ve; } @@ -5486,7 +5481,6 @@ static void virtual_submission_tasklet(unsigned long data) if (unlikely(!mask)) return; - local_irq_disable(); for (n = 0; n < ve->num_siblings; n++) { struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]); struct ve_node * const node = &ve->nodes[sibling->id]; @@ -5496,20 +5490,19 @@ static void virtual_submission_tasklet(unsigned long data) if (!READ_ONCE(ve->request)) break; /* already handled by a sibling's tasklet */ + spin_lock_irq(&sibling->active.lock); + if (unlikely(!(mask & sibling->mask))) { if (!RB_EMPTY_NODE(&node->rb)) { - spin_lock(&sibling->active.lock); rb_erase_cached(&node->rb, &sibling->execlists.virtual); RB_CLEAR_NODE(&node->rb); - spin_unlock(&sibling->active.lock); } - continue; - } - spin_lock(&sibling->active.lock); + goto unlock_engine; + } - if (!RB_EMPTY_NODE(&node->rb)) { + if (unlikely(!RB_EMPTY_NODE(&node->rb))) { /* * Cheat and avoid rebalancing the tree if we can * reuse this node in situ. @@ -5549,9 +5542,12 @@ static void virtual_submission_tasklet(unsigned long data) if (first && prio > sibling->execlists.queue_priority_hint) tasklet_hi_schedule(&sibling->execlists.tasklet); - spin_unlock(&sibling->active.lock); +unlock_engine: + spin_unlock_irq(&sibling->active.lock); + + if (intel_context_inflight(&ve->context)) + break; } - local_irq_enable(); } static void virtual_submit_request(struct i915_request *rq) -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:14 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:14 +0100 Subject: [Intel-gfx] [PATCH 04/10] drm/i915/execlists: Replace direct submit with direct call to tasklet In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-4-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +++---- drivers/gpu/drm/i915/gt/intel_lrc.c | 78 ++++++++------------ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + 4 files changed, 45 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..c77b3c0d2b3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -210,6 +210,7 @@ int intel_engine_resume(struct intel_engine_cs *engine); int intel_ring_submission_setup(struct intel_engine_cs *engine); +void __intel_engine_stop_cs(struct intel_engine_cs *engine); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 81884303bf6d..667ee52448a0 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,33 +903,34 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +void __intel_engine_stop_cs(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); - int err; + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + intel_uncore_posting_read_fw(uncore, mode); +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + __intel_engine_stop_cs(engine); - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, + if (__intel_wait_for_register_fw(engine->uncore, + RING_MI_MODE(engine->mmio_base), + MODE_IDLE, MODE_IDLE, 1000, stop_timeout(engine), NULL)) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); - err = -ETIMEDOUT; + return -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - - return err; + return 0; } void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..40c5085765da 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2703,16 +2703,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3102,7 +3092,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3112,7 +3102,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3122,16 +3111,17 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); + + if (!engine->execlists.pending[0]) { unsigned long flags; + rcu_read_lock(); /* protect peeking at execlists->active */ spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); + execlists_dequeue(engine); spin_unlock_irqrestore(&engine->active.lock, flags); - - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); + rcu_read_unlock(); } } @@ -3163,26 +3153,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3196,20 +3176,22 @@ static void flush_csb(struct intel_engine_cs *engine) { struct intel_engine_execlists *el = &engine->execlists; - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); + if (!tasklet_trylock(&el->tasklet)) { + tasklet_hi_schedule(&el->tasklet); + return; } + + if (!reset_in_progress(el)) + execlists_submission_tasklet((unsigned long)engine); + + tasklet_unlock(&el->tasklet); } static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); + bool submit = false; /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3224,10 +3206,13 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + submit = submit_queue(engine, request); } spin_unlock_irqrestore(&engine->active.lock, flags); + + if (submit) + flush_csb(engine); } static void __execlists_context_fini(struct intel_context *ce) @@ -4113,7 +4098,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4130,10 +4114,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4147,7 +4127,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) * FIXME: Wa for more modern gens needs to be validated */ ring_set_paused(engine, 1); - intel_engine_stop_cs(engine); + __intel_engine_stop_cs(engine); engine->execlists.reset_ccid = active_ccid(engine); } @@ -4377,12 +4357,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + flush_csb(engine); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 0f1be62cdc6f..1f26db4fc998 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1601,6 +1601,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:15 +0100 Subject: [Intel-gfx] [PATCH 05/10] drm/i915/execlists: Defer schedule_out until after the next dequeue In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-5-chris@chris-wilson.co.uk> Inside schedule_out, we do extra work upon idling the context, such as updating the runtime, kicking off retires, kicking virtual engines. However, if we are in a series of processing single requests per contexts, we may find ourselves scheduling out the context, only to immediately schedule it back in during dequeue. This is just extra work that we can avoid if we keep the context marked as inflight across the dequeue. This becomes more significant later on for minimising virtual engine misses. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++++++++++++++----- 4 files changed, 51 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 4954b0df4864..b63db45bab7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -45,8 +45,8 @@ struct intel_context { struct intel_engine_cs *engine; struct intel_engine_cs *inflight; -#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2) -#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2) +#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 3) +#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 3) struct i915_address_space *vm; struct i915_gem_context __rcu *gem_context; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 667ee52448a0..0e94e52ee760 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -515,6 +515,8 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine) memset(execlists->pending, 0, sizeof(execlists->pending)); execlists->active = memset(execlists->inflight, 0, sizeof(execlists->inflight)); + execlists->inactive = + memset(execlists->post, 0, sizeof(execlists->post)); execlists->queue_priority_hint = INT_MIN; execlists->queue = RB_ROOT_CACHED; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 073c3769e8cc..31cf60cef5a8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -208,6 +208,10 @@ struct intel_engine_execlists { * @active: the currently known context executing on HW */ struct i915_request * const *active; + /** + * @inactive: the current vacancy of completed CS + */ + struct i915_request **inactive; /** * @inflight: the set of contexts submitted and acknowleged by HW * @@ -225,6 +229,15 @@ struct intel_engine_execlists { * preemption or idle-to-active event. */ struct i915_request *pending[EXECLIST_MAX_PORTS + 1]; + /** + * @post: the set of completed context switches + * + * Since we may want to stagger the processing of the CS switches + * with the next submission, so that the context are notionally + * kept in flight across the dequeue, we defer scheduling out of + * the completed context switches. + */ + struct i915_request *post[2 * EXECLIST_MAX_PORTS + 1]; /** * @port_mask: number of execlist ports - 1 diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 40c5085765da..adc14adfa89c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1385,6 +1385,8 @@ __execlists_schedule_in(struct i915_request *rq) execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); + CE_TRACE(ce, "schedule-in, ccid:%x\n", ce->lrc.ccid); + return engine; } @@ -1431,6 +1433,8 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ + CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + /* * If we have just completed this context, the engine may now be * idle and we want to re-enter powersaving. @@ -2055,9 +2059,10 @@ static void set_preempt_timeout(struct intel_engine_cs *engine, active_preempt_timeout(engine, rq)); } -static inline void clear_ports(struct i915_request **ports, int count) +static inline struct i915_request ** +clear_ports(struct i915_request **ports, int count) { - memset_p((void **)ports, NULL, count); + return memset_p((void **)ports, NULL, count); } static void execlists_dequeue(struct intel_engine_cs *engine) @@ -2433,7 +2438,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (!memcmp(active, execlists->pending, (port - execlists->pending + 1) * sizeof(*port))) { do - execlists_schedule_out(fetch_and_zero(port)); + *execlists->inactive++ = *port; while (port-- != execlists->pending); goto skip_submit; @@ -2447,6 +2452,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + execlists->pending[0] = NULL; } } @@ -2456,12 +2462,12 @@ cancel_port_requests(struct intel_engine_execlists * const execlists) struct i915_request * const *port; for (port = execlists->pending; *port; port++) - execlists_schedule_out(*port); + *execlists->inactive++ = *port; clear_ports(execlists->pending, ARRAY_SIZE(execlists->pending)); /* Mark the end of active before we overwrite *active */ for (port = xchg(&execlists->active, execlists->pending); *port; port++) - execlists_schedule_out(*port); + *execlists->inactive++ = *port; clear_ports(execlists->inflight, ARRAY_SIZE(execlists->inflight)); smp_wmb(); /* complete the seqlock for execlists_active() */ @@ -2622,7 +2628,7 @@ static void process_csb(struct intel_engine_cs *engine) /* cancel old inflight, prepare for switch */ trace_ports(execlists, "preempted", old); while (*old) - execlists_schedule_out(*old++); + *execlists->inactive++ = *old++; /* switch pending to inflight */ GEM_BUG_ON(!assert_pending_valid(execlists, "promote")); @@ -2679,7 +2685,7 @@ static void process_csb(struct intel_engine_cs *engine) regs[CTX_RING_TAIL]); } - execlists_schedule_out(*execlists->active++); + *execlists->inactive++ = *execlists->active++; GEM_BUG_ON(execlists->active - execlists->inflight > execlists_num_ports(execlists)); @@ -2703,6 +2709,20 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } +static void post_process_csb(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request **port; + + if (!el->post[0]) + return; + + GEM_BUG_ON(el->post[2 * EXECLIST_MAX_PORTS]); + for (port = el->post; *port; port++) + execlists_schedule_out(*port); + el->inactive = clear_ports(el->post, port - el->post); +} + static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -2971,8 +2991,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->active; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at active:%zd\n", - port - el->active); + "ccid:%x found at active:%zd\n", + ccid, port - el->active); return rq; } } @@ -2980,8 +3000,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->pending; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at pending:%zd\n", - port - el->pending); + "ccid:%x found at pending:%zd\n", + ccid, port - el->pending); return rq; } } @@ -3123,6 +3143,8 @@ static void execlists_submission_tasklet(unsigned long data) spin_unlock_irqrestore(&engine->active.lock, flags); rcu_read_unlock(); } + + post_process_csb(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -4061,8 +4083,6 @@ static void enable_execlists(struct intel_engine_cs *engine) ENGINE_POSTING_READ(engine, RING_HWS_PGA); enable_error_interrupt(engine); - - engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); } static bool unexpected_starting_state(struct intel_engine_cs *engine) @@ -5104,6 +5124,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) else execlists->csb_size = GEN11_CSB_ENTRIES; + engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); if (INTEL_GEN(engine->i915) >= 11) { execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32); execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:16 +0100 Subject: [Intel-gfx] [PATCH 06/10] drm/i915/gt: ce->inflight updates are now serialised In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-6-chris@chris-wilson.co.uk> Since schedule-in and schedule-out are now both always under the tasklet bitlock, we can reduce the individual atomic operations to simple instructions and worry less. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 43 ++++++++++++----------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index adc14adfa89c..8b3959207c02 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1371,7 +1371,7 @@ __execlists_schedule_in(struct i915_request *rq) unsigned int tag = ffs(READ_ONCE(engine->context_tag)); GEM_BUG_ON(tag == 0 || tag >= BITS_PER_LONG); - clear_bit(tag - 1, &engine->context_tag); + __clear_bit(tag - 1, &engine->context_tag); ce->lrc.ccid = tag << (GEN11_SW_CTX_ID_SHIFT - 32); BUILD_BUG_ON(BITS_PER_LONG > GEN12_MAX_CONTEXT_HW_ID); @@ -1399,13 +1399,10 @@ execlists_schedule_in(struct i915_request *rq, int idx) GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine)); trace_i915_request_in(rq, idx); - old = READ_ONCE(ce->inflight); - do { - if (!old) { - WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq)); - break; - } - } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old))); + old = ce->inflight; + if (!old) + old = __execlists_schedule_in(rq); + WRITE_ONCE(ce->inflight, ptr_inc(old)); GEM_BUG_ON(intel_context_inflight(ce) != rq->engine); return i915_request_get(rq); @@ -1420,12 +1417,11 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce) tasklet_hi_schedule(&ve->base.execlists.tasklet); } -static inline void -__execlists_schedule_out(struct i915_request *rq, - struct intel_engine_cs * const engine, - unsigned int ccid) +static inline void __execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; + struct intel_engine_cs * const engine = ce->inflight; + unsigned int ccid; /* * NB process_csb() is not under the engine->active.lock and hence @@ -1433,7 +1429,7 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ - CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + CE_TRACE(ce, "schedule-out, ccid:%x\n", ce->lrc.ccid); /* * If we have just completed this context, the engine may now be @@ -1443,12 +1439,13 @@ __execlists_schedule_out(struct i915_request *rq, i915_request_completed(rq)) intel_engine_add_retire(engine, ce->timeline); + ccid = ce->lrc.ccid; ccid >>= GEN11_SW_CTX_ID_SHIFT - 32; ccid &= GEN12_MAX_CONTEXT_HW_ID; if (ccid < BITS_PER_LONG) { GEM_BUG_ON(ccid == 0); GEM_BUG_ON(test_bit(ccid - 1, &engine->context_tag)); - set_bit(ccid - 1, &engine->context_tag); + __set_bit(ccid - 1, &engine->context_tag); } intel_context_update_runtime(ce); @@ -1469,26 +1466,22 @@ __execlists_schedule_out(struct i915_request *rq, */ if (ce->engine != engine) kick_siblings(rq, ce); - - intel_context_put(ce); } static inline void execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; - struct intel_engine_cs *cur, *old; - u32 ccid; trace_i915_request_out(rq); - ccid = rq->context->lrc.ccid; - old = READ_ONCE(ce->inflight); - do - cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL; - while (!try_cmpxchg(&ce->inflight, &old, cur)); - if (!cur) - __execlists_schedule_out(rq, old, ccid); + GEM_BUG_ON(!ce->inflight); + ce->inflight = ptr_dec(ce->inflight); + if (!intel_context_inflight_count(ce)) { + __execlists_schedule_out(rq); + WRITE_ONCE(ce->inflight, NULL); + intel_context_put(ce); + } i915_request_put(rq); } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:17 +0100 Subject: [Intel-gfx] [PATCH 07/10] drm/i915/gt: Drop atomic for engine->fw_active tracking In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-7-chris@chris-wilson.co.uk> Since schedule-in/out is now entirely serialised by the tasklet bitlock, we do not need to worry about concurrent in/out operations and so reduce the atomic operations to plain instructions. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 0e94e52ee760..c91d18b384e7 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1524,7 +1524,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, drm_printf(m, "\tLatency: %luus\n", ewma__engine_latency_read(&engine->latency)); drm_printf(m, "\tForcewake: %x domains, %d active\n", - engine->fw_domain, atomic_read(&engine->fw_active)); + engine->fw_domain, READ_ONCE(engine->fw_active)); rcu_read_lock(); rq = READ_ONCE(engine->heartbeat.systole); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 31cf60cef5a8..ca124f229f65 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -335,7 +335,7 @@ struct intel_engine_cs { * as possible. */ enum forcewake_domains fw_domain; - atomic_t fw_active; + unsigned int fw_active; unsigned long context_tag; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 8b3959207c02..09ec7242fbcb 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1380,7 +1380,7 @@ __execlists_schedule_in(struct i915_request *rq) ce->lrc.ccid |= engine->execlists.ccid; __intel_gt_pm_get(engine->gt); - if (engine->fw_domain && !atomic_fetch_inc(&engine->fw_active)) + if (engine->fw_domain && !engine->fw_active++) intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); @@ -1451,7 +1451,7 @@ static inline void __execlists_schedule_out(struct i915_request *rq) intel_context_update_runtime(ce); intel_engine_context_out(engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); - if (engine->fw_domain && !atomic_dec_return(&engine->fw_active)) + if (engine->fw_domain && !--engine->fw_active) intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:12 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:12 +0100 Subject: [Intel-gfx] [PATCH 02/10] drm/i915/selftests: Dump engine state and trace upon hanging after reset In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-2-chris@chris-wilson.co.uk> If the engine dies after a reset, and so we fail to submit a request but need to be interrupted by the CI runner, dump the engine state. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 2af66f8ffbd2..0f1be62cdc6f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -499,6 +499,24 @@ static int igt_reset_nop_engine(void *arg) rq = intel_context_create_request(ce); if (IS_ERR(rq)) { + struct drm_printer p = + drm_info_printer(gt->i915->drm.dev); + intel_engine_dump(engine, &p, + "%s(%s): failed to submit request %llx:%lld\n", + __func__, + engine->name, + rq->fence.context, + rq->fence.seqno); + + + GEM_TRACE("%s(%s): failed to submit request %llx:%lld\n", + __func__, engine->name, + rq->fence.context, + rq->fence.seqno); + GEM_TRACE_DUMP(); + + intel_gt_set_wedged(gt); + err = PTR_ERR(rq); break; } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:13 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:13 +0100 Subject: [Intel-gfx] [PATCH 03/10] drm/i915/gt: Add a safety submission flush in the heartbeat In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-3-chris@chris-wilson.co.uk> Just in case everything fails (like for example "missed interrupt syndrome" on Sandybridge), always flush the submission tasklet from the heartbeat. This papers over such issues, but will still appear as a second long glitch, and prevents us from detecting it unless we happen to be performing a timed test. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 19 +++++++------------ .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +++ 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index d613cf31970c..81884303bf6d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1094,19 +1094,14 @@ void intel_engine_flush_submission(struct intel_engine_cs *engine) { struct tasklet_struct *t = &engine->execlists.tasklet; - if (__tasklet_is_scheduled(t)) { - local_bh_disable(); - if (tasklet_trylock(t)) { - /* Must wait for any GPU reset in progress. */ - if (__tasklet_is_enabled(t)) - t->func(t->data); - tasklet_unlock(t); - } - local_bh_enable(); + local_bh_disable(); + if (tasklet_trylock(t)) { + /* Must wait for any GPU reset in progress. */ + if (__tasklet_is_enabled(t)) + t->func(t->data); + tasklet_unlock(t); } - - /* Otherwise flush the tasklet if it was running on another cpu */ - tasklet_unlock_wait(t); + local_bh_enable(); } /** diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index f67ad937eefb..cd20fb549b38 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -65,6 +65,9 @@ static void heartbeat(struct work_struct *wrk) struct intel_context *ce = engine->kernel_context; struct i915_request *rq; + /* Just in case everything has gone horribly wrong, give it a kick */ + intel_engine_flush_submission(engine); + rq = engine->heartbeat.systole; if (rq && i915_request_completed(rq)) { i915_request_put(rq); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:18 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:18 +0100 Subject: [Intel-gfx] [PATCH 08/10] drm/i915/gt: Use virtual_engine during execlists_dequeue In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-8-chris@chris-wilson.co.uk> Rather than going back and forth between the rb_node entry and the virtual_engine type, store the ve local and reuse it. As the container_of conversion from rb_node to virtual_engine requires a variable offset, performing that conversion just once shaves off a bit of code. v2: Keep a single virtual engine lookup, for typical use. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 214 +++++++++++++--------------- 1 file changed, 101 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 09ec7242fbcb..34a8eadc2de3 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -454,7 +454,7 @@ static int queue_prio(const struct intel_engine_execlists *execlists) static inline bool need_preempt(const struct intel_engine_cs *engine, const struct i915_request *rq, - struct rb_node *rb) + struct virtual_engine *ve) { int last_prio; @@ -491,9 +491,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, rq_prio(list_next_entry(rq, sched.link)) > last_prio) return true; - if (rb) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { bool preempt = false; if (engine == ve->siblings[0]) { /* only preempt one sibling */ @@ -1816,6 +1814,35 @@ static bool virtual_matches(const struct virtual_engine *ve, return true; } +static struct virtual_engine * +first_virtual_engine(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists *el = &engine->execlists; + struct rb_node *rb = rb_first_cached(&el->virtual); + + while (rb) { + struct virtual_engine *ve = + rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + struct i915_request *rq = READ_ONCE(ve->request); + + if (!rq) { /* lazily cleanup after another engine handled rq */ + rb_erase_cached(rb, &el->virtual); + RB_CLEAR_NODE(rb); + rb = rb_first_cached(&el->virtual); + continue; + } + + if (!virtual_matches(ve, rq, engine)) { + rb = rb_next(rb); + continue; + } + + return ve; + } + + return NULL; +} + static void virtual_xfer_breadcrumbs(struct virtual_engine *ve) { /* @@ -1900,7 +1927,7 @@ static void defer_active(struct intel_engine_cs *engine) static bool need_timeslice(const struct intel_engine_cs *engine, const struct i915_request *rq, - const struct rb_node *rb) + struct virtual_engine *ve) { int hint; @@ -1909,9 +1936,7 @@ need_timeslice(const struct intel_engine_cs *engine, hint = engine->execlists.queue_priority_hint; - if (rb) { - const struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { const struct intel_engine_cs *inflight = intel_context_inflight(&ve->context); @@ -2063,7 +2088,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = READ_ONCE(execlists->active); + struct virtual_engine *ve = first_virtual_engine(engine); struct i915_request *last; struct rb_node *rb; bool submit = false; @@ -2090,26 +2116,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * and context switches) submission. */ - for (rb = rb_first_cached(&execlists->virtual); rb; ) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); - struct i915_request *rq = READ_ONCE(ve->request); - - if (!rq) { /* lazily cleanup after another engine handled rq */ - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } - - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - - break; - } - /* * If the queue is higher priority than the last * request in the currently active context, submit afresh. @@ -2117,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2131,9 +2134,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * find itself trying to jump back into a context it has just * completed and barf. */ - if ((last = *active)) { - if (need_preempt(engine, last, rb)) { + if (need_preempt(engine, last, ve)) { if (i915_request_completed(last)) { tasklet_hi_schedule(&execlists->tasklet); return; @@ -2164,7 +2166,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) __unwind_incomplete_requests(engine); last = NULL; - } else if (need_timeslice(engine, last, rb) && + } else if (need_timeslice(engine, last, ve) && timeslice_expired(execlists, last)) { if (i915_request_completed(last)) { tasklet_hi_schedule(&execlists->tasklet); @@ -2218,110 +2220,96 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } } - while (rb) { /* XXX virtual is always taking precedence */ - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + while (ve) { /* XXX virtual is always taking precedence */ struct i915_request *rq; spin_lock(&ve->base.active.lock); rq = ve->request; - if (unlikely(!rq)) { /* lost the race to a sibling */ - spin_unlock(&ve->base.active.lock); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } + if (unlikely(!rq)) /* lost the race to a sibling */ + goto unlock; GEM_BUG_ON(rq != ve->request); GEM_BUG_ON(rq->engine != &ve->base); GEM_BUG_ON(rq->context != &ve->context); - if (rq_prio(rq) >= queue_prio(execlists)) { - if (!virtual_matches(ve, rq, engine)) { - spin_unlock(&ve->base.active.lock); - rb = rb_next(rb); - continue; - } + if (unlikely(rq_prio(rq) < queue_prio(execlists))) { + spin_unlock(&ve->base.active.lock); + break; + } - if (last && !can_merge_rq(last, rq)) { - spin_unlock(&ve->base.active.lock); - start_timeslice(engine, rq_prio(rq)); - return; /* leave this for another sibling */ - } + GEM_BUG_ON(!virtual_matches(ve, rq, engine)); - ENGINE_TRACE(engine, - "virtual rq=%llx:%lld%s, new engine? %s\n", - rq->fence.context, - rq->fence.seqno, - i915_request_completed(rq) ? "!" : - i915_request_started(rq) ? "*" : - "", - yesno(engine != ve->siblings[0])); - - WRITE_ONCE(ve->request, NULL); - WRITE_ONCE(ve->base.execlists.queue_priority_hint, - INT_MIN); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); + if (last && !can_merge_rq(last, rq)) { + spin_unlock(&ve->base.active.lock); + start_timeslice(engine, rq_prio(rq)); + return; /* leave this for another sibling */ + } - GEM_BUG_ON(!(rq->execution_mask & engine->mask)); - WRITE_ONCE(rq->engine, engine); + ENGINE_TRACE(engine, + "virtual rq=%llx:%lld%s, new engine? %s\n", + rq->fence.context, + rq->fence.seqno, + i915_request_completed(rq) ? "!" : + i915_request_started(rq) ? "*" : + "", + yesno(engine != ve->siblings[0])); - if (engine != ve->siblings[0]) { - u32 *regs = ve->context.lrc_reg_state; - unsigned int n; + WRITE_ONCE(ve->request, NULL); + WRITE_ONCE(ve->base.execlists.queue_priority_hint, INT_MIN); - GEM_BUG_ON(READ_ONCE(ve->context.inflight)); + rb = &ve->nodes[engine->id].rb; + rb_erase_cached(rb, &execlists->virtual); + RB_CLEAR_NODE(rb); - if (!intel_engine_has_relative_mmio(engine)) - virtual_update_register_offsets(regs, - engine); + GEM_BUG_ON(!(rq->execution_mask & engine->mask)); + WRITE_ONCE(rq->engine, engine); - if (!list_empty(&ve->context.signals)) - virtual_xfer_breadcrumbs(ve); + if (engine != ve->siblings[0]) { + u32 *regs = ve->context.lrc_reg_state; + unsigned int n; - /* - * Move the bound engine to the top of the list - * for future execution. We then kick this - * tasklet first before checking others, so that - * we preferentially reuse this set of bound - * registers. - */ - for (n = 1; n < ve->num_siblings; n++) { - if (ve->siblings[n] == engine) { - swap(ve->siblings[n], - ve->siblings[0]); - break; - } - } + GEM_BUG_ON(READ_ONCE(ve->context.inflight)); - GEM_BUG_ON(ve->siblings[0] != engine); - } + if (!intel_engine_has_relative_mmio(engine)) + virtual_update_register_offsets(regs, engine); - if (__i915_request_submit(rq)) { - submit = true; - last = rq; - } - i915_request_put(rq); + if (!list_empty(&ve->context.signals)) + virtual_xfer_breadcrumbs(ve); /* - * Hmm, we have a bunch of virtual engine requests, - * but the first one was already completed (thanks - * preempt-to-busy!). Keep looking at the veng queue - * until we have no more relevant requests (i.e. - * the normal submit queue has higher priority). + * Move the bound engine to the top of the list for + * future execution. We then kick this tasklet first + * before checking others, so that we preferentially + * reuse this set of bound registers. */ - if (!submit) { - spin_unlock(&ve->base.active.lock); - rb = rb_first_cached(&execlists->virtual); - continue; + for (n = 1; n < ve->num_siblings; n++) { + if (ve->siblings[n] == engine) { + swap(ve->siblings[n], ve->siblings[0]); + break; + } } + + GEM_BUG_ON(ve->siblings[0] != engine); + } + + if (__i915_request_submit(rq)) { + submit = true; + last = rq; } + i915_request_put(rq); +unlock: spin_unlock(&ve->base.active.lock); - break; + + /* + * Hmm, we have a bunch of virtual engine requests, + * but the first one was already completed (thanks + * preempt-to-busy!). Keep looking at the veng queue + * until we have no more relevant requests (i.e. + * the normal submit queue has higher priority). + */ + ve = submit ? NULL : first_virtual_engine(engine); } while ((rb = rb_first_cached(&execlists->queue))) { -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 12:39:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 13:39:20 +0100 Subject: [Intel-gfx] [PATCH 10/10] drm/i915/gt: Resubmit the virtual engine on schedule-out In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <20200615123920.17749-10-chris@chris-wilson.co.uk> Having recognised that we do not change the sibling until we schedule out, we can then defer the decision to resubmit the virtual engine from the unwind of the active queue to scheduling out of the virtual context. By keeping the unwind order intact on the local engine, we can preserve data dependency ordering while doing a preempt-to-busy pass until we have determined the new ELSP. This means that if we try to timeslice between a virtual engine and a data-dependent ordinary request, the pair will maintain their relative ordering and we will avoid the resubmission, cancelling the timeslicing until further change. The dilemma though is that we then may end up in a situation where the 'demotion' of the virtual request to an ordinary request in the engine queue results in filling the ELSP[] with virtual requests instead of spreading the load across the engines. To compensate for this, we mark each virtual request and refuse to resubmit a virtual request in the secondary ELSP slots, thus forcing subsequent virtual requests to be scheduled out after timeslicing. By delaying the decision until we schedule out, we will avoid unnecessary resubmission. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 118 ++++++++++++++++--------- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 2 files changed, 75 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 4a1e23e51314..45029eb86b6e 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1117,53 +1117,23 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) __i915_request_unsubmit(rq); - /* - * Push the request back into the queue for later resubmission. - * If this request is not native to this physical engine (i.e. - * it came from a virtual source), push it back onto the virtual - * engine so that it can be moved across onto another physical - * engine as load dictates. - */ - if (likely(rq->execution_mask == engine->mask)) { - GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); - if (rq_prio(rq) != prio) { - prio = rq_prio(rq); - pl = i915_sched_lookup_priolist(engine, prio); - } - GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - - list_move(&rq->sched.link, pl); - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); + if (rq_prio(rq) != prio) { + prio = rq_prio(rq); + pl = i915_sched_lookup_priolist(engine, prio); + } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - /* Check in case we rollback so far we wrap [size/2] */ - if (intel_ring_direction(rq->ring, - intel_ring_wrap(rq->ring, - rq->tail), - rq->ring->tail) > 0) - rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; + list_move(&rq->sched.link, pl); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); - active = rq; - } else { - struct intel_engine_cs *owner = rq->context->engine; + /* Check in case we rollback so far we wrap [size/2] */ + if (intel_ring_direction(rq->ring, + intel_ring_wrap(rq->ring, rq->tail), + rq->ring->tail) > 0) + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; - /* - * Decouple the virtual breadcrumb before moving it - * back to the virtual engine -- we don't want the - * request to complete in the background and try - * and cancel the breadcrumb on the virtual engine - * (instead of the old engine where it is linked)! - */ - if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &rq->fence.flags)) { - spin_lock_nested(&rq->lock, - SINGLE_DEPTH_NESTING); - i915_request_cancel_breadcrumb(rq); - spin_unlock(&rq->lock); - } - WRITE_ONCE(rq->engine, owner); - owner->submit_request(rq); - active = NULL; - } + active = rq; } return active; @@ -1406,12 +1376,49 @@ execlists_schedule_in(struct i915_request *rq, int idx) return i915_request_get(rq); } +static void +resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve) +{ + struct intel_engine_cs *engine = rq->engine; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + + /* + * Decouple the virtual breadcrumb before moving it back to the virtual + * engine -- we don't want the request to complete in the background + * and then try and cancel the breadcrumb on the virtual engine + * (instead of the old engine where it is linked)! + */ + if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) { + spin_lock_nested(&rq->lock, SINGLE_DEPTH_NESTING); + i915_request_cancel_breadcrumb(rq); + spin_unlock(&rq->lock); + } + + clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + WRITE_ONCE(rq->engine, &ve->base); + ve->base.submit_request(rq); + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); + + /* + * This engine is now too busy to run this virtual request, so + * see if we can find an alternative engine for it to execute on. + * Once a request has become bonded to this engine, we treat it the + * same as other native request. + */ + if (i915_request_in_priority_queue(rq) && + rq->execution_mask != rq->engine->mask) + resubmit_virtual_request(rq, ve); } static inline void __execlists_schedule_out(struct i915_request *rq) @@ -1650,6 +1657,20 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, } sentinel = i915_request_has_sentinel(rq); + /* + * We want virtual requests to only be in the first slot so + * that they are never stuck behind a hog and can be immediately + * transferred onto the next idle engine. + */ + if (rq->execution_mask != engine->mask && + port != execlists->pending) { + GEM_TRACE_ERR("%s: virtual engine:%llx not in prime position[%zd]\n", + engine->name, + ce->timeline->fence_context, + port - execlists->pending); + return false; + } + /* Hold tightly onto the lock to prevent concurrent retires! */ if (!spin_trylock_irqsave(&rq->lock, flags)) continue; @@ -2346,6 +2367,15 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (i915_request_has_sentinel(last)) goto done; + /* + * We avoid submitting virtual requests into + * the secondary ports so that we can migrate + * the request immediately to another engine + * rather than wait for the primary request. + */ + if (rq->execution_mask != engine->mask) + goto done; + /* * If GVT overrides us we only ever submit * port[0], leaving port[1] empty. Note that we diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 91543494f595..a8d62faa3a88 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -4289,7 +4289,7 @@ static int reset_virtual_engine(struct intel_gt *gt, spin_lock_irq(&engine->active.lock); __unwind_incomplete_requests(engine); spin_unlock_irq(&engine->active.lock); - GEM_BUG_ON(rq->engine != ve->engine); + GEM_BUG_ON(rq->engine != engine); /* Reset the engine while keeping our active request on hold */ execlists_hold(engine, rq); -- 2.20.1 From u.kleine-koenig at pengutronix.de Sat Jun 13 20:50:08 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Sat, 13 Jun 2020 22:50:08 +0200 Subject: [Intel-gfx] [PATCH v2 03/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200612115732.GC2428291@smile.fi.intel.com> References: <20200607181840.13536-1-hdegoede@redhat.com> <20200607181840.13536-4-hdegoede@redhat.com> <20200608035023.GZ2428291@smile.fi.intel.com> <90769dc0-3174-195b-34e0-ef4bb9d9b982@redhat.com> <20200611221242.3bjqvnhcwwxaocxy@taurus.defre.kleine-koenig.org> <20200612115732.GC2428291@smile.fi.intel.com> Message-ID: <20200613205008.l2gxw6pm2ywmj3gz@taurus.defre.kleine-koenig.org> Hello Andy, On Fri, Jun 12, 2020 at 02:57:32PM +0300, Andy Shevchenko wrote: > On Fri, Jun 12, 2020 at 12:12:42AM +0200, Uwe Kleine-K?nig wrote: > > I didn't follow the complete discussion but note that the general rule > > is: > > > > round period down to the next possible implementable period > > round duty_cycle down to the next possible implementable duty_cycle > > > > so if a small enough period (and so a small duty_cycle) is requested it > > is expected that duty_cycle will be zero. > > ...which brings me an idea that PWM framework should expose API to get a > capabilities, like DMA Engine has. > > In such capabilities, in particular, caller can get ranges of the correct > frequencies of the underneath hardware. my idea is to introduce a function pwm_round_state() that has a similar semantic to clk_round_rate(). But this is only one of several thoughts I have for the pwm framework. And as there is (AFAIK) no user who would benefit from pwm_round_state() this is further down on my todo list. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200613/680d190f/attachment.sig> From bernard at vivo.com Mon Jun 15 04:38:22 2020 From: bernard at vivo.com (Bernard Zhao) Date: Mon, 15 Jun 2020 12:38:22 +0800 Subject: [Intel-gfx] [PATCH] drm/i915: remove unnecessary conversion to bool Message-ID: <20200615043822.14206-1-bernard@vivo.com> In function perform_bb_shadow, bb->ppgtt is bool, so maybe there is no need to convert the bool condition to bool. This change is to make the code a bit readable. Signed-off-by: Bernard Zhao <bernard at vivo.com> --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 8b87f130f7f1..221eaebfe513 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1880,7 +1880,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) if (!bb) return -ENOMEM; - bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true; + bb->ppgtt = (s->buf_addr_type != GTT_BUFFER); /* the start_offset stores the batch buffer's start gma's * offset relative to page boundary. so for non-privileged batch -- 2.17.1 From chris at chris-wilson.co.uk Mon Jun 15 13:11:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 14:11:20 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Add a safety submission flush in the heartbeat In-Reply-To: <20200615123920.17749-3-chris@chris-wilson.co.uk> References: <20200615123920.17749-3-chris@chris-wilson.co.uk> Message-ID: <20200615131120.18948-1-chris@chris-wilson.co.uk> Just in case everything fails (like for example "missed interrupt syndrome" on Sandybridge), always flush the submission tasklet from the heartbeat. This papers over such issues, but will still appear as a second long glitch, and prevents us from detecting it unless we happen to be performing a timed test. v2: We rely on flush_submission() synchronizing with the tasklet on another CPU. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 +++++++++---------- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +++ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index d613cf31970c..31049e0bdb57 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1094,19 +1094,18 @@ void intel_engine_flush_submission(struct intel_engine_cs *engine) { struct tasklet_struct *t = &engine->execlists.tasklet; - if (__tasklet_is_scheduled(t)) { - local_bh_disable(); - if (tasklet_trylock(t)) { - /* Must wait for any GPU reset in progress. */ - if (__tasklet_is_enabled(t)) - t->func(t->data); - tasklet_unlock(t); - } - local_bh_enable(); + /* Synchronise and wait for the tasklet on another CPU */ + tasklet_kill(t); + + /* Having cancelled the tasklet, ensure that is run */ + local_bh_disable(); + if (tasklet_trylock(t)) { + /* Must wait for any GPU reset in progress. */ + if (__tasklet_is_enabled(t)) + t->func(t->data); + tasklet_unlock(t); } - - /* Otherwise flush the tasklet if it was running on another cpu */ - tasklet_unlock_wait(t); + local_bh_enable(); } /** diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index f67ad937eefb..cd20fb549b38 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -65,6 +65,9 @@ static void heartbeat(struct work_struct *wrk) struct intel_context *ce = engine->kernel_context; struct i915_request *rq; + /* Just in case everything has gone horribly wrong, give it a kick */ + intel_engine_flush_submission(engine); + rq = engine->heartbeat.systole; if (rq && i915_request_completed(rq)) { i915_request_put(rq); -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 15 14:00:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 14:00:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_remove_unnecessary_conversion_to_bool?= In-Reply-To: <20200615043822.14206-1-bernard@vivo.com> References: <20200615043822.14206-1-bernard@vivo.com> Message-ID: <159222962207.16141.6756290398179952171@emeril.freedesktop.org> == Series Details == Series: drm/i915: remove unnecessary conversion to bool URL : https://patchwork.freedesktop.org/series/78372/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17947 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/index.html Known issues ------------ Here are the changes found in Patchwork_17947 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_flink_basic@double-flink: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_flink_basic@double-flink.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-tgl-y/igt at gem_flink_basic@double-flink.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at gem_flink_basic@flink-lifetime: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at modeset: - {fi-tgl-dsi}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at kms_busy@basic at modeset.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-tgl-dsi/igt at kms_busy@basic at modeset.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][23] ([i915#402]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][25] ([i915#62]) -> [DMESG-FAIL][26] ([i915#62] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][28] ([i915#62] / [i915#92]) +4 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92]) -> [DMESG-WARN][30] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 43) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17947 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17947: 2581895c0fd0630d61a1ade5e61ff609439f68c9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2581895c0fd0 drm/i915: remove unnecessary conversion to bool == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/index.html From patchwork at emeril.freedesktop.org Mon Jun 15 14:03:48 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 14:03:48 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/10=5D_drm/i915/selftests=3A_Disa?= =?utf-8?q?ble_preemptive_heartbeats_over_preemption_tests_=28rev2=29?= In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <159222982894.16140.10690678992750510621@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests (rev2) URL : https://patchwork.freedesktop.org/series/78371/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4a185d115cdb drm/i915/selftests: Disable preemptive heartbeats over preemption tests 7188eaf51b40 drm/i915/selftests: Dump engine state and trace upon hanging after reset -:29: CHECK:LINE_SPACING: Please don't use multiple blank lines #29: FILE: drivers/gpu/drm/i915/gt/selftest_hangcheck.c:511: + + total: 0 errors, 0 warnings, 1 checks, 24 lines checked 8ca01417d140 drm/i915/gt: Add a safety submission flush in the heartbeat 211c9c5a677c drm/i915/execlists: Replace direct submit with direct call to tasklet 502d7d962450 drm/i915/execlists: Defer schedule_out until after the next dequeue -:117: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV) #117: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:2441: + *execlists->inactive++ = *port; ^ total: 0 errors, 0 warnings, 1 checks, 179 lines checked ab23cefb7c81 drm/i915/gt: ce->inflight updates are now serialised ffe345ebb5eb drm/i915/gt: Drop atomic for engine->fw_active tracking d8fe93841b53 drm/i915/gt: Use virtual_engine during execlists_dequeue db4fcfc79839 drm/i915/gt: Decouple inflight virtual engines 2d03c2830ca3 drm/i915/gt: Resubmit the virtual engine on schedule-out From patchwork at emeril.freedesktop.org Mon Jun 15 14:05:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 14:05:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/10=5D_drm/i915/selftests=3A_Disable_?= =?utf-8?q?preemptive_heartbeats_over_preemption_tests_=28rev2=29?= In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <159222990487.16139.14419149165638415238@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests (rev2) URL : https://patchwork.freedesktop.org/series/78371/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From tvrtko.ursulin at linux.intel.com Mon Jun 15 14:09:28 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 15 Jun 2020 15:09:28 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Remove redundant i915_request_await_object in blit clears Message-ID: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> One i915_request_await_object is enough and we keep the one under the object lock so it is final. At the same time move async clflushing setup under the same locked section and consolidate common code into a helper function. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Matthew Auld <matthew.auld at intel.com> Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> --- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 35 +++++++------------ 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index f457d7130491..7d8b396e265a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context *ce, struct i915_vma *vma) intel_engine_pm_put(ce->engine); } +static int +move_obj_to_gpu(struct drm_i915_gem_object *obj, + struct i915_request *rq, + bool write) +{ + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, 0); + + return i915_request_await_object(rq, obj, write); +} + int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, struct intel_context *ce, u32 value) @@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, if (unlikely(err)) return err; - if (obj->cache_dirty & ~obj->cache_coherent) { - i915_gem_object_lock(obj); - i915_gem_clflush_object(obj, 0); - i915_gem_object_unlock(obj); - } - batch = intel_emit_vma_fill_blt(ce, vma, value); if (IS_ERR(batch)) { err = PTR_ERR(batch); @@ -165,10 +170,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, if (unlikely(err)) goto out_request; - err = i915_request_await_object(rq, obj, true); - if (unlikely(err)) - goto out_request; - if (ce->engine->emit_init_breadcrumb) { err = ce->engine->emit_init_breadcrumb(rq); if (unlikely(err)) @@ -176,7 +177,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, } i915_vma_lock(vma); - err = i915_request_await_object(rq, vma->obj, true); + err = move_obj_to_gpu(vma->obj, rq, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); i915_vma_unlock(vma); @@ -317,16 +318,6 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, return ERR_PTR(err); } -static int move_to_gpu(struct i915_vma *vma, struct i915_request *rq, bool write) -{ - struct drm_i915_gem_object *obj = vma->obj; - - if (obj->cache_dirty & ~obj->cache_coherent) - i915_gem_clflush_object(obj, 0); - - return i915_request_await_object(rq, obj, write); -} - int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, struct drm_i915_gem_object *dst, struct intel_context *ce) @@ -375,7 +366,7 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, goto out_request; for (i = 0; i < ARRAY_SIZE(vma); i++) { - err = move_to_gpu(vma[i], rq, i); + err = move_obj_to_gpu(vma[i]->obj, rq, i); if (unlikely(err)) goto out_unlock; } -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 15 14:26:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 14:26:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/10=5D_drm/i915/selftests=3A_Disable_pre?= =?utf-8?q?emptive_heartbeats_over_preemption_tests_=28rev2=29?= In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <159223119128.16139.11465874538348609031@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests (rev2) URL : https://patchwork.freedesktop.org/series/78371/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17948 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17948 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17948, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17948: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at hangcheck: - fi-tgl-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-tgl-u2/igt at i915_selftest@live at hangcheck.html Known issues ------------ Here are the changes found in Patchwork_17948 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1242]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][7] -> [DMESG-WARN][8] ([i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at vgem_basic@dmabuf-mmap: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at vgem_basic@dmabuf-mmap.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-tgl-y/igt at vgem_basic@dmabuf-mmap.html #### Possible fixes #### * igt at gem_ctx_create@basic: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_ctx_create@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-tgl-y/igt at gem_ctx_create@basic.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at modeset: - {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at kms_busy@basic at modeset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-tgl-dsi/igt at kms_busy@basic at modeset.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][23] ([i915#62]) -> [SKIP][24] ([fdo#109271]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 32) ------------------------------ Missing (18): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-ilk-650 fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-pnv-d510 fi-blb-e6850 fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17948 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17948: 2d03c2830ca379b6bc73c3e25e323c58ac6955c8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2d03c2830ca3 drm/i915/gt: Resubmit the virtual engine on schedule-out db4fcfc79839 drm/i915/gt: Decouple inflight virtual engines d8fe93841b53 drm/i915/gt: Use virtual_engine during execlists_dequeue ffe345ebb5eb drm/i915/gt: Drop atomic for engine->fw_active tracking ab23cefb7c81 drm/i915/gt: ce->inflight updates are now serialised 502d7d962450 drm/i915/execlists: Defer schedule_out until after the next dequeue 211c9c5a677c drm/i915/execlists: Replace direct submit with direct call to tasklet 8ca01417d140 drm/i915/gt: Add a safety submission flush in the heartbeat 7188eaf51b40 drm/i915/selftests: Dump engine state and trace upon hanging after reset 4a185d115cdb drm/i915/selftests: Disable preemptive heartbeats over preemption tests == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17948/index.html From chris at chris-wilson.co.uk Mon Jun 15 14:30:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 15:30:35 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159223143519.2981.2404611553306232536@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-15 15:09:28) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > One i915_request_await_object is enough and we keep the one under the > object lock so it is final. > > At the same time move async clflushing setup under the same locked > section and consolidate common code into a helper function. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > Cc: Matthew Auld <matthew.auld at intel.com> > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> > --- > .../gpu/drm/i915/gem/i915_gem_object_blt.c | 35 +++++++------------ > 1 file changed, 13 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > index f457d7130491..7d8b396e265a 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context *ce, struct i915_vma *vma) > intel_engine_pm_put(ce->engine); > } > > +static int > +move_obj_to_gpu(struct drm_i915_gem_object *obj, > + struct i915_request *rq, > + bool write) > +{ > + if (obj->cache_dirty & ~obj->cache_coherent) > + i915_gem_clflush_object(obj, 0); > + > + return i915_request_await_object(rq, obj, write); > +} > + > int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > struct intel_context *ce, > u32 value) > @@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > if (unlikely(err)) > return err; > > - if (obj->cache_dirty & ~obj->cache_coherent) { > - i915_gem_object_lock(obj); > - i915_gem_clflush_object(obj, 0); > - i915_gem_object_unlock(obj); > - } > - > batch = intel_emit_vma_fill_blt(ce, vma, value); > if (IS_ERR(batch)) { > err = PTR_ERR(batch); > @@ -165,10 +170,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > if (unlikely(err)) > goto out_request; > > - err = i915_request_await_object(rq, obj, true); > - if (unlikely(err)) > - goto out_request; > - > if (ce->engine->emit_init_breadcrumb) { > err = ce->engine->emit_init_breadcrumb(rq); > if (unlikely(err)) > @@ -176,7 +177,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > } > > i915_vma_lock(vma); > - err = i915_request_await_object(rq, vma->obj, true); > + err = move_obj_to_gpu(vma->obj, rq, true); > if (err == 0) > err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); > i915_vma_unlock(vma); Ah, but here it's also the wrong side of init_breadcrumb. -Chris From chris at chris-wilson.co.uk Mon Jun 15 14:33:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 15:33:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Dump engine state and trace upon hanging after reset In-Reply-To: <20200615123920.17749-2-chris@chris-wilson.co.uk> References: <20200615123920.17749-2-chris@chris-wilson.co.uk> Message-ID: <20200615143321.14371-1-chris@chris-wilson.co.uk> If the engine dies after a reset, and so we fail to submit a request but need to be interrupted by the CI runner, dump the engine state. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 2af66f8ffbd2..1ea4935e0eeb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -499,6 +499,21 @@ static int igt_reset_nop_engine(void *arg) rq = intel_context_create_request(ce); if (IS_ERR(rq)) { + struct drm_printer p = + drm_info_printer(gt->i915->drm.dev); + intel_engine_dump(engine, &p, + "%s(%s): failed to submit request\n", + __func__, + engine->name); + + + GEM_TRACE("%s(%s): failed to submit request\n", + __func__, + engine->name); + GEM_TRACE_DUMP(); + + intel_gt_set_wedged(gt); + err = PTR_ERR(rq); break; } -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 15 14:51:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 14:51:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Remove_redundant_i915=5Frequest=5Fawait=5Fobject_in_bl?= =?utf-8?q?it_clears?= In-Reply-To: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159223266080.16139.7266345127297276860@emeril.freedesktop.org> == Series Details == Series: drm/i915: Remove redundant i915_request_await_object in blit clears URL : https://patchwork.freedesktop.org/series/78374/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17949 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/index.html Known issues ------------ Here are the changes found in Patchwork_17949 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-byt-n2820/igt at debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-byt-n2820/igt at debugfs_test@read_all_entries.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-tgl-y/igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_frontbuffer_tracking@basic: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at kms_frontbuffer_tracking@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-tgl-y/igt at kms_frontbuffer_tracking@basic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][11] ([i915#1888]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at gem_flink_basic@flink-lifetime: - fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at modeset: - {fi-tgl-dsi}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at kms_busy@basic at modeset.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-tgl-dsi/igt at kms_busy@basic at modeset.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][23] ([i915#402]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][27] ([i915#62]) -> [SKIP][28] ([fdo#109271]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92]) -> [DMESG-WARN][30] ([i915#62] / [i915#92] / [i915#95]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][32] ([i915#62] / [i915#92]) +4 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-gdg-551 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17949 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17949: 3c89ad48e5ffb2be20173ef5a9e42950d696d223 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3c89ad48e5ff drm/i915: Remove redundant i915_request_await_object in blit clears == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/index.html From tvrtko.ursulin at linux.intel.com Mon Jun 15 14:54:56 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 15 Jun 2020 15:54:56 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <159223143519.2981.2404611553306232536@build.alporthouse.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> <159223143519.2981.2404611553306232536@build.alporthouse.com> Message-ID: <1264692d-8fa6-7731-548a-923c6279d537@linux.intel.com> On 15/06/2020 15:30, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-15 15:09:28) >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> One i915_request_await_object is enough and we keep the one under the >> object lock so it is final. >> >> At the same time move async clflushing setup under the same locked >> section and consolidate common code into a helper function. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> Cc: Matthew Auld <matthew.auld at intel.com> >> Cc: Chris Wilson <chris at chris-wilson.co.uk> >> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> >> --- >> .../gpu/drm/i915/gem/i915_gem_object_blt.c | 35 +++++++------------ >> 1 file changed, 13 insertions(+), 22 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> index f457d7130491..7d8b396e265a 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context *ce, struct i915_vma *vma) >> intel_engine_pm_put(ce->engine); >> } >> >> +static int >> +move_obj_to_gpu(struct drm_i915_gem_object *obj, >> + struct i915_request *rq, >> + bool write) >> +{ >> + if (obj->cache_dirty & ~obj->cache_coherent) >> + i915_gem_clflush_object(obj, 0); >> + >> + return i915_request_await_object(rq, obj, write); >> +} >> + >> int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, >> struct intel_context *ce, >> u32 value) >> @@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, >> if (unlikely(err)) >> return err; >> >> - if (obj->cache_dirty & ~obj->cache_coherent) { >> - i915_gem_object_lock(obj); >> - i915_gem_clflush_object(obj, 0); >> - i915_gem_object_unlock(obj); >> - } >> - >> batch = intel_emit_vma_fill_blt(ce, vma, value); >> if (IS_ERR(batch)) { >> err = PTR_ERR(batch); >> @@ -165,10 +170,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, >> if (unlikely(err)) >> goto out_request; >> >> - err = i915_request_await_object(rq, obj, true); >> - if (unlikely(err)) >> - goto out_request; >> - >> if (ce->engine->emit_init_breadcrumb) { >> err = ce->engine->emit_init_breadcrumb(rq); >> if (unlikely(err)) >> @@ -176,7 +177,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, >> } >> >> i915_vma_lock(vma); >> - err = i915_request_await_object(rq, vma->obj, true); >> + err = move_obj_to_gpu(vma->obj, rq, true); >> if (err == 0) >> err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); >> i915_vma_unlock(vma); > > Ah, but here it's also the wrong side of init_breadcrumb. Why it is important to mark the object as active on the failure path? We skip the payload, no? Regards, Tvrtko From patchwork at emeril.freedesktop.org Mon Jun 15 14:55:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 14:55:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/10=5D_drm/i915/selftests=3A_Disa?= =?utf-8?q?ble_preemptive_heartbeats_over_preemption_tests_=28rev3=29?= In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <159223292223.16139.3930311921160019064@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests (rev3) URL : https://patchwork.freedesktop.org/series/78371/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5fa39ee36f3b drm/i915/selftests: Disable preemptive heartbeats over preemption tests 00b8905ebbd9 drm/i915/selftests: Dump engine state and trace upon hanging after reset -:27: CHECK:LINE_SPACING: Please don't use multiple blank lines #27: FILE: drivers/gpu/drm/i915/gt/selftest_hangcheck.c:509: + + total: 0 errors, 0 warnings, 1 checks, 21 lines checked 4dc0044cb492 drm/i915/gt: Add a safety submission flush in the heartbeat 6f4c470b5862 drm/i915/execlists: Replace direct submit with direct call to tasklet a2f814c038a3 drm/i915/execlists: Defer schedule_out until after the next dequeue -:117: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV) #117: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:2441: + *execlists->inactive++ = *port; ^ total: 0 errors, 0 warnings, 1 checks, 179 lines checked cd5b50c90e8b drm/i915/gt: ce->inflight updates are now serialised db8e1905bf15 drm/i915/gt: Drop atomic for engine->fw_active tracking fd7fb36f7457 drm/i915/gt: Use virtual_engine during execlists_dequeue 0d9311cd5488 drm/i915/gt: Decouple inflight virtual engines 11a16dbbd0c4 drm/i915/gt: Resubmit the virtual engine on schedule-out From patchwork at emeril.freedesktop.org Mon Jun 15 14:56:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 14:56:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/10=5D_drm/i915/selftests=3A_Disable_?= =?utf-8?q?preemptive_heartbeats_over_preemption_tests_=28rev3=29?= In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <159223299833.16139.3201144306789889437@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests (rev3) URL : https://patchwork.freedesktop.org/series/78371/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From chris at chris-wilson.co.uk Mon Jun 15 15:01:19 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 16:01:19 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <1264692d-8fa6-7731-548a-923c6279d537@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> <159223143519.2981.2404611553306232536@build.alporthouse.com> <1264692d-8fa6-7731-548a-923c6279d537@linux.intel.com> Message-ID: <159223327959.2981.13152363683001575042@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-15 15:54:56) > > On 15/06/2020 15:30, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-15 15:09:28) > >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> > >> One i915_request_await_object is enough and we keep the one under the > >> object lock so it is final. > >> > >> At the same time move async clflushing setup under the same locked > >> section and consolidate common code into a helper function. > >> > >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> Cc: Matthew Auld <matthew.auld at intel.com> > >> Cc: Chris Wilson <chris at chris-wilson.co.uk> > >> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> > >> --- > >> .../gpu/drm/i915/gem/i915_gem_object_blt.c | 35 +++++++------------ > >> 1 file changed, 13 insertions(+), 22 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > >> index f457d7130491..7d8b396e265a 100644 > >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > >> @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context *ce, struct i915_vma *vma) > >> intel_engine_pm_put(ce->engine); > >> } > >> > >> +static int > >> +move_obj_to_gpu(struct drm_i915_gem_object *obj, > >> + struct i915_request *rq, > >> + bool write) > >> +{ > >> + if (obj->cache_dirty & ~obj->cache_coherent) > >> + i915_gem_clflush_object(obj, 0); > >> + > >> + return i915_request_await_object(rq, obj, write); > >> +} > >> + > >> int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > >> struct intel_context *ce, > >> u32 value) > >> @@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > >> if (unlikely(err)) > >> return err; > >> > >> - if (obj->cache_dirty & ~obj->cache_coherent) { > >> - i915_gem_object_lock(obj); > >> - i915_gem_clflush_object(obj, 0); > >> - i915_gem_object_unlock(obj); > >> - } > >> - > >> batch = intel_emit_vma_fill_blt(ce, vma, value); > >> if (IS_ERR(batch)) { > >> err = PTR_ERR(batch); > >> @@ -165,10 +170,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > >> if (unlikely(err)) > >> goto out_request; > >> > >> - err = i915_request_await_object(rq, obj, true); > >> - if (unlikely(err)) > >> - goto out_request; > >> - > >> if (ce->engine->emit_init_breadcrumb) { > >> err = ce->engine->emit_init_breadcrumb(rq); > >> if (unlikely(err)) > >> @@ -176,7 +177,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > >> } > >> > >> i915_vma_lock(vma); > >> - err = i915_request_await_object(rq, vma->obj, true); > >> + err = move_obj_to_gpu(vma->obj, rq, true); > >> if (err == 0) > >> err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); > >> i915_vma_unlock(vma); > > > > Ah, but here it's also the wrong side of init_breadcrumb. > > Why it is important to mark the object as active on the failure path? We > skip the payload, no? It's important that all the async waits are before the breadcrumb. Up until recently we would emit the semaphore after the init, and so believe the payload was running and all waits were completed even though it was still waiting on another request to complete. If this blt request was subsequently relied upon to indicate the other fence completions we would then start other requests early. [It's less important now as we look at a flag saying that the init_breadcrumb has been emitted and avoid adding more semaphores.] -Chris From ckoenig.leichtzumerken at gmail.com Mon Jun 15 14:54:13 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?q?Christian=20K=C3=B6nig?=) Date: Mon, 15 Jun 2020 16:54:13 +0200 Subject: [Intel-gfx] [PATCH 1/3] drm/mm: remove unused rb_hole_size() Message-ID: <20200615145415.1775-1-christian.koenig@amd.com> Just some code cleanup. Signed-off-by: Christian K?nig <christian.koenig at amd.com> --- drivers/gpu/drm/drm_mm.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 82d2888eb7fe..425fcd3590e8 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -305,11 +305,6 @@ static inline struct drm_mm_node *rb_hole_addr_to_node(struct rb_node *rb) return rb_entry_safe(rb, struct drm_mm_node, rb_hole_addr); } -static inline u64 rb_hole_size(struct rb_node *rb) -{ - return rb_entry(rb, struct drm_mm_node, rb_hole_size)->hole_size; -} - static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size) { struct rb_node *rb = mm->holes_size.rb_root.rb_node; -- 2.17.1 From ckoenig.leichtzumerken at gmail.com Mon Jun 15 14:54:14 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?q?Christian=20K=C3=B6nig?=) Date: Mon, 15 Jun 2020 16:54:14 +0200 Subject: [Intel-gfx] [PATCH 2/3] drm/mm: optimize find_hole() as well In-Reply-To: <20200615145415.1775-1-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> Message-ID: <20200615145415.1775-2-christian.koenig@amd.com> Abort early if there isn't enough space to allocate from a subtree. Signed-off-by: Christian K?nig <christian.koenig at amd.com> --- drivers/gpu/drm/drm_mm.c | 11 +++++++---- drivers/gpu/drm/selftests/test-drm_mm.c | 11 ----------- 2 files changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 425fcd3590e8..177a5df0fe95 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -325,7 +325,7 @@ static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size) return best; } -static struct drm_mm_node *find_hole(struct drm_mm *mm, u64 addr) +static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64 size) { struct rb_node *rb = mm->holes_addr.rb_node; struct drm_mm_node *node = NULL; @@ -333,6 +333,9 @@ static struct drm_mm_node *find_hole(struct drm_mm *mm, u64 addr) while (rb) { u64 hole_start; + if (rb_hole_addr_to_node(rb)->subtree_max_hole < size) + break; + node = rb_hole_addr_to_node(rb); hole_start = __drm_mm_hole_node_start(node); @@ -358,10 +361,10 @@ first_hole(struct drm_mm *mm, return best_hole(mm, size); case DRM_MM_INSERT_LOW: - return find_hole(mm, start); + return find_hole_addr(mm, start, size); case DRM_MM_INSERT_HIGH: - return find_hole(mm, end); + return find_hole_addr(mm, end, size); case DRM_MM_INSERT_EVICT: return list_first_entry_or_null(&mm->hole_stack, @@ -497,7 +500,7 @@ int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node) return -ENOSPC; /* Find the relevant hole to add our node to */ - hole = find_hole(mm, node->start); + hole = find_hole_addr(mm, node->start, 0); if (!hole) return -ENOSPC; diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c b/drivers/gpu/drm/selftests/test-drm_mm.c index ca5f35def905..b879aedfc00d 100644 --- a/drivers/gpu/drm/selftests/test-drm_mm.c +++ b/drivers/gpu/drm/selftests/test-drm_mm.c @@ -1981,16 +1981,6 @@ static int __igt_once(unsigned int mode) } memset(&node, 0, sizeof(node)); - err = drm_mm_insert_node_generic(&mm, &node, - 2, 0, 0, - mode | DRM_MM_INSERT_ONCE); - if (!err) { - pr_err("Unexpectedly inserted the node into the wrong hole: node.start=%llx\n", - node.start); - err = -EINVAL; - goto err_node; - } - err = drm_mm_insert_node_generic(&mm, &node, 2, 0, 0, mode); if (err) { pr_err("Could not insert the node into the available hole!\n"); @@ -1998,7 +1988,6 @@ static int __igt_once(unsigned int mode) goto err_hi; } -err_node: drm_mm_remove_node(&node); err_hi: drm_mm_remove_node(&rsvd_hi); -- 2.17.1 From ckoenig.leichtzumerken at gmail.com Mon Jun 15 14:54:15 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?q?Christian=20K=C3=B6nig?=) Date: Mon, 15 Jun 2020 16:54:15 +0200 Subject: [Intel-gfx] [PATCH 3/3] drm/mm: cleanup and improve next_hole_*_addr() In-Reply-To: <20200615145415.1775-1-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> Message-ID: <20200615145415.1775-3-christian.koenig@amd.com> Skipping just one branch of the tree is not the most effective approach. Instead use a macro to define the traversal functions and sort out both branch sides. This improves the performance of the unit tests by a factor of more than 4. Signed-off-by: Christian K?nig <christian.koenig at amd.com> --- drivers/gpu/drm/drm_mm.c | 106 +++++++++++++-------------------------- 1 file changed, 34 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index 177a5df0fe95..a4a04d246135 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -325,6 +325,11 @@ static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size) return best; } +static bool usable_hole_addr(struct rb_node *rb, u64 size) +{ + return rb && rb_hole_addr_to_node(rb)->subtree_max_hole >= size; +} + static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64 size) { struct rb_node *rb = mm->holes_addr.rb_node; @@ -333,7 +338,7 @@ static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64 size) while (rb) { u64 hole_start; - if (rb_hole_addr_to_node(rb)->subtree_max_hole < size) + if (!usable_hole_addr(rb, size)) break; node = rb_hole_addr_to_node(rb); @@ -374,82 +379,39 @@ first_hole(struct drm_mm *mm, } /** - * next_hole_high_addr - returns next hole for a DRM_MM_INSERT_HIGH mode request - * @entry: previously selected drm_mm_node - * @size: size of the a hole needed for the request - * - * This function will verify whether left subtree of @entry has hole big enough - * to fit the requtested size. If so, it will return previous node of @entry or - * else it will return parent node of @entry + * DECLARE_NEXT_HOLE_ADDR - macro to declare next hole functions + * @name: name of function to declare + * @first: first rb member to traverse (either rb_left or rb_right). + * @last: last rb member to traverse (either rb_right or rb_left). * - * It will also skip the complete left subtree if subtree_max_hole of that - * subtree is same as the subtree_max_hole of the @entry. - * - * Returns: - * previous node of @entry if left subtree of @entry can serve the request or - * else return parent of @entry + * This macro declares a function to return the next hole of the addr rb tree. + * While traversing the tree we take the searched size into account and only + * visit branches with potential big enough holes. */ -static struct drm_mm_node * -next_hole_high_addr(struct drm_mm_node *entry, u64 size) -{ - struct rb_node *rb_node, *left_rb_node, *parent_rb_node; - struct drm_mm_node *left_node; - - if (!entry) - return NULL; - rb_node = &entry->rb_hole_addr; - if (rb_node->rb_left) { - left_rb_node = rb_node->rb_left; - parent_rb_node = rb_parent(rb_node); - left_node = rb_entry(left_rb_node, - struct drm_mm_node, rb_hole_addr); - if (left_node->subtree_max_hole < size && - parent_rb_node && parent_rb_node->rb_left != rb_node) - return rb_hole_addr_to_node(parent_rb_node); - } - - return rb_hole_addr_to_node(rb_prev(rb_node)); +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ +{ \ + struct rb_node *parent, *node = &entry->rb_hole_addr; \ + \ + if (!entry || RB_EMPTY_NODE(node)) \ + return NULL; \ + \ + if (usable_hole_addr(node->first, size)) { \ + node = node->first; \ + while (usable_hole_addr(node->last, size)) \ + node = node->last; \ + return rb_hole_addr_to_node(node); \ + } \ + \ + while ((parent = rb_parent(node)) && node == parent->first) \ + node = parent; \ + \ + return rb_hole_addr_to_node(parent); \ } -/** - * next_hole_low_addr - returns next hole for a DRM_MM_INSERT_LOW mode request - * @entry: previously selected drm_mm_node - * @size: size of the a hole needed for the request - * - * This function will verify whether right subtree of @entry has hole big enough - * to fit the requtested size. If so, it will return next node of @entry or - * else it will return parent node of @entry - * - * It will also skip the complete right subtree if subtree_max_hole of that - * subtree is same as the subtree_max_hole of the @entry. - * - * Returns: - * next node of @entry if right subtree of @entry can serve the request or - * else return parent of @entry - */ -static struct drm_mm_node * -next_hole_low_addr(struct drm_mm_node *entry, u64 size) -{ - struct rb_node *rb_node, *right_rb_node, *parent_rb_node; - struct drm_mm_node *right_node; - - if (!entry) - return NULL; - - rb_node = &entry->rb_hole_addr; - if (rb_node->rb_right) { - right_rb_node = rb_node->rb_right; - parent_rb_node = rb_parent(rb_node); - right_node = rb_entry(right_rb_node, - struct drm_mm_node, rb_hole_addr); - if (right_node->subtree_max_hole < size && - parent_rb_node && parent_rb_node->rb_right != rb_node) - return rb_hole_addr_to_node(parent_rb_node); - } - - return rb_hole_addr_to_node(rb_next(rb_node)); -} +DECLARE_NEXT_HOLE_ADDR(next_hole_high_addr, rb_left, rb_right) +DECLARE_NEXT_HOLE_ADDR(next_hole_low_addr, rb_right, rb_left) static struct drm_mm_node * next_hole(struct drm_mm *mm, -- 2.17.1 From daniel.vetter at ffwll.ch Mon Jun 15 15:10:26 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Mon, 15 Jun 2020 17:10:26 +0200 Subject: [Intel-gfx] [PATCH] drm/shmem-helper: Fix obj->filp derefence Message-ID: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> I broke that in my refactoring: commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca Author: Daniel Vetter <daniel.vetter at ffwll.ch> Date: Fri May 29 16:05:42 2020 +0200 drm/shmem-helpers: Simplify dma-buf importing Reported-by: Thomas Zimmermann <tzimmermann at suse.de> Fixes: 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing") Cc: Boris Brezillon <boris.brezillon at collabora.com> Cc: Thomas Zimmermann <tzimmermann at suse.de> Cc: Gerd Hoffmann <kraxel at redhat.com> Cc: Rob Herring <robh at kernel.org> Cc: Noralf Tr?nnes <noralf at tronnes.org> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/drm_gem_shmem_helper.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index 0a7e3b664bc2..3e7ee407a17c 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -70,15 +70,17 @@ __drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private) mutex_init(&shmem->vmap_lock); INIT_LIST_HEAD(&shmem->madv_list); - /* - * Our buffers are kept pinned, so allocating them - * from the MOVABLE zone is a really bad idea, and - * conflicts with CMA. See comments above new_inode() - * why this is required _and_ expected if you're - * going to pin these pages. - */ - mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | - __GFP_RETRY_MAYFAIL | __GFP_NOWARN); + if (!private) { + /* + * Our buffers are kept pinned, so allocating them + * from the MOVABLE zone is a really bad idea, and + * conflicts with CMA. See comments above new_inode() + * why this is required _and_ expected if you're + * going to pin these pages. + */ + mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | + __GFP_RETRY_MAYFAIL | __GFP_NOWARN); + } return shmem; -- 2.27.0 From tvrtko.ursulin at linux.intel.com Mon Jun 15 15:14:49 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 15 Jun 2020 16:14:49 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200615151449.32605-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> One i915_request_await_object is enough and we keep the one under the object lock so it is final. At the same time move async clflushing setup under the same locked section and consolidate common code into a helper function. v2: * Emit initial breadcrumbs after aways are set up. (Chris) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Matthew Auld <matthew.auld at intel.com> Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> --- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 52 ++++++++----------- 1 file changed, 21 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index f457d7130491..bfdb32d46877 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context *ce, struct i915_vma *vma) intel_engine_pm_put(ce->engine); } +static int +move_obj_to_gpu(struct drm_i915_gem_object *obj, + struct i915_request *rq, + bool write) +{ + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, 0); + + return i915_request_await_object(rq, obj, write); +} + int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, struct intel_context *ce, u32 value) @@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, if (unlikely(err)) return err; - if (obj->cache_dirty & ~obj->cache_coherent) { - i915_gem_object_lock(obj); - i915_gem_clflush_object(obj, 0); - i915_gem_object_unlock(obj); - } - batch = intel_emit_vma_fill_blt(ce, vma, value); if (IS_ERR(batch)) { err = PTR_ERR(batch); @@ -165,27 +170,22 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, if (unlikely(err)) goto out_request; - err = i915_request_await_object(rq, obj, true); - if (unlikely(err)) - goto out_request; - - if (ce->engine->emit_init_breadcrumb) { - err = ce->engine->emit_init_breadcrumb(rq); - if (unlikely(err)) - goto out_request; - } - i915_vma_lock(vma); - err = i915_request_await_object(rq, vma->obj, true); + err = move_obj_to_gpu(vma->obj, rq, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); i915_vma_unlock(vma); if (unlikely(err)) goto out_request; - err = ce->engine->emit_bb_start(rq, - batch->node.start, batch->node.size, - 0); + if (ce->engine->emit_init_breadcrumb) + err = ce->engine->emit_init_breadcrumb(rq); + + if (likely(!err)) + err = ce->engine->emit_bb_start(rq, + batch->node.start, + batch->node.size, + 0); out_request: if (unlikely(err)) i915_request_set_error_once(rq, err); @@ -317,16 +317,6 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, return ERR_PTR(err); } -static int move_to_gpu(struct i915_vma *vma, struct i915_request *rq, bool write) -{ - struct drm_i915_gem_object *obj = vma->obj; - - if (obj->cache_dirty & ~obj->cache_coherent) - i915_gem_clflush_object(obj, 0); - - return i915_request_await_object(rq, obj, write); -} - int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, struct drm_i915_gem_object *dst, struct intel_context *ce) @@ -375,7 +365,7 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, goto out_request; for (i = 0; i < ARRAY_SIZE(vma); i++) { - err = move_to_gpu(vma[i], rq, i); + err = move_obj_to_gpu(vma[i]->obj, rq, i); if (unlikely(err)) goto out_unlock; } -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 15 15:20:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 15:20:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/3=5D_drm/mm=3A_remove_unused_rb?= =?utf-8?b?X2hvbGVfc2l6ZSgp?= In-Reply-To: <20200615145415.1775-1-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> Message-ID: <159223442616.16138.11698664913286621776@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/mm: remove unused rb_hole_size() URL : https://patchwork.freedesktop.org/series/78376/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4790c8cb3116 drm/mm: remove unused rb_hole_size() -:28: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author '"Christian K?nig" <ckoenig.leichtzumerken at gmail.com>' total: 0 errors, 1 warnings, 0 checks, 11 lines checked 53df83ceed85 drm/mm: optimize find_hole() as well -:86: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author '"Christian K?nig" <ckoenig.leichtzumerken at gmail.com>' total: 0 errors, 1 warnings, 0 checks, 60 lines checked ef8803bbb4c3 drm/mm: cleanup and improve next_hole_*_addr() -:92: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues #92: FILE: drivers/gpu/drm/drm_mm.c:392: +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ +{ \ + struct rb_node *parent, *node = &entry->rb_hole_addr; \ + \ + if (!entry || RB_EMPTY_NODE(node)) \ + return NULL; \ + \ + if (usable_hole_addr(node->first, size)) { \ + node = node->first; \ + while (usable_hole_addr(node->last, size)) \ + node = node->last; \ + return rb_hole_addr_to_node(node); \ + } \ + \ + while ((parent = rb_parent(node)) && node == parent->first) \ + node = parent; \ + \ + return rb_hole_addr_to_node(parent); \ } -:92: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'first' - possible side-effects? #92: FILE: drivers/gpu/drm/drm_mm.c:392: +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ +{ \ + struct rb_node *parent, *node = &entry->rb_hole_addr; \ + \ + if (!entry || RB_EMPTY_NODE(node)) \ + return NULL; \ + \ + if (usable_hole_addr(node->first, size)) { \ + node = node->first; \ + while (usable_hole_addr(node->last, size)) \ + node = node->last; \ + return rb_hole_addr_to_node(node); \ + } \ + \ + while ((parent = rb_parent(node)) && node == parent->first) \ + node = parent; \ + \ + return rb_hole_addr_to_node(parent); \ } -:92: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'first' may be better as '(first)' to avoid precedence issues #92: FILE: drivers/gpu/drm/drm_mm.c:392: +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ +{ \ + struct rb_node *parent, *node = &entry->rb_hole_addr; \ + \ + if (!entry || RB_EMPTY_NODE(node)) \ + return NULL; \ + \ + if (usable_hole_addr(node->first, size)) { \ + node = node->first; \ + while (usable_hole_addr(node->last, size)) \ + node = node->last; \ + return rb_hole_addr_to_node(node); \ + } \ + \ + while ((parent = rb_parent(node)) && node == parent->first) \ + node = parent; \ + \ + return rb_hole_addr_to_node(parent); \ } -:92: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'last' - possible side-effects? #92: FILE: drivers/gpu/drm/drm_mm.c:392: +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ +{ \ + struct rb_node *parent, *node = &entry->rb_hole_addr; \ + \ + if (!entry || RB_EMPTY_NODE(node)) \ + return NULL; \ + \ + if (usable_hole_addr(node->first, size)) { \ + node = node->first; \ + while (usable_hole_addr(node->last, size)) \ + node = node->last; \ + return rb_hole_addr_to_node(node); \ + } \ + \ + while ((parent = rb_parent(node)) && node == parent->first) \ + node = parent; \ + \ + return rb_hole_addr_to_node(parent); \ } -:92: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'last' may be better as '(last)' to avoid precedence issues #92: FILE: drivers/gpu/drm/drm_mm.c:392: +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ +{ \ + struct rb_node *parent, *node = &entry->rb_hole_addr; \ + \ + if (!entry || RB_EMPTY_NODE(node)) \ + return NULL; \ + \ + if (usable_hole_addr(node->first, size)) { \ + node = node->first; \ + while (usable_hole_addr(node->last, size)) \ + node = node->last; \ + return rb_hole_addr_to_node(node); \ + } \ + \ + while ((parent = rb_parent(node)) && node == parent->first) \ + node = parent; \ + \ + return rb_hole_addr_to_node(parent); \ } -:92: WARNING:MACRO_WITH_FLOW_CONTROL: Macros with flow control statements should be avoided #92: FILE: drivers/gpu/drm/drm_mm.c:392: +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ +{ \ + struct rb_node *parent, *node = &entry->rb_hole_addr; \ + \ + if (!entry || RB_EMPTY_NODE(node)) \ + return NULL; \ + \ + if (usable_hole_addr(node->first, size)) { \ + node = node->first; \ + while (usable_hole_addr(node->last, size)) \ + node = node->last; \ + return rb_hole_addr_to_node(node); \ + } \ + \ + while ((parent = rb_parent(node)) && node == parent->first) \ + node = parent; \ + \ + return rb_hole_addr_to_node(parent); \ } -:155: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author '"Christian K?nig" <ckoenig.leichtzumerken at gmail.com>' total: 0 errors, 2 warnings, 5 checks, 129 lines checked From patchwork at emeril.freedesktop.org Mon Jun 15 15:20:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 15:20:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/10=5D_drm/i915/selftests=3A_Disable_pre?= =?utf-8?q?emptive_heartbeats_over_preemption_tests_=28rev3=29?= In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <159223444314.16140.13542005291944376739@emeril.freedesktop.org> == Series Details == Series: series starting with [01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests (rev3) URL : https://patchwork.freedesktop.org/series/78371/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17950 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17950 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17950, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17950: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at hangcheck: - fi-tgl-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-tgl-u2/igt at i915_selftest@live at hangcheck.html Known issues ------------ Here are the changes found in Patchwork_17950 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_getparams_basic@basic-subslice-total: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at i915_getparams_basic@basic-subslice-total.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-tgl-y/igt at i915_getparams_basic@basic-subslice-total.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][7] ([i915#1888]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at gem_flink_basic@flink-lifetime: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at modeset: - {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at kms_busy@basic at modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-tgl-dsi/igt at kms_busy@basic at modeset.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][21] ([i915#62]) -> [SKIP][22] ([fdo#109271]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 32) ------------------------------ Missing (18): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-ilk-650 fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-pnv-d510 fi-blb-e6850 fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17950 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17950: 11a16dbbd0c41889dccf4207b4bac2a9f08d3f7c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 11a16dbbd0c4 drm/i915/gt: Resubmit the virtual engine on schedule-out 0d9311cd5488 drm/i915/gt: Decouple inflight virtual engines fd7fb36f7457 drm/i915/gt: Use virtual_engine during execlists_dequeue db8e1905bf15 drm/i915/gt: Drop atomic for engine->fw_active tracking cd5b50c90e8b drm/i915/gt: ce->inflight updates are now serialised a2f814c038a3 drm/i915/execlists: Defer schedule_out until after the next dequeue 6f4c470b5862 drm/i915/execlists: Replace direct submit with direct call to tasklet 4dc0044cb492 drm/i915/gt: Add a safety submission flush in the heartbeat 00b8905ebbd9 drm/i915/selftests: Dump engine state and trace upon hanging after reset 5fa39ee36f3b drm/i915/selftests: Disable preemptive heartbeats over preemption tests == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17950/index.html From mika.kuoppala at linux.intel.com Mon Jun 15 15:29:08 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 15 Jun 2020 18:29:08 +0300 Subject: [Intel-gfx] [PATCH 01/10] drm/i915/selftests: Disable preemptive heartbeats over preemption tests In-Reply-To: <20200615123920.17749-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-1-chris@chris-wilson.co.uk> Message-ID: <87d0609wl7.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Since the heartbeat may cause a preemption event, disable it over the > preemption suppression tests. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index f651bdf7f191..91543494f595 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -2282,7 +2282,7 @@ static int live_suppress_self_preempt(void *arg) > if (igt_flush_test(gt->i915)) > goto err_wedged; > > - intel_engine_pm_get(engine); > + engine_heartbeat_disable(engine); > engine->execlists.preempt_hang.count = 0; > > rq_a = spinner_create_request(&a.spin, > @@ -2290,14 +2290,14 @@ static int live_suppress_self_preempt(void *arg) > MI_NOOP); > if (IS_ERR(rq_a)) { > err = PTR_ERR(rq_a); > - intel_engine_pm_put(engine); > + engine_heartbeat_enable(engine); > goto err_client_b; > } > > i915_request_add(rq_a); > if (!igt_wait_for_spinner(&a.spin, rq_a)) { > pr_err("First client failed to start\n"); > - intel_engine_pm_put(engine); > + engine_heartbeat_enable(engine); > goto err_wedged; > } > > @@ -2309,7 +2309,7 @@ static int live_suppress_self_preempt(void *arg) > MI_NOOP); > if (IS_ERR(rq_b)) { > err = PTR_ERR(rq_b); > - intel_engine_pm_put(engine); > + engine_heartbeat_enable(engine); > goto err_client_b; > } > i915_request_add(rq_b); > @@ -2320,7 +2320,7 @@ static int live_suppress_self_preempt(void *arg) > > if (!igt_wait_for_spinner(&b.spin, rq_b)) { > pr_err("Second client failed to start\n"); > - intel_engine_pm_put(engine); > + engine_heartbeat_enable(engine); > goto err_wedged; > } > > @@ -2334,12 +2334,12 @@ static int live_suppress_self_preempt(void *arg) > engine->name, > engine->execlists.preempt_hang.count, > depth); > - intel_engine_pm_put(engine); > + engine_heartbeat_enable(engine); > err = -EINVAL; > goto err_client_b; > } > > - intel_engine_pm_put(engine); > + engine_heartbeat_enable(engine); > if (igt_flush_test(gt->i915)) > goto err_wedged; > } > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Mon Jun 15 15:41:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 15:41:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/mm=3A_remove_unused_rb=5Fhole?= =?utf-8?b?X3NpemUoKQ==?= In-Reply-To: <20200615145415.1775-1-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> Message-ID: <159223570996.16141.4948322080108796523@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/mm: remove unused rb_hole_size() URL : https://patchwork.freedesktop.org/series/78376/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17951 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/index.html Known issues ------------ Here are the changes found in Patchwork_17951 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-apl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-apl-guc/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-apl-guc/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_selftest@live at active: - fi-skl-lmem: [PASS][5] -> [DMESG-FAIL][6] ([i915#666]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-skl-lmem/igt at i915_selftest@live at active.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-skl-lmem/igt at i915_selftest@live at active.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-kbl-x1275/igt at kms_busy@basic at flip.html - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-tgl-y/igt at kms_busy@basic at flip.html * igt at prime_vgem@basic-fence-flip: - fi-tgl-y: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at prime_vgem@basic-fence-flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-tgl-y/igt at prime_vgem@basic-fence-flip.html #### Possible fixes #### * igt at gem_flink_basic@flink-lifetime: - fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at i915_module_load@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-tgl-y: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-tgl-y/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] +3 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][27] ([i915#402]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][29] ([i915#62]) -> [SKIP][30] ([fdo#109271]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][32] ([i915#62] / [i915#92]) +3 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][33] ([i915#62] / [i915#92]) -> [DMESG-WARN][34] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-gdg-551 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17951 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17951: ef8803bbb4c34b9aa3afeba137902113894fc5b8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ef8803bbb4c3 drm/mm: cleanup and improve next_hole_*_addr() 53df83ceed85 drm/mm: optimize find_hole() as well 4790c8cb3116 drm/mm: remove unused rb_hole_size() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/index.html From patchwork at emeril.freedesktop.org Mon Jun 15 15:46:01 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 15:46:01 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/shmem-helper=3A_Fix_obj-=3Efilp_derefence?= In-Reply-To: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> References: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> Message-ID: <159223596147.16140.4917936311410614284@emeril.freedesktop.org> == Series Details == Series: drm/shmem-helper: Fix obj->filp derefence URL : https://patchwork.freedesktop.org/series/78378/ State : warning == Summary == $ dim checkpatch origin/drm-tip ce71e5b57288 drm/shmem-helper: Fix obj->filp derefence -:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing")' #11: commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca -:56: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 1 errors, 1 warnings, 0 checks, 26 lines checked From mika.kuoppala at linux.intel.com Mon Jun 15 15:56:16 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 15 Jun 2020 18:56:16 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Dump engine state and trace upon hanging after reset In-Reply-To: <20200615143321.14371-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-2-chris@chris-wilson.co.uk> <20200615143321.14371-1-chris@chris-wilson.co.uk> Message-ID: <87a7149vbz.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > If the engine dies after a reset, and so we fail to submit a request > but need to be interrupted by the CI runner, dump the engine state. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > index 2af66f8ffbd2..1ea4935e0eeb 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > @@ -499,6 +499,21 @@ static int igt_reset_nop_engine(void *arg) > > rq = intel_context_create_request(ce); > if (IS_ERR(rq)) { > + struct drm_printer p = > + drm_info_printer(gt->i915->drm.dev); > + intel_engine_dump(engine, &p, > + "%s(%s): failed to submit request\n", > + __func__, > + engine->name); > + > + > + GEM_TRACE("%s(%s): failed to submit request\n", > + __func__, > + engine->name); > + GEM_TRACE_DUMP(); > + > + intel_gt_set_wedged(gt); > + > err = PTR_ERR(rq); > break; > } > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Mon Jun 15 16:03:14 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 16:03:14 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_remove_unnecessary_conversion_to_bool?= In-Reply-To: <20200615043822.14206-1-bernard@vivo.com> References: <20200615043822.14206-1-bernard@vivo.com> Message-ID: <159223699444.16141.3112202990179713343@emeril.freedesktop.org> == Series Details == Series: drm/i915: remove unnecessary conversion to bool URL : https://patchwork.freedesktop.org/series/78372/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627_full -> Patchwork_17947_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17947_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_reloc@basic-spin-others at vcs0}: - shard-snb: [WARN][1] ([i915#2036]) -> [WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb5/igt at gem_exec_reloc@basic-spin-others at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-snb4/igt at gem_exec_reloc@basic-spin-others at vcs0.html Known issues ------------ Here are the changes found in Patchwork_17947_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-kbl1/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * igt at i915_module_load@reload: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-tglb5/igt at i915_module_load@reload.html * igt at i915_pm_rpm@system-suspend-modeset: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#151] / [i915#69]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl2/igt at i915_pm_rpm@system-suspend-modeset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl3/igt at i915_pm_rpm@system-suspend-modeset.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk7/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#62]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html * igt at kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#69]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl4/igt at kms_fbcon_fbt@psr-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl8/igt at kms_fbcon_fbt@psr-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#46]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl7/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl6/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#95]) +21 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-tglb8/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl6/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-iclb4/igt at kms_psr@psr2_cursor_render.html * igt at perf@polling-parameterized: - shard-iclb: [PASS][31] -> [FAIL][32] ([i915#1542]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb5/igt at perf@polling-parameterized.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-iclb6/igt at perf@polling-parameterized.html #### Possible fixes #### * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][33] ([i915#1936]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at gem_exec_balancer@sliced.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-tglb8/igt at gem_exec_balancer@sliced.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][35] ([i915#82]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-snb6/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [DMESG-WARN][37] ([i915#180]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at gem_exec_suspend@basic-s3.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-kbl4/igt at gem_exec_suspend@basic-s3.html * {igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a}: - shard-tglb: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-tglb5/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-apl2/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1: - shard-tglb: [DMESG-WARN][43] ([i915#402]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb7/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-tglb8/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html * igt at kms_flip@flip-vs-panning-interruptible at a-edp1: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +6 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl10/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [FAIL][47] ([i915#1928]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][49] ([fdo#108145] / [i915#265]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_cursor@pipe-a-primary-size-256: - shard-glk: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk9/igt at kms_plane_cursor@pipe-a-primary-size-256.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-glk1/igt at kms_plane_cursor@pipe-a-primary-size-256.html * igt at kms_properties@invalid-properties-atomic: - shard-apl: [DMESG-WARN][53] ([i915#95]) -> [PASS][54] +17 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl1/igt at kms_properties@invalid-properties-atomic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-apl2/igt at kms_properties@invalid-properties-atomic.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][55] ([i915#173]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb1/igt at kms_psr@no_drrs.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-iclb3/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb7/igt at kms_psr@psr2_cursor_plane_onoff.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-iclb2/igt at kms_psr@psr2_cursor_plane_onoff.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-tglb: [TIMEOUT][59] -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_psr@psr2_sprite_mmap_cpu.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-tglb8/igt at kms_psr@psr2_sprite_mmap_cpu.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-skl: [DMESG-FAIL][61] ([i915#1982]) -> [FAIL][62] ([i915#454]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl5/igt at i915_pm_dc@dc6-psr.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-skl10/igt at i915_pm_dc@dc6-psr.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [INCOMPLETE][64] ([i915#155]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_flip@flip-vs-suspend at a-dp1.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-kbl1/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite: - shard-tglb: [TIMEOUT][65] -> [SKIP][66] ([fdo#111825]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17947 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17947: 2581895c0fd0630d61a1ade5e61ff609439f68c9 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17947/index.html From patchwork at emeril.freedesktop.org Mon Jun 15 16:07:38 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 16:07:38 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/shmem-helper=3A_Fix_obj-=3Efilp_derefence?= In-Reply-To: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> References: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> Message-ID: <159223725846.16139.9690020915376218777@emeril.freedesktop.org> == Series Details == Series: drm/shmem-helper: Fix obj->filp derefence URL : https://patchwork.freedesktop.org/series/78378/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17952 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/index.html Known issues ------------ Here are the changes found in Patchwork_17952 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at vgem_basic@setversion: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at vgem_basic@setversion.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-tgl-y/igt at vgem_basic@setversion.html #### Possible fixes #### * igt at gem_flink_basic@flink-lifetime: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at modeset: - {fi-tgl-dsi}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at kms_busy@basic at modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-tgl-dsi/igt at kms_busy@basic at modeset.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][19] ([i915#62]) -> [SKIP][20] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-gdg-551 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17952 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17952: ce71e5b572884577644db2f7a3f09760105ca1dd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ce71e5b57288 drm/shmem-helper: Fix obj->filp derefence == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/index.html From michael.j.ruhl at intel.com Mon Jun 15 16:11:48 2020 From: michael.j.ruhl at intel.com (Ruhl, Michael J) Date: Mon, 15 Jun 2020 16:11:48 +0000 Subject: [Intel-gfx] [PATCH v2] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <20200615151449.32605-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> <20200615151449.32605-1-tvrtko.ursulin@linux.intel.com> Message-ID: <14063C7AD467DE4B82DEDB5C278E8663010F364871@fmsmsx107.amr.corp.intel.com> >-----Original Message----- >From: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> >Sent: Monday, June 15, 2020 11:15 AM >To: Intel-gfx at lists.freedesktop.org >Cc: Ursulin, Tvrtko <tvrtko.ursulin at intel.com>; Auld, Matthew ><matthew.auld at intel.com>; Chris Wilson <chris at chris-wilson.co.uk>; Ruhl, >Michael J <michael.j.ruhl at intel.com> >Subject: [PATCH v2] drm/i915: Remove redundant i915_request_await_object >in blit clears > >From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >One i915_request_await_object is enough and we keep the one under the >object lock so it is final. > >At the same time move async clflushing setup under the same locked >section and consolidate common code into a helper function. > >v2: > * Emit initial breadcrumbs after aways are set up. (Chris) > >Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >Cc: Matthew Auld <matthew.auld at intel.com> >Cc: Chris Wilson <chris at chris-wilson.co.uk> >Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> >--- > .../gpu/drm/i915/gem/i915_gem_object_blt.c | 52 ++++++++----------- > 1 file changed, 21 insertions(+), 31 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >index f457d7130491..bfdb32d46877 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >@@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context >*ce, struct i915_vma *vma) > intel_engine_pm_put(ce->engine); > } > >+static int >+move_obj_to_gpu(struct drm_i915_gem_object *obj, I am not understanding the name of this function. How is the object moved to the gpu? Is clflush a move? Or is it that it is moving to the gpu domain? What about: obj_flush_and_wait() or just: flush_and_wait() ? Or am I missing something? ? Mike >+ struct i915_request *rq, >+ bool write) >+{ >+ if (obj->cache_dirty & ~obj->cache_coherent) >+ i915_gem_clflush_object(obj, 0); >+ >+ return i915_request_await_object(rq, obj, write); >+} >+ > int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, > struct intel_context *ce, > u32 value) >@@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct >drm_i915_gem_object *obj, > if (unlikely(err)) > return err; > >- if (obj->cache_dirty & ~obj->cache_coherent) { >- i915_gem_object_lock(obj); >- i915_gem_clflush_object(obj, 0); >- i915_gem_object_unlock(obj); >- } >- > batch = intel_emit_vma_fill_blt(ce, vma, value); > if (IS_ERR(batch)) { > err = PTR_ERR(batch); >@@ -165,27 +170,22 @@ int i915_gem_object_fill_blt(struct >drm_i915_gem_object *obj, > if (unlikely(err)) > goto out_request; > >- err = i915_request_await_object(rq, obj, true); >- if (unlikely(err)) >- goto out_request; >- >- if (ce->engine->emit_init_breadcrumb) { >- err = ce->engine->emit_init_breadcrumb(rq); >- if (unlikely(err)) >- goto out_request; >- } >- > i915_vma_lock(vma); >- err = i915_request_await_object(rq, vma->obj, true); >+ err = move_obj_to_gpu(vma->obj, rq, true); > if (err == 0) > err = i915_vma_move_to_active(vma, rq, >EXEC_OBJECT_WRITE); > i915_vma_unlock(vma); > if (unlikely(err)) > goto out_request; > >- err = ce->engine->emit_bb_start(rq, >- batch->node.start, batch->node.size, >- 0); >+ if (ce->engine->emit_init_breadcrumb) >+ err = ce->engine->emit_init_breadcrumb(rq); >+ >+ if (likely(!err)) >+ err = ce->engine->emit_bb_start(rq, >+ batch->node.start, >+ batch->node.size, >+ 0); > out_request: > if (unlikely(err)) > i915_request_set_error_once(rq, err); >@@ -317,16 +317,6 @@ struct i915_vma *intel_emit_vma_copy_blt(struct >intel_context *ce, > return ERR_PTR(err); > } > >-static int move_to_gpu(struct i915_vma *vma, struct i915_request *rq, bool >write) >-{ >- struct drm_i915_gem_object *obj = vma->obj; >- >- if (obj->cache_dirty & ~obj->cache_coherent) >- i915_gem_clflush_object(obj, 0); >- >- return i915_request_await_object(rq, obj, write); >-} >- > int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, > struct drm_i915_gem_object *dst, > struct intel_context *ce) >@@ -375,7 +365,7 @@ int i915_gem_object_copy_blt(struct >drm_i915_gem_object *src, > goto out_request; > > for (i = 0; i < ARRAY_SIZE(vma); i++) { >- err = move_to_gpu(vma[i], rq, i); >+ err = move_obj_to_gpu(vma[i]->obj, rq, i); > if (unlikely(err)) > goto out_unlock; > } >-- >2.20.1 From tvrtko.ursulin at linux.intel.com Mon Jun 15 16:15:38 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 15 Jun 2020 17:15:38 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <14063C7AD467DE4B82DEDB5C278E8663010F364871@fmsmsx107.amr.corp.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> <20200615151449.32605-1-tvrtko.ursulin@linux.intel.com> <14063C7AD467DE4B82DEDB5C278E8663010F364871@fmsmsx107.amr.corp.intel.com> Message-ID: <d99797ba-a7fe-342c-c98e-d606d53ac116@linux.intel.com> On 15/06/2020 17:11, Ruhl, Michael J wrote: >> -----Original Message----- >> From: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> >> Sent: Monday, June 15, 2020 11:15 AM >> To: Intel-gfx at lists.freedesktop.org >> Cc: Ursulin, Tvrtko <tvrtko.ursulin at intel.com>; Auld, Matthew >> <matthew.auld at intel.com>; Chris Wilson <chris at chris-wilson.co.uk>; Ruhl, >> Michael J <michael.j.ruhl at intel.com> >> Subject: [PATCH v2] drm/i915: Remove redundant i915_request_await_object >> in blit clears >> >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> One i915_request_await_object is enough and we keep the one under the >> object lock so it is final. >> >> At the same time move async clflushing setup under the same locked >> section and consolidate common code into a helper function. >> >> v2: >> * Emit initial breadcrumbs after aways are set up. (Chris) >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> Cc: Matthew Auld <matthew.auld at intel.com> >> Cc: Chris Wilson <chris at chris-wilson.co.uk> >> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> >> --- >> .../gpu/drm/i915/gem/i915_gem_object_blt.c | 52 ++++++++----------- >> 1 file changed, 21 insertions(+), 31 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> index f457d7130491..bfdb32d46877 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >> @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context >> *ce, struct i915_vma *vma) >> intel_engine_pm_put(ce->engine); >> } >> >> +static int >> +move_obj_to_gpu(struct drm_i915_gem_object *obj, > > I am not understanding the name of this function. > > How is the object moved to the gpu? Is clflush a move? Or is > it that it is moving to the gpu domain? > > What about: > > obj_flush_and_wait() > > or just: > > flush_and_wait() > > ? > > Or am I missing something? ? Yes, the fact I have renamed the existing move_to_gpu to move_obj_to_gpu while moving it up in the file and so risked falling victim to bike shedding now. :D Regards, Tvrtko > > Mike > >> + struct i915_request *rq, >> + bool write) >> +{ >> + if (obj->cache_dirty & ~obj->cache_coherent) >> + i915_gem_clflush_object(obj, 0); >> + >> + return i915_request_await_object(rq, obj, write); >> +} >> + >> int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, >> struct intel_context *ce, >> u32 value) >> @@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct >> drm_i915_gem_object *obj, >> if (unlikely(err)) >> return err; >> >> - if (obj->cache_dirty & ~obj->cache_coherent) { >> - i915_gem_object_lock(obj); >> - i915_gem_clflush_object(obj, 0); >> - i915_gem_object_unlock(obj); >> - } >> - >> batch = intel_emit_vma_fill_blt(ce, vma, value); >> if (IS_ERR(batch)) { >> err = PTR_ERR(batch); >> @@ -165,27 +170,22 @@ int i915_gem_object_fill_blt(struct >> drm_i915_gem_object *obj, >> if (unlikely(err)) >> goto out_request; >> >> - err = i915_request_await_object(rq, obj, true); >> - if (unlikely(err)) >> - goto out_request; >> - >> - if (ce->engine->emit_init_breadcrumb) { >> - err = ce->engine->emit_init_breadcrumb(rq); >> - if (unlikely(err)) >> - goto out_request; >> - } >> - >> i915_vma_lock(vma); >> - err = i915_request_await_object(rq, vma->obj, true); >> + err = move_obj_to_gpu(vma->obj, rq, true); >> if (err == 0) >> err = i915_vma_move_to_active(vma, rq, >> EXEC_OBJECT_WRITE); >> i915_vma_unlock(vma); >> if (unlikely(err)) >> goto out_request; >> >> - err = ce->engine->emit_bb_start(rq, >> - batch->node.start, batch->node.size, >> - 0); >> + if (ce->engine->emit_init_breadcrumb) >> + err = ce->engine->emit_init_breadcrumb(rq); >> + >> + if (likely(!err)) >> + err = ce->engine->emit_bb_start(rq, >> + batch->node.start, >> + batch->node.size, >> + 0); >> out_request: >> if (unlikely(err)) >> i915_request_set_error_once(rq, err); >> @@ -317,16 +317,6 @@ struct i915_vma *intel_emit_vma_copy_blt(struct >> intel_context *ce, >> return ERR_PTR(err); >> } >> >> -static int move_to_gpu(struct i915_vma *vma, struct i915_request *rq, bool >> write) >> -{ >> - struct drm_i915_gem_object *obj = vma->obj; >> - >> - if (obj->cache_dirty & ~obj->cache_coherent) >> - i915_gem_clflush_object(obj, 0); >> - >> - return i915_request_await_object(rq, obj, write); >> -} >> - >> int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, >> struct drm_i915_gem_object *dst, >> struct intel_context *ce) >> @@ -375,7 +365,7 @@ int i915_gem_object_copy_blt(struct >> drm_i915_gem_object *src, >> goto out_request; >> >> for (i = 0; i < ARRAY_SIZE(vma); i++) { >> - err = move_to_gpu(vma[i], rq, i); >> + err = move_obj_to_gpu(vma[i]->obj, rq, i); >> if (unlikely(err)) >> goto out_unlock; >> } >> -- >> 2.20.1 > From chris at chris-wilson.co.uk Mon Jun 15 16:16:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 17:16:50 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <20200615151449.32605-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> <20200615151449.32605-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159223781010.2981.3500655964984382451@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-15 16:14:49) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > One i915_request_await_object is enough and we keep the one under the > object lock so it is final. > > At the same time move async clflushing setup under the same locked > section and consolidate common code into a helper function. > > v2: > * Emit initial breadcrumbs after aways are set up. (Chris) s/aways/awaits/ > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > Cc: Matthew Auld <matthew.auld at intel.com> > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> > --- > .../gpu/drm/i915/gem/i915_gem_object_blt.c | 52 ++++++++----------- > 1 file changed, 21 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > index f457d7130491..bfdb32d46877 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c > @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context *ce, struct i915_vma *vma) > intel_engine_pm_put(ce->engine); > } > > +static int > +move_obj_to_gpu(struct drm_i915_gem_object *obj, > + struct i915_request *rq, > + bool write) * shrug, I prefer to think in terms of vma, but even vma are unlikely to be the final form here. Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From mika.kuoppala at linux.intel.com Mon Jun 15 16:16:30 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 15 Jun 2020 19:16:30 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Add a safety submission flush in the heartbeat In-Reply-To: <20200615131120.18948-1-chris@chris-wilson.co.uk> References: <20200615123920.17749-3-chris@chris-wilson.co.uk> <20200615131120.18948-1-chris@chris-wilson.co.uk> Message-ID: <877dw89ue9.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Just in case everything fails (like for example "missed interrupt > syndrome" on Sandybridge), always flush the submission tasklet from the > heartbeat. This papers over such issues, but will still appear as a > second long glitch, and prevents us from detecting it unless we happen > to be performing a timed test. > > v2: We rely on flush_submission() synchronizing with the tasklet on > another CPU. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 +++++++++---------- > .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +++ > 2 files changed, 14 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index d613cf31970c..31049e0bdb57 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1094,19 +1094,18 @@ void intel_engine_flush_submission(struct intel_engine_cs *engine) > { > struct tasklet_struct *t = &engine->execlists.tasklet; > > - if (__tasklet_is_scheduled(t)) { > - local_bh_disable(); > - if (tasklet_trylock(t)) { > - /* Must wait for any GPU reset in progress. */ > - if (__tasklet_is_enabled(t)) > - t->func(t->data); > - tasklet_unlock(t); > - } > - local_bh_enable(); > + /* Synchronise and wait for the tasklet on another CPU */ > + tasklet_kill(t); > + > + /* Having cancelled the tasklet, ensure that is run */ > + local_bh_disable(); > + if (tasklet_trylock(t)) { > + /* Must wait for any GPU reset in progress. */ > + if (__tasklet_is_enabled(t)) On heartbeat context this could be an assertion I think. But it is difficult to enforce hw sanity and still please the user. They will curse on glitch, even tho thye are saved! Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> -Mika > + t->func(t->data); > + tasklet_unlock(t); > } > - > - /* Otherwise flush the tasklet if it was running on another cpu */ > - tasklet_unlock_wait(t); > + local_bh_enable(); > } > > /** > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > index f67ad937eefb..cd20fb549b38 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c > @@ -65,6 +65,9 @@ static void heartbeat(struct work_struct *wrk) > struct intel_context *ce = engine->kernel_context; > struct i915_request *rq; > > + /* Just in case everything has gone horribly wrong, give it a kick */ > + intel_engine_flush_submission(engine); > + > rq = engine->heartbeat.systole; > if (rq && i915_request_completed(rq)) { > i915_request_put(rq); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From ville.syrjala at linux.intel.com Mon Jun 15 16:19:45 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 15 Jun 2020 19:19:45 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL In-Reply-To: <20200612193859.GB7611@intel.com> References: <20200604190612.GI6112@intel.com> <fea323968324ceefe813d34d80fdd9779614aa01.camel@intel.com> <20200604210319.GJ6112@intel.com> <20200612182542.GA7458@intel.com> <20200612183637.GL6112@intel.com> <20200612184413.GC7458@intel.com> <20200612190119.GN6112@intel.com> <20200612191224.GA7611@intel.com> <20200612192131.GO6112@intel.com> <20200612193859.GB7611@intel.com> Message-ID: <20200615161945.GP6112@intel.com> On Fri, Jun 12, 2020 at 12:38:59PM -0700, Manasi Navare wrote: > On Fri, Jun 12, 2020 at 10:21:31PM +0300, Ville Syrj?l? wrote: > > On Fri, Jun 12, 2020 at 12:12:25PM -0700, Manasi Navare wrote: > > > On Fri, Jun 12, 2020 at 10:01:19PM +0300, Ville Syrj?l? wrote: > > > > On Fri, Jun 12, 2020 at 11:44:13AM -0700, Manasi Navare wrote: > > > > > On Fri, Jun 12, 2020 at 09:36:37PM +0300, Ville Syrj?l? wrote: > > > > > > On Fri, Jun 12, 2020 at 11:25:42AM -0700, Manasi Navare wrote: > > > > > > > On Fri, Jun 05, 2020 at 12:03:19AM +0300, Ville Syrj?l? wrote: > > > > > > > > On Thu, Jun 04, 2020 at 08:01:03PM +0000, Almahallawy, Khaled wrote: > > > > > > > > > On Thu, 2020-06-04 at 22:06 +0300, Ville Syrj?l? wrote: > > > > > > > > > > On Thu, Jun 04, 2020 at 10:33:48AM +0530, Vidya Srinivas wrote: > > > > > > > > > > > Signed-off-by: Khaled Almahallawy <khaled.almahallawy at intel.com> > > > > > > > > > > > Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com> > > > > > > > > > > > --- > > > > > > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 40 > > > > > > > > > > > ++++++++++++++++++++++++++------- > > > > > > > > > > > 1 file changed, 32 insertions(+), 8 deletions(-) > > > > > > > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > > index 7223367171d1..44663e8ac9a1 100644 > > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > > > > > > @@ -5470,22 +5470,32 @@ intel_dp_autotest_phy_ddi_disable(struct > > > > > > > > > > > intel_dp *intel_dp) > > > > > > > > > > > struct drm_i915_private *dev_priv = to_i915(dev); > > > > > > > > > > > struct intel_crtc *crtc = to_intel_crtc(intel_dig_port- > > > > > > > > > > > >base.base.crtc); > > > > > > > > > > > enum pipe pipe = crtc->pipe; > > > > > > > > > > > - u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > > > > dp_tp_ctl_value; > > > > > > > > > > > + u32 trans_ddi_func_ctl_value, trans_conf_value, > > > > > > > > > > > dp_tp_ctl_value, trans_ddi_port_mask; > > > > > > > > > > > + enum port port = intel_dig_port->base.port; > > > > > > > > > > > + i915_reg_t dp_tp_reg; > > > > > > > > > > > + > > > > > > > > > > > + if (IS_ELKHARTLAKE(dev_priv)) { > > > > > > > > > > > + dp_tp_reg = DP_TP_CTL(port); > > > > > > > > > > > + trans_ddi_port_mask = TRANS_DDI_PORT_MASK; > > > > > > > > > > > + } else if (IS_TIGERLAKE(dev_priv)) { > > > > > > > > > > > + dp_tp_reg = TGL_DP_TP_CTL(pipe); > > > > > > > > > > > + trans_ddi_port_mask = TGL_TRANS_DDI_PORT_MASK; > > > > > > > > > > > + } > > > > > > > > > > > > > > > > > > > > > > trans_ddi_func_ctl_value = intel_de_read(dev_priv, > > > > > > > > > > > TRANS_DDI_FUNC_CTL(pip > > > > > > > > > > > e)); > > > > > > > > > > > trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); > > > > > > > > > > > - dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); > > > > > > > > > > > > > > > > > > > > > > + dp_tp_ctl_value = intel_de_read(dev_priv, dp_tp_reg); > > > > > > > > > > > trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | > > > > > > > > > > > - TGL_TRANS_DDI_PORT_MASK); > > > > > > > > > > > + trans_ddi_port_mask); > > > > > > > > > > > trans_conf_value &= ~PIPECONF_ENABLE; > > > > > > > > > > > dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; > > > > > > > > > > > > > > > > > > > > > > intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); > > > > > > > > > > > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), > > > > > > > > > > > trans_ddi_func_ctl_value); > > > > > > > > > > > - intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); > > > > > > > > > > > + intel_de_write(dev_priv, dp_tp_reg, dp_tp_ctl_value); > > > > > > > > > > > > > > > > > > > > All this ad-hoc modeset code really should not exist. It's going to > > > > > > > > > > have different bugs than the norma modeset paths, so compliance > > > > > > > > > > testing > > > > > > > > > > this special code proves absolutely nothing about the normal modeset > > > > > > > > > > code. IMO someone needs to take up the task of rewrtiting all this to > > > > > > > > > > just perform normal modesets. > > > > > > > > > > > > > > > > > > Agree. I've just found that we get kernel NULL pointer dereference and > > > > > > > > > panic when we try to access to_intel_crtc(intel_dig_port- > > > > > > > > > >base.base.crtc). > > > > > > > > > > > > > > > > Yeah, that's a legacy pointer which should no longer be used at all > > > > > > > > with atomic drivers. I'm slowly trying to clear out all this legacy > > > > > > > > cruft. The next step I had hoped to take was > > > > > > > > https://patchwork.freedesktop.org/series/76993/ but then this > > > > > > > > compliacnce stuff landed and threw another wrench into the works. > > > > > > > > > > > > > > We had several discussions on design of DP PHY compliance and the patches were on the M-L > > > > > > > for quite some time without anyone giving feedback on the actual design of whether they should > > > > > > > happen through modeset or directly from the PHY comp request short pulse. > > > > > > > My first feedback was also that this should happen through a complete modeset where after we get > > > > > > > PHY comp request we send a uevent like we do for link layer compliance and then trigger a full modeset. > > > > > > > But honestly that was just a lot of overhead and > > > > > > > The reason we decided to go with this ad hoc approach was that with PHY compliance request, > > > > > > > nothing really changes in terms of link parameters so we do not need to go through > > > > > > > a complete modeset request unlike link layer compliance where we need to do compute config > > > > > > > all over again to do the link params computation. > > > > > > > > > > > > > > Every PHY comp request first sends a link layer comp request that does a full modeset > > > > > > > and sets up the desired link rate/lane count. > > > > > > > Then with PHY request, all we need to do is disable pipe conf, dp_tp_ctl, set the PHY patterns > > > > > > > and renable the pipe conf and dp_tp_ctl without interfering and doing anything with a full modeset. > > > > > > > > > > > > > > Now i think if we need to scale this to other platforms, can we add a per platform hook > > > > > > > for handle_phy_request that gets the correct DP_TP_CTL etc and sets up the PHY patterns and > > > > > > > reenables the already set link? > > > > > > > > > > > > > > We have thoroughly tested this using the scopes and DPR 100 and it has been working correctly > > > > > > > with the existing IGT compliance tool so IMO no need to rewrite the entire set of patches. > > > > > > > > > > > > > > Ville, Khaled ? > > > > > > > > > > > > You're just multiplying the amount of work and bugs we have > > > > > > for every platform. > > > > > > > > > > > > And as said testing some special compliance paths proves > > > > > > pretty much nothing about the real code paths. So the only > > > > > > point of that code AFAICS it to tick some "we haz > > > > > > compliance code?" checkbox in some random spreadsheet instead > > > > > > of actually providing evidence that our real code works > > > > > > correctly. > > > > > > > > > > > > > > > > I thougt the whole point of PHY compliance is not to be able to see if the > > > > > driver can do a modeset but just to confirm that driver is able to send > > > > > the requested patterns out on already enabled link. So shouldnt doing this > > > > > directly through the phy request handling on short pulse suffice? > > > > > > > > You're not proving the driver proper can transmit the requested stuff, > > > > you're only proving the special compliance code can do that. I could > > > > easily break the normal codepaths and yet this magic compliance thing > > > > could still indicate that everything is hunky dory. > > > > > > > > > > > > > > > > > But if we want to insert this in the modeset what should be the flow: > > > > > - AFter getting PHY request, store the requested PHY patterns, send a uevent > > > > > > > > You don't really need any uevent. We coukd do the stuff directly from > > > > the hotplug work. > > > > > > > > > - This will trigger a complete modeset, in this path for atomic check, see > > > > > if PHY compliance test active then ignore recomputing the parameters and > > > > > also in the commit tail, only disable the Pipeconf, dp_tp_ctl and send these patterns > > > > > and then reenable? > > > > > > > > We should just do a full modeset if possible. Randomly turning the > > > > pipe/etc. on/off without following the proper modeset sequence is > > > > dubious at best. > > > > > > how do we trigger a full modeset directly from the hotplug work just from > > > within the kernel? We faced the same problem with link layer compliance > > > and hence we decided to send the uevent there to trigger a ful modeset. > > > > The full modeset via userspace route is only needed if the resolution > > needs to be changed since that's something userspace gets to decide. > > If the current mode is still OK we can directly trigger the modeset > > from the kernel. Not sure if we do or not. > > > > We do a full modeset for HDMI when the sink forgets that scrambling > > was supposed to be on, and I'm a bit tempted to do the same for > > plain old DP retraining to get rid of the special case code for > > that (and to actually follow the modeset seqeunce properly when > > doing retraining). > > > > For retraining we dont have any special case code right, Yes we do. intel_dp_retrain_link(). > we just fallback and then send uevent. > Oh but do you mean like getting rid of setting the link status and forcing a full modeset etc? > > So for PHY compliance, we do something similar to calling modeset_pipe() from > intel_hdmi_reset_link()? So call this modeset_pipe from intel_dp_autotest_phy_pattern() after > storing the requested phy patterns in a compliance struct? The modeset moust be moved into the hotplug work. The dig_port work shouldn't do anything except stash the request somewhere and kick off the hotplug work. -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Mon Jun 15 16:33:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 16:33:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Remove_redundant_i915=5Frequest=5Fawait=5Fobject_in_bl?= =?utf-8?q?it_clears_=28rev2=29?= In-Reply-To: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159223880957.16138.11921184666347808602@emeril.freedesktop.org> == Series Details == Series: drm/i915: Remove redundant i915_request_await_object in blit clears (rev2) URL : https://patchwork.freedesktop.org/series/78374/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17953 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/index.html Known issues ------------ Here are the changes found in Patchwork_17953 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-byt-j1900/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at vgem_basic@setversion: - fi-tgl-y: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at vgem_basic@setversion.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-tgl-y/igt at vgem_basic@setversion.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][11] ([i915#1888]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at gem_flink_basic@flink-lifetime: - fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-tgl-y/igt at gem_flink_basic@flink-lifetime.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at modeset: - {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at kms_busy@basic at modeset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-tgl-dsi/igt at kms_busy@basic at modeset.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 44) ------------------------------ Additional (1): fi-gdg-551 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17953 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17953: ad451451c90b1e063dd032f5ed563f501ff0350c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ad451451c90b drm/i915: Remove redundant i915_request_await_object in blit clears == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/index.html From ville.syrjala at linux.intel.com Mon Jun 15 16:40:24 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 15 Jun 2020 19:40:24 +0300 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch In-Reply-To: <ee0340f8ea128ed2caa4a6882ded6cb28bf0d8d9.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-5-jose.souza@intel.com> <20200612163029.GK6112@intel.com> <ee0340f8ea128ed2caa4a6882ded6cb28bf0d8d9.camel@intel.com> Message-ID: <20200615164024.GQ6112@intel.com> On Fri, Jun 12, 2020 at 08:33:31PM +0000, Souza, Jose wrote: > On Fri, 2020-06-12 at 19:30 +0300, Ville Syrj?l? wrote: > > On Tue, May 26, 2020 at 03:14:46PM -0700, Jos? Roberto de Souza wrote: > > > All GEN12 platforms supports PSR2 selective fetch but not all GEN12 > > > platforms supports PSR2 hardware tracking(aka RKL). > > > > > > This feature consists in software program registers with the damaged > > > area of each plane this way hardware will only fetch from memory those > > > areas and sent the PSR2 selective update blocks to panel, saving even > > > more power but to it actually happen userspace needs to send the > > > damaged areas otherwise it will still fetch the whole plane as > > > fallback. > > > As today Gnome3 do not send damaged areas and the only compositor that > > > I'm aware that sets the damaged areas is Weston. > > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > > > > > So here implementing page flip part, it is still completely missing > > > frontbuffer modifications, that is why the enable_psr2_sel_fetch > > > parameter was added. > > > > > > The plan is to switch all GEN12 platforms to selective fetch when > > > ready, it will also depend in add some tests sending damaged areas. > > > I have a hacked version of kms_psr2_su with 3 planes that I can > > > cleanup and send in a few days(99% of PSR2 selective fetch changes was > > > done during my free time while bored during quarantine rainy days). > > > > > > BSpec: 55229 > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 5 + > > > .../drm/i915/display/intel_display_debugfs.c | 3 + > > > .../drm/i915/display/intel_display_types.h | 10 + > > > drivers/gpu/drm/i915/display/intel_psr.c | 329 +++++++++++++++++- > > > drivers/gpu/drm/i915/display/intel_psr.h | 10 + > > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 + > > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > > drivers/gpu/drm/i915/i915_params.c | 5 + > > > drivers/gpu/drm/i915/i915_params.h | 1 + > > > 9 files changed, 352 insertions(+), 15 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index b69878334040..984809208c29 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -11729,6 +11729,8 @@ static void i9xx_update_cursor(struct intel_plane *plane, > > > if (INTEL_GEN(dev_priv) >= 9) > > > skl_write_cursor_wm(plane, crtc_state); > > > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state); > > > + > > > if (plane->cursor.base != base || > > > plane->cursor.size != fbc_ctl || > > > plane->cursor.cntl != cntl) { > > > @@ -15115,6 +15117,8 @@ static void commit_pipe_config(struct intel_atomic_state *state, > > > > > > if (new_crtc_state->update_pipe) > > > intel_pipe_fastset(old_crtc_state, new_crtc_state); > > > + > > > + intel_psr2_program_trans_man_trk_ctl(new_crtc_state); > > > } > > > > > > if (dev_priv->display.atomic_update_watermarks) > > > @@ -15156,6 +15160,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > > > intel_color_load_luts(new_crtc_state); > > > > > > intel_pre_plane_update(state, crtc); > > > + intel_psr2_sel_fetch_update(state, crtc); > > > > > > if (new_crtc_state->update_pipe) > > > intel_encoders_update_pipe(state, crtc); > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > index 70525623bcdf..0f600974462b 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > > > su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); > > > seq_printf(m, "%d\t%d\n", frame, su_blocks); > > > } > > > + > > > + seq_printf(m, "PSR2 selective fetch: %s\n", > > > + enableddisabled(psr->psr2_sel_fetch_enabled)); > > > } > > > > > > unlock: > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > > > index 30b2767578dc..b77a512e5362 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -586,6 +586,13 @@ struct intel_plane_state { > > > u32 planar_slave; > > > > > > struct drm_intel_sprite_colorkey ckey; > > > + > > > + struct { > > > + u32 ctl; > > > + u32 pos; > > > + u32 offset; > > > + u32 size; > > > + } psr2_sel_fetch; > > > > Do we really need all that here? We don't store them for the normal > > plane updates either. > > For ctl we do, anyways could be removed if we store overlapping damage are in here so intel_psr2_program_plane_sel_fetch() would incorporate > intel_psr2_plane_sel_fetch_calc() code, both looks good to me. > > > > > > }; > > > > > > struct intel_initial_plane_config { > > > @@ -931,6 +938,7 @@ struct intel_crtc_state { > > > > > > bool has_psr; > > > bool has_psr2; > > > + bool enable_psr2_sel_fetch; > > > u32 dc3co_exitline; > > > > > > /* > > > @@ -1070,6 +1078,8 @@ struct intel_crtc_state { > > > > > > /* For DSB related info */ > > > struct intel_dsb *dsb; > > > + > > > + u32 psr2_sw_man_track_ctl; > > > }; > > > > > > enum intel_pipe_crc_source { > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > > > index 0c86e9e341a2..bc2a2e64fe2a 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > @@ -518,6 +518,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > > > else > > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > > > + intel_de_write(dev_priv, > > > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), > > > + PSR2_MAN_TRK_CTL_ENABLE); > > > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > > > + intel_de_write(dev_priv, > > > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); > > > + > > > /* > > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > > > * recommending keep this bit unset while PSR2 is enabled. > > > @@ -628,6 +636,38 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, > > > crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; > > > } > > > > > > +static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, > > > + struct intel_crtc_state *crtc_state) > > > +{ > > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); > > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > + struct intel_plane_state *plane_state; > > > + struct intel_plane *plane; > > > + int i; > > > + > > > + if (!i915_modparams.enable_psr2_sel_fetch) { > > > + drm_dbg_kms(&dev_priv->drm, > > > + "PSR2 sel fetch not enabled, disabled by parameter\n"); > > > + return false; > > > + } > > > + > > > + if (crtc_state->uapi.async_flip) { > > > + drm_dbg_kms(&dev_priv->drm, > > > + "PSR2 sel fetch not enabled, async flip enabled\n"); > > > + return false; > > > + } > > > > Not supported anyway. > > > > > + > > > + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { > > > + if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { > > > + drm_dbg_kms(&dev_priv->drm, > > > + "PSR2 sel fetch not enabled, plane rotated\n"); > > > + return false; > > > + } > > > + } > > > + > > > + return crtc_state->enable_psr2_sel_fetch = true; > > > +} > > > + > > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > > struct intel_crtc_state *crtc_state) > > > { > > > @@ -697,22 +737,17 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > > return false; > > > } > > > > > > - /* > > > - * Some platforms lack PSR2 HW tracking and instead require manual > > > - * tracking by software. In this case, the driver is required to track > > > - * the areas that need updates and program hardware to send selective > > > - * updates. > > > - * > > > - * So until the software tracking is implemented, PSR2 needs to be > > > - * disabled for platforms without PSR2 HW tracking. > > > - */ > > > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > > > - drm_dbg_kms(&dev_priv->drm, > > > - "No PSR2 HW tracking in the platform\n"); > > > - return false; > > > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > > > + if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > > > + !HAS_PSR_HW_TRACKING(dev_priv)) { > > > + drm_dbg_kms(&dev_priv->drm, > > > + "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); > > > + return false; > > > + } > > > } > > > > > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > > > + if (!crtc_state->enable_psr2_sel_fetch && > > > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { > > > drm_dbg_kms(&dev_priv->drm, > > > "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", > > > crtc_hdisplay, crtc_vdisplay, > > > @@ -863,6 +898,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, > > > val |= EXITLINE_ENABLE; > > > intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); > > > } > > > + > > > + if (HAS_PSR_HW_TRACKING(dev_priv)) > > > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, > > > + dev_priv->psr.psr2_sel_fetch_enabled ? > > > + IGNORE_PSR2_HW_TRACKING : 0); > > > } > > > > > > static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > > > @@ -884,7 +924,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > > > /* DC5/DC6 requires at least 6 idle frames */ > > > val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > > > dev_priv->psr.dc3co_exit_delay = val; > > > - > > > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; > > > /* > > > * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR > > > * will still keep the error set even after the reset done in the > > > @@ -1080,6 +1120,265 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) > > > intel_psr_exit(dev_priv); > > > } > > > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, > > > + const struct intel_crtc_state *crtc_state, > > > + const struct intel_plane_state *plane_state) > > > +{ > > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); > > > + enum pipe pipe = plane->pipe; > > > + > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > + !plane_state || > > > + !crtc_state->enable_psr2_sel_fetch) > > > + return; > > > + > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), > > > + plane_state->psr2_sel_fetch.ctl); > > > + if (!plane_state->psr2_sel_fetch.ctl || plane->id == PLANE_CURSOR) > > > + return; > > > + > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), > > > + plane_state->psr2_sel_fetch.pos); > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > > > + plane_state->psr2_sel_fetch.offset); > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), > > > + plane_state->psr2_sel_fetch.size); > > > +} > > > + > > > +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) > > > +{ > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > + struct i915_psr *psr = &dev_priv->psr; > > > + > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > + !crtc_state->enable_psr2_sel_fetch) > > > + return; > > > + > > > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), > > > + crtc_state->psr2_sw_man_track_ctl); > > > +} > > > + > > > +static void intel_psr2_plane_sel_fetch_calc(struct intel_plane_state *plane_state, > > > + struct drm_rect *clip) > > > +{ > > > + int color_plane = plane_state->planar_linked_plane && !plane_state->planar_slave; > > > + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); > > > + u32 val; > > > + > > > + if (plane->id == PLANE_CURSOR) > > > + return; > > > + > > > + val = (plane_state->color_plane[color_plane].y + clip->y1) << 16; > > > + val |= plane_state->color_plane[color_plane].x; > > > + plane_state->psr2_sel_fetch.offset = val; > > > + > > > + val = (clip->y1 + plane_state->uapi.crtc_y) << 16; > > > + val |= plane_state->uapi.crtc_x; > > > + plane_state->psr2_sel_fetch.pos = val; > > > + > > > + /* Sizes are 0 based */ > > > + val = (clip->y2 - clip->y1 - 1) << 16; > > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; > > > + plane_state->psr2_sel_fetch.size = val; > > > +} > > > + > > > +static void intel_psr2_trans_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, > > > + struct drm_rect *clip, > > > + bool full_update) > > > +{ > > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE; > > > + > > > + if (full_update) { > > > + val |= PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME; > > > + goto exit; > > > + } > > > + > > > + if (clip->y1 == -1) > > > + goto exit; > > > + > > > + val |= PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE; > > > + val |= PSR2_MAN_TRK_CTL_REGION_START_ADDR(clip->y1 / 4 + 1); > > > + val |= PSR2_MAN_TRK_CTL_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1); > > > +exit: > > > + crtc_state->psr2_sw_man_track_ctl = val; > > > +} > > > + > > > +static void intel_psr2_plane_sel_fetch_ctl_calc(struct intel_plane *plane, > > > + struct intel_plane_state *plane_state, > > > + bool enable) > > > +{ > > > + if (!enable) > > > + plane_state->psr2_sel_fetch.ctl = 0; > > > + else if (plane->id == PLANE_CURSOR) > > > + plane_state->psr2_sel_fetch.ctl = plane->cursor.cntl; > > > + else > > > + plane_state->psr2_sel_fetch.ctl = plane_state->ctl; > > > +} > > > + > > > +static void clip_update(struct drm_rect *overlap_damage_area, > > > + struct drm_rect *damage_area) > > > +{ > > > + if (overlap_damage_area->y1 == -1) { > > > + overlap_damage_area->y1 = damage_area->y1; > > > + overlap_damage_area->y2 = damage_area->y2; > > > + return; > > > + } > > > + > > > + if (damage_area->y1 < overlap_damage_area->y1) > > > + overlap_damage_area->y1 = damage_area->y1; > > > + > > > + if (damage_area->y2 > overlap_damage_area->y2) > > > + overlap_damage_area->y2 = damage_area->y2; > > > +} > > > + > > > +/* Update plane damage area if planes above moved or have alpha */ > > > +static void intel_psr2_pipe_dirty_areas_set(struct intel_plane_state *plane_state, > > > + struct intel_plane *plane, > > > + const struct drm_rect *pipe_dirty_areas, > > > + struct drm_rect *plane_clip) > > > +{ > > > + enum plane_id i; > > > + > > > + for (i = PLANE_CURSOR; i > plane->id; i--) { > > > + int j; > > > + > > > + for (j = 0; j < 2; j++) { > > > + struct drm_rect r = pipe_dirty_areas[i * 2 + j]; > > > + > > > + if (!drm_rect_width(&r)) > > > + continue; > > > + if (!drm_rect_intersect(&r, &plane_state->uapi.dst)) > > > + continue; > > > + > > > + r.y1 -= plane_state->uapi.crtc_y; > > > + r.y2 -= plane_state->uapi.crtc_y; > > > + clip_update(plane_clip, &r); > > > + } > > > + } > > > +} > > > + > > > +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > > > + struct intel_crtc *crtc) > > > +{ > > > + struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); > > > + struct intel_plane_state *new_plane_state, *old_plane_state; > > > + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = {}; > > > + struct drm_rect pipe_clip = { .y1 = -1 }; > > > + struct intel_plane *plane; > > > + bool full_update = false; > > > + int i; > > > + > > > + if (!crtc_state->enable_psr2_sel_fetch) > > > + return; > > > + > > > + /* > > > + * Load all the pipes areas where there is a plane with alpha or a plane > > > + * that moved or plane that the visibility changed in those > > > + * cases planes bellow it will need to be fetched in those intersection > > > + * areas even if they are not damaged in those areas. > > > + */ > > > + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, > > > + new_plane_state, i) { > > > + bool alpha, flip, dirty; > > > + > > > + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) > > > + continue; > > > + > > > + alpha = new_plane_state->uapi.alpha != U16_MAX; > > > + alpha |= old_plane_state->uapi.alpha != U16_MAX; > > > + flip = new_plane_state->uapi.fb != old_plane_state->uapi.fb; > > > + dirty = alpha && flip; > > > + dirty |= !drm_rect_equals(&new_plane_state->uapi.dst, > > > + &old_plane_state->uapi.dst); > > > + dirty |= new_plane_state->uapi.visible != > > > + old_plane_state->uapi.visible; > > > + if (!dirty) > > > + continue; > > > + > > > + if (old_plane_state->uapi.visible) > > > + pipe_dirty_areas[plane->id * 2] = old_plane_state->uapi.dst; > > > + if (new_plane_state->uapi.visible) > > > + pipe_dirty_areas[plane->id * 2 + 1] = new_plane_state->uapi.dst; > > > + } > > > + > > > + /* > > > + * Iterate over all planes, compute the damaged clip area also including > > > + * the pipe_dirty_areas, compute plane registers and update pipe damaged > > > + * area > > > + */ > > > + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, > > > + new_plane_state, i) { > > > + struct drm_rect plane_clip = { .y1 = -1 }; > > > + struct drm_mode_rect *clips; > > > + u32 num_clips; > > > + int j; > > > + > > > + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) > > > + continue; > > > + > > > + /* > > > + * TODO: Not clear how to handle planes with negative position, > > > + * also planes are not updated if they have a negative X > > > + * position so for now doing a full update in this cases > > > + */ > > > + if (new_plane_state->uapi.crtc_y < 0 || > > > + new_plane_state->uapi.crtc_x < 0) { > > > + full_update = true; > > > + break; > > > + } > > > + > > > + intel_psr2_plane_sel_fetch_ctl_calc(plane, new_plane_state, > > > + new_plane_state->uapi.visible); > > > + if (!new_plane_state->uapi.visible) > > > + continue; > > > + > > > + clips = drm_plane_get_damage_clips(&new_plane_state->uapi); > > > + num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi); > > > + > > > + /* > > > + * If plane moved mark the whole plane area as damaged so it > > > + * can be complete draw in the new position > > > + */ > > > + if (!drm_rect_equals(&new_plane_state->uapi.dst, > > > + &old_plane_state->uapi.dst)) { > > > + num_clips = 0; > > > + plane_clip.y1 = new_plane_state->uapi.src.y1 >> 16; > > > + plane_clip.y2 = new_plane_state->uapi.src.y2 >> 16; > > > + } else if (!num_clips) { > > > + /* > > > + * If plane don't have damage areas but the framebuffer > > > + * changed mark the whole plane as damaged > > > + */ > > > + if (new_plane_state->uapi.fb == old_plane_state->uapi.fb) > > > + continue; > > > + > > > + plane_clip.y1 = new_plane_state->uapi.src.y1 >> 16; > > > + plane_clip.y2 = new_plane_state->uapi.src.y2 >> 16; > > > + } > > > + > > > + for (j = 0; j < num_clips; j++) { > > > + struct drm_rect damage_area; > > > + > > > + damage_area.x1 = clips[j].x1; > > > + damage_area.x2 = clips[j].x2; > > > + damage_area.y1 = clips[j].y1; > > > + damage_area.y2 = clips[j].y2; > > > + clip_update(&plane_clip, &damage_area); > > > + } > > > + > > > + intel_psr2_pipe_dirty_areas_set(new_plane_state, plane, > > > + pipe_dirty_areas, &plane_clip); > > > + intel_psr2_plane_sel_fetch_calc(new_plane_state, &plane_clip); > > > + > > > + plane_clip.y1 += new_plane_state->uapi.crtc_y; > > > + plane_clip.y2 += new_plane_state->uapi.crtc_y; > > > + clip_update(&pipe_clip, &plane_clip); > > > + } > > > > This whole thing seems rather convoluted. Also using lots of uapi state > > in places where I don't expect to see any. > > Not sure from where I should get this information then, intel_plane_state don't have it. > > > > > I would suggest the correct way would be something like: > > 1) for_each_plane_in_state() > > hw.damage = translate_to_some_hw_coord_space(union(uapi.damages)) > > or just use the full plane size if we have scaling i guess > > 99% of the time the coordinates used are based on pipe coord space, only to calculate the plane overlapping damaged area is used plane coord space. > > > > > 2) need to add all affected planes to the state and set the appropriate > > bitmask, which may mean we want to track the planes' positions in the > > crtc state. I think atm we only have it in the plane state > > This looks a "or" to me, have all the planes added to the state when psr2 sel fetch is enabled or add track all the planes position in pipe. *Affected* planes, not all planes. Hmm. I guess affected planes are actually the ones whose selective fetch coordinates change. If they don't change then no need to add them to the state. Plane updates are rather expensive (lots of mmio) so I've generally tried to avoid pointless plane updates. But this whole thing might turn a bit annoying since we'd to keep adding affected planes until the total selective fetch region stops growing. I think that would probably want the two stage plane state compuation. So just blindly adding all of them would probably be simpler, albeit less efficient. > > Although the second one would avoid us to do plane calculations and plane register sometimes, in some cases where a plane above a non-modified plane > moves the non-modified plane bellow will need to be added to the state so the plane sel_fetch registers are written. > We could go with the easy one(add all planes to the state) and then move to the second one latter. > > > > > 3) translate the damage further into the final plane src coordinate > > space. Dunno if we have enough state around still to do it cleanly. > > I was thinking maybe it could be done alongside all the other plane > > surface calculations, but there might be a chicken vs. egg situation > > here since we probably want to do the plane check stuff before doing > > step 1, but plane check is also where we do the surface calculations. > > Dunno if we may just want to split the plane check into two stages > > As right now it depends mostly in uapi this could be moved to the check phase, did not left there because this will never have a error or a conflict > that will cause us to reject the state. > > > > > To keep things simple I guess what I'd suggest is to forget about the > > damage stuff in the first version of the series and just do full > > plane updates. That way we don't have to worry about so many coordinate > > space transformations. > > Do that would only save us the for bellow and the if to check if plane moved: > > for (j = 0; j < num_clips; j++) { > struct drm_rect damage_area; > > damage_area.x1 = clips[j].x1; > damage_area.x2 = clips[j].x2; > damage_area.y1 = clips[j].y1; > damage_area.y2 = clips[j].y2; > clip_update(&plane_clip, &damage_area); > } That's just some minor detail. The real issue is converting the damage between the various coordinate spaces we have for planes (original fb relative src coordiantes, final SURF relative src coordinates, crtc relative dst coordinates, and also the hw vs. uapi stuff affects this stuff). -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Mon Jun 15 16:46:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 16:46:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Remove_redundant_i915=5Frequest=5Fawait=5Fobject_in_bl?= =?utf-8?q?it_clears?= In-Reply-To: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159223957863.16139.8370612319725453249@emeril.freedesktop.org> == Series Details == Series: drm/i915: Remove redundant i915_request_await_object in blit clears URL : https://patchwork.freedesktop.org/series/78374/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627_full -> Patchwork_17949_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17949_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@processes: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl2/igt at gem_ctx_persistence@processes.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-skl3/igt at gem_ctx_persistence@processes.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [PASS][3] -> [DMESG-FAIL][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl2/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-apl3/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-ytiled.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +9 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt: - shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb8/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-skl6/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-iclb3/igt at kms_psr@psr2_cursor_render.html * igt at kms_sequence@queue-idle: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#93] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at kms_sequence@queue-idle.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-kbl4/igt at kms_sequence@queue-idle.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +16 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-apl1/igt at kms_vblank@pipe-c-wait-busy-hang.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][23] -> [FAIL][24] ([i915#1820]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-kbl1/igt at perf_pmu@semaphore-busy at rcs0.html * igt at sysfs_timeslice_duration@timeout at vecs0: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1755]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl2/igt at sysfs_timeslice_duration@timeout at vecs0.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-skl4/igt at sysfs_timeslice_duration@timeout at vecs0.html #### Possible fixes #### * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][27] ([i915#1936]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at gem_exec_balancer@sliced.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-tglb3/igt at gem_exec_balancer@sliced.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][29] ([i915#82]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html * {igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a}: - shard-tglb: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-tglb7/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-apl7/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: - shard-apl: [DMESG-WARN][35] ([i915#95]) -> [PASS][36] +16 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl7/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-apl2/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html * igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2: - shard-glk: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk1/igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-glk6/igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1: - shard-tglb: [DMESG-WARN][39] ([i915#402]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb7/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-tglb3/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html * igt at kms_flip@flip-vs-panning-interruptible at a-edp1: - shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +9 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-skl3/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [FAIL][43] ([i915#1928]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-skl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][45] ([i915#173]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb1/igt at kms_psr@no_drrs.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-iclb6/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb8/igt at kms_psr@psr2_no_drrs.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-iclb2/igt at kms_psr@psr2_no_drrs.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-tglb: [TIMEOUT][49] -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_psr@psr2_sprite_mmap_cpu.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-tglb3/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][51] ([i915#1542]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb4/igt at perf@blocking-parameterized.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-iclb8/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][53] ([i915#454]) -> [SKIP][54] ([i915#468]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb3/igt at i915_pm_dc@dc6-dpms.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at i915_pm_dc@dc6-psr: - shard-skl: [DMESG-FAIL][55] ([i915#1982]) -> [FAIL][56] ([i915#454]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl5/igt at i915_pm_dc@dc6-psr.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-skl3/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][57] ([i915#1319] / [i915#1958]) -> [TIMEOUT][58] ([i915#1319]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at kms_content_protection@atomic.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-kbl7/igt at kms_content_protection@atomic.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [INCOMPLETE][60] ([i915#155]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_flip@flip-vs-suspend at a-dp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-kbl2/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite: - shard-tglb: [TIMEOUT][61] -> [SKIP][62] ([fdo#111825]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17949 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17949: 3c89ad48e5ffb2be20173ef5a9e42950d696d223 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17949/index.html From chris at chris-wilson.co.uk Mon Jun 15 16:50:11 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 17:50:11 +0100 Subject: [Intel-gfx] [CI 1/3] drm/i915/selftests: Disable preemptive heartbeats over preemption tests Message-ID: <20200615165013.22973-1-chris@chris-wilson.co.uk> Since the heartbeat may cause a preemption event, disable it over the preemption suppression tests. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index f651bdf7f191..91543494f595 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2282,7 +2282,7 @@ static int live_suppress_self_preempt(void *arg) if (igt_flush_test(gt->i915)) goto err_wedged; - intel_engine_pm_get(engine); + engine_heartbeat_disable(engine); engine->execlists.preempt_hang.count = 0; rq_a = spinner_create_request(&a.spin, @@ -2290,14 +2290,14 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_a)) { err = PTR_ERR(rq_a); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_a); if (!igt_wait_for_spinner(&a.spin, rq_a)) { pr_err("First client failed to start\n"); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_wedged; } @@ -2309,7 +2309,7 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_b)) { err = PTR_ERR(rq_b); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_b); @@ -2320,7 +2320,7 @@ static int live_suppress_self_preempt(void *arg) if (!igt_wait_for_spinner(&b.spin, rq_b)) { pr_err("Second client failed to start\n"); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); goto err_wedged; } @@ -2334,12 +2334,12 @@ static int live_suppress_self_preempt(void *arg) engine->name, engine->execlists.preempt_hang.count, depth); - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); err = -EINVAL; goto err_client_b; } - intel_engine_pm_put(engine); + engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) goto err_wedged; } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 16:50:13 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 17:50:13 +0100 Subject: [Intel-gfx] [CI 3/3] drm/i915/gt: Add a safety submission flush in the heartbeat In-Reply-To: <20200615165013.22973-1-chris@chris-wilson.co.uk> References: <20200615165013.22973-1-chris@chris-wilson.co.uk> Message-ID: <20200615165013.22973-3-chris@chris-wilson.co.uk> Just in case everything fails (like for example "missed interrupt syndrome" on Sandybridge), always flush the submission tasklet from the heartbeat. This papers over such issues, but will still appear as a second long glitch, and prevents us from detecting it unless we happen to be performing a timed test. v2: We rely on flush_submission() synchronizing with the tasklet on another CPU. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 23 +++++++++---------- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +++ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index d613cf31970c..31049e0bdb57 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1094,19 +1094,18 @@ void intel_engine_flush_submission(struct intel_engine_cs *engine) { struct tasklet_struct *t = &engine->execlists.tasklet; - if (__tasklet_is_scheduled(t)) { - local_bh_disable(); - if (tasklet_trylock(t)) { - /* Must wait for any GPU reset in progress. */ - if (__tasklet_is_enabled(t)) - t->func(t->data); - tasklet_unlock(t); - } - local_bh_enable(); + /* Synchronise and wait for the tasklet on another CPU */ + tasklet_kill(t); + + /* Having cancelled the tasklet, ensure that is run */ + local_bh_disable(); + if (tasklet_trylock(t)) { + /* Must wait for any GPU reset in progress. */ + if (__tasklet_is_enabled(t)) + t->func(t->data); + tasklet_unlock(t); } - - /* Otherwise flush the tasklet if it was running on another cpu */ - tasklet_unlock_wait(t); + local_bh_enable(); } /** diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index f67ad937eefb..cd20fb549b38 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -65,6 +65,9 @@ static void heartbeat(struct work_struct *wrk) struct intel_context *ce = engine->kernel_context; struct i915_request *rq; + /* Just in case everything has gone horribly wrong, give it a kick */ + intel_engine_flush_submission(engine); + rq = engine->heartbeat.systole; if (rq && i915_request_completed(rq)) { i915_request_put(rq); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 15 16:50:12 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 17:50:12 +0100 Subject: [Intel-gfx] [CI 2/3] drm/i915/selftests: Dump engine state and trace upon hanging after reset In-Reply-To: <20200615165013.22973-1-chris@chris-wilson.co.uk> References: <20200615165013.22973-1-chris@chris-wilson.co.uk> Message-ID: <20200615165013.22973-2-chris@chris-wilson.co.uk> If the engine dies after a reset, and so we fail to submit a request but need to be interrupted by the CI runner, dump the engine state. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 2af66f8ffbd2..1ea4935e0eeb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -499,6 +499,21 @@ static int igt_reset_nop_engine(void *arg) rq = intel_context_create_request(ce); if (IS_ERR(rq)) { + struct drm_printer p = + drm_info_printer(gt->i915->drm.dev); + intel_engine_dump(engine, &p, + "%s(%s): failed to submit request\n", + __func__, + engine->name); + + + GEM_TRACE("%s(%s): failed to submit request\n", + __func__, + engine->name); + GEM_TRACE_DUMP(); + + intel_gt_set_wedged(gt); + err = PTR_ERR(rq); break; } -- 2.20.1 From nirmodas at amd.com Mon Jun 15 16:38:21 2020 From: nirmodas at amd.com (Nirmoy) Date: Mon, 15 Jun 2020 18:38:21 +0200 Subject: [Intel-gfx] [PATCH 3/3] drm/mm: cleanup and improve next_hole_*_addr() In-Reply-To: <20200615145415.1775-3-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> <20200615145415.1775-3-christian.koenig@amd.com> Message-ID: <170daa8f-811b-8cec-8235-9da9af96243e@amd.com> Reviewed-by: Nirmoy Das <nirmoy.das at amd.com> On 6/15/20 4:54 PM, Christian K?nig wrote: > Skipping just one branch of the tree is not the most > effective approach. > > Instead use a macro to define the traversal functions and > sort out both branch sides. > > This improves the performance of the unit tests by > a factor of more than 4. > > Signed-off-by: Christian K?nig <christian.koenig at amd.com> > --- > drivers/gpu/drm/drm_mm.c | 106 +++++++++++++-------------------------- > 1 file changed, 34 insertions(+), 72 deletions(-) > > diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c > index 177a5df0fe95..a4a04d246135 100644 > --- a/drivers/gpu/drm/drm_mm.c > +++ b/drivers/gpu/drm/drm_mm.c > @@ -325,6 +325,11 @@ static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size) > return best; > } > > +static bool usable_hole_addr(struct rb_node *rb, u64 size) > +{ > + return rb && rb_hole_addr_to_node(rb)->subtree_max_hole >= size; > +} > + > static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64 size) > { > struct rb_node *rb = mm->holes_addr.rb_node; > @@ -333,7 +338,7 @@ static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64 size) > while (rb) { > u64 hole_start; > > - if (rb_hole_addr_to_node(rb)->subtree_max_hole < size) > + if (!usable_hole_addr(rb, size)) > break; > > node = rb_hole_addr_to_node(rb); > @@ -374,82 +379,39 @@ first_hole(struct drm_mm *mm, > } > > /** > - * next_hole_high_addr - returns next hole for a DRM_MM_INSERT_HIGH mode request > - * @entry: previously selected drm_mm_node > - * @size: size of the a hole needed for the request > - * > - * This function will verify whether left subtree of @entry has hole big enough > - * to fit the requtested size. If so, it will return previous node of @entry or > - * else it will return parent node of @entry > + * DECLARE_NEXT_HOLE_ADDR - macro to declare next hole functions > + * @name: name of function to declare > + * @first: first rb member to traverse (either rb_left or rb_right). > + * @last: last rb member to traverse (either rb_right or rb_left). > * > - * It will also skip the complete left subtree if subtree_max_hole of that > - * subtree is same as the subtree_max_hole of the @entry. > - * > - * Returns: > - * previous node of @entry if left subtree of @entry can serve the request or > - * else return parent of @entry > + * This macro declares a function to return the next hole of the addr rb tree. > + * While traversing the tree we take the searched size into account and only > + * visit branches with potential big enough holes. > */ > -static struct drm_mm_node * > -next_hole_high_addr(struct drm_mm_node *entry, u64 size) > -{ > - struct rb_node *rb_node, *left_rb_node, *parent_rb_node; > - struct drm_mm_node *left_node; > - > - if (!entry) > - return NULL; > > - rb_node = &entry->rb_hole_addr; > - if (rb_node->rb_left) { > - left_rb_node = rb_node->rb_left; > - parent_rb_node = rb_parent(rb_node); > - left_node = rb_entry(left_rb_node, > - struct drm_mm_node, rb_hole_addr); > - if (left_node->subtree_max_hole < size && > - parent_rb_node && parent_rb_node->rb_left != rb_node) > - return rb_hole_addr_to_node(parent_rb_node); > - } > - > - return rb_hole_addr_to_node(rb_prev(rb_node)); > +#define DECLARE_NEXT_HOLE_ADDR(name, first, last) \ > +static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size) \ > +{ \ > + struct rb_node *parent, *node = &entry->rb_hole_addr; \ > + \ > + if (!entry || RB_EMPTY_NODE(node)) \ > + return NULL; \ > + \ > + if (usable_hole_addr(node->first, size)) { \ > + node = node->first; \ > + while (usable_hole_addr(node->last, size)) \ > + node = node->last; \ > + return rb_hole_addr_to_node(node); \ > + } \ > + \ > + while ((parent = rb_parent(node)) && node == parent->first) \ > + node = parent; \ > + \ > + return rb_hole_addr_to_node(parent); \ > } > > -/** > - * next_hole_low_addr - returns next hole for a DRM_MM_INSERT_LOW mode request > - * @entry: previously selected drm_mm_node > - * @size: size of the a hole needed for the request > - * > - * This function will verify whether right subtree of @entry has hole big enough > - * to fit the requtested size. If so, it will return next node of @entry or > - * else it will return parent node of @entry > - * > - * It will also skip the complete right subtree if subtree_max_hole of that > - * subtree is same as the subtree_max_hole of the @entry. > - * > - * Returns: > - * next node of @entry if right subtree of @entry can serve the request or > - * else return parent of @entry > - */ > -static struct drm_mm_node * > -next_hole_low_addr(struct drm_mm_node *entry, u64 size) > -{ > - struct rb_node *rb_node, *right_rb_node, *parent_rb_node; > - struct drm_mm_node *right_node; > - > - if (!entry) > - return NULL; > - > - rb_node = &entry->rb_hole_addr; > - if (rb_node->rb_right) { > - right_rb_node = rb_node->rb_right; > - parent_rb_node = rb_parent(rb_node); > - right_node = rb_entry(right_rb_node, > - struct drm_mm_node, rb_hole_addr); > - if (right_node->subtree_max_hole < size && > - parent_rb_node && parent_rb_node->rb_right != rb_node) > - return rb_hole_addr_to_node(parent_rb_node); > - } > - > - return rb_hole_addr_to_node(rb_next(rb_node)); > -} > +DECLARE_NEXT_HOLE_ADDR(next_hole_high_addr, rb_left, rb_right) > +DECLARE_NEXT_HOLE_ADDR(next_hole_low_addr, rb_right, rb_left) > > static struct drm_mm_node * > next_hole(struct drm_mm *mm, From nirmodas at amd.com Mon Jun 15 16:54:47 2020 From: nirmodas at amd.com (Nirmoy) Date: Mon, 15 Jun 2020 18:54:47 +0200 Subject: [Intel-gfx] [PATCH 2/3] drm/mm: optimize find_hole() as well In-Reply-To: <20200615145415.1775-2-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> <20200615145415.1775-2-christian.koenig@amd.com> Message-ID: <060aa4b7-54ca-1621-4bf2-b018f7da0121@amd.com> Acked-by: Nirmoy Das <nirmoy.das at amd.com> On 6/15/20 4:54 PM, Christian K?nig wrote: > Abort early if there isn't enough space to allocate from a subtree. > > Signed-off-by: Christian K?nig <christian.koenig at amd.com> > --- > drivers/gpu/drm/drm_mm.c | 11 +++++++---- > drivers/gpu/drm/selftests/test-drm_mm.c | 11 ----------- > 2 files changed, 7 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c > index 425fcd3590e8..177a5df0fe95 100644 > --- a/drivers/gpu/drm/drm_mm.c > +++ b/drivers/gpu/drm/drm_mm.c > @@ -325,7 +325,7 @@ static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size) > return best; > } > > -static struct drm_mm_node *find_hole(struct drm_mm *mm, u64 addr) > +static struct drm_mm_node *find_hole_addr(struct drm_mm *mm, u64 addr, u64 size) > { > struct rb_node *rb = mm->holes_addr.rb_node; > struct drm_mm_node *node = NULL; > @@ -333,6 +333,9 @@ static struct drm_mm_node *find_hole(struct drm_mm *mm, u64 addr) > while (rb) { > u64 hole_start; > > + if (rb_hole_addr_to_node(rb)->subtree_max_hole < size) > + break; > + > node = rb_hole_addr_to_node(rb); > hole_start = __drm_mm_hole_node_start(node); > > @@ -358,10 +361,10 @@ first_hole(struct drm_mm *mm, > return best_hole(mm, size); > > case DRM_MM_INSERT_LOW: > - return find_hole(mm, start); > + return find_hole_addr(mm, start, size); > > case DRM_MM_INSERT_HIGH: > - return find_hole(mm, end); > + return find_hole_addr(mm, end, size); > > case DRM_MM_INSERT_EVICT: > return list_first_entry_or_null(&mm->hole_stack, > @@ -497,7 +500,7 @@ int drm_mm_reserve_node(struct drm_mm *mm, struct drm_mm_node *node) > return -ENOSPC; > > /* Find the relevant hole to add our node to */ > - hole = find_hole(mm, node->start); > + hole = find_hole_addr(mm, node->start, 0); > if (!hole) > return -ENOSPC; > > diff --git a/drivers/gpu/drm/selftests/test-drm_mm.c b/drivers/gpu/drm/selftests/test-drm_mm.c > index ca5f35def905..b879aedfc00d 100644 > --- a/drivers/gpu/drm/selftests/test-drm_mm.c > +++ b/drivers/gpu/drm/selftests/test-drm_mm.c > @@ -1981,16 +1981,6 @@ static int __igt_once(unsigned int mode) > } > > memset(&node, 0, sizeof(node)); > - err = drm_mm_insert_node_generic(&mm, &node, > - 2, 0, 0, > - mode | DRM_MM_INSERT_ONCE); > - if (!err) { > - pr_err("Unexpectedly inserted the node into the wrong hole: node.start=%llx\n", > - node.start); > - err = -EINVAL; > - goto err_node; > - } > - > err = drm_mm_insert_node_generic(&mm, &node, 2, 0, 0, mode); > if (err) { > pr_err("Could not insert the node into the available hole!\n"); > @@ -1998,7 +1988,6 @@ static int __igt_once(unsigned int mode) > goto err_hi; > } > > -err_node: > drm_mm_remove_node(&node); > err_hi: > drm_mm_remove_node(&rsvd_hi); From nirmodas at amd.com Mon Jun 15 16:36:25 2020 From: nirmodas at amd.com (Nirmoy) Date: Mon, 15 Jun 2020 18:36:25 +0200 Subject: [Intel-gfx] [PATCH 1/3] drm/mm: remove unused rb_hole_size() In-Reply-To: <20200615145415.1775-1-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> Message-ID: <77ebb52b-806f-8129-9237-06b0ea4515c2@amd.com> Reviewed-by: Nirmoy Das <nirmoy.das at amd.com> On 6/15/20 4:54 PM, Christian K?nig wrote: > Just some code cleanup. > > Signed-off-by: Christian K?nig <christian.koenig at amd.com> > --- > drivers/gpu/drm/drm_mm.c | 5 ----- > 1 file changed, 5 deletions(-) > > diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c > index 82d2888eb7fe..425fcd3590e8 100644 > --- a/drivers/gpu/drm/drm_mm.c > +++ b/drivers/gpu/drm/drm_mm.c > @@ -305,11 +305,6 @@ static inline struct drm_mm_node *rb_hole_addr_to_node(struct rb_node *rb) > return rb_entry_safe(rb, struct drm_mm_node, rb_hole_addr); > } > > -static inline u64 rb_hole_size(struct rb_node *rb) > -{ > - return rb_entry(rb, struct drm_mm_node, rb_hole_size)->hole_size; > -} > - > static struct drm_mm_node *best_hole(struct drm_mm *mm, u64 size) > { > struct rb_node *rb = mm->holes_size.rb_root.rb_node; From patchwork at emeril.freedesktop.org Mon Jun 15 17:08:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 17:08:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5BCI=2C1/3=5D_drm/i915/selftests=3A_D?= =?utf-8?q?isable_preemptive_heartbeats_over_preemption_tests?= In-Reply-To: <20200615165013.22973-1-chris@chris-wilson.co.uk> References: <20200615165013.22973-1-chris@chris-wilson.co.uk> Message-ID: <159224088293.16138.11431336191450835143@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/selftests: Disable preemptive heartbeats over preemption tests URL : https://patchwork.freedesktop.org/series/78380/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5227b0190b79 drm/i915/selftests: Disable preemptive heartbeats over preemption tests 031614ee83cc drm/i915/selftests: Dump engine state and trace upon hanging after reset -:28: CHECK:LINE_SPACING: Please don't use multiple blank lines #28: FILE: drivers/gpu/drm/i915/gt/selftest_hangcheck.c:509: + + total: 0 errors, 0 warnings, 1 checks, 21 lines checked 13826b79b2ed drm/i915/gt: Add a safety submission flush in the heartbeat From patchwork at emeril.freedesktop.org Mon Jun 15 17:08:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 17:08:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5BCI=2C1/3=5D_drm/i915/selftests=3A_Disab?= =?utf-8?q?le_preemptive_heartbeats_over_preemption_tests?= In-Reply-To: <20200615165013.22973-1-chris@chris-wilson.co.uk> References: <20200615165013.22973-1-chris@chris-wilson.co.uk> Message-ID: <159224092070.16140.16156926383920998198@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/selftests: Disable preemptive heartbeats over preemption tests URL : https://patchwork.freedesktop.org/series/78380/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Mon Jun 15 17:28:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 17:28:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BCI=2C1/3=5D_drm/i915/selftests=3A_Disable_?= =?utf-8?q?preemptive_heartbeats_over_preemption_tests?= In-Reply-To: <20200615165013.22973-1-chris@chris-wilson.co.uk> References: <20200615165013.22973-1-chris@chris-wilson.co.uk> Message-ID: <159224211567.16140.5992113094925329918@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/selftests: Disable preemptive heartbeats over preemption tests URL : https://patchwork.freedesktop.org/series/78380/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627 -> Patchwork_17954 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/index.html Known issues ------------ Here are the changes found in Patchwork_17954 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][1] -> [FAIL][2] ([i915#579]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#262]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][7] ([i915#1888]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at modeset: - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-dsi/igt at kms_busy@basic at modeset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-tgl-dsi/igt at kms_busy@basic at modeset.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][19] ([i915#62]) -> [SKIP][20] ([fdo#109271]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +6 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 31) ------------------------------ Missing (19): fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-snb-2520m fi-ilk-650 fi-ctg-p8600 fi-hsw-4770 fi-tgl-y fi-ivb-3770 fi-elk-e7500 fi-pnv-d510 fi-blb-e6850 fi-byt-n2820 fi-byt-clapper fi-bdw-samus fi-snb-2600 Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17954 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17954: 13826b79b2ed4a01413b0b89161fff737319f9e3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 13826b79b2ed drm/i915/gt: Add a safety submission flush in the heartbeat 031614ee83cc drm/i915/selftests: Dump engine state and trace upon hanging after reset 5227b0190b79 drm/i915/selftests: Disable preemptive heartbeats over preemption tests == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/index.html From patchwork at emeril.freedesktop.org Mon Jun 15 17:30:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 17:30:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/3=5D_drm/mm=3A_remove_unused_rb=5Fhole?= =?utf-8?b?X3NpemUoKQ==?= In-Reply-To: <20200615145415.1775-1-christian.koenig@amd.com> References: <20200615145415.1775-1-christian.koenig@amd.com> Message-ID: <159224222907.16139.6430906840021452793@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/mm: remove unused rb_hole_size() URL : https://patchwork.freedesktop.org/series/78376/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627_full -> Patchwork_17951_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17951_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - shard-tglb: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb5/igt at i915_module_load@reload.html * igt at i915_pm_rpm@system-suspend-modeset: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#165]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl1/igt at i915_pm_rpm@system-suspend-modeset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-kbl2/igt at i915_pm_rpm@system-suspend-modeset.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +5 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl1/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#95]) +18 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl3/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb5/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +10 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl3/igt at kms_plane_multiple@atomic-pipe-a-tiling-yf.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-skl9/igt at kms_plane_multiple@atomic-pipe-a-tiling-yf.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-iclb1/igt at kms_psr@psr2_cursor_render.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][19] -> [FAIL][20] ([i915#1820]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][21] ([i915#1936]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at gem_exec_balancer@sliced.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb8/igt at gem_exec_balancer@sliced.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][23] ([i915#82]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-snb6/igt at gem_exec_schedule@implicit-read-write at rcs0.html * {igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a}: - shard-tglb: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb5/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-apl7/igt at kms_big_fb@linear-64bpp-rotate-180.html - shard-glk: [DMESG-FAIL][29] ([i915#118] / [i915#95]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-glk6/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: - shard-apl: [DMESG-WARN][31] ([i915#95]) -> [PASS][32] +16 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl7/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-apl3/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html * igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2: - shard-glk: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk1/igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-glk8/igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-suspend at a-edp1: - shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +10 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl10/igt at kms_flip@flip-vs-suspend at a-edp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-skl4/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [FAIL][37] ([i915#1928]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][39] ([i915#173]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb1/igt at kms_psr@no_drrs.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-iclb7/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb7/igt at kms_psr@psr2_primary_mmap_gtt.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-tglb: [TIMEOUT][43] -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_psr@psr2_sprite_mmap_cpu.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb8/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][45] ([i915#31]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at kms_setmode@basic.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-kbl3/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +3 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][49] ([i915#1542]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb4/igt at perf@blocking-parameterized.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-iclb4/igt at perf@blocking-parameterized.html * igt at syncobj_wait@multi-wait-for-submit-unsubmitted-submitted: - shard-snb: [TIMEOUT][51] ([i915#1958]) -> [PASS][52] +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted-submitted.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-snb5/igt at syncobj_wait@multi-wait-for-submit-unsubmitted-submitted.html #### Warnings #### * igt at gem_exec_balancer@invalid-bonds: - shard-snb: [TIMEOUT][53] ([i915#1958]) -> [SKIP][54] ([fdo#109271]) +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb6/igt at gem_exec_balancer@invalid-bonds.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-snb5/igt at gem_exec_balancer@invalid-bonds.html * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][55] ([i915#1958]) -> [FAIL][56] ([i915#1930]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][57] ([i915#454]) -> [SKIP][58] ([i915#468]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb3/igt at i915_pm_dc@dc6-dpms.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at i915_pm_rc6_residency@media-rc6-accuracy: - shard-tglb: [SKIP][59] ([fdo#111719]) -> [SKIP][60] ([fdo#109289] / [fdo#111719]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at i915_pm_rc6_residency@media-rc6-accuracy.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb6/igt at i915_pm_rc6_residency@media-rc6-accuracy.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][61] ([i915#1319] / [i915#1958]) -> [TIMEOUT][62] ([i915#1319]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at kms_content_protection@atomic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-kbl3/igt at kms_content_protection@atomic.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite: - shard-tglb: [TIMEOUT][63] -> [SKIP][64] ([fdo#111825]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [DMESG-WARN][66] ([i915#1982]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111719]: https://bugs.freedesktop.org/show_bug.cgi?id=111719 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17951 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17951: ef8803bbb4c34b9aa3afeba137902113894fc5b8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17951/index.html From michael.j.ruhl at intel.com Mon Jun 15 17:58:49 2020 From: michael.j.ruhl at intel.com (Ruhl, Michael J) Date: Mon, 15 Jun 2020 17:58:49 +0000 Subject: [Intel-gfx] [PATCH v2] drm/i915: Remove redundant i915_request_await_object in blit clears In-Reply-To: <d99797ba-a7fe-342c-c98e-d606d53ac116@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> <20200615151449.32605-1-tvrtko.ursulin@linux.intel.com> <14063C7AD467DE4B82DEDB5C278E8663010F364871@fmsmsx107.amr.corp.intel.com> <d99797ba-a7fe-342c-c98e-d606d53ac116@linux.intel.com> Message-ID: <14063C7AD467DE4B82DEDB5C278E8663010F36497B@fmsmsx107.amr.corp.intel.com> >-----Original Message----- >From: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> >Sent: Monday, June 15, 2020 12:16 PM >To: Ruhl, Michael J <michael.j.ruhl at intel.com>; Intel- >gfx at lists.freedesktop.org >Cc: Ursulin, Tvrtko <tvrtko.ursulin at intel.com>; Auld, Matthew ><matthew.auld at intel.com>; Chris Wilson <chris at chris-wilson.co.uk> >Subject: Re: [PATCH v2] drm/i915: Remove redundant >i915_request_await_object in blit clears > > >On 15/06/2020 17:11, Ruhl, Michael J wrote: >>> -----Original Message----- >>> From: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> >>> Sent: Monday, June 15, 2020 11:15 AM >>> To: Intel-gfx at lists.freedesktop.org >>> Cc: Ursulin, Tvrtko <tvrtko.ursulin at intel.com>; Auld, Matthew >>> <matthew.auld at intel.com>; Chris Wilson <chris at chris-wilson.co.uk>; >Ruhl, >>> Michael J <michael.j.ruhl at intel.com> >>> Subject: [PATCH v2] drm/i915: Remove redundant >i915_request_await_object >>> in blit clears >>> >>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>> >>> One i915_request_await_object is enough and we keep the one under the >>> object lock so it is final. >>> >>> At the same time move async clflushing setup under the same locked >>> section and consolidate common code into a helper function. >>> >>> v2: >>> * Emit initial breadcrumbs after aways are set up. (Chris) >>> >>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>> Cc: Matthew Auld <matthew.auld at intel.com> >>> Cc: Chris Wilson <chris at chris-wilson.co.uk> >>> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> >>> --- >>> .../gpu/drm/i915/gem/i915_gem_object_blt.c | 52 ++++++++----------- >>> 1 file changed, 21 insertions(+), 31 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >>> b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >>> index f457d7130491..bfdb32d46877 100644 >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c >>> @@ -126,6 +126,17 @@ void intel_emit_vma_release(struct intel_context >>> *ce, struct i915_vma *vma) >>> intel_engine_pm_put(ce->engine); >>> } >>> >>> +static int >>> +move_obj_to_gpu(struct drm_i915_gem_object *obj, >> >> I am not understanding the name of this function. >> >> How is the object moved to the gpu? Is clflush a move? Or is >> it that it is moving to the gpu domain? >> >> What about: >> >> obj_flush_and_wait() >> >> or just: >> >> flush_and_wait() >> >> ? >> >> Or am I missing something? ? > >Yes, the fact I have renamed the existing move_to_gpu to move_obj_to_gpu >while moving it up in the file and so risked falling victim to bike >shedding now. :D Ok. Code path makes sense to me. Reviewed-by: Michael J. Ruhl <michael.j.ruhl at intel.com> M > >Regards, > >Tvrtko > >> >> Mike >> >>> + struct i915_request *rq, >>> + bool write) >>> +{ >>> + if (obj->cache_dirty & ~obj->cache_coherent) >>> + i915_gem_clflush_object(obj, 0); >>> + >>> + return i915_request_await_object(rq, obj, write); >>> +} >>> + >>> int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, >>> struct intel_context *ce, >>> u32 value) >>> @@ -143,12 +154,6 @@ int i915_gem_object_fill_blt(struct >>> drm_i915_gem_object *obj, >>> if (unlikely(err)) >>> return err; >>> >>> - if (obj->cache_dirty & ~obj->cache_coherent) { >>> - i915_gem_object_lock(obj); >>> - i915_gem_clflush_object(obj, 0); >>> - i915_gem_object_unlock(obj); >>> - } >>> - >>> batch = intel_emit_vma_fill_blt(ce, vma, value); >>> if (IS_ERR(batch)) { >>> err = PTR_ERR(batch); >>> @@ -165,27 +170,22 @@ int i915_gem_object_fill_blt(struct >>> drm_i915_gem_object *obj, >>> if (unlikely(err)) >>> goto out_request; >>> >>> - err = i915_request_await_object(rq, obj, true); >>> - if (unlikely(err)) >>> - goto out_request; >>> - >>> - if (ce->engine->emit_init_breadcrumb) { >>> - err = ce->engine->emit_init_breadcrumb(rq); >>> - if (unlikely(err)) >>> - goto out_request; >>> - } >>> - >>> i915_vma_lock(vma); >>> - err = i915_request_await_object(rq, vma->obj, true); >>> + err = move_obj_to_gpu(vma->obj, rq, true); >>> if (err == 0) >>> err = i915_vma_move_to_active(vma, rq, >>> EXEC_OBJECT_WRITE); >>> i915_vma_unlock(vma); >>> if (unlikely(err)) >>> goto out_request; >>> >>> - err = ce->engine->emit_bb_start(rq, >>> - batch->node.start, batch->node.size, >>> - 0); >>> + if (ce->engine->emit_init_breadcrumb) >>> + err = ce->engine->emit_init_breadcrumb(rq); >>> + >>> + if (likely(!err)) >>> + err = ce->engine->emit_bb_start(rq, >>> + batch->node.start, >>> + batch->node.size, >>> + 0); >>> out_request: >>> if (unlikely(err)) >>> i915_request_set_error_once(rq, err); >>> @@ -317,16 +317,6 @@ struct i915_vma *intel_emit_vma_copy_blt(struct >>> intel_context *ce, >>> return ERR_PTR(err); >>> } >>> >>> -static int move_to_gpu(struct i915_vma *vma, struct i915_request *rq, >bool >>> write) >>> -{ >>> - struct drm_i915_gem_object *obj = vma->obj; >>> - >>> - if (obj->cache_dirty & ~obj->cache_coherent) >>> - i915_gem_clflush_object(obj, 0); >>> - >>> - return i915_request_await_object(rq, obj, write); >>> -} >>> - >>> int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, >>> struct drm_i915_gem_object *dst, >>> struct intel_context *ce) >>> @@ -375,7 +365,7 @@ int i915_gem_object_copy_blt(struct >>> drm_i915_gem_object *src, >>> goto out_request; >>> >>> for (i = 0; i < ARRAY_SIZE(vma); i++) { >>> - err = move_to_gpu(vma[i], rq, i); >>> + err = move_obj_to_gpu(vma[i]->obj, rq, i); >>> if (unlikely(err)) >>> goto out_unlock; >>> } >>> -- >>> 2.20.1 >> From patchwork at emeril.freedesktop.org Mon Jun 15 18:13:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 18:13:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/shmem-helper=3A_Fix_obj-=3Efilp_derefence?= In-Reply-To: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> References: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> Message-ID: <159224480014.16141.3965256309574011963@emeril.freedesktop.org> == Series Details == Series: drm/shmem-helper: Fix obj->filp derefence URL : https://patchwork.freedesktop.org/series/78378/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627_full -> Patchwork_17952_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17952_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_eio@in-flight-suspend: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#69]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl10/igt at gem_eio@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl10/igt at gem_eio@in-flight-suspend.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][3] -> [FAIL][4] ([i915#454]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb1/igt at i915_pm_dc@dc6-psr.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-iclb6/igt at i915_pm_dc@dc6-psr.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk9/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#1928]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl4/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-edp1.html * igt at kms_flip_tiling@flip-to-y-tiled: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_flip_tiling@flip-to-y-tiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-kbl4/igt at kms_flip_tiling@flip-to-y-tiled.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb5/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-tglb8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl6/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-iclb3/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#95]) +22 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-apl1/igt at kms_vblank@pipe-c-wait-busy-hang.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][27] -> [FAIL][28] ([i915#1820]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-kbl4/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][29] ([i915#1936]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at gem_exec_balancer@sliced.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-tglb5/igt at gem_exec_balancer@sliced.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][31] ([i915#82]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-snb1/igt at gem_exec_schedule@implicit-read-write at rcs0.html * {igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a}: - shard-tglb: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-tglb7/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-apl7/igt at kms_big_fb@linear-64bpp-rotate-180.html - shard-glk: [DMESG-FAIL][37] ([i915#118] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: - shard-apl: [DMESG-WARN][39] ([i915#95]) -> [PASS][40] +21 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl7/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-apl2/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html * igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1: - shard-tglb: [DMESG-WARN][41] ([i915#402]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb7/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-tglb1/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html * igt at kms_flip@flip-vs-panning-interruptible at a-edp1: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +7 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl6/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl4/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_plane_cursor@pipe-a-primary-size-256: - shard-glk: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk9/igt at kms_plane_cursor@pipe-a-primary-size-256.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-glk5/igt at kms_plane_cursor@pipe-a-primary-size-256.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][49] ([i915#173]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb1/igt at kms_psr@no_drrs.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-iclb6/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-tglb: [TIMEOUT][51] -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_psr@psr2_sprite_mmap_cpu.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-tglb5/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +3 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb4/igt at kms_psr@psr2_suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb4/igt at perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-iclb2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][59] ([i915#658]) -> [SKIP][60] ([i915#588]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb4/igt at i915_pm_dc@dc3co-vpb-simulation.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-skl: [DMESG-FAIL][61] ([i915#1982]) -> [FAIL][62] ([i915#454]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl5/igt at i915_pm_dc@dc6-psr.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-skl1/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][63] ([i915#1319] / [i915#1958]) -> [TIMEOUT][64] ([i915#1319]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at kms_content_protection@atomic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-kbl3/igt at kms_content_protection@atomic.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][65] ([i915#1319]) -> [TIMEOUT][66] ([i915#1319] / [i915#1958]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_content_protection@atomic-dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-kbl4/igt at kms_content_protection@atomic-dpms.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [INCOMPLETE][68] ([i915#155]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_flip@flip-vs-suspend at a-dp1.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-kbl2/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite: - shard-tglb: [TIMEOUT][69] -> [SKIP][70] ([fdo#111825]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17952 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17952: ce71e5b572884577644db2f7a3f09760105ca1dd @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17952/index.html From gwan-gyeong.mun at intel.com Mon Jun 15 18:37:14 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Mon, 15 Jun 2020 18:37:14 +0000 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers In-Reply-To: <41bec38440596890bea141b564235340709d414e.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-4-jose.souza@intel.com> <0cd79dd50c476c01afddea6ca1ee2fe80b0b40c1.camel@intel.com> <a900639aa1065838eb841afbd4d8d3713fe9cf74.camel@intel.com> <41bec38440596890bea141b564235340709d414e.camel@intel.com> Message-ID: <9f6c388b49e0bb5c8045034ac64c4b710d1bc140.camel@intel.com> On Fri, 2020-06-12 at 21:49 +0000, Mun, Gwan-gyeong wrote: > On Fri, 2020-06-12 at 14:18 -0700, Souza, Jose wrote: > > On Fri, 2020-06-12 at 21:57 +0100, Mun, Gwan-gyeong wrote: > > > On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > > > > This registers will be used to implement PSR2 software > > > > tracking. > > > > > > > > BSpec: 55229 > > > > BSpec: 50424 > > > > BSpec: 50420 > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/i915_reg.h | 68 > > > > ++++++++++++++++++++++++++++++- > > > > -- > > > > 1 file changed, 63 insertions(+), 5 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > b/drivers/gpu/drm/i915/i915_reg.h > > > > index e9d50fe0f375..6f547e459d30 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -4566,6 +4566,18 @@ enum { > > > > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > > > > PSR2_SU_STATUS_SHIFT(frame)) > > > > #define PSR2_SU_STATUS_FRAMES 8 > > > > > > > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > > > > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > > > > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > > > > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > > > > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT > > > > (31) > > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK REG_GEN > > > > MASK(30, > > > > 21) > > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR(val) REG_FIE > > > > LD_PREP( > > > > PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val) > > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK REG_GEN > > > > MASK(20, 11) > > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR(val) REG_FIE > > > > LD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val) > > > > +#define PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME REG_BIT > > > > (3) > > > > +#define PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME REG_BIT > > > > (2) > > > > +#define PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE REG_BIT > > > > (1) > > > > + > > > As per Bspec, it would be better that the names of bit as below. > > > > > > PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > > > PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > > > PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE > > > > No problem in naming like this but MAN_TRK and SF is kind of > > redundant and the name was already big. > > Your call. > > > > > > /* VGA port control */ > > > > #define ADPA _MMIO(0x61100) > > > > #define PCH_ADPA _MMIO(0xe1100) > > > > @@ -7129,7 +7141,52 @@ enum { > > > > #define PLANE_COLOR_CTL(pipe, plane) \ > > > > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > > > > _PLANE_COLOR_CTL_2(pipe)) > > > > > > > > -#/* SKL new cursor registers */ > > > > +#define _PLANE_SEL_FETCH_BASE_1_A 0x70890 > > > > +#define _PLANE_SEL_FETCH_BASE_2_A 0x708B0 > > > > +#define _PLANE_SEL_FETCH_BASE_3_A 0x708D0 > > > > +#define _PLANE_SEL_FETCH_BASE_4_A 0x708F0 > > > > +#define _PLANE_SEL_FETCH_BASE_5_A 0x70920 > > > > +#define _PLANE_SEL_FETCH_BASE_6_A 0x70940 > > > > +#define _PLANE_SEL_FETCH_BASE_7_A 0x70960 > > > > +#define _PLANE_SEL_FETCH_BASE_CUR_A 0x70880 > > > > +#define _PLANE_SEL_FETCH_BASE_1_B 0x70990 > > > > + > > > And as per Bspec, the prefix _SEL_FETCH_PLANE_ is better than > > > _PLANE_SEL_FETCH_ . > > You mean just for the "internal" ones? For PLANE_SEL_FETCH_CTL, > > PLANE_SEL_FETCH_SIZE... would be better keep like this to match > > other > > plane register > > names. > Internals and externals. I also noticed your intention (match other > plane related registers), but when I checked other plane related > resiters, they followed bspec names. (But I am not confident on > register naming policy; we always have to follow documented register > names or not. ) > > > > +#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_1_A, > > > > \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_2_A, > > > > \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_3_A, > > > > \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_4_A, > > > > \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_5_A, > > > > \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_6_A, > > > > \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_7_A, > > > > \ > > > > + _PLANE_SEL_FETCH_B > > > > ASE_CUR_ > > > > A) > > > > +#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, > > > > _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A) It seems that indicates an wrong register name. IMHO, is it your intention like this? " #define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_B) "? > > > > +#define PLANE_SEL_FETCH_BASE(pipe, plane) > > > > (_PLANE_SEL_FETCH_BASE_1(pipe) - \ > > > > + _PLANE_SEL_FETCH_BAS > > > > E_1_A + > > > > \ > > > > + _PLANE_SEL_FETCH_BAS > > > > E_A(plan > > > > e)) > > > > + > > > > +#define _PLANE_SEL_FETCH_CTL_1_A 0x70890 > > > > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > + _PLANE_SEL_FETCH > > > > _CTL_1_A > > > > - \ > > > > + _PLANE_SEL_FETCH > > > > _BASE_1_ > > > > A) > > > > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) > > > > + > > > > +#define _PLANE_SEL_FETCH_POS_1_A 0x70894 > > > > +#define PLANE_SEL_FETCH_POS(pipe, plane) > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > + _PLANE_SEL_FETCH > > > > _POS_1_A > > > > - \ > > > > + _PLANE_SEL_FETCH > > > > _BASE_1_ > > > > A) > > > > + > > > > +#define _PLANE_SEL_FETCH_SIZE_1_A 0x70898 > > > > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > + _PLANE_SEL_FETC > > > > H_SIZE_1 > > > > _A - \ > > > > + _PLANE_SEL_FETC > > > > H_BASE_1 > > > > _A) > > > > + > > > > +#define _PLANE_SEL_FETCH_OFFSET_1_A 0x7089C > > > > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > + _PLANE_SEL_FE > > > > TCH_OFFS > > > > ET_1_A - \ > > > > + _PLANE_SEL_FE > > > > TCH_BASE > > > > _1_A) > > > > + > > > > +/* SKL new cursor registers */ > > > > #define _CUR_BUF_CFG_A 0x7017c > > > > #define _CUR_BUF_CFG_B 0x7117c > > > > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, > > > > _CUR_BUF_CFG_A, > > > > _CUR_BUF_CFG_B) > > > > @@ -7775,11 +7832,12 @@ enum { > > > > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > > > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << > > > > 2) > > > > > > > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > > > > -#define DPA_MASK_VBLANK_SRD (1 << 15) > > > > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > > +#define DPA_MASK_VBLANK_SRD (1 << 15) > > > > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > > > > > > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > > > > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Mon Jun 15 18:39:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 19:39:35 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Don't flush the tasklet if not setup Message-ID: <20200615183935.17389-1-chris@chris-wilson.co.uk> If the tasklet is not being used, don't try and flush it. Fixes: 594893870044 ("drm/i915/gt: Add a safety submission flush in the heartbeat") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 31049e0bdb57..045179c65c44 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1094,6 +1094,9 @@ void intel_engine_flush_submission(struct intel_engine_cs *engine) { struct tasklet_struct *t = &engine->execlists.tasklet; + if (!t->func) + return; + /* Synchronise and wait for the tasklet on another CPU */ tasklet_kill(t); -- 2.20.1 From mika.kuoppala at linux.intel.com Mon Jun 15 18:44:42 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Mon, 15 Jun 2020 21:44:42 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Don't flush the tasklet if not setup In-Reply-To: <20200615183935.17389-1-chris@chris-wilson.co.uk> References: <20200615183935.17389-1-chris@chris-wilson.co.uk> Message-ID: <874krc9nj9.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > If the tasklet is not being used, don't try and flush it. > > Fixes: 594893870044 ("drm/i915/gt: Add a safety submission flush in the heartbeat") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 31049e0bdb57..045179c65c44 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1094,6 +1094,9 @@ void intel_engine_flush_submission(struct intel_engine_cs *engine) > { > struct tasklet_struct *t = &engine->execlists.tasklet; > > + if (!t->func) > + return; > + > /* Synchronise and wait for the tasklet on another CPU */ > tasklet_kill(t); > > -- > 2.20.1 From rodrigo.vivi at intel.com Mon Jun 15 18:54:20 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Mon, 15 Jun 2020 11:54:20 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, hsw}_clear_kernel.c In-Reply-To: <AD48BB7FB99B174FBCC69E228F58B3B6B78F0D73@fmsmsx116.amr.corp.intel.com> References: <159163988890.30073.8976615673203599761@build.alporthouse.com> <20200610201807.191440-1-rodrigo.vivi@intel.com> <AD48BB7FB99B174FBCC69E228F58B3B6B78F0D73@fmsmsx116.amr.corp.intel.com> Message-ID: <20200615185420.GA334084@intel.com> On Fri, Jun 12, 2020 at 02:15:02PM -0700, Bloomfield, Jon wrote: > > -----Original Message----- > > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of > > Rodrigo Vivi > > Sent: Wednesday, June 10, 2020 1:18 PM > > To: intel-gfx at lists.freedesktop.org > > Cc: Alexandre Oliva <lxoliva at fsfla.org>; Nikula, Jani <jani.nikula at intel.com>; > > stable at vger.kernel.org; Chris Wilson <chris at chris-wilson.co.uk> > > Subject: [Intel-gfx] [PATCH] drm/i915: Include asm sources for {ivb, > > hsw}_clear_kernel.c > > > > Alexandre Oliva has recently removed these files from Linux Libre > > with concerns that the sources weren't available. > > > > The sources are available on IGT repository, and only open source > > tools are used to generate the {ivb,hsw}_clear_kernel.c files. > > > > However, the remaining concern from Alexandre Oliva was around > > GPL license and the source not been present when distributing > > the code. > > > > So, it looks like 2 alternatives are possible, the use of > > linux-firmware.git repository to store the blob or making sure > > that the source is also present in our tree. Since the goal > > is to limit the i915 firmware to only the micro-controller blobs > > let's make sure that we do include the asm sources here in our tree. > > > > Btw, I tried to have some diligence here and make sure that the > > asms that these commits are adding are truly the source for > > the mentioned files: > > > > igt$ ./scripts/generate_clear_kernel.sh -g ivb \ > > -m ~/mesa/build/src/intel/tools/i965_asm > > Output file not specified - using default file "ivb-cb_assembled" > > > > Generating gen7 CB Kernel assembled file "ivb_clear_kernel.c" > > for i915 driver... > > > > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/ivb_clear_kernel.c \ > > ivb_clear_kernel.c > > > > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:29:32 AM UTC > > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:00:54 AM PDT > > 61c61 > > < }; > > > }; > > \ No newline at end of file > > > > igt$ ./scripts/generate_clear_kernel.sh -g hsw \ > > -m ~/mesa/build/src/intel/tools/i965_asm > > Output file not specified - using default file "hsw-cb_assembled" > > > > Generating gen7.5 CB Kernel assembled file "hsw_clear_kernel.c" > > for i915 driver... > > > > igt$ diff ~/i915/drm-tip/drivers/gpu/drm/i915/gt/hsw_clear_kernel.c \ > > hsw_clear_kernel.c > > 5c5 > > < * Generated by: IGT Gpu Tools on Fri 21 Feb 2020 05:30:13 AM UTC > > > * Generated by: IGT Gpu Tools on Mon 08 Jun 2020 10:01:42 AM PDT > > 61c61 > > < }; > > > }; > > \ No newline at end of file > > > > Used IGT and Mesa master repositories from Fri Jun 5 2020) > > IGT: 53e8c878a6fb ("tests/kms_chamelium: Force reprobe after replugging > > the connector") > > Mesa: 5d13c7477eb1 ("radv: set keep_statistic_info with > > RADV_DEBUG=shaderstats") > > Mesa built with: meson build -D platforms=drm,x11 -D dri-drivers=i965 \ > > -D gallium-drivers=iris -D prefix=/usr \ > > -D libdir=/usr/lib64/ -Dtools=intel \ > > -Dkulkan-drivers=intel && ninja -C build > > > > v2: Header clean-up and include build instructions in a readme (Chris) > > Modified commit message to respect check-patch > > > > Reference: http://www.fsfla.org/pipermail/linux-libre/2020- > > June/003374.html > > Reference: http://www.fsfla.org/pipermail/linux-libre/2020- > > June/003375.html > > Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts") > > Cc: <stable at vger.kernel.org> # v5.7+ > > Cc: Alexandre Oliva <lxoliva at fsfla.org> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com> > > Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com> > > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > > Cc: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Jani Nikula <jani.nikula at intel.com> > > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> > > Reviewed-by: Jon Bloomfield <jon.bloomfield at intel.com> Thanks, pushed to dinq From patchwork at emeril.freedesktop.org Mon Jun 15 18:57:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 18:57:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Remove_redundant_i915=5Frequest=5Fawait=5Fobject_in_bl?= =?utf-8?q?it_clears_=28rev2=29?= In-Reply-To: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> References: <20200615140928.27336-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159224744002.16141.5132655641686500716@emeril.freedesktop.org> == Series Details == Series: drm/i915: Remove redundant i915_request_await_object in blit clears (rev2) URL : https://patchwork.freedesktop.org/series/78374/ State : success == Summary == CI Bug Log - changes from CI_DRM_8627_full -> Patchwork_17953_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17953_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][1] -> [DMESG-FAIL][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk7/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#300]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl10/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl3/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#46]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl1/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-iclb1/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#95]) +6 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-apl7/igt at kms_vblank@pipe-c-wait-busy-hang.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][19] -> [FAIL][20] ([i915#1820]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][21] ([i915#1936]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at gem_exec_balancer@sliced.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-tglb2/igt at gem_exec_balancer@sliced.html * {igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a}: - shard-tglb: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-tglb6/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-apl3/igt at kms_big_fb@linear-64bpp-rotate-180.html - shard-glk: [DMESG-FAIL][27] ([i915#118] / [i915#95]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1: - shard-tglb: [DMESG-WARN][29] ([i915#402]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb7/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-tglb2/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html * igt at kms_flip@flip-vs-panning-interruptible at a-edp1: - shard-skl: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32] +11 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl9/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [FAIL][35] ([i915#1928]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][37] ([i915#1188]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_cursor@pipe-a-primary-size-256: - shard-glk: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk9/igt at kms_plane_cursor@pipe-a-primary-size-256.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-glk1/igt at kms_plane_cursor@pipe-a-primary-size-256.html * igt at kms_properties@invalid-properties-atomic: - shard-apl: [DMESG-WARN][41] ([i915#95]) -> [PASS][42] +15 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl1/igt at kms_properties@invalid-properties-atomic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-apl3/igt at kms_properties@invalid-properties-atomic.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][43] ([i915#173]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb1/igt at kms_psr@no_drrs.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-iclb7/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb5/igt at kms_psr@psr2_cursor_mmap_cpu.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-tglb: [TIMEOUT][47] -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_psr@psr2_sprite_mmap_cpu.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-tglb2/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at syncobj_wait@multi-wait-for-submit-unsubmitted-submitted: - shard-snb: [TIMEOUT][49] ([i915#1958]) -> [PASS][50] +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb6/igt at syncobj_wait@multi-wait-for-submit-unsubmitted-submitted.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-snb4/igt at syncobj_wait@multi-wait-for-submit-unsubmitted-submitted.html #### Warnings #### * igt at gem_exec_balancer@invalid-bonds: - shard-snb: [TIMEOUT][51] ([i915#1958]) -> [SKIP][52] ([fdo#109271]) +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb6/igt at gem_exec_balancer@invalid-bonds.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-snb4/igt at gem_exec_balancer@invalid-bonds.html * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][53] ([i915#1958]) -> [FAIL][54] ([i915#1930]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-skl: [SKIP][55] ([fdo#109271] / [i915#658]) -> [INCOMPLETE][56] ([i915#198]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at i915_pm_dc@dc3co-vpb-simulation.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-skl5/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite: - shard-tglb: [TIMEOUT][57] -> [SKIP][58] ([fdo#111825]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17953 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17953: ad451451c90b1e063dd032f5ed563f501ff0350c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17953/index.html From jose.souza at intel.com Mon Jun 15 19:23:37 2020 From: jose.souza at intel.com (Souza, Jose) Date: Mon, 15 Jun 2020 19:23:37 +0000 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers In-Reply-To: <9f6c388b49e0bb5c8045034ac64c4b710d1bc140.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-4-jose.souza@intel.com> <0cd79dd50c476c01afddea6ca1ee2fe80b0b40c1.camel@intel.com> <a900639aa1065838eb841afbd4d8d3713fe9cf74.camel@intel.com> <41bec38440596890bea141b564235340709d414e.camel@intel.com> <9f6c388b49e0bb5c8045034ac64c4b710d1bc140.camel@intel.com> Message-ID: <9b14efe375bb34a2dd59b45ea747dda514b38161.camel@intel.com> On Mon, 2020-06-15 at 19:37 +0100, Mun, Gwan-gyeong wrote: > On Fri, 2020-06-12 at 21:49 +0000, Mun, Gwan-gyeong wrote: > > On Fri, 2020-06-12 at 14:18 -0700, Souza, Jose wrote: > > > On Fri, 2020-06-12 at 21:57 +0100, Mun, Gwan-gyeong wrote: > > > > On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > > > > > This registers will be used to implement PSR2 software > > > > > tracking. > > > > > > > > > > BSpec: 55229 > > > > > BSpec: 50424 > > > > > BSpec: 50420 > > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/i915_reg.h | 68 > > > > > ++++++++++++++++++++++++++++++- > > > > > -- > > > > > 1 file changed, 63 insertions(+), 5 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > > b/drivers/gpu/drm/i915/i915_reg.h > > > > > index e9d50fe0f375..6f547e459d30 100644 > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > > @@ -4566,6 +4566,18 @@ enum { > > > > > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > > > > > PSR2_SU_STATUS_SHIFT(frame)) > > > > > #define PSR2_SU_STATUS_FRAMES 8 > > > > > > > > > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > > > > > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > > > > > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > > > > > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > > > > > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT > > > > > (31) > > > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK REG_GEN > > > > > MASK(30, > > > > > 21) > > > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR(val) REG_FIE > > > > > LD_PREP( > > > > > PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val) > > > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK REG_GEN > > > > > MASK(20, 11) > > > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR(val) REG_FIE > > > > > LD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val) > > > > > +#define PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME REG_BIT > > > > > (3) > > > > > +#define PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME REG_BIT > > > > > (2) > > > > > +#define PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE REG_BIT > > > > > (1) > > > > > + > > > > As per Bspec, it would be better that the names of bit as below. > > > > > > > > PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > > > > PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > > > > PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE > > > > > > No problem in naming like this but MAN_TRK and SF is kind of > > > redundant and the name was already big. > > > Your call. > > > > > > > > /* VGA port control */ > > > > > #define ADPA _MMIO(0x61100) > > > > > #define PCH_ADPA _MMIO(0xe1100) > > > > > @@ -7129,7 +7141,52 @@ enum { > > > > > #define PLANE_COLOR_CTL(pipe, plane) \ > > > > > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > > > > > _PLANE_COLOR_CTL_2(pipe)) > > > > > > > > > > -#/* SKL new cursor registers */ > > > > > +#define _PLANE_SEL_FETCH_BASE_1_A 0x70890 > > > > > +#define _PLANE_SEL_FETCH_BASE_2_A 0x708B0 > > > > > +#define _PLANE_SEL_FETCH_BASE_3_A 0x708D0 > > > > > +#define _PLANE_SEL_FETCH_BASE_4_A 0x708F0 > > > > > +#define _PLANE_SEL_FETCH_BASE_5_A 0x70920 > > > > > +#define _PLANE_SEL_FETCH_BASE_6_A 0x70940 > > > > > +#define _PLANE_SEL_FETCH_BASE_7_A 0x70960 > > > > > +#define _PLANE_SEL_FETCH_BASE_CUR_A 0x70880 > > > > > +#define _PLANE_SEL_FETCH_BASE_1_B 0x70990 > > > > > + > > > > And as per Bspec, the prefix _SEL_FETCH_PLANE_ is better than > > > > _PLANE_SEL_FETCH_ . > > > You mean just for the "internal" ones? For PLANE_SEL_FETCH_CTL, > > > PLANE_SEL_FETCH_SIZE... would be better keep like this to match > > > other > > > plane register > > > names. > > Internals and externals. I also noticed your intention (match other > > plane related registers), but when I checked other plane related > > resiters, they followed bspec names. (But I am not confident on > > register naming policy; we always have to follow documented register > > names or not. ) > > > > > +#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_1_A, > > > > > \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_2_A, > > > > > \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_3_A, > > > > > \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_4_A, > > > > > \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_5_A, > > > > > \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_6_A, > > > > > \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_7_A, > > > > > \ > > > > > + _PLANE_SEL_FETCH_B > > > > > ASE_CUR_ > > > > > A) > > > > > +#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, > > > > > _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A) > > It seems that indicates an wrong register name. > IMHO, is it your intention like this? " #define > _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, _PLANE_SEL_FETCH_BASE_1_A, > _PLANE_SEL_FETCH_BASE_1_B) "? Yes, it should be _PLANE_SEL_FETCH_BASE_1_B, thanks for catching this. Will send this 4 patches in a few days with the requested fixes. > > > > > > +#define PLANE_SEL_FETCH_BASE(pipe, plane) > > > > > (_PLANE_SEL_FETCH_BASE_1(pipe) - \ > > > > > + _PLANE_SEL_FETCH_BAS > > > > > E_1_A + > > > > > \ > > > > > + _PLANE_SEL_FETCH_BAS > > > > > E_A(plan > > > > > e)) > > > > > + > > > > > +#define _PLANE_SEL_FETCH_CTL_1_A 0x70890 > > > > > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > + _PLANE_SEL_FETCH > > > > > _CTL_1_A > > > > > - \ > > > > > + _PLANE_SEL_FETCH > > > > > _BASE_1_ > > > > > A) > > > > > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) > > > > > + > > > > > +#define _PLANE_SEL_FETCH_POS_1_A 0x70894 > > > > > +#define PLANE_SEL_FETCH_POS(pipe, plane) > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > + _PLANE_SEL_FETCH > > > > > _POS_1_A > > > > > - \ > > > > > + _PLANE_SEL_FETCH > > > > > _BASE_1_ > > > > > A) > > > > > + > > > > > +#define _PLANE_SEL_FETCH_SIZE_1_A 0x70898 > > > > > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > + _PLANE_SEL_FETC > > > > > H_SIZE_1 > > > > > _A - \ > > > > > + _PLANE_SEL_FETC > > > > > H_BASE_1 > > > > > _A) > > > > > + > > > > > +#define _PLANE_SEL_FETCH_OFFSET_1_A 0x7089C > > > > > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > + _PLANE_SEL_FE > > > > > TCH_OFFS > > > > > ET_1_A - \ > > > > > + _PLANE_SEL_FE > > > > > TCH_BASE > > > > > _1_A) > > > > > + > > > > > +/* SKL new cursor registers */ > > > > > #define _CUR_BUF_CFG_A 0x7017c > > > > > #define _CUR_BUF_CFG_B 0x7117c > > > > > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, > > > > > _CUR_BUF_CFG_A, > > > > > _CUR_BUF_CFG_B) > > > > > @@ -7775,11 +7832,12 @@ enum { > > > > > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > > > > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << > > > > > 2) > > > > > > > > > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > > > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > > > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > > > > > -#define DPA_MASK_VBLANK_SRD (1 << 15) > > > > > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > > > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > > > +#define DPA_MASK_VBLANK_SRD (1 << 15) > > > > > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > > > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > > > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > > > > > > > > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > > > > > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Mon Jun 15 19:42:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 19:42:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BCI=2C1/3=5D_drm/i915/selftests=3A_Disable_?= =?utf-8?q?preemptive_heartbeats_over_preemption_tests?= In-Reply-To: <20200615165013.22973-1-chris@chris-wilson.co.uk> References: <20200615165013.22973-1-chris@chris-wilson.co.uk> Message-ID: <159225017855.16140.114868228443967591@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/3] drm/i915/selftests: Disable preemptive heartbeats over preemption tests URL : https://patchwork.freedesktop.org/series/78380/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8627_full -> Patchwork_17954_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17954_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17954_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17954_full: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@mock at requests: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at i915_selftest@mock at requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-kbl2/igt at i915_selftest@mock at requests.html - shard-tglb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb5/igt at i915_selftest@mock at requests.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-tglb2/igt at i915_selftest@mock at requests.html - shard-apl: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl1/igt at i915_selftest@mock at requests.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-apl6/igt at i915_selftest@mock at requests.html - shard-iclb: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb6/igt at i915_selftest@mock at requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-iclb7/igt at i915_selftest@mock at requests.html Known issues ------------ Here are the changes found in Patchwork_17954_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at gem_workarounds@suspend-resume-fd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-kbl4/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_selftest@mock at requests: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#58] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk7/igt at i915_selftest@mock at requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-glk8/igt at i915_selftest@mock at requests.html - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#198]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl7/igt at i915_selftest@mock at requests.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-skl10/igt at i915_selftest@mock at requests.html * igt at kms_flip@wf_vblank-ts-check-interruptible at a-hdmi-a1: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#1928]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk8/igt at kms_flip@wf_vblank-ts-check-interruptible at a-hdmi-a1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-glk8/igt at kms_flip@wf_vblank-ts-check-interruptible at a-hdmi-a1.html * igt at kms_flip_event_leak: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#165] / [i915#78]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at kms_flip_event_leak.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-kbl2/igt at kms_flip_event_leak.html * igt at kms_panel_fitting@atomic-fastset: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +13 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl2/igt at kms_panel_fitting@atomic-fastset.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-skl4/igt at kms_panel_fitting@atomic-fastset.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb2/igt at kms_psr@psr2_cursor_render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-iclb1/igt at kms_psr@psr2_cursor_render.html * igt at kms_sequence@queue-idle: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at kms_sequence@queue-idle.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-kbl2/igt at kms_sequence@queue-idle.html * igt at kms_vblank@pipe-c-wait-busy-hang: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#95]) +16 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl8/igt at kms_vblank@pipe-c-wait-busy-hang.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-apl7/igt at kms_vblank@pipe-c-wait-busy-hang.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][29] -> [FAIL][30] ([i915#1820]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_exec_balancer@sliced: - shard-tglb: [TIMEOUT][31] ([i915#1936]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at gem_exec_balancer@sliced.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-tglb3/igt at gem_exec_balancer@sliced.html * {igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a}: - shard-tglb: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-tglb1/igt at kms_atomic_transition@plane-all-transition-nonblocking-fencing at edp-1-pipe-a.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-apl4/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic: - shard-apl: [DMESG-WARN][37] ([i915#95]) -> [PASS][38] +16 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-apl7/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-apl3/igt at kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html * igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2: - shard-glk: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-glk1/igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-glk9/igt at kms_flip@2x-wf_vblank-ts-check at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1: - shard-tglb: [DMESG-WARN][41] ([i915#402]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb7/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-tglb3/igt at kms_flip@flip-vs-dpms-off-vs-modeset at a-edp1.html * igt at kms_flip@flip-vs-panning-interruptible at a-edp1: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +8 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl9/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-skl2/igt at kms_flip@flip-vs-panning-interruptible at a-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-skl6/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][47] ([i915#173]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb1/igt at kms_psr@no_drrs.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-iclb7/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-tglb: [TIMEOUT][49] -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_psr@psr2_sprite_mmap_cpu.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-tglb3/igt at kms_psr@psr2_sprite_mmap_cpu.html - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb8/igt at kms_psr@psr2_sprite_mmap_cpu.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +4 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][55] ([i915#1542]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-iclb4/igt at perf@blocking-parameterized.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-iclb6/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc6-psr: - shard-skl: [DMESG-FAIL][57] ([i915#1982]) -> [FAIL][58] ([i915#454]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-skl5/igt at i915_pm_dc@dc6-psr.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-skl8/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][59] ([i915#1319] / [i915#1958]) -> [TIMEOUT][60] ([i915#1319]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-kbl4/igt at kms_content_protection@atomic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-kbl2/igt at kms_content_protection@atomic.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite: - shard-tglb: [TIMEOUT][61] -> [SKIP][62] ([fdo#111825]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8627/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8627 -> Patchwork_17954 CI-20190529: 20190529 CI_DRM_8627: 593c112156feb0f6159814f2276a32c90f243823 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5710: f524eee47930601ad7b4cba9d40c26d68dc7d250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17954: 13826b79b2ed4a01413b0b89161fff737319f9e3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17954/index.html From chris at chris-wilson.co.uk Mon Jun 15 20:06:03 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 21:06:03 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise far preemption rollbacks Message-ID: <20200615200603.18827-1-chris@chris-wilson.co.uk> Not too long ago, we realised we had issues with a rolling back a context so far for a preemption request we considered the resubmit not to be a rollback but a forward roll. This means we would issue a lite restore instead of forcing a full restore, continuing execution of the old requests rather than causing a preemption. Add a selftest to exercise such a far rollback, such that if we were to skip the full restore, we would execute invalid instructions in the ring and hang. Note that while I was able to confirm that this causes us to do a lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") disabled), it did not trick the HW into rolling past the old RING_TAIL. Myybe on other HW. References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 150 +++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 91543494f595..dc11d8562d34 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -363,6 +363,155 @@ static int live_unlite_preempt(void *arg) return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); } +static int live_unlite_ring(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + struct igt_spinner spin; + enum intel_engine_id id; + int err = 0; + + /* + * Setup a preemption event that will cause almost the entire ring + * to be unwound, potentially fooling our intel_ring_direction() + * into emitting a forward lite-restore instead of the rollback. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + for_each_engine(engine, gt, id) { + struct intel_context *ce[2] = {}; + struct i915_request *rq; + struct igt_live_test t; + int n; + + if (!intel_engine_has_preemption(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { + err = -EIO; + break; + } + engine_heartbeat_disable(engine); + + for (n = 0; n < ARRAY_SIZE(ce); n++) { + struct intel_context *tmp; + + tmp = intel_context_create(engine); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + goto err_ce; + } + + err = intel_context_pin(tmp); + if (err) { + intel_context_put(tmp); + goto err_ce; + } + + memset32(tmp->ring->vaddr, + 0xdeadbeef, /* trigger a hang if executed */ + tmp->ring->vma->size / sizeof(u32)); + + ce[n] = tmp; + } + + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + i915_request_get(rq); + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(gt); + i915_request_put(rq); + err = -ETIME; + goto err_ce; + } + + /* Fill the ring, until we will cause a wrap */ + n = 0; + while (intel_ring_direction(ce[0]->ring, + rq->wa_tail, + ce[0]->ring->emit) <= 0) { + struct i915_request *tmp; + + tmp = intel_context_create_request(ce[0]); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + i915_request_put(rq); + goto err_ce; + } + + i915_request_add(tmp); + intel_engine_flush_submission(engine); + n++; + } + intel_engine_flush_submission(engine); + pr_debug("%s: Filled ring with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", + engine->name, n, + ce[0]->ring->size, + ce[0]->ring->tail, + ce[0]->ring->emit, + rq->tail); + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, + rq->tail, + ce[0]->ring->tail) <= 0); + i915_request_put(rq); + + /* Create a second request to preempt the first ring */ + rq = intel_context_create_request(ce[1]); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_get(rq); + i915_request_add(rq); + + err = wait_for_submit(engine, rq, HZ / 2); + i915_request_put(rq); + if (err) { + pr_err("%s: preemption request was not submited\n", + engine->name); + err = -ETIME; + } + + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", + engine->name, + ce[0]->ring->tail, ce[0]->ring->emit, + ce[1]->ring->tail, ce[1]->ring->emit); + +err_ce: + intel_engine_flush_submission(engine); + igt_spinner_end(&spin); + for (n = 0; n < ARRAY_SIZE(ce); n++) { + if (IS_ERR_OR_NULL(ce[n])) + break; + + intel_context_unpin(ce[n]); + intel_context_put(ce[n]); + } + engine_heartbeat_enable(engine); + if (igt_live_test_end(&t)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + return err; +} + static int live_pin_rewind(void *arg) { struct intel_gt *gt = arg; @@ -4374,6 +4523,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_sanitycheck), SUBTEST(live_unlite_switch), SUBTEST(live_unlite_preempt), + SUBTEST(live_unlite_ring), SUBTEST(live_pin_rewind), SUBTEST(live_hold_reset), SUBTEST(live_error_interrupt), -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 15 20:12:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 20:12:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Don=27t_flush_the_tasklet_if_not_setup?= In-Reply-To: <20200615183935.17389-1-chris@chris-wilson.co.uk> References: <20200615183935.17389-1-chris@chris-wilson.co.uk> Message-ID: <159225194554.16138.832652663374300815@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Don't flush the tasklet if not setup URL : https://patchwork.freedesktop.org/series/78382/ State : success == Summary == CI Bug Log - changes from CI_DRM_8629 -> Patchwork_17955 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/index.html Known issues ------------ Here are the changes found in Patchwork_17955 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1242]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at vgem_basic@dmabuf-export: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-tgl-y/igt at vgem_basic@dmabuf-export.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-tgl-y/igt at vgem_basic@dmabuf-export.html #### Possible fixes #### * igt at gem_flink_basic@bad-open: - fi-tgl-y: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-tgl-y/igt at gem_flink_basic@bad-open.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-tgl-y/igt at gem_flink_basic@bad-open.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][11] ([i915#1233]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-guc: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - fi-tgl-y: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_pipe_crc_basic@read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (34 -> 43) ------------------------------ Additional (11): fi-byt-j1900 fi-bwr-2160 fi-ilk-650 fi-hsw-4770 fi-gdg-551 fi-ivb-3770 fi-elk-e7500 fi-pnv-d510 fi-blb-e6850 fi-byt-n2820 fi-snb-2600 Missing (2): fi-bsw-cyan fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8629 -> Patchwork_17955 CI-20190529: 20190529 CI_DRM_8629: d5f177af226836ef59edf6dfaa7297c5a75fa089 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17955: 3a591b832d873af97d2401e09c5d1d8005ccbeb3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3a591b832d87 drm/i915/gt: Don't flush the tasklet if not setup == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/index.html From chris at chris-wilson.co.uk Mon Jun 15 20:14:06 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 15 Jun 2020 21:14:06 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise far preemption rollbacks In-Reply-To: <20200615200603.18827-1-chris@chris-wilson.co.uk> References: <20200615200603.18827-1-chris@chris-wilson.co.uk> Message-ID: <20200615201406.19286-1-chris@chris-wilson.co.uk> Not too long ago, we realised we had issues with a rolling back a context so far for a preemption request we considered the resubmit not to be a rollback but a forward roll. This means we would issue a lite restore instead of forcing a full restore, continuing execution of the old requests rather than causing a preemption. Add a selftest to exercise such a far rollback, such that if we were to skip the full restore, we would execute invalid instructions in the ring and hang. Note that while I was able to confirm that this causes us to do a lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") disabled), it did not trick the HW into rolling past the old RING_TAIL. Myybe on other HW. References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 150 +++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 91543494f595..3d088116a055 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -363,6 +363,155 @@ static int live_unlite_preempt(void *arg) return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); } +static int live_unlite_ring(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + struct igt_spinner spin; + enum intel_engine_id id; + int err = 0; + + /* + * Setup a preemption event that will cause almost the entire ring + * to be unwound, potentially fooling our intel_ring_direction() + * into emitting a forward lite-restore instead of the rollback. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + for_each_engine(engine, gt, id) { + struct intel_context *ce[2] = {}; + struct i915_request *rq; + struct igt_live_test t; + int n; + + if (!intel_engine_has_preemption(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { + err = -EIO; + break; + } + engine_heartbeat_disable(engine); + + for (n = 0; n < ARRAY_SIZE(ce); n++) { + struct intel_context *tmp; + + tmp = intel_context_create(engine); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + goto err_ce; + } + + err = intel_context_pin(tmp); + if (err) { + intel_context_put(tmp); + goto err_ce; + } + + memset32(tmp->ring->vaddr, + 0xdeadbeef, /* trigger a hang if executed */ + tmp->ring->vma->size / sizeof(u32)); + + ce[n] = tmp; + } + + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + i915_request_get(rq); + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(gt); + i915_request_put(rq); + err = -ETIME; + goto err_ce; + } + + /* Fill the ring, until we will cause a wrap */ + n = 0; + while (intel_ring_direction(ce[0]->ring, + rq->wa_tail, + ce[0]->ring->tail) <= 0) { + struct i915_request *tmp; + + tmp = intel_context_create_request(ce[0]); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + i915_request_put(rq); + goto err_ce; + } + + i915_request_add(tmp); + intel_engine_flush_submission(engine); + n++; + } + intel_engine_flush_submission(engine); + pr_debug("%s: Filled ring with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", + engine->name, n, + ce[0]->ring->size, + ce[0]->ring->tail, + ce[0]->ring->emit, + rq->tail); + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, + rq->tail, + ce[0]->ring->tail) <= 0); + i915_request_put(rq); + + /* Create a second request to preempt the first ring */ + rq = intel_context_create_request(ce[1]); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_get(rq); + i915_request_add(rq); + + err = wait_for_submit(engine, rq, HZ / 2); + i915_request_put(rq); + if (err) { + pr_err("%s: preemption request was not submited\n", + engine->name); + err = -ETIME; + } + + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", + engine->name, + ce[0]->ring->tail, ce[0]->ring->emit, + ce[1]->ring->tail, ce[1]->ring->emit); + +err_ce: + intel_engine_flush_submission(engine); + igt_spinner_end(&spin); + for (n = 0; n < ARRAY_SIZE(ce); n++) { + if (IS_ERR_OR_NULL(ce[n])) + break; + + intel_context_unpin(ce[n]); + intel_context_put(ce[n]); + } + engine_heartbeat_enable(engine); + if (igt_live_test_end(&t)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + return err; +} + static int live_pin_rewind(void *arg) { struct intel_gt *gt = arg; @@ -4374,6 +4523,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_sanitycheck), SUBTEST(live_unlite_switch), SUBTEST(live_unlite_preempt), + SUBTEST(live_unlite_ring), SUBTEST(live_pin_rewind), SUBTEST(live_hold_reset), SUBTEST(live_error_interrupt), -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 15 20:16:34 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 20:16:34 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/selftests=3A_Exercise_far_preemption_rollbacks?= In-Reply-To: <20200615200603.18827-1-chris@chris-wilson.co.uk> References: <20200615200603.18827-1-chris@chris-wilson.co.uk> Message-ID: <159225219415.16141.13781389468485471563@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise far preemption rollbacks URL : https://patchwork.freedesktop.org/series/78384/ State : warning == Summary == $ dim checkpatch origin/drm-tip 268ee667bc05 drm/i915/selftests: Exercise far preemption rollbacks -:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding")' #19: References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") total: 1 errors, 0 warnings, 0 checks, 162 lines checked From patchwork at emeril.freedesktop.org Mon Jun 15 20:38:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 20:38:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Exercise_far_preemption_rollbacks?= In-Reply-To: <20200615200603.18827-1-chris@chris-wilson.co.uk> References: <20200615200603.18827-1-chris@chris-wilson.co.uk> Message-ID: <159225352059.16138.10696849526252346774@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise far preemption rollbacks URL : https://patchwork.freedesktop.org/series/78384/ State : success == Summary == CI Bug Log - changes from CI_DRM_8629 -> Patchwork_17956 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/index.html Known issues ------------ Here are the changes found in Patchwork_17956 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_flink_basic@bad-flink: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-tgl-y/igt at gem_flink_basic@bad-flink.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-tgl-y/igt at gem_flink_basic@bad-flink.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][5] -> [FAIL][6] ([i915#138]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at gem_ctx_exec@basic: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-tgl-y/igt at gem_ctx_exec@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-tgl-y/igt at gem_ctx_exec@basic.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-c: - fi-tgl-y: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-tgl-y/igt at kms_pipe_crc_basic@read-crc-pipe-c.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92]) -> [DMESG-WARN][26] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][28] ([i915#62] / [i915#92]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [i915#138]: https://gitlab.freedesktop.org/drm/intel/issues/138 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (34 -> 32) ------------------------------ Missing (2): fi-bsw-cyan fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8629 -> Patchwork_17956 CI-20190529: 20190529 CI_DRM_8629: d5f177af226836ef59edf6dfaa7297c5a75fa089 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17956: 268ee667bc054982faaaf8eca48c5a0c12ea8c72 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 268ee667bc05 drm/i915/selftests: Exercise far preemption rollbacks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17956/index.html From uma.shankar at intel.com Mon Jun 15 20:39:55 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 15 Jun 2020 20:39:55 +0000 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200611160112.GC6112@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> > -----Original Message----- > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Sent: Thursday, June 11, 2020 9:31 PM > To: Shankar, Uma <uma.shankar at intel.com> > Cc: intel-gfx at lists.freedesktop.org; jani.nikula at linux.intel.com; Mun, Gwan- > gyeong <gwan-gyeong.mun at intel.com> > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes readback for > LSPCON > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > Implemented Infoframes enabled readback for LSPCON devices. > > > This will help align the implementation with state readback > > > infrastructure. > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > ++++++++++++++++++++- > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct intel_encoder > *encoder, > > > buf, ret); > > > } > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct > > > +drm_dp_aux *aux) { > > > + int ret; > > > + u32 val = 0; > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > + > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > + if (ret < 0) { > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > + return false; > > > + } > > > + > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > + return true; > > > + > > > + return false; > > > > return val & ...; > > > > > +} > > > + > > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct > > > +drm_dp_aux *aux) { > > > + int ret; > > > + u32 val = 0; > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > + > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > + if (ret < 0) { > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > + return false; > > > + } > > > + > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > + return true; > > > + > > > + return false; > > > +} > > > + > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > const struct intel_crtc_state *pipe_config) { > > > - /* FIXME actually read this from the hw */ > > > - return 0; > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > + bool infoframes_enabled; > > > + u32 mask = 0; > > > + u32 val; > > > + > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > + infoframes_enabled = > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > + else > > > + infoframes_enabled = > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); > > > + > > > + if (infoframes_enabled) > > > + return true; > > > > This is supposed to return a bitmask of all enabled infoframes. > Actually since we're dealing with both the LSPCON specific stuff and DIP stuff for > the DRM infoframe I think we should stop using using > intel_hdmi_infoframes_enabled(), and instead provide a LSPCON specific > replacement for it. That way we can directly return the abstract bitmask instead > of pretending to return a bitmask of the DIP bits. Sure, will fix this and resend the next version. > > > > Also my question "how do we turn off infoframes once enabled?" > > from > > https://patchwork.freedesktop.org/patch/351719/?series=72928&rev=1 > > still remains unanswered... For the AVI infoframe we generally compute and change the respective values. If no change is requested and computed we can let the existing infoframes be transmitted. AFAIK there is no mechanism called out, to explicitly disable this on Lspcon. Have not seen any issues due to this, so hoping that it may be safe even if they are enabled. I am planning to take your patch from the series and float along with this series, adding check for DRM Infoframes also. Hope that is ok ? Thanks Ville for your feedback. Regards, Uma Shankar > > > + > > > + if (lspcon->hdr_supported) { > > > + val = intel_de_read(dev_priv, > > > + HSW_TVIDEO_DIP_CTL(pipe_config- > >cpu_transcoder)); > > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > > + > > > + if (val & mask) > > > + return val & mask; > > > + } > > > + > > > + return false; > > > } > > > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > > -- > > > 2.22.0 > > > > -- > > Ville Syrj?l? > > Intel > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Mon Jun 15 20:52:33 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 15 Jun 2020 23:52:33 +0300 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> Message-ID: <20200615205233.GS6112@intel.com> On Mon, Jun 15, 2020 at 08:39:55PM +0000, Shankar, Uma wrote: > > > > -----Original Message----- > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Sent: Thursday, June 11, 2020 9:31 PM > > To: Shankar, Uma <uma.shankar at intel.com> > > Cc: intel-gfx at lists.freedesktop.org; jani.nikula at linux.intel.com; Mun, Gwan- > > gyeong <gwan-gyeong.mun at intel.com> > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes readback for > > LSPCON > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > This will help align the implementation with state readback > > > > infrastructure. > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > ++++++++++++++++++++- > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct intel_encoder > > *encoder, > > > > buf, ret); > > > > } > > > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct > > > > +drm_dp_aux *aux) { > > > > + int ret; > > > > + u32 val = 0; > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > + > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > + if (ret < 0) { > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > + return false; > > > > + } > > > > + > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > + return true; > > > > + > > > > + return false; > > > > > > return val & ...; > > > > > > > +} > > > > + > > > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct > > > > +drm_dp_aux *aux) { > > > > + int ret; > > > > + u32 val = 0; > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > + > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > + if (ret < 0) { > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > + return false; > > > > + } > > > > + > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > + return true; > > > > + > > > > + return false; > > > > +} > > > > + > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > const struct intel_crtc_state *pipe_config) { > > > > - /* FIXME actually read this from the hw */ > > > > - return 0; > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > + bool infoframes_enabled; > > > > + u32 mask = 0; > > > > + u32 val; > > > > + > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > + infoframes_enabled = > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > + else > > > > + infoframes_enabled = > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); > > > > + > > > > + if (infoframes_enabled) > > > > + return true; > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > Actually since we're dealing with both the LSPCON specific stuff and DIP stuff for > > the DRM infoframe I think we should stop using using > > intel_hdmi_infoframes_enabled(), and instead provide a LSPCON specific > > replacement for it. That way we can directly return the abstract bitmask instead > > of pretending to return a bitmask of the DIP bits. > > Sure, will fix this and resend the next version. > > > > > > > Also my question "how do we turn off infoframes once enabled?" > > > from > > > https://patchwork.freedesktop.org/patch/351719/?series=72928&rev=1 > > > still remains unanswered... > > For the AVI infoframe we generally compute and change the respective values. If no change is > requested and computed we can let the existing infoframes be transmitted. AFAIK there is no > mechanism called out, to explicitly disable this on Lspcon. Have not seen any issues due to this, > so hoping that it may be safe even if they are enabled. It's not valid to transmit infoframes to DVI sinks. > > I am planning to take your patch from the series and float along with this series, adding check for DRM > Infoframes also. Hope that is ok ? > > Thanks Ville for your feedback. > > Regards, > Uma Shankar > > > > > + > > > > + if (lspcon->hdr_supported) { > > > > + val = intel_de_read(dev_priv, > > > > + HSW_TVIDEO_DIP_CTL(pipe_config- > > >cpu_transcoder)); > > > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > > > + > > > > + if (val & mask) > > > > + return val & mask; > > > > + } > > > > + > > > > + return false; > > > > } > > > > > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > > > -- > > > > 2.22.0 > > > > > > -- > > > Ville Syrj?l? > > > Intel > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From uma.shankar at intel.com Mon Jun 15 21:03:23 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 15 Jun 2020 21:03:23 +0000 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200615205233.GS6112@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> > > > -----Original Message----- > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Sent: Thursday, June 11, 2020 9:31 PM > > > To: Shankar, Uma <uma.shankar at intel.com> > > > Cc: intel-gfx at lists.freedesktop.org; jani.nikula at linux.intel.com; > > > Mun, Gwan- gyeong <gwan-gyeong.mun at intel.com> > > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes > > > readback for LSPCON > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > This will help align the implementation with state readback > > > > > infrastructure. > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > ++++++++++++++++++++- > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct > > > > > intel_encoder > > > *encoder, > > > > > buf, ret); > > > > > } > > > > > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct > > > > > +drm_dp_aux *aux) { > > > > > + int ret; > > > > > + u32 val = 0; > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > + > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > + if (ret < 0) { > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > + return false; > > > > > + } > > > > > + > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > + return true; > > > > > + > > > > > + return false; > > > > > > > > return val & ...; > > > > > > > > > +} > > > > > + > > > > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct > > > > > +drm_dp_aux *aux) { > > > > > + int ret; > > > > > + u32 val = 0; > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > + > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > + if (ret < 0) { > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > + return false; > > > > > + } > > > > > + > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > + return true; > > > > > + > > > > > + return false; > > > > > +} > > > > > + > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > const struct intel_crtc_state *pipe_config) { > > > > > - /* FIXME actually read this from the hw */ > > > > > - return 0; > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > + bool infoframes_enabled; > > > > > + u32 mask = 0; > > > > > + u32 val; > > > > > + > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > + infoframes_enabled = > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > + else > > > > > + infoframes_enabled = > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); > > > > > + > > > > > + if (infoframes_enabled) > > > > > + return true; > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > Actually since we're dealing with both the LSPCON specific stuff and > > > DIP stuff for the DRM infoframe I think we should stop using using > > > intel_hdmi_infoframes_enabled(), and instead provide a LSPCON > > > specific replacement for it. That way we can directly return the > > > abstract bitmask instead of pretending to return a bitmask of the DIP bits. > > > > Sure, will fix this and resend the next version. > > > > > > > > > > Also my question "how do we turn off infoframes once enabled?" > > > > from > > > > https://patchwork.freedesktop.org/patch/351719/?series=72928&rev=1 > > > > still remains unanswered... > > > > For the AVI infoframe we generally compute and change the respective > > values. If no change is requested and computed we can let the existing > > infoframes be transmitted. AFAIK there is no mechanism called out, to > > explicitly disable this on Lspcon. Have not seen any issues due to this, so > hoping that it may be safe even if they are enabled. > > It's not valid to transmit infoframes to DVI sinks. With your fix, we won't be enabling or setting the infoframe on DVI sinks. If I understand correctly, we may have issue if we connect HDMI (where we would have sent the infoframe) and later unplug and plug a DVI sink. With unplug if Lspcon is not resetting this internally then this will be a problem. I will try to get this information on Lspcon behavior. > > > > I am planning to take your patch from the series and float along with > > this series, adding check for DRM Infoframes also. Hope that is ok ? > > > > Thanks Ville for your feedback. > > > > Regards, > > Uma Shankar > > > > > > > + > > > > > + if (lspcon->hdr_supported) { > > > > > + val = intel_de_read(dev_priv, > > > > > + HSW_TVIDEO_DIP_CTL(pipe_config- > > > >cpu_transcoder)); > > > > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > > > > + > > > > > + if (val & mask) > > > > > + return val & mask; > > > > > + } > > > > > + > > > > > + return false; > > > > > } > > > > > > > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > > > > -- > > > > > 2.22.0 > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Mon Jun 15 21:30:07 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 21:30:07 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/selftests=3A_Exercise_far_preemption_rollbacks_=28?= =?utf-8?q?rev2=29?= In-Reply-To: <20200615200603.18827-1-chris@chris-wilson.co.uk> References: <20200615200603.18827-1-chris@chris-wilson.co.uk> Message-ID: <159225660709.16139.12618997987343984501@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise far preemption rollbacks (rev2) URL : https://patchwork.freedesktop.org/series/78384/ State : warning == Summary == $ dim checkpatch origin/drm-tip 39ae8f5dde72 drm/i915/selftests: Exercise far preemption rollbacks -:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding")' #19: References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") total: 1 errors, 0 warnings, 0 checks, 162 lines checked From emil.l.velikov at gmail.com Mon Jun 15 21:31:50 2020 From: emil.l.velikov at gmail.com (Emil Velikov) Date: Mon, 15 Jun 2020 22:31:50 +0100 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <20200612160056.2082681-7-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-7-daniel.vetter@ffwll.ch> Message-ID: <CACvgo51AVVOxhGK2Uin=ZLgPpihJiEsnc6pvAyKqFKPvLdOzLA@mail.gmail.com> Hi Daniel, On Fri, 12 Jun 2020 at 17:01, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > The atomic helpers try really hard to not lose track of things, > duplicating enabled tracking in the driver is at best confusing. > Double-enabling or disabling is a bug in atomic helpers. > > In the fb_dirty function we can just assume that the fb always exists, > simple display pipe helpers guarantee that the crtc is only enabled > together with the output, so we always have a primary plane around. > > Now in the update function we need to be a notch more careful, since > that can also get called when the crtc is off. And we don't want to > upload frames when that's the case, so filter that out too. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Maxime Ripard <mripard at kernel.org> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: David Airlie <airlied at linux.ie> > Cc: Daniel Vetter <daniel at ffwll.ch> > Cc: David Lechner <david at lechnology.com> > --- > drivers/gpu/drm/drm_mipi_dbi.c | 16 ++++++---------- > drivers/gpu/drm/tiny/ili9225.c | 12 +++--------- > drivers/gpu/drm/tiny/st7586.c | 11 +++-------- > include/drm/drm_mipi_dbi.h | 5 ----- > 4 files changed, 12 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c > index fd8d672972a9..79532b9a324a 100644 > --- a/drivers/gpu/drm/drm_mipi_dbi.c > +++ b/drivers/gpu/drm/drm_mipi_dbi.c > @@ -268,7 +268,7 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) > bool full; > void *tr; > > - if (!dbidev->enabled) > + if (WARN_ON(!fb)) > return; > AFAICT no other driver has such WARN_ON. Let's drop that - it is pretty confusing and misleading as-is. With that, patches 7/8 and 8/8 are: Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com> -Emil From emil.l.velikov at gmail.com Mon Jun 15 21:36:28 2020 From: emil.l.velikov at gmail.com (Emil Velikov) Date: Mon, 15 Jun 2020 22:36:28 +0100 Subject: [Intel-gfx] [PATCH v7 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <20200612235606.25120-1-manasi.d.navare@intel.com> References: <20200612230444.10121-4-manasi.d.navare@intel.com> <20200612235606.25120-1-manasi.d.navare@intel.com> Message-ID: <CACvgo522mYhCRkNXuwJDCt2fh4-Piq9ZOH9rNbO+HrcbrytJgQ@mail.gmail.com> Hi Manasi, On Sat, 13 Jun 2020 at 00:55, Manasi Navare <manasi.d.navare at intel.com> wrote: > > From: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > [Why] > It's useful to know the min and max vrr range for IGT testing. > > [How] > Expose the min and max vfreq for the connector via a debugfs file > on the connector, "vrr_range". > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > v7: > * Fix cmpilation due to rebase > v6: > * Rebase (manasi) > v5: > * Rename to vrr_range to match AMD debugfs > v4: > * Rebase > v3: > * Remove the unnecessary debug print (Manasi) > v2: > * Fix the typo in max_vfreq (Manasi) > * Change the name of node to i915_vrr_info so we can add > other vrr info for more debug info (Manasi) > * Change the VRR capable to display Yes or No (Manasi) > * Fix indentation checkpatch errors (Manasi) > Nit: generally revision log is listed in v2 -> v6 order. > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > Cc: Jani Nikula <jani.nikula at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Tested-by: Manasi Navare <manasi.d.navare at intel.com> > --- > .../drm/i915/display/intel_display_debugfs.c | 22 ++++++++++++++++++- > 1 file changed, 21 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 28dd717e943a..2921f7d2a26e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -2185,6 +2185,21 @@ static const struct file_operations i915_dsc_fec_support_fops = { > .write = i915_dsc_fec_support_write > }; > > +static int vrr_range_show(struct seq_file *m, void *data) > +{ > + struct drm_connector *connector = m->private; > + > + if (connector->status != connector_status_connected) > + return -ENODEV; > + > + seq_printf(m, "Vrr_capable: %s\n", yesno(intel_dp_is_vrr_capable(connector))); > + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); > + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); > + > + return 0; > +} > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > + > /** > * intel_connector_debugfs_add - add i915 specific connector debugfs files > * @connector: pointer to a registered drm_connector > @@ -2220,10 +2235,15 @@ int intel_connector_debugfs_add(struct drm_connector *connector) > if (INTEL_GEN(dev_priv) >= 10 && > ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && > !to_intel_connector(connector)->mst_port) || > - connector->connector_type == DRM_MODE_CONNECTOR_eDP)) > + connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { > debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, > connector, &i915_dsc_fec_support_fops); > > + if (INTEL_GEN(dev_priv) >= 12) > + debugfs_create_file("vrr_range", S_IRUGO, > + root, connector, &vrr_range_fops); > + } > + I think this should be added by core drm. Ideally drm will add it automatically for each connector that the driver has called drm_connector_attach_vrr_capable_property() upon. -Emil From manasi.d.navare at intel.com Mon Jun 15 21:48:09 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Mon, 15 Jun 2020 14:48:09 -0700 Subject: [Intel-gfx] [PATCH v7 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <CACvgo522mYhCRkNXuwJDCt2fh4-Piq9ZOH9rNbO+HrcbrytJgQ@mail.gmail.com> References: <20200612230444.10121-4-manasi.d.navare@intel.com> <20200612235606.25120-1-manasi.d.navare@intel.com> <CACvgo522mYhCRkNXuwJDCt2fh4-Piq9ZOH9rNbO+HrcbrytJgQ@mail.gmail.com> Message-ID: <20200615214809.GA4334@intel.com> On Mon, Jun 15, 2020 at 10:36:28PM +0100, Emil Velikov wrote: > Hi Manasi, > > On Sat, 13 Jun 2020 at 00:55, Manasi Navare <manasi.d.navare at intel.com> wrote: > > > > From: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > > > [Why] > > It's useful to know the min and max vrr range for IGT testing. > > > > [How] > > Expose the min and max vfreq for the connector via a debugfs file > > on the connector, "vrr_range". > > > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > > > v7: > > * Fix cmpilation due to rebase > > v6: > > * Rebase (manasi) > > v5: > > * Rename to vrr_range to match AMD debugfs > > v4: > > * Rebase > > v3: > > * Remove the unnecessary debug print (Manasi) > > v2: > > * Fix the typo in max_vfreq (Manasi) > > * Change the name of node to i915_vrr_info so we can add > > other vrr info for more debug info (Manasi) > > * Change the VRR capable to display Yes or No (Manasi) > > * Fix indentation checkpatch errors (Manasi) > > > Nit: generally revision log is listed in v2 -> v6 order. Okay point noted. Will update this in the next rev > > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Tested-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > .../drm/i915/display/intel_display_debugfs.c | 22 ++++++++++++++++++- > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > index 28dd717e943a..2921f7d2a26e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > @@ -2185,6 +2185,21 @@ static const struct file_operations i915_dsc_fec_support_fops = { > > .write = i915_dsc_fec_support_write > > }; > > > > +static int vrr_range_show(struct seq_file *m, void *data) > > +{ > > + struct drm_connector *connector = m->private; > > + > > + if (connector->status != connector_status_connected) > > + return -ENODEV; > > + > > + seq_printf(m, "Vrr_capable: %s\n", yesno(intel_dp_is_vrr_capable(connector))); > > + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); > > + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); > > + > > + return 0; > > +} > > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > > + > > /** > > * intel_connector_debugfs_add - add i915 specific connector debugfs files > > * @connector: pointer to a registered drm_connector > > @@ -2220,10 +2235,15 @@ int intel_connector_debugfs_add(struct drm_connector *connector) > > if (INTEL_GEN(dev_priv) >= 10 && > > ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && > > !to_intel_connector(connector)->mst_port) || > > - connector->connector_type == DRM_MODE_CONNECTOR_eDP)) > > + connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { > > debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, > > connector, &i915_dsc_fec_support_fops); > > > > + if (INTEL_GEN(dev_priv) >= 12) > > + debugfs_create_file("vrr_range", S_IRUGO, > > + root, connector, &vrr_range_fops); > > + } > > + > > I think this should be added by core drm. Ideally drm will add it > automatically for each connector that the driver has called > drm_connector_attach_vrr_capable_property() upon. > But in this case drm_connector_attach_vrr_capable_property() is called by individual driver since its an optional connector property. So we call this inside i915. Also currently AMD sets this debugfs inside AMD IMO, so setting this here for now. But I agree that can be moved to drm core may be when drm_display_info gets populated with min and max, thats where drm can add this? Manasi > -Emil From patchwork at emeril.freedesktop.org Mon Jun 15 21:51:15 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 21:51:15 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Exercise_far_preemption_rollbacks_=28rev2=29?= In-Reply-To: <20200615200603.18827-1-chris@chris-wilson.co.uk> References: <20200615200603.18827-1-chris@chris-wilson.co.uk> Message-ID: <159225787538.16141.10156491870662714384@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise far preemption rollbacks (rev2) URL : https://patchwork.freedesktop.org/series/78384/ State : success == Summary == CI Bug Log - changes from CI_DRM_8630 -> Patchwork_17957 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/index.html Known issues ------------ Here are the changes found in Patchwork_17957 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-tgl-u2/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-tgl-y/igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-tgl-y/igt at kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at gem_render_linear_blits@basic: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-tgl-y/igt at gem_render_linear_blits@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-tgl-y/igt at gem_render_linear_blits@basic.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-kbl-x1275/igt at kms_busy@basic at flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html * igt at kms_psr@cursor_plane_move: - fi-tgl-y: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-tgl-y/igt at kms_psr@cursor_plane_move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-tgl-y/igt at kms_psr@cursor_plane_move.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#1982] / [i915#62] / [i915#92]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 43) ------------------------------ Additional (1): fi-byt-n2820 Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8630 -> Patchwork_17957 CI-20190529: 20190529 CI_DRM_8630: bd2e730744f57bd02dba9c9b0ef64b3b1b8850e4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17957: 39ae8f5dde72d43e63c5de8d838c9b363b6741f6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 39ae8f5dde72 drm/i915/selftests: Exercise far preemption rollbacks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/index.html From lkp at intel.com Mon Jun 15 22:27:20 2020 From: lkp at intel.com (kernel test robot) Date: Tue, 16 Jun 2020 06:27:20 +0800 Subject: [Intel-gfx] [drm-intel:for-linux-next-fixes 4/16] drivers/gpu/drm/i915/gt/selftest_lrc.c:1333:34: error: too few arguments to function call, expected 2, have 1 Message-ID: <202006160616.CeXj3XPH%lkp@intel.com> tree: git://anongit.freedesktop.org/drm-intel for-linux-next-fixes head: add78d27d388520cbed6a7bf01d1e0afa183314d commit: 04dc41776145f539ab6da442cb633e45539bed9a [4/16] drm/i915/gt: Prevent timeslicing into unpreemptable requests config: x86_64-allyesconfig (attached as .config) compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 3d8149c2a1228609fd7d7c91a04681304a2f0ca9) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install x86_64 cross compiling tool for clang build # apt-get install binutils-x86-64-linux-gnu git checkout 04dc41776145f539ab6da442cb633e45539bed9a # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5953: >> drivers/gpu/drm/i915/gt/selftest_lrc.c:1333:34: error: too few arguments to function call, expected 2, have 1 engine_heartbeat_disable(engine); ~~~~~~~~~~~~~~~~~~~~~~~~ ^ drivers/gpu/drm/i915/gt/selftest_lrc.c:54:13: note: 'engine_heartbeat_disable' declared here static void engine_heartbeat_disable(struct intel_engine_cs *engine, ^ drivers/gpu/drm/i915/gt/selftest_lrc.c:1402:33: error: too few arguments to function call, expected 2, have 1 engine_heartbeat_enable(engine); ~~~~~~~~~~~~~~~~~~~~~~~ ^ drivers/gpu/drm/i915/gt/selftest_lrc.c:64:13: note: 'engine_heartbeat_enable' declared here static void engine_heartbeat_enable(struct intel_engine_cs *engine, ^ 2 errors generated. vim +1333 drivers/gpu/drm/i915/gt/selftest_lrc.c 1300 1301 static int live_timeslice_nopreempt(void *arg) 1302 { 1303 struct intel_gt *gt = arg; 1304 struct intel_engine_cs *engine; 1305 enum intel_engine_id id; 1306 struct igt_spinner spin; 1307 int err = 0; 1308 1309 /* 1310 * We should not timeslice into a request that is marked with 1311 * I915_REQUEST_NOPREEMPT. 1312 */ 1313 if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) 1314 return 0; 1315 1316 if (igt_spinner_init(&spin, gt)) 1317 return -ENOMEM; 1318 1319 for_each_engine(engine, gt, id) { 1320 struct intel_context *ce; 1321 struct i915_request *rq; 1322 unsigned long timeslice; 1323 1324 if (!intel_engine_has_preemption(engine)) 1325 continue; 1326 1327 ce = intel_context_create(engine); 1328 if (IS_ERR(ce)) { 1329 err = PTR_ERR(ce); 1330 break; 1331 } 1332 > 1333 engine_heartbeat_disable(engine); 1334 timeslice = xchg(&engine->props.timeslice_duration_ms, 1); 1335 1336 /* Create an unpreemptible spinner */ 1337 1338 rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK); 1339 intel_context_put(ce); 1340 if (IS_ERR(rq)) { 1341 err = PTR_ERR(rq); 1342 goto out_heartbeat; 1343 } 1344 1345 i915_request_get(rq); 1346 i915_request_add(rq); 1347 1348 if (!igt_wait_for_spinner(&spin, rq)) { 1349 i915_request_put(rq); 1350 err = -ETIME; 1351 goto out_spin; 1352 } 1353 1354 set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags); 1355 i915_request_put(rq); 1356 1357 /* Followed by a maximum priority barrier (heartbeat) */ 1358 1359 ce = intel_context_create(engine); 1360 if (IS_ERR(ce)) { 1361 err = PTR_ERR(rq); 1362 goto out_spin; 1363 } 1364 1365 rq = intel_context_create_request(ce); 1366 intel_context_put(ce); 1367 if (IS_ERR(rq)) { 1368 err = PTR_ERR(rq); 1369 goto out_spin; 1370 } 1371 1372 rq->sched.attr.priority = I915_PRIORITY_BARRIER; 1373 i915_request_get(rq); 1374 i915_request_add(rq); 1375 1376 /* 1377 * Wait until the barrier is in ELSP, and we know timeslicing 1378 * will have been activated. 1379 */ 1380 if (wait_for_submit(engine, rq, HZ / 2)) { 1381 i915_request_put(rq); 1382 err = -ETIME; 1383 goto out_spin; 1384 } 1385 1386 /* 1387 * Since the ELSP[0] request is unpreemptible, it should not 1388 * allow the maximum priority barrier through. Wait long 1389 * enough to see if it is timesliced in by mistake. 1390 */ 1391 if (i915_request_wait(rq, 0, timeslice_threshold(engine)) >= 0) { 1392 pr_err("%s: I915_PRIORITY_BARRIER request completed, bypassing no-preempt request\n", 1393 engine->name); 1394 err = -EINVAL; 1395 } 1396 i915_request_put(rq); 1397 1398 out_spin: 1399 igt_spinner_end(&spin); 1400 out_heartbeat: 1401 xchg(&engine->props.timeslice_duration_ms, timeslice); 1402 engine_heartbeat_enable(engine); 1403 if (err) 1404 break; 1405 1406 if (igt_flush_test(gt->i915)) { 1407 err = -EIO; 1408 break; 1409 } 1410 } 1411 1412 igt_spinner_fini(&spin); 1413 return err; 1414 } 1415 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 74750 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200616/484e32e9/attachment-0001.gz> From patchwork at emeril.freedesktop.org Mon Jun 15 22:56:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 15 Jun 2020 22:56:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Don=27t_flush_the_tasklet_if_not_setup?= In-Reply-To: <20200615183935.17389-1-chris@chris-wilson.co.uk> References: <20200615183935.17389-1-chris@chris-wilson.co.uk> Message-ID: <159226180155.16138.4520857142649656148@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Don't flush the tasklet if not setup URL : https://patchwork.freedesktop.org/series/78382/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8629_full -> Patchwork_17955_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17955_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17955_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17955_full: ### IGT changes ### #### Possible regressions #### * igt at gem_ctx_isolation@preservation-s3 at bcs0: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-iclb2/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-iclb3/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * igt at gem_exec_balancer@bonded-early: - shard-tglb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-tglb7/igt at gem_exec_balancer@bonded-early.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-tglb5/igt at gem_exec_balancer@bonded-early.html ### Piglit changes ### #### Possible regressions #### * spec at glsl-4.00@execution at built-in-functions@fs-op-mult-dmat2x4-dmat4x2 (NEW): - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][5] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/pig-icl-1065g7/spec at glsl-4.00@execution at built-in-functions@fs-op-mult-dmat2x4-dmat4x2.html * spec at glsl-4.00@execution at built-in-functions@gs-op-div-double-dmat3x4 (NEW): - {pig-icl-1065g7}: NOTRUN -> [CRASH][6] +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/pig-icl-1065g7/spec at glsl-4.00@execution at built-in-functions@gs-op-div-double-dmat3x4.html New tests --------- New tests have been introduced between CI_DRM_8629_full and Patchwork_17955_full: ### New Piglit tests (6) ### * spec at glsl-4.00@execution at built-in-functions@fs-op-mult-dmat2x4-dmat4x2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at glsl-4.00@execution at built-in-functions@fs-op-mult-dmat3x4-dmat3: - Statuses : 1 crash(s) - Exec time: [93.95] s * spec at glsl-4.00@execution at built-in-functions@fs-op-mult-dmat4-dmat3x4: - Statuses : 1 crash(s) - Exec time: [159.53] s * spec at glsl-4.00@execution at built-in-functions@fs-op-sub-dmat4-double: - Statuses : 1 crash(s) - Exec time: [28.11] s * spec at glsl-4.00@execution at built-in-functions@gs-op-div-double-dmat3x4: - Statuses : 1 crash(s) - Exec time: [20.37] s * spec at glsl-4.00@execution at built-in-functions@vs-op-div-dvec3-dvec3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in Patchwork_17955_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vcs0: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#198]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl1/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl8/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#1930]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-glk1/igt at gem_exec_reloc@basic-concurrent0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_mmap_offset@ptrace at gtt: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-kbl6/igt at gem_mmap_offset@ptrace at gtt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-kbl1/igt at gem_mmap_offset@ptrace at gtt.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +26 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-apl3/igt at gem_mmap_wc@write-cpu-read-wc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-apl1/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][15] -> [DMESG-FAIL][16] ([i915#118] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#54]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl7/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-256x85-sliding.html * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-apl7/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-apl6/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html * igt at kms_flip@busy-flip at c-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#275]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl3/igt at kms_flip@busy-flip at c-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl2/igt at kms_flip@busy-flip at c-edp1.html * igt at kms_flip@flip-vs-expired-vblank at a-dp1: - shard-apl: [PASS][23] -> [FAIL][24] ([i915#79]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-apl8/igt at kms_flip@flip-vs-expired-vblank at a-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-apl4/igt at kms_flip@flip-vs-expired-vblank at a-dp1.html * igt at kms_flip@flip-vs-suspend at b-dp1: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-kbl1/igt at kms_flip@flip-vs-suspend at b-dp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-kbl3/igt at kms_flip@flip-vs-suspend at b-dp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][27] -> [DMESG-FAIL][28] ([i915#95]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-apl4/igt at kms_flip_tiling@flip-changes-tiling-y.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-tglb: [PASS][29] -> [INCOMPLETE][30] ([i915#456]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-tglb3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-tglb7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-iclb4/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_psr@suspend: - shard-skl: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) +13 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl9/igt at kms_psr@suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl3/igt at kms_psr@suspend.html * igt at kms_vblank@pipe-c-wait-forked-busy: - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-tglb8/igt at kms_vblank@pipe-c-wait-forked-busy.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-tglb7/igt at kms_vblank@pipe-c-wait-forked-busy.html #### Possible fixes #### * igt at gem_exec_whisper@basic-normal-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-glk6/igt at gem_exec_whisper@basic-normal-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-glk7/igt at gem_exec_whisper@basic-normal-all.html * igt at i915_selftest@mock at requests: - shard-kbl: [INCOMPLETE][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-kbl4/igt at i915_selftest@mock at requests.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-kbl4/igt at i915_selftest@mock at requests.html - shard-tglb: [INCOMPLETE][43] -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-tglb6/igt at i915_selftest@mock at requests.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-tglb1/igt at i915_selftest@mock at requests.html - shard-apl: [INCOMPLETE][45] -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-apl4/igt at i915_selftest@mock at requests.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-apl3/igt at i915_selftest@mock at requests.html - shard-glk: [INCOMPLETE][47] ([i915#58] / [k.org#198133]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-glk4/igt at i915_selftest@mock at requests.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-glk1/igt at i915_selftest@mock at requests.html - shard-skl: [INCOMPLETE][49] ([i915#198]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl10/igt at i915_selftest@mock at requests.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl5/igt at i915_selftest@mock at requests.html - shard-iclb: [INCOMPLETE][51] -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-iclb1/igt at i915_selftest@mock at requests.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-iclb1/igt at i915_selftest@mock at requests.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][53] ([i915#118] / [i915#95]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-glk7/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +28 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-position-covered-pipe-b-planes: - shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +7 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl10/igt at kms_plane@plane-position-covered-pipe-b-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl6/igt at kms_plane@plane-position-covered-pipe-b-planes.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-iclb4/igt at kms_psr@psr2_sprite_mmap_gtt.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at perf_pmu@module-unload: - shard-tglb: [DMESG-WARN][65] ([i915#402]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-tglb1/igt at perf_pmu@module-unload.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-tglb3/igt at perf_pmu@module-unload.html #### Warnings #### * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][67] ([i915#1319] / [i915#1958]) -> [TIMEOUT][68] ([i915#1319]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-kbl4/igt at kms_content_protection@lic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-kbl3/igt at kms_content_protection@lic.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding: - shard-kbl: [DMESG-WARN][69] ([i915#93] / [i915#95]) -> [DMESG-FAIL][70] ([i915#54] / [i915#95]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][71] ([i915#1525]) -> [DMESG-FAIL][72] ([i915#95]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-apl8/igt at kms_fbcon_fbt@fbc-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-apl4/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][73] ([i915#93] / [i915#95]) -> [DMESG-WARN][74] ([i915#180] / [i915#93] / [i915#95]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][75] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][76] ([fdo#108145] / [i915#1982]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8629/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#275]: https://gitlab.freedesktop.org/drm/intel/issues/275 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8629 -> Patchwork_17955 CI-20190529: 20190529 CI_DRM_8629: d5f177af226836ef59edf6dfaa7297c5a75fa089 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17955: 3a591b832d873af97d2401e09c5d1d8005ccbeb3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17955/index.html From sfr at canb.auug.org.au Mon Jun 15 23:39:12 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Tue, 16 Jun 2020 09:39:12 +1000 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-intel-fixes tree Message-ID: <20200616093912.4dffcc71@canb.auug.org.au> Hi all, After merging the drm-intel-fixes tree, today's linux-next build (x86_64 allmodconfig) failed like this: In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5972: drivers/gpu/drm/i915/gt/selftest_lrc.c: In function 'live_timeslice_nopreempt': drivers/gpu/drm/i915/gt/selftest_lrc.c:1333:3: error: too few arguments to function 'engine_heartbeat_disable' 1333 | engine_heartbeat_disable(engine); | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/selftest_lrc.c:54:13: note: declared here 54 | static void engine_heartbeat_disable(struct intel_engine_cs *engine, | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/selftest_lrc.c:1402:3: error: too few arguments to function 'engine_heartbeat_enable' 1402 | engine_heartbeat_enable(engine); | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/selftest_lrc.c:64:13: note: declared here 64 | static void engine_heartbeat_enable(struct intel_engine_cs *engine, | ^~~~~~~~~~~~~~~~~~~~~~~ Caused by commit 04dc41776145 ("drm/i915/gt: Prevent timeslicing into unpreemptable requests") I have reverted that commit for today. -- Cheers, Stephen Rothwell -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 484 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200616/30841e51/attachment.sig> From patchwork at emeril.freedesktop.org Tue Jun 16 00:30:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 00:30:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Exercise_far_preemption_rollbacks_=28rev2=29?= In-Reply-To: <20200615200603.18827-1-chris@chris-wilson.co.uk> References: <20200615200603.18827-1-chris@chris-wilson.co.uk> Message-ID: <159226740256.4598.5110550722047468477@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Exercise far preemption rollbacks (rev2) URL : https://patchwork.freedesktop.org/series/78384/ State : success == Summary == CI Bug Log - changes from CI_DRM_8630_full -> Patchwork_17957_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17957_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at blt: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-apl8/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-apl1/igt at gem_ctx_persistence@legacy-engines-mixed-process at blt.html * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#1528]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl6/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl4/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html * igt at gem_ctx_persistence@process: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl7/igt at gem_ctx_persistence@process.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl2/igt at gem_ctx_persistence@process.html * igt at gem_exec_schedule@implicit-boths at bcs0: - shard-snb: [PASS][7] -> [INCOMPLETE][8] ([i915#82]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-snb2/igt at gem_exec_schedule@implicit-boths at bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-snb4/igt at gem_exec_schedule@implicit-boths at bcs0.html * igt at gem_exec_whisper@basic-queues-priority: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-glk8/igt at gem_exec_whisper@basic-queues-priority.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-glk9/igt at gem_exec_whisper@basic-queues-priority.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-glk4/igt at kms_big_fb@linear-64bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_color@pipe-b-ctm-negative: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +9 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl10/igt at kms_color@pipe-b-ctm-negative.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl8/igt at kms_color@pipe-b-ctm-negative.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][15] -> [DMESG-FAIL][16] ([i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#95]) +11 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html * igt at kms_plane@plane-position-covered-pipe-a-planes: - shard-snb: [PASS][23] -> [SKIP][24] ([fdo#109271]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-snb5/igt at kms_plane@plane-position-covered-pipe-a-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-snb2/igt at kms_plane@plane-position-covered-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109642] / [fdo#111068]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-iclb7/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][29] -> [FAIL][30] ([i915#173]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-iclb6/igt at kms_psr@no_drrs.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-iclb4/igt at kms_psr@psr2_sprite_blt.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [PASS][33] -> [INCOMPLETE][34] ([i915#69]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl3/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl1/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +5 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at kms_vblank@pipe-b-wait-forked-hang: - shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-apl1/igt at kms_vblank@pipe-b-wait-forked-hang.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-apl3/igt at kms_vblank@pipe-b-wait-forked-hang.html * igt at perf@blocking-parameterized: - shard-kbl: [PASS][39] -> [FAIL][40] ([i915#1542]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl1/igt at perf@blocking-parameterized.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl4/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_exec_endless@dispatch at rcs0: - shard-tglb: [INCOMPLETE][41] -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-tglb7/igt at gem_exec_endless@dispatch at rcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-tglb8/igt at gem_exec_endless@dispatch at rcs0.html * igt at gem_exec_flush@basic-uc-rw-default: - shard-hsw: [INCOMPLETE][43] ([i915#61]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-hsw8/igt at gem_exec_flush@basic-uc-rw-default.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-hsw7/igt at gem_exec_flush@basic-uc-rw-default.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [INCOMPLETE][45] ([i915#82]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_suspend@basic-s3: - shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl1/igt at gem_exec_suspend@basic-s3.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl4/igt at gem_exec_suspend@basic-s3.html * igt at gem_shrink@reclaim: - shard-hsw: [SKIP][49] ([fdo#109271]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-hsw1/igt at gem_shrink@reclaim.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-hsw5/igt at gem_shrink@reclaim.html * igt at i915_pm_rpm@dpms-non-lpsp: - shard-apl: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-apl4/igt at i915_pm_rpm@dpms-non-lpsp.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-apl1/igt at i915_pm_rpm@dpms-non-lpsp.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][53] ([i915#118] / [i915#95]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-glk9/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge: - shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +13 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][63] ([i915#1188]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-iclb4/igt at kms_psr@psr2_sprite_mmap_gtt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_psr@suspend: - shard-skl: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +5 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl10/igt at kms_psr@suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl5/igt at kms_psr@suspend.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][71] ([i915#31]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl2/igt at kms_setmode@basic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl2/igt at kms_setmode@basic.html #### Warnings #### * igt at i915_suspend@fence-restore-untiled: - shard-kbl: [INCOMPLETE][73] ([i915#155]) -> [DMESG-WARN][74] ([i915#180]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl3/igt at i915_suspend@fence-restore-untiled.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html * igt at kms_content_protection@atomic: - shard-kbl: [TIMEOUT][75] ([i915#1319]) -> [TIMEOUT][76] ([i915#1319] / [i915#1958]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-kbl2/igt at kms_content_protection@atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-kbl4/igt at kms_content_protection@atomic.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [DMESG-WARN][77] ([i915#1226]) -> [SKIP][78] ([fdo#109349]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-iclb4/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [FAIL][79] ([i915#1525]) -> [DMESG-FAIL][80] ([i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-apl8/igt at kms_fbcon_fbt@fbc.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-apl1/igt at kms_fbcon_fbt@fbc.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][81] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][82] ([fdo#108145] / [i915#1982]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8630/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8630 -> Patchwork_17957 CI-20190529: 20190529 CI_DRM_8630: bd2e730744f57bd02dba9c9b0ef64b3b1b8850e4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17957: 39ae8f5dde72d43e63c5de8d838c9b363b6741f6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17957/index.html From lkp at intel.com Tue Jun 16 04:18:23 2020 From: lkp at intel.com (kernel test robot) Date: Tue, 16 Jun 2020 12:18:23 +0800 Subject: [Intel-gfx] [drm-intel:for-linux-next-fixes 4/16] drivers/gpu/drm/i915/gt/selftest_lrc.c:1402:3: error: too few arguments to function 'engine_heartbeat_enable' Message-ID: <202006161220.qdjmXp6k%lkp@intel.com> tree: git://anongit.freedesktop.org/drm-intel for-linux-next-fixes head: add78d27d388520cbed6a7bf01d1e0afa183314d commit: 04dc41776145f539ab6da442cb633e45539bed9a [4/16] drm/i915/gt: Prevent timeslicing into unpreemptable requests config: i386-allmodconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5953: drivers/gpu/drm/i915/gt/selftest_lrc.c: In function 'live_timeslice_nopreempt': drivers/gpu/drm/i915/gt/selftest_lrc.c:1333:3: error: too few arguments to function 'engine_heartbeat_disable' 1333 | engine_heartbeat_disable(engine); | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/selftest_lrc.c:54:13: note: declared here 54 | static void engine_heartbeat_disable(struct intel_engine_cs *engine, | ^~~~~~~~~~~~~~~~~~~~~~~~ >> drivers/gpu/drm/i915/gt/selftest_lrc.c:1402:3: error: too few arguments to function 'engine_heartbeat_enable' 1402 | engine_heartbeat_enable(engine); | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/selftest_lrc.c:64:13: note: declared here 64 | static void engine_heartbeat_enable(struct intel_engine_cs *engine, | ^~~~~~~~~~~~~~~~~~~~~~~ vim +/engine_heartbeat_enable +1402 drivers/gpu/drm/i915/gt/selftest_lrc.c 1300 1301 static int live_timeslice_nopreempt(void *arg) 1302 { 1303 struct intel_gt *gt = arg; 1304 struct intel_engine_cs *engine; 1305 enum intel_engine_id id; 1306 struct igt_spinner spin; 1307 int err = 0; 1308 1309 /* 1310 * We should not timeslice into a request that is marked with 1311 * I915_REQUEST_NOPREEMPT. 1312 */ 1313 if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) 1314 return 0; 1315 1316 if (igt_spinner_init(&spin, gt)) 1317 return -ENOMEM; 1318 1319 for_each_engine(engine, gt, id) { 1320 struct intel_context *ce; 1321 struct i915_request *rq; 1322 unsigned long timeslice; 1323 1324 if (!intel_engine_has_preemption(engine)) 1325 continue; 1326 1327 ce = intel_context_create(engine); 1328 if (IS_ERR(ce)) { 1329 err = PTR_ERR(ce); 1330 break; 1331 } 1332 1333 engine_heartbeat_disable(engine); 1334 timeslice = xchg(&engine->props.timeslice_duration_ms, 1); 1335 1336 /* Create an unpreemptible spinner */ 1337 1338 rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK); 1339 intel_context_put(ce); 1340 if (IS_ERR(rq)) { 1341 err = PTR_ERR(rq); 1342 goto out_heartbeat; 1343 } 1344 1345 i915_request_get(rq); 1346 i915_request_add(rq); 1347 1348 if (!igt_wait_for_spinner(&spin, rq)) { 1349 i915_request_put(rq); 1350 err = -ETIME; 1351 goto out_spin; 1352 } 1353 1354 set_bit(I915_FENCE_FLAG_NOPREEMPT, &rq->fence.flags); 1355 i915_request_put(rq); 1356 1357 /* Followed by a maximum priority barrier (heartbeat) */ 1358 1359 ce = intel_context_create(engine); 1360 if (IS_ERR(ce)) { 1361 err = PTR_ERR(rq); 1362 goto out_spin; 1363 } 1364 1365 rq = intel_context_create_request(ce); 1366 intel_context_put(ce); 1367 if (IS_ERR(rq)) { 1368 err = PTR_ERR(rq); 1369 goto out_spin; 1370 } 1371 1372 rq->sched.attr.priority = I915_PRIORITY_BARRIER; 1373 i915_request_get(rq); 1374 i915_request_add(rq); 1375 1376 /* 1377 * Wait until the barrier is in ELSP, and we know timeslicing 1378 * will have been activated. 1379 */ 1380 if (wait_for_submit(engine, rq, HZ / 2)) { 1381 i915_request_put(rq); 1382 err = -ETIME; 1383 goto out_spin; 1384 } 1385 1386 /* 1387 * Since the ELSP[0] request is unpreemptible, it should not 1388 * allow the maximum priority barrier through. Wait long 1389 * enough to see if it is timesliced in by mistake. 1390 */ 1391 if (i915_request_wait(rq, 0, timeslice_threshold(engine)) >= 0) { 1392 pr_err("%s: I915_PRIORITY_BARRIER request completed, bypassing no-preempt request\n", 1393 engine->name); 1394 err = -EINVAL; 1395 } 1396 i915_request_put(rq); 1397 1398 out_spin: 1399 igt_spinner_end(&spin); 1400 out_heartbeat: 1401 xchg(&engine->props.timeslice_duration_ms, timeslice); > 1402 engine_heartbeat_enable(engine); 1403 if (err) 1404 break; 1405 1406 if (igt_flush_test(gt->i915)) { 1407 err = -EIO; 1408 break; 1409 } 1410 } 1411 1412 igt_spinner_fini(&spin); 1413 return err; 1414 } 1415 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 74221 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200616/5f0b0319/attachment-0001.gz> From lkp at intel.com Tue Jun 16 05:43:03 2020 From: lkp at intel.com (kernel test robot) Date: Tue, 16 Jun 2020 13:43:03 +0800 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <20200612230444.10121-4-manasi.d.navare@intel.com> Message-ID: <20200616054303.GI23105@xsang-OptiPlex-9020> Hi Manasi, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next linus/master next-20200613] [cannot apply to tegra-drm/drm/tegra/for-next drm/drm-next v5.7] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Manasi-Navare/VRR-capable-attach-prop-in-i915-DPCD-helper-VRR-debugfs/20200613-070517 base: git://anongit.freedesktop.org/drm-intel for-linux-next :::::: branch date: 2 days ago :::::: commit date: 2 days ago compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> cppcheck warnings: (new ones prefixed by >>) >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2258:0: warning: Invalid number of character '{' when no macros are defined. [syntaxError] ^ >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2258:0: warning: Invalid number of character '{' when these macros are defined: 'CONFIG_DEBUG_FS'. [syntaxError] ^ >> drivers/gpu/drm/i915/display/intel_display_debugfs.c:2258:0: warning: Invalid number of character '{' when these macros are defined: 'CONFIG_DRM_FBDEV_EMULATION'. [syntaxError] ^ # https://github.com/0day-ci/linux/commit/670af3cf7a3a36bb87776fbfd7f913cd33681bbc git remote add linux-review https://github.com/0day-ci/linux git remote update linux-review git checkout 670af3cf7a3a36bb87776fbfd7f913cd33681bbc vim +2258 drivers/gpu/drm/i915/display/intel_display_debugfs.c 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2202 926b005cd8c4e3 Jani Nikula 2020-02-11 2203 /** 926b005cd8c4e3 Jani Nikula 2020-02-11 2204 * intel_connector_debugfs_add - add i915 specific connector debugfs files 926b005cd8c4e3 Jani Nikula 2020-02-11 2205 * @connector: pointer to a registered drm_connector 926b005cd8c4e3 Jani Nikula 2020-02-11 2206 * 926b005cd8c4e3 Jani Nikula 2020-02-11 2207 * Cleanup will be done by drm_connector_unregister() through a call to 926b005cd8c4e3 Jani Nikula 2020-02-11 2208 * drm_debugfs_connector_remove(). 926b005cd8c4e3 Jani Nikula 2020-02-11 2209 * 926b005cd8c4e3 Jani Nikula 2020-02-11 2210 * Returns 0 on success, negative error codes on error. 926b005cd8c4e3 Jani Nikula 2020-02-11 2211 */ 926b005cd8c4e3 Jani Nikula 2020-02-11 2212 int intel_connector_debugfs_add(struct drm_connector *connector) 926b005cd8c4e3 Jani Nikula 2020-02-11 2213 { 926b005cd8c4e3 Jani Nikula 2020-02-11 2214 struct dentry *root = connector->debugfs_entry; 926b005cd8c4e3 Jani Nikula 2020-02-11 2215 struct drm_i915_private *dev_priv = to_i915(connector->dev); 926b005cd8c4e3 Jani Nikula 2020-02-11 2216 926b005cd8c4e3 Jani Nikula 2020-02-11 2217 /* The connector must have been registered beforehands. */ 926b005cd8c4e3 Jani Nikula 2020-02-11 2218 if (!root) 926b005cd8c4e3 Jani Nikula 2020-02-11 2219 return -ENODEV; 926b005cd8c4e3 Jani Nikula 2020-02-11 2220 926b005cd8c4e3 Jani Nikula 2020-02-11 2221 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2222 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2223 connector, &i915_panel_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2224 debugfs_create_file("i915_psr_sink_status", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2225 connector, &i915_psr_sink_status_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2226 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2227 926b005cd8c4e3 Jani Nikula 2020-02-11 2228 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 926b005cd8c4e3 Jani Nikula 2020-02-11 2229 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 926b005cd8c4e3 Jani Nikula 2020-02-11 2230 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { 926b005cd8c4e3 Jani Nikula 2020-02-11 2231 debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2232 connector, &i915_hdcp_sink_capability_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2233 } 926b005cd8c4e3 Jani Nikula 2020-02-11 2234 926b005cd8c4e3 Jani Nikula 2020-02-11 2235 if (INTEL_GEN(dev_priv) >= 10 && 926b005cd8c4e3 Jani Nikula 2020-02-11 2236 (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 926b005cd8c4e3 Jani Nikula 2020-02-11 2237 connector->connector_type == DRM_MODE_CONNECTOR_eDP)) 926b005cd8c4e3 Jani Nikula 2020-02-11 2238 debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, 926b005cd8c4e3 Jani Nikula 2020-02-11 2239 connector, &i915_dsc_fec_support_fops); 926b005cd8c4e3 Jani Nikula 2020-02-11 2240 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2241 if (INTEL_GEN(dev_priv) >= 12) 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2242 debugfs_create_file("vrr_range", S_IRUGO, 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2243 root, connector, &vrr_range_fops); 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2244 } 670af3cf7a3a36 Bhanuprakash Modem 2020-06-12 2245 8806211fe7b306 Anshuman Gupta 2020-04-15 2246 /* Legacy panels doesn't lpsp on any platform */ 8806211fe7b306 Anshuman Gupta 2020-04-15 2247 if ((INTEL_GEN(dev_priv) >= 9 || IS_HASWELL(dev_priv) || 8806211fe7b306 Anshuman Gupta 2020-04-15 2248 IS_BROADWELL(dev_priv)) && 8806211fe7b306 Anshuman Gupta 2020-04-15 2249 (connector->connector_type == DRM_MODE_CONNECTOR_DSI || 8806211fe7b306 Anshuman Gupta 2020-04-15 2250 connector->connector_type == DRM_MODE_CONNECTOR_eDP || 8806211fe7b306 Anshuman Gupta 2020-04-15 2251 connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 8806211fe7b306 Anshuman Gupta 2020-04-15 2252 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 8806211fe7b306 Anshuman Gupta 2020-04-15 2253 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)) 8806211fe7b306 Anshuman Gupta 2020-04-15 2254 debugfs_create_file("i915_lpsp_capability", 0444, root, 8806211fe7b306 Anshuman Gupta 2020-04-15 2255 connector, &i915_lpsp_capability_fops); 8806211fe7b306 Anshuman Gupta 2020-04-15 2256 926b005cd8c4e3 Jani Nikula 2020-02-11 2257 return 0; 926b005cd8c4e3 Jani Nikula 2020-02-11 @2258 } :::::: The code at line 2258 was first introduced by commit :::::: 926b005cd8c4e325ab918edea0fbdd1d25d1ba28 drm/i915: split out display debugfs to a separate file :::::: TO: Jani Nikula <jani.nikula at intel.com> :::::: CC: Jani Nikula <jani.nikula at intel.com> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org From daniel.vetter at ffwll.ch Tue Jun 16 06:50:06 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 16 Jun 2020 08:50:06 +0200 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <CACvgo51AVVOxhGK2Uin=ZLgPpihJiEsnc6pvAyKqFKPvLdOzLA@mail.gmail.com> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-7-daniel.vetter@ffwll.ch> <CACvgo51AVVOxhGK2Uin=ZLgPpihJiEsnc6pvAyKqFKPvLdOzLA@mail.gmail.com> Message-ID: <CAKMK7uEEkH+8BuFcFUVTv6p8swZZTwcho-HNx5GdZTO1vHDoeg@mail.gmail.com> On Mon, Jun 15, 2020 at 11:35 PM Emil Velikov <emil.l.velikov at gmail.com> wrote: > > Hi Daniel, > > On Fri, 12 Jun 2020 at 17:01, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > The atomic helpers try really hard to not lose track of things, > > duplicating enabled tracking in the driver is at best confusing. > > Double-enabling or disabling is a bug in atomic helpers. > > > > In the fb_dirty function we can just assume that the fb always exists, > > simple display pipe helpers guarantee that the crtc is only enabled > > together with the output, so we always have a primary plane around. > > > > Now in the update function we need to be a notch more careful, since > > that can also get called when the crtc is off. And we don't want to > > upload frames when that's the case, so filter that out too. > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Maxime Ripard <mripard at kernel.org> > > Cc: Thomas Zimmermann <tzimmermann at suse.de> > > Cc: David Airlie <airlied at linux.ie> > > Cc: Daniel Vetter <daniel at ffwll.ch> > > Cc: David Lechner <david at lechnology.com> > > --- > > drivers/gpu/drm/drm_mipi_dbi.c | 16 ++++++---------- > > drivers/gpu/drm/tiny/ili9225.c | 12 +++--------- > > drivers/gpu/drm/tiny/st7586.c | 11 +++-------- > > include/drm/drm_mipi_dbi.h | 5 ----- > > 4 files changed, 12 insertions(+), 32 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c > > index fd8d672972a9..79532b9a324a 100644 > > --- a/drivers/gpu/drm/drm_mipi_dbi.c > > +++ b/drivers/gpu/drm/drm_mipi_dbi.c > > @@ -268,7 +268,7 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) > > bool full; > > void *tr; > > > > - if (!dbidev->enabled) > > + if (WARN_ON(!fb)) > > return; > > > AFAICT no other driver has such WARN_ON. Let's drop that - it is > pretty confusing and misleading as-is. Yeah, this is a helper library which might be used wrongly by drivers. That's why I put it in - if you don't put all the various calls together correctly, this should at least catch one case. So really would like to keep this, can I convince you? -Daniel > With that, patches 7/8 and 8/8 are: > Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com> > > -Emil -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From colin.king at canonical.com Tue Jun 16 08:21:29 2020 From: colin.king at canonical.com (Colin King) Date: Tue, 16 Jun 2020 09:21:29 +0100 Subject: [Intel-gfx] [PATCH][next] drm/i915: fix a couple of spelling mistakes in kernel parameter help text Message-ID: <20200616082129.65517-1-colin.king@canonical.com> From: Colin Ian King <colin.king at canonical.com> There are a couple of spelling mistakes in kernel parameter help text, namely "helpfull" and "paramters". Fix them. Signed-off-by: Colin Ian King <colin.king at canonical.com> --- drivers/gpu/drm/i915/i915_params.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index a7b61e6ec508..8d8db9ff0a48 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -99,8 +99,8 @@ i915_param_named_unsafe(enable_psr, int, 0400, i915_param_named(psr_safest_params, bool, 0400, "Replace PSR VBT parameters by the safest and not optimal ones. This " - "is helpfull to detect if PSR issues are related to bad values set in " - " VBT. (0=use VBT paramters, 1=use safest parameters)"); + "is helpful to detect if PSR issues are related to bad values set in " + " VBT. (0=use VBT parameters, 1=use safest parameters)"); i915_param_named_unsafe(force_probe, charp, 0400, "Force probe the driver for specified devices. " -- 2.27.0.rc0 From shaofeng.tang at intel.com Tue Jun 16 08:29:20 2020 From: shaofeng.tang at intel.com (Shaofeng Tang) Date: Tue, 16 Jun 2020 16:29:20 +0800 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL Message-ID: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> [Why] Query if vgpu is active, it is useful to the user. Currently, only the primary plane is usable when vgpu is active. The value of vgpu active is useful for user to determine how many planes can be used. also useful for user to determine different behaviors according to vgpu is active or not. [How] Add a switch-case in the IOCTL 'i915_getparam_ioctl' to return 'intel_vgpu_active' Signed-off-by: Shaofeng Tang <shaofeng.tang at intel.com> --- drivers/gpu/drm/i915/i915_getparam.c | 3 +++ include/uapi/drm/i915_drm.h | 6 ++++++ tools/include/uapi/drm/i915_drm.h | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index d042644..c50555b 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -161,6 +161,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, case I915_PARAM_PERF_REVISION: value = i915_perf_ioctl_version(); break; + case I915_PARAM_IS_GVT: + value = intel_vgpu_active(i915); + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 14b67cd..74f06e2 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ enum drm_i915_pmu_engine_sample { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h index 2813e57..ecaad82 100644 --- a/tools/include/uapi/drm/i915_drm.h +++ b/tools/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ enum drm_i915_pmu_engine_sample { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { -- 1.9.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:34 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:34 +0100 Subject: [Intel-gfx] [PATCH 2/9] drm/i915/selftests: Use friendly request names for live_timeslice_rewind In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-2-chris@chris-wilson.co.uk> Rather than mixing [012] and (A1, A2, B2) for the request indices, use the enums throughout. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 3d088116a055..72d52c9c042f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -1176,18 +1176,18 @@ static int live_timeslice_rewind(void *arg) goto err; } - rq[0] = create_rewinder(ce, NULL, slot, X); - if (IS_ERR(rq[0])) { + rq[A1] = create_rewinder(ce, NULL, slot, X); + if (IS_ERR(rq[A1])) { intel_context_put(ce); goto err; } - rq[1] = create_rewinder(ce, NULL, slot, Y); + rq[A2] = create_rewinder(ce, NULL, slot, Y); intel_context_put(ce); - if (IS_ERR(rq[1])) + if (IS_ERR(rq[A2])) goto err; - err = wait_for_submit(engine, rq[1], HZ / 2); + err = wait_for_submit(engine, rq[A2], HZ / 2); if (err) { pr_err("%s: failed to submit first context\n", engine->name); @@ -1200,12 +1200,12 @@ static int live_timeslice_rewind(void *arg) goto err; } - rq[2] = create_rewinder(ce, rq[0], slot, Z); + rq[B1] = create_rewinder(ce, rq[A1], slot, Z); intel_context_put(ce); if (IS_ERR(rq[2])) goto err; - err = wait_for_submit(engine, rq[2], HZ / 2); + err = wait_for_submit(engine, rq[B1], HZ / 2); if (err) { pr_err("%s: failed to submit second context\n", engine->name); @@ -1213,6 +1213,7 @@ static int live_timeslice_rewind(void *arg) } /* ELSP[] = { { A:rq1, A:rq2 }, { B:rq1 } } */ + ENGINE_TRACE(engine, "forcing tasklet for rewind\n"); if (i915_request_is_active(rq[A2])) { /* semaphore yielded! */ /* Wait for the timeslice to kick in */ del_timer(&engine->execlists.timer); -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:41 +0100 Subject: [Intel-gfx] [PATCH 9/9] drm/i915/gt: Convert stats.active to plain unsigned int In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-9-chris@chris-wilson.co.uk> As context-in/out is now always serialised, we do not have to worry about concurrent enabling/disable of the busy-stats and can reduce the atomic_t active to a plain unsigned int, and the seqlock to a seqcount. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++--- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 28 +++++++------------- drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +-- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 39471674a40f..c378f1c4afff 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -338,7 +338,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) engine->schedule = NULL; ewma__engine_latency_init(&engine->latency); - seqlock_init(&engine->stats.lock); + seqcount_init(&engine->stats.lock); ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); @@ -1606,7 +1606,7 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) * If the engine is executing something at the moment * add it to the total. */ - if (atomic_read(&engine->stats.active)) + if (engine->stats.active) total = ktime_add(total, ktime_sub(ktime_get(), engine->stats.start)); @@ -1625,9 +1625,9 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) ktime_t total; do { - seq = read_seqbegin(&engine->stats.lock); + seq = read_seqcount_begin(&engine->stats.lock); total = __intel_engine_get_busy_time(engine); - } while (read_seqretry(&engine->stats.lock, seq)); + } while (read_seqcount_retry(&engine->stats.lock, seq)); return total; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h index 58491eae3482..09e4aca8cff6 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_stats.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -15,35 +15,25 @@ static inline void intel_engine_context_in(struct intel_engine_cs *engine) { - unsigned long flags; + raw_write_seqcount_begin(&engine->stats.lock); - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + if (!engine->stats.active++) engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); + + raw_write_seqcount_end(&engine->stats.lock); } static inline void intel_engine_context_out(struct intel_engine_cs *engine) { - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); + raw_write_seqcount_begin(&engine->stats.lock); - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { + GEM_BUG_ON(!engine->stats.active); + if (!--engine->stats.active) engine->stats.total = ktime_add(engine->stats.total, ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); + + raw_write_seqcount_end(&engine->stats.lock); } #endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index ca124f229f65..50951a129db5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -557,12 +557,12 @@ struct intel_engine_cs { /** * @active: Number of contexts currently scheduled in. */ - atomic_t active; + unsigned int active; /** * @lock: Lock protecting the below fields. */ - seqlock_t lock; + seqcount_t lock; /** * @total: Total time this engine was busy. -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:40 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:40 +0100 Subject: [Intel-gfx] [PATCH 8/9] drm/i915/gt: Extract busy-stats for ring-scheduler In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-8-chris@chris-wilson.co.uk> Lift the busy-stats context-in/out implementation out of intel_lrc, so that we can reuse it for other scheduler implementations. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------------- 2 files changed, 50 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include <linux/atomic.h> +#include <linux/ktime.h> +#include <linux/seqlock.h> + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 09ec7242fbcb..bd82abfdc49d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1194,39 +1195,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:35 +0100 Subject: [Intel-gfx] [PATCH 3/9] drm/i915/selftests: Enable selftesting of busy-stats In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-3-chris@chris-wilson.co.uk> A couple of very simple tests to ensure that the basic properties of per-engine busyness accounting [0% and 100% busy] are faithful. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 94 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ 2 files changed, 99 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..fb0fd8a7db9a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,99 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t de; + u64 dt; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + /* 100% busy */ + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + break; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + break; + } + + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (100 * de < 95 * dt || 95 * de > 100 * dt) { + pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + igt_spinner_fini(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +170,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:37 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:37 +0100 Subject: [Intel-gfx] [PATCH 5/9] drm/i915/execlists: Defer schedule_out until after the next dequeue In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-5-chris@chris-wilson.co.uk> Inside schedule_out, we do extra work upon idling the context, such as updating the runtime, kicking off retires, kicking virtual engines. However, if we are in a series of processing single requests per contexts, we may find ourselves scheduling out the context, only to immediately schedule it back in during dequeue. This is just extra work that we can avoid if we keep the context marked as inflight across the dequeue. This becomes more significant later on for minimising virtual engine misses. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++++++++++++++----- 4 files changed, 51 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 4954b0df4864..b63db45bab7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -45,8 +45,8 @@ struct intel_context { struct intel_engine_cs *engine; struct intel_engine_cs *inflight; -#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2) -#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2) +#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 3) +#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 3) struct i915_address_space *vm; struct i915_gem_context __rcu *gem_context; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index fbb8ac659b82..be1730773db8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -515,6 +515,8 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine) memset(execlists->pending, 0, sizeof(execlists->pending)); execlists->active = memset(execlists->inflight, 0, sizeof(execlists->inflight)); + execlists->inactive = + memset(execlists->post, 0, sizeof(execlists->post)); execlists->queue_priority_hint = INT_MIN; execlists->queue = RB_ROOT_CACHED; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 073c3769e8cc..31cf60cef5a8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -208,6 +208,10 @@ struct intel_engine_execlists { * @active: the currently known context executing on HW */ struct i915_request * const *active; + /** + * @inactive: the current vacancy of completed CS + */ + struct i915_request **inactive; /** * @inflight: the set of contexts submitted and acknowleged by HW * @@ -225,6 +229,15 @@ struct intel_engine_execlists { * preemption or idle-to-active event. */ struct i915_request *pending[EXECLIST_MAX_PORTS + 1]; + /** + * @post: the set of completed context switches + * + * Since we may want to stagger the processing of the CS switches + * with the next submission, so that the context are notionally + * kept in flight across the dequeue, we defer scheduling out of + * the completed context switches. + */ + struct i915_request *post[2 * EXECLIST_MAX_PORTS + 1]; /** * @port_mask: number of execlist ports - 1 diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 40c5085765da..adc14adfa89c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1385,6 +1385,8 @@ __execlists_schedule_in(struct i915_request *rq) execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); + CE_TRACE(ce, "schedule-in, ccid:%x\n", ce->lrc.ccid); + return engine; } @@ -1431,6 +1433,8 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ + CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + /* * If we have just completed this context, the engine may now be * idle and we want to re-enter powersaving. @@ -2055,9 +2059,10 @@ static void set_preempt_timeout(struct intel_engine_cs *engine, active_preempt_timeout(engine, rq)); } -static inline void clear_ports(struct i915_request **ports, int count) +static inline struct i915_request ** +clear_ports(struct i915_request **ports, int count) { - memset_p((void **)ports, NULL, count); + return memset_p((void **)ports, NULL, count); } static void execlists_dequeue(struct intel_engine_cs *engine) @@ -2433,7 +2438,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (!memcmp(active, execlists->pending, (port - execlists->pending + 1) * sizeof(*port))) { do - execlists_schedule_out(fetch_and_zero(port)); + *execlists->inactive++ = *port; while (port-- != execlists->pending); goto skip_submit; @@ -2447,6 +2452,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + execlists->pending[0] = NULL; } } @@ -2456,12 +2462,12 @@ cancel_port_requests(struct intel_engine_execlists * const execlists) struct i915_request * const *port; for (port = execlists->pending; *port; port++) - execlists_schedule_out(*port); + *execlists->inactive++ = *port; clear_ports(execlists->pending, ARRAY_SIZE(execlists->pending)); /* Mark the end of active before we overwrite *active */ for (port = xchg(&execlists->active, execlists->pending); *port; port++) - execlists_schedule_out(*port); + *execlists->inactive++ = *port; clear_ports(execlists->inflight, ARRAY_SIZE(execlists->inflight)); smp_wmb(); /* complete the seqlock for execlists_active() */ @@ -2622,7 +2628,7 @@ static void process_csb(struct intel_engine_cs *engine) /* cancel old inflight, prepare for switch */ trace_ports(execlists, "preempted", old); while (*old) - execlists_schedule_out(*old++); + *execlists->inactive++ = *old++; /* switch pending to inflight */ GEM_BUG_ON(!assert_pending_valid(execlists, "promote")); @@ -2679,7 +2685,7 @@ static void process_csb(struct intel_engine_cs *engine) regs[CTX_RING_TAIL]); } - execlists_schedule_out(*execlists->active++); + *execlists->inactive++ = *execlists->active++; GEM_BUG_ON(execlists->active - execlists->inflight > execlists_num_ports(execlists)); @@ -2703,6 +2709,20 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } +static void post_process_csb(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request **port; + + if (!el->post[0]) + return; + + GEM_BUG_ON(el->post[2 * EXECLIST_MAX_PORTS]); + for (port = el->post; *port; port++) + execlists_schedule_out(*port); + el->inactive = clear_ports(el->post, port - el->post); +} + static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -2971,8 +2991,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->active; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at active:%zd\n", - port - el->active); + "ccid:%x found at active:%zd\n", + ccid, port - el->active); return rq; } } @@ -2980,8 +3000,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->pending; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at pending:%zd\n", - port - el->pending); + "ccid:%x found at pending:%zd\n", + ccid, port - el->pending); return rq; } } @@ -3123,6 +3143,8 @@ static void execlists_submission_tasklet(unsigned long data) spin_unlock_irqrestore(&engine->active.lock, flags); rcu_read_unlock(); } + + post_process_csb(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -4061,8 +4083,6 @@ static void enable_execlists(struct intel_engine_cs *engine) ENGINE_POSTING_READ(engine, RING_HWS_PGA); enable_error_interrupt(engine); - - engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); } static bool unexpected_starting_state(struct intel_engine_cs *engine) @@ -5104,6 +5124,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) else execlists->csb_size = GEN11_CSB_ENTRIES; + engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); if (INTEL_GEN(engine->i915) >= 11) { execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32); execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32); -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:39 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:39 +0100 Subject: [Intel-gfx] [PATCH 7/9] drm/i915/gt: Drop atomic for engine->fw_active tracking In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-7-chris@chris-wilson.co.uk> Since schedule-in/out is now entirely serialised by the tasklet bitlock, we do not need to worry about concurrent in/out operations and so reduce the atomic operations to plain instructions. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index be1730773db8..39471674a40f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1531,7 +1531,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, drm_printf(m, "\tLatency: %luus\n", ewma__engine_latency_read(&engine->latency)); drm_printf(m, "\tForcewake: %x domains, %d active\n", - engine->fw_domain, atomic_read(&engine->fw_active)); + engine->fw_domain, READ_ONCE(engine->fw_active)); rcu_read_lock(); rq = READ_ONCE(engine->heartbeat.systole); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 31cf60cef5a8..ca124f229f65 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -335,7 +335,7 @@ struct intel_engine_cs { * as possible. */ enum forcewake_domains fw_domain; - atomic_t fw_active; + unsigned int fw_active; unsigned long context_tag; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 8b3959207c02..09ec7242fbcb 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1380,7 +1380,7 @@ __execlists_schedule_in(struct i915_request *rq) ce->lrc.ccid |= engine->execlists.ccid; __intel_gt_pm_get(engine->gt); - if (engine->fw_domain && !atomic_fetch_inc(&engine->fw_active)) + if (engine->fw_domain && !engine->fw_active++) intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); @@ -1451,7 +1451,7 @@ static inline void __execlists_schedule_out(struct i915_request *rq) intel_context_update_runtime(ce); intel_engine_context_out(engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); - if (engine->fw_domain && !atomic_dec_return(&engine->fw_active)) + if (engine->fw_domain && !--engine->fw_active) intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:36 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:36 +0100 Subject: [Intel-gfx] [PATCH 4/9] drm/i915/execlists: Replace direct submit with direct call to tasklet In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-4-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine.h | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +++---- drivers/gpu/drm/i915/gt/intel_lrc.c | 78 +++++++------------ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 5 files changed, 46 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..c77b3c0d2b3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -210,6 +210,7 @@ int intel_engine_resume(struct intel_engine_cs *engine); int intel_ring_submission_setup(struct intel_engine_cs *engine); +void __intel_engine_stop_cs(struct intel_engine_cs *engine); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 045179c65c44..fbb8ac659b82 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,33 +903,34 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +void __intel_engine_stop_cs(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); - int err; + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + intel_uncore_posting_read_fw(uncore, mode); +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + __intel_engine_stop_cs(engine); - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, + if (__intel_wait_for_register_fw(engine->uncore, + RING_MI_MODE(engine->mmio_base), + MODE_IDLE, MODE_IDLE, 1000, stop_timeout(engine), NULL)) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); - err = -ETIMEDOUT; + return -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - - return err; + return 0; } void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..40c5085765da 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2703,16 +2703,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3102,7 +3092,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3112,7 +3102,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3122,16 +3111,17 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); + + if (!engine->execlists.pending[0]) { unsigned long flags; + rcu_read_lock(); /* protect peeking at execlists->active */ spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); + execlists_dequeue(engine); spin_unlock_irqrestore(&engine->active.lock, flags); - - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); + rcu_read_unlock(); } } @@ -3163,26 +3153,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3196,20 +3176,22 @@ static void flush_csb(struct intel_engine_cs *engine) { struct intel_engine_execlists *el = &engine->execlists; - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); + if (!tasklet_trylock(&el->tasklet)) { + tasklet_hi_schedule(&el->tasklet); + return; } + + if (!reset_in_progress(el)) + execlists_submission_tasklet((unsigned long)engine); + + tasklet_unlock(&el->tasklet); } static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); + bool submit = false; /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3224,10 +3206,13 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + submit = submit_queue(engine, request); } spin_unlock_irqrestore(&engine->active.lock, flags); + + if (submit) + flush_csb(engine); } static void __execlists_context_fini(struct intel_context *ce) @@ -4113,7 +4098,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4130,10 +4114,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4147,7 +4127,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) * FIXME: Wa for more modern gens needs to be validated */ ring_set_paused(engine, 1); - intel_engine_stop_cs(engine); + __intel_engine_stop_cs(engine); engine->execlists.reset_ccid = active_ccid(engine); } @@ -4377,12 +4357,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + flush_csb(engine); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 7461936d549d..355ee8562bc1 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1597,6 +1597,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 92c628f18c60..4f1b82c7eeaf 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1925,9 +1925,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2213,11 +2211,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:38 +0100 Subject: [Intel-gfx] [PATCH 6/9] drm/i915/gt: ce->inflight updates are now serialised In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <20200616084141.3722-6-chris@chris-wilson.co.uk> Since schedule-in and schedule-out are now both always under the tasklet bitlock, we can reduce the individual atomic operations to simple instructions and worry less. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 43 ++++++++++++----------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index adc14adfa89c..8b3959207c02 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1371,7 +1371,7 @@ __execlists_schedule_in(struct i915_request *rq) unsigned int tag = ffs(READ_ONCE(engine->context_tag)); GEM_BUG_ON(tag == 0 || tag >= BITS_PER_LONG); - clear_bit(tag - 1, &engine->context_tag); + __clear_bit(tag - 1, &engine->context_tag); ce->lrc.ccid = tag << (GEN11_SW_CTX_ID_SHIFT - 32); BUILD_BUG_ON(BITS_PER_LONG > GEN12_MAX_CONTEXT_HW_ID); @@ -1399,13 +1399,10 @@ execlists_schedule_in(struct i915_request *rq, int idx) GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine)); trace_i915_request_in(rq, idx); - old = READ_ONCE(ce->inflight); - do { - if (!old) { - WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq)); - break; - } - } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old))); + old = ce->inflight; + if (!old) + old = __execlists_schedule_in(rq); + WRITE_ONCE(ce->inflight, ptr_inc(old)); GEM_BUG_ON(intel_context_inflight(ce) != rq->engine); return i915_request_get(rq); @@ -1420,12 +1417,11 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce) tasklet_hi_schedule(&ve->base.execlists.tasklet); } -static inline void -__execlists_schedule_out(struct i915_request *rq, - struct intel_engine_cs * const engine, - unsigned int ccid) +static inline void __execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; + struct intel_engine_cs * const engine = ce->inflight; + unsigned int ccid; /* * NB process_csb() is not under the engine->active.lock and hence @@ -1433,7 +1429,7 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ - CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + CE_TRACE(ce, "schedule-out, ccid:%x\n", ce->lrc.ccid); /* * If we have just completed this context, the engine may now be @@ -1443,12 +1439,13 @@ __execlists_schedule_out(struct i915_request *rq, i915_request_completed(rq)) intel_engine_add_retire(engine, ce->timeline); + ccid = ce->lrc.ccid; ccid >>= GEN11_SW_CTX_ID_SHIFT - 32; ccid &= GEN12_MAX_CONTEXT_HW_ID; if (ccid < BITS_PER_LONG) { GEM_BUG_ON(ccid == 0); GEM_BUG_ON(test_bit(ccid - 1, &engine->context_tag)); - set_bit(ccid - 1, &engine->context_tag); + __set_bit(ccid - 1, &engine->context_tag); } intel_context_update_runtime(ce); @@ -1469,26 +1466,22 @@ __execlists_schedule_out(struct i915_request *rq, */ if (ce->engine != engine) kick_siblings(rq, ce); - - intel_context_put(ce); } static inline void execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; - struct intel_engine_cs *cur, *old; - u32 ccid; trace_i915_request_out(rq); - ccid = rq->context->lrc.ccid; - old = READ_ONCE(ce->inflight); - do - cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL; - while (!try_cmpxchg(&ce->inflight, &old, cur)); - if (!cur) - __execlists_schedule_out(rq, old, ccid); + GEM_BUG_ON(!ce->inflight); + ce->inflight = ptr_dec(ce->inflight); + if (!intel_context_inflight_count(ce)) { + __execlists_schedule_out(rq); + WRITE_ONCE(ce->inflight, NULL); + intel_context_put(ce); + } i915_request_put(rq); } -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 08:41:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 09:41:33 +0100 Subject: [Intel-gfx] [PATCH 1/9] drm/i915/selftests: Exercise far preemption rollbacks Message-ID: <20200616084141.3722-1-chris@chris-wilson.co.uk> Not too long ago, we realised we had issues with a rolling back a context so far for a preemption request we considered the resubmit not to be a rollback but a forward roll. This means we would issue a lite restore instead of forcing a full restore, continuing execution of the old requests rather than causing a preemption. Add a selftest to exercise such a far rollback, such that if we were to skip the full restore, we would execute invalid instructions in the ring and hang. Note that while I was able to confirm that this causes us to do a lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") disabled), it did not trick the HW into rolling past the old RING_TAIL. Myybe on other HW. References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 150 +++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 91543494f595..3d088116a055 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -363,6 +363,155 @@ static int live_unlite_preempt(void *arg) return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); } +static int live_unlite_ring(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + struct igt_spinner spin; + enum intel_engine_id id; + int err = 0; + + /* + * Setup a preemption event that will cause almost the entire ring + * to be unwound, potentially fooling our intel_ring_direction() + * into emitting a forward lite-restore instead of the rollback. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + for_each_engine(engine, gt, id) { + struct intel_context *ce[2] = {}; + struct i915_request *rq; + struct igt_live_test t; + int n; + + if (!intel_engine_has_preemption(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { + err = -EIO; + break; + } + engine_heartbeat_disable(engine); + + for (n = 0; n < ARRAY_SIZE(ce); n++) { + struct intel_context *tmp; + + tmp = intel_context_create(engine); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + goto err_ce; + } + + err = intel_context_pin(tmp); + if (err) { + intel_context_put(tmp); + goto err_ce; + } + + memset32(tmp->ring->vaddr, + 0xdeadbeef, /* trigger a hang if executed */ + tmp->ring->vma->size / sizeof(u32)); + + ce[n] = tmp; + } + + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + i915_request_get(rq); + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(gt); + i915_request_put(rq); + err = -ETIME; + goto err_ce; + } + + /* Fill the ring, until we will cause a wrap */ + n = 0; + while (intel_ring_direction(ce[0]->ring, + rq->wa_tail, + ce[0]->ring->tail) <= 0) { + struct i915_request *tmp; + + tmp = intel_context_create_request(ce[0]); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + i915_request_put(rq); + goto err_ce; + } + + i915_request_add(tmp); + intel_engine_flush_submission(engine); + n++; + } + intel_engine_flush_submission(engine); + pr_debug("%s: Filled ring with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", + engine->name, n, + ce[0]->ring->size, + ce[0]->ring->tail, + ce[0]->ring->emit, + rq->tail); + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, + rq->tail, + ce[0]->ring->tail) <= 0); + i915_request_put(rq); + + /* Create a second request to preempt the first ring */ + rq = intel_context_create_request(ce[1]); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_get(rq); + i915_request_add(rq); + + err = wait_for_submit(engine, rq, HZ / 2); + i915_request_put(rq); + if (err) { + pr_err("%s: preemption request was not submited\n", + engine->name); + err = -ETIME; + } + + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", + engine->name, + ce[0]->ring->tail, ce[0]->ring->emit, + ce[1]->ring->tail, ce[1]->ring->emit); + +err_ce: + intel_engine_flush_submission(engine); + igt_spinner_end(&spin); + for (n = 0; n < ARRAY_SIZE(ce); n++) { + if (IS_ERR_OR_NULL(ce[n])) + break; + + intel_context_unpin(ce[n]); + intel_context_put(ce[n]); + } + engine_heartbeat_enable(engine); + if (igt_live_test_end(&t)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + return err; +} + static int live_pin_rewind(void *arg) { struct intel_gt *gt = arg; @@ -4374,6 +4523,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_sanitycheck), SUBTEST(live_unlite_switch), SUBTEST(live_unlite_preempt), + SUBTEST(live_unlite_ring), SUBTEST(live_pin_rewind), SUBTEST(live_hold_reset), SUBTEST(live_error_interrupt), -- 2.20.1 From mika.kuoppala at linux.intel.com Tue Jun 16 08:55:04 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 11:55:04 +0300 Subject: [Intel-gfx] [PATCH 1/9] drm/i915/selftests: Exercise far preemption rollbacks In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <87a713s847.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Not too long ago, we realised we had issues with a rolling back a > context so far for a preemption request we considered the resubmit not > to be a rollback but a forward roll. This means we would issue a lite > restore instead of forcing a full restore, continuing execution of the > old requests rather than causing a preemption. Add a selftest to > exercise such a far rollback, such that if we were to skip the full > restore, we would execute invalid instructions in the ring and hang. > > Note that while I was able to confirm that this causes us to do a > lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: > Incrementally check for rewinding") disabled), it did not trick the HW > into rolling past the old RING_TAIL. Myybe on other HW. > > References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 150 +++++++++++++++++++++++++ > 1 file changed, 150 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index 91543494f595..3d088116a055 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -363,6 +363,155 @@ static int live_unlite_preempt(void *arg) > return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); > } > > +static int live_unlite_ring(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + struct igt_spinner spin; > + enum intel_engine_id id; > + int err = 0; > + > + /* > + * Setup a preemption event that will cause almost the entire ring > + * to be unwound, potentially fooling our intel_ring_direction() > + * into emitting a forward lite-restore instead of the rollback. > + */ > + > + if (igt_spinner_init(&spin, gt)) > + return -ENOMEM; > + > + for_each_engine(engine, gt, id) { > + struct intel_context *ce[2] = {}; > + struct i915_request *rq; > + struct igt_live_test t; > + int n; > + > + if (!intel_engine_has_preemption(engine)) > + continue; > + > + if (!intel_engine_can_store_dword(engine)) > + continue; > + > + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { > + err = -EIO; > + break; > + } > + engine_heartbeat_disable(engine); > + > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + struct intel_context *tmp; > + > + tmp = intel_context_create(engine); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + goto err_ce; > + } > + > + err = intel_context_pin(tmp); > + if (err) { > + intel_context_put(tmp); > + goto err_ce; > + } > + > + memset32(tmp->ring->vaddr, > + 0xdeadbeef, /* trigger a hang if executed */ > + tmp->ring->vma->size / sizeof(u32)); > + > + ce[n] = tmp; > + } > + > + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + i915_request_get(rq); > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > + i915_request_add(rq); > + > + if (!igt_wait_for_spinner(&spin, rq)) { > + intel_gt_set_wedged(gt); > + i915_request_put(rq); > + err = -ETIME; > + goto err_ce; > + } > + > + /* Fill the ring, until we will cause a wrap */ > + n = 0; > + while (intel_ring_direction(ce[0]->ring, > + rq->wa_tail, > + ce[0]->ring->tail) <= 0) { > + struct i915_request *tmp; I got that you tested it with revert of incremental, but can we make 2 versions of this test so that the half ring size is honoured and then another where we do few requests past the half? Just would like to see the hardware get confused according to our assertions. -Mika > + > + tmp = intel_context_create_request(ce[0]); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + i915_request_put(rq); > + goto err_ce; > + } > + > + i915_request_add(tmp); > + intel_engine_flush_submission(engine); > + n++; > + } > + intel_engine_flush_submission(engine); > + pr_debug("%s: Filled ring with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", > + engine->name, n, > + ce[0]->ring->size, > + ce[0]->ring->tail, > + ce[0]->ring->emit, > + rq->tail); > + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, > + rq->tail, > + ce[0]->ring->tail) <= 0); > + i915_request_put(rq); > + > + /* Create a second request to preempt the first ring */ > + rq = intel_context_create_request(ce[1]); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > + i915_request_get(rq); > + i915_request_add(rq); > + > + err = wait_for_submit(engine, rq, HZ / 2); > + i915_request_put(rq); > + if (err) { > + pr_err("%s: preemption request was not submited\n", > + engine->name); > + err = -ETIME; > + } > + > + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", > + engine->name, > + ce[0]->ring->tail, ce[0]->ring->emit, > + ce[1]->ring->tail, ce[1]->ring->emit); > + > +err_ce: > + intel_engine_flush_submission(engine); > + igt_spinner_end(&spin); > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + if (IS_ERR_OR_NULL(ce[n])) > + break; > + > + intel_context_unpin(ce[n]); > + intel_context_put(ce[n]); > + } > + engine_heartbeat_enable(engine); > + if (igt_live_test_end(&t)) > + err = -EIO; > + if (err) > + break; > + } > + > + igt_spinner_fini(&spin); > + return err; > +} > + > static int live_pin_rewind(void *arg) > { > struct intel_gt *gt = arg; > @@ -4374,6 +4523,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) > SUBTEST(live_sanitycheck), > SUBTEST(live_unlite_switch), > SUBTEST(live_unlite_preempt), > + SUBTEST(live_unlite_ring), > SUBTEST(live_pin_rewind), > SUBTEST(live_hold_reset), > SUBTEST(live_error_interrupt), > -- > 2.20.1 From mika.kuoppala at linux.intel.com Tue Jun 16 08:56:58 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 11:56:58 +0300 Subject: [Intel-gfx] [PATCH 2/9] drm/i915/selftests: Use friendly request names for live_timeslice_rewind In-Reply-To: <20200616084141.3722-2-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> <20200616084141.3722-2-chris@chris-wilson.co.uk> Message-ID: <877dw7s811.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rather than mixing [012] and (A1, A2, B2) for the request indices, use > the enums throughout. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Yes, much more friendlier. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index 3d088116a055..72d52c9c042f 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -1176,18 +1176,18 @@ static int live_timeslice_rewind(void *arg) > goto err; > } > > - rq[0] = create_rewinder(ce, NULL, slot, X); > - if (IS_ERR(rq[0])) { > + rq[A1] = create_rewinder(ce, NULL, slot, X); > + if (IS_ERR(rq[A1])) { > intel_context_put(ce); > goto err; > } > > - rq[1] = create_rewinder(ce, NULL, slot, Y); > + rq[A2] = create_rewinder(ce, NULL, slot, Y); > intel_context_put(ce); > - if (IS_ERR(rq[1])) > + if (IS_ERR(rq[A2])) > goto err; > > - err = wait_for_submit(engine, rq[1], HZ / 2); > + err = wait_for_submit(engine, rq[A2], HZ / 2); > if (err) { > pr_err("%s: failed to submit first context\n", > engine->name); > @@ -1200,12 +1200,12 @@ static int live_timeslice_rewind(void *arg) > goto err; > } > > - rq[2] = create_rewinder(ce, rq[0], slot, Z); > + rq[B1] = create_rewinder(ce, rq[A1], slot, Z); > intel_context_put(ce); > if (IS_ERR(rq[2])) > goto err; > > - err = wait_for_submit(engine, rq[2], HZ / 2); > + err = wait_for_submit(engine, rq[B1], HZ / 2); > if (err) { > pr_err("%s: failed to submit second context\n", > engine->name); > @@ -1213,6 +1213,7 @@ static int live_timeslice_rewind(void *arg) > } > > /* ELSP[] = { { A:rq1, A:rq2 }, { B:rq1 } } */ > + ENGINE_TRACE(engine, "forcing tasklet for rewind\n"); > if (i915_request_is_active(rq[A2])) { /* semaphore yielded! */ > /* Wait for the timeslice to kick in */ > del_timer(&engine->execlists.timer); > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Tue Jun 16 09:03:19 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 12:03:19 +0300 Subject: [Intel-gfx] [PATCH 3/9] drm/i915/selftests: Enable selftesting of busy-stats In-Reply-To: <20200616084141.3722-3-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> <20200616084141.3722-3-chris@chris-wilson.co.uk> Message-ID: <874krbs7qg.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > A couple of very simple tests to ensure that the basic properties of > per-engine busyness accounting [0% and 100% busy] are faithful. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 94 ++++++++++++++++++++ > drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ > 2 files changed, 99 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > index cbf6b0735272..fb0fd8a7db9a 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > @@ -7,6 +7,99 @@ > #include "i915_selftest.h" > #include "selftest_engine.h" > #include "selftests/igt_atomic.h" > +#include "selftests/igt_flush_test.h" > +#include "selftests/igt_spinner.h" > + > +static int live_engine_busy_stats(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + enum intel_engine_id id; > + struct igt_spinner spin; > + int err = 0; > + > + /* > + * Check that if an engine supports busy-stats, they tell the truth. > + */ > + > + if (igt_spinner_init(&spin, gt)) > + return -ENOMEM; > + > + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); > + for_each_engine(engine, gt, id) { > + struct i915_request *rq; > + ktime_t de; > + u64 dt; > + > + if (!intel_engine_supports_stats(engine)) > + continue; > + > + if (!intel_engine_can_store_dword(engine)) > + continue; > + > + if (intel_gt_pm_wait_for_idle(gt)) { > + err = -EBUSY; > + break; > + } > + > + preempt_disable(); > + dt = ktime_to_ns(ktime_get()); > + de = intel_engine_get_busy_time(engine); > + udelay(100); > + de = ktime_sub(intel_engine_get_busy_time(engine), de); > + dt = ktime_to_ns(ktime_get()) - dt; > + preempt_enable(); > + if (de > 10) { 10 is from stetson? Well I would say it is strict enough. The signed de just makes me nervous, so de < 0 too? > + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", > + engine->name, > + de, (int)div64_u64(100 * de, dt), dt); > + err = -EINVAL; > + break; > + } > + > + /* 100% busy */ > + rq = igt_spinner_create_request(&spin, > + engine->kernel_context, > + MI_NOOP); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + break; > + } > + i915_request_add(rq); > + > + if (!igt_wait_for_spinner(&spin, rq)) { > + intel_gt_set_wedged(engine->gt); > + err = -ETIME; > + break; > + } > + > + preempt_disable(); > + dt = ktime_to_ns(ktime_get()); > + de = intel_engine_get_busy_time(engine); > + udelay(100); > + de = ktime_sub(intel_engine_get_busy_time(engine), de); > + dt = ktime_to_ns(ktime_get()) - dt; > + preempt_enable(); > + if (100 * de < 95 * dt || 95 * de > 100 * dt) { I do remember in igt side we have nice helper for these. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > + pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", > + engine->name, > + de, (int)div64_u64(100 * de, dt), dt); > + err = -EINVAL; > + break; > + } > + > + igt_spinner_end(&spin); > + if (igt_flush_test(gt->i915)) { > + err = -EIO; > + break; > + } > + } > + > + igt_spinner_fini(&spin); > + if (igt_flush_test(gt->i915)) > + err = -EIO; > + return err; > +} > > static int live_engine_pm(void *arg) > { > @@ -77,6 +170,7 @@ static int live_engine_pm(void *arg) > int live_engine_pm_selftests(struct intel_gt *gt) > { > static const struct i915_subtest tests[] = { > + SUBTEST(live_engine_busy_stats), > SUBTEST(live_engine_pm), > }; > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c > index 5049c3dd08a6..5e364fb31aea 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_rps.c > +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c > @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) > if (igt_spinner_init(&spin, gt)) > return -ENOMEM; > > + if (intel_rps_has_interrupts(rps)) > + pr_info("RPS has interrupt support\n"); > + if (intel_rps_uses_timer(rps)) > + pr_info("RPS has timer support\n"); > + > for_each_engine(engine, gt, id) { > struct i915_request *rq; > struct { > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From thomas_os at shipmail.org Tue Jun 16 09:07:28 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 16 Jun 2020 11:07:28 +0200 Subject: [Intel-gfx] [PATCH 26/28] drm/i915: Fair low-latency scheduling In-Reply-To: <20200607222108.14401-26-chris@chris-wilson.co.uk> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-26-chris@chris-wilson.co.uk> Message-ID: <5a7ebfbc-665b-eff6-d969-7d27b568f161@shipmail.org> Hi, Chris, Some comments and questions: On 6/8/20 12:21 AM, Chris Wilson wrote: > The first "scheduler" was a topographical sorting of requests into > priority order. The execution order was deterministic, the earliest > submitted, highest priority request would be executed first. Priority > inherited ensured that inversions were kept at bay, and allowed us to > dynamically boost priorities (e.g. for interactive pageflips). > > The minimalistic timeslicing scheme was an attempt to introduce fairness > between long running requests, by evicting the active request at the end > of a timeslice and moving it to the back of its priority queue (while > ensuring that dependencies were kept in order). For short running > requests from many clients of equal priority, the scheme is still very > much FIFO submission ordering, and as unfair as before. > > To impose fairness, we need an external metric that ensures that clients > are interpersed, we don't execute one long chain from client A before > executing any of client B. This could be imposed by the clients by using > a fences based on an external clock, that is they only submit work for a > "frame" at frame-interval, instead of submitting as much work as they > are able to. The standard SwapBuffers approach is akin to double > bufferring, where as one frame is being executed, the next is being > submitted, such that there is always a maximum of two frames per client > in the pipeline. Even this scheme exhibits unfairness under load as a > single client will execute two frames back to back before the next, and > with enough clients, deadlines will be missed. > > The idea introduced by BFS/MuQSS is that fairness is introduced by > metering with an external clock. Every request, when it becomes ready to > execute is assigned a virtual deadline, and execution order is then > determined by earliest deadline. Priority is used as a hint, rather than > strict ordering, where high priority requests have earlier deadlines, > but not necessarily earlier than outstanding work. Thus work is executed > in order of 'readiness', with timeslicing to demote long running work. > > The Achille's heel of this scheduler is its strong preference for > low-latency and favouring of new queues. Whereas it was easy to dominate > the old scheduler by flooding it with many requests over a short period > of time, the new scheduler can be dominated by a 'synchronous' client > that waits for each of its requests to complete before submitting the > next. As such a client has no history, it is always considered > ready-to-run and receives an earlier deadline than the long running > requests. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- > .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 1 + > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +- > drivers/gpu/drm/i915/gt/intel_engine_types.h | 24 -- > drivers/gpu/drm/i915/gt/intel_lrc.c | 328 +++++++----------- > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 5 +- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 43 ++- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- > drivers/gpu/drm/i915/i915_priolist_types.h | 7 +- > drivers/gpu/drm/i915/i915_request.h | 4 +- > drivers/gpu/drm/i915/i915_scheduler.c | 322 ++++++++++++----- > drivers/gpu/drm/i915/i915_scheduler.h | 22 +- > drivers/gpu/drm/i915/i915_scheduler_types.h | 17 + > .../drm/i915/selftests/i915_mock_selftests.h | 1 + > drivers/gpu/drm/i915/selftests/i915_request.c | 1 + > .../gpu/drm/i915/selftests/i915_scheduler.c | 49 +++ > 16 files changed, 484 insertions(+), 362 deletions(-) > create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c Do we have timings to back this change up? Would it make sense to have a configurable scheduler choice? > @@ -1096,22 +1099,30 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) > { > struct i915_request *rq, *rn, *active = NULL; > struct list_head *uninitialized_var(pl); > - int prio = I915_PRIORITY_INVALID; > + u64 deadline = I915_DEADLINE_NEVER; > > lockdep_assert_held(&engine->active.lock); > > list_for_each_entry_safe_reverse(rq, rn, > &engine->active.requests, > sched.link) { > - if (i915_request_completed(rq)) > + if (i915_request_completed(rq)) { > + list_del_init(&rq->sched.link); > continue; /* XXX */ > + } Is this an unrelated change? If so separate patch? ... > @@ -2162,14 +2140,13 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > __unwind_incomplete_requests(engine); > > last = NULL; > - } else if (need_timeslice(engine, last, ve) && > - timeslice_expired(execlists, last)) { > + } else if (timeslice_expired(engine, last)) { > ENGINE_TRACE(engine, > - "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n", > - last->fence.context, > - last->fence.seqno, > - last->sched.attr.priority, > - execlists->queue_priority_hint, > + "expired:%s last=%llx:%llu, deadline=%llu, now=%llu, yield?=%s\n", > + yesno(timer_expired(&execlists->timer)), > + last->fence.context, last->fence.seqno, > + rq_deadline(last), > + i915_sched_to_ticks(ktime_get()), > yesno(timeslice_yield(execlists, last))); There are multiple introductions of ktime_get() in the patch. Perhaps use monotonic clock source like ktime_get_raw()? Also immediately convert to ns. ... > @@ -2837,10 +2788,7 @@ static void __execlists_unhold(struct i915_request *rq) > GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); > > i915_request_clear_hold(rq); > - list_move_tail(&rq->sched.link, > - i915_sched_lookup_priolist(rq->engine, > - rq_prio(rq))); > - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); > + submit |= intel_engine_queue_request(rq->engine, rq); As new to this codebase, I immediately wonder whether that bitwise or is intentional and whether you got the short-circuiting right. It looks correct to me. ... > diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h > index 118ab6650d1f..23594e712292 100644 > --- a/drivers/gpu/drm/i915/i915_request.h > +++ b/drivers/gpu/drm/i915/i915_request.h > @@ -561,7 +561,7 @@ static inline void i915_request_clear_hold(struct i915_request *rq) > } > > static inline struct intel_timeline * > -i915_request_timeline(struct i915_request *rq) > +i915_request_timeline(const struct i915_request *rq) > { > /* Valid only while the request is being constructed (or retired). */ > return rcu_dereference_protected(rq->timeline, > @@ -576,7 +576,7 @@ i915_request_gem_context(struct i915_request *rq) > } > > static inline struct intel_timeline * > -i915_request_active_timeline(struct i915_request *rq) > +i915_request_active_timeline(const struct i915_request *rq) Are these unrelated? Separate patch? > { > /* > * When in use during submission, we are protected by a guarantee that > diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c > index 4c189b81cc62..30bcb6f9d99f 100644 > --- a/drivers/gpu/drm/i915/i915_scheduler.c > +++ b/drivers/gpu/drm/i915/i915_scheduler.c > @@ -20,6 +20,11 @@ static struct i915_global_scheduler { > static DEFINE_SPINLOCK(ipi_lock); > static LIST_HEAD(ipi_list); > > +static inline u64 rq_deadline(const struct i915_request *rq) > +{ > + return READ_ONCE(rq->sched.deadline); > +} > + Does this need a release barrier paired with an acquire barrier in __i915_request_set_deadline below? > + > +static bool __i915_request_set_deadline(struct i915_request *rq, u64 deadline) > +{ > + struct intel_engine_cs *engine = rq->engine; > + struct i915_request *rn; > + struct list_head *plist; > + LIST_HEAD(dfs); > + > + lockdep_assert_held(&engine->active.lock); > + list_add(&rq->sched.dfs, &dfs); > + > + list_for_each_entry(rq, &dfs, sched.dfs) { > + struct i915_dependency *p; > + > + GEM_BUG_ON(rq->engine != engine); > + > + for_each_signaler(p, rq) { > + struct i915_request *s = > + container_of(p->signaler, typeof(*s), sched); > + > + GEM_BUG_ON(s == rq); > + > + if (rq_deadline(s) <= deadline) > + continue; > + > + if (i915_request_completed(s)) > + continue; > + > + if (s->engine != rq->engine) { > + spin_lock(&ipi_lock); > + if (deadline < p->ipi_deadline) { > + p->ipi_deadline = deadline; > + list_move(&p->ipi_link, &ipi_list); > + irq_work_queue(&ipi_work); > + } > + spin_unlock(&ipi_lock); > + continue; > + } > + > + list_move_tail(&s->sched.dfs, &dfs); > + } > + } > + > + plist = i915_sched_lookup_priolist(engine, deadline); > + > + /* Fifo and depth-first replacement ensure our deps execute first */ > + list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) { > + GEM_BUG_ON(rq->engine != engine); > + GEM_BUG_ON(deadline > rq_deadline(rq)); > + > + INIT_LIST_HEAD(&rq->sched.dfs); > + WRITE_ONCE(rq->sched.deadline, deadline); An smp barrier needed? ... > +static u64 prio_slice(int prio) > { > - const struct i915_request *inflight; > + u64 slice; > + int sf; > > /* > - * We only need to kick the tasklet once for the high priority > - * new context we add into the queue. > + * With a 1ms scheduling quantum: > + * > + * MAX USER: ~32us deadline > + * 0: ~16ms deadline > + * MIN_USER: 1000ms deadline > */ > - if (prio <= engine->execlists.queue_priority_hint) > - return; > > - rcu_read_lock(); > + if (prio >= __I915_PRIORITY_KERNEL__) > + return INT_MAX - prio; > > - /* Nothing currently active? We're overdue for a submission! */ > - inflight = execlists_active(&engine->execlists); > - if (!inflight) > - goto unlock; > + slice = __I915_PRIORITY_KERNEL__ - prio; > + if (prio >= 0) > + sf = 20 - 6; > + else > + sf = 20 - 1; > + > + return slice << sf; > +} > + Is this the same deadline calculation as used in the BFS? Could you perhaps add a pointer to some documentation? /Thomas From chris at chris-wilson.co.uk Tue Jun 16 09:09:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 10:09:15 +0100 Subject: [Intel-gfx] [PATCH 1/9] drm/i915/selftests: Exercise far preemption rollbacks In-Reply-To: <87a713s847.fsf@gaia.fi.intel.com> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> <87a713s847.fsf@gaia.fi.intel.com> Message-ID: <159229855527.18308.214917781408344749@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-16 09:55:04) > > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > Not too long ago, we realised we had issues with a rolling back a > > context so far for a preemption request we considered the resubmit not > > to be a rollback but a forward roll. This means we would issue a lite > > restore instead of forcing a full restore, continuing execution of the > > old requests rather than causing a preemption. Add a selftest to > > exercise such a far rollback, such that if we were to skip the full > > restore, we would execute invalid instructions in the ring and hang. > > > > Note that while I was able to confirm that this causes us to do a > > lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: > > Incrementally check for rewinding") disabled), it did not trick the HW > > into rolling past the old RING_TAIL. Myybe on other HW. > > > > References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > > --- > > drivers/gpu/drm/i915/gt/selftest_lrc.c | 150 +++++++++++++++++++++++++ > > 1 file changed, 150 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > > index 91543494f595..3d088116a055 100644 > > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > > @@ -363,6 +363,155 @@ static int live_unlite_preempt(void *arg) > > return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); > > } > > > > +static int live_unlite_ring(void *arg) > > +{ > > + struct intel_gt *gt = arg; > > + struct intel_engine_cs *engine; > > + struct igt_spinner spin; > > + enum intel_engine_id id; > > + int err = 0; > > + > > + /* > > + * Setup a preemption event that will cause almost the entire ring > > + * to be unwound, potentially fooling our intel_ring_direction() > > + * into emitting a forward lite-restore instead of the rollback. > > + */ > > + > > + if (igt_spinner_init(&spin, gt)) > > + return -ENOMEM; > > + > > + for_each_engine(engine, gt, id) { > > + struct intel_context *ce[2] = {}; > > + struct i915_request *rq; > > + struct igt_live_test t; > > + int n; > > + > > + if (!intel_engine_has_preemption(engine)) > > + continue; > > + > > + if (!intel_engine_can_store_dword(engine)) > > + continue; > > + > > + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { > > + err = -EIO; > > + break; > > + } > > + engine_heartbeat_disable(engine); > > + > > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > > + struct intel_context *tmp; > > + > > + tmp = intel_context_create(engine); > > + if (IS_ERR(tmp)) { > > + err = PTR_ERR(tmp); > > + goto err_ce; > > + } > > + > > + err = intel_context_pin(tmp); > > + if (err) { > > + intel_context_put(tmp); > > + goto err_ce; > > + } > > + > > + memset32(tmp->ring->vaddr, > > + 0xdeadbeef, /* trigger a hang if executed */ > > + tmp->ring->vma->size / sizeof(u32)); > > + > > + ce[n] = tmp; > > + } > > + > > + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); > > + if (IS_ERR(rq)) { > > + err = PTR_ERR(rq); > > + goto err_ce; > > + } > > + > > + i915_request_get(rq); > > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > > + i915_request_add(rq); > > + > > + if (!igt_wait_for_spinner(&spin, rq)) { > > + intel_gt_set_wedged(gt); > > + i915_request_put(rq); > > + err = -ETIME; > > + goto err_ce; > > + } > > + > > + /* Fill the ring, until we will cause a wrap */ > > + n = 0; > > + while (intel_ring_direction(ce[0]->ring, > > + rq->wa_tail, > > + ce[0]->ring->tail) <= 0) { > > + struct i915_request *tmp; > > I got that you tested it with revert of incremental, but > > can we make 2 versions of this test so that the half ring size > is honoured and then another where we do few requests past the half? We have examples of normal preemption. This chooses to focus on the impact of intel_ring_direction(). > Just would like to see the hardware get confused according > to our assertions. I haven't tricked the HW into doing anything unexpected. I've tried switching the spinner out for a semaphore in the ring (in case that would keep the ring registers primed) and I've tried releasing the spinner at the same time as trying to submit the preemption (though that will be incredibly timing dependent) with the aim of having it process the request tail at the same time as the ELSP. -Chris From joonas.lahtinen at linux.intel.com Tue Jun 16 09:22:36 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Tue, 16 Jun 2020 12:22:36 +0300 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-intel-fixes tree In-Reply-To: <20200616093912.4dffcc71@canb.auug.org.au> References: <20200616093912.4dffcc71@canb.auug.org.au> Message-ID: <159229935689.7727.9085291204498542933@jlahtine-desk.ger.corp.intel.com> Quoting Stephen Rothwell (2020-06-16 02:39:12) > Hi all, > > After merging the drm-intel-fixes tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > In file included from drivers/gpu/drm/i915/gt/intel_lrc.c:5972: > drivers/gpu/drm/i915/gt/selftest_lrc.c: In function 'live_timeslice_nopreempt': > drivers/gpu/drm/i915/gt/selftest_lrc.c:1333:3: error: too few arguments to function 'engine_heartbeat_disable' > 1333 | engine_heartbeat_disable(engine); > | ^~~~~~~~~~~~~~~~~~~~~~~~ > drivers/gpu/drm/i915/gt/selftest_lrc.c:54:13: note: declared here > 54 | static void engine_heartbeat_disable(struct intel_engine_cs *engine, > | ^~~~~~~~~~~~~~~~~~~~~~~~ > drivers/gpu/drm/i915/gt/selftest_lrc.c:1402:3: error: too few arguments to function 'engine_heartbeat_enable' > 1402 | engine_heartbeat_enable(engine); > | ^~~~~~~~~~~~~~~~~~~~~~~ > drivers/gpu/drm/i915/gt/selftest_lrc.c:64:13: note: declared here > 64 | static void engine_heartbeat_enable(struct intel_engine_cs *engine, > | ^~~~~~~~~~~~~~~~~~~~~~~ > > Caused by commit > > 04dc41776145 ("drm/i915/gt: Prevent timeslicing into unpreemptable requests") > > I have reverted that commit for today. Thanks for reporting. I had my drm-intel-fixes build tree configured without selftests. I've now corrected that and added a missing dependency patch. Regards, Joonas > > -- > Cheers, > Stephen Rothwell From chris at chris-wilson.co.uk Tue Jun 16 09:28:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 10:28:33 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Check preemption rollback of different ring queue depths Message-ID: <20200616092833.18498-1-chris@chris-wilson.co.uk> Like live_unlite_ring, but instead of simply looking at the impact of intel_ring_direction(), check that preemption more generally works with different depths of queued requests in the ring. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 163 +++++++++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 3d088116a055..530718797848 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2756,6 +2756,168 @@ static int create_gang(struct intel_engine_cs *engine, return err; } +static int __live_preempt_ring(struct intel_engine_cs *engine, + struct igt_spinner *spin, + int sz) +{ + struct intel_context *ce[2] = {}; + struct i915_request *rq; + struct igt_live_test t; + int err = 0; + int n; + + if (igt_live_test_begin(&t, engine->i915, __func__, engine->name)) + return -EIO; + + for (n = 0; n < ARRAY_SIZE(ce); n++) { + struct intel_context *tmp; + + tmp = intel_context_create(engine); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + goto err_ce; + } + + err = intel_context_pin(tmp); + if (err) { + intel_context_put(tmp); + goto err_ce; + } + + memset32(tmp->ring->vaddr, + 0xdeadbeef, /* trigger a hang if executed */ + tmp->ring->vma->size / sizeof(u32)); + + ce[n] = tmp; + } + + rq = igt_spinner_create_request(spin, ce[0], MI_ARB_CHECK); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + i915_request_get(rq); + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_add(rq); + + if (!igt_wait_for_spinner(spin, rq)) { + intel_gt_set_wedged(engine->gt); + i915_request_put(rq); + err = -ETIME; + goto err_ce; + } + + /* Fill the ring, until we will cause a wrap */ + n = 0; + while (ce[0]->ring->tail - rq->wa_tail <= sz) { + struct i915_request *tmp; + + tmp = intel_context_create_request(ce[0]); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + i915_request_put(rq); + goto err_ce; + } + + i915_request_add(tmp); + intel_engine_flush_submission(engine); + n++; + } + intel_engine_flush_submission(engine); + pr_debug("%s: Filled %d with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", + engine->name, sz, n, + ce[0]->ring->size, + ce[0]->ring->tail, + ce[0]->ring->emit, + rq->tail); + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, + rq->tail, + ce[0]->ring->tail) <= 0); + i915_request_put(rq); + + /* Create a second request to preempt the first ring */ + rq = intel_context_create_request(ce[1]); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_get(rq); + i915_request_add(rq); + + err = wait_for_submit(engine, rq, HZ / 2); + i915_request_put(rq); + if (err) { + pr_err("%s: preemption request was not submited\n", + engine->name); + err = -ETIME; + } + + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", + engine->name, + ce[0]->ring->tail, ce[0]->ring->emit, + ce[1]->ring->tail, ce[1]->ring->emit); + +err_ce: + intel_engine_flush_submission(engine); + igt_spinner_end(spin); + for (n = 0; n < ARRAY_SIZE(ce); n++) { + if (IS_ERR_OR_NULL(ce[n])) + break; + + intel_context_unpin(ce[n]); + intel_context_put(ce[n]); + } + if (igt_live_test_end(&t)) + err = -EIO; + return err; +} + +static int live_preempt_ring(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + struct igt_spinner spin; + enum intel_engine_id id; + int err = 0; + + /* + * Check that we rollback large chunks of a ring in order to do a + * preemption event. Similar to live_unlite_ring, but looking at + * ring size rather than the impact of intel_ring_direction(). + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + for_each_engine(engine, gt, id) { + int n; + + if (!intel_engine_has_preemption(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + engine_heartbeat_disable(engine); + + for (n = 0; n <= 3; n++) { + err = __live_preempt_ring(engine, &spin, n * SZ_4K / 4); + if (err) + break; + } + + engine_heartbeat_enable(engine); + if (err) + break; + } + + igt_spinner_fini(&spin); + return err; +} + static int live_preempt_gang(void *arg) { struct intel_gt *gt = arg; @@ -4538,6 +4700,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_preempt_cancel), SUBTEST(live_suppress_self_preempt), SUBTEST(live_chain_preempt), + SUBTEST(live_preempt_ring), SUBTEST(live_preempt_gang), SUBTEST(live_preempt_timeout), SUBTEST(live_preempt_user), -- 2.20.1 From mika.kuoppala at linux.intel.com Tue Jun 16 09:35:00 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 12:35:00 +0300 Subject: [Intel-gfx] [PATCH 4/9] drm/i915/execlists: Replace direct submit with direct call to tasklet In-Reply-To: <20200616084141.3722-4-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> <20200616084141.3722-4-chris@chris-wilson.co.uk> Message-ID: <871rmf9wvv.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Rather than having special case code for opportunistically calling > process_csb() and performing a direct submit while holding the engine > spinlock for submitting the request, simply call the tasklet directly. > This allows us to retain the direct submission path, including the CS > draining to allow fast/immediate submissions, without requiring any > duplicated code paths. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 1 + > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +++---- > drivers/gpu/drm/i915/gt/intel_lrc.c | 78 +++++++------------ > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + > drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- > 5 files changed, 46 insertions(+), 67 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 791897f8d847..c77b3c0d2b3b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -210,6 +210,7 @@ int intel_engine_resume(struct intel_engine_cs *engine); > > int intel_ring_submission_setup(struct intel_engine_cs *engine); > > +void __intel_engine_stop_cs(struct intel_engine_cs *engine); > int intel_engine_stop_cs(struct intel_engine_cs *engine); > void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 045179c65c44..fbb8ac659b82 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -903,33 +903,34 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) > return READ_ONCE(engine->props.stop_timeout_ms); > } > > -int intel_engine_stop_cs(struct intel_engine_cs *engine) > +void __intel_engine_stop_cs(struct intel_engine_cs *engine) > { > struct intel_uncore *uncore = engine->uncore; > - const u32 base = engine->mmio_base; > - const i915_reg_t mode = RING_MI_MODE(base); > - int err; > + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); > > + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); > + intel_uncore_posting_read_fw(uncore, mode); > +} > + > +int intel_engine_stop_cs(struct intel_engine_cs *engine) > +{ > if (INTEL_GEN(engine->i915) < 3) > return -ENODEV; > > ENGINE_TRACE(engine, "\n"); > > - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); > + __intel_engine_stop_cs(engine); > > - err = 0; > - if (__intel_wait_for_register_fw(uncore, > - mode, MODE_IDLE, MODE_IDLE, > + if (__intel_wait_for_register_fw(engine->uncore, > + RING_MI_MODE(engine->mmio_base), > + MODE_IDLE, MODE_IDLE, > 1000, stop_timeout(engine), > NULL)) { > ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); > - err = -ETIMEDOUT; > + return -ETIMEDOUT; > } > > - /* A final mmio read to let GPU writes be hopefully flushed to memory */ > - intel_uncore_posting_read_fw(uncore, mode); > - > - return err; > + return 0; > } > > void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index e866b8d721ed..40c5085765da 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -2703,16 +2703,6 @@ static void process_csb(struct intel_engine_cs *engine) > invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); > } > > -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) > -{ > - lockdep_assert_held(&engine->active.lock); > - if (!READ_ONCE(engine->execlists.pending[0])) { > - rcu_read_lock(); /* protect peeking at execlists->active */ > - execlists_dequeue(engine); > - rcu_read_unlock(); > - } > -} > - > static void __execlists_hold(struct i915_request *rq) > { > LIST_HEAD(list); > @@ -3102,7 +3092,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) > if (!timer_expired(t)) > return false; > > - return READ_ONCE(engine->execlists.pending[0]); > + return engine->execlists.pending[0]; Sometimes I yearn for intel_execlists_request_pending() but it would be wonky and the port0 is quite core to the lrc... Overall this patch makes things more straightfoward. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > } > > /* > @@ -3112,7 +3102,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) > static void execlists_submission_tasklet(unsigned long data) > { > struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; > - bool timeout = preempt_timeout(engine); > > process_csb(engine); > > @@ -3122,16 +3111,17 @@ static void execlists_submission_tasklet(unsigned long data) > execlists_reset(engine, "CS error"); > } > > - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { > + if (unlikely(preempt_timeout(engine))) > + execlists_reset(engine, "preemption time out"); > + > + if (!engine->execlists.pending[0]) { > unsigned long flags; > > + rcu_read_lock(); /* protect peeking at execlists->active */ > spin_lock_irqsave(&engine->active.lock, flags); > - __execlists_submission_tasklet(engine); > + execlists_dequeue(engine); > spin_unlock_irqrestore(&engine->active.lock, flags); > - > - /* Recheck after serialising with direct-submission */ > - if (unlikely(timeout && preempt_timeout(engine))) > - execlists_reset(engine, "preemption time out"); > + rcu_read_unlock(); > } > } > > @@ -3163,26 +3153,16 @@ static void queue_request(struct intel_engine_cs *engine, > set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); > } > > -static void __submit_queue_imm(struct intel_engine_cs *engine) > -{ > - struct intel_engine_execlists * const execlists = &engine->execlists; > - > - if (reset_in_progress(execlists)) > - return; /* defer until we restart the engine following reset */ > - > - __execlists_submission_tasklet(engine); > -} > - > -static void submit_queue(struct intel_engine_cs *engine, > +static bool submit_queue(struct intel_engine_cs *engine, > const struct i915_request *rq) > { > struct intel_engine_execlists *execlists = &engine->execlists; > > if (rq_prio(rq) <= execlists->queue_priority_hint) > - return; > + return false; > > execlists->queue_priority_hint = rq_prio(rq); > - __submit_queue_imm(engine); > + return true; > } > > static bool ancestor_on_hold(const struct intel_engine_cs *engine, > @@ -3196,20 +3176,22 @@ static void flush_csb(struct intel_engine_cs *engine) > { > struct intel_engine_execlists *el = &engine->execlists; > > - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { > - if (!reset_in_progress(el)) > - process_csb(engine); > - tasklet_unlock(&el->tasklet); > + if (!tasklet_trylock(&el->tasklet)) { > + tasklet_hi_schedule(&el->tasklet); > + return; > } > + > + if (!reset_in_progress(el)) > + execlists_submission_tasklet((unsigned long)engine); > + > + tasklet_unlock(&el->tasklet); > } > > static void execlists_submit_request(struct i915_request *request) > { > struct intel_engine_cs *engine = request->engine; > unsigned long flags; > - > - /* Hopefully we clear execlists->pending[] to let us through */ > - flush_csb(engine); > + bool submit = false; > > /* Will be called from irq-context when using foreign fences. */ > spin_lock_irqsave(&engine->active.lock, flags); > @@ -3224,10 +3206,13 @@ static void execlists_submit_request(struct i915_request *request) > GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); > GEM_BUG_ON(list_empty(&request->sched.link)); > > - submit_queue(engine, request); > + submit = submit_queue(engine, request); > } > > spin_unlock_irqrestore(&engine->active.lock, flags); > + > + if (submit) > + flush_csb(engine); > } > > static void __execlists_context_fini(struct intel_context *ce) > @@ -4113,7 +4098,6 @@ static int execlists_resume(struct intel_engine_cs *engine) > static void execlists_reset_prepare(struct intel_engine_cs *engine) > { > struct intel_engine_execlists * const execlists = &engine->execlists; > - unsigned long flags; > > ENGINE_TRACE(engine, "depth<-%d\n", > atomic_read(&execlists->tasklet.count)); > @@ -4130,10 +4114,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) > __tasklet_disable_sync_once(&execlists->tasklet); > GEM_BUG_ON(!reset_in_progress(execlists)); > > - /* And flush any current direct submission. */ > - spin_lock_irqsave(&engine->active.lock, flags); > - spin_unlock_irqrestore(&engine->active.lock, flags); > - > /* > * We stop engines, otherwise we might get failed reset and a > * dead gpu (on elk). Also as modern gpu as kbl can suffer > @@ -4147,7 +4127,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) > * FIXME: Wa for more modern gens needs to be validated > */ > ring_set_paused(engine, 1); > - intel_engine_stop_cs(engine); > + __intel_engine_stop_cs(engine); > > engine->execlists.reset_ccid = active_ccid(engine); > } > @@ -4377,12 +4357,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) > * to sleep before we restart and reload a context. > */ > GEM_BUG_ON(!reset_in_progress(execlists)); > - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) > - execlists->tasklet.func(execlists->tasklet.data); > + GEM_BUG_ON(engine->execlists.pending[0]); > > + /* And kick in case we missed a new request submission. */ > if (__tasklet_enable(&execlists->tasklet)) > - /* And kick in case we missed a new request submission. */ > - tasklet_hi_schedule(&execlists->tasklet); > + flush_csb(engine); > + > ENGINE_TRACE(engine, "depth->%d\n", > atomic_read(&execlists->tasklet.count)); > } > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > index 7461936d549d..355ee8562bc1 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c > @@ -1597,6 +1597,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, > > p->critical_section_end(); > tasklet_enable(t); > + tasklet_hi_schedule(t); > > if (err) > pr_err("i915_reset_engine(%s:%s) failed under %s\n", > diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c > index 92c628f18c60..4f1b82c7eeaf 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_request.c > +++ b/drivers/gpu/drm/i915/selftests/i915_request.c > @@ -1925,9 +1925,7 @@ static int measure_inter_request(struct intel_context *ce) > intel_ring_advance(rq, cs); > i915_request_add(rq); > } > - local_bh_disable(); > i915_sw_fence_commit(submit); > - local_bh_enable(); > intel_engine_flush_submission(ce->engine); > heap_fence_put(submit); > > @@ -2213,11 +2211,9 @@ static int measure_completion(struct intel_context *ce) > intel_ring_advance(rq, cs); > > dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); > - > - local_bh_disable(); > i915_request_add(rq); > - local_bh_enable(); > > + intel_engine_flush_submission(ce->engine); > if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { > err = -EIO; > goto err; > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From martin.peres at intel.com Tue Jun 16 09:37:40 2020 From: martin.peres at intel.com (Peres, Martin) Date: Tue, 16 Jun 2020 09:37:40 +0000 Subject: [Intel-gfx] [CI] Pre-merge testing disabled Message-ID: <c80cb85e77c74b949ab75778b330494b@intel.com> Hello world, Due to changes in our global data policy rules, the bucket used to store the CI results became private, which prevents us from providing any testing result. We have received a notice on Sunday about this change, notified them on Monday that we wanted to keep our storage public and ended up on Tuesday with a private bucket. We are working as fast as possible to address this, but we cannot give any ETA. We'll be updating you in this thread. Sorry for the inconvenience, Martin -------------- next part -------------- A non-text attachment was scrubbed... Name: pEpkey.asc Type: application/pgp-keys Size: 1774 bytes Desc: pEpkey.asc URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200616/fa81c242/attachment.key> From mika.kuoppala at linux.intel.com Tue Jun 16 09:45:11 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 12:45:11 +0300 Subject: [Intel-gfx] [PATCH 1/9] drm/i915/selftests: Exercise far preemption rollbacks In-Reply-To: <159229855527.18308.214917781408344749@build.alporthouse.com> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> <87a713s847.fsf@gaia.fi.intel.com> <159229855527.18308.214917781408344749@build.alporthouse.com> Message-ID: <87zh93qr88.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Quoting Mika Kuoppala (2020-06-16 09:55:04) >> >> Chris Wilson <chris at chris-wilson.co.uk> writes: >> >> > Not too long ago, we realised we had issues with a rolling back a >> > context so far for a preemption request we considered the resubmit not >> > to be a rollback but a forward roll. This means we would issue a lite >> > restore instead of forcing a full restore, continuing execution of the >> > old requests rather than causing a preemption. Add a selftest to >> > exercise such a far rollback, such that if we were to skip the full >> > restore, we would execute invalid instructions in the ring and hang. >> > >> > Note that while I was able to confirm that this causes us to do a >> > lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: >> > Incrementally check for rewinding") disabled), it did not trick the HW >> > into rolling past the old RING_TAIL. Myybe on other HW. >> > >> > References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") >> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> >> > --- >> > drivers/gpu/drm/i915/gt/selftest_lrc.c | 150 +++++++++++++++++++++++++ >> > 1 file changed, 150 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c >> > index 91543494f595..3d088116a055 100644 >> > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c >> > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c >> > @@ -363,6 +363,155 @@ static int live_unlite_preempt(void *arg) >> > return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); >> > } >> > >> > +static int live_unlite_ring(void *arg) >> > +{ >> > + struct intel_gt *gt = arg; >> > + struct intel_engine_cs *engine; >> > + struct igt_spinner spin; >> > + enum intel_engine_id id; >> > + int err = 0; >> > + >> > + /* >> > + * Setup a preemption event that will cause almost the entire ring >> > + * to be unwound, potentially fooling our intel_ring_direction() >> > + * into emitting a forward lite-restore instead of the rollback. >> > + */ >> > + >> > + if (igt_spinner_init(&spin, gt)) >> > + return -ENOMEM; >> > + >> > + for_each_engine(engine, gt, id) { >> > + struct intel_context *ce[2] = {}; >> > + struct i915_request *rq; >> > + struct igt_live_test t; >> > + int n; >> > + >> > + if (!intel_engine_has_preemption(engine)) >> > + continue; >> > + >> > + if (!intel_engine_can_store_dword(engine)) >> > + continue; >> > + >> > + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { >> > + err = -EIO; >> > + break; >> > + } >> > + engine_heartbeat_disable(engine); >> > + >> > + for (n = 0; n < ARRAY_SIZE(ce); n++) { >> > + struct intel_context *tmp; >> > + >> > + tmp = intel_context_create(engine); >> > + if (IS_ERR(tmp)) { >> > + err = PTR_ERR(tmp); >> > + goto err_ce; >> > + } >> > + >> > + err = intel_context_pin(tmp); >> > + if (err) { >> > + intel_context_put(tmp); >> > + goto err_ce; >> > + } >> > + >> > + memset32(tmp->ring->vaddr, >> > + 0xdeadbeef, /* trigger a hang if executed */ >> > + tmp->ring->vma->size / sizeof(u32)); >> > + >> > + ce[n] = tmp; >> > + } >> > + >> > + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); >> > + if (IS_ERR(rq)) { >> > + err = PTR_ERR(rq); >> > + goto err_ce; >> > + } >> > + >> > + i915_request_get(rq); >> > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; >> > + i915_request_add(rq); >> > + >> > + if (!igt_wait_for_spinner(&spin, rq)) { >> > + intel_gt_set_wedged(gt); >> > + i915_request_put(rq); >> > + err = -ETIME; >> > + goto err_ce; >> > + } >> > + >> > + /* Fill the ring, until we will cause a wrap */ >> > + n = 0; >> > + while (intel_ring_direction(ce[0]->ring, >> > + rq->wa_tail, >> > + ce[0]->ring->tail) <= 0) { >> > + struct i915_request *tmp; >> >> I got that you tested it with revert of incremental, but >> >> can we make 2 versions of this test so that the half ring size >> is honoured and then another where we do few requests past the half? > > We have examples of normal preemption. This chooses to focus on the > impact of intel_ring_direction(). Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > >> Just would like to see the hardware get confused according >> to our assertions. > > I haven't tricked the HW into doing anything unexpected. I've tried > switching the spinner out for a semaphore in the ring (in case that > would keep the ring registers primed) and I've tried releasing the > spinner at the same time as trying to submit the preemption (though that > will be incredibly timing dependent) with the aim of having it process > the request tail at the same time as the ELSP. > -Chris From chris at chris-wilson.co.uk Tue Jun 16 10:12:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 11:12:55 +0100 Subject: [Intel-gfx] [PATCH 26/28] drm/i915: Fair low-latency scheduling In-Reply-To: <5a7ebfbc-665b-eff6-d969-7d27b568f161@shipmail.org> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-26-chris@chris-wilson.co.uk> <5a7ebfbc-665b-eff6-d969-7d27b568f161@shipmail.org> Message-ID: <159230237587.18308.5225913549750961471@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-16 10:07:28) > Hi, Chris, > > Some comments and questions: > > On 6/8/20 12:21 AM, Chris Wilson wrote: > > The first "scheduler" was a topographical sorting of requests into > > priority order. The execution order was deterministic, the earliest > > submitted, highest priority request would be executed first. Priority > > inherited ensured that inversions were kept at bay, and allowed us to > > dynamically boost priorities (e.g. for interactive pageflips). > > > > The minimalistic timeslicing scheme was an attempt to introduce fairness > > between long running requests, by evicting the active request at the end > > of a timeslice and moving it to the back of its priority queue (while > > ensuring that dependencies were kept in order). For short running > > requests from many clients of equal priority, the scheme is still very > > much FIFO submission ordering, and as unfair as before. > > > > To impose fairness, we need an external metric that ensures that clients > > are interpersed, we don't execute one long chain from client A before > > executing any of client B. This could be imposed by the clients by using > > a fences based on an external clock, that is they only submit work for a > > "frame" at frame-interval, instead of submitting as much work as they > > are able to. The standard SwapBuffers approach is akin to double > > bufferring, where as one frame is being executed, the next is being > > submitted, such that there is always a maximum of two frames per client > > in the pipeline. Even this scheme exhibits unfairness under load as a > > single client will execute two frames back to back before the next, and > > with enough clients, deadlines will be missed. > > > > The idea introduced by BFS/MuQSS is that fairness is introduced by > > metering with an external clock. Every request, when it becomes ready to > > execute is assigned a virtual deadline, and execution order is then > > determined by earliest deadline. Priority is used as a hint, rather than > > strict ordering, where high priority requests have earlier deadlines, > > but not necessarily earlier than outstanding work. Thus work is executed > > in order of 'readiness', with timeslicing to demote long running work. > > > > The Achille's heel of this scheduler is its strong preference for > > low-latency and favouring of new queues. Whereas it was easy to dominate > > the old scheduler by flooding it with many requests over a short period > > of time, the new scheduler can be dominated by a 'synchronous' client > > that waits for each of its requests to complete before submitting the > > next. As such a client has no history, it is always considered > > ready-to-run and receives an earlier deadline than the long running > > requests. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- > > .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 1 + > > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +- > > drivers/gpu/drm/i915/gt/intel_engine_types.h | 24 -- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 328 +++++++----------- > > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 5 +- > > drivers/gpu/drm/i915/gt/selftest_lrc.c | 43 ++- > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- > > drivers/gpu/drm/i915/i915_priolist_types.h | 7 +- > > drivers/gpu/drm/i915/i915_request.h | 4 +- > > drivers/gpu/drm/i915/i915_scheduler.c | 322 ++++++++++++----- > > drivers/gpu/drm/i915/i915_scheduler.h | 22 +- > > drivers/gpu/drm/i915/i915_scheduler_types.h | 17 + > > .../drm/i915/selftests/i915_mock_selftests.h | 1 + > > drivers/gpu/drm/i915/selftests/i915_request.c | 1 + > > .../gpu/drm/i915/selftests/i915_scheduler.c | 49 +++ > > 16 files changed, 484 insertions(+), 362 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c > > Do we have timings to back this change up? Would it make sense to have a > configurable scheduler choice? Yes, there's igt/benchmarks/gem_wsim to show the impact on scheduling decisions for various workloads. (You can guess what the impact of choosing a different execution order and forcing more context switches will be... About -1% to throughput with multiple clients) And igt/tests/gem_exec_schedule to test basic properties, with a bunch of new fairness tests to try and decide if this is the right thing. Under saturated conditions, there is no contest, a fair scheduler produces consistent results, and the vdeadlines allow for realtime-response under load. > > @@ -1096,22 +1099,30 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) > > { > > struct i915_request *rq, *rn, *active = NULL; > > struct list_head *uninitialized_var(pl); > > - int prio = I915_PRIORITY_INVALID; > > + u64 deadline = I915_DEADLINE_NEVER; > > > > lockdep_assert_held(&engine->active.lock); > > > > list_for_each_entry_safe_reverse(rq, rn, > > &engine->active.requests, > > sched.link) { > > - if (i915_request_completed(rq)) > > + if (i915_request_completed(rq)) { > > + list_del_init(&rq->sched.link); > > continue; /* XXX */ > > + } > > Is this an unrelated change? If so separate patch? It's not totally unrelated :) > > @@ -2162,14 +2140,13 @@ static void execlists_dequeue(struct intel_engine_cs *engine) > > __unwind_incomplete_requests(engine); > > > > last = NULL; > > - } else if (need_timeslice(engine, last, ve) && > > - timeslice_expired(execlists, last)) { > > + } else if (timeslice_expired(engine, last)) { > > ENGINE_TRACE(engine, > > - "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n", > > - last->fence.context, > > - last->fence.seqno, > > - last->sched.attr.priority, > > - execlists->queue_priority_hint, > > + "expired:%s last=%llx:%llu, deadline=%llu, now=%llu, yield?=%s\n", > > + yesno(timer_expired(&execlists->timer)), > > + last->fence.context, last->fence.seqno, > > + rq_deadline(last), > > + i915_sched_to_ticks(ktime_get()), > > yesno(timeslice_yield(execlists, last))); > > There are multiple introductions of ktime_get() in the patch. Perhaps > use monotonic clock source like ktime_get_raw()? Also immediately > convert to ns. ktime_get() is monotonic. The only difference is that tkr_mono has an wall-offset that tkr_raw does not. [I'm sure there's a good reason.] The choice is really whether ktime_get_(mono|raw)_fast_ns() is sufficient for our needs. I do like the idea of having the deadline being some recognisable timestamp, as it makes it easier to play with mixing in real, albeit soft, deadlines. > > @@ -2837,10 +2788,7 @@ static void __execlists_unhold(struct i915_request *rq) > > GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); > > > > i915_request_clear_hold(rq); > > - list_move_tail(&rq->sched.link, > > - i915_sched_lookup_priolist(rq->engine, > > - rq_prio(rq))); > > - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); > > + submit |= intel_engine_queue_request(rq->engine, rq); > > As new to this codebase, I immediately wonder whether that bitwise or is > intentional and whether you got the short-circuiting right. It looks > correct to me. bool submit, not many bits :) > > diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h > > index 118ab6650d1f..23594e712292 100644 > > --- a/drivers/gpu/drm/i915/i915_request.h > > +++ b/drivers/gpu/drm/i915/i915_request.h > > @@ -561,7 +561,7 @@ static inline void i915_request_clear_hold(struct i915_request *rq) > > } > > > > static inline struct intel_timeline * > > -i915_request_timeline(struct i915_request *rq) > > +i915_request_timeline(const struct i915_request *rq) > > { > > /* Valid only while the request is being constructed (or retired). */ > > return rcu_dereference_protected(rq->timeline, > > @@ -576,7 +576,7 @@ i915_request_gem_context(struct i915_request *rq) > > } > > > > static inline struct intel_timeline * > > -i915_request_active_timeline(struct i915_request *rq) > > +i915_request_active_timeline(const struct i915_request *rq) > > Are these unrelated? Separate patch? They were used at one point, when I had a const request. > > { > > /* > > * When in use during submission, we are protected by a guarantee that > > diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c > > index 4c189b81cc62..30bcb6f9d99f 100644 > > --- a/drivers/gpu/drm/i915/i915_scheduler.c > > +++ b/drivers/gpu/drm/i915/i915_scheduler.c > > @@ -20,6 +20,11 @@ static struct i915_global_scheduler { > > static DEFINE_SPINLOCK(ipi_lock); > > static LIST_HEAD(ipi_list); > > > > +static inline u64 rq_deadline(const struct i915_request *rq) > > +{ > > + return READ_ONCE(rq->sched.deadline); > > +} > > + > > Does this need a release barrier paired with an acquire barrier in > __i915_request_set_deadline below? No, the state can be inconsistent. If it changes as we are processing the previous value, there will be another reschedule. Within set_deadline, rq->sched.deadline is under the engine->active.lock, it is just that rq_deadline() is used to peek before we take the lock, as well as shorthand within the critical section. > > +static bool __i915_request_set_deadline(struct i915_request *rq, u64 deadline) > > +{ > > + struct intel_engine_cs *engine = rq->engine; > > + struct i915_request *rn; > > + struct list_head *plist; > > + LIST_HEAD(dfs); > > + > > + lockdep_assert_held(&engine->active.lock); > > + list_add(&rq->sched.dfs, &dfs); > > + > > + list_for_each_entry(rq, &dfs, sched.dfs) { > > + struct i915_dependency *p; > > + > > + GEM_BUG_ON(rq->engine != engine); > > + > > + for_each_signaler(p, rq) { > > + struct i915_request *s = > > + container_of(p->signaler, typeof(*s), sched); > > + > > + GEM_BUG_ON(s == rq); > > + > > + if (rq_deadline(s) <= deadline) > > + continue; > > + > > + if (i915_request_completed(s)) > > + continue; > > + > > + if (s->engine != rq->engine) { > > + spin_lock(&ipi_lock); > > + if (deadline < p->ipi_deadline) { > > + p->ipi_deadline = deadline; > > + list_move(&p->ipi_link, &ipi_list); > > + irq_work_queue(&ipi_work); > > + } > > + spin_unlock(&ipi_lock); > > + continue; > > + } > > + > > + list_move_tail(&s->sched.dfs, &dfs); > > + } > > + } > > + > > + plist = i915_sched_lookup_priolist(engine, deadline); > > + > > + /* Fifo and depth-first replacement ensure our deps execute first */ > > + list_for_each_entry_safe_reverse(rq, rn, &dfs, sched.dfs) { > > + GEM_BUG_ON(rq->engine != engine); > > + GEM_BUG_ON(deadline > rq_deadline(rq)); > > + > > + INIT_LIST_HEAD(&rq->sched.dfs); > > + WRITE_ONCE(rq->sched.deadline, deadline); > > An smp barrier needed? No. It is locked by engine->active.lock, with a couple of peeks before the lock that do not require serialisation with other changes. > > +static u64 prio_slice(int prio) > > { > > - const struct i915_request *inflight; > > + u64 slice; > > + int sf; > > > > /* > > - * We only need to kick the tasklet once for the high priority > > - * new context we add into the queue. > > + * With a 1ms scheduling quantum: > > + * > > + * MAX USER: ~32us deadline > > + * 0: ~16ms deadline > > + * MIN_USER: 1000ms deadline > > */ > > - if (prio <= engine->execlists.queue_priority_hint) > > - return; > > > > - rcu_read_lock(); > > + if (prio >= __I915_PRIORITY_KERNEL__) > > + return INT_MAX - prio; > > > > - /* Nothing currently active? We're overdue for a submission! */ > > - inflight = execlists_active(&engine->execlists); > > - if (!inflight) > > - goto unlock; > > + slice = __I915_PRIORITY_KERNEL__ - prio; > > + if (prio >= 0) > > + sf = 20 - 6; > > + else > > + sf = 20 - 1; > > + > > + return slice << sf; > > +} > > + > > Is this the same deadline calculation as used in the BFS? Could you > perhaps add a pointer to some documentation? It is a heuristic. The scale factor in BFS is designed for a smaller range and is not effective for passing our existing priority ordering tests. The challenge is to pick something that is fair that roughly matches usage. It basically says that if client A submits 3 requests, then client B, C will be able to run before the later requests of client A so long as they are submitted within 16ms. Currently we get AAABC, the vdeadlines turn that into ABCAA. So we would ideally like the quota for each client to reflect their needs, so if client A needed all 3 requests within 16ms, it would have a vdeadline closer to 5ms (and so it would compete for the GPU against other clients). Now with this less strict priority system we can let normal userspace bump their priorities, or we can use the average context runtime to try and adjust priorities on the fly (i.e. do not used an unbias quota). But I suspect removing any fairness will skew the scheduler once more. -Chris From chris at chris-wilson.co.uk Tue Jun 16 10:38:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 11:38:48 +0100 Subject: [Intel-gfx] [PATCH 3/9] drm/i915/selftests: Enable selftesting of busy-stats In-Reply-To: <874krbs7qg.fsf@gaia.fi.intel.com> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> <20200616084141.3722-3-chris@chris-wilson.co.uk> <874krbs7qg.fsf@gaia.fi.intel.com> Message-ID: <159230392826.18853.3449404310767518966@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-16 10:03:19) > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > A couple of very simple tests to ensure that the basic properties of > > per-engine busyness accounting [0% and 100% busy] are faithful. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 94 ++++++++++++++++++++ > > drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ > > 2 files changed, 99 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > > index cbf6b0735272..fb0fd8a7db9a 100644 > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > > @@ -7,6 +7,99 @@ > > #include "i915_selftest.h" > > #include "selftest_engine.h" > > #include "selftests/igt_atomic.h" > > +#include "selftests/igt_flush_test.h" > > +#include "selftests/igt_spinner.h" > > + > > +static int live_engine_busy_stats(void *arg) > > +{ > > + struct intel_gt *gt = arg; > > + struct intel_engine_cs *engine; > > + enum intel_engine_id id; > > + struct igt_spinner spin; > > + int err = 0; > > + > > + /* > > + * Check that if an engine supports busy-stats, they tell the truth. > > + */ > > + > > + if (igt_spinner_init(&spin, gt)) > > + return -ENOMEM; > > + > > + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); > > + for_each_engine(engine, gt, id) { > > + struct i915_request *rq; > > + ktime_t de; > > + u64 dt; > > + > > + if (!intel_engine_supports_stats(engine)) > > + continue; > > + > > + if (!intel_engine_can_store_dword(engine)) > > + continue; > > + > > + if (intel_gt_pm_wait_for_idle(gt)) { > > + err = -EBUSY; > > + break; > > + } > > + > > + preempt_disable(); > > + dt = ktime_to_ns(ktime_get()); > > + de = intel_engine_get_busy_time(engine); > > + udelay(100); > > + de = ktime_sub(intel_engine_get_busy_time(engine), de); > > + dt = ktime_to_ns(ktime_get()) - dt; > > + preempt_enable(); > > + if (de > 10) { > > 10 is from stetson? > > Well I would say it is strict enough. > > The signed de just makes me nervous, so de < 0 too? de < 0 would be nasty, monotonic going backwards, so yeah. -Chris From chris at chris-wilson.co.uk Tue Jun 16 10:54:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 11:54:58 +0100 Subject: [Intel-gfx] [PATCH 26/28] drm/i915: Fair low-latency scheduling In-Reply-To: <5a7ebfbc-665b-eff6-d969-7d27b568f161@shipmail.org> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-26-chris@chris-wilson.co.uk> <5a7ebfbc-665b-eff6-d969-7d27b568f161@shipmail.org> Message-ID: <159230489800.18853.12875850746221737321@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-16 10:07:28) > Hi, Chris, > > Some comments and questions: > > On 6/8/20 12:21 AM, Chris Wilson wrote: > > The first "scheduler" was a topographical sorting of requests into > > priority order. The execution order was deterministic, the earliest > > submitted, highest priority request would be executed first. Priority > > inherited ensured that inversions were kept at bay, and allowed us to > > dynamically boost priorities (e.g. for interactive pageflips). > > > > The minimalistic timeslicing scheme was an attempt to introduce fairness > > between long running requests, by evicting the active request at the end > > of a timeslice and moving it to the back of its priority queue (while > > ensuring that dependencies were kept in order). For short running > > requests from many clients of equal priority, the scheme is still very > > much FIFO submission ordering, and as unfair as before. > > > > To impose fairness, we need an external metric that ensures that clients > > are interpersed, we don't execute one long chain from client A before > > executing any of client B. This could be imposed by the clients by using > > a fences based on an external clock, that is they only submit work for a > > "frame" at frame-interval, instead of submitting as much work as they > > are able to. The standard SwapBuffers approach is akin to double > > bufferring, where as one frame is being executed, the next is being > > submitted, such that there is always a maximum of two frames per client > > in the pipeline. Even this scheme exhibits unfairness under load as a > > single client will execute two frames back to back before the next, and > > with enough clients, deadlines will be missed. > > > > The idea introduced by BFS/MuQSS is that fairness is introduced by > > metering with an external clock. Every request, when it becomes ready to > > execute is assigned a virtual deadline, and execution order is then > > determined by earliest deadline. Priority is used as a hint, rather than > > strict ordering, where high priority requests have earlier deadlines, > > but not necessarily earlier than outstanding work. Thus work is executed > > in order of 'readiness', with timeslicing to demote long running work. > > > > The Achille's heel of this scheduler is its strong preference for > > low-latency and favouring of new queues. Whereas it was easy to dominate > > the old scheduler by flooding it with many requests over a short period > > of time, the new scheduler can be dominated by a 'synchronous' client > > that waits for each of its requests to complete before submitting the > > next. As such a client has no history, it is always considered > > ready-to-run and receives an earlier deadline than the long running > > requests. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- > > .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 1 + > > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +- > > drivers/gpu/drm/i915/gt/intel_engine_types.h | 24 -- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 328 +++++++----------- > > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 5 +- > > drivers/gpu/drm/i915/gt/selftest_lrc.c | 43 ++- > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- > > drivers/gpu/drm/i915/i915_priolist_types.h | 7 +- > > drivers/gpu/drm/i915/i915_request.h | 4 +- > > drivers/gpu/drm/i915/i915_scheduler.c | 322 ++++++++++++----- > > drivers/gpu/drm/i915/i915_scheduler.h | 22 +- > > drivers/gpu/drm/i915/i915_scheduler_types.h | 17 + > > .../drm/i915/selftests/i915_mock_selftests.h | 1 + > > drivers/gpu/drm/i915/selftests/i915_request.c | 1 + > > .../gpu/drm/i915/selftests/i915_scheduler.c | 49 +++ > > 16 files changed, 484 insertions(+), 362 deletions(-) > > create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c > > Do we have timings to back this change up? Would it make sense to have a > configurable scheduler choice? gem_wsim workloads with different load balancers, varying the number of clients, % variation from previous patch. +mB--------------------------------------------------------------------+ | a | | cda | | c.a | | ..aa | | ..---. | | -.--+-. | | .c.-.-+++. b | | b bb.d-c-+--+++.aab aa b b | |b b b b b. b ..---+++-+++++....a. b. b b b b b b| | A| | | |___AM____| | | |A__| | | |MA_| | +----------------------------------------------------------------------+ Clients N Min Max Median Avg Stddev 1 63 -8.2 5.4 -0.045 -0.02375 0.094722134 2 63 -15.96 19.28 -0.64 -1.05 2.2428076 4 63 -5.11 2.95 -1.15 -1.0683333 0.72382651 8 63 -5.63 1.85 -0.905 -0.87122449 0.73390971 The wildest swings there do appear to be a result of interrupt latency, with the -1% impact from execution order and more context switching. -Chris From tzimmermann at suse.de Tue Jun 16 11:24:28 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Tue, 16 Jun 2020 13:24:28 +0200 Subject: [Intel-gfx] [PATCH] drm/shmem-helper: Fix obj->filp derefence In-Reply-To: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> References: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> Message-ID: <3c060e54-d209-dcb8-ca8b-73dd18324a8b@suse.de> Hi Daniel Am 15.06.20 um 17:10 schrieb Daniel Vetter: > I broke that in my refactoring: > > commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca > Author: Daniel Vetter <daniel.vetter at ffwll.ch> > Date: Fri May 29 16:05:42 2020 +0200 > > drm/shmem-helpers: Simplify dma-buf importing > > Reported-by: Thomas Zimmermann <tzimmermann at suse.de> > Fixes: 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing") > Cc: Boris Brezillon <boris.brezillon at collabora.com> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: Gerd Hoffmann <kraxel at redhat.com> > Cc: Rob Herring <robh at kernel.org> > Cc: Noralf Tr?nnes <noralf at tronnes.org> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > drivers/gpu/drm/drm_gem_shmem_helper.c | 20 +++++++++++--------- > 1 file changed, 11 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > index 0a7e3b664bc2..3e7ee407a17c 100644 > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > @@ -70,15 +70,17 @@ __drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private) > mutex_init(&shmem->vmap_lock); > INIT_LIST_HEAD(&shmem->madv_list); > > - /* > - * Our buffers are kept pinned, so allocating them > - * from the MOVABLE zone is a really bad idea, and > - * conflicts with CMA. See comments above new_inode() > - * why this is required _and_ expected if you're > - * going to pin these pages. > - */ > - mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | > - __GFP_RETRY_MAYFAIL | __GFP_NOWARN); > + if (!private) { > + /* > + * Our buffers are kept pinned, so allocating them > + * from the MOVABLE zone is a really bad idea, and > + * conflicts with CMA. See comments above new_inode() > + * why this is required _and_ expected if you're > + * going to pin these pages. > + */ > + mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | > + __GFP_RETRY_MAYFAIL | __GFP_NOWARN); > + } This bug is gone, but now I see [ 5.577857] ------------[ cut here ]------------ [ 5.577881] WARNING: CPU: 0 PID: 1 at drivers/gpu/drm/drm_gem.c:564 drm_gem_get_pages+0x190/0x1b0 [ 5.577883] Modules linked in: [ 5.577891] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.7.0-1-pae+ #40 [ 5.577893] Hardware name: MSI MS-6380 /MS-6380 , BIOS 07.00T [ 5.577897] EIP: drm_gem_get_pages+0x190/0x1b0 [ 5.577904] Code: b7 ff 8d 45 b0 e8 30 63 b7 ff e8 6b d8 38 00 eb 9d 8d b4 26 00 00 00 00 66 90 89 fb eb 97 8d 74 26 00 bb f4 ff ff ff eb 8c 90 <0f> 0b bb ea ff ff ff eb 82 8d b4 26 00 00 00 00 0f 0b e9 95 fe ff [ 5.577907] EAX: f24c0c00 EBX: f24c0c00 ECX: f3ae1900 EDX: 00000000 [ 5.577909] ESI: 00000000 EDI: 00000000 EBP: f3941b50 ESP: f3941afc [ 5.577912] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00010246 [ 5.577915] CR0: 80050033 CR2: b7f5c784 CR3: 1b6b8000 CR4: 000006f0 [ 5.577918] Call Trace: [ 5.577938] ? _cond_resched+0x18/0x50 [ 5.577950] drm_gem_shmem_get_pages+0x52/0xa0 [ 5.577955] drm_gem_shmem_vmap+0xa1/0x160 [ 5.577963] skms_simple_display_pipe_update+0x68/0xb0 [ 5.577973] drm_simple_kms_plane_atomic_update+0x23/0x30 [ 5.577976] drm_atomic_helper_commit_planes+0xba/0x220 [ 5.577981] drm_atomic_helper_commit_tail+0x33/0x70 [ 5.577984] commit_tail+0xe7/0x120 [ 5.577988] drm_atomic_helper_commit+0x107/0x130 [ 5.577991] ? drm_atomic_helper_setup_commit+0x5a0/0x5a0 [ 5.577995] drm_atomic_commit+0x3a/0x50 [ 5.577999] drm_client_modeset_commit_atomic+0x1ae/0x1e0 [ 5.578004] drm_client_modeset_commit_locked+0x48/0x80 [ 5.578008] drm_client_modeset_commit+0x20/0x40 [ 5.578012] drm_fb_helper_restore_fbdev_mode_unlocked+0x44/0x90 [ 5.578015] drm_fb_helper_set_par+0x2e/0x40 [ 5.578025] fbcon_init+0x285/0x590 [ 5.578035] visual_init+0xb9/0x120 [ 5.578040] do_bind_con_driver.isra.0+0x18a/0x280 [ 5.578045] do_take_over_console+0x2c/0x40 [ 5.578049] do_fbcon_takeover+0x5f/0xd0 [ 5.578053] fbcon_fb_registered+0xb7/0xe0 [ 5.578057] do_register_framebuffer+0x1ae/0x2e0 [ 5.578062] register_framebuffer+0x1c/0x30 [ 5.578065] __drm_fb_helper_initial_config_and_unlock+0x96/0xd0 [ 5.578069] drm_fbdev_client_hotplug+0x136/0x220 [ 5.578072] drm_fbdev_generic_setup+0x9f/0x14a [ 5.578076] ? skms_device_create.constprop.0+0x9f/0xb0 [ 5.578079] skms_probe+0x1b/0x20 [ 5.578083] platform_drv_probe+0x47/0x90 [ 5.578092] really_probe+0x2a9/0x3f0 [ 5.578096] driver_probe_device+0xa9/0xf0 [ 5.578100] ? _cond_resched+0x18/0x50 [ 5.578103] device_driver_attach+0x99/0xa0 [ 5.578107] __driver_attach+0x79/0x130 [ 5.578111] ? device_driver_attach+0xa0/0xa0 [ 5.578114] bus_for_each_dev+0x5b/0xa0 [ 5.578118] driver_attach+0x19/0x20 [ 5.578122] ? device_driver_attach+0xa0/0xa0 [ 5.578125] bus_add_driver+0x10d/0x1e0 [ 5.578130] driver_register+0x79/0xd0 [ 5.578137] ? mipi_dsi_bus_init+0x14/0x14 [ 5.578140] __platform_driver_register+0x2f/0x40 [ 5.578143] skms_platform_driver_init+0x14/0x16 [ 5.578150] do_one_initcall+0x42/0x1e0 [ 5.578158] ? rdinit_setup+0x2a/0x2a [ 5.578161] ? rdinit_setup+0x2a/0x2a [ 5.578166] do_initcalls+0xae/0xd1 [ 5.578170] kernel_init_freeable+0x108/0x14f [ 5.578181] ? rest_init+0x9b/0x9b [ 5.578185] kernel_init+0xd/0xe5 [ 5.578193] ret_from_fork+0x2e/0x38 [ 5.578201] ---[ end trace d857253095ede2e3 ]--- [ 5.578221] BUG: unable to handle page fault for address: ffffffea [ 5.578223] #PF: supervisor read access in kernel mode [ 5.578225] #PF: error_code(0x0000) - not-present page [ 5.578227] *pdpt = 000000001b6b4001 *pde = 000000001bc91067 *pte = 0000000000000000 [ 5.578233] Oops: 0000 [#1] SMP NOPTI [ 5.578237] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 5.7.0-1-pae+ #40 [ 5.578239] Hardware name: MSI MS-6380 /MS-6380 , BIOS 07.00T [ 5.578249] EIP: memcpy_toio+0x2b/0x60 [ 5.578252] Code: 8d 44 20 00 85 c9 74 47 55 89 e5 57 89 c7 56 89 d6 53 89 cb a8 01 75 3f 83 fb 01 76 08 f7 c7 02 00 00 00 75 1a 89 d9 c1 e9 02 <f3> a5 f6 c3 02 74 02 66 a5 f6 c3 01 74 01 a4 5b 5e 5f 5d c3 90 66 [ 5.578255] EAX: f7200000 EBX: 00001400 ECX: 00000500 EDX: ffffffea [ 5.578257] ESI: ffffffea EDI: f7200000 EBP: f3941b3c ESP: f3941b30 [ 5.578260] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00010216 [ 5.578262] CR0: 80050033 CR2: ffffffea CR3: 1b6b8000 CR4: 000006f0 [ 5.578263] Call Trace: [ 5.578271] drm_fb_memcpy_dstclip+0x6f/0x90 [ 5.578276] drm_fb_blit_rect_dstclip+0x8d/0xc0 [ 5.578280] skms_simple_display_pipe_update+0x8d/0xb0 [ 5.578285] drm_simple_kms_plane_atomic_update+0x23/0x30 [ 5.578288] drm_atomic_helper_commit_planes+0xba/0x220 [ 5.578292] drm_atomic_helper_commit_tail+0x33/0x70 [ 5.578295] commit_tail+0xe7/0x120 [ 5.578299] drm_atomic_helper_commit+0x107/0x130 [ 5.578303] ? drm_atomic_helper_setup_commit+0x5a0/0x5a0 [ 5.578306] drm_atomic_commit+0x3a/0x50 [ 5.578310] drm_client_modeset_commit_atomic+0x1ae/0x1e0 [ 5.578315] drm_client_modeset_commit_locked+0x48/0x80 [ 5.578318] drm_client_modeset_commit+0x20/0x40 [ 5.578322] drm_fb_helper_restore_fbdev_mode_unlocked+0x44/0x90 [ 5.578325] drm_fb_helper_set_par+0x2e/0x40 [ 5.578329] fbcon_init+0x285/0x590 [ 5.578333] visual_init+0xb9/0x120 [ 5.578338] do_bind_con_driver.isra.0+0x18a/0x280 [ 5.578342] do_take_over_console+0x2c/0x40 [ 5.578346] do_fbcon_takeover+0x5f/0xd0 [ 5.578350] fbcon_fb_registered+0xb7/0xe0 [ 5.578353] do_register_framebuffer+0x1ae/0x2e0 [ 5.578358] register_framebuffer+0x1c/0x30 [ 5.578361] __drm_fb_helper_initial_config_and_unlock+0x96/0xd0 [ 5.578364] drm_fbdev_client_hotplug+0x136/0x220 [ 5.578368] drm_fbdev_generic_setup+0x9f/0x14a [ 5.578371] ? skms_device_create.constprop.0+0x9f/0xb0 [ 5.578374] skms_probe+0x1b/0x20 [ 5.578377] platform_drv_probe+0x47/0x90 [ 5.578381] really_probe+0x2a9/0x3f0 [ 5.578385] driver_probe_device+0xa9/0xf0 [ 5.578388] ? _cond_resched+0x18/0x50 [ 5.578392] device_driver_attach+0x99/0xa0 [ 5.578396] __driver_attach+0x79/0x130 [ 5.578400] ? device_driver_attach+0xa0/0xa0 [ 5.578403] bus_for_each_dev+0x5b/0xa0 [ 5.578407] driver_attach+0x19/0x20 [ 5.578411] ? device_driver_attach+0xa0/0xa0 [ 5.578414] bus_add_driver+0x10d/0x1e0 [ 5.578418] driver_register+0x79/0xd0 [ 5.578421] ? mipi_dsi_bus_init+0x14/0x14 [ 5.578424] __platform_driver_register+0x2f/0x40 [ 5.578428] skms_platform_driver_init+0x14/0x16 [ 5.578431] do_one_initcall+0x42/0x1e0 [ 5.578434] ? rdinit_setup+0x2a/0x2a [ 5.578437] ? rdinit_setup+0x2a/0x2a [ 5.578441] do_initcalls+0xae/0xd1 [ 5.578445] kernel_init_freeable+0x108/0x14f [ 5.578449] ? rest_init+0x9b/0x9b [ 5.578453] kernel_init+0xd/0xe5 [ 5.578457] ret_from_fork+0x2e/0x38 [ 5.578459] Modules linked in: [ 5.578463] CR2: 00000000ffffffea [ 5.578472] ---[ end trace d857253095ede2e4 ]--- because drm_gem_get_pages() needs obj->filp. All this happens for dumb buffers. Why is a dumb buffer set up with (private == true) ? It has an associated file. Best regards Thomas > > return shmem; > > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N?rnberg, Germany (HRB 36809, AG N?rnberg) Gesch?ftsf?hrer: Felix Imend?rffer -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200616/eff425c9/attachment.sig> From colin.king at canonical.com Tue Jun 16 11:42:21 2020 From: colin.king at canonical.com (Colin King) Date: Tue, 16 Jun 2020 12:42:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/display: fix missing null check on allocated dsb object Message-ID: <20200616114221.73971-1-colin.king@canonical.com> From: Colin Ian King <colin.king at canonical.com> Currently there is no null check for a failed memory allocation on the dsb object and without this a null pointer dereference error can occur. Fix this by adding a null check. Note: added a drm_err message in keeping with the error message style in the function. Addresses-Coverity: ("Dereference null return") Fixes: afeda4f3b1c8 ("drm/i915/dsb: Pre allocate and late cleanup of cmd buffer") Signed-off-by: Colin Ian King <colin.king at canonical.com> --- drivers/gpu/drm/i915/display/intel_dsb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 24e6d63e2d47..566fa72427b3 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -271,6 +271,10 @@ void intel_dsb_prepare(struct intel_crtc_state *crtc_state) return; dsb = kmalloc(sizeof(*dsb), GFP_KERNEL); + if (!dsb) { + drm_err(&i915->drm, "DSB object creation failed\n"); + return; + } wakeref = intel_runtime_pm_get(&i915->runtime_pm); -- 2.27.0.rc0 From daniel.vetter at ffwll.ch Tue Jun 16 11:47:23 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 16 Jun 2020 13:47:23 +0200 Subject: [Intel-gfx] [PATCH] drm/shmem-helper: Only dma-buf imports are private obj Message-ID: <20200616114723.2363268-1-daniel.vetter@ffwll.ch> I broke that in my refactoring: commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca Author: Daniel Vetter <daniel.vetter at ffwll.ch> Date: Fri May 29 16:05:42 2020 +0200 drm/shmem-helpers: Simplify dma-buf importing I'm not entirely sure of the history here, but I suspect that in one of the rebases or when applying the patch I moved the hunk from drm_gem_shmem_prime_import_sg_table(), where it should be, to drm_gem_shmem_create_with_handle(), which is totally wrong. Remedy this. Thanks for Thomas for the crucual hint in debugging this. Reported-by: Thomas Zimmermann <tzimmermann at suse.de> Fixes: 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing") Cc: Boris Brezillon <boris.brezillon at collabora.com> Cc: Thomas Zimmermann <tzimmermann at suse.de> Cc: Gerd Hoffmann <kraxel at redhat.com> Cc: Rob Herring <robh at kernel.org> Cc: Noralf Tr?nnes <noralf at tronnes.org> Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index 0a7e3b664bc2..837e0840990c 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -377,7 +377,7 @@ drm_gem_shmem_create_with_handle(struct drm_file *file_priv, struct drm_gem_shmem_object *shmem; int ret; - shmem = __drm_gem_shmem_create(dev, size, true); + shmem = drm_gem_shmem_create(dev, size); if (IS_ERR(shmem)) return shmem; @@ -730,7 +730,7 @@ drm_gem_shmem_prime_import_sg_table(struct drm_device *dev, size_t size = PAGE_ALIGN(attach->dmabuf->size); struct drm_gem_shmem_object *shmem; - shmem = drm_gem_shmem_create(dev, size); + shmem = __drm_gem_shmem_create(dev, size, true); if (IS_ERR(shmem)) return ERR_CAST(shmem); -- 2.27.0 From dan.carpenter at oracle.com Tue Jun 16 11:54:59 2020 From: dan.carpenter at oracle.com (Dan Carpenter) Date: Tue, 16 Jun 2020 14:54:59 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/display: fix missing null check on allocated dsb object In-Reply-To: <20200616114221.73971-1-colin.king@canonical.com> References: <20200616114221.73971-1-colin.king@canonical.com> Message-ID: <20200616115459.GN4151@kadam> On Tue, Jun 16, 2020 at 12:42:21PM +0100, Colin King wrote: > From: Colin Ian King <colin.king at canonical.com> > > Currently there is no null check for a failed memory allocation > on the dsb object and without this a null pointer dereference > error can occur. Fix this by adding a null check. > > Note: added a drm_err message in keeping with the error message style > in the function. Don't give in to peer pressure! That's like being a lemming when Disney film makers come to push you off the cliff to create the 1958 nature film "White Wilderness". regards, dan carpenter From daniel at ffwll.ch Tue Jun 16 11:55:27 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 16 Jun 2020 13:55:27 +0200 Subject: [Intel-gfx] [PATCH 57/59] drm/ast: Use managed pci functions In-Reply-To: <b14b78e4-556d-9e52-bdfd-7c4229392ed9@suse.de> References: <20200415074034.175360-1-daniel.vetter@ffwll.ch> <20200415074034.175360-58-daniel.vetter@ffwll.ch> <b14b78e4-556d-9e52-bdfd-7c4229392ed9@suse.de> Message-ID: <20200616115527.GK20149@phenom.ffwll.local> On Thu, Jun 11, 2020 at 02:04:03PM +0200, Thomas Zimmermann wrote: > Hi > > Am 15.04.20 um 09:40 schrieb Daniel Vetter: > > Allows us to remove a bit of cleanup code. > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Cc: Dave Airlie <airlied at redhat.com> > > Cc: Thomas Zimmermann <tzimmermann at suse.de> > > Cc: Gerd Hoffmann <kraxel at redhat.com> > > Cc: Daniel Vetter <daniel.vetter at ffwll.ch> > > Cc: Emil Velikov <emil.velikov at collabora.com> > > Cc: "Noralf Tr?nnes" <noralf at tronnes.org> > > Cc: Sam Ravnborg <sam at ravnborg.org> > > Cc: "Christian K?nig" <christian.koenig at amd.com> > > Cc: "Y.C. Chen" <yc_chen at aspeedtech.com> > > Reviewed-by: Thomas Zimmermann <tzimmermann at suse.de> > > Thanks for answering my questions. Sorry for never getting back to it. Nw, patch applied now, thanks for your review. -Daniel > > Best regards > Thomas > > > --- > > drivers/gpu/drm/ast/ast_drv.c | 10 +++------- > > drivers/gpu/drm/ast/ast_main.c | 3 --- > > 2 files changed, 3 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c > > index b7ba22dddcad..48a9cc4e080a 100644 > > --- a/drivers/gpu/drm/ast/ast_drv.c > > +++ b/drivers/gpu/drm/ast/ast_drv.c > > @@ -91,15 +91,13 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) > > > > ast_kick_out_firmware_fb(pdev); > > > > - ret = pci_enable_device(pdev); > > + ret = pcim_enable_device(pdev); > > if (ret) > > return ret; > > > > dev = drm_dev_alloc(&driver, &pdev->dev); > > - if (IS_ERR(dev)) { > > - ret = PTR_ERR(dev); > > - goto err_pci_disable_device; > > - } > > + if (IS_ERR(dev)) > > + return PTR_ERR(dev); > > > > dev->pdev = pdev; > > pci_set_drvdata(pdev, dev); > > @@ -120,8 +118,6 @@ static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) > > ast_driver_unload(dev); > > err_drm_dev_put: > > drm_dev_put(dev); > > -err_pci_disable_device: > > - pci_disable_device(pdev); > > return ret; > > > > } > > diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c > > index e5398e3dabe7..1b35728ad871 100644 > > --- a/drivers/gpu/drm/ast/ast_main.c > > +++ b/drivers/gpu/drm/ast/ast_main.c > > @@ -531,8 +531,5 @@ void ast_driver_unload(struct drm_device *dev) > > drm_mode_config_cleanup(dev); > > > > ast_mm_fini(ast); > > - if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET) > > - pci_iounmap(dev->pdev, ast->ioregs); > > - pci_iounmap(dev->pdev, ast->regs); > > kfree(ast); > > } > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 N?rnberg, Germany > (HRB 36809, AG N?rnberg) > Gesch?ftsf?hrer: Felix Imend?rffer > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From colin.king at canonical.com Tue Jun 16 11:56:00 2020 From: colin.king at canonical.com (Colin Ian King) Date: Tue, 16 Jun 2020 12:56:00 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/display: fix missing null check on allocated dsb object In-Reply-To: <20200616115459.GN4151@kadam> References: <20200616114221.73971-1-colin.king@canonical.com> <20200616115459.GN4151@kadam> Message-ID: <45e8594c-14e5-ba67-9708-1b72fa2c51d3@canonical.com> On 16/06/2020 12:54, Dan Carpenter wrote: > On Tue, Jun 16, 2020 at 12:42:21PM +0100, Colin King wrote: >> From: Colin Ian King <colin.king at canonical.com> >> >> Currently there is no null check for a failed memory allocation >> on the dsb object and without this a null pointer dereference >> error can occur. Fix this by adding a null check. >> >> Note: added a drm_err message in keeping with the error message style >> in the function. > > Don't give in to peer pressure! That's like being a lemming when Disney > film makers come to push you off the cliff to create the 1958 nature > film "White Wilderness". :-) > > regards, > dan carpenter > From tzimmermann at suse.de Tue Jun 16 12:06:24 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Tue, 16 Jun 2020 14:06:24 +0200 Subject: [Intel-gfx] [PATCH] drm/shmem-helper: Only dma-buf imports are private obj In-Reply-To: <20200616114723.2363268-1-daniel.vetter@ffwll.ch> References: <20200616114723.2363268-1-daniel.vetter@ffwll.ch> Message-ID: <8c125158-fe7c-29a9-d9a8-9e6b418b6dd5@suse.de> Hi Am 16.06.20 um 13:47 schrieb Daniel Vetter: > I broke that in my refactoring: > > commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca > Author: Daniel Vetter <daniel.vetter at ffwll.ch> > Date: Fri May 29 16:05:42 2020 +0200 > > drm/shmem-helpers: Simplify dma-buf importing > > I'm not entirely sure of the history here, but I suspect that in one > of the rebases or when applying the patch I moved the hunk from > drm_gem_shmem_prime_import_sg_table(), where it should be, to > drm_gem_shmem_create_with_handle(), which is totally wrong. > > Remedy this. > > Thanks for Thomas for the crucual hint in debugging this. > > Reported-by: Thomas Zimmermann <tzimmermann at suse.de> > Fixes: 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing") > Cc: Boris Brezillon <boris.brezillon at collabora.com> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: Gerd Hoffmann <kraxel at redhat.com> > Cc: Rob Herring <robh at kernel.org> > Cc: Noralf Tr?nnes <noralf at tronnes.org> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Tested-by: Thomas Zimmermann <tzimmermann at suse.de> Reviewed-by: Thomas Zimmermann <tzimmermann at suse.de> > --- > drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > index 0a7e3b664bc2..837e0840990c 100644 > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > @@ -377,7 +377,7 @@ drm_gem_shmem_create_with_handle(struct drm_file *file_priv, > struct drm_gem_shmem_object *shmem; > int ret; > > - shmem = __drm_gem_shmem_create(dev, size, true); > + shmem = drm_gem_shmem_create(dev, size); > if (IS_ERR(shmem)) > return shmem; > > @@ -730,7 +730,7 @@ drm_gem_shmem_prime_import_sg_table(struct drm_device *dev, > size_t size = PAGE_ALIGN(attach->dmabuf->size); > struct drm_gem_shmem_object *shmem; > > - shmem = drm_gem_shmem_create(dev, size); > + shmem = __drm_gem_shmem_create(dev, size, true); > if (IS_ERR(shmem)) > return ERR_CAST(shmem); > > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N?rnberg, Germany (HRB 36809, AG N?rnberg) Gesch?ftsf?hrer: Felix Imend?rffer -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200616/78bfa948/attachment.sig> From daniel at ffwll.ch Tue Jun 16 12:07:19 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 16 Jun 2020 14:07:19 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200611141515.GW6578@ziepe.ca> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> Message-ID: <20200616120719.GL20149@phenom.ffwll.local> Hi Jason, Somehow this got stuck somewhere in the mail queues, only popped up just now ... On Thu, Jun 11, 2020 at 11:15:15AM -0300, Jason Gunthorpe wrote: > On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: > > > I still have my doubts about allowing fence waiting from within shrinkers. > > > IMO ideally they should use a trywait approach, in order to allow memory > > > allocation during command submission for drivers that > > > publish fences before command submission. (Since early reservation object > > > release requires that). > > > > Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up > > with a mempool to make sure it can handle it's allocations. > > > > > But since drivers are already waiting from within shrinkers and I take your > > > word for HMM requiring this, > > > > Yeah the big trouble is HMM and mmu notifiers. That's the really awkward > > one, the shrinker one is a lot less established. > > I really question if HW that needs something like DMA fence should > even be using mmu notifiers - the best use is HW that can fence the > DMA directly without having to get involved with some command stream > processing. > > Or at the very least it should not be a generic DMA fence but a > narrowed completion tied only into the same GPU driver's command > completion processing which should be able to progress without > blocking. The problem with gpus is that these completions leak across the board like mad. Both internally within memory managers (made a lot worse with p2p direct access to vram), and through uapi. Many gpus still have a very hard time preempting, so doing an overall switch in drivers/gpu to a memory management model where that is required is not a very realistic option. And minimally you need either preempt (still takes a while, but a lot faster generally than waiting for work to complete) or hw faults (just a bunch of tlb flushes plus virtual indexed caches, so just the caveat of that for a gpu, which has lots and big tlbs and caches). So preventing the completion leaks within the kernel is I think unrealistic, except if we just say "well sorry, run on windows, mkay" for many gpu workloads. Or more realistic "well sorry, run on the nvidia blob with nvidia hw". The userspace side we can somewhat isolate, at least for pure compute workloads. But the thing is drivers/gpu is a continum from tiny socs (where dma_fence is a very nice model) to huge compute stuff (where it's maybe not the nicest, but hey hw sucks so still neeeded). Doing full on break in uapi somewhere in there is at least a bit awkward, e.g. some of the media codec code on intel runs all the way from the smallest intel soc to the big transcode servers. So the current status quo is "total mess, every driver defines their own rules". All I'm trying to do is some common rules here, do make this mess slightly more manageable and overall reviewable and testable. I have no illusions that this is fundamentally pretty horrible, and the leftover wiggle room for writing memory manager is barely more than a hairline. Just not seeing how other options are better. > The intent of notifiers was never to endlessly block while vast > amounts of SW does work. > > Going around and switching everything in a GPU to GFP_ATOMIC seems > like bad idea. It's not everyone, or at least not everywhere, it's some fairly limited cases. Also, even if we drop the mmu_notifier on the floor, then we're stuck with shrinkers and GFP_NOFS. Still need a mempool of some sorts to guarantee you get out of a bind, so not much better. At least that's my current understanding of where we are across all drivers. > > I've pinged a bunch of armsoc gpu driver people and ask them how much this > > hurts, so that we have a clear answer. On x86 I don't think we have much > > of a choice on this, with userptr in amd and i915 and hmm work in nouveau > > (but nouveau I think doesn't use dma_fence in there). > > Right, nor will RDMA ODP. Hm, what's the context here? I thought RDMA side you really don't want dma_fence in mmu_notifiers, so not clear to me what you're agreeing on here. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From tzimmermann at suse.de Tue Jun 16 12:10:10 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Tue, 16 Jun 2020 14:10:10 +0200 Subject: [Intel-gfx] [PATCH] drm/shmem-helper: Fix obj->filp derefence In-Reply-To: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> References: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> Message-ID: <a1290884-8cca-f1a1-a05b-8d5c3e323506@suse.de> Hi, as discussed on IRC, we still need this patch. Am 15.06.20 um 17:10 schrieb Daniel Vetter: > I broke that in my refactoring: > > commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca > Author: Daniel Vetter <daniel.vetter at ffwll.ch> > Date: Fri May 29 16:05:42 2020 +0200 > > drm/shmem-helpers: Simplify dma-buf importing > > Reported-by: Thomas Zimmermann <tzimmermann at suse.de> > Fixes: 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing") > Cc: Boris Brezillon <boris.brezillon at collabora.com> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: Gerd Hoffmann <kraxel at redhat.com> > Cc: Rob Herring <robh at kernel.org> > Cc: Noralf Tr?nnes <noralf at tronnes.org> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > drivers/gpu/drm/drm_gem_shmem_helper.c | 20 +++++++++++--------- > 1 file changed, 11 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > index 0a7e3b664bc2..3e7ee407a17c 100644 > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > @@ -70,15 +70,17 @@ __drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private) > mutex_init(&shmem->vmap_lock); > INIT_LIST_HEAD(&shmem->madv_list); > > - /* > - * Our buffers are kept pinned, so allocating them > - * from the MOVABLE zone is a really bad idea, and > - * conflicts with CMA. See comments above new_inode() > - * why this is required _and_ expected if you're > - * going to pin these pages. > - */ > - mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | > - __GFP_RETRY_MAYFAIL | __GFP_NOWARN); > + if (!private) { I would test for (obj->filp) here, because it's what the branch depends on. Your choice. In any case Tested-by: Thomas Zimmermann <tzimmermann at suse.de> Reviewed-by: Thomas Zimmermann <tzimmermann at suse.de> > + /* > + * Our buffers are kept pinned, so allocating them > + * from the MOVABLE zone is a really bad idea, and > + * conflicts with CMA. See comments above new_inode() > + * why this is required _and_ expected if you're > + * going to pin these pages. > + */ > + mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | > + __GFP_RETRY_MAYFAIL | __GFP_NOWARN); > + } > > return shmem; > > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N?rnberg, Germany (HRB 36809, AG N?rnberg) Gesch?ftsf?hrer: Felix Imend?rffer -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200616/79d43db1/attachment.sig> From thomas_os at shipmail.org Tue Jun 16 12:11:25 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 16 Jun 2020 14:11:25 +0200 Subject: [Intel-gfx] [PATCH 26/28] drm/i915: Fair low-latency scheduling In-Reply-To: <159230237587.18308.5225913549750961471@build.alporthouse.com> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-26-chris@chris-wilson.co.uk> <5a7ebfbc-665b-eff6-d969-7d27b568f161@shipmail.org> <159230237587.18308.5225913549750961471@build.alporthouse.com> Message-ID: <623f4f89-1377-d18d-f611-7126a08ec85c@shipmail.org> Hi, On 6/16/20 12:12 PM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-16 10:07:28) >> Hi, Chris, >> >> Some comments and questions: >> >> On 6/8/20 12:21 AM, Chris Wilson wrote: >>> The first "scheduler" was a topographical sorting of requests into >>> priority order. The execution order was deterministic, the earliest >>> submitted, highest priority request would be executed first. Priority >>> inherited ensured that inversions were kept at bay, and allowed us to >>> dynamically boost priorities (e.g. for interactive pageflips). >>> >>> The minimalistic timeslicing scheme was an attempt to introduce fairness >>> between long running requests, by evicting the active request at the end >>> of a timeslice and moving it to the back of its priority queue (while >>> ensuring that dependencies were kept in order). For short running >>> requests from many clients of equal priority, the scheme is still very >>> much FIFO submission ordering, and as unfair as before. >>> >>> To impose fairness, we need an external metric that ensures that clients >>> are interpersed, we don't execute one long chain from client A before >>> executing any of client B. This could be imposed by the clients by using >>> a fences based on an external clock, that is they only submit work for a >>> "frame" at frame-interval, instead of submitting as much work as they >>> are able to. The standard SwapBuffers approach is akin to double >>> bufferring, where as one frame is being executed, the next is being >>> submitted, such that there is always a maximum of two frames per client >>> in the pipeline. Even this scheme exhibits unfairness under load as a >>> single client will execute two frames back to back before the next, and >>> with enough clients, deadlines will be missed. >>> >>> The idea introduced by BFS/MuQSS is that fairness is introduced by >>> metering with an external clock. Every request, when it becomes ready to >>> execute is assigned a virtual deadline, and execution order is then >>> determined by earliest deadline. Priority is used as a hint, rather than >>> strict ordering, where high priority requests have earlier deadlines, >>> but not necessarily earlier than outstanding work. Thus work is executed >>> in order of 'readiness', with timeslicing to demote long running work. >>> >>> The Achille's heel of this scheduler is its strong preference for >>> low-latency and favouring of new queues. Whereas it was easy to dominate >>> the old scheduler by flooding it with many requests over a short period >>> of time, the new scheduler can be dominated by a 'synchronous' client >>> that waits for each of its requests to complete before submitting the >>> next. As such a client has no history, it is always considered >>> ready-to-run and receives an earlier deadline than the long running >>> requests. >>> >>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>> --- >>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- >>> .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 1 + >>> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +- >>> drivers/gpu/drm/i915/gt/intel_engine_types.h | 24 -- >>> drivers/gpu/drm/i915/gt/intel_lrc.c | 328 +++++++----------- >>> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 5 +- >>> drivers/gpu/drm/i915/gt/selftest_lrc.c | 43 ++- >>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- >>> drivers/gpu/drm/i915/i915_priolist_types.h | 7 +- >>> drivers/gpu/drm/i915/i915_request.h | 4 +- >>> drivers/gpu/drm/i915/i915_scheduler.c | 322 ++++++++++++----- >>> drivers/gpu/drm/i915/i915_scheduler.h | 22 +- >>> drivers/gpu/drm/i915/i915_scheduler_types.h | 17 + >>> .../drm/i915/selftests/i915_mock_selftests.h | 1 + >>> drivers/gpu/drm/i915/selftests/i915_request.c | 1 + >>> .../gpu/drm/i915/selftests/i915_scheduler.c | 49 +++ >>> 16 files changed, 484 insertions(+), 362 deletions(-) >>> create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c >> Do we have timings to back this change up? Would it make sense to have a >> configurable scheduler choice? > Yes, there's igt/benchmarks/gem_wsim to show the impact on scheduling > decisions for various workloads. (You can guess what the impact of > choosing a different execution order and forcing more context switches > will be... About -1% to throughput with multiple clients) And > igt/tests/gem_exec_schedule to test basic properties, with a bunch of new > fairness tests to try and decide if this is the right thing. Under > saturated conditions, there is no contest, a fair scheduler produces > consistent results, and the vdeadlines allow for realtime-response under > load. Yeah, it's not really to convince me, but to provide a reference for the future. Perhaps add the gem_wsim timings to the commit message? > >> There are multiple introductions of ktime_get() in the patch. Perhaps >> use monotonic clock source like ktime_get_raw()? Also immediately >> convert to ns. > ktime_get() is monotonic. The only difference is that tkr_mono has an > wall-offset that tkr_raw does not. [I'm sure there's a good reason.] The > choice is really whether ktime_get_(mono|raw)_fast_ns() is sufficient for > our needs. Hmm. Yes you're right. I was thinking about the NTP adjustments. But given the requirement below they might be unimportant. > > I do like the idea of having the deadline being some recognisable > timestamp, as it makes it easier to play with mixing in real, albeit > soft, deadlines. > >>> @@ -2837,10 +2788,7 @@ static void __execlists_unhold(struct i915_request *rq) >>> GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); >>> >>> i915_request_clear_hold(rq); >>> - list_move_tail(&rq->sched.link, >>> - i915_sched_lookup_priolist(rq->engine, >>> - rq_prio(rq))); >>> - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); >>> + submit |= intel_engine_queue_request(rq->engine, rq); >> As new to this codebase, I immediately wonder whether that bitwise or is >> intentional and whether you got the short-circuiting right. It looks >> correct to me. > bool submit, not many bits :) Yes, the code is correct. My question was related to whether it was accepted practice, considering a future reader may think it might have been a mistake and change it anyway.... > >>> { >>> /* >>> * When in use during submission, we are protected by a guarantee that >>> diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c >>> index 4c189b81cc62..30bcb6f9d99f 100644 >>> --- a/drivers/gpu/drm/i915/i915_scheduler.c >>> +++ b/drivers/gpu/drm/i915/i915_scheduler.c >>> @@ -20,6 +20,11 @@ static struct i915_global_scheduler { >>> static DEFINE_SPINLOCK(ipi_lock); >>> static LIST_HEAD(ipi_list); >>> >>> +static inline u64 rq_deadline(const struct i915_request *rq) >>> +{ >>> + return READ_ONCE(rq->sched.deadline); >>> +} >>> + >> Does this need a release barrier paired with an acquire barrier in >> __i915_request_set_deadline below? > No, the state can be inconsistent. If it changes as we are processing > the previous value, there will be another reschedule. Within > set_deadline, rq->sched.deadline is under the engine->active.lock, it is > just that rq_deadline() is used to peek before we take the lock, as well > as shorthand within the critical section. > OK, understood. >>> +static u64 prio_slice(int prio) >>> { >>> - const struct i915_request *inflight; >>> + u64 slice; >>> + int sf; >>> >>> /* >>> - * We only need to kick the tasklet once for the high priority >>> - * new context we add into the queue. >>> + * With a 1ms scheduling quantum: >>> + * >>> + * MAX USER: ~32us deadline >>> + * 0: ~16ms deadline >>> + * MIN_USER: 1000ms deadline >>> */ >>> - if (prio <= engine->execlists.queue_priority_hint) >>> - return; >>> >>> - rcu_read_lock(); >>> + if (prio >= __I915_PRIORITY_KERNEL__) >>> + return INT_MAX - prio; >>> >>> - /* Nothing currently active? We're overdue for a submission! */ >>> - inflight = execlists_active(&engine->execlists); >>> - if (!inflight) >>> - goto unlock; >>> + slice = __I915_PRIORITY_KERNEL__ - prio; >>> + if (prio >= 0) >>> + sf = 20 - 6; >>> + else >>> + sf = 20 - 1; >>> + >>> + return slice << sf; >>> +} >>> + >> Is this the same deadline calculation as used in the BFS? Could you >> perhaps add a pointer to some documentation? > It is a heuristic. The scale factor in BFS is designed for a smaller > range and is not effective for passing our existing priority ordering > tests. > > The challenge is to pick something that is fair that roughly matches > usage. It basically says that if client A submits 3 requests, then > client B, C will be able to run before the later requests of client A so > long as they are submitted within 16ms. Currently we get AAABC, > the vdeadlines turn that into ABCAA. So we would ideally like the quota > for each client to reflect their needs, so if client A needed all 3 > requests within 16ms, it would have a vdeadline closer to 5ms (and so it > would compete for the GPU against other clients). Now with this less > strict priority system we can let normal userspace bump their > priorities, or we can use the average context runtime to try and adjust > priorities on the fly (i.e. do not used an unbias quota). But I suspect > removing any fairness will skew the scheduler once more. OK, also for future reference, it would be good to have at least a subset of this documented somewhere! Thanks, Thomas > -Chris From chris at chris-wilson.co.uk Tue Jun 16 12:44:29 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 13:44:29 +0100 Subject: [Intel-gfx] [PATCH 26/28] drm/i915: Fair low-latency scheduling In-Reply-To: <623f4f89-1377-d18d-f611-7126a08ec85c@shipmail.org> References: <20200607222108.14401-1-chris@chris-wilson.co.uk> <20200607222108.14401-26-chris@chris-wilson.co.uk> <5a7ebfbc-665b-eff6-d969-7d27b568f161@shipmail.org> <159230237587.18308.5225913549750961471@build.alporthouse.com> <623f4f89-1377-d18d-f611-7126a08ec85c@shipmail.org> Message-ID: <159231146971.18853.4423648105222638065@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-16 13:11:25) > Hi, > > On 6/16/20 12:12 PM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-16 10:07:28) > >> Hi, Chris, > >> > >> Some comments and questions: > >> > >> On 6/8/20 12:21 AM, Chris Wilson wrote: > >>> The first "scheduler" was a topographical sorting of requests into > >>> priority order. The execution order was deterministic, the earliest > >>> submitted, highest priority request would be executed first. Priority > >>> inherited ensured that inversions were kept at bay, and allowed us to > >>> dynamically boost priorities (e.g. for interactive pageflips). > >>> > >>> The minimalistic timeslicing scheme was an attempt to introduce fairness > >>> between long running requests, by evicting the active request at the end > >>> of a timeslice and moving it to the back of its priority queue (while > >>> ensuring that dependencies were kept in order). For short running > >>> requests from many clients of equal priority, the scheme is still very > >>> much FIFO submission ordering, and as unfair as before. > >>> > >>> To impose fairness, we need an external metric that ensures that clients > >>> are interpersed, we don't execute one long chain from client A before > >>> executing any of client B. This could be imposed by the clients by using > >>> a fences based on an external clock, that is they only submit work for a > >>> "frame" at frame-interval, instead of submitting as much work as they > >>> are able to. The standard SwapBuffers approach is akin to double > >>> bufferring, where as one frame is being executed, the next is being > >>> submitted, such that there is always a maximum of two frames per client > >>> in the pipeline. Even this scheme exhibits unfairness under load as a > >>> single client will execute two frames back to back before the next, and > >>> with enough clients, deadlines will be missed. > >>> > >>> The idea introduced by BFS/MuQSS is that fairness is introduced by > >>> metering with an external clock. Every request, when it becomes ready to > >>> execute is assigned a virtual deadline, and execution order is then > >>> determined by earliest deadline. Priority is used as a hint, rather than > >>> strict ordering, where high priority requests have earlier deadlines, > >>> but not necessarily earlier than outstanding work. Thus work is executed > >>> in order of 'readiness', with timeslicing to demote long running work. > >>> > >>> The Achille's heel of this scheduler is its strong preference for > >>> low-latency and favouring of new queues. Whereas it was easy to dominate > >>> the old scheduler by flooding it with many requests over a short period > >>> of time, the new scheduler can be dominated by a 'synchronous' client > >>> that waits for each of its requests to complete before submitting the > >>> next. As such a client has no history, it is always considered > >>> ready-to-run and receives an earlier deadline than the long running > >>> requests. > >>> > >>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>> --- > >>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 +- > >>> .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 1 + > >>> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +- > >>> drivers/gpu/drm/i915/gt/intel_engine_types.h | 24 -- > >>> drivers/gpu/drm/i915/gt/intel_lrc.c | 328 +++++++----------- > >>> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 5 +- > >>> drivers/gpu/drm/i915/gt/selftest_lrc.c | 43 ++- > >>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- > >>> drivers/gpu/drm/i915/i915_priolist_types.h | 7 +- > >>> drivers/gpu/drm/i915/i915_request.h | 4 +- > >>> drivers/gpu/drm/i915/i915_scheduler.c | 322 ++++++++++++----- > >>> drivers/gpu/drm/i915/i915_scheduler.h | 22 +- > >>> drivers/gpu/drm/i915/i915_scheduler_types.h | 17 + > >>> .../drm/i915/selftests/i915_mock_selftests.h | 1 + > >>> drivers/gpu/drm/i915/selftests/i915_request.c | 1 + > >>> .../gpu/drm/i915/selftests/i915_scheduler.c | 49 +++ > >>> 16 files changed, 484 insertions(+), 362 deletions(-) > >>> create mode 100644 drivers/gpu/drm/i915/selftests/i915_scheduler.c > >> Do we have timings to back this change up? Would it make sense to have a > >> configurable scheduler choice? > > Yes, there's igt/benchmarks/gem_wsim to show the impact on scheduling > > decisions for various workloads. (You can guess what the impact of > > choosing a different execution order and forcing more context switches > > will be... About -1% to throughput with multiple clients) And > > igt/tests/gem_exec_schedule to test basic properties, with a bunch of new > > fairness tests to try and decide if this is the right thing. Under > > saturated conditions, there is no contest, a fair scheduler produces > > consistent results, and the vdeadlines allow for realtime-response under > > load. > > Yeah, it's not really to convince me, but to provide a reference for the > future. > > Perhaps add the gem_wsim timings to the commit message? I don't like posting such benchmarks without saying how they can be reproduced or providing absolute values to verify future runs. Our rules are terrible. This trimmed down set takes about a day to run, and we've yet to convince people that this is a fundamental requirement for CI. So it's really frustrating, the best we can try and do is distill essential requirements into a pass/fair test to be run on debug kernels. At least we cover the pathological exploits, except for where they are so bad CI complains for them taking too long. > >> There are multiple introductions of ktime_get() in the patch. Perhaps > >> use monotonic clock source like ktime_get_raw()? Also immediately > >> convert to ns. > > ktime_get() is monotonic. The only difference is that tkr_mono has an > > wall-offset that tkr_raw does not. [I'm sure there's a good reason.] The > > choice is really whether ktime_get_(mono|raw)_fast_ns() is sufficient for > > our needs. > > Hmm. Yes you're right. I was thinking about the NTP adjustments. But > given the requirement below they might be unimportant. I never know which is the right one to use :| Just follow the guideline that the shortest function name is the intended one to use, unless you understand why you should use one of the others. > > I do like the idea of having the deadline being some recognisable > > timestamp, as it makes it easier to play with mixing in real, albeit > > soft, deadlines. > > > > > >>> @@ -2837,10 +2788,7 @@ static void __execlists_unhold(struct i915_request *rq) > >>> GEM_BUG_ON(!i915_sw_fence_signaled(&rq->submit)); > >>> > >>> i915_request_clear_hold(rq); > >>> - list_move_tail(&rq->sched.link, > >>> - i915_sched_lookup_priolist(rq->engine, > >>> - rq_prio(rq))); > >>> - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); > >>> + submit |= intel_engine_queue_request(rq->engine, rq); > >> As new to this codebase, I immediately wonder whether that bitwise or is > >> intentional and whether you got the short-circuiting right. It looks > >> correct to me. > > bool submit, not many bits :) > > Yes, the code is correct. My question was related to whether it was > accepted practice, considering a future reader may think it might have > been a mistake and change it anyway.... submit |= vs if () submit = true I feel I have used both variants in this patch. > >>> { > >>> /* > >>> * When in use during submission, we are protected by a guarantee that > >>> diff --git a/drivers/gpu/drm/i915/i915_scheduler.c b/drivers/gpu/drm/i915/i915_scheduler.c > >>> index 4c189b81cc62..30bcb6f9d99f 100644 > >>> --- a/drivers/gpu/drm/i915/i915_scheduler.c > >>> +++ b/drivers/gpu/drm/i915/i915_scheduler.c > >>> @@ -20,6 +20,11 @@ static struct i915_global_scheduler { > >>> static DEFINE_SPINLOCK(ipi_lock); > >>> static LIST_HEAD(ipi_list); > >>> > >>> +static inline u64 rq_deadline(const struct i915_request *rq) > >>> +{ > >>> + return READ_ONCE(rq->sched.deadline); > >>> +} > >>> + > >> Does this need a release barrier paired with an acquire barrier in > >> __i915_request_set_deadline below? > > No, the state can be inconsistent. If it changes as we are processing > > the previous value, there will be another reschedule. Within > > set_deadline, rq->sched.deadline is under the engine->active.lock, it is > > just that rq_deadline() is used to peek before we take the lock, as well > > as shorthand within the critical section. > > > > OK, understood. > > > >>> +static u64 prio_slice(int prio) > >>> { > >>> - const struct i915_request *inflight; > >>> + u64 slice; > >>> + int sf; > >>> > >>> /* > >>> - * We only need to kick the tasklet once for the high priority > >>> - * new context we add into the queue. > >>> + * With a 1ms scheduling quantum: > >>> + * > >>> + * MAX USER: ~32us deadline > >>> + * 0: ~16ms deadline > >>> + * MIN_USER: 1000ms deadline > >>> */ > >>> - if (prio <= engine->execlists.queue_priority_hint) > >>> - return; > >>> > >>> - rcu_read_lock(); > >>> + if (prio >= __I915_PRIORITY_KERNEL__) > >>> + return INT_MAX - prio; > >>> > >>> - /* Nothing currently active? We're overdue for a submission! */ > >>> - inflight = execlists_active(&engine->execlists); > >>> - if (!inflight) > >>> - goto unlock; > >>> + slice = __I915_PRIORITY_KERNEL__ - prio; > >>> + if (prio >= 0) > >>> + sf = 20 - 6; > >>> + else > >>> + sf = 20 - 1; > >>> + > >>> + return slice << sf; > >>> +} > >>> + > >> Is this the same deadline calculation as used in the BFS? Could you > >> perhaps add a pointer to some documentation? > > It is a heuristic. The scale factor in BFS is designed for a smaller > > range and is not effective for passing our existing priority ordering > > tests. > > > > The challenge is to pick something that is fair that roughly matches > > usage. It basically says that if client A submits 3 requests, then > > client B, C will be able to run before the later requests of client A so > > long as they are submitted within 16ms. Currently we get AAABC, > > the vdeadlines turn that into ABCAA. So we would ideally like the quota > > for each client to reflect their needs, so if client A needed all 3 > > requests within 16ms, it would have a vdeadline closer to 5ms (and so it > > would compete for the GPU against other clients). Now with this less > > strict priority system we can let normal userspace bump their > > priorities, or we can use the average context runtime to try and adjust > > priorities on the fly (i.e. do not used an unbias quota). But I suspect > > removing any fairness will skew the scheduler once more. > > OK, also for future reference, it would be good to have at least a > subset of this documented somewhere! Yeah. I think prio_slice is the best spot to try and explain why different priorities have different quotas, and the impact. -Chris From ramadevi.gandi at intel.com Tue Jun 16 12:37:58 2020 From: ramadevi.gandi at intel.com (ramadevi.gandi at intel.com) Date: Tue, 16 Jun 2020 18:07:58 +0530 Subject: [Intel-gfx] [PATCH libdrm] intel: sync i915_pciids.h with kernel Message-ID: <20200616123758.3331-1-ramadevi.gandi@intel.com> From: Gandi Ramadevi <ramadevi.gandi at intel.com> Add DG1 PCI ID Signed-off-by: Gandi Ramadevi <ramadevi.gandi at intel.com> --- intel/i915_pciids.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h index 662d8351..724e68a0 100644 --- a/intel/i915_pciids.h +++ b/intel/i915_pciids.h @@ -605,4 +605,9 @@ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) +/* DG1 */ +#define INTEL_DG1_IDS(info) \ + INTEL_VGA_DEVICE(0x4905, info), \ + INTEL_VGA_DEVICE(0x4906, info) + #endif /* _I915_PCIIDS_H */ -- 2.25.1 From emil.l.velikov at gmail.com Tue Jun 16 13:54:01 2020 From: emil.l.velikov at gmail.com (Emil Velikov) Date: Tue, 16 Jun 2020 14:54:01 +0100 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <CAKMK7uEEkH+8BuFcFUVTv6p8swZZTwcho-HNx5GdZTO1vHDoeg@mail.gmail.com> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-7-daniel.vetter@ffwll.ch> <CACvgo51AVVOxhGK2Uin=ZLgPpihJiEsnc6pvAyKqFKPvLdOzLA@mail.gmail.com> <CAKMK7uEEkH+8BuFcFUVTv6p8swZZTwcho-HNx5GdZTO1vHDoeg@mail.gmail.com> Message-ID: <CACvgo51ZObyCiOeV+cdJo6xJ3ahuvBUxx1DrK+emDHTOfmVA_g@mail.gmail.com> On Tue, 16 Jun 2020 at 07:50, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > On Mon, Jun 15, 2020 at 11:35 PM Emil Velikov <emil.l.velikov at gmail.com> wrote: > > > > Hi Daniel, > > > > On Fri, 12 Jun 2020 at 17:01, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > > > The atomic helpers try really hard to not lose track of things, > > > duplicating enabled tracking in the driver is at best confusing. > > > Double-enabling or disabling is a bug in atomic helpers. > > > > > > In the fb_dirty function we can just assume that the fb always exists, > > > simple display pipe helpers guarantee that the crtc is only enabled > > > together with the output, so we always have a primary plane around. > > > > > > Now in the update function we need to be a notch more careful, since > > > that can also get called when the crtc is off. And we don't want to > > > upload frames when that's the case, so filter that out too. > > > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > Cc: Maxime Ripard <mripard at kernel.org> > > > Cc: Thomas Zimmermann <tzimmermann at suse.de> > > > Cc: David Airlie <airlied at linux.ie> > > > Cc: Daniel Vetter <daniel at ffwll.ch> > > > Cc: David Lechner <david at lechnology.com> > > > --- > > > drivers/gpu/drm/drm_mipi_dbi.c | 16 ++++++---------- > > > drivers/gpu/drm/tiny/ili9225.c | 12 +++--------- > > > drivers/gpu/drm/tiny/st7586.c | 11 +++-------- > > > include/drm/drm_mipi_dbi.h | 5 ----- > > > 4 files changed, 12 insertions(+), 32 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c > > > index fd8d672972a9..79532b9a324a 100644 > > > --- a/drivers/gpu/drm/drm_mipi_dbi.c > > > +++ b/drivers/gpu/drm/drm_mipi_dbi.c > > > @@ -268,7 +268,7 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) > > > bool full; > > > void *tr; > > > > > > - if (!dbidev->enabled) > > > + if (WARN_ON(!fb)) > > > return; > > > > > AFAICT no other driver has such WARN_ON. Let's drop that - it is > > pretty confusing and misleading as-is. > > Yeah, this is a helper library which might be used wrongly by drivers. > That's why I put it in - if you don't put all the various calls > together correctly, this should at least catch one case. So really > would like to keep this, can I convince you? There are plenty of similar places where a drm library/helper can be misused, lacking a WARN. Nevertheless - sure feel free to keep it. -Emil From imre.deak at intel.com Tue Jun 16 14:18:50 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 17:18:50 +0300 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders Message-ID: <20200616141855.746-1-imre.deak@intel.com> MST encoders must use the master MST transcoder's DP_TP_STATUS and DP_TP_CONTROL registers. Atm, during the HW readout of a slave transcoder's CRTC state we reset these register addresses in intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register addresses incorrectly; fix this. This issue led at least to 'Timed out waiting for ACT sent when disabling' errors during output disabling in a multiple MST stream config. This change replaces https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 which just papered over the problem. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..73d6cc29291a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) return; - if (INTEL_GEN(dev_priv) >= 12) { - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); - } - intel_dsc_get_config(encoder, pipe_config); temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, break; } + if (INTEL_GEN(dev_priv) >= 12) { + enum transcoder transcoder = + intel_dp_mst_is_slave_trans(pipe_config) ? + pipe_config->mst_master_transcoder : + pipe_config->cpu_transcoder; + + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); + } + pipe_config->has_audio = intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); -- 2.23.1 From imre.deak at intel.com Tue Jun 16 14:18:51 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 17:18:51 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <20200616141855.746-2-imre.deak@intel.com> We calculate the MST available bandwidth using the link's maximum rate and lane count. This bandwidth won't be recalculated in response to a link training error and fallback setting, so modesets following a link training error will calculate incorrect timing parameters (like the transcoder's data M/N params or the number of MST TUs). Prevent the above problem by disabling the link training fallback on MST links for now, until the MST compute config can deal with changing link parameters. The misconfigured timing lead at least to a 'Timed out waiting for DP idle patterns' error. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Manasi Navare <manasi.d.navare at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..c585b002783a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -468,6 +468,13 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, struct drm_i915_private *i915 = dp_to_i915(intel_dp); int index; + /* + * TODO: Enable fallback on MST links once MST link compute can handle + * the fallback params. + */ + if (intel_dp->is_mst) + return -1; + index = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, link_rate); @@ -6163,7 +6170,17 @@ intel_dp_detect(struct drm_connector *connector, goto out; } - if (intel_dp->reset_link_params) { + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ + if (INTEL_GEN(dev_priv) >= 11) + intel_dp_get_dsc_sink_cap(intel_dp); + + intel_dp_configure_mst(intel_dp); + + /* + * TODO: Reset link params when switching to MST mode, until MST + * supports link training fallback params. + */ + if (intel_dp->reset_link_params || intel_dp->is_mst) { /* Initial max link lane count */ intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); @@ -6175,12 +6192,6 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_print_rates(intel_dp); - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ - if (INTEL_GEN(dev_priv) >= 11) - intel_dp_get_dsc_sink_cap(intel_dp); - - intel_dp_configure_mst(intel_dp); - if (intel_dp->is_mst) { /* * If we are in MST mode then this connector -- 2.23.1 From imre.deak at intel.com Tue Jun 16 14:18:53 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 17:18:53 +0300 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/dp_mst: Clear only the ACT sent flag from DP_TP_STATUS In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <20200616141855.746-4-imre.deak@intel.com> It's not clear if the DP_TP_STATUS flags other than the ACT sent flag have some side-effect, so don't clear those; we don't depend on the state of these flags anyway. Suggested-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 3977ee4f7176..b66b56a070e5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -322,7 +322,7 @@ static void clear_act_sent(struct intel_dp *intel_dp) struct drm_i915_private *i915 = dp_to_i915(intel_dp); intel_de_write(i915, intel_dp->regs.dp_tp_status, - intel_de_read(i915, intel_dp->regs.dp_tp_status)); + DP_TP_STATUS_ACT_SENT); } static void wait_for_act_sent(struct intel_dp *intel_dp) -- 2.23.1 From imre.deak at intel.com Tue Jun 16 14:18:52 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 17:18:52 +0300 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <20200616141855.746-3-imre.deak@intel.com> During transcoder enabling we'll configure the transcoder in MST mode and enable the VC payload allocation, which will start the ACT sequence. Before waiting for the ACT sequence completion, we need to clear the ACT sent flag, but based on the above we can do this right before enabling the transcoder. For clarity, move the flag clearing closer to where we wait for it. While at it also factor out some common code. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 36 +++++++++++++-------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2e6c6375a23b..3977ee4f7176 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -317,6 +317,25 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, return ret; } +static void clear_act_sent(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + intel_de_write(i915, intel_dp->regs.dp_tp_status, + intel_de_read(i915, intel_dp->regs.dp_tp_status)); +} + +static void wait_for_act_sent(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (intel_de_wait_for_set(i915, intel_dp->regs.dp_tp_status, + DP_TP_STATUS_ACT_SENT, 1)) + drm_err(&i915->drm, "Timed out waiting for ACT sent\n"); + + drm_dp_check_act_status(&intel_dp->mst_mgr); +} + static void intel_mst_disable_dp(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, @@ -377,11 +396,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), val); - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, - DP_TP_STATUS_ACT_SENT, 1)) - drm_err(&dev_priv->drm, - "Timed out waiting for ACT sent when disabling\n"); - drm_dp_check_act_status(&intel_dp->mst_mgr); + wait_for_act_sent(intel_dp); drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); @@ -452,7 +467,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, struct intel_connector *connector = to_intel_connector(conn_state->connector); int ret; - u32 temp; bool first_mst_stream; /* MST encoders are bound to a crtc, not to a connector, @@ -485,8 +499,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); intel_dp->active_mst_links++; - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); @@ -517,16 +529,14 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); + clear_act_sent(intel_dp); + intel_ddi_enable_transcoder_func(encoder, pipe_config); drm_dbg_kms(&dev_priv->drm, "active links %d\n", intel_dp->active_mst_links); - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, - DP_TP_STATUS_ACT_SENT, 1)) - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); - - drm_dp_check_act_status(&intel_dp->mst_mgr); + wait_for_act_sent(intel_dp); drm_dp_update_payload_part2(&intel_dp->mst_mgr); -- 2.23.1 From imre.deak at intel.com Tue Jun 16 14:18:54 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 17:18:54 +0300 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <20200616141855.746-5-imre.deak@intel.com> During encoder enabling we clear the flag before starting the ACT sequence and wait for the flag, but the clearing is missing during encoder disabling, add it there too. Since nothing cleared the flag automatically we could've run subsequent disabling steps too early. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b66b56a070e5..9308b5920780 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -389,6 +389,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, drm_dp_update_payload_part2(&intel_dp->mst_mgr); + clear_act_sent(intel_dp); + val = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder)); val &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; -- 2.23.1 From imre.deak at intel.com Tue Jun 16 14:18:55 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 17:18:55 +0300 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <20200616141855.746-6-imre.deak@intel.com> Atm, we clear the ACT sent flag in the sink's DPCD before updating the sink's payload table, along clearing the payload table updated flag. The sink is supposed to set this flag once it detects that the source has completed the ACT sequence (after detecting the 4 required ACT MTPH symbols sent by the source). As opposed to this 2 DELL monitors I have set the flag already along the payload table updated flag, which is not quite correct. To be sure that the sink has detected the ACT MTPH symbols before continuing enabling the encoder, clear the ACT sent flag before enabling or disabling the transcoder VC payload allocation (which is what starts the ACT sequence). Cc: Lyude Paul <lyude at redhat.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: dri-devel at lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 31 +++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ include/drm/drm_dp_mst_helper.h | 2 ++ 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index b2f5a84b4cfb..e3bf8c9c8267 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -4377,6 +4377,34 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, } EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); +/** + * drm_dp_clear_payload_status() - Clears the payload table status flags + * @mgr: manager to use + * + * Clears the payload table ACT handled and table updated flags in the MST hub's + * DPCD. This function must be called before updating the payload table or + * starting the ACT sequence and waiting for the corresponding flags to get + * set by the hub. + * + * Returns: + * 0 if the flag got cleared successfully, otherwise a negative error code. + */ +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) +{ + int ret; + + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, + DP_PAYLOAD_ACT_HANDLED); + if (ret < 0) { + DRM_DEBUG_DRIVER("Can't clear the ACT sent flag (%d)\n", ret); + return ret; + } + WARN_ON(ret != 1); + + return 0; +} +EXPORT_SYMBOL(drm_dp_clear_payload_status); + static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload) { @@ -4384,8 +4412,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, int ret; int retries = 0; - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, - DP_PAYLOAD_TABLE_UPDATED); + drm_dp_clear_payload_status(mgr); payload_alloc[0] = id; payload_alloc[1] = payload->start_slot; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 9308b5920780..3c4b0fb10d8b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) intel_de_write(i915, intel_dp->regs.dp_tp_status, DP_TP_STATUS_ACT_SENT); + + drm_dp_clear_payload_status(&intel_dp->mst_mgr); } static void wait_for_act_sent(struct intel_dp *intel_dp) diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 8b9eb4db3381..2facb87624bf 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, int pbn); +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); + int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); -- 2.23.1 From mika.kuoppala at linux.intel.com Tue Jun 16 14:23:23 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 17:23:23 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Exercise far preemption rollbacks In-Reply-To: <20200615201406.19286-1-chris@chris-wilson.co.uk> References: <20200615200603.18827-1-chris@chris-wilson.co.uk> <20200615201406.19286-1-chris@chris-wilson.co.uk> Message-ID: <87y2on84ys.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Not too long ago, we realised we had issues with a rolling back a > context so far for a preemption request we considered the resubmit not > to be a rollback but a forward roll. This means we would issue a lite > restore instead of forcing a full restore, continuing execution of the > old requests rather than causing a preemption. Add a selftest to > exercise such a far rollback, such that if we were to skip the full > restore, we would execute invalid instructions in the ring and hang. > > Note that while I was able to confirm that this causes us to do a > lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: > Incrementally check for rewinding") disabled), it did not trick the HW > into rolling past the old RING_TAIL. Myybe on other HW. s/Myybe/Maybe. > > References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 150 +++++++++++++++++++++++++ > 1 file changed, 150 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index 91543494f595..3d088116a055 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -363,6 +363,155 @@ static int live_unlite_preempt(void *arg) > return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); > } > > +static int live_unlite_ring(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + struct igt_spinner spin; > + enum intel_engine_id id; > + int err = 0; > + > + /* > + * Setup a preemption event that will cause almost the entire ring > + * to be unwound, potentially fooling our intel_ring_direction() > + * into emitting a forward lite-restore instead of the rollback. > + */ > + > + if (igt_spinner_init(&spin, gt)) > + return -ENOMEM; > + > + for_each_engine(engine, gt, id) { > + struct intel_context *ce[2] = {}; > + struct i915_request *rq; > + struct igt_live_test t; > + int n; > + > + if (!intel_engine_has_preemption(engine)) > + continue; > + > + if (!intel_engine_can_store_dword(engine)) > + continue; > + > + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { > + err = -EIO; > + break; > + } > + engine_heartbeat_disable(engine); > + > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + struct intel_context *tmp; > + > + tmp = intel_context_create(engine); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + goto err_ce; > + } > + > + err = intel_context_pin(tmp); > + if (err) { > + intel_context_put(tmp); > + goto err_ce; > + } > + > + memset32(tmp->ring->vaddr, > + 0xdeadbeef, /* trigger a hang if executed */ > + tmp->ring->vma->size / sizeof(u32)); > + > + ce[n] = tmp; > + } > + > + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + i915_request_get(rq); > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; I missed this on reading and was very lost in the woods. Chris kindly explained the scheduling steps, in short: This makes both contexts first requests to be equal prio and causes the ce[0] ring tail manipulation to happen back and forth, when the spinner is released. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > + i915_request_add(rq); > + > + if (!igt_wait_for_spinner(&spin, rq)) { > + intel_gt_set_wedged(gt); > + i915_request_put(rq); > + err = -ETIME; > + goto err_ce; > + } > + > + /* Fill the ring, until we will cause a wrap */ > + n = 0; > + while (intel_ring_direction(ce[0]->ring, > + rq->wa_tail, > + ce[0]->ring->tail) <= 0) { > + struct i915_request *tmp; > + > + tmp = intel_context_create_request(ce[0]); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + i915_request_put(rq); > + goto err_ce; > + } > + > + i915_request_add(tmp); > + intel_engine_flush_submission(engine); > + n++; > + } > + intel_engine_flush_submission(engine); > + pr_debug("%s: Filled ring with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", > + engine->name, n, > + ce[0]->ring->size, > + ce[0]->ring->tail, > + ce[0]->ring->emit, > + rq->tail); > + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, > + rq->tail, > + ce[0]->ring->tail) <= 0); > + i915_request_put(rq); > + > + /* Create a second request to preempt the first ring */ > + rq = intel_context_create_request(ce[1]); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > + i915_request_get(rq); > + i915_request_add(rq); > + > + err = wait_for_submit(engine, rq, HZ / 2); > + i915_request_put(rq); > + if (err) { > + pr_err("%s: preemption request was not submited\n", > + engine->name); > + err = -ETIME; > + } > + > + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", > + engine->name, > + ce[0]->ring->tail, ce[0]->ring->emit, > + ce[1]->ring->tail, ce[1]->ring->emit); > + > +err_ce: > + intel_engine_flush_submission(engine); > + igt_spinner_end(&spin); > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + if (IS_ERR_OR_NULL(ce[n])) > + break; > + > + intel_context_unpin(ce[n]); > + intel_context_put(ce[n]); > + } > + engine_heartbeat_enable(engine); > + if (igt_live_test_end(&t)) > + err = -EIO; > + if (err) > + break; > + } > + > + igt_spinner_fini(&spin); > + return err; > +} > + > static int live_pin_rewind(void *arg) > { > struct intel_gt *gt = arg; > @@ -4374,6 +4523,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) > SUBTEST(live_sanitycheck), > SUBTEST(live_unlite_switch), > SUBTEST(live_unlite_preempt), > + SUBTEST(live_unlite_ring), > SUBTEST(live_pin_rewind), > SUBTEST(live_hold_reset), > SUBTEST(live_error_interrupt), > -- > 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 14:53:27 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 15:53:27 +0100 Subject: [Intel-gfx] [PATCH][next] drm/i915/selftests: Fix inconsistent IS_ERR and PTR_ERR In-Reply-To: <20200616145452.GA25291@embeddedor> References: <20200616145452.GA25291@embeddedor> Message-ID: <159231920737.18853.4543157798745594821@build.alporthouse.com> Quoting Gustavo A. R. Silva (2020-06-16 15:54:52) > Fix inconsistent IS_ERR and PTR_ERR in live_timeslice_nopreempt(). > > The proper pointer to be passed as argument to PTR_ERR() is ce. > > This bug was detected with the help of Coccinelle. > > Fixes: b72f02d78e4f ("drm/i915/gt: Prevent timeslicing into unpreemptable requests") > Signed-off-by: Gustavo A. R. Silva <gustavoars at kernel.org> Fair enough, I had sent out a patch that included this, but never split it out for early adoption. Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From gwan-gyeong.mun at intel.com Tue Jun 16 15:16:41 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Tue, 16 Jun 2020 15:16:41 +0000 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch In-Reply-To: <20200615164024.GQ6112@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-5-jose.souza@intel.com> <20200612163029.GK6112@intel.com> <ee0340f8ea128ed2caa4a6882ded6cb28bf0d8d9.camel@intel.com> <20200615164024.GQ6112@intel.com> Message-ID: <421d8bd4ac0456ac448839194d535777424e6589.camel@intel.com> On Mon, 2020-06-15 at 19:40 +0300, Ville Syrj?l? wrote: > On Fri, Jun 12, 2020 at 08:33:31PM +0000, Souza, Jose wrote: > > On Fri, 2020-06-12 at 19:30 +0300, Ville Syrj?l? wrote: > > > On Tue, May 26, 2020 at 03:14:46PM -0700, Jos? Roberto de Souza > > > wrote: > > > > All GEN12 platforms supports PSR2 selective fetch but not all > > > > GEN12 > > > > platforms supports PSR2 hardware tracking(aka RKL). > > > > > > > > This feature consists in software program registers with the > > > > damaged > > > > area of each plane this way hardware will only fetch from > > > > memory those > > > > areas and sent the PSR2 selective update blocks to panel, > > > > saving even > > > > more power but to it actually happen userspace needs to send > > > > the > > > > damaged areas otherwise it will still fetch the whole plane as > > > > fallback. > > > > As today Gnome3 do not send damaged areas and the only > > > > compositor that > > > > I'm aware that sets the damaged areas is Weston. > > > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > > > > > > > So here implementing page flip part, it is still completely > > > > missing > > > > frontbuffer modifications, that is why the > > > > enable_psr2_sel_fetch > > > > parameter was added. > > > > > > > > The plan is to switch all GEN12 platforms to selective fetch > > > > when > > > > ready, it will also depend in add some tests sending damaged > > > > areas. > > > > I have a hacked version of kms_psr2_su with 3 planes that I can > > > > cleanup and send in a few days(99% of PSR2 selective fetch > > > > changes was > > > > done during my free time while bored during quarantine rainy > > > > days). > > > > > > > > BSpec: 55229 > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Cc: Imre Deak <imre.deak at intel.com> > > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > > > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_display.c | 5 + > > > > .../drm/i915/display/intel_display_debugfs.c | 3 + > > > > .../drm/i915/display/intel_display_types.h | 10 + > > > > drivers/gpu/drm/i915/display/intel_psr.c | 329 > > > > +++++++++++++++++- > > > > drivers/gpu/drm/i915/display/intel_psr.h | 10 + > > > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 + > > > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > > > drivers/gpu/drm/i915/i915_params.c | 5 + > > > > drivers/gpu/drm/i915/i915_params.h | 1 + > > > > 9 files changed, 352 insertions(+), 15 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > index b69878334040..984809208c29 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > @@ -11729,6 +11729,8 @@ static void i9xx_update_cursor(struct > > > > intel_plane *plane, > > > > if (INTEL_GEN(dev_priv) >= 9) > > > > skl_write_cursor_wm(plane, crtc_state); > > > > > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, > > > > plane_state); > > > > + > > > > if (plane->cursor.base != base || > > > > plane->cursor.size != fbc_ctl || > > > > plane->cursor.cntl != cntl) { > > > > @@ -15115,6 +15117,8 @@ static void commit_pipe_config(struct > > > > intel_atomic_state *state, > > > > > > > > if (new_crtc_state->update_pipe) > > > > intel_pipe_fastset(old_crtc_state, > > > > new_crtc_state); > > > > + > > > > + intel_psr2_program_trans_man_trk_ctl(new_crtc_s > > > > tate); > > > > } > > > > > > > > if (dev_priv->display.atomic_update_watermarks) > > > > @@ -15156,6 +15160,7 @@ static void intel_update_crtc(struct > > > > intel_atomic_state *state, > > > > intel_color_load_luts(new_crtc_state); > > > > > > > > intel_pre_plane_update(state, crtc); > > > > + intel_psr2_sel_fetch_update(state, crtc); > > > > > > > > if (new_crtc_state->update_pipe) > > > > intel_encoders_update_pipe(state, > > > > crtc); > > > > diff --git > > > > a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > index 70525623bcdf..0f600974462b 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct > > > > seq_file *m, void *data) > > > > su_blocks = su_blocks >> > > > > PSR2_SU_STATUS_SHIFT(frame); > > > > seq_printf(m, "%d\t%d\n", frame, > > > > su_blocks); > > > > } > > > > + > > > > + seq_printf(m, "PSR2 selective fetch: %s\n", > > > > + enableddisabled(psr- > > > > >psr2_sel_fetch_enabled)); > > > > } > > > > > > > > unlock: > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > index 30b2767578dc..b77a512e5362 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > @@ -586,6 +586,13 @@ struct intel_plane_state { > > > > u32 planar_slave; > > > > > > > > struct drm_intel_sprite_colorkey ckey; > > > > + > > > > + struct { > > > > + u32 ctl; > > > > + u32 pos; > > > > + u32 offset; > > > > + u32 size; > > > > + } psr2_sel_fetch; > > > > > > Do we really need all that here? We don't store them for the > > > normal > > > plane updates either. > > > > For ctl we do, anyways could be removed if we store overlapping > > damage are in here so intel_psr2_program_plane_sel_fetch() would > > incorporate > > intel_psr2_plane_sel_fetch_calc() code, both looks good to me. > > > > > > }; > > > > > > > > struct intel_initial_plane_config { > > > > @@ -931,6 +938,7 @@ struct intel_crtc_state { > > > > > > > > bool has_psr; > > > > bool has_psr2; > > > > + bool enable_psr2_sel_fetch; > > > > u32 dc3co_exitline; > > > > > > > > /* > > > > @@ -1070,6 +1078,8 @@ struct intel_crtc_state { > > > > > > > > /* For DSB related info */ > > > > struct intel_dsb *dsb; > > > > + > > > > + u32 psr2_sw_man_track_ctl; > > > > }; > > > > > > > > enum intel_pipe_crc_source { > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > > index 0c86e9e341a2..bc2a2e64fe2a 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > > @@ -518,6 +518,14 @@ static void hsw_activate_psr2(struct > > > > intel_dp *intel_dp) > > > > else > > > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > > > > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > > > > + intel_de_write(dev_priv, > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > >psr.transcoder), > > > > + PSR2_MAN_TRK_CTL_ENABLE); > > > > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > > > > + intel_de_write(dev_priv, > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > >psr.transcoder), 0); > > > > + > > > > /* > > > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and > > > > BSpec is > > > > * recommending keep this bit unset while PSR2 is > > > > enabled. > > > > @@ -628,6 +636,38 @@ tgl_dc3co_exitline_compute_config(struct > > > > intel_dp *intel_dp, > > > > crtc_state->dc3co_exitline = crtc_vdisplay - > > > > exit_scanlines; > > > > } > > > > > > > > +static bool intel_psr2_sel_fetch_config_valid(struct intel_dp > > > > *intel_dp, > > > > + struct > > > > intel_crtc_state *crtc_state) > > > > +{ > > > > + struct intel_atomic_state *state = > > > > to_intel_atomic_state(crtc_state->uapi.state); > > > > + struct drm_i915_private *dev_priv = > > > > dp_to_i915(intel_dp); > > > > + struct intel_plane_state *plane_state; > > > > + struct intel_plane *plane; > > > > + int i; > > > > + > > > > + if (!i915_modparams.enable_psr2_sel_fetch) { > > > > + drm_dbg_kms(&dev_priv->drm, > > > > + "PSR2 sel fetch not enabled, > > > > disabled by parameter\n"); > > > > + return false; > > > > + } > > > > + > > > > + if (crtc_state->uapi.async_flip) { > > > > + drm_dbg_kms(&dev_priv->drm, > > > > + "PSR2 sel fetch not enabled, async > > > > flip enabled\n"); > > > > + return false; > > > > + } > > > > > > Not supported anyway. > > > > > > > + > > > > + for_each_new_intel_plane_in_state(state, plane, > > > > plane_state, i) { > > > > + if (plane_state->uapi.rotation != > > > > DRM_MODE_ROTATE_0) { > > > > + drm_dbg_kms(&dev_priv->drm, > > > > + "PSR2 sel fetch not > > > > enabled, plane rotated\n"); > > > > + return false; > > > > + } > > > > + } > > > > + > > > > + return crtc_state->enable_psr2_sel_fetch = true; > > > > +} > > > > + > > > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > > > struct intel_crtc_state > > > > *crtc_state) > > > > { > > > > @@ -697,22 +737,17 @@ static bool > > > > intel_psr2_config_valid(struct intel_dp *intel_dp, > > > > return false; > > > > } > > > > > > > > - /* > > > > - * Some platforms lack PSR2 HW tracking and instead > > > > require manual > > > > - * tracking by software. In this case, the driver is > > > > required to track > > > > - * the areas that need updates and program hardware to > > > > send selective > > > > - * updates. > > > > - * > > > > - * So until the software tracking is implemented, PSR2 > > > > needs to be > > > > - * disabled for platforms without PSR2 HW tracking. > > > > - */ > > > > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > > > > - drm_dbg_kms(&dev_priv->drm, > > > > - "No PSR2 HW tracking in the > > > > platform\n"); > > > > - return false; > > > > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > > > > + if > > > > (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > > > > + !HAS_PSR_HW_TRACKING(dev_priv)) { > > > > + drm_dbg_kms(&dev_priv->drm, > > > > + "PSR2 not enabled, > > > > selective fetch not valid and no HW tracking available\n"); > > > > + return false; > > > > + } > > > > } > > > > > > > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > psr_max_v) { > > > > + if (!crtc_state->enable_psr2_sel_fetch && > > > > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > psr_max_v)) { > > > > drm_dbg_kms(&dev_priv->drm, > > > > "PSR2 not enabled, resolution %dx%d > > > > > max supported %dx%d\n", > > > > crtc_hdisplay, crtc_vdisplay, > > > > @@ -863,6 +898,11 @@ static void intel_psr_enable_source(struct > > > > intel_dp *intel_dp, > > > > val |= EXITLINE_ENABLE; > > > > intel_de_write(dev_priv, > > > > EXITLINE(cpu_transcoder), val); > > > > } > > > > + > > > > + if (HAS_PSR_HW_TRACKING(dev_priv)) > > > > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, > > > > IGNORE_PSR2_HW_TRACKING, > > > > + dev_priv- > > > > >psr.psr2_sel_fetch_enabled ? > > > > + IGNORE_PSR2_HW_TRACKING : 0); > > > > } > > > > > > > > static void intel_psr_enable_locked(struct drm_i915_private > > > > *dev_priv, > > > > @@ -884,7 +924,7 @@ static void intel_psr_enable_locked(struct > > > > drm_i915_private *dev_priv, > > > > /* DC5/DC6 requires at least 6 idle frames */ > > > > val = > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > > > > dev_priv->psr.dc3co_exit_delay = val; > > > > - > > > > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state- > > > > >enable_psr2_sel_fetch; > > > > /* > > > > * If a PSR error happened and the driver is reloaded, > > > > the EDP_PSR_IIR > > > > * will still keep the error set even after the reset > > > > done in the > > > > @@ -1080,6 +1120,265 @@ static void > > > > psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) > > > > intel_psr_exit(dev_priv); > > > > } > > > > > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane > > > > *plane, > > > > + const struct > > > > intel_crtc_state *crtc_state, > > > > + const struct > > > > intel_plane_state *plane_state) > > > > +{ > > > > + struct drm_i915_private *dev_priv = to_i915(plane- > > > > >base.dev); > > > > + enum pipe pipe = plane->pipe; > > > > + > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > + !plane_state || > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > + return; > > > > + > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, > > > > plane->id), > > > > + plane_state->psr2_sel_fetch.ctl); > > > > + if (!plane_state->psr2_sel_fetch.ctl || plane->id == > > > > PLANE_CURSOR) > > > > + return; > > > > + > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, > > > > plane->id), > > > > + plane_state->psr2_sel_fetch.pos); > > > > + intel_de_write_fw(dev_priv, > > > > PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > > > > + plane_state->psr2_sel_fetch.offset); > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, > > > > plane->id), > > > > + plane_state->psr2_sel_fetch.size); > > > > +} > > > > + > > > > +void intel_psr2_program_trans_man_trk_ctl(const struct > > > > intel_crtc_state *crtc_state) > > > > +{ > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state- > > > > >uapi.crtc); > > > > + struct drm_i915_private *dev_priv = to_i915(crtc- > > > > >base.dev); > > > > + struct i915_psr *psr = &dev_priv->psr; > > > > + > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > + return; > > > > + > > > > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr- > > > > >transcoder), > > > > + crtc_state->psr2_sw_man_track_ctl); > > > > +} > > > > + > > > > +static void intel_psr2_plane_sel_fetch_calc(struct > > > > intel_plane_state *plane_state, > > > > + struct drm_rect > > > > *clip) > > > > +{ > > > > + int color_plane = plane_state->planar_linked_plane && > > > > !plane_state->planar_slave; > > > > + struct intel_plane *plane = to_intel_plane(plane_state- > > > > >uapi.plane); > > > > + u32 val; > > > > + > > > > + if (plane->id == PLANE_CURSOR) > > > > + return; > > > > + > > > > + val = (plane_state->color_plane[color_plane].y + clip- > > > > >y1) << 16; > > > > + val |= plane_state->color_plane[color_plane].x; > > > > + plane_state->psr2_sel_fetch.offset = val; > > > > + > > > > + val = (clip->y1 + plane_state->uapi.crtc_y) << 16; > > > > + val |= plane_state->uapi.crtc_x; > > > > + plane_state->psr2_sel_fetch.pos = val; > > > > + > > > > + /* Sizes are 0 based */ > > > > + val = (clip->y2 - clip->y1 - 1) << 16; > > > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - > > > > 1; > > > > + plane_state->psr2_sel_fetch.size = val; > > > > +} > > > > + > > > > +static void intel_psr2_trans_man_trk_ctl_calc(struct > > > > intel_crtc_state *crtc_state, > > > > + struct drm_rect > > > > *clip, > > > > + bool full_update) > > > > +{ > > > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE; > > > > + > > > > + if (full_update) { > > > > + val |= PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME; > > > > + goto exit; > > > > + } > > > > + > > > > + if (clip->y1 == -1) > > > > + goto exit; > > > > + > > > > + val |= PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE; > > > > + val |= PSR2_MAN_TRK_CTL_REGION_START_ADDR(clip->y1 / 4 > > > > + 1); > > > > + val |= > > > > PSR2_MAN_TRK_CTL_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + > > > > 1); > > > > +exit: > > > > + crtc_state->psr2_sw_man_track_ctl = val; > > > > +} > > > > + > > > > +static void intel_psr2_plane_sel_fetch_ctl_calc(struct > > > > intel_plane *plane, > > > > + struct > > > > intel_plane_state *plane_state, > > > > + bool enable) > > > > +{ > > > > + if (!enable) > > > > + plane_state->psr2_sel_fetch.ctl = 0; > > > > + else if (plane->id == PLANE_CURSOR) > > > > + plane_state->psr2_sel_fetch.ctl = plane- > > > > >cursor.cntl; > > > > + else > > > > + plane_state->psr2_sel_fetch.ctl = plane_state- > > > > >ctl; > > > > +} > > > > + > > > > +static void clip_update(struct drm_rect *overlap_damage_area, > > > > + struct drm_rect *damage_area) > > > > +{ > > > > + if (overlap_damage_area->y1 == -1) { > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > + return; > > > > + } > > > > + > > > > + if (damage_area->y1 < overlap_damage_area->y1) > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > + > > > > + if (damage_area->y2 > overlap_damage_area->y2) > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > +} > > > > + > > > > +/* Update plane damage area if planes above moved or have > > > > alpha */ > > > > +static void intel_psr2_pipe_dirty_areas_set(struct > > > > intel_plane_state *plane_state, > > > > + struct intel_plane > > > > *plane, > > > > + const struct > > > > drm_rect *pipe_dirty_areas, > > > > + struct drm_rect > > > > *plane_clip) > > > > +{ > > > > + enum plane_id i; > > > > + > > > > + for (i = PLANE_CURSOR; i > plane->id; i--) { > > > > + int j; > > > > + > > > > + for (j = 0; j < 2; j++) { > > > > + struct drm_rect r = pipe_dirty_areas[i > > > > * 2 + j]; > > > > + > > > > + if (!drm_rect_width(&r)) > > > > + continue; > > > > + if (!drm_rect_intersect(&r, > > > > &plane_state->uapi.dst)) > > > > + continue; > > > > + > > > > + r.y1 -= plane_state->uapi.crtc_y; > > > > + r.y2 -= plane_state->uapi.crtc_y; > > > > + clip_update(plane_clip, &r); > > > > + } > > > > + } > > > > +} > > > > + > > > > +void intel_psr2_sel_fetch_update(struct intel_atomic_state > > > > *state, > > > > + struct intel_crtc *crtc) > > > > +{ > > > > + struct intel_crtc_state *crtc_state = > > > > intel_atomic_get_new_crtc_state(state, crtc); > > > > + struct intel_plane_state *new_plane_state, > > > > *old_plane_state; > > > > + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = > > > > {}; > > > > + struct drm_rect pipe_clip = { .y1 = -1 }; > > > > + struct intel_plane *plane; > > > > + bool full_update = false; > > > > + int i; > > > > + > > > > + if (!crtc_state->enable_psr2_sel_fetch) > > > > + return; > > > > + > > > > + /* > > > > + * Load all the pipes areas where there is a plane with > > > > alpha or a plane > > > > + * that moved or plane that the visibility changed in > > > > those > > > > + * cases planes bellow it will need to be fetched in > > > > those intersection > > > > + * areas even if they are not damaged in those areas. > > > > + */ > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > old_plane_state, > > > > + new_plane_state, > > > > i) { > > > > + bool alpha, flip, dirty; > > > > + > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > >uapi.crtc) > > > > + continue; > > > > + > > > > + alpha = new_plane_state->uapi.alpha != U16_MAX; > > > > + alpha |= old_plane_state->uapi.alpha != > > > > U16_MAX; > > > > + flip = new_plane_state->uapi.fb != > > > > old_plane_state->uapi.fb; > > > > + dirty = alpha && flip; > > > > + dirty |= !drm_rect_equals(&new_plane_state- > > > > >uapi.dst, > > > > + &old_plane_state- > > > > >uapi.dst); > > > > + dirty |= new_plane_state->uapi.visible != > > > > + old_plane_state->uapi.visible; > > > > + if (!dirty) > > > > + continue; > > > > + > > > > + if (old_plane_state->uapi.visible) > > > > + pipe_dirty_areas[plane->id * 2] = > > > > old_plane_state->uapi.dst; > > > > + if (new_plane_state->uapi.visible) > > > > + pipe_dirty_areas[plane->id * 2 + 1] = > > > > new_plane_state->uapi.dst; > > > > + } > > > > + > > > > + /* > > > > + * Iterate over all planes, compute the damaged clip > > > > area also including > > > > + * the pipe_dirty_areas, compute plane registers and > > > > update pipe damaged > > > > + * area > > > > + */ > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > old_plane_state, > > > > + new_plane_state, > > > > i) { > > > > + struct drm_rect plane_clip = { .y1 = -1 }; > > > > + struct drm_mode_rect *clips; > > > > + u32 num_clips; > > > > + int j; > > > > + > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > >uapi.crtc) > > > > + continue; > > > > + > > > > + /* > > > > + * TODO: Not clear how to handle planes with > > > > negative position, > > > > + * also planes are not updated if they have a > > > > negative X > > > > + * position so for now doing a full update in > > > > this cases > > > > + */ > > > > + if (new_plane_state->uapi.crtc_y < 0 || > > > > + new_plane_state->uapi.crtc_x < 0) { > > > > + full_update = true; > > > > + break; > > > > + } > > > > + > > > > + intel_psr2_plane_sel_fetch_ctl_calc(plane, > > > > new_plane_state, > > > > + new_plane_s > > > > tate->uapi.visible); > > > > + if (!new_plane_state->uapi.visible) > > > > + continue; > > > > + > > > > + clips = > > > > drm_plane_get_damage_clips(&new_plane_state->uapi); > > > > + num_clips = > > > > drm_plane_get_damage_clips_count(&new_plane_state->uapi); > > > > + > > > > + /* > > > > + * If plane moved mark the whole plane area as > > > > damaged so it > > > > + * can be complete draw in the new position > > > > + */ > > > > + if (!drm_rect_equals(&new_plane_state- > > > > >uapi.dst, > > > > + &old_plane_state- > > > > >uapi.dst)) { > > > > + num_clips = 0; > > > > + plane_clip.y1 = new_plane_state- > > > > >uapi.src.y1 >> 16; > > > > + plane_clip.y2 = new_plane_state- > > > > >uapi.src.y2 >> 16; > > > > + } else if (!num_clips) { > > > > + /* > > > > + * If plane don't have damage areas but > > > > the framebuffer > > > > + * changed mark the whole plane as > > > > damaged > > > > + */ > > > > + if (new_plane_state->uapi.fb == > > > > old_plane_state->uapi.fb) > > > > + continue; > > > > + > > > > + plane_clip.y1 = new_plane_state- > > > > >uapi.src.y1 >> 16; > > > > + plane_clip.y2 = new_plane_state- > > > > >uapi.src.y2 >> 16; > > > > + } > > > > + > > > > + for (j = 0; j < num_clips; j++) { > > > > + struct drm_rect damage_area; > > > > + > > > > + damage_area.x1 = clips[j].x1; > > > > + damage_area.x2 = clips[j].x2; > > > > + damage_area.y1 = clips[j].y1; > > > > + damage_area.y2 = clips[j].y2; > > > > + clip_update(&plane_clip, &damage_area); > > > > + } > > > > + > > > > + intel_psr2_pipe_dirty_areas_set(new_plane_state > > > > , plane, > > > > + pipe_dirty_area > > > > s, &plane_clip); > > > > + intel_psr2_plane_sel_fetch_calc(new_plane_state > > > > , &plane_clip); > > > > + > > > > + plane_clip.y1 += new_plane_state->uapi.crtc_y; > > > > + plane_clip.y2 += new_plane_state->uapi.crtc_y; > > > > + clip_update(&pipe_clip, &plane_clip); > > > > + } > > > > > > This whole thing seems rather convoluted. Also using lots of uapi > > > state > > > in places where I don't expect to see any. > > > > Not sure from where I should get this information then, > > intel_plane_state don't have it. > > > > > I would suggest the correct way would be something like: > > > 1) for_each_plane_in_state() > > > hw.damage = > > > translate_to_some_hw_coord_space(union(uapi.damages)) > > > or just use the full plane size if we have scaling i guess > > > > 99% of the time the coordinates used are based on pipe coord space, > > only to calculate the plane overlapping damaged area is used plane > > coord space. > > > > > 2) need to add all affected planes to the state and set the > > > appropriate > > > bitmask, which may mean we want to track the planes' positions > > > in the > > > crtc state. I think atm we only have it in the plane state > > > > This looks a "or" to me, have all the planes added to the state > > when psr2 sel fetch is enabled or add track all the planes position > > in pipe. > > *Affected* planes, not all planes. Hmm. I guess affected planes are > actually the ones whose selective fetch coordinates change. If they > don't change then no need to add them to the state. Plane updates are > rather expensive (lots of mmio) so I've generally tried to avoid > pointless plane updates. > > But this whole thing might turn a bit annoying since we'd to keep > adding affected planes until the total selective fetch region stops > growing. I think that would probably want the two stage plane state > compuation. So just blindly adding all of them would probably be > simpler, albeit less efficient. > > > Although the second one would avoid us to do plane calculations and > > plane register sometimes, in some cases where a plane above a non- > > modified plane > > moves the non-modified plane bellow will need to be added to the > > state so the plane sel_fetch registers are written. > > We could go with the easy one(add all planes to the state) and then > > move to the second one latter. > > > > > 3) translate the damage further into the final plane src > > > coordinate > > > space. Dunno if we have enough state around still to do it > > > cleanly. > > > I was thinking maybe it could be done alongside all the other > > > plane > > > surface calculations, but there might be a chicken vs. egg > > > situation > > > here since we probably want to do the plane check stuff before > > > doing > > > step 1, but plane check is also where we do the surface > > > calculations. > > > Dunno if we may just want to split the plane check into two > > > stages > > > > As right now it depends mostly in uapi this could be moved to the > > check phase, did not left there because this will never have a > > error or a conflict > > that will cause us to reject the state. > > > > > To keep things simple I guess what I'd suggest is to forget about > > > the > > > damage stuff in the first version of the series and just do full > > > plane updates. That way we don't have to worry about so many > > > coordinate > > > space transformations. > > > > Do that would only save us the for bellow and the if to check if > > plane moved: > > > > for (j = 0; j < num_clips; j++) { > > struct drm_rect damage_area; > > > > damage_area.x1 = clips[j].x1; > > damage_area.x2 = clips[j].x2; > > damage_area.y1 = clips[j].y1; > > damage_area.y2 = clips[j].y2; > > clip_update(&plane_clip, &damage_area); > > } > > That's just some minor detail. The real issue is converting the > damage > between the various coordinate spaces we have for planes (original fb > relative src coordiantes, final SURF relative src coordinates, > crtc relative dst coordinates, and also the hw vs. uapi stuff affects > this stuff). > For the most efficient power comsumption and usage of bandthwidth, we can use Selective Fetch of Plane and PSR2 Manual Tracking together. But PSR2 Manual Tracking can be enabled without Selective Fetch of Plane. (And pre GEN12 does not have a feature "Selective Fetch of Plane".) So can you split this commit to Selective Fetch and PSR2 Manual Tracking? From ville.syrjala at linux.intel.com Tue Jun 16 15:22:51 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 18:22:51 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links In-Reply-To: <20200616141855.746-2-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-2-imre.deak@intel.com> Message-ID: <20200616152251.GW6112@intel.com> On Tue, Jun 16, 2020 at 05:18:51PM +0300, Imre Deak wrote: > We calculate the MST available bandwidth using the link's maximum rate > and lane count. This bandwidth won't be recalculated in response to a Thw wording here is a bit ambiguousr as to who "we" is, and what exactly "link's maximum rate and lane count". I would try to clarify a bit that it's drm_dp_mst_topology.c who is mostly in error here by directly interpreting the max data rate/lanes from the DPCD. Althoguh the i915 code is not wihtout faults, as it lacks any logic to modeset all the MST streams for this link when the link params change (except on tgl+ where the master/slave stuff should force all streams to do a modeset anyway). > link training error and fallback setting, so modesets following a link > training error will calculate incorrect timing parameters (like the > transcoder's data M/N params or the number of MST TUs). > > Prevent the above problem by disabling the link training fallback on MST > links for now, until the MST compute config can deal with changing link > parameters. > > The misconfigured timing lead at least to a > 'Timed out waiting for DP idle patterns' > error. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Manasi Navare <manasi.d.navare at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++------- > 1 file changed, 18 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 42589cae766d..c585b002783a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -468,6 +468,13 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > int index; > > + /* > + * TODO: Enable fallback on MST links once MST link compute can handle > + * the fallback params. > + */ > + if (intel_dp->is_mst) > + return -1; Should we duplicate the drm_error() from the other path here maybe? > + > index = intel_dp_rate_index(intel_dp->common_rates, > intel_dp->num_common_rates, > link_rate); > @@ -6163,7 +6170,17 @@ intel_dp_detect(struct drm_connector *connector, > goto out; > } > > - if (intel_dp->reset_link_params) { > + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > + if (INTEL_GEN(dev_priv) >= 11) > + intel_dp_get_dsc_sink_cap(intel_dp); > + > + intel_dp_configure_mst(intel_dp); > + > + /* > + * TODO: Reset link params when switching to MST mode, until MST > + * supports link training fallback params. > + */ > + if (intel_dp->reset_link_params || intel_dp->is_mst) { /me confused. Why do we need to touch this code? > /* Initial max link lane count */ > intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > @@ -6175,12 +6192,6 @@ intel_dp_detect(struct drm_connector *connector, > > intel_dp_print_rates(intel_dp); > > - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > - if (INTEL_GEN(dev_priv) >= 11) > - intel_dp_get_dsc_sink_cap(intel_dp); > - > - intel_dp_configure_mst(intel_dp); > - > if (intel_dp->is_mst) { > /* > * If we are in MST mode then this connector > -- > 2.23.1 -- Ville Syrj?l? Intel From imre.deak at intel.com Tue Jun 16 15:30:55 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 18:30:55 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links In-Reply-To: <20200616152251.GW6112@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-2-imre.deak@intel.com> <20200616152251.GW6112@intel.com> Message-ID: <20200616153055.GA21389@ideak-desk.fi.intel.com> On Tue, Jun 16, 2020 at 06:22:51PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 05:18:51PM +0300, Imre Deak wrote: > > We calculate the MST available bandwidth using the link's maximum rate > > and lane count. This bandwidth won't be recalculated in response to a > > Thw wording here is a bit ambiguousr as to who "we" is, and what exactly > "link's maximum rate and lane count". I would try to clarify a bit that > it's drm_dp_mst_topology.c who is mostly in error here by directly > interpreting the max data rate/lanes from the DPCD. > > Althoguh the i915 code is not wihtout faults, as it lacks any logic > to modeset all the MST streams for this link when the link params > change (except on tgl+ where the master/slave stuff should force > all streams to do a modeset anyway). > > > link training error and fallback setting, so modesets following a link > > training error will calculate incorrect timing parameters (like the > > transcoder's data M/N params or the number of MST TUs). > > > > Prevent the above problem by disabling the link training fallback on MST > > links for now, until the MST compute config can deal with changing link > > parameters. > > > > The misconfigured timing lead at least to a > > 'Timed out waiting for DP idle patterns' > > error. > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Manasi Navare <manasi.d.navare at intel.com> > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++------- > > 1 file changed, 18 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > index 42589cae766d..c585b002783a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -468,6 +468,13 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > int index; > > > > + /* > > + * TODO: Enable fallback on MST links once MST link compute can handle > > + * the fallback params. > > + */ > > + if (intel_dp->is_mst) > > + return -1; > > Should we duplicate the drm_error() from the other path here maybe? Yes, will add it. > > > + > > index = intel_dp_rate_index(intel_dp->common_rates, > > intel_dp->num_common_rates, > > link_rate); > > @@ -6163,7 +6170,17 @@ intel_dp_detect(struct drm_connector *connector, > > goto out; > > } > > > > - if (intel_dp->reset_link_params) { > > + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > + if (INTEL_GEN(dev_priv) >= 11) > > + intel_dp_get_dsc_sink_cap(intel_dp); > > + > > + intel_dp_configure_mst(intel_dp); > > + > > + /* > > + * TODO: Reset link params when switching to MST mode, until MST > > + * supports link training fallback params. > > + */ > > + if (intel_dp->reset_link_params || intel_dp->is_mst) { > > /me confused. Why do we need to touch this code? It's possible to switch to MST mode after the link rate/lane count got reduced by a link training error in SST mode. > > /* Initial max link lane count */ > > intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > @@ -6175,12 +6192,6 @@ intel_dp_detect(struct drm_connector *connector, > > > > intel_dp_print_rates(intel_dp); > > > > - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > - if (INTEL_GEN(dev_priv) >= 11) > > - intel_dp_get_dsc_sink_cap(intel_dp); > > - > > - intel_dp_configure_mst(intel_dp); > > - > > if (intel_dp->is_mst) { > > /* > > * If we are in MST mode then this connector > > -- > > 2.23.1 > > -- > Ville Syrj?l? > Intel From gustavoars at kernel.org Tue Jun 16 14:54:52 2020 From: gustavoars at kernel.org (Gustavo A. R. Silva) Date: Tue, 16 Jun 2020 09:54:52 -0500 Subject: [Intel-gfx] [PATCH][next] drm/i915/selftests: Fix inconsistent IS_ERR and PTR_ERR Message-ID: <20200616145452.GA25291@embeddedor> Fix inconsistent IS_ERR and PTR_ERR in live_timeslice_nopreempt(). The proper pointer to be passed as argument to PTR_ERR() is ce. This bug was detected with the help of Coccinelle. Fixes: b72f02d78e4f ("drm/i915/gt: Prevent timeslicing into unpreemptable requests") Signed-off-by: Gustavo A. R. Silva <gustavoars at kernel.org> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 91543494f595..393339de0910 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -1337,7 +1337,7 @@ static int live_timeslice_nopreempt(void *arg) ce = intel_context_create(engine); if (IS_ERR(ce)) { - err = PTR_ERR(rq); + err = PTR_ERR(ce); goto out_spin; } -- 2.27.0 From emil.l.velikov at gmail.com Tue Jun 16 15:34:07 2020 From: emil.l.velikov at gmail.com (Emil Velikov) Date: Tue, 16 Jun 2020 16:34:07 +0100 Subject: [Intel-gfx] [PATCH v7 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <20200615214809.GA4334@intel.com> References: <20200612230444.10121-4-manasi.d.navare@intel.com> <20200612235606.25120-1-manasi.d.navare@intel.com> <CACvgo522mYhCRkNXuwJDCt2fh4-Piq9ZOH9rNbO+HrcbrytJgQ@mail.gmail.com> <20200615214809.GA4334@intel.com> Message-ID: <CACvgo51j1BXN2ZyQ-m5AALup3ruoUHZhobSeNfS8QsV-UEjS-Q@mail.gmail.com> On Mon, 15 Jun 2020 at 22:47, Manasi Navare <manasi.d.navare at intel.com> wrote: > > On Mon, Jun 15, 2020 at 10:36:28PM +0100, Emil Velikov wrote: > > Hi Manasi, > > > > On Sat, 13 Jun 2020 at 00:55, Manasi Navare <manasi.d.navare at intel.com> wrote: > > > > > > From: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > > > > > [Why] > > > It's useful to know the min and max vrr range for IGT testing. > > > > > > [How] > > > Expose the min and max vfreq for the connector via a debugfs file > > > on the connector, "vrr_range". > > > > > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > > > > > v7: > > > * Fix cmpilation due to rebase > > > v6: > > > * Rebase (manasi) > > > v5: > > > * Rename to vrr_range to match AMD debugfs > > > v4: > > > * Rebase > > > v3: > > > * Remove the unnecessary debug print (Manasi) > > > v2: > > > * Fix the typo in max_vfreq (Manasi) > > > * Change the name of node to i915_vrr_info so we can add > > > other vrr info for more debug info (Manasi) > > > * Change the VRR capable to display Yes or No (Manasi) > > > * Fix indentation checkpatch errors (Manasi) > > > > > Nit: generally revision log is listed in v2 -> v6 order. > > Okay point noted. Will update this in the next rev > > > > > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Tested-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > .../drm/i915/display/intel_display_debugfs.c | 22 ++++++++++++++++++- > > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > index 28dd717e943a..2921f7d2a26e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > @@ -2185,6 +2185,21 @@ static const struct file_operations i915_dsc_fec_support_fops = { > > > .write = i915_dsc_fec_support_write > > > }; > > > > > > +static int vrr_range_show(struct seq_file *m, void *data) > > > +{ > > > + struct drm_connector *connector = m->private; > > > + > > > + if (connector->status != connector_status_connected) > > > + return -ENODEV; > > > + > > > + seq_printf(m, "Vrr_capable: %s\n", yesno(intel_dp_is_vrr_capable(connector))); > > > + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); > > > + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); > > > + > > > + return 0; > > > +} > > > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > > > + > > > /** > > > * intel_connector_debugfs_add - add i915 specific connector debugfs files > > > * @connector: pointer to a registered drm_connector > > > @@ -2220,10 +2235,15 @@ int intel_connector_debugfs_add(struct drm_connector *connector) > > > if (INTEL_GEN(dev_priv) >= 10 && > > > ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && > > > !to_intel_connector(connector)->mst_port) || > > > - connector->connector_type == DRM_MODE_CONNECTOR_eDP)) > > > + connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { > > > debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, > > > connector, &i915_dsc_fec_support_fops); > > > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > + debugfs_create_file("vrr_range", S_IRUGO, > > > + root, connector, &vrr_range_fops); > > > + } > > > + > > > > I think this should be added by core drm. Ideally drm will add it > > automatically for each connector that the driver has called > > drm_connector_attach_vrr_capable_property() upon. > > > > But in this case drm_connector_attach_vrr_capable_property() is called by individual > driver since its an optional connector property. So we call this inside i915. I'm _not_ suggesting that one moves the drm_connector_attach_vrr_capable_property() call. Simply create the debugfs file in drm itself. > Also currently AMD sets this debugfs inside AMD IMO, so setting this here for now. Let's do the better thing of a) make drm create the file, and b) remove the AMDGPU specific one. We're talking about 20-30 lines worth of a patch. Postponing it sounds silly. > But I agree that can be moved to drm core may be when drm_display_info gets populated > with min and max, thats where drm can add this? > Both min and max are already part of drm_display_info. On the question of how - check the existing properties (edid_override, force) for examples. -Emil From ville.syrjala at linux.intel.com Tue Jun 16 15:39:30 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 18:39:30 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links In-Reply-To: <20200616153055.GA21389@ideak-desk.fi.intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-2-imre.deak@intel.com> <20200616152251.GW6112@intel.com> <20200616153055.GA21389@ideak-desk.fi.intel.com> Message-ID: <20200616153930.GX6112@intel.com> On Tue, Jun 16, 2020 at 06:30:55PM +0300, Imre Deak wrote: > On Tue, Jun 16, 2020 at 06:22:51PM +0300, Ville Syrj?l? wrote: > > On Tue, Jun 16, 2020 at 05:18:51PM +0300, Imre Deak wrote: > > > We calculate the MST available bandwidth using the link's maximum rate > > > and lane count. This bandwidth won't be recalculated in response to a > > > > Thw wording here is a bit ambiguousr as to who "we" is, and what exactly > > "link's maximum rate and lane count". I would try to clarify a bit that > > it's drm_dp_mst_topology.c who is mostly in error here by directly > > interpreting the max data rate/lanes from the DPCD. > > > > Althoguh the i915 code is not wihtout faults, as it lacks any logic > > to modeset all the MST streams for this link when the link params > > change (except on tgl+ where the master/slave stuff should force > > all streams to do a modeset anyway). > > > > > link training error and fallback setting, so modesets following a link > > > training error will calculate incorrect timing parameters (like the > > > transcoder's data M/N params or the number of MST TUs). > > > > > > Prevent the above problem by disabling the link training fallback on MST > > > links for now, until the MST compute config can deal with changing link > > > parameters. > > > > > > The misconfigured timing lead at least to a > > > 'Timed out waiting for DP idle patterns' > > > error. > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Manasi Navare <manasi.d.navare at intel.com> > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++------- > > > 1 file changed, 18 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 42589cae766d..c585b002783a 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -468,6 +468,13 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > int index; > > > > > > + /* > > > + * TODO: Enable fallback on MST links once MST link compute can handle > > > + * the fallback params. > > > + */ > > > + if (intel_dp->is_mst) > > > + return -1; > > > > Should we duplicate the drm_error() from the other path here maybe? > > Yes, will add it. > > > > > > + > > > index = intel_dp_rate_index(intel_dp->common_rates, > > > intel_dp->num_common_rates, > > > link_rate); > > > @@ -6163,7 +6170,17 @@ intel_dp_detect(struct drm_connector *connector, > > > goto out; > > > } > > > > > > - if (intel_dp->reset_link_params) { > > > + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > > + if (INTEL_GEN(dev_priv) >= 11) > > > + intel_dp_get_dsc_sink_cap(intel_dp); > > > + > > > + intel_dp_configure_mst(intel_dp); > > > + > > > + /* > > > + * TODO: Reset link params when switching to MST mode, until MST > > > + * supports link training fallback params. > > > + */ > > > + if (intel_dp->reset_link_params || intel_dp->is_mst) { > > > > /me confused. Why do we need to touch this code? > > It's possible to switch to MST mode after the link rate/lane count got > reduced by a link training error in SST mode. But then we should have a long hpd and reset_link_params should be set anyway no? > > > > /* Initial max link lane count */ > > > intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > > > @@ -6175,12 +6192,6 @@ intel_dp_detect(struct drm_connector *connector, > > > > > > intel_dp_print_rates(intel_dp); > > > > > > - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > > - if (INTEL_GEN(dev_priv) >= 11) > > > - intel_dp_get_dsc_sink_cap(intel_dp); > > > - > > > - intel_dp_configure_mst(intel_dp); > > > - > > > if (intel_dp->is_mst) { > > > /* > > > * If we are in MST mode then this connector > > > -- > > > 2.23.1 > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 16 15:45:46 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 18:45:46 +0300 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616141855.746-6-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-6-imre.deak@intel.com> Message-ID: <20200616154546.GY6112@intel.com> On Tue, Jun 16, 2020 at 05:18:55PM +0300, Imre Deak wrote: > Atm, we clear the ACT sent flag in the sink's DPCD before updating the > sink's payload table, along clearing the payload table updated flag. > The sink is supposed to set this flag once it detects that the source > has completed the ACT sequence (after detecting the 4 required ACT MTPH > symbols sent by the source). As opposed to this 2 DELL monitors I have > set the flag already along the payload table updated flag, which is not > quite correct. > > To be sure that the sink has detected the ACT MTPH symbols before > continuing enabling the encoder, clear the ACT sent flag before enabling > or disabling the transcoder VC payload allocation (which is what starts > the ACT sequence). > > Cc: Lyude Paul <lyude at redhat.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: dri-devel at lists.freedesktop.org > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 31 +++++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > include/drm/drm_dp_mst_helper.h | 2 ++ > 3 files changed, 33 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index b2f5a84b4cfb..e3bf8c9c8267 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -4377,6 +4377,34 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, > } > EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); > > +/** > + * drm_dp_clear_payload_status() - Clears the payload table status flags > + * @mgr: manager to use > + * > + * Clears the payload table ACT handled and table updated flags in the MST hub's > + * DPCD. This function must be called before updating the payload table or > + * starting the ACT sequence and waiting for the corresponding flags to get > + * set by the hub. > + * > + * Returns: > + * 0 if the flag got cleared successfully, otherwise a negative error code. > + */ > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) > +{ > + int ret; > + > + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > + DP_PAYLOAD_ACT_HANDLED); > + if (ret < 0) { > + DRM_DEBUG_DRIVER("Can't clear the ACT sent flag (%d)\n", ret); > + return ret; > + } > + WARN_ON(ret != 1); > + > + return 0; > +} > +EXPORT_SYMBOL(drm_dp_clear_payload_status); > + > static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > int id, struct drm_dp_payload *payload) > { > @@ -4384,8 +4412,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > int ret; > int retries = 0; > > - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > - DP_PAYLOAD_TABLE_UPDATED); We used to clear DP_PAYLOAD_TABLE_UPDATED but now we clear DP_PAYLOAD_ACT_HANDLED ? > + drm_dp_clear_payload_status(mgr); > > payload_alloc[0] = id; > payload_alloc[1] = payload->start_slot; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 9308b5920780..3c4b0fb10d8b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > DP_TP_STATUS_ACT_SENT); > + > + drm_dp_clear_payload_status(&intel_dp->mst_mgr); > } > > static void wait_for_act_sent(struct intel_dp *intel_dp) > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 8b9eb4db3381..2facb87624bf 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, > int pbn); > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); > + > int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); > > > -- > 2.23.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 16 15:46:22 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 18:46:22 +0300 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <20200616154622.GZ6112@intel.com> On Tue, Jun 16, 2020 at 05:18:50PM +0300, Imre Deak wrote: > MST encoders must use the master MST transcoder's DP_TP_STATUS and > DP_TP_CONTROL registers. Atm, during the HW readout of a slave > transcoder's CRTC state we reset these register addresses in > intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register > addresses incorrectly; fix this. > > This issue led at least to > 'Timed out waiting for ACT sent when disabling' > errors during output disabling in a multiple MST stream config. > > This change replaces > https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 > which just papered over the problem. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b..73d6cc29291a 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) > return; > > - if (INTEL_GEN(dev_priv) >= 12) { > - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); > - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); > - } > - > intel_dsc_get_config(encoder, pipe_config); > > temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); > @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > break; > } > > + if (INTEL_GEN(dev_priv) >= 12) { > + enum transcoder transcoder = > + intel_dp_mst_is_slave_trans(pipe_config) ? > + pipe_config->mst_master_transcoder : > + pipe_config->cpu_transcoder; > + > + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); > + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); > + } > + > pipe_config->has_audio = > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); > > -- > 2.23.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 16 15:47:02 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 18:47:02 +0300 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling In-Reply-To: <20200616141855.746-3-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-3-imre.deak@intel.com> Message-ID: <20200616154702.GA6112@intel.com> On Tue, Jun 16, 2020 at 05:18:52PM +0300, Imre Deak wrote: > During transcoder enabling we'll configure the transcoder in MST mode > and enable the VC payload allocation, which will start the ACT sequence. > Before waiting for the ACT sequence completion, we need to clear the ACT > sent flag, but based on the above we can do this right before enabling > the transcoder. > > For clarity, move the flag clearing closer to where we wait for it. > > While at it also factor out some common code. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 36 +++++++++++++-------- > 1 file changed, 23 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 2e6c6375a23b..3977ee4f7176 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -317,6 +317,25 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, > return ret; > } > > +static void clear_act_sent(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + > + intel_de_write(i915, intel_dp->regs.dp_tp_status, > + intel_de_read(i915, intel_dp->regs.dp_tp_status)); > +} > + > +static void wait_for_act_sent(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + > + if (intel_de_wait_for_set(i915, intel_dp->regs.dp_tp_status, > + DP_TP_STATUS_ACT_SENT, 1)) > + drm_err(&i915->drm, "Timed out waiting for ACT sent\n"); > + > + drm_dp_check_act_status(&intel_dp->mst_mgr); > +} > + > static void intel_mst_disable_dp(struct intel_atomic_state *state, > struct intel_encoder *encoder, > const struct intel_crtc_state *old_crtc_state, > @@ -377,11 +396,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), > val); > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > - drm_err(&dev_priv->drm, > - "Timed out waiting for ACT sent when disabling\n"); > - drm_dp_check_act_status(&intel_dp->mst_mgr); > + wait_for_act_sent(intel_dp); > > drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); > > @@ -452,7 +467,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > struct intel_connector *connector = > to_intel_connector(conn_state->connector); > int ret; > - u32 temp; > bool first_mst_stream; > > /* MST encoders are bound to a crtc, not to a connector, > @@ -485,8 +499,6 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); > > intel_dp->active_mst_links++; > - temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); > - intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); > > ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); > > @@ -517,16 +529,14 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); > > + clear_act_sent(intel_dp); > + > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > intel_dp->active_mst_links); > > - if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > - DP_TP_STATUS_ACT_SENT, 1)) > - drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n"); > - > - drm_dp_check_act_status(&intel_dp->mst_mgr); > + wait_for_act_sent(intel_dp); > > drm_dp_update_payload_part2(&intel_dp->mst_mgr); > > -- > 2.23.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 16 15:47:17 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 18:47:17 +0300 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/dp_mst: Clear only the ACT sent flag from DP_TP_STATUS In-Reply-To: <20200616141855.746-4-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-4-imre.deak@intel.com> Message-ID: <20200616154717.GB6112@intel.com> On Tue, Jun 16, 2020 at 05:18:53PM +0300, Imre Deak wrote: > It's not clear if the DP_TP_STATUS flags other than the ACT sent flag > have some side-effect, so don't clear those; we don't depend on the > state of these flags anyway. > > Suggested-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 3977ee4f7176..b66b56a070e5 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -322,7 +322,7 @@ static void clear_act_sent(struct intel_dp *intel_dp) > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > - intel_de_read(i915, intel_dp->regs.dp_tp_status)); > + DP_TP_STATUS_ACT_SENT); > } > > static void wait_for_act_sent(struct intel_dp *intel_dp) > -- > 2.23.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 16 15:47:44 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 18:47:44 +0300 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too In-Reply-To: <20200616141855.746-5-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-5-imre.deak@intel.com> Message-ID: <20200616154744.GC6112@intel.com> On Tue, Jun 16, 2020 at 05:18:54PM +0300, Imre Deak wrote: > During encoder enabling we clear the flag before starting the ACT > sequence and wait for the flag, but the clearing is missing during > encoder disabling, add it there too. Since nothing cleared the flag > automatically we could've run subsequent disabling steps too early. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index b66b56a070e5..9308b5920780 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -389,6 +389,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > > drm_dp_update_payload_part2(&intel_dp->mst_mgr); > > + clear_act_sent(intel_dp); > + > val = intel_de_read(dev_priv, > TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder)); > val &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; > -- > 2.23.1 -- Ville Syrj?l? Intel From imre.deak at intel.com Tue Jun 16 15:49:20 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 18:49:20 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links In-Reply-To: <20200616153930.GX6112@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-2-imre.deak@intel.com> <20200616152251.GW6112@intel.com> <20200616153055.GA21389@ideak-desk.fi.intel.com> <20200616153930.GX6112@intel.com> Message-ID: <20200616154920.GB21389@ideak-desk.fi.intel.com> On Tue, Jun 16, 2020 at 06:39:30PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 06:30:55PM +0300, Imre Deak wrote: > > On Tue, Jun 16, 2020 at 06:22:51PM +0300, Ville Syrj?l? wrote: > > > On Tue, Jun 16, 2020 at 05:18:51PM +0300, Imre Deak wrote: > > > > We calculate the MST available bandwidth using the link's maximum rate > > > > and lane count. This bandwidth won't be recalculated in response to a > > > > > > Thw wording here is a bit ambiguousr as to who "we" is, and what exactly > > > "link's maximum rate and lane count". I would try to clarify a bit that > > > it's drm_dp_mst_topology.c who is mostly in error here by directly > > > interpreting the max data rate/lanes from the DPCD. > > > > > > Althoguh the i915 code is not wihtout faults, as it lacks any logic > > > to modeset all the MST streams for this link when the link params > > > change (except on tgl+ where the master/slave stuff should force > > > all streams to do a modeset anyway). > > > > > > > link training error and fallback setting, so modesets following a link > > > > training error will calculate incorrect timing parameters (like the > > > > transcoder's data M/N params or the number of MST TUs). > > > > > > > > Prevent the above problem by disabling the link training fallback on MST > > > > links for now, until the MST compute config can deal with changing link > > > > parameters. > > > > > > > > The misconfigured timing lead at least to a > > > > 'Timed out waiting for DP idle patterns' > > > > error. > > > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Cc: Manasi Navare <manasi.d.navare at intel.com> > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++------- > > > > 1 file changed, 18 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 42589cae766d..c585b002783a 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -468,6 +468,13 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, > > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > int index; > > > > > > > > + /* > > > > + * TODO: Enable fallback on MST links once MST link compute can handle > > > > + * the fallback params. > > > > + */ > > > > + if (intel_dp->is_mst) > > > > + return -1; > > > > > > Should we duplicate the drm_error() from the other path here maybe? > > > > Yes, will add it. > > > > > > > > > + > > > > index = intel_dp_rate_index(intel_dp->common_rates, > > > > intel_dp->num_common_rates, > > > > link_rate); > > > > @@ -6163,7 +6170,17 @@ intel_dp_detect(struct drm_connector *connector, > > > > goto out; > > > > } > > > > > > > > - if (intel_dp->reset_link_params) { > > > > + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > > > + if (INTEL_GEN(dev_priv) >= 11) > > > > + intel_dp_get_dsc_sink_cap(intel_dp); > > > > + > > > > + intel_dp_configure_mst(intel_dp); > > > > + > > > > + /* > > > > + * TODO: Reset link params when switching to MST mode, until MST > > > > + * supports link training fallback params. > > > > + */ > > > > + if (intel_dp->reset_link_params || intel_dp->is_mst) { > > > > > > /me confused. Why do we need to touch this code? > > > > It's possible to switch to MST mode after the link rate/lane count got > > reduced by a link training error in SST mode. > > But then we should have a long hpd and reset_link_params should be set > anyway no? I meant switching the mode for the same sink as it would change its DP_MST_CAP. I'm not sure if a long HPD is required in that case. Also if we had a long HPD after a mode change couldn't a modeset run before the next intel_dp_detect() call could reset the link params? > > > > > > /* Initial max link lane count */ > > > > intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > > > > > @@ -6175,12 +6192,6 @@ intel_dp_detect(struct drm_connector *connector, > > > > > > > > intel_dp_print_rates(intel_dp); > > > > > > > > - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > > > - if (INTEL_GEN(dev_priv) >= 11) > > > > - intel_dp_get_dsc_sink_cap(intel_dp); > > > > - > > > > - intel_dp_configure_mst(intel_dp); > > > > - > > > > if (intel_dp->is_mst) { > > > > /* > > > > * If we are in MST mode then this connector > > > > -- > > > > 2.23.1 > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel From imre.deak at intel.com Tue Jun 16 15:54:41 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 18:54:41 +0300 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616154546.GY6112@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-6-imre.deak@intel.com> <20200616154546.GY6112@intel.com> Message-ID: <20200616155441.GC21389@ideak-desk.fi.intel.com> On Tue, Jun 16, 2020 at 06:45:46PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 05:18:55PM +0300, Imre Deak wrote: > > Atm, we clear the ACT sent flag in the sink's DPCD before updating the > > sink's payload table, along clearing the payload table updated flag. > > The sink is supposed to set this flag once it detects that the source > > has completed the ACT sequence (after detecting the 4 required ACT MTPH > > symbols sent by the source). As opposed to this 2 DELL monitors I have > > set the flag already along the payload table updated flag, which is not > > quite correct. > > > > To be sure that the sink has detected the ACT MTPH symbols before > > continuing enabling the encoder, clear the ACT sent flag before enabling > > or disabling the transcoder VC payload allocation (which is what starts > > the ACT sequence). > > > > Cc: Lyude Paul <lyude at redhat.com> > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: dri-devel at lists.freedesktop.org > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 31 +++++++++++++++++++-- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > > include/drm/drm_dp_mst_helper.h | 2 ++ > > 3 files changed, 33 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > index b2f5a84b4cfb..e3bf8c9c8267 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -4377,6 +4377,34 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, > > } > > EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); > > > > +/** > > + * drm_dp_clear_payload_status() - Clears the payload table status flags > > + * @mgr: manager to use > > + * > > + * Clears the payload table ACT handled and table updated flags in the MST hub's > > + * DPCD. This function must be called before updating the payload table or > > + * starting the ACT sequence and waiting for the corresponding flags to get > > + * set by the hub. > > + * > > + * Returns: > > + * 0 if the flag got cleared successfully, otherwise a negative error code. > > + */ > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) > > +{ > > + int ret; > > + > > + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > + DP_PAYLOAD_ACT_HANDLED); > > + if (ret < 0) { > > + DRM_DEBUG_DRIVER("Can't clear the ACT sent flag (%d)\n", ret); > > + return ret; > > + } > > + WARN_ON(ret != 1); > > + > > + return 0; > > +} > > +EXPORT_SYMBOL(drm_dp_clear_payload_status); > > + > > static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > int id, struct drm_dp_payload *payload) > > { > > @@ -4384,8 +4412,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > int ret; > > int retries = 0; > > > > - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > - DP_PAYLOAD_TABLE_UPDATED); > > We used to clear DP_PAYLOAD_TABLE_UPDATED but now we clear > DP_PAYLOAD_ACT_HANDLED ? Eek. We should write DP_PAYLOAD_TABLE_UPDATED which is the only way to clear both the act-handled and the table-updated flags. I tested things that way but managed to send an old version. Thanks for catching it. > > > + drm_dp_clear_payload_status(mgr); > > > > payload_alloc[0] = id; > > payload_alloc[1] = payload->start_slot; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index 9308b5920780..3c4b0fb10d8b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) > > > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > > DP_TP_STATUS_ACT_SENT); > > + > > + drm_dp_clear_payload_status(&intel_dp->mst_mgr); > > } > > > > static void wait_for_act_sent(struct intel_dp *intel_dp) > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > > index 8b9eb4db3381..2facb87624bf 100644 > > --- a/include/drm/drm_dp_mst_helper.h > > +++ b/include/drm/drm_dp_mst_helper.h > > @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, > > int pbn); > > > > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); > > + > > int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); > > > > > > -- > > 2.23.1 > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Tue Jun 16 16:20:10 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 19:20:10 +0300 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Disable link training fallback on MST links In-Reply-To: <20200616154920.GB21389@ideak-desk.fi.intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-2-imre.deak@intel.com> <20200616152251.GW6112@intel.com> <20200616153055.GA21389@ideak-desk.fi.intel.com> <20200616153930.GX6112@intel.com> <20200616154920.GB21389@ideak-desk.fi.intel.com> Message-ID: <20200616162010.GD6112@intel.com> On Tue, Jun 16, 2020 at 06:49:20PM +0300, Imre Deak wrote: > On Tue, Jun 16, 2020 at 06:39:30PM +0300, Ville Syrj?l? wrote: > > On Tue, Jun 16, 2020 at 06:30:55PM +0300, Imre Deak wrote: > > > On Tue, Jun 16, 2020 at 06:22:51PM +0300, Ville Syrj?l? wrote: > > > > On Tue, Jun 16, 2020 at 05:18:51PM +0300, Imre Deak wrote: > > > > > We calculate the MST available bandwidth using the link's maximum rate > > > > > and lane count. This bandwidth won't be recalculated in response to a > > > > > > > > Thw wording here is a bit ambiguousr as to who "we" is, and what exactly > > > > "link's maximum rate and lane count". I would try to clarify a bit that > > > > it's drm_dp_mst_topology.c who is mostly in error here by directly > > > > interpreting the max data rate/lanes from the DPCD. > > > > > > > > Althoguh the i915 code is not wihtout faults, as it lacks any logic > > > > to modeset all the MST streams for this link when the link params > > > > change (except on tgl+ where the master/slave stuff should force > > > > all streams to do a modeset anyway). > > > > > > > > > link training error and fallback setting, so modesets following a link > > > > > training error will calculate incorrect timing parameters (like the > > > > > transcoder's data M/N params or the number of MST TUs). > > > > > > > > > > Prevent the above problem by disabling the link training fallback on MST > > > > > links for now, until the MST compute config can deal with changing link > > > > > parameters. > > > > > > > > > > The misconfigured timing lead at least to a > > > > > 'Timed out waiting for DP idle patterns' > > > > > error. > > > > > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > Cc: Manasi Navare <manasi.d.navare at intel.com> > > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 25 ++++++++++++++++++------- > > > > > 1 file changed, 18 insertions(+), 7 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > index 42589cae766d..c585b002783a 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > @@ -468,6 +468,13 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, > > > > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > > > > > int index; > > > > > > > > > > + /* > > > > > + * TODO: Enable fallback on MST links once MST link compute can handle > > > > > + * the fallback params. > > > > > + */ > > > > > + if (intel_dp->is_mst) > > > > > + return -1; > > > > > > > > Should we duplicate the drm_error() from the other path here maybe? > > > > > > Yes, will add it. > > > > > > > > > > > > + > > > > > index = intel_dp_rate_index(intel_dp->common_rates, > > > > > intel_dp->num_common_rates, > > > > > link_rate); > > > > > @@ -6163,7 +6170,17 @@ intel_dp_detect(struct drm_connector *connector, > > > > > goto out; > > > > > } > > > > > > > > > > - if (intel_dp->reset_link_params) { > > > > > + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > > > > + if (INTEL_GEN(dev_priv) >= 11) > > > > > + intel_dp_get_dsc_sink_cap(intel_dp); > > > > > + > > > > > + intel_dp_configure_mst(intel_dp); > > > > > + > > > > > + /* > > > > > + * TODO: Reset link params when switching to MST mode, until MST > > > > > + * supports link training fallback params. > > > > > + */ > > > > > + if (intel_dp->reset_link_params || intel_dp->is_mst) { > > > > > > > > /me confused. Why do we need to touch this code? > > > > > > It's possible to switch to MST mode after the link rate/lane count got > > > reduced by a link training error in SST mode. > > > > But then we should have a long hpd and reset_link_params should be set > > anyway no? > > I meant switching the mode for the same sink as it would change its > DP_MST_CAP. I'm not sure if a long HPD is required in that case. I would expect so. I don't think there's a requirement in the spec to re-evaluate this sort of stuff for a short hpd. > Also if > we had a long HPD after a mode change couldn't a modeset run before the > next intel_dp_detect() call could reset the link params? This is detect() we're talking about here, so I guess you mean detect() running before the hpd gets to flag reset_link_params=true ? Not sure I'd worry about that, but I guess there should be no harm in reordering these things a bit. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > > /* Initial max link lane count */ > > > > > intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); > > > > > > > > > > @@ -6175,12 +6192,6 @@ intel_dp_detect(struct drm_connector *connector, > > > > > > > > > > intel_dp_print_rates(intel_dp); > > > > > > > > > > - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ > > > > > - if (INTEL_GEN(dev_priv) >= 11) > > > > > - intel_dp_get_dsc_sink_cap(intel_dp); > > > > > - > > > > > - intel_dp_configure_mst(intel_dp); > > > > > - > > > > > if (intel_dp->is_mst) { > > > > > /* > > > > > * If we are in MST mode then this connector > > > > > -- > > > > > 2.23.1 > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 16 16:23:21 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 19:23:21 +0300 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616155441.GC21389@ideak-desk.fi.intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-6-imre.deak@intel.com> <20200616154546.GY6112@intel.com> <20200616155441.GC21389@ideak-desk.fi.intel.com> Message-ID: <20200616162321.GE6112@intel.com> On Tue, Jun 16, 2020 at 06:54:41PM +0300, Imre Deak wrote: > On Tue, Jun 16, 2020 at 06:45:46PM +0300, Ville Syrj?l? wrote: > > On Tue, Jun 16, 2020 at 05:18:55PM +0300, Imre Deak wrote: > > > Atm, we clear the ACT sent flag in the sink's DPCD before updating the > > > sink's payload table, along clearing the payload table updated flag. > > > The sink is supposed to set this flag once it detects that the source > > > has completed the ACT sequence (after detecting the 4 required ACT MTPH > > > symbols sent by the source). As opposed to this 2 DELL monitors I have > > > set the flag already along the payload table updated flag, which is not > > > quite correct. > > > > > > To be sure that the sink has detected the ACT MTPH symbols before > > > continuing enabling the encoder, clear the ACT sent flag before enabling > > > or disabling the transcoder VC payload allocation (which is what starts > > > the ACT sequence). > > > > > > Cc: Lyude Paul <lyude at redhat.com> > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: dri-devel at lists.freedesktop.org > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > --- > > > drivers/gpu/drm/drm_dp_mst_topology.c | 31 +++++++++++++++++++-- > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > > > include/drm/drm_dp_mst_helper.h | 2 ++ > > > 3 files changed, 33 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > > index b2f5a84b4cfb..e3bf8c9c8267 100644 > > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > > @@ -4377,6 +4377,34 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, > > > } > > > EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); > > > > > > +/** > > > + * drm_dp_clear_payload_status() - Clears the payload table status flags > > > + * @mgr: manager to use > > > + * > > > + * Clears the payload table ACT handled and table updated flags in the MST hub's > > > + * DPCD. This function must be called before updating the payload table or > > > + * starting the ACT sequence and waiting for the corresponding flags to get > > > + * set by the hub. > > > + * > > > + * Returns: > > > + * 0 if the flag got cleared successfully, otherwise a negative error code. > > > + */ > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) > > > +{ > > > + int ret; > > > + > > > + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > > + DP_PAYLOAD_ACT_HANDLED); > > > + if (ret < 0) { > > > + DRM_DEBUG_DRIVER("Can't clear the ACT sent flag (%d)\n", ret); > > > + return ret; > > > + } > > > + WARN_ON(ret != 1); > > > + > > > + return 0; > > > +} > > > +EXPORT_SYMBOL(drm_dp_clear_payload_status); > > > + > > > static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > > int id, struct drm_dp_payload *payload) > > > { > > > @@ -4384,8 +4412,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > > int ret; > > > int retries = 0; > > > > > > - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > > - DP_PAYLOAD_TABLE_UPDATED); > > > > We used to clear DP_PAYLOAD_TABLE_UPDATED but now we clear > > DP_PAYLOAD_ACT_HANDLED ? > > Eek. We should write DP_PAYLOAD_TABLE_UPDATED which is the only way to > clear both the act-handled and the table-updated flags. Huh. That's a bit crazy. But it is what the spec says. > I tested things > that way but managed to send an old version. Thanks for catching it. > > > > > > + drm_dp_clear_payload_status(mgr); > > > > > > payload_alloc[0] = id; > > > payload_alloc[1] = payload->start_slot; > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > index 9308b5920780..3c4b0fb10d8b 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) > > > > > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > > > DP_TP_STATUS_ACT_SENT); > > > + > > > + drm_dp_clear_payload_status(&intel_dp->mst_mgr); > > > } > > > > > > static void wait_for_act_sent(struct intel_dp *intel_dp) > > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > > > index 8b9eb4db3381..2facb87624bf 100644 > > > --- a/include/drm/drm_dp_mst_helper.h > > > +++ b/include/drm/drm_dp_mst_helper.h > > > @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, > > > int pbn); > > > > > > > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); > > > + > > > int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); > > > > > > > > > -- > > > 2.23.1 > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From jose.souza at intel.com Tue Jun 16 16:32:46 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 16 Jun 2020 16:32:46 +0000 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <4c40d13cfdb9cfe4d59eb04f27828b597949c54e.camel@intel.com> On Tue, 2020-06-16 at 17:18 +0300, Imre Deak wrote: > MST encoders must use the master MST transcoder's DP_TP_STATUS and > DP_TP_CONTROL registers. Atm, during the HW readout of a slave > transcoder's CRTC state we reset these register addresses in > intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register > addresses incorrectly; fix this. > > This issue led at least to > 'Timed out waiting for ACT sent when disabling' > errors during output disabling in a multiple MST stream config. Can you point to place where dp_tp_ctl is used and cause this? All the MST code paths uses the dp_tp_ctl of the main intel_dp(the one that is not a mst connector). > > This change replaces > https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 > which just papered over the problem. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b..73d6cc29291a 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) > return; > > - if (INTEL_GEN(dev_priv) >= 12) { > - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); > - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); > - } > - > intel_dsc_get_config(encoder, pipe_config); > > temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); > @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > break; > } > > + if (INTEL_GEN(dev_priv) >= 12) { > + enum transcoder transcoder = > + intel_dp_mst_is_slave_trans(pipe_config) ? > + pipe_config->mst_master_transcoder : > + pipe_config->cpu_transcoder; > + > + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); > + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); > + } Also not sure how change only in the config readout would fix the issue, IFWI don't enable MST so when i915 takes over a full modeset will happen to enable MST and only dp_tp_ctl of the main intel_dp(the one that is not a mst connector) will be set, check tgl_ddi_pre_enable_dp(). > + > pipe_config->has_audio = > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); > From matthew.s.atwood at intel.com Tue Jun 16 16:34:06 2020 From: matthew.s.atwood at intel.com (Matt Atwood) Date: Tue, 16 Jun 2020 09:34:06 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ Message-ID: <20200616163406.27387-1-matthew.s.atwood@intel.com> Add minimum width to planes, variable with specific formats, for gen11+. Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++--- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7457813ef273..d4fdad6cb3b1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb, } } +static int icl_min_plane_width(struct drm_i915_private *dev_priv, + const struct drm_framebuffer *fb) +{ + /* Wa_14011264657, Wa_14011050563 */ + switch (fb->format->format) { + case DRM_FORMAT_C8: + return 18; + case DRM_FORMAT_RGB565: + return 10; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_XVYU2101010: + case DRM_FORMAT_Y212: + case DRM_FORMAT_Y216: + return 6; + case DRM_FORMAT_NV12: + return 20; + case DRM_FORMAT_P010: + case DRM_FORMAT_P012: + case DRM_FORMAT_P016: + return 12; + case DRM_FORMAT_XRGB16161616F: + case DRM_FORMAT_XBGR16161616F: + case DRM_FORMAT_ARGB16161616F: + case DRM_FORMAT_ABGR16161616F: + case DRM_FORMAT_XVYU12_16161616: + case DRM_FORMAT_XVYU16161616: + return 4; + default: + return 1; + } +} + static int icl_max_plane_width(const struct drm_framebuffer *fb, int color_plane, unsigned int rotation) @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) int y = plane_state->uapi.src.y1 >> 16; int w = drm_rect_width(&plane_state->uapi.src) >> 16; int h = drm_rect_height(&plane_state->uapi.src) >> 16; - int max_width; - int max_height; - u32 alignment; - u32 offset; + int max_width, min_width = 1, max_height; + u32 alignment, offset; int aux_plane = intel_main_to_aux_plane(fb, 0); u32 aux_offset = plane_state->color_plane[aux_plane].offset; - if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_GEN(dev_priv) >= 11) { max_width = icl_max_plane_width(fb, 0, rotation); + min_width = icl_min_plane_width(dev_priv, fb); + } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) max_width = glk_max_plane_width(fb, 0, rotation); else @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) else max_height = skl_max_plane_height(); - if (w > max_width || h > max_height) { + if (w > max_width || w < min_width || h > max_height) { drm_dbg_kms(&dev_priv->drm, - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n", - w, h, max_width, max_height); + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", + w, h, min_width, max_width, max_height); return -EINVAL; } -- 2.21.3 From lkp at intel.com Tue Jun 16 16:34:06 2020 From: lkp at intel.com (kernel test robot) Date: Wed, 17 Jun 2020 00:34:06 +0800 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> References: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> Message-ID: <202006170019.J27emK9x%lkp@intel.com> Hi Shaofeng, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on drm-tip/drm-tip linus/master v5.8-rc1 next-20200616] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Shaofeng-Tang/drm-i915-gvt-query-if-vgpu-is-active-via-GETPARAM-IOCTL/20200616-162408 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-debian-10.3 (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>, old ones prefixed by <<): drivers/gpu/drm/i915/i915_getparam.c: In function 'i915_getparam_ioctl': >> drivers/gpu/drm/i915/i915_getparam.c:165:11: error: implicit declaration of function 'intel_vgpu_active'; did you mean 'intel_vtd_active'? [-Werror=implicit-function-declaration] 165 | value = intel_vgpu_active(i915); | ^~~~~~~~~~~~~~~~~ | intel_vtd_active cc1: some warnings being treated as errors vim +165 drivers/gpu/drm/i915/i915_getparam.c 10 11 int i915_getparam_ioctl(struct drm_device *dev, void *data, 12 struct drm_file *file_priv) 13 { 14 struct drm_i915_private *i915 = to_i915(dev); 15 const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; 16 drm_i915_getparam_t *param = data; 17 int value; 18 19 switch (param->param) { 20 case I915_PARAM_IRQ_ACTIVE: 21 case I915_PARAM_ALLOW_BATCHBUFFER: 22 case I915_PARAM_LAST_DISPATCH: 23 case I915_PARAM_HAS_EXEC_CONSTANTS: 24 /* Reject all old ums/dri params. */ 25 return -ENODEV; 26 case I915_PARAM_CHIPSET_ID: 27 value = i915->drm.pdev->device; 28 break; 29 case I915_PARAM_REVISION: 30 value = i915->drm.pdev->revision; 31 break; 32 case I915_PARAM_NUM_FENCES_AVAIL: 33 value = i915->ggtt.num_fences; 34 break; 35 case I915_PARAM_HAS_OVERLAY: 36 value = !!i915->overlay; 37 break; 38 case I915_PARAM_HAS_BSD: 39 value = !!intel_engine_lookup_user(i915, 40 I915_ENGINE_CLASS_VIDEO, 0); 41 break; 42 case I915_PARAM_HAS_BLT: 43 value = !!intel_engine_lookup_user(i915, 44 I915_ENGINE_CLASS_COPY, 0); 45 break; 46 case I915_PARAM_HAS_VEBOX: 47 value = !!intel_engine_lookup_user(i915, 48 I915_ENGINE_CLASS_VIDEO_ENHANCE, 0); 49 break; 50 case I915_PARAM_HAS_BSD2: 51 value = !!intel_engine_lookup_user(i915, 52 I915_ENGINE_CLASS_VIDEO, 1); 53 break; 54 case I915_PARAM_HAS_LLC: 55 value = HAS_LLC(i915); 56 break; 57 case I915_PARAM_HAS_WT: 58 value = HAS_WT(i915); 59 break; 60 case I915_PARAM_HAS_ALIASING_PPGTT: 61 value = INTEL_PPGTT(i915); 62 break; 63 case I915_PARAM_HAS_SEMAPHORES: 64 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES); 65 break; 66 case I915_PARAM_HAS_SECURE_BATCHES: 67 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN); 68 break; 69 case I915_PARAM_CMD_PARSER_VERSION: 70 value = i915_cmd_parser_get_version(i915); 71 break; 72 case I915_PARAM_SUBSLICE_TOTAL: 73 value = intel_sseu_subslice_total(sseu); 74 if (!value) 75 return -ENODEV; 76 break; 77 case I915_PARAM_EU_TOTAL: 78 value = sseu->eu_total; 79 if (!value) 80 return -ENODEV; 81 break; 82 case I915_PARAM_HAS_GPU_RESET: 83 value = i915_modparams.enable_hangcheck && 84 intel_has_gpu_reset(&i915->gt); 85 if (value && intel_has_reset_engine(&i915->gt)) 86 value = 2; 87 break; 88 case I915_PARAM_HAS_RESOURCE_STREAMER: 89 value = 0; 90 break; 91 case I915_PARAM_HAS_POOLED_EU: 92 value = HAS_POOLED_EU(i915); 93 break; 94 case I915_PARAM_MIN_EU_IN_POOL: 95 value = sseu->min_eu_in_pool; 96 break; 97 case I915_PARAM_HUC_STATUS: 98 value = intel_huc_check_status(&i915->gt.uc.huc); 99 if (value < 0) 100 return value; 101 break; 102 case I915_PARAM_MMAP_GTT_VERSION: 103 /* Though we've started our numbering from 1, and so class all 104 * earlier versions as 0, in effect their value is undefined as 105 * the ioctl will report EINVAL for the unknown param! 106 */ 107 value = i915_gem_mmap_gtt_version(); 108 break; 109 case I915_PARAM_HAS_SCHEDULER: 110 value = i915->caps.scheduler; 111 break; 112 113 case I915_PARAM_MMAP_VERSION: 114 /* Remember to bump this if the version changes! */ 115 case I915_PARAM_HAS_GEM: 116 case I915_PARAM_HAS_PAGEFLIPPING: 117 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */ 118 case I915_PARAM_HAS_RELAXED_FENCING: 119 case I915_PARAM_HAS_COHERENT_RINGS: 120 case I915_PARAM_HAS_RELAXED_DELTA: 121 case I915_PARAM_HAS_GEN7_SOL_RESET: 122 case I915_PARAM_HAS_WAIT_TIMEOUT: 123 case I915_PARAM_HAS_PRIME_VMAP_FLUSH: 124 case I915_PARAM_HAS_PINNED_BATCHES: 125 case I915_PARAM_HAS_EXEC_NO_RELOC: 126 case I915_PARAM_HAS_EXEC_HANDLE_LUT: 127 case I915_PARAM_HAS_COHERENT_PHYS_GTT: 128 case I915_PARAM_HAS_EXEC_SOFTPIN: 129 case I915_PARAM_HAS_EXEC_ASYNC: 130 case I915_PARAM_HAS_EXEC_FENCE: 131 case I915_PARAM_HAS_EXEC_CAPTURE: 132 case I915_PARAM_HAS_EXEC_BATCH_FIRST: 133 case I915_PARAM_HAS_EXEC_FENCE_ARRAY: 134 case I915_PARAM_HAS_EXEC_SUBMIT_FENCE: 135 /* For the time being all of these are always true; 136 * if some supported hardware does not have one of these 137 * features this value needs to be provided from 138 * INTEL_INFO(), a feature macro, or similar. 139 */ 140 value = 1; 141 break; 142 case I915_PARAM_HAS_CONTEXT_ISOLATION: 143 value = intel_engines_has_context_isolation(i915); 144 break; 145 case I915_PARAM_SLICE_MASK: 146 value = sseu->slice_mask; 147 if (!value) 148 return -ENODEV; 149 break; 150 case I915_PARAM_SUBSLICE_MASK: 151 value = sseu->subslice_mask[0]; 152 if (!value) 153 return -ENODEV; 154 break; 155 case I915_PARAM_CS_TIMESTAMP_FREQUENCY: 156 value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz; 157 break; 158 case I915_PARAM_MMAP_GTT_COHERENT: 159 value = INTEL_INFO(i915)->has_coherent_ggtt; 160 break; 161 case I915_PARAM_PERF_REVISION: 162 value = i915_perf_ioctl_version(); 163 break; 164 case I915_PARAM_IS_GVT: > 165 value = intel_vgpu_active(i915); --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 34625 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200617/14f9d085/attachment-0001.gz> From ville.syrjala at linux.intel.com Tue Jun 16 16:39:09 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 19:39:09 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ In-Reply-To: <20200616163406.27387-1-matthew.s.atwood@intel.com> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> Message-ID: <20200616163909.GF6112@intel.com> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote: > Add minimum width to planes, variable with specific formats, for gen11+. How did this suddenly become gen11+? Wasn't it rkl only before? > > Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++--- > 1 file changed, 47 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 7457813ef273..d4fdad6cb3b1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb, > } > } > > +static int icl_min_plane_width(struct drm_i915_private *dev_priv, > + const struct drm_framebuffer *fb) > +{ > + /* Wa_14011264657, Wa_14011050563 */ > + switch (fb->format->format) { > + case DRM_FORMAT_C8: > + return 18; > + case DRM_FORMAT_RGB565: > + return 10; > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ARGB8888: > + case DRM_FORMAT_ABGR8888: > + case DRM_FORMAT_XRGB2101010: > + case DRM_FORMAT_XBGR2101010: > + case DRM_FORMAT_ARGB2101010: > + case DRM_FORMAT_ABGR2101010: > + case DRM_FORMAT_XVYU2101010: > + case DRM_FORMAT_Y212: > + case DRM_FORMAT_Y216: > + return 6; > + case DRM_FORMAT_NV12: > + return 20; > + case DRM_FORMAT_P010: > + case DRM_FORMAT_P012: > + case DRM_FORMAT_P016: > + return 12; > + case DRM_FORMAT_XRGB16161616F: > + case DRM_FORMAT_XBGR16161616F: > + case DRM_FORMAT_ARGB16161616F: > + case DRM_FORMAT_ABGR16161616F: > + case DRM_FORMAT_XVYU12_16161616: > + case DRM_FORMAT_XVYU16161616: > + return 4; > + default: > + return 1; > + } > +} > + > static int icl_max_plane_width(const struct drm_framebuffer *fb, > int color_plane, > unsigned int rotation) > @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > int y = plane_state->uapi.src.y1 >> 16; > int w = drm_rect_width(&plane_state->uapi.src) >> 16; > int h = drm_rect_height(&plane_state->uapi.src) >> 16; > - int max_width; > - int max_height; > - u32 alignment; > - u32 offset; > + int max_width, min_width = 1, max_height; > + u32 alignment, offset; > int aux_plane = intel_main_to_aux_plane(fb, 0); > u32 aux_offset = plane_state->color_plane[aux_plane].offset; > > - if (INTEL_GEN(dev_priv) >= 11) > + if (INTEL_GEN(dev_priv) >= 11) { > max_width = icl_max_plane_width(fb, 0, rotation); > + min_width = icl_min_plane_width(dev_priv, fb); > + } > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > max_width = glk_max_plane_width(fb, 0, rotation); > else > @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > else > max_height = skl_max_plane_height(); > > - if (w > max_width || h > max_height) { > + if (w > max_width || w < min_width || h > max_height) { > drm_dbg_kms(&dev_priv->drm, > - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n", > - w, h, max_width, max_height); > + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", > + w, h, min_width, max_width, max_height); > return -EINVAL; > } > > -- > 2.21.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 16 16:40:47 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 19:40:47 +0300 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616162321.GE6112@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-6-imre.deak@intel.com> <20200616154546.GY6112@intel.com> <20200616155441.GC21389@ideak-desk.fi.intel.com> <20200616162321.GE6112@intel.com> Message-ID: <20200616164047.GG6112@intel.com> On Tue, Jun 16, 2020 at 07:23:21PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 06:54:41PM +0300, Imre Deak wrote: > > On Tue, Jun 16, 2020 at 06:45:46PM +0300, Ville Syrj?l? wrote: > > > On Tue, Jun 16, 2020 at 05:18:55PM +0300, Imre Deak wrote: > > > > Atm, we clear the ACT sent flag in the sink's DPCD before updating the > > > > sink's payload table, along clearing the payload table updated flag. > > > > The sink is supposed to set this flag once it detects that the source > > > > has completed the ACT sequence (after detecting the 4 required ACT MTPH > > > > symbols sent by the source). As opposed to this 2 DELL monitors I have > > > > set the flag already along the payload table updated flag, which is not > > > > quite correct. > > > > > > > > To be sure that the sink has detected the ACT MTPH symbols before > > > > continuing enabling the encoder, clear the ACT sent flag before enabling > > > > or disabling the transcoder VC payload allocation (which is what starts > > > > the ACT sequence). > > > > > > > > Cc: Lyude Paul <lyude at redhat.com> > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Cc: dri-devel at lists.freedesktop.org > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > --- > > > > drivers/gpu/drm/drm_dp_mst_topology.c | 31 +++++++++++++++++++-- > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > > > > include/drm/drm_dp_mst_helper.h | 2 ++ > > > > 3 files changed, 33 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > > > index b2f5a84b4cfb..e3bf8c9c8267 100644 > > > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > > > @@ -4377,6 +4377,34 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, > > > > } > > > > EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); > > > > > > > > +/** > > > > + * drm_dp_clear_payload_status() - Clears the payload table status flags > > > > + * @mgr: manager to use > > > > + * > > > > + * Clears the payload table ACT handled and table updated flags in the MST hub's > > > > + * DPCD. This function must be called before updating the payload table or > > > > + * starting the ACT sequence and waiting for the corresponding flags to get > > > > + * set by the hub. > > > > + * > > > > + * Returns: > > > > + * 0 if the flag got cleared successfully, otherwise a negative error code. > > > > + */ > > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) > > > > +{ > > > > + int ret; > > > > + > > > > + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > > > + DP_PAYLOAD_ACT_HANDLED); > > > > + if (ret < 0) { > > > > + DRM_DEBUG_DRIVER("Can't clear the ACT sent flag (%d)\n", ret); > > > > + return ret; > > > > + } > > > > + WARN_ON(ret != 1); > > > > + > > > > + return 0; > > > > +} > > > > +EXPORT_SYMBOL(drm_dp_clear_payload_status); > > > > + > > > > static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > > > int id, struct drm_dp_payload *payload) > > > > { > > > > @@ -4384,8 +4412,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > > > int ret; > > > > int retries = 0; > > > > > > > > - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > > > - DP_PAYLOAD_TABLE_UPDATED); > > > > > > We used to clear DP_PAYLOAD_TABLE_UPDATED but now we clear > > > DP_PAYLOAD_ACT_HANDLED ? > > > > Eek. We should write DP_PAYLOAD_TABLE_UPDATED which is the only way to > > clear both the act-handled and the table-updated flags. > > Huh. That's a bit crazy. But it is what the spec says. In fact, I'd suggest adding a comment explaining this crazyness so that the next person doesn't have to wonder why we're never clearing the ACT bit. > > > I tested things > > that way but managed to send an old version. Thanks for catching it. > > > > > > > > > + drm_dp_clear_payload_status(mgr); > > > > > > > > payload_alloc[0] = id; > > > > payload_alloc[1] = payload->start_slot; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > > index 9308b5920780..3c4b0fb10d8b 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > > @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) > > > > > > > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > > > > DP_TP_STATUS_ACT_SENT); > > > > + > > > > + drm_dp_clear_payload_status(&intel_dp->mst_mgr); > > > > } > > > > > > > > static void wait_for_act_sent(struct intel_dp *intel_dp) > > > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > > > > index 8b9eb4db3381..2facb87624bf 100644 > > > > --- a/include/drm/drm_dp_mst_helper.h > > > > +++ b/include/drm/drm_dp_mst_helper.h > > > > @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, > > > > int pbn); > > > > > > > > > > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); > > > > + > > > > int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); > > > > > > > > > > > > -- > > > > 2.23.1 > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Ville Syrj?l? Intel From imre.deak at intel.com Tue Jun 16 16:42:09 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 19:42:09 +0300 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders In-Reply-To: <4c40d13cfdb9cfe4d59eb04f27828b597949c54e.camel@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <4c40d13cfdb9cfe4d59eb04f27828b597949c54e.camel@intel.com> Message-ID: <20200616164209.GD21389@ideak-desk.fi.intel.com> On Tue, Jun 16, 2020 at 07:32:46PM +0300, Souza, Jose wrote: > On Tue, 2020-06-16 at 17:18 +0300, Imre Deak wrote: > > MST encoders must use the master MST transcoder's DP_TP_STATUS and > > DP_TP_CONTROL registers. Atm, during the HW readout of a slave > > transcoder's CRTC state we reset these register addresses in > > intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register > > addresses incorrectly; fix this. > > > > This issue led at least to > > 'Timed out waiting for ACT sent when disabling' > > errors during output disabling in a multiple MST stream config. > > Can you point to place where dp_tp_ctl is used and cause this? All > the MST code paths uses the dp_tp_ctl of the main intel_dp(the one > that is not a mst connector). During a slave stream disabling when waiting for the ACT sent flag for that stream. > > > > > This change replaces > > https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 > > which just papered over the problem. > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- > > 1 file changed, 10 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index ca7bb2294d2b..73d6cc29291a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) > > return; > > > > - if (INTEL_GEN(dev_priv) >= 12) { > > - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); > > - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); > > - } > > - > > intel_dsc_get_config(encoder, pipe_config); > > > > temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); > > @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > break; > > } > > > > + if (INTEL_GEN(dev_priv) >= 12) { > > + enum transcoder transcoder = > > + intel_dp_mst_is_slave_trans(pipe_config) ? > > + pipe_config->mst_master_transcoder : > > + pipe_config->cpu_transcoder; > > + > > + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); > > + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); > > + } > > Also not sure how change only in the config readout would fix the issue, After a modeset we'll verify the HW state. The readout for a slave stream CRTC (get_pipe_config) running after the master CRTC's readout will overwrite the dp_tp reg addresses. The other instance of dp_tp register address init (in tgl_ddi_pre_enable_dp()) is correct. > IFWI don't enable MST so when i915 takes over a full modeset will > happen to enable MST and only dp_tp_ctl of the main intel_dp(the one > that is not a mst connector) will be set, check > tgl_ddi_pre_enable_dp(). > > > + > > pipe_config->has_audio = > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); > > From imre.deak at intel.com Tue Jun 16 16:47:53 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 19:47:53 +0300 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616164047.GG6112@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616141855.746-6-imre.deak@intel.com> <20200616154546.GY6112@intel.com> <20200616155441.GC21389@ideak-desk.fi.intel.com> <20200616162321.GE6112@intel.com> <20200616164047.GG6112@intel.com> Message-ID: <20200616164753.GE21389@ideak-desk.fi.intel.com> On Tue, Jun 16, 2020 at 07:40:47PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 07:23:21PM +0300, Ville Syrj?l? wrote: > > On Tue, Jun 16, 2020 at 06:54:41PM +0300, Imre Deak wrote: > > > On Tue, Jun 16, 2020 at 06:45:46PM +0300, Ville Syrj?l? wrote: > > > > On Tue, Jun 16, 2020 at 05:18:55PM +0300, Imre Deak wrote: > > > > > Atm, we clear the ACT sent flag in the sink's DPCD before updating the > > > > > sink's payload table, along clearing the payload table updated flag. > > > > > The sink is supposed to set this flag once it detects that the source > > > > > has completed the ACT sequence (after detecting the 4 required ACT MTPH > > > > > symbols sent by the source). As opposed to this 2 DELL monitors I have > > > > > set the flag already along the payload table updated flag, which is not > > > > > quite correct. > > > > > > > > > > To be sure that the sink has detected the ACT MTPH symbols before > > > > > continuing enabling the encoder, clear the ACT sent flag before enabling > > > > > or disabling the transcoder VC payload allocation (which is what starts > > > > > the ACT sequence). > > > > > > > > > > Cc: Lyude Paul <lyude at redhat.com> > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > Cc: dri-devel at lists.freedesktop.org > > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > > --- > > > > > drivers/gpu/drm/drm_dp_mst_topology.c | 31 +++++++++++++++++++-- > > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > > > > > include/drm/drm_dp_mst_helper.h | 2 ++ > > > > > 3 files changed, 33 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > > > > index b2f5a84b4cfb..e3bf8c9c8267 100644 > > > > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > > > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > > > > @@ -4377,6 +4377,34 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, > > > > > } > > > > > EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); > > > > > > > > > > +/** > > > > > + * drm_dp_clear_payload_status() - Clears the payload table status flags > > > > > + * @mgr: manager to use > > > > > + * > > > > > + * Clears the payload table ACT handled and table updated flags in the MST hub's > > > > > + * DPCD. This function must be called before updating the payload table or > > > > > + * starting the ACT sequence and waiting for the corresponding flags to get > > > > > + * set by the hub. > > > > > + * > > > > > + * Returns: > > > > > + * 0 if the flag got cleared successfully, otherwise a negative error code. > > > > > + */ > > > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) > > > > > +{ > > > > > + int ret; > > > > > + > > > > > + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > > > > + DP_PAYLOAD_ACT_HANDLED); > > > > > + if (ret < 0) { > > > > > + DRM_DEBUG_DRIVER("Can't clear the ACT sent flag (%d)\n", ret); > > > > > + return ret; > > > > > + } > > > > > + WARN_ON(ret != 1); > > > > > + > > > > > + return 0; > > > > > +} > > > > > +EXPORT_SYMBOL(drm_dp_clear_payload_status); > > > > > + > > > > > static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > > > > int id, struct drm_dp_payload *payload) > > > > > { > > > > > @@ -4384,8 +4412,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > > > > > int ret; > > > > > int retries = 0; > > > > > > > > > > - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > > > > > - DP_PAYLOAD_TABLE_UPDATED); > > > > > > > > We used to clear DP_PAYLOAD_TABLE_UPDATED but now we clear > > > > DP_PAYLOAD_ACT_HANDLED ? > > > > > > Eek. We should write DP_PAYLOAD_TABLE_UPDATED which is the only way to > > > clear both the act-handled and the table-updated flags. > > > > Huh. That's a bit crazy. But it is what the spec says. > > In fact, I'd suggest adding a comment explaining this crazyness > so that the next person doesn't have to wonder why we're never > clearing the ACT bit. Ok. > > > > > > I tested things > > > that way but managed to send an old version. Thanks for catching it. > > > > > > > > > > > > + drm_dp_clear_payload_status(mgr); > > > > > > > > > > payload_alloc[0] = id; > > > > > payload_alloc[1] = payload->start_slot; > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > > > index 9308b5920780..3c4b0fb10d8b 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > > > > @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) > > > > > > > > > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > > > > > DP_TP_STATUS_ACT_SENT); > > > > > + > > > > > + drm_dp_clear_payload_status(&intel_dp->mst_mgr); > > > > > } > > > > > > > > > > static void wait_for_act_sent(struct intel_dp *intel_dp) > > > > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > > > > > index 8b9eb4db3381..2facb87624bf 100644 > > > > > --- a/include/drm/drm_dp_mst_helper.h > > > > > +++ b/include/drm/drm_dp_mst_helper.h > > > > > @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, > > > > > int pbn); > > > > > > > > > > > > > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); > > > > > + > > > > > int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); > > > > > > > > > > > > > > > -- > > > > > 2.23.1 > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > > > -- > > Ville Syrj?l? > > Intel > > _______________________________________________ > > dri-devel mailing list > > dri-devel at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > > -- > Ville Syrj?l? > Intel From jose.souza at intel.com Tue Jun 16 17:02:10 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 16 Jun 2020 17:02:10 +0000 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders In-Reply-To: <20200616164209.GD21389@ideak-desk.fi.intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <4c40d13cfdb9cfe4d59eb04f27828b597949c54e.camel@intel.com> <20200616164209.GD21389@ideak-desk.fi.intel.com> Message-ID: <afab588c525d40b6b02347645808ce159bc4b44b.camel@intel.com> On Tue, 2020-06-16 at 19:42 +0300, Imre Deak wrote: > On Tue, Jun 16, 2020 at 07:32:46PM +0300, Souza, Jose wrote: > > On Tue, 2020-06-16 at 17:18 +0300, Imre Deak wrote: > > > MST encoders must use the master MST transcoder's DP_TP_STATUS and > > > DP_TP_CONTROL registers. Atm, during the HW readout of a slave > > > transcoder's CRTC state we reset these register addresses in > > > intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register > > > addresses incorrectly; fix this. > > > > > > This issue led at least to > > > 'Timed out waiting for ACT sent when disabling' > > > errors during output disabling in a multiple MST stream config. > > > > Can you point to place where dp_tp_ctl is used and cause this? All > > the MST code paths uses the dp_tp_ctl of the main intel_dp(the one > > that is not a mst connector). > > During a slave stream disabling when waiting for the ACT sent flag for > that stream. > > > > This change replaces > > > https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 > > > which just papered over the problem. > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- > > > 1 file changed, 10 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index ca7bb2294d2b..73d6cc29291a 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > > if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) > > > return; > > > > > > - if (INTEL_GEN(dev_priv) >= 12) { > > > - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); > > > - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); > > > - } > > > - > > > intel_dsc_get_config(encoder, pipe_config); > > > > > > temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); > > > @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > > break; > > > } > > > > > > + if (INTEL_GEN(dev_priv) >= 12) { > > > + enum transcoder transcoder = > > > + intel_dp_mst_is_slave_trans(pipe_config) ? > > > + pipe_config->mst_master_transcoder : > > > + pipe_config->cpu_transcoder; > > > + > > > + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); > > > + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); > > > + } > > > > Also not sure how change only in the config readout would fix the issue, > > After a modeset we'll verify the HW state. The readout for a slave > stream CRTC (get_pipe_config) running after the master CRTC's readout > will overwrite the dp_tp reg addresses. The other instance of dp_tp > register address init (in tgl_ddi_pre_enable_dp()) is correct. intel_mst_post_disable_dp() struct intel_digital_port *intel_dig_port = intel_mst->primary; struct intel_dp *intel_dp = &intel_dig_port->dp; ... if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_ACT_SENT, 1)) drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when disabling\n"); Until here is right, but yeah bellow is the problem: static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); struct intel_digital_port *intel_dig_port = intel_mst->primary; intel_ddi_get_config(&intel_dig_port->base, pipe_config); } It will be overwritten with the transcoder of the last crtc read.Would suggest to add something about intel_dp_mst_enc_get_config() to the commit description but the change looks good now. > > > IFWI don't enable MST so when i915 takes over a full modeset will > > happen to enable MST and only dp_tp_ctl of the main intel_dp(the one > > that is not a mst connector) will be set, check > > tgl_ddi_pre_enable_dp(). > > > > > + > > > pipe_config->has_audio = > > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); > > > From matthew.s.atwood at intel.com Tue Jun 16 17:01:40 2020 From: matthew.s.atwood at intel.com (Matt Atwood) Date: Tue, 16 Jun 2020 10:01:40 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ In-Reply-To: <20200616163909.GF6112@intel.com> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> <20200616163909.GF6112@intel.com> Message-ID: <20200616170140.GA28232@msatwood-mobl> On Tue, Jun 16, 2020 at 07:39:09PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote: > > Add minimum width to planes, variable with specific formats, for gen11+. > > How did this suddenly become gen11+? Wasn't it rkl only before? gen11 platforms were currently in pending, that has changed. > > > > > Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++--- > > 1 file changed, 47 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 7457813ef273..d4fdad6cb3b1 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb, > > } > > } > > > > +static int icl_min_plane_width(struct drm_i915_private *dev_priv, > > + const struct drm_framebuffer *fb) > > +{ > > + /* Wa_14011264657, Wa_14011050563 */ > > + switch (fb->format->format) { > > + case DRM_FORMAT_C8: > > + return 18; > > + case DRM_FORMAT_RGB565: > > + return 10; > > + case DRM_FORMAT_XRGB8888: > > + case DRM_FORMAT_XBGR8888: > > + case DRM_FORMAT_ARGB8888: > > + case DRM_FORMAT_ABGR8888: > > + case DRM_FORMAT_XRGB2101010: > > + case DRM_FORMAT_XBGR2101010: > > + case DRM_FORMAT_ARGB2101010: > > + case DRM_FORMAT_ABGR2101010: > > + case DRM_FORMAT_XVYU2101010: > > + case DRM_FORMAT_Y212: > > + case DRM_FORMAT_Y216: > > + return 6; > > + case DRM_FORMAT_NV12: > > + return 20; > > + case DRM_FORMAT_P010: > > + case DRM_FORMAT_P012: > > + case DRM_FORMAT_P016: > > + return 12; > > + case DRM_FORMAT_XRGB16161616F: > > + case DRM_FORMAT_XBGR16161616F: > > + case DRM_FORMAT_ARGB16161616F: > > + case DRM_FORMAT_ABGR16161616F: > > + case DRM_FORMAT_XVYU12_16161616: > > + case DRM_FORMAT_XVYU16161616: > > + return 4; > > + default: > > + return 1; > > + } > > +} > > + > > static int icl_max_plane_width(const struct drm_framebuffer *fb, > > int color_plane, > > unsigned int rotation) > > @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > > int y = plane_state->uapi.src.y1 >> 16; > > int w = drm_rect_width(&plane_state->uapi.src) >> 16; > > int h = drm_rect_height(&plane_state->uapi.src) >> 16; > > - int max_width; > > - int max_height; > > - u32 alignment; > > - u32 offset; > > + int max_width, min_width = 1, max_height; > > + u32 alignment, offset; > > int aux_plane = intel_main_to_aux_plane(fb, 0); > > u32 aux_offset = plane_state->color_plane[aux_plane].offset; > > > > - if (INTEL_GEN(dev_priv) >= 11) > > + if (INTEL_GEN(dev_priv) >= 11) { > > max_width = icl_max_plane_width(fb, 0, rotation); > > + min_width = icl_min_plane_width(dev_priv, fb); > > + } > > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > max_width = glk_max_plane_width(fb, 0, rotation); > > else > > @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > > else > > max_height = skl_max_plane_height(); > > > > - if (w > max_width || h > max_height) { > > + if (w > max_width || w < min_width || h > max_height) { > > drm_dbg_kms(&dev_priv->drm, > > - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n", > > - w, h, max_width, max_height); > > + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", > > + w, h, min_width, max_width, max_height); > > return -EINVAL; > > } > > > > -- > > 2.21.3 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Tue Jun 16 17:06:49 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 20:06:49 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ In-Reply-To: <20200616170140.GA28232@msatwood-mobl> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> <20200616163909.GF6112@intel.com> <20200616170140.GA28232@msatwood-mobl> Message-ID: <20200616170649.GH6112@intel.com> On Tue, Jun 16, 2020 at 10:01:40AM -0700, Matt Atwood wrote: > On Tue, Jun 16, 2020 at 07:39:09PM +0300, Ville Syrj?l? wrote: > > On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote: > > > Add minimum width to planes, variable with specific formats, for gen11+. > > > > How did this suddenly become gen11+? Wasn't it rkl only before? > gen11 platforms were currently in pending, that has changed. What does "in pending" mean? > > > > > > > > Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++--- > > > 1 file changed, 47 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index 7457813ef273..d4fdad6cb3b1 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb, > > > } > > > } > > > > > > +static int icl_min_plane_width(struct drm_i915_private *dev_priv, > > > + const struct drm_framebuffer *fb) > > > +{ > > > + /* Wa_14011264657, Wa_14011050563 */ > > > + switch (fb->format->format) { > > > + case DRM_FORMAT_C8: > > > + return 18; > > > + case DRM_FORMAT_RGB565: > > > + return 10; > > > + case DRM_FORMAT_XRGB8888: > > > + case DRM_FORMAT_XBGR8888: > > > + case DRM_FORMAT_ARGB8888: > > > + case DRM_FORMAT_ABGR8888: > > > + case DRM_FORMAT_XRGB2101010: > > > + case DRM_FORMAT_XBGR2101010: > > > + case DRM_FORMAT_ARGB2101010: > > > + case DRM_FORMAT_ABGR2101010: > > > + case DRM_FORMAT_XVYU2101010: > > > + case DRM_FORMAT_Y212: > > > + case DRM_FORMAT_Y216: > > > + return 6; > > > + case DRM_FORMAT_NV12: > > > + return 20; > > > + case DRM_FORMAT_P010: > > > + case DRM_FORMAT_P012: > > > + case DRM_FORMAT_P016: > > > + return 12; > > > + case DRM_FORMAT_XRGB16161616F: > > > + case DRM_FORMAT_XBGR16161616F: > > > + case DRM_FORMAT_ARGB16161616F: > > > + case DRM_FORMAT_ABGR16161616F: > > > + case DRM_FORMAT_XVYU12_16161616: > > > + case DRM_FORMAT_XVYU16161616: > > > + return 4; > > > + default: > > > + return 1; > > > + } > > > +} > > > + > > > static int icl_max_plane_width(const struct drm_framebuffer *fb, > > > int color_plane, > > > unsigned int rotation) > > > @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > > > int y = plane_state->uapi.src.y1 >> 16; > > > int w = drm_rect_width(&plane_state->uapi.src) >> 16; > > > int h = drm_rect_height(&plane_state->uapi.src) >> 16; > > > - int max_width; > > > - int max_height; > > > - u32 alignment; > > > - u32 offset; > > > + int max_width, min_width = 1, max_height; > > > + u32 alignment, offset; > > > int aux_plane = intel_main_to_aux_plane(fb, 0); > > > u32 aux_offset = plane_state->color_plane[aux_plane].offset; > > > > > > - if (INTEL_GEN(dev_priv) >= 11) > > > + if (INTEL_GEN(dev_priv) >= 11) { > > > max_width = icl_max_plane_width(fb, 0, rotation); > > > + min_width = icl_min_plane_width(dev_priv, fb); > > > + } > > > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > > max_width = glk_max_plane_width(fb, 0, rotation); > > > else > > > @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > > > else > > > max_height = skl_max_plane_height(); > > > > > > - if (w > max_width || h > max_height) { > > > + if (w > max_width || w < min_width || h > max_height) { > > > drm_dbg_kms(&dev_priv->drm, > > > - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n", > > > - w, h, max_width, max_height); > > > + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", > > > + w, h, min_width, max_width, max_height); > > > return -EINVAL; > > > } > > > > > > -- > > > 2.21.3 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From daniel at ffwll.ch Tue Jun 16 17:10:23 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 16 Jun 2020 19:10:23 +0200 Subject: [Intel-gfx] [PATCH] drm/shmem-helper: Fix obj->filp derefence In-Reply-To: <a1290884-8cca-f1a1-a05b-8d5c3e323506@suse.de> References: <20200615151026.2339113-1-daniel.vetter@ffwll.ch> <a1290884-8cca-f1a1-a05b-8d5c3e323506@suse.de> Message-ID: <20200616171023.GP20149@phenom.ffwll.local> On Tue, Jun 16, 2020 at 02:10:10PM +0200, Thomas Zimmermann wrote: > Hi, > > as discussed on IRC, we still need this patch. > > Am 15.06.20 um 17:10 schrieb Daniel Vetter: > > I broke that in my refactoring: > > > > commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca > > Author: Daniel Vetter <daniel.vetter at ffwll.ch> > > Date: Fri May 29 16:05:42 2020 +0200 > > > > drm/shmem-helpers: Simplify dma-buf importing > > > > Reported-by: Thomas Zimmermann <tzimmermann at suse.de> > > Fixes: 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing") > > Cc: Boris Brezillon <boris.brezillon at collabora.com> > > Cc: Thomas Zimmermann <tzimmermann at suse.de> > > Cc: Gerd Hoffmann <kraxel at redhat.com> > > Cc: Rob Herring <robh at kernel.org> > > Cc: Noralf Tr?nnes <noralf at tronnes.org> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > --- > > drivers/gpu/drm/drm_gem_shmem_helper.c | 20 +++++++++++--------- > > 1 file changed, 11 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > > index 0a7e3b664bc2..3e7ee407a17c 100644 > > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > > @@ -70,15 +70,17 @@ __drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private) > > mutex_init(&shmem->vmap_lock); > > INIT_LIST_HEAD(&shmem->madv_list); > > > > - /* > > - * Our buffers are kept pinned, so allocating them > > - * from the MOVABLE zone is a really bad idea, and > > - * conflicts with CMA. See comments above new_inode() > > - * why this is required _and_ expected if you're > > - * going to pin these pages. > > - */ > > - mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | > > - __GFP_RETRY_MAYFAIL | __GFP_NOWARN); > > + if (!private) { > > I would test for (obj->filp) here, because it's what the branch depends > on. Your choice. In any case I was pondering this too, on one hand it's the thing we're using, otoh it's a direct consequence of the private flag, and the private flag has a bit the clearer control flow I think - the obj->filp is clear that it's a NULL check, but it's a lot less clear _why_ it is ok to have obj->filp == NULL. Checking for private makes this a bit clearer imo. But yeah I considered both options. Maybe we should improve the comment in a follow-up patch? I want to land the bugfix meanwhile, to close the regression. > Tested-by: Thomas Zimmermann <tzimmermann at suse.de> > Reviewed-by: Thomas Zimmermann <tzimmermann at suse.de> Thanks for testing and reviewing! -Daniel > > > > + /* > > + * Our buffers are kept pinned, so allocating them > > + * from the MOVABLE zone is a really bad idea, and > > + * conflicts with CMA. See comments above new_inode() > > + * why this is required _and_ expected if you're > > + * going to pin these pages. > > + */ > > + mapping_set_gfp_mask(obj->filp->f_mapping, GFP_HIGHUSER | > > + __GFP_RETRY_MAYFAIL | __GFP_NOWARN); > > + } > > > > return shmem; > > > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 N?rnberg, Germany > (HRB 36809, AG N?rnberg) > Gesch?ftsf?hrer: Felix Imend?rffer > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Tue Jun 16 17:10:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 17:10:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915=3A_fix_a_couple_of_spelling_mistakes_in_kernel_par?= =?utf-8?q?ameter_help_text?= In-Reply-To: <20200616082129.65517-1-colin.king@canonical.com> References: <20200616082129.65517-1-colin.king@canonical.com> Message-ID: <159232744948.4596.17293976881649935321@emeril.freedesktop.org> == Series Details == Series: drm/i915: fix a couple of spelling mistakes in kernel parameter help text URL : https://patchwork.freedesktop.org/series/78407/ State : warning == Summary == $ dim checkpatch origin/drm-tip b463d0076902 drm/i915: fix a couple of spelling mistakes in kernel parameter help text -:8: WARNING:TYPO_SPELLING: 'helpfull' may be misspelled - perhaps 'helpful'? #8: namely "helpfull" and "paramters". Fix them. -:8: WARNING:TYPO_SPELLING: 'paramters' may be misspelled - perhaps 'parameters'? #8: namely "helpfull" and "paramters". Fix them. total: 0 errors, 2 warnings, 0 checks, 10 lines checked From daniel at ffwll.ch Tue Jun 16 17:12:43 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 16 Jun 2020 19:12:43 +0200 Subject: [Intel-gfx] [PATCH] drm/shmem-helper: Only dma-buf imports are private obj In-Reply-To: <8c125158-fe7c-29a9-d9a8-9e6b418b6dd5@suse.de> References: <20200616114723.2363268-1-daniel.vetter@ffwll.ch> <8c125158-fe7c-29a9-d9a8-9e6b418b6dd5@suse.de> Message-ID: <20200616171243.GQ20149@phenom.ffwll.local> On Tue, Jun 16, 2020 at 02:06:24PM +0200, Thomas Zimmermann wrote: > Hi > > Am 16.06.20 um 13:47 schrieb Daniel Vetter: > > I broke that in my refactoring: > > > > commit 7d2cd72a9aa3df3604cafd169a2d4a525afb68ca > > Author: Daniel Vetter <daniel.vetter at ffwll.ch> > > Date: Fri May 29 16:05:42 2020 +0200 > > > > drm/shmem-helpers: Simplify dma-buf importing > > > > I'm not entirely sure of the history here, but I suspect that in one > > of the rebases or when applying the patch I moved the hunk from > > drm_gem_shmem_prime_import_sg_table(), where it should be, to > > drm_gem_shmem_create_with_handle(), which is totally wrong. > > > > Remedy this. > > > > Thanks for Thomas for the crucual hint in debugging this. > > > > Reported-by: Thomas Zimmermann <tzimmermann at suse.de> > > Fixes: 7d2cd72a9aa3 ("drm/shmem-helpers: Simplify dma-buf importing") > > Cc: Boris Brezillon <boris.brezillon at collabora.com> > > Cc: Thomas Zimmermann <tzimmermann at suse.de> > > Cc: Gerd Hoffmann <kraxel at redhat.com> > > Cc: Rob Herring <robh at kernel.org> > > Cc: Noralf Tr?nnes <noralf at tronnes.org> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Tested-by: Thomas Zimmermann <tzimmermann at suse.de> > Reviewed-by: Thomas Zimmermann <tzimmermann at suse.de> Now also merged, thanks a lot for your help. -Daniel > > > --- > > drivers/gpu/drm/drm_gem_shmem_helper.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c > > index 0a7e3b664bc2..837e0840990c 100644 > > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > > @@ -377,7 +377,7 @@ drm_gem_shmem_create_with_handle(struct drm_file *file_priv, > > struct drm_gem_shmem_object *shmem; > > int ret; > > > > - shmem = __drm_gem_shmem_create(dev, size, true); > > + shmem = drm_gem_shmem_create(dev, size); > > if (IS_ERR(shmem)) > > return shmem; > > > > @@ -730,7 +730,7 @@ drm_gem_shmem_prime_import_sg_table(struct drm_device *dev, > > size_t size = PAGE_ALIGN(attach->dmabuf->size); > > struct drm_gem_shmem_object *shmem; > > > > - shmem = drm_gem_shmem_create(dev, size); > > + shmem = __drm_gem_shmem_create(dev, size, true); > > if (IS_ERR(shmem)) > > return ERR_CAST(shmem); > > > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 N?rnberg, Germany > (HRB 36809, AG N?rnberg) > Gesch?ftsf?hrer: Felix Imend?rffer > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From daniel.vetter at ffwll.ch Tue Jun 16 17:16:45 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 16 Jun 2020 19:16:45 +0200 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <CACvgo51ZObyCiOeV+cdJo6xJ3ahuvBUxx1DrK+emDHTOfmVA_g@mail.gmail.com> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-7-daniel.vetter@ffwll.ch> <CACvgo51AVVOxhGK2Uin=ZLgPpihJiEsnc6pvAyKqFKPvLdOzLA@mail.gmail.com> <CAKMK7uEEkH+8BuFcFUVTv6p8swZZTwcho-HNx5GdZTO1vHDoeg@mail.gmail.com> <CACvgo51ZObyCiOeV+cdJo6xJ3ahuvBUxx1DrK+emDHTOfmVA_g@mail.gmail.com> Message-ID: <CAKMK7uFkXzMMWqaS52K6_tdi-xbsqWTySQATpJewLDL_ebXiMA@mail.gmail.com> On Tue, Jun 16, 2020 at 3:57 PM Emil Velikov <emil.l.velikov at gmail.com> wrote: > > On Tue, 16 Jun 2020 at 07:50, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > On Mon, Jun 15, 2020 at 11:35 PM Emil Velikov <emil.l.velikov at gmail.com> wrote: > > > > > > Hi Daniel, > > > > > > On Fri, 12 Jun 2020 at 17:01, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > > > > > The atomic helpers try really hard to not lose track of things, > > > > duplicating enabled tracking in the driver is at best confusing. > > > > Double-enabling or disabling is a bug in atomic helpers. > > > > > > > > In the fb_dirty function we can just assume that the fb always exists, > > > > simple display pipe helpers guarantee that the crtc is only enabled > > > > together with the output, so we always have a primary plane around. > > > > > > > > Now in the update function we need to be a notch more careful, since > > > > that can also get called when the crtc is off. And we don't want to > > > > upload frames when that's the case, so filter that out too. > > > > > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > > Cc: Maxime Ripard <mripard at kernel.org> > > > > Cc: Thomas Zimmermann <tzimmermann at suse.de> > > > > Cc: David Airlie <airlied at linux.ie> > > > > Cc: Daniel Vetter <daniel at ffwll.ch> > > > > Cc: David Lechner <david at lechnology.com> > > > > --- > > > > drivers/gpu/drm/drm_mipi_dbi.c | 16 ++++++---------- > > > > drivers/gpu/drm/tiny/ili9225.c | 12 +++--------- > > > > drivers/gpu/drm/tiny/st7586.c | 11 +++-------- > > > > include/drm/drm_mipi_dbi.h | 5 ----- > > > > 4 files changed, 12 insertions(+), 32 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c > > > > index fd8d672972a9..79532b9a324a 100644 > > > > --- a/drivers/gpu/drm/drm_mipi_dbi.c > > > > +++ b/drivers/gpu/drm/drm_mipi_dbi.c > > > > @@ -268,7 +268,7 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) > > > > bool full; > > > > void *tr; > > > > > > > > - if (!dbidev->enabled) > > > > + if (WARN_ON(!fb)) > > > > return; > > > > > > > AFAICT no other driver has such WARN_ON. Let's drop that - it is > > > pretty confusing and misleading as-is. > > > > Yeah, this is a helper library which might be used wrongly by drivers. > > That's why I put it in - if you don't put all the various calls > > together correctly, this should at least catch one case. So really > > would like to keep this, can I convince you? > > There are plenty of similar places where a drm library/helper can be > misused, lacking a WARN. Nevertheless - sure feel free to keep it. Yeah I agree, we can't check for everything. Personally I think a check is warranted in two conditions: - drivers got it wrong, and the WARNING helps catch driver-bugs we've seen in the wild. Not really the case here - drivers do check something as defensive programming, but it's an invariant enforced by higher levels or helpers. Those I like to convert to WARNING so that other driver authors learn that this should never happen. This is such a case imo, I removed a bunch of fb checks from drivers here. But yeah I think we should only add WARNING checks if this is actually something people have gotten wrong, otherwise there's just too many of them, distracting from the code. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From jose.souza at intel.com Tue Jun 16 17:29:12 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 16 Jun 2020 17:29:12 +0000 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch In-Reply-To: <421d8bd4ac0456ac448839194d535777424e6589.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-5-jose.souza@intel.com> <20200612163029.GK6112@intel.com> <ee0340f8ea128ed2caa4a6882ded6cb28bf0d8d9.camel@intel.com> <20200615164024.GQ6112@intel.com> <421d8bd4ac0456ac448839194d535777424e6589.camel@intel.com> Message-ID: <c6ab07cda882b2252030b417a938af8d2b0accab.camel@intel.com> On Tue, 2020-06-16 at 16:16 +0100, Mun, Gwan-gyeong wrote: > On Mon, 2020-06-15 at 19:40 +0300, Ville Syrj?l? wrote: > > On Fri, Jun 12, 2020 at 08:33:31PM +0000, Souza, Jose wrote: > > > On Fri, 2020-06-12 at 19:30 +0300, Ville Syrj?l? wrote: > > > > On Tue, May 26, 2020 at 03:14:46PM -0700, Jos? Roberto de Souza > > > > wrote: > > > > > All GEN12 platforms supports PSR2 selective fetch but not all > > > > > GEN12 > > > > > platforms supports PSR2 hardware tracking(aka RKL). > > > > > > > > > > This feature consists in software program registers with the > > > > > damaged > > > > > area of each plane this way hardware will only fetch from > > > > > memory those > > > > > areas and sent the PSR2 selective update blocks to panel, > > > > > saving even > > > > > more power but to it actually happen userspace needs to send > > > > > the > > > > > damaged areas otherwise it will still fetch the whole plane as > > > > > fallback. > > > > > As today Gnome3 do not send damaged areas and the only > > > > > compositor that > > > > > I'm aware that sets the damaged areas is Weston. > > > > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > > > > > > > > > So here implementing page flip part, it is still completely > > > > > missing > > > > > frontbuffer modifications, that is why the > > > > > enable_psr2_sel_fetch > > > > > parameter was added. > > > > > > > > > > The plan is to switch all GEN12 platforms to selective fetch > > > > > when > > > > > ready, it will also depend in add some tests sending damaged > > > > > areas. > > > > > I have a hacked version of kms_psr2_su with 3 planes that I can > > > > > cleanup and send in a few days(99% of PSR2 selective fetch > > > > > changes was > > > > > done during my free time while bored during quarantine rainy > > > > > days). > > > > > > > > > > BSpec: 55229 > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > Cc: Imre Deak <imre.deak at intel.com> > > > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > > > > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_display.c | 5 + > > > > > .../drm/i915/display/intel_display_debugfs.c | 3 + > > > > > .../drm/i915/display/intel_display_types.h | 10 + > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 329 > > > > > +++++++++++++++++- > > > > > drivers/gpu/drm/i915/display/intel_psr.h | 10 + > > > > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 + > > > > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > > > > drivers/gpu/drm/i915/i915_params.c | 5 + > > > > > drivers/gpu/drm/i915/i915_params.h | 1 + > > > > > 9 files changed, 352 insertions(+), 15 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > > index b69878334040..984809208c29 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > @@ -11729,6 +11729,8 @@ static void i9xx_update_cursor(struct > > > > > intel_plane *plane, > > > > > if (INTEL_GEN(dev_priv) >= 9) > > > > > skl_write_cursor_wm(plane, crtc_state); > > > > > > > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, > > > > > plane_state); > > > > > + > > > > > if (plane->cursor.base != base || > > > > > plane->cursor.size != fbc_ctl || > > > > > plane->cursor.cntl != cntl) { > > > > > @@ -15115,6 +15117,8 @@ static void commit_pipe_config(struct > > > > > intel_atomic_state *state, > > > > > > > > > > if (new_crtc_state->update_pipe) > > > > > intel_pipe_fastset(old_crtc_state, > > > > > new_crtc_state); > > > > > + > > > > > + intel_psr2_program_trans_man_trk_ctl(new_crtc_s > > > > > tate); > > > > > } > > > > > > > > > > if (dev_priv->display.atomic_update_watermarks) > > > > > @@ -15156,6 +15160,7 @@ static void intel_update_crtc(struct > > > > > intel_atomic_state *state, > > > > > intel_color_load_luts(new_crtc_state); > > > > > > > > > > intel_pre_plane_update(state, crtc); > > > > > + intel_psr2_sel_fetch_update(state, crtc); > > > > > > > > > > if (new_crtc_state->update_pipe) > > > > > intel_encoders_update_pipe(state, > > > > > crtc); > > > > > diff --git > > > > > a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > index 70525623bcdf..0f600974462b 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct > > > > > seq_file *m, void *data) > > > > > su_blocks = su_blocks >> > > > > > PSR2_SU_STATUS_SHIFT(frame); > > > > > seq_printf(m, "%d\t%d\n", frame, > > > > > su_blocks); > > > > > } > > > > > + > > > > > + seq_printf(m, "PSR2 selective fetch: %s\n", > > > > > + enableddisabled(psr- > > > > > > psr2_sel_fetch_enabled)); > > > > > } > > > > > > > > > > unlock: > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > index 30b2767578dc..b77a512e5362 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > @@ -586,6 +586,13 @@ struct intel_plane_state { > > > > > u32 planar_slave; > > > > > > > > > > struct drm_intel_sprite_colorkey ckey; > > > > > + > > > > > + struct { > > > > > + u32 ctl; > > > > > + u32 pos; > > > > > + u32 offset; > > > > > + u32 size; > > > > > + } psr2_sel_fetch; > > > > > > > > Do we really need all that here? We don't store them for the > > > > normal > > > > plane updates either. > > > > > > For ctl we do, anyways could be removed if we store overlapping > > > damage are in here so intel_psr2_program_plane_sel_fetch() would > > > incorporate > > > intel_psr2_plane_sel_fetch_calc() code, both looks good to me. > > > > > > > > }; > > > > > > > > > > struct intel_initial_plane_config { > > > > > @@ -931,6 +938,7 @@ struct intel_crtc_state { > > > > > > > > > > bool has_psr; > > > > > bool has_psr2; > > > > > + bool enable_psr2_sel_fetch; > > > > > u32 dc3co_exitline; > > > > > > > > > > /* > > > > > @@ -1070,6 +1078,8 @@ struct intel_crtc_state { > > > > > > > > > > /* For DSB related info */ > > > > > struct intel_dsb *dsb; > > > > > + > > > > > + u32 psr2_sw_man_track_ctl; > > > > > }; > > > > > > > > > > enum intel_pipe_crc_source { > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > > > index 0c86e9e341a2..bc2a2e64fe2a 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > > > @@ -518,6 +518,14 @@ static void hsw_activate_psr2(struct > > > > > intel_dp *intel_dp) > > > > > else > > > > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > > > > > > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > > > > > + intel_de_write(dev_priv, > > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > > > psr.transcoder), > > > > > + PSR2_MAN_TRK_CTL_ENABLE); > > > > > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > > > > > + intel_de_write(dev_priv, > > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > > > psr.transcoder), 0); > > > > > + > > > > > /* > > > > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and > > > > > BSpec is > > > > > * recommending keep this bit unset while PSR2 is > > > > > enabled. > > > > > @@ -628,6 +636,38 @@ tgl_dc3co_exitline_compute_config(struct > > > > > intel_dp *intel_dp, > > > > > crtc_state->dc3co_exitline = crtc_vdisplay - > > > > > exit_scanlines; > > > > > } > > > > > > > > > > +static bool intel_psr2_sel_fetch_config_valid(struct intel_dp > > > > > *intel_dp, > > > > > + struct > > > > > intel_crtc_state *crtc_state) > > > > > +{ > > > > > + struct intel_atomic_state *state = > > > > > to_intel_atomic_state(crtc_state->uapi.state); > > > > > + struct drm_i915_private *dev_priv = > > > > > dp_to_i915(intel_dp); > > > > > + struct intel_plane_state *plane_state; > > > > > + struct intel_plane *plane; > > > > > + int i; > > > > > + > > > > > + if (!i915_modparams.enable_psr2_sel_fetch) { > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > + "PSR2 sel fetch not enabled, > > > > > disabled by parameter\n"); > > > > > + return false; > > > > > + } > > > > > + > > > > > + if (crtc_state->uapi.async_flip) { > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > + "PSR2 sel fetch not enabled, async > > > > > flip enabled\n"); > > > > > + return false; > > > > > + } > > > > > > > > Not supported anyway. > > > > > > > > > + > > > > > + for_each_new_intel_plane_in_state(state, plane, > > > > > plane_state, i) { > > > > > + if (plane_state->uapi.rotation != > > > > > DRM_MODE_ROTATE_0) { > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > + "PSR2 sel fetch not > > > > > enabled, plane rotated\n"); > > > > > + return false; > > > > > + } > > > > > + } > > > > > + > > > > > + return crtc_state->enable_psr2_sel_fetch = true; > > > > > +} > > > > > + > > > > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > > > > struct intel_crtc_state > > > > > *crtc_state) > > > > > { > > > > > @@ -697,22 +737,17 @@ static bool > > > > > intel_psr2_config_valid(struct intel_dp *intel_dp, > > > > > return false; > > > > > } > > > > > > > > > > - /* > > > > > - * Some platforms lack PSR2 HW tracking and instead > > > > > require manual > > > > > - * tracking by software. In this case, the driver is > > > > > required to track > > > > > - * the areas that need updates and program hardware to > > > > > send selective > > > > > - * updates. > > > > > - * > > > > > - * So until the software tracking is implemented, PSR2 > > > > > needs to be > > > > > - * disabled for platforms without PSR2 HW tracking. > > > > > - */ > > > > > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > > > > > - drm_dbg_kms(&dev_priv->drm, > > > > > - "No PSR2 HW tracking in the > > > > > platform\n"); > > > > > - return false; > > > > > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > > > > > + if > > > > > (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > > > > > + !HAS_PSR_HW_TRACKING(dev_priv)) { > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > + "PSR2 not enabled, > > > > > selective fetch not valid and no HW tracking available\n"); > > > > > + return false; > > > > > + } > > > > > } > > > > > > > > > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > > psr_max_v) { > > > > > + if (!crtc_state->enable_psr2_sel_fetch && > > > > > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > > psr_max_v)) { > > > > > drm_dbg_kms(&dev_priv->drm, > > > > > "PSR2 not enabled, resolution %dx%d > > > > > > max supported %dx%d\n", > > > > > crtc_hdisplay, crtc_vdisplay, > > > > > @@ -863,6 +898,11 @@ static void intel_psr_enable_source(struct > > > > > intel_dp *intel_dp, > > > > > val |= EXITLINE_ENABLE; > > > > > intel_de_write(dev_priv, > > > > > EXITLINE(cpu_transcoder), val); > > > > > } > > > > > + > > > > > + if (HAS_PSR_HW_TRACKING(dev_priv)) > > > > > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, > > > > > IGNORE_PSR2_HW_TRACKING, > > > > > + dev_priv- > > > > > > psr.psr2_sel_fetch_enabled ? > > > > > + IGNORE_PSR2_HW_TRACKING : 0); > > > > > } > > > > > > > > > > static void intel_psr_enable_locked(struct drm_i915_private > > > > > *dev_priv, > > > > > @@ -884,7 +924,7 @@ static void intel_psr_enable_locked(struct > > > > > drm_i915_private *dev_priv, > > > > > /* DC5/DC6 requires at least 6 idle frames */ > > > > > val = > > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > > > > > dev_priv->psr.dc3co_exit_delay = val; > > > > > - > > > > > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state- > > > > > > enable_psr2_sel_fetch; > > > > > /* > > > > > * If a PSR error happened and the driver is reloaded, > > > > > the EDP_PSR_IIR > > > > > * will still keep the error set even after the reset > > > > > done in the > > > > > @@ -1080,6 +1120,265 @@ static void > > > > > psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) > > > > > intel_psr_exit(dev_priv); > > > > > } > > > > > > > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane > > > > > *plane, > > > > > + const struct > > > > > intel_crtc_state *crtc_state, > > > > > + const struct > > > > > intel_plane_state *plane_state) > > > > > +{ > > > > > + struct drm_i915_private *dev_priv = to_i915(plane- > > > > > > base.dev); > > > > > + enum pipe pipe = plane->pipe; > > > > > + > > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > > + !plane_state || > > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > > + return; > > > > > + > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, > > > > > plane->id), > > > > > + plane_state->psr2_sel_fetch.ctl); > > > > > + if (!plane_state->psr2_sel_fetch.ctl || plane->id == > > > > > PLANE_CURSOR) > > > > > + return; > > > > > + > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, > > > > > plane->id), > > > > > + plane_state->psr2_sel_fetch.pos); > > > > > + intel_de_write_fw(dev_priv, > > > > > PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > > > > > + plane_state->psr2_sel_fetch.offset); > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, > > > > > plane->id), > > > > > + plane_state->psr2_sel_fetch.size); > > > > > +} > > > > > + > > > > > +void intel_psr2_program_trans_man_trk_ctl(const struct > > > > > intel_crtc_state *crtc_state) > > > > > +{ > > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state- > > > > > > uapi.crtc); > > > > > + struct drm_i915_private *dev_priv = to_i915(crtc- > > > > > > base.dev); > > > > > + struct i915_psr *psr = &dev_priv->psr; > > > > > + > > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > > + return; > > > > > + > > > > > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr- > > > > > > transcoder), > > > > > + crtc_state->psr2_sw_man_track_ctl); > > > > > +} > > > > > + > > > > > +static void intel_psr2_plane_sel_fetch_calc(struct > > > > > intel_plane_state *plane_state, > > > > > + struct drm_rect > > > > > *clip) > > > > > +{ > > > > > + int color_plane = plane_state->planar_linked_plane && > > > > > !plane_state->planar_slave; > > > > > + struct intel_plane *plane = to_intel_plane(plane_state- > > > > > > uapi.plane); > > > > > + u32 val; > > > > > + > > > > > + if (plane->id == PLANE_CURSOR) > > > > > + return; > > > > > + > > > > > + val = (plane_state->color_plane[color_plane].y + clip- > > > > > > y1) << 16; > > > > > + val |= plane_state->color_plane[color_plane].x; > > > > > + plane_state->psr2_sel_fetch.offset = val; > > > > > + > > > > > + val = (clip->y1 + plane_state->uapi.crtc_y) << 16; > > > > > + val |= plane_state->uapi.crtc_x; > > > > > + plane_state->psr2_sel_fetch.pos = val; > > > > > + > > > > > + /* Sizes are 0 based */ > > > > > + val = (clip->y2 - clip->y1 - 1) << 16; > > > > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - > > > > > 1; > > > > > + plane_state->psr2_sel_fetch.size = val; > > > > > +} > > > > > + > > > > > +static void intel_psr2_trans_man_trk_ctl_calc(struct > > > > > intel_crtc_state *crtc_state, > > > > > + struct drm_rect > > > > > *clip, > > > > > + bool full_update) > > > > > +{ > > > > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE; > > > > > + > > > > > + if (full_update) { > > > > > + val |= PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME; > > > > > + goto exit; > > > > > + } > > > > > + > > > > > + if (clip->y1 == -1) > > > > > + goto exit; > > > > > + > > > > > + val |= PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE; > > > > > + val |= PSR2_MAN_TRK_CTL_REGION_START_ADDR(clip->y1 / 4 > > > > > + 1); > > > > > + val |= > > > > > PSR2_MAN_TRK_CTL_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + > > > > > 1); > > > > > +exit: > > > > > + crtc_state->psr2_sw_man_track_ctl = val; > > > > > +} > > > > > + > > > > > +static void intel_psr2_plane_sel_fetch_ctl_calc(struct > > > > > intel_plane *plane, > > > > > + struct > > > > > intel_plane_state *plane_state, > > > > > + bool enable) > > > > > +{ > > > > > + if (!enable) > > > > > + plane_state->psr2_sel_fetch.ctl = 0; > > > > > + else if (plane->id == PLANE_CURSOR) > > > > > + plane_state->psr2_sel_fetch.ctl = plane- > > > > > > cursor.cntl; > > > > > + else > > > > > + plane_state->psr2_sel_fetch.ctl = plane_state- > > > > > > ctl; > > > > > +} > > > > > + > > > > > +static void clip_update(struct drm_rect *overlap_damage_area, > > > > > + struct drm_rect *damage_area) > > > > > +{ > > > > > + if (overlap_damage_area->y1 == -1) { > > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > > + return; > > > > > + } > > > > > + > > > > > + if (damage_area->y1 < overlap_damage_area->y1) > > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > > + > > > > > + if (damage_area->y2 > overlap_damage_area->y2) > > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > > +} > > > > > + > > > > > +/* Update plane damage area if planes above moved or have > > > > > alpha */ > > > > > +static void intel_psr2_pipe_dirty_areas_set(struct > > > > > intel_plane_state *plane_state, > > > > > + struct intel_plane > > > > > *plane, > > > > > + const struct > > > > > drm_rect *pipe_dirty_areas, > > > > > + struct drm_rect > > > > > *plane_clip) > > > > > +{ > > > > > + enum plane_id i; > > > > > + > > > > > + for (i = PLANE_CURSOR; i > plane->id; i--) { > > > > > + int j; > > > > > + > > > > > + for (j = 0; j < 2; j++) { > > > > > + struct drm_rect r = pipe_dirty_areas[i > > > > > * 2 + j]; > > > > > + > > > > > + if (!drm_rect_width(&r)) > > > > > + continue; > > > > > + if (!drm_rect_intersect(&r, > > > > > &plane_state->uapi.dst)) > > > > > + continue; > > > > > + > > > > > + r.y1 -= plane_state->uapi.crtc_y; > > > > > + r.y2 -= plane_state->uapi.crtc_y; > > > > > + clip_update(plane_clip, &r); > > > > > + } > > > > > + } > > > > > +} > > > > > + > > > > > +void intel_psr2_sel_fetch_update(struct intel_atomic_state > > > > > *state, > > > > > + struct intel_crtc *crtc) > > > > > +{ > > > > > + struct intel_crtc_state *crtc_state = > > > > > intel_atomic_get_new_crtc_state(state, crtc); > > > > > + struct intel_plane_state *new_plane_state, > > > > > *old_plane_state; > > > > > + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = > > > > > {}; > > > > > + struct drm_rect pipe_clip = { .y1 = -1 }; > > > > > + struct intel_plane *plane; > > > > > + bool full_update = false; > > > > > + int i; > > > > > + > > > > > + if (!crtc_state->enable_psr2_sel_fetch) > > > > > + return; > > > > > + > > > > > + /* > > > > > + * Load all the pipes areas where there is a plane with > > > > > alpha or a plane > > > > > + * that moved or plane that the visibility changed in > > > > > those > > > > > + * cases planes bellow it will need to be fetched in > > > > > those intersection > > > > > + * areas even if they are not damaged in those areas. > > > > > + */ > > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > > old_plane_state, > > > > > + new_plane_state, > > > > > i) { > > > > > + bool alpha, flip, dirty; > > > > > + > > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > > > uapi.crtc) > > > > > + continue; > > > > > + > > > > > + alpha = new_plane_state->uapi.alpha != U16_MAX; > > > > > + alpha |= old_plane_state->uapi.alpha != > > > > > U16_MAX; > > > > > + flip = new_plane_state->uapi.fb != > > > > > old_plane_state->uapi.fb; > > > > > + dirty = alpha && flip; > > > > > + dirty |= !drm_rect_equals(&new_plane_state- > > > > > > uapi.dst, > > > > > + &old_plane_state- > > > > > > uapi.dst); > > > > > + dirty |= new_plane_state->uapi.visible != > > > > > + old_plane_state->uapi.visible; > > > > > + if (!dirty) > > > > > + continue; > > > > > + > > > > > + if (old_plane_state->uapi.visible) > > > > > + pipe_dirty_areas[plane->id * 2] = > > > > > old_plane_state->uapi.dst; > > > > > + if (new_plane_state->uapi.visible) > > > > > + pipe_dirty_areas[plane->id * 2 + 1] = > > > > > new_plane_state->uapi.dst; > > > > > + } > > > > > + > > > > > + /* > > > > > + * Iterate over all planes, compute the damaged clip > > > > > area also including > > > > > + * the pipe_dirty_areas, compute plane registers and > > > > > update pipe damaged > > > > > + * area > > > > > + */ > > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > > old_plane_state, > > > > > + new_plane_state, > > > > > i) { > > > > > + struct drm_rect plane_clip = { .y1 = -1 }; > > > > > + struct drm_mode_rect *clips; > > > > > + u32 num_clips; > > > > > + int j; > > > > > + > > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > > > uapi.crtc) > > > > > + continue; > > > > > + > > > > > + /* > > > > > + * TODO: Not clear how to handle planes with > > > > > negative position, > > > > > + * also planes are not updated if they have a > > > > > negative X > > > > > + * position so for now doing a full update in > > > > > this cases > > > > > + */ > > > > > + if (new_plane_state->uapi.crtc_y < 0 || > > > > > + new_plane_state->uapi.crtc_x < 0) { > > > > > + full_update = true; > > > > > + break; > > > > > + } > > > > > + > > > > > + intel_psr2_plane_sel_fetch_ctl_calc(plane, > > > > > new_plane_state, > > > > > + new_plane_s > > > > > tate->uapi.visible); > > > > > + if (!new_plane_state->uapi.visible) > > > > > + continue; > > > > > + > > > > > + clips = > > > > > drm_plane_get_damage_clips(&new_plane_state->uapi); > > > > > + num_clips = > > > > > drm_plane_get_damage_clips_count(&new_plane_state->uapi); > > > > > + > > > > > + /* > > > > > + * If plane moved mark the whole plane area as > > > > > damaged so it > > > > > + * can be complete draw in the new position > > > > > + */ > > > > > + if (!drm_rect_equals(&new_plane_state- > > > > > > uapi.dst, > > > > > + &old_plane_state- > > > > > > uapi.dst)) { > > > > > + num_clips = 0; > > > > > + plane_clip.y1 = new_plane_state- > > > > > > uapi.src.y1 >> 16; > > > > > + plane_clip.y2 = new_plane_state- > > > > > > uapi.src.y2 >> 16; > > > > > + } else if (!num_clips) { > > > > > + /* > > > > > + * If plane don't have damage areas but > > > > > the framebuffer > > > > > + * changed mark the whole plane as > > > > > damaged > > > > > + */ > > > > > + if (new_plane_state->uapi.fb == > > > > > old_plane_state->uapi.fb) > > > > > + continue; > > > > > + > > > > > + plane_clip.y1 = new_plane_state- > > > > > > uapi.src.y1 >> 16; > > > > > + plane_clip.y2 = new_plane_state- > > > > > > uapi.src.y2 >> 16; > > > > > + } > > > > > + > > > > > + for (j = 0; j < num_clips; j++) { > > > > > + struct drm_rect damage_area; > > > > > + > > > > > + damage_area.x1 = clips[j].x1; > > > > > + damage_area.x2 = clips[j].x2; > > > > > + damage_area.y1 = clips[j].y1; > > > > > + damage_area.y2 = clips[j].y2; > > > > > + clip_update(&plane_clip, &damage_area); > > > > > + } > > > > > + > > > > > + intel_psr2_pipe_dirty_areas_set(new_plane_state > > > > > , plane, > > > > > + pipe_dirty_area > > > > > s, &plane_clip); > > > > > + intel_psr2_plane_sel_fetch_calc(new_plane_state > > > > > , &plane_clip); > > > > > + > > > > > + plane_clip.y1 += new_plane_state->uapi.crtc_y; > > > > > + plane_clip.y2 += new_plane_state->uapi.crtc_y; > > > > > + clip_update(&pipe_clip, &plane_clip); > > > > > + } > > > > > > > > This whole thing seems rather convoluted. Also using lots of uapi > > > > state > > > > in places where I don't expect to see any. > > > > > > Not sure from where I should get this information then, > > > intel_plane_state don't have it. > > > > > > > I would suggest the correct way would be something like: > > > > 1) for_each_plane_in_state() > > > > hw.damage = > > > > translate_to_some_hw_coord_space(union(uapi.damages)) > > > > or just use the full plane size if we have scaling i guess > > > > > > 99% of the time the coordinates used are based on pipe coord space, > > > only to calculate the plane overlapping damaged area is used plane > > > coord space. > > > > > > > 2) need to add all affected planes to the state and set the > > > > appropriate > > > > bitmask, which may mean we want to track the planes' positions > > > > in the > > > > crtc state. I think atm we only have it in the plane state > > > > > > This looks a "or" to me, have all the planes added to the state > > > when psr2 sel fetch is enabled or add track all the planes position > > > in pipe. > > > > *Affected* planes, not all planes. Hmm. I guess affected planes are > > actually the ones whose selective fetch coordinates change. If they > > don't change then no need to add them to the state. Plane updates are > > rather expensive (lots of mmio) so I've generally tried to avoid > > pointless plane updates. > > > > But this whole thing might turn a bit annoying since we'd to keep > > adding affected planes until the total selective fetch region stops > > growing. I think that would probably want the two stage plane state > > compuation. So just blindly adding all of them would probably be > > simpler, albeit less efficient. > > > > > Although the second one would avoid us to do plane calculations and > > > plane register sometimes, in some cases where a plane above a non- > > > modified plane > > > moves the non-modified plane bellow will need to be added to the > > > state so the plane sel_fetch registers are written. > > > We could go with the easy one(add all planes to the state) and then > > > move to the second one latter. > > > > > > > 3) translate the damage further into the final plane src > > > > coordinate > > > > space. Dunno if we have enough state around still to do it > > > > cleanly. > > > > I was thinking maybe it could be done alongside all the other > > > > plane > > > > surface calculations, but there might be a chicken vs. egg > > > > situation > > > > here since we probably want to do the plane check stuff before > > > > doing > > > > step 1, but plane check is also where we do the surface > > > > calculations. > > > > Dunno if we may just want to split the plane check into two > > > > stages > > > > > > As right now it depends mostly in uapi this could be moved to the > > > check phase, did not left there because this will never have a > > > error or a conflict > > > that will cause us to reject the state. > > > > > > > To keep things simple I guess what I'd suggest is to forget about > > > > the > > > > damage stuff in the first version of the series and just do full > > > > plane updates. That way we don't have to worry about so many > > > > coordinate > > > > space transformations. > > > > > > Do that would only save us the for bellow and the if to check if > > > plane moved: > > > > > > for (j = 0; j < num_clips; j++) { > > > struct drm_rect damage_area; > > > > > > damage_area.x1 = clips[j].x1; > > > damage_area.x2 = clips[j].x2; > > > damage_area.y1 = clips[j].y1; > > > damage_area.y2 = clips[j].y2; > > > clip_update(&plane_clip, &damage_area); > > > } > > > > That's just some minor detail. The real issue is converting the > > damage > > between the various coordinate spaces we have for planes (original fb > > relative src coordiantes, final SURF relative src coordinates, > > crtc relative dst coordinates, and also the hw vs. uapi stuff affects > > this stuff). > > > For the most efficient power comsumption and usage of bandthwidth, we > can use Selective Fetch of Plane and PSR2 Manual Tracking together. > But PSR2 Manual Tracking can be enabled without Selective Fetch of > Plane. (And pre GEN12 does not have a feature "Selective Fetch of > Plane".) > So can you split this commit to Selective Fetch and PSR2 Manual > Tracking? Pre GEN12 have selective fetch of plane, check BSpec: 33712 and 33711. The programming sequences states that program plane selective fetch registers and PSR2 Manual tracking must be combined, otherwise HW don't know if regular plane registers or selective fetch registers needs to be used. From patchwork at emeril.freedesktop.org Tue Jun 16 17:31:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 17:31:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_fix_a_couple_of_spelling_mistakes_in_kernel_parameter_?= =?utf-8?q?help_text?= In-Reply-To: <20200616082129.65517-1-colin.king@canonical.com> References: <20200616082129.65517-1-colin.king@canonical.com> Message-ID: <159232870167.4597.9607959179501790724@emeril.freedesktop.org> == Series Details == Series: drm/i915: fix a couple of spelling mistakes in kernel parameter help text URL : https://patchwork.freedesktop.org/series/78407/ State : success == Summary == CI Bug Log - changes from CI_DRM_8634 -> Patchwork_17958 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/index.html Known issues ------------ Here are the changes found in Patchwork_17958 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][5] -> [DMESG-WARN][6] ([i915#62] / [i915#92] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-tgl-u2/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][11] ([i915#1233]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-tgl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8634 -> Patchwork_17958 CI-20190529: 20190529 CI_DRM_8634: 72c556b3627adef8cef3b7a47c32987b96e7f1c2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17958: b463d0076902a926d54ec11be3d6131cf2416156 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b463d0076902 drm/i915: fix a couple of spelling mistakes in kernel parameter help text == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/index.html From imre.deak at intel.com Tue Jun 16 17:32:27 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 16 Jun 2020 20:32:27 +0300 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders In-Reply-To: <afab588c525d40b6b02347645808ce159bc4b44b.camel@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <4c40d13cfdb9cfe4d59eb04f27828b597949c54e.camel@intel.com> <20200616164209.GD21389@ideak-desk.fi.intel.com> <afab588c525d40b6b02347645808ce159bc4b44b.camel@intel.com> Message-ID: <20200616173227.GF21389@ideak-desk.fi.intel.com> On Tue, Jun 16, 2020 at 08:02:10PM +0300, Souza, Jose wrote: > On Tue, 2020-06-16 at 19:42 +0300, Imre Deak wrote: > > On Tue, Jun 16, 2020 at 07:32:46PM +0300, Souza, Jose wrote: > > > On Tue, 2020-06-16 at 17:18 +0300, Imre Deak wrote: > > > > MST encoders must use the master MST transcoder's DP_TP_STATUS and > > > > DP_TP_CONTROL registers. Atm, during the HW readout of a slave > > > > transcoder's CRTC state we reset these register addresses in > > > > intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register > > > > addresses incorrectly; fix this. > > > > > > > > This issue led at least to > > > > 'Timed out waiting for ACT sent when disabling' > > > > errors during output disabling in a multiple MST stream config. > > > > > > Can you point to place where dp_tp_ctl is used and cause this? All > > > the MST code paths uses the dp_tp_ctl of the main intel_dp(the one > > > that is not a mst connector). > > > > During a slave stream disabling when waiting for the ACT sent flag for > > that stream. > > > > > > This change replaces > > > > https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 > > > > which just papered over the problem. > > > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > > > > Signed-off-by: Imre Deak <imre.deak at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- > > > > 1 file changed, 10 insertions(+), 5 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index ca7bb2294d2b..73d6cc29291a 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > > > if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) > > > > return; > > > > > > > > - if (INTEL_GEN(dev_priv) >= 12) { > > > > - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); > > > > - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); > > > > - } > > > > - > > > > intel_dsc_get_config(encoder, pipe_config); > > > > > > > > temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); > > > > @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > > > break; > > > > } > > > > > > > > + if (INTEL_GEN(dev_priv) >= 12) { > > > > + enum transcoder transcoder = > > > > + intel_dp_mst_is_slave_trans(pipe_config) ? > > > > + pipe_config->mst_master_transcoder : > > > > + pipe_config->cpu_transcoder; > > > > + > > > > + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); > > > > + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); > > > > + } > > > > > > Also not sure how change only in the config readout would fix the issue, > > > > After a modeset we'll verify the HW state. The readout for a slave > > stream CRTC (get_pipe_config) running after the master CRTC's readout > > will overwrite the dp_tp reg addresses. The other instance of dp_tp > > register address init (in tgl_ddi_pre_enable_dp()) is correct. > > intel_mst_post_disable_dp() > struct intel_digital_port *intel_dig_port = intel_mst->primary; > struct intel_dp *intel_dp = &intel_dig_port->dp; > > ... > > if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, > DP_TP_STATUS_ACT_SENT, 1)) > drm_err(&dev_priv->drm, "Timed out waiting for ACT sent when disabling\n"); > > > Until here is right, but yeah bellow is the problem: > > static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > struct intel_digital_port *intel_dig_port = intel_mst->primary; > > intel_ddi_get_config(&intel_dig_port->base, pipe_config); > } > > > It will be overwritten with the transcoder of the last crtc read.Would > suggest to add something about intel_dp_mst_enc_get_config() to the > commit description but the change looks good now. Hm yea, it's the encoder not the CRTC readout where the overwrite happens. Will update this in the commit log. > > > IFWI don't enable MST so when i915 takes over a full modeset will > > > happen to enable MST and only dp_tp_ctl of the main intel_dp(the one > > > that is not a mst connector) will be set, check > > > tgl_ddi_pre_enable_dp(). > > > > > > > + > > > > pipe_config->has_audio = > > > > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); > > > > From ville.syrjala at linux.intel.com Tue Jun 16 17:34:07 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 20:34:07 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ In-Reply-To: <20200616163406.27387-1-matthew.s.atwood@intel.com> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> Message-ID: <20200616173407.GI6112@intel.com> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote: > Add minimum width to planes, variable with specific formats, for gen11+. > > Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++--- > 1 file changed, 47 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 7457813ef273..d4fdad6cb3b1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb, > } > } > > +static int icl_min_plane_width(struct drm_i915_private *dev_priv, > + const struct drm_framebuffer *fb) > +{ > + /* Wa_14011264657, Wa_14011050563 */ > + switch (fb->format->format) { > + case DRM_FORMAT_C8: > + return 18; > + case DRM_FORMAT_RGB565: > + return 10; > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ARGB8888: > + case DRM_FORMAT_ABGR8888: > + case DRM_FORMAT_XRGB2101010: > + case DRM_FORMAT_XBGR2101010: > + case DRM_FORMAT_ARGB2101010: > + case DRM_FORMAT_ABGR2101010: > + case DRM_FORMAT_XVYU2101010: > + case DRM_FORMAT_Y212: > + case DRM_FORMAT_Y216: > + return 6; > + case DRM_FORMAT_NV12: > + return 20; > + case DRM_FORMAT_P010: > + case DRM_FORMAT_P012: > + case DRM_FORMAT_P016: > + return 12; > + case DRM_FORMAT_XRGB16161616F: > + case DRM_FORMAT_XBGR16161616F: > + case DRM_FORMAT_ARGB16161616F: > + case DRM_FORMAT_ABGR16161616F: > + case DRM_FORMAT_XVYU12_16161616: > + case DRM_FORMAT_XVYU16161616: > + return 4; > + default: > + return 1; > + } if (semiplanar) { switch (cpp[0]) { case 1: return 20; case 2: return 12; } } else { switch (cpp[0]) { case 1: return 18; case 2: return 10; case 4: return 6; case 8: return 4; } } Actually if we fully reverse engineer this we are left with just: if (semiplanar) return 16/cpp[0] + 4; else return 16/cpp[0] + 2; I'd much prefer calculating this since then it's fully divorced from defining new pixel formats. Can we get a confirmation from the hw folks if that is in fact the formula (or if there's a different formula how they came up with these magic numbers)? > +} > + > static int icl_max_plane_width(const struct drm_framebuffer *fb, > int color_plane, > unsigned int rotation) > @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > int y = plane_state->uapi.src.y1 >> 16; > int w = drm_rect_width(&plane_state->uapi.src) >> 16; > int h = drm_rect_height(&plane_state->uapi.src) >> 16; > - int max_width; > - int max_height; > - u32 alignment; > - u32 offset; > + int max_width, min_width = 1, max_height; > + u32 alignment, offset; > int aux_plane = intel_main_to_aux_plane(fb, 0); > u32 aux_offset = plane_state->color_plane[aux_plane].offset; > > - if (INTEL_GEN(dev_priv) >= 11) > + if (INTEL_GEN(dev_priv) >= 11) { > max_width = icl_max_plane_width(fb, 0, rotation); > + min_width = icl_min_plane_width(dev_priv, fb); > + } > else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) Missing curly braces on all the branches. Feels like dejavu... I'd also do the min_width=1 assignment in each branch to make it clear what's what. > max_width = glk_max_plane_width(fb, 0, rotation); > else > @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) > else > max_height = skl_max_plane_height(); > > - if (w > max_width || h > max_height) { > + if (w > max_width || w < min_width || h > max_height) { > drm_dbg_kms(&dev_priv->drm, > - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n", > - w, h, max_width, max_height); > + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", > + w, h, min_width, max_width, max_height); > return -EINVAL; > } > > -- > 2.21.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Tue Jun 16 17:58:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 17:58:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBk?= =?utf-8?q?rm/i915/gvt=3A_query_if_vgpu_is_active_via_GETPARAM_IOCTL?= In-Reply-To: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> References: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> Message-ID: <159233031994.4598.17487090911055330606@emeril.freedesktop.org> == Series Details == Series: drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL URL : https://patchwork.freedesktop.org/series/78409/ State : failure == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/i915_getparam.o drivers/gpu/drm/i915/i915_getparam.c: In function ?i915_getparam_ioctl?: drivers/gpu/drm/i915/i915_getparam.c:165:11: error: implicit declaration of function ?intel_vgpu_active?; did you mean ?intel_vtd_active?? [-Werror=implicit-function-declaration] value = intel_vgpu_active(i915); ^~~~~~~~~~~~~~~~~ intel_vtd_active cc1: all warnings being treated as errors scripts/Makefile.build:280: recipe for target 'drivers/gpu/drm/i915/i915_getparam.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_getparam.o] Error 1 scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:497: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1764: recipe for target 'drivers' failed make: *** [drivers] Error 2 From patchwork at emeril.freedesktop.org Tue Jun 16 18:04:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 18:04:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/9=5D_drm/i915/selftests=3A_Exerci?= =?utf-8?q?se_far_preemption_rollbacks?= In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <159233069034.4595.8564515414778788292@emeril.freedesktop.org> == Series Details == Series: series starting with [1/9] drm/i915/selftests: Exercise far preemption rollbacks URL : https://patchwork.freedesktop.org/series/78410/ State : warning == Summary == $ dim checkpatch origin/drm-tip 49d66c60e62f drm/i915/selftests: Exercise far preemption rollbacks -:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding")' #19: References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") total: 1 errors, 0 warnings, 0 checks, 162 lines checked c6088929414a drm/i915/selftests: Use friendly request names for live_timeslice_rewind 110ee4d71849 drm/i915/selftests: Enable selftesting of busy-stats -:58: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #58: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:48: + udelay(100); -:89: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #89: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:79: + udelay(100); total: 0 errors, 0 warnings, 2 checks, 117 lines checked 16284702446a drm/i915/execlists: Replace direct submit with direct call to tasklet 81ca04a94781 drm/i915/execlists: Defer schedule_out until after the next dequeue -:117: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV) #117: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:2441: + *execlists->inactive++ = *port; ^ total: 0 errors, 0 warnings, 1 checks, 179 lines checked 499dd7003551 drm/i915/gt: ce->inflight updates are now serialised 2f30d63c06b7 drm/i915/gt: Drop atomic for engine->fw_active tracking ef92526598ab drm/i915/gt: Extract busy-stats for ring-scheduler -:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #12: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 95 lines checked 480f3ff83a82 drm/i915/gt: Convert stats.active to plain unsigned int From chris at chris-wilson.co.uk Tue Jun 16 18:31:39 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 19:31:39 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Mark up inline getters as taking a const i915_request Message-ID: <20200616183139.4061-1-chris@chris-wilson.co.uk> Since these inline routines only return from the i915_request to return the desired pointer (after checking the preconditions for acquiring said pointer), they can be const. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_request.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index 118ab6650d1f..590762820761 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -561,7 +561,7 @@ static inline void i915_request_clear_hold(struct i915_request *rq) } static inline struct intel_timeline * -i915_request_timeline(struct i915_request *rq) +i915_request_timeline(const struct i915_request *rq) { /* Valid only while the request is being constructed (or retired). */ return rcu_dereference_protected(rq->timeline, @@ -569,14 +569,14 @@ i915_request_timeline(struct i915_request *rq) } static inline struct i915_gem_context * -i915_request_gem_context(struct i915_request *rq) +i915_request_gem_context(const struct i915_request *rq) { /* Valid only while the request is being constructed (or retired). */ return rcu_dereference_protected(rq->context->gem_context, true); } static inline struct intel_timeline * -i915_request_active_timeline(struct i915_request *rq) +i915_request_active_timeline(const struct i915_request *rq) { /* * When in use during submission, we are protected by a guarantee that -- 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 16 18:37:54 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 18:37:54 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/9=5D_drm/i915/selftests=3A_Exercise_far_?= =?utf-8?q?preemption_rollbacks?= In-Reply-To: <20200616084141.3722-1-chris@chris-wilson.co.uk> References: <20200616084141.3722-1-chris@chris-wilson.co.uk> Message-ID: <159233267499.4596.1199876364095873767@emeril.freedesktop.org> == Series Details == Series: series starting with [1/9] drm/i915/selftests: Exercise far preemption rollbacks URL : https://patchwork.freedesktop.org/series/78410/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8635 -> Patchwork_17960 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17960 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17960, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17960: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_engines: - fi-kbl-soraka: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-soraka/igt at i915_selftest@live at gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-kbl-soraka/igt at i915_selftest@live at gt_engines.html - fi-icl-y: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-y/igt at i915_selftest@live at gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-icl-y/igt at i915_selftest@live at gt_engines.html - fi-bsw-n3050: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-bsw-n3050/igt at i915_selftest@live at gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-bsw-n3050/igt at i915_selftest@live at gt_engines.html - fi-cml-s: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-cml-s/igt at i915_selftest@live at gt_engines.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-cml-s/igt at i915_selftest@live at gt_engines.html - fi-skl-6600u: [PASS][9] -> [FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-skl-6600u/igt at i915_selftest@live at gt_engines.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-skl-6600u/igt at i915_selftest@live at gt_engines.html - fi-bsw-kefka: [PASS][11] -> [FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-bsw-kefka/igt at i915_selftest@live at gt_engines.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-bsw-kefka/igt at i915_selftest@live at gt_engines.html * igt at i915_selftest@live at hangcheck: - fi-tgl-u2: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt at i915_selftest@live at hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-tgl-u2/igt at i915_selftest@live at hangcheck.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at gt_engines: - {fi-tgl-dsi}: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-dsi/igt at i915_selftest@live at gt_engines.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-tgl-dsi/igt at i915_selftest@live at gt_engines.html Known issues ------------ Here are the changes found in Patchwork_17960 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-kbl-soraka: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-soraka/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-kbl-soraka/igt at i915_pm_rpm@module-reload.html - fi-apl-guc: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at hangcheck: - fi-glk-dsi: [PASS][21] -> [INCOMPLETE][22] ([i915#58] / [k.org#198133]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-glk-dsi/igt at i915_selftest@live at hangcheck.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-glk-dsi/igt at i915_selftest@live at hangcheck.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_busy@basic at flip.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at kms_flip@basic-flip-vs-dpms at a-dp1: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92]) -> [DMESG-WARN][32] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17960 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17960: 480f3ff83a825775e754a364ae7096a67807ee2d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 480f3ff83a82 drm/i915/gt: Convert stats.active to plain unsigned int ef92526598ab drm/i915/gt: Extract busy-stats for ring-scheduler 2f30d63c06b7 drm/i915/gt: Drop atomic for engine->fw_active tracking 499dd7003551 drm/i915/gt: ce->inflight updates are now serialised 81ca04a94781 drm/i915/execlists: Defer schedule_out until after the next dequeue 16284702446a drm/i915/execlists: Replace direct submit with direct call to tasklet 110ee4d71849 drm/i915/selftests: Enable selftesting of busy-stats c6088929414a drm/i915/selftests: Use friendly request names for live_timeslice_rewind 49d66c60e62f drm/i915/selftests: Exercise far preemption rollbacks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17960/index.html From chris at chris-wilson.co.uk Tue Jun 16 18:47:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 19:47:20 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> References: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> Message-ID: <159233324036.19488.6385709597388673560@build.alporthouse.com> Quoting Shaofeng Tang (2020-06-16 09:29:20) > [Why] > Query if vgpu is active, it is useful to the user. > Currently, only the primary plane is usable when vgpu is active. > The value of vgpu active is useful for user to determine > how many planes can be used. also useful for user to > determine different behaviors according to vgpu is active or not. The number of planes must be queried via kms, and all such kernel capabilities should be declared via the appropriate interface. I am not saying that there is not potentially good reason to let the user to know it's a virtual gpu, but hardcoding api limits in the client based on the parameter is a bad idea. -Chris From chris at chris-wilson.co.uk Tue Jun 16 18:55:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 19:55:17 +0100 Subject: [Intel-gfx] [CI 1/2] drm/i915/selftests: Exercise far preemption rollbacks Message-ID: <20200616185518.11948-1-chris@chris-wilson.co.uk> Not too long ago, we realised we had issues with a rolling back a context so far for a preemption request we considered the resubmit not to be a rollback but a forward roll. This means we would issue a lite restore instead of forcing a full restore, continuing execution of the old requests rather than causing a preemption. Add a selftest to exercise such a far rollback, such that if we were to skip the full restore, we would execute invalid instructions in the ring and hang. Note that while I was able to confirm that this causes us to do a lite-restore preemption rollback (with commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") disabled), it did not trick the HW into rolling past the old RING_TAIL. Myybe on other HW. References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 151 +++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 91543494f595..5c5900443c52 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -363,6 +363,156 @@ static int live_unlite_preempt(void *arg) return live_unlite_restore(arg, I915_USER_PRIORITY(I915_PRIORITY_MAX)); } +static int live_unlite_ring(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + struct igt_spinner spin; + enum intel_engine_id id; + int err = 0; + + /* + * Setup a preemption event that will cause almost the entire ring + * to be unwound, potentially fooling our intel_ring_direction() + * into emitting a forward lite-restore instead of the rollback. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + for_each_engine(engine, gt, id) { + struct intel_context *ce[2] = {}; + struct i915_request *rq; + struct igt_live_test t; + int n; + + if (!intel_engine_has_preemption(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) { + err = -EIO; + break; + } + engine_heartbeat_disable(engine); + + for (n = 0; n < ARRAY_SIZE(ce); n++) { + struct intel_context *tmp; + + tmp = intel_context_create(engine); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + goto err_ce; + } + + err = intel_context_pin(tmp); + if (err) { + intel_context_put(tmp); + goto err_ce; + } + + memset32(tmp->ring->vaddr, + 0xdeadbeef, /* trigger a hang if executed */ + tmp->ring->vma->size / sizeof(u32)); + + ce[n] = tmp; + } + + /* Create max prio spinner, followed by N low prio nops */ + rq = igt_spinner_create_request(&spin, ce[0], MI_ARB_CHECK); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + i915_request_get(rq); + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(gt); + i915_request_put(rq); + err = -ETIME; + goto err_ce; + } + + /* Fill the ring, until we will cause a wrap */ + n = 0; + while (intel_ring_direction(ce[0]->ring, + rq->wa_tail, + ce[0]->ring->tail) <= 0) { + struct i915_request *tmp; + + tmp = intel_context_create_request(ce[0]); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + i915_request_put(rq); + goto err_ce; + } + + i915_request_add(tmp); + intel_engine_flush_submission(engine); + n++; + } + intel_engine_flush_submission(engine); + pr_debug("%s: Filled ring with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", + engine->name, n, + ce[0]->ring->size, + ce[0]->ring->tail, + ce[0]->ring->emit, + rq->tail); + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, + rq->tail, + ce[0]->ring->tail) <= 0); + i915_request_put(rq); + + /* Create a second ring to preempt the first ring after rq[0] */ + rq = intel_context_create_request(ce[1]); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_get(rq); + i915_request_add(rq); + + err = wait_for_submit(engine, rq, HZ / 2); + i915_request_put(rq); + if (err) { + pr_err("%s: preemption request was not submited\n", + engine->name); + err = -ETIME; + } + + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", + engine->name, + ce[0]->ring->tail, ce[0]->ring->emit, + ce[1]->ring->tail, ce[1]->ring->emit); + +err_ce: + intel_engine_flush_submission(engine); + igt_spinner_end(&spin); + for (n = 0; n < ARRAY_SIZE(ce); n++) { + if (IS_ERR_OR_NULL(ce[n])) + break; + + intel_context_unpin(ce[n]); + intel_context_put(ce[n]); + } + engine_heartbeat_enable(engine); + if (igt_live_test_end(&t)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + return err; +} + static int live_pin_rewind(void *arg) { struct intel_gt *gt = arg; @@ -4374,6 +4524,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_sanitycheck), SUBTEST(live_unlite_switch), SUBTEST(live_unlite_preempt), + SUBTEST(live_unlite_ring), SUBTEST(live_pin_rewind), SUBTEST(live_hold_reset), SUBTEST(live_error_interrupt), -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 16 18:55:18 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 19:55:18 +0100 Subject: [Intel-gfx] [CI 2/2] drm/i915/selftests: Use friendly request names for live_timeslice_rewind In-Reply-To: <20200616185518.11948-1-chris@chris-wilson.co.uk> References: <20200616185518.11948-1-chris@chris-wilson.co.uk> Message-ID: <20200616185518.11948-2-chris@chris-wilson.co.uk> Rather than mixing [012] and (A1, A2, B2) for the request indices, use the enums throughout. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 5c5900443c52..e709361c139e 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -1177,18 +1177,18 @@ static int live_timeslice_rewind(void *arg) goto err; } - rq[0] = create_rewinder(ce, NULL, slot, X); - if (IS_ERR(rq[0])) { + rq[A1] = create_rewinder(ce, NULL, slot, X); + if (IS_ERR(rq[A1])) { intel_context_put(ce); goto err; } - rq[1] = create_rewinder(ce, NULL, slot, Y); + rq[A2] = create_rewinder(ce, NULL, slot, Y); intel_context_put(ce); - if (IS_ERR(rq[1])) + if (IS_ERR(rq[A2])) goto err; - err = wait_for_submit(engine, rq[1], HZ / 2); + err = wait_for_submit(engine, rq[A2], HZ / 2); if (err) { pr_err("%s: failed to submit first context\n", engine->name); @@ -1201,12 +1201,12 @@ static int live_timeslice_rewind(void *arg) goto err; } - rq[2] = create_rewinder(ce, rq[0], slot, Z); + rq[B1] = create_rewinder(ce, rq[A1], slot, Z); intel_context_put(ce); if (IS_ERR(rq[2])) goto err; - err = wait_for_submit(engine, rq[2], HZ / 2); + err = wait_for_submit(engine, rq[B1], HZ / 2); if (err) { pr_err("%s: failed to submit second context\n", engine->name); @@ -1214,6 +1214,7 @@ static int live_timeslice_rewind(void *arg) } /* ELSP[] = { { A:rq1, A:rq2 }, { B:rq1 } } */ + ENGINE_TRACE(engine, "forcing tasklet for rewind\n"); if (i915_request_is_active(rq[A2])) { /* semaphore yielded! */ /* Wait for the timeslice to kick in */ del_timer(&engine->execlists.timer); -- 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 16 18:59:06 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 18:59:06 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Check_preemption_rollback_of_different_ring_?= =?utf-8?q?queue_depths?= In-Reply-To: <20200616092833.18498-1-chris@chris-wilson.co.uk> References: <20200616092833.18498-1-chris@chris-wilson.co.uk> Message-ID: <159233394636.4598.9254408792105868798@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Check preemption rollback of different ring queue depths URL : https://patchwork.freedesktop.org/series/78411/ State : success == Summary == CI Bug Log - changes from CI_DRM_8635 -> Patchwork_17961 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/index.html Known issues ------------ Here are the changes found in Patchwork_17961 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1242]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at i915_module_load@reload: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/fi-kbl-x1275/igt at i915_module_load@reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 41) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-glk-dsi fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17961 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17961: 6fd85c27f831221e7c9b2339ff44f835f8ca19da @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6fd85c27f831 drm/i915/selftests: Check preemption rollback of different ring queue depths == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/index.html From chris at chris-wilson.co.uk Tue Jun 16 19:01:36 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 20:01:36 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Decouple completed requests on unwind Message-ID: <20200616190136.19905-1-chris@chris-wilson.co.uk> Since the introduction of preempt-to-busy, requests can complete in the background, even while they are not on the engine->active.requests list. As such, the engine->active.request list itself is not in strict retirement order, and we have to scan the entire list while unwinding to not miss any. However, if the request is completed we currently leave it on the list [until retirement], but we could just as simply remove it and stop treating it as active. We would only have to then traverse it once while unwinding in quick succession. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..4eb397b0e14d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1114,8 +1114,10 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) list_for_each_entry_safe_reverse(rq, rn, &engine->active.requests, sched.link) { - if (i915_request_completed(rq)) - continue; /* XXX */ + if (i915_request_completed(rq)) { + list_del_init(&rq->sched.link); + continue; + } __i915_request_unsubmit(rq); -- 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 16 19:03:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 19:03:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/display=3A_fix_missing_null_check_on_allocated_dsb?= =?utf-8?q?_object?= In-Reply-To: <20200616114221.73971-1-colin.king@canonical.com> References: <20200616114221.73971-1-colin.king@canonical.com> Message-ID: <159233420999.4595.17677590135204023959@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: fix missing null check on allocated dsb object URL : https://patchwork.freedesktop.org/series/78414/ State : warning == Summary == $ dim checkpatch origin/drm-tip f48c185da47b drm/i915/display: fix missing null check on allocated dsb object -:27: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message #27: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:275: + if (!dsb) { + drm_err(&i915->drm, "DSB object creation failed\n"); total: 0 errors, 1 warnings, 0 checks, 10 lines checked From patchwork at emeril.freedesktop.org Tue Jun 16 19:08:16 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 19:08:16 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_fix_a_couple_of_spelling_mistakes_in_kernel_parameter_?= =?utf-8?q?help_text?= In-Reply-To: <20200616082129.65517-1-colin.king@canonical.com> References: <20200616082129.65517-1-colin.king@canonical.com> Message-ID: <159233449650.4595.11321149677218385066@emeril.freedesktop.org> == Series Details == Series: drm/i915: fix a couple of spelling mistakes in kernel parameter help text URL : https://patchwork.freedesktop.org/series/78407/ State : success == Summary == CI Bug Log - changes from CI_DRM_8634_full -> Patchwork_17958_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17958_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-kbl3/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-glk2/igt at gem_exec_schedule@smoketest-all.html * igt at gem_workarounds@suspend-resume-fd: - shard-snb: [PASS][5] -> [DMESG-WARN][6] ([i915#42]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-snb6/igt at gem_workarounds@suspend-resume-fd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-snb5/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_module_load@reload: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-tglb6/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-tglb3/igt at i915_module_load@reload.html * igt at kms_cursor_crc@pipe-a-cursor-128x128-onscreen: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#54]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl10/igt at kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl2/igt at kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html * igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-glk7/igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-glk1/igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html * igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#79]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-glk8/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ab-hdmi-a1-hdmi-a2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-glk1/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-expired-vblank at a-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#79]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl5/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl10/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1928]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl2/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-apl1/igt at kms_flip_tiling@flip-changes-tiling-y.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-apl7/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-tglb1/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-tglb5/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-position-covered-pipe-b-planes: - shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) +9 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl6/igt at kms_plane@plane-position-covered-pipe-b-planes.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl7/igt at kms_plane@plane-position-covered-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_plane_cursor@pipe-b-overlay-size-256: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#95]) +10 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-apl2/igt at kms_plane_cursor@pipe-b-overlay-size-256.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-apl1/igt at kms_plane_cursor@pipe-b-overlay-size-256.html - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#93] / [i915#95]) +3 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-kbl2/igt at kms_plane_cursor@pipe-b-overlay-size-256.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-kbl3/igt at kms_plane_cursor@pipe-b-overlay-size-256.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109642] / [fdo#111068]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-iclb1/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-iclb7/igt at kms_psr@psr2_sprite_plane_move.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][39] -> [FAIL][40] ([i915#1542]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-iclb2/igt at perf@blocking-parameterized.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-iclb1/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [INCOMPLETE][41] ([i915#82]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_mmap_offset@ptrace at gtt: - shard-kbl: [DMESG-WARN][43] ([i915#93] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-kbl7/igt at gem_mmap_offset@ptrace at gtt.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-kbl4/igt at gem_mmap_offset@ptrace at gtt.html * igt at gem_shrink@reclaim: - shard-hsw: [SKIP][45] ([fdo#109271]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-hsw1/igt at gem_shrink@reclaim.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-hsw4/igt at gem_shrink@reclaim.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][47] ([i915#1436] / [i915#716]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl7/igt at gen9_exec_parse@allowed-single.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl10/igt at gen9_exec_parse@allowed-single.html * igt at i915_query@query-topology-kernel-writes: - shard-iclb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-iclb7/igt at i915_query@query-topology-kernel-writes.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-iclb3/igt at i915_query@query-topology-kernel-writes.html * igt at i915_suspend@fence-restore-untiled: - shard-kbl: [INCOMPLETE][51] ([i915#155]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-kbl1/igt at i915_suspend@fence-restore-untiled.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][53] ([i915#118] / [i915#95]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-glk1/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][55] ([IGT#5]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl3/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl4/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-blocking-wf-vblank at a-edp1: - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +5 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl10/igt at kms_flip@flip-vs-blocking-wf-vblank at a-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl10/igt at kms_flip@flip-vs-blocking-wf-vblank at a-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-tglb: [DMESG-WARN][59] ([i915#1982] / [i915#402]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-kbl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-iclb8/igt at kms_psr@psr2_sprite_render.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-iclb2/igt at kms_psr@psr2_sprite_render.html * igt at kms_vblank@pipe-b-wait-busy-hang: - shard-apl: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-apl3/igt at kms_vblank@pipe-b-wait-busy-hang.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-apl3/igt at kms_vblank@pipe-b-wait-busy-hang.html * igt at syncobj_basic@illegal-fd-to-handle: - shard-apl: [DMESG-WARN][69] ([i915#95]) -> [PASS][70] +9 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-apl1/igt at syncobj_basic@illegal-fd-to-handle.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-apl8/igt at syncobj_basic@illegal-fd-to-handle.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][71] ([i915#658]) -> [SKIP][72] ([i915#588]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-iclb8/igt at i915_pm_dc@dc3co-vpb-simulation.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][73] ([i915#1319]) -> [TIMEOUT][74] ([i915#1319] / [i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-kbl1/igt at kms_content_protection@lic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-kbl7/igt at kms_content_protection@lic.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][75] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][76] ([fdo#108145] / [i915#1982]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt at kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-apl: [DMESG-FAIL][77] ([i915#95]) -> [FAIL][78] ([i915#265]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-apl3/igt at kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-apl3/igt at kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][79] ([i915#180]) -> [INCOMPLETE][80] ([i915#155]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8634/shard-kbl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/shard-kbl1/igt at kms_vblank@pipe-b-ts-continuation-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8634 -> Patchwork_17958 CI-20190529: 20190529 CI_DRM_8634: 72c556b3627adef8cef3b7a47c32987b96e7f1c2 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17958: b463d0076902a926d54ec11be3d6131cf2416156 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17958/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 19:23:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 19:23:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/shmem-helper=3A_Only_dma-buf_imports_are_private_obj?= In-Reply-To: <20200616114723.2363268-1-daniel.vetter@ffwll.ch> References: <20200616114723.2363268-1-daniel.vetter@ffwll.ch> Message-ID: <159233542255.4598.2596535367896358897@emeril.freedesktop.org> == Series Details == Series: drm/shmem-helper: Only dma-buf imports are private obj URL : https://patchwork.freedesktop.org/series/78416/ State : failure == Summary == Applying: drm/shmem-helper: Only dma-buf imports are private obj Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_gem_shmem_helper.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_gem_shmem_helper.c No changes -- Patch already applied. From patchwork at emeril.freedesktop.org Tue Jun 16 19:24:27 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 19:24:27 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_fix_missing_null_check_on_allocated_dsb_object?= In-Reply-To: <20200616114221.73971-1-colin.king@canonical.com> References: <20200616114221.73971-1-colin.king@canonical.com> Message-ID: <159233546772.4597.16185238602820262467@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: fix missing null check on allocated dsb object URL : https://patchwork.freedesktop.org/series/78414/ State : success == Summary == CI Bug Log - changes from CI_DRM_8635 -> Patchwork_17962 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/index.html Known issues ------------ Here are the changes found in Patchwork_17962 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1242]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_busy@basic at flip.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at kms_flip@basic-flip-vs-dpms at a-dp1: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 41) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-whl-u fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17962 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17962: f48c185da47b189fee405b28a4e607332d5b200d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f48c185da47b drm/i915/display: fix missing null check on allocated dsb object == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/index.html From manasi.d.navare at intel.com Tue Jun 16 19:30:56 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 16 Jun 2020 12:30:56 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf Message-ID: <20200616193056.4817-1-manasi.d.navare@intel.com> The Bspec sequence expects us to poll for DDI Idle status to be 0 (not idle) with a timeout of 600usecs after enabling the DDI BUF CTL. But currently in the driver we just wait for 600usecs without polling so add that. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..de7e15de0bc5 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4023,7 +4023,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); - udelay(600); + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + DDI_BUF_IS_IDLE), + 600)) + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", + port_name(port)); } static void intel_ddi_set_link_train(struct intel_dp *intel_dp, -- 2.19.1 From ville.syrjala at linux.intel.com Tue Jun 16 19:42:44 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 22:42:44 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf In-Reply-To: <20200616193056.4817-1-manasi.d.navare@intel.com> References: <20200616193056.4817-1-manasi.d.navare@intel.com> Message-ID: <20200616194244.GJ6112@intel.com> On Tue, Jun 16, 2020 at 12:30:56PM -0700, Manasi Navare wrote: > The Bspec sequence expects us to poll for DDI Idle status > to be 0 (not idle) with a timeout of 600usecs after enabling the > DDI BUF CTL. It only says that for newer platforms. We need to either keep the fixed delay before starting to poll, or someone needs confirm how the idle bit really behaves on the older platforms. > But currently in the driver we just wait for 600usecs > without polling so add that. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b..de7e15de0bc5 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4023,7 +4023,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > - udelay(600); > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), > + 600)) > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > + port_name(port)); > } > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > -- > 2.19.1 -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Tue Jun 16 19:50:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 19:50:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/6=5D_drm/i915/tgl+=3A_Use_the_correct_DP?= =?utf-8?q?=5FTP=5F*_register_instances_in_MST_encoders?= In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <159233703300.4596.7457059522418906935@emeril.freedesktop.org> == Series Details == Series: series starting with [1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders URL : https://patchwork.freedesktop.org/series/78423/ State : success == Summary == CI Bug Log - changes from CI_DRM_8635 -> Patchwork_17964 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/index.html Known issues ------------ Here are the changes found in Patchwork_17964 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at i915_module_load@reload: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/fi-kbl-x1275/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-rte: - fi-kbl-guc: [SKIP][11] ([fdo#109271]) -> [FAIL][12] ([i915#665] / [i915#704]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17964 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17964: d302e0a23522a808ab7073bf458e7b70df70def3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d302e0a23522 drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it 005be72f6fe4 drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too 1c1441217489 drm/i915/dp_mst: Clear only the ACT sent flag from DP_TP_STATUS 23865500149b drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling 94a0f7ad711f drm/i915/dp_mst: Disable link training fallback on MST links 15358e434948 drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/index.html From ville.syrjala at linux.intel.com Tue Jun 16 19:54:22 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 22:54:22 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf In-Reply-To: <20200616194244.GJ6112@intel.com> References: <20200616193056.4817-1-manasi.d.navare@intel.com> <20200616194244.GJ6112@intel.com> Message-ID: <20200616195422.GK6112@intel.com> On Tue, Jun 16, 2020 at 10:42:44PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 12:30:56PM -0700, Manasi Navare wrote: > > The Bspec sequence expects us to poll for DDI Idle status > > to be 0 (not idle) with a timeout of 600usecs after enabling the > > DDI BUF CTL. > > It only says that for newer platforms. We need to either keep > the fixed delay before starting to poll, or someone needs confirm > how the idle bit really behaves on the older platforms. In fact it says not to use this bit at all on BXT. So even our disable sequence is potentially borked on BXT. Unfortunately the spec doesn't say which way the bit is broken, so not clear if that's the case or not. > > > But currently in the driver we just wait for 600usecs > > without polling so add that. > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index ca7bb2294d2b..de7e15de0bc5 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -4023,7 +4023,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > - udelay(600); > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), > > + 600)) > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > + port_name(port)); > > } > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From manasi.d.navare at intel.com Tue Jun 16 20:07:53 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 16 Jun 2020 13:07:53 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf In-Reply-To: <20200616195422.GK6112@intel.com> References: <20200616193056.4817-1-manasi.d.navare@intel.com> <20200616194244.GJ6112@intel.com> <20200616195422.GK6112@intel.com> Message-ID: <20200616200753.GA4903@intel.com> On Tue, Jun 16, 2020 at 10:54:22PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 10:42:44PM +0300, Ville Syrj?l? wrote: > > On Tue, Jun 16, 2020 at 12:30:56PM -0700, Manasi Navare wrote: > > > The Bspec sequence expects us to poll for DDI Idle status > > > to be 0 (not idle) with a timeout of 600usecs after enabling the > > > DDI BUF CTL. > > > > It only says that for newer platforms. We need to either keep > > the fixed delay before starting to poll, or someone needs confirm > > how the idle bit really behaves on the older platforms. > > In fact it says not to use this bit at all on BXT. So even our disable > sequence is potentially borked on BXT. Unfortunately the spec doesn't > say which way the bit is broken, so not clear if that's the case or > not. > I double checked on Gen 9, it is > 518 usecs timeout and Gen 10+ it is 500usecs and then gen 12, it is 600 usecs timeout. Should we add this max timeout for Gen >=10, we def need this for platforms starting Gen 10+ Manasi > > > > > But currently in the driver we just wait for 600usecs > > > without polling so add that. > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- > > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index ca7bb2294d2b..de7e15de0bc5 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -4023,7 +4023,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > > > - udelay(600); > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), > > > + 600)) > > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > > + port_name(port)); > > > } > > > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > > -- > > > 2.19.1 > > > > -- > > Ville Syrj?l? > > Intel > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From mika.kuoppala at linux.intel.com Tue Jun 16 20:07:54 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 23:07:54 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Mark up inline getters as taking a const i915_request In-Reply-To: <20200616183139.4061-1-chris@chris-wilson.co.uk> References: <20200616183139.4061-1-chris@chris-wilson.co.uk> Message-ID: <87r1ue93l1.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Since these inline routines only return from the i915_request to return only return desired pointer from i915_request > the desired pointer (after checking the preconditions for acquiring said > pointer), they can be const. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/i915_request.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h > index 118ab6650d1f..590762820761 100644 > --- a/drivers/gpu/drm/i915/i915_request.h > +++ b/drivers/gpu/drm/i915/i915_request.h > @@ -561,7 +561,7 @@ static inline void i915_request_clear_hold(struct i915_request *rq) > } > > static inline struct intel_timeline * > -i915_request_timeline(struct i915_request *rq) > +i915_request_timeline(const struct i915_request *rq) > { > /* Valid only while the request is being constructed (or retired). */ > return rcu_dereference_protected(rq->timeline, > @@ -569,14 +569,14 @@ i915_request_timeline(struct i915_request *rq) > } > > static inline struct i915_gem_context * > -i915_request_gem_context(struct i915_request *rq) > +i915_request_gem_context(const struct i915_request *rq) > { > /* Valid only while the request is being constructed (or retired). */ > return rcu_dereference_protected(rq->context->gem_context, true); > } > > static inline struct intel_timeline * > -i915_request_active_timeline(struct i915_request *rq) > +i915_request_active_timeline(const struct i915_request *rq) > { > /* > * When in use during submission, we are protected by a guarantee that > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mika.kuoppala at linux.intel.com Tue Jun 16 20:09:52 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 16 Jun 2020 23:09:52 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/selftests: Check preemption rollback of different ring queue depths In-Reply-To: <20200616092833.18498-1-chris@chris-wilson.co.uk> References: <20200616092833.18498-1-chris@chris-wilson.co.uk> Message-ID: <87o8pi93hr.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Like live_unlite_ring, but instead of simply looking at the impact of > intel_ring_direction(), check that preemption more generally works with > different depths of queued requests in the ring. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Pondering about the sizes of try but I can't make up anything better. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 163 +++++++++++++++++++++++++ > 1 file changed, 163 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index 3d088116a055..530718797848 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -2756,6 +2756,168 @@ static int create_gang(struct intel_engine_cs *engine, > return err; > } > > +static int __live_preempt_ring(struct intel_engine_cs *engine, > + struct igt_spinner *spin, > + int sz) > +{ > + struct intel_context *ce[2] = {}; > + struct i915_request *rq; > + struct igt_live_test t; > + int err = 0; > + int n; > + > + if (igt_live_test_begin(&t, engine->i915, __func__, engine->name)) > + return -EIO; > + > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + struct intel_context *tmp; > + > + tmp = intel_context_create(engine); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + goto err_ce; > + } > + > + err = intel_context_pin(tmp); > + if (err) { > + intel_context_put(tmp); > + goto err_ce; > + } > + > + memset32(tmp->ring->vaddr, > + 0xdeadbeef, /* trigger a hang if executed */ > + tmp->ring->vma->size / sizeof(u32)); > + > + ce[n] = tmp; > + } > + > + rq = igt_spinner_create_request(spin, ce[0], MI_ARB_CHECK); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + i915_request_get(rq); > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > + i915_request_add(rq); > + > + if (!igt_wait_for_spinner(spin, rq)) { > + intel_gt_set_wedged(engine->gt); > + i915_request_put(rq); > + err = -ETIME; > + goto err_ce; > + } > + > + /* Fill the ring, until we will cause a wrap */ > + n = 0; > + while (ce[0]->ring->tail - rq->wa_tail <= sz) { > + struct i915_request *tmp; > + > + tmp = intel_context_create_request(ce[0]); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + i915_request_put(rq); > + goto err_ce; > + } > + > + i915_request_add(tmp); > + intel_engine_flush_submission(engine); > + n++; > + } > + intel_engine_flush_submission(engine); > + pr_debug("%s: Filled %d with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", > + engine->name, sz, n, > + ce[0]->ring->size, > + ce[0]->ring->tail, > + ce[0]->ring->emit, > + rq->tail); > + GEM_BUG_ON(intel_ring_direction(ce[0]->ring, > + rq->tail, > + ce[0]->ring->tail) <= 0); > + i915_request_put(rq); > + > + /* Create a second request to preempt the first ring */ > + rq = intel_context_create_request(ce[1]); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > + i915_request_get(rq); > + i915_request_add(rq); > + > + err = wait_for_submit(engine, rq, HZ / 2); > + i915_request_put(rq); > + if (err) { > + pr_err("%s: preemption request was not submited\n", > + engine->name); > + err = -ETIME; > + } > + > + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", > + engine->name, > + ce[0]->ring->tail, ce[0]->ring->emit, > + ce[1]->ring->tail, ce[1]->ring->emit); > + > +err_ce: > + intel_engine_flush_submission(engine); > + igt_spinner_end(spin); > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + if (IS_ERR_OR_NULL(ce[n])) > + break; > + > + intel_context_unpin(ce[n]); > + intel_context_put(ce[n]); > + } > + if (igt_live_test_end(&t)) > + err = -EIO; > + return err; > +} > + > +static int live_preempt_ring(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + struct igt_spinner spin; > + enum intel_engine_id id; > + int err = 0; > + > + /* > + * Check that we rollback large chunks of a ring in order to do a > + * preemption event. Similar to live_unlite_ring, but looking at > + * ring size rather than the impact of intel_ring_direction(). > + */ > + > + if (igt_spinner_init(&spin, gt)) > + return -ENOMEM; > + > + for_each_engine(engine, gt, id) { > + int n; > + > + if (!intel_engine_has_preemption(engine)) > + continue; > + > + if (!intel_engine_can_store_dword(engine)) > + continue; > + > + engine_heartbeat_disable(engine); > + > + for (n = 0; n <= 3; n++) { > + err = __live_preempt_ring(engine, &spin, n * SZ_4K / 4); > + if (err) > + break; > + } > + > + engine_heartbeat_enable(engine); > + if (err) > + break; > + } > + > + igt_spinner_fini(&spin); > + return err; > +} > + > static int live_preempt_gang(void *arg) > { > struct intel_gt *gt = arg; > @@ -4538,6 +4700,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) > SUBTEST(live_preempt_cancel), > SUBTEST(live_suppress_self_preempt), > SUBTEST(live_chain_preempt), > + SUBTEST(live_preempt_ring), > SUBTEST(live_preempt_gang), > SUBTEST(live_preempt_timeout), > SUBTEST(live_preempt_user), > -- > 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 16 20:16:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 20:16:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_fix_inconsistent_IS=5FERR_and_PTR=5FERR_=28r?= =?utf-8?q?ev2=29?= In-Reply-To: <20200616145452.GA25291@embeddedor> References: <20200616145452.GA25291@embeddedor> Message-ID: <159233858409.4596.14601318131298520473@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: fix inconsistent IS_ERR and PTR_ERR (rev2) URL : https://patchwork.freedesktop.org/series/38366/ State : success == Summary == CI Bug Log - changes from CI_DRM_8635 -> Patchwork_17965 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/index.html Known issues ------------ Here are the changes found in Patchwork_17965 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at coherency: - fi-gdg-551: [PASS][5] -> [DMESG-FAIL][6] ([i915#1748]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-gdg-551/igt at i915_selftest@live at coherency.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/fi-gdg-551/igt at i915_selftest@live at coherency.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at i915_module_load@reload: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/fi-kbl-x1275/igt at i915_module_load@reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17965 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17965: c02b027d9362eea5bc00596c8d3ba31dc4a9aac5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c02b027d9362 drm/i915/selftests: Fix inconsistent IS_ERR and PTR_ERR == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 20:20:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 20:20:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915=3A_Apply_Wa=5F14011264657=3Agen11+?= In-Reply-To: <20200616163406.27387-1-matthew.s.atwood@intel.com> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> Message-ID: <159233883983.4597.540253862102939845@emeril.freedesktop.org> == Series Details == Series: drm/i915: Apply Wa_14011264657:gen11+ URL : https://patchwork.freedesktop.org/series/78430/ State : warning == Summary == $ dim checkpatch origin/drm-tip 71e1726c303a drm/i915: Apply Wa_14011264657:gen11+ -:19: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #19: FILE: drivers/gpu/drm/i915/display/intel_display.c:3764: +static int icl_min_plane_width(struct drm_i915_private *dev_priv, + const struct drm_framebuffer *fb) -:74: CHECK:BRACES: braces {} should be used on all arms of this statement #74: FILE: drivers/gpu/drm/i915/display/intel_display.c:3878: + if (INTEL_GEN(dev_priv) >= 11) { [...] else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) [...] total: 0 errors, 0 warnings, 2 checks, 78 lines checked From ville.syrjala at linux.intel.com Tue Jun 16 20:22:32 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 16 Jun 2020 23:22:32 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf In-Reply-To: <20200616193056.4817-1-manasi.d.navare@intel.com> References: <20200616193056.4817-1-manasi.d.navare@intel.com> Message-ID: <20200616202232.GL6112@intel.com> On Tue, Jun 16, 2020 at 12:30:56PM -0700, Manasi Navare wrote: > The Bspec sequence expects us to poll for DDI Idle status > to be 0 (not idle) with a timeout of 600usecs after enabling the > DDI BUF CTL. But currently in the driver we just wait for 600usecs > without polling so add that. > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b..de7e15de0bc5 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4023,7 +4023,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > - udelay(600); > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), > + 600)) > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > + port_name(port)); Another thing I just noticed is that icl+ need this for HDMI as well. The slightly odd thing is that glk is documented to need this for DP but not HDMI. But I'm thinking doing it also for glk HDMI should be fine. So I guess to line up with the spec we should: - fixed >518us enable delay for pre-glk (not sure if polling would be ok for hsw/bdw/skl) - poll for enable on glk+ - fixed 16us disable delay for bxt - poll for disable on !bxt And do it for both DP and HDMI for consistency. > } > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > -- > 2.19.1 -- Ville Syrj?l? Intel From gwan-gyeong.mun at intel.com Tue Jun 16 20:33:38 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Tue, 16 Jun 2020 20:33:38 +0000 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch In-Reply-To: <c6ab07cda882b2252030b417a938af8d2b0accab.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-5-jose.souza@intel.com> <20200612163029.GK6112@intel.com> <ee0340f8ea128ed2caa4a6882ded6cb28bf0d8d9.camel@intel.com> <20200615164024.GQ6112@intel.com> <421d8bd4ac0456ac448839194d535777424e6589.camel@intel.com> <c6ab07cda882b2252030b417a938af8d2b0accab.camel@intel.com> Message-ID: <d74e8a0b704d906b1904f66365dbea35e22739ba.camel@intel.com> On Tue, 2020-06-16 at 10:29 -0700, Souza, Jose wrote: > On Tue, 2020-06-16 at 16:16 +0100, Mun, Gwan-gyeong wrote: > > On Mon, 2020-06-15 at 19:40 +0300, Ville Syrj?l? wrote: > > > On Fri, Jun 12, 2020 at 08:33:31PM +0000, Souza, Jose wrote: > > > > On Fri, 2020-06-12 at 19:30 +0300, Ville Syrj?l? wrote: > > > > > On Tue, May 26, 2020 at 03:14:46PM -0700, Jos? Roberto de > > > > > Souza > > > > > wrote: > > > > > > All GEN12 platforms supports PSR2 selective fetch but not > > > > > > all > > > > > > GEN12 > > > > > > platforms supports PSR2 hardware tracking(aka RKL). > > > > > > > > > > > > This feature consists in software program registers with > > > > > > the > > > > > > damaged > > > > > > area of each plane this way hardware will only fetch from > > > > > > memory those > > > > > > areas and sent the PSR2 selective update blocks to panel, > > > > > > saving even > > > > > > more power but to it actually happen userspace needs to > > > > > > send > > > > > > the > > > > > > damaged areas otherwise it will still fetch the whole plane > > > > > > as > > > > > > fallback. > > > > > > As today Gnome3 do not send damaged areas and the only > > > > > > compositor that > > > > > > I'm aware that sets the damaged areas is Weston. > > > > > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > > > > > > > > > > > So here implementing page flip part, it is still completely > > > > > > missing > > > > > > frontbuffer modifications, that is why the > > > > > > enable_psr2_sel_fetch > > > > > > parameter was added. > > > > > > > > > > > > The plan is to switch all GEN12 platforms to selective > > > > > > fetch > > > > > > when > > > > > > ready, it will also depend in add some tests sending > > > > > > damaged > > > > > > areas. > > > > > > I have a hacked version of kms_psr2_su with 3 planes that I > > > > > > can > > > > > > cleanup and send in a few days(99% of PSR2 selective fetch > > > > > > changes was > > > > > > done during my free time while bored during quarantine > > > > > > rainy > > > > > > days). > > > > > > > > > > > > BSpec: 55229 > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > Cc: Imre Deak <imre.deak at intel.com> > > > > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > > > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 5 + > > > > > > .../drm/i915/display/intel_display_debugfs.c | 3 + > > > > > > .../drm/i915/display/intel_display_types.h | 10 + > > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 329 > > > > > > +++++++++++++++++- > > > > > > drivers/gpu/drm/i915/display/intel_psr.h | 10 + > > > > > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 + > > > > > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > > > > > drivers/gpu/drm/i915/i915_params.c | 5 + > > > > > > drivers/gpu/drm/i915/i915_params.h | 1 + > > > > > > 9 files changed, 352 insertions(+), 15 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > index b69878334040..984809208c29 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > @@ -11729,6 +11729,8 @@ static void > > > > > > i9xx_update_cursor(struct > > > > > > intel_plane *plane, > > > > > > if (INTEL_GEN(dev_priv) >= 9) > > > > > > skl_write_cursor_wm(plane, crtc_state); > > > > > > > > > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, > > > > > > plane_state); > > > > > > + > > > > > > if (plane->cursor.base != base || > > > > > > plane->cursor.size != fbc_ctl || > > > > > > plane->cursor.cntl != cntl) { > > > > > > @@ -15115,6 +15117,8 @@ static void > > > > > > commit_pipe_config(struct > > > > > > intel_atomic_state *state, > > > > > > > > > > > > if (new_crtc_state->update_pipe) > > > > > > intel_pipe_fastset(old_crtc_state, > > > > > > new_crtc_state); > > > > > > + > > > > > > + intel_psr2_program_trans_man_trk_ctl(new_crtc_s > > > > > > tate); > > > > > > } > > > > > > > > > > > > if (dev_priv->display.atomic_update_watermarks) > > > > > > @@ -15156,6 +15160,7 @@ static void > > > > > > intel_update_crtc(struct > > > > > > intel_atomic_state *state, > > > > > > intel_color_load_luts(new_crtc_state); > > > > > > > > > > > > intel_pre_plane_update(state, crtc); > > > > > > + intel_psr2_sel_fetch_update(state, crtc); > > > > > > > > > > > > if (new_crtc_state->update_pipe) > > > > > > intel_encoders_update_pipe(state, > > > > > > crtc); > > > > > > diff --git > > > > > > a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > index 70525623bcdf..0f600974462b 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct > > > > > > seq_file *m, void *data) > > > > > > su_blocks = su_blocks >> > > > > > > PSR2_SU_STATUS_SHIFT(frame); > > > > > > seq_printf(m, "%d\t%d\n", frame, > > > > > > su_blocks); > > > > > > } > > > > > > + > > > > > > + seq_printf(m, "PSR2 selective fetch: %s\n", > > > > > > + enableddisabled(psr- > > > > > > > psr2_sel_fetch_enabled)); > > > > > > } > > > > > > > > > > > > unlock: > > > > > > diff --git > > > > > > a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > index 30b2767578dc..b77a512e5362 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > @@ -586,6 +586,13 @@ struct intel_plane_state { > > > > > > u32 planar_slave; > > > > > > > > > > > > struct drm_intel_sprite_colorkey ckey; > > > > > > + > > > > > > + struct { > > > > > > + u32 ctl; > > > > > > + u32 pos; > > > > > > + u32 offset; > > > > > > + u32 size; > > > > > > + } psr2_sel_fetch; > > > > > > > > > > Do we really need all that here? We don't store them for the > > > > > normal > > > > > plane updates either. > > > > > > > > For ctl we do, anyways could be removed if we store overlapping > > > > damage are in here so intel_psr2_program_plane_sel_fetch() > > > > would > > > > incorporate > > > > intel_psr2_plane_sel_fetch_calc() code, both looks good to me. > > > > > > > > > > }; > > > > > > > > > > > > struct intel_initial_plane_config { > > > > > > @@ -931,6 +938,7 @@ struct intel_crtc_state { > > > > > > > > > > > > bool has_psr; > > > > > > bool has_psr2; > > > > > > + bool enable_psr2_sel_fetch; > > > > > > u32 dc3co_exitline; > > > > > > > > > > > > /* > > > > > > @@ -1070,6 +1078,8 @@ struct intel_crtc_state { > > > > > > > > > > > > /* For DSB related info */ > > > > > > struct intel_dsb *dsb; > > > > > > + > > > > > > + u32 psr2_sw_man_track_ctl; > > > > > > }; > > > > > > > > > > > > enum intel_pipe_crc_source { > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > index 0c86e9e341a2..bc2a2e64fe2a 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > @@ -518,6 +518,14 @@ static void hsw_activate_psr2(struct > > > > > > intel_dp *intel_dp) > > > > > > else > > > > > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > > > > > > > > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > > > > > > + intel_de_write(dev_priv, > > > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > > > > psr.transcoder), > > > > > > + PSR2_MAN_TRK_CTL_ENABLE); > > > > > > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > > > > > > + intel_de_write(dev_priv, > > > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > > > > psr.transcoder), 0); > > > > > > + > > > > > > /* > > > > > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and > > > > > > BSpec is > > > > > > * recommending keep this bit unset while PSR2 is > > > > > > enabled. > > > > > > @@ -628,6 +636,38 @@ > > > > > > tgl_dc3co_exitline_compute_config(struct > > > > > > intel_dp *intel_dp, > > > > > > crtc_state->dc3co_exitline = crtc_vdisplay - > > > > > > exit_scanlines; > > > > > > } > > > > > > > > > > > > +static bool intel_psr2_sel_fetch_config_valid(struct > > > > > > intel_dp > > > > > > *intel_dp, > > > > > > + struct > > > > > > intel_crtc_state *crtc_state) > > > > > > +{ > > > > > > + struct intel_atomic_state *state = > > > > > > to_intel_atomic_state(crtc_state->uapi.state); > > > > > > + struct drm_i915_private *dev_priv = > > > > > > dp_to_i915(intel_dp); > > > > > > + struct intel_plane_state *plane_state; > > > > > > + struct intel_plane *plane; > > > > > > + int i; > > > > > > + > > > > > > + if (!i915_modparams.enable_psr2_sel_fetch) { > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > + "PSR2 sel fetch not enabled, > > > > > > disabled by parameter\n"); > > > > > > + return false; > > > > > > + } > > > > > > + > > > > > > + if (crtc_state->uapi.async_flip) { > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > + "PSR2 sel fetch not enabled, async > > > > > > flip enabled\n"); > > > > > > + return false; > > > > > > + } > > > > > > > > > > Not supported anyway. > > > > > > > > > > > + > > > > > > + for_each_new_intel_plane_in_state(state, plane, > > > > > > plane_state, i) { > > > > > > + if (plane_state->uapi.rotation != > > > > > > DRM_MODE_ROTATE_0) { > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > + "PSR2 sel fetch not > > > > > > enabled, plane rotated\n"); > > > > > > + return false; > > > > > > + } > > > > > > + } > > > > > > + > > > > > > + return crtc_state->enable_psr2_sel_fetch = true; > > > > > > +} > > > > > > + > > > > > > static bool intel_psr2_config_valid(struct intel_dp > > > > > > *intel_dp, > > > > > > struct intel_crtc_state > > > > > > *crtc_state) > > > > > > { > > > > > > @@ -697,22 +737,17 @@ static bool > > > > > > intel_psr2_config_valid(struct intel_dp *intel_dp, > > > > > > return false; > > > > > > } > > > > > > > > > > > > - /* > > > > > > - * Some platforms lack PSR2 HW tracking and instead > > > > > > require manual > > > > > > - * tracking by software. In this case, the driver is > > > > > > required to track > > > > > > - * the areas that need updates and program hardware to > > > > > > send selective > > > > > > - * updates. > > > > > > - * > > > > > > - * So until the software tracking is implemented, PSR2 > > > > > > needs to be > > > > > > - * disabled for platforms without PSR2 HW tracking. > > > > > > - */ > > > > > > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > > > > > > - drm_dbg_kms(&dev_priv->drm, > > > > > > - "No PSR2 HW tracking in the > > > > > > platform\n"); > > > > > > - return false; > > > > > > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > > > > > > + if > > > > > > (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) > > > > > > && > > > > > > + !HAS_PSR_HW_TRACKING(dev_priv)) { > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > + "PSR2 not enabled, > > > > > > selective fetch not valid and no HW tracking available\n"); > > > > > > + return false; > > > > > > + } > > > > > > } > > > > > > > > > > > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > > > psr_max_v) { > > > > > > + if (!crtc_state->enable_psr2_sel_fetch && > > > > > > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > > > psr_max_v)) { > > > > > > drm_dbg_kms(&dev_priv->drm, > > > > > > "PSR2 not enabled, resolution %dx%d > > > > > > > max supported %dx%d\n", > > > > > > crtc_hdisplay, crtc_vdisplay, > > > > > > @@ -863,6 +898,11 @@ static void > > > > > > intel_psr_enable_source(struct > > > > > > intel_dp *intel_dp, > > > > > > val |= EXITLINE_ENABLE; > > > > > > intel_de_write(dev_priv, > > > > > > EXITLINE(cpu_transcoder), val); > > > > > > } > > > > > > + > > > > > > + if (HAS_PSR_HW_TRACKING(dev_priv)) > > > > > > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, > > > > > > IGNORE_PSR2_HW_TRACKING, > > > > > > + dev_priv- > > > > > > > psr.psr2_sel_fetch_enabled ? > > > > > > + IGNORE_PSR2_HW_TRACKING : 0); > > > > > > } > > > > > > > > > > > > static void intel_psr_enable_locked(struct > > > > > > drm_i915_private > > > > > > *dev_priv, > > > > > > @@ -884,7 +924,7 @@ static void > > > > > > intel_psr_enable_locked(struct > > > > > > drm_i915_private *dev_priv, > > > > > > /* DC5/DC6 requires at least 6 idle frames */ > > > > > > val = > > > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > > > > > > dev_priv->psr.dc3co_exit_delay = val; > > > > > > - > > > > > > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state- > > > > > > > enable_psr2_sel_fetch; > > > > > > /* > > > > > > * If a PSR error happened and the driver is reloaded, > > > > > > the EDP_PSR_IIR > > > > > > * will still keep the error set even after the reset > > > > > > done in the > > > > > > @@ -1080,6 +1120,265 @@ static void > > > > > > psr_force_hw_tracking_exit(struct drm_i915_private > > > > > > *dev_priv) > > > > > > intel_psr_exit(dev_priv); > > > > > > } > > > > > > > > > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane > > > > > > *plane, > > > > > > + const struct > > > > > > intel_crtc_state *crtc_state, > > > > > > + const struct > > > > > > intel_plane_state *plane_state) > > > > > > +{ > > > > > > + struct drm_i915_private *dev_priv = to_i915(plane- > > > > > > > base.dev); > > > > > > + enum pipe pipe = plane->pipe; > > > > > > + > > > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > > > + !plane_state || > > > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > > > + return; > > > > > > + > > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, > > > > > > plane->id), > > > > > > + plane_state->psr2_sel_fetch.ctl); > > > > > > + if (!plane_state->psr2_sel_fetch.ctl || plane->id == > > > > > > PLANE_CURSOR) > > > > > > + return; > > > > > > + > > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, > > > > > > plane->id), > > > > > > + plane_state->psr2_sel_fetch.pos); > > > > > > + intel_de_write_fw(dev_priv, > > > > > > PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > > > > > > + plane_state->psr2_sel_fetch.offset); > > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, > > > > > > plane->id), > > > > > > + plane_state->psr2_sel_fetch.size); > > > > > > +} > > > > > > + > > > > > > +void intel_psr2_program_trans_man_trk_ctl(const struct > > > > > > intel_crtc_state *crtc_state) > > > > > > +{ > > > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state- > > > > > > > uapi.crtc); > > > > > > + struct drm_i915_private *dev_priv = to_i915(crtc- > > > > > > > base.dev); > > > > > > + struct i915_psr *psr = &dev_priv->psr; > > > > > > + > > > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > > > + return; > > > > > > + > > > > > > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr- > > > > > > > transcoder), > > > > > > + crtc_state->psr2_sw_man_track_ctl); > > > > > > +} > > > > > > + > > > > > > +static void intel_psr2_plane_sel_fetch_calc(struct > > > > > > intel_plane_state *plane_state, > > > > > > + struct drm_rect > > > > > > *clip) > > > > > > +{ > > > > > > + int color_plane = plane_state->planar_linked_plane && > > > > > > !plane_state->planar_slave; > > > > > > + struct intel_plane *plane = to_intel_plane(plane_state- > > > > > > > uapi.plane); > > > > > > + u32 val; > > > > > > + > > > > > > + if (plane->id == PLANE_CURSOR) > > > > > > + return; > > > > > > + > > > > > > + val = (plane_state->color_plane[color_plane].y + clip- > > > > > > > y1) << 16; > > > > > > + val |= plane_state->color_plane[color_plane].x; > > > > > > + plane_state->psr2_sel_fetch.offset = val; > > > > > > + > > > > > > + val = (clip->y1 + plane_state->uapi.crtc_y) << 16; > > > > > > + val |= plane_state->uapi.crtc_x; > > > > > > + plane_state->psr2_sel_fetch.pos = val; > > > > > > + > > > > > > + /* Sizes are 0 based */ > > > > > > + val = (clip->y2 - clip->y1 - 1) << 16; > > > > > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - > > > > > > 1; > > > > > > + plane_state->psr2_sel_fetch.size = val; > > > > > > +} > > > > > > + > > > > > > +static void intel_psr2_trans_man_trk_ctl_calc(struct > > > > > > intel_crtc_state *crtc_state, > > > > > > + struct drm_rect > > > > > > *clip, > > > > > > + bool full_update) > > > > > > +{ > > > > > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE; > > > > > > + > > > > > > + if (full_update) { > > > > > > + val |= PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME; > > > > > > + goto exit; > > > > > > + } > > > > > > + > > > > > > + if (clip->y1 == -1) > > > > > > + goto exit; > > > > > > + > > > > > > + val |= PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE; > > > > > > + val |= PSR2_MAN_TRK_CTL_REGION_START_ADDR(clip->y1 / 4 > > > > > > + 1); > > > > > > + val |= > > > > > > PSR2_MAN_TRK_CTL_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) > > > > > > + > > > > > > 1); > > > > > > +exit: > > > > > > + crtc_state->psr2_sw_man_track_ctl = val; > > > > > > +} > > > > > > + > > > > > > +static void intel_psr2_plane_sel_fetch_ctl_calc(struct > > > > > > intel_plane *plane, > > > > > > + struct > > > > > > intel_plane_state *plane_state, > > > > > > + bool enable) > > > > > > +{ > > > > > > + if (!enable) > > > > > > + plane_state->psr2_sel_fetch.ctl = 0; > > > > > > + else if (plane->id == PLANE_CURSOR) > > > > > > + plane_state->psr2_sel_fetch.ctl = plane- > > > > > > > cursor.cntl; > > > > > > + else > > > > > > + plane_state->psr2_sel_fetch.ctl = plane_state- > > > > > > > ctl; > > > > > > +} > > > > > > + > > > > > > +static void clip_update(struct drm_rect > > > > > > *overlap_damage_area, > > > > > > + struct drm_rect *damage_area) > > > > > > +{ > > > > > > + if (overlap_damage_area->y1 == -1) { > > > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > > > + return; > > > > > > + } > > > > > > + > > > > > > + if (damage_area->y1 < overlap_damage_area->y1) > > > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > > > + > > > > > > + if (damage_area->y2 > overlap_damage_area->y2) > > > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > > > +} > > > > > > + > > > > > > +/* Update plane damage area if planes above moved or have > > > > > > alpha */ > > > > > > +static void intel_psr2_pipe_dirty_areas_set(struct > > > > > > intel_plane_state *plane_state, > > > > > > + struct intel_plane > > > > > > *plane, > > > > > > + const struct > > > > > > drm_rect *pipe_dirty_areas, > > > > > > + struct drm_rect > > > > > > *plane_clip) > > > > > > +{ > > > > > > + enum plane_id i; > > > > > > + > > > > > > + for (i = PLANE_CURSOR; i > plane->id; i--) { > > > > > > + int j; > > > > > > + > > > > > > + for (j = 0; j < 2; j++) { > > > > > > + struct drm_rect r = pipe_dirty_areas[i > > > > > > * 2 + j]; > > > > > > + > > > > > > + if (!drm_rect_width(&r)) > > > > > > + continue; > > > > > > + if (!drm_rect_intersect(&r, > > > > > > &plane_state->uapi.dst)) > > > > > > + continue; > > > > > > + > > > > > > + r.y1 -= plane_state->uapi.crtc_y; > > > > > > + r.y2 -= plane_state->uapi.crtc_y; > > > > > > + clip_update(plane_clip, &r); > > > > > > + } > > > > > > + } > > > > > > +} > > > > > > + > > > > > > +void intel_psr2_sel_fetch_update(struct intel_atomic_state > > > > > > *state, > > > > > > + struct intel_crtc *crtc) > > > > > > +{ > > > > > > + struct intel_crtc_state *crtc_state = > > > > > > intel_atomic_get_new_crtc_state(state, crtc); > > > > > > + struct intel_plane_state *new_plane_state, > > > > > > *old_plane_state; > > > > > > + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = > > > > > > {}; > > > > > > + struct drm_rect pipe_clip = { .y1 = -1 }; > > > > > > + struct intel_plane *plane; > > > > > > + bool full_update = false; > > > > > > + int i; > > > > > > + > > > > > > + if (!crtc_state->enable_psr2_sel_fetch) > > > > > > + return; > > > > > > + > > > > > > + /* > > > > > > + * Load all the pipes areas where there is a plane with > > > > > > alpha or a plane > > > > > > + * that moved or plane that the visibility changed in > > > > > > those > > > > > > + * cases planes bellow it will need to be fetched in > > > > > > those intersection > > > > > > + * areas even if they are not damaged in those areas. > > > > > > + */ > > > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > > > old_plane_state, > > > > > > + new_plane_state, > > > > > > i) { > > > > > > + bool alpha, flip, dirty; > > > > > > + > > > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > > > > uapi.crtc) > > > > > > + continue; > > > > > > + > > > > > > + alpha = new_plane_state->uapi.alpha != U16_MAX; > > > > > > + alpha |= old_plane_state->uapi.alpha != > > > > > > U16_MAX; > > > > > > + flip = new_plane_state->uapi.fb != > > > > > > old_plane_state->uapi.fb; > > > > > > + dirty = alpha && flip; > > > > > > + dirty |= !drm_rect_equals(&new_plane_state- > > > > > > > uapi.dst, > > > > > > + &old_plane_state- > > > > > > > uapi.dst); > > > > > > + dirty |= new_plane_state->uapi.visible != > > > > > > + old_plane_state->uapi.visible; > > > > > > + if (!dirty) > > > > > > + continue; > > > > > > + > > > > > > + if (old_plane_state->uapi.visible) > > > > > > + pipe_dirty_areas[plane->id * 2] = > > > > > > old_plane_state->uapi.dst; > > > > > > + if (new_plane_state->uapi.visible) > > > > > > + pipe_dirty_areas[plane->id * 2 + 1] = > > > > > > new_plane_state->uapi.dst; > > > > > > + } > > > > > > + > > > > > > + /* > > > > > > + * Iterate over all planes, compute the damaged clip > > > > > > area also including > > > > > > + * the pipe_dirty_areas, compute plane registers and > > > > > > update pipe damaged > > > > > > + * area > > > > > > + */ > > > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > > > old_plane_state, > > > > > > + new_plane_state, > > > > > > i) { > > > > > > + struct drm_rect plane_clip = { .y1 = -1 }; > > > > > > + struct drm_mode_rect *clips; > > > > > > + u32 num_clips; > > > > > > + int j; > > > > > > + > > > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > > > > uapi.crtc) > > > > > > + continue; > > > > > > + > > > > > > + /* > > > > > > + * TODO: Not clear how to handle planes with > > > > > > negative position, > > > > > > + * also planes are not updated if they have a > > > > > > negative X > > > > > > + * position so for now doing a full update in > > > > > > this cases > > > > > > + */ > > > > > > + if (new_plane_state->uapi.crtc_y < 0 || > > > > > > + new_plane_state->uapi.crtc_x < 0) { > > > > > > + full_update = true; > > > > > > + break; > > > > > > + } > > > > > > + > > > > > > + intel_psr2_plane_sel_fetch_ctl_calc(plane, > > > > > > new_plane_state, > > > > > > + new_plane_s > > > > > > tate->uapi.visible); > > > > > > + if (!new_plane_state->uapi.visible) > > > > > > + continue; > > > > > > + > > > > > > + clips = > > > > > > drm_plane_get_damage_clips(&new_plane_state->uapi); > > > > > > + num_clips = > > > > > > drm_plane_get_damage_clips_count(&new_plane_state->uapi); > > > > > > + > > > > > > + /* > > > > > > + * If plane moved mark the whole plane area as > > > > > > damaged so it > > > > > > + * can be complete draw in the new position > > > > > > + */ > > > > > > + if (!drm_rect_equals(&new_plane_state- > > > > > > > uapi.dst, > > > > > > + &old_plane_state- > > > > > > > uapi.dst)) { > > > > > > + num_clips = 0; > > > > > > + plane_clip.y1 = new_plane_state- > > > > > > > uapi.src.y1 >> 16; > > > > > > + plane_clip.y2 = new_plane_state- > > > > > > > uapi.src.y2 >> 16; > > > > > > + } else if (!num_clips) { > > > > > > + /* > > > > > > + * If plane don't have damage areas but > > > > > > the framebuffer > > > > > > + * changed mark the whole plane as > > > > > > damaged > > > > > > + */ > > > > > > + if (new_plane_state->uapi.fb == > > > > > > old_plane_state->uapi.fb) > > > > > > + continue; > > > > > > + > > > > > > + plane_clip.y1 = new_plane_state- > > > > > > > uapi.src.y1 >> 16; > > > > > > + plane_clip.y2 = new_plane_state- > > > > > > > uapi.src.y2 >> 16; > > > > > > + } > > > > > > + > > > > > > + for (j = 0; j < num_clips; j++) { > > > > > > + struct drm_rect damage_area; > > > > > > + > > > > > > + damage_area.x1 = clips[j].x1; > > > > > > + damage_area.x2 = clips[j].x2; > > > > > > + damage_area.y1 = clips[j].y1; > > > > > > + damage_area.y2 = clips[j].y2; > > > > > > + clip_update(&plane_clip, &damage_area); > > > > > > + } > > > > > > + > > > > > > + intel_psr2_pipe_dirty_areas_set(new_plane_state > > > > > > , plane, > > > > > > + pipe_dirty_area > > > > > > s, &plane_clip); > > > > > > + intel_psr2_plane_sel_fetch_calc(new_plane_state > > > > > > , &plane_clip); > > > > > > + > > > > > > + plane_clip.y1 += new_plane_state->uapi.crtc_y; > > > > > > + plane_clip.y2 += new_plane_state->uapi.crtc_y; > > > > > > + clip_update(&pipe_clip, &plane_clip); > > > > > > + } > > > > > > > > > > This whole thing seems rather convoluted. Also using lots of > > > > > uapi > > > > > state > > > > > in places where I don't expect to see any. > > > > > > > > Not sure from where I should get this information then, > > > > intel_plane_state don't have it. > > > > > > > > > I would suggest the correct way would be something like: > > > > > 1) for_each_plane_in_state() > > > > > hw.damage = > > > > > translate_to_some_hw_coord_space(union(uapi.damages)) > > > > > or just use the full plane size if we have scaling i > > > > > guess > > > > > > > > 99% of the time the coordinates used are based on pipe coord > > > > space, > > > > only to calculate the plane overlapping damaged area is used > > > > plane > > > > coord space. > > > > > > > > > 2) need to add all affected planes to the state and set the > > > > > appropriate > > > > > bitmask, which may mean we want to track the planes' > > > > > positions > > > > > in the > > > > > crtc state. I think atm we only have it in the plane state > > > > > > > > This looks a "or" to me, have all the planes added to the state > > > > when psr2 sel fetch is enabled or add track all the planes > > > > position > > > > in pipe. > > > > > > *Affected* planes, not all planes. Hmm. I guess affected planes > > > are > > > actually the ones whose selective fetch coordinates change. If > > > they > > > don't change then no need to add them to the state. Plane updates > > > are > > > rather expensive (lots of mmio) so I've generally tried to avoid > > > pointless plane updates. > > > > > > But this whole thing might turn a bit annoying since we'd to keep > > > adding affected planes until the total selective fetch region > > > stops > > > growing. I think that would probably want the two stage plane > > > state > > > compuation. So just blindly adding all of them would probably be > > > simpler, albeit less efficient. > > > > > > > Although the second one would avoid us to do plane calculations > > > > and > > > > plane register sometimes, in some cases where a plane above a > > > > non- > > > > modified plane > > > > moves the non-modified plane bellow will need to be added to > > > > the > > > > state so the plane sel_fetch registers are written. > > > > We could go with the easy one(add all planes to the state) and > > > > then > > > > move to the second one latter. > > > > > > > > > 3) translate the damage further into the final plane src > > > > > coordinate > > > > > space. Dunno if we have enough state around still to do it > > > > > cleanly. > > > > > I was thinking maybe it could be done alongside all the > > > > > other > > > > > plane > > > > > surface calculations, but there might be a chicken vs. egg > > > > > situation > > > > > here since we probably want to do the plane check stuff > > > > > before > > > > > doing > > > > > step 1, but plane check is also where we do the surface > > > > > calculations. > > > > > Dunno if we may just want to split the plane check into > > > > > two > > > > > stages > > > > > > > > As right now it depends mostly in uapi this could be moved to > > > > the > > > > check phase, did not left there because this will never have a > > > > error or a conflict > > > > that will cause us to reject the state. > > > > > > > > > To keep things simple I guess what I'd suggest is to forget > > > > > about > > > > > the > > > > > damage stuff in the first version of the series and just do > > > > > full > > > > > plane updates. That way we don't have to worry about so many > > > > > coordinate > > > > > space transformations. > > > > > > > > Do that would only save us the for bellow and the if to check > > > > if > > > > plane moved: > > > > > > > > for (j = 0; j < num_clips; j++) { > > > > struct drm_rect damage_area; > > > > > > > > damage_area.x1 = clips[j].x1; > > > > damage_area.x2 = clips[j].x2; > > > > damage_area.y1 = clips[j].y1; > > > > damage_area.y2 = clips[j].y2; > > > > clip_update(&plane_clip, &damage_area); > > > > } > > > > > > That's just some minor detail. The real issue is converting the > > > damage > > > between the various coordinate spaces we have for planes > > > (original fb > > > relative src coordiantes, final SURF relative src coordinates, > > > crtc relative dst coordinates, and also the hw vs. uapi stuff > > > affects > > > this stuff). > > > > > For the most efficient power comsumption and usage of bandthwidth, > > we > > can use Selective Fetch of Plane and PSR2 Manual Tracking together. > > But PSR2 Manual Tracking can be enabled without Selective Fetch of > > Plane. (And pre GEN12 does not have a feature "Selective Fetch of > > Plane".) > > So can you split this commit to Selective Fetch and PSR2 Manual > > Tracking? > > Pre GEN12 have selective fetch of plane, check BSpec: 33712 and > 33711. > The programming sequences states that program plane selective fetch > registers and PSR2 Manual tracking must be combined, otherwise HW > don't know if > regular plane registers or selective fetch registers needs to be > used. Hi, (Such as SKL and ICL LP platforms, they don't have a feature of Selective Fetch Plane, therefore when PSR2_MAN_TRK is used, regular plane registers will be used on that platforms. - but PreGEN12 is not scope of this series.) GEN12 (such as TGL LP )platform has "BitField: SF Partial Frame Enable" on Register_PSR2_MAN_TRK_CTL. The desciptions says "This field enables the planes to use the SEL_FETCH registers for selective fetch on selective update frames.". IMHO, this bit can be used to select a plane register (regular or selective fetch) for PSR2_MAN_TRK. From patchwork at emeril.freedesktop.org Tue Jun 16 20:43:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 20:43:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Apply_Wa=5F14011264657=3Agen11+?= In-Reply-To: <20200616163406.27387-1-matthew.s.atwood@intel.com> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> Message-ID: <159234018275.4596.3228176206555330690@emeril.freedesktop.org> == Series Details == Series: drm/i915: Apply Wa_14011264657:gen11+ URL : https://patchwork.freedesktop.org/series/78430/ State : success == Summary == CI Bug Log - changes from CI_DRM_8635 -> Patchwork_17966 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/index.html Known issues ------------ Here are the changes found in Patchwork_17966 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-icl-guc/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at active: - fi-skl-6600u: [PASS][5] -> [DMESG-FAIL][6] ([i915#666]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-skl-6600u/igt at i915_selftest@live at active.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-skl-6600u/igt at i915_selftest@live at active.html * igt at i915_selftest@live at coherency: - fi-gdg-551: [PASS][7] -> [DMESG-FAIL][8] ([i915#1748]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-gdg-551/igt at i915_selftest@live at coherency.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-gdg-551/igt at i915_selftest@live at coherency.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [PASS][9] -> [INCOMPLETE][10] ([i915#1932]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at kms_busy@basic at flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17966 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17966: 71e1726c303a2e7fd80ac1e3e8a4578ffee856c8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 71e1726c303a drm/i915: Apply Wa_14011264657:gen11+ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 20:47:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 20:47:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Check_preemption_rollback_of_different_ring_?= =?utf-8?q?queue_depths?= In-Reply-To: <20200616092833.18498-1-chris@chris-wilson.co.uk> References: <20200616092833.18498-1-chris@chris-wilson.co.uk> Message-ID: <159234047823.4595.1137348750828122907@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Check preemption rollback of different ring queue depths URL : https://patchwork.freedesktop.org/series/78411/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8635_full -> Patchwork_17961_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17961_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17961_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17961_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_whisper@basic-normal: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw2/igt at gem_exec_whisper@basic-normal.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-hsw4/igt at gem_exec_whisper@basic-normal.html Known issues ------------ Here are the changes found in Patchwork_17961_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@process: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl4/igt at gem_ctx_persistence@process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-kbl6/igt at gem_ctx_persistence@process.html * igt at gem_exec_gttfill@all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk6/igt at gem_exec_gttfill@all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-glk2/igt at gem_exec_gttfill@all.html * igt at gem_exec_schedule@implicit-boths at bcs0: - shard-snb: [PASS][7] -> [INCOMPLETE][8] ([i915#82]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-snb6/igt at gem_exec_schedule@implicit-boths at bcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-snb6/igt at gem_exec_schedule@implicit-boths at bcs0.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-random: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#54]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl7/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-random.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][13] -> [FAIL][14] ([i915#57]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw1/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-hsw6/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_cursor_legacy@cursorb-vs-flipb-varying-size: - shard-hsw: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw2/igt at kms_cursor_legacy@cursorb-vs-flipb-varying-size.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-hsw5/igt at kms_cursor_legacy@cursorb-vs-flipb-varying-size.html * igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1928]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl5/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +7 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_flip_tiling@flip-changes-tiling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl8/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][21] -> [DMESG-FAIL][22] ([i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-kbl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#173]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb7/igt at kms_psr@no_drrs.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-iclb7/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend: - shard-skl: [PASS][31] -> [INCOMPLETE][32] ([i915#69]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl9/igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl10/igt at kms_vblank@pipe-b-ts-continuation-dpms-suspend.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][33] -> [INCOMPLETE][34] ([i915#155]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-kbl2/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at perf@create-destroy-userspace-config: - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#402]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at perf@create-destroy-userspace-config.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-tglb8/igt at perf@create-destroy-userspace-config.html * igt at perf@polling-small-buf: - shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#95]) +11 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl3/igt at perf@polling-small-buf.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-apl7/igt at perf@polling-small-buf.html #### Possible fixes #### * igt at gem_ctx_persistence@legacy-engines-hang at render: - shard-tglb: [DMESG-WARN][39] ([i915#402]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb7/igt at gem_ctx_persistence@legacy-engines-hang at render.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-tglb5/igt at gem_ctx_persistence@legacy-engines-hang at render.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][41] ([i915#1930]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@smoketest at bcs0: - shard-tglb: [INCOMPLETE][43] ([i915#1829]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-tglb6/igt at gem_exec_schedule@smoketest at bcs0.html * igt at gem_exec_whisper@basic-queues-priority: - shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk2/igt at gem_exec_whisper@basic-queues-priority.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-glk9/igt at gem_exec_whisper@basic-queues-priority.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl1/igt at gem_mmap_wc@write-cpu-read-wc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-kbl2/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at i915_module_load@reload: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +2 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl9/igt at i915_module_load@reload.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl10/igt at i915_module_load@reload.html * igt at kms_addfb_basic@framebuffer-vs-set-tiling: - shard-apl: [DMESG-WARN][51] ([i915#95]) -> [PASS][52] +12 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl6/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-apl8/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][53] ([IGT#5]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl5/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: - shard-glk: [FAIL][55] ([i915#79]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-glk2/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-kbl7/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][59] ([i915#165] / [i915#78]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-kbl7/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-apl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][63] ([i915#1188]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl9/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb4/igt at kms_psr@psr2_primary_mmap_cpu.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at kms_setmode@basic: - shard-hsw: [FAIL][69] ([i915#31]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw1/igt at kms_setmode@basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-hsw6/igt at kms_setmode@basic.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb8/igt at perf@blocking-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-iclb5/igt at perf@blocking-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [INCOMPLETE][73] ([i915#1635] / [i915#1958]) -> [TIMEOUT][74] ([i915#1635] / [i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt at gem_exec_reloc@basic-concurrent16.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-apl2/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_suspend@fence-restore-untiled: - shard-kbl: [DMESG-WARN][75] ([i915#180]) -> [INCOMPLETE][76] ([i915#155]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-kbl4/igt at i915_suspend@fence-restore-untiled.html * igt at kms_color@pipe-c-ctm-0-25: - shard-tglb: [DMESG-FAIL][77] ([i915#1149] / [i915#1982]) -> [FAIL][78] ([i915#1149] / [i915#315]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-tglb8/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [DMESG-FAIL][79] ([i915#95]) -> [FAIL][80] ([i915#1525]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl4/igt at kms_fbcon_fbt@fbc.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-apl3/igt at kms_fbcon_fbt@fbc.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][81] ([i915#1525]) -> [DMESG-FAIL][82] ([i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl3/igt at kms_fbcon_fbt@fbc-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-apl7/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][83] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][84] ([fdo#108145] / [i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1829]: https://gitlab.freedesktop.org/drm/intel/issues/1829 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17961 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17961: 6fd85c27f831221e7c9b2339ff44f835f8ca19da @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17961/index.html From jose.souza at intel.com Tue Jun 16 21:00:53 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 16 Jun 2020 21:00:53 +0000 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Implement PSR2 selective fetch In-Reply-To: <d74e8a0b704d906b1904f66365dbea35e22739ba.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-5-jose.souza@intel.com> <20200612163029.GK6112@intel.com> <ee0340f8ea128ed2caa4a6882ded6cb28bf0d8d9.camel@intel.com> <20200615164024.GQ6112@intel.com> <421d8bd4ac0456ac448839194d535777424e6589.camel@intel.com> <c6ab07cda882b2252030b417a938af8d2b0accab.camel@intel.com> <d74e8a0b704d906b1904f66365dbea35e22739ba.camel@intel.com> Message-ID: <009de60a01f4a0fe5e1558f385d888685a2f2cef.camel@intel.com> On Tue, 2020-06-16 at 21:33 +0100, Mun, Gwan-gyeong wrote: > On Tue, 2020-06-16 at 10:29 -0700, Souza, Jose wrote: > > On Tue, 2020-06-16 at 16:16 +0100, Mun, Gwan-gyeong wrote: > > > On Mon, 2020-06-15 at 19:40 +0300, Ville Syrj?l? wrote: > > > > On Fri, Jun 12, 2020 at 08:33:31PM +0000, Souza, Jose wrote: > > > > > On Fri, 2020-06-12 at 19:30 +0300, Ville Syrj?l? wrote: > > > > > > On Tue, May 26, 2020 at 03:14:46PM -0700, Jos? Roberto de > > > > > > Souza > > > > > > wrote: > > > > > > > All GEN12 platforms supports PSR2 selective fetch but not > > > > > > > all > > > > > > > GEN12 > > > > > > > platforms supports PSR2 hardware tracking(aka RKL). > > > > > > > > > > > > > > This feature consists in software program registers with > > > > > > > the > > > > > > > damaged > > > > > > > area of each plane this way hardware will only fetch from > > > > > > > memory those > > > > > > > areas and sent the PSR2 selective update blocks to panel, > > > > > > > saving even > > > > > > > more power but to it actually happen userspace needs to > > > > > > > send > > > > > > > the > > > > > > > damaged areas otherwise it will still fetch the whole plane > > > > > > > as > > > > > > > fallback. > > > > > > > As today Gnome3 do not send damaged areas and the only > > > > > > > compositor that > > > > > > > I'm aware that sets the damaged areas is Weston. > > > > > > > https://gitlab.freedesktop.org/wayland/weston/-/merge_requests/17 > > > > > > > > > > > > > > So here implementing page flip part, it is still completely > > > > > > > missing > > > > > > > frontbuffer modifications, that is why the > > > > > > > enable_psr2_sel_fetch > > > > > > > parameter was added. > > > > > > > > > > > > > > The plan is to switch all GEN12 platforms to selective > > > > > > > fetch > > > > > > > when > > > > > > > ready, it will also depend in add some tests sending > > > > > > > damaged > > > > > > > areas. > > > > > > > I have a hacked version of kms_psr2_su with 3 planes that I > > > > > > > can > > > > > > > cleanup and send in a few days(99% of PSR2 selective fetch > > > > > > > changes was > > > > > > > done during my free time while bored during quarantine > > > > > > > rainy > > > > > > > days). > > > > > > > > > > > > > > BSpec: 55229 > > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > Cc: Imre Deak <imre.deak at intel.com> > > > > > > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > > > > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 5 + > > > > > > > .../drm/i915/display/intel_display_debugfs.c | 3 + > > > > > > > .../drm/i915/display/intel_display_types.h | 10 + > > > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 329 > > > > > > > +++++++++++++++++- > > > > > > > drivers/gpu/drm/i915/display/intel_psr.h | 10 + > > > > > > > drivers/gpu/drm/i915/display/intel_sprite.c | 2 + > > > > > > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > > > > > > drivers/gpu/drm/i915/i915_params.c | 5 + > > > > > > > drivers/gpu/drm/i915/i915_params.h | 1 + > > > > > > > 9 files changed, 352 insertions(+), 15 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > index b69878334040..984809208c29 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > @@ -11729,6 +11729,8 @@ static void > > > > > > > i9xx_update_cursor(struct > > > > > > > intel_plane *plane, > > > > > > > if (INTEL_GEN(dev_priv) >= 9) > > > > > > > skl_write_cursor_wm(plane, crtc_state); > > > > > > > > > > > > > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state, > > > > > > > plane_state); > > > > > > > + > > > > > > > if (plane->cursor.base != base || > > > > > > > plane->cursor.size != fbc_ctl || > > > > > > > plane->cursor.cntl != cntl) { > > > > > > > @@ -15115,6 +15117,8 @@ static void > > > > > > > commit_pipe_config(struct > > > > > > > intel_atomic_state *state, > > > > > > > > > > > > > > if (new_crtc_state->update_pipe) > > > > > > > intel_pipe_fastset(old_crtc_state, > > > > > > > new_crtc_state); > > > > > > > + > > > > > > > + intel_psr2_program_trans_man_trk_ctl(new_crtc_s > > > > > > > tate); > > > > > > > } > > > > > > > > > > > > > > if (dev_priv->display.atomic_update_watermarks) > > > > > > > @@ -15156,6 +15160,7 @@ static void > > > > > > > intel_update_crtc(struct > > > > > > > intel_atomic_state *state, > > > > > > > intel_color_load_luts(new_crtc_state); > > > > > > > > > > > > > > intel_pre_plane_update(state, crtc); > > > > > > > + intel_psr2_sel_fetch_update(state, crtc); > > > > > > > > > > > > > > if (new_crtc_state->update_pipe) > > > > > > > intel_encoders_update_pipe(state, > > > > > > > crtc); > > > > > > > diff --git > > > > > > > a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > > index 70525623bcdf..0f600974462b 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > > > > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct > > > > > > > seq_file *m, void *data) > > > > > > > su_blocks = su_blocks >> > > > > > > > PSR2_SU_STATUS_SHIFT(frame); > > > > > > > seq_printf(m, "%d\t%d\n", frame, > > > > > > > su_blocks); > > > > > > > } > > > > > > > + > > > > > > > + seq_printf(m, "PSR2 selective fetch: %s\n", > > > > > > > + enableddisabled(psr- > > > > > > > > psr2_sel_fetch_enabled)); > > > > > > > } > > > > > > > > > > > > > > unlock: > > > > > > > diff --git > > > > > > > a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > > index 30b2767578dc..b77a512e5362 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > > > > > @@ -586,6 +586,13 @@ struct intel_plane_state { > > > > > > > u32 planar_slave; > > > > > > > > > > > > > > struct drm_intel_sprite_colorkey ckey; > > > > > > > + > > > > > > > + struct { > > > > > > > + u32 ctl; > > > > > > > + u32 pos; > > > > > > > + u32 offset; > > > > > > > + u32 size; > > > > > > > + } psr2_sel_fetch; > > > > > > > > > > > > Do we really need all that here? We don't store them for the > > > > > > normal > > > > > > plane updates either. > > > > > > > > > > For ctl we do, anyways could be removed if we store overlapping > > > > > damage are in here so intel_psr2_program_plane_sel_fetch() > > > > > would > > > > > incorporate > > > > > intel_psr2_plane_sel_fetch_calc() code, both looks good to me. > > > > > > > > > > > > }; > > > > > > > > > > > > > > struct intel_initial_plane_config { > > > > > > > @@ -931,6 +938,7 @@ struct intel_crtc_state { > > > > > > > > > > > > > > bool has_psr; > > > > > > > bool has_psr2; > > > > > > > + bool enable_psr2_sel_fetch; > > > > > > > u32 dc3co_exitline; > > > > > > > > > > > > > > /* > > > > > > > @@ -1070,6 +1078,8 @@ struct intel_crtc_state { > > > > > > > > > > > > > > /* For DSB related info */ > > > > > > > struct intel_dsb *dsb; > > > > > > > + > > > > > > > + u32 psr2_sw_man_track_ctl; > > > > > > > }; > > > > > > > > > > > > > > enum intel_pipe_crc_source { > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > > index 0c86e9e341a2..bc2a2e64fe2a 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > > > > > @@ -518,6 +518,14 @@ static void hsw_activate_psr2(struct > > > > > > > intel_dp *intel_dp) > > > > > > > else > > > > > > > val |= EDP_PSR2_TP2_TIME_2500us; > > > > > > > > > > > > > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > > > > > > > + intel_de_write(dev_priv, > > > > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > > > > > psr.transcoder), > > > > > > > + PSR2_MAN_TRK_CTL_ENABLE); > > > > > > > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > > > > > > > + intel_de_write(dev_priv, > > > > > > > + PSR2_MAN_TRK_CTL(dev_priv- > > > > > > > > psr.transcoder), 0); > > > > > > > + > > > > > > > /* > > > > > > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and > > > > > > > BSpec is > > > > > > > * recommending keep this bit unset while PSR2 is > > > > > > > enabled. > > > > > > > @@ -628,6 +636,38 @@ > > > > > > > tgl_dc3co_exitline_compute_config(struct > > > > > > > intel_dp *intel_dp, > > > > > > > crtc_state->dc3co_exitline = crtc_vdisplay - > > > > > > > exit_scanlines; > > > > > > > } > > > > > > > > > > > > > > +static bool intel_psr2_sel_fetch_config_valid(struct > > > > > > > intel_dp > > > > > > > *intel_dp, > > > > > > > + struct > > > > > > > intel_crtc_state *crtc_state) > > > > > > > +{ > > > > > > > + struct intel_atomic_state *state = > > > > > > > to_intel_atomic_state(crtc_state->uapi.state); > > > > > > > + struct drm_i915_private *dev_priv = > > > > > > > dp_to_i915(intel_dp); > > > > > > > + struct intel_plane_state *plane_state; > > > > > > > + struct intel_plane *plane; > > > > > > > + int i; > > > > > > > + > > > > > > > + if (!i915_modparams.enable_psr2_sel_fetch) { > > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > > + "PSR2 sel fetch not enabled, > > > > > > > disabled by parameter\n"); > > > > > > > + return false; > > > > > > > + } > > > > > > > + > > > > > > > + if (crtc_state->uapi.async_flip) { > > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > > + "PSR2 sel fetch not enabled, async > > > > > > > flip enabled\n"); > > > > > > > + return false; > > > > > > > + } > > > > > > > > > > > > Not supported anyway. > > > > > > > > > > > > > + > > > > > > > + for_each_new_intel_plane_in_state(state, plane, > > > > > > > plane_state, i) { > > > > > > > + if (plane_state->uapi.rotation != > > > > > > > DRM_MODE_ROTATE_0) { > > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > > + "PSR2 sel fetch not > > > > > > > enabled, plane rotated\n"); > > > > > > > + return false; > > > > > > > + } > > > > > > > + } > > > > > > > + > > > > > > > + return crtc_state->enable_psr2_sel_fetch = true; > > > > > > > +} > > > > > > > + > > > > > > > static bool intel_psr2_config_valid(struct intel_dp > > > > > > > *intel_dp, > > > > > > > struct intel_crtc_state > > > > > > > *crtc_state) > > > > > > > { > > > > > > > @@ -697,22 +737,17 @@ static bool > > > > > > > intel_psr2_config_valid(struct intel_dp *intel_dp, > > > > > > > return false; > > > > > > > } > > > > > > > > > > > > > > - /* > > > > > > > - * Some platforms lack PSR2 HW tracking and instead > > > > > > > require manual > > > > > > > - * tracking by software. In this case, the driver is > > > > > > > required to track > > > > > > > - * the areas that need updates and program hardware to > > > > > > > send selective > > > > > > > - * updates. > > > > > > > - * > > > > > > > - * So until the software tracking is implemented, PSR2 > > > > > > > needs to be > > > > > > > - * disabled for platforms without PSR2 HW tracking. > > > > > > > - */ > > > > > > > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > > > > > > > - drm_dbg_kms(&dev_priv->drm, > > > > > > > - "No PSR2 HW tracking in the > > > > > > > platform\n"); > > > > > > > - return false; > > > > > > > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > > > > > > > + if > > > > > > > (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) > > > > > > > && > > > > > > > + !HAS_PSR_HW_TRACKING(dev_priv)) { > > > > > > > + drm_dbg_kms(&dev_priv->drm, > > > > > > > + "PSR2 not enabled, > > > > > > > selective fetch not valid and no HW tracking available\n"); > > > > > > > + return false; > > > > > > > + } > > > > > > > } > > > > > > > > > > > > > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > > > > psr_max_v) { > > > > > > > + if (!crtc_state->enable_psr2_sel_fetch && > > > > > > > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > > > > > > > > psr_max_v)) { > > > > > > > drm_dbg_kms(&dev_priv->drm, > > > > > > > "PSR2 not enabled, resolution %dx%d > > > > > > > > max supported %dx%d\n", > > > > > > > crtc_hdisplay, crtc_vdisplay, > > > > > > > @@ -863,6 +898,11 @@ static void > > > > > > > intel_psr_enable_source(struct > > > > > > > intel_dp *intel_dp, > > > > > > > val |= EXITLINE_ENABLE; > > > > > > > intel_de_write(dev_priv, > > > > > > > EXITLINE(cpu_transcoder), val); > > > > > > > } > > > > > > > + > > > > > > > + if (HAS_PSR_HW_TRACKING(dev_priv)) > > > > > > > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, > > > > > > > IGNORE_PSR2_HW_TRACKING, > > > > > > > + dev_priv- > > > > > > > > psr.psr2_sel_fetch_enabled ? > > > > > > > + IGNORE_PSR2_HW_TRACKING : 0); > > > > > > > } > > > > > > > > > > > > > > static void intel_psr_enable_locked(struct > > > > > > > drm_i915_private > > > > > > > *dev_priv, > > > > > > > @@ -884,7 +924,7 @@ static void > > > > > > > intel_psr_enable_locked(struct > > > > > > > drm_i915_private *dev_priv, > > > > > > > /* DC5/DC6 requires at least 6 idle frames */ > > > > > > > val = > > > > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > > > > > > > dev_priv->psr.dc3co_exit_delay = val; > > > > > > > - > > > > > > > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state- > > > > > > > > enable_psr2_sel_fetch; > > > > > > > /* > > > > > > > * If a PSR error happened and the driver is reloaded, > > > > > > > the EDP_PSR_IIR > > > > > > > * will still keep the error set even after the reset > > > > > > > done in the > > > > > > > @@ -1080,6 +1120,265 @@ static void > > > > > > > psr_force_hw_tracking_exit(struct drm_i915_private > > > > > > > *dev_priv) > > > > > > > intel_psr_exit(dev_priv); > > > > > > > } > > > > > > > > > > > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane > > > > > > > *plane, > > > > > > > + const struct > > > > > > > intel_crtc_state *crtc_state, > > > > > > > + const struct > > > > > > > intel_plane_state *plane_state) > > > > > > > +{ > > > > > > > + struct drm_i915_private *dev_priv = to_i915(plane- > > > > > > > > base.dev); > > > > > > > + enum pipe pipe = plane->pipe; > > > > > > > + > > > > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > > > > + !plane_state || > > > > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > > > > + return; > > > > > > > + > > > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, > > > > > > > plane->id), > > > > > > > + plane_state->psr2_sel_fetch.ctl); > > > > > > > + if (!plane_state->psr2_sel_fetch.ctl || plane->id == > > > > > > > PLANE_CURSOR) > > > > > > > + return; > > > > > > > + > > > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, > > > > > > > plane->id), > > > > > > > + plane_state->psr2_sel_fetch.pos); > > > > > > > + intel_de_write_fw(dev_priv, > > > > > > > PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > > > > > > > + plane_state->psr2_sel_fetch.offset); > > > > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, > > > > > > > plane->id), > > > > > > > + plane_state->psr2_sel_fetch.size); > > > > > > > +} > > > > > > > + > > > > > > > +void intel_psr2_program_trans_man_trk_ctl(const struct > > > > > > > intel_crtc_state *crtc_state) > > > > > > > +{ > > > > > > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state- > > > > > > > > uapi.crtc); > > > > > > > + struct drm_i915_private *dev_priv = to_i915(crtc- > > > > > > > > base.dev); > > > > > > > + struct i915_psr *psr = &dev_priv->psr; > > > > > > > + > > > > > > > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > > > > > > > + !crtc_state->enable_psr2_sel_fetch) > > > > > > > + return; > > > > > > > + > > > > > > > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr- > > > > > > > > transcoder), > > > > > > > + crtc_state->psr2_sw_man_track_ctl); > > > > > > > +} > > > > > > > + > > > > > > > +static void intel_psr2_plane_sel_fetch_calc(struct > > > > > > > intel_plane_state *plane_state, > > > > > > > + struct drm_rect > > > > > > > *clip) > > > > > > > +{ > > > > > > > + int color_plane = plane_state->planar_linked_plane && > > > > > > > !plane_state->planar_slave; > > > > > > > + struct intel_plane *plane = to_intel_plane(plane_state- > > > > > > > > uapi.plane); > > > > > > > + u32 val; > > > > > > > + > > > > > > > + if (plane->id == PLANE_CURSOR) > > > > > > > + return; > > > > > > > + > > > > > > > + val = (plane_state->color_plane[color_plane].y + clip- > > > > > > > > y1) << 16; > > > > > > > + val |= plane_state->color_plane[color_plane].x; > > > > > > > + plane_state->psr2_sel_fetch.offset = val; > > > > > > > + > > > > > > > + val = (clip->y1 + plane_state->uapi.crtc_y) << 16; > > > > > > > + val |= plane_state->uapi.crtc_x; > > > > > > > + plane_state->psr2_sel_fetch.pos = val; > > > > > > > + > > > > > > > + /* Sizes are 0 based */ > > > > > > > + val = (clip->y2 - clip->y1 - 1) << 16; > > > > > > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - > > > > > > > 1; > > > > > > > + plane_state->psr2_sel_fetch.size = val; > > > > > > > +} > > > > > > > + > > > > > > > +static void intel_psr2_trans_man_trk_ctl_calc(struct > > > > > > > intel_crtc_state *crtc_state, > > > > > > > + struct drm_rect > > > > > > > *clip, > > > > > > > + bool full_update) > > > > > > > +{ > > > > > > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE; > > > > > > > + > > > > > > > + if (full_update) { > > > > > > > + val |= PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME; > > > > > > > + goto exit; > > > > > > > + } > > > > > > > + > > > > > > > + if (clip->y1 == -1) > > > > > > > + goto exit; > > > > > > > + > > > > > > > + val |= PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE; > > > > > > > + val |= PSR2_MAN_TRK_CTL_REGION_START_ADDR(clip->y1 / 4 > > > > > > > + 1); > > > > > > > + val |= > > > > > > > PSR2_MAN_TRK_CTL_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) > > > > > > > + > > > > > > > 1); > > > > > > > +exit: > > > > > > > + crtc_state->psr2_sw_man_track_ctl = val; > > > > > > > +} > > > > > > > + > > > > > > > +static void intel_psr2_plane_sel_fetch_ctl_calc(struct > > > > > > > intel_plane *plane, > > > > > > > + struct > > > > > > > intel_plane_state *plane_state, > > > > > > > + bool enable) > > > > > > > +{ > > > > > > > + if (!enable) > > > > > > > + plane_state->psr2_sel_fetch.ctl = 0; > > > > > > > + else if (plane->id == PLANE_CURSOR) > > > > > > > + plane_state->psr2_sel_fetch.ctl = plane- > > > > > > > > cursor.cntl; > > > > > > > + else > > > > > > > + plane_state->psr2_sel_fetch.ctl = plane_state- > > > > > > > > ctl; > > > > > > > +} > > > > > > > + > > > > > > > +static void clip_update(struct drm_rect > > > > > > > *overlap_damage_area, > > > > > > > + struct drm_rect *damage_area) > > > > > > > +{ > > > > > > > + if (overlap_damage_area->y1 == -1) { > > > > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > > > > + return; > > > > > > > + } > > > > > > > + > > > > > > > + if (damage_area->y1 < overlap_damage_area->y1) > > > > > > > + overlap_damage_area->y1 = damage_area->y1; > > > > > > > + > > > > > > > + if (damage_area->y2 > overlap_damage_area->y2) > > > > > > > + overlap_damage_area->y2 = damage_area->y2; > > > > > > > +} > > > > > > > + > > > > > > > +/* Update plane damage area if planes above moved or have > > > > > > > alpha */ > > > > > > > +static void intel_psr2_pipe_dirty_areas_set(struct > > > > > > > intel_plane_state *plane_state, > > > > > > > + struct intel_plane > > > > > > > *plane, > > > > > > > + const struct > > > > > > > drm_rect *pipe_dirty_areas, > > > > > > > + struct drm_rect > > > > > > > *plane_clip) > > > > > > > +{ > > > > > > > + enum plane_id i; > > > > > > > + > > > > > > > + for (i = PLANE_CURSOR; i > plane->id; i--) { > > > > > > > + int j; > > > > > > > + > > > > > > > + for (j = 0; j < 2; j++) { > > > > > > > + struct drm_rect r = pipe_dirty_areas[i > > > > > > > * 2 + j]; > > > > > > > + > > > > > > > + if (!drm_rect_width(&r)) > > > > > > > + continue; > > > > > > > + if (!drm_rect_intersect(&r, > > > > > > > &plane_state->uapi.dst)) > > > > > > > + continue; > > > > > > > + > > > > > > > + r.y1 -= plane_state->uapi.crtc_y; > > > > > > > + r.y2 -= plane_state->uapi.crtc_y; > > > > > > > + clip_update(plane_clip, &r); > > > > > > > + } > > > > > > > + } > > > > > > > +} > > > > > > > + > > > > > > > +void intel_psr2_sel_fetch_update(struct intel_atomic_state > > > > > > > *state, > > > > > > > + struct intel_crtc *crtc) > > > > > > > +{ > > > > > > > + struct intel_crtc_state *crtc_state = > > > > > > > intel_atomic_get_new_crtc_state(state, crtc); > > > > > > > + struct intel_plane_state *new_plane_state, > > > > > > > *old_plane_state; > > > > > > > + struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = > > > > > > > {}; > > > > > > > + struct drm_rect pipe_clip = { .y1 = -1 }; > > > > > > > + struct intel_plane *plane; > > > > > > > + bool full_update = false; > > > > > > > + int i; > > > > > > > + > > > > > > > + if (!crtc_state->enable_psr2_sel_fetch) > > > > > > > + return; > > > > > > > + > > > > > > > + /* > > > > > > > + * Load all the pipes areas where there is a plane with > > > > > > > alpha or a plane > > > > > > > + * that moved or plane that the visibility changed in > > > > > > > those > > > > > > > + * cases planes bellow it will need to be fetched in > > > > > > > those intersection > > > > > > > + * areas even if they are not damaged in those areas. > > > > > > > + */ > > > > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > > > > old_plane_state, > > > > > > > + new_plane_state, > > > > > > > i) { > > > > > > > + bool alpha, flip, dirty; > > > > > > > + > > > > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > > > > > uapi.crtc) > > > > > > > + continue; > > > > > > > + > > > > > > > + alpha = new_plane_state->uapi.alpha != U16_MAX; > > > > > > > + alpha |= old_plane_state->uapi.alpha != > > > > > > > U16_MAX; > > > > > > > + flip = new_plane_state->uapi.fb != > > > > > > > old_plane_state->uapi.fb; > > > > > > > + dirty = alpha && flip; > > > > > > > + dirty |= !drm_rect_equals(&new_plane_state- > > > > > > > > uapi.dst, > > > > > > > + &old_plane_state- > > > > > > > > uapi.dst); > > > > > > > + dirty |= new_plane_state->uapi.visible != > > > > > > > + old_plane_state->uapi.visible; > > > > > > > + if (!dirty) > > > > > > > + continue; > > > > > > > + > > > > > > > + if (old_plane_state->uapi.visible) > > > > > > > + pipe_dirty_areas[plane->id * 2] = > > > > > > > old_plane_state->uapi.dst; > > > > > > > + if (new_plane_state->uapi.visible) > > > > > > > + pipe_dirty_areas[plane->id * 2 + 1] = > > > > > > > new_plane_state->uapi.dst; > > > > > > > + } > > > > > > > + > > > > > > > + /* > > > > > > > + * Iterate over all planes, compute the damaged clip > > > > > > > area also including > > > > > > > + * the pipe_dirty_areas, compute plane registers and > > > > > > > update pipe damaged > > > > > > > + * area > > > > > > > + */ > > > > > > > + for_each_oldnew_intel_plane_in_state(state, plane, > > > > > > > old_plane_state, > > > > > > > + new_plane_state, > > > > > > > i) { > > > > > > > + struct drm_rect plane_clip = { .y1 = -1 }; > > > > > > > + struct drm_mode_rect *clips; > > > > > > > + u32 num_clips; > > > > > > > + int j; > > > > > > > + > > > > > > > + if (new_plane_state->uapi.crtc != crtc_state- > > > > > > > > uapi.crtc) > > > > > > > + continue; > > > > > > > + > > > > > > > + /* > > > > > > > + * TODO: Not clear how to handle planes with > > > > > > > negative position, > > > > > > > + * also planes are not updated if they have a > > > > > > > negative X > > > > > > > + * position so for now doing a full update in > > > > > > > this cases > > > > > > > + */ > > > > > > > + if (new_plane_state->uapi.crtc_y < 0 || > > > > > > > + new_plane_state->uapi.crtc_x < 0) { > > > > > > > + full_update = true; > > > > > > > + break; > > > > > > > + } > > > > > > > + > > > > > > > + intel_psr2_plane_sel_fetch_ctl_calc(plane, > > > > > > > new_plane_state, > > > > > > > + new_plane_s > > > > > > > tate->uapi.visible); > > > > > > > + if (!new_plane_state->uapi.visible) > > > > > > > + continue; > > > > > > > + > > > > > > > + clips = > > > > > > > drm_plane_get_damage_clips(&new_plane_state->uapi); > > > > > > > + num_clips = > > > > > > > drm_plane_get_damage_clips_count(&new_plane_state->uapi); > > > > > > > + > > > > > > > + /* > > > > > > > + * If plane moved mark the whole plane area as > > > > > > > damaged so it > > > > > > > + * can be complete draw in the new position > > > > > > > + */ > > > > > > > + if (!drm_rect_equals(&new_plane_state- > > > > > > > > uapi.dst, > > > > > > > + &old_plane_state- > > > > > > > > uapi.dst)) { > > > > > > > + num_clips = 0; > > > > > > > + plane_clip.y1 = new_plane_state- > > > > > > > > uapi.src.y1 >> 16; > > > > > > > + plane_clip.y2 = new_plane_state- > > > > > > > > uapi.src.y2 >> 16; > > > > > > > + } else if (!num_clips) { > > > > > > > + /* > > > > > > > + * If plane don't have damage areas but > > > > > > > the framebuffer > > > > > > > + * changed mark the whole plane as > > > > > > > damaged > > > > > > > + */ > > > > > > > + if (new_plane_state->uapi.fb == > > > > > > > old_plane_state->uapi.fb) > > > > > > > + continue; > > > > > > > + > > > > > > > + plane_clip.y1 = new_plane_state- > > > > > > > > uapi.src.y1 >> 16; > > > > > > > + plane_clip.y2 = new_plane_state- > > > > > > > > uapi.src.y2 >> 16; > > > > > > > + } > > > > > > > + > > > > > > > + for (j = 0; j < num_clips; j++) { > > > > > > > + struct drm_rect damage_area; > > > > > > > + > > > > > > > + damage_area.x1 = clips[j].x1; > > > > > > > + damage_area.x2 = clips[j].x2; > > > > > > > + damage_area.y1 = clips[j].y1; > > > > > > > + damage_area.y2 = clips[j].y2; > > > > > > > + clip_update(&plane_clip, &damage_area); > > > > > > > + } > > > > > > > + > > > > > > > + intel_psr2_pipe_dirty_areas_set(new_plane_state > > > > > > > , plane, > > > > > > > + pipe_dirty_area > > > > > > > s, &plane_clip); > > > > > > > + intel_psr2_plane_sel_fetch_calc(new_plane_state > > > > > > > , &plane_clip); > > > > > > > + > > > > > > > + plane_clip.y1 += new_plane_state->uapi.crtc_y; > > > > > > > + plane_clip.y2 += new_plane_state->uapi.crtc_y; > > > > > > > + clip_update(&pipe_clip, &plane_clip); > > > > > > > + } > > > > > > > > > > > > This whole thing seems rather convoluted. Also using lots of > > > > > > uapi > > > > > > state > > > > > > in places where I don't expect to see any. > > > > > > > > > > Not sure from where I should get this information then, > > > > > intel_plane_state don't have it. > > > > > > > > > > > I would suggest the correct way would be something like: > > > > > > 1) for_each_plane_in_state() > > > > > > hw.damage = > > > > > > translate_to_some_hw_coord_space(union(uapi.damages)) > > > > > > or just use the full plane size if we have scaling i > > > > > > guess > > > > > > > > > > 99% of the time the coordinates used are based on pipe coord > > > > > space, > > > > > only to calculate the plane overlapping damaged area is used > > > > > plane > > > > > coord space. > > > > > > > > > > > 2) need to add all affected planes to the state and set the > > > > > > appropriate > > > > > > bitmask, which may mean we want to track the planes' > > > > > > positions > > > > > > in the > > > > > > crtc state. I think atm we only have it in the plane state > > > > > > > > > > This looks a "or" to me, have all the planes added to the state > > > > > when psr2 sel fetch is enabled or add track all the planes > > > > > position > > > > > in pipe. > > > > > > > > *Affected* planes, not all planes. Hmm. I guess affected planes > > > > are > > > > actually the ones whose selective fetch coordinates change. If > > > > they > > > > don't change then no need to add them to the state. Plane updates > > > > are > > > > rather expensive (lots of mmio) so I've generally tried to avoid > > > > pointless plane updates. > > > > > > > > But this whole thing might turn a bit annoying since we'd to keep > > > > adding affected planes until the total selective fetch region > > > > stops > > > > growing. I think that would probably want the two stage plane > > > > state > > > > compuation. So just blindly adding all of them would probably be > > > > simpler, albeit less efficient. > > > > > > > > > Although the second one would avoid us to do plane calculations > > > > > and > > > > > plane register sometimes, in some cases where a plane above a > > > > > non- > > > > > modified plane > > > > > moves the non-modified plane bellow will need to be added to > > > > > the > > > > > state so the plane sel_fetch registers are written. > > > > > We could go with the easy one(add all planes to the state) and > > > > > then > > > > > move to the second one latter. > > > > > > > > > > > 3) translate the damage further into the final plane src > > > > > > coordinate > > > > > > space. Dunno if we have enough state around still to do it > > > > > > cleanly. > > > > > > I was thinking maybe it could be done alongside all the > > > > > > other > > > > > > plane > > > > > > surface calculations, but there might be a chicken vs. egg > > > > > > situation > > > > > > here since we probably want to do the plane check stuff > > > > > > before > > > > > > doing > > > > > > step 1, but plane check is also where we do the surface > > > > > > calculations. > > > > > > Dunno if we may just want to split the plane check into > > > > > > two > > > > > > stages > > > > > > > > > > As right now it depends mostly in uapi this could be moved to > > > > > the > > > > > check phase, did not left there because this will never have a > > > > > error or a conflict > > > > > that will cause us to reject the state. > > > > > > > > > > > To keep things simple I guess what I'd suggest is to forget > > > > > > about > > > > > > the > > > > > > damage stuff in the first version of the series and just do > > > > > > full > > > > > > plane updates. That way we don't have to worry about so many > > > > > > coordinate > > > > > > space transformations. > > > > > > > > > > Do that would only save us the for bellow and the if to check > > > > > if > > > > > plane moved: > > > > > > > > > > for (j = 0; j < num_clips; j++) { > > > > > struct drm_rect damage_area; > > > > > > > > > > damage_area.x1 = clips[j].x1; > > > > > damage_area.x2 = clips[j].x2; > > > > > damage_area.y1 = clips[j].y1; > > > > > damage_area.y2 = clips[j].y2; > > > > > clip_update(&plane_clip, &damage_area); > > > > > } > > > > > > > > That's just some minor detail. The real issue is converting the > > > > damage > > > > between the various coordinate spaces we have for planes > > > > (original fb > > > > relative src coordiantes, final SURF relative src coordinates, > > > > crtc relative dst coordinates, and also the hw vs. uapi stuff > > > > affects > > > > this stuff). > > > > > > > For the most efficient power comsumption and usage of bandthwidth, > > > we > > > can use Selective Fetch of Plane and PSR2 Manual Tracking together. > > > But PSR2 Manual Tracking can be enabled without Selective Fetch of > > > Plane. (And pre GEN12 does not have a feature "Selective Fetch of > > > Plane".) > > > So can you split this commit to Selective Fetch and PSR2 Manual > > > Tracking? > > > > Pre GEN12 have selective fetch of plane, check BSpec: 33712 and > > 33711. > > The programming sequences states that program plane selective fetch > > registers and PSR2 Manual tracking must be combined, otherwise HW > > don't know if > > regular plane registers or selective fetch registers needs to be > > used. > Hi, > (Such as SKL and ICL LP platforms, they don't have a feature of > Selective Fetch Plane, therefore when PSR2_MAN_TRK is used, regular > plane registers will be used on that platforms. - but PreGEN12 is not > scope of this series.) > GEN12 (such as TGL LP )platform has "BitField: SF Partial Frame > Enable" on Register_PSR2_MAN_TRK_CTL. > The desciptions says "This field enables the planes to use the > SEL_FETCH registers for selective fetch on selective update frames.". > IMHO, this bit can be used to select a plane register (regular or > selective fetch) for PSR2_MAN_TRK. Will only focus in GEN12 in my comments. One of the following must be set to have the panel refreshed: "SF Partial Frame Enable", "SF Continuous full frame" and "SF Continuous full frame". Have a patch that only sets "SF Continuous full frame" or "SF Continuous full frame" would be very simple but then almost complete overwritten for the one using "SF Partial Frame Enable" and like you said the power savings and bandwidth would be at the same level as PSR1, not sure how useful it is. Anyways will check if useful when sending a new version of first 4 patches with comments addressed separated. From imre.deak at intel.com Tue Jun 16 21:11:44 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 17 Jun 2020 00:11:44 +0300 Subject: [Intel-gfx] [PATCH v2 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <20200616211146.23027-1-imre.deak@intel.com> MST encoders must use the master MST transcoder's DP_TP_STATUS and DP_TP_CONTROL registers. Atm, during the HW readout of an MST encoder connected to a slave transcoder we reset these register addresses in intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register addresses incorrectly; fix this. One example where the above overwite happens is the encoder HW state validation after enabling multiple streams; see intel_dp_mst_enc_get_config(). After that during disabling any stream we'll get a 'Timed out waiting for ACT sent when disabling' error, due to reading from the incorrect DP_TP_STATUS register. This change replaces https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 which just papered over the problem. v2: - Correct the failure scenario in the commit log. (Jos?) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..73d6cc29291a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) return; - if (INTEL_GEN(dev_priv) >= 12) { - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); - } - intel_dsc_get_config(encoder, pipe_config); temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, break; } + if (INTEL_GEN(dev_priv) >= 12) { + enum transcoder transcoder = + intel_dp_mst_is_slave_trans(pipe_config) ? + pipe_config->mst_master_transcoder : + pipe_config->cpu_transcoder; + + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); + } + pipe_config->has_audio = intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); -- 2.23.1 From imre.deak at intel.com Tue Jun 16 21:11:45 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 17 Jun 2020 00:11:45 +0300 Subject: [Intel-gfx] [PATCH v2 2/6] drm/i915/dp_mst: Disable link training fallback on MST links In-Reply-To: <20200616141855.746-2-imre.deak@intel.com> References: <20200616141855.746-2-imre.deak@intel.com> Message-ID: <20200616211146.23027-2-imre.deak@intel.com> During the initial probing of an MST sink, MST core will determine the sink's link bandwidth based on its own version of the sink link rate/lane count caps it reads from the DPCD. At a later point (after probing and 1 or more modesets) i915 may limit the link parameters wrt. the original source/sink common caps above due to link training failures during a modeset and the resulting link training fallback logic. Based on the above a modeset following another modeset with a link training error will compute the i915 HW specific and DP protocol timing parameters (data/link M/N and MST TU values) taking into account only the unlimited source/sink common caps, but not taking into account the fallback limits. This will also let DRM core oversubscribe the actual link bandwidth during the MST payload allocation. Prevent the above problem by disabling the link training fallback on MST links for now, until the MST probe time initialization and the MST compute config logic can deal with changing link parameters. The misconfigured timings lead at least to a 'Timed out waiting for DP idle patterns' error. v2: (Ville) - Print link training error message on the MST path too. - Clarify the problem in the commit log. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Manasi Navare <manasi.d.navare at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 ++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..66d9ee94cdd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -468,6 +468,15 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, struct drm_i915_private *i915 = dp_to_i915(intel_dp); int index; + /* + * TODO: Enable fallback on MST links once MST link compute can handle + * the fallback params. + */ + if (intel_dp->is_mst) { + drm_err(&i915->drm, "Link Training Unsuccessful\n"); + return -1; + } + index = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, link_rate); @@ -6163,7 +6172,17 @@ intel_dp_detect(struct drm_connector *connector, goto out; } - if (intel_dp->reset_link_params) { + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ + if (INTEL_GEN(dev_priv) >= 11) + intel_dp_get_dsc_sink_cap(intel_dp); + + intel_dp_configure_mst(intel_dp); + + /* + * TODO: Reset link params when switching to MST mode, until MST + * supports link training fallback params. + */ + if (intel_dp->reset_link_params || intel_dp->is_mst) { /* Initial max link lane count */ intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); @@ -6175,12 +6194,6 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_print_rates(intel_dp); - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ - if (INTEL_GEN(dev_priv) >= 11) - intel_dp_get_dsc_sink_cap(intel_dp); - - intel_dp_configure_mst(intel_dp); - if (intel_dp->is_mst) { /* * If we are in MST mode then this connector -- 2.23.1 From imre.deak at intel.com Tue Jun 16 21:11:46 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 17 Jun 2020 00:11:46 +0300 Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616141855.746-6-imre.deak@intel.com> References: <20200616141855.746-6-imre.deak@intel.com> Message-ID: <20200616211146.23027-3-imre.deak@intel.com> Atm, we clear the ACT sent flag in the sink's DPCD before updating the sink's payload table, along clearing the payload table updated flag. The sink is supposed to set this flag once it detects that the source has completed the ACT sequence (after detecting the 4 required ACT MTPH symbols sent by the source). As opposed to this 2 DELL monitors I have set the flag already along the payload table updated flag, which is not quite correct. To be sure that the sink has detected the ACT MTPH symbols before continuing enabling the encoder, clear the ACT sent flag before enabling or disabling the transcoder VC payload allocation (which is what starts the ACT sequence). v2 (Ville): - Use the correct bit to clear the flags. - Add code comment explaining the clearing semantics of the ACT handled flag. Cc: Lyude Paul <lyude at redhat.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: dri-devel at lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/drm_dp_mst_topology.c | 38 +++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ include/drm/drm_dp_mst_helper.h | 2 ++ 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index b2f5a84b4cfb..1f5d14128c1a 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -4377,6 +4377,41 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, } EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); +/** + * drm_dp_clear_payload_status() - Clears the payload table status flags + * @mgr: manager to use + * + * Clears the payload table ACT handled and table updated flags in the MST hub's + * DPCD. This function must be called before updating the payload table or + * starting the ACT sequence and waiting for the corresponding flags to get + * set by the hub. + * + * Returns: + * 0 if the flags got cleared successfully, otherwise a negative error code. + */ +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) +{ + int ret; + + /* + * Note that the following is based on the DP Standard stating that + * writing the DP_PAYLOAD_TABLE_UPDATED bit alone will clear both the + * DP_PAYLOAD_TABLE_UPDATED and the DP_PAYLOAD_ACT_HANDLED flags. This + * seems to be also the only way to clear DP_PAYLOAD_ACT_HANDLED. + */ + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, + DP_PAYLOAD_TABLE_UPDATED); + if (ret < 0) { + DRM_DEBUG_DRIVER("Can't clear the ACT handled/table updated flags (%d)\n", + ret); + return ret; + } + WARN_ON(ret != 1); + + return 0; +} +EXPORT_SYMBOL(drm_dp_clear_payload_status); + static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload) { @@ -4384,8 +4419,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, int ret; int retries = 0; - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, - DP_PAYLOAD_TABLE_UPDATED); + drm_dp_clear_payload_status(mgr); payload_alloc[0] = id; payload_alloc[1] = payload->start_slot; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 9308b5920780..3c4b0fb10d8b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) intel_de_write(i915, intel_dp->regs.dp_tp_status, DP_TP_STATUS_ACT_SENT); + + drm_dp_clear_payload_status(&intel_dp->mst_mgr); } static void wait_for_act_sent(struct intel_dp *intel_dp) diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 8b9eb4db3381..2facb87624bf 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, int pbn); +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); + int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); -- 2.23.1 From akeem.g.abodunrin at intel.com Tue Jun 16 21:31:45 2020 From: akeem.g.abodunrin at intel.com (Abodunrin, Akeem G) Date: Tue, 16 Jun 2020 21:31:45 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Decouple completed requests on unwind In-Reply-To: <20200616190136.19905-1-chris@chris-wilson.co.uk> References: <20200616190136.19905-1-chris@chris-wilson.co.uk> Message-ID: <BYAPR11MB379930B74EC336F26E655B0FA99D0@BYAPR11MB3799.namprd11.prod.outlook.com> > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Chris > Wilson > Sent: Tuesday, June 16, 2020 12:02 PM > To: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Subject: [Intel-gfx] [PATCH] drm/i915/gt: Decouple completed requests on > unwind > > Since the introduction of preempt-to-busy, requests can complete in the > background, even while they are not on the engine->active.requests list. > As such, the engine->active.request list itself is not in strict retirement order, > and we have to scan the entire list while unwinding to not miss any. > However, if the request is completed we currently leave it on the list [until > retirement], but we could just as simply remove it and stop treating it as > active. We would only have to then traverse it once while unwinding in quick > succession. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > b/drivers/gpu/drm/i915/gt/intel_lrc.c > index e866b8d721ed..4eb397b0e14d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1114,8 +1114,10 @@ __unwind_incomplete_requests(struct > intel_engine_cs *engine) > list_for_each_entry_safe_reverse(rq, rn, > &engine->active.requests, > sched.link) { > - if (i915_request_completed(rq)) > - continue; /* XXX */ > + if (i915_request_completed(rq)) { > + list_del_init(&rq->sched.link); Albeit this seems like a valid approach to resolve inconsistence in the list of requests that are active or retired, but we can't just delete completed requests from the list until full retirement is done - otherwise we stand the risk of out-of-the-order list, and could lead to inconsistence (which is the original problem you intend to resolve). Have you thought about locking mechanism? Regards, ~Akeem > + continue; > + } > > __i915_request_unsubmit(rq); > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Tue Jun 16 21:33:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 21:33:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_fix_missing_null_check_on_allocated_dsb_object?= In-Reply-To: <20200616114221.73971-1-colin.king@canonical.com> References: <20200616114221.73971-1-colin.king@canonical.com> Message-ID: <159234322046.4596.8535606236671819186@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: fix missing null check on allocated dsb object URL : https://patchwork.freedesktop.org/series/78414/ State : success == Summary == CI Bug Log - changes from CI_DRM_8635_full -> Patchwork_17962_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17962_full: ### Piglit changes ### #### Possible regressions #### * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat2x4_array3-position-double_double (NEW): - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat2x4_array3-position-double_double.html * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dvec3_array3-double_dmat2x4_array2-position (NEW): - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dvec3_array3-double_dmat2x4_array2-position.html New tests --------- New tests have been introduced between CI_DRM_8635_full and Patchwork_17962_full: ### New Piglit tests (4) ### * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat2x4_array3-position-double_double: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dvec3_array3-double_dmat2x4_array2-position: - Statuses : 1 crash(s) - Exec time: [0.44] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3x2_array5-float_vec4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_vec4_array3-double_dmat3x4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in Patchwork_17962_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl1/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-glk1/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#95]) +15 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt at gem_mmap_wc@write-cpu-read-wc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-apl1/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at gem_shrink@reclaim: - shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw5/igt at gem_shrink@reclaim.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-hsw1/igt at gem_shrink@reclaim.html * igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk4/igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-glk5/igt at kms_cursor_edge_walk@pipe-c-256x256-bottom-edge.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-hsw: [PASS][13] -> [FAIL][14] ([IGT#5]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw1/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-hsw6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-expired-vblank at b-hdmi-a1: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at kms_flip@flip-vs-expired-vblank at b-hdmi-a1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-glk4/igt at kms_flip@flip-vs-expired-vblank at b-hdmi-a1.html * igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl7/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl1/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-apl1/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#93] / [i915#95]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt at kms_plane@plane-panning-top-left-pipe-b-planes: - shard-snb: [PASS][23] -> [SKIP][24] ([fdo#109271]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-snb6/igt at kms_plane@plane-panning-top-left-pipe-b-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-snb4/igt at kms_plane@plane-panning-top-left-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_psr@suspend: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +12 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl2/igt at kms_psr@suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-skl6/igt at kms_psr@suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][31] -> [INCOMPLETE][32] ([i915#69]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-skl5/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][33] -> [INCOMPLETE][34] ([i915#155]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl3/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at perf_pmu@module-unload: - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#402]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb8/igt at perf_pmu@module-unload.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-tglb1/igt at perf_pmu@module-unload.html #### Possible fixes #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][37] ([i915#1930]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][39] ([i915#82]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-snb1/igt at gem_exec_schedule@implicit-read-write at rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-snb6/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk5/igt at gem_exec_schedule@smoketest-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-glk2/igt at gem_exec_schedule@smoketest-all.html * igt at gem_exec_schedule@smoketest at bcs0: - shard-tglb: [INCOMPLETE][43] ([i915#1829]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-tglb3/igt at gem_exec_schedule@smoketest at bcs0.html * igt at gem_mmap_offset@ptrace at gtt: - shard-kbl: [DMESG-WARN][45] ([i915#93] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl1/igt at gem_mmap_offset@ptrace at gtt.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl3/igt at gem_mmap_offset@ptrace at gtt.html * igt at i915_module_load@reload: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +3 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl9/igt at i915_module_load@reload.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-skl8/igt at i915_module_load@reload.html - shard-tglb: [DMESG-WARN][49] ([i915#402]) -> [PASS][50] +2 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb8/igt at i915_module_load@reload.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-tglb1/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][51] ([IGT#5]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-skl5/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: - shard-glk: [FAIL][53] ([i915#79]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-glk4/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][57] ([i915#165] / [i915#78]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl3/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][61] ([fdo#108145] / [i915#265]) -> [PASS][62] +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_cursor@pipe-b-overlay-size-256: - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [PASS][64] +12 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl1/igt at kms_plane_cursor@pipe-b-overlay-size-256.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-apl8/igt at kms_plane_cursor@pipe-b-overlay-size-256.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb6/igt at kms_psr@psr2_cursor_blt.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html #### Warnings #### * igt at i915_suspend@fence-restore-untiled: - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [INCOMPLETE][68] ([i915#155]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-kbl2/igt at i915_suspend@fence-restore-untiled.html * igt at kms_color@pipe-c-ctm-0-25: - shard-tglb: [DMESG-FAIL][69] ([i915#1149] / [i915#1982]) -> [FAIL][70] ([i915#1149] / [i915#315]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-tglb5/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][71] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][72] ([fdo#108145] / [i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1829]: https://gitlab.freedesktop.org/drm/intel/issues/1829 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17962 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17962: f48c185da47b189fee405b28a4e607332d5b200d @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17962/index.html From chris at chris-wilson.co.uk Tue Jun 16 21:34:52 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 16 Jun 2020 22:34:52 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Decouple completed requests on unwind In-Reply-To: <BYAPR11MB379930B74EC336F26E655B0FA99D0@BYAPR11MB3799.namprd11.prod.outlook.com> References: <20200616190136.19905-1-chris@chris-wilson.co.uk> <BYAPR11MB379930B74EC336F26E655B0FA99D0@BYAPR11MB3799.namprd11.prod.outlook.com> Message-ID: <159234329283.19488.13313421164867153363@build.alporthouse.com> Quoting Abodunrin, Akeem G (2020-06-16 22:31:45) > > > > -----Original Message----- > > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Chris > > Wilson > > Sent: Tuesday, June 16, 2020 12:02 PM > > To: intel-gfx at lists.freedesktop.org > > Cc: Chris Wilson <chris at chris-wilson.co.uk> > > Subject: [Intel-gfx] [PATCH] drm/i915/gt: Decouple completed requests on > > unwind > > > > Since the introduction of preempt-to-busy, requests can complete in the > > background, even while they are not on the engine->active.requests list. > > As such, the engine->active.request list itself is not in strict retirement order, > > and we have to scan the entire list while unwinding to not miss any. > > However, if the request is completed we currently leave it on the list [until > > retirement], but we could just as simply remove it and stop treating it as > > active. We would only have to then traverse it once while unwinding in quick > > succession. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++++-- > > 1 file changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c > > b/drivers/gpu/drm/i915/gt/intel_lrc.c > > index e866b8d721ed..4eb397b0e14d 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > > @@ -1114,8 +1114,10 @@ __unwind_incomplete_requests(struct > > intel_engine_cs *engine) > > list_for_each_entry_safe_reverse(rq, rn, > > &engine->active.requests, > > sched.link) { > > - if (i915_request_completed(rq)) > > - continue; /* XXX */ > > + if (i915_request_completed(rq)) { > > + list_del_init(&rq->sched.link); > > Albeit this seems like a valid approach to resolve inconsistence in the list of requests that are active or retired, but we can't just delete completed requests from the list until full retirement is done - otherwise we stand the risk of out-of-the-order list, and could lead to inconsistence (which is the original problem you intend to resolve). Have you thought about locking mechanism? The list is always in execution [context] order. Within a context it is in retirement order. It is irrelevant whether it is removed here or in remove_from_engine(). -Chris From manasi.d.navare at intel.com Tue Jun 16 21:55:10 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 16 Jun 2020 14:55:10 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf In-Reply-To: <20200616202232.GL6112@intel.com> References: <20200616193056.4817-1-manasi.d.navare@intel.com> <20200616202232.GL6112@intel.com> Message-ID: <20200616215510.GB4903@intel.com> On Tue, Jun 16, 2020 at 11:22:32PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 12:30:56PM -0700, Manasi Navare wrote: > > The Bspec sequence expects us to poll for DDI Idle status > > to be 0 (not idle) with a timeout of 600usecs after enabling the > > DDI BUF CTL. But currently in the driver we just wait for 600usecs > > without polling so add that. > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index ca7bb2294d2b..de7e15de0bc5 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -4023,7 +4023,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > - udelay(600); > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), > > + 600)) > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > + port_name(port)); > > Another thing I just noticed is that icl+ need this for HDMI as well. > The slightly odd thing is that glk is documented to need this for > DP but not HDMI. But I'm thinking doing it also for glk HDMI should > be fine. > > So I guess to line up with the spec we should: > - fixed >518us enable delay for pre-glk (not sure if polling > would be ok for hsw/bdw/skl) > - poll for enable on glk+ > - fixed 16us disable delay for bxt > - poll for disable on !bxt > > And do it for both DP and HDMI for consistency. So since its different one each platform, should we create a per platform hook like wait_for_non_idle_status or something per platform? Manasi > > > > } > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Tue Jun 16 21:54:05 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 21:54:05 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Mark_up_inline_getters_as_taking_a_const_i915=5Freques?= =?utf-8?q?t?= In-Reply-To: <20200616183139.4061-1-chris@chris-wilson.co.uk> References: <20200616183139.4061-1-chris@chris-wilson.co.uk> Message-ID: <159234444504.4596.15052520423953588006@emeril.freedesktop.org> == Series Details == Series: drm/i915: Mark up inline getters as taking a const i915_request URL : https://patchwork.freedesktop.org/series/78432/ State : success == Summary == CI Bug Log - changes from CI_DRM_8636 -> Patchwork_17967 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/index.html Known issues ------------ Here are the changes found in Patchwork_17967 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#262]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][7] ([i915#1888]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([i915#227]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][17] ([i915#665] / [i915#704]) -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8636 -> Patchwork_17967 CI-20190529: 20190529 CI_DRM_8636: dd73f1f0cf1ea35520ff8267e59159be8c884e23 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17967: 1067aa77ab73eca13389452fd6226b33c7fd80a6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1067aa77ab73 drm/i915: Mark up inline getters as taking a const i915_request == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17967/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 21:58:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 21:58:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5BCI=2C1/2=5D_drm/i915/selftests=3A_E?= =?utf-8?q?xercise_far_preemption_rollbacks?= In-Reply-To: <20200616185518.11948-1-chris@chris-wilson.co.uk> References: <20200616185518.11948-1-chris@chris-wilson.co.uk> Message-ID: <159234469746.4596.18052373853409097854@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/2] drm/i915/selftests: Exercise far preemption rollbacks URL : https://patchwork.freedesktop.org/series/78433/ State : warning == Summary == $ dim checkpatch origin/drm-tip 97ec6b6737a1 drm/i915/selftests: Exercise far preemption rollbacks -:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding")' #19: References: e36ba817fa96 ("drm/i915/gt: Incrementally check for rewinding") total: 1 errors, 0 warnings, 0 checks, 163 lines checked f00bbf1a4c7f drm/i915/selftests: Use friendly request names for live_timeslice_rewind From patchwork at emeril.freedesktop.org Tue Jun 16 22:16:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 22:16:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/6=5D_drm/i915/tgl+=3A_Use_the_correct_DP?= =?utf-8?q?=5FTP=5F*_register_instances_in_MST_encoders?= In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <159234578905.4595.10106455518193745480@emeril.freedesktop.org> == Series Details == Series: series starting with [1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders URL : https://patchwork.freedesktop.org/series/78423/ State : success == Summary == CI Bug Log - changes from CI_DRM_8635_full -> Patchwork_17964_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17964_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-apl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl1/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_ctx_persistence@process: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl4/igt at gem_ctx_persistence@process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl7/igt at gem_ctx_persistence@process.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk1/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_workarounds@basic-read: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb3/igt at gem_workarounds@basic-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb7/igt at gem_workarounds@basic-read.html * igt at i915_pm_rps@waitboost: - shard-glk: [PASS][9] -> [FAIL][10] ([i915#39]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at i915_pm_rps@waitboost.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk6/igt at i915_pm_rps@waitboost.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk2/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl4/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html * igt at kms_flip@flip-vs-blocking-wf-vblank at b-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1928]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at kms_flip@flip-vs-blocking-wf-vblank at b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl2/igt at kms_flip@flip-vs-blocking-wf-vblank at b-edp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +10 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_flip_tiling@flip-changes-tiling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl2/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +10 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@psr-farfromfence: - shard-tglb: [PASS][23] -> [SKIP][24] ([i915#668]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb3/igt at kms_frontbuffer_tracking@psr-farfromfence.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb6/igt at kms_frontbuffer_tracking@psr-farfromfence.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr@psr2_cursor_plane_move: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-iclb4/igt at kms_psr@psr2_cursor_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +6 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][31] -> [FAIL][32] ([i915#1820]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_ctx_freq@sysfs: - shard-apl: [DMESG-WARN][33] ([i915#95]) -> [PASS][34] +18 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at gem_ctx_freq@sysfs.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl1/igt at gem_ctx_freq@sysfs.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][35] ([i915#1930]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-snb1/igt at gem_exec_schedule@implicit-read-write at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_schedule@smoketest at bcs0: - shard-tglb: [INCOMPLETE][39] ([i915#1829]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html * igt at gem_exec_whisper@basic-queues-priority: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk2/igt at gem_exec_whisper@basic-queues-priority.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk8/igt at gem_exec_whisper@basic-queues-priority.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][43] ([i915#402]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb8/igt at i915_module_load@reload.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb2/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][45] ([IGT#5]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl10/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-absolute-wf_vblank at a-edp1: - shard-tglb: [FAIL][47] ([i915#1928]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb3/igt at kms_flip@flip-vs-absolute-wf_vblank at a-edp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb6/igt at kms_flip@flip-vs-absolute-wf_vblank at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: - shard-glk: [FAIL][49] ([i915#79]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk6/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][53] ([i915#165] / [i915#78]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl3/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-apl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html * igt at kms_plane@plane-position-covered-pipe-b-planes: - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +6 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl4/igt at kms_plane@plane-position-covered-pipe-b-planes.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl5/igt at kms_plane@plane-position-covered-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] +2 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb5/igt at kms_psr@psr2_sprite_mmap_gtt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb8/igt at perf@blocking-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-iclb5/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_suspend@fence-restore-untiled: - shard-kbl: [DMESG-WARN][65] ([i915#180]) -> [INCOMPLETE][66] ([i915#155]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl4/igt at i915_suspend@fence-restore-untiled.html * igt at kms_color@pipe-c-ctm-0-25: - shard-tglb: [DMESG-FAIL][67] ([i915#1149] / [i915#1982]) -> [FAIL][68] ([i915#1149] / [i915#315]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][69] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][70] ([fdo#108145] / [i915#1982]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1829]: https://gitlab.freedesktop.org/drm/intel/issues/1829 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 10) ------------------------------ Missing (1): pig-icl-1065g7 Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17964 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17964: d302e0a23522a808ab7073bf458e7b70df70def3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 22:20:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 22:20:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BCI=2C1/2=5D_drm/i915/selftests=3A_Exercise?= =?utf-8?q?_far_preemption_rollbacks?= In-Reply-To: <20200616185518.11948-1-chris@chris-wilson.co.uk> References: <20200616185518.11948-1-chris@chris-wilson.co.uk> Message-ID: <159234604918.4598.3027694597053217480@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/2] drm/i915/selftests: Exercise far preemption rollbacks URL : https://patchwork.freedesktop.org/series/78433/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8636 -> Patchwork_17968 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17968 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17968, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17968: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_pm: - fi-icl-y: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-y/igt at i915_selftest@live at gt_pm.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-icl-y/igt at i915_selftest@live at gt_pm.html Known issues ------------ Here are the changes found in Patchwork_17968 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-n2820: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-byt-n2820/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-byt-n2820/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][13] ([i915#1888]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][15] ([i915#95]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][19] ([i915#227]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][25] ([i915#665] / [i915#704]) -> [SKIP][26] ([fdo#109271]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][28] ([i915#62] / [i915#92]) +5 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8636 -> Patchwork_17968 CI-20190529: 20190529 CI_DRM_8636: dd73f1f0cf1ea35520ff8267e59159be8c884e23 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17968: f00bbf1a4c7f4625c4d881070c18d2cb3e3deded @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f00bbf1a4c7f drm/i915/selftests: Use friendly request names for live_timeslice_rewind 97ec6b6737a1 drm/i915/selftests: Exercise far preemption rollbacks == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17968/index.html From jose.souza at intel.com Tue Jun 16 22:38:13 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 16 Jun 2020 22:38:13 +0000 Subject: [Intel-gfx] [PATCH v2 1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders In-Reply-To: <20200616211146.23027-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> <20200616211146.23027-1-imre.deak@intel.com> Message-ID: <c3fddfc00e9400a3e90b77d87350853653952d21.camel@intel.com> On Wed, 2020-06-17 at 00:11 +0300, Imre Deak wrote: > MST encoders must use the master MST transcoder's DP_TP_STATUS and > DP_TP_CONTROL registers. Atm, during the HW readout of an MST encoder > connected to a slave transcoder we reset these register addresses in > intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register > addresses incorrectly; fix this. > > One example where the above overwite happens is the encoder HW state > validation after enabling multiple streams; see > intel_dp_mst_enc_get_config(). After that during disabling any stream > we'll get a > > 'Timed out waiting for ACT sent when disabling' > > error, due to reading from the incorrect DP_TP_STATUS register. > > This change replaces > https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1 > which just papered over the problem. > > v2: > - Correct the failure scenario in the commit log. (Jos?) > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b..73d6cc29291a 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) > return; > > - if (INTEL_GEN(dev_priv) >= 12) { > - intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder); > - intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder); > - } > - > intel_dsc_get_config(encoder, pipe_config); > > temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); > @@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > break; > } > > + if (INTEL_GEN(dev_priv) >= 12) { > + enum transcoder transcoder = > + intel_dp_mst_is_slave_trans(pipe_config) ? > + pipe_config->mst_master_transcoder : > + pipe_config->cpu_transcoder; > + > + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); > + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); > + } > + > pipe_config->has_audio = > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); > From patchwork at emeril.freedesktop.org Tue Jun 16 22:45:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 22:45:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Decouple_completed_requests_on_unwind?= In-Reply-To: <20200616190136.19905-1-chris@chris-wilson.co.uk> References: <20200616190136.19905-1-chris@chris-wilson.co.uk> Message-ID: <159234754953.4597.14429767346535613281@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Decouple completed requests on unwind URL : https://patchwork.freedesktop.org/series/78434/ State : success == Summary == CI Bug Log - changes from CI_DRM_8636 -> Patchwork_17969 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/index.html Known issues ------------ Here are the changes found in Patchwork_17969 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][1] ([i915#1888]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][5] ([i915#227]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][13] ([i915#665] / [i915#704]) -> [SKIP][14] ([fdo#109271]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8636 -> Patchwork_17969 CI-20190529: 20190529 CI_DRM_8636: dd73f1f0cf1ea35520ff8267e59159be8c884e23 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17969: 50e74fde64a5812a37dcd90120b1c061af35e4a7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 50e74fde64a5 drm/i915/gt: Decouple completed requests on unwind == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17969/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 23:02:55 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 23:02:55 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_fix_inconsistent_IS=5FERR_and_PTR=5FERR_=28r?= =?utf-8?q?ev2=29?= In-Reply-To: <20200616145452.GA25291@embeddedor> References: <20200616145452.GA25291@embeddedor> Message-ID: <159234857546.4597.17946911787141602333@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: fix inconsistent IS_ERR and PTR_ERR (rev2) URL : https://patchwork.freedesktop.org/series/38366/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8635_full -> Patchwork_17965_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17965_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17965_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17965_full: ### IGT changes ### #### Possible regressions #### * igt at gem_ctx_persistence@engines-mixed at vecs0: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at gem_ctx_persistence@engines-mixed at vecs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl3/igt at gem_ctx_persistence@engines-mixed at vecs0.html * igt at gem_exec_balancer@bonded-early: - shard-tglb: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at gem_exec_balancer@bonded-early.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb2/igt at gem_exec_balancer@bonded-early.html * igt at gem_exec_whisper@basic-normal: - shard-hsw: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw2/igt at gem_exec_whisper@basic-normal.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-hsw4/igt at gem_exec_whisper@basic-normal.html Known issues ------------ Here are the changes found in Patchwork_17965_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: - shard-tglb: [PASS][7] -> [FAIL][8] ([i915#1528]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb3/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb7/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html * igt at gem_ctx_persistence@process: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl4/igt at gem_ctx_persistence@process.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-kbl7/igt at gem_ctx_persistence@process.html * igt at gem_exec_flush@basic-wb-rw-before-default: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#95]) +19 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt at gem_exec_flush@basic-wb-rw-before-default.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-apl7/igt at gem_exec_flush@basic-wb-rw-before-default.html * igt at gem_exec_whisper@basic-normal-all: - shard-glk: [PASS][13] -> [DMESG-WARN][14] ([i915#118] / [i915#95]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk6/igt at gem_exec_whisper@basic-normal-all.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-glk4/igt at gem_exec_whisper@basic-normal-all.html * igt at gem_shrink@reclaim: - shard-hsw: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw5/igt at gem_shrink@reclaim.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-hsw2/igt at gem_shrink@reclaim.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk6/igt at kms_big_fb@linear-64bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_flip@2x-flip-vs-wf_vblank-interruptible at ab-vga1-hdmi-a1: - shard-hsw: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw8/igt at kms_flip@2x-flip-vs-wf_vblank-interruptible at ab-vga1-hdmi-a1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-hsw6/igt at kms_flip@2x-flip-vs-wf_vblank-interruptible at ab-vga1-hdmi-a1.html * igt at kms_flip@flip-vs-expired-vblank at c-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at c-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at c-edp1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl7/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-kbl3/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html * igt at kms_flip@plain-flip-ts-check at a-edp1: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1928]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl10/igt at kms_flip@plain-flip-ts-check at a-edp1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl8/igt at kms_flip@plain-flip-ts-check at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][29] -> [DMESG-FAIL][30] ([i915#95]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-iclb4/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_psr@suspend: - shard-skl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) +11 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl2/igt at kms_psr@suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl6/igt at kms_psr@suspend.html * igt at kms_setmode@basic: - shard-kbl: [PASS][39] -> [FAIL][40] ([i915#31]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at kms_setmode@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-kbl4/igt at kms_setmode@basic.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][41] -> [FAIL][42] ([i915#1820]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_ctx_freq@sysfs: - shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +20 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at gem_ctx_freq@sysfs.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-apl3/igt at gem_ctx_freq@sysfs.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk5/igt at gem_exec_schedule@smoketest-all.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-glk6/igt at gem_exec_schedule@smoketest-all.html * igt at gem_exec_schedule@smoketest at bcs0: - shard-tglb: [INCOMPLETE][47] ([i915#1829]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb8/igt at gem_exec_schedule@smoketest at bcs0.html * igt at i915_module_load@reload: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +2 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl9/igt at i915_module_load@reload.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl2/igt at i915_module_load@reload.html - shard-tglb: [DMESG-WARN][51] ([i915#402]) -> [PASS][52] +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb8/igt at i915_module_load@reload.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb6/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][53] ([IGT#5]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl3/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: - shard-glk: [FAIL][55] ([i915#79]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-glk5/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt: - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][63] ([fdo#108145] / [i915#265]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb7/igt at kms_psr@psr2_cursor_render.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-iclb2/igt at kms_psr@psr2_cursor_render.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent0: - shard-apl: [FAIL][67] ([i915#1930]) -> [INCOMPLETE][68] ([i915#1926]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl3/igt at gem_exec_reloc@basic-concurrent0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-apl3/igt at gem_exec_reloc@basic-concurrent0.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][69] ([i915#454]) -> [SKIP][70] ([i915#468]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at i915_pm_dc@dc6-dpms.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at kms_color@pipe-c-ctm-0-25: - shard-tglb: [DMESG-FAIL][71] ([i915#1149] / [i915#1982]) -> [FAIL][72] ([i915#1149] / [i915#315]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-tglb2/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding: - shard-kbl: [DMESG-WARN][73] ([i915#93] / [i915#95]) -> [DMESG-FAIL][74] ([i915#54] / [i915#95]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [DMESG-FAIL][75] ([i915#95]) -> [FAIL][76] ([i915#1525]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl4/igt at kms_fbcon_fbt@fbc.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-apl2/igt at kms_fbcon_fbt@fbc.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][77] ([i915#1525]) -> [DMESG-FAIL][78] ([i915#95]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl3/igt at kms_fbcon_fbt@fbc-suspend.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-apl6/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][79] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][80] ([fdo#108145] / [i915#1982]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1829]: https://gitlab.freedesktop.org/drm/intel/issues/1829 [i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 10) ------------------------------ Missing (1): pig-icl-1065g7 Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17965 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17965: c02b027d9362eea5bc00596c8d3ba31dc4a9aac5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17965/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 23:11:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 23:11:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/dp=3A_Poll_for_DDI_Idle_status_to_be_0_after_enabling_DDI?= =?utf-8?q?_Buf?= In-Reply-To: <20200616193056.4817-1-manasi.d.navare@intel.com> References: <20200616193056.4817-1-manasi.d.navare@intel.com> Message-ID: <159234908838.4596.2590011175428845574@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf URL : https://patchwork.freedesktop.org/series/78435/ State : success == Summary == CI Bug Log - changes from CI_DRM_8636 -> Patchwork_17970 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/index.html Known issues ------------ Here are the changes found in Patchwork_17970 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][7] ([i915#227]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][15] ([i915#665] / [i915#704]) -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 40) ------------------------------ Missing (7): fi-ilk-m540 fi-byt-j1900 fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8636 -> Patchwork_17970 CI-20190529: 20190529 CI_DRM_8636: dd73f1f0cf1ea35520ff8267e59159be8c884e23 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17970: 56786c7f15db8d8f1ad41d0e56de30044599d33a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 56786c7f15db drm/i915/dp: Poll for DDI Idle status to be 0 after enabling DDI Buf == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17970/index.html From patchwork at emeril.freedesktop.org Tue Jun 16 23:36:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 23:36:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/6=5D_drm/i915/tgl+=3A_Use_the_corre?= =?utf-8?q?ct_DP=5FTP=5F*_register_instances_in_MST_encoders_=28rev4=29?= In-Reply-To: <20200616141855.746-1-imre.deak@intel.com> References: <20200616141855.746-1-imre.deak@intel.com> Message-ID: <159235059398.4595.7288673509583537991@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders (rev4) URL : https://patchwork.freedesktop.org/series/78423/ State : success == Summary == CI Bug Log - changes from CI_DRM_8636 -> Patchwork_17971 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/index.html Known issues ------------ Here are the changes found in Patchwork_17971 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_chamelium@dp-crc-fast: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#262]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-icl-u2/igt at kms_chamelium@dp-crc-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][9] ([i915#95]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][13] ([i915#227]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-kbl-7500u/igt at kms_chamelium@hdmi-hpd-fast.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at i915_pm_rpm@basic-rte: - fi-kbl-guc: [FAIL][17] ([i915#665] / [i915#704]) -> [SKIP][18] ([fdo#109271]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-kbl-guc/igt at i915_pm_rpm@basic-rte.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8636/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#227]: https://gitlab.freedesktop.org/drm/intel/issues/227 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#665]: https://gitlab.freedesktop.org/drm/intel/issues/665 [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8636 -> Patchwork_17971 CI-20190529: 20190529 CI_DRM_8636: dd73f1f0cf1ea35520ff8267e59159be8c884e23 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17971: 448ae11c4b10098f824f972c5e23f8e35845e27e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 448ae11c4b10 drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it c836c00b27b7 drm/i915/dp_mst: Clear the ACT sent flag during encoder disabling too 129b4b528789 drm/i915/dp_mst: Clear only the ACT sent flag from DP_TP_STATUS 8ded6cb7fc67 drm/i915/dp_mst: Move clearing the ACT sent flag closer to its polling d5591a33514f drm/i915/dp_mst: Disable link training fallback on MST links 6182299efa2a drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17971/index.html From chris at chris-wilson.co.uk Tue Jun 16 23:37:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 00:37:33 +0100 Subject: [Intel-gfx] [CI] drm/i915/selftests: Check preemption rollback of different ring queue depths Message-ID: <20200616233733.18050-1-chris@chris-wilson.co.uk> Like live_unlite_ring, but instead of simply looking at the impact of intel_ring_direction(), check that preemption more generally works with different depths of queued requests in the ring. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 163 +++++++++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index b8b7b91019f4..4f3758a1cbcf 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -2758,6 +2758,168 @@ static int create_gang(struct intel_engine_cs *engine, return err; } +static int __live_preempt_ring(struct intel_engine_cs *engine, + struct igt_spinner *spin, + int queue_sz, int ring_sz) +{ + struct intel_context *ce[2] = {}; + struct i915_request *rq; + struct igt_live_test t; + int err = 0; + int n; + + if (igt_live_test_begin(&t, engine->i915, __func__, engine->name)) + return -EIO; + + for (n = 0; n < ARRAY_SIZE(ce); n++) { + struct intel_context *tmp; + + tmp = intel_context_create(engine); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + goto err_ce; + } + + tmp->ring = __intel_context_ring_size(ring_sz); + + err = intel_context_pin(tmp); + if (err) { + intel_context_put(tmp); + goto err_ce; + } + + memset32(tmp->ring->vaddr, + 0xdeadbeef, /* trigger a hang if executed */ + tmp->ring->vma->size / sizeof(u32)); + + ce[n] = tmp; + } + + rq = igt_spinner_create_request(spin, ce[0], MI_ARB_CHECK); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + i915_request_get(rq); + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_add(rq); + + if (!igt_wait_for_spinner(spin, rq)) { + intel_gt_set_wedged(engine->gt); + i915_request_put(rq); + err = -ETIME; + goto err_ce; + } + + /* Fill the ring, until we will cause a wrap */ + n = 0; + while (ce[0]->ring->tail - rq->wa_tail <= queue_sz) { + struct i915_request *tmp; + + tmp = intel_context_create_request(ce[0]); + if (IS_ERR(tmp)) { + err = PTR_ERR(tmp); + i915_request_put(rq); + goto err_ce; + } + + i915_request_add(tmp); + intel_engine_flush_submission(engine); + n++; + } + intel_engine_flush_submission(engine); + pr_debug("%s: Filled %d with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", + engine->name, queue_sz, n, + ce[0]->ring->size, + ce[0]->ring->tail, + ce[0]->ring->emit, + rq->tail); + i915_request_put(rq); + + /* Create a second request to preempt the first ring */ + rq = intel_context_create_request(ce[1]); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err_ce; + } + + rq->sched.attr.priority = I915_PRIORITY_BARRIER; + i915_request_get(rq); + i915_request_add(rq); + + err = wait_for_submit(engine, rq, HZ / 2); + i915_request_put(rq); + if (err) { + pr_err("%s: preemption request was not submited\n", + engine->name); + err = -ETIME; + } + + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", + engine->name, + ce[0]->ring->tail, ce[0]->ring->emit, + ce[1]->ring->tail, ce[1]->ring->emit); + +err_ce: + intel_engine_flush_submission(engine); + igt_spinner_end(spin); + for (n = 0; n < ARRAY_SIZE(ce); n++) { + if (IS_ERR_OR_NULL(ce[n])) + break; + + intel_context_unpin(ce[n]); + intel_context_put(ce[n]); + } + if (igt_live_test_end(&t)) + err = -EIO; + return err; +} + +static int live_preempt_ring(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + struct igt_spinner spin; + enum intel_engine_id id; + int err = 0; + + /* + * Check that we rollback large chunks of a ring in order to do a + * preemption event. Similar to live_unlite_ring, but looking at + * ring size rather than the impact of intel_ring_direction(). + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + for_each_engine(engine, gt, id) { + int n; + + if (!intel_engine_has_preemption(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + engine_heartbeat_disable(engine); + + for (n = 0; n <= 3; n++) { + err = __live_preempt_ring(engine, &spin, + n * SZ_4K / 4, SZ_4K); + if (err) + break; + } + + engine_heartbeat_enable(engine); + if (err) + break; + } + + igt_spinner_fini(&spin); + return err; +} + static int live_preempt_gang(void *arg) { struct intel_gt *gt = arg; @@ -4540,6 +4702,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) SUBTEST(live_preempt_cancel), SUBTEST(live_suppress_self_preempt), SUBTEST(live_chain_preempt), + SUBTEST(live_preempt_ring), SUBTEST(live_preempt_gang), SUBTEST(live_preempt_timeout), SUBTEST(live_preempt_user), -- 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 16 23:48:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 16 Jun 2020 23:48:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915=3A_Apply_Wa=5F14011264657=3Agen11+?= In-Reply-To: <20200616163406.27387-1-matthew.s.atwood@intel.com> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> Message-ID: <159235130501.4598.16064304597414655657@emeril.freedesktop.org> == Series Details == Series: drm/i915: Apply Wa_14011264657:gen11+ URL : https://patchwork.freedesktop.org/series/78430/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8635_full -> Patchwork_17966_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17966_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17966_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17966_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_balancer@bonded-early: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at gem_exec_balancer@bonded-early.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl7/igt at gem_exec_balancer@bonded-early.html * igt at kms_plane_scaling@pipe-b-scaler-with-pixel-format: - shard-tglb: [PASS][3] -> [FAIL][4] +6 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb7/igt at kms_plane_scaling@pipe-b-scaler-with-pixel-format.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb1/igt at kms_plane_scaling@pipe-b-scaler-with-pixel-format.html * igt at kms_plane_scaling@pipe-d-scaler-with-pixel-format: - shard-tglb: NOTRUN -> [FAIL][5] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb2/igt at kms_plane_scaling@pipe-d-scaler-with-pixel-format.html Known issues ------------ Here are the changes found in Patchwork_17966_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@engines-mixed-process at rcs0: - shard-skl: [PASS][6] -> [FAIL][7] ([i915#1528]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl7/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl3/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html * igt at gem_exec_flush@basic-wb-rw-before-default: - shard-apl: [PASS][8] -> [DMESG-WARN][9] ([i915#95]) +17 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt at gem_exec_flush@basic-wb-rw-before-default.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl4/igt at gem_exec_flush@basic-wb-rw-before-default.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118] / [i915#95]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_shrink@reclaim: - shard-hsw: [PASS][12] -> [SKIP][13] ([fdo#109271]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-hsw5/igt at gem_shrink@reclaim.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-hsw1/igt at gem_shrink@reclaim.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][14] -> [DMESG-FAIL][15] ([i915#118] / [i915#95]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-180.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1: - shard-apl: [PASS][16] -> [FAIL][17] ([i915#79]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-dp1.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-kbl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +5 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl3/igt at kms_flip@flip-vs-suspend at a-dp1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl4/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +7 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_flip_tiling@flip-changes-tiling.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl10/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][22] -> [DMESG-FAIL][23] ([i915#95]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#93] / [i915#95]) +3 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-tglb: [PASS][26] -> [DMESG-WARN][27] ([i915#1982]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][28] -> [FAIL][29] ([fdo#108145] / [i915#265]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-b-scaler-with-rotation: - shard-iclb: [PASS][30] -> [FAIL][31] ([fdo#109052]) +5 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-rotation.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb4/igt at kms_plane_scaling@pipe-b-scaler-with-rotation.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][32] -> [SKIP][33] ([fdo#109441]) +2 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb8/igt at kms_psr@psr2_sprite_plane_move.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][34] -> [FAIL][35] ([i915#1820]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_ctx_freq@sysfs: - shard-apl: [DMESG-WARN][36] ([i915#95]) -> [PASS][37] +19 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at gem_ctx_freq@sysfs.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl8/igt at gem_ctx_freq@sysfs.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [DMESG-WARN][38] ([i915#118] / [i915#95]) -> [PASS][39] +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk5/igt at gem_exec_schedule@smoketest-all.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk9/igt at gem_exec_schedule@smoketest-all.html * igt at gem_exec_schedule@smoketest at bcs0: - shard-tglb: [INCOMPLETE][40] ([i915#1829]) -> [PASS][41] [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb2/igt at gem_exec_schedule@smoketest at bcs0.html * igt at i915_module_load@reload: - shard-skl: [DMESG-WARN][42] ([i915#1982]) -> [PASS][43] +1 similar issue [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl9/igt at i915_module_load@reload.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl9/igt at i915_module_load@reload.html - shard-tglb: [DMESG-WARN][44] ([i915#402]) -> [PASS][45] +2 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb8/igt at i915_module_load@reload.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic: - shard-skl: [FAIL][46] ([IGT#5]) -> [PASS][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: - shard-glk: [FAIL][48] ([i915#79]) -> [PASS][49] +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-glk9/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][50] ([i915#180]) -> [PASS][51] +1 similar issue [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][52] ([i915#165] / [i915#78]) -> [PASS][53] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-kbl3/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: - shard-apl: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt: - shard-tglb: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][58] ([fdo#109441]) -> [PASS][59] +2 similar issues [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb1/igt at kms_psr@psr2_primary_page_flip.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][60] ([i915#1542]) -> [PASS][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb8/igt at perf@blocking-parameterized.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-iclb1/igt at perf@blocking-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [INCOMPLETE][62] ([i915#1635] / [i915#1958]) -> [TIMEOUT][63] ([i915#1635] / [i915#1958]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt at gem_exec_reloc@basic-concurrent16.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl1/igt at gem_exec_reloc@basic-concurrent16.html * igt at kms_color@pipe-c-ctm-0-25: - shard-tglb: [DMESG-FAIL][64] ([i915#1149] / [i915#1982]) -> [FAIL][65] ([i915#1149] / [i915#315]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-tglb3/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [DMESG-FAIL][66] ([i915#95]) -> [FAIL][67] ([i915#1525]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl4/igt at kms_fbcon_fbt@fbc.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl2/igt at kms_fbcon_fbt@fbc.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][68] ([i915#1525]) -> [DMESG-FAIL][69] ([i915#95]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl3/igt at kms_fbcon_fbt@fbc-suspend.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-apl6/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][70] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][71] ([fdo#108145] / [i915#1982]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1829]: https://gitlab.freedesktop.org/drm/intel/issues/1829 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8635 -> Patchwork_17966 CI-20190529: 20190529 CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17966: 71e1726c303a2e7fd80ac1e3e8a4578ffee856c8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17966/index.html From matthew.d.roper at intel.com Tue Jun 16 23:58:05 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 16:58:05 -0700 Subject: [Intel-gfx] [PATCH v6 0/5] Remaining RKL patches Message-ID: <20200616235810.3848540-1-matthew.d.roper@intel.com> Pretty much the same as v5 (and v4). The only changes are: * Extend Wa_1604555607 to RKL in patch #4. * Add display Wa_14011224835 as a new patch #5. Matt Roper (5): drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout drm/i915/rkl: Add DPLL4 support drm/i915/rkl: Handle HTI drm/i915/rkl: Add initial workarounds drm/i915/rkl: Add Wa_14011224835 for PHY B initialization .../gpu/drm/i915/display/intel_combo_phy.c | 26 ++++++ drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++- drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++++++- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++++++++++++------- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 25 +++++- 9 files changed, 213 insertions(+), 48 deletions(-) -- 2.24.1 From matthew.d.roper at intel.com Tue Jun 16 23:58:06 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 16:58:06 -0700 Subject: [Intel-gfx] [PATCH v6 1/5] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout In-Reply-To: <20200616235810.3848540-1-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> Message-ID: <20200616235810.3848540-2-matthew.d.roper@intel.com> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. v2: - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 - Checkpatch style fixes Bspec: 50287 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..8790f221dc77 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, enum phy phy) { - if (intel_phy_is_combo(dev_priv, phy)) { + if (IS_ROCKETLAKE(dev_priv)) { + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + } else if (intel_phy_is_combo(dev_priv, phy)) { return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } else if (intel_phy_is_tc(dev_priv, phy)) { enum tc_port tc_port = intel_port_to_tc(dev_priv, @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { + u32 mask, sel; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } + /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + val &= ~mask; + val |= sel; intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7457813ef273..6c2bb3354b86 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + u32 mask, shift; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } + + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; + id = temp >> shift; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..45bda5819abd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10195,12 +10195,18 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ (tc_port) + 12 : \ (tc_port) - PORT_TC4 + 21)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) /* CNL PLL */ #define DPLL0_ENABLE 0x46010 -- 2.24.1 From matthew.d.roper at intel.com Tue Jun 16 23:58:07 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 16:58:07 -0700 Subject: [Intel-gfx] [PATCH v6 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200616235810.3848540-1-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> Message-ID: <20200616235810.3848540-3-matthew.d.roper@intel.com> Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were DPLL2, so no extra offset handling is needed either. v2: - Add new .update_ref_clks() hook. Bspec: 49202 Bspec: 49443 Bspec: 50288 Bspec: 50289 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b45185b80bec..b5f4d4cef682 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, return false; } - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) + if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - else + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { + dpll_mask = + BIT(DPLL_ID_EHL_DPLL4) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else { dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); + } port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info rkl_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, + { }, +}; + +static const struct intel_dpll_mgr rkl_pll_mgr = { + .dpll_info = rkl_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (INTEL_GEN(dev_priv) >= 12) + if (IS_ROCKETLAKE(dev_priv)) + dpll_mgr = &rkl_pll_mgr; + else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr; else if (IS_ELKHARTLAKE(dev_priv)) dpll_mgr = &ehl_pll_mgr; -- 2.24.1 From matthew.d.roper at intel.com Tue Jun 16 23:58:08 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 16:58:08 -0700 Subject: [Intel-gfx] [PATCH v6 3/5] drm/i915/rkl: Handle HTI In-Reply-To: <20200616235810.3848540-1-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> Message-ID: <20200616235810.3848540-4-matthew.d.roper@intel.com> If HTI (also sometimes called HDPORT) is enabled at startup, it may be using some of the PHYs and DPLLs making them unavailable for general usage. Let's read out the HDPORT_STATE register and avoid making use of resources that HTI is already using. v2: - Fix minor checkpatch warnings Bspec: 49189 Bspec: 53707 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++ 5 files changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6c2bb3354b86..f16512eddc58 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -46,6 +46,7 @@ #include "display/intel_ddi.h" #include "display/intel_dp.h" #include "display/intel_dp_mst.h" +#include "display/intel_dpll_mgr.h" #include "display/intel_dsi.h" #include "display/intel_dvo.h" #include "display/intel_gmbus.h" @@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } +static bool hti_uses_phy(u32 hdport_state, enum phy phy) +{ + return hdport_state & HDPORT_ENABLED && + (hdport_state & HDPORT_PHY_USED_DP(phy) || + hdport_state & HDPORT_PHY_USED_HDMI(phy)); +} + static void intel_setup_outputs(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; @@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_ROCKETLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + /* + * If HTI (aka HDPORT) is enabled at boot, it may have taken + * over some of the PHYs and made them unavailable to the + * driver. In that case we should skip initializing the + * corresponding outputs. + */ + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + + if (!hti_uses_phy(hdport_state, PHY_A)) + intel_ddi_init(dev_priv, PORT_A); + if (!hti_uses_phy(hdport_state, PHY_B)) + intel_ddi_init(dev_priv, PORT_B); + if (!hti_uses_phy(hdport_state, PHY_C)) + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + if (!hti_uses_phy(hdport_state, PHY_D)) + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); @@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) intel_dpll_readout_hw_state(dev_priv); + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); + for_each_intel_encoder(dev, encoder) { pipe = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b5f4d4cef682..6f59f9ec453b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) mutex_unlock(&dev_priv->dpll.lock); } +/* + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them + * unavailable for use. + */ +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) +{ + u32 hdport_state; + + if (!IS_ROCKETLAKE(dev_priv)) + return 0; + + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + if (!(hdport_state & HDPORT_ENABLED)) + return 0; + + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); +} + static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + /* Eliminate DPLLs from consideration if reserved by HTI */ + dpll_mask &= ~dev_priv->hti_pll_mask; + for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { pll = &dev_priv->dpll.shared_dplls[i]; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 5d9a2bc371e7..ac2238646fe7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device *dev); void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..b836032fa0de 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1037,6 +1037,9 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ + u32 hti_pll_mask; + /* * edram size in MB. * Cannot be determined by PCIID. You must always read a register. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 45bda5819abd..90f11517f656 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2909,6 +2909,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) +#define HDPORT_STATE _MMIO(0x45050) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) +#define HDPORT_ENABLED REG_BIT(0) + /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -- 2.24.1 From matthew.d.roper at intel.com Tue Jun 16 23:58:09 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 16:58:09 -0700 Subject: [Intel-gfx] [PATCH v6 4/5] drm/i915/rkl: Add initial workarounds In-Reply-To: <20200616235810.3848540-1-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> Message-ID: <20200616235810.3848540-5-matthew.d.roper@intel.com> RKL and TGL share some general gen12 workarounds, but each platform also has its own platform-specific workarounds. v2: - Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to TGL's, so we'll have both functions call the tgl_ function for now; this workaround isn't listed for DG1 so we don't want to add it to the general gen12_ function. Cc: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++-------- 2 files changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3cd461bf9131..63ac79f88fa2 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0] */ - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) + /* Wa_14010477008:tgl[a0..c0],rkl[all] */ + if (IS_ROCKETLAKE(dev_priv) || + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..741710ca2b9a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) { /* * Wa_1409142259:tgl @@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1409207793:tgl * Wa_1409178076:tgl * Wa_1408979724:tgl + * Wa_14010443199:rkl + * Wa_14010698770:rkl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); + /* WaDisableGPGPUMidThreadPreemption:gen12 */ + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, + GEN9_PREEMPT_GPGPU_LEVEL_MASK, + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); +} + +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + /* - * Wa_1604555607:gen12 and Wa_1608008084:gen12 + * Wa_1604555607:tgl,rkl + * + * Note that the implementation of this workaround is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit * masks. So instead of doing a RMW we should just write the GS Timer @@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 0); - - /* WaDisableGPGPUMidThreadPreemption:tgl */ - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, - GEN9_PREEMPT_GPGPU_LEVEL_MASK, - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); } static void @@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_GEN(i915, 12)) + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 12)) + gen12_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 11)) icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) @@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen12_gt_workarounds_init(struct drm_i915_private *i915, + struct i915_wa_list *wal) { wa_init_mcr(i915, wal); +} + +static void +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) @@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 12)) + gen12_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 11)) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) @@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); - /* - * Wa_1607030317:tgl - * Wa_1607186500:tgl - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 - * of then says it is fixed on B0 the other one says it is - * permanent - */ - wa_masked_en(wal, - GEN6_RC_SLEEP_PSMI_CONTROL, - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE); - /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl */ + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); - /* Wa_1409804808:tgl */ + /* Wa_1409804808:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); - /* Wa_1606700617:tgl */ - wa_masked_en(wal, - GEN9_CS_DEBUG_MODE1, - FF_DOP_CLOCK_GATE_DISABLE); - /* * Wa_1409085225:tgl - * Wa_14010229206:tgl + * Wa_14010229206:tgl,rkl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); + + /* + * Wa_1607030317:tgl + * Wa_1607186500:tgl + * Wa_1607297627:tgl,rkl there are multiple entries for this + * WA in the BSpec; some indicate this is an A0-only WA, + * others indicate it applies to all steppings. + */ + wa_masked_en(wal, + GEN6_RC_SLEEP_PSMI_CONTROL, + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + } + + if (IS_TIGERLAKE(i915)) { + /* Wa_1606700617:tgl */ + wa_masked_en(wal, + GEN9_CS_DEBUG_MODE1, + FF_DOP_CLOCK_GATE_DISABLE); } if (IS_GEN(i915, 11)) { -- 2.24.1 From matthew.d.roper at intel.com Tue Jun 16 23:58:10 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 16:58:10 -0700 Subject: [Intel-gfx] [PATCH v6 5/5] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization In-Reply-To: <20200616235810.3848540-1-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> Message-ID: <20200616235810.3848540-6-matthew.d.roper@intel.com> After doing normal PHY-B initialization on Rocket Lake, we need to manually copy some additional PHY-A register values into PHY-B registers. Note that the bspec's combo phy page doesn't specify that this workaround is restricted to specific platform steppings (and doesn't even do a very good job of specifying that RKL is the only platform this is needed on), but the RKL workaround page lists this as relevant only for A and B steppings, so I'm trusting that information for now. Bspec: 49291 Bspec: 53273 Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 26 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec62..53a1b49e305a 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -338,6 +338,27 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); } +void rkl_combo_phy_b_init_wa(struct drm_i915_private *i915) +{ + u32 grccode, grccode_ldo; + u32 iref_rcal_ord, rcompcode_ld_cap_ov; + + intel_de_wait_for_register(i915, ICL_PORT_COMP_DW3(PHY_A), + FIRST_COMP_DONE, FIRST_COMP_DONE, 100); + + grccode = REG_FIELD_GET(GRCCODE, + intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A))); + iref_rcal_ord = REG_FIELD_PREP(IREF_RCAL_ORD, grccode); + intel_de_rmw(i915, ICL_PORT_COMP_DW2(PHY_B), IREF_RCAL_ORD, + iref_rcal_ord | IREF_RCAL_ORD_EN); + + grccode_ldo = REG_FIELD_GET(GRCCODE_LDO, + intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A))); + rcompcode_ld_cap_ov = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode_ldo); + intel_de_rmw(i915, ICL_PORT_COMP_DW6(PHY_B), RCOMPCODE_LD_CAP_OV, + rcompcode_ld_cap_ov | RCOMPCODEOVEN_LDO_SYNC); +} + static void icl_combo_phys_init(struct drm_i915_private *dev_priv) { enum phy phy; @@ -390,6 +411,11 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); + + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && + phy == PHY_B) + /* Wa_14011224835:rkl[a0..c0] */ + rkl_combo_phy_b_init_wa(dev_priv); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 90f11517f656..9c0d0ca14664 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1909,11 +1909,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CNL_PORT_COMP_DW0 _MMIO(0x162100) #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) -#define COMP_INIT (1 << 31) +#define COMP_INIT REG_BIT(31) +#define GRCCODE_LDO REG_GENMASK(7, 0) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) +#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy)) +#define IREF_RCAL_ORD_EN REG_BIT(7) +#define IREF_RCAL_ORD REG_GENMASK(6, 0) + #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) @@ -1926,6 +1931,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VOLTAGE_INFO_1_05V (2 << 24) #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 +#define FIRST_COMP_DONE REG_BIT(22) + +#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy)) +#define GRCCODE REG_GENMASK(30, 24) +#define RCOMPCODEOVEN_LDO_SYNC REG_BIT(23) +#define RCOMPCODE_LD_CAP_OV REG_GENMASK(22, 16) #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24) -- 2.24.1 From sfr at canb.auug.org.au Wed Jun 17 00:46:12 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Wed, 17 Jun 2020 10:46:12 +1000 Subject: [Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree Message-ID: <20200617104612.59695467@canb.auug.org.au> Hi all, Today's linux-next merge of the drm-misc tree got a conflict in: drivers/gpu/drm/nouveau/nouveau_display.c between commit: 183405879255 ("drm/nouveau/kms: Remove field nvbo from struct nouveau_framebuffer") from Linus' tree and commit: cdc194cebd71 ("drm/nouveau: remove _unlocked suffix in drm_gem_object_put_unlocked") from the drm-misc tree. I fixed it up (the former just removed one of the functions modified by the latter) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200617/1e003b64/attachment.sig> From patchwork at emeril.freedesktop.org Wed Jun 17 00:50:54 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 00:50:54 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Check_preemption_rollback_of_different_ring_?= =?utf-8?q?queue_depths_=28rev2=29?= In-Reply-To: <20200616233733.18050-1-chris@chris-wilson.co.uk> References: <20200616233733.18050-1-chris@chris-wilson.co.uk> Message-ID: <159235505443.29978.17680211880336458237@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Check preemption rollback of different ring queue depths (rev2) URL : https://patchwork.freedesktop.org/series/78411/ State : success == Summary == CI Bug Log - changes from CI_DRM_8637 -> Patchwork_17972 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/index.html Known issues ------------ Here are the changes found in Patchwork_17972 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-apl-guc/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-bsw-n3050: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-y/igt at i915_selftest@live at execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][13] ([i915#1233]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][21] ([fdo#109271]) -> [DMESG-FAIL][22] ([i915#62]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8637 -> Patchwork_17972 CI-20190529: 20190529 CI_DRM_8637: 091db6eff650d91a12485725f764bc60909344fb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17972: c94fe0724411deaec7f7d5c29975200cbaa2cb9f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c94fe0724411 drm/i915/selftests: Check preemption rollback of different ring queue depths == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 00:56:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 00:56:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Remaining_RKL_patches_=28rev5=29?= In-Reply-To: <20200616235810.3848540-1-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> Message-ID: <159235540151.29978.16520775095276722426@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev5) URL : https://patchwork.freedesktop.org/series/77971/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_combo_phy.c:341:6: warning: symbol 'rkl_combo_phy_b_init_wa' was not declared. Should it be static? From sfr at canb.auug.org.au Wed Jun 17 00:59:29 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Wed, 17 Jun 2020 10:59:29 +1000 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree Message-ID: <20200617105929.534edd34@canb.auug.org.au> Hi all, After merging the drm-misc tree, today's linux-next build (x86_64 allmodconfig) failed like this: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c: In function 'amdgpu_amdkfd_gpuvm_free_memory_of_gpu': drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1357:2: error: implicit declaration of function 'drm_gem_object_put_unlocked'; did you mean 'drm_gem_object_put_locked'? [-Werror=implicit-function-declaration] 1357 | drm_gem_object_put_unlocked(&mem->bo->tbo.base); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ | drm_gem_object_put_locked Caused by commit ab15d56e27be ("drm: remove transient drm_gem_object_put_unlocked()") interacting with commit fd9a9f8801de ("drm/amdgpu: Use GEM obj reference for KFD BOs") from Linus' tree. I have applied the following merge fix up patch for today. From: Stephen Rothwell <sfr at canb.auug.org.au> Date: Wed, 17 Jun 2020 10:55:32 +1000 Subject: [PATCH] drm/amdgpu: remove stray drm_gem_object_put_unlocked Signed-off-by: Stephen Rothwell <sfr at canb.auug.org.au> --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index b91b5171270f..9015c7b76d60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1354,7 +1354,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( } /* Free the BO*/ - drm_gem_object_put_unlocked(&mem->bo->tbo.base); + drm_gem_object_put(&mem->bo->tbo.base); mutex_destroy(&mem->lock); kfree(mem); -- 2.26.2 -- Cheers, Stephen Rothwell -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200617/fcb78128/attachment.sig> From lucas.demarchi at intel.com Wed Jun 17 01:11:13 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Tue, 16 Jun 2020 18:11:13 -0700 Subject: [Intel-gfx] [PATCH v6 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200616235810.3848540-3-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> <20200616235810.3848540-3-matthew.d.roper@intel.com> Message-ID: <20200617011113.o5ghzgk2ileysqrm@ldmartin-desk1> On Tue, Jun 16, 2020 at 04:58:07PM -0700, Matt Roper wrote: >Rocket Lake has a third DPLL (called 'DPLL4') that must be used to >enable a third display. Unlike EHL's variant of DPLL4, the RKL variant >behaves the same as DPLL0/1. And despite its name, the DPLL4 registers >are offset as if it were DPLL2, so no extra offset handling is needed >either. > >v2: > - Add new .update_ref_clks() hook. > >Bspec: 49202 >Bspec: 49443 >Bspec: 50288 >Bspec: 50289 >Cc: Lucas De Marchi <lucas.demarchi at intel.com> >Signed-off-by: Matt Roper <matthew.d.roper at intel.com> >--- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- > 1 file changed, 26 insertions(+), 3 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >index b45185b80bec..b5f4d4cef682 100644 >--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >@@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, > return false; > } > >- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) >+ if (IS_ROCKETLAKE(dev_priv)) { > dpll_mask = > BIT(DPLL_ID_EHL_DPLL4) | > BIT(DPLL_ID_ICL_DPLL1) | > BIT(DPLL_ID_ICL_DPLL0); I don't think that is sufficient. As you said in the commit message, here DPLL4 are much like DPLL0, DPLL1 rather than the special treatment it has in EHL. That means we need to update the places making use of it. Example: TGL_DPLL_CFGCR0() TGL_DPLL_CFGCR1() The way it is now, it would basically be using the address 0x16429C / 0x1642A0 that are actually for TBT Looking at bspec 50288, it seems we should reorder the IDs to be DPLL0, DPLL1, DPLL4, TBTPLL. Then we can go back and use _MMIO_PLL() rather than _MMIO_PLL3(). There is even a "TODO" in the right place in the source code for that, although I don't remember if in TGL it has any special. I think we never added it for TGL just because with 2 combo ports you will never need 3 PLLs. Lucas De Marchi >- else >+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { >+ dpll_mask = >+ BIT(DPLL_ID_EHL_DPLL4) | >+ BIT(DPLL_ID_ICL_DPLL1) | >+ BIT(DPLL_ID_ICL_DPLL0); >+ } else { > dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); >+ } > > port_dpll->pll = intel_find_shared_dpll(state, crtc, > &port_dpll->hw_state, >@@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { > .dump_hw_state = icl_dump_hw_state, > }; > >+static const struct dpll_info rkl_plls[] = { >+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, >+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, >+ { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, >+ { }, >+}; >+ >+static const struct intel_dpll_mgr rkl_pll_mgr = { >+ .dpll_info = rkl_plls, >+ .get_dplls = icl_get_dplls, >+ .put_dplls = icl_put_dplls, >+ .update_ref_clks = icl_update_dpll_ref_clks, >+ .dump_hw_state = icl_dump_hw_state, >+}; >+ > /** > * intel_shared_dpll_init - Initialize shared DPLLs > * @dev: drm device >@@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) > const struct dpll_info *dpll_info; > int i; > >- if (INTEL_GEN(dev_priv) >= 12) >+ if (IS_ROCKETLAKE(dev_priv)) >+ dpll_mgr = &rkl_pll_mgr; >+ else if (INTEL_GEN(dev_priv) >= 12) > dpll_mgr = &tgl_pll_mgr; > else if (IS_ELKHARTLAKE(dev_priv)) > dpll_mgr = &ehl_pll_mgr; >-- >2.24.1 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx at lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Wed Jun 17 01:16:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 01:16:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev5=29?= In-Reply-To: <20200616235810.3848540-1-matthew.d.roper@intel.com> References: <20200616235810.3848540-1-matthew.d.roper@intel.com> Message-ID: <159235658505.29977.16840557648278005438@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev5) URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8637 -> Patchwork_17973 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/index.html Known issues ------------ Here are the changes found in Patchwork_17973 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-byt-j1900/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-byt-j1900/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][5] -> [DMESG-WARN][6] ([i915#62] / [i915#92] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-kbl-x1275/igt at kms_busy@basic at flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][11] ([i915#1888]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [INCOMPLETE][15] -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-y/igt at i915_selftest@live at execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][19] ([fdo#109271]) -> [DMESG-FAIL][20] ([i915#62]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +6 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8637 -> Patchwork_17973 CI-20190529: 20190529 CI_DRM_8637: 091db6eff650d91a12485725f764bc60909344fb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17973: 1d222fefb84f2d28b15a164a357f39db9d3f35e6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1d222fefb84f drm/i915/rkl: Add Wa_14011224835 for PHY B initialization fae694548268 drm/i915/rkl: Add initial workarounds 1a857648140e drm/i915/rkl: Handle HTI b9801bb978f8 drm/i915/rkl: Add DPLL4 support 54d1bd2f5f04 drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17973/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 01:46:15 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 01:46:15 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_linux-next=3A_build_failure_after_merge_of_the_drm-misc_tre?= =?utf-8?q?e?= In-Reply-To: <20200617105929.534edd34@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> Message-ID: <159235837586.29978.6433340452681460996@emeril.freedesktop.org> == Series Details == Series: linux-next: build failure after merge of the drm-misc tree URL : https://patchwork.freedesktop.org/series/78444/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5bf216c35bb2 linux-next: build failure after merge of the drm-misc tree -:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit ab15d56e27be ("drm: remove transient drm_gem_object_put_unlocked()")' #19: ab15d56e27be ("drm: remove transient drm_gem_object_put_unlocked()") -:23: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit fd9a9f8801de ("drm/amdgpu: Use GEM obj reference for KFD BOs")' #23: fd9a9f8801de ("drm/amdgpu: Use GEM obj reference for KFD BOs") total: 2 errors, 0 warnings, 0 checks, 8 lines checked From patchwork at emeril.freedesktop.org Wed Jun 17 02:07:48 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 02:07:48 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgbGlu?= =?utf-8?q?ux-next=3A_build_failure_after_merge_of_the_drm-misc_tree?= In-Reply-To: <20200617105929.534edd34@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> Message-ID: <159235966862.29979.15310466158223485907@emeril.freedesktop.org> == Series Details == Series: linux-next: build failure after merge of the drm-misc tree URL : https://patchwork.freedesktop.org/series/78444/ State : success == Summary == CI Bug Log - changes from CI_DRM_8638 -> Patchwork_17974 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/index.html Known issues ------------ Here are the changes found in Patchwork_17974 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][5] ([i915#95]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_selftest@live at active: - fi-icl-y: [DMESG-FAIL][7] ([i915#765]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-icl-y/igt at i915_selftest@live at active.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-icl-y/igt at i915_selftest@live at active.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][9] ([i915#1233]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][13] ([fdo#109271]) -> [DMESG-FAIL][14] ([i915#62]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 42) ------------------------------ Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8638 -> Patchwork_17974 CI-20190529: 20190529 CI_DRM_8638: 83818e4910cac8b84d8f915c773ab3f55fa30365 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17974: 5bf216c35bb20d8eed4b272e9d273906b8a2e514 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5bf216c35bb2 linux-next: build failure after merge of the drm-misc tree == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/index.html From matthew.d.roper at intel.com Wed Jun 17 03:30:55 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 20:30:55 -0700 Subject: [Intel-gfx] [PATCH v7 0/5] Remaining RKL patches Message-ID: <20200617033100.4044428-1-matthew.d.roper@intel.com> Changes since v6: - Renumber TGL's TBT PLL so that the same TGL PLL selector macros can be used seamlessly on all gen12 platforms. (Lucas) - Make the PHY initialization WA function static Matt Roper (5): drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout drm/i915/rkl: Add DPLL4 support drm/i915/rkl: Handle HTI drm/i915/rkl: Add initial workarounds drm/i915/rkl: Add Wa_14011224835 for PHY B initialization .../gpu/drm/i915/display/intel_combo_phy.c | 26 ++++++ drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++- drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 ++++++++++- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 15 ++-- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++++++++++++------- drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 40 ++++++--- 9 files changed, 224 insertions(+), 66 deletions(-) -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 17 03:30:56 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 20:30:56 -0700 Subject: [Intel-gfx] [PATCH v7 1/5] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout In-Reply-To: <20200617033100.4044428-1-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> Message-ID: <20200617033100.4044428-2-matthew.d.roper@intel.com> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. v2: - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 - Checkpatch style fixes Bspec: 50287 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..8790f221dc77 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, enum phy phy) { - if (intel_phy_is_combo(dev_priv, phy)) { + if (IS_ROCKETLAKE(dev_priv)) { + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + } else if (intel_phy_is_combo(dev_priv, phy)) { return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } else if (intel_phy_is_tc(dev_priv, phy)) { enum tc_port tc_port = intel_port_to_tc(dev_priv, @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { + u32 mask, sel; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } + /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + val &= ~mask; + val |= sel; intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7457813ef273..6c2bb3354b86 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + u32 mask, shift; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } + + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; + id = temp >> shift; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..45bda5819abd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10195,12 +10195,18 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ (tc_port) + 12 : \ (tc_port) - PORT_TC4 + 21)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) /* CNL PLL */ #define DPLL0_ENABLE 0x46010 -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 17 03:30:57 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 20:30:57 -0700 Subject: [Intel-gfx] [PATCH v7 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200617033100.4044428-1-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> Message-ID: <20200617033100.4044428-3-matthew.d.roper@intel.com> Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were DPLL2. To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT. This means just renumbering TBT to be ID '3' rather than being another ID '2' like DPLL4. With this change, we can build our register selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register offsets are evenly-spaced. MGPLL's don't need any specific ID's (they're just used to translate back to a tc_port), so we let them float at the top of the enum. v2: - Add new .update_ref_clks() hook. v3: - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas) Bspec: 49202 Bspec: 49443 Bspec: 50288 Bspec: 50289 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++----- drivers/gpu/drm/i915/i915_reg.h | 15 +++------- 3 files changed, 37 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b45185b80bec..b5f4d4cef682 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, return false; } - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) + if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - else + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { + dpll_mask = + BIT(DPLL_ID_EHL_DPLL4) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else { dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); + } port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info rkl_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, + { }, +}; + +static const struct intel_dpll_mgr rkl_pll_mgr = { + .dpll_info = rkl_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (INTEL_GEN(dev_priv) >= 12) + if (IS_ROCKETLAKE(dev_priv)) + dpll_mgr = &rkl_pll_mgr; + else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr; else if (IS_ELKHARTLAKE(dev_priv)) dpll_mgr = &ehl_pll_mgr; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 5d9a2bc371e7..49367847bfb5 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -125,35 +125,35 @@ enum intel_dpll_id { /** * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL */ - DPLL_ID_ICL_TBTPLL = 2, + DPLL_ID_ICL_TBTPLL = 3, /** * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), * TGL TC PLL 1 port 1 (TC1) */ - DPLL_ID_ICL_MGPLL1 = 3, + DPLL_ID_ICL_MGPLL1, /** * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) * TGL TC PLL 1 port 2 (TC2) */ - DPLL_ID_ICL_MGPLL2 = 4, + DPLL_ID_ICL_MGPLL2, /** * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) * TGL TC PLL 1 port 3 (TC3) */ - DPLL_ID_ICL_MGPLL3 = 5, + DPLL_ID_ICL_MGPLL3, /** * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) * TGL TC PLL 1 port 4 (TC4) */ - DPLL_ID_ICL_MGPLL4 = 6, + DPLL_ID_ICL_MGPLL4, /** * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) */ - DPLL_ID_TGL_MGPLL5 = 7, + DPLL_ID_TGL_MGPLL5, /** * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) */ - DPLL_ID_TGL_MGPLL6 = 8, + DPLL_ID_TGL_MGPLL6, }; #define I915_NUM_PLLS 9 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 45bda5819abd..34f8698ac3aa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) -#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) /* * Device info offset array based helpers for groups of registers with unevenly @@ -10427,19 +10426,13 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR0 0x164284 #define _TGL_DPLL1_CFGCR0 0x16428C -/* TODO: add DPLL4 */ -#define _TGL_TBTPLL_CFGCR0 0x16429C -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _TGL_TBTPLL_CFGCR0) +#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ + _TGL_DPLL1_CFGCR0) #define _TGL_DPLL0_CFGCR1 0x164288 #define _TGL_DPLL1_CFGCR1 0x164290 -/* TODO: add DPLL4 */ -#define _TGL_TBTPLL_CFGCR1 0x1642A0 -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _TGL_TBTPLL_CFGCR1) +#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ + _TGL_DPLL1_CFGCR1) #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000 -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 17 03:30:58 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 20:30:58 -0700 Subject: [Intel-gfx] [PATCH v7 3/5] drm/i915/rkl: Handle HTI In-Reply-To: <20200617033100.4044428-1-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> Message-ID: <20200617033100.4044428-4-matthew.d.roper@intel.com> If HTI (also sometimes called HDPORT) is enabled at startup, it may be using some of the PHYs and DPLLs making them unavailable for general usage. Let's read out the HDPORT_STATE register and avoid making use of resources that HTI is already using. v2: - Fix minor checkpatch warnings Bspec: 49189 Bspec: 53707 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++ 5 files changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6c2bb3354b86..f16512eddc58 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -46,6 +46,7 @@ #include "display/intel_ddi.h" #include "display/intel_dp.h" #include "display/intel_dp_mst.h" +#include "display/intel_dpll_mgr.h" #include "display/intel_dsi.h" #include "display/intel_dvo.h" #include "display/intel_gmbus.h" @@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } +static bool hti_uses_phy(u32 hdport_state, enum phy phy) +{ + return hdport_state & HDPORT_ENABLED && + (hdport_state & HDPORT_PHY_USED_DP(phy) || + hdport_state & HDPORT_PHY_USED_HDMI(phy)); +} + static void intel_setup_outputs(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; @@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_ROCKETLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + /* + * If HTI (aka HDPORT) is enabled at boot, it may have taken + * over some of the PHYs and made them unavailable to the + * driver. In that case we should skip initializing the + * corresponding outputs. + */ + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + + if (!hti_uses_phy(hdport_state, PHY_A)) + intel_ddi_init(dev_priv, PORT_A); + if (!hti_uses_phy(hdport_state, PHY_B)) + intel_ddi_init(dev_priv, PORT_B); + if (!hti_uses_phy(hdport_state, PHY_C)) + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + if (!hti_uses_phy(hdport_state, PHY_D)) + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); @@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) intel_dpll_readout_hw_state(dev_priv); + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); + for_each_intel_encoder(dev, encoder) { pipe = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b5f4d4cef682..6f59f9ec453b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) mutex_unlock(&dev_priv->dpll.lock); } +/* + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them + * unavailable for use. + */ +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) +{ + u32 hdport_state; + + if (!IS_ROCKETLAKE(dev_priv)) + return 0; + + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + if (!(hdport_state & HDPORT_ENABLED)) + return 0; + + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); +} + static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + /* Eliminate DPLLs from consideration if reserved by HTI */ + dpll_mask &= ~dev_priv->hti_pll_mask; + for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { pll = &dev_priv->dpll.shared_dplls[i]; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 49367847bfb5..edcc43f4670f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device *dev); void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..b836032fa0de 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1037,6 +1037,9 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ + u32 hti_pll_mask; + /* * edram size in MB. * Cannot be determined by PCIID. You must always read a register. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 34f8698ac3aa..34b2ec04ccd8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2908,6 +2908,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) +#define HDPORT_STATE _MMIO(0x45050) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) +#define HDPORT_ENABLED REG_BIT(0) + /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 17 03:30:59 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 20:30:59 -0700 Subject: [Intel-gfx] [PATCH v7 4/5] drm/i915/rkl: Add initial workarounds In-Reply-To: <20200617033100.4044428-1-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> Message-ID: <20200617033100.4044428-5-matthew.d.roper@intel.com> RKL and TGL share some general gen12 workarounds, but each platform also has its own platform-specific workarounds. v2: - Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to TGL's, so we'll have both functions call the tgl_ function for now; this workaround isn't listed for DG1 so we don't want to add it to the general gen12_ function. Cc: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++-------- 2 files changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3cd461bf9131..63ac79f88fa2 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0] */ - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) + /* Wa_14010477008:tgl[a0..c0],rkl[all] */ + if (IS_ROCKETLAKE(dev_priv) || + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..741710ca2b9a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) { /* * Wa_1409142259:tgl @@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1409207793:tgl * Wa_1409178076:tgl * Wa_1408979724:tgl + * Wa_14010443199:rkl + * Wa_14010698770:rkl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); + /* WaDisableGPGPUMidThreadPreemption:gen12 */ + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, + GEN9_PREEMPT_GPGPU_LEVEL_MASK, + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); +} + +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + /* - * Wa_1604555607:gen12 and Wa_1608008084:gen12 + * Wa_1604555607:tgl,rkl + * + * Note that the implementation of this workaround is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit * masks. So instead of doing a RMW we should just write the GS Timer @@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 0); - - /* WaDisableGPGPUMidThreadPreemption:tgl */ - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, - GEN9_PREEMPT_GPGPU_LEVEL_MASK, - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); } static void @@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_GEN(i915, 12)) + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 12)) + gen12_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 11)) icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) @@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen12_gt_workarounds_init(struct drm_i915_private *i915, + struct i915_wa_list *wal) { wa_init_mcr(i915, wal); +} + +static void +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) @@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 12)) + gen12_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 11)) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) @@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); - /* - * Wa_1607030317:tgl - * Wa_1607186500:tgl - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 - * of then says it is fixed on B0 the other one says it is - * permanent - */ - wa_masked_en(wal, - GEN6_RC_SLEEP_PSMI_CONTROL, - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE); - /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl */ + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); - /* Wa_1409804808:tgl */ + /* Wa_1409804808:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); - /* Wa_1606700617:tgl */ - wa_masked_en(wal, - GEN9_CS_DEBUG_MODE1, - FF_DOP_CLOCK_GATE_DISABLE); - /* * Wa_1409085225:tgl - * Wa_14010229206:tgl + * Wa_14010229206:tgl,rkl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); + + /* + * Wa_1607030317:tgl + * Wa_1607186500:tgl + * Wa_1607297627:tgl,rkl there are multiple entries for this + * WA in the BSpec; some indicate this is an A0-only WA, + * others indicate it applies to all steppings. + */ + wa_masked_en(wal, + GEN6_RC_SLEEP_PSMI_CONTROL, + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + } + + if (IS_TIGERLAKE(i915)) { + /* Wa_1606700617:tgl */ + wa_masked_en(wal, + GEN9_CS_DEBUG_MODE1, + FF_DOP_CLOCK_GATE_DISABLE); } if (IS_GEN(i915, 11)) { -- 2.24.1 From matthew.d.roper at intel.com Wed Jun 17 03:31:00 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Tue, 16 Jun 2020 20:31:00 -0700 Subject: [Intel-gfx] [PATCH v7 5/5] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization In-Reply-To: <20200617033100.4044428-1-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> Message-ID: <20200617033100.4044428-6-matthew.d.roper@intel.com> After doing normal PHY-B initialization on Rocket Lake, we need to manually copy some additional PHY-A register values into PHY-B registers. Note that the bspec's combo phy page doesn't specify that this workaround is restricted to specific platform steppings (and doesn't even do a very good job of specifying that RKL is the only platform this is needed on), but the RKL workaround page lists this as relevant only for A and B steppings, so I'm trusting that information for now. v2: Make rkl_combo_phy_b_init_wa() static Bspec: 49291 Bspec: 53273 Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 26 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec62..d5d95e2746c2 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -338,6 +338,27 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); } +static void rkl_combo_phy_b_init_wa(struct drm_i915_private *i915) +{ + u32 grccode, grccode_ldo; + u32 iref_rcal_ord, rcompcode_ld_cap_ov; + + intel_de_wait_for_register(i915, ICL_PORT_COMP_DW3(PHY_A), + FIRST_COMP_DONE, FIRST_COMP_DONE, 100); + + grccode = REG_FIELD_GET(GRCCODE, + intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A))); + iref_rcal_ord = REG_FIELD_PREP(IREF_RCAL_ORD, grccode); + intel_de_rmw(i915, ICL_PORT_COMP_DW2(PHY_B), IREF_RCAL_ORD, + iref_rcal_ord | IREF_RCAL_ORD_EN); + + grccode_ldo = REG_FIELD_GET(GRCCODE_LDO, + intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A))); + rcompcode_ld_cap_ov = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode_ldo); + intel_de_rmw(i915, ICL_PORT_COMP_DW6(PHY_B), RCOMPCODE_LD_CAP_OV, + rcompcode_ld_cap_ov | RCOMPCODEOVEN_LDO_SYNC); +} + static void icl_combo_phys_init(struct drm_i915_private *dev_priv) { enum phy phy; @@ -390,6 +411,11 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); + + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && + phy == PHY_B) + /* Wa_14011224835:rkl[a0..c0] */ + rkl_combo_phy_b_init_wa(dev_priv); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 34b2ec04ccd8..10f6e46523b6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1908,11 +1908,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CNL_PORT_COMP_DW0 _MMIO(0x162100) #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) -#define COMP_INIT (1 << 31) +#define COMP_INIT REG_BIT(31) +#define GRCCODE_LDO REG_GENMASK(7, 0) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) +#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy)) +#define IREF_RCAL_ORD_EN REG_BIT(7) +#define IREF_RCAL_ORD REG_GENMASK(6, 0) + #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) @@ -1925,6 +1930,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VOLTAGE_INFO_1_05V (2 << 24) #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 +#define FIRST_COMP_DONE REG_BIT(22) + +#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy)) +#define GRCCODE REG_GENMASK(30, 24) +#define RCOMPCODEOVEN_LDO_SYNC REG_BIT(23) +#define RCOMPCODE_LD_CAP_OV REG_GENMASK(22, 16) #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24) -- 2.24.1 From patchwork at emeril.freedesktop.org Wed Jun 17 04:30:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 04:30:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev6=29?= In-Reply-To: <20200617033100.4044428-1-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> Message-ID: <159236824262.29980.1388826083041848599@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev6) URL : https://patchwork.freedesktop.org/series/77971/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8638 -> Patchwork_17975 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17975 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17975, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17975/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17975: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - fi-tgl-u2: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17975/fi-tgl-u2/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at runner@aborted: - {fi-tgl-dsi}: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17975/fi-tgl-dsi/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17975 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1242]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17975/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 Participating hosts (47 -> 10) ------------------------------ ERROR: It appears as if the changes made in Patchwork_17975 prevented too many machines from booting. Missing (37): fi-icl-u2 fi-skl-lmem fi-blb-e6850 fi-byt-n2820 fi-skl-6600u fi-snb-2600 fi-cml-u2 fi-bxt-dsi fi-bdw-5557u fi-cml-s fi-bsw-n3050 fi-byt-j1900 fi-glk-dsi fi-bwr-2160 fi-ilk-650 fi-kbl-7500u fi-hsw-4770 fi-gdg-551 fi-ivb-3770 fi-elk-e7500 fi-bsw-nick fi-skl-6700k2 fi-kbl-r fi-ilk-m540 fi-ehl-1 fi-skl-guc fi-cfl-8700k fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-whl-u fi-kbl-x1275 fi-cfl-8109u fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8638 -> Patchwork_17975 CI-20190529: 20190529 CI_DRM_8638: 83818e4910cac8b84d8f915c773ab3f55fa30365 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17975: a03fa5993eeac9c31bbf8ab3b6c79ac7f4b6e4d7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a03fa5993eea drm/i915/rkl: Add Wa_14011224835 for PHY B initialization 0b4911dd9a47 drm/i915/rkl: Add initial workarounds 1f13cd3654fb drm/i915/rkl: Handle HTI c8d0aab47fb8 drm/i915/rkl: Add DPLL4 support bf41347d51b5 drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17975/index.html From zhenyuw at linux.intel.com Wed Jun 17 04:34:18 2020 From: zhenyuw at linux.intel.com (Zhenyu Wang) Date: Wed, 17 Jun 2020 12:34:18 +0800 Subject: [Intel-gfx] [PULL] gvt-fixes Message-ID: <20200617043418.GQ5687@zhen-hp.sh.intel.com> Hi, This contains misc fixes for gvt. Two MMIO handler fixes on SKL/CFL, one mask register bit checking fix exposed in suspend/resume path and one lockdep error fix for debugfs entry access. Thanks. -- The following changes since commit 8e68c6340d5833077b3753eabedab40755571383: drm/i915/display: Fix the encoder type check (2020-06-16 11:34:24 +0300) are available in the Git repository at: https://github.com/intel/gvt-linux tags/gvt-fixes-2020-06-17 for you to fetch changes up to a291e4fba259a56a6a274c1989997acb6f0bb03a: drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context (2020-06-17 12:36:19 +0800) ---------------------------------------------------------------- gvt-fixes-2020-06-17 - Two missed MMIO handler fixes for SKL/CFL (Colin) - Fix mask register bits check (Colin) - Fix one lockdep error for debugfs entry access (Colin) ---------------------------------------------------------------- Colin Xu (4): drm/i915/gvt: Add one missing MMIO handler for D_SKL_PLUS drm/i915/gvt: Fix two CFL MMIO handling caused by regression. drm/i915/gvt: Fix incorrect check of enabled bits in mask registers drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context drivers/gpu/drm/i915/gvt/debugfs.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 24 +++++++++++++----------- drivers/gpu/drm/i915/gvt/mmio_context.h | 6 +++--- drivers/gpu/drm/i915/gvt/reg.h | 5 +++++ 4 files changed, 22 insertions(+), 15 deletions(-) -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 195 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200617/4be079cb/attachment-0001.sig> From patchwork at emeril.freedesktop.org Wed Jun 17 05:07:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 05:07:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Check_preemption_rollback_of_different_ring_?= =?utf-8?q?queue_depths_=28rev2=29?= In-Reply-To: <20200616233733.18050-1-chris@chris-wilson.co.uk> References: <20200616233733.18050-1-chris@chris-wilson.co.uk> Message-ID: <159237045566.29979.13133236687333842422@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Check preemption rollback of different ring queue depths (rev2) URL : https://patchwork.freedesktop.org/series/78411/ State : success == Summary == CI Bug Log - changes from CI_DRM_8637_full -> Patchwork_17972_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17972_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-kbl1/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-snb6/igt at gem_exec_schedule@implicit-read-write at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-snb1/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_whisper@basic-queues-priority: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-glk5/igt at gem_exec_whisper@basic-queues-priority.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-glk7/igt at gem_exec_whisper@basic-queues-priority.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_fence_pin_leak: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-kbl6/igt at kms_fence_pin_leak.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-kbl7/igt at kms_fence_pin_leak.html * igt at kms_flip@flip-vs-suspend-interruptible at b-edp1: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#198]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl4/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl1/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][13] -> [DMESG-FAIL][14] ([i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-iclb1/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-iclb7/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_psr@suspend: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +10 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl4/igt at kms_psr@suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl10/igt at kms_psr@suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#1542]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-iclb3/igt at perf@blocking-parameterized.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-iclb3/igt at perf@blocking-parameterized.html * igt at syncobj_basic@illegal-fd-to-handle: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#95]) +32 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-apl8/igt at syncobj_basic@illegal-fd-to-handle.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-apl1/igt at syncobj_basic@illegal-fd-to-handle.html * igt at template@a: - shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#402]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-tglb8/igt at template@a.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-tglb3/igt at template@a.html #### Possible fixes #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][31] ([i915#1930]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-glk1/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_partial_pwrite_pread@writes-after-reads-uncached: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-glk2/igt at gem_partial_pwrite_pread@writes-after-reads-uncached.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-glk8/igt at gem_partial_pwrite_pread@writes-after-reads-uncached.html * igt at kms_addfb_basic@framebuffer-vs-set-tiling: - shard-apl: [DMESG-WARN][35] ([i915#95]) -> [PASS][36] +22 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-apl4/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-apl2/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html * igt at kms_color@pipe-c-ctm-0-5: - shard-skl: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +4 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl10/igt at kms_color@pipe-c-ctm-0-5.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl1/igt at kms_color@pipe-c-ctm-0-5.html * igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-glk: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-glk8/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-glk2/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +7 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-kbl1/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-kbl3/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt: - shard-iclb: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-iclb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][47] ([i915#1188]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][49] ([fdo#108145] / [i915#265]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-iclb5/igt at kms_psr@psr2_primary_page_flip.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [INCOMPLETE][53] ([i915#155]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-kbl6/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-kbl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at perf_pmu@module-unload: - shard-hsw: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-hsw6/igt at perf_pmu@module-unload.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-hsw4/igt at perf_pmu@module-unload.html * igt at sysfs_timeslice_duration@timeout at vecs0: - shard-skl: [FAIL][57] ([i915#1732]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl2/igt at sysfs_timeslice_duration@timeout at vecs0.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl4/igt at sysfs_timeslice_duration@timeout at vecs0.html #### Warnings #### * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][59] ([i915#1319] / [i915#1958]) -> [TIMEOUT][60] ([i915#1319]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-kbl2/igt at kms_content_protection@lic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-kbl6/igt at kms_content_protection@lic.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding: - shard-kbl: [DMESG-WARN][61] ([i915#93] / [i915#95]) -> [DMESG-FAIL][62] ([i915#54] / [i915#95]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-sliding.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][63] ([fdo#109349]) -> [DMESG-WARN][64] ([i915#1226]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-iclb8/igt at kms_dp_dsc@basic-dsc-enable-edp.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][65] ([i915#1525]) -> [DMESG-FAIL][66] ([i915#95]) +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-apl2/igt at kms_fbcon_fbt@fbc-suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-apl1/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][68] ([fdo#108145] / [i915#1982]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8637/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1732]: https://gitlab.freedesktop.org/drm/intel/issues/1732 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (10 -> 11) ------------------------------ Additional (1): pig-glk-j5005 Build changes ------------- * Linux: CI_DRM_8637 -> Patchwork_17972 CI-20190529: 20190529 CI_DRM_8637: 091db6eff650d91a12485725f764bc60909344fb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17972: c94fe0724411deaec7f7d5c29975200cbaa2cb9f @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17972/index.html From shaofeng.tang at intel.com Wed Jun 17 05:51:49 2020 From: shaofeng.tang at intel.com (Shaofeng Tang) Date: Wed, 17 Jun 2020 13:51:49 +0800 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <otc-external> References: <otc-external> Message-ID: <20200617055149.16411-1-shaofeng.tang@intel.com> [Why] Query if vgpu is active, it is useful to the user. Currently, only the primary plane is usable when vgpu is active. The value of vgpu active is useful for user to determine how many planes can be used. also useful for user to determine different behaviors according to vgpu is active or not. [How] Add a switch-case in the IOCTL 'i915_getparam_ioctl' to return 'intel_vgpu_active' Signed-off-by: Shaofeng Tang <shaofeng.tang at intel.com> --- drivers/gpu/drm/i915/i915_getparam.c | 3 +++ include/uapi/drm/i915_drm.h | 6 ++++++ tools/include/uapi/drm/i915_drm.h | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index d042644..c50555b 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -161,6 +161,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, case I915_PARAM_PERF_REVISION: value = i915_perf_ioctl_version(); break; + case I915_PARAM_IS_GVT: + value = intel_vgpu_active(i915); + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 14b67cd..74f06e2 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h index 2813e57..ecaad82 100644 --- a/tools/include/uapi/drm/i915_drm.h +++ b/tools/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { -- 2.9.2 base-commit: 999bc17a2471df17a3af3001d094cf6d5d4849b0 From patchwork at emeril.freedesktop.org Wed Jun 17 06:01:16 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 06:01:16 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBk?= =?utf-8?q?rm/i915/gvt=3A_query_if_vgpu_is_active_via_GETPARAM_IOCTL_=28re?= =?utf-8?b?djIp?= In-Reply-To: <otc-external> References: <otc-external> Message-ID: <159237367626.29977.5878071509647713836@emeril.freedesktop.org> == Series Details == Series: drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL (rev2) URL : https://patchwork.freedesktop.org/series/78409/ State : failure == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/i915_getparam.o drivers/gpu/drm/i915/i915_getparam.c: In function ?i915_getparam_ioctl?: drivers/gpu/drm/i915/i915_getparam.c:165:11: error: implicit declaration of function ?intel_vgpu_active?; did you mean ?intel_vtd_active?? [-Werror=implicit-function-declaration] value = intel_vgpu_active(i915); ^~~~~~~~~~~~~~~~~ intel_vtd_active cc1: all warnings being treated as errors scripts/Makefile.build:280: recipe for target 'drivers/gpu/drm/i915/i915_getparam.o' failed make[4]: *** [drivers/gpu/drm/i915/i915_getparam.o] Error 1 scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:497: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1764: recipe for target 'drivers' failed make: *** [drivers] Error 2 From tzimmermann at suse.de Wed Jun 17 06:33:24 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Wed, 17 Jun 2020 08:33:24 +0200 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree In-Reply-To: <20200617105929.534edd34@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> Message-ID: <c82b9c52-d4e6-9eef-e37d-0a26ee9f1183@suse.de> Hi Am 17.06.20 um 02:59 schrieb Stephen Rothwell: > Hi all, > > After merging the drm-misc tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c: In function 'amdgpu_amdkfd_gpuvm_free_memory_of_gpu': > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1357:2: error: implicit declaration of function 'drm_gem_object_put_unlocked'; did you mean 'drm_gem_object_put_locked'? [-Werror=implicit-function-declaration] > 1357 | drm_gem_object_put_unlocked(&mem->bo->tbo.base); > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ > | drm_gem_object_put_locked > > Caused by commit > > ab15d56e27be ("drm: remove transient drm_gem_object_put_unlocked()") > > interacting with commit > > fd9a9f8801de ("drm/amdgpu: Use GEM obj reference for KFD BOs") > > from Linus' tree. > > I have applied the following merge fix up patch for today. > > From: Stephen Rothwell <sfr at canb.auug.org.au> > Date: Wed, 17 Jun 2020 10:55:32 +1000 > Subject: [PATCH] drm/amdgpu: remove stray drm_gem_object_put_unlocked > > Signed-off-by: Stephen Rothwell <sfr at canb.auug.org.au> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > index b91b5171270f..9015c7b76d60 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > @@ -1354,7 +1354,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( > } > > /* Free the BO*/ > - drm_gem_object_put_unlocked(&mem->bo->tbo.base); > + drm_gem_object_put(&mem->bo->tbo.base); We recently dropped the _unlock() suffix from drm_gem_object_put(). This patch should be ok. Best regards Thomas > mutex_destroy(&mem->lock); > kfree(mem); > > > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N?rnberg, Germany (HRB 36809, AG N?rnberg) Gesch?ftsf?hrer: Felix Imend?rffer -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200617/85d0b17e/attachment-0001.sig> From patchwork at emeril.freedesktop.org Wed Jun 17 06:44:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 06:44:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgbGlu?= =?utf-8?q?ux-next=3A_build_failure_after_merge_of_the_drm-misc_tree?= In-Reply-To: <20200617105929.534edd34@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> Message-ID: <159237626226.29979.3277218756983964974@emeril.freedesktop.org> == Series Details == Series: linux-next: build failure after merge of the drm-misc tree URL : https://patchwork.freedesktop.org/series/78444/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8638_full -> Patchwork_17974_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17974_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17974_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17974_full: ### IGT changes ### #### Possible regressions #### * igt at kms_flip@basic-plain-flip at c-hdmi-a1: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-hsw6/igt at kms_flip@basic-plain-flip at c-hdmi-a1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-hsw2/igt at kms_flip@basic-plain-flip at c-hdmi-a1.html Known issues ------------ Here are the changes found in Patchwork_17974_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at bcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * igt at gem_ctx_persistence@engines-mixed-process at rcs0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#1528]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl3/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl6/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#1528]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl5/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl5/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [PASS][9] -> [INCOMPLETE][10] ([i915#82]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-glk2/igt at gem_exec_whisper@basic-contexts-priority-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-glk2/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_userptr_blits@userfault: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl2/igt at gem_userptr_blits@userfault.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl7/igt at gem_userptr_blits@userfault.html * igt at i915_suspend@forcewake: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#636] / [i915#69]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl7/igt at i915_suspend@forcewake.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl5/igt at i915_suspend@forcewake.html * igt at kms_ccs@pipe-b-missing-ccs-buffer: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#165]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl3/igt at kms_ccs@pipe-b-missing-ccs-buffer.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl2/igt at kms_ccs@pipe-b-missing-ccs-buffer.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl4/igt at kms_flip_tiling@flip-changes-tiling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl6/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][21] -> [DMESG-FAIL][22] ([i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl6/igt at kms_flip_tiling@flip-changes-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-glk6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-glk9/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_cursor@pipe-b-overlay-size-256: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#95]) +22 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl8/igt at kms_plane_cursor@pipe-b-overlay-size-256.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl4/igt at kms_plane_cursor@pipe-b-overlay-size-256.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb3/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-b-wait-busy-hang: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl1/igt at kms_vblank@pipe-b-wait-busy-hang.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl1/igt at kms_vblank@pipe-b-wait-busy-hang.html * igt at perf_pmu@module-unload: - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb6/igt at perf_pmu@module-unload.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb5/igt at perf_pmu@module-unload.html #### Possible fixes #### * igt at core_getstats: - shard-kbl: [DMESG-WARN][35] ([i915#93] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl2/igt at core_getstats.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl7/igt at core_getstats.html * igt at gem_ctx_persistence@engines-hostile at vcs0: - shard-tglb: [FAIL][37] ([i915#1622]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-tglb1/igt at gem_ctx_persistence@engines-hostile at vcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-tglb3/igt at gem_ctx_persistence@engines-hostile at vcs0.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][39] ([i915#82]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-snb5/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_mmap@basic: - shard-iclb: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb3/igt at gem_mmap@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb1/igt at gem_mmap@basic.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +13 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl1/igt at gem_mmap_wc@write-cpu-read-wc.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl2/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at gem_shrink@reclaim: - shard-hsw: [SKIP][45] ([fdo#109271]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-hsw1/igt at gem_shrink@reclaim.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-hsw4/igt at gem_shrink@reclaim.html * igt at i915_query@query-topology-kernel-writes: - shard-apl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl4/igt at i915_query@query-topology-kernel-writes.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl7/igt at i915_query@query-topology-kernel-writes.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-tglb: [DMESG-WARN][49] ([i915#402]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-tglb5/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-tglb3/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [FAIL][51] ([i915#46]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl7/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-tglb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb7/igt at kms_psr@psr2_cursor_blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html * igt at kms_psr@suspend: - shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +6 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl6/igt at kms_psr@suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl8/igt at kms_psr@suspend.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [INCOMPLETE][61] ([i915#69]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl8/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl9/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +3 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html #### Warnings #### * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][65] ([i915#1319]) -> [TIMEOUT][66] ([i915#1319] / [i915#1958]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl1/igt at kms_content_protection@lic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl6/igt at kms_content_protection@lic.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][67] ([i915#1525]) -> [DMESG-FAIL][68] ([i915#95]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl2/igt at kms_fbcon_fbt@fbc-suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl6/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [FAIL][69] ([i915#79]) -> [DMESG-WARN][70] ([i915#1982]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-suspend at a-edp1: - shard-skl: [DMESG-WARN][71] ([i915#1982]) -> [INCOMPLETE][72] ([i915#198]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl9/igt at kms_flip@flip-vs-suspend at a-edp1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl2/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1622]: https://gitlab.freedesktop.org/drm/intel/issues/1622 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8638 -> Patchwork_17974 CI-20190529: 20190529 CI_DRM_8638: 83818e4910cac8b84d8f915c773ab3f55fa30365 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17974: 5bf216c35bb20d8eed4b272e9d273906b8a2e514 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/index.html From daniel at ffwll.ch Wed Jun 17 06:48:50 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 17 Jun 2020 08:48:50 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200616120719.GL20149@phenom.ffwll.local> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> Message-ID: <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> On Tue, Jun 16, 2020 at 2:07 PM Daniel Vetter <daniel at ffwll.ch> wrote: > > Hi Jason, > > Somehow this got stuck somewhere in the mail queues, only popped up just > now ... > > On Thu, Jun 11, 2020 at 11:15:15AM -0300, Jason Gunthorpe wrote: > > On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: > > > > I still have my doubts about allowing fence waiting from within shrinkers. > > > > IMO ideally they should use a trywait approach, in order to allow memory > > > > allocation during command submission for drivers that > > > > publish fences before command submission. (Since early reservation object > > > > release requires that). > > > > > > Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up > > > with a mempool to make sure it can handle it's allocations. > > > > > > > But since drivers are already waiting from within shrinkers and I take your > > > > word for HMM requiring this, > > > > > > Yeah the big trouble is HMM and mmu notifiers. That's the really awkward > > > one, the shrinker one is a lot less established. > > > > I really question if HW that needs something like DMA fence should > > even be using mmu notifiers - the best use is HW that can fence the > > DMA directly without having to get involved with some command stream > > processing. > > > > Or at the very least it should not be a generic DMA fence but a > > narrowed completion tied only into the same GPU driver's command > > completion processing which should be able to progress without > > blocking. > > The problem with gpus is that these completions leak across the board like > mad. Both internally within memory managers (made a lot worse with p2p > direct access to vram), and through uapi. > > Many gpus still have a very hard time preempting, so doing an overall > switch in drivers/gpu to a memory management model where that is required > is not a very realistic option. And minimally you need either preempt > (still takes a while, but a lot faster generally than waiting for work to > complete) or hw faults (just a bunch of tlb flushes plus virtual indexed > caches, so just the caveat of that for a gpu, which has lots and big tlbs > and caches). So preventing the completion leaks within the kernel is I > think unrealistic, except if we just say "well sorry, run on windows, > mkay" for many gpu workloads. Or more realistic "well sorry, run on the > nvidia blob with nvidia hw". > > The userspace side we can somewhat isolate, at least for pure compute > workloads. But the thing is drivers/gpu is a continum from tiny socs > (where dma_fence is a very nice model) to huge compute stuff (where it's > maybe not the nicest, but hey hw sucks so still neeeded). Doing full on > break in uapi somewhere in there is at least a bit awkward, e.g. some of > the media codec code on intel runs all the way from the smallest intel soc > to the big transcode servers. > > So the current status quo is "total mess, every driver defines their own > rules". All I'm trying to do is some common rules here, do make this mess > slightly more manageable and overall reviewable and testable. > > I have no illusions that this is fundamentally pretty horrible, and the > leftover wiggle room for writing memory manager is barely more than a > hairline. Just not seeing how other options are better. So bad news is that gpu's are horrible, but I think if you don't have to review gpu drivers it's substantially better. If you do have hw with full device page fault support, then there's no need to ever install a dma_fence. Punching out device ptes and flushing caches is all that's needed. That is also the plan we have, for the workloads and devices where that's possible. Now my understanding for rdma is that if you don't have hw page fault support, then the only other object is to more or less permanently pin the memory. So again, dma_fence are completely useless, since it's entirely up to userspace when a given piece of registered memory isn't needed anymore, and the entire problem boils down to how much do we allow random userspace to just pin (system or device) memory. Or at least I don't really see any other solution. On the other end we have simpler devices like video input/output. Those always need pinned memory, but through hw design it's limited in how much you can pin (generally max resolution times a limited set of buffers to cycle through). Just including that memory pinning allowance as part of device access makes sense. It's only gpus (I think) which are in this awkward in-between spot where dynamic memory management really is much wanted, but the hw kinda sucks. Aside, about 10+ years ago we had a similar problem with gpu hw, but for security: Many gpu didn't have any kinds of page tables to isolate different clients from each another. drivers/gpu fixed this by parsing&validating what userspace submitted to make sure it's only every accessing its own buffers. Most gpus have become reasonable nowadays and do have proper per-process pagetables (gpu process, not the pasid stuff), but even today there's still some of the old model left in some of the smallest SoC. tldr; of all this: gpus kinda suck sometimes, but that's also not news :-/ Cheers, Daniel > > The intent of notifiers was never to endlessly block while vast > > amounts of SW does work. > > > > Going around and switching everything in a GPU to GFP_ATOMIC seems > > like bad idea. > > It's not everyone, or at least not everywhere, it's some fairly limited > cases. Also, even if we drop the mmu_notifier on the floor, then we're > stuck with shrinkers and GFP_NOFS. Still need a mempool of some sorts to > guarantee you get out of a bind, so not much better. > > At least that's my current understanding of where we are across all > drivers. > > > > I've pinged a bunch of armsoc gpu driver people and ask them how much this > > > hurts, so that we have a clear answer. On x86 I don't think we have much > > > of a choice on this, with userptr in amd and i915 and hmm work in nouveau > > > (but nouveau I think doesn't use dma_fence in there). > > > > Right, nor will RDMA ODP. > > Hm, what's the context here? I thought RDMA side you really don't want > dma_fence in mmu_notifiers, so not clear to me what you're agreeing on > here. > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From dyoung at redhat.com Wed Jun 17 06:53:15 2020 From: dyoung at redhat.com (Dave Young) Date: Wed, 17 Jun 2020 14:53:15 +0800 Subject: [Intel-gfx] i915/kexec: warning at drivers/gpu/drm/i915/display/intel_psr.c:782 intel_psr_activate+0x3c6/0x440 Message-ID: <20200617065315.GA6501@dhcp-128-65.nay.redhat.com> Hi, This warning exists for long time, I did not find time to report, here is the latest kernel logs, can you please to have a look? hardware: Thinkpad T480s lspci: 00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 07) -- [ 0.000000] Linux version 5.8.0-rc1+ (dyoung at dhcp-128-65.nay.redhat.com) (gcc (GCC) 10.0.1 20200328 (Red Hat 10.0.1-0.11), GNU ld version 2.34-2.fc32) #179 SMP Wed Jun 17 14:12:27 CST 2020 [ 0.000000] Command line: ramoops.mem_address=0x20000000 ramoops.mem_size=0x400000 hung_task_panic=1 softlockup_panic=1 panic=6 root=/dev/nvme0n1p9 ro rd.lvm.lv=rhel/swap LANG=zh_CN.UTF-8 audit=0 selinux=0 no_console_suspend crashkernel=160M printk.devkmsg=off usbcore.autosuspend=-1 [ 0.000000] KERNEL supported cpus: [ 0.000000] Intel GenuineIntel [ 0.000000] AMD AuthenticAMD [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' [ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 [ 0.000000] x86/fpu: xstate_offset[3]: 832, xstate_sizes[3]: 64 [ 0.000000] x86/fpu: xstate_offset[4]: 896, xstate_sizes[4]: 64 [ 0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format. [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable [ 0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009cfff] usable [ 0.000000] BIOS-e820: [mem 0x000000000009d000-0x00000000000fffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000003fffffff] usable [ 0.000000] BIOS-e820: [mem 0x0000000040000000-0x00000000403fffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000040400000-0x000000007b4b2fff] usable [ 0.000000] BIOS-e820: [mem 0x000000007b4b3000-0x000000007b4b4fff] reserved [ 0.000000] BIOS-e820: [mem 0x000000007b4b5000-0x000000007b51cfff] usable [ 0.000000] BIOS-e820: [mem 0x000000007b51d000-0x000000007b51dfff] reserved [ 0.000000] BIOS-e820: [mem 0x000000007b51e000-0x00000000ad334fff] usable [ 0.000000] BIOS-e820: [mem 0x00000000ad335000-0x00000000ad335fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000ad336000-0x00000000ad336fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000ad337000-0x00000000ba3e9fff] usable [ 0.000000] BIOS-e820: [mem 0x00000000ba3ea000-0x00000000bb535fff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000bb536000-0x00000000bb599fff] ACPI NVS [ 0.000000] BIOS-e820: [mem 0x00000000bb59a000-0x00000000bb5fefff] ACPI data [ 0.000000] BIOS-e820: [mem 0x00000000bb5ff000-0x00000000bb5fffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000bb600000-0x00000000bf7fffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fe010000-0x00000000fe010fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000043e7fffff] usable [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] e820: update [mem 0x00050270-0x000502df] usable ==> usable [ 0.000000] extended physical RAM map: [ 0.000000] reserve setup_data: [mem 0x0000000000000000-0x000000000005026f] usable [ 0.000000] reserve setup_data: [mem 0x0000000000050270-0x00000000000502df] usable [ 0.000000] reserve setup_data: [mem 0x00000000000502e0-0x0000000000057fff] usable [ 0.000000] reserve setup_data: [mem 0x0000000000058000-0x0000000000058fff] reserved [ 0.000000] reserve setup_data: [mem 0x0000000000059000-0x000000000009cfff] usable [ 0.000000] reserve setup_data: [mem 0x000000000009d000-0x00000000000fffff] reserved [ 0.000000] reserve setup_data: [mem 0x0000000000100000-0x000000003fffffff] usable [ 0.000000] reserve setup_data: [mem 0x0000000040000000-0x00000000403fffff] reserved [ 0.000000] reserve setup_data: [mem 0x0000000040400000-0x000000007b4b2fff] usable [ 0.000000] reserve setup_data: [mem 0x000000007b4b3000-0x000000007b4b4fff] reserved [ 0.000000] reserve setup_data: [mem 0x000000007b4b5000-0x000000007b51cfff] usable [ 0.000000] reserve setup_data: [mem 0x000000007b51d000-0x000000007b51dfff] reserved [ 0.000000] reserve setup_data: [mem 0x000000007b51e000-0x00000000ad334fff] usable [ 0.000000] reserve setup_data: [mem 0x00000000ad335000-0x00000000ad335fff] ACPI NVS [ 0.000000] reserve setup_data: [mem 0x00000000ad336000-0x00000000ad336fff] reserved [ 0.000000] reserve setup_data: [mem 0x00000000ad337000-0x00000000ba3e9fff] usable [ 0.000000] reserve setup_data: [mem 0x00000000ba3ea000-0x00000000bb535fff] reserved [ 0.000000] reserve setup_data: [mem 0x00000000bb536000-0x00000000bb599fff] ACPI NVS [ 0.000000] reserve setup_data: [mem 0x00000000bb59a000-0x00000000bb5fefff] ACPI data [ 0.000000] reserve setup_data: [mem 0x00000000bb5ff000-0x00000000bb5fffff] usable [ 0.000000] reserve setup_data: [mem 0x00000000bb600000-0x00000000bf7fffff] reserved [ 0.000000] reserve setup_data: [mem 0x00000000f8000000-0x00000000fbffffff] reserved [ 0.000000] reserve setup_data: [mem 0x00000000fe010000-0x00000000fe010fff] reserved [ 0.000000] reserve setup_data: [mem 0x0000000100000000-0x000000043e7fffff] usable [ 0.000000] efi: EFI v2.50 by Lenovo [ 0.000000] efi: SMBIOS=0xba674000 SMBIOS 3.0=0xba671000 ACPI=0xbb5fe000 ACPI 2.0=0xbb5fe014 ESRT=0xba4ec000 MEMATTR=0xb520e018 RNG=0xba675998 [ 0.000000] efi: seeding entropy pool [ 0.000000] SMBIOS 3.0.0 present. [ 0.000000] DMI: LENOVO 20L8S3M801/20L8S3M801, BIOS N22ET54W (1.31 ) 04/22/2019 [ 0.000000] tsc: Detected 2100.000 MHz processor [ 0.001190] tsc: Detected 2099.944 MHz TSC [ 0.001190] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.001192] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.001196] last_pfn = 0x43e800 max_arch_pfn = 0x400000000 [ 0.001197] x86/PAT: Configuration [0-7]: WB WT UC- UC WB WT UC- UC [ 0.001197] last_pfn = 0xbb600 max_arch_pfn = 0x400000000 [ 0.001202] esrt: Reserving ESRT space from 0x00000000ba4ec000 to 0x00000000ba4ec088. [ 0.001204] kexec: Reserving the low 1M of memory for crashkernel [ 0.001206] Using GB pages for direct mapping [ 0.001704] Secure boot disabled [ 0.001709] ACPI: Early table checksum verification disabled [ 0.001711] ACPI: RSDP 0x00000000BB5FE014 000024 (v02 LENOVO) [ 0.001713] ACPI: XSDT 0x00000000BB5AD188 00010C (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001716] ACPI: FACP 0x00000000BB5E3000 0000F4 (v05 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001719] ACPI: DSDT 0x00000000BB5BD000 021E4F (v02 LENOVO SKL 00000000 INTL 20160527) [ 0.001721] ACPI: FACS 0x00000000BB546000 000040 [ 0.001722] ACPI: SSDT 0x00000000BB5E9000 01320E (v02 LENOVO DptfTabl 00001000 INTL 20160527) [ 0.001724] ACPI: UEFI 0x00000000BB55C000 000042 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001725] ACPI: SSDT 0x00000000BB5E5000 0030B0 (v02 LENOVO SaSsdt 00003000 INTL 20160527) [ 0.001727] ACPI: SSDT 0x00000000BB5E4000 0005C6 (v02 LENOVO PerfTune 00001000 INTL 20160527) [ 0.001728] ACPI: HPET 0x00000000BB5E2000 000038 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001730] ACPI: APIC 0x00000000BB5E1000 00012C (v03 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001731] ACPI: MCFG 0x00000000BB5E0000 00003C (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001733] ACPI: ECDT 0x00000000BB5DF000 000053 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001734] ACPI: SSDT 0x00000000BB5BB000 001C9C (v02 LENOVO RVP7Rtd3 00001000 INTL 20160527) [ 0.001736] ACPI: SSDT 0x00000000BB5B9000 00163C (v02 LENOVO ProjSsdt 00000010 INTL 20160527) [ 0.001738] ACPI: BOOT 0x00000000BB5B8000 000028 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001739] ACPI: BATB 0x00000000BB5B7000 00004A (v02 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001741] ACPI: SSDT 0x00000000BB5B5000 0017AE (v02 LENOVO CpuSsdt 00003000 INTL 20160527) [ 0.001742] ACPI: SSDT 0x00000000BB5B4000 00056D (v02 LENOVO CtdpB 00001000 INTL 20160527) [ 0.001744] ACPI: SSDT 0x00000000BB5B3000 000678 (v02 LENOVO UsbCTabl 00001000 INTL 20160527) [ 0.001745] ACPI: LPIT 0x00000000BB5B2000 000094 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001747] ACPI: WSMT 0x00000000BB5B1000 000028 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001748] ACPI: SSDT 0x00000000BB5B0000 0001D8 (v02 LENOVO HdaDsp 00000000 INTL 20160527) [ 0.001750] ACPI: SSDT 0x00000000BB5AF000 0004FC (v02 LENOVO TbtTypeC 00000000 INTL 20160527) [ 0.001751] ACPI: SSDT 0x00000000BB5AE000 0002D1 (v02 LENOVO Wwan 00000001 INTL 20160527) [ 0.001753] ACPI: DBGP 0x00000000BB5FD000 000034 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001754] ACPI: DBG2 0x00000000BB5AC000 000054 (v00 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001756] ACPI: POAT 0x00000000BB5AB000 000055 (v03 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001757] ACPI: DMAR 0x00000000BB5AA000 0000A8 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001759] ACPI: ASF! 0x00000000BB5A9000 0000A0 (v32 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001760] ACPI: FPDT 0x00000000BB5A8000 000044 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001762] ACPI: BGRT 0x00000000BB5A7000 000038 (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001763] ACPI: UEFI 0x00000000BB543000 00013E (v01 LENOVO TP-N22 00001310 PTEC 00000002) [ 0.001768] ACPI: Local APIC address 0xfee00000 [ 0.001775] No NUMA configuration found [ 0.001775] Faking a node at [mem 0x0000000000000000-0x000000043e7fffff] [ 0.001778] NODE_DATA(0) allocated [mem 0x43e7fa000-0x43e7fbfff] [ 0.001781] Reserving 160MB of memory at 2608MB for crashkernel (System RAM: 16263MB) [ 0.001791] Zone ranges: [ 0.001792] DMA [mem 0x0000000000001000-0x0000000000ffffff] [ 0.001793] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] [ 0.001794] Normal [mem 0x0000000100000000-0x000000043e7fffff] [ 0.001794] Movable zone start for each node [ 0.001795] Early memory node ranges [ 0.001795] node 0: [mem 0x0000000000001000-0x0000000000057fff] [ 0.001796] node 0: [mem 0x0000000000059000-0x000000000009cfff] [ 0.001797] node 0: [mem 0x0000000000100000-0x000000003fffffff] [ 0.001797] node 0: [mem 0x0000000040400000-0x000000007b4b2fff] [ 0.001798] node 0: [mem 0x000000007b4b5000-0x000000007b51cfff] [ 0.001798] node 0: [mem 0x000000007b51e000-0x00000000ad334fff] [ 0.001799] node 0: [mem 0x00000000ad337000-0x00000000ba3e9fff] [ 0.001799] node 0: [mem 0x00000000bb5ff000-0x00000000bb5fffff] [ 0.001800] node 0: [mem 0x0000000100000000-0x000000043e7fffff] [ 0.001961] Zeroed struct page in unavailable ranges: 30847 pages [ 0.001962] Initmem setup node 0 [mem 0x0000000000001000-0x000000043e7fffff] [ 0.001964] On node 0 totalpages: 4163457 [ 0.001965] DMA zone: 64 pages used for memmap [ 0.001965] DMA zone: 155 pages reserved [ 0.001966] DMA zone: 3995 pages, LIFO batch:0 [ 0.001982] DMA32 zone: 11840 pages used for memmap [ 0.001983] DMA32 zone: 757734 pages, LIFO batch:63 [ 0.005402] Normal zone: 53152 pages used for memmap [ 0.005402] Normal zone: 3401728 pages, LIFO batch:63 [ 0.020786] Reserving Intel graphics memory at [mem 0xbd800000-0xbf7fffff] [ 0.020959] ACPI: PM-Timer IO Port: 0x1808 [ 0.020960] ACPI: Local APIC address 0xfee00000 [ 0.020964] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) [ 0.020965] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1]) [ 0.020965] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1]) [ 0.020966] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1]) [ 0.020966] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1]) [ 0.020966] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1]) [ 0.020967] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1]) [ 0.020967] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1]) [ 0.020968] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1]) [ 0.020968] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1]) [ 0.020969] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1]) [ 0.020969] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1]) [ 0.020969] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1]) [ 0.020970] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1]) [ 0.020970] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1]) [ 0.020971] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1]) [ 0.020997] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119 [ 0.020998] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.020999] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) [ 0.021000] ACPI: IRQ0 used by override. [ 0.021000] ACPI: IRQ9 used by override. [ 0.021001] Using ACPI (MADT) for SMP configuration information [ 0.021002] ACPI: HPET id: 0x8086a201 base: 0xfed00000 [ 0.021005] e820: update [mem 0xb07d0000-0xb0860fff] usable ==> reserved [ 0.021011] TSC deadline timer available [ 0.021011] smpboot: Allowing 8 CPUs, 0 hotplug CPUs [ 0.021023] [mem 0xbf800000-0xf7ffffff] available for PCI devices [ 0.021023] Booting paravirtualized kernel on bare hardware [ 0.021025] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns [ 0.023365] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1 [ 0.023470] percpu: Embedded 50 pages/cpu s167936 r8192 d28672 u262144 [ 0.023473] pcpu-alloc: s167936 r8192 d28672 u262144 alloc=1*2097152 [ 0.023474] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 [ 0.023484] Built 1 zonelists, mobility grouping on. Total pages: 4098246 [ 0.023485] Policy zone: Normal [ 0.023486] Kernel command line: ramoops.mem_address=0x20000000 ramoops.mem_size=0x400000 hung_task_panic=1 softlockup_panic=1 panic=6 root=/dev/nvme0n1p9 ro rd.lvm.lv=rhel/swap LANG=zh_CN.UTF-8 audit=0 selinux=0 no_console_suspend crashkernel=160M printk.devkmsg=off usbcore.autosuspend=-1 [ 0.023516] audit: disabled (until reboot) [ 0.024068] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear) [ 0.024322] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear) [ 0.024365] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.049642] Memory: 16109860K/16653828K available (10243K kernel code, 1030K rwdata, 2484K rodata, 1224K init, 2960K bss, 543968K reserved, 0K cma-reserved) [ 0.049673] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 [ 0.049679] Kernel/User page tables isolation: enabled [ 0.049688] ftrace: allocating 29741 entries in 117 pages [ 0.057842] ftrace: allocated 117 pages with 5 groups [ 0.057893] rcu: Hierarchical RCU implementation. [ 0.057894] Rude variant of Tasks RCU enabled. [ 0.057895] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies. [ 0.057971] NR_IRQS: 4352, nr_irqs: 2048, preallocated irqs: 16 [ 0.058112] rcu: Offload RCU callbacks from CPUs: (none). [ 0.058245] random: get_random_bytes called from start_kernel+0x5b1/0x772 with crng_init=0 [ 0.058260] Console: colour dummy device 80x25 [ 0.058409] printk: console [tty0] enabled [ 0.058418] ACPI: Core revision 20200528 [ 0.058701] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns [ 0.058769] APIC: Switch to symmetric I/O mode setup [ 0.060036] x2apic: IRQ remapping doesn't support X2APIC mode [ 0.064358] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.068800] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x1e44fb6c2ab, max_idle_ns: 440795206594 ns [ 0.068803] Calibrating delay loop (skipped), value calculated using timer frequency.. 4199.88 BogoMIPS (lpj=2099944) [ 0.068806] pid_max: default: 32768 minimum: 301 [ 0.068842] LSM: Security Framework initializing [ 0.068874] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear) [ 0.068900] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear) [ 0.069032] mce: CPU0: Thermal monitoring enabled (TM1) [ 0.069046] process: using mwait in idle threads [ 0.069048] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8 [ 0.069050] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4 [ 0.069051] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization [ 0.069053] Spectre V2 : Mitigation: Full generic retpoline [ 0.069054] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch [ 0.069055] Spectre V2 : Enabling Restricted Speculation for firmware calls [ 0.069057] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier [ 0.069058] Spectre V2 : User space: Mitigation: STIBP via seccomp and prctl [ 0.069060] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp [ 0.069062] TAA: Mitigation: Clear CPU buffers [ 0.069063] SRBDS: Vulnerable: No microcode [ 0.069063] MDS: Mitigation: Clear CPU buffers [ 0.069180] Freeing SMP alternatives memory: 28K [ 0.069223] smpboot: CPU0: Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz (family: 0x6, model: 0x8e, stepping: 0xa) [ 0.069278] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver. [ 0.069284] ... version: 4 [ 0.069285] ... bit width: 48 [ 0.069286] ... generic registers: 4 [ 0.069287] ... value mask: 0000ffffffffffff [ 0.069288] ... max period: 00007fffffffffff [ 0.069289] ... fixed-purpose events: 3 [ 0.069290] ... event mask: 000000070000000f [ 0.069314] rcu: Hierarchical SRCU implementation. [ 0.069803] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter. [ 0.069803] smp: Bringing up secondary CPUs ... [ 0.069803] x86: Booting SMP configuration: [ 0.069803] .... node #0, CPUs: #1 #2 #3 #4 [ 0.071250] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details. [ 0.071250] TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details. [ 0.071250] #5 #6 #7 [ 0.072162] smp: Brought up 1 node, 8 CPUs [ 0.072162] smpboot: Max logical packages: 1 [ 0.072162] smpboot: Total of 8 processors activated (33599.10 BogoMIPS) [ 0.072162] devtmpfs: initialized [ 0.072818] PM: Registering ACPI NVS region [mem 0xad335000-0xad335fff] (4096 bytes) [ 0.072820] PM: Registering ACPI NVS region [mem 0xbb536000-0xbb599fff] (409600 bytes) [ 0.072851] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns [ 0.072851] futex hash table entries: 2048 (order: 5, 131072 bytes, linear) [ 0.072862] thermal_sys: Registered thermal governor 'fair_share' [ 0.072889] NET: Registered protocol family 16 [ 0.072941] DMA: preallocated 4096 KiB GFP_KERNEL pool for atomic allocations [ 0.072946] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations [ 0.072952] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations [ 0.072959] ramoops: using module parameters [ 0.074125] printk: console [ramoops-1] enabled [ 0.074135] pstore: Registered ramoops as persistent store backend [ 0.074135] ramoops: using 0x400000 at 0x20000000, ecc: 0 [ 0.074135] cpuidle: using governor ladder [ 0.074135] Simple Boot Flag at 0x47 set to 0x1 [ 0.074135] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it [ 0.074135] ACPI: bus type PCI registered [ 0.074135] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf8000000-0xfbffffff] (base 0xf8000000) [ 0.074135] PCI: MMCONFIG at [mem 0xf8000000-0xfbffffff] reserved in E820 [ 0.074135] PCI: Using configuration type 1 for base access [ 0.234910] ACPI: Added _OSI(Module Device) [ 0.234910] ACPI: Added _OSI(Processor Device) [ 0.234910] ACPI: Added _OSI(3.0 _SCP Extensions) [ 0.234910] ACPI: Added _OSI(Processor Aggregator Device) [ 0.234910] ACPI: Added _OSI(Linux-Dell-Video) [ 0.234910] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) [ 0.234910] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics) [ 0.258697] ACPI: 12 ACPI AML tables successfully acquired and loaded [ 0.259375] ACPI: EC: EC started [ 0.259376] ACPI: EC: interrupt blocked [ 0.260428] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62 [ 0.260430] ACPI: EC: Boot ECDT EC used to handle transactions [ 0.261354] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored [ 0.266910] ACPI: Dynamic OEM Table Load: [ 0.266921] ACPI: SSDT 0xFFFF88842C3CD000 0005EE (v02 PmRef Cpu0Ist 00003000 INTL 20160527) [ 0.267682] ACPI: \_PR_.PR00: _OSC native thermal LVT Acked [ 0.268203] ACPI: Dynamic OEM Table Load: [ 0.268210] ACPI: SSDT 0xFFFF88842BA58400 0003FF (v02 PmRef Cpu0Cst 00003001 INTL 20160527) [ 0.268959] ACPI: Dynamic OEM Table Load: [ 0.268965] ACPI: SSDT 0xFFFF88842BA41480 0000BA (v02 PmRef Cpu0Hwp 00003000 INTL 20160527) [ 0.269663] ACPI: Dynamic OEM Table Load: [ 0.269668] ACPI: SSDT 0xFFFF88842C3CD800 000628 (v02 PmRef HwpLvt 00003000 INTL 20160527) [ 0.270545] ACPI: Dynamic OEM Table Load: [ 0.270552] ACPI: SSDT 0xFFFF88842BAB0000 000D14 (v02 PmRef ApIst 00003000 INTL 20160527) [ 0.271593] ACPI: Dynamic OEM Table Load: [ 0.271599] ACPI: SSDT 0xFFFF88842BA58800 000317 (v02 PmRef ApHwp 00003000 INTL 20160527) [ 0.272361] ACPI: Dynamic OEM Table Load: [ 0.272366] ACPI: SSDT 0xFFFF88842BA58C00 00030A (v02 PmRef ApCst 00003000 INTL 20160527) [ 0.274300] ACPI: Interpreter enabled [ 0.274322] ACPI: (supports S0 S3 S5) [ 0.274324] ACPI: Using IOAPIC for interrupt routing [ 0.274344] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.274666] ACPI: Enabled 8 GPEs in block 00 to 7F [ 0.276464] ACPI: Power Resource [PUBS] (on) [ 0.308825] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-3e]) [ 0.308832] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig Segments MSI HPX-Type3] [ 0.308888] acpi PNP0A08:00: _OSC: not requesting OS control; OS requires [ExtendedConfig ASPM ClockPM MSI] [ 0.309086] PCI host bridge to bus 0000:00 [ 0.309090] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] [ 0.309094] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 0.309097] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] [ 0.309101] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window] [ 0.309104] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window] [ 0.309108] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window] [ 0.309111] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window] [ 0.309115] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window] [ 0.309118] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window] [ 0.309121] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window] [ 0.309125] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window] [ 0.309128] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window] [ 0.309132] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window] [ 0.309135] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window] [ 0.309139] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window] [ 0.309142] pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff window] [ 0.309146] pci_bus 0000:00: root bus resource [mem 0xbf800000-0xf7ffffff window] [ 0.309149] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window] [ 0.309153] pci_bus 0000:00: root bus resource [bus 00-3e] [ 0.309164] pci 0000:00:00.0: [8086:5914] type 00 class 0x060000 [ 0.309758] pci 0000:00:02.0: [8086:5917] type 00 class 0x030000 [ 0.309773] pci 0000:00:02.0: reg 0x10: [mem 0xe0000000-0xe0ffffff 64bit] [ 0.309781] pci 0000:00:02.0: reg 0x18: [mem 0xc0000000-0xdfffffff 64bit pref] [ 0.309788] pci 0000:00:02.0: reg 0x20: [io 0xe000-0xe03f] [ 0.309806] pci 0000:00:02.0: BAR 2: assigned to efifb [ 0.310405] pci 0000:00:04.0: [8086:1903] type 00 class 0x118000 [ 0.310421] pci 0000:00:04.0: reg 0x10: [mem 0xe1240000-0xe1247fff 64bit] [ 0.311080] pci 0000:00:08.0: [8086:1911] type 00 class 0x088000 [ 0.311097] pci 0000:00:08.0: reg 0x10: [mem 0xe1250000-0xe1250fff 64bit] [ 0.311720] pci 0000:00:14.0: [8086:9d2f] type 00 class 0x0c0330 [ 0.311745] pci 0000:00:14.0: reg 0x10: [mem 0xe1220000-0xe122ffff 64bit] [ 0.311814] pci 0000:00:14.0: PME# supported from D3hot D3cold [ 0.312481] pci 0000:00:14.2: [8086:9d31] type 00 class 0x118000 [ 0.312505] pci 0000:00:14.2: reg 0x10: [mem 0xe1251000-0xe1251fff 64bit] [ 0.313229] pci 0000:00:15.0: [8086:9d60] type 00 class 0x118000 [ 0.313495] pci 0000:00:15.0: reg 0x10: [mem 0xe1252000-0xe1252fff 64bit] [ 0.314891] pci 0000:00:16.0: [8086:9d3a] type 00 class 0x078000 [ 0.314919] pci 0000:00:16.0: reg 0x10: [mem 0xe1253000-0xe1253fff 64bit] [ 0.314992] pci 0000:00:16.0: PME# supported from D3hot [ 0.315564] pci 0000:00:1c.0: [8086:9d10] type 01 class 0x060400 [ 0.315636] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold [ 0.316190] pci 0000:00:1c.4: [8086:9d14] type 01 class 0x060400 [ 0.316261] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold [ 0.316810] pci 0000:00:1c.6: [8086:9d16] type 01 class 0x060400 [ 0.316890] pci 0000:00:1c.6: PME# supported from D0 D3hot D3cold [ 0.317435] pci 0000:00:1d.0: [8086:9d18] type 01 class 0x060400 [ 0.317507] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold [ 0.318082] pci 0000:00:1f.0: [8086:9d4e] type 00 class 0x060100 [ 0.318722] pci 0000:00:1f.2: [8086:9d21] type 00 class 0x058000 [ 0.318738] pci 0000:00:1f.2: reg 0x10: [mem 0xe124c000-0xe124ffff] [ 0.319260] pci 0000:00:1f.3: [8086:9d71] type 00 class 0x040300 [ 0.319290] pci 0000:00:1f.3: reg 0x10: [mem 0xe1248000-0xe124bfff 64bit] [ 0.319322] pci 0000:00:1f.3: reg 0x20: [mem 0xe1230000-0xe123ffff 64bit] [ 0.319370] pci 0000:00:1f.3: PME# supported from D3hot D3cold [ 0.319871] pci 0000:00:1f.4: [8086:9d23] type 00 class 0x0c0500 [ 0.319934] pci 0000:00:1f.4: reg 0x10: [mem 0xe1254000-0xe12540ff 64bit] [ 0.320007] pci 0000:00:1f.4: reg 0x20: [io 0xefa0-0xefbf] [ 0.320552] pci 0000:00:1f.6: [8086:15d7] type 00 class 0x020000 [ 0.320576] pci 0000:00:1f.6: reg 0x10: [mem 0xe1200000-0xe121ffff] [ 0.320664] pci 0000:00:1f.6: PME# supported from D0 D3hot D3cold [ 0.321165] pci 0000:00:1c.0: PCI bridge to [bus 01] [ 0.321169] pci 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 0.321173] pci 0000:00:1c.0: bridge window [mem 0xbf800000-0xbf9fffff] [ 0.321179] pci 0000:00:1c.0: bridge window [mem 0xbfa00000-0xbfbfffff 64bit pref] [ 0.321216] pci 0000:00:1c.4: PCI bridge to [bus 04-3c] [ 0.321583] pci 0000:3d:00.0: [8086:24fd] type 00 class 0x028000 [ 0.321686] pci 0000:3d:00.0: reg 0x10: [mem 0xe1100000-0xe1101fff 64bit] [ 0.322020] pci 0000:3d:00.0: PME# supported from D0 D3hot D3cold [ 0.322179] pci 0000:00:1c.6: PCI bridge to [bus 3d] [ 0.322186] pci 0000:00:1c.6: bridge window [mem 0xe1100000-0xe11fffff] [ 0.322224] pci 0000:3e:00.0: [144d:a808] type 00 class 0x010802 [ 0.322254] pci 0000:3e:00.0: reg 0x10: [mem 0xe1000000-0xe1003fff 64bit] [ 0.322401] pci 0000:00:1d.0: PCI bridge to [bus 3e] [ 0.322406] pci 0000:00:1d.0: bridge window [mem 0xe1000000-0xe10fffff] [ 0.323696] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. [ 0.323735] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15), disabled. [ 0.323770] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. [ 0.323807] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. [ 0.323856] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. [ 0.323889] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. [ 0.323922] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. [ 0.323956] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. [ 0.324178] ACPI: EC: interrupt unblocked [ 0.324180] ACPI: EC: event unblocked [ 0.324193] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62 [ 0.324195] ACPI: EC: GPE=0x16 [ 0.324197] ACPI: \_SB_.PCI0.LPCB.EC__: Boot ECDT EC initialization complete [ 0.324200] ACPI: \_SB_.PCI0.LPCB.EC__: EC: Used to handle transactions and events [ 0.324240] pci 0000:00:02.0: vgaarb: setting as boot VGA device [ 0.324240] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none [ 0.324240] pci 0000:00:02.0: vgaarb: bridge control possible [ 0.324240] vgaarb: loaded [ 0.324240] SCSI subsystem initialized [ 0.324240] libata version 3.00 loaded. [ 0.324240] ACPI: bus type USB registered [ 0.324240] usbcore: registered new interface driver usbfs [ 0.324240] usbcore: registered new interface driver hub [ 0.324240] usbcore: registered new device driver usb [ 0.324240] videodev: Linux video capture interface: v2.00 [ 0.324240] Registered efivars operations [ 0.324240] PCI: Using ACPI for IRQ routing [ 0.326401] PCI: pci_cache_line_size set to 64 bytes [ 0.326815] e820: reserve RAM buffer [mem 0x00050270-0x0005ffff] [ 0.326816] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff] [ 0.326816] e820: reserve RAM buffer [mem 0x0009d000-0x0009ffff] [ 0.326817] e820: reserve RAM buffer [mem 0x7b4b3000-0x7bffffff] [ 0.326817] e820: reserve RAM buffer [mem 0x7b51d000-0x7bffffff] [ 0.326818] e820: reserve RAM buffer [mem 0xad335000-0xafffffff] [ 0.326818] e820: reserve RAM buffer [mem 0xb07d0000-0xb3ffffff] [ 0.326819] e820: reserve RAM buffer [mem 0xba3ea000-0xbbffffff] [ 0.326819] e820: reserve RAM buffer [mem 0xbb600000-0xbbffffff] [ 0.326820] e820: reserve RAM buffer [mem 0x43e800000-0x43fffffff] [ 0.326837] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 [ 0.326840] hpet0: 8 comparators, 64-bit 24.000000 MHz counter [ 0.328813] clocksource: Switched to clocksource tsc-early [ 0.333518] pnp: PnP ACPI init [ 0.333555] system 00:00: [mem 0x40000000-0x403fffff] has been reserved [ 0.333560] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.333617] system 00:01: [mem 0xfd000000-0xfdabffff] has been reserved [ 0.333620] system 00:01: [mem 0xfdad0000-0xfdadffff] has been reserved [ 0.333623] system 00:01: [mem 0xfdb00000-0xfdffffff] has been reserved [ 0.333625] system 00:01: [mem 0xfe000000-0xfe01ffff] could not be reserved [ 0.333627] system 00:01: [mem 0xfe036000-0xfe03bfff] has been reserved [ 0.333630] system 00:01: [mem 0xfe03d000-0xfe3fffff] has been reserved [ 0.333632] system 00:01: [mem 0xfe410000-0xfe7fffff] has been reserved [ 0.333636] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.333779] system 00:02: [io 0xff00-0xfffe] has been reserved [ 0.333783] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.334085] system 00:03: [io 0x0680-0x069f] has been reserved [ 0.334087] system 00:03: [io 0xffff] has been reserved [ 0.334090] system 00:03: [io 0xffff] has been reserved [ 0.334092] system 00:03: [io 0xffff] has been reserved [ 0.334094] system 00:03: [io 0x1800-0x18fe] has been reserved [ 0.334096] system 00:03: [io 0x164e-0x164f] has been reserved [ 0.334099] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.334145] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.334164] system 00:05: [io 0x1854-0x1857] has been reserved [ 0.334168] system 00:05: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) [ 0.334176] pnp 00:06: Plug and Play ACPI device, IDs LEN0071 PNP0303 (active) [ 0.334184] pnp 00:07: Plug and Play ACPI device, IDs LEN008f PNP0f13 (active) [ 0.334231] system 00:08: [io 0x1800-0x189f] could not be reserved [ 0.334234] system 00:08: [io 0x0800-0x087f] has been reserved [ 0.334236] system 00:08: [io 0x0880-0x08ff] has been reserved [ 0.334238] system 00:08: [io 0x0900-0x097f] has been reserved [ 0.334241] system 00:08: [io 0x0980-0x09ff] has been reserved [ 0.334243] system 00:08: [io 0x0a00-0x0a7f] has been reserved [ 0.334245] system 00:08: [io 0x0a80-0x0aff] has been reserved [ 0.334247] system 00:08: [io 0x0b00-0x0b7f] has been reserved [ 0.334249] system 00:08: [io 0x0b80-0x0bff] has been reserved [ 0.334251] system 00:08: [io 0x15e0-0x15ef] has been reserved [ 0.334254] system 00:08: [io 0x1600-0x167f] could not be reserved [ 0.334256] system 00:08: [io 0x1640-0x165f] could not be reserved [ 0.334258] system 00:08: [mem 0xf8000000-0xfbffffff] has been reserved [ 0.334261] system 00:08: [mem 0xfed10000-0xfed13fff] has been reserved [ 0.334263] system 00:08: [mem 0xfed18000-0xfed18fff] has been reserved [ 0.334265] system 00:08: [mem 0xfed19000-0xfed19fff] has been reserved [ 0.334268] system 00:08: [mem 0xfeb00000-0xfebfffff] has been reserved [ 0.334270] system 00:08: [mem 0xfed20000-0xfed3ffff] has been reserved [ 0.334272] system 00:08: [mem 0xfed90000-0xfed93fff] has been reserved [ 0.334275] system 00:08: [mem 0xf7fe0000-0xf7ffffff] has been reserved [ 0.334278] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.334873] system 00:09: [mem 0xfdaf0000-0xfdafffff] has been reserved [ 0.334876] system 00:09: [mem 0xfdae0000-0xfdaeffff] has been reserved [ 0.334878] system 00:09: [mem 0xfdac0000-0xfdacffff] has been reserved [ 0.334882] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.335298] system 00:0a: [mem 0xfed10000-0xfed17fff] could not be reserved [ 0.335301] system 00:0a: [mem 0xfed18000-0xfed18fff] has been reserved [ 0.335303] system 00:0a: [mem 0xfed19000-0xfed19fff] has been reserved [ 0.335305] system 00:0a: [mem 0xf8000000-0xfbffffff] has been reserved [ 0.335308] system 00:0a: [mem 0xfed20000-0xfed3ffff] has been reserved [ 0.335310] system 00:0a: [mem 0xfed90000-0xfed93fff] has been reserved [ 0.335312] system 00:0a: [mem 0xfed45000-0xfed8ffff] has been reserved [ 0.335315] system 00:0a: [mem 0xff000000-0xffffffff] has been reserved [ 0.335317] system 00:0a: [mem 0xfee00000-0xfeefffff] has been reserved [ 0.335319] system 00:0a: [mem 0xf7fe0000-0xf7ffffff] has been reserved [ 0.335323] system 00:0a: Plug and Play ACPI device, IDs PNP0c02 (active) [ 0.335462] system 00:0b: [mem 0x00000000-0x0009ffff] could not be reserved [ 0.335465] system 00:0b: [mem 0x000f0000-0x000fffff] could not be reserved [ 0.335467] system 00:0b: [mem 0x00100000-0xbf7fffff] could not be reserved [ 0.335470] system 00:0b: [mem 0xfec00000-0xfed3ffff] could not be reserved [ 0.335472] system 00:0b: [mem 0xfed4c000-0xffffffff] could not be reserved [ 0.335476] system 00:0b: Plug and Play ACPI device, IDs PNP0c01 (active) [ 0.335521] pnp: PnP ACPI: found 12 devices [ 0.340600] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns [ 0.340618] NET: Registered protocol family 2 [ 0.340679] tcp_listen_portaddr_hash hash table entries: 8192 (order: 5, 131072 bytes, linear) [ 0.340696] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear) [ 0.340808] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear) [ 0.340925] TCP: Hash tables configured (established 131072 bind 65536) [ 0.340945] UDP hash table entries: 8192 (order: 6, 262144 bytes, linear) [ 0.340974] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes, linear) [ 0.341024] NET: Registered protocol family 1 [ 0.341032] pci 0000:00:1c.0: PCI bridge to [bus 01] [ 0.341037] pci 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 0.341041] pci 0000:00:1c.0: bridge window [mem 0xbf800000-0xbf9fffff] [ 0.341045] pci 0000:00:1c.0: bridge window [mem 0xbfa00000-0xbfbfffff 64bit pref] [ 0.341050] pci 0000:00:1c.4: PCI bridge to [bus 04-3c] [ 0.341060] pci 0000:00:1c.6: PCI bridge to [bus 3d] [ 0.341065] pci 0000:00:1c.6: bridge window [mem 0xe1100000-0xe11fffff] [ 0.341071] pci 0000:00:1d.0: PCI bridge to [bus 3e] [ 0.341075] pci 0000:00:1d.0: bridge window [mem 0xe1000000-0xe10fffff] [ 0.341081] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] [ 0.341084] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] [ 0.341086] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] [ 0.341088] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window] [ 0.341091] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window] [ 0.341093] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window] [ 0.341095] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window] [ 0.341097] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window] [ 0.341100] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window] [ 0.341102] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window] [ 0.341104] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window] [ 0.341106] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window] [ 0.341109] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window] [ 0.341111] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window] [ 0.341113] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window] [ 0.341115] pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff window] [ 0.341118] pci_bus 0000:00: resource 20 [mem 0xbf800000-0xf7ffffff window] [ 0.341120] pci_bus 0000:00: resource 21 [mem 0xfd000000-0xfe7fffff window] [ 0.341122] pci_bus 0000:01: resource 0 [io 0x2000-0x2fff] [ 0.341124] pci_bus 0000:01: resource 1 [mem 0xbf800000-0xbf9fffff] [ 0.341127] pci_bus 0000:01: resource 2 [mem 0xbfa00000-0xbfbfffff 64bit pref] [ 0.341129] pci_bus 0000:3d: resource 1 [mem 0xe1100000-0xe11fffff] [ 0.341132] pci_bus 0000:3e: resource 1 [mem 0xe1000000-0xe10fffff] [ 0.341195] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] [ 0.341673] PCI: CLS 0 bytes, default 64 [ 0.341691] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 0.341694] software IO TLB: mapped [mem 0xb63ea000-0xba3ea000] (64MB) [ 0.341729] resource sanity check: requesting [mem 0xfed10000-0xfed15fff], which spans more than pnp 00:08 [mem 0xfed10000-0xfed13fff] [ 0.341734] caller snb_uncore_imc_init_box+0x6c/0xb0 mapping multiple BARs [ 0.342043] simple-framebuffer simple-framebuffer.0: framebuffer at 0xc0000000, 0x7e9000 bytes, mapped to 0x000000004ff2874b [ 0.342047] simple-framebuffer simple-framebuffer.0: format=a8r8g8b8, mode=1920x1080x32, linelength=7680 [ 0.475073] Console: switching to colour frame buffer device 240x67 [ 0.608186] simple-framebuffer simple-framebuffer.0: fb0: simplefb registered! [ 0.608391] Initialise system trusted keyrings [ 0.609324] workingset: timestamp_bits=60 max_order=22 bucket_order=0 [ 0.610567] 9p: Installing v9fs 9p2000 file system support [ 0.616822] Key type asymmetric registered [ 0.617209] Asymmetric key parser 'x509' registered [ 0.617668] Key type pkcs7_test registered [ 0.618058] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) [ 0.618772] io scheduler bfq registered [ 0.619875] ACPI: AC Adapter [AC] (on-line) [ 0.620314] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input0 [ 0.621116] ACPI: Sleep Button [SLPB] [ 0.621475] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input1 [ 0.622255] ACPI: Lid Switch [LID] [ 0.622588] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 [ 0.623294] ACPI: Power Button [PWRF] [ 0.623815] Monitor-Mwait will be used to enter C-1 state [ 0.623818] Monitor-Mwait will be used to enter C-2 state [ 0.623821] Monitor-Mwait will be used to enter C-3 state [ 0.623823] ACPI: \_PR_.PR00: Found 3 idle states [ 0.624412] ACPI: \_PR_.PR01: Found 3 idle states [ 0.624979] ACPI: \_PR_.PR02: Found 3 idle states [ 0.625545] ACPI: \_PR_.PR03: Found 3 idle states [ 0.626114] ACPI: \_PR_.PR04: Found 3 idle states [ 0.626693] ACPI: \_PR_.PR05: Found 3 idle states [ 0.627275] ACPI: \_PR_.PR06: Found 3 idle states [ 0.627857] ACPI: \_PR_.PR07: Found 3 idle states [ 0.631002] thermal LNXTHERM:00: registered as thermal_zone0 [ 0.631535] ACPI: Thermal Zone [THM0] (46 C) [ 0.632018] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 0.632947] Non-volatile memory driver v1.3 [ 0.633970] brd: module loaded [ 0.634784] nvme nvme0: pci function 0000:3e:00.0 [ 0.635268] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 0.635895] ehci-pci: EHCI PCI platform driver [ 0.636403] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 0.636903] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1 [ 0.638679] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x0000000081109810 [ 0.639627] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported [ 0.640462] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.08 [ 0.641262] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 0.641965] usb usb1: Product: xHCI Host Controller [ 0.642417] usb usb1: Manufacturer: Linux 5.8.0-rc1+ xhci-hcd [ 0.642985] usb usb1: SerialNumber: 0000:00:14.0 [ 0.643553] hub 1-0:1.0: USB hub found [ 0.644738] nvme nvme0: Shutdown timeout set to 8 seconds [ 0.659136] battery: ACPI: Battery Slot [BAT0] (battery present) [ 0.670685] hub 1-0:1.0: 12 ports detected [ 0.706146] nvme nvme0: 8/0/0 default/read/poll queues [ 0.726320] xhci_hcd 0000:00:14.0: xHCI Host Controller [ 0.760397] nvme0n1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 [ 0.782379] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 [ 0.869762] xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed [ 0.899414] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.08 [ 0.929333] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 0.959125] usb usb2: Product: xHCI Host Controller [ 0.989123] usb usb2: Manufacturer: Linux 5.8.0-rc1+ xhci-hcd [ 1.019029] usb usb2: SerialNumber: 0000:00:14.0 [ 1.048692] hub 2-0:1.0: USB hub found [ 1.078218] hub 2-0:1.0: 6 ports detected [ 1.107665] usb: port power management may be unreliable [ 1.137123] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 [ 1.168929] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 1.198243] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 1.218815] usb 1-2: new high-speed USB device number 2 using xhci_hcd [ 1.226895] mousedev: PS/2 mouse device common for all mice [ 1.283539] rtc_cmos 00:04: RTC can wake from S4 [ 1.311857] rtc_cmos 00:04: registered as rtc0 [ 1.338713] rtc_cmos 00:04: setting system clock to 2020-06-17T06:16:02 UTC (1592374562) [ 1.365651] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs [ 1.372857] tsc: Refined TSC clocksource calibration: 2111.991 MHz [ 1.392532] usb 1-2: New USB device found, idVendor=0bda, idProduct=5411, bcdDevice= 1.04 [ 1.392533] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 1.392534] usb 1-2: Product: 4-Port USB 2.0 Hub [ 1.392535] usb 1-2: Manufacturer: Generic [ 1.392924] device-mapper: uevent: version 1.0.3 [ 1.393324] hub 1-2:1.0: USB hub found [ 1.393916] hub 1-2:1.0: 4 ports detected [ 1.420841] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x1e716fff2bd, max_idle_ns: 440795203249 ns [ 1.638917] clocksource: Switched to clocksource tsc [ 1.638944] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 [ 1.639001] device-mapper: ioctl: 4.42.0-ioctl (2020-02-27) initialised: dm-devel at redhat.com [ 1.639003] intel_pstate: Intel P-state driver initializing [ 1.693085] usb 2-2: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd [ 1.779384] intel_pstate: HWP enabled [ 1.797519] random: fast init done [ 1.801443] usb 2-2: New USB device found, idVendor=0bda, idProduct=0411, bcdDevice= 1.04 [ 1.801444] usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 1.801445] usb 2-2: Product: 4-Port USB 3.0 Hub [ 1.801445] usb 2-2: Manufacturer: Generic [ 1.806226] hub 2-2:1.0: USB hub found [ 1.806378] EFI Variables Facility v0.08 2004-May-17 [ 1.807181] hub 2-2:1.0: 4 ports detected [ 1.909848] usb 1-7: new full-speed USB device number 3 using xhci_hcd [ 1.949253] usbcore: registered new interface driver usbhid [ 2.012594] input: PS/2 Generic Mouse as /devices/platform/i8042/serio1/input/input5 [ 2.026540] usbhid: USB HID core driver [ 2.097189] usb 1-7: New USB device found, idVendor=8087, idProduct=0a2b, bcdDevice= 0.10 [ 2.113071] Initializing XFRM netlink socket [ 2.142150] usb 1-7: New USB device strings: Mfr=0, Product=0, SerialNumber=0 [ 2.193860] usb 1-2.1: new low-speed USB device number 4 using xhci_hcd [ 2.200942] NET: Registered protocol family 17 [ 2.321413] NET: Registered protocol family 15 [ 2.324535] usb 1-2.1: New USB device found, idVendor=413c, idProduct=301a, bcdDevice= 1.00 [ 2.351264] Bridge firewalling registered [ 2.381722] usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [ 2.381723] usb 1-2.1: Product: Dell MS116 USB Optical Mouse [ 2.411714] 9pnet: Installing 9P2000 support [ 2.433980] usb 2-3: new SuperSpeed Gen 1 USB device number 3 using xhci_hcd [ 2.442082] usb 1-2.1: Manufacturer: PixArt [ 2.457036] usb 2-3: New USB device found, idVendor=0bda, idProduct=0316, bcdDevice= 2.04 [ 2.457037] usb 2-3: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 2.457037] usb 2-3: Product: USB3.0-CRW [ 2.457038] usb 2-3: Manufacturer: Generic [ 2.457038] usb 2-3: SerialNumber: 20120501030900000 [ 2.713976] microcode: sig=0x806ea, pf=0x80, revision=0xb4 [ 2.718305] input: PixArt Dell MS116 USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.1/1-2.1:1.0/0003:413C:301A.0001/input/input6 [ 2.777500] hid-generic 0003:413C:301A.0001: input: USB HID v1.11 Mouse [PixArt Dell MS116 USB Optical Mouse] on usb-0000:00:14.0-2.1/input0 [ 2.777608] microcode: Microcode Update Driver: v2.2. [ 2.777628] IPI shorthand broadcast: enabled [ 2.873283] sched_clock: Marking stable (2869680977, 3595871)->(2874053724, -776876) [ 2.885847] usb 1-2.2: new low-speed USB device number 5 using xhci_hcd [ 2.905201] registered taskstats version 1 [ 2.969261] Loading compiled-in X.509 certificates [ 3.022476] Loaded X.509 cert 'dyoung kernel test key: 9d5c9a70fe6578e1ba171ba2ab9f3449d6688559' [ 3.034053] usb 1-2.2: New USB device found, idVendor=413c, idProduct=2113, bcdDevice= 1.10 [ 3.057031] Loaded X.509 cert 'dyoung kernel test key: 9d5c9a70fe6578e1ba171ba2ab9f3449d6688559' [ 3.090359] usb 1-2.2: New USB device strings: Mfr=0, Product=2, SerialNumber=0 [ 3.124441] pstore: Using crash dump compression: lzo [ 3.158473] usb 1-2.2: Product: Dell KB216 Wired Keyboard [ 3.192879] Key type encrypted registered [ 3.236217] input: Dell KB216 Wired Keyboard as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.2/1-2.2:1.0/0003:413C:2113.0002/input/input7 [ 3.348685] hid-generic 0003:413C:2113.0002: input: USB HID v1.11 Keyboard [Dell KB216 Wired Keyboard] on usb-0000:00:14.0-2.2/input0 [ 3.396179] input: Dell KB216 Wired Keyboard Consumer Control as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.2/1-2.2:1.1/0003:413C:2113.0003/input/input8 [ 3.484726] input: Dell KB216 Wired Keyboard System Control as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.2/1-2.2:1.1/0003:413C:2113.0003/input/input9 [ 3.527580] hid-generic 0003:413C:2113.0003: input: USB HID v1.11 Device [Dell KB216 Wired Keyboard] on usb-0000:00:14.0-2.2/input1 [ 3.573674] EXT4-fs (nvme0n1p9): mounted filesystem with ordered data mode. Opts: (null) [ 3.611217] VFS: Mounted root (ext4 filesystem) readonly on device 259:9. [ 3.640814] usb 1-2.3: new high-speed USB device number 6 using xhci_hcd [ 3.651423] devtmpfs: mounted [ 3.722718] Freeing unused decrypted memory: 2040K [ 3.760257] Freeing unused kernel image (initmem) memory: 1224K [ 3.775165] usb 1-2.3: New USB device found, idVendor=046d, idProduct=085c, bcdDevice= 0.16 [ 3.835064] Write protecting the kernel read-only data: 16384k [ 3.872466] usb 1-2.3: New USB device strings: Mfr=0, Product=2, SerialNumber=1 [ 3.909811] usb 1-2.3: Product: C922 Pro Stream Webcam [ 3.946736] usb 1-2.3: SerialNumber: 9D6A015F [ 3.983384] Freeing unused kernel image (text/rodata gap) memory: 2044K [ 4.020469] Freeing unused kernel image (rodata/data gap) memory: 1612K [ 4.060040] usb 1-2.4: new high-speed USB device number 7 using xhci_hcd [ 4.096819] Run 5 as init process [ 4.132427] with arguments: [ 4.132428] 5 [ 4.132428] with environment: [ 4.132428] HOME=/ [ 4.132428] TERM=linux [ 4.132429] hung_task_panic=1 [ 4.132429] softlockup_panic=1 [ 4.132429] LANG=zh_CN.UTF-8 [ 4.132429] selinux=0 [ 4.132430] crashkernel=160M [ 4.132440] Default init 5 failed (error -2) [ 4.168197] Run /sbin/init as init process [ 4.185829] usb 1-2.4: New USB device found, idVendor=0bda, idProduct=8152, bcdDevice=20.00 [ 4.203820] with arguments: [ 4.203821] /sbin/init [ 4.239856] usb 1-2.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.239857] usb 1-2.4: Product: USB 10/100 LAN [ 4.275831] with environment: [ 4.275831] HOME=/ [ 4.275832] TERM=linux [ 4.275832] hung_task_panic=1 [ 4.311766] softlockup_panic=1 [ 4.311766] usb 1-2.4: Manufacturer: Realtek [ 4.311767] usb 1-2.4: SerialNumber: 00E04C363074 [ 4.347697] LANG=zh_CN.UTF-8 [ 4.383522] selinux=0 [ 4.383522] crashkernel=160M [ 4.906362] random: lvmconfig: uninitialized urandom read (4 bytes read) [ 6.526063] fuse: init (API version 7.31) [ 7.016455] EXT4-fs (nvme0n1p9): re-mounted. Opts: (null) [ 8.256267] i801_smbus 0000:00:1f.4: SPD Write Disable is set [ 8.261557] random: mktemp: uninitialized urandom read (6 bytes read) [ 8.267828] random: mktemp: uninitialized urandom read (6 bytes read) [ 8.273515] random: tlp-readconfs: uninitialized urandom read (4 bytes read) [ 8.306017] i801_smbus 0000:00:1f.4: SMBus using PCI interrupt [ 8.645630] i2c i2c-0: 2/2 memory slots populated (from DMI) [ 8.705690] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k [ 8.706126] i2c i2c-0: Successfully instantiated SPD at 0x51 [ 8.780357] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. [ 8.942072] e1000e 0000:00:1f.6: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode [ 8.985248] input: PC Speaker as /devices/platform/pcspkr/input/input10 [ 9.042729] checking generic (c0000000 7e9000) vs hw (e0000000 1000000) [ 9.042730] checking generic (c0000000 7e9000) vs hw (c0000000 20000000) [ 9.042731] fb0: switching to inteldrmfb from simple [ 9.043504] thinkpad_acpi: ThinkPad ACPI Extras v0.26 [ 9.043512] cfg80211: Loading compiled-in X.509 certificates for regulatory database [ 9.043652] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' [ 9.098996] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 8c:16:45:75:50:6c [ 9.099625] thinkpad_acpi: http://ibm-acpi.sf.net/ [ 9.125361] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection [ 9.149540] thinkpad_acpi: ThinkPad BIOS N22ET54W (1.31 ), EC N22HT26W [ 9.175060] e1000e 0000:00:1f.6 eth0: MAC: 12, PHY: 12, PBA No: 1000FF-0FF [ 9.243214] thinkpad_acpi: Lenovo ThinkPad T480s, model 20L8S3M801 [ 9.405125] Console: switching to colour dummy device 80x25 [ 9.405156] i915 0000:00:02.0: vgaarb: deactivate vga console [ 9.408636] Intel(R) Wireless WiFi driver for Linux [ 9.414444] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 9.415081] i915 0000:00:02.0: [drm] *ERROR* DC state mismatch (0x0 -> 0x2) [ 9.415115] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem [ 9.416314] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_04.bin (v1.4) [ 9.431961] iwlwifi 0000:3d:00.0: Found debug destination: EXTERNAL_DRAM [ 9.431968] iwlwifi 0000:3d:00.0: Found debug configuration: 0 [ 9.432338] iwlwifi 0000:3d:00.0: loaded firmware version 36.77d01142.0 8265-36.ucode op_mode iwlmvm [ 9.432451] iwlwifi 0000:3d:00.0: Direct firmware load for iwl-debug-yoyo.bin failed with error -2 [ 9.435126] thinkpad_acpi: radio switch found; radios are enabled [ 9.435261] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver [ 9.435266] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... [ 9.449417] thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is unblocked [ 9.468511] [drm] Initialized i915 1.6.0 20200515 for 0000:00:02.0 on minor 0 [ 9.472498] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one [ 9.493868] Adding 1048572k swap on /dev/nvme0n1p10. Priority:-2 extents:1 across:1048572k SS [ 9.512366] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) [ 9.512522] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input12 [ 9.512890] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) [ 9.520300] thinkpad_acpi: battery 1 registered (start 0, stop 100) [ 9.520303] battery: new extension: ThinkPad Battery Extension [ 9.521015] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input11 [ 9.545743] iwlwifi 0000:3d:00.0: Detected Intel(R) Dual Band Wireless AC 8265, REV=0x230 [ 9.562287] iwlwifi 0000:3d:00.0: Applying debug destination EXTERNAL_DRAM [ 9.563432] iwlwifi 0000:3d:00.0: Allocated 0x00400000 bytes for firmware monitor. [ 9.602240] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC257: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker [ 9.602408] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) [ 9.602412] snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x21/0x0/0x0/0x0/0x0) [ 9.602416] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 [ 9.602418] snd_hda_codec_realtek hdaudioC0D0: inputs: [ 9.602422] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 [ 9.602425] snd_hda_codec_realtek hdaudioC0D0: Internal Mic=0x12 [ 9.628002] iwlwifi 0000:3d:00.0: base HW address: b4:6b:fc:a3:80:d6 [ 9.652406] fbcon: i915drmfb (fb0) is primary device [ 9.653653] ------------[ cut here ]------------ [ 9.653654] i915 0000:00:02.0: drm_WARN_ON(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })) & (1 << 31)) [ 9.657092] WARNING: CPU: 1 PID: 103 at drivers/gpu/drm/i915/display/intel_psr.c:782 intel_psr_activate+0x3c6/0x440 [i915] [ 9.657093] Modules linked in: snd_hda_codec_realtek(+) snd_hda_codec_generic iwlmvm(+) mac80211 input_leds snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core kvm_intel libarc4 snd_seq kvm snd_seq_device iwlwifi serio_raw irqbypass snd_pcm thinkpad_acpi pcspkr cfg80211 ledtrig_audio snd_timer rfkill i915 e1000e snd i2c_i801 soundcore i2c_smbus video intel_gtt iosf_mbi drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops fuse drm [ 9.657262] CPU: 1 PID: 103 Comm: kworker/u16:3 Not tainted 5.8.0-rc1+ #179 [ 9.657262] Hardware name: LENOVO 20L8S3M801/20L8S3M801, BIOS N22ET54W (1.31 ) 04/22/2019 [ 9.657262] Workqueue: events_unbound async_run_entry_fn [ 9.657263] RIP: 0010:intel_psr_activate+0x3c6/0x440 [i915] [ 9.657264] Code: 4c 8b 6f 50 4d 85 ed 75 03 4c 8b 2f e8 c3 e0 1f e1 48 c7 c1 a0 ca 2e a0 4c 89 ea 48 c7 c7 40 3b 30 a0 48 89 c6 e8 f2 21 e0 e0 <0f> 0b 80 bd 88 69 00 00 00 0f 84 b5 fc ff ff 48 8b 7d 18 4c 8b 6f [ 9.657264] RSP: 0018:ffff88842ad2b898 EFLAGS: 00010282 [ 9.657265] RAX: 0000000000000000 RBX: 0000000000000001 RCX: 0000000000000000 [ 9.657265] RDX: 000000000000013a RSI: ffffffff825346da RDI: ffffffff82534ada [ 9.657265] RBP: ffff888423228000 R08: 000000023f6713ae R09: 000000000000013a [ 9.657266] R10: 0000000000000067 R11: 000000000002fa10 R12: ffff88842c16b128 [ 9.657266] R13: ffff88842bb09970 R14: 0000000000000001 R15: ffff88842cbcc000 [ 9.657266] FS: 0000000000000000(0000) GS:ffff88842e440000(0000) knlGS:0000000000000000 [ 9.657267] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 9.657267] CR2: 000055b5c70404c8 CR3: 0000000421d96005 CR4: 00000000001606e0 [ 9.657267] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 9.657267] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 9.657267] Call Trace: [ 9.657268] intel_psr_update+0x17c/0x1a0 [i915] [ 9.657268] intel_ddi_update_pipe+0x6c/0xb0 [i915] [ 9.657268] intel_update_crtc+0x28b/0x420 [i915] [ 9.657268] skl_commit_modeset_enables+0x142/0x4e0 [i915] [ 9.657269] intel_atomic_commit_tail+0x2c6/0x1290 [i915] [ 9.657269] ? complete+0x2f/0x40 [ 9.657269] ? flush_workqueue_prep_pwqs+0x118/0x130 [ 9.657269] ? flush_workqueue+0x178/0x3c0 [ 9.657270] intel_atomic_commit+0x281/0x300 [i915] [ 9.657270] drm_client_modeset_commit_atomic+0x1be/0x200 [drm] [ 9.657270] drm_client_modeset_commit_locked+0x54/0x150 [drm] [ 9.657270] drm_client_modeset_commit+0x24/0x40 [drm] [ 9.657271] drm_fb_helper_restore_fbdev_mode_unlocked+0x49/0x90 [drm_kms_helper] [ 9.657271] drm_fb_helper_set_par+0x30/0x40 [drm_kms_helper] [ 9.657271] intel_fbdev_set_par+0x16/0x60 [i915] [ 9.657272] ? con_is_visible+0x27/0x40 [ 9.657272] fbcon_init+0x2e7/0x680 [ 9.657272] visual_init+0xce/0x130 [ 9.657272] do_bind_con_driver.isra.0+0x1da/0x2e0 [ 9.657273] do_take_over_console+0x116/0x180 [ 9.657273] do_fbcon_takeover+0x5c/0xc0 [ 9.657273] register_framebuffer+0x1e4/0x300 [ 9.657274] __drm_fb_helper_initial_config_and_unlock+0x320/0x490 [drm_kms_helper] [ 9.657274] intel_fbdev_initial_config+0x14/0x30 [i915] [ 9.657274] async_run_entry_fn+0x37/0x150 [ 9.657274] process_one_work+0x1bf/0x3d0 [ 9.657275] worker_thread+0x4d/0x3d0 [ 9.657275] ? process_one_work+0x3d0/0x3d0 [ 9.657275] kthread+0x11b/0x140 [ 9.657276] ? kthread_create_worker_on_cpu+0x70/0x70 [ 9.657276] ret_from_fork+0x22/0x30 [ 9.657276] ---[ end trace f701c3abca58b4af ]--- [ 9.674849] Console: switching to colour frame buffer device 240x67 [snip] Thanks Dave From sfr at canb.auug.org.au Wed Jun 17 07:03:07 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Wed, 17 Jun 2020 17:03:07 +1000 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree In-Reply-To: <c82b9c52-d4e6-9eef-e37d-0a26ee9f1183@suse.de> References: <20200617105929.534edd34@canb.auug.org.au> <c82b9c52-d4e6-9eef-e37d-0a26ee9f1183@suse.de> Message-ID: <20200617170307.3c87be5a@canb.auug.org.au> Hi Thomas, On Wed, 17 Jun 2020 08:33:24 +0200 Thomas Zimmermann <tzimmermann at suse.de> wrote: > > We recently dropped the _unlock() suffix from drm_gem_object_put(). This > patch should be ok. Yes, but what it shows is that the drm-misc tree is still based on v5.7-rc1 and v5.8-rc1 has about 16000 more commits for you to get conflicts against :-) -- Cheers, Stephen Rothwell -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200617/c6c80b33/attachment.sig> From shaofeng.tang at intel.com Wed Jun 17 07:41:40 2020 From: shaofeng.tang at intel.com (Shaofeng Tang) Date: Wed, 17 Jun 2020 15:41:40 +0800 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <otc-external> References: <otc-external> Message-ID: <20200617074140.17032-1-shaofeng.tang@intel.com> [Why] Query if vgpu is active, it is useful to the user. Currently, only the primary plane is usable when vgpu is active. The value of vgpu active is useful for user to determine how many planes can be used. also useful for user to determine different behaviors according to vgpu is active or not. [How] Add a switch-case in the IOCTL 'i915_getparam_ioctl' to return 'intel_vgpu_active' Signed-off-by: Shaofeng Tang <shaofeng.tang at intel.com> --- drivers/gpu/drm/i915/i915_getparam.c | 4 ++++ include/uapi/drm/i915_drm.h | 6 ++++++ tools/include/uapi/drm/i915_drm.h | 6 ++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index d042644..6d9a0b9 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -7,6 +7,7 @@ #include "i915_drv.h" #include "i915_perf.h" +#include "i915_vgpu.h" int i915_getparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) @@ -161,6 +162,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, case I915_PARAM_PERF_REVISION: value = i915_perf_ioctl_version(); break; + case I915_PARAM_IS_GVT: + value = intel_vgpu_active(i915); + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 14b67cd..74f06e2 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h index 2813e57..ecaad82 100644 --- a/tools/include/uapi/drm/i915_drm.h +++ b/tools/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { -- 2.9.2 base-commit: a4136c4aa44855a8301f32fd4db5bde84ebb8e89 prerequisite-patch-id: 7ee5af51de7b25a7f547e64696dc813062e2299b From shaofeng.tang at intel.com Wed Jun 17 07:54:40 2020 From: shaofeng.tang at intel.com (Shaofeng Tang) Date: Wed, 17 Jun 2020 15:54:40 +0800 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <otc-external> References: <otc-external> Message-ID: <20200617075440.6913-1-shaofeng.tang@intel.com> [Why] Query if vgpu is active, it is useful to the user. Currently, only the primary plane is usable when vgpu is active. The value of vgpu active is useful for user to determine how many planes can be used. also useful for user to determine different behaviors according to vgpu is active or not. [How] Add a switch-case in the IOCTL 'i915_getparam_ioctl' to return 'intel_vgpu_active' Signed-off-by: Shaofeng Tang <shaofeng.tang at intel.com> --- drivers/gpu/drm/i915/i915_getparam.c | 4 ++++ include/uapi/drm/i915_drm.h | 6 ++++++ tools/include/uapi/drm/i915_drm.h | 6 ++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index d042644..6d9a0b9 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -7,6 +7,7 @@ #include "i915_drv.h" #include "i915_perf.h" +#include "i915_vgpu.h" int i915_getparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) @@ -161,6 +162,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, case I915_PARAM_PERF_REVISION: value = i915_perf_ioctl_version(); break; + case I915_PARAM_IS_GVT: + value = intel_vgpu_active(i915); + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 14b67cd..74f06e2 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h index 2813e57..ecaad82 100644 --- a/tools/include/uapi/drm/i915_drm.h +++ b/tools/include/uapi/drm/i915_drm.h @@ -619,6 +619,12 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_PERF_REVISION 54 +/* + * Query whether GVT is active. The value returned helps userspace application + * to determine what KMS resources are workable. + */ +#define I915_PARAM_IS_GVT 55 + /* Must be kept compact -- no holes and well documented */ typedef struct drm_i915_getparam { -- 2.9.2 base-commit: 999bc17a2471df17a3af3001d094cf6d5d4849b0 From daniel at ffwll.ch Wed Jun 17 07:57:54 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 17 Jun 2020 09:57:54 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200616145312.GC6578@ziepe.ca> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> <20200616145312.GC6578@ziepe.ca> Message-ID: <CAKMK7uER6ax1zr14xYLKqDfDZp+ycBsY9Yx7JaVkKQ849VfSPg@mail.gmail.com> On Wed, Jun 17, 2020 at 9:27 AM Jason Gunthorpe <jgg at ziepe.ca> wrote: > > On Tue, Jun 16, 2020 at 02:07:19PM +0200, Daniel Vetter wrote: > > > > I've pinged a bunch of armsoc gpu driver people and ask them how much this > > > > hurts, so that we have a clear answer. On x86 I don't think we have much > > > > of a choice on this, with userptr in amd and i915 and hmm work in nouveau > > > > (but nouveau I think doesn't use dma_fence in there). > > > > > > Right, nor will RDMA ODP. > > > > Hm, what's the context here? I thought RDMA side you really don't want > > dma_fence in mmu_notifiers, so not clear to me what you're agreeing on > > here. > > rdma does not use dma_fence at all, and though it is hard to tell, I > didn't notice a dma_fence in the nouveau invalidation call path. Nouveau for compute has hw page faults. It doesn't have hw page faults for non-compute fixed function blocks afaik, so there's a hybrid model going on. But nouveau also doesn't support userspace memory (instead of driver-allocated buffer objects) for these fixed function blocks, so no need to have a dma_fence_wait in there. > At the very least I think there should be some big warning that > dma_fence in notifiers should be avoided. Yeah I'm working on documentation, and also the notifiers here hopefully make it clear it's massive pain. I think we could even make a hard rule that dma_fence in mmu notifier outside of drivers/gpu is a bug/misfeature. Might be a good idea to add a MAINTAINERS entry with a K: regex pattern, so that you can catch such modifiers. We do already have such a pattern for dma-fence, to catch abuse. So if you want I could type up a documentation patch for this, get your and others acks and the dri-devel folks would enforce that the dma_fence_wait madness doesn't leak beyond drivers/gpu > Ie it is strange that the new totally-not-a-gpu drivers use dma_fence, > they surely don't have the same constraints as the existing GPU world, > and it would be annoying to see dma_fence notifiers spring up in them If you mean drivers/misc/habanalabs, that's going to get taken care of: commit ed65bfd9fd86dec3772570b0320ca85b9fb69f2e Author: Daniel Vetter <daniel.vetter at ffwll.ch> Date: Mon May 11 11:11:42 2020 +0200 habanalabs: don't set default fence_ops->wait It's the default. Also so much for "we're not going to tell the graphics people how to review their code", dma_fence is a pretty core piece of gpu driver infrastructure. And it's very much uapi relevant, including piles of corresponding userspace protocols and libraries for how to pass these around. Would be great if habanalabs would not use this (from a quick look it's not needed at all), since open source the userspace and playing by the usual rules isn't on the table. If that's not possible (because it's actually using the uapi part of dma_fence to interact with gpu drivers) then we have exactly what everyone promised we'd want to avoid. Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Reviewed-by: Oded Gabbay <oded.gabbay at gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay at gmail.com> Oded has agreed to remove the dma-fence usage, since they really don't need it (and all the baggage that comes with it), plain old completion is enough for their use. This use is also why I added the regex to MAINTAINERS, so that in the future we can catch people who try to use dma_fence because it looks cute and useful, and are completely oblivious to all the pain and headaches involved. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From martin.peres at intel.com Wed Jun 17 08:29:10 2020 From: martin.peres at intel.com (Peres, Martin) Date: Wed, 17 Jun 2020 08:29:10 +0000 Subject: [Intel-gfx] [CI] Pre-merge testing disabled References: <c80cb85e77c74b949ab75778b330494b@intel.com> Message-ID: <91072193e4654296924cd9ca13463da8@intel.com> On 2020-06-16 12:37, Peres, Martin wrote: > Hello world, > > Due to changes in our global data policy rules, the bucket used to store > the CI results became private, which prevents us from providing any > testing result. > > We have received a notice on Sunday about this change, notified them on > Monday that we wanted to keep our storage public and ended up on Tuesday > with a private bucket. > > We are working as fast as possible to address this, but we cannot give > any ETA. We'll be updating you in this thread. > > Sorry for the inconvenience, > Martin Thanks to Tomi Sarvela for his efforts, it's back! Sorry again for the inconvenience! Martin -------------- next part -------------- A non-text attachment was scrubbed... Name: pEpkey.asc Type: application/pgp-keys Size: 1765 bytes Desc: pEpkey.asc URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200617/52d68bcb/attachment.key> From colin.king at canonical.com Wed Jun 17 08:52:07 2020 From: colin.king at canonical.com (Colin King) Date: Wed, 17 Jun 2020 09:52:07 +0100 Subject: [Intel-gfx] [PATCH][next] drm/i915/selftests: fix spelling mistake "submited" -> "submitted" Message-ID: <20200617085207.167552-1-colin.king@canonical.com> From: Colin Ian King <colin.king at canonical.com> There is a spelling mistake in a pr_err message. Fix it. Signed-off-by: Colin Ian King <colin.king at canonical.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index b8b7b91019f4..547edf3d902b 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -482,7 +482,7 @@ static int live_unlite_ring(void *arg) err = wait_for_submit(engine, rq, HZ / 2); i915_request_put(rq); if (err) { - pr_err("%s: preemption request was not submited\n", + pr_err("%s: preemption request was not submitted\n", engine->name); err = -ETIME; } -- 2.27.0.rc0 From patchwork at emeril.freedesktop.org Wed Jun 17 09:08:06 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 09:08:06 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgbGlu?= =?utf-8?q?ux-next=3A_build_failure_after_merge_of_the_drm-misc_tree?= In-Reply-To: <20200617105929.534edd34@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> Message-ID: <159238488609.29977.1316223417165602523@emeril.freedesktop.org> == Series Details == Series: linux-next: build failure after merge of the drm-misc tree URL : https://patchwork.freedesktop.org/series/78444/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8638_full -> Patchwork_17974_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17974_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17974_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17974_full: ### IGT changes ### #### Possible regressions #### * igt at kms_flip@basic-plain-flip at c-hdmi-a1: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-hsw6/igt at kms_flip@basic-plain-flip at c-hdmi-a1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-hsw2/igt at kms_flip@basic-plain-flip at c-hdmi-a1.html Known issues ------------ Here are the changes found in Patchwork_17974_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at bcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * igt at gem_ctx_persistence@engines-mixed-process at rcs0: - shard-apl: [PASS][5] -> [FAIL][6] ([i915#1528]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl3/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl6/igt at gem_ctx_persistence@engines-mixed-process at rcs0.html * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [PASS][7] -> [FAIL][8] ([i915#1528]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl5/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl5/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [PASS][9] -> [INCOMPLETE][10] ([i915#82]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-snb4/igt at gem_exec_schedule@implicit-write-read at rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-glk2/igt at gem_exec_whisper@basic-contexts-priority-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-glk2/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_userptr_blits@userfault: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl2/igt at gem_userptr_blits@userfault.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl7/igt at gem_userptr_blits@userfault.html * igt at i915_suspend@forcewake: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#636] / [i915#69]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl7/igt at i915_suspend@forcewake.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl5/igt at i915_suspend@forcewake.html * igt at kms_ccs@pipe-b-missing-ccs-buffer: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#165]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl3/igt at kms_ccs@pipe-b-missing-ccs-buffer.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl2/igt at kms_ccs@pipe-b-missing-ccs-buffer.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl4/igt at kms_flip_tiling@flip-changes-tiling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl6/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][21] -> [DMESG-FAIL][22] ([i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl6/igt at kms_flip_tiling@flip-changes-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-glk6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-glk9/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_cursor@pipe-b-overlay-size-256: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#95]) +22 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl8/igt at kms_plane_cursor@pipe-b-overlay-size-256.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl4/igt at kms_plane_cursor@pipe-b-overlay-size-256.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb3/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-b-wait-busy-hang: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl1/igt at kms_vblank@pipe-b-wait-busy-hang.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl1/igt at kms_vblank@pipe-b-wait-busy-hang.html * igt at perf_pmu@module-unload: - shard-iclb: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb6/igt at perf_pmu@module-unload.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb5/igt at perf_pmu@module-unload.html #### Possible fixes #### * igt at core_getstats: - shard-kbl: [DMESG-WARN][35] ([i915#93] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl2/igt at core_getstats.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl7/igt at core_getstats.html * igt at gem_ctx_persistence@engines-hostile at vcs0: - shard-tglb: [FAIL][37] ([i915#1622]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-tglb1/igt at gem_ctx_persistence@engines-hostile at vcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-tglb3/igt at gem_ctx_persistence@engines-hostile at vcs0.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [INCOMPLETE][39] ([i915#82]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-snb5/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_mmap@basic: - shard-iclb: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb3/igt at gem_mmap@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb1/igt at gem_mmap@basic.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [DMESG-WARN][43] ([i915#95]) -> [PASS][44] +13 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl1/igt at gem_mmap_wc@write-cpu-read-wc.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl2/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at gem_shrink@reclaim: - shard-hsw: [SKIP][45] ([fdo#109271]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-hsw1/igt at gem_shrink@reclaim.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-hsw4/igt at gem_shrink@reclaim.html * igt at i915_query@query-topology-kernel-writes: - shard-apl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl4/igt at i915_query@query-topology-kernel-writes.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl7/igt at i915_query@query-topology-kernel-writes.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-tglb: [DMESG-WARN][49] ([i915#402]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-tglb5/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-tglb3/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [FAIL][51] ([i915#46]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl7/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc: - shard-tglb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-iclb7/igt at kms_psr@psr2_cursor_blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html * igt at kms_psr@suspend: - shard-skl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +6 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl6/igt at kms_psr@suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl8/igt at kms_psr@suspend.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [INCOMPLETE][61] ([i915#69]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl8/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl9/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +3 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html #### Warnings #### * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][65] ([i915#1319]) -> [TIMEOUT][66] ([i915#1319] / [i915#1958]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-kbl1/igt at kms_content_protection@lic.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-kbl6/igt at kms_content_protection@lic.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [FAIL][67] ([i915#1525]) -> [DMESG-FAIL][68] ([i915#95]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-apl2/igt at kms_fbcon_fbt@fbc-suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-apl6/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [FAIL][69] ([i915#79]) -> [DMESG-WARN][70] ([i915#1982]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-suspend at a-edp1: - shard-skl: [DMESG-WARN][71] ([i915#1982]) -> [INCOMPLETE][72] ([i915#198]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl9/igt at kms_flip@flip-vs-suspend at a-edp1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl2/igt at kms_flip@flip-vs-suspend at a-edp1.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1622]: https://gitlab.freedesktop.org/drm/intel/issues/1622 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8638 -> Patchwork_17974 CI-20190529: 20190529 CI_DRM_8638: 83818e4910cac8b84d8f915c773ab3f55fa30365 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17974: 5bf216c35bb20d8eed4b272e9d273906b8a2e514 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17974/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 09:14:10 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 09:14:10 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgUmVt?= =?utf-8?q?aining_RKL_patches_=28rev6=29?= In-Reply-To: <20200617033100.4044428-1-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> Message-ID: <159238525090.29979.9868252764534719538@emeril.freedesktop.org> == Series Details == Series: Remaining RKL patches (rev6) URL : https://patchwork.freedesktop.org/series/77971/ State : success == Summary == CI Bug Log - changes from CI_DRM_8638_full -> Patchwork_17975_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17975/index.html Changes ------- No changes found Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_8638 -> Patchwork_17975 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_8638: 83818e4910cac8b84d8f915c773ab3f55fa30365 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17975: a03fa5993eeac9c31bbf8ab3b6c79ac7f4b6e4d7 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17975/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 09:20:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 09:20:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_fix_spelling_mistake_=22submited=22_-=3E_=22?= =?utf-8?q?submitted=22?= In-Reply-To: <20200617085207.167552-1-colin.king@canonical.com> References: <20200617085207.167552-1-colin.king@canonical.com> Message-ID: <159238565180.29980.13348201854943837131@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: fix spelling mistake "submited" -> "submitted" URL : https://patchwork.freedesktop.org/series/78459/ State : success == Summary == CI Bug Log - changes from CI_DRM_8638_full -> Patchwork_17977_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/index.html Changes ------- No changes found Participating hosts (11 -> 8) ------------------------------ Missing (3): pig-skl-6260u pig-glk-j5005 pig-icl-1065g7 Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_8638 -> Patchwork_17977 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_8638: 83818e4910cac8b84d8f915c773ab3f55fa30365 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17977: 6958b3f61f8d73e5e03b775d9a569529c210a750 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 09:29:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 09:29:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_fix_spelling_mistake_=22submited=22_-=3E_=22?= =?utf-8?q?submitted=22?= In-Reply-To: <20200617085207.167552-1-colin.king@canonical.com> References: <20200617085207.167552-1-colin.king@canonical.com> Message-ID: <159238617925.29979.11143259640536375277@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: fix spelling mistake "submited" -> "submitted" URL : https://patchwork.freedesktop.org/series/78459/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8638 -> Patchwork_17977 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17977 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17977, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17977: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-icl-y/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-icl-y/igt at i915_selftest@live at execlists.html Known issues ------------ Here are the changes found in Patchwork_17977 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1242]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at active: - fi-icl-y: [DMESG-FAIL][13] ([i915#765]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-icl-y/igt at i915_selftest@live at active.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-icl-y/igt at i915_selftest@live at active.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8638/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (47 -> 41) ------------------------------ Additional (1): fi-snb-2520m Missing (7): fi-ilk-m540 fi-tgl-u2 fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8638 -> Patchwork_17977 CI-20190529: 20190529 CI_DRM_8638: 83818e4910cac8b84d8f915c773ab3f55fa30365 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17977: 6958b3f61f8d73e5e03b775d9a569529c210a750 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6958b3f61f8d drm/i915/selftests: fix spelling mistake "submited" -> "submitted" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17977/index.html From daniel at ffwll.ch Wed Jun 17 09:58:10 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 17 Jun 2020 11:58:10 +0200 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> Message-ID: <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote: > Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: > > Add enable/disable flip done functions and the flip done handler > > function which handles the flip done interrupt. > > > > Enable the flip done interrupt in IER. > > > > Enable flip done function is called before writing the > > surface address register as the write to this register triggers > > the flip done interrupt > > > > Flip done handler is used to send the page flip event as soon as the > > surface address is written as per the requirement of async flips. > > The interrupt is disabled after the event is sent. > > > > v2: -Change function name from icl_* to skl_* (Paulo) > > -Move flip handler to this patch (Paulo) > > -Remove vblank_put() (Paulo) > > -Enable flip done interrupt for gen9+ only (Paulo) > > -Enable flip done interrupt in power_well_post_enable hook (Paulo) > > -Removed the event check in flip done handler to handle async > > flips without pageflip events. > > > > v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) > > -Make the pending vblank event NULL in the begining of > > flip_done_handler to remove sporadic WARN_ON that is seen. > > > > Signed-off-by: Karthik B S <karthik.b.s at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ > > drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ > > drivers/gpu/drm/i915/i915_irq.h | 2 + > > 3 files changed, 64 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index f40b909952cc..48cc1fc9bc5a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > > > intel_dbuf_pre_plane_update(state); > > > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > + if (new_crtc_state->uapi.async_flip) { > > + skl_enable_flip_done(&crtc->base); > > + break; > > + } > > + } > > + > > /* Now enable the clocks, plane, pipe, and connectors that we set up. */ > > dev_priv->display.commit_modeset_enables(state); > > > > @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > drm_atomic_helper_wait_for_flip_done(dev, &state->base); > > > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > + if (new_crtc_state->uapi.async_flip) > > + skl_disable_flip_done(&crtc->base); > > + > > if (new_crtc_state->hw.active && > > !needs_modeset(new_crtc_state) && > > !new_crtc_state->preload_luts && > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index efdd4c7b8e92..632e7b1deb87 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > > u32 crc4) {} > > #endif > > > > +static void flip_done_handler(struct drm_i915_private *dev_priv, > > + unsigned int pipe) > > +{ > > + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); > > + struct drm_crtc_state *crtc_state = crtc->base.state; > > + struct drm_pending_vblank_event *e = crtc_state->event; > > + struct drm_device *dev = &dev_priv->drm; > > + unsigned long irqflags; > > + > > + crtc_state->event = NULL; > > + > > + spin_lock_irqsave(&dev->event_lock, irqflags); > > + > > + drm_crtc_send_vblank_event(&crtc->base, e); > > I don't think this is what we want. With this, the events the Kernel > sends us all have the same sequence and timestamp. In fact, the IGT > test you submitted fails because of this. > > In my original hackish proof-of-concept patch I had changed > drm_update_vblank_count() to force diff=1 in order to always send > events and I also changed g4x_get_vblank_counter() to get the counter > from FLIPCOUNT (which updates every time there's a flip) instead of > FRMCOUNT (which doesn't seem to increment when you do async flips). > That is a drastic change, but the patch was just a PoC so I didn't care > about keeping anything else working. > > One thing that confused me a little bit when dealing the the > vblank/flip event interface from drm.ko is that "flips" and "vblanks" > seem to be changed interchangeably, which is confusing for async flips: > if you keep forever doing async flips in the very first few scanlines > you never actually reach the "vblank" period, yet you keep flipping > your frame. Then, what should your expectation regarding events be? Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR where that changes), no idea why we can't keep sending out vblank interrupts. Now flip events look maybe conflated in drm.ko code with vblank events since most of the time a flip complete happens at exactly the same time the vblank event. But for async flip this is not the case. Probably worth it to have new helpers/function in drm_vblank.c for async flips, so that this is less confusing. Plus good documentation. > I think we may need to check how the other drivers handle async vblanks > (or how drm.ko wants us to handle async vblanks). Should we increment > sequence on every async flip? What about the timestamp? > > Daniel, Ville, do you happen to know the proper semantics here? > > There's certainly some adjustment to do to both this patch and the IGT. I think it would be really good if we cc dri-devel on this. amdgpu.ko is currently the only implementation of async flips, we need to make sure we are fully aligned on all the semantic details. That also means that the igt needs to be reviewed and tested by amdgpu people. Might also be good to get the implementation acked by amd DC people, just to make triple-sure we have the same semantics and generic userspace compositors like mutter can use this across drivers. We've had way too much pain here in the past, especially with the details you point out here. Also, I think we need to have updated drm core documentation for async flips, since the current ones are "do it like amdgpu does it". I think just documenting the various pieces and flags in detail and how it all interacts with e.g. other atomic commits and everything else would be great. Harry and Nicholaus are the people you want from amd. Added everyone to cc. -Daniel > > > + > > + spin_unlock_irqrestore(&dev->event_lock, irqflags); > > +} > > > > static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > > enum pipe pipe) > > @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > > if (iir & GEN8_PIPE_VBLANK) > > intel_handle_vblank(dev_priv, pipe); > > > > + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) > > + flip_done_handler(dev_priv, pipe); > > + > > if (iir & GEN8_PIPE_CDCLK_CRC_DONE) > > hsw_pipe_crc_irq_handler(dev_priv, pipe); > > > > @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) > > return 0; > > } > > > > +void skl_enable_flip_done(struct drm_crtc *crtc) > > +{ > > + struct drm_i915_private *dev_priv = to_i915(crtc->dev); > > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > > + unsigned long irqflags; > > + > > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > > + > > + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); > > + > > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > > +} > > + > > /* Called from drm generic code, passed 'crtc' which > > * we use as a pipe index > > */ > > @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) > > spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > > } > > > > +void skl_disable_flip_done(struct drm_crtc *crtc) > > +{ > > + struct drm_i915_private *dev_priv = to_i915(crtc->dev); > > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > > + unsigned long irqflags; > > + > > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > > + > > + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); > > + > > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > > +} > > + > > static void ibx_irq_reset(struct drm_i915_private *dev_priv) > > { > > struct intel_uncore *uncore = &dev_priv->uncore; > > @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > > u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; > > enum pipe pipe; > > > > + if (INTEL_GEN(dev_priv) >= 9) > > + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; > > + > > spin_lock_irq(&dev_priv->irq_lock); > > > > if (!intel_irqs_enabled(dev_priv)) { > > @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > > de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | > > GEN8_PIPE_FIFO_UNDERRUN; > > > > + if (INTEL_GEN(dev_priv) >= 9) > > + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; > > + > > de_port_enables = de_port_masked; > > if (IS_GEN9_LP(dev_priv)) > > de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; > > diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h > > index 25f25cd95818..2f10c8135116 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.h > > +++ b/drivers/gpu/drm/i915/i915_irq.h > > @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); > > int i965_enable_vblank(struct drm_crtc *crtc); > > int ilk_enable_vblank(struct drm_crtc *crtc); > > int bdw_enable_vblank(struct drm_crtc *crtc); > > +void skl_enable_flip_done(struct drm_crtc *crtc); > > void i8xx_disable_vblank(struct drm_crtc *crtc); > > void i915gm_disable_vblank(struct drm_crtc *crtc); > > void i965_disable_vblank(struct drm_crtc *crtc); > > void ilk_disable_vblank(struct drm_crtc *crtc); > > void bdw_disable_vblank(struct drm_crtc *crtc); > > +void skl_disable_flip_done(struct drm_crtc *crtc); > > > > void gen2_irq_reset(struct intel_uncore *uncore); > > void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From anshuman.gupta at intel.com Wed Jun 17 09:50:01 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Wed, 17 Jun 2020 15:20:01 +0530 Subject: [Intel-gfx] [PATCH] drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs Message-ID: <20200617095001.19220-1-anshuman.gupta@intel.com> Debug print for power domain audio get/put. This will help to deubg the CI s2idle incomplete failures. Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com> --- drivers/gpu/drm/i915/display/intel_audio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index ad4aa66fd676..145afd2f1d4a 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -1012,6 +1012,7 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) /* Catch potential impedance mismatches before they occur! */ BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); + drm_dbg_kms(&dev_priv->drm, "get audio power domian power\n"); ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); if (dev_priv->audio_power_refcount++ == 0) { @@ -1045,6 +1046,7 @@ static void i915_audio_component_put_power(struct device *kdev, if (IS_GEMINILAKE(dev_priv)) glk_force_audio_cdclk(dev_priv, false); + drm_dbg_kms(&dev_priv->drm, "put audio power domian power\n"); intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie); } -- 2.26.2 From chris at chris-wilson.co.uk Wed Jun 17 10:12:12 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 11:12:12 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs In-Reply-To: <20200617095001.19220-1-anshuman.gupta@intel.com> References: <20200617095001.19220-1-anshuman.gupta@intel.com> Message-ID: <159238873248.19488.1166033909635410870@build.alporthouse.com> Quoting Anshuman Gupta (2020-06-17 10:50:01) > Debug print for power domain audio get/put. > This will help to deubg the CI s2idle incomplete > failures. Do we not already print the mismatching pm, and who we are unable to find a corresponding release for? -Chris From anshuman.gupta at intel.com Wed Jun 17 10:17:15 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Wed, 17 Jun 2020 15:47:15 +0530 Subject: [Intel-gfx] [PATCH] drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs In-Reply-To: <159238873248.19488.1166033909635410870@build.alporthouse.com> References: <20200617095001.19220-1-anshuman.gupta@intel.com> <159238873248.19488.1166033909635410870@build.alporthouse.com> Message-ID: <20200617101714.GM14085@intel.com> On 2020-06-17 at 11:12:12 +0100, Chris Wilson wrote: > Quoting Anshuman Gupta (2020-06-17 10:50:01) > > Debug print for power domain audio get/put. > > This will help to deubg the CI s2idle incomplete > > failures. > > Do we not already print the mismatching pm, and who we are unable to > find a corresponding release for? Thanks Chris for review comment, Yes it is there, but POWER_DOMAIN_AUDIO get/put request initiated by snd_audio along with i915. So in order to confirm if it is a bug from snd_audio module we would require to track the get/put resuest from snd_audio. Thanks, Anshuman Gupta. > -Chris From chris at chris-wilson.co.uk Wed Jun 17 10:46:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 11:46:16 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs In-Reply-To: <20200617101714.GM14085@intel.com> References: <20200617095001.19220-1-anshuman.gupta@intel.com> <159238873248.19488.1166033909635410870@build.alporthouse.com> <20200617101714.GM14085@intel.com> Message-ID: <159239077681.19488.15781759768532189029@build.alporthouse.com> Quoting Anshuman Gupta (2020-06-17 11:17:15) > On 2020-06-17 at 11:12:12 +0100, Chris Wilson wrote: > > Quoting Anshuman Gupta (2020-06-17 10:50:01) > > > Debug print for power domain audio get/put. > > > This will help to deubg the CI s2idle incomplete > > > failures. > > > > Do we not already print the mismatching pm, and who we are unable to > > find a corresponding release for? > Thanks Chris for review comment, > Yes it is there, but POWER_DOMAIN_AUDIO get/put request initiated by > snd_audio along with i915. So in order to confirm if it is a bug from > snd_audio module we would require to track the get/put resuest from > snd_audio. But we are, see the cookie. -Chris From chris at chris-wilson.co.uk Wed Jun 17 11:13:09 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 12:13:09 +0100 Subject: [Intel-gfx] [CI] drm/i915/selftests: Enable selftesting of busy-stats Message-ID: <20200617111309.28218-1-chris@chris-wilson.co.uk> A couple of very simple tests to ensure that the basic properties of per-engine busyness accounting [0% and 100% busy] are faithful. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 94 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 ++ 2 files changed, 99 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..cd435b7b7731 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,99 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t de; + u64 dt; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (de < 0 || de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + /* 100% busy */ + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + break; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + break; + } + + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (100 * de < 95 * dt || 95 * de > 100 * dt) { + pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + err = -EINVAL; + break; + } + + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + igt_spinner_fini(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +170,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From patchwork at emeril.freedesktop.org Wed Jun 17 11:22:45 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 11:22:45 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_POWER=5FDOMAIN=5FAUDIO_ref-count_debug_logs?= In-Reply-To: <20200617095001.19220-1-anshuman.gupta@intel.com> References: <20200617095001.19220-1-anshuman.gupta@intel.com> Message-ID: <159239296588.29978.6831854246283855318@emeril.freedesktop.org> == Series Details == Series: drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs URL : https://patchwork.freedesktop.org/series/78463/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17978 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/index.html Known issues ------------ Here are the changes found in Patchwork_17978 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_parallel@engines at fds: - fi-icl-guc: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at gem_exec_parallel@engines at fds.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/fi-icl-guc/igt at gem_exec_parallel@engines at fds.html #### Possible fixes #### * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][3] ([i915#1233]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - {fi-tgl-dsi}: [INCOMPLETE][7] -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569 [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192 [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193 [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17978 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17978: 1627afde2cc088538b87890cc69618233ba9e679 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1627afde2cc0 drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 11:26:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 11:26:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/selftests=3A_Enable_selftesting_of_busy-stats?= In-Reply-To: <20200617111309.28218-1-chris@chris-wilson.co.uk> References: <20200617111309.28218-1-chris@chris-wilson.co.uk> Message-ID: <159239321270.29980.15593221339120888923@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78465/ State : warning == Summary == $ dim checkpatch origin/drm-tip 053cd0314edc drm/i915/selftests: Enable selftesting of busy-stats -:59: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #59: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:48: + udelay(100); -:90: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #90: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:79: + udelay(100); total: 0 errors, 0 warnings, 2 checks, 117 lines checked From patchwork at emeril.freedesktop.org Wed Jun 17 11:48:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 11:48:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Enable_selftesting_of_busy-stats?= In-Reply-To: <20200617111309.28218-1-chris@chris-wilson.co.uk> References: <20200617111309.28218-1-chris@chris-wilson.co.uk> Message-ID: <159239452621.29979.3454315303828282369@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78465/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17979 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17979 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17979, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17979: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_engines: - fi-kbl-soraka: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-soraka/igt at i915_selftest@live at gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-kbl-soraka/igt at i915_selftest@live at gt_engines.html - fi-icl-y: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-y/igt at i915_selftest@live at gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-icl-y/igt at i915_selftest@live at gt_engines.html - fi-cml-s: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-cml-s/igt at i915_selftest@live at gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-cml-s/igt at i915_selftest@live at gt_engines.html Known issues ------------ Here are the changes found in Patchwork_17979 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_selftest@live at gt_contexts: - fi-snb-2520m: [PASS][7] -> [DMESG-FAIL][8] ([i915#541]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-snb-2520m/igt at i915_selftest@live at gt_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-snb-2520m/igt at i915_selftest@live at gt_contexts.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_busy@basic at flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - {fi-tgl-dsi}: [INCOMPLETE][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +3 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17979 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17979: 053cd0314edcc7661369b14b811a0eea29d433b4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 053cd0314edc drm/i915/selftests: Enable selftesting of busy-stats == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17979/index.html From chris at chris-wilson.co.uk Wed Jun 17 12:12:11 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 13:12:11 +0100 Subject: [Intel-gfx] [CI] drm/i915/selftests: Enable selftesting of busy-stats Message-ID: <20200617121211.32198-1-chris@chris-wilson.co.uk> A couple of very simple tests to ensure that the basic properties of per-engine busyness accounting [0% and 100% busy] are faithful. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 102 +++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 5 + 2 files changed, 107 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..92278d92e7b0 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -7,6 +7,107 @@ #include "i915_selftest.h" #include "selftest_engine.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t de; + u64 dt; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + engine_heartbeat_disable(engine); + + ENGINE_TRACE(engine, "measuring idle time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (de < 0 || de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + + /* 100% busy */ + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto end; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + goto end; + } + + ENGINE_TRACE(engine, "measuring busy time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (100 * de < 95 * dt || 95 * de > 100 * dt) { + pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + +end: + engine_heartbeat_enable(engine); + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +178,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..5e364fb31aea 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -1252,6 +1252,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 12:25:19 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 13:25:19 +0100 Subject: [Intel-gfx] [CI] drm/i915/selftests: Enable selftesting of busy-stats Message-ID: <20200617122519.32765-1-chris@chris-wilson.co.uk> A couple of very simple tests to ensure that the basic properties of per-engine busyness accounting [0% and 100% busy] are faithful. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- .../drm/i915/gt/selftest_engine_heartbeat.c | 47 ++++---- .../drm/i915/gt/selftest_engine_heartbeat.h | 15 +++ drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 103 ++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 29 ++--- drivers/gpu/drm/i915/gt/selftest_lrc.c | 79 ++++++-------- drivers/gpu/drm/i915/gt/selftest_rps.c | 68 +++++------- drivers/gpu/drm/i915/gt/selftest_timeline.c | 21 +--- drivers/gpu/drm/i915/selftests/i915_request.c | 21 +--- 8 files changed, 213 insertions(+), 170 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 697114dd1f47..f3034c613bc0 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -10,6 +10,7 @@ #include "intel_gt_requests.h" #include "i915_selftest.h" +#include "selftest_engine_heartbeat.h" static int timeline_sync(struct intel_timeline *tl) { @@ -142,24 +143,6 @@ static int __live_idle_pulse(struct intel_engine_cs *engine, return err; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine, - unsigned long *saved) -{ - *saved = engine->props.heartbeat_interval_ms; - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine, - unsigned long saved) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = saved; -} - static int live_idle_flush(void *arg) { struct intel_gt *gt = arg; @@ -170,11 +153,9 @@ static int live_idle_flush(void *arg) /* Check that we can flush the idle barriers */ for_each_engine(engine, gt, id) { - unsigned long heartbeat; - - engine_heartbeat_disable(engine, &heartbeat); + st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_flush_barriers); - engine_heartbeat_enable(engine, heartbeat); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -192,11 +173,9 @@ static int live_idle_pulse(void *arg) /* Check that heartbeat pulses flush the idle barriers */ for_each_engine(engine, gt, id) { - unsigned long heartbeat; - - engine_heartbeat_disable(engine, &heartbeat); + st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_pulse); - engine_heartbeat_enable(engine, heartbeat); + st_engine_heartbeat_enable(engine); if (err && err != -ENODEV) break; @@ -394,3 +373,19 @@ int intel_heartbeat_live_selftests(struct drm_i915_private *i915) i915_modparams.enable_hangcheck = saved_hangcheck; return err; } + +void st_engine_heartbeat_disable(struct intel_engine_cs *engine) +{ + engine->props.heartbeat_interval_ms = 0; + + intel_engine_pm_get(engine); + intel_engine_park_heartbeat(engine); +} + +void st_engine_heartbeat_enable(struct intel_engine_cs *engine) +{ + intel_engine_pm_put(engine); + + engine->props.heartbeat_interval_ms = + engine->defaults.heartbeat_interval_ms; +} diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h new file mode 100644 index 000000000000..fb92d2b0f36e --- /dev/null +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h @@ -0,0 +1,15 @@ + +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef SELFTEST_ENGINE_HEARTBEAT_H +#define SELFTEST_ENGINE_HEARTBEAT_H + +struct intel_engine_cs; + +void st_engine_heartbeat_disable(struct intel_engine_cs *engine); +void st_engine_heartbeat_enable(struct intel_engine_cs *engine); + +#endif /* SELFTEST_ENGINE_HEARTBEAT_H */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..dd54dcb5cca2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -6,7 +6,109 @@ #include "i915_selftest.h" #include "selftest_engine.h" +#include "selftest_engine_heartbeat.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t de; + u64 dt; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + st_engine_heartbeat_disable(engine); + + ENGINE_TRACE(engine, "measuring idle time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (de < 0 || de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + + /* 100% busy */ + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto end; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + goto end; + } + + ENGINE_TRACE(engine, "measuring busy time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (100 * de < 95 * dt || 95 * de > 100 * dt) { + pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + +end: + st_engine_heartbeat_enable(engine); + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +179,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 7461936d549d..fb5ebf930ab2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -29,6 +29,7 @@ #include "intel_gt.h" #include "intel_engine_heartbeat.h" #include "intel_engine_pm.h" +#include "selftest_engine_heartbeat.h" #include "i915_selftest.h" #include "selftests/i915_random.h" @@ -310,22 +311,6 @@ static bool wait_until_running(struct hang *h, struct i915_request *rq) 1000)); } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int igt_hang_sanitycheck(void *arg) { struct intel_gt *gt = arg; @@ -482,7 +467,7 @@ static int igt_reset_nop_engine(void *arg) reset_engine_count = i915_reset_engine_count(global, engine); count = 0; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { int i; @@ -540,7 +525,7 @@ static int igt_reset_nop_engine(void *arg) } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s(%s): %d resets\n", __func__, engine->name, count); @@ -590,7 +575,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) reset_count = i915_reset_count(global); reset_engine_count = i915_reset_engine_count(global, engine); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { if (active) { @@ -642,7 +627,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; @@ -841,7 +826,7 @@ static int __igt_reset_engines(struct intel_gt *gt, yield(); /* start all threads before we begin */ - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { struct i915_request *rq = NULL; @@ -931,7 +916,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("i915_reset_engine(%s:%s): %lu resets\n", engine->name, test_name, count); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 4f3758a1cbcf..7f27088ded55 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -9,6 +9,7 @@ #include "gem/i915_gem_pm.h" #include "gt/intel_engine_heartbeat.h" #include "gt/intel_reset.h" +#include "gt/selftest_engine_heartbeat.h" #include "i915_selftest.h" #include "selftests/i915_random.h" @@ -51,22 +52,6 @@ static struct i915_vma *create_scratch(struct intel_gt *gt) return vma; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static bool is_active(struct i915_request *rq) { if (i915_request_is_active(rq)) @@ -234,7 +219,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) err = -EIO; break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n < ARRAY_SIZE(ce); n++) { struct intel_context *tmp; @@ -342,7 +327,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) intel_context_put(ce[n]); } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_live_test_end(&t)) err = -EIO; if (err) @@ -396,7 +381,7 @@ static int live_unlite_ring(void *arg) err = -EIO; break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n < ARRAY_SIZE(ce); n++) { struct intel_context *tmp; @@ -502,7 +487,7 @@ static int live_unlite_ring(void *arg) intel_context_unpin(ce[n]); intel_context_put(ce[n]); } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_live_test_end(&t)) err = -EIO; if (err) @@ -621,7 +606,7 @@ static int live_hold_reset(void *arg) break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK); if (IS_ERR(rq)) { @@ -681,7 +666,7 @@ static int live_hold_reset(void *arg) i915_request_put(rq); out: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_context_put(ce); if (err) break; @@ -728,7 +713,7 @@ static int live_error_interrupt(void *arg) const struct error_phase *p; int err = 0; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (p = phases; p->error[0] != GOOD; p++) { struct i915_request *client[ARRAY_SIZE(phases->error)]; @@ -827,7 +812,7 @@ static int live_error_interrupt(void *arg) } } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) { intel_gt_set_wedged(gt); return err; @@ -1042,9 +1027,9 @@ static int live_timeslice_preempt(void *arg) memset(vaddr, 0, PAGE_SIZE); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = slice_semaphore_queue(engine, vma, 5); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto err_pin; @@ -1166,7 +1151,7 @@ static int live_timeslice_rewind(void *arg) * Expect execution/evaluation order XZY */ - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); timeslice = xchg(&engine->props.timeslice_duration_ms, 1); slot = memset32(engine->status_page.addr + 1000, 0, 4); @@ -1261,7 +1246,7 @@ static int live_timeslice_rewind(void *arg) wmb(); engine->props.timeslice_duration_ms = timeslice; - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); for (i = 0; i < 3; i++) i915_request_put(rq[i]); if (igt_flush_test(gt->i915)) @@ -1353,7 +1338,7 @@ static int live_timeslice_queue(void *arg) if (!intel_engine_has_preemption(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); memset(vaddr, 0, PAGE_SIZE); /* ELSP[0]: semaphore wait */ @@ -1414,7 +1399,7 @@ static int live_timeslice_queue(void *arg) err_rq: i915_request_put(rq); err_heartbeat: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -1460,7 +1445,7 @@ static int live_timeslice_nopreempt(void *arg) break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); timeslice = xchg(&engine->props.timeslice_duration_ms, 1); /* Create an unpreemptible spinner */ @@ -1529,7 +1514,7 @@ static int live_timeslice_nopreempt(void *arg) igt_spinner_end(&spin); out_heartbeat: xchg(&engine->props.timeslice_duration_ms, timeslice); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; @@ -2433,7 +2418,7 @@ static int live_suppress_self_preempt(void *arg) if (igt_flush_test(gt->i915)) goto err_wedged; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); engine->execlists.preempt_hang.count = 0; rq_a = spinner_create_request(&a.spin, @@ -2441,14 +2426,14 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_a)) { err = PTR_ERR(rq_a); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_a); if (!igt_wait_for_spinner(&a.spin, rq_a)) { pr_err("First client failed to start\n"); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_wedged; } @@ -2460,7 +2445,7 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_b)) { err = PTR_ERR(rq_b); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_b); @@ -2471,7 +2456,7 @@ static int live_suppress_self_preempt(void *arg) if (!igt_wait_for_spinner(&b.spin, rq_b)) { pr_err("Second client failed to start\n"); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_wedged; } @@ -2485,12 +2470,12 @@ static int live_suppress_self_preempt(void *arg) engine->name, engine->execlists.preempt_hang.count, depth); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = -EINVAL; goto err_client_b; } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) goto err_wedged; } @@ -2902,7 +2887,7 @@ static int live_preempt_ring(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n <= 3; n++) { err = __live_preempt_ring(engine, &spin, @@ -2911,7 +2896,7 @@ static int live_preempt_ring(void *arg) break; } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -4568,7 +4553,7 @@ static int reset_virtual_engine(struct intel_gt *gt, } for (n = 0; n < nsibling; n++) - engine_heartbeat_disable(siblings[n]); + st_engine_heartbeat_disable(siblings[n]); rq = igt_spinner_create_request(&spin, ve, MI_ARB_CHECK); if (IS_ERR(rq)) { @@ -4639,7 +4624,7 @@ static int reset_virtual_engine(struct intel_gt *gt, i915_request_put(rq); out_heartbeat: for (n = 0; n < nsibling; n++) - engine_heartbeat_enable(siblings[n]); + st_engine_heartbeat_enable(siblings[n]); intel_context_put(ve); out_spin: @@ -5314,7 +5299,7 @@ static int live_lrc_gpr(void *arg) return PTR_ERR(scratch); for_each_engine(engine, gt, id) { - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = __live_lrc_gpr(engine, scratch, false); if (err) @@ -5325,7 +5310,7 @@ static int live_lrc_gpr(void *arg) goto err; err: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -5474,7 +5459,7 @@ static int live_lrc_timestamp(void *arg) for_each_engine(data.engine, gt, id) { int i, err = 0; - engine_heartbeat_disable(data.engine); + st_engine_heartbeat_disable(data.engine); for (i = 0; i < ARRAY_SIZE(data.ce); i++) { struct intel_context *tmp; @@ -5507,7 +5492,7 @@ static int live_lrc_timestamp(void *arg) } err: - engine_heartbeat_enable(data.engine); + st_engine_heartbeat_enable(data.engine); for (i = 0; i < ARRAY_SIZE(data.ce); i++) { if (!data.ce[i]) break; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..bb753f0c12eb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -12,6 +12,7 @@ #include "intel_gt_clock_utils.h" #include "intel_gt_pm.h" #include "intel_rc6.h" +#include "selftest_engine_heartbeat.h" #include "selftest_rps.h" #include "selftests/igt_flush_test.h" #include "selftests/igt_spinner.h" @@ -20,22 +21,6 @@ /* Try to isolate the impact of cstates from determing frequency response */ #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */ -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static void dummy_rps_work(struct work_struct *wrk) { } @@ -249,13 +234,13 @@ int live_rps_clock_interval(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); if (IS_ERR(rq)) { - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = PTR_ERR(rq); break; } @@ -266,7 +251,7 @@ int live_rps_clock_interval(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -322,7 +307,7 @@ int live_rps_clock_interval(void *arg) intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err == 0) { u64 time = intel_gt_pm_interval_to_ns(gt, cycles); @@ -408,7 +393,7 @@ int live_rps_control(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, @@ -424,7 +409,7 @@ int live_rps_control(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -434,7 +419,7 @@ int live_rps_control(void *arg) pr_err("%s: could not set minimum frequency [%x], only %x!\n", engine->name, rps->min_freq, read_cagf(rps)); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); show_pstate_limits(rps); err = -EINVAL; break; @@ -451,7 +436,7 @@ int live_rps_control(void *arg) pr_err("%s: could not restore minimum frequency [%x], only %x!\n", engine->name, rps->min_freq, read_cagf(rps)); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); show_pstate_limits(rps); err = -EINVAL; break; @@ -466,7 +451,7 @@ int live_rps_control(void *arg) min_dt = ktime_sub(ktime_get(), min_dt); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s: range:[%x:%uMHz, %x:%uMHz] limit:[%x:%uMHz], %x:%x response %lluns:%lluns\n", engine->name, @@ -637,14 +622,14 @@ int live_rps_frequency_cs(void *arg) int freq; } min, max; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); vma = create_spin_counter(engine, engine->kernel_context->vm, false, &cancel, &cntr); if (IS_ERR(vma)) { err = PTR_ERR(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); break; } @@ -725,7 +710,7 @@ int live_rps_frequency_cs(void *arg) i915_vma_unpin(vma); i915_vma_put(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -779,14 +764,14 @@ int live_rps_frequency_srm(void *arg) int freq; } min, max; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); vma = create_spin_counter(engine, engine->kernel_context->vm, true, &cancel, &cntr); if (IS_ERR(vma)) { err = PTR_ERR(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); break; } @@ -866,7 +851,7 @@ int live_rps_frequency_srm(void *arg) i915_vma_unpin(vma); i915_vma_put(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -1061,11 +1046,11 @@ int live_rps_interrupt(void *arg) intel_gt_pm_wait_for_idle(engine->gt); GEM_BUG_ON(intel_rps_is_active(rps)); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = __rps_up_interrupt(rps, engine, &spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto out; @@ -1074,13 +1059,13 @@ int live_rps_interrupt(void *arg) /* Keep the engine awake but idle and check for DOWN */ if (pm_events & GEN6_PM_RP_DOWN_THRESHOLD) { - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); intel_rc6_disable(>->rc6); err = __rps_down_interrupt(rps, engine); intel_rc6_enable(>->rc6); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto out; } @@ -1165,13 +1150,13 @@ int live_rps_power(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); if (IS_ERR(rq)) { - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = PTR_ERR(rq); break; } @@ -1182,7 +1167,7 @@ int live_rps_power(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -1195,7 +1180,7 @@ int live_rps_power(void *arg) min.power = measure_power_at(rps, &min.freq); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n", engine->name, @@ -1252,6 +1237,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index b2aad7ef046a..fcdee951579b 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -12,6 +12,7 @@ #include "intel_gt.h" #include "intel_gt_requests.h" #include "intel_ring.h" +#include "selftest_engine_heartbeat.h" #include "../selftests/i915_random.h" #include "../i915_selftest.h" @@ -751,22 +752,6 @@ static int live_hwsp_wrap(void *arg) return err; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int live_hwsp_rollover_kernel(void *arg) { struct intel_gt *gt = arg; @@ -785,7 +770,7 @@ static int live_hwsp_rollover_kernel(void *arg) struct i915_request *rq[3] = {}; int i; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); if (intel_gt_wait_for_idle(gt, HZ / 2)) { err = -EIO; goto out; @@ -836,7 +821,7 @@ static int live_hwsp_rollover_kernel(void *arg) out: for (i = 0; i < ARRAY_SIZE(rq); i++) i915_request_put(rq[i]); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 92c628f18c60..06d18aae070b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -34,6 +34,7 @@ #include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "gt/intel_gt_requests.h" +#include "gt/selftest_engine_heartbeat.h" #include "i915_random.h" #include "i915_selftest.h" @@ -2270,22 +2271,6 @@ static void rps_unpin(struct intel_gt *gt) atomic_dec(>->rps.num_waiters); } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int perf_request_latency(void *arg) { struct drm_i915_private *i915 = arg; @@ -2311,7 +2296,7 @@ static int perf_request_latency(void *arg) goto out; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rps_pin(engine->gt); if (err == 0) @@ -2330,7 +2315,7 @@ static int perf_request_latency(void *arg) err = measure_completion(ce); rps_unpin(engine->gt); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_context_unpin(ce); intel_context_put(ce); -- 2.20.1 From patchwork at emeril.freedesktop.org Wed Jun 17 12:38:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 12:38:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/selftests=3A_Enable_selftesting_of_busy-stats_=28r?= =?utf-8?q?ev3=29?= In-Reply-To: <20200617122519.32765-1-chris@chris-wilson.co.uk> References: <20200617122519.32765-1-chris@chris-wilson.co.uk> Message-ID: <159239749903.29980.183799686871669907@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Enable selftesting of busy-stats (rev3) URL : https://patchwork.freedesktop.org/series/78465/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6f2bdb806cc4 drm/i915/selftests: Enable selftesting of busy-stats -:99: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #99: new file mode 100644 -:104: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #104: FILE: drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h:1: + -:105: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead #105: FILE: drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h:2: +/* SPDX-License-Identifier: MIT */ -:170: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #170: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:52: + udelay(100); -:203: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #203: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:85: + udelay(100); total: 0 errors, 3 warnings, 2 checks, 862 lines checked From patchwork at emeril.freedesktop.org Wed Jun 17 13:07:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 13:07:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/selftests=3A_Enable_selftesting_of_busy-stats_=28rev3=29?= In-Reply-To: <20200617122519.32765-1-chris@chris-wilson.co.uk> References: <20200617122519.32765-1-chris@chris-wilson.co.uk> Message-ID: <159239924423.29978.7055626577777591496@emeril.freedesktop.org> == Series Details == Series: drm/i915/selftests: Enable selftesting of busy-stats (rev3) URL : https://patchwork.freedesktop.org/series/78465/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17980 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17980 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17980, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17980: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_engines: - fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-soraka/igt at i915_selftest@live at gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-kbl-soraka/igt at i915_selftest@live at gt_engines.html - fi-icl-y: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-y/igt at i915_selftest@live at gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-icl-y/igt at i915_selftest@live at gt_engines.html - fi-cml-s: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-cml-s/igt at i915_selftest@live at gt_engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-cml-s/igt at i915_selftest@live at gt_engines.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at gt_engines: - {fi-tgl-dsi}: NOTRUN -> [INCOMPLETE][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-tgl-dsi/igt at i915_selftest@live at gt_engines.html Known issues ------------ Here are the changes found in Patchwork_17980 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#1242]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-icl-y: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-y/igt at i915_module_load@reload.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-icl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][16] -> [DMESG-WARN][17] ([i915#402]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][18] ([i915#1982]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][20] ([i915#1233]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_busy@basic at flip.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-tgl-dsi}: [DMESG-WARN][24] ([i915#1982]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][26] ([i915#1982]) -> [PASS][27] +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - {fi-tgl-dsi}: [INCOMPLETE][28] -> [PASS][29] [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][30] ([i915#1982]) -> [PASS][31] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][32] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][33] ([i915#62] / [i915#92]) +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][34] ([i915#62] / [i915#92]) -> [DMESG-WARN][35] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17980 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17980: 6f2bdb806cc466e9e38a2b2dfe83ad3b754f4fed @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6f2bdb806cc4 drm/i915/selftests: Enable selftesting of busy-stats == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17980/index.html From chris at chris-wilson.co.uk Wed Jun 17 13:09:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 14:09:16 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Always report the sample time for busy-stats In-Reply-To: <20200617130916.15261-1-chris@chris-wilson.co.uk> References: <20200617130916.15261-1-chris@chris-wilson.co.uk> Message-ID: <20200617130916.15261-2-chris@chris-wilson.co.uk> Return the monotonic timestamp (ktime_get()) at the time of sampling the busy-time. This is used in preference to taking ktime_get() separately before or after the read seqlock as there can be some large variance in reported timestamps. For selftests trying to ascertain that we are reporting accurate to within a few microseconds, even a small delay leads to the test failing. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 ++-- drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 18 +++--- drivers/gpu/drm/i915/i915_pmu.c | 5 +- drivers/gpu/drm/i915/selftests/i915_request.c | 63 ++++++++++++------- 6 files changed, 66 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..a9249a23903a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -334,7 +334,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m, const char *header, ...); -ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine); +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, + ktime_t *now); struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 045179c65c44..c62b3cbdbbf9 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1595,7 +1595,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, intel_engine_print_breadcrumbs(engine, m); } -static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) +static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, + ktime_t *now) { ktime_t total = engine->stats.total; @@ -1603,9 +1604,9 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) * If the engine is executing something at the moment * add it to the total. */ + *now = ktime_get(); if (atomic_read(&engine->stats.active)) - total = ktime_add(total, - ktime_sub(ktime_get(), engine->stats.start)); + total = ktime_add(total, ktime_sub(*now, engine->stats.start)); return total; } @@ -1613,17 +1614,18 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) /** * intel_engine_get_busy_time() - Return current accumulated engine busyness * @engine: engine to report on + * @now: monotonic timestamp of sampling * * Returns accumulated time @engine was busy since engine stats were enabled. */ -ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) { unsigned int seq; ktime_t total; do { seq = read_seqbegin(&engine->stats.lock); - total = __intel_engine_get_busy_time(engine); + total = __intel_engine_get_busy_time(engine, now); } while (read_seqretry(&engine->stats.lock, seq)); return total; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2f59fc6df3c2..bdece932592b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -53,13 +53,13 @@ static void rps_timer(struct timer_list *t) struct intel_engine_cs *engine; enum intel_engine_id id; s64 max_busy[3] = {}; - ktime_t dt, last; + ktime_t dt, timestamp, last; for_each_engine(engine, rps_to_gt(rps), id) { s64 busy; int i; - dt = intel_engine_get_busy_time(engine); + dt = intel_engine_get_busy_time(engine, ×tamp); last = engine->stats.rps; engine->stats.rps = dt; @@ -70,15 +70,14 @@ static void rps_timer(struct timer_list *t) } } - dt = ktime_get(); last = rps->pm_timestamp; - rps->pm_timestamp = dt; + rps->pm_timestamp = timestamp; if (intel_rps_is_active(rps)) { s64 busy; int i; - dt = ktime_sub(dt, last); + dt = ktime_sub(timestamp, last); /* * Our goal is to evaluate each engine independently, so we run diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index dd54dcb5cca2..b08fc5390e8a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -29,8 +29,8 @@ static int live_engine_busy_stats(void *arg) GEM_BUG_ON(intel_gt_pm_is_awake(gt)); for_each_engine(engine, gt, id) { struct i915_request *rq; - ktime_t de; - u64 dt; + ktime_t de, dt; + ktime_t t[2]; if (!intel_engine_supports_stats(engine)) continue; @@ -47,12 +47,11 @@ static int live_engine_busy_stats(void *arg) ENGINE_TRACE(engine, "measuring idle time\n"); preempt_disable(); - dt = ktime_to_ns(ktime_get()); - de = intel_engine_get_busy_time(engine); + de = intel_engine_get_busy_time(engine, &t[0]); udelay(100); - de = ktime_sub(intel_engine_get_busy_time(engine), de); - dt = ktime_to_ns(ktime_get()) - dt; + de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de); preempt_enable(); + dt = ktime_sub(t[1], t[0]); if (de < 0 || de > 10) { pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", engine->name, @@ -80,12 +79,11 @@ static int live_engine_busy_stats(void *arg) ENGINE_TRACE(engine, "measuring busy time\n"); preempt_disable(); - dt = ktime_to_ns(ktime_get()); - de = intel_engine_get_busy_time(engine); + de = intel_engine_get_busy_time(engine, &t[0]); udelay(100); - de = ktime_sub(intel_engine_get_busy_time(engine), de); - dt = ktime_to_ns(ktime_get()) - dt; + de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de); preempt_enable(); + dt = ktime_sub(t[1], t[0]); if (100 * de < 95 * dt || 95 * de > 100 * dt) { pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", engine->name, diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 802837de1767..28bc5f13ae52 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -565,7 +565,10 @@ static u64 __i915_pmu_event_read(struct perf_event *event) /* Do nothing */ } else if (sample == I915_SAMPLE_BUSY && intel_engine_supports_stats(engine)) { - val = ktime_to_ns(intel_engine_get_busy_time(engine)); + ktime_t unused; + + val = ktime_to_ns(intel_engine_get_busy_time(engine, + &unused)); } else { val = engine->pmu.sample[sample].cur; } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 06d18aae070b..9271aad7f779 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -2492,9 +2492,11 @@ static int perf_series_engines(void *arg) intel_engine_pm_get(p->engine); if (intel_engine_supports_stats(p->engine)) - p->busy = intel_engine_get_busy_time(p->engine) + 1; + p->busy = intel_engine_get_busy_time(p->engine, + &p->time) + 1; + else + p->time = ktime_get(); p->runtime = -intel_context_get_total_runtime_ns(ce); - p->time = ktime_get(); } err = (*fn)(ps); @@ -2505,13 +2507,15 @@ static int perf_series_engines(void *arg) struct perf_stats *p = &stats[idx]; struct intel_context *ce = ps->ce[idx]; int integer, decimal; - u64 busy, dt; + u64 busy, dt, now; - p->time = ktime_sub(ktime_get(), p->time); - if (p->busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(p->engine), + if (p->busy) + p->busy = ktime_sub(intel_engine_get_busy_time(p->engine, + &now), p->busy - 1); - } + else + now = ktime_get(); + p->time = ktime_sub(now, p->time); err = switch_to_kernel_sync(ce, err); p->runtime += intel_context_get_total_runtime_ns(ce); @@ -2571,13 +2575,14 @@ static int p_sync0(void *arg) return err; } - busy = false; if (intel_engine_supports_stats(engine)) { - p->busy = intel_engine_get_busy_time(engine); + p->busy = intel_engine_get_busy_time(engine, &p->time); busy = true; + } else { + p->time = ktime_get(); + busy = false; } - p->time = ktime_get(); count = 0; do { struct i915_request *rq; @@ -2600,11 +2605,15 @@ static int p_sync0(void *arg) count++; } while (!__igt_timeout(end_time, NULL)); - p->time = ktime_sub(ktime_get(), p->time); if (busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(engine), + ktime_t now; + + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), p->busy); + p->time = ktime_sub(now, p->time); + } else { + p->time = ktime_sub(ktime_get(), p->time); } err = switch_to_kernel_sync(ce, err); @@ -2637,13 +2646,14 @@ static int p_sync1(void *arg) return err; } - busy = false; if (intel_engine_supports_stats(engine)) { - p->busy = intel_engine_get_busy_time(engine); + p->busy = intel_engine_get_busy_time(engine, &p->time); busy = true; + } else { + p->time = ktime_get(); + busy = false; } - p->time = ktime_get(); count = 0; do { struct i915_request *rq; @@ -2668,11 +2678,15 @@ static int p_sync1(void *arg) count++; } while (!__igt_timeout(end_time, NULL)); i915_request_put(prev); - p->time = ktime_sub(ktime_get(), p->time); if (busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(engine), + ktime_t now; + + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), p->busy); + p->time = ktime_sub(now, p->time); + } else { + p->time = ktime_sub(ktime_get(), p->time); } err = switch_to_kernel_sync(ce, err); @@ -2704,14 +2718,15 @@ static int p_many(void *arg) return err; } - busy = false; if (intel_engine_supports_stats(engine)) { - p->busy = intel_engine_get_busy_time(engine); + p->busy = intel_engine_get_busy_time(engine, &p->time); busy = true; + } else { + p->time = ktime_get(); + busy = false; } count = 0; - p->time = ktime_get(); do { struct i915_request *rq; @@ -2724,11 +2739,15 @@ static int p_many(void *arg) i915_request_add(rq); count++; } while (!__igt_timeout(end_time, NULL)); - p->time = ktime_sub(ktime_get(), p->time); if (busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(engine), + ktime_t now; + + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), p->busy); + p->time = ktime_sub(now, p->time); + } else { + p->time = ktime_sub(ktime_get(), p->time); } err = switch_to_kernel_sync(ce, err); -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 13:09:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 14:09:15 +0100 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Enable selftesting of busy-stats Message-ID: <20200617130916.15261-1-chris@chris-wilson.co.uk> A couple of very simple tests to ensure that the basic properties of per-engine busyness accounting [0% and 100% busy] are faithful. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- .../drm/i915/gt/selftest_engine_heartbeat.c | 47 ++++---- .../drm/i915/gt/selftest_engine_heartbeat.h | 14 +++ drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 103 ++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 29 ++--- drivers/gpu/drm/i915/gt/selftest_lrc.c | 79 ++++++-------- drivers/gpu/drm/i915/gt/selftest_rps.c | 68 +++++------- drivers/gpu/drm/i915/gt/selftest_timeline.c | 21 +--- drivers/gpu/drm/i915/selftests/i915_request.c | 21 +--- 8 files changed, 212 insertions(+), 170 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 697114dd1f47..f3034c613bc0 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -10,6 +10,7 @@ #include "intel_gt_requests.h" #include "i915_selftest.h" +#include "selftest_engine_heartbeat.h" static int timeline_sync(struct intel_timeline *tl) { @@ -142,24 +143,6 @@ static int __live_idle_pulse(struct intel_engine_cs *engine, return err; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine, - unsigned long *saved) -{ - *saved = engine->props.heartbeat_interval_ms; - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine, - unsigned long saved) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = saved; -} - static int live_idle_flush(void *arg) { struct intel_gt *gt = arg; @@ -170,11 +153,9 @@ static int live_idle_flush(void *arg) /* Check that we can flush the idle barriers */ for_each_engine(engine, gt, id) { - unsigned long heartbeat; - - engine_heartbeat_disable(engine, &heartbeat); + st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_flush_barriers); - engine_heartbeat_enable(engine, heartbeat); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -192,11 +173,9 @@ static int live_idle_pulse(void *arg) /* Check that heartbeat pulses flush the idle barriers */ for_each_engine(engine, gt, id) { - unsigned long heartbeat; - - engine_heartbeat_disable(engine, &heartbeat); + st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_pulse); - engine_heartbeat_enable(engine, heartbeat); + st_engine_heartbeat_enable(engine); if (err && err != -ENODEV) break; @@ -394,3 +373,19 @@ int intel_heartbeat_live_selftests(struct drm_i915_private *i915) i915_modparams.enable_hangcheck = saved_hangcheck; return err; } + +void st_engine_heartbeat_disable(struct intel_engine_cs *engine) +{ + engine->props.heartbeat_interval_ms = 0; + + intel_engine_pm_get(engine); + intel_engine_park_heartbeat(engine); +} + +void st_engine_heartbeat_enable(struct intel_engine_cs *engine) +{ + intel_engine_pm_put(engine); + + engine->props.heartbeat_interval_ms = + engine->defaults.heartbeat_interval_ms; +} diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h new file mode 100644 index 000000000000..cd27113d5400 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef SELFTEST_ENGINE_HEARTBEAT_H +#define SELFTEST_ENGINE_HEARTBEAT_H + +struct intel_engine_cs; + +void st_engine_heartbeat_disable(struct intel_engine_cs *engine); +void st_engine_heartbeat_enable(struct intel_engine_cs *engine); + +#endif /* SELFTEST_ENGINE_HEARTBEAT_H */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..dd54dcb5cca2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -6,7 +6,109 @@ #include "i915_selftest.h" #include "selftest_engine.h" +#include "selftest_engine_heartbeat.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t de; + u64 dt; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + st_engine_heartbeat_disable(engine); + + ENGINE_TRACE(engine, "measuring idle time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (de < 0 || de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + + /* 100% busy */ + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto end; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + goto end; + } + + ENGINE_TRACE(engine, "measuring busy time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (100 * de < 95 * dt || 95 * de > 100 * dt) { + pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + +end: + st_engine_heartbeat_enable(engine); + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +179,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 7461936d549d..fb5ebf930ab2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -29,6 +29,7 @@ #include "intel_gt.h" #include "intel_engine_heartbeat.h" #include "intel_engine_pm.h" +#include "selftest_engine_heartbeat.h" #include "i915_selftest.h" #include "selftests/i915_random.h" @@ -310,22 +311,6 @@ static bool wait_until_running(struct hang *h, struct i915_request *rq) 1000)); } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int igt_hang_sanitycheck(void *arg) { struct intel_gt *gt = arg; @@ -482,7 +467,7 @@ static int igt_reset_nop_engine(void *arg) reset_engine_count = i915_reset_engine_count(global, engine); count = 0; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { int i; @@ -540,7 +525,7 @@ static int igt_reset_nop_engine(void *arg) } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s(%s): %d resets\n", __func__, engine->name, count); @@ -590,7 +575,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) reset_count = i915_reset_count(global); reset_engine_count = i915_reset_engine_count(global, engine); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { if (active) { @@ -642,7 +627,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; @@ -841,7 +826,7 @@ static int __igt_reset_engines(struct intel_gt *gt, yield(); /* start all threads before we begin */ - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { struct i915_request *rq = NULL; @@ -931,7 +916,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("i915_reset_engine(%s:%s): %lu resets\n", engine->name, test_name, count); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 4f3758a1cbcf..7f27088ded55 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -9,6 +9,7 @@ #include "gem/i915_gem_pm.h" #include "gt/intel_engine_heartbeat.h" #include "gt/intel_reset.h" +#include "gt/selftest_engine_heartbeat.h" #include "i915_selftest.h" #include "selftests/i915_random.h" @@ -51,22 +52,6 @@ static struct i915_vma *create_scratch(struct intel_gt *gt) return vma; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static bool is_active(struct i915_request *rq) { if (i915_request_is_active(rq)) @@ -234,7 +219,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) err = -EIO; break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n < ARRAY_SIZE(ce); n++) { struct intel_context *tmp; @@ -342,7 +327,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) intel_context_put(ce[n]); } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_live_test_end(&t)) err = -EIO; if (err) @@ -396,7 +381,7 @@ static int live_unlite_ring(void *arg) err = -EIO; break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n < ARRAY_SIZE(ce); n++) { struct intel_context *tmp; @@ -502,7 +487,7 @@ static int live_unlite_ring(void *arg) intel_context_unpin(ce[n]); intel_context_put(ce[n]); } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_live_test_end(&t)) err = -EIO; if (err) @@ -621,7 +606,7 @@ static int live_hold_reset(void *arg) break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK); if (IS_ERR(rq)) { @@ -681,7 +666,7 @@ static int live_hold_reset(void *arg) i915_request_put(rq); out: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_context_put(ce); if (err) break; @@ -728,7 +713,7 @@ static int live_error_interrupt(void *arg) const struct error_phase *p; int err = 0; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (p = phases; p->error[0] != GOOD; p++) { struct i915_request *client[ARRAY_SIZE(phases->error)]; @@ -827,7 +812,7 @@ static int live_error_interrupt(void *arg) } } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) { intel_gt_set_wedged(gt); return err; @@ -1042,9 +1027,9 @@ static int live_timeslice_preempt(void *arg) memset(vaddr, 0, PAGE_SIZE); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = slice_semaphore_queue(engine, vma, 5); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto err_pin; @@ -1166,7 +1151,7 @@ static int live_timeslice_rewind(void *arg) * Expect execution/evaluation order XZY */ - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); timeslice = xchg(&engine->props.timeslice_duration_ms, 1); slot = memset32(engine->status_page.addr + 1000, 0, 4); @@ -1261,7 +1246,7 @@ static int live_timeslice_rewind(void *arg) wmb(); engine->props.timeslice_duration_ms = timeslice; - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); for (i = 0; i < 3; i++) i915_request_put(rq[i]); if (igt_flush_test(gt->i915)) @@ -1353,7 +1338,7 @@ static int live_timeslice_queue(void *arg) if (!intel_engine_has_preemption(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); memset(vaddr, 0, PAGE_SIZE); /* ELSP[0]: semaphore wait */ @@ -1414,7 +1399,7 @@ static int live_timeslice_queue(void *arg) err_rq: i915_request_put(rq); err_heartbeat: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -1460,7 +1445,7 @@ static int live_timeslice_nopreempt(void *arg) break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); timeslice = xchg(&engine->props.timeslice_duration_ms, 1); /* Create an unpreemptible spinner */ @@ -1529,7 +1514,7 @@ static int live_timeslice_nopreempt(void *arg) igt_spinner_end(&spin); out_heartbeat: xchg(&engine->props.timeslice_duration_ms, timeslice); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; @@ -2433,7 +2418,7 @@ static int live_suppress_self_preempt(void *arg) if (igt_flush_test(gt->i915)) goto err_wedged; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); engine->execlists.preempt_hang.count = 0; rq_a = spinner_create_request(&a.spin, @@ -2441,14 +2426,14 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_a)) { err = PTR_ERR(rq_a); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_a); if (!igt_wait_for_spinner(&a.spin, rq_a)) { pr_err("First client failed to start\n"); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_wedged; } @@ -2460,7 +2445,7 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_b)) { err = PTR_ERR(rq_b); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_b); @@ -2471,7 +2456,7 @@ static int live_suppress_self_preempt(void *arg) if (!igt_wait_for_spinner(&b.spin, rq_b)) { pr_err("Second client failed to start\n"); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_wedged; } @@ -2485,12 +2470,12 @@ static int live_suppress_self_preempt(void *arg) engine->name, engine->execlists.preempt_hang.count, depth); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = -EINVAL; goto err_client_b; } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) goto err_wedged; } @@ -2902,7 +2887,7 @@ static int live_preempt_ring(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n <= 3; n++) { err = __live_preempt_ring(engine, &spin, @@ -2911,7 +2896,7 @@ static int live_preempt_ring(void *arg) break; } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -4568,7 +4553,7 @@ static int reset_virtual_engine(struct intel_gt *gt, } for (n = 0; n < nsibling; n++) - engine_heartbeat_disable(siblings[n]); + st_engine_heartbeat_disable(siblings[n]); rq = igt_spinner_create_request(&spin, ve, MI_ARB_CHECK); if (IS_ERR(rq)) { @@ -4639,7 +4624,7 @@ static int reset_virtual_engine(struct intel_gt *gt, i915_request_put(rq); out_heartbeat: for (n = 0; n < nsibling; n++) - engine_heartbeat_enable(siblings[n]); + st_engine_heartbeat_enable(siblings[n]); intel_context_put(ve); out_spin: @@ -5314,7 +5299,7 @@ static int live_lrc_gpr(void *arg) return PTR_ERR(scratch); for_each_engine(engine, gt, id) { - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = __live_lrc_gpr(engine, scratch, false); if (err) @@ -5325,7 +5310,7 @@ static int live_lrc_gpr(void *arg) goto err; err: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -5474,7 +5459,7 @@ static int live_lrc_timestamp(void *arg) for_each_engine(data.engine, gt, id) { int i, err = 0; - engine_heartbeat_disable(data.engine); + st_engine_heartbeat_disable(data.engine); for (i = 0; i < ARRAY_SIZE(data.ce); i++) { struct intel_context *tmp; @@ -5507,7 +5492,7 @@ static int live_lrc_timestamp(void *arg) } err: - engine_heartbeat_enable(data.engine); + st_engine_heartbeat_enable(data.engine); for (i = 0; i < ARRAY_SIZE(data.ce); i++) { if (!data.ce[i]) break; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..bb753f0c12eb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -12,6 +12,7 @@ #include "intel_gt_clock_utils.h" #include "intel_gt_pm.h" #include "intel_rc6.h" +#include "selftest_engine_heartbeat.h" #include "selftest_rps.h" #include "selftests/igt_flush_test.h" #include "selftests/igt_spinner.h" @@ -20,22 +21,6 @@ /* Try to isolate the impact of cstates from determing frequency response */ #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */ -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static void dummy_rps_work(struct work_struct *wrk) { } @@ -249,13 +234,13 @@ int live_rps_clock_interval(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); if (IS_ERR(rq)) { - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = PTR_ERR(rq); break; } @@ -266,7 +251,7 @@ int live_rps_clock_interval(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -322,7 +307,7 @@ int live_rps_clock_interval(void *arg) intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err == 0) { u64 time = intel_gt_pm_interval_to_ns(gt, cycles); @@ -408,7 +393,7 @@ int live_rps_control(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, @@ -424,7 +409,7 @@ int live_rps_control(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -434,7 +419,7 @@ int live_rps_control(void *arg) pr_err("%s: could not set minimum frequency [%x], only %x!\n", engine->name, rps->min_freq, read_cagf(rps)); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); show_pstate_limits(rps); err = -EINVAL; break; @@ -451,7 +436,7 @@ int live_rps_control(void *arg) pr_err("%s: could not restore minimum frequency [%x], only %x!\n", engine->name, rps->min_freq, read_cagf(rps)); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); show_pstate_limits(rps); err = -EINVAL; break; @@ -466,7 +451,7 @@ int live_rps_control(void *arg) min_dt = ktime_sub(ktime_get(), min_dt); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s: range:[%x:%uMHz, %x:%uMHz] limit:[%x:%uMHz], %x:%x response %lluns:%lluns\n", engine->name, @@ -637,14 +622,14 @@ int live_rps_frequency_cs(void *arg) int freq; } min, max; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); vma = create_spin_counter(engine, engine->kernel_context->vm, false, &cancel, &cntr); if (IS_ERR(vma)) { err = PTR_ERR(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); break; } @@ -725,7 +710,7 @@ int live_rps_frequency_cs(void *arg) i915_vma_unpin(vma); i915_vma_put(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -779,14 +764,14 @@ int live_rps_frequency_srm(void *arg) int freq; } min, max; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); vma = create_spin_counter(engine, engine->kernel_context->vm, true, &cancel, &cntr); if (IS_ERR(vma)) { err = PTR_ERR(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); break; } @@ -866,7 +851,7 @@ int live_rps_frequency_srm(void *arg) i915_vma_unpin(vma); i915_vma_put(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -1061,11 +1046,11 @@ int live_rps_interrupt(void *arg) intel_gt_pm_wait_for_idle(engine->gt); GEM_BUG_ON(intel_rps_is_active(rps)); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = __rps_up_interrupt(rps, engine, &spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto out; @@ -1074,13 +1059,13 @@ int live_rps_interrupt(void *arg) /* Keep the engine awake but idle and check for DOWN */ if (pm_events & GEN6_PM_RP_DOWN_THRESHOLD) { - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); intel_rc6_disable(>->rc6); err = __rps_down_interrupt(rps, engine); intel_rc6_enable(>->rc6); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto out; } @@ -1165,13 +1150,13 @@ int live_rps_power(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); if (IS_ERR(rq)) { - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = PTR_ERR(rq); break; } @@ -1182,7 +1167,7 @@ int live_rps_power(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -1195,7 +1180,7 @@ int live_rps_power(void *arg) min.power = measure_power_at(rps, &min.freq); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n", engine->name, @@ -1252,6 +1237,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index b2aad7ef046a..fcdee951579b 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -12,6 +12,7 @@ #include "intel_gt.h" #include "intel_gt_requests.h" #include "intel_ring.h" +#include "selftest_engine_heartbeat.h" #include "../selftests/i915_random.h" #include "../i915_selftest.h" @@ -751,22 +752,6 @@ static int live_hwsp_wrap(void *arg) return err; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int live_hwsp_rollover_kernel(void *arg) { struct intel_gt *gt = arg; @@ -785,7 +770,7 @@ static int live_hwsp_rollover_kernel(void *arg) struct i915_request *rq[3] = {}; int i; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); if (intel_gt_wait_for_idle(gt, HZ / 2)) { err = -EIO; goto out; @@ -836,7 +821,7 @@ static int live_hwsp_rollover_kernel(void *arg) out: for (i = 0; i < ARRAY_SIZE(rq); i++) i915_request_put(rq[i]); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 92c628f18c60..06d18aae070b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -34,6 +34,7 @@ #include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "gt/intel_gt_requests.h" +#include "gt/selftest_engine_heartbeat.h" #include "i915_random.h" #include "i915_selftest.h" @@ -2270,22 +2271,6 @@ static void rps_unpin(struct intel_gt *gt) atomic_dec(>->rps.num_waiters); } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int perf_request_latency(void *arg) { struct drm_i915_private *i915 = arg; @@ -2311,7 +2296,7 @@ static int perf_request_latency(void *arg) goto out; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rps_pin(engine->gt); if (err == 0) @@ -2330,7 +2315,7 @@ static int perf_request_latency(void *arg) err = measure_completion(ce); rps_unpin(engine->gt); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_context_unpin(ce); intel_context_put(ce); -- 2.20.1 From patchwork at emeril.freedesktop.org Wed Jun 17 13:20:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 13:20:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_POWER=5FDOMAIN=5FAUDIO_ref-count_debug_logs?= In-Reply-To: <20200617095001.19220-1-anshuman.gupta@intel.com> References: <20200617095001.19220-1-anshuman.gupta@intel.com> Message-ID: <159240002495.29980.14386699104803648626@emeril.freedesktop.org> == Series Details == Series: drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs URL : https://patchwork.freedesktop.org/series/78463/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639_full -> Patchwork_17978_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17978_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_flush@basic-wb-rw-before-default: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) +20 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl2/igt at gem_exec_flush@basic-wb-rw-before-default.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-apl6/igt at gem_exec_flush@basic-wb-rw-before-default.html * igt at i915_module_load@reload: - shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-iclb3/igt at i915_module_load@reload.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-tglb8/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_rpm@fences-dpms: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl6/igt at i915_pm_rpm@fences-dpms.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-kbl3/igt at i915_pm_rpm@fences-dpms.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk9/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-b-ctm-negative: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl4/igt at kms_color@pipe-b-ctm-negative.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-skl1/igt at kms_color@pipe-b-ctm-negative.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][15] -> [FAIL][16] ([i915#57]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-hsw2/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-hsw6/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl4/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#46]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk8/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-glk2/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][21] -> [DMESG-FAIL][22] ([i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb2/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-tglb8/igt at kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-snb: [PASS][25] -> [DMESG-WARN][26] ([i915#42]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-snb5/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html - shard-skl: [PASS][27] -> [INCOMPLETE][28] ([i915#69]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl10/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-skl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-iclb8/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][33] -> [INCOMPLETE][34] ([i915#155]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-kbl4/igt at kms_vblank@pipe-b-ts-continuation-suspend.html #### Possible fixes #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][35] ([i915#1930]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-normal-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk9/igt at gem_exec_whisper@basic-normal-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-glk4/igt at gem_exec_whisper@basic-normal-all.html * igt at gem_tiled_blits@basic: - shard-snb: [TIMEOUT][41] ([i915#1958]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gem_tiled_blits@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-snb1/igt at gem_tiled_blits@basic.html * igt at gem_tiled_swapping@non-threaded: - shard-apl: [DMESG-WARN][43] ([i915#183]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl2/igt at gem_tiled_swapping@non-threaded.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-apl6/igt at gem_tiled_swapping@non-threaded.html * igt at kms_addfb_basic@framebuffer-vs-set-tiling: - shard-apl: [DMESG-WARN][45] ([i915#95]) -> [PASS][46] +13 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl1/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-apl3/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +8 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl5/igt at kms_color@pipe-c-ctm-0-25.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-skl10/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-tglb: [DMESG-WARN][49] ([i915#402]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb5/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-tglb7/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +5 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [FAIL][53] ([i915#1928]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl10/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-kbl: [DMESG-WARN][55] ([i915#93] / [i915#95]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-apl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl6/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-apl7/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-iclb4/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb6/igt at kms_psr@psr2_sprite_plane_move.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_setmode@basic: - shard-hsw: [FAIL][67] ([i915#31]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-hsw2/igt at kms_setmode@basic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-hsw6/igt at kms_setmode@basic.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][69] ([i915#1958]) -> [FAIL][70] ([i915#1930]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html * igt at gen7_exec_parse@chained-batch: - shard-snb: [TIMEOUT][71] ([i915#1958]) -> [SKIP][72] ([fdo#109271]) +2 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gen7_exec_parse@chained-batch.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-snb1/igt at gen7_exec_parse@chained-batch.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][73] ([i915#454]) -> [SKIP][74] ([i915#468]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb5/igt at i915_pm_dc@dc6-dpms.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at kms_color_chamelium@pipe-b-ctm-max: - shard-snb: [TIMEOUT][75] ([i915#1958]) -> [SKIP][76] ([fdo#109271] / [fdo#111827]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at kms_color_chamelium@pipe-b-ctm-max.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-snb1/igt at kms_color_chamelium@pipe-b-ctm-max.html * igt at kms_content_protection@lic: - shard-kbl: [TIMEOUT][77] ([i915#1319] / [i915#1958]) -> [TIMEOUT][78] ([i915#1319]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl4/igt at kms_content_protection@lic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-kbl6/igt at kms_content_protection@lic.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [DMESG-FAIL][79] ([i915#95]) -> [FAIL][80] ([i915#1525]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl7/igt at kms_fbcon_fbt@fbc.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-apl8/igt at kms_fbcon_fbt@fbc.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][81] ([i915#93] / [i915#95]) -> [DMESG-WARN][82] ([i915#180] / [i915#93] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][83] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][84] ([fdo#108145] / [i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#183]: https://gitlab.freedesktop.org/drm/intel/issues/183 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17978 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17978: 1627afde2cc088538b87890cc69618233ba9e679 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17978/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 13:28:08 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 13:28:08 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/2=5D_drm/i915/selftests=3A_Enable?= =?utf-8?q?_selftesting_of_busy-stats?= In-Reply-To: <20200617130916.15261-1-chris@chris-wilson.co.uk> References: <20200617130916.15261-1-chris@chris-wilson.co.uk> Message-ID: <159240048849.29978.4188896982104443569@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78472/ State : warning == Summary == $ dim checkpatch origin/drm-tip de62af0961f8 drm/i915/selftests: Enable selftesting of busy-stats -:99: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #99: new file mode 100644 -:169: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #169: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:52: + udelay(100); -:202: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #202: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:85: + udelay(100); total: 0 errors, 1 warnings, 2 checks, 861 lines checked 62c9c2ccee1d drm/i915/gt: Always report the sample time for busy-stats From patchwork at emeril.freedesktop.org Wed Jun 17 13:49:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 13:49:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/selftests=3A_Enable_selfte?= =?utf-8?q?sting_of_busy-stats?= In-Reply-To: <20200617130916.15261-1-chris@chris-wilson.co.uk> References: <20200617130916.15261-1-chris@chris-wilson.co.uk> Message-ID: <159240176937.29980.5765144416935650142@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78472/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17981 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/index.html Known issues ------------ Here are the changes found in Patchwork_17981 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_rpm@module-reload: - fi-apl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-apl-guc/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-apl-guc/igt at i915_pm_rpm@module-reload.html - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][13] ([i915#1233]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_busy@basic at flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - {fi-tgl-dsi}: [INCOMPLETE][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +3 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17981 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17981: 62c9c2ccee1d8883b1b1c83e3f179065f0491cae @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 62c9c2ccee1d drm/i915/gt: Always report the sample time for busy-stats de62af0961f8 drm/i915/selftests: Enable selftesting of busy-stats == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/index.html From chris at chris-wilson.co.uk Wed Jun 17 14:16:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:49 +0100 Subject: [Intel-gfx] [PATCH 05/12] drm/i915/execlists: Defer schedule_out until after the next dequeue In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-5-chris@chris-wilson.co.uk> Inside schedule_out, we do extra work upon idling the context, such as updating the runtime, kicking off retires, kicking virtual engines. However, if we are in a series of processing single requests per contexts, we may find ourselves scheduling out the context, only to immediately schedule it back in during dequeue. This is just extra work that we can avoid if we keep the context marked as inflight across the dequeue. This becomes more significant later on for minimising virtual engine misses. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_types.h | 13 +++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 47 ++++++++++++++----- 4 files changed, 51 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 4954b0df4864..b63db45bab7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -45,8 +45,8 @@ struct intel_context { struct intel_engine_cs *engine; struct intel_engine_cs *inflight; -#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2) -#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2) +#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 3) +#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 3) struct i915_address_space *vm; struct i915_gem_context __rcu *gem_context; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index f30cdd591c8c..c8255611573e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -515,6 +515,8 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine) memset(execlists->pending, 0, sizeof(execlists->pending)); execlists->active = memset(execlists->inflight, 0, sizeof(execlists->inflight)); + execlists->inactive = + memset(execlists->post, 0, sizeof(execlists->post)); execlists->queue_priority_hint = INT_MIN; execlists->queue = RB_ROOT_CACHED; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 073c3769e8cc..31cf60cef5a8 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -208,6 +208,10 @@ struct intel_engine_execlists { * @active: the currently known context executing on HW */ struct i915_request * const *active; + /** + * @inactive: the current vacancy of completed CS + */ + struct i915_request **inactive; /** * @inflight: the set of contexts submitted and acknowleged by HW * @@ -225,6 +229,15 @@ struct intel_engine_execlists { * preemption or idle-to-active event. */ struct i915_request *pending[EXECLIST_MAX_PORTS + 1]; + /** + * @post: the set of completed context switches + * + * Since we may want to stagger the processing of the CS switches + * with the next submission, so that the context are notionally + * kept in flight across the dequeue, we defer scheduling out of + * the completed context switches. + */ + struct i915_request *post[2 * EXECLIST_MAX_PORTS + 1]; /** * @port_mask: number of execlist ports - 1 diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index c26f3fe17ebb..0fd8a6741b06 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1387,6 +1387,8 @@ __execlists_schedule_in(struct i915_request *rq) execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); + CE_TRACE(ce, "schedule-in, ccid:%x\n", ce->lrc.ccid); + return engine; } @@ -1433,6 +1435,8 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ + CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + /* * If we have just completed this context, the engine may now be * idle and we want to re-enter powersaving. @@ -2057,9 +2061,10 @@ static void set_preempt_timeout(struct intel_engine_cs *engine, active_preempt_timeout(engine, rq)); } -static inline void clear_ports(struct i915_request **ports, int count) +static inline struct i915_request ** +clear_ports(struct i915_request **ports, int count) { - memset_p((void **)ports, NULL, count); + return memset_p((void **)ports, NULL, count); } static void execlists_dequeue(struct intel_engine_cs *engine) @@ -2435,7 +2440,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (!memcmp(active, execlists->pending, (port - execlists->pending + 1) * sizeof(*port))) { do - execlists_schedule_out(fetch_and_zero(port)); + *execlists->inactive++ = *port; while (port-- != execlists->pending); goto skip_submit; @@ -2449,6 +2454,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + execlists->pending[0] = NULL; } } @@ -2458,12 +2464,12 @@ cancel_port_requests(struct intel_engine_execlists * const execlists) struct i915_request * const *port; for (port = execlists->pending; *port; port++) - execlists_schedule_out(*port); + *execlists->inactive++ = *port; clear_ports(execlists->pending, ARRAY_SIZE(execlists->pending)); /* Mark the end of active before we overwrite *active */ for (port = xchg(&execlists->active, execlists->pending); *port; port++) - execlists_schedule_out(*port); + *execlists->inactive++ = *port; clear_ports(execlists->inflight, ARRAY_SIZE(execlists->inflight)); smp_wmb(); /* complete the seqlock for execlists_active() */ @@ -2624,7 +2630,7 @@ static void process_csb(struct intel_engine_cs *engine) /* cancel old inflight, prepare for switch */ trace_ports(execlists, "preempted", old); while (*old) - execlists_schedule_out(*old++); + *execlists->inactive++ = *old++; /* switch pending to inflight */ GEM_BUG_ON(!assert_pending_valid(execlists, "promote")); @@ -2681,7 +2687,7 @@ static void process_csb(struct intel_engine_cs *engine) regs[CTX_RING_TAIL]); } - execlists_schedule_out(*execlists->active++); + *execlists->inactive++ = *execlists->active++; GEM_BUG_ON(execlists->active - execlists->inflight > execlists_num_ports(execlists)); @@ -2705,6 +2711,20 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } +static void post_process_csb(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists * const el = &engine->execlists; + struct i915_request **port; + + if (!el->post[0]) + return; + + GEM_BUG_ON(el->post[2 * EXECLIST_MAX_PORTS]); + for (port = el->post; *port; port++) + execlists_schedule_out(*port); + el->inactive = clear_ports(el->post, port - el->post); +} + static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -2973,8 +2993,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->active; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at active:%zd\n", - port - el->active); + "ccid:%x found at active:%zd\n", + ccid, port - el->active); return rq; } } @@ -2982,8 +3002,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->pending; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at pending:%zd\n", - port - el->pending); + "ccid:%x found at pending:%zd\n", + ccid, port - el->pending); return rq; } } @@ -3125,6 +3145,8 @@ static void execlists_submission_tasklet(unsigned long data) spin_unlock_irqrestore(&engine->active.lock, flags); rcu_read_unlock(); } + + post_process_csb(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -4063,8 +4085,6 @@ static void enable_execlists(struct intel_engine_cs *engine) ENGINE_POSTING_READ(engine, RING_HWS_PGA); enable_error_interrupt(engine); - - engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); } static bool unexpected_starting_state(struct intel_engine_cs *engine) @@ -5107,6 +5127,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) else execlists->csb_size = GEN11_CSB_ENTRIES; + engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); if (INTEL_GEN(engine->i915) >= 11) { execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32); execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32); -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:47 +0100 Subject: [Intel-gfx] [PATCH 03/12] drm/i915/gt: Decouple completed requests on unwind In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-3-chris@chris-wilson.co.uk> Since the introduction of preempt-to-busy, requests can complete in the background, even while they are not on the engine->active.requests list. As such, the engine->active.request list itself is not in strict retirement order, and we have to scan the entire list while unwinding to not miss any. However, if the request is completed we currently leave it on the list [until retirement], but we could just as simply remove it and stop treating it as active. We would only have to then traverse it once while unwinding in quick succession. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..4eb397b0e14d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1114,8 +1114,10 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) list_for_each_entry_safe_reverse(rq, rn, &engine->active.requests, sched.link) { - if (i915_request_completed(rq)) - continue; /* XXX */ + if (i915_request_completed(rq)) { + list_del_init(&rq->sched.link); + continue; + } __i915_request_unsubmit(rq); -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:56 +0100 Subject: [Intel-gfx] [PATCH 12/12] drm/i915/gt: Resubmit the virtual engine on schedule-out In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-12-chris@chris-wilson.co.uk> Having recognised that we do not change the sibling until we schedule out, we can then defer the decision to resubmit the virtual engine from the unwind of the active queue to scheduling out of the virtual context. By keeping the unwind order intact on the local engine, we can preserve data dependency ordering while doing a preempt-to-busy pass until we have determined the new ELSP. This means that if we try to timeslice between a virtual engine and a data-dependent ordinary request, the pair will maintain their relative ordering and we will avoid the resubmission, cancelling the timeslicing until further change. The dilemma though is that we then may end up in a situation where the 'demotion' of the virtual request to an ordinary request in the engine queue results in filling the ELSP[] with virtual requests instead of spreading the load across the engines. To compensate for this, we mark each virtual request and refuse to resubmit a virtual request in the secondary ELSP slots, thus forcing subsequent virtual requests to be scheduled out after timeslicing. By delaying the decision until we schedule out, we will avoid unnecessary resubmission. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 118 ++++++++++++++++--------- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 2 files changed, 75 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6a36939abfab..07a69765b73c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1120,53 +1120,23 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) __i915_request_unsubmit(rq); - /* - * Push the request back into the queue for later resubmission. - * If this request is not native to this physical engine (i.e. - * it came from a virtual source), push it back onto the virtual - * engine so that it can be moved across onto another physical - * engine as load dictates. - */ - if (likely(rq->execution_mask == engine->mask)) { - GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); - if (rq_prio(rq) != prio) { - prio = rq_prio(rq); - pl = i915_sched_lookup_priolist(engine, prio); - } - GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - - list_move(&rq->sched.link, pl); - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); + if (rq_prio(rq) != prio) { + prio = rq_prio(rq); + pl = i915_sched_lookup_priolist(engine, prio); + } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - /* Check in case we rollback so far we wrap [size/2] */ - if (intel_ring_direction(rq->ring, - intel_ring_wrap(rq->ring, - rq->tail), - rq->ring->tail) > 0) - rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; + list_move(&rq->sched.link, pl); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); - active = rq; - } else { - struct intel_engine_cs *owner = rq->context->engine; + /* Check in case we rollback so far we wrap [size/2] */ + if (intel_ring_direction(rq->ring, + intel_ring_wrap(rq->ring, rq->tail), + rq->ring->tail) > 0) + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; - /* - * Decouple the virtual breadcrumb before moving it - * back to the virtual engine -- we don't want the - * request to complete in the background and try - * and cancel the breadcrumb on the virtual engine - * (instead of the old engine where it is linked)! - */ - if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &rq->fence.flags)) { - spin_lock_nested(&rq->lock, - SINGLE_DEPTH_NESTING); - i915_request_cancel_breadcrumb(rq); - spin_unlock(&rq->lock); - } - WRITE_ONCE(rq->engine, owner); - owner->submit_request(rq); - active = NULL; - } + active = rq; } return active; @@ -1376,12 +1346,49 @@ execlists_schedule_in(struct i915_request *rq, int idx) return i915_request_get(rq); } +static void +resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve) +{ + struct intel_engine_cs *engine = rq->engine; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + + /* + * Decouple the virtual breadcrumb before moving it back to the virtual + * engine -- we don't want the request to complete in the background + * and then try and cancel the breadcrumb on the virtual engine + * (instead of the old engine where it is linked)! + */ + if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) { + spin_lock_nested(&rq->lock, SINGLE_DEPTH_NESTING); + i915_request_cancel_breadcrumb(rq); + spin_unlock(&rq->lock); + } + + clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + WRITE_ONCE(rq->engine, &ve->base); + ve->base.submit_request(rq); + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); + + /* + * This engine is now too busy to run this virtual request, so + * see if we can find an alternative engine for it to execute on. + * Once a request has become bonded to this engine, we treat it the + * same as other native request. + */ + if (i915_request_in_priority_queue(rq) && + rq->execution_mask != rq->engine->mask) + resubmit_virtual_request(rq, ve); } static inline void __execlists_schedule_out(struct i915_request *rq) @@ -1621,6 +1628,20 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, } sentinel = i915_request_has_sentinel(rq); + /* + * We want virtual requests to only be in the first slot so + * that they are never stuck behind a hog and can be immediately + * transferred onto the next idle engine. + */ + if (rq->execution_mask != engine->mask && + port != execlists->pending) { + GEM_TRACE_ERR("%s: virtual engine:%llx not in prime position[%zd]\n", + engine->name, + ce->timeline->fence_context, + port - execlists->pending); + return false; + } + /* Hold tightly onto the lock to prevent concurrent retires! */ if (!spin_trylock_irqsave(&rq->lock, flags)) continue; @@ -2317,6 +2338,15 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (i915_request_has_sentinel(last)) goto done; + /* + * We avoid submitting virtual requests into + * the secondary ports so that we can migrate + * the request immediately to another engine + * rather than wait for the primary request. + */ + if (rq->execution_mask != engine->mask) + goto done; + /* * If GVT overrides us we only ever submit * port[0], leaving port[1] empty. Note that we diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 7f27088ded55..241e65e77889 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -4587,7 +4587,7 @@ static int reset_virtual_engine(struct intel_gt *gt, spin_lock_irq(&engine->active.lock); __unwind_incomplete_requests(engine); spin_unlock_irq(&engine->active.lock); - GEM_BUG_ON(rq->engine != ve->engine); + GEM_BUG_ON(rq->engine != engine); /* Reset the engine while keeping our active request on hold */ execlists_hold(engine, rq); -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:53 +0100 Subject: [Intel-gfx] [PATCH 09/12] drm/i915/gt: Convert stats.active to plain unsigned int In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-9-chris@chris-wilson.co.uk> As context-in/out is now always serialised, we do not have to worry about concurrent enabling/disable of the busy-stats and can reduce the atomic_t active to a plain unsigned int, and the seqlock to a seqcount. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++--- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 28 +++++++------------- drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +-- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index a6b085d42672..b048e28f9886 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -338,7 +338,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) engine->schedule = NULL; ewma__engine_latency_init(&engine->latency); - seqlock_init(&engine->stats.lock); + seqcount_init(&engine->stats.lock); ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); @@ -1614,7 +1614,7 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, * add it to the total. */ *now = ktime_get(); - if (atomic_read(&engine->stats.active)) + if (engine->stats.active) total = ktime_add(total, ktime_sub(*now, engine->stats.start)); return total; @@ -1633,9 +1633,9 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) ktime_t total; do { - seq = read_seqbegin(&engine->stats.lock); + seq = read_seqcount_begin(&engine->stats.lock); total = __intel_engine_get_busy_time(engine, now); - } while (read_seqretry(&engine->stats.lock, seq)); + } while (read_seqcount_retry(&engine->stats.lock, seq)); return total; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h index 58491eae3482..09e4aca8cff6 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_stats.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -15,35 +15,25 @@ static inline void intel_engine_context_in(struct intel_engine_cs *engine) { - unsigned long flags; + raw_write_seqcount_begin(&engine->stats.lock); - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + if (!engine->stats.active++) engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); + + raw_write_seqcount_end(&engine->stats.lock); } static inline void intel_engine_context_out(struct intel_engine_cs *engine) { - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); + raw_write_seqcount_begin(&engine->stats.lock); - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { + GEM_BUG_ON(!engine->stats.active); + if (!--engine->stats.active) engine->stats.total = ktime_add(engine->stats.total, ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); + + raw_write_seqcount_end(&engine->stats.lock); } #endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index ca124f229f65..50951a129db5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -557,12 +557,12 @@ struct intel_engine_cs { /** * @active: Number of contexts currently scheduled in. */ - atomic_t active; + unsigned int active; /** * @lock: Lock protecting the below fields. */ - seqlock_t lock; + seqcount_t lock; /** * @total: Total time this engine was busy. -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:51 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:51 +0100 Subject: [Intel-gfx] [PATCH 07/12] drm/i915/gt: Drop atomic for engine->fw_active tracking In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-7-chris@chris-wilson.co.uk> Since schedule-in/out is now entirely serialised by the tasklet bitlock, we do not need to worry about concurrent in/out operations and so reduce the atomic operations to plain instructions. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c8255611573e..a6b085d42672 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1537,7 +1537,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, drm_printf(m, "\tLatency: %luus\n", ewma__engine_latency_read(&engine->latency)); drm_printf(m, "\tForcewake: %x domains, %d active\n", - engine->fw_domain, atomic_read(&engine->fw_active)); + engine->fw_domain, READ_ONCE(engine->fw_active)); rcu_read_lock(); rq = READ_ONCE(engine->heartbeat.systole); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 31cf60cef5a8..ca124f229f65 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -335,7 +335,7 @@ struct intel_engine_cs { * as possible. */ enum forcewake_domains fw_domain; - atomic_t fw_active; + unsigned int fw_active; unsigned long context_tag; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 40e6ab6d03e3..372aff5c5663 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1382,7 +1382,7 @@ __execlists_schedule_in(struct i915_request *rq) ce->lrc.ccid |= engine->execlists.ccid; __intel_gt_pm_get(engine->gt); - if (engine->fw_domain && !atomic_fetch_inc(&engine->fw_active)) + if (engine->fw_domain && !engine->fw_active++) intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); @@ -1453,7 +1453,7 @@ static inline void __execlists_schedule_out(struct i915_request *rq) intel_context_update_runtime(ce); intel_engine_context_out(engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); - if (engine->fw_domain && !atomic_dec_return(&engine->fw_active)) + if (engine->fw_domain && !--engine->fw_active) intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:50 +0100 Subject: [Intel-gfx] [PATCH 06/12] drm/i915/gt: ce->inflight updates are now serialised In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-6-chris@chris-wilson.co.uk> Since schedule-in and schedule-out are now both always under the tasklet bitlock, we can reduce the individual atomic operations to simple instructions and worry less. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 44 +++++++++++++---------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 0fd8a6741b06..40e6ab6d03e3 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1373,7 +1373,7 @@ __execlists_schedule_in(struct i915_request *rq) unsigned int tag = ffs(READ_ONCE(engine->context_tag)); GEM_BUG_ON(tag == 0 || tag >= BITS_PER_LONG); - clear_bit(tag - 1, &engine->context_tag); + __clear_bit(tag - 1, &engine->context_tag); ce->lrc.ccid = tag << (GEN11_SW_CTX_ID_SHIFT - 32); BUILD_BUG_ON(BITS_PER_LONG > GEN12_MAX_CONTEXT_HW_ID); @@ -1401,13 +1401,10 @@ execlists_schedule_in(struct i915_request *rq, int idx) GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine)); trace_i915_request_in(rq, idx); - old = READ_ONCE(ce->inflight); - do { - if (!old) { - WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq)); - break; - } - } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old))); + old = ce->inflight; + if (!old) + old = __execlists_schedule_in(rq); + WRITE_ONCE(ce->inflight, ptr_inc(old)); GEM_BUG_ON(intel_context_inflight(ce) != rq->engine); return i915_request_get(rq); @@ -1422,12 +1419,11 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce) tasklet_hi_schedule(&ve->base.execlists.tasklet); } -static inline void -__execlists_schedule_out(struct i915_request *rq, - struct intel_engine_cs * const engine, - unsigned int ccid) +static inline void __execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; + struct intel_engine_cs * const engine = rq->engine; + unsigned int ccid; /* * NB process_csb() is not under the engine->active.lock and hence @@ -1435,7 +1431,7 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ - CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + CE_TRACE(ce, "schedule-out, ccid:%x\n", ce->lrc.ccid); /* * If we have just completed this context, the engine may now be @@ -1445,12 +1441,13 @@ __execlists_schedule_out(struct i915_request *rq, i915_request_completed(rq)) intel_engine_add_retire(engine, ce->timeline); + ccid = ce->lrc.ccid; ccid >>= GEN11_SW_CTX_ID_SHIFT - 32; ccid &= GEN12_MAX_CONTEXT_HW_ID; if (ccid < BITS_PER_LONG) { GEM_BUG_ON(ccid == 0); GEM_BUG_ON(test_bit(ccid - 1, &engine->context_tag)); - set_bit(ccid - 1, &engine->context_tag); + __set_bit(ccid - 1, &engine->context_tag); } intel_context_update_runtime(ce); @@ -1471,26 +1468,23 @@ __execlists_schedule_out(struct i915_request *rq, */ if (ce->engine != engine) kick_siblings(rq, ce); - - intel_context_put(ce); } static inline void execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; - struct intel_engine_cs *cur, *old; - u32 ccid; trace_i915_request_out(rq); - ccid = rq->context->lrc.ccid; - old = READ_ONCE(ce->inflight); - do - cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL; - while (!try_cmpxchg(&ce->inflight, &old, cur)); - if (!cur) - __execlists_schedule_out(rq, old, ccid); + GEM_BUG_ON(!ce->inflight); + ce->inflight = ptr_dec(ce->inflight); + if (!intel_context_inflight_count(ce)) { + GEM_BUG_ON(ce->inflight != rq->engine); + WRITE_ONCE(ce->inflight, NULL); + __execlists_schedule_out(rq); + intel_context_put(ce); + } i915_request_put(rq); } -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:55 +0100 Subject: [Intel-gfx] [PATCH 11/12] drm/i915/gt: Decouple inflight virtual engines In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-11-chris@chris-wilson.co.uk> Once a virtual engine has been bound to a sibling, it will remain bound until we finally schedule out the last active request. We can not rebind the context to a new sibling while it is inflight as the context save will conflict, hence we wait. As we cannot then use any other sibliing while the context is inflight, only kick the bound sibling while it inflight and upon scheduling out the kick the rest (so that we can swap engines on timeslicing if the previously bound engine becomes oversubscribed). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +++++++++++++---------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 96483a153b62..6a36939abfab 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1379,9 +1379,8 @@ execlists_schedule_in(struct i915_request *rq, int idx) static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); - struct i915_request *next = READ_ONCE(ve->request); - if (next == rq || (next && next->execution_mask & ~rq->execution_mask)) + if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); } @@ -1796,18 +1795,14 @@ first_virtual_engine(struct intel_engine_cs *engine) rb_entry(rb, typeof(*ve), nodes[engine->id].rb); struct i915_request *rq = READ_ONCE(ve->request); - if (!rq) { /* lazily cleanup after another engine handled rq */ + /* lazily cleanup after another engine handled rq */ + if (!rq || !virtual_matches(ve, rq, engine)) { rb_erase_cached(rb, &el->virtual); RB_CLEAR_NODE(rb); rb = rb_first_cached(&el->virtual); continue; } - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - return ve; } @@ -5458,7 +5453,6 @@ static void virtual_submission_tasklet(unsigned long data) if (unlikely(!mask)) return; - local_irq_disable(); for (n = 0; n < ve->num_siblings; n++) { struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]); struct ve_node * const node = &ve->nodes[sibling->id]; @@ -5468,20 +5462,19 @@ static void virtual_submission_tasklet(unsigned long data) if (!READ_ONCE(ve->request)) break; /* already handled by a sibling's tasklet */ + spin_lock_irq(&sibling->active.lock); + if (unlikely(!(mask & sibling->mask))) { if (!RB_EMPTY_NODE(&node->rb)) { - spin_lock(&sibling->active.lock); rb_erase_cached(&node->rb, &sibling->execlists.virtual); RB_CLEAR_NODE(&node->rb); - spin_unlock(&sibling->active.lock); } - continue; - } - spin_lock(&sibling->active.lock); + goto unlock_engine; + } - if (!RB_EMPTY_NODE(&node->rb)) { + if (unlikely(!RB_EMPTY_NODE(&node->rb))) { /* * Cheat and avoid rebalancing the tree if we can * reuse this node in situ. @@ -5521,9 +5514,12 @@ static void virtual_submission_tasklet(unsigned long data) if (first && prio > sibling->execlists.queue_priority_hint) tasklet_hi_schedule(&sibling->execlists.tasklet); - spin_unlock(&sibling->active.lock); +unlock_engine: + spin_unlock_irq(&sibling->active.lock); + + if (intel_context_inflight(&ve->context)) + break; } - local_irq_enable(); } static void virtual_submit_request(struct i915_request *rq) -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:54 +0100 Subject: [Intel-gfx] [PATCH 10/12] drm/i915/gt: Use virtual_engine during execlists_dequeue In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-10-chris@chris-wilson.co.uk> Rather than going back and forth between the rb_node entry and the virtual_engine type, store the ve local and reuse it. As the container_of conversion from rb_node to virtual_engine requires a variable offset, performing that conversion just once shaves off a bit of code. v2: Keep a single virtual engine lookup, for typical use. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 214 +++++++++++++--------------- 1 file changed, 101 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 4c444477abf8..96483a153b62 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -455,7 +455,7 @@ static int queue_prio(const struct intel_engine_execlists *execlists) static inline bool need_preempt(const struct intel_engine_cs *engine, const struct i915_request *rq, - struct rb_node *rb) + struct virtual_engine *ve) { int last_prio; @@ -492,9 +492,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, rq_prio(list_next_entry(rq, sched.link)) > last_prio) return true; - if (rb) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { bool preempt = false; if (engine == ve->siblings[0]) { /* only preempt one sibling */ @@ -1787,6 +1785,35 @@ static bool virtual_matches(const struct virtual_engine *ve, return true; } +static struct virtual_engine * +first_virtual_engine(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists *el = &engine->execlists; + struct rb_node *rb = rb_first_cached(&el->virtual); + + while (rb) { + struct virtual_engine *ve = + rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + struct i915_request *rq = READ_ONCE(ve->request); + + if (!rq) { /* lazily cleanup after another engine handled rq */ + rb_erase_cached(rb, &el->virtual); + RB_CLEAR_NODE(rb); + rb = rb_first_cached(&el->virtual); + continue; + } + + if (!virtual_matches(ve, rq, engine)) { + rb = rb_next(rb); + continue; + } + + return ve; + } + + return NULL; +} + static void virtual_xfer_breadcrumbs(struct virtual_engine *ve) { /* @@ -1871,7 +1898,7 @@ static void defer_active(struct intel_engine_cs *engine) static bool need_timeslice(const struct intel_engine_cs *engine, const struct i915_request *rq, - const struct rb_node *rb) + struct virtual_engine *ve) { int hint; @@ -1880,9 +1907,7 @@ need_timeslice(const struct intel_engine_cs *engine, hint = engine->execlists.queue_priority_hint; - if (rb) { - const struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { const struct intel_engine_cs *inflight = intel_context_inflight(&ve->context); @@ -2034,7 +2059,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = READ_ONCE(execlists->active); + struct virtual_engine *ve = first_virtual_engine(engine); struct i915_request *last; struct rb_node *rb; bool submit = false; @@ -2061,26 +2087,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * and context switches) submission. */ - for (rb = rb_first_cached(&execlists->virtual); rb; ) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); - struct i915_request *rq = READ_ONCE(ve->request); - - if (!rq) { /* lazily cleanup after another engine handled rq */ - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } - - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - - break; - } - /* * If the queue is higher priority than the last * request in the currently active context, submit afresh. @@ -2088,10 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2102,9 +2105,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * find itself trying to jump back into a context it has just * completed and barf. */ - if ((last = *active)) { - if (need_preempt(engine, last, rb)) { + if (need_preempt(engine, last, ve)) { if (i915_request_completed(last)) { tasklet_hi_schedule(&execlists->tasklet); return; @@ -2135,7 +2137,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) __unwind_incomplete_requests(engine); last = NULL; - } else if (need_timeslice(engine, last, rb) && + } else if (need_timeslice(engine, last, ve) && timeslice_expired(execlists, last)) { if (i915_request_completed(last)) { tasklet_hi_schedule(&execlists->tasklet); @@ -2189,110 +2191,96 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } } - while (rb) { /* XXX virtual is always taking precedence */ - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + while (ve) { /* XXX virtual is always taking precedence */ struct i915_request *rq; spin_lock(&ve->base.active.lock); rq = ve->request; - if (unlikely(!rq)) { /* lost the race to a sibling */ - spin_unlock(&ve->base.active.lock); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } + if (unlikely(!rq)) /* lost the race to a sibling */ + goto unlock; GEM_BUG_ON(rq != ve->request); GEM_BUG_ON(rq->engine != &ve->base); GEM_BUG_ON(rq->context != &ve->context); - if (rq_prio(rq) >= queue_prio(execlists)) { - if (!virtual_matches(ve, rq, engine)) { - spin_unlock(&ve->base.active.lock); - rb = rb_next(rb); - continue; - } + if (unlikely(rq_prio(rq) < queue_prio(execlists))) { + spin_unlock(&ve->base.active.lock); + break; + } - if (last && !can_merge_rq(last, rq)) { - spin_unlock(&ve->base.active.lock); - start_timeslice(engine, rq_prio(rq)); - return; /* leave this for another sibling */ - } + GEM_BUG_ON(!virtual_matches(ve, rq, engine)); - ENGINE_TRACE(engine, - "virtual rq=%llx:%lld%s, new engine? %s\n", - rq->fence.context, - rq->fence.seqno, - i915_request_completed(rq) ? "!" : - i915_request_started(rq) ? "*" : - "", - yesno(engine != ve->siblings[0])); - - WRITE_ONCE(ve->request, NULL); - WRITE_ONCE(ve->base.execlists.queue_priority_hint, - INT_MIN); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); + if (last && !can_merge_rq(last, rq)) { + spin_unlock(&ve->base.active.lock); + start_timeslice(engine, rq_prio(rq)); + return; /* leave this for another sibling */ + } - GEM_BUG_ON(!(rq->execution_mask & engine->mask)); - WRITE_ONCE(rq->engine, engine); + ENGINE_TRACE(engine, + "virtual rq=%llx:%lld%s, new engine? %s\n", + rq->fence.context, + rq->fence.seqno, + i915_request_completed(rq) ? "!" : + i915_request_started(rq) ? "*" : + "", + yesno(engine != ve->siblings[0])); - if (engine != ve->siblings[0]) { - u32 *regs = ve->context.lrc_reg_state; - unsigned int n; + WRITE_ONCE(ve->request, NULL); + WRITE_ONCE(ve->base.execlists.queue_priority_hint, INT_MIN); - GEM_BUG_ON(READ_ONCE(ve->context.inflight)); + rb = &ve->nodes[engine->id].rb; + rb_erase_cached(rb, &execlists->virtual); + RB_CLEAR_NODE(rb); - if (!intel_engine_has_relative_mmio(engine)) - virtual_update_register_offsets(regs, - engine); + GEM_BUG_ON(!(rq->execution_mask & engine->mask)); + WRITE_ONCE(rq->engine, engine); - if (!list_empty(&ve->context.signals)) - virtual_xfer_breadcrumbs(ve); + if (engine != ve->siblings[0]) { + u32 *regs = ve->context.lrc_reg_state; + unsigned int n; - /* - * Move the bound engine to the top of the list - * for future execution. We then kick this - * tasklet first before checking others, so that - * we preferentially reuse this set of bound - * registers. - */ - for (n = 1; n < ve->num_siblings; n++) { - if (ve->siblings[n] == engine) { - swap(ve->siblings[n], - ve->siblings[0]); - break; - } - } + GEM_BUG_ON(READ_ONCE(ve->context.inflight)); - GEM_BUG_ON(ve->siblings[0] != engine); - } + if (!intel_engine_has_relative_mmio(engine)) + virtual_update_register_offsets(regs, engine); - if (__i915_request_submit(rq)) { - submit = true; - last = rq; - } - i915_request_put(rq); + if (!list_empty(&ve->context.signals)) + virtual_xfer_breadcrumbs(ve); /* - * Hmm, we have a bunch of virtual engine requests, - * but the first one was already completed (thanks - * preempt-to-busy!). Keep looking at the veng queue - * until we have no more relevant requests (i.e. - * the normal submit queue has higher priority). + * Move the bound engine to the top of the list for + * future execution. We then kick this tasklet first + * before checking others, so that we preferentially + * reuse this set of bound registers. */ - if (!submit) { - spin_unlock(&ve->base.active.lock); - rb = rb_first_cached(&execlists->virtual); - continue; + for (n = 1; n < ve->num_siblings; n++) { + if (ve->siblings[n] == engine) { + swap(ve->siblings[n], ve->siblings[0]); + break; + } } + + GEM_BUG_ON(ve->siblings[0] != engine); + } + + if (__i915_request_submit(rq)) { + submit = true; + last = rq; } + i915_request_put(rq); +unlock: spin_unlock(&ve->base.active.lock); - break; + + /* + * Hmm, we have a bunch of virtual engine requests, + * but the first one was already completed (thanks + * preempt-to-busy!). Keep looking at the veng queue + * until we have no more relevant requests (i.e. + * the normal submit queue has higher priority). + */ + ve = submit ? NULL : first_virtual_engine(engine); } while ((rb = rb_first_cached(&execlists->queue))) { -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:52 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:52 +0100 Subject: [Intel-gfx] [PATCH 08/12] drm/i915/gt: Extract busy-stats for ring-scheduler In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-8-chris@chris-wilson.co.uk> Lift the busy-stats context-in/out implementation out of intel_lrc, so that we can reuse it for other scheduler implementations. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------------- 2 files changed, 50 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include <linux/atomic.h> +#include <linux/ktime.h> +#include <linux/seqlock.h> + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 372aff5c5663..4c444477abf8 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1196,39 +1197,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:46 +0100 Subject: [Intel-gfx] [PATCH 02/12] drm/i915/gt: Always report the sample time for busy-stats In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-2-chris@chris-wilson.co.uk> Return the monotonic timestamp (ktime_get()) at the time of sampling the busy-time. This is used in preference to taking ktime_get() separately before or after the read seqlock as there can be some large variance in reported timestamps. For selftests trying to ascertain that we are reporting accurate to within a few microseconds, even a small delay leads to the test failing. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 ++-- drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 18 +++--- drivers/gpu/drm/i915/i915_pmu.c | 5 +- drivers/gpu/drm/i915/selftests/i915_request.c | 63 ++++++++++++------- 6 files changed, 66 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 791897f8d847..a9249a23903a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -334,7 +334,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *m, const char *header, ...); -ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine); +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, + ktime_t *now); struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 045179c65c44..c62b3cbdbbf9 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1595,7 +1595,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, intel_engine_print_breadcrumbs(engine, m); } -static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) +static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, + ktime_t *now) { ktime_t total = engine->stats.total; @@ -1603,9 +1604,9 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) * If the engine is executing something at the moment * add it to the total. */ + *now = ktime_get(); if (atomic_read(&engine->stats.active)) - total = ktime_add(total, - ktime_sub(ktime_get(), engine->stats.start)); + total = ktime_add(total, ktime_sub(*now, engine->stats.start)); return total; } @@ -1613,17 +1614,18 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) /** * intel_engine_get_busy_time() - Return current accumulated engine busyness * @engine: engine to report on + * @now: monotonic timestamp of sampling * * Returns accumulated time @engine was busy since engine stats were enabled. */ -ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) { unsigned int seq; ktime_t total; do { seq = read_seqbegin(&engine->stats.lock); - total = __intel_engine_get_busy_time(engine); + total = __intel_engine_get_busy_time(engine, now); } while (read_seqretry(&engine->stats.lock, seq)); return total; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 2f59fc6df3c2..bdece932592b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -53,13 +53,13 @@ static void rps_timer(struct timer_list *t) struct intel_engine_cs *engine; enum intel_engine_id id; s64 max_busy[3] = {}; - ktime_t dt, last; + ktime_t dt, timestamp, last; for_each_engine(engine, rps_to_gt(rps), id) { s64 busy; int i; - dt = intel_engine_get_busy_time(engine); + dt = intel_engine_get_busy_time(engine, ×tamp); last = engine->stats.rps; engine->stats.rps = dt; @@ -70,15 +70,14 @@ static void rps_timer(struct timer_list *t) } } - dt = ktime_get(); last = rps->pm_timestamp; - rps->pm_timestamp = dt; + rps->pm_timestamp = timestamp; if (intel_rps_is_active(rps)) { s64 busy; int i; - dt = ktime_sub(dt, last); + dt = ktime_sub(timestamp, last); /* * Our goal is to evaluate each engine independently, so we run diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index dd54dcb5cca2..b08fc5390e8a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -29,8 +29,8 @@ static int live_engine_busy_stats(void *arg) GEM_BUG_ON(intel_gt_pm_is_awake(gt)); for_each_engine(engine, gt, id) { struct i915_request *rq; - ktime_t de; - u64 dt; + ktime_t de, dt; + ktime_t t[2]; if (!intel_engine_supports_stats(engine)) continue; @@ -47,12 +47,11 @@ static int live_engine_busy_stats(void *arg) ENGINE_TRACE(engine, "measuring idle time\n"); preempt_disable(); - dt = ktime_to_ns(ktime_get()); - de = intel_engine_get_busy_time(engine); + de = intel_engine_get_busy_time(engine, &t[0]); udelay(100); - de = ktime_sub(intel_engine_get_busy_time(engine), de); - dt = ktime_to_ns(ktime_get()) - dt; + de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de); preempt_enable(); + dt = ktime_sub(t[1], t[0]); if (de < 0 || de > 10) { pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", engine->name, @@ -80,12 +79,11 @@ static int live_engine_busy_stats(void *arg) ENGINE_TRACE(engine, "measuring busy time\n"); preempt_disable(); - dt = ktime_to_ns(ktime_get()); - de = intel_engine_get_busy_time(engine); + de = intel_engine_get_busy_time(engine, &t[0]); udelay(100); - de = ktime_sub(intel_engine_get_busy_time(engine), de); - dt = ktime_to_ns(ktime_get()) - dt; + de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de); preempt_enable(); + dt = ktime_sub(t[1], t[0]); if (100 * de < 95 * dt || 95 * de > 100 * dt) { pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", engine->name, diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 802837de1767..28bc5f13ae52 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -565,7 +565,10 @@ static u64 __i915_pmu_event_read(struct perf_event *event) /* Do nothing */ } else if (sample == I915_SAMPLE_BUSY && intel_engine_supports_stats(engine)) { - val = ktime_to_ns(intel_engine_get_busy_time(engine)); + ktime_t unused; + + val = ktime_to_ns(intel_engine_get_busy_time(engine, + &unused)); } else { val = engine->pmu.sample[sample].cur; } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 06d18aae070b..9271aad7f779 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -2492,9 +2492,11 @@ static int perf_series_engines(void *arg) intel_engine_pm_get(p->engine); if (intel_engine_supports_stats(p->engine)) - p->busy = intel_engine_get_busy_time(p->engine) + 1; + p->busy = intel_engine_get_busy_time(p->engine, + &p->time) + 1; + else + p->time = ktime_get(); p->runtime = -intel_context_get_total_runtime_ns(ce); - p->time = ktime_get(); } err = (*fn)(ps); @@ -2505,13 +2507,15 @@ static int perf_series_engines(void *arg) struct perf_stats *p = &stats[idx]; struct intel_context *ce = ps->ce[idx]; int integer, decimal; - u64 busy, dt; + u64 busy, dt, now; - p->time = ktime_sub(ktime_get(), p->time); - if (p->busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(p->engine), + if (p->busy) + p->busy = ktime_sub(intel_engine_get_busy_time(p->engine, + &now), p->busy - 1); - } + else + now = ktime_get(); + p->time = ktime_sub(now, p->time); err = switch_to_kernel_sync(ce, err); p->runtime += intel_context_get_total_runtime_ns(ce); @@ -2571,13 +2575,14 @@ static int p_sync0(void *arg) return err; } - busy = false; if (intel_engine_supports_stats(engine)) { - p->busy = intel_engine_get_busy_time(engine); + p->busy = intel_engine_get_busy_time(engine, &p->time); busy = true; + } else { + p->time = ktime_get(); + busy = false; } - p->time = ktime_get(); count = 0; do { struct i915_request *rq; @@ -2600,11 +2605,15 @@ static int p_sync0(void *arg) count++; } while (!__igt_timeout(end_time, NULL)); - p->time = ktime_sub(ktime_get(), p->time); if (busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(engine), + ktime_t now; + + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), p->busy); + p->time = ktime_sub(now, p->time); + } else { + p->time = ktime_sub(ktime_get(), p->time); } err = switch_to_kernel_sync(ce, err); @@ -2637,13 +2646,14 @@ static int p_sync1(void *arg) return err; } - busy = false; if (intel_engine_supports_stats(engine)) { - p->busy = intel_engine_get_busy_time(engine); + p->busy = intel_engine_get_busy_time(engine, &p->time); busy = true; + } else { + p->time = ktime_get(); + busy = false; } - p->time = ktime_get(); count = 0; do { struct i915_request *rq; @@ -2668,11 +2678,15 @@ static int p_sync1(void *arg) count++; } while (!__igt_timeout(end_time, NULL)); i915_request_put(prev); - p->time = ktime_sub(ktime_get(), p->time); if (busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(engine), + ktime_t now; + + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), p->busy); + p->time = ktime_sub(now, p->time); + } else { + p->time = ktime_sub(ktime_get(), p->time); } err = switch_to_kernel_sync(ce, err); @@ -2704,14 +2718,15 @@ static int p_many(void *arg) return err; } - busy = false; if (intel_engine_supports_stats(engine)) { - p->busy = intel_engine_get_busy_time(engine); + p->busy = intel_engine_get_busy_time(engine, &p->time); busy = true; + } else { + p->time = ktime_get(); + busy = false; } count = 0; - p->time = ktime_get(); do { struct i915_request *rq; @@ -2724,11 +2739,15 @@ static int p_many(void *arg) i915_request_add(rq); count++; } while (!__igt_timeout(end_time, NULL)); - p->time = ktime_sub(ktime_get(), p->time); if (busy) { - p->busy = ktime_sub(intel_engine_get_busy_time(engine), + ktime_t now; + + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), p->busy); + p->time = ktime_sub(now, p->time); + } else { + p->time = ktime_sub(ktime_get(), p->time); } err = switch_to_kernel_sync(ce, err); -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:48 +0100 Subject: [Intel-gfx] [PATCH 04/12] drm/i915/execlists: Replace direct submit with direct call to tasklet In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <20200617141656.24384-4-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 3 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 ++++---- drivers/gpu/drm/i915/gt/intel_lrc.c | 79 +++++++------------ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 5 files changed, 56 insertions(+), 68 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index a9249a23903a..e6991521cd54 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -210,6 +210,9 @@ int intel_engine_resume(struct intel_engine_cs *engine); int intel_ring_submission_setup(struct intel_engine_cs *engine); +int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms); int intel_engine_stop_cs(struct intel_engine_cs *engine); void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..f30cdd591c8c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err =__intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 4eb397b0e14d..c26f3fe17ebb 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2705,16 +2705,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3104,7 +3094,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3114,7 +3104,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3124,16 +3113,17 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); + + if (!engine->execlists.pending[0]) { unsigned long flags; + rcu_read_lock(); /* protect peeking at execlists->active */ spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); + execlists_dequeue(engine); spin_unlock_irqrestore(&engine->active.lock, flags); - - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); + rcu_read_unlock(); } } @@ -3165,26 +3155,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3198,20 +3178,22 @@ static void flush_csb(struct intel_engine_cs *engine) { struct intel_engine_execlists *el = &engine->execlists; - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); + if (!tasklet_trylock(&el->tasklet)) { + __execlists_kick(el); + return; } + + if (!reset_in_progress(el)) + execlists_submission_tasklet((unsigned long)engine); + + tasklet_unlock(&el->tasklet); } static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); + bool submit = false; /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3226,10 +3208,13 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + submit = submit_queue(engine, request); } spin_unlock_irqrestore(&engine->active.lock, flags); + + if (submit) + flush_csb(engine); } static void __execlists_context_fini(struct intel_context *ce) @@ -4115,7 +4100,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4132,10 +4116,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4149,7 +4129,8 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) * FIXME: Wa for more modern gens needs to be validated */ ring_set_paused(engine, 1); - intel_engine_stop_cs(engine); + if (__intel_engine_stop_cs(engine, 1000, 0)) + ENGINE_TRACE(engine, "stop-cs idling timed out\n"); engine->execlists.reset_ccid = active_ccid(engine); } @@ -4379,12 +4360,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + flush_csb(engine); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..0fa23cb6bf1a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1582,6 +1582,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 14:16:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 15:16:45 +0100 Subject: [Intel-gfx] [PATCH 01/12] drm/i915/selftests: Enable selftesting of busy-stats Message-ID: <20200617141656.24384-1-chris@chris-wilson.co.uk> A couple of very simple tests to ensure that the basic properties of per-engine busyness accounting [0% and 100% busy] are faithful. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- .../drm/i915/gt/selftest_engine_heartbeat.c | 47 ++++---- .../drm/i915/gt/selftest_engine_heartbeat.h | 14 +++ drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 103 ++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 29 ++--- drivers/gpu/drm/i915/gt/selftest_lrc.c | 79 ++++++-------- drivers/gpu/drm/i915/gt/selftest_rps.c | 68 +++++------- drivers/gpu/drm/i915/gt/selftest_timeline.c | 21 +--- drivers/gpu/drm/i915/selftests/i915_request.c | 21 +--- 8 files changed, 212 insertions(+), 170 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index 697114dd1f47..f3034c613bc0 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -10,6 +10,7 @@ #include "intel_gt_requests.h" #include "i915_selftest.h" +#include "selftest_engine_heartbeat.h" static int timeline_sync(struct intel_timeline *tl) { @@ -142,24 +143,6 @@ static int __live_idle_pulse(struct intel_engine_cs *engine, return err; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine, - unsigned long *saved) -{ - *saved = engine->props.heartbeat_interval_ms; - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine, - unsigned long saved) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = saved; -} - static int live_idle_flush(void *arg) { struct intel_gt *gt = arg; @@ -170,11 +153,9 @@ static int live_idle_flush(void *arg) /* Check that we can flush the idle barriers */ for_each_engine(engine, gt, id) { - unsigned long heartbeat; - - engine_heartbeat_disable(engine, &heartbeat); + st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_flush_barriers); - engine_heartbeat_enable(engine, heartbeat); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -192,11 +173,9 @@ static int live_idle_pulse(void *arg) /* Check that heartbeat pulses flush the idle barriers */ for_each_engine(engine, gt, id) { - unsigned long heartbeat; - - engine_heartbeat_disable(engine, &heartbeat); + st_engine_heartbeat_disable(engine); err = __live_idle_pulse(engine, intel_engine_pulse); - engine_heartbeat_enable(engine, heartbeat); + st_engine_heartbeat_enable(engine); if (err && err != -ENODEV) break; @@ -394,3 +373,19 @@ int intel_heartbeat_live_selftests(struct drm_i915_private *i915) i915_modparams.enable_hangcheck = saved_hangcheck; return err; } + +void st_engine_heartbeat_disable(struct intel_engine_cs *engine) +{ + engine->props.heartbeat_interval_ms = 0; + + intel_engine_pm_get(engine); + intel_engine_park_heartbeat(engine); +} + +void st_engine_heartbeat_enable(struct intel_engine_cs *engine) +{ + intel_engine_pm_put(engine); + + engine->props.heartbeat_interval_ms = + engine->defaults.heartbeat_interval_ms; +} diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h new file mode 100644 index 000000000000..cd27113d5400 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef SELFTEST_ENGINE_HEARTBEAT_H +#define SELFTEST_ENGINE_HEARTBEAT_H + +struct intel_engine_cs; + +void st_engine_heartbeat_disable(struct intel_engine_cs *engine); +void st_engine_heartbeat_enable(struct intel_engine_cs *engine); + +#endif /* SELFTEST_ENGINE_HEARTBEAT_H */ diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c index cbf6b0735272..dd54dcb5cca2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c @@ -6,7 +6,109 @@ #include "i915_selftest.h" #include "selftest_engine.h" +#include "selftest_engine_heartbeat.h" #include "selftests/igt_atomic.h" +#include "selftests/igt_flush_test.h" +#include "selftests/igt_spinner.h" + +static int live_engine_busy_stats(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + struct igt_spinner spin; + int err = 0; + + /* + * Check that if an engine supports busy-stats, they tell the truth. + */ + + if (igt_spinner_init(&spin, gt)) + return -ENOMEM; + + GEM_BUG_ON(intel_gt_pm_is_awake(gt)); + for_each_engine(engine, gt, id) { + struct i915_request *rq; + ktime_t de; + u64 dt; + + if (!intel_engine_supports_stats(engine)) + continue; + + if (!intel_engine_can_store_dword(engine)) + continue; + + if (intel_gt_pm_wait_for_idle(gt)) { + err = -EBUSY; + break; + } + + st_engine_heartbeat_disable(engine); + + ENGINE_TRACE(engine, "measuring idle time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (de < 0 || de > 10) { + pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + + /* 100% busy */ + rq = igt_spinner_create_request(&spin, + engine->kernel_context, + MI_NOOP); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto end; + } + i915_request_add(rq); + + if (!igt_wait_for_spinner(&spin, rq)) { + intel_gt_set_wedged(engine->gt); + err = -ETIME; + goto end; + } + + ENGINE_TRACE(engine, "measuring busy time\n"); + preempt_disable(); + dt = ktime_to_ns(ktime_get()); + de = intel_engine_get_busy_time(engine); + udelay(100); + de = ktime_sub(intel_engine_get_busy_time(engine), de); + dt = ktime_to_ns(ktime_get()) - dt; + preempt_enable(); + if (100 * de < 95 * dt || 95 * de > 100 * dt) { + pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", + engine->name, + de, (int)div64_u64(100 * de, dt), dt); + GEM_TRACE_DUMP(); + err = -EINVAL; + goto end; + } + +end: + st_engine_heartbeat_enable(engine); + igt_spinner_end(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + if (err) + break; + } + + igt_spinner_fini(&spin); + if (igt_flush_test(gt->i915)) + err = -EIO; + return err; +} static int live_engine_pm(void *arg) { @@ -77,6 +179,7 @@ static int live_engine_pm(void *arg) int live_engine_pm_selftests(struct intel_gt *gt) { static const struct i915_subtest tests[] = { + SUBTEST(live_engine_busy_stats), SUBTEST(live_engine_pm), }; diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 7461936d549d..fb5ebf930ab2 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -29,6 +29,7 @@ #include "intel_gt.h" #include "intel_engine_heartbeat.h" #include "intel_engine_pm.h" +#include "selftest_engine_heartbeat.h" #include "i915_selftest.h" #include "selftests/i915_random.h" @@ -310,22 +311,6 @@ static bool wait_until_running(struct hang *h, struct i915_request *rq) 1000)); } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int igt_hang_sanitycheck(void *arg) { struct intel_gt *gt = arg; @@ -482,7 +467,7 @@ static int igt_reset_nop_engine(void *arg) reset_engine_count = i915_reset_engine_count(global, engine); count = 0; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { int i; @@ -540,7 +525,7 @@ static int igt_reset_nop_engine(void *arg) } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s(%s): %d resets\n", __func__, engine->name, count); @@ -590,7 +575,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) reset_count = i915_reset_count(global); reset_engine_count = i915_reset_engine_count(global, engine); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { if (active) { @@ -642,7 +627,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; @@ -841,7 +826,7 @@ static int __igt_reset_engines(struct intel_gt *gt, yield(); /* start all threads before we begin */ - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); set_bit(I915_RESET_ENGINE + id, >->reset.flags); do { struct i915_request *rq = NULL; @@ -931,7 +916,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } } while (time_before(jiffies, end_time)); clear_bit(I915_RESET_ENGINE + id, >->reset.flags); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("i915_reset_engine(%s:%s): %lu resets\n", engine->name, test_name, count); diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 4f3758a1cbcf..7f27088ded55 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -9,6 +9,7 @@ #include "gem/i915_gem_pm.h" #include "gt/intel_engine_heartbeat.h" #include "gt/intel_reset.h" +#include "gt/selftest_engine_heartbeat.h" #include "i915_selftest.h" #include "selftests/i915_random.h" @@ -51,22 +52,6 @@ static struct i915_vma *create_scratch(struct intel_gt *gt) return vma; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static bool is_active(struct i915_request *rq) { if (i915_request_is_active(rq)) @@ -234,7 +219,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) err = -EIO; break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n < ARRAY_SIZE(ce); n++) { struct intel_context *tmp; @@ -342,7 +327,7 @@ static int live_unlite_restore(struct intel_gt *gt, int prio) intel_context_put(ce[n]); } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_live_test_end(&t)) err = -EIO; if (err) @@ -396,7 +381,7 @@ static int live_unlite_ring(void *arg) err = -EIO; break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n < ARRAY_SIZE(ce); n++) { struct intel_context *tmp; @@ -502,7 +487,7 @@ static int live_unlite_ring(void *arg) intel_context_unpin(ce[n]); intel_context_put(ce[n]); } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_live_test_end(&t)) err = -EIO; if (err) @@ -621,7 +606,7 @@ static int live_hold_reset(void *arg) break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK); if (IS_ERR(rq)) { @@ -681,7 +666,7 @@ static int live_hold_reset(void *arg) i915_request_put(rq); out: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_context_put(ce); if (err) break; @@ -728,7 +713,7 @@ static int live_error_interrupt(void *arg) const struct error_phase *p; int err = 0; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (p = phases; p->error[0] != GOOD; p++) { struct i915_request *client[ARRAY_SIZE(phases->error)]; @@ -827,7 +812,7 @@ static int live_error_interrupt(void *arg) } } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) { intel_gt_set_wedged(gt); return err; @@ -1042,9 +1027,9 @@ static int live_timeslice_preempt(void *arg) memset(vaddr, 0, PAGE_SIZE); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = slice_semaphore_queue(engine, vma, 5); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto err_pin; @@ -1166,7 +1151,7 @@ static int live_timeslice_rewind(void *arg) * Expect execution/evaluation order XZY */ - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); timeslice = xchg(&engine->props.timeslice_duration_ms, 1); slot = memset32(engine->status_page.addr + 1000, 0, 4); @@ -1261,7 +1246,7 @@ static int live_timeslice_rewind(void *arg) wmb(); engine->props.timeslice_duration_ms = timeslice; - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); for (i = 0; i < 3; i++) i915_request_put(rq[i]); if (igt_flush_test(gt->i915)) @@ -1353,7 +1338,7 @@ static int live_timeslice_queue(void *arg) if (!intel_engine_has_preemption(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); memset(vaddr, 0, PAGE_SIZE); /* ELSP[0]: semaphore wait */ @@ -1414,7 +1399,7 @@ static int live_timeslice_queue(void *arg) err_rq: i915_request_put(rq); err_heartbeat: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -1460,7 +1445,7 @@ static int live_timeslice_nopreempt(void *arg) break; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); timeslice = xchg(&engine->props.timeslice_duration_ms, 1); /* Create an unpreemptible spinner */ @@ -1529,7 +1514,7 @@ static int live_timeslice_nopreempt(void *arg) igt_spinner_end(&spin); out_heartbeat: xchg(&engine->props.timeslice_duration_ms, timeslice); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; @@ -2433,7 +2418,7 @@ static int live_suppress_self_preempt(void *arg) if (igt_flush_test(gt->i915)) goto err_wedged; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); engine->execlists.preempt_hang.count = 0; rq_a = spinner_create_request(&a.spin, @@ -2441,14 +2426,14 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_a)) { err = PTR_ERR(rq_a); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_a); if (!igt_wait_for_spinner(&a.spin, rq_a)) { pr_err("First client failed to start\n"); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_wedged; } @@ -2460,7 +2445,7 @@ static int live_suppress_self_preempt(void *arg) MI_NOOP); if (IS_ERR(rq_b)) { err = PTR_ERR(rq_b); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_client_b; } i915_request_add(rq_b); @@ -2471,7 +2456,7 @@ static int live_suppress_self_preempt(void *arg) if (!igt_wait_for_spinner(&b.spin, rq_b)) { pr_err("Second client failed to start\n"); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); goto err_wedged; } @@ -2485,12 +2470,12 @@ static int live_suppress_self_preempt(void *arg) engine->name, engine->execlists.preempt_hang.count, depth); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = -EINVAL; goto err_client_b; } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) goto err_wedged; } @@ -2902,7 +2887,7 @@ static int live_preempt_ring(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); for (n = 0; n <= 3; n++) { err = __live_preempt_ring(engine, &spin, @@ -2911,7 +2896,7 @@ static int live_preempt_ring(void *arg) break; } - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } @@ -4568,7 +4553,7 @@ static int reset_virtual_engine(struct intel_gt *gt, } for (n = 0; n < nsibling; n++) - engine_heartbeat_disable(siblings[n]); + st_engine_heartbeat_disable(siblings[n]); rq = igt_spinner_create_request(&spin, ve, MI_ARB_CHECK); if (IS_ERR(rq)) { @@ -4639,7 +4624,7 @@ static int reset_virtual_engine(struct intel_gt *gt, i915_request_put(rq); out_heartbeat: for (n = 0; n < nsibling; n++) - engine_heartbeat_enable(siblings[n]); + st_engine_heartbeat_enable(siblings[n]); intel_context_put(ve); out_spin: @@ -5314,7 +5299,7 @@ static int live_lrc_gpr(void *arg) return PTR_ERR(scratch); for_each_engine(engine, gt, id) { - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = __live_lrc_gpr(engine, scratch, false); if (err) @@ -5325,7 +5310,7 @@ static int live_lrc_gpr(void *arg) goto err; err: - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -5474,7 +5459,7 @@ static int live_lrc_timestamp(void *arg) for_each_engine(data.engine, gt, id) { int i, err = 0; - engine_heartbeat_disable(data.engine); + st_engine_heartbeat_disable(data.engine); for (i = 0; i < ARRAY_SIZE(data.ce); i++) { struct intel_context *tmp; @@ -5507,7 +5492,7 @@ static int live_lrc_timestamp(void *arg) } err: - engine_heartbeat_enable(data.engine); + st_engine_heartbeat_enable(data.engine); for (i = 0; i < ARRAY_SIZE(data.ce); i++) { if (!data.ce[i]) break; diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index 5049c3dd08a6..bb753f0c12eb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -12,6 +12,7 @@ #include "intel_gt_clock_utils.h" #include "intel_gt_pm.h" #include "intel_rc6.h" +#include "selftest_engine_heartbeat.h" #include "selftest_rps.h" #include "selftests/igt_flush_test.h" #include "selftests/igt_spinner.h" @@ -20,22 +21,6 @@ /* Try to isolate the impact of cstates from determing frequency response */ #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */ -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static void dummy_rps_work(struct work_struct *wrk) { } @@ -249,13 +234,13 @@ int live_rps_clock_interval(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); if (IS_ERR(rq)) { - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = PTR_ERR(rq); break; } @@ -266,7 +251,7 @@ int live_rps_clock_interval(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -322,7 +307,7 @@ int live_rps_clock_interval(void *arg) intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err == 0) { u64 time = intel_gt_pm_interval_to_ns(gt, cycles); @@ -408,7 +393,7 @@ int live_rps_control(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, @@ -424,7 +409,7 @@ int live_rps_control(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -434,7 +419,7 @@ int live_rps_control(void *arg) pr_err("%s: could not set minimum frequency [%x], only %x!\n", engine->name, rps->min_freq, read_cagf(rps)); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); show_pstate_limits(rps); err = -EINVAL; break; @@ -451,7 +436,7 @@ int live_rps_control(void *arg) pr_err("%s: could not restore minimum frequency [%x], only %x!\n", engine->name, rps->min_freq, read_cagf(rps)); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); show_pstate_limits(rps); err = -EINVAL; break; @@ -466,7 +451,7 @@ int live_rps_control(void *arg) min_dt = ktime_sub(ktime_get(), min_dt); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s: range:[%x:%uMHz, %x:%uMHz] limit:[%x:%uMHz], %x:%x response %lluns:%lluns\n", engine->name, @@ -637,14 +622,14 @@ int live_rps_frequency_cs(void *arg) int freq; } min, max; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); vma = create_spin_counter(engine, engine->kernel_context->vm, false, &cancel, &cntr); if (IS_ERR(vma)) { err = PTR_ERR(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); break; } @@ -725,7 +710,7 @@ int live_rps_frequency_cs(void *arg) i915_vma_unpin(vma); i915_vma_put(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -779,14 +764,14 @@ int live_rps_frequency_srm(void *arg) int freq; } min, max; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); vma = create_spin_counter(engine, engine->kernel_context->vm, true, &cancel, &cntr); if (IS_ERR(vma)) { err = PTR_ERR(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); break; } @@ -866,7 +851,7 @@ int live_rps_frequency_srm(void *arg) i915_vma_unpin(vma); i915_vma_put(vma); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (igt_flush_test(gt->i915)) err = -EIO; if (err) @@ -1061,11 +1046,11 @@ int live_rps_interrupt(void *arg) intel_gt_pm_wait_for_idle(engine->gt); GEM_BUG_ON(intel_rps_is_active(rps)); - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); err = __rps_up_interrupt(rps, engine, &spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto out; @@ -1074,13 +1059,13 @@ int live_rps_interrupt(void *arg) /* Keep the engine awake but idle and check for DOWN */ if (pm_events & GEN6_PM_RP_DOWN_THRESHOLD) { - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); intel_rc6_disable(>->rc6); err = __rps_down_interrupt(rps, engine); intel_rc6_enable(>->rc6); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) goto out; } @@ -1165,13 +1150,13 @@ int live_rps_power(void *arg) if (!intel_engine_can_store_dword(engine)) continue; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rq = igt_spinner_create_request(&spin, engine->kernel_context, MI_NOOP); if (IS_ERR(rq)) { - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); err = PTR_ERR(rq); break; } @@ -1182,7 +1167,7 @@ int live_rps_power(void *arg) pr_err("%s: RPS spinner did not start\n", engine->name); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_gt_set_wedged(engine->gt); err = -EIO; break; @@ -1195,7 +1180,7 @@ int live_rps_power(void *arg) min.power = measure_power_at(rps, &min.freq); igt_spinner_end(&spin); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n", engine->name, @@ -1252,6 +1237,11 @@ int live_rps_dynamic(void *arg) if (igt_spinner_init(&spin, gt)) return -ENOMEM; + if (intel_rps_has_interrupts(rps)) + pr_info("RPS has interrupt support\n"); + if (intel_rps_uses_timer(rps)) + pr_info("RPS has timer support\n"); + for_each_engine(engine, gt, id) { struct i915_request *rq; struct { diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index b2aad7ef046a..fcdee951579b 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -12,6 +12,7 @@ #include "intel_gt.h" #include "intel_gt_requests.h" #include "intel_ring.h" +#include "selftest_engine_heartbeat.h" #include "../selftests/i915_random.h" #include "../i915_selftest.h" @@ -751,22 +752,6 @@ static int live_hwsp_wrap(void *arg) return err; } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int live_hwsp_rollover_kernel(void *arg) { struct intel_gt *gt = arg; @@ -785,7 +770,7 @@ static int live_hwsp_rollover_kernel(void *arg) struct i915_request *rq[3] = {}; int i; - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); if (intel_gt_wait_for_idle(gt, HZ / 2)) { err = -EIO; goto out; @@ -836,7 +821,7 @@ static int live_hwsp_rollover_kernel(void *arg) out: for (i = 0; i < ARRAY_SIZE(rq); i++) i915_request_put(rq[i]); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); if (err) break; } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 92c628f18c60..06d18aae070b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -34,6 +34,7 @@ #include "gt/intel_engine_user.h" #include "gt/intel_gt.h" #include "gt/intel_gt_requests.h" +#include "gt/selftest_engine_heartbeat.h" #include "i915_random.h" #include "i915_selftest.h" @@ -2270,22 +2271,6 @@ static void rps_unpin(struct intel_gt *gt) atomic_dec(>->rps.num_waiters); } -static void engine_heartbeat_disable(struct intel_engine_cs *engine) -{ - engine->props.heartbeat_interval_ms = 0; - - intel_engine_pm_get(engine); - intel_engine_park_heartbeat(engine); -} - -static void engine_heartbeat_enable(struct intel_engine_cs *engine) -{ - intel_engine_pm_put(engine); - - engine->props.heartbeat_interval_ms = - engine->defaults.heartbeat_interval_ms; -} - static int perf_request_latency(void *arg) { struct drm_i915_private *i915 = arg; @@ -2311,7 +2296,7 @@ static int perf_request_latency(void *arg) goto out; } - engine_heartbeat_disable(engine); + st_engine_heartbeat_disable(engine); rps_pin(engine->gt); if (err == 0) @@ -2330,7 +2315,7 @@ static int perf_request_latency(void *arg) err = measure_completion(ce); rps_unpin(engine->gt); - engine_heartbeat_enable(engine); + st_engine_heartbeat_enable(engine); intel_context_unpin(ce); intel_context_put(ce); -- 2.20.1 From patchwork at emeril.freedesktop.org Wed Jun 17 14:41:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 14:41:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/12=5D_drm/i915/selftests=3A_Enab?= =?utf-8?q?le_selftesting_of_busy-stats?= In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <159240490971.29980.9755837986259388039@emeril.freedesktop.org> == Series Details == Series: series starting with [01/12] drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78475/ State : warning == Summary == $ dim checkpatch origin/drm-tip 87b8cc65bf25 drm/i915/selftests: Enable selftesting of busy-stats -:99: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #99: new file mode 100644 -:169: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #169: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:52: + udelay(100); -:202: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #202: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:85: + udelay(100); total: 0 errors, 1 warnings, 2 checks, 861 lines checked fcfc30daed01 drm/i915/gt: Always report the sample time for busy-stats 7121cc80a52d drm/i915/gt: Decouple completed requests on unwind dd8868ea0e43 drm/i915/execlists: Replace direct submit with direct call to tasklet -:51: ERROR:SPACING: spaces required around that '=' (ctx:WxV) #51: FILE: drivers/gpu/drm/i915/gt/intel_engine_cs.c:915: + err =__intel_wait_for_register_fw(engine->uncore, mode, ^ total: 1 errors, 0 warnings, 0 checks, 258 lines checked b5a72ad15f35 drm/i915/execlists: Defer schedule_out until after the next dequeue -:117: CHECK:SPACING: spaces preferred around that '*' (ctx:ExV) #117: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:2443: + *execlists->inactive++ = *port; ^ total: 0 errors, 0 warnings, 1 checks, 179 lines checked 9228c631502e drm/i915/gt: ce->inflight updates are now serialised cdd288e77320 drm/i915/gt: Drop atomic for engine->fw_active tracking cab30a74f3d5 drm/i915/gt: Extract busy-stats for ring-scheduler -:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #12: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 95 lines checked e26534592d91 drm/i915/gt: Convert stats.active to plain unsigned int e834f6d8791c drm/i915/gt: Use virtual_engine during execlists_dequeue 6ea10f6c057d drm/i915/gt: Decouple inflight virtual engines c2d47fcbc1c0 drm/i915/gt: Resubmit the virtual engine on schedule-out From patchwork at emeril.freedesktop.org Wed Jun 17 14:43:05 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 14:43:05 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/12=5D_drm/i915/selftests=3A_Enable_s?= =?utf-8?q?elftesting_of_busy-stats?= In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <159240498576.29978.17775327125874488668@emeril.freedesktop.org> == Series Details == Series: series starting with [01/12] drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78475/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From nicholas.kazlauskas at amd.com Wed Jun 17 14:45:59 2020 From: nicholas.kazlauskas at amd.com (Kazlauskas, Nicholas) Date: Wed, 17 Jun 2020 10:45:59 -0400 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> Message-ID: <b82053ef-03b1-8d4a-24d8-bc2c07037f84@amd.com> On 2020-06-17 5:58 a.m., Daniel Vetter wrote: > On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote: >> Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: >>> Add enable/disable flip done functions and the flip done handler >>> function which handles the flip done interrupt. >>> >>> Enable the flip done interrupt in IER. >>> >>> Enable flip done function is called before writing the >>> surface address register as the write to this register triggers >>> the flip done interrupt >>> >>> Flip done handler is used to send the page flip event as soon as the >>> surface address is written as per the requirement of async flips. >>> The interrupt is disabled after the event is sent. >>> >>> v2: -Change function name from icl_* to skl_* (Paulo) >>> -Move flip handler to this patch (Paulo) >>> -Remove vblank_put() (Paulo) >>> -Enable flip done interrupt for gen9+ only (Paulo) >>> -Enable flip done interrupt in power_well_post_enable hook (Paulo) >>> -Removed the event check in flip done handler to handle async >>> flips without pageflip events. >>> >>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) >>> -Make the pending vblank event NULL in the begining of >>> flip_done_handler to remove sporadic WARN_ON that is seen. >>> >>> Signed-off-by: Karthik B S <karthik.b.s at intel.com> >>> --- >>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ >>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ >>> drivers/gpu/drm/i915/i915_irq.h | 2 + >>> 3 files changed, 64 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >>> index f40b909952cc..48cc1fc9bc5a 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_display.c >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c >>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >>> >>> intel_dbuf_pre_plane_update(state); >>> >>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>> + if (new_crtc_state->uapi.async_flip) { >>> + skl_enable_flip_done(&crtc->base); >>> + break; >>> + } >>> + } >>> + >>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */ >>> dev_priv->display.commit_modeset_enables(state); >>> >>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >>> drm_atomic_helper_wait_for_flip_done(dev, &state->base); >>> >>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>> + if (new_crtc_state->uapi.async_flip) >>> + skl_disable_flip_done(&crtc->base); >>> + >>> if (new_crtc_state->hw.active && >>> !needs_modeset(new_crtc_state) && >>> !new_crtc_state->preload_luts && >>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >>> index efdd4c7b8e92..632e7b1deb87 100644 >>> --- a/drivers/gpu/drm/i915/i915_irq.c >>> +++ b/drivers/gpu/drm/i915/i915_irq.c >>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >>> u32 crc4) {} >>> #endif >>> >>> +static void flip_done_handler(struct drm_i915_private *dev_priv, >>> + unsigned int pipe) >>> +{ >>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); >>> + struct drm_crtc_state *crtc_state = crtc->base.state; >>> + struct drm_pending_vblank_event *e = crtc_state->event; >>> + struct drm_device *dev = &dev_priv->drm; >>> + unsigned long irqflags; >>> + >>> + crtc_state->event = NULL; >>> + >>> + spin_lock_irqsave(&dev->event_lock, irqflags); >>> + >>> + drm_crtc_send_vblank_event(&crtc->base, e); >> >> I don't think this is what we want. With this, the events the Kernel >> sends us all have the same sequence and timestamp. In fact, the IGT >> test you submitted fails because of this. >> >> In my original hackish proof-of-concept patch I had changed >> drm_update_vblank_count() to force diff=1 in order to always send >> events and I also changed g4x_get_vblank_counter() to get the counter >> from FLIPCOUNT (which updates every time there's a flip) instead of >> FRMCOUNT (which doesn't seem to increment when you do async flips). >> That is a drastic change, but the patch was just a PoC so I didn't care >> about keeping anything else working. >> >> One thing that confused me a little bit when dealing the the >> vblank/flip event interface from drm.ko is that "flips" and "vblanks" >> seem to be changed interchangeably, which is confusing for async flips: >> if you keep forever doing async flips in the very first few scanlines >> you never actually reach the "vblank" period, yet you keep flipping >> your frame. Then, what should your expectation regarding events be? > > Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR > where that changes), no idea why we can't keep sending out vblank > interrupts. > > Now flip events look maybe conflated in drm.ko code with vblank events > since most of the time a flip complete happens at exactly the same time > the vblank event. But for async flip this is not the case. > > Probably worth it to have new helpers/function in drm_vblank.c for > async flips, so that this is less confusing. Plus good documentation. > >> I think we may need to check how the other drivers handle async vblanks >> (or how drm.ko wants us to handle async vblanks). Should we increment >> sequence on every async flip? What about the timestamp? >> >> Daniel, Ville, do you happen to know the proper semantics here? >> >> There's certainly some adjustment to do to both this patch and the IGT. > > I think it would be really good if we cc dri-devel on this. amdgpu.ko is > currently the only implementation of async flips, we need to make sure we > are fully aligned on all the semantic details. > > That also means that the igt needs to be reviewed and tested by amdgpu > people. Might also be good to get the implementation acked by amd DC > people, just to make triple-sure we have the same semantics and generic > userspace compositors like mutter can use this across drivers. We've had > way too much pain here in the past, especially with the details you point > out here. > > Also, I think we need to have updated drm core documentation for async > flips, since the current ones are "do it like amdgpu does it". I think > just documenting the various pieces and flags in detail and how it all > interacts with e.g. other atomic commits and everything else would be > great. > > Harry and Nicholaus are the people you want from amd. Added everyone to cc. > -Daniel IIRC async flips are treated the same as regular flips from amdgpu perspective. When the hardware latches the new flip address an interrupt is triggered and we send back the vblank event from the interrupt handler immediately. I think we use the same timestamp calculation code for both paths in this case where we take the current hpos/vpos and calculate when scanout is going to actually occur. Technically we're actually scanning out the framebuffer immediately though so the timestamp is probably bogus. The regular vblank handler continues to run as usual in the background, there's no change to the timing. On newer hardware this triggers around when the hardware starts preparing the next frame, so close to the double buffer latch (which is typically in the back porch). Regards, Nicholas Kazlauskas > > >> >>> + >>> + spin_unlock_irqrestore(&dev->event_lock, irqflags); >>> +} >>> >>> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >>> enum pipe pipe) >>> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) >>> if (iir & GEN8_PIPE_VBLANK) >>> intel_handle_vblank(dev_priv, pipe); >>> >>> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) >>> + flip_done_handler(dev_priv, pipe); >>> + >>> if (iir & GEN8_PIPE_CDCLK_CRC_DONE) >>> hsw_pipe_crc_irq_handler(dev_priv, pipe); >>> >>> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) >>> return 0; >>> } >>> >>> +void skl_enable_flip_done(struct drm_crtc *crtc) >>> +{ >>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >>> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >>> + unsigned long irqflags; >>> + >>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >>> + >>> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >>> + >>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>> +} >>> + >>> /* Called from drm generic code, passed 'crtc' which >>> * we use as a pipe index >>> */ >>> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) >>> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>> } >>> >>> +void skl_disable_flip_done(struct drm_crtc *crtc) >>> +{ >>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >>> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >>> + unsigned long irqflags; >>> + >>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >>> + >>> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >>> + >>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>> +} >>> + >>> static void ibx_irq_reset(struct drm_i915_private *dev_priv) >>> { >>> struct intel_uncore *uncore = &dev_priv->uncore; >>> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, >>> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; >>> enum pipe pipe; >>> >>> + if (INTEL_GEN(dev_priv) >= 9) >>> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; >>> + >>> spin_lock_irq(&dev_priv->irq_lock); >>> >>> if (!intel_irqs_enabled(dev_priv)) { >>> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) >>> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | >>> GEN8_PIPE_FIFO_UNDERRUN; >>> >>> + if (INTEL_GEN(dev_priv) >= 9) >>> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; >>> + >>> de_port_enables = de_port_masked; >>> if (IS_GEN9_LP(dev_priv)) >>> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; >>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h >>> index 25f25cd95818..2f10c8135116 100644 >>> --- a/drivers/gpu/drm/i915/i915_irq.h >>> +++ b/drivers/gpu/drm/i915/i915_irq.h >>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); >>> int i965_enable_vblank(struct drm_crtc *crtc); >>> int ilk_enable_vblank(struct drm_crtc *crtc); >>> int bdw_enable_vblank(struct drm_crtc *crtc); >>> +void skl_enable_flip_done(struct drm_crtc *crtc); >>> void i8xx_disable_vblank(struct drm_crtc *crtc); >>> void i915gm_disable_vblank(struct drm_crtc *crtc); >>> void i965_disable_vblank(struct drm_crtc *crtc); >>> void ilk_disable_vblank(struct drm_crtc *crtc); >>> void bdw_disable_vblank(struct drm_crtc *crtc); >>> +void skl_disable_flip_done(struct drm_crtc *crtc); >>> >>> void gen2_irq_reset(struct intel_uncore *uncore); >>> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch/ > From patchwork at emeril.freedesktop.org Wed Jun 17 15:11:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 15:11:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/12=5D_drm/i915/selftests=3A_Enable_self?= =?utf-8?q?testing_of_busy-stats?= In-Reply-To: <20200617141656.24384-1-chris@chris-wilson.co.uk> References: <20200617141656.24384-1-chris@chris-wilson.co.uk> Message-ID: <159240668302.29977.7567262317096292884@emeril.freedesktop.org> == Series Details == Series: series starting with [01/12] drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78475/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17982 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17982 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17982, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17982: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at hangcheck: - fi-cml-s: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-cml-s/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-cml-s/igt at i915_selftest@live at hangcheck.html Known issues ------------ Here are the changes found in Patchwork_17982 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at hangcheck: - fi-icl-y: [PASS][9] -> [INCOMPLETE][10] ([i915#926]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-y/igt at i915_selftest@live at hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-icl-y/igt at i915_selftest@live at hangcheck.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - {fi-tgl-dsi}: [INCOMPLETE][19] -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#926]: https://gitlab.freedesktop.org/drm/intel/issues/926 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 42) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17982 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17982: c2d47fcbc1c0c926e90c5005c68002daf9a50ce1 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c2d47fcbc1c0 drm/i915/gt: Resubmit the virtual engine on schedule-out 6ea10f6c057d drm/i915/gt: Decouple inflight virtual engines e834f6d8791c drm/i915/gt: Use virtual_engine during execlists_dequeue e26534592d91 drm/i915/gt: Convert stats.active to plain unsigned int cab30a74f3d5 drm/i915/gt: Extract busy-stats for ring-scheduler cdd288e77320 drm/i915/gt: Drop atomic for engine->fw_active tracking 9228c631502e drm/i915/gt: ce->inflight updates are now serialised b5a72ad15f35 drm/i915/execlists: Defer schedule_out until after the next dequeue dd8868ea0e43 drm/i915/execlists: Replace direct submit with direct call to tasklet 7121cc80a52d drm/i915/gt: Decouple completed requests on unwind fcfc30daed01 drm/i915/gt: Always report the sample time for busy-stats 87b8cc65bf25 drm/i915/selftests: Enable selftesting of busy-stats == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17982/index.html From patchwork at emeril.freedesktop.org Wed Jun 17 15:13:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 15:13:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/selftests=3A_Enable_selfte?= =?utf-8?q?sting_of_busy-stats?= In-Reply-To: <20200617130916.15261-1-chris@chris-wilson.co.uk> References: <20200617130916.15261-1-chris@chris-wilson.co.uk> Message-ID: <159240679950.29977.209540502128640430@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/selftests: Enable selftesting of busy-stats URL : https://patchwork.freedesktop.org/series/78472/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639_full -> Patchwork_17981_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17981_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt at gem_exec_reloc@basic-spin-others at vcs0}: - shard-snb: [WARN][1] ([i915#2036]) -> [WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb5/igt at gem_exec_reloc@basic-spin-others at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-snb2/igt at gem_exec_reloc@basic-spin-others at vcs0.html Known issues ------------ Here are the changes found in Patchwork_17981_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at bcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl1/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * igt at gem_ctx_persistence@process: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at gem_ctx_persistence@process.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl2/igt at gem_ctx_persistence@process.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [PASS][7] -> [INCOMPLETE][8] ([i915#82]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-snb5/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_mmap_wc@write-cpu-read-wc: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#95]) +17 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl3/igt at gem_mmap_wc@write-cpu-read-wc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-apl4/igt at gem_mmap_wc@write-cpu-read-wc.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-iclb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb1/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-iclb3/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_dp_aux_dev: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb8/igt at kms_dp_aux_dev.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-tglb8/igt at kms_dp_aux_dev.html * igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk6/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ab-hdmi-a1-hdmi-a2.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-glk9/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl2/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl6/igt at kms_flip@flip-vs-wf_vblank-interruptible at a-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +10 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt at kms_flip_tiling@flip-changes-tiling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-skl1/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][21] -> [DMESG-FAIL][22] ([i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling-y.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-iclb1/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_setmode@basic: - shard-kbl: [PASS][27] -> [FAIL][28] ([i915#31]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at kms_setmode@basic.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl1/igt at kms_setmode@basic.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][29] -> [FAIL][30] ([i915#1542]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb5/igt at perf@blocking-parameterized.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-iclb6/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_exec_gttfill@all: - shard-glk: [DMESG-WARN][31] ([i915#118] / [i915#95]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk4/igt at gem_exec_gttfill@all.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-glk1/igt at gem_exec_gttfill@all.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [INCOMPLETE][33] ([i915#82]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-snb5/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_mmap_offset@ptrace at gtt: - shard-kbl: [DMESG-WARN][35] ([i915#93] / [i915#95]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl1/igt at gem_mmap_offset@ptrace at gtt.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl2/igt at gem_mmap_offset@ptrace at gtt.html * igt at gem_shrink@reclaim: - shard-hsw: [SKIP][37] ([fdo#109271]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-hsw2/igt at gem_shrink@reclaim.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-hsw8/igt at gem_shrink@reclaim.html * igt at gem_tiled_swapping@non-threaded: - shard-apl: [DMESG-WARN][39] ([i915#183]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl2/igt at gem_tiled_swapping@non-threaded.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-apl1/igt at gem_tiled_swapping@non-threaded.html * igt at i915_suspend@fence-restore-untiled: - shard-kbl: [INCOMPLETE][41] ([i915#155]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl4/igt at i915_suspend@fence-restore-untiled.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html * igt at kms_color@pipe-a-ctm-red-to-blue: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +3 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl8/igt at kms_color@pipe-a-ctm-red-to-blue.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-skl1/igt at kms_color@pipe-a-ctm-red-to-blue.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-tglb: [DMESG-WARN][45] ([i915#402]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb5/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-tglb3/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +6 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [FAIL][49] ([i915#1928]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl10/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-skl10/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-apl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl6/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-apl7/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-iclb4/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb6/igt at kms_psr@psr2_sprite_blt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html * igt at kms_vblank@invalid: - shard-apl: [DMESG-WARN][59] ([i915#95]) -> [PASS][60] +13 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl4/igt at kms_vblank@invalid.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-apl8/igt at kms_vblank@invalid.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][61] ([i915#1820]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][63] ([fdo#109349]) -> [DMESG-WARN][64] ([i915#1226]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb6/igt at kms_dp_dsc@basic-dsc-enable-edp.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_fbcon_fbt@fbc: - shard-apl: [DMESG-FAIL][65] ([i915#95]) -> [FAIL][66] ([i915#1525]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl7/igt at kms_fbcon_fbt@fbc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-apl8/igt at kms_fbcon_fbt@fbc.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][68] ([fdo#108145] / [i915#1982]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#183]: https://gitlab.freedesktop.org/drm/intel/issues/183 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 10) ------------------------------ Missing (1): pig-icl-1065g7 Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17981 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17981: 62c9c2ccee1d8883b1b1c83e3f179065f0491cae @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17981/index.html From lyude at redhat.com Wed Jun 17 15:27:58 2020 From: lyude at redhat.com (Lyude Paul) Date: Wed, 17 Jun 2020 11:27:58 -0400 Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616211146.23027-3-imre.deak@intel.com> References: <20200616141855.746-6-imre.deak@intel.com> <20200616211146.23027-3-imre.deak@intel.com> Message-ID: <656eecf36aa1200fd3c994a5c5dd2678c5cf8564.camel@redhat.com> Reviewed-by: Lyude Paul <lyude at redhat.com> Thanks for all the subtle fixes for broken MST displays, these are always my favorite to find :) On Wed, 2020-06-17 at 00:11 +0300, Imre Deak wrote: > Atm, we clear the ACT sent flag in the sink's DPCD before updating the > sink's payload table, along clearing the payload table updated flag. > The sink is supposed to set this flag once it detects that the source > has completed the ACT sequence (after detecting the 4 required ACT MTPH > symbols sent by the source). As opposed to this 2 DELL monitors I have > set the flag already along the payload table updated flag, which is not > quite correct. > > To be sure that the sink has detected the ACT MTPH symbols before > continuing enabling the encoder, clear the ACT sent flag before enabling > or disabling the transcoder VC payload allocation (which is what starts > the ACT sequence). > > v2 (Ville): > - Use the correct bit to clear the flags. > - Add code comment explaining the clearing semantics of the ACT handled > flag. > > Cc: Lyude Paul <lyude at redhat.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: dri-devel at lists.freedesktop.org > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 38 +++++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > include/drm/drm_dp_mst_helper.h | 2 ++ > 3 files changed, 40 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > b/drivers/gpu/drm/drm_dp_mst_topology.c > index b2f5a84b4cfb..1f5d14128c1a 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -4377,6 +4377,41 @@ void drm_dp_mst_deallocate_vcpi(struct > drm_dp_mst_topology_mgr *mgr, > } > EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); > > +/** > + * drm_dp_clear_payload_status() - Clears the payload table status flags > + * @mgr: manager to use > + * > + * Clears the payload table ACT handled and table updated flags in the MST > hub's > + * DPCD. This function must be called before updating the payload table or > + * starting the ACT sequence and waiting for the corresponding flags to get > + * set by the hub. > + * > + * Returns: > + * 0 if the flags got cleared successfully, otherwise a negative error > code. > + */ > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) > +{ > + int ret; > + > + /* > + * Note that the following is based on the DP Standard stating that > + * writing the DP_PAYLOAD_TABLE_UPDATED bit alone will clear both the > + * DP_PAYLOAD_TABLE_UPDATED and the DP_PAYLOAD_ACT_HANDLED flags. This > + * seems to be also the only way to clear DP_PAYLOAD_ACT_HANDLED. > + */ > + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > + DP_PAYLOAD_TABLE_UPDATED); > + if (ret < 0) { > + DRM_DEBUG_DRIVER("Can't clear the ACT handled/table updated > flags (%d)\n", > + ret); > + return ret; > + } > + WARN_ON(ret != 1); > + > + return 0; > +} > +EXPORT_SYMBOL(drm_dp_clear_payload_status); > + > static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > int id, struct drm_dp_payload *payload) > { > @@ -4384,8 +4419,7 @@ static int drm_dp_dpcd_write_payload(struct > drm_dp_mst_topology_mgr *mgr, > int ret; > int retries = 0; > > - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > - DP_PAYLOAD_TABLE_UPDATED); > + drm_dp_clear_payload_status(mgr); > > payload_alloc[0] = id; > payload_alloc[1] = payload->start_slot; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 9308b5920780..3c4b0fb10d8b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > DP_TP_STATUS_ACT_SENT); > + > + drm_dp_clear_payload_status(&intel_dp->mst_mgr); > } > > static void wait_for_act_sent(struct intel_dp *intel_dp) > diff --git a/include/drm/drm_dp_mst_helper.h > b/include/drm/drm_dp_mst_helper.h > index 8b9eb4db3381..2facb87624bf 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct > drm_dp_mst_topology_mgr *mgr, > int pbn); > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); > + > int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); > > -- Cheers, Lyude Paul (she/her) Associate Software Engineer at Red Hat From ville.syrjala at linux.intel.com Wed Jun 17 15:30:38 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 17 Jun 2020 18:30:38 +0300 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> Message-ID: <20200617153038.GM6112@intel.com> On Wed, Jun 17, 2020 at 11:58:10AM +0200, Daniel Vetter wrote: > On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote: > > Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: > > > Add enable/disable flip done functions and the flip done handler > > > function which handles the flip done interrupt. > > > > > > Enable the flip done interrupt in IER. > > > > > > Enable flip done function is called before writing the > > > surface address register as the write to this register triggers > > > the flip done interrupt > > > > > > Flip done handler is used to send the page flip event as soon as the > > > surface address is written as per the requirement of async flips. > > > The interrupt is disabled after the event is sent. > > > > > > v2: -Change function name from icl_* to skl_* (Paulo) > > > -Move flip handler to this patch (Paulo) > > > -Remove vblank_put() (Paulo) > > > -Enable flip done interrupt for gen9+ only (Paulo) > > > -Enable flip done interrupt in power_well_post_enable hook (Paulo) > > > -Removed the event check in flip done handler to handle async > > > flips without pageflip events. > > > > > > v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) > > > -Make the pending vblank event NULL in the begining of > > > flip_done_handler to remove sporadic WARN_ON that is seen. > > > > > > Signed-off-by: Karthik B S <karthik.b.s at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ > > > drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ > > > drivers/gpu/drm/i915/i915_irq.h | 2 + > > > 3 files changed, 64 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index f40b909952cc..48cc1fc9bc5a 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > > > > > intel_dbuf_pre_plane_update(state); > > > > > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > > + if (new_crtc_state->uapi.async_flip) { > > > + skl_enable_flip_done(&crtc->base); > > > + break; > > > + } > > > + } > > > + > > > /* Now enable the clocks, plane, pipe, and connectors that we set up. */ > > > dev_priv->display.commit_modeset_enables(state); > > > > > > @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) > > > drm_atomic_helper_wait_for_flip_done(dev, &state->base); > > > > > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > > > + if (new_crtc_state->uapi.async_flip) > > > + skl_disable_flip_done(&crtc->base); > > > + > > > if (new_crtc_state->hw.active && > > > !needs_modeset(new_crtc_state) && > > > !new_crtc_state->preload_luts && > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > > index efdd4c7b8e92..632e7b1deb87 100644 > > > --- a/drivers/gpu/drm/i915/i915_irq.c > > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > > @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, > > > u32 crc4) {} > > > #endif > > > > > > +static void flip_done_handler(struct drm_i915_private *dev_priv, > > > + unsigned int pipe) > > > +{ > > > + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); > > > + struct drm_crtc_state *crtc_state = crtc->base.state; > > > + struct drm_pending_vblank_event *e = crtc_state->event; > > > + struct drm_device *dev = &dev_priv->drm; > > > + unsigned long irqflags; > > > + > > > + crtc_state->event = NULL; > > > + > > > + spin_lock_irqsave(&dev->event_lock, irqflags); > > > + > > > + drm_crtc_send_vblank_event(&crtc->base, e); > > > > I don't think this is what we want. With this, the events the Kernel > > sends us all have the same sequence and timestamp. In fact, the IGT > > test you submitted fails because of this. > > > > In my original hackish proof-of-concept patch I had changed > > drm_update_vblank_count() to force diff=1 in order to always send > > events and I also changed g4x_get_vblank_counter() to get the counter > > from FLIPCOUNT (which updates every time there's a flip) instead of > > FRMCOUNT (which doesn't seem to increment when you do async flips). > > That is a drastic change, but the patch was just a PoC so I didn't care > > about keeping anything else working. > > > > One thing that confused me a little bit when dealing the the > > vblank/flip event interface from drm.ko is that "flips" and "vblanks" > > seem to be changed interchangeably, which is confusing for async flips: > > if you keep forever doing async flips in the very first few scanlines > > you never actually reach the "vblank" period, yet you keep flipping > > your frame. Then, what should your expectation regarding events be? > > Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR > where that changes), no idea why we can't keep sending out vblank > interrupts. > > Now flip events look maybe conflated in drm.ko code with vblank events > since most of the time a flip complete happens at exactly the same time > the vblank event. But for async flip this is not the case. > > Probably worth it to have new helpers/function in drm_vblank.c for > async flips, so that this is less confusing. Plus good documentation. We're going to need three different ways to calculate the flip timestamps: sync flip, vrr sync flip, async flip. First one we handle just fine currently since we know know when the timestamp was sampled and when the vblank ends so we can do the appropriate correction. VRR is going to be a bit more interesting since we don't really know how long the vblank will be. I think we may have to use the frame timestamp and current timestamp counter to first convert the monotonic timestamp to correlate with the start of the vblank exit, and then we can move it forward by the fixed (I think) length of the vblank exit procedure. For async flip I think we may want to do something similar with the flip done timestamp and current timestamp (apart from adding the fixed length of the vblank exit procedure of course, since there is no vblank exit). Although I'm not entirely sure what we should do if we do the async flip during the vblank. If we want to maintain that the timestamp always correlates with the first pixel actually getting scanned out then we should still correct the timestamp to point past the end of vblank. And even with the corrections there will be some amount of error due to the old data first having to drain out of the FIFO. That error I think we're just going to have to accept. Not sure how much surgery all that is going to require to the vblank timestamping code. -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Wed Jun 17 15:57:19 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 17 Jun 2020 18:57:19 +0300 Subject: [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips In-Reply-To: <20200528053931.29282-4-karthik.b.s@intel.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-4-karthik.b.s@intel.com> Message-ID: <20200617155719.GN6112@intel.com> On Thu, May 28, 2020 at 11:09:29AM +0530, Karthik B S wrote: > Support added only for async flips on primary plane. > If flip is requested on any other plane, reject it. > > Make sure there is no change in fbc, offset and framebuffer modifiers > when async flip is requested. > > If any of these are modified, reject async flip. > > v2: -Replace DRM_ERROR (Paulo) > -Add check for changes in OFFSET, FBC, RC(Paulo) > > v3: -Removed TODO as benchmarking tests have been run now. > > Signed-off-by: Karthik B S <karthik.b.s at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index eb1c360431ae..2307f924732c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -14798,6 +14798,53 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, > return false; > } > > +static int intel_atomic_check_async(struct intel_atomic_state *state) > +{ > + struct drm_plane *plane; > + struct drm_plane_state *plane_state; > + struct intel_crtc_state *old_crtc_state, *new_crtc_state; > + struct intel_plane_state *new_plane_state, *old_plane_state; > + struct intel_crtc *crtc; > + struct intel_plane *intel_plane; > + int i, j; > + > + /*FIXME: Async flip is only supported for primary plane currently > + * Support for overlays to be added. > + */ > + for_each_new_plane_in_state(&state->base, plane, plane_state, j) { > + if (plane->type != DRM_PLANE_TYPE_PRIMARY) { I think skl+ can do async flips on any universal planes. Earlier platforms were limited to primary only I think. Can't remember if g4x already had usable async flip via mmio. Pretty sure at least ilk+ had it. Also intel_ types are preferred, so this should use those, and I think since we're talking about hw planes we should rather check for PLANE_PRIMARY here. > + DRM_DEBUG_KMS("Async flips is NOT supported for non-primary plane\n"); > + return -EINVAL; > + } > + } > + > + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > + new_crtc_state, i) { > + if (old_crtc_state->enable_fbc != new_crtc_state->enable_fbc) { enable_fbc is bork, so this probably doesn't do anything particularly sensible. > + DRM_DEBUG_KMS("FBC status cannot be changed in async flip\n"); > + return -EINVAL; > + } > + } > + > + for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state, > + new_plane_state, i) { > + if ((old_plane_state->color_plane[0].x != > + new_plane_state->color_plane[0].x) || > + (old_plane_state->color_plane[0].y != > + new_plane_state->color_plane[0].y)) { Don't think we've even calculated those by the time you call this. So this stuff has to be called much later I think. > + DRM_DEBUG_KMS("Offsets cannot be changed in async\n"); > + return -EINVAL; > + } > + > + if (old_plane_state->uapi.fb->modifier != > + new_plane_state->uapi.fb->modifier) { We seem to be missing a lot of state here. Basically I think async flip can *only* change the plane surface address, so anything else changing we should reject. I guess if this comes in via the legacy page flip path the code/helpers do prevent most other things changing, but not sure. I don't really like relying on such core checks since someone could blindly expose this via the atomic ioctl without having those same restrictions in place. We might also want a dedicated plane hook for async flips since writing all the plane registers for these is rather pointless. I'm not even sure what happens with all the other double buffered registers if you write them and then do an async surface address update. Also if we want more accurate timestmaps based on the flip timestamp register then we're going to have to limit async flips to single plane per pipe at a time becasue the timestamp can only be sampled from a single plane. > + DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n"); > + return -EINVAL; > + } > + } > + return 0; > +} > + > /** > * intel_atomic_check - validate state object > * @dev: drm device > @@ -14825,6 +14872,14 @@ static int intel_atomic_check(struct drm_device *dev, > if (ret) > goto fail; > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { > + if (new_crtc_state->uapi.async_flip) { > + ret = intel_atomic_check_async(state); Kinda redundant to call this multiple times. I think the async_flip flag is actually misplaced. It should probably be in the drm_atomic_state instead of the crtc state. Also still not a huge fan of using the "async flip" termonology in the drm core. IMO we should just adopt the vulkan terminology for this stuff so it's obviuos what people mean when they talk about these things. > + if (ret) > + goto fail; > + } > + } > + > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > new_crtc_state, i) { > if (!needs_modeset(new_crtc_state)) { > -- > 2.17.1 -- Ville Syrj?l? Intel From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:10 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:10 +0100 Subject: [Intel-gfx] [PATCH i-g-t 00/10] gem_wsim improvements Message-ID: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Ripping out of legacy code and adding some new features, plus bugfixes. First bit is important so the tool can be refactored to support Gen11 and 12 properly. Working sets support is useful for simulating buffer contention and similar. Tvrtko Ursulin (10): gem_wsim: Rip out userspace balancing gem_wsim: Buffer objects working sets and complex dependencies gem_wsim: Show workload timing stats gem_wsim: Move BO allocation to a helper gem_wsim: Support random buffer sizes gem_wsim: Support scaling workload batch durations gem_wsim: Log max and active working set sizes in verbose mode gem_wsim: Snippet of a workload extracted from carchase gem_wsim: Implement device selection gem_wsim: Fix calibration handling benchmarks/Makefile.am | 2 +- benchmarks/Makefile.sources | 6 - benchmarks/ewma.h | 71 - benchmarks/gem_wsim.c | 2054 ++++++----------- benchmarks/ilog2.h | 104 - benchmarks/meson.build | 6 +- benchmarks/wsim/README | 63 + benchmarks/wsim/carchasepart.wsim | 184 ++ benchmarks/wsim/cloud-gaming-60fps.wsim | 11 + benchmarks/wsim/composited-ui.wsim | 7 + benchmarks/wsim/media-1080p-player.wsim | 2 + benchmarks/wsim/media_1n2_480p.wsim | 12 +- benchmarks/wsim/media_1n2_asy.wsim | 8 +- benchmarks/wsim/media_1n3_480p.wsim | 16 +- benchmarks/wsim/media_1n3_asy.wsim | 8 + benchmarks/wsim/media_1n4_480p.wsim | 20 +- benchmarks/wsim/media_1n4_asy.wsim | 10 + benchmarks/wsim/media_1n5_480p.wsim | 24 +- benchmarks/wsim/media_1n5_asy.wsim | 12 + benchmarks/wsim/media_load_balance_17i7.wsim | 10 +- benchmarks/wsim/media_load_balance_19.wsim | 4 +- .../wsim/media_load_balance_4k12u7.wsim | 2 + .../wsim/media_load_balance_fhd26u7.wsim | 16 +- benchmarks/wsim/media_load_balance_hd01.wsim | 34 +- .../wsim/media_load_balance_hd06mp2.wsim | 6 +- benchmarks/wsim/media_load_balance_hd12.wsim | 6 +- .../wsim/media_load_balance_hd17i4.wsim | 8 +- benchmarks/wsim/media_mfe2_480p.wsim | 12 +- benchmarks/wsim/media_mfe3_480p.wsim | 18 +- benchmarks/wsim/media_mfe4_480p.wsim | 24 +- benchmarks/wsim/media_nn_1080p.wsim | 4 + benchmarks/wsim/media_nn_1080p_s1.wsim | 4 +- benchmarks/wsim/media_nn_1080p_s2.wsim | 2 + benchmarks/wsim/media_nn_1080p_s3.wsim | 2 + benchmarks/wsim/media_nn_480p.wsim | 4 + benchmarks/wsim/vcs_balanced.wsim | 52 +- scripts/media-bench.pl | 736 ------ 37 files changed, 1171 insertions(+), 2393 deletions(-) delete mode 100644 benchmarks/ewma.h delete mode 100644 benchmarks/ilog2.h create mode 100644 benchmarks/wsim/carchasepart.wsim create mode 100644 benchmarks/wsim/cloud-gaming-60fps.wsim create mode 100644 benchmarks/wsim/composited-ui.wsim delete mode 100755 scripts/media-bench.pl -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:11 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:11 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/10] gem_wsim: Rip out userspace balancing In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Evaluation of userspace load balancing options was how this tool started but since we have settled on doing it in the kernel. Tomorrow we will want to update the tool for new engine interfaces and all this legacy code will just be a distraction. Rip out everything not related to explicit load balancing implemented via context engine maps and adjust the workloads to use it. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/Makefile.am | 2 +- benchmarks/Makefile.sources | 6 - benchmarks/ewma.h | 71 - benchmarks/gem_wsim.c | 1362 +---------------- benchmarks/ilog2.h | 104 -- benchmarks/meson.build | 6 +- benchmarks/wsim/media-1080p-player.wsim | 2 + benchmarks/wsim/media_1n2_480p.wsim | 12 +- benchmarks/wsim/media_1n2_asy.wsim | 8 +- benchmarks/wsim/media_1n3_480p.wsim | 16 +- benchmarks/wsim/media_1n3_asy.wsim | 8 + benchmarks/wsim/media_1n4_480p.wsim | 20 +- benchmarks/wsim/media_1n4_asy.wsim | 10 + benchmarks/wsim/media_1n5_480p.wsim | 24 +- benchmarks/wsim/media_1n5_asy.wsim | 12 + benchmarks/wsim/media_load_balance_17i7.wsim | 10 +- benchmarks/wsim/media_load_balance_19.wsim | 4 +- .../wsim/media_load_balance_4k12u7.wsim | 2 + .../wsim/media_load_balance_fhd26u7.wsim | 16 +- benchmarks/wsim/media_load_balance_hd01.wsim | 34 +- .../wsim/media_load_balance_hd06mp2.wsim | 6 +- benchmarks/wsim/media_load_balance_hd12.wsim | 6 +- .../wsim/media_load_balance_hd17i4.wsim | 8 +- benchmarks/wsim/media_mfe2_480p.wsim | 12 +- benchmarks/wsim/media_mfe3_480p.wsim | 18 +- benchmarks/wsim/media_mfe4_480p.wsim | 24 +- benchmarks/wsim/media_nn_1080p.wsim | 4 + benchmarks/wsim/media_nn_1080p_s1.wsim | 4 +- benchmarks/wsim/media_nn_1080p_s2.wsim | 2 + benchmarks/wsim/media_nn_1080p_s3.wsim | 2 + benchmarks/wsim/media_nn_480p.wsim | 4 + benchmarks/wsim/vcs_balanced.wsim | 52 +- scripts/media-bench.pl | 736 --------- 33 files changed, 300 insertions(+), 2307 deletions(-) delete mode 100644 benchmarks/ewma.h delete mode 100644 benchmarks/ilog2.h delete mode 100755 scripts/media-bench.pl diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am index 1f05adf31527..45b923ebbae3 100644 --- a/benchmarks/Makefile.am +++ b/benchmarks/Makefile.am @@ -25,4 +25,4 @@ gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_latency_LDADD = $(LDADD) -lpthread gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_syslatency_LDADD = $(LDADD) -lpthread -gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread +gem_wsim_LDADD = $(LDADD) -lpthread diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources index ee045fb309ad..dae3cdda4cf7 100644 --- a/benchmarks/Makefile.sources +++ b/benchmarks/Makefile.sources @@ -19,12 +19,6 @@ benchmarks_prog_list = \ vgem_mmap \ $(NULL) -gem_wsim_SOURCES = \ - gem_wsim.c \ - ewma.h \ - ilog2.h \ - $(NULL) - LIBDRM_INTEL_BENCHMARKS = \ intel_upload_blit_large \ intel_upload_blit_large_gtt \ diff --git a/benchmarks/ewma.h b/benchmarks/ewma.h deleted file mode 100644 index 8711004ed992..000000000000 --- a/benchmarks/ewma.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef EWMA_H -#define EWMA_H - -#include <ilog2.h> - -#define BUILD_BUG_ON(expr) -#define BUILD_BUG_ON_NOT_POWER_OF_2(expr) - -/* - * Exponentially weighted moving average (EWMA) - * - * This implements a fixed-precision EWMA algorithm, with both the - * precision and fall-off coefficient determined at compile-time - * and built into the generated helper funtions. - * - * The first argument to the macro is the name that will be used - * for the struct and helper functions. - * - * The second argument, the precision, expresses how many bits are - * used for the fractional part of the fixed-precision values. - * - * The third argument, the weight reciprocal, determines how the - * new values will be weighed vs. the old state, new values will - * get weight 1/weight_rcp and old values 1-1/weight_rcp. Note - * that this parameter must be a power of two for efficiency. - */ - -#define DECLARE_EWMA(T, name, _precision, _weight_rcp) \ - struct ewma_##name { \ - T internal; \ - }; \ - static inline void ewma_##name##_init(struct ewma_##name *e) \ - { \ - BUILD_BUG_ON(!__builtin_constant_p(_precision)); \ - BUILD_BUG_ON(!__builtin_constant_p(_weight_rcp)); \ - /* \ - * Even if you want to feed it just 0/1 you should have \ - * some bits for the non-fractional part... \ - */ \ - BUILD_BUG_ON((_precision) > 30); \ - BUILD_BUG_ON_NOT_POWER_OF_2(_weight_rcp); \ - e->internal = 0; \ - } \ - static inline T \ - ewma_##name##_read(struct ewma_##name *e) \ - { \ - BUILD_BUG_ON(!__builtin_constant_p(_precision)); \ - BUILD_BUG_ON(!__builtin_constant_p(_weight_rcp)); \ - BUILD_BUG_ON((_precision) > 30); \ - BUILD_BUG_ON_NOT_POWER_OF_2(_weight_rcp); \ - return e->internal >> (_precision); \ - } \ - static inline void ewma_##name##_add(struct ewma_##name *e, \ - T val) \ - { \ - const T weight_rcp = ilog2(_weight_rcp); \ - const T precision = _precision; \ - T internal = e->internal; \ - \ - BUILD_BUG_ON(!__builtin_constant_p(_precision)); \ - BUILD_BUG_ON(!__builtin_constant_p(_weight_rcp)); \ - BUILD_BUG_ON((_precision) > 30); \ - BUILD_BUG_ON_NOT_POWER_OF_2(_weight_rcp); \ - \ - e->internal = internal ? \ - (((internal << weight_rcp) - internal) + \ - (val << precision)) >> weight_rcp : \ - (val << precision); \ - } - -#endif /* EWMA_H */ diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index ad4edb936920..02fe8f5a5e69 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -55,7 +55,6 @@ #include "sw_sync.h" #include "i915/gem_mman.h" -#include "ewma.h" #include "i915/gem_engine_topology.h" enum intel_engine_id { @@ -154,21 +153,12 @@ struct w_step struct drm_i915_gem_execbuffer2 eb; struct drm_i915_gem_exec_object2 *obj; - struct drm_i915_gem_relocation_entry reloc[5]; + struct drm_i915_gem_relocation_entry reloc[1]; unsigned long bb_sz; uint32_t bb_handle; - uint32_t *seqno_value; - uint32_t *seqno_address; - uint32_t *rt0_value; - uint32_t *rt0_address; - uint32_t *rt1_address; - uint32_t *latch_value; - uint32_t *latch_address; uint32_t *recursive_bb_start; }; -DECLARE_EWMA(uint64_t, rt, 4, 2) - struct ctx { uint32_t id; int priority; @@ -176,9 +166,7 @@ struct ctx { enum intel_engine_id *engine_map; unsigned int bond_count; struct bond *bonds; - bool targets_instance; - bool wants_balance; - unsigned int static_vcs; + bool load_balance; uint64_t sseu; }; @@ -194,13 +182,11 @@ struct workload pthread_t thread; bool run; bool background; - const struct workload_balancer *balancer; unsigned int repeat; unsigned int flags; bool print_stats; uint32_t bb_prng; - uint32_t prng; struct timespec repeat_start; @@ -210,73 +196,25 @@ struct workload int sync_timeline; uint32_t sync_seqno; - uint32_t seqno[NUM_ENGINES]; - struct drm_i915_gem_exec_object2 status_object[2]; - uint32_t *status_page; - uint32_t *status_cs; - unsigned int vcs_rr; - - unsigned long qd_sum[NUM_ENGINES]; - unsigned long nr_bb[NUM_ENGINES]; - struct igt_list_head requests[NUM_ENGINES]; unsigned int nrequest[NUM_ENGINES]; - - struct workload *global_wrk; - const struct workload_balancer *global_balancer; - pthread_mutex_t mutex; - - union { - struct rtavg { - struct ewma_rt avg[NUM_ENGINES]; - uint32_t last[NUM_ENGINES]; - } rt; - }; - - struct busy_balancer { - int fd; - bool first; - unsigned int num_engines; - unsigned int engine_map[NUM_ENGINES]; - uint64_t t_prev; - uint64_t prev[NUM_ENGINES]; - double busy[NUM_ENGINES]; - } busy_balancer; }; -struct intel_mmio_data mmio_data; static const unsigned int nop_calibration_us = 1000; static bool has_nop_calibration = false; static bool sequential = true; static unsigned int master_prng; -static unsigned int context_vcs_rr; - static int verbose = 1; static int fd; static struct drm_i915_gem_context_param_sseu device_sseu = { .slice_mask = -1 /* Force read on first use. */ }; -#define SWAPVCS (1<<0) -#define SEQNO (1<<1) -#define BALANCE (1<<2) -#define RT (1<<3) -#define VCS2REMAP (1<<4) -#define INITVCSRR (1<<5) -#define SYNCEDCLIENTS (1<<6) -#define HEARTBEAT (1<<7) -#define GLOBAL_BALANCE (1<<8) -#define DEPSYNC (1<<9) -#define I915 (1<<10) -#define SSEU (1<<11) - -#define SEQNO_IDX(engine) ((engine) * 16) -#define SEQNO_OFFSET(engine) (SEQNO_IDX(engine) * sizeof(uint32_t)) - -#define RCS_TIMESTAMP (0x2000 + 0x358) -#define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x) +#define SYNCEDCLIENTS (1<<1) +#define DEPSYNC (1<<2) +#define SSEU (1<<3) static const char *ring_str_map[NUM_ENGINES] = { [DEFAULT] = "DEFAULT", @@ -578,26 +516,6 @@ static unsigned int num_engines_in_class(enum intel_engine_id class) return count; } -static void -fill_engines_class(struct i915_engine_class_instance *ci, - enum intel_engine_id class) -{ - unsigned int i, j = 0; - - igt_assert(class == VCS); - - query_engines(); - - for (i = 0; i < __num_engines; i++) { - if (__engines[i].engine_class != I915_ENGINE_CLASS_VIDEO) - continue; - - ci[j].engine_class = __engines[i].engine_class; - ci[j].engine_instance = __engines[i].engine_instance; - j++; - } -} - static void fill_engines_id_class(enum intel_engine_id *list, enum intel_engine_id class) @@ -744,7 +662,6 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) char *_token, *token, *tctx = NULL, *tstart = desc; char *field, *fctx = NULL, *fstart; struct w_step step, *steps = NULL; - bool bcs_used = false; unsigned int valid; int i, j, tmp; @@ -962,9 +879,6 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) valid++; step.engine = i; - - if (step.engine == BCS) - bcs_used = true; } if ((field = strtok_r(fstart, ".", &fctx))) { @@ -1089,9 +1003,6 @@ add_step: } } - if (bcs_used && (flags & VCS2REMAP) && verbose) - printf("BCS usage in workload with VCS2 remapping enabled!\n"); - return wrk; } @@ -1147,7 +1058,7 @@ static unsigned int get_duration(struct workload *wrk, struct w_step *w) static struct ctx * __get_ctx(struct workload *wrk, const struct w_step *w) { - return &wrk->ctx_list[w->context * 2]; + return &wrk->ctx_list[w->context]; } static unsigned long @@ -1211,13 +1122,7 @@ terminate_bb(struct w_step *w, unsigned int flags) unsigned int r = 0; uint32_t *ptr, *cs; - igt_assert(((flags & RT) && (flags & SEQNO)) || !(flags & RT)); - batch_start -= sizeof(uint32_t); /* bbend */ - if (flags & SEQNO) - batch_start -= 4 * sizeof(uint32_t); - if (flags & RT) - batch_start -= 12 * sizeof(uint32_t); if (w->unbound_duration) batch_start -= 4 * sizeof(uint32_t); /* MI_ARB_CHK + MI_BATCH_BUFFER_START */ @@ -1242,49 +1147,6 @@ terminate_bb(struct w_step *w, unsigned int flags) *cs++ = 0; } - if (flags & SEQNO) { - w->reloc[r++].offset = batch_start + sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = MI_STORE_DWORD_IMM; - w->seqno_address = cs; - *cs++ = 0; - *cs++ = 0; - w->seqno_value = cs; - *cs++ = 0; - } - - if (flags & RT) { - w->reloc[r++].offset = batch_start + sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = MI_STORE_DWORD_IMM; - w->rt0_address = cs; - *cs++ = 0; - *cs++ = 0; - w->rt0_value = cs; - *cs++ = 0; - - w->reloc[r++].offset = batch_start + 2 * sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = 0x24 << 23 | 2; /* MI_STORE_REG_MEM */ - *cs++ = RCS_TIMESTAMP; - w->rt1_address = cs; - *cs++ = 0; - *cs++ = 0; - - w->reloc[r++].offset = batch_start + sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = MI_STORE_DWORD_IMM; - w->latch_address = cs; - *cs++ = 0; - *cs++ = 0; - w->latch_value = cs; - *cs++ = 0; - } - *cs = bbe; return r; @@ -1305,13 +1167,7 @@ eb_set_engine(struct drm_i915_gem_execbuffer2 *eb, enum intel_engine_id engine, unsigned int flags) { - if (engine == VCS2 && (flags & VCS2REMAP)) - engine = BCS; - - if ((flags & I915) && engine == VCS) - eb->flags = 0; - else - eb->flags = eb_engine_map[engine]; + eb->flags = eb_engine_map[engine]; } static unsigned int @@ -1324,7 +1180,7 @@ find_engine_in_map(struct ctx *ctx, enum intel_engine_id engine) return i + 1; } - igt_assert(ctx->wants_balance); + igt_assert(ctx->load_balance); return 0; } @@ -1347,24 +1203,10 @@ eb_update_flags(struct workload *wrk, struct w_step *w, w->eb.flags |= I915_EXEC_FENCE_OUT; } -static struct drm_i915_gem_exec_object2 * -get_status_objects(struct workload *wrk) -{ - if (wrk->flags & GLOBAL_BALANCE) - return wrk->global_wrk->status_object; - else - return wrk->status_object; -} - static uint32_t get_ctxid(struct workload *wrk, struct w_step *w) { - struct ctx *ctx = __get_ctx(wrk, w); - - if (ctx->targets_instance && ctx->wants_balance && w->engine == VCS) - return wrk->ctx_list[w->context * 2 + 1].id; - else - return wrk->ctx_list[w->context * 2].id; + return wrk->ctx_list[w->context].id; } static void @@ -1372,7 +1214,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) { enum intel_engine_id engine = w->engine; unsigned int j = 0; - unsigned int nr_obj = 3 + w->data_deps.nr; + unsigned int nr_obj = 2 + w->data_deps.nr; unsigned int i; w->obj = calloc(nr_obj, sizeof(*w->obj)); @@ -1383,11 +1225,6 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) j++; igt_assert(j < nr_obj); - if (flags & SEQNO) { - w->obj[j++] = get_status_objects(wrk)[0]; - igt_assert(j < nr_obj); - } - for (i = 0; i < w->data_deps.nr; i++) { igt_assert(w->data_deps.list[i] <= 0); if (w->data_deps.list[i]) { @@ -1414,21 +1251,15 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) w->obj[j].relocation_count = terminate_bb(w, flags); if (w->obj[j].relocation_count) { + igt_assert(w->unbound_duration); w->obj[j].relocs_ptr = to_user_pointer(&w->reloc); - for (i = 0; i < w->obj[j].relocation_count; i++) - w->reloc[i].target_handle = 1; - if (w->unbound_duration) - w->reloc[0].target_handle = j; + w->reloc[0].target_handle = j; } w->eb.buffers_ptr = to_user_pointer(w->obj); w->eb.buffer_count = j + 1; w->eb.rsvd1 = get_ctxid(wrk, w); - if (flags & SWAPVCS && engine == VCS1) - engine = VCS2; - else if (flags & SWAPVCS && engine == VCS2) - engine = VCS1; eb_update_flags(wrk, w, engine, flags); #ifdef DEBUG printf("%u: %u:|", w->idx, w->eb.buffer_count); @@ -1528,7 +1359,7 @@ set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask) if (slice_mask == -1) slice_mask = device_sseu.slice_mask; - if (ctx->engine_map && ctx->wants_balance) { + if (ctx->engine_map && ctx->load_balance) { sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX; sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; sseu.engine.engine_instance = 0; @@ -1569,48 +1400,20 @@ static size_t sizeof_engines_bond(int count) static int prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) { - unsigned int ctx_vcs; + uint32_t share_vm = 0; int max_ctx = -1; struct w_step *w; int i, j; wrk->id = id; - wrk->prng = rand(); wrk->bb_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); wrk->run = true; - ctx_vcs = 0; - if (flags & INITVCSRR) - ctx_vcs = id & 1; - wrk->vcs_rr = ctx_vcs; - - if (flags & GLOBAL_BALANCE) { - int ret = pthread_mutex_init(&wrk->mutex, NULL); - igt_assert(ret == 0); - } - - if (flags & SEQNO) { - if (!(flags & GLOBAL_BALANCE) || id == 0) { - uint32_t handle; - - handle = gem_create(fd, 4096); - gem_set_caching(fd, handle, I915_CACHING_CACHED); - wrk->status_object[0].handle = handle; - wrk->status_page = gem_mmap__cpu(fd, handle, 0, 4096, - PROT_READ); - - handle = gem_create(fd, 4096); - wrk->status_object[1].handle = handle; - wrk->status_cs = gem_mmap__wc(fd, handle, - 0, 4096, PROT_WRITE); - } - } - /* * Pre-scan workload steps to allocate context list storage. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - int ctx = w->context * 2 + 1; /* Odd slots are special. */ + int ctx = w->context + 1; int delta; w->wrk = wrk; @@ -1630,27 +1433,16 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) } /* - * Identify if contexts target specific engine instances and if they - * want to be balanced. - * * Transfer over engine map configuration from the workload step. */ - for (j = 0; j < wrk->nr_ctxs; j += 2) { + for (j = 0; j < wrk->nr_ctxs; j++) { struct ctx *ctx = &wrk->ctx_list[j]; - bool targets = false; - bool balance = false; - for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - if (w->context != (j / 2)) + if (w->context != j) continue; - if (w->type == BATCH) { - if (w->engine == VCS) - balance = true; - else - targets = true; - } else if (w->type == ENGINE_MAP) { + if (w->type == ENGINE_MAP) { ctx->engine_map = w->engine_map; ctx->engine_map_count = w->engine_map_count; } else if (w->type == LOAD_BALANCE) { @@ -1658,9 +1450,9 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) wsim_err("Load balancing needs an engine map!\n"); return 1; } - ctx->wants_balance = w->load_balance; + ctx->load_balance = w->load_balance; } else if (w->type == BOND) { - if (!ctx->wants_balance) { + if (!ctx->load_balance) { wsim_err("Engine bonds need load balancing engine map!\n"); return 1; } @@ -1675,133 +1467,53 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) w->bond_master; } } - - wrk->ctx_list[j].targets_instance = targets; - if (flags & I915) - wrk->ctx_list[j].wants_balance |= balance; - } - - /* - * Ensure VCS is not allowed with engine map contexts. - */ - for (j = 0; j < wrk->nr_ctxs; j += 2) { - for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - if (w->context != (j / 2)) - continue; - - if (w->type != BATCH) - continue; - - if (wrk->ctx_list[j].engine_map && - !wrk->ctx_list[j].wants_balance && - (w->engine == VCS || w->engine == DEFAULT)) { - wsim_err("Batches targetting engine maps must use explicit engines!\n"); - return -1; - } - } } - /* * Create and configure contexts. */ - for (i = 0; i < wrk->nr_ctxs; i += 2) { + for (i = 0; i < wrk->nr_ctxs; i++) { + struct drm_i915_gem_context_create_ext_setparam ext = { + .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM, + .param.param = I915_CONTEXT_PARAM_VM, + }; + struct drm_i915_gem_context_create_ext args = { }; struct ctx *ctx = &wrk->ctx_list[i]; - uint32_t ctx_id, share_vm = 0; + uint32_t ctx_id; - if (ctx->id) - continue; + igt_assert(!ctx->id); - if ((flags & I915) || ctx->engine_map) { - struct drm_i915_gem_context_create_ext_setparam ext = { - .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM, - .param.param = I915_CONTEXT_PARAM_VM, + /* Find existing context to share ppgtt with. */ + for (j = 0; !share_vm && j < wrk->nr_ctxs; j++) { + struct drm_i915_gem_context_param param = { + .param = I915_CONTEXT_PARAM_VM, + .ctx_id = wrk->ctx_list[j].id, }; - struct drm_i915_gem_context_create_ext args = { }; - - /* Find existing context to share ppgtt with. */ - for (j = 0; j < wrk->nr_ctxs; j++) { - struct drm_i915_gem_context_param param = { - .param = I915_CONTEXT_PARAM_VM, - }; - - if (!wrk->ctx_list[j].id) - continue; - param.ctx_id = wrk->ctx_list[j].id; - - gem_context_get_param(fd, ¶m); - igt_assert(param.value); - - share_vm = param.value; - - ext.param.value = share_vm; - args.flags = - I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS; - args.extensions = to_user_pointer(&ext); - break; - } - - if ((!ctx->engine_map && !ctx->targets_instance) || - (ctx->engine_map && ctx->wants_balance)) - args.flags |= - I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE; - - drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, - &args); + if (!param.ctx_id) + continue; - ctx_id = args.ctx_id; - } else { - struct drm_i915_gem_context_create args = {}; + gem_context_get_param(fd, ¶m); + igt_assert(param.value); + share_vm = param.value; + break; + } - drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &args); - ctx_id = args.ctx_id; + if (share_vm) { + ext.param.value = share_vm; + args.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS; + args.extensions = to_user_pointer(&ext); } - igt_assert(ctx_id); + drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &args); + igt_assert(args.ctx_id); + + ctx_id = args.ctx_id; ctx->id = ctx_id; ctx->sseu = device_sseu.slice_mask; - if (flags & GLOBAL_BALANCE) { - ctx->static_vcs = context_vcs_rr; - context_vcs_rr ^= 1; - } else { - ctx->static_vcs = ctx_vcs; - ctx_vcs ^= 1; - } - __configure_context(ctx_id, wrk->prio); - /* - * Do we need a separate context to satisfy this workloads which - * both want to target specific engines and be balanced by i915? - */ - if ((flags & I915) && ctx->wants_balance && - ctx->targets_instance && !ctx->engine_map) { - struct drm_i915_gem_context_create_ext_setparam ext = { - .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM, - .param.param = I915_CONTEXT_PARAM_VM, - .param.value = share_vm, - }; - struct drm_i915_gem_context_create_ext args = { - .extensions = to_user_pointer(&ext), - .flags = - I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS | - I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE, - }; - - igt_assert(share_vm); - - drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, - &args); - - igt_assert(args.ctx_id); - ctx_id = args.ctx_id; - wrk->ctx_list[i + 1].id = args.ctx_id; - - __configure_context(ctx_id, wrk->prio); - } - if (ctx->engine_map) { struct i915_context_param_engines *set_engines = alloca0(sizeof_param_engines(ctx->engine_map_count + 1)); @@ -1815,7 +1527,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) }; struct i915_context_engines_bond *last = NULL; - if (ctx->wants_balance) { + if (ctx->load_balance) { set_engines->extensions = to_user_pointer(load_balance); @@ -1869,34 +1581,6 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) } load_balance->base.next_extension = to_user_pointer(last); - gem_context_set_param(fd, ¶m); - } else if (ctx->wants_balance) { - const unsigned int count = num_engines_in_class(VCS); - struct i915_context_engines_load_balance *load_balance = - alloca0(sizeof_load_balance(count)); - struct i915_context_param_engines *set_engines = - alloca0(sizeof_param_engines(count + 1)); - struct drm_i915_gem_context_param param = { - .ctx_id = ctx_id, - .param = I915_CONTEXT_PARAM_ENGINES, - .size = sizeof_param_engines(count + 1), - .value = to_user_pointer(set_engines), - }; - - set_engines->extensions = to_user_pointer(load_balance); - - set_engines->engines[0].engine_class = - I915_ENGINE_CLASS_INVALID; - set_engines->engines[0].engine_instance = - I915_ENGINE_CLASS_INVALID_NONE; - fill_engines_class(&set_engines->engines[1], VCS); - - load_balance->base.name = - I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE; - load_balance->num_siblings = count; - - fill_engines_class(&load_balance->engines[0], VCS); - gem_context_set_param(fd, ¶m); } @@ -1904,11 +1588,11 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) /* Set to slice 0 only, one slice. */ ctx->sseu = set_ctx_sseu(ctx, 1); } - - if (share_vm) - vm_destroy(fd, share_vm); } + if (share_vm) + vm_destroy(fd, share_vm); + /* Record default preemption. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == BATCH) @@ -1954,16 +1638,10 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) * Allocate batch buffers. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - unsigned int _flags = flags; - enum intel_engine_id engine = w->engine; - if (w->type != BATCH) continue; - if (engine == VCS) - _flags &= ~SWAPVCS; - - alloc_step_batch(wrk, w, _flags); + alloc_step_batch(wrk, w, flags); } return 0; @@ -1980,602 +1658,6 @@ static int elapsed_us(const struct timespec *start, const struct timespec *end) return elapsed(start, end) * 1e6; } -static enum intel_engine_id get_vcs_engine(unsigned int n) -{ - const enum intel_engine_id vcs_engines[2] = { VCS1, VCS2 }; - - igt_assert(n < ARRAY_SIZE(vcs_engines)); - - return vcs_engines[n]; -} - -static uint32_t new_seqno(struct workload *wrk, enum intel_engine_id engine) -{ - uint32_t seqno; - int ret; - - if (wrk->flags & GLOBAL_BALANCE) { - igt_assert(wrk->global_wrk); - wrk = wrk->global_wrk; - - ret = pthread_mutex_lock(&wrk->mutex); - igt_assert(ret == 0); - } - - seqno = ++wrk->seqno[engine]; - - if (wrk->flags & GLOBAL_BALANCE) { - ret = pthread_mutex_unlock(&wrk->mutex); - igt_assert(ret == 0); - } - - return seqno; -} - -static uint32_t -current_seqno(struct workload *wrk, enum intel_engine_id engine) -{ - if (wrk->flags & GLOBAL_BALANCE) - return wrk->global_wrk->seqno[engine]; - else - return wrk->seqno[engine]; -} - -static uint32_t -read_status_page(struct workload *wrk, unsigned int idx) -{ - if (wrk->flags & GLOBAL_BALANCE) - return READ_ONCE(wrk->global_wrk->status_page[idx]); - else - return READ_ONCE(wrk->status_page[idx]); -} - -static uint32_t -current_gpu_seqno(struct workload *wrk, enum intel_engine_id engine) -{ - return read_status_page(wrk, SEQNO_IDX(engine)); -} - -struct workload_balancer { - unsigned int id; - const char *name; - const char *desc; - unsigned int flags; - unsigned int min_gen; - - int (*init)(const struct workload_balancer *balancer, - struct workload *wrk); - unsigned int (*get_qd)(const struct workload_balancer *balancer, - struct workload *wrk, - enum intel_engine_id engine); - enum intel_engine_id (*balance)(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w); -}; - -static enum intel_engine_id -rr_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - unsigned int engine; - - engine = get_vcs_engine(wrk->vcs_rr); - wrk->vcs_rr ^= 1; - - return engine; -} - -static enum intel_engine_id -rand_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return get_vcs_engine(hars_petruska_f54_1_random(&wrk->prng) & 1); -} - -static unsigned int -get_qd_depth(const struct workload_balancer *balancer, - struct workload *wrk, enum intel_engine_id engine) -{ - return current_seqno(wrk, engine) - current_gpu_seqno(wrk, engine); -} - -static enum intel_engine_id -__qd_select_engine(struct workload *wrk, const unsigned long *qd, bool random) -{ - unsigned int n; - - if (qd[VCS1] < qd[VCS2]) - n = 0; - else if (qd[VCS1] > qd[VCS2]) - n = 1; - else if (random) - n = hars_petruska_f54_1_random(&wrk->prng) & 1; - else - n = wrk->vcs_rr; - wrk->vcs_rr = n ^ 1; - - return get_vcs_engine(n); -} - -static enum intel_engine_id -__qd_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w, bool random) -{ - enum intel_engine_id engine; - unsigned long qd[NUM_ENGINES]; - - igt_assert(w->engine == VCS); - - qd[VCS1] = balancer->get_qd(balancer, wrk, VCS1); - wrk->qd_sum[VCS1] += qd[VCS1]; - - qd[VCS2] = balancer->get_qd(balancer, wrk, VCS2); - wrk->qd_sum[VCS2] += qd[VCS2]; - - engine = __qd_select_engine(wrk, qd, random); - -#ifdef DEBUG - printf("qd_balance[%u]: 1:%ld 2:%ld rr:%u = %u\t(%u - %u) (%u - %u)\n", - wrk->id, qd[VCS1], qd[VCS2], wrk->vcs_rr, engine, - current_seqno(wrk, VCS1), current_gpu_seqno(wrk, VCS1), - current_seqno(wrk, VCS2), current_gpu_seqno(wrk, VCS2)); -#endif - return engine; -} - -static enum intel_engine_id -qd_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return __qd_balance(balancer, wrk, w, false); -} - -static enum intel_engine_id -qdr_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return __qd_balance(balancer, wrk, w, true); -} - -static enum intel_engine_id -qdavg_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - unsigned long qd[NUM_ENGINES]; - unsigned int engine; - - igt_assert(w->engine == VCS); - - for (engine = VCS1; engine <= VCS2; engine++) { - qd[engine] = balancer->get_qd(balancer, wrk, engine); - wrk->qd_sum[engine] += qd[engine]; - - ewma_rt_add(&wrk->rt.avg[engine], qd[engine]); - qd[engine] = ewma_rt_read(&wrk->rt.avg[engine]); - } - - engine = __qd_select_engine(wrk, qd, false); -#ifdef DEBUG - printf("qdavg_balance[%u]: 1:%ld 2:%ld rr:%u = %u\t(%u - %u) (%u - %u)\n", - wrk->id, qd[VCS1], qd[VCS2], wrk->vcs_rr, engine, - current_seqno(wrk, VCS1), current_gpu_seqno(wrk, VCS1), - current_seqno(wrk, VCS2), current_gpu_seqno(wrk, VCS2)); -#endif - return engine; -} - -static enum intel_engine_id -__rt_select_engine(struct workload *wrk, unsigned long *qd, bool random) -{ - qd[VCS1] >>= 10; - qd[VCS2] >>= 10; - - return __qd_select_engine(wrk, qd, random); -} - -struct rt_depth { - uint32_t seqno; - uint32_t submitted; - uint32_t completed; -}; - -static void get_rt_depth(struct workload *wrk, - unsigned int engine, - struct rt_depth *rt) -{ - const unsigned int idx = SEQNO_IDX(engine); - uint32_t latch; - - do { - latch = read_status_page(wrk, idx + 3); - rt->submitted = read_status_page(wrk, idx + 1); - rt->completed = read_status_page(wrk, idx + 2); - rt->seqno = read_status_page(wrk, idx); - } while (latch != rt->seqno); -} - -static enum intel_engine_id -__rt_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w, bool random) -{ - unsigned long qd[NUM_ENGINES]; - unsigned int engine; - - igt_assert(w->engine == VCS); - - /* Estimate the "speed" of the most recent batch - * (finish time - submit time) - * and use that as an approximate for the total remaining time for - * all batches on that engine, plus the time we expect this batch to - * take. We try to keep the total balanced between the engines. - */ - for (engine = VCS1; engine <= VCS2; engine++) { - struct rt_depth rt; - - get_rt_depth(wrk, engine, &rt); - qd[engine] = current_seqno(wrk, engine) - rt.seqno; - wrk->qd_sum[engine] += qd[engine]; - qd[engine] = (qd[engine] + 1) * (rt.completed - rt.submitted); -#ifdef DEBUG - printf("rt[0] = %d (%d - %d) x %d (%d - %d) = %ld\n", - current_seqno(wrk, engine) - rt.seqno, - current_seqno(wrk, engine), rt.seqno, - rt.completed - rt.submitted, - rt.completed, rt.submitted, - qd[engine]); -#endif - } - - return __rt_select_engine(wrk, qd, random); -} - -static enum intel_engine_id -rt_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - - return __rt_balance(balancer, wrk, w, false); -} - -static enum intel_engine_id -rtr_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return __rt_balance(balancer, wrk, w, true); -} - -static enum intel_engine_id -rtavg_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - unsigned long qd[NUM_ENGINES]; - unsigned int engine; - - igt_assert(w->engine == VCS); - - /* Estimate the average "speed" of the most recent batches - * (finish time - submit time) - * and use that as an approximate for the total remaining time for - * all batches on that engine plus the time we expect to execute in. - * We try to keep the total remaining balanced between the engines. - */ - for (engine = VCS1; engine <= VCS2; engine++) { - struct rt_depth rt; - - get_rt_depth(wrk, engine, &rt); - if (rt.seqno != wrk->rt.last[engine]) { - igt_assert((long)(rt.completed - rt.submitted) > 0); - ewma_rt_add(&wrk->rt.avg[engine], - rt.completed - rt.submitted); - wrk->rt.last[engine] = rt.seqno; - } - qd[engine] = current_seqno(wrk, engine) - rt.seqno; - wrk->qd_sum[engine] += qd[engine]; - qd[engine] = - (qd[engine] + 1) * ewma_rt_read(&wrk->rt.avg[engine]); - -#ifdef DEBUG - printf("rtavg[%d] = %d (%d - %d) x %ld (%d) = %ld\n", - engine, - current_seqno(wrk, engine) - rt.seqno, - current_seqno(wrk, engine), rt.seqno, - ewma_rt_read(&wrk->rt.avg[engine]), - rt.completed - rt.submitted, - qd[engine]); -#endif - } - - return __rt_select_engine(wrk, qd, false); -} - -static enum intel_engine_id -context_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return get_vcs_engine(__get_ctx(wrk, w)->static_vcs); -} - -static unsigned int -get_engine_busy(const struct workload_balancer *balancer, - struct workload *wrk, enum intel_engine_id engine) -{ - struct busy_balancer *bb = &wrk->busy_balancer; - - if (engine == VCS2 && (wrk->flags & VCS2REMAP)) - engine = BCS; - - return bb->busy[bb->engine_map[engine]]; -} - -static void -get_pmu_stats(const struct workload_balancer *b, struct workload *wrk) -{ - struct busy_balancer *bb = &wrk->busy_balancer; - uint64_t val[7]; - unsigned int i; - - igt_assert_eq(read(bb->fd, val, sizeof(val)), - (2 + bb->num_engines) * sizeof(uint64_t)); - - if (!bb->first) { - for (i = 0; i < bb->num_engines; i++) { - double d; - - d = (val[2 + i] - bb->prev[i]) * 100; - d /= val[1] - bb->t_prev; - bb->busy[i] = d; - } - } - - for (i = 0; i < bb->num_engines; i++) - bb->prev[i] = val[2 + i]; - - bb->t_prev = val[1]; - bb->first = false; -} - -static enum intel_engine_id -busy_avg_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - get_pmu_stats(balancer, wrk); - - return qdavg_balance(balancer, wrk, w); -} - -static enum intel_engine_id -busy_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - get_pmu_stats(balancer, wrk); - - return qd_balance(balancer, wrk, w); -} - -static int -busy_init(const struct workload_balancer *balancer, struct workload *wrk) -{ - struct busy_balancer *bb = &wrk->busy_balancer; - struct engine_desc { - unsigned class, inst; - enum intel_engine_id id; - } *d, engines[] = { - { I915_ENGINE_CLASS_RENDER, 0, RCS }, - { I915_ENGINE_CLASS_COPY, 0, BCS }, - { I915_ENGINE_CLASS_VIDEO, 0, VCS1 }, - { I915_ENGINE_CLASS_VIDEO, 1, VCS2 }, - { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, VECS }, - { 0, 0, VCS } - }; - - bb->num_engines = 0; - bb->first = true; - bb->fd = -1; - - for (d = &engines[0]; d->id != VCS; d++) { - int pfd; - - pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, - d->inst), - bb->fd); - if (pfd < 0) { - if (d->id != VCS2) - return -(10 + bb->num_engines); - else - continue; - } - - if (bb->num_engines == 0) - bb->fd = pfd; - - bb->engine_map[d->id] = bb->num_engines++; - } - - if (bb->num_engines < 5 && !(wrk->flags & VCS2REMAP)) - return -1; - - return 0; -} - -static const struct workload_balancer all_balancers[] = { - { - .id = 0, - .name = "rr", - .desc = "Simple round-robin.", - .balance = rr_balance, - }, - { - .id = 6, - .name = "rand", - .desc = "Random selection.", - .balance = rand_balance, - }, - { - .id = 1, - .name = "qd", - .desc = "Queue depth estimation with round-robin on equal depth.", - .flags = SEQNO, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = qd_balance, - }, - { - .id = 5, - .name = "qdr", - .desc = "Queue depth estimation with random selection on equal depth.", - .flags = SEQNO, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = qdr_balance, - }, - { - .id = 7, - .name = "qdavg", - .desc = "Like qd, but using an average queue depth estimator.", - .flags = SEQNO, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = qdavg_balance, - }, - { - .id = 2, - .name = "rt", - .desc = "Queue depth plus last runtime estimation.", - .flags = SEQNO | RT, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = rt_balance, - }, - { - .id = 3, - .name = "rtr", - .desc = "Like rt but with random engine selection on equal depth.", - .flags = SEQNO | RT, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = rtr_balance, - }, - { - .id = 4, - .name = "rtavg", - .desc = "Improved version rt tracking average execution speed per engine.", - .flags = SEQNO | RT, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = rtavg_balance, - }, - { - .id = 8, - .name = "context", - .desc = "Static round-robin VCS assignment at context creation.", - .balance = context_balance, - }, - { - .id = 9, - .name = "busy", - .desc = "Engine busyness based balancing.", - .init = busy_init, - .get_qd = get_engine_busy, - .balance = busy_balance, - }, - { - .id = 10, - .name = "busy-avg", - .desc = "Average engine busyness based balancing.", - .init = busy_init, - .get_qd = get_engine_busy, - .balance = busy_avg_balance, - }, - { - .id = 11, - .name = "i915", - .desc = "i915 balancing.", - .flags = I915, - }, -}; - -static unsigned int -global_get_qd(const struct workload_balancer *balancer, - struct workload *wrk, enum intel_engine_id engine) -{ - igt_assert(wrk->global_wrk); - igt_assert(wrk->global_balancer); - - return wrk->global_balancer->get_qd(wrk->global_balancer, - wrk->global_wrk, engine); -} - -static enum intel_engine_id -global_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - enum intel_engine_id engine; - int ret; - - igt_assert(wrk->global_wrk); - igt_assert(wrk->global_balancer); - - wrk = wrk->global_wrk; - - ret = pthread_mutex_lock(&wrk->mutex); - igt_assert(ret == 0); - - engine = wrk->global_balancer->balance(wrk->global_balancer, wrk, w); - - ret = pthread_mutex_unlock(&wrk->mutex); - igt_assert(ret == 0); - - return engine; -} - -static const struct workload_balancer global_balancer = { - .id = ~0, - .name = "global", - .desc = "Global balancer", - .get_qd = global_get_qd, - .balance = global_balance, - }; - -static void -update_bb_seqno(struct w_step *w, enum intel_engine_id engine, uint32_t seqno) -{ - gem_set_domain(fd, w->bb_handle, - I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); - - w->reloc[0].delta = SEQNO_OFFSET(engine); - - *w->seqno_value = seqno; - *w->seqno_address = w->reloc[0].presumed_offset + w->reloc[0].delta; - - /* If not using NO_RELOC, force the relocations */ - if (!(w->eb.flags & I915_EXEC_NO_RELOC)) - w->reloc[0].presumed_offset = -1; -} - -static void -update_bb_rt(struct w_step *w, enum intel_engine_id engine, uint32_t seqno) -{ - gem_set_domain(fd, w->bb_handle, - I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); - - w->reloc[1].delta = SEQNO_OFFSET(engine) + sizeof(uint32_t); - w->reloc[2].delta = SEQNO_OFFSET(engine) + 2 * sizeof(uint32_t); - w->reloc[3].delta = SEQNO_OFFSET(engine) + 3 * sizeof(uint32_t); - - *w->latch_value = seqno; - *w->latch_address = w->reloc[3].presumed_offset + w->reloc[3].delta; - - *w->rt0_value = *REG(RCS_TIMESTAMP); - *w->rt0_address = w->reloc[1].presumed_offset + w->reloc[1].delta; - *w->rt1_address = w->reloc[2].presumed_offset + w->reloc[2].delta; - - /* If not using NO_RELOC, force the relocations */ - if (!(w->eb.flags & I915_EXEC_NO_RELOC)) { - w->reloc[1].presumed_offset = -1; - w->reloc[2].presumed_offset = -1; - w->reloc[3].presumed_offset = -1; - } -} - static void update_bb_start(struct w_step *w) { @@ -2606,123 +1688,13 @@ static void w_sync_to(struct workload *wrk, struct w_step *w, int target) gem_sync(fd, wrk->steps[target].obj[0].handle); } -static uint32_t *get_status_cs(struct workload *wrk) -{ - return wrk->status_cs; -} - -#define INIT_CLOCKS 0x1 -#define INIT_ALL (INIT_CLOCKS) -static void init_status_page(struct workload *wrk, unsigned int flags) -{ - struct drm_i915_gem_relocation_entry reloc[4] = {}; - struct drm_i915_gem_exec_object2 *status_object = - get_status_objects(wrk); - struct drm_i915_gem_execbuffer2 eb = { - .buffer_count = ARRAY_SIZE(wrk->status_object), - .buffers_ptr = to_user_pointer(status_object) - }; - uint32_t *base = get_status_cs(wrk); - - /* Want to make sure that the balancer has a reasonable view of - * the background busyness of each engine. To do that we occasionally - * send a dummy batch down the pipeline. - */ - - if (!base) - return; - - gem_set_domain(fd, status_object[1].handle, - I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); - - status_object[1].relocs_ptr = to_user_pointer(reloc); - status_object[1].relocation_count = 2; - if (flags & INIT_CLOCKS) - status_object[1].relocation_count += 2; - - for (int engine = 0; engine < NUM_ENGINES; engine++) { - struct drm_i915_gem_relocation_entry *r = reloc; - uint64_t presumed_offset = status_object[0].offset; - uint32_t offset = engine * 128; - uint32_t *cs = base + offset / sizeof(*cs); - uint64_t addr; - - r->offset = offset + sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = MI_STORE_DWORD_IMM; - *cs++ = addr; - *cs++ = addr >> 32; - *cs++ = new_seqno(wrk, engine); - offset += 4 * sizeof(uint32_t); - - /* When we are busy, we can just reuse the last set of timings. - * If we have been idle for a while, we want to resample the - * latency on each engine (to measure external load). - */ - if (flags & INIT_CLOCKS) { - r->offset = offset + sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine) + sizeof(uint32_t); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = MI_STORE_DWORD_IMM; - *cs++ = addr; - *cs++ = addr >> 32; - *cs++ = *REG(RCS_TIMESTAMP); - offset += 4 * sizeof(uint32_t); - - r->offset = offset + 2 * sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine) + 2*sizeof(uint32_t); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = 0x24 << 23 | 2; /* MI_STORE_REG_MEM */ - *cs++ = RCS_TIMESTAMP; - *cs++ = addr; - *cs++ = addr >> 32; - offset += 4 * sizeof(uint32_t); - } - - r->offset = offset + sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine) + 3*sizeof(uint32_t); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = MI_STORE_DWORD_IMM; - *cs++ = addr; - *cs++ = addr >> 32; - *cs++ = current_seqno(wrk, engine); - offset += 4 * sizeof(uint32_t); - - *cs++ = MI_BATCH_BUFFER_END; - - eb_set_engine(&eb, engine, wrk->flags); - eb.flags |= I915_EXEC_HANDLE_LUT; - eb.flags |= I915_EXEC_NO_RELOC; - - eb.batch_start_offset = 128 * engine; - - gem_execbuf(fd, &eb); - } -} - static void do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, unsigned int flags) { - uint32_t seqno = new_seqno(wrk, engine); unsigned int i; eb_update_flags(wrk, w, engine, flags); - - if (flags & SEQNO) - update_bb_seqno(w, engine, seqno); - if (flags & RT) - update_bb_rt(w, engine, seqno); - update_bb_start(w); w->eb.batch_start_offset = @@ -2758,9 +1730,8 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, } } -static bool sync_deps(struct workload *wrk, struct w_step *w) +static void sync_deps(struct workload *wrk, struct w_step *w) { - bool synced = false; unsigned int i; for (i = 0; i < w->data_deps.nr; i++) { @@ -2777,11 +1748,7 @@ static bool sync_deps(struct workload *wrk, struct w_step *w) igt_assert(wrk->steps[dep_idx].type == BATCH); gem_sync(fd, wrk->steps[dep_idx].obj[0].handle); - - synced = true; } - - return synced; } static void *run_workload(void *data) @@ -2789,7 +1756,6 @@ static void *run_workload(void *data) struct workload *wrk = (struct workload *)data; struct timespec t_start, t_end; struct w_step *w; - bool last_sync = false; int throttle = -1; int qd_throttle = -1; int count; @@ -2797,7 +1763,6 @@ static void *run_workload(void *data) clock_gettime(CLOCK_MONOTONIC, &t_start); - init_status_page(wrk, INIT_ALL); for (count = 0; wrk->run && (wrk->background || count < wrk->repeat); count++) { unsigned int cur_seqno = wrk->sync_seqno; @@ -2898,21 +1863,8 @@ static void *run_workload(void *data) igt_assert(w->type == BATCH); - if ((wrk->flags & DEPSYNC) && engine == VCS) - last_sync = sync_deps(wrk, w); - - if (last_sync && (wrk->flags & HEARTBEAT)) - init_status_page(wrk, 0); - - last_sync = false; - - wrk->nr_bb[engine]++; - if (engine == VCS && wrk->balancer && - wrk->balancer->balance) { - engine = wrk->balancer->balance(wrk->balancer, - wrk, w); - wrk->nr_bb[engine]++; - } + if (wrk->flags & DEPSYNC) + sync_deps(wrk, w); if (throttle > 0) w_sync_to(wrk, w, i - throttle); @@ -2930,10 +1882,8 @@ static void *run_workload(void *data) if (!wrk->run) break; - if (w->sync) { + if (w->sync) gem_sync(fd, w->obj[0].handle); - last_sync = true; - } if (qd_throttle > 0) { while (wrk->nrequest[engine] > qd_throttle) { @@ -2943,7 +1893,6 @@ static void *run_workload(void *data) s, rq_link); gem_sync(fd, s->obj[0].handle); - last_sync = true; s->request = -1; igt_list_del(&s->rq_link); @@ -2986,13 +1935,6 @@ static void *run_workload(void *data) printf("%c%u: %.3fs elapsed (%d cycles, %.3f workloads/s).", wrk->background ? ' ' : '*', wrk->id, t, count, count / t); - if (wrk->balancer) - printf(" %lu (%lu + %lu) total VCS batches.", - wrk->nr_bb[VCS], wrk->nr_bb[VCS1], wrk->nr_bb[VCS2]); - if (wrk->balancer && wrk->balancer->get_qd) - printf(" Average queue depths %.3f, %.3f.", - (double)wrk->qd_sum[VCS1] / wrk->nr_bb[VCS], - (double)wrk->qd_sum[VCS2] / wrk->nr_bb[VCS]); putchar('\n'); } @@ -3114,8 +2056,6 @@ calibrate_engines(void) static void print_help(void) { - unsigned int i; - puts( "Usage: gem_wsim [OPTIONS]\n" "\n" @@ -3145,32 +2085,11 @@ static void print_help(void) " -a <desc|path> Append a workload to all other workloads.\n" " -r <n> How many times to emit the workload.\n" " -c <n> Fork N clients emitting the workload simultaneously.\n" -" -x Swap VCS1 and VCS2 engines in every other client.\n" -" -b <n> Load balancing to use.\n" -" Available load balancers are:" - ); - - for (i = 0; i < ARRAY_SIZE(all_balancers); i++) { - igt_assert(all_balancers[i].desc); - printf( -" %s (%u): %s\n", - all_balancers[i].name, all_balancers[i].id, - all_balancers[i].desc); - } - puts( -" Balancers can be specified either as names or as their id\n" -" number as listed above.\n" -" -2 Remap VCS2 to BCS.\n" -" -R Round-robin initial VCS assignment per client.\n" -" -H Send heartbeat on synchronisation points with seqno based\n" -" balancers. Gives better engine busyness view in some cases.\n" -" -s Turn on small SSEU config for the next workload on the\n" -" command line. Subsequent -s switches it off.\n" -" -S Synchronize the sequence of random batch durations between\n" -" clients.\n" -" -G Global load balancing - a single load balancer will be shared\n" -" between all clients and there will be a single seqno domain.\n" -" -d Sync between data dependencies in userspace." +" -s Turn on small SSEU config for the next workload on the\n" +" command line. Subsequent -s switches it off.\n" +" -S Synchronize the sequence of random batch durations between\n" +" clients.\n" +" -d Sync between data dependencies in userspace." ); } @@ -3218,62 +2137,6 @@ add_workload_arg(struct w_arg *w_args, unsigned int nr_args, char *w_arg, return w_args; } -static int find_balancer_by_name(char *name) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(all_balancers); i++) { - if (!strcasecmp(name, all_balancers[i].name)) - return all_balancers[i].id; - } - - return -1; -} - -static const struct workload_balancer *find_balancer_by_id(unsigned int id) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(all_balancers); i++) { - if (id == all_balancers[i].id) - return &all_balancers[i]; - } - - return NULL; -} - -static void init_clocks(void) -{ - struct timespec t_start, t_end; - uint32_t rcs_start, rcs_end; - double overhead, t; - - if (verbose <= 1) - return; - - clock_gettime(CLOCK_MONOTONIC, &t_start); - for (int i = 0; i < 100; i++) - rcs_start = *REG(RCS_TIMESTAMP); - clock_gettime(CLOCK_MONOTONIC, &t_end); - overhead = 2 * elapsed(&t_start, &t_end) / 100; - - clock_gettime(CLOCK_MONOTONIC, &t_start); - for (int i = 0; i < 100; i++) - clock_gettime(CLOCK_MONOTONIC, &t_end); - clock_gettime(CLOCK_MONOTONIC, &t_end); - overhead += elapsed(&t_start, &t_end) / 100; - - clock_gettime(CLOCK_MONOTONIC, &t_start); - rcs_start = *REG(RCS_TIMESTAMP); - usleep(100); - rcs_end = *REG(RCS_TIMESTAMP); - clock_gettime(CLOCK_MONOTONIC, &t_end); - - t = elapsed(&t_start, &t_end) - overhead; - printf("%d cycles in %.1fus, i.e. 1024 cycles takes %1.fus\n", - rcs_end - rcs_start, 1e6*t, 1024e6 * t / (rcs_end - rcs_start)); -} - int main(int argc, char **argv) { unsigned int repeat = 1; @@ -3287,9 +2150,7 @@ int main(int argc, char **argv) char *append_workload_arg = NULL; struct w_arg *w_args = NULL; unsigned int tolerance_pct = 1; - const struct workload_balancer *balancer = NULL; int exitcode = EXIT_FAILURE; - char *endptr = NULL; int prio = 0; double t; int i, c; @@ -3304,17 +2165,13 @@ int main(int argc, char **argv) * This minimizes the gap in engine utilization tracking when observed * via external tools like trace.pl. */ - fd = __drm_open_driver(DRIVER_INTEL); + fd = __drm_open_driver_render(DRIVER_INTEL); igt_require(fd); - intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd); - - init_clocks(); - master_prng = time(NULL); while ((c = getopt(argc, argv, - "Thqv2RsSHxGdc:n:r:w:W:a:t:b:p:I:")) != -1) { + "ThqvsSdc:n:r:w:W:a:t:p:I:")) != -1) { switch (c) { case 'W': if (master_workload >= 0) { @@ -3413,52 +2270,15 @@ int main(int argc, char **argv) case 'v': verbose++; break; - case 'x': - flags |= SWAPVCS; - break; - case '2': - flags |= VCS2REMAP; - break; - case 'R': - flags |= INITVCSRR; - break; case 'S': flags |= SYNCEDCLIENTS; break; case 's': flags ^= SSEU; break; - case 'H': - flags |= HEARTBEAT; - break; - case 'G': - flags |= GLOBAL_BALANCE; - break; case 'd': flags |= DEPSYNC; break; - case 'b': - i = find_balancer_by_name(optarg); - if (i < 0) { - i = strtol(optarg, &endptr, 0); - if (endptr && *endptr) - i = -1; - } - - if (i >= 0) { - balancer = find_balancer_by_id(i); - if (balancer) { - igt_assert(intel_gen(intel_get_drm_devid(fd)) >= balancer->min_gen); - flags |= BALANCE | balancer->flags; - } - } - - if (!balancer) { - wsim_err("Unknown balancing mode '%s'!\n", - optarg); - goto err; - } - break; case 'I': master_prng = strtol(optarg, NULL, 0); break; @@ -3470,16 +2290,6 @@ int main(int argc, char **argv) } } - if ((flags & HEARTBEAT) && !(flags & SEQNO)) { - wsim_err("Heartbeat needs a seqno based balancer!\n"); - goto err; - } - - if ((flags & VCS2REMAP) && (flags & I915)) { - wsim_err("VCS remapping not supported with i915 balancing!\n"); - goto err; - } - if (!has_nop_calibration) { if (verbose > 1) { printf("Calibrating nop delays with %u%% tolerance...\n", @@ -3519,11 +2329,6 @@ int main(int argc, char **argv) goto err; } - if ((flags & GLOBAL_BALANCE) && !balancer) { - wsim_err("Balancer not specified in global balancing mode!\n"); - goto err; - } - if (append_workload_arg) { append_workload_arg = load_workload_descriptor(append_workload_arg); if (!append_workload_arg) { @@ -3566,19 +2371,6 @@ int main(int argc, char **argv) printf("Random seed is %u.\n", master_prng); print_engine_calibrations(); printf("%u client%s.\n", clients, clients > 1 ? "s" : ""); - if (flags & SWAPVCS) - printf("Swapping VCS rings between clients.\n"); - if (flags & GLOBAL_BALANCE) { - if (flags & I915) { - printf("Ignoring global balancing with i915!\n"); - flags &= ~GLOBAL_BALANCE; - } else { - printf("Using %s balancer in global mode.\n", - balancer->name); - } - } else if (balancer) { - printf("Using %s balancer.\n", balancer->name); - } } srand(master_prng); @@ -3591,41 +2383,18 @@ int main(int argc, char **argv) igt_assert(w); for (i = 0; i < clients; i++) { - unsigned int flags_ = flags; - w[i] = clone_workload(wrk[nr_w_args > 1 ? i : 0]); - if (flags & SWAPVCS && i & 1) - flags_ &= ~SWAPVCS; - - if ((flags & GLOBAL_BALANCE) && !(flags & I915)) { - w[i]->balancer = &global_balancer; - w[i]->global_wrk = w[0]; - w[i]->global_balancer = balancer; - } else { - w[i]->balancer = balancer; - } - w[i]->flags = flags; w[i]->repeat = repeat; w[i]->background = master_workload >= 0 && i != master_workload; w[i]->print_stats = verbose > 1 || (verbose > 0 && master_workload == i); - if (prepare_workload(i, w[i], flags_)) { + if (prepare_workload(i, w[i], flags)) { wsim_err("Failed to prepare workload %u!\n", i); goto err; } - - - if (balancer && balancer->init) { - int ret = balancer->init(balancer, w[i]); - if (ret) { - wsim_err("Failed to initialize balancing! (%u=%d)\n", - i, ret); - goto err; - } - } } clock_gettime(CLOCK_MONOTONIC, &t_start); @@ -3670,6 +2439,5 @@ int main(int argc, char **argv) out: exitcode = EXIT_SUCCESS; err: - intel_register_access_fini(&mmio_data); return exitcode; } diff --git a/benchmarks/ilog2.h b/benchmarks/ilog2.h deleted file mode 100644 index 596d7c23e0d1..000000000000 --- a/benchmarks/ilog2.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef ILOG2_H -#define ILOG2_H - -#include <stdint.h> - -static inline int fls(int x) -{ - int r = -1; - asm("bsrl %1,%0" : "=r" (r) : "rm" (x), "0" (-1)); - return r + 1; -} - -static inline int fls64(__u64 x) -{ - int r = -1; - asm("bsrq %1,%q0" : "+r" (r) : "rm" (x)); - return r + 1; -} - -static inline __attribute__((const)) -int __ilog2_u32(uint32_t n) -{ - return fls(n) - 1; -} - -static inline __attribute__((const)) -int __ilog2_u64(uint64_t n) -{ - return fls64(n) - 1; -} - -#define ilog2(n) \ -( \ - __builtin_constant_p(n) ? ( \ - (n) < 2 ? 0 : \ - (n) & (1ULL << 63) ? 63 : \ - (n) & (1ULL << 62) ? 62 : \ - (n) & (1ULL << 61) ? 61 : \ - (n) & (1ULL << 60) ? 60 : \ - (n) & (1ULL << 59) ? 59 : \ - (n) & (1ULL << 58) ? 58 : \ - (n) & (1ULL << 57) ? 57 : \ - (n) & (1ULL << 56) ? 56 : \ - (n) & (1ULL << 55) ? 55 : \ - (n) & (1ULL << 54) ? 54 : \ - (n) & (1ULL << 53) ? 53 : \ - (n) & (1ULL << 52) ? 52 : \ - (n) & (1ULL << 51) ? 51 : \ - (n) & (1ULL << 50) ? 50 : \ - (n) & (1ULL << 49) ? 49 : \ - (n) & (1ULL << 48) ? 48 : \ - (n) & (1ULL << 47) ? 47 : \ - (n) & (1ULL << 46) ? 46 : \ - (n) & (1ULL << 45) ? 45 : \ - (n) & (1ULL << 44) ? 44 : \ - (n) & (1ULL << 43) ? 43 : \ - (n) & (1ULL << 42) ? 42 : \ - (n) & (1ULL << 41) ? 41 : \ - (n) & (1ULL << 40) ? 40 : \ - (n) & (1ULL << 39) ? 39 : \ - (n) & (1ULL << 38) ? 38 : \ - (n) & (1ULL << 37) ? 37 : \ - (n) & (1ULL << 36) ? 36 : \ - (n) & (1ULL << 35) ? 35 : \ - (n) & (1ULL << 34) ? 34 : \ - (n) & (1ULL << 33) ? 33 : \ - (n) & (1ULL << 32) ? 32 : \ - (n) & (1ULL << 31) ? 31 : \ - (n) & (1ULL << 30) ? 30 : \ - (n) & (1ULL << 29) ? 29 : \ - (n) & (1ULL << 28) ? 28 : \ - (n) & (1ULL << 27) ? 27 : \ - (n) & (1ULL << 26) ? 26 : \ - (n) & (1ULL << 25) ? 25 : \ - (n) & (1ULL << 24) ? 24 : \ - (n) & (1ULL << 23) ? 23 : \ - (n) & (1ULL << 22) ? 22 : \ - (n) & (1ULL << 21) ? 21 : \ - (n) & (1ULL << 20) ? 20 : \ - (n) & (1ULL << 19) ? 19 : \ - (n) & (1ULL << 18) ? 18 : \ - (n) & (1ULL << 17) ? 17 : \ - (n) & (1ULL << 16) ? 16 : \ - (n) & (1ULL << 15) ? 15 : \ - (n) & (1ULL << 14) ? 14 : \ - (n) & (1ULL << 13) ? 13 : \ - (n) & (1ULL << 12) ? 12 : \ - (n) & (1ULL << 11) ? 11 : \ - (n) & (1ULL << 10) ? 10 : \ - (n) & (1ULL << 9) ? 9 : \ - (n) & (1ULL << 8) ? 8 : \ - (n) & (1ULL << 7) ? 7 : \ - (n) & (1ULL << 6) ? 6 : \ - (n) & (1ULL << 5) ? 5 : \ - (n) & (1ULL << 4) ? 4 : \ - (n) & (1ULL << 3) ? 3 : \ - (n) & (1ULL << 2) ? 2 : \ - 1 ) : \ - (sizeof(n) <= 4) ? \ - __ilog2_u32(n) : \ - __ilog2_u64(n) \ - ) - -#endif /* ILOG2_H */ diff --git a/benchmarks/meson.build b/benchmarks/meson.build index ef93193b70dd..c70e1aac79c6 100644 --- a/benchmarks/meson.build +++ b/benchmarks/meson.build @@ -11,6 +11,7 @@ benchmark_progs = [ 'gem_prw', 'gem_set_domain', 'gem_syslatency', + 'gem_wsim', 'kms_vblank', 'prime_lookup', 'vgem_mmap', @@ -34,8 +35,3 @@ foreach prog : benchmark_progs install_dir : benchmarksdir, dependencies : igt_deps) endforeach - -executable('gem_wsim', 'gem_wsim.c', - install : true, - install_dir : benchmarksdir, - dependencies : igt_deps + [ lib_igt_perf ]) diff --git a/benchmarks/wsim/media-1080p-player.wsim b/benchmarks/wsim/media-1080p-player.wsim index bcbb0cfd2ad3..c87e1aee4f5d 100644 --- a/benchmarks/wsim/media-1080p-player.wsim +++ b/benchmarks/wsim/media-1080p-player.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.5000-10000.0.0 2.RCS.1000-2000.-1.0 P.3.1 diff --git a/benchmarks/wsim/media_1n2_480p.wsim b/benchmarks/wsim/media_1n2_480p.wsim index 11a4da6bfae8..3ce15ebc3d71 100644 --- a/benchmarks/wsim/media_1n2_480p.wsim +++ b/benchmarks/wsim/media_1n2_480p.wsim @@ -1,9 +1,15 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.1 +12.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n2_asy.wsim b/benchmarks/wsim/media_1n2_asy.wsim index 58c99ca1122c..f9943eb62e8a 100644 --- a/benchmarks/wsim/media_1n2_asy.wsim +++ b/benchmarks/wsim/media_1n2_asy.wsim @@ -1,9 +1,11 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.400-800.-5.0 5.RCS.500-700.-1.0 5.RCS.5000-6000.0.0 -5.VCS.1200-1500.-1.1 +12.VCS.1200-1500.-1.1 diff --git a/benchmarks/wsim/media_1n3_480p.wsim b/benchmarks/wsim/media_1n3_480p.wsim index c724ab28a1f4..4f585fa8a8e0 100644 --- a/benchmarks/wsim/media_1n3_480p.wsim +++ b/benchmarks/wsim/media_1n3_480p.wsim @@ -1,13 +1,21 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.0 +12.VCS.2500-3500.-1.0 6.RCS.1000-2200.-9.0 7.RCS.1000-1400.-1.0 7.RCS.10000-12000.0.0 -7.VCS.2500-3500.-1.1 +13.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n3_asy.wsim b/benchmarks/wsim/media_1n3_asy.wsim index c7588328e3f1..dce7789ec1d8 100644 --- a/benchmarks/wsim/media_1n3_asy.wsim +++ b/benchmarks/wsim/media_1n3_asy.wsim @@ -1,3 +1,11 @@ +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 diff --git a/benchmarks/wsim/media_1n4_480p.wsim b/benchmarks/wsim/media_1n4_480p.wsim index e67fefc3bf17..06fa9adef5eb 100644 --- a/benchmarks/wsim/media_1n4_480p.wsim +++ b/benchmarks/wsim/media_1n4_480p.wsim @@ -1,17 +1,27 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.0 +12.VCS.2500-3500.-1.0 6.RCS.1000-2200.-9.0 7.RCS.1000-1400.-1.0 7.RCS.10000-12000.0.0 -7.VCS.2500-3500.-1.0 +13.VCS.2500-3500.-1.0 8.RCS.1000-2200.-13.0 9.RCS.1000-1400.-1.0 9.RCS.10000-12000.0.0 -9.VCS.2500-3500.-1.1 +14.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n4_asy.wsim b/benchmarks/wsim/media_1n4_asy.wsim index ede4fd7a2205..6dc6b652e903 100644 --- a/benchmarks/wsim/media_1n4_asy.wsim +++ b/benchmarks/wsim/media_1n4_asy.wsim @@ -1,3 +1,13 @@ +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 diff --git a/benchmarks/wsim/media_1n5_480p.wsim b/benchmarks/wsim/media_1n5_480p.wsim index 9e43b9845430..3467a386887a 100644 --- a/benchmarks/wsim/media_1n5_480p.wsim +++ b/benchmarks/wsim/media_1n5_480p.wsim @@ -1,21 +1,33 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 +M.15.VCS +B.15 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.0 +12.VCS.2500-3500.-1.0 6.RCS.1000-2200.-9.0 7.RCS.1000-1400.-1.0 7.RCS.10000-12000.0.0 -7.VCS.2500-3500.-1.0 +13.VCS.2500-3500.-1.0 8.RCS.1000-2200.-13.0 9.RCS.1000-1400.-1.0 9.RCS.10000-12000.0.0 -9.VCS.2500-3500.-1.0 +14.VCS.2500-3500.-1.0 10.RCS.1000-2200.-17.0 11.RCS.1000-1400.-1.0 11.RCS.10000-12000.0.0 -11.VCS.2500-3500.-1.1 +15.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n5_asy.wsim b/benchmarks/wsim/media_1n5_asy.wsim index 78bb4a86dbca..4b205457a8d4 100644 --- a/benchmarks/wsim/media_1n5_asy.wsim +++ b/benchmarks/wsim/media_1n5_asy.wsim @@ -1,3 +1,15 @@ +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 +M.15.VCS +B.15 1.VCS.12000-15000.0.0 2.RCS.2000-3000.-1.0 3.RCS.500-900.-1.0 diff --git a/benchmarks/wsim/media_load_balance_17i7.wsim b/benchmarks/wsim/media_load_balance_17i7.wsim index 0830a3231ea9..bcb1ab2f04fa 100644 --- a/benchmarks/wsim/media_load_balance_17i7.wsim +++ b/benchmarks/wsim/media_load_balance_17i7.wsim @@ -1,7 +1,9 @@ +M.1.VCS +B.1 1.VCS.2800-3200.0.1 -1.RCS.900-1100.-1.0 -1.RCS.3600-3800.0.0 -1.RCS.900-1100.-2.0 +2.RCS.900-1100.-1.0 +2.RCS.3600-3800.0.0 +2.RCS.900-1100.-2.0 1.VCS.2200-2400.-2.0 -1.RCS.4500-4900.-1.0 +2.RCS.4500-4900.-1.0 1.VCS.500-700.-1.1 diff --git a/benchmarks/wsim/media_load_balance_19.wsim b/benchmarks/wsim/media_load_balance_19.wsim index 03890776fda3..88cd34fb6898 100644 --- a/benchmarks/wsim/media_load_balance_19.wsim +++ b/benchmarks/wsim/media_load_balance_19.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 0.VECS.1400-1500.0.0 0.RCS.1000-1500.-1.0 s.-2 @@ -5,6 +7,6 @@ s.-2 1.VCS.1300-1400.0.1 0.VECS.1400-1500.0.0 0.RCS.100-300.-1.1 -1.RCS.1300-1500.0.0 +2.RCS.1300-1500.-3.0 1.VCS.100-300.-1.1 1.VCS.900-1400.0.1 diff --git a/benchmarks/wsim/media_load_balance_4k12u7.wsim b/benchmarks/wsim/media_load_balance_4k12u7.wsim index ff10425b6bec..a417bb18e121 100644 --- a/benchmarks/wsim/media_load_balance_4k12u7.wsim +++ b/benchmarks/wsim/media_load_balance_4k12u7.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.4000-6000.0.0 2.RCS.400-800.-1.0 3.RCS.1900-2200.-1.0 diff --git a/benchmarks/wsim/media_load_balance_fhd26u7.wsim b/benchmarks/wsim/media_load_balance_fhd26u7.wsim index 56114ddc48c2..4c8225e1fe13 100644 --- a/benchmarks/wsim/media_load_balance_fhd26u7.wsim +++ b/benchmarks/wsim/media_load_balance_fhd26u7.wsim @@ -1,25 +1,27 @@ +M.3.VCS +B.3 1.VCS1.1200-1800.0.0 1.VCS1.1900-2100.0.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.200-400.-1.0 2.RCS.1500-2000.0.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.200-400.-1.0 2.RCS.1500-2000.0.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 2.RCS.1500-2000.0.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 diff --git a/benchmarks/wsim/media_load_balance_hd01.wsim b/benchmarks/wsim/media_load_balance_hd01.wsim index 862931521c90..8e7e9d90e435 100644 --- a/benchmarks/wsim/media_load_balance_hd01.wsim +++ b/benchmarks/wsim/media_load_balance_hd01.wsim @@ -1,23 +1,27 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.1400-1900.0.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 s.-17 s.-14 s.-11 diff --git a/benchmarks/wsim/media_load_balance_hd06mp2.wsim b/benchmarks/wsim/media_load_balance_hd06mp2.wsim index 1e1fc003c755..cfe985019a7b 100644 --- a/benchmarks/wsim/media_load_balance_hd06mp2.wsim +++ b/benchmarks/wsim/media_load_balance_hd06mp2.wsim @@ -1,4 +1,8 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 1.VCS.900-1700.0.0 2.RCS.100-400.-1.0 3.RCS.800-900.-1.0 -3.VCS.100-200.-1.1 +4.VCS.100-200.-1.1 diff --git a/benchmarks/wsim/media_load_balance_hd12.wsim b/benchmarks/wsim/media_load_balance_hd12.wsim index 8f3b41ca5ab6..684e6b511762 100644 --- a/benchmarks/wsim/media_load_balance_hd12.wsim +++ b/benchmarks/wsim/media_load_balance_hd12.wsim @@ -1,4 +1,8 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 1.VCS.850-1300.0.0 2.RCS.50-250.-1.0 3.RCS.400-800.-1.0 -3.VCS.100-200.-1.1 +4.VCS.100-200.-1.1 diff --git a/benchmarks/wsim/media_load_balance_hd17i4.wsim b/benchmarks/wsim/media_load_balance_hd17i4.wsim index b6195b605bf7..1430f18df033 100644 --- a/benchmarks/wsim/media_load_balance_hd17i4.wsim +++ b/benchmarks/wsim/media_load_balance_hd17i4.wsim @@ -1,7 +1,11 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.900-1400.0.0 2.RCS.200-300.-1.0 2.RCS.1000-2000.0.0 2.RCS.1000-2000.0.0 -2.VCS.800-1000.-1.0 -1.RCS.2800-3100.-1.0 +3.VCS.800-1000.-1.0 +4.RCS.2800-3100.-1.0 1.VCS.800-1000.-1.1 diff --git a/benchmarks/wsim/media_mfe2_480p.wsim b/benchmarks/wsim/media_mfe2_480p.wsim index 18bc756f1b55..00ef5c3a7574 100644 --- a/benchmarks/wsim/media_mfe2_480p.wsim +++ b/benchmarks/wsim/media_mfe2_480p.wsim @@ -1,3 +1,11 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 +M.7.VCS +B.7 +M.8.VCS +B.8 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.800-1600.-1.0 @@ -5,5 +13,5 @@ 5.RCS.1000-2200.-1.0 6.RCS.800-1600.-1.0 6.RCS.10000-12000.-4.0 -6.VCS.2500-3500.-1.0 -3.VCS.2500-3500.-2.1 +7.VCS.2500-3500.-1.0 +8.VCS.2500-3500.-2.1 diff --git a/benchmarks/wsim/media_mfe3_480p.wsim b/benchmarks/wsim/media_mfe3_480p.wsim index e12a2e6ac29d..3ac4db0eb8ec 100644 --- a/benchmarks/wsim/media_mfe3_480p.wsim +++ b/benchmarks/wsim/media_mfe3_480p.wsim @@ -1,3 +1,15 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 +M.7.VCS +B.7 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.800-1600.-1.0 @@ -8,6 +20,6 @@ 8.RCS.1000-2200.-1.0 9.RCS.800-1600.-1.0 9.RCS.10000-12000.-7/-4.0 -9.VCS.2500-3500.-1.0 -3.VCS.2500-3500.-2.0 -6.VCS.2500-3500.-3.1 +10.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-2.0 +12.VCS.2500-3500.-3.1 diff --git a/benchmarks/wsim/media_mfe4_480p.wsim b/benchmarks/wsim/media_mfe4_480p.wsim index 75d4f67ea4fb..7f6831569908 100644 --- a/benchmarks/wsim/media_mfe4_480p.wsim +++ b/benchmarks/wsim/media_mfe4_480p.wsim @@ -1,3 +1,19 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 +M.7.VCS +B.7 +M.10.VCS +B.10 +M.13.VCS +B.13 +M.14.VCS +B.14 +M.15.VCS +B.15 +M.16.VCS +B.16 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.800-1600.-1.0 @@ -11,7 +27,7 @@ 11.RCS.1000-2200.-1.0 12.RCS.800-1600.-1.0 12.RCS.10000-12000.-4/-7/-10.0 -12.VCS.2500-3500.-1.0 -3.VCS.2500-3500.-2.0 -6.VCS.2500-3500.-3.0 -9.VCS.2500-3500.-4.1 +13.VCS.2500-3500.-1.0 +14.VCS.2500-3500.-2.0 +15.VCS.2500-3500.-3.0 +16.VCS.2500-3500.-4.1 diff --git a/benchmarks/wsim/media_nn_1080p.wsim b/benchmarks/wsim/media_nn_1080p.wsim index f9a3ca1b9963..88c5c772202c 100644 --- a/benchmarks/wsim/media_nn_1080p.wsim +++ b/benchmarks/wsim/media_nn_1080p.wsim @@ -1,3 +1,7 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.13000-17000.0.0 2.RCS.2000-4000.-1.0 3.RCS.3000-5000.-1.0 diff --git a/benchmarks/wsim/media_nn_1080p_s1.wsim b/benchmarks/wsim/media_nn_1080p_s1.wsim index 4fa6ca653000..5b47d2a3c7ec 100644 --- a/benchmarks/wsim/media_nn_1080p_s1.wsim +++ b/benchmarks/wsim/media_nn_1080p_s1.wsim @@ -1,3 +1,5 @@ +M.4.VCS +B.4 f 1.VCS1.6500-8000.f-1.0 1.VCS2.6500-8000.f-2.0 @@ -5,4 +7,4 @@ a.-3 2.RCS.2000-4000.-2/-3.0 3.RCS.3000-5000.-1.0 3.RCS.23000-27000.0.0 -3.VCS.16000-20000.-1.1 +4.VCS.16000-20000.-1.1 diff --git a/benchmarks/wsim/media_nn_1080p_s2.wsim b/benchmarks/wsim/media_nn_1080p_s2.wsim index 68f0acdfb842..e3678b396b42 100644 --- a/benchmarks/wsim/media_nn_1080p_s2.wsim +++ b/benchmarks/wsim/media_nn_1080p_s2.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.13000-17000.0.0 2.RCS.2000-4000.-1.0 3.RCS.3000-5000.-1.0 diff --git a/benchmarks/wsim/media_nn_1080p_s3.wsim b/benchmarks/wsim/media_nn_1080p_s3.wsim index 12368da83dca..ee3b675de9e5 100644 --- a/benchmarks/wsim/media_nn_1080p_s3.wsim +++ b/benchmarks/wsim/media_nn_1080p_s3.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.13000-17000.0.0 2.RCS.2000-4000.-1.0 3.RCS.3000-5000.-1.0 diff --git a/benchmarks/wsim/media_nn_480p.wsim b/benchmarks/wsim/media_nn_480p.wsim index ab64a4569d71..73fc643dc9e5 100644 --- a/benchmarks/wsim/media_nn_480p.wsim +++ b/benchmarks/wsim/media_nn_480p.wsim @@ -1,3 +1,7 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 diff --git a/benchmarks/wsim/vcs_balanced.wsim b/benchmarks/wsim/vcs_balanced.wsim index e8958b8f7f43..78d953fb7551 100644 --- a/benchmarks/wsim/vcs_balanced.wsim +++ b/benchmarks/wsim/vcs_balanced.wsim @@ -1,26 +1,28 @@ q.5 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 +M.1.VCS +B.1 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 diff --git a/scripts/media-bench.pl b/scripts/media-bench.pl deleted file mode 100755 index 1cd8205ff07c..000000000000 --- a/scripts/media-bench.pl +++ /dev/null @@ -1,736 +0,0 @@ -#! /usr/bin/perl -# -# Copyright ? 2017 Intel Corporation -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# - -use strict; -use warnings; -use 5.010; - -use Getopt::Std; - -chomp(my $igt_root = `pwd -P`); -my $wsim = "$igt_root/benchmarks/gem_wsim"; -my $wrk_root = "$igt_root/benchmarks/wsim"; -my $tracepl = "$igt_root/scripts/trace.pl"; -my $tolerance = 0.01; -my $client_target_s = 10; -my $idle_tolerance_pct = 2.0; -my $verbose = 0; -my $gt2 = 0; -my $show_cmds = 0; -my $realtime_target = 0; -my $wps_target = 0; -my $wps_target_param = 0; -my $multi_mode = 0; -my @multi_workloads; -my $w_direct; -my $balancer; -my $nop; -my %opts; - -my @balancers = ( 'rr', 'rand', 'qd', 'qdr', 'qdavg', 'rt', 'rtr', 'rtavg', - 'context', 'busy', 'busy-avg', 'i915' ); -my %bal_skip_H = ( 'rr' => 1, 'rand' => 1, 'context' => 1, , 'busy' => 1, - 'busy-avg' => 1, 'i915' => 1 ); -my %bal_skip_R = ( 'i915' => 1 ); -my %bal_skip_G = ( 'i915' => 1 ); - -my @workloads = ( - 'media_load_balance_17i7.wsim', - 'media_load_balance_19.wsim', - 'media_load_balance_4k12u7.wsim', - 'media_load_balance_fhd26u7.wsim', - 'media_load_balance_hd01.wsim', - 'media_load_balance_hd06mp2.wsim', - 'media_load_balance_hd12.wsim', - 'media_load_balance_hd17i4.wsim', - 'media_1n2_480p.wsim', - 'media_1n3_480p.wsim', - 'media_1n4_480p.wsim', - 'media_1n5_480p.wsim', - 'media_1n2_asy.wsim', - 'media_1n3_asy.wsim', - 'media_1n4_asy.wsim', - 'media_1n5_asy.wsim', - 'media_mfe2_480p.wsim', - 'media_mfe3_480p.wsim', - 'media_mfe4_480p.wsim', - 'media_nn_1080p.wsim', - 'media_nn_480p.wsim', - ); - -sub show_cmd -{ - my ($cmd) = @_; - - say "\n+++ $cmd" if $show_cmds; -} - -sub calibrate_nop -{ - my ($delay, $nop); - my $cmd = "$wsim"; - - show_cmd($cmd); - open WSIM, "$cmd |" or die; - while (<WSIM>) { - chomp; - if (/Nop calibration for (\d+)us delay is (\d+)./) { - $delay = $1; - $nop = $2; - } - - } - close WSIM; - - die unless $nop; - - return $nop -} - -sub can_balance_workload -{ - my ($wrk) = @_; - my $res = 0; - - open WRK, "$wrk_root/$wrk" or die; - while (<WRK>) { - chomp; - if (/\.VCS\./) { - $res = 1; - last; - } - } - close WRK; - - return $res; -} - -sub add_wps_arg -{ - my (@args) = @_; - my $period; - - return @args if $realtime_target <= 0; - - $period = int(1000000 / $realtime_target); - push @args, '-a'; - push @args, 'p.$period'; - - return @args; -} - -sub run_workload -{ - my (@args) = @_; - my ($time, $wps, $cmd); - my @ret; - - @args = add_wps_arg(@args); - push @args, '-2' if $gt2; - - unshift @args, $wsim; - $cmd = join ' ', @args; - show_cmd($cmd); - - open WSIM, "$cmd |" or die; - while (<WSIM>) { - chomp; - if (/^(\d+\.\d+)s elapsed \((\d+\.?\d+) workloads\/s\)$/) { - $time = $1; - $wps = $2; - } elsif (/(\d+)\: \d+\.\d+s elapsed \(\d+ cycles, (\d+\.?\d+) workloads\/s\)/) { - $ret[$1] = $2; - } - } - close WSIM; - - return ($time, $wps, \@ret); -} - -sub dump_cmd -{ - my ($cmd, $file) = @_; - - show_cmd("$cmd > $file"); - - open FOUT, '>', $file or die; - open TIN, "$cmd |" or die; - while (<TIN>) { - print FOUT $_; - } - close TIN; - close FOUT; -} - -sub trace_workload -{ - my ($wrk, $b, $r, $c) = @_; - my @args = ($tracepl, '--trace', $wsim, '-q', '-n', $nop, '-r', $r, '-c', $c); - my $min_batches = 16 + $r * $c / 2; - my @skip_engine; - my %engines; - my ($cmd, $file); - - push @args, '-2' if $gt2; - - unless ($b eq '<none>') { - push @args, '-R'; - push @args, split /\s+/, $b; - } - - if (defined $w_direct) { - push @args, split /\s+/, $wrk; - } else { - push @args, '-w'; - push @args, $wrk_root . '/' . $wrk; - } - - show_cmd(join ' ', @args); - if (-e 'perf.data') { - unlink 'perf.data' or die; - } - system(@args) == 0 or die; - - $cmd = "perf script | $tracepl"; - show_cmd($cmd); - open CMD, "$cmd |" or die; - while (<CMD>) { - chomp; - if (/Ring(\S+): (\d+) batches.*?(\d+\.?\d+)% idle,/) { - if ($2 >= $min_batches) { - $engines{$1} = $3; - } else { - push @skip_engine, $1; - } - } elsif (/GPU: (\d+\.?\d+)% idle/) { - $engines{'gpu'} = $1; - } - } - close CMD; - - $wrk =~ s/$wrk_root//g; - $wrk =~ s/\.wsim//g; - $wrk =~ s/-w/W/g; - $wrk =~ s/[ -]/_/g; - $wrk =~ s/\//-/g; - $b =~ s/[ <>]/_/g; - $file = "${wrk}_${b}_-r${r}_-c${c}"; - - dump_cmd('perf script', "${file}.trace"); - - $cmd = "perf script | $tracepl --html -x ctxsave -s -c "; - $cmd .= join ' ', map("-i $_", @skip_engine); - - dump_cmd($cmd, "${file}.html"); - - return \%engines; -} - -sub calibrate_workload -{ - my ($wrk) = @_; - my $tol = $tolerance; - my $loops = 0; - my $error; - my $r; - - $r = $realtime_target > 0 ? $realtime_target * $client_target_s : 23; - for (;;) { - my @args = ('-n', $nop, '-r', $r); - my ($time, $wps); - - if (defined $w_direct) { - push @args, split /\s+/, $wrk; - } else { - push @args, '-w'; - push @args, $wrk_root . '/' . $wrk; - } - - ($time, $wps) = run_workload(@args); - - $wps = $r / $time if $w_direct; - $error = abs($time - $client_target_s) / $client_target_s; - - last if $error <= $tol; - - $r = int($wps * $client_target_s); - $loops = $loops + 1; - if ($loops >= 3) { - $tol = $tol * (1.2 + ($tol)); - $loops = 0; - } - last if $tol > 0.2; - } - - return ($r, $error); -} - -sub find_saturation_point -{ - my ($wrk, $rr, $verbose, @args) = @_; - my ($last_wps, $c, $swps, $wwps); - my $target = $realtime_target > 0 ? $realtime_target : $wps_target; - my $r = $rr; - my $wcnt; - my $maxc; - my $max = 0; - - push @args, '-v' if $multi_mode and $w_direct; - - if (defined $w_direct) { - push @args, split /\s+/, $wrk; - $wcnt = () = $wrk =~ /-[wW]/gi; - - } else { - push @args, '-w'; - push @args, $wrk_root . '/' . $wrk; - $wcnt = 1; - } - - for ($c = 1; ; $c = $c + 1) { - my ($time, $wps); - my @args_ = (@args, ('-r', $r, '-c', $c)); - - ($time, $wps, $wwps) = run_workload(@args_); - - say " $c clients is $wps wps." if $verbose; - - if ($c > 1) { - my $delta; - - if ($target <= 0) { - if ($wps > $max) { - $max = $wps; - $maxc = $c; - } - $delta = ($wps - $last_wps) / $last_wps; - if ($delta > 0) { - last if $delta < $tolerance; - } else { - $delta = ($wps - $max) / $max; - last if abs($delta) >= $tolerance; - } - } else { - $delta = ($wps / $c - $target) / $target; - last if $delta < 0 and abs($delta) >= $tolerance; - } - $r = int($rr * ($client_target_s / $time)); - } elsif ($c == 1) { - $swps = $wps; - return ($c, $wps, $swps, $wwps) if $wcnt > 1 or - $multi_mode or - ($wps_target_param < 0 and - $wps_target == 0); - } - - $last_wps = $wps; - } - - if ($target <= 0) { - return ($maxc, $max, $swps, $wwps); - } else { - return ($c - 1, $last_wps, $swps, $wwps); - } -} - -getopts('hv2xmn:b:W:B:r:t:i:R:T:w:', \%opts); - -if (defined $opts{'h'}) { - print <<ENDHELP; -Supported options: - - -h Help text. - -v Be verbose. - -x Show external commands. - -2 Run gem_wsim in GT2 mode. - -n num Nop calibration. - -b str Balancer to pre-select. - Skips balancer auto-selection. - Passed straight the gem_wsim so use like -b "-b qd -R" - -W a,b,c Override the default list of workloads. - -B a,b,c Override the default list of balancers. - -r sec Target workload duration. - -t pct Calibration tolerance. - -i pct Engine idleness tolerance. - -R wps Run workloads in the real-time mode at wps rate. - -T wps Calibrate up to wps/client target instead of GPU saturation. - Negative values set the target based on the single client - performance where target = single-client-wps / -N. - -w str Pass-through to gem_wsim. Overrides normal workload selection. - -m Multi-workload mode. All selected workloads will be run in - parallel and overal score will be relative to when run - individually. -ENDHELP - exit 0; -} - -$verbose = 1 if defined $opts{'v'}; -$gt2 = 1 if defined $opts{'2'}; -$show_cmds = 1 if defined $opts{'x'}; -$multi_mode = 1 if defined $opts{'m'}; -if (defined $opts{'b'}) { - die unless substr($opts{'b'}, 0, 2) eq '-b'; - $balancer = $opts{'b'}; -} -if (defined $opts{'B'}) { - @balancers = split /,/, $opts{'B'}; -} else { - unshift @balancers, ''; -} - at workloads = split /,/, $opts{'W'} if defined $opts{'W'}; -$client_target_s = $opts{'r'} if defined $opts{'r'}; -$tolerance = $opts{'t'} / 100.0 if defined $opts{'t'}; -$idle_tolerance_pct = $opts{'i'} if defined $opts{'i'}; -$realtime_target = $opts{'R'} if defined $opts{'R'}; -$wps_target = $opts{'T'} if defined $opts{'T'}; -$wps_target_param = $wps_target; -$w_direct = $opts{'w'} if defined $opts{'w'}; - -if ($multi_mode) { - die if $w_direct; # Not supported - @multi_workloads = @workloads; -} - - at workloads = ($w_direct) if defined $w_direct; - -say "Workloads:"; -print map { " $_\n" } @workloads; -print "Balancers: "; -say map { "$_," } @balancers; -say "Target workload duration is ${client_target_s}s."; -say "Calibration tolerance is $tolerance."; -say "Real-time mode at ${realtime_target} wps." if $realtime_target > 0; -say "Wps target is ${wps_target} wps." if $wps_target > 0; -say "Multi-workload mode." if $multi_mode; -$nop = $opts{'n'}; -$nop = calibrate_nop() unless $nop; -say "Nop calibration is $nop."; - -goto VERIFY if defined $balancer; - -my (%best_bal, %best_bid); -my %results; -my %scores; -my %wscores; -my %cscores; -my %cwscores; -my %mscores; -my %mwscores; - -sub add_points -{ - my ($wps, $scores, $wscores) = @_; - my ($min, $max, $spread); - my @sorted; - - @sorted = sort { $b <=> $a } values %{$wps}; - $max = $sorted[0]; - $min = $sorted[-1]; - $spread = $max - $min; - die if $spread < 0; - - foreach my $w (keys %{$wps}) { - my ($score, $wscore); - - unless (exists $scores->{$w}) { - $scores->{$w} = 0; - $wscores->{$w} = 0; - } - - $score = $wps->{$w} / $max; - $scores->{$w} = $scores->{$w} + $score; - $wscore = $score * $spread / $max; - $wscores->{$w} = $wscores->{$w} + $wscore; - } -} - -my @saturation_workloads = $multi_mode ? @multi_workloads : @workloads; -my %allwps; -my $widx = 0; - -push @saturation_workloads, '-w ' . join ' -w ', map("$wrk_root/$_", @workloads) - if $multi_mode; - -foreach my $wrk (@saturation_workloads) { - my @args = ( "-n $nop"); - my ($r, $error, $should_b, $best); - my (%wps, %cwps, %mwps); - my @sorted; - my $range; - - $w_direct = $wrk if $multi_mode and $widx == $#saturation_workloads; - - $should_b = 1; - $should_b = can_balance_workload($wrk) unless defined $w_direct; - - print "\nEvaluating '$wrk'..."; - - ($r, $error) = calibrate_workload($wrk); - say " ${client_target_s}s is $r workloads. (error=$error)"; - - say " Finding saturation points for '$wrk'..."; - - BAL: foreach my $bal (@balancers) { - GBAL: foreach my $G ('', '-G', '-d', '-G -d') { - foreach my $H ('', '-H') { - my @xargs; - my ($w, $c, $s, $bwwps); - my $bid; - - if ($bal ne '') { - next GBAL if $G =~ '-G' and exists $bal_skip_G{$bal}; - - push @xargs, "-b $bal"; - push @xargs, '-R' unless exists $bal_skip_R{$bal}; - push @xargs, $G if $G ne ''; - push @xargs, $H if $H ne ''; - $bid = join ' ', @xargs; - print " $bal balancer ('$bid'): "; - } else { - $bid = '<none>'; - print " No balancing: "; - } - - $wps_target = 0 if $wps_target_param < 0; - - ($c, $w, $s, $bwwps) = - find_saturation_point($wrk, $r, 0, - (@args, @xargs)); - - if ($wps_target_param < 0) { - $wps_target = $s / -$wps_target_param; - - ($c, $w, $s, $bwwps) = - find_saturation_point($wrk, $r, - 0, - (@args, - @xargs)); - } - - if ($multi_mode and $w_direct) { - my $widx; - - die unless scalar(@multi_workloads) == - scalar(@{$bwwps}); - die unless scalar(@multi_workloads) == - scalar(keys %allwps); - - # Total of all workload wps from the - # mixed run. - $w = 0; - foreach $widx (0..$#{$bwwps}) { - $w += $bwwps->[$widx]; - } - - # Total of all workload wps from when - # ran individually with the best - # balancer. - my $tot = 0; - foreach my $wrk (@multi_workloads) { - $tot += $allwps{$wrk}->{$best_bid{$wrk}}; - } - - # Normalize mixed sum with sum of - # individual runs. - $w *= 100; - $w /= $tot; - - # Second metric is average of each - # workload wps normalized by their - # individual run performance with the - # best balancer. - $s = 0; - $widx = 0; - foreach my $wrk (@multi_workloads) { - $s += 100 * $bwwps->[$widx] / - $allwps{$wrk}->{$best_bid{$wrk}}; - $widx++; - } - $s /= scalar(@multi_workloads); - - say sprintf('Aggregate (normalized) %.2f%%; fairness %.2f%%', - $w, $s); - } else { - $allwps{$wrk} = \%wps; - } - - $wps{$bid} = $w; - $cwps{$bid} = $s; - - if ($realtime_target > 0 || $wps_target_param > 0) { - $mwps{$bid} = $w * $c; - } else { - $mwps{$bid} = $w + $s; - } - - say "$c clients ($w wps, $s wps single client, score=$mwps{$bid})." - unless $multi_mode and $w_direct; - - last BAL unless $should_b; - next BAL if $bal eq ''; - next GBAL if exists $bal_skip_H{$bal}; - } - } - } - - $widx++; - - @sorted = sort { $mwps{$b} <=> $mwps{$a} } keys %mwps; - $best_bid{$wrk} = $sorted[0]; - @sorted = sort { $b <=> $a } values %mwps; - $range = 1 - $sorted[-1] / $sorted[0]; - $best_bal{$wrk} = $sorted[0]; - - next if $multi_mode and not $w_direct; - - say " Best balancer is '$best_bid{$wrk}' (range=$range)."; - - - $results{$wrk} = \%mwps; - - add_points(\%wps, \%scores, \%wscores); - add_points(\%mwps, \%mscores, \%mwscores); - add_points(\%cwps, \%cscores, \%cwscores); -} - -sub dump_scoreboard -{ - my ($n, $h) = @_; - my ($i, $str, $balancer); - my ($max, $range); - my @sorted; - - @sorted = sort { $b <=> $a } values %{$h}; - $max = $sorted[0]; - $range = 1 - $sorted[-1] / $max; - $str = "$n rank (range=$range):"; - say "\n$str"; - say '=' x length($str); - $i = 1; - foreach my $w (sort { $h->{$b} <=> $h->{$a} } keys %{$h}) { - my $score; - - $balancer = $w if $i == 1; - $score = $h->{$w} / $max; - - say " $i: '$w' ($score)"; - - $i = $i + 1; - } - - return $balancer; -} - -dump_scoreboard($multi_mode ? 'Throughput' : 'Total wps', \%scores); -dump_scoreboard('Total weighted wps', \%wscores) unless $multi_mode; -dump_scoreboard($multi_mode ? 'Fairness' : 'Per client wps', \%cscores); -dump_scoreboard('Per client weighted wps', \%cwscores) unless $multi_mode; -$balancer = dump_scoreboard($multi_mode ? 'Combined' : 'Combined wps', \%mscores); -$balancer = dump_scoreboard('Combined weighted wps', \%mwscores) unless $multi_mode; - -VERIFY: - -my %problem_wrk; - -die unless defined $balancer; - -say "\nBalancer is '$balancer'."; -say "Idleness tolerance is $idle_tolerance_pct%."; - -if ($multi_mode) { - $w_direct = '-w ' . join ' -w ', map("$wrk_root/$_", @workloads); - @workloads = ($w_direct); -} - -foreach my $wrk (@workloads) { - my @args = ( "-n $nop" ); - my ($r, $error, $c, $wps, $swps); - my $saturated = 0; - my $result = 'Pass'; - my $vcs2 = $gt2 ? '1:0' : '2:1'; - my %problem; - my $engines; - - next if not defined $w_direct and not can_balance_workload($wrk); - - push @args, $balancer unless $balancer eq '<none>'; - - if (scalar(keys %results)) { - $r = $results{$wrk}->{$balancer} / $best_bal{$wrk} * 100.0; - } else { - $r = '---'; - } - say " \nProfiling '$wrk' ($r% of best)..."; - - ($r, $error) = calibrate_workload($wrk); - say " ${client_target_s}s is $r workloads. (error=$error)"; - - ($c, $wps, $swps) = find_saturation_point($wrk, $r, $verbose, @args); - say " Saturation at $c clients ($wps workloads/s)."; - push @args, "-c $c"; - - $engines = trace_workload($wrk, $balancer, $r, $c); - - foreach my $key (keys %{$engines}) { - next if $key eq 'gpu'; - $saturated = $saturated + 1 - if $engines->{$key} < $idle_tolerance_pct; - } - - if ($saturated == 0) { - # Not a single saturated engine - $result = 'FAIL'; - } elsif (not exists $engines->{'2:0'} or not exists $engines->{$vcs2}) { - # VCS1 and VCS2 not present in a balancing workload - $result = 'FAIL'; - } elsif ($saturated == 1 and - ($engines->{'2:0'} < $idle_tolerance_pct or - $engines->{$vcs2} < $idle_tolerance_pct)) { - # Only one VCS saturated - $result = 'WARN'; - } - - $result = 'WARN' if $engines->{'gpu'} > $idle_tolerance_pct; - - if ($result ne 'Pass') { - $problem{'c'} = $c; - $problem{'r'} = $r; - $problem{'stats'} = $engines; - $problem_wrk{$wrk} = \%problem; - } - - print " $result ["; - print map " $_: $engines->{$_}%,", sort keys %{$engines}; - say " ]"; -} - -say "\nProblematic workloads were:" if scalar(keys %problem_wrk) > 0; -foreach my $wrk (sort keys %problem_wrk) { - my $problem = $problem_wrk{$wrk}; - - print " $wrk -c $problem->{'c'} -r $problem->{'r'} ["; - print map " $_: $problem->{'stats'}->{$_}%,", - sort keys %{$problem->{'stats'}}; - say " ]"; -} -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:12 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:12 +0100 Subject: [Intel-gfx] [PATCH i-g-t 02/10] gem_wsim: Buffer objects working sets and complex dependencies In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-3-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Add support for defining buffer object working sets and targetting them as data dependencies. For more information please see the README file. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 453 +++++++++++++++++++++--- benchmarks/wsim/README | 59 +++ benchmarks/wsim/cloud-gaming-60fps.wsim | 11 + benchmarks/wsim/composited-ui.wsim | 7 + 4 files changed, 476 insertions(+), 54 deletions(-) create mode 100644 benchmarks/wsim/cloud-gaming-60fps.wsim create mode 100644 benchmarks/wsim/composited-ui.wsim diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 02fe8f5a5e69..9e5bfe6a36d4 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -88,14 +88,21 @@ enum w_type LOAD_BALANCE, BOND, TERMINATE, - SSEU + SSEU, + WORKINGSET, +}; + +struct dep_entry { + int target; + bool write; + int working_set; /* -1 = step dependecy, >= 0 working set id */ }; struct deps { int nr; bool submit_fence; - int *list; + struct dep_entry *list; }; struct w_arg { @@ -110,6 +117,14 @@ struct bond { enum intel_engine_id master; }; +struct working_set { + int id; + bool shared; + unsigned int nr; + uint32_t *handles; + unsigned long *sizes; +}; + struct workload; struct w_step @@ -143,6 +158,7 @@ struct w_step enum intel_engine_id bond_master; }; int sseu; + struct working_set working_set; }; /* Implementation details */ @@ -193,6 +209,9 @@ struct workload unsigned int nr_ctxs; struct ctx *ctx_list; + struct working_set **working_sets; /* array indexed by set id */ + int max_working_set_id; + int sync_timeline; uint32_t sync_seqno; @@ -281,11 +300,120 @@ print_engine_calibrations(void) printf("\n"); } +static void add_dep(struct deps *deps, struct dep_entry entry) +{ + deps->list = realloc(deps->list, sizeof(*deps->list) * (deps->nr + 1)); + igt_assert(deps->list); + + deps->list[deps->nr++] = entry; +} + +static int +parse_working_set_deps(struct workload *wrk, + struct deps *deps, + struct dep_entry _entry, + char *str) +{ + /* + * 1 - target handle index in the specified working set. + * 2-4 - range + */ + struct dep_entry entry = _entry; + char *s; + + s = index(str, '-'); + if (s) { + int from, to; + + from = atoi(str); + if (from < 0) + return -1; + + to = atoi(++s); + if (to <= 0) + return -1; + + for (entry.target = from; entry.target <= to; entry.target++) + add_dep(deps, entry); + } else { + entry.target = atoi(str); + if (entry.target < 0) + return -1; + + add_dep(deps, entry); + } + + return 0; +} + +static int +parse_dependency(unsigned int nr_steps, struct w_step *w, char *str) +{ + struct dep_entry entry = { .working_set = -1 }; + bool submit_fence = false; + char *s; + + switch (str[0]) { + case '-': + if (str[1] < '0' || str[1] > '9') + return -1; + + entry.target = atoi(str); + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) + return -1; + + add_dep(&w->data_deps, entry); + + break; + case 's': + submit_fence = true; + /* Fall-through. */ + case 'f': + /* Multiple fences not yet supported. */ + igt_assert_eq(w->fence_deps.nr, 0); + + entry.target = atoi(++str); + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) + return -1; + + add_dep(&w->fence_deps, entry); + + w->fence_deps.submit_fence = submit_fence; + break; + case 'w': + entry.write = true; + /* Fall-through. */ + case 'r': + /* + * [rw]N-<str> + * r1-<str> or w2-<str>, where N is working set id. + */ + s = index(++str, '-'); + if (!s) + return -1; + + entry.working_set = atoi(str); + + if (parse_working_set_deps(w->wrk, &w->data_deps, entry, ++s)) + return -1; + + break; + default: + return -1; + }; + + return 0; +} + static int parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) { char *desc = strdup(_desc); char *token, *tctx = NULL, *tstart = desc; + int ret = 0; + + if (!strcmp(_desc, "0")) + goto out; igt_assert(desc); igt_assert(!w->data_deps.nr && w->data_deps.nr == w->fence_deps.nr); @@ -293,47 +421,17 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) w->data_deps.list == w->fence_deps.list); while ((token = strtok_r(tstart, "/", &tctx)) != NULL) { - bool submit_fence = false; - char *str = token; - struct deps *deps; - int dep; - tstart = NULL; - if (str[0] == '-' || (str[0] >= '0' && str[0] <= '9')) { - deps = &w->data_deps; - } else { - if (str[0] == 's') - submit_fence = true; - else if (str[0] != 'f') - return -1; - - deps = &w->fence_deps; - str++; - } - - dep = atoi(str); - if (dep > 0 || ((int)nr_steps + dep) < 0) { - if (deps->list) - free(deps->list); - return -1; - } - - if (dep < 0) { - deps->nr++; - /* Multiple fences not yet supported. */ - igt_assert(deps->nr == 1 || deps != &w->fence_deps); - deps->list = realloc(deps->list, - sizeof(*deps->list) * deps->nr); - igt_assert(deps->list); - deps->list[deps->nr - 1] = dep; - deps->submit_fence = submit_fence; - } + ret = parse_dependency(nr_steps, w, token); + if (ret) + break; } +out: free(desc); - return 0; + return ret; } static void __attribute__((format(printf, 1, 2))) @@ -624,6 +722,88 @@ static int parse_engine_map(struct w_step *step, const char *_str) return 0; } +static unsigned long parse_size(char *str) +{ + const unsigned int len = strlen(str); + unsigned int mult = 1; + + if (len == 0) + return 0; + + switch (str[len - 1]) { + case 'g': + case 'G': + mult *= 1024; + /* Fall-throuogh. */ + case 'm': + case 'M': + mult *= 1024; + /* Fall-throuogh. */ + case 'k': + case 'K': + mult *= 1024; + + str[len - 1] = 0; + } + + return atol(str) * mult; +} + +static int add_buffers(struct working_set *set, char *str) +{ + /* + * 4096 + * 4k + * 4m + * 4g + * 10n4k - 10 4k batches + */ + unsigned long *sizes, size; + unsigned int add, i; + char *n; + + n = index(str, 'n'); + if (n) { + *n = 0; + add = atoi(str); + if (!add) + return -1; + str = ++n; + } else { + add = 1; + } + + size = parse_size(str); + if (!size) + return -1; + + sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); + if (!sizes) + return -1; + + for (i = 0; i < add; i++) + sizes[set->nr + i] = size; + + set->nr += add; + set->sizes = sizes; + + return 0; +} + +static int parse_working_set(struct working_set *set, char *str) +{ + char *token, *tctx = NULL, *tstart = str; + + while ((token = strtok_r(tstart, "/", &tctx))) { + tstart = NULL; + + if (add_buffers(set, token)) + return -1; + } + + return 0; +} + static uint64_t engine_list_mask(const char *_str) { uint64_t mask = 0; @@ -644,6 +824,8 @@ static uint64_t engine_list_mask(const char *_str) return mask; } +static void allocate_working_set(struct working_set *set); + #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ if ((field = strtok_r(fstart, ".", &fctx))) { \ tmp = atoi(field); \ @@ -661,7 +843,7 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) char *desc = strdup(arg->desc); char *_token, *token, *tctx = NULL, *tstart = desc; char *field, *fctx = NULL, *fstart; - struct w_step step, *steps = NULL; + struct w_step step, *w, *steps = NULL; unsigned int valid; int i, j, tmp; @@ -851,6 +1033,28 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) step.type = BOND; goto add_step; + } else if (!strcmp(field, "w") || !strcmp(field, "W")) { + unsigned int nr = 0; + + step.working_set.shared = field[0] == 'W'; + + while ((field = strtok_r(fstart, ".", &fctx))) { + tmp = atoi(field); + if (nr == 0) { + step.working_set.id = tmp; + } else { + tmp = parse_working_set(&step.working_set, + field); + check_arg(tmp < 0, + "Invalid working set at step %u!\n", + nr_steps); + } + + nr++; + } + + step.type = WORKINGSET; + goto add_step; } if (!field) { @@ -975,6 +1179,8 @@ add_step: wrk->steps = steps; wrk->prio = arg->prio; wrk->sseu = arg->sseu; + wrk->max_working_set_id = -1; + wrk->working_sets = NULL; free(desc); @@ -984,7 +1190,7 @@ add_step: */ for (i = 0; i < nr_steps; i++) { for (j = 0; j < steps[i].fence_deps.nr; j++) { - tmp = steps[i].idx + steps[i].fence_deps.list[j]; + tmp = steps[i].idx + steps[i].fence_deps.list[j].target; check_arg(tmp < 0 || tmp >= i || (steps[tmp].type != BATCH && steps[tmp].type != SW_FENCE), @@ -1003,6 +1209,51 @@ add_step: } } + /* + * Check no duplicate working set ids. + */ + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + struct w_step *w2; + + if (w->type != WORKINGSET) + continue; + + for (j = 0, w2 = wrk->steps; j < wrk->nr_steps; w2++, j++) { + if (j == i) + continue; + if (w2->type != WORKINGSET) + continue; + + check_arg(w->working_set.id == w2->working_set.id, + "Duplicate working set id at %u!\n", j); + } + } + + /* + * Allocate shared working sets. + */ + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && w->working_set.shared) + allocate_working_set(&w->working_set); + } + + wrk->max_working_set_id = -1; + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && + w->working_set.shared && + w->working_set.id > wrk->max_working_set_id) + wrk->max_working_set_id = w->working_set.id; + } + + wrk->working_sets = calloc(wrk->max_working_set_id + 1, + sizeof(*wrk->working_sets)); + igt_assert(wrk->working_sets); + + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && w->working_set.shared) + wrk->working_sets[w->working_set.id] = &w->working_set; + } + return wrk; } @@ -1024,6 +1275,18 @@ clone_workload(struct workload *_wrk) memcpy(wrk->steps, _wrk->steps, sizeof(struct w_step) * wrk->nr_steps); + wrk->max_working_set_id = _wrk->max_working_set_id; + if (wrk->max_working_set_id >= 0) { + wrk->working_sets = calloc(wrk->max_working_set_id + 1, + sizeof(*wrk->working_sets)); + igt_assert(wrk->working_sets); + + memcpy(wrk->working_sets, + _wrk->working_sets, + (wrk->max_working_set_id + 1) * + sizeof(*wrk->working_sets)); + } + /* Check if we need a sw sync timeline. */ for (i = 0; i < wrk->nr_steps; i++) { if (wrk->steps[i].type == SW_FENCE) { @@ -1226,17 +1489,36 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) igt_assert(j < nr_obj); for (i = 0; i < w->data_deps.nr; i++) { - igt_assert(w->data_deps.list[i] <= 0); - if (w->data_deps.list[i]) { - int dep_idx = w->idx + w->data_deps.list[i]; + struct dep_entry *entry = &w->data_deps.list[i]; + uint32_t dep_handle; + + if (entry->working_set == -1) { + int dep_idx = w->idx + entry->target; + igt_assert(entry->target <= 0); igt_assert(dep_idx >= 0 && dep_idx < w->idx); igt_assert(wrk->steps[dep_idx].type == BATCH); - w->obj[j].handle = wrk->steps[dep_idx].obj[0].handle; - j++; - igt_assert(j < nr_obj); + dep_handle = wrk->steps[dep_idx].obj[0].handle; + } else { + struct working_set *set; + + igt_assert(entry->working_set <= + wrk->max_working_set_id); + + set = wrk->working_sets[entry->working_set]; + + igt_assert(set->nr); + igt_assert(entry->target < set->nr); + igt_assert(set->sizes[entry->target]); + + dep_handle = set->handles[entry->target]; } + + w->obj[j].flags = entry->write ? EXEC_OBJECT_WRITE : 0; + w->obj[j].handle = dep_handle; + j++; + igt_assert(j < nr_obj); } if (w->unbound_duration) @@ -1395,11 +1677,23 @@ static size_t sizeof_engines_bond(int count) engines[count]); } +static void allocate_working_set(struct working_set *set) +{ + unsigned int i; + + set->handles = calloc(set->nr, sizeof(*set->handles)); + igt_assert(set->handles); + + for (i = 0; i < set->nr; i++) + set->handles[i] = gem_create(fd, set->sizes[i]); +} + #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) static int prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) { + struct working_set **sets; uint32_t share_vm = 0; int max_ctx = -1; struct w_step *w; @@ -1634,6 +1928,51 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) } } + /* + * Allocate working sets. + */ + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && !w->working_set.shared) + allocate_working_set(&w->working_set); + } + + /* + * Map of working set ids. + */ + wrk->max_working_set_id = -1; + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && + w->working_set.id > wrk->max_working_set_id) + wrk->max_working_set_id = w->working_set.id; + } + + sets = wrk->working_sets; + wrk->working_sets = calloc(wrk->max_working_set_id + 1, + sizeof(*wrk->working_sets)); + igt_assert(wrk->working_sets); + + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + struct working_set *set; + + if (w->type != WORKINGSET) + continue; + + if (!w->working_set.shared) { + set = &w->working_set; + } else { + igt_assert(sets); + + set = sets[w->working_set.id]; + igt_assert(set->shared); + igt_assert(set->sizes); + } + + wrk->working_sets[w->working_set.id] = set; + } + + if (sets) + free(sets); + /* * Allocate batch buffers. */ @@ -1704,7 +2043,7 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, 2 * sizeof(uint32_t)); for (i = 0; i < w->fence_deps.nr; i++) { - int tgt = w->idx + w->fence_deps.list[i]; + int tgt = w->idx + w->fence_deps.list[i].target; /* TODO: fence merging needed to support multiple inputs */ igt_assert(i == 0); @@ -1735,14 +2074,18 @@ static void sync_deps(struct workload *wrk, struct w_step *w) unsigned int i; for (i = 0; i < w->data_deps.nr; i++) { + struct dep_entry *entry = &w->data_deps.list[i]; int dep_idx; - igt_assert(w->data_deps.list[i] <= 0); + if (entry->working_set == -1) + continue; + + igt_assert(entry->target <= 0); - if (!w->data_deps.list[i]) + if (!entry->target) continue; - dep_idx = w->idx + w->data_deps.list[i]; + dep_idx = w->idx + entry->target; igt_assert(dep_idx >= 0 && dep_idx < w->idx); igt_assert(wrk->steps[dep_idx].type == BATCH); @@ -1842,11 +2185,6 @@ static void *run_workload(void *data) MI_BATCH_BUFFER_END; __sync_synchronize(); continue; - } else if (w->type == PREEMPTION || - w->type == ENGINE_MAP || - w->type == LOAD_BALANCE || - w->type == BOND) { - continue; } else if (w->type == SSEU) { if (w->sseu != wrk->ctx_list[w->context * 2].sseu) { wrk->ctx_list[w->context * 2].sseu = @@ -1854,6 +2192,13 @@ static void *run_workload(void *data) w->sseu); } continue; + } else if (w->type == PREEMPTION || + w->type == ENGINE_MAP || + w->type == LOAD_BALANCE || + w->type == BOND || + w->type == WORKINGSET) { + /* No action for these at execution time. */ + continue; } if (do_sleep || w->type == PERIOD) { diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 9f770217f075..3d9143226740 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -8,6 +8,7 @@ M.<uint>.<str>[|<str>]... P|S|X.<uint>.<int> d|p|s|t|q|a|T.<int>,... b.<uint>.<str>[|<str>].<str> +w|W.<uint>.<str>[/<str>]... f For duration a range can be given from which a random value will be picked @@ -32,6 +33,8 @@ Additional workload steps are also supported: 'P' - Context priority. 'S' - Context SSEU configuration. 'T' - Terminate an infinite batch. + 'w' - Working set. (See Working sets section.) + 'W' - Shared working set. 'X' - Context preemption control. Engine ids: DEFAULT, RCS, BCS, VCS, VCS1, VCS2, VECS @@ -275,3 +278,59 @@ for the render engine. Slice mask of -1 has a special meaning of "all slices". Otherwise any integer can be specifying as the slice mask, but beware any apart from 1 and -1 can make the workload not portable between different GPUs. + +Working sets +------------ + +When used plainly workload steps can create implicit data dependencies by +relatively referencing another workload steps of a batch buffer type. Fourth +field contains the relative data dependncy. For example: + + 1.RCS.1000.0.0 + 1.BCS.1000.-1.0 + +This means the second batch buffer will be marked as having a read data +dependency on the first one. (The shared buffer is always marked as written to +by the dependency target buffer.) This will cause a serialization between the +two batch buffers. + +Working sets are used where more complex data dependencies are required. Each +working set has an id, a list of buffers, and can either be local to the +workload or shared within the cloned workloads (-c command line option). + +Lower-case 'w' command defines a local working set while upper-case 'W' defines +a shared version. Syntax is as follows: + + w.<id>.<size>[/<size>]... + +For size a byte size can be given, or suffix 'k', 'm' or 'g' can be used (case +insensitive). Prefix in the format of "<int>n<size>" can also be given to create +multiple objects of the same size. + +Examples: + + w.1.4k - Working set 1 with a single 4KiB object in it. + W.2.2M/32768 - Working set 2 with one 2MiB and one 32768 byte object. + w.3.10n4k/2n20000 - Working set 3 with ten 4KiB and two 20000 byte objects. + +Working set objects can be referenced as data dependency targets using the new +'r'/'w' syntax. Simple example: + + w.1.4k + W.2.1m + 1.RCS.1000.r1-0/w2-0.0 + 1.BCS.1000.r2-0.0 + +In this example the RCS batch is reading from working set 1 object 0 and writing +to working set 2 object 0. BCS batch is reading from working set 2 object 0. + +Because working set 2 is of a shared type, should two instances of the same +workload be executed (-c 2) then the 1MiB buffer would be shared and written +and read by both clients creating a serialization point. + +Apart from single objects, ranges can also be given as depenencies: + + w.1.10n4k + 1.RCS.1000.r1-0-9.0 + +Here the RCS batch has a read dependency on working set 1 objects 0 to 9. diff --git a/benchmarks/wsim/cloud-gaming-60fps.wsim b/benchmarks/wsim/cloud-gaming-60fps.wsim new file mode 100644 index 000000000000..9e48bbc2f617 --- /dev/null +++ b/benchmarks/wsim/cloud-gaming-60fps.wsim @@ -0,0 +1,11 @@ +w.1.10n8m +w.2.3n16m +1.RCS.500-1500.r1-0-4/w2-0.0 +1.RCS.500-1500.r1-5-9/w2-1.0 +1.RCS.500-1500.r2-0-1/w2-2.0 +M.2.VCS +B.2 +3.RCS.500-1500.r2-2.0 +2.DEFAULT.2000-4000.-1.0 +4.VCS1.250-750.-1.1 +p.16667 diff --git a/benchmarks/wsim/composited-ui.wsim b/benchmarks/wsim/composited-ui.wsim new file mode 100644 index 000000000000..4164f8bf7393 --- /dev/null +++ b/benchmarks/wsim/composited-ui.wsim @@ -0,0 +1,7 @@ +w.1.10n8m/3n16m +W.2.16m +1.RCS.200-600.r1-0-4/w1-10.0 +1.RCS.200-600.r1-5-9/w1-11.0 +1.RCS.400-800.r1-10-11/w1-12.0 +3.BCS.200-800.r1-12/w2-0.1 +p.16667 -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:13 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:13 +0100 Subject: [Intel-gfx] [PATCH i-g-t 03/10] gem_wsim: Show workload timing stats In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-4-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Show average/min/max workload iteration and dropped period stats when 'p' command is used. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 9e5bfe6a36d4..60982cb73ba7 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -2101,7 +2101,8 @@ static void *run_workload(void *data) struct w_step *w; int throttle = -1; int qd_throttle = -1; - int count; + int count, missed = 0; + unsigned long time_tot = 0, time_min = ULONG_MAX, time_max = 0; int i; clock_gettime(CLOCK_MONOTONIC, &t_start); @@ -2121,12 +2122,19 @@ static void *run_workload(void *data) do_sleep = w->delay; } else if (w->type == PERIOD) { struct timespec now; + int elapsed; clock_gettime(CLOCK_MONOTONIC, &now); - do_sleep = w->period - - elapsed_us(&wrk->repeat_start, &now); + elapsed = elapsed_us(&wrk->repeat_start, &now); + do_sleep = w->period - elapsed; + time_tot += elapsed; + if (elapsed < time_min) + time_min = elapsed; + if (elapsed > time_max) + time_max = elapsed; if (do_sleep < 0) { - if (verbose > 1) + missed++; + if (verbose > 2) printf("%u: Dropped period @ %u/%u (%dus late)!\n", wrk->id, count, i, do_sleep); continue; @@ -2280,6 +2288,9 @@ static void *run_workload(void *data) printf("%c%u: %.3fs elapsed (%d cycles, %.3f workloads/s).", wrk->background ? ' ' : '*', wrk->id, t, count, count / t); + if (time_tot) + printf(" Time avg/min/max=%lu/%lu/%luus; %u missed.", + time_tot / count, time_min, time_max, missed); putchar('\n'); } -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:14 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:14 +0100 Subject: [Intel-gfx] [PATCH i-g-t 04/10] gem_wsim: Move BO allocation to a helper In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-5-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 60982cb73ba7..5893de38a98e 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -1472,6 +1472,11 @@ get_ctxid(struct workload *wrk, struct w_step *w) return wrk->ctx_list[w->context].id; } +static uint32_t alloc_bo(int i915, unsigned long size) +{ + return gem_create(i915, size); +} + static void alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) { @@ -1483,7 +1488,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) w->obj = calloc(nr_obj, sizeof(*w->obj)); igt_assert(w->obj); - w->obj[j].handle = gem_create(fd, 4096); + w->obj[j].handle = alloc_bo(fd, 4096); w->obj[j].flags = EXEC_OBJECT_WRITE; j++; igt_assert(j < nr_obj); @@ -1528,7 +1533,8 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) else w->bb_sz = get_bb_sz(w, w->duration.max); - w->bb_handle = w->obj[j].handle = gem_create(fd, w->bb_sz + (w->unbound_duration ? 4096 : 0)); + w->bb_handle = w->obj[j].handle = + alloc_bo(fd, w->bb_sz + (w->unbound_duration ? 4096 : 0)); init_bb(w, flags); w->obj[j].relocation_count = terminate_bb(w, flags); @@ -1685,7 +1691,7 @@ static void allocate_working_set(struct working_set *set) igt_assert(set->handles); for (i = 0; i < set->nr; i++) - set->handles[i] = gem_create(fd, set->sizes[i]); + set->handles[i] = alloc_bo(fd, set->sizes[i]); } #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) @@ -2323,7 +2329,7 @@ static unsigned long calibrate_nop(unsigned int tolerance_pct, struct intel_exec do { struct timespec t_start; - obj.handle = gem_create(fd, size); + obj.handle = alloc_bo(fd, size); gem_write(fd, obj.handle, size - sizeof(bbe), &bbe, sizeof(bbe)); gem_execbuf(fd, &eb); -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:15 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:15 +0100 Subject: [Intel-gfx] [PATCH i-g-t 05/10] gem_wsim: Support random buffer sizes In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-6-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> See README for more details. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 71 +++++++++++++++++++++++++++++++++--------- benchmarks/wsim/README | 4 +++ 2 files changed, 61 insertions(+), 14 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 5893de38a98e..c1405596c46a 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -117,12 +117,18 @@ struct bond { enum intel_engine_id master; }; +struct work_buffer_size { + unsigned long size; + unsigned long min; + unsigned long max; +}; + struct working_set { int id; bool shared; unsigned int nr; uint32_t *handles; - unsigned long *sizes; + struct work_buffer_size *sizes; }; struct workload; @@ -203,6 +209,7 @@ struct workload bool print_stats; uint32_t bb_prng; + uint32_t bo_prng; struct timespec repeat_start; @@ -757,10 +764,12 @@ static int add_buffers(struct working_set *set, char *str) * 4m * 4g * 10n4k - 10 4k batches + * 4096-16k - random size in range */ - unsigned long *sizes, size; + struct work_buffer_size *sizes; + unsigned long min_sz, max_sz; + char *n, *max = NULL; unsigned int add, i; - char *n; n = index(str, 'n'); if (n) { @@ -773,16 +782,34 @@ static int add_buffers(struct working_set *set, char *str) add = 1; } - size = parse_size(str); - if (!size) + n = index(str, '-'); + if (n) { + *n = 0; + max = ++n; + } + + min_sz = parse_size(str); + if (!min_sz) return -1; + if (max) { + max_sz = parse_size(max); + if (!max_sz) + return -1; + } else { + max_sz = min_sz; + } + sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); if (!sizes) return -1; - for (i = 0; i < add; i++) - sizes[set->nr + i] = size; + for (i = 0; i < add; i++) { + struct work_buffer_size *sz = &sizes[set->nr + i]; + sz->min = min_sz; + sz->max = max_sz; + sz->size = 0; + } set->nr += add; set->sizes = sizes; @@ -824,7 +851,7 @@ static uint64_t engine_list_mask(const char *_str) return mask; } -static void allocate_working_set(struct working_set *set); +static void allocate_working_set(struct workload *wrk, struct working_set *set); #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ if ((field = strtok_r(fstart, ".", &fctx))) { \ @@ -1177,10 +1204,12 @@ add_step: wrk->nr_steps = nr_steps; wrk->steps = steps; + wrk->flags = flags; wrk->prio = arg->prio; wrk->sseu = arg->sseu; wrk->max_working_set_id = -1; wrk->working_sets = NULL; + wrk->bo_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); free(desc); @@ -1234,7 +1263,7 @@ add_step: */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == WORKINGSET && w->working_set.shared) - allocate_working_set(&w->working_set); + allocate_working_set(wrk, &w->working_set); } wrk->max_working_set_id = -1; @@ -1267,6 +1296,7 @@ clone_workload(struct workload *_wrk) igt_assert(wrk); memset(wrk, 0, sizeof(*wrk)); + wrk->flags = _wrk->flags; wrk->prio = _wrk->prio; wrk->sseu = _wrk->sseu; wrk->nr_steps = _wrk->nr_steps; @@ -1515,7 +1545,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) igt_assert(set->nr); igt_assert(entry->target < set->nr); - igt_assert(set->sizes[entry->target]); + igt_assert(set->sizes[entry->target].size); dep_handle = set->handles[entry->target]; } @@ -1683,15 +1713,27 @@ static size_t sizeof_engines_bond(int count) engines[count]); } -static void allocate_working_set(struct working_set *set) +static unsigned long +get_buffer_size(struct workload *wrk, const struct work_buffer_size *sz) +{ + if (sz->min == sz->max) + return sz->min; + else + return sz->min + hars_petruska_f54_1_random(&wrk->bo_prng) % + (sz->max + 1 - sz->min); +} + +static void allocate_working_set(struct workload *wrk, struct working_set *set) { unsigned int i; set->handles = calloc(set->nr, sizeof(*set->handles)); igt_assert(set->handles); - for (i = 0; i < set->nr; i++) - set->handles[i] = alloc_bo(fd, set->sizes[i]); + for (i = 0; i < set->nr; i++) { + set->sizes[i].size = get_buffer_size(wrk, &set->sizes[i]); + set->handles[i] = alloc_bo(fd, set->sizes[i].size); + } } #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) @@ -1707,6 +1749,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) wrk->id = id; wrk->bb_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); + wrk->bo_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); wrk->run = true; /* @@ -1939,7 +1982,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == WORKINGSET && !w->working_set.shared) - allocate_working_set(&w->working_set); + allocate_working_set(wrk, &w->working_set); } /* diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 3d9143226740..8c71f2fe6579 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -307,11 +307,15 @@ For size a byte size can be given, or suffix 'k', 'm' or 'g' can be used (case insensitive). Prefix in the format of "<int>n<size>" can also be given to create multiple objects of the same size. +Ranges can also be specified using the <min>-<max> syntax. + Examples: w.1.4k - Working set 1 with a single 4KiB object in it. W.2.2M/32768 - Working set 2 with one 2MiB and one 32768 byte object. w.3.10n4k/2n20000 - Working set 3 with ten 4KiB and two 20000 byte objects. + w.4.4n4k-1m - Working set 4 with four objects of random size between 4KiB and + 1MiB. Working set objects can be referenced as data dependency targets using the new 'r'/'w' syntax. Simple example: -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:16 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:16 +0100 Subject: [Intel-gfx] [PATCH i-g-t 06/10] gem_wsim: Support scaling workload batch durations In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-7-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> -f <float> on the command line can be used to scale batch buffer durations in all parsed workloads. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index c1405596c46a..025385a144b8 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -41,6 +41,7 @@ #include <assert.h> #include <limits.h> #include <pthread.h> +#include <math.h> #include "intel_chipset.h" #include "intel_reg.h" @@ -853,6 +854,11 @@ static uint64_t engine_list_mask(const char *_str) static void allocate_working_set(struct workload *wrk, struct working_set *set); +static long __duration(long dur, double scale) +{ + return round(scale * dur); +} + #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ if ((field = strtok_r(fstart, ".", &fctx))) { \ tmp = atoi(field); \ @@ -863,7 +869,8 @@ static void allocate_working_set(struct workload *wrk, struct working_set *set); } \ static struct workload * -parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) +parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur, + struct workload *app_w) { struct workload *wrk; unsigned int nr_steps = 0; @@ -1129,7 +1136,7 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) tmpl == LONG_MAX, "Invalid duration at step %u!\n", nr_steps); - step.duration.min = tmpl; + step.duration.min = __duration(tmpl, scale_dur); if (sep && *sep == '-') { tmpl = strtol(sep + 1, NULL, 10); @@ -1139,7 +1146,8 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) tmpl == LONG_MAX, "Invalid duration range at step %u!\n", nr_steps); - step.duration.max = tmpl; + step.duration.max = __duration(tmpl, + scale_dur); } else { step.duration.max = step.duration.min; } @@ -2494,7 +2502,8 @@ static void print_help(void) " command line. Subsequent -s switches it off.\n" " -S Synchronize the sequence of random batch durations between\n" " clients.\n" -" -d Sync between data dependencies in userspace." +" -d Sync between data dependencies in userspace.\n" +" -f <scale> Scale factor for batch durations." ); } @@ -2556,6 +2565,7 @@ int main(int argc, char **argv) struct w_arg *w_args = NULL; unsigned int tolerance_pct = 1; int exitcode = EXIT_FAILURE; + double scale_arg = 1.0f; int prio = 0; double t; int i, c; @@ -2576,7 +2586,7 @@ int main(int argc, char **argv) master_prng = time(NULL); while ((c = getopt(argc, argv, - "ThqvsSdc:n:r:w:W:a:t:p:I:")) != -1) { + "ThqvsSdc:n:r:w:W:a:t:p:I:f:")) != -1) { switch (c) { case 'W': if (master_workload >= 0) { @@ -2687,6 +2697,9 @@ int main(int argc, char **argv) case 'I': master_prng = strtol(optarg, NULL, 0); break; + case 'f': + scale_arg = atof(optarg); + break; case 'h': print_help(); goto out; @@ -2744,7 +2757,7 @@ int main(int argc, char **argv) if (append_workload_arg) { struct w_arg arg = { NULL, append_workload_arg, 0 }; - app_w = parse_workload(&arg, flags, NULL); + app_w = parse_workload(&arg, flags, scale_arg, NULL); if (!app_w) { wsim_err("Failed to parse append workload!\n"); goto err; @@ -2762,7 +2775,7 @@ int main(int argc, char **argv) goto err; } - wrk[i] = parse_workload(&w_args[i], flags, app_w); + wrk[i] = parse_workload(&w_args[i], flags, scale_arg, app_w); if (!wrk[i]) { wsim_err("Failed to parse workload %u!\n", i); goto err; -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:17 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:17 +0100 Subject: [Intel-gfx] [PATCH i-g-t 07/10] gem_wsim: Log max and active working set sizes in verbose mode In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-8-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> It is useful to know how much memory workload is allocating. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 100 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 95 insertions(+), 5 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 025385a144b8..96ee923fb699 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -852,7 +852,8 @@ static uint64_t engine_list_mask(const char *_str) return mask; } -static void allocate_working_set(struct workload *wrk, struct working_set *set); +static unsigned long +allocate_working_set(struct workload *wrk, struct working_set *set); static long __duration(long dur, double scale) { @@ -1270,8 +1271,14 @@ add_step: * Allocate shared working sets. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - if (w->type == WORKINGSET && w->working_set.shared) - allocate_working_set(wrk, &w->working_set); + if (w->type == WORKINGSET && w->working_set.shared) { + unsigned long total = + allocate_working_set(wrk, &w->working_set); + + if (verbose > 1) + printf("%u: %lu bytes in shared working set %u\n", + wrk->id, total, w->working_set.id); + } } wrk->max_working_set_id = -1; @@ -1731,8 +1738,10 @@ get_buffer_size(struct workload *wrk, const struct work_buffer_size *sz) (sz->max + 1 - sz->min); } -static void allocate_working_set(struct workload *wrk, struct working_set *set) +static unsigned long +allocate_working_set(struct workload *wrk, struct working_set *set) { + unsigned long total = 0; unsigned int i; set->handles = calloc(set->nr, sizeof(*set->handles)); @@ -1741,7 +1750,82 @@ static void allocate_working_set(struct workload *wrk, struct working_set *set) for (i = 0; i < set->nr; i++) { set->sizes[i].size = get_buffer_size(wrk, &set->sizes[i]); set->handles[i] = alloc_bo(fd, set->sizes[i].size); + total += set->sizes[i].size; + } + + return total; +} + +static bool +find_dep(struct dep_entry *deps, unsigned int nr, struct dep_entry dep) +{ + unsigned int i; + + for (i = 0; i < nr; i++) { + if (deps[i].working_set == dep.working_set && + deps[i].target == dep.target) + return true; } + + return false; +} + +static void measure_active_set(struct workload *wrk) +{ + unsigned long total = 0, batch_sizes = 0; + struct dep_entry *deps = NULL; + unsigned int nr = 0, i, j; + struct w_step *w; + + if (verbose < 3) + return; + + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type != BATCH) + continue; + + batch_sizes += w->bb_sz; + + for (j = 0; j < w->data_deps.nr; j++) { + struct dep_entry *dep = &w->data_deps.list[j]; + struct dep_entry _dep = *dep; + + if (dep->working_set == -1 && dep->target < 0) { + int idx = w->idx + dep->target; + + igt_assert(idx >= 0 && idx < w->idx); + igt_assert(wrk->steps[idx].type == BATCH); + + _dep.target = wrk->steps[idx].obj[0].handle; + } + + if (!find_dep(deps, nr, _dep)) { + if (dep->working_set == -1) { + total += 4096; + } else { + struct working_set *set; + + igt_assert(dep->working_set <= + wrk->max_working_set_id); + + set = wrk->working_sets[dep->working_set]; + igt_assert(set->nr); + igt_assert(dep->target < set->nr); + igt_assert(set->sizes[dep->target].size); + + total += set->sizes[dep->target].size; + } + + deps = realloc(deps, (nr + 1) * sizeof(*deps)); + deps[nr++] = *dep; + } + } + } + + free(deps); + + printf("%u: %lu bytes active working set in %u buffers. %lu in batch buffers.\n", + wrk->id, total, nr, batch_sizes); } #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) @@ -1750,6 +1834,7 @@ static int prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) { struct working_set **sets; + unsigned long total = 0; uint32_t share_vm = 0; int max_ctx = -1; struct w_step *w; @@ -1990,9 +2075,12 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == WORKINGSET && !w->working_set.shared) - allocate_working_set(wrk, &w->working_set); + total += allocate_working_set(wrk, &w->working_set); } + if (verbose > 2) + printf("%u: %lu bytes in working sets.\n", wrk->id, total); + /* * Map of working set ids. */ @@ -2040,6 +2128,8 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) alloc_step_batch(wrk, w, flags); } + measure_active_set(wrk); + return 0; } -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:18 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:18 +0100 Subject: [Intel-gfx] [PATCH i-g-t 08/10] gem_wsim: Snippet of a workload extracted from carchase In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-9-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Some frames from the middle of a demo with corresponding buffers. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/wsim/carchasepart.wsim | 184 ++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 benchmarks/wsim/carchasepart.wsim diff --git a/benchmarks/wsim/carchasepart.wsim b/benchmarks/wsim/carchasepart.wsim new file mode 100644 index 000000000000..4407d0ef47dc --- /dev/null +++ b/benchmarks/wsim/carchasepart.wsim @@ -0,0 +1,184 @@ +w.0.118n8192 +w.1.69n12288 +w.10.145n131072 +w.11.1n163840 +w.12.3n196608 +w.13.2n229376 +w.14.2n262144 +w.15.7n327680 +w.16.2n393216 +w.17.9n458752 +w.18.30n524288 +w.19.1n655360 +w.2.74n16384 +w.20.2n917504 +w.21.1n1048576 +w.22.33n1310720 +w.23.1n1572864 +w.24.24n1835008 +w.25.117n2097152 +w.26.1n2621440 +w.27.2n3670016 +w.28.4n4194304 +w.29.3n6291456 +w.3.123n20480 +w.30.1n7340032 +w.31.1n8388608 +w.32.20n10485760 +w.33.4n12582912 +w.34.3n14680064 +w.35.1n25165824 +w.4.19n24576 +w.5.2n32768 +w.6.2n40960 +w.7.4n49152 +w.8.2n65536 +w.9.9n81920 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+1.RCS.6159.r3-80/r22-31/r3-74/r3-0/r9-4/w9-5/r0-92/r0-58/w32-19/r3-18/r3-60/r22-14/r3-78/r3-88/r22-5/r22-6/r22-29/r22-7/r22-1/r22-12/r22-18/r22-28/r22-3/r22-0/r3-75/r3-104/w3-64/r0-87/r22-20/r25-99/r22-16/r21-0/r0-106/r0-71/r0-26/w28-2/r0-107/w8-0/r0-75.0 -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:20 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:20 +0100 Subject: [Intel-gfx] [PATCH i-g-t 10/10] gem_wsim: Fix calibration handling In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-11-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Intended use case was that run without arguments prints out the calibrations which can be simply copied and pasted to the -n argument and things should just work. Two problems we need to solve: If the print out loops shows zero calibrations (engine not present) they are later rejected and also if some calibration is not given it is only an error if it needs to be used (engine present). Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index ca07b670bd42..3bbb8fcbe17c 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -296,8 +296,8 @@ print_engine_calibrations(void) printf("Nop calibration for %uus delay is: ", nop_calibration_us); for (int i = 0; i < NUM_ENGINES; i++) { - /* skip DEFAULT and VCS engines */ - if (i != DEFAULT && i != VCS) { + /* skip engines not present and DEFAULT and VCS */ + if (i != DEFAULT && i != VCS && engine_calib_map[i]) { if (first_entry) { printf("%s=%lu", ring_str_map[i], engine_calib_map[i]); first_entry = false; @@ -2840,22 +2840,6 @@ int main(int argc, char **argv) if (verbose) print_engine_calibrations(); goto out; - } else { - bool missing = false; - - for (i = 0; i < NUM_ENGINES; i++) { - if (i == VCS) - continue; - - if (!engine_calib_map[i]) { - wsim_err("Missing calibration for '%s'!\n", - ring_str_map[i]); - missing = true; - } - } - - if (missing) - goto err; } if (!nr_w_args) { -- 2.20.1 From tvrtko.ursulin at linux.intel.com Wed Jun 17 16:01:19 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Wed, 17 Jun 2020 17:01:19 +0100 Subject: [Intel-gfx] [PATCH i-g-t 09/10] gem_wsim: Implement device selection In-Reply-To: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200617160120.16555-10-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> New command line options -L and -D <device> can respectively be used to list and select a GPU when more than one is present. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 62 +++++++++++++++++++++++++++++++------------ 1 file changed, 45 insertions(+), 17 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 96ee923fb699..ca07b670bd42 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -43,6 +43,7 @@ #include <pthread.h> #include <math.h> +#include "igt_device_scan.h" #include "intel_chipset.h" #include "intel_reg.h" #include "drm.h" @@ -2593,7 +2594,9 @@ static void print_help(void) " -S Synchronize the sequence of random batch durations between\n" " clients.\n" " -d Sync between data dependencies in userspace.\n" -" -f <scale> Scale factor for batch durations." +" -f <scale> Scale factor for batch durations.\n" +" -L List GPUs.\n" +" -D <gpu> One of the GPUs from -L." ); } @@ -2654,30 +2657,31 @@ int main(int argc, char **argv) char *append_workload_arg = NULL; struct w_arg *w_args = NULL; unsigned int tolerance_pct = 1; + enum igt_devices_print_type printtype = IGT_PRINT_SIMPLE; + bool list_devices_arg = false; int exitcode = EXIT_FAILURE; + struct igt_device_card card; double scale_arg = 1.0f; + char *device_arg = NULL; int prio = 0; double t; - int i, c; + int i, c, ret; char *subopts, *value; int raw_number = 0; long calib_val; int eng; - /* - * Open the device via the low-level API so we can do the GPU quiesce - * manually as close as possible in time to the start of the workload. - * This minimizes the gap in engine utilization tracking when observed - * via external tools like trace.pl. - */ - fd = __drm_open_driver_render(DRIVER_INTEL); - igt_require(fd); - master_prng = time(NULL); while ((c = getopt(argc, argv, - "ThqvsSdc:n:r:w:W:a:t:p:I:f:")) != -1) { + "LThqvsSdc:n:r:w:W:a:t:p:I:f:D:")) != -1) { switch (c) { + case 'L': + list_devices_arg = true; + break; + case 'D': + device_arg = strdup(optarg); + break; case 'W': if (master_workload >= 0) { wsim_err("Only one master workload can be given!\n"); @@ -2798,6 +2802,33 @@ int main(int argc, char **argv) } } + + igt_devices_scan(false); + + if (list_devices_arg) { + igt_devices_print(printtype); + return EXIT_SUCCESS; + } + + if (device_arg) { + ret = igt_device_card_match(device_arg, &card); + if (!ret) { + wsim_err("Requested device %s not found!\n", device_arg); + free(device_arg); + + return EXIT_FAILURE; + } + free(device_arg); + } else { + igt_device_find_first_i915_discrete_card(&card); + } + + if (card.render[0]) + fd = igt_open_render(&card); + else + fd = __drm_open_driver_render(DRIVER_INTEL); + igt_require(fd); + if (!has_nop_calibration) { if (verbose > 1) { printf("Calibrating nop delays with %u%% tolerance...\n", @@ -2908,15 +2939,12 @@ int main(int argc, char **argv) clock_gettime(CLOCK_MONOTONIC, &t_start); for (i = 0; i < clients; i++) { - int ret; - ret = pthread_create(&w[i]->thread, NULL, run_workload, w[i]); igt_assert_eq(ret, 0); } if (master_workload >= 0) { - int ret = pthread_join(w[master_workload]->thread, NULL); - + ret = pthread_join(w[master_workload]->thread, NULL); igt_assert(ret == 0); for (i = 0; i < clients; i++) @@ -2925,7 +2953,7 @@ int main(int argc, char **argv) for (i = 0; i < clients; i++) { if (master_workload != i) { - int ret = pthread_join(w[i]->thread, NULL); + ret = pthread_join(w[i]->thread, NULL); igt_assert(ret == 0); } } -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 17 16:07:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 17:07:54 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/10] gem_wsim: Rip out userspace balancing In-Reply-To: <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> Message-ID: <159241007493.19488.13894581877702829359@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:11) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Evaluation of userspace load balancing options was how this tool started > but since we have settled on doing it in the kernel. > > Tomorrow we will want to update the tool for new engine interfaces and all > this legacy code will just be a distraction. > > Rip out everything not related to explicit load balancing implemented via > context engine maps and adjust the workloads to use it. I'm still using busy & contexts to ground i915. Any chance of a reprieve? At least for context with -R? Or shall I just keep a pristine copy? -Chris From chris at chris-wilson.co.uk Wed Jun 17 16:22:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 17:22:16 +0100 Subject: [Intel-gfx] [PATCH i-g-t 06/10] gem_wsim: Support scaling workload batch durations In-Reply-To: <20200617160120.16555-7-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-7-tvrtko.ursulin@linux.intel.com> Message-ID: <159241093617.19488.6127572319183957508@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:16) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > -f <float> on the command line can be used to scale batch buffer durations > in all parsed workloads. But not the period? -Chris From chris at chris-wilson.co.uk Wed Jun 17 16:31:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 17:31:17 +0100 Subject: [Intel-gfx] [PATCH i-g-t 05/10] gem_wsim: Support random buffer sizes In-Reply-To: <20200617160120.16555-6-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-6-tvrtko.ursulin@linux.intel.com> Message-ID: <159241147774.19488.12762220143650374149@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:15) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > See README for more details. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > benchmarks/gem_wsim.c | 71 +++++++++++++++++++++++++++++++++--------- > benchmarks/wsim/README | 4 +++ > 2 files changed, 61 insertions(+), 14 deletions(-) > > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > index 5893de38a98e..c1405596c46a 100644 > --- a/benchmarks/gem_wsim.c > +++ b/benchmarks/gem_wsim.c > @@ -117,12 +117,18 @@ struct bond { > enum intel_engine_id master; > }; > > +struct work_buffer_size { > + unsigned long size; > + unsigned long min; > + unsigned long max; > +}; > + > struct working_set { > int id; > bool shared; > unsigned int nr; > uint32_t *handles; > - unsigned long *sizes; > + struct work_buffer_size *sizes; > }; > > struct workload; > @@ -203,6 +209,7 @@ struct workload > bool print_stats; > > uint32_t bb_prng; > + uint32_t bo_prng; > > struct timespec repeat_start; > > @@ -757,10 +764,12 @@ static int add_buffers(struct working_set *set, char *str) > * 4m > * 4g > * 10n4k - 10 4k batches > + * 4096-16k - random size in range > */ > - unsigned long *sizes, size; > + struct work_buffer_size *sizes; > + unsigned long min_sz, max_sz; > + char *n, *max = NULL; > unsigned int add, i; > - char *n; > > n = index(str, 'n'); > if (n) { > @@ -773,16 +782,34 @@ static int add_buffers(struct working_set *set, char *str) > add = 1; > } > > - size = parse_size(str); > - if (!size) > + n = index(str, '-'); > + if (n) { > + *n = 0; > + max = ++n; > + } > + > + min_sz = parse_size(str); > + if (!min_sz) > return -1; > > + if (max) { > + max_sz = parse_size(max); > + if (!max_sz) > + return -1; > + } else { > + max_sz = min_sz; > + } > + > sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); > if (!sizes) > return -1; > > - for (i = 0; i < add; i++) > - sizes[set->nr + i] = size; > + for (i = 0; i < add; i++) { > + struct work_buffer_size *sz = &sizes[set->nr + i]; > + sz->min = min_sz; > + sz->max = max_sz; > + sz->size = 0; > + } > > set->nr += add; > set->sizes = sizes; > @@ -824,7 +851,7 @@ static uint64_t engine_list_mask(const char *_str) > return mask; > } > > -static void allocate_working_set(struct working_set *set); > +static void allocate_working_set(struct workload *wrk, struct working_set *set); > > #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ > if ((field = strtok_r(fstart, ".", &fctx))) { \ > @@ -1177,10 +1204,12 @@ add_step: > > wrk->nr_steps = nr_steps; > wrk->steps = steps; > + wrk->flags = flags; > wrk->prio = arg->prio; > wrk->sseu = arg->sseu; > wrk->max_working_set_id = -1; > wrk->working_sets = NULL; > + wrk->bo_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); > > free(desc); > > @@ -1234,7 +1263,7 @@ add_step: > */ > for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { > if (w->type == WORKINGSET && w->working_set.shared) > - allocate_working_set(&w->working_set); > + allocate_working_set(wrk, &w->working_set); > } > > wrk->max_working_set_id = -1; > @@ -1267,6 +1296,7 @@ clone_workload(struct workload *_wrk) > igt_assert(wrk); > memset(wrk, 0, sizeof(*wrk)); > > + wrk->flags = _wrk->flags; > wrk->prio = _wrk->prio; > wrk->sseu = _wrk->sseu; > wrk->nr_steps = _wrk->nr_steps; wrk->flags wasn't introduced in this patch, why are we needing to copy them now. I see wrk->bo_prn = flags & SYNC above, but I haven't seem them used again later. They used to carry the balancer info and were setup in main. Am I not mistaken in thinking they still are being set in main() as well? -Chris From chris at chris-wilson.co.uk Wed Jun 17 16:57:02 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 17:57:02 +0100 Subject: [Intel-gfx] [PATCH i-g-t 02/10] gem_wsim: Buffer objects working sets and complex dependencies In-Reply-To: <20200617160120.16555-3-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-3-tvrtko.ursulin@linux.intel.com> Message-ID: <159241302236.19488.10161905992897259551@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:12) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Add support for defining buffer object working sets and targetting them as > data dependencies. For more information please see the README file. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > benchmarks/gem_wsim.c | 453 +++++++++++++++++++++--- > benchmarks/wsim/README | 59 +++ > benchmarks/wsim/cloud-gaming-60fps.wsim | 11 + > benchmarks/wsim/composited-ui.wsim | 7 + > 4 files changed, 476 insertions(+), 54 deletions(-) > create mode 100644 benchmarks/wsim/cloud-gaming-60fps.wsim > create mode 100644 benchmarks/wsim/composited-ui.wsim > > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > index 02fe8f5a5e69..9e5bfe6a36d4 100644 > --- a/benchmarks/gem_wsim.c > +++ b/benchmarks/gem_wsim.c > @@ -88,14 +88,21 @@ enum w_type > LOAD_BALANCE, > BOND, > TERMINATE, > - SSEU > + SSEU, > + WORKINGSET, > +}; > + > +struct dep_entry { > + int target; > + bool write; > + int working_set; /* -1 = step dependecy, >= 0 working set id */ > }; > > struct deps > { > int nr; > bool submit_fence; > - int *list; > + struct dep_entry *list; > }; > > struct w_arg { > @@ -110,6 +117,14 @@ struct bond { > enum intel_engine_id master; > }; > > +struct working_set { > + int id; > + bool shared; > + unsigned int nr; > + uint32_t *handles; > + unsigned long *sizes; > +}; > + > struct workload; > > struct w_step > @@ -143,6 +158,7 @@ struct w_step > enum intel_engine_id bond_master; > }; > int sseu; > + struct working_set working_set; > }; > > /* Implementation details */ > @@ -193,6 +209,9 @@ struct workload > unsigned int nr_ctxs; > struct ctx *ctx_list; > > + struct working_set **working_sets; /* array indexed by set id */ > + int max_working_set_id; > + > int sync_timeline; > uint32_t sync_seqno; > > @@ -281,11 +300,120 @@ print_engine_calibrations(void) > printf("\n"); > } > > +static void add_dep(struct deps *deps, struct dep_entry entry) > +{ > + deps->list = realloc(deps->list, sizeof(*deps->list) * (deps->nr + 1)); > + igt_assert(deps->list); > + > + deps->list[deps->nr++] = entry; > +} > + > + > +static int > +parse_dependency(unsigned int nr_steps, struct w_step *w, char *str) > +{ > + struct dep_entry entry = { .working_set = -1 }; > + bool submit_fence = false; > + char *s; > + > + switch (str[0]) { > + case '-': > + if (str[1] < '0' || str[1] > '9') > + return -1; > + > + entry.target = atoi(str); > + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) > + return -1; add_dep for N steps ago, using a handle. > + > + add_dep(&w->data_deps, entry); > + > + break; > + case 's': > + submit_fence = true; > + /* Fall-through. */ > + case 'f': > + /* Multiple fences not yet supported. */ > + igt_assert_eq(w->fence_deps.nr, 0); > + > + entry.target = atoi(++str); > + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) > + return -1; > + > + add_dep(&w->fence_deps, entry); > + > + w->fence_deps.submit_fence = submit_fence; add_dep for N steps ago, using the out-fence from that step [A post processing steps adds emit_fence to the earlier steps.] > + break; > + case 'w': > + entry.write = true; Got confused for a moment as I was expecting the submit_fence fallthrough pattern. > + /* Fall-through. */ > + case 'r': > + /* > + * [rw]N-<str> > + * r1-<str> or w2-<str>, where N is working set id. > + */ > + s = index(++str, '-'); > + if (!s) > + return -1; > + > + entry.working_set = atoi(str); if (entry.working_set < 0) return -1; > + > + if (parse_working_set_deps(w->wrk, &w->data_deps, entry, ++s)) > + return -1; The new one... > +static int > +parse_working_set_deps(struct workload *wrk, > + struct deps *deps, > + struct dep_entry _entry, > + char *str) > +{ > + /* > + * 1 - target handle index in the specified working set. > + * 2-4 - range > + */ > + struct dep_entry entry = _entry; > + char *s; > + > + s = index(str, '-'); > + if (s) { > + int from, to; > + > + from = atoi(str); > + if (from < 0) > + return -1; > + > + to = atoi(++s); > + if (to <= 0) > + return -1; if to < from, we add nothing. Is that worth the error? > + > + for (entry.target = from; entry.target <= to; entry.target++) > + add_dep(deps, entry); > + } else { > + entry.target = atoi(str); > + if (entry.target < 0) > + return -1; > + > + add_dep(deps, entry); > + } > + > + return 0; > +} > + > + break; > + default: > + return -1; > + }; > + > + return 0; > +} > + > static int > parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) > { > char *desc = strdup(_desc); > char *token, *tctx = NULL, *tstart = desc; > + int ret = 0; > + > + if (!strcmp(_desc, "0")) > + goto out; Hang on, what this special case? > > igt_assert(desc); > igt_assert(!w->data_deps.nr && w->data_deps.nr == w->fence_deps.nr); > static void __attribute__((format(printf, 1, 2))) > @@ -624,6 +722,88 @@ static int parse_engine_map(struct w_step *step, const char *_str) > return 0; > } > > +static unsigned long parse_size(char *str) > +{ /* "1234567890[gGmMkK]" */ > + const unsigned int len = strlen(str); > + unsigned int mult = 1; > + > + if (len == 0) > + return 0; > + > + switch (str[len - 1]) { T? P? E? Let's plan ahead! :) > + case 'g': > + case 'G': > + mult *= 1024; > + /* Fall-throuogh. */ > + case 'm': > + case 'M': > + mult *= 1024; > + /* Fall-throuogh. */ > + case 'k': > + case 'K': > + mult *= 1024; > + > + str[len - 1] = 0; > + } > + > + return atol(str) * mult; Negatives? > +} > + > +static int add_buffers(struct working_set *set, char *str) > +{ > + /* > + * 4096 > + * 4k > + * 4m > + * 4g > + * 10n4k - 10 4k batches > + */ > + unsigned long *sizes, size; > + unsigned int add, i; > + char *n; > + > + n = index(str, 'n'); > + if (n) { > + *n = 0; > + add = atoi(str); > + if (!add) > + return -1; if (add <= 0) [int add goes without saying then] > + str = ++n; > + } else { > + add = 1; > + } > + > + size = parse_size(str); > + if (!size) > + return -1; > + > + sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); > + if (!sizes) > + return -1; > + > + for (i = 0; i < add; i++) > + sizes[set->nr + i] = size; > + > + set->nr += add; > + set->sizes = sizes; > + > + return 0; > +} > @@ -1003,6 +1209,51 @@ add_step: > } > } > > + /* > + * Check no duplicate working set ids. > + */ > + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { > + struct w_step *w2; > + > + if (w->type != WORKINGSET) > + continue; > + > + for (j = 0, w2 = wrk->steps; j < wrk->nr_steps; w2++, j++) { > + if (j == i) > + continue; > + if (w2->type != WORKINGSET) > + continue; > + > + check_arg(w->working_set.id == w2->working_set.id, > + "Duplicate working set id at %u!\n", j); > + } > + } > + > + /* > + * Allocate shared working sets. > + */ > + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { > + if (w->type == WORKINGSET && w->working_set.shared) > + allocate_working_set(&w->working_set); > + } > + > + wrk->max_working_set_id = -1; > + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { > + if (w->type == WORKINGSET && > + w->working_set.shared && > + w->working_set.id > wrk->max_working_set_id) > + wrk->max_working_set_id = w->working_set.id; > + } > + > + wrk->working_sets = calloc(wrk->max_working_set_id + 1, > + sizeof(*wrk->working_sets)); > + igt_assert(wrk->working_sets); > + > + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { > + if (w->type == WORKINGSET && w->working_set.shared) > + wrk->working_sets[w->working_set.id] = &w->working_set; > + } Ok, sharing works by reusing the same set of handles within the process. Is there room in the parser namespace for dmabuf sharing? -Chris From chris at chris-wilson.co.uk Wed Jun 17 16:58:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 17:58:21 +0100 Subject: [Intel-gfx] [PATCH i-g-t 03/10] gem_wsim: Show workload timing stats In-Reply-To: <20200617160120.16555-4-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-4-tvrtko.ursulin@linux.intel.com> Message-ID: <159241310169.19488.4644166988486362775@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:13) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Show average/min/max workload iteration and dropped period stats when 'p' > command is used. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > benchmarks/gem_wsim.c | 19 +++++++++++++++---- > 1 file changed, 15 insertions(+), 4 deletions(-) > > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > index 9e5bfe6a36d4..60982cb73ba7 100644 > --- a/benchmarks/gem_wsim.c > +++ b/benchmarks/gem_wsim.c > @@ -2101,7 +2101,8 @@ static void *run_workload(void *data) > struct w_step *w; > int throttle = -1; > int qd_throttle = -1; > - int count; > + int count, missed = 0; > + unsigned long time_tot = 0, time_min = ULONG_MAX, time_max = 0; > int i; > > clock_gettime(CLOCK_MONOTONIC, &t_start); > @@ -2121,12 +2122,19 @@ static void *run_workload(void *data) > do_sleep = w->delay; > } else if (w->type == PERIOD) { > struct timespec now; > + int elapsed; > > clock_gettime(CLOCK_MONOTONIC, &now); > - do_sleep = w->period - > - elapsed_us(&wrk->repeat_start, &now); > + elapsed = elapsed_us(&wrk->repeat_start, &now); > + do_sleep = w->period - elapsed; > + time_tot += elapsed; > + if (elapsed < time_min) > + time_min = elapsed; > + if (elapsed > time_max) > + time_max = elapsed; Keep the running average? > if (do_sleep < 0) { > - if (verbose > 1) > + missed++; > + if (verbose > 2) > printf("%u: Dropped period @ %u/%u (%dus late)!\n", > wrk->id, count, i, do_sleep); > continue; > @@ -2280,6 +2288,9 @@ static void *run_workload(void *data) > printf("%c%u: %.3fs elapsed (%d cycles, %.3f workloads/s).", > wrk->background ? ' ' : '*', wrk->id, > t, count, count / t); > + if (time_tot) > + printf(" Time avg/min/max=%lu/%lu/%luus; %u missed.", > + time_tot / count, time_min, time_max, missed); > putchar('\n'); > } > > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > From chris at chris-wilson.co.uk Wed Jun 17 17:07:22 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 18:07:22 +0100 Subject: [Intel-gfx] [PATCH i-g-t 07/10] gem_wsim: Log max and active working set sizes in verbose mode In-Reply-To: <20200617160120.16555-8-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-8-tvrtko.ursulin@linux.intel.com> Message-ID: <159241364264.19488.3379036675234090722@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:17) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > It is useful to know how much memory workload is allocating. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > benchmarks/gem_wsim.c | 100 +++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 95 insertions(+), 5 deletions(-) > > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > index 025385a144b8..96ee923fb699 100644 > --- a/benchmarks/gem_wsim.c > +++ b/benchmarks/gem_wsim.c > @@ -852,7 +852,8 @@ static uint64_t engine_list_mask(const char *_str) > return mask; > } > > -static void allocate_working_set(struct workload *wrk, struct working_set *set); > +static unsigned long > +allocate_working_set(struct workload *wrk, struct working_set *set); > > static long __duration(long dur, double scale) > { > @@ -1270,8 +1271,14 @@ add_step: > * Allocate shared working sets. > */ > for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { > - if (w->type == WORKINGSET && w->working_set.shared) > - allocate_working_set(wrk, &w->working_set); > + if (w->type == WORKINGSET && w->working_set.shared) { > + unsigned long total = > + allocate_working_set(wrk, &w->working_set); > + > + if (verbose > 1) > + printf("%u: %lu bytes in shared working set %u\n", > + wrk->id, total, w->working_set.id); > + } > } The total total might be nice; although that doesn't reflect usage so might be misleading as to what is the active RSS is at any time. > wrk->max_working_set_id = -1; > @@ -1731,8 +1738,10 @@ get_buffer_size(struct workload *wrk, const struct work_buffer_size *sz) > (sz->max + 1 - sz->min); > } > > -static void allocate_working_set(struct workload *wrk, struct working_set *set) > +static unsigned long > +allocate_working_set(struct workload *wrk, struct working_set *set) > { > + unsigned long total = 0; > unsigned int i; > > set->handles = calloc(set->nr, sizeof(*set->handles)); > @@ -1741,7 +1750,82 @@ static void allocate_working_set(struct workload *wrk, struct working_set *set) > for (i = 0; i < set->nr; i++) { > set->sizes[i].size = get_buffer_size(wrk, &set->sizes[i]); > set->handles[i] = alloc_bo(fd, set->sizes[i].size); > + total += set->sizes[i].size; > + } > + > + return total; > +} > + > +static bool > +find_dep(struct dep_entry *deps, unsigned int nr, struct dep_entry dep) > +{ > + unsigned int i; > + > + for (i = 0; i < nr; i++) { > + if (deps[i].working_set == dep.working_set && > + deps[i].target == dep.target) > + return true; > } > + > + return false; > +} > + > +static void measure_active_set(struct workload *wrk) > +{ > + unsigned long total = 0, batch_sizes = 0; > + struct dep_entry *deps = NULL; > + unsigned int nr = 0, i, j; > + struct w_step *w; > + > + if (verbose < 3) > + return; > + > + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { > + if (w->type != BATCH) > + continue; > + > + batch_sizes += w->bb_sz; > + > + for (j = 0; j < w->data_deps.nr; j++) { > + struct dep_entry *dep = &w->data_deps.list[j]; > + struct dep_entry _dep = *dep; > + > + if (dep->working_set == -1 && dep->target < 0) { > + int idx = w->idx + dep->target; > + > + igt_assert(idx >= 0 && idx < w->idx); > + igt_assert(wrk->steps[idx].type == BATCH); > + > + _dep.target = wrk->steps[idx].obj[0].handle; > + } > + > + if (!find_dep(deps, nr, _dep)) { > + if (dep->working_set == -1) { > + total += 4096; > + } else { > + struct working_set *set; > + > + igt_assert(dep->working_set <= > + wrk->max_working_set_id); > + > + set = wrk->working_sets[dep->working_set]; > + igt_assert(set->nr); > + igt_assert(dep->target < set->nr); > + igt_assert(set->sizes[dep->target].size); > + > + total += set->sizes[dep->target].size; > + } > + > + deps = realloc(deps, (nr + 1) * sizeof(*deps)); > + deps[nr++] = *dep; > + } > + } > + } So a sum of all the unique handles used by all the steps. Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Wed Jun 17 17:09:00 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 18:09:00 +0100 Subject: [Intel-gfx] [PATCH i-g-t 09/10] gem_wsim: Implement device selection In-Reply-To: <20200617160120.16555-10-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-10-tvrtko.ursulin@linux.intel.com> Message-ID: <159241374015.19488.9326114327906198949@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:19) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > New command line options -L and -D <device> can respectively be used to > list and select a GPU when more than one is present. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > benchmarks/gem_wsim.c | 62 +++++++++++++++++++++++++++++++------------ > 1 file changed, 45 insertions(+), 17 deletions(-) > > diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > index 96ee923fb699..ca07b670bd42 100644 > --- a/benchmarks/gem_wsim.c > +++ b/benchmarks/gem_wsim.c > @@ -43,6 +43,7 @@ > #include <pthread.h> > #include <math.h> > > +#include "igt_device_scan.h" > #include "intel_chipset.h" > #include "intel_reg.h" > #include "drm.h" > @@ -2593,7 +2594,9 @@ static void print_help(void) > " -S Synchronize the sequence of random batch durations between\n" > " clients.\n" > " -d Sync between data dependencies in userspace.\n" > -" -f <scale> Scale factor for batch durations." > +" -f <scale> Scale factor for batch durations.\n" > +" -L List GPUs.\n" > +" -D <gpu> One of the GPUs from -L." This is unlike you, I was expecting a range! -Chris From jose.souza at intel.com Wed Jun 17 17:34:21 2020 From: jose.souza at intel.com (Souza, Jose) Date: Wed, 17 Jun 2020 17:34:21 +0000 Subject: [Intel-gfx] i915/kexec: warning at drivers/gpu/drm/i915/display/intel_psr.c:782 intel_psr_activate+0x3c6/0x440 In-Reply-To: <20200617065315.GA6501@dhcp-128-65.nay.redhat.com> References: <20200617065315.GA6501@dhcp-128-65.nay.redhat.com> Message-ID: <b9abdee84e2465da720d2c44e80ba286470f7f3d.camel@intel.com> Hi Dave Will take care of this, looks like PSR2 was left enabled by UEFI/BIOS then i915 enables PSR1.Are you affected by any visual glitches or other issues? Could you attach a log with drm.debug=0x1e set? Thanks On Wed, 2020-06-17 at 14:53 +0800, Dave Young wrote: > Hi, > > This warning exists for long time, I did not find time to report, here > is the latest kernel logs, can you please to have a look? > > hardware: Thinkpad T480s > lspci: 00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 07) > -- > [ 0.000000] Linux version 5.8.0-rc1+ (dyoung at dhcp-128-65.nay.redhat.com) (gcc (GCC) 10.0.1 20200328 (Red Hat 10.0.1-0.11), GNU ld version 2.34-2.fc32) #179 SMP Wed Jun 17 14:12:27 CST 2020 > [ 0.000000] Command line: ramoops.mem_address=0x20000000 ramoops.mem_size=0x400000 hung_task_panic=1 softlockup_panic=1 panic=6 root=/dev/nvme0n1p9 ro rd.lvm.lv=rhel/swap LANG=zh_CN.UTF-8 audit=0 selinux=0 no_console_suspend crashkernel=160M printk.devkmsg=off usbcore.autosuspend=-1 > [ 0.000000] KERNEL supported cpus: > [ 0.000000] Intel GenuineIntel > [ 0.000000] AMD AuthenticAMD > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers' > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR' > [ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 > [ 0.000000] x86/fpu: xstate_offset[3]: 832, xstate_sizes[3]: 64 > [ 0.000000] x86/fpu: xstate_offset[4]: 896, xstate_sizes[4]: 64 > [ 0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format. > [ 0.000000] BIOS-provided physical RAM map: > [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable > [ 0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved > [ 0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009cfff] usable > [ 0.000000] BIOS-e820: [mem 0x000000000009d000-0x00000000000fffff] reserved > [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000003fffffff] usable > [ 0.000000] BIOS-e820: [mem 0x0000000040000000-0x00000000403fffff] reserved > [ 0.000000] BIOS-e820: [mem 0x0000000040400000-0x000000007b4b2fff] usable > [ 0.000000] BIOS-e820: [mem 0x000000007b4b3000-0x000000007b4b4fff] reserved > [ 0.000000] BIOS-e820: [mem 0x000000007b4b5000-0x000000007b51cfff] usable > [ 0.000000] BIOS-e820: [mem 0x000000007b51d000-0x000000007b51dfff] reserved > [ 0.000000] BIOS-e820: [mem 0x000000007b51e000-0x00000000ad334fff] usable > [ 0.000000] BIOS-e820: [mem 0x00000000ad335000-0x00000000ad335fff] ACPI NVS > [ 0.000000] BIOS-e820: [mem 0x00000000ad336000-0x00000000ad336fff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000ad337000-0x00000000ba3e9fff] usable > [ 0.000000] BIOS-e820: [mem 0x00000000ba3ea000-0x00000000bb535fff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000bb536000-0x00000000bb599fff] ACPI NVS > [ 0.000000] BIOS-e820: [mem 0x00000000bb59a000-0x00000000bb5fefff] ACPI data > [ 0.000000] BIOS-e820: [mem 0x00000000bb5ff000-0x00000000bb5fffff] usable > [ 0.000000] BIOS-e820: [mem 0x00000000bb600000-0x00000000bf7fffff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved > [ 0.000000] BIOS-e820: [mem 0x00000000fe010000-0x00000000fe010fff] reserved > [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000043e7fffff] usable > [ 0.000000] NX (Execute Disable) protection: active > [ 0.000000] e820: update [mem 0x00050270-0x000502df] usable ==> usable > [ 0.000000] extended physical RAM map: > [ 0.000000] reserve setup_data: [mem 0x0000000000000000-0x000000000005026f] usable > [ 0.000000] reserve setup_data: [mem 0x0000000000050270-0x00000000000502df] usable > [ 0.000000] reserve setup_data: [mem 0x00000000000502e0-0x0000000000057fff] usable > [ 0.000000] reserve setup_data: [mem 0x0000000000058000-0x0000000000058fff] reserved > [ 0.000000] reserve setup_data: [mem 0x0000000000059000-0x000000000009cfff] usable > [ 0.000000] reserve setup_data: [mem 0x000000000009d000-0x00000000000fffff] reserved > [ 0.000000] reserve setup_data: [mem 0x0000000000100000-0x000000003fffffff] usable > [ 0.000000] reserve setup_data: [mem 0x0000000040000000-0x00000000403fffff] reserved > [ 0.000000] reserve setup_data: [mem 0x0000000040400000-0x000000007b4b2fff] usable > [ 0.000000] reserve setup_data: [mem 0x000000007b4b3000-0x000000007b4b4fff] reserved > [ 0.000000] reserve setup_data: [mem 0x000000007b4b5000-0x000000007b51cfff] usable > [ 0.000000] reserve setup_data: [mem 0x000000007b51d000-0x000000007b51dfff] reserved > [ 0.000000] reserve setup_data: [mem 0x000000007b51e000-0x00000000ad334fff] usable > [ 0.000000] reserve setup_data: [mem 0x00000000ad335000-0x00000000ad335fff] ACPI NVS > [ 0.000000] reserve setup_data: [mem 0x00000000ad336000-0x00000000ad336fff] reserved > [ 0.000000] reserve setup_data: [mem 0x00000000ad337000-0x00000000ba3e9fff] usable > [ 0.000000] reserve setup_data: [mem 0x00000000ba3ea000-0x00000000bb535fff] reserved > [ 0.000000] reserve setup_data: [mem 0x00000000bb536000-0x00000000bb599fff] ACPI NVS > [ 0.000000] reserve setup_data: [mem 0x00000000bb59a000-0x00000000bb5fefff] ACPI data > [ 0.000000] reserve setup_data: [mem 0x00000000bb5ff000-0x00000000bb5fffff] usable > [ 0.000000] reserve setup_data: [mem 0x00000000bb600000-0x00000000bf7fffff] reserved > [ 0.000000] reserve setup_data: [mem 0x00000000f8000000-0x00000000fbffffff] reserved > [ 0.000000] reserve setup_data: [mem 0x00000000fe010000-0x00000000fe010fff] reserved > [ 0.000000] reserve setup_data: [mem 0x0000000100000000-0x000000043e7fffff] usable > [ 0.000000] efi: EFI v2.50 by Lenovo > [ 0.000000] efi: SMBIOS=0xba674000 SMBIOS 3.0=0xba671000 ACPI=0xbb5fe000 ACPI 2.0=0xbb5fe014 ESRT=0xba4ec000 MEMATTR=0xb520e018 RNG=0xba675998 > [ 0.000000] efi: seeding entropy pool > [ 0.000000] SMBIOS 3.0.0 present. > [ 0.000000] DMI: LENOVO 20L8S3M801/20L8S3M801, BIOS N22ET54W (1.31 ) 04/22/2019 > [ 0.000000] tsc: Detected 2100.000 MHz processor > [ 0.001190] tsc: Detected 2099.944 MHz TSC > [ 0.001190] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved > [ 0.001192] e820: remove [mem 0x000a0000-0x000fffff] usable > [ 0.001196] last_pfn = 0x43e800 max_arch_pfn = 0x400000000 > [ 0.001197] x86/PAT: Configuration [0-7]: WB WT UC- UC WB WT UC- UC > [ 0.001197] last_pfn = 0xbb600 max_arch_pfn = 0x400000000 > [ 0.001202] esrt: Reserving ESRT space from 0x00000000ba4ec000 to 0x00000000ba4ec088. > [ 0.001204] kexec: Reserving the low 1M of memory for crashkernel > [ 0.001206] Using GB pages for direct mapping > [ 0.001704] Secure boot disabled > [ 0.001709] ACPI: Early table checksum verification disabled > [ 0.001711] ACPI: RSDP 0x00000000BB5FE014 000024 (v02 LENOVO) > [ 0.001713] ACPI: XSDT 0x00000000BB5AD188 00010C (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001716] ACPI: FACP 0x00000000BB5E3000 0000F4 (v05 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001719] ACPI: DSDT 0x00000000BB5BD000 021E4F (v02 LENOVO SKL 00000000 INTL 20160527) > [ 0.001721] ACPI: FACS 0x00000000BB546000 000040 > [ 0.001722] ACPI: SSDT 0x00000000BB5E9000 01320E (v02 LENOVO DptfTabl 00001000 INTL 20160527) > [ 0.001724] ACPI: UEFI 0x00000000BB55C000 000042 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001725] ACPI: SSDT 0x00000000BB5E5000 0030B0 (v02 LENOVO SaSsdt 00003000 INTL 20160527) > [ 0.001727] ACPI: SSDT 0x00000000BB5E4000 0005C6 (v02 LENOVO PerfTune 00001000 INTL 20160527) > [ 0.001728] ACPI: HPET 0x00000000BB5E2000 000038 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001730] ACPI: APIC 0x00000000BB5E1000 00012C (v03 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001731] ACPI: MCFG 0x00000000BB5E0000 00003C (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001733] ACPI: ECDT 0x00000000BB5DF000 000053 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001734] ACPI: SSDT 0x00000000BB5BB000 001C9C (v02 LENOVO RVP7Rtd3 00001000 INTL 20160527) > [ 0.001736] ACPI: SSDT 0x00000000BB5B9000 00163C (v02 LENOVO ProjSsdt 00000010 INTL 20160527) > [ 0.001738] ACPI: BOOT 0x00000000BB5B8000 000028 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001739] ACPI: BATB 0x00000000BB5B7000 00004A (v02 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001741] ACPI: SSDT 0x00000000BB5B5000 0017AE (v02 LENOVO CpuSsdt 00003000 INTL 20160527) > [ 0.001742] ACPI: SSDT 0x00000000BB5B4000 00056D (v02 LENOVO CtdpB 00001000 INTL 20160527) > [ 0.001744] ACPI: SSDT 0x00000000BB5B3000 000678 (v02 LENOVO UsbCTabl 00001000 INTL 20160527) > [ 0.001745] ACPI: LPIT 0x00000000BB5B2000 000094 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001747] ACPI: WSMT 0x00000000BB5B1000 000028 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001748] ACPI: SSDT 0x00000000BB5B0000 0001D8 (v02 LENOVO HdaDsp 00000000 INTL 20160527) > [ 0.001750] ACPI: SSDT 0x00000000BB5AF000 0004FC (v02 LENOVO TbtTypeC 00000000 INTL 20160527) > [ 0.001751] ACPI: SSDT 0x00000000BB5AE000 0002D1 (v02 LENOVO Wwan 00000001 INTL 20160527) > [ 0.001753] ACPI: DBGP 0x00000000BB5FD000 000034 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001754] ACPI: DBG2 0x00000000BB5AC000 000054 (v00 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001756] ACPI: POAT 0x00000000BB5AB000 000055 (v03 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001757] ACPI: DMAR 0x00000000BB5AA000 0000A8 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001759] ACPI: ASF! 0x00000000BB5A9000 0000A0 (v32 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001760] ACPI: FPDT 0x00000000BB5A8000 000044 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001762] ACPI: BGRT 0x00000000BB5A7000 000038 (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001763] ACPI: UEFI 0x00000000BB543000 00013E (v01 LENOVO TP-N22 00001310 PTEC 00000002) > [ 0.001768] ACPI: Local APIC address 0xfee00000 > [ 0.001775] No NUMA configuration found > [ 0.001775] Faking a node at [mem 0x0000000000000000-0x000000043e7fffff] > [ 0.001778] NODE_DATA(0) allocated [mem 0x43e7fa000-0x43e7fbfff] > [ 0.001781] Reserving 160MB of memory at 2608MB for crashkernel (System RAM: 16263MB) > [ 0.001791] Zone ranges: > [ 0.001792] DMA [mem 0x0000000000001000-0x0000000000ffffff] > [ 0.001793] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] > [ 0.001794] Normal [mem 0x0000000100000000-0x000000043e7fffff] > [ 0.001794] Movable zone start for each node > [ 0.001795] Early memory node ranges > [ 0.001795] node 0: [mem 0x0000000000001000-0x0000000000057fff] > [ 0.001796] node 0: [mem 0x0000000000059000-0x000000000009cfff] > [ 0.001797] node 0: [mem 0x0000000000100000-0x000000003fffffff] > [ 0.001797] node 0: [mem 0x0000000040400000-0x000000007b4b2fff] > [ 0.001798] node 0: [mem 0x000000007b4b5000-0x000000007b51cfff] > [ 0.001798] node 0: [mem 0x000000007b51e000-0x00000000ad334fff] > [ 0.001799] node 0: [mem 0x00000000ad337000-0x00000000ba3e9fff] > [ 0.001799] node 0: [mem 0x00000000bb5ff000-0x00000000bb5fffff] > [ 0.001800] node 0: [mem 0x0000000100000000-0x000000043e7fffff] > [ 0.001961] Zeroed struct page in unavailable ranges: 30847 pages > [ 0.001962] Initmem setup node 0 [mem 0x0000000000001000-0x000000043e7fffff] > [ 0.001964] On node 0 totalpages: 4163457 > [ 0.001965] DMA zone: 64 pages used for memmap > [ 0.001965] DMA zone: 155 pages reserved > [ 0.001966] DMA zone: 3995 pages, LIFO batch:0 > [ 0.001982] DMA32 zone: 11840 pages used for memmap > [ 0.001983] DMA32 zone: 757734 pages, LIFO batch:63 > [ 0.005402] Normal zone: 53152 pages used for memmap > [ 0.005402] Normal zone: 3401728 pages, LIFO batch:63 > [ 0.020786] Reserving Intel graphics memory at [mem 0xbd800000-0xbf7fffff] > [ 0.020959] ACPI: PM-Timer IO Port: 0x1808 > [ 0.020960] ACPI: Local APIC address 0xfee00000 > [ 0.020964] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) > [ 0.020965] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1]) > [ 0.020965] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1]) > [ 0.020966] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1]) > [ 0.020966] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1]) > [ 0.020966] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1]) > [ 0.020967] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1]) > [ 0.020967] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1]) > [ 0.020968] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1]) > [ 0.020968] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1]) > [ 0.020969] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1]) > [ 0.020969] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1]) > [ 0.020969] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1]) > [ 0.020970] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1]) > [ 0.020970] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1]) > [ 0.020971] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1]) > [ 0.020997] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119 > [ 0.020998] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) > [ 0.020999] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) > [ 0.021000] ACPI: IRQ0 used by override. > [ 0.021000] ACPI: IRQ9 used by override. > [ 0.021001] Using ACPI (MADT) for SMP configuration information > [ 0.021002] ACPI: HPET id: 0x8086a201 base: 0xfed00000 > [ 0.021005] e820: update [mem 0xb07d0000-0xb0860fff] usable ==> reserved > [ 0.021011] TSC deadline timer available > [ 0.021011] smpboot: Allowing 8 CPUs, 0 hotplug CPUs > [ 0.021023] [mem 0xbf800000-0xf7ffffff] available for PCI devices > [ 0.021023] Booting paravirtualized kernel on bare hardware > [ 0.021025] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns > [ 0.023365] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:8 nr_node_ids:1 > [ 0.023470] percpu: Embedded 50 pages/cpu s167936 r8192 d28672 u262144 > [ 0.023473] pcpu-alloc: s167936 r8192 d28672 u262144 alloc=1*2097152 > [ 0.023474] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 > [ 0.023484] Built 1 zonelists, mobility grouping on. Total pages: 4098246 > [ 0.023485] Policy zone: Normal > [ 0.023486] Kernel command line: ramoops.mem_address=0x20000000 ramoops.mem_size=0x400000 hung_task_panic=1 softlockup_panic=1 panic=6 root=/dev/nvme0n1p9 ro rd.lvm.lv=rhel/swap LANG=zh_CN.UTF-8 audit=0 selinux=0 no_console_suspend crashkernel=160M printk.devkmsg=off usbcore.autosuspend=-1 > [ 0.023516] audit: disabled (until reboot) > [ 0.024068] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear) > [ 0.024322] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear) > [ 0.024365] mem auto-init: stack:off, heap alloc:off, heap free:off > [ 0.049642] Memory: 16109860K/16653828K available (10243K kernel code, 1030K rwdata, 2484K rodata, 1224K init, 2960K bss, 543968K reserved, 0K cma-reserved) > [ 0.049673] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 > [ 0.049679] Kernel/User page tables isolation: enabled > [ 0.049688] ftrace: allocating 29741 entries in 117 pages > [ 0.057842] ftrace: allocated 117 pages with 5 groups > [ 0.057893] rcu: Hierarchical RCU implementation. > [ 0.057894] Rude variant of Tasks RCU enabled. > [ 0.057895] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies. > [ 0.057971] NR_IRQS: 4352, nr_irqs: 2048, preallocated irqs: 16 > [ 0.058112] rcu: Offload RCU callbacks from CPUs: (none). > [ 0.058245] random: get_random_bytes called from start_kernel+0x5b1/0x772 with crng_init=0 > [ 0.058260] Console: colour dummy device 80x25 > [ 0.058409] printk: console [tty0] enabled > [ 0.058418] ACPI: Core revision 20200528 > [ 0.058701] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns > [ 0.058769] APIC: Switch to symmetric I/O mode setup > [ 0.060036] x2apic: IRQ remapping doesn't support X2APIC mode > [ 0.064358] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 > [ 0.068800] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x1e44fb6c2ab, max_idle_ns: 440795206594 ns > [ 0.068803] Calibrating delay loop (skipped), value calculated using timer frequency.. 4199.88 BogoMIPS (lpj=2099944) > [ 0.068806] pid_max: default: 32768 minimum: 301 > [ 0.068842] LSM: Security Framework initializing > [ 0.068874] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear) > [ 0.068900] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear) > [ 0.069032] mce: CPU0: Thermal monitoring enabled (TM1) > [ 0.069046] process: using mwait in idle threads > [ 0.069048] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8 > [ 0.069050] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4 > [ 0.069051] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization > [ 0.069053] Spectre V2 : Mitigation: Full generic retpoline > [ 0.069054] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch > [ 0.069055] Spectre V2 : Enabling Restricted Speculation for firmware calls > [ 0.069057] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier > [ 0.069058] Spectre V2 : User space: Mitigation: STIBP via seccomp and prctl > [ 0.069060] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp > [ 0.069062] TAA: Mitigation: Clear CPU buffers > [ 0.069063] SRBDS: Vulnerable: No microcode > [ 0.069063] MDS: Mitigation: Clear CPU buffers > [ 0.069180] Freeing SMP alternatives memory: 28K > [ 0.069223] smpboot: CPU0: Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz (family: 0x6, model: 0x8e, stepping: 0xa) > [ 0.069278] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver. > [ 0.069284] ... version: 4 > [ 0.069285] ... bit width: 48 > [ 0.069286] ... generic registers: 4 > [ 0.069287] ... value mask: 0000ffffffffffff > [ 0.069288] ... max period: 00007fffffffffff > [ 0.069289] ... fixed-purpose events: 3 > [ 0.069290] ... event mask: 000000070000000f > [ 0.069314] rcu: Hierarchical SRCU implementation. > [ 0.069803] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter. > [ 0.069803] smp: Bringing up secondary CPUs ... > [ 0.069803] x86: Booting SMP configuration: > [ 0.069803] .... node #0, CPUs: #1 #2 #3 #4 > [ 0.071250] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details. > [ 0.071250] TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details. > [ 0.071250] #5 #6 #7 > [ 0.072162] smp: Brought up 1 node, 8 CPUs > [ 0.072162] smpboot: Max logical packages: 1 > [ 0.072162] smpboot: Total of 8 processors activated (33599.10 BogoMIPS) > [ 0.072162] devtmpfs: initialized > [ 0.072818] PM: Registering ACPI NVS region [mem 0xad335000-0xad335fff] (4096 bytes) > [ 0.072820] PM: Registering ACPI NVS region [mem 0xbb536000-0xbb599fff] (409600 bytes) > [ 0.072851] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns > [ 0.072851] futex hash table entries: 2048 (order: 5, 131072 bytes, linear) > [ 0.072862] thermal_sys: Registered thermal governor 'fair_share' > [ 0.072889] NET: Registered protocol family 16 > [ 0.072941] DMA: preallocated 4096 KiB GFP_KERNEL pool for atomic allocations > [ 0.072946] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations > [ 0.072952] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations > [ 0.072959] ramoops: using module parameters > [ 0.074125] printk: console [ramoops-1] enabled > [ 0.074135] pstore: Registered ramoops as persistent store backend > [ 0.074135] ramoops: using 0x400000 at 0x20000000, ecc: 0 > [ 0.074135] cpuidle: using governor ladder > [ 0.074135] Simple Boot Flag at 0x47 set to 0x1 > [ 0.074135] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it > [ 0.074135] ACPI: bus type PCI registered > [ 0.074135] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf8000000-0xfbffffff] (base 0xf8000000) > [ 0.074135] PCI: MMCONFIG at [mem 0xf8000000-0xfbffffff] reserved in E820 > [ 0.074135] PCI: Using configuration type 1 for base access > [ 0.234910] ACPI: Added _OSI(Module Device) > [ 0.234910] ACPI: Added _OSI(Processor Device) > [ 0.234910] ACPI: Added _OSI(3.0 _SCP Extensions) > [ 0.234910] ACPI: Added _OSI(Processor Aggregator Device) > [ 0.234910] ACPI: Added _OSI(Linux-Dell-Video) > [ 0.234910] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) > [ 0.234910] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics) > [ 0.258697] ACPI: 12 ACPI AML tables successfully acquired and loaded > [ 0.259375] ACPI: EC: EC started > [ 0.259376] ACPI: EC: interrupt blocked > [ 0.260428] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62 > [ 0.260430] ACPI: EC: Boot ECDT EC used to handle transactions > [ 0.261354] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored > [ 0.266910] ACPI: Dynamic OEM Table Load: > [ 0.266921] ACPI: SSDT 0xFFFF88842C3CD000 0005EE (v02 PmRef Cpu0Ist 00003000 INTL 20160527) > [ 0.267682] ACPI: \_PR_.PR00: _OSC native thermal LVT Acked > [ 0.268203] ACPI: Dynamic OEM Table Load: > [ 0.268210] ACPI: SSDT 0xFFFF88842BA58400 0003FF (v02 PmRef Cpu0Cst 00003001 INTL 20160527) > [ 0.268959] ACPI: Dynamic OEM Table Load: > [ 0.268965] ACPI: SSDT 0xFFFF88842BA41480 0000BA (v02 PmRef Cpu0Hwp 00003000 INTL 20160527) > [ 0.269663] ACPI: Dynamic OEM Table Load: > [ 0.269668] ACPI: SSDT 0xFFFF88842C3CD800 000628 (v02 PmRef HwpLvt 00003000 INTL 20160527) > [ 0.270545] ACPI: Dynamic OEM Table Load: > [ 0.270552] ACPI: SSDT 0xFFFF88842BAB0000 000D14 (v02 PmRef ApIst 00003000 INTL 20160527) > [ 0.271593] ACPI: Dynamic OEM Table Load: > [ 0.271599] ACPI: SSDT 0xFFFF88842BA58800 000317 (v02 PmRef ApHwp 00003000 INTL 20160527) > [ 0.272361] ACPI: Dynamic OEM Table Load: > [ 0.272366] ACPI: SSDT 0xFFFF88842BA58C00 00030A (v02 PmRef ApCst 00003000 INTL 20160527) > [ 0.274300] ACPI: Interpreter enabled > [ 0.274322] ACPI: (supports S0 S3 S5) > [ 0.274324] ACPI: Using IOAPIC for interrupt routing > [ 0.274344] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug > [ 0.274666] ACPI: Enabled 8 GPEs in block 00 to 7F > [ 0.276464] ACPI: Power Resource [PUBS] (on) > [ 0.308825] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-3e]) > [ 0.308832] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig Segments MSI HPX-Type3] > [ 0.308888] acpi PNP0A08:00: _OSC: not requesting OS control; OS requires [ExtendedConfig ASPM ClockPM MSI] > [ 0.309086] PCI host bridge to bus 0000:00 > [ 0.309090] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] > [ 0.309094] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] > [ 0.309097] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window] > [ 0.309101] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window] > [ 0.309104] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window] > [ 0.309108] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window] > [ 0.309111] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window] > [ 0.309115] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window] > [ 0.309118] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window] > [ 0.309121] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window] > [ 0.309125] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window] > [ 0.309128] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window] > [ 0.309132] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window] > [ 0.309135] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window] > [ 0.309139] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window] > [ 0.309142] pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff window] > [ 0.309146] pci_bus 0000:00: root bus resource [mem 0xbf800000-0xf7ffffff window] > [ 0.309149] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window] > [ 0.309153] pci_bus 0000:00: root bus resource [bus 00-3e] > [ 0.309164] pci 0000:00:00.0: [8086:5914] type 00 class 0x060000 > [ 0.309758] pci 0000:00:02.0: [8086:5917] type 00 class 0x030000 > [ 0.309773] pci 0000:00:02.0: reg 0x10: [mem 0xe0000000-0xe0ffffff 64bit] > [ 0.309781] pci 0000:00:02.0: reg 0x18: [mem 0xc0000000-0xdfffffff 64bit pref] > [ 0.309788] pci 0000:00:02.0: reg 0x20: [io 0xe000-0xe03f] > [ 0.309806] pci 0000:00:02.0: BAR 2: assigned to efifb > [ 0.310405] pci 0000:00:04.0: [8086:1903] type 00 class 0x118000 > [ 0.310421] pci 0000:00:04.0: reg 0x10: [mem 0xe1240000-0xe1247fff 64bit] > [ 0.311080] pci 0000:00:08.0: [8086:1911] type 00 class 0x088000 > [ 0.311097] pci 0000:00:08.0: reg 0x10: [mem 0xe1250000-0xe1250fff 64bit] > [ 0.311720] pci 0000:00:14.0: [8086:9d2f] type 00 class 0x0c0330 > [ 0.311745] pci 0000:00:14.0: reg 0x10: [mem 0xe1220000-0xe122ffff 64bit] > [ 0.311814] pci 0000:00:14.0: PME# supported from D3hot D3cold > [ 0.312481] pci 0000:00:14.2: [8086:9d31] type 00 class 0x118000 > [ 0.312505] pci 0000:00:14.2: reg 0x10: [mem 0xe1251000-0xe1251fff 64bit] > [ 0.313229] pci 0000:00:15.0: [8086:9d60] type 00 class 0x118000 > [ 0.313495] pci 0000:00:15.0: reg 0x10: [mem 0xe1252000-0xe1252fff 64bit] > [ 0.314891] pci 0000:00:16.0: [8086:9d3a] type 00 class 0x078000 > [ 0.314919] pci 0000:00:16.0: reg 0x10: [mem 0xe1253000-0xe1253fff 64bit] > [ 0.314992] pci 0000:00:16.0: PME# supported from D3hot > [ 0.315564] pci 0000:00:1c.0: [8086:9d10] type 01 class 0x060400 > [ 0.315636] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold > [ 0.316190] pci 0000:00:1c.4: [8086:9d14] type 01 class 0x060400 > [ 0.316261] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold > [ 0.316810] pci 0000:00:1c.6: [8086:9d16] type 01 class 0x060400 > [ 0.316890] pci 0000:00:1c.6: PME# supported from D0 D3hot D3cold > [ 0.317435] pci 0000:00:1d.0: [8086:9d18] type 01 class 0x060400 > [ 0.317507] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold > [ 0.318082] pci 0000:00:1f.0: [8086:9d4e] type 00 class 0x060100 > [ 0.318722] pci 0000:00:1f.2: [8086:9d21] type 00 class 0x058000 > [ 0.318738] pci 0000:00:1f.2: reg 0x10: [mem 0xe124c000-0xe124ffff] > [ 0.319260] pci 0000:00:1f.3: [8086:9d71] type 00 class 0x040300 > [ 0.319290] pci 0000:00:1f.3: reg 0x10: [mem 0xe1248000-0xe124bfff 64bit] > [ 0.319322] pci 0000:00:1f.3: reg 0x20: [mem 0xe1230000-0xe123ffff 64bit] > [ 0.319370] pci 0000:00:1f.3: PME# supported from D3hot D3cold > [ 0.319871] pci 0000:00:1f.4: [8086:9d23] type 00 class 0x0c0500 > [ 0.319934] pci 0000:00:1f.4: reg 0x10: [mem 0xe1254000-0xe12540ff 64bit] > [ 0.320007] pci 0000:00:1f.4: reg 0x20: [io 0xefa0-0xefbf] > [ 0.320552] pci 0000:00:1f.6: [8086:15d7] type 00 class 0x020000 > [ 0.320576] pci 0000:00:1f.6: reg 0x10: [mem 0xe1200000-0xe121ffff] > [ 0.320664] pci 0000:00:1f.6: PME# supported from D0 D3hot D3cold > [ 0.321165] pci 0000:00:1c.0: PCI bridge to [bus 01] > [ 0.321169] pci 0000:00:1c.0: bridge window [io 0x2000-0x2fff] > [ 0.321173] pci 0000:00:1c.0: bridge window [mem 0xbf800000-0xbf9fffff] > [ 0.321179] pci 0000:00:1c.0: bridge window [mem 0xbfa00000-0xbfbfffff 64bit pref] > [ 0.321216] pci 0000:00:1c.4: PCI bridge to [bus 04-3c] > [ 0.321583] pci 0000:3d:00.0: [8086:24fd] type 00 class 0x028000 > [ 0.321686] pci 0000:3d:00.0: reg 0x10: [mem 0xe1100000-0xe1101fff 64bit] > [ 0.322020] pci 0000:3d:00.0: PME# supported from D0 D3hot D3cold > [ 0.322179] pci 0000:00:1c.6: PCI bridge to [bus 3d] > [ 0.322186] pci 0000:00:1c.6: bridge window [mem 0xe1100000-0xe11fffff] > [ 0.322224] pci 0000:3e:00.0: [144d:a808] type 00 class 0x010802 > [ 0.322254] pci 0000:3e:00.0: reg 0x10: [mem 0xe1000000-0xe1003fff 64bit] > [ 0.322401] pci 0000:00:1d.0: PCI bridge to [bus 3e] > [ 0.322406] pci 0000:00:1d.0: bridge window [mem 0xe1000000-0xe10fffff] > [ 0.323696] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. > [ 0.323735] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15), disabled. > [ 0.323770] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. > [ 0.323807] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. > [ 0.323856] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. > [ 0.323889] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. > [ 0.323922] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. > [ 0.323956] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15), disabled. > [ 0.324178] ACPI: EC: interrupt unblocked > [ 0.324180] ACPI: EC: event unblocked > [ 0.324193] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62 > [ 0.324195] ACPI: EC: GPE=0x16 > [ 0.324197] ACPI: \_SB_.PCI0.LPCB.EC__: Boot ECDT EC initialization complete > [ 0.324200] ACPI: \_SB_.PCI0.LPCB.EC__: EC: Used to handle transactions and events > [ 0.324240] pci 0000:00:02.0: vgaarb: setting as boot VGA device > [ 0.324240] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none > [ 0.324240] pci 0000:00:02.0: vgaarb: bridge control possible > [ 0.324240] vgaarb: loaded > [ 0.324240] SCSI subsystem initialized > [ 0.324240] libata version 3.00 loaded. > [ 0.324240] ACPI: bus type USB registered > [ 0.324240] usbcore: registered new interface driver usbfs > [ 0.324240] usbcore: registered new interface driver hub > [ 0.324240] usbcore: registered new device driver usb > [ 0.324240] videodev: Linux video capture interface: v2.00 > [ 0.324240] Registered efivars operations > [ 0.324240] PCI: Using ACPI for IRQ routing > [ 0.326401] PCI: pci_cache_line_size set to 64 bytes > [ 0.326815] e820: reserve RAM buffer [mem 0x00050270-0x0005ffff] > [ 0.326816] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff] > [ 0.326816] e820: reserve RAM buffer [mem 0x0009d000-0x0009ffff] > [ 0.326817] e820: reserve RAM buffer [mem 0x7b4b3000-0x7bffffff] > [ 0.326817] e820: reserve RAM buffer [mem 0x7b51d000-0x7bffffff] > [ 0.326818] e820: reserve RAM buffer [mem 0xad335000-0xafffffff] > [ 0.326818] e820: reserve RAM buffer [mem 0xb07d0000-0xb3ffffff] > [ 0.326819] e820: reserve RAM buffer [mem 0xba3ea000-0xbbffffff] > [ 0.326819] e820: reserve RAM buffer [mem 0xbb600000-0xbbffffff] > [ 0.326820] e820: reserve RAM buffer [mem 0x43e800000-0x43fffffff] > [ 0.326837] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 > [ 0.326840] hpet0: 8 comparators, 64-bit 24.000000 MHz counter > [ 0.328813] clocksource: Switched to clocksource tsc-early > [ 0.333518] pnp: PnP ACPI init > [ 0.333555] system 00:00: [mem 0x40000000-0x403fffff] has been reserved > [ 0.333560] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.333617] system 00:01: [mem 0xfd000000-0xfdabffff] has been reserved > [ 0.333620] system 00:01: [mem 0xfdad0000-0xfdadffff] has been reserved > [ 0.333623] system 00:01: [mem 0xfdb00000-0xfdffffff] has been reserved > [ 0.333625] system 00:01: [mem 0xfe000000-0xfe01ffff] could not be reserved > [ 0.333627] system 00:01: [mem 0xfe036000-0xfe03bfff] has been reserved > [ 0.333630] system 00:01: [mem 0xfe03d000-0xfe3fffff] has been reserved > [ 0.333632] system 00:01: [mem 0xfe410000-0xfe7fffff] has been reserved > [ 0.333636] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.333779] system 00:02: [io 0xff00-0xfffe] has been reserved > [ 0.333783] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.334085] system 00:03: [io 0x0680-0x069f] has been reserved > [ 0.334087] system 00:03: [io 0xffff] has been reserved > [ 0.334090] system 00:03: [io 0xffff] has been reserved > [ 0.334092] system 00:03: [io 0xffff] has been reserved > [ 0.334094] system 00:03: [io 0x1800-0x18fe] has been reserved > [ 0.334096] system 00:03: [io 0x164e-0x164f] has been reserved > [ 0.334099] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.334145] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active) > [ 0.334164] system 00:05: [io 0x1854-0x1857] has been reserved > [ 0.334168] system 00:05: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active) > [ 0.334176] pnp 00:06: Plug and Play ACPI device, IDs LEN0071 PNP0303 (active) > [ 0.334184] pnp 00:07: Plug and Play ACPI device, IDs LEN008f PNP0f13 (active) > [ 0.334231] system 00:08: [io 0x1800-0x189f] could not be reserved > [ 0.334234] system 00:08: [io 0x0800-0x087f] has been reserved > [ 0.334236] system 00:08: [io 0x0880-0x08ff] has been reserved > [ 0.334238] system 00:08: [io 0x0900-0x097f] has been reserved > [ 0.334241] system 00:08: [io 0x0980-0x09ff] has been reserved > [ 0.334243] system 00:08: [io 0x0a00-0x0a7f] has been reserved > [ 0.334245] system 00:08: [io 0x0a80-0x0aff] has been reserved > [ 0.334247] system 00:08: [io 0x0b00-0x0b7f] has been reserved > [ 0.334249] system 00:08: [io 0x0b80-0x0bff] has been reserved > [ 0.334251] system 00:08: [io 0x15e0-0x15ef] has been reserved > [ 0.334254] system 00:08: [io 0x1600-0x167f] could not be reserved > [ 0.334256] system 00:08: [io 0x1640-0x165f] could not be reserved > [ 0.334258] system 00:08: [mem 0xf8000000-0xfbffffff] has been reserved > [ 0.334261] system 00:08: [mem 0xfed10000-0xfed13fff] has been reserved > [ 0.334263] system 00:08: [mem 0xfed18000-0xfed18fff] has been reserved > [ 0.334265] system 00:08: [mem 0xfed19000-0xfed19fff] has been reserved > [ 0.334268] system 00:08: [mem 0xfeb00000-0xfebfffff] has been reserved > [ 0.334270] system 00:08: [mem 0xfed20000-0xfed3ffff] has been reserved > [ 0.334272] system 00:08: [mem 0xfed90000-0xfed93fff] has been reserved > [ 0.334275] system 00:08: [mem 0xf7fe0000-0xf7ffffff] has been reserved > [ 0.334278] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.334873] system 00:09: [mem 0xfdaf0000-0xfdafffff] has been reserved > [ 0.334876] system 00:09: [mem 0xfdae0000-0xfdaeffff] has been reserved > [ 0.334878] system 00:09: [mem 0xfdac0000-0xfdacffff] has been reserved > [ 0.334882] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.335298] system 00:0a: [mem 0xfed10000-0xfed17fff] could not be reserved > [ 0.335301] system 00:0a: [mem 0xfed18000-0xfed18fff] has been reserved > [ 0.335303] system 00:0a: [mem 0xfed19000-0xfed19fff] has been reserved > [ 0.335305] system 00:0a: [mem 0xf8000000-0xfbffffff] has been reserved > [ 0.335308] system 00:0a: [mem 0xfed20000-0xfed3ffff] has been reserved > [ 0.335310] system 00:0a: [mem 0xfed90000-0xfed93fff] has been reserved > [ 0.335312] system 00:0a: [mem 0xfed45000-0xfed8ffff] has been reserved > [ 0.335315] system 00:0a: [mem 0xff000000-0xffffffff] has been reserved > [ 0.335317] system 00:0a: [mem 0xfee00000-0xfeefffff] has been reserved > [ 0.335319] system 00:0a: [mem 0xf7fe0000-0xf7ffffff] has been reserved > [ 0.335323] system 00:0a: Plug and Play ACPI device, IDs PNP0c02 (active) > [ 0.335462] system 00:0b: [mem 0x00000000-0x0009ffff] could not be reserved > [ 0.335465] system 00:0b: [mem 0x000f0000-0x000fffff] could not be reserved > [ 0.335467] system 00:0b: [mem 0x00100000-0xbf7fffff] could not be reserved > [ 0.335470] system 00:0b: [mem 0xfec00000-0xfed3ffff] could not be reserved > [ 0.335472] system 00:0b: [mem 0xfed4c000-0xffffffff] could not be reserved > [ 0.335476] system 00:0b: Plug and Play ACPI device, IDs PNP0c01 (active) > [ 0.335521] pnp: PnP ACPI: found 12 devices > [ 0.340600] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns > [ 0.340618] NET: Registered protocol family 2 > [ 0.340679] tcp_listen_portaddr_hash hash table entries: 8192 (order: 5, 131072 bytes, linear) > [ 0.340696] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear) > [ 0.340808] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear) > [ 0.340925] TCP: Hash tables configured (established 131072 bind 65536) > [ 0.340945] UDP hash table entries: 8192 (order: 6, 262144 bytes, linear) > [ 0.340974] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes, linear) > [ 0.341024] NET: Registered protocol family 1 > [ 0.341032] pci 0000:00:1c.0: PCI bridge to [bus 01] > [ 0.341037] pci 0000:00:1c.0: bridge window [io 0x2000-0x2fff] > [ 0.341041] pci 0000:00:1c.0: bridge window [mem 0xbf800000-0xbf9fffff] > [ 0.341045] pci 0000:00:1c.0: bridge window [mem 0xbfa00000-0xbfbfffff 64bit pref] > [ 0.341050] pci 0000:00:1c.4: PCI bridge to [bus 04-3c] > [ 0.341060] pci 0000:00:1c.6: PCI bridge to [bus 3d] > [ 0.341065] pci 0000:00:1c.6: bridge window [mem 0xe1100000-0xe11fffff] > [ 0.341071] pci 0000:00:1d.0: PCI bridge to [bus 3e] > [ 0.341075] pci 0000:00:1d.0: bridge window [mem 0xe1000000-0xe10fffff] > [ 0.341081] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] > [ 0.341084] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] > [ 0.341086] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window] > [ 0.341088] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window] > [ 0.341091] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window] > [ 0.341093] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window] > [ 0.341095] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window] > [ 0.341097] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window] > [ 0.341100] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window] > [ 0.341102] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window] > [ 0.341104] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window] > [ 0.341106] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window] > [ 0.341109] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window] > [ 0.341111] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window] > [ 0.341113] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window] > [ 0.341115] pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff window] > [ 0.341118] pci_bus 0000:00: resource 20 [mem 0xbf800000-0xf7ffffff window] > [ 0.341120] pci_bus 0000:00: resource 21 [mem 0xfd000000-0xfe7fffff window] > [ 0.341122] pci_bus 0000:01: resource 0 [io 0x2000-0x2fff] > [ 0.341124] pci_bus 0000:01: resource 1 [mem 0xbf800000-0xbf9fffff] > [ 0.341127] pci_bus 0000:01: resource 2 [mem 0xbfa00000-0xbfbfffff 64bit pref] > [ 0.341129] pci_bus 0000:3d: resource 1 [mem 0xe1100000-0xe11fffff] > [ 0.341132] pci_bus 0000:3e: resource 1 [mem 0xe1000000-0xe10fffff] > [ 0.341195] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] > [ 0.341673] PCI: CLS 0 bytes, default 64 > [ 0.341691] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) > [ 0.341694] software IO TLB: mapped [mem 0xb63ea000-0xba3ea000] (64MB) > [ 0.341729] resource sanity check: requesting [mem 0xfed10000-0xfed15fff], which spans more than pnp 00:08 [mem 0xfed10000-0xfed13fff] > [ 0.341734] caller snb_uncore_imc_init_box+0x6c/0xb0 mapping multiple BARs > [ 0.342043] simple-framebuffer simple-framebuffer.0: framebuffer at 0xc0000000, 0x7e9000 bytes, mapped to 0x000000004ff2874b > [ 0.342047] simple-framebuffer simple-framebuffer.0: format=a8r8g8b8, mode=1920x1080x32, linelength=7680 > [ 0.475073] Console: switching to colour frame buffer device 240x67 > [ 0.608186] simple-framebuffer simple-framebuffer.0: fb0: simplefb registered! > [ 0.608391] Initialise system trusted keyrings > [ 0.609324] workingset: timestamp_bits=60 max_order=22 bucket_order=0 > [ 0.610567] 9p: Installing v9fs 9p2000 file system support > [ 0.616822] Key type asymmetric registered > [ 0.617209] Asymmetric key parser 'x509' registered > [ 0.617668] Key type pkcs7_test registered > [ 0.618058] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249) > [ 0.618772] io scheduler bfq registered > [ 0.619875] ACPI: AC Adapter [AC] (on-line) > [ 0.620314] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input0 > [ 0.621116] ACPI: Sleep Button [SLPB] > [ 0.621475] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input1 > [ 0.622255] ACPI: Lid Switch [LID] > [ 0.622588] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 > [ 0.623294] ACPI: Power Button [PWRF] > [ 0.623815] Monitor-Mwait will be used to enter C-1 state > [ 0.623818] Monitor-Mwait will be used to enter C-2 state > [ 0.623821] Monitor-Mwait will be used to enter C-3 state > [ 0.623823] ACPI: \_PR_.PR00: Found 3 idle states > [ 0.624412] ACPI: \_PR_.PR01: Found 3 idle states > [ 0.624979] ACPI: \_PR_.PR02: Found 3 idle states > [ 0.625545] ACPI: \_PR_.PR03: Found 3 idle states > [ 0.626114] ACPI: \_PR_.PR04: Found 3 idle states > [ 0.626693] ACPI: \_PR_.PR05: Found 3 idle states > [ 0.627275] ACPI: \_PR_.PR06: Found 3 idle states > [ 0.627857] ACPI: \_PR_.PR07: Found 3 idle states > [ 0.631002] thermal LNXTHERM:00: registered as thermal_zone0 > [ 0.631535] ACPI: Thermal Zone [THM0] (46 C) > [ 0.632018] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled > [ 0.632947] Non-volatile memory driver v1.3 > [ 0.633970] brd: module loaded > [ 0.634784] nvme nvme0: pci function 0000:3e:00.0 > [ 0.635268] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver > [ 0.635895] ehci-pci: EHCI PCI platform driver > [ 0.636403] xhci_hcd 0000:00:14.0: xHCI Host Controller > [ 0.636903] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1 > [ 0.638679] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x0000000081109810 > [ 0.639627] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported > [ 0.640462] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.08 > [ 0.641262] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 > [ 0.641965] usb usb1: Product: xHCI Host Controller > [ 0.642417] usb usb1: Manufacturer: Linux 5.8.0-rc1+ xhci-hcd > [ 0.642985] usb usb1: SerialNumber: 0000:00:14.0 > [ 0.643553] hub 1-0:1.0: USB hub found > [ 0.644738] nvme nvme0: Shutdown timeout set to 8 seconds > [ 0.659136] battery: ACPI: Battery Slot [BAT0] (battery present) > [ 0.670685] hub 1-0:1.0: 12 ports detected > [ 0.706146] nvme nvme0: 8/0/0 default/read/poll queues > [ 0.726320] xhci_hcd 0000:00:14.0: xHCI Host Controller > [ 0.760397] nvme0n1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 > [ 0.782379] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2 > [ 0.869762] xhci_hcd 0000:00:14.0: Host supports USB 3.0 SuperSpeed > [ 0.899414] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.08 > [ 0.929333] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 > [ 0.959125] usb usb2: Product: xHCI Host Controller > [ 0.989123] usb usb2: Manufacturer: Linux 5.8.0-rc1+ xhci-hcd > [ 1.019029] usb usb2: SerialNumber: 0000:00:14.0 > [ 1.048692] hub 2-0:1.0: USB hub found > [ 1.078218] hub 2-0:1.0: 6 ports detected > [ 1.107665] usb: port power management may be unreliable > [ 1.137123] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 > [ 1.168929] serio: i8042 KBD port at 0x60,0x64 irq 1 > [ 1.198243] serio: i8042 AUX port at 0x60,0x64 irq 12 > [ 1.218815] usb 1-2: new high-speed USB device number 2 using xhci_hcd > [ 1.226895] mousedev: PS/2 mouse device common for all mice > [ 1.283539] rtc_cmos 00:04: RTC can wake from S4 > [ 1.311857] rtc_cmos 00:04: registered as rtc0 > [ 1.338713] rtc_cmos 00:04: setting system clock to 2020-06-17T06:16:02 UTC (1592374562) > [ 1.365651] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs > [ 1.372857] tsc: Refined TSC clocksource calibration: 2111.991 MHz > [ 1.392532] usb 1-2: New USB device found, idVendor=0bda, idProduct=5411, bcdDevice= 1.04 > [ 1.392533] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 > [ 1.392534] usb 1-2: Product: 4-Port USB 2.0 Hub > [ 1.392535] usb 1-2: Manufacturer: Generic > [ 1.392924] device-mapper: uevent: version 1.0.3 > [ 1.393324] hub 1-2:1.0: USB hub found > [ 1.393916] hub 1-2:1.0: 4 ports detected > [ 1.420841] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x1e716fff2bd, max_idle_ns: 440795203249 ns > [ 1.638917] clocksource: Switched to clocksource tsc > [ 1.638944] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 > [ 1.639001] device-mapper: ioctl: 4.42.0-ioctl (2020-02-27) initialised: dm-devel at redhat.com > [ 1.639003] intel_pstate: Intel P-state driver initializing > [ 1.693085] usb 2-2: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd > [ 1.779384] intel_pstate: HWP enabled > [ 1.797519] random: fast init done > [ 1.801443] usb 2-2: New USB device found, idVendor=0bda, idProduct=0411, bcdDevice= 1.04 > [ 1.801444] usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 > [ 1.801445] usb 2-2: Product: 4-Port USB 3.0 Hub > [ 1.801445] usb 2-2: Manufacturer: Generic > [ 1.806226] hub 2-2:1.0: USB hub found > [ 1.806378] EFI Variables Facility v0.08 2004-May-17 > [ 1.807181] hub 2-2:1.0: 4 ports detected > [ 1.909848] usb 1-7: new full-speed USB device number 3 using xhci_hcd > [ 1.949253] usbcore: registered new interface driver usbhid > [ 2.012594] input: PS/2 Generic Mouse as /devices/platform/i8042/serio1/input/input5 > [ 2.026540] usbhid: USB HID core driver > [ 2.097189] usb 1-7: New USB device found, idVendor=8087, idProduct=0a2b, bcdDevice= 0.10 > [ 2.113071] Initializing XFRM netlink socket > [ 2.142150] usb 1-7: New USB device strings: Mfr=0, Product=0, SerialNumber=0 > [ 2.193860] usb 1-2.1: new low-speed USB device number 4 using xhci_hcd > [ 2.200942] NET: Registered protocol family 17 > [ 2.321413] NET: Registered protocol family 15 > [ 2.324535] usb 1-2.1: New USB device found, idVendor=413c, idProduct=301a, bcdDevice= 1.00 > [ 2.351264] Bridge firewalling registered > [ 2.381722] usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0 > [ 2.381723] usb 1-2.1: Product: Dell MS116 USB Optical Mouse > [ 2.411714] 9pnet: Installing 9P2000 support > [ 2.433980] usb 2-3: new SuperSpeed Gen 1 USB device number 3 using xhci_hcd > [ 2.442082] usb 1-2.1: Manufacturer: PixArt > [ 2.457036] usb 2-3: New USB device found, idVendor=0bda, idProduct=0316, bcdDevice= 2.04 > [ 2.457037] usb 2-3: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 2.457037] usb 2-3: Product: USB3.0-CRW > [ 2.457038] usb 2-3: Manufacturer: Generic > [ 2.457038] usb 2-3: SerialNumber: 20120501030900000 > [ 2.713976] microcode: sig=0x806ea, pf=0x80, revision=0xb4 > [ 2.718305] input: PixArt Dell MS116 USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.1/1-2.1:1.0/0003:413C:301A.0001/input/input6 > [ 2.777500] hid-generic 0003:413C:301A.0001: input: USB HID v1.11 Mouse [PixArt Dell MS116 USB Optical Mouse] on usb-0000:00:14.0-2.1/input0 > [ 2.777608] microcode: Microcode Update Driver: v2.2. > [ 2.777628] IPI shorthand broadcast: enabled > [ 2.873283] sched_clock: Marking stable (2869680977, 3595871)->(2874053724, -776876) > [ 2.885847] usb 1-2.2: new low-speed USB device number 5 using xhci_hcd > [ 2.905201] registered taskstats version 1 > [ 2.969261] Loading compiled-in X.509 certificates > [ 3.022476] Loaded X.509 cert 'dyoung kernel test key: 9d5c9a70fe6578e1ba171ba2ab9f3449d6688559' > [ 3.034053] usb 1-2.2: New USB device found, idVendor=413c, idProduct=2113, bcdDevice= 1.10 > [ 3.057031] Loaded X.509 cert 'dyoung kernel test key: 9d5c9a70fe6578e1ba171ba2ab9f3449d6688559' > [ 3.090359] usb 1-2.2: New USB device strings: Mfr=0, Product=2, SerialNumber=0 > [ 3.124441] pstore: Using crash dump compression: lzo > [ 3.158473] usb 1-2.2: Product: Dell KB216 Wired Keyboard > [ 3.192879] Key type encrypted registered > [ 3.236217] input: Dell KB216 Wired Keyboard as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.2/1-2.2:1.0/0003:413C:2113.0002/input/input7 > [ 3.348685] hid-generic 0003:413C:2113.0002: input: USB HID v1.11 Keyboard [Dell KB216 Wired Keyboard] on usb-0000:00:14.0-2.2/input0 > [ 3.396179] input: Dell KB216 Wired Keyboard Consumer Control as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.2/1-2.2:1.1/0003:413C:2113.0003/input/input8 > [ 3.484726] input: Dell KB216 Wired Keyboard System Control as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2.2/1-2.2:1.1/0003:413C:2113.0003/input/input9 > [ 3.527580] hid-generic 0003:413C:2113.0003: input: USB HID v1.11 Device [Dell KB216 Wired Keyboard] on usb-0000:00:14.0-2.2/input1 > [ 3.573674] EXT4-fs (nvme0n1p9): mounted filesystem with ordered data mode. Opts: (null) > [ 3.611217] VFS: Mounted root (ext4 filesystem) readonly on device 259:9. > [ 3.640814] usb 1-2.3: new high-speed USB device number 6 using xhci_hcd > [ 3.651423] devtmpfs: mounted > [ 3.722718] Freeing unused decrypted memory: 2040K > [ 3.760257] Freeing unused kernel image (initmem) memory: 1224K > [ 3.775165] usb 1-2.3: New USB device found, idVendor=046d, idProduct=085c, bcdDevice= 0.16 > [ 3.835064] Write protecting the kernel read-only data: 16384k > [ 3.872466] usb 1-2.3: New USB device strings: Mfr=0, Product=2, SerialNumber=1 > [ 3.909811] usb 1-2.3: Product: C922 Pro Stream Webcam > [ 3.946736] usb 1-2.3: SerialNumber: 9D6A015F > [ 3.983384] Freeing unused kernel image (text/rodata gap) memory: 2044K > [ 4.020469] Freeing unused kernel image (rodata/data gap) memory: 1612K > [ 4.060040] usb 1-2.4: new high-speed USB device number 7 using xhci_hcd > [ 4.096819] Run 5 as init process > [ 4.132427] with arguments: > [ 4.132428] 5 > [ 4.132428] with environment: > [ 4.132428] HOME=/ > [ 4.132428] TERM=linux > [ 4.132429] hung_task_panic=1 > [ 4.132429] softlockup_panic=1 > [ 4.132429] LANG=zh_CN.UTF-8 > [ 4.132429] selinux=0 > [ 4.132430] crashkernel=160M > [ 4.132440] Default init 5 failed (error -2) > [ 4.168197] Run /sbin/init as init process > [ 4.185829] usb 1-2.4: New USB device found, idVendor=0bda, idProduct=8152, bcdDevice=20.00 > [ 4.203820] with arguments: > [ 4.203821] /sbin/init > [ 4.239856] usb 1-2.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3 > [ 4.239857] usb 1-2.4: Product: USB 10/100 LAN > [ 4.275831] with environment: > [ 4.275831] HOME=/ > [ 4.275832] TERM=linux > [ 4.275832] hung_task_panic=1 > [ 4.311766] softlockup_panic=1 > [ 4.311766] usb 1-2.4: Manufacturer: Realtek > [ 4.311767] usb 1-2.4: SerialNumber: 00E04C363074 > [ 4.347697] LANG=zh_CN.UTF-8 > [ 4.383522] selinux=0 > [ 4.383522] crashkernel=160M > [ 4.906362] random: lvmconfig: uninitialized urandom read (4 bytes read) > [ 6.526063] fuse: init (API version 7.31) > [ 7.016455] EXT4-fs (nvme0n1p9): re-mounted. Opts: (null) > [ 8.256267] i801_smbus 0000:00:1f.4: SPD Write Disable is set > [ 8.261557] random: mktemp: uninitialized urandom read (6 bytes read) > [ 8.267828] random: mktemp: uninitialized urandom read (6 bytes read) > [ 8.273515] random: tlp-readconfs: uninitialized urandom read (4 bytes read) > [ 8.306017] i801_smbus 0000:00:1f.4: SMBus using PCI interrupt > [ 8.645630] i2c i2c-0: 2/2 memory slots populated (from DMI) > [ 8.705690] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k > [ 8.706126] i2c i2c-0: Successfully instantiated SPD at 0x51 > [ 8.780357] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. > [ 8.942072] e1000e 0000:00:1f.6: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode > [ 8.985248] input: PC Speaker as /devices/platform/pcspkr/input/input10 > [ 9.042729] checking generic (c0000000 7e9000) vs hw (e0000000 1000000) > [ 9.042730] checking generic (c0000000 7e9000) vs hw (c0000000 20000000) > [ 9.042731] fb0: switching to inteldrmfb from simple > [ 9.043504] thinkpad_acpi: ThinkPad ACPI Extras v0.26 > [ 9.043512] cfg80211: Loading compiled-in X.509 certificates for regulatory database > [ 9.043652] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' > [ 9.098996] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 8c:16:45:75:50:6c > [ 9.099625] thinkpad_acpi: http://ibm-acpi.sf.net/ > [ 9.125361] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection > [ 9.149540] thinkpad_acpi: ThinkPad BIOS N22ET54W (1.31 ), EC N22HT26W > [ 9.175060] e1000e 0000:00:1f.6 eth0: MAC: 12, PHY: 12, PBA No: 1000FF-0FF > [ 9.243214] thinkpad_acpi: Lenovo ThinkPad T480s, model 20L8S3M801 > [ 9.405125] Console: switching to colour dummy device 80x25 > [ 9.405156] i915 0000:00:02.0: vgaarb: deactivate vga console > [ 9.408636] Intel(R) Wireless WiFi driver for Linux > [ 9.414444] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). > [ 9.415081] i915 0000:00:02.0: [drm] *ERROR* DC state mismatch (0x0 -> 0x2) > [ 9.415115] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem > [ 9.416314] i915 0000:00:02.0: [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_04.bin (v1.4) > [ 9.431961] iwlwifi 0000:3d:00.0: Found debug destination: EXTERNAL_DRAM > [ 9.431968] iwlwifi 0000:3d:00.0: Found debug configuration: 0 > [ 9.432338] iwlwifi 0000:3d:00.0: loaded firmware version 36.77d01142.0 8265-36.ucode op_mode iwlmvm > [ 9.432451] iwlwifi 0000:3d:00.0: Direct firmware load for iwl-debug-yoyo.bin failed with error -2 > [ 9.435126] thinkpad_acpi: radio switch found; radios are enabled > [ 9.435261] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver > [ 9.435266] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... > [ 9.449417] thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is unblocked > [ 9.468511] [drm] Initialized i915 1.6.0 20200515 for 0000:00:02.0 on minor 0 > [ 9.472498] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one > [ 9.493868] Adding 1048572k swap on /dev/nvme0n1p10. Priority:-2 extents:1 across:1048572k SS > [ 9.512366] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) > [ 9.512522] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input12 > [ 9.512890] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915]) > [ 9.520300] thinkpad_acpi: battery 1 registered (start 0, stop 100) > [ 9.520303] battery: new extension: ThinkPad Battery Extension > [ 9.521015] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input11 > [ 9.545743] iwlwifi 0000:3d:00.0: Detected Intel(R) Dual Band Wireless AC 8265, REV=0x230 > [ 9.562287] iwlwifi 0000:3d:00.0: Applying debug destination EXTERNAL_DRAM > [ 9.563432] iwlwifi 0000:3d:00.0: Allocated 0x00400000 bytes for firmware monitor. > [ 9.602240] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC257: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker > [ 9.602408] snd_hda_codec_realtek hdaudioC0D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) > [ 9.602412] snd_hda_codec_realtek hdaudioC0D0: hp_outs=1 (0x21/0x0/0x0/0x0/0x0) > [ 9.602416] snd_hda_codec_realtek hdaudioC0D0: mono: mono_out=0x0 > [ 9.602418] snd_hda_codec_realtek hdaudioC0D0: inputs: > [ 9.602422] snd_hda_codec_realtek hdaudioC0D0: Mic=0x19 > [ 9.602425] snd_hda_codec_realtek hdaudioC0D0: Internal Mic=0x12 > [ 9.628002] iwlwifi 0000:3d:00.0: base HW address: b4:6b:fc:a3:80:d6 > [ 9.652406] fbcon: i915drmfb (fb0) is primary device > [ 9.653653] ------------[ cut here ]------------ > [ 9.653654] i915 0000:00:02.0: drm_WARN_ON(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })) & (1 << 31)) > [ 9.657092] WARNING: CPU: 1 PID: 103 at drivers/gpu/drm/i915/display/intel_psr.c:782 intel_psr_activate+0x3c6/0x440 [i915] > [ 9.657093] Modules linked in: snd_hda_codec_realtek(+) snd_hda_codec_generic iwlmvm(+) mac80211 input_leds snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core kvm_intel libarc4 snd_seq kvm snd_seq_device iwlwifi serio_raw irqbypass snd_pcm thinkpad_acpi pcspkr cfg80211 ledtrig_audio snd_timer rfkill i915 e1000e snd i2c_i801 soundcore i2c_smbus video intel_gtt iosf_mbi drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops fuse drm > [ 9.657262] CPU: 1 PID: 103 Comm: kworker/u16:3 Not tainted 5.8.0-rc1+ #179 > [ 9.657262] Hardware name: LENOVO 20L8S3M801/20L8S3M801, BIOS N22ET54W (1.31 ) 04/22/2019 > [ 9.657262] Workqueue: events_unbound async_run_entry_fn > [ 9.657263] RIP: 0010:intel_psr_activate+0x3c6/0x440 [i915] > [ 9.657264] Code: 4c 8b 6f 50 4d 85 ed 75 03 4c 8b 2f e8 c3 e0 1f e1 48 c7 c1 a0 ca 2e a0 4c 89 ea 48 c7 c7 40 3b 30 a0 48 89 c6 e8 f2 21 e0 e0 <0f> 0b 80 bd 88 69 00 00 00 0f 84 b5 fc ff ff 48 8b 7d 18 4c 8b 6f > [ 9.657264] RSP: 0018:ffff88842ad2b898 EFLAGS: 00010282 > [ 9.657265] RAX: 0000000000000000 RBX: 0000000000000001 RCX: 0000000000000000 > [ 9.657265] RDX: 000000000000013a RSI: ffffffff825346da RDI: ffffffff82534ada > [ 9.657265] RBP: ffff888423228000 R08: 000000023f6713ae R09: 000000000000013a > [ 9.657266] R10: 0000000000000067 R11: 000000000002fa10 R12: ffff88842c16b128 > [ 9.657266] R13: ffff88842bb09970 R14: 0000000000000001 R15: ffff88842cbcc000 > [ 9.657266] FS: 0000000000000000(0000) GS:ffff88842e440000(0000) knlGS:0000000000000000 > [ 9.657267] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 9.657267] CR2: 000055b5c70404c8 CR3: 0000000421d96005 CR4: 00000000001606e0 > [ 9.657267] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > [ 9.657267] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 > [ 9.657267] Call Trace: > [ 9.657268] intel_psr_update+0x17c/0x1a0 [i915] > [ 9.657268] intel_ddi_update_pipe+0x6c/0xb0 [i915] > [ 9.657268] intel_update_crtc+0x28b/0x420 [i915] > [ 9.657268] skl_commit_modeset_enables+0x142/0x4e0 [i915] > [ 9.657269] intel_atomic_commit_tail+0x2c6/0x1290 [i915] > [ 9.657269] ? complete+0x2f/0x40 > [ 9.657269] ? flush_workqueue_prep_pwqs+0x118/0x130 > [ 9.657269] ? flush_workqueue+0x178/0x3c0 > [ 9.657270] intel_atomic_commit+0x281/0x300 [i915] > [ 9.657270] drm_client_modeset_commit_atomic+0x1be/0x200 [drm] > [ 9.657270] drm_client_modeset_commit_locked+0x54/0x150 [drm] > [ 9.657270] drm_client_modeset_commit+0x24/0x40 [drm] > [ 9.657271] drm_fb_helper_restore_fbdev_mode_unlocked+0x49/0x90 [drm_kms_helper] > [ 9.657271] drm_fb_helper_set_par+0x30/0x40 [drm_kms_helper] > [ 9.657271] intel_fbdev_set_par+0x16/0x60 [i915] > [ 9.657272] ? con_is_visible+0x27/0x40 > [ 9.657272] fbcon_init+0x2e7/0x680 > [ 9.657272] visual_init+0xce/0x130 > [ 9.657272] do_bind_con_driver.isra.0+0x1da/0x2e0 > [ 9.657273] do_take_over_console+0x116/0x180 > [ 9.657273] do_fbcon_takeover+0x5c/0xc0 > [ 9.657273] register_framebuffer+0x1e4/0x300 > [ 9.657274] __drm_fb_helper_initial_config_and_unlock+0x320/0x490 [drm_kms_helper] > [ 9.657274] intel_fbdev_initial_config+0x14/0x30 [i915] > [ 9.657274] async_run_entry_fn+0x37/0x150 > [ 9.657274] process_one_work+0x1bf/0x3d0 > [ 9.657275] worker_thread+0x4d/0x3d0 > [ 9.657275] ? process_one_work+0x3d0/0x3d0 > [ 9.657275] kthread+0x11b/0x140 > [ 9.657276] ? kthread_create_worker_on_cpu+0x70/0x70 > [ 9.657276] ret_from_fork+0x22/0x30 > [ 9.657276] ---[ end trace f701c3abca58b4af ]--- > [ 9.674849] Console: switching to colour frame buffer device 240x67 > > [snip] > > Thanks > Dave > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Wed Jun 17 17:45:08 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 17 Jun 2020 18:45:08 +0100 Subject: [Intel-gfx] [PATCH i-g-t 08/10] gem_wsim: Snippet of a workload extracted from carchase In-Reply-To: <20200617160120.16555-9-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-9-tvrtko.ursulin@linux.intel.com> Message-ID: <159241590881.2739.7990352305579268212@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:18) > +1.RCS.1000.r3-47/w27-0/r0-58/r3-80/r22-31/r3-42/r9-4/w34-0/r3-18/r3-41/r21-0/r9-5/r3-78/r25-4/r3-104/r3-23/r30-0/r3-88/r22-27/r22-1/r25-45/r3-50/r22-12/r22-22/r22-3/r22-0/r25-56/r3-4/r22-15/r25-113/r3-7/r22-18/r25-60/r3-81/r25-21/r3-89/r18-5/r3-93/r17-8/r25-28/r25-87/r25-9/r25-13/r25-42/r25-90/r22-16/r34-2/r3-15/w3-64/r0-67/r25-99/r25-73/r3-6/r25-40/r3-90/r22-20/r0-45/r3-110/w32-17/w32-16/w32-3/w32-1/w33-2/r28-2/r3-98/r3-85/r25-48/r3-12/r25-104/r24-23/r3-87/r3-108/r3-26/r3-96/r22-5/r22-14/r3-49/r3-103/r22-6/r3-68/r3-112/r22-29/r22-28/r25-14/r25-44/r25-19/r3-67/r25-111/r18-4/r3-66/r18-17/r4-5/r25-68/r25-86/r25-26/r25-67/r3-37/r25-0/r22-7/r25-59/r25-71/r25-101/r25-75/r25-20/r25-91/r3-2/r3-117/r3-33/r22-2/r25-55/r25-66/r25-24/r25-105/r25-61/r25-11/r25-51/r25-64/r25-70/r18-19/r18-26/r18-21/r25-81/r25-78/r25-37/r25-50/r25-102/r25-35/r18-18/r18-13/r18-12/r3-69/r3-19/r3-100/r22-21/r25-22/r3-29/r25-93/r18-2/r18-14/r18-3/r22-10/r18-23/r18-7/r18-11/r3-73/r8-0/r25-92/r25-41/w33-3/r0-1! > 07/w19-0. > 0 This patch has been mangled. -Chris From matthew.d.roper at intel.com Wed Jun 17 18:00:06 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 17 Jun 2020 11:00:06 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Extend Wa_14010685332 to all ICP+ PCH's Message-ID: <20200617180006.4130501-1-matthew.d.roper@intel.com> This workaround now also applies to TGL and RKL, so extend the PCH test to just capture everthing ICP and beyond. Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8e823ba25f5f..923822343311 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2907,10 +2907,8 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) GEN3_IRQ_RESET(uncore, SDE); - /* Wa_14010685332:icl,jsl,ehl */ - if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP || - INTEL_PCH_TYPE(dev_priv) == PCH_JSP || - INTEL_PCH_TYPE(dev_priv) == PCH_MCC) { + /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */ + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); intel_uncore_rmw(uncore, SOUTH_CHICKEN1, -- 2.24.1 From lucas.demarchi at intel.com Wed Jun 17 18:22:58 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 11:22:58 -0700 Subject: [Intel-gfx] [PATCH v7 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200617033100.4044428-3-matthew.d.roper@intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> <20200617033100.4044428-3-matthew.d.roper@intel.com> Message-ID: <20200617182258.7gwvcbf35o3pi7cz@ldmartin-desk1> On Tue, Jun 16, 2020 at 08:30:57PM -0700, Matt Roper wrote: >Rocket Lake has a third DPLL (called 'DPLL4') that must be used to >enable a third display. Unlike EHL's variant of DPLL4, the RKL variant >behaves the same as DPLL0/1. And despite its name, the DPLL4 registers >are offset as if it were DPLL2. > >To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used >seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match >how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT. >This means just renumbering TBT to be ID '3' rather than being another >ID '2' like DPLL4. With this change, we can build our register >selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register >offsets are evenly-spaced. MGPLL's don't need any specific ID's >(they're just used to translate back to a tc_port), so we let them float >at the top of the enum. > >v2: > - Add new .update_ref_clks() hook. > >v3: > - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas) > >Bspec: 49202 >Bspec: 49443 >Bspec: 50288 >Bspec: 50289 >Cc: Lucas De Marchi <lucas.demarchi at intel.com> >Signed-off-by: Matt Roper <matthew.d.roper at intel.com> >--- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++----- > drivers/gpu/drm/i915/i915_reg.h | 15 +++------- > 3 files changed, 37 insertions(+), 21 deletions(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >index b45185b80bec..b5f4d4cef682 100644 >--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >@@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, > return false; > } > >- if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) >+ if (IS_ROCKETLAKE(dev_priv)) { > dpll_mask = > BIT(DPLL_ID_EHL_DPLL4) | > BIT(DPLL_ID_ICL_DPLL1) | > BIT(DPLL_ID_ICL_DPLL0); >- else >+ } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { >+ dpll_mask = >+ BIT(DPLL_ID_EHL_DPLL4) | >+ BIT(DPLL_ID_ICL_DPLL1) | >+ BIT(DPLL_ID_ICL_DPLL0); >+ } else { > dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); >+ } > > port_dpll->pll = intel_find_shared_dpll(state, crtc, > &port_dpll->hw_state, >@@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { > .dump_hw_state = icl_dump_hw_state, > }; > >+static const struct dpll_info rkl_plls[] = { >+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, >+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, >+ { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, >+ { }, >+}; >+ >+static const struct intel_dpll_mgr rkl_pll_mgr = { >+ .dpll_info = rkl_plls, >+ .get_dplls = icl_get_dplls, >+ .put_dplls = icl_put_dplls, >+ .update_ref_clks = icl_update_dpll_ref_clks, >+ .dump_hw_state = icl_dump_hw_state, >+}; >+ > /** > * intel_shared_dpll_init - Initialize shared DPLLs > * @dev: drm device >@@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) > const struct dpll_info *dpll_info; > int i; > >- if (INTEL_GEN(dev_priv) >= 12) >+ if (IS_ROCKETLAKE(dev_priv)) >+ dpll_mgr = &rkl_pll_mgr; >+ else if (INTEL_GEN(dev_priv) >= 12) > dpll_mgr = &tgl_pll_mgr; > else if (IS_ELKHARTLAKE(dev_priv)) > dpll_mgr = &ehl_pll_mgr; >diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >index 5d9a2bc371e7..49367847bfb5 100644 >--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >@@ -125,35 +125,35 @@ enum intel_dpll_id { > /** > * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL > */ >- DPLL_ID_ICL_TBTPLL = 2, >+ DPLL_ID_ICL_TBTPLL = 3, > /** > * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), > * TGL TC PLL 1 port 1 (TC1) > */ >- DPLL_ID_ICL_MGPLL1 = 3, >+ DPLL_ID_ICL_MGPLL1, > /** > * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) > * TGL TC PLL 1 port 2 (TC2) > */ >- DPLL_ID_ICL_MGPLL2 = 4, >+ DPLL_ID_ICL_MGPLL2, > /** > * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) > * TGL TC PLL 1 port 3 (TC3) > */ >- DPLL_ID_ICL_MGPLL3 = 5, >+ DPLL_ID_ICL_MGPLL3, > /** > * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) > * TGL TC PLL 1 port 4 (TC4) > */ >- DPLL_ID_ICL_MGPLL4 = 6, >+ DPLL_ID_ICL_MGPLL4, > /** > * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) > */ >- DPLL_ID_TGL_MGPLL5 = 7, >+ DPLL_ID_TGL_MGPLL5, > /** > * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) > */ >- DPLL_ID_TGL_MGPLL6 = 8, >+ DPLL_ID_TGL_MGPLL6, > }; > > #define I915_NUM_PLLS 9 >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >index 45bda5819abd..34f8698ac3aa 100644 >--- a/drivers/gpu/drm/i915/i915_reg.h >+++ b/drivers/gpu/drm/i915/i915_reg.h >@@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) >-#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) See my series adding DPLL support for DG1. We will need it again for a different reason, with a slightly different form. I'd let this here to avoid removing and adding it back. Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com> thanks Lucas De Marchi > > /* > * Device info offset array based helpers for groups of registers with unevenly >@@ -10427,19 +10426,13 @@ enum skl_power_gate { > > #define _TGL_DPLL0_CFGCR0 0x164284 > #define _TGL_DPLL1_CFGCR0 0x16428C >-/* TODO: add DPLL4 */ >-#define _TGL_TBTPLL_CFGCR0 0x16429C >-#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ >- _TGL_DPLL1_CFGCR0, \ >- _TGL_TBTPLL_CFGCR0) >+#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ >+ _TGL_DPLL1_CFGCR0) > > #define _TGL_DPLL0_CFGCR1 0x164288 > #define _TGL_DPLL1_CFGCR1 0x164290 >-/* TODO: add DPLL4 */ >-#define _TGL_TBTPLL_CFGCR1 0x1642A0 >-#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ >- _TGL_DPLL1_CFGCR1, \ >- _TGL_TBTPLL_CFGCR1) >+#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ >+ _TGL_DPLL1_CFGCR1) > > #define _DKL_PHY1_BASE 0x168000 > #define _DKL_PHY2_BASE 0x169000 >-- >2.24.1 > From patchwork at emeril.freedesktop.org Wed Jun 17 19:02:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 19:02:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Extend_Wa=5F14010685332_to_all_ICP+_PCH=27s?= In-Reply-To: <20200617180006.4130501-1-matthew.d.roper@intel.com> References: <20200617180006.4130501-1-matthew.d.roper@intel.com> Message-ID: <159242055721.29979.1747741231686415932@emeril.freedesktop.org> == Series Details == Series: drm/i915: Extend Wa_14010685332 to all ICP+ PCH's URL : https://patchwork.freedesktop.org/series/78481/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17983 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/index.html Known issues ------------ Here are the changes found in Patchwork_17983 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - {fi-tgl-dsi}: [INCOMPLETE][11] -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 41) ------------------------------ Missing (7): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17983 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17983: 5191bc177abc6e252b93ce4a081b472d06681472 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5191bc177abc drm/i915: Extend Wa_14010685332 to all ICP+ PCH's == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/index.html From emil.l.velikov at gmail.com Wed Jun 17 19:06:11 2020 From: emil.l.velikov at gmail.com (Emil Velikov) Date: Wed, 17 Jun 2020 20:06:11 +0100 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree In-Reply-To: <20200617170307.3c87be5a@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> <c82b9c52-d4e6-9eef-e37d-0a26ee9f1183@suse.de> <20200617170307.3c87be5a@canb.auug.org.au> Message-ID: <CACvgo50Ke-7pGqpwEb8y0iYOKv7wep1qUMm8_KJvUp0fV-YHoQ@mail.gmail.com> Hi Stephen, On Wed, 17 Jun 2020 at 08:03, Stephen Rothwell <sfr at canb.auug.org.au> wrote: > > Hi Thomas, > > On Wed, 17 Jun 2020 08:33:24 +0200 Thomas Zimmermann <tzimmermann at suse.de> wrote: > > > > We recently dropped the _unlock() suffix from drm_gem_object_put(). This > > patch should be ok. > > Yes, but what it shows is that the drm-misc tree is still based on > v5.7-rc1 and v5.8-rc1 has about 16000 more commits for you to get > conflicts against :-) > Being the culprit here - thanks for the patience and report. I believe that both AMD and drm-misc teams are aware of this lovely situation I've put them in. As you mentioned drm-misc is a bit special and doing the usual backmerge will be fun. If you have any tips on how to minimise such issues, I'd gladly utilise them. Thanks again, -Emil From matthew.d.roper at intel.com Wed Jun 17 20:00:38 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 17 Jun 2020 13:00:38 -0700 Subject: [Intel-gfx] [PATCH v7 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200617182258.7gwvcbf35o3pi7cz@ldmartin-desk1> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> <20200617033100.4044428-3-matthew.d.roper@intel.com> <20200617182258.7gwvcbf35o3pi7cz@ldmartin-desk1> Message-ID: <20200617200038.GG3680866@mdroper-desk1.amr.corp.intel.com> On Wed, Jun 17, 2020 at 11:22:58AM -0700, Lucas De Marchi wrote: > On Tue, Jun 16, 2020 at 08:30:57PM -0700, Matt Roper wrote: > > Rocket Lake has a third DPLL (called 'DPLL4') that must be used to > > enable a third display. Unlike EHL's variant of DPLL4, the RKL variant > > behaves the same as DPLL0/1. And despite its name, the DPLL4 registers > > are offset as if it were DPLL2. > > > > To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used > > seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match > > how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT. > > This means just renumbering TBT to be ID '3' rather than being another > > ID '2' like DPLL4. With this change, we can build our register > > selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register > > offsets are evenly-spaced. MGPLL's don't need any specific ID's > > (they're just used to translate back to a tc_port), so we let them float > > at the top of the enum. > > > > v2: > > - Add new .update_ref_clks() hook. > > > > v3: > > - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas) > > > > Bspec: 49202 > > Bspec: 49443 > > Bspec: 50288 > > Bspec: 50289 > > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++----- > > drivers/gpu/drm/i915/i915_reg.h | 15 +++------- > > 3 files changed, 37 insertions(+), 21 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > index b45185b80bec..b5f4d4cef682 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, > > return false; > > } > > > > - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) > > + if (IS_ROCKETLAKE(dev_priv)) { > > dpll_mask = > > BIT(DPLL_ID_EHL_DPLL4) | > > BIT(DPLL_ID_ICL_DPLL1) | > > BIT(DPLL_ID_ICL_DPLL0); > > - else > > + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { > > + dpll_mask = > > + BIT(DPLL_ID_EHL_DPLL4) | > > + BIT(DPLL_ID_ICL_DPLL1) | > > + BIT(DPLL_ID_ICL_DPLL0); > > + } else { > > dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); > > + } > > > > port_dpll->pll = intel_find_shared_dpll(state, crtc, > > &port_dpll->hw_state, > > @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { > > .dump_hw_state = icl_dump_hw_state, > > }; > > > > +static const struct dpll_info rkl_plls[] = { > > + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, > > + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, > > + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, > > + { }, > > +}; > > + > > +static const struct intel_dpll_mgr rkl_pll_mgr = { > > + .dpll_info = rkl_plls, > > + .get_dplls = icl_get_dplls, > > + .put_dplls = icl_put_dplls, > > + .update_ref_clks = icl_update_dpll_ref_clks, > > + .dump_hw_state = icl_dump_hw_state, > > +}; > > + > > /** > > * intel_shared_dpll_init - Initialize shared DPLLs > > * @dev: drm device > > @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) > > const struct dpll_info *dpll_info; > > int i; > > > > - if (INTEL_GEN(dev_priv) >= 12) > > + if (IS_ROCKETLAKE(dev_priv)) > > + dpll_mgr = &rkl_pll_mgr; > > + else if (INTEL_GEN(dev_priv) >= 12) > > dpll_mgr = &tgl_pll_mgr; > > else if (IS_ELKHARTLAKE(dev_priv)) > > dpll_mgr = &ehl_pll_mgr; > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > index 5d9a2bc371e7..49367847bfb5 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > @@ -125,35 +125,35 @@ enum intel_dpll_id { > > /** > > * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL > > */ > > - DPLL_ID_ICL_TBTPLL = 2, > > + DPLL_ID_ICL_TBTPLL = 3, > > /** > > * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), > > * TGL TC PLL 1 port 1 (TC1) > > */ > > - DPLL_ID_ICL_MGPLL1 = 3, > > + DPLL_ID_ICL_MGPLL1, > > /** > > * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) > > * TGL TC PLL 1 port 2 (TC2) > > */ > > - DPLL_ID_ICL_MGPLL2 = 4, > > + DPLL_ID_ICL_MGPLL2, > > /** > > * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) > > * TGL TC PLL 1 port 3 (TC3) > > */ > > - DPLL_ID_ICL_MGPLL3 = 5, > > + DPLL_ID_ICL_MGPLL3, > > /** > > * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) > > * TGL TC PLL 1 port 4 (TC4) > > */ > > - DPLL_ID_ICL_MGPLL4 = 6, > > + DPLL_ID_ICL_MGPLL4, > > /** > > * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) > > */ > > - DPLL_ID_TGL_MGPLL5 = 7, > > + DPLL_ID_TGL_MGPLL5, > > /** > > * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) > > */ > > - DPLL_ID_TGL_MGPLL6 = 8, > > + DPLL_ID_TGL_MGPLL6, > > }; > > > > #define I915_NUM_PLLS 9 > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 45bda5819abd..34f8698ac3aa 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > > -#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) > > See my series adding DPLL support for DG1. We will need it again for a > different reason, with a slightly different form. I'd let this here > to avoid removing and adding it back. > > Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com> With the renumbering of TBT to 3, we now have a "hole" in the DPLLs exposed on TGL (0, 1, 3) which WARNs: <4>[ 6.165705] i915 0000:00:02.0: drm_WARN_ON(i != dpll_info[i].id) <4>[ 6.166050] WARNING: CPU: 7 PID: 335 at drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4360 intel_shared_dpll_init+0xa6/0x1d0 [i915] I remember having a hole was a problem back when we just passed min/max DPLLs for initialization, but I think it should be safe now ever since: commit 2a86972f60fcfaa0daa02b9fe461935ea2063791 Author: Matt Roper <matthew.d.roper at intel.com> Date: Tue Oct 8 10:29:20 2019 -0700 drm/i915: Select DPLL's via mask so I'll send another version that drops that WARN and keeps the _MMIO_PLL3 definition here. Thanks. Matt > > thanks > Lucas De Marchi > > > > > /* > > * Device info offset array based helpers for groups of registers with unevenly > > @@ -10427,19 +10426,13 @@ enum skl_power_gate { > > > > #define _TGL_DPLL0_CFGCR0 0x164284 > > #define _TGL_DPLL1_CFGCR0 0x16428C > > -/* TODO: add DPLL4 */ > > -#define _TGL_TBTPLL_CFGCR0 0x16429C > > -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ > > - _TGL_DPLL1_CFGCR0, \ > > - _TGL_TBTPLL_CFGCR0) > > +#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ > > + _TGL_DPLL1_CFGCR0) > > > > #define _TGL_DPLL0_CFGCR1 0x164288 > > #define _TGL_DPLL1_CFGCR1 0x164290 > > -/* TODO: add DPLL4 */ > > -#define _TGL_TBTPLL_CFGCR1 0x1642A0 > > -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ > > - _TGL_DPLL1_CFGCR1, \ > > - _TGL_TBTPLL_CFGCR1) > > +#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ > > + _TGL_DPLL1_CFGCR1) > > > > #define _DKL_PHY1_BASE 0x168000 > > #define _DKL_PHY2_BASE 0x169000 > > -- > > 2.24.1 > > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From patchwork at emeril.freedesktop.org Wed Jun 17 20:20:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 17 Jun 2020 20:20:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Extend_Wa=5F14010685332_to_all_ICP+_PCH=27s?= In-Reply-To: <20200617180006.4130501-1-matthew.d.roper@intel.com> References: <20200617180006.4130501-1-matthew.d.roper@intel.com> Message-ID: <159242521166.29980.11889795722588587477@emeril.freedesktop.org> == Series Details == Series: drm/i915: Extend Wa_14010685332 to all ICP+ PCH's URL : https://patchwork.freedesktop.org/series/78481/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639_full -> Patchwork_17983_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17983_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at bcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +7 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl2/igt at gem_ctx_isolation@preservation-s3 at bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at bcs0.html * igt at gem_ctx_persistence@process: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at gem_ctx_persistence@process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl1/igt at gem_ctx_persistence@process.html * igt at gem_exec_flush@basic-wb-rw-before-default: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +24 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl2/igt at gem_exec_flush@basic-wb-rw-before-default.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-apl7/igt at gem_exec_flush@basic-wb-rw-before-default.html * igt at kms_flip@2x-plain-flip-ts-check at bc-hdmi-a1-hdmi-a2: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#1928]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk5/igt at kms_flip@2x-plain-flip-ts-check at bc-hdmi-a1-hdmi-a2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-glk4/igt at kms_flip@2x-plain-flip-ts-check at bc-hdmi-a1-hdmi-a2.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#165] / [i915#78]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl1/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl2/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt at kms_flip_tiling@flip-changes-tiling.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-skl10/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][13] -> [DMESG-FAIL][14] ([i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling-y.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-iclb1/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_setmode@basic: - shard-kbl: [PASS][19] -> [FAIL][20] ([i915#31]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at kms_setmode@basic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-b-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([i915#155]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at kms_vblank@pipe-b-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl6/igt at kms_vblank@pipe-b-ts-continuation-suspend.html * igt at kms_vblank@pipe-c-wait-forked-busy: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb6/igt at kms_vblank@pipe-c-wait-forked-busy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-tglb7/igt at kms_vblank@pipe-c-wait-forked-busy.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#1542]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb5/igt at perf@blocking-parameterized.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-iclb7/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_exec_gttfill@all: - shard-glk: [DMESG-WARN][27] ([i915#118] / [i915#95]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk4/igt at gem_exec_gttfill@all.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-glk8/igt at gem_exec_gttfill@all.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [INCOMPLETE][29] ([i915#82]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_mmap_offset@ptrace at gtt: - shard-kbl: [DMESG-WARN][31] ([i915#93] / [i915#95]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl1/igt at gem_mmap_offset@ptrace at gtt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl6/igt at gem_mmap_offset@ptrace at gtt.html * igt at gem_tiled_blits@basic: - shard-snb: [TIMEOUT][33] ([i915#1958]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gem_tiled_blits@basic.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-snb5/igt at gem_tiled_blits@basic.html * igt at gem_tiled_swapping@non-threaded: - shard-apl: [DMESG-WARN][35] ([i915#183]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl2/igt at gem_tiled_swapping@non-threaded.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-apl7/igt at gem_tiled_swapping@non-threaded.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-tglb: [DMESG-WARN][37] ([i915#402]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb5/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-tglb2/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +4 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl7/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [FAIL][41] ([i915#1928]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl10/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_plane@plane-position-covered-pipe-b-planes: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +6 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl6/igt at kms_plane@plane-position-covered-pipe-b-planes.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-skl6/igt at kms_plane@plane-position-covered-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][47] ([fdo#108145] / [i915#265]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-apl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl6/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-apl1/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][53] ([fdo#109642] / [fdo#111068]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb5/igt at kms_psr2_su@page_flip.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb6/igt at kms_psr@psr2_sprite_mmap_gtt.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_vblank@invalid: - shard-apl: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] +17 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl4/igt at kms_vblank@invalid.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-apl2/igt at kms_vblank@invalid.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][59] ([i915#1958]) -> [FAIL][60] ([i915#1930]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html * igt at gen7_exec_parse@chained-batch: - shard-snb: [TIMEOUT][61] ([i915#1958]) -> [SKIP][62] ([fdo#109271]) +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gen7_exec_parse@chained-batch.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-snb5/igt at gen7_exec_parse@chained-batch.html * igt at kms_color_chamelium@pipe-b-ctm-max: - shard-snb: [TIMEOUT][63] ([i915#1958]) -> [SKIP][64] ([fdo#109271] / [fdo#111827]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at kms_color_chamelium@pipe-b-ctm-max.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-snb5/igt at kms_color_chamelium@pipe-b-ctm-max.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][65] ([i915#93] / [i915#95]) -> [DMESG-WARN][66] ([i915#180] / [i915#93] / [i915#95]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][68] ([fdo#108145] / [i915#1982]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#183]: https://gitlab.freedesktop.org/drm/intel/issues/183 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17983 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17983: 5191bc177abc6e252b93ce4a081b472d06681472 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17983/index.html From lucas.demarchi at intel.com Wed Jun 17 20:41:02 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 13:41:02 -0700 Subject: [Intel-gfx] [PATCH v7 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200617200038.GG3680866@mdroper-desk1.amr.corp.intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> <20200617033100.4044428-3-matthew.d.roper@intel.com> <20200617182258.7gwvcbf35o3pi7cz@ldmartin-desk1> <20200617200038.GG3680866@mdroper-desk1.amr.corp.intel.com> Message-ID: <20200617204102.lkzn75au57i6fd4x@ldmartin-desk1> On Wed, Jun 17, 2020 at 01:00:38PM -0700, Matt Roper wrote: >On Wed, Jun 17, 2020 at 11:22:58AM -0700, Lucas De Marchi wrote: >> On Tue, Jun 16, 2020 at 08:30:57PM -0700, Matt Roper wrote: >> > Rocket Lake has a third DPLL (called 'DPLL4') that must be used to >> > enable a third display. Unlike EHL's variant of DPLL4, the RKL variant >> > behaves the same as DPLL0/1. And despite its name, the DPLL4 registers >> > are offset as if it were DPLL2. >> > >> > To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used >> > seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match >> > how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT. >> > This means just renumbering TBT to be ID '3' rather than being another >> > ID '2' like DPLL4. With this change, we can build our register >> > selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register >> > offsets are evenly-spaced. MGPLL's don't need any specific ID's >> > (they're just used to translate back to a tc_port), so we let them float >> > at the top of the enum. >> > >> > v2: >> > - Add new .update_ref_clks() hook. >> > >> > v3: >> > - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas) >> > >> > Bspec: 49202 >> > Bspec: 49443 >> > Bspec: 50288 >> > Bspec: 50289 >> > Cc: Lucas De Marchi <lucas.demarchi at intel.com> >> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> >> > --- >> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- >> > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++----- >> > drivers/gpu/drm/i915/i915_reg.h | 15 +++------- >> > 3 files changed, 37 insertions(+), 21 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >> > index b45185b80bec..b5f4d4cef682 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c >> > @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, >> > return false; >> > } >> > >> > - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) >> > + if (IS_ROCKETLAKE(dev_priv)) { >> > dpll_mask = >> > BIT(DPLL_ID_EHL_DPLL4) | >> > BIT(DPLL_ID_ICL_DPLL1) | >> > BIT(DPLL_ID_ICL_DPLL0); >> > - else >> > + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { >> > + dpll_mask = >> > + BIT(DPLL_ID_EHL_DPLL4) | >> > + BIT(DPLL_ID_ICL_DPLL1) | >> > + BIT(DPLL_ID_ICL_DPLL0); >> > + } else { >> > dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); >> > + } >> > >> > port_dpll->pll = intel_find_shared_dpll(state, crtc, >> > &port_dpll->hw_state, >> > @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { >> > .dump_hw_state = icl_dump_hw_state, >> > }; >> > >> > +static const struct dpll_info rkl_plls[] = { >> > + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, >> > + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, >> > + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, >> > + { }, >> > +}; >> > + >> > +static const struct intel_dpll_mgr rkl_pll_mgr = { >> > + .dpll_info = rkl_plls, >> > + .get_dplls = icl_get_dplls, >> > + .put_dplls = icl_put_dplls, >> > + .update_ref_clks = icl_update_dpll_ref_clks, >> > + .dump_hw_state = icl_dump_hw_state, >> > +}; >> > + >> > /** >> > * intel_shared_dpll_init - Initialize shared DPLLs >> > * @dev: drm device >> > @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) >> > const struct dpll_info *dpll_info; >> > int i; >> > >> > - if (INTEL_GEN(dev_priv) >= 12) >> > + if (IS_ROCKETLAKE(dev_priv)) >> > + dpll_mgr = &rkl_pll_mgr; >> > + else if (INTEL_GEN(dev_priv) >= 12) >> > dpll_mgr = &tgl_pll_mgr; >> > else if (IS_ELKHARTLAKE(dev_priv)) >> > dpll_mgr = &ehl_pll_mgr; >> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >> > index 5d9a2bc371e7..49367847bfb5 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h >> > @@ -125,35 +125,35 @@ enum intel_dpll_id { >> > /** >> > * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL >> > */ >> > - DPLL_ID_ICL_TBTPLL = 2, >> > + DPLL_ID_ICL_TBTPLL = 3, >> > /** >> > * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), >> > * TGL TC PLL 1 port 1 (TC1) >> > */ >> > - DPLL_ID_ICL_MGPLL1 = 3, >> > + DPLL_ID_ICL_MGPLL1, >> > /** >> > * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) >> > * TGL TC PLL 1 port 2 (TC2) >> > */ >> > - DPLL_ID_ICL_MGPLL2 = 4, >> > + DPLL_ID_ICL_MGPLL2, >> > /** >> > * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) >> > * TGL TC PLL 1 port 3 (TC3) >> > */ >> > - DPLL_ID_ICL_MGPLL3 = 5, >> > + DPLL_ID_ICL_MGPLL3, >> > /** >> > * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) >> > * TGL TC PLL 1 port 4 (TC4) >> > */ >> > - DPLL_ID_ICL_MGPLL4 = 6, >> > + DPLL_ID_ICL_MGPLL4, >> > /** >> > * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) >> > */ >> > - DPLL_ID_TGL_MGPLL5 = 7, >> > + DPLL_ID_TGL_MGPLL5, >> > /** >> > * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) >> > */ >> > - DPLL_ID_TGL_MGPLL6 = 8, >> > + DPLL_ID_TGL_MGPLL6, >> > }; >> > >> > #define I915_NUM_PLLS 9 >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> > index 45bda5819abd..34f8698ac3aa 100644 >> > --- a/drivers/gpu/drm/i915/i915_reg.h >> > +++ b/drivers/gpu/drm/i915/i915_reg.h >> > @@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) >> > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) >> > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) >> > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) >> > -#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) >> >> See my series adding DPLL support for DG1. We will need it again for a >> different reason, with a slightly different form. I'd let this here >> to avoid removing and adding it back. >> >> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com> > >With the renumbering of TBT to 3, we now have a "hole" in the DPLLs >exposed on TGL (0, 1, 3) which WARNs: > > <4>[ 6.165705] i915 0000:00:02.0: drm_WARN_ON(i != dpll_info[i].id) > <4>[ 6.166050] WARNING: CPU: 7 PID: 335 at drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4360 intel_shared_dpll_init+0xa6/0x1d0 [i915] > >I remember having a hole was a problem back when we just passed min/max >DPLLs for initialization, but I think it should be safe now ever since: yep, I think we had a change like that when we had DPLL4 for TGL implemented. > > commit 2a86972f60fcfaa0daa02b9fe461935ea2063791 > Author: Matt Roper <matthew.d.roper at intel.com> > Date: Tue Oct 8 10:29:20 2019 -0700 > > drm/i915: Select DPLL's via mask > >so I'll send another version that drops that WARN and keeps the >_MMIO_PLL3 definition here. thanks Lucas De Marchi > >Thanks. > > >Matt > >> >> thanks >> Lucas De Marchi >> >> > >> > /* >> > * Device info offset array based helpers for groups of registers with unevenly >> > @@ -10427,19 +10426,13 @@ enum skl_power_gate { >> > >> > #define _TGL_DPLL0_CFGCR0 0x164284 >> > #define _TGL_DPLL1_CFGCR0 0x16428C >> > -/* TODO: add DPLL4 */ >> > -#define _TGL_TBTPLL_CFGCR0 0x16429C >> > -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ >> > - _TGL_DPLL1_CFGCR0, \ >> > - _TGL_TBTPLL_CFGCR0) >> > +#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ >> > + _TGL_DPLL1_CFGCR0) >> > >> > #define _TGL_DPLL0_CFGCR1 0x164288 >> > #define _TGL_DPLL1_CFGCR1 0x164290 >> > -/* TODO: add DPLL4 */ >> > -#define _TGL_TBTPLL_CFGCR1 0x1642A0 >> > -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ >> > - _TGL_DPLL1_CFGCR1, \ >> > - _TGL_TBTPLL_CFGCR1) >> > +#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ >> > + _TGL_DPLL1_CFGCR1) >> > >> > #define _DKL_PHY1_BASE 0x168000 >> > #define _DKL_PHY2_BASE 0x169000 >> > -- >> > 2.24.1 >> > > >-- >Matt Roper >Graphics Software Engineer >VTT-OSGC Platform Enablement >Intel Corporation >(916) 356-2795 From manasi.d.navare at intel.com Thu Jun 18 00:01:24 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Wed, 17 Jun 2020 17:01:24 -0700 Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable In-Reply-To: <20200618000124.29036-1-manasi.d.navare@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> Message-ID: <20200618000124.29036-2-manasi.d.navare@intel.com> Based on the platform, Bspec expects us to wait or poll with timeout for DDI BUF IDLE bit to be set to 0 (non idle) afetr enabling DDI_BUF_CTL. Use the existing wait_for_buf_idle() to do this. v2: * Based on platform, fixed delay or poll (Ville) * Use a helper to do this (Imre, Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index e4738c3b6d44..788c2be8fa73 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4031,7 +4031,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); - udelay(600); + intel_wait_ddi_buf_idle(dev_priv, port, false); } static void intel_ddi_set_link_train(struct intel_dp *intel_dp, -- 2.19.1 From manasi.d.navare at intel.com Thu Jun 18 00:01:23 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Wed, 17 Jun 2020 17:01:23 -0700 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Message-ID: <20200618000124.29036-1-manasi.d.navare@intel.com> Modify the helper to add a fixed delay or poll with timeout based on platform specification in bothe enable and disable cases so check for either Idle bit set (DDI_BUF_CTL is idle for disable case) or check for Idle bit = 0 (non idle for DDI BUF enable case) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++--------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..e4738c3b6d44 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, } static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, - enum port port) + enum port port, bool idle) { - i915_reg_t reg = DDI_BUF_CTL(port); - int i; - - for (i = 0; i < 16; i++) { - udelay(1); - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) - return; + if (idle) { + if (IS_BROXTON(dev_priv)) + udelay(16); + else + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + DDI_BUF_IS_IDLE), 16)) + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", + port_name(port)); + } else { + if (INTEL_GEN(dev_priv) < 10) + udelay(600); + else + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + DDI_BUF_IS_IDLE), 600)) + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", + port_name(port)); } - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", - port_name(port)); + } static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); - intel_wait_ddi_buf_idle(dev_priv, PORT_E); + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true); /* Reset FDI_RX_MISC pwrdn lanes */ temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, intel_ddi_disable_fec_state(encoder, crtc_state); if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); + intel_wait_ddi_buf_idle(dev_priv, port, true); } static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); + intel_wait_ddi_buf_idle(dev_priv, port, true); } dp_tp_ctl = DP_TP_CTL_ENABLE | -- 2.19.1 From patchwork at emeril.freedesktop.org Thu Jun 18 00:31:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 00:31:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv2=2C1/2=5D_drm/i915/dp=3A_Helper_f?= =?utf-8?q?or_checking_DDI=5FBUF=5FCTL_Idle_status?= In-Reply-To: <20200618000124.29036-1-manasi.d.navare@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> Message-ID: <159244028662.22459.6905843510578091860@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status URL : https://patchwork.freedesktop.org/series/78500/ State : warning == Summary == $ dim checkpatch origin/drm-tip 42dd12bb148b drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status -:39: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #39: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1189: + udelay(16); -:47: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #47: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1197: + udelay(600); total: 0 errors, 0 warnings, 2 checks, 60 lines checked ed2c62fe315d drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable From lucas.demarchi at intel.com Thu Jun 18 00:42:08 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:08 -0700 Subject: [Intel-gfx] [PATCH v2 00/32] Introduce DG1 Message-ID: <20200618004240.16263-1-lucas.demarchi@intel.com> v2: - Remove some wrong/unneeded patches - Collect R-b - Rebase As in previous version, the RKL patches are here only for completeness and avoid future conflicts, not to be reviewed/applied. Original cover: DG1 is a gen12 dgfx platform. This is the first batch of patches to support it. It also depends on some in-flight patches adding RKL. In order for this series to be compiled, I'm including them here. While converting some of these patches to the current intel_uncore/intel_de APIs I thought it could be useful to return the previous value. The patch for that is included here, but I ended up not using and it can be dropped if there is no interest. Abdiel Janulgue (2): drm/i915/dg1: add initial DG-1 definitions drm/i915/dg1: Add DG1 PCI IDs Aditya Swarup (4): drm/i915/dg1: Add DPLL macros for DG1 drm/i915/dg1: Add and setup DPLLs for DG1 drm/i915/dg1: Enable DPLL for DG1 drm/i915/dg1: Enable first 2 ports for DG1 Anshuman Gupta (1): drm/i915/dg1: DG1 does not support DC6 Anusha Srivatsa (1): drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Clinton A Taylor (1): drm/i915/dg1: invert HPD pins Lucas De Marchi (7): drm/i915/dg1: add support for the master unit interrupt drm/i915/dg1: Add fake PCH drm/i915/dg1: Define MOCS table for DG1 drm/i915/dg1: add hpd interrupt handling drm/i915/dg1: gmbus pin mapping drm/i915/dg1: map/unmap pll clocks drm/i915/dg1: enable PORT C/D aka D/E Matt Atwood (1): drm/i915/dg1: Load DMC Matt Roper (11): drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout drm/i915/rkl: Add DPLL4 support drm/i915/rkl: Handle HTI drm/i915/rkl: Add initial workarounds drm/i915/rkl: Add Wa_14011224835 for PHY B initialization drm/i915/dg1: Initialize RAWCLK properly drm/i915/dg1: Wait for pcode/uncore handshake at startup drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D drm/i915/dg1: Update comp master/slave relationships for PHYs drm/i915/dg1: Update voltage swing tables for DP drm/i915/dg1: provide port/phy mapping for vbt Stuart Summers (2): drm/i915: Add has_master_unit_irq flag drm/i915/dg1: Add initial DG1 workarounds Uma Shankar (1): drm/i915/dg1: Add DG1 power wells Venkata Sandeep Dhanalakota (1): drm/i915/dg1: Increase mmio size to 4MB drivers/gpu/drm/i915/display/intel_bios.c | 12 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +- .../gpu/drm/i915/display/intel_combo_phy.c | 33 ++- drivers/gpu/drm/i915/display/intel_csr.c | 19 +- drivers/gpu/drm/i915/display/intel_ddi.c | 144 +++++++++++- drivers/gpu/drm/i915/display/intel_display.c | 87 +++++++- .../drm/i915/display/intel_display_power.c | 211 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 117 ++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 32 ++- drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 9 +- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 159 ++++++++++--- drivers/gpu/drm/i915/i915_debugfs.c | 4 + drivers/gpu/drm/i915/i915_drv.c | 3 + drivers/gpu/drm/i915/i915_drv.h | 12 + drivers/gpu/drm/i915/i915_irq.c | 120 +++++++++- drivers/gpu/drm/i915/i915_pci.c | 13 ++ drivers/gpu/drm/i915/i915_reg.h | 101 +++++++-- drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 2 + drivers/gpu/drm/i915/intel_pch.c | 6 + drivers/gpu/drm/i915/intel_pch.h | 4 + drivers/gpu/drm/i915/intel_pm.c | 17 +- drivers/gpu/drm/i915/intel_sideband.c | 15 ++ drivers/gpu/drm/i915/intel_sideband.h | 2 + drivers/gpu/drm/i915/intel_uncore.c | 4 + include/drm/i915_pciids.h | 4 + 29 files changed, 1083 insertions(+), 123 deletions(-) -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:09 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:09 -0700 Subject: [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-2-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. v2: - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 - Checkpatch style fixes Bspec: 50287 Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b6..8790f221dc77c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, enum phy phy) { - if (intel_phy_is_combo(dev_priv, phy)) { + if (IS_ROCKETLAKE(dev_priv)) { + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + } else if (intel_phy_is_combo(dev_priv, phy)) { return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } else if (intel_phy_is_tc(dev_priv, phy)) { enum tc_port tc_port = intel_port_to_tc(dev_priv, @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { + u32 mask, sel; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + } + /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, * Clock Select chooses the PLL for both DDIA and DDID and * drives port A in all cases." */ - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + val &= ~mask; + val |= sel; intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7457813ef2733..6c2bb3354b869 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + u32 mask, shift; + + if (IS_ROCKETLAKE(dev_priv)) { + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } else { + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); + } + + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; + id = temp >> shift; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89aa..45bda5819abd0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10195,12 +10195,18 @@ enum skl_power_gate { #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ (tc_port) + 12 : \ (tc_port) - PORT_TC4 + 21)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) /* CNL PLL */ #define DPLL0_ENABLE 0x46010 -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:11 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:11 -0700 Subject: [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-4-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> If HTI (also sometimes called HDPORT) is enabled at startup, it may be using some of the PHYs and DPLLs making them unavailable for general usage. Let's read out the HDPORT_STATE register and avoid making use of resources that HTI is already using. v2: - Fix minor checkpatch warnings Bspec: 49189 Bspec: 53707 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++ 5 files changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6c2bb3354b869..f16512eddc587 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -46,6 +46,7 @@ #include "display/intel_ddi.h" #include "display/intel_dp.h" #include "display/intel_dp_mst.h" +#include "display/intel_dpll_mgr.h" #include "display/intel_dsi.h" #include "display/intel_dvo.h" #include "display/intel_gmbus.h" @@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } +static bool hti_uses_phy(u32 hdport_state, enum phy phy) +{ + return hdport_state & HDPORT_ENABLED && + (hdport_state & HDPORT_PHY_USED_DP(phy) || + hdport_state & HDPORT_PHY_USED_HDMI(phy)); +} + static void intel_setup_outputs(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; @@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_ROCKETLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + /* + * If HTI (aka HDPORT) is enabled at boot, it may have taken + * over some of the PHYs and made them unavailable to the + * driver. In that case we should skip initializing the + * corresponding outputs. + */ + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + + if (!hti_uses_phy(hdport_state, PHY_A)) + intel_ddi_init(dev_priv, PORT_A); + if (!hti_uses_phy(hdport_state, PHY_B)) + intel_ddi_init(dev_priv, PORT_B); + if (!hti_uses_phy(hdport_state, PHY_C)) + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ + if (!hti_uses_phy(hdport_state, PHY_D)) + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ } else if (INTEL_GEN(dev_priv) >= 12) { intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); @@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) intel_dpll_readout_hw_state(dev_priv); + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); + for_each_intel_encoder(dev, encoder) { pipe = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b5f4d4cef682b..6f59f9ec453bf 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) mutex_unlock(&dev_priv->dpll.lock); } +/* + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them + * unavailable for use. + */ +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) +{ + u32 hdport_state; + + if (!IS_ROCKETLAKE(dev_priv)) + return 0; + + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); + if (!(hdport_state & HDPORT_ENABLED)) + return 0; + + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); +} + static struct intel_shared_dpll * intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + /* Eliminate DPLLs from consideration if reserved by HTI */ + dpll_mask &= ~dev_priv->hti_pll_mask; + for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { pll = &dev_priv->dpll.shared_dplls[i]; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 49367847bfb55..edcc43f4670ff 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device *dev); void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fef..b836032fa0deb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1037,6 +1037,9 @@ struct drm_i915_private { struct intel_l3_parity l3_parity; + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ + u32 hti_pll_mask; + /* * edram size in MB. * Cannot be determined by PCIID. You must always read a register. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 34f8698ac3aa6..34b2ec04ccd86 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2908,6 +2908,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) +#define HDPORT_STATE _MMIO(0x45050) +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) +#define HDPORT_ENABLED REG_BIT(0) + /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:14 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:14 -0700 Subject: [Intel-gfx] [PATCH v2 06/32] drm/i915: Add has_master_unit_irq flag In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-7-lucas.demarchi@intel.com> From: Stuart Summers <stuart.summers at intel.com> Add flag to differentiate platforms with and without the master IRQ control bit. Signed-off-by: Stuart Summers <stuart.summers at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b836032fa0deb..2f8057a0b2280 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1595,6 +1595,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ (INTEL_INFO(dev_priv)->has_logical_ring_preemption) +#define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq) + #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 8d62b8538585d..770d07003ce60 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -122,6 +122,7 @@ enum intel_ppgtt_type { func(has_logical_ring_contexts); \ func(has_logical_ring_elsq); \ func(has_logical_ring_preemption); \ + func(has_master_unit_irq); \ func(has_pooled_eu); \ func(has_rc6); \ func(has_rc6p); \ -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:15 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:15 -0700 Subject: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-8-lucas.demarchi@intel.com> From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> Bspec: 33617, 33617 Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Stuart Summers <stuart.summers at intel.com> Cc: Vanshidhar Konda <vanshidhar.r.konda at intel.com> Cc: Lucas De Marchi <lucas.demarchi at intel.com> Cc: Aravind Iddamsetty <aravind.iddamsetty at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++ drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 4 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2f8057a0b2280..f79c09257eb6b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) #define IS_BDW_ULT(dev_priv) \ @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_RKL_REVID(p, since, until) \ (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) +#define DG1_REVID_A0 0x0 +#define DG1_REVID_B0 0x1 + +#define IS_DG1_REVID(p, since, until) \ + (IS_DG1(p) && IS_REVID(p, since, until)) + #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index e5fdf17cd9cdd..58cceeaa0ffa5 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = { #define GEN12_DGFX_FEATURES \ GEN12_FEATURES, \ + .memory_regions = REGION_SMEM | REGION_LMEM, \ + .has_master_unit_irq = 1, \ .is_dgfx = 1 +static const struct intel_device_info intel_dg1_info = { + GEN12_DGFX_FEATURES, + PLATFORM(INTEL_DG1), + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), + .require_force_probe = 1, + .engine_mask = + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | + BIT(VCS0) | BIT(VCS2), +}; + #undef GEN #undef PLATFORM diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 544ac61fbc363..2e40a6649d142 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -63,6 +63,7 @@ static const char * const platform_names[] = { PLATFORM_NAME(ELKHARTLAKE), PLATFORM_NAME(TIGERLAKE), PLATFORM_NAME(ROCKETLAKE), + PLATFORM_NAME(DG1), }; #undef PLATFORM_NAME diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 770d07003ce60..bdd21cde917cc 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -82,6 +82,7 @@ enum intel_platform { /* gen12 */ INTEL_TIGERLAKE, INTEL_ROCKETLAKE, + INTEL_DG1, INTEL_MAX_PLATFORMS }; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:19 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:19 -0700 Subject: [Intel-gfx] [PATCH v2 11/32] drm/i915/dg1: Add fake PCH In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-12-lucas.demarchi@intel.com> DG1 has the south engine display on the same PCI device. Ideally we could use HAS_PCH_SPLIT(), but that macro is misused all across the code base to rather signify a range of gens. So add a fake one for DG1 to be used where needed. Cc: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/intel_pch.c | 6 ++++++ drivers/gpu/drm/i915/intel_pch.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c index c668e99eb2e46..6c97192e9ca87 100644 --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c @@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) { struct pci_dev *pch = NULL; + /* DG1 has south engine display on the same PCI device */ + if (IS_DG1(dev_priv)) { + dev_priv->pch_type = PCH_DG1; + return; + } + /* * The reason to probe ISA bridge instead of Dev31:Fun0 is to * make graphics device passthrough work easy for VMM, that only diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h index 3053d1ce398b1..06d2cd50af0b9 100644 --- a/drivers/gpu/drm/i915/intel_pch.h +++ b/drivers/gpu/drm/i915/intel_pch.h @@ -26,6 +26,9 @@ enum intel_pch { PCH_JSP, /* Jasper Lake PCH */ PCH_MCC, /* Mule Creek Canyon PCH */ PCH_TGP, /* Tiger Lake PCH */ + + /* Fake PCHs, functionality handled on the same PCI dev */ + PCH_DG1 = 1024, }; #define INTEL_PCH_DEVICE_ID_MASK 0xff80 @@ -56,6 +59,7 @@ enum intel_pch { #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) +#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:20 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:20 -0700 Subject: [Intel-gfx] [PATCH v2 12/32] drm/i915/dg1: Initialize RAWCLK properly In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-13-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz frequencies on CNP+. Note that register bits associated with this frequency confusingly use 37 for the divider field rather than 38 as you might expect. For simplicity, let's just assume that this 38.4 MHz frequency will hold true for other future platforms with "fake" PCH south displays and that the CNP-style behavior will remain for other platforms with a real PCH. Bspec: 49950 Bspec: 49309 Cc: Aditya Swarup <aditya.swarup at intel.com> Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 45f7f33d11447..3aea30ba9f743 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2673,6 +2673,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv) DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); } +static int dg1_rawclk(struct drm_i915_private *dev_priv) +{ + /* + * DG1 always uses a 38.4 MHz rawclk. The bspec tells us + * "Program Numerator=2, Denominator=4, Divider=37 decimal." + */ + I915_WRITE(PCH_RAWCLK_FREQ, + CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); + + return 38400; +} + static int cnp_rawclk(struct drm_i915_private *dev_priv) { u32 rawclk; @@ -2781,7 +2793,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) { u32 freq; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) + if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + freq = dg1_rawclk(dev_priv); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) freq = cnp_rawclk(dev_priv); else if (HAS_PCH_SPLIT(dev_priv)) freq = pch_rawclk(dev_priv); -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:24 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:24 -0700 Subject: [Intel-gfx] [PATCH v2 16/32] drm/i915/dg1: Wait for pcode/uncore handshake at startup In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-17-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> DG1 does some additional pcode/uncore handshaking at boot time; this handshaking must complete before various other pcode commands are effective and before general work is submitted to the GPU. We need to poll a new pcode mailbox during startup until it reports that this handshaking is complete. The bspec doesn't give guidance on how long we may need to wait for this handshaking to complete. For now, let's just set a really long timeout; if we still don't get a completion status by the end of that timeout, we'll just continue on and hope for the best. Bspec: 52065 Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_sideband.h | 2 ++ 4 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 34ee12f3f02d4..58b9c6b778aa4 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -85,6 +85,7 @@ #include "intel_gvt.h" #include "intel_memory_region.h" #include "intel_pm.h" +#include "intel_sideband.h" #include "vlv_suspend.h" static struct drm_driver driver; @@ -741,6 +742,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) */ intel_dram_detect(dev_priv); + intel_pcode_init(dev_priv); + intel_bw_init_hw(dev_priv); return 0; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52cef469b8b7c..cc593c8b43ac3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9164,6 +9164,9 @@ enum { #define GEN9_SAGV_DISABLE 0x0 #define GEN9_SAGV_IS_DISABLED 0x1 #define GEN9_SAGV_ENABLE 0x3 +#define DG1_PCODE_STATUS 0x7E +#define DG1_CHECK_UNCORE_INIT_STATUS 0x0 +#define DG1_UNCORE_INIT_COMPLETE 0x1 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 #define GEN6_PCODE_DATA _MMIO(0x138128) #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index 916ccd1c0e969..8b093525240d6 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request, return ret ? ret : status; #undef COND } + +void intel_pcode_init(struct drm_i915_private *i915) +{ + int ret; + + if (!IS_DGFX(i915)) + return; + + ret = skl_pcode_request(i915, DG1_PCODE_STATUS, + DG1_CHECK_UNCORE_INIT_STATUS, + DG1_UNCORE_INIT_COMPLETE, + DG1_UNCORE_INIT_COMPLETE, 50); + if (ret) + drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n"); +} diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h index 7fb95745a4449..094c7b19c5d42 100644 --- a/drivers/gpu/drm/i915/intel_sideband.h +++ b/drivers/gpu/drm/i915/intel_sideband.h @@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request, u32 reply_mask, u32 reply, int timeout_base_ms); +void intel_pcode_init(struct drm_i915_private *i915); + #endif /* _INTEL_SIDEBAND_H */ -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:12 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:12 -0700 Subject: [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-5-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> RKL and TGL share some general gen12 workarounds, but each platform also has its own platform-specific workarounds. v2: - Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to TGL's, so we'll have both functions call the tgl_ function for now; this workaround isn't listed for DG1 so we don't want to add it to the general gen12_ function. Cc: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++-------- 2 files changed, 59 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3cd461bf91311..63ac79f88fa21 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0] */ - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) + /* Wa_14010477008:tgl[a0..c0],rkl[all] */ + if (IS_ROCKETLAKE(dev_priv) || + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821ddaf..741710ca2b9a5 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); } -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, - struct i915_wa_list *wal) +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) { /* * Wa_1409142259:tgl @@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, * Wa_1409207793:tgl * Wa_1409178076:tgl * Wa_1408979724:tgl + * Wa_14010443199:rkl + * Wa_14010698770:rkl */ WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); + /* WaDisableGPGPUMidThreadPreemption:gen12 */ + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, + GEN9_PREEMPT_GPGPU_LEVEL_MASK, + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); +} + +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + /* - * Wa_1604555607:gen12 and Wa_1608008084:gen12 + * Wa_1604555607:tgl,rkl + * + * Note that the implementation of this workaround is further modified + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. * FF_MODE2 register will return the wrong value when read. The default * value for this register is zero for all fields and there are no bit * masks. So instead of doing a RMW we should just write the GS Timer @@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, 0); - - /* WaDisableGPGPUMidThreadPreemption:tgl */ - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, - GEN9_PREEMPT_GPGPU_LEVEL_MASK, - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); } static void @@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_GEN(i915, 12)) + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); + else if (IS_GEN(i915, 12)) + gen12_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 11)) icl_ctx_workarounds_init(engine, wal); else if (IS_CANNONLAKE(i915)) @@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) } static void -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +gen12_gt_workarounds_init(struct drm_i915_private *i915, + struct i915_wa_list *wal) { wa_init_mcr(i915, wal); +} + +static void +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) @@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_GEN(i915, 12)) + if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); + else if (IS_GEN(i915, 12)) + gen12_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 11)) icl_gt_workarounds_init(i915, wal); else if (IS_CANNONLAKE(i915)) @@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); - /* - * Wa_1607030317:tgl - * Wa_1607186500:tgl - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 - * of then says it is fixed on B0 the other one says it is - * permanent - */ - wa_masked_en(wal, - GEN6_RC_SLEEP_PSMI_CONTROL, - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | - GEN8_RC_SEMA_IDLE_MSG_DISABLE); - /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) VSUNIT_CLKGATE_DIS_TGL); } - if (IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl */ + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); - /* Wa_1409804808:tgl */ + /* Wa_1409804808:tgl,rkl */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); - /* Wa_1606700617:tgl */ - wa_masked_en(wal, - GEN9_CS_DEBUG_MODE1, - FF_DOP_CLOCK_GATE_DISABLE); - /* * Wa_1409085225:tgl - * Wa_14010229206:tgl + * Wa_14010229206:tgl,rkl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); + + /* + * Wa_1607030317:tgl + * Wa_1607186500:tgl + * Wa_1607297627:tgl,rkl there are multiple entries for this + * WA in the BSpec; some indicate this is an A0-only WA, + * others indicate it applies to all steppings. + */ + wa_masked_en(wal, + GEN6_RC_SLEEP_PSMI_CONTROL, + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + } + + if (IS_TIGERLAKE(i915)) { + /* Wa_1606700617:tgl */ + wa_masked_en(wal, + GEN9_CS_DEBUG_MODE1, + FF_DOP_CLOCK_GATE_DISABLE); } if (IS_GEN(i915, 11)) { -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:13 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:13 -0700 Subject: [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-6-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> After doing normal PHY-B initialization on Rocket Lake, we need to manually copy some additional PHY-A register values into PHY-B registers. Note that the bspec's combo phy page doesn't specify that this workaround is restricted to specific platform steppings (and doesn't even do a very good job of specifying that RKL is the only platform this is needed on), but the RKL workaround page lists this as relevant only for A and B steppings, so I'm trusting that information for now. v2: Make rkl_combo_phy_b_init_wa() static Bspec: 49291 Bspec: 53273 Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 26 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec624..d5d95e2746c2c 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -338,6 +338,27 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); } +static void rkl_combo_phy_b_init_wa(struct drm_i915_private *i915) +{ + u32 grccode, grccode_ldo; + u32 iref_rcal_ord, rcompcode_ld_cap_ov; + + intel_de_wait_for_register(i915, ICL_PORT_COMP_DW3(PHY_A), + FIRST_COMP_DONE, FIRST_COMP_DONE, 100); + + grccode = REG_FIELD_GET(GRCCODE, + intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A))); + iref_rcal_ord = REG_FIELD_PREP(IREF_RCAL_ORD, grccode); + intel_de_rmw(i915, ICL_PORT_COMP_DW2(PHY_B), IREF_RCAL_ORD, + iref_rcal_ord | IREF_RCAL_ORD_EN); + + grccode_ldo = REG_FIELD_GET(GRCCODE_LDO, + intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A))); + rcompcode_ld_cap_ov = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode_ldo); + intel_de_rmw(i915, ICL_PORT_COMP_DW6(PHY_B), RCOMPCODE_LD_CAP_OV, + rcompcode_ld_cap_ov | RCOMPCODEOVEN_LDO_SYNC); +} + static void icl_combo_phys_init(struct drm_i915_private *dev_priv) { enum phy phy; @@ -390,6 +411,11 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); + + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && + phy == PHY_B) + /* Wa_14011224835:rkl[a0..c0] */ + rkl_combo_phy_b_init_wa(dev_priv); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 34b2ec04ccd86..10f6e46523b6e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1908,11 +1908,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CNL_PORT_COMP_DW0 _MMIO(0x162100) #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) -#define COMP_INIT (1 << 31) +#define COMP_INIT REG_BIT(31) +#define GRCCODE_LDO REG_GENMASK(7, 0) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) +#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy)) +#define IREF_RCAL_ORD_EN REG_BIT(7) +#define IREF_RCAL_ORD REG_GENMASK(6, 0) + #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) @@ -1925,6 +1930,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VOLTAGE_INFO_1_05V (2 << 24) #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 +#define FIRST_COMP_DONE REG_BIT(22) + +#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy)) +#define GRCCODE REG_GENMASK(30, 24) +#define RCOMPCODEOVEN_LDO_SYNC REG_BIT(23) +#define RCOMPCODE_LD_CAP_OV REG_GENMASK(22, 16) #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24) -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:17 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:17 -0700 Subject: [Intel-gfx] [PATCH v2 09/32] drm/i915/dg1: add support for the master unit interrupt In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-10-lucas.demarchi@intel.com> DG1 has master unit interrupt register which is used to indicate the correct source of interrupt. v2: fix coding style on register definition Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com> Cc: Daniele Spurio Ceraolo <daniele.ceraolospurio at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 4 +++ drivers/gpu/drm/i915/i915_irq.c | 56 +++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 4 +++ 3 files changed, 61 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bca036ac66212..4e13f7d7dc5de 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -492,6 +492,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data) seq_printf(m, "PCU interrupt enable:\t%08x\n", I915_READ(GEN8_PCU_IER)); } else if (INTEL_GEN(dev_priv) >= 11) { + if (HAS_MASTER_UNIT_IRQ(dev_priv)) + seq_printf(m, "Master Unit Interrupt Control: %08x\n", + I915_READ(DG1_MSTR_UNIT_INTR)); + seq_printf(m, "Master Interrupt Control: %08x\n", I915_READ(GEN11_GFX_MSTR_IRQ)); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 710224d930c53..8652e1e69db72 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2584,6 +2584,46 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg) gen11_master_intr_enable); } +static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs) +{ + u32 val; + + /* First disable interrupts */ + raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0); + + /* Get the indication levels and ack the master unit */ + val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR); + if (unlikely(!val)) + return 0; + + raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val); + + /* + * Now with master disabled, get a sample of level indications + * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ + * out as this bit doesn't exist anymore for DG1 + */ + val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ; + if (unlikely(!val)) + return 0; + + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val); + + return val; +} + +static inline void dg1_master_intr_enable(void __iomem * const regs) +{ + raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ); +} + +static irqreturn_t dg1_irq_handler(int irq, void *arg) +{ + return __gen11_irq_handler(arg, + dg1_master_intr_disable_and_ack, + dg1_master_intr_enable); +} + /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */ @@ -2922,7 +2962,10 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; - gen11_master_intr_disable(dev_priv->uncore.regs); + if (HAS_MASTER_UNIT_IRQ(dev_priv)) + dg1_master_intr_disable_and_ack(dev_priv->uncore.regs); + else + gen11_master_intr_disable(dev_priv->uncore.regs); gen11_gt_irq_reset(&dev_priv->gt); gen11_display_irq_reset(dev_priv); @@ -3519,8 +3562,13 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); - gen11_master_intr_enable(uncore->regs); - POSTING_READ(GEN11_GFX_MSTR_IRQ); + if (HAS_MASTER_UNIT_IRQ(dev_priv)) { + dg1_master_intr_enable(uncore->regs); + POSTING_READ(DG1_MSTR_UNIT_INTR); + } else { + gen11_master_intr_enable(uncore->regs); + POSTING_READ(GEN11_GFX_MSTR_IRQ); + } } static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) @@ -4045,6 +4093,8 @@ static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) else return i8xx_irq_handler; } else { + if (HAS_MASTER_UNIT_IRQ(dev_priv)) + return dg1_irq_handler; if (INTEL_GEN(dev_priv) >= 11) return gen11_irq_handler; else if (INTEL_GEN(dev_priv) >= 8) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 10f6e46523b6e..52cef469b8b7c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7678,6 +7678,10 @@ enum { #define GEN11_GT_DW1_IRQ (1 << 1) #define GEN11_GT_DW0_IRQ (1 << 0) +#define DG1_MSTR_UNIT_INTR _MMIO(0x190008) +#define DG1_MSTR_IRQ REG_BIT(31) +#define DG1_MSTR_UNIT(u) REG_BIT(u) + #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) #define GEN11_AUDIO_CODEC_IRQ (1 << 24) -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:26 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:26 -0700 Subject: [Intel-gfx] [PATCH v2 18/32] drm/i915/dg1: Add and setup DPLLs for DG1 In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-19-lucas.demarchi@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks. Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1. Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++++++++-- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6f59f9ec453bf..ed2d007d2687e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3527,7 +3527,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, return false; } - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + if (port == PORT_D || port == PORT_E) { + dpll_mask = + BIT(DPLL_ID_DG1_DPLL2) | + BIT(DPLL_ID_DG1_DPLL3); + } else { + dpll_mask = + BIT(DPLL_ID_DG1_DPLL0) | + BIT(DPLL_ID_DG1_DPLL1); + } + } else if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | @@ -3817,7 +3827,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!(val & PLL_ENABLE)) goto out; - if (INTEL_GEN(dev_priv) >= 12) { + if (IS_DG1(dev_priv)) { + hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id)); + } else if (INTEL_GEN(dev_priv) >= 12) { hw_state->cfgcr0 = intel_de_read(dev_priv, TGL_DPLL_CFGCR0(id)); hw_state->cfgcr1 = intel_de_read(dev_priv, @@ -3870,7 +3883,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; i915_reg_t cfgcr0_reg, cfgcr1_reg; - if (INTEL_GEN(dev_priv) >= 12) { + if (IS_DG1(dev_priv)) { + cfgcr0_reg = DG1_DPLL_CFGCR0(id); + cfgcr1_reg = DG1_DPLL_CFGCR1(id); + } else if (INTEL_GEN(dev_priv) >= 12) { cfgcr0_reg = TGL_DPLL_CFGCR0(id); cfgcr1_reg = TGL_DPLL_CFGCR1(id); } else { @@ -4317,6 +4333,21 @@ static const struct intel_dpll_mgr rkl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info dg1_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 }, + { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 }, + { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 }, + { }, +}; + +static const struct intel_dpll_mgr dg1_pll_mgr = { + .dpll_info = dg1_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4330,7 +4361,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (IS_ROCKETLAKE(dev_priv)) + if (IS_DG1(dev_priv)) + dpll_mgr = &dg1_pll_mgr; + else if (IS_ROCKETLAKE(dev_priv)) dpll_mgr = &rkl_pll_mgr; else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:27 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:27 -0700 Subject: [Intel-gfx] [PATCH v2 19/32] drm/i915/dg1: Enable DPLL for DG1 In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-20-lucas.demarchi@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> Add DG1 DPLL Enable register macro and use the macro to enable the correct DPLL based on PLL id. Bspec: 49443, 49206 Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ++++++++++++------- drivers/gpu/drm/i915/i915_reg.h | 4 +++ 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index ed2d007d2687e..7035280e2e9ea 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3859,12 +3859,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + i915_reg_t enable_reg; - if (IS_ELKHARTLAKE(dev_priv) && - pll->info->id == DPLL_ID_EHL_DPLL4) { + if (IS_DG1(dev_priv)) + enable_reg = DG1_DPLL_ENABLE(pll->info->id); + else if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4) enable_reg = MG_PLL_ENABLE(0); - } + else + enable_reg = CNL_DPLL_ENABLE(pll->info->id); return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); } @@ -4062,10 +4064,12 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, static void combo_pll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + i915_reg_t enable_reg; - if (IS_ELKHARTLAKE(dev_priv) && - pll->info->id == DPLL_ID_EHL_DPLL4) { + if (IS_DG1(dev_priv)) { + enable_reg = DG1_DPLL_ENABLE(pll->info->id); + } else if (IS_ELKHARTLAKE(dev_priv) && + pll->info->id == DPLL_ID_EHL_DPLL4) { enable_reg = MG_PLL_ENABLE(0); /* @@ -4075,6 +4079,8 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, */ pll->wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DPLL_DC_OFF); + } else { + enable_reg = CNL_DPLL_ENABLE(pll->info->id); } icl_pll_power_enable(dev_priv, pll, enable_reg); @@ -4174,16 +4180,20 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, static void combo_pll_disable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + i915_reg_t enable_reg; - if (IS_ELKHARTLAKE(dev_priv) && - pll->info->id == DPLL_ID_EHL_DPLL4) { + if (IS_DG1(dev_priv)) { + enable_reg = DG1_DPLL_ENABLE(pll->info->id); + } else if (IS_ELKHARTLAKE(dev_priv) && + pll->info->id == DPLL_ID_EHL_DPLL4) { enable_reg = MG_PLL_ENABLE(0); icl_pll_disable(dev_priv, pll, enable_reg); intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF, pll->wakeref); return; + } else { + enable_reg = CNL_DPLL_ENABLE(pll->info->id); } icl_pll_disable(dev_priv, pll, enable_reg); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7519371a5144e..6649aeca25d72 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10251,6 +10251,10 @@ enum skl_power_gate { #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ _MG_PLL2_ENABLE) +/* DG1 PLL */ +#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ + _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) + #define _MG_REFCLKIN_CTL_PORT1 0x16892C #define _MG_REFCLKIN_CTL_PORT2 0x16992C #define _MG_REFCLKIN_CTL_PORT3 0x16A92C -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:28 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:28 -0700 Subject: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-21-lucas.demarchi@intel.com> DG1 has one more combo phy port, no TC and all irq handling goes through SDE, like for MCC. Cc: Anshuman Gupta <anshuman.gupta at intel.com> Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 8 +++++ 2 files changed, 59 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 48e1686df3416..3707f9231171f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), }; +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = { + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A), + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B), + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C), + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D), +}; + static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) { struct i915_hotplug *hpd = &dev_priv->hotplug; @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) else hpd->hpd = hpd_ilk; - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) return; - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) + if (HAS_PCH_DG1(dev_priv)) + hpd->pch_hpd = hpd_dg1_sde; + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) hpd->pch_hpd = hpd_tgp; else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) hpd->pch_hpd = hpd_icp; @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) } } +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) +{ + switch (pin) { + case HPD_PORT_A: + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A); + case HPD_PORT_B: + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B); + case HPD_PORT_D: + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C); + case HPD_PORT_E: + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D); + default: + return false; + } +} + static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) u32 ddi_hotplug_trigger, tc_hotplug_trigger; u32 pin_mask = 0, long_mask = 0; bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); - if (HAS_PCH_TGP(dev_priv)) { + if (HAS_PCH_DG1(dev_priv)) { + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1; + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect; + tc_hotplug_trigger = 0; + } else if (HAS_PCH_TGP(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; } else if (HAS_PCH_JSP(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; tc_hotplug_trigger = 0; } else if (HAS_PCH_MCC(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) INTEL_PCH_TYPE(dev_priv)); ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; } @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, ddi_hotplug_trigger, dig_hotplug_reg, dev_priv->hotplug.pch_hpd, - icp_ddi_port_hotplug_long_detect); + ddi_port_hotplug_long_detect); } if (tc_hotplug_trigger) { @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) TGP_DDI_HPD_ENABLE_MASK, 0); } +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) +{ + icp_hpd_irq_setup(dev_priv, + SDE_DDI_MASK_DG1, 0, + DG1_DDI_HPD_ENABLE_MASK, 0); +} + static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); I915_WRITE(SDEIMR, ~mask); - if (HAS_PCH_TGP(dev_priv)) + if (HAS_PCH_DG1(dev_priv)) + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0); + else if (HAS_PCH_TGP(dev_priv)) icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK); else if (HAS_PCH_JSP(dev_priv)) @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (I915_HAS_HOTPLUG(dev_priv)) dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; } else { - if (HAS_PCH_JSP(dev_priv)) + if (HAS_PCH_DG1(dev_priv)) + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; + else if (HAS_PCH_JSP(dev_priv)) dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; else if (HAS_PCH_MCC(dev_priv)) dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6649aeca25d72..13a989f5e8dd3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8168,6 +8168,10 @@ enum { SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ SDE_TC_HOTPLUG_ICP(PORT_TC1)) +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \ + SDE_DDI_HOTPLUG_ICP(PORT_C) | \ + SDE_DDI_HOTPLUG_ICP(PORT_B) | \ + SDE_DDI_HOTPLUG_ICP(PORT_A)) #define SDEISR _MMIO(0xc4000) #define SDEIMR _MMIO(0xc4004) @@ -8367,6 +8371,10 @@ enum { #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ ICP_TC_HPD_ENABLE(PORT_TC5) | \ ICP_TC_HPD_ENABLE_MASK) +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \ + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) #define _PCH_DPLL_A 0xc6014 #define _PCH_DPLL_B 0xc6018 -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:29 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:29 -0700 Subject: [Intel-gfx] [PATCH v2 21/32] drm/i915/dg1: invert HPD pins In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-22-lucas.demarchi@intel.com> From: Clinton A Taylor <clinton.a.taylor at intel.com> HPD pins are inverted for DG1 platform. Bspec: 49956 Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Clinton A Taylor <clinton.a.taylor at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 3707f9231171f..4fd667bc88c2e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3183,6 +3183,10 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) { + intel_de_rmw(dev_priv, SOUTH_CHICKEN1, 0, + INVERT_DDIA_HPD | INVERT_DDIB_HPD | + INVERT_DDIC_HPD | INVERT_DDID_HPD); + icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_DG1, 0, DG1_DDI_HPD_ENABLE_MASK, 0); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 13a989f5e8dd3..3f9a10dd5be27 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8635,6 +8635,10 @@ enum { #define SOUTH_CHICKEN1 _MMIO(0xc2000) #define FDIA_PHASE_SYNC_SHIFT_OVR 19 #define FDIA_PHASE_SYNC_SHIFT_EN 18 +#define INVERT_DDID_HPD (1 << 18) +#define INVERT_DDIC_HPD (1 << 17) +#define INVERT_DDIB_HPD (1 << 16) +#define INVERT_DDIA_HPD (1 << 15) #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) #define FDI_BC_BIFURCATION_SELECT (1 << 12) -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:30 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:30 -0700 Subject: [Intel-gfx] [PATCH v2 22/32] drm/i915/dg1: gmbus pin mapping In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-23-lucas.demarchi@intel.com> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. The values for VBT are currently not in BSpec. If we assume the latest is ICL (like we did for TGL), then the mapping is wrong per VBT we can currently parse. >From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9 mapping as in ICL/TGL. BSpec: 49311, 49945, 20124 Cc: Aditya Swarup <aditya.swarup at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 4 +++- drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 9 ++++++++- 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index c974c716f8593..308160f015186 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1599,7 +1599,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) const u8 *ddc_pin_map; int n_entries; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { + if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) { + return vbt_pin; + } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { ddc_pin_map = icp_ddc_pin_map; n_entries = ARRAY_SIZE(icp_ddc_pin_map); } else if (HAS_PCH_CNP(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index a8d119b6b45c8..528e48658340c 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = { [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, }; +static const struct gmbus_pin gmbus_pins_dg1[] = { + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, +}; + /* pin is expected to be valid */ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, unsigned int pin) { - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + return &gmbus_pins_dg1[pin]; + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) return &gmbus_pins_icp[pin]; else if (HAS_PCH_CNP(dev_priv)) return &gmbus_pins_cnp[pin]; @@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, { unsigned int size; - if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + size = ARRAY_SIZE(gmbus_pins_dg1); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) size = ARRAY_SIZE(gmbus_pins_icp); else if (HAS_PCH_CNP(dev_priv)) size = ARRAY_SIZE(gmbus_pins_cnp); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a31a98d268823..34f133e2a90db 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3100,6 +3100,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) return GMBUS_PIN_1_BXT + phy; } +static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) +{ + return intel_port_to_phy(dev_priv, port) + 1; +} + static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) { @@ -3137,7 +3142,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) return ddc_pin; } - if (IS_ROCKETLAKE(dev_priv)) + if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); + else if (IS_ROCKETLAKE(dev_priv)) ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); else if (HAS_PCH_MCC(dev_priv)) ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:31 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:31 -0700 Subject: [Intel-gfx] [PATCH v2 23/32] drm/i915/dg1: Enable first 2 ports for DG1 In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-24-lucas.demarchi@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> Enable PORTS A and B for DG1 initially, the other ports still need more plumbing code in order to be enabled. Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f16512eddc587..58c08ec0298a0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7219,6 +7219,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { if (phy == PHY_NONE) return false; + else if (IS_DG1(dev_priv)) + /* FIXME: Enable only two ports for now */ + return phy <= PHY_B; else if (IS_ROCKETLAKE(dev_priv)) return phy <= PHY_D; else if (IS_ELKHARTLAKE(dev_priv)) @@ -7231,7 +7234,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { - if (IS_ROCKETLAKE(dev_priv)) + if (IS_ROCKETLAKE(dev_priv) || IS_DG1(dev_priv)) return false; else if (INTEL_GEN(dev_priv) >= 12) return phy >= PHY_D && phy <= PHY_I; @@ -16832,7 +16835,11 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) return; - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + /* FIXME: Enable only two ports for now */ + intel_ddi_init(dev_priv, PORT_A); + intel_ddi_init(dev_priv, PORT_B); + } else if (IS_ROCKETLAKE(dev_priv)) { /* * If HTI (aka HDPORT) is enabled at boot, it may have taken * over some of the PHYs and made them unavailable to the -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:32 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:32 -0700 Subject: [Intel-gfx] [PATCH v2 24/32] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-25-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec details for that bit tell us that it need only be set for PHY-A and PHY-B. It also turns out that there isn't even an instance of the PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL logic that conditionally skips PHY_MISC usage to DG1 as well. Bspec: 50107 Cc: Aditya Swarup <aditya.swarup at intel.com> Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index d5d95e2746c2c..336d18f3d1c52 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) * other combo PHY's. */ if (IS_ELKHARTLAKE(i915) || - IS_ROCKETLAKE(i915)) + IS_ROCKETLAKE(i915) || + IS_DG1(i915)) return phy < PHY_C; return true; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:33 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:33 -0700 Subject: [Intel-gfx] [PATCH v2 25/32] drm/i915/dg1: Update comp master/slave relationships for PHYs In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-26-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> As with RKL, DG1's PHY C acts as a comp master for PHY D. Bspec: 49291 Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 336d18f3d1c52..ba6a21c5ef15d 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) * * ICL,TGL: * A(master) -> B(slave), C(slave) - * RKL: + * RKL,DG1: * A(master) -> B(slave) * C(master) -> D(slave) * * We must set the IREFGEN bit for any PHY acting as a master * to another PHY. */ - if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C) + if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C) return true; return phy == PHY_A; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:34 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:34 -0700 Subject: [Intel-gfx] [PATCH v2 26/32] drm/i915/dg1: Update voltage swing tables for DP In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-27-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> DG1's vswing tables are the same for eDP and HDMI but have slight differences from ICL/TGL for DP. Bspec: 49291 Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8790f221dc77c..f500c9677b278 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; +static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = { + /* NT mV Trans mV db */ + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ + { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ + { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ + { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ + { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ + { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +}; + +static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = { + /* NT mV Trans mV db */ + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ + { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */ + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ + { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ + { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ + { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ + { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +}; + struct icl_mg_phy_ddi_buf_trans { u32 cri_txdeemph_override_11_6; u32 cri_txdeemph_override_5_0; @@ -993,6 +1021,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); return icl_combo_phy_ddi_translations_edp_hbr2; + } else if (IS_DG1(dev_priv) && rate > 270000) { + *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2); + return dg1_combo_phy_ddi_translations_dp_hbr2; + } else if (IS_DG1(dev_priv)) { + *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr); + return dg1_combo_phy_ddi_translations_dp_hbr; } *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:36 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:36 -0700 Subject: [Intel-gfx] [PATCH v2 28/32] drm/i915/dg1: map/unmap pll clocks In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-29-lucas.demarchi@intel.com> DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a single macro that chooses the correct register according to the phy being accessed, use the correct bitfields for each pll/phy and implement separate functions for DG1 since it doesn't share much with ICL/TGL anymore. The previous values were correct for PHY A and B since they were using the same register as before and the bitfields were matching. Cc: Jos? Roberto de Souza <jose.souza at intel.com> Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 92 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_display.c | 25 +++++- drivers/gpu/drm/i915/i915_reg.h | 15 ++++ 3 files changed, 128 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f500c9677b278..85052328a59a2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2818,6 +2818,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, return 0; } +static void dg1_map_plls_to_ports(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_shared_dpll *pll = crtc_state->shared_dpll; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + u32 val; + + /* + * If we fail this, something went very wrong: first 2 PLLs should be + * used by first 2 phys and last 2 PLLs by last phys + */ + if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || + (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) + return; + + mutex_lock(&dev_priv->dpll.lock); + + val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); + WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0); + + val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); + intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); + + val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); + + mutex_unlock(&dev_priv->dpll.lock); +} + static void icl_map_plls_to_ports(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -2865,6 +2897,19 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, mutex_unlock(&dev_priv->dpll.lock); } +static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + + mutex_lock(&dev_priv->dpll.lock); + + intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0, + DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); + + mutex_unlock(&dev_priv->dpll.lock); +} + static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -2880,6 +2925,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) mutex_unlock(&dev_priv->dpll.lock); } +static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv, + u32 port_mask, bool ddi_clk_needed) +{ + enum port port; + u32 val; + + for_each_port_masked(port, port_mask) { + enum phy phy = intel_port_to_phy(dev_priv, port); + bool ddi_clk_off; + + val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)); + ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + + if (ddi_clk_needed == !ddi_clk_off) + continue; + + /* + * Punt on the case now where clock is gated, but it would + * be needed by the port. Something else is really broken then. + */ + if (ddi_clk_needed) { + WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n", + ddi_clk_needed, ddi_clk_off, phy); + continue; + } + + DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", + phy_name(phy)); + + val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); + intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val); + } +} + static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, u32 port_mask, bool ddi_clk_needed) { @@ -2962,7 +3041,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) ddi_clk_needed = false; } - icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); + if (IS_DG1(dev_priv)) + dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); + else + icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); } static void intel_ddi_clk_select(struct intel_encoder *encoder, @@ -3488,7 +3570,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); - if (INTEL_GEN(dev_priv) >= 11) + if (IS_DG1(dev_priv)) + dg1_map_plls_to_ports(encoder, crtc_state); + else if (INTEL_GEN(dev_priv) >= 11) icl_map_plls_to_ports(encoder, crtc_state); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); @@ -3674,7 +3758,9 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, intel_ddi_post_disable_dp(state, encoder, old_crtc_state, old_conn_state); - if (INTEL_GEN(dev_priv) >= 11) + if (IS_DG1(dev_priv)) + dg1_unmap_plls_to_ports(encoder); + else if (INTEL_GEN(dev_priv) >= 11) icl_unmap_plls_to_ports(encoder); if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 58c08ec0298a0..4b5d6c7c5782d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10765,6 +10765,27 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc, return 0; } +static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, + struct intel_crtc_state *pipe_config) +{ + enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; + enum phy phy = intel_port_to_phy(dev_priv, port); + enum intel_dpll_id id; + u32 val; + + val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy)) + & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); + id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy); + + if (WARN_ON(id > DPLL_ID_DG1_DPLL3)) + return; + + pipe_config->icl_port_dplls[port_dpll_id].pll = + intel_get_shared_dpll_by_id(dev_priv, id); + + icl_set_active_port_dpll(pipe_config, port_dpll_id); +} + static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) { @@ -11073,7 +11094,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc, port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); } - if (INTEL_GEN(dev_priv) >= 11) + if (IS_DG1(dev_priv)) + dg1_get_ddi_pll(dev_priv, port, pipe_config); + else if (INTEL_GEN(dev_priv) >= 11) icl_get_ddi_pll(dev_priv, port, pipe_config); else if (IS_CANNONLAKE(dev_priv)) cnl_get_ddi_pll(dev_priv, port, pipe_config); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3f9a10dd5be27..34ed419283a70 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) #define _PORT(port, a, b) _PICK_EVEN(port, a, b) #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) +#define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) +#define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) @@ -10229,6 +10231,7 @@ enum skl_power_gate { #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) +/* ICL Clocks */ #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) @@ -10244,6 +10247,18 @@ enum skl_power_gate { #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) +/* DG1 Clocks */ +#define _DG1_DPCLKA_CFGCR0 0x164280 +#define _DG1_DPCLKA1_CFGCR0 0x16C280 +#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ + _DG1_DPCLKA_CFGCR0, \ + _DG1_DPCLKA1_CFGCR0) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << (10 + ((phy) % 2))) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << (((phy) % 2) * 2)) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (((pll) % 2) << (((phy) % 2)) * 2) +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \ + ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2))) + /* CNL PLL */ #define DPLL0_ENABLE 0x46010 #define DPLL1_ENABLE 0x46014 -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:35 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:35 -0700 Subject: [Intel-gfx] [PATCH v2 27/32] drm/i915/dg1: provide port/phy mapping for vbt In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-28-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> As with RKL, DG1's VBT outputs are indexed according to PHY rather than DDI. Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 308160f015186..064c74f70a58b 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1670,7 +1670,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, }; - if (IS_ROCKETLAKE(dev_priv)) + if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), ARRAY_SIZE(rkl_port_mapping[0]), rkl_port_mapping, @@ -2635,10 +2635,12 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, aux_ch = AUX_CH_B; break; case DP_AUX_C: - aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C; + aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? + AUX_CH_D : AUX_CH_C; break; case DP_AUX_D: - aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D; + aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ? + AUX_CH_E : AUX_CH_D; break; case DP_AUX_E: aux_ch = AUX_CH_E; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:37 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:37 -0700 Subject: [Intel-gfx] [PATCH v2 29/32] drm/i915/dg1: enable PORT C/D aka D/E In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-30-lucas.demarchi@intel.com> For DG1 we have a little of mix up wrt to DDI/port names and indexes. Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2 (besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the most unambiguous one. This means that for any register on Display Engine we should use the index of A, B, D and E. However in some places this is not true: - VBT: uses C and D and have to be mapped to D/E - IO/Combo: uses C and D, but we already differentiate those when we created the phy vs port distinction. Ths additional mapping for VBT and phy are already covered in previous patches, so now we can initialize the DDI as D/E. Cc: Clinton Taylor <Clinton.A.Taylor at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4b5d6c7c5782d..2a345be705e65 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7219,10 +7219,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) { if (phy == PHY_NONE) return false; - else if (IS_DG1(dev_priv)) - /* FIXME: Enable only two ports for now */ - return phy <= PHY_B; - else if (IS_ROCKETLAKE(dev_priv)) + else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) return phy <= PHY_D; else if (IS_ELKHARTLAKE(dev_priv)) return phy <= PHY_C; @@ -7246,7 +7243,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) { - if (IS_ROCKETLAKE(i915) && port >= PORT_D) + if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_D) return (enum phy)port - 1; else if (IS_ELKHARTLAKE(i915) && port == PORT_D) return PHY_A; @@ -16859,9 +16856,18 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_DG1(dev_priv)) { - /* FIXME: Enable only two ports for now */ intel_ddi_init(dev_priv, PORT_A); intel_ddi_init(dev_priv, PORT_B); + + /* + * Bspec lists the ports as A, B, C (USBC1) and D (USBC2). + * However from the Display Engine perspective all registers are + * actually wired to handle C and D as offsets of D/E. Instead + * of fighting all our macros for handling them specially for + * DG1, just call them D/E + */ + intel_ddi_init(dev_priv, PORT_D); + intel_ddi_init(dev_priv, PORT_E); } else if (IS_ROCKETLAKE(dev_priv)) { /* * If HTI (aka HDPORT) is enabled at boot, it may have taken -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:16 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:16 -0700 Subject: [Intel-gfx] [PATCH v2 08/32] drm/i915/dg1: Add DG1 PCI IDs In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-9-lucas.demarchi@intel.com> From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> Bspec: 44463 Cc: Matthew Auld <matthew.auld at intel.com> Cc: James Ausmus <james.ausmus at intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/i915_pci.c | 3 ++- include/drm/i915_pciids.h | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 58cceeaa0ffa5..8d5b23946d7dd 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -900,7 +900,7 @@ static const struct intel_device_info rkl_info = { .has_master_unit_irq = 1, \ .is_dgfx = 1 -static const struct intel_device_info intel_dg1_info = { +static const struct intel_device_info dg1_info = { GEN12_DGFX_FEATURES, PLATFORM(INTEL_DG1), .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), @@ -985,6 +985,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_EHL_IDS(&ehl_info), INTEL_TGL_12_IDS(&tgl_info), INTEL_RKL_IDS(&rkl_info), + INTEL_DG1_IDS(&dg1_info), {0, 0, 0} }; MODULE_DEVICE_TABLE(pci, pciidlist); diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index bc989de2aac2b..f44fe822880d2 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -614,4 +614,8 @@ INTEL_VGA_DEVICE(0x4C90, info), \ INTEL_VGA_DEVICE(0x4C9A, info) +/* DG1 */ +#define INTEL_DG1_IDS(info) \ + INTEL_VGA_DEVICE(0x4905, info) + #endif /* _I915_PCIIDS_H */ -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:23 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:23 -0700 Subject: [Intel-gfx] [PATCH v2 15/32] drm/i915/dg1: Increase mmio size to 4MB In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-16-lucas.demarchi@intel.com> From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> On dgfx register range has been extended to go up to 4MB. Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 7d6b9ae7403cb..ed56608ae925a 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1699,11 +1699,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore) * clobbering the GTT which we want ioremap_wc instead. Fortunately, * the register BAR remains the same size for all the earlier * generations up to Ironlake. + * For dgfx chips register range is expanded to 4MB. */ if (INTEL_GEN(i915) < 5) mmio_size = 512 * 1024; + else if (IS_DGFX(i915)) + mmio_size = 4 * 1024 * 1024; else mmio_size = 2 * 1024 * 1024; + uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); if (uncore->regs == NULL) { drm_err(&i915->drm, "failed to map registers\n"); -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:25 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:25 -0700 Subject: [Intel-gfx] [PATCH v2 17/32] drm/i915/dg1: Add DPLL macros for DG1 In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-18-lucas.demarchi@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and DPLL2 and DPLL3 drive DDIC/DDID. Introduce DG1_DPLL_CFCRx() helper macros to configure DPLL registers. Bspec: 50288, 50299 Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index edcc43f4670ff..325d22bf7b9ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -154,6 +154,23 @@ enum intel_dpll_id { * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) */ DPLL_ID_TGL_MGPLL6, + + /** + * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0 + */ + DPLL_ID_DG1_DPLL0 = 0, + /** + * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1 + */ + DPLL_ID_DG1_DPLL1, + /** + * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2 + */ + DPLL_ID_DG1_DPLL2, + /** + * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3 + */ + DPLL_ID_DG1_DPLL3, }; #define I915_NUM_PLLS 9 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cc593c8b43ac3..7519371a5144e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) +#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) /* * Device info offset array based helpers for groups of registers with unevenly @@ -10458,6 +10459,20 @@ enum skl_power_gate { #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ _TGL_DPLL1_CFGCR1) +#define _DG1_DPLL2_CFGCR0 0x16C284 +#define _DG1_DPLL3_CFGCR0 0x16C28C +#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ + _TGL_DPLL1_CFGCR0, \ + _DG1_DPLL2_CFGCR0, \ + _DG1_DPLL3_CFGCR0) + +#define _DG1_DPLL2_CFGCR1 0x16C288 +#define _DG1_DPLL3_CFGCR1 0x16C290 +#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ + _TGL_DPLL1_CFGCR1, \ + _DG1_DPLL2_CFGCR1, \ + _DG1_DPLL3_CFGCR1) + #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000 #define _DKL_PHY3_BASE 0x16A000 -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:10 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:10 -0700 Subject: [Intel-gfx] [PATCH v2 02/32] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-3-lucas.demarchi@intel.com> From: Matt Roper <matthew.d.roper at intel.com> Rocket Lake has a third DPLL (called 'DPLL4') that must be used to enable a third display. Unlike EHL's variant of DPLL4, the RKL variant behaves the same as DPLL0/1. And despite its name, the DPLL4 registers are offset as if it were DPLL2. To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT. This means just renumbering TBT to be ID '3' rather than being another ID '2' like DPLL4. With this change, we can build our register selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register offsets are evenly-spaced. MGPLL's don't need any specific ID's (they're just used to translate back to a tc_port), so we let them float at the top of the enum. v2: - Add new .update_ref_clks() hook. v3: - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas) Bspec: 49202 Bspec: 49443 Bspec: 50288 Bspec: 50289 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++----- drivers/gpu/drm/i915/i915_reg.h | 15 +++------- 3 files changed, 37 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b45185b80bec5..b5f4d4cef682b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, return false; } - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) + if (IS_ROCKETLAKE(dev_priv)) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - else + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { + dpll_mask = + BIT(DPLL_ID_EHL_DPLL4) | + BIT(DPLL_ID_ICL_DPLL1) | + BIT(DPLL_ID_ICL_DPLL0); + } else { dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); + } port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { .dump_hw_state = icl_dump_hw_state, }; +static const struct dpll_info rkl_plls[] = { + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, + { }, +}; + +static const struct intel_dpll_mgr rkl_pll_mgr = { + .dpll_info = rkl_plls, + .get_dplls = icl_get_dplls, + .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = icl_dump_hw_state, +}; + /** * intel_shared_dpll_init - Initialize shared DPLLs * @dev: drm device @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) const struct dpll_info *dpll_info; int i; - if (INTEL_GEN(dev_priv) >= 12) + if (IS_ROCKETLAKE(dev_priv)) + dpll_mgr = &rkl_pll_mgr; + else if (INTEL_GEN(dev_priv) >= 12) dpll_mgr = &tgl_pll_mgr; else if (IS_ELKHARTLAKE(dev_priv)) dpll_mgr = &ehl_pll_mgr; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 5d9a2bc371e7c..49367847bfb55 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -125,35 +125,35 @@ enum intel_dpll_id { /** * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL */ - DPLL_ID_ICL_TBTPLL = 2, + DPLL_ID_ICL_TBTPLL = 3, /** * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), * TGL TC PLL 1 port 1 (TC1) */ - DPLL_ID_ICL_MGPLL1 = 3, + DPLL_ID_ICL_MGPLL1, /** * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) * TGL TC PLL 1 port 2 (TC2) */ - DPLL_ID_ICL_MGPLL2 = 4, + DPLL_ID_ICL_MGPLL2, /** * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) * TGL TC PLL 1 port 3 (TC3) */ - DPLL_ID_ICL_MGPLL3 = 5, + DPLL_ID_ICL_MGPLL3, /** * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) * TGL TC PLL 1 port 4 (TC4) */ - DPLL_ID_ICL_MGPLL4 = 6, + DPLL_ID_ICL_MGPLL4, /** * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) */ - DPLL_ID_TGL_MGPLL5 = 7, + DPLL_ID_TGL_MGPLL5, /** * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) */ - DPLL_ID_TGL_MGPLL6 = 8, + DPLL_ID_TGL_MGPLL6, }; #define I915_NUM_PLLS 9 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 45bda5819abd0..34f8698ac3aa6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) -#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) /* * Device info offset array based helpers for groups of registers with unevenly @@ -10427,19 +10426,13 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR0 0x164284 #define _TGL_DPLL1_CFGCR0 0x16428C -/* TODO: add DPLL4 */ -#define _TGL_TBTPLL_CFGCR0 0x16429C -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _TGL_TBTPLL_CFGCR0) +#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ + _TGL_DPLL1_CFGCR0) #define _TGL_DPLL0_CFGCR1 0x164288 #define _TGL_DPLL1_CFGCR1 0x164290 -/* TODO: add DPLL4 */ -#define _TGL_TBTPLL_CFGCR1 0x1642A0 -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _TGL_TBTPLL_CFGCR1) +#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ + _TGL_DPLL1_CFGCR1) #define _DKL_PHY1_BASE 0x168000 #define _DKL_PHY2_BASE 0x169000 -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:18 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:18 -0700 Subject: [Intel-gfx] [PATCH v2 10/32] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-11-lucas.demarchi@intel.com> From: Anusha Srivatsa <anusha.srivatsa at intel.com> Bspec asks us to remove the special programming of the SHPD_FILTER_CNT register which we have been doing since CNP+. Bspec: 49305 Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8652e1e69db72..48e1686df3416 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3116,7 +3116,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, hotplug_irqs = sde_ddi_mask | sde_tc_mask; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); - I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); + if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP) + I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:21 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:21 -0700 Subject: [Intel-gfx] [PATCH v2 13/32] drm/i915/dg1: Define MOCS table for DG1 In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-14-lucas.demarchi@intel.com> DG1 has a new MOCS table. We still use the old definition of the table, but as for any dgfx card it doesn't contain the control_value values (these values don't matter as we won't program them). Bspec: 45101 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 632e08a4592b2..7217c6e2087cb 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = { GEN11_MOCS_ENTRIES }; +static const struct drm_i915_mocs_entry dg1_mocs_table[] = { + /* Error */ + MOCS_ENTRY(0, 0, L3_0_DIRECT), + + /* UC */ + MOCS_ENTRY(1, 0, L3_1_UC), + + /* Reserved */ + MOCS_ENTRY(2, 0, L3_0_DIRECT), + MOCS_ENTRY(3, 0, L3_0_DIRECT), + MOCS_ENTRY(4, 0, L3_0_DIRECT), + + /* WB - L3 */ + MOCS_ENTRY(5, 0, L3_3_WB), + /* WB - L3 50% */ + MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB), + /* WB - L3 25% */ + MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB), + /* WB - L3 12.5% */ + MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB), + + /* HDC:L1 + L3 */ + MOCS_ENTRY(48, 0, L3_3_WB), + /* HDC:L1 */ + MOCS_ENTRY(49, 0, L3_1_UC), + + /* HW Reserved */ + MOCS_ENTRY(60, 0, L3_1_UC), + MOCS_ENTRY(61, 0, L3_1_UC), + MOCS_ENTRY(62, 0, L3_1_UC), + MOCS_ENTRY(63, 0, L3_1_UC), +}; + enum { HAS_GLOBAL_MOCS = BIT(0), HAS_ENGINE_MOCS = BIT(1), @@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, { unsigned int flags; - if (INTEL_GEN(i915) >= 12) { + if (IS_DG1(i915)) { + table->size = ARRAY_SIZE(dg1_mocs_table); + table->table = dg1_mocs_table; + table->n_entries = GEN11_NUM_MOCS_ENTRIES; + } else if (INTEL_GEN(i915) >= 12) { table->size = ARRAY_SIZE(tgl_mocs_table); table->table = tgl_mocs_table; table->n_entries = GEN11_NUM_MOCS_ENTRIES; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:22 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:22 -0700 Subject: [Intel-gfx] [PATCH v2 14/32] drm/i915/dg1: Add DG1 power wells In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-15-lucas.demarchi@intel.com> From: Uma Shankar <uma.shankar at intel.com> Most of TGL power wells are re-used for DG1. However, AUDIO Power Domain is moved from PG3 to PG0. Handle the change and initialize power wells with the new power well structure. Some of the Audio Streaming logic still remains in PW3 so still it needs to be enabled. DDIA, DDIB, TC1 and TC2 are the active ports on DG1. Need to keep Transcoder C and D to Pipe Power wells, this is against the spec but else hitting unclaimed register warnings (kept the logic same as TGL) Bspec: 49182 Cc: Matt Roper <matthew.d.roper at intel.com> Cc: Anshuman Gupta <anshuman.gupta at intel.com> Signed-off-by: Uma Shankar <uma.shankar at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- .../drm/i915/display/intel_display_power.c | 201 +++++++++++++++++- 1 file changed, 200 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 24a2aa1fdc9c1..5dc62e6068f24 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_INIT)) +#define DG1_PW_5_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_D) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \ + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_4_POWER_DOMAINS ( \ + DG1_PW_5_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_3_POWER_DOMAINS ( \ + DG1_PW_4_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUX_E) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_2_POWER_DOMAINS ( \ + DG1_PW_3_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + DG1_PW_3_POWER_DOMAINS | \ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = i9xx_always_on_power_well_noop, @@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = { }, }; +static const struct i915_power_well_desc dg1_power_wells[] = { + { + .name = "always-on", + .always_on = true, + .domains = POWER_DOMAIN_MASK, + .ops = &i9xx_always_on_power_well_ops, + .id = DISP_PW_ID_NONE, + }, + { + .name = "power well 1", + /* Handled by the DMC firmware */ + .always_on = true, + .domains = 0, + .ops = &hsw_power_well_ops, + .id = SKL_DISP_PW_1, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_1, + .hsw.has_fuses = true, + }, + }, + { + .name = "DC off", + .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS, + .ops = &gen9_dc_off_power_well_ops, + .id = SKL_DISP_DC_OFF, + }, + { + .name = "power well 2", + .domains = DG1_PW_2_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = SKL_DISP_PW_2, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_2, + .hsw.has_fuses = true, + }, + }, + { + .name = "power well 3", + .domains = DG1_PW_3_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = ICL_DISP_PW_3, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_3, + .hsw.irq_pipe_mask = BIT(PIPE_B), + .hsw.has_vga = true, + .hsw.has_fuses = true, + }, + }, + { + .name = "DDI A IO", + .domains = ICL_DDI_IO_A_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_ddi_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_DDI_A, + } + }, + { + .name = "DDI B IO", + .domains = ICL_DDI_IO_B_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_ddi_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_DDI_B, + } + }, + { + .name = "DDI D TC1 IO", + .domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_ddi_power_well_regs, + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1, + }, + }, + { + .name = "DDI E TC2 IO", + .domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_ddi_power_well_regs, + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2, + }, + }, + { + .name = "AUX A", + .domains = ICL_AUX_A_IO_POWER_DOMAINS, + .ops = &icl_aux_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_aux_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_AUX_A, + }, + }, + { + .name = "AUX B", + .domains = ICL_AUX_B_IO_POWER_DOMAINS, + .ops = &icl_aux_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_aux_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_AUX_B, + }, + }, + { + .name = "AUX D TC1", + .domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS, + .ops = &icl_aux_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_aux_power_well_regs, + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1, + .hsw.is_tc_tbt = false, + }, + }, + { + .name = "AUX E TC2", + .domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS, + .ops = &icl_aux_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &icl_aux_power_well_regs, + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2, + .hsw.is_tc_tbt = false, + }, + }, + { + .name = "power well 4", + .domains = DG1_PW_4_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_4, + .hsw.has_fuses = true, + .hsw.irq_pipe_mask = BIT(PIPE_C), + } + }, + { + .name = "power well 5", + .domains = DG1_PW_5_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = DISP_PW_ID_NONE, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = TGL_PW_CTL_IDX_PW_5, + .hsw.has_fuses = true, + .hsw.irq_pipe_mask = BIT(PIPE_D), + }, + }, +}; + static int sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, int disable_power_well) @@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) * The enabling order will be from lower to higher indexed wells, * the disabling order is reversed. */ - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + err = set_power_wells(power_domains, dg1_power_wells); + } else if (IS_ROCKETLAKE(dev_priv)) { err = set_power_wells(power_domains, rkl_power_wells); } else if (IS_GEN(dev_priv, 12)) { err = set_power_wells(power_domains, tgl_power_wells); -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:38 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:38 -0700 Subject: [Intel-gfx] [PATCH v2 30/32] drm/i915/dg1: Load DMC In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-31-lucas.demarchi@intel.com> From: Matt Atwood <matthew.s.atwood at intel.com> Add support to load DMC v2.0.2 on DG1 While we're at it, tweak the TGL and RKL firmware size definition to follow the convention used in previous platforms. Remove obsolete commenting. Bpec: 49230 Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 9843c9af6c132..9cb293ee55cea 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -38,15 +38,19 @@ * low-power state and comes back to normal. */ -#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin" +#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) +#define DG1_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +MODULE_FIRMWARE(DG1_CSR_PATH); #define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin" #define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) +#define RKL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE MODULE_FIRMWARE(RKL_CSR_PATH); #define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin" #define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6) -#define TGL_CSR_MAX_FW_SIZE 0x6000 +#define TGL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE MODULE_FIRMWARE(TGL_CSR_PATH); #define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin" @@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) */ intel_csr_runtime_pm_get(dev_priv); - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + csr->fw_path = DG1_CSR_PATH; + csr->required_version = DG1_CSR_VERSION_REQUIRED; + csr->max_fw_size = DG1_CSR_MAX_FW_SIZE; + } else if (IS_ROCKETLAKE(dev_priv)) { csr->fw_path = RKL_CSR_PATH; csr->required_version = RKL_CSR_VERSION_REQUIRED; - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + csr->max_fw_size = RKL_CSR_MAX_FW_SIZE; } else if (INTEL_GEN(dev_priv) >= 12) { csr->fw_path = TGL_CSR_PATH; csr->required_version = TGL_CSR_VERSION_REQUIRED; - /* Allow to load fw via parameter using the last known size */ - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + csr->max_fw_size = TGL_CSR_MAX_FW_SIZE; } else if (IS_GEN(dev_priv, 11)) { csr->fw_path = ICL_CSR_PATH; csr->required_version = ICL_CSR_VERSION_REQUIRED; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:39 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:39 -0700 Subject: [Intel-gfx] [PATCH v2 31/32] drm/i915/dg1: Add initial DG1 workarounds In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-32-lucas.demarchi@intel.com> From: Stuart Summers <stuart.summers at intel.com> DG1 shares some workarounds with TGL and RKL and also has some additional workarounds of its own. Media power gating should not be applied so we just set it to nop_init_clock_gating(). BSpec: 53508 Cc: Matt Atwood <matthew.s.atwood at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com> Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Stuart Summers <stuart.summers at intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- .../drm/i915/display/intel_display_power.c | 5 +- drivers/gpu/drm/i915/display/intel_sprite.c | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 91 ++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 10 +- drivers/gpu/drm/i915/intel_pm.c | 17 +++- 5 files changed, 105 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 5dc62e6068f24..3a016abd80c53 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5462,8 +5462,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask; int config, i; - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) - /* Wa_1409767108: tgl */ + if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) || + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0)) + /* Wa_1409767108:tgl,dg1 */ table = wa_1409767108_buddy_page_masks; else table = tgl_buddy_page_masks; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 63ac79f88fa21..ba03f2459d9b5 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -2842,8 +2842,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, enum plane_id plane_id) { - /* Wa_14010477008:tgl[a0..c0],rkl[all] */ - if (IS_ROCKETLAKE(dev_priv) || + /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ + if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) return false; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 741710ca2b9a5..5a9772011d335 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -641,6 +641,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 0); } +static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) +{ + gen12_ctx_workarounds_init(engine, wal); + + /* Wa_1409044764 */ + WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, + DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN); + + /* Wa_22010493298 */ + WA_SET_BIT_MASKED(HIZ_CHICKEN, + DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE); +} + static void __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, struct i915_wa_list *wal, @@ -653,7 +667,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, wa_init_start(wal, name, engine->name); - if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) + if (IS_DG1(i915)) + dg1_ctx_workarounds_init(engine, wal); + else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) tgl_ctx_workarounds_init(engine, wal); else if (IS_GEN(i915, 12)) gen12_ctx_workarounds_init(engine, wal); @@ -1213,10 +1229,30 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); } +static void +dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + gen12_gt_workarounds_init(i915, wal); + + /* Wa_1607087056:dg1 */ + if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0)) + wa_write_or(wal, + SLICE_UNIT_LEVEL_CLKGATE, + L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); + + /* Wa_1409420604:dg1 */ + if (IS_DG1(i915)) + wa_write_or(wal, + SUBSLICE_UNIT_LEVEL_CLKGATE2, + CPSSUNIT_CLKGATE_DIS); +} + static void gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_TIGERLAKE(i915)) + if (IS_DG1(i915)) + dg1_gt_workarounds_init(i915, wal); + else if (IS_TIGERLAKE(i915)) tgl_gt_workarounds_init(i915, wal); else if (IS_GEN(i915, 12)) gen12_gt_workarounds_init(i915, wal); @@ -1581,6 +1617,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) } } +static void dg1_whitelist_build(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + + tgl_whitelist_build(engine); + + /* GEN:BUG:1409280441:dg1 */ + if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) && + (engine->class == RENDER_CLASS || + engine->class == COPY_ENGINE_CLASS)) + whitelist_reg_ext(w, RING_ID(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); +} + void intel_engine_init_whitelist(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; @@ -1588,7 +1638,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) wa_init_start(w, "whitelist", engine->name); - if (IS_GEN(i915, 12)) + if (IS_DG1(i915)) + dg1_whitelist_build(engine); + else if (IS_GEN(i915, 12)) tgl_whitelist_build(engine); else if (IS_GEN(i915, 11)) icl_whitelist_build(engine); @@ -1642,15 +1694,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct drm_i915_private *i915 = engine->i915; - if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { + if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || + IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { /* - * Wa_1607138336:tgl - * Wa_1607063988:tgl + * Wa_1607138336:tgl[a0],dg1[a0] + * Wa_1607063988:tgl[a0],dg1[a0] */ wa_write_or(wal, GEN9_CTX_PREEMPT_REG, GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); + } + if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) @@ -1663,32 +1718,40 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_write_or(wal, GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE); + } - /* Wa_1408615072:tgl */ + if (IS_DG1(i915) || IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) { + /* Wa_1408615072:tgl[a0],dg1 */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); } - if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { - /* Wa_1606931601:tgl,rkl */ + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1606931601:tgl,rkl,dg1 */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); + } - /* Wa_1409804808:tgl,rkl */ + if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || + IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { + /* Wa_1409804808:tgl,rkl,dg1[a0] */ wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS); /* * Wa_1409085225:tgl - * Wa_14010229206:tgl,rkl + * Wa_14010229206:tgl,rkl,dg1[a0] */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); /* * Wa_1607030317:tgl * Wa_1607186500:tgl - * Wa_1607297627:tgl,rkl there are multiple entries for this - * WA in the BSpec; some indicate this is an A0-only WA, - * others indicate it applies to all steppings. + * Wa_1607297627:tgl,rkl,dg1[a0] + * + * On TGL and RKL there are multiple entries for this WA in the + * BSpec; some indicate this is an A0-only WA, others indicate + * it applies to all steppings so we trust the "all steppings." + * For DG1 this only applies to A0. */ wa_masked_en(wal, GEN6_RC_SLEEP_PSMI_CONTROL, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 34ed419283a70..0fd6aed908cde 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2530,6 +2530,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) #define RING_MAX_IDLE(base) _MMIO((base) + 0x54) #define RING_HWS_PGA(base) _MMIO((base) + 0x80) +#define RING_ID(base) _MMIO((base) + 0x8c) #define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) #define RING_RESET_CTL(base) _MMIO((base) + 0xd0) #define RESET_CTL_CAT_ERROR REG_BIT(2) @@ -4144,6 +4145,7 @@ enum { #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) #define TGL_VRH_GATING_DIS REG_BIT(31) +#define DPT_GATING_DIS REG_BIT(22) #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) #define BXT_GMBUS_GATING_DIS (1 << 14) @@ -7959,12 +7961,14 @@ enum { #define GEN8_L3CNTLREG _MMIO(0x7034) #define GEN8_ERRDETBCTRL (1 << 9) -#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) - #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) - #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) +#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) + #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) + #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) + #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) #define HIZ_CHICKEN _MMIO(0x7018) # define CHV_HZ_8X8_MODE_IN_1X (1 << 15) +# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE (1 << 14) # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) #define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2a32d62307954..77bf1a8c285b3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7123,6 +7123,19 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) 0, DFR_DISABLE); } +static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) +{ + /* + * As opposed to TGL, we should not touch the registers for media power + * gating + */ + + /* Wa_14010096844:dg1[a0] */ + if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0)) + I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | + DPT_GATING_DIS); +} + static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) { if (!HAS_PCH_CNP(dev_priv)) @@ -7499,7 +7512,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) */ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { - if (IS_GEN(dev_priv, 12)) + if (IS_DG1(dev_priv)) + dev_priv->display.init_clock_gating = dg1_init_clock_gating; + else if (IS_GEN(dev_priv, 12)) dev_priv->display.init_clock_gating = tgl_init_clock_gating; else if (IS_GEN(dev_priv, 11)) dev_priv->display.init_clock_gating = icl_init_clock_gating; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 18 00:42:40 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 17:42:40 -0700 Subject: [Intel-gfx] [PATCH v2 32/32] drm/i915/dg1: DG1 does not support DC6 In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <20200618004240.16263-33-lucas.demarchi@intel.com> From: Anshuman Gupta <anshuman.gupta at intel.com> DC6 is not supported on DG1, so change the allowed DC mask for DG1. Cc: Uma Shankar <uma.shankar at intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 3a016abd80c53..33c89cdfb3977 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, int max_dc; if (INTEL_GEN(dev_priv) >= 12) { - max_dc = 4; + if (IS_DG1(dev_priv)) + max_dc = 3; + else + max_dc = 4; /* * DC9 has a separate HW flow from the rest of the DC states, * not depending on the DMC firmware. It's needed by system -- 2.26.2 From patchwork at emeril.freedesktop.org Thu Jun 18 00:51:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 00:51:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/2=5D_drm/i915/dp=3A_Helper_for_chec?= =?utf-8?q?king_DDI=5FBUF=5FCTL_Idle_status?= In-Reply-To: <20200618000124.29036-1-manasi.d.navare@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> Message-ID: <159244151064.22460.15082308685847975632@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status URL : https://patchwork.freedesktop.org/series/78500/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17984 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/index.html Known issues ------------ Here are the changes found in Patchwork_17984 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-bsw-n3050: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html - fi-glk-dsi: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][13] ([i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_busy@basic at flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-guc: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - {fi-tgl-dsi}: [INCOMPLETE][21] -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-tgl-dsi/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][25] ([fdo#109271]) -> [DMESG-FAIL][26] ([i915#62] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 41) ------------------------------ Missing (7): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17984 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17984: ed2c62fe315d12edf14a8de352d0ccf3c0ea9780 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ed2c62fe315d drm/i915/dp: Wait or poll with timeout for DDI BUF non idle after enable 42dd12bb148b drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/index.html From patchwork at emeril.freedesktop.org Thu Jun 18 00:56:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 00:56:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Introduce_DG1_=28rev2=29?= In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <159244180291.22461.1017514311246139674@emeril.freedesktop.org> == Series Details == Series: Introduce DG1 (rev2) URL : https://patchwork.freedesktop.org/series/77496/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0168a6dc120d drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout b533bd97f161 drm/i915/rkl: Add DPLL4 support 266c7f569e81 drm/i915/rkl: Handle HTI 0dcdc976291d drm/i915/rkl: Add initial workarounds bc9a17f57138 drm/i915/rkl: Add Wa_14011224835 for PHY B initialization 8f27f0ec2180 drm/i915: Add has_master_unit_irq flag 5e175aa8a3f1 drm/i915/dg1: add initial DG-1 definitions -:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects? #41: FILE: drivers/gpu/drm/i915/i915_drv.h:1563: +#define IS_DG1_REVID(p, since, until) \ + (IS_DG1(p) && IS_REVID(p, since, until)) total: 0 errors, 0 warnings, 1 checks, 53 lines checked 1f9863075fc5 drm/i915/dg1: Add DG1 PCI IDs e5efb9b1d3a3 drm/i915/dg1: add support for the master unit interrupt e45165e0ecea drm/i915/dg1: Remove SHPD_FILTER_CNT register programming 1a41b5d5a734 drm/i915/dg1: Add fake PCH e1eb70f5e961 drm/i915/dg1: Initialize RAWCLK properly 40ff297509d4 drm/i915/dg1: Define MOCS table for DG1 95dc688fbad0 drm/i915/dg1: Add DG1 power wells 9e17457108d4 drm/i915/dg1: Increase mmio size to 4MB 63bc63bff441 drm/i915/dg1: Wait for pcode/uncore handshake at startup bdec0b31b8b0 drm/i915/dg1: Add DPLL macros for DG1 67f3b147ced0 drm/i915/dg1: Add and setup DPLLs for DG1 955fe7def921 drm/i915/dg1: Enable DPLL for DG1 eb5057fd8085 drm/i915/dg1: add hpd interrupt handling c56090c99ac7 drm/i915/dg1: invert HPD pins 592dd39473a7 drm/i915/dg1: gmbus pin mapping 9f15f4f45591 drm/i915/dg1: Enable first 2 ports for DG1 5a0cc1900a4f drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D f2cac2139aff drm/i915/dg1: Update comp master/slave relationships for PHYs 2d8d3581a563 drm/i915/dg1: Update voltage swing tables for DP ee62584fb237 drm/i915/dg1: provide port/phy mapping for vbt 6313b83c0806 drm/i915/dg1: map/unmap pll clocks -:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects? #244: FILE: drivers/gpu/drm/i915/i915_reg.h:10259: +#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \ + ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2))) total: 0 errors, 0 warnings, 1 checks, 204 lines checked a1377be54bdb drm/i915/dg1: enable PORT C/D aka D/E ad0d140c9965 drm/i915/dg1: Load DMC 277c534f9b87 drm/i915/dg1: Add initial DG1 workarounds a976a97be22b drm/i915/dg1: DG1 does not support DC6 From patchwork at emeril.freedesktop.org Thu Jun 18 00:57:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 00:57:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Introduce_DG1_=28rev2=29?= In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <159244187602.22462.12778912698871614485@emeril.freedesktop.org> == Series Details == Series: Introduce DG1 (rev2) URL : https://patchwork.freedesktop.org/series/77496/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1223:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1226:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1229:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1232:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Thu Jun 18 01:18:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 01:18:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgSW50?= =?utf-8?q?roduce_DG1_=28rev2=29?= In-Reply-To: <20200618004240.16263-1-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> Message-ID: <159244310495.22461.1986226893136778661@emeril.freedesktop.org> == Series Details == Series: Introduce DG1 (rev2) URL : https://patchwork.freedesktop.org/series/77496/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8639 -> Patchwork_17985 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17985 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17985, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17985: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gt_engines: - fi-skl-lmem: [PASS][1] -> [DMESG-WARN][2] +31 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-skl-lmem/igt at i915_selftest@live at gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-skl-lmem/igt at i915_selftest@live at gt_engines.html * igt at runner@aborted: - fi-tgl-u2: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-tgl-u2/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at runner@aborted: - {fi-tgl-dsi}: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-tgl-dsi/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_17985 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_busy@basic at flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][11] ([fdo#109271]) -> [DMESG-FAIL][12] ([i915#62] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 41) ------------------------------ Missing (7): fi-ilk-m540 fi-cml-s fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17985 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17985: a976a97be22b2b60c6ba1f42db1c5fc110958ba0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a976a97be22b drm/i915/dg1: DG1 does not support DC6 277c534f9b87 drm/i915/dg1: Add initial DG1 workarounds ad0d140c9965 drm/i915/dg1: Load DMC a1377be54bdb drm/i915/dg1: enable PORT C/D aka D/E 6313b83c0806 drm/i915/dg1: map/unmap pll clocks ee62584fb237 drm/i915/dg1: provide port/phy mapping for vbt 2d8d3581a563 drm/i915/dg1: Update voltage swing tables for DP f2cac2139aff drm/i915/dg1: Update comp master/slave relationships for PHYs 5a0cc1900a4f drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D 9f15f4f45591 drm/i915/dg1: Enable first 2 ports for DG1 592dd39473a7 drm/i915/dg1: gmbus pin mapping c56090c99ac7 drm/i915/dg1: invert HPD pins eb5057fd8085 drm/i915/dg1: add hpd interrupt handling 955fe7def921 drm/i915/dg1: Enable DPLL for DG1 67f3b147ced0 drm/i915/dg1: Add and setup DPLLs for DG1 bdec0b31b8b0 drm/i915/dg1: Add DPLL macros for DG1 63bc63bff441 drm/i915/dg1: Wait for pcode/uncore handshake at startup 9e17457108d4 drm/i915/dg1: Increase mmio size to 4MB 95dc688fbad0 drm/i915/dg1: Add DG1 power wells 40ff297509d4 drm/i915/dg1: Define MOCS table for DG1 e1eb70f5e961 drm/i915/dg1: Initialize RAWCLK properly 1a41b5d5a734 drm/i915/dg1: Add fake PCH e45165e0ecea drm/i915/dg1: Remove SHPD_FILTER_CNT register programming e5efb9b1d3a3 drm/i915/dg1: add support for the master unit interrupt 1f9863075fc5 drm/i915/dg1: Add DG1 PCI IDs 5e175aa8a3f1 drm/i915/dg1: add initial DG-1 definitions 8f27f0ec2180 drm/i915: Add has_master_unit_irq flag bc9a17f57138 drm/i915/rkl: Add Wa_14011224835 for PHY B initialization 0dcdc976291d drm/i915/rkl: Add initial workarounds 266c7f569e81 drm/i915/rkl: Handle HTI b533bd97f161 drm/i915/rkl: Add DPLL4 support 0168a6dc120d drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17985/index.html From patchwork at emeril.freedesktop.org Thu Jun 18 01:55:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 01:55:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/2=5D_drm/i915/dp=3A_Helper_for_chec?= =?utf-8?q?king_DDI=5FBUF=5FCTL_Idle_status?= In-Reply-To: <20200618000124.29036-1-manasi.d.navare@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> Message-ID: <159244531285.22462.10227084297666189275@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status URL : https://patchwork.freedesktop.org/series/78500/ State : success == Summary == CI Bug Log - changes from CI_DRM_8639_full -> Patchwork_17984_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17984_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@process: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#93] / [i915#95]) +3 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at gem_ctx_persistence@process.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl3/igt at gem_ctx_persistence@process.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb2/igt at gem_exec_schedule@implicit-read-write at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb5/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_suspend@basic: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk4/igt at gem_exec_suspend@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk4/igt at gem_exec_suspend@basic.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [PASS][9] -> [FAIL][10] ([i915#57]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-hsw2/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-hsw6/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at bc-hdmi-a1-hdmi-a2: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#1928]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk5/igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at bc-hdmi-a1-hdmi-a2.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk2/igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at bc-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +12 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt at kms_flip_tiling@flip-changes-tiling.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl7/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-apl: [PASS][17] -> [DMESG-FAIL][18] ([i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - shard-iclb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb1/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_properties@connector-properties-legacy: - shard-iclb: [PASS][23] -> [DMESG-WARN][24] ([i915#1226]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb4/igt at kms_properties@connector-properties-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb4/igt at kms_properties@connector-properties-legacy.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb7/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_vblank@pipe-b-wait-busy-hang: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl7/igt at kms_vblank@pipe-b-wait-busy-hang.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl6/igt at kms_vblank@pipe-b-wait-busy-hang.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][29] -> [FAIL][30] ([i915#1542]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb5/igt at perf@blocking-parameterized.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb7/igt at perf@blocking-parameterized.html * igt at perf@invalid-create-userspace-config: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#95]) +10 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl4/igt at perf@invalid-create-userspace-config.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl8/igt at perf@invalid-create-userspace-config.html #### Possible fixes #### * igt at gem_exec_gttfill@all: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-glk4/igt at gem_exec_gttfill@all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-glk8/igt at gem_exec_gttfill@all.html * igt at gem_tiled_blits@basic: - shard-snb: [TIMEOUT][35] ([i915#1958]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gem_tiled_blits@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt at gem_tiled_blits@basic.html * igt at gem_tiled_swapping@non-threaded: - shard-apl: [DMESG-WARN][37] ([i915#183]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl2/igt at gem_tiled_swapping@non-threaded.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl3/igt at gem_tiled_swapping@non-threaded.html * igt at kms_addfb_basic@framebuffer-vs-set-tiling: - shard-apl: [DMESG-WARN][39] ([i915#95]) -> [PASS][40] +9 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl1/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl3/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-tglb: [DMESG-WARN][41] ([i915#402]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb5/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-tglb2/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +6 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl1/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl10/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render: - shard-kbl: [DMESG-WARN][47] ([i915#93] / [i915#95]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl9/igt at kms_hdr@bpc-switch-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-position-covered-pipe-b-planes: - shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +4 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl6/igt at kms_plane@plane-position-covered-pipe-b-planes.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl4/igt at kms_plane@plane-position-covered-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-rotation: - shard-apl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-apl6/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-apl4/igt at kms_plane_scaling@pipe-a-scaler-with-rotation.html * igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb3/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb6/igt at kms_plane_scaling@pipe-b-scaler-with-clipping-clamping.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-iclb7/igt at kms_psr@psr2_cursor_render.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][63] ([i915#1820]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][65] ([i915#1958]) -> [FAIL][66] ([i915#1930]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html * igt at gen7_exec_parse@chained-batch: - shard-snb: [TIMEOUT][67] ([i915#1958]) -> [SKIP][68] ([fdo#109271]) +2 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at gen7_exec_parse@chained-batch.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt at gen7_exec_parse@chained-batch.html * igt at kms_color_chamelium@pipe-b-ctm-max: - shard-snb: [TIMEOUT][69] ([i915#1958]) -> [SKIP][70] ([fdo#109271] / [fdo#111827]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-snb4/igt at kms_color_chamelium@pipe-b-ctm-max.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-snb1/igt at kms_color_chamelium@pipe-b-ctm-max.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][71] ([i915#93] / [i915#95]) -> [DMESG-WARN][72] ([i915#180] / [i915#93] / [i915#95]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8639/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#183]: https://gitlab.freedesktop.org/drm/intel/issues/183 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8639 -> Patchwork_17984 CI-20190529: 20190529 CI_DRM_8639: 47584e59cf51ec499d68a4cefbaf447448ce2894 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17984: ed2c62fe315d12edf14a8de352d0ccf3c0ea9780 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17984/index.html From matthew.d.roper at intel.com Thu Jun 18 05:57:35 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Wed, 17 Jun 2020 22:57:35 -0700 Subject: [Intel-gfx] [PATCH v7 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200617200038.GG3680866@mdroper-desk1.amr.corp.intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> <20200617033100.4044428-3-matthew.d.roper@intel.com> <20200617182258.7gwvcbf35o3pi7cz@ldmartin-desk1> <20200617200038.GG3680866@mdroper-desk1.amr.corp.intel.com> Message-ID: <20200618055735.GI3680866@mdroper-desk1.amr.corp.intel.com> On Wed, Jun 17, 2020 at 01:00:38PM -0700, Matt Roper wrote: > On Wed, Jun 17, 2020 at 11:22:58AM -0700, Lucas De Marchi wrote: > > On Tue, Jun 16, 2020 at 08:30:57PM -0700, Matt Roper wrote: > > > Rocket Lake has a third DPLL (called 'DPLL4') that must be used to > > > enable a third display. Unlike EHL's variant of DPLL4, the RKL variant > > > behaves the same as DPLL0/1. And despite its name, the DPLL4 registers > > > are offset as if it were DPLL2. > > > > > > To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used > > > seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match > > > how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT. > > > This means just renumbering TBT to be ID '3' rather than being another > > > ID '2' like DPLL4. With this change, we can build our register > > > selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register > > > offsets are evenly-spaced. MGPLL's don't need any specific ID's > > > (they're just used to translate back to a tc_port), so we let them float > > > at the top of the enum. > > > > > > v2: > > > - Add new .update_ref_clks() hook. > > > > > > v3: > > > - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas) > > > > > > Bspec: 49202 > > > Bspec: 49443 > > > Bspec: 50288 > > > Bspec: 50289 > > > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++----- > > > drivers/gpu/drm/i915/i915_reg.h | 15 +++------- > > > 3 files changed, 37 insertions(+), 21 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > > index b45185b80bec..b5f4d4cef682 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > > @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, > > > return false; > > > } > > > > > > - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) > > > + if (IS_ROCKETLAKE(dev_priv)) { > > > dpll_mask = > > > BIT(DPLL_ID_EHL_DPLL4) | > > > BIT(DPLL_ID_ICL_DPLL1) | > > > BIT(DPLL_ID_ICL_DPLL0); > > > - else > > > + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { > > > + dpll_mask = > > > + BIT(DPLL_ID_EHL_DPLL4) | > > > + BIT(DPLL_ID_ICL_DPLL1) | > > > + BIT(DPLL_ID_ICL_DPLL0); > > > + } else { > > > dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); > > > + } > > > > > > port_dpll->pll = intel_find_shared_dpll(state, crtc, > > > &port_dpll->hw_state, > > > @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { > > > .dump_hw_state = icl_dump_hw_state, > > > }; > > > > > > +static const struct dpll_info rkl_plls[] = { > > > + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, > > > + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, > > > + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, > > > + { }, > > > +}; > > > + > > > +static const struct intel_dpll_mgr rkl_pll_mgr = { > > > + .dpll_info = rkl_plls, > > > + .get_dplls = icl_get_dplls, > > > + .put_dplls = icl_put_dplls, > > > + .update_ref_clks = icl_update_dpll_ref_clks, > > > + .dump_hw_state = icl_dump_hw_state, > > > +}; > > > + > > > /** > > > * intel_shared_dpll_init - Initialize shared DPLLs > > > * @dev: drm device > > > @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) > > > const struct dpll_info *dpll_info; > > > int i; > > > > > > - if (INTEL_GEN(dev_priv) >= 12) > > > + if (IS_ROCKETLAKE(dev_priv)) > > > + dpll_mgr = &rkl_pll_mgr; > > > + else if (INTEL_GEN(dev_priv) >= 12) > > > dpll_mgr = &tgl_pll_mgr; > > > else if (IS_ELKHARTLAKE(dev_priv)) > > > dpll_mgr = &ehl_pll_mgr; > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > > index 5d9a2bc371e7..49367847bfb5 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > > @@ -125,35 +125,35 @@ enum intel_dpll_id { > > > /** > > > * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL > > > */ > > > - DPLL_ID_ICL_TBTPLL = 2, > > > + DPLL_ID_ICL_TBTPLL = 3, > > > /** > > > * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), > > > * TGL TC PLL 1 port 1 (TC1) > > > */ > > > - DPLL_ID_ICL_MGPLL1 = 3, > > > + DPLL_ID_ICL_MGPLL1, > > > /** > > > * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) > > > * TGL TC PLL 1 port 2 (TC2) > > > */ > > > - DPLL_ID_ICL_MGPLL2 = 4, > > > + DPLL_ID_ICL_MGPLL2, > > > /** > > > * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) > > > * TGL TC PLL 1 port 3 (TC3) > > > */ > > > - DPLL_ID_ICL_MGPLL3 = 5, > > > + DPLL_ID_ICL_MGPLL3, > > > /** > > > * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) > > > * TGL TC PLL 1 port 4 (TC4) > > > */ > > > - DPLL_ID_ICL_MGPLL4 = 6, > > > + DPLL_ID_ICL_MGPLL4, > > > /** > > > * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) > > > */ > > > - DPLL_ID_TGL_MGPLL5 = 7, > > > + DPLL_ID_TGL_MGPLL5, > > > /** > > > * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) > > > */ > > > - DPLL_ID_TGL_MGPLL6 = 8, > > > + DPLL_ID_TGL_MGPLL6, > > > }; > > > > > > #define I915_NUM_PLLS 9 > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 45bda5819abd..34f8698ac3aa 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > > > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > > > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > > > -#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) > > > > See my series adding DPLL support for DG1. We will need it again for a > > different reason, with a slightly different form. I'd let this here > > to avoid removing and adding it back. > > > > Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com> > > With the renumbering of TBT to 3, we now have a "hole" in the DPLLs > exposed on TGL (0, 1, 3) which WARNs: > > <4>[ 6.165705] i915 0000:00:02.0: drm_WARN_ON(i != dpll_info[i].id) > <4>[ 6.166050] WARNING: CPU: 7 PID: 335 at drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4360 intel_shared_dpll_init+0xa6/0x1d0 [i915] > > I remember having a hole was a problem back when we just passed min/max > DPLLs for initialization, but I think it should be safe now ever since: > > commit 2a86972f60fcfaa0daa02b9fe461935ea2063791 > Author: Matt Roper <matthew.d.roper at intel.com> > Date: Tue Oct 8 10:29:20 2019 -0700 > > drm/i915: Select DPLL's via mask Actually it turns out there are still some assumptions that DPLLs have contiguous ID's and the dpll array index matches the ID. I'll need to make some other changes to allow us to break those assumptions; I'll work on that some more tomorrow when I get free time. Matt > > so I'll send another version that drops that WARN and keeps the > _MMIO_PLL3 definition here. > > Thanks. > > > Matt > > > > > thanks > > Lucas De Marchi > > > > > > > > /* > > > * Device info offset array based helpers for groups of registers with unevenly > > > @@ -10427,19 +10426,13 @@ enum skl_power_gate { > > > > > > #define _TGL_DPLL0_CFGCR0 0x164284 > > > #define _TGL_DPLL1_CFGCR0 0x16428C > > > -/* TODO: add DPLL4 */ > > > -#define _TGL_TBTPLL_CFGCR0 0x16429C > > > -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ > > > - _TGL_DPLL1_CFGCR0, \ > > > - _TGL_TBTPLL_CFGCR0) > > > +#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ > > > + _TGL_DPLL1_CFGCR0) > > > > > > #define _TGL_DPLL0_CFGCR1 0x164288 > > > #define _TGL_DPLL1_CFGCR1 0x164290 > > > -/* TODO: add DPLL4 */ > > > -#define _TGL_TBTPLL_CFGCR1 0x1642A0 > > > -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ > > > - _TGL_DPLL1_CFGCR1, \ > > > - _TGL_TBTPLL_CFGCR1) > > > +#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ > > > + _TGL_DPLL1_CFGCR1) > > > > > > #define _DKL_PHY1_BASE 0x168000 > > > #define _DKL_PHY2_BASE 0x169000 > > > -- > > > 2.24.1 > > > > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From lucas.de.marchi at gmail.com Thu Jun 18 06:38:20 2020 From: lucas.de.marchi at gmail.com (Lucas De Marchi) Date: Wed, 17 Jun 2020 23:38:20 -0700 Subject: [Intel-gfx] [PATCH v7 2/5] drm/i915/rkl: Add DPLL4 support In-Reply-To: <20200618055735.GI3680866@mdroper-desk1.amr.corp.intel.com> References: <20200617033100.4044428-1-matthew.d.roper@intel.com> <20200617033100.4044428-3-matthew.d.roper@intel.com> <20200617182258.7gwvcbf35o3pi7cz@ldmartin-desk1> <20200617200038.GG3680866@mdroper-desk1.amr.corp.intel.com> <20200618055735.GI3680866@mdroper-desk1.amr.corp.intel.com> Message-ID: <CAKi4VAJh2a+YPwBWNmEVGFxbJ1y=JqiJZ7Z9AYm-j6_x91ZMQw@mail.gmail.com> On Wed, Jun 17, 2020 at 10:57 PM Matt Roper <matthew.d.roper at intel.com> wrote: > > On Wed, Jun 17, 2020 at 01:00:38PM -0700, Matt Roper wrote: > > On Wed, Jun 17, 2020 at 11:22:58AM -0700, Lucas De Marchi wrote: > > > On Tue, Jun 16, 2020 at 08:30:57PM -0700, Matt Roper wrote: > > > > Rocket Lake has a third DPLL (called 'DPLL4') that must be used to > > > > enable a third display. Unlike EHL's variant of DPLL4, the RKL variant > > > > behaves the same as DPLL0/1. And despite its name, the DPLL4 registers > > > > are offset as if it were DPLL2. > > > > > > > > To allow the TGL register selectors like TGL_DPLL_CFGCR0 to be used > > > > seamlessly on all gen12 platforms, we set the non-MG PLL ID's to match > > > > how the registers are laid out: DPLL0, DPLL1, DPLL4 (RKL-only), TBT. > > > > This means just renumbering TBT to be ID '3' rather than being another > > > > ID '2' like DPLL4. With this change, we can build our register > > > > selectors with _MMIO_PLL rather than _MMIO_PLL3 since the register > > > > offsets are evenly-spaced. MGPLL's don't need any specific ID's > > > > (they're just used to translate back to a tc_port), so we let them float > > > > at the top of the enum. > > > > > > > > v2: > > > > - Add new .update_ref_clks() hook. > > > > > > > > v3: > > > > - Renumber TBT PLL to '3' and switch _MMIO_PLL3 to _MMIO_PLL (Lucas) > > > > > > > > Bspec: 49202 > > > > Bspec: 49443 > > > > Bspec: 50288 > > > > Bspec: 50289 > > > > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > > > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++-- > > > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 14 ++++----- > > > > drivers/gpu/drm/i915/i915_reg.h | 15 +++------- > > > > 3 files changed, 37 insertions(+), 21 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > > > index b45185b80bec..b5f4d4cef682 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > > > @@ -3506,13 +3506,19 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, > > > > return false; > > > > } > > > > > > > > - if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) > > > > + if (IS_ROCKETLAKE(dev_priv)) { > > > > dpll_mask = > > > > BIT(DPLL_ID_EHL_DPLL4) | > > > > BIT(DPLL_ID_ICL_DPLL1) | > > > > BIT(DPLL_ID_ICL_DPLL0); > > > > - else > > > > + } else if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) { > > > > + dpll_mask = > > > > + BIT(DPLL_ID_EHL_DPLL4) | > > > > + BIT(DPLL_ID_ICL_DPLL1) | > > > > + BIT(DPLL_ID_ICL_DPLL0); > > > > + } else { > > > > dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); > > > > + } > > > > > > > > port_dpll->pll = intel_find_shared_dpll(state, crtc, > > > > &port_dpll->hw_state, > > > > @@ -4275,6 +4281,21 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { > > > > .dump_hw_state = icl_dump_hw_state, > > > > }; > > > > > > > > +static const struct dpll_info rkl_plls[] = { > > > > + { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, > > > > + { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, > > > > + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, > > > > + { }, > > > > +}; > > > > + > > > > +static const struct intel_dpll_mgr rkl_pll_mgr = { > > > > + .dpll_info = rkl_plls, > > > > + .get_dplls = icl_get_dplls, > > > > + .put_dplls = icl_put_dplls, > > > > + .update_ref_clks = icl_update_dpll_ref_clks, > > > > + .dump_hw_state = icl_dump_hw_state, > > > > +}; > > > > + > > > > /** > > > > * intel_shared_dpll_init - Initialize shared DPLLs > > > > * @dev: drm device > > > > @@ -4288,7 +4309,9 @@ void intel_shared_dpll_init(struct drm_device *dev) > > > > const struct dpll_info *dpll_info; > > > > int i; > > > > > > > > - if (INTEL_GEN(dev_priv) >= 12) > > > > + if (IS_ROCKETLAKE(dev_priv)) > > > > + dpll_mgr = &rkl_pll_mgr; > > > > + else if (INTEL_GEN(dev_priv) >= 12) > > > > dpll_mgr = &tgl_pll_mgr; > > > > else if (IS_ELKHARTLAKE(dev_priv)) > > > > dpll_mgr = &ehl_pll_mgr; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > > > index 5d9a2bc371e7..49367847bfb5 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > > > > @@ -125,35 +125,35 @@ enum intel_dpll_id { > > > > /** > > > > * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL > > > > */ > > > > - DPLL_ID_ICL_TBTPLL = 2, > > > > + DPLL_ID_ICL_TBTPLL = 3, > > > > /** > > > > * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), > > > > * TGL TC PLL 1 port 1 (TC1) > > > > */ > > > > - DPLL_ID_ICL_MGPLL1 = 3, > > > > + DPLL_ID_ICL_MGPLL1, > > > > /** > > > > * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) > > > > * TGL TC PLL 1 port 2 (TC2) > > > > */ > > > > - DPLL_ID_ICL_MGPLL2 = 4, > > > > + DPLL_ID_ICL_MGPLL2, > > > > /** > > > > * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) > > > > * TGL TC PLL 1 port 3 (TC3) > > > > */ > > > > - DPLL_ID_ICL_MGPLL3 = 5, > > > > + DPLL_ID_ICL_MGPLL3, > > > > /** > > > > * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) > > > > * TGL TC PLL 1 port 4 (TC4) > > > > */ > > > > - DPLL_ID_ICL_MGPLL4 = 6, > > > > + DPLL_ID_ICL_MGPLL4, > > > > /** > > > > * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) > > > > */ > > > > - DPLL_ID_TGL_MGPLL5 = 7, > > > > + DPLL_ID_TGL_MGPLL5, > > > > /** > > > > * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) > > > > */ > > > > - DPLL_ID_TGL_MGPLL6 = 8, > > > > + DPLL_ID_TGL_MGPLL6, > > > > }; > > > > > > > > #define I915_NUM_PLLS 9 > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > > index 45bda5819abd..34f8698ac3aa 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -242,7 +242,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > > > #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > > > > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > > > > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > > > > -#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) > > > > > > See my series adding DPLL support for DG1. We will need it again for a > > > different reason, with a slightly different form. I'd let this here > > > to avoid removing and adding it back. > > > > > > Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com> > > > > With the renumbering of TBT to 3, we now have a "hole" in the DPLLs > > exposed on TGL (0, 1, 3) which WARNs: > > > > <4>[ 6.165705] i915 0000:00:02.0: drm_WARN_ON(i != dpll_info[i].id) > > <4>[ 6.166050] WARNING: CPU: 7 PID: 335 at drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4360 intel_shared_dpll_init+0xa6/0x1d0 [i915] > > > > I remember having a hole was a problem back when we just passed min/max > > DPLLs for initialization, but I think it should be safe now ever since: > > > > commit 2a86972f60fcfaa0daa02b9fe461935ea2063791 > > Author: Matt Roper <matthew.d.roper at intel.com> > > Date: Tue Oct 8 10:29:20 2019 -0700 > > > > drm/i915: Select DPLL's via mask > > Actually it turns out there are still some assumptions that DPLLs have > contiguous ID's and the dpll array index matches the ID. I'll need to > make some other changes to allow us to break those assumptions; I'll > work on that some more tomorrow when I get free time. I think we had removed that long ago...? Maybe we missed some patch? I think that was the intention of https://patchwork.freedesktop.org/series/55378/#rev1 So.... either that or remove the hole. The new IDs could be used by TGL and RKL and leave ICL/EHL alone. For DG1 we are defining new IDs for clarity nonetheless. Lucas De Marchi > > > > Matt > > > > > so I'll send another version that drops that WARN and keeps the > > _MMIO_PLL3 definition here. > > > > Thanks. > > > > > > Matt > > > > > > > > thanks > > > Lucas De Marchi > > > > > > > > > > > /* > > > > * Device info offset array based helpers for groups of registers with unevenly > > > > @@ -10427,19 +10426,13 @@ enum skl_power_gate { > > > > > > > > #define _TGL_DPLL0_CFGCR0 0x164284 > > > > #define _TGL_DPLL1_CFGCR0 0x16428C > > > > -/* TODO: add DPLL4 */ > > > > -#define _TGL_TBTPLL_CFGCR0 0x16429C > > > > -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ > > > > - _TGL_DPLL1_CFGCR0, \ > > > > - _TGL_TBTPLL_CFGCR0) > > > > +#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ > > > > + _TGL_DPLL1_CFGCR0) > > > > > > > > #define _TGL_DPLL0_CFGCR1 0x164288 > > > > #define _TGL_DPLL1_CFGCR1 0x164290 > > > > -/* TODO: add DPLL4 */ > > > > -#define _TGL_TBTPLL_CFGCR1 0x1642A0 > > > > -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ > > > > - _TGL_DPLL1_CFGCR1, \ > > > > - _TGL_TBTPLL_CFGCR1) > > > > +#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ > > > > + _TGL_DPLL1_CFGCR1) > > > > > > > > #define _DKL_PHY1_BASE 0x168000 > > > > #define _DKL_PHY2_BASE 0x169000 > > > > -- > > > > 2.24.1 > > > > > > > > -- > > Matt Roper > > Graphics Software Engineer > > VTT-OSGC Platform Enablement > > Intel Corporation > > (916) 356-2795 > > -- > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi From chris at chris-wilson.co.uk Thu Jun 18 07:14:34 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 08:14:34 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/10] gem_wsim: Rip out userspace balancing In-Reply-To: <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> Message-ID: <159246447431.2739.9873271400703393063@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-17 17:01:11) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Evaluation of userspace load balancing options was how this tool started > but since we have settled on doing it in the kernel. > > Tomorrow we will want to update the tool for new engine interfaces and all > this legacy code will just be a distraction. > > Rip out everything not related to explicit load balancing implemented via > context engine maps and adjust the workloads to use it. Hmm, if this is on the table, should we also then restrict load-balancing wsim to gen11+ so that we can use the timed loops rather nop batches? That would be a huge selling point, and I'll just keep an old checkout around for nop load balancing with all the trimmings. -Chris From tvrtko.ursulin at linux.intel.com Thu Jun 18 07:40:25 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 08:40:25 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/10] gem_wsim: Rip out userspace balancing In-Reply-To: <159246447431.2739.9873271400703393063@build.alporthouse.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> <159246447431.2739.9873271400703393063@build.alporthouse.com> Message-ID: <09894f81-19b3-4dde-0764-ec042a5c61e8@linux.intel.com> On 18/06/2020 08:14, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-17 17:01:11) >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> Evaluation of userspace load balancing options was how this tool started >> but since we have settled on doing it in the kernel. >> >> Tomorrow we will want to update the tool for new engine interfaces and all >> this legacy code will just be a distraction. >> >> Rip out everything not related to explicit load balancing implemented via >> context engine maps and adjust the workloads to use it. > > Hmm, if this is on the table, should we also then restrict > load-balancing wsim to gen11+ so that we can use the timed loops rather > nop batches? That would be a huge selling point, and I'll just keep an > old checkout around for nop load balancing with all the trimmings. That was my plan for the next step yes. Just taking your patch without further changes would already make it work I think. But also at some point I want to convert the engine selection (and engine naming in descriptors) to class:instance. Why do you need the nop/old balancing stuff? I would hope going forward we only need to compare current balancing against any changes. So I'd really like to remoev the userspace balancing stuff. Regards, Tvrtko From tvrtko.ursulin at linux.intel.com Thu Jun 18 07:46:18 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 08:46:18 +0100 Subject: [Intel-gfx] [PATCH i-g-t 03/10] gem_wsim: Show workload timing stats In-Reply-To: <159241310169.19488.4644166988486362775@build.alporthouse.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-4-tvrtko.ursulin@linux.intel.com> <159241310169.19488.4644166988486362775@build.alporthouse.com> Message-ID: <e7902369-6c97-c18b-728a-038a8d8c18ff@linux.intel.com> On 17/06/2020 17:58, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-17 17:01:13) >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> Show average/min/max workload iteration and dropped period stats when 'p' >> command is used. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> --- >> benchmarks/gem_wsim.c | 19 +++++++++++++++---- >> 1 file changed, 15 insertions(+), 4 deletions(-) >> >> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c >> index 9e5bfe6a36d4..60982cb73ba7 100644 >> --- a/benchmarks/gem_wsim.c >> +++ b/benchmarks/gem_wsim.c >> @@ -2101,7 +2101,8 @@ static void *run_workload(void *data) >> struct w_step *w; >> int throttle = -1; >> int qd_throttle = -1; >> - int count; >> + int count, missed = 0; >> + unsigned long time_tot = 0, time_min = ULONG_MAX, time_max = 0; >> int i; >> >> clock_gettime(CLOCK_MONOTONIC, &t_start); >> @@ -2121,12 +2122,19 @@ static void *run_workload(void *data) >> do_sleep = w->delay; >> } else if (w->type == PERIOD) { >> struct timespec now; >> + int elapsed; >> >> clock_gettime(CLOCK_MONOTONIC, &now); >> - do_sleep = w->period - >> - elapsed_us(&wrk->repeat_start, &now); >> + elapsed = elapsed_us(&wrk->repeat_start, &now); >> + do_sleep = w->period - elapsed; >> + time_tot += elapsed; >> + if (elapsed < time_min) >> + time_min = elapsed; >> + if (elapsed > time_max) >> + time_max = elapsed; > > Keep the running average? Could do but why? I already have the count so adding up total elapsed frame time sound easiest. Regards, Tvrtko > >> if (do_sleep < 0) { >> - if (verbose > 1) >> + missed++; >> + if (verbose > 2) >> printf("%u: Dropped period @ %u/%u (%dus late)!\n", >> wrk->id, count, i, do_sleep); >> continue; >> @@ -2280,6 +2288,9 @@ static void *run_workload(void *data) >> printf("%c%u: %.3fs elapsed (%d cycles, %.3f workloads/s).", >> wrk->background ? ' ' : '*', wrk->id, >> t, count, count / t); >> + if (time_tot) >> + printf(" Time avg/min/max=%lu/%lu/%luus; %u missed.", >> + time_tot / count, time_min, time_max, missed); >> putchar('\n'); >> } >> >> -- >> 2.20.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> From tvrtko.ursulin at linux.intel.com Thu Jun 18 07:53:47 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 08:53:47 +0100 Subject: [Intel-gfx] [PATCH i-g-t 08/10] gem_wsim: Snippet of a workload extracted from carchase In-Reply-To: <159241590881.2739.7990352305579268212@build.alporthouse.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-9-tvrtko.ursulin@linux.intel.com> <159241590881.2739.7990352305579268212@build.alporthouse.com> Message-ID: <d38387a9-45c7-4138-8f65-0879f74f2f2d@linux.intel.com> On 17/06/2020 18:45, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-17 17:01:18) >> +1.RCS.1000.r3-47/w27-0/r0-58/r3-80/r22-31/r3-42/r9-4/w34-0/r3-18/r3-41/r21-0/r9-5/r3-78/r25-4/r3-104/r3-23/r30-0/r3-88/r22-27/r22-1/r25-45/r3-50/r22-12/r22-22/r22-3/r22-0/r25-56/r3-4/r22-15/r25-113/r3-7/r22-18/r25-60/r3-81/r25-21/r3-89/r18-5/r3-93/r17-8/r25-28/r25-87/r25-9/r25-13/r25-42/r25-90/r22-16/r34-2/r3-15/w3-64/r0-67/r25-99/r25-73/r3-6/r25-40/r3-90/r22-20/r0-45/r3-110/w32-17/w32-16/w32-3/w32-1/w33-2/r28-2/r3-98/r3-85/r25-48/r3-12/r25-104/r24-23/r3-87/r3-108/r3-26/r3-96/r22-5/r22-14/r3-49/r3-103/r22-6/r3-68/r3-112/r22-29/r22-28/r25-14/r25-44/r25-19/r3-67/r25-111/r18-4/r3-66/r18-17/r4-5/r25-68/r25-86/r25-26/r25-67/r3-37/r25-0/r22-7/r25-59/r25-71/r25-101/r25-75/r25-20/r25-91/r3-2/r3-117/r3-33/r22-2/r25-55/r25-66/r25-24/r25-105/r25-61/r25-11/r25-51/r25-64/r25-70/r18-19/r18-26/r18-21/r25-81/r25-78/r25-37/r25-50/r25-102/r25-35/r18-18/r18-13/r18-12/r3-69/r3-19/r3-100/r22-21/r25-22/r3-29/r25-93/r18-2/r18-14/r18-3/r22-10/r18-23/r18-7/r18-11/r3-73/r8-0/r25-92/r25-41/w33-3/r0-1! >> 07/w19-0. >> 0 > > This patch has been mangled. Could it be your email client? (Very long lines in the patch.) I don't see corruption anywhere on my side, or on the copy I received from the mailing list. Regards, Tvrtko From chris at chris-wilson.co.uk Thu Jun 18 07:55:03 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 08:55:03 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/10] gem_wsim: Rip out userspace balancing In-Reply-To: <09894f81-19b3-4dde-0764-ec042a5c61e8@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> <159246447431.2739.9873271400703393063@build.alporthouse.com> <09894f81-19b3-4dde-0764-ec042a5c61e8@linux.intel.com> Message-ID: <159246690392.4042.13152874782613620641@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 08:40:25) > > On 18/06/2020 08:14, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-17 17:01:11) > >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> > >> Evaluation of userspace load balancing options was how this tool started > >> but since we have settled on doing it in the kernel. > >> > >> Tomorrow we will want to update the tool for new engine interfaces and all > >> this legacy code will just be a distraction. > >> > >> Rip out everything not related to explicit load balancing implemented via > >> context engine maps and adjust the workloads to use it. > > > > Hmm, if this is on the table, should we also then restrict > > load-balancing wsim to gen11+ so that we can use the timed loops rather > > nop batches? That would be a huge selling point, and I'll just keep an > > old checkout around for nop load balancing with all the trimmings. > > That was my plan for the next step yes. Just taking your patch without > further changes would already make it work I think. But also at some > point I want to convert the engine selection (and engine naming in > descriptors) to class:instance. > > Why do you need the nop/old balancing stuff? I would hope going forward > we only need to compare current balancing against any changes. So I'd > really like to remoev the userspace balancing stuff. There are still some cases where i915 is beaten by plain old contexts, usually that is a combination of semaphores and interrupt latency, but some I just don't understand. There is still an uncomfortably large variation between kernel releases, and comparing the regressions in different balancers is useful to narrow down the problem. -Chris From chris at chris-wilson.co.uk Thu Jun 18 07:57:59 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 08:57:59 +0100 Subject: [Intel-gfx] [PATCH i-g-t 03/10] gem_wsim: Show workload timing stats In-Reply-To: <e7902369-6c97-c18b-728a-038a8d8c18ff@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-4-tvrtko.ursulin@linux.intel.com> <159241310169.19488.4644166988486362775@build.alporthouse.com> <e7902369-6c97-c18b-728a-038a8d8c18ff@linux.intel.com> Message-ID: <159246707980.4042.10689124567850438846@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 08:46:18) > > On 17/06/2020 17:58, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-17 17:01:13) > >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> > >> Show average/min/max workload iteration and dropped period stats when 'p' > >> command is used. > >> > >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> --- > >> benchmarks/gem_wsim.c | 19 +++++++++++++++---- > >> 1 file changed, 15 insertions(+), 4 deletions(-) > >> > >> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > >> index 9e5bfe6a36d4..60982cb73ba7 100644 > >> --- a/benchmarks/gem_wsim.c > >> +++ b/benchmarks/gem_wsim.c > >> @@ -2101,7 +2101,8 @@ static void *run_workload(void *data) > >> struct w_step *w; > >> int throttle = -1; > >> int qd_throttle = -1; > >> - int count; > >> + int count, missed = 0; > >> + unsigned long time_tot = 0, time_min = ULONG_MAX, time_max = 0; > >> int i; > >> > >> clock_gettime(CLOCK_MONOTONIC, &t_start); > >> @@ -2121,12 +2122,19 @@ static void *run_workload(void *data) > >> do_sleep = w->delay; > >> } else if (w->type == PERIOD) { > >> struct timespec now; > >> + int elapsed; > >> > >> clock_gettime(CLOCK_MONOTONIC, &now); > >> - do_sleep = w->period - > >> - elapsed_us(&wrk->repeat_start, &now); > >> + elapsed = elapsed_us(&wrk->repeat_start, &now); > >> + do_sleep = w->period - elapsed; > >> + time_tot += elapsed; > >> + if (elapsed < time_min) > >> + time_min = elapsed; > >> + if (elapsed > time_max) > >> + time_max = elapsed; > > > > Keep the running average? > > Could do but why? I already have the count so adding up total elapsed > frame time sound easiest. Because I was blind and didn't see it in the printf. -Chris From tvrtko.ursulin at linux.intel.com Thu Jun 18 08:01:10 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 09:01:10 +0100 Subject: [Intel-gfx] [PATCH i-g-t 06/10] gem_wsim: Support scaling workload batch durations In-Reply-To: <159241093617.19488.6127572319183957508@build.alporthouse.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-7-tvrtko.ursulin@linux.intel.com> <159241093617.19488.6127572319183957508@build.alporthouse.com> Message-ID: <ea8887b4-e5d7-2940-3c78-18785ee815ea@linux.intel.com> On 17/06/2020 17:22, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-17 17:01:16) >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> -f <float> on the command line can be used to scale batch buffer durations >> in all parsed workloads. > > But not the period? I had it scale both at some point but then it ended up more useful to only do batches. So I could stuff more clients in before saturation. I suppose that's an argument to have both independently controlled. Regards, Tvrtko From chris at chris-wilson.co.uk Thu Jun 18 08:02:03 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 09:02:03 +0100 Subject: [Intel-gfx] [PATCH i-g-t 08/10] gem_wsim: Snippet of a workload extracted from carchase In-Reply-To: <d38387a9-45c7-4138-8f65-0879f74f2f2d@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-9-tvrtko.ursulin@linux.intel.com> <159241590881.2739.7990352305579268212@build.alporthouse.com> <d38387a9-45c7-4138-8f65-0879f74f2f2d@linux.intel.com> Message-ID: <159246732394.4042.8495240313391590510@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 08:53:47) > > On 17/06/2020 18:45, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-17 17:01:18) > >> +1.RCS.1000.r3-47/w27-0/r0-58/r3-80/r22-31/r3-42/r9-4/w34-0/r3-18/r3-41/r21-0/r9-5/r3-78/r25-4/r3-104/r3-23/r30-0/r3-88/r22-27/r22-1/r25-45/r3-50/r22-12/r22-22/r22-3/r22-0/r25-56/r3-4/r22-15/r25-113/r3-7/r22-18/r25-60/r3-81/r25-21/r3-89/r18-5/r3-93/r17-8/r25-28/r25-87/r25-9/r25-13/r25-42/r25-90/r22-16/r34-2/r3-15/w3-64/r0-67/r25-99/r25-73/r3-6/r25-40/r3-90/r22-20/r0-45/r3-110/w32-17/w32-16/w32-3/w32-1/w33-2/r28-2/r3-98/r3-85/r25-48/r3-12/r25-104/r24-23/r3-87/r3-108/r3-26/r3-96/r22-5/r22-14/r3-49/r3-103/r22-6/r3-68/r3-112/r22-29/r22-28/r25-14/r25-44/r25-19/r3-67/r25-111/r18-4/r3-66/r18-17/r4-5/r25-68/r25-86/r25-26/r25-67/r3-37/r25-0/r22-7/r25-59/r25-71/r25-101/r25-75/r25-20/r25-91/r3-2/r3-117/r3-33/r22-2/r25-55/r25-66/r25-24/r25-105/r25-61/r25-11/r25-51/r25-64/r25-70/r18-19/r18-26/r18-21/r25-81/r25-78/r25-37/r25-50/r25-102/r25-35/r18-18/r18-13/r18-12/r3-69/r3-19/r3-100/r22-21/r25-22/r3-29/r25-93/r18-2/r18-14/r18-3/r22-10/r18-23/r18-7/r18-11/r3-73/r8-0/r25-92/r25-41/w33-3/r! > 0-1! > >> 07/w19-0. > >> 0 > > > > This patch has been mangled. > > Could it be your email client? (Very long lines in the patch.) I don't > see corruption anywhere on my side, or on the copy I received from the > mailing list. Somewhere in the chain, it's the same breakage in the file as well. It's not something I've seen before; and extremely strange choice for breaking the subsequent lines. Anyway, it did lead me to suggest to add printing the _token for the invalid step; and perhaps change that from "step" to "line"? -Chris From tvrtko.ursulin at linux.intel.com Thu Jun 18 08:06:49 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 09:06:49 +0100 Subject: [Intel-gfx] [PATCH i-g-t 05/10] gem_wsim: Support random buffer sizes In-Reply-To: <159241147774.19488.12762220143650374149@build.alporthouse.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-6-tvrtko.ursulin@linux.intel.com> <159241147774.19488.12762220143650374149@build.alporthouse.com> Message-ID: <78b0713b-a1a6-34d3-99f8-bdff1ed8a83d@linux.intel.com> On 17/06/2020 17:31, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-17 17:01:15) >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> See README for more details. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> --- >> benchmarks/gem_wsim.c | 71 +++++++++++++++++++++++++++++++++--------- >> benchmarks/wsim/README | 4 +++ >> 2 files changed, 61 insertions(+), 14 deletions(-) >> >> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c >> index 5893de38a98e..c1405596c46a 100644 >> --- a/benchmarks/gem_wsim.c >> +++ b/benchmarks/gem_wsim.c >> @@ -117,12 +117,18 @@ struct bond { >> enum intel_engine_id master; >> }; >> >> +struct work_buffer_size { >> + unsigned long size; >> + unsigned long min; >> + unsigned long max; >> +}; >> + >> struct working_set { >> int id; >> bool shared; >> unsigned int nr; >> uint32_t *handles; >> - unsigned long *sizes; >> + struct work_buffer_size *sizes; >> }; >> >> struct workload; >> @@ -203,6 +209,7 @@ struct workload >> bool print_stats; >> >> uint32_t bb_prng; >> + uint32_t bo_prng; >> >> struct timespec repeat_start; >> >> @@ -757,10 +764,12 @@ static int add_buffers(struct working_set *set, char *str) >> * 4m >> * 4g >> * 10n4k - 10 4k batches >> + * 4096-16k - random size in range >> */ >> - unsigned long *sizes, size; >> + struct work_buffer_size *sizes; >> + unsigned long min_sz, max_sz; >> + char *n, *max = NULL; >> unsigned int add, i; >> - char *n; >> >> n = index(str, 'n'); >> if (n) { >> @@ -773,16 +782,34 @@ static int add_buffers(struct working_set *set, char *str) >> add = 1; >> } >> >> - size = parse_size(str); >> - if (!size) >> + n = index(str, '-'); >> + if (n) { >> + *n = 0; >> + max = ++n; >> + } >> + >> + min_sz = parse_size(str); >> + if (!min_sz) >> return -1; >> >> + if (max) { >> + max_sz = parse_size(max); >> + if (!max_sz) >> + return -1; >> + } else { >> + max_sz = min_sz; >> + } >> + >> sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); >> if (!sizes) >> return -1; >> >> - for (i = 0; i < add; i++) >> - sizes[set->nr + i] = size; >> + for (i = 0; i < add; i++) { >> + struct work_buffer_size *sz = &sizes[set->nr + i]; >> + sz->min = min_sz; >> + sz->max = max_sz; >> + sz->size = 0; >> + } >> >> set->nr += add; >> set->sizes = sizes; >> @@ -824,7 +851,7 @@ static uint64_t engine_list_mask(const char *_str) >> return mask; >> } >> >> -static void allocate_working_set(struct working_set *set); >> +static void allocate_working_set(struct workload *wrk, struct working_set *set); >> >> #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ >> if ((field = strtok_r(fstart, ".", &fctx))) { \ >> @@ -1177,10 +1204,12 @@ add_step: >> >> wrk->nr_steps = nr_steps; >> wrk->steps = steps; >> + wrk->flags = flags; >> wrk->prio = arg->prio; >> wrk->sseu = arg->sseu; >> wrk->max_working_set_id = -1; >> wrk->working_sets = NULL; >> + wrk->bo_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); >> >> free(desc); >> >> @@ -1234,7 +1263,7 @@ add_step: >> */ >> for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { >> if (w->type == WORKINGSET && w->working_set.shared) >> - allocate_working_set(&w->working_set); >> + allocate_working_set(wrk, &w->working_set); >> } >> >> wrk->max_working_set_id = -1; >> @@ -1267,6 +1296,7 @@ clone_workload(struct workload *_wrk) >> igt_assert(wrk); >> memset(wrk, 0, sizeof(*wrk)); >> >> + wrk->flags = _wrk->flags; >> wrk->prio = _wrk->prio; >> wrk->sseu = _wrk->sseu; >> wrk->nr_steps = _wrk->nr_steps; > > wrk->flags wasn't introduced in this patch, why are we needing to copy > them now. > > I see wrk->bo_prn = flags & SYNC above, but I haven't seem them used > again later. They used to carry the balancer info and were setup in > main. Am I not mistaken in thinking they still are being set in main() > as well? I couldn't remember but looking around looks like you are right. I'll do some experiments and remove it if confirmed. Regards, Tvrtko From chris at chris-wilson.co.uk Thu Jun 18 08:07:45 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 09:07:45 +0100 Subject: [Intel-gfx] [PATCH i-g-t 06/10] gem_wsim: Support scaling workload batch durations In-Reply-To: <ea8887b4-e5d7-2940-3c78-18785ee815ea@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-7-tvrtko.ursulin@linux.intel.com> <159241093617.19488.6127572319183957508@build.alporthouse.com> <ea8887b4-e5d7-2940-3c78-18785ee815ea@linux.intel.com> Message-ID: <159246766519.4042.17567924336007381150@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 09:01:10) > > On 17/06/2020 17:22, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-17 17:01:16) > >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> > >> -f <float> on the command line can be used to scale batch buffer durations > >> in all parsed workloads. > > > > But not the period? > > I had it scale both at some point but then it ended up more useful to > only do batches. So I could stuff more clients in before saturation. I > suppose that's an argument to have both independently controlled. I was moreover trying to work out why one would want to. I was guessing shrink the duration and add more clients, and there you would the independent control, but if you just shrank the duration for a fixed number of clients, you would also want to shrink the period. -Chris From tvrtko.ursulin at linux.intel.com Thu Jun 18 08:13:06 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 09:13:06 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Always report the sample time for busy-stats In-Reply-To: <20200617130916.15261-2-chris@chris-wilson.co.uk> References: <20200617130916.15261-1-chris@chris-wilson.co.uk> <20200617130916.15261-2-chris@chris-wilson.co.uk> Message-ID: <d86f8c3c-c47a-282a-f5a9-212ef8da7935@linux.intel.com> On 17/06/2020 14:09, Chris Wilson wrote: > Return the monotonic timestamp (ktime_get()) at the time of sampling the > busy-time. This is used in preference to taking ktime_get() separately > before or after the read seqlock as there can be some large variance in > reported timestamps. For selftests trying to ascertain that we are > reporting accurate to within a few microseconds, even a small delay > leads to the test failing. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 3 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 12 ++-- > drivers/gpu/drm/i915/gt/intel_rps.c | 9 ++- > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 18 +++--- > drivers/gpu/drm/i915/i915_pmu.c | 5 +- > drivers/gpu/drm/i915/selftests/i915_request.c | 63 ++++++++++++------- > 6 files changed, 66 insertions(+), 44 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 791897f8d847..a9249a23903a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -334,7 +334,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, > struct drm_printer *m, > const char *header, ...); > > -ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine); > +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, > + ktime_t *now); > > struct i915_request * > intel_engine_find_active_request(struct intel_engine_cs *engine); > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 045179c65c44..c62b3cbdbbf9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -1595,7 +1595,8 @@ void intel_engine_dump(struct intel_engine_cs *engine, > intel_engine_print_breadcrumbs(engine, m); > } > > -static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) > +static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, > + ktime_t *now) > { > ktime_t total = engine->stats.total; > > @@ -1603,9 +1604,9 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) > * If the engine is executing something at the moment > * add it to the total. > */ > + *now = ktime_get(); > if (atomic_read(&engine->stats.active)) > - total = ktime_add(total, > - ktime_sub(ktime_get(), engine->stats.start)); > + total = ktime_add(total, ktime_sub(*now, engine->stats.start)); > > return total; > } > @@ -1613,17 +1614,18 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine) > /** > * intel_engine_get_busy_time() - Return current accumulated engine busyness > * @engine: engine to report on > + * @now: monotonic timestamp of sampling > * > * Returns accumulated time @engine was busy since engine stats were enabled. > */ > -ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine) > +ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) > { > unsigned int seq; > ktime_t total; > > do { > seq = read_seqbegin(&engine->stats.lock); > - total = __intel_engine_get_busy_time(engine); > + total = __intel_engine_get_busy_time(engine, now); > } while (read_seqretry(&engine->stats.lock, seq)); > > return total; > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 2f59fc6df3c2..bdece932592b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -53,13 +53,13 @@ static void rps_timer(struct timer_list *t) > struct intel_engine_cs *engine; > enum intel_engine_id id; > s64 max_busy[3] = {}; > - ktime_t dt, last; > + ktime_t dt, timestamp, last; > > for_each_engine(engine, rps_to_gt(rps), id) { > s64 busy; > int i; > > - dt = intel_engine_get_busy_time(engine); > + dt = intel_engine_get_busy_time(engine, ×tamp); > last = engine->stats.rps; > engine->stats.rps = dt; > > @@ -70,15 +70,14 @@ static void rps_timer(struct timer_list *t) > } > } > > - dt = ktime_get(); > last = rps->pm_timestamp; > - rps->pm_timestamp = dt; > + rps->pm_timestamp = timestamp; > > if (intel_rps_is_active(rps)) { > s64 busy; > int i; > > - dt = ktime_sub(dt, last); > + dt = ktime_sub(timestamp, last); > > /* > * Our goal is to evaluate each engine independently, so we run > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > index dd54dcb5cca2..b08fc5390e8a 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c > @@ -29,8 +29,8 @@ static int live_engine_busy_stats(void *arg) > GEM_BUG_ON(intel_gt_pm_is_awake(gt)); > for_each_engine(engine, gt, id) { > struct i915_request *rq; > - ktime_t de; > - u64 dt; > + ktime_t de, dt; > + ktime_t t[2]; > > if (!intel_engine_supports_stats(engine)) > continue; > @@ -47,12 +47,11 @@ static int live_engine_busy_stats(void *arg) > > ENGINE_TRACE(engine, "measuring idle time\n"); > preempt_disable(); > - dt = ktime_to_ns(ktime_get()); > - de = intel_engine_get_busy_time(engine); > + de = intel_engine_get_busy_time(engine, &t[0]); > udelay(100); > - de = ktime_sub(intel_engine_get_busy_time(engine), de); > - dt = ktime_to_ns(ktime_get()) - dt; > + de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de); > preempt_enable(); > + dt = ktime_sub(t[1], t[0]); > if (de < 0 || de > 10) { > pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n", > engine->name, > @@ -80,12 +79,11 @@ static int live_engine_busy_stats(void *arg) > > ENGINE_TRACE(engine, "measuring busy time\n"); > preempt_disable(); > - dt = ktime_to_ns(ktime_get()); > - de = intel_engine_get_busy_time(engine); > + de = intel_engine_get_busy_time(engine, &t[0]); > udelay(100); > - de = ktime_sub(intel_engine_get_busy_time(engine), de); > - dt = ktime_to_ns(ktime_get()) - dt; > + de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de); > preempt_enable(); > + dt = ktime_sub(t[1], t[0]); > if (100 * de < 95 * dt || 95 * de > 100 * dt) { > pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n", > engine->name, > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 802837de1767..28bc5f13ae52 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -565,7 +565,10 @@ static u64 __i915_pmu_event_read(struct perf_event *event) > /* Do nothing */ > } else if (sample == I915_SAMPLE_BUSY && > intel_engine_supports_stats(engine)) { > - val = ktime_to_ns(intel_engine_get_busy_time(engine)); > + ktime_t unused; > + > + val = ktime_to_ns(intel_engine_get_busy_time(engine, > + &unused)); > } else { > val = engine->pmu.sample[sample].cur; > } > diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c > index 06d18aae070b..9271aad7f779 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_request.c > +++ b/drivers/gpu/drm/i915/selftests/i915_request.c > @@ -2492,9 +2492,11 @@ static int perf_series_engines(void *arg) > intel_engine_pm_get(p->engine); > > if (intel_engine_supports_stats(p->engine)) > - p->busy = intel_engine_get_busy_time(p->engine) + 1; > + p->busy = intel_engine_get_busy_time(p->engine, > + &p->time) + 1; > + else > + p->time = ktime_get(); > p->runtime = -intel_context_get_total_runtime_ns(ce); > - p->time = ktime_get(); > } > > err = (*fn)(ps); > @@ -2505,13 +2507,15 @@ static int perf_series_engines(void *arg) > struct perf_stats *p = &stats[idx]; > struct intel_context *ce = ps->ce[idx]; > int integer, decimal; > - u64 busy, dt; > + u64 busy, dt, now; > > - p->time = ktime_sub(ktime_get(), p->time); > - if (p->busy) { > - p->busy = ktime_sub(intel_engine_get_busy_time(p->engine), > + if (p->busy) > + p->busy = ktime_sub(intel_engine_get_busy_time(p->engine, > + &now), > p->busy - 1); > - } > + else > + now = ktime_get(); > + p->time = ktime_sub(now, p->time); > > err = switch_to_kernel_sync(ce, err); > p->runtime += intel_context_get_total_runtime_ns(ce); > @@ -2571,13 +2575,14 @@ static int p_sync0(void *arg) > return err; > } > > - busy = false; > if (intel_engine_supports_stats(engine)) { > - p->busy = intel_engine_get_busy_time(engine); > + p->busy = intel_engine_get_busy_time(engine, &p->time); > busy = true; > + } else { > + p->time = ktime_get(); > + busy = false; > } > > - p->time = ktime_get(); > count = 0; > do { > struct i915_request *rq; > @@ -2600,11 +2605,15 @@ static int p_sync0(void *arg) > > count++; > } while (!__igt_timeout(end_time, NULL)); > - p->time = ktime_sub(ktime_get(), p->time); > > if (busy) { > - p->busy = ktime_sub(intel_engine_get_busy_time(engine), > + ktime_t now; > + > + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), > p->busy); > + p->time = ktime_sub(now, p->time); > + } else { > + p->time = ktime_sub(ktime_get(), p->time); > } > > err = switch_to_kernel_sync(ce, err); > @@ -2637,13 +2646,14 @@ static int p_sync1(void *arg) > return err; > } > > - busy = false; > if (intel_engine_supports_stats(engine)) { > - p->busy = intel_engine_get_busy_time(engine); > + p->busy = intel_engine_get_busy_time(engine, &p->time); > busy = true; > + } else { > + p->time = ktime_get(); > + busy = false; > } > > - p->time = ktime_get(); > count = 0; > do { > struct i915_request *rq; > @@ -2668,11 +2678,15 @@ static int p_sync1(void *arg) > count++; > } while (!__igt_timeout(end_time, NULL)); > i915_request_put(prev); > - p->time = ktime_sub(ktime_get(), p->time); > > if (busy) { > - p->busy = ktime_sub(intel_engine_get_busy_time(engine), > + ktime_t now; > + > + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), > p->busy); > + p->time = ktime_sub(now, p->time); > + } else { > + p->time = ktime_sub(ktime_get(), p->time); > } > > err = switch_to_kernel_sync(ce, err); > @@ -2704,14 +2718,15 @@ static int p_many(void *arg) > return err; > } > > - busy = false; > if (intel_engine_supports_stats(engine)) { > - p->busy = intel_engine_get_busy_time(engine); > + p->busy = intel_engine_get_busy_time(engine, &p->time); > busy = true; > + } else { > + p->time = ktime_get(); > + busy = false; > } > > count = 0; > - p->time = ktime_get(); > do { > struct i915_request *rq; > > @@ -2724,11 +2739,15 @@ static int p_many(void *arg) > i915_request_add(rq); > count++; > } while (!__igt_timeout(end_time, NULL)); > - p->time = ktime_sub(ktime_get(), p->time); > > if (busy) { > - p->busy = ktime_sub(intel_engine_get_busy_time(engine), > + ktime_t now; > + > + p->busy = ktime_sub(intel_engine_get_busy_time(engine, &now), > p->busy); > + p->time = ktime_sub(now, p->time); > + } else { > + p->time = ktime_sub(ktime_get(), p->time); > } > > err = switch_to_kernel_sync(ce, err); > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From mika.kuoppala at linux.intel.com Thu Jun 18 08:53:20 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Thu, 18 Jun 2020 11:53:20 +0300 Subject: [Intel-gfx] [CI] drm/i915/selftests: Check preemption rollback of different ring queue depths In-Reply-To: <20200616233733.18050-1-chris@chris-wilson.co.uk> References: <20200616233733.18050-1-chris@chris-wilson.co.uk> Message-ID: <87lfkk92m7.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > Like live_unlite_ring, but instead of simply looking at the impact of > intel_ring_direction(), check that preemption more generally works with > different depths of queued requests in the ring. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 163 +++++++++++++++++++++++++ > 1 file changed, 163 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index b8b7b91019f4..4f3758a1cbcf 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -2758,6 +2758,168 @@ static int create_gang(struct intel_engine_cs *engine, > return err; > } > > +static int __live_preempt_ring(struct intel_engine_cs *engine, > + struct igt_spinner *spin, > + int queue_sz, int ring_sz) > +{ > + struct intel_context *ce[2] = {}; > + struct i915_request *rq; > + struct igt_live_test t; > + int err = 0; > + int n; > + > + if (igt_live_test_begin(&t, engine->i915, __func__, engine->name)) > + return -EIO; > + > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + struct intel_context *tmp; > + > + tmp = intel_context_create(engine); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + goto err_ce; > + } > + > + tmp->ring = __intel_context_ring_size(ring_sz); Unexpected way of passing the size. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > + > + err = intel_context_pin(tmp); > + if (err) { > + intel_context_put(tmp); > + goto err_ce; > + } > + > + memset32(tmp->ring->vaddr, > + 0xdeadbeef, /* trigger a hang if executed */ > + tmp->ring->vma->size / sizeof(u32)); > + > + ce[n] = tmp; > + } > + > + rq = igt_spinner_create_request(spin, ce[0], MI_ARB_CHECK); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + i915_request_get(rq); > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > + i915_request_add(rq); > + > + if (!igt_wait_for_spinner(spin, rq)) { > + intel_gt_set_wedged(engine->gt); > + i915_request_put(rq); > + err = -ETIME; > + goto err_ce; > + } > + > + /* Fill the ring, until we will cause a wrap */ > + n = 0; > + while (ce[0]->ring->tail - rq->wa_tail <= queue_sz) { > + struct i915_request *tmp; > + > + tmp = intel_context_create_request(ce[0]); > + if (IS_ERR(tmp)) { > + err = PTR_ERR(tmp); > + i915_request_put(rq); > + goto err_ce; > + } > + > + i915_request_add(tmp); > + intel_engine_flush_submission(engine); > + n++; > + } > + intel_engine_flush_submission(engine); > + pr_debug("%s: Filled %d with %d nop tails {size:%x, tail:%x, emit:%x, rq.tail:%x}\n", > + engine->name, queue_sz, n, > + ce[0]->ring->size, > + ce[0]->ring->tail, > + ce[0]->ring->emit, > + rq->tail); > + i915_request_put(rq); > + > + /* Create a second request to preempt the first ring */ > + rq = intel_context_create_request(ce[1]); > + if (IS_ERR(rq)) { > + err = PTR_ERR(rq); > + goto err_ce; > + } > + > + rq->sched.attr.priority = I915_PRIORITY_BARRIER; > + i915_request_get(rq); > + i915_request_add(rq); > + > + err = wait_for_submit(engine, rq, HZ / 2); > + i915_request_put(rq); > + if (err) { > + pr_err("%s: preemption request was not submited\n", > + engine->name); > + err = -ETIME; > + } > + > + pr_debug("%s: ring[0]:{ tail:%x, emit:%x }, ring[1]:{ tail:%x, emit:%x }\n", > + engine->name, > + ce[0]->ring->tail, ce[0]->ring->emit, > + ce[1]->ring->tail, ce[1]->ring->emit); > + > +err_ce: > + intel_engine_flush_submission(engine); > + igt_spinner_end(spin); > + for (n = 0; n < ARRAY_SIZE(ce); n++) { > + if (IS_ERR_OR_NULL(ce[n])) > + break; > + > + intel_context_unpin(ce[n]); > + intel_context_put(ce[n]); > + } > + if (igt_live_test_end(&t)) > + err = -EIO; > + return err; > +} > + > +static int live_preempt_ring(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + struct igt_spinner spin; > + enum intel_engine_id id; > + int err = 0; > + > + /* > + * Check that we rollback large chunks of a ring in order to do a > + * preemption event. Similar to live_unlite_ring, but looking at > + * ring size rather than the impact of intel_ring_direction(). > + */ > + > + if (igt_spinner_init(&spin, gt)) > + return -ENOMEM; > + > + for_each_engine(engine, gt, id) { > + int n; > + > + if (!intel_engine_has_preemption(engine)) > + continue; > + > + if (!intel_engine_can_store_dword(engine)) > + continue; > + > + engine_heartbeat_disable(engine); > + > + for (n = 0; n <= 3; n++) { > + err = __live_preempt_ring(engine, &spin, > + n * SZ_4K / 4, SZ_4K); > + if (err) > + break; > + } > + > + engine_heartbeat_enable(engine); > + if (err) > + break; > + } > + > + igt_spinner_fini(&spin); > + return err; > +} > + > static int live_preempt_gang(void *arg) > { > struct intel_gt *gt = arg; > @@ -4540,6 +4702,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915) > SUBTEST(live_preempt_cancel), > SUBTEST(live_suppress_self_preempt), > SUBTEST(live_chain_preempt), > + SUBTEST(live_preempt_ring), > SUBTEST(live_preempt_gang), > SUBTEST(live_preempt_timeout), > SUBTEST(live_preempt_user), > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From tvrtko.ursulin at linux.intel.com Thu Jun 18 09:05:56 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 10:05:56 +0100 Subject: [Intel-gfx] [PATCH i-g-t 02/10] gem_wsim: Buffer objects working sets and complex dependencies In-Reply-To: <159241302236.19488.10161905992897259551@build.alporthouse.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-3-tvrtko.ursulin@linux.intel.com> <159241302236.19488.10161905992897259551@build.alporthouse.com> Message-ID: <a05d07a2-8f65-cfbd-2c16-83bfe81cfdd3@linux.intel.com> On 17/06/2020 17:57, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-17 17:01:12) >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> >> Add support for defining buffer object working sets and targetting them as >> data dependencies. For more information please see the README file. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> --- >> benchmarks/gem_wsim.c | 453 +++++++++++++++++++++--- >> benchmarks/wsim/README | 59 +++ >> benchmarks/wsim/cloud-gaming-60fps.wsim | 11 + >> benchmarks/wsim/composited-ui.wsim | 7 + >> 4 files changed, 476 insertions(+), 54 deletions(-) >> create mode 100644 benchmarks/wsim/cloud-gaming-60fps.wsim >> create mode 100644 benchmarks/wsim/composited-ui.wsim >> >> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c >> index 02fe8f5a5e69..9e5bfe6a36d4 100644 >> --- a/benchmarks/gem_wsim.c >> +++ b/benchmarks/gem_wsim.c >> @@ -88,14 +88,21 @@ enum w_type >> LOAD_BALANCE, >> BOND, >> TERMINATE, >> - SSEU >> + SSEU, >> + WORKINGSET, >> +}; >> + >> +struct dep_entry { >> + int target; >> + bool write; >> + int working_set; /* -1 = step dependecy, >= 0 working set id */ >> }; >> >> struct deps >> { >> int nr; >> bool submit_fence; >> - int *list; >> + struct dep_entry *list; >> }; >> >> struct w_arg { >> @@ -110,6 +117,14 @@ struct bond { >> enum intel_engine_id master; >> }; >> >> +struct working_set { >> + int id; >> + bool shared; >> + unsigned int nr; >> + uint32_t *handles; >> + unsigned long *sizes; >> +}; >> + >> struct workload; >> >> struct w_step >> @@ -143,6 +158,7 @@ struct w_step >> enum intel_engine_id bond_master; >> }; >> int sseu; >> + struct working_set working_set; >> }; >> >> /* Implementation details */ >> @@ -193,6 +209,9 @@ struct workload >> unsigned int nr_ctxs; >> struct ctx *ctx_list; >> >> + struct working_set **working_sets; /* array indexed by set id */ >> + int max_working_set_id; >> + >> int sync_timeline; >> uint32_t sync_seqno; >> >> @@ -281,11 +300,120 @@ print_engine_calibrations(void) >> printf("\n"); >> } >> >> +static void add_dep(struct deps *deps, struct dep_entry entry) >> +{ >> + deps->list = realloc(deps->list, sizeof(*deps->list) * (deps->nr + 1)); >> + igt_assert(deps->list); >> + >> + deps->list[deps->nr++] = entry; >> +} >> + >> + >> +static int >> +parse_dependency(unsigned int nr_steps, struct w_step *w, char *str) >> +{ >> + struct dep_entry entry = { .working_set = -1 }; >> + bool submit_fence = false; >> + char *s; >> + >> + switch (str[0]) { >> + case '-': >> + if (str[1] < '0' || str[1] > '9') >> + return -1; >> + >> + entry.target = atoi(str); >> + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) >> + return -1; > > add_dep for N steps ago, using a handle. > >> + >> + add_dep(&w->data_deps, entry); >> + >> + break; >> + case 's': >> + submit_fence = true; >> + /* Fall-through. */ >> + case 'f': >> + /* Multiple fences not yet supported. */ >> + igt_assert_eq(w->fence_deps.nr, 0); >> + >> + entry.target = atoi(++str); >> + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) >> + return -1; >> + >> + add_dep(&w->fence_deps, entry); >> + >> + w->fence_deps.submit_fence = submit_fence; > > add_dep for N steps ago, using the out-fence from that step > [A post processing steps adds emit_fence to the earlier steps.] > >> + break; >> + case 'w': >> + entry.write = true; > > Got confused for a moment as I was expecting the submit_fence > fallthrough pattern. >> + /* Fall-through. */ >> + case 'r': >> + /* >> + * [rw]N-<str> >> + * r1-<str> or w2-<str>, where N is working set id. >> + */ >> + s = index(++str, '-'); >> + if (!s) >> + return -1; >> + >> + entry.working_set = atoi(str); > > if (entry.working_set < 0) > return -1; Yep. > >> + >> + if (parse_working_set_deps(w->wrk, &w->data_deps, entry, ++s)) >> + return -1; > > The new one... > >> +static int >> +parse_working_set_deps(struct workload *wrk, >> + struct deps *deps, >> + struct dep_entry _entry, >> + char *str) >> +{ >> + /* >> + * 1 - target handle index in the specified working set. >> + * 2-4 - range >> + */ >> + struct dep_entry entry = _entry; >> + char *s; >> + >> + s = index(str, '-'); >> + if (s) { >> + int from, to; >> + >> + from = atoi(str); >> + if (from < 0) >> + return -1; >> + >> + to = atoi(++s); >> + if (to <= 0) >> + return -1; > > if to < from, we add nothing. Is that worth the error? Yep. > >> + >> + for (entry.target = from; entry.target <= to; entry.target++) >> + add_dep(deps, entry); >> + } else { >> + entry.target = atoi(str); >> + if (entry.target < 0) >> + return -1; >> + >> + add_dep(deps, entry); > > >> + } >> + >> + return 0; >> +} >> + >> + break; >> + default: >> + return -1; >> + }; >> + >> + return 0; >> +} >> + >> static int >> parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) >> { >> char *desc = strdup(_desc); >> char *token, *tctx = NULL, *tstart = desc; >> + int ret = 0; >> + >> + if (!strcmp(_desc, "0")) >> + goto out; > > Hang on, what this special case? For no dependencies. If I move the check to parse_dependency then dependency of "0/0/0/0" would be silently accepted. It wouldn't be a big deal, who cares, but I thought it is better to be more strict. > >> >> igt_assert(desc); >> igt_assert(!w->data_deps.nr && w->data_deps.nr == w->fence_deps.nr); >> static void __attribute__((format(printf, 1, 2))) >> @@ -624,6 +722,88 @@ static int parse_engine_map(struct w_step *step, const char *_str) >> return 0; >> } >> >> +static unsigned long parse_size(char *str) >> +{ > /* "1234567890[gGmMkK]" */ >> + const unsigned int len = strlen(str); >> + unsigned int mult = 1; >> + >> + if (len == 0) >> + return 0; >> + >> + switch (str[len - 1]) { > > T? P? E? Let's plan ahead! :) Error on unrecognized non-digit? Ok. > >> + case 'g': >> + case 'G': >> + mult *= 1024; >> + /* Fall-throuogh. */ >> + case 'm': >> + case 'M': >> + mult *= 1024; >> + /* Fall-throuogh. */ >> + case 'k': >> + case 'K': >> + mult *= 1024; >> + >> + str[len - 1] = 0; >> + } >> + >> + return atol(str) * mult; > > Negatives? Ok. > >> +} >> + >> +static int add_buffers(struct working_set *set, char *str) >> +{ >> + /* >> + * 4096 >> + * 4k >> + * 4m >> + * 4g >> + * 10n4k - 10 4k batches >> + */ >> + unsigned long *sizes, size; >> + unsigned int add, i; >> + char *n; >> + >> + n = index(str, 'n'); >> + if (n) { >> + *n = 0; >> + add = atoi(str); >> + if (!add) >> + return -1; > > if (add <= 0) [int add goes without saying then] Yep. > >> + str = ++n; >> + } else { >> + add = 1; >> + } >> + >> + size = parse_size(str); >> + if (!size) >> + return -1; >> + >> + sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); >> + if (!sizes) >> + return -1; >> + >> + for (i = 0; i < add; i++) >> + sizes[set->nr + i] = size; >> + >> + set->nr += add; >> + set->sizes = sizes; >> + >> + return 0; >> +} > >> @@ -1003,6 +1209,51 @@ add_step: >> } >> } >> >> + /* >> + * Check no duplicate working set ids. >> + */ >> + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { >> + struct w_step *w2; >> + >> + if (w->type != WORKINGSET) >> + continue; >> + >> + for (j = 0, w2 = wrk->steps; j < wrk->nr_steps; w2++, j++) { >> + if (j == i) >> + continue; >> + if (w2->type != WORKINGSET) >> + continue; >> + >> + check_arg(w->working_set.id == w2->working_set.id, >> + "Duplicate working set id at %u!\n", j); >> + } >> + } >> + >> + /* >> + * Allocate shared working sets. >> + */ >> + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { >> + if (w->type == WORKINGSET && w->working_set.shared) >> + allocate_working_set(&w->working_set); >> + } >> + >> + wrk->max_working_set_id = -1; >> + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { >> + if (w->type == WORKINGSET && >> + w->working_set.shared && >> + w->working_set.id > wrk->max_working_set_id) >> + wrk->max_working_set_id = w->working_set.id; >> + } >> + >> + wrk->working_sets = calloc(wrk->max_working_set_id + 1, >> + sizeof(*wrk->working_sets)); >> + igt_assert(wrk->working_sets); >> + >> + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { >> + if (w->type == WORKINGSET && w->working_set.shared) >> + wrk->working_sets[w->working_set.id] = &w->working_set; >> + } > > Ok, sharing works by reusing the same set of handles within the process. > > Is there room in the parser namespace for dmabuf sharing? Plenty of unused characters. :) Regards, Tvrtko From chris at chris-wilson.co.uk Thu Jun 18 09:22:59 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 10:22:59 +0100 Subject: [Intel-gfx] [PATCH i-g-t 02/10] gem_wsim: Buffer objects working sets and complex dependencies In-Reply-To: <a05d07a2-8f65-cfbd-2c16-83bfe81cfdd3@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-3-tvrtko.ursulin@linux.intel.com> <159241302236.19488.10161905992897259551@build.alporthouse.com> <a05d07a2-8f65-cfbd-2c16-83bfe81cfdd3@linux.intel.com> Message-ID: <159247217901.4042.14297182857579041618@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 10:05:56) > > On 17/06/2020 17:57, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-17 17:01:12) > >> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> > >> Add support for defining buffer object working sets and targetting them as > >> data dependencies. For more information please see the README file. > >> > >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >> --- > >> benchmarks/gem_wsim.c | 453 +++++++++++++++++++++--- > >> benchmarks/wsim/README | 59 +++ > >> benchmarks/wsim/cloud-gaming-60fps.wsim | 11 + > >> benchmarks/wsim/composited-ui.wsim | 7 + > >> 4 files changed, 476 insertions(+), 54 deletions(-) > >> create mode 100644 benchmarks/wsim/cloud-gaming-60fps.wsim > >> create mode 100644 benchmarks/wsim/composited-ui.wsim > >> > >> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c > >> index 02fe8f5a5e69..9e5bfe6a36d4 100644 > >> --- a/benchmarks/gem_wsim.c > >> +++ b/benchmarks/gem_wsim.c > >> @@ -88,14 +88,21 @@ enum w_type > >> LOAD_BALANCE, > >> BOND, > >> TERMINATE, > >> - SSEU > >> + SSEU, > >> + WORKINGSET, > >> +}; > >> + > >> +struct dep_entry { > >> + int target; > >> + bool write; > >> + int working_set; /* -1 = step dependecy, >= 0 working set id */ > >> }; > >> > >> struct deps > >> { > >> int nr; > >> bool submit_fence; > >> - int *list; > >> + struct dep_entry *list; > >> }; > >> > >> struct w_arg { > >> @@ -110,6 +117,14 @@ struct bond { > >> enum intel_engine_id master; > >> }; > >> > >> +struct working_set { > >> + int id; > >> + bool shared; > >> + unsigned int nr; > >> + uint32_t *handles; > >> + unsigned long *sizes; > >> +}; > >> + > >> struct workload; > >> > >> struct w_step > >> @@ -143,6 +158,7 @@ struct w_step > >> enum intel_engine_id bond_master; > >> }; > >> int sseu; > >> + struct working_set working_set; > >> }; > >> > >> /* Implementation details */ > >> @@ -193,6 +209,9 @@ struct workload > >> unsigned int nr_ctxs; > >> struct ctx *ctx_list; > >> > >> + struct working_set **working_sets; /* array indexed by set id */ > >> + int max_working_set_id; > >> + > >> int sync_timeline; > >> uint32_t sync_seqno; > >> > >> @@ -281,11 +300,120 @@ print_engine_calibrations(void) > >> printf("\n"); > >> } > >> > >> +static void add_dep(struct deps *deps, struct dep_entry entry) > >> +{ > >> + deps->list = realloc(deps->list, sizeof(*deps->list) * (deps->nr + 1)); > >> + igt_assert(deps->list); > >> + > >> + deps->list[deps->nr++] = entry; > >> +} > >> + > >> + > >> +static int > >> +parse_dependency(unsigned int nr_steps, struct w_step *w, char *str) > >> +{ > >> + struct dep_entry entry = { .working_set = -1 }; > >> + bool submit_fence = false; > >> + char *s; > >> + > >> + switch (str[0]) { > >> + case '-': > >> + if (str[1] < '0' || str[1] > '9') > >> + return -1; > >> + > >> + entry.target = atoi(str); > >> + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) > >> + return -1; > > > > add_dep for N steps ago, using a handle. > > > >> + > >> + add_dep(&w->data_deps, entry); > >> + > >> + break; > >> + case 's': > >> + submit_fence = true; > >> + /* Fall-through. */ > >> + case 'f': > >> + /* Multiple fences not yet supported. */ > >> + igt_assert_eq(w->fence_deps.nr, 0); > >> + > >> + entry.target = atoi(++str); > >> + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) > >> + return -1; > >> + > >> + add_dep(&w->fence_deps, entry); > >> + > >> + w->fence_deps.submit_fence = submit_fence; > > > > add_dep for N steps ago, using the out-fence from that step > > [A post processing steps adds emit_fence to the earlier steps.] > > > >> + break; > >> + case 'w': > >> + entry.write = true; > > > > Got confused for a moment as I was expecting the submit_fence > > fallthrough pattern. > >> + /* Fall-through. */ > >> + case 'r': > >> + /* > >> + * [rw]N-<str> > >> + * r1-<str> or w2-<str>, where N is working set id. > >> + */ > >> + s = index(++str, '-'); > >> + if (!s) > >> + return -1; > >> + > >> + entry.working_set = atoi(str); > > > > if (entry.working_set < 0) > > return -1; > > Yep. > > > > >> + > >> + if (parse_working_set_deps(w->wrk, &w->data_deps, entry, ++s)) > >> + return -1; > > > > The new one... > > > >> +static int > >> +parse_working_set_deps(struct workload *wrk, > >> + struct deps *deps, > >> + struct dep_entry _entry, > >> + char *str) > >> +{ > >> + /* > >> + * 1 - target handle index in the specified working set. > >> + * 2-4 - range > >> + */ > >> + struct dep_entry entry = _entry; > >> + char *s; > >> + > >> + s = index(str, '-'); > >> + if (s) { > >> + int from, to; > >> + > >> + from = atoi(str); > >> + if (from < 0) > >> + return -1; > >> + > >> + to = atoi(++s); > >> + if (to <= 0) > >> + return -1; > > > > if to < from, we add nothing. Is that worth the error? > > Yep. > > > > >> + > >> + for (entry.target = from; entry.target <= to; entry.target++) > >> + add_dep(deps, entry); > >> + } else { > >> + entry.target = atoi(str); > >> + if (entry.target < 0) > >> + return -1; > >> + > >> + add_dep(deps, entry); > > > > > >> + } > >> + > >> + return 0; > >> +} > >> + > >> + break; > >> + default: > >> + return -1; > >> + }; > >> + > >> + return 0; > >> +} > >> + > >> static int > >> parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) > >> { > >> char *desc = strdup(_desc); > >> char *token, *tctx = NULL, *tstart = desc; > >> + int ret = 0; > >> + > >> + if (!strcmp(_desc, "0")) > >> + goto out; > > > > Hang on, what this special case? > > For no dependencies. > > If I move the check to parse_dependency then dependency of "0/0/0/0" > would be silently accepted. It wouldn't be a big deal, who cares, but I > thought it is better to be more strict. It was just not clear at this point what is being matched, what the meaning of 0 is. /* 0 refers to self, a degenerate dependency */ ? -Chris From chris at chris-wilson.co.uk Thu Jun 18 09:50:14 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 10:50:14 +0100 Subject: [Intel-gfx] [PATCH i-g-t] tests: Move perf/perf_pmu under i915 Message-ID: <20200618095014.252677-1-chris@chris-wilson.co.uk> These are i915 specific tests of the perf and perf-workalike interfaces, so move them under i915/ Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- tests/Makefile.sources | 8 ++++++-- tests/{ => i915}/perf.c | 0 tests/{ => i915}/perf_pmu.c | 0 tests/meson.build | 6 ++++-- 4 files changed, 10 insertions(+), 4 deletions(-) rename tests/{ => i915}/perf.c (100%) rename tests/{ => i915}/perf_pmu.c (100%) diff --git a/tests/Makefile.sources b/tests/Makefile.sources index eaa6c0d04..af900bcfc 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -88,8 +88,6 @@ TESTS_progs = \ kms_vblank \ kms_vrr \ meta_test \ - perf \ - perf_pmu \ prime_busy \ prime_mmap \ prime_mmap_coherency \ @@ -115,6 +113,12 @@ sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c TESTS_progs += sysfs_timeslice_duration sysfs_timeslice_duration_SOURCES = i915/sysfs_timeslice_duration.c +TESTS_progs += perf +perf_SOURCES = i915/perf.c + +TESTS_progs += perf_pmu +perf_pmu_SOURCES = i915/perf_pmu.c + TESTS_progs += gem_bad_reloc gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c diff --git a/tests/perf.c b/tests/i915/perf.c similarity index 100% rename from tests/perf.c rename to tests/i915/perf.c diff --git a/tests/perf_pmu.c b/tests/i915/perf_pmu.c similarity index 100% rename from tests/perf_pmu.c rename to tests/i915/perf_pmu.c diff --git a/tests/meson.build b/tests/meson.build index e69bdb7d0..28091794f 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -336,14 +336,16 @@ test_executables += executable('i915_pm_rc6_residency', install : true) test_list += 'i915_pm_rc6_residency' -test_executables += executable('perf_pmu', 'perf_pmu.c', +test_executables += executable('perf_pmu', + join_paths('i915', 'perf_pmu.c'), dependencies : test_deps + [ lib_igt_perf ], install_dir : libexecdir, install_rpath : libexecdir_rpathdir, install : true) test_list += 'perf_pmu' -test_executables += executable('perf', 'perf.c', +test_executables += executable('perf', + join_paths('i915', 'perf.c'), dependencies : test_deps + [ lib_igt_i915_perf ], install_dir : libexecdir, install_rpath : libexecdir_rpathdir, -- 2.27.0 From lionel.g.landwerlin at intel.com Thu Jun 18 09:52:28 2020 From: lionel.g.landwerlin at intel.com (Lionel Landwerlin) Date: Thu, 18 Jun 2020 12:52:28 +0300 Subject: [Intel-gfx] [PATCH i-g-t] tests: Move perf/perf_pmu under i915 In-Reply-To: <20200618095014.252677-1-chris@chris-wilson.co.uk> References: <20200618095014.252677-1-chris@chris-wilson.co.uk> Message-ID: <1fb2b246-ce6c-1e06-68a7-6a4e968aa6d5@intel.com> On 18/06/2020 12:50, Chris Wilson wrote: > These are i915 specific tests of the perf and perf-workalike interfaces, > so move them under i915/ > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com> > --- > tests/Makefile.sources | 8 ++++++-- > tests/{ => i915}/perf.c | 0 > tests/{ => i915}/perf_pmu.c | 0 > tests/meson.build | 6 ++++-- > 4 files changed, 10 insertions(+), 4 deletions(-) > rename tests/{ => i915}/perf.c (100%) > rename tests/{ => i915}/perf_pmu.c (100%) > > diff --git a/tests/Makefile.sources b/tests/Makefile.sources > index eaa6c0d04..af900bcfc 100644 > --- a/tests/Makefile.sources > +++ b/tests/Makefile.sources > @@ -88,8 +88,6 @@ TESTS_progs = \ > kms_vblank \ > kms_vrr \ > meta_test \ > - perf \ > - perf_pmu \ > prime_busy \ > prime_mmap \ > prime_mmap_coherency \ > @@ -115,6 +113,12 @@ sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c > TESTS_progs += sysfs_timeslice_duration > sysfs_timeslice_duration_SOURCES = i915/sysfs_timeslice_duration.c > > +TESTS_progs += perf > +perf_SOURCES = i915/perf.c > + > +TESTS_progs += perf_pmu > +perf_pmu_SOURCES = i915/perf_pmu.c > + > TESTS_progs += gem_bad_reloc > gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c > > diff --git a/tests/perf.c b/tests/i915/perf.c > similarity index 100% > rename from tests/perf.c > rename to tests/i915/perf.c > diff --git a/tests/perf_pmu.c b/tests/i915/perf_pmu.c > similarity index 100% > rename from tests/perf_pmu.c > rename to tests/i915/perf_pmu.c > diff --git a/tests/meson.build b/tests/meson.build > index e69bdb7d0..28091794f 100644 > --- a/tests/meson.build > +++ b/tests/meson.build > @@ -336,14 +336,16 @@ test_executables += executable('i915_pm_rc6_residency', > install : true) > test_list += 'i915_pm_rc6_residency' > > -test_executables += executable('perf_pmu', 'perf_pmu.c', > +test_executables += executable('perf_pmu', > + join_paths('i915', 'perf_pmu.c'), > dependencies : test_deps + [ lib_igt_perf ], > install_dir : libexecdir, > install_rpath : libexecdir_rpathdir, > install : true) > test_list += 'perf_pmu' > > -test_executables += executable('perf', 'perf.c', > +test_executables += executable('perf', > + join_paths('i915', 'perf.c'), > dependencies : test_deps + [ lib_igt_i915_perf ], > install_dir : libexecdir, > install_rpath : libexecdir_rpathdir, From dyoung at redhat.com Thu Jun 18 09:54:01 2020 From: dyoung at redhat.com (dyoung at redhat.com) Date: Thu, 18 Jun 2020 17:54:01 +0800 Subject: [Intel-gfx] i915/kexec: warning at drivers/gpu/drm/i915/display/intel_psr.c:782 intel_psr_activate+0x3c6/0x440 In-Reply-To: <b9abdee84e2465da720d2c44e80ba286470f7f3d.camel@intel.com> References: <20200617065315.GA6501@dhcp-128-65.nay.redhat.com> <b9abdee84e2465da720d2c44e80ba286470f7f3d.camel@intel.com> Message-ID: <20200618095401.GB8527@dhcp-128-65.nay.redhat.com> Hi Souza, On 06/17/20 at 05:34pm, Souza, Jose wrote: > Hi Dave > > Will take care of this, looks like PSR2 was left enabled by UEFI/BIOS then i915 enables PSR1.Are you affected by any visual glitches or other issues? Thanks you. I do not see visual glitches and other issues other than the warning. > Could you attach a log with drm.debug=0x1e set? It seems a lot of output with the debug option enabled, will send to you separately with an attachment. > > Thanks > > On Wed, 2020-06-17 at 14:53 +0800, Dave Young wrote: > > Hi, > > > > This warning exists for long time, I did not find time to report, here > > is the latest kernel logs, can you please to have a look? > > > > hardware: Thinkpad T480s > > lspci: 00:02.0 VGA compatible controller: Intel Corporation UHD Graphics 620 (rev 07) > > -- [snip] > > [ 9.652406] fbcon: i915drmfb (fb0) is primary device > > [ 9.653653] ------------[ cut here ]------------ > > [ 9.653654] i915 0000:00:02.0: drm_WARN_ON(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })) & (1 << 31)) > > [ 9.657092] WARNING: CPU: 1 PID: 103 at drivers/gpu/drm/i915/display/intel_psr.c:782 intel_psr_activate+0x3c6/0x440 [i915] > > [ 9.657093] Modules linked in: snd_hda_codec_realtek(+) snd_hda_codec_generic iwlmvm(+) mac80211 input_leds snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hwdep snd_hda_core kvm_intel libarc4 snd_seq kvm snd_seq_device iwlwifi serio_raw irqbypass snd_pcm thinkpad_acpi pcspkr cfg80211 ledtrig_audio snd_timer rfkill i915 e1000e snd i2c_i801 soundcore i2c_smbus video intel_gtt iosf_mbi drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops fuse drm > > [ 9.657262] CPU: 1 PID: 103 Comm: kworker/u16:3 Not tainted 5.8.0-rc1+ #179 > > [ 9.657262] Hardware name: LENOVO 20L8S3M801/20L8S3M801, BIOS N22ET54W (1.31 ) 04/22/2019 > > [ 9.657262] Workqueue: events_unbound async_run_entry_fn > > [ 9.657263] RIP: 0010:intel_psr_activate+0x3c6/0x440 [i915] > > [ 9.657264] Code: 4c 8b 6f 50 4d 85 ed 75 03 4c 8b 2f e8 c3 e0 1f e1 48 c7 c1 a0 ca 2e a0 4c 89 ea 48 c7 c7 40 3b 30 a0 48 89 c6 e8 f2 21 e0 e0 <0f> 0b 80 bd 88 69 00 00 00 0f 84 b5 fc ff ff 48 8b 7d 18 4c 8b 6f > > [ 9.657264] RSP: 0018:ffff88842ad2b898 EFLAGS: 00010282 > > [ 9.657265] RAX: 0000000000000000 RBX: 0000000000000001 RCX: 0000000000000000 > > [ 9.657265] RDX: 000000000000013a RSI: ffffffff825346da RDI: ffffffff82534ada > > [ 9.657265] RBP: ffff888423228000 R08: 000000023f6713ae R09: 000000000000013a > > [ 9.657266] R10: 0000000000000067 R11: 000000000002fa10 R12: ffff88842c16b128 > > [ 9.657266] R13: ffff88842bb09970 R14: 0000000000000001 R15: ffff88842cbcc000 > > [ 9.657266] FS: 0000000000000000(0000) GS:ffff88842e440000(0000) knlGS:0000000000000000 > > [ 9.657267] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > > [ 9.657267] CR2: 000055b5c70404c8 CR3: 0000000421d96005 CR4: 00000000001606e0 > > [ 9.657267] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > > [ 9.657267] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 > > [ 9.657267] Call Trace: > > [ 9.657268] intel_psr_update+0x17c/0x1a0 [i915] > > [ 9.657268] intel_ddi_update_pipe+0x6c/0xb0 [i915] > > [ 9.657268] intel_update_crtc+0x28b/0x420 [i915] > > [ 9.657268] skl_commit_modeset_enables+0x142/0x4e0 [i915] > > [ 9.657269] intel_atomic_commit_tail+0x2c6/0x1290 [i915] > > [ 9.657269] ? complete+0x2f/0x40 > > [ 9.657269] ? flush_workqueue_prep_pwqs+0x118/0x130 > > [ 9.657269] ? flush_workqueue+0x178/0x3c0 > > [ 9.657270] intel_atomic_commit+0x281/0x300 [i915] > > [ 9.657270] drm_client_modeset_commit_atomic+0x1be/0x200 [drm] > > [ 9.657270] drm_client_modeset_commit_locked+0x54/0x150 [drm] > > [ 9.657270] drm_client_modeset_commit+0x24/0x40 [drm] > > [ 9.657271] drm_fb_helper_restore_fbdev_mode_unlocked+0x49/0x90 [drm_kms_helper] > > [ 9.657271] drm_fb_helper_set_par+0x30/0x40 [drm_kms_helper] > > [ 9.657271] intel_fbdev_set_par+0x16/0x60 [i915] > > [ 9.657272] ? con_is_visible+0x27/0x40 > > [ 9.657272] fbcon_init+0x2e7/0x680 > > [ 9.657272] visual_init+0xce/0x130 > > [ 9.657272] do_bind_con_driver.isra.0+0x1da/0x2e0 > > [ 9.657273] do_take_over_console+0x116/0x180 > > [ 9.657273] do_fbcon_takeover+0x5c/0xc0 > > [ 9.657273] register_framebuffer+0x1e4/0x300 > > [ 9.657274] __drm_fb_helper_initial_config_and_unlock+0x320/0x490 [drm_kms_helper] > > [ 9.657274] intel_fbdev_initial_config+0x14/0x30 [i915] > > [ 9.657274] async_run_entry_fn+0x37/0x150 > > [ 9.657274] process_one_work+0x1bf/0x3d0 > > [ 9.657275] worker_thread+0x4d/0x3d0 > > [ 9.657275] ? process_one_work+0x3d0/0x3d0 > > [ 9.657275] kthread+0x11b/0x140 > > [ 9.657276] ? kthread_create_worker_on_cpu+0x70/0x70 > > [ 9.657276] ret_from_fork+0x22/0x30 > > [ 9.657276] ---[ end trace f701c3abca58b4af ]--- > > [ 9.674849] Console: switching to colour frame buffer device 240x67 > > > > [snip] Thanks Dave From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:03:11 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:03:11 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/10] gem_wsim: Rip out userspace balancing In-Reply-To: <159246690392.4042.13152874782613620641@build.alporthouse.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> <159246447431.2739.9873271400703393063@build.alporthouse.com> <09894f81-19b3-4dde-0764-ec042a5c61e8@linux.intel.com> <159246690392.4042.13152874782613620641@build.alporthouse.com> Message-ID: <53e95097-aa6d-537b-9639-1a259e7a231c@linux.intel.com> On 18/06/2020 08:55, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2020-06-18 08:40:25) >> >> On 18/06/2020 08:14, Chris Wilson wrote: >>> Quoting Tvrtko Ursulin (2020-06-17 17:01:11) >>>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >>>> >>>> Evaluation of userspace load balancing options was how this tool started >>>> but since we have settled on doing it in the kernel. >>>> >>>> Tomorrow we will want to update the tool for new engine interfaces and all >>>> this legacy code will just be a distraction. >>>> >>>> Rip out everything not related to explicit load balancing implemented via >>>> context engine maps and adjust the workloads to use it. >>> >>> Hmm, if this is on the table, should we also then restrict >>> load-balancing wsim to gen11+ so that we can use the timed loops rather >>> nop batches? That would be a huge selling point, and I'll just keep an >>> old checkout around for nop load balancing with all the trimmings. >> >> That was my plan for the next step yes. Just taking your patch without >> further changes would already make it work I think. But also at some >> point I want to convert the engine selection (and engine naming in >> descriptors) to class:instance. >> >> Why do you need the nop/old balancing stuff? I would hope going forward >> we only need to compare current balancing against any changes. So I'd >> really like to remoev the userspace balancing stuff. > > There are still some cases where i915 is beaten by plain old contexts, > usually that is a combination of semaphores and interrupt latency, but > some I just don't understand. There is still an uncomfortably large > variation between kernel releases, and comparing the regressions in > different balancers is useful to narrow down the problem. You could create separate workloads to simulate "-b context" to a degree? I really want to rip this out. Can you cut your losses and forget it existed? :) Regards, Tvrtko From chris at chris-wilson.co.uk Thu Jun 18 10:03:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:49 +0100 Subject: [Intel-gfx] [PATCH 04/11] drm/i915/execlists: Defer schedule_out until after the next dequeue In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-4-chris@chris-wilson.co.uk> Inside schedule_out, we do extra work upon idling the context, such as updating the runtime, kicking off retires, kicking virtual engines. However, if we are in a series of processing single requests per contexts, we may find ourselves scheduling out the context, only to immediately schedule it back in during dequeue. This is just extra work that we can avoid if we keep the context marked as inflight across the dequeue. This becomes more significant later on for minimising virtual engine misses. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 91 ++++++++++++++----- 2 files changed, 68 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 4954b0df4864..b63db45bab7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -45,8 +45,8 @@ struct intel_context { struct intel_engine_cs *engine; struct intel_engine_cs *inflight; -#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2) -#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2) +#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 3) +#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 3) struct i915_address_space *vm; struct i915_gem_context __rcu *gem_context; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 70671dbdcc77..15e073a0ff7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1387,6 +1387,8 @@ __execlists_schedule_in(struct i915_request *rq) execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); + CE_TRACE(ce, "schedule-in, ccid:%x\n", ce->lrc.ccid); + return engine; } @@ -1433,6 +1435,8 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ + CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + /* * If we have just completed this context, the engine may now be * idle and we want to re-enter powersaving. @@ -2057,9 +2061,10 @@ static void set_preempt_timeout(struct intel_engine_cs *engine, active_preempt_timeout(engine, rq)); } -static inline void clear_ports(struct i915_request **ports, int count) +static inline struct i915_request ** +clear_ports(struct i915_request **ports, int count) { - memset_p((void **)ports, NULL, count); + return memset_p((void **)ports, NULL, count); } static void execlists_dequeue(struct intel_engine_cs *engine) @@ -2448,22 +2453,25 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } } -static void -cancel_port_requests(struct intel_engine_execlists * const execlists) +static struct i915_request ** +cancel_port_requests(struct intel_engine_execlists * const execlists, + struct i915_request **inactive) { struct i915_request * const *port; for (port = execlists->pending; *port; port++) - execlists_schedule_out(*port); + *inactive++ = *port; clear_ports(execlists->pending, ARRAY_SIZE(execlists->pending)); /* Mark the end of active before we overwrite *active */ for (port = xchg(&execlists->active, execlists->pending); *port; port++) - execlists_schedule_out(*port); + *inactive++ = *port; clear_ports(execlists->inflight, ARRAY_SIZE(execlists->inflight)); smp_wmb(); /* complete the seqlock for execlists_active() */ WRITE_ONCE(execlists->active, execlists->inflight); + + return inactive; } static inline void @@ -2535,7 +2543,8 @@ gen8_csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb) return *csb & (GEN8_CTX_STATUS_IDLE_ACTIVE | GEN8_CTX_STATUS_PREEMPTED); } -static void process_csb(struct intel_engine_cs *engine) +static struct i915_request ** +process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) { struct intel_engine_execlists * const execlists = &engine->execlists; const u32 * const buf = execlists->csb_status; @@ -2564,7 +2573,7 @@ static void process_csb(struct intel_engine_cs *engine) head = execlists->csb_head; tail = READ_ONCE(*execlists->csb_write); if (unlikely(head == tail)) - return; + return inactive; /* * Hopefully paired with a wmb() in HW! @@ -2620,7 +2629,7 @@ static void process_csb(struct intel_engine_cs *engine) /* cancel old inflight, prepare for switch */ trace_ports(execlists, "preempted", old); while (*old) - execlists_schedule_out(*old++); + *inactive++ = *old++; /* switch pending to inflight */ GEM_BUG_ON(!assert_pending_valid(execlists, "promote")); @@ -2677,7 +2686,7 @@ static void process_csb(struct intel_engine_cs *engine) regs[CTX_RING_TAIL]); } - execlists_schedule_out(*execlists->active++); + *inactive++ = *execlists->active++; GEM_BUG_ON(execlists->active - execlists->inflight > execlists_num_ports(execlists)); @@ -2699,6 +2708,16 @@ static void process_csb(struct intel_engine_cs *engine) * invalidation before. */ invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); + + return inactive; +} + +static void post_process_csb(struct intel_engine_cs *engine, + struct i915_request **port, + struct i915_request **last) +{ + while (port != last) + execlists_schedule_out(*port++); } static void __execlists_hold(struct i915_request *rq) @@ -2969,8 +2988,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->active; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at active:%zd\n", - port - el->active); + "ccid:%x found at active:%zd\n", + ccid, port - el->active); return rq; } } @@ -2978,8 +2997,8 @@ active_context(struct intel_engine_cs *engine, u32 ccid) for (port = el->pending; (rq = *port); port++) { if (rq->context->lrc.ccid == ccid) { ENGINE_TRACE(engine, - "ccid found at pending:%zd\n", - port - el->pending); + "ccid:%x found at pending:%zd\n", + ccid, port - el->pending); return rq; } } @@ -3100,8 +3119,11 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; + struct i915_request *post[2 * EXECLIST_MAX_PORTS]; + struct i915_request **inactive; - process_csb(engine); + inactive = process_csb(engine, post); + GEM_BUG_ON(inactive - post > ARRAY_SIZE(post)); if (unlikely(READ_ONCE(engine->execlists.error_interrupt))) { engine->execlists.error_interrupt = 0; @@ -3114,6 +3136,8 @@ static void execlists_submission_tasklet(unsigned long data) if (!engine->execlists.pending[0]) execlists_dequeue(engine); + + post_process_csb(engine, post, inactive); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -4034,8 +4058,6 @@ static void enable_execlists(struct intel_engine_cs *engine) ENGINE_POSTING_READ(engine, RING_HWS_PGA); enable_error_interrupt(engine); - - engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); } static bool unexpected_starting_state(struct intel_engine_cs *engine) @@ -4124,22 +4146,29 @@ static void __execlists_reset_reg_state(const struct intel_context *ce, __reset_stop_ring(regs, engine); } -static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) +static struct i915_request **reset_csb(struct intel_engine_cs *engine, + struct i915_request **inactive) { struct intel_engine_execlists * const execlists = &engine->execlists; - struct intel_context *ce; - struct i915_request *rq; - u32 head; mb(); /* paranoia: read the CSB pointers from after the reset */ clflush(execlists->csb_write); mb(); - process_csb(engine); /* drain preemption events */ + inactive = process_csb(engine, inactive); /* drain preemption events */ /* Following the reset, we need to reload the CSB read/write pointers */ reset_csb_pointers(engine); + return inactive; +} + +static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) +{ + struct intel_context *ce; + struct i915_request *rq; + u32 head; + /* * Save the currently executing context, even if we completed * its request, it was still running at the time of the @@ -4213,21 +4242,25 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) unwind: /* Push back any incomplete requests for replay after the reset. */ - cancel_port_requests(execlists); __unwind_incomplete_requests(engine); } static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled) { + struct i915_request *post[2 * EXECLIST_MAX_PORTS]; + struct i915_request **inactive; unsigned long flags; ENGINE_TRACE(engine, "\n"); - spin_lock_irqsave(&engine->active.lock, flags); + inactive = reset_csb(engine, post); + spin_lock_irqsave(&engine->active.lock, flags); __execlists_reset(engine, stalled); - spin_unlock_irqrestore(&engine->active.lock, flags); + + inactive = cancel_port_requests(&engine->execlists, inactive); + post_process_csb(engine, post, inactive); } static void nop_submission_tasklet(unsigned long data) @@ -4241,12 +4274,16 @@ static void nop_submission_tasklet(unsigned long data) static void execlists_reset_cancel(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; + struct i915_request *post[2 * EXECLIST_MAX_PORTS]; + struct i915_request **inactive; struct i915_request *rq, *rn; struct rb_node *rb; unsigned long flags; ENGINE_TRACE(engine, "\n"); + inactive = reset_csb(engine, post); + /* * Before we call engine->cancel_requests(), we should have exclusive * access to the submission state. This is arranged for us by the @@ -4318,6 +4355,9 @@ static void execlists_reset_cancel(struct intel_engine_cs *engine) execlists->tasklet.func = nop_submission_tasklet; spin_unlock_irqrestore(&engine->active.lock, flags); + + inactive = cancel_port_requests(execlists, inactive); + post_process_csb(engine, post, inactive); } static void execlists_reset_finish(struct intel_engine_cs *engine) @@ -5077,6 +5117,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) else execlists->csb_size = GEN11_CSB_ENTRIES; + engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0); if (INTEL_GEN(engine->i915) >= 11) { execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32); execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:47 +0100 Subject: [Intel-gfx] [PATCH 02/11] drm/i915/gt: Check for a completed last request once In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-2-chris@chris-wilson.co.uk> Pull the repeated check for the last active request being completed to a single spot, when deciding whether or not execlist preemption is required. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 4eb397b0e14d..7bdbfac26d7b 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2137,12 +2137,11 @@ static void execlists_dequeue(struct intel_engine_cs *engine) */ if ((last = *active)) { - if (need_preempt(engine, last, rb)) { - if (i915_request_completed(last)) { - tasklet_hi_schedule(&execlists->tasklet); - return; - } + if (i915_request_completed(last) && + !list_is_last(&last->sched.link, &engine->active.requests)) + return; + if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, "preempting last=%llx:%lld, prio=%d, hint=%d\n", last->fence.context, @@ -2170,11 +2169,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) last = NULL; } else if (need_timeslice(engine, last, rb) && timeslice_expired(execlists, last)) { - if (i915_request_completed(last)) { - tasklet_hi_schedule(&execlists->tasklet); - return; - } - ENGINE_TRACE(engine, "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n", last->fence.context, -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:51 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:51 +0100 Subject: [Intel-gfx] [PATCH 06/11] drm/i915/gt: Drop atomic for engine->fw_active tracking In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-6-chris@chris-wilson.co.uk> Since schedule-in/out is now entirely serialised by the tasklet bitlock, we do not need to worry about concurrent in/out operations and so reduce the atomic operations to plain instructions. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 60881c8b5b7c..a0723c474e03 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1535,7 +1535,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, drm_printf(m, "\tLatency: %luus\n", ewma__engine_latency_read(&engine->latency)); drm_printf(m, "\tForcewake: %x domains, %d active\n", - engine->fw_domain, atomic_read(&engine->fw_active)); + engine->fw_domain, READ_ONCE(engine->fw_active)); rcu_read_lock(); rq = READ_ONCE(engine->heartbeat.systole); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 073c3769e8cc..fc399a39579c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -322,7 +322,7 @@ struct intel_engine_cs { * as possible. */ enum forcewake_domains fw_domain; - atomic_t fw_active; + unsigned int fw_active; unsigned long context_tag; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index f36d35ac3b75..72355578377b 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1382,7 +1382,7 @@ __execlists_schedule_in(struct i915_request *rq) ce->lrc.ccid |= engine->execlists.ccid; __intel_gt_pm_get(engine->gt); - if (engine->fw_domain && !atomic_fetch_inc(&engine->fw_active)) + if (engine->fw_domain && !engine->fw_active++) intel_uncore_forcewake_get(engine->uncore, engine->fw_domain); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); intel_engine_context_in(engine); @@ -1453,7 +1453,7 @@ static inline void __execlists_schedule_out(struct i915_request *rq) intel_context_update_runtime(ce); intel_engine_context_out(engine); execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); - if (engine->fw_domain && !atomic_dec_return(&engine->fw_active)) + if (engine->fw_domain && !--engine->fw_active) intel_uncore_forcewake_put(engine->uncore, engine->fw_domain); intel_gt_pm_put_async(engine->gt); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:55 +0100 Subject: [Intel-gfx] [PATCH 10/11] drm/i915/gt: Decouple inflight virtual engines In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-10-chris@chris-wilson.co.uk> Once a virtual engine has been bound to a sibling, it will remain bound until we finally schedule out the last active request. We can not rebind the context to a new sibling while it is inflight as the context save will conflict, hence we wait. As we cannot then use any other sibliing while the context is inflight, only kick the bound sibling while it inflight and upon scheduling out the kick the rest (so that we can swap engines on timeslicing if the previously bound engine becomes oversubscribed). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 30 +++++++++++++---------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index fd8c5cf0b482..8d3a6d995c45 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1379,9 +1379,8 @@ execlists_schedule_in(struct i915_request *rq, int idx) static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); - struct i915_request *next = READ_ONCE(ve->request); - if (next == rq || (next && next->execution_mask & ~rq->execution_mask)) + if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); } @@ -1796,18 +1795,14 @@ first_virtual_engine(struct intel_engine_cs *engine) rb_entry(rb, typeof(*ve), nodes[engine->id].rb); struct i915_request *rq = READ_ONCE(ve->request); - if (!rq) { /* lazily cleanup after another engine handled rq */ + /* lazily cleanup after another engine handled rq */ + if (!rq || !virtual_matches(ve, rq, engine)) { rb_erase_cached(rb, &el->virtual); RB_CLEAR_NODE(rb); rb = rb_first_cached(&el->virtual); continue; } - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - return ve; } @@ -5453,7 +5448,6 @@ static void virtual_submission_tasklet(unsigned long data) if (unlikely(!mask)) return; - local_irq_disable(); for (n = 0; n < ve->num_siblings; n++) { struct intel_engine_cs *sibling = READ_ONCE(ve->siblings[n]); struct ve_node * const node = &ve->nodes[sibling->id]; @@ -5463,20 +5457,19 @@ static void virtual_submission_tasklet(unsigned long data) if (!READ_ONCE(ve->request)) break; /* already handled by a sibling's tasklet */ + spin_lock_irq(&sibling->active.lock); + if (unlikely(!(mask & sibling->mask))) { if (!RB_EMPTY_NODE(&node->rb)) { - spin_lock(&sibling->active.lock); rb_erase_cached(&node->rb, &sibling->execlists.virtual); RB_CLEAR_NODE(&node->rb); - spin_unlock(&sibling->active.lock); } - continue; - } - spin_lock(&sibling->active.lock); + goto unlock_engine; + } - if (!RB_EMPTY_NODE(&node->rb)) { + if (unlikely(!RB_EMPTY_NODE(&node->rb))) { /* * Cheat and avoid rebalancing the tree if we can * reuse this node in situ. @@ -5516,9 +5509,12 @@ static void virtual_submission_tasklet(unsigned long data) if (first && prio > sibling->execlists.queue_priority_hint) tasklet_hi_schedule(&sibling->execlists.tasklet); - spin_unlock(&sibling->active.lock); +unlock_engine: + spin_unlock_irq(&sibling->active.lock); + + if (intel_context_inflight(&ve->context)) + break; } - local_irq_enable(); } static void virtual_submit_request(struct i915_request *rq) -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:54 +0100 Subject: [Intel-gfx] [PATCH 09/11] drm/i915/gt: Use virtual_engine during execlists_dequeue In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-9-chris@chris-wilson.co.uk> Rather than going back and forth between the rb_node entry and the virtual_engine type, store the ve local and reuse it. As the container_of conversion from rb_node to virtual_engine requires a variable offset, performing that conversion just once shaves off a bit of code. v2: Keep a single virtual engine lookup, for typical use. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 209 ++++++++++++++-------------- 1 file changed, 101 insertions(+), 108 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 68b8e687f354..fd8c5cf0b482 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -455,7 +455,7 @@ static int queue_prio(const struct intel_engine_execlists *execlists) static inline bool need_preempt(const struct intel_engine_cs *engine, const struct i915_request *rq, - struct rb_node *rb) + const struct virtual_engine *ve) { int last_prio; @@ -492,9 +492,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, rq_prio(list_next_entry(rq, sched.link)) > last_prio) return true; - if (rb) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { bool preempt = false; if (engine == ve->siblings[0]) { /* only preempt one sibling */ @@ -1787,6 +1785,35 @@ static bool virtual_matches(const struct virtual_engine *ve, return true; } +static struct virtual_engine * +first_virtual_engine(struct intel_engine_cs *engine) +{ + struct intel_engine_execlists *el = &engine->execlists; + struct rb_node *rb = rb_first_cached(&el->virtual); + + while (rb) { + struct virtual_engine *ve = + rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + struct i915_request *rq = READ_ONCE(ve->request); + + if (!rq) { /* lazily cleanup after another engine handled rq */ + rb_erase_cached(rb, &el->virtual); + RB_CLEAR_NODE(rb); + rb = rb_first_cached(&el->virtual); + continue; + } + + if (!virtual_matches(ve, rq, engine)) { + rb = rb_next(rb); + continue; + } + + return ve; + } + + return NULL; +} + static void virtual_xfer_breadcrumbs(struct virtual_engine *ve) { /* @@ -1871,7 +1898,7 @@ static void defer_active(struct intel_engine_cs *engine) static bool need_timeslice(const struct intel_engine_cs *engine, const struct i915_request *rq, - const struct rb_node *rb) + const struct virtual_engine *ve) { int hint; @@ -1880,9 +1907,7 @@ need_timeslice(const struct intel_engine_cs *engine, hint = engine->execlists.queue_priority_hint; - if (rb) { - const struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + if (ve) { const struct intel_engine_cs *inflight = intel_context_inflight(&ve->context); @@ -2035,6 +2060,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; struct i915_request * const *active = execlists->active; + struct virtual_engine *ve; struct i915_request *last; unsigned long flags; struct rb_node *rb; @@ -2062,26 +2088,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * and context switches) submission. */ spin_lock_irqsave(&engine->active.lock, flags); - - for (rb = rb_first_cached(&execlists->virtual); rb; ) { - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); - struct i915_request *rq = READ_ONCE(ve->request); - - if (!rq) { /* lazily cleanup after another engine handled rq */ - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } - - if (!virtual_matches(ve, rq, engine)) { - rb = rb_next(rb); - continue; - } - - break; - } + ve = first_virtual_engine(engine); /* * If the queue is higher priority than the last @@ -2109,7 +2116,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) return; } - if (need_preempt(engine, last, rb)) { + if (need_preempt(engine, last, ve)) { ENGINE_TRACE(engine, "preempting last=%llx:%lld, prio=%d, hint=%d\n", last->fence.context, @@ -2135,7 +2142,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) __unwind_incomplete_requests(engine); last = NULL; - } else if (need_timeslice(engine, last, rb) && + } else if (need_timeslice(engine, last, ve) && timeslice_expired(execlists, last)) { ENGINE_TRACE(engine, "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n", @@ -2185,111 +2192,97 @@ static void execlists_dequeue(struct intel_engine_cs *engine) } } - while (rb) { /* XXX virtual is always taking precedence */ - struct virtual_engine *ve = - rb_entry(rb, typeof(*ve), nodes[engine->id].rb); + while (ve) { /* XXX virtual is always taking precedence */ struct i915_request *rq; spin_lock(&ve->base.active.lock); rq = ve->request; - if (unlikely(!rq)) { /* lost the race to a sibling */ - spin_unlock(&ve->base.active.lock); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); - rb = rb_first_cached(&execlists->virtual); - continue; - } + if (unlikely(!rq)) /* lost the race to a sibling */ + goto unlock; GEM_BUG_ON(rq != ve->request); GEM_BUG_ON(rq->engine != &ve->base); GEM_BUG_ON(rq->context != &ve->context); - if (rq_prio(rq) >= queue_prio(execlists)) { - if (!virtual_matches(ve, rq, engine)) { - spin_unlock(&ve->base.active.lock); - rb = rb_next(rb); - continue; - } + if (unlikely(rq_prio(rq) < queue_prio(execlists))) { + spin_unlock(&ve->base.active.lock); + break; + } - if (last && !can_merge_rq(last, rq)) { - spin_unlock(&ve->base.active.lock); - spin_unlock_irqrestore(&engine->active.lock, flags); - start_timeslice(engine, rq_prio(rq)); - return; /* leave this for another sibling */ - } + GEM_BUG_ON(!virtual_matches(ve, rq, engine)); - ENGINE_TRACE(engine, - "virtual rq=%llx:%lld%s, new engine? %s\n", - rq->fence.context, - rq->fence.seqno, - i915_request_completed(rq) ? "!" : - i915_request_started(rq) ? "*" : - "", - yesno(engine != ve->siblings[0])); - - WRITE_ONCE(ve->request, NULL); - WRITE_ONCE(ve->base.execlists.queue_priority_hint, - INT_MIN); - rb_erase_cached(rb, &execlists->virtual); - RB_CLEAR_NODE(rb); + if (last && !can_merge_rq(last, rq)) { + spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); + start_timeslice(engine, rq_prio(rq)); + return; /* leave this for another sibling */ + } - GEM_BUG_ON(!(rq->execution_mask & engine->mask)); - WRITE_ONCE(rq->engine, engine); + ENGINE_TRACE(engine, + "virtual rq=%llx:%lld%s, new engine? %s\n", + rq->fence.context, + rq->fence.seqno, + i915_request_completed(rq) ? "!" : + i915_request_started(rq) ? "*" : + "", + yesno(engine != ve->siblings[0])); - if (engine != ve->siblings[0]) { - u32 *regs = ve->context.lrc_reg_state; - unsigned int n; + WRITE_ONCE(ve->request, NULL); + WRITE_ONCE(ve->base.execlists.queue_priority_hint, INT_MIN); - GEM_BUG_ON(READ_ONCE(ve->context.inflight)); + rb = &ve->nodes[engine->id].rb; + rb_erase_cached(rb, &execlists->virtual); + RB_CLEAR_NODE(rb); - if (!intel_engine_has_relative_mmio(engine)) - virtual_update_register_offsets(regs, - engine); + GEM_BUG_ON(!(rq->execution_mask & engine->mask)); + WRITE_ONCE(rq->engine, engine); - if (!list_empty(&ve->context.signals)) - virtual_xfer_breadcrumbs(ve); + if (engine != ve->siblings[0]) { + u32 *regs = ve->context.lrc_reg_state; + unsigned int n; - /* - * Move the bound engine to the top of the list - * for future execution. We then kick this - * tasklet first before checking others, so that - * we preferentially reuse this set of bound - * registers. - */ - for (n = 1; n < ve->num_siblings; n++) { - if (ve->siblings[n] == engine) { - swap(ve->siblings[n], - ve->siblings[0]); - break; - } - } + GEM_BUG_ON(READ_ONCE(ve->context.inflight)); - GEM_BUG_ON(ve->siblings[0] != engine); - } + if (!intel_engine_has_relative_mmio(engine)) + virtual_update_register_offsets(regs, engine); - if (__i915_request_submit(rq)) { - submit = true; - last = rq; - } - i915_request_put(rq); + if (!list_empty(&ve->context.signals)) + virtual_xfer_breadcrumbs(ve); /* - * Hmm, we have a bunch of virtual engine requests, - * but the first one was already completed (thanks - * preempt-to-busy!). Keep looking at the veng queue - * until we have no more relevant requests (i.e. - * the normal submit queue has higher priority). + * Move the bound engine to the top of the list for + * future execution. We then kick this tasklet first + * before checking others, so that we preferentially + * reuse this set of bound registers. */ - if (!submit) { - spin_unlock(&ve->base.active.lock); - rb = rb_first_cached(&execlists->virtual); - continue; + for (n = 1; n < ve->num_siblings; n++) { + if (ve->siblings[n] == engine) { + swap(ve->siblings[n], ve->siblings[0]); + break; + } } + + GEM_BUG_ON(ve->siblings[0] != engine); } + if (__i915_request_submit(rq)) { + submit = true; + last = rq; + } + + i915_request_put(rq); +unlock: spin_unlock(&ve->base.active.lock); - break; + + /* + * Hmm, we have a bunch of virtual engine requests, + * but the first one was already completed (thanks + * preempt-to-busy!). Keep looking at the veng queue + * until we have no more relevant requests (i.e. + * the normal submit queue has higher priority). + */ + ve = submit ? NULL : first_virtual_engine(engine); } while ((rb = rb_first_cached(&execlists->queue))) { -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:56 +0100 Subject: [Intel-gfx] [PATCH 11/11] drm/i915/gt: Resubmit the virtual engine on schedule-out In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-11-chris@chris-wilson.co.uk> Having recognised that we do not change the sibling until we schedule out, we can then defer the decision to resubmit the virtual engine from the unwind of the active queue to scheduling out of the virtual context. By keeping the unwind order intact on the local engine, we can preserve data dependency ordering while doing a preempt-to-busy pass until we have determined the new ELSP. This means that if we try to timeslice between a virtual engine and a data-dependent ordinary request, the pair will maintain their relative ordering and we will avoid the resubmission, cancelling the timeslicing until further change. The dilemma though is that we then may end up in a situation where the 'demotion' of the virtual request to an ordinary request in the engine queue results in filling the ELSP[] with virtual requests instead of spreading the load across the engines. To compensate for this, we mark each virtual request and refuse to resubmit a virtual request in the secondary ELSP slots, thus forcing subsequent virtual requests to be scheduled out after timeslicing. By delaying the decision until we schedule out, we will avoid unnecessary resubmission. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 118 ++++++++++++++++--------- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- 2 files changed, 75 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 8d3a6d995c45..b67977424d80 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1120,53 +1120,23 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) __i915_request_unsubmit(rq); - /* - * Push the request back into the queue for later resubmission. - * If this request is not native to this physical engine (i.e. - * it came from a virtual source), push it back onto the virtual - * engine so that it can be moved across onto another physical - * engine as load dictates. - */ - if (likely(rq->execution_mask == engine->mask)) { - GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); - if (rq_prio(rq) != prio) { - prio = rq_prio(rq); - pl = i915_sched_lookup_priolist(engine, prio); - } - GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - - list_move(&rq->sched.link, pl); - set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); + if (rq_prio(rq) != prio) { + prio = rq_prio(rq); + pl = i915_sched_lookup_priolist(engine, prio); + } + GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); - /* Check in case we rollback so far we wrap [size/2] */ - if (intel_ring_direction(rq->ring, - intel_ring_wrap(rq->ring, - rq->tail), - rq->ring->tail) > 0) - rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; + list_move(&rq->sched.link, pl); + set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); - active = rq; - } else { - struct intel_engine_cs *owner = rq->context->engine; + /* Check in case we rollback so far we wrap [size/2] */ + if (intel_ring_direction(rq->ring, + intel_ring_wrap(rq->ring, rq->tail), + rq->ring->tail) > 0) + rq->context->lrc.desc |= CTX_DESC_FORCE_RESTORE; - /* - * Decouple the virtual breadcrumb before moving it - * back to the virtual engine -- we don't want the - * request to complete in the background and try - * and cancel the breadcrumb on the virtual engine - * (instead of the old engine where it is linked)! - */ - if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &rq->fence.flags)) { - spin_lock_nested(&rq->lock, - SINGLE_DEPTH_NESTING); - i915_request_cancel_breadcrumb(rq); - spin_unlock(&rq->lock); - } - WRITE_ONCE(rq->engine, owner); - owner->submit_request(rq); - active = NULL; - } + active = rq; } return active; @@ -1376,12 +1346,49 @@ execlists_schedule_in(struct i915_request *rq, int idx) return i915_request_get(rq); } +static void +resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve) +{ + struct intel_engine_cs *engine = rq->engine; + unsigned long flags; + + spin_lock_irqsave(&engine->active.lock, flags); + + /* + * Decouple the virtual breadcrumb before moving it back to the virtual + * engine -- we don't want the request to complete in the background + * and then try and cancel the breadcrumb on the virtual engine + * (instead of the old engine where it is linked)! + */ + if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags)) { + spin_lock_nested(&rq->lock, SINGLE_DEPTH_NESTING); + i915_request_cancel_breadcrumb(rq); + spin_unlock(&rq->lock); + } + + clear_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); + WRITE_ONCE(rq->engine, &ve->base); + ve->base.submit_request(rq); + + spin_unlock_irqrestore(&engine->active.lock, flags); +} + static void kick_siblings(struct i915_request *rq, struct intel_context *ce) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); if (READ_ONCE(ve->request)) tasklet_hi_schedule(&ve->base.execlists.tasklet); + + /* + * This engine is now too busy to run this virtual request, so + * see if we can find an alternative engine for it to execute on. + * Once a request has become bonded to this engine, we treat it the + * same as other native request. + */ + if (i915_request_in_priority_queue(rq) && + rq->execution_mask != rq->engine->mask) + resubmit_virtual_request(rq, ve); } static inline void __execlists_schedule_out(struct i915_request *rq) @@ -1621,6 +1628,20 @@ assert_pending_valid(const struct intel_engine_execlists *execlists, } sentinel = i915_request_has_sentinel(rq); + /* + * We want virtual requests to only be in the first slot so + * that they are never stuck behind a hog and can be immediately + * transferred onto the next idle engine. + */ + if (rq->execution_mask != engine->mask && + port != execlists->pending) { + GEM_TRACE_ERR("%s: virtual engine:%llx not in prime position[%zd]\n", + engine->name, + ce->timeline->fence_context, + port - execlists->pending); + return false; + } + /* Hold tightly onto the lock to prevent concurrent retires! */ if (!spin_trylock_irqsave(&rq->lock, flags)) continue; @@ -2319,6 +2340,15 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (i915_request_has_sentinel(last)) goto done; + /* + * We avoid submitting virtual requests into + * the secondary ports so that we can migrate + * the request immediately to another engine + * rather than wait for the primary request. + */ + if (rq->execution_mask != engine->mask) + goto done; + /* * If GVT overrides us we only ever submit * port[0], leaving port[1] empty. Note that we diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index daa4aabab9a7..0178524818ba 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -4587,7 +4587,7 @@ static int reset_virtual_engine(struct intel_gt *gt, spin_lock_irq(&engine->active.lock); __unwind_incomplete_requests(engine); spin_unlock_irq(&engine->active.lock); - GEM_BUG_ON(rq->engine != ve->engine); + GEM_BUG_ON(rq->engine != engine); /* Reset the engine while keeping our active request on hold */ execlists_hold(engine, rq); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:52 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:52 +0100 Subject: [Intel-gfx] [PATCH 07/11] drm/i915/gt: Extract busy-stats for ring-scheduler In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-7-chris@chris-wilson.co.uk> Lift the busy-stats context-in/out implementation out of intel_lrc, so that we can reuse it for other scheduler implementations. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 34 +------------- 2 files changed, 50 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_engine_stats.h diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h new file mode 100644 index 000000000000..58491eae3482 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright ? 2020 Intel Corporation + */ + +#ifndef __INTEL_ENGINE_STATS_H__ +#define __INTEL_ENGINE_STATS_H__ + +#include <linux/atomic.h> +#include <linux/ktime.h> +#include <linux/seqlock.h> + +#include "i915_gem.h" /* GEM_BUG_ON */ +#include "intel_engine.h" + +static inline void intel_engine_context_in(struct intel_engine_cs *engine) +{ + unsigned long flags; + + if (atomic_add_unless(&engine->stats.active, 1, 0)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + engine->stats.start = ktime_get(); + atomic_inc(&engine->stats.active); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +static inline void intel_engine_context_out(struct intel_engine_cs *engine) +{ + unsigned long flags; + + GEM_BUG_ON(!atomic_read(&engine->stats.active)); + + if (atomic_add_unless(&engine->stats.active, -1, 1)) + return; + + write_seqlock_irqsave(&engine->stats.lock, flags); + if (atomic_dec_and_test(&engine->stats.active)) { + engine->stats.total = + ktime_add(engine->stats.total, + ktime_sub(ktime_get(), engine->stats.start)); + } + write_sequnlock_irqrestore(&engine->stats.lock, flags); +} + +#endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 72355578377b..68b8e687f354 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -139,6 +139,7 @@ #include "i915_vgpu.h" #include "intel_context.h" #include "intel_engine_pm.h" +#include "intel_engine_stats.h" #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" @@ -1196,39 +1197,6 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) status, rq); } -static void intel_engine_context_in(struct intel_engine_cs *engine) -{ - unsigned long flags; - - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { - engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - -static void intel_engine_context_out(struct intel_engine_cs *engine) -{ - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); - - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { - engine->stats.total = - ktime_add(engine->stats.total, - ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); -} - static void execlists_check_context(const struct intel_context *ce, const struct intel_engine_cs *engine) -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:50 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:50 +0100 Subject: [Intel-gfx] [PATCH 05/11] drm/i915/gt: ce->inflight updates are now serialised In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-5-chris@chris-wilson.co.uk> Since schedule-in and schedule-out are now both always under the tasklet bitlock, we can reduce the individual atomic operations to simple instructions and worry less. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 44 +++++++++++++---------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 15e073a0ff7c..f36d35ac3b75 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1373,7 +1373,7 @@ __execlists_schedule_in(struct i915_request *rq) unsigned int tag = ffs(READ_ONCE(engine->context_tag)); GEM_BUG_ON(tag == 0 || tag >= BITS_PER_LONG); - clear_bit(tag - 1, &engine->context_tag); + __clear_bit(tag - 1, &engine->context_tag); ce->lrc.ccid = tag << (GEN11_SW_CTX_ID_SHIFT - 32); BUILD_BUG_ON(BITS_PER_LONG > GEN12_MAX_CONTEXT_HW_ID); @@ -1401,13 +1401,10 @@ execlists_schedule_in(struct i915_request *rq, int idx) GEM_BUG_ON(!intel_engine_pm_is_awake(rq->engine)); trace_i915_request_in(rq, idx); - old = READ_ONCE(ce->inflight); - do { - if (!old) { - WRITE_ONCE(ce->inflight, __execlists_schedule_in(rq)); - break; - } - } while (!try_cmpxchg(&ce->inflight, &old, ptr_inc(old))); + old = ce->inflight; + if (!old) + old = __execlists_schedule_in(rq); + WRITE_ONCE(ce->inflight, ptr_inc(old)); GEM_BUG_ON(intel_context_inflight(ce) != rq->engine); return i915_request_get(rq); @@ -1422,12 +1419,11 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce) tasklet_hi_schedule(&ve->base.execlists.tasklet); } -static inline void -__execlists_schedule_out(struct i915_request *rq, - struct intel_engine_cs * const engine, - unsigned int ccid) +static inline void __execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; + struct intel_engine_cs * const engine = rq->engine; + unsigned int ccid; /* * NB process_csb() is not under the engine->active.lock and hence @@ -1435,7 +1431,7 @@ __execlists_schedule_out(struct i915_request *rq, * refrain from doing non-trivial work here. */ - CE_TRACE(ce, "schedule-out, ccid:%x\n", ccid); + CE_TRACE(ce, "schedule-out, ccid:%x\n", ce->lrc.ccid); /* * If we have just completed this context, the engine may now be @@ -1445,12 +1441,13 @@ __execlists_schedule_out(struct i915_request *rq, i915_request_completed(rq)) intel_engine_add_retire(engine, ce->timeline); + ccid = ce->lrc.ccid; ccid >>= GEN11_SW_CTX_ID_SHIFT - 32; ccid &= GEN12_MAX_CONTEXT_HW_ID; if (ccid < BITS_PER_LONG) { GEM_BUG_ON(ccid == 0); GEM_BUG_ON(test_bit(ccid - 1, &engine->context_tag)); - set_bit(ccid - 1, &engine->context_tag); + __set_bit(ccid - 1, &engine->context_tag); } intel_context_update_runtime(ce); @@ -1471,26 +1468,23 @@ __execlists_schedule_out(struct i915_request *rq, */ if (ce->engine != engine) kick_siblings(rq, ce); - - intel_context_put(ce); } static inline void execlists_schedule_out(struct i915_request *rq) { struct intel_context * const ce = rq->context; - struct intel_engine_cs *cur, *old; - u32 ccid; trace_i915_request_out(rq); - ccid = rq->context->lrc.ccid; - old = READ_ONCE(ce->inflight); - do - cur = ptr_unmask_bits(old, 2) ? ptr_dec(old) : NULL; - while (!try_cmpxchg(&ce->inflight, &old, cur)); - if (!cur) - __execlists_schedule_out(rq, old, ccid); + GEM_BUG_ON(!ce->inflight); + ce->inflight = ptr_dec(ce->inflight); + if (!intel_context_inflight_count(ce)) { + GEM_BUG_ON(ce->inflight != rq->engine); + WRITE_ONCE(ce->inflight, NULL); + __execlists_schedule_out(rq); + intel_context_put(ce); + } i915_request_put(rq); } -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:46 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:46 +0100 Subject: [Intel-gfx] [PATCH 01/11] drm/i915/gt: Decouple completed requests on unwind Message-ID: <20200618100356.15744-1-chris@chris-wilson.co.uk> Since the introduction of preempt-to-busy, requests can complete in the background, even while they are not on the engine->active.requests list. As such, the engine->active.request list itself is not in strict retirement order, and we have to scan the entire list while unwinding to not miss any. However, if the request is completed we currently leave it on the list [until retirement], but we could just as simply remove it and stop treating it as active. We would only have to then traverse it once while unwinding in quick succession. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..4eb397b0e14d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1114,8 +1114,10 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) list_for_each_entry_safe_reverse(rq, rn, &engine->active.requests, sched.link) { - if (i915_request_completed(rq)) - continue; /* XXX */ + if (i915_request_completed(rq)) { + list_del_init(&rq->sched.link); + continue; + } __i915_request_unsubmit(rq); -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:53 +0100 Subject: [Intel-gfx] [PATCH 08/11] drm/i915/gt: Convert stats.active to plain unsigned int In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-8-chris@chris-wilson.co.uk> As context-in/out is now always serialised, we do not have to worry about concurrent enabling/disable of the busy-stats and can reduce the atomic_t active to a plain unsigned int, and the seqlock to a seqcount. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 8 +++--- drivers/gpu/drm/i915/gt/intel_engine_stats.h | 28 +++++++------------- drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +-- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index a0723c474e03..df19e83a3701 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -338,7 +338,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id) engine->schedule = NULL; ewma__engine_latency_init(&engine->latency); - seqlock_init(&engine->stats.lock); + seqcount_init(&engine->stats.lock); ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); @@ -1612,7 +1612,7 @@ static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine, * add it to the total. */ *now = ktime_get(); - if (atomic_read(&engine->stats.active)) + if (engine->stats.active) total = ktime_add(total, ktime_sub(*now, engine->stats.start)); return total; @@ -1631,9 +1631,9 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now) ktime_t total; do { - seq = read_seqbegin(&engine->stats.lock); + seq = read_seqcount_begin(&engine->stats.lock); total = __intel_engine_get_busy_time(engine, now); - } while (read_seqretry(&engine->stats.lock, seq)); + } while (read_seqcount_retry(&engine->stats.lock, seq)); return total; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_stats.h b/drivers/gpu/drm/i915/gt/intel_engine_stats.h index 58491eae3482..4965eb5bfb65 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_stats.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_stats.h @@ -15,35 +15,25 @@ static inline void intel_engine_context_in(struct intel_engine_cs *engine) { - unsigned long flags; + write_seqcount_begin(&engine->stats.lock); - if (atomic_add_unless(&engine->stats.active, 1, 0)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (!atomic_add_unless(&engine->stats.active, 1, 0)) { + if (!engine->stats.active++) engine->stats.start = ktime_get(); - atomic_inc(&engine->stats.active); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); + + write_seqcount_end(&engine->stats.lock); } static inline void intel_engine_context_out(struct intel_engine_cs *engine) { - unsigned long flags; - - GEM_BUG_ON(!atomic_read(&engine->stats.active)); + write_seqcount_begin(&engine->stats.lock); - if (atomic_add_unless(&engine->stats.active, -1, 1)) - return; - - write_seqlock_irqsave(&engine->stats.lock, flags); - if (atomic_dec_and_test(&engine->stats.active)) { + GEM_BUG_ON(!engine->stats.active); + if (!--engine->stats.active) engine->stats.total = ktime_add(engine->stats.total, ktime_sub(ktime_get(), engine->stats.start)); - } - write_sequnlock_irqrestore(&engine->stats.lock, flags); + + write_seqcount_end(&engine->stats.lock); } #endif /* __INTEL_ENGINE_STATS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index fc399a39579c..e1564930bd06 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -544,12 +544,12 @@ struct intel_engine_cs { /** * @active: Number of contexts currently scheduled in. */ - atomic_t active; + unsigned int active; /** * @lock: Lock protecting the below fields. */ - seqlock_t lock; + seqcount_t lock; /** * @total: Total time this engine was busy. -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:03:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:03:48 +0100 Subject: [Intel-gfx] [PATCH 03/11] drm/i915/gt: Replace direct submit with direct call to tasklet In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <20200618100356.15744-3-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET softirq synchronous"). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 20 ++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 113 ++++++------------ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/i915_request.c | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 7 files changed, 75 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef425fd990c4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2355,7 +2355,9 @@ static void eb_request_add(struct i915_execbuffer *eb) __i915_request_skip(rq); } + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); /* Try to clean up the client's timeline after submitting the request */ if (prev) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..60881c8b5b7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +static int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err = __intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..80e9f74040f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,17 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void heartbeat_commit(struct i915_request *rq, + const struct i915_sched_attr *attr) +{ + idle_pulse(rq->engine, rq); + __i915_request_commit(rq); + + local_bh_disable(); + __i915_request_queue(rq, attr); + local_bh_enable(); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -132,12 +143,10 @@ static void heartbeat(struct work_struct *wrk) if (IS_ERR(rq)) goto unlock; - idle_pulse(engine, rq); if (i915_modparams.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); unlock: mutex_unlock(&ce->timeline->mutex); @@ -218,10 +227,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) } __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); - idle_pulse(engine, rq); - - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER); err = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7bdbfac26d7b..70671dbdcc77 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2067,8 +2067,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = execlists->active; struct i915_request *last; + unsigned long flags; struct rb_node *rb; bool submit = false; @@ -2093,6 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * sequence of requests as being the most optimal (fewest wake ups * and context switches) submission. */ + spin_lock_irqsave(&engine->active.lock, flags); for (rb = rb_first_cached(&execlists->virtual); rb; ) { struct virtual_engine *ve = @@ -2121,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2138,8 +2137,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if ((last = *active)) { if (i915_request_completed(last) && - !list_is_last(&last->sched.link, &engine->active.requests)) + !list_is_last(&last->sched.link, &engine->active.requests)) { + spin_unlock_irqrestore(&engine->active.lock, flags); return; + } if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, @@ -2210,6 +2211,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, queue_prio(execlists)); return; } @@ -2245,6 +2247,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2377,8 +2380,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (__i915_request_submit(rq)) { if (!merge) { - *port = execlists_schedule_in(last, port - execlists->pending); - port++; + *port++ = last; last = NULL; } @@ -2416,25 +2418,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * interrupt for secondary ports). */ execlists->queue_priority_hint = queue_prio(execlists); + spin_unlock_irqrestore(&engine->active.lock, flags); if (submit) { - *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); - + *port++ = last; /* * Skip if we ended up with exactly the same set of requests, * e.g. trying to timeslice a pair of ordered contexts */ if (!memcmp(active, execlists->pending, - (port - execlists->pending + 1) * sizeof(*port))) { - do - execlists_schedule_out(fetch_and_zero(port)); - while (port-- != execlists->pending); - + (port - execlists->pending) * sizeof(*port))) goto skip_submit; - } - clear_ports(port + 1, last_port - port); + + *port = NULL; + while (port-- != execlists->pending) + *port = execlists_schedule_in(*port, + port - execlists->pending); + execlists->switch_priority_hint = + switch_prio(engine, *execlists->pending); WRITE_ONCE(execlists->yield, -1); set_preempt_timeout(engine, *active); @@ -2443,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + *execlists->pending = NULL; } } @@ -2699,16 +2701,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3098,7 +3090,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3108,7 +3100,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3118,17 +3109,11 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { - unsigned long flags; - - spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); - spin_unlock_irqrestore(&engine->active.lock, flags); + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); - } + if (!engine->execlists.pending[0]) + execlists_dequeue(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3159,26 +3144,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3188,25 +3163,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } -static void flush_csb(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists *el = &engine->execlists; - - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); - } -} - static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); - /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3220,7 +3181,8 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + if (submit_queue(engine, request)) + __execlists_kick(&engine->execlists); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4109,7 +4071,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4126,10 +4087,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4373,12 +4330,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + __execlists_kick(execlists); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..0fa23cb6bf1a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1582,6 +1582,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..0dad1f0fbd32 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1599,7 +1599,9 @@ void i915_request_add(struct i915_request *rq) attr = ctx->sched; rcu_read_unlock(); + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); mutex_unlock(&tl->mutex); } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:05:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:05:48 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/10] gem_wsim: Rip out userspace balancing In-Reply-To: <53e95097-aa6d-537b-9639-1a259e7a231c@linux.intel.com> References: <20200617160120.16555-1-tvrtko.ursulin@linux.intel.com> <20200617160120.16555-2-tvrtko.ursulin@linux.intel.com> <159246447431.2739.9873271400703393063@build.alporthouse.com> <09894f81-19b3-4dde-0764-ec042a5c61e8@linux.intel.com> <159246690392.4042.13152874782613620641@build.alporthouse.com> <53e95097-aa6d-537b-9639-1a259e7a231c@linux.intel.com> Message-ID: <159247474805.4042.2360082438731185973@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:03:11) > > On 18/06/2020 08:55, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2020-06-18 08:40:25) > >> > >> On 18/06/2020 08:14, Chris Wilson wrote: > >>> Quoting Tvrtko Ursulin (2020-06-17 17:01:11) > >>>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > >>>> > >>>> Evaluation of userspace load balancing options was how this tool started > >>>> but since we have settled on doing it in the kernel. > >>>> > >>>> Tomorrow we will want to update the tool for new engine interfaces and all > >>>> this legacy code will just be a distraction. > >>>> > >>>> Rip out everything not related to explicit load balancing implemented via > >>>> context engine maps and adjust the workloads to use it. > >>> > >>> Hmm, if this is on the table, should we also then restrict > >>> load-balancing wsim to gen11+ so that we can use the timed loops rather > >>> nop batches? That would be a huge selling point, and I'll just keep an > >>> old checkout around for nop load balancing with all the trimmings. > >> > >> That was my plan for the next step yes. Just taking your patch without > >> further changes would already make it work I think. But also at some > >> point I want to convert the engine selection (and engine naming in > >> descriptors) to class:instance. > >> > >> Why do you need the nop/old balancing stuff? I would hope going forward > >> we only need to compare current balancing against any changes. So I'd > >> really like to remoev the userspace balancing stuff. > > > > There are still some cases where i915 is beaten by plain old contexts, > > usually that is a combination of semaphores and interrupt latency, but > > some I just don't understand. There is still an uncomfortably large > > variation between kernel releases, and comparing the regressions in > > different balancers is useful to narrow down the problem. > > You could create separate workloads to simulate "-b context" to a > degree? I really want to rip this out. Can you cut your losses and > forget it existed? :) It's fine; I can keep a stable benchmark around of a known checkout. -Chris From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:37 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:37 +0100 Subject: [Intel-gfx] [PATCH i-g-t 01/11] gem_wsim: Rip out userspace balancing Message-ID: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Evaluation of userspace load balancing options was how this tool started but since we have settled on doing it in the kernel. Tomorrow we will want to update the tool for new engine interfaces and all this legacy code will just be a distraction. Rip out everything not related to explicit load balancing implemented via context engine maps and adjust the workloads to use it. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/Makefile.am | 2 +- benchmarks/Makefile.sources | 6 - benchmarks/ewma.h | 71 - benchmarks/gem_wsim.c | 1394 +---------------- benchmarks/ilog2.h | 104 -- benchmarks/meson.build | 6 +- benchmarks/wsim/media-1080p-player.wsim | 2 + benchmarks/wsim/media_1n2_480p.wsim | 12 +- benchmarks/wsim/media_1n2_asy.wsim | 8 +- benchmarks/wsim/media_1n3_480p.wsim | 16 +- benchmarks/wsim/media_1n3_asy.wsim | 8 + benchmarks/wsim/media_1n4_480p.wsim | 20 +- benchmarks/wsim/media_1n4_asy.wsim | 10 + benchmarks/wsim/media_1n5_480p.wsim | 24 +- benchmarks/wsim/media_1n5_asy.wsim | 12 + benchmarks/wsim/media_load_balance_17i7.wsim | 10 +- benchmarks/wsim/media_load_balance_19.wsim | 4 +- .../wsim/media_load_balance_4k12u7.wsim | 2 + .../wsim/media_load_balance_fhd26u7.wsim | 16 +- benchmarks/wsim/media_load_balance_hd01.wsim | 34 +- .../wsim/media_load_balance_hd06mp2.wsim | 6 +- benchmarks/wsim/media_load_balance_hd12.wsim | 6 +- .../wsim/media_load_balance_hd17i4.wsim | 8 +- benchmarks/wsim/media_mfe2_480p.wsim | 12 +- benchmarks/wsim/media_mfe3_480p.wsim | 18 +- benchmarks/wsim/media_mfe4_480p.wsim | 24 +- benchmarks/wsim/media_nn_1080p.wsim | 4 + benchmarks/wsim/media_nn_1080p_s1.wsim | 4 +- benchmarks/wsim/media_nn_1080p_s2.wsim | 2 + benchmarks/wsim/media_nn_1080p_s3.wsim | 2 + benchmarks/wsim/media_nn_480p.wsim | 4 + benchmarks/wsim/vcs_balanced.wsim | 52 +- scripts/Makefile.am | 2 +- scripts/media-bench.pl | 736 --------- 34 files changed, 314 insertions(+), 2327 deletions(-) delete mode 100644 benchmarks/ewma.h delete mode 100644 benchmarks/ilog2.h delete mode 100755 scripts/media-bench.pl diff --git a/benchmarks/Makefile.am b/benchmarks/Makefile.am index 1f05adf31527..45b923ebbae3 100644 --- a/benchmarks/Makefile.am +++ b/benchmarks/Makefile.am @@ -25,4 +25,4 @@ gem_latency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_latency_LDADD = $(LDADD) -lpthread gem_syslatency_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_syslatency_LDADD = $(LDADD) -lpthread -gem_wsim_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la -lpthread +gem_wsim_LDADD = $(LDADD) -lpthread diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources index ee045fb309ad..dae3cdda4cf7 100644 --- a/benchmarks/Makefile.sources +++ b/benchmarks/Makefile.sources @@ -19,12 +19,6 @@ benchmarks_prog_list = \ vgem_mmap \ $(NULL) -gem_wsim_SOURCES = \ - gem_wsim.c \ - ewma.h \ - ilog2.h \ - $(NULL) - LIBDRM_INTEL_BENCHMARKS = \ intel_upload_blit_large \ intel_upload_blit_large_gtt \ diff --git a/benchmarks/ewma.h b/benchmarks/ewma.h deleted file mode 100644 index 8711004ed992..000000000000 --- a/benchmarks/ewma.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef EWMA_H -#define EWMA_H - -#include <ilog2.h> - -#define BUILD_BUG_ON(expr) -#define BUILD_BUG_ON_NOT_POWER_OF_2(expr) - -/* - * Exponentially weighted moving average (EWMA) - * - * This implements a fixed-precision EWMA algorithm, with both the - * precision and fall-off coefficient determined at compile-time - * and built into the generated helper funtions. - * - * The first argument to the macro is the name that will be used - * for the struct and helper functions. - * - * The second argument, the precision, expresses how many bits are - * used for the fractional part of the fixed-precision values. - * - * The third argument, the weight reciprocal, determines how the - * new values will be weighed vs. the old state, new values will - * get weight 1/weight_rcp and old values 1-1/weight_rcp. Note - * that this parameter must be a power of two for efficiency. - */ - -#define DECLARE_EWMA(T, name, _precision, _weight_rcp) \ - struct ewma_##name { \ - T internal; \ - }; \ - static inline void ewma_##name##_init(struct ewma_##name *e) \ - { \ - BUILD_BUG_ON(!__builtin_constant_p(_precision)); \ - BUILD_BUG_ON(!__builtin_constant_p(_weight_rcp)); \ - /* \ - * Even if you want to feed it just 0/1 you should have \ - * some bits for the non-fractional part... \ - */ \ - BUILD_BUG_ON((_precision) > 30); \ - BUILD_BUG_ON_NOT_POWER_OF_2(_weight_rcp); \ - e->internal = 0; \ - } \ - static inline T \ - ewma_##name##_read(struct ewma_##name *e) \ - { \ - BUILD_BUG_ON(!__builtin_constant_p(_precision)); \ - BUILD_BUG_ON(!__builtin_constant_p(_weight_rcp)); \ - BUILD_BUG_ON((_precision) > 30); \ - BUILD_BUG_ON_NOT_POWER_OF_2(_weight_rcp); \ - return e->internal >> (_precision); \ - } \ - static inline void ewma_##name##_add(struct ewma_##name *e, \ - T val) \ - { \ - const T weight_rcp = ilog2(_weight_rcp); \ - const T precision = _precision; \ - T internal = e->internal; \ - \ - BUILD_BUG_ON(!__builtin_constant_p(_precision)); \ - BUILD_BUG_ON(!__builtin_constant_p(_weight_rcp)); \ - BUILD_BUG_ON((_precision) > 30); \ - BUILD_BUG_ON_NOT_POWER_OF_2(_weight_rcp); \ - \ - e->internal = internal ? \ - (((internal << weight_rcp) - internal) + \ - (val << precision)) >> weight_rcp : \ - (val << precision); \ - } - -#endif /* EWMA_H */ diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index ad4edb936920..5cc71c56fe6e 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -55,7 +55,6 @@ #include "sw_sync.h" #include "i915/gem_mman.h" -#include "ewma.h" #include "i915/gem_engine_topology.h" enum intel_engine_id { @@ -154,21 +153,12 @@ struct w_step struct drm_i915_gem_execbuffer2 eb; struct drm_i915_gem_exec_object2 *obj; - struct drm_i915_gem_relocation_entry reloc[5]; + struct drm_i915_gem_relocation_entry reloc[1]; unsigned long bb_sz; uint32_t bb_handle; - uint32_t *seqno_value; - uint32_t *seqno_address; - uint32_t *rt0_value; - uint32_t *rt0_address; - uint32_t *rt1_address; - uint32_t *latch_value; - uint32_t *latch_address; uint32_t *recursive_bb_start; }; -DECLARE_EWMA(uint64_t, rt, 4, 2) - struct ctx { uint32_t id; int priority; @@ -176,9 +166,7 @@ struct ctx { enum intel_engine_id *engine_map; unsigned int bond_count; struct bond *bonds; - bool targets_instance; - bool wants_balance; - unsigned int static_vcs; + bool load_balance; uint64_t sseu; }; @@ -194,13 +182,11 @@ struct workload pthread_t thread; bool run; bool background; - const struct workload_balancer *balancer; unsigned int repeat; unsigned int flags; bool print_stats; uint32_t bb_prng; - uint32_t prng; struct timespec repeat_start; @@ -210,73 +196,25 @@ struct workload int sync_timeline; uint32_t sync_seqno; - uint32_t seqno[NUM_ENGINES]; - struct drm_i915_gem_exec_object2 status_object[2]; - uint32_t *status_page; - uint32_t *status_cs; - unsigned int vcs_rr; - - unsigned long qd_sum[NUM_ENGINES]; - unsigned long nr_bb[NUM_ENGINES]; - struct igt_list_head requests[NUM_ENGINES]; unsigned int nrequest[NUM_ENGINES]; - - struct workload *global_wrk; - const struct workload_balancer *global_balancer; - pthread_mutex_t mutex; - - union { - struct rtavg { - struct ewma_rt avg[NUM_ENGINES]; - uint32_t last[NUM_ENGINES]; - } rt; - }; - - struct busy_balancer { - int fd; - bool first; - unsigned int num_engines; - unsigned int engine_map[NUM_ENGINES]; - uint64_t t_prev; - uint64_t prev[NUM_ENGINES]; - double busy[NUM_ENGINES]; - } busy_balancer; }; -struct intel_mmio_data mmio_data; static const unsigned int nop_calibration_us = 1000; static bool has_nop_calibration = false; static bool sequential = true; static unsigned int master_prng; -static unsigned int context_vcs_rr; - static int verbose = 1; static int fd; static struct drm_i915_gem_context_param_sseu device_sseu = { .slice_mask = -1 /* Force read on first use. */ }; -#define SWAPVCS (1<<0) -#define SEQNO (1<<1) -#define BALANCE (1<<2) -#define RT (1<<3) -#define VCS2REMAP (1<<4) -#define INITVCSRR (1<<5) -#define SYNCEDCLIENTS (1<<6) -#define HEARTBEAT (1<<7) -#define GLOBAL_BALANCE (1<<8) -#define DEPSYNC (1<<9) -#define I915 (1<<10) -#define SSEU (1<<11) - -#define SEQNO_IDX(engine) ((engine) * 16) -#define SEQNO_OFFSET(engine) (SEQNO_IDX(engine) * sizeof(uint32_t)) - -#define RCS_TIMESTAMP (0x2000 + 0x358) -#define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x) +#define SYNCEDCLIENTS (1<<1) +#define DEPSYNC (1<<2) +#define SSEU (1<<3) static const char *ring_str_map[NUM_ENGINES] = { [DEFAULT] = "DEFAULT", @@ -578,26 +516,6 @@ static unsigned int num_engines_in_class(enum intel_engine_id class) return count; } -static void -fill_engines_class(struct i915_engine_class_instance *ci, - enum intel_engine_id class) -{ - unsigned int i, j = 0; - - igt_assert(class == VCS); - - query_engines(); - - for (i = 0; i < __num_engines; i++) { - if (__engines[i].engine_class != I915_ENGINE_CLASS_VIDEO) - continue; - - ci[j].engine_class = __engines[i].engine_class; - ci[j].engine_instance = __engines[i].engine_instance; - j++; - } -} - static void fill_engines_id_class(enum intel_engine_id *list, enum intel_engine_id class) @@ -744,7 +662,6 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) char *_token, *token, *tctx = NULL, *tstart = desc; char *field, *fctx = NULL, *fstart; struct w_step step, *steps = NULL; - bool bcs_used = false; unsigned int valid; int i, j, tmp; @@ -962,9 +879,6 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) valid++; step.engine = i; - - if (step.engine == BCS) - bcs_used = true; } if ((field = strtok_r(fstart, ".", &fctx))) { @@ -1089,9 +1003,6 @@ add_step: } } - if (bcs_used && (flags & VCS2REMAP) && verbose) - printf("BCS usage in workload with VCS2 remapping enabled!\n"); - return wrk; } @@ -1147,7 +1058,7 @@ static unsigned int get_duration(struct workload *wrk, struct w_step *w) static struct ctx * __get_ctx(struct workload *wrk, const struct w_step *w) { - return &wrk->ctx_list[w->context * 2]; + return &wrk->ctx_list[w->context]; } static unsigned long @@ -1179,8 +1090,7 @@ get_bb_sz(const struct w_step *w, unsigned int duration) return d; } -static void -init_bb(struct w_step *w, unsigned int flags) +static void init_bb(struct w_step *w) { const unsigned int arb_period = __get_bb_sz(w, w->preempt_us) / sizeof(uint32_t); @@ -1202,8 +1112,7 @@ init_bb(struct w_step *w, unsigned int flags) munmap(ptr, mmap_len); } -static unsigned int -terminate_bb(struct w_step *w, unsigned int flags) +static unsigned int terminate_bb(struct w_step *w) { const uint32_t bbe = 0xa << 23; unsigned long mmap_start, mmap_len; @@ -1211,13 +1120,7 @@ terminate_bb(struct w_step *w, unsigned int flags) unsigned int r = 0; uint32_t *ptr, *cs; - igt_assert(((flags & RT) && (flags & SEQNO)) || !(flags & RT)); - batch_start -= sizeof(uint32_t); /* bbend */ - if (flags & SEQNO) - batch_start -= 4 * sizeof(uint32_t); - if (flags & RT) - batch_start -= 12 * sizeof(uint32_t); if (w->unbound_duration) batch_start -= 4 * sizeof(uint32_t); /* MI_ARB_CHK + MI_BATCH_BUFFER_START */ @@ -1242,49 +1145,6 @@ terminate_bb(struct w_step *w, unsigned int flags) *cs++ = 0; } - if (flags & SEQNO) { - w->reloc[r++].offset = batch_start + sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = MI_STORE_DWORD_IMM; - w->seqno_address = cs; - *cs++ = 0; - *cs++ = 0; - w->seqno_value = cs; - *cs++ = 0; - } - - if (flags & RT) { - w->reloc[r++].offset = batch_start + sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = MI_STORE_DWORD_IMM; - w->rt0_address = cs; - *cs++ = 0; - *cs++ = 0; - w->rt0_value = cs; - *cs++ = 0; - - w->reloc[r++].offset = batch_start + 2 * sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = 0x24 << 23 | 2; /* MI_STORE_REG_MEM */ - *cs++ = RCS_TIMESTAMP; - w->rt1_address = cs; - *cs++ = 0; - *cs++ = 0; - - w->reloc[r++].offset = batch_start + sizeof(uint32_t); - batch_start += 4 * sizeof(uint32_t); - - *cs++ = MI_STORE_DWORD_IMM; - w->latch_address = cs; - *cs++ = 0; - *cs++ = 0; - w->latch_value = cs; - *cs++ = 0; - } - *cs = bbe; return r; @@ -1301,17 +1161,9 @@ static const unsigned int eb_engine_map[NUM_ENGINES] = { }; static void -eb_set_engine(struct drm_i915_gem_execbuffer2 *eb, - enum intel_engine_id engine, - unsigned int flags) +eb_set_engine(struct drm_i915_gem_execbuffer2 *eb, enum intel_engine_id engine) { - if (engine == VCS2 && (flags & VCS2REMAP)) - engine = BCS; - - if ((flags & I915) && engine == VCS) - eb->flags = 0; - else - eb->flags = eb_engine_map[engine]; + eb->flags = eb_engine_map[engine]; } static unsigned int @@ -1324,20 +1176,20 @@ find_engine_in_map(struct ctx *ctx, enum intel_engine_id engine) return i + 1; } - igt_assert(ctx->wants_balance); + igt_assert(ctx->load_balance); return 0; } static void eb_update_flags(struct workload *wrk, struct w_step *w, - enum intel_engine_id engine, unsigned int flags) + enum intel_engine_id engine) { struct ctx *ctx = __get_ctx(wrk, w); if (ctx->engine_map) w->eb.flags = find_engine_in_map(ctx, engine); else - eb_set_engine(&w->eb, engine, flags); + eb_set_engine(&w->eb, engine); w->eb.flags |= I915_EXEC_HANDLE_LUT; w->eb.flags |= I915_EXEC_NO_RELOC; @@ -1347,32 +1199,18 @@ eb_update_flags(struct workload *wrk, struct w_step *w, w->eb.flags |= I915_EXEC_FENCE_OUT; } -static struct drm_i915_gem_exec_object2 * -get_status_objects(struct workload *wrk) -{ - if (wrk->flags & GLOBAL_BALANCE) - return wrk->global_wrk->status_object; - else - return wrk->status_object; -} - static uint32_t get_ctxid(struct workload *wrk, struct w_step *w) { - struct ctx *ctx = __get_ctx(wrk, w); - - if (ctx->targets_instance && ctx->wants_balance && w->engine == VCS) - return wrk->ctx_list[w->context * 2 + 1].id; - else - return wrk->ctx_list[w->context * 2].id; + return wrk->ctx_list[w->context].id; } static void -alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) +alloc_step_batch(struct workload *wrk, struct w_step *w) { enum intel_engine_id engine = w->engine; unsigned int j = 0; - unsigned int nr_obj = 3 + w->data_deps.nr; + unsigned int nr_obj = 2 + w->data_deps.nr; unsigned int i; w->obj = calloc(nr_obj, sizeof(*w->obj)); @@ -1383,11 +1221,6 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) j++; igt_assert(j < nr_obj); - if (flags & SEQNO) { - w->obj[j++] = get_status_objects(wrk)[0]; - igt_assert(j < nr_obj); - } - for (i = 0; i < w->data_deps.nr; i++) { igt_assert(w->data_deps.list[i] <= 0); if (w->data_deps.list[i]) { @@ -1410,26 +1243,20 @@ alloc_step_batch(struct workload *wrk, struct w_step *w, unsigned int flags) w->bb_sz = get_bb_sz(w, w->duration.max); w->bb_handle = w->obj[j].handle = gem_create(fd, w->bb_sz + (w->unbound_duration ? 4096 : 0)); - init_bb(w, flags); - w->obj[j].relocation_count = terminate_bb(w, flags); + init_bb(w); + w->obj[j].relocation_count = terminate_bb(w); if (w->obj[j].relocation_count) { + igt_assert(w->unbound_duration); w->obj[j].relocs_ptr = to_user_pointer(&w->reloc); - for (i = 0; i < w->obj[j].relocation_count; i++) - w->reloc[i].target_handle = 1; - if (w->unbound_duration) - w->reloc[0].target_handle = j; + w->reloc[0].target_handle = j; } w->eb.buffers_ptr = to_user_pointer(w->obj); w->eb.buffer_count = j + 1; w->eb.rsvd1 = get_ctxid(wrk, w); - if (flags & SWAPVCS && engine == VCS1) - engine = VCS2; - else if (flags & SWAPVCS && engine == VCS2) - engine = VCS1; - eb_update_flags(wrk, w, engine, flags); + eb_update_flags(wrk, w, engine); #ifdef DEBUG printf("%u: %u:|", w->idx, w->eb.buffer_count); for (i = 0; i <= j; i++) @@ -1528,7 +1355,7 @@ set_ctx_sseu(struct ctx *ctx, uint64_t slice_mask) if (slice_mask == -1) slice_mask = device_sseu.slice_mask; - if (ctx->engine_map && ctx->wants_balance) { + if (ctx->engine_map && ctx->load_balance) { sseu.flags = I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX; sseu.engine.engine_class = I915_ENGINE_CLASS_INVALID; sseu.engine.engine_instance = 0; @@ -1566,51 +1393,22 @@ static size_t sizeof_engines_bond(int count) #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) -static int -prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) +static int prepare_workload(unsigned int id, struct workload *wrk) { - unsigned int ctx_vcs; + uint32_t share_vm = 0; int max_ctx = -1; struct w_step *w; int i, j; wrk->id = id; - wrk->prng = rand(); wrk->bb_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); wrk->run = true; - ctx_vcs = 0; - if (flags & INITVCSRR) - ctx_vcs = id & 1; - wrk->vcs_rr = ctx_vcs; - - if (flags & GLOBAL_BALANCE) { - int ret = pthread_mutex_init(&wrk->mutex, NULL); - igt_assert(ret == 0); - } - - if (flags & SEQNO) { - if (!(flags & GLOBAL_BALANCE) || id == 0) { - uint32_t handle; - - handle = gem_create(fd, 4096); - gem_set_caching(fd, handle, I915_CACHING_CACHED); - wrk->status_object[0].handle = handle; - wrk->status_page = gem_mmap__cpu(fd, handle, 0, 4096, - PROT_READ); - - handle = gem_create(fd, 4096); - wrk->status_object[1].handle = handle; - wrk->status_cs = gem_mmap__wc(fd, handle, - 0, 4096, PROT_WRITE); - } - } - /* * Pre-scan workload steps to allocate context list storage. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - int ctx = w->context * 2 + 1; /* Odd slots are special. */ + int ctx = w->context + 1; int delta; w->wrk = wrk; @@ -1630,27 +1428,16 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) } /* - * Identify if contexts target specific engine instances and if they - * want to be balanced. - * * Transfer over engine map configuration from the workload step. */ - for (j = 0; j < wrk->nr_ctxs; j += 2) { + for (j = 0; j < wrk->nr_ctxs; j++) { struct ctx *ctx = &wrk->ctx_list[j]; - bool targets = false; - bool balance = false; - for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - if (w->context != (j / 2)) + if (w->context != j) continue; - if (w->type == BATCH) { - if (w->engine == VCS) - balance = true; - else - targets = true; - } else if (w->type == ENGINE_MAP) { + if (w->type == ENGINE_MAP) { ctx->engine_map = w->engine_map; ctx->engine_map_count = w->engine_map_count; } else if (w->type == LOAD_BALANCE) { @@ -1658,9 +1445,9 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) wsim_err("Load balancing needs an engine map!\n"); return 1; } - ctx->wants_balance = w->load_balance; + ctx->load_balance = w->load_balance; } else if (w->type == BOND) { - if (!ctx->wants_balance) { + if (!ctx->load_balance) { wsim_err("Engine bonds need load balancing engine map!\n"); return 1; } @@ -1675,133 +1462,53 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) w->bond_master; } } - - wrk->ctx_list[j].targets_instance = targets; - if (flags & I915) - wrk->ctx_list[j].wants_balance |= balance; - } - - /* - * Ensure VCS is not allowed with engine map contexts. - */ - for (j = 0; j < wrk->nr_ctxs; j += 2) { - for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - if (w->context != (j / 2)) - continue; - - if (w->type != BATCH) - continue; - - if (wrk->ctx_list[j].engine_map && - !wrk->ctx_list[j].wants_balance && - (w->engine == VCS || w->engine == DEFAULT)) { - wsim_err("Batches targetting engine maps must use explicit engines!\n"); - return -1; - } - } } - /* * Create and configure contexts. */ - for (i = 0; i < wrk->nr_ctxs; i += 2) { + for (i = 0; i < wrk->nr_ctxs; i++) { + struct drm_i915_gem_context_create_ext_setparam ext = { + .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM, + .param.param = I915_CONTEXT_PARAM_VM, + }; + struct drm_i915_gem_context_create_ext args = { }; struct ctx *ctx = &wrk->ctx_list[i]; - uint32_t ctx_id, share_vm = 0; + uint32_t ctx_id; - if (ctx->id) - continue; + igt_assert(!ctx->id); - if ((flags & I915) || ctx->engine_map) { - struct drm_i915_gem_context_create_ext_setparam ext = { - .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM, - .param.param = I915_CONTEXT_PARAM_VM, + /* Find existing context to share ppgtt with. */ + for (j = 0; !share_vm && j < wrk->nr_ctxs; j++) { + struct drm_i915_gem_context_param param = { + .param = I915_CONTEXT_PARAM_VM, + .ctx_id = wrk->ctx_list[j].id, }; - struct drm_i915_gem_context_create_ext args = { }; - - /* Find existing context to share ppgtt with. */ - for (j = 0; j < wrk->nr_ctxs; j++) { - struct drm_i915_gem_context_param param = { - .param = I915_CONTEXT_PARAM_VM, - }; - - if (!wrk->ctx_list[j].id) - continue; - - param.ctx_id = wrk->ctx_list[j].id; - gem_context_get_param(fd, ¶m); - igt_assert(param.value); - - share_vm = param.value; - - ext.param.value = share_vm; - args.flags = - I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS; - args.extensions = to_user_pointer(&ext); - break; - } - - if ((!ctx->engine_map && !ctx->targets_instance) || - (ctx->engine_map && ctx->wants_balance)) - args.flags |= - I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE; - - drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, - &args); + if (!param.ctx_id) + continue; - ctx_id = args.ctx_id; - } else { - struct drm_i915_gem_context_create args = {}; + gem_context_get_param(fd, ¶m); + igt_assert(param.value); + share_vm = param.value; + break; + } - drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &args); - ctx_id = args.ctx_id; + if (share_vm) { + ext.param.value = share_vm; + args.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS; + args.extensions = to_user_pointer(&ext); } - igt_assert(ctx_id); + drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, &args); + igt_assert(args.ctx_id); + + ctx_id = args.ctx_id; ctx->id = ctx_id; ctx->sseu = device_sseu.slice_mask; - if (flags & GLOBAL_BALANCE) { - ctx->static_vcs = context_vcs_rr; - context_vcs_rr ^= 1; - } else { - ctx->static_vcs = ctx_vcs; - ctx_vcs ^= 1; - } - __configure_context(ctx_id, wrk->prio); - /* - * Do we need a separate context to satisfy this workloads which - * both want to target specific engines and be balanced by i915? - */ - if ((flags & I915) && ctx->wants_balance && - ctx->targets_instance && !ctx->engine_map) { - struct drm_i915_gem_context_create_ext_setparam ext = { - .base.name = I915_CONTEXT_CREATE_EXT_SETPARAM, - .param.param = I915_CONTEXT_PARAM_VM, - .param.value = share_vm, - }; - struct drm_i915_gem_context_create_ext args = { - .extensions = to_user_pointer(&ext), - .flags = - I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS | - I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE, - }; - - igt_assert(share_vm); - - drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT, - &args); - - igt_assert(args.ctx_id); - ctx_id = args.ctx_id; - wrk->ctx_list[i + 1].id = args.ctx_id; - - __configure_context(ctx_id, wrk->prio); - } - if (ctx->engine_map) { struct i915_context_param_engines *set_engines = alloca0(sizeof_param_engines(ctx->engine_map_count + 1)); @@ -1815,7 +1522,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) }; struct i915_context_engines_bond *last = NULL; - if (ctx->wants_balance) { + if (ctx->load_balance) { set_engines->extensions = to_user_pointer(load_balance); @@ -1869,34 +1576,6 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) } load_balance->base.next_extension = to_user_pointer(last); - gem_context_set_param(fd, ¶m); - } else if (ctx->wants_balance) { - const unsigned int count = num_engines_in_class(VCS); - struct i915_context_engines_load_balance *load_balance = - alloca0(sizeof_load_balance(count)); - struct i915_context_param_engines *set_engines = - alloca0(sizeof_param_engines(count + 1)); - struct drm_i915_gem_context_param param = { - .ctx_id = ctx_id, - .param = I915_CONTEXT_PARAM_ENGINES, - .size = sizeof_param_engines(count + 1), - .value = to_user_pointer(set_engines), - }; - - set_engines->extensions = to_user_pointer(load_balance); - - set_engines->engines[0].engine_class = - I915_ENGINE_CLASS_INVALID; - set_engines->engines[0].engine_instance = - I915_ENGINE_CLASS_INVALID_NONE; - fill_engines_class(&set_engines->engines[1], VCS); - - load_balance->base.name = - I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE; - load_balance->num_siblings = count; - - fill_engines_class(&load_balance->engines[0], VCS); - gem_context_set_param(fd, ¶m); } @@ -1904,11 +1583,11 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) /* Set to slice 0 only, one slice. */ ctx->sseu = set_ctx_sseu(ctx, 1); } - - if (share_vm) - vm_destroy(fd, share_vm); } + if (share_vm) + vm_destroy(fd, share_vm); + /* Record default preemption. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == BATCH) @@ -1954,16 +1633,10 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) * Allocate batch buffers. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - unsigned int _flags = flags; - enum intel_engine_id engine = w->engine; - if (w->type != BATCH) continue; - if (engine == VCS) - _flags &= ~SWAPVCS; - - alloc_step_batch(wrk, w, _flags); + alloc_step_batch(wrk, w); } return 0; @@ -1980,602 +1653,6 @@ static int elapsed_us(const struct timespec *start, const struct timespec *end) return elapsed(start, end) * 1e6; } -static enum intel_engine_id get_vcs_engine(unsigned int n) -{ - const enum intel_engine_id vcs_engines[2] = { VCS1, VCS2 }; - - igt_assert(n < ARRAY_SIZE(vcs_engines)); - - return vcs_engines[n]; -} - -static uint32_t new_seqno(struct workload *wrk, enum intel_engine_id engine) -{ - uint32_t seqno; - int ret; - - if (wrk->flags & GLOBAL_BALANCE) { - igt_assert(wrk->global_wrk); - wrk = wrk->global_wrk; - - ret = pthread_mutex_lock(&wrk->mutex); - igt_assert(ret == 0); - } - - seqno = ++wrk->seqno[engine]; - - if (wrk->flags & GLOBAL_BALANCE) { - ret = pthread_mutex_unlock(&wrk->mutex); - igt_assert(ret == 0); - } - - return seqno; -} - -static uint32_t -current_seqno(struct workload *wrk, enum intel_engine_id engine) -{ - if (wrk->flags & GLOBAL_BALANCE) - return wrk->global_wrk->seqno[engine]; - else - return wrk->seqno[engine]; -} - -static uint32_t -read_status_page(struct workload *wrk, unsigned int idx) -{ - if (wrk->flags & GLOBAL_BALANCE) - return READ_ONCE(wrk->global_wrk->status_page[idx]); - else - return READ_ONCE(wrk->status_page[idx]); -} - -static uint32_t -current_gpu_seqno(struct workload *wrk, enum intel_engine_id engine) -{ - return read_status_page(wrk, SEQNO_IDX(engine)); -} - -struct workload_balancer { - unsigned int id; - const char *name; - const char *desc; - unsigned int flags; - unsigned int min_gen; - - int (*init)(const struct workload_balancer *balancer, - struct workload *wrk); - unsigned int (*get_qd)(const struct workload_balancer *balancer, - struct workload *wrk, - enum intel_engine_id engine); - enum intel_engine_id (*balance)(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w); -}; - -static enum intel_engine_id -rr_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - unsigned int engine; - - engine = get_vcs_engine(wrk->vcs_rr); - wrk->vcs_rr ^= 1; - - return engine; -} - -static enum intel_engine_id -rand_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return get_vcs_engine(hars_petruska_f54_1_random(&wrk->prng) & 1); -} - -static unsigned int -get_qd_depth(const struct workload_balancer *balancer, - struct workload *wrk, enum intel_engine_id engine) -{ - return current_seqno(wrk, engine) - current_gpu_seqno(wrk, engine); -} - -static enum intel_engine_id -__qd_select_engine(struct workload *wrk, const unsigned long *qd, bool random) -{ - unsigned int n; - - if (qd[VCS1] < qd[VCS2]) - n = 0; - else if (qd[VCS1] > qd[VCS2]) - n = 1; - else if (random) - n = hars_petruska_f54_1_random(&wrk->prng) & 1; - else - n = wrk->vcs_rr; - wrk->vcs_rr = n ^ 1; - - return get_vcs_engine(n); -} - -static enum intel_engine_id -__qd_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w, bool random) -{ - enum intel_engine_id engine; - unsigned long qd[NUM_ENGINES]; - - igt_assert(w->engine == VCS); - - qd[VCS1] = balancer->get_qd(balancer, wrk, VCS1); - wrk->qd_sum[VCS1] += qd[VCS1]; - - qd[VCS2] = balancer->get_qd(balancer, wrk, VCS2); - wrk->qd_sum[VCS2] += qd[VCS2]; - - engine = __qd_select_engine(wrk, qd, random); - -#ifdef DEBUG - printf("qd_balance[%u]: 1:%ld 2:%ld rr:%u = %u\t(%u - %u) (%u - %u)\n", - wrk->id, qd[VCS1], qd[VCS2], wrk->vcs_rr, engine, - current_seqno(wrk, VCS1), current_gpu_seqno(wrk, VCS1), - current_seqno(wrk, VCS2), current_gpu_seqno(wrk, VCS2)); -#endif - return engine; -} - -static enum intel_engine_id -qd_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return __qd_balance(balancer, wrk, w, false); -} - -static enum intel_engine_id -qdr_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return __qd_balance(balancer, wrk, w, true); -} - -static enum intel_engine_id -qdavg_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - unsigned long qd[NUM_ENGINES]; - unsigned int engine; - - igt_assert(w->engine == VCS); - - for (engine = VCS1; engine <= VCS2; engine++) { - qd[engine] = balancer->get_qd(balancer, wrk, engine); - wrk->qd_sum[engine] += qd[engine]; - - ewma_rt_add(&wrk->rt.avg[engine], qd[engine]); - qd[engine] = ewma_rt_read(&wrk->rt.avg[engine]); - } - - engine = __qd_select_engine(wrk, qd, false); -#ifdef DEBUG - printf("qdavg_balance[%u]: 1:%ld 2:%ld rr:%u = %u\t(%u - %u) (%u - %u)\n", - wrk->id, qd[VCS1], qd[VCS2], wrk->vcs_rr, engine, - current_seqno(wrk, VCS1), current_gpu_seqno(wrk, VCS1), - current_seqno(wrk, VCS2), current_gpu_seqno(wrk, VCS2)); -#endif - return engine; -} - -static enum intel_engine_id -__rt_select_engine(struct workload *wrk, unsigned long *qd, bool random) -{ - qd[VCS1] >>= 10; - qd[VCS2] >>= 10; - - return __qd_select_engine(wrk, qd, random); -} - -struct rt_depth { - uint32_t seqno; - uint32_t submitted; - uint32_t completed; -}; - -static void get_rt_depth(struct workload *wrk, - unsigned int engine, - struct rt_depth *rt) -{ - const unsigned int idx = SEQNO_IDX(engine); - uint32_t latch; - - do { - latch = read_status_page(wrk, idx + 3); - rt->submitted = read_status_page(wrk, idx + 1); - rt->completed = read_status_page(wrk, idx + 2); - rt->seqno = read_status_page(wrk, idx); - } while (latch != rt->seqno); -} - -static enum intel_engine_id -__rt_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w, bool random) -{ - unsigned long qd[NUM_ENGINES]; - unsigned int engine; - - igt_assert(w->engine == VCS); - - /* Estimate the "speed" of the most recent batch - * (finish time - submit time) - * and use that as an approximate for the total remaining time for - * all batches on that engine, plus the time we expect this batch to - * take. We try to keep the total balanced between the engines. - */ - for (engine = VCS1; engine <= VCS2; engine++) { - struct rt_depth rt; - - get_rt_depth(wrk, engine, &rt); - qd[engine] = current_seqno(wrk, engine) - rt.seqno; - wrk->qd_sum[engine] += qd[engine]; - qd[engine] = (qd[engine] + 1) * (rt.completed - rt.submitted); -#ifdef DEBUG - printf("rt[0] = %d (%d - %d) x %d (%d - %d) = %ld\n", - current_seqno(wrk, engine) - rt.seqno, - current_seqno(wrk, engine), rt.seqno, - rt.completed - rt.submitted, - rt.completed, rt.submitted, - qd[engine]); -#endif - } - - return __rt_select_engine(wrk, qd, random); -} - -static enum intel_engine_id -rt_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - - return __rt_balance(balancer, wrk, w, false); -} - -static enum intel_engine_id -rtr_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return __rt_balance(balancer, wrk, w, true); -} - -static enum intel_engine_id -rtavg_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - unsigned long qd[NUM_ENGINES]; - unsigned int engine; - - igt_assert(w->engine == VCS); - - /* Estimate the average "speed" of the most recent batches - * (finish time - submit time) - * and use that as an approximate for the total remaining time for - * all batches on that engine plus the time we expect to execute in. - * We try to keep the total remaining balanced between the engines. - */ - for (engine = VCS1; engine <= VCS2; engine++) { - struct rt_depth rt; - - get_rt_depth(wrk, engine, &rt); - if (rt.seqno != wrk->rt.last[engine]) { - igt_assert((long)(rt.completed - rt.submitted) > 0); - ewma_rt_add(&wrk->rt.avg[engine], - rt.completed - rt.submitted); - wrk->rt.last[engine] = rt.seqno; - } - qd[engine] = current_seqno(wrk, engine) - rt.seqno; - wrk->qd_sum[engine] += qd[engine]; - qd[engine] = - (qd[engine] + 1) * ewma_rt_read(&wrk->rt.avg[engine]); - -#ifdef DEBUG - printf("rtavg[%d] = %d (%d - %d) x %ld (%d) = %ld\n", - engine, - current_seqno(wrk, engine) - rt.seqno, - current_seqno(wrk, engine), rt.seqno, - ewma_rt_read(&wrk->rt.avg[engine]), - rt.completed - rt.submitted, - qd[engine]); -#endif - } - - return __rt_select_engine(wrk, qd, false); -} - -static enum intel_engine_id -context_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - return get_vcs_engine(__get_ctx(wrk, w)->static_vcs); -} - -static unsigned int -get_engine_busy(const struct workload_balancer *balancer, - struct workload *wrk, enum intel_engine_id engine) -{ - struct busy_balancer *bb = &wrk->busy_balancer; - - if (engine == VCS2 && (wrk->flags & VCS2REMAP)) - engine = BCS; - - return bb->busy[bb->engine_map[engine]]; -} - -static void -get_pmu_stats(const struct workload_balancer *b, struct workload *wrk) -{ - struct busy_balancer *bb = &wrk->busy_balancer; - uint64_t val[7]; - unsigned int i; - - igt_assert_eq(read(bb->fd, val, sizeof(val)), - (2 + bb->num_engines) * sizeof(uint64_t)); - - if (!bb->first) { - for (i = 0; i < bb->num_engines; i++) { - double d; - - d = (val[2 + i] - bb->prev[i]) * 100; - d /= val[1] - bb->t_prev; - bb->busy[i] = d; - } - } - - for (i = 0; i < bb->num_engines; i++) - bb->prev[i] = val[2 + i]; - - bb->t_prev = val[1]; - bb->first = false; -} - -static enum intel_engine_id -busy_avg_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - get_pmu_stats(balancer, wrk); - - return qdavg_balance(balancer, wrk, w); -} - -static enum intel_engine_id -busy_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - get_pmu_stats(balancer, wrk); - - return qd_balance(balancer, wrk, w); -} - -static int -busy_init(const struct workload_balancer *balancer, struct workload *wrk) -{ - struct busy_balancer *bb = &wrk->busy_balancer; - struct engine_desc { - unsigned class, inst; - enum intel_engine_id id; - } *d, engines[] = { - { I915_ENGINE_CLASS_RENDER, 0, RCS }, - { I915_ENGINE_CLASS_COPY, 0, BCS }, - { I915_ENGINE_CLASS_VIDEO, 0, VCS1 }, - { I915_ENGINE_CLASS_VIDEO, 1, VCS2 }, - { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, VECS }, - { 0, 0, VCS } - }; - - bb->num_engines = 0; - bb->first = true; - bb->fd = -1; - - for (d = &engines[0]; d->id != VCS; d++) { - int pfd; - - pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, - d->inst), - bb->fd); - if (pfd < 0) { - if (d->id != VCS2) - return -(10 + bb->num_engines); - else - continue; - } - - if (bb->num_engines == 0) - bb->fd = pfd; - - bb->engine_map[d->id] = bb->num_engines++; - } - - if (bb->num_engines < 5 && !(wrk->flags & VCS2REMAP)) - return -1; - - return 0; -} - -static const struct workload_balancer all_balancers[] = { - { - .id = 0, - .name = "rr", - .desc = "Simple round-robin.", - .balance = rr_balance, - }, - { - .id = 6, - .name = "rand", - .desc = "Random selection.", - .balance = rand_balance, - }, - { - .id = 1, - .name = "qd", - .desc = "Queue depth estimation with round-robin on equal depth.", - .flags = SEQNO, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = qd_balance, - }, - { - .id = 5, - .name = "qdr", - .desc = "Queue depth estimation with random selection on equal depth.", - .flags = SEQNO, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = qdr_balance, - }, - { - .id = 7, - .name = "qdavg", - .desc = "Like qd, but using an average queue depth estimator.", - .flags = SEQNO, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = qdavg_balance, - }, - { - .id = 2, - .name = "rt", - .desc = "Queue depth plus last runtime estimation.", - .flags = SEQNO | RT, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = rt_balance, - }, - { - .id = 3, - .name = "rtr", - .desc = "Like rt but with random engine selection on equal depth.", - .flags = SEQNO | RT, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = rtr_balance, - }, - { - .id = 4, - .name = "rtavg", - .desc = "Improved version rt tracking average execution speed per engine.", - .flags = SEQNO | RT, - .min_gen = 8, - .get_qd = get_qd_depth, - .balance = rtavg_balance, - }, - { - .id = 8, - .name = "context", - .desc = "Static round-robin VCS assignment at context creation.", - .balance = context_balance, - }, - { - .id = 9, - .name = "busy", - .desc = "Engine busyness based balancing.", - .init = busy_init, - .get_qd = get_engine_busy, - .balance = busy_balance, - }, - { - .id = 10, - .name = "busy-avg", - .desc = "Average engine busyness based balancing.", - .init = busy_init, - .get_qd = get_engine_busy, - .balance = busy_avg_balance, - }, - { - .id = 11, - .name = "i915", - .desc = "i915 balancing.", - .flags = I915, - }, -}; - -static unsigned int -global_get_qd(const struct workload_balancer *balancer, - struct workload *wrk, enum intel_engine_id engine) -{ - igt_assert(wrk->global_wrk); - igt_assert(wrk->global_balancer); - - return wrk->global_balancer->get_qd(wrk->global_balancer, - wrk->global_wrk, engine); -} - -static enum intel_engine_id -global_balance(const struct workload_balancer *balancer, - struct workload *wrk, struct w_step *w) -{ - enum intel_engine_id engine; - int ret; - - igt_assert(wrk->global_wrk); - igt_assert(wrk->global_balancer); - - wrk = wrk->global_wrk; - - ret = pthread_mutex_lock(&wrk->mutex); - igt_assert(ret == 0); - - engine = wrk->global_balancer->balance(wrk->global_balancer, wrk, w); - - ret = pthread_mutex_unlock(&wrk->mutex); - igt_assert(ret == 0); - - return engine; -} - -static const struct workload_balancer global_balancer = { - .id = ~0, - .name = "global", - .desc = "Global balancer", - .get_qd = global_get_qd, - .balance = global_balance, - }; - -static void -update_bb_seqno(struct w_step *w, enum intel_engine_id engine, uint32_t seqno) -{ - gem_set_domain(fd, w->bb_handle, - I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); - - w->reloc[0].delta = SEQNO_OFFSET(engine); - - *w->seqno_value = seqno; - *w->seqno_address = w->reloc[0].presumed_offset + w->reloc[0].delta; - - /* If not using NO_RELOC, force the relocations */ - if (!(w->eb.flags & I915_EXEC_NO_RELOC)) - w->reloc[0].presumed_offset = -1; -} - -static void -update_bb_rt(struct w_step *w, enum intel_engine_id engine, uint32_t seqno) -{ - gem_set_domain(fd, w->bb_handle, - I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); - - w->reloc[1].delta = SEQNO_OFFSET(engine) + sizeof(uint32_t); - w->reloc[2].delta = SEQNO_OFFSET(engine) + 2 * sizeof(uint32_t); - w->reloc[3].delta = SEQNO_OFFSET(engine) + 3 * sizeof(uint32_t); - - *w->latch_value = seqno; - *w->latch_address = w->reloc[3].presumed_offset + w->reloc[3].delta; - - *w->rt0_value = *REG(RCS_TIMESTAMP); - *w->rt0_address = w->reloc[1].presumed_offset + w->reloc[1].delta; - *w->rt1_address = w->reloc[2].presumed_offset + w->reloc[2].delta; - - /* If not using NO_RELOC, force the relocations */ - if (!(w->eb.flags & I915_EXEC_NO_RELOC)) { - w->reloc[1].presumed_offset = -1; - w->reloc[2].presumed_offset = -1; - w->reloc[3].presumed_offset = -1; - } -} - static void update_bb_start(struct w_step *w) { @@ -2606,123 +1683,12 @@ static void w_sync_to(struct workload *wrk, struct w_step *w, int target) gem_sync(fd, wrk->steps[target].obj[0].handle); } -static uint32_t *get_status_cs(struct workload *wrk) -{ - return wrk->status_cs; -} - -#define INIT_CLOCKS 0x1 -#define INIT_ALL (INIT_CLOCKS) -static void init_status_page(struct workload *wrk, unsigned int flags) -{ - struct drm_i915_gem_relocation_entry reloc[4] = {}; - struct drm_i915_gem_exec_object2 *status_object = - get_status_objects(wrk); - struct drm_i915_gem_execbuffer2 eb = { - .buffer_count = ARRAY_SIZE(wrk->status_object), - .buffers_ptr = to_user_pointer(status_object) - }; - uint32_t *base = get_status_cs(wrk); - - /* Want to make sure that the balancer has a reasonable view of - * the background busyness of each engine. To do that we occasionally - * send a dummy batch down the pipeline. - */ - - if (!base) - return; - - gem_set_domain(fd, status_object[1].handle, - I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC); - - status_object[1].relocs_ptr = to_user_pointer(reloc); - status_object[1].relocation_count = 2; - if (flags & INIT_CLOCKS) - status_object[1].relocation_count += 2; - - for (int engine = 0; engine < NUM_ENGINES; engine++) { - struct drm_i915_gem_relocation_entry *r = reloc; - uint64_t presumed_offset = status_object[0].offset; - uint32_t offset = engine * 128; - uint32_t *cs = base + offset / sizeof(*cs); - uint64_t addr; - - r->offset = offset + sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = MI_STORE_DWORD_IMM; - *cs++ = addr; - *cs++ = addr >> 32; - *cs++ = new_seqno(wrk, engine); - offset += 4 * sizeof(uint32_t); - - /* When we are busy, we can just reuse the last set of timings. - * If we have been idle for a while, we want to resample the - * latency on each engine (to measure external load). - */ - if (flags & INIT_CLOCKS) { - r->offset = offset + sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine) + sizeof(uint32_t); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = MI_STORE_DWORD_IMM; - *cs++ = addr; - *cs++ = addr >> 32; - *cs++ = *REG(RCS_TIMESTAMP); - offset += 4 * sizeof(uint32_t); - - r->offset = offset + 2 * sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine) + 2*sizeof(uint32_t); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = 0x24 << 23 | 2; /* MI_STORE_REG_MEM */ - *cs++ = RCS_TIMESTAMP; - *cs++ = addr; - *cs++ = addr >> 32; - offset += 4 * sizeof(uint32_t); - } - - r->offset = offset + sizeof(uint32_t); - r->delta = SEQNO_OFFSET(engine) + 3*sizeof(uint32_t); - r->presumed_offset = presumed_offset; - addr = presumed_offset + r->delta; - r++; - *cs++ = MI_STORE_DWORD_IMM; - *cs++ = addr; - *cs++ = addr >> 32; - *cs++ = current_seqno(wrk, engine); - offset += 4 * sizeof(uint32_t); - - *cs++ = MI_BATCH_BUFFER_END; - - eb_set_engine(&eb, engine, wrk->flags); - eb.flags |= I915_EXEC_HANDLE_LUT; - eb.flags |= I915_EXEC_NO_RELOC; - - eb.batch_start_offset = 128 * engine; - - gem_execbuf(fd, &eb); - } -} - static void -do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, - unsigned int flags) +do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine) { - uint32_t seqno = new_seqno(wrk, engine); unsigned int i; - eb_update_flags(wrk, w, engine, flags); - - if (flags & SEQNO) - update_bb_seqno(w, engine, seqno); - if (flags & RT) - update_bb_rt(w, engine, seqno); - + eb_update_flags(wrk, w, engine); update_bb_start(w); w->eb.batch_start_offset = @@ -2758,9 +1724,8 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, } } -static bool sync_deps(struct workload *wrk, struct w_step *w) +static void sync_deps(struct workload *wrk, struct w_step *w) { - bool synced = false; unsigned int i; for (i = 0; i < w->data_deps.nr; i++) { @@ -2777,11 +1742,7 @@ static bool sync_deps(struct workload *wrk, struct w_step *w) igt_assert(wrk->steps[dep_idx].type == BATCH); gem_sync(fd, wrk->steps[dep_idx].obj[0].handle); - - synced = true; } - - return synced; } static void *run_workload(void *data) @@ -2789,7 +1750,6 @@ static void *run_workload(void *data) struct workload *wrk = (struct workload *)data; struct timespec t_start, t_end; struct w_step *w; - bool last_sync = false; int throttle = -1; int qd_throttle = -1; int count; @@ -2797,7 +1757,6 @@ static void *run_workload(void *data) clock_gettime(CLOCK_MONOTONIC, &t_start); - init_status_page(wrk, INIT_ALL); for (count = 0; wrk->run && (wrk->background || count < wrk->repeat); count++) { unsigned int cur_seqno = wrk->sync_seqno; @@ -2898,26 +1857,13 @@ static void *run_workload(void *data) igt_assert(w->type == BATCH); - if ((wrk->flags & DEPSYNC) && engine == VCS) - last_sync = sync_deps(wrk, w); - - if (last_sync && (wrk->flags & HEARTBEAT)) - init_status_page(wrk, 0); - - last_sync = false; - - wrk->nr_bb[engine]++; - if (engine == VCS && wrk->balancer && - wrk->balancer->balance) { - engine = wrk->balancer->balance(wrk->balancer, - wrk, w); - wrk->nr_bb[engine]++; - } + if (wrk->flags & DEPSYNC) + sync_deps(wrk, w); if (throttle > 0) w_sync_to(wrk, w, i - throttle); - do_eb(wrk, w, engine, wrk->flags); + do_eb(wrk, w, engine); if (w->request != -1) { igt_list_del(&w->rq_link); @@ -2930,10 +1876,8 @@ static void *run_workload(void *data) if (!wrk->run) break; - if (w->sync) { + if (w->sync) gem_sync(fd, w->obj[0].handle); - last_sync = true; - } if (qd_throttle > 0) { while (wrk->nrequest[engine] > qd_throttle) { @@ -2943,7 +1887,6 @@ static void *run_workload(void *data) s, rq_link); gem_sync(fd, s->obj[0].handle); - last_sync = true; s->request = -1; igt_list_del(&s->rq_link); @@ -2986,13 +1929,6 @@ static void *run_workload(void *data) printf("%c%u: %.3fs elapsed (%d cycles, %.3f workloads/s).", wrk->background ? ' ' : '*', wrk->id, t, count, count / t); - if (wrk->balancer) - printf(" %lu (%lu + %lu) total VCS batches.", - wrk->nr_bb[VCS], wrk->nr_bb[VCS1], wrk->nr_bb[VCS2]); - if (wrk->balancer && wrk->balancer->get_qd) - printf(" Average queue depths %.3f, %.3f.", - (double)wrk->qd_sum[VCS1] / wrk->nr_bb[VCS], - (double)wrk->qd_sum[VCS2] / wrk->nr_bb[VCS]); putchar('\n'); } @@ -3114,8 +2050,6 @@ calibrate_engines(void) static void print_help(void) { - unsigned int i; - puts( "Usage: gem_wsim [OPTIONS]\n" "\n" @@ -3145,32 +2079,11 @@ static void print_help(void) " -a <desc|path> Append a workload to all other workloads.\n" " -r <n> How many times to emit the workload.\n" " -c <n> Fork N clients emitting the workload simultaneously.\n" -" -x Swap VCS1 and VCS2 engines in every other client.\n" -" -b <n> Load balancing to use.\n" -" Available load balancers are:" - ); - - for (i = 0; i < ARRAY_SIZE(all_balancers); i++) { - igt_assert(all_balancers[i].desc); - printf( -" %s (%u): %s\n", - all_balancers[i].name, all_balancers[i].id, - all_balancers[i].desc); - } - puts( -" Balancers can be specified either as names or as their id\n" -" number as listed above.\n" -" -2 Remap VCS2 to BCS.\n" -" -R Round-robin initial VCS assignment per client.\n" -" -H Send heartbeat on synchronisation points with seqno based\n" -" balancers. Gives better engine busyness view in some cases.\n" -" -s Turn on small SSEU config for the next workload on the\n" -" command line. Subsequent -s switches it off.\n" -" -S Synchronize the sequence of random batch durations between\n" -" clients.\n" -" -G Global load balancing - a single load balancer will be shared\n" -" between all clients and there will be a single seqno domain.\n" -" -d Sync between data dependencies in userspace." +" -s Turn on small SSEU config for the next workload on the\n" +" command line. Subsequent -s switches it off.\n" +" -S Synchronize the sequence of random batch durations between\n" +" clients.\n" +" -d Sync between data dependencies in userspace." ); } @@ -3218,62 +2131,6 @@ add_workload_arg(struct w_arg *w_args, unsigned int nr_args, char *w_arg, return w_args; } -static int find_balancer_by_name(char *name) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(all_balancers); i++) { - if (!strcasecmp(name, all_balancers[i].name)) - return all_balancers[i].id; - } - - return -1; -} - -static const struct workload_balancer *find_balancer_by_id(unsigned int id) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(all_balancers); i++) { - if (id == all_balancers[i].id) - return &all_balancers[i]; - } - - return NULL; -} - -static void init_clocks(void) -{ - struct timespec t_start, t_end; - uint32_t rcs_start, rcs_end; - double overhead, t; - - if (verbose <= 1) - return; - - clock_gettime(CLOCK_MONOTONIC, &t_start); - for (int i = 0; i < 100; i++) - rcs_start = *REG(RCS_TIMESTAMP); - clock_gettime(CLOCK_MONOTONIC, &t_end); - overhead = 2 * elapsed(&t_start, &t_end) / 100; - - clock_gettime(CLOCK_MONOTONIC, &t_start); - for (int i = 0; i < 100; i++) - clock_gettime(CLOCK_MONOTONIC, &t_end); - clock_gettime(CLOCK_MONOTONIC, &t_end); - overhead += elapsed(&t_start, &t_end) / 100; - - clock_gettime(CLOCK_MONOTONIC, &t_start); - rcs_start = *REG(RCS_TIMESTAMP); - usleep(100); - rcs_end = *REG(RCS_TIMESTAMP); - clock_gettime(CLOCK_MONOTONIC, &t_end); - - t = elapsed(&t_start, &t_end) - overhead; - printf("%d cycles in %.1fus, i.e. 1024 cycles takes %1.fus\n", - rcs_end - rcs_start, 1e6*t, 1024e6 * t / (rcs_end - rcs_start)); -} - int main(int argc, char **argv) { unsigned int repeat = 1; @@ -3287,9 +2144,7 @@ int main(int argc, char **argv) char *append_workload_arg = NULL; struct w_arg *w_args = NULL; unsigned int tolerance_pct = 1; - const struct workload_balancer *balancer = NULL; int exitcode = EXIT_FAILURE; - char *endptr = NULL; int prio = 0; double t; int i, c; @@ -3304,17 +2159,13 @@ int main(int argc, char **argv) * This minimizes the gap in engine utilization tracking when observed * via external tools like trace.pl. */ - fd = __drm_open_driver(DRIVER_INTEL); + fd = __drm_open_driver_render(DRIVER_INTEL); igt_require(fd); - intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd); - - init_clocks(); - master_prng = time(NULL); while ((c = getopt(argc, argv, - "Thqv2RsSHxGdc:n:r:w:W:a:t:b:p:I:")) != -1) { + "ThqvsSdc:n:r:w:W:a:t:p:I:")) != -1) { switch (c) { case 'W': if (master_workload >= 0) { @@ -3413,52 +2264,15 @@ int main(int argc, char **argv) case 'v': verbose++; break; - case 'x': - flags |= SWAPVCS; - break; - case '2': - flags |= VCS2REMAP; - break; - case 'R': - flags |= INITVCSRR; - break; case 'S': flags |= SYNCEDCLIENTS; break; case 's': flags ^= SSEU; break; - case 'H': - flags |= HEARTBEAT; - break; - case 'G': - flags |= GLOBAL_BALANCE; - break; case 'd': flags |= DEPSYNC; break; - case 'b': - i = find_balancer_by_name(optarg); - if (i < 0) { - i = strtol(optarg, &endptr, 0); - if (endptr && *endptr) - i = -1; - } - - if (i >= 0) { - balancer = find_balancer_by_id(i); - if (balancer) { - igt_assert(intel_gen(intel_get_drm_devid(fd)) >= balancer->min_gen); - flags |= BALANCE | balancer->flags; - } - } - - if (!balancer) { - wsim_err("Unknown balancing mode '%s'!\n", - optarg); - goto err; - } - break; case 'I': master_prng = strtol(optarg, NULL, 0); break; @@ -3470,16 +2284,6 @@ int main(int argc, char **argv) } } - if ((flags & HEARTBEAT) && !(flags & SEQNO)) { - wsim_err("Heartbeat needs a seqno based balancer!\n"); - goto err; - } - - if ((flags & VCS2REMAP) && (flags & I915)) { - wsim_err("VCS remapping not supported with i915 balancing!\n"); - goto err; - } - if (!has_nop_calibration) { if (verbose > 1) { printf("Calibrating nop delays with %u%% tolerance...\n", @@ -3519,11 +2323,6 @@ int main(int argc, char **argv) goto err; } - if ((flags & GLOBAL_BALANCE) && !balancer) { - wsim_err("Balancer not specified in global balancing mode!\n"); - goto err; - } - if (append_workload_arg) { append_workload_arg = load_workload_descriptor(append_workload_arg); if (!append_workload_arg) { @@ -3566,19 +2365,6 @@ int main(int argc, char **argv) printf("Random seed is %u.\n", master_prng); print_engine_calibrations(); printf("%u client%s.\n", clients, clients > 1 ? "s" : ""); - if (flags & SWAPVCS) - printf("Swapping VCS rings between clients.\n"); - if (flags & GLOBAL_BALANCE) { - if (flags & I915) { - printf("Ignoring global balancing with i915!\n"); - flags &= ~GLOBAL_BALANCE; - } else { - printf("Using %s balancer in global mode.\n", - balancer->name); - } - } else if (balancer) { - printf("Using %s balancer.\n", balancer->name); - } } srand(master_prng); @@ -3591,41 +2377,18 @@ int main(int argc, char **argv) igt_assert(w); for (i = 0; i < clients; i++) { - unsigned int flags_ = flags; - w[i] = clone_workload(wrk[nr_w_args > 1 ? i : 0]); - if (flags & SWAPVCS && i & 1) - flags_ &= ~SWAPVCS; - - if ((flags & GLOBAL_BALANCE) && !(flags & I915)) { - w[i]->balancer = &global_balancer; - w[i]->global_wrk = w[0]; - w[i]->global_balancer = balancer; - } else { - w[i]->balancer = balancer; - } - w[i]->flags = flags; w[i]->repeat = repeat; w[i]->background = master_workload >= 0 && i != master_workload; w[i]->print_stats = verbose > 1 || (verbose > 0 && master_workload == i); - if (prepare_workload(i, w[i], flags_)) { + if (prepare_workload(i, w[i])) { wsim_err("Failed to prepare workload %u!\n", i); goto err; } - - - if (balancer && balancer->init) { - int ret = balancer->init(balancer, w[i]); - if (ret) { - wsim_err("Failed to initialize balancing! (%u=%d)\n", - i, ret); - goto err; - } - } } clock_gettime(CLOCK_MONOTONIC, &t_start); @@ -3670,6 +2433,5 @@ int main(int argc, char **argv) out: exitcode = EXIT_SUCCESS; err: - intel_register_access_fini(&mmio_data); return exitcode; } diff --git a/benchmarks/ilog2.h b/benchmarks/ilog2.h deleted file mode 100644 index 596d7c23e0d1..000000000000 --- a/benchmarks/ilog2.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef ILOG2_H -#define ILOG2_H - -#include <stdint.h> - -static inline int fls(int x) -{ - int r = -1; - asm("bsrl %1,%0" : "=r" (r) : "rm" (x), "0" (-1)); - return r + 1; -} - -static inline int fls64(__u64 x) -{ - int r = -1; - asm("bsrq %1,%q0" : "+r" (r) : "rm" (x)); - return r + 1; -} - -static inline __attribute__((const)) -int __ilog2_u32(uint32_t n) -{ - return fls(n) - 1; -} - -static inline __attribute__((const)) -int __ilog2_u64(uint64_t n) -{ - return fls64(n) - 1; -} - -#define ilog2(n) \ -( \ - __builtin_constant_p(n) ? ( \ - (n) < 2 ? 0 : \ - (n) & (1ULL << 63) ? 63 : \ - (n) & (1ULL << 62) ? 62 : \ - (n) & (1ULL << 61) ? 61 : \ - (n) & (1ULL << 60) ? 60 : \ - (n) & (1ULL << 59) ? 59 : \ - (n) & (1ULL << 58) ? 58 : \ - (n) & (1ULL << 57) ? 57 : \ - (n) & (1ULL << 56) ? 56 : \ - (n) & (1ULL << 55) ? 55 : \ - (n) & (1ULL << 54) ? 54 : \ - (n) & (1ULL << 53) ? 53 : \ - (n) & (1ULL << 52) ? 52 : \ - (n) & (1ULL << 51) ? 51 : \ - (n) & (1ULL << 50) ? 50 : \ - (n) & (1ULL << 49) ? 49 : \ - (n) & (1ULL << 48) ? 48 : \ - (n) & (1ULL << 47) ? 47 : \ - (n) & (1ULL << 46) ? 46 : \ - (n) & (1ULL << 45) ? 45 : \ - (n) & (1ULL << 44) ? 44 : \ - (n) & (1ULL << 43) ? 43 : \ - (n) & (1ULL << 42) ? 42 : \ - (n) & (1ULL << 41) ? 41 : \ - (n) & (1ULL << 40) ? 40 : \ - (n) & (1ULL << 39) ? 39 : \ - (n) & (1ULL << 38) ? 38 : \ - (n) & (1ULL << 37) ? 37 : \ - (n) & (1ULL << 36) ? 36 : \ - (n) & (1ULL << 35) ? 35 : \ - (n) & (1ULL << 34) ? 34 : \ - (n) & (1ULL << 33) ? 33 : \ - (n) & (1ULL << 32) ? 32 : \ - (n) & (1ULL << 31) ? 31 : \ - (n) & (1ULL << 30) ? 30 : \ - (n) & (1ULL << 29) ? 29 : \ - (n) & (1ULL << 28) ? 28 : \ - (n) & (1ULL << 27) ? 27 : \ - (n) & (1ULL << 26) ? 26 : \ - (n) & (1ULL << 25) ? 25 : \ - (n) & (1ULL << 24) ? 24 : \ - (n) & (1ULL << 23) ? 23 : \ - (n) & (1ULL << 22) ? 22 : \ - (n) & (1ULL << 21) ? 21 : \ - (n) & (1ULL << 20) ? 20 : \ - (n) & (1ULL << 19) ? 19 : \ - (n) & (1ULL << 18) ? 18 : \ - (n) & (1ULL << 17) ? 17 : \ - (n) & (1ULL << 16) ? 16 : \ - (n) & (1ULL << 15) ? 15 : \ - (n) & (1ULL << 14) ? 14 : \ - (n) & (1ULL << 13) ? 13 : \ - (n) & (1ULL << 12) ? 12 : \ - (n) & (1ULL << 11) ? 11 : \ - (n) & (1ULL << 10) ? 10 : \ - (n) & (1ULL << 9) ? 9 : \ - (n) & (1ULL << 8) ? 8 : \ - (n) & (1ULL << 7) ? 7 : \ - (n) & (1ULL << 6) ? 6 : \ - (n) & (1ULL << 5) ? 5 : \ - (n) & (1ULL << 4) ? 4 : \ - (n) & (1ULL << 3) ? 3 : \ - (n) & (1ULL << 2) ? 2 : \ - 1 ) : \ - (sizeof(n) <= 4) ? \ - __ilog2_u32(n) : \ - __ilog2_u64(n) \ - ) - -#endif /* ILOG2_H */ diff --git a/benchmarks/meson.build b/benchmarks/meson.build index ef93193b70dd..c70e1aac79c6 100644 --- a/benchmarks/meson.build +++ b/benchmarks/meson.build @@ -11,6 +11,7 @@ benchmark_progs = [ 'gem_prw', 'gem_set_domain', 'gem_syslatency', + 'gem_wsim', 'kms_vblank', 'prime_lookup', 'vgem_mmap', @@ -34,8 +35,3 @@ foreach prog : benchmark_progs install_dir : benchmarksdir, dependencies : igt_deps) endforeach - -executable('gem_wsim', 'gem_wsim.c', - install : true, - install_dir : benchmarksdir, - dependencies : igt_deps + [ lib_igt_perf ]) diff --git a/benchmarks/wsim/media-1080p-player.wsim b/benchmarks/wsim/media-1080p-player.wsim index bcbb0cfd2ad3..c87e1aee4f5d 100644 --- a/benchmarks/wsim/media-1080p-player.wsim +++ b/benchmarks/wsim/media-1080p-player.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.5000-10000.0.0 2.RCS.1000-2000.-1.0 P.3.1 diff --git a/benchmarks/wsim/media_1n2_480p.wsim b/benchmarks/wsim/media_1n2_480p.wsim index 11a4da6bfae8..3ce15ebc3d71 100644 --- a/benchmarks/wsim/media_1n2_480p.wsim +++ b/benchmarks/wsim/media_1n2_480p.wsim @@ -1,9 +1,15 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.1 +12.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n2_asy.wsim b/benchmarks/wsim/media_1n2_asy.wsim index 58c99ca1122c..f9943eb62e8a 100644 --- a/benchmarks/wsim/media_1n2_asy.wsim +++ b/benchmarks/wsim/media_1n2_asy.wsim @@ -1,9 +1,11 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.400-800.-5.0 5.RCS.500-700.-1.0 5.RCS.5000-6000.0.0 -5.VCS.1200-1500.-1.1 +12.VCS.1200-1500.-1.1 diff --git a/benchmarks/wsim/media_1n3_480p.wsim b/benchmarks/wsim/media_1n3_480p.wsim index c724ab28a1f4..4f585fa8a8e0 100644 --- a/benchmarks/wsim/media_1n3_480p.wsim +++ b/benchmarks/wsim/media_1n3_480p.wsim @@ -1,13 +1,21 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.0 +12.VCS.2500-3500.-1.0 6.RCS.1000-2200.-9.0 7.RCS.1000-1400.-1.0 7.RCS.10000-12000.0.0 -7.VCS.2500-3500.-1.1 +13.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n3_asy.wsim b/benchmarks/wsim/media_1n3_asy.wsim index c7588328e3f1..dce7789ec1d8 100644 --- a/benchmarks/wsim/media_1n3_asy.wsim +++ b/benchmarks/wsim/media_1n3_asy.wsim @@ -1,3 +1,11 @@ +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 diff --git a/benchmarks/wsim/media_1n4_480p.wsim b/benchmarks/wsim/media_1n4_480p.wsim index e67fefc3bf17..06fa9adef5eb 100644 --- a/benchmarks/wsim/media_1n4_480p.wsim +++ b/benchmarks/wsim/media_1n4_480p.wsim @@ -1,17 +1,27 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.0 +12.VCS.2500-3500.-1.0 6.RCS.1000-2200.-9.0 7.RCS.1000-1400.-1.0 7.RCS.10000-12000.0.0 -7.VCS.2500-3500.-1.0 +13.VCS.2500-3500.-1.0 8.RCS.1000-2200.-13.0 9.RCS.1000-1400.-1.0 9.RCS.10000-12000.0.0 -9.VCS.2500-3500.-1.1 +14.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n4_asy.wsim b/benchmarks/wsim/media_1n4_asy.wsim index ede4fd7a2205..6dc6b652e903 100644 --- a/benchmarks/wsim/media_1n4_asy.wsim +++ b/benchmarks/wsim/media_1n4_asy.wsim @@ -1,3 +1,13 @@ +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 diff --git a/benchmarks/wsim/media_1n5_480p.wsim b/benchmarks/wsim/media_1n5_480p.wsim index 9e43b9845430..3467a386887a 100644 --- a/benchmarks/wsim/media_1n5_480p.wsim +++ b/benchmarks/wsim/media_1n5_480p.wsim @@ -1,21 +1,33 @@ -1.VCS.12000-15000.0.0 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 +M.15.VCS +B.15 +10.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 3.RCS.10000-12000.0.0 -3.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-1.0 4.RCS.1000-2200.-5.0 5.RCS.1000-1400.-1.0 5.RCS.10000-12000.0.0 -5.VCS.2500-3500.-1.0 +12.VCS.2500-3500.-1.0 6.RCS.1000-2200.-9.0 7.RCS.1000-1400.-1.0 7.RCS.10000-12000.0.0 -7.VCS.2500-3500.-1.0 +13.VCS.2500-3500.-1.0 8.RCS.1000-2200.-13.0 9.RCS.1000-1400.-1.0 9.RCS.10000-12000.0.0 -9.VCS.2500-3500.-1.0 +14.VCS.2500-3500.-1.0 10.RCS.1000-2200.-17.0 11.RCS.1000-1400.-1.0 11.RCS.10000-12000.0.0 -11.VCS.2500-3500.-1.1 +15.VCS.2500-3500.-1.1 diff --git a/benchmarks/wsim/media_1n5_asy.wsim b/benchmarks/wsim/media_1n5_asy.wsim index 78bb4a86dbca..4b205457a8d4 100644 --- a/benchmarks/wsim/media_1n5_asy.wsim +++ b/benchmarks/wsim/media_1n5_asy.wsim @@ -1,3 +1,15 @@ +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 +M.13.VCS +B.13 +M.14.VCS +B.14 +M.15.VCS +B.15 1.VCS.12000-15000.0.0 2.RCS.2000-3000.-1.0 3.RCS.500-900.-1.0 diff --git a/benchmarks/wsim/media_load_balance_17i7.wsim b/benchmarks/wsim/media_load_balance_17i7.wsim index 0830a3231ea9..bcb1ab2f04fa 100644 --- a/benchmarks/wsim/media_load_balance_17i7.wsim +++ b/benchmarks/wsim/media_load_balance_17i7.wsim @@ -1,7 +1,9 @@ +M.1.VCS +B.1 1.VCS.2800-3200.0.1 -1.RCS.900-1100.-1.0 -1.RCS.3600-3800.0.0 -1.RCS.900-1100.-2.0 +2.RCS.900-1100.-1.0 +2.RCS.3600-3800.0.0 +2.RCS.900-1100.-2.0 1.VCS.2200-2400.-2.0 -1.RCS.4500-4900.-1.0 +2.RCS.4500-4900.-1.0 1.VCS.500-700.-1.1 diff --git a/benchmarks/wsim/media_load_balance_19.wsim b/benchmarks/wsim/media_load_balance_19.wsim index 03890776fda3..88cd34fb6898 100644 --- a/benchmarks/wsim/media_load_balance_19.wsim +++ b/benchmarks/wsim/media_load_balance_19.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 0.VECS.1400-1500.0.0 0.RCS.1000-1500.-1.0 s.-2 @@ -5,6 +7,6 @@ s.-2 1.VCS.1300-1400.0.1 0.VECS.1400-1500.0.0 0.RCS.100-300.-1.1 -1.RCS.1300-1500.0.0 +2.RCS.1300-1500.-3.0 1.VCS.100-300.-1.1 1.VCS.900-1400.0.1 diff --git a/benchmarks/wsim/media_load_balance_4k12u7.wsim b/benchmarks/wsim/media_load_balance_4k12u7.wsim index ff10425b6bec..a417bb18e121 100644 --- a/benchmarks/wsim/media_load_balance_4k12u7.wsim +++ b/benchmarks/wsim/media_load_balance_4k12u7.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.4000-6000.0.0 2.RCS.400-800.-1.0 3.RCS.1900-2200.-1.0 diff --git a/benchmarks/wsim/media_load_balance_fhd26u7.wsim b/benchmarks/wsim/media_load_balance_fhd26u7.wsim index 56114ddc48c2..4c8225e1fe13 100644 --- a/benchmarks/wsim/media_load_balance_fhd26u7.wsim +++ b/benchmarks/wsim/media_load_balance_fhd26u7.wsim @@ -1,25 +1,27 @@ +M.3.VCS +B.3 1.VCS1.1200-1800.0.0 1.VCS1.1900-2100.0.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.200-400.-1.0 2.RCS.1500-2000.0.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.200-400.-1.0 2.RCS.1500-2000.0.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 1.VCS1.1900-2100.-1.0 2.RCS.1500-2000.-1.0 2.RCS.1500-2000.0.0 -2.VCS.1400-1800.-1.1 +3.VCS.1400-1800.-1.1 diff --git a/benchmarks/wsim/media_load_balance_hd01.wsim b/benchmarks/wsim/media_load_balance_hd01.wsim index 862931521c90..8e7e9d90e435 100644 --- a/benchmarks/wsim/media_load_balance_hd01.wsim +++ b/benchmarks/wsim/media_load_balance_hd01.wsim @@ -1,23 +1,27 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.1400-1900.0.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 1.VCS.1400-1900.-4.0 -1.RCS.1200-1600.-1.0 -1.RCS.1000-1400.-1.0 -2.VCS.800-1000.-1.0 +2.RCS.1200-1600.-1.0 +2.RCS.1000-1400.-1.0 +3.VCS.800-1000.-1.0 s.-17 s.-14 s.-11 diff --git a/benchmarks/wsim/media_load_balance_hd06mp2.wsim b/benchmarks/wsim/media_load_balance_hd06mp2.wsim index 1e1fc003c755..cfe985019a7b 100644 --- a/benchmarks/wsim/media_load_balance_hd06mp2.wsim +++ b/benchmarks/wsim/media_load_balance_hd06mp2.wsim @@ -1,4 +1,8 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 1.VCS.900-1700.0.0 2.RCS.100-400.-1.0 3.RCS.800-900.-1.0 -3.VCS.100-200.-1.1 +4.VCS.100-200.-1.1 diff --git a/benchmarks/wsim/media_load_balance_hd12.wsim b/benchmarks/wsim/media_load_balance_hd12.wsim index 8f3b41ca5ab6..684e6b511762 100644 --- a/benchmarks/wsim/media_load_balance_hd12.wsim +++ b/benchmarks/wsim/media_load_balance_hd12.wsim @@ -1,4 +1,8 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 1.VCS.850-1300.0.0 2.RCS.50-250.-1.0 3.RCS.400-800.-1.0 -3.VCS.100-200.-1.1 +4.VCS.100-200.-1.1 diff --git a/benchmarks/wsim/media_load_balance_hd17i4.wsim b/benchmarks/wsim/media_load_balance_hd17i4.wsim index b6195b605bf7..1430f18df033 100644 --- a/benchmarks/wsim/media_load_balance_hd17i4.wsim +++ b/benchmarks/wsim/media_load_balance_hd17i4.wsim @@ -1,7 +1,11 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.900-1400.0.0 2.RCS.200-300.-1.0 2.RCS.1000-2000.0.0 2.RCS.1000-2000.0.0 -2.VCS.800-1000.-1.0 -1.RCS.2800-3100.-1.0 +3.VCS.800-1000.-1.0 +4.RCS.2800-3100.-1.0 1.VCS.800-1000.-1.1 diff --git a/benchmarks/wsim/media_mfe2_480p.wsim b/benchmarks/wsim/media_mfe2_480p.wsim index 18bc756f1b55..00ef5c3a7574 100644 --- a/benchmarks/wsim/media_mfe2_480p.wsim +++ b/benchmarks/wsim/media_mfe2_480p.wsim @@ -1,3 +1,11 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 +M.7.VCS +B.7 +M.8.VCS +B.8 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.800-1600.-1.0 @@ -5,5 +13,5 @@ 5.RCS.1000-2200.-1.0 6.RCS.800-1600.-1.0 6.RCS.10000-12000.-4.0 -6.VCS.2500-3500.-1.0 -3.VCS.2500-3500.-2.1 +7.VCS.2500-3500.-1.0 +8.VCS.2500-3500.-2.1 diff --git a/benchmarks/wsim/media_mfe3_480p.wsim b/benchmarks/wsim/media_mfe3_480p.wsim index e12a2e6ac29d..3ac4db0eb8ec 100644 --- a/benchmarks/wsim/media_mfe3_480p.wsim +++ b/benchmarks/wsim/media_mfe3_480p.wsim @@ -1,3 +1,15 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 +M.7.VCS +B.7 +M.10.VCS +B.10 +M.11.VCS +B.11 +M.12.VCS +B.12 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.800-1600.-1.0 @@ -8,6 +20,6 @@ 8.RCS.1000-2200.-1.0 9.RCS.800-1600.-1.0 9.RCS.10000-12000.-7/-4.0 -9.VCS.2500-3500.-1.0 -3.VCS.2500-3500.-2.0 -6.VCS.2500-3500.-3.1 +10.VCS.2500-3500.-1.0 +11.VCS.2500-3500.-2.0 +12.VCS.2500-3500.-3.1 diff --git a/benchmarks/wsim/media_mfe4_480p.wsim b/benchmarks/wsim/media_mfe4_480p.wsim index 75d4f67ea4fb..7f6831569908 100644 --- a/benchmarks/wsim/media_mfe4_480p.wsim +++ b/benchmarks/wsim/media_mfe4_480p.wsim @@ -1,3 +1,19 @@ +M.1.VCS +B.1 +M.4.VCS +B.4 +M.7.VCS +B.7 +M.10.VCS +B.10 +M.13.VCS +B.13 +M.14.VCS +B.14 +M.15.VCS +B.15 +M.16.VCS +B.16 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.800-1600.-1.0 @@ -11,7 +27,7 @@ 11.RCS.1000-2200.-1.0 12.RCS.800-1600.-1.0 12.RCS.10000-12000.-4/-7/-10.0 -12.VCS.2500-3500.-1.0 -3.VCS.2500-3500.-2.0 -6.VCS.2500-3500.-3.0 -9.VCS.2500-3500.-4.1 +13.VCS.2500-3500.-1.0 +14.VCS.2500-3500.-2.0 +15.VCS.2500-3500.-3.0 +16.VCS.2500-3500.-4.1 diff --git a/benchmarks/wsim/media_nn_1080p.wsim b/benchmarks/wsim/media_nn_1080p.wsim index f9a3ca1b9963..88c5c772202c 100644 --- a/benchmarks/wsim/media_nn_1080p.wsim +++ b/benchmarks/wsim/media_nn_1080p.wsim @@ -1,3 +1,7 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.13000-17000.0.0 2.RCS.2000-4000.-1.0 3.RCS.3000-5000.-1.0 diff --git a/benchmarks/wsim/media_nn_1080p_s1.wsim b/benchmarks/wsim/media_nn_1080p_s1.wsim index 4fa6ca653000..5b47d2a3c7ec 100644 --- a/benchmarks/wsim/media_nn_1080p_s1.wsim +++ b/benchmarks/wsim/media_nn_1080p_s1.wsim @@ -1,3 +1,5 @@ +M.4.VCS +B.4 f 1.VCS1.6500-8000.f-1.0 1.VCS2.6500-8000.f-2.0 @@ -5,4 +7,4 @@ a.-3 2.RCS.2000-4000.-2/-3.0 3.RCS.3000-5000.-1.0 3.RCS.23000-27000.0.0 -3.VCS.16000-20000.-1.1 +4.VCS.16000-20000.-1.1 diff --git a/benchmarks/wsim/media_nn_1080p_s2.wsim b/benchmarks/wsim/media_nn_1080p_s2.wsim index 68f0acdfb842..e3678b396b42 100644 --- a/benchmarks/wsim/media_nn_1080p_s2.wsim +++ b/benchmarks/wsim/media_nn_1080p_s2.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.13000-17000.0.0 2.RCS.2000-4000.-1.0 3.RCS.3000-5000.-1.0 diff --git a/benchmarks/wsim/media_nn_1080p_s3.wsim b/benchmarks/wsim/media_nn_1080p_s3.wsim index 12368da83dca..ee3b675de9e5 100644 --- a/benchmarks/wsim/media_nn_1080p_s3.wsim +++ b/benchmarks/wsim/media_nn_1080p_s3.wsim @@ -1,3 +1,5 @@ +M.1.VCS +B.1 1.VCS.13000-17000.0.0 2.RCS.2000-4000.-1.0 3.RCS.3000-5000.-1.0 diff --git a/benchmarks/wsim/media_nn_480p.wsim b/benchmarks/wsim/media_nn_480p.wsim index ab64a4569d71..73fc643dc9e5 100644 --- a/benchmarks/wsim/media_nn_480p.wsim +++ b/benchmarks/wsim/media_nn_480p.wsim @@ -1,3 +1,7 @@ +M.1.VCS +B.1 +M.3.VCS +B.3 1.VCS.12000-15000.0.0 2.RCS.1000-2200.-1.0 3.RCS.1000-1400.-1.0 diff --git a/benchmarks/wsim/vcs_balanced.wsim b/benchmarks/wsim/vcs_balanced.wsim index e8958b8f7f43..78d953fb7551 100644 --- a/benchmarks/wsim/vcs_balanced.wsim +++ b/benchmarks/wsim/vcs_balanced.wsim @@ -1,26 +1,28 @@ q.5 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 -0.VCS.500-2000.0.0 +M.1.VCS +B.1 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 +1.VCS.500-2000.0.0 diff --git a/scripts/Makefile.am b/scripts/Makefile.am index e26a39e2f072..641715294936 100644 --- a/scripts/Makefile.am +++ b/scripts/Makefile.am @@ -1,2 +1,2 @@ -dist_noinst_SCRIPTS = intel-gfx-trybot who.sh run-tests.sh trace.pl media-bench.pl +dist_noinst_SCRIPTS = intel-gfx-trybot who.sh run-tests.sh trace.pl noinst_PYTHON = throttle.py diff --git a/scripts/media-bench.pl b/scripts/media-bench.pl deleted file mode 100755 index 1cd8205ff07c..000000000000 --- a/scripts/media-bench.pl +++ /dev/null @@ -1,736 +0,0 @@ -#! /usr/bin/perl -# -# Copyright ? 2017 Intel Corporation -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice (including the next -# paragraph) shall be included in all copies or substantial portions of the -# Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -# IN THE SOFTWARE. -# - -use strict; -use warnings; -use 5.010; - -use Getopt::Std; - -chomp(my $igt_root = `pwd -P`); -my $wsim = "$igt_root/benchmarks/gem_wsim"; -my $wrk_root = "$igt_root/benchmarks/wsim"; -my $tracepl = "$igt_root/scripts/trace.pl"; -my $tolerance = 0.01; -my $client_target_s = 10; -my $idle_tolerance_pct = 2.0; -my $verbose = 0; -my $gt2 = 0; -my $show_cmds = 0; -my $realtime_target = 0; -my $wps_target = 0; -my $wps_target_param = 0; -my $multi_mode = 0; -my @multi_workloads; -my $w_direct; -my $balancer; -my $nop; -my %opts; - -my @balancers = ( 'rr', 'rand', 'qd', 'qdr', 'qdavg', 'rt', 'rtr', 'rtavg', - 'context', 'busy', 'busy-avg', 'i915' ); -my %bal_skip_H = ( 'rr' => 1, 'rand' => 1, 'context' => 1, , 'busy' => 1, - 'busy-avg' => 1, 'i915' => 1 ); -my %bal_skip_R = ( 'i915' => 1 ); -my %bal_skip_G = ( 'i915' => 1 ); - -my @workloads = ( - 'media_load_balance_17i7.wsim', - 'media_load_balance_19.wsim', - 'media_load_balance_4k12u7.wsim', - 'media_load_balance_fhd26u7.wsim', - 'media_load_balance_hd01.wsim', - 'media_load_balance_hd06mp2.wsim', - 'media_load_balance_hd12.wsim', - 'media_load_balance_hd17i4.wsim', - 'media_1n2_480p.wsim', - 'media_1n3_480p.wsim', - 'media_1n4_480p.wsim', - 'media_1n5_480p.wsim', - 'media_1n2_asy.wsim', - 'media_1n3_asy.wsim', - 'media_1n4_asy.wsim', - 'media_1n5_asy.wsim', - 'media_mfe2_480p.wsim', - 'media_mfe3_480p.wsim', - 'media_mfe4_480p.wsim', - 'media_nn_1080p.wsim', - 'media_nn_480p.wsim', - ); - -sub show_cmd -{ - my ($cmd) = @_; - - say "\n+++ $cmd" if $show_cmds; -} - -sub calibrate_nop -{ - my ($delay, $nop); - my $cmd = "$wsim"; - - show_cmd($cmd); - open WSIM, "$cmd |" or die; - while (<WSIM>) { - chomp; - if (/Nop calibration for (\d+)us delay is (\d+)./) { - $delay = $1; - $nop = $2; - } - - } - close WSIM; - - die unless $nop; - - return $nop -} - -sub can_balance_workload -{ - my ($wrk) = @_; - my $res = 0; - - open WRK, "$wrk_root/$wrk" or die; - while (<WRK>) { - chomp; - if (/\.VCS\./) { - $res = 1; - last; - } - } - close WRK; - - return $res; -} - -sub add_wps_arg -{ - my (@args) = @_; - my $period; - - return @args if $realtime_target <= 0; - - $period = int(1000000 / $realtime_target); - push @args, '-a'; - push @args, 'p.$period'; - - return @args; -} - -sub run_workload -{ - my (@args) = @_; - my ($time, $wps, $cmd); - my @ret; - - @args = add_wps_arg(@args); - push @args, '-2' if $gt2; - - unshift @args, $wsim; - $cmd = join ' ', @args; - show_cmd($cmd); - - open WSIM, "$cmd |" or die; - while (<WSIM>) { - chomp; - if (/^(\d+\.\d+)s elapsed \((\d+\.?\d+) workloads\/s\)$/) { - $time = $1; - $wps = $2; - } elsif (/(\d+)\: \d+\.\d+s elapsed \(\d+ cycles, (\d+\.?\d+) workloads\/s\)/) { - $ret[$1] = $2; - } - } - close WSIM; - - return ($time, $wps, \@ret); -} - -sub dump_cmd -{ - my ($cmd, $file) = @_; - - show_cmd("$cmd > $file"); - - open FOUT, '>', $file or die; - open TIN, "$cmd |" or die; - while (<TIN>) { - print FOUT $_; - } - close TIN; - close FOUT; -} - -sub trace_workload -{ - my ($wrk, $b, $r, $c) = @_; - my @args = ($tracepl, '--trace', $wsim, '-q', '-n', $nop, '-r', $r, '-c', $c); - my $min_batches = 16 + $r * $c / 2; - my @skip_engine; - my %engines; - my ($cmd, $file); - - push @args, '-2' if $gt2; - - unless ($b eq '<none>') { - push @args, '-R'; - push @args, split /\s+/, $b; - } - - if (defined $w_direct) { - push @args, split /\s+/, $wrk; - } else { - push @args, '-w'; - push @args, $wrk_root . '/' . $wrk; - } - - show_cmd(join ' ', @args); - if (-e 'perf.data') { - unlink 'perf.data' or die; - } - system(@args) == 0 or die; - - $cmd = "perf script | $tracepl"; - show_cmd($cmd); - open CMD, "$cmd |" or die; - while (<CMD>) { - chomp; - if (/Ring(\S+): (\d+) batches.*?(\d+\.?\d+)% idle,/) { - if ($2 >= $min_batches) { - $engines{$1} = $3; - } else { - push @skip_engine, $1; - } - } elsif (/GPU: (\d+\.?\d+)% idle/) { - $engines{'gpu'} = $1; - } - } - close CMD; - - $wrk =~ s/$wrk_root//g; - $wrk =~ s/\.wsim//g; - $wrk =~ s/-w/W/g; - $wrk =~ s/[ -]/_/g; - $wrk =~ s/\//-/g; - $b =~ s/[ <>]/_/g; - $file = "${wrk}_${b}_-r${r}_-c${c}"; - - dump_cmd('perf script', "${file}.trace"); - - $cmd = "perf script | $tracepl --html -x ctxsave -s -c "; - $cmd .= join ' ', map("-i $_", @skip_engine); - - dump_cmd($cmd, "${file}.html"); - - return \%engines; -} - -sub calibrate_workload -{ - my ($wrk) = @_; - my $tol = $tolerance; - my $loops = 0; - my $error; - my $r; - - $r = $realtime_target > 0 ? $realtime_target * $client_target_s : 23; - for (;;) { - my @args = ('-n', $nop, '-r', $r); - my ($time, $wps); - - if (defined $w_direct) { - push @args, split /\s+/, $wrk; - } else { - push @args, '-w'; - push @args, $wrk_root . '/' . $wrk; - } - - ($time, $wps) = run_workload(@args); - - $wps = $r / $time if $w_direct; - $error = abs($time - $client_target_s) / $client_target_s; - - last if $error <= $tol; - - $r = int($wps * $client_target_s); - $loops = $loops + 1; - if ($loops >= 3) { - $tol = $tol * (1.2 + ($tol)); - $loops = 0; - } - last if $tol > 0.2; - } - - return ($r, $error); -} - -sub find_saturation_point -{ - my ($wrk, $rr, $verbose, @args) = @_; - my ($last_wps, $c, $swps, $wwps); - my $target = $realtime_target > 0 ? $realtime_target : $wps_target; - my $r = $rr; - my $wcnt; - my $maxc; - my $max = 0; - - push @args, '-v' if $multi_mode and $w_direct; - - if (defined $w_direct) { - push @args, split /\s+/, $wrk; - $wcnt = () = $wrk =~ /-[wW]/gi; - - } else { - push @args, '-w'; - push @args, $wrk_root . '/' . $wrk; - $wcnt = 1; - } - - for ($c = 1; ; $c = $c + 1) { - my ($time, $wps); - my @args_ = (@args, ('-r', $r, '-c', $c)); - - ($time, $wps, $wwps) = run_workload(@args_); - - say " $c clients is $wps wps." if $verbose; - - if ($c > 1) { - my $delta; - - if ($target <= 0) { - if ($wps > $max) { - $max = $wps; - $maxc = $c; - } - $delta = ($wps - $last_wps) / $last_wps; - if ($delta > 0) { - last if $delta < $tolerance; - } else { - $delta = ($wps - $max) / $max; - last if abs($delta) >= $tolerance; - } - } else { - $delta = ($wps / $c - $target) / $target; - last if $delta < 0 and abs($delta) >= $tolerance; - } - $r = int($rr * ($client_target_s / $time)); - } elsif ($c == 1) { - $swps = $wps; - return ($c, $wps, $swps, $wwps) if $wcnt > 1 or - $multi_mode or - ($wps_target_param < 0 and - $wps_target == 0); - } - - $last_wps = $wps; - } - - if ($target <= 0) { - return ($maxc, $max, $swps, $wwps); - } else { - return ($c - 1, $last_wps, $swps, $wwps); - } -} - -getopts('hv2xmn:b:W:B:r:t:i:R:T:w:', \%opts); - -if (defined $opts{'h'}) { - print <<ENDHELP; -Supported options: - - -h Help text. - -v Be verbose. - -x Show external commands. - -2 Run gem_wsim in GT2 mode. - -n num Nop calibration. - -b str Balancer to pre-select. - Skips balancer auto-selection. - Passed straight the gem_wsim so use like -b "-b qd -R" - -W a,b,c Override the default list of workloads. - -B a,b,c Override the default list of balancers. - -r sec Target workload duration. - -t pct Calibration tolerance. - -i pct Engine idleness tolerance. - -R wps Run workloads in the real-time mode at wps rate. - -T wps Calibrate up to wps/client target instead of GPU saturation. - Negative values set the target based on the single client - performance where target = single-client-wps / -N. - -w str Pass-through to gem_wsim. Overrides normal workload selection. - -m Multi-workload mode. All selected workloads will be run in - parallel and overal score will be relative to when run - individually. -ENDHELP - exit 0; -} - -$verbose = 1 if defined $opts{'v'}; -$gt2 = 1 if defined $opts{'2'}; -$show_cmds = 1 if defined $opts{'x'}; -$multi_mode = 1 if defined $opts{'m'}; -if (defined $opts{'b'}) { - die unless substr($opts{'b'}, 0, 2) eq '-b'; - $balancer = $opts{'b'}; -} -if (defined $opts{'B'}) { - @balancers = split /,/, $opts{'B'}; -} else { - unshift @balancers, ''; -} - at workloads = split /,/, $opts{'W'} if defined $opts{'W'}; -$client_target_s = $opts{'r'} if defined $opts{'r'}; -$tolerance = $opts{'t'} / 100.0 if defined $opts{'t'}; -$idle_tolerance_pct = $opts{'i'} if defined $opts{'i'}; -$realtime_target = $opts{'R'} if defined $opts{'R'}; -$wps_target = $opts{'T'} if defined $opts{'T'}; -$wps_target_param = $wps_target; -$w_direct = $opts{'w'} if defined $opts{'w'}; - -if ($multi_mode) { - die if $w_direct; # Not supported - @multi_workloads = @workloads; -} - - at workloads = ($w_direct) if defined $w_direct; - -say "Workloads:"; -print map { " $_\n" } @workloads; -print "Balancers: "; -say map { "$_," } @balancers; -say "Target workload duration is ${client_target_s}s."; -say "Calibration tolerance is $tolerance."; -say "Real-time mode at ${realtime_target} wps." if $realtime_target > 0; -say "Wps target is ${wps_target} wps." if $wps_target > 0; -say "Multi-workload mode." if $multi_mode; -$nop = $opts{'n'}; -$nop = calibrate_nop() unless $nop; -say "Nop calibration is $nop."; - -goto VERIFY if defined $balancer; - -my (%best_bal, %best_bid); -my %results; -my %scores; -my %wscores; -my %cscores; -my %cwscores; -my %mscores; -my %mwscores; - -sub add_points -{ - my ($wps, $scores, $wscores) = @_; - my ($min, $max, $spread); - my @sorted; - - @sorted = sort { $b <=> $a } values %{$wps}; - $max = $sorted[0]; - $min = $sorted[-1]; - $spread = $max - $min; - die if $spread < 0; - - foreach my $w (keys %{$wps}) { - my ($score, $wscore); - - unless (exists $scores->{$w}) { - $scores->{$w} = 0; - $wscores->{$w} = 0; - } - - $score = $wps->{$w} / $max; - $scores->{$w} = $scores->{$w} + $score; - $wscore = $score * $spread / $max; - $wscores->{$w} = $wscores->{$w} + $wscore; - } -} - -my @saturation_workloads = $multi_mode ? @multi_workloads : @workloads; -my %allwps; -my $widx = 0; - -push @saturation_workloads, '-w ' . join ' -w ', map("$wrk_root/$_", @workloads) - if $multi_mode; - -foreach my $wrk (@saturation_workloads) { - my @args = ( "-n $nop"); - my ($r, $error, $should_b, $best); - my (%wps, %cwps, %mwps); - my @sorted; - my $range; - - $w_direct = $wrk if $multi_mode and $widx == $#saturation_workloads; - - $should_b = 1; - $should_b = can_balance_workload($wrk) unless defined $w_direct; - - print "\nEvaluating '$wrk'..."; - - ($r, $error) = calibrate_workload($wrk); - say " ${client_target_s}s is $r workloads. (error=$error)"; - - say " Finding saturation points for '$wrk'..."; - - BAL: foreach my $bal (@balancers) { - GBAL: foreach my $G ('', '-G', '-d', '-G -d') { - foreach my $H ('', '-H') { - my @xargs; - my ($w, $c, $s, $bwwps); - my $bid; - - if ($bal ne '') { - next GBAL if $G =~ '-G' and exists $bal_skip_G{$bal}; - - push @xargs, "-b $bal"; - push @xargs, '-R' unless exists $bal_skip_R{$bal}; - push @xargs, $G if $G ne ''; - push @xargs, $H if $H ne ''; - $bid = join ' ', @xargs; - print " $bal balancer ('$bid'): "; - } else { - $bid = '<none>'; - print " No balancing: "; - } - - $wps_target = 0 if $wps_target_param < 0; - - ($c, $w, $s, $bwwps) = - find_saturation_point($wrk, $r, 0, - (@args, @xargs)); - - if ($wps_target_param < 0) { - $wps_target = $s / -$wps_target_param; - - ($c, $w, $s, $bwwps) = - find_saturation_point($wrk, $r, - 0, - (@args, - @xargs)); - } - - if ($multi_mode and $w_direct) { - my $widx; - - die unless scalar(@multi_workloads) == - scalar(@{$bwwps}); - die unless scalar(@multi_workloads) == - scalar(keys %allwps); - - # Total of all workload wps from the - # mixed run. - $w = 0; - foreach $widx (0..$#{$bwwps}) { - $w += $bwwps->[$widx]; - } - - # Total of all workload wps from when - # ran individually with the best - # balancer. - my $tot = 0; - foreach my $wrk (@multi_workloads) { - $tot += $allwps{$wrk}->{$best_bid{$wrk}}; - } - - # Normalize mixed sum with sum of - # individual runs. - $w *= 100; - $w /= $tot; - - # Second metric is average of each - # workload wps normalized by their - # individual run performance with the - # best balancer. - $s = 0; - $widx = 0; - foreach my $wrk (@multi_workloads) { - $s += 100 * $bwwps->[$widx] / - $allwps{$wrk}->{$best_bid{$wrk}}; - $widx++; - } - $s /= scalar(@multi_workloads); - - say sprintf('Aggregate (normalized) %.2f%%; fairness %.2f%%', - $w, $s); - } else { - $allwps{$wrk} = \%wps; - } - - $wps{$bid} = $w; - $cwps{$bid} = $s; - - if ($realtime_target > 0 || $wps_target_param > 0) { - $mwps{$bid} = $w * $c; - } else { - $mwps{$bid} = $w + $s; - } - - say "$c clients ($w wps, $s wps single client, score=$mwps{$bid})." - unless $multi_mode and $w_direct; - - last BAL unless $should_b; - next BAL if $bal eq ''; - next GBAL if exists $bal_skip_H{$bal}; - } - } - } - - $widx++; - - @sorted = sort { $mwps{$b} <=> $mwps{$a} } keys %mwps; - $best_bid{$wrk} = $sorted[0]; - @sorted = sort { $b <=> $a } values %mwps; - $range = 1 - $sorted[-1] / $sorted[0]; - $best_bal{$wrk} = $sorted[0]; - - next if $multi_mode and not $w_direct; - - say " Best balancer is '$best_bid{$wrk}' (range=$range)."; - - - $results{$wrk} = \%mwps; - - add_points(\%wps, \%scores, \%wscores); - add_points(\%mwps, \%mscores, \%mwscores); - add_points(\%cwps, \%cscores, \%cwscores); -} - -sub dump_scoreboard -{ - my ($n, $h) = @_; - my ($i, $str, $balancer); - my ($max, $range); - my @sorted; - - @sorted = sort { $b <=> $a } values %{$h}; - $max = $sorted[0]; - $range = 1 - $sorted[-1] / $max; - $str = "$n rank (range=$range):"; - say "\n$str"; - say '=' x length($str); - $i = 1; - foreach my $w (sort { $h->{$b} <=> $h->{$a} } keys %{$h}) { - my $score; - - $balancer = $w if $i == 1; - $score = $h->{$w} / $max; - - say " $i: '$w' ($score)"; - - $i = $i + 1; - } - - return $balancer; -} - -dump_scoreboard($multi_mode ? 'Throughput' : 'Total wps', \%scores); -dump_scoreboard('Total weighted wps', \%wscores) unless $multi_mode; -dump_scoreboard($multi_mode ? 'Fairness' : 'Per client wps', \%cscores); -dump_scoreboard('Per client weighted wps', \%cwscores) unless $multi_mode; -$balancer = dump_scoreboard($multi_mode ? 'Combined' : 'Combined wps', \%mscores); -$balancer = dump_scoreboard('Combined weighted wps', \%mwscores) unless $multi_mode; - -VERIFY: - -my %problem_wrk; - -die unless defined $balancer; - -say "\nBalancer is '$balancer'."; -say "Idleness tolerance is $idle_tolerance_pct%."; - -if ($multi_mode) { - $w_direct = '-w ' . join ' -w ', map("$wrk_root/$_", @workloads); - @workloads = ($w_direct); -} - -foreach my $wrk (@workloads) { - my @args = ( "-n $nop" ); - my ($r, $error, $c, $wps, $swps); - my $saturated = 0; - my $result = 'Pass'; - my $vcs2 = $gt2 ? '1:0' : '2:1'; - my %problem; - my $engines; - - next if not defined $w_direct and not can_balance_workload($wrk); - - push @args, $balancer unless $balancer eq '<none>'; - - if (scalar(keys %results)) { - $r = $results{$wrk}->{$balancer} / $best_bal{$wrk} * 100.0; - } else { - $r = '---'; - } - say " \nProfiling '$wrk' ($r% of best)..."; - - ($r, $error) = calibrate_workload($wrk); - say " ${client_target_s}s is $r workloads. (error=$error)"; - - ($c, $wps, $swps) = find_saturation_point($wrk, $r, $verbose, @args); - say " Saturation at $c clients ($wps workloads/s)."; - push @args, "-c $c"; - - $engines = trace_workload($wrk, $balancer, $r, $c); - - foreach my $key (keys %{$engines}) { - next if $key eq 'gpu'; - $saturated = $saturated + 1 - if $engines->{$key} < $idle_tolerance_pct; - } - - if ($saturated == 0) { - # Not a single saturated engine - $result = 'FAIL'; - } elsif (not exists $engines->{'2:0'} or not exists $engines->{$vcs2}) { - # VCS1 and VCS2 not present in a balancing workload - $result = 'FAIL'; - } elsif ($saturated == 1 and - ($engines->{'2:0'} < $idle_tolerance_pct or - $engines->{$vcs2} < $idle_tolerance_pct)) { - # Only one VCS saturated - $result = 'WARN'; - } - - $result = 'WARN' if $engines->{'gpu'} > $idle_tolerance_pct; - - if ($result ne 'Pass') { - $problem{'c'} = $c; - $problem{'r'} = $r; - $problem{'stats'} = $engines; - $problem_wrk{$wrk} = \%problem; - } - - print " $result ["; - print map " $_: $engines->{$_}%,", sort keys %{$engines}; - say " ]"; -} - -say "\nProblematic workloads were:" if scalar(keys %problem_wrk) > 0; -foreach my $wrk (sort keys %problem_wrk) { - my $problem = $problem_wrk{$wrk}; - - print " $wrk -c $problem->{'c'} -r $problem->{'r'} ["; - print map " $_: $problem->{'stats'}->{$_}%,", - sort keys %{$problem->{'stats'}}; - say " ]"; -} -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:38 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:38 +0100 Subject: [Intel-gfx] [PATCH i-g-t 02/11] gem_wsim: Buffer objects working sets and complex dependencies In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-2-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Add support for defining buffer object working sets and targetting them as data dependencies. For more information please see the README file. v2: * More robustness in parsing here and there. (Chris) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 475 +++++++++++++++++++++--- benchmarks/wsim/README | 59 +++ benchmarks/wsim/cloud-gaming-60fps.wsim | 11 + benchmarks/wsim/composited-ui.wsim | 7 + 4 files changed, 498 insertions(+), 54 deletions(-) create mode 100644 benchmarks/wsim/cloud-gaming-60fps.wsim create mode 100644 benchmarks/wsim/composited-ui.wsim diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 5cc71c56fe6e..dc47470c621d 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -88,14 +88,21 @@ enum w_type LOAD_BALANCE, BOND, TERMINATE, - SSEU + SSEU, + WORKINGSET, +}; + +struct dep_entry { + int target; + bool write; + int working_set; /* -1 = step dependecy, >= 0 working set id */ }; struct deps { int nr; bool submit_fence; - int *list; + struct dep_entry *list; }; struct w_arg { @@ -110,6 +117,14 @@ struct bond { enum intel_engine_id master; }; +struct working_set { + int id; + bool shared; + unsigned int nr; + uint32_t *handles; + unsigned long *sizes; +}; + struct workload; struct w_step @@ -143,6 +158,7 @@ struct w_step enum intel_engine_id bond_master; }; int sseu; + struct working_set working_set; }; /* Implementation details */ @@ -193,6 +209,9 @@ struct workload unsigned int nr_ctxs; struct ctx *ctx_list; + struct working_set **working_sets; /* array indexed by set id */ + int max_working_set_id; + int sync_timeline; uint32_t sync_seqno; @@ -281,11 +300,129 @@ print_engine_calibrations(void) printf("\n"); } +static void add_dep(struct deps *deps, struct dep_entry entry) +{ + deps->list = realloc(deps->list, sizeof(*deps->list) * (deps->nr + 1)); + igt_assert(deps->list); + + deps->list[deps->nr++] = entry; +} + +static int +parse_working_set_deps(struct workload *wrk, + struct deps *deps, + struct dep_entry _entry, + char *str) +{ + /* + * 1 - target handle index in the specified working set. + * 2-4 - range + */ + struct dep_entry entry = _entry; + char *s; + + s = index(str, '-'); + if (s) { + int from, to; + + from = atoi(str); + if (from < 0) + return -1; + + to = atoi(++s); + if (to <= 0) + return -1; + + if (to <= from) + return -1; + + for (entry.target = from; entry.target <= to; entry.target++) + add_dep(deps, entry); + } else { + entry.target = atoi(str); + if (entry.target < 0) + return -1; + + add_dep(deps, entry); + } + + return 0; +} + +static int +parse_dependency(unsigned int nr_steps, struct w_step *w, char *str) +{ + struct dep_entry entry = { .working_set = -1 }; + bool submit_fence = false; + char *s; + + switch (str[0]) { + case '-': + if (str[1] < '0' || str[1] > '9') + return -1; + + entry.target = atoi(str); + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) + return -1; + + add_dep(&w->data_deps, entry); + + break; + case 's': + submit_fence = true; + /* Fall-through. */ + case 'f': + /* Multiple fences not yet supported. */ + igt_assert_eq(w->fence_deps.nr, 0); + + entry.target = atoi(++str); + if (entry.target > 0 || ((int)nr_steps + entry.target) < 0) + return -1; + + add_dep(&w->fence_deps, entry); + + w->fence_deps.submit_fence = submit_fence; + break; + case 'w': + entry.write = true; + /* Fall-through. */ + case 'r': + /* + * [rw]N-<str> + * r1-<str> or w2-<str>, where N is working set id. + */ + s = index(++str, '-'); + if (!s) + return -1; + + entry.working_set = atoi(str); + if (entry.working_set < 0) + return -1; + + if (parse_working_set_deps(w->wrk, &w->data_deps, entry, ++s)) + return -1; + + break; + default: + return -1; + }; + + return 0; +} + static int parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) { char *desc = strdup(_desc); char *token, *tctx = NULL, *tstart = desc; + int ret = 0; + + /* + * Skip when no dependencies to avoid having to detect + * non-sensical "0/0/..." below. + */ + if (!strcmp(_desc, "0")) + goto out; igt_assert(desc); igt_assert(!w->data_deps.nr && w->data_deps.nr == w->fence_deps.nr); @@ -293,47 +430,17 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) w->data_deps.list == w->fence_deps.list); while ((token = strtok_r(tstart, "/", &tctx)) != NULL) { - bool submit_fence = false; - char *str = token; - struct deps *deps; - int dep; - tstart = NULL; - if (str[0] == '-' || (str[0] >= '0' && str[0] <= '9')) { - deps = &w->data_deps; - } else { - if (str[0] == 's') - submit_fence = true; - else if (str[0] != 'f') - return -1; - - deps = &w->fence_deps; - str++; - } - - dep = atoi(str); - if (dep > 0 || ((int)nr_steps + dep) < 0) { - if (deps->list) - free(deps->list); - return -1; - } - - if (dep < 0) { - deps->nr++; - /* Multiple fences not yet supported. */ - igt_assert(deps->nr == 1 || deps != &w->fence_deps); - deps->list = realloc(deps->list, - sizeof(*deps->list) * deps->nr); - igt_assert(deps->list); - deps->list[deps->nr - 1] = dep; - deps->submit_fence = submit_fence; - } + ret = parse_dependency(nr_steps, w, token); + if (ret) + break; } +out: free(desc); - return 0; + return ret; } static void __attribute__((format(printf, 1, 2))) @@ -624,6 +731,101 @@ static int parse_engine_map(struct w_step *step, const char *_str) return 0; } +static unsigned long parse_size(char *str) +{ + const unsigned int len = strlen(str); + unsigned int mult = 1; + long val; + + /* "1234567890[gGmMkK]" */ + + if (len == 0) + return 0; + + switch (str[len - 1]) { + case 'g': + case 'G': + mult *= 1024; + /* Fall-throuogh. */ + case 'm': + case 'M': + mult *= 1024; + /* Fall-throuogh. */ + case 'k': + case 'K': + mult *= 1024; + + str[len - 1] = 0; + /* Fall-throuogh. */ + + case '0' ... '9': + break; + default: + return 0; /* Unrecognized non-digit. */ + } + + val = atol(str); + if (val <= 0) + return 0; + + return val * mult; +} + +static int add_buffers(struct working_set *set, char *str) +{ + /* + * 4096 + * 4k + * 4m + * 4g + * 10n4k - 10 4k batches + */ + unsigned long *sizes, size; + int add, i; + char *n; + + n = index(str, 'n'); + if (n) { + *n = 0; + add = atoi(str); + if (add <= 0) + return -1; + str = ++n; + } else { + add = 1; + } + + size = parse_size(str); + if (!size) + return -1; + + sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); + if (!sizes) + return -1; + + for (i = 0; i < add; i++) + sizes[set->nr + i] = size; + + set->nr += add; + set->sizes = sizes; + + return 0; +} + +static int parse_working_set(struct working_set *set, char *str) +{ + char *token, *tctx = NULL, *tstart = str; + + while ((token = strtok_r(tstart, "/", &tctx))) { + tstart = NULL; + + if (add_buffers(set, token)) + return -1; + } + + return 0; +} + static uint64_t engine_list_mask(const char *_str) { uint64_t mask = 0; @@ -644,6 +846,8 @@ static uint64_t engine_list_mask(const char *_str) return mask; } +static void allocate_working_set(struct working_set *set); + #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ if ((field = strtok_r(fstart, ".", &fctx))) { \ tmp = atoi(field); \ @@ -661,7 +865,7 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) char *desc = strdup(arg->desc); char *_token, *token, *tctx = NULL, *tstart = desc; char *field, *fctx = NULL, *fstart; - struct w_step step, *steps = NULL; + struct w_step step, *w, *steps = NULL; unsigned int valid; int i, j, tmp; @@ -851,6 +1055,28 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) step.type = BOND; goto add_step; + } else if (!strcmp(field, "w") || !strcmp(field, "W")) { + unsigned int nr = 0; + + step.working_set.shared = field[0] == 'W'; + + while ((field = strtok_r(fstart, ".", &fctx))) { + tmp = atoi(field); + if (nr == 0) { + step.working_set.id = tmp; + } else { + tmp = parse_working_set(&step.working_set, + field); + check_arg(tmp < 0, + "Invalid working set at step %u!\n", + nr_steps); + } + + nr++; + } + + step.type = WORKINGSET; + goto add_step; } if (!field) { @@ -975,6 +1201,8 @@ add_step: wrk->steps = steps; wrk->prio = arg->prio; wrk->sseu = arg->sseu; + wrk->max_working_set_id = -1; + wrk->working_sets = NULL; free(desc); @@ -984,7 +1212,7 @@ add_step: */ for (i = 0; i < nr_steps; i++) { for (j = 0; j < steps[i].fence_deps.nr; j++) { - tmp = steps[i].idx + steps[i].fence_deps.list[j]; + tmp = steps[i].idx + steps[i].fence_deps.list[j].target; check_arg(tmp < 0 || tmp >= i || (steps[tmp].type != BATCH && steps[tmp].type != SW_FENCE), @@ -1003,6 +1231,51 @@ add_step: } } + /* + * Check no duplicate working set ids. + */ + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + struct w_step *w2; + + if (w->type != WORKINGSET) + continue; + + for (j = 0, w2 = wrk->steps; j < wrk->nr_steps; w2++, j++) { + if (j == i) + continue; + if (w2->type != WORKINGSET) + continue; + + check_arg(w->working_set.id == w2->working_set.id, + "Duplicate working set id at %u!\n", j); + } + } + + /* + * Allocate shared working sets. + */ + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && w->working_set.shared) + allocate_working_set(&w->working_set); + } + + wrk->max_working_set_id = -1; + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && + w->working_set.shared && + w->working_set.id > wrk->max_working_set_id) + wrk->max_working_set_id = w->working_set.id; + } + + wrk->working_sets = calloc(wrk->max_working_set_id + 1, + sizeof(*wrk->working_sets)); + igt_assert(wrk->working_sets); + + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && w->working_set.shared) + wrk->working_sets[w->working_set.id] = &w->working_set; + } + return wrk; } @@ -1024,6 +1297,18 @@ clone_workload(struct workload *_wrk) memcpy(wrk->steps, _wrk->steps, sizeof(struct w_step) * wrk->nr_steps); + wrk->max_working_set_id = _wrk->max_working_set_id; + if (wrk->max_working_set_id >= 0) { + wrk->working_sets = calloc(wrk->max_working_set_id + 1, + sizeof(*wrk->working_sets)); + igt_assert(wrk->working_sets); + + memcpy(wrk->working_sets, + _wrk->working_sets, + (wrk->max_working_set_id + 1) * + sizeof(*wrk->working_sets)); + } + /* Check if we need a sw sync timeline. */ for (i = 0; i < wrk->nr_steps; i++) { if (wrk->steps[i].type == SW_FENCE) { @@ -1222,17 +1507,36 @@ alloc_step_batch(struct workload *wrk, struct w_step *w) igt_assert(j < nr_obj); for (i = 0; i < w->data_deps.nr; i++) { - igt_assert(w->data_deps.list[i] <= 0); - if (w->data_deps.list[i]) { - int dep_idx = w->idx + w->data_deps.list[i]; + struct dep_entry *entry = &w->data_deps.list[i]; + uint32_t dep_handle; + if (entry->working_set == -1) { + int dep_idx = w->idx + entry->target; + + igt_assert(entry->target <= 0); igt_assert(dep_idx >= 0 && dep_idx < w->idx); igt_assert(wrk->steps[dep_idx].type == BATCH); - w->obj[j].handle = wrk->steps[dep_idx].obj[0].handle; - j++; - igt_assert(j < nr_obj); + dep_handle = wrk->steps[dep_idx].obj[0].handle; + } else { + struct working_set *set; + + igt_assert(entry->working_set <= + wrk->max_working_set_id); + + set = wrk->working_sets[entry->working_set]; + + igt_assert(set->nr); + igt_assert(entry->target < set->nr); + igt_assert(set->sizes[entry->target]); + + dep_handle = set->handles[entry->target]; } + + w->obj[j].flags = entry->write ? EXEC_OBJECT_WRITE : 0; + w->obj[j].handle = dep_handle; + j++; + igt_assert(j < nr_obj); } if (w->unbound_duration) @@ -1391,10 +1695,22 @@ static size_t sizeof_engines_bond(int count) engines[count]); } +static void allocate_working_set(struct working_set *set) +{ + unsigned int i; + + set->handles = calloc(set->nr, sizeof(*set->handles)); + igt_assert(set->handles); + + for (i = 0; i < set->nr; i++) + set->handles[i] = gem_create(fd, set->sizes[i]); +} + #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) static int prepare_workload(unsigned int id, struct workload *wrk) { + struct working_set **sets; uint32_t share_vm = 0; int max_ctx = -1; struct w_step *w; @@ -1629,6 +1945,51 @@ static int prepare_workload(unsigned int id, struct workload *wrk) } } + /* + * Allocate working sets. + */ + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && !w->working_set.shared) + allocate_working_set(&w->working_set); + } + + /* + * Map of working set ids. + */ + wrk->max_working_set_id = -1; + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type == WORKINGSET && + w->working_set.id > wrk->max_working_set_id) + wrk->max_working_set_id = w->working_set.id; + } + + sets = wrk->working_sets; + wrk->working_sets = calloc(wrk->max_working_set_id + 1, + sizeof(*wrk->working_sets)); + igt_assert(wrk->working_sets); + + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + struct working_set *set; + + if (w->type != WORKINGSET) + continue; + + if (!w->working_set.shared) { + set = &w->working_set; + } else { + igt_assert(sets); + + set = sets[w->working_set.id]; + igt_assert(set->shared); + igt_assert(set->sizes); + } + + wrk->working_sets[w->working_set.id] = set; + } + + if (sets) + free(sets); + /* * Allocate batch buffers. */ @@ -1698,7 +2059,7 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine) 2 * sizeof(uint32_t)); for (i = 0; i < w->fence_deps.nr; i++) { - int tgt = w->idx + w->fence_deps.list[i]; + int tgt = w->idx + w->fence_deps.list[i].target; /* TODO: fence merging needed to support multiple inputs */ igt_assert(i == 0); @@ -1729,14 +2090,18 @@ static void sync_deps(struct workload *wrk, struct w_step *w) unsigned int i; for (i = 0; i < w->data_deps.nr; i++) { + struct dep_entry *entry = &w->data_deps.list[i]; int dep_idx; - igt_assert(w->data_deps.list[i] <= 0); + if (entry->working_set == -1) + continue; + + igt_assert(entry->target <= 0); - if (!w->data_deps.list[i]) + if (!entry->target) continue; - dep_idx = w->idx + w->data_deps.list[i]; + dep_idx = w->idx + entry->target; igt_assert(dep_idx >= 0 && dep_idx < w->idx); igt_assert(wrk->steps[dep_idx].type == BATCH); @@ -1836,11 +2201,6 @@ static void *run_workload(void *data) MI_BATCH_BUFFER_END; __sync_synchronize(); continue; - } else if (w->type == PREEMPTION || - w->type == ENGINE_MAP || - w->type == LOAD_BALANCE || - w->type == BOND) { - continue; } else if (w->type == SSEU) { if (w->sseu != wrk->ctx_list[w->context * 2].sseu) { wrk->ctx_list[w->context * 2].sseu = @@ -1848,6 +2208,13 @@ static void *run_workload(void *data) w->sseu); } continue; + } else if (w->type == PREEMPTION || + w->type == ENGINE_MAP || + w->type == LOAD_BALANCE || + w->type == BOND || + w->type == WORKINGSET) { + /* No action for these at execution time. */ + continue; } if (do_sleep || w->type == PERIOD) { diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 9f770217f075..3d9143226740 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -8,6 +8,7 @@ M.<uint>.<str>[|<str>]... P|S|X.<uint>.<int> d|p|s|t|q|a|T.<int>,... b.<uint>.<str>[|<str>].<str> +w|W.<uint>.<str>[/<str>]... f For duration a range can be given from which a random value will be picked @@ -32,6 +33,8 @@ Additional workload steps are also supported: 'P' - Context priority. 'S' - Context SSEU configuration. 'T' - Terminate an infinite batch. + 'w' - Working set. (See Working sets section.) + 'W' - Shared working set. 'X' - Context preemption control. Engine ids: DEFAULT, RCS, BCS, VCS, VCS1, VCS2, VECS @@ -275,3 +278,59 @@ for the render engine. Slice mask of -1 has a special meaning of "all slices". Otherwise any integer can be specifying as the slice mask, but beware any apart from 1 and -1 can make the workload not portable between different GPUs. + +Working sets +------------ + +When used plainly workload steps can create implicit data dependencies by +relatively referencing another workload steps of a batch buffer type. Fourth +field contains the relative data dependncy. For example: + + 1.RCS.1000.0.0 + 1.BCS.1000.-1.0 + +This means the second batch buffer will be marked as having a read data +dependency on the first one. (The shared buffer is always marked as written to +by the dependency target buffer.) This will cause a serialization between the +two batch buffers. + +Working sets are used where more complex data dependencies are required. Each +working set has an id, a list of buffers, and can either be local to the +workload or shared within the cloned workloads (-c command line option). + +Lower-case 'w' command defines a local working set while upper-case 'W' defines +a shared version. Syntax is as follows: + + w.<id>.<size>[/<size>]... + +For size a byte size can be given, or suffix 'k', 'm' or 'g' can be used (case +insensitive). Prefix in the format of "<int>n<size>" can also be given to create +multiple objects of the same size. + +Examples: + + w.1.4k - Working set 1 with a single 4KiB object in it. + W.2.2M/32768 - Working set 2 with one 2MiB and one 32768 byte object. + w.3.10n4k/2n20000 - Working set 3 with ten 4KiB and two 20000 byte objects. + +Working set objects can be referenced as data dependency targets using the new +'r'/'w' syntax. Simple example: + + w.1.4k + W.2.1m + 1.RCS.1000.r1-0/w2-0.0 + 1.BCS.1000.r2-0.0 + +In this example the RCS batch is reading from working set 1 object 0 and writing +to working set 2 object 0. BCS batch is reading from working set 2 object 0. + +Because working set 2 is of a shared type, should two instances of the same +workload be executed (-c 2) then the 1MiB buffer would be shared and written +and read by both clients creating a serialization point. + +Apart from single objects, ranges can also be given as depenencies: + + w.1.10n4k + 1.RCS.1000.r1-0-9.0 + +Here the RCS batch has a read dependency on working set 1 objects 0 to 9. diff --git a/benchmarks/wsim/cloud-gaming-60fps.wsim b/benchmarks/wsim/cloud-gaming-60fps.wsim new file mode 100644 index 000000000000..9e48bbc2f617 --- /dev/null +++ b/benchmarks/wsim/cloud-gaming-60fps.wsim @@ -0,0 +1,11 @@ +w.1.10n8m +w.2.3n16m +1.RCS.500-1500.r1-0-4/w2-0.0 +1.RCS.500-1500.r1-5-9/w2-1.0 +1.RCS.500-1500.r2-0-1/w2-2.0 +M.2.VCS +B.2 +3.RCS.500-1500.r2-2.0 +2.DEFAULT.2000-4000.-1.0 +4.VCS1.250-750.-1.1 +p.16667 diff --git a/benchmarks/wsim/composited-ui.wsim b/benchmarks/wsim/composited-ui.wsim new file mode 100644 index 000000000000..4164f8bf7393 --- /dev/null +++ b/benchmarks/wsim/composited-ui.wsim @@ -0,0 +1,7 @@ +w.1.10n8m/3n16m +W.2.16m +1.RCS.200-600.r1-0-4/w1-10.0 +1.RCS.200-600.r1-5-9/w1-11.0 +1.RCS.400-800.r1-10-11/w1-12.0 +3.BCS.200-800.r1-12/w2-0.1 +p.16667 -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:39 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:39 +0100 Subject: [Intel-gfx] [PATCH i-g-t 03/11] gem_wsim: Show workload timing stats In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-3-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Show average/min/max workload iteration and dropped period stats when 'p' command is used. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index dc47470c621d..dd0b2e260a5a 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -2117,7 +2117,8 @@ static void *run_workload(void *data) struct w_step *w; int throttle = -1; int qd_throttle = -1; - int count; + int count, missed = 0; + unsigned long time_tot = 0, time_min = ULONG_MAX, time_max = 0; int i; clock_gettime(CLOCK_MONOTONIC, &t_start); @@ -2137,12 +2138,19 @@ static void *run_workload(void *data) do_sleep = w->delay; } else if (w->type == PERIOD) { struct timespec now; + int elapsed; clock_gettime(CLOCK_MONOTONIC, &now); - do_sleep = w->period - - elapsed_us(&wrk->repeat_start, &now); + elapsed = elapsed_us(&wrk->repeat_start, &now); + do_sleep = w->period - elapsed; + time_tot += elapsed; + if (elapsed < time_min) + time_min = elapsed; + if (elapsed > time_max) + time_max = elapsed; if (do_sleep < 0) { - if (verbose > 1) + missed++; + if (verbose > 2) printf("%u: Dropped period @ %u/%u (%dus late)!\n", wrk->id, count, i, do_sleep); continue; @@ -2296,6 +2304,9 @@ static void *run_workload(void *data) printf("%c%u: %.3fs elapsed (%d cycles, %.3f workloads/s).", wrk->background ? ' ' : '*', wrk->id, t, count, count / t); + if (time_tot) + printf(" Time avg/min/max=%lu/%lu/%luus; %u missed.", + time_tot / count, time_min, time_max, missed); putchar('\n'); } -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:40 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:40 +0100 Subject: [Intel-gfx] [PATCH i-g-t 04/11] gem_wsim: Move BO allocation to a helper In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-4-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index dd0b2e260a5a..23b81d181df3 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -1490,6 +1490,11 @@ get_ctxid(struct workload *wrk, struct w_step *w) return wrk->ctx_list[w->context].id; } +static uint32_t alloc_bo(int i915, unsigned long size) +{ + return gem_create(i915, size); +} + static void alloc_step_batch(struct workload *wrk, struct w_step *w) { @@ -1501,7 +1506,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w) w->obj = calloc(nr_obj, sizeof(*w->obj)); igt_assert(w->obj); - w->obj[j].handle = gem_create(fd, 4096); + w->obj[j].handle = alloc_bo(fd, 4096); w->obj[j].flags = EXEC_OBJECT_WRITE; j++; igt_assert(j < nr_obj); @@ -1546,7 +1551,8 @@ alloc_step_batch(struct workload *wrk, struct w_step *w) else w->bb_sz = get_bb_sz(w, w->duration.max); - w->bb_handle = w->obj[j].handle = gem_create(fd, w->bb_sz + (w->unbound_duration ? 4096 : 0)); + w->bb_handle = w->obj[j].handle = + alloc_bo(fd, w->bb_sz + (w->unbound_duration ? 4096 : 0)); init_bb(w); w->obj[j].relocation_count = terminate_bb(w); @@ -1703,7 +1709,7 @@ static void allocate_working_set(struct working_set *set) igt_assert(set->handles); for (i = 0; i < set->nr; i++) - set->handles[i] = gem_create(fd, set->sizes[i]); + set->handles[i] = alloc_bo(fd, set->sizes[i]); } #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) @@ -2339,7 +2345,7 @@ static unsigned long calibrate_nop(unsigned int tolerance_pct, struct intel_exec do { struct timespec t_start; - obj.handle = gem_create(fd, size); + obj.handle = alloc_bo(fd, size); gem_write(fd, obj.handle, size - sizeof(bbe), &bbe, sizeof(bbe)); gem_execbuf(fd, &eb); -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:42 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:42 +0100 Subject: [Intel-gfx] [PATCH i-g-t 06/11] gem_wsim: Support scaling workload batch durations In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-6-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> -f <float> on the command line can be used to scale batch buffer durations in all parsed workloads. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index a387e180c242..2d6d0a6a7b4b 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -41,6 +41,7 @@ #include <assert.h> #include <limits.h> #include <pthread.h> +#include <math.h> #include "intel_chipset.h" #include "intel_reg.h" @@ -875,6 +876,11 @@ static uint64_t engine_list_mask(const char *_str) static void allocate_working_set(struct workload *wrk, struct working_set *set); +static long __duration(long dur, double scale) +{ + return round(scale * dur); +} + #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ if ((field = strtok_r(fstart, ".", &fctx))) { \ tmp = atoi(field); \ @@ -885,7 +891,8 @@ static void allocate_working_set(struct workload *wrk, struct working_set *set); } \ static struct workload * -parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) +parse_workload(struct w_arg *arg, unsigned int flags, double scale_dur, + double scale_time, struct workload *app_w) { struct workload *wrk; unsigned int nr_steps = 0; @@ -1151,7 +1158,7 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) tmpl == LONG_MAX, "Invalid duration at step %u!\n", nr_steps); - step.duration.min = tmpl; + step.duration.min = __duration(tmpl, scale_dur); if (sep && *sep == '-') { tmpl = strtol(sep + 1, NULL, 10); @@ -1161,7 +1168,8 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) tmpl == LONG_MAX, "Invalid duration range at step %u!\n", nr_steps); - step.duration.max = tmpl; + step.duration.max = __duration(tmpl, + scale_dur); } else { step.duration.max = step.duration.min; } @@ -1197,6 +1205,9 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) step.type = BATCH; add_step: + if (step.type == DELAY) + step.delay = __duration(step.delay, scale_time); + step.idx = nr_steps++; step.request = -1; steps = realloc(steps, sizeof(step) * nr_steps); @@ -2508,7 +2519,9 @@ static void print_help(void) " command line. Subsequent -s switches it off.\n" " -S Synchronize the sequence of random batch durations between\n" " clients.\n" -" -d Sync between data dependencies in userspace." +" -d Sync between data dependencies in userspace.\n" +" -f <scale> Scale factor for batch durations.\n" +" -F <scale> Scale factor for delays." ); } @@ -2570,6 +2583,8 @@ int main(int argc, char **argv) struct w_arg *w_args = NULL; unsigned int tolerance_pct = 1; int exitcode = EXIT_FAILURE; + double scale_time = 1.0f; + double scale_dur = 1.0f; int prio = 0; double t; int i, c; @@ -2590,7 +2605,7 @@ int main(int argc, char **argv) master_prng = time(NULL); while ((c = getopt(argc, argv, - "ThqvsSdc:n:r:w:W:a:t:p:I:")) != -1) { + "ThqvsSdc:n:r:w:W:a:t:p:I:f:F:")) != -1) { switch (c) { case 'W': if (master_workload >= 0) { @@ -2701,6 +2716,12 @@ int main(int argc, char **argv) case 'I': master_prng = strtol(optarg, NULL, 0); break; + case 'f': + scale_dur = atof(optarg); + break; + case 'F': + scale_time = atof(optarg); + break; case 'h': print_help(); goto out; @@ -2758,7 +2779,8 @@ int main(int argc, char **argv) if (append_workload_arg) { struct w_arg arg = { NULL, append_workload_arg, 0 }; - app_w = parse_workload(&arg, flags, NULL); + app_w = parse_workload(&arg, flags, scale_dur, scale_time, + NULL); if (!app_w) { wsim_err("Failed to parse append workload!\n"); goto err; @@ -2776,7 +2798,8 @@ int main(int argc, char **argv) goto err; } - wrk[i] = parse_workload(&w_args[i], flags, app_w); + wrk[i] = parse_workload(&w_args[i], flags, scale_dur, + scale_time, app_w); if (!wrk[i]) { wsim_err("Failed to parse workload %u!\n", i); goto err; -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:43 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:43 +0100 Subject: [Intel-gfx] [PATCH i-g-t 07/11] gem_wsim: Log max and active working set sizes in verbose mode In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-7-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> It is useful to know how much memory workload is allocating. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> --- benchmarks/gem_wsim.c | 100 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 95 insertions(+), 5 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 2d6d0a6a7b4b..8788f752121b 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -874,7 +874,8 @@ static uint64_t engine_list_mask(const char *_str) return mask; } -static void allocate_working_set(struct workload *wrk, struct working_set *set); +static unsigned long +allocate_working_set(struct workload *wrk, struct working_set *set); static long __duration(long dur, double scale) { @@ -1294,8 +1295,14 @@ add_step: * Allocate shared working sets. */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { - if (w->type == WORKINGSET && w->working_set.shared) - allocate_working_set(wrk, &w->working_set); + if (w->type == WORKINGSET && w->working_set.shared) { + unsigned long total = + allocate_working_set(wrk, &w->working_set); + + if (verbose > 1) + printf("%u: %lu bytes in shared working set %u\n", + wrk->id, total, w->working_set.id); + } } wrk->max_working_set_id = -1; @@ -1750,8 +1757,10 @@ get_buffer_size(struct workload *wrk, const struct work_buffer_size *sz) (sz->max + 1 - sz->min); } -static void allocate_working_set(struct workload *wrk, struct working_set *set) +static unsigned long +allocate_working_set(struct workload *wrk, struct working_set *set) { + unsigned long total = 0; unsigned int i; set->handles = calloc(set->nr, sizeof(*set->handles)); @@ -1760,7 +1769,82 @@ static void allocate_working_set(struct workload *wrk, struct working_set *set) for (i = 0; i < set->nr; i++) { set->sizes[i].size = get_buffer_size(wrk, &set->sizes[i]); set->handles[i] = alloc_bo(fd, set->sizes[i].size); + total += set->sizes[i].size; + } + + return total; +} + +static bool +find_dep(struct dep_entry *deps, unsigned int nr, struct dep_entry dep) +{ + unsigned int i; + + for (i = 0; i < nr; i++) { + if (deps[i].working_set == dep.working_set && + deps[i].target == dep.target) + return true; } + + return false; +} + +static void measure_active_set(struct workload *wrk) +{ + unsigned long total = 0, batch_sizes = 0; + struct dep_entry *deps = NULL; + unsigned int nr = 0, i, j; + struct w_step *w; + + if (verbose < 3) + return; + + for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { + if (w->type != BATCH) + continue; + + batch_sizes += w->bb_sz; + + for (j = 0; j < w->data_deps.nr; j++) { + struct dep_entry *dep = &w->data_deps.list[j]; + struct dep_entry _dep = *dep; + + if (dep->working_set == -1 && dep->target < 0) { + int idx = w->idx + dep->target; + + igt_assert(idx >= 0 && idx < w->idx); + igt_assert(wrk->steps[idx].type == BATCH); + + _dep.target = wrk->steps[idx].obj[0].handle; + } + + if (!find_dep(deps, nr, _dep)) { + if (dep->working_set == -1) { + total += 4096; + } else { + struct working_set *set; + + igt_assert(dep->working_set <= + wrk->max_working_set_id); + + set = wrk->working_sets[dep->working_set]; + igt_assert(set->nr); + igt_assert(dep->target < set->nr); + igt_assert(set->sizes[dep->target].size); + + total += set->sizes[dep->target].size; + } + + deps = realloc(deps, (nr + 1) * sizeof(*deps)); + deps[nr++] = *dep; + } + } + } + + free(deps); + + printf("%u: %lu bytes active working set in %u buffers. %lu in batch buffers.\n", + wrk->id, total, nr, batch_sizes); } #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) @@ -1768,6 +1852,7 @@ static void allocate_working_set(struct workload *wrk, struct working_set *set) static int prepare_workload(unsigned int id, struct workload *wrk) { struct working_set **sets; + unsigned long total = 0; uint32_t share_vm = 0; int max_ctx = -1; struct w_step *w; @@ -2008,9 +2093,12 @@ static int prepare_workload(unsigned int id, struct workload *wrk) */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == WORKINGSET && !w->working_set.shared) - allocate_working_set(wrk, &w->working_set); + total += allocate_working_set(wrk, &w->working_set); } + if (verbose > 2) + printf("%u: %lu bytes in working sets.\n", wrk->id, total); + /* * Map of working set ids. */ @@ -2058,6 +2146,8 @@ static int prepare_workload(unsigned int id, struct workload *wrk) alloc_step_batch(wrk, w); } + measure_active_set(wrk); + return 0; } -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:41 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:41 +0100 Subject: [Intel-gfx] [PATCH i-g-t 05/11] gem_wsim: Support random buffer sizes In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-5-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> See README for more details. v2: * No need to mess with flags. (Chris) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 69 +++++++++++++++++++++++++++++++++--------- benchmarks/wsim/README | 4 +++ 2 files changed, 59 insertions(+), 14 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 23b81d181df3..a387e180c242 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -117,12 +117,18 @@ struct bond { enum intel_engine_id master; }; +struct work_buffer_size { + unsigned long size; + unsigned long min; + unsigned long max; +}; + struct working_set { int id; bool shared; unsigned int nr; uint32_t *handles; - unsigned long *sizes; + struct work_buffer_size *sizes; }; struct workload; @@ -203,6 +209,7 @@ struct workload bool print_stats; uint32_t bb_prng; + uint32_t bo_prng; struct timespec repeat_start; @@ -779,10 +786,12 @@ static int add_buffers(struct working_set *set, char *str) * 4m * 4g * 10n4k - 10 4k batches + * 4096-16k - random size in range */ - unsigned long *sizes, size; + struct work_buffer_size *sizes; + unsigned long min_sz, max_sz; + char *n, *max = NULL; int add, i; - char *n; n = index(str, 'n'); if (n) { @@ -795,16 +804,34 @@ static int add_buffers(struct working_set *set, char *str) add = 1; } - size = parse_size(str); - if (!size) + n = index(str, '-'); + if (n) { + *n = 0; + max = ++n; + } + + min_sz = parse_size(str); + if (!min_sz) return -1; + if (max) { + max_sz = parse_size(max); + if (!max_sz) + return -1; + } else { + max_sz = min_sz; + } + sizes = realloc(set->sizes, (set->nr + add) * sizeof(*sizes)); if (!sizes) return -1; - for (i = 0; i < add; i++) - sizes[set->nr + i] = size; + for (i = 0; i < add; i++) { + struct work_buffer_size *sz = &sizes[set->nr + i]; + sz->min = min_sz; + sz->max = max_sz; + sz->size = 0; + } set->nr += add; set->sizes = sizes; @@ -846,7 +873,7 @@ static uint64_t engine_list_mask(const char *_str) return mask; } -static void allocate_working_set(struct working_set *set); +static void allocate_working_set(struct workload *wrk, struct working_set *set); #define int_field(_STEP_, _FIELD_, _COND_, _ERR_) \ if ((field = strtok_r(fstart, ".", &fctx))) { \ @@ -1203,6 +1230,7 @@ add_step: wrk->sseu = arg->sseu; wrk->max_working_set_id = -1; wrk->working_sets = NULL; + wrk->bo_prng = (flags & SYNCEDCLIENTS) ? master_prng : rand(); free(desc); @@ -1256,7 +1284,7 @@ add_step: */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == WORKINGSET && w->working_set.shared) - allocate_working_set(&w->working_set); + allocate_working_set(wrk, &w->working_set); } wrk->max_working_set_id = -1; @@ -1533,7 +1561,7 @@ alloc_step_batch(struct workload *wrk, struct w_step *w) igt_assert(set->nr); igt_assert(entry->target < set->nr); - igt_assert(set->sizes[entry->target]); + igt_assert(set->sizes[entry->target].size); dep_handle = set->handles[entry->target]; } @@ -1701,15 +1729,27 @@ static size_t sizeof_engines_bond(int count) engines[count]); } -static void allocate_working_set(struct working_set *set) +static unsigned long +get_buffer_size(struct workload *wrk, const struct work_buffer_size *sz) +{ + if (sz->min == sz->max) + return sz->min; + else + return sz->min + hars_petruska_f54_1_random(&wrk->bo_prng) % + (sz->max + 1 - sz->min); +} + +static void allocate_working_set(struct workload *wrk, struct working_set *set) { unsigned int i; set->handles = calloc(set->nr, sizeof(*set->handles)); igt_assert(set->handles); - for (i = 0; i < set->nr; i++) - set->handles[i] = alloc_bo(fd, set->sizes[i]); + for (i = 0; i < set->nr; i++) { + set->sizes[i].size = get_buffer_size(wrk, &set->sizes[i]); + set->handles[i] = alloc_bo(fd, set->sizes[i].size); + } } #define alloca0(sz) ({ size_t sz__ = (sz); memset(alloca(sz__), 0, sz__); }) @@ -1724,6 +1764,7 @@ static int prepare_workload(unsigned int id, struct workload *wrk) wrk->id = id; wrk->bb_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); + wrk->bo_prng = (wrk->flags & SYNCEDCLIENTS) ? master_prng : rand(); wrk->run = true; /* @@ -1956,7 +1997,7 @@ static int prepare_workload(unsigned int id, struct workload *wrk) */ for (i = 0, w = wrk->steps; i < wrk->nr_steps; i++, w++) { if (w->type == WORKINGSET && !w->working_set.shared) - allocate_working_set(&w->working_set); + allocate_working_set(wrk, &w->working_set); } /* diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 3d9143226740..8c71f2fe6579 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -307,11 +307,15 @@ For size a byte size can be given, or suffix 'k', 'm' or 'g' can be used (case insensitive). Prefix in the format of "<int>n<size>" can also be given to create multiple objects of the same size. +Ranges can also be specified using the <min>-<max> syntax. + Examples: w.1.4k - Working set 1 with a single 4KiB object in it. W.2.2M/32768 - Working set 2 with one 2MiB and one 32768 byte object. w.3.10n4k/2n20000 - Working set 3 with ten 4KiB and two 20000 byte objects. + w.4.4n4k-1m - Working set 4 with four objects of random size between 4KiB and + 1MiB. Working set objects can be referenced as data dependency targets using the new 'r'/'w' syntax. Simple example: -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:44 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:44 +0100 Subject: [Intel-gfx] [PATCH i-g-t 08/11] gem_wsim: Snippet of a workload extracted from carchase In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-8-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Some frames from the middle of a demo with corresponding buffers. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/wsim/carchasepart.wsim | 184 ++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 benchmarks/wsim/carchasepart.wsim diff --git a/benchmarks/wsim/carchasepart.wsim b/benchmarks/wsim/carchasepart.wsim new file mode 100644 index 000000000000..4407d0ef47dc --- /dev/null +++ b/benchmarks/wsim/carchasepart.wsim @@ -0,0 +1,184 @@ +w.0.118n8192 +w.1.69n12288 +w.10.145n131072 +w.11.1n163840 +w.12.3n196608 +w.13.2n229376 +w.14.2n262144 +w.15.7n327680 +w.16.2n393216 +w.17.9n458752 +w.18.30n524288 +w.19.1n655360 +w.2.74n16384 +w.20.2n917504 +w.21.1n1048576 +w.22.33n1310720 +w.23.1n1572864 +w.24.24n1835008 +w.25.117n2097152 +w.26.1n2621440 +w.27.2n3670016 +w.28.4n4194304 +w.29.3n6291456 +w.3.123n20480 +w.30.1n7340032 +w.31.1n8388608 +w.32.20n10485760 +w.33.4n12582912 +w.34.3n14680064 +w.35.1n25165824 +w.4.19n24576 +w.5.2n32768 +w.6.2n40960 +w.7.4n49152 +w.8.2n65536 +w.9.9n81920 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+1.RCS.1000.r3-60/w27-0/r0-58/r3-80/r22-31/r3-110/r9-4/w34-0/r3-18/r3-47/r21-0/r9-5/r3-78/r25-4/r3-104/r3-23/r30-0/r3-88/r22-27/r22-1/r25-45/r3-50/r22-12/r22-22/r22-3/r22-0/r25-56/r3-4/r22-15/r25-113/r3-7/r22-18/r25-60/r3-81/r25-21/r3-89/r18-5/r3-93/r17-8/r25-28/r25-87/r25-9/r25-13/r25-42/r25-90/r22-16/r34-2/r3-15/w3-64/r0-52/r25-99/r25-73/r3-6/r25-40/r3-90/r22-20/r0-68/w32-17/w32-16/w32-3/w32-1/w33-2/r28-2/r3-98/r3-85/r25-14/r3-12/r3-87/r3-108/r3-26/r3-96/r22-29/r22-14/r3-68/r3-112/r3-103/r22-5/r3-49/r22-6/r25-104/r22-28/r24-23/r25-44/r25-19/r3-67/r18-17/r4-5/r18-4/r25-111/r3-66/r25-81/r25-78/r25-37/r25-50/r25-102/r25-35/r22-7/r18-18/r18-13/r18-12/r3-69/r3-19/r3-100/r18-19/r18-26/r18-21/r3-2/r3-117/r3-33/r22-2/r25-51/r25-64/r25-70/r25-105/r25-61/r25-11/r25-75/r25-20/r25-91/r25-55/r25-66/r25-24/r25-68/r25-86/r25-26/r22-21/r25-82/r25-77/r25-33/r22-10/r25-110/r25-62/r25-72/r22-9/r8-0/r18-23/r18-7/r18-11/r3-73/r25-92/r25-41/w33-3/r0-107/w19-0/w31-0/r3-74/r32-19/r3-0/r3-114/w32-4/w29-1/w32-8.0 +d.3470 +1.RCS.32141.r9-4/r3-60/r3-18/r3-74/r22-3/r22-31/r9-5/w32-8/r3-98/r32-17/r3-6/r32-3/r32-1/w33-2/r29-1/r30-0/r3-104/r35-0/r34-1/r34-0/r3-78/r3-80/r3-92/r0-107/r34-2/r22-12/r22-1/r0-58/r3-0/w32-0/r3-75/r3-118/r3-70/r32-19/r3-1/r3-113/r22-29/r22-14/r3-109/r3-28/r3-79/r22-7.0 +d.2303 +2.RCS.33018.r9-4/r0-48/r3-0/w7-2/r3-60/r0-109/r3-74/r0-67/w6-1/r0-115/w7-0/r0-35/w7-1/r0-58/r32-8/r3-6/r22-31/w0-2/r3-113/r9-5/w0-32.0 +1.RCS.5660.r0-58/r3-80/r22-31/r3-74/r3-0/r9-4/w27-1/r3-18/r3-60/r22-14/r9-5/r0-32/r3-6/r32-8/r3-78/r3-113/r0-107/w28-0/r3-98/r3-91/w28-1/r3-93/w32-14/r32-0/r33-2/w32-16.0 +d.1494 +2.RCS.1000.r9-4/r3-74/r3-0/r32-16/r3-93/w4-16/r0-3/w3-122/r3-91/r0-58.0 +2.RCS.5873.r9-4/r33-2/r3-6/r22-31/r3-0/w0-103/w0-19/r3-74/r2-54.0 +d.1151 +1.RCS.12578.r0-58/r3-80/r22-31/r3-74/r3-0/r9-4/w32-18/r3-18/r3-60/r22-14/r9-5/r3-98/r32-14/r3-93/r33-2/r3-6/r32-16/r3-122/r3-106/r3-78/r2-54/r0-107/w32-7/w32-11/w32-2/r33-0/r25-116/r0-19/r16-0/r28-3/r0-3/r0-111/r22-32/r10-58/r4-13/r4-3/r4-1.0 +1.RCS.6159.r3-80/r22-31/r3-74/r3-0/r9-4/w9-5/r0-92/r0-58/w32-19/r3-18/r3-60/r22-14/r3-78/r3-88/r22-5/r22-6/r22-29/r22-7/r22-1/r22-12/r22-18/r22-28/r22-3/r22-0/r3-75/r3-104/w3-64/r0-87/r22-20/r25-99/r22-16/r21-0/r0-106/r0-71/r0-26/w28-2/r0-107/w8-0/r0-75.0 -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:45 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:45 +0100 Subject: [Intel-gfx] [PATCH i-g-t 09/11] gem_wsim: Implement device selection In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-9-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> New command line options -L and -D <device> can respectively be used to list and select a GPU when more than one is present. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 62 +++++++++++++++++++++++++++++++------------ 1 file changed, 45 insertions(+), 17 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 8788f752121b..59ddc798a3ea 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -43,6 +43,7 @@ #include <pthread.h> #include <math.h> +#include "igt_device_scan.h" #include "intel_chipset.h" #include "intel_reg.h" #include "drm.h" @@ -2611,7 +2612,9 @@ static void print_help(void) " clients.\n" " -d Sync between data dependencies in userspace.\n" " -f <scale> Scale factor for batch durations.\n" -" -F <scale> Scale factor for delays." +" -F <scale> Scale factor for delays.\n" +" -L List GPUs.\n" +" -D <gpu> One of the GPUs from -L." ); } @@ -2672,31 +2675,32 @@ int main(int argc, char **argv) char *append_workload_arg = NULL; struct w_arg *w_args = NULL; unsigned int tolerance_pct = 1; + enum igt_devices_print_type printtype = IGT_PRINT_SIMPLE; + bool list_devices_arg = false; int exitcode = EXIT_FAILURE; + struct igt_device_card card; double scale_time = 1.0f; double scale_dur = 1.0f; + char *device_arg = NULL; int prio = 0; double t; - int i, c; + int i, c, ret; char *subopts, *value; int raw_number = 0; long calib_val; int eng; - /* - * Open the device via the low-level API so we can do the GPU quiesce - * manually as close as possible in time to the start of the workload. - * This minimizes the gap in engine utilization tracking when observed - * via external tools like trace.pl. - */ - fd = __drm_open_driver_render(DRIVER_INTEL); - igt_require(fd); - master_prng = time(NULL); while ((c = getopt(argc, argv, - "ThqvsSdc:n:r:w:W:a:t:p:I:f:F:")) != -1) { + "LThqvsSdc:n:r:w:W:a:t:p:I:f:F:D:")) != -1) { switch (c) { + case 'L': + list_devices_arg = true; + break; + case 'D': + device_arg = strdup(optarg); + break; case 'W': if (master_workload >= 0) { wsim_err("Only one master workload can be given!\n"); @@ -2820,6 +2824,33 @@ int main(int argc, char **argv) } } + + igt_devices_scan(false); + + if (list_devices_arg) { + igt_devices_print(printtype); + return EXIT_SUCCESS; + } + + if (device_arg) { + ret = igt_device_card_match(device_arg, &card); + if (!ret) { + wsim_err("Requested device %s not found!\n", device_arg); + free(device_arg); + + return EXIT_FAILURE; + } + free(device_arg); + } else { + igt_device_find_first_i915_discrete_card(&card); + } + + if (card.render[0]) + fd = igt_open_render(&card); + else + fd = __drm_open_driver_render(DRIVER_INTEL); + igt_require(fd); + if (!has_nop_calibration) { if (verbose > 1) { printf("Calibrating nop delays with %u%% tolerance...\n", @@ -2932,15 +2963,12 @@ int main(int argc, char **argv) clock_gettime(CLOCK_MONOTONIC, &t_start); for (i = 0; i < clients; i++) { - int ret; - ret = pthread_create(&w[i]->thread, NULL, run_workload, w[i]); igt_assert_eq(ret, 0); } if (master_workload >= 0) { - int ret = pthread_join(w[master_workload]->thread, NULL); - + ret = pthread_join(w[master_workload]->thread, NULL); igt_assert(ret == 0); for (i = 0; i < clients; i++) @@ -2949,7 +2977,7 @@ int main(int argc, char **argv) for (i = 0; i < clients; i++) { if (master_workload != i) { - int ret = pthread_join(w[i]->thread, NULL); + ret = pthread_join(w[i]->thread, NULL); igt_assert(ret == 0); } } -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:46 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:46 +0100 Subject: [Intel-gfx] [PATCH i-g-t 10/11] gem_wsim: Fix calibration handling In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-10-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Intended use case was that run without arguments prints out the calibrations which can be simply copied and pasted to the -n argument and things should just work. Two problems we need to solve: If the print out loops shows zero calibrations (engine not present) they are later rejected and also if some calibration is not given it is only an error if it needs to be used (engine present). Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 59ddc798a3ea..811a4b1b7161 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -296,8 +296,8 @@ print_engine_calibrations(void) printf("Nop calibration for %uus delay is: ", nop_calibration_us); for (int i = 0; i < NUM_ENGINES; i++) { - /* skip DEFAULT and VCS engines */ - if (i != DEFAULT && i != VCS) { + /* skip engines not present and DEFAULT and VCS */ + if (i != DEFAULT && i != VCS && engine_calib_map[i]) { if (first_entry) { printf("%s=%lu", ring_str_map[i], engine_calib_map[i]); first_entry = false; @@ -2862,22 +2862,6 @@ int main(int argc, char **argv) if (verbose) print_engine_calibrations(); goto out; - } else { - bool missing = false; - - for (i = 0; i < NUM_ENGINES; i++) { - if (i == VCS) - continue; - - if (!engine_calib_map[i]) { - wsim_err("Missing calibration for '%s'!\n", - ring_str_map[i]); - missing = true; - } - } - - if (missing) - goto err; } if (!nr_w_args) { -- 2.20.1 From tvrtko.ursulin at linux.intel.com Thu Jun 18 10:47:47 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Thu, 18 Jun 2020 11:47:47 +0100 Subject: [Intel-gfx] [PATCH i-g-t 11/11] gem_wsim: Do not keep batch mapped unless needed In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <20200618104747.24005-11-tvrtko.ursulin@linux.intel.com> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> At this point we only need to keep the mapping for infinite batch buffers. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> --- benchmarks/gem_wsim.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 811a4b1b7161..496e5042d89c 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -1449,6 +1449,7 @@ static unsigned int terminate_bb(struct w_step *w) const uint32_t bbe = 0xa << 23; unsigned long mmap_start, mmap_len; unsigned long batch_start = w->bb_sz; + bool keep_mmap = false; unsigned int r = 0; uint32_t *ptr, *cs; @@ -1472,6 +1473,7 @@ static unsigned int terminate_bb(struct w_step *w) *cs++ = w->preempt_us ? 0x5 << 23 /* MI_ARB_CHK; */ : MI_NOOP; w->recursive_bb_start = cs; + keep_mmap = true; *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; *cs++ = 0; *cs++ = 0; @@ -1479,6 +1481,9 @@ static unsigned int terminate_bb(struct w_step *w) *cs = bbe; + if (!keep_mmap) + munmap(ptr, mmap_len); + return r; } -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 10:50:02 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 11:50:02 +0100 Subject: [Intel-gfx] [PATCH i-g-t] tests: Move perf/perf_pmu under i915 Message-ID: <20200618105002.292615-1-chris@chris-wilson.co.uk> These are i915 specific tests of the perf and perf-workalike interfaces, so move them under i915/ Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- tests/Makefile.sources | 8 ++++++-- tests/{ => i915}/perf.c | 0 tests/{ => i915}/perf_pmu.c | 0 tests/meson.build | 6 ++++-- 4 files changed, 10 insertions(+), 4 deletions(-) rename tests/{ => i915}/perf.c (100%) rename tests/{ => i915}/perf_pmu.c (100%) diff --git a/tests/Makefile.sources b/tests/Makefile.sources index eaa6c0d04..af900bcfc 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -88,8 +88,6 @@ TESTS_progs = \ kms_vblank \ kms_vrr \ meta_test \ - perf \ - perf_pmu \ prime_busy \ prime_mmap \ prime_mmap_coherency \ @@ -115,6 +113,12 @@ sysfs_preempt_timeout_SOURCES = i915/sysfs_preempt_timeout.c TESTS_progs += sysfs_timeslice_duration sysfs_timeslice_duration_SOURCES = i915/sysfs_timeslice_duration.c +TESTS_progs += perf +perf_SOURCES = i915/perf.c + +TESTS_progs += perf_pmu +perf_pmu_SOURCES = i915/perf_pmu.c + TESTS_progs += gem_bad_reloc gem_bad_reloc_SOURCES = i915/gem_bad_reloc.c diff --git a/tests/perf.c b/tests/i915/perf.c similarity index 100% rename from tests/perf.c rename to tests/i915/perf.c diff --git a/tests/perf_pmu.c b/tests/i915/perf_pmu.c similarity index 100% rename from tests/perf_pmu.c rename to tests/i915/perf_pmu.c diff --git a/tests/meson.build b/tests/meson.build index e69bdb7d0..28091794f 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -336,14 +336,16 @@ test_executables += executable('i915_pm_rc6_residency', install : true) test_list += 'i915_pm_rc6_residency' -test_executables += executable('perf_pmu', 'perf_pmu.c', +test_executables += executable('perf_pmu', + join_paths('i915', 'perf_pmu.c'), dependencies : test_deps + [ lib_igt_perf ], install_dir : libexecdir, install_rpath : libexecdir_rpathdir, install : true) test_list += 'perf_pmu' -test_executables += executable('perf', 'perf.c', +test_executables += executable('perf', + join_paths('i915', 'perf.c'), dependencies : test_deps + [ lib_igt_i915_perf ], install_dir : libexecdir, install_rpath : libexecdir_rpathdir, -- 2.27.0 From patchwork at emeril.freedesktop.org Thu Jun 18 11:02:15 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 11:02:15 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_co?= =?utf-8?q?mpleted_requests_on_unwind?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159247813563.22462.1529923705945791908@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0c59db1704c2 drm/i915/gt: Decouple completed requests on unwind 4579cb31c97b drm/i915/gt: Check for a completed last request once 4222b55f2f1b drm/i915/gt: Replace direct submit with direct call to tasklet 398abbf02330 drm/i915/execlists: Defer schedule_out until after the next dequeue fbe78a584bd5 drm/i915/gt: ce->inflight updates are now serialised ddfc925aa0db drm/i915/gt: Drop atomic for engine->fw_active tracking caa926734fc2 drm/i915/gt: Extract busy-stats for ring-scheduler -:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #12: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 95 lines checked 94d03393704b drm/i915/gt: Convert stats.active to plain unsigned int 779d99c25deb drm/i915/gt: Use virtual_engine during execlists_dequeue 0cdb3bb12cc5 drm/i915/gt: Decouple inflight virtual engines d1bee1d3a71f drm/i915/gt: Resubmit the virtual engine on schedule-out From patchwork at emeril.freedesktop.org Thu Jun 18 11:03:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 11:03:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_comple?= =?utf-8?q?ted_requests_on_unwind?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159247821147.22459.5147479854828881991@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From chris at chris-wilson.co.uk Thu Jun 18 11:09:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:09:58 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t 01/11] gem_wsim: Rip out userspace balancing In-Reply-To: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> Message-ID: <159247859872.4042.2113901688631498152@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:37) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Evaluation of userspace load balancing options was how this tool started > but since we have settled on doing it in the kernel. > > Tomorrow we will want to update the tool for new engine interfaces and all > this legacy code will just be a distraction. > > Rip out everything not related to explicit load balancing implemented via > context engine maps and adjust the workloads to use it. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Acked-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Thu Jun 18 11:10:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:10:53 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t 02/11] gem_wsim: Buffer objects working sets and complex dependencies In-Reply-To: <20200618104747.24005-2-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> <20200618104747.24005-2-tvrtko.ursulin@linux.intel.com> Message-ID: <159247865314.4042.1526670173526063951@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:38) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Add support for defining buffer object working sets and targetting them as > data dependencies. For more information please see the README file. > > v2: > * More robustness in parsing here and there. (Chris) > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Is there a tag for "please don't make me read more of the parser"? Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Thu Jun 18 11:11:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:11:21 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t 03/11] gem_wsim: Show workload timing stats In-Reply-To: <20200618104747.24005-3-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> <20200618104747.24005-3-tvrtko.ursulin@linux.intel.com> Message-ID: <159247868128.4042.6014377314408789507@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:39) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Show average/min/max workload iteration and dropped period stats when 'p' > command is used. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Thu Jun 18 11:11:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:11:47 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t 04/11] gem_wsim: Move BO allocation to a helper In-Reply-To: <20200618104747.24005-4-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> <20200618104747.24005-4-tvrtko.ursulin@linux.intel.com> Message-ID: <159247870755.4042.5483070981360593479@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:40) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Thu Jun 18 11:12:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:12:16 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t 05/11] gem_wsim: Support random buffer sizes In-Reply-To: <20200618104747.24005-5-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> <20200618104747.24005-5-tvrtko.ursulin@linux.intel.com> Message-ID: <159247873610.4042.1730295657652342446@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:41) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > See README for more details. > > v2: > * No need to mess with flags. (Chris) > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Thu Jun 18 11:13:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:13:20 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t 06/11] gem_wsim: Support scaling workload batch durations In-Reply-To: <20200618104747.24005-6-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> <20200618104747.24005-6-tvrtko.ursulin@linux.intel.com> Message-ID: <159247880012.4042.9756640358854900579@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:42) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > -f <float> on the command line can be used to scale batch buffer durations > in all parsed workloads. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From chris at chris-wilson.co.uk Thu Jun 18 11:13:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:13:41 +0100 Subject: [Intel-gfx] [PATCH i-g-t 08/11] gem_wsim: Snippet of a workload extracted from carchase In-Reply-To: <20200618104747.24005-8-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> <20200618104747.24005-8-tvrtko.ursulin@linux.intel.com> Message-ID: <159247882154.4042.3156108670582393851@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:44) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Some frames from the middle of a demo with corresponding buffers. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Acked-by: Chris Wilson <chris at chris-wilson.co.uk> From chris at chris-wilson.co.uk Thu Jun 18 11:15:52 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:15:52 +0100 Subject: [Intel-gfx] [igt-dev] [PATCH i-g-t 10/11] gem_wsim: Fix calibration handling In-Reply-To: <20200618104747.24005-10-tvrtko.ursulin@linux.intel.com> References: <20200618104747.24005-1-tvrtko.ursulin@linux.intel.com> <20200618104747.24005-10-tvrtko.ursulin@linux.intel.com> Message-ID: <159247895295.4042.7104358099170023321@build.alporthouse.com> Quoting Tvrtko Ursulin (2020-06-18 11:47:46) > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Intended use case was that run without arguments prints out the > calibrations which can be simply copied and pasted to the -n argument and > things should just work. > > Two problems we need to solve: If the print out loops shows zero > calibrations (engine not present) they are later rejected and also if some > calibration is not given it is only an error if it needs to be used > (engine present). > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Good enough, Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris From patchwork at emeril.freedesktop.org Thu Jun 18 11:32:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 11:32:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_completed?= =?utf-8?q?_requests_on_unwind?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159247996318.22461.4296202779497322763@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind URL : https://patchwork.freedesktop.org/series/78522/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8641 -> Patchwork_17986 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17986 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17986, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17986: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_selftest@live at hangcheck: - fi-bsw-nick: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-nick/igt at i915_selftest@live at hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-bsw-nick/igt at i915_selftest@live at hangcheck.html - fi-cml-s: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-s/igt at i915_selftest@live at hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-cml-s/igt at i915_selftest@live at hangcheck.html * igt at i915_selftest@live at workarounds: - fi-bsw-n3050: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-n3050/igt at i915_selftest@live at workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-bsw-n3050/igt at i915_selftest@live at workarounds.html - fi-cml-s: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-s/igt at i915_selftest@live at workarounds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-cml-s/igt at i915_selftest@live at workarounds.html - fi-icl-y: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-y/igt at i915_selftest@live at workarounds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-icl-y/igt at i915_selftest@live at workarounds.html - fi-kbl-x1275: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at i915_selftest@live at workarounds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-x1275/igt at i915_selftest@live at workarounds.html - fi-cfl-guc: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-guc/igt at i915_selftest@live at workarounds.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-cfl-guc/igt at i915_selftest@live at workarounds.html - fi-skl-6600u: [PASS][17] -> [DMESG-WARN][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-skl-6600u/igt at i915_selftest@live at workarounds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-skl-6600u/igt at i915_selftest@live at workarounds.html - fi-apl-guc: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-apl-guc/igt at i915_selftest@live at workarounds.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-apl-guc/igt at i915_selftest@live at workarounds.html - fi-kbl-8809g: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-8809g/igt at i915_selftest@live at workarounds.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-8809g/igt at i915_selftest@live at workarounds.html - fi-cfl-8700k: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-8700k/igt at i915_selftest@live at workarounds.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-cfl-8700k/igt at i915_selftest@live at workarounds.html - fi-kbl-r: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-r/igt at i915_selftest@live at workarounds.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-r/igt at i915_selftest@live at workarounds.html - fi-icl-guc: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-guc/igt at i915_selftest@live at workarounds.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-icl-guc/igt at i915_selftest@live at workarounds.html - fi-icl-u2: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-u2/igt at i915_selftest@live at workarounds.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-icl-u2/igt at i915_selftest@live at workarounds.html - fi-cfl-8109u: [PASS][31] -> [INCOMPLETE][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-8109u/igt at i915_selftest@live at workarounds.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-cfl-8109u/igt at i915_selftest@live at workarounds.html - fi-bsw-nick: [PASS][33] -> [DMESG-WARN][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-nick/igt at i915_selftest@live at workarounds.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-bsw-nick/igt at i915_selftest@live at workarounds.html - fi-skl-lmem: [PASS][35] -> [DMESG-WARN][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-skl-lmem/igt at i915_selftest@live at workarounds.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-skl-lmem/igt at i915_selftest@live at workarounds.html - fi-kbl-7500u: [PASS][37] -> [INCOMPLETE][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-7500u/igt at i915_selftest@live at workarounds.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-7500u/igt at i915_selftest@live at workarounds.html - fi-kbl-guc: [PASS][39] -> [DMESG-WARN][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-guc/igt at i915_selftest@live at workarounds.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-guc/igt at i915_selftest@live at workarounds.html - fi-bdw-5557u: [PASS][41] -> [DMESG-WARN][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bdw-5557u/igt at i915_selftest@live at workarounds.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-bdw-5557u/igt at i915_selftest@live at workarounds.html - fi-kbl-soraka: [PASS][43] -> [INCOMPLETE][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-soraka/igt at i915_selftest@live at workarounds.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-soraka/igt at i915_selftest@live at workarounds.html - fi-whl-u: [PASS][45] -> [INCOMPLETE][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-whl-u/igt at i915_selftest@live at workarounds.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-whl-u/igt at i915_selftest@live at workarounds.html - fi-bxt-dsi: [PASS][47] -> [INCOMPLETE][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bxt-dsi/igt at i915_selftest@live at workarounds.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-bxt-dsi/igt at i915_selftest@live at workarounds.html - fi-cml-u2: [PASS][49] -> [INCOMPLETE][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-u2/igt at i915_selftest@live at workarounds.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-cml-u2/igt at i915_selftest@live at workarounds.html * igt at runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][51] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-bdw-5557u/igt at runner@aborted.html - fi-tgl-u2: NOTRUN -> [FAIL][52] [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-tgl-u2/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at workarounds: - {fi-tgl-dsi}: [PASS][53] -> [INCOMPLETE][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html - {fi-ehl-1}: [PASS][55] -> [DMESG-WARN][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-ehl-1/igt at i915_selftest@live at workarounds.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-ehl-1/igt at i915_selftest@live at workarounds.html - {fi-kbl-7560u}: [PASS][57] -> [INCOMPLETE][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-7560u/igt at i915_selftest@live at workarounds.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-7560u/igt at i915_selftest@live at workarounds.html Known issues ------------ Here are the changes found in Patchwork_17986 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-kbl-soraka: [PASS][59] -> [DMESG-WARN][60] ([i915#1982]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-soraka/igt at i915_module_load@reload.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-soraka/igt at i915_module_load@reload.html * igt at i915_selftest@live at hangcheck: - fi-kbl-guc: [PASS][61] -> [INCOMPLETE][62] ([fdo#108744]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-guc/igt at i915_selftest@live at hangcheck.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-guc/igt at i915_selftest@live at hangcheck.html * igt at i915_selftest@live at workarounds: - fi-skl-6700k2: [PASS][63] -> [INCOMPLETE][64] ([i915#69]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-skl-6700k2/igt at i915_selftest@live at workarounds.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-skl-6700k2/igt at i915_selftest@live at workarounds.html - fi-glk-dsi: [PASS][65] -> [INCOMPLETE][66] ([i915#58] / [k.org#198133]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-glk-dsi/igt at i915_selftest@live at workarounds.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-glk-dsi/igt at i915_selftest@live at workarounds.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][67] -> [DMESG-WARN][68] ([i915#1982]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-cml-s: [PASS][69] -> [DMESG-WARN][70] ([i915#1982]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-s/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-cml-s/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][71] ([i915#1888]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][73] ([i915#1982]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-modeset at d-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][75] ([i915#1982]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][77] ([fdo#109271]) -> [DMESG-FAIL][78] ([i915#62]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][79] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][80] ([i915#62] / [i915#92]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][81] ([i915#62] / [i915#92]) -> [DMESG-WARN][82] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (49 -> 41) ------------------------------ Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17986 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17986: d1bee1d3a71f8bff04efbc4680db74983532e812 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d1bee1d3a71f drm/i915/gt: Resubmit the virtual engine on schedule-out 0cdb3bb12cc5 drm/i915/gt: Decouple inflight virtual engines 779d99c25deb drm/i915/gt: Use virtual_engine during execlists_dequeue 94d03393704b drm/i915/gt: Convert stats.active to plain unsigned int caa926734fc2 drm/i915/gt: Extract busy-stats for ring-scheduler ddfc925aa0db drm/i915/gt: Drop atomic for engine->fw_active tracking fbe78a584bd5 drm/i915/gt: ce->inflight updates are now serialised 398abbf02330 drm/i915/execlists: Defer schedule_out until after the next dequeue 4222b55f2f1b drm/i915/gt: Replace direct submit with direct call to tasklet 4579cb31c97b drm/i915/gt: Check for a completed last request once 0c59db1704c2 drm/i915/gt: Decouple completed requests on unwind == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17986/index.html From chris at chris-wilson.co.uk Thu Jun 18 11:48:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:48:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Replace direct submit with direct call to tasklet In-Reply-To: <20200618100356.15744-3-chris@chris-wilson.co.uk> References: <20200618100356.15744-3-chris@chris-wilson.co.uk> Message-ID: <20200618114821.8148-1-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET softirq synchronous"). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 20 ++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 113 ++++++------------ drivers/gpu/drm/i915/gt/intel_reset.c | 4 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/i915_request.c | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 8 files changed, 79 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef425fd990c4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2355,7 +2355,9 @@ static void eb_request_add(struct i915_execbuffer *eb) __i915_request_skip(rq); } + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); /* Try to clean up the client's timeline after submitting the request */ if (prev) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..60881c8b5b7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +static int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err = __intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..80e9f74040f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,17 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void heartbeat_commit(struct i915_request *rq, + const struct i915_sched_attr *attr) +{ + idle_pulse(rq->engine, rq); + __i915_request_commit(rq); + + local_bh_disable(); + __i915_request_queue(rq, attr); + local_bh_enable(); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -132,12 +143,10 @@ static void heartbeat(struct work_struct *wrk) if (IS_ERR(rq)) goto unlock; - idle_pulse(engine, rq); if (i915_modparams.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); unlock: mutex_unlock(&ce->timeline->mutex); @@ -218,10 +227,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) } __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); - idle_pulse(engine, rq); - - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER); err = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7bdbfac26d7b..70671dbdcc77 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2067,8 +2067,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = execlists->active; struct i915_request *last; + unsigned long flags; struct rb_node *rb; bool submit = false; @@ -2093,6 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * sequence of requests as being the most optimal (fewest wake ups * and context switches) submission. */ + spin_lock_irqsave(&engine->active.lock, flags); for (rb = rb_first_cached(&execlists->virtual); rb; ) { struct virtual_engine *ve = @@ -2121,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2138,8 +2137,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if ((last = *active)) { if (i915_request_completed(last) && - !list_is_last(&last->sched.link, &engine->active.requests)) + !list_is_last(&last->sched.link, &engine->active.requests)) { + spin_unlock_irqrestore(&engine->active.lock, flags); return; + } if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, @@ -2210,6 +2211,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, queue_prio(execlists)); return; } @@ -2245,6 +2247,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2377,8 +2380,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (__i915_request_submit(rq)) { if (!merge) { - *port = execlists_schedule_in(last, port - execlists->pending); - port++; + *port++ = last; last = NULL; } @@ -2416,25 +2418,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * interrupt for secondary ports). */ execlists->queue_priority_hint = queue_prio(execlists); + spin_unlock_irqrestore(&engine->active.lock, flags); if (submit) { - *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); - + *port++ = last; /* * Skip if we ended up with exactly the same set of requests, * e.g. trying to timeslice a pair of ordered contexts */ if (!memcmp(active, execlists->pending, - (port - execlists->pending + 1) * sizeof(*port))) { - do - execlists_schedule_out(fetch_and_zero(port)); - while (port-- != execlists->pending); - + (port - execlists->pending) * sizeof(*port))) goto skip_submit; - } - clear_ports(port + 1, last_port - port); + + *port = NULL; + while (port-- != execlists->pending) + *port = execlists_schedule_in(*port, + port - execlists->pending); + execlists->switch_priority_hint = + switch_prio(engine, *execlists->pending); WRITE_ONCE(execlists->yield, -1); set_preempt_timeout(engine, *active); @@ -2443,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + *execlists->pending = NULL; } } @@ -2699,16 +2701,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3098,7 +3090,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3108,7 +3100,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3118,17 +3109,11 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { - unsigned long flags; - - spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); - spin_unlock_irqrestore(&engine->active.lock, flags); + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); - } + if (!engine->execlists.pending[0]) + execlists_dequeue(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3159,26 +3144,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3188,25 +3163,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } -static void flush_csb(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists *el = &engine->execlists; - - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); - } -} - static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); - /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3220,7 +3181,8 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + if (submit_queue(engine, request)) + __execlists_kick(&engine->execlists); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4109,7 +4071,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4126,10 +4087,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4373,12 +4330,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + __execlists_kick(execlists); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..b31e2f5ec70b 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -774,11 +774,13 @@ static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake) struct intel_engine_cs *engine; enum intel_engine_id id; + local_bh_disable(); for_each_engine(engine, gt, id) { reset_finish_engine(engine); if (awake & engine->mask) intel_engine_pm_put(engine); } + local_bh_enable(); } static void nop_submit_request(struct i915_request *request) @@ -1167,7 +1169,9 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) out: intel_engine_cancel_stop_cs(engine); + local_bh_disable(); reset_finish_engine(engine); + local_bh_enable(); intel_engine_pm_put_async(engine); return ret; } diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..0fa23cb6bf1a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1582,6 +1582,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..0dad1f0fbd32 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1599,7 +1599,9 @@ void i915_request_add(struct i915_request *rq) attr = ctx->sched; rcu_read_unlock(); + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); mutex_unlock(&tl->mutex); } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 11:51:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 12:51:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Replace direct submit with direct call to tasklet In-Reply-To: <20200618100356.15744-3-chris@chris-wilson.co.uk> References: <20200618100356.15744-3-chris@chris-wilson.co.uk> Message-ID: <20200618115121.8491-1-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET softirq synchronous"). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 20 ++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 113 ++++++------------ drivers/gpu/drm/i915/gt/intel_reset.c | 4 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/i915_request.c | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 8 files changed, 79 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef425fd990c4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2355,7 +2355,9 @@ static void eb_request_add(struct i915_execbuffer *eb) __i915_request_skip(rq); } + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); /* Try to clean up the client's timeline after submitting the request */ if (prev) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..60881c8b5b7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +static int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err = __intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..80e9f74040f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,17 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void heartbeat_commit(struct i915_request *rq, + const struct i915_sched_attr *attr) +{ + idle_pulse(rq->engine, rq); + __i915_request_commit(rq); + + local_bh_disable(); + __i915_request_queue(rq, attr); + local_bh_enable(); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -132,12 +143,10 @@ static void heartbeat(struct work_struct *wrk) if (IS_ERR(rq)) goto unlock; - idle_pulse(engine, rq); if (i915_modparams.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); unlock: mutex_unlock(&ce->timeline->mutex); @@ -218,10 +227,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) } __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); - idle_pulse(engine, rq); - - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER); err = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7bdbfac26d7b..70671dbdcc77 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2067,8 +2067,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = execlists->active; struct i915_request *last; + unsigned long flags; struct rb_node *rb; bool submit = false; @@ -2093,6 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * sequence of requests as being the most optimal (fewest wake ups * and context switches) submission. */ + spin_lock_irqsave(&engine->active.lock, flags); for (rb = rb_first_cached(&execlists->virtual); rb; ) { struct virtual_engine *ve = @@ -2121,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2138,8 +2137,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if ((last = *active)) { if (i915_request_completed(last) && - !list_is_last(&last->sched.link, &engine->active.requests)) + !list_is_last(&last->sched.link, &engine->active.requests)) { + spin_unlock_irqrestore(&engine->active.lock, flags); return; + } if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, @@ -2210,6 +2211,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, queue_prio(execlists)); return; } @@ -2245,6 +2247,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2377,8 +2380,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (__i915_request_submit(rq)) { if (!merge) { - *port = execlists_schedule_in(last, port - execlists->pending); - port++; + *port++ = last; last = NULL; } @@ -2416,25 +2418,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * interrupt for secondary ports). */ execlists->queue_priority_hint = queue_prio(execlists); + spin_unlock_irqrestore(&engine->active.lock, flags); if (submit) { - *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); - + *port++ = last; /* * Skip if we ended up with exactly the same set of requests, * e.g. trying to timeslice a pair of ordered contexts */ if (!memcmp(active, execlists->pending, - (port - execlists->pending + 1) * sizeof(*port))) { - do - execlists_schedule_out(fetch_and_zero(port)); - while (port-- != execlists->pending); - + (port - execlists->pending) * sizeof(*port))) goto skip_submit; - } - clear_ports(port + 1, last_port - port); + + *port = NULL; + while (port-- != execlists->pending) + *port = execlists_schedule_in(*port, + port - execlists->pending); + execlists->switch_priority_hint = + switch_prio(engine, *execlists->pending); WRITE_ONCE(execlists->yield, -1); set_preempt_timeout(engine, *active); @@ -2443,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + *execlists->pending = NULL; } } @@ -2699,16 +2701,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3098,7 +3090,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3108,7 +3100,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3118,17 +3109,11 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { - unsigned long flags; - - spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); - spin_unlock_irqrestore(&engine->active.lock, flags); + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); - } + if (!engine->execlists.pending[0]) + execlists_dequeue(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3159,26 +3144,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3188,25 +3163,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } -static void flush_csb(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists *el = &engine->execlists; - - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); - } -} - static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); - /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3220,7 +3181,8 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + if (submit_queue(engine, request)) + __execlists_kick(&engine->execlists); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4109,7 +4071,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4126,10 +4087,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4373,12 +4330,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + __execlists_kick(execlists); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..3ba8057645f8 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -752,8 +752,10 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask) if (err) return err; + local_bh_disable(); for_each_engine(engine, gt, id) __intel_engine_reset(engine, stalled_mask & engine->mask); + local_bh_enable(); intel_ggtt_restore_fences(gt->ggtt); @@ -1156,7 +1158,9 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) * active request and can drop it, adjust head to skip the offending * request to resume executing remaining requests in the queue. */ + local_bh_disable(); __intel_engine_reset(engine, true); + local_bh_enable(); /* * The engine and its registers (and workarounds in case of render) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..0fa23cb6bf1a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1582,6 +1582,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..0dad1f0fbd32 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1599,7 +1599,9 @@ void i915_request_add(struct i915_request *rq) attr = ctx->sched; rcu_read_unlock(); + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); mutex_unlock(&tl->mutex); } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From patchwork at emeril.freedesktop.org Thu Jun 18 12:08:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 12:08:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_co?= =?utf-8?q?mpleted_requests_on_unwind_=28rev3=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159248213744.22460.12378956608806655392@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev3) URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim checkpatch origin/drm-tip 990732b3a2b0 drm/i915/gt: Decouple completed requests on unwind 3ef642da1d22 drm/i915/gt: Check for a completed last request once 24ac4a11960a drm/i915/gt: Replace direct submit with direct call to tasklet 19e8c8871406 drm/i915/execlists: Defer schedule_out until after the next dequeue 4134bd32c7be drm/i915/gt: ce->inflight updates are now serialised d04ee88b4f0c drm/i915/gt: Drop atomic for engine->fw_active tracking debb4583e9c0 drm/i915/gt: Extract busy-stats for ring-scheduler -:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #12: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 95 lines checked fd9642a91243 drm/i915/gt: Convert stats.active to plain unsigned int da379162e57f drm/i915/gt: Use virtual_engine during execlists_dequeue 7411d8542246 drm/i915/gt: Decouple inflight virtual engines 00d941188df5 drm/i915/gt: Resubmit the virtual engine on schedule-out From patchwork at emeril.freedesktop.org Thu Jun 18 12:10:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 12:10:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_comple?= =?utf-8?q?ted_requests_on_unwind_=28rev3=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159248221262.22461.11186374900040391159@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev3) URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1314:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From chris at chris-wilson.co.uk Thu Jun 18 12:10:43 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 13:10:43 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Replace direct submit with direct call to tasklet In-Reply-To: <20200618100356.15744-3-chris@chris-wilson.co.uk> References: <20200618100356.15744-3-chris@chris-wilson.co.uk> Message-ID: <20200618121043.9206-1-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET softirq synchronous"). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 20 ++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 113 ++++++------------ drivers/gpu/drm/i915/gt/intel_reset.c | 4 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/gt/selftest_reset.c | 4 + drivers/gpu/drm/i915/i915_request.c | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 9 files changed, 83 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef425fd990c4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2355,7 +2355,9 @@ static void eb_request_add(struct i915_execbuffer *eb) __i915_request_skip(rq); } + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); /* Try to clean up the client's timeline after submitting the request */ if (prev) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..60881c8b5b7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +static int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err = __intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..80e9f74040f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,17 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void heartbeat_commit(struct i915_request *rq, + const struct i915_sched_attr *attr) +{ + idle_pulse(rq->engine, rq); + __i915_request_commit(rq); + + local_bh_disable(); + __i915_request_queue(rq, attr); + local_bh_enable(); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -132,12 +143,10 @@ static void heartbeat(struct work_struct *wrk) if (IS_ERR(rq)) goto unlock; - idle_pulse(engine, rq); if (i915_modparams.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); unlock: mutex_unlock(&ce->timeline->mutex); @@ -218,10 +227,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) } __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); - idle_pulse(engine, rq); - - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER); err = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7bdbfac26d7b..70671dbdcc77 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2067,8 +2067,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = execlists->active; struct i915_request *last; + unsigned long flags; struct rb_node *rb; bool submit = false; @@ -2093,6 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * sequence of requests as being the most optimal (fewest wake ups * and context switches) submission. */ + spin_lock_irqsave(&engine->active.lock, flags); for (rb = rb_first_cached(&execlists->virtual); rb; ) { struct virtual_engine *ve = @@ -2121,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2138,8 +2137,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if ((last = *active)) { if (i915_request_completed(last) && - !list_is_last(&last->sched.link, &engine->active.requests)) + !list_is_last(&last->sched.link, &engine->active.requests)) { + spin_unlock_irqrestore(&engine->active.lock, flags); return; + } if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, @@ -2210,6 +2211,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, queue_prio(execlists)); return; } @@ -2245,6 +2247,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2377,8 +2380,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (__i915_request_submit(rq)) { if (!merge) { - *port = execlists_schedule_in(last, port - execlists->pending); - port++; + *port++ = last; last = NULL; } @@ -2416,25 +2418,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * interrupt for secondary ports). */ execlists->queue_priority_hint = queue_prio(execlists); + spin_unlock_irqrestore(&engine->active.lock, flags); if (submit) { - *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); - + *port++ = last; /* * Skip if we ended up with exactly the same set of requests, * e.g. trying to timeslice a pair of ordered contexts */ if (!memcmp(active, execlists->pending, - (port - execlists->pending + 1) * sizeof(*port))) { - do - execlists_schedule_out(fetch_and_zero(port)); - while (port-- != execlists->pending); - + (port - execlists->pending) * sizeof(*port))) goto skip_submit; - } - clear_ports(port + 1, last_port - port); + + *port = NULL; + while (port-- != execlists->pending) + *port = execlists_schedule_in(*port, + port - execlists->pending); + execlists->switch_priority_hint = + switch_prio(engine, *execlists->pending); WRITE_ONCE(execlists->yield, -1); set_preempt_timeout(engine, *active); @@ -2443,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + *execlists->pending = NULL; } } @@ -2699,16 +2701,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3098,7 +3090,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3108,7 +3100,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3118,17 +3109,11 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { - unsigned long flags; - - spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); - spin_unlock_irqrestore(&engine->active.lock, flags); + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); - } + if (!engine->execlists.pending[0]) + execlists_dequeue(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3159,26 +3144,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3188,25 +3163,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } -static void flush_csb(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists *el = &engine->execlists; - - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); - } -} - static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); - /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3220,7 +3181,8 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + if (submit_queue(engine, request)) + __execlists_kick(&engine->execlists); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4109,7 +4071,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4126,10 +4087,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4373,12 +4330,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + __execlists_kick(execlists); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..3ba8057645f8 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -752,8 +752,10 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask) if (err) return err; + local_bh_disable(); for_each_engine(engine, gt, id) __intel_engine_reset(engine, stalled_mask & engine->mask); + local_bh_enable(); intel_ggtt_restore_fences(gt->ggtt); @@ -1156,7 +1158,9 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) * active request and can drop it, adjust head to skip the offending * request to resume executing remaining requests in the queue. */ + local_bh_disable(); __intel_engine_reset(engine, true); + local_bh_enable(); /* * The engine and its registers (and workarounds in case of render) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..0fa23cb6bf1a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1582,6 +1582,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 35406ecdf0b2..43a939e39ac4 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -130,6 +130,10 @@ static int igt_atomic_engine_reset(void *arg) intel_engine_pm_get(engine); for (p = igt_atomic_phases; p->name; p++) { + /* reset utilizes tasklets / softirq */ + if (!strcmp(p->name, "softirq")) + continue; + GEM_TRACE("intel_engine_reset(%s) under %s\n", engine->name, p->name); diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..0dad1f0fbd32 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1599,7 +1599,9 @@ void i915_request_add(struct i915_request *rq) attr = ctx->sched; rcu_read_unlock(); + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); mutex_unlock(&tl->mutex); } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 12:15:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 13:15:56 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Replace direct submit with direct call to tasklet In-Reply-To: <20200618100356.15744-3-chris@chris-wilson.co.uk> References: <20200618100356.15744-3-chris@chris-wilson.co.uk> Message-ID: <20200618121556.17123-1-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET softirq synchronous"). v3: Update selftests as we now need softirq around the reset to protect the tasklet. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 20 ++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 113 ++++++------------ drivers/gpu/drm/i915/gt/intel_reset.c | 4 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/gt/selftest_reset.c | 59 --------- drivers/gpu/drm/i915/i915_request.c | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 9 files changed, 79 insertions(+), 163 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef425fd990c4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2355,7 +2355,9 @@ static void eb_request_add(struct i915_execbuffer *eb) __i915_request_skip(rq); } + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); /* Try to clean up the client's timeline after submitting the request */ if (prev) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..60881c8b5b7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +static int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err = __intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..80e9f74040f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,17 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void heartbeat_commit(struct i915_request *rq, + const struct i915_sched_attr *attr) +{ + idle_pulse(rq->engine, rq); + __i915_request_commit(rq); + + local_bh_disable(); + __i915_request_queue(rq, attr); + local_bh_enable(); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -132,12 +143,10 @@ static void heartbeat(struct work_struct *wrk) if (IS_ERR(rq)) goto unlock; - idle_pulse(engine, rq); if (i915_modparams.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); unlock: mutex_unlock(&ce->timeline->mutex); @@ -218,10 +227,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) } __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); - idle_pulse(engine, rq); - - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER); err = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7bdbfac26d7b..70671dbdcc77 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2067,8 +2067,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = execlists->active; struct i915_request *last; + unsigned long flags; struct rb_node *rb; bool submit = false; @@ -2093,6 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * sequence of requests as being the most optimal (fewest wake ups * and context switches) submission. */ + spin_lock_irqsave(&engine->active.lock, flags); for (rb = rb_first_cached(&execlists->virtual); rb; ) { struct virtual_engine *ve = @@ -2121,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2138,8 +2137,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if ((last = *active)) { if (i915_request_completed(last) && - !list_is_last(&last->sched.link, &engine->active.requests)) + !list_is_last(&last->sched.link, &engine->active.requests)) { + spin_unlock_irqrestore(&engine->active.lock, flags); return; + } if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, @@ -2210,6 +2211,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, queue_prio(execlists)); return; } @@ -2245,6 +2247,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2377,8 +2380,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (__i915_request_submit(rq)) { if (!merge) { - *port = execlists_schedule_in(last, port - execlists->pending); - port++; + *port++ = last; last = NULL; } @@ -2416,25 +2418,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * interrupt for secondary ports). */ execlists->queue_priority_hint = queue_prio(execlists); + spin_unlock_irqrestore(&engine->active.lock, flags); if (submit) { - *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); - + *port++ = last; /* * Skip if we ended up with exactly the same set of requests, * e.g. trying to timeslice a pair of ordered contexts */ if (!memcmp(active, execlists->pending, - (port - execlists->pending + 1) * sizeof(*port))) { - do - execlists_schedule_out(fetch_and_zero(port)); - while (port-- != execlists->pending); - + (port - execlists->pending) * sizeof(*port))) goto skip_submit; - } - clear_ports(port + 1, last_port - port); + + *port = NULL; + while (port-- != execlists->pending) + *port = execlists_schedule_in(*port, + port - execlists->pending); + execlists->switch_priority_hint = + switch_prio(engine, *execlists->pending); WRITE_ONCE(execlists->yield, -1); set_preempt_timeout(engine, *active); @@ -2443,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + *execlists->pending = NULL; } } @@ -2699,16 +2701,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3098,7 +3090,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3108,7 +3100,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3118,17 +3109,11 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { - unsigned long flags; - - spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); - spin_unlock_irqrestore(&engine->active.lock, flags); + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); - } + if (!engine->execlists.pending[0]) + execlists_dequeue(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3159,26 +3144,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3188,25 +3163,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } -static void flush_csb(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists *el = &engine->execlists; - - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); - } -} - static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); - /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3220,7 +3181,8 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + if (submit_queue(engine, request)) + __execlists_kick(&engine->execlists); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4109,7 +4071,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4126,10 +4087,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4373,12 +4330,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + __execlists_kick(execlists); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..3ba8057645f8 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -752,8 +752,10 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask) if (err) return err; + local_bh_disable(); for_each_engine(engine, gt, id) __intel_engine_reset(engine, stalled_mask & engine->mask); + local_bh_enable(); intel_ggtt_restore_fences(gt->ggtt); @@ -1156,7 +1158,9 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) * active request and can drop it, adjust head to skip the offending * request to resume executing remaining requests in the queue. */ + local_bh_disable(); __intel_engine_reset(engine, true); + local_bh_enable(); /* * The engine and its registers (and workarounds in case of render) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..0fa23cb6bf1a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1582,6 +1582,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 35406ecdf0b2..b6b9d7d12c9a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -102,71 +102,12 @@ static int igt_atomic_reset(void *arg) return err; } -static int igt_atomic_engine_reset(void *arg) -{ - struct intel_gt *gt = arg; - const typeof(*igt_atomic_phases) *p; - struct intel_engine_cs *engine; - enum intel_engine_id id; - int err = 0; - - /* Check that the resets are usable from atomic context */ - - if (!intel_has_reset_engine(gt)) - return 0; - - if (intel_uc_uses_guc_submission(>->uc)) - return 0; - - intel_gt_pm_get(gt); - igt_global_reset_lock(gt); - - /* Flush any requests before we get started and check basics */ - if (!igt_force_reset(gt)) - goto out_unlock; - - for_each_engine(engine, gt, id) { - tasklet_disable(&engine->execlists.tasklet); - intel_engine_pm_get(engine); - - for (p = igt_atomic_phases; p->name; p++) { - GEM_TRACE("intel_engine_reset(%s) under %s\n", - engine->name, p->name); - - p->critical_section_begin(); - err = intel_engine_reset(engine, NULL); - p->critical_section_end(); - - if (err) { - pr_err("intel_engine_reset(%s) failed under %s\n", - engine->name, p->name); - break; - } - } - - intel_engine_pm_put(engine); - tasklet_enable(&engine->execlists.tasklet); - if (err) - break; - } - - /* As we poke around the guts, do a full reset before continuing. */ - igt_force_reset(gt); - -out_unlock: - igt_global_reset_unlock(gt); - intel_gt_pm_put(gt); - - return err; -} - int intel_reset_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { SUBTEST(igt_global_reset), /* attempt to recover GPU first */ SUBTEST(igt_wedged_reset), SUBTEST(igt_atomic_reset), - SUBTEST(igt_atomic_engine_reset), }; struct intel_gt *gt = &i915->gt; diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..0dad1f0fbd32 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1599,7 +1599,9 @@ void i915_request_add(struct i915_request *rq) attr = ctx->sched; rcu_read_unlock(); + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); mutex_unlock(&tl->mutex); } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From chris at chris-wilson.co.uk Thu Jun 18 12:22:12 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 13:22:12 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Replace direct submit with direct call to tasklet In-Reply-To: <20200618100356.15744-3-chris@chris-wilson.co.uk> References: <20200618100356.15744-3-chris@chris-wilson.co.uk> Message-ID: <20200618122212.25180-1-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET softirq synchronous"). v3: Update engine-reset to be tasklet aware Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 20 ++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 113 ++++++------------ drivers/gpu/drm/i915/gt/intel_reset.c | 4 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 1 + drivers/gpu/drm/i915/i915_request.c | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 8 files changed, 79 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef425fd990c4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2355,7 +2355,9 @@ static void eb_request_add(struct i915_execbuffer *eb) __i915_request_skip(rq); } + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); /* Try to clean up the client's timeline after submitting the request */ if (prev) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..60881c8b5b7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +static int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err = __intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..80e9f74040f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,17 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void heartbeat_commit(struct i915_request *rq, + const struct i915_sched_attr *attr) +{ + idle_pulse(rq->engine, rq); + __i915_request_commit(rq); + + local_bh_disable(); + __i915_request_queue(rq, attr); + local_bh_enable(); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -132,12 +143,10 @@ static void heartbeat(struct work_struct *wrk) if (IS_ERR(rq)) goto unlock; - idle_pulse(engine, rq); if (i915_modparams.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); unlock: mutex_unlock(&ce->timeline->mutex); @@ -218,10 +227,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) } __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); - idle_pulse(engine, rq); - - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER); err = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7bdbfac26d7b..70671dbdcc77 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2067,8 +2067,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = execlists->active; struct i915_request *last; + unsigned long flags; struct rb_node *rb; bool submit = false; @@ -2093,6 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * sequence of requests as being the most optimal (fewest wake ups * and context switches) submission. */ + spin_lock_irqsave(&engine->active.lock, flags); for (rb = rb_first_cached(&execlists->virtual); rb; ) { struct virtual_engine *ve = @@ -2121,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2138,8 +2137,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if ((last = *active)) { if (i915_request_completed(last) && - !list_is_last(&last->sched.link, &engine->active.requests)) + !list_is_last(&last->sched.link, &engine->active.requests)) { + spin_unlock_irqrestore(&engine->active.lock, flags); return; + } if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, @@ -2210,6 +2211,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, queue_prio(execlists)); return; } @@ -2245,6 +2247,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2377,8 +2380,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (__i915_request_submit(rq)) { if (!merge) { - *port = execlists_schedule_in(last, port - execlists->pending); - port++; + *port++ = last; last = NULL; } @@ -2416,25 +2418,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * interrupt for secondary ports). */ execlists->queue_priority_hint = queue_prio(execlists); + spin_unlock_irqrestore(&engine->active.lock, flags); if (submit) { - *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); - + *port++ = last; /* * Skip if we ended up with exactly the same set of requests, * e.g. trying to timeslice a pair of ordered contexts */ if (!memcmp(active, execlists->pending, - (port - execlists->pending + 1) * sizeof(*port))) { - do - execlists_schedule_out(fetch_and_zero(port)); - while (port-- != execlists->pending); - + (port - execlists->pending) * sizeof(*port))) goto skip_submit; - } - clear_ports(port + 1, last_port - port); + + *port = NULL; + while (port-- != execlists->pending) + *port = execlists_schedule_in(*port, + port - execlists->pending); + execlists->switch_priority_hint = + switch_prio(engine, *execlists->pending); WRITE_ONCE(execlists->yield, -1); set_preempt_timeout(engine, *active); @@ -2443,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + *execlists->pending = NULL; } } @@ -2699,16 +2701,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3098,7 +3090,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3108,7 +3100,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3118,17 +3109,11 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { - unsigned long flags; - - spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); - spin_unlock_irqrestore(&engine->active.lock, flags); + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); - } + if (!engine->execlists.pending[0]) + execlists_dequeue(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3159,26 +3144,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3188,25 +3163,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } -static void flush_csb(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists *el = &engine->execlists; - - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); - } -} - static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); - /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3220,7 +3181,8 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + if (submit_queue(engine, request)) + __execlists_kick(&engine->execlists); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4109,7 +4071,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4126,10 +4087,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4373,12 +4330,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + __execlists_kick(execlists); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..d98455008a69 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -752,8 +752,10 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask) if (err) return err; + local_bh_disable(); for_each_engine(engine, gt, id) __intel_engine_reset(engine, stalled_mask & engine->mask); + local_bh_enable(); intel_ggtt_restore_fences(gt->ggtt); @@ -1258,6 +1260,7 @@ void intel_gt_handle_error(struct intel_gt *gt, * single reset fails. */ if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) { + local_bh_disable(); for_each_engine_masked(engine, gt, engine_mask, tmp) { BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE); if (test_and_set_bit(I915_RESET_ENGINE + engine->id, @@ -1270,6 +1273,7 @@ void intel_gt_handle_error(struct intel_gt *gt, clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, >->reset.flags); } + local_bh_enable(); } if (!engine_mask) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..0fa23cb6bf1a 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1582,6 +1582,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, p->critical_section_end(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..0dad1f0fbd32 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1599,7 +1599,9 @@ void i915_request_add(struct i915_request *rq) attr = ctx->sched; rcu_read_unlock(); + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); mutex_unlock(&tl->mutex); } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From gustavoars at kernel.org Wed Jun 17 22:03:31 2020 From: gustavoars at kernel.org (Gustavo A. R. Silva) Date: Wed, 17 Jun 2020 17:03:31 -0500 Subject: [Intel-gfx] [PATCH][next] drm/i915/query: Use struct_size() helper Message-ID: <20200617220331.GA19550@embeddedor> Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. This code was detected with the help of Coccinelle and, audited and fixed manually. Signed-off-by: Gustavo A. R. Silva <gustavoars at kernel.org> --- drivers/gpu/drm/i915/i915_query.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index e75c528ebbe0..c1ebda9b5627 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -109,8 +109,7 @@ query_engine_info(struct drm_i915_private *i915, for_each_uabi_engine(engine, i915) num_uabi_engines++; - len = sizeof(struct drm_i915_query_engine_info) + - num_uabi_engines * sizeof(struct drm_i915_engine_info); + len = struct_size(query_ptr, engines, num_uabi_engines); ret = copy_query_item(&query, sizeof(query), len, query_item); if (ret != 0) -- 2.27.0 From patchwork at emeril.freedesktop.org Thu Jun 18 12:41:05 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 12:41:05 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_completed?= =?utf-8?q?_requests_on_unwind_=28rev3=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159248406500.22460.16640419528145048799@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev3) URL : https://patchwork.freedesktop.org/series/78522/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8641 -> Patchwork_17987 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17987 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17987, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17987: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at hangcheck: - fi-snb-2520m: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-snb-2520m/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-snb-2520m/igt at i915_selftest@live at hangcheck.html * igt at i915_selftest@live at hugepages: - fi-cml-u2: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-u2/igt at i915_selftest@live at hugepages.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-cml-u2/igt at i915_selftest@live at hugepages.html * igt at i915_selftest@live at reset: - fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-guc/igt at i915_selftest@live at reset.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-cfl-guc/igt at i915_selftest@live at reset.html - fi-kbl-soraka: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-soraka/igt at i915_selftest@live at reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-kbl-soraka/igt at i915_selftest@live at reset.html - fi-cml-s: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-s/igt at i915_selftest@live at reset.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-cml-s/igt at i915_selftest@live at reset.html - fi-tgl-u2: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_selftest@live at reset.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-tgl-u2/igt at i915_selftest@live at reset.html - fi-icl-guc: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-guc/igt at i915_selftest@live at reset.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-icl-guc/igt at i915_selftest@live at reset.html - fi-bsw-kefka: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-kefka/igt at i915_selftest@live at reset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-bsw-kefka/igt at i915_selftest@live at reset.html - fi-bdw-5557u: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bdw-5557u/igt at i915_selftest@live at reset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-bdw-5557u/igt at i915_selftest@live at reset.html - fi-kbl-x1275: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at i915_selftest@live at reset.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-kbl-x1275/igt at i915_selftest@live at reset.html - fi-kbl-7500u: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-7500u/igt at i915_selftest@live at reset.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-kbl-7500u/igt at i915_selftest@live at reset.html - fi-icl-y: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-y/igt at i915_selftest@live at reset.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-icl-y/igt at i915_selftest@live at reset.html - fi-cfl-8109u: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-8109u/igt at i915_selftest@live at reset.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-cfl-8109u/igt at i915_selftest@live at reset.html - fi-icl-u2: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-u2/igt at i915_selftest@live at reset.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-icl-u2/igt at i915_selftest@live at reset.html - fi-cfl-8700k: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-8700k/igt at i915_selftest@live at reset.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-cfl-8700k/igt at i915_selftest@live at reset.html - fi-apl-guc: [PASS][31] -> [INCOMPLETE][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-apl-guc/igt at i915_selftest@live at reset.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-apl-guc/igt at i915_selftest@live at reset.html - fi-skl-6600u: [PASS][33] -> [INCOMPLETE][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-skl-6600u/igt at i915_selftest@live at reset.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-skl-6600u/igt at i915_selftest@live at reset.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at reset: - {fi-ehl-1}: [PASS][35] -> [INCOMPLETE][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-ehl-1/igt at i915_selftest@live at reset.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-ehl-1/igt at i915_selftest@live at reset.html - {fi-tgl-dsi}: [PASS][37] -> [INCOMPLETE][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at i915_selftest@live at reset.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-tgl-dsi/igt at i915_selftest@live at reset.html Known issues ------------ Here are the changes found in Patchwork_17987 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at reset: - fi-glk-dsi: [PASS][41] -> [INCOMPLETE][42] ([i915#58] / [k.org#198133]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-glk-dsi/igt at i915_selftest@live at reset.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-glk-dsi/igt at i915_selftest@live at reset.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][43] -> [DMESG-WARN][44] ([i915#62] / [i915#92] / [i915#95]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_busy@basic at flip.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [PASS][45] -> [DMESG-WARN][46] ([i915#1982]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][47] ([i915#1888]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][49] ([i915#402]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_module_load@reload.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-modeset at d-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html #### Warnings #### * igt at kms_force_connector_basic@force-connector-state: - fi-kbl-x1275: [DMESG-WARN][55] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][56] ([i915#62] / [i915#92]) +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][57] ([i915#62] / [i915#92]) -> [DMESG-WARN][58] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (49 -> 32) ------------------------------ Missing (17): fi-ilk-m540 fi-bxt-dsi fi-bdw-samus fi-bsw-n3050 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-guc fi-ctg-p8600 fi-whl-u fi-kbl-8809g fi-skl-lmem fi-kbl-7560u fi-byt-clapper fi-bsw-nick fi-skl-6700k2 fi-kbl-r Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17987 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17987: 00d941188df5028230c80cc86e67ddd84ccc0f98 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 00d941188df5 drm/i915/gt: Resubmit the virtual engine on schedule-out 7411d8542246 drm/i915/gt: Decouple inflight virtual engines da379162e57f drm/i915/gt: Use virtual_engine during execlists_dequeue fd9642a91243 drm/i915/gt: Convert stats.active to plain unsigned int debb4583e9c0 drm/i915/gt: Extract busy-stats for ring-scheduler d04ee88b4f0c drm/i915/gt: Drop atomic for engine->fw_active tracking 4134bd32c7be drm/i915/gt: ce->inflight updates are now serialised 19e8c8871406 drm/i915/execlists: Defer schedule_out until after the next dequeue 24ac4a11960a drm/i915/gt: Replace direct submit with direct call to tasklet 3ef642da1d22 drm/i915/gt: Check for a completed last request once 990732b3a2b0 drm/i915/gt: Decouple completed requests on unwind == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17987/index.html From joonas.lahtinen at linux.intel.com Thu Jun 18 12:46:59 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Thu, 18 Jun 2020 15:46:59 +0300 Subject: [Intel-gfx] [PULL] drm-intel-fixes Message-ID: <20200618124659.GA12342@jlahtine-desk.ger.corp.intel.com> Hi Dave & Daniel, -rc1 required the usual juggling to get baseline from CI. Needed to temporarily apply this fixup to drm-intel-fixes: "ext4: mballoc: Use this_cpu_read instead of this_cpu_ptr" For display side, fix for TypeC interrupt storm detection. Fixes to TypeC, DDI and MST hardware register programming. On GT side, fixes into timeslicing and missing workarounds after GPU reset. A couple of build time warning fixes. CI results are partially back online (hopefully more will come shortly): https://intel-gfx-ci.01.org/tree/drm-intel-fixes/combined-alt.html? CI_DIF_483 - With the ext4 fix CI_DIF_484 - This PR, no ext4 fix => extra warnings Regards, Joonas PS. I'll be away for the next 4 weeks, so expect to see the following drm-intel-fixes PRs from Jani and Rodrigo. *** drm-intel-fixes-2020-06-18: - Fix for timeslicing and virtual engines/unpremptable requests (+ 1 dependency patch) - Fixes into TypeC register programming and interrupt storm detecting - Disable DIP on MST ports with the transcoder clock still on - Avoid missing GT workarounds at reset for HSW and older gens - Fix for unwinding multiple requests missing force restore - Fix encoder type check for DDI vswing sequence - Build warning fixes The following changes since commit b3a9e3b9622ae10064826dccb4f7a52bd88c7407: Linux 5.8-rc1 (2020-06-14 12:45:04 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2020-06-18 for you to fetch changes up to 8e68c6340d5833077b3753eabedab40755571383: drm/i915/display: Fix the encoder type check (2020-06-16 11:34:24 +0300) ---------------------------------------------------------------- - Fix for timeslicing and virtual engines/unpremptable requests (+ 1 dependency patch) - Fixes into TypeC register programming and interrupt storm detecting - Disable DIP on MST ports with the transcoder clock still on - Avoid missing GT workarounds at reset for HSW and older gens - Fix for unwinding multiple requests missing force restore - Fix encoder type check for DDI vswing sequence - Build warning fixes ---------------------------------------------------------------- Arnd Bergmann (2): drm/i915/pmu: avoid an maybe-uninitialized warning drm/i915: work around false-positive maybe-uninitialized warning Chris Wilson (10): drm/i915/gt: Incorporate the virtual engine into timeslicing drm/i915/selftests: Restore to default heartbeat drm/i915/gt: Prevent timeslicing into unpreemptable requests drm/i915/gt: Incrementally check for rewinding drm/i915/gt: Move hsw GT workarounds from init_clock_gating to workarounds drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workarounds drm/i915/gt: Move vlv GT workarounds from init_clock_gating to workarounds drm/i915/gt: Move snb GT workarounds from init_clock_gating to workarounds drm/i915/gt: Move ilk GT workarounds from init_clock_gating to workarounds drm/i915/gt: Move gen4 GT workarounds from init_clock_gating to workarounds Imre Deak (2): drm/i915/icl: Disable DIP on MST ports with the transcoder clock still on drm/i915/icl+: Fix hotplug interrupt disabling after storm detection Khaled Almahallawy (1): drm/i915/tc: fix the reset of ln0 Vandita Kulkarni (1): drm/i915/display: Fix the encoder type check drivers/gpu/drm/i915/display/intel_ddi.c | 12 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 52 ++++- drivers/gpu/drm/i915/gt/intel_ring.c | 4 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 241 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 25 +-- drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++++++++++++---- drivers/gpu/drm/i915/gt/selftest_mocs.c | 18 +- drivers/gpu/drm/i915/gt/selftest_ring.c | 110 ++++++++++ drivers/gpu/drm/i915/gt/selftest_rps.c | 69 +++--- drivers/gpu/drm/i915/gt/selftest_timeline.c | 15 +- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 2 + drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/i915_pmu.c | 84 +++---- drivers/gpu/drm/i915/i915_priolist_types.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 206 +----------------- .../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 + 19 files changed, 668 insertions(+), 373 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/selftest_ring.c From joonas.lahtinen at linux.intel.com Thu Jun 18 12:48:01 2020 From: joonas.lahtinen at linux.intel.com (Joonas Lahtinen) Date: Thu, 18 Jun 2020 15:48:01 +0300 Subject: [Intel-gfx] [PULL] gvt-fixes In-Reply-To: <20200617043418.GQ5687@zhen-hp.sh.intel.com> References: <20200617043418.GQ5687@zhen-hp.sh.intel.com> Message-ID: <159248448107.8757.1901135788098329902@jlahtine-desk.ger.corp.intel.com> Quoting Zhenyu Wang (2020-06-17 07:34:18) > > Hi, > > This contains misc fixes for gvt. Two MMIO handler fixes on SKL/CFL, > one mask register bit checking fix exposed in suspend/resume path and > one lockdep error fix for debugfs entry access. Could not pull this one due to the extra hassle with CI this week. Jani, can you please pull this next week. Regards, Joonas > Thanks. > -- > The following changes since commit 8e68c6340d5833077b3753eabedab40755571383: > > drm/i915/display: Fix the encoder type check (2020-06-16 11:34:24 +0300) > > are available in the Git repository at: > > https://github.com/intel/gvt-linux tags/gvt-fixes-2020-06-17 > > for you to fetch changes up to a291e4fba259a56a6a274c1989997acb6f0bb03a: > > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context (2020-06-17 12:36:19 +0800) > > ---------------------------------------------------------------- > gvt-fixes-2020-06-17 > > - Two missed MMIO handler fixes for SKL/CFL (Colin) > - Fix mask register bits check (Colin) > - Fix one lockdep error for debugfs entry access (Colin) > > ---------------------------------------------------------------- > Colin Xu (4): > drm/i915/gvt: Add one missing MMIO handler for D_SKL_PLUS > drm/i915/gvt: Fix two CFL MMIO handling caused by regression. > drm/i915/gvt: Fix incorrect check of enabled bits in mask registers > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context > > drivers/gpu/drm/i915/gvt/debugfs.c | 2 +- > drivers/gpu/drm/i915/gvt/handlers.c | 24 +++++++++++++----------- > drivers/gpu/drm/i915/gvt/mmio_context.h | 6 +++--- > drivers/gpu/drm/i915/gvt/reg.h | 5 +++++ > 4 files changed, 22 insertions(+), 15 deletions(-) From patchwork at emeril.freedesktop.org Thu Jun 18 13:28:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 13:28:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_co?= =?utf-8?q?mpleted_requests_on_unwind_=28rev6=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159248689881.22460.2009412207316642342@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev6) URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9ce2e355ae34 drm/i915/gt: Decouple completed requests on unwind f28adb65371f drm/i915/gt: Check for a completed last request once 14dcb843c8c9 drm/i915/gt: Replace direct submit with direct call to tasklet 481651f51f06 drm/i915/execlists: Defer schedule_out until after the next dequeue 3e4560a995ed drm/i915/gt: ce->inflight updates are now serialised 4ed52f6c3765 drm/i915/gt: Drop atomic for engine->fw_active tracking f4bf534598ab drm/i915/gt: Extract busy-stats for ring-scheduler -:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #12: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 95 lines checked 6dfcfa8830cf drm/i915/gt: Convert stats.active to plain unsigned int c5298470fd7f drm/i915/gt: Use virtual_engine during execlists_dequeue 0f90ab391e31 drm/i915/gt: Decouple inflight virtual engines f1d37af00d9c drm/i915/gt: Resubmit the virtual engine on schedule-out From patchwork at emeril.freedesktop.org Thu Jun 18 13:29:34 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 13:29:34 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_comple?= =?utf-8?q?ted_requests_on_unwind_=28rev6=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159248697414.22462.10386448243375140927@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev6) URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1314:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Thu Jun 18 14:00:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 14:00:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_completed?= =?utf-8?q?_requests_on_unwind_=28rev6=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159248882383.22461.15265461547898176191@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev6) URL : https://patchwork.freedesktop.org/series/78522/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8641 -> Patchwork_17988 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17988 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17988, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17988: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at hangcheck: - fi-whl-u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-whl-u/igt at i915_selftest@live at hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-whl-u/igt at i915_selftest@live at hangcheck.html - fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bdw-5557u/igt at i915_selftest@live at hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-bdw-5557u/igt at i915_selftest@live at hangcheck.html - fi-cml-s: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-s/igt at i915_selftest@live at hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-cml-s/igt at i915_selftest@live at hangcheck.html * igt at i915_selftest@live at workarounds: - fi-tgl-u2: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_selftest@live at workarounds.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-tgl-u2/igt at i915_selftest@live at workarounds.html - fi-bsw-n3050: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-n3050/igt at i915_selftest@live at workarounds.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-bsw-n3050/igt at i915_selftest@live at workarounds.html - fi-cml-s: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-s/igt at i915_selftest@live at workarounds.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-cml-s/igt at i915_selftest@live at workarounds.html - fi-icl-y: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-y/igt at i915_selftest@live at workarounds.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-icl-y/igt at i915_selftest@live at workarounds.html - fi-cfl-guc: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-guc/igt at i915_selftest@live at workarounds.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-cfl-guc/igt at i915_selftest@live at workarounds.html - fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-skl-6600u/igt at i915_selftest@live at workarounds.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-skl-6600u/igt at i915_selftest@live at workarounds.html - fi-apl-guc: [PASS][19] -> [DMESG-WARN][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-apl-guc/igt at i915_selftest@live at workarounds.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-apl-guc/igt at i915_selftest@live at workarounds.html - fi-kbl-8809g: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-8809g/igt at i915_selftest@live at workarounds.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-kbl-8809g/igt at i915_selftest@live at workarounds.html - fi-bsw-kefka: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-kefka/igt at i915_selftest@live at workarounds.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-bsw-kefka/igt at i915_selftest@live at workarounds.html - fi-cfl-8700k: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-8700k/igt at i915_selftest@live at workarounds.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-cfl-8700k/igt at i915_selftest@live at workarounds.html - fi-kbl-r: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-r/igt at i915_selftest@live at workarounds.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-kbl-r/igt at i915_selftest@live at workarounds.html - fi-icl-guc: [PASS][29] -> [DMESG-WARN][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-guc/igt at i915_selftest@live at workarounds.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-icl-guc/igt at i915_selftest@live at workarounds.html - fi-icl-u2: [PASS][31] -> [DMESG-WARN][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-u2/igt at i915_selftest@live at workarounds.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-icl-u2/igt at i915_selftest@live at workarounds.html - fi-cfl-8109u: [PASS][33] -> [DMESG-WARN][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-8109u/igt at i915_selftest@live at workarounds.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-cfl-8109u/igt at i915_selftest@live at workarounds.html - fi-bsw-nick: [PASS][35] -> [INCOMPLETE][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-nick/igt at i915_selftest@live at workarounds.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-bsw-nick/igt at i915_selftest@live at workarounds.html - fi-kbl-7500u: [PASS][37] -> [INCOMPLETE][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-7500u/igt at i915_selftest@live at workarounds.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-kbl-7500u/igt at i915_selftest@live at workarounds.html - fi-kbl-guc: [PASS][39] -> [DMESG-WARN][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-guc/igt at i915_selftest@live at workarounds.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-kbl-guc/igt at i915_selftest@live at workarounds.html - fi-bdw-5557u: [PASS][41] -> [DMESG-WARN][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bdw-5557u/igt at i915_selftest@live at workarounds.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-bdw-5557u/igt at i915_selftest@live at workarounds.html - fi-kbl-soraka: [PASS][43] -> [INCOMPLETE][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-soraka/igt at i915_selftest@live at workarounds.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-kbl-soraka/igt at i915_selftest@live at workarounds.html - fi-whl-u: [PASS][45] -> [DMESG-WARN][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-whl-u/igt at i915_selftest@live at workarounds.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-whl-u/igt at i915_selftest@live at workarounds.html - fi-bxt-dsi: [PASS][47] -> [DMESG-WARN][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bxt-dsi/igt at i915_selftest@live at workarounds.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-bxt-dsi/igt at i915_selftest@live at workarounds.html - fi-cml-u2: [PASS][49] -> [INCOMPLETE][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-u2/igt at i915_selftest@live at workarounds.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-cml-u2/igt at i915_selftest@live at workarounds.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at workarounds: - {fi-tgl-dsi}: [PASS][51] -> [INCOMPLETE][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-tgl-dsi/igt at i915_selftest@live at workarounds.html - {fi-ehl-1}: [PASS][53] -> [DMESG-WARN][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-ehl-1/igt at i915_selftest@live at workarounds.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-ehl-1/igt at i915_selftest@live at workarounds.html Known issues ------------ Here are the changes found in Patchwork_17988 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][55] -> [DMESG-WARN][56] ([i915#1982]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_module_load@reload.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-byt-j1900/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][57] -> [DMESG-WARN][58] ([i915#1982]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [PASS][59] -> [INCOMPLETE][60] ([i915#1932]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at i915_selftest@live at workarounds: - fi-glk-dsi: [PASS][61] -> [INCOMPLETE][62] ([i915#58] / [k.org#198133]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-glk-dsi/igt at i915_selftest@live at workarounds.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-glk-dsi/igt at i915_selftest@live at workarounds.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][63] -> [DMESG-WARN][64] ([i915#1982]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][65] -> [DMESG-WARN][66] ([i915#402]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][67] ([i915#1888]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-modeset at d-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (49 -> 39) ------------------------------ Missing (10): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 fi-skl-lmem fi-bdw-samus fi-byt-clapper fi-skl-6700k2 Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17988 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17988: f1d37af00d9c64aac63052be876f2317853d59d2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f1d37af00d9c drm/i915/gt: Resubmit the virtual engine on schedule-out 0f90ab391e31 drm/i915/gt: Decouple inflight virtual engines c5298470fd7f drm/i915/gt: Use virtual_engine during execlists_dequeue 6dfcfa8830cf drm/i915/gt: Convert stats.active to plain unsigned int f4bf534598ab drm/i915/gt: Extract busy-stats for ring-scheduler 4ed52f6c3765 drm/i915/gt: Drop atomic for engine->fw_active tracking 3e4560a995ed drm/i915/gt: ce->inflight updates are now serialised 481651f51f06 drm/i915/execlists: Defer schedule_out until after the next dequeue 14dcb843c8c9 drm/i915/gt: Replace direct submit with direct call to tasklet f28adb65371f drm/i915/gt: Check for a completed last request once 9ce2e355ae34 drm/i915/gt: Decouple completed requests on unwind == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17988/index.html From patchwork at emeril.freedesktop.org Thu Jun 18 14:20:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 14:20:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/query=3A_Use_struct=5Fsize=28=29_helper?= In-Reply-To: <20200617220331.GA19550@embeddedor> References: <20200617220331.GA19550@embeddedor> Message-ID: <159249005630.22462.10240815207011609288@emeril.freedesktop.org> == Series Details == Series: drm/i915/query: Use struct_size() helper URL : https://patchwork.freedesktop.org/series/78527/ State : success == Summary == CI Bug Log - changes from CI_DRM_8641 -> Patchwork_17989 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/index.html Known issues ------------ Here are the changes found in Patchwork_17989 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (49 -> 30) ------------------------------ Missing (19): fi-cml-u2 fi-ilk-m540 fi-bdw-5557u fi-cml-s fi-tgl-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-8700k fi-kbl-7500u fi-ctg-p8600 fi-kbl-x1275 fi-kbl-8809g fi-skl-lmem fi-bdw-samus fi-byt-clapper fi-bsw-nick fi-skl-6700k2 fi-kbl-r Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17989 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17989: 65c25dcbbb056a8f4e88cea8fca087e524b349d5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 65c25dcbbb05 drm/i915/query: Use struct_size() helper == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/index.html From daniel at ffwll.ch Thu Jun 18 14:42:36 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Thu, 18 Jun 2020 16:42:36 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200617152940.GG6578@ziepe.ca> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> <20200616145312.GC6578@ziepe.ca> <CAKMK7uER6ax1zr14xYLKqDfDZp+ycBsY9Yx7JaVkKQ849VfSPg@mail.gmail.com> <20200617152940.GG6578@ziepe.ca> Message-ID: <20200618144236.GR20149@phenom.ffwll.local> On Wed, Jun 17, 2020 at 12:29:40PM -0300, Jason Gunthorpe wrote: > On Wed, Jun 17, 2020 at 09:57:54AM +0200, Daniel Vetter wrote: > > > > At the very least I think there should be some big warning that > > > dma_fence in notifiers should be avoided. > > > > Yeah I'm working on documentation, and also the notifiers here > > hopefully make it clear it's massive pain. I think we could even make > > a hard rule that dma_fence in mmu notifier outside of drivers/gpu is a > > bug/misfeature. > > Yep! > > > Might be a good idea to add a MAINTAINERS entry with a K: regex > > pattern, so that you can catch such modifiers. We do already have such > > a pattern for dma-fence, to catch abuse. So if you want I could type > > up a documentation patch for this, get your and others acks and the > > dri-devel folks would enforce that the dma_fence_wait madness doesn't > > leak beyond drivers/gpu > > It seems like the best thing Just thought about where to best put this, and I think including it as another paragraph in the next round of this series makes the most sense. You'll get cc'ed for acking when that happens - might take a while since there's a lot of details here all over to sort out. -Daniel > > > Oded has agreed to remove the dma-fence usage, since they really don't > > need it (and all the baggage that comes with it), plain old completion > > is enough for their use. This use is also why I added the regex to > > MAINTAINERS, so that in the future we can catch people who try to use > > dma_fence because it looks cute and useful, and are completely > > oblivious to all the pain and headaches involved. > > This is good! > > Thanks, > Jason -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From chris at chris-wilson.co.uk Thu Jun 18 14:51:07 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 18 Jun 2020 15:51:07 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Replace direct submit with direct call to tasklet In-Reply-To: <20200618100356.15744-3-chris@chris-wilson.co.uk> References: <20200618100356.15744-3-chris@chris-wilson.co.uk> Message-ID: <20200618145107.8708-1-chris@chris-wilson.co.uk> Rather than having special case code for opportunistically calling process_csb() and performing a direct submit while holding the engine spinlock for submitting the request, simply call the tasklet directly. This allows us to retain the direct submission path, including the CS draining to allow fast/immediate submissions, without requiring any duplicated code paths. v2: Use bh kicking, see commit 3c53776e29f8 ("Mark HI and TASKLET softirq synchronous"). v3: Update engine-reset to be tasklet aware Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +++--- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 20 ++-- drivers/gpu/drm/i915/gt/intel_lrc.c | 113 ++++++------------ drivers/gpu/drm/i915/gt/intel_reset.c | 45 ++++--- drivers/gpu/drm/i915/gt/intel_reset.h | 2 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 7 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 27 +++-- drivers/gpu/drm/i915/gt/selftest_reset.c | 8 +- drivers/gpu/drm/i915/i915_request.c | 2 + drivers/gpu/drm/i915/selftests/i915_request.c | 6 +- 12 files changed, 139 insertions(+), 132 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 30c229fcb404..9206844796cc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -399,12 +399,14 @@ static bool __reset_engine(struct intel_engine_cs *engine) if (!intel_has_reset_engine(gt)) return false; + local_bh_disable(); if (!test_and_set_bit(I915_RESET_ENGINE + engine->id, >->reset.flags)) { - success = intel_engine_reset(engine, NULL) == 0; + success = __intel_engine_reset_bh(engine, NULL) == 0; clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, >->reset.flags); } + local_bh_enable(); return success; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef425fd990c4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2355,7 +2355,9 @@ static void eb_request_add(struct i915_execbuffer *eb) __i915_request_skip(rq); } + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); /* Try to clean up the client's timeline after submitting the request */ if (prev) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..60881c8b5b7c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -903,32 +903,39 @@ static unsigned long stop_timeout(const struct intel_engine_cs *engine) return READ_ONCE(engine->props.stop_timeout_ms); } -int intel_engine_stop_cs(struct intel_engine_cs *engine) +static int __intel_engine_stop_cs(struct intel_engine_cs *engine, + int fast_timeout_us, + int slow_timeout_ms) { struct intel_uncore *uncore = engine->uncore; - const u32 base = engine->mmio_base; - const i915_reg_t mode = RING_MI_MODE(base); + const i915_reg_t mode = RING_MI_MODE(engine->mmio_base); + int err; + + intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); + err = __intel_wait_for_register_fw(engine->uncore, mode, + MODE_IDLE, MODE_IDLE, + fast_timeout_us, + slow_timeout_ms, + NULL); + + /* A final mmio read to let GPU writes be hopefully flushed to memory */ + intel_uncore_posting_read_fw(uncore, mode); + return err; +} + +int intel_engine_stop_cs(struct intel_engine_cs *engine) +{ int err; if (INTEL_GEN(engine->i915) < 3) return -ENODEV; ENGINE_TRACE(engine, "\n"); - - intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING)); - - err = 0; - if (__intel_wait_for_register_fw(uncore, - mode, MODE_IDLE, MODE_IDLE, - 1000, stop_timeout(engine), - NULL)) { + if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) { ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n"); err = -ETIMEDOUT; } - /* A final mmio read to let GPU writes be hopefully flushed to memory */ - intel_uncore_posting_read_fw(uncore, mode); - return err; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..80e9f74040f1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -42,6 +42,17 @@ static void idle_pulse(struct intel_engine_cs *engine, struct i915_request *rq) i915_request_add_active_barriers(rq); } +static void heartbeat_commit(struct i915_request *rq, + const struct i915_sched_attr *attr) +{ + idle_pulse(rq->engine, rq); + __i915_request_commit(rq); + + local_bh_disable(); + __i915_request_queue(rq, attr); + local_bh_enable(); +} + static void show_heartbeat(const struct i915_request *rq, struct intel_engine_cs *engine) { @@ -132,12 +143,10 @@ static void heartbeat(struct work_struct *wrk) if (IS_ERR(rq)) goto unlock; - idle_pulse(engine, rq); if (i915_modparams.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); unlock: mutex_unlock(&ce->timeline->mutex); @@ -218,10 +227,7 @@ int intel_engine_pulse(struct intel_engine_cs *engine) } __set_bit(I915_FENCE_FLAG_SENTINEL, &rq->fence.flags); - idle_pulse(engine, rq); - - __i915_request_commit(rq); - __i915_request_queue(rq, &attr); + heartbeat_commit(rq, &attr); GEM_BUG_ON(rq->sched.attr.priority < I915_PRIORITY_BARRIER); err = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7bdbfac26d7b..70671dbdcc77 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2067,8 +2067,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) struct intel_engine_execlists * const execlists = &engine->execlists; struct i915_request **port = execlists->pending; struct i915_request ** const last_port = port + execlists->port_mask; - struct i915_request * const *active; + struct i915_request * const *active = execlists->active; struct i915_request *last; + unsigned long flags; struct rb_node *rb; bool submit = false; @@ -2093,6 +2094,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * sequence of requests as being the most optimal (fewest wake ups * and context switches) submission. */ + spin_lock_irqsave(&engine->active.lock, flags); for (rb = rb_first_cached(&execlists->virtual); rb; ) { struct virtual_engine *ve = @@ -2121,10 +2123,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * the active context to interject the preemption request, * i.e. we will retrigger preemption following the ack in case * of trouble. - */ - active = READ_ONCE(execlists->active); - - /* + * * In theory we can skip over completed contexts that have not * yet been processed by events (as those events are in flight): * @@ -2138,8 +2137,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if ((last = *active)) { if (i915_request_completed(last) && - !list_is_last(&last->sched.link, &engine->active.requests)) + !list_is_last(&last->sched.link, &engine->active.requests)) { + spin_unlock_irqrestore(&engine->active.lock, flags); return; + } if (need_preempt(engine, last, rb)) { ENGINE_TRACE(engine, @@ -2210,6 +2211,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * Even if ELSP[1] is occupied and not worthy * of timeslices, our queue might be. */ + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, queue_prio(execlists)); return; } @@ -2245,6 +2247,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (last && !can_merge_rq(last, rq)) { spin_unlock(&ve->base.active.lock); + spin_unlock_irqrestore(&engine->active.lock, flags); start_timeslice(engine, rq_prio(rq)); return; /* leave this for another sibling */ } @@ -2377,8 +2380,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) if (__i915_request_submit(rq)) { if (!merge) { - *port = execlists_schedule_in(last, port - execlists->pending); - port++; + *port++ = last; last = NULL; } @@ -2416,25 +2418,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) * interrupt for secondary ports). */ execlists->queue_priority_hint = queue_prio(execlists); + spin_unlock_irqrestore(&engine->active.lock, flags); if (submit) { - *port = execlists_schedule_in(last, port - execlists->pending); - execlists->switch_priority_hint = - switch_prio(engine, *execlists->pending); - + *port++ = last; /* * Skip if we ended up with exactly the same set of requests, * e.g. trying to timeslice a pair of ordered contexts */ if (!memcmp(active, execlists->pending, - (port - execlists->pending + 1) * sizeof(*port))) { - do - execlists_schedule_out(fetch_and_zero(port)); - while (port-- != execlists->pending); - + (port - execlists->pending) * sizeof(*port))) goto skip_submit; - } - clear_ports(port + 1, last_port - port); + + *port = NULL; + while (port-- != execlists->pending) + *port = execlists_schedule_in(*port, + port - execlists->pending); + execlists->switch_priority_hint = + switch_prio(engine, *execlists->pending); WRITE_ONCE(execlists->yield, -1); set_preempt_timeout(engine, *active); @@ -2443,6 +2444,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) start_timeslice(engine, execlists->queue_priority_hint); skip_submit: ring_set_paused(engine, 0); + *execlists->pending = NULL; } } @@ -2699,16 +2701,6 @@ static void process_csb(struct intel_engine_cs *engine) invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); } -static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) -{ - lockdep_assert_held(&engine->active.lock); - if (!READ_ONCE(engine->execlists.pending[0])) { - rcu_read_lock(); /* protect peeking at execlists->active */ - execlists_dequeue(engine); - rcu_read_unlock(); - } -} - static void __execlists_hold(struct i915_request *rq) { LIST_HEAD(list); @@ -3098,7 +3090,7 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) if (!timer_expired(t)) return false; - return READ_ONCE(engine->execlists.pending[0]); + return engine->execlists.pending[0]; } /* @@ -3108,7 +3100,6 @@ static bool preempt_timeout(const struct intel_engine_cs *const engine) static void execlists_submission_tasklet(unsigned long data) { struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; - bool timeout = preempt_timeout(engine); process_csb(engine); @@ -3118,17 +3109,11 @@ static void execlists_submission_tasklet(unsigned long data) execlists_reset(engine, "CS error"); } - if (!READ_ONCE(engine->execlists.pending[0]) || timeout) { - unsigned long flags; - - spin_lock_irqsave(&engine->active.lock, flags); - __execlists_submission_tasklet(engine); - spin_unlock_irqrestore(&engine->active.lock, flags); + if (unlikely(preempt_timeout(engine))) + execlists_reset(engine, "preemption time out"); - /* Recheck after serialising with direct-submission */ - if (unlikely(timeout && preempt_timeout(engine))) - execlists_reset(engine, "preemption time out"); - } + if (!engine->execlists.pending[0]) + execlists_dequeue(engine); } static void __execlists_kick(struct intel_engine_execlists *execlists) @@ -3159,26 +3144,16 @@ static void queue_request(struct intel_engine_cs *engine, set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags); } -static void __submit_queue_imm(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists * const execlists = &engine->execlists; - - if (reset_in_progress(execlists)) - return; /* defer until we restart the engine following reset */ - - __execlists_submission_tasklet(engine); -} - -static void submit_queue(struct intel_engine_cs *engine, +static bool submit_queue(struct intel_engine_cs *engine, const struct i915_request *rq) { struct intel_engine_execlists *execlists = &engine->execlists; if (rq_prio(rq) <= execlists->queue_priority_hint) - return; + return false; execlists->queue_priority_hint = rq_prio(rq); - __submit_queue_imm(engine); + return true; } static bool ancestor_on_hold(const struct intel_engine_cs *engine, @@ -3188,25 +3163,11 @@ static bool ancestor_on_hold(const struct intel_engine_cs *engine, return !list_empty(&engine->active.hold) && hold_request(rq); } -static void flush_csb(struct intel_engine_cs *engine) -{ - struct intel_engine_execlists *el = &engine->execlists; - - if (READ_ONCE(el->pending[0]) && tasklet_trylock(&el->tasklet)) { - if (!reset_in_progress(el)) - process_csb(engine); - tasklet_unlock(&el->tasklet); - } -} - static void execlists_submit_request(struct i915_request *request) { struct intel_engine_cs *engine = request->engine; unsigned long flags; - /* Hopefully we clear execlists->pending[] to let us through */ - flush_csb(engine); - /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->active.lock, flags); @@ -3220,7 +3181,8 @@ static void execlists_submit_request(struct i915_request *request) GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); GEM_BUG_ON(list_empty(&request->sched.link)); - submit_queue(engine, request); + if (submit_queue(engine, request)) + __execlists_kick(&engine->execlists); } spin_unlock_irqrestore(&engine->active.lock, flags); @@ -4109,7 +4071,6 @@ static int execlists_resume(struct intel_engine_cs *engine) static void execlists_reset_prepare(struct intel_engine_cs *engine) { struct intel_engine_execlists * const execlists = &engine->execlists; - unsigned long flags; ENGINE_TRACE(engine, "depth<-%d\n", atomic_read(&execlists->tasklet.count)); @@ -4126,10 +4087,6 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) __tasklet_disable_sync_once(&execlists->tasklet); GEM_BUG_ON(!reset_in_progress(execlists)); - /* And flush any current direct submission. */ - spin_lock_irqsave(&engine->active.lock, flags); - spin_unlock_irqrestore(&engine->active.lock, flags); - /* * We stop engines, otherwise we might get failed reset and a * dead gpu (on elk). Also as modern gpu as kbl can suffer @@ -4373,12 +4330,12 @@ static void execlists_reset_finish(struct intel_engine_cs *engine) * to sleep before we restart and reload a context. */ GEM_BUG_ON(!reset_in_progress(execlists)); - if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) - execlists->tasklet.func(execlists->tasklet.data); + GEM_BUG_ON(engine->execlists.pending[0]); + /* And kick in case we missed a new request submission. */ if (__tasklet_enable(&execlists->tasklet)) - /* And kick in case we missed a new request submission. */ - tasklet_hi_schedule(&execlists->tasklet); + __execlists_kick(execlists); + ENGINE_TRACE(engine, "depth->%d\n", atomic_read(&execlists->tasklet.count)); } diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..29835d203971 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -752,8 +752,10 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask) if (err) return err; + local_bh_disable(); for_each_engine(engine, gt, id) __intel_engine_reset(engine, stalled_mask & engine->mask); + local_bh_enable(); intel_ggtt_restore_fences(gt->ggtt); @@ -1108,20 +1110,7 @@ static inline int intel_gt_reset_engine(struct intel_engine_cs *engine) return __intel_gt_reset(engine->gt, engine->mask); } -/** - * intel_engine_reset - reset GPU engine to recover from a hang - * @engine: engine to reset - * @msg: reason for GPU reset; or NULL for no drm_notice() - * - * Reset a specific GPU engine. Useful if a hang is detected. - * Returns zero on successful reset or otherwise an error code. - * - * Procedure is: - * - identifies the request that caused the hang and it is dropped - * - reset engine (which will force the engine to idle) - * - re-init/configure engine - */ -int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) +int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg) { struct intel_gt *gt = engine->gt; bool uses_guc = intel_engine_in_guc_submission_mode(engine); @@ -1172,6 +1161,30 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) return ret; } +/** + * intel_engine_reset - reset GPU engine to recover from a hang + * @engine: engine to reset + * @msg: reason for GPU reset; or NULL for no drm_notice() + * + * Reset a specific GPU engine. Useful if a hang is detected. + * Returns zero on successful reset or otherwise an error code. + * + * Procedure is: + * - identifies the request that caused the hang and it is dropped + * - reset engine (which will force the engine to idle) + * - re-init/configure engine + */ +int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) +{ + int err; + + local_bh_disable(); + err = __intel_engine_reset_bh(engine, msg); + local_bh_enable(); + + return err; +} + static void intel_gt_reset_global(struct intel_gt *gt, u32 engine_mask, const char *reason) @@ -1258,18 +1271,20 @@ void intel_gt_handle_error(struct intel_gt *gt, * single reset fails. */ if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) { + local_bh_disable(); for_each_engine_masked(engine, gt, engine_mask, tmp) { BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE); if (test_and_set_bit(I915_RESET_ENGINE + engine->id, >->reset.flags)) continue; - if (intel_engine_reset(engine, msg) == 0) + if (__intel_engine_reset_bh(engine, msg) == 0) engine_mask &= ~engine->mask; clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, >->reset.flags); } + local_bh_enable(); } if (!engine_mask) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h index 8e8d5f761166..675910ca1a35 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.h +++ b/drivers/gpu/drm/i915/gt/intel_reset.h @@ -34,6 +34,8 @@ void intel_gt_reset(struct intel_gt *gt, const char *reason); int intel_engine_reset(struct intel_engine_cs *engine, const char *reason); +int __intel_engine_reset_bh(struct intel_engine_cs *engine, + const char *reason); void __i915_request_reset(struct i915_request *rq, bool guilty); diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index fb5ebf930ab2..c28d1fcad673 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -1576,12 +1576,17 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, engine->name, mode, p->name); tasklet_disable(t); + if (strcmp(p->name, "softirq")) + local_bh_disable(); p->critical_section_begin(); - err = intel_engine_reset(engine, NULL); + err = __intel_engine_reset_bh(engine, NULL); p->critical_section_end(); + if (strcmp(p->name, "softirq")) + local_bh_enable(); tasklet_enable(t); + tasklet_hi_schedule(t); if (err) pr_err("i915_reset_engine(%s:%s) failed under %s\n", diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index daa4aabab9a7..aa98d351dfcc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -623,8 +623,10 @@ static int live_hold_reset(void *arg) /* We have our request executing, now remove it and reset */ + local_bh_disable(); if (test_and_set_bit(I915_RESET_ENGINE + id, >->reset.flags)) { + local_bh_enable(); intel_gt_set_wedged(gt); err = -EBUSY; goto out; @@ -638,12 +640,13 @@ static int live_hold_reset(void *arg) execlists_hold(engine, rq); GEM_BUG_ON(!i915_request_on_hold(rq)); - intel_engine_reset(engine, NULL); + __intel_engine_reset_bh(engine, NULL); GEM_BUG_ON(rq->fence.error != -EIO); tasklet_enable(&engine->execlists.tasklet); clear_and_wake_up_bit(I915_RESET_ENGINE + id, >->reset.flags); + local_bh_enable(); /* Check that we do not resubmit the held request */ if (!i915_request_wait(rq, 0, HZ / 5)) { @@ -4572,8 +4575,10 @@ static int reset_virtual_engine(struct intel_gt *gt, GEM_BUG_ON(engine == ve->engine); /* Take ownership of the reset and tasklet */ + local_bh_disable(); if (test_and_set_bit(I915_RESET_ENGINE + engine->id, >->reset.flags)) { + local_bh_enable(); intel_gt_set_wedged(gt); err = -EBUSY; goto out_heartbeat; @@ -4593,12 +4598,13 @@ static int reset_virtual_engine(struct intel_gt *gt, execlists_hold(engine, rq); GEM_BUG_ON(!i915_request_on_hold(rq)); - intel_engine_reset(engine, NULL); + __intel_engine_reset_bh(engine, NULL); GEM_BUG_ON(rq->fence.error != -EIO); /* Release our grasp on the engine, letting CS flow again */ tasklet_enable(&engine->execlists.tasklet); clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id, >->reset.flags); + local_bh_enable(); /* Check that we do not resubmit the held request */ i915_request_get(rq); @@ -6236,16 +6242,17 @@ static void garbage_reset(struct intel_engine_cs *engine, const unsigned int bit = I915_RESET_ENGINE + engine->id; unsigned long *lock = &engine->gt->reset.flags; - if (test_and_set_bit(bit, lock)) - return; - - tasklet_disable(&engine->execlists.tasklet); + local_bh_disable(); + if (!test_and_set_bit(bit, lock)) { + tasklet_disable(&engine->execlists.tasklet); - if (!rq->fence.error) - intel_engine_reset(engine, NULL); + if (!rq->fence.error) + __intel_engine_reset_bh(engine, NULL); - tasklet_enable(&engine->execlists.tasklet); - clear_and_wake_up_bit(bit, lock); + tasklet_enable(&engine->execlists.tasklet); + clear_and_wake_up_bit(bit, lock); + } + local_bh_enable(); } static struct i915_request *garbage(struct intel_context *ce, diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 35406ecdf0b2..19dd0c347874 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -132,11 +132,16 @@ static int igt_atomic_engine_reset(void *arg) for (p = igt_atomic_phases; p->name; p++) { GEM_TRACE("intel_engine_reset(%s) under %s\n", engine->name, p->name); + if (strcmp(p->name, "softirq")) + local_bh_disable(); p->critical_section_begin(); - err = intel_engine_reset(engine, NULL); + err = __intel_engine_reset_bh(engine, NULL); p->critical_section_end(); + if (strcmp(p->name, "softirq")) + local_bh_enable(); + if (err) { pr_err("intel_engine_reset(%s) failed under %s\n", engine->name, p->name); @@ -146,6 +151,7 @@ static int igt_atomic_engine_reset(void *arg) intel_engine_pm_put(engine); tasklet_enable(&engine->execlists.tasklet); + tasklet_hi_schedule(&engine->execlists.tasklet); if (err) break; } diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 3bb7320249ae..0dad1f0fbd32 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1599,7 +1599,9 @@ void i915_request_add(struct i915_request *rq) attr = ctx->sched; rcu_read_unlock(); + local_bh_disable(); __i915_request_queue(rq, &attr); + local_bh_enable(); mutex_unlock(&tl->mutex); } diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..66564f37fd06 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1926,9 +1926,7 @@ static int measure_inter_request(struct intel_context *ce) intel_ring_advance(rq, cs); i915_request_add(rq); } - local_bh_disable(); i915_sw_fence_commit(submit); - local_bh_enable(); intel_engine_flush_submission(ce->engine); heap_fence_put(submit); @@ -2214,11 +2212,9 @@ static int measure_completion(struct intel_context *ce) intel_ring_advance(rq, cs); dma_fence_add_callback(&rq->fence, &cb.base, signal_cb); - - local_bh_disable(); i915_request_add(rq); - local_bh_enable(); + intel_engine_flush_submission(ce->engine); if (wait_for(READ_ONCE(sema[i]) == -1, 50)) { err = -EIO; goto err; -- 2.20.1 From daniel at ffwll.ch Thu Jun 18 15:00:51 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Thu, 18 Jun 2020 17:00:51 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200617152835.GF6578@ziepe.ca> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> <20200617152835.GF6578@ziepe.ca> Message-ID: <20200618150051.GS20149@phenom.ffwll.local> On Wed, Jun 17, 2020 at 12:28:35PM -0300, Jason Gunthorpe wrote: > On Wed, Jun 17, 2020 at 08:48:50AM +0200, Daniel Vetter wrote: > > > Now my understanding for rdma is that if you don't have hw page fault > > support, > > The RDMA ODP feature is restartable HW page faulting just like nouveau > has. The classical MR feature doesn't have this. Only mlx5 HW supports > ODP today. > > > It's only gpus (I think) which are in this awkward in-between spot > > where dynamic memory management really is much wanted, but the hw > > kinda sucks. Aside, about 10+ years ago we had a similar problem with > > gpu hw, but for security: Many gpu didn't have any kinds of page > > tables to isolate different clients from each another. drivers/gpu > > fixed this by parsing&validating what userspace submitted to make sure > > it's only every accessing its own buffers. Most gpus have become > > reasonable nowadays and do have proper per-process pagetables (gpu > > process, not the pasid stuff), but even today there's still some of > > the old model left in some of the smallest SoC. > > But I still don't understand why a dma fence is needed inside the GPU > driver itself in the notifier. > > Surely the GPU driver can block and release the notifier directly from > its own command processing channel? > > Why does this fence and all it entails need to leak out across > drivers? So 10 years ago we had this world of every gpu driver is its own bucket, nothing leaks out to the world. But the world had a different idea how gpus where supposed to work, with stuff like: - laptops with a power-efficient but slow gpu integrated on the cpu die, and a 2nd, much faster but also more wasteful gpu seperately - also multi-gpu rendering (but on linux we never really got around to enabling that, at least not for 3d rendering) - soc just bundle IP blocks together, and very often they feel like they have to do their own display block (it's fairly easy and allows you to keep your hw engineers justified on payroll with some more patents they create), but anything more fancy they buy in. So from a driver architecture pov even a single chip soc looks like a bundle of gpus And you want to pipeline all this because performance, so waiting in userspace for one block to finish before you hand it ever to the other isn't a good idea. Hence dma_fence as a cross driver leak was created by pulling the gpu completion tracking from the drm/ttm library for managing vram. Now with glorious hindsight we could have come up with a different approach, where synchronization is managed by userspace, kernel just provides some primitives (kinda like futexes, but for gpu). And the kernel manages residency and gpu pte wrangling entirely seperately. But: - 10 years ago drivers/gpu was a handful of people at best - we just finished the massive rewrite to get to a kernel memory manager and kernel modesetting (over 5 years after windows/macos), so appetite for massive rewrites was minimal. Here we are, now with 50 more drivers built on top and an entire userspace ecosystem that relies on all this (because yes we made dma_fence also the building block for all the cross-process uapi, why wouldn't we). I hope that explains a bit the history of how and why we ended up here. Maybe I should do a plumbers talk about "How not to memory manage - cautious tales from drivers/gpu" I think there's a lot of areas where the conversation usually goes "wtf" ... long explanation of history and technical reasons leading to a "oh dear". With a lot of other accelerators and things landing might be good to have a list of things that look tempting (because hey 2% faster) but arent worth the pain. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From jani.nikula at intel.com Thu Jun 18 15:04:02 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Thu, 18 Jun 2020 18:04:02 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/params: switch to device specific parameters Message-ID: <20200618150402.14022-1-jani.nikula@intel.com> Start using device specific parameters instead of module parameters for most things. The module parameters become the immutable initial values for i915 parameters. The device specific parameters in i915->params start life as a copy of i915_modparams. Any later changes are only reflected in the debugfs. The stragglers are: * i915.force_probe and i915.modeset. Needed before dev_priv is available. This is fine because the parameters are read-only and never modified. * i915.verbose_state_checks. Passing dev_priv to I915_STATE_WARN and I915_STATE_WARN_ON would result in massive and ugly churn. This is handled by not exposing the parameter via debugfs, and leaving the parameter writable in sysfs. This may be fixed up in follow-up work. * i915.inject_probe_failure. Only makes sense in terms of the module, not the device. This is handled by not exposing the parameter via debugfs. v2: Fix uc i915 lookup code (Micha? Winiarski) Cc: Juha-Pekka Heikkil? <juha-pekka.heikkila at intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> Cc: Micha? Winiarski <michal.winiarski at intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com> Signed-off-by: Jani Nikula <jani.nikula at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 6 ++-- drivers/gpu/drm/i915/display/intel_crt.c | 4 +-- drivers/gpu/drm/i915/display/intel_csr.c | 6 ++-- drivers/gpu/drm/i915/display/intel_display.c | 12 +++---- .../drm/i915/display/intel_display_debugfs.c | 2 +- .../drm/i915/display/intel_display_power.c | 14 ++++---- drivers/gpu/drm/i915/display/intel_dp.c | 8 +++-- .../drm/i915/display/intel_dp_aux_backlight.c | 4 +-- drivers/gpu/drm/i915/display/intel_fbc.c | 12 +++---- drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-- drivers/gpu/drm/i915/display/intel_opregion.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 4 +-- drivers/gpu/drm/i915/display/intel_psr.c | 10 +++--- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 3 +- drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++-- .../drm/i915/gt/selftest_engine_heartbeat.c | 6 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 15 +++++---- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++- drivers/gpu/drm/i915/gt/uc/intel_uc.c | 20 ++++++------ drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 +++++++++---------- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_debugfs_params.c | 7 +--- drivers/gpu/drm/i915/i915_drv.c | 9 ++++-- drivers/gpu/drm/i915/i915_drv.h | 5 ++- drivers/gpu/drm/i915/i915_getparam.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-- drivers/gpu/drm/i915/intel_gvt.c | 8 ++--- drivers/gpu/drm/i915/intel_region_lmem.c | 6 ++-- drivers/gpu/drm/i915/intel_uncore.c | 8 ++--- 30 files changed, 120 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index c974c716f859..6593e2c38043 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -479,7 +479,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv, struct drm_display_mode *panel_fixed_mode; int index; - index = i915_modparams.vbt_sdvo_panel_type; + index = dev_priv->params.vbt_sdvo_panel_type; if (index == -2) { drm_dbg_kms(&dev_priv->drm, "Ignore SDVO panel mode from BIOS VBT tables.\n"); @@ -829,9 +829,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) u8 vswing; /* Don't read from VBT if module parameter has valid value*/ - if (i915_modparams.edp_vswing) { + if (dev_priv->params.edp_vswing) { dev_priv->vbt.edp.low_vswing = - i915_modparams.edp_vswing == 1; + dev_priv->params.edp_vswing == 1; } else { vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; dev_priv->vbt.edp.low_vswing = vswing == 0; diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 2f5b9a4baafd..5b4510ce5693 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -833,7 +833,7 @@ intel_crt_detect(struct drm_connector *connector, connector->base.id, connector->name, force); - if (i915_modparams.load_detect_test) { + if (dev_priv->params.load_detect_test) { wakeref = intel_display_power_get(dev_priv, intel_encoder->power_domain); goto load_detect; @@ -889,7 +889,7 @@ intel_crt_detect(struct drm_connector *connector, else if (INTEL_GEN(dev_priv) < 4) status = intel_crt_load_detect(crt, to_intel_crtc(connector->state->crtc)->pipe); - else if (i915_modparams.load_detect_test) + else if (dev_priv->params.load_detect_test) status = connector_status_disconnected; else status = connector_status_unknown; diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index 9843c9af6c13..f22a7645c249 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -723,15 +723,15 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) csr->max_fw_size = BXT_CSR_MAX_FW_SIZE; } - if (i915_modparams.dmc_firmware_path) { - if (strlen(i915_modparams.dmc_firmware_path) == 0) { + if (dev_priv->params.dmc_firmware_path) { + if (strlen(dev_priv->params.dmc_firmware_path) == 0) { csr->fw_path = NULL; drm_info(&dev_priv->drm, "Disabling CSR firmware and runtime PM\n"); return; } - csr->fw_path = i915_modparams.dmc_firmware_path; + csr->fw_path = dev_priv->params.dmc_firmware_path; /* Bypass version check for firmware override. */ csr->required_version = 0; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7457813ef273..a11bb675f9b3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4886,7 +4886,7 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) int ret; /* reset doesn't touch the display */ - if (!i915_modparams.force_reset_modeset_test && + if (!dev_priv->params.force_reset_modeset_test && !gpu_reset_clobbers_display(dev_priv)) return; @@ -7882,7 +7882,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) if (!hsw_crtc_supports_ips(crtc)) return false; - if (!i915_modparams.enable_ips) + if (!dev_priv->params.enable_ips) return false; if (crtc_state->pipe_bpp > 24) @@ -8153,8 +8153,8 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) static bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) { - if (i915_modparams.panel_use_ssc >= 0) - return i915_modparams.panel_use_ssc != 0; + if (dev_priv->params.panel_use_ssc >= 0) + return dev_priv->params.panel_use_ssc != 0; return dev_priv->vbt.lvds_use_ssc && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); } @@ -13583,8 +13583,8 @@ pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, static bool fastboot_enabled(struct drm_i915_private *dev_priv) { - if (i915_modparams.fastboot != -1) - return i915_modparams.fastboot; + if (dev_priv->params.fastboot != -1) + return dev_priv->params.fastboot; /* Enable fastboot by default on Skylake and newer */ if (INTEL_GEN(dev_priv) >= 9) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 28dd717e943a..d1cb48b3f462 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -125,7 +125,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); seq_printf(m, "Enabled by kernel parameter: %s\n", - yesno(i915_modparams.enable_ips)); + yesno(dev_priv->params.enable_ips)); if (INTEL_GEN(dev_priv) >= 8) { seq_puts(m, "Currently: unknown\n"); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 24a2aa1fdc9c..834162bc5a3f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4513,7 +4513,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, mask = 0; } - if (!i915_modparams.disable_power_well) + if (!dev_priv->params.disable_power_well) max_dc = 0; if (enable_dc >= 0 && enable_dc <= max_dc) { @@ -4602,11 +4602,11 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) struct i915_power_domains *power_domains = &dev_priv->power_domains; int err; - i915_modparams.disable_power_well = + dev_priv->params.disable_power_well = sanitize_disable_power_well_option(dev_priv, - i915_modparams.disable_power_well); + dev_priv->params.disable_power_well); dev_priv->csr.allowed_dc_mask = - get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); + get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc); dev_priv->csr.target_dc_state = sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); @@ -5568,7 +5568,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) intel_display_power_get(i915, POWER_DOMAIN_INIT); /* Disable power support if the user asked so. */ - if (!i915_modparams.disable_power_well) + if (!i915->params.disable_power_well) intel_display_power_get(i915, POWER_DOMAIN_INIT); intel_power_domains_sync_hw(i915); @@ -5592,7 +5592,7 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915) fetch_and_zero(&i915->power_domains.wakeref); /* Remove the refcount we took to keep power well support disabled. */ - if (!i915_modparams.disable_power_well) + if (!i915->params.disable_power_well) intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT); intel_display_power_flush_work_sync(i915); @@ -5681,7 +5681,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, * Even if power well support was disabled we still want to disable * power wells if power domains must be deinitialized for suspend. */ - if (!i915_modparams.disable_power_well) + if (!i915->params.disable_power_well) intel_display_power_put_unchecked(i915, POWER_DOMAIN_INIT); intel_display_power_flush_work(i915); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..192678bd9b42 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4707,7 +4707,9 @@ intel_dp_sink_can_mst(struct intel_dp *intel_dp) static bool intel_dp_can_mst(struct intel_dp *intel_dp) { - return i915_modparams.enable_dp_mst && + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + return i915->params.enable_dp_mst && intel_dp->can_mst && intel_dp_sink_can_mst(intel_dp); } @@ -4724,13 +4726,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", encoder->base.base.id, encoder->base.name, yesno(intel_dp->can_mst), yesno(sink_can_mst), - yesno(i915_modparams.enable_dp_mst)); + yesno(i915->params.enable_dp_mst)); if (!intel_dp->can_mst) return; intel_dp->is_mst = sink_can_mst && - i915_modparams.enable_dp_mst; + i915->params.enable_dp_mst; drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 0722540d64ad..acbd7eb66cbe 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -348,7 +348,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder); struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (i915_modparams.enable_dpcd_backlight == 0 || + if (i915->params.enable_dpcd_backlight == 0 || !intel_dp_aux_display_control_capable(intel_connector)) return -ENODEV; @@ -358,7 +358,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) */ if (i915->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE && - i915_modparams.enable_dpcd_backlight != 1 && + i915->params.enable_dpcd_backlight != 1 && !drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks, DP_QUIRK_FORCE_DPCD_BACKLIGHT)) { drm_info(&i915->drm, diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 1c26673acb2d..30649e17cfb7 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -740,7 +740,7 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) return false; } - if (!i915_modparams.enable_fbc) { + if (!dev_priv->params.enable_fbc) { fbc->no_fbc_reason = "disabled per module param or by default"; return false; } @@ -1017,7 +1017,7 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) fbc->flip_pending = false; - if (!i915_modparams.enable_fbc) { + if (!dev_priv->params.enable_fbc) { intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); __intel_fbc_disable(dev_priv); @@ -1370,8 +1370,8 @@ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) */ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) { - if (i915_modparams.enable_fbc >= 0) - return !!i915_modparams.enable_fbc; + if (dev_priv->params.enable_fbc >= 0) + return !!dev_priv->params.enable_fbc; if (!HAS_FBC(dev_priv)) return 0; @@ -1415,9 +1415,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) if (need_fbc_vtd_wa(dev_priv)) mkwrite_device_info(dev_priv)->display.has_fbc = false; - i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv); + dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv); drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n", - i915_modparams.enable_fbc); + dev_priv->params.enable_fbc); if (!HAS_FBC(dev_priv)) { fbc->no_fbc_reason = "unsupported by this chipset"; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 872f2a489339..1888611244db 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -784,8 +784,8 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) struct drm_i915_private *dev_priv = to_i915(dev); /* use the module option value if specified */ - if (i915_modparams.lvds_channel_mode > 0) - return i915_modparams.lvds_channel_mode == 2; + if (dev_priv->params.lvds_channel_mode > 0) + return dev_priv->params.lvds_channel_mode == 2; /* single channel LVDS is limited to 112 MHz */ if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index cc6b00959586..de995362f428 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -801,7 +801,7 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; const struct firmware *fw = NULL; - const char *name = i915_modparams.vbt_firmware; + const char *name = dev_priv->params.vbt_firmware; int ret; if (!name || !*name) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 3c5056dbf607..aaed9eb3b56c 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -521,10 +521,10 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector, drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); - if (i915_modparams.invert_brightness < 0) + if (dev_priv->params.invert_brightness < 0) return val; - if (i915_modparams.invert_brightness > 0 || + if (dev_priv->params.invert_brightness > 0 || dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { return panel->backlight.max - val + panel->backlight.min; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ab380e6dc674..86bf7a76f93d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -83,7 +83,7 @@ static bool psr_global_enabled(struct drm_i915_private *i915) { switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { case I915_PSR_DEBUG_DEFAULT: - return i915_modparams.enable_psr; + return i915->params.enable_psr; case I915_PSR_DEBUG_DISABLE: return false; default: @@ -426,7 +426,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 11) val |= EDP_PSR_TP4_TIME_0US; - if (i915_modparams.psr_safest_params) { + if (dev_priv->params.psr_safest_params) { val |= EDP_PSR_TP1_TIME_2500us; val |= EDP_PSR_TP2_TP3_TIME_2500us; goto check_tp3_sel; @@ -507,7 +507,7 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u32 val = 0; - if (i915_modparams.psr_safest_params) + if (dev_priv->params.psr_safest_params) return EDP_PSR2_TP2_TIME_2500us; if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && @@ -1500,9 +1500,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv) */ dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP - _HSW_EDP_PSR_BASE; - if (i915_modparams.enable_psr == -1) + if (dev_priv->params.enable_psr == -1) if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) - i915_modparams.enable_psr = 0; + dev_priv->params.enable_psr = 0; /* Set link_standby x link_off defaults */ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 30c229fcb404..5c13809dc3c8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -650,7 +650,7 @@ static void context_close(struct i915_gem_context *ctx) * context close. */ if (!i915_gem_context_is_persistent(ctx) || - !i915_modparams.enable_hangcheck) + !ctx->i915->params.enable_hangcheck) kill_context(ctx); i915_gem_context_put(ctx); @@ -667,7 +667,7 @@ static int __context_set_persistence(struct i915_gem_context *ctx, bool state) * reset] are allowed to survive past termination. We require * hangcheck to ensure that the persistent requests are healthy. */ - if (!i915_modparams.enable_hangcheck) + if (!ctx->i915->params.enable_hangcheck) return -EINVAL; i915_gem_context_set_persistence(ctx); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c index cd20fb549b38..8db7e93abde5 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c @@ -4,6 +4,7 @@ * Copyright ? 2019 Intel Corporation */ +#include "i915_drv.h" #include "i915_request.h" #include "intel_context.h" @@ -133,7 +134,7 @@ static void heartbeat(struct work_struct *wrk) goto unlock; idle_pulse(engine, rq); - if (i915_modparams.enable_hangcheck) + if (engine->i915->params.enable_hangcheck) engine->heartbeat.systole = i915_request_get(rq); __i915_request_commit(rq); diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 39070b514e65..0156f1f5c736 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -638,7 +638,7 @@ int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask) bool intel_has_gpu_reset(const struct intel_gt *gt) { - if (!i915_modparams.reset) + if (!gt->i915->params.reset) return NULL; return intel_get_gpu_reset(gt); @@ -646,7 +646,7 @@ bool intel_has_gpu_reset(const struct intel_gt *gt) bool intel_has_reset_engine(const struct intel_gt *gt) { - if (i915_modparams.reset < 2) + if (gt->i915->params.reset < 2) return false; return INTEL_INFO(gt->i915)->has_reset_engine; @@ -1038,7 +1038,7 @@ void intel_gt_reset(struct intel_gt *gt, awake = reset_prepare(gt); if (!intel_has_gpu_reset(gt)) { - if (i915_modparams.reset) + if (gt->i915->params.reset) drm_err(>->i915->drm, "GPU reset not supported\n"); else drm_dbg(>->i915->drm, "GPU reset disabled\n"); diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c index f3034c613bc0..73243ba59c7d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c @@ -365,12 +365,12 @@ int intel_heartbeat_live_selftests(struct drm_i915_private *i915) if (intel_gt_is_wedged(&i915->gt)) return 0; - saved_hangcheck = i915_modparams.enable_hangcheck; - i915_modparams.enable_hangcheck = INT_MAX; + saved_hangcheck = i915->params.enable_hangcheck; + i915->params.enable_hangcheck = INT_MAX; err = intel_gt_live_subtests(tests, &i915->gt); - i915_modparams.enable_hangcheck = saved_hangcheck; + i915->params.enable_hangcheck = saved_hangcheck; return err; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c index fb10f3597ea5..9bbe8a795cb8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c @@ -424,25 +424,28 @@ static void guc_log_capture_logs(struct intel_guc_log *log) static u32 __get_default_log_level(struct intel_guc_log *log) { + struct intel_guc *guc = log_to_guc(log); + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + /* A negative value means "use platform/config default" */ - if (i915_modparams.guc_log_level < 0) { + if (i915->params.guc_log_level < 0) { return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) || IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ? GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_NON_VERBOSE; } - if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) { + if (i915->params.guc_log_level > GUC_LOG_LEVEL_MAX) { DRM_WARN("Incompatible option detected: %s=%d, %s!\n", - "guc_log_level", i915_modparams.guc_log_level, + "guc_log_level", i915->params.guc_log_level, "verbosity too high"); return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) || IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ? GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_DISABLED; } - GEM_BUG_ON(i915_modparams.guc_log_level < GUC_LOG_LEVEL_DISABLED); - GEM_BUG_ON(i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX); - return i915_modparams.guc_log_level; + GEM_BUG_ON(i915->params.guc_log_level < GUC_LOG_LEVEL_DISABLED); + GEM_BUG_ON(i915->params.guc_log_level > GUC_LOG_LEVEL_MAX); + return i915->params.guc_log_level; } int intel_guc_log_create(struct intel_guc_log *log) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 94eb63f309ce..fdfeb4b9b0f5 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -660,10 +660,12 @@ void intel_guc_submission_disable(struct intel_guc *guc) static bool __guc_submission_selected(struct intel_guc *guc) { + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + if (!intel_guc_submission_is_supported(guc)) return false; - return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION; + return i915->params.enable_guc & ENABLE_GUC_SUBMISSION; } void intel_guc_submission_init_early(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index f518fe05c6f9..1c2d6358826c 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -47,15 +47,15 @@ static void __confirm_options(struct intel_uc *uc) drm_dbg(&i915->drm, "enable_guc=%d (guc:%s submission:%s huc:%s)\n", - i915_modparams.enable_guc, + i915->params.enable_guc, yesno(intel_uc_wants_guc(uc)), yesno(intel_uc_wants_guc_submission(uc)), yesno(intel_uc_wants_huc(uc))); - if (i915_modparams.enable_guc == -1) + if (i915->params.enable_guc == -1) return; - if (i915_modparams.enable_guc == 0) { + if (i915->params.enable_guc == 0) { GEM_BUG_ON(intel_uc_wants_guc(uc)); GEM_BUG_ON(intel_uc_wants_guc_submission(uc)); GEM_BUG_ON(intel_uc_wants_huc(uc)); @@ -65,25 +65,25 @@ static void __confirm_options(struct intel_uc *uc) if (!intel_uc_supports_guc(uc)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "GuC is not supported!"); + i915->params.enable_guc, "GuC is not supported!"); - if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC && + if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC && !intel_uc_supports_huc(uc)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "HuC is not supported!"); + i915->params.enable_guc, "HuC is not supported!"); - if (i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION && + if (i915->params.enable_guc & ENABLE_GUC_SUBMISSION && !intel_uc_supports_guc_submission(uc)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "GuC submission is N/A"); + i915->params.enable_guc, "GuC submission is N/A"); - if (i915_modparams.enable_guc & ~(ENABLE_GUC_SUBMISSION | + if (i915->params.enable_guc & ~(ENABLE_GUC_SUBMISSION | ENABLE_GUC_LOAD_HUC)) drm_info(&i915->drm, "Incompatible option enable_guc=%d - %s\n", - i915_modparams.enable_guc, "undocumented flag"); + i915->params.enable_guc, "undocumented flag"); } void intel_uc_init_early(struct intel_uc *uc) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index e75be3999358..59b27aba15c6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -115,11 +115,13 @@ struct __packed uc_fw_platform_requirement { }, static void -__uc_fw_auto_select(struct intel_uc_fw *uc_fw, enum intel_platform p, u8 rev) +__uc_fw_auto_select(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) { static const struct uc_fw_platform_requirement fw_blobs[] = { INTEL_UC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, HUC_FW_BLOB) }; + enum intel_platform p = INTEL_INFO(i915)->platform; + u8 rev = INTEL_REVID(i915); int i; for (i = 0; i < ARRAY_SIZE(fw_blobs) && p <= fw_blobs[i].p; i++) { @@ -154,35 +156,35 @@ __uc_fw_auto_select(struct intel_uc_fw *uc_fw, enum intel_platform p, u8 rev) } /* We don't want to enable GuC/HuC on pre-Gen11 by default */ - if (i915_modparams.enable_guc == -1 && p < INTEL_ICELAKE) + if (i915->params.enable_guc == -1 && p < INTEL_ICELAKE) uc_fw->path = NULL; } -static const char *__override_guc_firmware_path(void) +static const char *__override_guc_firmware_path(struct drm_i915_private *i915) { - if (i915_modparams.enable_guc & (ENABLE_GUC_SUBMISSION | - ENABLE_GUC_LOAD_HUC)) - return i915_modparams.guc_firmware_path; + if (i915->params.enable_guc & (ENABLE_GUC_SUBMISSION | + ENABLE_GUC_LOAD_HUC)) + return i915->params.guc_firmware_path; return ""; } -static const char *__override_huc_firmware_path(void) +static const char *__override_huc_firmware_path(struct drm_i915_private *i915) { - if (i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC) - return i915_modparams.huc_firmware_path; + if (i915->params.enable_guc & ENABLE_GUC_LOAD_HUC) + return i915->params.huc_firmware_path; return ""; } -static void __uc_fw_user_override(struct intel_uc_fw *uc_fw) +static void __uc_fw_user_override(struct drm_i915_private *i915, struct intel_uc_fw *uc_fw) { const char *path = NULL; switch (uc_fw->type) { case INTEL_UC_FW_TYPE_GUC: - path = __override_guc_firmware_path(); + path = __override_guc_firmware_path(i915); break; case INTEL_UC_FW_TYPE_HUC: - path = __override_huc_firmware_path(); + path = __override_huc_firmware_path(i915); break; } @@ -216,10 +218,8 @@ void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw, uc_fw->type = type; if (HAS_GT_UC(i915)) { - __uc_fw_auto_select(uc_fw, - INTEL_INFO(i915)->platform, - INTEL_REVID(i915)); - __uc_fw_user_override(uc_fw); + __uc_fw_auto_select(i915, uc_fw); + __uc_fw_user_override(i915, uc_fw); } intel_uc_fw_change_status(uc_fw, uc_fw->path ? *uc_fw->path ? diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index bca036ac6621..8594a8ef08ce 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -64,7 +64,7 @@ static int i915_capabilities(struct seq_file *m, void *data) intel_driver_caps_print(&i915->caps, &p); kernel_param_lock(THIS_MODULE); - i915_params_dump(&i915_modparams, &p); + i915_params_dump(&i915->params, &p); kernel_param_unlock(THIS_MODULE); return 0; diff --git a/drivers/gpu/drm/i915/i915_debugfs_params.c b/drivers/gpu/drm/i915/i915_debugfs_params.c index 62b2c5f0495d..4e2b077692cb 100644 --- a/drivers/gpu/drm/i915/i915_debugfs_params.c +++ b/drivers/gpu/drm/i915/i915_debugfs_params.c @@ -138,9 +138,6 @@ static ssize_t i915_param_charp_write(struct file *file, char **s = m->private; char *new, *old; - /* FIXME: remove locking after params aren't the module params */ - kernel_param_lock(THIS_MODULE); - old = *s; new = strndup_user(ubuf, PAGE_SIZE); if (IS_ERR(new)) { @@ -152,8 +149,6 @@ static ssize_t i915_param_charp_write(struct file *file, kfree(old); out: - kernel_param_unlock(THIS_MODULE); - return len; } @@ -229,7 +224,7 @@ _i915_param_create_file(struct dentry *parent, const char *name, struct dentry *i915_debugfs_params(struct drm_i915_private *i915) { struct drm_minor *minor = i915->drm.primary; - struct i915_params *params = &i915_modparams; + struct i915_params *params = &i915->params; struct dentry *dir; dir = debugfs_create_dir("i915_params", minor->debugfs_root); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 34ee12f3f02d..67102dc26fce 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -501,6 +501,8 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv) cpu_latency_qos_remove_request(&dev_priv->sb_qos); mutex_destroy(&dev_priv->sb_lock); + + i915_params_free(&dev_priv->params); } /** @@ -915,6 +917,9 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) i915->drm.pdev = pdev; pci_set_drvdata(pdev, i915); + /* Device parameters start as a copy of module parameters. */ + i915_params_copy(&i915->params, &i915_modparams); + /* Setup the write-once "constant" device info */ device_info = mkwrite_device_info(i915); memcpy(device_info, match_info, sizeof(*device_info)); @@ -948,7 +953,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return PTR_ERR(i915); /* Disable nuclear pageflip by default on pre-ILK */ - if (!i915_modparams.nuclear_pageflip && match_info->gen < 5) + if (!i915->params.nuclear_pageflip && match_info->gen < 5) i915->drm.driver_features &= ~DRIVER_ATOMIC; /* @@ -958,7 +963,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) { if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 && - i915_modparams.fake_lmem_start) { + i915->params.fake_lmem_start) { mkwrite_device_info(i915)->memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN; mkwrite_device_info(i915)->is_dgfx = true; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..9aad3ec979bd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -830,6 +830,9 @@ struct drm_i915_private { /* FIXME: Device release actions should all be moved to drmm_ */ bool do_release; + /* i915 device parameters */ + struct i915_params params; + const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ struct intel_driver_caps caps; @@ -1691,7 +1694,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, /* Only valid when HAS_DISPLAY() is true */ #define INTEL_DISPLAY_ENABLED(dev_priv) \ - (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) + (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) static inline bool intel_vtd_active(void) { diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index d042644b9cd2..40390b2352b1 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -80,7 +80,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, return -ENODEV; break; case I915_PARAM_HAS_GPU_RESET: - value = i915_modparams.enable_hangcheck && + value = i915->params.enable_hangcheck && intel_has_gpu_reset(&i915->gt); if (value && intel_has_reset_engine(&i915->gt)) value = 2; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index eec292d06f11..866166ada10e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1698,7 +1698,7 @@ static void capture_gen(struct i915_gpu_coredump *error) error->reset_count = i915_reset_count(&i915->gpu_error); error->suspend_count = i915->suspend_count; - i915_params_copy(&error->params, &i915_modparams); + i915_params_copy(&error->params, &i915->params); memcpy(&error->device_info, INTEL_INFO(i915), sizeof(error->device_info)); @@ -1713,7 +1713,7 @@ i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) { struct i915_gpu_coredump *error; - if (!i915_modparams.error_capture) + if (!i915->params.error_capture) return NULL; error = kzalloc(sizeof(*error), gfp); diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index dd8981340d6e..99fe8aef1c67 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -66,7 +66,7 @@ static bool is_supported_device(struct drm_i915_private *dev_priv) */ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv) { - if (!i915_modparams.enable_gvt) + if (!dev_priv->params.enable_gvt) return; if (intel_vgpu_active(dev_priv)) { @@ -82,7 +82,7 @@ void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv) return; bail: - i915_modparams.enable_gvt = 0; + dev_priv->params.enable_gvt = 0; } /** @@ -102,7 +102,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) if (i915_inject_probe_failure(dev_priv)) return -ENODEV; - if (!i915_modparams.enable_gvt) { + if (!dev_priv->params.enable_gvt) { drm_dbg(&dev_priv->drm, "GVT-g is disabled by kernel params\n"); return 0; @@ -123,7 +123,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; bail: - i915_modparams.enable_gvt = 0; + dev_priv->params.enable_gvt = 0; return 0; } diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c index 14b59b899c9b..40d8f1a95df6 100644 --- a/drivers/gpu/drm/i915/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/intel_region_lmem.c @@ -76,7 +76,7 @@ region_lmem_init(struct intel_memory_region *mem) { int ret; - if (i915_modparams.fake_lmem_start) { + if (mem->i915->params.fake_lmem_start) { ret = init_fake_lmem_bar(mem); GEM_BUG_ON(ret); } @@ -111,12 +111,12 @@ intel_setup_fake_lmem(struct drm_i915_private *i915) resource_size_t start; GEM_BUG_ON(i915_ggtt_has_aperture(&i915->ggtt)); - GEM_BUG_ON(!i915_modparams.fake_lmem_start); + GEM_BUG_ON(!i915->params.fake_lmem_start); /* Your mappable aperture belongs to me now! */ mappable_end = pci_resource_len(pdev, 2); io_start = pci_resource_start(pdev, 2), - start = i915_modparams.fake_lmem_start; + start = i915->params.fake_lmem_start; mem = intel_memory_region_create(i915, start, diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 7d6b9ae7403c..592364aed2da 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1185,7 +1185,7 @@ __unclaimed_reg_debug(struct intel_uncore *uncore, read ? "read from" : "write to", i915_mmio_reg_offset(reg))) /* Only report the first N failures */ - i915_modparams.mmio_debug--; + uncore->i915->params.mmio_debug--; } static inline void @@ -1194,7 +1194,7 @@ unclaimed_reg_debug(struct intel_uncore *uncore, const bool read, const bool before) { - if (likely(!i915_modparams.mmio_debug)) + if (likely(!uncore->i915->params.mmio_debug)) return; /* interrupts are disabled and re-enabled around uncore->lock usage */ @@ -2093,12 +2093,12 @@ intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) goto out; if (unlikely(check_for_unclaimed_mmio(uncore))) { - if (!i915_modparams.mmio_debug) { + if (!uncore->i915->params.mmio_debug) { drm_dbg(&uncore->i915->drm, "Unclaimed register detected, " "enabling oneshot unclaimed register reporting. " "Please use i915.mmio_debug=N for more information.\n"); - i915_modparams.mmio_debug++; + uncore->i915->params.mmio_debug++; } uncore->debug->unclaimed_mmio_check--; ret = true; -- 2.20.1 From patchwork at emeril.freedesktop.org Thu Jun 18 15:09:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 15:09:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_co?= =?utf-8?q?mpleted_requests_on_unwind_=28rev7=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159249296821.22459.12208926070705506788@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev7) URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim checkpatch origin/drm-tip 97832ef83a00 drm/i915/gt: Decouple completed requests on unwind 11c6d2df5262 drm/i915/gt: Check for a completed last request once e40dd82b6f76 drm/i915/gt: Replace direct submit with direct call to tasklet 864f39b155c8 drm/i915/execlists: Defer schedule_out until after the next dequeue 1ede78bf8834 drm/i915/gt: ce->inflight updates are now serialised a22d22c0a3fe drm/i915/gt: Drop atomic for engine->fw_active tracking f78897462980 drm/i915/gt: Extract busy-stats for ring-scheduler -:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #12: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 95 lines checked c8c2a7c5b398 drm/i915/gt: Convert stats.active to plain unsigned int 8f1962dcb6c6 drm/i915/gt: Use virtual_engine during execlists_dequeue e1646a762cf5 drm/i915/gt: Decouple inflight virtual engines ae7db00042bf drm/i915/gt: Resubmit the virtual engine on schedule-out From patchwork at emeril.freedesktop.org Thu Jun 18 15:10:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 15:10:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_comple?= =?utf-8?q?ted_requests_on_unwind_=28rev7=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159249304292.22462.10027378099667614261@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev7) URL : https://patchwork.freedesktop.org/series/78522/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_reset.c:1325:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Thu Jun 18 15:25:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 15:25:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/query=3A_Use_struct=5Fsize=28=29_helper?= In-Reply-To: <20200617220331.GA19550@embeddedor> References: <20200617220331.GA19550@embeddedor> Message-ID: <159249395367.22461.13597971041966480149@emeril.freedesktop.org> == Series Details == Series: drm/i915/query: Use struct_size() helper URL : https://patchwork.freedesktop.org/series/78527/ State : success == Summary == CI Bug Log - changes from CI_DRM_8641_full -> Patchwork_17989_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17989_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd: - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl8/igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd.html * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-snb1/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_whisper@basic-fds: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk9/igt at gem_exec_whisper@basic-fds.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-glk7/igt at gem_exec_whisper@basic-fds.html * igt at gem_exec_whisper@basic-fds-priority-all: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +4 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at gem_exec_whisper@basic-fds-priority-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-kbl4/igt at gem_exec_whisper@basic-fds-priority-all.html * igt at gem_shrink@reclaim: - shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-hsw8/igt at gem_shrink@reclaim.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-hsw2/igt at gem_shrink@reclaim.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb2/igt at i915_module_load@reload-with-fault-injection.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_backlight@fade_with_suspend: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#69]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at i915_pm_backlight@fade_with_suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl5/igt at i915_pm_backlight@fade_with_suspend.html * igt at kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +10 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl5/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk2/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-max: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#168]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_color@pipe-c-ctm-max.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl3/igt at kms_color@pipe-c-ctm-max.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding: - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +22 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-apl4/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html * igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#54]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl5/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk9/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html * igt at kms_flip@2x-flip-vs-dpms-off-vs-modeset at ab-vga1-hdmi-a1: - shard-hsw: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-hsw1/igt at kms_flip@2x-flip-vs-dpms-off-vs-modeset at ab-vga1-hdmi-a1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-hsw6/igt at kms_flip@2x-flip-vs-dpms-off-vs-modeset at ab-vga1-hdmi-a1.html * igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at ab-hdmi-a1-hdmi-a2: - shard-glk: [PASS][29] -> [FAIL][30] ([i915#1928]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk4/igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at ab-hdmi-a1-hdmi-a2.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-glk4/igt at kms_flip@2x-plain-flip-fb-recreate-interruptible at ab-hdmi-a1-hdmi-a2.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt: - shard-skl: [PASS][33] -> [FAIL][34] ([i915#49]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][37] -> [FAIL][38] ([fdo#108145] / [i915#265]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_primary_render: - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb2/igt at kms_psr@psr2_primary_render.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-iclb1/igt at kms_psr@psr2_primary_render.html * igt at kms_setmode@basic: - shard-apl: [PASS][41] -> [FAIL][42] ([i915#31]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_setmode@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-apl2/igt at kms_setmode@basic.html #### Possible fixes #### * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [INCOMPLETE][43] ([i915#82]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-contexts-all: - shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk7/igt at gem_exec_whisper@basic-contexts-all.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-glk2/igt at gem_exec_whisper@basic-contexts-all.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][47] ([i915#402]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb3/igt at i915_module_load@reload.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_addfb_basic@bad-pitch-128: - shard-snb: [TIMEOUT][49] ([i915#1958]) -> [PASS][50] +4 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb1/igt at kms_addfb_basic@bad-pitch-128.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-snb6/igt at kms_addfb_basic@bad-pitch-128.html * {igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a}: - shard-glk: [INCOMPLETE][51] ([i915#58] / [k.org#198133]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk8/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-glk5/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_color@pipe-a-ctm-0-5.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl8/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding: - shard-apl: [FAIL][55] ([i915#54]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [DMESG-FAIL][57] ([i915#1982] / [i915#79]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +13 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][61] ([i915#95]) -> [PASS][62] +19 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl6/igt at kms_flip_tiling@flip-x-tiled.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-apl8/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-iclb4/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][67] ([i915#1188]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][69] ([fdo#108145] / [i915#265]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][71] ([fdo#109642] / [fdo#111068]) -> [PASS][72] +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb1/igt at kms_psr2_su@frontbuffer.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][73] ([i915#173]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb1/igt at kms_psr@no_drrs.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-iclb2/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb1/igt at kms_psr@psr2_cursor_render.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][77] ([i915#31]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl6/igt at kms_setmode@basic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-kbl2/igt at kms_setmode@basic.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][79] ([i915#1958]) -> [FAIL][80] ([i915#1930]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-snb6/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][81] ([i915#468]) -> [FAIL][82] ([i915#1899]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-tglb1/igt at i915_pm_dc@dc6-psr.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#168]: https://gitlab.freedesktop.org/drm/intel/issues/168 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17989 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17989: 65c25dcbbb056a8f4e88cea8fca087e524b349d5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17989/index.html From patchwork at emeril.freedesktop.org Thu Jun 18 15:31:09 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 15:31:09 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/11=5D_drm/i915/gt=3A_Decouple_completed?= =?utf-8?q?_requests_on_unwind_=28rev7=29?= In-Reply-To: <20200618100356.15744-1-chris@chris-wilson.co.uk> References: <20200618100356.15744-1-chris@chris-wilson.co.uk> Message-ID: <159249426900.22462.15763575603967618248@emeril.freedesktop.org> == Series Details == Series: series starting with [01/11] drm/i915/gt: Decouple completed requests on unwind (rev7) URL : https://patchwork.freedesktop.org/series/78522/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8641 -> Patchwork_17990 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17990 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17990, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17990: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - fi-tgl-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-tgl-u2/igt at i915_selftest@live at execlists.html * igt at i915_selftest@live at hugepages: - fi-cfl-8700k: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cfl-8700k/igt at i915_selftest@live at hugepages.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-cfl-8700k/igt at i915_selftest@live at hugepages.html - fi-kbl-x1275: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at i915_selftest@live at hugepages.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-kbl-x1275/igt at i915_selftest@live at hugepages.html * igt at i915_selftest@live at reset: - fi-cml-s: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-cml-s/igt at i915_selftest@live at reset.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-cml-s/igt at i915_selftest@live at reset.html Known issues ------------ Here are the changes found in Patchwork_17990 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][9] -> [FAIL][10] ([i915#1888]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-kbl-soraka: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-soraka/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-kbl-soraka/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][17] ([i915#1888]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_module_load@reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-modeset at d-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][26] ([i915#62] / [i915#92]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 37) ------------------------------ Missing (12): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-skl-lmem fi-bdw-samus fi-byt-clapper fi-skl-6700k2 fi-kbl-r Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17990 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17990: ae7db00042bfa8f4a1db938ca90ce7136251c75d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ae7db00042bf drm/i915/gt: Resubmit the virtual engine on schedule-out e1646a762cf5 drm/i915/gt: Decouple inflight virtual engines 8f1962dcb6c6 drm/i915/gt: Use virtual_engine during execlists_dequeue c8c2a7c5b398 drm/i915/gt: Convert stats.active to plain unsigned int f78897462980 drm/i915/gt: Extract busy-stats for ring-scheduler a22d22c0a3fe drm/i915/gt: Drop atomic for engine->fw_active tracking 1ede78bf8834 drm/i915/gt: ce->inflight updates are now serialised 864f39b155c8 drm/i915/execlists: Defer schedule_out until after the next dequeue e40dd82b6f76 drm/i915/gt: Replace direct submit with direct call to tasklet 11c6d2df5262 drm/i915/gt: Check for a completed last request once 97832ef83a00 drm/i915/gt: Decouple completed requests on unwind == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17990/index.html From aditya.swarup at intel.com Thu Jun 18 15:37:01 2020 From: aditya.swarup at intel.com (Aditya Swarup) Date: Thu, 18 Jun 2020 08:37:01 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Apply Wa_14011264657:gen11+ In-Reply-To: <20200616173407.GI6112@intel.com> References: <20200616163406.27387-1-matthew.s.atwood@intel.com> <20200616173407.GI6112@intel.com> Message-ID: <dda1bdbb-e661-cccd-44b2-c52fc6dc32d1@intel.com> On 6/16/20 10:34 AM, Ville Syrj?l? wrote: > On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote: >> Add minimum width to planes, variable with specific formats, for gen11+. >> >> Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_display.c | 55 +++++++++++++++++--- >> 1 file changed, 47 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> index 7457813ef273..d4fdad6cb3b1 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_display.c >> @@ -3760,6 +3760,45 @@ static int glk_max_plane_width(const struct drm_framebuffer *fb, >> } >> } >> >> +static int icl_min_plane_width(struct drm_i915_private *dev_priv, >> + const struct drm_framebuffer *fb) >> +{ >> + /* Wa_14011264657, Wa_14011050563 */ >> + switch (fb->format->format) { >> + case DRM_FORMAT_C8: >> + return 18; >> + case DRM_FORMAT_RGB565: >> + return 10; >> + case DRM_FORMAT_XRGB8888: >> + case DRM_FORMAT_XBGR8888: >> + case DRM_FORMAT_ARGB8888: >> + case DRM_FORMAT_ABGR8888: >> + case DRM_FORMAT_XRGB2101010: >> + case DRM_FORMAT_XBGR2101010: >> + case DRM_FORMAT_ARGB2101010: >> + case DRM_FORMAT_ABGR2101010: >> + case DRM_FORMAT_XVYU2101010: >> + case DRM_FORMAT_Y212: >> + case DRM_FORMAT_Y216: >> + return 6; >> + case DRM_FORMAT_NV12: >> + return 20; >> + case DRM_FORMAT_P010: >> + case DRM_FORMAT_P012: >> + case DRM_FORMAT_P016: >> + return 12; >> + case DRM_FORMAT_XRGB16161616F: >> + case DRM_FORMAT_XBGR16161616F: >> + case DRM_FORMAT_ARGB16161616F: >> + case DRM_FORMAT_ABGR16161616F: >> + case DRM_FORMAT_XVYU12_16161616: >> + case DRM_FORMAT_XVYU16161616: >> + return 4; >> + default: >> + return 1; >> + } > > if (semiplanar) { > switch (cpp[0]) { > case 1: > return 20; > case 2: > return 12; > } > } else { > switch (cpp[0]) { > case 1: > return 18; > case 2: > return 10; > case 4: > return 6; > case 8: > return 4; > } > } > > Actually if we fully reverse engineer this we are left with just: > if (semiplanar) > return 16/cpp[0] + 4; > else > return 16/cpp[0] + 2; > > I'd much prefer calculating this since then it's fully divorced from > defining new pixel formats. Can we get a confirmation from the hw > folks if that is in fact the formula (or if there's a different formula > how they came up with these magic numbers)? > >> +} >> + >> static int icl_max_plane_width(const struct drm_framebuffer *fb, >> int color_plane, >> unsigned int rotation) >> @@ -3831,15 +3870,15 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) >> int y = plane_state->uapi.src.y1 >> 16; >> int w = drm_rect_width(&plane_state->uapi.src) >> 16; >> int h = drm_rect_height(&plane_state->uapi.src) >> 16; >> - int max_width; >> - int max_height; >> - u32 alignment; >> - u32 offset; >> + int max_width, min_width = 1, max_height; >> + u32 alignment, offset; >> int aux_plane = intel_main_to_aux_plane(fb, 0); >> u32 aux_offset = plane_state->color_plane[aux_plane].offset; >> >> - if (INTEL_GEN(dev_priv) >= 11) >> + if (INTEL_GEN(dev_priv) >= 11) { >> max_width = icl_max_plane_width(fb, 0, rotation); >> + min_width = icl_min_plane_width(dev_priv, fb); To add to Ville's comments, there is no need for dev_priv and while we are at it, I don't understand the significance of passing parameters rotation if we are not going to use it? Aditya >> + } >> else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > Missing curly braces on all the branches. Feels like dejavu... > > I'd also do the min_width=1 assignment in each branch to make it > clear what's what. > >> max_width = glk_max_plane_width(fb, 0, rotation); >> else >> @@ -3850,10 +3889,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) >> else >> max_height = skl_max_plane_height(); >> >> - if (w > max_width || h > max_height) { >> + if (w > max_width || w < min_width || h > max_height) { >> drm_dbg_kms(&dev_priv->drm, >> - "requested Y/RGB source size %dx%d too big (limit %dx%d)\n", >> - w, h, max_width, max_height); >> + "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", >> + w, h, min_width, max_width, max_height); >> return -EINVAL; >> } >> >> -- >> 2.21.3 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > From m.szyprowski at samsung.com Thu Jun 18 15:39:30 2020 From: m.szyprowski at samsung.com (Marek Szyprowski) Date: Thu, 18 Jun 2020 17:39:30 +0200 Subject: [Intel-gfx] [PATCH v6 09/36] drm: i915: fix common struct sg_table related issues In-Reply-To: <20200618153956.29558-1-m.szyprowski@samsung.com> References: <20200618153956.29558-1-m.szyprowski@samsung.com> <CGME20200618154020eucas1p2b1cc0b386396bd09b735cc9d06906082@eucas1p2.samsung.com> Message-ID: <20200618153956.29558-10-m.szyprowski@samsung.com> The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function returns the number of the created entries in the DMA address space. However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and dma_unmap_sg must be called with the original number of the entries passed to the dma_map_sg(). struct sg_table is a common structure used for describing a non-contiguous memory buffer, used commonly in the DRM and graphics subsystems. It consists of a scatterlist with memory pages and DMA addresses (sgl entry), as well as the number of scatterlist entries: CPU pages (orig_nents entry) and DMA mapped pages (nents entry). It turned out that it was a common mistake to misuse nents and orig_nents entries, calling DMA-mapping functions with a wrong number of entries or ignoring the number of mapped entries returned by the dma_map_sg() function. This driver creatively uses sg_table->orig_nents to store the size of the allocated scatterlist and ignores the number of the entries returned by dma_map_sg function. The sg_table->orig_nents is (mis)used to properly free the (over)allocated scatterlist. This patch only introduces the common DMA-mapping wrappers operating directly on the struct sg_table objects to the dmabuf related functions, so the other drivers, which might share buffers with i915 could rely on the properly set nents and orig_nents values. Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com> --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 11 +++-------- drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c | 7 +++---- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 2679380159fc..8a988592715b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -48,12 +48,9 @@ static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attachme src = sg_next(src); } - if (!dma_map_sg_attrs(attachment->dev, - st->sgl, st->nents, dir, - DMA_ATTR_SKIP_CPU_SYNC)) { - ret = -ENOMEM; + ret = dma_map_sgtable(attachment->dev, st, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) goto err_free_sg; - } return st; @@ -73,9 +70,7 @@ static void i915_gem_unmap_dma_buf(struct dma_buf_attachment *attachment, { struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf); - dma_unmap_sg_attrs(attachment->dev, - sg->sgl, sg->nents, dir, - DMA_ATTR_SKIP_CPU_SYNC); + dma_unmap_sgtable(attachment->dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); sg_free_table(sg); kfree(sg); diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c index debaf7b18ab5..be30b27e2926 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c @@ -28,10 +28,9 @@ static struct sg_table *mock_map_dma_buf(struct dma_buf_attachment *attachment, sg = sg_next(sg); } - if (!dma_map_sg(attachment->dev, st->sgl, st->nents, dir)) { - err = -ENOMEM; + err = dma_map_sgtable(attachment->dev, st, dir, 0); + if (err) goto err_st; - } return st; @@ -46,7 +45,7 @@ static void mock_unmap_dma_buf(struct dma_buf_attachment *attachment, struct sg_table *st, enum dma_data_direction dir) { - dma_unmap_sg(attachment->dev, st->sgl, st->nents, dir); + dma_unmap_sgtable(attachment->dev, st, dir, 0); sg_free_table(st); kfree(st); } -- 2.17.1 From patchwork at emeril.freedesktop.org Thu Jun 18 16:17:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 16:17:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_switch_to_device_specific_parameters_=28rev2=29?= In-Reply-To: <20200618150402.14022-1-jani.nikula@intel.com> References: <20200618150402.14022-1-jani.nikula@intel.com> Message-ID: <159249707832.22459.7012213239537543300@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: switch to device specific parameters (rev2) URL : https://patchwork.freedesktop.org/series/78004/ State : success == Summary == CI Bug Log - changes from CI_DRM_8641 -> Patchwork_17991 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/index.html Known issues ------------ Here are the changes found in Patchwork_17991 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1242]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-modeset at d-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 36) ------------------------------ Missing (13): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-icl-y fi-skl-lmem fi-bdw-samus fi-byt-clapper fi-skl-6700k2 fi-kbl-r Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17991 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17991: e566ccf2edc78018c04fdbfd8bf29e8e8ed0b49c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e566ccf2edc7 drm/i915/params: switch to device specific parameters == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/index.html From patchwork at emeril.freedesktop.org Thu Jun 18 17:24:48 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 17:24:48 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_switch_to_device_specific_parameters_=28rev2=29?= In-Reply-To: <20200618150402.14022-1-jani.nikula@intel.com> References: <20200618150402.14022-1-jani.nikula@intel.com> Message-ID: <159250108898.22462.2290838479863621731@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: switch to device specific parameters (rev2) URL : https://patchwork.freedesktop.org/series/78004/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8641_full -> Patchwork_17991_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17991_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17991_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17991_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_balancer@bonded-early: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl7/igt at gem_exec_balancer@bonded-early.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl2/igt at gem_exec_balancer@bonded-early.html Known issues ------------ Here are the changes found in Patchwork_17991_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_schedule@implicit-read-write at rcs0: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-snb5/igt at gem_exec_schedule@implicit-read-write at rcs0.html * igt at gem_exec_whisper@basic-fds-priority-all: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at gem_exec_whisper@basic-fds-priority-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl4/igt at gem_exec_whisper@basic-fds-priority-all.html * igt at gem_mmap_gtt@medium-copy: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +9 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl7/igt at gem_mmap_gtt@medium-copy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl10/igt at gem_mmap_gtt@medium-copy.html * igt at gem_shrink@reclaim: - shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-hsw8/igt at gem_shrink@reclaim.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-hsw7/igt at gem_shrink@reclaim.html * igt at gem_softpin@noreloc-s3: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl1/igt at gem_softpin@noreloc-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl1/igt at gem_softpin@noreloc-s3.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk6/igt at kms_big_fb@linear-64bpp-rotate-0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk1/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-glk8/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-max: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#168]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_color@pipe-c-ctm-max.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl1/igt at kms_color@pipe-c-ctm-max.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#95]) +18 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-apl7/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html * igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl8/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html * igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ac-hdmi-a1-hdmi-a2: - shard-glk: [PASS][23] -> [FAIL][24] ([i915#79]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk4/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ac-hdmi-a1-hdmi-a2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-glk4/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at ac-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-suspend at b-edp1: - shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#198]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_flip@flip-vs-suspend at b-edp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl3/igt at kms_flip@flip-vs-suspend at b-edp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-hdmi-a1: - shard-glk: [PASS][27] -> [FAIL][28] ([i915#1928]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk5/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-hdmi-a1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-glk6/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-hdmi-a1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at c-dp1: - shard-kbl: [PASS][29] -> [FAIL][30] ([i915#1928]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl3/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-dp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl1/igt at kms_flip@plain-flip-fb-recreate-interruptible at c-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu: - shard-snb: [PASS][31] -> [SKIP][32] ([fdo#109271]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb5/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-snb6/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt: - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb2/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-tglb1/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][37] -> [INCOMPLETE][38] ([i915#123] / [i915#69]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl1/igt at kms_frontbuffer_tracking@psr-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl4/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][39] -> [FAIL][40] ([fdo#108145] / [i915#265]) +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_primary_render: - shard-iclb: [PASS][41] -> [SKIP][42] ([fdo#109441]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb2/igt at kms_psr@psr2_primary_render.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-iclb5/igt at kms_psr@psr2_primary_render.html * igt at kms_setmode@basic: - shard-apl: [PASS][43] -> [FAIL][44] ([i915#31]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_setmode@basic.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-apl4/igt at kms_setmode@basic.html #### Possible fixes #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][45] ([i915#1930]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [INCOMPLETE][47] ([i915#82]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb2/igt at gem_exec_schedule@implicit-write-read at rcs0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-snb1/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-contexts-all: - shard-glk: [DMESG-WARN][49] ([i915#118] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk7/igt at gem_exec_whisper@basic-contexts-all.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-glk8/igt at gem_exec_whisper@basic-contexts-all.html * {igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a}: - shard-glk: [INCOMPLETE][51] ([i915#58] / [k.org#198133]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk8/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-glk2/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding: - shard-apl: [FAIL][53] ([i915#54]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled: - shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +4 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [DMESG-FAIL][57] ([i915#1982] / [i915#79]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl3/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +13 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][61] ([i915#95]) -> [PASS][62] +20 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl6/igt at kms_flip_tiling@flip-x-tiled.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-apl2/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][67] ([i915#1188]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl8/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][69] ([fdo#108145] / [i915#265]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][71] ([fdo#109642] / [fdo#111068]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb6/igt at kms_psr2_su@page_flip.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][73] ([i915#173]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb1/igt at kms_psr@no_drrs.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-iclb5/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_page_flip: - shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb5/igt at kms_psr@psr2_primary_page_flip.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-iclb2/igt at kms_psr@psr2_primary_page_flip.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][77] ([i915#31]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl6/igt at kms_setmode@basic.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl6/igt at kms_setmode@basic.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][79] ([i915#1820] / [i915#93] / [i915#95]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][81] ([i915#454]) -> [SKIP][82] ([i915#468]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb8/igt at i915_pm_dc@dc6-dpms.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][83] ([i915#468]) -> [FAIL][84] ([i915#1899]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-tglb1/igt at i915_pm_dc@dc6-psr.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [DMESG-FAIL][85] ([i915#49] / [i915#95]) -> [FAIL][86] ([i915#49]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-apl4/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][87] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][88] ([i915#93] / [i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: [FAIL][89] ([i915#265]) -> [DMESG-FAIL][90] ([i915#95]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/shard-apl4/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#168]: https://gitlab.freedesktop.org/drm/intel/issues/168 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17991 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17991: e566ccf2edc78018c04fdbfd8bf29e8e8ed0b49c @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17991/index.html From sean at poorly.run Thu Jun 18 18:20:22 2020 From: sean at poorly.run (Sean Paul) Date: Thu, 18 Jun 2020 14:20:22 -0400 Subject: [Intel-gfx] [PATCH v6 16/16] drm/i915: Add HDCP 1.4 support for MST connectors In-Reply-To: <20200515144255.GA11877@intel.com> References: <20200429195502.39919-1-sean@poorly.run> <20200429195502.39919-17-sean@poorly.run> <20200515144255.GA11877@intel.com> Message-ID: <CAMavQK+GQD8xxTzzTP3SdPTWdViBvU=KVGeqBnwgEDeex=tGFA@mail.gmail.com> On Fri, May 15, 2020 at 10:43 AM Ramalingam C <ramalingam.c at intel.com> wrote: > > On 2020-04-29 at 15:55:02 -0400, Sean Paul wrote: > > From: Sean Paul <seanpaul at chromium.org> > > > > Now that all the groundwork has been laid, we can turn on HDCP 1.4 over > > MST. Everything except for toggling the HDCP signalling and HDCP 2.2 > > support is the same as the DP case, so we'll re-use those callbacks > > > > Cc: Juston Li <juston.li at intel.com> > > Signed-off-by: Sean Paul <seanpaul at chromium.org> > > Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-12-sean at poorly.run #v1 > > Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-13-sean at poorly.run #v2 > > Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-13-sean at poorly.run #v3 > > Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-15-sean at poorly.run #v4 > > Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-17-sean at poorly.run #v5 > > > > Changes in v2: > > -Toggle HDCP from encoder disable/enable > > -Don't disable HDCP on MST connector destroy, leave that for encoder > > disable, just ensure the check_work routine isn't running any longer > > Changes in v3: > > -Place the shim in the new intel_dp_hdcp.c file (Ville) > > Changes in v4: > > -Actually use the mst shim for mst connections (Juston) > > -Use QUERY_STREAM_ENC_STATUS MST message to verify channel is encrypted > > Changes in v5: > > -Add sleep on disable signalling to match hdmi delay > > Changes in v6: > > -Disable HDCP over MST on GEN12+ since I'm unsure how it should work and I > > don't have hardware to test it > > --- > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 107 ++++++++++++++++++- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++ > > 2 files changed, 124 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > index 4e3dafbea1f9..331fdb312e05 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > @@ -7,10 +7,12 @@ > > */ > > > > #include <drm/drm_dp_helper.h> > > +#include <drm/drm_dp_mst_helper.h> > > #include <drm/drm_hdcp.h> > > #include <drm/drm_print.h> > > > > #include "intel_display_types.h" > > +#include "intel_ddi.h" > > #include "intel_dp.h" > > #include "intel_hdcp.h" > > > > @@ -618,6 +620,106 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = { > > .protocol = HDCP_PROTOCOL_DP, > > }; > > > > +static int > > +intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, > > + enum transcoder cpu_transcoder, > > + bool enable) > > +{ > > + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > > + int ret; > > + > > + if (!enable) > > + usleep_range(6, 60); /* Bspec says >= 6us */ > > + > > + ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, > > + cpu_transcoder, enable); > Sean, > > The bit configured here is meant for HDMI and DVI only. Ignore for DP. > Thanks anshuman for pointing that out. The bspec says "Select HDCP for the desired stream using the Pipe DDI Function Control register." this is required to get stream level encryption (confirmed via the QUERY_STREAM_ENCRYPTION_STATUS sideband message). > > + if (ret) > > + drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n", > > + enable ? "Enable" : "Disable", ret); > > + return ret; > > +} \snip > > +static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { > > + .write_an_aksv = intel_dp_hdcp_write_an_aksv, > > + .read_bksv = intel_dp_hdcp_read_bksv, > > + .read_bstatus = intel_dp_hdcp_read_bstatus, > > + .repeater_present = intel_dp_hdcp_repeater_present, > > + .read_ri_prime = intel_dp_hdcp_read_ri_prime, > > + .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, > > + .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, > > + .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, > > + .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling, > > + .check_link = intel_dp_mst_hdcp_check_link, > > + .hdcp_capable = intel_dp_hdcp_capable, > > + > > + .write_2_2_msg = intel_dp_mst_hdcp2_write_msg, > > + .read_2_2_msg = intel_dp_mst_hdcp2_read_msg, > > + .config_stream_type = intel_dp_mst_hdcp2_config_stream_type, > > + .check_2_2_link = intel_dp_mst_hdcp2_check_link, > > + .hdcp_2_2_capable = intel_dp_mst_hdcp2_capable, > IMO, we dont need to introduce dummy functions for HDCP2.2 on MST shim, > when we are not enabling HDCP2.2 on it. > > At is_hdcp2_supported() just add > if (connector->mst_port) > return false; Ok, will do. > > + > > + .protocol = HDCP_PROTOCOL_DP, > > +}; > > + \snip > > + > > + /* Enable hdcp if it's desired */ > > + if (conn_state->content_protection == > > + DRM_MODE_CONTENT_PROTECTION_DESIRED) > > + intel_hdcp_enable(to_intel_connector(conn_state->connector), > > + pipe_config->cpu_transcoder, > > + (u8)conn_state->hdcp_content_type); > > I am afraid I am not seeing the stream level HDCP encryption set > anywhere. How the userspace will indicate the streams that needs to be > hdcp encrypted? > See above. Stream level encryption is achieved via the toggle_hdcp_signalling above (that's why it's needed). Sean > Thanks, > -Ram > > } > > > > static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, > > @@ -748,6 +758,14 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo > > intel_attach_force_audio_property(connector); > > intel_attach_broadcast_rgb_property(connector); > > > > + > > + /* TODO: Figure out how to make HDCP work on GEN12+ */ > > + if (INTEL_GEN(dev_priv) < 12) { > > + ret = intel_dp_init_hdcp(intel_dig_port, intel_connector); > > + if (ret) > > + DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); > > + } > > + > > /* > > * Reuse the prop from the SST connector because we're > > * not allowed to create new props after device registration. > > -- > > Sean Paul, Software Engineer, Google / Chromium OS > > From manasi.d.navare at intel.com Thu Jun 18 18:35:58 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 18 Jun 2020 11:35:58 -0700 Subject: [Intel-gfx] [PATCH v7 3/3] drm/i915/dp: Expose connector VRR monitor range via debugfs In-Reply-To: <CACvgo51j1BXN2ZyQ-m5AALup3ruoUHZhobSeNfS8QsV-UEjS-Q@mail.gmail.com> References: <20200612230444.10121-4-manasi.d.navare@intel.com> <20200612235606.25120-1-manasi.d.navare@intel.com> <CACvgo522mYhCRkNXuwJDCt2fh4-Piq9ZOH9rNbO+HrcbrytJgQ@mail.gmail.com> <20200615214809.GA4334@intel.com> <CACvgo51j1BXN2ZyQ-m5AALup3ruoUHZhobSeNfS8QsV-UEjS-Q@mail.gmail.com> Message-ID: <20200618183558.GA32149@intel.com> On Tue, Jun 16, 2020 at 04:34:07PM +0100, Emil Velikov wrote: > On Mon, 15 Jun 2020 at 22:47, Manasi Navare <manasi.d.navare at intel.com> wrote: > > > > On Mon, Jun 15, 2020 at 10:36:28PM +0100, Emil Velikov wrote: > > > Hi Manasi, > > > > > > On Sat, 13 Jun 2020 at 00:55, Manasi Navare <manasi.d.navare at intel.com> wrote: > > > > > > > > From: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > > > > > > > [Why] > > > > It's useful to know the min and max vrr range for IGT testing. > > > > > > > > [How] > > > > Expose the min and max vfreq for the connector via a debugfs file > > > > on the connector, "vrr_range". > > > > > > > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > > > > > > > v7: > > > > * Fix cmpilation due to rebase > > > > v6: > > > > * Rebase (manasi) > > > > v5: > > > > * Rename to vrr_range to match AMD debugfs > > > > v4: > > > > * Rebase > > > > v3: > > > > * Remove the unnecessary debug print (Manasi) > > > > v2: > > > > * Fix the typo in max_vfreq (Manasi) > > > > * Change the name of node to i915_vrr_info so we can add > > > > other vrr info for more debug info (Manasi) > > > > * Change the VRR capable to display Yes or No (Manasi) > > > > * Fix indentation checkpatch errors (Manasi) > > > > > > > Nit: generally revision log is listed in v2 -> v6 order. > > > > Okay point noted. Will update this in the next rev > > > > > > > > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Tested-by: Manasi Navare <manasi.d.navare at intel.com> > > > > --- > > > > .../drm/i915/display/intel_display_debugfs.c | 22 ++++++++++++++++++- > > > > 1 file changed, 21 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > index 28dd717e943a..2921f7d2a26e 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > > > > @@ -2185,6 +2185,21 @@ static const struct file_operations i915_dsc_fec_support_fops = { > > > > .write = i915_dsc_fec_support_write > > > > }; > > > > > > > > +static int vrr_range_show(struct seq_file *m, void *data) > > > > +{ > > > > + struct drm_connector *connector = m->private; > > > > + > > > > + if (connector->status != connector_status_connected) > > > > + return -ENODEV; > > > > + > > > > + seq_printf(m, "Vrr_capable: %s\n", yesno(intel_dp_is_vrr_capable(connector))); > > > > + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); > > > > + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); > > > > + > > > > + return 0; > > > > +} > > > > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > > > > + > > > > /** > > > > * intel_connector_debugfs_add - add i915 specific connector debugfs files > > > > * @connector: pointer to a registered drm_connector > > > > @@ -2220,10 +2235,15 @@ int intel_connector_debugfs_add(struct drm_connector *connector) > > > > if (INTEL_GEN(dev_priv) >= 10 && > > > > ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort && > > > > !to_intel_connector(connector)->mst_port) || > > > > - connector->connector_type == DRM_MODE_CONNECTOR_eDP)) > > > > + connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { > > > > debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, > > > > connector, &i915_dsc_fec_support_fops); > > > > > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > > + debugfs_create_file("vrr_range", S_IRUGO, > > > > + root, connector, &vrr_range_fops); > > > > + } > > > > + > > > > > > I think this should be added by core drm. Ideally drm will add it > > > automatically for each connector that the driver has called > > > drm_connector_attach_vrr_capable_property() upon. > > > > > > > But in this case drm_connector_attach_vrr_capable_property() is called by individual > > driver since its an optional connector property. So we call this inside i915. > > I'm _not_ suggesting that one moves the > drm_connector_attach_vrr_capable_property() call. Simply create the > debugfs file in drm itself. > > > Also currently AMD sets this debugfs inside AMD IMO, so setting this here for now. > Let's do the better thing of a) make drm create the file, and b) > remove the AMDGPU specific one. > > We're talking about 20-30 lines worth of a patch. Postponing it sounds silly. > > > But I agree that can be moved to drm core may be when drm_display_info gets populated > > with min and max, thats where drm can add this? > > > Both min and max are already part of drm_display_info. On the question > of how - check the existing properties (edid_override, force) for > examples. > Okay makes sense. Will move the vrr_range to drm debugfs node. Thanks for your feedback. Regards Manasi > -Emil From rodrigo.vivi at intel.com Thu Jun 18 20:27:00 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Thu, 18 Jun 2020 13:27:00 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Make Wa_14010229206 permanent Message-ID: <20200618202701.729-1-rodrigo.vivi@intel.com> From: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> commit 63d0f3ea8ebb67160eca281320d255c72b0cb51a upstream. This workaround now applies to all steppings, not just A0. Wa_1409085225 is a temporary A0-only W/A however it is identical to Wa_14010229206 and hence the combined workaround is made permanent. Bspec: 52890 Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> Tested-by: Rafael Antognolli <rafael.antognolli at intel.com> Reviewed-by: Matt Roper <matthew.d.roper at intel.com> [mattrope: added missing blank line] Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200326234955.16155-1-swathi.dhanavanthri at intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5176ad1a3976..092a42367851 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1379,12 +1379,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN7_FF_THREAD_MODE, GEN12_FF_TESSELATION_DOP_GATE_DISABLE); - /* - * Wa_1409085225:tgl - * Wa_14010229206:tgl - */ - wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); - /* Wa_1408615072:tgl */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); @@ -1402,6 +1396,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_masked_en(wal, GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE); + + /* + * Wa_1409085225:tgl + * Wa_14010229206:tgl + */ + wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); } if (IS_GEN(i915, 11)) { -- 2.24.1 From patchwork at emeril.freedesktop.org Thu Jun 18 20:42:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 20:42:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/tgl=3A_Make_Wa=5F14010229206_permanent_=28rev2=29?= In-Reply-To: <20200618202701.729-1-rodrigo.vivi@intel.com> References: <20200618202701.729-1-rodrigo.vivi@intel.com> Message-ID: <159251292077.22462.15409128357079448651@emeril.freedesktop.org> == Series Details == Series: drm/i915/tgl: Make Wa_14010229206 permanent (rev2) URL : https://patchwork.freedesktop.org/series/75139/ State : failure == Summary == Applying: drm/i915/tgl: Make Wa_14010229206 permanent Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_workarounds.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_workarounds.c No changes -- Patch already applied. From pavel at ucw.cz Thu Jun 18 21:29:42 2020 From: pavel at ucw.cz (Pavel Machek) Date: Thu, 18 Jun 2020 23:29:42 +0200 Subject: [Intel-gfx] next-20200618: oops in eb_relocate_vma in Xorg process, making machine unusable Message-ID: <20200618212942.GA3831@amd> Hi! On thinkpad X60 (x86-32): I got this: Had to reboot.... Best regards, Pavel Jun 18 23:16:28 amd kernel: BUG: unable to handle page fault for address: f8600000 Jun 18 23:16:28 amd kernel: #PF: supervisor write access in kernel mode Jun 18 23:16:28 amd kernel: #PF: error_code(0x0002) - not-present page Jun 18 23:16:28 amd kernel: *pdpt = 00000000319d7001 *pde = 0000000000000000 Jun 18 23:16:28 amd kernel: Oops: 0002 [#1] PREEMPT SMP PTI Jun 18 23:16:28 amd kernel: CPU: 0 PID: 2951 Comm: Xorg Not tainted 5.8.0-rc1-next-20200618+ #125 Jun 18 23:16:28 amd kernel: Hardware name: LENOVO 17097HU/17097HU, BIOS 7BETD8WW (2.19 ) 03/31/2011 Jun 18 23:16:28 amd kernel: EIP: eb_relocate_vma+0xdee/0xf50 Jun 18 23:16:28 amd kernel: Code: 85 c0 fd ff ff ed ff ff ff c7 85 c4 fd ff ff ff ff ff ff 8b 85 c0 fd ff ff e9 33 f7 ff ff 8d b6 00 00 00 00 8b 85 d0 fd ff ff <c7> 03 01 00 40 10 89 43 04 8b 85 dc fd ff ff 89 43 08 e9 2c f6 ff Jun 18 23:16:28 amd kernel: EAX: 003095c8 EBX: f8600000 ECX: 012c8000 EDX: 00000000 Jun 18 23:16:28 amd kernel: ESI: f1ad7cbc EDI: f1ad7b04 EBP: f1ad7c54 ESP: f1ad79ec Jun 18 23:16:28 amd kernel: DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210246 Jun 18 23:16:28 amd kernel: CR0: 80050033 CR2: f8600000 CR3: 31ada000 CR4: 000006b0 Jun 18 23:16:28 amd kernel: Call Trace: Jun 18 23:16:28 amd kernel: ? __lock_acquire.isra.0+0x223/0x500 Jun 18 23:16:28 amd kernel: i915_gem_do_execbuffer+0x9a1/0x2a70 Jun 18 23:16:28 amd kernel: ? intel_runtime_pm_put_unchecked+0xd/0x10 Jun 18 23:16:28 amd kernel: ? i915_gem_gtt_pwrite_fast+0xf6/0x520 Jun 18 23:16:28 amd kernel: ? __lock_acquire.isra.0+0x223/0x500 Jun 18 23:16:28 amd kernel: ? cache_alloc_debugcheck_after+0x151/0x180 Jun 18 23:16:28 amd kernel: ? kvmalloc_node+0x69/0x80 Jun 18 23:16:28 amd kernel: ? __kmalloc+0x92/0x120 Jun 18 23:16:28 amd kernel: ? kvmalloc_node+0x69/0x80 Jun 18 23:16:28 amd kernel: i915_gem_execbuffer2_ioctl+0x1b9/0x3a0 Jun 18 23:16:28 amd kernel: ? drm_dev_exit+0xb/0x40 Jun 18 23:16:28 amd kernel: ? i915_gem_execbuffer_ioctl+0x2a0/0x2a0 Jun 18 23:16:28 amd kernel: drm_ioctl_kernel+0x91/0xe0 Jun 18 23:16:28 amd kernel: ? i915_gem_execbuffer_ioctl+0x2a0/0x2a0 Jun 18 23:16:28 amd kernel: drm_ioctl+0x1fd/0x371 Jun 18 23:16:28 amd kernel: ? i915_gem_execbuffer_ioctl+0x2a0/0x2a0 Jun 18 23:16:28 amd kernel: ? posix_get_monotonic_timespec+0x1d/0x80 Jun 18 23:16:28 amd kernel: ? drm_ioctl_kernel+0xe0/0xe0 Jun 18 23:16:28 amd kernel: ksys_ioctl+0x143/0x7d0 Jun 18 23:16:28 amd kernel: ? ktime_get_ts64+0x77/0x1d0 Jun 18 23:16:28 amd kernel: ? _copy_to_user+0x21/0x30 Jun 18 23:16:28 amd kernel: ? __prepare_exit_to_usermode+0xe5/0x110 Jun 18 23:16:28 amd kernel: __ia32_sys_ioctl+0x10/0x12 Jun 18 23:16:28 amd kernel: do_syscall_32_irqs_on+0x3a/0xf0 Jun 18 23:16:28 amd kernel: do_int80_syscall_32+0x9/0x20 Jun 18 23:16:28 amd kernel: entry_INT80_32+0x116/0x116 Jun 18 23:16:28 amd kernel: EIP: 0xb7f1c092 Jun 18 23:16:28 amd kernel: Code: Bad RIP value. Jun 18 23:16:28 amd kernel: EAX: ffffffda EBX: 0000000a ECX: c0406469 EDX: bf97792c Jun 18 23:16:28 amd kernel: ESI: b730a000 EDI: c0406469 EBP: 0000000a ESP: bf9778a4 Jun 18 23:16:28 amd kernel: DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 007b EFLAGS: 00200292 Jun 18 23:16:28 amd kernel: ? asm_exc_nmi+0xcc/0x2bc Jun 18 23:16:28 amd kernel: Modules linked in: Jun 18 23:16:28 amd kernel: CR2: 00000000f8600000 Jun 18 23:16:28 amd kernel: ---[ end trace 216ff69b99738a0d ]--- Jun 18 23:16:28 amd kernel: EIP: eb_relocate_vma+0xdee/0xf50 Jun 18 23:16:28 amd kernel: Code: 85 c0 fd ff ff ed ff ff ff c7 85 c4 fd ff ff ff ff ff ff 8b 85 c0 fd ff ff e9 33 f7 ff ff 8d b6 00 00 00 00 8b 85 d0 fd ff ff <c7> 03 01 00 40 10 89 43 04 8b 85 dc fd ff ff 89 43 08 e9 2c f6 ff Jun 18 23:16:28 amd kernel: EAX: 003095c8 EBX: f8600000 ECX: 012c8000 EDX: 00000000 Jun 18 23:16:28 amd kernel: ESI: f1ad7cbc EDI: f1ad7b04 EBP: f1ad7c54 ESP: f1ad79ec Jun 18 23:16:28 amd kernel: DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210246 Jun 18 23:16:28 amd kernel: CR0: 80050033 CR2: f8600000 CR3: 31ada000 CR4: 000006b0 Jun 18 23:16:28 amd kernel: BUG: unable to handle page fault for address: f8602038 Jun 18 23:16:28 amd kernel: #PF: supervisor write access in kernel mode Jun 18 23:16:28 amd kernel: #PF: error_code(0x0002) - not-present page Jun 18 23:16:28 amd kernel: *pdpt = 000000002e39f001 *pde = 0000000000000000 Jun 18 23:16:28 amd kernel: Oops: 0002 [#2] PREEMPT SMP PTI Jun 18 23:16:28 amd kernel: CPU: 0 PID: 2951 Comm: Xorg Tainted: G D 5.8.0-rc1-next-20200618+ #125 Jun 18 23:16:28 amd kernel: Hardware name: LENOVO 17097HU/17097HU, BIOS 7BETD8WW (2.19 ) 03/31/2011 Jun 18 23:16:28 amd kernel: EIP: n_tty_open+0x26/0x80 Jun 18 23:16:28 amd kernel: Code: 00 00 00 90 55 89 e5 56 53 89 c3 b8 f0 22 00 00 e8 0f 6a cb ff 85 c0 74 62 89 c6 a1 00 cd 25 c5 b9 c8 66 6b c5 ba a9 3b 11 c5 <89> 46 38 8d 86 58 22 00 00 e8 9c 66 c0 ff 8d 86 a4 22 00 00 b9 c0 Jun 18 23:16:28 amd kernel: EAX: 00024042 EBX: f3e8dc00 ECX: c56b66c8 EDX: c5113ba9 Jun 18 23:16:28 amd kernel: ESI: f8602000 EDI: 00000000 EBP: f1ad7ee4 ESP: f1ad7edc Jun 18 23:16:28 amd kernel: DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210286 Jun 18 23:16:28 amd kernel: CR0: 80050033 CR2: f8602038 CR3: 2dd5c000 CR4: 000006b0 Jun 18 23:16:28 amd kernel: Call Trace: Jun 18 23:16:28 amd kernel: tty_ldisc_open.isra.0+0x23/0x40 Jun 18 23:16:28 amd kernel: tty_ldisc_reinit+0x99/0xe0 Jun 18 23:16:28 amd kernel: tty_ldisc_hangup+0xc4/0x1e0 Jun 18 23:16:28 amd kernel: __tty_hangup.part.0+0x13f/0x250 Jun 18 23:16:28 amd kernel: tty_vhangup_session+0x11/0x20 Jun 18 23:16:28 amd kernel: disassociate_ctty.part.0+0x34/0x230 Jun 18 23:16:28 amd kernel: disassociate_ctty+0x28/0x30 Jun 18 23:16:28 amd kernel: do_exit+0x466/0x980 Jun 18 23:16:28 amd kernel: ? __ia32_sys_ioctl+0x10/0x12 Jun 18 23:16:28 amd kernel: ? do_syscall_32_irqs_on+0x3a/0xf0 Jun 18 23:16:28 amd kernel: rewind_stack_do_exit+0x11/0x13 Jun 18 23:16:28 amd kernel: EIP: 0xb7f1c092 Jun 18 23:16:28 amd kernel: Code: Bad RIP value. Jun 18 23:16:28 amd kernel: EAX: ffffffda EBX: 0000000a ECX: c0406469 EDX: bf97792c Jun 18 23:16:28 amd kernel: ESI: b730a000 EDI: c0406469 EBP: 0000000a ESP: bf9778a4 Jun 18 23:16:28 amd kernel: DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 007b EFLAGS: 00200292 Jun 18 23:16:28 amd kernel: ? asm_exc_nmi+0xcc/0x2bc Jun 18 23:16:28 amd kernel: Modules linked in: Jun 18 23:16:28 amd kernel: CR2: 00000000f8602038 Jun 18 23:16:28 amd kernel: ---[ end trace 216ff69b99738a0e ]--- Jun 18 23:16:28 amd kernel: EIP: eb_relocate_vma+0xdee/0xf50 Jun 18 23:16:28 amd kernel: Code: 85 c0 fd ff ff ed ff ff ff c7 85 c4 fd ff ff ff ff ff ff 8b 85 c0 fd ff ff e9 33 f7 ff ff 8d b6 00 00 00 00 8b 85 d0 fd ff ff <c7> 03 01 00 40 10 89 43 04 8b 85 dc fd ff ff 89 43 08 e9 2c f6 ff Jun 18 23:16:28 amd kernel: EAX: 003095c8 EBX: f8600000 ECX: 012c8000 EDX: 00000000 Jun 18 23:16:28 amd kernel: ESI: f1ad7cbc EDI: f1ad7b04 EBP: f1ad7c54 ESP: f1ad79ec Jun 18 23:16:28 amd kernel: DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210246 Jun 18 23:16:28 amd kernel: CR0: 80050033 CR2: f8602038 CR3: 2dd5c000 CR4: 000006b0 Jun 18 23:16:28 amd kernel: Fixing recursive fault but reboot is needed! Jun 18 23:16:38 amd systemd[1]: Starting Cleanup of Temporary Directories... Jun 18 23:16:39 amd systemd[1]: Started Cleanup of Temporary Directories. -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 181 bytes Desc: Digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200618/059b66a7/attachment.sig> From patchwork at emeril.freedesktop.org Thu Jun 18 22:20:59 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 22:20:59 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_switch_to_device_specific_parameters_=28rev3=29?= In-Reply-To: <20200618150402.14022-1-jani.nikula@intel.com> References: <20200618150402.14022-1-jani.nikula@intel.com> Message-ID: <159251885921.22460.9003863693507960295@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: switch to device specific parameters (rev3) URL : https://patchwork.freedesktop.org/series/78004/ State : success == Summary == CI Bug Log - changes from CI_DRM_8641 -> Patchwork_17993 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/index.html Known issues ------------ Here are the changes found in Patchwork_17993 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_selftest@live at execlists: - fi-icl-y: [PASS][1] -> [INCOMPLETE][2] ([i915#1684]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-y/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-u2/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-modeset at d-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-modeset at d-dsi1.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][15] ([fdo#109271]) -> [DMESG-FAIL][16] ([i915#62] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1684]: https://gitlab.freedesktop.org/drm/intel/issues/1684 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 37) ------------------------------ Missing (12): fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-skl-lmem fi-bdw-samus fi-byt-clapper fi-skl-6700k2 fi-kbl-r Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17993 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17993: 7e653187560babd808318d160f9a3f8dcee515a8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7e653187560b drm/i915/params: switch to device specific parameters == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/index.html From manasi.d.navare at intel.com Thu Jun 18 23:23:03 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 18 Jun 2020 16:23:03 -0700 Subject: [Intel-gfx] [PATCH v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD In-Reply-To: <20200612230444.10121-2-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> <20200612230444.10121-2-manasi.d.navare@intel.com> Message-ID: <20200618232303.GB32149@intel.com> @Jani N, could you give an ACK on this if this looks okay, addressed your review comments regarding the name of the function. Else I have a r-b functionality wise so good to get merged? Regards Manasi On Fri, Jun 12, 2020 at 04:04:42PM -0700, Manasi Navare wrote: > DP sink device sets the Ignore MSA bit in its > DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to > ignore the MSA video timing parameters and its ability to support > seamless video timing change over a range of timing exposed by > DisplayID and EDID. > This is required for the sink to indicate that it is Adaptive sync > capable. > > v3: > * Fi the typo in commit message (Manasi) > v2: > * Rename to describe what the function does (Jani Nikula) > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Harry Wentland <harry.wentland at amd.com> > Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas at amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > Reviewed-by: Harry Wentland <harry.wentland at amd.com> > --- > include/drm/drm_dp_helper.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 1165ec105638..e47dc22ebf50 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > DP_ALTERNATE_SCRAMBLER_RESET_CAP; > } > > +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ > +static inline bool > +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +{ > + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & > + DP_MSA_TIMING_PAR_IGNORED; > +} > + > /* > * DisplayPort AUX channel > */ > -- > 2.19.1 > From patchwork at emeril.freedesktop.org Thu Jun 18 23:28:09 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Thu, 18 Jun 2020 23:28:09 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_switch_to_device_specific_parameters_=28rev3=29?= In-Reply-To: <20200618150402.14022-1-jani.nikula@intel.com> References: <20200618150402.14022-1-jani.nikula@intel.com> Message-ID: <159252288903.22460.5464398107550245782@emeril.freedesktop.org> == Series Details == Series: drm/i915/params: switch to device specific parameters (rev3) URL : https://patchwork.freedesktop.org/series/78004/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8641_full -> Patchwork_17993_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17993_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17993_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17993_full: ### IGT changes ### #### Possible regressions #### * igt at sysfs_heartbeat_interval@nopreempt at bcs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl4/igt at sysfs_heartbeat_interval@nopreempt at bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl3/igt at sysfs_heartbeat_interval@nopreempt at bcs0.html Known issues ------------ Here are the changes found in Patchwork_17993_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: - shard-kbl: [PASS][3] -> [FAIL][4] ([i915#1528]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl6/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html * igt at gem_exec_schedule@implicit-boths at rcs0: - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb5/igt at gem_exec_schedule@implicit-boths at rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-snb4/igt at gem_exec_schedule@implicit-boths at rcs0.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk1/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_exec_whisper@basic-fds-priority-all: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at gem_exec_whisper@basic-fds-priority-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at gem_exec_whisper@basic-fds-priority-all.html * igt at gem_mmap_gtt@medium-copy: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +11 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl7/igt at gem_mmap_gtt@medium-copy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl7/igt at gem_mmap_gtt@medium-copy.html * igt at gem_tiled_pread_pwrite: - shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb3/igt at gem_tiled_pread_pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb2/igt at gem_tiled_pread_pwrite.html * igt at kms_color@pipe-c-ctm-max: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#168]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_color@pipe-c-ctm-max.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl8/igt at kms_color@pipe-c-ctm-max.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#95]) +10 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-c-cursor-64x64-offscreen: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_cursor_crc@pipe-c-cursor-64x64-offscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-64x64-offscreen.html * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk9/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk8/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html * igt at kms_flip@dpms-vs-vblank-race-interruptible at c-hdmi-a1: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#407]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk5/igt at kms_flip@dpms-vs-vblank-race-interruptible at c-hdmi-a1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk6/igt at kms_flip@dpms-vs-vblank-race-interruptible at c-hdmi-a1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_cursor@pipe-c-primary-size-64: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#62]) +5 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl7/igt at kms_plane_cursor@pipe-c-primary-size-64.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_plane_cursor@pipe-c-primary-size-64.html * igt at kms_psr@psr2_primary_render: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb2/igt at kms_psr@psr2_primary_render.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb6/igt at kms_psr@psr2_primary_render.html * igt at kms_setmode@basic: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#31]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_setmode@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl3/igt at kms_setmode@basic.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-b: - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb5/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-tglb7/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html #### Possible fixes #### * igt at gem_exec_whisper@basic-contexts-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk7/igt at gem_exec_whisper@basic-contexts-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk5/igt at gem_exec_whisper@basic-contexts-all.html * {igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a}: - shard-glk: [INCOMPLETE][41] ([i915#58] / [k.org#198133]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk8/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk6/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding: - shard-apl: [FAIL][43] ([i915#54]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +1 similar issue [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl5/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl10/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +7 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip_tiling@flip-x-tiled: - shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +13 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl6/igt at kms_flip_tiling@flip-x-tiled.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl8/igt at kms_flip_tiling@flip-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb5/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl3/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][59] ([i915#173]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb1/igt at kms_psr@no_drrs.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb6/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb3/igt at kms_psr@psr2_cursor_blt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html #### Warnings #### * igt at gem_eio@execbuf: - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [DMESG-WARN][64] ([i915#62]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl7/igt at gem_eio@execbuf.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at gem_eio@execbuf.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#1899]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-tglb6/igt at i915_pm_dc@dc6-psr.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-kbl: [DMESG-WARN][67] ([i915#93] / [i915#95]) -> [DMESG-WARN][68] ([i915#180] / [i915#93] / [i915#95]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl6/igt at i915_suspend@fence-restore-tiled2untiled.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [DMESG-FAIL][69] ([i915#1982] / [i915#79]) -> [FAIL][70] ([i915#79]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][71] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][72] ([i915#93] / [i915#95]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_properties@crtc-properties-atomic: - shard-apl: [DMESG-WARN][73] ([i915#95]) -> [DMESG-FAIL][74] ([i915#62]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl7/igt at kms_properties@crtc-properties-atomic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_properties@crtc-properties-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#168]: https://gitlab.freedesktop.org/drm/intel/issues/168 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8641 -> Patchwork_17993 CI-20190529: 20190529 CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17993: 7e653187560babd808318d160f9a3f8dcee515a8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/index.html From daniel at ffwll.ch Fri Jun 19 07:22:09 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 19 Jun 2020 09:22:09 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200618172338.GM6578@ziepe.ca> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> <20200617152835.GF6578@ziepe.ca> <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> Message-ID: <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> On Fri, Jun 19, 2020 at 8:58 AM Jason Gunthorpe <jgg at ziepe.ca> wrote: > > On Thu, Jun 18, 2020 at 05:00:51PM +0200, Daniel Vetter wrote: > > On Wed, Jun 17, 2020 at 12:28:35PM -0300, Jason Gunthorpe wrote: > > > On Wed, Jun 17, 2020 at 08:48:50AM +0200, Daniel Vetter wrote: > > > > > > > Now my understanding for rdma is that if you don't have hw page fault > > > > support, > > > > > > The RDMA ODP feature is restartable HW page faulting just like nouveau > > > has. The classical MR feature doesn't have this. Only mlx5 HW supports > > > ODP today. > > > > > > > It's only gpus (I think) which are in this awkward in-between spot > > > > where dynamic memory management really is much wanted, but the hw > > > > kinda sucks. Aside, about 10+ years ago we had a similar problem with > > > > gpu hw, but for security: Many gpu didn't have any kinds of page > > > > tables to isolate different clients from each another. drivers/gpu > > > > fixed this by parsing&validating what userspace submitted to make sure > > > > it's only every accessing its own buffers. Most gpus have become > > > > reasonable nowadays and do have proper per-process pagetables (gpu > > > > process, not the pasid stuff), but even today there's still some of > > > > the old model left in some of the smallest SoC. > > > > > > But I still don't understand why a dma fence is needed inside the GPU > > > driver itself in the notifier. > > > > > > Surely the GPU driver can block and release the notifier directly from > > > its own command processing channel? > > > > > > Why does this fence and all it entails need to leak out across > > > drivers? > > > > So 10 years ago we had this world of every gpu driver is its own bucket, > > nothing leaks out to the world. But the world had a different idea how > > gpus where supposed to work, with stuff like: > > Sure, I understand DMA fence, but why does a *notifier* need it? > > The job of the notifier is to guarentee that the device it is > connected to is not doing DMA before it returns. > > That just means you need to prove that device is done with the buffer. > > As I've understood GPU that means you need to show that the commands > associated with the buffer have completed. This is all local stuff > within the driver, right? Why use fence (other than it already exists) Because that's the end-of-dma thing. And it's cross-driver for the above reasons, e.g. - device A renders some stuff. Userspace gets dma_fence A out of that (well sync_file or one of the other uapi interfaces, but you get the idea) - userspace (across process or just different driver) issues more rendering for device B, which depends upon the rendering done on device A. So dma_fence A is an dependency and will block this dma operation. Userspace (and the kernel) gets dma_fence B out of this - because unfortunate reasons, the same rendering on device B also needs a userptr buffer, which means that dma_fence B is also the one that the mmu_range_notifier needs to wait on before it can tell core mm that it can go ahead and release those pages - unhappiness ensues, because now the mmu notifier from device B can get hung up on the dma operation device A is doing If you want to avoid this either a) have less shitty hw (not an option, gpus are gpus, it is slowly getting better though) or b) force userspace to stall before handing over to next device (about as uncool) or c) just pin all the memory always, who cares (also rather unpopular, gpus tend to use all the memory they can get). I guess the thing with gpus is that dma operations aren't like read/writes for pretty much everything else, but essentially compute contexts (usually implemented as ringbuffers where you stream stuff into) with cross everything dependencies. This even holds within a single gpu, since pretty much all modern gpus have multiple different engines special on different things. And yup that's directly exposed to userspace, for vulkan and other low-level gpu apis even directly to applications. So dma operation for gpu isn't just "done when the read/write finishes", but pulls in an entire chain of dependencies and ordering that needs to happen before it can even start. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From chris at chris-wilson.co.uk Fri Jun 19 08:25:11 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 09:25:11 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> Message-ID: <159255511144.7737.12635440776531222029@build.alporthouse.com> Quoting Daniel Stone (2020-06-11 10:01:46) > Hi, > > On Thu, 11 Jun 2020 at 09:44, Dave Airlie <airlied at gmail.com> wrote: > > On Thu, 11 Jun 2020 at 18:01, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > Introducing a global lockmap that cannot capture the rules correctly, > > > > Can you document the rules all drivers should be following then, > > because from here it looks to get refactored every version of i915, > > and it would be nice if we could all aim for the same set of things > > roughly. We've already had enough problems with amdgpu vs i915 vs > > everyone else with fences, if this stops that in the future then I'd > > rather we have that than just some unwritten rules per driver and > > untestable. > > As someone who has sunk a bunch of work into explicit-fencing > awareness in my compositor so I can never be blocked, I'd be > disappointed if the infrastructure was ultimately pointless because > the documented fencing rules were \_o_/ or thereabouts. Lockdep > definitely isn't my area of expertise so I can't comment on the patch > per se, but having something to ensure we don't hit deadlocks sure > seems a lot better than nothing. This is doing dependency analysis on execution contexts which is a far cry from doing the fence dependency analysis, and so has to actively ignore the cycles that must exist on the dma side, and also the cycles that prevent entering execution contexts on the CPU. It has to actively ignore scheduler execution contexts, for lockdep cries, and so we do not get analysis of the locking contexts along that path. This would be solvable along the lines of extending lockdep ala lockdep_dma_enter(). Had i915's execution flow been marked up, it should have found the dubious wait for external fences inside the dead GPU recovery, and probably found a few more things to complain about with the reset locking. [Note we already do the same annotations for wait-vs-reset, but not reset-vs-execution.] Determination of which waits are legal and which are not is entirely ad hoc, for there is no status change tracking in the dependency analysis [that is once an execution context is linked to a published fence, again integral to lockdep.] Consider if the completion chain in atomic is swapped out for the morally equivalent fences along intertwined timelines, and so it does a bunch of dma_fence_wait() instead. Why are those waits legal despite them being after we have committed to fulfilling the out fence? [Why are the waits on and for the GPU legal, since they equally block execution flow?] Forcing a generic primitive to always be part of the same global map is horrible. You forgo being able to use the primitive for unrelated tasks, lose the ability to name particular contexts to gain more informative dependency cycle reports from having the explicit linkage. You can add wait_map tracking without loss of generality [in less than 10 lines], and you can still enforce that all fences used for a common purpose follow the same rules [the simplest way being to default to the singular wait_map]. But it's the explicitly named execution contexts that are the biggest boon to reading the code and reading the lockdep warns. This is a bunch of ad hoc tracking for a very narrow purpose applied globally, with loss of information. -Chris From gregkh at linuxfoundation.org Fri Jun 19 08:09:00 2020 From: gregkh at linuxfoundation.org (Greg KH) Date: Fri, 19 Jun 2020 10:09:00 +0200 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Make Wa_14010229206 permanent In-Reply-To: <20200618202701.729-1-rodrigo.vivi@intel.com> References: <20200618202701.729-1-rodrigo.vivi@intel.com> Message-ID: <20200619080900.GD8425@kroah.com> On Thu, Jun 18, 2020 at 01:27:00PM -0700, Rodrigo Vivi wrote: > From: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> > > commit 63d0f3ea8ebb67160eca281320d255c72b0cb51a upstream. > > This workaround now applies to all steppings, not just A0. > Wa_1409085225 is a temporary A0-only W/A however it is > identical to Wa_14010229206 and hence the combined workaround > is made permanent. > Bspec: 52890 > > Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> > Tested-by: Rafael Antognolli <rafael.antognolli at intel.com> > Reviewed-by: Matt Roper <matthew.d.roper at intel.com> > [mattrope: added missing blank line] > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > Link: https://patchwork.freedesktop.org/patch/msgid/20200326234955.16155-1-swathi.dhanavanthri at intel.com > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) What stable kernel(s) is this backport for? You need to give us a hint :) thanks, greg k-h > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 5176ad1a3976..092a42367851 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1379,12 +1379,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > GEN7_FF_THREAD_MODE, > GEN12_FF_TESSELATION_DOP_GATE_DISABLE); > > - /* > - * Wa_1409085225:tgl > - * Wa_14010229206:tgl > - */ > - wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); > - > /* Wa_1408615072:tgl */ > wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > VSUNIT_CLKGATE_DIS_TGL); > @@ -1402,6 +1396,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > wa_masked_en(wal, > GEN9_CS_DEBUG_MODE1, > FF_DOP_CLOCK_GATE_DISABLE); > + > + /* > + * Wa_1409085225:tgl > + * Wa_14010229206:tgl > + */ > + wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); > } > > if (IS_GEN(i915, 11)) { > -- > 2.24.1 > From daniel.vetter at ffwll.ch Fri Jun 19 08:51:59 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Fri, 19 Jun 2020 10:51:59 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <159255511144.7737.12635440776531222029@build.alporthouse.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> <159255511144.7737.12635440776531222029@build.alporthouse.com> Message-ID: <CAKMK7uHEwj6jiZkRZ5PaCUNWcuU9oE4KYm4XHZwHnFzEuChZ7w@mail.gmail.com> On Fri, Jun 19, 2020 at 10:25 AM Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Quoting Daniel Stone (2020-06-11 10:01:46) > > Hi, > > > > On Thu, 11 Jun 2020 at 09:44, Dave Airlie <airlied at gmail.com> wrote: > > > On Thu, 11 Jun 2020 at 18:01, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > Introducing a global lockmap that cannot capture the rules correctly, > > > > > > Can you document the rules all drivers should be following then, > > > because from here it looks to get refactored every version of i915, > > > and it would be nice if we could all aim for the same set of things > > > roughly. We've already had enough problems with amdgpu vs i915 vs > > > everyone else with fences, if this stops that in the future then I'd > > > rather we have that than just some unwritten rules per driver and > > > untestable. > > > > As someone who has sunk a bunch of work into explicit-fencing > > awareness in my compositor so I can never be blocked, I'd be > > disappointed if the infrastructure was ultimately pointless because > > the documented fencing rules were \_o_/ or thereabouts. Lockdep > > definitely isn't my area of expertise so I can't comment on the patch > > per se, but having something to ensure we don't hit deadlocks sure > > seems a lot better than nothing. > > This is doing dependency analysis on execution contexts which is a far > cry from doing the fence dependency analysis, and so has to actively > ignore the cycles that must exist on the dma side, and also the cycles > that prevent entering execution contexts on the CPU. It has to actively > ignore scheduler execution contexts, for lockdep cries, and so we do not > get analysis of the locking contexts along that path. This would be > solvable along the lines of extending lockdep ala lockdep_dma_enter(). drm/scheduler is annotated, found some rather improbably to hit issues in practice. But from the quick chat I've had with K?nig and others I think he agrees that it's real at least in the theoretical sense. Probably should consider playing lottery if you hit it in practice though :-) > Had i915's execution flow been marked up, it should have found the > dubious wait for external fences inside the dead GPU recovery, and > probably found a few more things to complain about with the reset locking. > [Note we already do the same annotations for wait-vs-reset, but not > reset-vs-execution.] I know it splats, that's why the tdr annotation patch comes with a spec proposal for lifting the wait busting we do in i915 to the dma_fence level. I included that because amdgpu has the same problem on modern hw. Apparently their planned fix (because they've hit this bug in testing) was to push some shared lock down into their atomic_comit_tail function and use that in gpu reset, so don't seem that interested in extending dma_fence. For i915 it's just gen2/3 display, and cross-driver dma-buf/fence usage for those is nil and won't change. Pragmatic solution imo would be to just not annotate gpu reset on these platforms, and relying on our wait busting plus igt tests to make sure it keeps working as-is. The point of the explicit annotations for the signalling side is very much that it can be rolled out gradually, and entirely left out for old legacy paths that aren't worth fixing. > Determination of which waits are legal and which are not is entirely ad > hoc, for there is no status change tracking in the dependency analysis > [that is once an execution context is linked to a published fence, again > integral to lockdep.] Consider if the completion chain in atomic is > swapped out for the morally equivalent fences along intertwined timelines, > and so it does a bunch of dma_fence_wait() instead. Why are those waits > legal despite them being after we have committed to fulfilling the out > fence? [Why are the waits on and for the GPU legal, since they equally > block execution flow?] No need to consider, it's already real and resulted in some pretty splats until I got the recursion handling right. > Forcing a generic primitive to always be part of the same global map is > horrible. You forgo being able to use the primitive for unrelated tasks, > lose the ability to name particular contexts to gain more informative > dependency cycle reports from having the explicit linkage. You can add > wait_map tracking without loss of generality [in less than 10 lines], > and you can still enforce that all fences used for a common purpose > follow the same rules [the simplest way being to default to the singular > wait_map]. But it's the explicitly named execution contexts that are the > biggest boon to reading the code and reading the lockdep warns. So one thing that's maybe not clear here: This doesn't track the DAG of dependencies. Doesn't even try, I'm still faithfully assuming drivers get that part right. Which is a gap and maybe we should fix this, but not the goal here. All this does is validate fences against anything else that might be going on in the system. E.g. your recursion example for atomic is handled by just assuming that any dma_fence_wait within a signalling section is legit and correct. We can add this later on, but not with lockdep, since lockdep works with classes. And proofing that dma_fences are acyclic requires you track them all as individuals. Entirely different things. That still leaves the below: > Forcing a generic primitive to always be part of the same global map is > horrible. And no concrete example or reason for why that's not possible. Because frankly it's not horrible, this is what upstream is all about: Shared concepts, shared contracts, shared code. The proposed patches might very well encode the wrong contract, that's all up for discussion. But fundamentally questioning that we need one is missing what upstream is all about. > This is a bunch of ad hoc tracking for a very narrow purpose applied > globally, with loss of information. It doesn't solve every problem indeed. I'm happy to review patches to check acyclic-ness of dma-fence at the global level from you, I haven't figured out yet how to make that happen. I know i915-gem has that, but this is about the cross-driver contract here. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From chris at chris-wilson.co.uk Fri Jun 19 09:13:35 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 10:13:35 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <CAKMK7uHEwj6jiZkRZ5PaCUNWcuU9oE4KYm4XHZwHnFzEuChZ7w@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> <159255511144.7737.12635440776531222029@build.alporthouse.com> <CAKMK7uHEwj6jiZkRZ5PaCUNWcuU9oE4KYm4XHZwHnFzEuChZ7w@mail.gmail.com> Message-ID: <159255801588.7737.4425728073225310839@build.alporthouse.com> Quoting Daniel Vetter (2020-06-19 09:51:59) > On Fri, Jun 19, 2020 at 10:25 AM Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Forcing a generic primitive to always be part of the same global map is > > horrible. > > And no concrete example or reason for why that's not possible. > Because frankly it's not horrible, this is what upstream is all about: > Shared concepts, shared contracts, shared code. > > The proposed patches might very well encode the wrong contract, that's > all up for discussion. But fundamentally questioning that we need one > is missing what upstream is all about. Then I have not clearly communicated, as my opinion is not that validation is worthless, but that the implementation is enshrining a global property on a low level primitive that prevents it from being used elsewhere. And I want to replace completion [chains] with fences, and bio with fences, and closures with fences, and what other equivalencies there are in the kernel. The fence is as central a locking construct as struct completion and deserves to be a foundational primitive provided by kernel/ used throughout all drivers for discrete problem domains. This is narrowing dma_fence whereby adding struct lockdep_map *dma_fence::wait_map and annotating linkage, allows you to continue to specify that all dma_fence used for a particular purpose must follow common rules, without restricting the primitive for uses outside of this scope. -Chris From daniel at ffwll.ch Fri Jun 19 09:43:09 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 19 Jun 2020 11:43:09 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <159255801588.7737.4425728073225310839@build.alporthouse.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> <159255511144.7737.12635440776531222029@build.alporthouse.com> <CAKMK7uHEwj6jiZkRZ5PaCUNWcuU9oE4KYm4XHZwHnFzEuChZ7w@mail.gmail.com> <159255801588.7737.4425728073225310839@build.alporthouse.com> Message-ID: <20200619094309.GT20149@phenom.ffwll.local> On Fri, Jun 19, 2020 at 10:13:35AM +0100, Chris Wilson wrote: > Quoting Daniel Vetter (2020-06-19 09:51:59) > > On Fri, Jun 19, 2020 at 10:25 AM Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > Forcing a generic primitive to always be part of the same global map is > > > horrible. > > > > And no concrete example or reason for why that's not possible. > > Because frankly it's not horrible, this is what upstream is all about: > > Shared concepts, shared contracts, shared code. > > > > The proposed patches might very well encode the wrong contract, that's > > all up for discussion. But fundamentally questioning that we need one > > is missing what upstream is all about. > > Then I have not clearly communicated, as my opinion is not that > validation is worthless, but that the implementation is enshrining a > global property on a low level primitive that prevents it from being > used elsewhere. And I want to replace completion [chains] with fences, and > bio with fences, and closures with fences, and what other equivalencies > there are in the kernel. The fence is as central a locking construct as > struct completion and deserves to be a foundational primitive provided > by kernel/ used throughout all drivers for discrete problem domains. > > This is narrowing dma_fence whereby adding > struct lockdep_map *dma_fence::wait_map > and annotating linkage, allows you to continue to specify that all > dma_fence used for a particular purpose must follow common rules, > without restricting the primitive for uses outside of this scope. Somewhere else in this thread I had discussions with Jason Gunthorpe about this topic. It might maybe change somewhat depending upon exact rules, but his take is very much "I don't want dma_fence in rdma". Or pretty close to that at least. Similar discussions with habanalabs, they're using dma_fence internally without any of the uapi. Discussion there has also now concluded that it's best if they remove them, and simply switch over to a wait_queue or completion like every other driver does. The next round of the patches already have a paragraph to at least somewhat limit how non-gpu drivers use dma_fence. And I guess actual consensus might be pointing even more strongly at dma_fence being solely something for gpus and closely related subsystem (maybe media) for syncing dma-buf access. So dma_fence as general replacement for completion chains I think just wont happen. What might make sense is if e.g. the lockdep annotations could be reused, at least in design, for wait_queue or completion or anything else really. I do think that has a fair chance compared to the automagic cross-release annotations approach, which relied way too heavily on guessing where barriers are. My experience from just a bit of playing around with these patches here and discussing them with other driver maintainers is that accurately deciding where critical sections start and end is a job for humans only. And if you get it wrong, you will have a false positive. And you're indeed correct that if we'd do annotations for completions and wait queues, then that would need to have a class per semantically equivalent user, like we have lockdep classes for mutexes, not just one overall. But dma_fence otoh is something very specific, which comes with very specific rules attached - it's not a generic wait_queue at all. Originally it did start out as one even, but it is a very specialized wait_queue. So there's imo two cases: - Your completion is entirely orthogonal of dma_fences, and can never ever block a dma_fence. Don't use dma_fence for this, and no problem. It's just another wait_queue somewhere. - Your completion can eventually, maybe through lots of convolutions and depdencies, block a dma_fence. In that case full dma_fence rules apply, and the only thing you can do with a custom annotation is make the rules even stricter. E.g. if a sub-timeline in the scheduler isn't allowed to take certain scheduler locks. But the userspace visible/published fence do take them, maybe as part of command submission or retirement. Entirely hypotethical, no idea any driver actually needs this. Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From m.szyprowski at samsung.com Fri Jun 19 10:36:09 2020 From: m.szyprowski at samsung.com (Marek Szyprowski) Date: Fri, 19 Jun 2020 12:36:09 +0200 Subject: [Intel-gfx] [PATCH v7 09/36] drm: i915: fix common struct sg_table related issues In-Reply-To: <20200619103636.11974-1-m.szyprowski@samsung.com> References: <20200619103636.11974-1-m.szyprowski@samsung.com> <CGME20200619103659eucas1p27ece9865ea4cdd82d4ca4df06edef7e6@eucas1p2.samsung.com> Message-ID: <20200619103636.11974-10-m.szyprowski@samsung.com> The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function returns the number of the created entries in the DMA address space. However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and dma_unmap_sg must be called with the original number of the entries passed to the dma_map_sg(). struct sg_table is a common structure used for describing a non-contiguous memory buffer, used commonly in the DRM and graphics subsystems. It consists of a scatterlist with memory pages and DMA addresses (sgl entry), as well as the number of scatterlist entries: CPU pages (orig_nents entry) and DMA mapped pages (nents entry). It turned out that it was a common mistake to misuse nents and orig_nents entries, calling DMA-mapping functions with a wrong number of entries or ignoring the number of mapped entries returned by the dma_map_sg() function. This driver creatively uses sg_table->orig_nents to store the size of the allocated scatterlist and ignores the number of the entries returned by dma_map_sg function. The sg_table->orig_nents is (mis)used to properly free the (over)allocated scatterlist. This patch only introduces the common DMA-mapping wrappers operating directly on the struct sg_table objects to the dmabuf related functions, so the other drivers, which might share buffers with i915 could rely on the properly set nents and orig_nents values. Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com> --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 11 +++-------- drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c | 7 +++---- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 2679380159fc..8a988592715b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -48,12 +48,9 @@ static struct sg_table *i915_gem_map_dma_buf(struct dma_buf_attachment *attachme src = sg_next(src); } - if (!dma_map_sg_attrs(attachment->dev, - st->sgl, st->nents, dir, - DMA_ATTR_SKIP_CPU_SYNC)) { - ret = -ENOMEM; + ret = dma_map_sgtable(attachment->dev, st, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) goto err_free_sg; - } return st; @@ -73,9 +70,7 @@ static void i915_gem_unmap_dma_buf(struct dma_buf_attachment *attachment, { struct drm_i915_gem_object *obj = dma_buf_to_obj(attachment->dmabuf); - dma_unmap_sg_attrs(attachment->dev, - sg->sgl, sg->nents, dir, - DMA_ATTR_SKIP_CPU_SYNC); + dma_unmap_sgtable(attachment->dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); sg_free_table(sg); kfree(sg); diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c index debaf7b18ab5..be30b27e2926 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c @@ -28,10 +28,9 @@ static struct sg_table *mock_map_dma_buf(struct dma_buf_attachment *attachment, sg = sg_next(sg); } - if (!dma_map_sg(attachment->dev, st->sgl, st->nents, dir)) { - err = -ENOMEM; + err = dma_map_sgtable(attachment->dev, st, dir, 0); + if (err) goto err_st; - } return st; @@ -46,7 +45,7 @@ static void mock_unmap_dma_buf(struct dma_buf_attachment *attachment, struct sg_table *st, enum dma_data_direction dir) { - dma_unmap_sg(attachment->dev, st->sgl, st->nents, dir); + dma_unmap_sgtable(attachment->dev, st, dir, 0); sg_free_table(st); kfree(st); } -- 2.17.1 From chris at chris-wilson.co.uk Fri Jun 19 13:12:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 14:12:17 +0100 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <20200619094309.GT20149@phenom.ffwll.local> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> <159255511144.7737.12635440776531222029@build.alporthouse.com> <CAKMK7uHEwj6jiZkRZ5PaCUNWcuU9oE4KYm4XHZwHnFzEuChZ7w@mail.gmail.com> <159255801588.7737.4425728073225310839@build.alporthouse.com> <20200619094309.GT20149@phenom.ffwll.local> Message-ID: <159257233754.7737.17318605310513355800@build.alporthouse.com> Quoting Daniel Vetter (2020-06-19 10:43:09) > On Fri, Jun 19, 2020 at 10:13:35AM +0100, Chris Wilson wrote: > > Quoting Daniel Vetter (2020-06-19 09:51:59) > > > On Fri, Jun 19, 2020 at 10:25 AM Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > Forcing a generic primitive to always be part of the same global map is > > > > horrible. > > > > > > And no concrete example or reason for why that's not possible. > > > Because frankly it's not horrible, this is what upstream is all about: > > > Shared concepts, shared contracts, shared code. > > > > > > The proposed patches might very well encode the wrong contract, that's > > > all up for discussion. But fundamentally questioning that we need one > > > is missing what upstream is all about. > > > > Then I have not clearly communicated, as my opinion is not that > > validation is worthless, but that the implementation is enshrining a > > global property on a low level primitive that prevents it from being > > used elsewhere. And I want to replace completion [chains] with fences, and > > bio with fences, and closures with fences, and what other equivalencies > > there are in the kernel. The fence is as central a locking construct as > > struct completion and deserves to be a foundational primitive provided > > by kernel/ used throughout all drivers for discrete problem domains. > > > > This is narrowing dma_fence whereby adding > > struct lockdep_map *dma_fence::wait_map > > and annotating linkage, allows you to continue to specify that all > > dma_fence used for a particular purpose must follow common rules, > > without restricting the primitive for uses outside of this scope. > > Somewhere else in this thread I had discussions with Jason Gunthorpe about > this topic. It might maybe change somewhat depending upon exact rules, but > his take is very much "I don't want dma_fence in rdma". Or pretty close to > that at least. > > Similar discussions with habanalabs, they're using dma_fence internally > without any of the uapi. Discussion there has also now concluded that it's > best if they remove them, and simply switch over to a wait_queue or > completion like every other driver does. > > The next round of the patches already have a paragraph to at least > somewhat limit how non-gpu drivers use dma_fence. And I guess actual > consensus might be pointing even more strongly at dma_fence being solely > something for gpus and closely related subsystem (maybe media) for syncing > dma-buf access. > > So dma_fence as general replacement for completion chains I think just > wont happen. That is sad. I cannot comprehend going back to pure completions after a taste of fence scheduling. And we are not even close to fully utilising them, as not all the async cpu [allocation!] tasks are fully tracked by fences yet and are still stuck in a FIFO workqueue. > What might make sense is if e.g. the lockdep annotations could be reused, > at least in design, for wait_queue or completion or anything else > really. I do think that has a fair chance compared to the automagic > cross-release annotations approach, which relied way too heavily on > guessing where barriers are. My experience from just a bit of playing > around with these patches here and discussing them with other driver > maintainers is that accurately deciding where critical sections start and > end is a job for humans only. And if you get it wrong, you will have a > false positive. > > And you're indeed correct that if we'd do annotations for completions and > wait queues, then that would need to have a class per semantically > equivalent user, like we have lockdep classes for mutexes, not just one > overall. > > But dma_fence otoh is something very specific, which comes with very > specific rules attached - it's not a generic wait_queue at all. Originally > it did start out as one even, but it is a very specialized wait_queue. > > So there's imo two cases: > > - Your completion is entirely orthogonal of dma_fences, and can never ever > block a dma_fence. Don't use dma_fence for this, and no problem. It's > just another wait_queue somewhere. > > - Your completion can eventually, maybe through lots of convolutions and > depdencies, block a dma_fence. In that case full dma_fence rules apply, > and the only thing you can do with a custom annotation is make the rules > even stricter. E.g. if a sub-timeline in the scheduler isn't allowed to > take certain scheduler locks. But the userspace visible/published fence > do take them, maybe as part of command submission or retirement. > Entirely hypotethical, no idea any driver actually needs this. I think we are faced with this very real problem. The papering we have today over userptr is so very thin, and if you squint you can already see it is coupled into the completion signal. Just it happens to be on the other side of the fence. The next batch of priority inversions involve integrating the async cpu tasks into the scheduler, and have full dependency tracking over every internal fence. I do not see any way to avoid coupling the completion signal from the GPU to the earliest resource allocation, as it's an unbroken chain of work, at least from the user's perspective. [Next up for annotations is that we need to always assume that userspace has an implicit lock on GPU resources; having to break that lock with a GPU reset should be a breach of our data integrity, and best avoided, for compute does not care one iota about system integrity and insist userspace knows best.] Such allocations have to be allowed to fail and for that failure to propagate cancelling the queued work, such that I'm considering what rules we need for gfp_t. That might allow enough leverage to break any fs_reclaim loops, but userptr is likely forever doomed [aside from its fs_reclaim loop is as preventable as the normal shrinker paths], but we still need to suggest to pin_user_pages that failure is better than oom and that is not clear atm. Plus the usual failure can happen at any time after updating the user facing bookkeeping, but that is just extra layers in the execution monitor ready to step in and replacing failing work with the error propagation. Or where the system grinds to a halt, requiring the monitor to patch in a new page / resource. -Chris From bhanuprakash.modem at intel.com Fri Jun 19 21:11:03 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:41:03 +0530 Subject: [Intel-gfx] [v6 0/3] VRR capable attach prop in i915, DPCD helper, VRR debugfs In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <20200619211106.19207-1-bhanuprakash.modem@intel.com> This is an initial set of patches for enabling VRR support in i915. This series has patches for: 1. adding a drm dpcd helper to read ignore MSA bit in sink's DPCD indicating sink support for VRR 2. Attach and set VRR capable connector prop for Intel DP conn 3. Expose VRR min and max through debugfs Aditya Swarup (1): drm/i915/dp: Attach and set drm connector VRR property Bhanuprakash Modem (1): drm/debug: Expose connector VRR monitor range via debugfs Manasi Navare (1): drm/dp: DRM DP helper for reading Ignore MSA from DPCD .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 -------------- drivers/gpu/drm/drm_debugfs.c | 22 +++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ include/drm/drm_dp_helper.h | 8 ++++++ 5 files changed, 59 insertions(+), 20 deletions(-) -- 2.20.1 From bhanuprakash.modem at intel.com Fri Jun 19 21:11:04 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:41:04 +0530 Subject: [Intel-gfx] [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <20200619211106.19207-2-bhanuprakash.modem@intel.com> From: Manasi Navare <manasi.d.navare at intel.com> DP sink device sets the Ignore MSA bit in its DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to ignore the MSA video timing parameters and its ability to support seamless video timing change over a range of timing exposed by DisplayID and EDID. This is required for the sink to indicate that it is Adaptive sync capable. v3: * Fi the typo in commit message (Manasi) v2: * Rename to describe what the function does (Jani Nikula) Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Harry Wentland <harry.wentland at amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas at amd.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Reviewed-by: Harry Wentland <harry.wentland at amd.com> --- include/drm/drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1165ec105638..e47dc22ebf50 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) DP_ALTERNATE_SCRAMBLER_RESET_CAP; } +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + /* * DisplayPort AUX channel */ -- 2.20.1 From bhanuprakash.modem at intel.com Fri Jun 19 21:11:05 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:41:05 +0530 Subject: [Intel-gfx] [v6 2/3] drm/i915/dp: Attach and set drm connector VRR property In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <20200619211106.19207-3-bhanuprakash.modem@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..d0dba81cfb07 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6149,6 +6149,9 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -6256,6 +6259,23 @@ intel_dp_force(struct drm_connector *connector) intel_display_power_put(dev_priv, aux_domain, wakeref); } +bool intel_dp_is_vrr_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + static int intel_dp_get_modes(struct drm_connector *connector) { struct intel_connector *intel_connector = to_intel_connector(connector); @@ -6264,6 +6284,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_dp_is_vrr_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7325,6 +7349,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (INTEL_GEN(dev_priv) >= 12) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..db895a3cd93f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -14,6 +14,7 @@ enum pipe; enum port; struct drm_connector_state; struct drm_encoder; +struct drm_connector; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct drm_dp_vsc_sdp; @@ -120,6 +121,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); void intel_dp_process_phy_request(struct intel_dp *intel_dp); +bool intel_dp_is_vrr_capable(struct drm_connector *connector); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { -- 2.20.1 From bhanuprakash.modem at intel.com Fri Jun 19 21:11:06 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:41:06 +0530 Subject: [Intel-gfx] [v8 3/3] drm/debug: Expose connector VRR monitor range via debugfs In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> Message-ID: <20200619211106.19207-4-bhanuprakash.modem@intel.com> [Why] It's useful to know the min and max vrr range for IGT testing. [How] Expose the min and max vfreq for the connector via a debugfs file on the connector, "vrr_range". Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range v2: * Fix the typo in max_vfreq (Manasi) * Change the name of node to i915_vrr_info so we can add other vrr info for more debug info (Manasi) * Change the VRR capable to display Yes or No (Manasi) * Fix indentation checkpatch errors (Manasi) v3: * Remove the unnecessary debug print (Manasi) v4: * Rebase v5: * Rename to vrr_range to match AMD debugfs v6: * Rebase (manasi) v7: * Fix cmpilation due to rebase v8: * Move debugfs node creation logic to DRM * Remove AMD specific logic Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Harry Wentland <harry.wentland at amd.com> --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ----------------- drivers/gpu/drm/drm_debugfs.c | 22 +++++++++++++++++++ 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 076af267b488..71387d2af2ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void *data) return res; } -/* - * Returns the min and max vrr vfreq through the connector's debugfs file. - * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range - */ -static int vrr_range_show(struct seq_file *m, void *data) -{ - struct drm_connector *connector = m->private; - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - - if (connector->status != connector_status_connected) - return -ENODEV; - - seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); - seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); - - return 0; -} - #ifdef CONFIG_DRM_AMD_DC_HDCP /* * Returns the HDCP capability of the Display (1.4 for now). @@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); DEFINE_SHOW_ATTRIBUTE(output_bpc); -DEFINE_SHOW_ATTRIBUTE(vrr_range); #ifdef CONFIG_DRM_AMD_DC_HDCP DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); #endif @@ -1059,7 +1040,6 @@ static const struct { {"phy_settings", &dp_phy_settings_debugfs_fop}, {"test_pattern", &dp_phy_test_pattern_fops}, {"output_bpc", &output_bpc_fops}, - {"vrr_range", &vrr_range_fops}, #ifdef CONFIG_DRM_AMD_DC_HDCP {"hdcp_sink_capability", &hdcp_sink_capability_fops}, #endif diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c index bfe4602f206b..3d7182001004 100644 --- a/drivers/gpu/drm/drm_debugfs.c +++ b/drivers/gpu/drm/drm_debugfs.c @@ -376,6 +376,24 @@ static ssize_t edid_write(struct file *file, const char __user *ubuf, return (ret) ? ret : len; } +/* + * Returns the min and max vrr vfreq through the connector's debugfs file. + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range + */ +static int vrr_range_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + + if (connector->status != connector_status_connected) + return -ENODEV; + + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(vrr_range); + static const struct file_operations drm_edid_fops = { .owner = THIS_MODULE, .open = edid_open, @@ -413,6 +431,10 @@ void drm_debugfs_connector_add(struct drm_connector *connector) /* edid */ debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root, connector, &drm_edid_fops); + + /* vrr range */ + debugfs_create_file("vrr_range", S_IRUGO, root, connector, + &vrr_range_fops); } void drm_debugfs_connector_remove(struct drm_connector *connector) -- 2.20.1 From bhanuprakash.modem at intel.com Fri Jun 19 21:23:53 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:53:53 +0530 Subject: [Intel-gfx] [v6 0/3] VRR capable attach prop in i915, DPCD helper, VRR debugfs Message-ID: <20200619212356.19285-1-bhanuprakash.modem@intel.com> This is an initial set of patches for enabling VRR support in i915. This series has patches for: 1. Adding a drm dpcd helper to read ignore MSA bit in sink's DPCD indicating sink support for VRR 2. Attach and set VRR capable connector prop for Intel DP conn 3. Expose VRR min and max through debugfs Aditya Swarup (1): drm/i915/dp: Attach and set drm connector VRR property Bhanuprakash Modem (1): drm/debug: Expose connector VRR monitor range via debugfs Manasi Navare (1): drm/dp: DRM DP helper for reading Ignore MSA from DPCD .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 -------------- drivers/gpu/drm/drm_debugfs.c | 22 +++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ include/drm/drm_dp_helper.h | 8 ++++++ 5 files changed, 59 insertions(+), 20 deletions(-) -- 2.20.1 From bhanuprakash.modem at intel.com Fri Jun 19 21:23:54 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:53:54 +0530 Subject: [Intel-gfx] [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD In-Reply-To: <20200619212356.19285-1-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> Message-ID: <20200619212356.19285-2-bhanuprakash.modem@intel.com> From: Manasi Navare <manasi.d.navare at intel.com> DP sink device sets the Ignore MSA bit in its DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to ignore the MSA video timing parameters and its ability to support seamless video timing change over a range of timing exposed by DisplayID and EDID. This is required for the sink to indicate that it is Adaptive sync capable. v3: * Fi the typo in commit message (Manasi) v2: * Rename to describe what the function does (Jani Nikula) Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Harry Wentland <harry.wentland at amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas at amd.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Reviewed-by: Harry Wentland <harry.wentland at amd.com> --- include/drm/drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1165ec105638..e47dc22ebf50 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) DP_ALTERNATE_SCRAMBLER_RESET_CAP; } +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + /* * DisplayPort AUX channel */ -- 2.20.1 From bhanuprakash.modem at intel.com Fri Jun 19 21:23:55 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:53:55 +0530 Subject: [Intel-gfx] [v6 2/3] drm/i915/dp: Attach and set drm connector VRR property In-Reply-To: <20200619212356.19285-1-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> Message-ID: <20200619212356.19285-3-bhanuprakash.modem@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..d0dba81cfb07 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6149,6 +6149,9 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -6256,6 +6259,23 @@ intel_dp_force(struct drm_connector *connector) intel_display_power_put(dev_priv, aux_domain, wakeref); } +bool intel_dp_is_vrr_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + static int intel_dp_get_modes(struct drm_connector *connector) { struct intel_connector *intel_connector = to_intel_connector(connector); @@ -6264,6 +6284,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_dp_is_vrr_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7325,6 +7349,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (INTEL_GEN(dev_priv) >= 12) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..db895a3cd93f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -14,6 +14,7 @@ enum pipe; enum port; struct drm_connector_state; struct drm_encoder; +struct drm_connector; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct drm_dp_vsc_sdp; @@ -120,6 +121,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); void intel_dp_process_phy_request(struct intel_dp *intel_dp); +bool intel_dp_is_vrr_capable(struct drm_connector *connector); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { -- 2.20.1 From bhanuprakash.modem at intel.com Fri Jun 19 21:23:56 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Sat, 20 Jun 2020 02:53:56 +0530 Subject: [Intel-gfx] [v8 3/3] drm/debug: Expose connector VRR monitor range via debugfs In-Reply-To: <20200619212356.19285-1-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> Message-ID: <20200619212356.19285-4-bhanuprakash.modem@intel.com> [Why] It's useful to know the min and max vrr range for IGT testing. [How] Expose the min and max vfreq for the connector via a debugfs file on the connector, "vrr_range". Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range v2: * Fix the typo in max_vfreq (Manasi) * Change the name of node to i915_vrr_info so we can add other vrr info for more debug info (Manasi) * Change the VRR capable to display Yes or No (Manasi) * Fix indentation checkpatch errors (Manasi) v3: * Remove the unnecessary debug print (Manasi) v4: * Rebase v5: * Rename to vrr_range to match AMD debugfs v6: * Rebase (manasi) v7: * Fix cmpilation due to rebase v8: * Move debugfs node creation logic to DRM (Emil) * Remove AMD specific logic (Emil) Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Harry Wentland <harry.wentland at amd.com> --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ----------------- drivers/gpu/drm/drm_debugfs.c | 22 +++++++++++++++++++ 2 files changed, 22 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 076af267b488..71387d2af2ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void *data) return res; } -/* - * Returns the min and max vrr vfreq through the connector's debugfs file. - * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range - */ -static int vrr_range_show(struct seq_file *m, void *data) -{ - struct drm_connector *connector = m->private; - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - - if (connector->status != connector_status_connected) - return -ENODEV; - - seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); - seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); - - return 0; -} - #ifdef CONFIG_DRM_AMD_DC_HDCP /* * Returns the HDCP capability of the Display (1.4 for now). @@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); DEFINE_SHOW_ATTRIBUTE(output_bpc); -DEFINE_SHOW_ATTRIBUTE(vrr_range); #ifdef CONFIG_DRM_AMD_DC_HDCP DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); #endif @@ -1059,7 +1040,6 @@ static const struct { {"phy_settings", &dp_phy_settings_debugfs_fop}, {"test_pattern", &dp_phy_test_pattern_fops}, {"output_bpc", &output_bpc_fops}, - {"vrr_range", &vrr_range_fops}, #ifdef CONFIG_DRM_AMD_DC_HDCP {"hdcp_sink_capability", &hdcp_sink_capability_fops}, #endif diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c index bfe4602f206b..3d7182001004 100644 --- a/drivers/gpu/drm/drm_debugfs.c +++ b/drivers/gpu/drm/drm_debugfs.c @@ -376,6 +376,24 @@ static ssize_t edid_write(struct file *file, const char __user *ubuf, return (ret) ? ret : len; } +/* + * Returns the min and max vrr vfreq through the connector's debugfs file. + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range + */ +static int vrr_range_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + + if (connector->status != connector_status_connected) + return -ENODEV; + + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(vrr_range); + static const struct file_operations drm_edid_fops = { .owner = THIS_MODULE, .open = edid_open, @@ -413,6 +431,10 @@ void drm_debugfs_connector_add(struct drm_connector *connector) /* edid */ debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root, connector, &drm_edid_fops); + + /* vrr range */ + debugfs_create_file("vrr_range", S_IRUGO, root, connector, + &vrr_range_fops); } void drm_debugfs_connector_remove(struct drm_connector *connector) -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 19 14:31:04 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 15:31:04 +0100 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/gem: Avoid kmalloc under i915->mm_lock Message-ID: <20200619143106.10356-1-chris@chris-wilson.co.uk> Rearrange the allocation of the mm_struct registration to avoid allocating underneath the i915->mm_lock, so that we avoid tainting the lock (and in turn many other locks that may be held as i915->mm_lock is taken, and those locks we may want on the free [shrinker] paths). In doing so, we convert the lookup to be RCU protected by courtesy of converting the free-worker to be an rcu_work. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 123 +++++++++----------- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 59 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index 9c53eb883400..84766414a1f0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -21,7 +21,7 @@ struct i915_mm_struct { struct i915_mmu_notifier *mn; struct hlist_node node; struct kref kref; - struct work_struct work; + struct rcu_work work; }; #if defined(CONFIG_MMU_NOTIFIER) @@ -189,40 +189,31 @@ i915_gem_userptr_release__mmu_notifier(struct drm_i915_gem_object *obj) static struct i915_mmu_notifier * i915_mmu_notifier_find(struct i915_mm_struct *mm) { - struct i915_mmu_notifier *mn; - int err = 0; + struct i915_mmu_notifier *mn, *old; + int err; - mn = mm->mn; - if (mn) + mn = READ_ONCE(mm->mn); + if (likely(mn)) return mn; mn = i915_mmu_notifier_create(mm); if (IS_ERR(mn)) - err = PTR_ERR(mn); - - mmap_write_lock(mm->mm); - mutex_lock(&mm->i915->mm_lock); - if (mm->mn == NULL && !err) { - /* Protected by mmap_lock (write-lock) */ - err = __mmu_notifier_register(&mn->mn, mm->mm); - if (!err) { - /* Protected by mm_lock */ - mm->mn = fetch_and_zero(&mn); - } - } else if (mm->mn) { - /* - * Someone else raced and successfully installed the mmu - * notifier, we can cancel our own errors. - */ - err = 0; + return mn; + + err = mmu_notifier_register(&mn->mn, mm->mm); + if (err) { + kfree(mn); + return ERR_PTR(err); } - mutex_unlock(&mm->i915->mm_lock); - mmap_write_unlock(mm->mm); - if (mn && !IS_ERR(mn)) + old = cmpxchg(&mm->mn, NULL, mn); + if (old) { + mmu_notifier_unregister(&mn->mn, mm->mm); kfree(mn); + mn = old; + } - return err ? ERR_PTR(err) : mm->mn; + return mn; } static int @@ -301,23 +292,26 @@ i915_mmu_notifier_free(struct i915_mmu_notifier *mn, #endif static struct i915_mm_struct * -__i915_mm_struct_find(struct drm_i915_private *dev_priv, struct mm_struct *real) +__i915_mm_struct_find(struct drm_i915_private *i915, struct mm_struct *real) { - struct i915_mm_struct *mm; + struct i915_mm_struct *it, *mm = NULL; - /* Protected by dev_priv->mm_lock */ - hash_for_each_possible(dev_priv->mm_structs, mm, node, (unsigned long)real) - if (mm->mm == real) - return mm; + rcu_read_lock(); + hash_for_each_possible(i915->mm_structs, it, node, (unsigned long)real) + if (it->mm == real && kref_get_unless_zero(&it->kref)) { + mm = it; + break; + } + rcu_read_unlock(); - return NULL; + return mm; } static int i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) { - struct drm_i915_private *dev_priv = to_i915(obj->base.dev); - struct i915_mm_struct *mm; + struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_mm_struct *mm, *new; int ret = 0; /* During release of the GEM object we hold the struct_mutex. This @@ -330,39 +324,40 @@ i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) * struct_mutex, i.e. we need to schedule a worker to do the clean * up. */ - mutex_lock(&dev_priv->mm_lock); - mm = __i915_mm_struct_find(dev_priv, current->mm); - if (mm == NULL) { - mm = kmalloc(sizeof(*mm), GFP_KERNEL); - if (mm == NULL) { - ret = -ENOMEM; - goto out; - } + mm = __i915_mm_struct_find(i915, current->mm); + if (mm) + goto out; - kref_init(&mm->kref); - mm->i915 = to_i915(obj->base.dev); - - mm->mm = current->mm; - mmgrab(current->mm); + new = kmalloc(sizeof(*mm), GFP_KERNEL); + if (new == NULL) + return -ENOMEM; - mm->mn = NULL; + kref_init(&new->kref); + new->i915 = to_i915(obj->base.dev); + new->mm = current->mm; + new->mn = NULL; - /* Protected by dev_priv->mm_lock */ - hash_add(dev_priv->mm_structs, - &mm->node, (unsigned long)mm->mm); - } else - kref_get(&mm->kref); + spin_lock(&i915->mm_lock); + mm = __i915_mm_struct_find(i915, current->mm); + if (!mm) { + hash_add(i915->mm_structs, &new->node, (unsigned long)new->mm); + mmgrab(current->mm); + mm = new; + } + spin_unlock(&i915->mm_lock); + if (mm != new) + kfree(new); - obj->userptr.mm = mm; out: - mutex_unlock(&dev_priv->mm_lock); + obj->userptr.mm = mm; return ret; } static void __i915_mm_struct_free__worker(struct work_struct *work) { - struct i915_mm_struct *mm = container_of(work, typeof(*mm), work); + struct i915_mm_struct *mm = container_of(work, typeof(*mm), work.work); + i915_mmu_notifier_free(mm->mn, mm->mm); mmdrop(mm->mm); kfree(mm); @@ -373,12 +368,12 @@ __i915_mm_struct_free(struct kref *kref) { struct i915_mm_struct *mm = container_of(kref, typeof(*mm), kref); - /* Protected by dev_priv->mm_lock */ + spin_lock(&mm->i915->mm_lock); hash_del(&mm->node); - mutex_unlock(&mm->i915->mm_lock); + spin_unlock(&mm->i915->mm_lock); - INIT_WORK(&mm->work, __i915_mm_struct_free__worker); - queue_work(mm->i915->mm.userptr_wq, &mm->work); + INIT_RCU_WORK(&mm->work, __i915_mm_struct_free__worker); + queue_rcu_work(mm->i915->mm.userptr_wq, &mm->work); } static void @@ -387,9 +382,7 @@ i915_gem_userptr_release__mm_struct(struct drm_i915_gem_object *obj) if (obj->userptr.mm == NULL) return; - kref_put_mutex(&obj->userptr.mm->kref, - __i915_mm_struct_free, - &to_i915(obj->base.dev)->mm_lock); + kref_put(&obj->userptr.mm->kref, __i915_mm_struct_free); obj->userptr.mm = NULL; } @@ -851,7 +844,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, int i915_gem_init_userptr(struct drm_i915_private *dev_priv) { - mutex_init(&dev_priv->mm_lock); + spin_lock_init(&dev_priv->mm_lock); hash_init(dev_priv->mm_structs); dev_priv->mm.userptr_wq = diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..7464656253c9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -988,7 +988,7 @@ struct drm_i915_private { struct i915_gem_mm mm; DECLARE_HASHTABLE(mm_structs, 7); - struct mutex mm_lock; + spinlock_t mm_lock; /* Kernel Modesetting */ -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 19 14:31:05 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 15:31:05 +0100 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/gvt: Drop redundant prepare_write/pin_pages In-Reply-To: <20200619143106.10356-1-chris@chris-wilson.co.uk> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> Message-ID: <20200619143106.10356-2-chris@chris-wilson.co.uk> Since gvt calls pin_map for the shadow batch buffer, this makes the action of prepare_write [+pin_pages] redundant. We can write into the obj->mm.mapping directory and the flush_map routine knows when it has to flush the cpu cache afterwards. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 14 +------- drivers/gpu/drm/i915/gvt/scheduler.c | 51 ++++++++------------------- drivers/gpu/drm/i915/gvt/scheduler.h | 2 -- 3 files changed, 15 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 8b87f130f7f1..f1940939260a 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1904,19 +1904,10 @@ static int perform_bb_shadow(struct parser_exec_state *s) goto err_free_bb; } - ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush); - if (ret) - goto err_free_obj; - bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); if (IS_ERR(bb->va)) { ret = PTR_ERR(bb->va); - goto err_finish_shmem_access; - } - - if (bb->clflush & CLFLUSH_BEFORE) { - drm_clflush_virt_range(bb->va, bb->obj->base.size); - bb->clflush &= ~CLFLUSH_BEFORE; + goto err_free_obj; } ret = copy_gma_to_hva(s->vgpu, mm, @@ -1935,7 +1926,6 @@ static int perform_bb_shadow(struct parser_exec_state *s) INIT_LIST_HEAD(&bb->list); list_add(&bb->list, &s->workload->shadow_bb); - bb->accessing = true; bb->bb_start_cmd_va = s->ip_va; if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa)) @@ -1956,8 +1946,6 @@ static int perform_bb_shadow(struct parser_exec_state *s) return 0; err_unmap: i915_gem_object_unpin_map(bb->obj); -err_finish_shmem_access: - i915_gem_object_finish_access(bb->obj); err_free_obj: i915_gem_object_put(bb->obj); err_free_bb: diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 8fc2ad4517e9..3c3b9842bbbd 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -509,26 +509,18 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) bb->bb_start_cmd_va = workload->shadow_ring_buffer_va + bb->bb_offset; - if (bb->ppgtt) { - /* for non-priv bb, scan&shadow is only for - * debugging purpose, so the content of shadow bb - * is the same as original bb. Therefore, - * here, rather than switch to shadow bb's gma - * address, we directly use original batch buffer's - * gma address, and send original bb to hardware - * directly - */ - if (bb->clflush & CLFLUSH_AFTER) { - drm_clflush_virt_range(bb->va, - bb->obj->base.size); - bb->clflush &= ~CLFLUSH_AFTER; - } - i915_gem_object_finish_access(bb->obj); - bb->accessing = false; - - } else { + /* + * For non-priv bb, scan&shadow is only for + * debugging purpose, so the content of shadow bb + * is the same as original bb. Therefore, + * here, rather than switch to shadow bb's gma + * address, we directly use original batch buffer's + * gma address, and send original bb to hardware + * directly + */ + if (!bb->ppgtt) { bb->vma = i915_gem_object_ggtt_pin(bb->obj, - NULL, 0, 0, 0); + NULL, 0, 0, 0); if (IS_ERR(bb->vma)) { ret = PTR_ERR(bb->vma); goto err; @@ -539,27 +531,15 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) if (gmadr_bytes == 8) bb->bb_start_cmd_va[2] = 0; - /* No one is going to touch shadow bb from now on. */ - if (bb->clflush & CLFLUSH_AFTER) { - drm_clflush_virt_range(bb->va, - bb->obj->base.size); - bb->clflush &= ~CLFLUSH_AFTER; - } - - ret = i915_gem_object_set_to_gtt_domain(bb->obj, - false); - if (ret) - goto err; - ret = i915_vma_move_to_active(bb->vma, workload->req, 0); if (ret) goto err; - - i915_gem_object_finish_access(bb->obj); - bb->accessing = false; } + + /* No one is going to touch shadow bb from now on. */ + i915_gem_object_flush_map(bb->obj); } return 0; err: @@ -630,9 +610,6 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) { if (bb->obj) { - if (bb->accessing) - i915_gem_object_finish_access(bb->obj); - if (bb->va && !IS_ERR(bb->va)) i915_gem_object_unpin_map(bb->obj); diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h index 15d317f2a4a4..64e7a0b791c3 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.h +++ b/drivers/gpu/drm/i915/gvt/scheduler.h @@ -124,8 +124,6 @@ struct intel_vgpu_shadow_bb { struct i915_vma *vma; void *va; u32 *bb_start_cmd_va; - unsigned int clflush; - bool accessing; unsigned long bb_offset; bool ppgtt; }; -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 19 14:31:06 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 15:31:06 +0100 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Replace manual kmap_atomic() with pin_map for renderstate In-Reply-To: <20200619143106.10356-1-chris@chris-wilson.co.uk> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> Message-ID: <20200619143106.10356-3-chris@chris-wilson.co.uk> We only emit the renderstate once now during module load, it is no longer a concern that we are delaying context creation and so do not need to so eagerly optimise. Since the last time we have looked at the renderstate, we have a pin_map / flush_map facility that supports simple single mappings, replacing the open-coded kmap_atomic() and prepare_write. As it should be a single page, of which we only write a small portion, we stick to a simple WB [kmap] and use clflush on !llc platforms, rather than creating a temporary WC vmapping for the single page. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_renderstate.c | 29 +++++++-------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index f59e7875cc5e..6db23389e427 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -61,7 +61,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine) #define OUT_BATCH(batch, i, val) \ do { \ if ((i) >= PAGE_SIZE / sizeof(u32)) \ - goto err; \ + goto out; \ (batch)[(i)++] = (val); \ } while(0) @@ -70,15 +70,12 @@ static int render_state_setup(struct intel_renderstate *so, { const struct intel_renderstate_rodata *rodata = so->rodata; unsigned int i = 0, reloc_index = 0; - unsigned int needs_clflush; + int ret = -EINVAL; u32 *d; - int ret; - ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush); - if (ret) - return ret; - - d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0)); + d = i915_gem_object_pin_map(so->vma->obj, I915_MAP_WB); + if (IS_ERR(d)) + return PTR_ERR(d); while (i < rodata->batch_items) { u32 s = rodata->batch[i]; @@ -89,7 +86,7 @@ static int render_state_setup(struct intel_renderstate *so, if (HAS_64BIT_RELOC(i915)) { if (i + 1 >= rodata->batch_items || rodata->batch[i + 1] != 0) - goto err; + goto out; d[i++] = s; s = upper_32_bits(r); @@ -103,7 +100,7 @@ static int render_state_setup(struct intel_renderstate *so, if (rodata->reloc[reloc_index] != -1) { drm_err(&i915->drm, "only %d relocs resolved\n", reloc_index); - goto err; + goto out; } so->batch_offset = i915_ggtt_offset(so->vma); @@ -150,19 +147,11 @@ static int render_state_setup(struct intel_renderstate *so, */ so->aux_size = ALIGN(so->aux_size, 8); - if (needs_clflush) - drm_clflush_virt_range(d, i * sizeof(u32)); - kunmap_atomic(d); - ret = 0; out: - i915_gem_object_finish_access(so->vma->obj); + __i915_gem_object_flush_map(so->vma->obj, 0, i * sizeof(u32)); + i915_gem_object_unpin_map(so->vma->obj); return ret; - -err: - kunmap_atomic(d); - ret = -EINVAL; - goto out; } #undef OUT_BATCH -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 19 14:43:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 14:43:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_VRR_capable_attach_prop_in_i915=2C_DPCD_helper=2C_VRR_debug?= =?utf-8?b?ZnMgKHJldjMp?= In-Reply-To: <20200619212356.19285-1-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> Message-ID: <159257782333.12533.13885778921288107984@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev3) URL : https://patchwork.freedesktop.org/series/78278/ State : warning == Summary == $ dim checkpatch origin/drm-tip d029f13253a7 drm/dp: DRM DP helper for reading Ignore MSA from DPCD 8ab5efcf7756 drm/i915/dp: Attach and set drm connector VRR property b8d579bd6450 drm/debug: Expose connector VRR monitor range via debugfs -:124: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. #124: FILE: drivers/gpu/drm/drm_debugfs.c:436: + debugfs_create_file("vrr_range", S_IRUGO, root, connector, total: 0 errors, 1 warnings, 0 checks, 72 lines checked From patchwork at emeril.freedesktop.org Fri Jun 19 14:45:28 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 14:45:28 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?VRR_capable_attach_prop_in_i915=2C_DPCD_helper=2C_VRR_debugfs_?= =?utf-8?b?KHJldjMp?= In-Reply-To: <20200619212356.19285-1-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> Message-ID: <159257792855.12536.11888790618523154604@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev3) URL : https://patchwork.freedesktop.org/series/78278/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1171:46: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: got void [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] <asn:1> *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] <asn:1> **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] <asn:1> * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '<asn:1>' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space From daniel at ffwll.ch Fri Jun 19 15:06:04 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 19 Jun 2020 17:06:04 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619113934.GN6578@ziepe.ca> References: <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> <20200617152835.GF6578@ziepe.ca> <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> Message-ID: <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> On Fri, Jun 19, 2020 at 1:39 PM Jason Gunthorpe <jgg at ziepe.ca> wrote: > > On Fri, Jun 19, 2020 at 09:22:09AM +0200, Daniel Vetter wrote: > > > As I've understood GPU that means you need to show that the commands > > > associated with the buffer have completed. This is all local stuff > > > within the driver, right? Why use fence (other than it already exists) > > > > Because that's the end-of-dma thing. And it's cross-driver for the > > above reasons, e.g. > > - device A renders some stuff. Userspace gets dma_fence A out of that > > (well sync_file or one of the other uapi interfaces, but you get the > > idea) > > - userspace (across process or just different driver) issues more > > rendering for device B, which depends upon the rendering done on > > device A. So dma_fence A is an dependency and will block this dma > > operation. Userspace (and the kernel) gets dma_fence B out of this > > - because unfortunate reasons, the same rendering on device B also > > needs a userptr buffer, which means that dma_fence B is also the one > > that the mmu_range_notifier needs to wait on before it can tell core > > mm that it can go ahead and release those pages > > I was afraid you'd say this - this is complete madness for other DMA > devices to borrow the notifier hook of the first device! The first device might not even have a notifier. This is the 2nd device, waiting on a dma_fence of its own, but which happens to be queued up as a dma operation behind something else. > What if the first device is a page faulting device and doesn't call > dma_fence?? Not sure what you mean with this ... even if it does page-faulting for some other reasons, it'll emit a dma_fence which the 2nd device can consume as a dependency. > It you are going to treat things this way then the mmu notifier really > needs to be part of the some core DMA buf, and not randomly sprinkled > in drivers So maybe again unclear, we don't allow such userptr dma-buf to even be shared. They're just for slurping in stuff in the local device (general from file io or something the cpu has done or similar). There have been attempts to use it as the general backing storage, but that didn't go down too well because way too many complications. Generally most memory the gpu operates on isn't stuff that's mmu_notifier'ed. And also, the device with userptr support only waits for its own dma_fence (because well you can't share this stuff, we disallow that). The problem is that there's piles of other dependencies for a dma job. GPU doesn't just consume a single buffer each time, it consumes entire lists of buffers and mixes them all up in funny ways. Some of these buffers are userptr, entirely local to the device. Other buffers are just normal device driver allocations (and managed with some shrinker to keep them in check). And then there's the actually shared dma-buf with other devices. The trouble is that they're all bundled up together. Now we probably should have some helper code for userptr so that all drivers do this roughly the same, but that's just not there yet. But it can't be a dma-buf exporter behind the dma-buf interfaces, because even just pinned get_user_pages would be too different semantics compared to normal shared dma-buf objects, that's all very tightly tied into the specific driver. > But really this is what page pinning is supposed to be used for, the > MM behavior when it blocks on a pinned page is less invasive than if > it stalls inside a mmu notifier. > > You can mix it, use mmu notififers to keep track if the buffer is > still live, but when you want to trigger DMA then pin the pages and > keep them pinned until DMA is done. The pin protects things (well, > fork is still a problem) Hm I thought amdgpu had that (or drm/radeon as the previous incarnation of that stack), and was unhappy about the issues. Would need Christian K?nig to chime in. > Do not need to wait on dma_fence in notifiers. Maybe :-) The goal of this series is more to document current rules and make them more consistent. Fixing them if we don't like them might be a follow-up task, but that would likely be a pile more work. First we need to know what the exact shape of the problem even is. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Fri Jun 19 15:13:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 15:13:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgVlJS?= =?utf-8?q?_capable_attach_prop_in_i915=2C_DPCD_helper=2C_VRR_debugfs_=28r?= =?utf-8?q?ev3=29?= In-Reply-To: <20200619212356.19285-1-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> Message-ID: <159257962142.12533.6961184573185663134@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, DPCD helper, VRR debugfs (rev3) URL : https://patchwork.freedesktop.org/series/78278/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8645 -> Patchwork_17994 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17994 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17994, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17994/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17994: ### IGT changes ### #### Possible regressions #### * igt at kms_chamelium@dp-hpd-fast: - fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17994/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html Known issues ------------ Here are the changes found in Patchwork_17994 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17994/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17994/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 10) ------------------------------ ERROR: It appears as if the changes made in Patchwork_17994 prevented too many machines from booting. Missing (34): fi-kbl-soraka fi-icl-u2 fi-snb-2520m fi-apl-guc fi-icl-y fi-icl-guc fi-icl-dsi fi-byt-n2820 fi-skl-6600u fi-snb-2600 fi-bxt-dsi fi-cml-s fi-byt-j1900 fi-bsw-n3050 fi-glk-dsi fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-kbl-7560u fi-bsw-nick fi-ilk-m540 fi-ehl-1 fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-whl-u fi-kbl-x1275 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8645 -> Patchwork_17994 CI-20190529: 20190529 CI_DRM_8645: 9aae33db6b7490634fe14c866077c97fe7263e0a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17994: b8d579bd6450321c0431ef9d0cac0ad9b8f551b9 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b8d579bd6450 drm/debug: Expose connector VRR monitor range via debugfs 8ab5efcf7756 drm/i915/dp: Attach and set drm connector VRR property d029f13253a7 drm/dp: DRM DP helper for reading Ignore MSA from DPCD == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17994/index.html From maarten.lankhorst at linux.intel.com Fri Jun 19 15:19:28 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Fri, 19 Jun 2020 17:19:28 +0200 Subject: [Intel-gfx] [PULL] drm-misc-next Message-ID: <001cd9a6-405d-4e29-43d8-354f53ae4e8b@linux.intel.com> drm-misc-next-2020-06-19: drm-misc-next for v5.9: UAPI Changes: - Add DRM_MODE_TYPE_USERDEF for video modes specified in cmdline. Cross-subsystem Changes: - Assorted devicetree binding updates. - Add might_sleep() to dma_fence_wait(). - Fix fbdev's get_user_pages_fast() handling, and use pin_user_pages. - Small cleanup with IS_BUILTIN in video/fbdev drivers. - Fix video/hdmi coding style for infoframe size. Core Changes: - Silence vblank output during init. - Fix DP-MST corruption during send msg timeout. - Clear leak in drm_gem_objecs_lookup(). - Make newlines work with force connector attribute. - Fix module refcounting error in drm_encoder_slave, and use new i2c api. - Header fix for drm_managed.c - More struct_mutex removal for !legacy drivers: - Remove gem_free_object() - Removal of drm_gem_object_put_unlocked(). - Show current->comm alongside pid in debug printfs. - Add drm_client_modeset_check() + drm_client_framebuffer_flush(). - Replace drm_fb_swab16 with drm_fb_swap that also supports 32-bits. - Remove mode->vrefresh, and compactify drm_display_mode. - Use drm_* macros for logging and warnings. - Add WARN when drm_gem_get_pages is used on a private obj. - Handle importing and imported dmabuf better in shmem helpers. - Small fix for drm/mm hole size comparison, and remove invalid entry optimization. - Add a drm/mm selftest. - Set DSI connector type for DSI panels. - Assorted small fixes and documentation updates. - Fix DDI I2C device registration for MST ports, and flushing on destroy. - Fix master_set return type, used by vmwgfx. - Make the drm_set/drop_master ioctl symmetrical. Driver Changes: Allow iommu in the sun4i driver and use it for sun8i. - Simplify backlight lookup for omap, amba-clcd and tilcdc. - Hold reg_lock for rockchip. - Add support for bridge gpio and lane reordering + polarity to ti-sn65dsi86, and fix clock choice. - Small assorted fixes to tilcdc, vc4, i915, omap, fbdev/sm712fb, fbdev/pxafb, console/newport_con, msm, virtio, udl, malidp, hdlcd, bridge/ti-sn65dsi86, panfrost. - Remove hw cursor support for mgag200, and use simple kms helper + shmem helpers. - Add support for KOE Allow iommu in the sun4i driver and use it for sun8i. - Simplify backlight lookup for omap, amba-clcd and tilcdc. - Hold reg_lock for rockchip. - Add support for bridge gpio and lane reordering + polarity to ti-sn65dsi86, and fix clock choice. - Small assorted fixes to tilcdc, vc4 (multiple), i915. - Remove hw cursor support for mgag200, and use simple kms helper + shmem helpers. - Add support for KOE TX26D202VM0BWA panel. - Use GEM CMA functions in arc, arm, atmel-hlcdc, fsi-dcu, hisilicon, imx, ingenic, komeda, malidp, mcde, meson, msxfb, rcar-du, shmobile, stm, sti, tilcdc, tve200, zte. - Remove gem_print_info. - Improve gem_create_object_helper so udl can use shmem helpers. - Convert vc4 dt bindings to schemas, and add clock properties. - Device initialization cleanups for mgag200. - Add a workaround to fix DP-MST short pulses handling on broken hardware in i915. - Allow build test compiling arm drivers. - Use managed pci functions in mgag200 and ast. - Use dev_groups in malidp. - Add per pixel alpha support for PX30 VOP in rockchip. - Silence deferred probe logs in panfrost. The following changes since commit 1c530d431c698f156538b8954b07df95337beb34: dma-buf: Use atomic_fetch_add() for the context id (2020-05-13 13:38:59 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2020-06-19 for you to fetch changes up to 114427b8927a4def2942b2b886f7e4aeae289ccb: drm/panfrost: Use kvfree() to free bo->sgts (2020-06-19 11:00:02 +0100) ---------------------------------------------------------------- drm-misc-next for v5.9: UAPI Changes: - Add DRM_MODE_TYPE_USERDEF for video modes specified in cmdline. Cross-subsystem Changes: - Assorted devicetree binding updates. - Add might_sleep() to dma_fence_wait(). - Fix fbdev's get_user_pages_fast() handling, and use pin_user_pages. - Small cleanup with IS_BUILTIN in video/fbdev drivers. - Fix video/hdmi coding style for infoframe size. Core Changes: - Silence vblank output during init. - Fix DP-MST corruption during send msg timeout. - Clear leak in drm_gem_objecs_lookup(). - Make newlines work with force connector attribute. - Fix module refcounting error in drm_encoder_slave, and use new i2c api. - Header fix for drm_managed.c - More struct_mutex removal for !legacy drivers: - Remove gem_free_object() - Removal of drm_gem_object_put_unlocked(). - Show current->comm alongside pid in debug printfs. - Add drm_client_modeset_check() + drm_client_framebuffer_flush(). - Replace drm_fb_swab16 with drm_fb_swap that also supports 32-bits. - Remove mode->vrefresh, and compactify drm_display_mode. - Use drm_* macros for logging and warnings. - Add WARN when drm_gem_get_pages is used on a private obj. - Handle importing and imported dmabuf better in shmem helpers. - Small fix for drm/mm hole size comparison, and remove invalid entry optimization. - Add a drm/mm selftest. - Set DSI connector type for DSI panels. - Assorted small fixes and documentation updates. - Fix DDI I2C device registration for MST ports, and flushing on destroy. - Fix master_set return type, used by vmwgfx. - Make the drm_set/drop_master ioctl symmetrical. Driver Changes: Allow iommu in the sun4i driver and use it for sun8i. - Simplify backlight lookup for omap, amba-clcd and tilcdc. - Hold reg_lock for rockchip. - Add support for bridge gpio and lane reordering + polarity to ti-sn65dsi86, and fix clock choice. - Small assorted fixes to tilcdc, vc4, i915, omap, fbdev/sm712fb, fbdev/pxafb, console/newport_con, msm, virtio, udl, malidp, hdlcd, bridge/ti-sn65dsi86, panfrost. - Remove hw cursor support for mgag200, and use simple kms helper + shmem helpers. - Add support for KOE Allow iommu in the sun4i driver and use it for sun8i. - Simplify backlight lookup for omap, amba-clcd and tilcdc. - Hold reg_lock for rockchip. - Add support for bridge gpio and lane reordering + polarity to ti-sn65dsi86, and fix clock choice. - Small assorted fixes to tilcdc, vc4 (multiple), i915. - Remove hw cursor support for mgag200, and use simple kms helper + shmem helpers. - Add support for KOE TX26D202VM0BWA panel. - Use GEM CMA functions in arc, arm, atmel-hlcdc, fsi-dcu, hisilicon, imx, ingenic, komeda, malidp, mcde, meson, msxfb, rcar-du, shmobile, stm, sti, tilcdc, tve200, zte. - Remove gem_print_info. - Improve gem_create_object_helper so udl can use shmem helpers. - Convert vc4 dt bindings to schemas, and add clock properties. - Device initialization cleanups for mgag200. - Add a workaround to fix DP-MST short pulses handling on broken hardware in i915. - Allow build test compiling arm drivers. - Use managed pci functions in mgag200 and ast. - Use dev_groups in malidp. - Add per pixel alpha support for PX30 VOP in rockchip. - Silence deferred probe logs in panfrost. ---------------------------------------------------------------- Bernard Zhao (1): drivers: video: hdmi: cleanup coding style in video a bit Chris Wilson (5): drm: Include internal header for managed function declarations drm: Help unconfuse gcc, avoid accidental impossible unsigned comparisons drm: Describe dp_rev for drm_dp_set_phy_test_pattern drm: Match drm_dp_send_clear_payload_id_table definition to declaration drm: Restore the NULL check for drm_gem_object_put() Christian K?nig (1): drm/mm: remove invalid entry based optimization Christophe JAILLET (1): video: pxafb: Fix the function used to balance a 'dma_alloc_coherent()' call Colin Ian King (1): drm/auth: remove redundant assignment to variable ret Dan Carpenter (1): drm/gem: Fix a leak in drm_gem_objects_lookup() Daniel Vetter (17): dma-fence: add might_sleep annotation to _wait() drm/writeback: don't set fence->ops to default drm: use drm_dev_has_vblank more drm/msm: Don't call dma_buf_vunmap without _vmap drm/gem: WARN if drm_gem_get_pages is called on a private obj drm/doc: Some polish for shmem helpers drm/virtio: Call the right shmem helpers drm/udl: Don't call get/put_pages on imported dma-buf drm/shmem-helpers: Don't call get/put_pages on imported dma-buf in vmap drm/shmem-helpers: Redirect mmap for imported dma-buf drm/malidp: Don't call drm_crtc_vblank_off on unbind drm/hdlcd: Don't call drm_crtc_vblank_off on unbind drm/shmem-helpers: Ensure get_pages is not called on imported dma-buf drm/shmem-helpers: Simplify dma-buf importing drm/ast: Use managed pci functions drm/shmem-helper: Fix obj->filp derefence drm/shmem-helper: Only dma-buf imports are private obj Dejin Zheng (2): video: fbdev: sm712fb: fix an issue about iounmap for a wrong address console: newport_con: fix an issue about leak related system resources Denis Efremov (1): drm/panfrost: Use kvfree() to free bo->sgts Dinghao Liu (1): drm/panfrost: Fix runtime PM imbalance on error Douglas Anderson (10): drm/bridge: ti-sn65dsi86: Export bridge GPIOs to Linux dt-bindings: drm/bridge: ti-sn65dsi86: Convert to yaml dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd drm/bridge: ti-sn65dsi86: Clear old error bits before AUX transfers drm/bridge: ti-sn65dsi86: Fix off-by-one error in clock choice drm/bridge: ti-sn65dsi86: Implement lane reordering + polarity drm/bridge: ti-sn65dsi86: Don't compile GPIO bits if not CONFIG_OF_GPIO drm/bridge: ti-sn65dsi86: Don't use kernel-doc comment for local array drm/bridge: ti-sn65dsi86: Fix kernel-doc typo ln_polr => ln_polrs drm/bridge: ti-sn65dsi86: Check the regmap return value when setting a GPIO Emil Velikov (46): drm/rockchip: vop: call vop_cfg_done() under reg_lock drm: remove unused drm_gem.h include drm/gem: use _unlocked reference in drm_gem_objects_lookup docs drm/todo: mention i915 in the struct_mutex section drm/doc: drop struct_mutex references drm/doc: add WARNING for drm_device::struct_mutex drm/doc: drop struct_mutex reference for drm_gem_object_free drm/amdgpu: use the unlocked drm_gem_object_put drm/gma500: Use lockless gem BO free callback drm: remove drm_driver::gem_free_object drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() drm/gem: add _locked suffix to drm_gem_object_put drm/gem: add drm_gem_object_put helper drm: remove _unlocked suffix in drm_gem_object_put_unlocked drm/amd: remove _unlocked suffix in drm_gem_object_put_unlocked drm/arm: remove _unlocked suffix in drm_gem_object_put_unlocked drm/armada: remove _unlocked suffix in drm_gem_object_put_unlocked drm/etnaviv: remove _unlocked suffix in drm_gem_object_put_unlocked drm/exynos: remove _unlocked suffix in drm_gem_object_put_unlocked drm/gma500: remove _unlocked suffix in drm_gem_object_put_unlocked drm/i915: remove _unlocked suffix in drm_gem_object_put_unlocked drm/lima: remove _unlocked suffix in drm_gem_object_put_unlocked drm/mediatek: remove _unlocked suffix in drm_gem_object_put_unlocked drm/mgag200: remove _unlocked suffix in drm_gem_object_put_unlocked drm/msm: remove _unlocked suffix in drm_gem_object_put_unlocked drm/nouveau: remove _unlocked suffix in drm_gem_object_put_unlocked drm/omapdrm: remove _unlocked suffix in drm_gem_object_put_unlocked drm/panfrost: remove _unlocked suffix in drm_gem_object_put_unlocked drm/qxl: remove _unlocked suffix in drm_gem_object_put_unlocked drm/radeon: remove _unlocked suffix in drm_gem_object_put_unlocked drm/rockchip: remove _unlocked suffix in drm_gem_object_put_unlocked drm/tegra: remove _unlocked suffix in drm_gem_object_put_unlocked drm/v3d: remove _unlocked suffix in drm_gem_object_put_unlocked drm/vc4: remove _unlocked suffix in drm_gem_object_put_unlocked drm/vgem: remove _unlocked suffix in drm_gem_object_put_unlocked drm/virtio: remove _unlocked suffix in drm_gem_object_put_unlocked drm/vkms: remove _unlocked suffix in drm_gem_object_put_unlocked drm/xen: remove _unlocked suffix in drm_gem_object_put_unlocked drm: remove transient drm_gem_object_put_unlocked() drm: print the current->comm alongside the pid drm/file: wrap excessively long line drm: vmwgfx: remove drm_driver::master_set() return type drm/auth: make drm_{set,drop}master_ioctl symmetrical drm/todo: Add item about modeset properties drm/arm: Kconfig annotate drivers as COMPILE_TEST drm/malidp: convert platform driver to use dev_groups Hans de Goede (1): drm: Add DRM_MODE_TYPE_USERDEF flag to probed modes matching a video= argument Imre Deak (6): drm/dp_mst: Fix timeout handling of MST down messages drm/dp_mst: Sanitize mgr->qlock locking in drm_dp_mst_wait_tx_reply() drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses drm/dp_mst: Fix the DDC I2C device unregistration of an MST port drm/dp_mst: Fix the DDC I2C device registration of an MST port drm/dp_mst: Fix flushing the delayed port/mstb destroy work James Hilliard (1): drm/vc4: hdmi: Silence pixel clock error on -EPROBE_DEFER Jason Yan (1): omapfb/dss: fix comparison to bool warning Joe Perches (1): video: fbdev: Use IS_BUILTIN John Hubbard (2): video: fbdev: fix error handling for get_user_pages_fast() video: fbdev: convert get_user_pages() --> pin_user_pages() Kieran Bingham (1): drivers: gpu: drm: Fix trivial spelling Krzysztof Kozlowski (1): drm/panfrost: Reduce the amount of logs on deferred probe Laurent Pinchart (1): drm/panel: simple: Set connector type for DSI panels Liu Ying (2): dt-bindings: panel-simple: Add koe,tx26d202vm0bwa compatible drm/panel: simple: Add support for KOE TX26D202VM0BWA panel Lyude Paul (1): drm/vblank: Fix -Wformat compile warnings on some arches Masanari Iida (1): drm/kselftest: fix spellint typo in test-drm_mm.c Maxime Ripard (14): dt-bindings: display: sun8i-mixer: Allow for an iommu property drm/sun4i: mixer: Call of_dma_configure if there's an IOMMU dt-bindings: display: Convert VC4 bindings to schemas dt-bindings: display: vc4: dpi: Add missing clock-names property dt-bindings: display: vc4: dsi: Add missing clock properties dt-bindings: display: vc4: hdmi: Add missing clock-names property drm/vc4: drv: Add include guards drm/vc4: plane: Move planes creation to its own function drm/vc4: plane: Move additional planes creation to driver drm/vc4: crtc: Rename SoC data structures drm/vc4: crtc: Switch to of_device_get_match_data drm/vc4: crtc: Move crtc state to common header drm/vc4: crtc: Turn static const variable into a define drm/vc4: crtc: Restrict HACT_ACT setup to DSI Michael Tretter (1): drm/debugfs: fix plain echo to connector "force" attribute Nirmoy Das (2): drm/mm: fix hole size comparison drm/mm: add ig_frag selftest Noralf Tr?nnes (3): drm/client: Add drm_client_framebuffer_flush() drm/client: Add drm_client_modeset_check() drm/format-helper: Add drm_fb_swab() Paul Kocialkowski (1): drm/rockchip: Add per-pixel alpha support for the PX30 VOP Sam Ravnborg (5): drm/omap: display: use devm_of_find_backlight drm/tilcdc: use devm_of_find_backlight video: amba-clcd: use devm_of_find_backlight drm/vblank: use drm_* functions for logging drm/vblank: use drm_WARN for all warnings Sidong Yang (1): Documentation: Fix typo error in todo.rst Simon Ser (3): drm: DPMS is no longer the only mutable connector prop drm: add docs for standard CRTC properties drm: document how user-space should use link-status Steven Price (1): drm/panfrost: Fix inbalance of devfreq record_busy/idle() Thomas Zimmermann (74): drm/mgag200: Remove HW cursor drm/mgag200: Clean up mga_set_start_address() drm/mgag200: Clean up mga_crtc_do_set_base() drm/mgag200: Move mode-setting code into separate helper function drm/mgag200: Split MISC register update into PLL selection, SYNC and I/O drm/mgag200: Update mode registers after plane registers drm/mgag200: Set pitch in a separate helper function drm/mgag200: Set primary plane's format in separate helper function drm/mgag200: Move TAGFIFO reset into separate function drm/mgag200: Move hiprilvl setting into separate functions drm/mgag200: Move register initialization into separate function drm/mgag200: Remove out-commented suspend/resume helpers drm/mgag200: Use simple-display data structures drm/mgag200: Convert to simple KMS helper drm/mgag200: Replace VRAM helpers with SHMEM helpers drm/cma-helper: Rename symbols from drm_cma_gem_ to drm_gem_cma_ drm/cma-helper: Rework DRM_GEM_CMA_VMAP_DRIVER_OPS macro drm/cma-helper: Add DRM_GEM_CMA_DRIVER_OPS to set default GEM CMA functions drm/arc: Use GEM CMA object functions drm/arc: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/arm: Use GEM CMA object functions drm/arm: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/atmel-hlcdc: Use GEM CMA object functions drm/atmel-hlcdc: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/fsl-dcu: Use GEM CMA object functions drm/fsl-dcu: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/hisilicon/kirin: Set .dumb_create to drm_gem_cma_dumb_create() drm/hisilicon/kirin: Use GEM CMA object functions drm/hisilicon/kirin: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/imx: Use GEM CMA object functions drm/imx: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/ingenic: Use GEM CMA object functions drm/ingenic: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/komeda: Use GEM CMA object functions drm/komeda: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE drm/malidp: Use GEM CMA object functions drm/malidp: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE drm/mcde: Use GEM CMA object functions drm/mcde: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/meson: Use GEM CMA object functions drm/meson: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE drm/mxsfb: Use GEM CMA object functions drm/mxsfb: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/rcar-du: Use GEM CMA object functions drm/rcar-du: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE drm/shmobile: Use GEM CMA object functions drm/shmobile: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/stm: Use GEM CMA object functions drm/stm: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE drm/sti: Use GEM CMA object functions drm/sti: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/tilcdc: Use GEM CMA object functions drm/tilcdc: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/tve200: Use GEM CMA object functions drm/tve200: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm/zte: Use GEM CMA object functions drm/zte: Set GEM CMA functions with DRM_GEM_CMA_DRIVER_OPS drm: Remove struct drm_driver.gem_print_info drm/shmem-helper: Add .gem_create_object helper that sets map_cached flag drm/udl: Use GEM vmap/mmap function from SHMEM helpers drm/mgag200: Remove declaration of mgag200_mmap() from header file drm/mgag200: Remove mgag200_cursor.c drm/mgag200: Use pcim_enable_device() drm/mgag200: Rename mgag200_ttm.c to mgag200_mm.c drm/mgag200: Lookup VRAM PCI BAR start and length only once drm/mgag200: Merge VRAM setup into MM initialization drm/mgag200: Switch to managed MM drm/mgag200: Separate DRM and PCI functionality from each other drm/mgag200: Prefix symbol names in mgag200_drv.c with mgag200_ drm/mgag200: Move device init and cleanup to mgag200_drv.c drm/mgag200: Separate device initialization into allocation drm/mgag200: Allocate device structures in mgag200_driver_load() drm/mgag200: Embed instance of struct drm_device in struct mga_device drm/mgag200: Use managed device initialization Tiezhu Yang (1): video: fbdev: pxafb: Use correct return value for pxafb_probe() Tomi Valkeinen (3): drm/tilcdc: fix leak & null ref in panel_connector_get_modes drm/tilcdc: remove unnecessary state->fb check drm/tilcdc: add missing static for panel_driver Ville Syrj?l? (11): drm/i915: Introduce some local intel_dp variables drm: Nuke mode->vrefresh drm/msm/dpu: Stop copying around mode->private_flags drm: Shrink {width,height}_mm to u16 drm: Shrink mode->type to u8 drm: Make mode->flags u32 drm: Shrink drm_display_mode timings drm: Flatten drm_mode_vrefresh() drm: pahole struct drm_display_mode drm/mcde: Use mode->clock instead of reverse calculating it from the vrefresh drm/gma500: Stop using mode->private_flags Wolfram Sang (3): drm/vblank: remove outdated and noisy output drm: encoder_slave: fix refcouting error for modules drm: encoder_slave: use new I2C API .../display/allwinner,sun8i-a83t-de2-mixer.yaml | 3 + .../devicetree/bindings/display/brcm,bcm-vc4.txt | 174 ---- .../bindings/display/brcm,bcm2835-dpi.yaml | 72 ++ .../bindings/display/brcm,bcm2835-dsi0.yaml | 84 ++ .../bindings/display/brcm,bcm2835-hdmi.yaml | 80 ++ .../bindings/display/brcm,bcm2835-hvs.yaml | 37 + .../bindings/display/brcm,bcm2835-pixelvalve0.yaml | 40 + .../bindings/display/brcm,bcm2835-txp.yaml | 37 + .../bindings/display/brcm,bcm2835-v3d.yaml | 42 + .../bindings/display/brcm,bcm2835-vc4.yaml | 34 + .../bindings/display/brcm,bcm2835-vec.yaml | 44 ++ .../bindings/display/bridge/ti,sn65dsi86.txt | 87 -- .../bindings/display/bridge/ti,sn65dsi86.yaml | 293 +++++++ .../bindings/display/panel/panel-simple.yaml | 2 + Documentation/gpu/drm-kms-helpers.rst | 12 - Documentation/gpu/drm-kms.rst | 6 + Documentation/gpu/drm-mm.rst | 17 +- Documentation/gpu/todo.rst | 58 +- MAINTAINERS | 2 +- drivers/dma-buf/dma-fence.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 20 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +- drivers/gpu/drm/arc/arcpgu_drv.c | 12 +- drivers/gpu/drm/arm/Kconfig | 4 +- .../drm/arm/display/komeda/komeda_framebuffer.c | 6 +- drivers/gpu/drm/arm/display/komeda/komeda_kms.c | 11 +- drivers/gpu/drm/arm/hdlcd_drv.c | 15 +- drivers/gpu/drm/arm/malidp_drv.c | 45 +- drivers/gpu/drm/armada/armada_crtc.c | 8 +- drivers/gpu/drm/armada/armada_fb.c | 4 +- drivers/gpu/drm/armada/armada_fbdev.c | 6 +- drivers/gpu/drm/armada/armada_gem.c | 10 +- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 2 +- drivers/gpu/drm/ast/ast_drv.c | 10 +- drivers/gpu/drm/ast/ast_main.c | 3 - drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 11 +- drivers/gpu/drm/bridge/sii902x.c | 2 +- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 323 +++++++- drivers/gpu/drm/drm_atomic_helper.c | 2 +- drivers/gpu/drm/drm_auth.c | 46 +- drivers/gpu/drm/drm_client.c | 35 +- drivers/gpu/drm/drm_client_modeset.c | 42 +- drivers/gpu/drm/drm_connector.c | 29 +- drivers/gpu/drm/drm_crtc.c | 27 + drivers/gpu/drm/drm_debugfs.c | 8 +- drivers/gpu/drm/drm_dp_helper.c | 3 +- drivers/gpu/drm/drm_dp_mst_topology.c | 94 ++- drivers/gpu/drm/drm_edid.c | 328 ++++---- drivers/gpu/drm/drm_encoder_slave.c | 15 +- drivers/gpu/drm/drm_file.c | 10 +- drivers/gpu/drm/drm_format_helper.c | 61 +- drivers/gpu/drm/drm_gem.c | 84 +- drivers/gpu/drm/drm_gem_cma_helper.c | 20 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 6 +- drivers/gpu/drm/drm_gem_shmem_helper.c | 172 ++-- drivers/gpu/drm/drm_gem_ttm_helper.c | 2 +- drivers/gpu/drm/drm_gem_vram_helper.c | 10 +- drivers/gpu/drm/drm_ioc32.c | 4 +- drivers/gpu/drm/drm_ioctl.c | 11 +- drivers/gpu/drm/drm_irq.c | 2 +- drivers/gpu/drm/drm_managed.c | 2 + drivers/gpu/drm/drm_mipi_dbi.c | 2 +- drivers/gpu/drm/drm_mm.c | 6 +- drivers/gpu/drm/drm_modes.c | 40 +- drivers/gpu/drm/drm_prime.c | 6 +- drivers/gpu/drm/drm_probe_helper.c | 5 +- drivers/gpu/drm/drm_vblank.c | 215 ++--- drivers/gpu/drm/drm_vm.c | 1 - drivers/gpu/drm/drm_writeback.c | 1 - drivers/gpu/drm/etnaviv/etnaviv_drv.c | 8 +- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 6 +- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 2 +- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_gem.c | 4 +- drivers/gpu/drm/exynos/exynos_drm_gem.h | 2 +- drivers/gpu/drm/exynos/exynos_hdmi.c | 5 +- drivers/gpu/drm/exynos/exynos_mixer.c | 2 +- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 11 +- drivers/gpu/drm/gma500/framebuffer.c | 2 +- drivers/gpu/drm/gma500/gem.c | 2 +- drivers/gpu/drm/gma500/gma_display.c | 6 +- drivers/gpu/drm/gma500/psb_drv.c | 2 +- drivers/gpu/drm/gma500/psb_intel_drv.h | 19 - drivers/gpu/drm/gma500/psb_intel_sdvo.c | 11 +- drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 12 +- drivers/gpu/drm/i2c/ch7006_mode.c | 1 - drivers/gpu/drm/i915/display/intel_display.c | 1 - .../gpu/drm/i915/display/intel_display_debugfs.c | 4 +- drivers/gpu/drm/i915/display/intel_dp.c | 24 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 + drivers/gpu/drm/i915/display/intel_hotplug.c | 18 + drivers/gpu/drm/i915/display/intel_hotplug.h | 2 + drivers/gpu/drm/i915/display/intel_tv.c | 3 - drivers/gpu/drm/imx/imx-drm-core.c | 12 +- drivers/gpu/drm/ingenic/ingenic-drm.c | 13 +- drivers/gpu/drm/lima/lima_gem.c | 10 +- drivers/gpu/drm/lima/lima_sched.c | 2 +- drivers/gpu/drm/mcde/mcde_drv.c | 12 +- drivers/gpu/drm/mcde/mcde_dsi.c | 7 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_gem.c | 2 +- drivers/gpu/drm/mediatek/mtk_hdmi.c | 2 +- drivers/gpu/drm/meson/meson_drv.c | 15 +- drivers/gpu/drm/meson/meson_venc_cvbs.c | 2 - drivers/gpu/drm/mgag200/Kconfig | 4 +- drivers/gpu/drm/mgag200/Makefile | 3 +- drivers/gpu/drm/mgag200/mgag200_cursor.c | 319 -------- drivers/gpu/drm/mgag200/mgag200_drv.c | 204 ++--- drivers/gpu/drm/mgag200/mgag200_drv.h | 56 +- drivers/gpu/drm/mgag200/mgag200_main.c | 160 ---- drivers/gpu/drm/mgag200/mgag200_mm.c | 127 +++ drivers/gpu/drm/mgag200/mgag200_mode.c | 875 ++++++++++++--------- drivers/gpu/drm/mgag200/mgag200_reg.h | 11 +- drivers/gpu/drm/mgag200/mgag200_ttm.c | 70 -- drivers/gpu/drm/msm/adreno/a5xx_debugfs.c | 4 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 4 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 2 +- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +- drivers/gpu/drm/msm/msm_drv.c | 8 +- drivers/gpu/drm/msm/msm_fb.c | 4 +- drivers/gpu/drm/msm/msm_gem.c | 24 +- drivers/gpu/drm/msm/msm_gem_submit.c | 2 +- drivers/gpu/drm/msm/msm_gpu.c | 2 +- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 11 +- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 2 +- drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 +- drivers/gpu/drm/nouveau/nouveau_connector.c | 5 +- drivers/gpu/drm/nouveau/nouveau_display.c | 8 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 14 +- drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c | 18 +- drivers/gpu/drm/omapdrm/omap_drv.c | 2 +- drivers/gpu/drm/omapdrm/omap_fb.c | 2 +- drivers/gpu/drm/omapdrm/omap_fbdev.c | 2 +- drivers/gpu/drm/omapdrm/omap_gem.c | 4 +- drivers/gpu/drm/panel/panel-arm-versatile.c | 4 - .../gpu/drm/panel/panel-asus-z00t-tm5p5-n35596.c | 1 - drivers/gpu/drm/panel/panel-boe-himax8279d.c | 3 +- drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 7 +- drivers/gpu/drm/panel/panel-elida-kd35t133.c | 3 +- drivers/gpu/drm/panel/panel-feixin-k101-im2ba02.c | 3 +- .../gpu/drm/panel/panel-feiyang-fy07024di26a30d.c | 3 +- drivers/gpu/drm/panel/panel-ilitek-ili9322.c | 7 - drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 3 +- drivers/gpu/drm/panel/panel-innolux-p079zca.c | 4 +- drivers/gpu/drm/panel/panel-jdi-lt070me05000.c | 3 +- drivers/gpu/drm/panel/panel-kingdisplay-kd097d04.c | 3 +- drivers/gpu/drm/panel/panel-leadtek-ltk500hd1829.c | 3 +- drivers/gpu/drm/panel/panel-lg-lb035q02.c | 1 - drivers/gpu/drm/panel/panel-lg-lg4573.c | 3 +- drivers/gpu/drm/panel/panel-nec-nl8048hl11.c | 1 - drivers/gpu/drm/panel/panel-novatek-nt35510.c | 1 - drivers/gpu/drm/panel/panel-novatek-nt39016.c | 2 - drivers/gpu/drm/panel/panel-olimex-lcd-olinuxino.c | 1 - drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 3 +- drivers/gpu/drm/panel/panel-osd-osd101t2587-53ts.c | 3 +- .../gpu/drm/panel/panel-panasonic-vvx10f034n00.c | 3 +- .../gpu/drm/panel/panel-raspberrypi-touchscreen.c | 4 +- drivers/gpu/drm/panel/panel-raydium-rm67191.c | 3 +- drivers/gpu/drm/panel/panel-raydium-rm68200.c | 3 +- drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c | 5 +- drivers/gpu/drm/panel/panel-ronbo-rb070d30.c | 1 - drivers/gpu/drm/panel/panel-samsung-s6d16d0.c | 6 - drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c | 4 +- drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c | 3 +- drivers/gpu/drm/panel/panel-samsung-s6e63m0.c | 3 +- .../drm/panel/panel-samsung-s6e88a0-ams452ef01.c | 1 - drivers/gpu/drm/panel/panel-seiko-43wvf1g.c | 3 +- drivers/gpu/drm/panel/panel-sharp-lq101r1sx01.c | 3 +- drivers/gpu/drm/panel/panel-sharp-ls037v7dw01.c | 1 - drivers/gpu/drm/panel/panel-sharp-ls043t1le01.c | 3 +- drivers/gpu/drm/panel/panel-simple.c | 132 +--- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 2 +- drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 3 +- drivers/gpu/drm/panel/panel-sony-acx424akp.c | 2 - drivers/gpu/drm/panel/panel-sony-acx565akm.c | 1 - drivers/gpu/drm/panel/panel-tpo-td028ttec1.c | 1 - drivers/gpu/drm/panel/panel-tpo-td043mtea1.c | 1 - drivers/gpu/drm/panel/panel-tpo-tpg110.c | 5 - drivers/gpu/drm/panel/panel-truly-nt35597.c | 1 - drivers/gpu/drm/panel/panel-visionox-rm69299.c | 1 - drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c | 3 +- drivers/gpu/drm/panfrost/panfrost_device.c | 8 +- drivers/gpu/drm/panfrost/panfrost_drv.c | 10 +- drivers/gpu/drm/panfrost/panfrost_gem.c | 6 +- drivers/gpu/drm/panfrost/panfrost_job.c | 8 +- drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 +- drivers/gpu/drm/panfrost/panfrost_perfcnt.c | 4 +- drivers/gpu/drm/qxl/qxl_cmd.c | 2 +- drivers/gpu/drm/qxl/qxl_display.c | 6 +- drivers/gpu/drm/qxl/qxl_dumb.c | 2 +- drivers/gpu/drm/qxl/qxl_gem.c | 2 +- drivers/gpu/drm/qxl/qxl_ioctl.c | 4 +- drivers/gpu/drm/qxl/qxl_object.c | 4 +- drivers/gpu/drm/radeon/radeon_cs.c | 2 +- drivers/gpu/drm/radeon/radeon_cursor.c | 6 +- drivers/gpu/drm/radeon/radeon_display.c | 8 +- drivers/gpu/drm/radeon/radeon_fb.c | 4 +- drivers/gpu/drm/radeon/radeon_gem.c | 30 +- drivers/gpu/drm/radeon/radeon_object.c | 2 +- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 11 +- drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 2 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 8 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 9 + drivers/gpu/drm/selftests/drm_mm_selftests.h | 1 + drivers/gpu/drm/selftests/test-drm_mm.c | 126 ++- drivers/gpu/drm/shmobile/shmob_drm_drv.c | 11 +- drivers/gpu/drm/sti/sti_drv.c | 12 +- drivers/gpu/drm/sti/sti_hda.c | 1 - drivers/gpu/drm/stm/drv.c | 11 +- drivers/gpu/drm/sun4i/sun4i_drv.c | 3 +- drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 + drivers/gpu/drm/tegra/drm.c | 12 +- drivers/gpu/drm/tegra/fb.c | 6 +- drivers/gpu/drm/tegra/gem.c | 4 +- drivers/gpu/drm/tidss/tidss_drv.c | 2 +- drivers/gpu/drm/tilcdc/tilcdc_drv.c | 13 +- drivers/gpu/drm/tilcdc/tilcdc_panel.c | 25 +- drivers/gpu/drm/tilcdc/tilcdc_plane.c | 3 +- drivers/gpu/drm/tiny/hx8357d.c | 2 +- drivers/gpu/drm/tiny/ili9225.c | 2 +- drivers/gpu/drm/tiny/ili9341.c | 2 +- drivers/gpu/drm/tiny/ili9486.c | 2 +- drivers/gpu/drm/tiny/mi0283qt.c | 2 +- drivers/gpu/drm/tiny/repaper.c | 2 +- drivers/gpu/drm/tiny/st7586.c | 2 +- drivers/gpu/drm/tiny/st7735r.c | 2 +- drivers/gpu/drm/tve200/tve200_drv.c | 12 +- drivers/gpu/drm/udl/Makefile | 2 +- drivers/gpu/drm/udl/udl_drv.c | 4 +- drivers/gpu/drm/udl/udl_drv.h | 3 - drivers/gpu/drm/udl/udl_gem.c | 106 --- drivers/gpu/drm/v3d/v3d_bo.c | 6 +- drivers/gpu/drm/v3d/v3d_gem.c | 4 +- drivers/gpu/drm/v3d/v3d_irq.c | 2 +- drivers/gpu/drm/vc4/vc4_bo.c | 14 +- drivers/gpu/drm/vc4/vc4_crtc.c | 82 +- drivers/gpu/drm/vc4/vc4_drv.c | 4 + drivers/gpu/drm/vc4/vc4_drv.h | 26 + drivers/gpu/drm/vc4/vc4_gem.c | 14 +- drivers/gpu/drm/vc4/vc4_hdmi.c | 6 +- drivers/gpu/drm/vc4/vc4_kms.c | 2 +- drivers/gpu/drm/vc4/vc4_plane.c | 41 + drivers/gpu/drm/vc4/vc4_v3d.c | 4 +- drivers/gpu/drm/vgem/vgem_drv.c | 6 +- drivers/gpu/drm/vgem/vgem_fence.c | 2 +- drivers/gpu/drm/virtio/virtgpu_display.c | 2 +- drivers/gpu/drm/virtio/virtgpu_gem.c | 6 +- drivers/gpu/drm/virtio/virtgpu_ioctl.c | 6 +- drivers/gpu/drm/virtio/virtgpu_object.c | 2 +- drivers/gpu/drm/vkms/vkms_gem.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 8 +- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 2 - drivers/gpu/drm/xen/xen_drm_front.c | 4 +- drivers/gpu/drm/zte/zx_drm_drv.c | 11 +- drivers/video/console/newport_con.c | 12 +- drivers/video/fbdev/amba-clcd.c | 19 +- drivers/video/fbdev/aty/aty128fb.c | 6 +- drivers/video/fbdev/aty/atyfb_base.c | 7 +- drivers/video/fbdev/aty/radeon_base.c | 6 +- drivers/video/fbdev/nvidia/nvidia.c | 6 +- drivers/video/fbdev/omap/omapfb_main.c | 6 +- drivers/video/fbdev/omap2/omapfb/dss/dispc.c | 2 +- drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c | 4 +- drivers/video/fbdev/pvr2fb.c | 24 +- drivers/video/fbdev/pxafb.c | 6 +- drivers/video/fbdev/riva/fbdev.c | 6 +- drivers/video/fbdev/s3c2410fb.c | 6 +- drivers/video/fbdev/sm712fb.c | 2 + drivers/video/hdmi.c | 2 +- include/drm/drm_client.h | 2 + include/drm/drm_device.h | 3 + include/drm/drm_dp_helper.h | 2 +- include/drm/drm_dp_mst_helper.h | 17 + include/drm/drm_drv.h | 31 +- include/drm/drm_format_helper.h | 4 +- include/drm/drm_gem.h | 37 +- include/drm/drm_gem_cma_helper.h | 74 +- include/drm/drm_gem_shmem_helper.h | 4 + include/drm/drm_modes.h | 194 +++-- include/linux/hdmi.h | 1 + 294 files changed, 3573 insertions(+), 3142 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml delete mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml delete mode 100644 drivers/gpu/drm/mgag200/mgag200_cursor.c delete mode 100644 drivers/gpu/drm/mgag200/mgag200_main.c create mode 100644 drivers/gpu/drm/mgag200/mgag200_mm.c delete mode 100644 drivers/gpu/drm/mgag200/mgag200_ttm.c delete mode 100644 drivers/gpu/drm/udl/udl_gem.c From chris at chris-wilson.co.uk Fri Jun 19 15:19:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 16:19:38 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Initialise rps timestamp Message-ID: <20200619151938.21740-1-chris@chris-wilson.co.uk> Smatch warns that we may iterate over an empty array of gt->engines[]. One hopes that this is impossible, but nevertheless we can simply appease smatch by initialising the timestamp to zero before we starting probing the engines. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_rps.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index bdece932592b..296391deeb94 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -51,10 +51,11 @@ static void rps_timer(struct timer_list *t) { struct intel_rps *rps = from_timer(rps, t, timer); struct intel_engine_cs *engine; + ktime_t dt, last, timestamp; enum intel_engine_id id; s64 max_busy[3] = {}; - ktime_t dt, timestamp, last; + timestamp = 0; for_each_engine(engine, rps_to_gt(rps), id) { s64 busy; int i; @@ -69,7 +70,6 @@ static void rps_timer(struct timer_list *t) swap(busy, max_busy[i]); } } - last = rps->pm_timestamp; rps->pm_timestamp = timestamp; -- 2.20.1 From patchwork at emeril.freedesktop.org Fri Jun 19 15:41:44 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 15:41:44 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/3=5D_drm/i915/gem=3A_Avoid_kmallo?= =?utf-8?q?c_under_i915-=3Emm=5Flock?= In-Reply-To: <20200619143106.10356-1-chris@chris-wilson.co.uk> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> Message-ID: <159258130499.12534.3688368204961091069@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/gem: Avoid kmalloc under i915->mm_lock URL : https://patchwork.freedesktop.org/series/78643/ State : warning == Summary == $ dim checkpatch origin/drm-tip e219e0a60e23 drm/i915/gem: Avoid kmalloc under i915->mm_lock -:143: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!new" #143: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:332: + if (new == NULL) -:230: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #230: FILE: drivers/gpu/drm/i915/i915_drv.h:991: + spinlock_t mm_lock; total: 0 errors, 0 warnings, 2 checks, 203 lines checked f2a7b9c76cd4 drm/i915/gvt: Drop redundant prepare_write/pin_pages a5bd05750493 drm/i915/gt: Replace manual kmap_atomic() with pin_map for renderstate From patchwork at emeril.freedesktop.org Fri Jun 19 15:42:54 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 15:42:54 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/3=5D_drm/i915/gem=3A_Avoid_kmalloc_un?= =?utf-8?q?der_i915-=3Emm=5Flock?= In-Reply-To: <20200619143106.10356-1-chris@chris-wilson.co.uk> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> Message-ID: <159258137498.12535.2500459880189660239@emeril.freedesktop.org> == Series Details == Series: series starting with [1/3] drm/i915/gem: Avoid kmalloc under i915->mm_lock URL : https://patchwork.freedesktop.org/series/78643/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From daniel at ffwll.ch Fri Jun 19 16:19:41 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 19 Jun 2020 18:19:41 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619151551.GP6578@ziepe.ca> References: <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <20200616120719.GL20149@phenom.ffwll.local> <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> <20200617152835.GF6578@ziepe.ca> <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> Message-ID: <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> On Fri, Jun 19, 2020 at 5:15 PM Jason Gunthorpe <jgg at ziepe.ca> wrote: > > On Fri, Jun 19, 2020 at 05:06:04PM +0200, Daniel Vetter wrote: > > On Fri, Jun 19, 2020 at 1:39 PM Jason Gunthorpe <jgg at ziepe.ca> wrote: > > > > > > On Fri, Jun 19, 2020 at 09:22:09AM +0200, Daniel Vetter wrote: > > > > > As I've understood GPU that means you need to show that the commands > > > > > associated with the buffer have completed. This is all local stuff > > > > > within the driver, right? Why use fence (other than it already exists) > > > > > > > > Because that's the end-of-dma thing. And it's cross-driver for the > > > > above reasons, e.g. > > > > - device A renders some stuff. Userspace gets dma_fence A out of that > > > > (well sync_file or one of the other uapi interfaces, but you get the > > > > idea) > > > > - userspace (across process or just different driver) issues more > > > > rendering for device B, which depends upon the rendering done on > > > > device A. So dma_fence A is an dependency and will block this dma > > > > operation. Userspace (and the kernel) gets dma_fence B out of this > > > > - because unfortunate reasons, the same rendering on device B also > > > > needs a userptr buffer, which means that dma_fence B is also the one > > > > that the mmu_range_notifier needs to wait on before it can tell core > > > > mm that it can go ahead and release those pages > > > > > > I was afraid you'd say this - this is complete madness for other DMA > > > devices to borrow the notifier hook of the first device! > > > > The first device might not even have a notifier. This is the 2nd > > device, waiting on a dma_fence of its own, but which happens to be > > queued up as a dma operation behind something else. > > > > > What if the first device is a page faulting device and doesn't call > > > dma_fence?? > > > > Not sure what you mean with this ... even if it does page-faulting for > > some other reasons, it'll emit a dma_fence which the 2nd device can > > consume as a dependency. > > At some point the pages under the buffer have to be either pinned > or protected by mmu notifier. So each and every single device doing > DMA to these pages must either pin, or use mmu notifier. > > Driver A should never 'borrow' a notifier from B It doesn't. I guess this would be great topic for lpc with a seriously big white-board, but I guess we don't have that this year again, so let me try again. Simplified example ofc, but should be the gist. Ingredients: Device A and Device B A dma-buf, shared between device A and device B, let's call that shared_buf A userptr buffer, which userspace created on device B to hopefully somewhat track a virtual memory range, let's call that userptr_buf. A pile of other buffers, but we pretend they don't exist (because they kinda don't matter. Sequence of events as userspace issues them to the kernel. 1. dma operation on device A, which fills some interesting stuff into shared_buf. Userspace gets back a handle to dma_fence fence_A. No mmu notifier anywhere to be seen in the driver for device A. 2. userspace passes fence_A around to some other place 3. other places takes the handle for shared_buf and fence_A and userptr_buf and starts a dma operation on device B. It's one dma operation, maybe device B is taking the data from shared_buf and compresses it into userptr_buf, so that userspace can then send it over the network or to disk or whatever. device B has a mmu_notifier. Userspace gets back fence_B, which represents this dma operation. The kernel also stuffs this fence_B into the mmu_range_notifier for userptr_buf. -> at this point device A might still be crunching the numbers 4. device A is finally done doing whatever it was supposed to do, and fence_A completes 5. device B wakes up (this might or might not involve the kernel, usually it does) since fence_A has completed, and now starts doing its own crunching. 6. once device B is also done, it signals fence_B In all this device A has never borrowed the mmu notifier or even accessd the memory in userptr_buf or had access to that buffer handle. The madness is only that device B's mmu notifier might need to wait for fence_B so that the dma operation finishes. Which in turn has to wait for device A to finish first. > If each driver controls its own lifetime of the buffers, why can't the > driver locally wait for its device to finish? > > Can't the GPUs cancel work that is waiting on a DMA fence? Ie if > Driver A detects that work completed and wants to trigger a DMA fence, > but it now knows the buffer is invalidated, can't it tell driver B to > give up? We can (usually, the shitty hw where we can't has generally disappeared) with gpu reset. Users make really sad faces when that happens though, and generally they're only ok with that if it's indeed a nasty gpu program that resulted in the crash (there's some webgl shaders that run too long for quick&easy testing of how good the gpu reset is, don't do that if you care about the data in your desktop session ...). The trouble is that userspace assembles the work that's queued up on the gpu. After submission everyone has forgotten enough that just canceling stuff and re-issuing everything isn't on the table. Some hw is better, with real hw page faults and stuff, but those also don't need dma_fence to track their memory. But generally just not possible. > > The problem is that there's piles of other dependencies for a dma job. > > GPU doesn't just consume a single buffer each time, it consumes entire > > lists of buffers and mixes them all up in funny ways. Some of these > > buffers are userptr, entirely local to the device. Other buffers are > > just normal device driver allocations (and managed with some shrinker > > to keep them in check). And then there's the actually shared dma-buf > > with other devices. The trouble is that they're all bundled up > > together. > > But why does this matter? Does the GPU itself consume some work and > then stall internally waiting for an external DMA fence? Yup, see above, that's what's going on. Userspace queues up distributed work across engines & drivers, and then just waits for the entire thing to cascade and finish. > Otherwise I would expect this dependency chain should be breakable by > aborting work waiting on fences upon invalidation (without stalling) Yup, it would. Now on some hw you have a gpu work scheduler that sits in some kthread, and you could probably unschedule the work if there's some external dependency and you get an mmu notifier callback. Then put it on some queue, re-acquire the user pages and then reschedule it. It's still as horrible, since you still have the wait for the completion in there, the only benefit is that other device drivers without userptr support don't have to live with that specific constraint. dma_fence rules are still very strict and easy to deadlock, so we'd still want some lockdep checks, but now you'd have to somehow annotate whether you're a driver with userptr or a driver without userptr and make sure everyone gets it right. Also a scheduler which can unschedule and reschedule is mighty more complex than one which cannot, plus it needs to do that from mmu notifier callback (not the nicest calling context we have in the kernel by far). And if you have a single driver which doesn't unschedule, you're still screwed from an overall subsystem pov. So lots of code, lots of work, and not that much motivation to roll it out consistently across the board since there's no incremental payoff. Plus the thing is, the drivers without userptr are generally the really simple ones. Much easier to just fix those than to change the big complex render beasts which want userptr :-) E.g. the atomic modeset framework we've rolled out in the past few years and that almost all display drivers now use pulls any (sleeping) locks and memory allocations out of the critical async work section by design. Some drivers still managed to butcher it (the annotations caught some locking bugs already, not just memory allocations in the wrong spot), but generally easy to fix those. > > > Do not need to wait on dma_fence in notifiers. > > > > Maybe :-) The goal of this series is more to document current rules > > and make them more consistent. Fixing them if we don't like them might > > be a follow-up task, but that would likely be a pile more work. First > > we need to know what the exact shape of the problem even is. > > Fair enough Full disclosure: We are aware that we've designed ourselves into an impressive corner here, and there's lots of talks going on about untangling the dma synchronization from the memory management completely. But - that needs minimally reliable preempt support for gpu work, and hw engineers seem to have a hard time with that (or just don't want to do it). hw page faults would be even better, and even more wishlist than reality if you expect it to work everywhere. - it'd be a complete break of the established userspace abi, including all the cross driver stuff. Which means it's not just some in-kernel refactoring, we need to rev the entire ecosystem. And that takes a very long time, and needs serious pressure to get people moving. E.g. the atomic modeset rework is still not yet rolled out to major linux desktop environments, and it's over 5 years old, and it's starting to seriously hurt because lots of performance features require atomic modeset in userspace to be able to use them. I think rev'ing the entire memory management support will take as long. Plus I don't think we can ditch the old ways - even if all the hw currently using this would be dead (and we can delete the drivers) there's still the much smaller gpus in SoC that also need to go through the entire evolution. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Fri Jun 19 16:34:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 16:34:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Initialise_rps_timestamp?= In-Reply-To: <20200619151938.21740-1-chris@chris-wilson.co.uk> References: <20200619151938.21740-1-chris@chris-wilson.co.uk> Message-ID: <159258449151.12536.4735841389728666987@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Initialise rps timestamp URL : https://patchwork.freedesktop.org/series/78645/ State : success == Summary == CI Bug Log - changes from CI_DRM_8645 -> Patchwork_17996 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/index.html Known issues ------------ Here are the changes found in Patchwork_17996 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-byt-j1900/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-n2820: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-byt-n2820/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-icl-y: [INCOMPLETE][13] ([i915#1684]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-icl-y/igt at i915_selftest@live at execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-icl-y/igt at i915_selftest@live at execlists.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#1982] / [i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1684]: https://gitlab.freedesktop.org/drm/intel/issues/1684 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8645 -> Patchwork_17996 CI-20190529: 20190529 CI_DRM_8645: 9aae33db6b7490634fe14c866077c97fe7263e0a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17996: 8b7a3b62b511c678ed8bafb3022ea8abdde6df5f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8b7a3b62b511 drm/i915/gt: Initialise rps timestamp == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/index.html From patchwork at emeril.freedesktop.org Fri Jun 19 17:43:17 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 17:43:17 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Initialise_rps_timestamp?= In-Reply-To: <20200619151938.21740-1-chris@chris-wilson.co.uk> References: <20200619151938.21740-1-chris@chris-wilson.co.uk> Message-ID: <159258859749.12536.15615864755230299481@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Initialise rps timestamp URL : https://patchwork.freedesktop.org/series/78645/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8645_full -> Patchwork_17996_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_17996_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_17996_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_17996_full: ### IGT changes ### #### Possible regressions #### * igt at gem_exec_balancer@bonded-early: - shard-kbl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl7/igt at gem_exec_balancer@bonded-early.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl7/igt at gem_exec_balancer@bonded-early.html Known issues ------------ Here are the changes found in Patchwork_17996_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#1930]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@implicit-write-read at rcs0: - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-snb6/igt at gem_exec_schedule@implicit-write-read at rcs0.html * igt at gem_exec_whisper@basic-fds-priority-all: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl7/igt at gem_exec_whisper@basic-fds-priority-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl6/igt at gem_exec_whisper@basic-fds-priority-all.html * igt at i915_module_load@reload: - shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-tglb2/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-tglb5/igt at i915_module_load@reload.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-glk4/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#95]) +11 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-apl3/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-apl2/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html * igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#54]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl8/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl6/igt at kms_cursor_crc@pipe-b-cursor-128x128-sliding.html * igt at kms_flip@flip-vs-expired-vblank at a-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl10/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend at b-edp1: - shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#198]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl3/igt at kms_flip@flip-vs-suspend at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl3/igt at kms_flip@flip-vs-suspend at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-iclb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-iclb1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-tglb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-tglb3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_lease@page_flip_implicit_plane: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +8 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl8/igt at kms_lease@page_flip_implicit_plane.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl9/igt at kms_lease@page_flip_implicit_plane.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][31] -> [FAIL][32] ([fdo#108145] / [i915#265]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl6/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109642] / [fdo#111068]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-iclb2/igt at kms_psr2_su@frontbuffer.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-iclb3/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-iclb8/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][37] -> [FAIL][38] ([i915#1542]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-iclb5/igt at perf@blocking-parameterized.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-iclb8/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_blits@basic: - shard-glk: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-glk7/igt at gem_blits@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-glk8/igt at gem_blits@basic.html * igt at gem_exec_whisper@basic-contexts-all: - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-glk1/igt at gem_exec_whisper@basic-contexts-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-glk7/igt at gem_exec_whisper@basic-contexts-all.html * igt at gem_shrink@reclaim: - shard-hsw: [SKIP][43] ([fdo#109271]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-hsw1/igt at gem_shrink@reclaim.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-hsw4/igt at gem_shrink@reclaim.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [DMESG-WARN][45] ([i915#402]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-tglb3/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_addfb_basic@framebuffer-vs-set-tiling: - shard-apl: [DMESG-WARN][47] ([i915#95]) -> [PASS][48] +13 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-apl7/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-apl3/igt at kms_addfb_basic@framebuffer-vs-set-tiling.html * igt at kms_big_fb@x-tiled-8bpp-rotate-0: - shard-apl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-apl2/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-0.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +4 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl4/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [FAIL][53] ([i915#57]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-hsw8/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_cursor_legacy@cursora-vs-flipa-varying-size: - shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +7 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl10/igt at kms_cursor_legacy@cursora-vs-flipa-varying-size.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl1/igt at kms_cursor_legacy@cursora-vs-flipa-varying-size.html * igt at kms_cursor_legacy@pipe-c-torture-bo: - shard-kbl: [DMESG-WARN][57] ([i915#128]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl6/igt at kms_cursor_legacy@pipe-c-torture-bo.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl6/igt at kms_cursor_legacy@pipe-c-torture-bo.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl5/igt at kms_hdr@bpc-switch.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl5/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-pipe-a-planes: - shard-iclb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-iclb3/igt at kms_plane@plane-panning-bottom-right-pipe-a-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-iclb6/igt at kms_plane@plane-panning-bottom-right-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-iclb: [INCOMPLETE][63] ([i915#1185] / [i915#250]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-iclb3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-iclb3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-iclb1/igt at kms_psr@psr2_cursor_mmap_cpu.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][69] ([i915#1820] / [i915#93] / [i915#95]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl4/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [FAIL][71] ([i915#49]) -> [DMESG-FAIL][72] ([i915#49] / [i915#95]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-apl6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][73] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][74] ([i915#93] / [i915#95]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c: - shard-kbl: [DMESG-WARN][75] ([i915#93] / [i915#95]) -> [DMESG-WARN][76] ([i915#180] / [i915#93] / [i915#95]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-kbl2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-kbl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c.html * igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: [DMESG-FAIL][77] ([i915#95]) -> [FAIL][78] ([i915#265]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8645/shard-apl7/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/shard-apl3/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#57]: https://gitlab.freedesktop.org/drm/intel/issues/57 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8645 -> Patchwork_17996 CI-20190529: 20190529 CI_DRM_8645: 9aae33db6b7490634fe14c866077c97fe7263e0a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17996: 8b7a3b62b511c678ed8bafb3022ea8abdde6df5f @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17996/index.html From jglisse at redhat.com Fri Jun 19 18:09:35 2020 From: jglisse at redhat.com (Jerome Glisse) Date: Fri, 19 Jun 2020 14:09:35 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619172308.GQ6578@ziepe.ca> References: <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> <20200617152835.GF6578@ziepe.ca> <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> Message-ID: <20200619180935.GA10009@redhat.com> On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > > > The madness is only that device B's mmu notifier might need to wait > > for fence_B so that the dma operation finishes. Which in turn has to > > wait for device A to finish first. > > So, it sound, fundamentally you've got this graph of operations across > an unknown set of drivers and the kernel cannot insert itself in > dma_fence hand offs to re-validate any of the buffers involved? > Buffers which by definition cannot be touched by the hardware yet. > > That really is a pretty horrible place to end up.. > > Pinning really is right answer for this kind of work flow. I think > converting pinning to notifers should not be done unless notifier > invalidation is relatively bounded. > > I know people like notifiers because they give a bit nicer performance > in some happy cases, but this cripples all the bad cases.. > > If pinning doesn't work for some reason maybe we should address that? Note that the dma fence is only true for user ptr buffer which predate any HMM work and thus were using mmu notifier already. You need the mmu notifier there because of fork and other corner cases. For nouveau the notifier do not need to wait for anything it can update the GPU page table right away. Modulo needing to write to GPU memory using dma engine if the GPU page table is in GPU memory that is not accessible from the CPU but that's never the case for nouveau so far (but i expect it will be at one point). So i see this as 2 different cases, the user ptr case, which does pin pages by the way, where things are synchronous. Versus the HMM cases where everything is asynchronous. I probably need to warn AMD folks again that using HMM means that you must be able to update the GPU page table asynchronously without fence wait. The issue for AMD is that they already update their GPU page table using DMA engine. I believe this is still doable if they use a kernel only DMA engine context, where only kernel can queue up jobs so that you do not need to wait for unrelated things and you can prioritize GPU page table update which should translate in fast GPU page table update without DMA fence. > > Full disclosure: We are aware that we've designed ourselves into an > > impressive corner here, and there's lots of talks going on about > > untangling the dma synchronization from the memory management > > completely. But > > I think the documenting is really important: only GPU should be using > this stuff and driving notifiers this way. Complete NO for any > totally-not-a-GPU things in drivers/accel for sure. Yes for user that expect HMM they need to be asynchronous. But it is hard to revert user ptr has it was done a long time ago. Cheers, J?r?me From jglisse at redhat.com Fri Jun 19 18:13:26 2020 From: jglisse at redhat.com (Jerome Glisse) Date: Fri, 19 Jun 2020 14:13:26 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> Message-ID: <20200619181326.GB10009@redhat.com> On Thu, Jun 11, 2020 at 07:35:35PM -0400, Felix Kuehling wrote: > Am 2020-06-11 um 10:15 a.m. schrieb Jason Gunthorpe: > > On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: > >>> I still have my doubts about allowing fence waiting from within shrinkers. > >>> IMO ideally they should use a trywait approach, in order to allow memory > >>> allocation during command submission for drivers that > >>> publish fences before command submission. (Since early reservation object > >>> release requires that). > >> Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up > >> with a mempool to make sure it can handle it's allocations. > >> > >>> But since drivers are already waiting from within shrinkers and I take your > >>> word for HMM requiring this, > >> Yeah the big trouble is HMM and mmu notifiers. That's the really awkward > >> one, the shrinker one is a lot less established. > > I really question if HW that needs something like DMA fence should > > even be using mmu notifiers - the best use is HW that can fence the > > DMA directly without having to get involved with some command stream > > processing. > > > > Or at the very least it should not be a generic DMA fence but a > > narrowed completion tied only into the same GPU driver's command > > completion processing which should be able to progress without > > blocking. > > > > The intent of notifiers was never to endlessly block while vast > > amounts of SW does work. > > > > Going around and switching everything in a GPU to GFP_ATOMIC seems > > like bad idea. > > > >> I've pinged a bunch of armsoc gpu driver people and ask them how much this > >> hurts, so that we have a clear answer. On x86 I don't think we have much > >> of a choice on this, with userptr in amd and i915 and hmm work in nouveau > >> (but nouveau I think doesn't use dma_fence in there). > > Soon nouveau will get company. We're working on a recoverable page fault > implementation for HMM in amdgpu where we'll need to update page tables > using the GPUs SDMA engine and wait for corresponding fences in MMU > notifiers. Note that HMM mandate, and i stressed that several time in the past, that all GPU page table update are asynchronous and do not have to wait on _anything_. I understand that you use DMA engine for GPU page table update but if you want to do so with HMM then you need a GPU page table update only DMA context where all GPU page table update goes through and where user space can not queue up job. It can be for HMM only but if you want to mix HMM with non HMM then everything need to be on that queue and other command queue will have to depends on it. Cheers, J?r?me From matthew.william.auld at gmail.com Fri Jun 19 18:34:21 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 19 Jun 2020 19:34:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Initialise rps timestamp In-Reply-To: <20200619151938.21740-1-chris@chris-wilson.co.uk> References: <20200619151938.21740-1-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHM=7bTJr=f-sMuRN+2LhBFWDO4qrtXOmw3jg1xFrry5XA@mail.gmail.com> On Fri, 19 Jun 2020 at 16:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Smatch warns that we may iterate over an empty array of gt->engines[]. > One hopes that this is impossible, but nevertheless we can simply > appease smatch by initialising the timestamp to zero before we starting > probing the engines. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From manasi.d.navare at intel.com Fri Jun 19 18:42:39 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 19 Jun 2020 11:42:39 -0700 Subject: [Intel-gfx] [v8 3/3] drm/debug: Expose connector VRR monitor range via debugfs In-Reply-To: <20200619212356.19285-4-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> <20200619212356.19285-4-bhanuprakash.modem@intel.com> Message-ID: <20200619184239.GA4000@intel.com> Hi Bhanu, Thanks for the patch, functionality wise looks good. Have you tested this with kms_vrr IGT, do we see the vrr_range properly exposed? Also please find some comments below On Sat, Jun 20, 2020 at 02:53:56AM +0530, Bhanuprakash Modem wrote: > [Why] > It's useful to know the min and max vrr range for IGT testing. > > [How] > Expose the min and max vfreq for the connector via a debugfs file > on the connector, "vrr_range". > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > v2: > * Fix the typo in max_vfreq (Manasi) > * Change the name of node to i915_vrr_info so we can add > other vrr info for more debug info (Manasi) > * Change the VRR capable to display Yes or No (Manasi) > * Fix indentation checkpatch errors (Manasi) > v3: > * Remove the unnecessary debug print (Manasi) > v4: > * Rebase > v5: > * Rename to vrr_range to match AMD debugfs > v6: > * Rebase (manasi) > v7: > * Fix cmpilation due to rebase > v8: > * Move debugfs node creation logic to DRM (Emil) > * Remove AMD specific logic (Emil) > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > Cc: Jani Nikula <jani.nikula at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Harry Wentland <harry.wentland at amd.com> > --- > .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ----------------- > drivers/gpu/drm/drm_debugfs.c | 22 +++++++++++++++++++ > 2 files changed, 22 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > index 076af267b488..71387d2af2ed 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > @@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void *data) > return res; > } > > -/* > - * Returns the min and max vrr vfreq through the connector's debugfs file. > - * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > - */ > -static int vrr_range_show(struct seq_file *m, void *data) > -{ > - struct drm_connector *connector = m->private; > - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); > - > - if (connector->status != connector_status_connected) > - return -ENODEV; > - > - seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); > - seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); > - > - return 0; > -} > - > #ifdef CONFIG_DRM_AMD_DC_HDCP > /* > * Returns the HDCP capability of the Display (1.4 for now). > @@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, > DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); > DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); > DEFINE_SHOW_ATTRIBUTE(output_bpc); > -DEFINE_SHOW_ATTRIBUTE(vrr_range); > #ifdef CONFIG_DRM_AMD_DC_HDCP > DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); > #endif > @@ -1059,7 +1040,6 @@ static const struct { > {"phy_settings", &dp_phy_settings_debugfs_fop}, > {"test_pattern", &dp_phy_test_pattern_fops}, > {"output_bpc", &output_bpc_fops}, > - {"vrr_range", &vrr_range_fops}, > #ifdef CONFIG_DRM_AMD_DC_HDCP > {"hdcp_sink_capability", &hdcp_sink_capability_fops}, > #endif I think the AMD sepecific debugfs removal should be in a separate patch follwing the drm_debugfs addition patch because from merging pov that patch will get merged through AMD tree and drm patch will get merged through drm_misc Also cc the amd dev mailing list for that patch. @Harry does that sound okay from merging pov? Manasi > diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c > index bfe4602f206b..3d7182001004 100644 > --- a/drivers/gpu/drm/drm_debugfs.c > +++ b/drivers/gpu/drm/drm_debugfs.c > @@ -376,6 +376,24 @@ static ssize_t edid_write(struct file *file, const char __user *ubuf, > return (ret) ? ret : len; > } > > +/* > + * Returns the min and max vrr vfreq through the connector's debugfs file. > + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > + */ > +static int vrr_range_show(struct seq_file *m, void *data) > +{ > + struct drm_connector *connector = m->private; > + > + if (connector->status != connector_status_connected) > + return -ENODEV; > + > + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); > + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); > + > + return 0; > +} > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > + > static const struct file_operations drm_edid_fops = { > .owner = THIS_MODULE, > .open = edid_open, > @@ -413,6 +431,10 @@ void drm_debugfs_connector_add(struct drm_connector *connector) > /* edid */ > debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root, connector, > &drm_edid_fops); > + > + /* vrr range */ > + debugfs_create_file("vrr_range", S_IRUGO, root, connector, > + &vrr_range_fops); > } > > void drm_debugfs_connector_remove(struct drm_connector *connector) > -- > 2.20.1 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From chris at chris-wilson.co.uk Fri Jun 19 19:10:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 20:10:53 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Show the culmative runtime as part of the engine info Message-ID: <20200619191053.9654-1-chris@chris-wilson.co.uk> Since we always enable the busy-stats, the culmulative runtime should be accurate, and might be useful for diagnosing issues with the engine. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index c62b3cbdbbf9..7bf2f76212f0 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1510,6 +1510,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, struct i915_request *rq; intel_wakeref_t wakeref; unsigned long flags; + ktime_t dummy; if (header) { va_list ap; @@ -1527,6 +1528,10 @@ void intel_engine_dump(struct intel_engine_cs *engine, yesno(!llist_empty(&engine->barrier_tasks))); drm_printf(m, "\tLatency: %luus\n", ewma__engine_latency_read(&engine->latency)); + if (intel_engine_supports_stats(engine)) + drm_printf(m, "\tRuntime: %llums\n", + ktime_to_ms(intel_engine_get_busy_time(engine, + &dummy))); drm_printf(m, "\tForcewake: %x domains, %d active\n", engine->fw_domain, atomic_read(&engine->fw_active)); -- 2.20.1 From alexdeucher at gmail.com Fri Jun 19 19:11:12 2020 From: alexdeucher at gmail.com (Alex Deucher) Date: Fri, 19 Jun 2020 15:11:12 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619180935.GA10009@redhat.com> References: <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> <20200617152835.GF6578@ziepe.ca> <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> Message-ID: <CADnq5_Pw_85Kzh1of=MbDi4g9POeF3jO4AJ7p2FjY5XZW0=vsQ@mail.gmail.com> On Fri, Jun 19, 2020 at 2:09 PM Jerome Glisse <jglisse at redhat.com> wrote: > > On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > > On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > > > > > The madness is only that device B's mmu notifier might need to wait > > > for fence_B so that the dma operation finishes. Which in turn has to > > > wait for device A to finish first. > > > > So, it sound, fundamentally you've got this graph of operations across > > an unknown set of drivers and the kernel cannot insert itself in > > dma_fence hand offs to re-validate any of the buffers involved? > > Buffers which by definition cannot be touched by the hardware yet. > > > > That really is a pretty horrible place to end up.. > > > > Pinning really is right answer for this kind of work flow. I think > > converting pinning to notifers should not be done unless notifier > > invalidation is relatively bounded. > > > > I know people like notifiers because they give a bit nicer performance > > in some happy cases, but this cripples all the bad cases.. > > > > If pinning doesn't work for some reason maybe we should address that? > > Note that the dma fence is only true for user ptr buffer which predate > any HMM work and thus were using mmu notifier already. You need the > mmu notifier there because of fork and other corner cases. > > For nouveau the notifier do not need to wait for anything it can update > the GPU page table right away. Modulo needing to write to GPU memory > using dma engine if the GPU page table is in GPU memory that is not > accessible from the CPU but that's never the case for nouveau so far > (but i expect it will be at one point). > > > So i see this as 2 different cases, the user ptr case, which does pin > pages by the way, where things are synchronous. Versus the HMM cases > where everything is asynchronous. > > > I probably need to warn AMD folks again that using HMM means that you > must be able to update the GPU page table asynchronously without > fence wait. The issue for AMD is that they already update their GPU > page table using DMA engine. I believe this is still doable if they > use a kernel only DMA engine context, where only kernel can queue up > jobs so that you do not need to wait for unrelated things and you can > prioritize GPU page table update which should translate in fast GPU > page table update without DMA fence. All devices which support recoverable page faults also have a dedicated paging engine for the kernel driver which the driver already makes use of. We can also update the GPU page tables with the CPU. Alex > > > > > Full disclosure: We are aware that we've designed ourselves into an > > > impressive corner here, and there's lots of talks going on about > > > untangling the dma synchronization from the memory management > > > completely. But > > > > I think the documenting is really important: only GPU should be using > > this stuff and driving notifiers this way. Complete NO for any > > totally-not-a-GPU things in drivers/accel for sure. > > Yes for user that expect HMM they need to be asynchronous. But it is > hard to revert user ptr has it was done a long time ago. > > Cheers, > J?r?me > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx From matthew.william.auld at gmail.com Fri Jun 19 19:29:15 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 19 Jun 2020 20:29:15 +0100 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/gem: Avoid kmalloc under i915->mm_lock In-Reply-To: <20200619143106.10356-1-chris@chris-wilson.co.uk> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHOW69ivmnoPG2B8TygS-T3ZiboCO5T1qqnzY+3ioOpJ8w@mail.gmail.com> On Fri, 19 Jun 2020 at 15:31, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Rearrange the allocation of the mm_struct registration to avoid > allocating underneath the i915->mm_lock, so that we avoid tainting the > lock (and in turn many other locks that may be held as i915->mm_lock is > taken, and those locks we may want on the free [shrinker] paths). In > doing so, we convert the lookup to be RCU protected by courtesy of > converting the free-worker to be an rcu_work. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 123 +++++++++----------- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > 2 files changed, 59 insertions(+), 66 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c > index 9c53eb883400..84766414a1f0 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c > @@ -21,7 +21,7 @@ struct i915_mm_struct { > struct i915_mmu_notifier *mn; > struct hlist_node node; > struct kref kref; > - struct work_struct work; > + struct rcu_work work; > }; > > #if defined(CONFIG_MMU_NOTIFIER) > @@ -189,40 +189,31 @@ i915_gem_userptr_release__mmu_notifier(struct drm_i915_gem_object *obj) > static struct i915_mmu_notifier * > i915_mmu_notifier_find(struct i915_mm_struct *mm) > { > - struct i915_mmu_notifier *mn; > - int err = 0; > + struct i915_mmu_notifier *mn, *old; > + int err; > > - mn = mm->mn; > - if (mn) > + mn = READ_ONCE(mm->mn); > + if (likely(mn)) > return mn; > > mn = i915_mmu_notifier_create(mm); > if (IS_ERR(mn)) > - err = PTR_ERR(mn); > - > - mmap_write_lock(mm->mm); > - mutex_lock(&mm->i915->mm_lock); > - if (mm->mn == NULL && !err) { > - /* Protected by mmap_lock (write-lock) */ > - err = __mmu_notifier_register(&mn->mn, mm->mm); > - if (!err) { > - /* Protected by mm_lock */ > - mm->mn = fetch_and_zero(&mn); > - } > - } else if (mm->mn) { > - /* > - * Someone else raced and successfully installed the mmu > - * notifier, we can cancel our own errors. > - */ > - err = 0; > + return mn; > + > + err = mmu_notifier_register(&mn->mn, mm->mm); > + if (err) { > + kfree(mn); > + return ERR_PTR(err); > } > - mutex_unlock(&mm->i915->mm_lock); > - mmap_write_unlock(mm->mm); > > - if (mn && !IS_ERR(mn)) > + old = cmpxchg(&mm->mn, NULL, mn); > + if (old) { > + mmu_notifier_unregister(&mn->mn, mm->mm); > kfree(mn); > + mn = old; > + } > > - return err ? ERR_PTR(err) : mm->mn; > + return mn; > } > > static int > @@ -301,23 +292,26 @@ i915_mmu_notifier_free(struct i915_mmu_notifier *mn, > #endif > > static struct i915_mm_struct * > -__i915_mm_struct_find(struct drm_i915_private *dev_priv, struct mm_struct *real) > +__i915_mm_struct_find(struct drm_i915_private *i915, struct mm_struct *real) > { > - struct i915_mm_struct *mm; > + struct i915_mm_struct *it, *mm = NULL; > > - /* Protected by dev_priv->mm_lock */ > - hash_for_each_possible(dev_priv->mm_structs, mm, node, (unsigned long)real) > - if (mm->mm == real) > - return mm; > + rcu_read_lock(); > + hash_for_each_possible(i915->mm_structs, it, node, (unsigned long)real) > + if (it->mm == real && kref_get_unless_zero(&it->kref)) { > + mm = it; > + break; > + } > + rcu_read_unlock(); > > - return NULL; > + return mm; > } > > static int > i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) > { > - struct drm_i915_private *dev_priv = to_i915(obj->base.dev); > - struct i915_mm_struct *mm; > + struct drm_i915_private *i915 = to_i915(obj->base.dev); > + struct i915_mm_struct *mm, *new; > int ret = 0; > > /* During release of the GEM object we hold the struct_mutex. This > @@ -330,39 +324,40 @@ i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) > * struct_mutex, i.e. we need to schedule a worker to do the clean > * up. > */ > - mutex_lock(&dev_priv->mm_lock); > - mm = __i915_mm_struct_find(dev_priv, current->mm); > - if (mm == NULL) { > - mm = kmalloc(sizeof(*mm), GFP_KERNEL); > - if (mm == NULL) { > - ret = -ENOMEM; > - goto out; > - } > + mm = __i915_mm_struct_find(i915, current->mm); Is this really safe without the mm_lock, assuming concurrent hash_add/has_del with hash_for_each? Reviewed-by: Matthew Auld <matthew.auld at intel.com> From felix.kuehling at amd.com Fri Jun 19 19:30:32 2020 From: felix.kuehling at amd.com (Felix Kuehling) Date: Fri, 19 Jun 2020 15:30:32 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <CADnq5_Pw_85Kzh1of=MbDi4g9POeF3jO4AJ7p2FjY5XZW0=vsQ@mail.gmail.com> References: <CAKMK7uE7DKUo9Z+yCpY+mW5gmKet8ugbF3yZNyHGqsJ=e-g_hA@mail.gmail.com> <20200617152835.GF6578@ziepe.ca> <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <CADnq5_Pw_85Kzh1of=MbDi4g9POeF3jO4AJ7p2FjY5XZW0=vsQ@mail.gmail.com> Message-ID: <86f7f5e5-81a0-5429-5a6e-0d3b0860cfae@amd.com> Am 2020-06-19 um 3:11 p.m. schrieb Alex Deucher: > On Fri, Jun 19, 2020 at 2:09 PM Jerome Glisse <jglisse at redhat.com> wrote: >> On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: >>> On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: >>> >>>> The madness is only that device B's mmu notifier might need to wait >>>> for fence_B so that the dma operation finishes. Which in turn has to >>>> wait for device A to finish first. >>> So, it sound, fundamentally you've got this graph of operations across >>> an unknown set of drivers and the kernel cannot insert itself in >>> dma_fence hand offs to re-validate any of the buffers involved? >>> Buffers which by definition cannot be touched by the hardware yet. >>> >>> That really is a pretty horrible place to end up.. >>> >>> Pinning really is right answer for this kind of work flow. I think >>> converting pinning to notifers should not be done unless notifier >>> invalidation is relatively bounded. >>> >>> I know people like notifiers because they give a bit nicer performance >>> in some happy cases, but this cripples all the bad cases.. >>> >>> If pinning doesn't work for some reason maybe we should address that? >> Note that the dma fence is only true for user ptr buffer which predate >> any HMM work and thus were using mmu notifier already. You need the >> mmu notifier there because of fork and other corner cases. >> >> For nouveau the notifier do not need to wait for anything it can update >> the GPU page table right away. Modulo needing to write to GPU memory >> using dma engine if the GPU page table is in GPU memory that is not >> accessible from the CPU but that's never the case for nouveau so far >> (but i expect it will be at one point). >> >> >> So i see this as 2 different cases, the user ptr case, which does pin >> pages by the way, where things are synchronous. Versus the HMM cases >> where everything is asynchronous. >> >> >> I probably need to warn AMD folks again that using HMM means that you >> must be able to update the GPU page table asynchronously without >> fence wait. The issue for AMD is that they already update their GPU >> page table using DMA engine. I believe this is still doable if they >> use a kernel only DMA engine context, where only kernel can queue up >> jobs so that you do not need to wait for unrelated things and you can >> prioritize GPU page table update which should translate in fast GPU >> page table update without DMA fence. > All devices which support recoverable page faults also have a > dedicated paging engine for the kernel driver which the driver already > makes use of. We can also update the GPU page tables with the CPU. We have a potential problem with CPU updating page tables while the GPU is retrying on page table entries because 64 bit CPU transactions don't arrive in device memory atomically. We are using SDMA for page table updates. This currently goes through a the DRM GPU scheduler to a special SDMA queue that's used by kernel-mode only. But since it's based on the DRM GPU scheduler, we do use dma-fence to wait for completion. Regards, ? Felix > > Alex > >> >>>> Full disclosure: We are aware that we've designed ourselves into an >>>> impressive corner here, and there's lots of talks going on about >>>> untangling the dma synchronization from the memory management >>>> completely. But >>> I think the documenting is really important: only GPU should be using >>> this stuff and driving notifiers this way. Complete NO for any >>> totally-not-a-GPU things in drivers/accel for sure. >> Yes for user that expect HMM they need to be asynchronous. But it is >> hard to revert user ptr has it was done a long time ago. >> >> Cheers, >> J?r?me >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx From chris at chris-wilson.co.uk Fri Jun 19 19:36:05 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 20:36:05 +0100 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/gem: Avoid kmalloc under i915->mm_lock In-Reply-To: <CAM0jSHOW69ivmnoPG2B8TygS-T3ZiboCO5T1qqnzY+3ioOpJ8w@mail.gmail.com> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> <CAM0jSHOW69ivmnoPG2B8TygS-T3ZiboCO5T1qqnzY+3ioOpJ8w@mail.gmail.com> Message-ID: <159259536515.12119.8045043271199697348@build.alporthouse.com> Quoting Matthew Auld (2020-06-19 20:29:15) > On Fri, 19 Jun 2020 at 15:31, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > Rearrange the allocation of the mm_struct registration to avoid > > allocating underneath the i915->mm_lock, so that we avoid tainting the > > lock (and in turn many other locks that may be held as i915->mm_lock is > > taken, and those locks we may want on the free [shrinker] paths). In > > doing so, we convert the lookup to be RCU protected by courtesy of > > converting the free-worker to be an rcu_work. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 123 +++++++++----------- > > drivers/gpu/drm/i915/i915_drv.h | 2 +- > > 2 files changed, 59 insertions(+), 66 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c > > index 9c53eb883400..84766414a1f0 100644 > > --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c > > @@ -21,7 +21,7 @@ struct i915_mm_struct { > > struct i915_mmu_notifier *mn; > > struct hlist_node node; > > struct kref kref; > > - struct work_struct work; > > + struct rcu_work work; > > }; > > > > #if defined(CONFIG_MMU_NOTIFIER) > > @@ -189,40 +189,31 @@ i915_gem_userptr_release__mmu_notifier(struct drm_i915_gem_object *obj) > > static struct i915_mmu_notifier * > > i915_mmu_notifier_find(struct i915_mm_struct *mm) > > { > > - struct i915_mmu_notifier *mn; > > - int err = 0; > > + struct i915_mmu_notifier *mn, *old; > > + int err; > > > > - mn = mm->mn; > > - if (mn) > > + mn = READ_ONCE(mm->mn); > > + if (likely(mn)) > > return mn; > > > > mn = i915_mmu_notifier_create(mm); > > if (IS_ERR(mn)) > > - err = PTR_ERR(mn); > > - > > - mmap_write_lock(mm->mm); > > - mutex_lock(&mm->i915->mm_lock); > > - if (mm->mn == NULL && !err) { > > - /* Protected by mmap_lock (write-lock) */ > > - err = __mmu_notifier_register(&mn->mn, mm->mm); > > - if (!err) { > > - /* Protected by mm_lock */ > > - mm->mn = fetch_and_zero(&mn); > > - } > > - } else if (mm->mn) { > > - /* > > - * Someone else raced and successfully installed the mmu > > - * notifier, we can cancel our own errors. > > - */ > > - err = 0; > > + return mn; > > + > > + err = mmu_notifier_register(&mn->mn, mm->mm); > > + if (err) { > > + kfree(mn); > > + return ERR_PTR(err); > > } > > - mutex_unlock(&mm->i915->mm_lock); > > - mmap_write_unlock(mm->mm); > > > > - if (mn && !IS_ERR(mn)) > > + old = cmpxchg(&mm->mn, NULL, mn); > > + if (old) { > > + mmu_notifier_unregister(&mn->mn, mm->mm); > > kfree(mn); > > + mn = old; > > + } > > > > - return err ? ERR_PTR(err) : mm->mn; > > + return mn; > > } > > > > static int > > @@ -301,23 +292,26 @@ i915_mmu_notifier_free(struct i915_mmu_notifier *mn, > > #endif > > > > static struct i915_mm_struct * > > -__i915_mm_struct_find(struct drm_i915_private *dev_priv, struct mm_struct *real) > > +__i915_mm_struct_find(struct drm_i915_private *i915, struct mm_struct *real) > > { > > - struct i915_mm_struct *mm; > > + struct i915_mm_struct *it, *mm = NULL; > > > > - /* Protected by dev_priv->mm_lock */ > > - hash_for_each_possible(dev_priv->mm_structs, mm, node, (unsigned long)real) > > - if (mm->mm == real) > > - return mm; > > + rcu_read_lock(); > > + hash_for_each_possible(i915->mm_structs, it, node, (unsigned long)real) > > + if (it->mm == real && kref_get_unless_zero(&it->kref)) { > > + mm = it; > > + break; > > + } > > + rcu_read_unlock(); > > > > - return NULL; > > + return mm; > > } > > > > static int > > i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) > > { > > - struct drm_i915_private *dev_priv = to_i915(obj->base.dev); > > - struct i915_mm_struct *mm; > > + struct drm_i915_private *i915 = to_i915(obj->base.dev); > > + struct i915_mm_struct *mm, *new; > > int ret = 0; > > > > /* During release of the GEM object we hold the struct_mutex. This > > @@ -330,39 +324,40 @@ i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) > > * struct_mutex, i.e. we need to schedule a worker to do the clean > > * up. > > */ > > - mutex_lock(&dev_priv->mm_lock); > > - mm = __i915_mm_struct_find(dev_priv, current->mm); > > - if (mm == NULL) { > > - mm = kmalloc(sizeof(*mm), GFP_KERNEL); > > - if (mm == NULL) { > > - ret = -ENOMEM; > > - goto out; > > - } > > + mm = __i915_mm_struct_find(i915, current->mm); > > Is this really safe without the mm_lock, assuming concurrent > hash_add/has_del with hash_for_each? Hmm, not quite. There's hash_add_rcu, hash_del_rcu, hash_for_each_possible_rcu, to ensure the write ordering is safe for the concurrent readers. Good catch. -Chris From matthew.william.auld at gmail.com Fri Jun 19 19:39:04 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 19 Jun 2020 20:39:04 +0100 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/gt: Replace manual kmap_atomic() with pin_map for renderstate In-Reply-To: <20200619143106.10356-3-chris@chris-wilson.co.uk> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> <20200619143106.10356-3-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHNZSp7zjpcdfEcL8=_hAm39d+oxgyBv8KmUk-+fte9K+g@mail.gmail.com> On Fri, 19 Jun 2020 at 15:31, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > We only emit the renderstate once now during module load, it is no > longer a concern that we are delaying context creation and so do not > need to so eagerly optimise. Since the last time we have looked at the > renderstate, we have a pin_map / flush_map facility that supports simple > single mappings, replacing the open-coded kmap_atomic() and > prepare_write. As it should be a single page, of which we only write a > small portion, we stick to a simple WB [kmap] and use clflush on !llc > platforms, rather than creating a temporary WC vmapping for the single > page. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From chris at chris-wilson.co.uk Fri Jun 19 19:40:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 19 Jun 2020 20:40:38 +0100 Subject: [Intel-gfx] [CI] drm/i915/gem: Avoid kmalloc under i915->mm_lock Message-ID: <20200619194038.5088-1-chris@chris-wilson.co.uk> Rearrange the allocation of the mm_struct registration to avoid allocating underneath the i915->mm_lock, so that we avoid tainting the lock (and in turn many other locks that may be held as i915->mm_lock is taken, and those locks we may want on the free [shrinker] paths). In doing so, we convert the lookup to be RCU protected by courtesy of converting the free-worker to be an rcu_work. v2: Remember to use hash_rcu variants to protect the list iteration from concurrent add/del. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 131 ++++++++++---------- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 65 insertions(+), 68 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index 9c53eb883400..e946032b13e4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -21,7 +21,7 @@ struct i915_mm_struct { struct i915_mmu_notifier *mn; struct hlist_node node; struct kref kref; - struct work_struct work; + struct rcu_work work; }; #if defined(CONFIG_MMU_NOTIFIER) @@ -189,40 +189,31 @@ i915_gem_userptr_release__mmu_notifier(struct drm_i915_gem_object *obj) static struct i915_mmu_notifier * i915_mmu_notifier_find(struct i915_mm_struct *mm) { - struct i915_mmu_notifier *mn; - int err = 0; + struct i915_mmu_notifier *mn, *old; + int err; - mn = mm->mn; - if (mn) + mn = READ_ONCE(mm->mn); + if (likely(mn)) return mn; mn = i915_mmu_notifier_create(mm); if (IS_ERR(mn)) - err = PTR_ERR(mn); - - mmap_write_lock(mm->mm); - mutex_lock(&mm->i915->mm_lock); - if (mm->mn == NULL && !err) { - /* Protected by mmap_lock (write-lock) */ - err = __mmu_notifier_register(&mn->mn, mm->mm); - if (!err) { - /* Protected by mm_lock */ - mm->mn = fetch_and_zero(&mn); - } - } else if (mm->mn) { - /* - * Someone else raced and successfully installed the mmu - * notifier, we can cancel our own errors. - */ - err = 0; + return mn; + + err = mmu_notifier_register(&mn->mn, mm->mm); + if (err) { + kfree(mn); + return ERR_PTR(err); } - mutex_unlock(&mm->i915->mm_lock); - mmap_write_unlock(mm->mm); - if (mn && !IS_ERR(mn)) + old = cmpxchg(&mm->mn, NULL, mn); + if (old) { + mmu_notifier_unregister(&mn->mn, mm->mm); kfree(mn); + mn = old; + } - return err ? ERR_PTR(err) : mm->mn; + return mn; } static int @@ -301,23 +292,28 @@ i915_mmu_notifier_free(struct i915_mmu_notifier *mn, #endif static struct i915_mm_struct * -__i915_mm_struct_find(struct drm_i915_private *dev_priv, struct mm_struct *real) +__i915_mm_struct_find(struct drm_i915_private *i915, struct mm_struct *real) { - struct i915_mm_struct *mm; - - /* Protected by dev_priv->mm_lock */ - hash_for_each_possible(dev_priv->mm_structs, mm, node, (unsigned long)real) - if (mm->mm == real) - return mm; + struct i915_mm_struct *it, *mm = NULL; + + rcu_read_lock(); + hash_for_each_possible_rcu(i915->mm_structs, + it, node, + (unsigned long)real) + if (it->mm == real && kref_get_unless_zero(&it->kref)) { + mm = it; + break; + } + rcu_read_unlock(); - return NULL; + return mm; } static int i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) { - struct drm_i915_private *dev_priv = to_i915(obj->base.dev); - struct i915_mm_struct *mm; + struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_mm_struct *mm, *new; int ret = 0; /* During release of the GEM object we hold the struct_mutex. This @@ -330,39 +326,42 @@ i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj) * struct_mutex, i.e. we need to schedule a worker to do the clean * up. */ - mutex_lock(&dev_priv->mm_lock); - mm = __i915_mm_struct_find(dev_priv, current->mm); - if (mm == NULL) { - mm = kmalloc(sizeof(*mm), GFP_KERNEL); - if (mm == NULL) { - ret = -ENOMEM; - goto out; - } + mm = __i915_mm_struct_find(i915, current->mm); + if (mm) + goto out; - kref_init(&mm->kref); - mm->i915 = to_i915(obj->base.dev); + new = kmalloc(sizeof(*mm), GFP_KERNEL); + if (!new) + return -ENOMEM; - mm->mm = current->mm; + kref_init(&new->kref); + new->i915 = to_i915(obj->base.dev); + new->mm = current->mm; + new->mn = NULL; + + spin_lock(&i915->mm_lock); + mm = __i915_mm_struct_find(i915, current->mm); + if (!mm) { + hash_add_rcu(i915->mm_structs, + &new->node, + (unsigned long)new->mm); mmgrab(current->mm); + mm = new; + } + spin_unlock(&i915->mm_lock); + if (mm != new) + kfree(new); - mm->mn = NULL; - - /* Protected by dev_priv->mm_lock */ - hash_add(dev_priv->mm_structs, - &mm->node, (unsigned long)mm->mm); - } else - kref_get(&mm->kref); - - obj->userptr.mm = mm; out: - mutex_unlock(&dev_priv->mm_lock); + obj->userptr.mm = mm; return ret; } static void __i915_mm_struct_free__worker(struct work_struct *work) { - struct i915_mm_struct *mm = container_of(work, typeof(*mm), work); + struct i915_mm_struct *mm = container_of(work, typeof(*mm), work.work); + i915_mmu_notifier_free(mm->mn, mm->mm); mmdrop(mm->mm); kfree(mm); @@ -373,12 +372,12 @@ __i915_mm_struct_free(struct kref *kref) { struct i915_mm_struct *mm = container_of(kref, typeof(*mm), kref); - /* Protected by dev_priv->mm_lock */ - hash_del(&mm->node); - mutex_unlock(&mm->i915->mm_lock); + spin_lock(&mm->i915->mm_lock); + hash_del_rcu(&mm->node); + spin_unlock(&mm->i915->mm_lock); - INIT_WORK(&mm->work, __i915_mm_struct_free__worker); - queue_work(mm->i915->mm.userptr_wq, &mm->work); + INIT_RCU_WORK(&mm->work, __i915_mm_struct_free__worker); + queue_rcu_work(system_wq, &mm->work); } static void @@ -387,9 +386,7 @@ i915_gem_userptr_release__mm_struct(struct drm_i915_gem_object *obj) if (obj->userptr.mm == NULL) return; - kref_put_mutex(&obj->userptr.mm->kref, - __i915_mm_struct_free, - &to_i915(obj->base.dev)->mm_lock); + kref_put(&obj->userptr.mm->kref, __i915_mm_struct_free); obj->userptr.mm = NULL; } @@ -851,7 +848,7 @@ i915_gem_userptr_ioctl(struct drm_device *dev, int i915_gem_init_userptr(struct drm_i915_private *dev_priv) { - mutex_init(&dev_priv->mm_lock); + spin_lock_init(&dev_priv->mm_lock); hash_init(dev_priv->mm_structs); dev_priv->mm.userptr_wq = diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..7464656253c9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -988,7 +988,7 @@ struct drm_i915_private { struct i915_gem_mm mm; DECLARE_HASHTABLE(mm_structs, 7); - struct mutex mm_lock; + spinlock_t mm_lock; /* Kernel Modesetting */ -- 2.20.1 From jglisse at redhat.com Fri Jun 19 19:40:56 2020 From: jglisse at redhat.com (Jerome Glisse) Date: Fri, 19 Jun 2020 15:40:56 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <86f7f5e5-81a0-5429-5a6e-0d3b0860cfae@amd.com> References: <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <CADnq5_Pw_85Kzh1of=MbDi4g9POeF3jO4AJ7p2FjY5XZW0=vsQ@mail.gmail.com> <86f7f5e5-81a0-5429-5a6e-0d3b0860cfae@amd.com> Message-ID: <20200619194056.GA13117@redhat.com> On Fri, Jun 19, 2020 at 03:30:32PM -0400, Felix Kuehling wrote: > > Am 2020-06-19 um 3:11 p.m. schrieb Alex Deucher: > > On Fri, Jun 19, 2020 at 2:09 PM Jerome Glisse <jglisse at redhat.com> wrote: > >> On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > >>> On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > >>> > >>>> The madness is only that device B's mmu notifier might need to wait > >>>> for fence_B so that the dma operation finishes. Which in turn has to > >>>> wait for device A to finish first. > >>> So, it sound, fundamentally you've got this graph of operations across > >>> an unknown set of drivers and the kernel cannot insert itself in > >>> dma_fence hand offs to re-validate any of the buffers involved? > >>> Buffers which by definition cannot be touched by the hardware yet. > >>> > >>> That really is a pretty horrible place to end up.. > >>> > >>> Pinning really is right answer for this kind of work flow. I think > >>> converting pinning to notifers should not be done unless notifier > >>> invalidation is relatively bounded. > >>> > >>> I know people like notifiers because they give a bit nicer performance > >>> in some happy cases, but this cripples all the bad cases.. > >>> > >>> If pinning doesn't work for some reason maybe we should address that? > >> Note that the dma fence is only true for user ptr buffer which predate > >> any HMM work and thus were using mmu notifier already. You need the > >> mmu notifier there because of fork and other corner cases. > >> > >> For nouveau the notifier do not need to wait for anything it can update > >> the GPU page table right away. Modulo needing to write to GPU memory > >> using dma engine if the GPU page table is in GPU memory that is not > >> accessible from the CPU but that's never the case for nouveau so far > >> (but i expect it will be at one point). > >> > >> > >> So i see this as 2 different cases, the user ptr case, which does pin > >> pages by the way, where things are synchronous. Versus the HMM cases > >> where everything is asynchronous. > >> > >> > >> I probably need to warn AMD folks again that using HMM means that you > >> must be able to update the GPU page table asynchronously without > >> fence wait. The issue for AMD is that they already update their GPU > >> page table using DMA engine. I believe this is still doable if they > >> use a kernel only DMA engine context, where only kernel can queue up > >> jobs so that you do not need to wait for unrelated things and you can > >> prioritize GPU page table update which should translate in fast GPU > >> page table update without DMA fence. > > All devices which support recoverable page faults also have a > > dedicated paging engine for the kernel driver which the driver already > > makes use of. We can also update the GPU page tables with the CPU. > > We have a potential problem with CPU updating page tables while the GPU > is retrying on page table entries because 64 bit CPU transactions don't > arrive in device memory atomically. > > We are using SDMA for page table updates. This currently goes through a > the DRM GPU scheduler to a special SDMA queue that's used by kernel-mode > only. But since it's based on the DRM GPU scheduler, we do use dma-fence > to wait for completion. Yeah my worry is mostly that some cross dma fence leak into it but it should never happen realy, maybe there is a way to catch if it does and print a warning. So yes you can use dma fence, as long as they do not have cross-dep. Another expectation is that they complete quickly and usualy page table update do. Cheers, J?r?me From matthew.william.auld at gmail.com Fri Jun 19 19:44:29 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 19 Jun 2020 20:44:29 +0100 Subject: [Intel-gfx] [PATCH 2/3] drm/i915/gvt: Drop redundant prepare_write/pin_pages In-Reply-To: <20200619143106.10356-2-chris@chris-wilson.co.uk> References: <20200619143106.10356-1-chris@chris-wilson.co.uk> <20200619143106.10356-2-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHNuujgCy=JVSHZwyjYj08EiW_DYJko9__BxHD7Rw2Hd0Q@mail.gmail.com> On Fri, 19 Jun 2020 at 15:31, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Since gvt calls pin_map for the shadow batch buffer, this makes the > action of prepare_write [+pin_pages] redundant. We can write into the > obj->mm.mapping directory and the flush_map routine knows when it has to > flush the cpu cache afterwards. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From felix.kuehling at amd.com Fri Jun 19 19:48:49 2020 From: felix.kuehling at amd.com (Felix Kuehling) Date: Fri, 19 Jun 2020 15:48:49 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619181849.GR6578@ziepe.ca> References: <20200617152835.GF6578@ziepe.ca> <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> Message-ID: <56008d64-772d-5757-6136-f20591ef71d2@amd.com> Am 2020-06-19 um 2:18 p.m. schrieb Jason Gunthorpe: > On Fri, Jun 19, 2020 at 02:09:35PM -0400, Jerome Glisse wrote: >> On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: >>> On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: >>> >>>> The madness is only that device B's mmu notifier might need to wait >>>> for fence_B so that the dma operation finishes. Which in turn has to >>>> wait for device A to finish first. >>> So, it sound, fundamentally you've got this graph of operations across >>> an unknown set of drivers and the kernel cannot insert itself in >>> dma_fence hand offs to re-validate any of the buffers involved? >>> Buffers which by definition cannot be touched by the hardware yet. >>> >>> That really is a pretty horrible place to end up.. >>> >>> Pinning really is right answer for this kind of work flow. I think >>> converting pinning to notifers should not be done unless notifier >>> invalidation is relatively bounded. >>> >>> I know people like notifiers because they give a bit nicer performance >>> in some happy cases, but this cripples all the bad cases.. >>> >>> If pinning doesn't work for some reason maybe we should address that? >> Note that the dma fence is only true for user ptr buffer which predate >> any HMM work and thus were using mmu notifier already. You need the >> mmu notifier there because of fork and other corner cases. > I wonder if we should try to fix the fork case more directly - RDMA > has this same problem and added MADV_DONTFORK a long time ago as a > hacky way to deal with it. > > Some crazy page pin that resolved COW in a way that always kept the > physical memory with the mm that initiated the pin? > > (isn't this broken for O_DIRECT as well anyhow?) > > How does mmu_notifiers help the fork case anyhow? Block fork from > progressing? How much the mmu_notifier blocks fork progress depends, on quickly we can preempt GPU jobs accessing affected memory. If we don't have fine-grained preemption capability (graphics), the best we can do is wait for the GPU jobs to complete. We can also delay submission of new GPU jobs to the same memory until the MMU notifier is done. Future jobs would use the new page addresses. With fine-grained preemption (ROCm compute), we can preempt GPU work on the affected adders space to minimize the delay seen by fork. With recoverable device page faults, we can invalidate GPU page table entries, so device access to the affected pages stops immediately. In all cases, the end result is, that the device page table gets updated with the address of the copied pages before the GPU accesses the COW memory again.Without the MMU notifier, we'd end up with the GPU corrupting memory of the other process. Regards, ? Felix > >> I probably need to warn AMD folks again that using HMM means that you >> must be able to update the GPU page table asynchronously without >> fence wait. > It is kind of unrelated to HMM, it just shouldn't be using mmu > notifiers to replace page pinning.. > >> The issue for AMD is that they already update their GPU page table >> using DMA engine. I believe this is still doable if they use a >> kernel only DMA engine context, where only kernel can queue up jobs >> so that you do not need to wait for unrelated things and you can >> prioritize GPU page table update which should translate in fast GPU >> page table update without DMA fence. > Make sense > > I'm not sure I saw this in the AMD hmm stuff - it would be good if > someone would look at that. Every time I do it looks like the locking > is wrong. > > Jason > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx From matthew.william.auld at gmail.com Fri Jun 19 19:49:37 2020 From: matthew.william.auld at gmail.com (Matthew Auld) Date: Fri, 19 Jun 2020 20:49:37 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Show the culmative runtime as part of the engine info In-Reply-To: <20200619191053.9654-1-chris@chris-wilson.co.uk> References: <20200619191053.9654-1-chris@chris-wilson.co.uk> Message-ID: <CAM0jSHOWs56vFOFojEJLQbTBA3ohzToy-h3FiduimK4LuSDU2Q@mail.gmail.com> On Fri, 19 Jun 2020 at 20:11, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Since we always enable the busy-stats, the culmulative runtime should be > accurate, and might be useful for diagnosing issues with the engine. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> From manasi.d.navare at intel.com Fri Jun 19 20:01:28 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 19 Jun 2020 13:01:28 -0700 Subject: [Intel-gfx] [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD In-Reply-To: <20200619212356.19285-2-bhanuprakash.modem@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> <20200619212356.19285-2-bhanuprakash.modem@intel.com> Message-ID: <20200619200126.GA4176@intel.com> Thanks for the review, pushed to drm-misc Manasi On Sat, Jun 20, 2020 at 02:53:54AM +0530, Bhanuprakash Modem wrote: > From: Manasi Navare <manasi.d.navare at intel.com> > > DP sink device sets the Ignore MSA bit in its > DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to > ignore the MSA video timing parameters and its ability to support > seamless video timing change over a range of timing exposed by > DisplayID and EDID. > This is required for the sink to indicate that it is Adaptive sync > capable. > > v3: > * Fi the typo in commit message (Manasi) > v2: > * Rename to describe what the function does (Jani Nikula) > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Harry Wentland <harry.wentland at amd.com> > Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas at amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > Reviewed-by: Harry Wentland <harry.wentland at amd.com> > --- > include/drm/drm_dp_helper.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 1165ec105638..e47dc22ebf50 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > DP_ALTERNATE_SCRAMBLER_RESET_CAP; > } > > +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ > +static inline bool > +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +{ > + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & > + DP_MSA_TIMING_PAR_IGNORED; > +} > + > /* > * DisplayPort AUX channel > */ > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From felix.kuehling at amd.com Fri Jun 19 20:03:31 2020 From: felix.kuehling at amd.com (Felix Kuehling) Date: Fri, 19 Jun 2020 16:03:31 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619195538.GT6578@ziepe.ca> References: <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> <56008d64-772d-5757-6136-f20591ef71d2@amd.com> <20200619195538.GT6578@ziepe.ca> Message-ID: <789aa42e-0ddc-14f2-96be-07c00603efea@amd.com> Am 2020-06-19 um 3:55 p.m. schrieb Jason Gunthorpe: > On Fri, Jun 19, 2020 at 03:48:49PM -0400, Felix Kuehling wrote: >> Am 2020-06-19 um 2:18 p.m. schrieb Jason Gunthorpe: >>> On Fri, Jun 19, 2020 at 02:09:35PM -0400, Jerome Glisse wrote: >>>> On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: >>>>> On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: >>>>> >>>>>> The madness is only that device B's mmu notifier might need to wait >>>>>> for fence_B so that the dma operation finishes. Which in turn has to >>>>>> wait for device A to finish first. >>>>> So, it sound, fundamentally you've got this graph of operations across >>>>> an unknown set of drivers and the kernel cannot insert itself in >>>>> dma_fence hand offs to re-validate any of the buffers involved? >>>>> Buffers which by definition cannot be touched by the hardware yet. >>>>> >>>>> That really is a pretty horrible place to end up.. >>>>> >>>>> Pinning really is right answer for this kind of work flow. I think >>>>> converting pinning to notifers should not be done unless notifier >>>>> invalidation is relatively bounded. >>>>> >>>>> I know people like notifiers because they give a bit nicer performance >>>>> in some happy cases, but this cripples all the bad cases.. >>>>> >>>>> If pinning doesn't work for some reason maybe we should address that? >>>> Note that the dma fence is only true for user ptr buffer which predate >>>> any HMM work and thus were using mmu notifier already. You need the >>>> mmu notifier there because of fork and other corner cases. >>> I wonder if we should try to fix the fork case more directly - RDMA >>> has this same problem and added MADV_DONTFORK a long time ago as a >>> hacky way to deal with it. >>> >>> Some crazy page pin that resolved COW in a way that always kept the >>> physical memory with the mm that initiated the pin? >>> >>> (isn't this broken for O_DIRECT as well anyhow?) >>> >>> How does mmu_notifiers help the fork case anyhow? Block fork from >>> progressing? >> How much the mmu_notifier blocks fork progress depends, on quickly we >> can preempt GPU jobs accessing affected memory. If we don't have >> fine-grained preemption capability (graphics), the best we can do is >> wait for the GPU jobs to complete. We can also delay submission of new >> GPU jobs to the same memory until the MMU notifier is done. Future jobs >> would use the new page addresses. >> >> With fine-grained preemption (ROCm compute), we can preempt GPU work on >> the affected adders space to minimize the delay seen by fork. >> >> With recoverable device page faults, we can invalidate GPU page table >> entries, so device access to the affected pages stops immediately. >> >> In all cases, the end result is, that the device page table gets updated >> with the address of the copied pages before the GPU accesses the COW >> memory again.Without the MMU notifier, we'd end up with the GPU >> corrupting memory of the other process. > The model here in fork has been wrong for a long time, and I do wonder > how O_DIRECT manages to not be broken too.. I guess the time windows > there are too small to get unlucky. > > If you have a write pin on a page then it should not be COW'd into the > fork'd process but copied with the originating page remaining with the > original mm. > > I wonder if there is some easy way to achive that - if that is the > main reason to use notifiers then it would be a better solution. Other than the application changing its own virtual address mappings (mprotect, munmap, etc.), triggering MMU notifiers, we also get MMU notifiers from THP worker threads, and NUMA balancing. When we start doing migration to DEVICE_PRIVATE memory with HMM, we also get MMU notifiers during those driver-initiated migrations. Regards, ? Felix > > Jason From jglisse at redhat.com Fri Jun 19 20:10:11 2020 From: jglisse at redhat.com (Jerome Glisse) Date: Fri, 19 Jun 2020 16:10:11 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619181849.GR6578@ziepe.ca> References: <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> Message-ID: <20200619201011.GB13117@redhat.com> On Fri, Jun 19, 2020 at 03:18:49PM -0300, Jason Gunthorpe wrote: > On Fri, Jun 19, 2020 at 02:09:35PM -0400, Jerome Glisse wrote: > > On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > > > On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > > > > > > > The madness is only that device B's mmu notifier might need to wait > > > > for fence_B so that the dma operation finishes. Which in turn has to > > > > wait for device A to finish first. > > > > > > So, it sound, fundamentally you've got this graph of operations across > > > an unknown set of drivers and the kernel cannot insert itself in > > > dma_fence hand offs to re-validate any of the buffers involved? > > > Buffers which by definition cannot be touched by the hardware yet. > > > > > > That really is a pretty horrible place to end up.. > > > > > > Pinning really is right answer for this kind of work flow. I think > > > converting pinning to notifers should not be done unless notifier > > > invalidation is relatively bounded. > > > > > > I know people like notifiers because they give a bit nicer performance > > > in some happy cases, but this cripples all the bad cases.. > > > > > > If pinning doesn't work for some reason maybe we should address that? > > > > Note that the dma fence is only true for user ptr buffer which predate > > any HMM work and thus were using mmu notifier already. You need the > > mmu notifier there because of fork and other corner cases. > > I wonder if we should try to fix the fork case more directly - RDMA > has this same problem and added MADV_DONTFORK a long time ago as a > hacky way to deal with it. > > Some crazy page pin that resolved COW in a way that always kept the > physical memory with the mm that initiated the pin? Just no way to deal with it easily, i thought about forcing the anon_vma (page->mapping for anonymous page) to the anon_vma that belongs to the vma against which the GUP was done but it would break things if page is already in other branch of a fork tree. Also this forbid fast GUP. Quite frankly the fork was not the main motivating factor. GPU can pin potentialy GBytes of memory thus we wanted to be able to release it but since Michal changes to reclaim code this is no longer effective. User buffer should never end up in those weird corner case, iirc the first usage was for xorg exa texture upload, then generalize to texture upload in mesa and latter on to more upload cases (vertices, ...). At least this is what i remember today. So in those cases we do not expect fork, splice, mremap, mprotect, ... Maybe we can audit how user ptr buffer are use today and see if we can define a usage pattern that would allow to cut corner in kernel. For instance we could use mmu notifier just to block CPU pte update while we do GUP and thus never wait on dma fence. Then GPU driver just keep the GUP pin around until they are done with the page. They can also use the mmu notifier to keep a flag so that the driver know if it needs to redo a GUP ie: The notifier path: GPU_mmu_notifier_start_callback(range) gpu_lock_cpu_pagetable(range) for_each_bo_in(bo, range) { bo->need_gup = true; } gpu_unlock_cpu_pagetable(range) GPU_validate_buffer_pages(bo) if (!bo->need_gup) return; put_pages(bo->pages); range = bo_vaddr_range(bo) gpu_lock_cpu_pagetable(range) GUP(bo->pages, range) gpu_unlock_cpu_pagetable(range) Depending on how user_ptr are use today this could work. > (isn't this broken for O_DIRECT as well anyhow?) Yes it can in theory, if you have an application that does O_DIRECT and fork concurrently (ie O_DIRECT in one thread and fork in another). Note that O_DIRECT after fork is fine, it is an issue only if GUP_fast was able to lookup a page with write permission before fork had the chance to update it to read only for COW. But doing O_DIRECT (or anything that use GUP fast) in one thread and fork in another is inherently broken ie there is no way to fix it. See 17839856fd588f4ab6b789f482ed3ffd7c403e1f > > How does mmu_notifiers help the fork case anyhow? Block fork from > progressing? It enforce ordering between fork and GUP, if fork is first it blocks GUP and if forks is last then fork waits on GUP and then user buffer get invalidated. > > > I probably need to warn AMD folks again that using HMM means that you > > must be able to update the GPU page table asynchronously without > > fence wait. > > It is kind of unrelated to HMM, it just shouldn't be using mmu > notifiers to replace page pinning.. Well my POV is that if you abide by rules HMM defined then you do not need to pin pages. The rule is asynchronous device page table update. Pinning pages is problematic it blocks many core mm features and it is just bad all around. Also it is inherently broken in front of fork/mremap/splice/... Cheers, J?r?me From rodrigo.vivi at intel.com Fri Jun 19 20:14:04 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Fri, 19 Jun 2020 13:14:04 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Make Wa_14010229206 permanent In-Reply-To: <20200619080900.GD8425@kroah.com> References: <20200618202701.729-1-rodrigo.vivi@intel.com> <20200619080900.GD8425@kroah.com> Message-ID: <20200619201404.GI334084@intel.com> On Fri, Jun 19, 2020 at 10:09:00AM +0200, Greg KH wrote: > On Thu, Jun 18, 2020 at 01:27:00PM -0700, Rodrigo Vivi wrote: > > From: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> > > > > commit 63d0f3ea8ebb67160eca281320d255c72b0cb51a upstream. > > > > This workaround now applies to all steppings, not just A0. > > Wa_1409085225 is a temporary A0-only W/A however it is > > identical to Wa_14010229206 and hence the combined workaround > > is made permanent. > > Bspec: 52890 > > > > Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> > > Tested-by: Rafael Antognolli <rafael.antognolli at intel.com> > > Reviewed-by: Matt Roper <matthew.d.roper at intel.com> > > [mattrope: added missing blank line] > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > Link: https://patchwork.freedesktop.org/patch/msgid/20200326234955.16155-1-swathi.dhanavanthri at intel.com > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > What stable kernel(s) is this backport for? You need to give us a hint > :) It's for 5.7.y only. Sorry for not being clear > > thanks, > > greg k-h > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 5176ad1a3976..092a42367851 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -1379,12 +1379,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > > GEN7_FF_THREAD_MODE, > > GEN12_FF_TESSELATION_DOP_GATE_DISABLE); > > > > - /* > > - * Wa_1409085225:tgl > > - * Wa_14010229206:tgl > > - */ > > - wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); > > - > > /* Wa_1408615072:tgl */ > > wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > > VSUNIT_CLKGATE_DIS_TGL); > > @@ -1402,6 +1396,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > > wa_masked_en(wal, > > GEN9_CS_DEBUG_MODE1, > > FF_DOP_CLOCK_GATE_DISABLE); > > + > > + /* > > + * Wa_1409085225:tgl > > + * Wa_14010229206:tgl > > + */ > > + wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); > > } > > > > if (IS_GEN(i915, 11)) { > > -- > > 2.24.1 > > From patchwork at emeril.freedesktop.org Fri Jun 19 20:20:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 20:20:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Show_the_culmative_runtime_as_part_of_the_engine_in?= =?utf-8?q?fo?= In-Reply-To: <20200619191053.9654-1-chris@chris-wilson.co.uk> References: <20200619191053.9654-1-chris@chris-wilson.co.uk> Message-ID: <159259802960.12533.9944536573314775953@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Show the culmative runtime as part of the engine info URL : https://patchwork.freedesktop.org/series/78648/ State : success == Summary == CI Bug Log - changes from CI_DRM_8646 -> Patchwork_17997 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/index.html Known issues ------------ Here are the changes found in Patchwork_17997 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-bxt-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-bxt-dsi/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-bxt-dsi/igt at i915_module_load@reload.html #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-tgl-dsi/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8646 -> Patchwork_17997 CI-20190529: 20190529 CI_DRM_8646: 149f36f05192e8926ac39392cb7f904a4a9094f0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17997: 5dae6c717857aa484adbe45f1e81696c8cf39ce4 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5dae6c717857 drm/i915/gt: Show the culmative runtime as part of the engine info == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/index.html From jglisse at redhat.com Fri Jun 19 20:31:47 2020 From: jglisse at redhat.com (Jerome Glisse) Date: Fri, 19 Jun 2020 16:31:47 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619195538.GT6578@ziepe.ca> References: <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> <56008d64-772d-5757-6136-f20591ef71d2@amd.com> <20200619195538.GT6578@ziepe.ca> Message-ID: <20200619203147.GC13117@redhat.com> On Fri, Jun 19, 2020 at 04:55:38PM -0300, Jason Gunthorpe wrote: > On Fri, Jun 19, 2020 at 03:48:49PM -0400, Felix Kuehling wrote: > > Am 2020-06-19 um 2:18 p.m. schrieb Jason Gunthorpe: > > > On Fri, Jun 19, 2020 at 02:09:35PM -0400, Jerome Glisse wrote: > > >> On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > > >>> On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > > >>> > > >>>> The madness is only that device B's mmu notifier might need to wait > > >>>> for fence_B so that the dma operation finishes. Which in turn has to > > >>>> wait for device A to finish first. > > >>> So, it sound, fundamentally you've got this graph of operations across > > >>> an unknown set of drivers and the kernel cannot insert itself in > > >>> dma_fence hand offs to re-validate any of the buffers involved? > > >>> Buffers which by definition cannot be touched by the hardware yet. > > >>> > > >>> That really is a pretty horrible place to end up.. > > >>> > > >>> Pinning really is right answer for this kind of work flow. I think > > >>> converting pinning to notifers should not be done unless notifier > > >>> invalidation is relatively bounded. > > >>> > > >>> I know people like notifiers because they give a bit nicer performance > > >>> in some happy cases, but this cripples all the bad cases.. > > >>> > > >>> If pinning doesn't work for some reason maybe we should address that? > > >> Note that the dma fence is only true for user ptr buffer which predate > > >> any HMM work and thus were using mmu notifier already. You need the > > >> mmu notifier there because of fork and other corner cases. > > > I wonder if we should try to fix the fork case more directly - RDMA > > > has this same problem and added MADV_DONTFORK a long time ago as a > > > hacky way to deal with it. > > > > > > Some crazy page pin that resolved COW in a way that always kept the > > > physical memory with the mm that initiated the pin? > > > > > > (isn't this broken for O_DIRECT as well anyhow?) > > > > > > How does mmu_notifiers help the fork case anyhow? Block fork from > > > progressing? > > > > How much the mmu_notifier blocks fork progress depends, on quickly we > > can preempt GPU jobs accessing affected memory. If we don't have > > fine-grained preemption capability (graphics), the best we can do is > > wait for the GPU jobs to complete. We can also delay submission of new > > GPU jobs to the same memory until the MMU notifier is done. Future jobs > > would use the new page addresses. > > > > With fine-grained preemption (ROCm compute), we can preempt GPU work on > > the affected adders space to minimize the delay seen by fork. > > > > With recoverable device page faults, we can invalidate GPU page table > > entries, so device access to the affected pages stops immediately. > > > > In all cases, the end result is, that the device page table gets updated > > with the address of the copied pages before the GPU accesses the COW > > memory again.Without the MMU notifier, we'd end up with the GPU > > corrupting memory of the other process. > > The model here in fork has been wrong for a long time, and I do wonder > how O_DIRECT manages to not be broken too.. I guess the time windows > there are too small to get unlucky. This was discuss extensively in the GUP works John have been doing. Yes O_DIRECT can potentialy break but only if you are writting to COW pages and you initiated the O_DIRECT right before the fork and GUP happen before fork was able to write protect the pages. If you O_DIRECT but use memory as input ie you are writting the memory to the file not reading from the file. Then fork is harmless as you are just reading memory. You can still face the COW uncertainty (the process against which you did the O_DIRECT get "new" pages but your O_DIRECT goes on with the "old" pages) but doing O_DIRECT and fork concurently is asking for trouble. > > If you have a write pin on a page then it should not be COW'd into the > fork'd process but copied with the originating page remaining with the > original mm. > > I wonder if there is some easy way to achive that - if that is the > main reason to use notifiers then it would be a better solution. Not doable as page refcount can change for things unrelated to GUP, with John changes we can identify GUP and we could potentialy copy GUPed page instead of COW but this can potentialy slow down fork() and i am not sure how acceptable this would be. Also this does not solve GUP against page that are already in fork tree ie page P0 is in process A which forks, we now have page P0 in process A and B. Now we have process A which forks again and we have page P0 in A, B, and C. Here B and C are two branches with root in A. B and/or C can keep forking and grow the fork tree. Now if read only GUP on P0 happens in C (or B everything is symetrical in respect to root A) then P0 might not be the page that is in C after the GUP ie if something in C write to the virtual address corresponding to P0 then a new page might get allocated and the virtual address will no longer point to P0 for C. Semantic was change with 17839856fd588f4ab6b789f482ed3ffd7c403e1f to some what "fix" that but GUP fast is still succeptible to this. Note that above commit only address the GUP after/while forking. GUP before fork() need mmu notifier (or forcing page copy instead of COW). Cheers, J?r?me From daniel at ffwll.ch Fri Jun 19 20:43:20 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 19 Jun 2020 22:43:20 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200619201011.GB13117@redhat.com> References: <20200618150051.GS20149@phenom.ffwll.local> <20200618172338.GM6578@ziepe.ca> <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> <20200619201011.GB13117@redhat.com> Message-ID: <CAKMK7uFZgQH3bP4iC9MPArpngeSHESK62KFEeJvYyV9NSJ_GRw@mail.gmail.com> On Fri, Jun 19, 2020 at 10:10 PM Jerome Glisse <jglisse at redhat.com> wrote: > > On Fri, Jun 19, 2020 at 03:18:49PM -0300, Jason Gunthorpe wrote: > > On Fri, Jun 19, 2020 at 02:09:35PM -0400, Jerome Glisse wrote: > > > On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > > > > On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > > > > > > > > > The madness is only that device B's mmu notifier might need to wait > > > > > for fence_B so that the dma operation finishes. Which in turn has to > > > > > wait for device A to finish first. > > > > > > > > So, it sound, fundamentally you've got this graph of operations across > > > > an unknown set of drivers and the kernel cannot insert itself in > > > > dma_fence hand offs to re-validate any of the buffers involved? > > > > Buffers which by definition cannot be touched by the hardware yet. > > > > > > > > That really is a pretty horrible place to end up.. > > > > > > > > Pinning really is right answer for this kind of work flow. I think > > > > converting pinning to notifers should not be done unless notifier > > > > invalidation is relatively bounded. > > > > > > > > I know people like notifiers because they give a bit nicer performance > > > > in some happy cases, but this cripples all the bad cases.. > > > > > > > > If pinning doesn't work for some reason maybe we should address that? > > > > > > Note that the dma fence is only true for user ptr buffer which predate > > > any HMM work and thus were using mmu notifier already. You need the > > > mmu notifier there because of fork and other corner cases. > > > > I wonder if we should try to fix the fork case more directly - RDMA > > has this same problem and added MADV_DONTFORK a long time ago as a > > hacky way to deal with it. > > > > Some crazy page pin that resolved COW in a way that always kept the > > physical memory with the mm that initiated the pin? > > Just no way to deal with it easily, i thought about forcing the > anon_vma (page->mapping for anonymous page) to the anon_vma that > belongs to the vma against which the GUP was done but it would > break things if page is already in other branch of a fork tree. > Also this forbid fast GUP. > > Quite frankly the fork was not the main motivating factor. GPU > can pin potentialy GBytes of memory thus we wanted to be able > to release it but since Michal changes to reclaim code this is > no longer effective. What where how? My patch to annote reclaim paths with mmu notifier possibility just landed in -mm, so if direct reclaim can't reclaim mmu notifier'ed stuff anymore we need to know. Also this would resolve the entire pain we're discussing in this thread about dma_fence_wait deadlocking against anything that's not GFP_ATOMIC ... -Daniel > > User buffer should never end up in those weird corner case, iirc > the first usage was for xorg exa texture upload, then generalize > to texture upload in mesa and latter on to more upload cases > (vertices, ...). At least this is what i remember today. So in > those cases we do not expect fork, splice, mremap, mprotect, ... > > Maybe we can audit how user ptr buffer are use today and see if > we can define a usage pattern that would allow to cut corner in > kernel. For instance we could use mmu notifier just to block CPU > pte update while we do GUP and thus never wait on dma fence. > > Then GPU driver just keep the GUP pin around until they are done > with the page. They can also use the mmu notifier to keep a flag > so that the driver know if it needs to redo a GUP ie: > > The notifier path: > GPU_mmu_notifier_start_callback(range) > gpu_lock_cpu_pagetable(range) > for_each_bo_in(bo, range) { > bo->need_gup = true; > } > gpu_unlock_cpu_pagetable(range) > > GPU_validate_buffer_pages(bo) > if (!bo->need_gup) > return; > put_pages(bo->pages); > range = bo_vaddr_range(bo) > gpu_lock_cpu_pagetable(range) > GUP(bo->pages, range) > gpu_unlock_cpu_pagetable(range) > > > Depending on how user_ptr are use today this could work. > > > > (isn't this broken for O_DIRECT as well anyhow?) > > Yes it can in theory, if you have an application that does O_DIRECT > and fork concurrently (ie O_DIRECT in one thread and fork in another). > Note that O_DIRECT after fork is fine, it is an issue only if GUP_fast > was able to lookup a page with write permission before fork had the > chance to update it to read only for COW. > > But doing O_DIRECT (or anything that use GUP fast) in one thread and > fork in another is inherently broken ie there is no way to fix it. > > See 17839856fd588f4ab6b789f482ed3ffd7c403e1f > > > > > How does mmu_notifiers help the fork case anyhow? Block fork from > > progressing? > > It enforce ordering between fork and GUP, if fork is first it blocks > GUP and if forks is last then fork waits on GUP and then user buffer > get invalidated. > > > > > > I probably need to warn AMD folks again that using HMM means that you > > > must be able to update the GPU page table asynchronously without > > > fence wait. > > > > It is kind of unrelated to HMM, it just shouldn't be using mmu > > notifiers to replace page pinning.. > > Well my POV is that if you abide by rules HMM defined then you do > not need to pin pages. The rule is asynchronous device page table > update. > > Pinning pages is problematic it blocks many core mm features and > it is just bad all around. Also it is inherently broken in front > of fork/mremap/splice/... > > Cheers, > J?r?me > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Fri Jun 19 20:50:47 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 20:50:47 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gem=3A_Avoid_kmalloc_under_i915-=3Emm=5Flock?= In-Reply-To: <20200619194038.5088-1-chris@chris-wilson.co.uk> References: <20200619194038.5088-1-chris@chris-wilson.co.uk> Message-ID: <159259984755.12536.554419150118809392@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Avoid kmalloc under i915->mm_lock URL : https://patchwork.freedesktop.org/series/78650/ State : warning == Summary == $ dim checkpatch origin/drm-tip 04218f2bd97e drm/i915/gem: Avoid kmalloc under i915->mm_lock -:240: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment #240: FILE: drivers/gpu/drm/i915/i915_drv.h:991: + spinlock_t mm_lock; total: 0 errors, 0 warnings, 1 checks, 209 lines checked From jglisse at redhat.com Fri Jun 19 20:59:10 2020 From: jglisse at redhat.com (Jerome Glisse) Date: Fri, 19 Jun 2020 16:59:10 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <CAKMK7uFZgQH3bP4iC9MPArpngeSHESK62KFEeJvYyV9NSJ_GRw@mail.gmail.com> References: <CAKMK7uEbqTu4q-amkLXyd1i8KNtLaoO2ZFoGqYiG6D0m0FKpOg@mail.gmail.com> <20200619113934.GN6578@ziepe.ca> <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> <20200619201011.GB13117@redhat.com> <CAKMK7uFZgQH3bP4iC9MPArpngeSHESK62KFEeJvYyV9NSJ_GRw@mail.gmail.com> Message-ID: <20200619205910.GA14480@redhat.com> On Fri, Jun 19, 2020 at 10:43:20PM +0200, Daniel Vetter wrote: > On Fri, Jun 19, 2020 at 10:10 PM Jerome Glisse <jglisse at redhat.com> wrote: > > > > On Fri, Jun 19, 2020 at 03:18:49PM -0300, Jason Gunthorpe wrote: > > > On Fri, Jun 19, 2020 at 02:09:35PM -0400, Jerome Glisse wrote: > > > > On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > > > > > On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > > > > > > > > > > > The madness is only that device B's mmu notifier might need to wait > > > > > > for fence_B so that the dma operation finishes. Which in turn has to > > > > > > wait for device A to finish first. > > > > > > > > > > So, it sound, fundamentally you've got this graph of operations across > > > > > an unknown set of drivers and the kernel cannot insert itself in > > > > > dma_fence hand offs to re-validate any of the buffers involved? > > > > > Buffers which by definition cannot be touched by the hardware yet. > > > > > > > > > > That really is a pretty horrible place to end up.. > > > > > > > > > > Pinning really is right answer for this kind of work flow. I think > > > > > converting pinning to notifers should not be done unless notifier > > > > > invalidation is relatively bounded. > > > > > > > > > > I know people like notifiers because they give a bit nicer performance > > > > > in some happy cases, but this cripples all the bad cases.. > > > > > > > > > > If pinning doesn't work for some reason maybe we should address that? > > > > > > > > Note that the dma fence is only true for user ptr buffer which predate > > > > any HMM work and thus were using mmu notifier already. You need the > > > > mmu notifier there because of fork and other corner cases. > > > > > > I wonder if we should try to fix the fork case more directly - RDMA > > > has this same problem and added MADV_DONTFORK a long time ago as a > > > hacky way to deal with it. > > > > > > Some crazy page pin that resolved COW in a way that always kept the > > > physical memory with the mm that initiated the pin? > > > > Just no way to deal with it easily, i thought about forcing the > > anon_vma (page->mapping for anonymous page) to the anon_vma that > > belongs to the vma against which the GUP was done but it would > > break things if page is already in other branch of a fork tree. > > Also this forbid fast GUP. > > > > Quite frankly the fork was not the main motivating factor. GPU > > can pin potentialy GBytes of memory thus we wanted to be able > > to release it but since Michal changes to reclaim code this is > > no longer effective. > > What where how? My patch to annote reclaim paths with mmu notifier > possibility just landed in -mm, so if direct reclaim can't reclaim mmu > notifier'ed stuff anymore we need to know. > > Also this would resolve the entire pain we're discussing in this > thread about dma_fence_wait deadlocking against anything that's not > GFP_ATOMIC ... Sorry my bad, reclaim still works, only oom skip. It was couple years ago and i thought that some of the things discuss while back did make it upstream. It is probably a good time to also point out that what i wanted to do is have all the mmu notifier callback provide some kind of fence (not dma fence) so that we can split the notification into step: A- schedule notification on all devices/system get fences this step should minimize lock dependency and should not have to wait for anything also best if you can avoid memory allocation for instance by pre-allocating what you need for notification. B- mm can do things like unmap but can not map new page so write special swap pte to cpu page table C- wait on each fences from A ... resume old code ie replace pte or finish unmap ... The idea here is that at step C the core mm can decide to back off if any fence returned from A have to wait. This means that every device is invalidating for nothing but if we get there then it might still be a good thing as next time around maybe the kernel would be successfull without a wait. This would allow things like reclaim to make forward progress and skip over or limit wait time to given timeout. Also I thought to extend this even to multi-cpu tlb flush so that device and CPUs follow same pattern and we can make // progress on each. Getting to such scheme is a lot of work. My plan was to first get the fence as part of the notifier user API and hide it from mm inside notifier common code. Then update each core mm path to new model and see if there is any benefit from it. Reclaim would be first candidate. Cheers, J?r?me From patchwork at emeril.freedesktop.org Fri Jun 19 21:12:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 21:12:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Avoid_kmalloc_under_i915-=3Emm=5Flock?= In-Reply-To: <20200619194038.5088-1-chris@chris-wilson.co.uk> References: <20200619194038.5088-1-chris@chris-wilson.co.uk> Message-ID: <159260114078.12535.17526582688316187316@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Avoid kmalloc under i915->mm_lock URL : https://patchwork.freedesktop.org/series/78650/ State : success == Summary == CI Bug Log - changes from CI_DRM_8647 -> Patchwork_17998 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/index.html Known issues ------------ Here are the changes found in Patchwork_17998 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-tgl-dsi/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-tgl-dsi/igt at i915_module_load@reload.html - fi-tgl-u2: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-tgl-u2/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-tgl-u2/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-byt-n2820/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][13] ([i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#1982] / [i915#62] / [i915#92]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8647 -> Patchwork_17998 CI-20190529: 20190529 CI_DRM_8647: 71ab536a49048aff9e9bd07abb012785388be53a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17998: 04218f2bd97e5c2de77e5ffb28526b8169e55177 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 04218f2bd97e drm/i915/gem: Avoid kmalloc under i915->mm_lock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/index.html From patchwork at emeril.freedesktop.org Fri Jun 19 22:18:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 22:18:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Show_the_culmative_runtime_as_part_of_the_engine_in?= =?utf-8?q?fo?= In-Reply-To: <20200619191053.9654-1-chris@chris-wilson.co.uk> References: <20200619191053.9654-1-chris@chris-wilson.co.uk> Message-ID: <159260510056.12533.1927034084606327140@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Show the culmative runtime as part of the engine info URL : https://patchwork.freedesktop.org/series/78648/ State : success == Summary == CI Bug Log - changes from CI_DRM_8646_full -> Patchwork_17997_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17997_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_schedule@implicit-boths at bcs0: - shard-snb: [PASS][1] -> [INCOMPLETE][2] ([i915#82]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-snb4/igt at gem_exec_schedule@implicit-boths at bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-snb6/igt at gem_exec_schedule@implicit-boths at bcs0.html * igt at gem_mmap_offset@close-race: - shard-snb: [PASS][3] -> [TIMEOUT][4] ([i915#1958]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-snb2/igt at gem_mmap_offset@close-race.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-snb4/igt at gem_mmap_offset@close-race.html * igt at gem_tiled_blits@basic: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +16 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-apl3/igt at gem_tiled_blits@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-apl7/igt at gem_tiled_blits@basic.html * igt at i915_module_load@reload: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-tglb1/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-tglb5/igt at i915_module_load@reload.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180] / [i915#93] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl1/igt at i915_suspend@fence-restore-tiled2untiled.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl3/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at i915_suspend@sysfs-reader: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#69]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl8/igt at i915_suspend@sysfs-reader.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl1/igt at i915_suspend@sysfs-reader.html * igt at kms_color@pipe-a-ctm-red-to-blue: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#93] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl2/igt at kms_color@pipe-a-ctm-red-to-blue.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl1/igt at kms_color@pipe-a-ctm-red-to-blue.html * igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-glk6/igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-glk1/igt at kms_cursor_edge_walk@pipe-b-64x64-left-edge.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-tglb3/igt at kms_cursor_legacy@pipe-b-torture-move.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-tglb1/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_flip@flip-vs-suspend at b-dp1: - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl1/igt at kms_flip@flip-vs-suspend at b-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl4/igt at kms_flip@flip-vs-suspend at b-dp1.html * igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@no_drrs: - shard-iclb: [PASS][25] -> [FAIL][26] ([i915#173]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-iclb2/igt at kms_psr@no_drrs.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-iclb1/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-iclb3/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at kms_vblank@pipe-b-wait-forked-busy-hang: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +3 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl10/igt at kms_vblank@pipe-b-wait-forked-busy-hang.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl2/igt at kms_vblank@pipe-b-wait-forked-busy-hang.html #### Possible fixes #### * igt at gem_ctx_persistence@close-replace-race: - shard-skl: [TIMEOUT][31] ([i915#1340] / [i915#1958]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl6/igt at gem_ctx_persistence@close-replace-race.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl9/igt at gem_ctx_persistence@close-replace-race.html * igt at gem_exec_flush@basic-batch-kernel-default-wb: - shard-kbl: [DMESG-WARN][33] ([i915#165]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl2/igt at gem_exec_flush@basic-batch-kernel-default-wb.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl7/igt at gem_exec_flush@basic-batch-kernel-default-wb.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][35] ([i915#1930]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-glk1/igt at gem_exec_reloc@basic-concurrent0.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@implicit-read-write at bcs0: - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-snb4/igt at gem_exec_schedule@implicit-read-write at bcs0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-snb4/igt at gem_exec_schedule@implicit-read-write at bcs0.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][39] ([i915#1436] / [i915#716]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl1/igt at gen9_exec_parse@allowed-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl2/igt at gen9_exec_parse@allowed-all.html * igt at kms_big_fb@x-tiled-addfb-size-overflow: - shard-apl: [DMESG-WARN][41] ([i915#95]) -> [PASS][42] +16 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-apl4/igt at kms_big_fb@x-tiled-addfb-size-overflow.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-apl3/igt at kms_big_fb@x-tiled-addfb-size-overflow.html * igt at kms_big_fb@yf-tiled-16bpp-rotate-0: - shard-apl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-apl6/igt at kms_big_fb@yf-tiled-16bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-apl1/igt at kms_big_fb@yf-tiled-16bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +10 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl6/igt at kms_color@pipe-c-ctm-0-25.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl9/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-random: - shard-kbl: [DMESG-WARN][47] ([i915#78]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-256x256-random.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-256x256-random.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +5 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [INCOMPLETE][51] ([i915#300]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl9/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: [FAIL][53] ([i915#49]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-iclb1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-iclb5/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff: - shard-tglb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html * igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc: - shard-tglb: [SKIP][57] ([i915#668]) -> [PASS][58] +7 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-tglb6/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl1/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-FAIL][61] ([fdo#108145] / [i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_sprite_blt: - shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-iclb3/igt at kms_psr@psr2_sprite_blt.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-iclb2/igt at kms_psr@psr2_sprite_blt.html * igt at kms_vblank@pipe-b-accuracy-idle: - shard-glk: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-glk8/igt at kms_vblank@pipe-b-accuracy-idle.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-glk9/igt at kms_vblank@pipe-b-accuracy-idle.html * igt at kms_vblank@pipe-c-query-forked-busy: - shard-kbl: [DMESG-WARN][67] ([i915#62]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-kbl2/igt at kms_vblank@pipe-c-query-forked-busy.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-kbl7/igt at kms_vblank@pipe-c-query-forked-busy.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][69] ([i915#1542]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-iclb1/igt at perf@blocking-parameterized.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-iclb5/igt at perf@blocking-parameterized.html - shard-tglb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-tglb8/igt at perf@blocking-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-tglb3/igt at perf@blocking-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][73] ([i915#1930]) -> [TIMEOUT][74] ([i915#1958]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][75] ([i915#454]) -> [SKIP][76] ([i915#468]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-tglb5/igt at i915_pm_dc@dc6-dpms.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at kms_color_chamelium@pipe-a-gamma: - shard-snb: [SKIP][77] ([fdo#109271] / [fdo#111827]) -> [TIMEOUT][78] ([i915#1958]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-snb2/igt at kms_color_chamelium@pipe-a-gamma.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-snb4/igt at kms_color_chamelium@pipe-a-gamma.html * igt at kms_flip@2x-flip-vs-blocking-wf-vblank: - shard-snb: [SKIP][79] ([fdo#109271]) -> [TIMEOUT][80] ([i915#1958]) +2 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8646/shard-snb2/igt at kms_flip@2x-flip-vs-blocking-wf-vblank.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/shard-snb4/igt at kms_flip@2x-flip-vs-blocking-wf-vblank.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8646 -> Patchwork_17997 CI-20190529: 20190529 CI_DRM_8646: 149f36f05192e8926ac39392cb7f904a4a9094f0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17997: 5dae6c717857aa484adbe45f1e81696c8cf39ce4 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17997/index.html From patchwork at emeril.freedesktop.org Fri Jun 19 23:42:34 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 19 Jun 2020 23:42:34 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Avoid_kmalloc_under_i915-=3Emm=5Flock?= In-Reply-To: <20200619194038.5088-1-chris@chris-wilson.co.uk> References: <20200619194038.5088-1-chris@chris-wilson.co.uk> Message-ID: <159261015479.12533.8534815786216449835@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Avoid kmalloc under i915->mm_lock URL : https://patchwork.freedesktop.org/series/78650/ State : success == Summary == CI Bug Log - changes from CI_DRM_8647_full -> Patchwork_17998_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_17998_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#1930]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-glk7/igt at gem_exec_reloc@basic-concurrent0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-iclb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-iclb5/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-iclb3/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_big_fb@x-tiled-addfb-size-overflow: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#95]) +18 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-apl8/igt at kms_big_fb@x-tiled-addfb-size-overflow.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-apl6/igt at kms_big_fb@x-tiled-addfb-size-overflow.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-glk7/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-a-ctm-red-to-blue: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-kbl2/igt at kms_color@pipe-a-ctm-red-to-blue.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-kbl2/igt at kms_color@pipe-a-ctm-red-to-blue.html * igt at kms_cursor_edge_walk@pipe-b-128x128-right-edge: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-glk9/igt at kms_cursor_edge_walk@pipe-b-128x128-right-edge.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-glk8/igt at kms_cursor_edge_walk@pipe-b-128x128-right-edge.html * igt at kms_cursor_legacy@all-pipes-torture-move: - shard-tglb: [PASS][13] -> [DMESG-WARN][14] ([i915#128]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-tglb1/igt at kms_cursor_legacy@all-pipes-torture-move.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-tglb1/igt at kms_cursor_legacy@all-pipes-torture-move.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-kbl6/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-kbl4/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-dp1.html * igt at kms_flip@plain-flip-ts-check at c-edp1: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1928]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-skl2/igt at kms_flip@plain-flip-ts-check at c-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-skl7/igt at kms_flip@plain-flip-ts-check at c-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#49]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-iclb2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-tglb3/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_lease@page_flip_implicit_plane: - shard-skl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-skl8/igt at kms_lease@page_flip_implicit_plane.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-skl3/igt at kms_lease@page_flip_implicit_plane.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-skl3/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_basic: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-iclb2/igt at kms_psr@psr2_basic.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-iclb8/igt at kms_psr@psr2_basic.html #### Possible fixes #### * igt at gem_ctx_persistence@engines-cleanup at bcs0: - shard-apl: [DMESG-WARN][33] ([i915#95]) -> [PASS][34] +8 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-apl8/igt at gem_ctx_persistence@engines-cleanup at bcs0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-apl7/igt at gem_ctx_persistence@engines-cleanup at bcs0.html * igt at gem_shrink@reclaim: - shard-hsw: [SKIP][35] ([fdo#109271]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-hsw6/igt at gem_shrink@reclaim.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-hsw8/igt at gem_shrink@reclaim.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][37] ([i915#402]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-tglb8/igt at i915_module_load@reload.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-tglb3/igt at i915_module_load@reload.html * igt at kms_color@pipe-a-ctm-red-to-blue: - shard-skl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +9 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-skl4/igt at kms_color@pipe-a-ctm-red-to-blue.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-skl1/igt at kms_color@pipe-a-ctm-red-to-blue.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +10 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-kbl1/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-kbl1/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled: - shard-kbl: [DMESG-WARN][43] ([i915#93] / [i915#95]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-kbl2/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-kbl2/igt at kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html * igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1: - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-skl10/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-skl5/igt at kms_flip@plain-flip-ts-check-interruptible at a-edp1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][47] ([i915#1188]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-skl7/igt at kms_hdr@bpc-switch-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-skl8/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][49] ([i915#173]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-iclb1/igt at kms_psr@no_drrs.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-iclb4/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-iclb3/igt at kms_psr@psr2_cursor_render.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-b-accuracy-idle: - shard-apl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +3 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-apl8/igt at kms_vblank@pipe-b-accuracy-idle.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-apl7/igt at kms_vblank@pipe-b-accuracy-idle.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][55] ([i915#1542]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-iclb3/igt at perf@blocking-parameterized.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-iclb2/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_suspend@fence-restore-tiled2untiled: - shard-kbl: [DMESG-WARN][57] ([i915#180]) -> [DMESG-WARN][58] ([i915#93] / [i915#95]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-kbl3/igt at i915_suspend@fence-restore-tiled2untiled.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-kbl6/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-apl: [FAIL][59] ([i915#265]) -> [DMESG-FAIL][60] ([i915#95]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/shard-apl2/igt at kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/shard-apl2/igt at kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 12) ------------------------------ Additional (1): pig-snb-2600 Build changes ------------- * Linux: CI_DRM_8647 -> Patchwork_17998 CI-20190529: 20190529 CI_DRM_8647: 71ab536a49048aff9e9bd07abb012785388be53a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17998: 04218f2bd97e5c2de77e5ffb28526b8169e55177 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17998/index.html From chris at chris-wilson.co.uk Fri Jun 19 23:45:43 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sat, 20 Jun 2020 00:45:43 +0100 Subject: [Intel-gfx] [CI 2/2] drm/i915/gt: Replace manual kmap_atomic() with pin_map for renderstate In-Reply-To: <20200619234543.17499-1-chris@chris-wilson.co.uk> References: <20200619234543.17499-1-chris@chris-wilson.co.uk> Message-ID: <20200619234543.17499-2-chris@chris-wilson.co.uk> We only emit the renderstate once now during module load, it is no longer a concern that we are delaying context creation and so do not need to so eagerly optimise. Since the last time we have looked at the renderstate, we have a pin_map / flush_map facility that supports simple single mappings, replacing the open-coded kmap_atomic() and prepare_write. As it should be a single page, of which we only write a small portion, we stick to a simple WB [kmap] and use clflush on !llc platforms, rather than creating a temporary WC vmapping for the single page. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/gt/intel_renderstate.c | 29 +++++++-------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index f59e7875cc5e..6db23389e427 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -61,7 +61,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine) #define OUT_BATCH(batch, i, val) \ do { \ if ((i) >= PAGE_SIZE / sizeof(u32)) \ - goto err; \ + goto out; \ (batch)[(i)++] = (val); \ } while(0) @@ -70,15 +70,12 @@ static int render_state_setup(struct intel_renderstate *so, { const struct intel_renderstate_rodata *rodata = so->rodata; unsigned int i = 0, reloc_index = 0; - unsigned int needs_clflush; + int ret = -EINVAL; u32 *d; - int ret; - ret = i915_gem_object_prepare_write(so->vma->obj, &needs_clflush); - if (ret) - return ret; - - d = kmap_atomic(i915_gem_object_get_dirty_page(so->vma->obj, 0)); + d = i915_gem_object_pin_map(so->vma->obj, I915_MAP_WB); + if (IS_ERR(d)) + return PTR_ERR(d); while (i < rodata->batch_items) { u32 s = rodata->batch[i]; @@ -89,7 +86,7 @@ static int render_state_setup(struct intel_renderstate *so, if (HAS_64BIT_RELOC(i915)) { if (i + 1 >= rodata->batch_items || rodata->batch[i + 1] != 0) - goto err; + goto out; d[i++] = s; s = upper_32_bits(r); @@ -103,7 +100,7 @@ static int render_state_setup(struct intel_renderstate *so, if (rodata->reloc[reloc_index] != -1) { drm_err(&i915->drm, "only %d relocs resolved\n", reloc_index); - goto err; + goto out; } so->batch_offset = i915_ggtt_offset(so->vma); @@ -150,19 +147,11 @@ static int render_state_setup(struct intel_renderstate *so, */ so->aux_size = ALIGN(so->aux_size, 8); - if (needs_clflush) - drm_clflush_virt_range(d, i * sizeof(u32)); - kunmap_atomic(d); - ret = 0; out: - i915_gem_object_finish_access(so->vma->obj); + __i915_gem_object_flush_map(so->vma->obj, 0, i * sizeof(u32)); + i915_gem_object_unpin_map(so->vma->obj); return ret; - -err: - kunmap_atomic(d); - ret = -EINVAL; - goto out; } #undef OUT_BATCH -- 2.20.1 From chris at chris-wilson.co.uk Fri Jun 19 23:45:42 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Sat, 20 Jun 2020 00:45:42 +0100 Subject: [Intel-gfx] [CI 1/2] drm/i915/gvt: Drop redundant prepare_write/pin_pages Message-ID: <20200619234543.17499-1-chris@chris-wilson.co.uk> Since gvt calls pin_map for the shadow batch buffer, this makes the action of prepare_write [+pin_pages] redundant. We can write into the obj->mm.mapping directory and the flush_map routine knows when it has to flush the cpu cache afterwards. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld at intel.com> --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 14 +------- drivers/gpu/drm/i915/gvt/scheduler.c | 51 ++++++++------------------- drivers/gpu/drm/i915/gvt/scheduler.h | 2 -- 3 files changed, 15 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 8b87f130f7f1..f1940939260a 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1904,19 +1904,10 @@ static int perform_bb_shadow(struct parser_exec_state *s) goto err_free_bb; } - ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush); - if (ret) - goto err_free_obj; - bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB); if (IS_ERR(bb->va)) { ret = PTR_ERR(bb->va); - goto err_finish_shmem_access; - } - - if (bb->clflush & CLFLUSH_BEFORE) { - drm_clflush_virt_range(bb->va, bb->obj->base.size); - bb->clflush &= ~CLFLUSH_BEFORE; + goto err_free_obj; } ret = copy_gma_to_hva(s->vgpu, mm, @@ -1935,7 +1926,6 @@ static int perform_bb_shadow(struct parser_exec_state *s) INIT_LIST_HEAD(&bb->list); list_add(&bb->list, &s->workload->shadow_bb); - bb->accessing = true; bb->bb_start_cmd_va = s->ip_va; if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa)) @@ -1956,8 +1946,6 @@ static int perform_bb_shadow(struct parser_exec_state *s) return 0; err_unmap: i915_gem_object_unpin_map(bb->obj); -err_finish_shmem_access: - i915_gem_object_finish_access(bb->obj); err_free_obj: i915_gem_object_put(bb->obj); err_free_bb: diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 8fc2ad4517e9..3c3b9842bbbd 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -509,26 +509,18 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) bb->bb_start_cmd_va = workload->shadow_ring_buffer_va + bb->bb_offset; - if (bb->ppgtt) { - /* for non-priv bb, scan&shadow is only for - * debugging purpose, so the content of shadow bb - * is the same as original bb. Therefore, - * here, rather than switch to shadow bb's gma - * address, we directly use original batch buffer's - * gma address, and send original bb to hardware - * directly - */ - if (bb->clflush & CLFLUSH_AFTER) { - drm_clflush_virt_range(bb->va, - bb->obj->base.size); - bb->clflush &= ~CLFLUSH_AFTER; - } - i915_gem_object_finish_access(bb->obj); - bb->accessing = false; - - } else { + /* + * For non-priv bb, scan&shadow is only for + * debugging purpose, so the content of shadow bb + * is the same as original bb. Therefore, + * here, rather than switch to shadow bb's gma + * address, we directly use original batch buffer's + * gma address, and send original bb to hardware + * directly + */ + if (!bb->ppgtt) { bb->vma = i915_gem_object_ggtt_pin(bb->obj, - NULL, 0, 0, 0); + NULL, 0, 0, 0); if (IS_ERR(bb->vma)) { ret = PTR_ERR(bb->vma); goto err; @@ -539,27 +531,15 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) if (gmadr_bytes == 8) bb->bb_start_cmd_va[2] = 0; - /* No one is going to touch shadow bb from now on. */ - if (bb->clflush & CLFLUSH_AFTER) { - drm_clflush_virt_range(bb->va, - bb->obj->base.size); - bb->clflush &= ~CLFLUSH_AFTER; - } - - ret = i915_gem_object_set_to_gtt_domain(bb->obj, - false); - if (ret) - goto err; - ret = i915_vma_move_to_active(bb->vma, workload->req, 0); if (ret) goto err; - - i915_gem_object_finish_access(bb->obj); - bb->accessing = false; } + + /* No one is going to touch shadow bb from now on. */ + i915_gem_object_flush_map(bb->obj); } return 0; err: @@ -630,9 +610,6 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) { if (bb->obj) { - if (bb->accessing) - i915_gem_object_finish_access(bb->obj); - if (bb->va && !IS_ERR(bb->va)) i915_gem_object_unpin_map(bb->obj); diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h index 15d317f2a4a4..64e7a0b791c3 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.h +++ b/drivers/gpu/drm/i915/gvt/scheduler.h @@ -124,8 +124,6 @@ struct intel_vgpu_shadow_bb { struct i915_vma *vma; void *va; u32 *bb_start_cmd_va; - unsigned int clflush; - bool accessing; unsigned long bb_offset; bool ppgtt; }; -- 2.20.1 From lkp at intel.com Fri Jun 19 23:56:15 2020 From: lkp at intel.com (kernel test robot) Date: Sat, 20 Jun 2020 07:56:15 +0800 Subject: [Intel-gfx] [drm-intel:topic/core-for-CI 17/21] include/net/ax25.h:121:24: error: redeclaration of enumerator 'AX25_PROTO_DAMA_MASTER' Message-ID: <202006200702.0F3Jbjbf%lkp@intel.com> tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI head: 7baab4e528ef38546a32f0a368285289aa2c981f commit: 11be607ccb68a1604ce6768a3cfb1fb528cc401a [17/21] Revert "drm/i915: Don't select BROKEN" config: i386-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): git checkout 11be607ccb68a1604ce6768a3cfb1fb528cc401a # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>): In file included from net/ipv4/arp.c:110: >> include/net/ax25.h:121:24: error: redeclaration of enumerator 'AX25_PROTO_DAMA_MASTER' 121 | #define AX25_PROTO_MAX AX25_PROTO_DAMA_MASTER | ^~~~~~~~~~~~~~~~~~~~~~ include/net/ax25.h:125:2: note: in expansion of macro 'AX25_PROTO_MAX' 125 | AX25_PROTO_MAX = __AX25_PROTO_MAX -1 | ^~~~~~~~~~~~~~ include/net/ax25.h:120:2: note: previous definition of 'AX25_PROTO_DAMA_MASTER' was here 120 | AX25_PROTO_DAMA_MASTER, | ^~~~~~~~~~~~~~~~~~~~~~ vim +/AX25_PROTO_DAMA_MASTER +121 include/net/ax25.h ^1da177e4c3f41 Linus Torvalds 2005-04-16 113 ^1da177e4c3f41 Linus Torvalds 2005-04-16 114 enum { ^1da177e4c3f41 Linus Torvalds 2005-04-16 115 AX25_PROTO_STD_SIMPLEX, ^1da177e4c3f41 Linus Torvalds 2005-04-16 116 AX25_PROTO_STD_DUPLEX, c7c694d196a39a Ralf Baechle 2006-03-19 117 #ifdef CONFIG_AX25_DAMA_SLAVE ^1da177e4c3f41 Linus Torvalds 2005-04-16 118 AX25_PROTO_DAMA_SLAVE, c7c694d196a39a Ralf Baechle 2006-03-19 119 #ifdef CONFIG_AX25_DAMA_MASTER c7c694d196a39a Ralf Baechle 2006-03-19 120 AX25_PROTO_DAMA_MASTER, c7c694d196a39a Ralf Baechle 2006-03-19 @121 #define AX25_PROTO_MAX AX25_PROTO_DAMA_MASTER c7c694d196a39a Ralf Baechle 2006-03-19 122 #endif c7c694d196a39a Ralf Baechle 2006-03-19 123 #endif c7c694d196a39a Ralf Baechle 2006-03-19 124 __AX25_PROTO_MAX, c7c694d196a39a Ralf Baechle 2006-03-19 125 AX25_PROTO_MAX = __AX25_PROTO_MAX -1 ^1da177e4c3f41 Linus Torvalds 2005-04-16 126 }; ^1da177e4c3f41 Linus Torvalds 2005-04-16 127 :::::: The code at line 121 was first introduced by commit :::::: c7c694d196a39af6e644e24279953d04f30362db [AX.25]: Fix potencial memory hole. :::::: TO: Ralf Baechle DL5RB <ralf at linux-mips.org> :::::: CC: David S. Miller <davem at davemloft.net> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 74239 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200620/89a32d14/attachment-0001.gz> From lkp at intel.com Sat Jun 20 00:07:45 2020 From: lkp at intel.com (kernel test robot) Date: Sat, 20 Jun 2020 08:07:45 +0800 Subject: [Intel-gfx] [drm-intel:topic/core-for-CI 17/21] drivers/staging/media/soc_camera/soc_mediabus.c:19:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' Message-ID: <202006200836.ATsXJORs%lkp@intel.com> Hi Joonas, First bad commit (maybe != root cause): tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI head: 7baab4e528ef38546a32f0a368285289aa2c981f commit: 11be607ccb68a1604ce6768a3cfb1fb528cc401a [17/21] Revert "drm/i915: Don't select BROKEN" config: i386-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-13) 9.3.0 reproduce (this is a W=1 build): git checkout 11be607ccb68a1604ce6768a3cfb1fb528cc401a # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>): >> drivers/staging/media/soc_camera/soc_mediabus.c:19:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 19 | .name = "YUYV", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:19:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 19 | .name = "YUYV", | ^~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:29:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 29 | .name = "YVYU", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:29:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 29 | .name = "YVYU", | ^~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:39:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 39 | .name = "UYVY", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:39:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 39 | .name = "UYVY", | ^~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:49:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 49 | .name = "VYUY", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:49:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 49 | .name = "VYUY", | ^~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:59:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 59 | .name = "RGB555", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:59:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 59 | .name = "RGB555", | ^~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:69:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 69 | .name = "RGB555X", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:69:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 69 | .name = "RGB555X", | ^~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:79:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 79 | .name = "RGB565", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:79:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 79 | .name = "RGB565", | ^~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:89:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 89 | .name = "RGB565X", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:89:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 89 | .name = "RGB565X", | ^~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:99:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 99 | .name = "RGB666/32bpp", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:99:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 99 | .name = "RGB666/32bpp", | ^~~~~~~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:108:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 108 | .name = "RGB888/32bpp", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:108:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 108 | .name = "RGB888/32bpp", | ^~~~~~~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:117:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 117 | .name = "RGB888/32bpp", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:117:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 117 | .name = "RGB888/32bpp", | ^~~~~~~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:126:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 126 | .name = "RGB888/32bpp", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:126:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 126 | .name = "RGB888/32bpp", | ^~~~~~~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:135:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 135 | .name = "Bayer 8 BGGR", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:135:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 135 | .name = "Bayer 8 BGGR", | ^~~~~~~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:145:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 145 | .name = "Bayer 10 BGGR", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:145:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 145 | .name = "Bayer 10 BGGR", | ^~~~~~~~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:155:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 155 | .name = "Grey", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:155:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 155 | .name = "Grey", | ^~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:165:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 165 | .name = "Grey 10bit", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:165:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 165 | .name = "Grey 10bit", | ^~~~~~~~~~~~ drivers/staging/media/soc_camera/soc_mediabus.c:175:4: error: 'struct soc_mbus_pixelfmt' has no member named 'name' 175 | .name = "Bayer 10 BGGR", | ^~~~ drivers/staging/media/soc_camera/soc_mediabus.c:175:13: error: incompatible types when initializing type 'enum soc_mbus_packing' using type 'char *' 175 | .name = "Bayer 10 BGGR", vim +19 drivers/staging/media/soc_camera/soc_mediabus.c 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 13 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 14 static const struct soc_mbus_lookup mbus_fmt[] = { 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 15 { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 16 .code = MEDIA_BUS_FMT_YUYV8_2X8, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 17 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 18 .fourcc = V4L2_PIX_FMT_YUYV, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 @19 .name = "YUYV", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 20 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 21 .packing = SOC_MBUS_PACKING_2X8_PADHI, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 22 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 23 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 24 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 25 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 26 .code = MEDIA_BUS_FMT_YVYU8_2X8, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 27 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 28 .fourcc = V4L2_PIX_FMT_YVYU, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 29 .name = "YVYU", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 30 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 31 .packing = SOC_MBUS_PACKING_2X8_PADHI, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 32 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 33 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 34 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 35 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 36 .code = MEDIA_BUS_FMT_UYVY8_2X8, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 37 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 38 .fourcc = V4L2_PIX_FMT_UYVY, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 39 .name = "UYVY", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 40 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 41 .packing = SOC_MBUS_PACKING_2X8_PADHI, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 42 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 43 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 44 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 45 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 46 .code = MEDIA_BUS_FMT_VYUY8_2X8, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 47 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 48 .fourcc = V4L2_PIX_FMT_VYUY, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 49 .name = "VYUY", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 50 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 51 .packing = SOC_MBUS_PACKING_2X8_PADHI, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 52 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 53 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 54 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 55 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 56 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 57 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 58 .fourcc = V4L2_PIX_FMT_RGB555, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 59 .name = "RGB555", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 60 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 61 .packing = SOC_MBUS_PACKING_2X8_PADHI, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 62 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 63 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 64 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 65 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 66 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 67 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 68 .fourcc = V4L2_PIX_FMT_RGB555X, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 69 .name = "RGB555X", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 70 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 71 .packing = SOC_MBUS_PACKING_2X8_PADHI, abcb6b99f5e5d2c drivers/media/platform/soc_camera/soc_mediabus.c Guennadi Liakhovetski 2013-03-08 72 .order = SOC_MBUS_ORDER_BE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 73 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 74 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 75 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 76 .code = MEDIA_BUS_FMT_RGB565_2X8_LE, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 77 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 78 .fourcc = V4L2_PIX_FMT_RGB565, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 79 .name = "RGB565", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 80 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 81 .packing = SOC_MBUS_PACKING_2X8_PADHI, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 82 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 83 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 84 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 85 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 86 .code = MEDIA_BUS_FMT_RGB565_2X8_BE, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 87 .fmt = { 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 88 .fourcc = V4L2_PIX_FMT_RGB565X, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 89 .name = "RGB565X", 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 90 .bits_per_sample = 8, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 91 .packing = SOC_MBUS_PACKING_2X8_PADHI, abcb6b99f5e5d2c drivers/media/platform/soc_camera/soc_mediabus.c Guennadi Liakhovetski 2013-03-08 92 .order = SOC_MBUS_ORDER_BE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 93 .layout = SOC_MBUS_LAYOUT_PACKED, 81355e40826acea drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-24 94 }, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 95 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 96 .code = MEDIA_BUS_FMT_RGB666_1X18, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 97 .fmt = { 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 98 .fourcc = V4L2_PIX_FMT_RGB32, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 99 .name = "RGB666/32bpp", 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 100 .bits_per_sample = 18, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 101 .packing = SOC_MBUS_PACKING_EXTEND32, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 102 .order = SOC_MBUS_ORDER_LE, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 103 }, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 104 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 105 .code = MEDIA_BUS_FMT_RGB888_1X24, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 106 .fmt = { 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 107 .fourcc = V4L2_PIX_FMT_RGB32, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 108 .name = "RGB888/32bpp", 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 109 .bits_per_sample = 24, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 110 .packing = SOC_MBUS_PACKING_EXTEND32, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 111 .order = SOC_MBUS_ORDER_LE, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 112 }, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 113 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 114 .code = MEDIA_BUS_FMT_RGB888_2X12_BE, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 115 .fmt = { 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 116 .fourcc = V4L2_PIX_FMT_RGB32, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 117 .name = "RGB888/32bpp", 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 118 .bits_per_sample = 12, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 119 .packing = SOC_MBUS_PACKING_EXTEND32, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 120 .order = SOC_MBUS_ORDER_BE, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 121 }, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 122 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 123 .code = MEDIA_BUS_FMT_RGB888_2X12_LE, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 124 .fmt = { 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 125 .fourcc = V4L2_PIX_FMT_RGB32, 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 126 .name = "RGB888/32bpp", 7b88fc086a217be drivers/media/platform/soc_camera/soc_mediabus.c Phil Edworthy 2013-03-18 127 .bits_per_sample = 12, 7b88fc086a217be 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drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 262 .code = MEDIA_BUS_FMT_VYUY8_1X16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 263 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 264 .fourcc = V4L2_PIX_FMT_VYUY, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 265 .name = "VYUY 16bit", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 266 .bits_per_sample = 16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 267 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 268 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 269 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 270 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 271 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 272 .code = MEDIA_BUS_FMT_YUYV8_1X16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 273 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 274 .fourcc = V4L2_PIX_FMT_YUYV, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 275 .name = "YUYV 16bit", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 276 .bits_per_sample = 16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 277 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 278 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 279 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 280 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 281 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 282 .code = MEDIA_BUS_FMT_YVYU8_1X16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 283 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 284 .fourcc = V4L2_PIX_FMT_YVYU, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 285 .name = "YVYU 16bit", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 286 .bits_per_sample = 16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 287 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 288 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 289 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 290 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 291 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 292 .code = MEDIA_BUS_FMT_SGRBG8_1X8, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 293 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 294 .fourcc = V4L2_PIX_FMT_SGRBG8, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 295 .name = "Bayer 8 GRBG", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 296 .bits_per_sample = 8, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 297 .packing = SOC_MBUS_PACKING_NONE, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 298 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 299 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 300 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 301 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 302 .code = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 303 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 304 .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 305 .name = "Bayer 10 BGGR DPCM 8", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 306 .bits_per_sample = 8, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 307 .packing = SOC_MBUS_PACKING_NONE, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 308 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 309 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 310 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 311 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 312 .code = MEDIA_BUS_FMT_SGBRG10_1X10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 313 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 314 .fourcc = V4L2_PIX_FMT_SGBRG10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 315 .name = "Bayer 10 GBRG", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 316 .bits_per_sample = 10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 317 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 318 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 319 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 320 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 321 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 322 .code = MEDIA_BUS_FMT_SGRBG10_1X10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 323 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 324 .fourcc = V4L2_PIX_FMT_SGRBG10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 325 .name = "Bayer 10 GRBG", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 326 .bits_per_sample = 10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 327 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 328 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 329 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 330 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 331 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 332 .code = MEDIA_BUS_FMT_SRGGB10_1X10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 333 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 334 .fourcc = V4L2_PIX_FMT_SRGGB10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 335 .name = "Bayer 10 RGGB", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 336 .bits_per_sample = 10, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 337 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 338 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 339 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 340 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 341 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 342 .code = MEDIA_BUS_FMT_SBGGR12_1X12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 343 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 344 .fourcc = V4L2_PIX_FMT_SBGGR12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 345 .name = "Bayer 12 BGGR", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 346 .bits_per_sample = 12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 347 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 348 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 349 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 350 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 351 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 352 .code = MEDIA_BUS_FMT_SGBRG12_1X12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 353 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 354 .fourcc = V4L2_PIX_FMT_SGBRG12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 355 .name = "Bayer 12 GBRG", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 356 .bits_per_sample = 12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 357 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 358 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 359 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 360 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 361 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 362 .code = MEDIA_BUS_FMT_SGRBG12_1X12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 363 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 364 .fourcc = V4L2_PIX_FMT_SGRBG12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 365 .name = "Bayer 12 GRBG", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 366 .bits_per_sample = 12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 367 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 368 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 369 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 370 }, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 371 }, { 27ffaeb0ab16085 drivers/media/platform/soc_camera/soc_mediabus.c Boris Brezillon 2014-11-10 372 .code = MEDIA_BUS_FMT_SRGGB12_1X12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 373 .fmt = { e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 374 .fourcc = V4L2_PIX_FMT_SRGGB12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 375 .name = "Bayer 12 RGGB", e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 376 .bits_per_sample = 12, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 377 .packing = SOC_MBUS_PACKING_EXTEND16, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 378 .order = SOC_MBUS_ORDER_LE, ad3b81faa1db60b drivers/media/video/soc_mediabus.c Laurent Pinchart 2012-03-21 379 .layout = SOC_MBUS_LAYOUT_PACKED, e23b961dd1206ac drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-17 380 }, 93f116d595e9aa7 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2011-05-13 381 }, 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 382 }; 9a74251d8bee7a2 drivers/media/video/soc_mediabus.c Guennadi Liakhovetski 2009-12-11 383 :::::: The code at line 19 was first introduced by commit :::::: 9a74251d8bee7a25fee89a0be3ccea73e01c1a05 V4L/DVB (13658): v4l: add a media-bus API for configuring v4l2 subdev pixel and frame formats :::::: TO: Guennadi Liakhovetski <g.liakhovetski at gmx.de> :::::: CC: Mauro Carvalho Chehab <mchehab at redhat.com> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all at lists.01.org -------------- next part -------------- A non-text attachment was scrubbed... Name: .config.gz Type: application/gzip Size: 74239 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200620/890cb275/attachment-0001.gz> From patchwork at emeril.freedesktop.org Sat Jun 20 00:19:06 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 20 Jun 2020 00:19:06 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5BCI=2C1/2=5D_drm/i915/gvt=3A_Drop_redund?= =?utf-8?q?ant_prepare=5Fwrite/pin=5Fpages?= In-Reply-To: <20200619234543.17499-1-chris@chris-wilson.co.uk> References: <20200619234543.17499-1-chris@chris-wilson.co.uk> Message-ID: <159261234635.5570.9533698568551003396@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/2] drm/i915/gvt: Drop redundant prepare_write/pin_pages URL : https://patchwork.freedesktop.org/series/78655/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 From patchwork at emeril.freedesktop.org Sat Jun 20 00:35:19 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 20 Jun 2020 00:35:19 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5BCI=2C1/2=5D_drm/i915/gvt=3A_Drop_redundant?= =?utf-8?q?_prepare=5Fwrite/pin=5Fpages?= In-Reply-To: <20200619234543.17499-1-chris@chris-wilson.co.uk> References: <20200619234543.17499-1-chris@chris-wilson.co.uk> Message-ID: <159261331915.5570.11087154847253141464@emeril.freedesktop.org> == Series Details == Series: series starting with [CI,1/2] drm/i915/gvt: Drop redundant prepare_write/pin_pages URL : https://patchwork.freedesktop.org/series/78655/ State : success == Summary == CI Bug Log - changes from CI_DRM_8647 -> Patchwork_17999 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/index.html Known issues ------------ Here are the changes found in Patchwork_17999 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-tgl-dsi/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-tgl-dsi/igt at i915_module_load@reload.html - fi-byt-n2820: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-byt-n2820/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-guc: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-icl-guc/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8647/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8647 -> Patchwork_17999 CI-20190529: 20190529 CI_DRM_8647: 71ab536a49048aff9e9bd07abb012785388be53a @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17999: f35d9d302ad5b332467a7f3d29d3bc76f8ce0acd @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f35d9d302ad5 drm/i915/gt: Replace manual kmap_atomic() with pin_map for renderstate 51a62c8a65a8 drm/i915/gvt: Drop redundant prepare_write/pin_pages == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17999/index.html From hdegoede at redhat.com Sat Jun 20 12:17:43 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:43 +0200 Subject: [Intel-gfx] [PATCH v3 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API Message-ID: <20200620121758.14836-1-hdegoede@redhat.com> Hi All, Here is v3 of my patch series converting the i915 driver's code for controlling the panel's backlight with an external PWM controller to use the atomic PWM API. See below for the changelog. Initially the plan was for this series to consist of 2 parts: 1. convert the pwm-crc driver to support the atomic PWM API and 2. convert the i915 driver's PWM code to use the atomic PWM API. But during testing I've found a number of bugs in the pwm-lpss and I found that the acpi_lpss code needs some special handling because of some ugliness found in most Cherry Trail DSDTs. So now this series has grown somewhat large and consists of 4 parts: 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness 2. various fixes to the pwm-lpss driver 3. convert the pwm-crc driver to support the atomic PWM API and 4. convert the i915 driver's PWM code to use the atomic PWM API So we need to discuss how to merge this (once it passes review). Although the inter-dependencies are only runtime I still think we should make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before merging the i915 changes. Both to make sure that the intel-gfx CI system does not become unhappy and for bisecting reasons. The involved acpi_lpss and pwm drivers do not see a whole lot of churn, so it likely is the easiest to just merge everything through dinq. Rafael and Thierry, can I get your Acked-by for directly merging this into dinq? This series has been tested (and re-tested after adding various bug-fixes) extensively. It has been tested on the following devices: -Asus T100TA BYT + CRC-PMIC PWM -Toshiba WT8-A BYT + CRC-PMIC PWM -Thundersoft TS178 BYT + CRC-PMIC PWM, inverse PWM -Asus T100HA CHT + CRC-PMIC PWM -Terra Pad 1061 BYT + LPSS PWM -Trekstor Twin 10.1 BYT + LPSS PWM -Asus T101HA CHT + CRC-PMIC PWM -GPD Pocket CHT + CRC-PMIC PWM Changelog: Changes in v2: - Fix coverletter subject - Drop accidentally included debugging patch - "[PATCH v3 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once ( - Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX Changes in v3: - "[PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value" - Use base_unit_range - 1 as maximum value for the clamp() - "[PATCH v3 05/15] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume" - This replaces the "pwm: lpss: Set SW_UPDATE bit when enabling the PWM" patch from previous versions of this patch-set, which really was a hack working around the resume issue which this patch fixes properly. - PATCH v3 6 - 11 pwm-crc changes: - Various small changes resulting from the reviews by Andy and Uwe, including some refactoring of the patches to reduce the amount of churn in the patch-set Regards, Hans From hdegoede at redhat.com Sat Jun 20 12:17:44 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:44 +0200 Subject: [Intel-gfx] [PATCH v3 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-2-hdegoede@redhat.com> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM controller gets poked from the _PS0 method of the graphics-card device: Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ If (((Local0 & 0x03) == 0x03)) { PSAT &= 0xFFFFFFFC Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ RSTA = Zero RSTF = Zero RSTA = One RSTF = One PWMB |= 0xC0000000 PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */ } Where PSAT is the power-status register of the PWM controller, so if it is in D3 when the GFX0 device's PS0 method runs then it will turn it on and restore the PWM ctrl register value it saved from its PS3 handler. Note not only does it restore it, it ors it with 0xC0000000 turning it on at a time where we may not want it to get turned on at all. The pwm_get call which the i915 driver does to get a reference to the PWM controller, already adds a device-link making the GFX0 device a consumer of the PWM device. So it should already have been resumed when the above AML runs and the AML should thus not do its undesirable poking of the PWM controller register. But the PCI core powers on PCI devices in the no-irq resume phase and thus calls the troublesome PS0 method in the no-irq resume phase. Where as LPSS devices by default are resumed in the early resume phase. This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc struct, so that Cherry Trail PWM controllers will be resumed in the no-irq phase. Together with the device-link added by the pwm-get this ensures that the PWM controller will be on when the troublesome PS0 method runs, which stops it from poking the PWM controller. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/acpi/acpi_lpss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index c5a5a179f49d..446e666b3466 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = { .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, .prv_offset = 0x800, .setup = bsw_pwm_setup, + .resume_from_noirq = true, }; static const struct lpss_device_desc byt_uart_dev_desc = { -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:45 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:45 +0200 Subject: [Intel-gfx] [PATCH v3 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-3-hdegoede@redhat.com> The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM controller gets turned off from the _PS3 method of the graphics-card dev: Method (_PS3, 0, Serialized) // _PS3: Power State 3 { ... PWMB = PWMC /* \_SB_.PCI0.GFX0.PWMC */ PSAT |= 0x03 Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ ... } Where PSAT is the power-status register of the PWM controller. Since the i915 driver will do a pwm_get on the pwm device as it uses it to control the LCD panel backlight, there is a device-link marking the i915 device as a consumer of the pwm device. So that the PWM controller will always be suspended after the i915 driver suspends (which is the right thing to do). This causes the above GFX0 PS3 AML code to run before acpi_lpss.c calls acpi_lpss_save_ctx(). So on these devices the PWM controller will already be off when acpi_lpss_save_ctx() runs. This causes it to read/save all 1-s (0xffffffff) as ctx register values. When these bogus values get restored on resume the PWM controller actually keeps working, since most bits are reserved, but this does set bit 3 of the LPSS General purpose register, which for the PWM controller has the following function: "This bit is re-used to support 32kHz slow mode. Default is 19.2MHz as PWM source clock". This causes the clock of the PWM controller to switch from 19.2MHz to 32KHz, which is a slow-down of a factor 600. Surprisingly enough so far there have been few bug reports about this. This is likely because the i915 driver was hardcoding the PWM frequency to 46 KHz, which divided by 600 would result in a PWM frequency of approx. 78 Hz, which mostly still works fine. There are some bug reports about the LCD backlight flickering after suspend/resume which are likely caused by this issue. But with the upcoming patch-series to finally switch the i915 drivers code for external PWM controllers to use the atomic API and to honor the PWM frequency specified in the video BIOS (VBT), this becomes a much bigger problem. On most cases the VBT specifies either 200 Hz or 20 KHz as PWM frequency, which with the mentioned issue ends up being either 1/3 Hz, where the backlight actually visible blinks on and off every 3s, or in 33 Hz and horrible flickering of the backlight. There are a number of possible solutions to this problem: 1. Make acpi_lpss_save_ctx() run before GFX0._PS3 Pro: Clean solution from pov of not medling with save/restore ctx code Con: As mentioned the current ordering is the right thing to do Con: Requires assymmetry in at what suspend/resume phase we do the save vs restore, requiring more suspend/resume ordering hacks in already convoluted acpi_lpss.c suspend/resume code. 2. Do some sort of save once mode for the LPSS ctx Pro: Reasonably clean Con: Needs a new LPSS flag + code changes to handle the flag 3. Detect we have failed to save the ctx registers and do not restore them Pro: Not PWM specific, might help with issues on other LPSS devices too Con: If we can get away with not restoring the ctx why bother with it at all? 4. Do not save the ctx for CHT PWM controllers Pro: Clean, as simple as dropping a flag? Con: Not so simple as dropping a flag, needs a new flag to ensure that we still do lpss_deassert_reset() on device activation. 5. Make the pwm-lpss code fixup the LPSS-context registers Pro: Keeps acpi_lpss.c code clean Con: Moves knowledge of LPSS-context into the pwm-lpss.c code 1 and 5 both do not seem to be a desirable way forward. 3 and 4 seem ok, but they both assume that restoring the LPSS-context registers is not necessary. I have done a couple of test and those do show that restoring the LPSS-context indeed does not seem to be necessary on devices using s2idle suspend (and successfully reaching S0i3). But I have no hardware to test deep / S3 suspend. So I'm not sure that not restoring the context is safe. That leaves solution 2, which is about as simple / clean as 3 and 4, so this commit fixes the described problem by implementing a new LPSS_SAVE_CTX_ONCE flag and setting that for the CHT PWM controllers. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v2: - Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX --- drivers/acpi/acpi_lpss.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 446e666b3466..7e6db0f1d9ee 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -67,7 +67,15 @@ ACPI_MODULE_NAME("acpi_lpss"); #define LPSS_CLK_DIVIDER BIT(2) #define LPSS_LTR BIT(3) #define LPSS_SAVE_CTX BIT(4) -#define LPSS_NO_D3_DELAY BIT(5) +/* + * For some devices the DSDT AML code for another device turns off the device + * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) + * as ctx register values. + * Luckily these devices always use the same ctx register values, so we can + * work around this by saving the ctx registers once on activation. + */ +#define LPSS_SAVE_CTX_ONCE BIT(5) +#define LPSS_NO_D3_DELAY BIT(6) struct lpss_private_data; @@ -254,7 +262,7 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { }; static const struct lpss_device_desc bsw_pwm_dev_desc = { - .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, + .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, .prv_offset = 0x800, .setup = bsw_pwm_setup, .resume_from_noirq = true, @@ -885,9 +893,14 @@ static int acpi_lpss_activate(struct device *dev) * we have to deassert reset line to be sure that ->probe() will * recognize the device. */ - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) lpss_deassert_reset(pdata); +#ifdef CONFIG_PM + if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) + acpi_lpss_save_ctx(dev, pdata); +#endif + return 0; } @@ -1036,7 +1049,7 @@ static int acpi_lpss_resume(struct device *dev) acpi_lpss_d3_to_d0_delay(pdata); - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) acpi_lpss_restore_ctx(dev, pdata); return 0; -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:46 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:46 +0200 Subject: [Intel-gfx] [PATCH v3 03/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-4-hdegoede@redhat.com> According to the data-sheet the way the PWM controller works is that each input clock-cycle the base_unit gets added to a N bit counter and that counter overflowing determines the PWM output frequency. So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, after 65535 input clock-cycles the counter has been increased from 0 to 65535 and it will overflow on the next cycle, so it will overflow after every 65536 clock cycles and thus the calculations done in pwm_lpss_prepare() should use 65536 and not 65535. This commit fixes this. Note this also aligns the calculations in pwm_lpss_prepare() with those in pwm_lpss_get_state(). Note this effectively reverts commit 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit"). The next patch in this series really fixes the potential overflow of the base_unit value. Fixes: 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit") Reviewed-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com> Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - Add Fixes tag - Add Reviewed-by: Andy Shevchenko tag --- drivers/pwm/pwm-lpss.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 9d965ffe66d1..43b1fc634af1 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -93,7 +93,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, * The equation is: * base_unit = round(base_unit_range * freq / c) */ - base_unit_range = BIT(lpwm->info->base_unit_bits) - 1; + base_unit_range = BIT(lpwm->info->base_unit_bits); freq *= base_unit_range; base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); @@ -104,8 +104,8 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, orig_ctrl = ctrl = pwm_lpss_read(pwm); ctrl &= ~PWM_ON_TIME_DIV_MASK; - ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); - base_unit &= base_unit_range; + ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); + base_unit &= (base_unit_range - 1); ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:47 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:47 +0200 Subject: [Intel-gfx] [PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-5-hdegoede@redhat.com> When the user requests a high enough period ns value, then the calculations in pwm_lpss_prepare() might result in a base_unit value of 0. But according to the data-sheet the way the PWM controller works is that each input clock-cycle the base_unit gets added to a N bit counter and that counter overflowing determines the PWM output frequency. Adding 0 to the counter is a no-op. The data-sheet even explicitly states that writing 0 to the base_unit bits will result in the PWM outputting a continuous 0 signal. When the user requestes a low enough period ns value, then the calculations in pwm_lpss_prepare() might result in a base_unit value which is bigger then base_unit_range - 1. Currently the codes for this deals with this by applying a mask: base_unit &= (base_unit_range - 1); But this means that we let the value overflow the range, we throw away the higher bits and store whatever value is left in the lower bits into the register leading to a random output frequency, rather then clamping the output frequency to the highest frequency which the hardware can do. This commit fixes both issues by clamping the base_unit value to be between 1 and (base_unit_range - 1). Fixes: 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit") Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - Change upper limit of clamp to (base_unit_range - 1) - Add Fixes tag --- drivers/pwm/pwm-lpss.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 43b1fc634af1..80d0f9c64f9d 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -97,6 +97,9 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, freq *= base_unit_range; base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); + /* base_unit must not be 0 and we also want to avoid overflowing it */ + base_unit = clamp_t(unsigned long long, base_unit, 1, + base_unit_range - 1); on_time_div = 255ULL * duty_ns; do_div(on_time_div, period_ns); @@ -105,7 +108,6 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, orig_ctrl = ctrl = pwm_lpss_read(pwm); ctrl &= ~PWM_ON_TIME_DIV_MASK; ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); - base_unit &= (base_unit_range - 1); ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; ctrl |= on_time_div; -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:48 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:48 +0200 Subject: [Intel-gfx] [PATCH v3 05/15] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-6-hdegoede@redhat.com> Before this commit a suspend + resume of the LPSS PWM controller would result in the controller being reset to its defaults of output-freq = clock/256, duty-cycle=100%, until someone changes to the output-freq and/or duty-cycle are made. This problem has been masked so far because the main consumer (the i915 driver) was always making duty-cycle changes on resume. With the conversion of the i915 driver to the atomic PWM API the driver now only disables/enables the PWM on suspend/resume leaving the output-freq and duty as is, triggering this problem. The LPSS PWM controller has a mechanism where the ctrl register value and the actual base-unit and on-time-div values used are latched. When software sets the SW_UPDATE bit then at the end of the current PWM cycle, the new values from the ctrl-register will be latched into the actual registers, and the SW_UPDATE bit will be cleared. The problem is that before this commit our suspend/resume handling consisted of simply saving the PWM ctrl register on suspend and restoring it on resume, without setting the PWM_SW_UPDATE bit. When the controller has lost its state over a suspend/resume and thus has been reset to the defaults, just restoring the register is not enough. We must also set the SW_UPDATE bit to tell the controller to latch the restored values into the actual registers. Fixing this problem is not as simple as just or-ing in the value which is being restored with SW_UPDATE. If the PWM was enabled before we must write the new settings + PWM_SW_UPDATE before setting PWM_ENABLE. We must also wait for PWM_SW_UPDATE to become 0 again and depending on the model we must do this either before or after the setting of PWM_ENABLE. All the necessary logic for doing this is already present inside pwm_lpss_apply(), so instead of duplicating this inside the resume handler, this commit makes the resume handler use pwm_lpss_apply() to restore the settings when necessary. This fixes the output-freq and duty-cycle being reset to their defaults on resume. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - This replaces the "pwm: lpss: Set SW_UPDATE bit when enabling the PWM" patch from previous versions of this patch-set, which really was a hack working around the resume issue which this patch fixes properly. --- drivers/pwm/pwm-lpss.c | 62 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 53 insertions(+), 9 deletions(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 80d0f9c64f9d..4f3d60ce9929 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -123,25 +123,31 @@ static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond) pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); } -static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) +static int __pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state, bool from_resume) { struct pwm_lpss_chip *lpwm = to_lpwm(chip); int ret; if (state->enabled) { if (!pwm_is_enabled(pwm)) { - pm_runtime_get_sync(chip->dev); + if (!from_resume) + pm_runtime_get_sync(chip->dev); + ret = pwm_lpss_is_updating(pwm); if (ret) { - pm_runtime_put(chip->dev); + if (!from_resume) + pm_runtime_put(chip->dev); + return ret; } pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period); pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false); ret = pwm_lpss_wait_for_update(pwm); if (ret) { - pm_runtime_put(chip->dev); + if (!from_resume) + pm_runtime_put(chip->dev); + return ret; } pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true); @@ -154,12 +160,20 @@ static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, } } else if (pwm_is_enabled(pwm)) { pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); - pm_runtime_put(chip->dev); + + if (!from_resume) + pm_runtime_put(chip->dev); } return 0; } +static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + return __pwm_lpss_apply(chip, pwm, state, false); +} + static void pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { @@ -272,10 +286,40 @@ EXPORT_SYMBOL_GPL(pwm_lpss_suspend); int pwm_lpss_resume(struct device *dev) { struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev); - int i; + struct pwm_state saved_state; + struct pwm_device *pwm; + int i, ret; + u32 ctrl; - for (i = 0; i < lpwm->info->npwm; i++) - writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM); + for (i = 0; i < lpwm->info->npwm; i++) { + pwm = &lpwm->chip.pwms[i]; + + ctrl = pwm_lpss_read(pwm); + /* If we did not reach S0i3/S3 the controller keeps its state */ + if (ctrl == lpwm->saved_ctrl[i]) + continue; + + /* + * We cannot just blindly restore the old value here. Since we + * are changing the settings we must set SW_UPDATE and if the + * PWM was enabled before we must write the new settings + + * PWM_SW_UPDATE before setting PWM_ENABLE. We must also wait + * for PWM_SW_UPDATE to become 0 again and depending on the + * model we must do this either before or after the setting of + * PWM_ENABLE. + * So instead of reproducing all the code from pwm_apply() here, + * we just reapply the state as stored in pwm->state. + */ + saved_state = pwm->state; + /* + * Update enabled to its actual setting for the + * enabled<->disabled transitions inside apply(). + */ + pwm->state.enabled = !!(ctrl & PWM_ENABLE); + ret = __pwm_lpss_apply(&lpwm->chip, pwm, &saved_state, true); + if (ret) + dev_err(dev, "Error restoring state on resume\n"); + } return 0; } -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:49 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:49 +0200 Subject: [Intel-gfx] [PATCH v3 06/15] pwm: crc: Fix period / duty_cycle times being off by a factor of 256 In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-7-hdegoede@redhat.com> While looking into adding atomic-pwm support to the pwm-crc driver I noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and there is a clock-divider which divides this with a value between 1-128, and there are 256 duty-cycle steps. The pwm-crc code before this commit assumed that a clock-divider setting of 1 means that the PWM output is running at 6 MHZ, if that is true, where do these 256 duty-cycle steps come from? This would require an internal frequency of 256 * 6 MHz = 1.5 GHz, that seems unlikely for a PMIC which is using a silicon process optimized for power-switching transistors. It is way more likely that there is an 8 bit counter for the duty cycle which acts as an extra fixed divider wrt the PWM output frequency. The main user of the pwm-crc driver is the i915 GPU driver which uses it for backlight control. Lets compare the PWM register values set by the video-BIOS (the GOP), assuming the extra fixed divider is present versus the PWM frequency specified in the Video-BIOS-Tables: Device: PWM Hz set by BIOS PWM Hz specified in VBT Asus T100TA 200 200 Asus T100HA 200 200 Lenovo Miix 2 8 23437 20000 Toshiba WT8-A 23437 20000 So as we can see if we assume the extra division by 256 then the register values set by the GOP are an exact match for the VBT values, where as otherwise the values would be of by a factor of 256. This commit fixes the period / duty_cycle calculations to take the extra division by 256 into account. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - Use NSEC_PER_USEC instead of adding a new (non-sensical) NSEC_PER_MHZ define --- drivers/pwm/pwm-crc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 272eeb071147..c056eb9b858c 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -21,8 +21,8 @@ #define PWM_MAX_LEVEL 0xFF -#define PWM_BASE_CLK 6000000 /* 6 MHz */ -#define PWM_MAX_PERIOD_NS 21333 /* 46.875KHz */ +#define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ +#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ /** * struct crystalcove_pwm - Crystal Cove PWM controller @@ -72,7 +72,7 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, /* changing the clk divisor, need to disable fisrt */ crc_pwm_disable(c, pwm); - clk_div = PWM_BASE_CLK * period_ns / NSEC_PER_SEC; + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:50 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:50 +0200 Subject: [Intel-gfx] [PATCH v3 07/15] pwm: crc: Fix off-by-one error in the clock-divider calculations In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-8-hdegoede@redhat.com> The CRC PWM controller has a clock-divider which divides the clock with a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx defines, this range maps to a register value of 0-127. So after calculating the clock-divider we must subtract 1 to get the register value, unless the requested frequency was so high that the calculation has already resulted in a (rounded) divider value of 0. Note that before this fix, setting a period of PWM_MAX_PERIOD_NS which corresponds to the max. divider value of 128 could have resulted in a bug where the code would use 128 as divider-register value which would have resulted in an actual divider value of 0 (and the enable bit being set). A rounding error stopped this bug from actually happen. This same rounding error means that after the subtraction of 1 it is impossible to set the divider to 128. Also bump PWM_MAX_PERIOD_NS by 1 ns to allow setting a divider of 128 (register-value 127). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set to reduce the amount of churn in the patch-set a bit --- drivers/pwm/pwm-crc.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index c056eb9b858c..44ec7d5b63e1 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -22,7 +22,7 @@ #define PWM_MAX_LEVEL 0xFF #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ -#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ +#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */ /** * struct crystalcove_pwm - Crystal Cove PWM controller @@ -39,6 +39,18 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) return container_of(pc, struct crystalcove_pwm, chip); } +static int crc_pwm_calc_clk_div(int period_ns) +{ + int clk_div; + + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; + + return clk_div; +} + static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); @@ -68,11 +80,10 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, } if (pwm_get_period(pwm) != period_ns) { - int clk_div; + int clk_div = crc_pwm_calc_clk_div(period_ns); /* changing the clk divisor, need to disable fisrt */ crc_pwm_disable(c, pwm); - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:51 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:51 +0200 Subject: [Intel-gfx] [PATCH v3 08/15] pwm: crc: Fix period changes not having any effect In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-9-hdegoede@redhat.com> The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register I strongly suspect that the BACKLIGHT_EN register at address 0x51 really controls a separate output-only GPIO which is connected to the LCD panels backlight-enable input. Like how the PANEL_EN register at address 0x52 controls an output-only GPIO which is earmarked for the LCD panel's enable pin. If this is correct then this GPIO should really be added to the gpio-crystalcove.c driver and the PWM driver should stop poking it. But I've been unable to come up with a definitive answer here, so I'm keeping this as is for now. As the comment in the old code already indicates we must disable the PWM before we can change the clock divider. But the crc_pwm_disable() and crc_pwm_enable() calls the old code make for this only change the BACKLIGHT_EN register; and the value of that register does not matter for changing the period / the divider. What does matter is that the PWM_OUTPUT_ENABLE bit must be cleared before a new value can be written. This commit modifies crc_pwm_config() to clear PWM_OUTPUT_ENABLE instead when changing the period, so that period changes actually work. Note this fix will cause a significant behavior change on some devices using the CRC PWM output to drive their backlight. Before the PWM would always run with the output frequency configured by the BIOS at boot, now the period time specified by the i915 driver will actually be honored. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/pwm/pwm-crc.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 44ec7d5b63e1..81232da0c767 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -82,14 +82,11 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, if (pwm_get_period(pwm) != period_ns) { int clk_div = crc_pwm_calc_clk_div(period_ns); - /* changing the clk divisor, need to disable fisrt */ - crc_pwm_disable(c, pwm); + /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); - - /* enable back */ - crc_pwm_enable(c, pwm); } /* change the pwm duty cycle */ -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:52 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:52 +0200 Subject: [Intel-gfx] [PATCH v3 09/15] pwm: crc: Enable/disable PWM output on enable/disable In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-10-hdegoede@redhat.com> The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, this commit makes crc_pwm_disable() clear it on disable and makes crc_pwm_enable() set it again on re-enable. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - Remove paragraph about tri-stating the output from the commit message, we don't have a datasheet so this was just an unfounded guess --- drivers/pwm/pwm-crc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 81232da0c767..b72008c9b072 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -54,7 +54,9 @@ static int crc_pwm_calc_clk_div(int period_ns) static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div | PWM_OUTPUT_ENABLE); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); return 0; @@ -63,8 +65,10 @@ static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div); } static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:53 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:53 +0200 Subject: [Intel-gfx] [PATCH v3 10/15] pwm: crc: Implement apply() method to support the new atomic PWM API In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-11-hdegoede@redhat.com> Replace the enable, disable and config pwm_ops with an apply op, to support the new atomic PWM API. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - Keep crc_pwm_calc_clk_div() helper to avoid needless churn --- drivers/pwm/pwm-crc.c | 89 ++++++++++++++++++++++++++----------------- 1 file changed, 53 insertions(+), 36 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index b72008c9b072..8a7f4707279c 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -51,59 +51,76 @@ static int crc_pwm_calc_clk_div(int period_ns) return clk_div; } -static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) +static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) { - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); - int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); - - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div | PWM_OUTPUT_ENABLE); - regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); - - return 0; -} - -static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); - int div = crc_pwm_calc_clk_div(pwm_get_period(pwm)); - - regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, div); -} - -static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, - int duty_ns, int period_ns) -{ - struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); struct device *dev = crc_pwm->chip.dev; - int level; + int err; - if (period_ns > PWM_MAX_PERIOD_NS) { + if (state->period > PWM_MAX_PERIOD_NS) { dev_err(dev, "un-supported period_ns\n"); return -EINVAL; } - if (pwm_get_period(pwm) != period_ns) { - int clk_div = crc_pwm_calc_clk_div(period_ns); + if (state->polarity != PWM_POLARITY_NORMAL) + return -EOPNOTSUPP; + + if (pwm_is_enabled(pwm) && !state->enabled) { + err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0); + if (err) { + dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err); + return err; + } + } + + if (pwm_get_duty_cycle(pwm) != state->duty_cycle || + pwm_get_period(pwm) != state->period) { + int level = state->duty_cycle * PWM_MAX_LEVEL / state->period; + err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level); + if (err) { + dev_err(dev, "Error writing PWM0_DUTY_CYCLE %d\n", err); + return err; + } + } + + if (pwm_is_enabled(pwm) && state->enabled && + pwm_get_period(pwm) != state->period) { /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); + err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); + if (err) { + dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err); + return err; + } + } - regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, - clk_div | PWM_OUTPUT_ENABLE); + if (pwm_get_period(pwm) != state->period || + pwm_is_enabled(pwm) != state->enabled) { + int clk_div = crc_pwm_calc_clk_div(state->period); + int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0; + + err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, + clk_div | pwm_output_enable); + if (err) { + dev_err(dev, "Error writing PWM0_CLK_DIV %d\n", err); + return err; + } } - /* change the pwm duty cycle */ - level = duty_ns * PWM_MAX_LEVEL / period_ns; - regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level); + if (!pwm_is_enabled(pwm) && state->enabled) { + err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1); + if (err) { + dev_err(dev, "Error writing BACKLIGHT_EN %d\n", err); + return err; + } + } return 0; } static const struct pwm_ops crc_pwm_ops = { - .config = crc_pwm_config, - .enable = crc_pwm_enable, - .disable = crc_pwm_disable, + .apply = crc_pwm_apply, }; static int crystalcove_pwm_probe(struct platform_device *pdev) -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:54 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:54 +0200 Subject: [Intel-gfx] [PATCH v3 11/15] pwm: crc: Implement get_state() method In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-12-hdegoede@redhat.com> Implement the pwm_ops.get_state() method to complete the support for the new atomic PWM API. Reviewed-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com> Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- Changes in v3: - Add Andy's Reviewed-by tag - Remove extra whitespace to align some code after assignments (requested by Uwe Kleine-K?nig) --- drivers/pwm/pwm-crc.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 8a7f4707279c..b311354d40a3 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -119,8 +119,37 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return 0; } +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); + struct device *dev = crc_pwm->chip.dev; + unsigned int clk_div, clk_div_reg, duty_cycle_reg; + int error; + + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); + if (error) { + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); + return; + } + + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); + if (error) { + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); + return; + } + + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; + + state->period = clk_div * NSEC_PER_USEC * 256 / PWM_BASE_CLK_MHZ; + state->duty_cycle = duty_cycle_reg * state->period / PWM_MAX_LEVEL; + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); +} + static const struct pwm_ops crc_pwm_ops = { .apply = crc_pwm_apply, + .get_state = crc_pwm_get_state, }; static int crystalcove_pwm_probe(struct platform_device *pdev) -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:56 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:56 +0200 Subject: [Intel-gfx] [PATCH v3 13/15] drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-14-hdegoede@redhat.com> So far for devices using an external PWM controller (devices using pwm_setup_backlight()), we have been hardcoding the period-time passed to pwm_config() to 21333 ns. I suspect this was done because many VBTs set the PWM frequency to 200 which corresponds to a period-time of 5000000 ns, which greatly exceeds the PWM_MAX_PERIOD_NS define in the Crystal Cove PMIC PWM driver, which used to be 21333. This PWM_MAX_PERIOD_NS define was actually based on a bug in the PWM driver where its period and duty-cycle times where off by a factor of 256. Due to this bug the hardcoded CRC_PMIC_PWM_PERIOD_NS value of 21333 would result in the PWM driver using its divider of 128, which would result in a PWM output frequency of 6000000 Hz / 256 / 128 = 183 Hz. So actually pretty close to the default VBT value of 200 Hz. Now that this bug in the pwm-crc driver is fixed, we can actually use the VBT defined frequency. This is important because: a) With the pwm-crc driver fixed it will now translate the hardcoded CRC_PMIC_PWM_PERIOD_NS value of 21333 ns / 46 Khz to a PWM output frequency of 23 KHz (the max it can do). b) The pwm-lpss driver used on many models has always honored the 21333 ns / 46 Khz request Some panels do not like such high output frequencies. E.g. on a Terra Pad 1061 tablet, using the LPSS PWM controller, the backlight would go from off to max, when changing the sysfs backlight brightness value from 90-100%, anything under aprox. 90% would turn the backlight fully off. Honoring the VBT specified PWM frequency will also hopefully fix the various bug reports which we have received about users perceiving the backlight to flicker after a suspend/resume cycle. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_panel.c | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bf3d4cb4ea9..de32f9efb120 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -223,6 +223,7 @@ struct intel_panel { bool util_pin_active_low; /* bxt+ */ u8 controller; /* bxt+ only */ struct pwm_device *pwm; + int pwm_period_ns; /* DPCD backlight */ u8 pwmgen_bit_count; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 8efdd9f08a08..14e611c92194 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -40,8 +40,6 @@ #include "intel_dsi_dcs_backlight.h" #include "intel_panel.h" -#define CRC_PMIC_PWM_PERIOD_NS 21333 - void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, struct drm_display_mode *adjusted_mode) @@ -597,7 +595,7 @@ static u32 pwm_get_backlight(struct intel_connector *connector) int duty_ns; duty_ns = pwm_get_duty_cycle(panel->backlight.pwm); - return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS); + return DIV_ROUND_UP(duty_ns * 100, panel->backlight.pwm_period_ns); } static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -671,9 +669,10 @@ static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; - int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); + int duty_ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - pwm_config(panel->backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS); + pwm_config(panel->backlight.pwm, duty_ns, + panel->backlight.pwm_period_ns); } static void @@ -1917,6 +1916,9 @@ static int pwm_setup_backlight(struct intel_connector *connector, return -ENODEV; } + panel->backlight.pwm_period_ns = NSEC_PER_SEC / + get_vbt_pwm_freq(dev_priv); + /* * FIXME: pwm_apply_args() should be removed when switching to * the atomic PWM API. @@ -1926,9 +1928,10 @@ static int pwm_setup_backlight(struct intel_connector *connector, panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ level = intel_panel_compute_brightness(connector, 100); - ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); + ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - retval = pwm_config(panel->backlight.pwm, ns, CRC_PMIC_PWM_PERIOD_NS); + retval = pwm_config(panel->backlight.pwm, ns, + panel->backlight.pwm_period_ns); if (retval < 0) { drm_err(&dev_priv->drm, "Failed to configure the pwm chip\n"); pwm_put(panel->backlight.pwm); @@ -1937,7 +1940,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, } level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, - CRC_PMIC_PWM_PERIOD_NS); + panel->backlight.pwm_period_ns); panel->backlight.level = intel_panel_compute_brightness(connector, level); panel->backlight.enabled = panel->backlight.level != 0; -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:55 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:55 +0200 Subject: [Intel-gfx] [PATCH v3 12/15] drm/i915: panel: Add get_vbt_pwm_freq() helper In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-13-hdegoede@redhat.com> Factor the code which checks and drm_dbg_kms-s the VBT PWM frequency out of get_backlight_max_vbt(). This is a preparation patch for honering the VBT PWM frequency for devices which use an external PWM controller (devices using pwm_setup_backlight()). Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/gpu/drm/i915/display/intel_panel.c | 27 ++++++++++++++-------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 3c5056dbf607..8efdd9f08a08 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1543,18 +1543,9 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul); } -static u32 get_backlight_max_vbt(struct intel_connector *connector) +static u16 get_vbt_pwm_freq(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_panel *panel = &connector->panel; u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz; - u32 pwm; - - if (!panel->backlight.hz_to_pwm) { - drm_dbg_kms(&dev_priv->drm, - "backlight frequency conversion not supported\n"); - return 0; - } if (pwm_freq_hz) { drm_dbg_kms(&dev_priv->drm, @@ -1567,6 +1558,22 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector) pwm_freq_hz); } + return pwm_freq_hz; +} + +static u32 get_backlight_max_vbt(struct intel_connector *connector) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + u16 pwm_freq_hz = get_vbt_pwm_freq(dev_priv); + u32 pwm; + + if (!panel->backlight.hz_to_pwm) { + drm_dbg_kms(&dev_priv->drm, + "backlight frequency conversion not supported\n"); + return 0; + } + pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz); if (!pwm) { drm_dbg_kms(&dev_priv->drm, -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:57 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:57 +0200 Subject: [Intel-gfx] [PATCH v3 14/15] drm/i915: panel: Honor the VBT PWM min setting for devs with an external PWM controller In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-15-hdegoede@redhat.com> So far for devices using an external PWM controller (devices using pwm_setup_backlight()), we have been hardcoding the minimum allowed PWM level to 0. But several of these devices specify a non 0 minimum setting in their VBT. Change pwm_setup_backlight() to use get_backlight_min_vbt() to get the minimum level. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- drivers/gpu/drm/i915/display/intel_panel.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 14e611c92194..cb28b9908ca4 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -1925,8 +1925,8 @@ static int pwm_setup_backlight(struct intel_connector *connector, */ pwm_apply_args(panel->backlight.pwm); - panel->backlight.min = 0; /* 0% */ panel->backlight.max = 100; /* 100% */ + panel->backlight.min = get_backlight_min_vbt(connector); level = intel_panel_compute_brightness(connector, 100); ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); @@ -1941,8 +1941,9 @@ static int pwm_setup_backlight(struct intel_connector *connector, level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, panel->backlight.pwm_period_ns); - panel->backlight.level = - intel_panel_compute_brightness(connector, level); + level = intel_panel_compute_brightness(connector, level); + panel->backlight.level = clamp(level, panel->backlight.min, + panel->backlight.max); panel->backlight.enabled = panel->backlight.level != 0; drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n", -- 2.26.2 From hdegoede at redhat.com Sat Jun 20 12:17:58 2020 From: hdegoede at redhat.com (Hans de Goede) Date: Sat, 20 Jun 2020 14:17:58 +0200 Subject: [Intel-gfx] [PATCH v3 15/15] drm/i915: panel: Use atomic PWM API for devs with an external PWM controller In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <20200620121758.14836-16-hdegoede@redhat.com> Now that the PWM drivers which we use have been converted to the atomic PWM API, we can move the i915 panel code over to using the atomic PWM API. The removes a long standing FIXME and this removes a flicker where the backlight brightness would jump to 100% when i915 loads even if using the fastset path. Signed-off-by: Hans de Goede <hdegoede at redhat.com> --- .../drm/i915/display/intel_display_types.h | 3 +- drivers/gpu/drm/i915/display/intel_panel.c | 73 +++++++++---------- 2 files changed, 37 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index de32f9efb120..4bd9981e70a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -28,6 +28,7 @@ #include <linux/async.h> #include <linux/i2c.h> +#include <linux/pwm.h> #include <linux/sched/clock.h> #include <drm/drm_atomic.h> @@ -223,7 +224,7 @@ struct intel_panel { bool util_pin_active_low; /* bxt+ */ u8 controller; /* bxt+ only */ struct pwm_device *pwm; - int pwm_period_ns; + struct pwm_state pwm_state; /* DPCD backlight */ u8 pwmgen_bit_count; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index cb28b9908ca4..a0f76343f381 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -592,10 +592,11 @@ static u32 bxt_get_backlight(struct intel_connector *connector) static u32 pwm_get_backlight(struct intel_connector *connector) { struct intel_panel *panel = &connector->panel; - int duty_ns; + int duty_ns, period_ns; duty_ns = pwm_get_duty_cycle(panel->backlight.pwm); - return DIV_ROUND_UP(duty_ns * 100, panel->backlight.pwm_period_ns); + period_ns = pwm_get_period(panel->backlight.pwm); + return DIV_ROUND_UP(duty_ns * 100, period_ns); } static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -669,10 +670,10 @@ static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; - int duty_ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - pwm_config(panel->backlight.pwm, duty_ns, - panel->backlight.pwm_period_ns); + panel->backlight.pwm_state.duty_cycle = + DIV_ROUND_UP(level * panel->backlight.pwm_state.period, 100); + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } static void @@ -841,10 +842,8 @@ static void pwm_disable_backlight(const struct drm_connector_state *old_conn_sta struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct intel_panel *panel = &connector->panel; - /* Disable the backlight */ - intel_panel_actually_set_backlight(old_conn_state, 0); - usleep_range(2000, 3000); - pwm_disable(panel->backlight.pwm); + panel->backlight.pwm_state.enabled = false; + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -1176,9 +1175,14 @@ static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state, { struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_panel *panel = &connector->panel; + int level = panel->backlight.level; - pwm_enable(panel->backlight.pwm); - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + level = intel_panel_compute_brightness(connector, level); + + panel->backlight.pwm_state.duty_cycle = + DIV_ROUND_UP(level * panel->backlight.pwm_state.period, 100); + panel->backlight.pwm_state.enabled = true; + pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); } static void __intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -1897,8 +1901,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_panel *panel = &connector->panel; const char *desc; - u32 level, ns; - int retval; + u32 level; /* Get the right PWM chip for DSI backlight according to VBT */ if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { @@ -1916,36 +1919,30 @@ static int pwm_setup_backlight(struct intel_connector *connector, return -ENODEV; } - panel->backlight.pwm_period_ns = NSEC_PER_SEC / - get_vbt_pwm_freq(dev_priv); - - /* - * FIXME: pwm_apply_args() should be removed when switching to - * the atomic PWM API. - */ - pwm_apply_args(panel->backlight.pwm); - panel->backlight.max = 100; /* 100% */ panel->backlight.min = get_backlight_min_vbt(connector); - level = intel_panel_compute_brightness(connector, 100); - ns = DIV_ROUND_UP(level * panel->backlight.pwm_period_ns, 100); - retval = pwm_config(panel->backlight.pwm, ns, - panel->backlight.pwm_period_ns); - if (retval < 0) { - drm_err(&dev_priv->drm, "Failed to configure the pwm chip\n"); - pwm_put(panel->backlight.pwm); - panel->backlight.pwm = NULL; - return retval; + if (pwm_is_enabled(panel->backlight.pwm) && + pwm_get_period(panel->backlight.pwm)) { + /* PWM is already enabled, use existing settings */ + pwm_get_state(panel->backlight.pwm, &panel->backlight.pwm_state); + + level = DIV_ROUND_UP(panel->backlight.pwm_state.duty_cycle * + 100, panel->backlight.pwm_state.period); + level = intel_panel_compute_brightness(connector, level); + panel->backlight.level = clamp(level, panel->backlight.min, + panel->backlight.max); + panel->backlight.enabled = true; + + drm_dbg_kms(&dev_priv->drm, "PWM already enabled at freq %ld, VBT freq %d, level %d\n", + NSEC_PER_SEC / panel->backlight.pwm_state.period, + get_vbt_pwm_freq(dev_priv), level); + } else { + /* Set period from VBT frequency, leave other setting at 0. */ + panel->backlight.pwm_state.period = + NSEC_PER_SEC / get_vbt_pwm_freq(dev_priv); } - level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, - panel->backlight.pwm_period_ns); - level = intel_panel_compute_brightness(connector, level); - panel->backlight.level = clamp(level, panel->backlight.min, - panel->backlight.max); - panel->backlight.enabled = panel->backlight.level != 0; - drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n", desc); return 0; -- 2.26.2 From patchwork at emeril.freedesktop.org Sat Jun 20 12:41:47 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 20 Jun 2020 12:41:47 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_acpi/pwm/i915=3A_Convert_pwm-crc_and_i915_driver=27s_PWM_co?= =?utf-8?q?de_to_use_the_atomic_PWM_API?= In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <159265690725.5569.2518282758646834525@emeril.freedesktop.org> == Series Details == Series: acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API URL : https://patchwork.freedesktop.org/series/78657/ State : warning == Summary == $ dim checkpatch origin/drm-tip 00c7ab81dc2b ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase 70aa4c26421d ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) 2b3dc82c833f pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() 331619bd8d2d pwm: lpss: Add range limit check for the base_unit register value 8ca68e33dcee pwm: lpss: Use pwm_lpss_apply() when restoring state on resume eb1f77282a44 pwm: crc: Fix period / duty_cycle times being off by a factor of 256 5c49b15649d0 pwm: crc: Fix off-by-one error in the clock-divider calculations fd2e1f63fa16 pwm: crc: Fix period changes not having any effect 7f858f2631cc pwm: crc: Enable/disable PWM output on enable/disable 257686c338a9 pwm: crc: Implement apply() method to support the new atomic PWM API 7c35513a98ae pwm: crc: Implement get_state() method -:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #21: FILE: drivers/pwm/pwm-crc.c:123: +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) total: 0 errors, 0 warnings, 1 checks, 37 lines checked 09a8c4429a2c drm/i915: panel: Add get_vbt_pwm_freq() helper 2844a5b2bc7d drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller c9ae779cf5df drm/i915: panel: Honor the VBT PWM min setting for devs with an external PWM controller b38271ed1f65 drm/i915: panel: Use atomic PWM API for devs with an external PWM controller From patchwork at emeril.freedesktop.org Sat Jun 20 13:04:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 20 Jun 2020 13:04:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgYWNw?= =?utf-8?q?i/pwm/i915=3A_Convert_pwm-crc_and_i915_driver=27s_PWM_code_to_u?= =?utf-8?q?se_the_atomic_PWM_API?= In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <159265826242.5570.3512092262423559890@emeril.freedesktop.org> == Series Details == Series: acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API URL : https://patchwork.freedesktop.org/series/78657/ State : success == Summary == CI Bug Log - changes from CI_DRM_8649 -> Patchwork_18000 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/index.html Known issues ------------ Here are the changes found in Patchwork_18000 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-tgl-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-tgl-u2/igt at i915_module_load@reload.html - fi-byt-n2820: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-byt-n2820/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [PASS][11] -> [INCOMPLETE][12] ([i915#1932]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-n2820: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html - {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-kbl-guc: [FAIL][19] ([i915#579]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-kbl-x1275/igt at kms_busy@basic at flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-guc: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-icl-guc/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92]) -> [DMESG-WARN][32] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8649 -> Patchwork_18000 CI-20190529: 20190529 CI_DRM_8649: 08819db597ecdc426544d0fdd5dc352616eaba76 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18000: b38271ed1f65021eccb0c8df4114f6c16b071bbb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b38271ed1f65 drm/i915: panel: Use atomic PWM API for devs with an external PWM controller c9ae779cf5df drm/i915: panel: Honor the VBT PWM min setting for devs with an external PWM controller 2844a5b2bc7d drm/i915: panel: Honor the VBT PWM frequency for devs with an external PWM controller 09a8c4429a2c drm/i915: panel: Add get_vbt_pwm_freq() helper 7c35513a98ae pwm: crc: Implement get_state() method 257686c338a9 pwm: crc: Implement apply() method to support the new atomic PWM API 7f858f2631cc pwm: crc: Enable/disable PWM output on enable/disable fd2e1f63fa16 pwm: crc: Fix period changes not having any effect 5c49b15649d0 pwm: crc: Fix off-by-one error in the clock-divider calculations eb1f77282a44 pwm: crc: Fix period / duty_cycle times being off by a factor of 256 8ca68e33dcee pwm: lpss: Use pwm_lpss_apply() when restoring state on resume 331619bd8d2d pwm: lpss: Add range limit check for the base_unit register value 2b3dc82c833f pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() 70aa4c26421d ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) 00c7ab81dc2b ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/index.html From patchwork at emeril.freedesktop.org Sat Jun 20 14:10:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 20 Jun 2020 14:10:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgYWNw?= =?utf-8?q?i/pwm/i915=3A_Convert_pwm-crc_and_i915_driver=27s_PWM_code_to_u?= =?utf-8?q?se_the_atomic_PWM_API?= In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <159266222019.5568.13599614810608477931@emeril.freedesktop.org> == Series Details == Series: acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API URL : https://patchwork.freedesktop.org/series/78657/ State : success == Summary == CI Bug Log - changes from CI_DRM_8649_full -> Patchwork_18000_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18000_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#1930]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-glk6/igt at gem_exec_reloc@basic-concurrent0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_schedule@implicit-boths at bcs0: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-snb6/igt at gem_exec_schedule@implicit-boths at bcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-snb6/igt at gem_exec_schedule@implicit-boths at bcs0.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-skl10/igt at gen9_exec_parse@allowed-single.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-skl8/igt at gen9_exec_parse@allowed-single.html * igt at i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#95]) +22 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-apl6/igt at i915_suspend@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-apl6/igt at i915_suspend@fence-restore-tiled2untiled.html * igt at kms_big_fb@y-tiled-32bpp-rotate-180: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-skl6/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-skl10/igt at kms_big_fb@y-tiled-32bpp-rotate-180.html * igt at kms_color@pipe-a-ctm-red-to-blue: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-kbl3/igt at kms_color@pipe-a-ctm-red-to-blue.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-kbl6/igt at kms_color@pipe-a-ctm-red-to-blue.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-kbl4/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][19] -> [DMESG-FAIL][20] ([fdo#108145] / [i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-iclb1/igt at kms_psr@psr2_cursor_blt.html * igt at kms_setmode@basic: - shard-kbl: [PASS][23] -> [FAIL][24] ([i915#31]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-kbl6/igt at kms_setmode@basic.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-kbl4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-b-accuracy-idle: - shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-glk7/igt at kms_vblank@pipe-b-accuracy-idle.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-glk7/igt at kms_vblank@pipe-b-accuracy-idle.html - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-kbl6/igt at kms_vblank@pipe-b-accuracy-idle.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-kbl4/igt at kms_vblank@pipe-b-accuracy-idle.html * igt at perf@blocking-parameterized: - shard-tglb: [PASS][29] -> [FAIL][30] ([i915#1542]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-tglb7/igt at perf@blocking-parameterized.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-tglb8/igt at perf@blocking-parameterized.html * igt at perf@polling-parameterized: - shard-iclb: [PASS][31] -> [FAIL][32] ([i915#1542]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-iclb4/igt at perf@polling-parameterized.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-iclb7/igt at perf@polling-parameterized.html #### Possible fixes #### * igt at gem_blits@basic: - shard-tglb: [DMESG-WARN][33] ([i915#402]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-tglb6/igt at gem_blits@basic.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-tglb1/igt at gem_blits@basic.html * igt at gem_exec_suspend@basic: - shard-apl: [DMESG-WARN][35] ([i915#95]) -> [PASS][36] +19 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-apl4/igt at gem_exec_suspend@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-apl3/igt at gem_exec_suspend@basic.html * igt at gem_exec_suspend@basic-s3: - shard-skl: [INCOMPLETE][37] ([i915#69]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-skl1/igt at gem_exec_suspend@basic-s3.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-skl1/igt at gem_exec_suspend@basic-s3.html * igt at gem_mmap_gtt@cpuset-big-copy-odd: - shard-iclb: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-iclb2/igt at gem_mmap_gtt@cpuset-big-copy-odd.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-iclb5/igt at gem_mmap_gtt@cpuset-big-copy-odd.html - shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +4 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-skl1/igt at gem_mmap_gtt@cpuset-big-copy-odd.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-skl3/igt at gem_mmap_gtt@cpuset-big-copy-odd.html * igt at gem_softpin@noreloc-s3: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-kbl2/igt at gem_softpin@noreloc-s3.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-kbl7/igt at gem_softpin@noreloc-s3.html * igt at gen9_exec_parse@allowed-all: - shard-kbl: [DMESG-WARN][45] ([i915#1436] / [i915#716]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-kbl3/igt at gen9_exec_parse@allowed-all.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-kbl1/igt at gen9_exec_parse@allowed-all.html * igt at kms_cursor_legacy@cursorb-vs-flipa-legacy: - shard-hsw: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-hsw8/igt at kms_cursor_legacy@cursorb-vs-flipa-legacy.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-hsw8/igt at kms_cursor_legacy@cursorb-vs-flipa-legacy.html * igt at kms_flip@flip-vs-expired-vblank at c-hdmi-a2: - shard-glk: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-glk8/igt at kms_flip@flip-vs-expired-vblank at c-hdmi-a2.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-glk8/igt at kms_flip@flip-vs-expired-vblank at c-hdmi-a2.html * igt at kms_frontbuffer_tracking@psr-indfb-scaledprimary: - shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-tglb7/igt at kms_frontbuffer_tracking@psr-indfb-scaledprimary.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-tglb7/igt at kms_frontbuffer_tracking@psr-indfb-scaledprimary.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_cursor_render: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-iclb6/igt at kms_psr@psr2_cursor_render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-iclb2/igt at kms_psr@psr2_cursor_render.html * igt at kms_vblank@pipe-b-accuracy-idle: - shard-apl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-apl2/igt at kms_vblank@pipe-b-accuracy-idle.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-apl3/igt at kms_vblank@pipe-b-accuracy-idle.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][59] ([i915#1542]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-iclb3/igt at perf@blocking-parameterized.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-iclb2/igt at perf@blocking-parameterized.html * igt at perf@short-reads: - shard-hsw: [FAIL][61] -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-hsw1/igt at perf@short-reads.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-hsw1/igt at perf@short-reads.html * igt at sysfs_preempt_timeout@idempotent at vecs0: - shard-kbl: [DMESG-WARN][63] ([i915#93] / [i915#95]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-kbl1/igt at sysfs_preempt_timeout@idempotent at vecs0.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-kbl2/igt at sysfs_preempt_timeout@idempotent at vecs0.html #### Warnings #### * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#454]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-tglb1/igt at i915_pm_dc@dc6-dpms.html * igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding: - shard-apl: [DMESG-WARN][67] ([i915#95]) -> [DMESG-FAIL][68] ([i915#54] / [i915#95]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8649/shard-apl4/igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/shard-apl4/igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8649 -> Patchwork_18000 CI-20190529: 20190529 CI_DRM_8649: 08819db597ecdc426544d0fdd5dc352616eaba76 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18000: b38271ed1f65021eccb0c8df4114f6c16b071bbb @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18000/index.html From daniel.vetter at ffwll.ch Sun Jun 21 17:28:40 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Sun, 21 Jun 2020 19:28:40 +0200 Subject: [Intel-gfx] [PATCH 01/18] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200621170054.GA1398@lca.pw> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200621170054.GA1398@lca.pw> Message-ID: <CAKMK7uGbf=OAWWtZMwoaioDKHA_DUyVNiJU4ORbijzUcn+u+Mw@mail.gmail.com> On Sun, Jun 21, 2020 at 7:01 PM Qian Cai <cai at lca.pw> wrote: > > On Thu, Jun 04, 2020 at 10:12:07AM +0200, Daniel Vetter wrote: > > fs_reclaim_acquire/release nicely catch recursion issues when > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > to use to keep the excessive caches in check). For mmu notifier > > recursions we do have lockdep annotations since 23b68395c7c7 > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > But these only fire if a path actually results in some pte > > invalidation - for most small allocations that's very rarely the case. > > The other trouble is that pte invalidation can happen any time when > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > recursion. > > > > I was pondering whether we should just do the general annotation, but > > there's always the risk for false positives. Plus I'm assuming that > > the core fs and io code is a lot better reviewed and tested than > > random mmu notifier code in drivers. Hence why I decide to only > > annotate for that specific case. > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > still need to explicit pull in the mmu notifier map - there's a lot > > more places that do pte invalidation than just direct reclaim, these > > two contexts arent the same. > > > > Note that the mmu notifiers needing their own independent lockdep map > > is also the reason we can't hold them from fs_reclaim_acquire to > > fs_reclaim_release - it would nest with the acquistion in the pte > > invalidation code, causing a lockdep splat. And we can't remove the > > annotations from pte invalidation and all the other places since > > they're called from many other places than page reclaim. Hence we can > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > strictly more powerful. > > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > Cc: linux-mm at kvack.org > > Cc: linux-rdma at vger.kernel.org > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Reverting this commit fixed the lockdep splat below while applying some > memory pressure, This is a broken version of the patch, please use the one Andrew merged into -mm. Thanks, Daniel > > [ 190.455003][ T369] WARNING: possible circular locking dependency detected > [ 190.487291][ T369] 5.8.0-rc1-next-20200621 #1 Not tainted > [ 190.512363][ T369] ------------------------------------------------------ > [ 190.543354][ T369] kswapd3/369 is trying to acquire lock: > [ 190.568523][ T369] ffff889fcf694528 (&xfs_nondir_ilock_class){++++}-{3:3}, at: xfs_reclaim_inode+0xdf/0x860 > spin_lock at include/linux/spinlock.h:353 > (inlined by) xfs_iflags_test_and_set at fs/xfs/xfs_inode.h:166 > (inlined by) xfs_iflock_nowait at fs/xfs/xfs_inode.h:249 > (inlined by) xfs_reclaim_inode at fs/xfs/xfs_icache.c:1127 > [ 190.614359][ T369] > [ 190.614359][ T369] but task is already holding lock: > [ 190.647763][ T369] ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > __fs_reclaim_acquire at mm/page_alloc.c:4200 > [ 190.687845][ T369] > [ 190.687845][ T369] which lock already depends on the new lock. > [ 190.687845][ T369] > [ 190.734890][ T369] > [ 190.734890][ T369] the existing dependency chain (in reverse order) is: > [ 190.775991][ T369] > [ 190.775991][ T369] -> #1 (fs_reclaim){+.+.}-{0:0}: > [ 190.808150][ T369] fs_reclaim_acquire+0x77/0x80 > [ 190.832152][ T369] slab_pre_alloc_hook.constprop.52+0x20/0x120 > slab_pre_alloc_hook at mm/slab.h:507 > [ 190.862173][ T369] kmem_cache_alloc+0x43/0x2a0 > [ 190.885602][ T369] kmem_zone_alloc+0x113/0x3ef > kmem_zone_alloc at fs/xfs/kmem.c:129 > [ 190.908702][ T369] xfs_inode_item_init+0x1d/0xa0 > xfs_inode_item_init at fs/xfs/xfs_inode_item.c:639 > [ 190.934461][ T369] xfs_trans_ijoin+0x96/0x100 > xfs_trans_ijoin at fs/xfs/libxfs/xfs_trans_inode.c:34 > [ 190.961530][ T369] xfs_setattr_nonsize+0x1a6/0xcd0 > xfs_setattr_nonsize at fs/xfs/xfs_iops.c:716 > [ 190.987331][ T369] xfs_vn_setattr+0x133/0x160 > xfs_vn_setattr at fs/xfs/xfs_iops.c:1081 > [ 191.010476][ T369] notify_change+0x6c5/0xba1 > notify_change at fs/attr.c:336 > [ 191.033317][ T369] chmod_common+0x19b/0x390 > [ 191.055770][ T369] ksys_fchmod+0x28/0x60 > [ 191.077957][ T369] __x64_sys_fchmod+0x4e/0x70 > [ 191.102767][ T369] do_syscall_64+0x5f/0x310 > [ 191.125090][ T369] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > [ 191.153749][ T369] > [ 191.153749][ T369] -> #0 (&xfs_nondir_ilock_class){++++}-{3:3}: > [ 191.191267][ T369] __lock_acquire+0x2efc/0x4da0 > [ 191.215974][ T369] lock_acquire+0x1ac/0xaf0 > [ 191.238953][ T369] down_write_nested+0x92/0x150 > [ 191.262955][ T369] xfs_reclaim_inode+0xdf/0x860 > [ 191.287149][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 > [ 191.313291][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 > [ 191.338357][ T369] super_cache_scan+0x2fd/0x430 > [ 191.362354][ T369] do_shrink_slab+0x317/0x990 > [ 191.385341][ T369] shrink_slab+0x3a8/0x4b0 > [ 191.407214][ T369] shrink_node+0x49c/0x17b0 > [ 191.429841][ T369] balance_pgdat+0x59c/0xed0 > [ 191.455041][ T369] kswapd+0x5a4/0xc40 > [ 191.477524][ T369] kthread+0x358/0x420 > [ 191.499285][ T369] ret_from_fork+0x22/0x30 > [ 191.521107][ T369] > [ 191.521107][ T369] other info that might help us debug this: > [ 191.521107][ T369] > [ 191.567490][ T369] Possible unsafe locking scenario: > [ 191.567490][ T369] > [ 191.600947][ T369] CPU0 CPU1 > [ 191.624808][ T369] ---- ---- > [ 191.649236][ T369] lock(fs_reclaim); > [ 191.667607][ T369] lock(&xfs_nondir_ilock_class); > [ 191.702096][ T369] lock(fs_reclaim); > [ 191.731243][ T369] lock(&xfs_nondir_ilock_class); > [ 191.754025][ T369] > [ 191.754025][ T369] *** DEADLOCK *** > [ 191.754025][ T369] > [ 191.791126][ T369] 4 locks held by kswapd3/369: > [ 191.812198][ T369] #0: ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > [ 191.854319][ T369] #1: ffffffffb5074c50 (shrinker_rwsem){++++}-{3:3}, at: shrink_slab+0x219/0x4b0 > [ 191.896043][ T369] #2: ffff8890279b40e0 (&type->s_umount_key#27){++++}-{3:3}, at: trylock_super+0x11/0xb0 > [ 191.940538][ T369] #3: ffff889027a73a28 (&pag->pag_ici_reclaim_lock){+.+.}-{3:3}, at: xfs_reclaim_inodes_ag+0x135/0xb00 > [ 191.995314][ T369] > [ 191.995314][ T369] stack backtrace: > [ 192.022934][ T369] CPU: 42 PID: 369 Comm: kswapd3 Not tainted 5.8.0-rc1-next-20200621 #1 > [ 192.060546][ T369] Hardware name: HP ProLiant BL660c Gen9, BIOS I38 10/17/2018 > [ 192.094518][ T369] Call Trace: > [ 192.109005][ T369] dump_stack+0x9d/0xe0 > [ 192.127468][ T369] check_noncircular+0x347/0x400 > [ 192.149526][ T369] ? print_circular_bug+0x360/0x360 > [ 192.172584][ T369] ? freezing_slow_path.cold.2+0x2a/0x2a > [ 192.197251][ T369] __lock_acquire+0x2efc/0x4da0 > [ 192.218737][ T369] ? lockdep_hardirqs_on_prepare+0x550/0x550 > [ 192.246736][ T369] ? __lock_acquire+0x3541/0x4da0 > [ 192.269673][ T369] lock_acquire+0x1ac/0xaf0 > [ 192.290192][ T369] ? xfs_reclaim_inode+0xdf/0x860 > [ 192.313158][ T369] ? rcu_read_unlock+0x50/0x50 > [ 192.335057][ T369] down_write_nested+0x92/0x150 > [ 192.358409][ T369] ? xfs_reclaim_inode+0xdf/0x860 > [ 192.380890][ T369] ? rwsem_down_write_slowpath+0xf50/0xf50 > [ 192.406891][ T369] ? find_held_lock+0x33/0x1c0 > [ 192.427925][ T369] ? xfs_ilock+0x2ef/0x370 > [ 192.447496][ T369] ? xfs_reclaim_inode+0xdf/0x860 > [ 192.472315][ T369] xfs_reclaim_inode+0xdf/0x860 > [ 192.496649][ T369] ? xfs_inode_clear_reclaim_tag+0xa0/0xa0 > [ 192.524188][ T369] ? do_raw_spin_unlock+0x4f/0x250 > [ 192.546852][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 > [ 192.570473][ T369] ? xfs_reclaim_inode+0x860/0x860 > [ 192.592692][ T369] ? mark_held_locks+0xb0/0x110 > [ 192.614287][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 > [ 192.640800][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 > [ 192.666695][ T369] ? try_to_wake_up+0xcf/0xf40 > [ 192.688265][ T369] ? migrate_swap_stop+0xc10/0xc10 > [ 192.711966][ T369] ? do_raw_spin_unlock+0x4f/0x250 > [ 192.735032][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 > xfs_reclaim_inodes_nr at fs/xfs/xfs_icache.c:1399 > [ 192.757674][ T369] ? xfs_reclaim_inodes+0x90/0x90 > [ 192.780028][ T369] ? list_lru_count_one+0x177/0x300 > [ 192.803010][ T369] super_cache_scan+0x2fd/0x430 > super_cache_scan at fs/super.c:115 > [ 192.824491][ T369] do_shrink_slab+0x317/0x990 > do_shrink_slab at mm/vmscan.c:514 > [ 192.845160][ T369] shrink_slab+0x3a8/0x4b0 > shrink_slab_memcg at mm/vmscan.c:584 > (inlined by) shrink_slab at mm/vmscan.c:662 > [ 192.864722][ T369] ? do_shrink_slab+0x990/0x990 > [ 192.886137][ T369] ? rcu_is_watching+0x2c/0x80 > [ 192.907289][ T369] ? mem_cgroup_protected+0x228/0x470 > [ 192.931166][ T369] ? vmpressure+0x25/0x290 > [ 192.950595][ T369] shrink_node+0x49c/0x17b0 > [ 192.972332][ T369] balance_pgdat+0x59c/0xed0 > kswapd_shrink_node at mm/vmscan.c:3521 > (inlined by) balance_pgdat at mm/vmscan.c:3670 > [ 192.994918][ T369] ? __node_reclaim+0x950/0x950 > [ 193.018625][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 > [ 193.046566][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 > [ 193.070214][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 > [ 193.093176][ T369] ? finish_task_switch+0x129/0x650 > [ 193.116225][ T369] ? finish_task_switch+0xf2/0x650 > [ 193.138809][ T369] ? rcu_read_lock_bh_held+0xc0/0xc0 > [ 193.163323][ T369] kswapd+0x5a4/0xc40 > [ 193.182690][ T369] ? __kthread_parkme+0x4d/0x1a0 > [ 193.204660][ T369] ? balance_pgdat+0xed0/0xed0 > [ 193.225776][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 > [ 193.252306][ T369] ? finish_wait+0x270/0x270 > [ 193.272473][ T369] ? __kthread_parkme+0x4d/0x1a0 > [ 193.294476][ T369] ? __kthread_parkme+0xcc/0x1a0 > [ 193.316704][ T369] ? balance_pgdat+0xed0/0xed0 > [ 193.337808][ T369] kthread+0x358/0x420 > [ 193.355666][ T369] ? kthread_create_worker_on_cpu+0xc0/0xc0 > [ 193.381884][ T369] ret_from_fork+0x22/0x30 > > > --- > > This is part of a gpu lockdep annotation series simply because it > > really helps to catch issues where gpu subsystem locks and primitives > > can deadlock with themselves through allocations and mmu notifiers. > > But aside from that motivation it should be completely free-standing, > > and can land through -mm/-rdma/-hmm or any other tree really whenever. > > -Daniel > > --- > > mm/mmu_notifier.c | 7 ------- > > mm/page_alloc.c | 23 ++++++++++++++--------- > > 2 files changed, 14 insertions(+), 16 deletions(-) > > > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c > > index 06852b896fa6..5d578b9122f8 100644 > > --- a/mm/mmu_notifier.c > > +++ b/mm/mmu_notifier.c > > @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, > > lockdep_assert_held_write(&mm->mmap_sem); > > BUG_ON(atomic_read(&mm->mm_users) <= 0); > > > > - if (IS_ENABLED(CONFIG_LOCKDEP)) { > > - fs_reclaim_acquire(GFP_KERNEL); > > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > - fs_reclaim_release(GFP_KERNEL); > > - } > > - > > if (!mm->notifier_subscriptions) { > > /* > > * kmalloc cannot be called under mm_take_all_locks(), but we > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > > index 13cc653122b7..f8a222db4a53 100644 > > --- a/mm/page_alloc.c > > +++ b/mm/page_alloc.c > > @@ -57,6 +57,7 @@ > > #include <trace/events/oom.h> > > #include <linux/prefetch.h> > > #include <linux/mm_inline.h> > > +#include <linux/mmu_notifier.h> > > #include <linux/migrate.h> > > #include <linux/hugetlb.h> > > #include <linux/sched/rt.h> > > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > > static struct lockdep_map __fs_reclaim_map = > > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > > +static bool __need_reclaim(gfp_t gfp_mask) > > { > > gfp_mask = current_gfp_context(gfp_mask); > > > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > > if (current->flags & PF_MEMALLOC) > > return false; > > > > - /* We're only interested __GFP_FS allocations for now */ > > - if (!(gfp_mask & __GFP_FS)) > > - return false; > > - > > if (gfp_mask & __GFP_NOLOCKDEP) > > return false; > > > > @@ -4158,15 +4155,23 @@ void __fs_reclaim_release(void) > > > > void fs_reclaim_acquire(gfp_t gfp_mask) > > { > > - if (__need_fs_reclaim(gfp_mask)) > > - __fs_reclaim_acquire(); > > + if (__need_reclaim(gfp_mask)) { > > + if (!(gfp_mask & __GFP_FS)) > > + __fs_reclaim_acquire(); > > + > > + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > + lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > + > > + } > > } > > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > > > void fs_reclaim_release(gfp_t gfp_mask) > > { > > - if (__need_fs_reclaim(gfp_mask)) > > - __fs_reclaim_release(); > > + if (__need_reclaim(gfp_mask)) { > > + if (!(gfp_mask & __GFP_FS)) > > + __fs_reclaim_release(); > > + } > > } > > EXPORT_SYMBOL_GPL(fs_reclaim_release); > > #endif > > -- > > 2.26.2 > > > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From daniel.vetter at ffwll.ch Sun Jun 21 18:07:08 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Sun, 21 Jun 2020 20:07:08 +0200 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200621174205.GB1398@lca.pw> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> <20200621174205.GB1398@lca.pw> Message-ID: <CAKMK7uFZAFVmceoYvqPovOifGw_Y8Ey-OMy6wioMjwPWhu9dDg@mail.gmail.com> On Sun, Jun 21, 2020 at 7:42 PM Qian Cai <cai at lca.pw> wrote: > > On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > > fs_reclaim_acquire/release nicely catch recursion issues when > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > to use to keep the excessive caches in check). For mmu notifier > > recursions we do have lockdep annotations since 23b68395c7c7 > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > But these only fire if a path actually results in some pte > > invalidation - for most small allocations that's very rarely the case. > > The other trouble is that pte invalidation can happen any time when > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > recursion. > > > > I was pondering whether we should just do the general annotation, but > > there's always the risk for false positives. Plus I'm assuming that > > the core fs and io code is a lot better reviewed and tested than > > random mmu notifier code in drivers. Hence why I decide to only > > annotate for that specific case. > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > still need to explicit pull in the mmu notifier map - there's a lot > > more places that do pte invalidation than just direct reclaim, these > > two contexts arent the same. > > > > Note that the mmu notifiers needing their own independent lockdep map > > is also the reason we can't hold them from fs_reclaim_acquire to > > fs_reclaim_release - it would nest with the acquistion in the pte > > invalidation code, causing a lockdep splat. And we can't remove the > > annotations from pte invalidation and all the other places since > > they're called from many other places than page reclaim. Hence we can > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > strictly more powerful. > > > > v2: Review from Thomas Hellstrom: > > - unbotch the fs_reclaim context check, I accidentally inverted it, > > but it didn't blow up because I inverted it immediately > > - fix compiling for !CONFIG_MMU_NOTIFIER > > > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > > Cc: Andrew Morton <akpm at linux-foundation.org> > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > Cc: linux-mm at kvack.org > > Cc: linux-rdma at vger.kernel.org > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Replying the right patch here... > > Reverting this commit [1] fixed the lockdep warning below while applying > some memory pressure. > > [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") Hm, then I'm confused because - there's not mmut notifier lockdep map in the splat at a.. - the patch is supposed to not change anything for fs_reclaim (but the interim version got that wrong) - looking at the paths it's kmalloc vs kswapd, both places I totally expect fs_reflaim to be used. But you're claiming reverting this prevents the lockdep splat. If that's right, then my reasoning above is broken somewhere. Someone less blind than me having an idea? Aside this is the first email I've typed, until I realized the first report was against the broken patch and that looked like a much more reasonable explanation (but didn't quite match up with the code paths). Thanks, Daniel > > [ 190.455003][ T369] WARNING: possible circular locking dependency detected > [ 190.487291][ T369] 5.8.0-rc1-next-20200621 #1 Not tainted > [ 190.512363][ T369] ------------------------------------------------------ > [ 190.543354][ T369] kswapd3/369 is trying to acquire lock: > [ 190.568523][ T369] ffff889fcf694528 (&xfs_nondir_ilock_class){++++}-{3:3}, at: xfs_reclaim_inode+0xdf/0x860 > spin_lock at include/linux/spinlock.h:353 > (inlined by) xfs_iflags_test_and_set at fs/xfs/xfs_inode.h:166 > (inlined by) xfs_iflock_nowait at fs/xfs/xfs_inode.h:249 > (inlined by) xfs_reclaim_inode at fs/xfs/xfs_icache.c:1127 > [ 190.614359][ T369] > [ 190.614359][ T369] but task is already holding lock: > [ 190.647763][ T369] ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > __fs_reclaim_acquire at mm/page_alloc.c:4200 > [ 190.687845][ T369] > [ 190.687845][ T369] which lock already depends on the new lock. > [ 190.687845][ T369] > [ 190.734890][ T369] > [ 190.734890][ T369] the existing dependency chain (in reverse order) is: > [ 190.775991][ T369] > [ 190.775991][ T369] -> #1 (fs_reclaim){+.+.}-{0:0}: > [ 190.808150][ T369] fs_reclaim_acquire+0x77/0x80 > [ 190.832152][ T369] slab_pre_alloc_hook.constprop.52+0x20/0x120 > slab_pre_alloc_hook at mm/slab.h:507 > [ 190.862173][ T369] kmem_cache_alloc+0x43/0x2a0 > [ 190.885602][ T369] kmem_zone_alloc+0x113/0x3ef > kmem_zone_alloc at fs/xfs/kmem.c:129 > [ 190.908702][ T369] xfs_inode_item_init+0x1d/0xa0 > xfs_inode_item_init at fs/xfs/xfs_inode_item.c:639 > [ 190.934461][ T369] xfs_trans_ijoin+0x96/0x100 > xfs_trans_ijoin at fs/xfs/libxfs/xfs_trans_inode.c:34 > [ 190.961530][ T369] xfs_setattr_nonsize+0x1a6/0xcd0 > xfs_setattr_nonsize at fs/xfs/xfs_iops.c:716 > [ 190.987331][ T369] xfs_vn_setattr+0x133/0x160 > xfs_vn_setattr at fs/xfs/xfs_iops.c:1081 > [ 191.010476][ T369] notify_change+0x6c5/0xba1 > notify_change at fs/attr.c:336 > [ 191.033317][ T369] chmod_common+0x19b/0x390 > [ 191.055770][ T369] ksys_fchmod+0x28/0x60 > [ 191.077957][ T369] __x64_sys_fchmod+0x4e/0x70 > [ 191.102767][ T369] do_syscall_64+0x5f/0x310 > [ 191.125090][ T369] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > [ 191.153749][ T369] > [ 191.153749][ T369] -> #0 (&xfs_nondir_ilock_class){++++}-{3:3}: > [ 191.191267][ T369] __lock_acquire+0x2efc/0x4da0 > [ 191.215974][ T369] lock_acquire+0x1ac/0xaf0 > [ 191.238953][ T369] down_write_nested+0x92/0x150 > [ 191.262955][ T369] xfs_reclaim_inode+0xdf/0x860 > [ 191.287149][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 > [ 191.313291][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 > [ 191.338357][ T369] super_cache_scan+0x2fd/0x430 > [ 191.362354][ T369] do_shrink_slab+0x317/0x990 > [ 191.385341][ T369] shrink_slab+0x3a8/0x4b0 > [ 191.407214][ T369] shrink_node+0x49c/0x17b0 > [ 191.429841][ T369] balance_pgdat+0x59c/0xed0 > [ 191.455041][ T369] kswapd+0x5a4/0xc40 > [ 191.477524][ T369] kthread+0x358/0x420 > [ 191.499285][ T369] ret_from_fork+0x22/0x30 > [ 191.521107][ T369] > [ 191.521107][ T369] other info that might help us debug this: > [ 191.521107][ T369] > [ 191.567490][ T369] Possible unsafe locking scenario: > [ 191.567490][ T369] > [ 191.600947][ T369] CPU0 CPU1 > [ 191.624808][ T369] ---- ---- > [ 191.649236][ T369] lock(fs_reclaim); > [ 191.667607][ T369] lock(&xfs_nondir_ilock_class); > [ 191.702096][ T369] lock(fs_reclaim); > [ 191.731243][ T369] lock(&xfs_nondir_ilock_class); > [ 191.754025][ T369] > [ 191.754025][ T369] *** DEADLOCK *** > [ 191.754025][ T369] > [ 191.791126][ T369] 4 locks held by kswapd3/369: > [ 191.812198][ T369] #0: ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > [ 191.854319][ T369] #1: ffffffffb5074c50 (shrinker_rwsem){++++}-{3:3}, at: shrink_slab+0x219/0x4b0 > [ 191.896043][ T369] #2: ffff8890279b40e0 (&type->s_umount_key#27){++++}-{3:3}, at: trylock_super+0x11/0xb0 > [ 191.940538][ T369] #3: ffff889027a73a28 (&pag->pag_ici_reclaim_lock){+.+.}-{3:3}, at: xfs_reclaim_inodes_ag+0x135/0xb00 > [ 191.995314][ T369] > [ 191.995314][ T369] stack backtrace: > [ 192.022934][ T369] CPU: 42 PID: 369 Comm: kswapd3 Not tainted 5.8.0-rc1-next-20200621 #1 > [ 192.060546][ T369] Hardware name: HP ProLiant BL660c Gen9, BIOS I38 10/17/2018 > [ 192.094518][ T369] Call Trace: > [ 192.109005][ T369] dump_stack+0x9d/0xe0 > [ 192.127468][ T369] check_noncircular+0x347/0x400 > [ 192.149526][ T369] ? print_circular_bug+0x360/0x360 > [ 192.172584][ T369] ? freezing_slow_path.cold.2+0x2a/0x2a > [ 192.197251][ T369] __lock_acquire+0x2efc/0x4da0 > [ 192.218737][ T369] ? lockdep_hardirqs_on_prepare+0x550/0x550 > [ 192.246736][ T369] ? __lock_acquire+0x3541/0x4da0 > [ 192.269673][ T369] lock_acquire+0x1ac/0xaf0 > [ 192.290192][ T369] ? xfs_reclaim_inode+0xdf/0x860 > [ 192.313158][ T369] ? rcu_read_unlock+0x50/0x50 > [ 192.335057][ T369] down_write_nested+0x92/0x150 > [ 192.358409][ T369] ? xfs_reclaim_inode+0xdf/0x860 > [ 192.380890][ T369] ? rwsem_down_write_slowpath+0xf50/0xf50 > [ 192.406891][ T369] ? find_held_lock+0x33/0x1c0 > [ 192.427925][ T369] ? xfs_ilock+0x2ef/0x370 > [ 192.447496][ T369] ? xfs_reclaim_inode+0xdf/0x860 > [ 192.472315][ T369] xfs_reclaim_inode+0xdf/0x860 > [ 192.496649][ T369] ? xfs_inode_clear_reclaim_tag+0xa0/0xa0 > [ 192.524188][ T369] ? do_raw_spin_unlock+0x4f/0x250 > [ 192.546852][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 > [ 192.570473][ T369] ? xfs_reclaim_inode+0x860/0x860 > [ 192.592692][ T369] ? mark_held_locks+0xb0/0x110 > [ 192.614287][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 > [ 192.640800][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 > [ 192.666695][ T369] ? try_to_wake_up+0xcf/0xf40 > [ 192.688265][ T369] ? migrate_swap_stop+0xc10/0xc10 > [ 192.711966][ T369] ? do_raw_spin_unlock+0x4f/0x250 > [ 192.735032][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 > xfs_reclaim_inodes_nr at fs/xfs/xfs_icache.c:1399 > [ 192.757674][ T369] ? xfs_reclaim_inodes+0x90/0x90 > [ 192.780028][ T369] ? list_lru_count_one+0x177/0x300 > [ 192.803010][ T369] super_cache_scan+0x2fd/0x430 > super_cache_scan at fs/super.c:115 > [ 192.824491][ T369] do_shrink_slab+0x317/0x990 > do_shrink_slab at mm/vmscan.c:514 > [ 192.845160][ T369] shrink_slab+0x3a8/0x4b0 > shrink_slab_memcg at mm/vmscan.c:584 > (inlined by) shrink_slab at mm/vmscan.c:662 > [ 192.864722][ T369] ? do_shrink_slab+0x990/0x990 > [ 192.886137][ T369] ? rcu_is_watching+0x2c/0x80 > [ 192.907289][ T369] ? mem_cgroup_protected+0x228/0x470 > [ 192.931166][ T369] ? vmpressure+0x25/0x290 > [ 192.950595][ T369] shrink_node+0x49c/0x17b0 > [ 192.972332][ T369] balance_pgdat+0x59c/0xed0 > kswapd_shrink_node at mm/vmscan.c:3521 > (inlined by) balance_pgdat at mm/vmscan.c:3670 > [ 192.994918][ T369] ? __node_reclaim+0x950/0x950 > [ 193.018625][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 > [ 193.046566][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 > [ 193.070214][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 > [ 193.093176][ T369] ? finish_task_switch+0x129/0x650 > [ 193.116225][ T369] ? finish_task_switch+0xf2/0x650 > [ 193.138809][ T369] ? rcu_read_lock_bh_held+0xc0/0xc0 > [ 193.163323][ T369] kswapd+0x5a4/0xc40 > [ 193.182690][ T369] ? __kthread_parkme+0x4d/0x1a0 > [ 193.204660][ T369] ? balance_pgdat+0xed0/0xed0 > [ 193.225776][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 > [ 193.252306][ T369] ? finish_wait+0x270/0x270 > [ 193.272473][ T369] ? __kthread_parkme+0x4d/0x1a0 > [ 193.294476][ T369] ? __kthread_parkme+0xcc/0x1a0 > [ 193.316704][ T369] ? balance_pgdat+0xed0/0xed0 > [ 193.337808][ T369] kthread+0x358/0x420 > [ 193.355666][ T369] ? kthread_create_worker_on_cpu+0xc0/0xc0 > [ 193.381884][ T369] ret_from_fork+0x22/0x30 > > > --- > > This is part of a gpu lockdep annotation series simply because it > > really helps to catch issues where gpu subsystem locks and primitives > > can deadlock with themselves through allocations and mmu notifiers. > > But aside from that motivation it should be completely free-standing, > > and can land through -mm/-rdma/-hmm or any other tree really whenever. > > -Daniel > > --- > > mm/mmu_notifier.c | 7 ------- > > mm/page_alloc.c | 25 ++++++++++++++++--------- > > 2 files changed, 16 insertions(+), 16 deletions(-) > > > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c > > index 06852b896fa6..5d578b9122f8 100644 > > --- a/mm/mmu_notifier.c > > +++ b/mm/mmu_notifier.c > > @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, > > lockdep_assert_held_write(&mm->mmap_sem); > > BUG_ON(atomic_read(&mm->mm_users) <= 0); > > > > - if (IS_ENABLED(CONFIG_LOCKDEP)) { > > - fs_reclaim_acquire(GFP_KERNEL); > > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > - fs_reclaim_release(GFP_KERNEL); > > - } > > - > > if (!mm->notifier_subscriptions) { > > /* > > * kmalloc cannot be called under mm_take_all_locks(), but we > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > > index 13cc653122b7..7536faaaa0fd 100644 > > --- a/mm/page_alloc.c > > +++ b/mm/page_alloc.c > > @@ -57,6 +57,7 @@ > > #include <trace/events/oom.h> > > #include <linux/prefetch.h> > > #include <linux/mm_inline.h> > > +#include <linux/mmu_notifier.h> > > #include <linux/migrate.h> > > #include <linux/hugetlb.h> > > #include <linux/sched/rt.h> > > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > > static struct lockdep_map __fs_reclaim_map = > > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > > +static bool __need_reclaim(gfp_t gfp_mask) > > { > > gfp_mask = current_gfp_context(gfp_mask); > > > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > > if (current->flags & PF_MEMALLOC) > > return false; > > > > - /* We're only interested __GFP_FS allocations for now */ > > - if (!(gfp_mask & __GFP_FS)) > > - return false; > > - > > if (gfp_mask & __GFP_NOLOCKDEP) > > return false; > > > > @@ -4158,15 +4155,25 @@ void __fs_reclaim_release(void) > > > > void fs_reclaim_acquire(gfp_t gfp_mask) > > { > > - if (__need_fs_reclaim(gfp_mask)) > > - __fs_reclaim_acquire(); > > + if (__need_reclaim(gfp_mask)) { > > + if (gfp_mask & __GFP_FS) > > + __fs_reclaim_acquire(); > > + > > +#ifdef CONFIG_MMU_NOTIFIER > > + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > + lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > +#endif > > + > > + } > > } > > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > > > void fs_reclaim_release(gfp_t gfp_mask) > > { > > - if (__need_fs_reclaim(gfp_mask)) > > - __fs_reclaim_release(); > > + if (__need_reclaim(gfp_mask)) { > > + if (gfp_mask & __GFP_FS) > > + __fs_reclaim_release(); > > + } > > } > > EXPORT_SYMBOL_GPL(fs_reclaim_release); > > #endif > > -- > > 2.26.2 > > > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From daniel at ffwll.ch Sun Jun 21 20:01:03 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Sun, 21 Jun 2020 22:01:03 +0200 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <CAKMK7uFZAFVmceoYvqPovOifGw_Y8Ey-OMy6wioMjwPWhu9dDg@mail.gmail.com> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> <20200621174205.GB1398@lca.pw> <CAKMK7uFZAFVmceoYvqPovOifGw_Y8Ey-OMy6wioMjwPWhu9dDg@mail.gmail.com> Message-ID: <20200621200103.GV20149@phenom.ffwll.local> On Sun, Jun 21, 2020 at 08:07:08PM +0200, Daniel Vetter wrote: > On Sun, Jun 21, 2020 at 7:42 PM Qian Cai <cai at lca.pw> wrote: > > > > On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > > > fs_reclaim_acquire/release nicely catch recursion issues when > > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > > to use to keep the excessive caches in check). For mmu notifier > > > recursions we do have lockdep annotations since 23b68395c7c7 > > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > > > But these only fire if a path actually results in some pte > > > invalidation - for most small allocations that's very rarely the case. > > > The other trouble is that pte invalidation can happen any time when > > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > > recursion. > > > > > > I was pondering whether we should just do the general annotation, but > > > there's always the risk for false positives. Plus I'm assuming that > > > the core fs and io code is a lot better reviewed and tested than > > > random mmu notifier code in drivers. Hence why I decide to only > > > annotate for that specific case. > > > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > > still need to explicit pull in the mmu notifier map - there's a lot > > > more places that do pte invalidation than just direct reclaim, these > > > two contexts arent the same. > > > > > > Note that the mmu notifiers needing their own independent lockdep map > > > is also the reason we can't hold them from fs_reclaim_acquire to > > > fs_reclaim_release - it would nest with the acquistion in the pte > > > invalidation code, causing a lockdep splat. And we can't remove the > > > annotations from pte invalidation and all the other places since > > > they're called from many other places than page reclaim. Hence we can > > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > > strictly more powerful. > > > > > > v2: Review from Thomas Hellstrom: > > > - unbotch the fs_reclaim context check, I accidentally inverted it, > > > but it didn't blow up because I inverted it immediately > > > - fix compiling for !CONFIG_MMU_NOTIFIER > > > > > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > > Cc: linux-mm at kvack.org > > > Cc: linux-rdma at vger.kernel.org > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > Cc: Christian K?nig <christian.koenig at amd.com> > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > Replying the right patch here... > > > > Reverting this commit [1] fixed the lockdep warning below while applying > > some memory pressure. > > > > [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") > > Hm, then I'm confused because > - there's not mmut notifier lockdep map in the splat at a.. > - the patch is supposed to not change anything for fs_reclaim (but the > interim version got that wrong) > - looking at the paths it's kmalloc vs kswapd, both places I totally > expect fs_reflaim to be used. > > But you're claiming reverting this prevents the lockdep splat. If > that's right, then my reasoning above is broken somewhere. Someone > less blind than me having an idea? > > Aside this is the first email I've typed, until I realized the first > report was against the broken patch and that looked like a much more > reasonable explanation (but didn't quite match up with the code > paths). Below diff should undo the functional change in my patch. Can you pls test whether the lockdep splat is really gone with that? Might need a lot of testing and memory pressure to be sure, since all these reclaim paths aren't very deterministic. -Daniel --- diff --git a/mm/page_alloc.c b/mm/page_alloc.c index d807587c9ae6..27ea763c6155 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -4191,11 +4191,6 @@ void fs_reclaim_acquire(gfp_t gfp_mask) if (gfp_mask & __GFP_FS) __fs_reclaim_acquire(); -#ifdef CONFIG_MMU_NOTIFIER - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); - lock_map_release(&__mmu_notifier_invalidate_range_start_map); -#endif - } } EXPORT_SYMBOL_GPL(fs_reclaim_acquire); -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From bhanuprakash.modem at intel.com Mon Jun 22 04:34:36 2020 From: bhanuprakash.modem at intel.com (Modem, Bhanuprakash) Date: Mon, 22 Jun 2020 04:34:36 +0000 Subject: [Intel-gfx] [v8 3/3] drm/debug: Expose connector VRR monitor range via debugfs In-Reply-To: <20200619184239.GA4000@intel.com> References: <20200619212356.19285-1-bhanuprakash.modem@intel.com> <20200619212356.19285-4-bhanuprakash.modem@intel.com> <20200619184239.GA4000@intel.com> Message-ID: <SN6PR11MB33278D1F996464CC461921078D970@SN6PR11MB3327.namprd11.prod.outlook.com> > -----Original Message----- > From: Navare, Manasi D <manasi.d.navare at intel.com> > Sent: Saturday, June 20, 2020 12:13 AM > To: Modem, Bhanuprakash <bhanuprakash.modem at intel.com> > Cc: dri-devel at lists.freedesktop.org; intel-gfx at lists.freedesktop.org > Subject: Re: [v8 3/3] drm/debug: Expose connector VRR monitor range via > debugfs > > Hi Bhanu, > > Thanks for the patch, functionality wise looks good. Have you tested this > with kms_vrr IGT, do we see the vrr_range properly exposed? [Bhanu] Yes, the vrr_range is exposing properly. I have verified the debugfs node manually and through IGT. > > Also please find some comments below > > On Sat, Jun 20, 2020 at 02:53:56AM +0530, Bhanuprakash Modem wrote: > > [Why] > > It's useful to know the min and max vrr range for IGT testing. > > > > [How] > > Expose the min and max vfreq for the connector via a debugfs file > > on the connector, "vrr_range". > > > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > > > v2: > > * Fix the typo in max_vfreq (Manasi) > > * Change the name of node to i915_vrr_info so we can add > > other vrr info for more debug info (Manasi) > > * Change the VRR capable to display Yes or No (Manasi) > > * Fix indentation checkpatch errors (Manasi) > > v3: > > * Remove the unnecessary debug print (Manasi) > > v4: > > * Rebase > > v5: > > * Rename to vrr_range to match AMD debugfs > > v6: > > * Rebase (manasi) > > v7: > > * Fix cmpilation due to rebase > > v8: > > * Move debugfs node creation logic to DRM (Emil) > > * Remove AMD specific logic (Emil) > > > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > Cc: Jani Nikula <jani.nikula at linux.intel.com> > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Harry Wentland <harry.wentland at amd.com> > > --- > > .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ----------------- > > drivers/gpu/drm/drm_debugfs.c | 22 +++++++++++++++++++ > > 2 files changed, 22 insertions(+), 20 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > > index 076af267b488..71387d2af2ed 100644 > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > > @@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void > *data) > > return res; > > } > > > > -/* > > - * Returns the min and max vrr vfreq through the connector's debugfs > file. > > - * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > - */ > > -static int vrr_range_show(struct seq_file *m, void *data) > > -{ > > - struct drm_connector *connector = m->private; > > - struct amdgpu_dm_connector *aconnector = > to_amdgpu_dm_connector(connector); > > - > > - if (connector->status != connector_status_connected) > > - return -ENODEV; > > - > > - seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); > > - seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); > > - > > - return 0; > > -} > > - > > #ifdef CONFIG_DRM_AMD_DC_HDCP > > /* > > * Returns the HDCP capability of the Display (1.4 for now). > > @@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, > char __user *buf, > > DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); > > DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); > > DEFINE_SHOW_ATTRIBUTE(output_bpc); > > -DEFINE_SHOW_ATTRIBUTE(vrr_range); > > #ifdef CONFIG_DRM_AMD_DC_HDCP > > DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); > > #endif > > @@ -1059,7 +1040,6 @@ static const struct { > > {"phy_settings", &dp_phy_settings_debugfs_fop}, > > {"test_pattern", &dp_phy_test_pattern_fops}, > > {"output_bpc", &output_bpc_fops}, > > - {"vrr_range", &vrr_range_fops}, > > #ifdef CONFIG_DRM_AMD_DC_HDCP > > {"hdcp_sink_capability", &hdcp_sink_capability_fops}, > > #endif > > I think the AMD sepecific debugfs removal should be in a separate patch > follwing the drm_debugfs addition > patch because from merging pov that patch will get merged through AMD tree > and drm patch will get merged through drm_misc > Also cc the amd dev mailing list for that patch. [Bhanu] Sure > > @Harry does that sound okay from merging pov? > > Manasi > > > diff --git a/drivers/gpu/drm/drm_debugfs.c > b/drivers/gpu/drm/drm_debugfs.c > > index bfe4602f206b..3d7182001004 100644 > > --- a/drivers/gpu/drm/drm_debugfs.c > > +++ b/drivers/gpu/drm/drm_debugfs.c > > @@ -376,6 +376,24 @@ static ssize_t edid_write(struct file *file, const > char __user *ubuf, > > return (ret) ? ret : len; > > } > > > > +/* > > + * Returns the min and max vrr vfreq through the connector's debugfs > file. > > + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > + */ > > +static int vrr_range_show(struct seq_file *m, void *data) > > +{ > > + struct drm_connector *connector = m->private; > > + > > + if (connector->status != connector_status_connected) > > + return -ENODEV; > > + > > + seq_printf(m, "Min: %u\n", (u8)connector- > >display_info.monitor_range.min_vfreq); > > + seq_printf(m, "Max: %u\n", (u8)connector- > >display_info.monitor_range.max_vfreq); > > + > > + return 0; > > +} > > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > > + > > static const struct file_operations drm_edid_fops = { > > .owner = THIS_MODULE, > > .open = edid_open, > > @@ -413,6 +431,10 @@ void drm_debugfs_connector_add(struct drm_connector > *connector) > > /* edid */ > > debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root, > connector, > > &drm_edid_fops); > > + > > + /* vrr range */ > > + debugfs_create_file("vrr_range", S_IRUGO, root, connector, > > + &vrr_range_fops); > > } > > > > void drm_debugfs_connector_remove(struct drm_connector *connector) > > -- > > 2.20.1 > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel From bhanuprakash.modem at intel.com Mon Jun 22 14:25:16 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Mon, 22 Jun 2020 19:55:16 +0530 Subject: [Intel-gfx] [v6 0/3] VRR capable attach prop in i915, VRR debugfs Message-ID: <20200622142519.16214-1-bhanuprakash.modem@intel.com> This is an initial set of patches for enabling VRR support in i915. This series has patches for: 1. Attach and set VRR capable connector prop for Intel DP conn 2. Expose VRR min and max through debugfs 3. Remove AMD specific logic to create debugfs Aditya Swarup (1): drm/i915/dp: Attach and set drm connector VRR property Bhanuprakash Modem (2): drm/debug: Expose connector VRR monitor range via debugfs Revert "drm/amd/display: Expose connector VRR range via debugfs" .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 -------------- drivers/gpu/drm/drm_debugfs.c | 22 +++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 4 files changed, 51 insertions(+), 20 deletions(-) -- 2.20.1 From bhanuprakash.modem at intel.com Mon Jun 22 14:25:17 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Mon, 22 Jun 2020 19:55:17 +0530 Subject: [Intel-gfx] [v6 1/3] drm/i915/dp: Attach and set drm connector VRR property In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <20200622142519.16214-2-bhanuprakash.modem@intel.com> From: Aditya Swarup <aditya.swarup at intel.com> This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..d0dba81cfb07 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6149,6 +6149,9 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -6256,6 +6259,23 @@ intel_dp_force(struct drm_connector *connector) intel_display_power_put(dev_priv, aux_domain, wakeref); } +bool intel_dp_is_vrr_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + static int intel_dp_get_modes(struct drm_connector *connector) { struct intel_connector *intel_connector = to_intel_connector(connector); @@ -6264,6 +6284,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_dp_is_vrr_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7325,6 +7349,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (INTEL_GEN(dev_priv) >= 12) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..db895a3cd93f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -14,6 +14,7 @@ enum pipe; enum port; struct drm_connector_state; struct drm_encoder; +struct drm_connector; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct drm_dp_vsc_sdp; @@ -120,6 +121,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); void intel_dp_process_phy_request(struct intel_dp *intel_dp); +bool intel_dp_is_vrr_capable(struct drm_connector *connector); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { -- 2.20.1 From bhanuprakash.modem at intel.com Mon Jun 22 14:25:18 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Mon, 22 Jun 2020 19:55:18 +0530 Subject: [Intel-gfx] [v9 2/3] drm/debug: Expose connector VRR monitor range via debugfs In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <20200622142519.16214-3-bhanuprakash.modem@intel.com> [Why] It's useful to know the min and max vrr range for IGT testing. [How] Expose the min and max vfreq for the connector via a debugfs file on the connector, "vrr_range". Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range v2: * Fix the typo in max_vfreq (Manasi) * Change the name of node to i915_vrr_info so we can add other vrr info for more debug info (Manasi) * Change the VRR capable to display Yes or No (Manasi) * Fix indentation checkpatch errors (Manasi) v3: * Remove the unnecessary debug print (Manasi) v4: * Rebase v5: * Rename to vrr_range to match AMD debugfs v6: * Rebase (manasi) v7: * Fix cmpilation due to rebase v8: * Move debugfs node creation logic to DRM (Emil) * Remove AMD specific logic (Emil) v9: * Seperate patch for removal of AMD specific logic (Manasi) Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Harry Wentland <harry.wentland at amd.com> CC: Emil Velikov <emil.l.velikov at gmail.com> --- drivers/gpu/drm/drm_debugfs.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c index bfe4602f206b..3d7182001004 100644 --- a/drivers/gpu/drm/drm_debugfs.c +++ b/drivers/gpu/drm/drm_debugfs.c @@ -376,6 +376,24 @@ static ssize_t edid_write(struct file *file, const char __user *ubuf, return (ret) ? ret : len; } +/* + * Returns the min and max vrr vfreq through the connector's debugfs file. + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range + */ +static int vrr_range_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + + if (connector->status != connector_status_connected) + return -ENODEV; + + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(vrr_range); + static const struct file_operations drm_edid_fops = { .owner = THIS_MODULE, .open = edid_open, @@ -413,6 +431,10 @@ void drm_debugfs_connector_add(struct drm_connector *connector) /* edid */ debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root, connector, &drm_edid_fops); + + /* vrr range */ + debugfs_create_file("vrr_range", S_IRUGO, root, connector, + &vrr_range_fops); } void drm_debugfs_connector_remove(struct drm_connector *connector) -- 2.20.1 From bhanuprakash.modem at intel.com Mon Jun 22 14:25:19 2020 From: bhanuprakash.modem at intel.com (Bhanuprakash Modem) Date: Mon, 22 Jun 2020 19:55:19 +0530 Subject: [Intel-gfx] [v1 3/3] Revert "drm/amd/display: Expose connector VRR range via debugfs" In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <20200622142519.16214-4-bhanuprakash.modem@intel.com> As both VRR min and max are already part of drm_display_info, drm can expose this VRR range for each connector. Hence this logic should move to core DRM. This reverts commit 727962f030c23422a01e8b22d0f463815fb15ec4. Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> Cc: Harry Wentland <harry.wentland at amd.com> Cc: Alex Deucher <alexander.deucher at amd.com> Cc: Manasi Navare <manasi.d.navare at intel.com> Cc: AMD gfx <amd-gfx at lists.freedesktop.org> --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 076af267b488..71387d2af2ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void *data) return res; } -/* - * Returns the min and max vrr vfreq through the connector's debugfs file. - * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range - */ -static int vrr_range_show(struct seq_file *m, void *data) -{ - struct drm_connector *connector = m->private; - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - - if (connector->status != connector_status_connected) - return -ENODEV; - - seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); - seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); - - return 0; -} - #ifdef CONFIG_DRM_AMD_DC_HDCP /* * Returns the HDCP capability of the Display (1.4 for now). @@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); DEFINE_SHOW_ATTRIBUTE(output_bpc); -DEFINE_SHOW_ATTRIBUTE(vrr_range); #ifdef CONFIG_DRM_AMD_DC_HDCP DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); #endif @@ -1059,7 +1040,6 @@ static const struct { {"phy_settings", &dp_phy_settings_debugfs_fop}, {"test_pattern", &dp_phy_test_pattern_fops}, {"output_bpc", &output_bpc_fops}, - {"vrr_range", &vrr_range_fops}, #ifdef CONFIG_DRM_AMD_DC_HDCP {"hdcp_sink_capability", &hdcp_sink_capability_fops}, #endif -- 2.20.1 From daniel at ffwll.ch Mon Jun 22 07:51:13 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Mon, 22 Jun 2020 09:51:13 +0200 Subject: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions In-Reply-To: <20200618004240.16263-8-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-8-lucas.demarchi@intel.com> Message-ID: <CAKMK7uEBq6-MNL1EsZtT4d07tfq7bXCGXQNX9XnorCg2NuiS5g@mail.gmail.com> On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote: > From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> > > Bspec: 33617, 33617 > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Stuart Summers <stuart.summers at intel.com> > Cc: Vanshidhar Konda <vanshidhar.r.konda at intel.com> > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > Cc: Aravind Iddamsetty <aravind.iddamsetty at intel.com> > Cc: Matt Roper <matthew.d.roper at intel.com> > Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ > drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++ > drivers/gpu/drm/i915/intel_device_info.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 4 files changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 2f8057a0b2280..f79c09257eb6b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) > #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) > #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) > +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ > (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) > #define IS_BDW_ULT(dev_priv) \ > @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_RKL_REVID(p, since, until) \ > (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) > > +#define DG1_REVID_A0 0x0 > +#define DG1_REVID_B0 0x1 > + > +#define IS_DG1_REVID(p, since, until) \ > + (IS_DG1(p) && IS_REVID(p, since, until)) > + > #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) > #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index e5fdf17cd9cdd..58cceeaa0ffa5 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = { > > #define GEN12_DGFX_FEATURES \ > GEN12_FEATURES, \ > + .memory_regions = REGION_SMEM | REGION_LMEM, \ This has lmem, and we need a new uapi for that. Last year we discussed a plan to have that behind a very scary compile-time only option, to make absolutely sure no one will start relying on this broken state before we aligned everything. And we know the current status is wrong since this patch series doesn't include any of the lmem specific uapi that's being worked on. But now almost a year passed, so that original plan needs to be renegotiated. Personally I'm not sure the scary compile option makes sense any longer, we're way later, users will soon have real hw, and once they have that they will find ways to enable it and we're potentially screwed. Discussed this also with Joonas last week or so in private, and he shares similar concerns. So I think best option here (since keeping patches out of tree is rarely best option) would be to merge just the display enabling for DG1, but also making sure that we have all the rendering support completely disabled. This would mean: - wedge gpu on startup, just to make sure - drm_driver->num_ioctls = 0 (plus ioctls = NULL) - no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure display-only driver Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts? -Daniel > + .has_master_unit_irq = 1, \ > .is_dgfx = 1 > > +static const struct intel_device_info intel_dg1_info = { > + GEN12_DGFX_FEATURES, > + PLATFORM(INTEL_DG1), > + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), > + .require_force_probe = 1, > + .engine_mask = > + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | > + BIT(VCS0) | BIT(VCS2), > +}; > + > #undef GEN > #undef PLATFORM > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 544ac61fbc363..2e40a6649d142 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -63,6 +63,7 @@ static const char * const platform_names[] = { > PLATFORM_NAME(ELKHARTLAKE), > PLATFORM_NAME(TIGERLAKE), > PLATFORM_NAME(ROCKETLAKE), > + PLATFORM_NAME(DG1), > }; > #undef PLATFORM_NAME > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 770d07003ce60..bdd21cde917cc 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -82,6 +82,7 @@ enum intel_platform { > /* gen12 */ > INTEL_TIGERLAKE, > INTEL_ROCKETLAKE, > + INTEL_DG1, > INTEL_MAX_PLATFORMS > }; > > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From zhenyuw at linux.intel.com Mon Jun 22 08:23:19 2020 From: zhenyuw at linux.intel.com (Zhenyu Wang) Date: Mon, 22 Jun 2020 16:23:19 +0800 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <159233324036.19488.6385709597388673560@build.alporthouse.com> References: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> <159233324036.19488.6385709597388673560@build.alporthouse.com> Message-ID: <20200622082319.GZ5687@zhen-hp.sh.intel.com> On 2020.06.16 19:47:20 +0100, Chris Wilson wrote: > Quoting Shaofeng Tang (2020-06-16 09:29:20) > > [Why] > > Query if vgpu is active, it is useful to the user. > > Currently, only the primary plane is usable when vgpu is active. > > The value of vgpu active is useful for user to determine > > how many planes can be used. also useful for user to > > determine different behaviors according to vgpu is active or not. > > The number of planes must be queried via kms, and all such kernel > capabilities should be declared via the appropriate interface. > > I am not saying that there is not potentially good reason to let the > user to know it's a virtual gpu, but hardcoding api limits in the client > based on the parameter is a bad idea. Yeah, as I replied for internal before, guest shouldn't detect via this kind of interface, which also doesn't reflect any gvt host capability change. For any current gap, let's fix gvt or vgpu handling instead. Thanks. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 195 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200622/205d2e75/attachment.sig> From pavel at ucw.cz Mon Jun 22 08:52:59 2020 From: pavel at ucw.cz (Pavel Machek) Date: Mon, 22 Jun 2020 10:52:59 +0200 Subject: [Intel-gfx] v5.8-rc1 on thinkpad x220, intel graphics: interface frozen, can still switch to text console Message-ID: <20200622085258.GA22686@duo.ucw.cz> Hi! Linux duo 5.8.0-rc1+ #117 SMP PREEMPT Mon Jun 15 16:13:54 CEST 2020 x86_64 GNU/Linux [133747.719711] [ 17456] 0 17456 4166 271 65536 0 0 sshd [133747.719718] [ 17466] 1000 17466 4166 289 65536 0 0 sshd [133747.719724] [ 17468] 1000 17468 433587 303033 2588672 0 0 unison [133747.719730] [ 18023] 1000 18023 1316 16 40960 0 0 sleep [133747.719737] oom-kill:constraint=CONSTRAINT_NONE,nodemask=(null),task=chromium,pid=27368,uid=1000 [133747.719795] Out of memory: Killed process 27368 (chromium) total-vm:6686908kB, anon-rss:647056kB, file-rss:0kB, shmem-rss:7452kB, UID:1000 pgtables:5304kB oom_score_adj:300 [133747.799893] oom_reaper: reaped process 27368 (chromium), now anon-rss:0kB, file-rss:0kB, shmem-rss:6836kB [136841.820558] i915 0000:00:02.0: [drm] Resetting chip for stopped heartbeat on rcs0 [136841.924333] i915 0000:00:02.0: [drm] Xorg[3016] context reset due to GPU hang Kernel is v5.8-rc1. Any ideas? Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 195 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200622/b8f9208d/attachment.sig> From chris at chris-wilson.co.uk Mon Jun 22 09:13:13 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:13:13 +0100 Subject: [Intel-gfx] v5.8-rc1 on thinkpad x220, intel graphics: interface frozen, can still switch to text console In-Reply-To: <20200622085258.GA22686@duo.ucw.cz> References: <20200622085258.GA22686@duo.ucw.cz> Message-ID: <159281719363.11575.10607533427539631904@build.alporthouse.com> Quoting Pavel Machek (2020-06-22 09:52:59) > Hi! > > Linux duo 5.8.0-rc1+ #117 SMP PREEMPT Mon Jun 15 16:13:54 CEST 2020 x86_64 GNU/Linux > > [133747.719711] [ 17456] 0 17456 4166 271 65536 0 0 sshd > [133747.719718] [ 17466] 1000 17466 4166 289 65536 0 0 sshd > [133747.719724] [ 17468] 1000 17468 433587 303033 2588672 0 0 unison > [133747.719730] [ 18023] 1000 18023 1316 16 40960 0 0 sleep > [133747.719737] oom-kill:constraint=CONSTRAINT_NONE,nodemask=(null),task=chromium,pid=27368,uid=1000 > [133747.719795] Out of memory: Killed process 27368 (chromium) total-vm:6686908kB, anon-rss:647056kB, file-rss:0kB, shmem-rss:7452kB, UID:1000 pgtables:5304kB oom_score_adj:300 > [133747.799893] oom_reaper: reaped process 27368 (chromium), now anon-rss:0kB, file-rss:0kB, shmem-rss:6836kB > [136841.820558] i915 0000:00:02.0: [drm] Resetting chip for stopped heartbeat on rcs0 > [136841.924333] i915 0000:00:02.0: [drm] Xorg[3016] context reset due > to GPU hang If that was the first occurrence it would have pointed to the error state containing more information on the cause of the hang. Attach /sys/class/drm/card0/error -Chris From daniel at ffwll.ch Mon Jun 22 09:16:14 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Mon, 22 Jun 2020 11:16:14 +0200 Subject: [Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations In-Reply-To: <159257233754.7737.17318605310513355800@build.alporthouse.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-4-daniel.vetter@ffwll.ch> <159186243606.1506.4437341616828968890@build.alporthouse.com> <CAPM=9ty6r1LuXAH_rf98GH0R9yN3x8xzKPjZG3QyvokpQBR-Hg@mail.gmail.com> <CAPj87rM0S2OPssf+WA+pjanT-0Om3yuUM1zUJCv4qTx5VYE=Fw@mail.gmail.com> <159255511144.7737.12635440776531222029@build.alporthouse.com> <CAKMK7uHEwj6jiZkRZ5PaCUNWcuU9oE4KYm4XHZwHnFzEuChZ7w@mail.gmail.com> <159255801588.7737.4425728073225310839@build.alporthouse.com> <20200619094309.GT20149@phenom.ffwll.local> <159257233754.7737.17318605310513355800@build.alporthouse.com> Message-ID: <CAKMK7uG4KzUa5yJMXQ0ffUwC_fR+pPTEnag7=qfJNtobFH3+pQ@mail.gmail.com> On Fri, Jun 19, 2020 at 3:12 PM Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Quoting Daniel Vetter (2020-06-19 10:43:09) > > On Fri, Jun 19, 2020 at 10:13:35AM +0100, Chris Wilson wrote: > > > Quoting Daniel Vetter (2020-06-19 09:51:59) > > > > On Fri, Jun 19, 2020 at 10:25 AM Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > > Forcing a generic primitive to always be part of the same global map is > > > > > horrible. > > > > > > > > And no concrete example or reason for why that's not possible. > > > > Because frankly it's not horrible, this is what upstream is all about: > > > > Shared concepts, shared contracts, shared code. > > > > > > > > The proposed patches might very well encode the wrong contract, that's > > > > all up for discussion. But fundamentally questioning that we need one > > > > is missing what upstream is all about. > > > > > > Then I have not clearly communicated, as my opinion is not that > > > validation is worthless, but that the implementation is enshrining a > > > global property on a low level primitive that prevents it from being > > > used elsewhere. And I want to replace completion [chains] with fences, and > > > bio with fences, and closures with fences, and what other equivalencies > > > there are in the kernel. The fence is as central a locking construct as > > > struct completion and deserves to be a foundational primitive provided > > > by kernel/ used throughout all drivers for discrete problem domains. > > > > > > This is narrowing dma_fence whereby adding > > > struct lockdep_map *dma_fence::wait_map > > > and annotating linkage, allows you to continue to specify that all > > > dma_fence used for a particular purpose must follow common rules, > > > without restricting the primitive for uses outside of this scope. > > > > Somewhere else in this thread I had discussions with Jason Gunthorpe about > > this topic. It might maybe change somewhat depending upon exact rules, but > > his take is very much "I don't want dma_fence in rdma". Or pretty close to > > that at least. > > > > Similar discussions with habanalabs, they're using dma_fence internally > > without any of the uapi. Discussion there has also now concluded that it's > > best if they remove them, and simply switch over to a wait_queue or > > completion like every other driver does. > > > > The next round of the patches already have a paragraph to at least > > somewhat limit how non-gpu drivers use dma_fence. And I guess actual > > consensus might be pointing even more strongly at dma_fence being solely > > something for gpus and closely related subsystem (maybe media) for syncing > > dma-buf access. > > > > So dma_fence as general replacement for completion chains I think just > > wont happen. > > That is sad. I cannot comprehend going back to pure completions after a > taste of fence scheduling. And we are not even close to fully utilising > them, as not all the async cpu [allocation!] tasks are fully tracked by > fences yet and are still stuck in a FIFO workqueue. > > > What might make sense is if e.g. the lockdep annotations could be reused, > > at least in design, for wait_queue or completion or anything else > > really. I do think that has a fair chance compared to the automagic > > cross-release annotations approach, which relied way too heavily on > > guessing where barriers are. My experience from just a bit of playing > > around with these patches here and discussing them with other driver > > maintainers is that accurately deciding where critical sections start and > > end is a job for humans only. And if you get it wrong, you will have a > > false positive. > > > > And you're indeed correct that if we'd do annotations for completions and > > wait queues, then that would need to have a class per semantically > > equivalent user, like we have lockdep classes for mutexes, not just one > > overall. > > > > But dma_fence otoh is something very specific, which comes with very > > specific rules attached - it's not a generic wait_queue at all. Originally > > it did start out as one even, but it is a very specialized wait_queue. > > > > So there's imo two cases: > > > > - Your completion is entirely orthogonal of dma_fences, and can never ever > > block a dma_fence. Don't use dma_fence for this, and no problem. It's > > just another wait_queue somewhere. > > > > - Your completion can eventually, maybe through lots of convolutions and > > depdencies, block a dma_fence. In that case full dma_fence rules apply, > > and the only thing you can do with a custom annotation is make the rules > > even stricter. E.g. if a sub-timeline in the scheduler isn't allowed to > > take certain scheduler locks. But the userspace visible/published fence > > do take them, maybe as part of command submission or retirement. > > Entirely hypotethical, no idea any driver actually needs this. > > I think we are faced with this very real problem. > > The papering we have today over userptr is so very thin, and if you > squint you can already see it is coupled into the completion signal. Just > it happens to be on the other side of the fence. > > The next batch of priority inversions involve integrating the async cpu > tasks into the scheduler, and have full dependency tracking over every > internal fence. I do not see any way to avoid coupling the completion > signal from the GPU to the earliest resource allocation, as it's an > unbroken chain of work, at least from the user's perspective. [Next up > for annotations is that we need to always assume that userspace has an > implicit lock on GPU resources; having to break that lock with a GPU > reset should be a breach of our data integrity, and best avoided, for > compute does not care one iota about system integrity and insist > userspace knows best.] Such allocations have to be allowed to fail and > for that failure to propagate cancelling the queued work, such that I'm > considering what rules we need for gfp_t. That might allow enough > leverage to break any fs_reclaim loops, but userptr is likely forever > doomed [aside from its fs_reclaim loop is as preventable as the normal > shrinker paths], but we still need to suggest to pin_user_pages that > failure is better than oom and that is not clear atm. Plus the usual > failure can happen at any time after updating the user facing > bookkeeping, but that is just extra layers in the execution monitor > ready to step in and replacing failing work with the error propagation. > Or where the system grinds to a halt, requiring the monitor to patch in > a new page / resource. Zooming out a bunch, since this is a lot about the details of making this happen, and I want to make sure I'm understanding your aim correctly. I think we have 2 big things here interacting: On one side the "everything async" push, for some value of everything. Once everything is async we let either the linux scheduler (for dma_fence_work) or the gpu scheduler (for i915_request) figure out how to order everything, with all the dependencies. For memory allocations there's likely quite a bit of retrying (on the allocation side) and skipping (on the shrinker/mmu notifier side) involved to make this all pan out. Maybe something like a GFP_NOGPU flag. On the other side we have opinionated userspace with both very long-running batches (they might as well be infinite, best we can do is check that they still preempt within a reasonable amount of time, lack of hw support for preemption in all cases notwithstanding). And batches which synchronize across engines and whatever entirely under userspace controls, with stuff like gpu semaphore waits entirely in the cmd stream, without any kernel or gpu scheduler involvement. Well maybe a slightly smarter gpu scheduler which converts the semaphore wait from a pure busy loop into a "repoll on each scheduler timeslice". But not actual dependency tracking awareness in the kernel (or guc/hw fwiw) of what userspace is really trying to do. Later is a big motivator for the former, since with arbitrary long batches and arbitrary fences any wait for a batch to complete can take forever, hence anything that might end up doing that needs to be done async and without locks. That way we don't have to shoot anything if a batch takes too long. Finally if anything goes wrong (on the kernel side at least) we just propagete fence error state through the entire ladder of in-flight things (only if it goes wrong terminally ofc). Roughly correct or did I miss a big (or small but really important) thing? Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From jani.nikula at linux.intel.com Mon Jun 22 09:55:35 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Mon, 22 Jun 2020 12:55:35 +0300 Subject: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions In-Reply-To: <CAKMK7uEBq6-MNL1EsZtT4d07tfq7bXCGXQNX9XnorCg2NuiS5g@mail.gmail.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-8-lucas.demarchi@intel.com> <CAKMK7uEBq6-MNL1EsZtT4d07tfq7bXCGXQNX9XnorCg2NuiS5g@mail.gmail.com> Message-ID: <87zh8vo25k.fsf@intel.com> On Mon, 22 Jun 2020, Daniel Vetter <daniel at ffwll.ch> wrote: > On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote: >> From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> >> >> Bspec: 33617, 33617 >> >> Cc: Jos? Roberto de Souza <jose.souza at intel.com> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> >> Cc: Stuart Summers <stuart.summers at intel.com> >> Cc: Vanshidhar Konda <vanshidhar.r.konda at intel.com> >> Cc: Lucas De Marchi <lucas.demarchi at intel.com> >> Cc: Aravind Iddamsetty <aravind.iddamsetty at intel.com> >> Cc: Matt Roper <matthew.d.roper at intel.com> >> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> >> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> >> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> >> --- >> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ >> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++ >> drivers/gpu/drm/i915/intel_device_info.c | 1 + >> drivers/gpu/drm/i915/intel_device_info.h | 1 + >> 4 files changed, 21 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index 2f8057a0b2280..f79c09257eb6b 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, >> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) >> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) >> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) >> +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) >> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ >> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) >> #define IS_BDW_ULT(dev_priv) \ >> @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, >> #define IS_RKL_REVID(p, since, until) \ >> (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) >> >> +#define DG1_REVID_A0 0x0 >> +#define DG1_REVID_B0 0x1 >> + >> +#define IS_DG1_REVID(p, since, until) \ >> + (IS_DG1(p) && IS_REVID(p, since, until)) >> + >> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) >> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) >> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c >> index e5fdf17cd9cdd..58cceeaa0ffa5 100644 >> --- a/drivers/gpu/drm/i915/i915_pci.c >> +++ b/drivers/gpu/drm/i915/i915_pci.c >> @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = { >> >> #define GEN12_DGFX_FEATURES \ >> GEN12_FEATURES, \ >> + .memory_regions = REGION_SMEM | REGION_LMEM, \ > > This has lmem, and we need a new uapi for that. Last year we discussed a > plan to have that behind a very scary compile-time only option, to make > absolutely sure no one will start relying on this broken state before we > aligned everything. And we know the current status is wrong since this > patch series doesn't include any of the lmem specific uapi that's being > worked on. > > But now almost a year passed, so that original plan needs to be > renegotiated. Personally I'm not sure the scary compile option makes > sense any longer, we're way later, users will soon have real hw, and once > they have that they will find ways to enable it and we're potentially > screwed. Discussed this also with Joonas last week or so in private, and > he shares similar concerns. > > So I think best option here (since keeping patches out of tree is rarely > best option) would be to merge just the display enabling for DG1, but also > making sure that we have all the rendering support completely disabled. > This would mean: > - wedge gpu on startup, just to make sure > - drm_driver->num_ioctls = 0 (plus ioctls = NULL) > - no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure > display-only driver > > Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts? I'll defer the decision on lmem to folks who actually know this stuff, and focus on display. And from that perspective, I'd like to unblock merging the display patches. BR, Jani. > -Daniel > > >> + .has_master_unit_irq = 1, \ >> .is_dgfx = 1 >> >> +static const struct intel_device_info intel_dg1_info = { >> + GEN12_DGFX_FEATURES, >> + PLATFORM(INTEL_DG1), >> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), >> + .require_force_probe = 1, >> + .engine_mask = >> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | >> + BIT(VCS0) | BIT(VCS2), >> +}; >> + >> #undef GEN >> #undef PLATFORM >> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c >> index 544ac61fbc363..2e40a6649d142 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.c >> +++ b/drivers/gpu/drm/i915/intel_device_info.c >> @@ -63,6 +63,7 @@ static const char * const platform_names[] = { >> PLATFORM_NAME(ELKHARTLAKE), >> PLATFORM_NAME(TIGERLAKE), >> PLATFORM_NAME(ROCKETLAKE), >> + PLATFORM_NAME(DG1), >> }; >> #undef PLATFORM_NAME >> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h >> index 770d07003ce60..bdd21cde917cc 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.h >> +++ b/drivers/gpu/drm/i915/intel_device_info.h >> @@ -82,6 +82,7 @@ enum intel_platform { >> /* gen12 */ >> INTEL_TIGERLAKE, >> INTEL_ROCKETLAKE, >> + INTEL_DG1, >> INTEL_MAX_PLATFORMS >> }; >> >> -- >> 2.26.2 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Jani Nikula, Intel Open Source Graphics Center From chris at chris-wilson.co.uk Mon Jun 22 09:59:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:59:16 +0100 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Reuse the reservation_ww_class for acquiring vma backing storage In-Reply-To: <20200622095921.15530-1-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> Message-ID: <20200622095921.15530-2-chris@chris-wilson.co.uk> i915_vma_pin() remains as a convenience function to grab a single range of address space on the GPU, and must not only acquire the backing storage of the associated buffer/pages, but must also acquire backing storage for teh page directory. As such, it will want to receive the allocations, but in the meantime, convert the custom vma->pages_mutex to reuse the reservation_ww_class from the associated backing store (object for now). Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 21 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 - drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 1 - drivers/gpu/drm/i915/gt/intel_ggtt.c | 23 +-- drivers/gpu/drm/i915/gt/intel_gtt.h | 2 - drivers/gpu/drm/i915/gt/intel_ppgtt.c | 3 +- drivers/gpu/drm/i915/i915_vma.c | 189 ++++++------------ drivers/gpu/drm/i915/i915_vma.h | 3 - drivers/gpu/drm/i915/i915_vma_types.h | 7 - drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +- drivers/gpu/drm/i915/selftests/mock_gtt.c | 1 - 11 files changed, 92 insertions(+), 164 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index f7f34954a920..678e7f82f6c9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -332,7 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) __i915_vma_unpin(vma); if (ev->flags & __EXEC_OBJECT_HAS_PAGES) - i915_vma_put_pages(vma); + i915_gem_object_unpin_pages(vma->obj); ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE | @@ -1095,7 +1095,6 @@ static int eb_reserve_vma(struct eb_vm_work *work, struct eb_vma *ev) if (unlikely(err)) return err; - atomic_add(I915_VMA_PAGES_ACTIVE, &vma->pages_count); atomic_or(bind_flags, &vma->flags); if (i915_vma_is_ggtt(vma)) @@ -1160,6 +1159,13 @@ static int wait_for_timeline(struct intel_timeline *tl) } while (1); } +static void eb_pin_vma_pages(struct i915_vma *vma, unsigned int count) +{ + count = hweight32(count); + while (count--) + __i915_gem_object_pin_pages(vma->obj); +} + static int __eb_bind_vma(struct eb_vm_work *work, int err) { struct i915_address_space *vm = work->vm; @@ -1201,12 +1207,15 @@ static int __eb_bind_vma(struct eb_vm_work *work, int err) GEM_BUG_ON(vma->vm != vm); GEM_BUG_ON(!i915_vma_is_active(vma)); + if (!vma->pages) + err = vma->ops->set_pages(vma); if (err == 0) err = vma->ops->bind_vma(vma, vma->obj->cache_level, - ev->bind_flags | - I915_VMA_ALLOC); - if (err) + ev->bind_flags); + if (err == 0) + eb_pin_vma_pages(vma, ev->bind_flags); + else atomic_and(~ev->bind_flags, &vma->flags); if (drm_mm_node_allocated(&ev->hole)) { @@ -1318,7 +1327,7 @@ static int eb_prepare_vma(struct eb_vma *ev) ev->bind_flags = 0; if (!(ev->flags & __EXEC_OBJECT_HAS_PAGES)) { - err = i915_vma_get_pages(vma); + err = i915_gem_object_pin_pages(vma->obj); if (err) return err; diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index 2c5ac598ade2..34f66a9ccf2d 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -360,7 +360,6 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt *ppgtt, int size) i915_active_init(&vma->active, NULL, NULL); kref_init(&vma->ref); - mutex_init(&vma->pages_mutex); vma->vm = i915_vm_get(&ggtt->vm); vma->ops = &pd_vma_ops; vma->private = ppgtt; @@ -447,7 +446,6 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt) ppgtt_init(&ppgtt->base, gt); ppgtt->base.vm.top = 1; - ppgtt->base.vm.bind_async_flags = I915_VMA_LOCAL_BIND; ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range; ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range; ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries; diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 699125928272..1aea30238aa4 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -737,7 +737,6 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt) goto err_free_pd; } - ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND; ppgtt->vm.insert_entries = gen8_ppgtt_insert; ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc; ppgtt->vm.clear_range = gen8_ppgtt_clear; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index eaacf369d304..a7160e142c1c 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -582,8 +582,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, if (flags & I915_VMA_LOCAL_BIND) { struct i915_ppgtt *alias = i915_vm_to_ggtt(vma->vm)->alias; - if (flags & I915_VMA_ALLOC && - !test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { + if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { ret = alias->vm.allocate_va_range(&alias->vm, vma->node.start, vma->size); @@ -646,7 +645,6 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt) goto err_ppgtt; ggtt->alias = ppgtt; - ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags; GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma); ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma; @@ -882,8 +880,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) IS_CHERRYVIEW(i915) /* fails with concurrent use/update */) { ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL; ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL; - ggtt->vm.bind_async_flags = - I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; } ggtt->invalidate = gen8_ggtt_invalidate; @@ -1181,11 +1177,6 @@ void i915_ggtt_disable_guc(struct i915_ggtt *ggtt) ggtt->invalidate(ggtt); } -static unsigned int clear_bind(struct i915_vma *vma) -{ - return atomic_fetch_and(~I915_VMA_BIND_MASK, &vma->flags); -} - void i915_ggtt_resume(struct i915_ggtt *ggtt) { struct i915_vma *vma; @@ -1203,11 +1194,13 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt) /* clflush objects bound into the GGTT and rebind them. */ list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link) { struct drm_i915_gem_object *obj = vma->obj; - unsigned int was_bound = clear_bind(vma); + unsigned int was_bound = + atomic_read(&vma->flags) & I915_VMA_BIND_MASK; - WARN_ON(i915_vma_bind(vma, - obj ? obj->cache_level : 0, - was_bound, NULL)); + GEM_BUG_ON(!was_bound); + GEM_WARN_ON(vma->ops->bind_vma(vma, + obj ? obj->cache_level : 0, + was_bound)); if (obj) { /* only used during resume => exclusive access */ flush |= fetch_and_zero(&obj->write_domain); obj->read_domains |= I915_GEM_DOMAIN_GTT; @@ -1448,7 +1441,7 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) * must be the vma->pages. A simple rule is that vma->pages must only * be accessed when the obj->mm.pages are pinned. */ - GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); + GEM_BUG_ON(!i915_gem_object_has_pages(vma->obj)); switch (vma->ggtt_view.type) { default: diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 773fc76dfa1b..5cbaf55e4941 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -239,8 +239,6 @@ struct i915_address_space { u64 total; /* size addr space maps (ex. 2GB for ggtt) */ u64 reserved; /* size addr space reserved */ - unsigned int bind_async_flags; - /* * Each active user context has its own address space (in full-ppgtt). * Since the vm may be shared between multiple contexts, we count how diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index ecdd58f4b993..fd1abdee2b27 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -162,8 +162,7 @@ static int ppgtt_bind_vma(struct i915_vma *vma, u32 pte_flags; int err; - if (flags & I915_VMA_ALLOC && - !test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { + if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { err = vma->vm->allocate_va_range(vma->vm, vma->node.start, vma->size); if (err) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index efb9eacf59b9..dc656c7d3191 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -115,7 +115,6 @@ vma_create(struct drm_i915_gem_object *obj, return ERR_PTR(-ENOMEM); kref_init(&vma->ref); - mutex_init(&vma->pages_mutex); vma->vm = i915_vm_get(vm); vma->ops = &vm->vma_ops; vma->obj = obj; @@ -302,13 +301,27 @@ struct i915_vma_work { unsigned int flags; }; +static void pin_pages(struct i915_vma *vma, unsigned int bind) +{ + bind = hweight32(bind & I915_VMA_BIND_MASK); + while (bind--) + __i915_gem_object_pin_pages(vma->obj); +} + static int __vma_bind(struct dma_fence_work *work) { struct i915_vma_work *vw = container_of(work, typeof(*vw), base); struct i915_vma *vma = vw->vma; int err; - err = vma->ops->bind_vma(vma, vw->cache_level, vw->flags); + if (vma->obj) /* fixup the pin-pages for bind-flags */ + pin_pages(vma, vw->flags); + + err = 0; + if (!vma->pages) + err = vma->ops->set_pages(vma); + if (err == 0) + err = vma->ops->bind_vma(vma, vw->cache_level, vw->flags); if (err) atomic_or(I915_VMA_ERROR, &vma->flags); @@ -390,9 +403,9 @@ int i915_vma_bind(struct i915_vma *vma, u32 flags, struct i915_vma_work *work) { + struct dma_fence *prev; u32 bind_flags; u32 vma_flags; - int ret; GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); GEM_BUG_ON(vma->size > vma->node.size); @@ -415,43 +428,34 @@ int i915_vma_bind(struct i915_vma *vma, if (bind_flags == 0) return 0; - GEM_BUG_ON(!vma->pages); - trace_i915_vma_bind(vma, bind_flags); - if (work && bind_flags & vma->vm->bind_async_flags) { - struct dma_fence *prev; - work->vma = vma; - work->cache_level = cache_level; - work->flags = bind_flags | I915_VMA_ALLOC; + work->vma = vma; + work->cache_level = cache_level; + work->flags = bind_flags; - /* - * Note we only want to chain up to the migration fence on - * the pages (not the object itself). As we don't track that, - * yet, we have to use the exclusive fence instead. - * - * Also note that we do not want to track the async vma as - * part of the obj->resv->excl_fence as it only affects - * execution and not content or object's backing store lifetime. - */ - prev = i915_active_set_exclusive(&vma->active, &work->base.dma); - if (prev) { - __i915_sw_fence_await_dma_fence(&work->base.chain, - prev, - &work->cb); - dma_fence_put(prev); - } + /* + * Note we only want to chain up to the migration fence on + * the pages (not the object itself). As we don't track that, + * yet, we have to use the exclusive fence instead. + * + * Also note that we do not want to track the async vma as + * part of the obj->resv->excl_fence as it only affects + * execution and not content or object's backing store lifetime. + */ + prev = i915_active_set_exclusive(&vma->active, &work->base.dma); + if (prev) { + __i915_sw_fence_await_dma_fence(&work->base.chain, + prev, + &work->cb); + dma_fence_put(prev); + } - work->base.dma.error = 0; /* enable the queue_work() */ + work->base.dma.error = 0; /* enable the queue_work() */ - if (vma->obj) { - __i915_gem_object_pin_pages(vma->obj); - work->pinned = vma->obj; - } - } else { - ret = vma->ops->bind_vma(vma, cache_level, bind_flags); - if (ret) - return ret; + if (vma->obj) { + __i915_gem_object_pin_pages(vma->obj); + work->pinned = vma->obj; } atomic_or(bind_flags, &vma->flags); @@ -694,6 +698,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (ret) return ret; } else { + const unsigned long page_sizes = + INTEL_INFO(vma->vm->i915)->page_sizes; + /* * We only support huge gtt pages through the 48b PPGTT, * however we also don't want to force any alignment for @@ -703,7 +710,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) * forseeable future. See also i915_ggtt_offset(). */ if (upper_32_bits(end - 1) && - vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { + page_sizes > I915_GTT_PAGE_SIZE) { /* * We can't mix 64K and 4K PTEs in the same page-table * (2M block), and so to avoid the ugliness and @@ -711,7 +718,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) * objects to 2M. */ u64 page_alignment = - rounddown_pow_of_two(vma->page_sizes.sg | + rounddown_pow_of_two(page_sizes | I915_GTT_PAGE_SIZE_2M); /* @@ -723,7 +730,7 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) alignment = max(alignment, page_alignment); - if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K) + if (page_sizes & I915_GTT_PAGE_SIZE_64K) size = round_up(size, I915_GTT_PAGE_SIZE_2M); } @@ -798,74 +805,6 @@ static bool try_qad_pin(struct i915_vma *vma, unsigned int flags) return pinned; } -int i915_vma_get_pages(struct i915_vma *vma) -{ - int err = 0; - - if (atomic_add_unless(&vma->pages_count, 1, 0)) - return 0; - - /* Allocations ahoy! */ - if (mutex_lock_interruptible(&vma->pages_mutex)) - return -EINTR; - - if (!atomic_read(&vma->pages_count)) { - if (vma->obj) { - err = i915_gem_object_pin_pages(vma->obj); - if (err) - goto unlock; - } - - err = vma->ops->set_pages(vma); - if (err) { - if (vma->obj) - i915_gem_object_unpin_pages(vma->obj); - goto unlock; - } - } - atomic_inc(&vma->pages_count); - -unlock: - mutex_unlock(&vma->pages_mutex); - - return err; -} - -static void __vma_put_pages(struct i915_vma *vma, unsigned int count) -{ - /* We allocate under vma_get_pages, so beware the shrinker */ - mutex_lock_nested(&vma->pages_mutex, SINGLE_DEPTH_NESTING); - GEM_BUG_ON(atomic_read(&vma->pages_count) < count); - if (atomic_sub_return(count, &vma->pages_count) == 0) { - vma->ops->clear_pages(vma); - GEM_BUG_ON(vma->pages); - if (vma->obj) - i915_gem_object_unpin_pages(vma->obj); - } - mutex_unlock(&vma->pages_mutex); -} - -void i915_vma_put_pages(struct i915_vma *vma) -{ - if (atomic_add_unless(&vma->pages_count, -1, 1)) - return; - - __vma_put_pages(vma, 1); -} - -static void vma_unbind_pages(struct i915_vma *vma) -{ - unsigned int count; - - lockdep_assert_held(&vma->vm->mutex); - - /* The upper portion of pages_count is the number of bindings */ - count = atomic_read(&vma->pages_count); - count >>= I915_VMA_PAGES_BIAS; - if (count) - __vma_put_pages(vma, count | count << I915_VMA_PAGES_BIAS); -} - static int __wait_for_unbind(struct i915_vma *vma, unsigned int flags) { return __i915_vma_wait_excl(vma, false, flags); @@ -887,20 +826,20 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (try_qad_pin(vma, flags & I915_VMA_BIND_MASK)) return 0; - err = i915_vma_get_pages(vma); - if (err) - return err; + if (vma->obj) { + err = i915_gem_object_pin_pages(vma->obj); + if (err) + return err; + } err = __wait_for_unbind(vma, flags); if (err) goto err_pages; - if (flags & vma->vm->bind_async_flags) { - work = i915_vma_work(); - if (!work) { - err = -ENOMEM; - goto err_pages; - } + work = i915_vma_work(); + if (!work) { + err = -ENOMEM; + goto err_pages; } if (flags & PIN_GLOBAL) @@ -968,16 +907,12 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) __i915_vma_set_map_and_fenceable(vma); } - GEM_BUG_ON(!vma->pages); err = i915_vma_bind(vma, vma->obj ? vma->obj->cache_level : 0, flags, work); if (err) goto err_remove; - /* There should only be at most 2 active bindings (user, global) */ - GEM_BUG_ON(bound + I915_VMA_PAGES_ACTIVE < bound); - atomic_add(I915_VMA_PAGES_ACTIVE, &vma->pages_count); list_move_tail(&vma->vm_link, &vma->vm->bound_list); GEM_BUG_ON(!i915_vma_is_active(vma)); @@ -996,12 +931,12 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) err_unlock: mutex_unlock(&vma->vm->mutex); err_fence: - if (work) - dma_fence_work_commit_imm(&work->base); + dma_fence_work_commit_imm(&work->base); if (wakeref) intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); err_pages: - i915_vma_put_pages(vma); + if (vma->obj) + i915_gem_object_unpin_pages(vma->obj); return err; } @@ -1257,6 +1192,8 @@ int i915_vma_move_to_active(struct i915_vma *vma, void __i915_vma_evict(struct i915_vma *vma) { + int count; + GEM_BUG_ON(i915_vma_is_pinned(vma)); if (i915_vma_is_map_and_fenceable(vma)) { @@ -1291,11 +1228,17 @@ void __i915_vma_evict(struct i915_vma *vma) trace_i915_vma_unbind(vma); vma->ops->unbind_vma(vma); } + count = hweight32(atomic_read(&vma->flags) & I915_VMA_BIND_MASK); atomic_and(~(I915_VMA_BIND_MASK | I915_VMA_ERROR | I915_VMA_GGTT_WRITE), &vma->flags); i915_vma_detach(vma); - vma_unbind_pages(vma); + + vma->ops->clear_pages(vma); + if (vma->obj) { + while (count--) + __i915_gem_object_unpin_pages(vma->obj); + } } int __i915_vma_unbind(struct i915_vma *vma) diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 478e8679f331..8ec204817986 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -240,9 +240,6 @@ int __must_check i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags); int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags); -int i915_vma_get_pages(struct i915_vma *vma); -void i915_vma_put_pages(struct i915_vma *vma); - static inline int i915_vma_pin_count(const struct i915_vma *vma) { return atomic_read(&vma->flags) & I915_VMA_PIN_MASK; diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h index 63831cdb7402..02c1640bb034 100644 --- a/drivers/gpu/drm/i915/i915_vma_types.h +++ b/drivers/gpu/drm/i915/i915_vma_types.h @@ -235,7 +235,6 @@ struct i915_vma { #define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND) #define I915_VMA_ALLOC_BIT 12 -#define I915_VMA_ALLOC ((int)BIT(I915_VMA_ALLOC_BIT)) #define I915_VMA_ERROR_BIT 13 #define I915_VMA_ERROR ((int)BIT(I915_VMA_ERROR_BIT)) @@ -252,11 +251,6 @@ struct i915_vma { struct i915_active active; -#define I915_VMA_PAGES_BIAS 24 -#define I915_VMA_PAGES_ACTIVE (BIT(24) | 1) - atomic_t pages_count; /* number of active binds to the pages */ - struct mutex pages_mutex; /* protect acquire/release of backing pages */ - /** * Support different GGTT views into the same object. * This means there can be multiple VMA mappings per object and per VM. @@ -280,4 +274,3 @@ struct i915_vma { }; #endif - diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c index 0016ffc7d914..e840093e205f 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c @@ -1221,9 +1221,9 @@ static void track_vma_bind(struct i915_vma *vma) __i915_gem_object_pin_pages(obj); GEM_BUG_ON(vma->pages); - atomic_set(&vma->pages_count, I915_VMA_PAGES_ACTIVE); - __i915_gem_object_pin_pages(obj); vma->pages = obj->mm.pages; + __i915_gem_object_pin_pages(obj); + atomic_or(I915_VMA_GLOBAL_BIND, &vma->flags); mutex_lock(&vma->vm->mutex); list_add_tail(&vma->vm_link, &vma->vm->bound_list); diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c index edc5e3dda8ca..54825a322852 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -92,7 +92,6 @@ static int mock_bind_ggtt(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { - atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags); return 0; } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 22 09:59:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:59:15 +0100 Subject: [Intel-gfx] [PATCH 1/7] drm/i915/gem: Replace i915_gem_object.mm.mutex with reservation_ww_class Message-ID: <20200622095921.15530-1-chris@chris-wilson.co.uk> Our goal is to pull all memory reservations (next iteration obj->ops->get_pages()) under a ww_mutex, and to align those reservations with other drivers, i.e. control all such allocations with the reservation_ww_class. Currently, this is under the purview of the obj->mm.mutex, and while obj->mm remains an embedded struct we can "simply" switch to using the reservation_ww_class obj->base.resv->lock The major consequence is the impact on the shrinker paths as the reservation_ww_class is used to wrap allocations, and a ww_mutex does not support subclassing so we cannot do our usual trick of knowing that we never recurse inside the shrinker and instead have to finish the reclaim with a trylock. This may result in us failing to release the pages after having released the vma. This will have to do until a better idea comes along. However, this step only converts the mutex over and continues to treat everything as a single allocation and pinning the pages. With the ww_mutex in place we can remove the temporary pinning, as we can then reserve all storage en masse. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 18 +------ drivers/gpu/drm/i915/gem/i915_gem_domain.c | 36 ++++--------- drivers/gpu/drm/i915/gem/i915_gem_object.c | 8 +-- drivers/gpu/drm/i915/gem/i915_gem_object.h | 21 +------- .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 - drivers/gpu/drm/i915/gem/i915_gem_pages.c | 51 ++++++++++--------- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +-- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 15 +++--- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 - drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 15 ++++-- .../gpu/drm/i915/gem/selftests/huge_pages.c | 32 +++++++----- .../i915/gem/selftests/i915_gem_coherency.c | 14 +++-- .../drm/i915/gem/selftests/i915_gem_context.c | 10 +++- .../drm/i915/gem/selftests/i915_gem_mman.c | 2 + drivers/gpu/drm/i915/i915_gem.c | 16 ++++-- .../drm/i915/selftests/intel_memory_region.c | 17 +++++-- 16 files changed, 128 insertions(+), 136 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 2679380159fc..049a15e6b496 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -124,19 +124,12 @@ static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_dire bool write = (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE); int err; - err = i915_gem_object_pin_pages(obj); - if (err) - return err; - err = i915_gem_object_lock_interruptible(obj); if (err) - goto out; + return err; err = i915_gem_object_set_to_cpu_domain(obj, write); i915_gem_object_unlock(obj); - -out: - i915_gem_object_unpin_pages(obj); return err; } @@ -145,19 +138,12 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direct struct drm_i915_gem_object *obj = dma_buf_to_obj(dma_buf); int err; - err = i915_gem_object_pin_pages(obj); - if (err) - return err; - err = i915_gem_object_lock_interruptible(obj); if (err) - goto out; + return err; err = i915_gem_object_set_to_gtt_domain(obj, false); i915_gem_object_unlock(obj); - -out: - i915_gem_object_unpin_pages(obj); return err; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 7f76fc68f498..8b93941f7f93 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -70,7 +70,7 @@ i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) * continue to assume that the obj remained out of the CPU cached * domain. */ - ret = i915_gem_object_pin_pages(obj); + ret = __i915_gem_object_get_pages_locked(obj); if (ret) return ret; @@ -131,7 +131,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) * continue to assume that the obj remained out of the CPU cached * domain. */ - ret = i915_gem_object_pin_pages(obj); + ret = __i915_gem_object_get_pages_locked(obj); if (ret) return ret; @@ -532,13 +532,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, * continue to assume that the obj remained out of the CPU cached * domain. */ - err = i915_gem_object_pin_pages(obj); - if (err) - goto out; - err = i915_gem_object_lock_interruptible(obj); if (err) - goto out_unpin; + goto out; if (read_domains & I915_GEM_DOMAIN_WC) err = i915_gem_object_set_to_wc_domain(obj, write_domain); @@ -555,8 +551,6 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, if (write_domain) i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU); -out_unpin: - i915_gem_object_unpin_pages(obj); out: i915_gem_object_put(obj); return err; @@ -572,11 +566,13 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, { int ret; + assert_object_held(obj); + *needs_clflush = 0; if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj); + ret = __i915_gem_object_get_pages_locked(obj); if (ret) return ret; @@ -584,11 +580,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, I915_WAIT_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); if (ret) - goto err_unlock; - - ret = i915_gem_object_pin_pages(obj); - if (ret) - goto err_unlock; + goto err_unpin; if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || !static_cpu_has(X86_FEATURE_CLFLUSH)) { @@ -616,8 +608,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, err_unpin: i915_gem_object_unpin_pages(obj); -err_unlock: - i915_gem_object_unlock(obj); return ret; } @@ -626,11 +616,13 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, { int ret; + assert_object_held(obj); + *needs_clflush = 0; if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj); + ret = __i915_gem_object_get_pages_locked(obj); if (ret) return ret; @@ -639,11 +631,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, I915_WAIT_ALL, MAX_SCHEDULE_TIMEOUT); if (ret) - goto err_unlock; - - ret = i915_gem_object_pin_pages(obj); - if (ret) - goto err_unlock; + goto err_unpin; if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || !static_cpu_has(X86_FEATURE_CLFLUSH)) { @@ -680,7 +668,5 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, err_unpin: i915_gem_object_unpin_pages(obj); -err_unlock: - i915_gem_object_unlock(obj); return ret; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index b6ec5b50d93b..37b3fb0eb943 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -53,8 +53,6 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, const struct drm_i915_gem_object_ops *ops, struct lock_class_key *key) { - __mutex_init(&obj->mm.lock, ops->name ?: "obj->mm.lock", key); - spin_lock_init(&obj->vma.lock); INIT_LIST_HEAD(&obj->vma.list); @@ -72,10 +70,6 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, obj->mm.madv = I915_MADV_WILLNEED; INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); mutex_init(&obj->mm.get_page.lock); - - if (IS_ENABLED(CONFIG_LOCKDEP) && i915_gem_object_is_shrinkable(obj)) - i915_gem_shrinker_taints_mutex(to_i915(obj->base.dev), - &obj->mm.lock); } /** @@ -209,10 +203,12 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, GEM_BUG_ON(obj->userfault_count); GEM_BUG_ON(!list_empty(&obj->lut_list)); + i915_gem_object_lock(obj); atomic_set(&obj->mm.pages_pin_count, 0); __i915_gem_object_put_pages(obj); GEM_BUG_ON(i915_gem_object_has_pages(obj)); bitmap_free(obj->bit_17); + i915_gem_object_unlock(obj); if (obj->base.import_attach) drm_prime_gem_destroy(&obj->base, NULL); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 7bcd2661de4c..03a1b859aeef 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -277,28 +277,12 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj); int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); - -enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock/struct_mutex */ - I915_MM_NORMAL = 0, - /* - * Only used by struct_mutex, when called "recursively" from - * direct-reclaim-esque. Safe because there is only every one - * struct_mutex in the entire system. - */ - I915_MM_SHRINKER = 1, - /* - * Used for obj->mm.lock when allocating pages. Safe because the object - * isn't yet on any LRU, and therefore the shrinker can't deadlock on - * it. As soon as the object has pages, obj->mm.lock nests within - * fs_reclaim. - */ - I915_MM_GET_PAGES = 1, -}; +int __i915_gem_object_get_pages_locked(struct drm_i915_gem_object *obj); static inline int __must_check i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) { - might_lock_nested(&obj->mm.lock, I915_MM_GET_PAGES); + might_lock(&obj->base.resv->lock.base); if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) return 0; @@ -410,7 +394,6 @@ static inline void i915_gem_object_finish_access(struct drm_i915_gem_object *obj) { i915_gem_object_unpin_pages(obj); - i915_gem_object_unlock(obj); } static inline struct intel_engine_cs * diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index b1f82a11aef2..dbb33aac7828 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -186,7 +186,6 @@ struct drm_i915_gem_object { * Protects the pages and their use. Do not use directly, but * instead go through the pin/unpin interfaces. */ - struct mutex lock; atomic_t pages_pin_count; atomic_t shrink_pin; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index af9e48ee4a33..2ff1036ef91f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -18,7 +18,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, unsigned long supported = INTEL_INFO(i915)->page_sizes; int i; - lockdep_assert_held(&obj->mm.lock); + assert_object_held(obj); if (i915_gem_object_is_volatile(obj)) obj->mm.madv = I915_MADV_DONTNEED; @@ -86,6 +86,8 @@ int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) struct drm_i915_private *i915 = to_i915(obj->base.dev); int err; + assert_object_held(obj); + if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { drm_dbg(&i915->drm, "Attempting to obtain a purgeable object\n"); @@ -105,27 +107,34 @@ int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) * either as a result of memory pressure (reaping pages under the shrinker) * or as the object is itself released. */ -int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) +int __i915_gem_object_get_pages_locked(struct drm_i915_gem_object *obj) { int err; - err = mutex_lock_interruptible_nested(&obj->mm.lock, I915_MM_GET_PAGES); - if (err) - return err; - if (unlikely(!i915_gem_object_has_pages(obj))) { GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); err = ____i915_gem_object_get_pages(obj); if (err) - goto unlock; + return err; smp_mb__before_atomic(); } atomic_inc(&obj->mm.pages_pin_count); -unlock: - mutex_unlock(&obj->mm.lock); + return 0; +} + +int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) +{ + int err; + + err = i915_gem_object_lock_interruptible(obj); + if (err) + return err; + + err = __i915_gem_object_get_pages_locked(obj); + i915_gem_object_unlock(obj); return err; } @@ -140,7 +149,7 @@ void i915_gem_object_truncate(struct drm_i915_gem_object *obj) /* Try to discard unwanted pages */ void i915_gem_object_writeback(struct drm_i915_gem_object *obj) { - lockdep_assert_held(&obj->mm.lock); + assert_object_held(obj); GEM_BUG_ON(i915_gem_object_has_pages(obj)); if (obj->ops->writeback) @@ -194,17 +203,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj) { struct sg_table *pages; - int err; + + /* May be called by shrinker from within get_pages() (on another bo) */ + assert_object_held(obj); if (i915_gem_object_has_pinned_pages(obj)) return -EBUSY; - /* May be called by shrinker from within get_pages() (on another bo) */ - mutex_lock(&obj->mm.lock); - if (unlikely(atomic_read(&obj->mm.pages_pin_count))) { - err = -EBUSY; - goto unlock; - } + if (unlikely(atomic_read(&obj->mm.pages_pin_count))) + return -EBUSY; i915_gem_object_release_mmap_offset(obj); @@ -227,11 +234,7 @@ int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj) if (!IS_ERR(pages)) obj->ops->put_pages(obj, pages); - err = 0; -unlock: - mutex_unlock(&obj->mm.lock); - - return err; + return 0; } static inline pte_t iomap_pte(resource_size_t base, @@ -325,7 +328,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, if (!i915_gem_object_type_has(obj, flags)) return ERR_PTR(-ENXIO); - err = mutex_lock_interruptible_nested(&obj->mm.lock, I915_MM_GET_PAGES); + err = i915_gem_object_lock_interruptible(obj); if (err) return ERR_PTR(err); @@ -370,7 +373,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, } out_unlock: - mutex_unlock(&obj->mm.lock); + i915_gem_object_unlock(obj); return ptr; err_unpin: diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/i915_gem_phys.c index 28147aab47b9..099bcfa8f978 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c @@ -165,7 +165,7 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) if (err) return err; - mutex_lock_nested(&obj->mm.lock, I915_MM_GET_PAGES); + i915_gem_object_lock(obj); if (obj->mm.madv != I915_MADV_WILLNEED) { err = -EFAULT; @@ -198,7 +198,7 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) i915_gem_object_release_memory_region(obj); - mutex_unlock(&obj->mm.lock); + i915_gem_object_unlock(obj); return 0; err_xfer: @@ -209,7 +209,7 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) __i915_gem_object_set_pages(obj, pages, sg_page_sizes); } err_unlock: - mutex_unlock(&obj->mm.lock); + i915_gem_object_unlock(obj); return err; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c index 5b65ce738b16..5fe2c1dd82ee 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c @@ -45,10 +45,7 @@ static bool unsafe_drop_pages(struct drm_i915_gem_object *obj, if (!(shrink & I915_SHRINK_BOUND)) flags = I915_GEM_OBJECT_UNBIND_TEST; - if (i915_gem_object_unbind(obj, flags) == 0) - __i915_gem_object_put_pages(obj); - - return !i915_gem_object_has_pages(obj); + return i915_gem_object_unbind(obj, flags) == 0; } static void try_to_writeback(struct drm_i915_gem_object *obj, @@ -192,14 +189,14 @@ i915_gem_shrink(struct drm_i915_private *i915, spin_unlock_irqrestore(&i915->mm.obj_lock, flags); - if (unsafe_drop_pages(obj, shrink)) { - /* May arrive from get_pages on another bo */ - mutex_lock(&obj->mm.lock); + if (unsafe_drop_pages(obj, shrink) && + i915_gem_object_trylock(obj)) { + __i915_gem_object_put_pages(obj); if (!i915_gem_object_has_pages(obj)) { try_to_writeback(obj, shrink); count += obj->base.size >> PAGE_SHIFT; } - mutex_unlock(&obj->mm.lock); + i915_gem_object_unlock(obj); } scanned += obj->base.size >> PAGE_SHIFT; @@ -415,7 +412,7 @@ void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915, if (!lockdep_is_held_type(&i915->drm.struct_mutex, -1)) { mutex_acquire(&i915->drm.struct_mutex.dep_map, - I915_MM_NORMAL, 0, _RET_IP_); + 0, 0, _RET_IP_); unlock = true; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c index 0158e49bf9bb..a5a272c2e43b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c @@ -265,7 +265,6 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, * pages to prevent them being swapped out and causing corruption * due to the change in swizzling. */ - mutex_lock(&obj->mm.lock); if (i915_gem_object_has_pages(obj) && obj->mm.madv == I915_MADV_WILLNEED && i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) { @@ -280,7 +279,6 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, obj->mm.quirked = true; } } - mutex_unlock(&obj->mm.lock); spin_lock(&obj->vma.lock); for_each_ggtt_vma(vma, obj) { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index e946032b13e4..4cd79f425eac 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -129,8 +129,15 @@ userptr_mn_invalidate_range_start(struct mmu_notifier *_mn, ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE | I915_GEM_OBJECT_UNBIND_BARRIER); - if (ret == 0) - ret = __i915_gem_object_put_pages(obj); + if (ret == 0) { + /* XXX ww_mutex is fs_reclaim tainted */ + if (i915_gem_object_trylock(obj)) { + ret = __i915_gem_object_put_pages(obj); + i915_gem_object_unlock(obj); + } else { + ret = -EAGAIN; + } + } i915_gem_object_put(obj); if (ret) return ret; @@ -485,7 +492,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) } } - mutex_lock_nested(&obj->mm.lock, I915_MM_GET_PAGES); + i915_gem_object_lock(obj); if (obj->userptr.work == &work->work) { struct sg_table *pages = ERR_PTR(ret); @@ -502,7 +509,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) if (IS_ERR(pages)) __i915_gem_userptr_set_active(obj, false); } - mutex_unlock(&obj->mm.lock); + i915_gem_object_unlock(obj); unpin_user_pages(pvec, pinned); kvfree(pvec); diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index 8291ede6902c..6ff7c402556e 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -452,6 +452,15 @@ static int igt_mock_exhaust_device_supported_pages(void *arg) return err; } +static void close_object(struct drm_i915_gem_object *obj) +{ + i915_gem_object_lock(obj); + __i915_gem_object_put_pages(obj); + i915_gem_object_unlock(obj); + + i915_gem_object_put(obj); +} + static int igt_mock_memory_region_huge_pages(void *arg) { const unsigned int flags[] = { 0, I915_BO_ALLOC_CONTIGUOUS }; @@ -514,8 +523,7 @@ static int igt_mock_memory_region_huge_pages(void *arg) } i915_vma_unpin(vma); - __i915_gem_object_put_pages(obj); - i915_gem_object_put(obj); + close_object(obj); } } @@ -633,8 +641,7 @@ static int igt_mock_ppgtt_misaligned_dma(void *arg) } i915_gem_object_unpin_pages(obj); - __i915_gem_object_put_pages(obj); - i915_gem_object_put(obj); + close_object(obj); } return 0; @@ -655,8 +662,7 @@ static void close_object_list(struct list_head *objects, list_for_each_entry_safe(obj, on, objects, st_link) { list_del(&obj->st_link); i915_gem_object_unpin_pages(obj); - __i915_gem_object_put_pages(obj); - i915_gem_object_put(obj); + close_object(obj); } } @@ -923,8 +929,7 @@ static int igt_mock_ppgtt_64K(void *arg) i915_vma_unpin(vma); i915_gem_object_unpin_pages(obj); - __i915_gem_object_put_pages(obj); - i915_gem_object_put(obj); + close_object(obj); } } @@ -964,9 +969,10 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) unsigned long n; int err; + i915_gem_object_lock(obj); err = i915_gem_object_prepare_read(obj, &needs_flush); if (err) - return err; + goto unlock; for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) { u32 *ptr = kmap_atomic(i915_gem_object_get_page(obj, n)); @@ -986,7 +992,8 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) } i915_gem_object_finish_access(obj); - +unlock: + i915_gem_object_unlock(obj); return err; } @@ -1304,7 +1311,9 @@ static int igt_ppgtt_smoke_huge(void *arg) } out_unpin: i915_gem_object_unpin_pages(obj); + i915_gem_object_lock(obj); __i915_gem_object_put_pages(obj); + i915_gem_object_unlock(obj); out_put: i915_gem_object_put(obj); @@ -1392,8 +1401,7 @@ static int igt_ppgtt_sanity_check(void *arg) err = igt_write_huge(ctx, obj); i915_gem_object_unpin_pages(obj); - __i915_gem_object_put_pages(obj); - i915_gem_object_put(obj); + close_object(obj); if (err) { pr_err("%s write-huge failed with size=%u pages=%u i=%d, j=%d\n", diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 87d7d8aa080f..b8dd6fabe70a 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -27,9 +27,10 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) u32 *cpu; int err; + i915_gem_object_lock(ctx->obj); err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); if (err) - return err; + goto unlock; page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); @@ -46,7 +47,9 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) kunmap_atomic(map); i915_gem_object_finish_access(ctx->obj); - return 0; +unlock: + i915_gem_object_unlock(ctx->obj); + return err; } static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) @@ -57,9 +60,10 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) u32 *cpu; int err; + i915_gem_object_lock(ctx->obj); err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); if (err) - return err; + goto unlock; page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); @@ -73,7 +77,9 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) kunmap_atomic(map); i915_gem_object_finish_access(ctx->obj); - return 0; +unlock: + i915_gem_object_unlock(ctx->obj); + return err; } static int gtt_set(struct context *ctx, unsigned long offset, u32 v) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index bb57687aea99..7e373a5b5c3c 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -461,9 +461,10 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) unsigned int n, m, need_flush; int err; + i915_gem_object_lock(obj); err = i915_gem_object_prepare_write(obj, &need_flush); if (err) - return err; + goto unlock; for (n = 0; n < real_page_count(obj); n++) { u32 *map; @@ -479,6 +480,8 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) i915_gem_object_finish_access(obj); obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU; obj->write_domain = 0; +unlock: + i915_gem_object_unlock(obj); return 0; } @@ -488,9 +491,10 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, unsigned int n, m, needs_flush; int err; + i915_gem_object_lock(obj); err = i915_gem_object_prepare_read(obj, &needs_flush); if (err) - return err; + goto unlock; for (n = 0; n < real_page_count(obj); n++) { u32 *map; @@ -527,6 +531,8 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, } i915_gem_object_finish_access(obj); +unlock: + i915_gem_object_unlock(obj); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 9c7402ce5bf9..11f734fea3ab 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -1297,7 +1297,9 @@ static int __igt_mmap_revoke(struct drm_i915_private *i915, } if (type != I915_MMAP_TYPE_GTT) { + i915_gem_object_lock(obj); __i915_gem_object_put_pages(obj); + i915_gem_object_unlock(obj); if (i915_gem_object_has_pages(obj)) { pr_err("Failed to put-pages object!\n"); err = -EINVAL; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e998f25f30a3..0fbe438c4523 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -335,12 +335,16 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj, u64 remain; int ret; + i915_gem_object_lock(obj); ret = i915_gem_object_prepare_read(obj, &needs_clflush); - if (ret) + if (ret) { + i915_gem_object_unlock(obj); return ret; + } fence = i915_gem_object_lock_fence(obj); i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); if (!fence) return -ENOMEM; @@ -734,12 +738,16 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, u64 remain; int ret; + i915_gem_object_lock(obj); ret = i915_gem_object_prepare_write(obj, &needs_clflush); - if (ret) + if (ret) { + i915_gem_object_unlock(obj); return ret; + } fence = i915_gem_object_lock_fence(obj); i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); if (!fence) return -ENOMEM; @@ -1063,7 +1071,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data, if (!obj) return -ENOENT; - err = mutex_lock_interruptible(&obj->mm.lock); + err = i915_gem_object_lock_interruptible(obj); if (err) goto out; @@ -1109,7 +1117,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data, i915_gem_object_truncate(obj); args->retained = obj->mm.madv != __I915_MADV_PURGED; - mutex_unlock(&obj->mm.lock); + i915_gem_object_unlock(obj); out: i915_gem_object_put(obj); diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c index 6e80d99048e4..8d9fdf591514 100644 --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c @@ -24,6 +24,15 @@ #include "selftests/igt_flush_test.h" #include "selftests/i915_random.h" +static void close_object(struct drm_i915_gem_object *obj) +{ + i915_gem_object_lock(obj); + __i915_gem_object_put_pages(obj); + i915_gem_object_unlock(obj); + + i915_gem_object_put(obj); +} + static void close_objects(struct intel_memory_region *mem, struct list_head *objects) { @@ -33,10 +42,9 @@ static void close_objects(struct intel_memory_region *mem, list_for_each_entry_safe(obj, on, objects, st_link) { if (i915_gem_object_has_pinned_pages(obj)) i915_gem_object_unpin_pages(obj); - /* No polluting the memory region between tests */ - __i915_gem_object_put_pages(obj); list_del(&obj->st_link); - i915_gem_object_put(obj); + /* No polluting the memory region between tests */ + close_object(obj); } cond_resched(); @@ -124,9 +132,8 @@ igt_object_create(struct intel_memory_region *mem, static void igt_object_release(struct drm_i915_gem_object *obj) { i915_gem_object_unpin_pages(obj); - __i915_gem_object_put_pages(obj); list_del(&obj->st_link); - i915_gem_object_put(obj); + close_object(obj); } static int igt_mock_contiguous(void *arg) -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 22 09:59:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:59:20 +0100 Subject: [Intel-gfx] [PATCH 6/7] drm/i915/gem: Break apart the early i915_vma_pin from execbuf object lookup In-Reply-To: <20200622095921.15530-1-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> Message-ID: <20200622095921.15530-6-chris@chris-wilson.co.uk> As a prelude to the next step where we want to perform all the object allocations together under the same lock, we first must delay the i915_vma_pin() as that implicitly does the allocations for us, one by one. As it only does the allocations one by one, it is not allowed to wait/evict, whereas pulling all the allocations together the entire set can be scheduled as one. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 43 +++++++++++-------- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 60926209b1fc..46fcbdf8161c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -664,16 +664,6 @@ eb_add_vma(struct i915_execbuffer *eb, eb->lut_size)]); } - if (eb_pin_vma(eb, entry, ev)) { - if (entry->offset != vma->node.start) { - entry->offset = vma->node.start | UPDATE; - eb->args->flags |= __EXEC_HAS_RELOC; - } - } else { - eb_unreserve_vma(ev); - list_add_tail(&ev->bind_link, &eb->unbound); - } - list_add_tail(&ev->lock_link, &eb->lock); } @@ -1339,18 +1329,37 @@ static int eb_prepare_vma(struct eb_vma *ev) return 0; } -static int eb_reserve(struct i915_execbuffer *eb) +static int eb_reserve_vm(struct i915_execbuffer *eb) { const unsigned int count = eb->buffer_count; struct i915_address_space *vm = eb->context->vm; - struct list_head last; unsigned int i, pass; - struct eb_vma *ev; int err = 0; + for (i = 0; i < count; i++) { + struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; + struct eb_vma *ev = &eb->vma[i]; + + if (eb_pin_vma(eb, entry, ev)) { + struct i915_vma *vma = ev->vma; + + if (entry->offset != vma->node.start) { + entry->offset = vma->node.start | UPDATE; + eb->args->flags |= __EXEC_HAS_RELOC; + } + } else { + eb_unreserve_vma(ev); + list_add_tail(&ev->bind_link, &eb->unbound); + } + } + if (list_empty(&eb->unbound)) + return 0; + pass = 0; do { struct eb_vm_work *work; + struct list_head last; + struct eb_vma *ev; list_for_each_entry(ev, &eb->unbound, bind_link) { err = eb_prepare_vma(ev); @@ -2404,11 +2413,9 @@ static int eb_relocate(struct i915_execbuffer *eb) if (err) return err; - if (!list_empty(&eb->unbound)) { - err = eb_reserve(eb); - if (err) - return err; - } + err = eb_reserve_vm(eb); + if (err) + return err; /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 22 09:59:18 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:59:18 +0100 Subject: [Intel-gfx] [PATCH 4/7] drm/i915: Update vma to use async page allocations In-Reply-To: <20200622095921.15530-1-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> Message-ID: <20200622095921.15530-4-chris@chris-wilson.co.uk> Since we have asynchronous vma bindings, we are ready to utilise asynchronous page allocations. All we have to do is ask for the get_pages not to wait on our behalf, as our workqueue will. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 + drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 + drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +- drivers/gpu/drm/i915/i915_vma.c | 42 +++++++++---------- drivers/gpu/drm/i915/i915_vma_types.h | 1 + 5 files changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 678e7f82f6c9..59750edd617f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -699,6 +699,8 @@ static int set_bind_fence(struct i915_vma *vma, struct eb_vm_work *work) lockdep_assert_held(&vma->vm->mutex); prev = i915_active_set_exclusive(&vma->active, &work->base.dma); + if (!prev) + prev = i915_active_fence_get(&vma->obj->mm.active.excl); if (unlikely(prev)) { err = i915_sw_fence_await_dma_fence(&work->base.chain, prev, 0, GFP_NOWAIT | __GFP_NOWARN); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 03a1b859aeef..3bb0939dce99 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -275,6 +275,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, struct sg_table *pages, unsigned int sg_page_sizes); +int ____i915_gem_object_get_pages_async(struct drm_i915_gem_object *obj); int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj); int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); int __i915_gem_object_get_pages_locked(struct drm_i915_gem_object *obj); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index d0cdf1c93a67..4efd1aeedc2d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -95,7 +95,7 @@ static int __i915_gem_object_wait_for_pages(struct drm_i915_gem_object *obj) return 0; } -static int ____i915_gem_object_get_pages_async(struct drm_i915_gem_object *obj) +int ____i915_gem_object_get_pages_async(struct drm_i915_gem_object *obj) { int err; diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index dc656c7d3191..dc8fdb656e8b 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -123,6 +123,7 @@ vma_create(struct drm_i915_gem_object *obj, vma->display_alignment = I915_GTT_MIN_ALIGNMENT; i915_active_init(&vma->active, __i915_vma_active, __i915_vma_retire); + vma->fence_context = dma_fence_context_alloc(1); /* Declare ourselves safe for use inside shrinkers */ if (IS_ENABLED(CONFIG_LOCKDEP)) { @@ -295,7 +296,6 @@ i915_vma_instance(struct drm_i915_gem_object *obj, struct i915_vma_work { struct dma_fence_work base; struct i915_vma *vma; - struct drm_i915_gem_object *pinned; struct i915_sw_dma_fence_cb cb; enum i915_cache_level cache_level; unsigned int flags; @@ -331,9 +331,6 @@ static int __vma_bind(struct dma_fence_work *work) static void __vma_release(struct dma_fence_work *work) { struct i915_vma_work *vw = container_of(work, typeof(*vw), base); - - if (vw->pinned) - __i915_gem_object_unpin_pages(vw->pinned); } static const struct dma_fence_work_ops bind_ops = { @@ -444,6 +441,8 @@ int i915_vma_bind(struct i915_vma *vma, * execution and not content or object's backing store lifetime. */ prev = i915_active_set_exclusive(&vma->active, &work->base.dma); + if (!prev && vma->obj) + prev = i915_active_fence_get(&vma->obj->mm.active.excl); if (prev) { __i915_sw_fence_await_dma_fence(&work->base.chain, prev, @@ -453,11 +452,6 @@ int i915_vma_bind(struct i915_vma *vma, work->base.dma.error = 0; /* enable the queue_work() */ - if (vma->obj) { - __i915_gem_object_pin_pages(vma->obj); - work->pinned = vma->obj; - } - atomic_or(bind_flags, &vma->flags); return 0; } @@ -826,20 +820,27 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (try_qad_pin(vma, flags & I915_VMA_BIND_MASK)) return 0; - if (vma->obj) { - err = i915_gem_object_pin_pages(vma->obj); - if (err) - return err; - } - err = __wait_for_unbind(vma, flags); if (err) - goto err_pages; + return err; work = i915_vma_work(); - if (!work) { - err = -ENOMEM; - goto err_pages; + if (!work) + return -ENOMEM; + + if (vma->obj) { + if (dma_resv_lock_interruptible(vma->resv, NULL)) + return -EINTR; + + err = ____i915_gem_object_get_pages_async(vma->obj); + if (err == 0) { + err = i915_active_ref(&vma->obj->mm.active, + vma->fence_context, + &work->base.dma); + } + dma_resv_unlock(vma->resv); + if (err) + return err; } if (flags & PIN_GLOBAL) @@ -934,9 +935,6 @@ int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) dma_fence_work_commit_imm(&work->base); if (wakeref) intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref); -err_pages: - if (vma->obj) - i915_gem_object_unpin_pages(vma->obj); return err; } diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h index 02c1640bb034..10757319c2a4 100644 --- a/drivers/gpu/drm/i915/i915_vma_types.h +++ b/drivers/gpu/drm/i915/i915_vma_types.h @@ -250,6 +250,7 @@ struct i915_vma { #define I915_VMA_GGTT_WRITE ((int)BIT(I915_VMA_GGTT_WRITE_BIT)) struct i915_active active; + u64 fence_context; /** * Support different GGTT views into the same object. -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 22 09:59:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:59:17 +0100 Subject: [Intel-gfx] [PATCH 3/7] drm/i915/gem: Track the fences for object allocations In-Reply-To: <20200622095921.15530-1-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> Message-ID: <20200622095921.15530-3-chris@chris-wilson.co.uk> While often the allocation fence is a part of the implicit fences used for accessing the object, we also want to identify the pages allocation fence individually as different stages of the pipeline will want to only be queued for the pages. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_object.c | 23 +++++++++ .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 + drivers/gpu/drm/i915/gem/i915_gem_pages.c | 50 ++++++++++++++++--- drivers/gpu/drm/i915/i915_active.c | 18 +++++++ drivers/gpu/drm/i915/i915_active.h | 7 +++ 5 files changed, 93 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index 37b3fb0eb943..b7fc0da239f5 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -26,6 +26,7 @@ #include "display/intel_frontbuffer.h" #include "gt/intel_gt.h" +#include "i915_active.h" #include "i915_drv.h" #include "i915_gem_clflush.h" #include "i915_gem_context.h" @@ -49,6 +50,24 @@ void i915_gem_object_free(struct drm_i915_gem_object *obj) return kmem_cache_free(global.slab_objects, obj); } +static int i915_mm_active(struct i915_active *ref) +{ + struct drm_i915_gem_object *obj = + container_of(ref, typeof(*obj), mm.active); + + i915_gem_object_get(obj); + return 0; +} + +__i915_active_call +static void i915_mm_retire(struct i915_active *ref) +{ + struct drm_i915_gem_object *obj = + container_of(ref, typeof(*obj), mm.active); + + i915_gem_object_put(obj); +} + void i915_gem_object_init(struct drm_i915_gem_object *obj, const struct drm_i915_gem_object_ops *ops, struct lock_class_key *key) @@ -70,6 +89,8 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, obj->mm.madv = I915_MADV_WILLNEED; INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); mutex_init(&obj->mm.get_page.lock); + + i915_active_init(&obj->mm.active, i915_mm_active, i915_mm_retire); } /** @@ -149,6 +170,8 @@ static void __i915_gem_free_object_rcu(struct rcu_head *head) container_of(head, typeof(*obj), rcu); struct drm_i915_private *i915 = to_i915(obj->base.dev); + i915_active_fini(&obj->mm.active); + dma_resv_fini(&obj->base._resv); i915_gem_object_free(obj); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index dbb33aac7828..668b249fd109 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -189,6 +189,8 @@ struct drm_i915_gem_object { atomic_t pages_pin_count; atomic_t shrink_pin; + struct i915_active active; + /** * Memory region for this object. */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 2ff1036ef91f..d0cdf1c93a67 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -81,25 +81,59 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, } } -int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) +static int __i915_gem_object_wait_for_pages(struct drm_i915_gem_object *obj) +{ + int err; + + err = i915_active_wait_for_exclusive(&obj->mm.active); + if (err) + return err; + + if (IS_ERR(obj->mm.pages)) + return PTR_ERR(obj->mm.pages); + + return 0; +} + +static int ____i915_gem_object_get_pages_async(struct drm_i915_gem_object *obj) { - struct drm_i915_private *i915 = to_i915(obj->base.dev); int err; assert_object_held(obj); + if (i915_active_has_exclusive(&obj->mm.active)) + return 0; + + if (i915_gem_object_has_pages(obj)) + return PTR_ERR_OR_ZERO(obj->mm.pages); + if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { - drm_dbg(&i915->drm, + drm_dbg(obj->base.dev, "Attempting to obtain a purgeable object\n"); return -EFAULT; } + err = i915_active_acquire(&obj->mm.active); + if (err) + return err; + err = obj->ops->get_pages(obj); - GEM_BUG_ON(!err && !i915_gem_object_has_pages(obj)); + i915_active_release(&obj->mm.active); return err; } +int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) +{ + int err; + + err = ____i915_gem_object_get_pages_async(obj); + if (err) + return err; + + return __i915_gem_object_wait_for_pages(obj); +} + /* Ensure that the associated pages are gathered from the backing storage * and pinned into our object. i915_gem_object_pin_pages() may be called * multiple times before they are released by a single call to @@ -203,14 +237,16 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) int __i915_gem_object_put_pages(struct drm_i915_gem_object *obj) { struct sg_table *pages; + int err; /* May be called by shrinker from within get_pages() (on another bo) */ assert_object_held(obj); - if (i915_gem_object_has_pinned_pages(obj)) - return -EBUSY; + err = i915_active_wait(&obj->mm.active); + if (err) + return err; - if (unlikely(atomic_read(&obj->mm.pages_pin_count))) + if (i915_gem_object_has_pinned_pages(obj)) return -EBUSY; i915_gem_object_release_mmap_offset(obj); diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c index 3f595446fd44..886685d6e1e2 100644 --- a/drivers/gpu/drm/i915/i915_active.c +++ b/drivers/gpu/drm/i915/i915_active.c @@ -1073,6 +1073,24 @@ int i915_active_fence_set(struct i915_active_fence *active, return err; } +int i915_active_fence_wait(struct i915_active_fence *active) +{ + struct dma_fence *fence; + int err; + + if (GEM_WARN_ON(is_barrier(active))) + return -EBUSY; + + fence = i915_active_fence_get(active); + if (!fence) + return 0; + + err = dma_fence_wait(fence, true); + dma_fence_put(fence); + + return err; +} + void i915_active_noop(struct dma_fence *fence, struct dma_fence_cb *cb) { active_fence_cb(fence, cb); diff --git a/drivers/gpu/drm/i915/i915_active.h b/drivers/gpu/drm/i915/i915_active.h index 2e0bcb3289ec..eefcc2344509 100644 --- a/drivers/gpu/drm/i915/i915_active.h +++ b/drivers/gpu/drm/i915/i915_active.h @@ -123,6 +123,8 @@ i915_active_fence_isset(const struct i915_active_fence *active) return rcu_access_pointer(active->fence); } +int i915_active_fence_wait(struct i915_active_fence *active); + /* * GPU activity tracking * @@ -191,6 +193,11 @@ static inline int i915_active_wait(struct i915_active *ref) return __i915_active_wait(ref, TASK_INTERRUPTIBLE); } +static inline int i915_active_wait_for_exclusive(struct i915_active *ref) +{ + return i915_active_fence_wait(&ref->excl); +} + int i915_sw_fence_await_active(struct i915_sw_fence *fence, struct i915_active *ref, unsigned int flags); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 22 09:59:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:59:21 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <20200622095921.15530-1-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> Message-ID: <20200622095921.15530-7-chris@chris-wilson.co.uk> In order to actually handle eviction and what not, we need to process all the objects together under a common lock, reservation_ww_class. As such, do a memory reservation pass after looking up the object/vma, which then feeds into the rest of execbuf [relocation, cmdparsing, flushing and ofc execution]. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- 1 file changed, 70 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 46fcbdf8161c..8db2e013465f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -53,10 +53,9 @@ struct eb_vma_array { #define __EXEC_OBJECT_HAS_PIN BIT(31) #define __EXEC_OBJECT_HAS_FENCE BIT(30) -#define __EXEC_OBJECT_HAS_PAGES BIT(29) -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ #define __EXEC_HAS_RELOC BIT(31) #define __EXEC_INTERNAL_FLAGS (~0u << 31) @@ -241,6 +240,8 @@ struct i915_execbuffer { struct intel_context *context; /* logical state for the request */ struct i915_gem_context *gem_context; /** caller's context */ + struct dma_fence *mm_fence; + struct i915_request *request; /** our request to build */ struct eb_vma *batch; /** identity of the batch obj/vma */ struct i915_vma *trampoline; /** trampoline used for chaining */ @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) if (ev->flags & __EXEC_OBJECT_HAS_PIN) __i915_vma_unpin(vma); - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) - i915_gem_object_unpin_pages(vma->obj); - - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | - __EXEC_OBJECT_HAS_FENCE | - __EXEC_OBJECT_HAS_PAGES); + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); } static void eb_vma_array_destroy(struct kref *kref) @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, list_add_tail(&ev->lock_link, &eb->lock); } +static int eb_vma_get_pages(struct i915_execbuffer *eb, + struct eb_vma *ev, + u64 idx) +{ + struct i915_vma *vma = ev->vma; + int err; + + /* XXX also preallocate PD for vma */ + + err = ____i915_gem_object_get_pages_async(vma->obj); + if (err) + return err; + + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); +} + +static int eb_reserve_mm(struct i915_execbuffer *eb) +{ + const u64 idx = eb->context->timeline->fence_context; + struct ww_acquire_ctx acquire; + struct eb_vma *ev; + int err; + + eb->mm_fence = __dma_fence_create_proxy(0, 0); + if (!eb->mm_fence) + return -ENOMEM; + + ww_acquire_init(&acquire, &reservation_ww_class); + + err = eb_lock_vma(eb, &acquire); + if (err) + goto out; + + ww_acquire_done(&acquire); + + list_for_each_entry(ev, &eb->lock, lock_link) { + struct i915_vma *vma = ev->vma; + + if (err == 0) + err = eb_vma_get_pages(eb, ev, idx); + + i915_vma_unlock(vma); + } + +out: + ww_acquire_fini(&acquire); + return err; +} + struct eb_vm_work { struct dma_fence_work base; struct list_head unbound; @@ -1312,20 +1357,9 @@ static int eb_vm_throttle(struct eb_vm_work *work) static int eb_prepare_vma(struct eb_vma *ev) { - struct i915_vma *vma = ev->vma; - int err; - ev->hole.flags = 0; ev->bind_flags = 0; - if (!(ev->flags & __EXEC_OBJECT_HAS_PAGES)) { - err = i915_gem_object_pin_pages(vma->obj); - if (err) - return err; - - ev->flags |= __EXEC_OBJECT_HAS_PAGES; - } - return 0; } @@ -2413,6 +2447,10 @@ static int eb_relocate(struct i915_execbuffer *eb) if (err) return err; + err = eb_reserve_mm(eb); + if (err) + return err; + err = eb_reserve_vm(eb); if (err) return err; @@ -2844,6 +2882,12 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) { int err; + if (eb->mm_fence) { + dma_fence_proxy_set_real(eb->mm_fence, &eb->request->fence); + dma_fence_put(eb->mm_fence); + eb->mm_fence = NULL; + } + if (eb->reloc_cache.fence) { err = i915_request_await_dma_fence(eb->request, &eb->reloc_cache.rq->fence); @@ -3339,6 +3383,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.batch_start_offset = args->batch_start_offset; eb.batch_len = args->batch_len; eb.trampoline = NULL; + eb.mm_fence = NULL; eb.batch_flags = 0; if (args->flags & I915_EXEC_SECURE) { @@ -3533,6 +3578,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb_reloc_signal(&eb, eb.reloc_cache.rq); if (eb.trampoline) i915_vma_unpin(eb.trampoline); + if (eb.mm_fence) { + dma_fence_signal(eb.mm_fence); + dma_fence_put(eb.mm_fence); + } eb_unpin_engine(&eb); err_context: i915_gem_context_put(eb.gem_context); -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 22 09:59:19 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 10:59:19 +0100 Subject: [Intel-gfx] [PATCH 5/7] drm/i915/gem: Convert the userptr-worker to use a fence In-Reply-To: <20200622095921.15530-1-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> Message-ID: <20200622095921.15530-5-chris@chris-wilson.co.uk> Now that we have fence tracking in place for object allocations, we can remove the haphazard polling over a workqueue used for asynchronous userptr allocations. All consumers will now wait for the fence notification instead of leaking EAGAIN back to userspace. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 5 - .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 - drivers/gpu/drm/i915/gem/i915_gem_pages.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 136 ++++++++---------- drivers/gpu/drm/i915/i915_drv.h | 9 +- drivers/gpu/drm/i915/i915_gem.c | 4 +- 6 files changed, 66 insertions(+), 95 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 59750edd617f..60926209b1fc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1456,11 +1456,6 @@ static int eb_reserve(struct i915_execbuffer *eb) if (signal_pending(current)) return -EINTR; - if (err == -EAGAIN) { - flush_workqueue(eb->i915->mm.userptr_wq); - continue; - } - /* Now safe to wait with no reservations held */ list_for_each_entry(ev, &eb->unbound, bind_link) { struct i915_vma *vma = ev->vma; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 668b249fd109..17a47186ba81 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -278,7 +278,6 @@ struct drm_i915_gem_object { struct i915_mm_struct *mm; struct i915_mmu_object *mmu_object; - struct work_struct *work; } userptr; unsigned long scratch; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 4efd1aeedc2d..99f50c9d0ed6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -18,8 +18,6 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, unsigned long supported = INTEL_INFO(i915)->page_sizes; int i; - assert_object_held(obj); - if (i915_gem_object_is_volatile(obj)) obj->mm.madv = I915_MADV_DONTNEED; @@ -34,8 +32,6 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, obj->mm.get_page.sg_pos = pages->sgl; obj->mm.get_page.sg_idx = 0; - obj->mm.pages = pages; - if (i915_gem_object_is_tiled(obj) && i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) { GEM_BUG_ON(obj->mm.quirked); @@ -61,6 +57,8 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, } GEM_BUG_ON(!HAS_PAGE_SIZES(i915, obj->mm.page_sizes.sg)); + WRITE_ONCE(obj->mm.pages, pages); + if (i915_gem_object_is_shrinkable(obj)) { struct list_head *list; unsigned long flags; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index 4cd79f425eac..a236df02bc44 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -14,6 +14,7 @@ #include "i915_gem_ioctls.h" #include "i915_gem_object.h" #include "i915_scatterlist.h" +#include "i915_sw_fence_work.h" struct i915_mm_struct { struct mm_struct *mm; @@ -398,7 +399,7 @@ i915_gem_userptr_release__mm_struct(struct drm_i915_gem_object *obj) } struct get_pages_work { - struct work_struct work; + struct dma_fence_work base; struct drm_i915_gem_object *obj; struct task_struct *task; }; @@ -446,12 +447,12 @@ __i915_gem_userptr_alloc_pages(struct drm_i915_gem_object *obj, return st; } -static void -__i915_gem_userptr_get_pages_worker(struct work_struct *_work) +static int gup_work(struct dma_fence_work *base) { - struct get_pages_work *work = container_of(_work, typeof(*work), work); - struct drm_i915_gem_object *obj = work->obj; + struct get_pages_work *gup = container_of(base, typeof(*gup), base); + struct drm_i915_gem_object *obj = gup->obj; const unsigned long npages = obj->base.size >> PAGE_SHIFT; + struct sg_table *pages; unsigned long pinned; struct page **pvec; int ret; @@ -476,7 +477,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) locked = 1; } ret = pin_user_pages_remote - (work->task, mm, + (gup->task, mm, obj->userptr.ptr + pinned * PAGE_SIZE, npages - pinned, flags, @@ -492,37 +493,41 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) } } - i915_gem_object_lock(obj); - if (obj->userptr.work == &work->work) { - struct sg_table *pages = ERR_PTR(ret); - - if (pinned == npages) { - pages = __i915_gem_userptr_alloc_pages(obj, pvec, - npages); - if (!IS_ERR(pages)) { - pinned = 0; - pages = NULL; - } + if (pinned == npages) { + pages = __i915_gem_userptr_alloc_pages(obj, pvec, npages); + if (!IS_ERR(pages)) { + pinned = 0; + pages = NULL; } - - obj->userptr.work = ERR_CAST(pages); - if (IS_ERR(pages)) - __i915_gem_userptr_set_active(obj, false); + } else { + pages = ERR_PTR(ret); } - i915_gem_object_unlock(obj); + if (IS_ERR(pages)) + __i915_gem_userptr_set_active(obj, false); unpin_user_pages(pvec, pinned); kvfree(pvec); - i915_gem_object_put(obj); - put_task_struct(work->task); - kfree(work); + return PTR_ERR_OR_ZERO(pages); } -static struct sg_table * +static void gup_release(struct dma_fence_work *base) +{ + struct get_pages_work *gup = container_of(base, typeof(*gup), base); + + put_task_struct(gup->task); +} + +static const struct dma_fence_work_ops gup_ops = { + .name = "userptr-getpages", + .work = gup_work, + .release = gup_release, +}; + +static bool __i915_gem_userptr_get_pages_schedule(struct drm_i915_gem_object *obj) { - struct get_pages_work *work; + struct get_pages_work *gup; /* Spawn a worker so that we can acquire the * user pages without holding our mutex. Access @@ -543,21 +548,21 @@ __i915_gem_userptr_get_pages_schedule(struct drm_i915_gem_object *obj) * that error back to this function through * obj->userptr.work = ERR_PTR. */ - work = kmalloc(sizeof(*work), GFP_KERNEL); - if (work == NULL) - return ERR_PTR(-ENOMEM); - - obj->userptr.work = &work->work; + gup = kmalloc(sizeof(*gup), GFP_KERNEL); + if (!gup) + return false; - work->obj = i915_gem_object_get(obj); + dma_fence_work_init(&gup->base, &gup_ops); - work->task = current; - get_task_struct(work->task); + gup->obj = obj; + i915_active_set_exclusive(&obj->mm.active, &gup->base.dma); - INIT_WORK(&work->work, __i915_gem_userptr_get_pages_worker); - queue_work(to_i915(obj->base.dev)->mm.userptr_wq, &work->work); + gup->task = current; + get_task_struct(gup->task); - return ERR_PTR(-EAGAIN); + dma_resv_add_excl_fence(obj->base.resv, &gup->base.dma); + dma_fence_work_commit(&gup->base); + return true; } static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) @@ -566,7 +571,6 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) struct mm_struct *mm = obj->userptr.mm->mm; struct page **pvec; struct sg_table *pages; - bool active; int pinned; unsigned int gup_flags = 0; @@ -587,14 +591,6 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) * egregious cases from causing harm. */ - if (obj->userptr.work) { - /* active flag should still be held for the pending work */ - if (IS_ERR(obj->userptr.work)) - return PTR_ERR(obj->userptr.work); - else - return -EAGAIN; - } - pvec = NULL; pinned = 0; @@ -618,28 +614,31 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) pinned = pin_user_pages_fast_only(obj->userptr.ptr, num_pages, gup_flags, pvec); + if (pinned < 0) + goto out; } } - active = false; - if (pinned < 0) { - pages = ERR_PTR(pinned); - pinned = 0; - } else if (pinned < num_pages) { - pages = __i915_gem_userptr_get_pages_schedule(obj); - active = pages == ERR_PTR(-EAGAIN); - } else { + if (pinned == num_pages) { pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages); - active = !IS_ERR(pages); + if (IS_ERR(pages)) { + unpin_user_pages(pvec, pinned); + pinned = PTR_ERR(pages); + goto out; + } + } else { + unpin_user_pages(pvec, pinned); + if (!__i915_gem_userptr_get_pages_schedule(obj)) { + pinned = -ENOMEM; + goto out; + } } - if (active) - __i915_gem_userptr_set_active(obj, true); + __i915_gem_userptr_set_active(obj, true); + pinned = 0; - if (IS_ERR(pages)) - unpin_user_pages(pvec, pinned); +out: kvfree(pvec); - - return PTR_ERR_OR_ZERO(pages); + return pinned; } static void @@ -650,7 +649,6 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj, struct page *page; /* Cancel any inflight work and force them to restart their gup */ - obj->userptr.work = NULL; __i915_gem_userptr_set_active(obj, false); if (!pages) return; @@ -853,22 +851,12 @@ i915_gem_userptr_ioctl(struct drm_device *dev, return 0; } -int i915_gem_init_userptr(struct drm_i915_private *dev_priv) +void i915_gem_init_userptr(struct drm_i915_private *dev_priv) { spin_lock_init(&dev_priv->mm_lock); hash_init(dev_priv->mm_structs); - - dev_priv->mm.userptr_wq = - alloc_workqueue("i915-userptr-acquire", - WQ_HIGHPRI | WQ_UNBOUND, - 0); - if (!dev_priv->mm.userptr_wq) - return -ENOMEM; - - return 0; } void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv) { - destroy_workqueue(dev_priv->mm.userptr_wq); } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 072b1e19d86a..85c11912288a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -604,13 +604,6 @@ struct i915_gem_mm { struct notifier_block vmap_notifier; struct shrinker shrinker; - /** - * Workqueue to fault in userptr pages, flushed by the execbuf - * when required but otherwise left to userspace to try again - * on EAGAIN. - */ - struct workqueue_struct *userptr_wq; - /* shrinker accounting, also useful for userland debugging */ u64 shrink_memory; u32 shrink_count; @@ -1724,7 +1717,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); /* i915_gem.c */ -int i915_gem_init_userptr(struct drm_i915_private *dev_priv); +void i915_gem_init_userptr(struct drm_i915_private *dev_priv); void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); void i915_gem_init_early(struct drm_i915_private *dev_priv); void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0fbe438c4523..f886a98dc2ae 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1133,9 +1133,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv) mkwrite_device_info(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K; - ret = i915_gem_init_userptr(dev_priv); - if (ret) - return ret; + i915_gem_init_userptr(dev_priv); intel_uc_fetch_firmwares(&dev_priv->gt.uc); intel_wopcm_init(&dev_priv->wopcm); -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 22 10:11:27 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 10:11:27 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBk?= =?utf-8?q?ma-fence_lockdep_annotations=2C_round_2_=28rev7=29?= In-Reply-To: <20200604081224.863494-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> Message-ID: <159282068757.9208.12477325334464859954@emeril.freedesktop.org> == Series Details == Series: dma-fence lockdep annotations, round 2 (rev7) URL : https://patchwork.freedesktop.org/series/77986/ State : failure == Summary == Applying: mm: Track mmu notifiers in fs_reclaim_acquire/release error: sha1 information is lacking or useless (mm/page_alloc.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 mm: Track mmu notifiers in fs_reclaim_acquire/release When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Mon Jun 22 10:17:34 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 10:17:34 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_VRR_capable_attach_prop_in_i915=2C_VRR_debugfs?= In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <159282105471.9207.891544069521529567@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, VRR debugfs URL : https://patchwork.freedesktop.org/series/78670/ State : warning == Summary == $ dim checkpatch origin/drm-tip 383b031f7157 drm/i915/dp: Attach and set drm connector VRR property 5d20cfadedc4 drm/debug: Expose connector VRR monitor range via debugfs -:38: WARNING:TYPO_SPELLING: 'Seperate' may be misspelled - perhaps 'Separate'? #38: * Seperate patch for removal of AMD specific logic (Manasi) -:82: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. #82: FILE: drivers/gpu/drm/drm_debugfs.c:436: + debugfs_create_file("vrr_range", S_IRUGO, root, connector, total: 0 errors, 2 warnings, 0 checks, 34 lines checked 6206d3194afb Revert "drm/amd/display: Expose connector VRR range via debugfs" From patchwork at emeril.freedesktop.org Mon Jun 22 10:18:16 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 10:18:16 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?VRR_capable_attach_prop_in_i915=2C_VRR_debugfs?= In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <159282109687.9210.1465675744602820526@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, VRR debugfs URL : https://patchwork.freedesktop.org/series/78670/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1171:46: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1151:46: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement From pavel at ucw.cz Mon Jun 22 10:21:05 2020 From: pavel at ucw.cz (Pavel Machek) Date: Mon, 22 Jun 2020 12:21:05 +0200 Subject: [Intel-gfx] v5.8-rc1 on thinkpad x220, intel graphics: interface frozen, can still switch to text console In-Reply-To: <159281719363.11575.10607533427539631904@build.alporthouse.com> References: <20200622085258.GA22686@duo.ucw.cz> <159281719363.11575.10607533427539631904@build.alporthouse.com> Message-ID: <20200622102105.GA6353@duo.ucw.cz> On Mon 2020-06-22 10:13:13, Chris Wilson wrote: > Quoting Pavel Machek (2020-06-22 09:52:59) > > Hi! > > > > Linux duo 5.8.0-rc1+ #117 SMP PREEMPT Mon Jun 15 16:13:54 CEST 2020 x86_64 GNU/Linux > > > > [133747.719711] [ 17456] 0 17456 4166 271 65536 0 0 sshd > > [133747.719718] [ 17466] 1000 17466 4166 289 65536 0 0 sshd > > [133747.719724] [ 17468] 1000 17468 433587 303033 2588672 0 0 unison > > [133747.719730] [ 18023] 1000 18023 1316 16 40960 0 0 sleep > > [133747.719737] oom-kill:constraint=CONSTRAINT_NONE,nodemask=(null),task=chromium,pid=27368,uid=1000 > > [133747.719795] Out of memory: Killed process 27368 (chromium) total-vm:6686908kB, anon-rss:647056kB, file-rss:0kB, shmem-rss:7452kB, UID:1000 pgtables:5304kB oom_score_adj:300 > > [133747.799893] oom_reaper: reaped process 27368 (chromium), now anon-rss:0kB, file-rss:0kB, shmem-rss:6836kB > > [136841.820558] i915 0000:00:02.0: [drm] Resetting chip for stopped heartbeat on rcs0 > > [136841.924333] i915 0000:00:02.0: [drm] Xorg[3016] context reset due > > to GPU hang > > If that was the first occurrence it would have pointed to the error > state containing more information on the cause of the hang. > Attach /sys/class/drm/card0/error I rebooted in the meantime (I need this machine). I updated to 5.8-rc2, let me see if it appears again. Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 195 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200622/1c91cebf/attachment.sig> From patchwork at emeril.freedesktop.org Mon Jun 22 10:45:44 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 10:45:44 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBz?= =?utf-8?q?eries_starting_with_=5B1/7=5D_drm/i915/gem=3A_Replace_i915=5Fge?= =?utf-8?q?m=5Fobject=2Emm=2Emutex_with_reservation=5Fww=5Fclass?= In-Reply-To: <20200622095921.15530-1-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> Message-ID: <159282274429.9210.7722654468787899519@emeril.freedesktop.org> == Series Details == Series: series starting with [1/7] drm/i915/gem: Replace i915_gem_object.mm.mutex with reservation_ww_class URL : https://patchwork.freedesktop.org/series/78688/ State : failure == Summary == Applying: drm/i915/gem: Replace i915_gem_object.mm.mutex with reservation_ww_class Applying: drm/i915: Reuse the reservation_ww_class for acquiring vma backing storage error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0002 drm/i915: Reuse the reservation_ww_class for acquiring vma backing storage When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Mon Jun 22 10:47:36 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 10:47:36 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgVlJS?= =?utf-8?q?_capable_attach_prop_in_i915=2C_VRR_debugfs?= In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <159282285636.9210.15410265025014736951@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, VRR debugfs URL : https://patchwork.freedesktop.org/series/78670/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8650 -> Patchwork_18002 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18002 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18002, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18002/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18002: ### IGT changes ### #### Possible regressions #### * igt at kms_chamelium@dp-hpd-fast: - fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8650/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18002/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html Known issues ------------ Here are the changes found in Patchwork_18002 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8650/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18002/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8650/fi-tgl-u2/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18002/fi-tgl-u2/igt at i915_module_load@reload.html #### Possible fixes #### * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [INCOMPLETE][7] ([i915#1932]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8650/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18002/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][9] ([i915#402]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8650/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18002/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 10) ------------------------------ ERROR: It appears as if the changes made in Patchwork_18002 prevented too many machines from booting. Additional (1): fi-pnv-d510 Missing (35): fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc fi-snb-2520m fi-icl-y fi-byt-n2820 fi-icl-dsi fi-icl-guc fi-skl-6600u fi-snb-2600 fi-bxt-dsi fi-cml-s fi-bsw-n3050 fi-byt-j1900 fi-glk-dsi fi-ctg-p8600 fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-kbl-7560u fi-bsw-nick fi-ilk-m540 fi-ehl-1 fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-whl-u fi-kbl-x1275 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8650 -> Patchwork_18002 CI-20190529: 20190529 CI_DRM_8650: 24b806b0a1dd38c734e771ece9dd1ab6492bbb96 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5714: f0ade50caf38574592886f55bb03cf80c574bb83 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18002: 6206d3194afbfc3b06d9b9436c799126ece2cdb0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6206d3194afb Revert "drm/amd/display: Expose connector VRR range via debugfs" 5d20cfadedc4 drm/debug: Expose connector VRR monitor range via debugfs 383b031f7157 drm/i915/dp: Attach and set drm connector VRR property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18002/index.html From uma.shankar at intel.com Mon Jun 22 11:44:58 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 22 Jun 2020 11:44:58 +0000 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> > > > > -----Original Message----- > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Sent: Thursday, June 11, 2020 9:31 PM > > > > To: Shankar, Uma <uma.shankar at intel.com> > > > > Cc: intel-gfx at lists.freedesktop.org; jani.nikula at linux.intel.com; > > > > Mun, Gwan- gyeong <gwan-gyeong.mun at intel.com> > > > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes > > > > readback for LSPCON > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > This will help align the implementation with state readback > > > > > > infrastructure. > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > ++++++++++++++++++++- > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct > > > > > > intel_encoder > > > > *encoder, > > > > > > buf, ret); > > > > > > } > > > > > > > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > +drm_dp_aux *aux) { > > > > > > + int ret; > > > > > > + u32 val = 0; > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > + > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > + if (ret < 0) { > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > + return false; > > > > > > + } > > > > > > + > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > + return true; > > > > > > + > > > > > > + return false; > > > > > > > > > > return val & ...; > > > > > > > > > > > +} > > > > > > + > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > +drm_dp_aux *aux) { > > > > > > + int ret; > > > > > > + u32 val = 0; > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > + > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > + if (ret < 0) { > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > + return false; > > > > > > + } > > > > > > + > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > + return true; > > > > > > + > > > > > > + return false; > > > > > > +} > > > > > > + > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > > const struct intel_crtc_state *pipe_config) { > > > > > > - /* FIXME actually read this from the hw */ > > > > > > - return 0; > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > > + bool infoframes_enabled; > > > > > > + u32 mask = 0; > > > > > > + u32 val; > > > > > > + > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > + infoframes_enabled = > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > + else > > > > > > + infoframes_enabled = > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); > > > > > > + > > > > > > + if (infoframes_enabled) > > > > > > + return true; > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > Actually since we're dealing with both the LSPCON specific stuff > > > > and DIP stuff for the DRM infoframe I think we should stop using > > > > using intel_hdmi_infoframes_enabled(), and instead provide a > > > > LSPCON specific replacement for it. That way we can directly > > > > return the abstract bitmask instead of pretending to return a bitmask of > the DIP bits. We have DP (VSC etc) packets also managed as HDMI infoframes only. We can keep the same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW for AVI and similarly VIDEO_DIP_ENABLE_GMP_HSW for DRM (HDR metadata). This will help all the helper align appropriately even in the intel_dump_pipe_config. Will fix this accordingly and send the next version. Hope this is ok. > > > Sure, will fix this and resend the next version. > > > > > > > > > > > > > Also my question "how do we turn off infoframes once enabled?" > > > > > from > > > > > https://patchwork.freedesktop.org/patch/351719/?series=72928&rev > > > > > =1 > > > > > still remains unanswered... > > > > > > For the AVI infoframe we generally compute and change the respective > > > values. If no change is requested and computed we can let the > > > existing infoframes be transmitted. AFAIK there is no mechanism > > > called out, to explicitly disable this on Lspcon. Have not seen any > > > issues due to this, so > > hoping that it may be safe even if they are enabled. > > > > It's not valid to transmit infoframes to DVI sinks. > > With your fix, we won't be enabling or setting the infoframe on DVI sinks. > If I understand correctly, we may have issue if we connect HDMI (where we > would have sent the infoframe) and later unplug and plug a DVI sink. With > unplug if Lspcon is not resetting this internally then this will be a problem. I will > try to get this information on Lspcon behavior. Hi Ville, Searched various docs on LSPCON and couldn't find any mention of disabling infoframe. Reached out to few folks who were interfacing with Lspcon vendors and got this finally clarified. The expectation is that LSPCON will reset stuff on unplug and will not send infoframes to DVI sink, so from source side we don't need to explicitly disable them. Lspcon will take care of this, this was tested for compliance as well by them. I will share the updated series adding your patch stopping infoframes to be sent to DVI sinks. Please review the same. Thank & Regards, Uma Shankar > > > > > > I am planning to take your patch from the series and float along > > > with this series, adding check for DRM Infoframes also. Hope that is ok ? > > > > > > Thanks Ville for your feedback. > > > > > > Regards, > > > Uma Shankar > > > > > > > > > + > > > > > > + if (lspcon->hdr_supported) { > > > > > > + val = intel_de_read(dev_priv, > > > > > > + HSW_TVIDEO_DIP_CTL(pipe_config- > > > > >cpu_transcoder)); > > > > > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > > > > > + > > > > > > + if (val & mask) > > > > > > + return val & mask; > > > > > > + } > > > > > > + > > > > > > + return false; > > > > > > } > > > > > > > > > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > > > > > -- > > > > > > 2.22.0 > > > > > > > > > > -- > > > > > Ville Syrj?l? > > > > > Intel > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > > > -- > > Ville Syrj?l? > > Intel From uma.shankar at intel.com Mon Jun 22 13:00:19 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:19 +0530 Subject: [Intel-gfx] [v4 00/10] Enable HDR on MCA LSPCON based Gen9 devices Message-ID: <20200622130029.28667-1-uma.shankar@intel.com> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR support for MCA and Parade LSPCON based GEN9 devices. SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP packets. LSPCON will be set to operate in PCON mode, will receive the metadata and create Dynamic Range and Mastering Infoframe (DRM packets) and send it to HDR capable HDMI sink devices. v2: Fixed Ville's review comments. Suppressed some warnings. Patch 8 of the series is marked "Not for Merge" and is just for reference to userspace people to incorporate in order to support 10bit content with 4K at 60 resolutions. v3: Added Infoframe readout support for DRM infoframes. Addressed Jani Nikula's review comments. v4: Addressed Ville's review comments and added proper bitmask for enabled infoframes. Series also incorporates Ville's patch for stopping infoframes to be sent to DVI sinks. Extended the same for DRM as well. Note: Patch 10 of the series is for reference to userspace, not to be merged to driver. Uma Shankar (9): drm/i915/display: Add HDR Capability detection for LSPCON drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon drm/i915/display: Attach HDR property for capable Gen9 devices drm/i915/display: Enable BT2020 for HDR on LSPCON devices drm/i915/display: Enable HDR for Parade based lspcon drm/i915/display: Implement infoframes readback for LSPCON drm/i915/display: Implement DRM infoframe read for LSPCON drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60 at 10bpp for LSPCON Ville Syrj?l? (1): drm/i915/lspcon: Do not send infoframes to non-HDMI sinks drivers/gpu/drm/i915/display/intel_ddi.c | 20 ++- .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 24 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++ drivers/gpu/drm/i915/display/intel_lspcon.c | 152 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_lspcon.h | 9 +- 6 files changed, 203 insertions(+), 24 deletions(-) -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:21 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:21 +0530 Subject: [Intel-gfx] [v4 02/10] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-3-uma.shankar@intel.com> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR support for MCA LSPCON based GEN9 devices. SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP packets. LSPCON will be set to operate in PCON mode, will receive the metadata and create Dynamic Range and Mastering Infoframe (DRM packets) and send it to HDR capable HDMI sink devices. v2: Re-used hsw infoframe write implementation for HDR metadata for LSPCON as per Ville's suggestion. v3: Addressed Jani Nikula's review comments. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++ drivers/gpu/drm/i915/display/intel_lspcon.c | 37 +++++++++++++++------ drivers/gpu/drm/i915/display/intel_lspcon.h | 5 ++- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a31a98d26882..53103ef72a58 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -590,6 +590,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, return val & mask; } +void lspcon_drm_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len) +{ + drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n"); + /* It uses the legacy hsw implementation for the same */ + hsw_write_infoframe(encoder, crtc_state, type, frame, len); +} + static const u8 infoframe_type_to_idx[] = { HDMI_PACKET_TYPE_GENERAL_CONTROL, HDMI_PACKET_TYPE_GAMUT_METADATA, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 70bd564cae46..95d29c379076 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -461,27 +461,42 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, unsigned int type, const void *frame, ssize_t len) { - bool ret; + bool ret = true; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); - /* LSPCON only needs AVI IF */ - if (type != HDMI_INFOFRAME_TYPE_AVI) + /* + * Supporting HDR on MCA LSPCON + * Todo: Add support for Parade later + */ + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA && + lspcon->vendor != LSPCON_VENDOR_MCA) return; - if (lspcon->vendor == LSPCON_VENDOR_MCA) - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, - frame, len); - else - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, - frame, len); + switch (type) { + case HDMI_INFOFRAME_TYPE_AVI: + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, + frame, len); + else + ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, + frame, len); + break; + case HDMI_PACKET_TYPE_GAMUT_METADATA: + lspcon_drm_write_infoframe(encoder, crtc_state, + HDMI_PACKET_TYPE_GAMUT_METADATA, + frame, VIDEO_DIP_DATA_SIZE); + break; + default: + return; + } if (!ret) { - DRM_ERROR("Failed to write AVI infoframes\n"); + DRM_ERROR("Failed to write infoframes\n"); return; } - DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n"); + DRM_DEBUG_DRIVER("Infoframes updated successfully\n"); } void lspcon_read_infoframe(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 37cfddf8a9c5..b2051f236223 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config); void lspcon_ycbcr420_config(struct drm_connector *connector, struct intel_crtc_state *crtc_state); - +void lspcon_drm_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len); #endif /* __INTEL_LSPCON_H__ */ -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:22 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:22 +0530 Subject: [Intel-gfx] [v4 03/10] drm/i915/display: Attach HDR property for capable Gen9 devices In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-4-uma.shankar@intel.com> Attach HDR property for Gen9 devices with MCA LSPCON chips. v2: Cleaned HDR property attachment logic based on capability as per Jani Nikula's suggestion. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 95d29c379076..7113c2efdab4 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) lspcon_detect_hdr_capability(lspcon); + if (lspcon->hdr_supported) + drm_object_attach_property(&connector->base, + connector->dev->mode_config.hdr_output_metadata_property, + 0); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n"); -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:23 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:23 +0530 Subject: [Intel-gfx] [v4 04/10] drm/i915/display: Enable BT2020 for HDR on LSPCON devices In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-5-uma.shankar@intel.com> Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry data for HDR using AVI infoframe. LSPCON firmware expects this and though SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device which transfers the same to HDMI sink. v2: Dropped state managed in drm core as per Jani Nikula's suggestion. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 7113c2efdab4..10e2823bf1ae 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -507,6 +507,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder, /* FIXME implement this */ } +/* HDMI HDR Colorspace Spec Definitions */ +#define NORMAL_COLORIMETRY_MASK 0x3 +#define EXTENDED_COLORIMETRY_MASK 0x7 +#define HDMI_COLORIMETRY_BT2020_YCC ((3 << 0) | (6 << 2) | (0 << 5)) + void lspcon_set_infoframes(struct intel_encoder *encoder, bool enable, const struct intel_crtc_state *crtc_state, @@ -551,6 +556,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL); + /* + * Set BT2020 colorspace if driving HDR data + * ToDo: Make this generic and expose all colorspaces for lspcon + */ + if (lspcon->active && lspcon->hdr_supported) { + frame.avi.colorimetry = + HDMI_COLORIMETRY_BT2020_YCC & + NORMAL_COLORIMETRY_MASK; + frame.avi.extended_colorimetry = + (HDMI_COLORIMETRY_BT2020_YCC >> 2) & + EXTENDED_COLORIMETRY_MASK; + } + ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf)); if (ret < 0) { DRM_ERROR("Failed to pack AVI IF\n"); -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:24 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:24 +0530 Subject: [Intel-gfx] [v4 05/10] drm/i915/display: Enable HDR for Parade based lspcon In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-6-uma.shankar@intel.com> Enable HDR for LSPCON based on Parade along with MCA. Signed-off-by: Uma Shankar <uma.shankar at intel.com> Signed-off-by: Vipin Anand <vipin.anand at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 10e2823bf1ae..9034ce6f20b9 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -36,6 +36,7 @@ #define LSPCON_VENDOR_MCA_OUI 0x0060AD #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 +#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511 /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 @@ -112,16 +113,20 @@ static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) container_of(lspcon, struct intel_digital_port, lspcon); struct drm_device *dev = intel_dig_port->base.base.dev; struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u32 lspcon_hdr_status_reg; u8 hdr_caps; int ret; - /* Enable HDR for MCA based LSPCON devices */ if (lspcon->vendor == LSPCON_VENDOR_MCA) - ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, - &hdr_caps, 1); + lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS; + else if (lspcon->vendor == LSPCON_VENDOR_PARADE) + lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS; else return; + ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg, + &hdr_caps, 1); + if (ret < 0) { drm_dbg_kms(dev, "hdr capability detection failed\n"); lspcon->hdr_supported = false; @@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); - /* - * Supporting HDR on MCA LSPCON - * Todo: Add support for Parade later - */ - if (type == HDMI_PACKET_TYPE_GAMUT_METADATA && - lspcon->vendor != LSPCON_VENDOR_MCA) - return; - switch (type) { case HDMI_INFOFRAME_TYPE_AVI: if (lspcon->vendor == LSPCON_VENDOR_MCA) -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:25 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:25 +0530 Subject: [Intel-gfx] [v4 06/10] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-7-uma.shankar@intel.com> Implemented Infoframes enabled readback for LSPCON devices. This will help align the implementation with state readback infrastructure. v2: Added proper bitmask of enabled infoframes as per Ville's recommendation. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 9034ce6f20b9..0f19eb6c5a6d 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, buf, ret); } +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = LSPCON_MCA_AVI_IF_CTRL; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); + return false; + } + + return val & LSPCON_MCA_AVI_IF_KICKOFF; +} + +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); + return false; + } + + return val & LSPCON_PARADE_AVI_IF_KICKOFF; +} + u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { - /* FIXME actually read this from the hw */ - return 0; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + bool infoframes_enabled; + u32 val = 0; + u32 mask, tmp; + + if (lspcon->vendor == LSPCON_VENDOR_MCA) + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); + else + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); + + if (infoframes_enabled) + val |= VIDEO_DIP_ENABLE_AVI_HSW; + + if (lspcon->hdr_supported) { + tmp = intel_de_read(dev_priv, + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); + mask = VIDEO_DIP_ENABLE_GMP_HSW; + + if (tmp & mask) + val |= mask; + } + + return val; } void lspcon_resume(struct intel_lspcon *lspcon) -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:26 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:26 +0530 Subject: [Intel-gfx] [v4 07/10] drm/i915/display: Implement DRM infoframe read for LSPCON In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-8-uma.shankar@intel.com> Implement Read back of HDR metadata infoframes i.e Dynamic Range and Mastering Infoframe for LSPCON devices. v2: Added proper bitmask of enabled infoframes as per Ville's recommendation. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_lspcon.c | 6 +++++- drivers/gpu/drm/i915/display/intel_lspcon.h | 4 ++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 53103ef72a58..786378442dd2 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -600,6 +600,16 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder, hsw_write_infoframe(encoder, crtc_state, type, frame, len); } +void lspcon_drm_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len) +{ + drm_dbg_kms(encoder->base.dev, "Read HDR metadata for lspcon\n"); + /* It uses the legacy hsw implementation for the same */ + hsw_read_infoframe(encoder, crtc_state, type, frame, len); +} + static const u8 infoframe_type_to_idx[] = { HDMI_PACKET_TYPE_GENERAL_CONTROL, HDMI_PACKET_TYPE_GAMUT_METADATA, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 0f19eb6c5a6d..58ebcd198d9e 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -501,7 +501,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder, unsigned int type, void *frame, ssize_t len) { - /* FIXME implement this */ + /* FIXME implement for AVI Infoframe as well */ + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA) + lspcon_drm_read_infoframe(encoder, crtc_state, + HDMI_PACKET_TYPE_GAMUT_METADATA, + frame, VIDEO_DIP_DATA_SIZE); } /* HDMI HDR Colorspace Spec Definitions */ diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index b2051f236223..68d2d835bd86 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -38,4 +38,8 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type, const void *frame, ssize_t len); +void lspcon_drm_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len); #endif /* __INTEL_LSPCON_H__ */ -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:20 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:20 +0530 Subject: [Intel-gfx] [v4 01/10] drm/i915/display: Add HDR Capability detection for LSPCON In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-2-uma.shankar@intel.com> LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES DPCD register. LSPCON implementations capable of supporting HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch reads the same, detects the HDR capability and adds this to intel_lspcon struct. v2: Addressed Jani Nikula's review comment and fixed the HDR capability detection logic Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_lspcon.c | 30 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..ca99a05f52da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1386,6 +1386,7 @@ struct intel_lspcon { bool active; enum drm_lspcon_mode mode; enum lspcon_vendor vendor; + bool hdr_supported; }; struct intel_digital_port { diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 6ff7b226f0a1..70bd564cae46 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -35,6 +35,8 @@ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 #define LSPCON_VENDOR_MCA_OUI 0x0060AD +#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 + /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF @@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) return true; } +static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_digital_port *intel_dig_port = + container_of(lspcon, struct intel_digital_port, lspcon); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* Enable HDR for MCA based LSPCON devices */ + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, + &hdr_caps, 1); + else + return; + + if (ret < 0) { + drm_dbg_kms(dev, "hdr capability detection failed\n"); + lspcon->hdr_supported = false; + return; + } else if (hdr_caps & 0x1) { + drm_dbg_kms(dev, "lspcon capable of HDR\n"); + lspcon->hdr_supported = true; + } +} + static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) { enum drm_lspcon_mode current_mode; @@ -581,6 +609,8 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) return false; } + lspcon_detect_hdr_capability(lspcon); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n"); -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:27 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:27 +0530 Subject: [Intel-gfx] [v4 08/10] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-9-uma.shankar@intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> Non-HDMI sinks shouldn't be sent infoframes. Check for that when using LSPCON. FIXME: How do we turn off infoframes once enabled? Do we even have to? Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++------ drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..ca7911a47d0a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3451,19 +3451,17 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, conn_state); } else { - struct intel_lspcon *lspcon = - enc_to_intel_lspcon(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); - if (lspcon->active) { - struct intel_digital_port *dig_port = - enc_to_dig_port(encoder); + /* FIXME precompute everything properly */ + /* FIXME how do we turn infoframes off again? */ + if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) dig_port->set_infoframes(encoder, crtc_state->has_infoframe, crtc_state, conn_state); - } } } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ca99a05f52da..57f89fdcb50f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1272,6 +1272,7 @@ struct intel_dp { u8 sink_count; bool link_mst; bool link_trained; + bool has_hdmi_sink; bool has_audio; bool reset_link_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..c6b2b307cf4e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6104,7 +6104,11 @@ intel_dp_set_edid(struct intel_dp *intel_dp) edid = intel_dp_get_edid(intel_dp); intel_connector->detect_edid = edid; - intel_dp->has_audio = drm_detect_monitor_audio(edid); + if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { + intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); + intel_dp->has_audio = drm_detect_monitor_audio(edid); + } + drm_dp_cec_set_edid(&intel_dp->aux, edid); intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); } @@ -6118,6 +6122,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) kfree(intel_connector->detect_edid); intel_connector->detect_edid = NULL; + intel_dp->has_hdmi_sink = false; intel_dp->has_audio = false; intel_dp->edid_quirks = 0; } -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:29 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:29 +0530 Subject: [Intel-gfx] [v4 10/10] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-11-uma.shankar@intel.com> Blanking needs to be reduced to incorporate DP and HDMI timing/link bandwidth limitations for CEA modes (4k at 60 at 10 bpp). DP can drive 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will cause mode to blank out. Reduced Htotal by shortening the back porch and front porch within permissible limits. Note: This is for reference for userspace, not to be merged in kernel. v2: This is marked as Not for merge and the responsibilty to program these custom timings will be on userspace. This patch is just for reference purposes. This is based on Ville's recommendation. v3: updated commit message. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c6b2b307cf4e..0db8a7d65c35 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -632,8 +632,10 @@ intel_dp_mode_valid(struct drm_connector *connector, { struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; struct drm_i915_private *dev_priv = to_i915(connector->dev); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder); int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk; @@ -655,6 +657,21 @@ intel_dp_mode_valid(struct drm_connector *connector, target_clock = fixed_mode->clock; } + /* + * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth + * limitations for CEA modes (4k at 60 at 10 bpp). DP can drive 17.28Gbs + * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will + * cause mode to blank out. Reduced Htotal by shortening the back porch + * and front porch within permissible limits. + */ + if (lspcon->active && lspcon->hdr_supported && + mode->clock > 570000) { + mode->clock = 570000; + mode->htotal -= 180; + mode->hsync_start -= 72; + mode->hsync_end -= 72; + } + max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 13:00:28 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Mon, 22 Jun 2020 18:30:28 +0530 Subject: [Intel-gfx] [v4 09/10] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <20200622130029.28667-10-uma.shankar@intel.com> Non-HDMI sinks shouldn't be sent Dynamic Range and Mastering infoframes. Check for that when using LSPCON. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7911a47d0a..672441cc99c3 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3714,6 +3714,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum port port = encoder->port; if (port == PORT_A && INTEL_GEN(dev_priv) < 9) @@ -3721,7 +3722,14 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, intel_edp_backlight_on(crtc_state, conn_state); intel_psr_enable(intel_dp, crtc_state, conn_state); - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + + if (dig_port->lspcon.active) { + if (dig_port->dp.has_hdmi_sink) + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + } else { + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + } + intel_edp_drrs_enable(intel_dp, crtc_state); if (crtc_state->has_audio) -- 2.22.0 From patchwork at emeril.freedesktop.org Mon Jun 22 13:04:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 13:04:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Enable_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev4=29?= In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <159283104480.9207.8803310595134045370@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev4) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From cai at lca.pw Sun Jun 21 17:42:05 2020 From: cai at lca.pw (Qian Cai) Date: Sun, 21 Jun 2020 13:42:05 -0400 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200610194101.1668038-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> Message-ID: <20200621174205.GB1398@lca.pw> On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > fs_reclaim_acquire/release nicely catch recursion issues when > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > to use to keep the excessive caches in check). For mmu notifier > recursions we do have lockdep annotations since 23b68395c7c7 > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > But these only fire if a path actually results in some pte > invalidation - for most small allocations that's very rarely the case. > The other trouble is that pte invalidation can happen any time when > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > recursion. > > I was pondering whether we should just do the general annotation, but > there's always the risk for false positives. Plus I'm assuming that > the core fs and io code is a lot better reviewed and tested than > random mmu notifier code in drivers. Hence why I decide to only > annotate for that specific case. > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > still need to explicit pull in the mmu notifier map - there's a lot > more places that do pte invalidation than just direct reclaim, these > two contexts arent the same. > > Note that the mmu notifiers needing their own independent lockdep map > is also the reason we can't hold them from fs_reclaim_acquire to > fs_reclaim_release - it would nest with the acquistion in the pte > invalidation code, causing a lockdep splat. And we can't remove the > annotations from pte invalidation and all the other places since > they're called from many other places than page reclaim. Hence we can > only do the equivalent of might_lock, but on the raw lockdep map. > > With this we can also remove the lockdep priming added in 66204f1d2d1b > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > strictly more powerful. > > v2: Review from Thomas Hellstrom: > - unbotch the fs_reclaim context check, I accidentally inverted it, > but it didn't blow up because I inverted it immediately > - fix compiling for !CONFIG_MMU_NOTIFIER > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > Cc: Andrew Morton <akpm at linux-foundation.org> > Cc: Jason Gunthorpe <jgg at mellanox.com> > Cc: linux-mm at kvack.org > Cc: linux-rdma at vger.kernel.org > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Replying the right patch here... Reverting this commit [1] fixed the lockdep warning below while applying some memory pressure. [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") [ 190.455003][ T369] WARNING: possible circular locking dependency detected [ 190.487291][ T369] 5.8.0-rc1-next-20200621 #1 Not tainted [ 190.512363][ T369] ------------------------------------------------------ [ 190.543354][ T369] kswapd3/369 is trying to acquire lock: [ 190.568523][ T369] ffff889fcf694528 (&xfs_nondir_ilock_class){++++}-{3:3}, at: xfs_reclaim_inode+0xdf/0x860 spin_lock at include/linux/spinlock.h:353 (inlined by) xfs_iflags_test_and_set at fs/xfs/xfs_inode.h:166 (inlined by) xfs_iflock_nowait at fs/xfs/xfs_inode.h:249 (inlined by) xfs_reclaim_inode at fs/xfs/xfs_icache.c:1127 [ 190.614359][ T369] [ 190.614359][ T369] but task is already holding lock: [ 190.647763][ T369] ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 __fs_reclaim_acquire at mm/page_alloc.c:4200 [ 190.687845][ T369] [ 190.687845][ T369] which lock already depends on the new lock. [ 190.687845][ T369] [ 190.734890][ T369] [ 190.734890][ T369] the existing dependency chain (in reverse order) is: [ 190.775991][ T369] [ 190.775991][ T369] -> #1 (fs_reclaim){+.+.}-{0:0}: [ 190.808150][ T369] fs_reclaim_acquire+0x77/0x80 [ 190.832152][ T369] slab_pre_alloc_hook.constprop.52+0x20/0x120 slab_pre_alloc_hook at mm/slab.h:507 [ 190.862173][ T369] kmem_cache_alloc+0x43/0x2a0 [ 190.885602][ T369] kmem_zone_alloc+0x113/0x3ef kmem_zone_alloc at fs/xfs/kmem.c:129 [ 190.908702][ T369] xfs_inode_item_init+0x1d/0xa0 xfs_inode_item_init at fs/xfs/xfs_inode_item.c:639 [ 190.934461][ T369] xfs_trans_ijoin+0x96/0x100 xfs_trans_ijoin at fs/xfs/libxfs/xfs_trans_inode.c:34 [ 190.961530][ T369] xfs_setattr_nonsize+0x1a6/0xcd0 xfs_setattr_nonsize at fs/xfs/xfs_iops.c:716 [ 190.987331][ T369] xfs_vn_setattr+0x133/0x160 xfs_vn_setattr at fs/xfs/xfs_iops.c:1081 [ 191.010476][ T369] notify_change+0x6c5/0xba1 notify_change at fs/attr.c:336 [ 191.033317][ T369] chmod_common+0x19b/0x390 [ 191.055770][ T369] ksys_fchmod+0x28/0x60 [ 191.077957][ T369] __x64_sys_fchmod+0x4e/0x70 [ 191.102767][ T369] do_syscall_64+0x5f/0x310 [ 191.125090][ T369] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 191.153749][ T369] [ 191.153749][ T369] -> #0 (&xfs_nondir_ilock_class){++++}-{3:3}: [ 191.191267][ T369] __lock_acquire+0x2efc/0x4da0 [ 191.215974][ T369] lock_acquire+0x1ac/0xaf0 [ 191.238953][ T369] down_write_nested+0x92/0x150 [ 191.262955][ T369] xfs_reclaim_inode+0xdf/0x860 [ 191.287149][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 [ 191.313291][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 [ 191.338357][ T369] super_cache_scan+0x2fd/0x430 [ 191.362354][ T369] do_shrink_slab+0x317/0x990 [ 191.385341][ T369] shrink_slab+0x3a8/0x4b0 [ 191.407214][ T369] shrink_node+0x49c/0x17b0 [ 191.429841][ T369] balance_pgdat+0x59c/0xed0 [ 191.455041][ T369] kswapd+0x5a4/0xc40 [ 191.477524][ T369] kthread+0x358/0x420 [ 191.499285][ T369] ret_from_fork+0x22/0x30 [ 191.521107][ T369] [ 191.521107][ T369] other info that might help us debug this: [ 191.521107][ T369] [ 191.567490][ T369] Possible unsafe locking scenario: [ 191.567490][ T369] [ 191.600947][ T369] CPU0 CPU1 [ 191.624808][ T369] ---- ---- [ 191.649236][ T369] lock(fs_reclaim); [ 191.667607][ T369] lock(&xfs_nondir_ilock_class); [ 191.702096][ T369] lock(fs_reclaim); [ 191.731243][ T369] lock(&xfs_nondir_ilock_class); [ 191.754025][ T369] [ 191.754025][ T369] *** DEADLOCK *** [ 191.754025][ T369] [ 191.791126][ T369] 4 locks held by kswapd3/369: [ 191.812198][ T369] #0: ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 [ 191.854319][ T369] #1: ffffffffb5074c50 (shrinker_rwsem){++++}-{3:3}, at: shrink_slab+0x219/0x4b0 [ 191.896043][ T369] #2: ffff8890279b40e0 (&type->s_umount_key#27){++++}-{3:3}, at: trylock_super+0x11/0xb0 [ 191.940538][ T369] #3: ffff889027a73a28 (&pag->pag_ici_reclaim_lock){+.+.}-{3:3}, at: xfs_reclaim_inodes_ag+0x135/0xb00 [ 191.995314][ T369] [ 191.995314][ T369] stack backtrace: [ 192.022934][ T369] CPU: 42 PID: 369 Comm: kswapd3 Not tainted 5.8.0-rc1-next-20200621 #1 [ 192.060546][ T369] Hardware name: HP ProLiant BL660c Gen9, BIOS I38 10/17/2018 [ 192.094518][ T369] Call Trace: [ 192.109005][ T369] dump_stack+0x9d/0xe0 [ 192.127468][ T369] check_noncircular+0x347/0x400 [ 192.149526][ T369] ? print_circular_bug+0x360/0x360 [ 192.172584][ T369] ? freezing_slow_path.cold.2+0x2a/0x2a [ 192.197251][ T369] __lock_acquire+0x2efc/0x4da0 [ 192.218737][ T369] ? lockdep_hardirqs_on_prepare+0x550/0x550 [ 192.246736][ T369] ? __lock_acquire+0x3541/0x4da0 [ 192.269673][ T369] lock_acquire+0x1ac/0xaf0 [ 192.290192][ T369] ? xfs_reclaim_inode+0xdf/0x860 [ 192.313158][ T369] ? rcu_read_unlock+0x50/0x50 [ 192.335057][ T369] down_write_nested+0x92/0x150 [ 192.358409][ T369] ? xfs_reclaim_inode+0xdf/0x860 [ 192.380890][ T369] ? rwsem_down_write_slowpath+0xf50/0xf50 [ 192.406891][ T369] ? find_held_lock+0x33/0x1c0 [ 192.427925][ T369] ? xfs_ilock+0x2ef/0x370 [ 192.447496][ T369] ? xfs_reclaim_inode+0xdf/0x860 [ 192.472315][ T369] xfs_reclaim_inode+0xdf/0x860 [ 192.496649][ T369] ? xfs_inode_clear_reclaim_tag+0xa0/0xa0 [ 192.524188][ T369] ? do_raw_spin_unlock+0x4f/0x250 [ 192.546852][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 [ 192.570473][ T369] ? xfs_reclaim_inode+0x860/0x860 [ 192.592692][ T369] ? mark_held_locks+0xb0/0x110 [ 192.614287][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 [ 192.640800][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 [ 192.666695][ T369] ? try_to_wake_up+0xcf/0xf40 [ 192.688265][ T369] ? migrate_swap_stop+0xc10/0xc10 [ 192.711966][ T369] ? do_raw_spin_unlock+0x4f/0x250 [ 192.735032][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 xfs_reclaim_inodes_nr at fs/xfs/xfs_icache.c:1399 [ 192.757674][ T369] ? xfs_reclaim_inodes+0x90/0x90 [ 192.780028][ T369] ? list_lru_count_one+0x177/0x300 [ 192.803010][ T369] super_cache_scan+0x2fd/0x430 super_cache_scan at fs/super.c:115 [ 192.824491][ T369] do_shrink_slab+0x317/0x990 do_shrink_slab at mm/vmscan.c:514 [ 192.845160][ T369] shrink_slab+0x3a8/0x4b0 shrink_slab_memcg at mm/vmscan.c:584 (inlined by) shrink_slab at mm/vmscan.c:662 [ 192.864722][ T369] ? do_shrink_slab+0x990/0x990 [ 192.886137][ T369] ? rcu_is_watching+0x2c/0x80 [ 192.907289][ T369] ? mem_cgroup_protected+0x228/0x470 [ 192.931166][ T369] ? vmpressure+0x25/0x290 [ 192.950595][ T369] shrink_node+0x49c/0x17b0 [ 192.972332][ T369] balance_pgdat+0x59c/0xed0 kswapd_shrink_node at mm/vmscan.c:3521 (inlined by) balance_pgdat at mm/vmscan.c:3670 [ 192.994918][ T369] ? __node_reclaim+0x950/0x950 [ 193.018625][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 [ 193.046566][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 [ 193.070214][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 [ 193.093176][ T369] ? finish_task_switch+0x129/0x650 [ 193.116225][ T369] ? finish_task_switch+0xf2/0x650 [ 193.138809][ T369] ? rcu_read_lock_bh_held+0xc0/0xc0 [ 193.163323][ T369] kswapd+0x5a4/0xc40 [ 193.182690][ T369] ? __kthread_parkme+0x4d/0x1a0 [ 193.204660][ T369] ? balance_pgdat+0xed0/0xed0 [ 193.225776][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 [ 193.252306][ T369] ? finish_wait+0x270/0x270 [ 193.272473][ T369] ? __kthread_parkme+0x4d/0x1a0 [ 193.294476][ T369] ? __kthread_parkme+0xcc/0x1a0 [ 193.316704][ T369] ? balance_pgdat+0xed0/0xed0 [ 193.337808][ T369] kthread+0x358/0x420 [ 193.355666][ T369] ? kthread_create_worker_on_cpu+0xc0/0xc0 [ 193.381884][ T369] ret_from_fork+0x22/0x30 > --- > This is part of a gpu lockdep annotation series simply because it > really helps to catch issues where gpu subsystem locks and primitives > can deadlock with themselves through allocations and mmu notifiers. > But aside from that motivation it should be completely free-standing, > and can land through -mm/-rdma/-hmm or any other tree really whenever. > -Daniel > --- > mm/mmu_notifier.c | 7 ------- > mm/page_alloc.c | 25 ++++++++++++++++--------- > 2 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c > index 06852b896fa6..5d578b9122f8 100644 > --- a/mm/mmu_notifier.c > +++ b/mm/mmu_notifier.c > @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, > lockdep_assert_held_write(&mm->mmap_sem); > BUG_ON(atomic_read(&mm->mm_users) <= 0); > > - if (IS_ENABLED(CONFIG_LOCKDEP)) { > - fs_reclaim_acquire(GFP_KERNEL); > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > - fs_reclaim_release(GFP_KERNEL); > - } > - > if (!mm->notifier_subscriptions) { > /* > * kmalloc cannot be called under mm_take_all_locks(), but we > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > index 13cc653122b7..7536faaaa0fd 100644 > --- a/mm/page_alloc.c > +++ b/mm/page_alloc.c > @@ -57,6 +57,7 @@ > #include <trace/events/oom.h> > #include <linux/prefetch.h> > #include <linux/mm_inline.h> > +#include <linux/mmu_notifier.h> > #include <linux/migrate.h> > #include <linux/hugetlb.h> > #include <linux/sched/rt.h> > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > static struct lockdep_map __fs_reclaim_map = > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > +static bool __need_reclaim(gfp_t gfp_mask) > { > gfp_mask = current_gfp_context(gfp_mask); > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > if (current->flags & PF_MEMALLOC) > return false; > > - /* We're only interested __GFP_FS allocations for now */ > - if (!(gfp_mask & __GFP_FS)) > - return false; > - > if (gfp_mask & __GFP_NOLOCKDEP) > return false; > > @@ -4158,15 +4155,25 @@ void __fs_reclaim_release(void) > > void fs_reclaim_acquire(gfp_t gfp_mask) > { > - if (__need_fs_reclaim(gfp_mask)) > - __fs_reclaim_acquire(); > + if (__need_reclaim(gfp_mask)) { > + if (gfp_mask & __GFP_FS) > + __fs_reclaim_acquire(); > + > +#ifdef CONFIG_MMU_NOTIFIER > + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > + lock_map_release(&__mmu_notifier_invalidate_range_start_map); > +#endif > + > + } > } > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > void fs_reclaim_release(gfp_t gfp_mask) > { > - if (__need_fs_reclaim(gfp_mask)) > - __fs_reclaim_release(); > + if (__need_reclaim(gfp_mask)) { > + if (gfp_mask & __GFP_FS) > + __fs_reclaim_release(); > + } > } > EXPORT_SYMBOL_GPL(fs_reclaim_release); > #endif > -- > 2.26.2 > > From cai at lca.pw Sun Jun 21 17:46:46 2020 From: cai at lca.pw (Qian Cai) Date: Sun, 21 Jun 2020 13:46:46 -0400 Subject: [Intel-gfx] [PATCH 01/18] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <CAKMK7uGbf=OAWWtZMwoaioDKHA_DUyVNiJU4ORbijzUcn+u+Mw@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200621170054.GA1398@lca.pw> <CAKMK7uGbf=OAWWtZMwoaioDKHA_DUyVNiJU4ORbijzUcn+u+Mw@mail.gmail.com> Message-ID: <20200621174646.GC1398@lca.pw> On Sun, Jun 21, 2020 at 07:28:40PM +0200, Daniel Vetter wrote: > On Sun, Jun 21, 2020 at 7:01 PM Qian Cai <cai at lca.pw> wrote: > > > > On Thu, Jun 04, 2020 at 10:12:07AM +0200, Daniel Vetter wrote: > > > fs_reclaim_acquire/release nicely catch recursion issues when > > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > > to use to keep the excessive caches in check). For mmu notifier > > > recursions we do have lockdep annotations since 23b68395c7c7 > > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > > > But these only fire if a path actually results in some pte > > > invalidation - for most small allocations that's very rarely the case. > > > The other trouble is that pte invalidation can happen any time when > > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > > recursion. > > > > > > I was pondering whether we should just do the general annotation, but > > > there's always the risk for false positives. Plus I'm assuming that > > > the core fs and io code is a lot better reviewed and tested than > > > random mmu notifier code in drivers. Hence why I decide to only > > > annotate for that specific case. > > > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > > still need to explicit pull in the mmu notifier map - there's a lot > > > more places that do pte invalidation than just direct reclaim, these > > > two contexts arent the same. > > > > > > Note that the mmu notifiers needing their own independent lockdep map > > > is also the reason we can't hold them from fs_reclaim_acquire to > > > fs_reclaim_release - it would nest with the acquistion in the pte > > > invalidation code, causing a lockdep splat. And we can't remove the > > > annotations from pte invalidation and all the other places since > > > they're called from many other places than page reclaim. Hence we can > > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > > strictly more powerful. > > > > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > > Cc: linux-mm at kvack.org > > > Cc: linux-rdma at vger.kernel.org > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > Cc: Christian K?nig <christian.koenig at amd.com> > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > Reverting this commit fixed the lockdep splat below while applying some > > memory pressure, > > This is a broken version of the patch, please use the one Andrew > merged into -mm. Yes, since it is 5.8.0-rc1-next-20200621 which I believe it includes the latest version from -mm. Anyway, I replied again to your latest patch, https://lore.kernel.org/lkml/20200621174205.GB1398 at lca.pw/ > > Thanks, Daniel > > > > > > [ 190.455003][ T369] WARNING: possible circular locking dependency detected > > [ 190.487291][ T369] 5.8.0-rc1-next-20200621 #1 Not tainted > > [ 190.512363][ T369] ------------------------------------------------------ > > [ 190.543354][ T369] kswapd3/369 is trying to acquire lock: > > [ 190.568523][ T369] ffff889fcf694528 (&xfs_nondir_ilock_class){++++}-{3:3}, at: xfs_reclaim_inode+0xdf/0x860 > > spin_lock at include/linux/spinlock.h:353 > > (inlined by) xfs_iflags_test_and_set at fs/xfs/xfs_inode.h:166 > > (inlined by) xfs_iflock_nowait at fs/xfs/xfs_inode.h:249 > > (inlined by) xfs_reclaim_inode at fs/xfs/xfs_icache.c:1127 > > [ 190.614359][ T369] > > [ 190.614359][ T369] but task is already holding lock: > > [ 190.647763][ T369] ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > > __fs_reclaim_acquire at mm/page_alloc.c:4200 > > [ 190.687845][ T369] > > [ 190.687845][ T369] which lock already depends on the new lock. > > [ 190.687845][ T369] > > [ 190.734890][ T369] > > [ 190.734890][ T369] the existing dependency chain (in reverse order) is: > > [ 190.775991][ T369] > > [ 190.775991][ T369] -> #1 (fs_reclaim){+.+.}-{0:0}: > > [ 190.808150][ T369] fs_reclaim_acquire+0x77/0x80 > > [ 190.832152][ T369] slab_pre_alloc_hook.constprop.52+0x20/0x120 > > slab_pre_alloc_hook at mm/slab.h:507 > > [ 190.862173][ T369] kmem_cache_alloc+0x43/0x2a0 > > [ 190.885602][ T369] kmem_zone_alloc+0x113/0x3ef > > kmem_zone_alloc at fs/xfs/kmem.c:129 > > [ 190.908702][ T369] xfs_inode_item_init+0x1d/0xa0 > > xfs_inode_item_init at fs/xfs/xfs_inode_item.c:639 > > [ 190.934461][ T369] xfs_trans_ijoin+0x96/0x100 > > xfs_trans_ijoin at fs/xfs/libxfs/xfs_trans_inode.c:34 > > [ 190.961530][ T369] xfs_setattr_nonsize+0x1a6/0xcd0 > > xfs_setattr_nonsize at fs/xfs/xfs_iops.c:716 > > [ 190.987331][ T369] xfs_vn_setattr+0x133/0x160 > > xfs_vn_setattr at fs/xfs/xfs_iops.c:1081 > > [ 191.010476][ T369] notify_change+0x6c5/0xba1 > > notify_change at fs/attr.c:336 > > [ 191.033317][ T369] chmod_common+0x19b/0x390 > > [ 191.055770][ T369] ksys_fchmod+0x28/0x60 > > [ 191.077957][ T369] __x64_sys_fchmod+0x4e/0x70 > > [ 191.102767][ T369] do_syscall_64+0x5f/0x310 > > [ 191.125090][ T369] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > > [ 191.153749][ T369] > > [ 191.153749][ T369] -> #0 (&xfs_nondir_ilock_class){++++}-{3:3}: > > [ 191.191267][ T369] __lock_acquire+0x2efc/0x4da0 > > [ 191.215974][ T369] lock_acquire+0x1ac/0xaf0 > > [ 191.238953][ T369] down_write_nested+0x92/0x150 > > [ 191.262955][ T369] xfs_reclaim_inode+0xdf/0x860 > > [ 191.287149][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 > > [ 191.313291][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 > > [ 191.338357][ T369] super_cache_scan+0x2fd/0x430 > > [ 191.362354][ T369] do_shrink_slab+0x317/0x990 > > [ 191.385341][ T369] shrink_slab+0x3a8/0x4b0 > > [ 191.407214][ T369] shrink_node+0x49c/0x17b0 > > [ 191.429841][ T369] balance_pgdat+0x59c/0xed0 > > [ 191.455041][ T369] kswapd+0x5a4/0xc40 > > [ 191.477524][ T369] kthread+0x358/0x420 > > [ 191.499285][ T369] ret_from_fork+0x22/0x30 > > [ 191.521107][ T369] > > [ 191.521107][ T369] other info that might help us debug this: > > [ 191.521107][ T369] > > [ 191.567490][ T369] Possible unsafe locking scenario: > > [ 191.567490][ T369] > > [ 191.600947][ T369] CPU0 CPU1 > > [ 191.624808][ T369] ---- ---- > > [ 191.649236][ T369] lock(fs_reclaim); > > [ 191.667607][ T369] lock(&xfs_nondir_ilock_class); > > [ 191.702096][ T369] lock(fs_reclaim); > > [ 191.731243][ T369] lock(&xfs_nondir_ilock_class); > > [ 191.754025][ T369] > > [ 191.754025][ T369] *** DEADLOCK *** > > [ 191.754025][ T369] > > [ 191.791126][ T369] 4 locks held by kswapd3/369: > > [ 191.812198][ T369] #0: ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > > [ 191.854319][ T369] #1: ffffffffb5074c50 (shrinker_rwsem){++++}-{3:3}, at: shrink_slab+0x219/0x4b0 > > [ 191.896043][ T369] #2: ffff8890279b40e0 (&type->s_umount_key#27){++++}-{3:3}, at: trylock_super+0x11/0xb0 > > [ 191.940538][ T369] #3: ffff889027a73a28 (&pag->pag_ici_reclaim_lock){+.+.}-{3:3}, at: xfs_reclaim_inodes_ag+0x135/0xb00 > > [ 191.995314][ T369] > > [ 191.995314][ T369] stack backtrace: > > [ 192.022934][ T369] CPU: 42 PID: 369 Comm: kswapd3 Not tainted 5.8.0-rc1-next-20200621 #1 > > [ 192.060546][ T369] Hardware name: HP ProLiant BL660c Gen9, BIOS I38 10/17/2018 > > [ 192.094518][ T369] Call Trace: > > [ 192.109005][ T369] dump_stack+0x9d/0xe0 > > [ 192.127468][ T369] check_noncircular+0x347/0x400 > > [ 192.149526][ T369] ? print_circular_bug+0x360/0x360 > > [ 192.172584][ T369] ? freezing_slow_path.cold.2+0x2a/0x2a > > [ 192.197251][ T369] __lock_acquire+0x2efc/0x4da0 > > [ 192.218737][ T369] ? lockdep_hardirqs_on_prepare+0x550/0x550 > > [ 192.246736][ T369] ? __lock_acquire+0x3541/0x4da0 > > [ 192.269673][ T369] lock_acquire+0x1ac/0xaf0 > > [ 192.290192][ T369] ? xfs_reclaim_inode+0xdf/0x860 > > [ 192.313158][ T369] ? rcu_read_unlock+0x50/0x50 > > [ 192.335057][ T369] down_write_nested+0x92/0x150 > > [ 192.358409][ T369] ? xfs_reclaim_inode+0xdf/0x860 > > [ 192.380890][ T369] ? rwsem_down_write_slowpath+0xf50/0xf50 > > [ 192.406891][ T369] ? find_held_lock+0x33/0x1c0 > > [ 192.427925][ T369] ? xfs_ilock+0x2ef/0x370 > > [ 192.447496][ T369] ? xfs_reclaim_inode+0xdf/0x860 > > [ 192.472315][ T369] xfs_reclaim_inode+0xdf/0x860 > > [ 192.496649][ T369] ? xfs_inode_clear_reclaim_tag+0xa0/0xa0 > > [ 192.524188][ T369] ? do_raw_spin_unlock+0x4f/0x250 > > [ 192.546852][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 > > [ 192.570473][ T369] ? xfs_reclaim_inode+0x860/0x860 > > [ 192.592692][ T369] ? mark_held_locks+0xb0/0x110 > > [ 192.614287][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 > > [ 192.640800][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 > > [ 192.666695][ T369] ? try_to_wake_up+0xcf/0xf40 > > [ 192.688265][ T369] ? migrate_swap_stop+0xc10/0xc10 > > [ 192.711966][ T369] ? do_raw_spin_unlock+0x4f/0x250 > > [ 192.735032][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 > > xfs_reclaim_inodes_nr at fs/xfs/xfs_icache.c:1399 > > [ 192.757674][ T369] ? xfs_reclaim_inodes+0x90/0x90 > > [ 192.780028][ T369] ? list_lru_count_one+0x177/0x300 > > [ 192.803010][ T369] super_cache_scan+0x2fd/0x430 > > super_cache_scan at fs/super.c:115 > > [ 192.824491][ T369] do_shrink_slab+0x317/0x990 > > do_shrink_slab at mm/vmscan.c:514 > > [ 192.845160][ T369] shrink_slab+0x3a8/0x4b0 > > shrink_slab_memcg at mm/vmscan.c:584 > > (inlined by) shrink_slab at mm/vmscan.c:662 > > [ 192.864722][ T369] ? do_shrink_slab+0x990/0x990 > > [ 192.886137][ T369] ? rcu_is_watching+0x2c/0x80 > > [ 192.907289][ T369] ? mem_cgroup_protected+0x228/0x470 > > [ 192.931166][ T369] ? vmpressure+0x25/0x290 > > [ 192.950595][ T369] shrink_node+0x49c/0x17b0 > > [ 192.972332][ T369] balance_pgdat+0x59c/0xed0 > > kswapd_shrink_node at mm/vmscan.c:3521 > > (inlined by) balance_pgdat at mm/vmscan.c:3670 > > [ 192.994918][ T369] ? __node_reclaim+0x950/0x950 > > [ 193.018625][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 > > [ 193.046566][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 > > [ 193.070214][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 > > [ 193.093176][ T369] ? finish_task_switch+0x129/0x650 > > [ 193.116225][ T369] ? finish_task_switch+0xf2/0x650 > > [ 193.138809][ T369] ? rcu_read_lock_bh_held+0xc0/0xc0 > > [ 193.163323][ T369] kswapd+0x5a4/0xc40 > > [ 193.182690][ T369] ? __kthread_parkme+0x4d/0x1a0 > > [ 193.204660][ T369] ? balance_pgdat+0xed0/0xed0 > > [ 193.225776][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 > > [ 193.252306][ T369] ? finish_wait+0x270/0x270 > > [ 193.272473][ T369] ? __kthread_parkme+0x4d/0x1a0 > > [ 193.294476][ T369] ? __kthread_parkme+0xcc/0x1a0 > > [ 193.316704][ T369] ? balance_pgdat+0xed0/0xed0 > > [ 193.337808][ T369] kthread+0x358/0x420 > > [ 193.355666][ T369] ? kthread_create_worker_on_cpu+0xc0/0xc0 > > [ 193.381884][ T369] ret_from_fork+0x22/0x30 > > > > > --- > > > This is part of a gpu lockdep annotation series simply because it > > > really helps to catch issues where gpu subsystem locks and primitives > > > can deadlock with themselves through allocations and mmu notifiers. > > > But aside from that motivation it should be completely free-standing, > > > and can land through -mm/-rdma/-hmm or any other tree really whenever. > > > -Daniel > > > --- > > > mm/mmu_notifier.c | 7 ------- > > > mm/page_alloc.c | 23 ++++++++++++++--------- > > > 2 files changed, 14 insertions(+), 16 deletions(-) > > > > > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c > > > index 06852b896fa6..5d578b9122f8 100644 > > > --- a/mm/mmu_notifier.c > > > +++ b/mm/mmu_notifier.c > > > @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, > > > lockdep_assert_held_write(&mm->mmap_sem); > > > BUG_ON(atomic_read(&mm->mm_users) <= 0); > > > > > > - if (IS_ENABLED(CONFIG_LOCKDEP)) { > > > - fs_reclaim_acquire(GFP_KERNEL); > > > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > > - fs_reclaim_release(GFP_KERNEL); > > > - } > > > - > > > if (!mm->notifier_subscriptions) { > > > /* > > > * kmalloc cannot be called under mm_take_all_locks(), but we > > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > > > index 13cc653122b7..f8a222db4a53 100644 > > > --- a/mm/page_alloc.c > > > +++ b/mm/page_alloc.c > > > @@ -57,6 +57,7 @@ > > > #include <trace/events/oom.h> > > > #include <linux/prefetch.h> > > > #include <linux/mm_inline.h> > > > +#include <linux/mmu_notifier.h> > > > #include <linux/migrate.h> > > > #include <linux/hugetlb.h> > > > #include <linux/sched/rt.h> > > > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > > > static struct lockdep_map __fs_reclaim_map = > > > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > > > > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > > > +static bool __need_reclaim(gfp_t gfp_mask) > > > { > > > gfp_mask = current_gfp_context(gfp_mask); > > > > > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > > > if (current->flags & PF_MEMALLOC) > > > return false; > > > > > > - /* We're only interested __GFP_FS allocations for now */ > > > - if (!(gfp_mask & __GFP_FS)) > > > - return false; > > > - > > > if (gfp_mask & __GFP_NOLOCKDEP) > > > return false; > > > > > > @@ -4158,15 +4155,23 @@ void __fs_reclaim_release(void) > > > > > > void fs_reclaim_acquire(gfp_t gfp_mask) > > > { > > > - if (__need_fs_reclaim(gfp_mask)) > > > - __fs_reclaim_acquire(); > > > + if (__need_reclaim(gfp_mask)) { > > > + if (!(gfp_mask & __GFP_FS)) > > > + __fs_reclaim_acquire(); > > > + > > > + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > > + lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > > + > > > + } > > > } > > > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > > > > > void fs_reclaim_release(gfp_t gfp_mask) > > > { > > > - if (__need_fs_reclaim(gfp_mask)) > > > - __fs_reclaim_release(); > > > + if (__need_reclaim(gfp_mask)) { > > > + if (!(gfp_mask & __GFP_FS)) > > > + __fs_reclaim_release(); > > > + } > > > } > > > EXPORT_SYMBOL_GPL(fs_reclaim_release); > > > #endif > > > -- > > > 2.26.2 > > > > > > > > > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch From cai at lca.pw Sun Jun 21 22:09:37 2020 From: cai at lca.pw (Qian Cai) Date: Sun, 21 Jun 2020 18:09:37 -0400 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200621200103.GV20149@phenom.ffwll.local> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> <20200621174205.GB1398@lca.pw> <CAKMK7uFZAFVmceoYvqPovOifGw_Y8Ey-OMy6wioMjwPWhu9dDg@mail.gmail.com> <20200621200103.GV20149@phenom.ffwll.local> Message-ID: <20200621220937.GA2034@lca.pw> On Sun, Jun 21, 2020 at 10:01:03PM +0200, Daniel Vetter wrote: > On Sun, Jun 21, 2020 at 08:07:08PM +0200, Daniel Vetter wrote: > > On Sun, Jun 21, 2020 at 7:42 PM Qian Cai <cai at lca.pw> wrote: > > > > > > On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > > > > fs_reclaim_acquire/release nicely catch recursion issues when > > > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > > > to use to keep the excessive caches in check). For mmu notifier > > > > recursions we do have lockdep annotations since 23b68395c7c7 > > > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > > > > > But these only fire if a path actually results in some pte > > > > invalidation - for most small allocations that's very rarely the case. > > > > The other trouble is that pte invalidation can happen any time when > > > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > > > recursion. > > > > > > > > I was pondering whether we should just do the general annotation, but > > > > there's always the risk for false positives. Plus I'm assuming that > > > > the core fs and io code is a lot better reviewed and tested than > > > > random mmu notifier code in drivers. Hence why I decide to only > > > > annotate for that specific case. > > > > > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > > > still need to explicit pull in the mmu notifier map - there's a lot > > > > more places that do pte invalidation than just direct reclaim, these > > > > two contexts arent the same. > > > > > > > > Note that the mmu notifiers needing their own independent lockdep map > > > > is also the reason we can't hold them from fs_reclaim_acquire to > > > > fs_reclaim_release - it would nest with the acquistion in the pte > > > > invalidation code, causing a lockdep splat. And we can't remove the > > > > annotations from pte invalidation and all the other places since > > > > they're called from many other places than page reclaim. Hence we can > > > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > > > strictly more powerful. > > > > > > > > v2: Review from Thomas Hellstrom: > > > > - unbotch the fs_reclaim context check, I accidentally inverted it, > > > > but it didn't blow up because I inverted it immediately > > > > - fix compiling for !CONFIG_MMU_NOTIFIER > > > > > > > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > > > Cc: linux-mm at kvack.org > > > > Cc: linux-rdma at vger.kernel.org > > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > > Cc: Christian K?nig <christian.koenig at amd.com> > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > > > Replying the right patch here... > > > > > > Reverting this commit [1] fixed the lockdep warning below while applying > > > some memory pressure. > > > > > > [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") > > > > Hm, then I'm confused because > > - there's not mmut notifier lockdep map in the splat at a.. > > - the patch is supposed to not change anything for fs_reclaim (but the > > interim version got that wrong) > > - looking at the paths it's kmalloc vs kswapd, both places I totally > > expect fs_reflaim to be used. > > > > But you're claiming reverting this prevents the lockdep splat. If > > that's right, then my reasoning above is broken somewhere. Someone > > less blind than me having an idea? > > > > Aside this is the first email I've typed, until I realized the first > > report was against the broken patch and that looked like a much more > > reasonable explanation (but didn't quite match up with the code > > paths). > > Below diff should undo the functional change in my patch. Can you pls test > whether the lockdep splat is really gone with that? Might need a lot of > testing and memory pressure to be sure, since all these reclaim paths > aren't very deterministic. Well, I am running even heavy memory pressure workloads on linux-next like every day, and never saw this splat until today where your patch first show up. Since I am rather busy tracking another regression, here is the steps to reproduce (super easy to reproduce on multiple machines here.): # git clone https://github.com/cailca/linux-mm.git # cd linux-mm; make # ./random 0 The .config is in there as well if ever matters. From u.kleine-koenig at pengutronix.de Mon Jun 22 07:55:09 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Mon, 22 Jun 2020 09:55:09 +0200 Subject: [Intel-gfx] [PATCH v3 09/15] pwm: crc: Enable/disable PWM output on enable/disable In-Reply-To: <20200620121758.14836-10-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> <20200620121758.14836-10-hdegoede@redhat.com> Message-ID: <20200622075509.v4jlvqeyjip6wr6c@taurus.defre.kleine-koenig.org> Hello, [adding Shobhit Kumar <shobhit.kumar at intel.com> to Cc who is the author of this driver according to the comment on the top of the driver] On Sat, Jun 20, 2020 at 02:17:52PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM, > this commit makes crc_pwm_disable() clear it on disable and makes > crc_pwm_enable() set it again on re-enable. > > Signed-off-by: Hans de Goede <hdegoede at redhat.com> > --- > Changes in v3: > - Remove paragraph about tri-stating the output from the commit message, > we don't have a datasheet so this was just an unfounded guess I have the impression you spend quite some time with this driver trying to understand it. What I still think is a bit unfortunate is that there is quite some guesswork involved. I wonder if it would be possible to get the manual of that PWM. Do I understand correctly that this is IP from Intel? There are quite some Intel people on Cc; maybe someone can help/put in a good word/check and ack the changes? Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200622/a6bc4423/attachment-0001.sig> From u.kleine-koenig at pengutronix.de Mon Jun 22 07:57:30 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Mon, 22 Jun 2020 09:57:30 +0200 Subject: [Intel-gfx] [PATCH v3 11/15] pwm: crc: Implement get_state() method In-Reply-To: <20200620121758.14836-12-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> <20200620121758.14836-12-hdegoede@redhat.com> Message-ID: <20200622075730.lenaflptqnemagff@taurus.defre.kleine-koenig.org> On Sat, Jun 20, 2020 at 02:17:54PM +0200, Hans de Goede wrote: > Implement the pwm_ops.get_state() method to complete the support for the > new atomic PWM API. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com> > Signed-off-by: Hans de Goede <hdegoede at redhat.com> > --- > Changes in v3: > - Add Andy's Reviewed-by tag > - Remove extra whitespace to align some code after assignments (requested by > Uwe Kleine-K?nig) > --- > drivers/pwm/pwm-crc.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c > index 8a7f4707279c..b311354d40a3 100644 > --- a/drivers/pwm/pwm-crc.c > +++ b/drivers/pwm/pwm-crc.c > @@ -119,8 +119,37 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > return 0; > } > > +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, > + struct pwm_state *state) > +{ > + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); > + struct device *dev = crc_pwm->chip.dev; > + unsigned int clk_div, clk_div_reg, duty_cycle_reg; > + int error; > + > + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); > + if (error) { > + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); > + return; > + } > + > + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); > + if (error) { > + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); > + return; > + } > + > + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; > + > + state->period = clk_div * NSEC_PER_USEC * 256 / PWM_BASE_CLK_MHZ; > + state->duty_cycle = duty_cycle_reg * state->period / PWM_MAX_LEVEL; Please round up here. > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); > +} > + Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200622/e0f2227e/attachment.sig> From cai at lca.pw Sun Jun 21 17:00:54 2020 From: cai at lca.pw (Qian Cai) Date: Sun, 21 Jun 2020 13:00:54 -0400 Subject: [Intel-gfx] [PATCH 01/18] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200604081224.863494-2-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-2-daniel.vetter@ffwll.ch> Message-ID: <20200621170054.GA1398@lca.pw> On Thu, Jun 04, 2020 at 10:12:07AM +0200, Daniel Vetter wrote: > fs_reclaim_acquire/release nicely catch recursion issues when > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > to use to keep the excessive caches in check). For mmu notifier > recursions we do have lockdep annotations since 23b68395c7c7 > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > But these only fire if a path actually results in some pte > invalidation - for most small allocations that's very rarely the case. > The other trouble is that pte invalidation can happen any time when > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > recursion. > > I was pondering whether we should just do the general annotation, but > there's always the risk for false positives. Plus I'm assuming that > the core fs and io code is a lot better reviewed and tested than > random mmu notifier code in drivers. Hence why I decide to only > annotate for that specific case. > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > still need to explicit pull in the mmu notifier map - there's a lot > more places that do pte invalidation than just direct reclaim, these > two contexts arent the same. > > Note that the mmu notifiers needing their own independent lockdep map > is also the reason we can't hold them from fs_reclaim_acquire to > fs_reclaim_release - it would nest with the acquistion in the pte > invalidation code, causing a lockdep splat. And we can't remove the > annotations from pte invalidation and all the other places since > they're called from many other places than page reclaim. Hence we can > only do the equivalent of might_lock, but on the raw lockdep map. > > With this we can also remove the lockdep priming added in 66204f1d2d1b > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > strictly more powerful. > > Cc: Andrew Morton <akpm at linux-foundation.org> > Cc: Jason Gunthorpe <jgg at mellanox.com> > Cc: linux-mm at kvack.org > Cc: linux-rdma at vger.kernel.org > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Reverting this commit fixed the lockdep splat below while applying some memory pressure, [ 190.455003][ T369] WARNING: possible circular locking dependency detected [ 190.487291][ T369] 5.8.0-rc1-next-20200621 #1 Not tainted [ 190.512363][ T369] ------------------------------------------------------ [ 190.543354][ T369] kswapd3/369 is trying to acquire lock: [ 190.568523][ T369] ffff889fcf694528 (&xfs_nondir_ilock_class){++++}-{3:3}, at: xfs_reclaim_inode+0xdf/0x860 spin_lock at include/linux/spinlock.h:353 (inlined by) xfs_iflags_test_and_set at fs/xfs/xfs_inode.h:166 (inlined by) xfs_iflock_nowait at fs/xfs/xfs_inode.h:249 (inlined by) xfs_reclaim_inode at fs/xfs/xfs_icache.c:1127 [ 190.614359][ T369] [ 190.614359][ T369] but task is already holding lock: [ 190.647763][ T369] ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 __fs_reclaim_acquire at mm/page_alloc.c:4200 [ 190.687845][ T369] [ 190.687845][ T369] which lock already depends on the new lock. [ 190.687845][ T369] [ 190.734890][ T369] [ 190.734890][ T369] the existing dependency chain (in reverse order) is: [ 190.775991][ T369] [ 190.775991][ T369] -> #1 (fs_reclaim){+.+.}-{0:0}: [ 190.808150][ T369] fs_reclaim_acquire+0x77/0x80 [ 190.832152][ T369] slab_pre_alloc_hook.constprop.52+0x20/0x120 slab_pre_alloc_hook at mm/slab.h:507 [ 190.862173][ T369] kmem_cache_alloc+0x43/0x2a0 [ 190.885602][ T369] kmem_zone_alloc+0x113/0x3ef kmem_zone_alloc at fs/xfs/kmem.c:129 [ 190.908702][ T369] xfs_inode_item_init+0x1d/0xa0 xfs_inode_item_init at fs/xfs/xfs_inode_item.c:639 [ 190.934461][ T369] xfs_trans_ijoin+0x96/0x100 xfs_trans_ijoin at fs/xfs/libxfs/xfs_trans_inode.c:34 [ 190.961530][ T369] xfs_setattr_nonsize+0x1a6/0xcd0 xfs_setattr_nonsize at fs/xfs/xfs_iops.c:716 [ 190.987331][ T369] xfs_vn_setattr+0x133/0x160 xfs_vn_setattr at fs/xfs/xfs_iops.c:1081 [ 191.010476][ T369] notify_change+0x6c5/0xba1 notify_change at fs/attr.c:336 [ 191.033317][ T369] chmod_common+0x19b/0x390 [ 191.055770][ T369] ksys_fchmod+0x28/0x60 [ 191.077957][ T369] __x64_sys_fchmod+0x4e/0x70 [ 191.102767][ T369] do_syscall_64+0x5f/0x310 [ 191.125090][ T369] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 191.153749][ T369] [ 191.153749][ T369] -> #0 (&xfs_nondir_ilock_class){++++}-{3:3}: [ 191.191267][ T369] __lock_acquire+0x2efc/0x4da0 [ 191.215974][ T369] lock_acquire+0x1ac/0xaf0 [ 191.238953][ T369] down_write_nested+0x92/0x150 [ 191.262955][ T369] xfs_reclaim_inode+0xdf/0x860 [ 191.287149][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 [ 191.313291][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 [ 191.338357][ T369] super_cache_scan+0x2fd/0x430 [ 191.362354][ T369] do_shrink_slab+0x317/0x990 [ 191.385341][ T369] shrink_slab+0x3a8/0x4b0 [ 191.407214][ T369] shrink_node+0x49c/0x17b0 [ 191.429841][ T369] balance_pgdat+0x59c/0xed0 [ 191.455041][ T369] kswapd+0x5a4/0xc40 [ 191.477524][ T369] kthread+0x358/0x420 [ 191.499285][ T369] ret_from_fork+0x22/0x30 [ 191.521107][ T369] [ 191.521107][ T369] other info that might help us debug this: [ 191.521107][ T369] [ 191.567490][ T369] Possible unsafe locking scenario: [ 191.567490][ T369] [ 191.600947][ T369] CPU0 CPU1 [ 191.624808][ T369] ---- ---- [ 191.649236][ T369] lock(fs_reclaim); [ 191.667607][ T369] lock(&xfs_nondir_ilock_class); [ 191.702096][ T369] lock(fs_reclaim); [ 191.731243][ T369] lock(&xfs_nondir_ilock_class); [ 191.754025][ T369] [ 191.754025][ T369] *** DEADLOCK *** [ 191.754025][ T369] [ 191.791126][ T369] 4 locks held by kswapd3/369: [ 191.812198][ T369] #0: ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 [ 191.854319][ T369] #1: ffffffffb5074c50 (shrinker_rwsem){++++}-{3:3}, at: shrink_slab+0x219/0x4b0 [ 191.896043][ T369] #2: ffff8890279b40e0 (&type->s_umount_key#27){++++}-{3:3}, at: trylock_super+0x11/0xb0 [ 191.940538][ T369] #3: ffff889027a73a28 (&pag->pag_ici_reclaim_lock){+.+.}-{3:3}, at: xfs_reclaim_inodes_ag+0x135/0xb00 [ 191.995314][ T369] [ 191.995314][ T369] stack backtrace: [ 192.022934][ T369] CPU: 42 PID: 369 Comm: kswapd3 Not tainted 5.8.0-rc1-next-20200621 #1 [ 192.060546][ T369] Hardware name: HP ProLiant BL660c Gen9, BIOS I38 10/17/2018 [ 192.094518][ T369] Call Trace: [ 192.109005][ T369] dump_stack+0x9d/0xe0 [ 192.127468][ T369] check_noncircular+0x347/0x400 [ 192.149526][ T369] ? print_circular_bug+0x360/0x360 [ 192.172584][ T369] ? freezing_slow_path.cold.2+0x2a/0x2a [ 192.197251][ T369] __lock_acquire+0x2efc/0x4da0 [ 192.218737][ T369] ? lockdep_hardirqs_on_prepare+0x550/0x550 [ 192.246736][ T369] ? __lock_acquire+0x3541/0x4da0 [ 192.269673][ T369] lock_acquire+0x1ac/0xaf0 [ 192.290192][ T369] ? xfs_reclaim_inode+0xdf/0x860 [ 192.313158][ T369] ? rcu_read_unlock+0x50/0x50 [ 192.335057][ T369] down_write_nested+0x92/0x150 [ 192.358409][ T369] ? xfs_reclaim_inode+0xdf/0x860 [ 192.380890][ T369] ? rwsem_down_write_slowpath+0xf50/0xf50 [ 192.406891][ T369] ? find_held_lock+0x33/0x1c0 [ 192.427925][ T369] ? xfs_ilock+0x2ef/0x370 [ 192.447496][ T369] ? xfs_reclaim_inode+0xdf/0x860 [ 192.472315][ T369] xfs_reclaim_inode+0xdf/0x860 [ 192.496649][ T369] ? xfs_inode_clear_reclaim_tag+0xa0/0xa0 [ 192.524188][ T369] ? do_raw_spin_unlock+0x4f/0x250 [ 192.546852][ T369] xfs_reclaim_inodes_ag+0x505/0xb00 [ 192.570473][ T369] ? xfs_reclaim_inode+0x860/0x860 [ 192.592692][ T369] ? mark_held_locks+0xb0/0x110 [ 192.614287][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 [ 192.640800][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 [ 192.666695][ T369] ? try_to_wake_up+0xcf/0xf40 [ 192.688265][ T369] ? migrate_swap_stop+0xc10/0xc10 [ 192.711966][ T369] ? do_raw_spin_unlock+0x4f/0x250 [ 192.735032][ T369] xfs_reclaim_inodes_nr+0x93/0xd0 xfs_reclaim_inodes_nr at fs/xfs/xfs_icache.c:1399 [ 192.757674][ T369] ? xfs_reclaim_inodes+0x90/0x90 [ 192.780028][ T369] ? list_lru_count_one+0x177/0x300 [ 192.803010][ T369] super_cache_scan+0x2fd/0x430 super_cache_scan at fs/super.c:115 [ 192.824491][ T369] do_shrink_slab+0x317/0x990 do_shrink_slab at mm/vmscan.c:514 [ 192.845160][ T369] shrink_slab+0x3a8/0x4b0 shrink_slab_memcg at mm/vmscan.c:584 (inlined by) shrink_slab at mm/vmscan.c:662 [ 192.864722][ T369] ? do_shrink_slab+0x990/0x990 [ 192.886137][ T369] ? rcu_is_watching+0x2c/0x80 [ 192.907289][ T369] ? mem_cgroup_protected+0x228/0x470 [ 192.931166][ T369] ? vmpressure+0x25/0x290 [ 192.950595][ T369] shrink_node+0x49c/0x17b0 [ 192.972332][ T369] balance_pgdat+0x59c/0xed0 kswapd_shrink_node at mm/vmscan.c:3521 (inlined by) balance_pgdat at mm/vmscan.c:3670 [ 192.994918][ T369] ? __node_reclaim+0x950/0x950 [ 193.018625][ T369] ? lockdep_hardirqs_on_prepare+0x38c/0x550 [ 193.046566][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 [ 193.070214][ T369] ? _raw_spin_unlock_irq+0x1f/0x30 [ 193.093176][ T369] ? finish_task_switch+0x129/0x650 [ 193.116225][ T369] ? finish_task_switch+0xf2/0x650 [ 193.138809][ T369] ? rcu_read_lock_bh_held+0xc0/0xc0 [ 193.163323][ T369] kswapd+0x5a4/0xc40 [ 193.182690][ T369] ? __kthread_parkme+0x4d/0x1a0 [ 193.204660][ T369] ? balance_pgdat+0xed0/0xed0 [ 193.225776][ T369] ? _raw_spin_unlock_irqrestore+0x39/0x40 [ 193.252306][ T369] ? finish_wait+0x270/0x270 [ 193.272473][ T369] ? __kthread_parkme+0x4d/0x1a0 [ 193.294476][ T369] ? __kthread_parkme+0xcc/0x1a0 [ 193.316704][ T369] ? balance_pgdat+0xed0/0xed0 [ 193.337808][ T369] kthread+0x358/0x420 [ 193.355666][ T369] ? kthread_create_worker_on_cpu+0xc0/0xc0 [ 193.381884][ T369] ret_from_fork+0x22/0x30 > --- > This is part of a gpu lockdep annotation series simply because it > really helps to catch issues where gpu subsystem locks and primitives > can deadlock with themselves through allocations and mmu notifiers. > But aside from that motivation it should be completely free-standing, > and can land through -mm/-rdma/-hmm or any other tree really whenever. > -Daniel > --- > mm/mmu_notifier.c | 7 ------- > mm/page_alloc.c | 23 ++++++++++++++--------- > 2 files changed, 14 insertions(+), 16 deletions(-) > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c > index 06852b896fa6..5d578b9122f8 100644 > --- a/mm/mmu_notifier.c > +++ b/mm/mmu_notifier.c > @@ -612,13 +612,6 @@ int __mmu_notifier_register(struct mmu_notifier *subscription, > lockdep_assert_held_write(&mm->mmap_sem); > BUG_ON(atomic_read(&mm->mm_users) <= 0); > > - if (IS_ENABLED(CONFIG_LOCKDEP)) { > - fs_reclaim_acquire(GFP_KERNEL); > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > - fs_reclaim_release(GFP_KERNEL); > - } > - > if (!mm->notifier_subscriptions) { > /* > * kmalloc cannot be called under mm_take_all_locks(), but we > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > index 13cc653122b7..f8a222db4a53 100644 > --- a/mm/page_alloc.c > +++ b/mm/page_alloc.c > @@ -57,6 +57,7 @@ > #include <trace/events/oom.h> > #include <linux/prefetch.h> > #include <linux/mm_inline.h> > +#include <linux/mmu_notifier.h> > #include <linux/migrate.h> > #include <linux/hugetlb.h> > #include <linux/sched/rt.h> > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > static struct lockdep_map __fs_reclaim_map = > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > +static bool __need_reclaim(gfp_t gfp_mask) > { > gfp_mask = current_gfp_context(gfp_mask); > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > if (current->flags & PF_MEMALLOC) > return false; > > - /* We're only interested __GFP_FS allocations for now */ > - if (!(gfp_mask & __GFP_FS)) > - return false; > - > if (gfp_mask & __GFP_NOLOCKDEP) > return false; > > @@ -4158,15 +4155,23 @@ void __fs_reclaim_release(void) > > void fs_reclaim_acquire(gfp_t gfp_mask) > { > - if (__need_fs_reclaim(gfp_mask)) > - __fs_reclaim_acquire(); > + if (__need_reclaim(gfp_mask)) { > + if (!(gfp_mask & __GFP_FS)) > + __fs_reclaim_acquire(); > + > + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > + lock_map_release(&__mmu_notifier_invalidate_range_start_map); > + > + } > } > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > void fs_reclaim_release(gfp_t gfp_mask) > { > - if (__need_fs_reclaim(gfp_mask)) > - __fs_reclaim_release(); > + if (__need_reclaim(gfp_mask)) { > + if (!(gfp_mask & __GFP_FS)) > + __fs_reclaim_release(); > + } > } > EXPORT_SYMBOL_GPL(fs_reclaim_release); > #endif > -- > 2.26.2 > > From u.kleine-koenig at pengutronix.de Mon Jun 22 07:25:54 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Mon, 22 Jun 2020 09:25:54 +0200 Subject: [Intel-gfx] [PATCH v3 03/15] pwm: lpss: Fix off by one error in base_unit math in pwm_lpss_prepare() In-Reply-To: <20200620121758.14836-4-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> <20200620121758.14836-4-hdegoede@redhat.com> Message-ID: <20200622072554.qkuvf25xmy3vyjd2@taurus.defre.kleine-koenig.org> On Sat, Jun 20, 2020 at 02:17:46PM +0200, Hans de Goede wrote: > According to the data-sheet the way the PWM controller works is that > each input clock-cycle the base_unit gets added to a N bit counter and > that counter overflowing determines the PWM output frequency. > > So assuming e.g. a 16 bit counter this means that if base_unit is set to 1, > after 65535 input clock-cycles the counter has been increased from 0 to > 65535 and it will overflow on the next cycle, so it will overflow after > every 65536 clock cycles and thus the calculations done in > pwm_lpss_prepare() should use 65536 and not 65535. > > This commit fixes this. Note this also aligns the calculations in > pwm_lpss_prepare() with those in pwm_lpss_get_state(). > > Note this effectively reverts commit 684309e5043e ("pwm: lpss: Avoid > potential overflow of base_unit"). The next patch in this series really > fixes the potential overflow of the base_unit value. > > Fixes: 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit") > Reviewed-by: Andy Shevchenko <andriy.shevchenko at linux.intel.com> > Signed-off-by: Hans de Goede <hdegoede at redhat.com> > --- > Changes in v3: > - Add Fixes tag > - Add Reviewed-by: Andy Shevchenko tag > --- > drivers/pwm/pwm-lpss.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c > index 9d965ffe66d1..43b1fc634af1 100644 > --- a/drivers/pwm/pwm-lpss.c > +++ b/drivers/pwm/pwm-lpss.c > @@ -93,7 +93,7 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, > * The equation is: > * base_unit = round(base_unit_range * freq / c) > */ > - base_unit_range = BIT(lpwm->info->base_unit_bits) - 1; > + base_unit_range = BIT(lpwm->info->base_unit_bits); > freq *= base_unit_range; > > base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); > @@ -104,8 +104,8 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, > > orig_ctrl = ctrl = pwm_lpss_read(pwm); > ctrl &= ~PWM_ON_TIME_DIV_MASK; > - ctrl &= ~(base_unit_range << PWM_BASE_UNIT_SHIFT); > - base_unit &= base_unit_range; > + ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); > + base_unit &= (base_unit_range - 1); > ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; > ctrl |= on_time_div; I willing to believe your change is right, what I don't like is that the calculation is really hard to follow. But that's nothing I want to burden on you to improve. (If however you are motivated, adding some comments about the hardware would probably help.) Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de> Thanks Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200622/aae1fb5e/attachment-0001.sig> From u.kleine-koenig at pengutronix.de Mon Jun 22 07:35:54 2020 From: u.kleine-koenig at pengutronix.de (Uwe =?utf-8?Q?Kleine-K=C3=B6nig?=) Date: Mon, 22 Jun 2020 09:35:54 +0200 Subject: [Intel-gfx] [PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value In-Reply-To: <20200620121758.14836-5-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> <20200620121758.14836-5-hdegoede@redhat.com> Message-ID: <20200622073554.wf3smq3tvnr6t2xy@taurus.defre.kleine-koenig.org> On Sat, Jun 20, 2020 at 02:17:47PM +0200, Hans de Goede wrote: > When the user requests a high enough period ns value, then the > calculations in pwm_lpss_prepare() might result in a base_unit value of 0. > > But according to the data-sheet the way the PWM controller works is that > each input clock-cycle the base_unit gets added to a N bit counter and > that counter overflowing determines the PWM output frequency. Adding 0 > to the counter is a no-op. The data-sheet even explicitly states that > writing 0 to the base_unit bits will result in the PWM outputting a > continuous 0 signal. > > When the user requestes a low enough period ns value, then the > calculations in pwm_lpss_prepare() might result in a base_unit value > which is bigger then base_unit_range - 1. Currently the codes for this > deals with this by applying a mask: > > base_unit &= (base_unit_range - 1); > > But this means that we let the value overflow the range, we throw away the > higher bits and store whatever value is left in the lower bits into the > register leading to a random output frequency, rather then clamping the > output frequency to the highest frequency which the hardware can do. > > This commit fixes both issues by clamping the base_unit value to be > between 1 and (base_unit_range - 1). > > Fixes: 684309e5043e ("pwm: lpss: Avoid potential overflow of base_unit") > Signed-off-by: Hans de Goede <hdegoede at redhat.com> > --- > Changes in v3: > - Change upper limit of clamp to (base_unit_range - 1) > - Add Fixes tag > --- > drivers/pwm/pwm-lpss.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c > index 43b1fc634af1..80d0f9c64f9d 100644 > --- a/drivers/pwm/pwm-lpss.c > +++ b/drivers/pwm/pwm-lpss.c > @@ -97,6 +97,9 @@ static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm, > freq *= base_unit_range; > > base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); DIV_ROUND_CLOSEST_ULL is most probably wrong, too. But I didn't spend the time to actually confirm that. > + /* base_unit must not be 0 and we also want to avoid overflowing it */ > + base_unit = clamp_t(unsigned long long, base_unit, 1, > + base_unit_range - 1); .get_state seems to handle base_unit == 0 just fine?! Though this doesn't look right either ... Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | https://www.pengutronix.de/ | -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 488 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200622/f53ce6d4/attachment-0001.sig> From patchwork at emeril.freedesktop.org Mon Jun 22 13:26:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 13:26:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev4=29?= In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <159283236070.9209.17979482496429915072@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev4) URL : https://patchwork.freedesktop.org/series/68081/ State : success == Summary == CI Bug Log - changes from CI_DRM_8651 -> Patchwork_18004 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/index.html Known issues ------------ Here are the changes found in Patchwork_18004 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][3] -> [DMESG-WARN][4] ([i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [PASS][5] -> [DMESG-FAIL][6] ([i915#1233]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [INCOMPLETE][9] ([i915#1242]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-tgl-dsi/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-tgl-dsi/igt at i915_pm_rpm@module-reload.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 39) ------------------------------ Additional (1): fi-kbl-soraka Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8651 -> Patchwork_18004 CI-20190529: 20190529 CI_DRM_8651: f6210d1dd268f9e09e10d3704c768d7679a44f48 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5715: 3b6975c0f9e429c0c1f48c61a3417be9d68300cf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18004: c944d7fc0591a3d478712a5b7561525480f2f5d8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c944d7fc0591 drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60 at 10bpp for LSPCON 38d42b33e326 drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks 4510a87f28c5 drm/i915/lspcon: Do not send infoframes to non-HDMI sinks 735b2b898231 drm/i915/display: Implement DRM infoframe read for LSPCON da4ab47813eb drm/i915/display: Implement infoframes readback for LSPCON ac45f7f85e01 drm/i915/display: Enable HDR for Parade based lspcon 36e1b18b751e drm/i915/display: Enable BT2020 for HDR on LSPCON devices c7aa4dde8e19 drm/i915/display: Attach HDR property for capable Gen9 devices 5bf7b951df59 drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon 6ae867c8b14c drm/i915/display: Add HDR Capability detection for LSPCON == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/index.html From nicholas.kazlauskas at amd.com Mon Jun 22 14:57:02 2020 From: nicholas.kazlauskas at amd.com (Kazlauskas, Nicholas) Date: Mon, 22 Jun 2020 10:57:02 -0400 Subject: [Intel-gfx] [v1 3/3] Revert "drm/amd/display: Expose connector VRR range via debugfs" In-Reply-To: <20200622142519.16214-4-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> <20200622142519.16214-4-bhanuprakash.modem@intel.com> Message-ID: <f9c32dfa-0a23-45c0-8991-545c071da388@amd.com> On 2020-06-22 10:25 a.m., Bhanuprakash Modem wrote: > As both VRR min and max are already part of drm_display_info, > drm can expose this VRR range for each connector. > > Hence this logic should move to core DRM. > > This reverts commit 727962f030c23422a01e8b22d0f463815fb15ec4. > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > Cc: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> > Cc: Harry Wentland <harry.wentland at amd.com> > Cc: Alex Deucher <alexander.deucher at amd.com> > Cc: Manasi Navare <manasi.d.navare at intel.com> > Cc: AMD gfx <amd-gfx at lists.freedesktop.org> Looks good to me with Patch 2 part of the series. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> Thanks, Nicholas Kazlauskas > --- > .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ------------------- > 1 file changed, 20 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > index 076af267b488..71387d2af2ed 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > @@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void *data) > return res; > } > > -/* > - * Returns the min and max vrr vfreq through the connector's debugfs file. > - * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > - */ > -static int vrr_range_show(struct seq_file *m, void *data) > -{ > - struct drm_connector *connector = m->private; > - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); > - > - if (connector->status != connector_status_connected) > - return -ENODEV; > - > - seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); > - seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); > - > - return 0; > -} > - > #ifdef CONFIG_DRM_AMD_DC_HDCP > /* > * Returns the HDCP capability of the Display (1.4 for now). > @@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, > DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); > DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); > DEFINE_SHOW_ATTRIBUTE(output_bpc); > -DEFINE_SHOW_ATTRIBUTE(vrr_range); > #ifdef CONFIG_DRM_AMD_DC_HDCP > DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); > #endif > @@ -1059,7 +1040,6 @@ static const struct { > {"phy_settings", &dp_phy_settings_debugfs_fop}, > {"test_pattern", &dp_phy_test_pattern_fops}, > {"output_bpc", &output_bpc_fops}, > - {"vrr_range", &vrr_range_fops}, > #ifdef CONFIG_DRM_AMD_DC_HDCP > {"hdcp_sink_capability", &hdcp_sink_capability_fops}, > #endif > From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:37 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:37 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 0/8] tests/core_hotunplug: New subtests and enhancements Message-ID: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Add a bunch of new test variants, enhance debugging of hotunplug driver issues. Janusz Krzysztofik (8): tests/core_hotunplug: Duplicate debug messages in dmesg tests/core_hotunplug: Use PCI device sysfs entry, not DRM tests/core_hotunplug: Add unbind-unplug-rescan variant tests/core_hotunplug: Add 'lateclose before recover' variants tests/core_hotunplug: Add 'GEM address space' variant tests/core_hotunplug: Add 'GEM object' variant tests/core_hotunplug: Add 'PRIME handle' variant tests/core_hotunplug: Add 'GEM batch' variant tests/core_hotunplug.c | 331 +++++++++++++++++++++++++++++++++++------ 1 file changed, 284 insertions(+), 47 deletions(-) -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:39 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:39 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 2/8] tests/core_hotunplug: Use PCI device sysfs entry, not DRM In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-3-janusz.krzysztofik@linux.intel.com> Future subtests may want to access PCI attributes of the device after driver unbind. Refactor prepare() helper. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 68 +++++++++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 187168009..c7213d728 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -54,42 +54,54 @@ struct hotunplug { igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ }) -static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) +static inline int prepare_common(struct hotunplug *priv) { - int len; + int fd_sysfs_drm; + + local_debug("opening device"); + priv->fd.drm = __drm_open_driver(DRIVER_ANY); + igt_assert(priv->fd.drm >= 0); + + fd_sysfs_drm = igt_sysfs_open(priv->fd.drm); + igt_assert(fd_sysfs_drm >= 0); + + return fd_sysfs_drm; +} + +static inline void prepare_for_rebind(struct hotunplug *priv, + char *buf, int buflen) +{ + int fd_sysfs_drm, len; igt_assert(buflen); - priv->fd.sysfs_drv = openat(priv->fd.sysfs_dev, "device/driver", - O_DIRECTORY); - igt_assert(priv->fd.sysfs_drv >= 0); + fd_sysfs_drm = prepare_common(priv); + + priv->fd.sysfs_drv = openat(fd_sysfs_drm, "device/driver", O_DIRECTORY); - len = readlinkat(priv->fd.sysfs_dev, "device", buf, buflen - 1); + len = readlinkat(fd_sysfs_drm, "device", buf, buflen - 1); buf[len] = '\0'; priv->dev_bus_addr = strrchr(buf, '/'); - igt_assert(priv->dev_bus_addr++); - /* sysfs_dev no longer needed */ - close(priv->fd.sysfs_dev); + close(fd_sysfs_drm); + + igt_assert(priv->fd.sysfs_drv >= 0); + igt_assert(priv->dev_bus_addr++); } -static inline void prepare(struct hotunplug *priv, char *buf, int buflen) +static inline void prepare_for_rescan(struct hotunplug *priv) { - local_debug("opening device"); - priv->fd.drm = __drm_open_driver(DRIVER_ANY); - igt_assert(priv->fd.drm >= 0); + int fd_sysfs_drm = prepare_common(priv); - priv->fd.sysfs_dev = igt_sysfs_open(priv->fd.drm); - igt_assert(priv->fd.sysfs_dev >= 0); + priv->fd.sysfs_dev = openat(fd_sysfs_drm, "device", O_DIRECTORY); - if (buf) { - prepare_for_unbind(priv, buf, buflen); - } else { - /* prepare for bus rescan */ - priv->fd.sysfs_bus = openat(priv->fd.sysfs_dev, - "device/subsystem", O_DIRECTORY); - igt_assert(priv->fd.sysfs_bus >= 0); - } + priv->fd.sysfs_bus = openat(fd_sysfs_drm, "device/subsystem", + O_DIRECTORY); + + close(fd_sysfs_drm); + + igt_assert(priv->fd.sysfs_dev >= 0); + igt_assert(priv->fd.sysfs_bus >= 0); } static const char *failure; @@ -123,7 +135,7 @@ static void device_unplug(int fd_sysfs_dev) { failure = "Device unplug timeout!"; igt_set_timeout(60, failure); - igt_sysfs_set(fd_sysfs_dev, "device/remove", "1"); + igt_sysfs_set(fd_sysfs_dev, "remove", "1"); igt_reset_timeout(); failure = NULL; @@ -183,7 +195,7 @@ static void unbind_rebind(void) struct hotunplug priv; char buf[PATH_MAX]; - prepare(&priv, buf, sizeof(buf)); + prepare_for_rebind(&priv, buf, sizeof(buf)); local_debug("closing the device"); close(priv.fd.drm); @@ -201,7 +213,7 @@ static void unplug_rescan(void) { struct hotunplug priv; - prepare(&priv, NULL, 0); + prepare_for_rescan(&priv); local_debug("closing the device"); close(priv.fd.drm); @@ -220,7 +232,7 @@ static void hotunbind_lateclose(void) struct hotunplug priv; char buf[PATH_MAX]; - prepare(&priv, buf, sizeof(buf)); + prepare_for_rebind(&priv, buf, sizeof(buf)); local_debug("hot unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); @@ -238,7 +250,7 @@ static void hotunplug_lateclose(void) { struct hotunplug priv; - prepare(&priv, NULL, 0); + prepare_for_rescan(&priv); local_debug("hot unplugging the device"); device_unplug(priv.fd.sysfs_dev); -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:40 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:40 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 3/8] tests/core_hotunplug: Add unbind-unplug-rescan variant In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-4-janusz.krzysztofik@linux.intel.com> Check if this 3-step procedure exhibits any issues with device recover after unplug. Such issues may indicate insufficient device hardware re-initialization performed by the device driver, or other kernel bugs outside the driver code. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index c7213d728..0b7c6006b 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -209,6 +209,35 @@ static void unbind_rebind(void) healthcheck(); } +static void unbind_unplug_rescan(void) +{ + struct hotunplug priv; + char buf[PATH_MAX]; + + /* prepare for unbind */ + prepare_for_rebind(&priv, buf, sizeof(buf)); + + /* also prepare for unplug */ + local_debug("closing the device"); + close(priv.fd.drm); + prepare_for_rescan(&priv); + + local_debug("closing the device"); + close(priv.fd.drm); + + local_debug("unbinding the driver from the device"); + driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); + close(priv.fd.sysfs_drv); + + local_debug("unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + static void unplug_rescan(void) { struct hotunplug priv; @@ -288,14 +317,21 @@ igt_main close(fd_drm); } - igt_describe("Check if the driver can be cleanly unbound from a device believed to be closed"); + igt_describe("Check if the driver can be cleanly unbound from a device believed to be closed, then rebound"); igt_subtest("unbind-rebind") unbind_rebind(); igt_fixture igt_abort_on_f(failure, "%s\n", failure); - igt_describe("Check if a device believed to be closed can be cleanly unplugged"); + igt_describe("Check if a device with the driver unbound from it can be cleanly recovered after being unplugged\n"); + igt_subtest("unbind-unplug-rescan") + unbind_unplug_rescan(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device believed to be closed can be cleanly unplugged and recovered"); igt_subtest("unplug-rescan") unplug_rescan(); -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:38 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:38 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 1/8] tests/core_hotunplug: Duplicate debug messages in dmesg In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-2-janusz.krzysztofik@linux.intel.com> The purpose of debug messages displayed by the test is to make identification of a subtest phase that fails more easy. Since issues exhibited by the test are mostly reported to dmesg, print those debug messages to /dev/kmsg as well. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index f9cfc8c3c..187168009 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -48,6 +48,12 @@ struct hotunplug { /* Helpers */ +#define local_debug(msg...) \ +({ \ + igt_debug("%s: %s\n", __func__, msg); \ + igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ +}) + static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) { int len; @@ -67,9 +73,9 @@ static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) close(priv->fd.sysfs_dev); } -static void prepare(struct hotunplug *priv, char *buf, int buflen) +static inline void prepare(struct hotunplug *priv, char *buf, int buflen) { - igt_debug("opening device\n"); + local_debug("opening device"); priv->fd.drm = __drm_open_driver(DRIVER_ANY); igt_assert(priv->fd.drm >= 0); @@ -136,14 +142,14 @@ static void bus_rescan(int fd_sysfs_bus) close(fd_sysfs_bus); } -static void healthcheck(void) +static inline void healthcheck(void) { int fd_drm; /* device name may have changed, rebuild IGT device list */ igt_devices_scan(true); - igt_debug("reopening the device\n"); + local_debug("reopening the device"); fd_drm = __drm_open_driver(DRIVER_ANY); igt_abort_on_f(fd_drm < 0, "Device reopen failure"); @@ -179,13 +185,13 @@ static void unbind_rebind(void) prepare(&priv, buf, sizeof(buf)); - igt_debug("closing the device\n"); + local_debug("closing the device"); close(priv.fd.drm); - igt_debug("unbinding the driver from the device\n"); + local_debug("unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); - igt_debug("rebinding the driver to the device\n"); + local_debug("rebinding the driver to the device"); driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); healthcheck(); @@ -197,13 +203,13 @@ static void unplug_rescan(void) prepare(&priv, NULL, 0); - igt_debug("closing the device\n"); + local_debug("closing the device"); close(priv.fd.drm); - igt_debug("unplugging the device\n"); + local_debug("unplugging the device"); device_unplug(priv.fd.sysfs_dev); - igt_debug("recovering the device\n"); + local_debug("recovering the device"); bus_rescan(priv.fd.sysfs_bus); healthcheck(); @@ -216,13 +222,13 @@ static void hotunbind_lateclose(void) prepare(&priv, buf, sizeof(buf)); - igt_debug("hot unbinding the driver from the device\n"); + local_debug("hot unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); - igt_debug("rebinding the driver to the device\n"); + local_debug("rebinding the driver to the device"); driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); - igt_debug("late closing the unbound device instance\n"); + local_debug("late closing the unbound device instance"); close(priv.fd.drm); healthcheck(); @@ -234,13 +240,13 @@ static void hotunplug_lateclose(void) prepare(&priv, NULL, 0); - igt_debug("hot unplugging the device\n"); + local_debug("hot unplugging the device"); device_unplug(priv.fd.sysfs_dev); - igt_debug("recovering the device\n"); + local_debug("recovering the device"); bus_rescan(priv.fd.sysfs_bus); - igt_debug("late closing the removed device instance\n"); + local_debug("late closing the removed device instance"); close(priv.fd.drm); healthcheck(); -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:41 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:41 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 4/8] tests/core_hotunplug: Add 'lateclose before recover' variants In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-5-janusz.krzysztofik@linux.intel.com> If a GPU gets wedged during driver rebind or device re-plug for some reason, current hotunbind/hotunplug test variants may time out before lateclose phase, resulting in incomplete CI reports. Let's rename those variants to more adequate hotrebind/hotreplug-lateclose and add new variants focused on exercising the lateclose phase regardless of potential rebind/re-plug issues under old names. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 57 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 54 insertions(+), 3 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 0b7c6006b..f736a991f 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -266,6 +266,43 @@ static void hotunbind_lateclose(void) local_debug("hot unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); + local_debug("late closing the unbound device instance"); + close(priv.fd.drm); + + local_debug("rebinding the driver to the device"); + driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); + + healthcheck(); +} + +static void hotunplug_lateclose(void) +{ + struct hotunplug priv; + + prepare_for_rescan(&priv); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + +static void hotrebind_lateclose(void) +{ + struct hotunplug priv; + char buf[PATH_MAX]; + + prepare_for_rebind(&priv, buf, sizeof(buf)); + + local_debug("hot unbinding the driver from the device"); + driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); + local_debug("rebinding the driver to the device"); driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); @@ -275,7 +312,7 @@ static void hotunbind_lateclose(void) healthcheck(); } -static void hotunplug_lateclose(void) +static void hotreplug_lateclose(void) { struct hotunplug priv; @@ -338,17 +375,31 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); - igt_describe("Check if the driver can be cleanly unbound from a still open device, then released"); + igt_describe("Check if the driver can be cleanly unbound from a still open device, then released and rebound"); igt_subtest("hotunbind-lateclose") hotunbind_lateclose(); igt_fixture igt_abort_on_f(failure, "%s\n", failure); - igt_describe("Check if a still open device can be cleanly unplugged, then released"); + igt_describe("Check if a still open device can be cleanly unplugged, then released and recovered"); igt_subtest("hotunplug-lateclose") hotunplug_lateclose(); igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if the driver can be cleanly unbound from an open device and rebound back, then released"); + igt_subtest("hotrebind-lateclose") + hotrebind_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a still open device can be cleanly unplugged and recovered, then released"); + igt_subtest("hotreplug-lateclose") + hotreplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:42 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:42 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 5/8] tests/core_hotunplug: Add 'GEM address space' variant In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-6-janusz.krzysztofik@linux.intel.com> Verify if an additional address space associated with an open device file descriptor is cleaned up correctly on device hotunplug. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index f736a991f..6d9f530b1 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -34,6 +34,8 @@ #include "igt_kmod.h" #include "igt_sysfs.h" +#include "i915/gem_vm.h" + IGT_TEST_DESCRIPTION("Examine behavior of a driver on device hot unplug"); struct hotunplug { @@ -330,6 +332,29 @@ static void hotreplug_lateclose(void) healthcheck(); } +static void vm_hotunplug_lateclose(void) +{ + struct hotunplug priv; + + prepare_for_rescan(&priv); + + gem_require_vm(priv.fd.drm); + + local_debug("creating additional GEM user address space"); + igt_ignore_warn(gem_vm_create(priv.fd.drm)); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -402,4 +427,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a still open device with extra GEM address space can be cleanly unplugged, then released and recovered"); + igt_subtest("vm-hotunplug-lateclose") + vm_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:43 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:43 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 6/8] tests/core_hotunplug: Add 'GEM object' variant In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-7-janusz.krzysztofik@linux.intel.com> GEM objects belonging to user file descriptors still open on device hotunplug may exhibit still more driver issues. Add a subtest that implements this scenario. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 6d9f530b1..309d4efef 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -355,6 +355,29 @@ static void vm_hotunplug_lateclose(void) healthcheck(); } +static void gem_hotunplug_lateclose(void) +{ + struct hotunplug priv; + + prepare_for_rescan(&priv); + + igt_require_gem(priv.fd.drm); + + local_debug("creating a GEM user object"); + igt_ignore_warn(gem_create(priv.fd.drm, 4096)); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -434,4 +457,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device with a still open GEM object can be cleanly unplugged, then released and recovered"); + igt_subtest("gem-hotunplug-lateclose") + gem_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:44 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:44 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 7/8] tests/core_hotunplug: Add 'PRIME handle' variant In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-8-janusz.krzysztofik@linux.intel.com> Even if all device file descriptors are closed on device hotunplug, PRIME exported objects may still exists, referenced by still open dma-buf file handles. Add a subtest that keeps such handle open on device hotunplug. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 309d4efef..35a4fb13c 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -378,6 +378,35 @@ static void gem_hotunplug_lateclose(void) healthcheck(); } +static void prime_hotunplug_lateclose(void) +{ + struct hotunplug priv; + uint32_t handle; + int dmabuf; + + prepare_for_rescan(&priv); + + igt_require_gem(priv.fd.drm); + + local_debug("creating and PRIME-exporting a GEM object"); + handle = gem_create(priv.fd.drm, 4096); + dmabuf = prime_handle_to_fd(priv.fd.drm, handle); + + local_debug("closing the device"); + close(priv.fd.drm); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the PRIME file handle"); + close(dmabuf); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -464,4 +493,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device with a still open PRIME-exported object can be cleanly unplugged, then released and recovered"); + igt_subtest("prime-hotunplug-lateclose") + prime_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 15:18:45 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 17:18:45 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t 8/8] tests/core_hotunplug: Add 'GEM batch' variant In-Reply-To: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> References: <20200622151845.4520-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622151845.4520-9-janusz.krzysztofik@linux.intel.com> Verify if a device with a GEM batch job still running on a GPU can be hot-unplugged cleanly and released, then recovered. Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 35a4fb13c..c8d7ec7e1 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -31,6 +31,7 @@ #include "igt.h" #include "igt_device_scan.h" +#include "igt_dummyload.h" #include "igt_kmod.h" #include "igt_sysfs.h" @@ -407,6 +408,32 @@ static void prime_hotunplug_lateclose(void) healthcheck(); } +static void batch_hotunplug_lateclose(void) +{ + struct hotunplug priv; + igt_spin_t *spin; + + prepare_for_rescan(&priv); + + igt_require_gem(priv.fd.drm); + + local_debug("running dummy load"); + spin = __igt_spin_new(priv.fd.drm, .flags = IGT_SPIN_POLL_RUN | + IGT_SPIN_NO_PREEMPTION); + igt_spin_busywait_until_started(spin); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -500,4 +527,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device with a still running batch can be cleanly unplugged, then released and recovered"); + igt_subtest("batch-hotunplug-lateclose") + batch_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From jani.nikula at linux.intel.com Mon Jun 22 15:31:24 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Mon, 22 Jun 2020 18:31:24 +0300 Subject: [Intel-gfx] [PATCH libdrm] intel: sync i915_pciids.h with kernel In-Reply-To: <20200616123758.3331-1-ramadevi.gandi@intel.com> References: <20200616123758.3331-1-ramadevi.gandi@intel.com> Message-ID: <87wo3znmlv.fsf@intel.com> On Tue, 16 Jun 2020, ramadevi.gandi at intel.com wrote: > From: Gandi Ramadevi <ramadevi.gandi at intel.com> > > Add DG1 PCI ID There are no DG1 PCI IDs in kernel. So please don't add them here either. BR, Jani. > > Signed-off-by: Gandi Ramadevi <ramadevi.gandi at intel.com> > --- > intel/i915_pciids.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h > index 662d8351..724e68a0 100644 > --- a/intel/i915_pciids.h > +++ b/intel/i915_pciids.h > @@ -605,4 +605,9 @@ > INTEL_VGA_DEVICE(0x9AD9, info), \ > INTEL_VGA_DEVICE(0x9AF8, info) > > +/* DG1 */ > +#define INTEL_DG1_IDS(info) \ > + INTEL_VGA_DEVICE(0x4905, info), \ > + INTEL_VGA_DEVICE(0x4906, info) > + > #endif /* _I915_PCIIDS_H */ -- Jani Nikula, Intel Open Source Graphics Center From imre.deak at intel.com Mon Jun 22 15:49:26 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 22 Jun 2020 18:49:26 +0300 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200618000124.29036-1-manasi.d.navare@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> Message-ID: <20200622154921.GA25163@ideak-desk.fi.intel.com> On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote: > Modify the helper to add a fixed delay or poll with timeout > based on platform specification in bothe enable and disable > cases so check for either Idle bit set (DDI_BUF_CTL is idle > for disable case) or check for Idle bit = 0 (non idle for > DDI BUF enable case) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++--------- > 1 file changed, 21 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b..e4738c3b6d44 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > } > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > - enum port port) maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ? > + enum port port, bool idle) > { > - i915_reg_t reg = DDI_BUF_CTL(port); > - int i; > - > - for (i = 0; i < 16; i++) { > - udelay(1); > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > - return; > + if (idle) { > + if (IS_BROXTON(dev_priv)) > + udelay(16); > + else > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 16)) > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > + port_name(port)); > + } else { > + if (INTEL_GEN(dev_priv) < 10) > + udelay(600); > + else > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 600)) > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > + port_name(port)); > } > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > - port_name(port)); > + since we can only guarantee a minimum delay or timeout, imo it could be just: if (BXT && !active || GEN <= 9 && active) { usleep_range(600, 1000); return; } if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600)) drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n", port, active ? "active" : "idle")); > } > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E); > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true); > > /* Reset FDI_RX_MISC pwrdn lanes */ > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, > intel_ddi_disable_fec_state(encoder, crtc_state); > > if (wait) > - intel_wait_ddi_buf_idle(dev_priv, port); > + intel_wait_ddi_buf_idle(dev_priv, port, true); > } > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); > > if (wait) > - intel_wait_ddi_buf_idle(dev_priv, port); > + intel_wait_ddi_buf_idle(dev_priv, port, true); > } > > dp_tp_ctl = DP_TP_CTL_ENABLE | The DSI code could also use the new helper. > -- > 2.19.1 > From patchwork at emeril.freedesktop.org Mon Jun 22 16:00:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 16:00:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev4=29?= In-Reply-To: <20200622130029.28667-1-uma.shankar@intel.com> References: <20200622130029.28667-1-uma.shankar@intel.com> Message-ID: <159284164360.9207.12364130611374529650@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev4) URL : https://patchwork.freedesktop.org/series/68081/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8651_full -> Patchwork_18004_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18004_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18004_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18004_full: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - shard-kbl: NOTRUN -> ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5]) ([i915#1611]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl1/igt at runner@aborted.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl7/igt at runner@aborted.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl7/igt at runner@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl7/igt at runner@aborted.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl3/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_18004_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_balancer@bonded-early: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2079]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb2/igt at gem_exec_balancer@bonded-early.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-tglb2/igt at gem_exec_balancer@bonded-early.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#1930]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-forked: - shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118] / [i915#95]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk8/igt at gem_exec_whisper@basic-forked.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-glk9/igt at gem_exec_whisper@basic-forked.html * igt at gem_tiled_fence_blits@basic: - shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#93] / [i915#95]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl3/igt at gem_tiled_fence_blits@basic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl6/igt at gem_tiled_fence_blits@basic.html * igt at i915_module_load@reload: - shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#402]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb5/igt at i915_module_load@reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-tglb5/igt at i915_module_load@reload.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl2/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl6/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-256x85-random: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#54]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl4/igt at kms_cursor_crc@pipe-b-cursor-256x85-random.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl1/igt at kms_cursor_crc@pipe-b-cursor-256x85-random.html * igt at kms_cursor_edge_walk@pipe-b-128x128-left-edge: - shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk5/igt at kms_cursor_edge_walk@pipe-b-128x128-left-edge.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-glk8/igt at kms_cursor_edge_walk@pipe-b-128x128-left-edge.html * igt at kms_cursor_legacy@flip-vs-cursor-crc-atomic: - shard-skl: [PASS][22] -> [DMESG-WARN][23] ([i915#1982]) +5 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-crc-atomic.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl3/igt at kms_cursor_legacy@flip-vs-cursor-crc-atomic.html * igt at kms_cursor_legacy@short-flip-before-cursor-toggle: - shard-apl: [PASS][24] -> [DMESG-WARN][25] ([i915#1635] / [i915#95]) +24 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl8/igt at kms_cursor_legacy@short-flip-before-cursor-toggle.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl4/igt at kms_cursor_legacy@short-flip-before-cursor-toggle.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1: - shard-skl: [PASS][26] -> [FAIL][27] ([i915#46]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl9/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][28] -> [INCOMPLETE][29] ([i915#155] / [i915#180]) +2 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend at b-dp1: - shard-kbl: [PASS][30] -> [INCOMPLETE][31] ([i915#180]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl1/igt at kms_flip@flip-vs-suspend at b-dp1.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl7/igt at kms_flip@flip-vs-suspend at b-dp1.html * igt at kms_flip@plain-flip-fb-recreate at a-edp1: - shard-skl: [PASS][32] -> [FAIL][33] ([i915#1928]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl8/igt at kms_flip@plain-flip-fb-recreate at a-edp1.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl3/igt at kms_flip@plain-flip-fb-recreate at a-edp1.html * igt at kms_flip@plain-flip-ts-check-interruptible at b-dp1: - shard-kbl: [PASS][34] -> [FAIL][35] ([i915#1928]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl4/igt at kms_flip@plain-flip-ts-check-interruptible at b-dp1.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl6/igt at kms_flip@plain-flip-ts-check-interruptible at b-dp1.html * igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt: - shard-glk: [PASS][36] -> [FAIL][37] ([i915#49]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk2/igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-glk2/igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][38] -> [FAIL][39] ([i915#1188]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][40] -> [FAIL][41] ([fdo#108145] / [i915#265]) +1 similar issue [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [PASS][42] -> [SKIP][43] ([fdo#109642] / [fdo#111068]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb2/igt at kms_psr2_su@page_flip.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-iclb7/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][44] -> [SKIP][45] ([fdo#109441]) +2 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [PASS][46] -> [INCOMPLETE][47] ([i915#69]) +1 similar issue [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl7/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl7/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at perf@polling-small-buf: - shard-iclb: [PASS][48] -> [FAIL][49] ([i915#1722]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb8/igt at perf@polling-small-buf.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-iclb3/igt at perf@polling-small-buf.html #### Possible fixes #### * igt at gem_ctx_persistence@replace at bcs0: - shard-skl: [FAIL][50] -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl8/igt at gem_ctx_persistence@replace at bcs0.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl1/igt at gem_ctx_persistence@replace at bcs0.html * igt at gem_exec_whisper@basic-forked-all: - shard-glk: [DMESG-WARN][52] ([i915#118] / [i915#95]) -> [PASS][53] +1 similar issue [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk1/igt at gem_exec_whisper@basic-forked-all.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-glk2/igt at gem_exec_whisper@basic-forked-all.html * igt at gem_mmap_gtt@cpuset-medium-copy-odd: - shard-skl: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl7/igt at gem_mmap_gtt@cpuset-medium-copy-odd.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl7/igt at gem_mmap_gtt@cpuset-medium-copy-odd.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-apl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57] [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl7/igt at kms_big_fb@linear-64bpp-rotate-180.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl2/igt at kms_big_fb@linear-64bpp-rotate-180.html - shard-glk: [DMESG-FAIL][58] ([i915#118] / [i915#95]) -> [PASS][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-glk9/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-snb: [SKIP][60] ([fdo#109271]) -> [PASS][61] +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-snb1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-snb1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][62] ([i915#1188]) -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl10/igt at kms_hdr@bpc-switch.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl6/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][64] ([fdo#108145] / [i915#265]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-tglb: [DMESG-WARN][66] ([i915#402]) -> [PASS][67] +1 similar issue [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb7/igt at kms_plane_multiple@atomic-pipe-a-tiling-x.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-tglb1/igt at kms_plane_multiple@atomic-pipe-a-tiling-x.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [SKIP][68] ([fdo#109441]) -> [PASS][69] +1 similar issue [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb5/igt at kms_psr@psr2_sprite_render.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-iclb2/igt at kms_psr@psr2_sprite_render.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][70] ([i915#180]) -> [PASS][71] +6 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@invalid-oa-metric-set-id: - shard-apl: [DMESG-WARN][72] ([i915#1635] / [i915#95]) -> [PASS][73] +16 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl3/igt at perf@invalid-oa-metric-set-id.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl1/igt at perf@invalid-oa-metric-set-id.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][74] ([i915#1820]) -> [PASS][75] [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-glk: [INCOMPLETE][76] ([i915#1958] / [i915#58] / [k.org#198133]) -> [TIMEOUT][77] ([i915#1958]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk7/igt at gem_exec_reloc@basic-concurrent16.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-glk6/igt at gem_exec_reloc@basic-concurrent16.html * igt at gem_userptr_blits@process-exit-mmap at gtt: - shard-apl: [SKIP][78] ([fdo#109271] / [i915#1635] / [i915#1699]) -> [SKIP][79] ([fdo#109271] / [i915#1699]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl6/igt at gem_userptr_blits@process-exit-mmap at gtt.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl8/igt at gem_userptr_blits@process-exit-mmap at gtt.html * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][80] ([i915#588]) -> [SKIP][81] ([i915#658]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][82] ([i915#468]) -> [FAIL][83] ([i915#454]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-tglb6/igt at i915_pm_dc@dc6-psr.html * igt at kms_chamelium@dp-edid-read: - shard-apl: [SKIP][84] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][85] ([fdo#109271] / [fdo#111827]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl3/igt at kms_chamelium@dp-edid-read.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl4/igt at kms_chamelium@dp-edid-read.html * igt at kms_cursor_legacy@pipe-d-forked-bo: - shard-apl: [SKIP][86] ([fdo#109271]) -> [SKIP][87] ([fdo#109271] / [i915#1635]) +6 similar issues [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl3/igt at kms_cursor_legacy@pipe-d-forked-bo.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl1/igt at kms_cursor_legacy@pipe-d-forked-bo.html * igt at kms_flip_tiling@flip-changes-tiling-yf: - shard-kbl: [DMESG-WARN][88] ([i915#93] / [i915#95]) -> [DMESG-FAIL][89] ([i915#95]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling-yf.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl6/igt at kms_flip_tiling@flip-changes-tiling-yf.html - shard-apl: [DMESG-WARN][90] ([i915#1635] / [i915#95]) -> [DMESG-FAIL][91] ([i915#1635] / [i915#95]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl4/igt at kms_flip_tiling@flip-changes-tiling-yf.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl1/igt at kms_flip_tiling@flip-changes-tiling-yf.html * igt at kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt: - shard-apl: [SKIP][92] ([fdo#109271] / [i915#1635]) -> [SKIP][93] ([fdo#109271]) +7 similar issues [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl8/igt at kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl4/igt at kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [DMESG-WARN][94] ([i915#180]) -> [INCOMPLETE][95] ([i915#155] / [i915#180] / [i915#648]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-kbl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: [FAIL][96] ([i915#265]) -> [DMESG-FAIL][97] ([i915#1635] / [i915#95]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/shard-apl6/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1699]: https://gitlab.freedesktop.org/drm/intel/issues/1699 [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8651 -> Patchwork_18004 CI-20190529: 20190529 CI_DRM_8651: f6210d1dd268f9e09e10d3704c768d7679a44f48 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5715: 3b6975c0f9e429c0c1f48c61a3417be9d68300cf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18004: c944d7fc0591a3d478712a5b7561525480f2f5d8 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18004/index.html From rafael at kernel.org Mon Jun 22 16:03:17 2020 From: rafael at kernel.org (Rafael J. Wysocki) Date: Mon, 22 Jun 2020 18:03:17 +0200 Subject: [Intel-gfx] [PATCH v3 01/15] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase In-Reply-To: <20200620121758.14836-2-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> <20200620121758.14836-2-hdegoede@redhat.com> Message-ID: <CAJZ5v0hheU2SaebNiLgRdxwC_dV44uSFWgAx2pr3w5ENeEF7EQ@mail.gmail.com> On Sat, Jun 20, 2020 at 2:18 PM Hans de Goede <hdegoede at redhat.com> wrote: > > The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM > controller gets poked from the _PS0 method of the graphics-card device: > > Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ > If (((Local0 & 0x03) == 0x03)) > { > PSAT &= 0xFFFFFFFC > Local1 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ > RSTA = Zero > RSTF = Zero > RSTA = One > RSTF = One > PWMB |= 0xC0000000 > PWMC = PWMB /* \_SB_.PCI0.GFX0.PWMB */ > } > > Where PSAT is the power-status register of the PWM controller, so if it > is in D3 when the GFX0 device's PS0 method runs then it will turn it on > and restore the PWM ctrl register value it saved from its PS3 handler. > Note not only does it restore it, it ors it with 0xC0000000 turning it > on at a time where we may not want it to get turned on at all. > > The pwm_get call which the i915 driver does to get a reference to the > PWM controller, already adds a device-link making the GFX0 device a > consumer of the PWM device. So it should already have been resumed when > the above AML runs and the AML should thus not do its undesirable poking > of the PWM controller register. > > But the PCI core powers on PCI devices in the no-irq resume phase and > thus calls the troublesome PS0 method in the no-irq resume phase. > Where as LPSS devices by default are resumed in the early resume phase. > > This commit sets the resume_from_noirq flag in the bsw_pwm_dev_desc > struct, so that Cherry Trail PWM controllers will be resumed in the > no-irq phase. Together with the device-link added by the pwm-get this > ensures that the PWM controller will be on when the troublesome PS0 > method runs, which stops it from poking the PWM controller. > > Signed-off-by: Hans de Goede <hdegoede at redhat.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki at intel.com> > --- > drivers/acpi/acpi_lpss.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c > index c5a5a179f49d..446e666b3466 100644 > --- a/drivers/acpi/acpi_lpss.c > +++ b/drivers/acpi/acpi_lpss.c > @@ -257,6 +257,7 @@ static const struct lpss_device_desc bsw_pwm_dev_desc = { > .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, > .prv_offset = 0x800, > .setup = bsw_pwm_setup, > + .resume_from_noirq = true, > }; > > static const struct lpss_device_desc byt_uart_dev_desc = { > -- > 2.26.2 > From rafael at kernel.org Mon Jun 22 16:04:27 2020 From: rafael at kernel.org (Rafael J. Wysocki) Date: Mon, 22 Jun 2020 18:04:27 +0200 Subject: [Intel-gfx] [PATCH v3 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once (at activation) In-Reply-To: <20200620121758.14836-3-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> <20200620121758.14836-3-hdegoede@redhat.com> Message-ID: <CAJZ5v0jYuKFmabZg+Y-rvXFF_EBfXKn=vOcyxFEs9bJugtvCfg@mail.gmail.com> On Sat, Jun 20, 2020 at 2:18 PM Hans de Goede <hdegoede at redhat.com> wrote: > > The DSDTs on most Cherry Trail devices have an ugly clutch where the PWM > controller gets turned off from the _PS3 method of the graphics-card dev: > > Method (_PS3, 0, Serialized) // _PS3: Power State 3 > { > ... > PWMB = PWMC /* \_SB_.PCI0.GFX0.PWMC */ > PSAT |= 0x03 > Local0 = PSAT /* \_SB_.PCI0.GFX0.PSAT */ > ... > } > > Where PSAT is the power-status register of the PWM controller. > > Since the i915 driver will do a pwm_get on the pwm device as it uses it to > control the LCD panel backlight, there is a device-link marking the i915 > device as a consumer of the pwm device. So that the PWM controller will > always be suspended after the i915 driver suspends (which is the right > thing to do). This causes the above GFX0 PS3 AML code to run before > acpi_lpss.c calls acpi_lpss_save_ctx(). > > So on these devices the PWM controller will already be off when > acpi_lpss_save_ctx() runs. This causes it to read/save all 1-s (0xffffffff) > as ctx register values. > > When these bogus values get restored on resume the PWM controller actually > keeps working, since most bits are reserved, but this does set bit 3 of > the LPSS General purpose register, which for the PWM controller has the > following function: "This bit is re-used to support 32kHz slow mode. > Default is 19.2MHz as PWM source clock". > > This causes the clock of the PWM controller to switch from 19.2MHz to > 32KHz, which is a slow-down of a factor 600. Surprisingly enough so far > there have been few bug reports about this. This is likely because the > i915 driver was hardcoding the PWM frequency to 46 KHz, which divided > by 600 would result in a PWM frequency of approx. 78 Hz, which mostly > still works fine. There are some bug reports about the LCD backlight > flickering after suspend/resume which are likely caused by this issue. > > But with the upcoming patch-series to finally switch the i915 drivers > code for external PWM controllers to use the atomic API and to honor > the PWM frequency specified in the video BIOS (VBT), this becomes a much > bigger problem. On most cases the VBT specifies either 200 Hz or 20 > KHz as PWM frequency, which with the mentioned issue ends up being either > 1/3 Hz, where the backlight actually visible blinks on and off every 3s, > or in 33 Hz and horrible flickering of the backlight. > > There are a number of possible solutions to this problem: > > 1. Make acpi_lpss_save_ctx() run before GFX0._PS3 > Pro: Clean solution from pov of not medling with save/restore ctx code > Con: As mentioned the current ordering is the right thing to do > Con: Requires assymmetry in at what suspend/resume phase we do the save vs > restore, requiring more suspend/resume ordering hacks in already > convoluted acpi_lpss.c suspend/resume code. > 2. Do some sort of save once mode for the LPSS ctx > Pro: Reasonably clean > Con: Needs a new LPSS flag + code changes to handle the flag > 3. Detect we have failed to save the ctx registers and do not restore them > Pro: Not PWM specific, might help with issues on other LPSS devices too > Con: If we can get away with not restoring the ctx why bother with it at > all? > 4. Do not save the ctx for CHT PWM controllers > Pro: Clean, as simple as dropping a flag? > Con: Not so simple as dropping a flag, needs a new flag to ensure that > we still do lpss_deassert_reset() on device activation. > 5. Make the pwm-lpss code fixup the LPSS-context registers > Pro: Keeps acpi_lpss.c code clean > Con: Moves knowledge of LPSS-context into the pwm-lpss.c code > > 1 and 5 both do not seem to be a desirable way forward. > > 3 and 4 seem ok, but they both assume that restoring the LPSS-context > registers is not necessary. I have done a couple of test and those do > show that restoring the LPSS-context indeed does not seem to be necessary > on devices using s2idle suspend (and successfully reaching S0i3). But I > have no hardware to test deep / S3 suspend. So I'm not sure that not > restoring the context is safe. > > That leaves solution 2, which is about as simple / clean as 3 and 4, > so this commit fixes the described problem by implementing a new > LPSS_SAVE_CTX_ONCE flag and setting that for the CHT PWM controllers. > > Signed-off-by: Hans de Goede <hdegoede at redhat.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki at intel.com> > --- > Changes in v2: > - Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX > --- > drivers/acpi/acpi_lpss.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c > index 446e666b3466..7e6db0f1d9ee 100644 > --- a/drivers/acpi/acpi_lpss.c > +++ b/drivers/acpi/acpi_lpss.c > @@ -67,7 +67,15 @@ ACPI_MODULE_NAME("acpi_lpss"); > #define LPSS_CLK_DIVIDER BIT(2) > #define LPSS_LTR BIT(3) > #define LPSS_SAVE_CTX BIT(4) > -#define LPSS_NO_D3_DELAY BIT(5) > +/* > + * For some devices the DSDT AML code for another device turns off the device > + * before our suspend handler runs, causing us to read/save all 1-s (0xffffffff) > + * as ctx register values. > + * Luckily these devices always use the same ctx register values, so we can > + * work around this by saving the ctx registers once on activation. > + */ > +#define LPSS_SAVE_CTX_ONCE BIT(5) > +#define LPSS_NO_D3_DELAY BIT(6) > > struct lpss_private_data; > > @@ -254,7 +262,7 @@ static const struct lpss_device_desc byt_pwm_dev_desc = { > }; > > static const struct lpss_device_desc bsw_pwm_dev_desc = { > - .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, > + .flags = LPSS_SAVE_CTX_ONCE | LPSS_NO_D3_DELAY, > .prv_offset = 0x800, > .setup = bsw_pwm_setup, > .resume_from_noirq = true, > @@ -885,9 +893,14 @@ static int acpi_lpss_activate(struct device *dev) > * we have to deassert reset line to be sure that ->probe() will > * recognize the device. > */ > - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) > + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) > lpss_deassert_reset(pdata); > > +#ifdef CONFIG_PM > + if (pdata->dev_desc->flags & LPSS_SAVE_CTX_ONCE) > + acpi_lpss_save_ctx(dev, pdata); > +#endif > + > return 0; > } > > @@ -1036,7 +1049,7 @@ static int acpi_lpss_resume(struct device *dev) > > acpi_lpss_d3_to_d0_delay(pdata); > > - if (pdata->dev_desc->flags & LPSS_SAVE_CTX) > + if (pdata->dev_desc->flags & (LPSS_SAVE_CTX | LPSS_SAVE_CTX_ONCE)) > acpi_lpss_restore_ctx(dev, pdata); > > return 0; > -- > 2.26.2 > From melissa.srw at gmail.com Mon Jun 22 16:37:19 2020 From: melissa.srw at gmail.com (Melissa Wen) Date: Mon, 22 Jun 2020 13:37:19 -0300 Subject: [Intel-gfx] [PATCH i-g-t 0/2] test/kms_cursor_crc: tie some loose ends in the prepare_crtc Message-ID: <cover.1592840756.git.melissa.srw@gmail.com> Using vkms, when running a sequence of subtests from kms_cursor_crc, several strange timeout failures occurred. For example, running the alpha-opaque cursor twice, the first run is successful and the second fails. In addition, if we run the entire test in a call (i.e.: sudo IGT_FORCE_DRIVER=vkms build/tests/kms_cursor_crc), the first subtest passes and the rest of the subtests fail - even those that succeed when run in isolation. igt_debugfs-DEBUG: Opening debugfs directory '/sys/kernel/debug/dri/0' igt_core-INFO: Timed out: Opening crc fd, and poll for first CRC. During my debugging process, I found two issues that were blocking execution and the solution is in this patchset: 1 - When a subtest fails, it exits and skips the cleaning step, leaving the pipe_crc allocated and blocked for the next subtest. The first patch fixes it by releasing any old pipe_crc before creating a new one. 2 - When the CRC capture process starts, it enters an endless wait; this seems to be related to the fact that the VKMS simulates vblank events, generating a time mismatch between vblank and CRC capture. Waiting for vblank before starting the capture process sets the pace, as shown in the second patch. Melissa Wen (2): test/kms_cursor_crc: release old pipe_crc before create a new one test/kms_cursor_crc: align the start of the CRC capture to a vblank tests/kms_cursor_crc.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.27.0 From melissa.srw at gmail.com Mon Jun 22 16:37:55 2020 From: melissa.srw at gmail.com (Melissa Wen) Date: Mon, 22 Jun 2020 13:37:55 -0300 Subject: [Intel-gfx] [PATCH i-g-t 1/2] test/kms_cursor_crc: release old pipe_crc before create a new one In-Reply-To: <cover.1592840756.git.melissa.srw@gmail.com> References: <cover.1592840756.git.melissa.srw@gmail.com> Message-ID: <0cef6a7b7dbd8510de62f0c17e8cd952cfa84678.1592840756.git.melissa.srw@gmail.com> When a subtest fails, it skips the cleanup, and its pipe_crc remains allocated. As a consequence, the following subtest also fails (timeout) when trying to create a new one. This patch releases any remaining pipe_crc to enable the creation of a new one for the next subtest. Signed-off-by: Melissa Wen <melissa.srw at gmail.com> --- tests/kms_cursor_crc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index f105e295..5976df5f 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -423,6 +423,8 @@ static void prepare_crtc(data_t *data, igt_output_t *output, igt_display_commit(display); /* create the pipe_crc object for this pipe */ + if (data->pipe_crc) + igt_pipe_crc_free(data->pipe_crc); data->pipe_crc = igt_pipe_crc_new(data->drm_fd, data->pipe, INTEL_PIPE_CRC_SOURCE_AUTO); -- 2.27.0 From melissa.srw at gmail.com Mon Jun 22 16:38:26 2020 From: melissa.srw at gmail.com (Melissa Wen) Date: Mon, 22 Jun 2020 13:38:26 -0300 Subject: [Intel-gfx] [PATCH i-g-t 2/2] test/kms_cursor_crc: align the start of the CRC capture to a vblank In-Reply-To: <cover.1592840756.git.melissa.srw@gmail.com> References: <cover.1592840756.git.melissa.srw@gmail.com> Message-ID: <a1dabf70afc82f5069871489b409200e41e6ac0c.1592840756.git.melissa.srw@gmail.com> When running subtests in sequence using vkms, the beginning of CRC capture process does not match the simulated vblank timing. This mismatch leads to an endless busy wait and, consequently, timeout failures for the remaining subtests in the test sequence. This patch sets the pace by waiting for vblank before starting the CRC capture. Signed-off-by: Melissa Wen <melissa.srw at gmail.com> --- tests/kms_cursor_crc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index 5976df5f..755c34ed 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -474,6 +474,7 @@ static void prepare_crtc(data_t *data, igt_output_t *output, igt_assert(data->batch); } + igt_wait_for_vblank(data->drm_fd, data->pipe); igt_pipe_crc_start(data->pipe_crc); } -- 2.27.0 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:07 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:07 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 0/8] tests/core_hotunplug: New subtests and enhancements Message-ID: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Add a bunch of new test variants, enhance debugging of hotunplug driver issues. v2: rebase on upstream Janusz Krzysztofik (8): tests/core_hotunplug: Duplicate debug messages in dmesg tests/core_hotunplug: Use PCI device sysfs entry, not DRM tests/core_hotunplug: Add unbind-unplug-rescan variant tests/core_hotunplug: Add 'lateclose before recover' variants tests/core_hotunplug: Add 'GEM address space' variant tests/core_hotunplug: Add 'GEM object' variant tests/core_hotunplug: Add 'PRIME handle' variant tests/core_hotunplug: Add 'GEM batch' variant tests/core_hotunplug.c | 330 +++++++++++++++++++++++++++++++++++------ 1 file changed, 283 insertions(+), 47 deletions(-) -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:08 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:08 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 1/8] tests/core_hotunplug: Duplicate debug messages in dmesg In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-2-janusz.krzysztofik@linux.intel.com> The purpose of debug messages displayed by the test is to make identification of a subtest phase that fails more easy. Since issues exhibited by the test are mostly reported to dmesg, print those debug messages to /dev/kmsg as well. v2: rebase on upstream Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index e03f3b945..826645b1f 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -49,6 +49,12 @@ struct hotunplug { /* Helpers */ +#define local_debug(msg...) \ +({ \ + igt_debug("%s: %s\n", __func__, msg); \ + igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ +}) + static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) { int len; @@ -68,9 +74,9 @@ static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) close(priv->fd.sysfs_dev); } -static void prepare(struct hotunplug *priv, char *buf, int buflen) +static inline void prepare(struct hotunplug *priv, char *buf, int buflen) { - igt_debug("opening device\n"); + local_debug("opening device"); priv->fd.drm = __drm_open_driver(DRIVER_ANY); igt_assert(priv->fd.drm >= 0); @@ -137,14 +143,14 @@ static void bus_rescan(int fd_sysfs_bus) close(fd_sysfs_bus); } -static void healthcheck(void) +static inline void healthcheck(void) { int fd_drm; /* device name may have changed, rebuild IGT device list */ igt_devices_scan(true); - igt_debug("reopening the device\n"); + local_debug("reopening the device"); fd_drm = __drm_open_driver(DRIVER_ANY); igt_abort_on_f(fd_drm < 0, "Device reopen failure"); @@ -181,13 +187,13 @@ static void unbind_rebind(void) prepare(&priv, buf, sizeof(buf)); - igt_debug("closing the device\n"); + local_debug("closing the device"); close(priv.fd.drm); - igt_debug("unbinding the driver from the device\n"); + local_debug("unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); - igt_debug("rebinding the driver to the device\n"); + local_debug("rebinding the driver to the device"); driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); healthcheck(); @@ -199,13 +205,13 @@ static void unplug_rescan(void) prepare(&priv, NULL, 0); - igt_debug("closing the device\n"); + local_debug("closing the device"); close(priv.fd.drm); - igt_debug("unplugging the device\n"); + local_debug("unplugging the device"); device_unplug(priv.fd.sysfs_dev); - igt_debug("recovering the device\n"); + local_debug("recovering the device"); bus_rescan(priv.fd.sysfs_bus); healthcheck(); @@ -218,13 +224,13 @@ static void hotunbind_lateclose(void) prepare(&priv, buf, sizeof(buf)); - igt_debug("hot unbinding the driver from the device\n"); + local_debug("hot unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); - igt_debug("rebinding the driver to the device\n"); + local_debug("rebinding the driver to the device"); driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); - igt_debug("late closing the unbound device instance\n"); + local_debug("late closing the unbound device instance"); close(priv.fd.drm); healthcheck(); @@ -236,13 +242,13 @@ static void hotunplug_lateclose(void) prepare(&priv, NULL, 0); - igt_debug("hot unplugging the device\n"); + local_debug("hot unplugging the device"); device_unplug(priv.fd.sysfs_dev); - igt_debug("recovering the device\n"); + local_debug("recovering the device"); bus_rescan(priv.fd.sysfs_bus); - igt_debug("late closing the removed device instance\n"); + local_debug("late closing the removed device instance"); close(priv.fd.drm); healthcheck(); -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:09 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:09 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 2/8] tests/core_hotunplug: Use PCI device sysfs entry, not DRM In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-3-janusz.krzysztofik@linux.intel.com> Future subtests may want to access PCI attributes of the device after driver unbind. Refactor prepare() helper. v2: rebase on upstream Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 68 +++++++++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 826645b1f..35eba9b8a 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -55,42 +55,54 @@ struct hotunplug { igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ }) -static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) +static inline int prepare_common(struct hotunplug *priv) { - int len; + int fd_sysfs_drm; + + local_debug("opening device"); + priv->fd.drm = __drm_open_driver(DRIVER_ANY); + igt_assert(priv->fd.drm >= 0); + + fd_sysfs_drm = igt_sysfs_open(priv->fd.drm); + igt_assert(fd_sysfs_drm >= 0); + + return fd_sysfs_drm; +} + +static inline void prepare_for_rebind(struct hotunplug *priv, + char *buf, int buflen) +{ + int fd_sysfs_drm, len; igt_assert(buflen); - priv->fd.sysfs_drv = openat(priv->fd.sysfs_dev, "device/driver", - O_DIRECTORY); - igt_assert(priv->fd.sysfs_drv >= 0); + fd_sysfs_drm = prepare_common(priv); + + priv->fd.sysfs_drv = openat(fd_sysfs_drm, "device/driver", O_DIRECTORY); - len = readlinkat(priv->fd.sysfs_dev, "device", buf, buflen - 1); + len = readlinkat(fd_sysfs_drm, "device", buf, buflen - 1); buf[len] = '\0'; priv->dev_bus_addr = strrchr(buf, '/'); - igt_assert(priv->dev_bus_addr++); - /* sysfs_dev no longer needed */ - close(priv->fd.sysfs_dev); + close(fd_sysfs_drm); + + igt_assert(priv->fd.sysfs_drv >= 0); + igt_assert(priv->dev_bus_addr++); } -static inline void prepare(struct hotunplug *priv, char *buf, int buflen) +static inline void prepare_for_rescan(struct hotunplug *priv) { - local_debug("opening device"); - priv->fd.drm = __drm_open_driver(DRIVER_ANY); - igt_assert(priv->fd.drm >= 0); + int fd_sysfs_drm = prepare_common(priv); - priv->fd.sysfs_dev = igt_sysfs_open(priv->fd.drm); - igt_assert(priv->fd.sysfs_dev >= 0); + priv->fd.sysfs_dev = openat(fd_sysfs_drm, "device", O_DIRECTORY); - if (buf) { - prepare_for_unbind(priv, buf, buflen); - } else { - /* prepare for bus rescan */ - priv->fd.sysfs_bus = openat(priv->fd.sysfs_dev, - "device/subsystem", O_DIRECTORY); - igt_assert(priv->fd.sysfs_bus >= 0); - } + priv->fd.sysfs_bus = openat(fd_sysfs_drm, "device/subsystem", + O_DIRECTORY); + + close(fd_sysfs_drm); + + igt_assert(priv->fd.sysfs_dev >= 0); + igt_assert(priv->fd.sysfs_bus >= 0); } static const char *failure; @@ -124,7 +136,7 @@ static void device_unplug(int fd_sysfs_dev) { failure = "Device unplug timeout!"; igt_set_timeout(60, failure); - igt_sysfs_set(fd_sysfs_dev, "device/remove", "1"); + igt_sysfs_set(fd_sysfs_dev, "remove", "1"); igt_reset_timeout(); failure = NULL; @@ -185,7 +197,7 @@ static void unbind_rebind(void) struct hotunplug priv; char buf[PATH_MAX]; - prepare(&priv, buf, sizeof(buf)); + prepare_for_rebind(&priv, buf, sizeof(buf)); local_debug("closing the device"); close(priv.fd.drm); @@ -203,7 +215,7 @@ static void unplug_rescan(void) { struct hotunplug priv; - prepare(&priv, NULL, 0); + prepare_for_rescan(&priv); local_debug("closing the device"); close(priv.fd.drm); @@ -222,7 +234,7 @@ static void hotunbind_lateclose(void) struct hotunplug priv; char buf[PATH_MAX]; - prepare(&priv, buf, sizeof(buf)); + prepare_for_rebind(&priv, buf, sizeof(buf)); local_debug("hot unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); @@ -240,7 +252,7 @@ static void hotunplug_lateclose(void) { struct hotunplug priv; - prepare(&priv, NULL, 0); + prepare_for_rescan(&priv); local_debug("hot unplugging the device"); device_unplug(priv.fd.sysfs_dev); -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:10 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:10 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 3/8] tests/core_hotunplug: Add unbind-unplug-rescan variant In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-4-janusz.krzysztofik@linux.intel.com> Check if this 3-step procedure exhibits any issues with device recover after unplug. Such issues may indicate insufficient device hardware re-initialization performed by the device driver, or other kernel bugs outside the driver code. v2: rebase on upstream Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 35eba9b8a..a4809720b 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -211,6 +211,35 @@ static void unbind_rebind(void) healthcheck(); } +static void unbind_unplug_rescan(void) +{ + struct hotunplug priv; + char buf[PATH_MAX]; + + /* prepare for unbind */ + prepare_for_rebind(&priv, buf, sizeof(buf)); + + /* also prepare for unplug */ + local_debug("closing the device"); + close(priv.fd.drm); + prepare_for_rescan(&priv); + + local_debug("closing the device"); + close(priv.fd.drm); + + local_debug("unbinding the driver from the device"); + driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); + close(priv.fd.sysfs_drv); + + local_debug("unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + static void unplug_rescan(void) { struct hotunplug priv; @@ -290,14 +319,21 @@ igt_main close(fd_drm); } - igt_describe("Check if the driver can be cleanly unbound from a device believed to be closed"); + igt_describe("Check if the driver can be cleanly unbound from a device believed to be closed, then rebound"); igt_subtest("unbind-rebind") unbind_rebind(); igt_fixture igt_abort_on_f(failure, "%s\n", failure); - igt_describe("Check if a device believed to be closed can be cleanly unplugged"); + igt_describe("Check if a device with the driver unbound from it can be cleanly recovered after being unplugged\n"); + igt_subtest("unbind-unplug-rescan") + unbind_unplug_rescan(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device believed to be closed can be cleanly unplugged and recovered"); igt_subtest("unplug-rescan") unplug_rescan(); -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:11 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:11 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 4/8] tests/core_hotunplug: Add 'lateclose before recover' variants In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-5-janusz.krzysztofik@linux.intel.com> If a GPU gets wedged during driver rebind or device re-plug for some reason, current hotunbind/hotunplug test variants may time out before lateclose phase, resulting in incomplete CI reports. Let's rename those variants to more adequate hotrebind/hotreplug-lateclose and add new variants focused on exercising the lateclose phase regardless of potential rebind/re-plug issues under old names. v2: rebase on upstream Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 57 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 54 insertions(+), 3 deletions(-) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index a4809720b..0892e1927 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -268,6 +268,43 @@ static void hotunbind_lateclose(void) local_debug("hot unbinding the driver from the device"); driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); + local_debug("late closing the unbound device instance"); + close(priv.fd.drm); + + local_debug("rebinding the driver to the device"); + driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); + + healthcheck(); +} + +static void hotunplug_lateclose(void) +{ + struct hotunplug priv; + + prepare_for_rescan(&priv); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + +static void hotrebind_lateclose(void) +{ + struct hotunplug priv; + char buf[PATH_MAX]; + + prepare_for_rebind(&priv, buf, sizeof(buf)); + + local_debug("hot unbinding the driver from the device"); + driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); + local_debug("rebinding the driver to the device"); driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); @@ -277,7 +314,7 @@ static void hotunbind_lateclose(void) healthcheck(); } -static void hotunplug_lateclose(void) +static void hotreplug_lateclose(void) { struct hotunplug priv; @@ -340,17 +377,31 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); - igt_describe("Check if the driver can be cleanly unbound from a still open device, then released"); + igt_describe("Check if the driver can be cleanly unbound from a still open device, then released and rebound"); igt_subtest("hotunbind-lateclose") hotunbind_lateclose(); igt_fixture igt_abort_on_f(failure, "%s\n", failure); - igt_describe("Check if a still open device can be cleanly unplugged, then released"); + igt_describe("Check if a still open device can be cleanly unplugged, then released and recovered"); igt_subtest("hotunplug-lateclose") hotunplug_lateclose(); igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if the driver can be cleanly unbound from an open device and rebound back, then released"); + igt_subtest("hotrebind-lateclose") + hotrebind_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a still open device can be cleanly unplugged and recovered, then released"); + igt_subtest("hotreplug-lateclose") + hotreplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:12 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:12 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 5/8] tests/core_hotunplug: Add 'GEM address space' variant In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-6-janusz.krzysztofik@linux.intel.com> Verify if an additional address space associated with an open device file descriptor is cleaned up correctly on device hotunplug. v2: rebase on upstream, update includes order Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 0892e1927..18a963564 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -30,6 +30,7 @@ #include <unistd.h> #include "i915/gem.h" +#include "i915/gem_vm.h" #include "igt.h" #include "igt_device_scan.h" #include "igt_kmod.h" @@ -332,6 +333,29 @@ static void hotreplug_lateclose(void) healthcheck(); } +static void vm_hotunplug_lateclose(void) +{ + struct hotunplug priv; + + prepare_for_rescan(&priv); + + gem_require_vm(priv.fd.drm); + + local_debug("creating additional GEM user address space"); + igt_ignore_warn(gem_vm_create(priv.fd.drm)); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -404,4 +428,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a still open device with extra GEM address space can be cleanly unplugged, then released and recovered"); + igt_subtest("vm-hotunplug-lateclose") + vm_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:13 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:13 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 6/8] tests/core_hotunplug: Add 'GEM object' variant In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-7-janusz.krzysztofik@linux.intel.com> GEM objects belonging to user file descriptors still open on device hotunplug may exhibit still more driver issues. Add a subtest that implements this scenario. v2: rebase on upstream Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 18a963564..c30d98a69 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -356,6 +356,29 @@ static void vm_hotunplug_lateclose(void) healthcheck(); } +static void gem_hotunplug_lateclose(void) +{ + struct hotunplug priv; + + prepare_for_rescan(&priv); + + igt_require_gem(priv.fd.drm); + + local_debug("creating a GEM user object"); + igt_ignore_warn(gem_create(priv.fd.drm, 4096)); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -435,4 +458,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device with a still open GEM object can be cleanly unplugged, then released and recovered"); + igt_subtest("gem-hotunplug-lateclose") + gem_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:14 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:14 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 7/8] tests/core_hotunplug: Add 'PRIME handle' variant In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-8-janusz.krzysztofik@linux.intel.com> Even if all device file descriptors are closed on device hotunplug, PRIME exported objects may still exists, referenced by still open dma-buf file handles. Add a subtest that keeps such handle open on device hotunplug. v2: rebase on upstream Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index c30d98a69..7cb699cc2 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -379,6 +379,35 @@ static void gem_hotunplug_lateclose(void) healthcheck(); } +static void prime_hotunplug_lateclose(void) +{ + struct hotunplug priv; + uint32_t handle; + int dmabuf; + + prepare_for_rescan(&priv); + + igt_require_gem(priv.fd.drm); + + local_debug("creating and PRIME-exporting a GEM object"); + handle = gem_create(priv.fd.drm, 4096); + dmabuf = prime_handle_to_fd(priv.fd.drm, handle); + + local_debug("closing the device"); + close(priv.fd.drm); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the PRIME file handle"); + close(dmabuf); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -465,4 +494,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device with a still open PRIME-exported object can be cleanly unplugged, then released and recovered"); + igt_subtest("prime-hotunplug-lateclose") + prime_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From janusz.krzysztofik at linux.intel.com Mon Jun 22 16:44:15 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Mon, 22 Jun 2020 18:44:15 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 8/8] tests/core_hotunplug: Add 'GEM batch' variant In-Reply-To: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> Message-ID: <20200622164415.30352-9-janusz.krzysztofik@linux.intel.com> Verify if a device with a GEM batch job still running on a GPU can be hot-unplugged cleanly and released, then recovered. v2: rebase on upstream Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> --- tests/core_hotunplug.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c index 7cb699cc2..672ff661d 100644 --- a/tests/core_hotunplug.c +++ b/tests/core_hotunplug.c @@ -33,6 +33,7 @@ #include "i915/gem_vm.h" #include "igt.h" #include "igt_device_scan.h" +#include "igt_dummyload.h" #include "igt_kmod.h" #include "igt_sysfs.h" @@ -408,6 +409,32 @@ static void prime_hotunplug_lateclose(void) healthcheck(); } +static void batch_hotunplug_lateclose(void) +{ + struct hotunplug priv; + igt_spin_t *spin; + + prepare_for_rescan(&priv); + + igt_require_gem(priv.fd.drm); + + local_debug("running dummy load"); + spin = __igt_spin_new(priv.fd.drm, .flags = IGT_SPIN_POLL_RUN | + IGT_SPIN_NO_PREEMPTION); + igt_spin_busywait_until_started(spin); + + local_debug("hot unplugging the device"); + device_unplug(priv.fd.sysfs_dev); + + local_debug("late closing the removed device instance"); + close(priv.fd.drm); + + local_debug("recovering the device"); + bus_rescan(priv.fd.sysfs_bus); + + healthcheck(); +} + /* Main */ igt_main @@ -501,4 +528,11 @@ igt_main igt_fixture igt_abort_on_f(failure, "%s\n", failure); + + igt_describe("Check if a device with a still running batch can be cleanly unplugged, then released and recovered"); + igt_subtest("batch-hotunplug-lateclose") + batch_hotunplug_lateclose(); + + igt_fixture + igt_abort_on_f(failure, "%s\n", failure); } -- 2.21.1 From ville.syrjala at linux.intel.com Mon Jun 22 17:02:46 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 22 Jun 2020 20:02:46 +0300 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> Message-ID: <20200622170246.GP6112@intel.com> On Mon, Jun 22, 2020 at 11:44:58AM +0000, Shankar, Uma wrote: > > > > > > -----Original Message----- > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > Sent: Thursday, June 11, 2020 9:31 PM > > > > > To: Shankar, Uma <uma.shankar at intel.com> > > > > > Cc: intel-gfx at lists.freedesktop.org; jani.nikula at linux.intel.com; > > > > > Mun, Gwan- gyeong <gwan-gyeong.mun at intel.com> > > > > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes > > > > > readback for LSPCON > > > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > > This will help align the implementation with state readback > > > > > > > infrastructure. > > > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > > ++++++++++++++++++++- > > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct > > > > > > > intel_encoder > > > > > *encoder, > > > > > > > buf, ret); > > > > > > > } > > > > > > > > > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > > +drm_dp_aux *aux) { > > > > > > > + int ret; > > > > > > > + u32 val = 0; > > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > > + > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > + if (ret < 0) { > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > + return false; > > > > > > > + } > > > > > > > + > > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > > + return true; > > > > > > > + > > > > > > > + return false; > > > > > > > > > > > > return val & ...; > > > > > > > > > > > > > +} > > > > > > > + > > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > > +drm_dp_aux *aux) { > > > > > > > + int ret; > > > > > > > + u32 val = 0; > > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > > + > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > + if (ret < 0) { > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > + return false; > > > > > > > + } > > > > > > > + > > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > > + return true; > > > > > > > + > > > > > > > + return false; > > > > > > > +} > > > > > > > + > > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > > > const struct intel_crtc_state *pipe_config) { > > > > > > > - /* FIXME actually read this from the hw */ > > > > > > > - return 0; > > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > > > + bool infoframes_enabled; > > > > > > > + u32 mask = 0; > > > > > > > + u32 val; > > > > > > > + > > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > > + infoframes_enabled = > > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > > + else > > > > > > > + infoframes_enabled = > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); > > > > > > > + > > > > > > > + if (infoframes_enabled) > > > > > > > + return true; > > > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > > > Actually since we're dealing with both the LSPCON specific stuff > > > > > and DIP stuff for the DRM infoframe I think we should stop using > > > > > using intel_hdmi_infoframes_enabled(), and instead provide a > > > > > LSPCON specific replacement for it. That way we can directly > > > > > return the abstract bitmask instead of pretending to return a bitmask of > > the DIP bits. > > We have DP (VSC etc) packets also managed as HDMI infoframes only. We can keep the > same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW for AVI and similarly VIDEO_DIP_ENABLE_GMP_HSW > for DRM (HDR metadata). This will help all the helper align appropriately even in the intel_dump_pipe_config. intel_dump_infoframe() does not use any platform specific bitmasks. So I don't understand what you're talking about here. > > Will fix this accordingly and send the next version. Hope this is ok. > > > > > Sure, will fix this and resend the next version. > > > > > > > > > > > > > > > > Also my question "how do we turn off infoframes once enabled?" > > > > > > from > > > > > > https://patchwork.freedesktop.org/patch/351719/?series=72928&rev > > > > > > =1 > > > > > > still remains unanswered... > > > > > > > > For the AVI infoframe we generally compute and change the respective > > > > values. If no change is requested and computed we can let the > > > > existing infoframes be transmitted. AFAIK there is no mechanism > > > > called out, to explicitly disable this on Lspcon. Have not seen any > > > > issues due to this, so > > > hoping that it may be safe even if they are enabled. > > > > > > It's not valid to transmit infoframes to DVI sinks. > > > > With your fix, we won't be enabling or setting the infoframe on DVI sinks. > > If I understand correctly, we may have issue if we connect HDMI (where we > > would have sent the infoframe) and later unplug and plug a DVI sink. With > > unplug if Lspcon is not resetting this internally then this will be a problem. I will > > try to get this information on Lspcon behavior. > > Hi Ville, > Searched various docs on LSPCON and couldn't find any mention of disabling infoframe. > Reached out to few folks who were interfacing with Lspcon vendors and got this finally > clarified. The expectation is that LSPCON will reset stuff on unplug and will not send infoframes to DVI sink, > so from source side we don't need to explicitly disable them. Lspcon will take care of this, this was > tested for compliance as well by them. Unplug is irrelevant. We also have the property by which the user can force the inforframes off. > > I will share the updated series adding your patch stopping infoframes to be sent to DVI sinks. > Please review the same. > > Thank & Regards, > Uma Shankar > > > > > > > > > I am planning to take your patch from the series and float along > > > > with this series, adding check for DRM Infoframes also. Hope that is ok ? > > > > > > > > Thanks Ville for your feedback. > > > > > > > > Regards, > > > > Uma Shankar > > > > > > > > > > > + > > > > > > > + if (lspcon->hdr_supported) { > > > > > > > + val = intel_de_read(dev_priv, > > > > > > > + HSW_TVIDEO_DIP_CTL(pipe_config- > > > > > >cpu_transcoder)); > > > > > > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > > > > > > + > > > > > > > + if (val & mask) > > > > > > > + return val & mask; > > > > > > > + } > > > > > > > + > > > > > > > + return false; > > > > > > > } > > > > > > > > > > > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > > > > > > -- > > > > > > > 2.22.0 > > > > > > > > > > > > -- > > > > > > Ville Syrj?l? > > > > > > Intel > > > > > > > > > > -- > > > > > Ville Syrj?l? > > > > > Intel > > > > > > -- > > > Ville Syrj?l? > > > Intel -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Mon Jun 22 17:06:51 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 22 Jun 2020 20:06:51 +0300 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200622154921.GA25163@ideak-desk.fi.intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> Message-ID: <20200622170651.GQ6112@intel.com> On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote: > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote: > > Modify the helper to add a fixed delay or poll with timeout > > based on platform specification in bothe enable and disable > > cases so check for either Idle bit set (DDI_BUF_CTL is idle > > for disable case) or check for Idle bit = 0 (non idle for > > DDI BUF enable case) > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++--------- > > 1 file changed, 21 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index ca7bb2294d2b..e4738c3b6d44 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > } > > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > - enum port port) > > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ? I'd just make it two functions. Avoids that stupid boolean parameter. > > > + enum port port, bool idle) > > { > > - i915_reg_t reg = DDI_BUF_CTL(port); > > - int i; > > - > > - for (i = 0; i < 16; i++) { > > - udelay(1); > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > - return; > > + if (idle) { > > + if (IS_BROXTON(dev_priv)) > > + udelay(16); > > + else > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 16)) > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > + port_name(port)); > > + } else { > > + if (INTEL_GEN(dev_priv) < 10) > > + udelay(600); > > + else > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 600)) > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > + port_name(port)); > > } > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > - port_name(port)); > > + > > since we can only guarantee a minimum delay or timeout, imo it could be just: > > if (BXT && !active || GEN <= 9 && active) { > usleep_range(600, 1000); > return; > } > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600)) > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n", > port, active ? "active" : "idle")); > > > > } > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); > > > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E); > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true); > > > > /* Reset FDI_RX_MISC pwrdn lanes */ > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, > > intel_ddi_disable_fec_state(encoder, crtc_state); > > > > if (wait) > > - intel_wait_ddi_buf_idle(dev_priv, port); > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > } > > > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); > > > > if (wait) > > - intel_wait_ddi_buf_idle(dev_priv, port); > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > } > > > > dp_tp_ctl = DP_TP_CTL_ENABLE | > > The DSI code could also use the new helper. > > > -- > > 2.19.1 > > -- Ville Syrj?l? Intel From uma.shankar at intel.com Mon Jun 22 17:17:50 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 22 Jun 2020 17:17:50 +0000 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200622170246.GP6112@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> <20200622170246.GP6112@intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> > > > > > > -----Original Message----- > > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > Sent: Thursday, June 11, 2020 9:31 PM > > > > > > To: Shankar, Uma <uma.shankar at intel.com> > > > > > > Cc: intel-gfx at lists.freedesktop.org; > > > > > > jani.nikula at linux.intel.com; Mun, Gwan- gyeong > > > > > > <gwan-gyeong.mun at intel.com> > > > > > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes > > > > > > readback for LSPCON > > > > > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > > > This will help align the implementation with state > > > > > > > > readback infrastructure. > > > > > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > > > --- > > > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > > > ++++++++++++++++++++- > > > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct > > > > > > > > intel_encoder > > > > > > *encoder, > > > > > > > > buf, ret); > > > > > > > > } > > > > > > > > > > > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > + int ret; > > > > > > > > + u32 val = 0; > > > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > > > + > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > + if (ret < 0) { > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > + return false; > > > > > > > > + } > > > > > > > > + > > > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > > > + return true; > > > > > > > > + > > > > > > > > + return false; > > > > > > > > > > > > > > return val & ...; > > > > > > > > > > > > > > > +} > > > > > > > > + > > > > > > > > +static bool > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > + int ret; > > > > > > > > + u32 val = 0; > > > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > > > + > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > + if (ret < 0) { > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > + return false; > > > > > > > > + } > > > > > > > > + > > > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > > > + return true; > > > > > > > > + > > > > > > > > + return false; > > > > > > > > +} > > > > > > > > + > > > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > > > > const struct intel_crtc_state *pipe_config) { > > > > > > > > - /* FIXME actually read this from the hw */ > > > > > > > > - return 0; > > > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > > > > + bool infoframes_enabled; > > > > > > > > + u32 mask = 0; > > > > > > > > + u32 val; > > > > > > > > + > > > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > > > + infoframes_enabled = > > > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > > > + else > > > > > > > > + infoframes_enabled = > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux) > > > > > > > > +; > > > > > > > > + > > > > > > > > + if (infoframes_enabled) > > > > > > > > + return true; > > > > > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > > > > > Actually since we're dealing with both the LSPCON specific > > > > > > stuff and DIP stuff for the DRM infoframe I think we should > > > > > > stop using using intel_hdmi_infoframes_enabled(), and instead > > > > > > provide a LSPCON specific replacement for it. That way we can > > > > > > directly return the abstract bitmask instead of pretending to > > > > > > return a bitmask of > > > the DIP bits. > > > > We have DP (VSC etc) packets also managed as HDMI infoframes only. We > > can keep the same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW for AVI and > > similarly VIDEO_DIP_ENABLE_GMP_HSW for DRM (HDR metadata). This will > help all the helper align appropriately even in the intel_dump_pipe_config. > > intel_dump_infoframe() does not use any platform specific bitmasks. > So I don't understand what you're talking about here. What I meant is that if we continue to use the existing values and bitmask, we can have lspcon infoframes_enabled return the appropriate type of infoframe which is active (as you suggested) and later with intel_dump_pipe_config when it checks for intel_hdmi_infoframe_enable, we will get a matching value in pipe_config->infoframes.enable and be able to dump them as well. Hope I am on same page with you here. > > > > Will fix this accordingly and send the next version. Hope this is ok. > > > > > > > Sure, will fix this and resend the next version. > > > > > > > > > > > > > > > > > > > Also my question "how do we turn off infoframes once enabled?" > > > > > > > from > > > > > > > https://patchwork.freedesktop.org/patch/351719/?series=72928 > > > > > > > &rev > > > > > > > =1 > > > > > > > still remains unanswered... > > > > > > > > > > For the AVI infoframe we generally compute and change the > > > > > respective values. If no change is requested and computed we can > > > > > let the existing infoframes be transmitted. AFAIK there is no > > > > > mechanism called out, to explicitly disable this on Lspcon. Have > > > > > not seen any issues due to this, so > > > > hoping that it may be safe even if they are enabled. > > > > > > > > It's not valid to transmit infoframes to DVI sinks. > > > > > > With your fix, we won't be enabling or setting the infoframe on DVI sinks. > > > If I understand correctly, we may have issue if we connect HDMI > > > (where we would have sent the infoframe) and later unplug and plug a > > > DVI sink. With unplug if Lspcon is not resetting this internally > > > then this will be a problem. I will try to get this information on Lspcon > behavior. > > > > Hi Ville, > > Searched various docs on LSPCON and couldn't find any mention of disabling > infoframe. > > Reached out to few folks who were interfacing with Lspcon vendors and > > got this finally clarified. The expectation is that LSPCON will reset > > stuff on unplug and will not send infoframes to DVI sink, so from > > source side we don't need to explicitly disable them. Lspcon will take care of > this, this was tested for compliance as well by them. > > Unplug is irrelevant. We also have the property by which the user can force the > inforframes off. > > > > > I will share the updated series adding your patch stopping infoframes to be > sent to DVI sinks. > > Please review the same. > > > > Thank & Regards, > > Uma Shankar > > > > > > > > > > > > I am planning to take your patch from the series and float along > > > > > with this series, adding check for DRM Infoframes also. Hope that is ok ? > > > > > > > > > > Thanks Ville for your feedback. > > > > > > > > > > Regards, > > > > > Uma Shankar > > > > > > > > > > > > > + > > > > > > > > + if (lspcon->hdr_supported) { > > > > > > > > + val = intel_de_read(dev_priv, > > > > > > > > + HSW_TVIDEO_DIP_CTL(pipe_config- > > > > > > >cpu_transcoder)); > > > > > > > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > > > > > > > + > > > > > > > > + if (val & mask) > > > > > > > > + return val & mask; > > > > > > > > + } > > > > > > > > + > > > > > > > > + return false; > > > > > > > > } > > > > > > > > > > > > > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > > > > > > > -- > > > > > > > > 2.22.0 > > > > > > > > > > > > > > -- > > > > > > > Ville Syrj?l? > > > > > > > Intel > > > > > > > > > > > > -- > > > > > > Ville Syrj?l? > > > > > > Intel > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > -- > Ville Syrj?l? > Intel From uma.shankar at intel.com Mon Jun 22 17:21:50 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 22 Jun 2020 17:21:50 +0000 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> <20200622170246.GP6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2D4@BGSMSX104.gar.corp.intel.com> > > > > > > > -----Original Message----- > > > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > Sent: Thursday, June 11, 2020 9:31 PM > > > > > > > To: Shankar, Uma <uma.shankar at intel.com> > > > > > > > Cc: intel-gfx at lists.freedesktop.org; > > > > > > > jani.nikula at linux.intel.com; Mun, Gwan- gyeong > > > > > > > <gwan-gyeong.mun at intel.com> > > > > > > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes > > > > > > > readback for LSPCON > > > > > > > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > > > > This will help align the implementation with state > > > > > > > > > readback infrastructure. > > > > > > > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > > > > --- > > > > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > > > > ++++++++++++++++++++- > > > > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct > > > > > > > > > intel_encoder > > > > > > > *encoder, > > > > > > > > > buf, ret); > > > > > > > > > } > > > > > > > > > > > > > > > > > > +static bool > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > + int ret; > > > > > > > > > + u32 val = 0; > > > > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > > > > + > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > + if (ret < 0) { > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > > + return false; > > > > > > > > > + } > > > > > > > > > + > > > > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > > > > + return true; > > > > > > > > > + > > > > > > > > > + return false; > > > > > > > > > > > > > > > > return val & ...; > > > > > > > > > > > > > > > > > +} > > > > > > > > > + > > > > > > > > > +static bool > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > + int ret; > > > > > > > > > + u32 val = 0; > > > > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > > > > + > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > + if (ret < 0) { > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > > + return false; > > > > > > > > > + } > > > > > > > > > + > > > > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > > > > + return true; > > > > > > > > > + > > > > > > > > > + return false; > > > > > > > > > +} > > > > > > > > > + > > > > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > > > > > const struct intel_crtc_state *pipe_config) { > > > > > > > > > - /* FIXME actually read this from the hw */ > > > > > > > > > - return 0; > > > > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > > > > > + bool infoframes_enabled; > > > > > > > > > + u32 mask = 0; > > > > > > > > > + u32 val; > > > > > > > > > + > > > > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > > > > + infoframes_enabled = > > > > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > > > > + else > > > > > > > > > + infoframes_enabled = > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->au > > > > > > > > > +x) > > > > > > > > > +; > > > > > > > > > + > > > > > > > > > + if (infoframes_enabled) > > > > > > > > > + return true; > > > > > > > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > > > > > > > Actually since we're dealing with both the LSPCON specific > > > > > > > stuff and DIP stuff for the DRM infoframe I think we should > > > > > > > stop using using intel_hdmi_infoframes_enabled(), and > > > > > > > instead provide a LSPCON specific replacement for it. That > > > > > > > way we can directly return the abstract bitmask instead of > > > > > > > pretending to return a bitmask of > > > > the DIP bits. > > > > > > We have DP (VSC etc) packets also managed as HDMI infoframes only. > > > We can keep the same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW for > > > AVI and similarly VIDEO_DIP_ENABLE_GMP_HSW for DRM (HDR metadata). > > > This will > > help all the helper align appropriately even in the intel_dump_pipe_config. > > > > intel_dump_infoframe() does not use any platform specific bitmasks. > > So I don't understand what you're talking about here. > > What I meant is that if we continue to use the existing values and bitmask, we > can have lspcon infoframes_enabled return the appropriate type of infoframe > which is active (as you suggested) and later with intel_dump_pipe_config when it > checks for intel_hdmi_infoframe_enable, we will get a matching value in > pipe_config->infoframes.enable and be able to dump them as well. Hope I am on > same page with you here. > > > > > > > Will fix this accordingly and send the next version. Hope this is ok. > > > > > > > > > Sure, will fix this and resend the next version. > > > > > > > > > > > > > > > > > > > > > > Also my question "how do we turn off infoframes once enabled?" > > > > > > > > from > > > > > > > > https://patchwork.freedesktop.org/patch/351719/?series=729 > > > > > > > > 28 > > > > > > > > &rev > > > > > > > > =1 > > > > > > > > still remains unanswered... > > > > > > > > > > > > For the AVI infoframe we generally compute and change the > > > > > > respective values. If no change is requested and computed we > > > > > > can let the existing infoframes be transmitted. AFAIK there is > > > > > > no mechanism called out, to explicitly disable this on Lspcon. > > > > > > Have not seen any issues due to this, so > > > > > hoping that it may be safe even if they are enabled. > > > > > > > > > > It's not valid to transmit infoframes to DVI sinks. > > > > > > > > With your fix, we won't be enabling or setting the infoframe on DVI sinks. > > > > If I understand correctly, we may have issue if we connect HDMI > > > > (where we would have sent the infoframe) and later unplug and plug > > > > a DVI sink. With unplug if Lspcon is not resetting this internally > > > > then this will be a problem. I will try to get this information on > > > > Lspcon > > behavior. > > > > > > Hi Ville, > > > Searched various docs on LSPCON and couldn't find any mention of > > > disabling > > infoframe. > > > Reached out to few folks who were interfacing with Lspcon vendors > > > and got this finally clarified. The expectation is that LSPCON will > > > reset stuff on unplug and will not send infoframes to DVI sink, so > > > from source side we don't need to explicitly disable them. Lspcon > > > will take care of > > this, this was tested for compliance as well by them. > > > > Unplug is irrelevant. We also have the property by which the user can > > force the inforframes off. Oh ok, but it seems we don't have an option to disable them on LSPCON. They have not added any interface for that unfortunately. Regards, Uma Shankar > > > > > > I will share the updated series adding your patch stopping > > > infoframes to be > > sent to DVI sinks. > > > Please review the same. > > > > > > Thank & Regards, > > > Uma Shankar > > > > > > > > > > > > > > > I am planning to take your patch from the series and float > > > > > > along with this series, adding check for DRM Infoframes also. Hope that > is ok ? > > > > > > > > > > > > Thanks Ville for your feedback. > > > > > > > > > > > > Regards, > > > > > > Uma Shankar > > > > > > > > > > > > > > > + > > > > > > > > > + if (lspcon->hdr_supported) { > > > > > > > > > + val = intel_de_read(dev_priv, > > > > > > > > > + HSW_TVIDEO_DIP_CTL(pipe_config- > > > > > > > >cpu_transcoder)); > > > > > > > > > + mask |= VIDEO_DIP_ENABLE_GMP_HSW; > > > > > > > > > + > > > > > > > > > + if (val & mask) > > > > > > > > > + return val & mask; > > > > > > > > > + } > > > > > > > > > + > > > > > > > > > + return false; > > > > > > > > > } > > > > > > > > > > > > > > > > > > void lspcon_resume(struct intel_lspcon *lspcon) > > > > > > > > > -- > > > > > > > > > 2.22.0 > > > > > > > > > > > > > > > > -- > > > > > > > > Ville Syrj?l? > > > > > > > > Intel > > > > > > > > > > > > > > -- > > > > > > > Ville Syrj?l? > > > > > > > Intel > > > > > > > > > > -- > > > > > Ville Syrj?l? > > > > > Intel > > > > -- > > Ville Syrj?l? > > Intel From ville.syrjala at linux.intel.com Mon Jun 22 17:40:28 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 22 Jun 2020 20:40:28 +0300 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> <20200622170246.GP6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> Message-ID: <20200622174028.GR6112@intel.com> On Mon, Jun 22, 2020 at 05:17:50PM +0000, Shankar, Uma wrote: > > > > > > > > -----Original Message----- > > > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > Sent: Thursday, June 11, 2020 9:31 PM > > > > > > > To: Shankar, Uma <uma.shankar at intel.com> > > > > > > > Cc: intel-gfx at lists.freedesktop.org; > > > > > > > jani.nikula at linux.intel.com; Mun, Gwan- gyeong > > > > > > > <gwan-gyeong.mun at intel.com> > > > > > > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes > > > > > > > readback for LSPCON > > > > > > > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > > > > This will help align the implementation with state > > > > > > > > > readback infrastructure. > > > > > > > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > > > > --- > > > > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > > > > ++++++++++++++++++++- > > > > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct > > > > > > > > > intel_encoder > > > > > > > *encoder, > > > > > > > > > buf, ret); > > > > > > > > > } > > > > > > > > > > > > > > > > > > +static bool _lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > + int ret; > > > > > > > > > + u32 val = 0; > > > > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > > > > + > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > + if (ret < 0) { > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > > + return false; > > > > > > > > > + } > > > > > > > > > + > > > > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > > > > + return true; > > > > > > > > > + > > > > > > > > > + return false; > > > > > > > > > > > > > > > > return val & ...; > > > > > > > > > > > > > > > > > +} > > > > > > > > > + > > > > > > > > > +static bool > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > + int ret; > > > > > > > > > + u32 val = 0; > > > > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > > > > + > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > + if (ret < 0) { > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > > + return false; > > > > > > > > > + } > > > > > > > > > + > > > > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > > > > + return true; > > > > > > > > > + > > > > > > > > > + return false; > > > > > > > > > +} > > > > > > > > > + > > > > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > > > > > const struct intel_crtc_state *pipe_config) { > > > > > > > > > - /* FIXME actually read this from the hw */ > > > > > > > > > - return 0; > > > > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > > > > > + bool infoframes_enabled; > > > > > > > > > + u32 mask = 0; > > > > > > > > > + u32 val; > > > > > > > > > + > > > > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > > > > + infoframes_enabled = > > > > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > > > > + else > > > > > > > > > + infoframes_enabled = > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux) > > > > > > > > > +; > > > > > > > > > + > > > > > > > > > + if (infoframes_enabled) > > > > > > > > > + return true; > > > > > > > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > > > > > > > Actually since we're dealing with both the LSPCON specific > > > > > > > stuff and DIP stuff for the DRM infoframe I think we should > > > > > > > stop using using intel_hdmi_infoframes_enabled(), and instead > > > > > > > provide a LSPCON specific replacement for it. That way we can > > > > > > > directly return the abstract bitmask instead of pretending to > > > > > > > return a bitmask of > > > > the DIP bits. > > > > > > We have DP (VSC etc) packets also managed as HDMI infoframes only. We > > > can keep the same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW for AVI and > > > similarly VIDEO_DIP_ENABLE_GMP_HSW for DRM (HDR metadata). This will > > help all the helper align appropriately even in the intel_dump_pipe_config. > > > > intel_dump_infoframe() does not use any platform specific bitmasks. > > So I don't understand what you're talking about here. > > What I meant is that if we continue to use the existing values and bitmask, we can have > lspcon infoframes_enabled return the appropriate type of infoframe which is active (as you suggested) and later > with intel_dump_pipe_config when it checks for intel_hdmi_infoframe_enable, we will get a matching value > in pipe_config->infoframes.enable and be able to dump them as well. Hope I am on same page with you here. Still don't really get what you're saying. What I am saying is we have something like: intel_lspcon_infoframes_enabled() { u32 enabled = 0; if (lspcon_avi_enabled) enabled |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); if (dip_gmp_enabled) enabled |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); return enabled; } Or I suppose we could even do something like: intel_lspcon_infoframes_enabled() { u32 enabled = intel_hdmi_infoframes_enabled(); if (lspcon_avi_enabled) enabled |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); return enabled; } which would be more future proof if we start to use any other DIP stuff. -- Ville Syrj?l? Intel From uma.shankar at intel.com Mon Jun 22 18:25:04 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 22 Jun 2020 18:25:04 +0000 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200622174028.GR6112@intel.com> References: <20200610191232.11620-1-uma.shankar@intel.com> <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> <20200622170246.GP6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> <20200622174028.GR6112@intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D4B7@BGSMSX104.gar.corp.intel.com> > -----Original Message----- > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Sent: Monday, June 22, 2020 11:10 PM > To: Shankar, Uma <uma.shankar at intel.com> > Cc: intel-gfx at lists.freedesktop.org; jani.nikula at linux.intel.com; Mun, Gwan- > gyeong <gwan-gyeong.mun at intel.com> > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes readback for > LSPCON > > On Mon, Jun 22, 2020 at 05:17:50PM +0000, Shankar, Uma wrote: > > > > > > > > > > -----Original Message----- > > > > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > Sent: Thursday, June 11, 2020 9:31 PM > > > > > > > > To: Shankar, Uma <uma.shankar at intel.com> > > > > > > > > Cc: intel-gfx at lists.freedesktop.org; > > > > > > > > jani.nikula at linux.intel.com; Mun, Gwan- gyeong > > > > > > > > <gwan-gyeong.mun at intel.com> > > > > > > > > Subject: Re: [v3 6/8] drm/i915/display: Implement > > > > > > > > infoframes readback for LSPCON > > > > > > > > > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > > > > > This will help align the implementation with state > > > > > > > > > > readback infrastructure. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > > > > > --- > > > > > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > > > > > ++++++++++++++++++++- > > > > > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > > a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > @@ -576,11 +576,70 @@ void > > > > > > > > > > lspcon_set_infoframes(struct intel_encoder > > > > > > > > *encoder, > > > > > > > > > > buf, ret); > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > +static bool > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > > + int ret; > > > > > > > > > > + u32 val = 0; > > > > > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > > > > > + > > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > > + if (ret < 0) { > > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", > reg); > > > > > > > > > > + return false; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > > > > > + return true; > > > > > > > > > > + > > > > > > > > > > + return false; > > > > > > > > > > > > > > > > > > return val & ...; > > > > > > > > > > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +static bool > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > > + int ret; > > > > > > > > > > + u32 val = 0; > > > > > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > > > > > + > > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > > + if (ret < 0) { > > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", > reg); > > > > > > > > > > + return false; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > > > > > + return true; > > > > > > > > > > + > > > > > > > > > > + return false; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > > > > > > const struct intel_crtc_state > *pipe_config) { > > > > > > > > > > - /* FIXME actually read this from the hw */ > > > > > > > > > > - return 0; > > > > > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > > > > > + struct intel_lspcon *lspcon = > enc_to_intel_lspcon(encoder); > > > > > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder- > >base.dev); > > > > > > > > > > + bool infoframes_enabled; > > > > > > > > > > + u32 mask = 0; > > > > > > > > > > + u32 val; > > > > > > > > > > + > > > > > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > > > > > + infoframes_enabled = > > > > > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > > > > > + else > > > > > > > > > > + infoframes_enabled = > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp-> > > > > > > > > > > +aux) > > > > > > > > > > +; > > > > > > > > > > + > > > > > > > > > > + if (infoframes_enabled) > > > > > > > > > > + return true; > > > > > > > > > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > > > > > > > > > Actually since we're dealing with both the LSPCON specific > > > > > > > > stuff and DIP stuff for the DRM infoframe I think we > > > > > > > > should stop using using intel_hdmi_infoframes_enabled(), > > > > > > > > and instead provide a LSPCON specific replacement for it. > > > > > > > > That way we can directly return the abstract bitmask > > > > > > > > instead of pretending to return a bitmask of > > > > > the DIP bits. > > > > > > > > We have DP (VSC etc) packets also managed as HDMI infoframes only. > > > > We can keep the same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW for > > > > AVI and similarly VIDEO_DIP_ENABLE_GMP_HSW for DRM (HDR metadata). > > > > This will > > > help all the helper align appropriately even in the intel_dump_pipe_config. > > > > > > intel_dump_infoframe() does not use any platform specific bitmasks. > > > So I don't understand what you're talking about here. > > > > What I meant is that if we continue to use the existing values and > > bitmask, we can have lspcon infoframes_enabled return the appropriate > > type of infoframe which is active (as you suggested) and later with > > intel_dump_pipe_config when it checks for intel_hdmi_infoframe_enable, we > will get a matching value in pipe_config->infoframes.enable and be able to dump > them as well. Hope I am on same page with you here. > > Still don't really get what you're saying. > > What I am saying is we have something like: > > intel_lspcon_infoframes_enabled() > { > u32 enabled = 0; > > if (lspcon_avi_enabled) > enabled |= > intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); > > if (dip_gmp_enabled) > enabled |= > intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); > > return enabled; > } > > Or I suppose we could even do something like: > > intel_lspcon_infoframes_enabled() > { > u32 enabled = intel_hdmi_infoframes_enabled(); > > if (lspcon_avi_enabled) > enabled |= > intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); > > return enabled; > } > > which would be more future proof if we start to use any other DIP stuff. Got the point now, thanks Ville for patiently clarifying. Will incorporate this and send out the next version. Regards, Uma Shankar > -- > Ville Syrj?l? > Intel From imre.deak at intel.com Mon Jun 22 18:35:09 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 22 Jun 2020 21:35:09 +0300 Subject: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling In-Reply-To: <20200618004240.16263-21-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-21-lucas.demarchi@intel.com> Message-ID: <20200622183509.GB25163@ideak-desk.fi.intel.com> On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote: > DG1 has one more combo phy port, no TC and all irq handling goes through > SDE, like for MCC. > > Cc: Anshuman Gupta <anshuman.gupta at intel.com> > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_reg.h | 8 +++++ > 2 files changed, 59 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 48e1686df3416..3707f9231171f 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), > }; > > +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = { > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A), > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B), > + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C), > + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D), The above 2 entries look incorrect. encoder->hpd_pin will be assigned based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1 port D is connected to PHY C and port E is connected to PHY D. So the above two pin definitions should be: [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C), [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D), > +}; > + > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > { > struct i915_hotplug *hpd = &dev_priv->hotplug; > @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > else > hpd->hpd = hpd_ilk; > > - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) > + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && > + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) > return; > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > + if (HAS_PCH_DG1(dev_priv)) > + hpd->pch_hpd = hpd_dg1_sde; > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > hpd->pch_hpd = hpd_tgp; > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) > hpd->pch_hpd = hpd_icp; > @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) > } > } > > +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) > +{ > + switch (pin) { > + case HPD_PORT_A: > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A); > + case HPD_PORT_B: > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B); > + case HPD_PORT_D: > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C); > + case HPD_PORT_E: > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D); > + default: > + return false; > + } > +} > + > static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) > { > switch (pin) { > @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > u32 ddi_hotplug_trigger, tc_hotplug_trigger; > u32 pin_mask = 0, long_mask = 0; > bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); > + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); > > - if (HAS_PCH_TGP(dev_priv)) { > + if (HAS_PCH_DG1(dev_priv)) { > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1; > + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect; > + tc_hotplug_trigger = 0; > + } else if (HAS_PCH_TGP(dev_priv)) { > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; > tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; > } else if (HAS_PCH_JSP(dev_priv)) { > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; > tc_hotplug_trigger = 0; > } else if (HAS_PCH_MCC(dev_priv)) { > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > INTEL_PCH_TYPE(dev_priv)); > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; > tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; > } > @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, > ddi_hotplug_trigger, dig_hotplug_reg, > dev_priv->hotplug.pch_hpd, > - icp_ddi_port_hotplug_long_detect); > + ddi_port_hotplug_long_detect); > } > > if (tc_hotplug_trigger) { > @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) > TGP_DDI_HPD_ENABLE_MASK, 0); > } > > +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) > +{ > + icp_hpd_irq_setup(dev_priv, > + SDE_DDI_MASK_DG1, 0, > + DG1_DDI_HPD_ENABLE_MASK, 0); > +} > + > static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) > { > u32 hotplug; > @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) > gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); > I915_WRITE(SDEIMR, ~mask); > > - if (HAS_PCH_TGP(dev_priv)) > + if (HAS_PCH_DG1(dev_priv)) > + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0); > + else if (HAS_PCH_TGP(dev_priv)) > icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, > TGP_TC_HPD_ENABLE_MASK); > else if (HAS_PCH_JSP(dev_priv)) > @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) > if (I915_HAS_HOTPLUG(dev_priv)) > dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; > } else { > - if (HAS_PCH_JSP(dev_priv)) > + if (HAS_PCH_DG1(dev_priv)) > + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; > + else if (HAS_PCH_JSP(dev_priv)) > dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; > else if (HAS_PCH_MCC(dev_priv)) > dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 6649aeca25d72..13a989f5e8dd3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8168,6 +8168,10 @@ enum { > SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ > SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ > SDE_TC_HOTPLUG_ICP(PORT_TC1)) > +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \ > + SDE_DDI_HOTPLUG_ICP(PORT_C) | \ > + SDE_DDI_HOTPLUG_ICP(PORT_B) | \ > + SDE_DDI_HOTPLUG_ICP(PORT_A)) > > #define SDEISR _MMIO(0xc4000) > #define SDEIMR _MMIO(0xc4004) > @@ -8367,6 +8371,10 @@ enum { > #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ > ICP_TC_HPD_ENABLE(PORT_TC5) | \ > ICP_TC_HPD_ENABLE_MASK) > +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \ > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) > > #define _PCH_DPLL_A 0xc6014 > #define _PCH_DPLL_B 0xc6018 > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From manasi.d.navare at intel.com Mon Jun 22 19:00:43 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Mon, 22 Jun 2020 12:00:43 -0700 Subject: [Intel-gfx] [v1 3/3] Revert "drm/amd/display: Expose connector VRR range via debugfs" In-Reply-To: <f9c32dfa-0a23-45c0-8991-545c071da388@amd.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> <20200622142519.16214-4-bhanuprakash.modem@intel.com> <f9c32dfa-0a23-45c0-8991-545c071da388@amd.com> Message-ID: <20200622190042.GA18249@intel.com> On Mon, Jun 22, 2020 at 10:57:02AM -0400, Kazlauskas, Nicholas wrote: > On 2020-06-22 10:25 a.m., Bhanuprakash Modem wrote: > >As both VRR min and max are already part of drm_display_info, > >drm can expose this VRR range for each connector. > > > >Hence this logic should move to core DRM. > > > >This reverts commit 727962f030c23422a01e8b22d0f463815fb15ec4. > > > >Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > >Cc: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> > >Cc: Harry Wentland <harry.wentland at amd.com> > >Cc: Alex Deucher <alexander.deucher at amd.com> > >Cc: Manasi Navare <manasi.d.navare at intel.com> > >Cc: AMD gfx <amd-gfx at lists.freedesktop.org> > > > Looks good to me with Patch 2 part of the series. > > Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> > Thanks for your review, do we have your r-b on patch 2/3 also? In that case, how do you think we should merge the patches? Patch 2/3 will be merged through drm-misc, how about this one? Manasi > Thanks, > Nicholas Kazlauskas > > >--- > > .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ------------------- > > 1 file changed, 20 deletions(-) > > > >diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > >index 076af267b488..71387d2af2ed 100644 > >--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > >+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c > >@@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void *data) > > return res; > > } > >-/* > >- * Returns the min and max vrr vfreq through the connector's debugfs file. > >- * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > >- */ > >-static int vrr_range_show(struct seq_file *m, void *data) > >-{ > >- struct drm_connector *connector = m->private; > >- struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); > >- > >- if (connector->status != connector_status_connected) > >- return -ENODEV; > >- > >- seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); > >- seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); > >- > >- return 0; > >-} > >- > > #ifdef CONFIG_DRM_AMD_DC_HDCP > > /* > > * Returns the HDCP capability of the Display (1.4 for now). > >@@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, > > DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); > > DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); > > DEFINE_SHOW_ATTRIBUTE(output_bpc); > >-DEFINE_SHOW_ATTRIBUTE(vrr_range); > > #ifdef CONFIG_DRM_AMD_DC_HDCP > > DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); > > #endif > >@@ -1059,7 +1040,6 @@ static const struct { > > {"phy_settings", &dp_phy_settings_debugfs_fop}, > > {"test_pattern", &dp_phy_test_pattern_fops}, > > {"output_bpc", &output_bpc_fops}, > >- {"vrr_range", &vrr_range_fops}, > > #ifdef CONFIG_DRM_AMD_DC_HDCP > > {"hdcp_sink_capability", &hdcp_sink_capability_fops}, > > #endif > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From manasi.d.navare at intel.com Mon Jun 22 19:02:03 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Mon, 22 Jun 2020 12:02:03 -0700 Subject: [Intel-gfx] [v9 2/3] drm/debug: Expose connector VRR monitor range via debugfs In-Reply-To: <20200622142519.16214-3-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> <20200622142519.16214-3-bhanuprakash.modem@intel.com> Message-ID: <20200622190203.GB18249@intel.com> On Mon, Jun 22, 2020 at 07:55:18PM +0530, Bhanuprakash Modem wrote: > [Why] > It's useful to know the min and max vrr range for IGT testing. > > [How] > Expose the min and max vfreq for the connector via a debugfs file > on the connector, "vrr_range". > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > v2: > * Fix the typo in max_vfreq (Manasi) > * Change the name of node to i915_vrr_info so we can add > other vrr info for more debug info (Manasi) > * Change the VRR capable to display Yes or No (Manasi) > * Fix indentation checkpatch errors (Manasi) > v3: > * Remove the unnecessary debug print (Manasi) > v4: > * Rebase > v5: > * Rename to vrr_range to match AMD debugfs > v6: > * Rebase (manasi) > v7: > * Fix cmpilation due to rebase > v8: > * Move debugfs node creation logic to DRM (Emil) > * Remove AMD specific logic (Emil) > v9: > * Seperate patch for removal of AMD specific logic (Manasi) > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > Cc: Jani Nikula <jani.nikula at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Harry Wentland <harry.wentland at amd.com> > CC: Emil Velikov <emil.l.velikov at gmail.com> Looks good to me, Reviewed-by: Manasi Navare <manasi.d.navare at intel.com> Manasi > --- > drivers/gpu/drm/drm_debugfs.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c > index bfe4602f206b..3d7182001004 100644 > --- a/drivers/gpu/drm/drm_debugfs.c > +++ b/drivers/gpu/drm/drm_debugfs.c > @@ -376,6 +376,24 @@ static ssize_t edid_write(struct file *file, const char __user *ubuf, > return (ret) ? ret : len; > } > > +/* > + * Returns the min and max vrr vfreq through the connector's debugfs file. > + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > + */ > +static int vrr_range_show(struct seq_file *m, void *data) > +{ > + struct drm_connector *connector = m->private; > + > + if (connector->status != connector_status_connected) > + return -ENODEV; > + > + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); > + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); > + > + return 0; > +} > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > + > static const struct file_operations drm_edid_fops = { > .owner = THIS_MODULE, > .open = edid_open, > @@ -413,6 +431,10 @@ void drm_debugfs_connector_add(struct drm_connector *connector) > /* edid */ > debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root, connector, > &drm_edid_fops); > + > + /* vrr range */ > + debugfs_create_file("vrr_range", S_IRUGO, root, connector, > + &vrr_range_fops); > } > > void drm_debugfs_connector_remove(struct drm_connector *connector) > -- > 2.20.1 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From chris at chris-wilson.co.uk Mon Jun 22 19:08:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 22 Jun 2020 20:08:20 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_exec_schedule: Try to spot unfairness Message-ID: <20200622190820.849154-1-chris@chris-wilson.co.uk> An important property for multi-client systems is that each client gets a 'fair' allotment of system time. (Where fairness is at the whim of the context properties, such as priorities.) This test forks N independent clients (albeit they happen to share a single vm), and does an equal amount of work in client and asserts that they take an equal amount of time. Though we have never claimed to have a completely fair scheduler, that is what is expected. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Ramalingam C <ramalingam.c at intel.com> --- tests/i915/gem_exec_schedule.c | 782 +++++++++++++++++++++++++++++++++ 1 file changed, 782 insertions(+) diff --git a/tests/i915/gem_exec_schedule.c b/tests/i915/gem_exec_schedule.c index 931b1245f..fae04536c 100644 --- a/tests/i915/gem_exec_schedule.c +++ b/tests/i915/gem_exec_schedule.c @@ -29,6 +29,7 @@ #include <sys/poll.h> #include <sys/ioctl.h> #include <sys/mman.h> +#include <sys/resource.h> #include <sys/syscall.h> #include <sched.h> #include <signal.h> @@ -2501,6 +2502,766 @@ static void measure_semaphore_power(int i915) rapl_close(&pkg); } +static int read_timestamp_frequency(int i915) +{ + int value = 0; + drm_i915_getparam_t gp = { + .value = &value, + .param = I915_PARAM_CS_TIMESTAMP_FREQUENCY, + }; + ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp); + return value; +} + +static uint64_t div64_u64_round_up(uint64_t x, uint64_t y) +{ + return (x + y - 1) / y; +} + +static uint64_t ns_to_ticks(int i915, uint64_t ns) +{ + return div64_u64_round_up(ns * read_timestamp_frequency(i915), + NSEC_PER_SEC); +} + +static uint64_t ticks_to_ns(int i915, uint64_t ticks) +{ + return div64_u64_round_up(ticks * NSEC_PER_SEC, + read_timestamp_frequency(i915)); +} + +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) + +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1) +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) +/* Opcodes for MI_MATH_INSTR */ +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0) +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0) +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0) +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0) +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0) +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0) +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) +/* Registers used as operands in MI_MATH_INSTR */ +#define MI_MATH_REG(x) (x) +#define MI_MATH_REG_SRCA 0x20 +#define MI_MATH_REG_SRCB 0x21 +#define MI_MATH_REG_ACCU 0x31 +#define MI_MATH_REG_ZF 0x32 +#define MI_MATH_REG_CF 0x33 + +#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) + +static void delay(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr, + uint64_t ns) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define RUNTIME (base + 0x3a8) + enum { START_TS, NOW_TS }; + uint32_t *map, *cs, *jmp; + + igt_require(base); + + /* Loop until CTX_TIMESTAMP - initial > @ns */ + + cs = map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(START_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(START_TS); + + while (offset_in_page(cs) & 63) + *cs++ = 0; + jmp = cs; + + *cs++ = 0x5 << 23; /* MI_ARB_CHECK */ + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(NOW_TS) + 4; + *cs++ = 0; + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = RUNTIME; + *cs++ = CS_GPR(NOW_TS); + + /* delta = now - start; inverted to match COND_BBE */ + *cs++ = MI_MATH(4); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS)); + *cs++ = MI_MATH_SUB; + *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU); + + /* Save delta for reading by COND_BBE */ + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(NOW_TS); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + /* Delay between SRM and COND_BBE to post the writes */ + for (int n = 0; n < 8; n++) { + *cs++ = MI_STORE_DWORD_IMM; + if (use_64b) { + *cs++ = addr + 4064; + *cs++ = addr >> 32; + } else { + *cs++ = 0; + *cs++ = addr + 4064; + } + *cs++ = 0; + } + + /* Break if delta > ns */ + *cs++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (1 + use_64b); + *cs++ = ~ns_to_ticks(i915, ns); + *cs++ = addr + 4000; + *cs++ = addr >> 32; + + /* Otherwise back to recalculating delta */ + *cs++ = MI_BATCH_BUFFER_START | 1 << 8 | use_64b; + *cs++ = addr + offset_in_page(jmp); + *cs++ = addr >> 32; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +delay_create(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t target_ns) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + delay(i915, e, obj.handle, obj.offset, target_ns); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static void tslog(int i915, + const struct intel_execution_engine2 *e, + uint32_t handle, + uint64_t addr) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); +#define CS_GPR(x) (base + 0x600 + 8 * (x)) +#define CS_TIMESTAMP (base + 0x358) + enum { INC, MASK, ADDR }; + uint32_t *timestamp_lo, *addr_lo; + uint32_t *map, *cs; + + igt_require(base); + + map = gem_mmap__device_coherent(i915, handle, 0, 4096, PROT_WRITE); + cs = map + 512; + + /* Record the current CS_TIMESTAMP into a journal [a 512 slot ring]. */ + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_TIMESTAMP; + timestamp_lo = cs; + *cs++ = addr; + *cs++ = addr >> 32; + + /* Load the address + inc & mask variables */ + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR); + addr_lo = cs; + *cs++ = addr; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(ADDR) + 4; + *cs++ = addr >> 32; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(INC); + *cs++ = 4; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(INC) + 4; + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK); + *cs++ = 0xfffff7ff; + *cs++ = MI_LOAD_REGISTER_IMM; + *cs++ = CS_GPR(MASK) + 4; + *cs++ = 0xffffffff; + + /* Increment the [ring] address for saving CS_TIMESTAMP */ + *cs++ = MI_MATH(8); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(INC)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_ADD; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(ADDR)); + *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(MASK)); + *cs++ = MI_MATH_AND; + *cs++ = MI_MATH_STORE(MI_MATH_REG(ADDR), MI_MATH_REG_ACCU); + + /* Rewrite the batch buffer for the next execution */ + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(timestamp_lo); + *cs++ = addr >> 32; + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = CS_GPR(ADDR); + *cs++ = addr + offset_in_page(addr_lo); + *cs++ = addr >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + munmap(map, 4096); +} + +static struct drm_i915_gem_exec_object2 +tslog_create(int i915, uint32_t ctx, const struct intel_execution_engine2 *e) +{ + struct drm_i915_gem_exec_object2 obj = { + .handle = batch_create(i915), + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .rsvd1 = ctx, + .flags = e->flags, + }; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + + tslog(i915, e, obj.handle, obj.offset); + + obj.flags |= EXEC_OBJECT_PINNED; + return obj; +} + +static int cmp_u32(const void *A, const void *B) +{ + const uint32_t *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static struct intel_execution_engine2 +pick_random_engine(int i915, const struct intel_execution_engine2 *not) +{ + const struct intel_execution_engine2 *e; + unsigned int count = 0; + + __for_each_physical_engine(i915, e) { + if (e->flags == not->flags) + continue; + if (!gem_class_has_mutable_submission(i915, e->class)) + continue; + count++; + } + if (!count) + return *not; + + count = rand() % count; + __for_each_physical_engine(i915, e) { + if (e->flags == not->flags) + continue; + if (!gem_class_has_mutable_submission(i915, e->class)) + continue; + if (!count--) + break; + } + + return *e; +} + +static void fair_child(int i915, uint32_t ctx, + const struct intel_execution_engine2 *e, + uint64_t frame_ns, + int timeline, + uint32_t common, + unsigned int flags, + unsigned long *ctl, + unsigned long *out) +#define F_SYNC (1 << 0) +#define F_PACE (1 << 1) +#define F_FLOW (1 << 2) +#define F_HALF (1 << 3) +#define F_SOLO (1 << 4) +#define F_SPARE (1 << 5) +#define F_NEXT (1 << 6) +#define F_VIP (1 << 7) +#define F_RRUL (1 << 8) +#define F_SHARE (1 << 9) +#define F_PING (1 << 10) +#define F_THROTTLE (1 << 11) +{ + const int batches_per_frame = flags & F_SOLO ? 1 : 3; + struct drm_i915_gem_exec_object2 obj[4] = { + {}, + { + .handle = common ?: gem_create(i915, 4096), + }, + delay_create(i915, ctx, e, frame_ns / batches_per_frame), + delay_create(i915, ctx, e, frame_ns / batches_per_frame), + }; + struct intel_execution_engine2 ping = *e; + int p_fence = -1, n_fence = -1; + unsigned long count = 0; + int n; + + srandom(getpid()); + if (flags & F_PING) + ping = pick_random_engine(i915, e); + obj[0] = tslog_create(i915, ctx, &ping); + + while (!READ_ONCE(*ctl)) { + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(obj), + .buffer_count = 4, + .rsvd1 = ctx, + .rsvd2 = -1, + .flags = e->flags, + }; + + if (flags & F_FLOW) { + unsigned int seq; + + seq = count; + if (flags & F_NEXT) + seq++; + + execbuf.rsvd2 = + sw_sync_timeline_create_fence(timeline, seq); + execbuf.flags |= I915_EXEC_FENCE_IN; + } + + execbuf.flags |= I915_EXEC_FENCE_OUT; + gem_execbuf_wr(i915, &execbuf); + n_fence = execbuf.rsvd2 >> 32; + execbuf.flags &= ~(I915_EXEC_FENCE_OUT | I915_EXEC_FENCE_IN); + for (n = 1; n < batches_per_frame; n++) + gem_execbuf(i915, &execbuf); + close(execbuf.rsvd2); + + execbuf.buffer_count = 1; + execbuf.batch_start_offset = 2048; + execbuf.flags = ping.flags | I915_EXEC_FENCE_IN; + execbuf.rsvd2 = n_fence; + gem_execbuf(i915, &execbuf); + + if (flags & F_PACE && p_fence != -1) { + struct pollfd pfd = { + .fd = p_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + close(p_fence); + + if (flags & F_SYNC) { + struct pollfd pfd = { + .fd = n_fence, + .events = POLLIN, + }; + poll(&pfd, 1, -1); + } + + if (flags & F_THROTTLE) + igt_ioctl(i915, DRM_IOCTL_I915_GEM_THROTTLE, 0); + + igt_swap(obj[2], obj[3]); + igt_swap(p_fence, n_fence); + count++; + } + close(p_fence); + + gem_close(i915, obj[3].handle); + gem_close(i915, obj[2].handle); + if (obj[1].handle != common) + gem_close(i915, obj[1].handle); + + gem_sync(i915, obj[0].handle); + if (out) { + uint32_t *map; + + map = gem_mmap__device_coherent(i915, obj[0].handle, + 0, 4096, PROT_WRITE); + for (n = 1; n < min(count, 512); n++) { + igt_assert(map[n]); + map[n - 1] = map[n] - map[n - 1]; + } + qsort(map, --n, sizeof(*map), cmp_u32); + *out = ticks_to_ns(i915, map[n / 2]); + munmap(map, 4096); + } + gem_close(i915, obj[0].handle); +} + +static int cmp_ul(const void *A, const void *B) +{ + const unsigned long *a = A, *b = B; + + if (*a < *b) + return -1; + else if (*a > *b) + return 1; + else + return 0; +} + +static uint64_t d_cpu_time(const struct rusage *a, const struct rusage *b) +{ + uint64_t cpu_time = 0; + + cpu_time += (a->ru_utime.tv_sec - b->ru_utime.tv_sec) * NSEC_PER_SEC; + cpu_time += (a->ru_utime.tv_usec - b->ru_utime.tv_usec) * 1000; + + cpu_time += (a->ru_stime.tv_sec - b->ru_stime.tv_sec) * NSEC_PER_SEC; + cpu_time += (a->ru_stime.tv_usec - b->ru_stime.tv_usec) * 1000; + + return cpu_time; +} + +static void timeline_advance(int timeline, int delay_ns) +{ + struct timespec tv = { .tv_nsec = delay_ns }; + nanosleep(&tv, NULL); + sw_sync_timeline_inc(timeline, 1); +} + +static void fairness(int i915, + const struct intel_execution_engine2 *e, + int timeout, unsigned int flags) +{ + const int frame_ns = 16666 * 1000; + const int fence_ns = flags & F_HALF ? 2 * frame_ns : frame_ns; + unsigned long *result; + uint32_t common = 0; + + igt_require(gem_class_has_mutable_submission(i915, e->class)); + + if (flags & F_SHARE) + common = gem_create(i915, 4095); + + result = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0); + + for (int n = 2; n <= 64; n <<= 1) { /* 32 == 500us per client */ + int timeline = sw_sync_timeline_create(); + int nfences = timeout * NSEC_PER_SEC / fence_ns + 1; + const int nchild = n - 1; /* odd for easy medians */ + const int child_ns = frame_ns / (nchild + !!(flags & F_SPARE)); + const int lo = nchild / 4; + const int hi = (3 * nchild + 3) / 4 - 1; + struct rusage old_usage, usage; + uint64_t cpu_time, d_time; + unsigned long vip = -1; + struct timespec tv; + struct igt_mean m; + + if (flags & F_PING) { + struct intel_execution_engine2 *ping; + + __for_each_physical_engine(i915, ping) { + if (ping->flags == e->flags) + continue; + + igt_fork(child, 1) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + fair_child(i915, ctx, ping, + child_ns / 8, + -1, common, + F_SOLO | F_PACE | F_SHARE, + &result[nchild], + NULL); + + gem_context_destroy(i915, ctx); + } + } + } + + memset(result, 0, (nchild + 1) * sizeof(result[0])); + getrusage(RUSAGE_CHILDREN, &old_usage); + igt_nsec_elapsed(memset(&tv, 0, sizeof(tv))); + igt_fork(child, nchild) { + uint32_t ctx = gem_context_clone_with_engines(i915, 0); + + if (flags & F_VIP && child == 0) { + gem_context_set_priority(i915, ctx, MAX_PRIO); + flags |= F_FLOW; + } + if (flags & F_RRUL && child == 0) + flags |= F_SOLO | F_FLOW | F_SYNC; + + fair_child(i915, ctx, e, child_ns, + timeline, common, flags, + &result[nchild], + &result[child]); + + gem_context_destroy(i915, ctx); + } + + while (nfences--) + timeline_advance(timeline, fence_ns); + + result[nchild] = 1; + for (int child = 0; child < nchild; child++) { + while (!READ_ONCE(result[child])) + timeline_advance(timeline, fence_ns); + } + + igt_waitchildren(); + close(timeline); + + /* Are we running out of CPU time, and fail to submit frames? */ + d_time = igt_nsec_elapsed(&tv); + getrusage(RUSAGE_CHILDREN, &usage); + cpu_time = d_cpu_time(&usage, &old_usage); + if (10 * cpu_time > 9 * d_time) { + if (nchild > 7) + break; + + igt_skip_on_f(10 * cpu_time > 9 * d_time, + "%.0f%% CPU usage, presuming capacity exceeded\n", + 100. * cpu_time / d_time); + } + + igt_mean_init(&m); + for (int child = 0; child < nchild; child++) + igt_mean_add(&m, result[child]); + + if (flags & (F_VIP | F_RRUL)) + vip = result[0]; + + qsort(result, nchild, sizeof(*result), cmp_ul); + igt_info("%2d clients, range: [%.1f, %.1f], iqr: [%.1f, %.1f], median: %.1f, mean: %.1f ? %.2f ms\n", + nchild, + 1e-6 * result[0], 1e-6 * result[nchild - 1], + 1e-6 * result[lo], 1e-6 * result[hi], + 1e-6 * result[nchild / 2], + 1e-6 * igt_mean_get(&m), + 1e-6 * sqrt(igt_mean_get_variance(&m))); + + if (vip != -1) { + igt_info("VIP interval %.2f ms\n", 1e-6 * vip); + igt_assert(4 * vip > 3 * fence_ns && + 3 * vip < 4 * fence_ns); + } + + /* May be slowed due to sheer volume of context switches */ + igt_assert(4 * igt_mean_get(&m) > 3 * fence_ns && + igt_mean_get(&m) < 3 * fence_ns); + + igt_assert(4 * igt_mean_get(&m) > 3 * result[nchild / 2] && + 3 * igt_mean_get(&m) < 4 * result[nchild / 2]); + + igt_assert(2 * (result[hi] - result[lo]) < result[nchild / 2]); + } + + munmap(result, 4096); + if (common) + gem_close(i915, common); +} + +static void test_fairness(int i915, int timeout) +{ + static const struct { + const char *name; + unsigned int flags; + } fair[] = { + /* + * none - maximal greed in each client + * + * Push as many frames from each client as fast as possible + */ + { "none", 0 }, + { "none-vip", F_VIP }, /* one vip client must meet deadlines */ + { "none-solo", F_SOLO }, /* 1 batch per frame per client */ + { "none-share", F_SHARE }, /* read from a common buffer */ + { "none-rrul", F_RRUL }, /* "realtime-response under load" */ + { "none-ping", F_PING }, /* measure inter-engine fairness */ + + /* + * throttle - original per client throttling + * + * Used for front buffering rendering where there is no + * extenal frame marker. Each client tries to only keep + * 20ms of work submitted, though that measurement is + * flawed... + * + * This is used by Xory to try and maintain some resembalance + * of input/output consistency when being feed a continuous + * stream of X11 draw requests straight into scanout, where + * the clients may submit the work faster than can be drawn. + */ + { "throttle", F_THROTTLE }, + { "throttle-vip", F_THROTTLE | F_VIP }, + { "throttle-solo", F_THROTTLE | F_SOLO }, + { "throttle-share", F_THROTTLE | F_SHARE }, + { "throttle-rrul", F_THROTTLE | F_RRUL }, + + /* + * pace - mesa "submit double buffering" + * + * Submit a frame, wait for previous frame to start. This + * prevents each client from getting too far ahead of its + * rendering, maintaining a consistent input/output latency. + */ + { "pace", F_PACE }, + { "pace-solo", F_PACE | F_SOLO}, + { "pace-share", F_PACE | F_SHARE}, + { "pace-ping", F_PACE | F_SHARE | F_PING}, + + /* sync - only submit a frame at a time */ + { "sync", F_SYNC }, + { "sync-vip", F_SYNC | F_VIP }, + { "sync-solo", F_SYNC | F_SOLO }, + + /* flow - synchronise execution against the clock (vblank) */ + { "flow", F_PACE | F_FLOW }, + { "flow-share", F_PACE | F_FLOW | F_SHARE }, + { "flow-ping", F_PACE | F_FLOW | F_SHARE | F_PING }, + + /* next - submit ahead of the clock (vblank double buffering) */ + { "next", F_PACE | F_FLOW | F_NEXT }, + { "next-share", F_PACE | F_FLOW | F_NEXT | F_SHARE }, + { "next-ping", F_PACE | F_FLOW | F_NEXT | F_SHARE | F_PING }, + + /* spare - underutilise by a single client timeslice */ + { "spare", F_PACE | F_FLOW | F_SPARE }, + + /* half - run at half pace (submit 16ms of work every 32ms) */ + { "half", F_PACE | F_FLOW | F_HALF }, + + {} + }; + + for (typeof(*fair) *f = fair; f->name; f++) { + igt_subtest_with_dynamic_f("fair-%s", f->name) { + const struct intel_execution_engine2 *e; + + igt_require(intel_gen(intel_get_drm_devid(i915)) >= 8); + + __for_each_physical_engine(i915, e) { + if (!gem_class_can_store_dword(i915, e->class)) + continue; + + igt_dynamic_f("%s", e->name) + fairness(i915, e, timeout, f->flags); + } + } + } +} + +static uint32_t read_ctx_timestamp(int i915, + uint32_t ctx, + const struct intel_execution_engine2 *e) +{ + const int use_64b = intel_gen(intel_get_drm_devid(i915)) >= 8; + const uint32_t base = gem_engine_mmio_base(i915, e->name); + struct drm_i915_gem_relocation_entry reloc; + struct drm_i915_gem_exec_object2 obj = { + .handle = gem_create(i915, 4096), + .offset = 32 << 20, + .relocs_ptr = to_user_pointer(&reloc), + .relocation_count = 1, + }; + struct drm_i915_gem_execbuffer2 execbuf = { + .buffers_ptr = to_user_pointer(&obj), + .buffer_count = 1, + .flags = e->flags, + .rsvd1 = ctx, + }; +#define RUNTIME (base + 0x3a8) + uint32_t *map, *cs; + uint32_t ts; + + igt_require(base); + + cs = map = gem_mmap__device_coherent(i915, obj.handle, + 0, 4096, PROT_WRITE); + + *cs++ = 0x24 << 23 | (1 + use_64b); /* SRM */ + *cs++ = RUNTIME; + memset(&reloc, 0, sizeof(reloc)); + reloc.target_handle = obj.handle; + reloc.presumed_offset = obj.offset; + reloc.offset = offset_in_page(cs); + reloc.delta = 4000; + *cs++ = obj.offset + 4000; + *cs++ = obj.offset >> 32; + + *cs++ = MI_BATCH_BUFFER_END; + + gem_execbuf(i915, &execbuf); + gem_sync(i915, obj.handle); + gem_close(i915, obj.handle); + + ts = map[1000]; + munmap(map, 4096); + + return ts; +} + +static void fairslice(int i915, const struct intel_execution_engine2 *e) +{ + igt_spin_t *spin[3]; + uint32_t ctx[3]; + uint32_t ts[3]; + + for (int i = 0; i < ARRAY_SIZE(ctx); i++) { + ctx[i] = gem_context_clone_with_engines(i915, 0); + spin[i] = igt_spin_new(i915, .ctx = ctx[i], .engine = e->flags); + } + + sleep(2); /* over the course of many timeslices */ + + for (int i = 0; i < ARRAY_SIZE(ctx); i++) { + igt_assert(gem_bo_busy(i915, spin[i]->handle)); + igt_spin_end(spin[i]); + + ts[i] = read_ctx_timestamp(i915, ctx[i], e); + } + + for (int i = 0; i < ARRAY_SIZE(ctx); i++) { + igt_spin_free(i915, spin[i]); + gem_context_destroy(i915, ctx[i]); + } + + qsort(ts, 3, sizeof(*ts), cmp_u32); + igt_info("%s: [%.1f, %.1f] ms\n", e->name, + 1e-6 * ticks_to_ns(i915, ts[0]), + 1e-6 * ticks_to_ns(i915, ts[2])); + + igt_assert(ts[0] && ts[2] > ts[0]); + igt_assert(4 * ts[0] > 3 * ts[2]); +} + #define test_each_engine(T, i915, e) \ igt_subtest_with_dynamic(T) __for_each_physical_engine(i915, e) \ igt_dynamic_f("%s", e->name) @@ -2567,6 +3328,25 @@ igt_main test_each_engine("lateslice", fd, e) lateslice(fd, e->flags); + igt_subtest_group { + igt_fixture { + igt_require(gem_scheduler_has_semaphores(fd)); + igt_require(gem_scheduler_has_preemption(fd)); + igt_require(intel_gen(intel_get_drm_devid(fd)) >= 8); + } + + test_each_engine("fairslice", fd, e) + fairslice(fd, e); + + igt_subtest("fairslice-all") { + __for_each_physical_engine(fd, e) { + igt_fork(child, 1) + fairslice(fd, e); + } + igt_waitchildren(); + } + } + test_each_engine("submit-early-slice", fd, e) submit_slice(fd, e, EARLY_SUBMIT); test_each_engine("submit-golden-slice", fd, e) @@ -2595,6 +3375,8 @@ igt_main test_each_engine_store("promotion", fd, e) promotion(fd, e->flags); + test_fairness(fd, 2); + igt_subtest_group { igt_fixture { igt_require(gem_scheduler_has_preemption(fd)); -- 2.27.0 From uma.shankar at intel.com Mon Jun 22 20:00:27 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:27 +0530 Subject: [Intel-gfx] [v5 00/11] Enable HDR on MCA LSPCON based Gen9 devices Message-ID: <20200622200038.14034-1-uma.shankar@intel.com> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR support for MCA and Parade LSPCON based GEN9 devices. SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP packets. LSPCON will be set to operate in PCON mode, will receive the metadata and create Dynamic Range and Mastering Infoframe (DRM packets) and send it to HDR capable HDMI sink devices. v2: Fixed Ville's review comments. Suppressed some warnings. Patch 8 of the series is marked "Not for Merge" and is just for reference to userspace people to incorporate in order to support 10bit content with 4K at 60 resolutions. v3: Added Infoframe readout support for DRM infoframes. Addressed Jani Nikula's review comments. v4: Addressed Ville's review comments and added proper bitmask for enabled infoframes. Series also incorporates Ville's patch for stopping infoframes to be sent to DVI sinks. Extended the same for DRM as well. v5: Created separate helper function for lspcon_infoframes_enabled as per Ville's suggestion. Note: Patch 11 of the series is for reference to userspace, not to be merged to driver. Uma Shankar (10): drm/i915/display: Add HDR Capability detection for LSPCON drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon drm/i915/display: Attach HDR property for capable Gen9 devices drm/i915/display: Enable BT2020 for HDR on LSPCON devices drm/i915/display: Enable HDR for Parade based lspcon drm/i915/display: Implement infoframes readback for LSPCON drm/i915/display: Implement DRM infoframe read for LSPCON drm/i915/lspcon: Create separate infoframe_enabled helper drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60 at 10bpp for LSPCON Ville Syrj?l? (1): drm/i915/lspcon: Do not send infoframes to non-HDMI sinks drivers/gpu/drm/i915/display/intel_ddi.c | 30 ++-- .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 24 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++ drivers/gpu/drm/i915/display/intel_lspcon.c | 170 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_lspcon.h | 11 +- 6 files changed, 230 insertions(+), 27 deletions(-) -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:28 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:28 +0530 Subject: [Intel-gfx] [v5 01/11] drm/i915/display: Add HDR Capability detection for LSPCON In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-2-uma.shankar@intel.com> LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES DPCD register. LSPCON implementations capable of supporting HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch reads the same, detects the HDR capability and adds this to intel_lspcon struct. v2: Addressed Jani Nikula's review comment and fixed the HDR capability detection logic Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_lspcon.c | 30 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..ca99a05f52da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1386,6 +1386,7 @@ struct intel_lspcon { bool active; enum drm_lspcon_mode mode; enum lspcon_vendor vendor; + bool hdr_supported; }; struct intel_digital_port { diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 6ff7b226f0a1..70bd564cae46 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -35,6 +35,8 @@ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 #define LSPCON_VENDOR_MCA_OUI 0x0060AD +#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 + /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF @@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) return true; } +static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_digital_port *intel_dig_port = + container_of(lspcon, struct intel_digital_port, lspcon); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* Enable HDR for MCA based LSPCON devices */ + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, + &hdr_caps, 1); + else + return; + + if (ret < 0) { + drm_dbg_kms(dev, "hdr capability detection failed\n"); + lspcon->hdr_supported = false; + return; + } else if (hdr_caps & 0x1) { + drm_dbg_kms(dev, "lspcon capable of HDR\n"); + lspcon->hdr_supported = true; + } +} + static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) { enum drm_lspcon_mode current_mode; @@ -581,6 +609,8 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) return false; } + lspcon_detect_hdr_capability(lspcon); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n"); -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:29 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:29 +0530 Subject: [Intel-gfx] [v5 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-3-uma.shankar@intel.com> Gen9 hardware supports HDMI2.0 through LSPCON chips. Extending HDR support for MCA LSPCON based GEN9 devices. SOC will drive LSPCON as DP and send HDR metadata as standard DP SDP packets. LSPCON will be set to operate in PCON mode, will receive the metadata and create Dynamic Range and Mastering Infoframe (DRM packets) and send it to HDR capable HDMI sink devices. v2: Re-used hsw infoframe write implementation for HDR metadata for LSPCON as per Ville's suggestion. v3: Addressed Jani Nikula's review comments. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++ drivers/gpu/drm/i915/display/intel_lspcon.c | 37 +++++++++++++++------ drivers/gpu/drm/i915/display/intel_lspcon.h | 5 ++- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a31a98d26882..53103ef72a58 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -590,6 +590,16 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, return val & mask; } +void lspcon_drm_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len) +{ + drm_dbg_kms(encoder->base.dev, "Update HDR metadata for lspcon\n"); + /* It uses the legacy hsw implementation for the same */ + hsw_write_infoframe(encoder, crtc_state, type, frame, len); +} + static const u8 infoframe_type_to_idx[] = { HDMI_PACKET_TYPE_GENERAL_CONTROL, HDMI_PACKET_TYPE_GAMUT_METADATA, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 70bd564cae46..95d29c379076 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -461,27 +461,42 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, unsigned int type, const void *frame, ssize_t len) { - bool ret; + bool ret = true; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); - /* LSPCON only needs AVI IF */ - if (type != HDMI_INFOFRAME_TYPE_AVI) + /* + * Supporting HDR on MCA LSPCON + * Todo: Add support for Parade later + */ + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA && + lspcon->vendor != LSPCON_VENDOR_MCA) return; - if (lspcon->vendor == LSPCON_VENDOR_MCA) - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, - frame, len); - else - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, - frame, len); + switch (type) { + case HDMI_INFOFRAME_TYPE_AVI: + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, + frame, len); + else + ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, + frame, len); + break; + case HDMI_PACKET_TYPE_GAMUT_METADATA: + lspcon_drm_write_infoframe(encoder, crtc_state, + HDMI_PACKET_TYPE_GAMUT_METADATA, + frame, VIDEO_DIP_DATA_SIZE); + break; + default: + return; + } if (!ret) { - DRM_ERROR("Failed to write AVI infoframes\n"); + DRM_ERROR("Failed to write infoframes\n"); return; } - DRM_DEBUG_DRIVER("AVI infoframes updated successfully\n"); + DRM_DEBUG_DRIVER("Infoframes updated successfully\n"); } void lspcon_read_infoframe(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 37cfddf8a9c5..b2051f236223 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -34,5 +34,8 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config); void lspcon_ycbcr420_config(struct drm_connector *connector, struct intel_crtc_state *crtc_state); - +void lspcon_drm_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len); #endif /* __INTEL_LSPCON_H__ */ -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:30 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:30 +0530 Subject: [Intel-gfx] [v5 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-4-uma.shankar@intel.com> Attach HDR property for Gen9 devices with MCA LSPCON chips. v2: Cleaned HDR property attachment logic based on capability as per Jani Nikula's suggestion. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 95d29c379076..7113c2efdab4 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -626,6 +626,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) lspcon_detect_hdr_capability(lspcon); + if (lspcon->hdr_supported) + drm_object_attach_property(&connector->base, + connector->dev->mode_config.hdr_output_metadata_property, + 0); + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n"); -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:31 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:31 +0530 Subject: [Intel-gfx] [v5 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-5-uma.shankar@intel.com> Enable Colorspace as BT2020 if driving HDR content.Sending Colorimetry data for HDR using AVI infoframe. LSPCON firmware expects this and though SOC drives DP, for HDMI panel AVI infoframe is sent to the LSPCON device which transfers the same to HDMI sink. v2: Dropped state managed in drm core as per Jani Nikula's suggestion. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 7113c2efdab4..10e2823bf1ae 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -507,6 +507,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder, /* FIXME implement this */ } +/* HDMI HDR Colorspace Spec Definitions */ +#define NORMAL_COLORIMETRY_MASK 0x3 +#define EXTENDED_COLORIMETRY_MASK 0x7 +#define HDMI_COLORIMETRY_BT2020_YCC ((3 << 0) | (6 << 2) | (0 << 5)) + void lspcon_set_infoframes(struct intel_encoder *encoder, bool enable, const struct intel_crtc_state *crtc_state, @@ -551,6 +556,19 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, HDMI_QUANTIZATION_RANGE_LIMITED : HDMI_QUANTIZATION_RANGE_FULL); + /* + * Set BT2020 colorspace if driving HDR data + * ToDo: Make this generic and expose all colorspaces for lspcon + */ + if (lspcon->active && lspcon->hdr_supported) { + frame.avi.colorimetry = + HDMI_COLORIMETRY_BT2020_YCC & + NORMAL_COLORIMETRY_MASK; + frame.avi.extended_colorimetry = + (HDMI_COLORIMETRY_BT2020_YCC >> 2) & + EXTENDED_COLORIMETRY_MASK; + } + ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf)); if (ret < 0) { DRM_ERROR("Failed to pack AVI IF\n"); -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:32 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:32 +0530 Subject: [Intel-gfx] [v5 05/11] drm/i915/display: Enable HDR for Parade based lspcon In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-6-uma.shankar@intel.com> Enable HDR for LSPCON based on Parade along with MCA. Signed-off-by: Uma Shankar <uma.shankar at intel.com> Signed-off-by: Vipin Anand <vipin.anand at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 10e2823bf1ae..9034ce6f20b9 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -36,6 +36,7 @@ #define LSPCON_VENDOR_MCA_OUI 0x0060AD #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 +#define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511 /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 @@ -112,16 +113,20 @@ static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) container_of(lspcon, struct intel_digital_port, lspcon); struct drm_device *dev = intel_dig_port->base.base.dev; struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u32 lspcon_hdr_status_reg; u8 hdr_caps; int ret; - /* Enable HDR for MCA based LSPCON devices */ if (lspcon->vendor == LSPCON_VENDOR_MCA) - ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, - &hdr_caps, 1); + lspcon_hdr_status_reg = DPCD_MCA_LSPCON_HDR_STATUS; + else if (lspcon->vendor == LSPCON_VENDOR_PARADE) + lspcon_hdr_status_reg = DPCD_PARADE_LSPCON_HDR_STATUS; else return; + ret = drm_dp_dpcd_read(&dp->aux, lspcon_hdr_status_reg, + &hdr_caps, 1); + if (ret < 0) { drm_dbg_kms(dev, "hdr capability detection failed\n"); lspcon->hdr_supported = false; @@ -465,14 +470,6 @@ void lspcon_write_infoframe(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); - /* - * Supporting HDR on MCA LSPCON - * Todo: Add support for Parade later - */ - if (type == HDMI_PACKET_TYPE_GAMUT_METADATA && - lspcon->vendor != LSPCON_VENDOR_MCA) - return; - switch (type) { case HDMI_INFOFRAME_TYPE_AVI: if (lspcon->vendor == LSPCON_VENDOR_MCA) -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:34 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:34 +0530 Subject: [Intel-gfx] [v5 07/11] drm/i915/display: Implement DRM infoframe read for LSPCON In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-8-uma.shankar@intel.com> Implement Read back of HDR metadata infoframes i.e Dynamic Range and Mastering Infoframe for LSPCON devices. v2: Added proper bitmask of enabled infoframes as per Ville's recommendation. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_hdmi.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_lspcon.c | 6 +++++- drivers/gpu/drm/i915/display/intel_lspcon.h | 4 ++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 53103ef72a58..786378442dd2 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -600,6 +600,16 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder, hsw_write_infoframe(encoder, crtc_state, type, frame, len); } +void lspcon_drm_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len) +{ + drm_dbg_kms(encoder->base.dev, "Read HDR metadata for lspcon\n"); + /* It uses the legacy hsw implementation for the same */ + hsw_read_infoframe(encoder, crtc_state, type, frame, len); +} + static const u8 infoframe_type_to_idx[] = { HDMI_PACKET_TYPE_GENERAL_CONTROL, HDMI_PACKET_TYPE_GAMUT_METADATA, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 0f19eb6c5a6d..58ebcd198d9e 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -501,7 +501,11 @@ void lspcon_read_infoframe(struct intel_encoder *encoder, unsigned int type, void *frame, ssize_t len) { - /* FIXME implement this */ + /* FIXME implement for AVI Infoframe as well */ + if (type == HDMI_PACKET_TYPE_GAMUT_METADATA) + lspcon_drm_read_infoframe(encoder, crtc_state, + HDMI_PACKET_TYPE_GAMUT_METADATA, + frame, VIDEO_DIP_DATA_SIZE); } /* HDMI HDR Colorspace Spec Definitions */ diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index b2051f236223..68d2d835bd86 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -38,4 +38,8 @@ void lspcon_drm_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type, const void *frame, ssize_t len); +void lspcon_drm_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len); #endif /* __INTEL_LSPCON_H__ */ -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:33 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:33 +0530 Subject: [Intel-gfx] [v5 06/11] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-7-uma.shankar@intel.com> Implemented Infoframes enabled readback for LSPCON devices. This will help align the implementation with state readback infrastructure. v2: Added proper bitmask of enabled infoframes as per Ville's recommendation. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_lspcon.c | 57 ++++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 9034ce6f20b9..0f19eb6c5a6d 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -576,11 +576,64 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, buf, ret); } +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = LSPCON_MCA_AVI_IF_CTRL; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); + return false; + } + + return val & LSPCON_MCA_AVI_IF_KICKOFF; +} + +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); + return false; + } + + return val & LSPCON_PARADE_AVI_IF_KICKOFF; +} + u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { - /* FIXME actually read this from the hw */ - return 0; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + bool infoframes_enabled; + u32 val = 0; + u32 mask, tmp; + + if (lspcon->vendor == LSPCON_VENDOR_MCA) + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); + else + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); + + if (infoframes_enabled) + val |= VIDEO_DIP_ENABLE_AVI_HSW; + + if (lspcon->hdr_supported) { + tmp = intel_de_read(dev_priv, + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); + mask = VIDEO_DIP_ENABLE_GMP_HSW; + + if (tmp & mask) + val |= mask; + } + + return val; } void lspcon_resume(struct intel_lspcon *lspcon) -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:35 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:35 +0530 Subject: [Intel-gfx] [v5 08/11] drm/i915/lspcon: Create separate infoframe_enabled helper In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-9-uma.shankar@intel.com> Lspcon has Infoframes as well as DIP for HDR metadata(DRM Infoframe). Create a separate mechanism for lspcon compared to HDMI in order to address the same and ensure future scalability. Suggested-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++--- drivers/gpu/drm/i915/display/intel_lspcon.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_lspcon.h | 2 ++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..9742057dbcbc 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4187,6 +4187,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u32 temp, flags = 0; /* XXX: DSI transcoder paranoia */ @@ -4277,9 +4278,12 @@ void intel_ddi_get_config(struct intel_encoder *encoder, pipe_config->fec_enable); } - pipe_config->infoframes.enable |= - intel_hdmi_infoframes_enabled(encoder, pipe_config); - + if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) + pipe_config->infoframes.enable |= + intel_lspcon_infoframes_enabled(encoder, pipe_config); + else + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); break; case TRANS_DDI_MODE_SELECT_DP_MST: pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 58ebcd198d9e..52334747fb01 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -30,6 +30,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_lspcon.h" +#include "intel_hdmi.h" /* LSPCON OUI Vendor ID(signatures) */ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 @@ -640,6 +641,23 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, return val; } +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u32 val, enabled = 0; + + val = dig_port->infoframes_enabled(encoder, pipe_config); + + if (val & VIDEO_DIP_ENABLE_AVI_HSW) + enabled |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); + + if (val & VIDEO_DIP_ENABLE_GMP_HSW) + enabled |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); + + return enabled; +} + void lspcon_resume(struct intel_lspcon *lspcon) { enum drm_lspcon_mode expected_mode; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 68d2d835bd86..8ac5bd8d981d 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -42,4 +42,6 @@ void lspcon_drm_read_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type, void *frame, ssize_t len); +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config); #endif /* __INTEL_LSPCON_H__ */ -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:36 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:36 +0530 Subject: [Intel-gfx] [v5 09/11] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-10-uma.shankar@intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> Non-HDMI sinks shouldn't be sent infoframes. Check for that when using LSPCON. FIXME: How do we turn off infoframes once enabled? Do we even have to? Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++------ drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 9742057dbcbc..d5b14d3d5aee 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3451,19 +3451,17 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, conn_state); } else { - struct intel_lspcon *lspcon = - enc_to_intel_lspcon(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); - if (lspcon->active) { - struct intel_digital_port *dig_port = - enc_to_dig_port(encoder); + /* FIXME precompute everything properly */ + /* FIXME how do we turn infoframes off again? */ + if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) dig_port->set_infoframes(encoder, crtc_state->has_infoframe, crtc_state, conn_state); - } } } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ca99a05f52da..57f89fdcb50f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1272,6 +1272,7 @@ struct intel_dp { u8 sink_count; bool link_mst; bool link_trained; + bool has_hdmi_sink; bool has_audio; bool reset_link_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 42589cae766d..c6b2b307cf4e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6104,7 +6104,11 @@ intel_dp_set_edid(struct intel_dp *intel_dp) edid = intel_dp_get_edid(intel_dp); intel_connector->detect_edid = edid; - intel_dp->has_audio = drm_detect_monitor_audio(edid); + if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { + intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); + intel_dp->has_audio = drm_detect_monitor_audio(edid); + } + drm_dp_cec_set_edid(&intel_dp->aux, edid); intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); } @@ -6118,6 +6122,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) kfree(intel_connector->detect_edid); intel_connector->detect_edid = NULL; + intel_dp->has_hdmi_sink = false; intel_dp->has_audio = false; intel_dp->edid_quirks = 0; } -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:37 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:37 +0530 Subject: [Intel-gfx] [v5 10/11] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-11-uma.shankar@intel.com> Non-HDMI sinks shouldn't be sent Dynamic Range and Mastering infoframes. Check for that when using LSPCON. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d5b14d3d5aee..027b3b96e4f8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3714,6 +3714,7 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum port port = encoder->port; if (port == PORT_A && INTEL_GEN(dev_priv) < 9) @@ -3721,7 +3722,14 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, intel_edp_backlight_on(crtc_state, conn_state); intel_psr_enable(intel_dp, crtc_state, conn_state); - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + + if (dig_port->lspcon.active) { + if (dig_port->dp.has_hdmi_sink) + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + } else { + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + } + intel_edp_drrs_enable(intel_dp, crtc_state); if (crtc_state->has_audio) -- 2.22.0 From uma.shankar at intel.com Mon Jun 22 20:00:38 2020 From: uma.shankar at intel.com (Uma Shankar) Date: Tue, 23 Jun 2020 01:30:38 +0530 Subject: [Intel-gfx] [v5 11/11] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <20200622200038.14034-12-uma.shankar@intel.com> Blanking needs to be reduced to incorporate DP and HDMI timing/link bandwidth limitations for CEA modes (4k at 60 at 10 bpp). DP can drive 17.28Gbs while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will cause mode to blank out. Reduced Htotal by shortening the back porch and front porch within permissible limits. Note: This is for reference for userspace, not to be merged in kernel. v2: This is marked as Not for merge and the responsibilty to program these custom timings will be on userspace. This patch is just for reference purposes. This is based on Ville's recommendation. v3: updated commit message. Signed-off-by: Uma Shankar <uma.shankar at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c6b2b307cf4e..0db8a7d65c35 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -632,8 +632,10 @@ intel_dp_mode_valid(struct drm_connector *connector, { struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; struct drm_i915_private *dev_priv = to_i915(connector->dev); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(intel_encoder); int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk; @@ -655,6 +657,21 @@ intel_dp_mode_valid(struct drm_connector *connector, target_clock = fixed_mode->clock; } + /* + * Reducing Blanking to incorporate DP and HDMI timing/link bandwidth + * limitations for CEA modes (4k at 60 at 10 bpp). DP can drive 17.28Gbs + * while 4k modes (VIC97 etc) at 10 bpp required 17.8 Gbps. This will + * cause mode to blank out. Reduced Htotal by shortening the back porch + * and front porch within permissible limits. + */ + if (lspcon->active && lspcon->hdr_supported && + mode->clock > 570000) { + mode->clock = 570000; + mode->htotal -= 180; + mode->hsync_start -= 72; + mode->hsync_end -= 72; + } + max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); -- 2.22.0 From ville.syrjala at linux.intel.com Mon Jun 22 19:39:23 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 22 Jun 2020 22:39:23 +0300 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2D4@BGSMSX104.gar.corp.intel.com> References: <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> <20200622170246.GP6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2D4@BGSMSX104.gar.corp.intel.com> Message-ID: <20200622193923.GT6112@intel.com> On Mon, Jun 22, 2020 at 05:21:50PM +0000, Shankar, Uma wrote: > > > > > > > > > -----Original Message----- > > > > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > Sent: Thursday, June 11, 2020 9:31 PM > > > > > > > > To: Shankar, Uma <uma.shankar at intel.com> > > > > > > > > Cc: intel-gfx at lists.freedesktop.org; > > > > > > > > jani.nikula at linux.intel.com; Mun, Gwan- gyeong > > > > > > > > <gwan-gyeong.mun at intel.com> > > > > > > > > Subject: Re: [v3 6/8] drm/i915/display: Implement infoframes > > > > > > > > readback for LSPCON > > > > > > > > > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > > > > > This will help align the implementation with state > > > > > > > > > > readback infrastructure. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > > > > > --- > > > > > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > > > > > ++++++++++++++++++++- > > > > > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > @@ -576,11 +576,70 @@ void lspcon_set_infoframes(struct > > > > > > > > > > intel_encoder > > > > > > > > *encoder, > > > > > > > > > > buf, ret); > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > +static bool > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > > + int ret; > > > > > > > > > > + u32 val = 0; > > > > > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > > > > > + > > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > > + if (ret < 0) { > > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > > > + return false; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > > > > > + return true; > > > > > > > > > > + > > > > > > > > > > + return false; > > > > > > > > > > > > > > > > > > return val & ...; > > > > > > > > > > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > +static bool > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > > + int ret; > > > > > > > > > > + u32 val = 0; > > > > > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > > > > > + > > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > > + if (ret < 0) { > > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", reg); > > > > > > > > > > + return false; > > > > > > > > > > + } > > > > > > > > > > + > > > > > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > > > > > + return true; > > > > > > > > > > + > > > > > > > > > > + return false; > > > > > > > > > > +} > > > > > > > > > > + > > > > > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > > > > > > > > > > const struct intel_crtc_state *pipe_config) { > > > > > > > > > > - /* FIXME actually read this from the hw */ > > > > > > > > > > - return 0; > > > > > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > > > > > + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); > > > > > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > > > > > > > > > + bool infoframes_enabled; > > > > > > > > > > + u32 mask = 0; > > > > > > > > > > + u32 val; > > > > > > > > > > + > > > > > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > > > > > + infoframes_enabled = > > > > > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > > > > > + else > > > > > > > > > > + infoframes_enabled = > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp->au > > > > > > > > > > +x) > > > > > > > > > > +; > > > > > > > > > > + > > > > > > > > > > + if (infoframes_enabled) > > > > > > > > > > + return true; > > > > > > > > > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > > > > > > > > > Actually since we're dealing with both the LSPCON specific > > > > > > > > stuff and DIP stuff for the DRM infoframe I think we should > > > > > > > > stop using using intel_hdmi_infoframes_enabled(), and > > > > > > > > instead provide a LSPCON specific replacement for it. That > > > > > > > > way we can directly return the abstract bitmask instead of > > > > > > > > pretending to return a bitmask of > > > > > the DIP bits. > > > > > > > > We have DP (VSC etc) packets also managed as HDMI infoframes only. > > > > We can keep the same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW for > > > > AVI and similarly VIDEO_DIP_ENABLE_GMP_HSW for DRM (HDR metadata). > > > > This will > > > help all the helper align appropriately even in the intel_dump_pipe_config. > > > > > > intel_dump_infoframe() does not use any platform specific bitmasks. > > > So I don't understand what you're talking about here. > > > > What I meant is that if we continue to use the existing values and bitmask, we > > can have lspcon infoframes_enabled return the appropriate type of infoframe > > which is active (as you suggested) and later with intel_dump_pipe_config when it > > checks for intel_hdmi_infoframe_enable, we will get a matching value in > > pipe_config->infoframes.enable and be able to dump them as well. Hope I am on > > same page with you here. > > > > > > > > > > Will fix this accordingly and send the next version. Hope this is ok. > > > > > > > > > > > Sure, will fix this and resend the next version. > > > > > > > > > > > > > > > > > > > > > > > > > Also my question "how do we turn off infoframes once enabled?" > > > > > > > > > from > > > > > > > > > https://patchwork.freedesktop.org/patch/351719/?series=729 > > > > > > > > > 28 > > > > > > > > > &rev > > > > > > > > > =1 > > > > > > > > > still remains unanswered... > > > > > > > > > > > > > > For the AVI infoframe we generally compute and change the > > > > > > > respective values. If no change is requested and computed we > > > > > > > can let the existing infoframes be transmitted. AFAIK there is > > > > > > > no mechanism called out, to explicitly disable this on Lspcon. > > > > > > > Have not seen any issues due to this, so > > > > > > hoping that it may be safe even if they are enabled. > > > > > > > > > > > > It's not valid to transmit infoframes to DVI sinks. > > > > > > > > > > With your fix, we won't be enabling or setting the infoframe on DVI sinks. > > > > > If I understand correctly, we may have issue if we connect HDMI > > > > > (where we would have sent the infoframe) and later unplug and plug > > > > > a DVI sink. With unplug if Lspcon is not resetting this internally > > > > > then this will be a problem. I will try to get this information on > > > > > Lspcon > > > behavior. > > > > > > > > Hi Ville, > > > > Searched various docs on LSPCON and couldn't find any mention of > > > > disabling > > > infoframe. > > > > Reached out to few folks who were interfacing with Lspcon vendors > > > > and got this finally clarified. The expectation is that LSPCON will > > > > reset stuff on unplug and will not send infoframes to DVI sink, so > > > > from source side we don't need to explicitly disable them. Lspcon > > > > will take care of > > > this, this was tested for compliance as well by them. > > > > > > Unplug is irrelevant. We also have the property by which the user can > > > force the inforframes off. > > Oh ok, but it seems we don't have an option to disable them on LSPCON. They have not > added any interface for that unfortunately. That seems a bit crazy. What happens if we just zero out the whole thing? The parade version at least seems to have that "token" byte which maybe could be used to specify whether the infoframe is enabled? -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Mon Jun 22 19:54:30 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 19:54:30 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Enable_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev5=29?= In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <159285567076.9207.1603527838102941458@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev5) URL : https://patchwork.freedesktop.org/series/68081/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From uma.shankar at intel.com Mon Jun 22 20:05:06 2020 From: uma.shankar at intel.com (Shankar, Uma) Date: Mon, 22 Jun 2020 20:05:06 +0000 Subject: [Intel-gfx] [v3 6/8] drm/i915/display: Implement infoframes readback for LSPCON In-Reply-To: <20200622193923.GT6112@intel.com> References: <20200610191232.11620-7-uma.shankar@intel.com> <20200611154650.GB6112@intel.com> <20200611160112.GC6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F3E0@BGSMSX104.gar.corp.intel.com> <20200615205233.GS6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8255F444@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256CDCF@BGSMSX104.gar.corp.intel.com> <20200622170246.GP6112@intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2B9@BGSMSX104.gar.corp.intel.com> <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D2D4@BGSMSX104.gar.corp.intel.com> <20200622193923.GT6112@intel.com> Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F8256D6EC@BGSMSX104.gar.corp.intel.com> > > > > > > > > > On Thu, Jun 11, 2020 at 06:46:50PM +0300, Ville Syrj?l? wrote: > > > > > > > > > > On Thu, Jun 11, 2020 at 12:42:30AM +0530, Uma Shankar wrote: > > > > > > > > > > > Implemented Infoframes enabled readback for LSPCON devices. > > > > > > > > > > > This will help align the implementation with state > > > > > > > > > > > readback infrastructure. > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Uma Shankar <uma.shankar at intel.com> > > > > > > > > > > > --- > > > > > > > > > > > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 > > > > > > > > > > > ++++++++++++++++++++- > > > > > > > > > > > 1 file changed, 61 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > > > a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > > b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > > index 9034ce6f20b9..0ebe9a700291 100644 > > > > > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > > > > > > > > > > > @@ -576,11 +576,70 @@ void > > > > > > > > > > > lspcon_set_infoframes(struct intel_encoder > > > > > > > > > *encoder, > > > > > > > > > > > buf, ret); > > > > > > > > > > > } > > > > > > > > > > > > > > > > > > > > > > +static bool > > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_mca(struct > > > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > > > + int ret; > > > > > > > > > > > + u32 val = 0; > > > > > > > > > > > + u16 reg = LSPCON_MCA_AVI_IF_CTRL; > > > > > > > > > > > + > > > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > > > + if (ret < 0) { > > > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", > reg); > > > > > > > > > > > + return false; > > > > > > > > > > > + } > > > > > > > > > > > + > > > > > > > > > > > + if (val & LSPCON_MCA_AVI_IF_KICKOFF) > > > > > > > > > > > + return true; > > > > > > > > > > > + > > > > > > > > > > > + return false; > > > > > > > > > > > > > > > > > > > > return val & ...; > > > > > > > > > > > > > > > > > > > > > +} > > > > > > > > > > > + > > > > > > > > > > > +static bool > > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(struct > > > > > > > > > > > +drm_dp_aux *aux) { > > > > > > > > > > > + int ret; > > > > > > > > > > > + u32 val = 0; > > > > > > > > > > > + u16 reg = LSPCON_PARADE_AVI_IF_CTRL; > > > > > > > > > > > + > > > > > > > > > > > + ret = drm_dp_dpcd_read(aux, reg, &val, 1); > > > > > > > > > > > + if (ret < 0) { > > > > > > > > > > > + DRM_ERROR("DPCD read failed, address 0x%x\n", > reg); > > > > > > > > > > > + return false; > > > > > > > > > > > + } > > > > > > > > > > > + > > > > > > > > > > > + if (val & LSPCON_PARADE_AVI_IF_KICKOFF) > > > > > > > > > > > + return true; > > > > > > > > > > > + > > > > > > > > > > > + return false; > > > > > > > > > > > +} > > > > > > > > > > > + > > > > > > > > > > > u32 lspcon_infoframes_enabled(struct intel_encoder > *encoder, > > > > > > > > > > > const struct intel_crtc_state > *pipe_config) { > > > > > > > > > > > - /* FIXME actually read this from the hw */ > > > > > > > > > > > - return 0; > > > > > > > > > > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > > > > > > > > > > + struct intel_lspcon *lspcon = > enc_to_intel_lspcon(encoder); > > > > > > > > > > > + struct drm_i915_private *dev_priv = to_i915(encoder- > >base.dev); > > > > > > > > > > > + bool infoframes_enabled; > > > > > > > > > > > + u32 mask = 0; > > > > > > > > > > > + u32 val; > > > > > > > > > > > + > > > > > > > > > > > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > > > > > > > > > > > + infoframes_enabled = > > > > > > > > > _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); > > > > > > > > > > > + else > > > > > > > > > > > + infoframes_enabled = > > > > > > > > > > > +_lspcon_read_avi_infoframe_enabled_parade(&intel_dp > > > > > > > > > > > +->au > > > > > > > > > > > +x) > > > > > > > > > > > +; > > > > > > > > > > > + > > > > > > > > > > > + if (infoframes_enabled) > > > > > > > > > > > + return true; > > > > > > > > > > > > > > > > > > > > This is supposed to return a bitmask of all enabled infoframes. > > > > > > > > > > > > > > > > > Actually since we're dealing with both the LSPCON > > > > > > > > > specific stuff and DIP stuff for the DRM infoframe I > > > > > > > > > think we should stop using using > > > > > > > > > intel_hdmi_infoframes_enabled(), and instead provide a > > > > > > > > > LSPCON specific replacement for it. That way we can > > > > > > > > > directly return the abstract bitmask instead of > > > > > > > > > pretending to return a bitmask of > > > > > > the DIP bits. > > > > > > > > > > We have DP (VSC etc) packets also managed as HDMI infoframes only. > > > > > We can keep the same with bitmask as VIDEO_DIP_ENABLE_AVI_HSW > > > > > for AVI and similarly VIDEO_DIP_ENABLE_GMP_HSW for DRM (HDR > metadata). > > > > > This will > > > > help all the helper align appropriately even in the intel_dump_pipe_config. > > > > > > > > intel_dump_infoframe() does not use any platform specific bitmasks. > > > > So I don't understand what you're talking about here. > > > > > > What I meant is that if we continue to use the existing values and > > > bitmask, we can have lspcon infoframes_enabled return the > > > appropriate type of infoframe which is active (as you suggested) and > > > later with intel_dump_pipe_config when it checks for > > > intel_hdmi_infoframe_enable, we will get a matching value in > > > pipe_config->infoframes.enable and be able to dump them as well. Hope I > am on same page with you here. > > > > > > > > > > > > > Will fix this accordingly and send the next version. Hope this is ok. > > > > > > > > > > > > > Sure, will fix this and resend the next version. > > > > > > > > > > > > > > > > > > > > > > > > > > > > Also my question "how do we turn off infoframes once > enabled?" > > > > > > > > > > from > > > > > > > > > > https://patchwork.freedesktop.org/patch/351719/?series > > > > > > > > > > =729 > > > > > > > > > > 28 > > > > > > > > > > &rev > > > > > > > > > > =1 > > > > > > > > > > still remains unanswered... > > > > > > > > > > > > > > > > For the AVI infoframe we generally compute and change the > > > > > > > > respective values. If no change is requested and computed > > > > > > > > we can let the existing infoframes be transmitted. AFAIK > > > > > > > > there is no mechanism called out, to explicitly disable this on > Lspcon. > > > > > > > > Have not seen any issues due to this, so > > > > > > > hoping that it may be safe even if they are enabled. > > > > > > > > > > > > > > It's not valid to transmit infoframes to DVI sinks. > > > > > > > > > > > > With your fix, we won't be enabling or setting the infoframe on DVI > sinks. > > > > > > If I understand correctly, we may have issue if we connect > > > > > > HDMI (where we would have sent the infoframe) and later unplug > > > > > > and plug a DVI sink. With unplug if Lspcon is not resetting > > > > > > this internally then this will be a problem. I will try to get > > > > > > this information on Lspcon > > > > behavior. > > > > > > > > > > Hi Ville, > > > > > Searched various docs on LSPCON and couldn't find any mention of > > > > > disabling > > > > infoframe. > > > > > Reached out to few folks who were interfacing with Lspcon > > > > > vendors and got this finally clarified. The expectation is that > > > > > LSPCON will reset stuff on unplug and will not send infoframes > > > > > to DVI sink, so from source side we don't need to explicitly > > > > > disable them. Lspcon will take care of > > > > this, this was tested for compliance as well by them. > > > > > > > > Unplug is irrelevant. We also have the property by which the user > > > > can force the inforframes off. > > > > Oh ok, but it seems we don't have an option to disable them on LSPCON. > > They have not added any interface for that unfortunately. > > That seems a bit crazy. What happens if we just zero out the whole thing? The > parade version at least seems to have that "token" byte which maybe could be > used to specify whether the infoframe is enabled? Hmm, vendor has not defined his action in case we zero out stuff. Most definitely it should fail and hopefully would be able to recover without crashing himself (as this will be something he won't be expecting). For parade yeah we have the token byte which it expects to be non-zero, may be making that to 0 will trigger a failure. But no documentation regarding this is available, so cant say for sure. For the windows design which are productized, they have not disabled the infoframes. Just they try to ensure they always send appropriate values as infoframes. But yeah, this is something which was not thought of as part of Lspcon design. > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Mon Jun 22 20:14:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 20:14:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev5=29?= In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <159285688283.9207.9062413498261626992@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev5) URL : https://patchwork.freedesktop.org/series/68081/ State : success == Summary == CI Bug Log - changes from CI_DRM_8651 -> Patchwork_18005 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/index.html Known issues ------------ Here are the changes found in Patchwork_18005 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [PASS][1] -> [DMESG-WARN][2] ([i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at i915_pm_rpm@module-reload: - fi-bsw-kefka: [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#1844] / [i915#1909] / [i915#392]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-bsw-kefka/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-bsw-kefka/igt at i915_pm_rpm@module-reload.html - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [PASS][7] -> [DMESG-FAIL][8] ([i915#1233]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at kms_flip@basic-plain-flip at a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-kbl-x1275/igt at kms_flip@basic-plain-flip at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-kbl-x1275/igt at kms_flip@basic-plain-flip at a-dp1.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1844]: https://gitlab.freedesktop.org/drm/intel/issues/1844 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1909]: https://gitlab.freedesktop.org/drm/intel/issues/1909 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 38) ------------------------------ Additional (1): fi-kbl-soraka Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-guc fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8651 -> Patchwork_18005 CI-20190529: 20190529 CI_DRM_8651: f6210d1dd268f9e09e10d3704c768d7679a44f48 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5715: 3b6975c0f9e429c0c1f48c61a3417be9d68300cf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18005: 8693e9476eed01a45a08352a3d4287d989ec4507 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8693e9476eed drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60 at 10bpp for LSPCON e89edaaaa482 drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks cc5d22201f0d drm/i915/lspcon: Do not send infoframes to non-HDMI sinks db055c01d9e2 drm/i915/lspcon: Create separate infoframe_enabled helper d2c7d158139a drm/i915/display: Implement DRM infoframe read for LSPCON 538569c50e13 drm/i915/display: Implement infoframes readback for LSPCON ef977cb6b132 drm/i915/display: Enable HDR for Parade based lspcon 108ee767d0ab drm/i915/display: Enable BT2020 for HDR on LSPCON devices 97f260442e45 drm/i915/display: Attach HDR property for capable Gen9 devices 38bc2fbe32b1 drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon 79ed1e75d589 drm/i915/display: Add HDR Capability detection for LSPCON == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/index.html From jglisse at redhat.com Mon Jun 22 20:15:40 2020 From: jglisse at redhat.com (Jerome Glisse) Date: Mon, 22 Jun 2020 16:15:40 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <20200622114617.GU6578@ziepe.ca> References: <CAKMK7uE-kWA==Cko5uenMrcnopEjq42HxoDTDywzBAbHqsN13g@mail.gmail.com> <20200619151551.GP6578@ziepe.ca> <CAKMK7uEvkshAM6KUYZu8_OCpF4+1Y_SM7cQ9nJWpagfke8s8LA@mail.gmail.com> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> <56008d64-772d-5757-6136-f20591ef71d2@amd.com> <20200619195538.GT6578@ziepe.ca> <20200619203147.GC13117@redhat.com> <20200622114617.GU6578@ziepe.ca> Message-ID: <20200622201540.GB9708@redhat.com> On Mon, Jun 22, 2020 at 08:46:17AM -0300, Jason Gunthorpe wrote: > On Fri, Jun 19, 2020 at 04:31:47PM -0400, Jerome Glisse wrote: > > Not doable as page refcount can change for things unrelated to GUP, with > > John changes we can identify GUP and we could potentialy copy GUPed page > > instead of COW but this can potentialy slow down fork() and i am not sure > > how acceptable this would be. Also this does not solve GUP against page > > that are already in fork tree ie page P0 is in process A which forks, > > we now have page P0 in process A and B. Now we have process A which forks > > again and we have page P0 in A, B, and C. Here B and C are two branches > > with root in A. B and/or C can keep forking and grow the fork tree. > > For a long time now RDMA has broken COW pages when creating user DMA > regions. > > The problem has been that fork re-COW's regions that had their COW > broken. > > So, if you break the COW upon mapping and prevent fork (and others) > from copying DMA pinned then you'd cover the cases. I am not sure we want to prevent COW for pinned GUP pages, this would change current semantic and potentialy break/slow down existing apps. Anyway i think we focus too much on fork/COW, it is just an unfixable broken corner cases, mmu notifier allows you to avoid it. Forcing real copy on fork would likely be seen as regression by most people. > > Semantic was change with 17839856fd588f4ab6b789f482ed3ffd7c403e1f to some > > what "fix" that but GUP fast is still succeptible to this. > > Ah, so everyone breaks the COW now, not just RDMA.. > > What do you mean 'GUP fast is still succeptible to this' ? Not all GUP fast path are updated (intentionaly) __get_user_pages_fast() for instance still keeps COW intact. People using GUP should really knows what they are doing. Cheers, J?r?me From jani.nikula at intel.com Mon Jun 22 20:30:00 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Mon, 22 Jun 2020 23:30:00 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/params=3A_switch_to_device_specific_parameters_=28rev3=29?= In-Reply-To: <159252288903.22460.5464398107550245782@emeril.freedesktop.org> References: <20200618150402.14022-1-jani.nikula@intel.com> <159252288903.22460.5464398107550245782@emeril.freedesktop.org> Message-ID: <87tuz2oncn.fsf@intel.com> On Thu, 18 Jun 2020, Patchwork <patchwork at emeril.freedesktop.org> wrote: > == Series Details == > > Series: drm/i915/params: switch to device specific parameters (rev3) > URL : https://patchwork.freedesktop.org/series/78004/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8641_full -> Patchwork_17993_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17993_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17993_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17993_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at sysfs_heartbeat_interval@nopreempt at bcs0: > - shard-skl: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl4/igt at sysfs_heartbeat_interval@nopreempt at bcs0.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl3/igt at sysfs_heartbeat_interval@nopreempt at bcs0.html Unrelated, pushed with Micha?'s irc ack. BR, Jani. > > > Known issues > ------------ > > Here are the changes found in Patchwork_17993_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: > - shard-kbl: [PASS][3] -> [FAIL][4] ([i915#1528]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl6/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html > > * igt at gem_exec_schedule@implicit-boths at rcs0: > - shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-snb5/igt at gem_exec_schedule@implicit-boths at rcs0.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-snb4/igt at gem_exec_schedule@implicit-boths at rcs0.html > > * igt at gem_exec_whisper@basic-contexts-priority-all: > - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk1/igt at gem_exec_whisper@basic-contexts-priority-all.html > > * igt at gem_exec_whisper@basic-fds-priority-all: > - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +4 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at gem_exec_whisper@basic-fds-priority-all.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at gem_exec_whisper@basic-fds-priority-all.html > > * igt at gem_mmap_gtt@medium-copy: > - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +11 similar issues > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl7/igt at gem_mmap_gtt@medium-copy.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl7/igt at gem_mmap_gtt@medium-copy.html > > * igt at gem_tiled_pread_pwrite: > - shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb3/igt at gem_tiled_pread_pwrite.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb2/igt at gem_tiled_pread_pwrite.html > > * igt at kms_color@pipe-c-ctm-max: > - shard-skl: [PASS][15] -> [FAIL][16] ([i915#168]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_color@pipe-c-ctm-max.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl8/igt at kms_color@pipe-c-ctm-max.html > > * igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding: > - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#95]) +10 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_cursor_crc@pipe-a-cursor-64x21-sliding.html > > * igt at kms_cursor_crc@pipe-a-cursor-suspend: > - shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +4 similar issues > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html > > * igt at kms_cursor_crc@pipe-c-cursor-64x64-offscreen: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_cursor_crc@pipe-c-cursor-64x64-offscreen.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-64x64-offscreen.html > > * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: > - shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk9/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk8/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > > * igt at kms_flip@dpms-vs-vblank-race-interruptible at c-hdmi-a1: > - shard-glk: [PASS][25] -> [FAIL][26] ([i915#407]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk5/igt at kms_flip@dpms-vs-vblank-race-interruptible at c-hdmi-a1.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk6/igt at kms_flip@dpms-vs-vblank-race-interruptible at c-hdmi-a1.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) +1 similar issue > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_plane_cursor@pipe-c-primary-size-64: > - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#62]) +5 similar issues > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl7/igt at kms_plane_cursor@pipe-c-primary-size-64.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_plane_cursor@pipe-c-primary-size-64.html > > * igt at kms_psr@psr2_primary_render: > - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb2/igt at kms_psr@psr2_primary_render.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb6/igt at kms_psr@psr2_primary_render.html > > * igt at kms_setmode@basic: > - shard-apl: [PASS][35] -> [FAIL][36] ([i915#31]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl1/igt at kms_setmode@basic.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl3/igt at kms_setmode@basic.html > > * igt at kms_universal_plane@universal-plane-gen9-features-pipe-b: > - shard-tglb: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb5/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-tglb7/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html > > > #### Possible fixes #### > > * igt at gem_exec_whisper@basic-contexts-all: > - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] +1 similar issue > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk7/igt at gem_exec_whisper@basic-contexts-all.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk5/igt at gem_exec_whisper@basic-contexts-all.html > > * {igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a}: > - shard-glk: [INCOMPLETE][41] ([i915#58] / [k.org#198133]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-glk8/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-glk6/igt at kms_atomic_transition@plane-all-transition at hdmi-a-1-pipe-a.html > > * igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding: > - shard-apl: [FAIL][43] ([i915#54]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_cursor_crc@pipe-c-cursor-256x85-sliding.html > > * igt at kms_cursor_legacy@cursor-vs-flip-toggle: > - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +1 similar issue > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl5/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl10/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html > > * igt at kms_flip@flip-vs-suspend at c-dp1: > - shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +7 similar issues > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html > > * igt at kms_flip_tiling@flip-x-tiled: > - shard-apl: [DMESG-WARN][49] ([i915#95]) -> [PASS][50] +13 similar issues > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl6/igt at kms_flip_tiling@flip-x-tiled.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl8/igt at kms_flip_tiling@flip-x-tiled.html > > * igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: > - shard-iclb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb7/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb5/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt: > - shard-tglb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt.html > > * igt at kms_hdr@bpc-switch-dpms: > - shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl10/igt at kms_hdr@bpc-switch-dpms.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl3/igt at kms_hdr@bpc-switch-dpms.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] +1 similar issue > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt at kms_psr@no_drrs: > - shard-iclb: [FAIL][59] ([i915#173]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb1/igt at kms_psr@no_drrs.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb6/igt at kms_psr@no_drrs.html > > * igt at kms_psr@psr2_cursor_blt: > - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +2 similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-iclb3/igt at kms_psr@psr2_cursor_blt.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html > > > #### Warnings #### > > * igt at gem_eio@execbuf: > - shard-apl: [DMESG-WARN][63] ([i915#95]) -> [DMESG-WARN][64] ([i915#62]) > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl7/igt at gem_eio@execbuf.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at gem_eio@execbuf.html > > * igt at i915_pm_dc@dc6-psr: > - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#1899]) > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-tglb2/igt at i915_pm_dc@dc6-psr.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-tglb6/igt at i915_pm_dc@dc6-psr.html > > * igt at i915_suspend@fence-restore-tiled2untiled: > - shard-kbl: [DMESG-WARN][67] ([i915#93] / [i915#95]) -> [DMESG-WARN][68] ([i915#180] / [i915#93] / [i915#95]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl6/igt at i915_suspend@fence-restore-tiled2untiled.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at i915_suspend@fence-restore-tiled2untiled.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: > - shard-skl: [DMESG-FAIL][69] ([i915#1982] / [i915#79]) -> [FAIL][70] ([i915#79]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-skl2/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html > > * igt at kms_frontbuffer_tracking@fbc-suspend: > - shard-kbl: [DMESG-WARN][71] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][72] ([i915#93] / [i915#95]) > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html > > * igt at kms_properties@crtc-properties-atomic: > - shard-apl: [DMESG-WARN][73] ([i915#95]) -> [DMESG-FAIL][74] ([i915#62]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8641/shard-apl7/igt at kms_properties@crtc-properties-atomic.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/shard-apl6/igt at kms_properties@crtc-properties-atomic.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#168]: https://gitlab.freedesktop.org/drm/intel/issues/168 > [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407 > [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8641 -> Patchwork_17993 > > CI-20190529: 20190529 > CI_DRM_8641: aac91f91c7be78f53b352237d968dfa1996b2d4b @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5712: eba1135ddd35f9d3097ed91032aefe8f9a9f9d02 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17993: 7e653187560babd808318d160f9a3f8dcee515a8 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17993/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center From lucas.demarchi at intel.com Mon Jun 22 20:43:45 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 13:43:45 -0700 Subject: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling In-Reply-To: <20200622183509.GB25163@ideak-desk.fi.intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-21-lucas.demarchi@intel.com> <20200622183509.GB25163@ideak-desk.fi.intel.com> Message-ID: <20200622204345.l3hbdamz4zgymbuc@ldmartin-desk1> On Mon, Jun 22, 2020 at 09:35:09PM +0300, Imre Deak wrote: >On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote: >> DG1 has one more combo phy port, no TC and all irq handling goes through >> SDE, like for MCC. >> >> Cc: Anshuman Gupta <anshuman.gupta at intel.com> >> Cc: Jos? Roberto de Souza <jose.souza at intel.com> >> Cc: Imre Deak <imre.deak at intel.com> >> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> >> --- >> drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++---- >> drivers/gpu/drm/i915/i915_reg.h | 8 +++++ >> 2 files changed, 59 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> index 48e1686df3416..3707f9231171f 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.c >> +++ b/drivers/gpu/drm/i915/i915_irq.c >> @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { >> [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), >> }; >> >> +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = { >> + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A), >> + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B), >> + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C), >> + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D), > >The above 2 entries look incorrect. encoder->hpd_pin will be assigned >based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1 Humn... it was not like that. It seems to have changed recently: 270810a73210 ("drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)") Thanks for spotting that. Lucas De Marchi >port D is connected to PHY C and port E is connected to PHY D. So the >above two pin definitions should be: > > [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C), > [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D), > >> +}; >> + >> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) >> { >> struct i915_hotplug *hpd = &dev_priv->hotplug; >> @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) >> else >> hpd->hpd = hpd_ilk; >> >> - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) >> + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && >> + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) >> return; >> >> - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) >> + if (HAS_PCH_DG1(dev_priv)) >> + hpd->pch_hpd = hpd_dg1_sde; >> + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) >> hpd->pch_hpd = hpd_tgp; >> else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) >> hpd->pch_hpd = hpd_icp; >> @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) >> } >> } >> >> +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) >> +{ >> + switch (pin) { >> + case HPD_PORT_A: >> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A); >> + case HPD_PORT_B: >> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B); >> + case HPD_PORT_D: >> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C); >> + case HPD_PORT_E: >> + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D); >> + default: >> + return false; >> + } >> +} >> + >> static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) >> { >> switch (pin) { >> @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) >> u32 ddi_hotplug_trigger, tc_hotplug_trigger; >> u32 pin_mask = 0, long_mask = 0; >> bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); >> + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); >> >> - if (HAS_PCH_TGP(dev_priv)) { >> + if (HAS_PCH_DG1(dev_priv)) { >> + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1; >> + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect; >> + tc_hotplug_trigger = 0; >> + } else if (HAS_PCH_TGP(dev_priv)) { >> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; >> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; >> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; >> tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; >> } else if (HAS_PCH_JSP(dev_priv)) { >> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; >> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; >> tc_hotplug_trigger = 0; >> } else if (HAS_PCH_MCC(dev_priv)) { >> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; >> @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) >> INTEL_PCH_TYPE(dev_priv)); >> >> ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; >> + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; >> tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; >> tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; >> } >> @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) >> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, >> ddi_hotplug_trigger, dig_hotplug_reg, >> dev_priv->hotplug.pch_hpd, >> - icp_ddi_port_hotplug_long_detect); >> + ddi_port_hotplug_long_detect); >> } >> >> if (tc_hotplug_trigger) { >> @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) >> TGP_DDI_HPD_ENABLE_MASK, 0); >> } >> >> +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) >> +{ >> + icp_hpd_irq_setup(dev_priv, >> + SDE_DDI_MASK_DG1, 0, >> + DG1_DDI_HPD_ENABLE_MASK, 0); >> +} >> + >> static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) >> { >> u32 hotplug; >> @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) >> gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); >> I915_WRITE(SDEIMR, ~mask); >> >> - if (HAS_PCH_TGP(dev_priv)) >> + if (HAS_PCH_DG1(dev_priv)) >> + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0); >> + else if (HAS_PCH_TGP(dev_priv)) >> icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, >> TGP_TC_HPD_ENABLE_MASK); >> else if (HAS_PCH_JSP(dev_priv)) >> @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) >> if (I915_HAS_HOTPLUG(dev_priv)) >> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; >> } else { >> - if (HAS_PCH_JSP(dev_priv)) >> + if (HAS_PCH_DG1(dev_priv)) >> + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; >> + else if (HAS_PCH_JSP(dev_priv)) >> dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; >> else if (HAS_PCH_MCC(dev_priv)) >> dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 6649aeca25d72..13a989f5e8dd3 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -8168,6 +8168,10 @@ enum { >> SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ >> SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ >> SDE_TC_HOTPLUG_ICP(PORT_TC1)) >> +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \ >> + SDE_DDI_HOTPLUG_ICP(PORT_C) | \ >> + SDE_DDI_HOTPLUG_ICP(PORT_B) | \ >> + SDE_DDI_HOTPLUG_ICP(PORT_A)) >> >> #define SDEISR _MMIO(0xc4000) >> #define SDEIMR _MMIO(0xc4004) >> @@ -8367,6 +8371,10 @@ enum { >> #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ >> ICP_TC_HPD_ENABLE(PORT_TC5) | \ >> ICP_TC_HPD_ENABLE_MASK) >> +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \ >> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ >> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ >> + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) >> >> #define _PCH_DPLL_A 0xc6014 >> #define _PCH_DPLL_B 0xc6018 >> -- >> 2.26.2 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx From imre.deak at intel.com Mon Jun 22 20:54:11 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 22 Jun 2020 23:54:11 +0300 Subject: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling In-Reply-To: <20200622204345.l3hbdamz4zgymbuc@ldmartin-desk1> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-21-lucas.demarchi@intel.com> <20200622183509.GB25163@ideak-desk.fi.intel.com> <20200622204345.l3hbdamz4zgymbuc@ldmartin-desk1> Message-ID: <20200622205411.GA12843@ideak-desk.fi.intel.com> On Mon, Jun 22, 2020 at 01:43:45PM -0700, Lucas De Marchi wrote: > On Mon, Jun 22, 2020 at 09:35:09PM +0300, Imre Deak wrote: > > On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote: > > > DG1 has one more combo phy port, no TC and all irq handling goes through > > > SDE, like for MCC. > > > > > > Cc: Anshuman Gupta <anshuman.gupta at intel.com> > > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++---- > > > drivers/gpu/drm/i915/i915_reg.h | 8 +++++ > > > 2 files changed, 59 insertions(+), 6 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > > index 48e1686df3416..3707f9231171f 100644 > > > --- a/drivers/gpu/drm/i915/i915_irq.c > > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > > @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { > > > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), > > > }; > > > > > > +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = { > > > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A), > > > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B), > > > + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C), > > > + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D), > > > > The above 2 entries look incorrect. encoder->hpd_pin will be assigned > > based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1 > > Humn... it was not like that. It seems to have changed recently: > 270810a73210 ("drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)") > > Thanks for spotting that. Yea, but I think the correct change is to keep the hpd pin table above as-is and make DG1 the same case as RKL + TGP in intel_hpd_pin_default(). By changing the hpd pin table above would break the long/short pulse detection. > > Lucas De Marchi > > > port D is connected to PHY C and port E is connected to PHY D. So the > > above two pin definitions should be: > > > > [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C), > > [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D), > > > > > +}; > > > + > > > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > > > { > > > struct i915_hotplug *hpd = &dev_priv->hotplug; > > > @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) > > > else > > > hpd->hpd = hpd_ilk; > > > > > > - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) > > > + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && > > > + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) > > > return; > > > > > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > > > + if (HAS_PCH_DG1(dev_priv)) > > > + hpd->pch_hpd = hpd_dg1_sde; > > > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) > > > hpd->pch_hpd = hpd_tgp; > > > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) > > > hpd->pch_hpd = hpd_icp; > > > @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) > > > } > > > } > > > > > > +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) > > > +{ > > > + switch (pin) { > > > + case HPD_PORT_A: > > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A); > > > + case HPD_PORT_B: > > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B); > > > + case HPD_PORT_D: > > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C); > > > + case HPD_PORT_E: > > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D); > > > + default: > > > + return false; > > > + } > > > +} > > > + > > > static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) > > > { > > > switch (pin) { > > > @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > > > u32 ddi_hotplug_trigger, tc_hotplug_trigger; > > > u32 pin_mask = 0, long_mask = 0; > > > bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); > > > + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); > > > > > > - if (HAS_PCH_TGP(dev_priv)) { > > > + if (HAS_PCH_DG1(dev_priv)) { > > > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1; > > > + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect; > > > + tc_hotplug_trigger = 0; > > > + } else if (HAS_PCH_TGP(dev_priv)) { > > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; > > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; > > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; > > > tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; > > > } else if (HAS_PCH_JSP(dev_priv)) { > > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; > > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; > > > tc_hotplug_trigger = 0; > > > } else if (HAS_PCH_MCC(dev_priv)) { > > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > > > @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > > > INTEL_PCH_TYPE(dev_priv)); > > > > > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; > > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; > > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; > > > tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; > > > } > > > @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) > > > intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, > > > ddi_hotplug_trigger, dig_hotplug_reg, > > > dev_priv->hotplug.pch_hpd, > > > - icp_ddi_port_hotplug_long_detect); > > > + ddi_port_hotplug_long_detect); > > > } > > > > > > if (tc_hotplug_trigger) { > > > @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) > > > TGP_DDI_HPD_ENABLE_MASK, 0); > > > } > > > > > > +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) > > > +{ > > > + icp_hpd_irq_setup(dev_priv, > > > + SDE_DDI_MASK_DG1, 0, > > > + DG1_DDI_HPD_ENABLE_MASK, 0); > > > +} > > > + > > > static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) > > > { > > > u32 hotplug; > > > @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) > > > gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); > > > I915_WRITE(SDEIMR, ~mask); > > > > > > - if (HAS_PCH_TGP(dev_priv)) > > > + if (HAS_PCH_DG1(dev_priv)) > > > + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0); > > > + else if (HAS_PCH_TGP(dev_priv)) > > > icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, > > > TGP_TC_HPD_ENABLE_MASK); > > > else if (HAS_PCH_JSP(dev_priv)) > > > @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) > > > if (I915_HAS_HOTPLUG(dev_priv)) > > > dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; > > > } else { > > > - if (HAS_PCH_JSP(dev_priv)) > > > + if (HAS_PCH_DG1(dev_priv)) > > > + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; > > > + else if (HAS_PCH_JSP(dev_priv)) > > > dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; > > > else if (HAS_PCH_MCC(dev_priv)) > > > dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 6649aeca25d72..13a989f5e8dd3 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -8168,6 +8168,10 @@ enum { > > > SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ > > > SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ > > > SDE_TC_HOTPLUG_ICP(PORT_TC1)) > > > +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \ > > > + SDE_DDI_HOTPLUG_ICP(PORT_C) | \ > > > + SDE_DDI_HOTPLUG_ICP(PORT_B) | \ > > > + SDE_DDI_HOTPLUG_ICP(PORT_A)) > > > > > > #define SDEISR _MMIO(0xc4000) > > > #define SDEIMR _MMIO(0xc4004) > > > @@ -8367,6 +8371,10 @@ enum { > > > #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ > > > ICP_TC_HPD_ENABLE(PORT_TC5) | \ > > > ICP_TC_HPD_ENABLE_MASK) > > > +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \ > > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ > > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ > > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) > > > > > > #define _PCH_DPLL_A 0xc6014 > > > #define _PCH_DPLL_B 0xc6018 > > > -- > > > 2.26.2 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Mon Jun 22 21:58:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 21:58:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgRW5h?= =?utf-8?q?ble_HDR_on_MCA_LSPCON_based_Gen9_devices_=28rev5=29?= In-Reply-To: <20200622200038.14034-1-uma.shankar@intel.com> References: <20200622200038.14034-1-uma.shankar@intel.com> Message-ID: <159286312911.9208.1723250140234651221@emeril.freedesktop.org> == Series Details == Series: Enable HDR on MCA LSPCON based Gen9 devices (rev5) URL : https://patchwork.freedesktop.org/series/68081/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8651_full -> Patchwork_18005_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18005_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18005_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18005_full: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - shard-kbl: NOTRUN -> ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4]) ([i915#1611] / [i915#602]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl4/igt at runner@aborted.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl3/igt at runner@aborted.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl6/igt at runner@aborted.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl6/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_18005_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_sseu@engines: - shard-iclb: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb2/igt at gem_ctx_sseu@engines.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-iclb2/igt at gem_ctx_sseu@engines.html * igt at gem_exec_fence@parallel at vcs0: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk9/igt at gem_exec_fence@parallel at vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-glk4/igt at gem_exec_fence@parallel at vcs0.html * igt at gem_softpin@noreloc-s3: - shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([i915#180] / [i915#1959]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl1/igt at gem_softpin@noreloc-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl6/igt at gem_softpin@noreloc-s3.html * igt at gem_tiled_fence_blits@basic: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl3/igt at gem_tiled_fence_blits@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl3/igt at gem_tiled_fence_blits@basic.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl4/igt at i915_suspend@forcewake.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl3/igt at i915_suspend@forcewake.html * igt at i915_suspend@sysfs-reader: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#69]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl8/igt at i915_suspend@sysfs-reader.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl1/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [PASS][17] -> [DMESG-FAIL][18] ([i915#118] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_big_fb@x-tiled-32bpp-rotate-180: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +12 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl4/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl6/igt at kms_big_fb@x-tiled-32bpp-rotate-180.html * igt at kms_cursor_crc@pipe-c-cursor-64x64-onscreen: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl3/igt at kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl4/igt at kms_cursor_crc@pipe-c-cursor-64x64-onscreen.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#128]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb3/igt at kms_cursor_legacy@pipe-b-torture-move.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-tglb3/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_draw_crc@draw-method-rgb565-mmap-wc-untiled: - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#1635] / [i915#95]) +14 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl3/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl6/igt at kms_draw_crc@draw-method-rgb565-mmap-wc-untiled.html * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl4/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl6/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-wc-ytiled.html * igt at kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack: - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack.html * igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt: - shard-glk: [PASS][31] -> [FAIL][32] ([i915#49]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk2/igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-glk6/igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][33] -> [FAIL][34] ([i915#1188]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145] / [i915#265]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109642] / [fdo#111068]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb2/igt at kms_psr2_su@page_flip.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-iclb8/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-iclb6/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-kbl: [PASS][41] -> [INCOMPLETE][42] ([i915#155] / [i915#180] / [i915#794]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl6/igt at kms_vblank@pipe-c-ts-continuation-suspend.html * igt at sw_sync@sync_multi_producer_single_consumer: - shard-tglb: [PASS][43] -> [DMESG-WARN][44] ([i915#402]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb2/igt at sw_sync@sync_multi_producer_single_consumer.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-tglb6/igt at sw_sync@sync_multi_producer_single_consumer.html #### Possible fixes #### * igt at gem_ctx_persistence@replace at bcs0: - shard-skl: [FAIL][45] -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl8/igt at gem_ctx_persistence@replace at bcs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl1/igt at gem_ctx_persistence@replace at bcs0.html * igt at gem_exec_whisper@basic-fds: - shard-glk: [DMESG-WARN][47] ([i915#118] / [i915#95]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk4/igt at gem_exec_whisper@basic-fds.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-glk6/igt at gem_exec_whisper@basic-fds.html * igt at i915_suspend@forcewake: - shard-skl: [INCOMPLETE][49] ([i915#636] / [i915#69]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl1/igt at i915_suspend@forcewake.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl8/igt at i915_suspend@forcewake.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][51] ([i915#118] / [i915#95]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-glk9/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl3/igt at kms_color@pipe-a-ctm-0-5.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl10/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_edge_walk@pipe-b-128x128-bottom-edge: - shard-glk: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-glk2/igt at kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-glk1/igt at kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html * igt at kms_flip@2x-nonexisting-fb-interruptible at ab-vga1-hdmi-a1: - shard-hsw: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-hsw6/igt at kms_flip@2x-nonexisting-fb-interruptible at ab-vga1-hdmi-a1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-hsw4/igt at kms_flip@2x-nonexisting-fb-interruptible at ab-vga1-hdmi-a1.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-snb: [SKIP][59] ([fdo#109271]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-snb1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-snb2/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt at kms_hdr@bpc-switch: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-skl10/igt at kms_hdr@bpc-switch.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-skl5/igt at kms_hdr@bpc-switch.html * igt at kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-tglb: [DMESG-WARN][63] ([i915#402]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb7/igt at kms_plane_multiple@atomic-pipe-a-tiling-x.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-tglb2/igt at kms_plane_multiple@atomic-pipe-a-tiling-x.html * igt at kms_psr@psr2_no_drrs: - shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb8/igt at kms_psr@psr2_no_drrs.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-iclb2/igt at kms_psr@psr2_no_drrs.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][67] ([i915#180]) -> [PASS][68] +6 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@invalid-oa-metric-set-id: - shard-apl: [DMESG-WARN][69] ([i915#1635] / [i915#95]) -> [PASS][70] +18 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl3/igt at perf@invalid-oa-metric-set-id.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl6/igt at perf@invalid-oa-metric-set-id.html #### Warnings #### * igt at gem_ctx_persistence@engines-hang at rcs0: - shard-apl: [SKIP][71] ([fdo#109271]) -> [SKIP][72] ([fdo#109271] / [i915#1635]) +6 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl2/igt at gem_ctx_persistence@engines-hang at rcs0.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl8/igt at gem_ctx_persistence@engines-hang at rcs0.html * igt at gem_userptr_blits@process-exit-mmap at gtt: - shard-apl: [SKIP][73] ([fdo#109271] / [i915#1635] / [i915#1699]) -> [SKIP][74] ([fdo#109271] / [i915#1699]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl6/igt at gem_userptr_blits@process-exit-mmap at gtt.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl3/igt at gem_userptr_blits@process-exit-mmap at gtt.html * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][75] ([i915#588]) -> [SKIP][76] ([i915#658]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-iclb6/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [SKIP][77] ([i915#468]) -> [FAIL][78] ([i915#454]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-tglb2/igt at i915_pm_dc@dc6-psr.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-tglb7/igt at i915_pm_dc@dc6-psr.html * igt at kms_chamelium@dp-edid-read: - shard-apl: [SKIP][79] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][80] ([fdo#109271] / [fdo#111827]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl3/igt at kms_chamelium@dp-edid-read.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl6/igt at kms_chamelium@dp-edid-read.html * igt at kms_flip_tiling@flip-changes-tiling-yf: - shard-apl: [DMESG-WARN][81] ([i915#1635] / [i915#95]) -> [DMESG-FAIL][82] ([i915#1635] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl4/igt at kms_flip_tiling@flip-changes-tiling-yf.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl6/igt at kms_flip_tiling@flip-changes-tiling-yf.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [DMESG-WARN][83] ([i915#180]) -> [INCOMPLETE][84] ([i915#155] / [i915#180] / [i915#648]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-kbl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-kbl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: [FAIL][85] ([i915#265]) -> [DMESG-FAIL][86] ([i915#1635] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl2/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl1/igt at kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt at prime_nv_pcopy@test2: - shard-apl: [SKIP][87] ([fdo#109271] / [i915#1635]) -> [SKIP][88] ([fdo#109271]) +7 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8651/shard-apl6/igt at prime_nv_pcopy@test2.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/shard-apl2/igt at prime_nv_pcopy@test2.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1699]: https://gitlab.freedesktop.org/drm/intel/issues/1699 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1959]: https://gitlab.freedesktop.org/drm/intel/issues/1959 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8651 -> Patchwork_18005 CI-20190529: 20190529 CI_DRM_8651: f6210d1dd268f9e09e10d3704c768d7679a44f48 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5715: 3b6975c0f9e429c0c1f48c61a3417be9d68300cf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18005: 8693e9476eed01a45a08352a3d4287d989ec4507 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18005/index.html From lucas.demarchi at intel.com Mon Jun 22 21:59:24 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 14:59:24 -0700 Subject: [Intel-gfx] [PATCH v2 20/32] drm/i915/dg1: add hpd interrupt handling In-Reply-To: <20200622205411.GA12843@ideak-desk.fi.intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-21-lucas.demarchi@intel.com> <20200622183509.GB25163@ideak-desk.fi.intel.com> <20200622204345.l3hbdamz4zgymbuc@ldmartin-desk1> <20200622205411.GA12843@ideak-desk.fi.intel.com> Message-ID: <20200622215924.abjlra235lashoar@ldmartin-desk1> On Mon, Jun 22, 2020 at 11:54:11PM +0300, Imre Deak wrote: >On Mon, Jun 22, 2020 at 01:43:45PM -0700, Lucas De Marchi wrote: >> On Mon, Jun 22, 2020 at 09:35:09PM +0300, Imre Deak wrote: >> > On Wed, Jun 17, 2020 at 05:42:28PM -0700, Lucas De Marchi wrote: >> > > DG1 has one more combo phy port, no TC and all irq handling goes through >> > > SDE, like for MCC. >> > > >> > > Cc: Anshuman Gupta <anshuman.gupta at intel.com> >> > > Cc: Jos? Roberto de Souza <jose.souza at intel.com> >> > > Cc: Imre Deak <imre.deak at intel.com> >> > > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> >> > > --- >> > > drivers/gpu/drm/i915/i915_irq.c | 57 +++++++++++++++++++++++++++++---- >> > > drivers/gpu/drm/i915/i915_reg.h | 8 +++++ >> > > 2 files changed, 59 insertions(+), 6 deletions(-) >> > > >> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> > > index 48e1686df3416..3707f9231171f 100644 >> > > --- a/drivers/gpu/drm/i915/i915_irq.c >> > > +++ b/drivers/gpu/drm/i915/i915_irq.c >> > > @@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = { >> > > [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), >> > > }; >> > > >> > > +static const u32 hpd_dg1_sde[HPD_NUM_PINS] = { >> > > + [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A), >> > > + [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B), >> > > + [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C), >> > > + [HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D), >> > >> > The above 2 entries look incorrect. encoder->hpd_pin will be assigned >> > based on the encoder/port's PHY (see intel_hpd_pin_default()). On DG1 >> >> Humn... it was not like that. It seems to have changed recently: >> 270810a73210 ("drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)") >> >> Thanks for spotting that. > >Yea, but I think the correct change is to keep the hpd pin table above >as-is and make DG1 the same case as RKL + TGP in >intel_hpd_pin_default(). By changing the hpd pin table above would break >the long/short pulse detection. I think long term we should stop doing these conversions back and forth from port <-> phy. I will se if I can revive an old series I had to accomplish that. Lucas D Marchi > >> >> Lucas De Marchi >> >> > port D is connected to PHY C and port E is connected to PHY D. So the >> > above two pin definitions should be: >> > >> > [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PHY_C), >> > [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_D), >> > >> > > +}; >> > > + >> > > static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) >> > > { >> > > struct i915_hotplug *hpd = &dev_priv->hotplug; >> > > @@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) >> > > else >> > > hpd->hpd = hpd_ilk; >> > > >> > > - if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) >> > > + if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && >> > > + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) >> > > return; >> > > >> > > - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) >> > > + if (HAS_PCH_DG1(dev_priv)) >> > > + hpd->pch_hpd = hpd_dg1_sde; >> > > + else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) >> > > hpd->pch_hpd = hpd_tgp; >> > > else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) >> > > hpd->pch_hpd = hpd_icp; >> > > @@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) >> > > } >> > > } >> > > >> > > +static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) >> > > +{ >> > > + switch (pin) { >> > > + case HPD_PORT_A: >> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A); >> > > + case HPD_PORT_B: >> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B); >> > > + case HPD_PORT_D: >> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C); >> > > + case HPD_PORT_E: >> > > + return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D); >> > > + default: >> > > + return false; >> > > + } >> > > +} >> > > + >> > > static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) >> > > { >> > > switch (pin) { >> > > @@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) >> > > u32 ddi_hotplug_trigger, tc_hotplug_trigger; >> > > u32 pin_mask = 0, long_mask = 0; >> > > bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); >> > > + bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); >> > > >> > > - if (HAS_PCH_TGP(dev_priv)) { >> > > + if (HAS_PCH_DG1(dev_priv)) { >> > > + ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1; >> > > + ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect; >> > > + tc_hotplug_trigger = 0; >> > > + } else if (HAS_PCH_TGP(dev_priv)) { >> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; >> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; >> > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; >> > > tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; >> > > } else if (HAS_PCH_JSP(dev_priv)) { >> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; >> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; >> > > tc_hotplug_trigger = 0; >> > > } else if (HAS_PCH_MCC(dev_priv)) { >> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; >> > > @@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) >> > > INTEL_PCH_TYPE(dev_priv)); >> > > >> > > ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; >> > > + ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect; >> > > tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; >> > > tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; >> > > } >> > > @@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) >> > > intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, >> > > ddi_hotplug_trigger, dig_hotplug_reg, >> > > dev_priv->hotplug.pch_hpd, >> > > - icp_ddi_port_hotplug_long_detect); >> > > + ddi_port_hotplug_long_detect); >> > > } >> > > >> > > if (tc_hotplug_trigger) { >> > > @@ -3147,6 +3181,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) >> > > TGP_DDI_HPD_ENABLE_MASK, 0); >> > > } >> > > >> > > +static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) >> > > +{ >> > > + icp_hpd_irq_setup(dev_priv, >> > > + SDE_DDI_MASK_DG1, 0, >> > > + DG1_DDI_HPD_ENABLE_MASK, 0); >> > > +} >> > > + >> > > static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) >> > > { >> > > u32 hotplug; >> > > @@ -3535,7 +3576,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) >> > > gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); >> > > I915_WRITE(SDEIMR, ~mask); >> > > >> > > - if (HAS_PCH_TGP(dev_priv)) >> > > + if (HAS_PCH_DG1(dev_priv)) >> > > + icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0); >> > > + else if (HAS_PCH_TGP(dev_priv)) >> > > icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, >> > > TGP_TC_HPD_ENABLE_MASK); >> > > else if (HAS_PCH_JSP(dev_priv)) >> > > @@ -4051,7 +4094,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv) >> > > if (I915_HAS_HOTPLUG(dev_priv)) >> > > dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; >> > > } else { >> > > - if (HAS_PCH_JSP(dev_priv)) >> > > + if (HAS_PCH_DG1(dev_priv)) >> > > + dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup; >> > > + else if (HAS_PCH_JSP(dev_priv)) >> > > dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; >> > > else if (HAS_PCH_MCC(dev_priv)) >> > > dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; >> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> > > index 6649aeca25d72..13a989f5e8dd3 100644 >> > > --- a/drivers/gpu/drm/i915/i915_reg.h >> > > +++ b/drivers/gpu/drm/i915/i915_reg.h >> > > @@ -8168,6 +8168,10 @@ enum { >> > > SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ >> > > SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ >> > > SDE_TC_HOTPLUG_ICP(PORT_TC1)) >> > > +#define SDE_DDI_MASK_DG1 (SDE_DDI_HOTPLUG_ICP(PORT_D) | \ >> > > + SDE_DDI_HOTPLUG_ICP(PORT_C) | \ >> > > + SDE_DDI_HOTPLUG_ICP(PORT_B) | \ >> > > + SDE_DDI_HOTPLUG_ICP(PORT_A)) >> > > >> > > #define SDEISR _MMIO(0xc4000) >> > > #define SDEIMR _MMIO(0xc4004) >> > > @@ -8367,6 +8371,10 @@ enum { >> > > #define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ >> > > ICP_TC_HPD_ENABLE(PORT_TC5) | \ >> > > ICP_TC_HPD_ENABLE_MASK) >> > > +#define DG1_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \ >> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ >> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ >> > > + SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) >> > > >> > > #define _PCH_DPLL_A 0xc6014 >> > > #define _PCH_DPLL_B 0xc6018 >> > > -- >> > > 2.26.2 >> > > >> > > _______________________________________________ >> > > Intel-gfx mailing list >> > > Intel-gfx at lists.freedesktop.org >> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From lucas.demarchi at intel.com Mon Jun 22 23:28:20 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 16:28:20 -0700 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/display: remove alias to dig_port In-Reply-To: <20200622232821.3093-1-lucas.demarchi@intel.com> References: <20200622232821.3093-1-lucas.demarchi@intel.com> Message-ID: <20200622232821.3093-2-lucas.demarchi@intel.com> We don't need intel_dig_port and dig_port to refer to the same thing. Prefer the latter. Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..58c9f3d3e7ce 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3382,11 +3382,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int level = intel_ddi_hdmi_level(encoder); - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); intel_ddi_clk_select(encoder, crtc_state); @@ -3413,7 +3412,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, intel_ddi_enable_pipe_clock(encoder, crtc_state); - intel_dig_port->set_infoframes(encoder, + dig_port->set_infoframes(encoder, crtc_state->has_infoframe, crtc_state, conn_state); } -- 2.26.2 From lucas.demarchi at intel.com Mon Jun 22 23:28:19 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 16:28:19 -0700 Subject: [Intel-gfx] [PATCH 0/2] Variable renames Message-ID: <20200622232821.3093-1-lucas.demarchi@intel.com> These were part of previous unrelated series. Rebase and submit they together on their own. Lucas De Marchi (2): drm/i915/display: remove alias to dig_port drm/i915/display: prefer dig_port to reference intel_digital_port drivers/gpu/drm/i915/display/intel_ddi.c | 150 ++++---- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- .../drm/i915/display/intel_display_debugfs.c | 12 +- .../drm/i915/display/intel_display_power.c | 4 +- .../drm/i915/display/intel_display_types.h | 40 +-- drivers/gpu/drm/i915/display/intel_dp.c | 338 +++++++++--------- drivers/gpu/drm/i915/display/intel_dp.h | 4 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 74 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.h | 6 +- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 38 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 118 +++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 252 ++++++------- drivers/gpu/drm/i915/display/intel_hdmi.h | 4 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 8 +- drivers/gpu/drm/i915/display/intel_lspcon.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +- 18 files changed, 533 insertions(+), 537 deletions(-) -- 2.26.2 From lucas.demarchi at intel.com Mon Jun 22 23:28:21 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 16:28:21 -0700 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/display: prefer dig_port to reference intel_digital_port In-Reply-To: <20200622232821.3093-1-lucas.demarchi@intel.com> References: <20200622232821.3093-1-lucas.demarchi@intel.com> Message-ID: <20200622232821.3093-3-lucas.demarchi@intel.com> We have a mix of dport, intel_dport, intel_dig_port and dig_port to reference a intel_digital_port struct. Numbers are around 5 intel_dport 36 dport 479 intel_dig_port 352 dig_port Since we already removed the intel_ prefix from most of our other structs, do the same here and prefer dig_port. v2: rename everything in i915, not just a few display sources and reword commit message (from Matt Roper) Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 143 ++++---- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- .../drm/i915/display/intel_display_debugfs.c | 12 +- .../drm/i915/display/intel_display_power.c | 4 +- .../drm/i915/display/intel_display_types.h | 40 +-- drivers/gpu/drm/i915/display/intel_dp.c | 338 +++++++++--------- drivers/gpu/drm/i915/display/intel_dp.h | 4 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 74 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.h | 6 +- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 38 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 118 +++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 252 ++++++------- drivers/gpu/drm/i915/display/intel_hdmi.h | 4 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 8 +- drivers/gpu/drm/i915/display/intel_lspcon.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +- 18 files changed, 530 insertions(+), 533 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 58c9f3d3e7ce..a7c20bbd09f7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1394,10 +1394,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *intel_dig_port = - enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - intel_dp->DP = intel_dig_port->saved_port_bits | + intel_dp->DP = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); } @@ -2072,7 +2071,7 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, static void skl_ddi_set_iboost(struct intel_encoder *encoder, int level, enum intel_output_type type) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; u8 iboost; @@ -2109,7 +2108,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, _skl_ddi_set_iboost(dev_priv, port, iboost); - if (port == PORT_A && intel_dig_port->max_lanes == 4) + if (port == PORT_A && dig_port->max_lanes == 4) _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); } @@ -3002,15 +3001,15 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } static void -icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, +icl_program_mg_dp_mode(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); - enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); u32 ln0, ln1, pin_assignment; u8 width; - if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) + if (dig_port->tc_mode == TC_PORT_TBT_ALT) return; if (INTEL_GEN(dev_priv) >= 12) { @@ -3029,13 +3028,13 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); /* DPPATC */ - pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); + pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); width = crtc_state->lane_count; switch (pin_assignment) { case 0x0: drm_WARN_ON(&dev_priv->drm, - intel_dig_port->tc_mode != TC_PORT_LEGACY); + dig_port->tc_mode != TC_PORT_LEGACY); if (width == 1) { ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; } else { @@ -3980,10 +3979,9 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = - to_i915(intel_dig_port->base.base.dev); - enum port port = intel_dig_port->base.port; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->base.port; u32 dp_tp_ctl, ddi_buf_ctl; bool wait = false; @@ -4533,42 +4531,41 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { }; static struct intel_connector * -intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) +intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); struct intel_connector *connector; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; connector = intel_connector_alloc(); if (!connector) return NULL; - intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); - intel_dig_port->dp.prepare_link_retrain = - intel_ddi_prepare_link_retrain; - intel_dig_port->dp.set_link_train = intel_ddi_set_link_train; - intel_dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; + dig_port->dp.output_reg = DDI_BUF_CTL(port); + dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; + dig_port->dp.set_link_train = intel_ddi_set_link_train; + dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; if (INTEL_GEN(dev_priv) >= 12) - intel_dig_port->dp.set_signal_levels = tgl_set_signal_levels; + dig_port->dp.set_signal_levels = tgl_set_signal_levels; else if (INTEL_GEN(dev_priv) >= 11) - intel_dig_port->dp.set_signal_levels = icl_set_signal_levels; + dig_port->dp.set_signal_levels = icl_set_signal_levels; else if (IS_CANNONLAKE(dev_priv)) - intel_dig_port->dp.set_signal_levels = cnl_set_signal_levels; + dig_port->dp.set_signal_levels = cnl_set_signal_levels; else if (IS_GEN9_LP(dev_priv)) - intel_dig_port->dp.set_signal_levels = bxt_set_signal_levels; + dig_port->dp.set_signal_levels = bxt_set_signal_levels; else - intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels; + dig_port->dp.set_signal_levels = hsw_set_signal_levels; - intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; - intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; + dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; + dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; if (INTEL_GEN(dev_priv) < 12) { - intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); - intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); + dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); + dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); } - if (!intel_dp_init_connector(intel_dig_port, connector)) { + if (!intel_dp_init_connector(dig_port, connector)) { kfree(connector); return NULL; } @@ -4767,29 +4764,29 @@ static bool bdw_digital_port_connected(struct intel_encoder *encoder) } static struct intel_connector * -intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) +intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) { struct intel_connector *connector; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; connector = intel_connector_alloc(); if (!connector) return NULL; - intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); - intel_hdmi_init_connector(intel_dig_port, connector); + dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); + intel_hdmi_init_connector(dig_port, connector); return connector; } -static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) +static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); - if (dport->base.port != PORT_A) + if (dig_port->base.port != PORT_A) return false; - if (dport->saved_port_bits & DDI_A_4_LANES) + if (dig_port->saved_port_bits & DDI_A_4_LANES) return false; /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only @@ -4811,10 +4808,10 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) } static int -intel_ddi_max_lanes(struct intel_digital_port *intel_dport) +intel_ddi_max_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); - enum port port = intel_dport->base.port; + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->base.port; int max_lanes = 4; if (INTEL_GEN(dev_priv) >= 11) @@ -4833,10 +4830,10 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) * wasn't lit up at boot. Force this bit set when needed * so we use the proper lane count for our calculations. */ - if (intel_ddi_a_force_4_lanes(intel_dport)) { + if (intel_ddi_a_force_4_lanes(dig_port)) { drm_dbg_kms(&dev_priv->drm, "Forcing DDI_A_4_LANES for port A\n"); - intel_dport->saved_port_bits |= DDI_A_4_LANES; + dig_port->saved_port_bits |= DDI_A_4_LANES; max_lanes = 4; } @@ -4845,7 +4842,7 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) { - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct intel_encoder *encoder; bool init_hdmi, init_dp, init_lspcon = false; enum phy phy = intel_port_to_phy(dev_priv, port); @@ -4874,11 +4871,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) return; } - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); - if (!intel_dig_port) + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); + if (!dig_port) return; - encoder = &intel_dig_port->base; + encoder = &dig_port->base; drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); @@ -4905,49 +4902,49 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->pipe_mask = ~0; if (INTEL_GEN(dev_priv) >= 11) - intel_dig_port->saved_port_bits = intel_de_read(dev_priv, - DDI_BUF_CTL(port)) & - DDI_BUF_PORT_REVERSAL; + dig_port->saved_port_bits = + intel_de_read(dev_priv, DDI_BUF_CTL(port)) + & DDI_BUF_PORT_REVERSAL; else - intel_dig_port->saved_port_bits = intel_de_read(dev_priv, - DDI_BUF_CTL(port)) & - (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); + dig_port->saved_port_bits = + intel_de_read(dev_priv, DDI_BUF_CTL(port)) + & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); - intel_dig_port->dp.output_reg = INVALID_MMIO_REG; - intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); + dig_port->dp.output_reg = INVALID_MMIO_REG; + dig_port->max_lanes = intel_ddi_max_lanes(dig_port); + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); if (intel_phy_is_tc(dev_priv, phy)) { bool is_legacy = !intel_bios_port_supports_typec_usb(dev_priv, port) && !intel_bios_port_supports_tbt(dev_priv, port); - intel_tc_port_init(intel_dig_port, is_legacy); + intel_tc_port_init(dig_port, is_legacy); encoder->update_prepare = intel_ddi_update_prepare; encoder->update_complete = intel_ddi_update_complete; } drm_WARN_ON(&dev_priv->drm, port > PORT_I); - intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + + dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + port - PORT_A; if (init_dp) { - if (!intel_ddi_init_dp_connector(intel_dig_port)) + if (!intel_ddi_init_dp_connector(dig_port)) goto err; - intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; + dig_port->hpd_pulse = intel_dp_hpd_pulse; } /* In theory we don't need the encoder->type check, but leave it just in * case we have some really bad VBTs... */ if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { - if (!intel_ddi_init_hdmi_connector(intel_dig_port)) + if (!intel_ddi_init_hdmi_connector(dig_port)) goto err; } if (init_lspcon) { - if (lspcon_init(intel_dig_port)) + if (lspcon_init(dig_port)) /* TODO: handle hdmi info frame part */ drm_dbg_kms(&dev_priv->drm, "LSPCON init success on port %c\n", @@ -4964,26 +4961,26 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) if (INTEL_GEN(dev_priv) >= 11) { if (intel_phy_is_tc(dev_priv, phy)) - intel_dig_port->connected = intel_tc_port_connected; + dig_port->connected = intel_tc_port_connected; else - intel_dig_port->connected = lpt_digital_port_connected; + dig_port->connected = lpt_digital_port_connected; } else if (INTEL_GEN(dev_priv) >= 8) { if (port == PORT_A || IS_GEN9_LP(dev_priv)) - intel_dig_port->connected = bdw_digital_port_connected; + dig_port->connected = bdw_digital_port_connected; else - intel_dig_port->connected = lpt_digital_port_connected; + dig_port->connected = lpt_digital_port_connected; } else { if (port == PORT_A) - intel_dig_port->connected = hsw_digital_port_connected; + dig_port->connected = hsw_digital_port_connected; else - intel_dig_port->connected = lpt_digital_port_connected; + dig_port->connected = lpt_digital_port_connected; } - intel_infoframe_init(intel_dig_port); + intel_infoframe_init(dig_port); return; err: drm_encoder_cleanup(&encoder->base); - kfree(intel_dig_port); + kfree(dig_port); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a11bb675f9b3..3b1f0b28e585 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1611,13 +1611,13 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport, + struct intel_digital_port *dig_port, unsigned int expected_mask) { u32 port_mask; i915_reg_t dpll_reg; - switch (dport->base.port) { + switch (dig_port->base.port) { case PORT_B: port_mask = DPLL_PORTB_READY_MASK; dpll_reg = DPLL(0); @@ -1639,7 +1639,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, port_mask, expected_mask, 1000)) drm_WARN(&dev_priv->drm, 1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", - dport->base.base.base.id, dport->base.base.name, + dig_port->base.base.base.id, dig_port->base.base.name, intel_de_read(dev_priv, dpll_reg) & port_mask, expected_mask); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b7a6d56bac5f..bc6021b994b1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -542,7 +542,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport, + struct intel_digital_port *dig_port, unsigned int expected_mask); int intel_get_load_detect_pipe(struct drm_connector *connector, struct intel_load_detect_pipe *old, diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d1cb48b3f462..3644752cc5ec 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1194,7 +1194,7 @@ static int i915_dp_mst_info(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_device *dev = &dev_priv->drm; struct intel_encoder *intel_encoder; - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct drm_connector *connector; struct drm_connector_list_iter conn_iter; @@ -1207,14 +1207,14 @@ static int i915_dp_mst_info(struct seq_file *m, void *unused) if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) continue; - intel_dig_port = enc_to_dig_port(intel_encoder); - if (!intel_dig_port->dp.can_mst) + dig_port = enc_to_dig_port(intel_encoder); + if (!dig_port->dp.can_mst) continue; seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); - drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); + dig_port->base.base.base.id, + dig_port->base.base.name); + drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 834162bc5a3f..ff8cba9d72f1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1817,8 +1817,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct i915_power_domains *power_domains = &dev_priv->power_domains; - enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(encoder)); - enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(encoder)); + enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); + enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); mutex_lock(&power_domains->lock); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..e8f809161c75 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -279,10 +279,10 @@ enum check_link_response { */ struct intel_hdcp_shim { /* Outputs the transmitter's An and Aksv values to the receiver. */ - int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); + int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); /* Reads the receiver's key selection vector */ - int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); + int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); /* * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The @@ -290,52 +290,52 @@ struct intel_hdcp_shim { * different. Call it BSTATUS since that's the name the HDMI spec * uses and it was there first. */ - int (*read_bstatus)(struct intel_digital_port *intel_dig_port, + int (*read_bstatus)(struct intel_digital_port *dig_port, u8 *bstatus); /* Determines whether a repeater is present downstream */ - int (*repeater_present)(struct intel_digital_port *intel_dig_port, + int (*repeater_present)(struct intel_digital_port *dig_port, bool *repeater_present); /* Reads the receiver's Ri' value */ - int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); + int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); /* Determines if the receiver's KSV FIFO is ready for consumption */ - int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, + int (*read_ksv_ready)(struct intel_digital_port *dig_port, bool *ksv_ready); /* Reads the ksv fifo for num_downstream devices */ - int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, + int (*read_ksv_fifo)(struct intel_digital_port *dig_port, int num_downstream, u8 *ksv_fifo); /* Reads a 32-bit part of V' from the receiver */ - int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, + int (*read_v_prime_part)(struct intel_digital_port *dig_port, int i, u32 *part); /* Enables HDCP signalling on the port */ - int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, + int (*toggle_signalling)(struct intel_digital_port *dig_port, bool enable); /* Ensures the link is still protected */ - bool (*check_link)(struct intel_digital_port *intel_dig_port); + bool (*check_link)(struct intel_digital_port *dig_port); /* Detects panel's hdcp capability. This is optional for HDMI. */ - int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, + int (*hdcp_capable)(struct intel_digital_port *dig_port, bool *hdcp_capable); /* HDCP adaptation(DP/HDMI) required on the port */ enum hdcp_wired_protocol protocol; /* Detects whether sink is HDCP2.2 capable */ - int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port, + int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port, bool *capable); /* Write HDCP2.2 messages */ - int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port, + int (*write_2_2_msg)(struct intel_digital_port *dig_port, void *buf, size_t size); /* Read HDCP2.2 messages */ - int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port, + int (*read_2_2_msg)(struct intel_digital_port *dig_port, u8 msg_id, void *buf, size_t size); /* @@ -343,11 +343,11 @@ struct intel_hdcp_shim { * type to Receivers. In DP HDCP2.2 Stream type is one of the input to * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. */ - int (*config_stream_type)(struct intel_digital_port *intel_dig_port, + int (*config_stream_type)(struct intel_digital_port *dig_port, bool is_repeater, u8 type); /* HDCP2.2 Link Integrity Check */ - int (*check_2_2_link)(struct intel_digital_port *intel_dig_port); + int (*check_2_2_link)(struct intel_digital_port *dig_port); }; struct intel_hdcp { @@ -1434,9 +1434,9 @@ struct intel_dp_mst_encoder { }; static inline enum dpio_channel -vlv_dport_to_channel(struct intel_digital_port *dport) +vlv_dig_port_to_channel(struct intel_digital_port *dig_port) { - switch (dport->base.port) { + switch (dig_port->base.port) { case PORT_B: case PORT_D: return DPIO_CH0; @@ -1448,9 +1448,9 @@ vlv_dport_to_channel(struct intel_digital_port *dport) } static inline enum dpio_phy -vlv_dport_to_phy(struct intel_digital_port *dport) +vlv_dig_port_to_phy(struct intel_digital_port *dig_port) { - switch (dport->base.port) { + switch (dig_port->base.port) { case PORT_B: case PORT_C: return DPIO_PHY0; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 192678bd9b42..ea6dab1f32a5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -140,9 +140,9 @@ static const u8 valid_dsc_slicecount[] = {1, 2, 4}; */ bool intel_dp_is_edp(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - return intel_dig_port->base.type == INTEL_OUTPUT_EDP; + return dig_port->base.type == INTEL_OUTPUT_EDP; } static void intel_dp_link_down(struct intel_encoder *encoder, @@ -216,10 +216,10 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp) /* Theoretical max between source and sink */ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - int source_max = intel_dig_port->max_lanes; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + int source_max = dig_port->max_lanes; int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); - int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port); + int fia_max = intel_tc_port_fia_max_lane_count(dig_port); return min3(source_max, sink_max, fia_max); } @@ -251,8 +251,8 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) static int intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct intel_encoder *encoder = &intel_dig_port->base; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int max_dotclk = dev_priv->max_dotclk_freq; int ds_max_dotclk; @@ -769,7 +769,7 @@ static void vlv_power_sequencer_kick(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe = intel_dp->pps_pipe; bool pll_enabled, release_cl_override = false; enum dpio_phy phy = DPIO_PHY(pipe); @@ -779,14 +779,14 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) if (drm_WARN(&dev_priv->drm, intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name)) + pipe_name(pipe), dig_port->base.base.base.id, + dig_port->base.base.name)) return; drm_dbg_kms(&dev_priv->drm, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + pipe_name(pipe), dig_port->base.base.base.id, + dig_port->base.base.name); /* Preserve the BIOS-computed detected bit. This is * supposed to be read-only. @@ -882,7 +882,7 @@ static enum pipe vlv_power_sequencer_pipe(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe; lockdep_assert_held(&dev_priv->pps_mutex); @@ -911,8 +911,8 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) drm_dbg_kms(&dev_priv->drm, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", pipe_name(intel_dp->pps_pipe), - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); /* init power sequencer on this pipe and port */ intel_dp_init_panel_power_sequencer(intel_dp); @@ -1000,8 +1000,8 @@ static void vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - enum port port = intel_dig_port->base.port; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum port port = dig_port->base.port; lockdep_assert_held(&dev_priv->pps_mutex); @@ -1022,15 +1022,15 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) if (intel_dp->pps_pipe == INVALID_PIPE) { drm_dbg_kms(&dev_priv->drm, "no initial power sequencer for [ENCODER:%d:%s]\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); return; } drm_dbg_kms(&dev_priv->drm, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name, + dig_port->base.base.base.id, + dig_port->base.base.name, pipe_name(intel_dp->pps_pipe)); intel_dp_init_panel_power_sequencer(intel_dp); @@ -1295,9 +1295,9 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, int send_bytes, u32 aux_clock_divider) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = - to_i915(intel_dig_port->base.base.dev); + to_i915(dig_port->base.base.dev); u32 precharge, timeout; if (IS_GEN(dev_priv, 6)) @@ -1325,10 +1325,10 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, int send_bytes, u32 unused) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *i915 = - to_i915(intel_dig_port->base.base.dev); - enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); + to_i915(dig_port->base.base.dev); + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); u32 ret; ret = DP_AUX_CH_CTL_SEND_BUSY | @@ -1342,7 +1342,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); if (intel_phy_is_tc(i915, phy) && - intel_dig_port->tc_mode == TC_PORT_TBT_ALT) + dig_port->tc_mode == TC_PORT_TBT_ALT) ret |= DP_AUX_CH_CTL_TBT_IO; return ret; @@ -1354,11 +1354,11 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, u8 *recv, int recv_size, u32 aux_send_ctl_flags) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *i915 = - to_i915(intel_dig_port->base.base.dev); + to_i915(dig_port->base.base.dev); struct intel_uncore *uncore = &i915->uncore; - enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); bool is_tc_port = intel_phy_is_tc(i915, phy); i915_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; @@ -1375,9 +1375,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); if (is_tc_port) - intel_tc_port_lock(intel_dig_port); + intel_tc_port_lock(dig_port); - aux_domain = intel_aux_power_domain(intel_dig_port); + aux_domain = intel_aux_power_domain(dig_port); aux_wakeref = intel_display_power_get(i915, aux_domain); pps_wakeref = pps_lock(intel_dp); @@ -1536,7 +1536,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, intel_display_power_put_async(i915, aux_domain, aux_wakeref); if (is_tc_port) - intel_tc_port_unlock(intel_dig_port); + intel_tc_port_unlock(dig_port); return ret; } @@ -2882,7 +2882,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp) static bool edp_panel_vdd_on(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; bool need_to_disable = !intel_dp->want_panel_vdd; @@ -2899,11 +2899,11 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) return need_to_disable; intel_display_power_get(dev_priv, - intel_aux_power_domain(intel_dig_port)); + intel_aux_power_domain(dig_port)); drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); if (!edp_have_panel_power(intel_dp)) wait_panel_power_cycle(intel_dp); @@ -2925,8 +2925,8 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) if (!edp_have_panel_power(intel_dp)) { drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] panel power wasn't enabled\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); msleep(intel_dp->panel_power_up_delay); } @@ -2959,7 +2959,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; @@ -2972,8 +2972,8 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) return; drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); pp = ilk_get_pp_control(intel_dp); pp &= ~EDP_FORCE_VDD; @@ -2993,7 +2993,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) intel_dp->panel_power_off_time = ktime_get_boottime(); intel_display_power_put_unchecked(dev_priv, - intel_aux_power_domain(intel_dig_port)); + intel_aux_power_domain(dig_port)); } static void edp_panel_vdd_work(struct work_struct *__work) @@ -3824,8 +3824,8 @@ static void g4x_pre_enable_dp(struct intel_atomic_state *state, static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum pipe pipe = intel_dp->pps_pipe; i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); @@ -3847,8 +3847,8 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) */ drm_dbg_kms(&dev_priv->drm, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + pipe_name(pipe), dig_port->base.base.base.id, + dig_port->base.base.name); intel_de_write(dev_priv, pp_on_reg, 0); intel_de_posting_read(dev_priv, pp_on_reg); @@ -4914,7 +4914,7 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct dp_sdp sdp = {}; ssize_t len; @@ -4940,14 +4940,14 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, if (drm_WARN_ON(&dev_priv->drm, len < 0)) return; - intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); + dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); } void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, struct drm_dp_vsc_sdp *vsc) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct dp_sdp sdp = {}; ssize_t len; @@ -4957,7 +4957,7 @@ void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, if (drm_WARN_ON(&dev_priv->drm, len < 0)) return; - intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, + dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, &sdp, len); } @@ -5117,7 +5117,7 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_dp_vsc_sdp *vsc) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); unsigned int type = DP_SDP_VSC; @@ -5132,7 +5132,7 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, intel_hdmi_infoframe_enable(type)) == 0) return; - intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); + dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); @@ -5144,7 +5144,7 @@ static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encod struct intel_crtc_state *crtc_state, struct hdmi_drm_infoframe *drm_infoframe) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; struct dp_sdp sdp = {}; @@ -5154,8 +5154,8 @@ static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encod intel_hdmi_infoframe_enable(type)) == 0) return; - intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, - sizeof(sdp)); + dig_port->read_infoframe(encoder, crtc_state, type, &sdp, + sizeof(sdp)); ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, sizeof(sdp)); @@ -5357,10 +5357,10 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = to_i915(dp_to_dig_port(intel_dp)->base.base.dev); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_dp_phy_test_params *data = &intel_dp->compliance.test_data.phytest; - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; u32 pattern_val; @@ -5422,10 +5422,10 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) static void intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; @@ -5448,11 +5448,11 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) static void intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - enum port port = intel_dig_port->base.port; - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); + enum port port = dig_port->base.port; + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; @@ -6319,10 +6319,10 @@ intel_dp_connector_unregister(struct drm_connector *connector) void intel_dp_encoder_flush_work(struct drm_encoder *encoder) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder)); - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); + struct intel_dp *intel_dp = &dig_port->dp; - intel_dp_mst_encoder_cleanup(intel_dig_port); + intel_dp_mst_encoder_cleanup(dig_port); if (intel_dp_is_edp(intel_dp)) { intel_wakeref_t wakeref; @@ -6381,11 +6381,11 @@ static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) } static -int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, u8 *an) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base)); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&dig_port->base.base)); static const struct drm_dp_aux_msg msg = { .request = DP_AUX_NATIVE_WRITE, .address = DP_AUX_HDCP_AKSV, @@ -6396,7 +6396,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, int ret; /* Output An first, that's easy */ - dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, + dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, an, DRM_HDCP_AN_LEN); if (dpcd_ret != DRM_HDCP_AN_LEN) { drm_dbg_kms(&i915->drm, @@ -6435,13 +6435,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, return 0; } -static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, +static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, u8 *bksv) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, DRM_HDCP_KSV_LEN); if (ret != DRM_HDCP_KSV_LEN) { drm_dbg_kms(&i915->drm, @@ -6451,10 +6451,10 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, return 0; } -static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, +static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, u8 *bstatus) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; /* @@ -6462,7 +6462,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, * definition by different names. In the HDMI spec, it's called BSTATUS, * but in DP it's called BINFO. */ - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, bstatus, DRM_HDCP_BSTATUS_LEN); if (ret != DRM_HDCP_BSTATUS_LEN) { drm_dbg_kms(&i915->drm, @@ -6473,13 +6473,13 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port, u8 *bcaps) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS, bcaps, 1); if (ret != 1) { drm_dbg_kms(&i915->drm, @@ -6491,13 +6491,13 @@ int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, bool *repeater_present) { ssize_t ret; u8 bcaps; - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); if (ret) return ret; @@ -6506,13 +6506,13 @@ int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, u8 *ri_prime) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, ri_prime, DRM_HDCP_RI_LEN); if (ret != DRM_HDCP_RI_LEN) { drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", @@ -6523,14 +6523,14 @@ int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, bool *ksv_ready) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; u8 bstatus; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, &bstatus, 1); if (ret != 1) { drm_dbg_kms(&i915->drm, @@ -6542,17 +6542,17 @@ int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, int num_downstream, u8 *ksv_fifo) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; int i; /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ for (i = 0; i < num_downstream; i += 3) { size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_KSV_FIFO, ksv_fifo + i * DRM_HDCP_KSV_LEN, len); @@ -6567,16 +6567,16 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, int i, u32 *part) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) return -EINVAL; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_V_PRIME(i), part, DRM_HDCP_V_PRIME_PART_LEN); if (ret != DRM_HDCP_V_PRIME_PART_LEN) { @@ -6588,7 +6588,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, bool enable) { /* Not used for single stream DisplayPort setups */ @@ -6596,13 +6596,13 @@ int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, } static -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; u8 bstatus; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, &bstatus, 1); if (ret != 1) { drm_dbg_kms(&i915->drm, @@ -6614,13 +6614,13 @@ bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) } static -int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_capable(struct intel_digital_port *dig_port, bool *hdcp_capable) { ssize_t ret; u8 bcaps; - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); if (ret) return ret; @@ -6678,13 +6678,13 @@ static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { }; static int -intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, +intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, u8 *rx_status) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, HDCP_2_2_DP_RXSTATUS_LEN); if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { @@ -6697,14 +6697,14 @@ intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, } static -int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, +int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, u8 msg_id, bool *msg_ready) { u8 rx_status; int ret; *msg_ready = false; - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); if (ret < 0) return ret; @@ -6730,11 +6730,11 @@ int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, } static ssize_t -intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, const struct hdcp2_dp_msg_data *hdcp2_msg_data) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *dp = &intel_dig_port->dp; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *dp = &dig_port->dp; struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; u8 msg_id = hdcp2_msg_data->msg_id; int ret, timeout; @@ -6758,7 +6758,7 @@ intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, * the timeout at wait for CP_IRQ. */ intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); - ret = hdcp2_detect_msg_availability(intel_dig_port, + ret = hdcp2_detect_msg_availability(dig_port, msg_id, &msg_ready); if (!msg_ready) ret = -ETIMEDOUT; @@ -6784,10 +6784,10 @@ static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) } static -int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, void *buf, size_t size) { - struct intel_dp *dp = &intel_dig_port->dp; + struct intel_dp *dp = &dig_port->dp; struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; unsigned int offset; u8 *byte = buf; @@ -6810,7 +6810,7 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; - ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_write(&dig_port->dp.aux, offset, (void *)byte, len); if (ret < 0) return ret; @@ -6824,13 +6824,13 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, } static -ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) +ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port) { u8 rx_info[HDCP_2_2_RXINFO_LEN]; u32 dev_cnt; ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_HDCP_2_2_REG_RXINFO_OFFSET, (void *)rx_info, HDCP_2_2_RXINFO_LEN); if (ret != HDCP_2_2_RXINFO_LEN) @@ -6850,10 +6850,10 @@ ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) } static -int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, u8 msg_id, void *buf, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); unsigned int offset; u8 *byte = buf; ssize_t ret, bytes_to_recv, len; @@ -6864,12 +6864,12 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, return -EINVAL; offset = hdcp2_msg_data->offset; - ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); + ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data); if (ret < 0) return ret; if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { - ret = get_receiver_id_list_size(intel_dig_port); + ret = get_receiver_id_list_size(dig_port); if (ret < 0) return ret; @@ -6884,7 +6884,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset, (void *)byte, len); if (ret < 0) { drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", @@ -6903,7 +6903,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port, bool is_repeater, u8 content_type) { int ret; @@ -6922,7 +6922,7 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; stream_type_msg.stream_type = content_type; - ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, + ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg, sizeof(stream_type_msg)); return ret < 0 ? ret : 0; @@ -6930,12 +6930,12 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port) { u8 rx_status; int ret; - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); if (ret) return ret; @@ -6950,14 +6950,14 @@ int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) } static -int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port, bool *capable) { u8 rx_caps[3]; int ret; *capable = false; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_HDCP_2_2_REG_RX_CAPS_OFFSET, rx_caps, HDCP_2_2_RXCAPS_LEN); if (ret != HDCP_2_2_RXCAPS_LEN) @@ -7236,12 +7236,12 @@ static bool intel_edp_have_power(struct intel_dp *intel_dp) } enum irqreturn -intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) +intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *intel_dp = &dig_port->dp; - if (intel_dig_port->base.type == INTEL_OUTPUT_EDP && + if (dig_port->base.type == INTEL_OUTPUT_EDP && (long_hpd || !intel_edp_have_power(intel_dp))) { /* * vdd off can generate a long/short pulse on eDP which @@ -7252,14 +7252,14 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) drm_dbg_kms(&i915->drm, "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", long_hpd ? "long" : "short", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); return IRQ_HANDLED; } drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name, + dig_port->base.base.base.id, + dig_port->base.base.name, long_hpd ? "long" : "short"); if (long_hpd) { @@ -8122,12 +8122,12 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work) } bool -intel_dp_init_connector(struct intel_digital_port *intel_dig_port, +intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector) { struct drm_connector *connector = &intel_connector->base; - struct intel_dp *intel_dp = &intel_dig_port->dp; - struct intel_encoder *intel_encoder = &intel_dig_port->base; + struct intel_dp *intel_dp = &dig_port->dp; + struct intel_encoder *intel_encoder = &dig_port->base; struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum port port = intel_encoder->port; @@ -8138,9 +8138,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, INIT_WORK(&intel_connector->modeset_retry_work, intel_dp_modeset_retry_work_fn); - if (drm_WARN(dev, intel_dig_port->max_lanes < 1, + if (drm_WARN(dev, dig_port->max_lanes < 1, "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, + dig_port->max_lanes, intel_encoder->base.base.id, intel_encoder->base.name)) return false; @@ -8211,12 +8211,12 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_connector->get_hw_state = intel_connector_get_hw_state; /* init MST on ports that can support it */ - intel_dp_mst_encoder_init(intel_dig_port, + intel_dp_mst_encoder_init(dig_port, intel_connector->base.base.id); if (!intel_edp_init_connector(intel_dp, intel_connector)) { intel_dp_aux_fini(intel_dp); - intel_dp_mst_encoder_cleanup(intel_dig_port); + intel_dp_mst_encoder_cleanup(dig_port); goto fail; } @@ -8251,20 +8251,20 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, enum port port) { - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; struct drm_encoder *encoder; struct intel_connector *intel_connector; - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); - if (!intel_dig_port) + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); + if (!dig_port) return false; intel_connector = intel_connector_alloc(); if (!intel_connector) goto err_connector_alloc; - intel_encoder = &intel_dig_port->base; + intel_encoder = &dig_port->base; encoder = &intel_encoder->base; if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, @@ -8300,34 +8300,34 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || (HAS_PCH_CPT(dev_priv) && port != PORT_A)) - intel_dig_port->dp.set_link_train = cpt_set_link_train; + dig_port->dp.set_link_train = cpt_set_link_train; else - intel_dig_port->dp.set_link_train = g4x_set_link_train; + dig_port->dp.set_link_train = g4x_set_link_train; if (IS_CHERRYVIEW(dev_priv)) - intel_dig_port->dp.set_signal_levels = chv_set_signal_levels; + dig_port->dp.set_signal_levels = chv_set_signal_levels; else if (IS_VALLEYVIEW(dev_priv)) - intel_dig_port->dp.set_signal_levels = vlv_set_signal_levels; + dig_port->dp.set_signal_levels = vlv_set_signal_levels; else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) - intel_dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; + dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; else if (IS_GEN(dev_priv, 6) && port == PORT_A) - intel_dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; + dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; else - intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels; + dig_port->dp.set_signal_levels = g4x_set_signal_levels; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { - intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3; - intel_dig_port->dp.voltage_max = intel_dp_voltage_max_3; + dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3; + dig_port->dp.voltage_max = intel_dp_voltage_max_3; } else { - intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2; - intel_dig_port->dp.voltage_max = intel_dp_voltage_max_2; + dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2; + dig_port->dp.voltage_max = intel_dp_voltage_max_2; } - intel_dig_port->dp.output_reg = output_reg; - intel_dig_port->max_lanes = 4; - intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); - intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); + dig_port->dp.output_reg = output_reg; + dig_port->max_lanes = 4; + dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); + dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); intel_encoder->type = INTEL_OUTPUT_DP; intel_encoder->power_domain = intel_port_to_power_domain(port); @@ -8342,25 +8342,25 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, intel_encoder->cloneable = 0; intel_encoder->port = port; - intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; + dig_port->hpd_pulse = intel_dp_hpd_pulse; if (HAS_GMCH(dev_priv)) { if (IS_GM45(dev_priv)) - intel_dig_port->connected = gm45_digital_port_connected; + dig_port->connected = gm45_digital_port_connected; else - intel_dig_port->connected = g4x_digital_port_connected; + dig_port->connected = g4x_digital_port_connected; } else { if (port == PORT_A) - intel_dig_port->connected = ilk_digital_port_connected; + dig_port->connected = ilk_digital_port_connected; else - intel_dig_port->connected = ibx_digital_port_connected; + dig_port->connected = ibx_digital_port_connected; } if (port != PORT_A) - intel_infoframe_init(intel_dig_port); + intel_infoframe_init(dig_port); - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); - if (!intel_dp_init_connector(intel_dig_port, intel_connector)) + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); + if (!intel_dp_init_connector(dig_port, intel_connector)) goto err_init_connector; return true; @@ -8370,7 +8370,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, err_encoder_init: kfree(intel_connector); err_connector_alloc: - kfree(intel_dig_port); + kfree(dig_port); return false; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..b901ab850cbd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -40,7 +40,7 @@ bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, enum pipe *pipe); bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, enum port port); -bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, +bool intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, u8 lane_count, @@ -61,7 +61,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); -enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, +enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd); void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2e6c6375a23b..f6264e6269a4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -323,8 +323,8 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); @@ -350,8 +350,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); @@ -404,7 +404,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, * the transcoder clock select is set to none. */ if (last_mst_stream) - intel_dp_set_infoframes(&intel_dig_port->base, false, + intel_dp_set_infoframes(&dig_port->base, false, old_crtc_state, NULL); /* * From TGL spec: "If multi-stream slave transcoder: Configure @@ -419,7 +419,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_mst->connector = NULL; if (last_mst_stream) - intel_dig_port->base.post_disable(state, &intel_dig_port->base, + dig_port->base.post_disable(state, &dig_port->base, old_crtc_state, NULL); drm_dbg_kms(&dev_priv->drm, "active links %d\n", @@ -432,11 +432,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; if (intel_dp->active_mst_links == 0) - intel_dig_port->base.pre_pll_enable(state, &intel_dig_port->base, + dig_port->base.pre_pll_enable(state, &dig_port->base, pipe_config, NULL); } @@ -446,8 +446,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_connector *connector = to_intel_connector(conn_state->connector); @@ -474,7 +474,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); if (first_mst_stream) - intel_dig_port->base.pre_enable(state, &intel_dig_port->base, + dig_port->base.pre_enable(state, &dig_port->base, pipe_config, NULL); ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, @@ -492,7 +492,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, /* * Before Gen 12 this is not done as part of - * intel_dig_port->base.pre_enable() and should be done here. For + * dig_port->base.pre_enable() and should be done here. For * Gen 12+ the step in which this should be done is different for the * first MST stream, so it's done on the DDI for the first stream and * here for the following ones. @@ -511,8 +511,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); @@ -552,9 +552,9 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; + struct intel_digital_port *dig_port = intel_mst->primary; - intel_ddi_get_config(&intel_dig_port->base, pipe_config); + intel_ddi_get_config(&dig_port->base, pipe_config); } static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) @@ -712,8 +712,8 @@ static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) { struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_connector *intel_connector; struct drm_connector *connector; @@ -788,11 +788,11 @@ static const struct drm_dp_mst_topology_cbs mst_cbs = { }; static struct intel_dp_mst_encoder * -intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) +intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) { struct intel_dp_mst_encoder *intel_mst; struct intel_encoder *intel_encoder; - struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_device *dev = dig_port->base.base.dev; intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); @@ -801,14 +801,14 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum intel_mst->pipe = pipe; intel_encoder = &intel_mst->base; - intel_mst->primary = intel_dig_port; + intel_mst->primary = dig_port; drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); intel_encoder->type = INTEL_OUTPUT_DP_MST; - intel_encoder->power_domain = intel_dig_port->base.power_domain; - intel_encoder->port = intel_dig_port->base.port; + intel_encoder->power_domain = dig_port->base.power_domain; + intel_encoder->port = dig_port->base.port; intel_encoder->cloneable = 0; /* * This is wrong, but broken userspace uses the intersection @@ -835,29 +835,29 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum } static bool -intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) +intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) { - struct intel_dp *intel_dp = &intel_dig_port->dp; - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct intel_dp *intel_dp = &dig_port->dp; + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum pipe pipe; for_each_pipe(dev_priv, pipe) - intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(intel_dig_port, pipe); + intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); return true; } int -intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port) +intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) { - return intel_dig_port->dp.active_mst_links; + return dig_port->dp.active_mst_links; } int -intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) +intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *intel_dp = &intel_dig_port->dp; - enum port port = intel_dig_port->base.port; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *intel_dp = &dig_port->dp; + enum port port = dig_port->base.port; int ret; if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) @@ -872,7 +872,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_ba intel_dp->mst_mgr.cbs = &mst_cbs; /* create encoders */ - intel_dp_create_fake_mst_encoders(intel_dig_port); + intel_dp_create_fake_mst_encoders(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, conn_base_id); if (ret) @@ -884,9 +884,9 @@ intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_ba } void -intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) +intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) { - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_dp *intel_dp = &dig_port->dp; if (!intel_dp->can_mst) return; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h index 854724f68f09..6afda4e86b3c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h @@ -11,9 +11,9 @@ struct intel_digital_port; struct intel_crtc_state; -int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); -void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); -int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port); +int intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_id); +void intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port); +int intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port); bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state); bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 399a7edb4568..7910522273b2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -650,9 +650,9 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, bool uniq_trans_scale) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - enum dpio_channel ch = vlv_dport_to_channel(dport); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum pipe pipe = intel_crtc->pipe; u32 val; int i; @@ -746,7 +746,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, bool reset) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(encoder)); + enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; u32 val; @@ -789,10 +789,10 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, void chv_phy_pre_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel ch = vlv_dport_to_channel(dport); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; unsigned int lane_mask = intel_dp_unused_lane_mask(crtc_state->lane_count); @@ -803,7 +803,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, * Otherwise we can't even access the PLL. */ if (ch == DPIO_CH0 && pipe == PIPE_B) - dport->release_cl2_override = + dig_port->release_cl2_override = !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); chv_phy_powergate_lanes(encoder, true, lane_mask); @@ -870,10 +870,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel ch = vlv_dport_to_channel(dport); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; int data, i, stagger; u32 val; @@ -948,12 +948,12 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, void chv_phy_release_cl2_override(struct intel_encoder *encoder) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - if (dport->release_cl2_override) { + if (dig_port->release_cl2_override) { chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); - dport->release_cl2_override = false; + dig_port->release_cl2_override = false; } } @@ -997,8 +997,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - struct intel_digital_port *dport = enc_to_dig_port(encoder); - enum dpio_channel port = vlv_dport_to_channel(dport); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = intel_crtc->pipe; vlv_dpio_get(dev_priv); @@ -1022,10 +1022,10 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dport_to_channel(dport); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; /* Program Tx lane resets to default */ @@ -1052,10 +1052,10 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dport_to_channel(dport); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; u32 val; @@ -1081,10 +1081,10 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, void vlv_phy_reset_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dport_to_channel(dport); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; vlv_dpio_get(dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 815b054bb167..1b6dadfce4eb 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -40,15 +40,15 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv) } static -int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, +int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, const struct intel_hdcp_shim *shim, u8 *bksv) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret, i, tries = 2; /* HDCP spec states that we must retry the bksv if it is invalid */ for (i = 0; i < tries; i++) { - ret = shim->read_bksv(intel_dig_port, bksv); + ret = shim->read_bksv(dig_port, bksv); if (ret) return ret; if (intel_hdcp_is_ksv_valid(bksv)) @@ -65,7 +65,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, /* Is HDCP1.4 capable on Platform and Sink */ bool intel_hdcp_capable(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); const struct intel_hdcp_shim *shim = connector->hdcp.shim; bool capable = false; u8 bksv[5]; @@ -74,9 +74,9 @@ bool intel_hdcp_capable(struct intel_connector *connector) return capable; if (shim->hdcp_capable) { - shim->hdcp_capable(intel_dig_port, &capable); + shim->hdcp_capable(dig_port, &capable); } else { - if (!intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv)) + if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) capable = true; } @@ -86,7 +86,7 @@ bool intel_hdcp_capable(struct intel_connector *connector) /* Is HDCP2.2 capable on Platform and Sink */ bool intel_hdcp2_capable(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; bool capable = false; @@ -104,7 +104,7 @@ bool intel_hdcp2_capable(struct intel_connector *connector) mutex_unlock(&dev_priv->hdcp_comp_mutex); /* Sink's capability for HDCP2.2 */ - hdcp->shim->hdcp_2_2_capable(intel_dig_port, &capable); + hdcp->shim->hdcp_2_2_capable(dig_port, &capable); return capable; } @@ -125,14 +125,14 @@ static bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv, LINK_ENCRYPTION_STATUS; } -static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port, +static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, const struct intel_hdcp_shim *shim) { int ret, read_ret; bool ksv_ready; /* Poll for ksv list ready (spec says max time allowed is 5s) */ - ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port, + ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready), read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 100 * 1000); @@ -300,16 +300,16 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, const struct intel_hdcp_shim *shim, u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; u32 vprime, sha_text, sha_leftovers, rep_ctl; int ret, i, j, sha_idx; /* Process V' values from the receiver */ for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { - ret = shim->read_v_prime_part(intel_dig_port, i, &vprime); + ret = shim->read_v_prime_part(dig_port, i, &vprime); if (ret) return ret; intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime); @@ -528,20 +528,20 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, static int intel_hdcp_auth_downstream(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); const struct intel_hdcp_shim *shim = connector->hdcp.shim; u8 bstatus[2], num_downstream, *ksv_fifo; int ret, i, tries = 3; - ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim); + ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); if (ret) { drm_dbg_kms(&dev_priv->drm, "KSV list failed to become ready (%d)\n", ret); return ret; } - ret = shim->read_bstatus(intel_dig_port, bstatus); + ret = shim->read_bstatus(dig_port, bstatus); if (ret) return ret; @@ -571,7 +571,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) return -ENOMEM; } - ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo); + ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); if (ret) goto err; @@ -611,12 +611,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) /* Implements Part 1 of the HDCP authorization procedure */ static int intel_hdcp_auth(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; const struct intel_hdcp_shim *shim = hdcp->shim; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; unsigned long r0_prime_gen_start; int ret, i, tries = 2; union { @@ -640,7 +640,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) * displays, this is not necessary. */ if (shim->hdcp_capable) { - ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable); + ret = shim->hdcp_capable(dig_port, &hdcp_capable); if (ret) return ret; if (!hdcp_capable) { @@ -670,7 +670,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) HDCP_ANLO(dev_priv, cpu_transcoder, port)); an.reg[1] = intel_de_read(dev_priv, HDCP_ANHI(dev_priv, cpu_transcoder, port)); - ret = shim->write_an_aksv(intel_dig_port, an.shim); + ret = shim->write_an_aksv(dig_port, an.shim); if (ret) return ret; @@ -678,7 +678,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) memset(&bksv, 0, sizeof(bksv)); - ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim); + ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); if (ret < 0) return ret; @@ -692,14 +692,14 @@ static int intel_hdcp_auth(struct intel_connector *connector) intel_de_write(dev_priv, HDCP_BKSVHI(dev_priv, cpu_transcoder, port), bksv.reg[1]); - ret = shim->repeater_present(intel_dig_port, &repeater_present); + ret = shim->repeater_present(dig_port, &repeater_present); if (ret) return ret; if (repeater_present) intel_de_write(dev_priv, HDCP_REP_CTL, intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port)); - ret = shim->toggle_signalling(intel_dig_port, true); + ret = shim->toggle_signalling(dig_port, true); if (ret) return ret; @@ -732,7 +732,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) */ for (i = 0; i < tries; i++) { ri.reg = 0; - ret = shim->read_ri_prime(intel_dig_port, ri.shim); + ret = shim->read_ri_prime(dig_port, ri.shim); if (ret) return ret; intel_de_write(dev_priv, @@ -776,10 +776,10 @@ static int intel_hdcp_auth(struct intel_connector *connector) static int _intel_hdcp_disable(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; @@ -796,7 +796,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) return -ETIMEDOUT; } - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); + ret = hdcp->shim->toggle_signalling(dig_port, false); if (ret) { drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n"); return ret; @@ -859,10 +859,10 @@ static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) /* Implements Part 3 of the HDCP authorization procedure */ static int intel_hdcp_check_link(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder; int ret = 0; @@ -888,7 +888,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; } - if (hdcp->shim->check_link(intel_dig_port)) { + if (hdcp->shim->check_link(dig_port)) { if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; schedule_work(&hdcp->prop_work); @@ -1242,7 +1242,7 @@ static int hdcp2_deauthenticate_port(struct intel_connector *connector) /* Authentication flow starts from here */ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; union { @@ -1264,12 +1264,12 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) if (ret < 0) return ret; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.ake_init, + ret = shim->write_2_2_msg(dig_port, &msgs.ake_init, sizeof(msgs.ake_init)); if (ret < 0) return ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_CERT, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_CERT, &msgs.send_cert, sizeof(msgs.send_cert)); if (ret < 0) return ret; @@ -1298,11 +1298,11 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) if (ret < 0) return ret; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.no_stored_km, size); + ret = shim->write_2_2_msg(dig_port, &msgs.no_stored_km, size); if (ret < 0) return ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_HPRIME, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_HPRIME, &msgs.send_hprime, sizeof(msgs.send_hprime)); if (ret < 0) return ret; @@ -1313,7 +1313,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) if (!hdcp->is_paired) { /* Pairing is required */ - ret = shim->read_2_2_msg(intel_dig_port, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_PAIRING_INFO, &msgs.pairing_info, sizeof(msgs.pairing_info)); @@ -1331,7 +1331,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) static int hdcp2_locality_check(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; union { struct hdcp2_lc_init lc_init; @@ -1345,12 +1345,12 @@ static int hdcp2_locality_check(struct intel_connector *connector) if (ret < 0) continue; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.lc_init, + ret = shim->write_2_2_msg(dig_port, &msgs.lc_init, sizeof(msgs.lc_init)); if (ret < 0) continue; - ret = shim->read_2_2_msg(intel_dig_port, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_LC_SEND_LPRIME, &msgs.send_lprime, sizeof(msgs.send_lprime)); @@ -1367,7 +1367,7 @@ static int hdcp2_locality_check(struct intel_connector *connector) static int hdcp2_session_key_exchange(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; struct hdcp2_ske_send_eks send_eks; int ret; @@ -1376,7 +1376,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) if (ret < 0) return ret; - ret = hdcp->shim->write_2_2_msg(intel_dig_port, &send_eks, + ret = hdcp->shim->write_2_2_msg(dig_port, &send_eks, sizeof(send_eks)); if (ret < 0) return ret; @@ -1387,7 +1387,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) static int hdcp2_propagate_stream_management_info(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; union { @@ -1409,12 +1409,12 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector) msgs.stream_manage.streams[0].stream_type = hdcp->content_type; /* Send it to Repeater */ - ret = shim->write_2_2_msg(intel_dig_port, &msgs.stream_manage, + ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage, sizeof(msgs.stream_manage)); if (ret < 0) return ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_STREAM_READY, &msgs.stream_ready, sizeof(msgs.stream_ready)); if (ret < 0) return ret; @@ -1439,7 +1439,7 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector) static int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; union { @@ -1451,7 +1451,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) u8 *rx_info; int ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, &msgs.recvid_list, sizeof(msgs.recvid_list)); if (ret < 0) return ret; @@ -1496,7 +1496,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) return ret; hdcp->seq_num_v = seq_num_v; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.rep_ack, + ret = shim->write_2_2_msg(dig_port, &msgs.rep_ack, sizeof(msgs.rep_ack)); if (ret < 0) return ret; @@ -1517,7 +1517,7 @@ static int hdcp2_authenticate_repeater(struct intel_connector *connector) static int hdcp2_authenticate_sink(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; const struct intel_hdcp_shim *shim = hdcp->shim; @@ -1543,7 +1543,7 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) } if (shim->config_stream_type) { - ret = shim->config_stream_type(intel_dig_port, + ret = shim->config_stream_type(dig_port, hdcp->is_repeater, hdcp->content_type); if (ret < 0) @@ -1569,10 +1569,10 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) static int hdcp2_enable_encryption(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; @@ -1580,7 +1580,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & LINK_ENCRYPTION_STATUS); if (hdcp->shim->toggle_signalling) { - ret = hdcp->shim->toggle_signalling(intel_dig_port, true); + ret = hdcp->shim->toggle_signalling(dig_port, true); if (ret) { drm_err(&dev_priv->drm, "Failed to enable HDCP signalling. %d\n", @@ -1608,10 +1608,10 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) static int hdcp2_disable_encryption(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; @@ -1630,7 +1630,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout"); if (hdcp->shim->toggle_signalling) { - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); + ret = hdcp->shim->toggle_signalling(dig_port, false); if (ret) { drm_err(&dev_priv->drm, "Failed to disable HDCP signalling. %d\n", @@ -1723,10 +1723,10 @@ static int _intel_hdcp2_disable(struct intel_connector *connector) /* Implements the Link Integrity Check for HDCP2.2 */ static int intel_hdcp2_check_link(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder; int ret = 0; @@ -1751,7 +1751,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) goto out; } - ret = hdcp->shim->check_2_2_link(intel_dig_port); + ret = hdcp->shim->check_2_2_link(dig_port); if (ret == HDCP_LINK_PROTECTED) { if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a31a98d26882..414a0de2aab3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -88,10 +88,10 @@ assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) { - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = container_of(&encoder->base, struct intel_digital_port, base.base); - return &intel_dig_port->hdmi; + return &dig_port->hdmi; } static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) @@ -660,7 +660,7 @@ static void intel_write_infoframe(struct intel_encoder *encoder, enum hdmi_infoframe_type type, const union hdmi_infoframe *frame) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u8 buffer[VIDEO_DIP_DATA_SIZE]; ssize_t len; @@ -681,7 +681,7 @@ static void intel_write_infoframe(struct intel_encoder *encoder, buffer[3] = 0; len++; - intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); + dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); } void intel_read_infoframe(struct intel_encoder *encoder, @@ -689,7 +689,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, enum hdmi_infoframe_type type, union hdmi_infoframe *frame) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u8 buffer[VIDEO_DIP_DATA_SIZE]; int ret; @@ -697,7 +697,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, intel_hdmi_infoframe_enable(type)) == 0) return; - intel_dig_port->read_infoframe(encoder, crtc_state, + dig_port->read_infoframe(encoder, crtc_state, type, buffer, sizeof(buffer)); /* Fill the 'hole' (see big comment above) at position 3 */ @@ -872,8 +872,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; i915_reg_t reg = VIDEO_DIP_CTL; u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1057,8 +1057,8 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1275,11 +1275,11 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) adapter, enable); } -static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, +static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, unsigned int offset, void *buffer, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; @@ -1304,11 +1304,11 @@ static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, return ret >= 0 ? -EIO : ret; } -static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, +static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, unsigned int offset, void *buffer, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; @@ -1338,16 +1338,16 @@ static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, u8 *an) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; - ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, + ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, DRM_HDCP_AN_LEN); if (ret) { drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", @@ -1363,13 +1363,13 @@ int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, return 0; } -static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, +static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, u8 *bksv) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, DRM_HDCP_KSV_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", @@ -1378,13 +1378,13 @@ static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, u8 *bstatus) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, bstatus, DRM_HDCP_BSTATUS_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", @@ -1393,14 +1393,14 @@ int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, bool *repeater_present) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; u8 val; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); if (ret) { drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", ret); @@ -1411,13 +1411,13 @@ int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, u8 *ri_prime) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, ri_prime, DRM_HDCP_RI_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", @@ -1426,14 +1426,14 @@ int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, bool *ksv_ready) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; u8 val; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); if (ret) { drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", ret); @@ -1444,12 +1444,12 @@ int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, int num_downstream, u8 *ksv_fifo) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); if (ret) { drm_dbg_kms(&i915->drm, @@ -1460,16 +1460,16 @@ int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, int i, u32 *part) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) return -EINVAL; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), part, DRM_HDCP_V_PRIME_PART_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", @@ -1480,7 +1480,7 @@ int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_crtc *crtc = connector->base.state->crtc; struct intel_crtc *intel_crtc = container_of(crtc, struct intel_crtc, base); @@ -1494,13 +1494,13 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) usleep_range(25, 50); } - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, false); if (ret) { drm_err(&dev_priv->drm, "Disable HDCP signalling failed (%d)\n", ret); return ret; } - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, true); if (ret) { drm_err(&dev_priv->drm, "Enable HDCP signalling failed (%d)\n", ret); @@ -1511,10 +1511,10 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) } static -int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, bool enable) { - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct intel_hdmi *hdmi = &dig_port->hdmi; struct intel_connector *connector = hdmi->attached_connector; struct drm_i915_private *dev_priv = to_i915(connector->base.dev); int ret; @@ -1522,7 +1522,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, if (!enable) usleep_range(6, 60); /* Bspec says >= 6us */ - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, enable); if (ret) { drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", enable ? "Enable" : "Disable", ret); @@ -1540,12 +1540,12 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, } static -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); struct intel_connector *connector = - intel_dig_port->hdmi.attached_connector; - enum port port = intel_dig_port->base.port; + dig_port->hdmi.attached_connector; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; int ret; union { @@ -1553,7 +1553,7 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) u8 shim[DRM_HDCP_RI_LEN]; } ri; - ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); + ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); if (ret) return false; @@ -1586,10 +1586,10 @@ static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { }; static -int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, u8 *rx_status) { - return intel_hdmi_hdcp_read(intel_dig_port, + return intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, rx_status, HDCP_2_2_HDMI_RXSTATUS_LEN); @@ -1615,15 +1615,15 @@ static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) } static int -hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, +hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, u8 msg_id, bool *msg_ready, ssize_t *msg_sz) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; int ret; - ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); + ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); if (ret < 0) { drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", ret); @@ -1643,10 +1643,10 @@ hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, } static ssize_t -intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, +intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, u8 msg_id, bool paired) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); bool msg_ready = false; int timeout, ret; ssize_t msg_sz = 0; @@ -1655,7 +1655,7 @@ intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, if (timeout < 0) return timeout; - ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, + ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, msg_id, &msg_ready, &msg_sz), !ret && msg_ready && msg_sz, timeout * 1000, @@ -1668,26 +1668,26 @@ intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, void *buf, size_t size) { unsigned int offset; offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; - return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); + return intel_hdmi_hdcp_write(dig_port, offset, buf, size); } static -int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, u8 msg_id, void *buf, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; unsigned int offset; ssize_t ret; - ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, + ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, hdcp->is_paired); if (ret < 0) return ret; @@ -1704,7 +1704,7 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, } offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; - ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); + ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); if (ret) drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", msg_id, ret); @@ -1713,12 +1713,12 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port) { u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; int ret; - ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); + ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); if (ret) return ret; @@ -1735,14 +1735,14 @@ int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) } static -int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, bool *capable) { u8 hdcp2_version; int ret; *capable = false; - ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, + ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, &hdcp2_version, sizeof(hdcp2_version)); if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) *capable = true; @@ -2050,7 +2050,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = hdmi_to_dig_port(intel_hdmi); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); u32 temp; @@ -2094,7 +2094,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } - intel_dig_port->set_infoframes(encoder, + dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); @@ -2709,12 +2709,12 @@ static void intel_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_hdmi_prepare(encoder, pipe_config); - intel_dig_port->set_infoframes(encoder, + dig_port->set_infoframes(encoder, pipe_config->has_infoframe, pipe_config, conn_state); } @@ -2724,7 +2724,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); vlv_phy_pre_encoder_enable(encoder, pipe_config); @@ -2733,13 +2733,13 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 0x2b247878); - dport->set_infoframes(encoder, + dig_port->set_infoframes(encoder, pipe_config->has_infoframe, pipe_config, conn_state); g4x_enable_hdmi(state, encoder, pipe_config, conn_state); - vlv_wait_port_ready(dev_priv, dport, 0x0); + vlv_wait_port_ready(dev_priv, dig_port, 0x0); } static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, @@ -2800,7 +2800,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -2810,13 +2810,13 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, /* Use 800mV-0dB */ chv_set_phy_signal_level(encoder, 128, 102, false); - dport->set_infoframes(encoder, + dig_port->set_infoframes(encoder, pipe_config->has_infoframe, pipe_config, conn_state); g4x_enable_hdmi(state, encoder, pipe_config, conn_state); - vlv_wait_port_ready(dev_priv, dport, 0x0); + vlv_wait_port_ready(dev_priv, dig_port, 0x0); /* Second common lane will stay alive on its own now */ chv_phy_release_cl2_override(encoder); @@ -2910,7 +2910,7 @@ static void intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->dev); - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = hdmi_to_dig_port(intel_hdmi); intel_attach_force_audio_property(connector); @@ -2922,7 +2922,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c * ToDo: This needs to be extended for LSPCON implementation * as well. Will be implemented separately. */ - if (!intel_dig_port->lspcon.active) + if (!dig_port->lspcon.active) intel_attach_colorspace_property(connector); drm_connector_attach_content_type_property(connector); @@ -3159,52 +3159,52 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) return ddc_pin; } -void intel_infoframe_init(struct intel_digital_port *intel_dig_port) +void intel_infoframe_init(struct intel_digital_port *dig_port) { struct drm_i915_private *dev_priv = - to_i915(intel_dig_port->base.base.dev); + to_i915(dig_port->base.base.dev); if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - intel_dig_port->write_infoframe = vlv_write_infoframe; - intel_dig_port->read_infoframe = vlv_read_infoframe; - intel_dig_port->set_infoframes = vlv_set_infoframes; - intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; + dig_port->write_infoframe = vlv_write_infoframe; + dig_port->read_infoframe = vlv_read_infoframe; + dig_port->set_infoframes = vlv_set_infoframes; + dig_port->infoframes_enabled = vlv_infoframes_enabled; } else if (IS_G4X(dev_priv)) { - intel_dig_port->write_infoframe = g4x_write_infoframe; - intel_dig_port->read_infoframe = g4x_read_infoframe; - intel_dig_port->set_infoframes = g4x_set_infoframes; - intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; + dig_port->write_infoframe = g4x_write_infoframe; + dig_port->read_infoframe = g4x_read_infoframe; + dig_port->set_infoframes = g4x_set_infoframes; + dig_port->infoframes_enabled = g4x_infoframes_enabled; } else if (HAS_DDI(dev_priv)) { - if (intel_dig_port->lspcon.active) { - intel_dig_port->write_infoframe = lspcon_write_infoframe; - intel_dig_port->read_infoframe = lspcon_read_infoframe; - intel_dig_port->set_infoframes = lspcon_set_infoframes; - intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; + if (dig_port->lspcon.active) { + dig_port->write_infoframe = lspcon_write_infoframe; + dig_port->read_infoframe = lspcon_read_infoframe; + dig_port->set_infoframes = lspcon_set_infoframes; + dig_port->infoframes_enabled = lspcon_infoframes_enabled; } else { - intel_dig_port->write_infoframe = hsw_write_infoframe; - intel_dig_port->read_infoframe = hsw_read_infoframe; - intel_dig_port->set_infoframes = hsw_set_infoframes; - intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; + dig_port->write_infoframe = hsw_write_infoframe; + dig_port->read_infoframe = hsw_read_infoframe; + dig_port->set_infoframes = hsw_set_infoframes; + dig_port->infoframes_enabled = hsw_infoframes_enabled; } } else if (HAS_PCH_IBX(dev_priv)) { - intel_dig_port->write_infoframe = ibx_write_infoframe; - intel_dig_port->read_infoframe = ibx_read_infoframe; - intel_dig_port->set_infoframes = ibx_set_infoframes; - intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; + dig_port->write_infoframe = ibx_write_infoframe; + dig_port->read_infoframe = ibx_read_infoframe; + dig_port->set_infoframes = ibx_set_infoframes; + dig_port->infoframes_enabled = ibx_infoframes_enabled; } else { - intel_dig_port->write_infoframe = cpt_write_infoframe; - intel_dig_port->read_infoframe = cpt_read_infoframe; - intel_dig_port->set_infoframes = cpt_set_infoframes; - intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; + dig_port->write_infoframe = cpt_write_infoframe; + dig_port->read_infoframe = cpt_read_infoframe; + dig_port->set_infoframes = cpt_set_infoframes; + dig_port->infoframes_enabled = cpt_infoframes_enabled; } } -void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, +void intel_hdmi_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector) { struct drm_connector *connector = &intel_connector->base; - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; - struct intel_encoder *intel_encoder = &intel_dig_port->base; + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; + struct intel_encoder *intel_encoder = &dig_port->base; struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct i2c_adapter *ddc; @@ -3218,9 +3218,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) return; - if (drm_WARN(dev, intel_dig_port->max_lanes < 4, + if (drm_WARN(dev, dig_port->max_lanes < 4, "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, + dig_port->max_lanes, intel_encoder->base.base.id, intel_encoder->base.name)) return; @@ -3309,21 +3309,21 @@ intel_hdmi_hotplug(struct intel_encoder *encoder, void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, enum port port) { - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; struct intel_connector *intel_connector; - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); - if (!intel_dig_port) + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); + if (!dig_port) return; intel_connector = intel_connector_alloc(); if (!intel_connector) { - kfree(intel_dig_port); + kfree(dig_port); return; } - intel_encoder = &intel_dig_port->base; + intel_encoder = &dig_port->base; drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, @@ -3380,12 +3380,12 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, if (IS_G4X(dev_priv)) intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; - intel_dig_port->hdmi.hdmi_reg = hdmi_reg; - intel_dig_port->dp.output_reg = INVALID_MMIO_REG; - intel_dig_port->max_lanes = 4; + dig_port->hdmi.hdmi_reg = hdmi_reg; + dig_port->dp.output_reg = INVALID_MMIO_REG; + dig_port->max_lanes = 4; - intel_infoframe_init(intel_dig_port); + intel_infoframe_init(dig_port); - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); - intel_hdmi_init_connector(intel_dig_port, intel_connector); + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); + intel_hdmi_init_connector(dig_port, intel_connector); } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 8ff1f76a63df..213ff24befde 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -25,7 +25,7 @@ enum port; void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, enum port port); -void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, +void intel_hdmi_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder); int intel_hdmi_compute_config(struct intel_encoder *encoder, @@ -36,7 +36,7 @@ bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, bool high_tmds_clock_ratio, bool scrambling); void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); -void intel_infoframe_init(struct intel_digital_port *intel_dig_port); +void intel_infoframe_init(struct intel_digital_port *dig_port); u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); u32 intel_hdmi_infoframe_enable(unsigned int type); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 6ff7b226f0a1..b781bf469644 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -550,11 +550,11 @@ void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); } -bool lspcon_init(struct intel_digital_port *intel_dig_port) +bool lspcon_init(struct intel_digital_port *dig_port) { - struct intel_dp *dp = &intel_dig_port->dp; - struct intel_lspcon *lspcon = &intel_dig_port->lspcon; - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_dp *dp = &dig_port->dp; + struct intel_lspcon *lspcon = &dig_port->lspcon; + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct drm_connector *connector = &dp->attached_connector->base; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 37cfddf8a9c5..1cffe8a42a08 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -15,7 +15,7 @@ struct intel_digital_port; struct intel_encoder; struct intel_lspcon; -bool lspcon_init(struct intel_digital_port *intel_dig_port); +bool lspcon_init(struct intel_digital_port *dig_port); void lspcon_resume(struct intel_lspcon *lspcon); void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); void lspcon_write_infoframe(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 86bf7a76f93d..78762627a8ba 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -905,8 +905,8 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, const struct drm_connector_state *conn_state) { struct intel_dp *intel_dp = dev_priv->psr.dp; - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct intel_encoder *encoder = &intel_dig_port->base; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; u32 val; drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index d145fe2bed81..c5735c365659 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1045,7 +1045,7 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; @@ -1055,9 +1055,9 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); - intel_dig_port->write_infoframe(encoder, crtc_state, - DP_SDP_PPS, &dp_dsc_pps_sdp, - sizeof(dp_dsc_pps_sdp)); + dig_port->write_infoframe(encoder, crtc_state, + DP_SDP_PPS, &dp_dsc_pps_sdp, + sizeof(dp_dsc_pps_sdp)); } void intel_dsc_enable(struct intel_encoder *encoder, -- 2.26.2 From lucas.de.marchi at gmail.com Mon Jun 22 23:50:01 2020 From: lucas.de.marchi at gmail.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 16:50:01 -0700 Subject: [Intel-gfx] [PATCH 4/9] drm/i915/display: start description-based ddi initialization In-Reply-To: <CAKi4VAKOSLS-mKFgEsBHjw66ZoTXjWdZucgsK3Ogc+OkbPKZ3w@mail.gmail.com> References: <20191223195850.25997-1-lucas.demarchi@intel.com> <20191223195850.25997-5-lucas.demarchi@intel.com> <87tv5glstg.fsf@intel.com> <CAKi4VAKOSLS-mKFgEsBHjw66ZoTXjWdZucgsK3Ogc+OkbPKZ3w@mail.gmail.com> Message-ID: <CAKi4VAKnYNTisygz-8EW3Yw6xy5n1rpHjox=AqB077TUG-1jwQ@mail.gmail.com> On Wed, Jan 1, 2020 at 11:19 PM Lucas De Marchi <lucas.de.marchi at gmail.com> wrote: > > On Tue, Dec 31, 2019 at 1:58 AM Jani Nikula <jani.nikula at linux.intel.com> wrote: > > > > On Mon, 23 Dec 2019, Lucas De Marchi <lucas.demarchi at intel.com> wrote: > > > For the latest platforms we can share the logic to initialize the the > > > ddi, so start moving the most trivial ones to a new setup_outputs_desc() > > > function that will be responsible for initialization according to a > > > static const table. > > > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 96 +++++++++++++------ > > > .../drm/i915/display/intel_display_types.h | 4 + > > > 2 files changed, 73 insertions(+), 27 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index 04819b0bd494..b3fb1e03cb0b 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -16221,6 +16221,72 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) > > > intel_pps_unlock_regs_wa(dev_priv); > > > } > > > > > > +struct intel_output { > > > + /* Initialize DSI if present */ > > > + void (*dsi_init)(struct drm_i915_private *i915); > > > > We'll need to be able to initialize DSI on multiple ports too. I've > > already drafted a series to do so, maybe I've even sent it to the > > list. Basically you'd pass the port to icl_dsi_init() too. > > > > I don't want that development to get any more complicated than it > > already is. Did you make progress on that series? Anywhere for me to look at? I'd like to respin this series. Lucas De Marchi > > Right now this is just working with what is there. I don't see a problem > to update this series with the additional port argument, but let's > keep the series > independent from each other. > > Lucas De Marchi > > > > > BR, > > Jani. > > > > > > > + struct intel_ddi_port_info ddi_ports[]; > > > +}; > > > + > > > +static const struct intel_output tgl_output = { > > > + .dsi_init = icl_dsi_init, > > > + .ddi_ports = { > > > + { .port = PORT_A }, > > > + { .port = PORT_B }, > > > + { .port = PORT_D }, > > > + { .port = PORT_E }, > > > + { .port = PORT_F }, > > > + { .port = PORT_G }, > > > + { .port = PORT_H }, > > > + { .port = PORT_I }, > > > + { .port = PORT_NONE } > > > + } > > > +}; > > > + > > > +static const struct intel_output ehl_output = { > > > + .dsi_init = icl_dsi_init, > > > + .ddi_ports = { > > > + { .port = PORT_A }, > > > + { .port = PORT_B }, > > > + { .port = PORT_C }, > > > + { .port = PORT_D }, > > > + { .port = PORT_NONE } > > > + } > > > +}; > > > + > > > +static const struct intel_output gen9lp_output = { > > > + .dsi_init = vlv_dsi_init, > > > + .ddi_ports = { > > > + { .port = PORT_A }, > > > + { .port = PORT_B }, > > > + { .port = PORT_C }, > > > + { .port = PORT_NONE } > > > + }, > > > +}; > > > + > > > +/* > > > + * Use a description-based approach for platforms that can be supported with a > > > + * static table > > > + */ > > > +static void setup_ddi_outputs_desc(struct drm_i915_private *i915) > > > +{ > > > + const struct intel_output *output; > > > + const struct intel_ddi_port_info *port_info; > > > + > > > + if (INTEL_GEN(i915) >= 12) > > > + output = &tgl_output; > > > + else if (IS_ELKHARTLAKE(i915)) > > > + output = &ehl_output; > > > + else if (IS_GEN9_LP(i915)) > > > + output = &gen9lp_output; > > > + > > > + for (port_info = output->ddi_ports; > > > + port_info->port != PORT_NONE; port_info++) > > > + intel_ddi_init(i915, port_info->port); > > > + > > > + if (output->dsi_init) > > > + output->dsi_init(i915); > > > +} > > > + > > > static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > > { > > > struct intel_encoder *encoder; > > > @@ -16231,22 +16297,9 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > > if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) > > > return; > > > > > > - if (INTEL_GEN(dev_priv) >= 12) { > > > - intel_ddi_init(dev_priv, PORT_A); > > > - intel_ddi_init(dev_priv, PORT_B); > > > - intel_ddi_init(dev_priv, PORT_D); > > > - intel_ddi_init(dev_priv, PORT_E); > > > - intel_ddi_init(dev_priv, PORT_F); > > > - intel_ddi_init(dev_priv, PORT_G); > > > - intel_ddi_init(dev_priv, PORT_H); > > > - intel_ddi_init(dev_priv, PORT_I); > > > - icl_dsi_init(dev_priv); > > > - } else if (IS_ELKHARTLAKE(dev_priv)) { > > > - intel_ddi_init(dev_priv, PORT_A); > > > - intel_ddi_init(dev_priv, PORT_B); > > > - intel_ddi_init(dev_priv, PORT_C); > > > - intel_ddi_init(dev_priv, PORT_D); > > > - icl_dsi_init(dev_priv); > > > + if (INTEL_GEN(dev_priv) >= 12 || IS_ELKHARTLAKE(dev_priv) || > > > + IS_GEN9_LP(dev_priv)) { > > > + setup_ddi_outputs_desc(dev_priv); > > > } else if (IS_GEN(dev_priv, 11)) { > > > intel_ddi_init(dev_priv, PORT_A); > > > intel_ddi_init(dev_priv, PORT_B); > > > @@ -16263,17 +16316,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > > intel_ddi_init(dev_priv, PORT_F); > > > > > > icl_dsi_init(dev_priv); > > > - } else if (IS_GEN9_LP(dev_priv)) { > > > - /* > > > - * FIXME: Broxton doesn't support port detection via the > > > - * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to > > > - * detect the ports. > > > - */ > > > - intel_ddi_init(dev_priv, PORT_A); > > > - intel_ddi_init(dev_priv, PORT_B); > > > - intel_ddi_init(dev_priv, PORT_C); > > > - > > > - vlv_dsi_init(dev_priv); > > > } else if (HAS_DDI(dev_priv)) { > > > int found; > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > > > index a3a067dacf84..4d2f4ee35812 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -1376,6 +1376,10 @@ struct intel_dp_mst_encoder { > > > struct intel_connector *connector; > > > }; > > > > > > +struct intel_ddi_port_info { > > > + enum port port; > > > +}; > > > + > > > static inline enum dpio_channel > > > vlv_dig_port_to_channel(struct intel_digital_port *dig_port) > > > { > > > > -- > > Jani Nikula, Intel Open Source Graphics Center > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Lucas De Marchi -- Lucas De Marchi From patchwork at emeril.freedesktop.org Mon Jun 22 23:57:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 22 Jun 2020 23:57:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgVmFy?= =?utf-8?q?iable_renames?= In-Reply-To: <20200622232821.3093-1-lucas.demarchi@intel.com> References: <20200622232821.3093-1-lucas.demarchi@intel.com> Message-ID: <159287026648.9209.13328530318068015923@emeril.freedesktop.org> == Series Details == Series: Variable renames URL : https://patchwork.freedesktop.org/series/78714/ State : success == Summary == CI Bug Log - changes from CI_DRM_8653 -> Patchwork_18006 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/index.html Known issues ------------ Here are the changes found in Patchwork_18006 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [DMESG-FAIL][7] ([i915#62] / [i915#95]) -> [SKIP][8] ([fdo#109271]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8653 -> Patchwork_18006 CI-20190529: 20190529 CI_DRM_8653: dce458f7b00797dbc291296aacfab37075db7fee @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18006: 1f292211d1e31fa07247acb455b42921d629ad26 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1f292211d1e3 drm/i915/display: prefer dig_port to reference intel_digital_port f2a72269ce89 drm/i915/display: remove alias to dig_port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/index.html From lucas.demarchi at intel.com Tue Jun 23 01:11:46 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 18:11:46 -0700 Subject: [Intel-gfx] [PATCH 9/9] drm/i915/display: use port_info on intel_ddi_init In-Reply-To: <87d0c4lp1b.fsf@intel.com> References: <20191223195850.25997-1-lucas.demarchi@intel.com> <20191223195850.25997-10-lucas.demarchi@intel.com> <20191224001624.GX2877816@mdroper-desk1.amr.corp.intel.com> <87d0c4lp1b.fsf@intel.com> Message-ID: <20200623011146.2nq66p6oa7revqiu@ldmartin-desk1> On Tue, Dec 31, 2019 at 01:20:32PM +0200, Jani Nikula wrote: >On Mon, 23 Dec 2019, Matt Roper <matthew.d.roper at intel.com> wrote: >> On Mon, Dec 23, 2019 at 11:58:50AM -0800, Lucas De Marchi wrote: >>> Now that we have tables for all platforms using ddi, keep the port_info >>> around so we can use it for decisions like "what phy does it have?" >>> instead of keep checking the platform/gen everywhere. >>> >>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> >>> --- >>> drivers/gpu/drm/i915/display/intel_ddi.c | 36 ++++++++++++------- >>> drivers/gpu/drm/i915/display/intel_ddi.h | 8 ++++- >>> drivers/gpu/drm/i915/display/intel_display.c | 2 +- >>> .../drm/i915/display/intel_display_types.h | 3 ++ >>> 4 files changed, 35 insertions(+), 14 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >>> index a1b7075ea6be..9d06a34f5f8e 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >>> @@ -4782,14 +4782,25 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port) >>> return max_lanes; >>> } >>> >>> -void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) >>> +bool __pure intel_ddi_has_tc_phy(const struct intel_digital_port *dig_port) >>> { >>> + return dig_port->port_info->phy_type == PHY_TYPE_TC; >>> +} >>> + >>> +bool __pure intel_ddi_has_combo_phy(const struct intel_digital_port *dig_port) >>> +{ >>> + return dig_port->port_info->phy_type == PHY_TYPE_COMBO; >>> +} >>> + >>> +void intel_ddi_init(struct drm_i915_private *dev_priv, >>> + const struct intel_ddi_port_info *port_info) >>> +{ >>> + enum port port = port_info->port; >>> struct ddi_vbt_port_info *vbt_port_info = >>> &dev_priv->vbt.ddi_port_info[port]; >>> struct intel_digital_port *intel_dig_port; >>> struct intel_encoder *encoder; >>> bool init_hdmi, init_dp, init_lspcon = false; >>> - enum phy phy = intel_port_to_phy(dev_priv, port); >>> >>> init_hdmi = vbt_port_info->supports_dvi || vbt_port_info->supports_hdmi; >>> init_dp = vbt_port_info->supports_dp; >>> @@ -4803,12 +4814,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) >>> init_dp = true; >>> init_lspcon = true; >>> init_hdmi = false; >>> - DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); >>> + DRM_DEBUG_KMS("VBT says port %s has lspcon\n", port_info->name); >>> } >>> >>> if (!init_dp && !init_hdmi) { >>> - DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", >>> - port_name(port)); >>> + DRM_DEBUG_KMS("VBT says %s is not DVI/HDMI/DP compatible, respect it\n", >>> + port_info->name); >>> return; >>> } >>> >>> @@ -4819,7 +4830,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) >>> encoder = &intel_dig_port->base; >>> >>> drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, >>> - DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); >>> + DRM_MODE_ENCODER_TMDS, port_info->name); >>> >>> encoder->hotplug = intel_ddi_hotplug; >>> encoder->compute_output_type = intel_ddi_compute_output_type; >>> @@ -4837,7 +4848,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) >>> >>> encoder->type = INTEL_OUTPUT_DDI; >>> encoder->power_domain = intel_port_to_power_domain(port); >>> - encoder->port = port; >>> + encoder->port = port_info->port; >> >> In theory, shouldn't we be able to drop encoder->port completely once >> we've converted everything over to the proper ddi/phy/vbt namespace? >> >> Overall I like the direction this series is going. The continued use of >> 'port' terminology, both in the driver and in the hardware specs has >> become increasingly confusing as things get chopped up and indexed >> differently. I think this will help clarify exactly what a platform is >> expecting and force people to think about which namespace is correct for >> the part of the hardware they're working with. > >Indeed, this part I like. > >I am less certain whether we need to change output setup to be driven by >the new port_info. Seems like we could keep the existing output setup >(with its wrinkles) while converting port towards a struct consisting of >port, phy and phy type. And make the latter table driven instead of the >current intel_port_to_*() and intel_phy_is_*(). I think that's good >stuff. I have to put the table somewhere. I prefer it localized on intel_display then globally on device info because nobody really should be looking at that table except the init function. This prevents hacks to sprinkle over the driver. >But I don't like all the wrinkles with port F and DSI and straps etc. in >the output setup changes in this series. And we'll still *also* depend >on VBT here. I am not sure if the output setup should in fact be driven >by the VBT instead of the ports (yeah, *gasp*!). I think those are orthogonal things. On a quick look, for port F the thing that can be done is to move it to intel_bios.c as you suggested and then get rid of the "is_port_present()" hook. That would allow us to easily use the "generic approach" for gen9lp and gen11+. As I'm reworking on this stuff, I'd leave the previous platforms alone so we don't have to make it more complex. For dsi, it's not clear to me what to do. I could add a intel_dsi_init(), but that would be just an indirection over the platform-specific functions. I'm happy to rebase this series on whatever you provide for dsi. Lucas De Marchi > >I guess the issue with output setup would be if there are collisions in >ports with different phys. Though that would require VBT parsing changes >for DDI too, as that currently ignores such cases (and we have that in >CHV DSI). > > >BR, >Jani. > >> >> >> Matt >> >>> encoder->cloneable = 0; >>> encoder->pipe_mask = ~0; >>> >>> @@ -4851,8 +4862,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) >>> intel_dig_port->dp.output_reg = INVALID_MMIO_REG; >>> intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); >>> intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); >>> + intel_dig_port->port_info = port_info; >>> >>> - if (intel_phy_is_tc(dev_priv, phy)) { >>> + if (intel_ddi_has_tc_phy(intel_dig_port)) { >>> bool is_legacy = !vbt_port_info->supports_typec_usb && >>> !vbt_port_info->supports_tbt; >>> >>> @@ -4883,15 +4895,15 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) >>> if (init_lspcon) { >>> if (lspcon_init(intel_dig_port)) >>> /* TODO: handle hdmi info frame part */ >>> - DRM_DEBUG_KMS("LSPCON init success on port %c\n", >>> - port_name(port)); >>> + DRM_DEBUG_KMS("LSPCON init success on port %s\n", >>> + port_info->name); >>> else >>> /* >>> * LSPCON init faied, but DP init was success, so >>> * lets try to drive as DP++ port. >>> */ >>> - DRM_ERROR("LSPCON init failed on port %c\n", >>> - port_name(port)); >>> + DRM_ERROR("LSPCON init failed on port %s\n", >>> + port_info->name); >>> } >>> >>> intel_infoframe_init(intel_dig_port); >>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h >>> index 167c6579d972..c500d473963e 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_ddi.h >>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h >>> @@ -15,6 +15,7 @@ struct drm_i915_private; >>> struct intel_connector; >>> struct intel_crtc; >>> struct intel_crtc_state; >>> +struct intel_ddi_port_info; >>> struct intel_dp; >>> struct intel_dpll_hw_state; >>> struct intel_encoder; >>> @@ -24,7 +25,8 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, >>> const struct drm_connector_state *old_conn_state); >>> void hsw_fdi_link_train(struct intel_encoder *encoder, >>> const struct intel_crtc_state *crtc_state); >>> -void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); >>> +void intel_ddi_init(struct drm_i915_private *dev_priv, >>> + const struct intel_ddi_port_info *port_info); >>> bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); >>> void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state); >>> void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); >>> @@ -50,4 +52,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); >>> int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, >>> struct intel_dpll_hw_state *state); >>> >>> + >>> +bool __pure intel_ddi_has_tc_phy(const struct intel_digital_port *dig_port); >>> +bool __pure intel_ddi_has_combo_phy(const struct intel_digital_port *dig_port); >>> + >>> #endif /* __INTEL_DDI_H__ */ >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >>> index 219f180fa395..96207dc83fac 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_display.c >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c >>> @@ -16363,7 +16363,7 @@ static void setup_ddi_outputs(struct drm_i915_private *i915) >>> !output->is_port_present(i915, port_info)) >>> continue; >>> >>> - intel_ddi_init(i915, port_info->port); >>> + intel_ddi_init(i915, port_info); >>> } >>> >>> if (output->dsi_init) >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h >>> index 23a885895803..c54b0178e885 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h >>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h >>> @@ -1346,6 +1346,9 @@ struct intel_digital_port { >>> enum intel_display_power_domain ddi_io_power_domain; >>> struct mutex tc_lock; /* protects the TypeC port mode */ >>> intel_wakeref_t tc_lock_wakeref; >>> + >>> + const struct intel_ddi_port_info *port_info; >>> + >>> int tc_link_refcount; >>> bool tc_legacy_port:1; >>> char tc_port_name[8]; >>> -- >>> 2.24.0 >>> > >-- >Jani Nikula, Intel Open Source Graphics Center >_______________________________________________ >Intel-gfx mailing list >Intel-gfx at lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx From sfr at canb.auug.org.au Tue Jun 23 01:35:36 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Tue, 23 Jun 2020 11:35:36 +1000 Subject: [Intel-gfx] linux-next: manual merge of the drm-intel tree with Linus' tree Message-ID: <20200623113536.427ba57a@canb.auug.org.au> Hi all, Today's linux-next merge of the drm-intel tree got a conflict in: drivers/gpu/drm/i915/i915_drv.h between commit: 7fb81e9d8073 ("drm/i915: Use drmm_add_final_kfree") from Linus' tree and commit: 8a25c4be583d ("drm/i915/params: switch to device specific parameters") from the drm-intel tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell diff --cc drivers/gpu/drm/i915/i915_drv.h index adb9bf34cf97,2697960f15a9..000000000000 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@@ -826,9 -827,9 +827,12 @@@ struct i915_selftest_stash struct drm_i915_private { struct drm_device drm; + /* i915 device parameters */ + struct i915_params params; + + /* FIXME: Device release actions should all be moved to drmm_ */ + bool do_release; + const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ struct intel_driver_caps caps; -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200623/67079b1b/attachment.sig> From patchwork at emeril.freedesktop.org Tue Jun 23 01:55:18 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 01:55:18 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgVmFy?= =?utf-8?q?iable_renames?= In-Reply-To: <20200622232821.3093-1-lucas.demarchi@intel.com> References: <20200622232821.3093-1-lucas.demarchi@intel.com> Message-ID: <159287731868.27517.11594316268357785781@emeril.freedesktop.org> == Series Details == Series: Variable renames URL : https://patchwork.freedesktop.org/series/78714/ State : success == Summary == CI Bug Log - changes from CI_DRM_8653_full -> Patchwork_18006_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18006_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_balancer@hang: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#1635] / [i915#95]) +15 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl8/igt at gem_exec_balancer@hang.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl7/igt at gem_exec_balancer@hang.html * igt at gem_exec_whisper@basic-contexts: - shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk5/igt at gem_exec_whisper@basic-contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk4/igt at gem_exec_whisper@basic-contexts.html * igt at i915_pm_rpm@system-suspend-execbuf: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#151] / [i915#69]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl4/igt at i915_pm_rpm@system-suspend-execbuf.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl1/igt at i915_pm_rpm@system-suspend-execbuf.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk2/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_big_fb@x-tiled-8bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk7/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk5/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html * igt at kms_color@pipe-b-ctm-0-25: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#58] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk7/igt at kms_color@pipe-b-ctm-0-25.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk5/igt at kms_color@pipe-b-ctm-0-25.html * igt at kms_flip@2x-flip-vs-wf_vblank at ac-hdmi-a1-hdmi-a2: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#1928]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk7/igt at kms_flip@2x-flip-vs-wf_vblank at ac-hdmi-a1-hdmi-a2.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk5/igt at kms_flip@2x-flip-vs-wf_vblank at ac-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +6 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl7/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary: - shard-iclb: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-iclb4/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-iclb1/igt at kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl3/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#93] / [i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl1/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl7/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt at kms_plane_cursor@pipe-b-viewport-size-128: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +14 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl5/igt at kms_plane_cursor@pipe-b-viewport-size-128.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl3/igt at kms_plane_cursor@pipe-b-viewport-size-128.html * igt at kms_plane_lowres@pipe-a-tiling-none: - shard-glk: [PASS][25] -> [FAIL][26] ([i915#899]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk7/igt at kms_plane_lowres@pipe-a-tiling-none.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk5/igt at kms_plane_lowres@pipe-a-tiling-none.html * igt at kms_setmode@basic: - shard-kbl: [PASS][27] -> [FAIL][28] ([i915#31]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl1/igt at kms_setmode@basic.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl3/igt at kms_setmode@basic.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-tglb6/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-tglb8/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at prime_busy@after-wait at bcs0: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#402]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-tglb1/igt at prime_busy@after-wait at bcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-tglb3/igt at prime_busy@after-wait at bcs0.html #### Possible fixes #### * igt at gem_ctx_shared@q-smoketest-all: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk6/igt at gem_ctx_shared@q-smoketest-all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk8/igt at gem_ctx_shared@q-smoketest-all.html * igt at gem_eio@in-flight-suspend: - shard-apl: [CRASH][35] -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl2/igt at gem_eio@in-flight-suspend.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl6/igt at gem_eio@in-flight-suspend.html * igt at gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][37] ([i915#1436] / [i915#716]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl4/igt at gen9_exec_parse@allowed-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl1/igt at gen9_exec_parse@allowed-all.html * igt at i915_pm_backlight@fade_with_suspend: - shard-skl: [INCOMPLETE][39] ([i915#69]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl5/igt at i915_pm_backlight@fade_with_suspend.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl8/igt at i915_pm_backlight@fade_with_suspend.html * igt at kms_big_fb@x-tiled-8bpp-rotate-180: - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl8/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html * igt at kms_ccs@pipe-a-crc-sprite-planes-basic: - shard-kbl: [DMESG-WARN][43] ([i915#93] / [i915#95]) -> [PASS][44] +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl7/igt at kms_ccs@pipe-a-crc-sprite-planes-basic.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl6/igt at kms_ccs@pipe-a-crc-sprite-planes-basic.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +3 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl4/igt at kms_color@pipe-a-ctm-0-5.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl1/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_legacy@cursor-vs-flip-toggle: - shard-hsw: [INCOMPLETE][47] -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-hsw6/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-hsw1/igt at kms_cursor_legacy@cursor-vs-flip-toggle.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-iclb: [INCOMPLETE][49] ([i915#1185]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-iclb3/igt at kms_fbcon_fbt@fbc-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-iclb3/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_flip@2x-flip-vs-suspend-interruptible at ab-hdmi-a1-hdmi-a2: - shard-glk: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk5/igt at kms_flip@2x-flip-vs-suspend-interruptible at ab-hdmi-a1-hdmi-a2.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk7/igt at kms_flip@2x-flip-vs-suspend-interruptible at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][53] ([i915#1928]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-glk5/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-glk4/igt at kms_flip@2x-plain-flip-ts-check-interruptible at bc-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-expired-vblank at b-dp1: - shard-apl: [FAIL][55] ([i915#79]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl2/igt at kms_flip@flip-vs-expired-vblank at b-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl6/igt at kms_flip@flip-vs-expired-vblank at b-dp1.html * igt at kms_flip@flip-vs-suspend-interruptible at b-edp1: - shard-skl: [INCOMPLETE][57] ([i915#198]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl6/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl7/igt at kms_flip@flip-vs-suspend-interruptible at b-edp1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][59] ([i915#180]) -> [PASS][60] +5 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc: - shard-apl: [DMESG-WARN][61] ([i915#1635] / [i915#95]) -> [PASS][62] +10 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl8/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl7/igt at kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-tglb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-tglb1/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][65] ([i915#1188]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-kbl: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl1/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html #### Warnings #### * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [DMESG-WARN][71] ([i915#93] / [i915#95]) -> [DMESG-WARN][72] ([i915#180] / [i915#93] / [i915#95]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl3/igt at gem_workarounds@suspend-resume-fd.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl1/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][73] ([i915#454]) -> [SKIP][74] ([i915#468]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-tglb8/igt at i915_pm_dc@dc6-psr.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_chamelium@hdmi-hpd-storm-disable: - shard-apl: [SKIP][75] ([fdo#109271] / [fdo#111827]) -> [SKIP][76] ([fdo#109271] / [fdo#111827] / [i915#1635]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl3/igt at kms_chamelium@hdmi-hpd-storm-disable.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl4/igt at kms_chamelium@hdmi-hpd-storm-disable.html * igt at kms_chamelium@vga-hpd: - shard-apl: [SKIP][77] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][78] ([fdo#109271] / [fdo#111827]) +3 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl6/igt at kms_chamelium@vga-hpd.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl3/igt at kms_chamelium@vga-hpd.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding: - shard-kbl: [DMESG-WARN][79] ([i915#93] / [i915#95]) -> [DMESG-FAIL][80] ([i915#54] / [i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-apl: [SKIP][81] ([fdo#109271] / [i915#1635]) -> [SKIP][82] ([fdo#109271]) +5 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - shard-apl: [DMESG-FAIL][83] ([i915#1635] / [i915#95]) -> [DMESG-WARN][84] ([i915#1635] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl1/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl4/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-tglb: [INCOMPLETE][85] ([i915#1602] / [i915#402] / [i915#456]) -> [INCOMPLETE][86] ([i915#1602] / [i915#456]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-tglb7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-tglb2/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at prime_nv_pcopy@test3_2: - shard-apl: [SKIP][87] ([fdo#109271]) -> [SKIP][88] ([fdo#109271] / [i915#1635]) +6 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8653/shard-apl2/igt at prime_nv_pcopy@test3_2.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/shard-apl4/igt at prime_nv_pcopy@test3_2.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8653 -> Patchwork_18006 CI-20190529: 20190529 CI_DRM_8653: dce458f7b00797dbc291296aacfab37075db7fee @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18006: 1f292211d1e31fa07247acb455b42921d629ad26 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18006/index.html From zhenyuw at linux.intel.com Tue Jun 23 03:07:11 2020 From: zhenyuw at linux.intel.com (Zhenyu Wang) Date: Tue, 23 Jun 2020 11:07:11 +0800 Subject: [Intel-gfx] [PULL] gvt-fixes In-Reply-To: <159248448107.8757.1901135788098329902@jlahtine-desk.ger.corp.intel.com> References: <20200617043418.GQ5687@zhen-hp.sh.intel.com> <159248448107.8757.1901135788098329902@jlahtine-desk.ger.corp.intel.com> Message-ID: <20200623030711.GA5687@zhen-hp.sh.intel.com> On 2020.06.18 15:48:01 +0300, Joonas Lahtinen wrote: > Quoting Zhenyu Wang (2020-06-17 07:34:18) > > > > Hi, > > > > This contains misc fixes for gvt. Two MMIO handler fixes on SKL/CFL, > > one mask register bit checking fix exposed in suspend/resume path and > > one lockdep error fix for debugfs entry access. > > Could not pull this one due to the extra hassle with CI this week. > > Jani, can you please pull this next week. > Got it. Please help to pull then. One thing I forgot to mention that change in "drm/i915/gvt: Fix incorrect check of enabled bits in mask registers" would cause a minor conflict if backmerging from linux master to dinq, which is because of new IS_COMETLAKE. Change like below could resolve that. diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 9f48db0bf9d5..78ba2857144e 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1734,14 +1734,9 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, return 0; } -<<<<<<< HEAD if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || IS_COMETLAKE(vgpu->gvt->gt->i915)) && - data & _MASKED_BIT_ENABLE(2)) { -======= - if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && IS_MASKED_BITS_ENABLED(data, 2)) { ->>>>>>> origin/gvt-next-fixes enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); return 0; } > > > Thanks. > > -- > > The following changes since commit 8e68c6340d5833077b3753eabedab40755571383: > > > > drm/i915/display: Fix the encoder type check (2020-06-16 11:34:24 +0300) > > > > are available in the Git repository at: > > > > https://github.com/intel/gvt-linux tags/gvt-fixes-2020-06-17 > > > > for you to fetch changes up to a291e4fba259a56a6a274c1989997acb6f0bb03a: > > > > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context (2020-06-17 12:36:19 +0800) > > > > ---------------------------------------------------------------- > > gvt-fixes-2020-06-17 > > > > - Two missed MMIO handler fixes for SKL/CFL (Colin) > > - Fix mask register bits check (Colin) > > - Fix one lockdep error for debugfs entry access (Colin) > > > > ---------------------------------------------------------------- > > Colin Xu (4): > > drm/i915/gvt: Add one missing MMIO handler for D_SKL_PLUS > > drm/i915/gvt: Fix two CFL MMIO handling caused by regression. > > drm/i915/gvt: Fix incorrect check of enabled bits in mask registers > > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context > > > > drivers/gpu/drm/i915/gvt/debugfs.c | 2 +- > > drivers/gpu/drm/i915/gvt/handlers.c | 24 +++++++++++++----------- > > drivers/gpu/drm/i915/gvt/mmio_context.h | 6 +++--- > > drivers/gpu/drm/i915/gvt/reg.h | 5 +++++ > > 4 files changed, 22 insertions(+), 15 deletions(-) > _______________________________________________ > intel-gvt-dev mailing list > intel-gvt-dev at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 195 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200623/6911e7a5/attachment-0001.sig> From patchwork at emeril.freedesktop.org Tue Jun 23 03:27:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 03:27:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBn?= =?utf-8?q?vt-fixes?= In-Reply-To: <20200617043418.GQ5687@zhen-hp.sh.intel.com> References: <20200617043418.GQ5687@zhen-hp.sh.intel.com> Message-ID: <159288286069.27517.2443588616121037693@emeril.freedesktop.org> == Series Details == Series: gvt-fixes URL : https://patchwork.freedesktop.org/series/78717/ State : failure == Summary == Applying: gvt-fixes error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gvt/handlers.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 gvt-fixes When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From shaofeng.tang at intel.com Tue Jun 23 03:46:55 2020 From: shaofeng.tang at intel.com (Tang, Shaofeng) Date: Tue, 23 Jun 2020 03:46:55 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <20200622082319.GZ5687@zhen-hp.sh.intel.com> References: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> <159233324036.19488.6385709597388673560@build.alporthouse.com> <20200622082319.GZ5687@zhen-hp.sh.intel.com> Message-ID: <SN6PR11MB255859A6CB9B6BB51C1FB578E2940@SN6PR11MB2558.namprd11.prod.outlook.com> Hi Zhenyu and Chris, Yes, I agree with you. It must be better if only the workable planes/overlays are returned from KMS. but currently, KMS still return all planes. and User did not know if it is a virtual GPU or a native GPU. Do you know if there is a plan to fix or implement it? or any roadmap for sharing. If KMS does not work in this way, we have to customized our image for this issue. 2 possible solutions, first, provide 2 customized image, 1 for VM, and 1 for Native or bare-metal. and hard-code to only use 1 plane in the VM image. Second, only provide 1 image, and hard-code to only use 1 plane for both VM and native. None of them looks good to us. We don't hope to hardcode the plane usage in user-space either, so this API is really helpful before KMS work as expected. As you mentioned there is a potentially good reason to let the user know if it is a virtual GPU or not. it is not a hardcoding api limits. I suppose it is a ability to support developer for optimizing the performance on VM Including choose an appropriate renderer for better performance on VM. BR, Shaofeng -----Original Message----- From: Zhenyu Wang <zhenyuw at linux.intel.com> Sent: Monday, June 22, 2020 4:23 PM To: Chris Wilson <chris at chris-wilson.co.uk> Cc: Tang, Shaofeng <shaofeng.tang at intel.com>; intel-gfx at lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL On 2020.06.16 19:47:20 +0100, Chris Wilson wrote: > Quoting Shaofeng Tang (2020-06-16 09:29:20) > > [Why] > > Query if vgpu is active, it is useful to the user. > > Currently, only the primary plane is usable when vgpu is active. > > The value of vgpu active is useful for user to determine how many > > planes can be used. also useful for user to determine different > > behaviors according to vgpu is active or not. > > The number of planes must be queried via kms, and all such kernel > capabilities should be declared via the appropriate interface. > > I am not saying that there is not potentially good reason to let the > user to know it's a virtual gpu, but hardcoding api limits in the > client based on the parameter is a bad idea. Yeah, as I replied for internal before, guest shouldn't detect via this kind of interface, which also doesn't reflect any gvt host capability change. For any current gap, let's fix gvt or vgpu handling instead. Thanks. From zhenyuw at linux.intel.com Tue Jun 23 03:44:42 2020 From: zhenyuw at linux.intel.com (Zhenyu Wang) Date: Tue, 23 Jun 2020 11:44:42 +0800 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <SN6PR11MB255859A6CB9B6BB51C1FB578E2940@SN6PR11MB2558.namprd11.prod.outlook.com> References: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> <159233324036.19488.6385709597388673560@build.alporthouse.com> <20200622082319.GZ5687@zhen-hp.sh.intel.com> <SN6PR11MB255859A6CB9B6BB51C1FB578E2940@SN6PR11MB2558.namprd11.prod.outlook.com> Message-ID: <20200623034442.GB5687@zhen-hp.sh.intel.com> On 2020.06.23 03:46:55 +0000, Tang, Shaofeng wrote: > Hi Zhenyu and Chris, > > Yes, I agree with you. > It must be better if only the workable planes/overlays are returned from KMS. > but currently, KMS still return all planes. and User did not know if it is a virtual GPU > or a native GPU. Do you know if there is a plan to fix or implement it? or any roadmap for sharing. We should expose this info via PV to let guest expose correct config from KMS. I've asked Zhiyuan to add todo for the fix. Better include you to be clear on the issue and requirement. > If KMS does not work in this way, we have to customized our image for this issue. > 2 possible solutions, > first, provide 2 customized image, 1 for VM, and 1 for Native or bare-metal. > and hard-code to only use 1 plane in the VM image. > Second, only provide 1 image, and hard-code to only use 1 plane for both VM and native. > None of them looks good to us. > We don't hope to hardcode the plane usage in user-space either, so this API is really helpful before KMS work as expected. > > As you mentioned there is a potentially good reason to let the user > know if it is a virtual GPU or not. it is not a hardcoding api limits. > I suppose it is a ability to support developer for optimizing the performance on VM > Including choose an appropriate renderer for better performance on VM. > But simply expose virtual GPU flag doesn't give you reliable indicator for performance e.g it doesn't tell you what's rendering is preferred. Or either you do some runtime profiling or try to detect either it's passthrough or mediated device e.g from gpu resource size, etc. That's your guest application's choice. > BR, Shaofeng > > -----Original Message----- > From: Zhenyu Wang <zhenyuw at linux.intel.com> > Sent: Monday, June 22, 2020 4:23 PM > To: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Tang, Shaofeng <shaofeng.tang at intel.com>; intel-gfx at lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL > > On 2020.06.16 19:47:20 +0100, Chris Wilson wrote: > > Quoting Shaofeng Tang (2020-06-16 09:29:20) > > > [Why] > > > Query if vgpu is active, it is useful to the user. > > > Currently, only the primary plane is usable when vgpu is active. > > > The value of vgpu active is useful for user to determine how many > > > planes can be used. also useful for user to determine different > > > behaviors according to vgpu is active or not. > > > > The number of planes must be queried via kms, and all such kernel > > capabilities should be declared via the appropriate interface. > > > > I am not saying that there is not potentially good reason to let the > > user to know it's a virtual gpu, but hardcoding api limits in the > > client based on the parameter is a bad idea. > > Yeah, as I replied for internal before, guest shouldn't detect via this kind of interface, which also doesn't reflect any gvt host capability change. For any current gap, let's fix gvt or vgpu handling instead. > > Thanks. -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 195 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200623/38936ba3/attachment.sig> From airlied at gmail.com Tue Jun 23 04:54:18 2020 From: airlied at gmail.com (Dave Airlie) Date: Tue, 23 Jun 2020 14:54:18 +1000 Subject: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions In-Reply-To: <87zh8vo25k.fsf@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-8-lucas.demarchi@intel.com> <CAKMK7uEBq6-MNL1EsZtT4d07tfq7bXCGXQNX9XnorCg2NuiS5g@mail.gmail.com> <87zh8vo25k.fsf@intel.com> Message-ID: <CAPM=9twOo_5+q-tR9tYqENst59uea-Tf0jmQ4RS4miY_H_bCfg@mail.gmail.com> On Mon, 22 Jun 2020 at 19:55, Jani Nikula <jani.nikula at linux.intel.com> wrote: > > On Mon, 22 Jun 2020, Daniel Vetter <daniel at ffwll.ch> wrote: > > On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote: > >> From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> > >> > >> Bspec: 33617, 33617 > >> > >> Cc: Jos? Roberto de Souza <jose.souza at intel.com> > >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > >> Cc: Stuart Summers <stuart.summers at intel.com> > >> Cc: Vanshidhar Konda <vanshidhar.r.konda at intel.com> > >> Cc: Lucas De Marchi <lucas.demarchi at intel.com> > >> Cc: Aravind Iddamsetty <aravind.iddamsetty at intel.com> > >> Cc: Matt Roper <matthew.d.roper at intel.com> > >> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> > >> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > >> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > >> --- > >> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ > >> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++ > >> drivers/gpu/drm/i915/intel_device_info.c | 1 + > >> drivers/gpu/drm/i915/intel_device_info.h | 1 + > >> 4 files changed, 21 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >> index 2f8057a0b2280..f79c09257eb6b 100644 > >> --- a/drivers/gpu/drm/i915/i915_drv.h > >> +++ b/drivers/gpu/drm/i915/i915_drv.h > >> @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > >> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) > >> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) > >> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) > >> +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) > >> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ > >> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) > >> #define IS_BDW_ULT(dev_priv) \ > >> @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > >> #define IS_RKL_REVID(p, since, until) \ > >> (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) > >> > >> +#define DG1_REVID_A0 0x0 > >> +#define DG1_REVID_B0 0x1 > >> + > >> +#define IS_DG1_REVID(p, since, until) \ > >> + (IS_DG1(p) && IS_REVID(p, since, until)) > >> + > >> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > >> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) > >> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > >> index e5fdf17cd9cdd..58cceeaa0ffa5 100644 > >> --- a/drivers/gpu/drm/i915/i915_pci.c > >> +++ b/drivers/gpu/drm/i915/i915_pci.c > >> @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = { > >> > >> #define GEN12_DGFX_FEATURES \ > >> GEN12_FEATURES, \ > >> + .memory_regions = REGION_SMEM | REGION_LMEM, \ > > > > This has lmem, and we need a new uapi for that. Last year we discussed a > > plan to have that behind a very scary compile-time only option, to make > > absolutely sure no one will start relying on this broken state before we > > aligned everything. And we know the current status is wrong since this > > patch series doesn't include any of the lmem specific uapi that's being > > worked on. > > > > But now almost a year passed, so that original plan needs to be > > renegotiated. Personally I'm not sure the scary compile option makes > > sense any longer, we're way later, users will soon have real hw, and once > > they have that they will find ways to enable it and we're potentially > > screwed. Discussed this also with Joonas last week or so in private, and > > he shares similar concerns. > > > > So I think best option here (since keeping patches out of tree is rarely > > best option) would be to merge just the display enabling for DG1, but also > > making sure that we have all the rendering support completely disabled. > > This would mean: > > - wedge gpu on startup, just to make sure > > - drm_driver->num_ioctls = 0 (plus ioctls = NULL) > > - no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure > > display-only driver > > > > Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts? > > I'll defer the decision on lmem to folks who actually know this stuff, > and focus on display. And from that perspective, I'd like to unblock > merging the display patches. > How does display work without LMEM, I'm assuming you have to scan out from VRAM on DG1, even if we only have internal non-uapi is this enough to bring up fbcon? Dave. From ayaz.siddiqui at intel.com Tue Jun 23 04:59:56 2020 From: ayaz.siddiqui at intel.com (Ayaz A Siddiqui) Date: Tue, 23 Jun 2020 10:29:56 +0530 Subject: [Intel-gfx] [PATCH 0/1] drm/i915/gt: Initialize reserved and unspecified MOCS indices Message-ID: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> In order to avoid functional breakage of mis-programmed applications that have grown to depend on unused MOCS entries, we are programming those entries to be equal to fully cached ("L3 + LLC") entry. These reserved and unspecified entries should not be used as they may be changed to less performant variants with better coherency in the future if more entries are needed. I made some mistake in header of patch,Correcting that may leads to a new entry in patchwork. Please follow https://patchwork.freedesktop.org/patch/368699/?series=78012&rev=1 to get details of that discussion. Ayaz A Siddiqui (1): drm/i915/gt: Initialize reserved and unspecified MOCS indices drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- 1 file changed, 89 insertions(+), 4 deletions(-) -- 2.26.2 From ayaz.siddiqui at intel.com Tue Jun 23 04:59:57 2020 From: ayaz.siddiqui at intel.com (Ayaz A Siddiqui) Date: Tue, 23 Jun 2020 10:29:57 +0530 Subject: [Intel-gfx] [PATCH 1/1] drm/i915/gt: Initialize reserved and unspecified MOCS indices In-Reply-To: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> References: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> Message-ID: <20200623045957.1649059-2-ayaz.siddiqui@intel.com> In order to avoid functional breakage of mis-programmed applications that have grown to depend on unused MOCS entries, we are programming those entries to be equal to fully cached ("L3 + LLC") entry. These reserved and unspecified entries should not be used as they may be changed to less performant variants with better coherency in the future if more entries are needed. Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Lucas De Marchi <lucas.demarchi at intel.com> Cc: Tomasz Lis <tomasz.lis at intel.com> Cc: Matt Roper <matthew.d.roper at intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> Cc: Francisco Jerez <currojerez at riseup.net> Cc: Mathew, Alwin <alwin.mathew at intel.com> Cc: Mcguire, Russell W <russell.w.mcguire at intel.com> Cc: Spruit, Neil R <neil.r.spruit at intel.com> Cc: Zhou, Cheng <cheng.zhou at intel.com> Cc: Benemelis, Mike G <mike.g.benemelis at intel.com> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- 1 file changed, 89 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 632e08a4592b2..1089bd5fdba2c 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { L3_1_UC) static const struct drm_i915_mocs_entry tgl_mocs_table[] = { - /* Base - Error (Reserved for Non-Use) */ - MOCS_ENTRY(0, 0x0, 0x0), - /* Base - Reserved */ - MOCS_ENTRY(1, 0x0, 0x0), GEN11_MOCS_ENTRIES, @@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { MOCS_ENTRY(61, LE_1_UC | LE_TC_1_LLC, L3_3_WB), + + /* NOTE: + * Reserved and unspecified MOCS indices have been set to (L3 + LCC). + * These reserved entry should never be used, they may be chanaged + * to low performant variants with better coherency in the future if + * more entries are needed. + */ + + /* Reserved index 0 and 1 */ + MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Reserved index 16 and 17 */ + MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Reserved index 24 and 25 */ + MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Unspecified indices 26 to 47 */ + MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + + /* Unspecified indices 52 to 59 */ + MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB), + MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), + L3_3_WB) }; static const struct drm_i915_mocs_entry icl_mocs_table[] = { -- 2.26.2 From patchwork at emeril.freedesktop.org Tue Jun 23 05:35:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 05:35:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Initialize_reserved_and_unspecified_MOCS_indices_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> References: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> Message-ID: <159289052953.27519.13320000280383028319@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Initialize reserved and unspecified MOCS indices (rev2) URL : https://patchwork.freedesktop.org/series/78012/ State : success == Summary == CI Bug Log - changes from CI_DRM_8654 -> Patchwork_18008 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/index.html Known issues ------------ Here are the changes found in Patchwork_18008 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at kms_frontbuffer_tracking@basic: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1897]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-tgl-u2/igt at kms_frontbuffer_tracking@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-tgl-u2/igt at kms_frontbuffer_tracking@basic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gt_pm: - fi-tgl-u2: [DMESG-FAIL][9] ([i915#1754]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-tgl-u2/igt at i915_selftest@live at gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-tgl-u2/igt at i915_selftest@live at gt_pm.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-varying-size.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1754]: https://gitlab.freedesktop.org/drm/intel/issues/1754 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8654 -> Patchwork_18008 CI-20190529: 20190529 CI_DRM_8654: 0cb5566d436fed92775a65e7ef3b88bd12faf855 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18008: 225407abcf8b8e43275d8d98858b35966e97aba5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 225407abcf8b drm/i915/gt: Initialize reserved and unspecified MOCS indices == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/index.html From lucas.demarchi at intel.com Tue Jun 23 06:15:59 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Mon, 22 Jun 2020 23:15:59 -0700 Subject: [Intel-gfx] [PATCH 1/1] drm/i915/gt: Initialize reserved and unspecified MOCS indices In-Reply-To: <20200623045957.1649059-2-ayaz.siddiqui@intel.com> References: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> <20200623045957.1649059-2-ayaz.siddiqui@intel.com> Message-ID: <20200623061559.zgncq3hlbax4omgc@ldmartin-desk1> On Tue, Jun 23, 2020 at 10:29:57AM +0530, Ayaz A Siddiqui wrote: >In order to avoid functional breakage of mis-programmed applications that >have grown to depend on unused MOCS entries, we are programming >those entries to be equal to fully cached ("L3 + LLC") entry. > >These reserved and unspecified entries should not be used as they may be >changed to less performant variants with better coherency in the future >if more entries are needed. > >Cc: Chris Wilson <chris at chris-wilson.co.uk> >Cc: Lucas De Marchi <lucas.demarchi at intel.com> >Cc: Tomasz Lis <tomasz.lis at intel.com> >Cc: Matt Roper <matthew.d.roper at intel.com> >Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> >Cc: Francisco Jerez <currojerez at riseup.net> >Cc: Mathew, Alwin <alwin.mathew at intel.com> >Cc: Mcguire, Russell W <russell.w.mcguire at intel.com> >Cc: Spruit, Neil R <neil.r.spruit at intel.com> >Cc: Zhou, Cheng <cheng.zhou at intel.com> >Cc: Benemelis, Mike G <mike.g.benemelis at intel.com> > >Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com> >--- > drivers/gpu/drm/i915/gt/intel_mocs.c | 93 ++++++++++++++++++++++++++-- > 1 file changed, 89 insertions(+), 4 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c >index 632e08a4592b2..1089bd5fdba2c 100644 >--- a/drivers/gpu/drm/i915/gt/intel_mocs.c >+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c >@@ -234,10 +234,6 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = { > L3_1_UC) > > static const struct drm_i915_mocs_entry tgl_mocs_table[] = { >- /* Base - Error (Reserved for Non-Use) */ >- MOCS_ENTRY(0, 0x0, 0x0), >- /* Base - Reserved */ >- MOCS_ENTRY(1, 0x0, 0x0), > > GEN11_MOCS_ENTRIES, > >@@ -265,6 +261,95 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = { > MOCS_ENTRY(61, > LE_1_UC | LE_TC_1_LLC, > L3_3_WB), >+ >+ /* NOTE: >+ * Reserved and unspecified MOCS indices have been set to (L3 + LCC). >+ * These reserved entry should never be used, they may be chanaged >+ * to low performant variants with better coherency in the future if >+ * more entries are needed. >+ */ the whole point of structing this table the way it is is that it doesn't take more space than needed and we can override values from previous platforms. MOCS_ENTRY() will set .used = 1. It seems that what you want is to actually change the value when .used == 0 is set. It seems you actually want to set the unused ones to that specific value. See __init_mocs_table() Lucas De Marchi >+ >+ /* Reserved index 0 and 1 */ >+ MOCS_ENTRY(0, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Reserved index 16 and 17 */ >+ MOCS_ENTRY(16, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(17, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Reserved index 24 and 25 */ >+ MOCS_ENTRY(24, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(25, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Unspecified indices 26 to 47 */ >+ MOCS_ENTRY(26, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(27, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(28, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(29, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(30, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(31, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(32, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(33, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(34, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(35, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(36, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(37, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(38, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(39, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(40, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(41, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(42, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(43, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(44, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(45, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(46, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(47, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ >+ /* Unspecified indices 52 to 59 */ >+ MOCS_ENTRY(52, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(53, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(54, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(55, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(56, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(57, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(58, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB), >+ MOCS_ENTRY(59, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), >+ L3_3_WB) > }; > > static const struct drm_i915_mocs_entry icl_mocs_table[] = { >-- >2.26.2 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx at lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx From daniel at ffwll.ch Tue Jun 23 06:17:11 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 23 Jun 2020 08:17:11 +0200 Subject: [Intel-gfx] [PATCH v2 07/32] drm/i915/dg1: add initial DG-1 definitions In-Reply-To: <CAPM=9twOo_5+q-tR9tYqENst59uea-Tf0jmQ4RS4miY_H_bCfg@mail.gmail.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-8-lucas.demarchi@intel.com> <CAKMK7uEBq6-MNL1EsZtT4d07tfq7bXCGXQNX9XnorCg2NuiS5g@mail.gmail.com> <87zh8vo25k.fsf@intel.com> <CAPM=9twOo_5+q-tR9tYqENst59uea-Tf0jmQ4RS4miY_H_bCfg@mail.gmail.com> Message-ID: <CAKMK7uEEHziTci1j3DmawSQb=E1-sb5mS90E865qv_ZpPoSrTw@mail.gmail.com> On Tue, Jun 23, 2020 at 6:54 AM Dave Airlie <airlied at gmail.com> wrote: > > On Mon, 22 Jun 2020 at 19:55, Jani Nikula <jani.nikula at linux.intel.com> wrote: > > > > On Mon, 22 Jun 2020, Daniel Vetter <daniel at ffwll.ch> wrote: > > > On Wed, Jun 17, 2020 at 05:42:15PM -0700, Lucas De Marchi wrote: > > >> From: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> > > >> > > >> Bspec: 33617, 33617 > > >> > > >> Cc: Jos? Roberto de Souza <jose.souza at intel.com> > > >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > > >> Cc: Stuart Summers <stuart.summers at intel.com> > > >> Cc: Vanshidhar Konda <vanshidhar.r.konda at intel.com> > > >> Cc: Lucas De Marchi <lucas.demarchi at intel.com> > > >> Cc: Aravind Iddamsetty <aravind.iddamsetty at intel.com> > > >> Cc: Matt Roper <matthew.d.roper at intel.com> > > >> Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> > > >> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > > >> Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > >> --- > > >> drivers/gpu/drm/i915/i915_drv.h | 7 +++++++ > > >> drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++ > > >> drivers/gpu/drm/i915/intel_device_info.c | 1 + > > >> drivers/gpu/drm/i915/intel_device_info.h | 1 + > > >> 4 files changed, 21 insertions(+) > > >> > > >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > >> index 2f8057a0b2280..f79c09257eb6b 100644 > > >> --- a/drivers/gpu/drm/i915/i915_drv.h > > >> +++ b/drivers/gpu/drm/i915/i915_drv.h > > >> @@ -1428,6 +1428,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > >> #define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) > > >> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) > > >> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) > > >> +#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) > > >> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ > > >> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) > > >> #define IS_BDW_ULT(dev_priv) \ > > >> @@ -1556,6 +1557,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > >> #define IS_RKL_REVID(p, since, until) \ > > >> (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) > > >> > > >> +#define DG1_REVID_A0 0x0 > > >> +#define DG1_REVID_B0 0x1 > > >> + > > >> +#define IS_DG1_REVID(p, since, until) \ > > >> + (IS_DG1(p) && IS_REVID(p, since, until)) > > >> + > > >> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > > >> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) > > >> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > > >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > > >> index e5fdf17cd9cdd..58cceeaa0ffa5 100644 > > >> --- a/drivers/gpu/drm/i915/i915_pci.c > > >> +++ b/drivers/gpu/drm/i915/i915_pci.c > > >> @@ -896,8 +896,20 @@ static const struct intel_device_info rkl_info = { > > >> > > >> #define GEN12_DGFX_FEATURES \ > > >> GEN12_FEATURES, \ > > >> + .memory_regions = REGION_SMEM | REGION_LMEM, \ > > > > > > This has lmem, and we need a new uapi for that. Last year we discussed a > > > plan to have that behind a very scary compile-time only option, to make > > > absolutely sure no one will start relying on this broken state before we > > > aligned everything. And we know the current status is wrong since this > > > patch series doesn't include any of the lmem specific uapi that's being > > > worked on. > > > > > > But now almost a year passed, so that original plan needs to be > > > renegotiated. Personally I'm not sure the scary compile option makes > > > sense any longer, we're way later, users will soon have real hw, and once > > > they have that they will find ways to enable it and we're potentially > > > screwed. Discussed this also with Joonas last week or so in private, and > > > he shares similar concerns. > > > > > > So I think best option here (since keeping patches out of tree is rarely > > > best option) would be to merge just the display enabling for DG1, but also > > > making sure that we have all the rendering support completely disabled. > > > This would mean: > > > - wedge gpu on startup, just to make sure > > > - drm_driver->num_ioctls = 0 (plus ioctls = NULL) > > > - no setting DRIVER_RENDER and DRIVER_SYNCOBJ, we'd be a pure > > > display-only driver > > > > > > Adding Dave and drm-intel maintainers to quickly hash this out. Thoughts? > > > > I'll defer the decision on lmem to folks who actually know this stuff, > > and focus on display. And from that perspective, I'd like to unblock > > merging the display patches. > > > > How does display work without LMEM, I'm assuming you have to scan out > from VRAM on DG1, even if we only have internal non-uapi is this > enough to bring up fbcon? It doesn't. And I think merging completely non-functional code to upstream would be rather pointless, no one (outside from intel) can test it, so the usual Dave Airlie "how does this benefit upstream" would get a "not really, just dead weight". But we have some basic lmem code in upstream already, and afaik it's not much code to wire this up into dumb_create and intel_fbdev.c. Which would give us a working kms-only driver (more or less, still early enabling), which can be tested with what's in upstream only (so actually somewhat useful, and unblocks all the display upstreaming, heck we could even do kms-only CI with igt to make sure it keeps working). And as long as we remove the ioctls and DRIVER_RENDER flag (wedging the gpu is a bit overkill) I don't think there's any risk for uapi: As long as the i915 getparam ioctl doesn't work for reading the chipset id, umds skip (might need to double-check that, worst case we have to rename the driver to something like "intel-display" to make sure no one matches). But yeah I think this series here is not quite there yet. And then once Joonas we can try and figure out a new plan for upstreaming lmem refactoring and uapi. When we discussed this all late last summer just upstreaming kms-only was the first planned step, altough back then with the render uapi hidden behind a compile flag. Joonas thinks that's a bit too risk now that we're a lot later. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From shaofeng.tang at intel.com Tue Jun 23 06:41:03 2020 From: shaofeng.tang at intel.com (Tang, Shaofeng) Date: Tue, 23 Jun 2020 06:41:03 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL In-Reply-To: <20200623034442.GB5687@zhen-hp.sh.intel.com> References: <1592296160-3784-1-git-send-email-shaofeng.tang@intel.com> <159233324036.19488.6385709597388673560@build.alporthouse.com> <20200622082319.GZ5687@zhen-hp.sh.intel.com> <SN6PR11MB255859A6CB9B6BB51C1FB578E2940@SN6PR11MB2558.namprd11.prod.outlook.com> <20200623034442.GB5687@zhen-hp.sh.intel.com> Message-ID: <SN6PR11MB25580A9739F070F64E60437DE2940@SN6PR11MB2558.namprd11.prod.outlook.com> Hi Zhenyu, and Zhiyuan Thanks a lot for your comments. and glad to know it is in the TODO list. We really need this feature to make our released image workable on both GVT-g and GVT-d/native. Multiple plane/overlay are important to us for meeting the Graphics performance target. Do you have an estimate when the feature will be available? and what version of this kernel will provide it, or do you have a back-porting plan for Kernel 5.4? BR, Shaofeng -----Original Message----- From: Zhenyu Wang <zhenyuw at linux.intel.com> Sent: Tuesday, June 23, 2020 11:45 AM To: Tang, Shaofeng <shaofeng.tang at intel.com> Cc: Chris Wilson <chris at chris-wilson.co.uk>; intel-gfx at lists.freedesktop.org; Lv, Zhiyuan <zhiyuan.lv at intel.com> Subject: Re: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active via GETPARAM IOCTL On 2020.06.23 03:46:55 +0000, Tang, Shaofeng wrote: > Hi Zhenyu and Chris, > > Yes, I agree with you. > It must be better if only the workable planes/overlays are returned from KMS. > but currently, KMS still return all planes. and User did not know if > it is a virtual GPU or a native GPU. Do you know if there is a plan to fix or implement it? or any roadmap for sharing. We should expose this info via PV to let guest expose correct config from KMS. I've asked Zhiyuan to add todo for the fix. Better include you to be clear on the issue and requirement. > If KMS does not work in this way, we have to customized our image for this issue. > 2 possible solutions, > first, provide 2 customized image, 1 for VM, and 1 for Native or bare-metal. > and hard-code to only use 1 plane in the VM image. > Second, only provide 1 image, and hard-code to only use 1 plane for both VM and native. > None of them looks good to us. > We don't hope to hardcode the plane usage in user-space either, so this API is really helpful before KMS work as expected. > > As you mentioned there is a potentially good reason to let the user > know if it is a virtual GPU or not. it is not a hardcoding api limits. > I suppose it is a ability to support developer for optimizing the > performance on VM Including choose an appropriate renderer for better performance on VM. > But simply expose virtual GPU flag doesn't give you reliable indicator for performance e.g it doesn't tell you what's rendering is preferred. Or either you do some runtime profiling or try to detect either it's passthrough or mediated device e.g from gpu resource size, etc. That's your guest application's choice. > BR, Shaofeng > > -----Original Message----- > From: Zhenyu Wang <zhenyuw at linux.intel.com> > Sent: Monday, June 22, 2020 4:23 PM > To: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Tang, Shaofeng <shaofeng.tang at intel.com>; > intel-gfx at lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915/gvt: query if vgpu is active > via GETPARAM IOCTL > > On 2020.06.16 19:47:20 +0100, Chris Wilson wrote: > > Quoting Shaofeng Tang (2020-06-16 09:29:20) > > > [Why] > > > Query if vgpu is active, it is useful to the user. > > > Currently, only the primary plane is usable when vgpu is active. > > > The value of vgpu active is useful for user to determine how many > > > planes can be used. also useful for user to determine different > > > behaviors according to vgpu is active or not. > > > > The number of planes must be queried via kms, and all such kernel > > capabilities should be declared via the appropriate interface. > > > > I am not saying that there is not potentially good reason to let the > > user to know it's a virtual gpu, but hardcoding api limits in the > > client based on the parameter is a bad idea. > > Yeah, as I replied for internal before, guest shouldn't detect via this kind of interface, which also doesn't reflect any gvt host capability change. For any current gap, let's fix gvt or vgpu handling instead. > > Thanks. -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 From patchwork at emeril.freedesktop.org Tue Jun 23 06:57:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 06:57:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Initialize_reserved_and_unspecified_MOCS_indices_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> References: <20200623045957.1649059-1-ayaz.siddiqui@intel.com> Message-ID: <159289546158.27518.3778558746292193025@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Initialize reserved and unspecified MOCS indices (rev2) URL : https://patchwork.freedesktop.org/series/78012/ State : success == Summary == CI Bug Log - changes from CI_DRM_8654_full -> Patchwork_18008_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18008_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_shared@q-smoketest-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-glk7/igt at gem_ctx_shared@q-smoketest-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-glk7/igt at gem_ctx_shared@q-smoketest-all.html * igt at gem_exec_reloc@basic-range: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-tglb3/igt at gem_exec_reloc@basic-range.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-tglb7/igt at gem_exec_reloc@basic-range.html * igt at kms_big_fb@y-tiled-32bpp-rotate-270: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#1172] / [i915#1897]) +16 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-tglb6/igt at kms_big_fb@y-tiled-32bpp-rotate-270.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-tglb3/igt at kms_big_fb@y-tiled-32bpp-rotate-270.html * igt at kms_cursor_legacy@short-flip-before-cursor-atomic-transitions: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl7/igt at kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl3/igt at kms_cursor_legacy@short-flip-before-cursor-atomic-transitions.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-snb4/igt at kms_fbcon_fbt@fbc-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-snb1/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1635] / [i915#95]) +14 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt: - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#1897]) +130 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#93] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-kbl6/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-kbl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt at kms_plane_cursor@pipe-b-viewport-size-128: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl10/igt at kms_plane_cursor@pipe-b-viewport-size-128.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl2/igt at kms_plane_cursor@pipe-b-viewport-size-128.html * igt at kms_psr2_su@page_flip: - shard-tglb: [PASS][21] -> [SKIP][22] ([i915#1911]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-tglb2/igt at kms_psr2_su@page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-tglb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#198]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl8/igt at kms_psr@suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl7/igt at kms_psr@suspend.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-tglb7/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-tglb7/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html #### Possible fixes #### * igt at gem_exec_schedule@smoketest-all: - shard-glk: [DMESG-WARN][27] ([i915#118] / [i915#95]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-glk2/igt at gem_exec_schedule@smoketest-all.html * igt at i915_module_load@reload: - shard-iclb: [DMESG-WARN][29] ([i915#1982]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-iclb8/igt at i915_module_load@reload.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-iclb5/igt at i915_module_load@reload.html * igt at i915_pm_rpm@system-suspend-execbuf: - shard-skl: [INCOMPLETE][31] ([i915#151] / [i915#69]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl1/igt at i915_pm_rpm@system-suspend-execbuf.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl6/igt at i915_pm_rpm@system-suspend-execbuf.html * igt at kms_big_fb@x-tiled-32bpp-rotate-0: - shard-apl: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl4/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl2/igt at kms_big_fb@x-tiled-32bpp-rotate-0.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: - shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl4/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl9/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-glk5/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-glk7/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html * igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][39] ([i915#79]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html * igt at kms_flip@2x-modeset-vs-vblank-race-interruptible at ab-vga1-hdmi-a1: - shard-hsw: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-hsw6/igt at kms_flip@2x-modeset-vs-vblank-race-interruptible at ab-vga1-hdmi-a1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-hsw1/igt at kms_flip@2x-modeset-vs-vblank-race-interruptible at ab-vga1-hdmi-a1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-edp1: - shard-skl: [INCOMPLETE][43] ([i915#198]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl10/igt at kms_flip@flip-vs-suspend-interruptible at a-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl3/igt at kms_flip@flip-vs-suspend-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-to-x-tiled: - shard-skl: [FAIL][45] ([i915#167]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl9/igt at kms_flip_tiling@flip-to-x-tiled.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl4/igt at kms_flip_tiling@flip-to-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: - shard-kbl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-tglb3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +5 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at sysfs_heartbeat_interval@mixed at vecs0: - shard-skl: [FAIL][55] ([i915#1731]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl4/igt at sysfs_heartbeat_interval@mixed at vecs0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl10/igt at sysfs_heartbeat_interval@mixed at vecs0.html * igt at vgem_slow@nohang: - shard-apl: [DMESG-WARN][57] ([i915#1635] / [i915#95]) -> [PASS][58] +19 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl1/igt at vgem_slow@nohang.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl8/igt at vgem_slow@nohang.html #### Warnings #### * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [DMESG-WARN][60] ([i915#180] / [i915#93] / [i915#95]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-kbl1/igt at gem_workarounds@suspend-resume-fd.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-kbl7/igt at gem_workarounds@suspend-resume-fd.html * igt at kms_chamelium@vga-edid-read: - shard-apl: [SKIP][61] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][62] ([fdo#109271] / [fdo#111827]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl7/igt at kms_chamelium@vga-edid-read.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl3/igt at kms_chamelium@vga-edid-read.html * igt at kms_chamelium@vga-hpd: - shard-apl: [SKIP][63] ([fdo#109271] / [fdo#111827]) -> [SKIP][64] ([fdo#109271] / [fdo#111827] / [i915#1635]) +2 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl3/igt at kms_chamelium@vga-hpd.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl6/igt at kms_chamelium@vga-hpd.html * igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding: - shard-kbl: [DMESG-WARN][65] ([i915#93] / [i915#95]) -> [DMESG-FAIL][66] ([i915#54] / [i915#95]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-256x256-sliding.html * igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-apl: [SKIP][67] ([fdo#109271] / [i915#1635]) -> [SKIP][68] ([fdo#109271]) +11 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl7/igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl3/igt at kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-apl: [SKIP][69] ([fdo#109271]) -> [SKIP][70] ([fdo#109271] / [i915#1635]) +8 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-apl3/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-apl6/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [FAIL][71] ([fdo#108145] / [i915#265]) -> [DMESG-WARN][72] ([i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8654/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1172]: https://gitlab.freedesktop.org/drm/intel/issues/1172 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167 [i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1897]: https://gitlab.freedesktop.org/drm/intel/issues/1897 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8654 -> Patchwork_18008 CI-20190529: 20190529 CI_DRM_8654: 0cb5566d436fed92775a65e7ef3b88bd12faf855 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18008: 225407abcf8b8e43275d8d98858b35966e97aba5 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18008/index.html From imre.deak at intel.com Tue Jun 23 07:21:32 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 23 Jun 2020 10:21:32 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/6=5D_drm/i915/tgl+=3A_Use_the_correct_DP?= =?utf-8?q?=5FTP=5F*_register_instances_in_MST_encoders?= In-Reply-To: <159234578905.4595.10106455518193745480@emeril.freedesktop.org> References: <20200616141855.746-1-imre.deak@intel.com> <159234578905.4595.10106455518193745480@emeril.freedesktop.org> Message-ID: <20200623072132.GA21923@ideak-desk.fi.intel.com> On Tue, Jun 16, 2020 at 10:16:29PM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [1/6] drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders > URL : https://patchwork.freedesktop.org/series/78423/ > State : success Patches 1-5 pushed to -dinq, thanks for the reviews. > > == Summary == > > CI Bug Log - changes from CI_DRM_8635_full -> Patchwork_17964_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_17964_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_persistence@engines-mixed-process at vcs0: > - shard-apl: [PASS][1] -> [FAIL][2] ([i915#1528]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl1/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html > > * igt at gem_ctx_persistence@process: > - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#93] / [i915#95]) +2 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl4/igt at gem_ctx_persistence@process.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl7/igt at gem_ctx_persistence@process.html > > * igt at gem_exec_whisper@basic-contexts-priority-all: > - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk1/igt at gem_exec_whisper@basic-contexts-priority-all.html > > * igt at gem_workarounds@basic-read: > - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb3/igt at gem_workarounds@basic-read.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb7/igt at gem_workarounds@basic-read.html > > * igt at i915_pm_rps@waitboost: > - shard-glk: [PASS][9] -> [FAIL][10] ([i915#39]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at i915_pm_rps@waitboost.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk6/igt at i915_pm_rps@waitboost.html > > * igt at kms_big_fb@x-tiled-64bpp-rotate-180: > - shard-glk: [PASS][11] -> [DMESG-FAIL][12] ([i915#118] / [i915#95]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk2/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > > * igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled: > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl4/igt at kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-xtiled.html > > * igt at kms_flip@flip-vs-blocking-wf-vblank at b-edp1: > - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1928]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl1/igt at kms_flip@flip-vs-blocking-wf-vblank at b-edp1.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl2/igt at kms_flip@flip-vs-blocking-wf-vblank at b-edp1.html > > * igt at kms_flip_tiling@flip-changes-tiling: > - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +10 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_flip_tiling@flip-changes-tiling.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl2/igt at kms_flip_tiling@flip-changes-tiling.html > > * igt at kms_flip_tiling@flip-changes-tiling-y: > - shard-apl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl2/igt at kms_flip_tiling@flip-changes-tiling-y.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite: > - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#95]) +10 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html > > * igt at kms_frontbuffer_tracking@psr-farfromfence: > - shard-tglb: [PASS][23] -> [SKIP][24] ([i915#668]) +5 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb3/igt at kms_frontbuffer_tracking@psr-farfromfence.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb6/igt at kms_frontbuffer_tracking@psr-farfromfence.html > > * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: > - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html > > * igt at kms_psr@psr2_cursor_plane_move: > - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb2/igt at kms_psr@psr2_cursor_plane_move.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-iclb4/igt at kms_psr@psr2_cursor_plane_move.html > > * igt at kms_vblank@pipe-a-ts-continuation-suspend: > - shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#180]) +6 similar issues > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html > > * igt at perf_pmu@semaphore-busy at rcs0: > - shard-kbl: [PASS][31] -> [FAIL][32] ([i915#1820]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html > > > #### Possible fixes #### > > * igt at gem_ctx_freq@sysfs: > - shard-apl: [DMESG-WARN][33] ([i915#95]) -> [PASS][34] +18 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at gem_ctx_freq@sysfs.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl1/igt at gem_ctx_freq@sysfs.html > > * igt at gem_exec_reloc@basic-concurrent0: > - shard-glk: [FAIL][35] ([i915#1930]) -> [PASS][36] > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html > > * igt at gem_exec_schedule@implicit-read-write at rcs0: > - shard-snb: [INCOMPLETE][37] ([i915#82]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-snb1/igt at gem_exec_schedule@implicit-read-write at rcs0.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-snb4/igt at gem_exec_schedule@implicit-read-write at rcs0.html > > * igt at gem_exec_schedule@smoketest at bcs0: > - shard-tglb: [INCOMPLETE][39] ([i915#1829]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb1/igt at gem_exec_schedule@smoketest at bcs0.html > > * igt at gem_exec_whisper@basic-queues-priority: > - shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42] > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk2/igt at gem_exec_whisper@basic-queues-priority.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk8/igt at gem_exec_whisper@basic-queues-priority.html > > * igt at i915_module_load@reload: > - shard-tglb: [DMESG-WARN][43] ([i915#402]) -> [PASS][44] +2 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb8/igt at i915_module_load@reload.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb2/igt at i915_module_load@reload.html > > * igt at kms_cursor_legacy@flip-vs-cursor-atomic: > - shard-skl: [FAIL][45] ([IGT#5]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl10/igt at kms_cursor_legacy@flip-vs-cursor-atomic.html > > * igt at kms_flip@flip-vs-absolute-wf_vblank at a-edp1: > - shard-tglb: [FAIL][47] ([i915#1928]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb3/igt at kms_flip@flip-vs-absolute-wf_vblank at a-edp1.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb6/igt at kms_flip@flip-vs-absolute-wf_vblank at a-edp1.html > > * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: > - shard-glk: [FAIL][49] ([i915#79]) -> [PASS][50] +1 similar issue > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-glk7/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-glk6/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > > * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: > - shard-kbl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +2 similar issues > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: > - shard-kbl: [DMESG-WARN][53] ([i915#165] / [i915#78]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl2/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl3/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt: > - shard-apl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html > > * igt at kms_plane@plane-position-covered-pipe-b-planes: > - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +6 similar issues > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl4/igt at kms_plane@plane-position-covered-pipe-b-planes.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl5/igt at kms_plane@plane-position-covered-pipe-b-planes.html > > * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: > - shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60] +2 similar issues > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html > > * igt at kms_psr@psr2_sprite_mmap_gtt: > - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb5/igt at kms_psr@psr2_sprite_mmap_gtt.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html > > * igt at perf@blocking-parameterized: > - shard-iclb: [FAIL][63] ([i915#1542]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-iclb8/igt at perf@blocking-parameterized.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-iclb5/igt at perf@blocking-parameterized.html > > > #### Warnings #### > > * igt at i915_suspend@fence-restore-untiled: > - shard-kbl: [DMESG-WARN][65] ([i915#180]) -> [INCOMPLETE][66] ([i915#155]) > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-kbl7/igt at i915_suspend@fence-restore-untiled.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-kbl4/igt at i915_suspend@fence-restore-untiled.html > > * igt at kms_color@pipe-c-ctm-0-25: > - shard-tglb: [DMESG-FAIL][67] ([i915#1149] / [i915#1982]) -> [FAIL][68] ([i915#1149] / [i915#315]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-tglb6/igt at kms_color@pipe-c-ctm-0-25.html > > * igt at kms_plane_alpha_blend@pipe-b-alpha-basic: > - shard-skl: [FAIL][69] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][70] ([fdo#108145] / [i915#1982]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8635/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-alpha-basic.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 > [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 > [i915#1829]: https://gitlab.freedesktop.org/drm/intel/issues/1829 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315 > [i915#39]: https://gitlab.freedesktop.org/drm/intel/issues/39 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 > [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 10) > ------------------------------ > > Missing (1): pig-icl-1065g7 > > > Build changes > ------------- > > * Linux: CI_DRM_8635 -> Patchwork_17964 > > CI-20190529: 20190529 > CI_DRM_8635: f9acdb898773f94ac1bcb9a8826596f88412a53b @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5711: 90611a0c90afa4a46496c78a4faf9638a1538ac3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17964: d302e0a23522a808ab7073bf458e7b70df70def3 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17964/index.html From imre.deak at intel.com Tue Jun 23 07:30:10 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 23 Jun 2020 10:30:10 +0300 Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/dp_mst: Ensure the DPCD ACT sent flag is cleared before waiting for it In-Reply-To: <20200616211146.23027-3-imre.deak@intel.com> References: <20200616141855.746-6-imre.deak@intel.com> <20200616211146.23027-3-imre.deak@intel.com> Message-ID: <20200623073010.GB21923@ideak-desk.fi.intel.com> On Wed, Jun 17, 2020 at 12:11:46AM +0300, Imre Deak wrote: > Atm, we clear the ACT sent flag in the sink's DPCD before updating the > sink's payload table, along clearing the payload table updated flag. > The sink is supposed to set this flag once it detects that the source > has completed the ACT sequence (after detecting the 4 required ACT MTPH > symbols sent by the source). As opposed to this 2 DELL monitors I have > set the flag already along the payload table updated flag, which is not > quite correct. > > To be sure that the sink has detected the ACT MTPH symbols before > continuing enabling the encoder, clear the ACT sent flag before enabling > or disabling the transcoder VC payload allocation (which is what starts > the ACT sequence). > > v2 (Ville): > - Use the correct bit to clear the flags. > - Add code comment explaining the clearing semantics of the ACT handled > flag. > > Cc: Lyude Paul <lyude at redhat.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: dri-devel at lists.freedesktop.org > Signed-off-by: Imre Deak <imre.deak at intel.com> Dropping this patch because clearing the ACT handled flag from DPCD causes a problem for some sinks, which set this flag only once when the VC payload table is updated and do not set it when the ACT symbols are actually sent by the source. > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 38 +++++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ > include/drm/drm_dp_mst_helper.h | 2 ++ > 3 files changed, 40 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index b2f5a84b4cfb..1f5d14128c1a 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -4377,6 +4377,41 @@ void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, > } > EXPORT_SYMBOL(drm_dp_mst_deallocate_vcpi); > > +/** > + * drm_dp_clear_payload_status() - Clears the payload table status flags > + * @mgr: manager to use > + * > + * Clears the payload table ACT handled and table updated flags in the MST hub's > + * DPCD. This function must be called before updating the payload table or > + * starting the ACT sequence and waiting for the corresponding flags to get > + * set by the hub. > + * > + * Returns: > + * 0 if the flags got cleared successfully, otherwise a negative error code. > + */ > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr) > +{ > + int ret; > + > + /* > + * Note that the following is based on the DP Standard stating that > + * writing the DP_PAYLOAD_TABLE_UPDATED bit alone will clear both the > + * DP_PAYLOAD_TABLE_UPDATED and the DP_PAYLOAD_ACT_HANDLED flags. This > + * seems to be also the only way to clear DP_PAYLOAD_ACT_HANDLED. > + */ > + ret = drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > + DP_PAYLOAD_TABLE_UPDATED); > + if (ret < 0) { > + DRM_DEBUG_DRIVER("Can't clear the ACT handled/table updated flags (%d)\n", > + ret); > + return ret; > + } > + WARN_ON(ret != 1); > + > + return 0; > +} > +EXPORT_SYMBOL(drm_dp_clear_payload_status); > + > static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > int id, struct drm_dp_payload *payload) > { > @@ -4384,8 +4419,7 @@ static int drm_dp_dpcd_write_payload(struct drm_dp_mst_topology_mgr *mgr, > int ret; > int retries = 0; > > - drm_dp_dpcd_writeb(mgr->aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, > - DP_PAYLOAD_TABLE_UPDATED); > + drm_dp_clear_payload_status(mgr); > > payload_alloc[0] = id; > payload_alloc[1] = payload->start_slot; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 9308b5920780..3c4b0fb10d8b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -323,6 +323,8 @@ static void clear_act_sent(struct intel_dp *intel_dp) > > intel_de_write(i915, intel_dp->regs.dp_tp_status, > DP_TP_STATUS_ACT_SENT); > + > + drm_dp_clear_payload_status(&intel_dp->mst_mgr); > } > > static void wait_for_act_sent(struct intel_dp *intel_dp) > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 8b9eb4db3381..2facb87624bf 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -763,6 +763,8 @@ int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, > int pbn); > > > +int drm_dp_clear_payload_status(struct drm_dp_mst_topology_mgr *mgr); > + > int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr); > > > -- > 2.23.1 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From daniel at ffwll.ch Tue Jun 23 07:39:17 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 23 Jun 2020 09:39:17 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> Message-ID: <CAKMK7uHBKrpDWu+DvtYncDK=LOdGJyMK7t6fpOaGovnYFiBUZw@mail.gmail.com> On Fri, Jun 12, 2020 at 1:35 AM Felix Kuehling <felix.kuehling at amd.com> wrote: > > Am 2020-06-11 um 10:15 a.m. schrieb Jason Gunthorpe: > > On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: > >>> I still have my doubts about allowing fence waiting from within shrinkers. > >>> IMO ideally they should use a trywait approach, in order to allow memory > >>> allocation during command submission for drivers that > >>> publish fences before command submission. (Since early reservation object > >>> release requires that). > >> Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up > >> with a mempool to make sure it can handle it's allocations. > >> > >>> But since drivers are already waiting from within shrinkers and I take your > >>> word for HMM requiring this, > >> Yeah the big trouble is HMM and mmu notifiers. That's the really awkward > >> one, the shrinker one is a lot less established. > > I really question if HW that needs something like DMA fence should > > even be using mmu notifiers - the best use is HW that can fence the > > DMA directly without having to get involved with some command stream > > processing. > > > > Or at the very least it should not be a generic DMA fence but a > > narrowed completion tied only into the same GPU driver's command > > completion processing which should be able to progress without > > blocking. > > > > The intent of notifiers was never to endlessly block while vast > > amounts of SW does work. > > > > Going around and switching everything in a GPU to GFP_ATOMIC seems > > like bad idea. > > > >> I've pinged a bunch of armsoc gpu driver people and ask them how much this > >> hurts, so that we have a clear answer. On x86 I don't think we have much > >> of a choice on this, with userptr in amd and i915 and hmm work in nouveau > >> (but nouveau I think doesn't use dma_fence in there). > > Soon nouveau will get company. We're working on a recoverable page fault > implementation for HMM in amdgpu where we'll need to update page tables > using the GPUs SDMA engine and wait for corresponding fences in MMU > notifiers. Can you pls cc these patches to dri-devel when they show up? Depending upon how your hw works there's and endless amount of bad things that can happen. Also I think (again depending upon how the hw exactly works) this stuff would be a perfect example for the dma_fence annotations. The worst case is if your hw cannot preempt while a hw page fault is pending. That means none of the dma_fence will ever signal (the amdkfd preempt ctx fences wont, and the classic fences from amdgpu might be also stall). At least when you're unlucky and the fence you're waiting on somehow (anywhere in its dependency chain really) need the engine that's currently blocked waiting for the hw page fault. That in turn means anything you do in your hw page fault handler is in the critical section for dma fence signalling, which has far reaching implications. -Daniel > > Regards, > Felix > > > > Right, nor will RDMA ODP. > > > > Jason > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From imre.deak at intel.com Tue Jun 23 08:24:11 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 23 Jun 2020 11:24:11 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled Message-ID: <20200623082411.3889-1-imre.deak@intel.com> The spec requires enabling the MST Virtual Channel payload allocation - in a seperate step - after the transcoder is enabled, follow this. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Jos? Roberto de Souza <jose.souza at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++----- drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 73d6cc29291a..884b507c5f55 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1653,7 +1653,6 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - u32 ctl; if (INTEL_GEN(dev_priv) >= 11) { enum transcoder master_transcoder = crtc_state->master_transcoder; @@ -1671,10 +1670,9 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); } - ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) - ctl |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), + intel_ddi_transcoder_func_reg_val_get(encoder, + crtc_state)); } /* diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0c891bdd1aa0..3426ce8bbbd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -539,6 +539,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, struct intel_digital_port *intel_dig_port = intel_mst->primary; struct intel_dp *intel_dp = &intel_dig_port->dp; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + u32 val; drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); @@ -546,6 +547,13 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, intel_ddi_enable_transcoder_func(encoder, pipe_config); + val = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); + val |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder), + val); + drm_dbg_kms(&dev_priv->drm, "active links %d\n", intel_dp->active_mst_links); -- 2.23.1 From patchwork at emeril.freedesktop.org Tue Jun 23 08:36:23 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 08:36:23 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/dp=5Fmst=3A_Enable_VC_payload_allocation_after_tra?= =?utf-8?q?nscoder_is_enabled?= In-Reply-To: <20200623082411.3889-1-imre.deak@intel.com> References: <20200623082411.3889-1-imre.deak@intel.com> Message-ID: <159290138316.27520.10134801258671094378@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled URL : https://patchwork.freedesktop.org/series/78728/ State : warning == Summary == $ dim checkpatch origin/drm-tip c95fdf71011e drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled -:11: WARNING:TYPO_SPELLING: 'seperate' may be misspelled - perhaps 'separate'? #11: - in a seperate step - after the transcoder is enabled, follow this. total: 0 errors, 1 warnings, 0 checks, 40 lines checked From patchwork at emeril.freedesktop.org Tue Jun 23 09:19:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 09:19:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/dp=5Fmst=3A_Enable_VC_payload_allocation_after_transcoder?= =?utf-8?q?_is_enabled?= In-Reply-To: <20200623082411.3889-1-imre.deak@intel.com> References: <20200623082411.3889-1-imre.deak@intel.com> Message-ID: <159290396150.27520.16303798068762660271@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled URL : https://patchwork.freedesktop.org/series/78728/ State : success == Summary == CI Bug Log - changes from CI_DRM_8655 -> Patchwork_18009 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/index.html Known issues ------------ Here are the changes found in Patchwork_18009 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#1982] / [i915#62] / [i915#92]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8655 -> Patchwork_18009 CI-20190529: 20190529 CI_DRM_8655: 25d43cec6c2200a9ebe8a8b0923b27b164a6f424 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18009: c95fdf71011e7df7708cea81e3736b24fb8f5189 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c95fdf71011e drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/index.html From thomas_os at shipmail.org Tue Jun 23 09:33:20 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 11:33:20 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <20200622095921.15530-7-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> Message-ID: <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> Hi, Chris! On 6/22/20 11:59 AM, Chris Wilson wrote: > In order to actually handle eviction and what not, we need to process > all the objects together under a common lock, reservation_ww_class. As > such, do a memory reservation pass after looking up the object/vma, > which then feeds into the rest of execbuf [relocation, cmdparsing, > flushing and ofc execution]. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > 1 file changed, 70 insertions(+), 21 deletions(-) > Which tree is this against? The series doesn't apply cleanly against drm-tip? ... > +static int eb_reserve_mm(struct i915_execbuffer *eb) > +{ > + const u64 idx = eb->context->timeline->fence_context; > + struct ww_acquire_ctx acquire; > + struct eb_vma *ev; > + int err; > + > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > + if (!eb->mm_fence) > + return -ENOMEM; Where are the proxy fence functions defined? Thanks, Thomas From chris at chris-wilson.co.uk Tue Jun 23 10:03:31 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 11:03:31 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> Message-ID: <159290661156.6856.12185315246799210214@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > Hi, Chris! > > On 6/22/20 11:59 AM, Chris Wilson wrote: > > In order to actually handle eviction and what not, we need to process > > all the objects together under a common lock, reservation_ww_class. As > > such, do a memory reservation pass after looking up the object/vma, > > which then feeds into the rest of execbuf [relocation, cmdparsing, > > flushing and ofc execution]. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > > 1 file changed, 70 insertions(+), 21 deletions(-) > > > Which tree is this against? The series doesn't apply cleanly against > drm-tip? It's continuing on from the scheduler patches, the bug fixes and the iris-deferred-fence work. I thought throwing all of those old patches into the pile would have been distracting. > ... > > > +static int eb_reserve_mm(struct i915_execbuffer *eb) > > +{ > > + const u64 idx = eb->context->timeline->fence_context; > > + struct ww_acquire_ctx acquire; > > + struct eb_vma *ev; > > + int err; > > + > > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > > + if (!eb->mm_fence) > > + return -ENOMEM; > > Where are the proxy fence functions defined? In dma-fence-proxy.c ;) -Chris From patchwork at emeril.freedesktop.org Tue Jun 23 10:06:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 10:06:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_VRR_capable_attach_prop_in_i915=2C_VRR_debugfs_=28rev2=29?= In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <159290680385.27518.16409894714612194467@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, VRR debugfs (rev2) URL : https://patchwork.freedesktop.org/series/78670/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2ee51bf6e884 drm/i915/dp: Attach and set drm connector VRR property 377c60b4f795 drm/debug: Expose connector VRR monitor range via debugfs -:38: WARNING:TYPO_SPELLING: 'Seperate' may be misspelled - perhaps 'Separate'? #38: * Seperate patch for removal of AMD specific logic (Manasi) -:83: WARNING:SYMBOLIC_PERMS: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. #83: FILE: drivers/gpu/drm/drm_debugfs.c:436: + debugfs_create_file("vrr_range", S_IRUGO, root, connector, total: 0 errors, 2 warnings, 0 checks, 34 lines checked 5e027171f0c0 Revert "drm/amd/display: Expose connector VRR range via debugfs" From patchwork at emeril.freedesktop.org Tue Jun 23 10:07:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 10:07:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?VRR_capable_attach_prop_in_i915=2C_VRR_debugfs_=28rev2=29?= In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <159290684599.27518.4835680057251365249@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, VRR debugfs (rev2) URL : https://patchwork.freedesktop.org/series/78670/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. -drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1171:46: warning: Using plain integer as NULL pointer +drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.c:1151:46: warning: Using plain integer as NULL pointer +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement From patchwork at emeril.freedesktop.org Tue Jun 23 10:36:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 10:36:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgVlJS?= =?utf-8?q?_capable_attach_prop_in_i915=2C_VRR_debugfs_=28rev2=29?= In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <159290860097.27520.7248936921614051894@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, VRR debugfs (rev2) URL : https://patchwork.freedesktop.org/series/78670/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8655 -> Patchwork_18010 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18010 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18010, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18010/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18010: ### IGT changes ### #### Possible regressions #### * igt at kms_chamelium@dp-hpd-fast: - fi-cml-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18010/fi-cml-u2/igt at kms_chamelium@dp-hpd-fast.html Known issues ------------ Here are the changes found in Patchwork_18010 that come from known issues: ### IGT changes ### #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][3] ([i915#1888]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18010/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [INCOMPLETE][5] ([i915#1932]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18010/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][7] ([i915#402]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18010/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 Participating hosts (44 -> 11) ------------------------------ ERROR: It appears as if the changes made in Patchwork_18010 prevented too many machines from booting. Missing (33): fi-kbl-soraka fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc fi-snb-2520m fi-icl-y fi-byt-n2820 fi-icl-dsi fi-skl-6600u fi-snb-2600 fi-bxt-dsi fi-cml-s fi-bsw-n3050 fi-byt-j1900 fi-glk-dsi fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-bsw-nick fi-ilk-m540 fi-ehl-1 fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-guc fi-kbl-guc fi-whl-u fi-kbl-x1275 fi-bsw-kefka fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8655 -> Patchwork_18010 CI-20190529: 20190529 CI_DRM_8655: 25d43cec6c2200a9ebe8a8b0923b27b164a6f424 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18010: 5e027171f0c0028d9cc34be622d2e34b44a62c3a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5e027171f0c0 Revert "drm/amd/display: Expose connector VRR range via debugfs" 377c60b4f795 drm/debug: Expose connector VRR monitor range via debugfs 2ee51bf6e884 drm/i915/dp: Attach and set drm connector VRR property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18010/index.html From daniel.vetter at ffwll.ch Tue Jun 23 10:51:04 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 23 Jun 2020 12:51:04 +0200 Subject: [Intel-gfx] [PATCH 08/18] drm/amdgpu: add dma-fence annotations to atomic commit path In-Reply-To: <20200604081224.863494-9-daniel.vetter@ffwll.ch> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-9-daniel.vetter@ffwll.ch> Message-ID: <CAKMK7uHx+rFyjQOWL2r1fOo2EP3u_owMP2zfg3NnEkxUY4BhkA@mail.gmail.com> Hi Roland & vmwgfx maintainers, Thomas has played around with these annotations on his vmwgfx setup, and found some issues. Apparently in the atomic_commit_tail path when handling the dirty rectangle stuff you acquire a ttm reservation, which is a no-go since it could deadlock with other paths - atomic commits can produce a dma_fence. This patch here highlights that with the new annotations, and apparently causes a lockdep splat if you go through the dirty rect paths (not sure if it also happens otherwise, Thomas can fill you in with the details). Can you pls take a look at this? I'm happy to help out with analyzing any lockdep splats. For actual fixes Thomas is better since I don't understand a lot of how drm/vmwgfx works internally. Cheers, Daniel On Thu, Jun 4, 2020 at 10:12 AM Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > I need a canary in a ttm-based atomic driver to make sure the > dma_fence_begin/end_signalling annotations actually work. > > Cc: linux-media at vger.kernel.org > Cc: linaro-mm-sig at lists.linaro.org > Cc: linux-rdma at vger.kernel.org > Cc: amd-gfx at lists.freedesktop.org > Cc: intel-gfx at lists.freedesktop.org > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Christian K?nig <christian.koenig at amd.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index bdba0bfd6df1..adabfa929f42 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -57,6 +57,7 @@ > > #include "ivsrcid/ivsrcid_vislands30.h" > > +#include <linux/module.h> > #include <linux/module.h> > #include <linux/moduleparam.h> > #include <linux/version.h> > @@ -7320,6 +7321,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) > struct drm_connector_state *old_con_state, *new_con_state; > struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; > int crtc_disable_count = 0; > + bool fence_cookie; > + > + fence_cookie = dma_fence_begin_signalling(); > > drm_atomic_helper_update_legacy_modeset_state(dev, state); > > @@ -7600,6 +7604,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) > /* Signal HW programming completion */ > drm_atomic_helper_commit_hw_done(state); > > + dma_fence_end_signalling(fence_cookie); > + > if (wait_for_vblank) > drm_atomic_helper_wait_for_flip_done(dev, state); > > -- > 2.26.2 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Tue Jun 23 11:11:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 11:11:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/dp=5Fmst=3A_Enable_VC_payload_allocation_after_transcoder?= =?utf-8?q?_is_enabled?= In-Reply-To: <20200623082411.3889-1-imre.deak@intel.com> References: <20200623082411.3889-1-imre.deak@intel.com> Message-ID: <159291070631.27519.2625554200756771836@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled URL : https://patchwork.freedesktop.org/series/78728/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8655_full -> Patchwork_18009_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18009_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18009_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18009_full: ### IGT changes ### #### Possible regressions #### * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: - shard-kbl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html ### Piglit changes ### #### Possible regressions #### * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2 (NEW): - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +7 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2.html * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2 (NEW): - {pig-icl-1065g7}: NOTRUN -> [CRASH][4] +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2.html New tests --------- New tests have been introduced between CI_DRM_8655_full and Patchwork_18009_full: ### New Piglit tests (11) ### * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat3_array3-position-double_dmat3x4_array2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3-int_ivec3_array3: - Statuses : 1 crash(s) - Exec time: [1.00] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3x2_array3-double_dmat3x2_array2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3-float_mat4x2_array3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-int_ivec2-double_dmat3x4: - Statuses : 1 crash(s) - Exec time: [0.84] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-ubyte_uint-short_ivec4-double_dmat2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2: - Statuses : 1 crash(s) - Exec time: [0.92] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-ubyte_uvec2-short_int-position-double_dmat2x4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-uint_uint_array3-position-double_dmat4x3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in Patchwork_18009_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#58] / [k.org#198133]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk1/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk8/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at gem_exec_schedule@smoketest-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at gem_exec_schedule@smoketest-all.html * igt at gem_vm_create@isolation: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#95]) +16 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl6/igt at gem_vm_create@isolation.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at gem_vm_create@isolation.html * igt at gen9_exec_parse@allowed-all: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at gen9_exec_parse@allowed-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl2/igt at gen9_exec_parse@allowed-all.html - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1436] / [i915#716]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at gen9_exec_parse@allowed-all.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at gen9_exec_parse@allowed-all.html * igt at i915_suspend@forcewake: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#636] / [i915#69]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at i915_suspend@forcewake.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at i915_suspend@forcewake.html * igt at kms_big_fb@x-tiled-8bpp-rotate-180: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-rte: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +7 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_cursor@pipe-b-viewport-size-128: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +13 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl7/igt at kms_plane_cursor@pipe-b-viewport-size-128.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl8/igt at kms_plane_cursor@pipe-b-viewport-size-128.html * igt at kms_plane_lowres@pipe-a-tiling-none: - shard-glk: [PASS][33] -> [FAIL][34] ([i915#899]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_plane_lowres@pipe-a-tiling-none.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk7/igt at kms_plane_lowres@pipe-a-tiling-none.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#1542]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb4/igt at perf@blocking-parameterized.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb3/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_eio@kms: - shard-kbl: [DMESG-WARN][37] ([i915#93] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at gem_eio@kms.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at gem_eio@kms.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_big_fb@linear-32bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl1/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +5 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: - shard-glk: [FAIL][47] ([i915#46]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk9/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk1/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_flip@flip-vs-suspend at c-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-skl: [FAIL][51] ([i915#699]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-changes-tiling-y.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_flip_tiling@flip-to-x-tiled: - shard-skl: [FAIL][53] ([i915#167]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-to-x-tiled.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-to-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html * igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@read-crc-pipe-a: - shard-skl: [FAIL][63] ([i915#53]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_pipe_crc_basic@read-crc-pipe-a.html * igt at kms_plane_multiple@atomic-pipe-b-tiling-yf: - shard-kbl: [FAIL][65] ([i915#1779]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html * igt at vgem_slow@nohang: - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +11 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at vgem_slow@nohang.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at vgem_slow@nohang.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rpm@gem-execbuf-stress-pc8: - shard-apl: [SKIP][71] ([fdo#109271] / [i915#1635]) -> [SKIP][72] ([fdo#109271]) +4 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html * igt at kms_chamelium@dp-crc-multiple: - shard-apl: [SKIP][73] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_chamelium@dp-crc-multiple.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at kms_chamelium@dp-crc-multiple.html * igt at kms_chamelium@vga-hpd: - shard-apl: [SKIP][75] ([fdo#109271] / [fdo#111827]) -> [SKIP][76] ([fdo#109271] / [fdo#111827] / [i915#1635]) +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_chamelium@vga-hpd.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_chamelium@vga-hpd.html * igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled: - shard-snb: [SKIP][77] ([fdo#109271]) -> [TIMEOUT][78] ([i915#1958]) +5 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html * igt at kms_flip@flip-vs-expired-vblank at a-edp1: - shard-skl: [DMESG-WARN][79] ([i915#1982]) -> [DMESG-FAIL][80] ([i915#1982] / [i915#79]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +6 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][83] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][84] ([i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167 [i915#1779]: https://gitlab.freedesktop.org/drm/intel/issues/1779 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8655 -> Patchwork_18009 CI-20190529: 20190529 CI_DRM_8655: 25d43cec6c2200a9ebe8a8b0923b27b164a6f424 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18009: c95fdf71011e7df7708cea81e3736b24fb8f5189 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/index.html From thomas_os at shipmail.org Tue Jun 23 11:22:11 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 13:22:11 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <20200622095921.15530-7-chris@chris-wilson.co.uk> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> Message-ID: <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> Hi, Chris, On 6/22/20 11:59 AM, Chris Wilson wrote: > In order to actually handle eviction and what not, we need to process > all the objects together under a common lock, reservation_ww_class. As > such, do a memory reservation pass after looking up the object/vma, > which then feeds into the rest of execbuf [relocation, cmdparsing, > flushing and ofc execution]. > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > 1 file changed, 70 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 46fcbdf8161c..8db2e013465f 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -53,10 +53,9 @@ struct eb_vma_array { > > #define __EXEC_OBJECT_HAS_PIN BIT(31) > #define __EXEC_OBJECT_HAS_FENCE BIT(30) > -#define __EXEC_OBJECT_HAS_PAGES BIT(29) > -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) > -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) > -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ > +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) > +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) > +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ > > #define __EXEC_HAS_RELOC BIT(31) > #define __EXEC_INTERNAL_FLAGS (~0u << 31) > @@ -241,6 +240,8 @@ struct i915_execbuffer { > struct intel_context *context; /* logical state for the request */ > struct i915_gem_context *gem_context; /** caller's context */ > > + struct dma_fence *mm_fence; > + > struct i915_request *request; /** our request to build */ > struct eb_vma *batch; /** identity of the batch obj/vma */ > struct i915_vma *trampoline; /** trampoline used for chaining */ > @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) > if (ev->flags & __EXEC_OBJECT_HAS_PIN) > __i915_vma_unpin(vma); > > - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > - i915_gem_object_unpin_pages(vma->obj); > - > - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > - __EXEC_OBJECT_HAS_FENCE | > - __EXEC_OBJECT_HAS_PAGES); > + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > } > > static void eb_vma_array_destroy(struct kref *kref) > @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > list_add_tail(&ev->lock_link, &eb->lock); > } > > +static int eb_vma_get_pages(struct i915_execbuffer *eb, > + struct eb_vma *ev, > + u64 idx) > +{ > + struct i915_vma *vma = ev->vma; > + int err; > + > + /* XXX also preallocate PD for vma */ > + > + err = ____i915_gem_object_get_pages_async(vma->obj); > + if (err) > + return err; > + > + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > +} > + > +static int eb_reserve_mm(struct i915_execbuffer *eb) > +{ > + const u64 idx = eb->context->timeline->fence_context; > + struct ww_acquire_ctx acquire; > + struct eb_vma *ev; > + int err; > + > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > + if (!eb->mm_fence) > + return -ENOMEM; Question: eb is local to this thread, right, so eb->mm_fence is not considered "published" yet? > + > + ww_acquire_init(&acquire, &reservation_ww_class); > + > + err = eb_lock_vma(eb, &acquire); > + if (err) > + goto out; > + > + ww_acquire_done(&acquire); > + > + list_for_each_entry(ev, &eb->lock, lock_link) { > + struct i915_vma *vma = ev->vma; > + > + if (err == 0) > + err = eb_vma_get_pages(eb, ev, idx); I figure this is where you publish the proxy fence? If so, the fence signaling critical path starts with this loop, and that means any code we call between here and submission complete (including spawned work we need to wait for before submission) may not lock the reservation_ww_class nor (still being discussed) allocate memory. It looks like i915_pin_vma takes a reservation_ww_class. And all memory pinning seems to be in the fence critical path as well? /Thomas From daniel at ffwll.ch Tue Jun 23 11:30:04 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 23 Jun 2020 13:30:04 +0200 Subject: [Intel-gfx] [igt-dev] [PATCH libdrm] intel: sync i915_pciids.h with kernel In-Reply-To: <87wo3znmlv.fsf@intel.com> References: <20200616123758.3331-1-ramadevi.gandi@intel.com> <87wo3znmlv.fsf@intel.com> Message-ID: <20200623113004.GM20149@phenom.ffwll.local> On Mon, Jun 22, 2020 at 06:31:24PM +0300, Jani Nikula wrote: > On Tue, 16 Jun 2020, ramadevi.gandi at intel.com wrote: > > From: Gandi Ramadevi <ramadevi.gandi at intel.com> > > > > Add DG1 PCI ID > > There are no DG1 PCI IDs in kernel. So please don't add them here > either. Also, do we have anything left using libdrm-intel? -Daniel > > BR, > Jani. > > > > > > Signed-off-by: Gandi Ramadevi <ramadevi.gandi at intel.com> > > --- > > intel/i915_pciids.h | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h > > index 662d8351..724e68a0 100644 > > --- a/intel/i915_pciids.h > > +++ b/intel/i915_pciids.h > > @@ -605,4 +605,9 @@ > > INTEL_VGA_DEVICE(0x9AD9, info), \ > > INTEL_VGA_DEVICE(0x9AF8, info) > > > > +/* DG1 */ > > +#define INTEL_DG1_IDS(info) \ > > + INTEL_VGA_DEVICE(0x4905, info), \ > > + INTEL_VGA_DEVICE(0x4906, info) > > + > > #endif /* _I915_PCIIDS_H */ > > -- > Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > igt-dev mailing list > igt-dev at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/igt-dev -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From imre.deak at intel.com Tue Jun 23 11:53:09 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 23 Jun 2020 14:53:09 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/dp=5Fmst=3A_Enable_VC_payload_allocation_after_transcoder?= =?utf-8?q?_is_enabled?= In-Reply-To: <159291070631.27519.2625554200756771836@emeril.freedesktop.org> References: <20200623082411.3889-1-imre.deak@intel.com> <159291070631.27519.2625554200756771836@emeril.freedesktop.org> Message-ID: <20200623115309.GA5416@ideak-desk.fi.intel.com> Hi Lakshmi, On Tue, Jun 23, 2020 at 11:11:46AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled > URL : https://patchwork.freedesktop.org/series/78728/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8655_full -> Patchwork_18009_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_18009_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_18009_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_18009_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: > - shard-kbl: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html Looks unrelated, since no MST on this machine, and it's probably: https://gitlab.freedesktop.org/drm/intel/-/issues/636 > > > > ### Piglit changes ### > > #### Possible regressions #### > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2 (NEW): > - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +7 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2.html > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2 (NEW): > - {pig-icl-1065g7}: NOTRUN -> [CRASH][4] +2 similar issues > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2.html > > > New tests > --------- > > New tests have been introduced between CI_DRM_8655_full and Patchwork_18009_full: > > ### New Piglit tests (11) ### > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat3_array3-position-double_dmat3x4_array2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3-int_ivec3_array3: > - Statuses : 1 crash(s) > - Exec time: [1.00] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3x2_array3-double_dmat3x2_array2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3-float_mat4x2_array3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-int_ivec2-double_dmat3x4: > - Statuses : 1 crash(s) > - Exec time: [0.84] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-ubyte_uint-short_ivec4-double_dmat2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2: > - Statuses : 1 crash(s) > - Exec time: [0.92] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-ubyte_uvec2-short_int-position-double_dmat2x4: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-uint_uint_array3-position-double_dmat4x3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > > > Known issues > ------------ > > Here are the changes found in Patchwork_18009_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_isolation@preservation-s3 at vecs0: > - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#58] / [k.org#198133]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk1/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk8/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > > * igt at gem_exec_schedule@smoketest-all: > - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at gem_exec_schedule@smoketest-all.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at gem_exec_schedule@smoketest-all.html > > * igt at gem_vm_create@isolation: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#95]) +16 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl6/igt at gem_vm_create@isolation.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at gem_vm_create@isolation.html > > * igt at gen9_exec_parse@allowed-all: > - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at gen9_exec_parse@allowed-all.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl2/igt at gen9_exec_parse@allowed-all.html > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1436] / [i915#716]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at gen9_exec_parse@allowed-all.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at gen9_exec_parse@allowed-all.html > > * igt at i915_suspend@forcewake: > - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#636] / [i915#69]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at i915_suspend@forcewake.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at i915_suspend@forcewake.html > > * igt at kms_big_fb@x-tiled-8bpp-rotate-180: > - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html > > * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: > - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: > - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-rte: > - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html > > * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: > - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) +1 similar issue > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html > > * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: > - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +7 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_plane_cursor@pipe-b-viewport-size-128: > - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +13 similar issues > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl7/igt at kms_plane_cursor@pipe-b-viewport-size-128.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl8/igt at kms_plane_cursor@pipe-b-viewport-size-128.html > > * igt at kms_plane_lowres@pipe-a-tiling-none: > - shard-glk: [PASS][33] -> [FAIL][34] ([i915#899]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_plane_lowres@pipe-a-tiling-none.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk7/igt at kms_plane_lowres@pipe-a-tiling-none.html > > * igt at perf@blocking-parameterized: > - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#1542]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb4/igt at perf@blocking-parameterized.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb3/igt at perf@blocking-parameterized.html > > > #### Possible fixes #### > > * igt at gem_eio@kms: > - shard-kbl: [DMESG-WARN][37] ([i915#93] / [i915#95]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at gem_eio@kms.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at gem_eio@kms.html > > * igt at gem_exec_whisper@basic-queues-forked-all: > - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at gem_exec_whisper@basic-queues-forked-all.html > > * igt at kms_big_fb@linear-32bpp-rotate-180: > - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_big_fb@linear-32bpp-rotate-180.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl1/igt at kms_big_fb@linear-32bpp-rotate-180.html > > * igt at kms_big_fb@x-tiled-64bpp-rotate-0: > - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: > - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +5 similar issues > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html > > * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: > - shard-glk: [FAIL][47] ([i915#46]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk9/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk1/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > > * igt at kms_flip@flip-vs-suspend at c-dp1: > - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_flip@flip-vs-suspend at c-dp1.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html > > * igt at kms_flip_tiling@flip-changes-tiling-y: > - shard-skl: [FAIL][51] ([i915#699]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-changes-tiling-y.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-changes-tiling-y.html > > * igt at kms_flip_tiling@flip-to-x-tiled: > - shard-skl: [FAIL][53] ([i915#167]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-to-x-tiled.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-to-x-tiled.html > > * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: > - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html > > * igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt: > - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html > > * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: > - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_pipe_crc_basic@read-crc-pipe-a: > - shard-skl: [FAIL][63] ([i915#53]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-a.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_pipe_crc_basic@read-crc-pipe-a.html > > * igt at kms_plane_multiple@atomic-pipe-b-tiling-yf: > - shard-kbl: [FAIL][65] ([i915#1779]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html > > * igt at vgem_slow@nohang: > - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +11 similar issues > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at vgem_slow@nohang.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at vgem_slow@nohang.html > > > #### Warnings #### > > * igt at gem_exec_reloc@basic-concurrent16: > - shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html > > * igt at i915_pm_rpm@gem-execbuf-stress-pc8: > - shard-apl: [SKIP][71] ([fdo#109271] / [i915#1635]) -> [SKIP][72] ([fdo#109271]) +4 similar issues > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html > > * igt at kms_chamelium@dp-crc-multiple: > - shard-apl: [SKIP][73] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_chamelium@dp-crc-multiple.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at kms_chamelium@dp-crc-multiple.html > > * igt at kms_chamelium@vga-hpd: > - shard-apl: [SKIP][75] ([fdo#109271] / [fdo#111827]) -> [SKIP][76] ([fdo#109271] / [fdo#111827] / [i915#1635]) +2 similar issues > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_chamelium@vga-hpd.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_chamelium@vga-hpd.html > > * igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled: > - shard-snb: [SKIP][77] ([fdo#109271]) -> [TIMEOUT][78] ([i915#1958]) +5 similar issues > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html > > * igt at kms_flip@flip-vs-expired-vblank at a-edp1: > - shard-skl: [DMESG-WARN][79] ([i915#1982]) -> [DMESG-FAIL][80] ([i915#1982] / [i915#79]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: > - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +6 similar issues > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [DMESG-FAIL][83] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][84] ([i915#1982]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167 > [i915#1779]: https://gitlab.freedesktop.org/drm/intel/issues/1779 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8655 -> Patchwork_18009 > > CI-20190529: 20190529 > CI_DRM_8655: 25d43cec6c2200a9ebe8a8b0923b27b164a6f424 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18009: c95fdf71011e7df7708cea81e3736b24fb8f5189 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/index.html From gregkh at linuxfoundation.org Tue Jun 23 11:54:15 2020 From: gregkh at linuxfoundation.org (Greg KH) Date: Tue, 23 Jun 2020 13:54:15 +0200 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Make Wa_14010229206 permanent In-Reply-To: <20200619201404.GI334084@intel.com> References: <20200618202701.729-1-rodrigo.vivi@intel.com> <20200619080900.GD8425@kroah.com> <20200619201404.GI334084@intel.com> Message-ID: <20200623115415.GB1966723@kroah.com> On Fri, Jun 19, 2020 at 01:14:04PM -0700, Rodrigo Vivi wrote: > On Fri, Jun 19, 2020 at 10:09:00AM +0200, Greg KH wrote: > > On Thu, Jun 18, 2020 at 01:27:00PM -0700, Rodrigo Vivi wrote: > > > From: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> > > > > > > commit 63d0f3ea8ebb67160eca281320d255c72b0cb51a upstream. > > > > > > This workaround now applies to all steppings, not just A0. > > > Wa_1409085225 is a temporary A0-only W/A however it is > > > identical to Wa_14010229206 and hence the combined workaround > > > is made permanent. > > > Bspec: 52890 > > > > > > Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri at intel.com> > > > Tested-by: Rafael Antognolli <rafael.antognolli at intel.com> > > > Reviewed-by: Matt Roper <matthew.d.roper at intel.com> > > > [mattrope: added missing blank line] > > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > > > Link: https://patchwork.freedesktop.org/patch/msgid/20200326234955.16155-1-swathi.dhanavanthri at intel.com > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com> > > > --- > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++------ > > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > What stable kernel(s) is this backport for? You need to give us a hint > > :) > > It's for 5.7.y only. Sorry for not being clear Thanks, now queued up. greg k-h From patchwork at emeril.freedesktop.org Tue Jun 23 12:48:08 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 12:48:08 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/dp=5Fmst=3A_Enable_VC_payload_allocation_after_transcoder?= =?utf-8?q?_is_enabled?= In-Reply-To: <20200623082411.3889-1-imre.deak@intel.com> References: <20200623082411.3889-1-imre.deak@intel.com> Message-ID: <159291648828.4210.6579151037024071394@emeril.freedesktop.org> == Series Details == Series: drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled URL : https://patchwork.freedesktop.org/series/78728/ State : success == Summary == CI Bug Log - changes from CI_DRM_8655_full -> Patchwork_18009_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18009_full: ### Piglit changes ### #### Possible regressions #### * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2 (NEW): - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] +7 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2.html * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2 (NEW): - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2.html New tests --------- New tests have been introduced between CI_DRM_8655_full and Patchwork_18009_full: ### New Piglit tests (11) ### * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat3_array3-position-double_dmat3x4_array2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3-int_ivec3_array3: - Statuses : 1 crash(s) - Exec time: [1.00] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3x2_array3-double_dmat3x2_array2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3-float_mat4x2_array3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-int_ivec2-double_dmat3x4: - Statuses : 1 crash(s) - Exec time: [0.84] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-ubyte_uint-short_ivec4-double_dmat2: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2: - Statuses : 1 crash(s) - Exec time: [0.92] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-ubyte_uvec2-short_int-position-double_dmat2x4: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-uint_uint_array3-position-double_dmat4x3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s Known issues ------------ Here are the changes found in Patchwork_18009_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-glk: [PASS][3] -> [INCOMPLETE][4] ([i915#58] / [k.org#198133]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk1/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk8/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at gem_exec_schedule@smoketest-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at gem_exec_schedule@smoketest-all.html * igt at gem_vm_create@isolation: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / [i915#95]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl6/igt at gem_vm_create@isolation.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at gem_vm_create@isolation.html * igt at gen9_exec_parse@allowed-all: - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1436] / [i915#716]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at gen9_exec_parse@allowed-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl2/igt at gen9_exec_parse@allowed-all.html - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at gen9_exec_parse@allowed-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at gen9_exec_parse@allowed-all.html * igt at i915_suspend@forcewake: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#636] / [i915#69]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at i915_suspend@forcewake.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at i915_suspend@forcewake.html * igt at kms_big_fb@x-tiled-8bpp-rotate-180: - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: - shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#636]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-rte: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +7 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_cursor@pipe-b-viewport-size-128: - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +13 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl7/igt at kms_plane_cursor@pipe-b-viewport-size-128.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl8/igt at kms_plane_cursor@pipe-b-viewport-size-128.html * igt at kms_plane_lowres@pipe-a-tiling-none: - shard-glk: [PASS][33] -> [FAIL][34] ([i915#899]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_plane_lowres@pipe-a-tiling-none.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk7/igt at kms_plane_lowres@pipe-a-tiling-none.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#1542]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb4/igt at perf@blocking-parameterized.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb3/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_eio@kms: - shard-kbl: [DMESG-WARN][37] ([i915#93] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at gem_eio@kms.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at gem_eio@kms.html * igt at gem_exec_whisper@basic-queues-forked-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at gem_exec_whisper@basic-queues-forked-all.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_big_fb@linear-32bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl1/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +5 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: - shard-glk: [FAIL][47] ([i915#46]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk9/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk1/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_flip@flip-vs-suspend at c-dp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip_tiling@flip-changes-tiling-y: - shard-skl: [FAIL][51] ([i915#699]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-changes-tiling-y.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-changes-tiling-y.html * igt at kms_flip_tiling@flip-to-x-tiled: - shard-skl: [FAIL][53] ([i915#167]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-to-x-tiled.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-to-x-tiled.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html * igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@read-crc-pipe-a: - shard-skl: [FAIL][63] ([i915#53]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_pipe_crc_basic@read-crc-pipe-a.html * igt at kms_plane_multiple@atomic-pipe-b-tiling-yf: - shard-kbl: [FAIL][65] ([i915#1779]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html * igt at vgem_slow@nohang: - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +11 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at vgem_slow@nohang.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at vgem_slow@nohang.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_rpm@gem-execbuf-stress-pc8: - shard-apl: [SKIP][71] ([fdo#109271] / [i915#1635]) -> [SKIP][72] ([fdo#109271]) +4 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html * igt at kms_chamelium@dp-crc-multiple: - shard-apl: [SKIP][73] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_chamelium@dp-crc-multiple.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at kms_chamelium@dp-crc-multiple.html * igt at kms_chamelium@vga-hpd: - shard-apl: [SKIP][75] ([fdo#109271] / [fdo#111827]) -> [SKIP][76] ([fdo#109271] / [fdo#111827] / [i915#1635]) +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_chamelium@vga-hpd.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_chamelium@vga-hpd.html * igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled: - shard-snb: [SKIP][77] ([fdo#109271]) -> [TIMEOUT][78] ([i915#1958]) +5 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html * igt at kms_flip@flip-vs-expired-vblank at a-edp1: - shard-skl: [DMESG-WARN][79] ([i915#1982]) -> [DMESG-FAIL][80] ([i915#1982] / [i915#79]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +6 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][83] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][84] ([i915#1982]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167 [i915#1779]: https://gitlab.freedesktop.org/drm/intel/issues/1779 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8655 -> Patchwork_18009 CI-20190529: 20190529 CI_DRM_8655: 25d43cec6c2200a9ebe8a8b0923b27b164a6f424 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18009: c95fdf71011e7df7708cea81e3736b24fb8f5189 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/index.html From thomas_os at shipmail.org Tue Jun 23 12:57:06 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 14:57:06 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> Message-ID: <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> On 6/23/20 1:22 PM, Thomas Hellstr?m (Intel) wrote: > Hi, Chris, > > On 6/22/20 11:59 AM, Chris Wilson wrote: >> In order to actually handle eviction and what not, we need to process >> all the objects together under a common lock, reservation_ww_class. As >> such, do a memory reservation pass after looking up the object/vma, >> which then feeds into the rest of execbuf [relocation, cmdparsing, >> flushing and ofc execution]. >> >> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >> --- >> ? .../gpu/drm/i915/gem/i915_gem_execbuffer.c??? | 91 ++++++++++++++----- >> ? 1 file changed, 70 insertions(+), 21 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> index 46fcbdf8161c..8db2e013465f 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> @@ -53,10 +53,9 @@ struct eb_vma_array { >> ? ? #define __EXEC_OBJECT_HAS_PIN??????? BIT(31) >> ? #define __EXEC_OBJECT_HAS_FENCE??????? BIT(30) >> -#define __EXEC_OBJECT_HAS_PAGES??????? BIT(29) >> -#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(28) >> -#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(27) >> -#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 27) /* all of the >> above */ >> +#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(29) >> +#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(28) >> +#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 28) /* all of the >> above */ >> ? ? #define __EXEC_HAS_RELOC??? BIT(31) >> ? #define __EXEC_INTERNAL_FLAGS??? (~0u << 31) >> @@ -241,6 +240,8 @@ struct i915_execbuffer { >> ????? struct intel_context *context; /* logical state for the request */ >> ????? struct i915_gem_context *gem_context; /** caller's context */ >> ? +??? struct dma_fence *mm_fence; >> + >> ????? struct i915_request *request; /** our request to build */ >> ????? struct eb_vma *batch; /** identity of the batch obj/vma */ >> ????? struct i915_vma *trampoline; /** trampoline used for chaining */ >> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct >> eb_vma *ev) >> ????? if (ev->flags & __EXEC_OBJECT_HAS_PIN) >> ????????? __i915_vma_unpin(vma); >> ? -??? if (ev->flags & __EXEC_OBJECT_HAS_PAGES) >> -??????? i915_gem_object_unpin_pages(vma->obj); >> - >> -??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | >> -?????????????? __EXEC_OBJECT_HAS_FENCE | >> -?????????????? __EXEC_OBJECT_HAS_PAGES); >> +??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); >> ? } >> ? ? static void eb_vma_array_destroy(struct kref *kref) >> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, >> ????? list_add_tail(&ev->lock_link, &eb->lock); >> ? } >> ? +static int eb_vma_get_pages(struct i915_execbuffer *eb, >> +??????????????? struct eb_vma *ev, >> +??????????????? u64 idx) >> +{ >> +??? struct i915_vma *vma = ev->vma; >> +??? int err; >> + >> +??? /* XXX also preallocate PD for vma */ >> + >> +??? err = ____i915_gem_object_get_pages_async(vma->obj); >> +??? if (err) >> +??????? return err; >> + >> +??? return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); >> +} >> + >> +static int eb_reserve_mm(struct i915_execbuffer *eb) >> +{ >> +??? const u64 idx = eb->context->timeline->fence_context; >> +??? struct ww_acquire_ctx acquire; >> +??? struct eb_vma *ev; >> +??? int err; >> + >> +??? eb->mm_fence = __dma_fence_create_proxy(0, 0); >> +??? if (!eb->mm_fence) >> +??????? return -ENOMEM; > > Question: eb is local to this thread, right, so eb->mm_fence is not > considered "published" yet? > >> + >> +??? ww_acquire_init(&acquire, &reservation_ww_class); >> + >> +??? err = eb_lock_vma(eb, &acquire); >> +??? if (err) >> +??????? goto out; >> + >> +??? ww_acquire_done(&acquire); >> + >> +??? list_for_each_entry(ev, &eb->lock, lock_link) { >> +??????? struct i915_vma *vma = ev->vma; >> + >> +??????? if (err == 0) >> +??????????? err = eb_vma_get_pages(eb, ev, idx); > > I figure this is where you publish the proxy fence? If so, the fence > signaling critical path starts with this loop, and that means any code > we call between here and submission complete (including spawned work > we need to wait for before submission) may not lock the > reservation_ww_class nor (still being discussed) allocate memory. It > looks like i915_pin_vma takes a reservation_ww_class. And all memory > pinning seems to be in the fence critical path as well? And I think even if we at some point end up with the allocation annotation the other way around, allowing memory allocations in fence signalling critical paths, both relocations and userpointer would cause lockdep problems because of mmap_sem->reservation_object->fence_wait (fault handlers, lockdep priming) vs fence_critical->gup/copy_from_user->mmap_sem /Thomas > > /Thomas > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Tue Jun 23 14:01:01 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 15:01:01 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> Message-ID: <159292086189.10607.10450244252436195167@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 13:57:06) > > On 6/23/20 1:22 PM, Thomas Hellstr?m (Intel) wrote: > > Hi, Chris, > > > > On 6/22/20 11:59 AM, Chris Wilson wrote: > >> In order to actually handle eviction and what not, we need to process > >> all the objects together under a common lock, reservation_ww_class. As > >> such, do a memory reservation pass after looking up the object/vma, > >> which then feeds into the rest of execbuf [relocation, cmdparsing, > >> flushing and ofc execution]. > >> > >> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >> --- > >> ? .../gpu/drm/i915/gem/i915_gem_execbuffer.c??? | 91 ++++++++++++++----- > >> ? 1 file changed, 70 insertions(+), 21 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >> index 46fcbdf8161c..8db2e013465f 100644 > >> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >> @@ -53,10 +53,9 @@ struct eb_vma_array { > >> ? ? #define __EXEC_OBJECT_HAS_PIN??????? BIT(31) > >> ? #define __EXEC_OBJECT_HAS_FENCE??????? BIT(30) > >> -#define __EXEC_OBJECT_HAS_PAGES??????? BIT(29) > >> -#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(28) > >> -#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(27) > >> -#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 27) /* all of the > >> above */ > >> +#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(29) > >> +#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(28) > >> +#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 28) /* all of the > >> above */ > >> ? ? #define __EXEC_HAS_RELOC??? BIT(31) > >> ? #define __EXEC_INTERNAL_FLAGS??? (~0u << 31) > >> @@ -241,6 +240,8 @@ struct i915_execbuffer { > >> ????? struct intel_context *context; /* logical state for the request */ > >> ????? struct i915_gem_context *gem_context; /** caller's context */ > >> ? +??? struct dma_fence *mm_fence; > >> + > >> ????? struct i915_request *request; /** our request to build */ > >> ????? struct eb_vma *batch; /** identity of the batch obj/vma */ > >> ????? struct i915_vma *trampoline; /** trampoline used for chaining */ > >> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct > >> eb_vma *ev) > >> ????? if (ev->flags & __EXEC_OBJECT_HAS_PIN) > >> ????????? __i915_vma_unpin(vma); > >> ? -??? if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > >> -??????? i915_gem_object_unpin_pages(vma->obj); > >> - > >> -??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > >> -?????????????? __EXEC_OBJECT_HAS_FENCE | > >> -?????????????? __EXEC_OBJECT_HAS_PAGES); > >> +??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > >> ? } > >> ? ? static void eb_vma_array_destroy(struct kref *kref) > >> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > >> ????? list_add_tail(&ev->lock_link, &eb->lock); > >> ? } > >> ? +static int eb_vma_get_pages(struct i915_execbuffer *eb, > >> +??????????????? struct eb_vma *ev, > >> +??????????????? u64 idx) > >> +{ > >> +??? struct i915_vma *vma = ev->vma; > >> +??? int err; > >> + > >> +??? /* XXX also preallocate PD for vma */ > >> + > >> +??? err = ____i915_gem_object_get_pages_async(vma->obj); > >> +??? if (err) > >> +??????? return err; > >> + > >> +??? return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > >> +} > >> + > >> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >> +{ > >> +??? const u64 idx = eb->context->timeline->fence_context; > >> +??? struct ww_acquire_ctx acquire; > >> +??? struct eb_vma *ev; > >> +??? int err; > >> + > >> +??? eb->mm_fence = __dma_fence_create_proxy(0, 0); > >> +??? if (!eb->mm_fence) > >> +??????? return -ENOMEM; > > > > Question: eb is local to this thread, right, so eb->mm_fence is not > > considered "published" yet? > > > >> + > >> +??? ww_acquire_init(&acquire, &reservation_ww_class); > >> + > >> +??? err = eb_lock_vma(eb, &acquire); > >> +??? if (err) > >> +??????? goto out; > >> + > >> +??? ww_acquire_done(&acquire); > >> + > >> +??? list_for_each_entry(ev, &eb->lock, lock_link) { > >> +??????? struct i915_vma *vma = ev->vma; > >> + > >> +??????? if (err == 0) > >> +??????????? err = eb_vma_get_pages(eb, ev, idx); > > > > I figure this is where you publish the proxy fence? If so, the fence > > signaling critical path starts with this loop, and that means any code > > we call between here and submission complete (including spawned work > > we need to wait for before submission) may not lock the > > reservation_ww_class nor (still being discussed) allocate memory. Yes, at this point we have reserved the memory for the execbuf. > > It > > looks like i915_pin_vma takes a reservation_ww_class. And all memory > > pinning seems to be in the fence critical path as well? Correct, it's not meant to be waiting inside i915_vma_pin(); the intention was to pass in memory, and then we would not need to do the acquire ourselves. As we have just reserved the memory in the above loop, this should not be an issue. I was trying to keep the change minimal and allow incremental conversions. It does however need to add a reference to the object for the work it spawns -- equally though there is an async eviction pass later in execbuf. The challenge here is that the greedy grab of bound vma is faster than doing the unbound eviction handling (even when eviction is not required). > And I think even if we at some point end up with the allocation > annotation the other way around, allowing memory allocations in fence > signalling critical paths, both relocations and userpointer would cause > lockdep problems because of > > mmap_sem->reservation_object->fence_wait (fault handlers, lockdep priming) We don't wait inside mmap_sem. One cannot, you do not know the locking context, so you can only try to reclaim idle space. So you end up with the issue of a multitude of threads each trying to claim the last slice of the aperture/backing storage, not being able to directly reclaim and so have to hit the equivalent of kswapd. > vs > fence_critical->gup/copy_from_user->mmap_sem Which exists today, even the busy wait loop is implicit linkage; you only need userspace to be holding a resource on the gpu to create the deadlock. I've been using the userfault handler to develop test cases where we can arbitrarily block the userptr. -Chris From ville.syrjala at linux.intel.com Tue Jun 23 14:16:06 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 23 Jun 2020 17:16:06 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/display: remove alias to dig_port In-Reply-To: <20200622232821.3093-2-lucas.demarchi@intel.com> References: <20200622232821.3093-1-lucas.demarchi@intel.com> <20200622232821.3093-2-lucas.demarchi@intel.com> Message-ID: <20200623141606.GV6112@intel.com> On Mon, Jun 22, 2020 at 04:28:20PM -0700, Lucas De Marchi wrote: > We don't need intel_dig_port and dig_port to refer to the same thing. > Prefer the latter. > > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > Reviewed-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b..58c9f3d3e7ce 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3382,11 +3382,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, > const struct intel_crtc_state *crtc_state, > const struct drm_connector_state *conn_state) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > int level = intel_ddi_hdmi_level(encoder); > - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > > intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); > intel_ddi_clk_select(encoder, crtc_state); > @@ -3413,7 +3412,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, > > intel_ddi_enable_pipe_clock(encoder, crtc_state); > > - intel_dig_port->set_infoframes(encoder, > + dig_port->set_infoframes(encoder, > crtc_state->has_infoframe, > crtc_state, conn_state); Misalinged parameters staring me in the face here. Didn't trawl the other patch for similar since it's so big. > } > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From lakshminarayana.vudum at intel.com Tue Jun 23 14:17:59 2020 From: lakshminarayana.vudum at intel.com (Vudum, Lakshminarayana) Date: Tue, 23 Jun 2020 14:17:59 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/dp=5Fmst=3A_Enable_VC_payload_allocation_after_transcoder?= =?utf-8?q?_is_enabled?= In-Reply-To: <20200623115309.GA5416@ideak-desk.fi.intel.com> References: <20200623082411.3889-1-imre.deak@intel.com> <159291070631.27519.2625554200756771836@emeril.freedesktop.org> <20200623115309.GA5416@ideak-desk.fi.intel.com> Message-ID: <ec6028a2300a4fdda790ca11444f4aa3@intel.com> Re-reported. -----Original Message----- From: Imre Deak <imre.deak at intel.com> Sent: Tuesday, June 23, 2020 2:53 PM To: intel-gfx at lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum at intel.com> Subject: Re: ? Fi.CI.IGT: failure for drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled Hi Lakshmi, On Tue, Jun 23, 2020 at 11:11:46AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled > URL : https://patchwork.freedesktop.org/series/78728/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8655_full -> Patchwork_18009_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_18009_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_18009_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_18009_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: > - shard-kbl: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/ig > t at kms_flip@flip-vs-suspend-interruptible at c-dp1.html Looks unrelated, since no MST on this machine, and it's probably: https://gitlab.freedesktop.org/drm/intel/-/issues/636 > > > > ### Piglit changes ### > > #### Possible regressions #### > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2 (NEW): > - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +7 similar issues > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g > 7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float > _mat4x2_array3-double_dmat3x2.html > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2 (NEW): > - {pig-icl-1065g7}: NOTRUN -> [CRASH][4] +2 similar issues > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g > 7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_ > uvec2_array3-double_dvec3_array2.html > > > New tests > --------- > > New tests have been introduced between CI_DRM_8655_full and Patchwork_18009_full: > > ### New Piglit tests (11) ### > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat3_array3-position-double_dmat3x4_array2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3-int_ivec3_array3: > - Statuses : 1 crash(s) > - Exec time: [1.00] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3x2_array3-double_dmat3x2_array2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3-float_mat4x2_array3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-int_ivec2-double_dmat3x4: > - Statuses : 1 crash(s) > - Exec time: [0.84] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-ubyte_uint-short_ivec4-double_dmat2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2: > - Statuses : 1 crash(s) > - Exec time: [0.92] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-ubyte_uvec2-short_int-position-double_dmat2x4: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-uint_uint_array3-position-double_dmat4x3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > > > Known issues > ------------ > > Here are the changes found in Patchwork_18009_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_isolation@preservation-s3 at vecs0: > - shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#58] / [k.org#198133]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk1/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk8/ig > t at gem_ctx_isolation@preservation-s3 at vecs0.html > > * igt at gem_exec_schedule@smoketest-all: > - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95]) +1 similar issue > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at gem_exec_schedule@smoketest-all.html > [8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/ig > t at gem_exec_schedule@smoketest-all.html > > * igt at gem_vm_create@isolation: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#95]) +16 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl6/igt at gem_vm_create@isolation.html > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/ig > t at gem_vm_create@isolation.html > > * igt at gen9_exec_parse@allowed-all: > - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at gen9_exec_parse@allowed-all.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl2/igt at gen9_exec_parse@allowed-all.html > - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#1436] / [i915#716]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at gen9_exec_parse@allowed-all.html > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/ig > t at gen9_exec_parse@allowed-all.html > > * igt at i915_suspend@forcewake: > - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#636] / [i915#69]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at i915_suspend@forcewake.html > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/ig > t at i915_suspend@forcewake.html > > * igt at kms_big_fb@x-tiled-8bpp-rotate-180: > - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html > [18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl4/ig > t at kms_big_fb@x-tiled-8bpp-rotate-180.html > > * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: > - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > [20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/ig > t at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: > - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html > [22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb6/i > gt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.ht > ml > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-rte: > - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html > [24]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb5/i > gt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html > > * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: > - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) +1 similar issue > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html > [26]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/ig > t at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html > > * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: > - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +7 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > [28]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/ig > t at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [30]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/ig > t at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_plane_cursor@pipe-b-viewport-size-128: > - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +13 similar issues > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl7/igt at kms_plane_cursor@pipe-b-viewport-size-128.html > [32]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl8/ig > t at kms_plane_cursor@pipe-b-viewport-size-128.html > > * igt at kms_plane_lowres@pipe-a-tiling-none: > - shard-glk: [PASS][33] -> [FAIL][34] ([i915#899]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_plane_lowres@pipe-a-tiling-none.html > [34]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk7/ig > t at kms_plane_lowres@pipe-a-tiling-none.html > > * igt at perf@blocking-parameterized: > - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#1542]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb4/igt at perf@blocking-parameterized.html > [36]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb3/i > gt at perf@blocking-parameterized.html > > > #### Possible fixes #### > > * igt at gem_eio@kms: > - shard-kbl: [DMESG-WARN][37] ([i915#93] / [i915#95]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at gem_eio@kms.html > [38]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/ig > t at gem_eio@kms.html > > * igt at gem_exec_whisper@basic-queues-forked-all: > - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html > [40]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/ig > t at gem_exec_whisper@basic-queues-forked-all.html > > * igt at kms_big_fb@linear-32bpp-rotate-180: > - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_big_fb@linear-32bpp-rotate-180.html > [42]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl1/ig > t at kms_big_fb@linear-32bpp-rotate-180.html > > * igt at kms_big_fb@x-tiled-64bpp-rotate-0: > - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html > [44]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/ig > t at kms_big_fb@x-tiled-64bpp-rotate-0.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: > - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +5 similar issues > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html > [46]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl10/i > gt at kms_big_fb@yf-tiled-32bpp-rotate-270.html > > * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: > - shard-glk: [FAIL][47] ([i915#46]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk9/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > [48]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk1/ig > t at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > > * igt at kms_flip@flip-vs-suspend at c-dp1: > - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_flip@flip-vs-suspend at c-dp1.html > [50]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/ig > t at kms_flip@flip-vs-suspend at c-dp1.html > > * igt at kms_flip_tiling@flip-changes-tiling-y: > - shard-skl: [FAIL][51] ([i915#699]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-changes-tiling-y.html > [52]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/ig > t at kms_flip_tiling@flip-changes-tiling-y.html > > * igt at kms_flip_tiling@flip-to-x-tiled: > - shard-skl: [FAIL][53] ([i915#167]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-to-x-tiled.html > [54]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/ig > t at kms_flip_tiling@flip-to-x-tiled.html > > * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: > - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html > [56]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl1/ig > t at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html > > * igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt: > - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html > [58]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb7/i > gt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html > > * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: > - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > [60]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/ig > t at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html > [62]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl4/ig > t at kms_hdr@bpc-switch-suspend.html > > * igt at kms_pipe_crc_basic@read-crc-pipe-a: > - shard-skl: [FAIL][63] ([i915#53]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-a.html > [64]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/ig > t at kms_pipe_crc_basic@read-crc-pipe-a.html > > * igt at kms_plane_multiple@atomic-pipe-b-tiling-yf: > - shard-kbl: [FAIL][65] ([i915#1779]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html > [66]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/ig > t at kms_plane_multiple@atomic-pipe-b-tiling-yf.html > > * igt at vgem_slow@nohang: > - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +11 similar issues > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at vgem_slow@nohang.html > [68]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/ig > t at vgem_slow@nohang.html > > > #### Warnings #### > > * igt at gem_exec_reloc@basic-concurrent16: > - shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html > [70]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/ig > t at gem_exec_reloc@basic-concurrent16.html > > * igt at i915_pm_rpm@gem-execbuf-stress-pc8: > - shard-apl: [SKIP][71] ([fdo#109271] / [i915#1635]) -> [SKIP][72] ([fdo#109271]) +4 similar issues > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html > [72]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/ig > t at i915_pm_rpm@gem-execbuf-stress-pc8.html > > * igt at kms_chamelium@dp-crc-multiple: > - shard-apl: [SKIP][73] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_chamelium@dp-crc-multiple.html > [74]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/ig > t at kms_chamelium@dp-crc-multiple.html > > * igt at kms_chamelium@vga-hpd: > - shard-apl: [SKIP][75] ([fdo#109271] / [fdo#111827]) -> [SKIP][76] ([fdo#109271] / [fdo#111827] / [i915#1635]) +2 similar issues > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_chamelium@vga-hpd.html > [76]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/ig > t at kms_chamelium@vga-hpd.html > > * igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled: > - shard-snb: [SKIP][77] ([fdo#109271]) -> [TIMEOUT][78] ([i915#1958]) +5 similar issues > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html > [78]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/ig > t at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html > > * igt at kms_flip@flip-vs-expired-vblank at a-edp1: > - shard-skl: [DMESG-WARN][79] ([i915#1982]) -> [DMESG-FAIL][80] ([i915#1982] / [i915#79]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html > [80]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl9/ig > t at kms_flip@flip-vs-expired-vblank at a-edp1.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: > - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +6 similar issues > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > [82]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/ig > t at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [DMESG-FAIL][83] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][84] ([i915#1982]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [84]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/ig > t at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167 > [i915#1779]: https://gitlab.freedesktop.org/drm/intel/issues/1779 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8655 -> Patchwork_18009 > > CI-20190529: 20190529 > CI_DRM_8655: 25d43cec6c2200a9ebe8a8b0923b27b164a6f424 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18009: c95fdf71011e7df7708cea81e3736b24fb8f5189 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/index.html --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:18 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:18 +0200 Subject: [Intel-gfx] [PATCH 01/26] Revert "drm/i915/gem: Async GPU relocations only" Message-ID: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> This reverts commit 9e0f9464e2ab36b864359a59b0e9058fdef0ce47, and related commit 7ac2d2536dfa7 ("drm/i915/gem: Delete unused code"). Breaks the execbuf ww locking series. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 314 ++++++++++++++++-- .../i915/gem/selftests/i915_gem_execbuffer.c | 21 +- 2 files changed, 308 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..ef488acf44db 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -45,6 +45,13 @@ struct eb_vma_array { struct eb_vma vma[]; }; +enum { + FORCE_CPU_RELOC = 1, + FORCE_GTT_RELOC, + FORCE_GPU_RELOC, +#define DBG_FORCE_RELOC 0 /* choose one of the above! */ +}; + #define __EXEC_OBJECT_HAS_PIN BIT(31) #define __EXEC_OBJECT_HAS_FENCE BIT(30) #define __EXEC_OBJECT_NEEDS_MAP BIT(29) @@ -253,6 +260,8 @@ struct i915_execbuffer { */ struct reloc_cache { struct drm_mm_node node; /** temporary GTT binding */ + unsigned long vaddr; /** Current kmap address */ + unsigned long page; /** Currently mapped page index */ unsigned int gen; /** Cached value of INTEL_GEN */ bool use_64bit_reloc : 1; bool has_llc : 1; @@ -596,6 +605,23 @@ eb_add_vma(struct i915_execbuffer *eb, } } +static inline int use_cpu_reloc(const struct reloc_cache *cache, + const struct drm_i915_gem_object *obj) +{ + if (!i915_gem_object_has_struct_page(obj)) + return false; + + if (DBG_FORCE_RELOC == FORCE_CPU_RELOC) + return true; + + if (DBG_FORCE_RELOC == FORCE_GTT_RELOC) + return false; + + return (cache->has_llc || + obj->cache_dirty || + obj->cache_level != I915_CACHE_NONE); +} + static int eb_reserve_vma(const struct i915_execbuffer *eb, struct eb_vma *ev, u64 pin_flags) @@ -919,6 +945,8 @@ relocation_target(const struct drm_i915_gem_relocation_entry *reloc, static void reloc_cache_init(struct reloc_cache *cache, struct drm_i915_private *i915) { + cache->page = -1; + cache->vaddr = 0; /* Must be a variable in the struct to allow GCC to unroll. */ cache->gen = INTEL_GEN(i915); cache->has_llc = HAS_LLC(i915); @@ -930,6 +958,25 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->target = NULL; } +static inline void *unmask_page(unsigned long p) +{ + return (void *)(uintptr_t)(p & PAGE_MASK); +} + +static inline unsigned int unmask_flags(unsigned long p) +{ + return p & ~PAGE_MASK; +} + +#define KMAP 0x4 /* after CLFLUSH_FLAGS */ + +static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) +{ + struct drm_i915_private *i915 = + container_of(cache, struct i915_execbuffer, reloc_cache)->i915; + return &i915->ggtt; +} + #define RELOC_TAIL 4 static int reloc_gpu_chain(struct reloc_cache *cache) @@ -1042,6 +1089,181 @@ static int reloc_gpu_flush(struct reloc_cache *cache) return err; } +static void reloc_cache_reset(struct reloc_cache *cache) +{ + void *vaddr; + + if (!cache->vaddr) + return; + + vaddr = unmask_page(cache->vaddr); + if (cache->vaddr & KMAP) { + if (cache->vaddr & CLFLUSH_AFTER) + mb(); + + kunmap_atomic(vaddr); + i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); + } else { + struct i915_ggtt *ggtt = cache_to_ggtt(cache); + + intel_gt_flush_ggtt_writes(ggtt->vm.gt); + io_mapping_unmap_atomic((void __iomem *)vaddr); + + if (drm_mm_node_allocated(&cache->node)) { + ggtt->vm.clear_range(&ggtt->vm, + cache->node.start, + cache->node.size); + mutex_lock(&ggtt->vm.mutex); + drm_mm_remove_node(&cache->node); + mutex_unlock(&ggtt->vm.mutex); + } else { + i915_vma_unpin((struct i915_vma *)cache->node.mm); + } + } + + cache->vaddr = 0; + cache->page = -1; +} + +static void *reloc_kmap(struct drm_i915_gem_object *obj, + struct reloc_cache *cache, + unsigned long page) +{ + void *vaddr; + + if (cache->vaddr) { + kunmap_atomic(unmask_page(cache->vaddr)); + } else { + unsigned int flushes; + int err; + + err = i915_gem_object_prepare_write(obj, &flushes); + if (err) + return ERR_PTR(err); + + BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); + BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); + + cache->vaddr = flushes | KMAP; + cache->node.mm = (void *)obj; + if (flushes) + mb(); + } + + vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj, page)); + cache->vaddr = unmask_flags(cache->vaddr) | (unsigned long)vaddr; + cache->page = page; + + return vaddr; +} + +static void *reloc_iomap(struct drm_i915_gem_object *obj, + struct reloc_cache *cache, + unsigned long page) +{ + struct i915_ggtt *ggtt = cache_to_ggtt(cache); + unsigned long offset; + void *vaddr; + + if (cache->vaddr) { + intel_gt_flush_ggtt_writes(ggtt->vm.gt); + io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); + } else { + struct i915_vma *vma; + int err; + + if (i915_gem_object_is_tiled(obj)) + return ERR_PTR(-EINVAL); + + if (use_cpu_reloc(cache, obj)) + return NULL; + + i915_gem_object_lock(obj); + err = i915_gem_object_set_to_gtt_domain(obj, true); + i915_gem_object_unlock(obj); + if (err) + return ERR_PTR(err); + + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, + PIN_MAPPABLE | + PIN_NONBLOCK /* NOWARN */ | + PIN_NOEVICT); + if (IS_ERR(vma)) { + memset(&cache->node, 0, sizeof(cache->node)); + mutex_lock(&ggtt->vm.mutex); + err = drm_mm_insert_node_in_range + (&ggtt->vm.mm, &cache->node, + PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, + 0, ggtt->mappable_end, + DRM_MM_INSERT_LOW); + mutex_unlock(&ggtt->vm.mutex); + if (err) /* no inactive aperture space, use cpu reloc */ + return NULL; + } else { + cache->node.start = vma->node.start; + cache->node.mm = (void *)vma; + } + } + + offset = cache->node.start; + if (drm_mm_node_allocated(&cache->node)) { + ggtt->vm.insert_page(&ggtt->vm, + i915_gem_object_get_dma_address(obj, page), + offset, I915_CACHE_NONE, 0); + } else { + offset += page << PAGE_SHIFT; + } + + vaddr = (void __force *)io_mapping_map_atomic_wc(&ggtt->iomap, + offset); + cache->page = page; + cache->vaddr = (unsigned long)vaddr; + + return vaddr; +} + +static void *reloc_vaddr(struct drm_i915_gem_object *obj, + struct reloc_cache *cache, + unsigned long page) +{ + void *vaddr; + + if (cache->page == page) { + vaddr = unmask_page(cache->vaddr); + } else { + vaddr = NULL; + if ((cache->vaddr & KMAP) == 0) + vaddr = reloc_iomap(obj, cache, page); + if (!vaddr) + vaddr = reloc_kmap(obj, cache, page); + } + + return vaddr; +} + +static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) +{ + if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { + if (flushes & CLFLUSH_BEFORE) { + clflushopt(addr); + mb(); + } + + *addr = value; + + /* + * Writes to the same cacheline are serialised by the CPU + * (including clflush). On the write path, we only require + * that it hits memory in an orderly fashion and place + * mb barriers at the start and end of the relocation phase + * to ensure ordering of clflush wrt to the system. + */ + if (flushes & CLFLUSH_AFTER) + clflushopt(addr); + } else + *addr = value; +} + static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) { struct drm_i915_gem_object *obj = vma->obj; @@ -1207,6 +1429,17 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, return cmd; } +static inline bool use_reloc_gpu(struct i915_vma *vma) +{ + if (DBG_FORCE_RELOC == FORCE_GPU_RELOC) + return true; + + if (DBG_FORCE_RELOC) + return false; + + return !dma_resv_test_signaled_rcu(vma->resv, true); +} + static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) { struct page *page; @@ -1221,10 +1454,10 @@ static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) return addr + offset_in_page(offset); } -static int __reloc_entry_gpu(struct i915_execbuffer *eb, - struct i915_vma *vma, - u64 offset, - u64 target_addr) +static bool __reloc_entry_gpu(struct i915_execbuffer *eb, + struct i915_vma *vma, + u64 offset, + u64 target_addr) { const unsigned int gen = eb->reloc_cache.gen; unsigned int len; @@ -1240,7 +1473,7 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, batch = reloc_gpu(eb, vma, len); if (IS_ERR(batch)) - return PTR_ERR(batch); + return false; addr = gen8_canonical_addr(vma->node.start + offset); if (gen >= 8) { @@ -1289,21 +1522,55 @@ static int __reloc_entry_gpu(struct i915_execbuffer *eb, *batch++ = target_addr; } - return 0; + return true; +} + +static bool reloc_entry_gpu(struct i915_execbuffer *eb, + struct i915_vma *vma, + u64 offset, + u64 target_addr) +{ + if (eb->reloc_cache.vaddr) + return false; + + if (!use_reloc_gpu(vma)) + return false; + + return __reloc_entry_gpu(eb, vma, offset, target_addr); } static u64 -relocate_entry(struct i915_execbuffer *eb, - struct i915_vma *vma, +relocate_entry(struct i915_vma *vma, const struct drm_i915_gem_relocation_entry *reloc, + struct i915_execbuffer *eb, const struct i915_vma *target) { u64 target_addr = relocation_target(reloc, target); - int err; - - err = __reloc_entry_gpu(eb, vma, reloc->offset, target_addr); - if (err) - return err; + u64 offset = reloc->offset; + + if (!reloc_entry_gpu(eb, vma, offset, target_addr)) { + bool wide = eb->reloc_cache.use_64bit_reloc; + void *vaddr; + +repeat: + vaddr = reloc_vaddr(vma->obj, + &eb->reloc_cache, + offset >> PAGE_SHIFT); + if (IS_ERR(vaddr)) + return PTR_ERR(vaddr); + + GEM_BUG_ON(!IS_ALIGNED(offset, sizeof(u32))); + clflush_write32(vaddr + offset_in_page(offset), + lower_32_bits(target_addr), + eb->reloc_cache.vaddr); + + if (wide) { + offset += sizeof(u32); + target_addr >>= 32; + wide = false; + goto repeat; + } + } return target->node.start | UPDATE; } @@ -1368,7 +1635,8 @@ eb_relocate_entry(struct i915_execbuffer *eb, * If the relocation already has the right value in it, no * more work needs to be done. */ - if (gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) + if (!DBG_FORCE_RELOC && + gen8_canonical_addr(target->vma->node.start) == reloc->presumed_offset) return 0; /* Check that the relocation address is valid... */ @@ -1400,7 +1668,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, ev->flags &= ~EXEC_OBJECT_ASYNC; /* and update the user's relocation entry */ - return relocate_entry(eb, ev->vma, reloc, target->vma); + return relocate_entry(ev->vma, reloc, eb, target->vma); } static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) @@ -1438,8 +1706,10 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) * this is bad and so lockdep complains vehemently. */ copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); - if (unlikely(copied)) - return -EFAULT; + if (unlikely(copied)) { + remain = -EFAULT; + goto out; + } remain -= count; do { @@ -1447,7 +1717,8 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) if (likely(offset == 0)) { } else if ((s64)offset < 0) { - return (int)offset; + remain = (int)offset; + goto out; } else { /* * Note that reporting an error now @@ -1477,8 +1748,9 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) } while (r++, --count); urelocs += ARRAY_SIZE(stack); } while (remain); - - return 0; +out: + reloc_cache_reset(&eb->reloc_cache); + return remain; } static int eb_relocate(struct i915_execbuffer *eb) @@ -2386,7 +2658,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.i915 = i915; eb.file = file; eb.args = args; - if (!(args->flags & I915_EXEC_NO_RELOC)) + if (DBG_FORCE_RELOC || !(args->flags & I915_EXEC_NO_RELOC)) args->flags |= __EXEC_HAS_RELOC; eb.exec = exec; diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 57c14d3340cd..a49016f8ee0d 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -37,14 +37,20 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, return err; /* 8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); - if (err) + if (!__reloc_entry_gpu(eb, vma, + offsets[0] * sizeof(u32), + 0)) { + err = -EIO; goto unpin_vma; + } /* !8-Byte aligned */ - err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); - if (err) + if (!__reloc_entry_gpu(eb, vma, + offsets[1] * sizeof(u32), + 1)) { + err = -EIO; goto unpin_vma; + } /* Skip to the end of the cmd page */ i = PAGE_SIZE / sizeof(u32) - RELOC_TAIL - 1; @@ -54,9 +60,12 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force batch chaining */ - err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); - if (err) + if (!__reloc_entry_gpu(eb, vma, + offsets[2] * sizeof(u32), + 2)) { + err = -EIO; goto unpin_vma; + } GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); base-commit: 24b806b0a1dd38c734e771ece9dd1ab6492bbb96 prerequisite-patch-id: e6315738715ac4ffccaeb4c4bf5a94651fb8da1d -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:19 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:19 +0200 Subject: [Intel-gfx] [PATCH 02/26] drm/i915: Revert relocation chaining commits. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-2-maarten.lankhorst@linux.intel.com> This reverts commit 964a9b0f611ee ("drm/i915/gem: Use chained reloc batches") and commit 0e97fbb080553 ("drm/i915/gem: Use a single chained reloc batches for a single execbuf"). This breaks ww mutex -EDEADLK handling, and we can deal with relocations fine without it. The ww mutexes protect concurrent access to the BO's. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 171 ++++-------------- .../i915/gem/selftests/i915_gem_execbuffer.c | 8 +- 2 files changed, 35 insertions(+), 144 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index ef488acf44db..ea8c668d76e0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -268,9 +268,7 @@ struct i915_execbuffer { bool has_fence : 1; bool needs_unfenced : 1; - struct i915_vma *target; struct i915_request *rq; - struct i915_vma *rq_vma; u32 *rq_cmd; unsigned int rq_size; } reloc_cache; @@ -955,7 +953,7 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; cache->rq = NULL; - cache->target = NULL; + cache->rq_size = 0; } static inline void *unmask_page(unsigned long p) @@ -977,122 +975,29 @@ static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) return &i915->ggtt; } -#define RELOC_TAIL 4 - -static int reloc_gpu_chain(struct reloc_cache *cache) +static void reloc_gpu_flush(struct reloc_cache *cache) { - struct intel_gt_buffer_pool_node *pool; - struct i915_request *rq = cache->rq; - struct i915_vma *batch; - u32 *cmd; - int err; - - pool = intel_gt_get_buffer_pool(rq->engine->gt, PAGE_SIZE); - if (IS_ERR(pool)) - return PTR_ERR(pool); - - batch = i915_vma_instance(pool->obj, rq->context->vm, NULL); - if (IS_ERR(batch)) { - err = PTR_ERR(batch); - goto out_pool; - } - - err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK); - if (err) - goto out_pool; - - GEM_BUG_ON(cache->rq_size + RELOC_TAIL > PAGE_SIZE / sizeof(u32)); - cmd = cache->rq_cmd + cache->rq_size; - *cmd++ = MI_ARB_CHECK; - if (cache->gen >= 8) - *cmd++ = MI_BATCH_BUFFER_START_GEN8; - else if (cache->gen >= 6) - *cmd++ = MI_BATCH_BUFFER_START; - else - *cmd++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; - *cmd++ = lower_32_bits(batch->node.start); - *cmd++ = upper_32_bits(batch->node.start); /* Always 0 for gen<8 */ - i915_gem_object_flush_map(cache->rq_vma->obj); - i915_gem_object_unpin_map(cache->rq_vma->obj); - cache->rq_vma = NULL; - - err = intel_gt_buffer_pool_mark_active(pool, rq); - if (err == 0) { - i915_vma_lock(batch); - err = i915_request_await_object(rq, batch->obj, false); - if (err == 0) - err = i915_vma_move_to_active(batch, rq, 0); - i915_vma_unlock(batch); - } - i915_vma_unpin(batch); - if (err) - goto out_pool; + struct drm_i915_gem_object *obj = cache->rq->batch->obj; - cmd = i915_gem_object_pin_map(batch->obj, - cache->has_llc ? - I915_MAP_FORCE_WB : - I915_MAP_FORCE_WC); - if (IS_ERR(cmd)) { - err = PTR_ERR(cmd); - goto out_pool; - } + GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32)); + cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END; - /* Return with batch mapping (cmd) still pinned */ - cache->rq_cmd = cmd; - cache->rq_size = 0; - cache->rq_vma = batch; + __i915_gem_object_flush_map(obj, 0, sizeof(u32) * (cache->rq_size + 1)); + i915_gem_object_unpin_map(obj); -out_pool: - intel_gt_buffer_pool_put(pool); - return err; -} + intel_gt_chipset_flush(cache->rq->engine->gt); -static unsigned int reloc_bb_flags(const struct reloc_cache *cache) -{ - return cache->gen > 5 ? 0 : I915_DISPATCH_SECURE; -} - -static int reloc_gpu_flush(struct reloc_cache *cache) -{ - struct i915_request *rq; - int err; - - rq = fetch_and_zero(&cache->rq); - if (!rq) - return 0; - - if (cache->rq_vma) { - struct drm_i915_gem_object *obj = cache->rq_vma->obj; - - GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32)); - cache->rq_cmd[cache->rq_size++] = MI_BATCH_BUFFER_END; - - __i915_gem_object_flush_map(obj, - 0, sizeof(u32) * cache->rq_size); - i915_gem_object_unpin_map(obj); - } - - err = 0; - if (rq->engine->emit_init_breadcrumb) - err = rq->engine->emit_init_breadcrumb(rq); - if (!err) - err = rq->engine->emit_bb_start(rq, - rq->batch->node.start, - PAGE_SIZE, - reloc_bb_flags(cache)); - if (err) - i915_request_set_error_once(rq, err); - - intel_gt_chipset_flush(rq->engine->gt); - i915_request_add(rq); - - return err; + i915_request_add(cache->rq); + cache->rq = NULL; } static void reloc_cache_reset(struct reloc_cache *cache) { void *vaddr; + if (cache->rq) + reloc_gpu_flush(cache); + if (!cache->vaddr) return; @@ -1286,6 +1191,7 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) static int __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_cs *engine, + struct i915_vma *vma, unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; @@ -1308,7 +1214,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, goto out_pool; } - batch = i915_vma_instance(pool->obj, eb->context->vm, NULL); + batch = i915_vma_instance(pool->obj, vma->vm, NULL); if (IS_ERR(batch)) { err = PTR_ERR(batch); goto err_unmap; @@ -1344,6 +1250,16 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, if (err) goto err_request; + err = reloc_move_to_gpu(rq, vma); + if (err) + goto err_request; + + err = eb->engine->emit_bb_start(rq, + batch->node.start, PAGE_SIZE, + cache->gen > 5 ? 0 : I915_DISPATCH_SECURE); + if (err) + goto skip_request; + i915_vma_lock(batch); err = i915_request_await_object(rq, batch->obj, false); if (err == 0) @@ -1358,7 +1274,6 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, cache->rq = rq; cache->rq_cmd = cmd; cache->rq_size = 0; - cache->rq_vma = batch; /* Return with batch mapping (cmd) still pinned */ goto out_pool; @@ -1387,9 +1302,12 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, { struct reloc_cache *cache = &eb->reloc_cache; u32 *cmd; - int err; + + if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1)) + reloc_gpu_flush(cache); if (unlikely(!cache->rq)) { + int err; struct intel_engine_cs *engine = eb->engine; if (!reloc_can_use_engine(engine)) { @@ -1398,31 +1316,11 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, return ERR_PTR(-ENODEV); } - err = __reloc_gpu_alloc(eb, engine, len); + err = __reloc_gpu_alloc(eb, engine, vma, len); if (unlikely(err)) return ERR_PTR(err); } - if (vma != cache->target) { - err = reloc_move_to_gpu(cache->rq, vma); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); - return ERR_PTR(err); - } - - cache->target = vma; - } - - if (unlikely(cache->rq_size + len > - PAGE_SIZE / sizeof(u32) - RELOC_TAIL)) { - err = reloc_gpu_chain(cache); - if (unlikely(err)) { - i915_request_set_error_once(cache->rq, err); - return ERR_PTR(err); - } - } - - GEM_BUG_ON(cache->rq_size + len >= PAGE_SIZE / sizeof(u32)); cmd = cache->rq_cmd + cache->rq_size; cache->rq_size += len; @@ -1770,20 +1668,15 @@ static int eb_relocate(struct i915_execbuffer *eb) /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { struct eb_vma *ev; - int flush; list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) - break; + return err; } - - flush = reloc_gpu_flush(&eb->reloc_cache); - if (!err) - err = flush; } - return err; + return 0; } static int eb_move_to_gpu(struct i915_execbuffer *eb) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index a49016f8ee0d..580884cffec3 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -53,13 +53,13 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, } /* Skip to the end of the cmd page */ - i = PAGE_SIZE / sizeof(u32) - RELOC_TAIL - 1; + i = PAGE_SIZE / sizeof(u32) - 1; i -= eb->reloc_cache.rq_size; memset32(eb->reloc_cache.rq_cmd + eb->reloc_cache.rq_size, MI_NOOP, i); eb->reloc_cache.rq_size += i; - /* Force batch chaining */ + /* Force next batch */ if (!__reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2)) { @@ -69,9 +69,7 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); - err = reloc_gpu_flush(&eb->reloc_cache); - if (err) - goto put_rq; + reloc_gpu_flush(&eb->reloc_cache); GEM_BUG_ON(eb->reloc_cache.rq); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:20 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:20 +0200 Subject: [Intel-gfx] [PATCH 03/26] Revert "drm/i915/gem: Drop relocation slowpath". In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-3-maarten.lankhorst@linux.intel.com> This reverts commit 7dc8f1143778 ("drm/i915/gem: Drop relocation slowpath"). We need the slowpath relocation for taking ww-mutex inside the page fault handler, and we will take this mutex when pinning all objects. [mlankhorst: Adjusted for reloc_gpu_flush() changes] Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld at intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 249 +++++++++++++++++- 1 file changed, 248 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index ea8c668d76e0..2b4c210638c1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1603,7 +1603,9 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) * we would try to acquire the struct mutex again. Obviously * this is bad and so lockdep complains vehemently. */ - copied = __copy_from_user(r, urelocs, count * sizeof(r[0])); + pagefault_disable(); + copied = __copy_from_user_inatomic(r, urelocs, count * sizeof(r[0])); + pagefault_enable(); if (unlikely(copied)) { remain = -EFAULT; goto out; @@ -1651,6 +1653,248 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) return remain; } +static int +eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev) +{ + const struct drm_i915_gem_exec_object2 *entry = ev->exec; + struct drm_i915_gem_relocation_entry *relocs = + u64_to_ptr(typeof(*relocs), entry->relocs_ptr); + unsigned int i; + int err; + + for (i = 0; i < entry->relocation_count; i++) { + u64 offset = eb_relocate_entry(eb, ev, &relocs[i]); + + if ((s64)offset < 0) { + err = (int)offset; + goto err; + } + } + err = 0; +err: + reloc_cache_reset(&eb->reloc_cache); + return err; +} + +static int check_relocations(const struct drm_i915_gem_exec_object2 *entry) +{ + const char __user *addr, *end; + unsigned long size; + char __maybe_unused c; + + size = entry->relocation_count; + if (size == 0) + return 0; + + if (size > N_RELOC(ULONG_MAX)) + return -EINVAL; + + addr = u64_to_user_ptr(entry->relocs_ptr); + size *= sizeof(struct drm_i915_gem_relocation_entry); + if (!access_ok(addr, size)) + return -EFAULT; + + end = addr + size; + for (; addr < end; addr += PAGE_SIZE) { + int err = __get_user(c, addr); + if (err) + return err; + } + return __get_user(c, end - 1); +} + +static int eb_copy_relocations(const struct i915_execbuffer *eb) +{ + struct drm_i915_gem_relocation_entry *relocs; + const unsigned int count = eb->buffer_count; + unsigned int i; + int err; + + for (i = 0; i < count; i++) { + const unsigned int nreloc = eb->exec[i].relocation_count; + struct drm_i915_gem_relocation_entry __user *urelocs; + unsigned long size; + unsigned long copied; + + if (nreloc == 0) + continue; + + err = check_relocations(&eb->exec[i]); + if (err) + goto err; + + urelocs = u64_to_user_ptr(eb->exec[i].relocs_ptr); + size = nreloc * sizeof(*relocs); + + relocs = kvmalloc_array(size, 1, GFP_KERNEL); + if (!relocs) { + err = -ENOMEM; + goto err; + } + + /* copy_from_user is limited to < 4GiB */ + copied = 0; + do { + unsigned int len = + min_t(u64, BIT_ULL(31), size - copied); + + if (__copy_from_user((char *)relocs + copied, + (char __user *)urelocs + copied, + len)) + goto end; + + copied += len; + } while (copied < size); + + /* + * As we do not update the known relocation offsets after + * relocating (due to the complexities in lock handling), + * we need to mark them as invalid now so that we force the + * relocation processing next time. Just in case the target + * object is evicted and then rebound into its old + * presumed_offset before the next execbuffer - if that + * happened we would make the mistake of assuming that the + * relocations were valid. + */ + if (!user_access_begin(urelocs, size)) + goto end; + + for (copied = 0; copied < nreloc; copied++) + unsafe_put_user(-1, + &urelocs[copied].presumed_offset, + end_user); + user_access_end(); + + eb->exec[i].relocs_ptr = (uintptr_t)relocs; + } + + return 0; + +end_user: + user_access_end(); +end: + kvfree(relocs); + err = -EFAULT; +err: + while (i--) { + relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr); + if (eb->exec[i].relocation_count) + kvfree(relocs); + } + return err; +} + +static int eb_prefault_relocations(const struct i915_execbuffer *eb) +{ + const unsigned int count = eb->buffer_count; + unsigned int i; + + for (i = 0; i < count; i++) { + int err; + + err = check_relocations(&eb->exec[i]); + if (err) + return err; + } + + return 0; +} + +static noinline int eb_relocate_slow(struct i915_execbuffer *eb) +{ + bool have_copy = false; + struct eb_vma *ev; + int err = 0; + +repeat: + if (signal_pending(current)) { + err = -ERESTARTSYS; + goto out; + } + + /* + * We take 3 passes through the slowpatch. + * + * 1 - we try to just prefault all the user relocation entries and + * then attempt to reuse the atomic pagefault disabled fast path again. + * + * 2 - we copy the user entries to a local buffer here outside of the + * local and allow ourselves to wait upon any rendering before + * relocations + * + * 3 - we already have a local copy of the relocation entries, but + * were interrupted (EAGAIN) whilst waiting for the objects, try again. + */ + if (!err) { + err = eb_prefault_relocations(eb); + } else if (!have_copy) { + err = eb_copy_relocations(eb); + have_copy = err == 0; + } else { + cond_resched(); + err = 0; + } + if (err) + goto out; + + err = mutex_lock_interruptible(&eb->i915->drm.struct_mutex); + if (err) + goto out; + + list_for_each_entry(ev, &eb->relocs, reloc_link) { + if (!have_copy) { + pagefault_disable(); + err = eb_relocate_vma(eb, ev); + pagefault_enable(); + if (err) + break; + } else { + err = eb_relocate_vma_slow(eb, ev); + if (err) + break; + } + } + + reloc_gpu_flush(&eb->reloc_cache); + mutex_unlock(&eb->i915->drm.struct_mutex); + if (err && !have_copy) + goto repeat; + + if (err) + goto err; + + /* + * Leave the user relocations as are, this is the painfully slow path, + * and we want to avoid the complication of dropping the lock whilst + * having buffers reserved in the aperture and so causing spurious + * ENOSPC for random operations. + */ + +err: + if (err == -EAGAIN) + goto repeat; + +out: + if (have_copy) { + const unsigned int count = eb->buffer_count; + unsigned int i; + + for (i = 0; i < count; i++) { + const struct drm_i915_gem_exec_object2 *entry = + &eb->exec[i]; + struct drm_i915_gem_relocation_entry *relocs; + + if (!entry->relocation_count) + continue; + + relocs = u64_to_ptr(typeof(*relocs), entry->relocs_ptr); + kvfree(relocs); + } + } + + return err; +} + static int eb_relocate(struct i915_execbuffer *eb) { int err; @@ -1674,6 +1918,9 @@ static int eb_relocate(struct i915_execbuffer *eb) if (err) return err; } + + if (err) + return eb_relocate_slow(eb); } return 0; -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:21 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:21 +0200 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory eviction. We don't use it yet, but lets start adding the definition first. To use it, we have to pass a non-NULL ww to gem_object_lock, and don't unlock directly. It is done in i915_gem_ww_ctx_fini. Changes since v1: - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- drivers/gpu/drm/i915/i915_gem.h | 11 ++++ drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- .../drm/i915/selftests/intel_memory_region.c | 2 +- 24 files changed, 173 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7457813ef273..e909ccc37a54 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) { - i915_gem_object_lock(vma->obj); + i915_gem_object_lock(vma->obj, NULL); if (flags & PLANE_HAS_FENCE) i915_vma_unpin_fence(vma); i915_gem_object_unpin_from_display_plane(vma); @@ -17112,7 +17112,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, if (!intel_fb->frontbuffer) return -ENOMEM; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); tiling = i915_gem_object_get_tiling(obj); stride = i915_gem_object_get_stride(obj); i915_gem_object_unlock(obj); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c index d3a86a4d5c04..c182091c00ff 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c @@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0); i915_sw_fence_init(&work->wait, clear_pages_work_notify); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_sw_fence_await_reservation(&work->wait, obj->base.resv, NULL, true, 0, I915_FENCE_GFP); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 30c229fcb404..a996583640ee 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx) continue; rcu_read_unlock(); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); list_for_each_entry(lut, &obj->lut_list, obj_link) { if (lut->ctx != ctx) continue; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 2679380159fc..27fddc22a7c6 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_dire if (err) return err; - err = i915_gem_object_lock_interruptible(obj); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) goto out; @@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direct if (err) return err; - err = i915_gem_object_lock_interruptible(obj); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) goto out; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 7f76fc68f498..c0acfc97fae3 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -32,7 +32,7 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) if (!i915_gem_object_is_framebuffer(obj)) return; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); __i915_gem_object_flush_for_display(obj); i915_gem_object_unlock(obj); } @@ -197,7 +197,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (ret) return ret; - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; @@ -536,7 +536,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, if (err) goto out; - err = i915_gem_object_lock_interruptible(obj); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) goto out_unpin; @@ -576,7 +576,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; @@ -630,7 +630,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 2b4c210638c1..391d22051b20 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -813,7 +813,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, if (err == 0) { /* And nor has this handle */ struct drm_i915_gem_object *obj = vma->obj; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); if (idr_find(&eb->file->object_idr, handle) == obj) { list_add(&lut->obj_link, &obj->lut_list); } else { @@ -1083,7 +1083,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, if (use_cpu_reloc(cache, obj)) return NULL; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index b6ec5b50d93b..b59e2d40c347 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -108,7 +108,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) struct i915_lut_handle *lut, *ln; LIST_HEAD(close); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { struct i915_gem_context *ctx = lut->ctx; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 2faa481cc18f..5103067269b0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -110,20 +110,44 @@ i915_gem_object_put(struct drm_i915_gem_object *obj) #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv) -static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj) +static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + bool intr) { - dma_resv_lock(obj->base.resv, NULL); + int ret; + + if (intr) + ret = dma_resv_lock_interruptible(obj->base.resv, ww ? &ww->ctx : NULL); + else + ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL); + + if (!ret && ww) + list_add_tail(&obj->obj_link, &ww->obj_list); + if (ret == -EALREADY) + ret = 0; + + if (ret == -EDEADLK) + ww->contended = obj; + + return ret; } -static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) +static inline int i915_gem_object_lock(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww) { - return dma_resv_trylock(obj->base.resv); + return __i915_gem_object_lock(obj, ww, ww && ww->intr); } -static inline int -i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj) +static inline int i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww) { - return dma_resv_lock_interruptible(obj->base.resv, NULL); + WARN_ON(ww && !ww->intr); + return __i915_gem_object_lock(obj, ww, true); +} + +static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) +{ + return dma_resv_trylock(obj->base.resv); } static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index b1f82a11aef2..3740c0080e38 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -122,6 +122,15 @@ struct drm_i915_gem_object { */ struct list_head lut_list; + /** + * @obj_link: Link into @i915_gem_ww_ctx.obj_list + * + * When we lock this object through i915_gem_object_lock() with a + * context, we add it to the list to ensure we can unlock everything + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. + */ + struct list_head obj_link; + /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; union { diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 3d215164dd5a..40d3e40500fa 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c @@ -84,7 +84,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) spin_unlock_irqrestore(&i915->mm.obj_lock, flags); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); drm_WARN_ON(&i915->drm, i915_gem_object_set_to_gtt_domain(obj, false)); i915_gem_object_unlock(obj); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c index 0158e49bf9bb..65fbf29c4852 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c @@ -249,7 +249,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, * whilst executing a fenced command for an untiled object. */ - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); if (i915_gem_object_is_framebuffer(obj)) { i915_gem_object_unlock(obj); return -EBUSY; diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index 8291ede6902c..eb2011ccb92b 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -947,7 +947,7 @@ static int gpu_write(struct intel_context *ce, { int err; - i915_gem_object_lock(vma->obj); + i915_gem_object_lock(vma->obj, NULL); err = i915_gem_object_set_to_gtt_domain(vma->obj, true); i915_gem_object_unlock(vma->obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index 299c29e9ad86..4e36d4897ea6 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -75,7 +75,7 @@ static int __igt_client_fill(struct intel_engine_cs *engine) if (err) goto err_unpin; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_cpu_domain(obj, false); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 87d7d8aa080f..1de2959b153c 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -82,7 +82,7 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v) u32 __iomem *map; int err = 0; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); i915_gem_object_unlock(ctx->obj); if (err) @@ -115,7 +115,7 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) u32 __iomem *map; int err = 0; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); i915_gem_object_unlock(ctx->obj); if (err) @@ -147,7 +147,7 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v) u32 *map; int err; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_wc_domain(ctx->obj, true); i915_gem_object_unlock(ctx->obj); if (err) @@ -170,7 +170,7 @@ static int wc_get(struct context *ctx, unsigned long offset, u32 *v) u32 *map; int err; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_wc_domain(ctx->obj, false); i915_gem_object_unlock(ctx->obj); if (err) @@ -193,7 +193,7 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) u32 *cs; int err; - i915_gem_object_lock(ctx->obj); + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); i915_gem_object_unlock(ctx->obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index b81978890641..438c15ef2184 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -950,7 +950,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, if (IS_ERR(vma)) return PTR_ERR(vma); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, false); i915_gem_object_unlock(obj); if (err) @@ -1706,7 +1706,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, i915_request_add(rq); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_cpu_domain(obj, false); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 9c7402ce5bf9..9fb95a45bcad 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -103,7 +103,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj, GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) { @@ -188,7 +188,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj, GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) { diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c index 34932871b3a5..a94243dc4c5c 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c @@ -44,7 +44,7 @@ static int mock_phys_object(void *arg) } /* Make the object dirty so that put_pages must do copy back the data */ - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) { diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index febc9e6692ba..61a0532d0f3d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -214,7 +214,7 @@ static int check_whitelist(struct i915_gem_context *ctx, return PTR_ERR(results); err = 0; - i915_gem_object_lock(results); + i915_gem_object_lock(results, NULL); intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */ err = i915_gem_object_set_to_cpu_domain(results, false); i915_gem_object_unlock(results); diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index f1940939260a..943c8d232703 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -2982,7 +2982,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) goto put_obj; } - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); ret = i915_gem_object_set_to_cpu_domain(obj, false); i915_gem_object_unlock(obj); if (ret) { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9aa3066cb75d..1e06752835e5 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -420,7 +420,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, GEM_BUG_ON(!drm_mm_node_allocated(&node)); } - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) goto out_unpin; @@ -619,7 +619,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, GEM_BUG_ON(!drm_mm_node_allocated(&node)); } - ret = i915_gem_object_lock_interruptible(obj); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) goto out_unpin; @@ -1290,7 +1290,7 @@ int i915_gem_freeze_late(struct drm_i915_private *i915) i915_gem_drain_freed_objects(i915); list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) { - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); drm_WARN_ON(&i915->drm, i915_gem_object_set_to_cpu_domain(obj, true)); i915_gem_object_unlock(obj); @@ -1344,6 +1344,52 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) return ret; } +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr) +{ + ww_acquire_init(&ww->ctx, &reservation_ww_class); + INIT_LIST_HEAD(&ww->obj_list); + ww->intr = intr; + ww->contended = NULL; +} + +static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) +{ + struct drm_i915_gem_object *obj; + + while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { + list_del(&obj->obj_link); + i915_gem_object_unlock(obj); + } +} + +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) +{ + i915_gem_ww_ctx_unlock_all(ww); + WARN_ON(ww->contended); + ww_acquire_fini(&ww->ctx); +} + +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww) +{ + int ret = 0; + + if (WARN_ON(!ww->contended)) + return -EINVAL; + + i915_gem_ww_ctx_unlock_all(ww); + if (ww->intr) + ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx); + else + dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx); + + if (!ret) + list_add_tail(&ww->contended->obj_link, &ww->obj_list); + + ww->contended = NULL; + + return ret; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/mock_gem_device.c" #include "selftests/i915_gem.c" diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 1753c84d6c0d..988755dbf4be 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -116,4 +116,15 @@ static inline bool __tasklet_is_scheduled(struct tasklet_struct *t) return test_bit(TASKLET_STATE_SCHED, &t->state); } +struct i915_gem_ww_ctx { + struct ww_acquire_ctx ctx; + struct list_head obj_list; + bool intr; + struct drm_i915_gem_object *contended; +}; + +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx); + #endif /* __I915_GEM_H__ */ diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c index 88d400b9df88..23a6132c5f4e 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c @@ -199,11 +199,52 @@ static int igt_gem_hibernate(void *arg) return err; } +static int igt_gem_ww_ctx(void *arg) +{ + struct drm_i915_private *i915 = arg; + struct drm_i915_gem_object *obj, *obj2; + struct i915_gem_ww_ctx ww; + int err = 0; + + obj = i915_gem_object_create_internal(i915, PAGE_SIZE); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE); + if (IS_ERR(obj)) { + err = PTR_ERR(obj); + goto put1; + } + + i915_gem_ww_ctx_init(&ww, true); +retry: + /* Lock the objects, twice for good measure (-EALREADY handling) */ + err = i915_gem_object_lock(obj, &ww); + if (!err) + err = i915_gem_object_lock_interruptible(obj, &ww); + if (!err) + err = i915_gem_object_lock_interruptible(obj2, &ww); + if (!err) + err = i915_gem_object_lock(obj2, &ww); + + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + i915_gem_object_put(obj2); +put1: + i915_gem_object_put(obj); + return err; +} + int i915_gem_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { SUBTEST(igt_gem_suspend), SUBTEST(igt_gem_hibernate), + SUBTEST(igt_gem_ww_ctx), }; if (intel_gt_is_wedged(&i915->gt)) diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c index af89c7fc8f59..88c5e9acb84c 100644 --- a/drivers/gpu/drm/i915/selftests/i915_vma.c +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c @@ -892,7 +892,7 @@ static int igt_vma_remapped_gtt(void *arg) unsigned int x, y; int err; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); i915_gem_object_unlock(obj); if (err) diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c index 6e80d99048e4..957a7a52def7 100644 --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c @@ -509,7 +509,7 @@ static int igt_lmem_write_cpu(void *arg) if (err) goto out_unpin; - i915_gem_object_lock(obj); + i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_wc_domain(obj, true); i915_gem_object_unlock(obj); if (err) -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:22 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:22 +0200 Subject: [Intel-gfx] [PATCH 05/26] drm/i915: Remove locking from i915_gem_object_prepare_read/write In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-5-maarten.lankhorst@linux.intel.com> Execbuffer submission will perform its own WW locking, and we cannot rely on the implicit lock there. This also makes it clear that the GVT code will get a lockdep splat when multiple batchbuffer shadows need to be performed in the same instance, fix that up. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 20 ++++++------------- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 13 ++++++++++-- drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 - .../gpu/drm/i915/gem/selftests/huge_pages.c | 5 ++++- .../i915/gem/selftests/i915_gem_coherency.c | 14 +++++++++---- .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++++++++--- drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/i915_gem.c | 20 +++++++++++++++++-- 8 files changed, 59 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index c0acfc97fae3..8ebceebd11b0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -576,19 +576,17 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj, NULL); - if (ret) - return ret; + assert_object_held(obj); ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT); if (ret) - goto err_unlock; + return ret; ret = i915_gem_object_pin_pages(obj); if (ret) - goto err_unlock; + return ret; if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || !static_cpu_has(X86_FEATURE_CLFLUSH)) { @@ -616,8 +614,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, err_unpin: i915_gem_object_unpin_pages(obj); -err_unlock: - i915_gem_object_unlock(obj); return ret; } @@ -630,20 +626,18 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, if (!i915_gem_object_has_struct_page(obj)) return -ENODEV; - ret = i915_gem_object_lock_interruptible(obj, NULL); - if (ret) - return ret; + assert_object_held(obj); ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, MAX_SCHEDULE_TIMEOUT); if (ret) - goto err_unlock; + return ret; ret = i915_gem_object_pin_pages(obj); if (ret) - goto err_unlock; + return ret; if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || !static_cpu_has(X86_FEATURE_CLFLUSH)) { @@ -680,7 +674,5 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, err_unpin: i915_gem_object_unpin_pages(obj); -err_unlock: - i915_gem_object_unlock(obj); return ret; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 391d22051b20..f896b1a4b38a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1003,11 +1003,14 @@ static void reloc_cache_reset(struct reloc_cache *cache) vaddr = unmask_page(cache->vaddr); if (cache->vaddr & KMAP) { + struct drm_i915_gem_object *obj = + (struct drm_i915_gem_object *)cache->node.mm; if (cache->vaddr & CLFLUSH_AFTER) mb(); kunmap_atomic(vaddr); - i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); + i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); } else { struct i915_ggtt *ggtt = cache_to_ggtt(cache); @@ -1042,10 +1045,16 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj, unsigned int flushes; int err; - err = i915_gem_object_prepare_write(obj, &flushes); + err = i915_gem_object_lock_interruptible(obj, NULL); if (err) return ERR_PTR(err); + err = i915_gem_object_prepare_write(obj, &flushes); + if (err) { + i915_gem_object_unlock(obj); + return ERR_PTR(err); + } + BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 5103067269b0..11b8e2735071 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -434,7 +434,6 @@ static inline void i915_gem_object_finish_access(struct drm_i915_gem_object *obj) { i915_gem_object_unpin_pages(obj); - i915_gem_object_unlock(obj); } static inline struct intel_engine_cs * diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index eb2011ccb92b..fff11327a8da 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -964,9 +964,10 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) unsigned long n; int err; + i915_gem_object_lock(obj, NULL); err = i915_gem_object_prepare_read(obj, &needs_flush); if (err) - return err; + goto err_unlock; for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) { u32 *ptr = kmap_atomic(i915_gem_object_get_page(obj, n)); @@ -986,6 +987,8 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) } i915_gem_object_finish_access(obj); +err_unlock: + i915_gem_object_unlock(obj); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index 1de2959b153c..dcdfc396f2f8 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -27,9 +27,10 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) u32 *cpu; int err; + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); if (err) - return err; + goto out; page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); @@ -46,7 +47,9 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) kunmap_atomic(map); i915_gem_object_finish_access(ctx->obj); - return 0; +out: + i915_gem_object_unlock(ctx->obj); + return err; } static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) @@ -57,9 +60,10 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) u32 *cpu; int err; + i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); if (err) - return err; + goto out; page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); map = kmap_atomic(page); @@ -73,7 +77,9 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) kunmap_atomic(map); i915_gem_object_finish_access(ctx->obj); - return 0; +out: + i915_gem_object_unlock(ctx->obj); + return err; } static int gtt_set(struct context *ctx, unsigned long offset, u32 v) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 438c15ef2184..76671f587b9d 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -461,9 +461,10 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) unsigned int n, m, need_flush; int err; + i915_gem_object_lock(obj, NULL); err = i915_gem_object_prepare_write(obj, &need_flush); if (err) - return err; + goto out; for (n = 0; n < real_page_count(obj); n++) { u32 *map; @@ -479,7 +480,9 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) i915_gem_object_finish_access(obj); obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU; obj->write_domain = 0; - return 0; +out: + i915_gem_object_unlock(obj); + return err; } static noinline int cpu_check(struct drm_i915_gem_object *obj, @@ -488,9 +491,10 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, unsigned int n, m, needs_flush; int err; + i915_gem_object_lock(obj, NULL); err = i915_gem_object_prepare_read(obj, &needs_flush); if (err) - return err; + goto out_unlock; for (n = 0; n < real_page_count(obj); n++) { u32 *map; @@ -527,6 +531,8 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, } i915_gem_object_finish_access(obj); +out_unlock: + i915_gem_object_unlock(obj); return err; } diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 943c8d232703..d0a599b51bfe 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1923,6 +1923,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) if (ret) goto err_unmap; + i915_gem_object_unlock(bb->obj); INIT_LIST_HEAD(&bb->list); list_add(&bb->list, &s->workload->shadow_bb); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1e06752835e5..33f6f88c8b08 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -335,12 +335,20 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj, u64 remain; int ret; - ret = i915_gem_object_prepare_read(obj, &needs_clflush); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; + ret = i915_gem_object_prepare_read(obj, &needs_clflush); + if (ret) { + i915_gem_object_unlock(obj); + return ret; + } + fence = i915_gem_object_lock_fence(obj); i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); + if (!fence) return -ENOMEM; @@ -734,12 +742,20 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, u64 remain; int ret; - ret = i915_gem_object_prepare_write(obj, &needs_clflush); + ret = i915_gem_object_lock_interruptible(obj, NULL); if (ret) return ret; + ret = i915_gem_object_prepare_write(obj, &needs_clflush); + if (ret) { + i915_gem_object_unlock(obj); + return ret; + } + fence = i915_gem_object_lock_fence(obj); i915_gem_object_finish_access(obj); + i915_gem_object_unlock(obj); + if (!fence) return -ENOMEM; -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:24 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:24 +0200 Subject: [Intel-gfx] [PATCH 07/26] Revert "drm/i915/gem: Split eb_vma into its own allocation" In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-7-maarten.lankhorst@linux.intel.com> This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974. This conflicts with the ww mutex handling, which needs to drop the references after gpu submission anyway, because otherwise we may risk unlocking a BO after first freeing it. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 124 +++++++----------- 1 file changed, 51 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 7cb44915cfc7..2636a130fb57 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -40,11 +40,6 @@ struct eb_vma { u32 handle; }; -struct eb_vma_array { - struct kref kref; - struct eb_vma vma[]; -}; - enum { FORCE_CPU_RELOC = 1, FORCE_GTT_RELOC, @@ -57,6 +52,7 @@ enum { #define __EXEC_OBJECT_NEEDS_MAP BIT(29) #define __EXEC_OBJECT_NEEDS_BIAS BIT(28) #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ +#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) #define __EXEC_HAS_RELOC BIT(31) #define __EXEC_INTERNAL_FLAGS (~0u << 31) @@ -287,7 +283,6 @@ struct i915_execbuffer { */ int lut_size; struct hlist_head *buckets; /** ht for relocation handles */ - struct eb_vma_array *array; }; static int eb_parse(struct i915_execbuffer *eb); @@ -299,62 +294,8 @@ static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) eb->args->batch_len); } -static struct eb_vma_array *eb_vma_array_create(unsigned int count) -{ - struct eb_vma_array *arr; - - arr = kvmalloc(struct_size(arr, vma, count), GFP_KERNEL | __GFP_NOWARN); - if (!arr) - return NULL; - - kref_init(&arr->kref); - arr->vma[0].vma = NULL; - - return arr; -} - -static inline void eb_unreserve_vma(struct eb_vma *ev) -{ - struct i915_vma *vma = ev->vma; - - if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE)) - __i915_vma_unpin_fence(vma); - - if (ev->flags & __EXEC_OBJECT_HAS_PIN) - __i915_vma_unpin(vma); - - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | - __EXEC_OBJECT_HAS_FENCE); -} - -static void eb_vma_array_destroy(struct kref *kref) -{ - struct eb_vma_array *arr = container_of(kref, typeof(*arr), kref); - struct eb_vma *ev = arr->vma; - - while (ev->vma) { - eb_unreserve_vma(ev); - i915_vma_put(ev->vma); - ev++; - } - - kvfree(arr); -} - -static void eb_vma_array_put(struct eb_vma_array *arr) -{ - kref_put(&arr->kref, eb_vma_array_destroy); -} - static int eb_create(struct i915_execbuffer *eb) { - /* Allocate an extra slot for use by the command parser + sentinel */ - eb->array = eb_vma_array_create(eb->buffer_count + 2); - if (!eb->array) - return -ENOMEM; - - eb->vma = eb->array->vma; - if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { unsigned int size = 1 + ilog2(eb->buffer_count); @@ -388,10 +329,8 @@ static int eb_create(struct i915_execbuffer *eb) break; } while (--size); - if (unlikely(!size)) { - eb_vma_array_put(eb->array); + if (unlikely(!size)) return -ENOMEM; - } eb->lut_size = size; } else { @@ -502,6 +441,26 @@ eb_pin_vma(struct i915_execbuffer *eb, return !eb_vma_misplaced(entry, vma, ev->flags); } +static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) +{ + GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); + + if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) + __i915_vma_unpin_fence(vma); + + __i915_vma_unpin(vma); +} + +static inline void +eb_unreserve_vma(struct eb_vma *ev) +{ + if (!(ev->flags & __EXEC_OBJECT_HAS_PIN)) + return; + + __eb_unreserve_vma(ev->vma, ev->flags); + ev->flags &= ~__EXEC_OBJECT_RESERVED; +} + static int eb_validate_vma(struct i915_execbuffer *eb, struct drm_i915_gem_exec_object2 *entry, @@ -944,13 +903,31 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) } } +static void eb_release_vmas(const struct i915_execbuffer *eb) +{ + const unsigned int count = eb->buffer_count; + unsigned int i; + + for (i = 0; i < count; i++) { + struct eb_vma *ev = &eb->vma[i]; + struct i915_vma *vma = ev->vma; + + if (!vma) + break; + + eb->vma[i].vma = NULL; + + if (ev->flags & __EXEC_OBJECT_HAS_PIN) + __eb_unreserve_vma(vma, ev->flags); + + i915_vma_put(vma); + } +} + static void eb_destroy(const struct i915_execbuffer *eb) { GEM_BUG_ON(eb->reloc_cache.rq); - if (eb->array) - eb_vma_array_put(eb->array); - if (eb->lut_size > 0) kfree(eb->buckets); } @@ -2039,12 +2016,9 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) err = i915_vma_move_to_active(vma, eb->request, flags); i915_vma_unlock(vma); - eb_unreserve_vma(ev); } ww_acquire_fini(&acquire); - eb_vma_array_put(fetch_and_zero(&eb->array)); - if (unlikely(err)) goto err_skip; @@ -2340,7 +2314,6 @@ static int eb_parse(struct i915_execbuffer *eb) eb->vma[eb->buffer_count].vma = i915_vma_get(shadow); eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN; eb->batch = &eb->vma[eb->buffer_count++]; - eb->vma[eb->buffer_count].vma = NULL; eb->trampoline = trampoline; eb->batch_start_offset = 0; @@ -2838,6 +2811,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, args->flags |= __EXEC_HAS_RELOC; eb.exec = exec; + eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); + eb.vma[0].vma = NULL; eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; reloc_cache_init(&eb.reloc_cache, eb.i915); @@ -3014,6 +2989,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (batch->private) intel_gt_buffer_pool_put(batch->private); err_vma: + if (eb.exec) + eb_release_vmas(&eb); if (eb.trampoline) i915_vma_unpin(eb.trampoline); eb_unpin_engine(&eb); @@ -3031,7 +3008,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, static size_t eb_element_size(void) { - return sizeof(struct drm_i915_gem_exec_object2); + return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma); } static bool check_buffer_count(size_t count) @@ -3087,7 +3064,7 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, /* Copy in the exec list from userland */ exec_list = kvmalloc_array(count, sizeof(*exec_list), __GFP_NOWARN | GFP_KERNEL); - exec2_list = kvmalloc_array(count, eb_element_size(), + exec2_list = kvmalloc_array(count + 1, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec_list == NULL || exec2_list == NULL) { drm_dbg(&i915->drm, @@ -3165,7 +3142,8 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, if (err) return err; - exec2_list = kvmalloc_array(count, eb_element_size(), + /* Allocate an extra slot for use by the command parser */ + exec2_list = kvmalloc_array(count + 1, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec2_list == NULL) { drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:25 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:25 +0200 Subject: [Intel-gfx] [PATCH 08/26] drm/i915/gem: Make eb_add_lut interruptible wait on object lock. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-8-maarten.lankhorst@linux.intel.com> The lock here should be interruptible, so we can backoff if needed. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 2636a130fb57..aa441af81431 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -774,7 +774,12 @@ static int __eb_add_lut(struct i915_execbuffer *eb, if (err == 0) { /* And nor has this handle */ struct drm_i915_gem_object *obj = vma->obj; - i915_gem_object_lock(obj, NULL); + err = i915_gem_object_lock_interruptible(obj, NULL); + if (err) { + radix_tree_delete(&ctx->handles_vma, handle); + goto unlock; + } + if (idr_find(&eb->file->object_idr, handle) == obj) { list_add(&lut->obj_link, &obj->lut_list); } else { @@ -783,6 +788,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, } i915_gem_object_unlock(obj); } +unlock: mutex_unlock(&ctx->mutex); } if (unlikely(err)) -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:28 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:28 +0200 Subject: [Intel-gfx] [PATCH 11/26] drm/i915: Add ww context handling to context_barrier_task In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-11-maarten.lankhorst@linux.intel.com> This is required if we want to pass a ww context in intel_context_pin and gen6_ppgtt_pin(). Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 55 ++++++++++++++----- .../drm/i915/gem/selftests/i915_gem_context.c | 22 +++----- 2 files changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index a996583640ee..a1e709557704 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1094,6 +1094,7 @@ I915_SELFTEST_DECLARE(static intel_engine_mask_t context_barrier_inject_fault); static int context_barrier_task(struct i915_gem_context *ctx, intel_engine_mask_t engines, bool (*skip)(struct intel_context *ce, void *data), + int (*pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void *data), int (*emit)(struct i915_request *rq, void *data), void (*task)(void *data), void *data) @@ -1101,6 +1102,7 @@ static int context_barrier_task(struct i915_gem_context *ctx, struct context_barrier_task *cb; struct i915_gem_engines_iter it; struct i915_gem_engines *e; + struct i915_gem_ww_ctx ww; struct intel_context *ce; int err = 0; @@ -1138,10 +1140,21 @@ static int context_barrier_task(struct i915_gem_context *ctx, if (skip && skip(ce, data)) continue; - rq = intel_context_create_request(ce); + i915_gem_ww_ctx_init(&ww, true); +retry: + err = intel_context_pin(ce); + if (err) + goto err; + + if (pin) + err = pin(ce, &ww, data); + if (err) + goto err_unpin; + + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); - break; + goto err_unpin; } err = 0; @@ -1151,6 +1164,16 @@ static int context_barrier_task(struct i915_gem_context *ctx, err = i915_active_add_request(&cb->base, rq); i915_request_add(rq); +err_unpin: + intel_context_unpin(ce); +err: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + if (err) break; } @@ -1206,6 +1229,17 @@ static void set_ppgtt_barrier(void *data) i915_vm_close(old); } +static int pin_ppgtt_update(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void *data) +{ + struct i915_address_space *vm = ce->vm; + + if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915)) + /* ppGTT is not part of the legacy context image */ + return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm)); + + return 0; +} + static int emit_ppgtt_update(struct i915_request *rq, void *data) { struct i915_address_space *vm = rq->context->vm; @@ -1262,20 +1296,10 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data) static bool skip_ppgtt_update(struct intel_context *ce, void *data) { - if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) - return true; - if (HAS_LOGICAL_RING_CONTEXTS(ce->engine->i915)) - return false; - - if (!atomic_read(&ce->pin_count)) - return true; - - /* ppGTT is not part of the legacy context image */ - if (gen6_ppgtt_pin(i915_vm_to_ppgtt(ce->vm))) - return true; - - return false; + return !ce->state; + else + return !atomic_read(&ce->pin_count); } static int set_ppgtt(struct drm_i915_file_private *file_priv, @@ -1326,6 +1350,7 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv, */ err = context_barrier_task(ctx, ALL_ENGINES, skip_ppgtt_update, + pin_ppgtt_update, emit_ppgtt_update, set_ppgtt_barrier, old); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 76671f587b9d..1217f7a43069 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1917,8 +1917,8 @@ static int mock_context_barrier(void *arg) return -ENOMEM; counter = 0; - err = context_barrier_task(ctx, 0, - NULL, NULL, mock_barrier_task, &counter); + err = context_barrier_task(ctx, 0, NULL, NULL, NULL, + mock_barrier_task, &counter); if (err) { pr_err("Failed at line %d, err=%d\n", __LINE__, err); goto out; @@ -1930,11 +1930,8 @@ static int mock_context_barrier(void *arg) } counter = 0; - err = context_barrier_task(ctx, ALL_ENGINES, - skip_unused_engines, - NULL, - mock_barrier_task, - &counter); + err = context_barrier_task(ctx, ALL_ENGINES, skip_unused_engines, + NULL, NULL, mock_barrier_task, &counter); if (err) { pr_err("Failed at line %d, err=%d\n", __LINE__, err); goto out; @@ -1954,8 +1951,8 @@ static int mock_context_barrier(void *arg) counter = 0; context_barrier_inject_fault = BIT(RCS0); - err = context_barrier_task(ctx, ALL_ENGINES, - NULL, NULL, mock_barrier_task, &counter); + err = context_barrier_task(ctx, ALL_ENGINES, NULL, NULL, NULL, + mock_barrier_task, &counter); context_barrier_inject_fault = 0; if (err == -ENXIO) err = 0; @@ -1969,11 +1966,8 @@ static int mock_context_barrier(void *arg) goto out; counter = 0; - err = context_barrier_task(ctx, ALL_ENGINES, - skip_unused_engines, - NULL, - mock_barrier_task, - &counter); + err = context_barrier_task(ctx, ALL_ENGINES, skip_unused_engines, + NULL, NULL, mock_barrier_task, &counter); if (err) { pr_err("Failed at line %d, err=%d\n", __LINE__, err); goto out; -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:27 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:27 +0200 Subject: [Intel-gfx] [PATCH 10/26] drm/i915: Use ww locking in intel_renderstate. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-10-maarten.lankhorst@linux.intel.com> We want to start using ww locking in intel_context_pin, for this we need to lock multiple objects, and the single i915_gem_object_lock is not enough. Convert to using ww-waiting, and make sure we always pin intel_context_state, even if we don't have a renderstate object. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 21 +++--- drivers/gpu/drm/i915/gt/intel_renderstate.c | 73 +++++++++++++++------ drivers/gpu/drm/i915/gt/intel_renderstate.h | 9 ++- 3 files changed, 71 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ebc29b6ee86c..24a0e47a2477 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -398,21 +398,20 @@ static int __engines_record_defaults(struct intel_gt *gt) /* We must be able to switch to something! */ GEM_BUG_ON(!engine->kernel_context); - err = intel_renderstate_init(&so, engine); - if (err) - goto out; - ce = intel_context_create(engine); if (IS_ERR(ce)) { err = PTR_ERR(ce); goto out; } - rq = intel_context_create_request(ce); + err = intel_renderstate_init(&so, ce); + if (err) + goto err; + + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); - intel_context_put(ce); - goto out; + goto err_fini; } err = intel_engine_emit_ctx_wa(rq); @@ -426,9 +425,13 @@ static int __engines_record_defaults(struct intel_gt *gt) err_rq: requests[id] = i915_request_get(rq); i915_request_add(rq); - intel_renderstate_fini(&so); - if (err) +err_fini: + intel_renderstate_fini(&so, ce); +err: + if (err) { + intel_context_put(ce); goto out; + } } /* Flush the default context image to memory, and enable powersaving. */ diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index 6db23389e427..3f7881de6a3c 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -27,6 +27,7 @@ #include "i915_drv.h" #include "intel_renderstate.h" +#include "gt/intel_context.h" #include "intel_ring.h" static const struct intel_renderstate_rodata * @@ -157,33 +158,47 @@ static int render_state_setup(struct intel_renderstate *so, #undef OUT_BATCH int intel_renderstate_init(struct intel_renderstate *so, - struct intel_engine_cs *engine) + struct intel_context *ce) { - struct drm_i915_gem_object *obj; + struct intel_engine_cs *engine = ce->engine; + struct drm_i915_gem_object *obj = NULL; int err; memset(so, 0, sizeof(*so)); so->rodata = render_state_get_rodata(engine); - if (!so->rodata) - return 0; + if (so->rodata) { + if (so->rodata->batch_items * 4 > PAGE_SIZE) + return -EINVAL; + + obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); + if (IS_ERR(so->vma)) { + err = PTR_ERR(so->vma); + goto err_obj; + } + } - if (so->rodata->batch_items * 4 > PAGE_SIZE) - return -EINVAL; + i915_gem_ww_ctx_init(&so->ww, true); +retry: + err = intel_context_pin(ce); + if (err) + goto err_fini; - obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); - if (IS_ERR(obj)) - return PTR_ERR(obj); + /* return early if there's nothing to setup */ + if (!err && !so->rodata) + return 0; - so->vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); - if (IS_ERR(so->vma)) { - err = PTR_ERR(so->vma); - goto err_obj; - } + err = i915_gem_object_lock(so->vma->obj, &so->ww); + if (err) + goto err_context; err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH); if (err) - goto err_obj; + goto err_context; err = render_state_setup(so, engine->i915); if (err) @@ -193,8 +208,18 @@ int intel_renderstate_init(struct intel_renderstate *so, err_unpin: i915_vma_unpin(so->vma); +err_context: + intel_context_unpin(ce); +err_fini: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&so->ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&so->ww); err_obj: - i915_gem_object_put(obj); + if (obj) + i915_gem_object_put(obj); so->vma = NULL; return err; } @@ -208,11 +233,9 @@ int intel_renderstate_emit(struct intel_renderstate *so, if (!so->vma) return 0; - i915_vma_lock(so->vma); err = i915_request_await_object(rq, so->vma->obj, false); if (err == 0) err = i915_vma_move_to_active(so->vma, rq, 0); - i915_vma_unlock(so->vma); if (err) return err; @@ -233,7 +256,17 @@ int intel_renderstate_emit(struct intel_renderstate *so, return 0; } -void intel_renderstate_fini(struct intel_renderstate *so) +void intel_renderstate_fini(struct intel_renderstate *so, + struct intel_context *ce) { - i915_vma_unpin_and_release(&so->vma, 0); + if (so->vma) { + i915_vma_unpin(so->vma); + i915_vma_close(so->vma); + } + + intel_context_unpin(ce); + i915_gem_ww_ctx_fini(&so->ww); + + if (so->vma) + i915_gem_object_put(so->vma->obj); } diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.h b/drivers/gpu/drm/i915/gt/intel_renderstate.h index 5700be69a05a..713aa1e86c80 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.h +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.h @@ -25,9 +25,10 @@ #define _INTEL_RENDERSTATE_H_ #include <linux/types.h> +#include "i915_gem.h" struct i915_request; -struct intel_engine_cs; +struct intel_context; struct i915_vma; struct intel_renderstate_rodata { @@ -49,6 +50,7 @@ extern const struct intel_renderstate_rodata gen8_null_state; extern const struct intel_renderstate_rodata gen9_null_state; struct intel_renderstate { + struct i915_gem_ww_ctx ww; const struct intel_renderstate_rodata *rodata; struct i915_vma *vma; u32 batch_offset; @@ -58,9 +60,10 @@ struct intel_renderstate { }; int intel_renderstate_init(struct intel_renderstate *so, - struct intel_engine_cs *engine); + struct intel_context *ce); int intel_renderstate_emit(struct intel_renderstate *so, struct i915_request *rq); -void intel_renderstate_fini(struct intel_renderstate *so); +void intel_renderstate_fini(struct intel_renderstate *so, + struct intel_context *ce); #endif /* _INTEL_RENDERSTATE_H_ */ -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:36 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:36 +0200 Subject: [Intel-gfx] [PATCH 19/26] drm/i915: Dirty hack to fix selftests locking inversion In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-19-maarten.lankhorst@linux.intel.com> Some i915 selftests still use i915_vma_lock() as inner lock, and intel_context_create_request() intel_timeline->mutex as outer lock. Fortunately for selftests this is not an issue, they should be fixed but we can move ahead and cleanify lockdep now. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_context.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index 64948386630f..fe9fff5a63b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -459,6 +459,18 @@ struct i915_request *intel_context_create_request(struct intel_context *ce) rq = i915_request_create(ce); intel_context_unpin(ce); + if (IS_ERR(rq)) + return rq; + + /* + * timeline->mutex should be the inner lock, but is used as outer lock. + * Hack around this to shut up lockdep in selftests.. + */ + lockdep_unpin_lock(&ce->timeline->mutex, rq->cookie); + mutex_release(&ce->timeline->mutex.dep_map, _RET_IP_); + mutex_acquire(&ce->timeline->mutex.dep_map, SINGLE_DEPTH_NESTING, 0, _RET_IP_); + rq->cookie = lockdep_pin_lock(&ce->timeline->mutex); + return rq; } -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:39 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:39 +0200 Subject: [Intel-gfx] [PATCH 22/26] drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-22-maarten.lankhorst@linux.intel.com> Make sure vma_lock is not used as inner lock when kernel context is used, and add ww handling where appropriate. Ensure that execbuf selftests keep passing by using ww handling. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../i915/gem/selftests/i915_gem_coherency.c | 26 ++++++------ .../drm/i915/gem/selftests/i915_gem_mman.c | 41 ++++++++++++++----- drivers/gpu/drm/i915/gt/selftest_rps.c | 30 ++++++++------ drivers/gpu/drm/i915/selftests/i915_request.c | 18 +++++--- 4 files changed, 75 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c index dcdfc396f2f8..7049a6bbc03d 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c @@ -201,25 +201,25 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) i915_gem_object_lock(ctx->obj, NULL); err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); - i915_gem_object_unlock(ctx->obj); if (err) - return err; + goto out_unlock; vma = i915_gem_object_ggtt_pin(ctx->obj, NULL, 0, 0, 0); - if (IS_ERR(vma)) - return PTR_ERR(vma); + if (IS_ERR(vma)) { + err = PTR_ERR(vma); + goto out_unlock; + } rq = intel_engine_create_kernel_request(ctx->engine); if (IS_ERR(rq)) { - i915_vma_unpin(vma); - return PTR_ERR(rq); + err = PTR_ERR(rq); + goto out_unpin; } cs = intel_ring_begin(rq, 4); if (IS_ERR(cs)) { - i915_request_add(rq); - i915_vma_unpin(vma); - return PTR_ERR(cs); + err = PTR_ERR(cs); + goto out_rq; } if (INTEL_GEN(ctx->engine->i915) >= 8) { @@ -240,14 +240,16 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) } intel_ring_advance(rq, cs); - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); - i915_vma_unpin(vma); +out_rq: i915_request_add(rq); +out_unpin: + i915_vma_unpin(vma); +out_unlock: + i915_gem_object_unlock(ctx->obj); return err; } diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 9fb95a45bcad..d27d87a678c8 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -528,31 +528,42 @@ static int make_obj_busy(struct drm_i915_gem_object *obj) for_each_uabi_engine(engine, i915) { struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; int err; vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); if (IS_ERR(vma)) return PTR_ERR(vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(obj, &ww); + if (!err) + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); if (err) - return err; + goto err; rq = intel_engine_create_kernel_request(engine); if (IS_ERR(rq)) { - i915_vma_unpin(vma); - return PTR_ERR(rq); + err = PTR_ERR(rq); + goto err_unpin; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); i915_request_add(rq); +err_unpin: i915_vma_unpin(vma); +err: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); if (err) return err; } @@ -1123,6 +1134,7 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, for_each_uabi_engine(engine, i915) { struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; vma = i915_vma_instance(obj, engine->kernel_context->vm, NULL); if (IS_ERR(vma)) { @@ -1130,9 +1142,13 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, goto out_unmap; } - err = i915_vma_pin(vma, 0, 0, PIN_USER); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(obj, &ww); + if (!err) + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); if (err) - goto out_unmap; + goto out_ww; rq = i915_request_create(engine->kernel_context); if (IS_ERR(rq)) { @@ -1140,11 +1156,9 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, goto out_unpin; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (err == 0) err = i915_vma_move_to_active(vma, rq, 0); - i915_vma_unlock(vma); err = engine->emit_bb_start(rq, vma->node.start, 0, 0); i915_request_get(rq); @@ -1166,6 +1180,13 @@ static int __igt_mmap_gpu(struct drm_i915_private *i915, out_unpin: i915_vma_unpin(vma); +out_ww: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); if (err) goto out_unmap; } diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index bb753f0c12eb..ec1cfcfa0706 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -77,20 +77,20 @@ create_spin_counter(struct intel_engine_cs *engine, vma = i915_vma_instance(obj, vm, NULL); if (IS_ERR(vma)) { - i915_gem_object_put(obj); - return vma; + err = PTR_ERR(vma); + goto err_put; } err = i915_vma_pin(vma, 0, 0, PIN_USER); - if (err) { - i915_vma_put(vma); - return ERR_PTR(err); - } + if (err) + goto err_unlock; + + i915_vma_lock(vma); base = i915_gem_object_pin_map(obj, I915_MAP_WC); if (IS_ERR(base)) { - i915_gem_object_put(obj); - return ERR_CAST(base); + err = PTR_ERR(base); + goto err_unpin; } cs = base; @@ -134,6 +134,14 @@ create_spin_counter(struct intel_engine_cs *engine, *cancel = base + loop; *counter = srm ? memset32(base + end, 0, 1) : NULL; return vma; + +err_unpin: + i915_vma_unpin(vma); +err_unlock: + i915_vma_unlock(vma); +err_put: + i915_gem_object_put(obj); + return ERR_PTR(err); } static u8 wait_for_freq(struct intel_rps *rps, u8 freq, int timeout_ms) @@ -639,7 +647,6 @@ int live_rps_frequency_cs(void *arg) goto err_vma; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (!err) err = i915_vma_move_to_active(vma, rq, 0); @@ -647,7 +654,6 @@ int live_rps_frequency_cs(void *arg) err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, 0); - i915_vma_unlock(vma); i915_request_add(rq); if (err) goto err_vma; @@ -708,6 +714,7 @@ int live_rps_frequency_cs(void *arg) i915_gem_object_flush_map(vma->obj); i915_gem_object_unpin_map(vma->obj); i915_vma_unpin(vma); + i915_vma_unlock(vma); i915_vma_put(vma); st_engine_heartbeat_enable(engine); @@ -781,7 +788,6 @@ int live_rps_frequency_srm(void *arg) goto err_vma; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (!err) err = i915_vma_move_to_active(vma, rq, 0); @@ -789,7 +795,6 @@ int live_rps_frequency_srm(void *arg) err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, 0); - i915_vma_unlock(vma); i915_request_add(rq); if (err) goto err_vma; @@ -849,6 +854,7 @@ int live_rps_frequency_srm(void *arg) i915_gem_object_flush_map(vma->obj); i915_gem_object_unpin_map(vma->obj); i915_vma_unpin(vma); + i915_vma_unlock(vma); i915_vma_put(vma); st_engine_heartbeat_enable(engine); diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..07311437330f 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -862,6 +862,8 @@ static int live_all_engines(void *arg) goto out_free; } + i915_vma_lock(batch); + idx = 0; for_each_uabi_engine(engine, i915) { request[idx] = intel_engine_create_kernel_request(engine); @@ -872,11 +874,9 @@ static int live_all_engines(void *arg) goto out_request; } - i915_vma_lock(batch); err = i915_request_await_object(request[idx], batch->obj, 0); if (err == 0) err = i915_vma_move_to_active(batch, request[idx], 0); - i915_vma_unlock(batch); GEM_BUG_ON(err); err = engine->emit_bb_start(request[idx], @@ -891,6 +891,8 @@ static int live_all_engines(void *arg) idx++; } + i915_vma_unlock(batch); + idx = 0; for_each_uabi_engine(engine, i915) { if (i915_request_completed(request[idx])) { @@ -981,12 +983,13 @@ static int live_sequential_engines(void *arg) goto out_free; } + i915_vma_lock(batch); request[idx] = intel_engine_create_kernel_request(engine); if (IS_ERR(request[idx])) { err = PTR_ERR(request[idx]); pr_err("%s: Request allocation failed for %s with err=%d\n", __func__, engine->name, err); - goto out_request; + goto out_unlock; } if (prev) { @@ -996,16 +999,14 @@ static int live_sequential_engines(void *arg) i915_request_add(request[idx]); pr_err("%s: Request await failed for %s with err=%d\n", __func__, engine->name, err); - goto out_request; + goto out_unlock; } } - i915_vma_lock(batch); err = i915_request_await_object(request[idx], batch->obj, false); if (err == 0) err = i915_vma_move_to_active(batch, request[idx], 0); - i915_vma_unlock(batch); GEM_BUG_ON(err); err = engine->emit_bb_start(request[idx], @@ -1020,6 +1021,11 @@ static int live_sequential_engines(void *arg) prev = request[idx]; idx++; + +out_unlock: + i915_vma_unlock(batch); + if (err) + goto out_request; } idx = 0; -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:40 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:40 +0200 Subject: [Intel-gfx] [PATCH 23/26] drm/i915: Add ww locking to vm_fault_gtt In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-23-maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 51 +++++++++++++++--------- 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index fe27c5b344e3..874fa0489f6d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -283,37 +283,46 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) struct intel_runtime_pm *rpm = &i915->runtime_pm; struct i915_ggtt *ggtt = &i915->ggtt; bool write = area->vm_flags & VM_WRITE; + struct i915_gem_ww_ctx ww; intel_wakeref_t wakeref; struct i915_vma *vma; pgoff_t page_offset; int srcu; int ret; - /* Sanity check that we allow writing into this object */ - if (i915_gem_object_is_readonly(obj) && write) - return VM_FAULT_SIGBUS; - /* We don't use vmf->pgoff since that has the fake offset */ page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; trace_i915_gem_object_fault(obj, page_offset, true, write); - ret = i915_gem_object_pin_pages(obj); + wakeref = intel_runtime_pm_get(rpm); + + i915_gem_ww_ctx_init(&ww, true); +retry: + ret = i915_gem_object_lock(obj, &ww); if (ret) - goto err; + goto err_rpm; - wakeref = intel_runtime_pm_get(rpm); + /* Sanity check that we allow writing into this object */ + if (i915_gem_object_is_readonly(obj) && write) { + ret = -EFAULT; + goto err_rpm; + } - ret = intel_gt_reset_trylock(ggtt->vm.gt, &srcu); + ret = i915_gem_object_pin_pages(obj); if (ret) goto err_rpm; + ret = intel_gt_reset_trylock(ggtt->vm.gt, &srcu); + if (ret) + goto err_pages; + /* Now pin it into the GTT as needed */ - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, - PIN_MAPPABLE | - PIN_NONBLOCK /* NOWARN */ | - PIN_NOEVICT); - if (IS_ERR(vma)) { + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0, + PIN_MAPPABLE | + PIN_NONBLOCK /* NOWARN */ | + PIN_NOEVICT); + if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) { /* Use a partial view if it is bigger than available space */ struct i915_ggtt_view view = compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); @@ -328,11 +337,11 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) * all hope that the hardware is able to track future writes. */ - vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags); - if (IS_ERR(vma)) { + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags); + if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) { flags = PIN_MAPPABLE; view.type = I915_GGTT_VIEW_PARTIAL; - vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags); + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, &view, 0, 0, flags); } /* The entire mappable GGTT is pinned? Unexpected! */ @@ -389,10 +398,16 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) __i915_vma_unpin(vma); err_reset: intel_gt_reset_unlock(ggtt->vm.gt, srcu); +err_pages: + i915_gem_object_unpin_pages(obj); err_rpm: + if (ret == -EDEADLK) { + ret = i915_gem_ww_ctx_backoff(&ww); + if (!ret) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); intel_runtime_pm_put(rpm, wakeref); - i915_gem_object_unpin_pages(obj); -err: return i915_error_to_vmf_fault(ret); } -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:23 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:23 +0200 Subject: [Intel-gfx] [PATCH 06/26] drm/i915: Parse command buffer earlier in eb_relocate(slow) In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> We want to introduce backoff logic, but we need to lock the pool object as well for command parsing. Because of this, we will need backoff logic for the engine pool obj, move the batch validation up slightly to eb_lookup_vmas, and the actual command parsing in a separate function which can get called from execbuf relocation fast and slowpath. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 66 ++++++++++--------- 1 file changed, 36 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index f896b1a4b38a..7cb44915cfc7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -290,6 +290,8 @@ struct i915_execbuffer { struct eb_vma_array *array; }; +static int eb_parse(struct i915_execbuffer *eb); + static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) { return intel_engine_requires_cmd_parser(eb->engine) || @@ -873,6 +875,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) static int eb_lookup_vmas(struct i915_execbuffer *eb) { + struct drm_i915_private *i915 = eb->i915; unsigned int batch = eb_batch_index(eb); unsigned int i; int err = 0; @@ -886,18 +889,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) vma = eb_lookup_vma(eb, eb->exec[i].handle); if (IS_ERR(vma)) { err = PTR_ERR(vma); - break; + goto err; } err = eb_validate_vma(eb, &eb->exec[i], vma); if (unlikely(err)) { i915_vma_put(vma); - break; + goto err; } eb_add_vma(eb, i, batch, vma); } + if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) { + drm_dbg(&i915->drm, + "Attempting to use self-modifying batch buffer\n"); + return -EINVAL; + } + + if (range_overflows_t(u64, + eb->batch_start_offset, eb->batch_len, + eb->batch->vma->size)) { + drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); + return -EINVAL; + } + + if (eb->batch_len == 0) + eb->batch_len = eb->batch->vma->size - eb->batch_start_offset; + + return 0; + +err: eb->vma[i].vma = NULL; return err; } @@ -1809,7 +1831,7 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb) return 0; } -static noinline int eb_relocate_slow(struct i915_execbuffer *eb) +static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) { bool have_copy = false; struct eb_vma *ev; @@ -1872,6 +1894,11 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) if (err) goto err; + /* as last step, parse the command buffer */ + err = eb_parse(eb); + if (err) + goto err; + /* * Leave the user relocations as are, this is the painfully slow path, * and we want to avoid the complication of dropping the lock whilst @@ -1904,7 +1931,7 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) return err; } -static int eb_relocate(struct i915_execbuffer *eb) +static int eb_relocate_parse(struct i915_execbuffer *eb) { int err; @@ -1932,7 +1959,7 @@ static int eb_relocate(struct i915_execbuffer *eb) return eb_relocate_slow(eb); } - return 0; + return eb_parse(eb); } static int eb_move_to_gpu(struct i915_execbuffer *eb) @@ -2870,7 +2897,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_context; - err = eb_relocate(&eb); + err = eb_relocate_parse(&eb); if (err) { /* * If the user expects the execobject.offset and @@ -2883,33 +2910,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } - if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) { - drm_dbg(&i915->drm, - "Attempting to use self-modifying batch buffer\n"); - err = -EINVAL; - goto err_vma; - } - - if (range_overflows_t(u64, - eb.batch_start_offset, eb.batch_len, - eb.batch->vma->size)) { - drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); - err = -EINVAL; - goto err_vma; - } - - if (eb.batch_len == 0) - eb.batch_len = eb.batch->vma->size - eb.batch_start_offset; - - err = eb_parse(&eb); - if (err) - goto err_vma; - /* * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure * batch" bit. Hence we need to pin secure batches into the global gtt. * hsw should have this fixed, but bdw mucks it up again. */ - batch = eb.batch->vma; if (eb.batch_flags & I915_DISPATCH_SECURE) { struct i915_vma *vma; @@ -2923,13 +2927,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, * fitting due to fragmentation. * So this is actually safe. */ - vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); + vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { err = PTR_ERR(vma); goto err_parse; } batch = vma; + } else { + batch = eb.batch->vma; } /* All GPU relocation batches must be submitted prior to the user rq */ -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:26 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:26 +0200 Subject: [Intel-gfx] [PATCH 09/26] drm/i915: Use per object locking in execbuf, v12. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-9-maarten.lankhorst@linux.intel.com> Now that we changed execbuf submission slightly to allow us to do all pinning in one place, we can now simply add ww versions on top of struct_mutex. All we have to do is a separate path for -EDEADLK handling, which needs to unpin all gem bo's before dropping the lock, then starting over. This finally allows us to do parallel submission, but because not all of the pinning code uses the ww ctx yet, we cannot completely drop struct_mutex yet. Changes since v1: - Keep struct_mutex for now. :( Changes since v2: - Make sure we always lock the ww context in slowpath. Changes since v3: - Don't call __eb_unreserve_vma in eb_move_to_gpu now; this can be done on normal unlock path. - Unconditionally release vmas and context. Changes since v4: - Rebased on top of struct_mutex reduction. Changes since v5: - Remove training wheels. Changes since v6: - Fix accidentally broken -ENOSPC handling. Changes since v7: - Handle gt buffer pool better. Changes since v8: - Properly clear variables, to make -EDEADLK handling not BUG. Change since v9: - Fix unpinning fence on pnv and below. Changes since v10: - Make relocation gpu chaining working again. Changes since v11: - Remove relocation chaining, pain to make it work. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 378 ++++++++++-------- .../i915/gem/selftests/i915_gem_execbuffer.c | 62 +-- drivers/gpu/drm/i915/i915_gem.c | 6 + drivers/gpu/drm/i915/i915_gem.h | 1 + 4 files changed, 265 insertions(+), 182 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index aa441af81431..e00ae140e4d0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -249,6 +249,8 @@ struct i915_execbuffer { /** list of vma that have execobj.relocation_count */ struct list_head relocs; + struct i915_gem_ww_ctx ww; + /** * Track the most recently used object for relocations, as we * frequently have to perform multiple relocations within the same @@ -267,14 +269,18 @@ struct i915_execbuffer { struct i915_request *rq; u32 *rq_cmd; unsigned int rq_size; + struct intel_gt_buffer_pool_node *pool; } reloc_cache; + struct intel_gt_buffer_pool_node *reloc_pool; /** relocation pool for -EDEADLK handling */ + u64 invalid_flags; /** Set of execobj.flags that are invalid */ u32 context_flags; /** Set of execobj.flags to insert from the ctx */ u32 batch_start_offset; /** Location within object of batch */ u32 batch_len; /** Length of batch within object */ u32 batch_flags; /** Flags composed for emit_bb_start() */ + struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */ /** * Indicate either the size of the hastable used to resolve @@ -441,23 +447,16 @@ eb_pin_vma(struct i915_execbuffer *eb, return !eb_vma_misplaced(entry, vma, ev->flags); } -static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) -{ - GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); - - if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) - __i915_vma_unpin_fence(vma); - - __i915_vma_unpin(vma); -} - static inline void eb_unreserve_vma(struct eb_vma *ev) { if (!(ev->flags & __EXEC_OBJECT_HAS_PIN)) return; - __eb_unreserve_vma(ev->vma, ev->flags); + if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE)) + __i915_vma_unpin_fence(ev->vma); + + __i915_vma_unpin(ev->vma); ev->flags &= ~__EXEC_OBJECT_RESERVED; } @@ -552,16 +551,6 @@ eb_add_vma(struct i915_execbuffer *eb, eb->batch = ev; } - - if (eb_pin_vma(eb, entry, ev)) { - if (entry->offset != vma->node.start) { - entry->offset = vma->node.start | UPDATE; - eb->args->flags |= __EXEC_HAS_RELOC; - } - } else { - eb_unreserve_vma(ev); - list_add_tail(&ev->bind_link, &eb->unbound); - } } static inline int use_cpu_reloc(const struct reloc_cache *cache, @@ -646,10 +635,6 @@ static int eb_reserve(struct i915_execbuffer *eb) * This avoid unnecessary unbinding of later objects in order to make * room for the earlier objects *unless* we need to defragment. */ - - if (mutex_lock_interruptible(&eb->i915->drm.struct_mutex)) - return -EINTR; - pass = 0; do { list_for_each_entry(ev, &eb->unbound, bind_link) { @@ -657,8 +642,8 @@ static int eb_reserve(struct i915_execbuffer *eb) if (err) break; } - if (!(err == -ENOSPC || err == -EAGAIN)) - break; + if (err != -ENOSPC) + return err; /* Resort *all* the objects into priority order */ INIT_LIST_HEAD(&eb->unbound); @@ -688,13 +673,6 @@ static int eb_reserve(struct i915_execbuffer *eb) } list_splice_tail(&last, &eb->unbound); - if (err == -EAGAIN) { - mutex_unlock(&eb->i915->drm.struct_mutex); - flush_workqueue(eb->i915->mm.userptr_wq); - mutex_lock(&eb->i915->drm.struct_mutex); - continue; - } - switch (pass++) { case 0: break; @@ -705,20 +683,15 @@ static int eb_reserve(struct i915_execbuffer *eb) err = i915_gem_evict_vm(eb->context->vm); mutex_unlock(&eb->context->vm->mutex); if (err) - goto unlock; + return err; break; default: - err = -ENOSPC; - goto unlock; + return -ENOSPC; } pin_flags = PIN_USER; } while (1); - -unlock: - mutex_unlock(&eb->i915->drm.struct_mutex); - return err; } static unsigned int eb_batch_index(const struct i915_execbuffer *eb) @@ -846,7 +819,6 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) int err = 0; INIT_LIST_HEAD(&eb->relocs); - INIT_LIST_HEAD(&eb->unbound); for (i = 0; i < eb->buffer_count; i++) { struct i915_vma *vma; @@ -889,6 +861,48 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) return err; } +static int eb_validate_vmas(struct i915_execbuffer *eb) +{ + unsigned int i; + int err; + + INIT_LIST_HEAD(&eb->unbound); + + for (i = 0; i < eb->buffer_count; i++) { + struct drm_i915_gem_exec_object2 *entry = &eb->exec[i]; + struct eb_vma *ev = &eb->vma[i]; + struct i915_vma *vma = ev->vma; + + err = i915_gem_object_lock(vma->obj, &eb->ww); + if (err) + return err; + + if (eb_pin_vma(eb, entry, ev)) { + if (entry->offset != vma->node.start) { + entry->offset = vma->node.start | UPDATE; + eb->args->flags |= __EXEC_HAS_RELOC; + } + } else { + eb_unreserve_vma(ev); + + list_add_tail(&ev->bind_link, &eb->unbound); + if (drm_mm_node_allocated(&vma->node)) { + err = i915_vma_unbind(vma); + if (err) + return err; + } + } + + GEM_BUG_ON(drm_mm_node_allocated(&vma->node) && + eb_vma_misplaced(&eb->exec[i], vma, ev->flags)); + } + + if (!list_empty(&eb->unbound)) + return eb_reserve(eb); + + return 0; +} + static struct eb_vma * eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) { @@ -909,7 +923,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) } } -static void eb_release_vmas(const struct i915_execbuffer *eb) +static void eb_release_vmas(const struct i915_execbuffer *eb, bool final) { const unsigned int count = eb->buffer_count; unsigned int i; @@ -921,12 +935,10 @@ static void eb_release_vmas(const struct i915_execbuffer *eb) if (!vma) break; - eb->vma[i].vma = NULL; - - if (ev->flags & __EXEC_OBJECT_HAS_PIN) - __eb_unreserve_vma(vma, ev->flags); + eb_unreserve_vma(ev); - i915_vma_put(vma); + if (final) + i915_vma_put(vma); } } @@ -945,6 +957,14 @@ relocation_target(const struct drm_i915_gem_relocation_entry *reloc, return gen8_canonical_addr((int)reloc->delta + target->node.start); } +static void reloc_cache_clear(struct reloc_cache *cache) +{ + cache->rq = NULL; + cache->rq_cmd = NULL; + cache->pool = NULL; + cache->rq_size = 0; +} + static void reloc_cache_init(struct reloc_cache *cache, struct drm_i915_private *i915) { @@ -957,8 +977,7 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->has_fence = cache->gen < 4; cache->needs_unfenced = INTEL_INFO(i915)->unfenced_needs_alignment; cache->node.flags = 0; - cache->rq = NULL; - cache->rq_size = 0; + reloc_cache_clear(cache); } static inline void *unmask_page(unsigned long p) @@ -980,7 +999,23 @@ static inline struct i915_ggtt *cache_to_ggtt(struct reloc_cache *cache) return &i915->ggtt; } -static void reloc_gpu_flush(struct reloc_cache *cache) +static void reloc_cache_put_pool(struct i915_execbuffer *eb, struct reloc_cache *cache) +{ + if (!cache->pool) + return; + + /* + * This is a bit nasty, normally we keep objects locked until the end + * of execbuffer, but we already submit this, and have to unlock before + * dropping the reference. Fortunately we can only hold 1 pool node at + * a time, so this should be harmless. + */ + i915_gem_ww_unlock_single(cache->pool->obj); + intel_gt_buffer_pool_put(cache->pool); + cache->pool = NULL; +} + +static void reloc_gpu_flush(struct i915_execbuffer *eb, struct reloc_cache *cache) { struct drm_i915_gem_object *obj = cache->rq->batch->obj; @@ -993,15 +1028,18 @@ static void reloc_gpu_flush(struct reloc_cache *cache) intel_gt_chipset_flush(cache->rq->engine->gt); i915_request_add(cache->rq); - cache->rq = NULL; + reloc_cache_put_pool(eb, cache); + reloc_cache_clear(cache); + + eb->reloc_pool = NULL; } -static void reloc_cache_reset(struct reloc_cache *cache) +static void reloc_cache_reset(struct reloc_cache *cache, struct i915_execbuffer *eb) { void *vaddr; if (cache->rq) - reloc_gpu_flush(cache); + reloc_gpu_flush(eb, cache); if (!cache->vaddr) return; @@ -1015,7 +1053,6 @@ static void reloc_cache_reset(struct reloc_cache *cache) kunmap_atomic(vaddr); i915_gem_object_finish_access(obj); - i915_gem_object_unlock(obj); } else { struct i915_ggtt *ggtt = cache_to_ggtt(cache); @@ -1050,15 +1087,9 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj, unsigned int flushes; int err; - err = i915_gem_object_lock_interruptible(obj, NULL); - if (err) - return ERR_PTR(err); - err = i915_gem_object_prepare_write(obj, &flushes); - if (err) { - i915_gem_object_unlock(obj); + if (err) return ERR_PTR(err); - } BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); @@ -1097,9 +1128,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, if (use_cpu_reloc(cache, obj)) return NULL; - i915_gem_object_lock(obj, NULL); err = i915_gem_object_set_to_gtt_domain(obj, true); - i915_gem_object_unlock(obj); if (err) return ERR_PTR(err); @@ -1188,7 +1217,7 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) struct drm_i915_gem_object *obj = vma->obj; int err; - i915_vma_lock(vma); + assert_vma_held(vma); if (obj->cache_dirty & ~obj->cache_coherent) i915_gem_clflush_object(obj, 0); @@ -1198,8 +1227,6 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma) if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); - return err; } @@ -1209,15 +1236,22 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, unsigned int len) { struct reloc_cache *cache = &eb->reloc_cache; - struct intel_gt_buffer_pool_node *pool; + struct intel_gt_buffer_pool_node *pool = eb->reloc_pool; struct i915_request *rq; struct i915_vma *batch; u32 *cmd; int err; - pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE); - if (IS_ERR(pool)) - return PTR_ERR(pool); + if (!pool) { + pool = intel_gt_get_buffer_pool(engine->gt, PAGE_SIZE); + if (IS_ERR(pool)) + return PTR_ERR(pool); + } + eb->reloc_pool = NULL; + + err = i915_gem_object_lock(pool->obj, &eb->ww); + if (err) + goto err_pool; cmd = i915_gem_object_pin_map(pool->obj, cache->has_llc ? @@ -1225,7 +1259,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, I915_MAP_FORCE_WC); if (IS_ERR(cmd)) { err = PTR_ERR(cmd); - goto out_pool; + goto err_pool; } batch = i915_vma_instance(pool->obj, vma->vm, NULL); @@ -1274,11 +1308,10 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, if (err) goto skip_request; - i915_vma_lock(batch); + assert_vma_held(batch); err = i915_request_await_object(rq, batch->obj, false); if (err == 0) err = i915_vma_move_to_active(batch, rq, 0); - i915_vma_unlock(batch); if (err) goto skip_request; @@ -1288,9 +1321,10 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, cache->rq = rq; cache->rq_cmd = cmd; cache->rq_size = 0; + cache->pool = pool; /* Return with batch mapping (cmd) still pinned */ - goto out_pool; + return 0; skip_request: i915_request_set_error_once(rq, err); @@ -1300,8 +1334,8 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, i915_vma_unpin(batch); err_unmap: i915_gem_object_unpin_map(pool->obj); -out_pool: - intel_gt_buffer_pool_put(pool); +err_pool: + eb->reloc_pool = pool; return err; } @@ -1318,7 +1352,7 @@ static u32 *reloc_gpu(struct i915_execbuffer *eb, u32 *cmd; if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1)) - reloc_gpu_flush(cache); + reloc_gpu_flush(eb, cache); if (unlikely(!cache->rq)) { int err; @@ -1366,7 +1400,7 @@ static unsigned long vma_phys_addr(struct i915_vma *vma, u32 offset) return addr + offset_in_page(offset); } -static bool __reloc_entry_gpu(struct i915_execbuffer *eb, +static int __reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, u64 offset, u64 target_addr) @@ -1384,7 +1418,9 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, len = 3; batch = reloc_gpu(eb, vma, len); - if (IS_ERR(batch)) + if (batch == ERR_PTR(-EDEADLK)) + return (s64)-EDEADLK; + else if (IS_ERR(batch)) return false; addr = gen8_canonical_addr(vma->node.start + offset); @@ -1437,7 +1473,7 @@ static bool __reloc_entry_gpu(struct i915_execbuffer *eb, return true; } -static bool reloc_entry_gpu(struct i915_execbuffer *eb, +static int reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, u64 offset, u64 target_addr) @@ -1459,8 +1495,12 @@ relocate_entry(struct i915_vma *vma, { u64 target_addr = relocation_target(reloc, target); u64 offset = reloc->offset; + int reloc_gpu = reloc_entry_gpu(eb, vma, offset, target_addr); - if (!reloc_entry_gpu(eb, vma, offset, target_addr)) { + if (reloc_gpu < 0) + return reloc_gpu; + + if (!reloc_gpu) { bool wide = eb->reloc_cache.use_64bit_reloc; void *vaddr; @@ -1663,7 +1703,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct eb_vma *ev) urelocs += ARRAY_SIZE(stack); } while (remain); out: - reloc_cache_reset(&eb->reloc_cache); + reloc_cache_reset(&eb->reloc_cache, eb); return remain; } @@ -1686,7 +1726,7 @@ eb_relocate_vma_slow(struct i915_execbuffer *eb, struct eb_vma *ev) } err = 0; err: - reloc_cache_reset(&eb->reloc_cache); + reloc_cache_reset(&eb->reloc_cache, eb); return err; } @@ -1826,6 +1866,10 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) goto out; } + /* We may process another execbuffer during the unlock... */ + eb_release_vmas(eb, false); + i915_gem_ww_ctx_fini(&eb->ww); + /* * We take 3 passes through the slowpatch. * @@ -1848,12 +1892,20 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) cond_resched(); err = 0; } + + flush_workqueue(eb->i915->mm.userptr_wq); + + i915_gem_ww_ctx_init(&eb->ww, true); if (err) goto out; - err = mutex_lock_interruptible(&eb->i915->drm.struct_mutex); + /* reacquire the objects */ +repeat_validate: + err = eb_validate_vmas(eb); if (err) - goto out; + goto err; + + GEM_BUG_ON(!eb->batch); list_for_each_entry(ev, &eb->relocs, reloc_link) { if (!have_copy) { @@ -1869,8 +1921,9 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) } } - reloc_gpu_flush(&eb->reloc_cache); - mutex_unlock(&eb->i915->drm.struct_mutex); + if (err == -EDEADLK) + goto err; + if (err && !have_copy) goto repeat; @@ -1890,6 +1943,13 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) */ err: + if (err == -EDEADLK) { + eb_release_vmas(eb, false); + err = i915_gem_ww_ctx_backoff(&eb->ww); + if (!err) + goto repeat_validate; + } + if (err == -EAGAIN) goto repeat; @@ -1918,15 +1978,12 @@ static int eb_relocate_parse(struct i915_execbuffer *eb) { int err; - err = eb_lookup_vmas(eb); - if (err) - return err; - - if (!list_empty(&eb->unbound)) { - err = eb_reserve(eb); - if (err) - return err; - } +retry: + err = eb_validate_vmas(eb); + if (err == -EAGAIN) + goto slow; + else if (err) + goto err; /* The objects are in their final locations, apply the relocations. */ if (eb->args->flags & __EXEC_HAS_RELOC) { @@ -1935,48 +1992,49 @@ static int eb_relocate_parse(struct i915_execbuffer *eb) list_for_each_entry(ev, &eb->relocs, reloc_link) { err = eb_relocate_vma(eb, ev); if (err) - return err; + break; } - if (err) - return eb_relocate_slow(eb); + if (err == -EDEADLK) + goto err; + else if (err) + goto slow; } - return eb_parse(eb); + if (!err) + err = eb_parse(eb); + +err: + if (err == -EDEADLK) { + eb_release_vmas(eb, false); + err = i915_gem_ww_ctx_backoff(&eb->ww); + if (!err) + goto retry; + } + + return err; + +slow: + err = eb_relocate_parse_slow(eb); + if (err) + /* + * If the user expects the execobject.offset and + * reloc.presumed_offset to be an exact match, + * as for using NO_RELOC, then we cannot update + * the execobject.offset until we have completed + * relocation. + */ + eb->args->flags &= ~__EXEC_HAS_RELOC; + + return err; } static int eb_move_to_gpu(struct i915_execbuffer *eb) { const unsigned int count = eb->buffer_count; - struct ww_acquire_ctx acquire; - unsigned int i; + unsigned int i = count; int err = 0; - ww_acquire_init(&acquire, &reservation_ww_class); - - for (i = 0; i < count; i++) { - struct eb_vma *ev = &eb->vma[i]; - struct i915_vma *vma = ev->vma; - - err = ww_mutex_lock_interruptible(&vma->resv->lock, &acquire); - if (err == -EDEADLK) { - GEM_BUG_ON(i == 0); - do { - int j = i - 1; - - ww_mutex_unlock(&eb->vma[j].vma->resv->lock); - - swap(eb->vma[i], eb->vma[j]); - } while (--i); - - err = ww_mutex_lock_slow_interruptible(&vma->resv->lock, - &acquire); - } - if (err) - break; - } - ww_acquire_done(&acquire); - while (i--) { struct eb_vma *ev = &eb->vma[i]; struct i915_vma *vma = ev->vma; @@ -2020,10 +2078,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) if (err == 0) err = i915_vma_move_to_active(vma, eb->request, flags); - - i915_vma_unlock(vma); } - ww_acquire_fini(&acquire); if (unlikely(err)) goto err_skip; @@ -2214,36 +2269,26 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, if (err) goto err_commit; - err = dma_resv_lock_interruptible(pw->batch->resv, NULL); - if (err) - goto err_commit; - err = dma_resv_reserve_shared(pw->batch->resv, 1); if (err) - goto err_commit_unlock; + goto err_commit; /* Wait for all writes (and relocs) into the batch to complete */ err = i915_sw_fence_await_reservation(&pw->base.chain, pw->batch->resv, NULL, false, 0, I915_FENCE_GFP); if (err < 0) - goto err_commit_unlock; + goto err_commit; /* Keep the batch alive and unwritten as we parse */ dma_resv_add_shared_fence(pw->batch->resv, &pw->base.dma); - dma_resv_unlock(pw->batch->resv); - /* Force execution to wait for completion of the parser */ - dma_resv_lock(shadow->resv, NULL); dma_resv_add_excl_fence(shadow->resv, &pw->base.dma); - dma_resv_unlock(shadow->resv); dma_fence_work_commit_imm(&pw->base); return 0; -err_commit_unlock: - dma_resv_unlock(pw->batch->resv); err_commit: i915_sw_fence_set_error_once(&pw->base.chain, err); dma_fence_work_commit_imm(&pw->base); @@ -2261,7 +2306,7 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, static int eb_parse(struct i915_execbuffer *eb) { struct drm_i915_private *i915 = eb->i915; - struct intel_gt_buffer_pool_node *pool; + struct intel_gt_buffer_pool_node *pool = eb->batch_pool; struct i915_vma *shadow, *trampoline; unsigned int len; int err; @@ -2284,9 +2329,16 @@ static int eb_parse(struct i915_execbuffer *eb) len += I915_CMD_PARSER_TRAMPOLINE_SIZE; } - pool = intel_gt_get_buffer_pool(eb->engine->gt, len); - if (IS_ERR(pool)) - return PTR_ERR(pool); + if (!pool) { + pool = intel_gt_get_buffer_pool(eb->engine->gt, len); + if (IS_ERR(pool)) + return PTR_ERR(pool); + eb->batch_pool = pool; + } + + err = i915_gem_object_lock(pool->obj, &eb->ww); + if (err) + goto err; shadow = shadow_batch_pin(pool->obj, eb->context->vm, PIN_USER); if (IS_ERR(shadow)) { @@ -2332,7 +2384,6 @@ static int eb_parse(struct i915_execbuffer *eb) err_shadow: i915_vma_unpin(shadow); err: - intel_gt_buffer_pool_put(pool); return err; } @@ -2819,6 +2870,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.exec = exec; eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); eb.vma[0].vma = NULL; + eb.reloc_pool = eb.batch_pool = NULL; eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; reloc_cache_init(&eb.reloc_cache, eb.i915); @@ -2878,6 +2930,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_context; + err = eb_lookup_vmas(&eb); + if (err) { + eb_release_vmas(&eb, true); + goto err_engine; + } + + i915_gem_ww_ctx_init(&eb.ww, true); + err = eb_relocate_parse(&eb); if (err) { /* @@ -2891,6 +2951,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_vma; } + ww_acquire_done(&eb.ww.ctx); + /* * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure * batch" bit. Hence we need to pin secure batches into the global gtt. @@ -2911,7 +2973,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { err = PTR_ERR(vma); - goto err_parse; + goto err_vma; } batch = vma; @@ -2963,8 +3025,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, * to explicitly hold another reference here. */ eb.request->batch = batch; - if (batch->private) - intel_gt_buffer_pool_mark_active(batch->private, eb.request); + if (eb.batch_pool) + intel_gt_buffer_pool_mark_active(eb.batch_pool, eb.request); trace_i915_request_queue(eb.request, eb.batch_flags); err = eb_submit(&eb, batch); @@ -2991,14 +3053,18 @@ i915_gem_do_execbuffer(struct drm_device *dev, err_batch_unpin: if (eb.batch_flags & I915_DISPATCH_SECURE) i915_vma_unpin(batch); -err_parse: - if (batch->private) - intel_gt_buffer_pool_put(batch->private); err_vma: - if (eb.exec) - eb_release_vmas(&eb); + eb_release_vmas(&eb, true); if (eb.trampoline) i915_vma_unpin(eb.trampoline); + WARN_ON(err == -EDEADLK); + i915_gem_ww_ctx_fini(&eb.ww); + + if (eb.batch_pool) + intel_gt_buffer_pool_put(eb.batch_pool); + if (eb.reloc_pool) + intel_gt_buffer_pool_put(eb.reloc_pool); +err_engine: eb_unpin_engine(&eb); err_context: i915_gem_context_put(eb.gem_context); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c index 580884cffec3..2a421c64fafd 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c @@ -32,25 +32,19 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, if (IS_ERR(vma)) return PTR_ERR(vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH); + err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, PIN_USER | PIN_HIGH); if (err) return err; /* 8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[0] * sizeof(u32), - 0)) { - err = -EIO; - goto unpin_vma; - } + err = __reloc_entry_gpu(eb, vma, offsets[0] * sizeof(u32), 0); + if (err <= 0) + goto reloc_err; /* !8-Byte aligned */ - if (!__reloc_entry_gpu(eb, vma, - offsets[1] * sizeof(u32), - 1)) { - err = -EIO; - goto unpin_vma; - } + err = __reloc_entry_gpu(eb, vma, offsets[1] * sizeof(u32), 1); + if (err <= 0) + goto reloc_err; /* Skip to the end of the cmd page */ i = PAGE_SIZE / sizeof(u32) - 1; @@ -60,16 +54,13 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, eb->reloc_cache.rq_size += i; /* Force next batch */ - if (!__reloc_entry_gpu(eb, vma, - offsets[2] * sizeof(u32), - 2)) { - err = -EIO; - goto unpin_vma; - } + err = __reloc_entry_gpu(eb, vma, offsets[2] * sizeof(u32), 2); + if (err <= 0) + goto reloc_err; GEM_BUG_ON(!eb->reloc_cache.rq); rq = i915_request_get(eb->reloc_cache.rq); - reloc_gpu_flush(&eb->reloc_cache); + reloc_gpu_flush(eb, &eb->reloc_cache); GEM_BUG_ON(eb->reloc_cache.rq); err = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE, HZ / 2); @@ -101,6 +92,11 @@ static int __igt_gpu_reloc(struct i915_execbuffer *eb, unpin_vma: i915_vma_unpin(vma); return err; + +reloc_err: + if (!err) + err = -EIO; + goto unpin_vma; } static int igt_gpu_reloc(void *arg) @@ -122,6 +118,8 @@ static int igt_gpu_reloc(void *arg) goto err_scratch; } + intel_gt_pm_get(&eb.i915->gt); + for_each_uabi_engine(eb.engine, eb.i915) { reloc_cache_init(&eb.reloc_cache, eb.i915); memset(map, POISON_INUSE, 4096); @@ -132,15 +130,26 @@ static int igt_gpu_reloc(void *arg) err = PTR_ERR(eb.context); goto err_pm; } + eb.reloc_pool = NULL; - err = intel_context_pin(eb.context); - if (err) - goto err_put; + i915_gem_ww_ctx_init(&eb.ww, false); +retry: + err = intel_context_pin_ww(eb.context, &eb.ww); + if (!err) { + err = __igt_gpu_reloc(&eb, scratch); + + intel_context_unpin(eb.context); + } + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&eb.ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&eb.ww); - err = __igt_gpu_reloc(&eb, scratch); + if (eb.reloc_pool) + intel_gt_buffer_pool_put(eb.reloc_pool); - intel_context_unpin(eb.context); -err_put: intel_context_put(eb.context); err_pm: intel_engine_pm_put(eb.engine); @@ -151,6 +160,7 @@ static int igt_gpu_reloc(void *arg) if (igt_flush_test(eb.i915)) err = -EIO; + intel_gt_pm_put(&eb.i915->gt); err_scratch: i915_gem_object_put(scratch); return err; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 33f6f88c8b08..20653b660b61 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1378,6 +1378,12 @@ static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) } } +void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj) +{ + list_del(&obj->obj_link); + i915_gem_object_unlock(obj); +} + void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) { i915_gem_ww_ctx_unlock_all(ww); diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 988755dbf4be..f6bef9894111 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -126,5 +126,6 @@ struct i915_gem_ww_ctx { void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx); +void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj); #endif /* __I915_GEM_H__ */ -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:29 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:29 +0200 Subject: [Intel-gfx] [PATCH 12/26] drm/i915: Nuke arguments to eb_pin_engine In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-12-maarten.lankhorst@linux.intel.com> Those arguments are already set as eb.file and eb.args, so kill off the extra arguments. This will allow us to move eb_pin_engine() to after we reserved all BO's. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index e00ae140e4d0..83d83884b22d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2605,11 +2605,10 @@ static void eb_unpin_engine(struct i915_execbuffer *eb) } static unsigned int -eb_select_legacy_ring(struct i915_execbuffer *eb, - struct drm_file *file, - struct drm_i915_gem_execbuffer2 *args) +eb_select_legacy_ring(struct i915_execbuffer *eb) { struct drm_i915_private *i915 = eb->i915; + struct drm_i915_gem_execbuffer2 *args = eb->args; unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; if (user_ring_id != I915_EXEC_BSD && @@ -2624,7 +2623,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb, unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK; if (bsd_idx == I915_EXEC_BSD_DEFAULT) { - bsd_idx = gen8_dispatch_bsd_engine(i915, file); + bsd_idx = gen8_dispatch_bsd_engine(i915, eb->file); } else if (bsd_idx >= I915_EXEC_BSD_RING1 && bsd_idx <= I915_EXEC_BSD_RING2) { bsd_idx >>= I915_EXEC_BSD_SHIFT; @@ -2649,18 +2648,16 @@ eb_select_legacy_ring(struct i915_execbuffer *eb, } static int -eb_pin_engine(struct i915_execbuffer *eb, - struct drm_file *file, - struct drm_i915_gem_execbuffer2 *args) +eb_pin_engine(struct i915_execbuffer *eb) { struct intel_context *ce; unsigned int idx; int err; if (i915_gem_context_user_engines(eb->gem_context)) - idx = args->flags & I915_EXEC_RING_MASK; + idx = eb->args->flags & I915_EXEC_RING_MASK; else - idx = eb_select_legacy_ring(eb, file, args); + idx = eb_select_legacy_ring(eb); ce = i915_gem_context_get_engine(eb->gem_context, idx); if (IS_ERR(ce)) @@ -2926,7 +2923,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_destroy; - err = eb_pin_engine(&eb, file, args); + err = eb_pin_engine(&eb); if (unlikely(err)) goto err_context; -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:30 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:30 +0200 Subject: [Intel-gfx] [PATCH 13/26] drm/i915: Pin engine before pinning all objects, v4. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-13-maarten.lankhorst@linux.intel.com> We want to lock all gem objects, including the engine context objects, rework the throttling to ensure that we can do this. Now we only throttle once, but can take eb_pin_engine while acquiring objects. This means we will have to drop the lock to wait. If we don't have to throttle we can still take the fastpath, if not we will take the slowpath and wait for the throttle request while unlocked. The engine has to be pinned as first step, otherwise gpu relocations won't work. Changes since v1: - Only need to get a throttled request in the fastpath, no need for a global flag any more. - Always free the waited request correctly. Changes since v2: - Use intel_engine_pm_get()/put() to keeep engine pool alive during EDEADLK handling. Changes since v3: - Fix small rq leak. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 185 ++++++++++++------ 1 file changed, 129 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 83d83884b22d..9990e4677b9a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -55,7 +55,8 @@ enum { #define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) #define __EXEC_HAS_RELOC BIT(31) -#define __EXEC_INTERNAL_FLAGS (~0u << 31) +#define __EXEC_ENGINE_PINNED BIT(30) +#define __EXEC_INTERNAL_FLAGS (~0u << 30) #define UPDATE PIN_OFFSET_FIXED #define BATCH_OFFSET_BIAS (256*1024) @@ -292,6 +293,9 @@ struct i915_execbuffer { }; static int eb_parse(struct i915_execbuffer *eb); +static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, + bool throttle); +static void eb_unpin_engine(struct i915_execbuffer *eb); static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) { @@ -923,7 +927,7 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) } } -static void eb_release_vmas(const struct i915_execbuffer *eb, bool final) +static void eb_release_vmas(struct i915_execbuffer *eb, bool final) { const unsigned int count = eb->buffer_count; unsigned int i; @@ -940,6 +944,8 @@ static void eb_release_vmas(const struct i915_execbuffer *eb, bool final) if (final) i915_vma_put(vma); } + + eb_unpin_engine(eb); } static void eb_destroy(const struct i915_execbuffer *eb) @@ -1854,7 +1860,8 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb) return 0; } -static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) +static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb, + struct i915_request *rq) { bool have_copy = false; struct eb_vma *ev; @@ -1870,6 +1877,21 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) eb_release_vmas(eb, false); i915_gem_ww_ctx_fini(&eb->ww); + if (rq) { + /* nonblocking is always false */ + if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, + MAX_SCHEDULE_TIMEOUT) < 0) { + i915_request_put(rq); + rq = NULL; + + err = -EINTR; + goto err_relock; + } + + i915_request_put(rq); + rq = NULL; + } + /* * We take 3 passes through the slowpatch. * @@ -1893,14 +1915,25 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) err = 0; } - flush_workqueue(eb->i915->mm.userptr_wq); + if (!err) + flush_workqueue(eb->i915->mm.userptr_wq); +err_relock: i915_gem_ww_ctx_init(&eb->ww, true); if (err) goto out; /* reacquire the objects */ repeat_validate: + rq = eb_pin_engine(eb, false); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + goto err; + } + + /* We didn't throttle, should be NULL */ + GEM_WARN_ON(rq); + err = eb_validate_vmas(eb); if (err) goto err; @@ -1971,14 +2004,49 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) } } + if (rq) + i915_request_put(rq); + return err; } static int eb_relocate_parse(struct i915_execbuffer *eb) { int err; + struct i915_request *rq = NULL; + bool throttle = true; retry: + rq = eb_pin_engine(eb, throttle); + if (IS_ERR(rq)) { + err = PTR_ERR(rq); + rq = NULL; + if (err != -EDEADLK) + return err; + + goto err; + } + + if (rq) { + bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; + + /* Need to drop all locks now for throttling, take slowpath */ + err = i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, 0); + if (err == -ETIME) { + if (nonblock) { + err = -EWOULDBLOCK; + i915_request_put(rq); + goto err; + } + goto slow; + } + i915_request_put(rq); + rq = NULL; + } + + /* only throttle once, even if we didn't need to throttle */ + throttle = false; + err = eb_validate_vmas(eb); if (err == -EAGAIN) goto slow; @@ -2015,7 +2083,7 @@ static int eb_relocate_parse(struct i915_execbuffer *eb) return err; slow: - err = eb_relocate_parse_slow(eb); + err = eb_relocate_parse_slow(eb, rq); if (err) /* * If the user expects the execobject.offset and @@ -2481,7 +2549,7 @@ static const enum intel_engine_id user_ring_map[] = { [I915_EXEC_VEBOX] = VECS0 }; -static struct i915_request *eb_throttle(struct intel_context *ce) +static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce) { struct intel_ring *ring = ce->ring; struct intel_timeline *tl = ce->timeline; @@ -2515,22 +2583,17 @@ static struct i915_request *eb_throttle(struct intel_context *ce) return i915_request_get(rq); } -static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) +static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, bool throttle) { + struct intel_context *ce = eb->context; struct intel_timeline *tl; - struct i915_request *rq; + struct i915_request *rq = NULL; int err; - /* - * ABI: Before userspace accesses the GPU (e.g. execbuffer), report - * EIO if the GPU is already wedged. - */ - err = intel_gt_terminally_wedged(ce->engine->gt); - if (err) - return err; + GEM_BUG_ON(eb->args->flags & __EXEC_ENGINE_PINNED); if (unlikely(intel_context_is_banned(ce))) - return -EIO; + return ERR_PTR(-EIO); /* * Pinning the contexts may generate requests in order to acquire @@ -2539,7 +2602,7 @@ static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) */ err = intel_context_pin(ce); if (err) - return err; + return ERR_PTR(err); /* * Take a local wakeref for preparing to dispatch the execbuf as @@ -2551,45 +2614,17 @@ static int __eb_pin_engine(struct i915_execbuffer *eb, struct intel_context *ce) */ tl = intel_context_timeline_lock(ce); if (IS_ERR(tl)) { - err = PTR_ERR(tl); - goto err_unpin; + intel_context_unpin(ce); + return ERR_CAST(tl); } intel_context_enter(ce); - rq = eb_throttle(ce); - + if (throttle) + rq = eb_throttle(eb, ce); intel_context_timeline_unlock(tl); - if (rq) { - bool nonblock = eb->file->filp->f_flags & O_NONBLOCK; - long timeout; - - timeout = MAX_SCHEDULE_TIMEOUT; - if (nonblock) - timeout = 0; - - timeout = i915_request_wait(rq, - I915_WAIT_INTERRUPTIBLE, - timeout); - i915_request_put(rq); - - if (timeout < 0) { - err = nonblock ? -EWOULDBLOCK : timeout; - goto err_exit; - } - } - - eb->engine = ce->engine; - eb->context = ce; - return 0; - -err_exit: - mutex_lock(&tl->mutex); - intel_context_exit(ce); - intel_context_timeline_unlock(tl); -err_unpin: - intel_context_unpin(ce); - return err; + eb->args->flags |= __EXEC_ENGINE_PINNED; + return rq; } static void eb_unpin_engine(struct i915_execbuffer *eb) @@ -2597,6 +2632,11 @@ static void eb_unpin_engine(struct i915_execbuffer *eb) struct intel_context *ce = eb->context; struct intel_timeline *tl = ce->timeline; + if (!(eb->args->flags & __EXEC_ENGINE_PINNED)) + return; + + eb->args->flags &= ~__EXEC_ENGINE_PINNED; + mutex_lock(&tl->mutex); intel_context_exit(ce); mutex_unlock(&tl->mutex); @@ -2648,7 +2688,7 @@ eb_select_legacy_ring(struct i915_execbuffer *eb) } static int -eb_pin_engine(struct i915_execbuffer *eb) +eb_select_engine(struct i915_execbuffer *eb) { struct intel_context *ce; unsigned int idx; @@ -2663,10 +2703,43 @@ eb_pin_engine(struct i915_execbuffer *eb) if (IS_ERR(ce)) return PTR_ERR(ce); - err = __eb_pin_engine(eb, ce); - intel_context_put(ce); + intel_gt_pm_get(ce->engine->gt); + if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) { + err = intel_context_alloc_state(ce); + if (err) + goto err; + } + + /* + * ABI: Before userspace accesses the GPU (e.g. execbuffer), report + * EIO if the GPU is already wedged. + */ + err = intel_gt_terminally_wedged(ce->engine->gt); + if (err) + goto err; + + eb->context = ce; + eb->engine = ce->engine; + + /* + * Make sure engine pool stays alive even if we call intel_context_put + * during ww handling. The pool is destroyed when last pm reference + * is dropped, which breaks our -EDEADLK handling. + */ return err; + +err: + intel_gt_pm_put(ce->engine->gt); + intel_context_put(ce); + return err; +} + +static void +eb_put_engine(struct i915_execbuffer *eb) +{ + intel_gt_pm_put(eb->engine->gt); + intel_context_put(eb->context); } static void @@ -2923,7 +2996,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (unlikely(err)) goto err_destroy; - err = eb_pin_engine(&eb); + err = eb_select_engine(&eb); if (unlikely(err)) goto err_context; @@ -3062,7 +3135,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, if (eb.reloc_pool) intel_gt_buffer_pool_put(eb.reloc_pool); err_engine: - eb_unpin_engine(&eb); + eb_put_engine(&eb); err_context: i915_gem_context_put(eb.gem_context); err_destroy: -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:31 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:31 +0200 Subject: [Intel-gfx] [PATCH 14/26] drm/i915: Rework intel_context pinning to do everything outside of pin_mutex In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-14-maarten.lankhorst@linux.intel.com> Instead of doing everything inside of pin_mutex, we move all pinning outside. Because i915_active has its own reference counting and pinning is also having the same issues vs mutexes, we make sure everything is pinned first, so the pinning in i915_active only needs to bump refcounts. This allows us to take pin refcounts correctly all the time. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_context.c | 232 +++++++++++------- drivers/gpu/drm/i915/gt/intel_context_types.h | 4 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 34 ++- .../gpu/drm/i915/gt/intel_ring_submission.c | 13 +- drivers/gpu/drm/i915/gt/mock_engine.c | 13 +- 5 files changed, 190 insertions(+), 106 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index e4aece20bc80..c039e87a46c4 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -93,79 +93,6 @@ static void intel_context_active_release(struct intel_context *ce) i915_active_release(&ce->active); } -int __intel_context_do_pin(struct intel_context *ce) -{ - int err; - - if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) { - err = intel_context_alloc_state(ce); - if (err) - return err; - } - - err = i915_active_acquire(&ce->active); - if (err) - return err; - - if (mutex_lock_interruptible(&ce->pin_mutex)) { - err = -EINTR; - goto out_release; - } - - if (unlikely(intel_context_is_closed(ce))) { - err = -ENOENT; - goto out_unlock; - } - - if (likely(!atomic_add_unless(&ce->pin_count, 1, 0))) { - err = intel_context_active_acquire(ce); - if (unlikely(err)) - goto out_unlock; - - err = ce->ops->pin(ce); - if (unlikely(err)) - goto err_active; - - CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", - i915_ggtt_offset(ce->ring->vma), - ce->ring->head, ce->ring->tail); - - smp_mb__before_atomic(); /* flush pin before it is visible */ - atomic_inc(&ce->pin_count); - } - - GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */ - GEM_BUG_ON(i915_active_is_idle(&ce->active)); - goto out_unlock; - -err_active: - intel_context_active_release(ce); -out_unlock: - mutex_unlock(&ce->pin_mutex); -out_release: - i915_active_release(&ce->active); - return err; -} - -void intel_context_unpin(struct intel_context *ce) -{ - if (!atomic_dec_and_test(&ce->pin_count)) - return; - - CE_TRACE(ce, "unpin\n"); - ce->ops->unpin(ce); - - /* - * Once released, we may asynchronously drop the active reference. - * As that may be the only reference keeping the context alive, - * take an extra now so that it is not freed before we finish - * dereferencing it. - */ - intel_context_get(ce); - intel_context_active_release(ce); - intel_context_put(ce); -} - static int __context_pin_state(struct i915_vma *vma) { unsigned int bias = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS; @@ -225,6 +152,138 @@ static void __ring_retire(struct intel_ring *ring) i915_active_release(&ring->vma->active); } +static int intel_context_pre_pin(struct intel_context *ce) +{ + int err; + + CE_TRACE(ce, "active\n"); + + err = __ring_active(ce->ring); + if (err) + return err; + + err = intel_timeline_pin(ce->timeline); + if (err) + goto err_ring; + + if (!ce->state) + return 0; + + err = __context_pin_state(ce->state); + if (err) + goto err_timeline; + + + return 0; + +err_timeline: + intel_timeline_unpin(ce->timeline); +err_ring: + __ring_retire(ce->ring); + return err; +} + +static void intel_context_post_unpin(struct intel_context *ce) +{ + if (ce->state) + __context_unpin_state(ce->state); + + intel_timeline_unpin(ce->timeline); + __ring_retire(ce->ring); +} + +int __intel_context_do_pin(struct intel_context *ce) +{ + bool handoff = false; + void *vaddr; + int err = 0; + + if (unlikely(!test_bit(CONTEXT_ALLOC_BIT, &ce->flags))) { + err = intel_context_alloc_state(ce); + if (err) + return err; + } + + /* + * We always pin the context/ring/timeline here, to ensure a pin + * refcount for __intel_context_active(), which prevent a lock + * inversion of ce->pin_mutex vs dma_resv_lock(). + */ + err = intel_context_pre_pin(ce); + if (err) + return err; + + err = i915_active_acquire(&ce->active); + if (err) + goto err_ctx_unpin; + + err = ce->ops->pre_pin(ce, &vaddr); + if (err) + goto err_release; + + err = mutex_lock_interruptible(&ce->pin_mutex); + if (err) + goto err_post_unpin; + + if (unlikely(intel_context_is_closed(ce))) { + err = -ENOENT; + goto err_unlock; + } + + if (likely(!atomic_add_unless(&ce->pin_count, 1, 0))) { + err = intel_context_active_acquire(ce); + if (unlikely(err)) + goto err_unlock; + + err = ce->ops->pin(ce, vaddr); + if (err) { + intel_context_active_release(ce); + goto err_unlock; + } + + CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n", + i915_ggtt_offset(ce->ring->vma), + ce->ring->head, ce->ring->tail); + + handoff = true; + smp_mb__before_atomic(); /* flush pin before it is visible */ + atomic_inc(&ce->pin_count); + } + + GEM_BUG_ON(!intel_context_is_pinned(ce)); /* no overflow! */ + +err_unlock: + mutex_unlock(&ce->pin_mutex); +err_post_unpin: + if (!handoff) + ce->ops->post_unpin(ce); +err_release: + i915_active_release(&ce->active); +err_ctx_unpin: + intel_context_post_unpin(ce); + return err; +} + +void intel_context_unpin(struct intel_context *ce) +{ + if (!atomic_dec_and_test(&ce->pin_count)) + return; + + CE_TRACE(ce, "unpin\n"); + ce->ops->unpin(ce); + ce->ops->post_unpin(ce); + + /* + * Once released, we may asynchronously drop the active reference. + * As that may be the only reference keeping the context alive, + * take an extra now so that it is not freed before we finish + * dereferencing it. + */ + intel_context_get(ce); + intel_context_active_release(ce); + intel_context_put(ce); +} + __i915_active_call static void __intel_context_retire(struct i915_active *active) { @@ -235,12 +294,7 @@ static void __intel_context_retire(struct i915_active *active) intel_context_get_avg_runtime_ns(ce)); set_bit(CONTEXT_VALID_BIT, &ce->flags); - if (ce->state) - __context_unpin_state(ce->state); - - intel_timeline_unpin(ce->timeline); - __ring_retire(ce->ring); - + intel_context_post_unpin(ce); intel_context_put(ce); } @@ -249,29 +303,25 @@ static int __intel_context_active(struct i915_active *active) struct intel_context *ce = container_of(active, typeof(*ce), active); int err; - CE_TRACE(ce, "active\n"); - intel_context_get(ce); + /* everything should already be activated by intel_context_pre_pin() */ err = __ring_active(ce->ring); - if (err) + if (GEM_WARN_ON(err)) goto err_put; err = intel_timeline_pin(ce->timeline); - if (err) + if (GEM_WARN_ON(err)) goto err_ring; - if (!ce->state) - return 0; - - err = __context_pin_state(ce->state); - if (err) - goto err_timeline; + if (ce->state) { + GEM_WARN_ON(!i915_active_acquire_if_busy(&ce->state->active)); + __i915_vma_pin(ce->state); + i915_vma_make_unshrinkable(ce->state); + } return 0; -err_timeline: - intel_timeline_unpin(ce->timeline); err_ring: __ring_retire(ce->ring); err_put: diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 4954b0df4864..ca8e05b4d3ef 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -30,8 +30,10 @@ struct intel_ring; struct intel_context_ops { int (*alloc)(struct intel_context *ce); - int (*pin)(struct intel_context *ce); + int (*pre_pin)(struct intel_context *ce, void **vaddr); + int (*pin)(struct intel_context *ce, void *vaddr); void (*unpin)(struct intel_context *ce); + void (*post_unpin)(struct intel_context *ce); void (*enter)(struct intel_context *ce); void (*exit)(struct intel_context *ce); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..3dca5e5d8451 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3279,7 +3279,10 @@ static void execlists_context_unpin(struct intel_context *ce) { check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET, ce->engine); +} +static void execlists_context_post_unpin(struct intel_context *ce) +{ i915_gem_object_unpin_map(ce->state->obj); } @@ -3441,20 +3444,23 @@ __execlists_update_reg_state(const struct intel_context *ce, } static int -__execlists_context_pin(struct intel_context *ce, - struct intel_engine_cs *engine) +execlists_context_pre_pin(struct intel_context *ce, void **vaddr) { - void *vaddr; - GEM_BUG_ON(!ce->state); GEM_BUG_ON(!i915_vma_is_pinned(ce->state)); - vaddr = i915_gem_object_pin_map(ce->state->obj, - i915_coherent_map_type(engine->i915) | + *vaddr = i915_gem_object_pin_map(ce->state->obj, + i915_coherent_map_type(ce->engine->i915) | I915_MAP_OVERRIDE); - if (IS_ERR(vaddr)) - return PTR_ERR(vaddr); + return PTR_ERR_OR_ZERO(*vaddr); +} + +static int +__execlists_context_pin(struct intel_context *ce, + struct intel_engine_cs *engine, + void *vaddr) +{ ce->lrc.lrca = lrc_descriptor(ce, engine) | CTX_DESC_FORCE_RESTORE; ce->lrc_reg_state = vaddr + LRC_STATE_OFFSET; __execlists_update_reg_state(ce, engine, ce->ring->tail); @@ -3462,9 +3468,9 @@ __execlists_context_pin(struct intel_context *ce, return 0; } -static int execlists_context_pin(struct intel_context *ce) +static int execlists_context_pin(struct intel_context *ce, void *vaddr) { - return __execlists_context_pin(ce, ce->engine); + return __execlists_context_pin(ce, ce->engine, vaddr); } static int execlists_context_alloc(struct intel_context *ce) @@ -3490,8 +3496,10 @@ static void execlists_context_reset(struct intel_context *ce) static const struct intel_context_ops execlists_context_ops = { .alloc = execlists_context_alloc, + .pre_pin = execlists_context_pre_pin, .pin = execlists_context_pin, .unpin = execlists_context_unpin, + .post_unpin = execlists_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, @@ -5419,13 +5427,13 @@ static int virtual_context_alloc(struct intel_context *ce) return __execlists_context_alloc(ce, ve->siblings[0]); } -static int virtual_context_pin(struct intel_context *ce) +static int virtual_context_pin(struct intel_context *ce, void *vaddr) { struct virtual_engine *ve = container_of(ce, typeof(*ve), context); int err; /* Note: we must use a real engine class for setting up reg state */ - err = __execlists_context_pin(ce, ve->siblings[0]); + err = __execlists_context_pin(ce, ve->siblings[0], vaddr); if (err) return err; @@ -5458,8 +5466,10 @@ static void virtual_context_exit(struct intel_context *ce) static const struct intel_context_ops virtual_context_ops = { .alloc = virtual_context_alloc, + .pre_pin = execlists_context_pre_pin, .pin = virtual_context_pin, .unpin = execlists_context_unpin, + .post_unpin = execlists_context_post_unpin, .enter = virtual_context_enter, .exit = virtual_context_exit, diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 68a08486fc87..6914abf3a88d 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -496,6 +496,10 @@ static void __context_unpin_ppgtt(struct intel_context *ce) } static void ring_context_unpin(struct intel_context *ce) +{ +} + +static void ring_context_post_unpin(struct intel_context *ce) { __context_unpin_ppgtt(ce); } @@ -584,11 +588,16 @@ static int ring_context_alloc(struct intel_context *ce) return 0; } -static int ring_context_pin(struct intel_context *ce) +static int ring_context_pre_pin(struct intel_context *ce, void **unused) { return __context_pin_ppgtt(ce); } +static int ring_context_pin(struct intel_context *ce, void *unused) +{ + return 0; +} + static void ring_context_reset(struct intel_context *ce) { intel_ring_reset(ce->ring, ce->ring->emit); @@ -597,8 +606,10 @@ static void ring_context_reset(struct intel_context *ce) static const struct intel_context_ops ring_context_ops = { .alloc = ring_context_alloc, + .pre_pin = ring_context_pre_pin, .pin = ring_context_pin, .unpin = ring_context_unpin, + .post_unpin = ring_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index b8dd3cbc8696..62664601e683 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -131,6 +131,10 @@ static void mock_context_unpin(struct intel_context *ce) { } +static void mock_context_post_unpin(struct intel_context *ce) +{ +} + static void mock_context_destroy(struct kref *ref) { struct intel_context *ce = container_of(ref, typeof(*ce), ref); @@ -164,7 +168,12 @@ static int mock_context_alloc(struct intel_context *ce) return 0; } -static int mock_context_pin(struct intel_context *ce) +static int mock_context_pre_pin(struct intel_context *ce, void **unused) +{ + return 0; +} + +static int mock_context_pin(struct intel_context *ce, void *unused) { return 0; } @@ -176,8 +185,10 @@ static void mock_context_reset(struct intel_context *ce) static const struct intel_context_ops mock_context_ops = { .alloc = mock_context_alloc, + .pre_pin = mock_context_pre_pin, .pin = mock_context_pin, .unpin = mock_context_unpin, + .post_unpin = mock_context_post_unpin, .enter = intel_context_enter_engine, .exit = intel_context_exit_engine, -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:32 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:32 +0200 Subject: [Intel-gfx] [PATCH 15/26] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-15-maarten.lankhorst@linux.intel.com> As a preparation step for full object locking and wait/wound handling during pin and object mapping, ensure that we always pass the ww context in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this happens. This also requires changing the order of eb_parse slightly, to ensure we pass ww at a point where we could still handle -EDEADLK safely. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 138 ++++++++++-------- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +- drivers/gpu/drm/i915/gt/intel_context.c | 65 ++++++--- drivers/gpu/drm/i915/gt/intel_context.h | 13 ++ drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/gt/intel_ring.c | 10 +- drivers/gpu/drm/i915/gt/intel_ring.h | 3 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 15 +- drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +- drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +- drivers/gpu/drm/i915/gt/mock_engine.c | 3 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 13 +- drivers/gpu/drm/i915/i915_gem.c | 11 +- drivers/gpu/drm/i915/i915_vma.c | 13 +- drivers/gpu/drm/i915/i915_vma.h | 13 +- 25 files changed, 214 insertions(+), 134 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e909ccc37a54..759a94010d3c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3449,7 +3449,7 @@ initial_plane_vma(struct drm_i915_private *i915, if (IS_ERR(vma)) goto err_obj; - if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) + if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) goto err_obj; if (i915_gem_object_is_tiled(obj) && diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index a1e709557704..b9d38e8edb5b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1142,7 +1142,7 @@ static int context_barrier_task(struct i915_gem_context *ctx, i915_gem_ww_ctx_init(&ww, true); retry: - err = intel_context_pin(ce); + err = intel_context_pin_ww(ce, &ww); if (err) goto err; @@ -1235,7 +1235,7 @@ static int pin_ppgtt_update(struct intel_context *ce, struct i915_gem_ww_ctx *ww if (!HAS_LOGICAL_RING_CONTEXTS(vm->i915)) /* ppGTT is not part of the legacy context image */ - return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm)); + return gen6_ppgtt_pin(i915_vm_to_ppgtt(vm), ww); return 0; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 9990e4677b9a..680d9f0d55f8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -424,16 +424,17 @@ eb_pin_vma(struct i915_execbuffer *eb, pin_flags |= PIN_GLOBAL; /* Attempt to reuse the current location if available */ - if (unlikely(i915_vma_pin(vma, 0, 0, pin_flags))) { + /* TODO: Add -EDEADLK handling here */ + if (unlikely(i915_vma_pin_ww(vma, &eb->ww, 0, 0, pin_flags))) { if (entry->flags & EXEC_OBJECT_PINNED) return false; /* Failing that pick any _free_ space if suitable */ - if (unlikely(i915_vma_pin(vma, - entry->pad_to_size, - entry->alignment, - eb_pin_flags(entry, ev->flags) | - PIN_USER | PIN_NOEVICT))) + if (unlikely(i915_vma_pin_ww(vma, &eb->ww, + entry->pad_to_size, + entry->alignment, + eb_pin_flags(entry, ev->flags) | + PIN_USER | PIN_NOEVICT))) return false; } @@ -574,7 +575,7 @@ static inline int use_cpu_reloc(const struct reloc_cache *cache, obj->cache_level != I915_CACHE_NONE); } -static int eb_reserve_vma(const struct i915_execbuffer *eb, +static int eb_reserve_vma(struct i915_execbuffer *eb, struct eb_vma *ev, u64 pin_flags) { @@ -589,7 +590,7 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb, return err; } - err = i915_vma_pin(vma, + err = i915_vma_pin_ww(vma, &eb->ww, entry->pad_to_size, entry->alignment, eb_pin_flags(entry, ev->flags) | pin_flags); if (err) @@ -1114,9 +1115,10 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj, } static void *reloc_iomap(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, + struct i915_execbuffer *eb, unsigned long page) { + struct reloc_cache *cache = &eb->reloc_cache; struct i915_ggtt *ggtt = cache_to_ggtt(cache); unsigned long offset; void *vaddr; @@ -1138,10 +1140,13 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, if (err) return ERR_PTR(err); - vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, - PIN_MAPPABLE | - PIN_NONBLOCK /* NOWARN */ | - PIN_NOEVICT); + vma = i915_gem_object_ggtt_pin_ww(obj, &eb->ww, NULL, 0, 0, + PIN_MAPPABLE | + PIN_NONBLOCK /* NOWARN */ | + PIN_NOEVICT); + if (vma == ERR_PTR(-EDEADLK)) + return vma; + if (IS_ERR(vma)) { memset(&cache->node, 0, sizeof(cache->node)); mutex_lock(&ggtt->vm.mutex); @@ -1177,9 +1182,10 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, } static void *reloc_vaddr(struct drm_i915_gem_object *obj, - struct reloc_cache *cache, + struct i915_execbuffer *eb, unsigned long page) { + struct reloc_cache *cache = &eb->reloc_cache; void *vaddr; if (cache->page == page) { @@ -1187,7 +1193,7 @@ static void *reloc_vaddr(struct drm_i915_gem_object *obj, } else { vaddr = NULL; if ((cache->vaddr & KMAP) == 0) - vaddr = reloc_iomap(obj, cache, page); + vaddr = reloc_iomap(obj, eb, page); if (!vaddr) vaddr = reloc_kmap(obj, cache, page); } @@ -1274,7 +1280,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, goto err_unmap; } - err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK); + err = i915_vma_pin_ww(batch, &eb->ww, 0, 0, PIN_USER | PIN_NONBLOCK); if (err) goto err_unmap; @@ -1511,8 +1517,7 @@ relocate_entry(struct i915_vma *vma, void *vaddr; repeat: - vaddr = reloc_vaddr(vma->obj, - &eb->reloc_cache, + vaddr = reloc_vaddr(vma->obj, eb, offset >> PAGE_SHIFT); if (IS_ERR(vaddr)) return PTR_ERR(vaddr); @@ -1928,6 +1933,7 @@ static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb, rq = eb_pin_engine(eb, false); if (IS_ERR(rq)) { err = PTR_ERR(rq); + rq = NULL; goto err; } @@ -2210,7 +2216,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) } static struct i915_vma * -shadow_batch_pin(struct drm_i915_gem_object *obj, +shadow_batch_pin(struct i915_execbuffer *eb, + struct drm_i915_gem_object *obj, struct i915_address_space *vm, unsigned int flags) { @@ -2221,7 +2228,7 @@ shadow_batch_pin(struct drm_i915_gem_object *obj, if (IS_ERR(vma)) return vma; - err = i915_vma_pin(vma, 0, 0, flags); + err = i915_vma_pin_ww(vma, &eb->ww, 0, 0, flags); if (err) return ERR_PTR(err); @@ -2371,16 +2378,33 @@ static int eb_parse_pipeline(struct i915_execbuffer *eb, return err; } +static struct i915_vma *eb_dispatch_secure(struct i915_execbuffer *eb, struct i915_vma *vma) +{ + /* + * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure + * batch" bit. Hence we need to pin secure batches into the global gtt. + * hsw should have this fixed, but bdw mucks it up again. */ + if (eb->batch_flags & I915_DISPATCH_SECURE) + return i915_gem_object_ggtt_pin_ww(vma->obj, &eb->ww, NULL, 0, 0, 0); + + return NULL; +} + static int eb_parse(struct i915_execbuffer *eb) { struct drm_i915_private *i915 = eb->i915; struct intel_gt_buffer_pool_node *pool = eb->batch_pool; - struct i915_vma *shadow, *trampoline; + struct i915_vma *shadow, *trampoline, *batch; unsigned int len; int err; - if (!eb_use_cmdparser(eb)) - return 0; + if (!eb_use_cmdparser(eb)) { + batch = eb_dispatch_secure(eb, eb->batch->vma); + if (IS_ERR(batch)) + return PTR_ERR(batch); + + goto secure_batch; + } len = eb->batch_len; if (!CMDPARSER_USES_GGTT(eb->i915)) { @@ -2408,7 +2432,7 @@ static int eb_parse(struct i915_execbuffer *eb) if (err) goto err; - shadow = shadow_batch_pin(pool->obj, eb->context->vm, PIN_USER); + shadow = shadow_batch_pin(eb, pool->obj, eb->context->vm, PIN_USER); if (IS_ERR(shadow)) { err = PTR_ERR(shadow); goto err; @@ -2420,7 +2444,7 @@ static int eb_parse(struct i915_execbuffer *eb) if (CMDPARSER_USES_GGTT(eb->i915)) { trampoline = shadow; - shadow = shadow_batch_pin(pool->obj, + shadow = shadow_batch_pin(eb, pool->obj, &eb->engine->gt->ggtt->vm, PIN_GLOBAL); if (IS_ERR(shadow)) { @@ -2433,19 +2457,34 @@ static int eb_parse(struct i915_execbuffer *eb) eb->batch_flags |= I915_DISPATCH_SECURE; } + batch = eb_dispatch_secure(eb, shadow); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto err_trampoline; + } + err = eb_parse_pipeline(eb, shadow, trampoline); if (err) - goto err_trampoline; + goto err_unpin_batch; - eb->vma[eb->buffer_count].vma = i915_vma_get(shadow); - eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN; eb->batch = &eb->vma[eb->buffer_count++]; + eb->batch->vma = i915_vma_get(shadow); + eb->batch->flags = __EXEC_OBJECT_HAS_PIN; eb->trampoline = trampoline; eb->batch_start_offset = 0; +secure_batch: + if (batch) { + eb->batch = &eb->vma[eb->buffer_count++]; + eb->batch->flags = __EXEC_OBJECT_HAS_PIN; + eb->batch->vma = i915_vma_get(batch); + } return 0; +err_unpin_batch: + if (batch) + i915_vma_unpin(batch); err_trampoline: if (trampoline) i915_vma_unpin(trampoline); @@ -2600,7 +2639,7 @@ static struct i915_request *eb_pin_engine(struct i915_execbuffer *eb, bool throt * GGTT space, so do this first before we reserve a seqno for * ourselves. */ - err = intel_context_pin(ce); + err = intel_context_pin_ww(ce, &eb->ww); if (err) return ERR_PTR(err); @@ -3023,33 +3062,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, ww_acquire_done(&eb.ww.ctx); - /* - * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure - * batch" bit. Hence we need to pin secure batches into the global gtt. - * hsw should have this fixed, but bdw mucks it up again. */ - if (eb.batch_flags & I915_DISPATCH_SECURE) { - struct i915_vma *vma; - - /* - * So on first glance it looks freaky that we pin the batch here - * outside of the reservation loop. But: - * - The batch is already pinned into the relevant ppgtt, so we - * already have the backing storage fully allocated. - * - No other BO uses the global gtt (well contexts, but meh), - * so we don't really have issues with multiple objects not - * fitting due to fragmentation. - * So this is actually safe. - */ - vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); - if (IS_ERR(vma)) { - err = PTR_ERR(vma); - goto err_vma; - } - - batch = vma; - } else { - batch = eb.batch->vma; - } + batch = eb.batch->vma; /* All GPU relocation batches must be submitted prior to the user rq */ GEM_BUG_ON(eb.reloc_cache.rq); @@ -3058,7 +3071,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.request = i915_request_create(eb.context); if (IS_ERR(eb.request)) { err = PTR_ERR(eb.request); - goto err_batch_unpin; + goto err_vma; } if (in_fence) { @@ -3120,9 +3133,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, } i915_request_put(eb.request); -err_batch_unpin: - if (eb.batch_flags & I915_DISPATCH_SECURE) - i915_vma_unpin(batch); err_vma: eb_release_vmas(&eb, true); if (eb.trampoline) @@ -3206,7 +3216,9 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, /* Copy in the exec list from userland */ exec_list = kvmalloc_array(count, sizeof(*exec_list), __GFP_NOWARN | GFP_KERNEL); - exec2_list = kvmalloc_array(count + 1, eb_element_size(), + + /* Allocate extra slots for use by the command parser */ + exec2_list = kvmalloc_array(count + 2, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec_list == NULL || exec2_list == NULL) { drm_dbg(&i915->drm, @@ -3284,8 +3296,8 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, if (err) return err; - /* Allocate an extra slot for use by the command parser */ - exec2_list = kvmalloc_array(count + 1, eb_element_size(), + /* Allocate extra slots for use by the command parser */ + exec2_list = kvmalloc_array(count + 2, eb_element_size(), __GFP_NOWARN | GFP_KERNEL); if (exec2_list == NULL) { drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index f4fec7eb4064..8248efa9229f 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -376,7 +376,7 @@ static struct i915_vma *pd_vma_create(struct gen6_ppgtt *ppgtt, int size) return vma; } -int gen6_ppgtt_pin(struct i915_ppgtt *base) +int gen6_ppgtt_pin(struct i915_ppgtt *base, struct i915_gem_ww_ctx *ww) { struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(base); int err; @@ -402,7 +402,7 @@ int gen6_ppgtt_pin(struct i915_ppgtt *base) */ err = 0; if (!atomic_read(&ppgtt->pin_count)) - err = i915_ggtt_pin(ppgtt->vma, GEN6_PD_ALIGN, PIN_HIGH); + err = i915_ggtt_pin(ppgtt->vma, ww, GEN6_PD_ALIGN, PIN_HIGH); if (!err) atomic_inc(&ppgtt->pin_count); mutex_unlock(&ppgtt->pin_mutex); diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h index 72e481806c96..00032a931bae 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h @@ -8,6 +8,8 @@ #include "intel_gtt.h" +struct i915_gem_ww_ctx; + struct gen6_ppgtt { struct i915_ppgtt base; @@ -66,7 +68,7 @@ static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base) (pt = i915_pt_entry(pd, iter), true); \ ++iter) -int gen6_ppgtt_pin(struct i915_ppgtt *base); +int gen6_ppgtt_pin(struct i915_ppgtt *base, struct i915_gem_ww_ctx *ww); void gen6_ppgtt_unpin(struct i915_ppgtt *base); void gen6_ppgtt_unpin_all(struct i915_ppgtt *base); void gen6_ppgtt_enable(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index c039e87a46c4..64948386630f 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -93,12 +93,12 @@ static void intel_context_active_release(struct intel_context *ce) i915_active_release(&ce->active); } -static int __context_pin_state(struct i915_vma *vma) +static int __context_pin_state(struct i915_vma *vma, struct i915_gem_ww_ctx *ww) { unsigned int bias = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS; int err; - err = i915_ggtt_pin(vma, 0, bias | PIN_HIGH); + err = i915_ggtt_pin(vma, ww, 0, bias | PIN_HIGH); if (err) return err; @@ -127,7 +127,8 @@ static void __context_unpin_state(struct i915_vma *vma) __i915_vma_unpin(vma); } -static int __ring_active(struct intel_ring *ring) +static int __ring_active(struct intel_ring *ring, + struct i915_gem_ww_ctx *ww) { int err; @@ -135,7 +136,7 @@ static int __ring_active(struct intel_ring *ring) if (err) return err; - err = intel_ring_pin(ring); + err = intel_ring_pin(ring, ww); if (err) goto err_active; @@ -152,24 +153,25 @@ static void __ring_retire(struct intel_ring *ring) i915_active_release(&ring->vma->active); } -static int intel_context_pre_pin(struct intel_context *ce) +static int intel_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww) { int err; CE_TRACE(ce, "active\n"); - err = __ring_active(ce->ring); + err = __ring_active(ce->ring, ww); if (err) return err; - err = intel_timeline_pin(ce->timeline); + err = intel_timeline_pin(ce->timeline, ww); if (err) goto err_ring; if (!ce->state) return 0; - err = __context_pin_state(ce->state); + err = __context_pin_state(ce->state, ww); if (err) goto err_timeline; @@ -192,7 +194,8 @@ static void intel_context_post_unpin(struct intel_context *ce) __ring_retire(ce->ring); } -int __intel_context_do_pin(struct intel_context *ce) +int __intel_context_do_pin_ww(struct intel_context *ce, + struct i915_gem_ww_ctx *ww) { bool handoff = false; void *vaddr; @@ -209,7 +212,14 @@ int __intel_context_do_pin(struct intel_context *ce) * refcount for __intel_context_active(), which prevent a lock * inversion of ce->pin_mutex vs dma_resv_lock(). */ - err = intel_context_pre_pin(ce); + + err = i915_gem_object_lock(ce->timeline->hwsp_ggtt->obj, ww); + if (!err && ce->ring->vma->obj) + err = i915_gem_object_lock(ce->ring->vma->obj, ww); + if (!err && ce->state) + err = i915_gem_object_lock(ce->state->obj, ww); + if (!err) + err = intel_context_pre_pin(ce, ww); if (err) return err; @@ -217,7 +227,7 @@ int __intel_context_do_pin(struct intel_context *ce) if (err) goto err_ctx_unpin; - err = ce->ops->pre_pin(ce, &vaddr); + err = ce->ops->pre_pin(ce, ww, &vaddr); if (err) goto err_release; @@ -264,6 +274,23 @@ int __intel_context_do_pin(struct intel_context *ce) return err; } +int __intel_context_do_pin(struct intel_context *ce) +{ + struct i915_gem_ww_ctx ww; + int err; + + i915_gem_ww_ctx_init(&ww, true); +retry: + err = __intel_context_do_pin_ww(ce, &ww); + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + return err; +} + void intel_context_unpin(struct intel_context *ce) { if (!atomic_dec_and_test(&ce->pin_count)) @@ -301,18 +328,14 @@ static void __intel_context_retire(struct i915_active *active) static int __intel_context_active(struct i915_active *active) { struct intel_context *ce = container_of(active, typeof(*ce), active); - int err; intel_context_get(ce); /* everything should already be activated by intel_context_pre_pin() */ - err = __ring_active(ce->ring); - if (GEM_WARN_ON(err)) - goto err_put; + GEM_WARN_ON(!i915_active_acquire_if_busy(&ce->ring->vma->active)); + __intel_ring_pin(ce->ring); - err = intel_timeline_pin(ce->timeline); - if (GEM_WARN_ON(err)) - goto err_ring; + __intel_timeline_pin(ce->timeline); if (ce->state) { GEM_WARN_ON(!i915_active_acquire_if_busy(&ce->state->active)); @@ -321,12 +344,6 @@ static int __intel_context_active(struct i915_active *active) } return 0; - -err_ring: - __ring_retire(ce->ring); -err_put: - intel_context_put(ce); - return err; } void diff --git a/drivers/gpu/drm/i915/gt/intel_context.h b/drivers/gpu/drm/i915/gt/intel_context.h index 07be021882cc..fda2eba81e22 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.h +++ b/drivers/gpu/drm/i915/gt/intel_context.h @@ -25,6 +25,8 @@ ##__VA_ARGS__); \ } while (0) +struct i915_gem_ww_ctx; + void intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine); void intel_context_fini(struct intel_context *ce); @@ -81,6 +83,8 @@ static inline void intel_context_unlock_pinned(struct intel_context *ce) } int __intel_context_do_pin(struct intel_context *ce); +int __intel_context_do_pin_ww(struct intel_context *ce, + struct i915_gem_ww_ctx *ww); static inline bool intel_context_pin_if_active(struct intel_context *ce) { @@ -95,6 +99,15 @@ static inline int intel_context_pin(struct intel_context *ce) return __intel_context_do_pin(ce); } +static inline int intel_context_pin_ww(struct intel_context *ce, + struct i915_gem_ww_ctx *ww) +{ + if (likely(intel_context_pin_if_active(ce))) + return 0; + + return __intel_context_do_pin_ww(ce, ww); +} + static inline void __intel_context_pin(struct intel_context *ce) { GEM_BUG_ON(!intel_context_is_pinned(ce)); diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index ca8e05b4d3ef..552cb57a2e8c 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -23,6 +23,7 @@ DECLARE_EWMA(runtime, 3, 8); struct i915_gem_context; +struct i915_gem_ww_ctx; struct i915_vma; struct intel_context; struct intel_ring; @@ -30,7 +31,7 @@ struct intel_ring; struct intel_context_ops { int (*alloc)(struct intel_context *ce); - int (*pre_pin)(struct intel_context *ce, void **vaddr); + int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr); int (*pin)(struct intel_context *ce, void *vaddr); void (*unpin)(struct intel_context *ce); void (*post_unpin)(struct intel_context *ce); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 7bf2f76212f0..8167c4b2f795 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -559,7 +559,7 @@ static int pin_ggtt_status_page(struct intel_engine_cs *engine, else flags = PIN_HIGH; - return i915_ggtt_pin(vma, 0, flags); + return i915_ggtt_pin(vma, NULL, 0, flags); } static int init_status_page(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 24a0e47a2477..1942f53a60c2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -348,7 +348,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size) goto err_unref; } - ret = i915_ggtt_pin(vma, 0, PIN_HIGH); + ret = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); if (ret) goto err_unref; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 3dca5e5d8451..7c016f5e244f 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3444,7 +3444,8 @@ __execlists_update_reg_state(const struct intel_context *ce, } static int -execlists_context_pre_pin(struct intel_context *ce, void **vaddr) +execlists_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, void **vaddr) { GEM_BUG_ON(!ce->state); GEM_BUG_ON(!i915_vma_is_pinned(ce->state)); @@ -3863,7 +3864,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) goto err; } - err = i915_ggtt_pin(vma, 0, PIN_HIGH); + err = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); if (err) goto err; diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index 3f7881de6a3c..76b39f4c29b5 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -184,7 +184,7 @@ int intel_renderstate_init(struct intel_renderstate *so, i915_gem_ww_ctx_init(&so->ww, true); retry: - err = intel_context_pin(ce); + err = intel_context_pin_ww(ce, &so->ww); if (err) goto err_fini; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c index bdb324167ef3..4034a4bac7f0 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.c +++ b/drivers/gpu/drm/i915/gt/intel_ring.c @@ -21,7 +21,13 @@ unsigned int intel_ring_update_space(struct intel_ring *ring) return space; } -int intel_ring_pin(struct intel_ring *ring) +void __intel_ring_pin(struct intel_ring *ring) +{ + GEM_BUG_ON(!atomic_read(&ring->pin_count)); + atomic_inc(&ring->pin_count); +} + +int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww) { struct i915_vma *vma = ring->vma; unsigned int flags; @@ -39,7 +45,7 @@ int intel_ring_pin(struct intel_ring *ring) else flags |= PIN_HIGH; - ret = i915_ggtt_pin(vma, 0, flags); + ret = i915_ggtt_pin(vma, ww, 0, flags); if (unlikely(ret)) goto err_unpin; diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h index cc0ebca65167..1700579bdc93 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring.h +++ b/drivers/gpu/drm/i915/gt/intel_ring.h @@ -21,7 +21,8 @@ int intel_ring_cacheline_align(struct i915_request *rq); unsigned int intel_ring_update_space(struct intel_ring *ring); -int intel_ring_pin(struct intel_ring *ring); +void __intel_ring_pin(struct intel_ring *ring); +int intel_ring_pin(struct intel_ring *ring, struct i915_gem_ww_ctx *ww); void intel_ring_unpin(struct intel_ring *ring); void intel_ring_reset(struct intel_ring *ring, u32 tail); diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 6914abf3a88d..4201b9841fd7 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -474,14 +474,16 @@ static void ring_context_destroy(struct kref *ref) intel_context_free(ce); } -static int __context_pin_ppgtt(struct intel_context *ce) +static int ring_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, + void **unused) { struct i915_address_space *vm; int err = 0; vm = vm_alias(ce->vm); if (vm) - err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm))); + err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww); return err; } @@ -588,11 +590,6 @@ static int ring_context_alloc(struct intel_context *ce) return 0; } -static int ring_context_pre_pin(struct intel_context *ce, void **unused) -{ - return __context_pin_ppgtt(ce); -} - static int ring_context_pin(struct intel_context *ce, void *unused) { return 0; @@ -1268,7 +1265,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine) } GEM_BUG_ON(timeline->has_initial_breadcrumb); - err = intel_timeline_pin(timeline); + err = intel_timeline_pin(timeline, NULL); if (err) goto err_timeline; @@ -1278,7 +1275,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine) goto err_timeline_unpin; } - err = intel_ring_pin(ring); + err = intel_ring_pin(ring, NULL); if (err) goto err_ring; diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c index 4546284fede1..e53f958bb819 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.c +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c @@ -313,14 +313,20 @@ intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp) return timeline; } -int intel_timeline_pin(struct intel_timeline *tl) +void __intel_timeline_pin(struct intel_timeline *tl) +{ + GEM_BUG_ON(!atomic_read(&tl->pin_count)); + atomic_inc(&tl->pin_count); +} + +int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww) { int err; if (atomic_add_unless(&tl->pin_count, 1, 0)) return 0; - err = i915_ggtt_pin(tl->hwsp_ggtt, 0, PIN_HIGH); + err = i915_ggtt_pin(tl->hwsp_ggtt, ww, 0, PIN_HIGH); if (err) return err; @@ -460,7 +466,7 @@ __intel_timeline_get_seqno(struct intel_timeline *tl, goto err_rollback; } - err = i915_ggtt_pin(vma, 0, PIN_HIGH); + err = i915_ggtt_pin(vma, NULL, 0, PIN_HIGH); if (err) { __idle_hwsp_free(vma->private, cacheline); goto err_rollback; diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h index 4298b9ac7327..ff293dfdbc3b 100644 --- a/drivers/gpu/drm/i915/gt/intel_timeline.h +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h @@ -71,7 +71,8 @@ static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl, return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno); } -int intel_timeline_pin(struct intel_timeline *tl); +void __intel_timeline_pin(struct intel_timeline *tl); +int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww); void intel_timeline_enter(struct intel_timeline *tl); int intel_timeline_get_seqno(struct intel_timeline *tl, struct i915_request *rq, diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index 62664601e683..f349cb9115ce 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -168,7 +168,8 @@ static int mock_context_alloc(struct intel_context *ce) return 0; } -static int mock_context_pre_pin(struct intel_context *ce, void **unused) +static int mock_context_pre_pin(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, void **unused) { return 0; } diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index daa4aabab9a7..19ae1e6ba976 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -3090,7 +3090,7 @@ static struct i915_vma *create_global(struct intel_gt *gt, size_t sz) return vma; } - err = i915_ggtt_pin(vma, 0, 0); + err = i915_ggtt_pin(vma, NULL, 0, 0); if (err) { i915_vma_put(vma); return ERR_PTR(err); diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c index fcdee951579b..efeb354c81ad 100644 --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c @@ -455,7 +455,7 @@ tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value) struct i915_request *rq; int err; - err = intel_timeline_pin(tl); + err = intel_timeline_pin(tl, NULL); if (err) { rq = ERR_PTR(err); goto out; @@ -665,7 +665,7 @@ static int live_hwsp_wrap(void *arg) if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline) goto out_free; - err = intel_timeline_pin(tl); + err = intel_timeline_pin(tl, NULL); if (err) goto out_free; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 861657897c0f..942c7c187adb 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -677,7 +677,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) goto err; flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); - ret = i915_ggtt_pin(vma, 0, flags); + ret = i915_ggtt_pin(vma, NULL, 0, flags); if (ret) { vma = ERR_PTR(ret); goto err; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5649f8e502fe..e99037506a14 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1773,11 +1773,18 @@ static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) } struct i915_vma * __must_check +i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + const struct i915_ggtt_view *view, + u64 size, u64 alignment, u64 flags); + +static inline struct i915_vma * __must_check i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, const struct i915_ggtt_view *view, - u64 size, - u64 alignment, - u64 flags); + u64 size, u64 alignment, u64 flags) +{ + return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags); +} int i915_gem_object_unbind(struct drm_i915_gem_object *obj, unsigned long flags); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 20653b660b61..625b4fc8842f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -962,11 +962,10 @@ static void discard_ggtt_vma(struct i915_vma *vma) } struct i915_vma * -i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, - const struct i915_ggtt_view *view, - u64 size, - u64 alignment, - u64 flags) +i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + const struct i915_ggtt_view *view, + u64 size, u64 alignment, u64 flags) { struct drm_i915_private *i915 = to_i915(obj->base.dev); struct i915_ggtt *ggtt = &i915->ggtt; @@ -1032,7 +1031,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, return ERR_PTR(ret); } - ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); + ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 1f63c4a1f055..d540bf45bdb0 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -856,13 +856,19 @@ static void vma_unbind_pages(struct i915_vma *vma) __vma_put_pages(vma, count | count << I915_VMA_PAGES_BIAS); } -int i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) +int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u64 size, u64 alignment, u64 flags) { struct i915_vma_work *work = NULL; intel_wakeref_t wakeref = 0; unsigned int bound; int err; +#ifdef CONFIG_PROVE_LOCKING + if (debug_locks && lockdep_is_held(&vma->vm->i915->drm.struct_mutex)) + WARN_ON(!ww); +#endif + BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); BUILD_BUG_ON(PIN_USER != I915_VMA_LOCAL_BIND); @@ -992,7 +998,8 @@ static void flush_idle_contexts(struct intel_gt *gt) intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); } -int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags) +int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u32 align, unsigned int flags) { struct i915_address_space *vm = vma->vm; int err; @@ -1000,7 +1007,7 @@ int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags) GEM_BUG_ON(!i915_vma_is_ggtt(vma)); do { - err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL); + err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL); if (err != -ENOSPC) { if (!err) { err = i915_vma_wait_for_bind(vma); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index d0d01f909548..5b3a3c653454 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -237,8 +237,17 @@ static inline void i915_vma_unlock(struct i915_vma *vma) } int __must_check -i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags); -int i915_ggtt_pin(struct i915_vma *vma, u32 align, unsigned int flags); +i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u64 size, u64 alignment, u64 flags); + +static inline int __must_check +i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) +{ + return i915_vma_pin_ww(vma, NULL, size, alignment, flags); +} + +int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, + u32 align, unsigned int flags); static inline int i915_vma_pin_count(const struct i915_vma *vma) { -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:35 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:35 +0200 Subject: [Intel-gfx] [PATCH 18/26] drm/i915: Convert i915_perf to ww locking as well In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-18-maarten.lankhorst@linux.intel.com> We have the ordering of timeline->mutex vs resv_lock wrong, convert the i915_pin_vma and intel_context_pin as well to future-proof this. We may need to do future changes to do this more transaction-like, and only get down to a single i915_gem_ww_ctx, but for now this should work. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 57 +++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 25329b7600c9..71a77951467a 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1195,24 +1195,39 @@ static struct intel_context *oa_pin_context(struct i915_perf_stream *stream) struct i915_gem_engines_iter it; struct i915_gem_context *ctx = stream->ctx; struct intel_context *ce; - int err; + struct i915_gem_ww_ctx ww; + int err = -ENODEV; for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) { if (ce->engine != stream->engine) /* first match! */ continue; - /* - * As the ID is the gtt offset of the context's vma we - * pin the vma to ensure the ID remains fixed. - */ - err = intel_context_pin(ce); - if (err == 0) { - stream->pinned_ctx = ce; - break; - } + err = 0; + break; } i915_gem_context_unlock_engines(ctx); + if (err) + return ERR_PTR(err); + + i915_gem_ww_ctx_init(&ww, true); +retry: + /* + * As the ID is the gtt offset of the context's vma we + * pin the vma to ensure the ID remains fixed. + */ + err = intel_context_pin_ww(ce, &ww); + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + + if (err) + return ERR_PTR(err); + + stream->pinned_ctx = ce; return stream->pinned_ctx; } @@ -1922,15 +1937,22 @@ emit_oa_config(struct i915_perf_stream *stream, { struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; int err; vma = get_oa_vma(stream, oa_config); if (IS_ERR(vma)) return PTR_ERR(vma); - err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); + i915_gem_ww_ctx_init(&ww, true); +retry: + err = i915_gem_object_lock(vma->obj, &ww); + if (err) + goto err; + + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH); if (err) - goto err_vma_put; + goto err; intel_engine_pm_get(ce->engine); rq = i915_request_create(ce); @@ -1952,11 +1974,9 @@ emit_oa_config(struct i915_perf_stream *stream, goto err_add_request; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, 0); if (!err) err = i915_vma_move_to_active(vma, rq, 0); - i915_vma_unlock(vma); if (err) goto err_add_request; @@ -1970,7 +1990,14 @@ emit_oa_config(struct i915_perf_stream *stream, i915_request_add(rq); err_vma_unpin: i915_vma_unpin(vma); -err_vma_put: +err: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + + i915_gem_ww_ctx_fini(&ww); i915_vma_put(vma); return err; } -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:34 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:34 +0200 Subject: [Intel-gfx] [PATCH 17/26] drm/i915: Kill last user of intel_context_create_request outside of selftests In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-17-maarten.lankhorst@linux.intel.com> Instead of using intel_context_create_request(), use intel_context_pin() and i915_create_request directly. Now all those calls are gone outside of selftests. :) Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 43 ++++++++++++++------- 1 file changed, 29 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..705f627f7f47 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2042,6 +2042,7 @@ static int engine_wa_list_verify(struct intel_context *ce, const struct i915_wa *wa; struct i915_request *rq; struct i915_vma *vma; + struct i915_gem_ww_ctx ww; unsigned int i; u32 *results; int err; @@ -2054,29 +2055,34 @@ static int engine_wa_list_verify(struct intel_context *ce, return PTR_ERR(vma); intel_engine_pm_get(ce->engine); - rq = intel_context_create_request(ce); - intel_engine_pm_put(ce->engine); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(vma->obj, &ww); + if (err == 0) + err = intel_context_pin_ww(ce, &ww); + if (err) + goto err_pm; + + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); - goto err_vma; + goto err_unpin; } - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); - if (err) { - i915_request_add(rq); - goto err_vma; - } - - err = wa_list_srm(rq, wal, vma); - if (err) - goto err_vma; + if (err == 0) + err = wa_list_srm(rq, wal, vma); i915_request_get(rq); + if (err) + i915_request_set_error_once(rq, err); i915_request_add(rq); + + if (err) + goto err_rq; + if (i915_request_wait(rq, 0, HZ / 5) < 0) { err = -ETIME; goto err_rq; @@ -2101,7 +2107,16 @@ static int engine_wa_list_verify(struct intel_context *ce, err_rq: i915_request_put(rq); -err_vma: +err_unpin: + intel_context_unpin(ce); +err_pm: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + intel_engine_pm_put(ce->engine); i915_vma_unpin(vma); i915_vma_put(vma); return err; -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:33 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:33 +0200 Subject: [Intel-gfx] [PATCH 16/26] drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-16-maarten.lankhorst@linux.intel.com> This is the last part outside of selftests that still don't use the correct lock ordering of timeline->mutex vs resv_lock. With gem fixed, there are a few places that still get locking wrong: - gvt/scheduler.c - i915_perf.c - Most if not all selftests. Changes since v1: - Add intel_engine_pm_get/put() calls to fix use-after-free when using intel_engine_get_pool(). Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- .../gpu/drm/i915/gem/i915_gem_client_blt.c | 78 +++++++-- .../gpu/drm/i915/gem/i915_gem_object_blt.c | 152 ++++++++++++------ .../gpu/drm/i915/gem/i915_gem_object_blt.h | 3 + 3 files changed, 163 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c index c182091c00ff..c141d7ce8a75 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c @@ -156,6 +156,7 @@ static void clear_pages_worker(struct work_struct *work) struct clear_pages_work *w = container_of(work, typeof(*w), work); struct drm_i915_gem_object *obj = w->sleeve->vma->obj; struct i915_vma *vma = w->sleeve->vma; + struct i915_gem_ww_ctx ww; struct i915_request *rq; struct i915_vma *batch; int err = w->dma.error; @@ -171,17 +172,20 @@ static void clear_pages_worker(struct work_struct *work) obj->read_domains = I915_GEM_GPU_DOMAINS; obj->write_domain = 0; - err = i915_vma_pin(vma, 0, 0, PIN_USER); - if (unlikely(err)) + i915_gem_ww_ctx_init(&ww, false); + intel_engine_pm_get(w->ce->engine); +retry: + err = intel_context_pin_ww(w->ce, &ww); + if (err) goto out_signal; - batch = intel_emit_vma_fill_blt(w->ce, vma, w->value); + batch = intel_emit_vma_fill_blt(w->ce, vma, &ww, w->value); if (IS_ERR(batch)) { err = PTR_ERR(batch); - goto out_unpin; + goto out_ctx; } - rq = intel_context_create_request(w->ce); + rq = i915_request_create(w->ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); goto out_batch; @@ -223,9 +227,19 @@ static void clear_pages_worker(struct work_struct *work) i915_request_add(rq); out_batch: intel_emit_vma_release(w->ce, batch); -out_unpin: - i915_vma_unpin(vma); +out_ctx: + intel_context_unpin(w->ce); out_signal: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + + i915_vma_unpin(w->sleeve->vma); + intel_engine_pm_put(w->ce->engine); + if (unlikely(err)) { dma_fence_set_error(&w->dma, err); dma_fence_signal(&w->dma); @@ -233,6 +247,44 @@ static void clear_pages_worker(struct work_struct *work) } } +static int pin_wait_clear_pages_work(struct clear_pages_work *w, + struct intel_context *ce) +{ + struct i915_vma *vma = w->sleeve->vma; + struct i915_gem_ww_ctx ww; + int err; + + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(vma->obj, &ww); + if (err) + goto out; + + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); + if (unlikely(err)) + goto out; + + err = i915_sw_fence_await_reservation(&w->wait, + vma->obj->base.resv, NULL, + true, 0, I915_FENCE_GFP); + if (err) + goto err_unpin_vma; + + dma_resv_add_excl_fence(vma->obj->base.resv, &w->dma); + +err_unpin_vma: + if (err) + i915_vma_unpin(vma); +out: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + return err; +} + static int __i915_sw_fence_call clear_pages_work_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) @@ -286,17 +338,9 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0); i915_sw_fence_init(&work->wait, clear_pages_work_notify); - i915_gem_object_lock(obj, NULL); - err = i915_sw_fence_await_reservation(&work->wait, - obj->base.resv, NULL, true, 0, - I915_FENCE_GFP); - if (err < 0) { + err = pin_wait_clear_pages_work(work, ce); + if (err < 0) dma_fence_set_error(&work->dma, err); - } else { - dma_resv_add_excl_fence(obj->base.resv, &work->dma); - err = 0; - } - i915_gem_object_unlock(obj); dma_fence_get(&work->dma); i915_sw_fence_commit(&work->wait); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c index bfdb32d46877..d93eb36160c9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c @@ -14,6 +14,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, struct i915_vma *vma, + struct i915_gem_ww_ctx *ww, u32 value) { struct drm_i915_private *i915 = ce->vm->i915; @@ -39,10 +40,24 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, goto out_pm; } + err = i915_gem_object_lock(pool->obj, ww); + if (err) + goto out_put; + + batch = i915_vma_instance(pool->obj, ce->vm, NULL); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto out_put; + } + + err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER); + if (unlikely(err)) + goto out_put; + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC); if (IS_ERR(cmd)) { err = PTR_ERR(cmd); - goto out_put; + goto out_unpin; } rem = vma->size; @@ -84,19 +99,11 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, intel_gt_chipset_flush(ce->vm->gt); - batch = i915_vma_instance(pool->obj, ce->vm, NULL); - if (IS_ERR(batch)) { - err = PTR_ERR(batch); - goto out_put; - } - - err = i915_vma_pin(batch, 0, 0, PIN_USER); - if (unlikely(err)) - goto out_put; - batch->private = pool; return batch; +out_unpin: + i915_vma_unpin(batch); out_put: intel_gt_buffer_pool_put(pool); out_pm: @@ -108,11 +115,9 @@ int intel_emit_vma_mark_active(struct i915_vma *vma, struct i915_request *rq) { int err; - i915_vma_lock(vma); err = i915_request_await_object(rq, vma->obj, false); if (err == 0) err = i915_vma_move_to_active(vma, rq, 0); - i915_vma_unlock(vma); if (unlikely(err)) return err; @@ -141,6 +146,7 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, struct intel_context *ce, u32 value) { + struct i915_gem_ww_ctx ww; struct i915_request *rq; struct i915_vma *batch; struct i915_vma *vma; @@ -150,17 +156,28 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, if (IS_ERR(vma)) return PTR_ERR(vma); - err = i915_vma_pin(vma, 0, 0, PIN_USER); - if (unlikely(err)) - return err; + i915_gem_ww_ctx_init(&ww, true); + intel_engine_pm_get(ce->engine); +retry: + err = i915_gem_object_lock(obj, &ww); + if (err) + goto out; - batch = intel_emit_vma_fill_blt(ce, vma, value); + err = intel_context_pin_ww(ce, &ww); + if (err) + goto out; + + err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_USER); + if (err) + goto out_ctx; + + batch = intel_emit_vma_fill_blt(ce, vma, &ww, value); if (IS_ERR(batch)) { err = PTR_ERR(batch); - goto out_unpin; + goto out_vma; } - rq = intel_context_create_request(ce); + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); goto out_batch; @@ -170,11 +187,9 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, if (unlikely(err)) goto out_request; - i915_vma_lock(vma); err = move_obj_to_gpu(vma->obj, rq, true); if (err == 0) err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(vma); if (unlikely(err)) goto out_request; @@ -193,8 +208,18 @@ int i915_gem_object_fill_blt(struct drm_i915_gem_object *obj, i915_request_add(rq); out_batch: intel_emit_vma_release(ce, batch); -out_unpin: +out_vma: i915_vma_unpin(vma); +out_ctx: + intel_context_unpin(ce); +out: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + intel_engine_pm_put(ce->engine); return err; } @@ -210,6 +235,7 @@ static bool wa_1209644611_applies(struct drm_i915_private *i915, u32 size) } struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, struct i915_vma *src, struct i915_vma *dst) { @@ -236,10 +262,24 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, goto out_pm; } + err = i915_gem_object_lock(pool->obj, ww); + if (err) + goto out_put; + + batch = i915_vma_instance(pool->obj, ce->vm, NULL); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto out_put; + } + + err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER); + if (unlikely(err)) + goto out_put; + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_WC); if (IS_ERR(cmd)) { err = PTR_ERR(cmd); - goto out_put; + goto out_unpin; } rem = src->size; @@ -296,20 +336,11 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, i915_gem_object_unpin_map(pool->obj); intel_gt_chipset_flush(ce->vm->gt); - - batch = i915_vma_instance(pool->obj, ce->vm, NULL); - if (IS_ERR(batch)) { - err = PTR_ERR(batch); - goto out_put; - } - - err = i915_vma_pin(batch, 0, 0, PIN_USER); - if (unlikely(err)) - goto out_put; - batch->private = pool; return batch; +out_unpin: + i915_vma_unpin(batch); out_put: intel_gt_buffer_pool_put(pool); out_pm: @@ -321,10 +352,9 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, struct drm_i915_gem_object *dst, struct intel_context *ce) { - struct drm_gem_object *objs[] = { &src->base, &dst->base }; struct i915_address_space *vm = ce->vm; struct i915_vma *vma[2], *batch; - struct ww_acquire_ctx acquire; + struct i915_gem_ww_ctx ww; struct i915_request *rq; int err, i; @@ -332,25 +362,36 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, if (IS_ERR(vma[0])) return PTR_ERR(vma[0]); - err = i915_vma_pin(vma[0], 0, 0, PIN_USER); - if (unlikely(err)) - return err; - vma[1] = i915_vma_instance(dst, vm, NULL); if (IS_ERR(vma[1])) - goto out_unpin_src; + return PTR_ERR(vma); - err = i915_vma_pin(vma[1], 0, 0, PIN_USER); + i915_gem_ww_ctx_init(&ww, true); + intel_engine_pm_get(ce->engine); +retry: + err = i915_gem_object_lock(src, &ww); + if (!err) + err = i915_gem_object_lock(dst, &ww); + if (!err) + err = intel_context_pin_ww(ce, &ww); + if (err) + goto out; + + err = i915_vma_pin_ww(vma[0], &ww, 0, 0, PIN_USER); + if (err) + goto out_ctx; + + err = i915_vma_pin_ww(vma[1], &ww, 0, 0, PIN_USER); if (unlikely(err)) goto out_unpin_src; - batch = intel_emit_vma_copy_blt(ce, vma[0], vma[1]); + batch = intel_emit_vma_copy_blt(ce, &ww, vma[0], vma[1]); if (IS_ERR(batch)) { err = PTR_ERR(batch); goto out_unpin_dst; } - rq = intel_context_create_request(ce); + rq = i915_request_create(ce); if (IS_ERR(rq)) { err = PTR_ERR(rq); goto out_batch; @@ -360,14 +401,10 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, if (unlikely(err)) goto out_request; - err = drm_gem_lock_reservations(objs, ARRAY_SIZE(objs), &acquire); - if (unlikely(err)) - goto out_request; - for (i = 0; i < ARRAY_SIZE(vma); i++) { err = move_obj_to_gpu(vma[i]->obj, rq, i); if (unlikely(err)) - goto out_unlock; + goto out_request; } for (i = 0; i < ARRAY_SIZE(vma); i++) { @@ -375,20 +412,19 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, err = i915_vma_move_to_active(vma[i], rq, flags); if (unlikely(err)) - goto out_unlock; + goto out_request; } if (rq->engine->emit_init_breadcrumb) { err = rq->engine->emit_init_breadcrumb(rq); if (unlikely(err)) - goto out_unlock; + goto out_request; } err = rq->engine->emit_bb_start(rq, batch->node.start, batch->node.size, 0); -out_unlock: - drm_gem_unlock_reservations(objs, ARRAY_SIZE(objs), &acquire); + out_request: if (unlikely(err)) i915_request_set_error_once(rq, err); @@ -400,6 +436,16 @@ int i915_gem_object_copy_blt(struct drm_i915_gem_object *src, i915_vma_unpin(vma[1]); out_unpin_src: i915_vma_unpin(vma[0]); +out_ctx: + intel_context_unpin(ce); +out: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + intel_engine_pm_put(ce->engine); return err; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h index 8bcd336a90dc..2409fdcccf0e 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.h @@ -13,12 +13,15 @@ #include "i915_vma.h" struct drm_i915_gem_object; +struct i915_gem_ww_ctx; struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce, struct i915_vma *vma, + struct i915_gem_ww_ctx *ww, u32 value); struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce, + struct i915_gem_ww_ctx *ww, struct i915_vma *src, struct i915_vma *dst); -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:37 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:37 +0200 Subject: [Intel-gfx] [PATCH 20/26] drm/i915/selftests: Fix locking inversion in lrc selftest. In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-20-maarten.lankhorst@linux.intel.com> This function does not use intel_context_create_request, so it has to use the same locking order as normal code. This is required to shut up lockdep in selftests. Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 19ae1e6ba976..65abb3a14c2d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -4999,6 +4999,7 @@ static int __live_lrc_state(struct intel_engine_cs *engine, { struct intel_context *ce; struct i915_request *rq; + struct i915_gem_ww_ctx ww; enum { RING_START_IDX = 0, RING_TAIL_IDX, @@ -5013,7 +5014,11 @@ static int __live_lrc_state(struct intel_engine_cs *engine, if (IS_ERR(ce)) return PTR_ERR(ce); - err = intel_context_pin(ce); + i915_gem_ww_ctx_init(&ww, false); +retry: + err = i915_gem_object_lock(scratch->obj, &ww); + if (!err) + err = intel_context_pin_ww(ce, &ww); if (err) goto err_put; @@ -5042,11 +5047,9 @@ static int __live_lrc_state(struct intel_engine_cs *engine, *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); *cs++ = 0; - i915_vma_lock(scratch); err = i915_request_await_object(rq, scratch->obj, true); if (!err) err = i915_vma_move_to_active(scratch, rq, EXEC_OBJECT_WRITE); - i915_vma_unlock(scratch); i915_request_get(rq); i915_request_add(rq); @@ -5083,6 +5086,12 @@ static int __live_lrc_state(struct intel_engine_cs *engine, err_unpin: intel_context_unpin(ce); err_put: + if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); intel_context_put(ce); return err; } -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:38 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:38 +0200 Subject: [Intel-gfx] [PATCH 21/26] drm/i915: Use ww pinning for intel_context_create_request() In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-21-maarten.lankhorst@linux.intel.com> We want to get rid of intel_context_pin(), convert intel_context_create_request() first. :) Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_context.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c index fe9fff5a63b1..e148e2d69ae1 100644 --- a/drivers/gpu/drm/i915/gt/intel_context.c +++ b/drivers/gpu/drm/i915/gt/intel_context.c @@ -449,15 +449,25 @@ int intel_context_prepare_remote_request(struct intel_context *ce, struct i915_request *intel_context_create_request(struct intel_context *ce) { + struct i915_gem_ww_ctx ww; struct i915_request *rq; int err; - err = intel_context_pin(ce); - if (unlikely(err)) - return ERR_PTR(err); + i915_gem_ww_ctx_init(&ww, true); +retry: + err = intel_context_pin_ww(ce, &ww); + if (!err) { + rq = i915_request_create(ce); + intel_context_unpin(ce); + } else if (err == -EDEADLK) { + err = i915_gem_ww_ctx_backoff(&ww); + if (!err) + goto retry; + } else { + rq = ERR_PTR(err); + } - rq = i915_request_create(ce); - intel_context_unpin(ce); + i915_gem_ww_ctx_fini(&ww); if (IS_ERR(rq)) return rq; -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:42 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:42 +0200 Subject: [Intel-gfx] [PATCH 25/26] drm/i915: Ensure we hold the pin mutex In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-25-maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- drivers/gpu/drm/i915/i915_vma.c | 9 ++++++++- drivers/gpu/drm/i915/i915_vma.h | 3 +++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c index 76b39f4c29b5..22c54db3d3ca 100644 --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c @@ -196,7 +196,7 @@ int intel_renderstate_init(struct intel_renderstate *so, if (err) goto err_context; - err = i915_vma_pin(so->vma, 0, 0, PIN_GLOBAL | PIN_HIGH); + err = i915_vma_pin_ww(so->vma, &so->ww, 0, 0, PIN_GLOBAL | PIN_HIGH); if (err) goto err_context; diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index d540bf45bdb0..4d797add5323 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -867,6 +867,8 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, #ifdef CONFIG_PROVE_LOCKING if (debug_locks && lockdep_is_held(&vma->vm->i915->drm.struct_mutex)) WARN_ON(!ww); + if (debug_locks && ww && vma->resv) + assert_vma_held(vma); #endif BUILD_BUG_ON(PIN_GLOBAL != I915_VMA_GLOBAL_BIND); @@ -1006,8 +1008,13 @@ int i915_ggtt_pin(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, GEM_BUG_ON(!i915_vma_is_ggtt(vma)); + WARN_ON(!ww && vma->resv && dma_resv_held(vma->resv)); + do { - err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL); + if (ww) + err = i915_vma_pin_ww(vma, ww, 0, align, flags | PIN_GLOBAL); + else + err = i915_vma_pin(vma, 0, align, flags | PIN_GLOBAL); if (err != -ENOSPC) { if (!err) { err = i915_vma_wait_for_bind(vma); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 5b3a3c653454..838bbbeb11cc 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -243,6 +243,9 @@ i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, static inline int __must_check i915_vma_pin(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) { +#ifdef CONFIG_LOCKDEP + WARN_ON_ONCE(vma->resv && dma_resv_held(vma->resv)); +#endif return i915_vma_pin_ww(vma, NULL, size, alignment, flags); } -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:41 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:41 +0200 Subject: [Intel-gfx] [PATCH 24/26] drm/i915: Add ww locking to pin_to_display_plane In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-24-maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 65 ++++++++++++++++------ drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 + 2 files changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 8ebceebd11b0..c0d153284984 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -37,6 +37,12 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) i915_gem_object_unlock(obj); } +void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj) +{ + if (i915_gem_object_is_framebuffer(obj)) + __i915_gem_object_flush_for_display(obj); +} + /** * Moves a single object to the WC read, and possibly write domain. * @obj: object to act on @@ -197,18 +203,12 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, if (ret) return ret; - ret = i915_gem_object_lock_interruptible(obj, NULL); - if (ret) - return ret; - /* Always invalidate stale cachelines */ if (obj->cache_level != cache_level) { i915_gem_object_set_cache_coherency(obj, cache_level); obj->cache_dirty = true; } - i915_gem_object_unlock(obj); - /* The cache-level will be applied when each vma is rebound. */ return i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE | @@ -255,6 +255,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, struct drm_i915_gem_caching *args = data; struct drm_i915_gem_object *obj; enum i915_cache_level level; + struct i915_gem_ww_ctx ww; int ret = 0; switch (args->caching) { @@ -293,7 +294,18 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, goto out; } - ret = i915_gem_object_set_cache_level(obj, level); + i915_gem_ww_ctx_init(&ww, true); +retry: + ret = i915_gem_object_lock(obj, &ww); + if (!ret) + ret = i915_gem_object_set_cache_level(obj, level); + + if (ret == -EDEADLK) { + ret = i915_gem_ww_ctx_backoff(&ww); + if (!ret) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); out: i915_gem_object_put(obj); @@ -313,6 +325,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, unsigned int flags) { struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_gem_ww_ctx ww; struct i915_vma *vma; int ret; @@ -320,6 +333,11 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, if (HAS_LMEM(i915) && !i915_gem_object_is_lmem(obj)) return ERR_PTR(-EINVAL); + i915_gem_ww_ctx_init(&ww, true); +retry: + ret = i915_gem_object_lock(obj, &ww); + if (ret) + goto err; /* * The display engine is not coherent with the LLC cache on gen6. As * a result, we make sure that the pinning that is about to occur is @@ -334,7 +352,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE); if (ret) - return ERR_PTR(ret); + goto err; /* * As the user may map the buffer once pinned in the display plane @@ -347,18 +365,31 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, vma = ERR_PTR(-ENOSPC); if ((flags & PIN_MAPPABLE) == 0 && (!view || view->type == I915_GGTT_VIEW_NORMAL)) - vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, - flags | - PIN_MAPPABLE | - PIN_NONBLOCK); - if (IS_ERR(vma)) - vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); - if (IS_ERR(vma)) - return vma; + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0, alignment, + flags | PIN_MAPPABLE | + PIN_NONBLOCK); + if (IS_ERR(vma) && vma != ERR_PTR(-EDEADLK)) + vma = i915_gem_object_ggtt_pin_ww(obj, &ww, view, 0, + alignment, flags); + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); + goto err; + } vma->display_alignment = max_t(u64, vma->display_alignment, alignment); - i915_gem_object_flush_if_display(obj); + i915_gem_object_flush_if_display_locked(obj); + +err: + if (ret == -EDEADLK) { + ret = i915_gem_ww_ctx_backoff(&ww); + if (!ret) + goto retry; + } + i915_gem_ww_ctx_fini(&ww); + + if (ret) + return ERR_PTR(ret); return vma; } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 11b8e2735071..409fd00c8709 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -456,6 +456,7 @@ i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj) void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, unsigned int cache_level); void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj); +void i915_gem_object_flush_if_display_locked(struct drm_i915_gem_object *obj); int __must_check i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); -- 2.27.0 From maarten.lankhorst at linux.intel.com Tue Jun 23 14:28:43 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 23 Jun 2020 16:28:43 +0200 Subject: [Intel-gfx] [PATCH 26/26] drm/i915: Kill context before taking ctx->mutex In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <20200623142843.423594-26-maarten.lankhorst@linux.intel.com> Killing context before taking ctx->mutex fixes a hang in gem_ctx_persistence.close-replace-race, where lut_close takes obj->resv.lock which is already held by execbuf, causing a stalling indefinitely. [ 1904.342847] 2 locks held by gem_ctx_persist/11520: [ 1904.342849] #0: ffff8882188e4968 (&ctx->mutex){+.+.}-{3:3}, at: context_close+0xe6/0x850 [i915] [ 1904.342941] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: lut_close+0x2c2/0xba0 [i915] [ 1904.343033] 3 locks held by gem_ctx_persist/11521: [ 1904.343035] #0: ffffc900008ff938 (reservation_ww_class_acquire){+.+.}-{0:0}, at: i915_gem_do_execbuffer+0x103d/0x54c0 [i915] [ 1904.343157] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: eb_validate_vmas+0x602/0x2010 [i915] [ 1904.343267] #2: ffff88820afd9200 (&vm->mutex/1){+.+.}-{3:3}, at: i915_vma_pin_ww+0x335/0x2300 [i915] Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 24 ++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index b9d38e8edb5b..3c89150f7262 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -623,6 +623,18 @@ static void context_close(struct i915_gem_context *ctx) i915_gem_context_set_closed(ctx); mutex_unlock(&ctx->engines_mutex); + /* + * If the user has disabled hangchecking, we can not be sure that + * the batches will ever complete after the context is closed, + * keeping the context and all resources pinned forever. So in this + * case we opt to forcibly kill off all remaining requests on + * context close. + */ + if (!i915_gem_context_is_persistent(ctx) || + !i915_modparams.enable_hangcheck) + kill_context(ctx); + + mutex_lock(&ctx->mutex); set_closed_name(ctx); @@ -641,18 +653,6 @@ static void context_close(struct i915_gem_context *ctx) lut_close(ctx); mutex_unlock(&ctx->mutex); - - /* - * If the user has disabled hangchecking, we can not be sure that - * the batches will ever complete after the context is closed, - * keeping the context and all resources pinned forever. So in this - * case we opt to forcibly kill off all remaining requests on - * context close. - */ - if (!i915_gem_context_is_persistent(ctx) || - !i915_modparams.enable_hangcheck) - kill_context(ctx); - i915_gem_context_put(ctx); } -- 2.27.0 From thomas_os at shipmail.org Tue Jun 23 15:09:08 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 17:09:08 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159292086189.10607.10450244252436195167@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> <159292086189.10607.10450244252436195167@build.alporthouse.com> Message-ID: <3ea271d6-3101-62e0-8fb6-d433ba78ff17@shipmail.org> On 6/23/20 4:01 PM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-23 13:57:06) >> On 6/23/20 1:22 PM, Thomas Hellstr?m (Intel) wrote: >>> Hi, Chris, >>> >>> On 6/22/20 11:59 AM, Chris Wilson wrote: >>>> In order to actually handle eviction and what not, we need to process >>>> all the objects together under a common lock, reservation_ww_class. As >>>> such, do a memory reservation pass after looking up the object/vma, >>>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>>> flushing and ofc execution]. >>>> >>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>>> --- >>>> ? .../gpu/drm/i915/gem/i915_gem_execbuffer.c??? | 91 ++++++++++++++----- >>>> ? 1 file changed, 70 insertions(+), 21 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>> index 46fcbdf8161c..8db2e013465f 100644 >>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>> @@ -53,10 +53,9 @@ struct eb_vma_array { >>>> ? ? #define __EXEC_OBJECT_HAS_PIN??????? BIT(31) >>>> ? #define __EXEC_OBJECT_HAS_FENCE??????? BIT(30) >>>> -#define __EXEC_OBJECT_HAS_PAGES??????? BIT(29) >>>> -#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(28) >>>> -#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(27) >>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 27) /* all of the >>>> above */ >>>> +#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(29) >>>> +#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(28) >>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 28) /* all of the >>>> above */ >>>> ? ? #define __EXEC_HAS_RELOC??? BIT(31) >>>> ? #define __EXEC_INTERNAL_FLAGS??? (~0u << 31) >>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { >>>> ????? struct intel_context *context; /* logical state for the request */ >>>> ????? struct i915_gem_context *gem_context; /** caller's context */ >>>> ? +??? struct dma_fence *mm_fence; >>>> + >>>> ????? struct i915_request *request; /** our request to build */ >>>> ????? struct eb_vma *batch; /** identity of the batch obj/vma */ >>>> ????? struct i915_vma *trampoline; /** trampoline used for chaining */ >>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct >>>> eb_vma *ev) >>>> ????? if (ev->flags & __EXEC_OBJECT_HAS_PIN) >>>> ????????? __i915_vma_unpin(vma); >>>> ? -??? if (ev->flags & __EXEC_OBJECT_HAS_PAGES) >>>> -??????? i915_gem_object_unpin_pages(vma->obj); >>>> - >>>> -??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | >>>> -?????????????? __EXEC_OBJECT_HAS_FENCE | >>>> -?????????????? __EXEC_OBJECT_HAS_PAGES); >>>> +??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); >>>> ? } >>>> ? ? static void eb_vma_array_destroy(struct kref *kref) >>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, >>>> ????? list_add_tail(&ev->lock_link, &eb->lock); >>>> ? } >>>> ? +static int eb_vma_get_pages(struct i915_execbuffer *eb, >>>> +??????????????? struct eb_vma *ev, >>>> +??????????????? u64 idx) >>>> +{ >>>> +??? struct i915_vma *vma = ev->vma; >>>> +??? int err; >>>> + >>>> +??? /* XXX also preallocate PD for vma */ >>>> + >>>> +??? err = ____i915_gem_object_get_pages_async(vma->obj); >>>> +??? if (err) >>>> +??????? return err; >>>> + >>>> +??? return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); >>>> +} >>>> + >>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>>> +{ >>>> +??? const u64 idx = eb->context->timeline->fence_context; >>>> +??? struct ww_acquire_ctx acquire; >>>> +??? struct eb_vma *ev; >>>> +??? int err; >>>> + >>>> +??? eb->mm_fence = __dma_fence_create_proxy(0, 0); >>>> +??? if (!eb->mm_fence) >>>> +??????? return -ENOMEM; >>> Question: eb is local to this thread, right, so eb->mm_fence is not >>> considered "published" yet? >>> >>>> + >>>> +??? ww_acquire_init(&acquire, &reservation_ww_class); >>>> + >>>> +??? err = eb_lock_vma(eb, &acquire); >>>> +??? if (err) >>>> +??????? goto out; >>>> + >>>> +??? ww_acquire_done(&acquire); >>>> + >>>> +??? list_for_each_entry(ev, &eb->lock, lock_link) { >>>> +??????? struct i915_vma *vma = ev->vma; >>>> + >>>> +??????? if (err == 0) >>>> +??????????? err = eb_vma_get_pages(eb, ev, idx); >>> I figure this is where you publish the proxy fence? If so, the fence >>> signaling critical path starts with this loop, and that means any code >>> we call between here and submission complete (including spawned work >>> we need to wait for before submission) may not lock the >>> reservation_ww_class nor (still being discussed) allocate memory. > Yes, at this point we have reserved the memory for the execbuf. > >>> It >>> looks like i915_pin_vma takes a reservation_ww_class. And all memory >>> pinning seems to be in the fence critical path as well? > Correct, it's not meant to be waiting inside i915_vma_pin(); the > intention was to pass in memory, and then we would not need to > do the acquire ourselves. As we have just reserved the memory in the > above loop, this should not be an issue. I was trying to keep the > change minimal and allow incremental conversions. It does however need > to add a reference to the object for the work it spawns -- equally > though there is an async eviction pass later in execbuf. The challenge > here is that the greedy grab of bound vma is faster than doing the > unbound eviction handling (even when eviction is not required). So for the i915_vma_pin, it looks like fence_critical_start(eb_reserve_mm) -> dma_resv_lock_interruptible(i915_vma_pin) -> lockdep issue. You can't take the dma_resv_lock inside a fence critical section. And for the memory allocation, it looks like the fence is published in the first loop iteration, starting the critical section, meaning that any memory allocation that follows will cause a lockdep issue. That includes worker threads. (with the proposed dma_fence annotations). > >> And I think even if we at some point end up with the allocation >> annotation the other way around, allowing memory allocations in fence >> signalling critical paths, both relocations and userpointer would cause >> lockdep problems because of >> >> mmap_sem->reservation_object->fence_wait (fault handlers, lockdep priming) > We don't wait inside mmap_sem. One cannot, you do not know the locking > context, so you can only try to reclaim idle space. So you end up with > the issue of a multitude of threads each trying to claim the last slice > of the aperture/backing storage, not being able to directly reclaim and > so have to hit the equivalent of kswapd. I don't think I follow you here. There are a number of drivers that wait for dma_fences inside the fault handlers with mmap_sem held for data to be migrated before the pte is set up. > >> vs >> fence_critical->gup/copy_from_user->mmap_sem > Which exists today, even the busy wait loop is implicit linkage; you only > need userspace to be holding a resource on the gpu to create the deadlock. > I've been using the userfault handler to develop test cases where we can > arbitrarily block the userptr. Yes but in a case where we don't publish the fence early, the above would be reduced to the well known reservation_ww_class vs mmap_sem lockdep issue, which other drivers seem to have solved and we could copy what they've done. /Thomas > -Chris From chris at chris-wilson.co.uk Tue Jun 23 15:23:31 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 16:23:31 +0100 Subject: [Intel-gfx] [PATCH 01/26] Revert "drm/i915/gem: Async GPU relocations only" In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <159292581164.3967.4508032507063193551@build.alporthouse.com> Quoting Maarten Lankhorst (2020-06-23 15:28:18) > This reverts commit 9e0f9464e2ab36b864359a59b0e9058fdef0ce47, > and related commit 7ac2d2536dfa7 ("drm/i915/gem: Delete unused code"). Regardless that you haven't adapted the series... This still prevents concurrent submission between clients, and does not remove the allocation mutexes. That latter we can do in a couple of patches that preserve the status quo with just a name switch and the forced removal of nestable shrinkers. But the former we continue to be at an impasse for over 6 months. -Chris From thomas_os at shipmail.org Tue Jun 23 15:37:30 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 17:37:30 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159290661156.6856.12185315246799210214@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> Message-ID: <5c0df713-ea47-71ff-9833-9e99b36c5474@shipmail.org> On 6/23/20 12:03 PM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) >> Hi, Chris! >> >> On 6/22/20 11:59 AM, Chris Wilson wrote: >>> In order to actually handle eviction and what not, we need to process >>> all the objects together under a common lock, reservation_ww_class. As >>> such, do a memory reservation pass after looking up the object/vma, >>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>> flushing and ofc execution]. >>> >>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>> --- >>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>> 1 file changed, 70 insertions(+), 21 deletions(-) >>> >> Which tree is this against? The series doesn't apply cleanly against >> drm-tip? > It's continuing on from the scheduler patches, the bug fixes and the > iris-deferred-fence work. I thought throwing all of those old patches > into the pile would have been distracting. Is there somewhere you could push a branch for reviewer consumption? Thanks, /Thomas From patchwork at emeril.freedesktop.org Tue Jun 23 15:39:36 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 15:39:36 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBz?= =?utf-8?q?eries_starting_with_=5B01/26=5D_Revert_=22drm/i915/gem=3A_Async?= =?utf-8?q?_GPU_relocations_only=22?= In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <159292677615.4210.5829198074082791060@emeril.freedesktop.org> == Series Details == Series: series starting with [01/26] Revert "drm/i915/gem: Async GPU relocations only" URL : https://patchwork.freedesktop.org/series/78744/ State : failure == Summary == Applying: Revert "drm/i915/gem: Async GPU relocations only" Applying: drm/i915: Revert relocation chaining commits. Applying: Revert "drm/i915/gem: Drop relocation slowpath". Applying: drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. Applying: drm/i915: Remove locking from i915_gem_object_prepare_read/write Applying: drm/i915: Parse command buffer earlier in eb_relocate(slow) Applying: Revert "drm/i915/gem: Split eb_vma into its own allocation" Applying: drm/i915/gem: Make eb_add_lut interruptible wait on object lock. Applying: drm/i915: Use per object locking in execbuf, v12. Applying: drm/i915: Use ww locking in intel_renderstate. Applying: drm/i915: Add ww context handling to context_barrier_task Applying: drm/i915: Nuke arguments to eb_pin_engine Applying: drm/i915: Pin engine before pinning all objects, v4. Applying: drm/i915: Rework intel_context pinning to do everything outside of pin_mutex Applying: drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. Applying: drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. Applying: drm/i915: Kill last user of intel_context_create_request outside of selftests Applying: drm/i915: Convert i915_perf to ww locking as well Applying: drm/i915: Dirty hack to fix selftests locking inversion Applying: drm/i915/selftests: Fix locking inversion in lrc selftest. Applying: drm/i915: Use ww pinning for intel_context_create_request() Applying: drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2. Applying: drm/i915: Add ww locking to vm_fault_gtt Applying: drm/i915: Add ww locking to pin_to_display_plane Applying: drm/i915: Ensure we hold the pin mutex Applying: drm/i915: Kill context before taking ctx->mutex error: sha1 information is lacking or useless (drivers/gpu/drm/i915/gem/i915_gem_context.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0026 drm/i915: Kill context before taking ctx->mutex When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From daniel.vetter at ffwll.ch Tue Jun 23 15:54:56 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Tue, 23 Jun 2020 17:54:56 +0200 Subject: [Intel-gfx] [PATCH] drm/fb-helper: Fix vt restore Message-ID: <20200623155456.3092836-1-daniel.vetter@ffwll.ch> In the past we had a pile of hacks to orchestrate access between fbdev emulation and native kms clients. We've tried to streamline this, by always preferring the kms side above fbdev calls when a drm master exists, because drm master controls access to the display resources. Unfortunately this breaks existing userspace, specifically Xorg. When exiting Xorg first restores the console to text mode using the KDSET ioctl on the vt. This does nothing, because a drm master is still around. Then it drops the drm master status, which again does nothing, because logind is keeping additional drm fd open to be able to orchestrate vt switches. In the past this is the point where fbdev was restored, as part of the ->lastclose hook on the drm side. Now to fix this regression we don't want to go back to letting fbdev restore things whenever it feels like, or to the pile of hacks we've had before. Instead try and go with a minimal exception to make the KDSET case work again, and nothing else. This means that if userspace does a KDSET call when switching between graphical compositors, there will be some flickering with fbcon showing up for a bit. But a) that's not a regression and b) userspace can fix it by improving the vt switching dance - logind should have all the information it needs. While pondering all this I'm also wondering wheter we should have a SWITCH_MASTER ioctl to allow race-free master status handover. But that's for another day. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208179 Cc: shlomo at fastmail.com Reported-and-Tested-by: shlomo at fastmail.com Cc: Michel D?nzer <michel at daenzer.net> Fixes: 64914da24ea9 ("drm/fbdev-helper: don't force restores") Cc: Noralf Tr?nnes <noralf at tronnes.org> Cc: Thomas Zimmermann <tzimmermann at suse.de> Cc: Daniel Vetter <daniel.vetter at intel.com> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: Maxime Ripard <mripard at kernel.org> Cc: David Airlie <airlied at linux.ie> Cc: Daniel Vetter <daniel at ffwll.ch> Cc: dri-devel at lists.freedesktop.org Cc: <stable at vger.kernel.org> # v5.7+ Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> --- drivers/gpu/drm/drm_fb_helper.c | 63 +++++++++++++++++++++++++------- drivers/video/fbdev/core/fbcon.c | 3 +- include/uapi/linux/fb.h | 1 + 3 files changed, 52 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 170aa7689110..ae69bf8e9bcc 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -227,18 +227,9 @@ int drm_fb_helper_debug_leave(struct fb_info *info) } EXPORT_SYMBOL(drm_fb_helper_debug_leave); -/** - * drm_fb_helper_restore_fbdev_mode_unlocked - restore fbdev configuration - * @fb_helper: driver-allocated fbdev helper, can be NULL - * - * This should be called from driver's drm &drm_driver.lastclose callback - * when implementing an fbcon on top of kms using this helper. This ensures that - * the user isn't greeted with a black screen when e.g. X dies. - * - * RETURNS: - * Zero if everything went ok, negative error code otherwise. - */ -int drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper) +static int +__drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper, + bool force) { bool do_delayed; int ret; @@ -250,7 +241,16 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper) return 0; mutex_lock(&fb_helper->lock); - ret = drm_client_modeset_commit(&fb_helper->client); + if (force) { + /* + * Yes this is the _locked version which expects the master lock + * to be held. But for forced restores we're intentionally + * racing here, see drm_fb_helper_set_par(). + */ + ret = drm_client_modeset_commit_locked(&fb_helper->client); + } else { + ret = drm_client_modeset_commit(&fb_helper->client); + } do_delayed = fb_helper->delayed_hotplug; if (do_delayed) @@ -262,6 +262,22 @@ int drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper) return ret; } + +/** + * drm_fb_helper_restore_fbdev_mode_unlocked - restore fbdev configuration + * @fb_helper: driver-allocated fbdev helper, can be NULL + * + * This should be called from driver's drm &drm_driver.lastclose callback + * when implementing an fbcon on top of kms using this helper. This ensures that + * the user isn't greeted with a black screen when e.g. X dies. + * + * RETURNS: + * Zero if everything went ok, negative error code otherwise. + */ +int drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper) +{ + return __drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper, false); +} EXPORT_SYMBOL(drm_fb_helper_restore_fbdev_mode_unlocked); #ifdef CONFIG_MAGIC_SYSRQ @@ -1318,6 +1334,7 @@ int drm_fb_helper_set_par(struct fb_info *info) { struct drm_fb_helper *fb_helper = info->par; struct fb_var_screeninfo *var = &info->var; + bool force; if (oops_in_progress) return -EBUSY; @@ -1327,7 +1344,25 @@ int drm_fb_helper_set_par(struct fb_info *info) return -EINVAL; } - drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); + /* + * Normally we want to make sure that a kms master takes + * precedence over fbdev, to avoid fbdev flickering and + * occasionally stealing the display status. But Xorg first sets + * the vt back to text mode using the KDSET IOCTL with KD_TEXT, + * and only after that drops the master status when exiting. + * + * In the past this was caught by drm_fb_helper_lastclose(), but + * on modern systems where logind always keeps a drm fd open to + * orchestrate the vt switching, this doesn't work. + * + * To no break the userspace ABI we have this special case here, + * which is only used for the above case. Everything else uses + * the normal commit function, which ensures that we never steal + * the display from an active drm master. + */ + force = var->activate & FB_ACTIVATE_KD_TEXT; + + __drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper, force); return 0; } diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c index 9d28a8e3328f..e2a490c5ae08 100644 --- a/drivers/video/fbdev/core/fbcon.c +++ b/drivers/video/fbdev/core/fbcon.c @@ -2402,7 +2402,8 @@ static int fbcon_blank(struct vc_data *vc, int blank, int mode_switch) ops->graphics = 1; if (!blank) { - var.activate = FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE; + var.activate = FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE | + FB_ACTIVATE_KD_TEXT; fb_set_var(info, &var); ops->graphics = 0; ops->var = info->var; diff --git a/include/uapi/linux/fb.h b/include/uapi/linux/fb.h index b6aac7ee1f67..4c14e8be7267 100644 --- a/include/uapi/linux/fb.h +++ b/include/uapi/linux/fb.h @@ -205,6 +205,7 @@ struct fb_bitfield { #define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */ #define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/ #define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */ +#define FB_ACTIVATE_KD_TEXT 512 /* for KDSET vt ioctl */ #define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */ -- 2.27.0 From sean at poorly.run Tue Jun 23 15:58:50 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:50 -0400 Subject: [Intel-gfx] [PATCH v7 00/17] drm/i915: Add support for HDCP 1.4 over MST Message-ID: <20200623155907.22961-1-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> No functional changes, this set has the following changes since v6: - rebased on drm-tip - split "drm/i915: Clean up intel_hdcp_disable" out of "drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it" - remove hdcp2 dpmst stubs Regarding "level of testing" questions, I've tested with multiple MST hubs and displays. I don't have any compliance gear so all of this is desk tested and works for me. Sean Sean Paul (17): drm/i915: Fix sha_text population code drm/i915: Clear the repeater bit on HDCP disable drm/i915: WARN if HDCP signalling is enabled upon disable drm/i915: Intercept Aksv writes in the aux hooks drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signalling drm/i915: Factor out hdcp->value assignments drm/i915: Protect workers against disappearing connectors drm/i915: Clean up intel_hdcp_disable drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it drm/i915: Support DP MST in enc_to_dig_port() function drm/i915: Use ddi_update_pipe in intel_dp_mst drm/i915: Factor out HDCP shim functions from dp for use by dp_mst drm/i915: Plumb port through hdcp init drm/i915: Add connector to hdcp_shim->check_link() drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message drm/i915: Print HDCP version info for all connectors drm/i915: Add HDCP 1.4 support for MST connectors drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++ drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 29 +- drivers/gpu/drm/i915/display/intel_ddi.h | 2 + .../drm/i915/display/intel_display_debugfs.c | 21 +- .../drm/i915/display/intel_display_types.h | 30 +- drivers/gpu/drm/i915/display/intel_dp.c | 646 +--------------- drivers/gpu/drm/i915/display/intel_dp.h | 9 + drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 702 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 + drivers/gpu/drm/i915/display/intel_hdcp.c | 218 ++++-- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +- .../drm/selftests/test-drm_dp_mst_helper.c | 17 + include/drm/drm_dp_helper.h | 3 + include/drm/drm_dp_mst_helper.h | 44 ++ include/drm/drm_hdcp.h | 3 + 17 files changed, 1191 insertions(+), 722 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:51 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:51 -0400 Subject: [Intel-gfx] [PATCH v7 01/17] drm/i915: Fix sha_text population code In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-2-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> This patch fixes a few bugs: 1- We weren't taking into account sha_leftovers when adding multiple ksvs to sha_text. As such, we were or'ing the end of ksv[j - 1] with the beginning of ksv[j] 2- In the sha_leftovers == 2 and sha_leftovers == 3 case, bstatus was being placed on the wrong half of sha_text, overlapping the leftover ksv value 3- In the sha_leftovers == 2 case, we need to manually terminate the byte stream with 0x80 since the hardware doesn't have enough room to add it after writing M0 The upside is that all of the HDCP supported HDMI repeaters I could find on Amazon just strip HDCP anyways, so it turns out to be _really_ hard to hit any of these cases without an MST hub, which is not (yet) supported. Oh, and the sha_leftovers == 1 case works perfectly! Fixes: ee5e5e7a5e0f (drm/i915: Add HDCP framework + base implementation) Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Ramalingam C <ramalingam.c at intel.com> Cc: Daniel Vetter <daniel.vetter at ffwll.ch> Cc: Sean Paul <seanpaul at chromium.org> Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> Cc: intel-gfx at lists.freedesktop.org Cc: <stable at vger.kernel.org> # v4.17+ Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-2-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-2-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-2-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-2-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-2-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-2-sean at poorly.run #v6 Changes in v2: -None Changes in v3: -None Changes in v4: -Rebased on intel_de_write changes Changes in v5: -None Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_hdcp.c | 26 +++++++++++++++++------ include/drm/drm_hdcp.h | 3 +++ 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 815b054bb167..f26fee3b4624 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -336,8 +336,10 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, /* Fill up the empty slots in sha_text and write it out */ sha_empty = sizeof(sha_text) - sha_leftovers; - for (j = 0; j < sha_empty; j++) - sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8); + for (j = 0; j < sha_empty; j++) { + u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); + sha_text |= ksv[j] << off; + } ret = intel_write_sha_text(dev_priv, sha_text); if (ret < 0) @@ -435,7 +437,7 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, /* Write 32 bits of text */ intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); - sha_text |= bstatus[0] << 24 | bstatus[1] << 16; + sha_text |= bstatus[0] << 8 | bstatus[1]; ret = intel_write_sha_text(dev_priv, sha_text); if (ret < 0) return ret; @@ -450,17 +452,29 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, return ret; sha_idx += sizeof(sha_text); } + + /* + * Terminate the SHA-1 stream by hand. For the other leftover + * cases this is appended by the hardware. + */ + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_32); + sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; + ret = intel_write_sha_text(dev_priv, sha_text); + if (ret < 0) + return ret; + sha_idx += sizeof(sha_text); } else if (sha_leftovers == 3) { - /* Write 32 bits of text */ + /* Write 32 bits of text (filled from LSB) */ intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); - sha_text |= bstatus[0] << 24; + sha_text |= bstatus[0]; ret = intel_write_sha_text(dev_priv, sha_text); if (ret < 0) return ret; sha_idx += sizeof(sha_text); - /* Write 8 bits of text, 24 bits of M0 */ + /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8); ret = intel_write_sha_text(dev_priv, bstatus[1]); diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index c6bab4986a65..fe58dbb46962 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -29,6 +29,9 @@ /* Slave address for the HDCP registers in the receiver */ #define DRM_HDCP_DDC_ADDR 0x3A +/* Value to use at the end of the SHA-1 bytestream used for repeaters */ +#define DRM_HDCP_SHA1_TERMINATOR 0x80 + /* HDCP register offsets for HDMI/DVI devices */ #define DRM_HDCP_DDC_BKSV 0x00 #define DRM_HDCP_DDC_RI_PRIME 0x08 -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:52 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:52 -0400 Subject: [Intel-gfx] [PATCH v7 02/17] drm/i915: Clear the repeater bit on HDCP disable In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-3-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> On HDCP disable, clear the repeater bit. This ensures if we connect a non-repeater sink after a repeater, the bit is in the state we expect. Fixes: ee5e5e7a5e0f (drm/i915: Add HDCP framework + base implementation) Cc: Chris Wilson <chris at chris-wilson.co.uk> Cc: Ramalingam C <ramalingam.c at intel.com> Cc: Daniel Vetter <daniel.vetter at ffwll.ch> Cc: Sean Paul <seanpaul at chromium.org> Cc: Jani Nikula <jani.nikula at linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> Cc: intel-gfx at lists.freedesktop.org Cc: <stable at vger.kernel.org> # v4.17+ Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-3-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-3-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-3-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-3-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-3-sean at poorly.run #v6 Changes in v2: -Added to the set Changes in v3: -None I had previously agreed that clearing the rep_ctl bits on enable would also be a good idea. However when I committed that idea to code, it didn't look right. So let's rely on enables and disables being paired and everything outside of that will be considered a bug Changes in v4: -s/I915_(READ|WRITE)/intel_de_(read|write)/ Changes in v5: -None Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_hdcp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index f26fee3b4624..9f530b2f3606 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -795,6 +795,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) struct intel_hdcp *hdcp = &connector->hdcp; enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; + u32 repeater_ctl; int ret; drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n", @@ -810,6 +811,11 @@ static int _intel_hdcp_disable(struct intel_connector *connector) return -ETIMEDOUT; } + repeater_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, + port); + intel_de_write(dev_priv, HDCP_REP_CTL, + intel_de_read(dev_priv, HDCP_REP_CTL) & ~repeater_ctl); + ret = hdcp->shim->toggle_signalling(intel_dig_port, false); if (ret) { drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n"); -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:53 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:53 -0400 Subject: [Intel-gfx] [PATCH v7 03/17] drm/i915: WARN if HDCP signalling is enabled upon disable In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-4-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> HDCP signalling should not be left on, WARN if it is Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Daniel Vetter <daniel.vetter at ffwll.ch> Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-4-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-4-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-4-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-4-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-4-sean at poorly.run #v6 Changes in v2: -Added to the set in lieu of just clearing the bit Changes in v3: -None Changes in v4: -None Changes in v5: -Change WARN_ON to drm_WARN_ON Changes in v6: -None Changes in v7: -Rebased, variable name changed from 'ctl' to 'val' --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 73d6cc29291a..8a03c58cbd31 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1708,6 +1708,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); + drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); + ctl &= ~TRANS_DDI_FUNC_ENABLE; if (IS_GEN_RANGE(dev_priv, 8, 10)) -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:54 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:54 -0400 Subject: [Intel-gfx] [PATCH v7 04/17] drm/i915: Intercept Aksv writes in the aux hooks In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-5-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Instead of hand rolling the transfer ourselves in the hdcp hook, inspect aux messages and add the aksv flag in the aux transfer hook. IIRC, this was the original implementation and folks wanted this hack to be isolated to the hdcp code, which makes sense. However in testing an LG monitor on my desk, I noticed it was passing back a DEFER reply. This wasn't handled in our hand-rolled code and HDCP auth was failing as a result. Instead of copy/pasting all of the retry logic and delays from drm dp helpers, let's just use the helpers and hide the aksv select as best as we can. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-3-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-5-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-5-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-5-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-5-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-5-sean at poorly.run #v6 Changes in v2: -Remove 'generate' in intel_dp_aux_generate_xfer_flags, make arg const (Ville) -Bundle Aksv if statement together (Ville) -Rename 'txbuf' to 'aksv' (Ville) Changes in v3: -None Changes in v4: -None Changes in v5: -None Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_dp.c | 63 ++++++++++++------------- 1 file changed, 29 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3df5d901dd9d..b30846e9e634 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1563,6 +1563,20 @@ intel_dp_aux_header(u8 txbuf[HEADER_SIZE], txbuf[3] = msg->size - 1; } +static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) +{ + /* + * If we're trying to send the HDCP Aksv, we need to set a the Aksv + * select bit to inform the hardware to send the Aksv after our header + * since we can't access that data from software. + */ + if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && + msg->address == DP_AUX_HDCP_AKSV) + return DP_AUX_CH_CTL_AUX_AKSV_SELECT; + + return 0; +} + static ssize_t intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) { @@ -1570,6 +1584,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 txbuf[20], rxbuf[20]; size_t txsize, rxsize; + u32 flags = intel_dp_aux_xfer_flags(msg); int ret; intel_dp_aux_header(txbuf, msg); @@ -1590,7 +1605,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, - rxbuf, rxsize, 0); + rxbuf, rxsize, flags); if (ret > 0) { msg->reply = rxbuf[0] >> 4; @@ -1613,7 +1628,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) return -E2BIG; ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, - rxbuf, rxsize, 0); + rxbuf, rxsize, flags); if (ret > 0) { msg->reply = rxbuf[0] >> 4; /* @@ -6398,17 +6413,9 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, u8 *an) { struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base)); - static const struct drm_dp_aux_msg msg = { - .request = DP_AUX_NATIVE_WRITE, - .address = DP_AUX_HDCP_AKSV, - .size = DRM_HDCP_KSV_LEN, - }; - u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0; + u8 aksv[DRM_HDCP_KSV_LEN] = {}; ssize_t dpcd_ret; - int ret; - /* Output An first, that's easy */ dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, an, DRM_HDCP_AN_LEN); if (dpcd_ret != DRM_HDCP_AN_LEN) { @@ -6419,31 +6426,19 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, } /* - * Since Aksv is Oh-So-Secret, we can't access it in software. So in - * order to get it on the wire, we need to create the AUX header as if - * we were writing the data, and then tickle the hardware to output the - * data once the header is sent out. + * Since Aksv is Oh-So-Secret, we can't access it in software. So we + * send an empty buffer of the correct length through the DP helpers. On + * the other side, in the transfer hook, we'll generate a flag based on + * the destination address which will tickle the hardware to output the + * Aksv on our behalf after the header is sent. */ - intel_dp_aux_header(txbuf, &msg); - - ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size, - rxbuf, sizeof(rxbuf), - DP_AUX_CH_CTL_AUX_AKSV_SELECT); - if (ret < 0) { - drm_dbg_kms(&i915->drm, - "Write Aksv over DP/AUX failed (%d)\n", ret); - return ret; - } else if (ret == 0) { - drm_dbg_kms(&i915->drm, "Aksv write over DP/AUX was empty\n"); - return -EIO; - } - - reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK; - if (reply != DP_AUX_NATIVE_REPLY_ACK) { + dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AKSV, + aksv, DRM_HDCP_KSV_LEN); + if (dpcd_ret != DRM_HDCP_KSV_LEN) { drm_dbg_kms(&i915->drm, - "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n", - reply); - return -EIO; + "Failed to write Aksv over DP/AUX (%zd)\n", + dpcd_ret); + return dpcd_ret >= 0 ? -EIO : dpcd_ret; } return 0; } -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:55 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:55 -0400 Subject: [Intel-gfx] [PATCH v7 05/17] drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signalling In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-6-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Instead of using intel_dig_port's encoder pipe to determine which transcoder to toggle signalling on, use the cpu_transcoder field already stored in intel_hdmi. This is particularly important for MST. Suggested-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-6-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-6-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-6-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-6-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-6-sean at poorly.run #v6 Changes in v2: -Added to the set Changes in v3: -s/hdcp/hdmi/ in commit msg (Ram) Changes in v4: -Rebased on intel_de_(read|write) change Changes in v5: -Update hdcp->cpu_transcoder in intel_hdcp_enable so it works with pipe != 0 Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 +++---------- drivers/gpu/drm/i915/display/intel_ddi.h | 2 ++ .../gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 1 + drivers/gpu/drm/i915/display/intel_hdcp.c | 16 +++++++++------- drivers/gpu/drm/i915/display/intel_hdmi.c | 16 +++++++++++----- 6 files changed, 27 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 8a03c58cbd31..4153a0d1e07d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1737,12 +1737,12 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state } int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, + enum transcoder cpu_transcoder, bool enable) { struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); intel_wakeref_t wakeref; - enum pipe pipe = 0; int ret = 0; u32 tmp; @@ -1751,19 +1751,12 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, if (drm_WARN_ON(dev, !wakeref)) return -ENXIO; - if (drm_WARN_ON(dev, - !intel_encoder->get_hw_state(intel_encoder, &pipe))) { - ret = -EIO; - goto out; - } - - tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); + tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); if (enable) tmp |= TRANS_DDI_HDCP_SIGNALLING; else tmp &= ~TRANS_DDI_HDCP_SIGNALLING; - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); -out: + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 077e9dbbe367..f5fb62fc9400 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -16,6 +16,7 @@ struct intel_crtc_state; struct intel_dp; struct intel_dpll_hw_state; struct intel_encoder; +enum transcoder; void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, struct intel_encoder *intel_encoder, @@ -43,6 +44,7 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, u32 bxt_signal_levels(struct intel_dp *intel_dp); u32 ddi_signal_levels(struct intel_dp *intel_dp); int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, + enum transcoder cpu_transcoder, bool enable); void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..fc0befd55420 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -314,6 +314,7 @@ struct intel_hdcp_shim { /* Enables HDCP signalling on the port */ int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, + enum transcoder cpu_transcoder, bool enable); /* Ensures the link is still protected */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b30846e9e634..d0fea51f5dec 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6597,6 +6597,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, static int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, + enum transcoder cpu_transcoder, bool enable) { /* Not used for single stream DisplayPort setups */ diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 9f530b2f3606..39715abf2ce4 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -713,7 +713,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) intel_de_write(dev_priv, HDCP_REP_CTL, intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port)); - ret = shim->toggle_signalling(intel_dig_port, true); + ret = shim->toggle_signalling(intel_dig_port, cpu_transcoder, true); if (ret) return ret; @@ -816,7 +816,8 @@ static int _intel_hdcp_disable(struct intel_connector *connector) intel_de_write(dev_priv, HDCP_REP_CTL, intel_de_read(dev_priv, HDCP_REP_CTL) & ~repeater_ctl); - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); + ret = hdcp->shim->toggle_signalling(intel_dig_port, cpu_transcoder, + false); if (ret) { drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n"); return ret; @@ -1600,7 +1601,8 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & LINK_ENCRYPTION_STATUS); if (hdcp->shim->toggle_signalling) { - ret = hdcp->shim->toggle_signalling(intel_dig_port, true); + ret = hdcp->shim->toggle_signalling(intel_dig_port, + cpu_transcoder, true); if (ret) { drm_err(&dev_priv->drm, "Failed to enable HDCP signalling. %d\n", @@ -1650,7 +1652,8 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout"); if (hdcp->shim->toggle_signalling) { - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); + ret = hdcp->shim->toggle_signalling(intel_dig_port, + cpu_transcoder, false); if (ret) { drm_err(&dev_priv->drm, "Failed to disable HDCP signalling. %d\n", @@ -2036,11 +2039,10 @@ int intel_hdcp_enable(struct intel_connector *connector, drm_WARN_ON(&dev_priv->drm, hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); hdcp->content_type = content_type; + hdcp->cpu_transcoder = cpu_transcoder; - if (INTEL_GEN(dev_priv) >= 12) { - hdcp->cpu_transcoder = cpu_transcoder; + if (INTEL_GEN(dev_priv) >= 12) hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder); - } /* * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a31a98d26882..ab7bddf0dfdc 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1477,7 +1477,8 @@ int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, return ret; } -static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) +static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, + enum transcoder cpu_transcoder) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); @@ -1494,13 +1495,15 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) usleep_range(25, 50); } - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); + ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, + cpu_transcoder, false); if (ret) { drm_err(&dev_priv->drm, "Disable HDCP signalling failed (%d)\n", ret); return ret; } - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); + ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, + cpu_transcoder, true); if (ret) { drm_err(&dev_priv->drm, "Enable HDCP signalling failed (%d)\n", ret); @@ -1512,6 +1515,7 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) static int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, + enum transcoder cpu_transcoder, bool enable) { struct intel_hdmi *hdmi = &intel_dig_port->hdmi; @@ -1522,7 +1526,8 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, if (!enable) usleep_range(6, 60); /* Bspec says >= 6us */ - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); + ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, + cpu_transcoder, enable); if (ret) { drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", enable ? "Enable" : "Disable", ret); @@ -1534,7 +1539,8 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, * opportunity and enc_en signalling in KABYLAKE. */ if (IS_KABYLAKE(dev_priv) && enable) - return kbl_repositioning_enc_en_signal(connector); + return kbl_repositioning_enc_en_signal(connector, + cpu_transcoder); return 0; } -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:56 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:56 -0400 Subject: [Intel-gfx] [PATCH v7 06/17] drm/i915: Factor out hdcp->value assignments In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-7-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> This is a bit of housecleaning for a future patch. Instead of sprinkling hdcp->value assignments and prop_work scheduling everywhere, introduce a function to do it for us. Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-7-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-7-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-7-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-7-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-7-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-7-sean at poorly.run #v6 Changes in v2: -None Changes in v3: -None Changes in v4: -Rebased on top of drm_* logging changes Changes in v5: -Change WARN_ON to drm_WARN_ON Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_hdcp.c | 67 ++++++++++++++++------- 1 file changed, 46 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 39715abf2ce4..88500a0bd77e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -877,6 +877,21 @@ static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) return container_of(hdcp, struct intel_connector, hdcp); } +static void intel_hdcp_update_value(struct intel_connector *connector, + u64 value, bool update_property) +{ + struct intel_hdcp *hdcp = &connector->hdcp; + + drm_WARN_ON(connector->base.dev, !mutex_is_locked(&hdcp->mutex)); + + if (hdcp->value == value) + return; + + hdcp->value = value; + if (update_property) + schedule_work(&hdcp->prop_work); +} + /* Implements Part 3 of the HDCP authorization procedure */ static int intel_hdcp_check_link(struct intel_connector *connector) { @@ -904,15 +919,16 @@ static int intel_hdcp_check_link(struct intel_connector *connector) connector->base.name, connector->base.base.id, intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port))); ret = -ENXIO; - hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_DESIRED, + true); goto out; } if (hdcp->shim->check_link(intel_dig_port)) { if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { - hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, true); } goto out; } @@ -924,16 +940,18 @@ static int intel_hdcp_check_link(struct intel_connector *connector) ret = _intel_hdcp_disable(connector); if (ret) { drm_err(&dev_priv->drm, "Failed to disable hdcp (%d)\n", ret); - hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_DESIRED, + true); goto out; } ret = _intel_hdcp_enable(connector); if (ret) { drm_err(&dev_priv->drm, "Failed to enable hdcp (%d)\n", ret); - hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_DESIRED, + true); goto out; } @@ -1769,16 +1787,18 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) "HDCP2.2 link stopped the encryption, %x\n", intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port))); ret = -ENXIO; - hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_DESIRED, + true); goto out; } ret = hdcp->shim->check_2_2_link(intel_dig_port); if (ret == HDCP_LINK_PROTECTED) { if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { - hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, + true); } goto out; } @@ -1791,8 +1811,9 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) "HDCP2.2 Downstream topology change\n"); ret = hdcp2_authenticate_repeater_topology(connector); if (!ret) { - hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, + true); goto out; } drm_dbg_kms(&dev_priv->drm, @@ -1810,8 +1831,8 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) drm_err(&dev_priv->drm, "[%s:%d] Failed to disable hdcp2.2 (%d)\n", connector->base.name, connector->base.base.id, ret); - hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_DESIRED, true); goto out; } @@ -1821,8 +1842,9 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) "[%s:%d] Failed to enable hdcp2.2 (%d)\n", connector->base.name, connector->base.base.id, ret); - hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_DESIRED, + true); goto out; } @@ -2065,8 +2087,9 @@ int intel_hdcp_enable(struct intel_connector *connector, if (!ret) { schedule_delayed_work(&hdcp->check_work, check_link_interval); - hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; - schedule_work(&hdcp->prop_work); + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, + true); } mutex_unlock(&hdcp->mutex); @@ -2084,7 +2107,9 @@ int intel_hdcp_disable(struct intel_connector *connector) mutex_lock(&hdcp->mutex); if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { - hdcp->value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_UNDESIRED, + false); if (hdcp->hdcp2_encrypted) ret = _intel_hdcp2_disable(connector); else if (hdcp->hdcp_encrypted) -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:57 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:57 -0400 Subject: [Intel-gfx] [PATCH v7 07/17] drm/i915: Protect workers against disappearing connectors In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-8-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> This patch adds some protection against connectors being destroyed before the HDCP workers are finished. For check_work, we do a synchronous cancel after the connector is unregistered which will ensure that it is finished before destruction. In the case of prop_work, we can't do a synchronous wait since it needs to take connection_mutex which could cause deadlock. Instead, we'll take a reference on the connector when scheduling prop_work and give it up once we're done. Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-8-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-8-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-8-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-8-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-8-sean at poorly.run #v6 Changes in v2: -Added to the set Changes in v3: -Change the WARN_ON condition in intel_hdcp_cleanup to allow for initializing connectors as well Changes in v4: -None Changes in v5: -Change WARN_ON to drm_WARN_ON Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_hdcp.c | 44 ++++++++++++++++++++--- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 88500a0bd77e..62cab3aea745 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -888,8 +888,10 @@ static void intel_hdcp_update_value(struct intel_connector *connector, return; hdcp->value = value; - if (update_property) + if (update_property) { + drm_connector_get(&connector->base); schedule_work(&hdcp->prop_work); + } } /* Implements Part 3 of the HDCP authorization procedure */ @@ -981,6 +983,8 @@ static void intel_hdcp_prop_work(struct work_struct *work) mutex_unlock(&hdcp->mutex); drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex); + + drm_connector_put(&connector->base); } bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) @@ -1860,6 +1864,9 @@ static void intel_hdcp_check_work(struct work_struct *work) check_work); struct intel_connector *connector = intel_hdcp_to_connector(hdcp); + if (drm_connector_is_unregistered(&connector->base)) + return; + if (!intel_hdcp2_check_link(connector)) schedule_delayed_work(&hdcp->check_work, DRM_HDCP2_CHECK_PERIOD_MS); @@ -2178,12 +2185,39 @@ void intel_hdcp_component_fini(struct drm_i915_private *dev_priv) void intel_hdcp_cleanup(struct intel_connector *connector) { - if (!connector->hdcp.shim) + struct intel_hdcp *hdcp = &connector->hdcp; + + if (!hdcp->shim) return; - mutex_lock(&connector->hdcp.mutex); - kfree(connector->hdcp.port_data.streams); - mutex_unlock(&connector->hdcp.mutex); + /* + * If the connector is registered, it's possible userspace could kick + * off another HDCP enable, which would re-spawn the workers. + */ + drm_WARN_ON(connector->base.dev, + connector->base.registration_state == DRM_CONNECTOR_REGISTERED); + + /* + * Now that the connector is not registered, check_work won't be run, + * but cancel any outstanding instances of it + */ + cancel_delayed_work_sync(&hdcp->check_work); + + /* + * We don't cancel prop_work in the same way as check_work since it + * requires connection_mutex which could be held while calling this + * function. Instead, we rely on the connector references grabbed before + * scheduling prop_work to ensure the connector is alive when prop_work + * is run. So if we're in the destroy path (which is where this + * function should be called), we're "guaranteed" that prop_work is not + * active (tl;dr This Should Never Happen). + */ + drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); + + mutex_lock(&hdcp->mutex); + kfree(hdcp->port_data.streams); + hdcp->shim = NULL; + mutex_unlock(&hdcp->mutex); } void intel_hdcp_atomic_check(struct drm_connector *connector, -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:59 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:59 -0400 Subject: [Intel-gfx] [PATCH v7 09/17] drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-10-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> This patch is required for HDCP over MST. If a port is being used for multiple HDCP streams, we don't want to fully disable HDCP on a port if one of them is disabled. Instead, we just disable the HDCP signalling on that particular pipe and exit early. The last pipe to disable HDCP will also bring down HDCP on the port. In order to achieve this, we need to keep a refcount in intel_digital_port and protect it using a new hdcp_mutex. Cc: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-8-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-9-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-9-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-9-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-9-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-9-sean at poorly.run #v6 Changes in v2: -Move the toggle_signalling call into _intel_hdcp_disable so it's called from check_work Changes in v3: -None Changes in v4: -None Changes in v5: -Change WARN_ON to drm_WARN_ON Changes in v6: -None Changes in v7: -Split minor intel_hdcp_disable refactor into separate patch (Ramalingam) --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++ .../drm/i915/display/intel_display_types.h | 5 +++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ drivers/gpu/drm/i915/display/intel_hdcp.c | 33 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_hdmi.c | 2 ++ 5 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4153a0d1e07d..536299f902b9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4884,6 +4884,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); + mutex_init(&intel_dig_port->hdcp_mutex); + intel_dig_port->num_hdcp_streams = 0; + encoder->hotplug = intel_ddi_hotplug; encoder->compute_output_type = intel_ddi_compute_output_type; encoder->compute_config = intel_ddi_compute_config; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index fc0befd55420..1503403a808b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1410,6 +1410,11 @@ struct intel_digital_port { enum phy_fia tc_phy_fia; u8 tc_phy_fia_idx; + /* protects num_hdcp_streams reference count */ + struct mutex hdcp_mutex; + /* the number of pipes using HDCP signalling out of this port */ + unsigned int num_hdcp_streams; + void (*write_infoframe)(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d0fea51f5dec..d98e45a09c28 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -8276,6 +8276,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, intel_encoder = &intel_dig_port->base; encoder = &intel_encoder->base; + mutex_init(&intel_dig_port->hdcp_mutex); + if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 16bf0fbe5f17..5679877c6b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -801,6 +801,19 @@ static int _intel_hdcp_disable(struct intel_connector *connector) drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n", connector->base.name, connector->base.base.id); + /* + * If there are other connectors on this port using HDCP, don't disable + * it. Instead, toggle the HDCP signalling off on that particular + * connector/pipe and exit. + */ + if (intel_dig_port->num_hdcp_streams > 0) { + ret = hdcp->shim->toggle_signalling(intel_dig_port, + cpu_transcoder, false); + if (ret) + DRM_ERROR("Failed to disable HDCP signalling\n"); + return ret; + } + hdcp->hdcp_encrypted = false; intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0); if (intel_de_wait_for_clear(dev_priv, @@ -880,6 +893,8 @@ static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) static void intel_hdcp_update_value(struct intel_connector *connector, u64 value, bool update_property) { + struct drm_device *dev = connector->base.dev; + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; drm_WARN_ON(connector->base.dev, !mutex_is_locked(&hdcp->mutex)); @@ -887,6 +902,15 @@ static void intel_hdcp_update_value(struct intel_connector *connector, if (hdcp->value == value) return; + drm_WARN_ON(dev, !mutex_is_locked(&intel_dig_port->hdcp_mutex)); + + if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { + if (!drm_WARN_ON(dev, intel_dig_port->num_hdcp_streams == 0)) + intel_dig_port->num_hdcp_streams--; + } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { + intel_dig_port->num_hdcp_streams++; + } + hdcp->value = value; if (update_property) { drm_connector_get(&connector->base); @@ -905,6 +929,8 @@ static int intel_hdcp_check_link(struct intel_connector *connector) int ret = 0; mutex_lock(&hdcp->mutex); + mutex_lock(&intel_dig_port->hdcp_mutex); + cpu_transcoder = hdcp->cpu_transcoder; /* Check_link valid only when HDCP1.4 is enabled */ @@ -958,6 +984,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) } out: + mutex_unlock(&intel_dig_port->hdcp_mutex); mutex_unlock(&hdcp->mutex); return ret; } @@ -2057,6 +2084,7 @@ int intel_hdcp_enable(struct intel_connector *connector, enum transcoder cpu_transcoder, u8 content_type) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; int ret = -EINVAL; @@ -2065,6 +2093,7 @@ int intel_hdcp_enable(struct intel_connector *connector, return -ENOENT; mutex_lock(&hdcp->mutex); + mutex_lock(&intel_dig_port->hdcp_mutex); drm_WARN_ON(&dev_priv->drm, hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); hdcp->content_type = content_type; @@ -2099,12 +2128,14 @@ int intel_hdcp_enable(struct intel_connector *connector, true); } + mutex_unlock(&intel_dig_port->hdcp_mutex); mutex_unlock(&hdcp->mutex); return ret; } int intel_hdcp_disable(struct intel_connector *connector) { + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; int ret = 0; @@ -2112,6 +2143,7 @@ int intel_hdcp_disable(struct intel_connector *connector) return -ENOENT; mutex_lock(&hdcp->mutex); + mutex_lock(&intel_dig_port->hdcp_mutex); if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) goto out; @@ -2124,6 +2156,7 @@ int intel_hdcp_disable(struct intel_connector *connector) ret = _intel_hdcp_disable(connector); out: + mutex_unlock(&intel_dig_port->hdcp_mutex); mutex_unlock(&hdcp->mutex); cancel_delayed_work_sync(&hdcp->check_work); return ret; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ab7bddf0dfdc..a59acfff456e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3331,6 +3331,8 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, intel_encoder = &intel_dig_port->base; + mutex_init(&intel_dig_port->hdcp_mutex); + drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port)); -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:00 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:00 -0400 Subject: [Intel-gfx] [PATCH v7 10/17] drm/i915: Support DP MST in enc_to_dig_port() function In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-11-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Although DP_MST fake encoders are not subclassed from digital ports, they are associated with them. Support these encoders. Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-9-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-10-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-10-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-10-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-10-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-10-sean at poorly.run #v6 Changes in v2: -None Changes in v3: -None Changes in v4: -None Changes in v5: -None Changes in v6: -None Changes in v7: -None --- .../drm/i915/display/intel_display_types.h | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1503403a808b..811085ef3fba 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1525,6 +1525,18 @@ static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) } } +static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) +{ + return encoder->type == INTEL_OUTPUT_DP_MST; +} + +static inline struct intel_dp_mst_encoder * +enc_to_mst(struct intel_encoder *encoder) +{ + return container_of(&encoder->base, struct intel_dp_mst_encoder, + base.base); +} + static inline struct intel_digital_port * enc_to_dig_port(struct intel_encoder *encoder) { @@ -1533,6 +1545,8 @@ enc_to_dig_port(struct intel_encoder *encoder) if (intel_encoder_is_dig_port(intel_encoder)) return container_of(&encoder->base, struct intel_digital_port, base.base); + else if (intel_encoder_is_mst(intel_encoder)) + return enc_to_mst(encoder)->primary; else return NULL; } @@ -1543,13 +1557,6 @@ intel_attached_dig_port(struct intel_connector *connector) return enc_to_dig_port(intel_attached_encoder(connector)); } -static inline struct intel_dp_mst_encoder * -enc_to_mst(struct intel_encoder *encoder) -{ - return container_of(&encoder->base, struct intel_dp_mst_encoder, - base.base); -} - static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) { return &enc_to_dig_port(encoder)->dp; -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:01 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:01 -0400 Subject: [Intel-gfx] [PATCH v7 11/17] drm/i915: Use ddi_update_pipe in intel_dp_mst In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-12-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> In order to act upon content_protection property changes, we'll need to implement the .update_pipe() hook. We can re-use intel_ddi_update_pipe for this Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-10-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-11-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-11-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-11-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-11-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-11-sean at poorly.run #v6 Changes in v2: -None Changes in v3: -None Changes in v4: -None Changes in v5: -None Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_dp.h | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 536299f902b9..29f1f552e8d8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3907,13 +3907,14 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, intel_panel_update_backlight(state, encoder, crtc_state, conn_state); } -static void intel_ddi_update_pipe(struct intel_atomic_state *state, - struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) +void intel_ddi_update_pipe(struct intel_atomic_state *state, + struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && + !intel_encoder_is_mst(encoder)) intel_ddi_update_pipe_dp(state, encoder, crtc_state, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..6352c7e97e3b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -17,6 +17,7 @@ struct drm_encoder; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct drm_dp_vsc_sdp; +struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; struct intel_digital_port; @@ -128,4 +129,9 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count) u32 intel_dp_mode_to_fec_clock(u32 mode_clock); +void intel_ddi_update_pipe(struct intel_atomic_state *state, + struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); + #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 9308b5920780..0675825dcc20 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -836,6 +836,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum intel_encoder->compute_config_late = intel_dp_mst_compute_config_late; intel_encoder->disable = intel_mst_disable_dp; intel_encoder->post_disable = intel_mst_post_disable_dp; + intel_encoder->update_pipe = intel_ddi_update_pipe; intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp; intel_encoder->pre_enable = intel_mst_pre_enable_dp; intel_encoder->enable = intel_mst_enable_dp; -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:58:58 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:58:58 -0400 Subject: [Intel-gfx] [PATCH v7 08/17] drm/i915: Clean up intel_hdcp_disable In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-9-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Add an out label and un-indent hdcp disable in preparation for hdcp_mutex. No functional changes Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-9-sean at poorly.run #v6 Changes in v7: -Split into separate patch (Ramalingam) --- drivers/gpu/drm/i915/display/intel_hdcp.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 62cab3aea745..16bf0fbe5f17 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2113,16 +2113,17 @@ int intel_hdcp_disable(struct intel_connector *connector) mutex_lock(&hdcp->mutex); - if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { - intel_hdcp_update_value(connector, - DRM_MODE_CONTENT_PROTECTION_UNDESIRED, - false); - if (hdcp->hdcp2_encrypted) - ret = _intel_hdcp2_disable(connector); - else if (hdcp->hdcp_encrypted) - ret = _intel_hdcp_disable(connector); - } + if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) + goto out; + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); + if (hdcp->hdcp2_encrypted) + ret = _intel_hdcp2_disable(connector); + else if (hdcp->hdcp_encrypted) + ret = _intel_hdcp_disable(connector); + +out: mutex_unlock(&hdcp->mutex); cancel_delayed_work_sync(&hdcp->check_work); return ret; -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:02 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:02 -0400 Subject: [Intel-gfx] [PATCH v7 12/17] drm/i915: Factor out HDCP shim functions from dp for use by dp_mst In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-13-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> These functions are all the same for dp and dp_mst, so move them into a dedicated file for both sst and mst to use. Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-11-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-12-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-12-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-12-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-12-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-12-sean at poorly.run #v6 Changes in v2: -None Changes in v3: -Created intel_dp_hdcp.c for the shared functions to live (Ville) Changes in v4: -Rebased on new drm logging change Changes in v5: -None Changes in v6: -None Changes in v7: -Rebased patch --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 606 +----------------- drivers/gpu/drm/i915/display/intel_dp.h | 3 + drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 636 +++++++++++++++++++ 4 files changed, 641 insertions(+), 605 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 41a27fd5dbc7..cba4ddb95ab1 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -233,6 +233,7 @@ i915-y += \ display/intel_ddi.o \ display/intel_dp.o \ display/intel_dp_aux_backlight.o \ + display/intel_dp_hdcp.o \ display/intel_dp_link_training.o \ display/intel_dp_mst.o \ display/intel_dsi.o \ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d98e45a09c28..78ce5e41d559 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -38,7 +38,6 @@ #include <drm/drm_crtc.h> #include <drm/drm_dp_helper.h> #include <drm/drm_edid.h> -#include <drm/drm_hdcp.h> #include <drm/drm_probe_helper.h> #include "i915_debugfs.h" @@ -6396,609 +6395,6 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) edp_panel_vdd_off_sync(intel_dp); } -static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) -{ - long ret; - -#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) - ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, - msecs_to_jiffies(timeout)); - - if (!ret) - DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); -} - -static -int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, - u8 *an) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - u8 aksv[DRM_HDCP_KSV_LEN] = {}; - ssize_t dpcd_ret; - - dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, - an, DRM_HDCP_AN_LEN); - if (dpcd_ret != DRM_HDCP_AN_LEN) { - drm_dbg_kms(&i915->drm, - "Failed to write An over DP/AUX (%zd)\n", - dpcd_ret); - return dpcd_ret >= 0 ? -EIO : dpcd_ret; - } - - /* - * Since Aksv is Oh-So-Secret, we can't access it in software. So we - * send an empty buffer of the correct length through the DP helpers. On - * the other side, in the transfer hook, we'll generate a flag based on - * the destination address which will tickle the hardware to output the - * Aksv on our behalf after the header is sent. - */ - dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AKSV, - aksv, DRM_HDCP_KSV_LEN); - if (dpcd_ret != DRM_HDCP_KSV_LEN) { - drm_dbg_kms(&i915->drm, - "Failed to write Aksv over DP/AUX (%zd)\n", - dpcd_ret); - return dpcd_ret >= 0 ? -EIO : dpcd_ret; - } - return 0; -} - -static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, - u8 *bksv) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, - DRM_HDCP_KSV_LEN); - if (ret != DRM_HDCP_KSV_LEN) { - drm_dbg_kms(&i915->drm, - "Read Bksv from DP/AUX failed (%zd)\n", ret); - return ret >= 0 ? -EIO : ret; - } - return 0; -} - -static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, - u8 *bstatus) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - - /* - * For some reason the HDMI and DP HDCP specs call this register - * definition by different names. In the HDMI spec, it's called BSTATUS, - * but in DP it's called BINFO. - */ - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, - bstatus, DRM_HDCP_BSTATUS_LEN); - if (ret != DRM_HDCP_BSTATUS_LEN) { - drm_dbg_kms(&i915->drm, - "Read bstatus from DP/AUX failed (%zd)\n", ret); - return ret >= 0 ? -EIO : ret; - } - return 0; -} - -static -int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, - u8 *bcaps) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, - bcaps, 1); - if (ret != 1) { - drm_dbg_kms(&i915->drm, - "Read bcaps from DP/AUX failed (%zd)\n", ret); - return ret >= 0 ? -EIO : ret; - } - - return 0; -} - -static -int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, - bool *repeater_present) -{ - ssize_t ret; - u8 bcaps; - - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); - if (ret) - return ret; - - *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; - return 0; -} - -static -int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, - u8 *ri_prime) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, - ri_prime, DRM_HDCP_RI_LEN); - if (ret != DRM_HDCP_RI_LEN) { - drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", - ret); - return ret >= 0 ? -EIO : ret; - } - return 0; -} - -static -int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, - bool *ksv_ready) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - u8 bstatus; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, - &bstatus, 1); - if (ret != 1) { - drm_dbg_kms(&i915->drm, - "Read bstatus from DP/AUX failed (%zd)\n", ret); - return ret >= 0 ? -EIO : ret; - } - *ksv_ready = bstatus & DP_BSTATUS_READY; - return 0; -} - -static -int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, - int num_downstream, u8 *ksv_fifo) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - int i; - - /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ - for (i = 0; i < num_downstream; i += 3) { - size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, - DP_AUX_HDCP_KSV_FIFO, - ksv_fifo + i * DRM_HDCP_KSV_LEN, - len); - if (ret != len) { - drm_dbg_kms(&i915->drm, - "Read ksv[%d] from DP/AUX failed (%zd)\n", - i, ret); - return ret >= 0 ? -EIO : ret; - } - } - return 0; -} - -static -int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, - int i, u32 *part) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - - if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) - return -EINVAL; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, - DP_AUX_HDCP_V_PRIME(i), part, - DRM_HDCP_V_PRIME_PART_LEN); - if (ret != DRM_HDCP_V_PRIME_PART_LEN) { - drm_dbg_kms(&i915->drm, - "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); - return ret >= 0 ? -EIO : ret; - } - return 0; -} - -static -int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, - enum transcoder cpu_transcoder, - bool enable) -{ - /* Not used for single stream DisplayPort setups */ - return 0; -} - -static -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - u8 bstatus; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, - &bstatus, 1); - if (ret != 1) { - drm_dbg_kms(&i915->drm, - "Read bstatus from DP/AUX failed (%zd)\n", ret); - return false; - } - - return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); -} - -static -int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, - bool *hdcp_capable) -{ - ssize_t ret; - u8 bcaps; - - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); - if (ret) - return ret; - - *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; - return 0; -} - -struct hdcp2_dp_errata_stream_type { - u8 msg_id; - u8 stream_type; -} __packed; - -struct hdcp2_dp_msg_data { - u8 msg_id; - u32 offset; - bool msg_detectable; - u32 timeout; - u32 timeout2; /* Added for non_paired situation */ -}; - -static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { - { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 }, - { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, - false, HDCP_2_2_CERT_TIMEOUT_MS, 0 }, - { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, - false, 0, 0 }, - { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, - false, 0, 0 }, - { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, - true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, - HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS }, - { HDCP_2_2_AKE_SEND_PAIRING_INFO, - DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, - HDCP_2_2_PAIRING_TIMEOUT_MS, 0 }, - { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 }, - { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, - false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 }, - { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, - 0, 0 }, - { HDCP_2_2_REP_SEND_RECVID_LIST, - DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, - HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 }, - { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, - 0, 0 }, - { HDCP_2_2_REP_STREAM_MANAGE, - DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, - 0, 0 }, - { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, - false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 }, -/* local define to shovel this through the write_2_2 interface */ -#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 - { HDCP_2_2_ERRATA_DP_STREAM_TYPE, - DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, - 0, 0 }, -}; - -static int -intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, - u8 *rx_status) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - ssize_t ret; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, - DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, - HDCP_2_2_DP_RXSTATUS_LEN); - if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { - drm_dbg_kms(&i915->drm, - "Read bstatus from DP/AUX failed (%zd)\n", ret); - return ret >= 0 ? -EIO : ret; - } - - return 0; -} - -static -int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, - u8 msg_id, bool *msg_ready) -{ - u8 rx_status; - int ret; - - *msg_ready = false; - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); - if (ret < 0) - return ret; - - switch (msg_id) { - case HDCP_2_2_AKE_SEND_HPRIME: - if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) - *msg_ready = true; - break; - case HDCP_2_2_AKE_SEND_PAIRING_INFO: - if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) - *msg_ready = true; - break; - case HDCP_2_2_REP_SEND_RECVID_LIST: - if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) - *msg_ready = true; - break; - default: - DRM_ERROR("Unidentified msg_id: %d\n", msg_id); - return -EINVAL; - } - - return 0; -} - -static ssize_t -intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, - const struct hdcp2_dp_msg_data *hdcp2_msg_data) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *dp = &intel_dig_port->dp; - struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; - u8 msg_id = hdcp2_msg_data->msg_id; - int ret, timeout; - bool msg_ready = false; - - if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) - timeout = hdcp2_msg_data->timeout2; - else - timeout = hdcp2_msg_data->timeout; - - /* - * There is no way to detect the CERT, LPRIME and STREAM_READY - * availability. So Wait for timeout and read the msg. - */ - if (!hdcp2_msg_data->msg_detectable) { - mdelay(timeout); - ret = 0; - } else { - /* - * As we want to check the msg availability at timeout, Ignoring - * the timeout at wait for CP_IRQ. - */ - intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); - ret = hdcp2_detect_msg_availability(intel_dig_port, - msg_id, &msg_ready); - if (!msg_ready) - ret = -ETIMEDOUT; - } - - if (ret) - drm_dbg_kms(&i915->drm, - "msg_id %d, ret %d, timeout(mSec): %d\n", - hdcp2_msg_data->msg_id, ret, timeout); - - return ret; -} - -static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) - if (hdcp2_dp_msg_data[i].msg_id == msg_id) - return &hdcp2_dp_msg_data[i]; - - return NULL; -} - -static -int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, - void *buf, size_t size) -{ - struct intel_dp *dp = &intel_dig_port->dp; - struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; - unsigned int offset; - u8 *byte = buf; - ssize_t ret, bytes_to_write, len; - const struct hdcp2_dp_msg_data *hdcp2_msg_data; - - hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); - if (!hdcp2_msg_data) - return -EINVAL; - - offset = hdcp2_msg_data->offset; - - /* No msg_id in DP HDCP2.2 msgs */ - bytes_to_write = size - 1; - byte++; - - hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); - - while (bytes_to_write) { - len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? - DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; - - ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, - offset, (void *)byte, len); - if (ret < 0) - return ret; - - bytes_to_write -= ret; - byte += ret; - offset += ret; - } - - return size; -} - -static -ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) -{ - u8 rx_info[HDCP_2_2_RXINFO_LEN]; - u32 dev_cnt; - ssize_t ret; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, - DP_HDCP_2_2_REG_RXINFO_OFFSET, - (void *)rx_info, HDCP_2_2_RXINFO_LEN); - if (ret != HDCP_2_2_RXINFO_LEN) - return ret >= 0 ? -EIO : ret; - - dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | - HDCP_2_2_DEV_COUNT_LO(rx_info[1])); - - if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) - dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; - - ret = sizeof(struct hdcp2_rep_send_receiverid_list) - - HDCP_2_2_RECEIVER_IDS_MAX_LEN + - (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); - - return ret; -} - -static -int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, - u8 msg_id, void *buf, size_t size) -{ - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - unsigned int offset; - u8 *byte = buf; - ssize_t ret, bytes_to_recv, len; - const struct hdcp2_dp_msg_data *hdcp2_msg_data; - - hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); - if (!hdcp2_msg_data) - return -EINVAL; - offset = hdcp2_msg_data->offset; - - ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); - if (ret < 0) - return ret; - - if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { - ret = get_receiver_id_list_size(intel_dig_port); - if (ret < 0) - return ret; - - size = ret; - } - bytes_to_recv = size - 1; - - /* DP adaptation msgs has no msg_id */ - byte++; - - while (bytes_to_recv) { - len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? - DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; - - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, - (void *)byte, len); - if (ret < 0) { - drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", - msg_id, ret); - return ret; - } - - bytes_to_recv -= ret; - byte += ret; - offset += ret; - } - byte = buf; - *byte = msg_id; - - return size; -} - -static -int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, - bool is_repeater, u8 content_type) -{ - int ret; - struct hdcp2_dp_errata_stream_type stream_type_msg; - - if (is_repeater) - return 0; - - /* - * Errata for DP: As Stream type is used for encryption, Receiver - * should be communicated with stream type for the decryption of the - * content. - * Repeater will be communicated with stream type as a part of it's - * auth later in time. - */ - stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; - stream_type_msg.stream_type = content_type; - - ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, - sizeof(stream_type_msg)); - - return ret < 0 ? ret : 0; - -} - -static -int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) -{ - u8 rx_status; - int ret; - - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); - if (ret) - return ret; - - if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) - ret = HDCP_REAUTH_REQUEST; - else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) - ret = HDCP_LINK_INTEGRITY_FAILURE; - else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) - ret = HDCP_TOPOLOGY_CHANGE; - - return ret; -} - -static -int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, - bool *capable) -{ - u8 rx_caps[3]; - int ret; - - *capable = false; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, - DP_HDCP_2_2_REG_RX_CAPS_OFFSET, - rx_caps, HDCP_2_2_RXCAPS_LEN); - if (ret != HDCP_2_2_RXCAPS_LEN) - return ret >= 0 ? -EIO : ret; - - if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && - HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) - *capable = true; - - return 0; -} - -static const struct intel_hdcp_shim intel_dp_hdcp_shim = { - .write_an_aksv = intel_dp_hdcp_write_an_aksv, - .read_bksv = intel_dp_hdcp_read_bksv, - .read_bstatus = intel_dp_hdcp_read_bstatus, - .repeater_present = intel_dp_hdcp_repeater_present, - .read_ri_prime = intel_dp_hdcp_read_ri_prime, - .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, - .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, - .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, - .toggle_signalling = intel_dp_hdcp_toggle_signalling, - .check_link = intel_dp_hdcp_check_link, - .hdcp_capable = intel_dp_hdcp_capable, - .write_2_2_msg = intel_dp_hdcp2_write_msg, - .read_2_2_msg = intel_dp_hdcp2_read_msg, - .config_stream_type = intel_dp_hdcp2_config_stream_type, - .check_2_2_link = intel_dp_hdcp2_check_link, - .hdcp_2_2_capable = intel_dp_hdcp2_capable, - .protocol = HDCP_PROTOCOL_DP, -}; - static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -8232,7 +7628,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp_add_properties(intel_dp, connector); if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { - int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); + int ret = intel_dp_init_hdcp(intel_dig_port, intel_connector); if (ret) drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n"); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6352c7e97e3b..794f25573254 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -134,4 +134,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); +int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port, + struct intel_connector *intel_connector); + #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c new file mode 100644 index 000000000000..0e06a1066d61 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -0,0 +1,636 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2020 Google, Inc. + * + * Authors: + * Sean Paul <seanpaul at chromium.org> + */ + +#include <drm/drm_dp_helper.h> +#include <drm/drm_hdcp.h> +#include <drm/drm_print.h> + +#include "intel_display_types.h" +#include "intel_dp.h" +#include "intel_hdcp.h" + +static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) +{ + long ret; + +#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) + ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, + msecs_to_jiffies(timeout)); + + if (!ret) + DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); +} + +static +int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, + u8 *an) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + u8 aksv[DRM_HDCP_KSV_LEN] = {}; + ssize_t dpcd_ret; + + dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, + an, DRM_HDCP_AN_LEN); + if (dpcd_ret != DRM_HDCP_AN_LEN) { + drm_dbg_kms(&i915->drm, + "Failed to write An over DP/AUX (%zd)\n", + dpcd_ret); + return dpcd_ret >= 0 ? -EIO : dpcd_ret; + } + + /* + * Since Aksv is Oh-So-Secret, we can't access it in software. So we + * send an empty buffer of the correct length through the DP helpers. On + * the other side, in the transfer hook, we'll generate a flag based on + * the destination address which will tickle the hardware to output the + * Aksv on our behalf after the header is sent. + */ + dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AKSV, + aksv, DRM_HDCP_KSV_LEN); + if (dpcd_ret != DRM_HDCP_KSV_LEN) { + drm_dbg_kms(&i915->drm, + "Failed to write Aksv over DP/AUX (%zd)\n", + dpcd_ret); + return dpcd_ret >= 0 ? -EIO : dpcd_ret; + } + return 0; +} + +static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, + u8 *bksv) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, + DRM_HDCP_KSV_LEN); + if (ret != DRM_HDCP_KSV_LEN) { + drm_dbg_kms(&i915->drm, + "Read Bksv from DP/AUX failed (%zd)\n", ret); + return ret >= 0 ? -EIO : ret; + } + return 0; +} + +static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, + u8 *bstatus) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + + /* + * For some reason the HDMI and DP HDCP specs call this register + * definition by different names. In the HDMI spec, it's called BSTATUS, + * but in DP it's called BINFO. + */ + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, + bstatus, DRM_HDCP_BSTATUS_LEN); + if (ret != DRM_HDCP_BSTATUS_LEN) { + drm_dbg_kms(&i915->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); + return ret >= 0 ? -EIO : ret; + } + return 0; +} + +static +int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, + u8 *bcaps) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, + bcaps, 1); + if (ret != 1) { + drm_dbg_kms(&i915->drm, + "Read bcaps from DP/AUX failed (%zd)\n", ret); + return ret >= 0 ? -EIO : ret; + } + + return 0; +} + +static +int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, + bool *repeater_present) +{ + ssize_t ret; + u8 bcaps; + + ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + if (ret) + return ret; + + *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; + return 0; +} + +static +int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, + u8 *ri_prime) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, + ri_prime, DRM_HDCP_RI_LEN); + if (ret != DRM_HDCP_RI_LEN) { + drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", + ret); + return ret >= 0 ? -EIO : ret; + } + return 0; +} + +static +int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, + bool *ksv_ready) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + u8 bstatus; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, + &bstatus, 1); + if (ret != 1) { + drm_dbg_kms(&i915->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); + return ret >= 0 ? -EIO : ret; + } + *ksv_ready = bstatus & DP_BSTATUS_READY; + return 0; +} + +static +int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, + int num_downstream, u8 *ksv_fifo) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + int i; + + /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ + for (i = 0; i < num_downstream; i += 3) { + size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_AUX_HDCP_KSV_FIFO, + ksv_fifo + i * DRM_HDCP_KSV_LEN, + len); + if (ret != len) { + drm_dbg_kms(&i915->drm, + "Read ksv[%d] from DP/AUX failed (%zd)\n", + i, ret); + return ret >= 0 ? -EIO : ret; + } + } + return 0; +} + +static +int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, + int i, u32 *part) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + + if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) + return -EINVAL; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_AUX_HDCP_V_PRIME(i), part, + DRM_HDCP_V_PRIME_PART_LEN); + if (ret != DRM_HDCP_V_PRIME_PART_LEN) { + drm_dbg_kms(&i915->drm, + "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); + return ret >= 0 ? -EIO : ret; + } + return 0; +} + +static +int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, + enum transcoder cpu_transcoder, + bool enable) +{ + /* Not used for single stream DisplayPort setups */ + return 0; +} + +static +bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + u8 bstatus; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, + &bstatus, 1); + if (ret != 1) { + drm_dbg_kms(&i915->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); + return false; + } + + return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); +} + +static +int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, + bool *hdcp_capable) +{ + ssize_t ret; + u8 bcaps; + + ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + if (ret) + return ret; + + *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; + return 0; +} + +struct hdcp2_dp_errata_stream_type { + u8 msg_id; + u8 stream_type; +} __packed; + +struct hdcp2_dp_msg_data { + u8 msg_id; + u32 offset; + bool msg_detectable; + u32 timeout; + u32 timeout2; /* Added for non_paired situation */ +}; + +static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { + { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 }, + { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, + false, HDCP_2_2_CERT_TIMEOUT_MS, 0 }, + { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, + false, 0, 0 }, + { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, + false, 0, 0 }, + { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, + true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, + HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS }, + { HDCP_2_2_AKE_SEND_PAIRING_INFO, + DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, + HDCP_2_2_PAIRING_TIMEOUT_MS, 0 }, + { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 }, + { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, + false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 }, + { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, + 0, 0 }, + { HDCP_2_2_REP_SEND_RECVID_LIST, + DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, + HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 }, + { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, + 0, 0 }, + { HDCP_2_2_REP_STREAM_MANAGE, + DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, + 0, 0 }, + { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, + false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 }, +/* local define to shovel this through the write_2_2 interface */ +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 + { HDCP_2_2_ERRATA_DP_STREAM_TYPE, + DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, + 0, 0 }, +}; + +static int +intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, + u8 *rx_status) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + ssize_t ret; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, + HDCP_2_2_DP_RXSTATUS_LEN); + if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { + drm_dbg_kms(&i915->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); + return ret >= 0 ? -EIO : ret; + } + + return 0; +} + +static +int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, + u8 msg_id, bool *msg_ready) +{ + u8 rx_status; + int ret; + + *msg_ready = false; + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + if (ret < 0) + return ret; + + switch (msg_id) { + case HDCP_2_2_AKE_SEND_HPRIME: + if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) + *msg_ready = true; + break; + case HDCP_2_2_AKE_SEND_PAIRING_INFO: + if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) + *msg_ready = true; + break; + case HDCP_2_2_REP_SEND_RECVID_LIST: + if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) + *msg_ready = true; + break; + default: + DRM_ERROR("Unidentified msg_id: %d\n", msg_id); + return -EINVAL; + } + + return 0; +} + +static ssize_t +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, + const struct hdcp2_dp_msg_data *hdcp2_msg_data) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct intel_dp *dp = &intel_dig_port->dp; + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; + u8 msg_id = hdcp2_msg_data->msg_id; + int ret, timeout; + bool msg_ready = false; + + if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) + timeout = hdcp2_msg_data->timeout2; + else + timeout = hdcp2_msg_data->timeout; + + /* + * There is no way to detect the CERT, LPRIME and STREAM_READY + * availability. So Wait for timeout and read the msg. + */ + if (!hdcp2_msg_data->msg_detectable) { + mdelay(timeout); + ret = 0; + } else { + /* + * As we want to check the msg availability at timeout, Ignoring + * the timeout at wait for CP_IRQ. + */ + intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); + ret = hdcp2_detect_msg_availability(intel_dig_port, + msg_id, &msg_ready); + if (!msg_ready) + ret = -ETIMEDOUT; + } + + if (ret) + drm_dbg_kms(&i915->drm, + "msg_id %d, ret %d, timeout(mSec): %d\n", + hdcp2_msg_data->msg_id, ret, timeout); + + return ret; +} + +static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) + if (hdcp2_dp_msg_data[i].msg_id == msg_id) + return &hdcp2_dp_msg_data[i]; + + return NULL; +} + +static +int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, + void *buf, size_t size) +{ + struct intel_dp *dp = &intel_dig_port->dp; + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; + unsigned int offset; + u8 *byte = buf; + ssize_t ret, bytes_to_write, len; + const struct hdcp2_dp_msg_data *hdcp2_msg_data; + + hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); + if (!hdcp2_msg_data) + return -EINVAL; + + offset = hdcp2_msg_data->offset; + + /* No msg_id in DP HDCP2.2 msgs */ + bytes_to_write = size - 1; + byte++; + + hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); + + while (bytes_to_write) { + len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; + + ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, + offset, (void *)byte, len); + if (ret < 0) + return ret; + + bytes_to_write -= ret; + byte += ret; + offset += ret; + } + + return size; +} + +static +ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) +{ + u8 rx_info[HDCP_2_2_RXINFO_LEN]; + u32 dev_cnt; + ssize_t ret; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_HDCP_2_2_REG_RXINFO_OFFSET, + (void *)rx_info, HDCP_2_2_RXINFO_LEN); + if (ret != HDCP_2_2_RXINFO_LEN) + return ret >= 0 ? -EIO : ret; + + dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | + HDCP_2_2_DEV_COUNT_LO(rx_info[1])); + + if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) + dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; + + ret = sizeof(struct hdcp2_rep_send_receiverid_list) - + HDCP_2_2_RECEIVER_IDS_MAX_LEN + + (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); + + return ret; +} + +static +int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, + u8 msg_id, void *buf, size_t size) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + unsigned int offset; + u8 *byte = buf; + ssize_t ret, bytes_to_recv, len; + const struct hdcp2_dp_msg_data *hdcp2_msg_data; + + hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); + if (!hdcp2_msg_data) + return -EINVAL; + offset = hdcp2_msg_data->offset; + + ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); + if (ret < 0) + return ret; + + if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { + ret = get_receiver_id_list_size(intel_dig_port); + if (ret < 0) + return ret; + + size = ret; + } + bytes_to_recv = size - 1; + + /* DP adaptation msgs has no msg_id */ + byte++; + + while (bytes_to_recv) { + len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? + DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; + + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, + (void *)byte, len); + if (ret < 0) { + drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", + msg_id, ret); + return ret; + } + + bytes_to_recv -= ret; + byte += ret; + offset += ret; + } + byte = buf; + *byte = msg_id; + + return size; +} + +static +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, + bool is_repeater, u8 content_type) +{ + int ret; + struct hdcp2_dp_errata_stream_type stream_type_msg; + + if (is_repeater) + return 0; + + /* + * Errata for DP: As Stream type is used for encryption, Receiver + * should be communicated with stream type for the decryption of the + * content. + * Repeater will be communicated with stream type as a part of it's + * auth later in time. + */ + stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; + stream_type_msg.stream_type = content_type; + + ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, + sizeof(stream_type_msg)); + + return ret < 0 ? ret : 0; + +} + +static +int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) +{ + u8 rx_status; + int ret; + + ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + if (ret) + return ret; + + if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) + ret = HDCP_REAUTH_REQUEST; + else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) + ret = HDCP_LINK_INTEGRITY_FAILURE; + else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) + ret = HDCP_TOPOLOGY_CHANGE; + + return ret; +} + +static +int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, + bool *capable) +{ + u8 rx_caps[3]; + int ret; + + *capable = false; + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + DP_HDCP_2_2_REG_RX_CAPS_OFFSET, + rx_caps, HDCP_2_2_RXCAPS_LEN); + if (ret != HDCP_2_2_RXCAPS_LEN) + return ret >= 0 ? -EIO : ret; + + if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && + HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) + *capable = true; + + return 0; +} + +static const struct intel_hdcp_shim intel_dp_hdcp_shim = { + .write_an_aksv = intel_dp_hdcp_write_an_aksv, + .read_bksv = intel_dp_hdcp_read_bksv, + .read_bstatus = intel_dp_hdcp_read_bstatus, + .repeater_present = intel_dp_hdcp_repeater_present, + .read_ri_prime = intel_dp_hdcp_read_ri_prime, + .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, + .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, + .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, + .toggle_signalling = intel_dp_hdcp_toggle_signalling, + .check_link = intel_dp_hdcp_check_link, + .hdcp_capable = intel_dp_hdcp_capable, + .write_2_2_msg = intel_dp_hdcp2_write_msg, + .read_2_2_msg = intel_dp_hdcp2_read_msg, + .config_stream_type = intel_dp_hdcp2_config_stream_type, + .check_2_2_link = intel_dp_hdcp2_check_link, + .hdcp_2_2_capable = intel_dp_hdcp2_capable, + .protocol = HDCP_PROTOCOL_DP, +}; + +int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port, + struct intel_connector *intel_connector) +{ + struct drm_device *dev = intel_connector->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_encoder *intel_encoder = &intel_dig_port->base; + enum port port = intel_encoder->port; + struct intel_dp *intel_dp = &intel_dig_port->dp; + + if (!is_hdcp_supported(dev_priv, port)) + return 0; + + if (!intel_dp_is_edp(intel_dp)) + return intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); + + return 0; +} -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:03 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:03 -0400 Subject: [Intel-gfx] [PATCH v7 13/17] drm/i915: Plumb port through hdcp init In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-14-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> This patch plumbs port through hdcp init instead of relying on intel_attached_encoder() to return a non-NULL encoder which won't work for MST connectors. Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-13-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-13-sean at poorly.run #v6 Changes in v5: -Added to the set Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 0e06a1066d61..e26a45f880cb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -630,7 +630,8 @@ int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port, return 0; if (!intel_dp_is_edp(intel_dp)) - return intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); + return intel_hdcp_init(intel_connector, port, + &intel_dp_hdcp_shim); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 5679877c6b4c..d79d4142aea7 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -1955,6 +1955,7 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder) } static int initialize_hdcp_port_data(struct intel_connector *connector, + enum port port, const struct intel_hdcp_shim *shim) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); @@ -1962,8 +1963,7 @@ static int initialize_hdcp_port_data(struct intel_connector *connector, struct hdcp_port_data *data = &hdcp->port_data; if (INTEL_GEN(dev_priv) < 12) - data->fw_ddi = - intel_get_mei_fw_ddi_index(intel_attached_encoder(connector)->port); + data->fw_ddi = intel_get_mei_fw_ddi_index(port); else /* * As per ME FW API expectation, for GEN 12+, fw_ddi is filled @@ -2033,14 +2033,14 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv) } } -static void intel_hdcp2_init(struct intel_connector *connector, +static void intel_hdcp2_init(struct intel_connector *connector, enum port port, const struct intel_hdcp_shim *shim) { struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; int ret; - ret = initialize_hdcp_port_data(connector, shim); + ret = initialize_hdcp_port_data(connector, port, shim); if (ret) { drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n"); return; @@ -2050,6 +2050,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, } int intel_hdcp_init(struct intel_connector *connector, + enum port port, const struct intel_hdcp_shim *shim) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); @@ -2060,7 +2061,7 @@ int intel_hdcp_init(struct intel_connector *connector, return -EINVAL; if (is_hdcp2_supported(dev_priv)) - intel_hdcp2_init(connector, shim); + intel_hdcp2_init(connector, port, shim); ret = drm_connector_attach_content_protection_property(&connector->base, diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h index 86bbaec120cc..1bbf5b67ed0a 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h @@ -22,7 +22,7 @@ enum transcoder; void intel_hdcp_atomic_check(struct drm_connector *connector, struct drm_connector_state *old_state, struct drm_connector_state *new_state); -int intel_hdcp_init(struct intel_connector *connector, +int intel_hdcp_init(struct intel_connector *connector, enum port port, const struct intel_hdcp_shim *hdcp_shim); int intel_hdcp_enable(struct intel_connector *connector, enum transcoder cpu_transcoder, u8 content_type); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a59acfff456e..ca71ee3dd1c7 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3260,7 +3260,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, intel_hdmi->attached_connector = intel_connector; if (is_hdcp_supported(dev_priv, port)) { - int ret = intel_hdcp_init(intel_connector, + int ret = intel_hdcp_init(intel_connector, port, &intel_hdmi_hdcp_shim); if (ret) drm_dbg_kms(&dev_priv->drm, -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:04 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:04 -0400 Subject: [Intel-gfx] [PATCH v7 14/17] drm/i915: Add connector to hdcp_shim->check_link() In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-15-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Currently we derive the connector from digital port in check_link(). For MST, this isn't sufficient since the digital port passed into the function can have multiple connectors downstream. This patch adds connector to the check_link() arguments so we have it when we need it. Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-13-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-14-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-14-sean at poorly.run #v6 Changes in v4: -Added to the set Changes in v5: -None Changes in v6: -None Changes in v7: -None --- drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 5 ++--- 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 811085ef3fba..94211b8fc159 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -318,7 +318,8 @@ struct intel_hdcp_shim { bool enable); /* Ensures the link is still protected */ - bool (*check_link)(struct intel_digital_port *intel_dig_port); + bool (*check_link)(struct intel_digital_port *intel_dig_port, + struct intel_connector *connector); /* Detects panel's hdcp capability. This is optional for HDMI. */ int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index e26a45f880cb..43446a6cae8d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -223,7 +223,8 @@ int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, } static -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port, + struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); ssize_t ret; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index d79d4142aea7..6bd0e4616ee1 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -953,7 +953,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; } - if (hdcp->shim->check_link(intel_dig_port)) { + if (hdcp->shim->check_link(intel_dig_port, connector)) { if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { intel_hdcp_update_value(connector, DRM_MODE_CONTENT_PROTECTION_ENABLED, true); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ca71ee3dd1c7..b12f1af0611d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1546,11 +1546,10 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, } static -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port, + struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_connector *connector = - intel_dig_port->hdmi.attached_connector; enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; int ret; -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:05 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:05 -0400 Subject: [Intel-gfx] [PATCH v7 15/17] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-16-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Used to query whether an MST stream is encrypted or not. Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-sean at poorly.run #v6 Changes in v4: -Added to the set Changes in v5: -None Changes in v6: -Use FIELD_PREP to generate request buffer bitfields (Lyude) -Add mst selftest and dump/decode_sideband_req for QSES (Lyude) Changes in v7: -None --- drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++++++++++++++++ .../drm/selftests/test-drm_dp_mst_helper.c | 17 +++ include/drm/drm_dp_helper.h | 3 + include/drm/drm_dp_mst_helper.h | 44 ++++++ 4 files changed, 206 insertions(+) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index b2f5a84b4cfb..fc68478eaeb4 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -20,11 +20,13 @@ * OF THIS SOFTWARE. */ +#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/random.h> #include <linux/sched.h> #include <linux/seq_file.h> #include <linux/iopoll.h> @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes); idx += req->u.i2c_write.num_bytes; break; + case DP_QUERY_STREAM_ENC_STATUS: { + const struct drm_dp_query_stream_enc_status *msg; + + msg = &req->u.enc_status; + buf[idx] = msg->stream_id; + idx++; + memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id)); + idx += sizeof(msg->client_id); + buf[idx] = 0; + buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event); + buf[idx] |= msg->valid_stream_event ? BIT(2) : 0; + buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior); + buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0; + idx++; + } + break; } raw->cur_len = idx; } @@ -547,6 +565,20 @@ drm_dp_decode_sideband_req(const struct drm_dp_sideband_msg_tx *raw, return -ENOMEM; } break; + case DP_QUERY_STREAM_ENC_STATUS: + req->u.enc_status.stream_id = buf[idx++]; + for (i = 0; i < sizeof(req->u.enc_status.client_id); i++) + req->u.enc_status.client_id[i] = buf[idx++]; + + req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0), + buf[idx]); + req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2), + buf[idx]); + req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3), + buf[idx]); + req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5), + buf[idx]); + break; } return 0; @@ -625,6 +657,16 @@ drm_dp_dump_sideband_msg_req_body(const struct drm_dp_sideband_msg_req_body *req req->u.i2c_write.num_bytes, req->u.i2c_write.num_bytes, req->u.i2c_write.bytes); break; + case DP_QUERY_STREAM_ENC_STATUS: + P("stream_id=%u client_id=%*ph stream_event=%x " + "valid_event=%d stream_behavior=%x valid_behavior=%d", + req->u.enc_status.stream_id, + (int)ARRAY_SIZE(req->u.enc_status.client_id), + req->u.enc_status.client_id, req->u.enc_status.stream_event, + req->u.enc_status.valid_stream_event, + req->u.enc_status.stream_behavior, + req->u.enc_status.valid_stream_behavior); + break; default: P("???\n"); break; @@ -925,6 +967,34 @@ static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms return true; } +static bool +drm_dp_sideband_parse_query_stream_enc_status( + struct drm_dp_sideband_msg_rx *raw, + struct drm_dp_sideband_msg_reply_body *repmsg) +{ + struct drm_dp_query_stream_enc_status_ack_reply *reply; + + reply = &repmsg->u.enc_status; + + reply->stream_id = raw->msg[3]; + + reply->reply_signed = raw->msg[2] & BIT(0); + + reply->hdcp_1x_device_present = raw->msg[2] & BIT(3); + reply->hdcp_2x_device_present = raw->msg[2] & BIT(4); + + reply->query_capable_device_present = raw->msg[2] & BIT(5); + reply->legacy_device_present = raw->msg[2] & BIT(6); + reply->unauthorizable_device_present = raw->msg[2] & BIT(7); + + reply->auth_completed = !!(raw->msg[1] & BIT(3)); + reply->encryption_enabled = !!(raw->msg[1] & BIT(4)); + reply->repeater_present = !!(raw->msg[1] & BIT(5)); + reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6; + + return true; +} + static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, struct drm_dp_sideband_msg_reply_body *msg) { @@ -959,6 +1029,8 @@ static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg); case DP_CLEAR_PAYLOAD_ID_TABLE: return true; /* since there's nothing to parse */ + case DP_QUERY_STREAM_ENC_STATUS: + return drm_dp_sideband_parse_query_stream_enc_status(raw, msg); default: DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type, drm_dp_mst_req_type_str(msg->req_type)); @@ -1109,6 +1181,25 @@ static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, msg->path_msg = true; } +static int +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id, + u8 *q_id) +{ + struct drm_dp_sideband_msg_req_body req; + + req.req_type = DP_QUERY_STREAM_ENC_STATUS; + req.u.enc_status.stream_id = stream_id; + memcpy(req.u.enc_status.client_id, q_id, + sizeof(req.u.enc_status.client_id)); + req.u.enc_status.stream_event = 0; + req.u.enc_status.valid_stream_event = false; + req.u.enc_status.stream_behavior = 0; + req.u.enc_status.valid_stream_behavior = false; + + drm_dp_encode_sideband_req(&req, msg); + return 0; +} + static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_vcpi *vcpi) { @@ -3137,6 +3228,57 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, } EXPORT_SYMBOL(drm_dp_send_power_updown_phy); +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, + struct drm_dp_query_stream_enc_status_ack_reply *status) +{ + struct drm_dp_sideband_msg_tx *txmsg; + u8 nonce[7]; + int len, ret; + + txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); + if (!txmsg) + return -ENOMEM; + + port = drm_dp_mst_topology_get_port_validated(mgr, port); + if (!port) { + ret = -EINVAL; + goto out_get_port; + } + + get_random_bytes(nonce, sizeof(nonce)); + + /* + * "Source device targets the QUERY_STREAM_ENCRYPTION_STATUS message + * transaction at the MST Branch device directly connected to the + * Source" + */ + txmsg->dst = mgr->mst_primary; + + len = build_query_stream_enc_status(txmsg, port->vcpi.vcpi, nonce); + + drm_dp_queue_down_tx(mgr, txmsg); + + ret = drm_dp_mst_wait_tx_reply(mgr->mst_primary, txmsg); + if (ret < 0) { + goto out; + } else if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) { + DRM_DEBUG_KMS("query encryption status nak received\n"); + ret = -ENXIO; + goto out; + } + + ret = 0; + memcpy(status, &txmsg->reply.u.enc_status, sizeof(*status)); + +out: + drm_dp_mst_topology_put_port(port); +out_get_port: + kfree(txmsg); + return ret; +} +EXPORT_SYMBOL(drm_dp_send_query_stream_enc_status); + static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload) diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c index bd990d178765..1d696ec001cf 100644 --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c @@ -5,6 +5,8 @@ #define PREFIX_STR "[drm_dp_mst_helper]" +#include <linux/random.h> + #include <drm/drm_dp_mst_helper.h> #include <drm/drm_print.h> @@ -237,6 +239,21 @@ int igt_dp_mst_sideband_msg_req_decode(void *unused) in.u.i2c_write.bytes = data; DO_TEST(); + in.req_type = DP_QUERY_STREAM_ENC_STATUS; + in.u.enc_status.stream_id = 1; + DO_TEST(); + get_random_bytes(in.u.enc_status.client_id, + sizeof(in.u.enc_status.client_id)); + DO_TEST(); + in.u.enc_status.stream_event = 3; + DO_TEST(); + in.u.enc_status.valid_stream_event = 0; + DO_TEST(); + in.u.enc_status.stream_behavior = 3; + DO_TEST(); + in.u.enc_status.valid_stream_behavior = 1; + DO_TEST(); + #undef DO_TEST return 0; } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..e2d2df5e869e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1108,6 +1108,9 @@ #define DP_POWER_DOWN_PHY 0x25 #define DP_SINK_EVENT_NOTIFY 0x30 #define DP_QUERY_STREAM_ENC_STATUS 0x38 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2 /* DP 1.2 MST sideband reply types */ #define DP_SIDEBAND_REPLY_ACK 0x00 diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 8b9eb4db3381..371eef8798ad 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -313,6 +313,34 @@ struct drm_dp_remote_i2c_write_ack_reply { u8 port_number; }; +struct drm_dp_query_stream_enc_status_ack_reply { + /* Bit[23:16]- Stream Id */ + u8 stream_id; + + /* Bit[15]- Signed */ + bool reply_signed; + + /* Bit[10:8]- Stream Output Sink Type */ + bool unauthorizable_device_present; + bool legacy_device_present; + bool query_capable_device_present; + + /* Bit[12:11]- Stream Output CP Type */ + bool hdcp_1x_device_present; + bool hdcp_2x_device_present; + + /* Bit[4]- Stream Authentication */ + bool auth_completed; + + /* Bit[3]- Stream Encryption */ + bool encryption_enabled; + + /* Bit[2]- Stream Repeater Function Present */ + bool repeater_present; + + /* Bit[1:0]- Stream State */ + u8 state; +}; #define DRM_DP_MAX_SDP_STREAMS 16 struct drm_dp_allocate_payload { @@ -374,6 +402,15 @@ struct drm_dp_remote_i2c_write { u8 *bytes; }; +struct drm_dp_query_stream_enc_status { + u8 stream_id; + u8 client_id[7]; /* 56-bit nonce */ + u8 stream_event; + bool valid_stream_event; + u8 stream_behavior; + u8 valid_stream_behavior; +}; + /* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ struct drm_dp_port_number_req { u8 port_number; @@ -422,6 +459,8 @@ struct drm_dp_sideband_msg_req_body { struct drm_dp_remote_i2c_read i2c_read; struct drm_dp_remote_i2c_write i2c_write; + + struct drm_dp_query_stream_enc_status enc_status; } u; }; @@ -444,6 +483,8 @@ struct drm_dp_sideband_msg_reply_body { struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack; + + struct drm_dp_query_stream_enc_status_ack_reply enc_status; } u; }; @@ -808,6 +849,9 @@ drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, struct drm_dp_mst_port *port); int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, bool power_up); +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, + struct drm_dp_query_stream_enc_status_ack_reply *status); int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state); void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port); -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:06 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:06 -0400 Subject: [Intel-gfx] [PATCH v7 16/17] drm/i915: Print HDCP version info for all connectors In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-17-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> De-duplicate the HDCP version code for each connector and print it for all connectors. Cc: Juston Li <juston.li at intel.com> Cc: Ramalingam C <ramalingam.c at intel.com> Reviewed-by: Juston Li <juston.li at intel.com> Reviewed-by: Ramalingam C <ramalingam.c at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200227185714.171466-1-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-16-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-16-sean at poorly.run #v6 Changes in v4: - Added to the set Changes in v5: -Print "No connector support" for hdcp sink capability as well (Ram) Changes in v6: -None Changes in v7: -None --- .../drm/i915/display/intel_display_debugfs.c | 21 ++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d1cb48b3f462..1f748a480eb2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -598,6 +598,11 @@ static void intel_hdcp_info(struct seq_file *m, { bool hdcp_cap, hdcp2_cap; + if (!intel_connector->hdcp.shim) { + seq_puts(m, "No Connector Support"); + goto out; + } + hdcp_cap = intel_hdcp_capable(intel_connector); hdcp2_cap = intel_hdcp2_capable(intel_connector); @@ -609,6 +614,7 @@ static void intel_hdcp_info(struct seq_file *m, if (!hdcp_cap && !hdcp2_cap) seq_puts(m, "None"); +out: seq_puts(m, "\n"); } @@ -625,10 +631,6 @@ static void intel_dp_info(struct seq_file *m, drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, &intel_dp->aux); - if (intel_connector->hdcp.shim) { - seq_puts(m, "\tHDCP version: "); - intel_hdcp_info(m, intel_connector); - } } static void intel_dp_mst_info(struct seq_file *m, @@ -646,10 +648,6 @@ static void intel_hdmi_info(struct seq_file *m, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder); seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); - if (intel_connector->hdcp.shim) { - seq_puts(m, "\tHDCP version: "); - intel_hdcp_info(m, intel_connector); - } } static void intel_lvds_info(struct seq_file *m, @@ -705,6 +703,9 @@ static void intel_connector_info(struct seq_file *m, break; } + seq_puts(m, "\tHDCP version: "); + intel_hdcp_info(m, intel_connector); + seq_printf(m, "\tmodes:\n"); list_for_each_entry(mode, &connector->modes, head) intel_seq_print_mode(m, 2, mode); @@ -2026,10 +2027,6 @@ static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data) if (connector->status != connector_status_connected) return -ENODEV; - /* HDCP is supported by connector */ - if (!intel_connector->hdcp.shim) - return -EINVAL; - seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); intel_hdcp_info(m, intel_connector); -- Sean Paul, Software Engineer, Google / Chromium OS From sean at poorly.run Tue Jun 23 15:59:07 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 23 Jun 2020 11:59:07 -0400 Subject: [Intel-gfx] [PATCH v7 17/17] drm/i915: Add HDCP 1.4 support for MST connectors In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <20200623155907.22961-18-sean@poorly.run> From: Sean Paul <seanpaul at chromium.org> Now that all the groundwork has been laid, we can turn on HDCP 1.4 over MST. Everything except for toggling the HDCP signalling and HDCP 2.2 support is the same as the DP case, so we'll re-use those callbacks Cc: Juston Li <juston.li at intel.com> Signed-off-by: Sean Paul <seanpaul at chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-12-sean at poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-13-sean at poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-13-sean at poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-15-sean at poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-17-sean at poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-17-sean at poorly.run #v6 Changes in v2: -Toggle HDCP from encoder disable/enable -Don't disable HDCP on MST connector destroy, leave that for encoder disable, just ensure the check_work routine isn't running any longer Changes in v3: -Place the shim in the new intel_dp_hdcp.c file (Ville) Changes in v4: -Actually use the mst shim for mst connections (Juston) -Use QUERY_STREAM_ENC_STATUS MST message to verify channel is encrypted Changes in v5: -Add sleep on disable signalling to match hdmi delay Changes in v6: -Disable HDCP over MST on GEN12+ since I'm unsure how it should work and I don't have hardware to test it Changes in v7: -Remove hdcp2 shims for MST in favor of skipping hdcp2 init (Ramalingam) --- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 66 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++++ drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- 3 files changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 43446a6cae8d..3f67bd27fc3c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -7,10 +7,12 @@ */ #include <drm/drm_dp_helper.h> +#include <drm/drm_dp_mst_helper.h> #include <drm/drm_hdcp.h> #include <drm/drm_print.h> #include "intel_display_types.h" +#include "intel_ddi.h" #include "intel_dp.h" #include "intel_hdcp.h" @@ -618,6 +620,65 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = { .protocol = HDCP_PROTOCOL_DP, }; +static int +intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, + enum transcoder cpu_transcoder, + bool enable) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + int ret; + + if (!enable) + usleep_range(6, 60); /* Bspec says >= 6us */ + + ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, + cpu_transcoder, enable); + if (ret) + drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n", + enable ? "Enable" : "Disable", ret); + return ret; +} + +static +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *intel_dig_port, + struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct intel_dp *intel_dp = &intel_dig_port->dp; + struct drm_dp_query_stream_enc_status_ack_reply reply; + int ret; + + if (!intel_dp_hdcp_check_link(intel_dig_port, connector)) + return false; + + ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr, + connector->port, &reply); + if (ret) { + drm_dbg_kms(&i915->drm, + "[CONNECTOR:%d:%s] failed QSES ret=%d\n", + connector->base.base.id, connector->base.name, ret); + return false; + } + + return reply.auth_completed && reply.encryption_enabled; +} + +static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { + .write_an_aksv = intel_dp_hdcp_write_an_aksv, + .read_bksv = intel_dp_hdcp_read_bksv, + .read_bstatus = intel_dp_hdcp_read_bstatus, + .repeater_present = intel_dp_hdcp_repeater_present, + .read_ri_prime = intel_dp_hdcp_read_ri_prime, + .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, + .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, + .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, + .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling, + .check_link = intel_dp_mst_hdcp_check_link, + .hdcp_capable = intel_dp_hdcp_capable, + + .protocol = HDCP_PROTOCOL_DP, +}; + int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector) { @@ -630,7 +691,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port, if (!is_hdcp_supported(dev_priv, port)) return 0; - if (!intel_dp_is_edp(intel_dp)) + if (intel_connector->mst_port) + return intel_hdcp_init(intel_connector, port, + &intel_dp_mst_hdcp_shim); + else if (!intel_dp_is_edp(intel_dp)) return intel_hdcp_init(intel_connector, port, &intel_dp_hdcp_shim); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0675825dcc20..abaaeeb963d2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -37,6 +37,7 @@ #include "intel_dp.h" #include "intel_dp_mst.h" #include "intel_dpio_phy.h" +#include "intel_hdcp.h" static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, @@ -352,6 +353,8 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, drm_dbg_kms(&i915->drm, "active links %d\n", intel_dp->active_mst_links); + intel_hdcp_disable(intel_mst->connector); + drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port); ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); @@ -548,6 +551,13 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, if (pipe_config->has_audio) intel_audio_codec_enable(encoder, pipe_config, conn_state); + + /* Enable hdcp if it's desired */ + if (conn_state->content_protection == + DRM_MODE_CONTENT_PROTECTION_DESIRED) + intel_hdcp_enable(to_intel_connector(conn_state->connector), + pipe_config->cpu_transcoder, + (u8)conn_state->hdcp_content_type); } static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, @@ -770,6 +780,14 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo intel_attach_force_audio_property(connector); intel_attach_broadcast_rgb_property(connector); + + /* TODO: Figure out how to make HDCP work on GEN12+ */ + if (INTEL_GEN(dev_priv) < 12) { + ret = intel_dp_init_hdcp(intel_dig_port, intel_connector); + if (ret) + DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); + } + /* * Reuse the prop from the SST connector because we're * not allowed to create new props after device registration. diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 6bd0e4616ee1..ddc9db8de2bc 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2060,7 +2060,7 @@ int intel_hdcp_init(struct intel_connector *connector, if (!shim) return -EINVAL; - if (is_hdcp2_supported(dev_priv)) + if (is_hdcp2_supported(dev_priv) && !connector->mst_port) intel_hdcp2_init(connector, port, shim); ret = -- Sean Paul, Software Engineer, Google / Chromium OS From chris at chris-wilson.co.uk Tue Jun 23 16:00:31 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 17:00:31 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <3ea271d6-3101-62e0-8fb6-d433ba78ff17@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> <159292086189.10607.10450244252436195167@build.alporthouse.com> <3ea271d6-3101-62e0-8fb6-d433ba78ff17@shipmail.org> Message-ID: <159292803144.3967.1535107544852190069@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 16:09:08) > > On 6/23/20 4:01 PM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 13:57:06) > >> On 6/23/20 1:22 PM, Thomas Hellstr?m (Intel) wrote: > >>> Hi, Chris, > >>> > >>> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>>> In order to actually handle eviction and what not, we need to process > >>>> all the objects together under a common lock, reservation_ww_class. As > >>>> such, do a memory reservation pass after looking up the object/vma, > >>>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>>> flushing and ofc execution]. > >>>> > >>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>>> --- > >>>> ? .../gpu/drm/i915/gem/i915_gem_execbuffer.c??? | 91 ++++++++++++++----- > >>>> ? 1 file changed, 70 insertions(+), 21 deletions(-) > >>>> > >>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>> index 46fcbdf8161c..8db2e013465f 100644 > >>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>> @@ -53,10 +53,9 @@ struct eb_vma_array { > >>>> ? ? #define __EXEC_OBJECT_HAS_PIN??????? BIT(31) > >>>> ? #define __EXEC_OBJECT_HAS_FENCE??????? BIT(30) > >>>> -#define __EXEC_OBJECT_HAS_PAGES??????? BIT(29) > >>>> -#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(28) > >>>> -#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(27) > >>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 27) /* all of the > >>>> above */ > >>>> +#define __EXEC_OBJECT_NEEDS_MAP??????? BIT(29) > >>>> +#define __EXEC_OBJECT_NEEDS_BIAS??? BIT(28) > >>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS??? (~0u << 28) /* all of the > >>>> above */ > >>>> ? ? #define __EXEC_HAS_RELOC??? BIT(31) > >>>> ? #define __EXEC_INTERNAL_FLAGS??? (~0u << 31) > >>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { > >>>> ????? struct intel_context *context; /* logical state for the request */ > >>>> ????? struct i915_gem_context *gem_context; /** caller's context */ > >>>> ? +??? struct dma_fence *mm_fence; > >>>> + > >>>> ????? struct i915_request *request; /** our request to build */ > >>>> ????? struct eb_vma *batch; /** identity of the batch obj/vma */ > >>>> ????? struct i915_vma *trampoline; /** trampoline used for chaining */ > >>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct > >>>> eb_vma *ev) > >>>> ????? if (ev->flags & __EXEC_OBJECT_HAS_PIN) > >>>> ????????? __i915_vma_unpin(vma); > >>>> ? -??? if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > >>>> -??????? i915_gem_object_unpin_pages(vma->obj); > >>>> - > >>>> -??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > >>>> -?????????????? __EXEC_OBJECT_HAS_FENCE | > >>>> -?????????????? __EXEC_OBJECT_HAS_PAGES); > >>>> +??? ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > >>>> ? } > >>>> ? ? static void eb_vma_array_destroy(struct kref *kref) > >>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > >>>> ????? list_add_tail(&ev->lock_link, &eb->lock); > >>>> ? } > >>>> ? +static int eb_vma_get_pages(struct i915_execbuffer *eb, > >>>> +??????????????? struct eb_vma *ev, > >>>> +??????????????? u64 idx) > >>>> +{ > >>>> +??? struct i915_vma *vma = ev->vma; > >>>> +??? int err; > >>>> + > >>>> +??? /* XXX also preallocate PD for vma */ > >>>> + > >>>> +??? err = ____i915_gem_object_get_pages_async(vma->obj); > >>>> +??? if (err) > >>>> +??????? return err; > >>>> + > >>>> +??? return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > >>>> +} > >>>> + > >>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>>> +{ > >>>> +??? const u64 idx = eb->context->timeline->fence_context; > >>>> +??? struct ww_acquire_ctx acquire; > >>>> +??? struct eb_vma *ev; > >>>> +??? int err; > >>>> + > >>>> +??? eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>>> +??? if (!eb->mm_fence) > >>>> +??????? return -ENOMEM; > >>> Question: eb is local to this thread, right, so eb->mm_fence is not > >>> considered "published" yet? > >>> > >>>> + > >>>> +??? ww_acquire_init(&acquire, &reservation_ww_class); > >>>> + > >>>> +??? err = eb_lock_vma(eb, &acquire); > >>>> +??? if (err) > >>>> +??????? goto out; > >>>> + > >>>> +??? ww_acquire_done(&acquire); > >>>> + > >>>> +??? list_for_each_entry(ev, &eb->lock, lock_link) { > >>>> +??????? struct i915_vma *vma = ev->vma; > >>>> + > >>>> +??????? if (err == 0) > >>>> +??????????? err = eb_vma_get_pages(eb, ev, idx); > >>> I figure this is where you publish the proxy fence? If so, the fence > >>> signaling critical path starts with this loop, and that means any code > >>> we call between here and submission complete (including spawned work > >>> we need to wait for before submission) may not lock the > >>> reservation_ww_class nor (still being discussed) allocate memory. > > Yes, at this point we have reserved the memory for the execbuf. > > > >>> It > >>> looks like i915_pin_vma takes a reservation_ww_class. And all memory > >>> pinning seems to be in the fence critical path as well? > > Correct, it's not meant to be waiting inside i915_vma_pin(); the > > intention was to pass in memory, and then we would not need to > > do the acquire ourselves. As we have just reserved the memory in the > > above loop, this should not be an issue. I was trying to keep the > > change minimal and allow incremental conversions. It does however need > > to add a reference to the object for the work it spawns -- equally > > though there is an async eviction pass later in execbuf. The challenge > > here is that the greedy grab of bound vma is faster than doing the > > unbound eviction handling (even when eviction is not required). > > So for the i915_vma_pin, it looks like > > fence_critical_start(eb_reserve_mm) -> > dma_resv_lock_interruptible(i915_vma_pin) -> lockdep issue. > > You can't take the dma_resv_lock inside a fence critical section. Aye, and that is trivially liftable since the allocation is provided by the caller. But we still want one off access, hence the preference for keeping the convenience of i915_vma_pin until all callers have transitioned. > And for the memory allocation, it looks like the fence is published in > the first loop iteration, starting the critical section, meaning that > any memory allocation that follows will cause a lockdep issue. That > includes worker threads. (with the proposed dma_fence annotations). I fail to be convinced that proposal is a good solution. > >> And I think even if we at some point end up with the allocation > >> annotation the other way around, allowing memory allocations in fence > >> signalling critical paths, both relocations and userpointer would cause > >> lockdep problems because of > >> > >> mmap_sem->reservation_object->fence_wait (fault handlers, lockdep priming) > > We don't wait inside mmap_sem. One cannot, you do not know the locking > > context, so you can only try to reclaim idle space. So you end up with > > the issue of a multitude of threads each trying to claim the last slice > > of the aperture/backing storage, not being able to directly reclaim and > > so have to hit the equivalent of kswapd. > > I don't think I follow you here. There are a number of drivers that wait > for dma_fences inside the fault handlers with mmap_sem held for data to > be migrated before the pte is set up. I mean that userspace is at liberty to prevent the migration arbitrarily, forming a resource lock. Waiting for userspace while holding any mutex is an easy deadlock. Hence why any such wait for eviction of another must be interruptible (either by signal, timeout), ensure force completion or never actually wait. A wait for itself should at least be killable. > >> vs > >> fence_critical->gup/copy_from_user->mmap_sem > > Which exists today, even the busy wait loop is implicit linkage; you only > > need userspace to be holding a resource on the gpu to create the deadlock. > > I've been using the userfault handler to develop test cases where we can > > arbitrarily block the userptr. > > Yes but in a case where we don't publish the fence early, the above > would be reduced to the well known reservation_ww_class vs mmap_sem > lockdep issue, which other drivers seem to have solved and we could copy > what they've done. I don't see the difference. We have gup, malloc, copy_user inside a fence as it stands. What I would want to address, with say, ttm_bo_vm_reserve is that faulting should only care about the migration chain, and we should be careful when selecting eviction candidates (if only because we need to respect memory prioritisation). -Chris From chunkuang.hu at kernel.org Tue Jun 23 16:01:58 2020 From: chunkuang.hu at kernel.org (Chun-Kuang Hu) Date: Wed, 24 Jun 2020 00:01:58 +0800 Subject: [Intel-gfx] [PATCH 4/8] drm/mtk: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-4-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-4-daniel.vetter@ffwll.ch> Message-ID: <CAAOTY__Vvu8C97j3-zfUFeY4OgWZvUzqOm+=A2AQyJcRUWWidQ@mail.gmail.com> Hi, Daniel: Daniel Vetter <daniel.vetter at ffwll.ch> ? 2020?6?13? ?? ??12:01??? > > Now also comes with the added benefit of doing a drm_crtc_vblank_off(), > which means vblank state isn't ill-defined and fail-y at driver load > before the first modeset on each crtc. > Acked-by: Chun-Kuang Hu <chunkuang.hu at kernel.org> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Chun-Kuang Hu <chunkuang.hu at kernel.org> > Cc: Philipp Zabel <p.zabel at pengutronix.de> > Cc: Matthias Brugger <matthias.bgg at gmail.com> > Cc: linux-arm-kernel at lists.infradead.org > Cc: linux-mediatek at lists.infradead.org > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 16 ++++++---------- > 1 file changed, 6 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index a7dba4ced902..d654c7d514bd 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -112,19 +112,15 @@ static void mtk_drm_crtc_reset(struct drm_crtc *crtc) > { > struct mtk_crtc_state *state; > > - if (crtc->state) { > + if (crtc->state) > __drm_atomic_helper_crtc_destroy_state(crtc->state); > > - state = to_mtk_crtc_state(crtc->state); > - memset(state, 0, sizeof(*state)); > - } else { > - state = kzalloc(sizeof(*state), GFP_KERNEL); > - if (!state) > - return; > - crtc->state = &state->base; > - } > + kfree(to_mtk_crtc_state(crtc->state)); > + crtc->state = NULL; > > - state->base.crtc = crtc; > + state = kzalloc(sizeof(*state), GFP_KERNEL); > + if (state) > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > } > > static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) > -- > 2.26.2 > From patchwork at emeril.freedesktop.org Tue Jun 23 16:11:50 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 16:11:50 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/fb-helper=3A_Fix_vt_restore?= In-Reply-To: <20200623155456.3092836-1-daniel.vetter@ffwll.ch> References: <20200623155456.3092836-1-daniel.vetter@ffwll.ch> Message-ID: <159292871071.4209.6929757259293164916@emeril.freedesktop.org> == Series Details == Series: drm/fb-helper: Fix vt restore URL : https://patchwork.freedesktop.org/series/78746/ State : warning == Summary == $ dim checkpatch origin/drm-tip 71234d269281 drm/fb-helper: Fix vt restore -:33: WARNING:TYPO_SPELLING: 'wheter' may be misspelled - perhaps 'whether'? #33: While pondering all this I'm also wondering wheter we should have a -:39: WARNING:BAD_SIGN_OFF: 'Reported-and-tested-by:' is the preferred signature form #39: Reported-and-Tested-by: shlomo at fastmail.com -:180: WARNING:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Daniel Vetter <daniel.vetter at ffwll.ch>' total: 0 errors, 3 warnings, 0 checks, 109 lines checked From chris at chris-wilson.co.uk Tue Jun 23 16:17:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 17:17:38 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <3ea271d6-3101-62e0-8fb6-d433ba78ff17@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> <159292086189.10607.10450244252436195167@build.alporthouse.com> <3ea271d6-3101-62e0-8fb6-d433ba78ff17@shipmail.org> Message-ID: <159292905802.3967.14570193627723429860@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 16:09:08) > You can't take the dma_resv_lock inside a fence critical section. I much prefer the alternative interpretation, you can't wait inside a dma_resv_lock. -Chris From thomas_os at shipmail.org Tue Jun 23 16:29:46 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 18:29:46 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159292905802.3967.14570193627723429860@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> <159292086189.10607.10450244252436195167@build.alporthouse.com> <3ea271d6-3101-62e0-8fb6-d433ba78ff17@shipmail.org> <159292905802.3967.14570193627723429860@build.alporthouse.com> Message-ID: <84641356-2c26-6208-e165-3cb6a143ca2c@shipmail.org> On 6/23/20 6:17 PM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-23 16:09:08) >> You can't take the dma_resv_lock inside a fence critical section. > I much prefer the alternative interpretation, you can't wait inside a > dma_resv_lock. > -Chris I respect your point of view, athough I need to think we need to focus on what we have to do in the i915 driver. /Thomas From patchwork at emeril.freedesktop.org Tue Jun 23 16:33:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 16:33:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/fb-helper=3A_Fix_vt_restore?= In-Reply-To: <20200623155456.3092836-1-daniel.vetter@ffwll.ch> References: <20200623155456.3092836-1-daniel.vetter@ffwll.ch> Message-ID: <159293000128.4210.9260243391793088136@emeril.freedesktop.org> == Series Details == Series: drm/fb-helper: Fix vt restore URL : https://patchwork.freedesktop.org/series/78746/ State : success == Summary == CI Bug Log - changes from CI_DRM_8658 -> Patchwork_18012 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/index.html Known issues ------------ Here are the changes found in Patchwork_18012 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2] ([i915#1250] / [i915#1436]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-bsw-nick/igt at debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-bsw-nick/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][3] -> [FAIL][4] ([i915#1888]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-byt-j1900/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-byt-j1900/igt at i915_module_load@reload.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-bsw-kefka/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-bsw-kefka/igt at i915_module_load@reload.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8658 -> Patchwork_18012 CI-20190529: 20190529 CI_DRM_8658: c86979e2fe3c106d95b5fcf2075709afa40f0f95 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18012: 71234d269281c8b8a934040ef4eab9d2313acf92 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 71234d269281 drm/fb-helper: Fix vt restore == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/index.html From chris at chris-wilson.co.uk Tue Jun 23 16:36:18 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 17:36:18 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> Message-ID: <159293017861.3967.12926784772086320588@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) > Hi, Chris, > > On 6/22/20 11:59 AM, Chris Wilson wrote: > > In order to actually handle eviction and what not, we need to process > > all the objects together under a common lock, reservation_ww_class. As > > such, do a memory reservation pass after looking up the object/vma, > > which then feeds into the rest of execbuf [relocation, cmdparsing, > > flushing and ofc execution]. > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > --- > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > > 1 file changed, 70 insertions(+), 21 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > index 46fcbdf8161c..8db2e013465f 100644 > > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > > @@ -53,10 +53,9 @@ struct eb_vma_array { > > > > #define __EXEC_OBJECT_HAS_PIN BIT(31) > > #define __EXEC_OBJECT_HAS_FENCE BIT(30) > > -#define __EXEC_OBJECT_HAS_PAGES BIT(29) > > -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) > > -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) > > -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ > > +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) > > +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) > > +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ > > > > #define __EXEC_HAS_RELOC BIT(31) > > #define __EXEC_INTERNAL_FLAGS (~0u << 31) > > @@ -241,6 +240,8 @@ struct i915_execbuffer { > > struct intel_context *context; /* logical state for the request */ > > struct i915_gem_context *gem_context; /** caller's context */ > > > > + struct dma_fence *mm_fence; > > + > > struct i915_request *request; /** our request to build */ > > struct eb_vma *batch; /** identity of the batch obj/vma */ > > struct i915_vma *trampoline; /** trampoline used for chaining */ > > @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) > > if (ev->flags & __EXEC_OBJECT_HAS_PIN) > > __i915_vma_unpin(vma); > > > > - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > > - i915_gem_object_unpin_pages(vma->obj); > > - > > - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > > - __EXEC_OBJECT_HAS_FENCE | > > - __EXEC_OBJECT_HAS_PAGES); > > + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > > } > > > > static void eb_vma_array_destroy(struct kref *kref) > > @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > > list_add_tail(&ev->lock_link, &eb->lock); > > } > > > > +static int eb_vma_get_pages(struct i915_execbuffer *eb, > > + struct eb_vma *ev, > > + u64 idx) > > +{ > > + struct i915_vma *vma = ev->vma; > > + int err; > > + > > + /* XXX also preallocate PD for vma */ > > + > > + err = ____i915_gem_object_get_pages_async(vma->obj); > > + if (err) > > + return err; > > + > > + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > > +} > > + > > +static int eb_reserve_mm(struct i915_execbuffer *eb) > > +{ > > + const u64 idx = eb->context->timeline->fence_context; > > + struct ww_acquire_ctx acquire; > > + struct eb_vma *ev; > > + int err; > > + > > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > > + if (!eb->mm_fence) > > + return -ENOMEM; > > Question: eb is local to this thread, right, so eb->mm_fence is not > considered "published" yet? > > > + > > + ww_acquire_init(&acquire, &reservation_ww_class); > > + > > + err = eb_lock_vma(eb, &acquire); > > + if (err) > > + goto out; > > + > > + ww_acquire_done(&acquire); > > + > > + list_for_each_entry(ev, &eb->lock, lock_link) { > > + struct i915_vma *vma = ev->vma; > > + > > + if (err == 0) > > + err = eb_vma_get_pages(eb, ev, idx); > > I figure this is where you publish the proxy fence? If so, the fence > signaling critical path starts with this loop, Hmm, actually at this moment, the fence is still very much internal being only used as a reference token, and the async fence for the pages is still only in the internal migration slot [along side the reference tokens]. Those fences will not be attached to the dma_resv until the chains are completed in move-to-gpu. That might be enough of a difference to consider. -Chris From chris at chris-wilson.co.uk Tue Jun 23 16:37:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 17:37:54 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <5c0df713-ea47-71ff-9833-9e99b36c5474@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <5c0df713-ea47-71ff-9833-9e99b36c5474@shipmail.org> Message-ID: <159293027424.3967.5828636960136815373@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 16:37:30) > > On 6/23/20 12:03 PM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > >> Hi, Chris! > >> > >> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>> In order to actually handle eviction and what not, we need to process > >>> all the objects together under a common lock, reservation_ww_class. As > >>> such, do a memory reservation pass after looking up the object/vma, > >>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>> flushing and ofc execution]. > >>> > >>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>> --- > >>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>> > >> Which tree is this against? The series doesn't apply cleanly against > >> drm-tip? > > It's continuing on from the scheduler patches, the bug fixes and the > > iris-deferred-fence work. I thought throwing all of those old patches > > into the pile would have been distracting. > > Is there somewhere you could push a branch for reviewer consumption? I added some patches to remove some locked waits and having been regretting it all today. Coming soon, schedulers for all. -Chris From patchwork at emeril.freedesktop.org Tue Jun 23 16:38:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 16:38:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915=3A_Add_support_for_HDCP_1=2E4_over_MST?= In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <159293028039.4208.16868617419984002781@emeril.freedesktop.org> == Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST URL : https://patchwork.freedesktop.org/series/78749/ State : warning == Summary == $ dim checkpatch origin/drm-tip 40a9cf573823 drm/i915: Fix sha_text population code -:69: WARNING:LINE_SPACING: Missing a blank line after declarations #69: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:341: + u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); + sha_text |= ksv[j] << off; total: 0 errors, 1 warnings, 0 checks, 61 lines checked fdd9116bae73 drm/i915: Clear the repeater bit on HDCP disable 26c597bb2bdf drm/i915: WARN if HDCP signalling is enabled upon disable 2dfd826048e1 drm/i915: Intercept Aksv writes in the aux hooks f4a73566d2ac drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signalling 24dfa20af876 drm/i915: Factor out hdcp->value assignments -:75: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #75: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:931: + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, true); -:120: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #120: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:1800: + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, -:132: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #132: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:1815: + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, -:144: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #144: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:1835: + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_DESIRED, true); total: 0 errors, 0 warnings, 4 checks, 138 lines checked 96ac1382f6c4 drm/i915: Protect workers against disappearing connectors -:92: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #92: FILE: drivers/gpu/drm/i915/display/intel_hdcp.c:2198: + drm_WARN_ON(connector->base.dev, + connector->base.registration_state == DRM_CONNECTOR_REGISTERED); total: 0 errors, 0 warnings, 1 checks, 71 lines checked 5bef2450359c drm/i915: Clean up intel_hdcp_disable 6adefe67fdcb drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it 9118a955e697 drm/i915: Support DP MST in enc_to_dig_port() function 60fe26102e05 drm/i915: Use ddi_update_pipe in intel_dp_mst 294a579032b2 drm/i915: Factor out HDCP shim functions from dp for use by dp_mst -:687: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #687: new file mode 100644 -:692: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_dp_hdcp.c', please use '//' instead #692: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:1: +/* SPDX-License-Identifier: MIT */ -:692: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #692: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:1: +/* SPDX-License-Identifier: MIT */ -:872: WARNING:LINE_SPACING: Missing a blank line after declarations #872: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:181: + size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; + ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, -:1248: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #1248: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:557: + +} total: 0 errors, 4 warnings, 1 checks, 1274 lines checked e95d4796d643 drm/i915: Plumb port through hdcp init b159048d4ee3 drm/i915: Add connector to hdcp_shim->check_link() 43dca30ee7d8 drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message -:78: ERROR:CODE_INDENT: code indent should use tabs where possible #78: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:576: +^I^I^I^I^I^I^I ^I buf[idx]);$ -:78: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #78: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:576: +^I^I^I^I^I^I^I ^I buf[idx]);$ -:78: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #78: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:576: + req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2), + buf[idx]); -:109: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #109: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:971: +drm_dp_sideband_parse_query_stream_enc_status( -:179: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #179: FILE: drivers/gpu/drm/drm_dp_mst_topology.c:3232: +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, -:359: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #359: FILE: include/drm/drm_dp_mst_helper.h:853: +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, total: 1 errors, 1 warnings, 4 checks, 307 lines checked f415c158925f drm/i915: Print HDCP version info for all connectors ff0e9553b262 drm/i915: Add HDCP 1.4 support for MST connectors -:72: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #72: FILE: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:638: + drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n", + enable ? "Enable" : "Disable", ret); -:170: CHECK:LINE_SPACING: Please don't use multiple blank lines #170: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:783: + total: 0 errors, 0 warnings, 2 checks, 138 lines checked From patchwork at emeril.freedesktop.org Tue Jun 23 16:39:45 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 16:39:45 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?drm/i915=3A_Add_support_for_HDCP_1=2E4_over_MST?= In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <159293038590.4210.7896603796650202127@emeril.freedesktop.org> == Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST URL : https://patchwork.freedesktop.org/series/78749/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:184:13: warning: cast to restricted __le32 From chris at chris-wilson.co.uk Tue Jun 23 16:46:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 17:46:33 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <84641356-2c26-6208-e165-3cb6a143ca2c@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <e05ef872-8659-2a11-5c89-c42cf080905b@shipmail.org> <159292086189.10607.10450244252436195167@build.alporthouse.com> <3ea271d6-3101-62e0-8fb6-d433ba78ff17@shipmail.org> <159292905802.3967.14570193627723429860@build.alporthouse.com> <84641356-2c26-6208-e165-3cb6a143ca2c@shipmail.org> Message-ID: <159293079303.3967.6837309052965660392@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 17:29:46) > > On 6/23/20 6:17 PM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 16:09:08) > >> You can't take the dma_resv_lock inside a fence critical section. > > I much prefer the alternative interpretation, you can't wait inside a > > dma_resv_lock. > > -Chris > > I respect your point of view, athough I need to think we need to focus > on what we have to do in the i915 driver. While aiming for small steps, each improving upon the last. At the end of the day, whether it's an ww_mutex exclusive lock or a fence shared lock, it's all steps in the pipeline. -Chris From patchwork at emeril.freedesktop.org Tue Jun 23 16:58:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 23 Jun 2020 16:58:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Add_support_for_HDCP_1=2E4_over_MST?= In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <159293150973.4210.5254322716761785390@emeril.freedesktop.org> == Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST URL : https://patchwork.freedesktop.org/series/78749/ State : success == Summary == CI Bug Log - changes from CI_DRM_8658 -> Patchwork_18013 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/index.html Known issues ------------ Here are the changes found in Patchwork_18013 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-bsw-nick: [PASS][1] -> [INCOMPLETE][2] ([i915#1250] / [i915#1436]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-bsw-nick/igt at debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-bsw-nick/igt at debugfs_test@read_all_entries.html * igt at i915_pm_rpm@module-reload: - fi-bsw-n3050: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-bsw-n3050/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [INCOMPLETE][7] ([i915#1242]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html - fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-bsw-kefka/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-bsw-kefka/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/fi-kbl-x1275/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8658 -> Patchwork_18013 CI-20190529: 20190529 CI_DRM_8658: c86979e2fe3c106d95b5fcf2075709afa40f0f95 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18013: ff0e9553b262afa612271f33b6f768d8f39093e0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ff0e9553b262 drm/i915: Add HDCP 1.4 support for MST connectors f415c158925f drm/i915: Print HDCP version info for all connectors 43dca30ee7d8 drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message b159048d4ee3 drm/i915: Add connector to hdcp_shim->check_link() e95d4796d643 drm/i915: Plumb port through hdcp init 294a579032b2 drm/i915: Factor out HDCP shim functions from dp for use by dp_mst 60fe26102e05 drm/i915: Use ddi_update_pipe in intel_dp_mst 9118a955e697 drm/i915: Support DP MST in enc_to_dig_port() function 6adefe67fdcb drm/i915: Don't fully disable HDCP on a port if multiple pipes are using it 5bef2450359c drm/i915: Clean up intel_hdcp_disable 96ac1382f6c4 drm/i915: Protect workers against disappearing connectors 24dfa20af876 drm/i915: Factor out hdcp->value assignments f4a73566d2ac drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP signalling 2dfd826048e1 drm/i915: Intercept Aksv writes in the aux hooks 26c597bb2bdf drm/i915: WARN if HDCP signalling is enabled upon disable fdd9116bae73 drm/i915: Clear the repeater bit on HDCP disable 40a9cf573823 drm/i915: Fix sha_text population code == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/index.html From lucas.demarchi at intel.com Tue Jun 23 16:58:27 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Tue, 23 Jun 2020 09:58:27 -0700 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/display: remove alias to dig_port In-Reply-To: <20200623141606.GV6112@intel.com> References: <20200622232821.3093-1-lucas.demarchi@intel.com> <20200622232821.3093-2-lucas.demarchi@intel.com> <20200623141606.GV6112@intel.com> Message-ID: <20200623165827.tujntoytfsrm5hvt@ldmartin-desk1> On Tue, Jun 23, 2020 at 05:16:06PM +0300, Ville Syrj?l? wrote: >On Mon, Jun 22, 2020 at 04:28:20PM -0700, Lucas De Marchi wrote: >> We don't need intel_dig_port and dig_port to refer to the same thing. >> Prefer the latter. >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> >> Reviewed-by: Matt Roper <matthew.d.roper at intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++---- >> 1 file changed, 3 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c >> index ca7bb2294d2b..58c9f3d3e7ce 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c >> @@ -3382,11 +3382,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, >> const struct intel_crtc_state *crtc_state, >> const struct drm_connector_state *conn_state) >> { >> - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); >> - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; >> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); >> + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> int level = intel_ddi_hdmi_level(encoder); >> - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); >> >> intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); >> intel_ddi_clk_select(encoder, crtc_state); >> @@ -3413,7 +3412,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, >> >> intel_ddi_enable_pipe_clock(encoder, crtc_state); >> >> - intel_dig_port->set_infoframes(encoder, >> + dig_port->set_infoframes(encoder, >> crtc_state->has_infoframe, >> crtc_state, conn_state); > >Misalinged parameters staring me in the face here. Didn't trawl the >other patch for similar since it's so big. I did review the second one for misaligned things. I think I forgot to go back to this one because only after some review I noticed checkpatch was not failing for me for these misaligned parameters, not sure why. Lucas De Marchi > >> } >> -- >> 2.26.2 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > >-- >Ville Syrj?l? >Intel From cai at lca.pw Tue Jun 23 16:17:54 2020 From: cai at lca.pw (Qian Cai) Date: Tue, 23 Jun 2020 12:17:54 -0400 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200621200103.GV20149@phenom.ffwll.local> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> <20200621174205.GB1398@lca.pw> <CAKMK7uFZAFVmceoYvqPovOifGw_Y8Ey-OMy6wioMjwPWhu9dDg@mail.gmail.com> <20200621200103.GV20149@phenom.ffwll.local> Message-ID: <20200623161754.GA1140@lca.pw> On Sun, Jun 21, 2020 at 10:01:03PM +0200, Daniel Vetter wrote: > On Sun, Jun 21, 2020 at 08:07:08PM +0200, Daniel Vetter wrote: > > On Sun, Jun 21, 2020 at 7:42 PM Qian Cai <cai at lca.pw> wrote: > > > > > > On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > > > > fs_reclaim_acquire/release nicely catch recursion issues when > > > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > > > to use to keep the excessive caches in check). For mmu notifier > > > > recursions we do have lockdep annotations since 23b68395c7c7 > > > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > > > > > But these only fire if a path actually results in some pte > > > > invalidation - for most small allocations that's very rarely the case. > > > > The other trouble is that pte invalidation can happen any time when > > > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > > > recursion. > > > > > > > > I was pondering whether we should just do the general annotation, but > > > > there's always the risk for false positives. Plus I'm assuming that > > > > the core fs and io code is a lot better reviewed and tested than > > > > random mmu notifier code in drivers. Hence why I decide to only > > > > annotate for that specific case. > > > > > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > > > still need to explicit pull in the mmu notifier map - there's a lot > > > > more places that do pte invalidation than just direct reclaim, these > > > > two contexts arent the same. > > > > > > > > Note that the mmu notifiers needing their own independent lockdep map > > > > is also the reason we can't hold them from fs_reclaim_acquire to > > > > fs_reclaim_release - it would nest with the acquistion in the pte > > > > invalidation code, causing a lockdep splat. And we can't remove the > > > > annotations from pte invalidation and all the other places since > > > > they're called from many other places than page reclaim. Hence we can > > > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > > > strictly more powerful. > > > > > > > > v2: Review from Thomas Hellstrom: > > > > - unbotch the fs_reclaim context check, I accidentally inverted it, > > > > but it didn't blow up because I inverted it immediately > > > > - fix compiling for !CONFIG_MMU_NOTIFIER > > > > > > > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > > > Cc: linux-mm at kvack.org > > > > Cc: linux-rdma at vger.kernel.org > > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > > Cc: Christian K?nig <christian.koenig at amd.com> > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > > > Replying the right patch here... > > > > > > Reverting this commit [1] fixed the lockdep warning below while applying > > > some memory pressure. > > > > > > [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") > > > > Hm, then I'm confused because > > - there's not mmut notifier lockdep map in the splat at a.. > > - the patch is supposed to not change anything for fs_reclaim (but the > > interim version got that wrong) > > - looking at the paths it's kmalloc vs kswapd, both places I totally > > expect fs_reflaim to be used. > > > > But you're claiming reverting this prevents the lockdep splat. If > > that's right, then my reasoning above is broken somewhere. Someone > > less blind than me having an idea? > > > > Aside this is the first email I've typed, until I realized the first > > report was against the broken patch and that looked like a much more > > reasonable explanation (but didn't quite match up with the code > > paths). > > Below diff should undo the functional change in my patch. Can you pls test > whether the lockdep splat is really gone with that? Might need a lot of > testing and memory pressure to be sure, since all these reclaim paths > aren't very deterministic. No, this patch does not help but reverting the whole patch still fixed the splat. > -Daniel > > --- > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > index d807587c9ae6..27ea763c6155 100644 > --- a/mm/page_alloc.c > +++ b/mm/page_alloc.c > @@ -4191,11 +4191,6 @@ void fs_reclaim_acquire(gfp_t gfp_mask) > if (gfp_mask & __GFP_FS) > __fs_reclaim_acquire(); > > -#ifdef CONFIG_MMU_NOTIFIER > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > -#endif > - > } > } > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch From jose.souza at intel.com Tue Jun 23 17:31:46 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 23 Jun 2020 17:31:46 +0000 Subject: [Intel-gfx] [PATCH] drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled In-Reply-To: <20200623082411.3889-1-imre.deak@intel.com> References: <20200623082411.3889-1-imre.deak@intel.com> Message-ID: <0e9d806d5528e1752861a53dffc69b918f66d096.camel@intel.com> On Tue, 2020-06-23 at 11:24 +0300, Imre Deak wrote: > The spec requires enabling the MST Virtual Channel payload allocation > - in a seperate step - after the transcoder is enabled, follow this. > Is the next step but indeed a different step. Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++----- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ > 2 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 73d6cc29291a..884b507c5f55 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1653,7 +1653,6 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > - u32 ctl; > > if (INTEL_GEN(dev_priv) >= 11) { > enum transcoder master_transcoder = crtc_state->master_transcoder; > @@ -1671,10 +1670,9 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, > TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); > } > > - ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); > - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) > - ctl |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; > - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); > + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), > + intel_ddi_transcoder_func_reg_val_get(encoder, > + crtc_state)); > } > > /* > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 0c891bdd1aa0..3426ce8bbbd0 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -539,6 +539,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > struct intel_digital_port *intel_dig_port = intel_mst->primary; > struct intel_dp *intel_dp = &intel_dig_port->dp; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + u32 val; > > drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); > > @@ -546,6 +547,13 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > + val = intel_de_read(dev_priv, > + TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); > + val |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; > + intel_de_write(dev_priv, > + TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder), > + val); > + > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > intel_dp->active_mst_links); > From thomas_os at shipmail.org Tue Jun 23 18:21:28 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 20:21:28 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159293017861.3967.12926784772086320588@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> Message-ID: <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> On 6/23/20 6:36 PM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) >> Hi, Chris, >> >> On 6/22/20 11:59 AM, Chris Wilson wrote: >>> In order to actually handle eviction and what not, we need to process >>> all the objects together under a common lock, reservation_ww_class. As >>> such, do a memory reservation pass after looking up the object/vma, >>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>> flushing and ofc execution]. >>> >>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>> --- >>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>> 1 file changed, 70 insertions(+), 21 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>> index 46fcbdf8161c..8db2e013465f 100644 >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>> @@ -53,10 +53,9 @@ struct eb_vma_array { >>> >>> #define __EXEC_OBJECT_HAS_PIN BIT(31) >>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) >>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) >>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) >>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) >>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ >>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) >>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) >>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ >>> >>> #define __EXEC_HAS_RELOC BIT(31) >>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) >>> @@ -241,6 +240,8 @@ struct i915_execbuffer { >>> struct intel_context *context; /* logical state for the request */ >>> struct i915_gem_context *gem_context; /** caller's context */ >>> >>> + struct dma_fence *mm_fence; >>> + >>> struct i915_request *request; /** our request to build */ >>> struct eb_vma *batch; /** identity of the batch obj/vma */ >>> struct i915_vma *trampoline; /** trampoline used for chaining */ >>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) >>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) >>> __i915_vma_unpin(vma); >>> >>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) >>> - i915_gem_object_unpin_pages(vma->obj); >>> - >>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | >>> - __EXEC_OBJECT_HAS_FENCE | >>> - __EXEC_OBJECT_HAS_PAGES); >>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); >>> } >>> >>> static void eb_vma_array_destroy(struct kref *kref) >>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, >>> list_add_tail(&ev->lock_link, &eb->lock); >>> } >>> >>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, >>> + struct eb_vma *ev, >>> + u64 idx) >>> +{ >>> + struct i915_vma *vma = ev->vma; >>> + int err; >>> + >>> + /* XXX also preallocate PD for vma */ >>> + >>> + err = ____i915_gem_object_get_pages_async(vma->obj); >>> + if (err) >>> + return err; >>> + >>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); >>> +} >>> + >>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>> +{ >>> + const u64 idx = eb->context->timeline->fence_context; >>> + struct ww_acquire_ctx acquire; >>> + struct eb_vma *ev; >>> + int err; >>> + >>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); >>> + if (!eb->mm_fence) >>> + return -ENOMEM; >> Question: eb is local to this thread, right, so eb->mm_fence is not >> considered "published" yet? >> >>> + >>> + ww_acquire_init(&acquire, &reservation_ww_class); >>> + >>> + err = eb_lock_vma(eb, &acquire); >>> + if (err) >>> + goto out; >>> + >>> + ww_acquire_done(&acquire); >>> + >>> + list_for_each_entry(ev, &eb->lock, lock_link) { >>> + struct i915_vma *vma = ev->vma; >>> + >>> + if (err == 0) >>> + err = eb_vma_get_pages(eb, ev, idx); >> I figure this is where you publish the proxy fence? If so, the fence >> signaling critical path starts with this loop, > Hmm, actually at this moment, the fence is still very much internal > being only used as a reference token, I think as long as another thread, running in this driver or another gpu driver can theoretically reference the fence pointer from the reservation object and wait for the fence it's considered published. Also the ww_mutexes in this context are really all about grabbing a random set of resources and associate them with a point in a timeline, as the ww_mutexes are released, the fence pointer(s) need to point to published fence(s). /Thomas From chris at chris-wilson.co.uk Tue Jun 23 18:41:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 19:41:20 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> Message-ID: <159293768060.3967.16328770521784351822@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 19:21:28) > > On 6/23/20 6:36 PM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) > >> Hi, Chris, > >> > >> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>> In order to actually handle eviction and what not, we need to process > >>> all the objects together under a common lock, reservation_ww_class. As > >>> such, do a memory reservation pass after looking up the object/vma, > >>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>> flushing and ofc execution]. > >>> > >>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>> --- > >>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>> index 46fcbdf8161c..8db2e013465f 100644 > >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>> @@ -53,10 +53,9 @@ struct eb_vma_array { > >>> > >>> #define __EXEC_OBJECT_HAS_PIN BIT(31) > >>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) > >>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) > >>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) > >>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) > >>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ > >>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) > >>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) > >>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ > >>> > >>> #define __EXEC_HAS_RELOC BIT(31) > >>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) > >>> @@ -241,6 +240,8 @@ struct i915_execbuffer { > >>> struct intel_context *context; /* logical state for the request */ > >>> struct i915_gem_context *gem_context; /** caller's context */ > >>> > >>> + struct dma_fence *mm_fence; > >>> + > >>> struct i915_request *request; /** our request to build */ > >>> struct eb_vma *batch; /** identity of the batch obj/vma */ > >>> struct i915_vma *trampoline; /** trampoline used for chaining */ > >>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) > >>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) > >>> __i915_vma_unpin(vma); > >>> > >>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > >>> - i915_gem_object_unpin_pages(vma->obj); > >>> - > >>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > >>> - __EXEC_OBJECT_HAS_FENCE | > >>> - __EXEC_OBJECT_HAS_PAGES); > >>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > >>> } > >>> > >>> static void eb_vma_array_destroy(struct kref *kref) > >>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > >>> list_add_tail(&ev->lock_link, &eb->lock); > >>> } > >>> > >>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, > >>> + struct eb_vma *ev, > >>> + u64 idx) > >>> +{ > >>> + struct i915_vma *vma = ev->vma; > >>> + int err; > >>> + > >>> + /* XXX also preallocate PD for vma */ > >>> + > >>> + err = ____i915_gem_object_get_pages_async(vma->obj); > >>> + if (err) > >>> + return err; > >>> + > >>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > >>> +} > >>> + > >>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>> +{ > >>> + const u64 idx = eb->context->timeline->fence_context; > >>> + struct ww_acquire_ctx acquire; > >>> + struct eb_vma *ev; > >>> + int err; > >>> + > >>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>> + if (!eb->mm_fence) > >>> + return -ENOMEM; > >> Question: eb is local to this thread, right, so eb->mm_fence is not > >> considered "published" yet? > >> > >>> + > >>> + ww_acquire_init(&acquire, &reservation_ww_class); > >>> + > >>> + err = eb_lock_vma(eb, &acquire); > >>> + if (err) > >>> + goto out; > >>> + > >>> + ww_acquire_done(&acquire); > >>> + > >>> + list_for_each_entry(ev, &eb->lock, lock_link) { > >>> + struct i915_vma *vma = ev->vma; > >>> + > >>> + if (err == 0) > >>> + err = eb_vma_get_pages(eb, ev, idx); > >> I figure this is where you publish the proxy fence? If so, the fence > >> signaling critical path starts with this loop, > > Hmm, actually at this moment, the fence is still very much internal > > being only used as a reference token, > I think as long as another thread, running in this driver or another gpu > driver can theoretically reference the fence pointer from the > reservation object and wait for the fence it's considered published. It's not in the reservation object. > Also the ww_mutexes in this context are really all about grabbing a > random set of resources and associate them with a point in a timeline, > as the ww_mutexes are released, the fence pointer(s) need to point to > published fence(s). That's not the purpose of these fences, though. They exist to provide reference counting on the backing store, along side the migration fence. It's extra detail tacked on the equivalent of bo->moving. That is not to say that one could build up an async migration chain which form a graph back to these, that chain could only be formed once the operation itself has been published in the dma_resv though. -Chris From felix.kuehling at amd.com Tue Jun 23 18:44:24 2020 From: felix.kuehling at amd.com (Felix Kuehling) Date: Tue, 23 Jun 2020 14:44:24 -0400 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <CAKMK7uHBKrpDWu+DvtYncDK=LOdGJyMK7t6fpOaGovnYFiBUZw@mail.gmail.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> <CAKMK7uHBKrpDWu+DvtYncDK=LOdGJyMK7t6fpOaGovnYFiBUZw@mail.gmail.com> Message-ID: <99758c09-262a-e9a1-bf65-5702b35b4388@amd.com> Am 2020-06-23 um 3:39 a.m. schrieb Daniel Vetter: > On Fri, Jun 12, 2020 at 1:35 AM Felix Kuehling <felix.kuehling at amd.com> wrote: >> Am 2020-06-11 um 10:15 a.m. schrieb Jason Gunthorpe: >>> On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: >>>>> I still have my doubts about allowing fence waiting from within shrinkers. >>>>> IMO ideally they should use a trywait approach, in order to allow memory >>>>> allocation during command submission for drivers that >>>>> publish fences before command submission. (Since early reservation object >>>>> release requires that). >>>> Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up >>>> with a mempool to make sure it can handle it's allocations. >>>> >>>>> But since drivers are already waiting from within shrinkers and I take your >>>>> word for HMM requiring this, >>>> Yeah the big trouble is HMM and mmu notifiers. That's the really awkward >>>> one, the shrinker one is a lot less established. >>> I really question if HW that needs something like DMA fence should >>> even be using mmu notifiers - the best use is HW that can fence the >>> DMA directly without having to get involved with some command stream >>> processing. >>> >>> Or at the very least it should not be a generic DMA fence but a >>> narrowed completion tied only into the same GPU driver's command >>> completion processing which should be able to progress without >>> blocking. >>> >>> The intent of notifiers was never to endlessly block while vast >>> amounts of SW does work. >>> >>> Going around and switching everything in a GPU to GFP_ATOMIC seems >>> like bad idea. >>> >>>> I've pinged a bunch of armsoc gpu driver people and ask them how much this >>>> hurts, so that we have a clear answer. On x86 I don't think we have much >>>> of a choice on this, with userptr in amd and i915 and hmm work in nouveau >>>> (but nouveau I think doesn't use dma_fence in there). >> Soon nouveau will get company. We're working on a recoverable page fault >> implementation for HMM in amdgpu where we'll need to update page tables >> using the GPUs SDMA engine and wait for corresponding fences in MMU >> notifiers. > Can you pls cc these patches to dri-devel when they show up? Depending > upon how your hw works there's and endless amount of bad things that > can happen. Yes, I'll do that. > > Also I think (again depending upon how the hw exactly works) this > stuff would be a perfect example for the dma_fence annotations. We have already applied your patch series to our development branch. I haven't looked into what annotations we'd have to add to our new code yet. > > The worst case is if your hw cannot preempt while a hw page fault is > pending. That means none of the dma_fence will ever signal (the amdkfd > preempt ctx fences wont, and the classic fences from amdgpu might be > also stall). At least when you're unlucky and the fence you're waiting > on somehow (anywhere in its dependency chain really) need the engine > that's currently blocked waiting for the hw page fault. Our HW can preempt while handling a page fault, at least on the GPU generation we're working on now. On other GPUs we haven't included in our initial effort, we will not be able to preempt while a page fault is in progress. This is problematic, but that's for reasons related to our GPU hardware scheduler and unrelated to fences. > > That in turn means anything you do in your hw page fault handler is in > the critical section for dma fence signalling, which has far reaching > implications. I'm not sure I agree, at least for KFD. The only place where KFD uses fences that depend on preemptions is eviction fences. And we can get rid of those if we can preempt GPU access to specific BOs by invalidating GPU PTEs. That way we don't need to preempt the GPU queues while a page fault is in progress. Instead we would create more page faults. That assumes that we can invalidate GPU PTEs without depending on fences. We've discussed possible deadlocks due to memory allocations needed on that code paths for IBs or page tables. We've already eliminated page table allocations and reservation locks on the PTE invalidation code path. And we're using a separate scheduler entity so we can't get stuck behind other IBs that depend on fences. IIRC, Christian also implemented a separate memory pool for IBs for this code path. Regards, ? Felix > -Daniel > >> Regards, >> Felix >> >> >>> Right, nor will RDMA ODP. >>> >>> Jason >>> _______________________________________________ >>> amd-gfx mailing list >>> amd-gfx at lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> _______________________________________________ >> dri-devel mailing list >> dri-devel at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > > From daniel at ffwll.ch Tue Jun 23 19:02:33 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Tue, 23 Jun 2020 21:02:33 +0200 Subject: [Intel-gfx] [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations In-Reply-To: <99758c09-262a-e9a1-bf65-5702b35b4388@amd.com> References: <20200604081224.863494-1-daniel.vetter@ffwll.ch> <20200604081224.863494-5-daniel.vetter@ffwll.ch> <b11c2140-1b9c-9013-d9bb-9eb2c1906710@shipmail.org> <20200611083430.GD20149@phenom.ffwll.local> <20200611141515.GW6578@ziepe.ca> <4702e170-fd02-88fa-3da4-ea64252fff9a@amd.com> <CAKMK7uHBKrpDWu+DvtYncDK=LOdGJyMK7t6fpOaGovnYFiBUZw@mail.gmail.com> <99758c09-262a-e9a1-bf65-5702b35b4388@amd.com> Message-ID: <20200623190233.GP20149@phenom.ffwll.local> On Tue, Jun 23, 2020 at 02:44:24PM -0400, Felix Kuehling wrote: > Am 2020-06-23 um 3:39 a.m. schrieb Daniel Vetter: > > On Fri, Jun 12, 2020 at 1:35 AM Felix Kuehling <felix.kuehling at amd.com> wrote: > >> Am 2020-06-11 um 10:15 a.m. schrieb Jason Gunthorpe: > >>> On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: > >>>>> I still have my doubts about allowing fence waiting from within shrinkers. > >>>>> IMO ideally they should use a trywait approach, in order to allow memory > >>>>> allocation during command submission for drivers that > >>>>> publish fences before command submission. (Since early reservation object > >>>>> release requires that). > >>>> Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up > >>>> with a mempool to make sure it can handle it's allocations. > >>>> > >>>>> But since drivers are already waiting from within shrinkers and I take your > >>>>> word for HMM requiring this, > >>>> Yeah the big trouble is HMM and mmu notifiers. That's the really awkward > >>>> one, the shrinker one is a lot less established. > >>> I really question if HW that needs something like DMA fence should > >>> even be using mmu notifiers - the best use is HW that can fence the > >>> DMA directly without having to get involved with some command stream > >>> processing. > >>> > >>> Or at the very least it should not be a generic DMA fence but a > >>> narrowed completion tied only into the same GPU driver's command > >>> completion processing which should be able to progress without > >>> blocking. > >>> > >>> The intent of notifiers was never to endlessly block while vast > >>> amounts of SW does work. > >>> > >>> Going around and switching everything in a GPU to GFP_ATOMIC seems > >>> like bad idea. > >>> > >>>> I've pinged a bunch of armsoc gpu driver people and ask them how much this > >>>> hurts, so that we have a clear answer. On x86 I don't think we have much > >>>> of a choice on this, with userptr in amd and i915 and hmm work in nouveau > >>>> (but nouveau I think doesn't use dma_fence in there). > >> Soon nouveau will get company. We're working on a recoverable page fault > >> implementation for HMM in amdgpu where we'll need to update page tables > >> using the GPUs SDMA engine and wait for corresponding fences in MMU > >> notifiers. > > Can you pls cc these patches to dri-devel when they show up? Depending > > upon how your hw works there's and endless amount of bad things that > > can happen. > > Yes, I'll do that. > > > > > > Also I think (again depending upon how the hw exactly works) this > > stuff would be a perfect example for the dma_fence annotations. > > We have already applied your patch series to our development branch. I > haven't looked into what annotations we'd have to add to our new code yet. > > > > > > The worst case is if your hw cannot preempt while a hw page fault is > > pending. That means none of the dma_fence will ever signal (the amdkfd > > preempt ctx fences wont, and the classic fences from amdgpu might be > > also stall). At least when you're unlucky and the fence you're waiting > > on somehow (anywhere in its dependency chain really) need the engine > > that's currently blocked waiting for the hw page fault. > > Our HW can preempt while handling a page fault, at least on the GPU > generation we're working on now. On other GPUs we haven't included in > our initial effort, we will not be able to preempt while a page fault is > in progress. This is problematic, but that's for reasons related to our > GPU hardware scheduler and unrelated to fences. Well the trouble is if the page fault holds up a preempt, then there's no way for a dma_fence to complete while your hw page fault handler is stuck doing whatever. That means the entire hw page fault becomes a fence signalling critical section, with the consequence that there's almost nothing you can actually do. System memory becomes GFP_ATOMIC only, and for vram you need to make sure that you never evict anything that might be in active use. So not enabling these platforms sounds like a very good plan to me :-) > > That in turn means anything you do in your hw page fault handler is in > > the critical section for dma fence signalling, which has far reaching > > implications. > > I'm not sure I agree, at least for KFD. The only place where KFD uses > fences that depend on preemptions is eviction fences. And we can get rid > of those if we can preempt GPU access to specific BOs by invalidating > GPU PTEs. That way we don't need to preempt the GPU queues while a page > fault is in progress. Instead we would create more page faults. The big problem isn't pure kfd workloads, all the trouble comes in when you mix kfd and amdgpu workloads. kfd alone is easy, just make sure there's no fences to begin with, and there will be no problems. > That assumes that we can invalidate GPU PTEs without depending on > fences. We've discussed possible deadlocks due to memory allocations > needed on that code paths for IBs or page tables. We've already > eliminated page table allocations and reservation locks on the PTE > invalidation code path. And we're using a separate scheduler entity so > we can't get stuck behind other IBs that depend on fences. IIRC, > Christian also implemented a separate memory pool for IBs for this code > path. Yeah it's the memory allocations that kill you. Both system memory, but also vram. Since evicting vram might mean you end up stuck behind a dma_fence of a legacy context hogging that memory, and probably also means doing a few dma_resv_lock. All of these thing deadlock if you can't preempt the context with something else. -Daniel > > Regards, > ? Felix > > > > -Daniel > > > >> Regards, > >> Felix > >> > >> > >>> Right, nor will RDMA ODP. > >>> > >>> Jason > >>> _______________________________________________ > >>> amd-gfx mailing list > >>> amd-gfx at lists.freedesktop.org > >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >> _______________________________________________ > >> dri-devel mailing list > >> dri-devel at lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > > > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From manasi.d.navare at intel.com Tue Jun 23 19:26:41 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 23 Jun 2020 12:26:41 -0700 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200622170651.GQ6112@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> <20200622170651.GQ6112@intel.com> Message-ID: <20200623192641.GA22294@intel.com> On Mon, Jun 22, 2020 at 08:06:51PM +0300, Ville Syrj?l? wrote: > On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote: > > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote: > > > Modify the helper to add a fixed delay or poll with timeout > > > based on platform specification in bothe enable and disable > > > cases so check for either Idle bit set (DDI_BUF_CTL is idle > > > for disable case) or check for Idle bit = 0 (non idle for > > > DDI BUF enable case) > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++--------- > > > 1 file changed, 21 insertions(+), 13 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index ca7bb2294d2b..e4738c3b6d44 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > > } > > > > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > > - enum port port) > > > > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ? > > I'd just make it two functions. Avoids that stupid boolean > parameter. Just have 2 functions: 1. intel_ddi_wait_for_ddi_buf_idle() 2. intel_ddi_wait_for_ddi_buf_active or _non_idle()? Hmm but wouldnt it be more readable if we pass that bool and use the same function? Manasi > > > > > > + enum port port, bool idle) > > > { > > > - i915_reg_t reg = DDI_BUF_CTL(port); > > > - int i; > > > - > > > - for (i = 0; i < 16; i++) { > > > - udelay(1); > > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > > - return; > > > + if (idle) { > > > + if (IS_BROXTON(dev_priv)) > > > + udelay(16); > > > + else > > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), 16)) > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > + port_name(port)); > > > + } else { > > > + if (INTEL_GEN(dev_priv) < 10) > > > + udelay(600); > > > + else > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), 600)) > > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > > + port_name(port)); > > > } > > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > - port_name(port)); > > > + > > > > since we can only guarantee a minimum delay or timeout, imo it could be just: > > > > if (BXT && !active || GEN <= 9 && active) { > > usleep_range(600, 1000); > > return; > > } > > > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600)) > > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n", > > port, active ? "active" : "idle")); > > > > > > > } > > > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); > > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); > > > > > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E); > > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true); > > > > > > /* Reset FDI_RX_MISC pwrdn lanes */ > > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); > > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, > > > intel_ddi_disable_fec_state(encoder, crtc_state); > > > > > > if (wait) > > > - intel_wait_ddi_buf_idle(dev_priv, port); > > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > > } > > > > > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, > > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); > > > > > > if (wait) > > > - intel_wait_ddi_buf_idle(dev_priv, port); > > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > > } > > > > > > dp_tp_ctl = DP_TP_CTL_ENABLE | > > > > The DSI code could also use the new helper. > > > > > -- > > > 2.19.1 > > > > > -- > Ville Syrj?l? > Intel From manasi.d.navare at intel.com Tue Jun 23 19:42:00 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 23 Jun 2020 12:42:00 -0700 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200622154921.GA25163@ideak-desk.fi.intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> Message-ID: <20200623194200.GB22294@intel.com> On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote: > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote: > > Modify the helper to add a fixed delay or poll with timeout > > based on platform specification in bothe enable and disable > > cases so check for either Idle bit set (DDI_BUF_CTL is idle > > for disable case) or check for Idle bit = 0 (non idle for > > DDI BUF enable case) > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++--------- > > 1 file changed, 21 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index ca7bb2294d2b..e4738c3b6d44 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > } > > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > - enum port port) > > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ? So here you mean active which is true if we are checking during enable for non_idle and vice versa for disable, active will be false or checking for idel state? > > > + enum port port, bool idle) > > { > > - i915_reg_t reg = DDI_BUF_CTL(port); > > - int i; > > - > > - for (i = 0; i < 16; i++) { > > - udelay(1); > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > - return; > > + if (idle) { > > + if (IS_BROXTON(dev_priv)) > > + udelay(16); > > + else > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 16)) > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > + port_name(port)); > > + } else { > > + if (INTEL_GEN(dev_priv) < 10) > > + udelay(600); > > + else > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 600)) > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > + port_name(port)); > > } > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > - port_name(port)); > > + > > since we can only guarantee a minimum delay or timeout, imo it could be just: > > if (BXT && !active || GEN <= 9 && active) { > usleep_range(600, 1000); > return; Didnt quite understand this logic, for BXT & !active which is BXT and idle, it shd be fixed delay of just 16usecs or if it is !BXT and !active then we wait with a timeout also for gen <=9 and active, it shd be fixed delay of 600 and greater than or = 10 and active should be a timeout Manasi > } > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600)) > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n", > port, active ? "active" : "idle")); > > > > } > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); > > > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E); > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true); > > > > /* Reset FDI_RX_MISC pwrdn lanes */ > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, > > intel_ddi_disable_fec_state(encoder, crtc_state); > > > > if (wait) > > - intel_wait_ddi_buf_idle(dev_priv, port); > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > } > > > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); > > > > if (wait) > > - intel_wait_ddi_buf_idle(dev_priv, port); > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > } > > > > dp_tp_ctl = DP_TP_CTL_ENABLE | > > The DSI code could also use the new helper. > > > -- > > 2.19.1 > > From imre.deak at intel.com Tue Jun 23 19:57:10 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 23 Jun 2020 22:57:10 +0300 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200623194200.GB22294@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> <20200623194200.GB22294@intel.com> Message-ID: <20200623195710.GC7681@ideak-desk.fi.intel.com> On Tue, Jun 23, 2020 at 12:42:00PM -0700, Manasi Navare wrote: > On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote: > > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote: > > > Modify the helper to add a fixed delay or poll with timeout > > > based on platform specification in bothe enable and disable > > > cases so check for either Idle bit set (DDI_BUF_CTL is idle > > > for disable case) or check for Idle bit = 0 (non idle for > > > DDI BUF enable case) > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++--------- > > > 1 file changed, 21 insertions(+), 13 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index ca7bb2294d2b..e4738c3b6d44 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > > } > > > > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > > - enum port port) > > > > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ? > > So here you mean active which is true if we are checking during enable for non_idle > and vice versa for disable, active will be false or checking for idel state? Maybe just use Ville's idea with two functions instead. > > > > > > + enum port port, bool idle) > > > { > > > - i915_reg_t reg = DDI_BUF_CTL(port); > > > - int i; > > > - > > > - for (i = 0; i < 16; i++) { > > > - udelay(1); > > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > > - return; > > > + if (idle) { > > > + if (IS_BROXTON(dev_priv)) > > > + udelay(16); > > > + else > > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), 16)) > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > + port_name(port)); > > > + } else { > > > + if (INTEL_GEN(dev_priv) < 10) > > > + udelay(600); > > > + else > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), 600)) > > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > > + port_name(port)); > > > } > > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > - port_name(port)); > > > + > > > > since we can only guarantee a minimum delay or timeout, imo it could be just: > > > > if (BXT && !active || GEN <= 9 && active) { > > usleep_range(600, 1000); > > return; > > Didnt quite understand this logic, for BXT & !active which is BXT and > idle, it shd be fixed delay of just 16usecs > or if it is !BXT and !active then we wait with a timeout > also for gen <=9 and active, it shd be fixed delay of 600 > and greater than or = 10 and active should be a timeout yes, the above would match what I provided. The fixed delay for all platforms would be a minimum 600usec delay. You can't guarantee that the delay would be only 16usec in any case, so using 600 usec on BXT too would be ok. > Manasi > > > } > > > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600)) > > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n", > > port, active ? "active" : "idle")); > > > > > > > } > > > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); > > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); > > > > > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E); > > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true); > > > > > > /* Reset FDI_RX_MISC pwrdn lanes */ > > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); > > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, > > > intel_ddi_disable_fec_state(encoder, crtc_state); > > > > > > if (wait) > > > - intel_wait_ddi_buf_idle(dev_priv, port); > > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > > } > > > > > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, > > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); > > > > > > if (wait) > > > - intel_wait_ddi_buf_idle(dev_priv, port); > > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > > } > > > > > > dp_tp_ctl = DP_TP_CTL_ENABLE | > > > > The DSI code could also use the new helper. > > > > > -- > > > 2.19.1 > > > From manasi.d.navare at intel.com Tue Jun 23 20:32:50 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 23 Jun 2020 13:32:50 -0700 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200623195710.GC7681@ideak-desk.fi.intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> <20200623194200.GB22294@intel.com> <20200623195710.GC7681@ideak-desk.fi.intel.com> Message-ID: <20200623203250.GC22294@intel.com> On Tue, Jun 23, 2020 at 10:57:10PM +0300, Imre Deak wrote: > On Tue, Jun 23, 2020 at 12:42:00PM -0700, Manasi Navare wrote: > > On Mon, Jun 22, 2020 at 06:49:26PM +0300, Imre Deak wrote: > > > On Wed, Jun 17, 2020 at 05:01:23PM -0700, Manasi Navare wrote: > > > > Modify the helper to add a fixed delay or poll with timeout > > > > based on platform specification in bothe enable and disable > > > > cases so check for either Idle bit set (DDI_BUF_CTL is idle > > > > for disable case) or check for Idle bit = 0 (non idle for > > > > DDI BUF enable case) > > > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Cc: Imre Deak <imre.deak at intel.com> > > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++--------- > > > > 1 file changed, 21 insertions(+), 13 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index ca7bb2294d2b..e4738c3b6d44 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > @@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > > > } > > > > > > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > > > - enum port port) > > > > > > maybe intel_ddi_wait_for_ddi_buf(i915, port, active) ? > > > > So here you mean active which is true if we are checking during enable for non_idle > > and vice versa for disable, active will be false or checking for idel state? > > Maybe just use Ville's idea with two functions instead. > > > > > > > > > > + enum port port, bool idle) > > > > { > > > > - i915_reg_t reg = DDI_BUF_CTL(port); > > > > - int i; > > > > - > > > > - for (i = 0; i < 16; i++) { > > > > - udelay(1); > > > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > > > - return; > > > > + if (idle) { > > > > + if (IS_BROXTON(dev_priv)) > > > > + udelay(16); > > > > + else > > > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > > + DDI_BUF_IS_IDLE), 16)) > > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > > + port_name(port)); > > > > + } else { > > > > + if (INTEL_GEN(dev_priv) < 10) > > > > + udelay(600); > > > > + else > > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > > + DDI_BUF_IS_IDLE), 600)) > > > > + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", > > > > + port_name(port)); > > > > } > > > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > > - port_name(port)); > > > > + > > > > > > since we can only guarantee a minimum delay or timeout, imo it could be just: > > > > > > if (BXT && !active || GEN <= 9 && active) { > > > usleep_range(600, 1000); > > > return; > > > > > Didnt quite understand this logic, for BXT & !active which is BXT and > > idle, it shd be fixed delay of just 16usecs > > or if it is !BXT and !active then we wait with a timeout > > also for gen <=9 and active, it shd be fixed delay of 600 > > and greater than or = 10 and active should be a timeout > > yes, the above would match what I provided. The fixed delay for all > platforms would be a minimum 600usec delay. You can't guarantee that the > delay would be only 16usec in any case, so using 600 usec on BXT too > would be ok. still dont quite get it, how is usleep_range (600, 1000) providing a fixed delay? Now if we split ino 2 functs, one for disable, for that: if (BXT) usleep_range(600, 1000) else wait_for_us(check if Idle bit set) so in both functions, for the timeout part we still use the wait_for_us helper right? Manasi > > > Manasi > > > > > } > > > > > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE) == active, 600)) > > > drm_err("Port %c: Timeout waiting for DDI BUF to get %s\n", > > > port, active ? "active" : "idle")); > > > > > > > > > > } > > > > > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > > > @@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > > > > intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); > > > > intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); > > > > > > > > - intel_wait_ddi_buf_idle(dev_priv, PORT_E); > > > > + intel_wait_ddi_buf_idle(dev_priv, PORT_E, true); > > > > > > > > /* Reset FDI_RX_MISC pwrdn lanes */ > > > > temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); > > > > @@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, > > > > intel_ddi_disable_fec_state(encoder, crtc_state); > > > > > > > > if (wait) > > > > - intel_wait_ddi_buf_idle(dev_priv, port); > > > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > > > } > > > > > > > > static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, > > > > @@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > > > intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); > > > > > > > > if (wait) > > > > - intel_wait_ddi_buf_idle(dev_priv, port); > > > > + intel_wait_ddi_buf_idle(dev_priv, port, true); > > > > } > > > > > > > > dp_tp_ctl = DP_TP_CTL_ENABLE | > > > > > > The DSI code could also use the new helper. > > > > > > > -- > > > > 2.19.1 > > > > From thomas_os at shipmail.org Tue Jun 23 20:31:38 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Tue, 23 Jun 2020 22:31:38 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159293768060.3967.16328770521784351822@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> <159293768060.3967.16328770521784351822@build.alporthouse.com> Message-ID: <88f746c6-c6ad-8c19-7797-856ac6bb2f50@shipmail.org> On 6/23/20 8:41 PM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-23 19:21:28) >> On 6/23/20 6:36 PM, Chris Wilson wrote: >>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) >>>> Hi, Chris, >>>> >>>> On 6/22/20 11:59 AM, Chris Wilson wrote: >>>>> In order to actually handle eviction and what not, we need to process >>>>> all the objects together under a common lock, reservation_ww_class. As >>>>> such, do a memory reservation pass after looking up the object/vma, >>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>>>> flushing and ofc execution]. >>>>> >>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>>>> --- >>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>>>> 1 file changed, 70 insertions(+), 21 deletions(-) >>>>> >>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>> index 46fcbdf8161c..8db2e013465f 100644 >>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>> @@ -53,10 +53,9 @@ struct eb_vma_array { >>>>> >>>>> #define __EXEC_OBJECT_HAS_PIN BIT(31) >>>>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) >>>>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) >>>>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) >>>>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) >>>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ >>>>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) >>>>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) >>>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ >>>>> >>>>> #define __EXEC_HAS_RELOC BIT(31) >>>>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) >>>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { >>>>> struct intel_context *context; /* logical state for the request */ >>>>> struct i915_gem_context *gem_context; /** caller's context */ >>>>> >>>>> + struct dma_fence *mm_fence; >>>>> + >>>>> struct i915_request *request; /** our request to build */ >>>>> struct eb_vma *batch; /** identity of the batch obj/vma */ >>>>> struct i915_vma *trampoline; /** trampoline used for chaining */ >>>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) >>>>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) >>>>> __i915_vma_unpin(vma); >>>>> >>>>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) >>>>> - i915_gem_object_unpin_pages(vma->obj); >>>>> - >>>>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | >>>>> - __EXEC_OBJECT_HAS_FENCE | >>>>> - __EXEC_OBJECT_HAS_PAGES); >>>>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); >>>>> } >>>>> >>>>> static void eb_vma_array_destroy(struct kref *kref) >>>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, >>>>> list_add_tail(&ev->lock_link, &eb->lock); >>>>> } >>>>> >>>>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, >>>>> + struct eb_vma *ev, >>>>> + u64 idx) >>>>> +{ >>>>> + struct i915_vma *vma = ev->vma; >>>>> + int err; >>>>> + >>>>> + /* XXX also preallocate PD for vma */ >>>>> + >>>>> + err = ____i915_gem_object_get_pages_async(vma->obj); >>>>> + if (err) >>>>> + return err; >>>>> + >>>>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); >>>>> +} >>>>> + >>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>>>> +{ >>>>> + const u64 idx = eb->context->timeline->fence_context; >>>>> + struct ww_acquire_ctx acquire; >>>>> + struct eb_vma *ev; >>>>> + int err; >>>>> + >>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); >>>>> + if (!eb->mm_fence) >>>>> + return -ENOMEM; >>>> Question: eb is local to this thread, right, so eb->mm_fence is not >>>> considered "published" yet? >>>> >>>>> + >>>>> + ww_acquire_init(&acquire, &reservation_ww_class); >>>>> + >>>>> + err = eb_lock_vma(eb, &acquire); >>>>> + if (err) >>>>> + goto out; >>>>> + >>>>> + ww_acquire_done(&acquire); >>>>> + >>>>> + list_for_each_entry(ev, &eb->lock, lock_link) { >>>>> + struct i915_vma *vma = ev->vma; >>>>> + >>>>> + if (err == 0) >>>>> + err = eb_vma_get_pages(eb, ev, idx); >>>> I figure this is where you publish the proxy fence? If so, the fence >>>> signaling critical path starts with this loop, >>> Hmm, actually at this moment, the fence is still very much internal >>> being only used as a reference token, >> I think as long as another thread, running in this driver or another gpu >> driver can theoretically reference the fence pointer from the >> reservation object and wait for the fence it's considered published. > It's not in the reservation object. > >> Also the ww_mutexes in this context are really all about grabbing a >> random set of resources and associate them with a point in a timeline, >> as the ww_mutexes are released, the fence pointer(s) need to point to >> published fence(s). > That's not the purpose of these fences, though. They exist to provide > reference counting on the backing store, along side the migration fence. > It's extra detail tacked on the equivalent of bo->moving. > > That is not to say that one could build up an async migration chain which > form a graph back to these, that chain could only be formed once the > operation itself has been published in the dma_resv though. Hmm. So let's say another thread grabs one of the just released ww_mutexes and wants to schedule a blit from one of the buffers in the current operation with high priority. How would that thread know how to order that blit operation w r t the current operation? /Thomas > -Chris From imre.deak at intel.com Tue Jun 23 20:50:27 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 23 Jun 2020 23:50:27 +0300 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200623203250.GC22294@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> <20200623194200.GB22294@intel.com> <20200623195710.GC7681@ideak-desk.fi.intel.com> <20200623203250.GC22294@intel.com> Message-ID: <20200623205027.GD7681@ideak-desk.fi.intel.com> On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote: > still dont quite get it, how is usleep_range (600, 1000) providing a fixed delay? Not sure what you mean. udelay is busy looping, while usleep_range sleeps instead. How to chose between udelay/usleep_range please read Documentation/timers/timers-howto.rst > Now if we split ino 2 functs, one for disable, for that: > > if (BXT) > usleep_range(600, 1000) > else > wait_for_us(check if Idle bit set) > > so in both functions, for the timeout part we still use the wait_for_us helper right? with two functions it would get: intel_ddi_wait_for_ddi_buf_active(i915, port) { if (GEN <= 9) { usleep_range(600, 1000); return; } if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600)) drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port)); } intel_ddi_wait_for_ddi_buf_idle(i915, port) { if (BXT) { udelay(16); return; } if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600)) drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port)); } --Imre From airlied at gmail.com Tue Jun 23 21:01:24 2020 From: airlied at gmail.com (Dave Airlie) Date: Wed, 24 Jun 2020 07:01:24 +1000 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159290661156.6856.12185315246799210214@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> Message-ID: <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > > Hi, Chris! > > > > On 6/22/20 11:59 AM, Chris Wilson wrote: > > > In order to actually handle eviction and what not, we need to process > > > all the objects together under a common lock, reservation_ww_class. As > > > such, do a memory reservation pass after looking up the object/vma, > > > which then feeds into the rest of execbuf [relocation, cmdparsing, > > > flushing and ofc execution]. > > > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > > --- > > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > > > 1 file changed, 70 insertions(+), 21 deletions(-) > > > > > Which tree is this against? The series doesn't apply cleanly against > > drm-tip? > > It's continuing on from the scheduler patches, the bug fixes and the > iris-deferred-fence work. I thought throwing all of those old patches > into the pile would have been distracting. > > > ... > > > > > +static int eb_reserve_mm(struct i915_execbuffer *eb) > > > +{ > > > + const u64 idx = eb->context->timeline->fence_context; > > > + struct ww_acquire_ctx acquire; > > > + struct eb_vma *ev; > > > + int err; > > > + > > > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > > > + if (!eb->mm_fence) > > > + return -ENOMEM; > > > > Where are the proxy fence functions defined? > > In dma-fence-proxy.c ;) The dma-fence-proxy that Christian NAKed before? Dave. From chris at chris-wilson.co.uk Tue Jun 23 21:15:06 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 22:15:06 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <88f746c6-c6ad-8c19-7797-856ac6bb2f50@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> <159293768060.3967.16328770521784351822@build.alporthouse.com> <88f746c6-c6ad-8c19-7797-856ac6bb2f50@shipmail.org> Message-ID: <159294690652.3967.16801810632630360943@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-23 21:31:38) > > On 6/23/20 8:41 PM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 19:21:28) > >> On 6/23/20 6:36 PM, Chris Wilson wrote: > >>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) > >>>> Hi, Chris, > >>>> > >>>> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>>>> In order to actually handle eviction and what not, we need to process > >>>>> all the objects together under a common lock, reservation_ww_class. As > >>>>> such, do a memory reservation pass after looking up the object/vma, > >>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>>>> flushing and ofc execution]. > >>>>> > >>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>>>> --- > >>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>>>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>>>> > >>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>> index 46fcbdf8161c..8db2e013465f 100644 > >>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>> @@ -53,10 +53,9 @@ struct eb_vma_array { > >>>>> > >>>>> #define __EXEC_OBJECT_HAS_PIN BIT(31) > >>>>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) > >>>>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) > >>>>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) > >>>>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) > >>>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ > >>>>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) > >>>>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) > >>>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ > >>>>> > >>>>> #define __EXEC_HAS_RELOC BIT(31) > >>>>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) > >>>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { > >>>>> struct intel_context *context; /* logical state for the request */ > >>>>> struct i915_gem_context *gem_context; /** caller's context */ > >>>>> > >>>>> + struct dma_fence *mm_fence; > >>>>> + > >>>>> struct i915_request *request; /** our request to build */ > >>>>> struct eb_vma *batch; /** identity of the batch obj/vma */ > >>>>> struct i915_vma *trampoline; /** trampoline used for chaining */ > >>>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) > >>>>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) > >>>>> __i915_vma_unpin(vma); > >>>>> > >>>>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > >>>>> - i915_gem_object_unpin_pages(vma->obj); > >>>>> - > >>>>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > >>>>> - __EXEC_OBJECT_HAS_FENCE | > >>>>> - __EXEC_OBJECT_HAS_PAGES); > >>>>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > >>>>> } > >>>>> > >>>>> static void eb_vma_array_destroy(struct kref *kref) > >>>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > >>>>> list_add_tail(&ev->lock_link, &eb->lock); > >>>>> } > >>>>> > >>>>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, > >>>>> + struct eb_vma *ev, > >>>>> + u64 idx) > >>>>> +{ > >>>>> + struct i915_vma *vma = ev->vma; > >>>>> + int err; > >>>>> + > >>>>> + /* XXX also preallocate PD for vma */ > >>>>> + > >>>>> + err = ____i915_gem_object_get_pages_async(vma->obj); > >>>>> + if (err) > >>>>> + return err; > >>>>> + > >>>>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > >>>>> +} > >>>>> + > >>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>>>> +{ > >>>>> + const u64 idx = eb->context->timeline->fence_context; > >>>>> + struct ww_acquire_ctx acquire; > >>>>> + struct eb_vma *ev; > >>>>> + int err; > >>>>> + > >>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>>>> + if (!eb->mm_fence) > >>>>> + return -ENOMEM; > >>>> Question: eb is local to this thread, right, so eb->mm_fence is not > >>>> considered "published" yet? > >>>> > >>>>> + > >>>>> + ww_acquire_init(&acquire, &reservation_ww_class); > >>>>> + > >>>>> + err = eb_lock_vma(eb, &acquire); > >>>>> + if (err) > >>>>> + goto out; > >>>>> + > >>>>> + ww_acquire_done(&acquire); > >>>>> + > >>>>> + list_for_each_entry(ev, &eb->lock, lock_link) { > >>>>> + struct i915_vma *vma = ev->vma; > >>>>> + > >>>>> + if (err == 0) > >>>>> + err = eb_vma_get_pages(eb, ev, idx); > >>>> I figure this is where you publish the proxy fence? If so, the fence > >>>> signaling critical path starts with this loop, > >>> Hmm, actually at this moment, the fence is still very much internal > >>> being only used as a reference token, > >> I think as long as another thread, running in this driver or another gpu > >> driver can theoretically reference the fence pointer from the > >> reservation object and wait for the fence it's considered published. > > It's not in the reservation object. > > > >> Also the ww_mutexes in this context are really all about grabbing a > >> random set of resources and associate them with a point in a timeline, > >> as the ww_mutexes are released, the fence pointer(s) need to point to > >> published fence(s). > > That's not the purpose of these fences, though. They exist to provide > > reference counting on the backing store, along side the migration fence. > > It's extra detail tacked on the equivalent of bo->moving. > > > > That is not to say that one could build up an async migration chain which > > form a graph back to these, that chain could only be formed once the > > operation itself has been published in the dma_resv though. > > Hmm. So let's say another thread grabs one of the just released > ww_mutexes and wants to schedule a blit from one of the buffers in the > current operation with high priority. How would that thread know how to > order that blit operation w r t the current operation? Why would it order? At this moment in time all that has been reserved is the backing store. Both threads will issue an await on the same fence. As the high priority thread, it will be scheduled first (providing no other ordering is imposed). Neither thread will block the other inside execbuf, and their active reference fence is never published directly (indirect coupling would be after eviction, and if both threads are holding a reference to the current backing store they are before that eviction) so I do not see how even someone else can do a locked wait on their unpublished fences. After that, it is a race as to which thread hits the implicit fencing ww_mutex lock. (That is if they are using implicit write fencing on a shared buffer, a pair of reads to a common buffer are not ordered.) In which case GEM rules apply, first to install their write fence is ahead in the queue. So if the high priority arrives after the low priority, the low priority thread receives the priority boost to high. -Chris From chris at chris-wilson.co.uk Tue Jun 23 21:19:04 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 23 Jun 2020 22:19:04 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> Message-ID: <159294714433.24819.3044662904558073290@build.alporthouse.com> Quoting Dave Airlie (2020-06-23 22:01:24) > On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > > > Hi, Chris! > > > > > > On 6/22/20 11:59 AM, Chris Wilson wrote: > > > > In order to actually handle eviction and what not, we need to process > > > > all the objects together under a common lock, reservation_ww_class. As > > > > such, do a memory reservation pass after looking up the object/vma, > > > > which then feeds into the rest of execbuf [relocation, cmdparsing, > > > > flushing and ofc execution]. > > > > > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > > > --- > > > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > > > > 1 file changed, 70 insertions(+), 21 deletions(-) > > > > > > > Which tree is this against? The series doesn't apply cleanly against > > > drm-tip? > > > > It's continuing on from the scheduler patches, the bug fixes and the > > iris-deferred-fence work. I thought throwing all of those old patches > > into the pile would have been distracting. > > > > > ... > > > > > > > +static int eb_reserve_mm(struct i915_execbuffer *eb) > > > > +{ > > > > + const u64 idx = eb->context->timeline->fence_context; > > > > + struct ww_acquire_ctx acquire; > > > > + struct eb_vma *ev; > > > > + int err; > > > > + > > > > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > > > > + if (!eb->mm_fence) > > > > + return -ENOMEM; > > > > > > Where are the proxy fence functions defined? > > > > In dma-fence-proxy.c ;) > > The dma-fence-proxy that Christian NAKed before? I do not have an email from Christian about dma-fence-proxy in the last 3 years it has been on the list. -Chris From jose.souza at intel.com Tue Jun 23 21:52:34 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Tue, 23 Jun 2020 14:52:34 -0700 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/display/rkl: Implement WA 14011471926 Message-ID: <20200623215235.125665-1-jose.souza@intel.com> This WA fixes failures on DP and HDMI links in PHY B. For the PHY verification step, it is always returning false as this is a temporary workaround so not bothering with minimal drawbacks in programing phy B registers everytime for non-production HW. BSpec: 49291 BSpec: 53273 Cc: Matt Roper <matthew.d.roper at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 33 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++-- 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec62..9eba6e59fff3 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -264,6 +264,10 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, if (!icl_combo_phy_enabled(dev_priv, phy)) return false; + /* WA 14011471926 */ + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B) + return false; + ret = cnl_verify_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { @@ -390,6 +394,35 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); + + /* WA 14011471926 */ + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && + phy == PHY_B) { + u32 grccode; + + intel_de_wait_for_register(dev_priv, + ICL_PORT_COMP_DW3(PHY_A), + FIRST_COMP_DONE, + FIRST_COMP_DONE, 1); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW6(PHY_A)); + grccode = REG_FIELD_GET(ICL_PORT_COMP_DW6_GRCCODE_MASK, val); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW2(phy)); + val &= ~ICL_PORT_COMP_DW2_IREF_RCAL_ORD_MASK; + val |= REG_FIELD_PREP(ICL_PORT_COMP_DW2_IREF_RCAL_ORD_MASK, grccode); + val |= ICL_PORT_COMP_DW2_IREF_RCAL_ORD_END; + intel_de_write(dev_priv, ICL_PORT_COMP_DW2(phy), val); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(PHY_A)); + grccode = REG_FIELD_GET(ICL_PORT_COMP_DW0_GRCCODE_LDO_MASK, val); + + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW6(phy)); + val &= ~ICL_PORT_COMP_DW6_RCOMPCODE_LD_CAP_OV_MASK; + val |= REG_FIELD_PREP(ICL_PORT_COMP_DW6_RCOMPCODE_LD_CAP_OV_MASK, grccode); + val |= ICL_PORT_COMP_DW6_RCOMPCODEOVEN_LDO_SYNC; + intel_de_write(dev_priv, ICL_PORT_COMP_DW6(phy), val); + } } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..dbbe20a38345 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1907,13 +1907,18 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ _ICL_PORT_COMP + 4 * (dw)) -#define CNL_PORT_COMP_DW0 _MMIO(0x162100) -#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) -#define COMP_INIT (1 << 31) +#define CNL_PORT_COMP_DW0 _MMIO(0x162100) +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) +#define COMP_INIT REG_BIT(31) +#define ICL_PORT_COMP_DW0_GRCCODE_LDO_MASK REG_GENMASK(7, 0) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) +#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy)) +#define ICL_PORT_COMP_DW2_IREF_RCAL_ORD_END REG_BIT(7) +#define ICL_PORT_COMP_DW2_IREF_RCAL_ORD_MASK REG_GENMASK(6, 0) + #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) #define PROCESS_INFO_DOT_0 (0 << 26) @@ -1926,6 +1931,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VOLTAGE_INFO_1_05V (2 << 24) #define VOLTAGE_INFO_MASK (3 << 24) #define VOLTAGE_INFO_SHIFT 24 +#define FIRST_COMP_DONE (1 << 22) + +#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy)) +#define ICL_PORT_COMP_DW6_GRCCODE_MASK REG_GENMASK(30, 24) +#define ICL_PORT_COMP_DW6_RCOMPCODEOVEN_LDO_SYNC REG_BIT(23) +#define ICL_PORT_COMP_DW6_RCOMPCODE_LD_CAP_OV_MASK REG_GENMASK(22, 16) #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) #define IREFGEN (1 << 24) -- 2.27.0 From jose.souza at intel.com Tue Jun 23 21:52:35 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Tue, 23 Jun 2020 14:52:35 -0700 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/display: Rename COMP_INIT to CNL_PORT_COMP_DW0_COMP_INIT In-Reply-To: <20200623215235.125665-1-jose.souza@intel.com> References: <20200623215235.125665-1-jose.souza@intel.com> Message-ID: <20200623215235.125665-2-jose.souza@intel.com> Doing this rename to match with other registers and avoid name clash in case other register has the same name. Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_combo_phy.c | 14 ++++++++------ drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 9eba6e59fff3..38496d2e37fc 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -129,7 +129,7 @@ static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) { return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && - (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT); + (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & CNL_PORT_COMP_DW0_COMP_INIT); } static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) @@ -160,7 +160,7 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) cnl_set_procmon_ref_values(dev_priv, PHY_A); val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0); - val |= COMP_INIT; + val |= CNL_PORT_COMP_DW0_COMP_INIT; intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val); val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); @@ -198,13 +198,15 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, enum phy phy) { + const u32 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); + /* The PHY C added by EHL has no PHY_MISC register */ if (!has_phy_misc(dev_priv, phy)) - return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; + return val & CNL_PORT_COMP_DW0_COMP_INIT; else return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && - (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); + (val & CNL_PORT_COMP_DW0_COMP_INIT); } static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) @@ -388,7 +390,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) } val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); - val |= COMP_INIT; + val |= CNL_PORT_COMP_DW0_COMP_INIT; intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); @@ -448,7 +450,7 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) skip_phy_misc: val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); - val &= ~COMP_INIT; + val &= ~CNL_PORT_COMP_DW0_COMP_INIT; intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dbbe20a38345..6938f4d251ae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1909,7 +1909,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CNL_PORT_COMP_DW0 _MMIO(0x162100) #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) -#define COMP_INIT REG_BIT(31) +#define CNL_PORT_COMP_DW0_COMP_INIT REG_BIT(31) #define ICL_PORT_COMP_DW0_GRCCODE_LDO_MASK REG_GENMASK(7, 0) #define CNL_PORT_COMP_DW1 _MMIO(0x162104) -- 2.27.0 From daniel at ffwll.ch Tue Jun 23 22:13:23 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 24 Jun 2020 00:13:23 +0200 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200623161754.GA1140@lca.pw> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> <20200621174205.GB1398@lca.pw> <CAKMK7uFZAFVmceoYvqPovOifGw_Y8Ey-OMy6wioMjwPWhu9dDg@mail.gmail.com> <20200621200103.GV20149@phenom.ffwll.local> <20200623161754.GA1140@lca.pw> Message-ID: <CAKMK7uH90-k12KMHE0pWN6G_aCTr=YNhQsqoaAJC5FHygnf96g@mail.gmail.com> On Tue, Jun 23, 2020 at 6:18 PM Qian Cai <cai at lca.pw> wrote: > > On Sun, Jun 21, 2020 at 10:01:03PM +0200, Daniel Vetter wrote: > > On Sun, Jun 21, 2020 at 08:07:08PM +0200, Daniel Vetter wrote: > > > On Sun, Jun 21, 2020 at 7:42 PM Qian Cai <cai at lca.pw> wrote: > > > > > > > > On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > > > > > fs_reclaim_acquire/release nicely catch recursion issues when > > > > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > > > > to use to keep the excessive caches in check). For mmu notifier > > > > > recursions we do have lockdep annotations since 23b68395c7c7 > > > > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > > > > > > > But these only fire if a path actually results in some pte > > > > > invalidation - for most small allocations that's very rarely the case. > > > > > The other trouble is that pte invalidation can happen any time when > > > > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > > > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > > > > recursion. > > > > > > > > > > I was pondering whether we should just do the general annotation, but > > > > > there's always the risk for false positives. Plus I'm assuming that > > > > > the core fs and io code is a lot better reviewed and tested than > > > > > random mmu notifier code in drivers. Hence why I decide to only > > > > > annotate for that specific case. > > > > > > > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > > > > still need to explicit pull in the mmu notifier map - there's a lot > > > > > more places that do pte invalidation than just direct reclaim, these > > > > > two contexts arent the same. > > > > > > > > > > Note that the mmu notifiers needing their own independent lockdep map > > > > > is also the reason we can't hold them from fs_reclaim_acquire to > > > > > fs_reclaim_release - it would nest with the acquistion in the pte > > > > > invalidation code, causing a lockdep splat. And we can't remove the > > > > > annotations from pte invalidation and all the other places since > > > > > they're called from many other places than page reclaim. Hence we can > > > > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > > > > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > > > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > > > > strictly more powerful. > > > > > > > > > > v2: Review from Thomas Hellstrom: > > > > > - unbotch the fs_reclaim context check, I accidentally inverted it, > > > > > but it didn't blow up because I inverted it immediately > > > > > - fix compiling for !CONFIG_MMU_NOTIFIER > > > > > > > > > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > > > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > > > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > > > > Cc: linux-mm at kvack.org > > > > > Cc: linux-rdma at vger.kernel.org > > > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > > > Cc: Christian K?nig <christian.koenig at amd.com> > > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > > > > > Replying the right patch here... > > > > > > > > Reverting this commit [1] fixed the lockdep warning below while applying > > > > some memory pressure. > > > > > > > > [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") > > > > > > Hm, then I'm confused because > > > - there's not mmut notifier lockdep map in the splat at a.. > > > - the patch is supposed to not change anything for fs_reclaim (but the > > > interim version got that wrong) > > > - looking at the paths it's kmalloc vs kswapd, both places I totally > > > expect fs_reflaim to be used. > > > > > > But you're claiming reverting this prevents the lockdep splat. If > > > that's right, then my reasoning above is broken somewhere. Someone > > > less blind than me having an idea? > > > > > > Aside this is the first email I've typed, until I realized the first > > > report was against the broken patch and that looked like a much more > > > reasonable explanation (but didn't quite match up with the code > > > paths). > > > > Below diff should undo the functional change in my patch. Can you pls test > > whether the lockdep splat is really gone with that? Might need a lot of > > testing and memory pressure to be sure, since all these reclaim paths > > aren't very deterministic. > > No, this patch does not help but reverting the whole patch still fixed > the splat. Ok I tested this. I can't use your script to repro because - I don't have a setup with xfs, and the splat points at an issue in xfs - reproducing lockdep splats in shrinker callbacks is always a bit tricky So instead I made a quick test to validate whether the fs_reclaim annotations work correctly, and nothing has changed: + printk("GFP_NOFS block\n"); + fs_reclaim_acquire(GFP_NOFS); + printk("allocate atomic\n"); + kfree(kmalloc(16, GFP_ATOMIC)); + printk("allocate noio\n"); + kfree(kmalloc(16, GFP_NOIO)); The below two calls to kmalloc are wrong, but the current annotations don't track __GFP_IO and other levels, only __GFP_FS. So no lockdep splats here. + printk("allocate nofs\n"); + kfree(kmalloc(16, GFP_NOFS)); + printk("allocate kernel\n"); + kfree(kmalloc(16, GFP_KERNEL)); + fs_reclaim_release(GFP_NOFS); + + + printk("GFP_KERNEL block\n"); + fs_reclaim_acquire(GFP_KERNEL); + printk("allocate atomic\n"); + kfree(kmalloc(16, GFP_ATOMIC)); + printk("allocate noio\n"); + kfree(kmalloc(16, GFP_NOIO)); + printk("allocate nofs\n"); + kfree(kmalloc(16, GFP_NOFS)); This allocation is buggy, and should splat. This is the case for both with my patch, and with my patch reverted. + printk("allocate kernel\n"); + kfree(kmalloc(16, GFP_KERNEL)); + fs_reclaim_release(GFP_KERNEL); I also looked at the paths in your lockdep splat in xfs, this is simply GFP_KERNEL vs a shrinker reclaim in kswapd. Summary: Everything is working as expected, there's no change in the lockdep annotations. I really think the problem is that either your testcase doesn't hit the issue reliably enough, or that you're not actually testing the same kernels and there's some other changes (xfs most likely, but really it could be anywhere) which is causing this regression. I'm rather convinced now after this test that it's not my stuff. Thanks, Daniel > > > -Daniel > > > > --- > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > > index d807587c9ae6..27ea763c6155 100644 > > --- a/mm/page_alloc.c > > +++ b/mm/page_alloc.c > > @@ -4191,11 +4191,6 @@ void fs_reclaim_acquire(gfp_t gfp_mask) > > if (gfp_mask & __GFP_FS) > > __fs_reclaim_acquire(); > > > > -#ifdef CONFIG_MMU_NOTIFIER > > - lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); > > - lock_map_release(&__mmu_notifier_invalidate_range_start_map); > > -#endif > > - > > } > > } > > EXPORT_SYMBOL_GPL(fs_reclaim_acquire); > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From manasi.d.navare at intel.com Tue Jun 23 22:19:41 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 23 Jun 2020 15:19:41 -0700 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200623205027.GD7681@ideak-desk.fi.intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> <20200623194200.GB22294@intel.com> <20200623195710.GC7681@ideak-desk.fi.intel.com> <20200623203250.GC22294@intel.com> <20200623205027.GD7681@ideak-desk.fi.intel.com> Message-ID: <20200623221940.GD22294@intel.com> On Tue, Jun 23, 2020 at 11:50:27PM +0300, Imre Deak wrote: > On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote: > > still dont quite get it, how is usleep_range (600, 1000) providing a fixed delay? > > Not sure what you mean. udelay is busy looping, while usleep_range > sleeps instead. How to chose between udelay/usleep_range please read > > Documentation/timers/timers-howto.rst > Yes thanks for pointing me to the documentation. I guess I thought you were suggesting to use just usleep_range for both fixed delay and delay with timeout so got confused. > > Now if we split ino 2 functs, one for disable, for that: > > > > if (BXT) > > usleep_range(600, 1000) > > else > > wait_for_us(check if Idle bit set) > > > > so in both functions, for the timeout part we still use the wait_for_us helper right? > > with two functions it would get: > > intel_ddi_wait_for_ddi_buf_active(i915, port) > { > if (GEN <= 9) { > usleep_range(600, 1000); The doumentation however does suggest that we use udelay to avoid the overhead of setting up hrtimers needed for usleep_range in atomic context. But then checkpatch also suggests using usleep_range, why is that? so still not clear in the context of i915 how we decide where to use jiffie based delay through udelay and when to use hrtimers (usleep)? Manasi > return; > } > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600)) > drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port)); > } > > intel_ddi_wait_for_ddi_buf_idle(i915, port) > { > if (BXT) { > udelay(16); > return; > } > > if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600)) > drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port)); > } > > --Imre From daniel.vetter at ffwll.ch Tue Jun 23 22:36:18 2020 From: daniel.vetter at ffwll.ch (Daniel Vetter) Date: Wed, 24 Jun 2020 00:36:18 +0200 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200623223134.GC2005@dread.disaster.area> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> <20200621174205.GB1398@lca.pw> <20200623223134.GC2005@dread.disaster.area> Message-ID: <CAKMK7uGMJPf8p8sa=9N1hibqSTnXn3SfMzWy3+VC-pwkZENfpA@mail.gmail.com> On Wed, Jun 24, 2020 at 12:31 AM Dave Chinner <david at fromorbit.com> wrote: > > On Sun, Jun 21, 2020 at 01:42:05PM -0400, Qian Cai wrote: > > On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > > > fs_reclaim_acquire/release nicely catch recursion issues when > > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > > to use to keep the excessive caches in check). For mmu notifier > > > recursions we do have lockdep annotations since 23b68395c7c7 > > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > > > But these only fire if a path actually results in some pte > > > invalidation - for most small allocations that's very rarely the case. > > > The other trouble is that pte invalidation can happen any time when > > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > > recursion. > > > > > > I was pondering whether we should just do the general annotation, but > > > there's always the risk for false positives. Plus I'm assuming that > > > the core fs and io code is a lot better reviewed and tested than > > > random mmu notifier code in drivers. Hence why I decide to only > > > annotate for that specific case. > > > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > > still need to explicit pull in the mmu notifier map - there's a lot > > > more places that do pte invalidation than just direct reclaim, these > > > two contexts arent the same. > > > > > > Note that the mmu notifiers needing their own independent lockdep map > > > is also the reason we can't hold them from fs_reclaim_acquire to > > > fs_reclaim_release - it would nest with the acquistion in the pte > > > invalidation code, causing a lockdep splat. And we can't remove the > > > annotations from pte invalidation and all the other places since > > > they're called from many other places than page reclaim. Hence we can > > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > > strictly more powerful. > > > > > > v2: Review from Thomas Hellstrom: > > > - unbotch the fs_reclaim context check, I accidentally inverted it, > > > but it didn't blow up because I inverted it immediately > > > - fix compiling for !CONFIG_MMU_NOTIFIER > > > > > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > > > Cc: Andrew Morton <akpm at linux-foundation.org> > > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > > Cc: linux-mm at kvack.org > > > Cc: linux-rdma at vger.kernel.org > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > Cc: Christian K?nig <christian.koenig at amd.com> > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > Replying the right patch here... > > > > Reverting this commit [1] fixed the lockdep warning below while applying > > some memory pressure. > > > > [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") > > > > [ 190.455003][ T369] WARNING: possible circular locking dependency detected > > [ 190.487291][ T369] 5.8.0-rc1-next-20200621 #1 Not tainted > > [ 190.512363][ T369] ------------------------------------------------------ > > [ 190.543354][ T369] kswapd3/369 is trying to acquire lock: > > [ 190.568523][ T369] ffff889fcf694528 (&xfs_nondir_ilock_class){++++}-{3:3}, at: xfs_reclaim_inode+0xdf/0x860 > > spin_lock at include/linux/spinlock.h:353 > > (inlined by) xfs_iflags_test_and_set at fs/xfs/xfs_inode.h:166 > > (inlined by) xfs_iflock_nowait at fs/xfs/xfs_inode.h:249 > > (inlined by) xfs_reclaim_inode at fs/xfs/xfs_icache.c:1127 > > [ 190.614359][ T369] > > [ 190.614359][ T369] but task is already holding lock: > > [ 190.647763][ T369] ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > > __fs_reclaim_acquire at mm/page_alloc.c:4200 > > [ 190.687845][ T369] > > [ 190.687845][ T369] which lock already depends on the new lock. > > [ 190.687845][ T369] > > [ 190.734890][ T369] > > [ 190.734890][ T369] the existing dependency chain (in reverse order) is: > > [ 190.775991][ T369] > > [ 190.775991][ T369] -> #1 (fs_reclaim){+.+.}-{0:0}: > > [ 190.808150][ T369] fs_reclaim_acquire+0x77/0x80 > > [ 190.832152][ T369] slab_pre_alloc_hook.constprop.52+0x20/0x120 > > slab_pre_alloc_hook at mm/slab.h:507 > > [ 190.862173][ T369] kmem_cache_alloc+0x43/0x2a0 > > [ 190.885602][ T369] kmem_zone_alloc+0x113/0x3ef > > kmem_zone_alloc at fs/xfs/kmem.c:129 > > [ 190.908702][ T369] xfs_inode_item_init+0x1d/0xa0 > > xfs_inode_item_init at fs/xfs/xfs_inode_item.c:639 > > [ 190.934461][ T369] xfs_trans_ijoin+0x96/0x100 > > xfs_trans_ijoin at fs/xfs/libxfs/xfs_trans_inode.c:34 > > [ 190.961530][ T369] xfs_setattr_nonsize+0x1a6/0xcd0 > > OK, this patch has royally screwed something up if this path thinks > it can enter memory reclaim. This path is inside a transaction, so > it is running under PF_MEMALLOC_NOFS context, so should *never* > enter memory reclaim. > > I'd suggest that whatever mods were made to fs_reclaim_acquire by > this patch broke it's basic functionality.... > > > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > > > index 13cc653122b7..7536faaaa0fd 100644 > > > --- a/mm/page_alloc.c > > > +++ b/mm/page_alloc.c > > > @@ -57,6 +57,7 @@ > > > #include <trace/events/oom.h> > > > #include <linux/prefetch.h> > > > #include <linux/mm_inline.h> > > > +#include <linux/mmu_notifier.h> > > > #include <linux/migrate.h> > > > #include <linux/hugetlb.h> > > > #include <linux/sched/rt.h> > > > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > > > static struct lockdep_map __fs_reclaim_map = > > > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > > > > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > > > +static bool __need_reclaim(gfp_t gfp_mask) > > > { > > > gfp_mask = current_gfp_context(gfp_mask); > > This is applies the per-task memory allocation context flags to the > mask that is checked here. > > > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > > > if (current->flags & PF_MEMALLOC) > > > return false; > > > > > > - /* We're only interested __GFP_FS allocations for now */ > > > - if (!(gfp_mask & __GFP_FS)) > > > - return false; > > > - > > > if (gfp_mask & __GFP_NOLOCKDEP) > > > return false; > > > > > > @@ -4158,15 +4155,25 @@ void __fs_reclaim_release(void) > > > > > > void fs_reclaim_acquire(gfp_t gfp_mask) > > > { > > > - if (__need_fs_reclaim(gfp_mask)) > > > - __fs_reclaim_acquire(); > > > + if (__need_reclaim(gfp_mask)) { > > > + if (gfp_mask & __GFP_FS) > > > + __fs_reclaim_acquire(); > > .... and they have not been applied in this path. There's your > breakage. > > For future reference, please post anything that changes NOFS > allocation contexts or behaviours to linux-fsdevel, as filesystem > developers need to know about proposed changes to infrastructure > that is critical to the correct functioning of filesystems... Uh crap I totally missed that. Apologies for wasting everyone's time here. Andrew, please drop for now, I respin this thing. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From imre.deak at intel.com Tue Jun 23 22:50:06 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 24 Jun 2020 01:50:06 +0300 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200623221940.GD22294@intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> <20200623194200.GB22294@intel.com> <20200623195710.GC7681@ideak-desk.fi.intel.com> <20200623203250.GC22294@intel.com> <20200623205027.GD7681@ideak-desk.fi.intel.com> <20200623221940.GD22294@intel.com> Message-ID: <20200623223549.GE7681@ideak-desk.fi.intel.com> On Tue, Jun 23, 2020 at 03:19:41PM -0700, Manasi Navare wrote: > On Tue, Jun 23, 2020 at 11:50:27PM +0300, Imre Deak wrote: > > On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote: > > > > with two functions it would get: > > > > intel_ddi_wait_for_ddi_buf_active(i915, port) > > { > > if (GEN <= 9) { > > usleep_range(600, 1000); > > The doumentation however does suggest that we use udelay to avoid the overhead > of setting up hrtimers needed for usleep_range in atomic context. The relevant part here is "NON-ATOMIC CONTEXT": SLEEPING FOR "A FEW" USECS ( < ~10us? ): * Use udelay - Why not usleep? On slower systems, (embedded, OR perhaps a speed- stepped PC!) the overhead of setting up the hrtimers for usleep *may* not be worth it. Such an evaluation will obviously depend on your specific situation, but it is something to be aware of. SLEEPING FOR ~USECS OR SMALL MSECS ( 10us - 20ms): * Use usleep_range So, can use udelay() for 16usec and should use usleep_range() for 600 usec. > But then checkpatch also suggests using usleep_range, why is that? > > so still not clear in the context of i915 how we decide where to use jiffie based > delay through udelay and when to use hrtimers (usleep)? The above document should be followed. > > Manasi > > > > return; > > } > > > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600)) > > drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port)); > > } > > > > intel_ddi_wait_for_ddi_buf_idle(i915, port) > > { > > if (BXT) { > > udelay(16); > > return; > > } > > > > if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600)) > > drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port)); > > } > > > > --Imre From manasi.d.navare at intel.com Tue Jun 23 22:59:03 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 23 Jun 2020 15:59:03 -0700 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200623223549.GE7681@ideak-desk.fi.intel.com> References: <20200618000124.29036-1-manasi.d.navare@intel.com> <20200622154921.GA25163@ideak-desk.fi.intel.com> <20200623194200.GB22294@intel.com> <20200623195710.GC7681@ideak-desk.fi.intel.com> <20200623203250.GC22294@intel.com> <20200623205027.GD7681@ideak-desk.fi.intel.com> <20200623221940.GD22294@intel.com> <20200623223549.GE7681@ideak-desk.fi.intel.com> Message-ID: <20200623225903.GE22294@intel.com> On Wed, Jun 24, 2020 at 01:50:06AM +0300, Imre Deak wrote: > On Tue, Jun 23, 2020 at 03:19:41PM -0700, Manasi Navare wrote: > > On Tue, Jun 23, 2020 at 11:50:27PM +0300, Imre Deak wrote: > > > On Tue, Jun 23, 2020 at 01:32:50PM -0700, Manasi Navare wrote: > > > > > > with two functions it would get: > > > > > > intel_ddi_wait_for_ddi_buf_active(i915, port) > > > { > > > if (GEN <= 9) { > > > usleep_range(600, 1000); > > > > The doumentation however does suggest that we use udelay to avoid the overhead > > of setting up hrtimers needed for usleep_range in atomic context. > > The relevant part here is "NON-ATOMIC CONTEXT": > > SLEEPING FOR "A FEW" USECS ( < ~10us? ): > * Use udelay > > - Why not usleep? > On slower systems, (embedded, OR perhaps a speed- > stepped PC!) the overhead of setting up the hrtimers > for usleep *may* not be worth it. Such an evaluation > will obviously depend on your specific situation, but > it is something to be aware of. > > SLEEPING FOR ~USECS OR SMALL MSECS ( 10us - 20ms): > * Use usleep_range > > So, can use udelay() for 16usec and should use usleep_range() for 600 usec. Got it thanks will update and send the next rev Regards Manasi > > > But then checkpatch also suggests using usleep_range, why is that? > > > > so still not clear in the context of i915 how we decide where to use jiffie based > > delay through udelay and when to use hrtimers (usleep)? > > The above document should be followed. > > > > > Manasi > > > > > > > return; > > > } > > > > > > if (wait_for_us(!(read(BUF_CTL) & IS_IDLE), 600)) > > > drm_err("Port %c: Timeout waiting for DDI BUF to get active\n", port)); > > > } > > > > > > intel_ddi_wait_for_ddi_buf_idle(i915, port) > > > { > > > if (BXT) { > > > udelay(16); > > > return; > > > } > > > > > > if (wait_for_us(read(BUF_CTL) & IS_IDLE, 600)) > > > drm_err("Port %c: Timeout waiting for DDI BUF to get idle\n", port)); > > > } > > > > > > --Imre From jose.souza at intel.com Tue Jun 23 22:59:34 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Tue, 23 Jun 2020 15:59:34 -0700 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/display: Implement new combo phy initialization step In-Reply-To: <20200623215235.125665-1-jose.souza@intel.com> References: <20200623215235.125665-1-jose.souza@intel.com> Message-ID: <20200623225934.147326-1-jose.souza@intel.com> This is new step that was recently added to the combo phy initialization. BSpec: 49291 Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 25 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 ++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 38496d2e37fc..585504ad3e65 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -270,6 +270,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B) return false; + if (INTEL_GEN(dev_priv) >= 12) { + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_GRP(phy), + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); + + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_GRP(phy), + DCC_MODE_SELECT_MASK, + DCC_MODE_SELECT_CONTINUOSLY); + } + ret = cnl_verify_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { @@ -381,6 +393,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); skip_phy_misc: + if (INTEL_GEN(dev_priv) >= 12) { + val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_GRP(phy)); + val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK; + val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL; + val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2; + intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); + + val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_GRP(phy)); + val &= ~DCC_MODE_SELECT_MASK; + val |= DCC_MODE_SELECT_CONTINUOSLY; + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); + } + cnl_set_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6938f4d251ae..a882e6329f1b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1985,6 +1985,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) +#define DCC_MODE_SELECT_MASK (0x3 << 20) +#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) #define COMMON_KEEPER_EN (1 << 26) #define LATENCY_OPTIM_MASK (0x3 << 2) #define LATENCY_OPTIM_VAL(x) ((x) << 2) @@ -2083,6 +2085,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) +#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) + #define _ICL_DPHY_CHKN_REG 0x194 #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) -- 2.27.0 From david at fromorbit.com Tue Jun 23 22:31:35 2020 From: david at fromorbit.com (Dave Chinner) Date: Wed, 24 Jun 2020 08:31:35 +1000 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <20200621174205.GB1398@lca.pw> References: <20200604081224.863494-2-daniel.vetter@ffwll.ch> <20200610194101.1668038-1-daniel.vetter@ffwll.ch> <20200621174205.GB1398@lca.pw> Message-ID: <20200623223134.GC2005@dread.disaster.area> On Sun, Jun 21, 2020 at 01:42:05PM -0400, Qian Cai wrote: > On Wed, Jun 10, 2020 at 09:41:01PM +0200, Daniel Vetter wrote: > > fs_reclaim_acquire/release nicely catch recursion issues when > > allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend > > to use to keep the excessive caches in check). For mmu notifier > > recursions we do have lockdep annotations since 23b68395c7c7 > > ("mm/mmu_notifiers: add a lockdep map for invalidate_range_start/end"). > > > > But these only fire if a path actually results in some pte > > invalidation - for most small allocations that's very rarely the case. > > The other trouble is that pte invalidation can happen any time when > > __GFP_RECLAIM is set. Which means only really GFP_ATOMIC is a safe > > choice, GFP_NOIO isn't good enough to avoid potential mmu notifier > > recursion. > > > > I was pondering whether we should just do the general annotation, but > > there's always the risk for false positives. Plus I'm assuming that > > the core fs and io code is a lot better reviewed and tested than > > random mmu notifier code in drivers. Hence why I decide to only > > annotate for that specific case. > > > > Furthermore even if we'd create a lockdep map for direct reclaim, we'd > > still need to explicit pull in the mmu notifier map - there's a lot > > more places that do pte invalidation than just direct reclaim, these > > two contexts arent the same. > > > > Note that the mmu notifiers needing their own independent lockdep map > > is also the reason we can't hold them from fs_reclaim_acquire to > > fs_reclaim_release - it would nest with the acquistion in the pte > > invalidation code, causing a lockdep splat. And we can't remove the > > annotations from pte invalidation and all the other places since > > they're called from many other places than page reclaim. Hence we can > > only do the equivalent of might_lock, but on the raw lockdep map. > > > > With this we can also remove the lockdep priming added in 66204f1d2d1b > > ("mm/mmu_notifiers: prime lockdep") since the new annotations are > > strictly more powerful. > > > > v2: Review from Thomas Hellstrom: > > - unbotch the fs_reclaim context check, I accidentally inverted it, > > but it didn't blow up because I inverted it immediately > > - fix compiling for !CONFIG_MMU_NOTIFIER > > > > Cc: Thomas Hellstr?m (Intel) <thomas_os at shipmail.org> > > Cc: Andrew Morton <akpm at linux-foundation.org> > > Cc: Jason Gunthorpe <jgg at mellanox.com> > > Cc: linux-mm at kvack.org > > Cc: linux-rdma at vger.kernel.org > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > Cc: Christian K?nig <christian.koenig at amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Replying the right patch here... > > Reverting this commit [1] fixed the lockdep warning below while applying > some memory pressure. > > [1] linux-next cbf7c9d86d75 ("mm: track mmu notifiers in fs_reclaim_acquire/release") > > [ 190.455003][ T369] WARNING: possible circular locking dependency detected > [ 190.487291][ T369] 5.8.0-rc1-next-20200621 #1 Not tainted > [ 190.512363][ T369] ------------------------------------------------------ > [ 190.543354][ T369] kswapd3/369 is trying to acquire lock: > [ 190.568523][ T369] ffff889fcf694528 (&xfs_nondir_ilock_class){++++}-{3:3}, at: xfs_reclaim_inode+0xdf/0x860 > spin_lock at include/linux/spinlock.h:353 > (inlined by) xfs_iflags_test_and_set at fs/xfs/xfs_inode.h:166 > (inlined by) xfs_iflock_nowait at fs/xfs/xfs_inode.h:249 > (inlined by) xfs_reclaim_inode at fs/xfs/xfs_icache.c:1127 > [ 190.614359][ T369] > [ 190.614359][ T369] but task is already holding lock: > [ 190.647763][ T369] ffffffffb50ced00 (fs_reclaim){+.+.}-{0:0}, at: __fs_reclaim_acquire+0x0/0x30 > __fs_reclaim_acquire at mm/page_alloc.c:4200 > [ 190.687845][ T369] > [ 190.687845][ T369] which lock already depends on the new lock. > [ 190.687845][ T369] > [ 190.734890][ T369] > [ 190.734890][ T369] the existing dependency chain (in reverse order) is: > [ 190.775991][ T369] > [ 190.775991][ T369] -> #1 (fs_reclaim){+.+.}-{0:0}: > [ 190.808150][ T369] fs_reclaim_acquire+0x77/0x80 > [ 190.832152][ T369] slab_pre_alloc_hook.constprop.52+0x20/0x120 > slab_pre_alloc_hook at mm/slab.h:507 > [ 190.862173][ T369] kmem_cache_alloc+0x43/0x2a0 > [ 190.885602][ T369] kmem_zone_alloc+0x113/0x3ef > kmem_zone_alloc at fs/xfs/kmem.c:129 > [ 190.908702][ T369] xfs_inode_item_init+0x1d/0xa0 > xfs_inode_item_init at fs/xfs/xfs_inode_item.c:639 > [ 190.934461][ T369] xfs_trans_ijoin+0x96/0x100 > xfs_trans_ijoin at fs/xfs/libxfs/xfs_trans_inode.c:34 > [ 190.961530][ T369] xfs_setattr_nonsize+0x1a6/0xcd0 OK, this patch has royally screwed something up if this path thinks it can enter memory reclaim. This path is inside a transaction, so it is running under PF_MEMALLOC_NOFS context, so should *never* enter memory reclaim. I'd suggest that whatever mods were made to fs_reclaim_acquire by this patch broke it's basic functionality.... > > diff --git a/mm/page_alloc.c b/mm/page_alloc.c > > index 13cc653122b7..7536faaaa0fd 100644 > > --- a/mm/page_alloc.c > > +++ b/mm/page_alloc.c > > @@ -57,6 +57,7 @@ > > #include <trace/events/oom.h> > > #include <linux/prefetch.h> > > #include <linux/mm_inline.h> > > +#include <linux/mmu_notifier.h> > > #include <linux/migrate.h> > > #include <linux/hugetlb.h> > > #include <linux/sched/rt.h> > > @@ -4124,7 +4125,7 @@ should_compact_retry(struct alloc_context *ac, unsigned int order, int alloc_fla > > static struct lockdep_map __fs_reclaim_map = > > STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); > > > > -static bool __need_fs_reclaim(gfp_t gfp_mask) > > +static bool __need_reclaim(gfp_t gfp_mask) > > { > > gfp_mask = current_gfp_context(gfp_mask); This is applies the per-task memory allocation context flags to the mask that is checked here. > > @@ -4136,10 +4137,6 @@ static bool __need_fs_reclaim(gfp_t gfp_mask) > > if (current->flags & PF_MEMALLOC) > > return false; > > > > - /* We're only interested __GFP_FS allocations for now */ > > - if (!(gfp_mask & __GFP_FS)) > > - return false; > > - > > if (gfp_mask & __GFP_NOLOCKDEP) > > return false; > > > > @@ -4158,15 +4155,25 @@ void __fs_reclaim_release(void) > > > > void fs_reclaim_acquire(gfp_t gfp_mask) > > { > > - if (__need_fs_reclaim(gfp_mask)) > > - __fs_reclaim_acquire(); > > + if (__need_reclaim(gfp_mask)) { > > + if (gfp_mask & __GFP_FS) > > + __fs_reclaim_acquire(); .... and they have not been applied in this path. There's your breakage. For future reference, please post anything that changes NOFS allocation contexts or behaviours to linux-fsdevel, as filesystem developers need to know about proposed changes to infrastructure that is critical to the correct functioning of filesystems... Cheers, Dave. -- Dave Chinner david at fromorbit.com From lucas.de.marchi at gmail.com Tue Jun 23 23:03:36 2020 From: lucas.de.marchi at gmail.com (Lucas De Marchi) Date: Tue, 23 Jun 2020 16:03:36 -0700 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/display: Implement new combo phy initialization step In-Reply-To: <20200623225934.147326-1-jose.souza@intel.com> References: <20200623215235.125665-1-jose.souza@intel.com> <20200623225934.147326-1-jose.souza@intel.com> Message-ID: <CAKi4VALWM-QZDDv-c54jp2zv3V-cDwRhALr+bDYsSQC4oR+SVw@mail.gmail.com> On Tue, Jun 23, 2020 at 3:58 PM Jos? Roberto de Souza <jose.souza at intel.com> wrote: > > This is new step that was recently added to the combo phy > initialization. > > BSpec: 49291 > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > .../gpu/drm/i915/display/intel_combo_phy.c | 25 +++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 7 ++++++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c > index 38496d2e37fc..585504ad3e65 100644 > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c > @@ -270,6 +270,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, > if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B) > return false; > > + if (INTEL_GEN(dev_priv) >= 12) { > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_GRP(phy), > + ICL_PORT_TX_DW8_ODCC_CLK_SEL | > + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, > + ICL_PORT_TX_DW8_ODCC_CLK_SEL | > + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); > + > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_GRP(phy), > + DCC_MODE_SELECT_MASK, > + DCC_MODE_SELECT_CONTINUOSLY); > + } > + > ret = cnl_verify_procmon_ref_values(dev_priv, phy); > > if (phy_is_master(dev_priv, phy)) { > @@ -381,6 +393,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); > > skip_phy_misc: > + if (INTEL_GEN(dev_priv) >= 12) { > + val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_GRP(phy)); > + val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK; > + val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL; > + val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2; > + intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); > + > + val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_GRP(phy)); > + val &= ~DCC_MODE_SELECT_MASK; > + val |= DCC_MODE_SELECT_CONTINUOSLY; > + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); > + } any reason not to use intel_de_rmw() in these 2? Lucas De Marchi > + > cnl_set_procmon_ref_values(dev_priv, phy); > > if (phy_is_master(dev_priv, phy)) { > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 6938f4d251ae..a882e6329f1b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1985,6 +1985,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) > #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) > #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) > +#define DCC_MODE_SELECT_MASK (0x3 << 20) > +#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) > #define COMMON_KEEPER_EN (1 << 26) > #define LATENCY_OPTIM_MASK (0x3 << 2) > #define LATENCY_OPTIM_VAL(x) ((x) << 2) > @@ -2083,6 +2085,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define N_SCALAR(x) ((x) << 24) > #define N_SCALAR_MASK (0x7F << 24) > > +#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) > +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) > +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) > +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) > + > #define _ICL_DPHY_CHKN_REG 0x194 > #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) > #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) > -- > 2.27.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi From jose.souza at intel.com Tue Jun 23 23:09:52 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 23 Jun 2020 23:09:52 +0000 Subject: [Intel-gfx] [PATCH 3/3] drm/i915/display: Implement new combo phy initialization step In-Reply-To: <CAKi4VALWM-QZDDv-c54jp2zv3V-cDwRhALr+bDYsSQC4oR+SVw@mail.gmail.com> References: <20200623215235.125665-1-jose.souza@intel.com> <20200623225934.147326-1-jose.souza@intel.com> <CAKi4VALWM-QZDDv-c54jp2zv3V-cDwRhALr+bDYsSQC4oR+SVw@mail.gmail.com> Message-ID: <30c7de10069c986480d80ae79b853fe05685266e.camel@intel.com> On Tue, 2020-06-23 at 16:03 -0700, Lucas De Marchi wrote: > On Tue, Jun 23, 2020 at 3:58 PM Jos? Roberto de Souza > <jose.souza at intel.com> wrote: > > This is new step that was recently added to the combo phy > > initialization. > > > > BSpec: 49291 > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > --- > > .../gpu/drm/i915/display/intel_combo_phy.c | 25 +++++++++++++++++++ > > drivers/gpu/drm/i915/i915_reg.h | 7 ++++++ > > 2 files changed, 32 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c > > index 38496d2e37fc..585504ad3e65 100644 > > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c > > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c > > @@ -270,6 +270,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, > > if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && phy == PHY_B) > > return false; > > > > + if (INTEL_GEN(dev_priv) >= 12) { > > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_GRP(phy), > > + ICL_PORT_TX_DW8_ODCC_CLK_SEL | > > + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, > > + ICL_PORT_TX_DW8_ODCC_CLK_SEL | > > + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); > > + > > + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_GRP(phy), > > + DCC_MODE_SELECT_MASK, > > + DCC_MODE_SELECT_CONTINUOSLY); > > + } > > + > > ret = cnl_verify_procmon_ref_values(dev_priv, phy); > > > > if (phy_is_master(dev_priv, phy)) { > > @@ -381,6 +393,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > > intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); > > > > skip_phy_misc: > > + if (INTEL_GEN(dev_priv) >= 12) { > > + val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_GRP(phy)); > > + val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK; > > + val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL; > > + val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2; > > + intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); > > + > > + val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_GRP(phy)); > > + val &= ~DCC_MODE_SELECT_MASK; > > + val |= DCC_MODE_SELECT_CONTINUOSLY; > > + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); > > + } > > any reason not to use intel_de_rmw() in these 2? No reason at all, will change to intel_de_rmw().Thanks > > Lucas De Marchi > > + > > cnl_set_procmon_ref_values(dev_priv, phy); > > > > if (phy_is_master(dev_priv, phy)) { > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 6938f4d251ae..a882e6329f1b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1985,6 +1985,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) > > #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) > > #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) > > +#define DCC_MODE_SELECT_MASK (0x3 << 20) > > +#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) > > #define COMMON_KEEPER_EN (1 << 26) > > #define LATENCY_OPTIM_MASK (0x3 << 2) > > #define LATENCY_OPTIM_VAL(x) ((x) << 2) > > @@ -2083,6 +2085,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define N_SCALAR(x) ((x) << 24) > > #define N_SCALAR_MASK (0x7F << 24) > > > > +#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) > > +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) > > +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) > > +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) > > + > > #define _ICL_DPHY_CHKN_REG 0x194 > > #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) > > #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) > > -- > > 2.27.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > From jose.souza at intel.com Tue Jun 23 23:40:10 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 23 Jun 2020 23:40:10 +0000 Subject: [Intel-gfx] [PATCH v2 01/32] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout In-Reply-To: <20200618004240.16263-2-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-2-lucas.demarchi@intel.com> Message-ID: <07ec239b0cb3fe08ac97eca5566d4880ea3ad373.camel@intel.com> On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote: > From: Matt Roper <matthew.d.roper at intel.com> > > RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register. > > v2: > - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0 > - Checkpatch style fixes > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Bspec: 50287 > Cc: Aditya Swarup <aditya.swarup at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++--- > drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++--- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 3 files changed, 33 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index ca7bb2294d2b6..8790f221dc77c 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp) > static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, > enum phy phy) > { > - if (intel_phy_is_combo(dev_priv, phy)) { > + if (IS_ROCKETLAKE(dev_priv)) { > + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > + } else if (intel_phy_is_combo(dev_priv, phy)) { > return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); > } else if (intel_phy_is_tc(dev_priv, phy)) { > enum tc_port tc_port = intel_port_to_tc(dev_priv, > @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, > (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); > > if (intel_phy_is_combo(dev_priv, phy)) { > + u32 mask, sel; > + > + if (IS_ROCKETLAKE(dev_priv)) { > + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); > + } else { > + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); > + } > + > /* > * Even though this register references DDIs, note that we > * want to pass the PHY rather than the port (DDI). For > @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, > * Clock Select chooses the PLL for both DDIA and DDID and > * drives port A in all cases." > */ > - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); > + val &= ~mask; > + val |= sel; > intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); > intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 7457813ef2733..6c2bb3354b869 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, > u32 temp; > > if (intel_phy_is_combo(dev_priv, phy)) { > - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & > - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); > + u32 mask, shift; > + > + if (IS_ROCKETLAKE(dev_priv)) { > + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); > + } else { > + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); > + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); > + } > + > + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask; > + id = temp >> shift; > port_dpll_id = ICL_PORT_DPLL_DEFAULT; > } else if (intel_phy_is_tc(dev_priv, phy)) { > u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f09120cac89aa..45bda5819abd0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -10195,12 +10195,18 @@ enum skl_power_gate { > > #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) > #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) > +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) > #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ > (tc_port) + 12 : \ > (tc_port) - PORT_TC4 + 21)) > #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) > #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) > #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) > +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) > +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ > + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) > +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ > + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) > > /* CNL PLL */ > #define DPLL0_ENABLE 0x46010 From jose.souza at intel.com Tue Jun 23 23:56:45 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 23 Jun 2020 23:56:45 +0000 Subject: [Intel-gfx] [PATCH v2 03/32] drm/i915/rkl: Handle HTI In-Reply-To: <20200618004240.16263-4-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-4-lucas.demarchi@intel.com> Message-ID: <d243b8f2c8191da32cfa1d4d03d2629e5f5698c0.camel@intel.com> On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote: > From: Matt Roper <matthew.d.roper at intel.com> > > If HTI (also sometimes called HDPORT) is enabled at startup, it may be > using some of the PHYs and DPLLs making them unavailable for general > usage. Let's read out the HDPORT_STATE register and avoid making use of > resources that HTI is already using. > > v2: > - Fix minor checkpatch warnings > > Bspec: 49189 > Bspec: 53707 > Cc: Lucas De Marchi <lucas.demarchi at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 30 ++++++++++++++++--- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 21 +++++++++++++ > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + > drivers/gpu/drm/i915/i915_drv.h | 3 ++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++ > 5 files changed, 57 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 6c2bb3354b869..f16512eddc587 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -46,6 +46,7 @@ > #include "display/intel_ddi.h" > #include "display/intel_dp.h" > #include "display/intel_dp_mst.h" > +#include "display/intel_dpll_mgr.h" > #include "display/intel_dsi.h" > #include "display/intel_dvo.h" > #include "display/intel_gmbus.h" > @@ -16814,6 +16815,13 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) > intel_pps_unlock_regs_wa(dev_priv); > } > > +static bool hti_uses_phy(u32 hdport_state, enum phy phy) > +{ > + return hdport_state & HDPORT_ENABLED && > + (hdport_state & HDPORT_PHY_USED_DP(phy) || > + hdport_state & HDPORT_PHY_USED_HDMI(phy)); > +} > + > static void intel_setup_outputs(struct drm_i915_private *dev_priv) > { > struct intel_encoder *encoder; > @@ -16825,10 +16833,22 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > return; > > if (IS_ROCKETLAKE(dev_priv)) { > - intel_ddi_init(dev_priv, PORT_A); > - intel_ddi_init(dev_priv, PORT_B); > - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > + /* > + * If HTI (aka HDPORT) is enabled at boot, it may have taken > + * over some of the PHYs and made them unavailable to the > + * driver. In that case we should skip initializing the > + * corresponding outputs. > + */ > + u32 hdport_state = intel_de_read(dev_priv, HDPORT_STATE); > + > + if (!hti_uses_phy(hdport_state, PHY_A)) > + intel_ddi_init(dev_priv, PORT_A); > + if (!hti_uses_phy(hdport_state, PHY_B)) > + intel_ddi_init(dev_priv, PORT_B); > + if (!hti_uses_phy(hdport_state, PHY_C)) > + intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ > + if (!hti_uses_phy(hdport_state, PHY_D)) > + intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ > } else if (INTEL_GEN(dev_priv) >= 12) { > intel_ddi_init(dev_priv, PORT_A); > intel_ddi_init(dev_priv, PORT_B); > @@ -18376,6 +18396,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) > > intel_dpll_readout_hw_state(dev_priv); > > + dev_priv->hti_pll_mask = intel_get_hti_plls(dev_priv); Why not do this in intel_shared_dpll_init()? > + > for_each_intel_encoder(dev, encoder) { > pipe = 0; > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index b5f4d4cef682b..6f59f9ec453bf 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -265,6 +265,24 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) > mutex_unlock(&dev_priv->dpll.lock); > } > > +/* > + * HTI (aka HDPORT) may be using some of the platform's PLL's, making them > + * unavailable for use. > + */ > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv) No need to export this function, check above. > +{ > + u32 hdport_state; > + > + if (!IS_ROCKETLAKE(dev_priv)) > + return 0; > + > + hdport_state = intel_de_read(dev_priv, HDPORT_STATE); > + if (!(hdport_state & HDPORT_ENABLED)) > + return 0; > + > + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, hdport_state); > +} > + > static struct intel_shared_dpll * > intel_find_shared_dpll(struct intel_atomic_state *state, > const struct intel_crtc *crtc, > @@ -280,6 +298,9 @@ intel_find_shared_dpll(struct intel_atomic_state *state, > > drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); > > + /* Eliminate DPLLs from consideration if reserved by HTI */ > + dpll_mask &= ~dev_priv->hti_pll_mask; This should be done in icl_get_combo_phy_dpll() for RKL only. > + > for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { > pll = &dev_priv->dpll.shared_dplls[i]; > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > index 49367847bfb55..edcc43f4670ff 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h > @@ -390,6 +390,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state); > void intel_shared_dpll_init(struct drm_device *dev); > void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); > void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); > +u32 intel_get_hti_plls(struct drm_i915_private *dev_priv); > > void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, > const struct intel_dpll_hw_state *hw_state); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 5649f8e502fef..b836032fa0deb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1037,6 +1037,9 @@ struct drm_i915_private { > > struct intel_l3_parity l3_parity; > > + /* Mask of PLLs reserved for use by HTI and unavailable to driver. */ > + u32 hti_pll_mask; > + > /* > * edram size in MB. > * Cannot be determined by PCIID. You must always read a register. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 34f8698ac3aa6..34b2ec04ccd86 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2908,6 +2908,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) > #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) > > +#define HDPORT_STATE _MMIO(0x45050) > +#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) > +#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) > +#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) > +#define HDPORT_ENABLED REG_BIT(0) > + > /* Make render/texture TLB fetches lower priorty than associated data > * fetches. This is not turned on by default > */ From jose.souza at intel.com Wed Jun 24 00:07:53 2020 From: jose.souza at intel.com (Souza, Jose) Date: Wed, 24 Jun 2020 00:07:53 +0000 Subject: [Intel-gfx] [PATCH v2 05/32] drm/i915/rkl: Add Wa_14011224835 for PHY B initialization In-Reply-To: <20200618004240.16263-6-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-6-lucas.demarchi@intel.com> Message-ID: <5af82ae01a757747c44ebd3a913a580d4e714083.camel@intel.com> On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote: > From: Matt Roper <matthew.d.roper at intel.com> > > After doing normal PHY-B initialization on Rocket Lake, we need to > manually copy some additional PHY-A register values into PHY-B > registers. Damn, just sent this, did a search using 14011471926 and did not found it anywhere, anyways lets go with this one, please also refers to 14011471926. https://patchwork.freedesktop.org/patch/372713/?series=78761&rev=1 > > Note that the bspec's combo phy page doesn't specify that this > workaround is restricted to specific platform steppings (and doesn't > even do a very good job of specifying that RKL is the only platform this > is needed on), but the RKL workaround page lists this as relevant only > for A and B steppings, so I'm trusting that information for now. > > v2: Make rkl_combo_phy_b_init_wa() static > > Bspec: 49291 > Bspec: 53273 > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > .../gpu/drm/i915/display/intel_combo_phy.c | 26 +++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++- > 2 files changed, 38 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c > index 77b04bb3ec624..d5d95e2746c2c 100644 > --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c > @@ -338,6 +338,27 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, > intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); > } > > +static void rkl_combo_phy_b_init_wa(struct drm_i915_private *i915) > +{ > + u32 grccode, grccode_ldo; > + u32 iref_rcal_ord, rcompcode_ld_cap_ov; Nitpick: you could do all the bellow with just 2 u32(val and grccode). > + > + intel_de_wait_for_register(i915, ICL_PORT_COMP_DW3(PHY_A), > + FIRST_COMP_DONE, FIRST_COMP_DONE, 100); The timeout parameter here is in ms not usec. > + > + grccode = REG_FIELD_GET(GRCCODE, > + intel_de_read(i915, ICL_PORT_COMP_DW6(PHY_A))); > + iref_rcal_ord = REG_FIELD_PREP(IREF_RCAL_ORD, grccode); > + intel_de_rmw(i915, ICL_PORT_COMP_DW2(PHY_B), IREF_RCAL_ORD, > + iref_rcal_ord | IREF_RCAL_ORD_EN); > + > + grccode_ldo = REG_FIELD_GET(GRCCODE_LDO, > + intel_de_read(i915, ICL_PORT_COMP_DW0(PHY_A))); > + rcompcode_ld_cap_ov = REG_FIELD_PREP(RCOMPCODE_LD_CAP_OV, grccode_ldo); > + intel_de_rmw(i915, ICL_PORT_COMP_DW6(PHY_B), RCOMPCODE_LD_CAP_OV, > + rcompcode_ld_cap_ov | RCOMPCODEOVEN_LDO_SYNC); > +} > + > static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > { > enum phy phy; > @@ -390,6 +411,11 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) > val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); > val |= CL_POWER_DOWN_ENABLE; > intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); > + > + if (IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_B0) && > + phy == PHY_B) > + /* Wa_14011224835:rkl[a0..c0] */ > + rkl_combo_phy_b_init_wa(dev_priv); Missing the icl_combo_phy_verify_state() counter part. > } > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 34b2ec04ccd86..10f6e46523b6e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1908,11 +1908,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define CNL_PORT_COMP_DW0 _MMIO(0x162100) > #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) > -#define COMP_INIT (1 << 31) > +#define COMP_INIT REG_BIT(31) > +#define GRCCODE_LDO REG_GENMASK(7, 0) > > #define CNL_PORT_COMP_DW1 _MMIO(0x162104) > #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) > > +#define ICL_PORT_COMP_DW2(phy) _MMIO(_ICL_PORT_COMP_DW(2, phy)) > +#define IREF_RCAL_ORD_EN REG_BIT(7) > +#define IREF_RCAL_ORD REG_GENMASK(6, 0) > + > #define CNL_PORT_COMP_DW3 _MMIO(0x16210c) > #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) > #define PROCESS_INFO_DOT_0 (0 << 26) > @@ -1925,6 +1930,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define VOLTAGE_INFO_1_05V (2 << 24) > #define VOLTAGE_INFO_MASK (3 << 24) > #define VOLTAGE_INFO_SHIFT 24 > +#define FIRST_COMP_DONE REG_BIT(22) > + > +#define ICL_PORT_COMP_DW6(phy) _MMIO(_ICL_PORT_COMP_DW(6, phy)) > +#define GRCCODE REG_GENMASK(30, 24) > +#define RCOMPCODEOVEN_LDO_SYNC REG_BIT(23) > +#define RCOMPCODE_LD_CAP_OV REG_GENMASK(22, 16) > > #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) > #define IREFGEN (1 << 24) Register definition matches. From jose.souza at intel.com Wed Jun 24 00:13:18 2020 From: jose.souza at intel.com (Souza, Jose) Date: Wed, 24 Jun 2020 00:13:18 +0000 Subject: [Intel-gfx] [PATCH v2 04/32] drm/i915/rkl: Add initial workarounds In-Reply-To: <20200618004240.16263-5-lucas.demarchi@intel.com> References: <20200618004240.16263-1-lucas.demarchi@intel.com> <20200618004240.16263-5-lucas.demarchi@intel.com> Message-ID: <ec4a4921503507aa42e6eff61ffebe78a895cf26.camel@intel.com> On Wed, 2020-06-17 at 17:42 -0700, Lucas De Marchi wrote: > From: Matt Roper <matthew.d.roper at intel.com> > > RKL and TGL share some general gen12 workarounds, but each platform also > has its own platform-specific workarounds. > > v2: > - Add Wa_1604555607 for RKL. This makes RKL's ctx WA list identical to > TGL's, so we'll have both functions call the tgl_ function for now; > this workaround isn't listed for DG1 so we don't want to add it to > the general gen12_ function. > > Cc: Matt Atwood <matthew.s.atwood at intel.com> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > --- > drivers/gpu/drm/i915/display/intel_sprite.c | 5 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 +++++++++++++-------- > 2 files changed, 59 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > index 3cd461bf91311..63ac79f88fa21 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -2842,8 +2842,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, > enum plane_id plane_id) > { > - /* Wa_14010477008:tgl[a0..c0] */ > - if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) > + /* Wa_14010477008:tgl[a0..c0],rkl[all] */ > + if (IS_ROCKETLAKE(dev_priv) || > + IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0)) > return false; > > return plane_id < PLANE_SPRITE4; > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 2da366821ddaf..741710ca2b9a5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -596,8 +596,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, > wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); > } > > -static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > - struct i915_wa_list *wal) > +static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, > + struct i915_wa_list *wal) > { > /* > * Wa_1409142259:tgl > @@ -607,12 +607,28 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > * Wa_1409207793:tgl > * Wa_1409178076:tgl > * Wa_1408979724:tgl > + * Wa_14010443199:rkl > + * Wa_14010698770:rkl > */ > WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3, > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); > > + /* WaDisableGPGPUMidThreadPreemption:gen12 */ > + WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, > + GEN9_PREEMPT_GPGPU_LEVEL_MASK, > + GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); > +} > + > +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > + struct i915_wa_list *wal) > +{ > + gen12_ctx_workarounds_init(engine, wal); > + > /* > - * Wa_1604555607:gen12 and Wa_1608008084:gen12 > + * Wa_1604555607:tgl,rkl > + * > + * Note that the implementation of this workaround is further modified > + * according to the FF_MODE2 guidance given by Wa_1608008084:gen12. > * FF_MODE2 register will return the wrong value when read. The default > * value for this register is zero for all fields and there are no bit > * masks. So instead of doing a RMW we should just write the GS Timer > @@ -623,11 +639,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > FF_MODE2_GS_TIMER_MASK | FF_MODE2_TDS_TIMER_MASK, > FF_MODE2_GS_TIMER_224 | FF_MODE2_TDS_TIMER_128, > 0); > - > - /* WaDisableGPGPUMidThreadPreemption:tgl */ > - WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, > - GEN9_PREEMPT_GPGPU_LEVEL_MASK, > - GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); > } > > static void > @@ -642,8 +653,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, > > wa_init_start(wal, name, engine->name); > > - if (IS_GEN(i915, 12)) > + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) > tgl_ctx_workarounds_init(engine, wal); > + else if (IS_GEN(i915, 12)) > + gen12_ctx_workarounds_init(engine, wal); > else if (IS_GEN(i915, 11)) > icl_ctx_workarounds_init(engine, wal); > else if (IS_CANNONLAKE(i915)) > @@ -1176,9 +1189,16 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > } > > static void > -tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +gen12_gt_workarounds_init(struct drm_i915_private *i915, > + struct i915_wa_list *wal) > { > wa_init_mcr(i915, wal); > +} > + > +static void > +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > +{ > + gen12_gt_workarounds_init(i915, wal); > > /* Wa_1409420604:tgl */ > if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) > @@ -1196,8 +1216,10 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > static void > gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > - if (IS_GEN(i915, 12)) > + if (IS_TIGERLAKE(i915)) > tgl_gt_workarounds_init(i915, wal); > + else if (IS_GEN(i915, 12)) > + gen12_gt_workarounds_init(i915, wal); > else if (IS_GEN(i915, 11)) > icl_gt_workarounds_init(i915, wal); > else if (IS_CANNONLAKE(i915)) > @@ -1629,18 +1651,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > GEN9_CTX_PREEMPT_REG, > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); > > - /* > - * Wa_1607030317:tgl > - * Wa_1607186500:tgl > - * Wa_1607297627:tgl there is 3 entries for this WA on BSpec, 2 > - * of then says it is fixed on B0 the other one says it is > - * permanent > - */ > - wa_masked_en(wal, > - GEN6_RC_SLEEP_PSMI_CONTROL, > - GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | > - GEN8_RC_SEMA_IDLE_MSG_DISABLE); > - > /* > * Wa_1606679103:tgl > * (see also Wa_1606682166:icl) > @@ -1659,24 +1669,38 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > VSUNIT_CLKGATE_DIS_TGL); > } > > - if (IS_TIGERLAKE(i915)) { > - /* Wa_1606931601:tgl */ > + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) { > + /* Wa_1606931601:tgl,rkl */ > wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); > > - /* Wa_1409804808:tgl */ > + /* Wa_1409804808:tgl,rkl */ > wa_masked_en(wal, GEN7_ROW_CHICKEN2, > GEN12_PUSH_CONST_DEREF_HOLD_DIS); > > - /* Wa_1606700617:tgl */ > - wa_masked_en(wal, > - GEN9_CS_DEBUG_MODE1, > - FF_DOP_CLOCK_GATE_DISABLE); > - > /* > * Wa_1409085225:tgl > - * Wa_14010229206:tgl > + * Wa_14010229206:tgl,rkl > */ > wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); > + > + /* > + * Wa_1607030317:tgl > + * Wa_1607186500:tgl > + * Wa_1607297627:tgl,rkl there are multiple entries for this > + * WA in the BSpec; some indicate this is an A0-only WA, > + * others indicate it applies to all steppings. > + */ > + wa_masked_en(wal, > + GEN6_RC_SLEEP_PSMI_CONTROL, > + GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE | > + GEN8_RC_SEMA_IDLE_MSG_DISABLE); > + } > + > + if (IS_TIGERLAKE(i915)) { > + /* Wa_1606700617:tgl */ > + wa_masked_en(wal, > + GEN9_CS_DEBUG_MODE1, > + FF_DOP_CLOCK_GATE_DISABLE); RKL might need this one too under the number 14010230801 but is still pending. Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > } > > if (IS_GEN(i915, 11)) { From sfr at canb.auug.org.au Wed Jun 24 01:36:37 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Wed, 24 Jun 2020 11:36:37 +1000 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree In-Reply-To: <20200617105929.534edd34@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> Message-ID: <20200624113452.54b72fcc@canb.auug.org.au> Hi all, On Wed, 17 Jun 2020 10:59:29 +1000 Stephen Rothwell <sfr at canb.auug.org.au> wrote: > > After merging the drm-misc tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c: In function 'amdgpu_amdkfd_gpuvm_free_memory_of_gpu': > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1357:2: error: implicit declaration of function 'drm_gem_object_put_unlocked'; did you mean 'drm_gem_object_put_locked'? [-Werror=implicit-function-declaration] > 1357 | drm_gem_object_put_unlocked(&mem->bo->tbo.base); > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ > | drm_gem_object_put_locked > > Caused by commit > > ab15d56e27be ("drm: remove transient drm_gem_object_put_unlocked()") > > interacting with commit > > fd9a9f8801de ("drm/amdgpu: Use GEM obj reference for KFD BOs") > > from Linus' tree. > > I have applied the following merge fix up patch for today. > > From: Stephen Rothwell <sfr at canb.auug.org.au> > Date: Wed, 17 Jun 2020 10:55:32 +1000 > Subject: [PATCH] drm/amdgpu: remove stray drm_gem_object_put_unlocked > > Signed-off-by: Stephen Rothwell <sfr at canb.auug.org.au> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > index b91b5171270f..9015c7b76d60 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > @@ -1354,7 +1354,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( > } > > /* Free the BO*/ > - drm_gem_object_put_unlocked(&mem->bo->tbo.base); > + drm_gem_object_put(&mem->bo->tbo.base); > mutex_destroy(&mem->lock); > kfree(mem); > > -- > 2.26.2 This fix is now needed when I merge the drm tree :-( Given that the drm tree is based on v5.8-rc2 and the commit from Linus' tree above was merged before v5.8-rc1, the above patch should be applied to the drm tree (and should have been part of the patch that merged the drm-misc tree). I am a bit suprised that the drm tree currently passes CI. Sorry, Dave, for not cc'ing you in the original report. -- Cheers, Stephen Rothwell -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200624/b3b3f2f8/attachment.sig> From patchwork at emeril.freedesktop.org Wed Jun 24 02:08:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 02:08:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/fb-helper=3A_Fix_vt_restore?= In-Reply-To: <20200623155456.3092836-1-daniel.vetter@ffwll.ch> References: <20200623155456.3092836-1-daniel.vetter@ffwll.ch> Message-ID: <159296451751.19236.14371336120373354229@emeril.freedesktop.org> == Series Details == Series: drm/fb-helper: Fix vt restore URL : https://patchwork.freedesktop.org/series/78746/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8658_full -> Patchwork_18012_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18012_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18012_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18012_full: ### IGT changes ### #### Possible regressions #### * igt at kms_cursor_crc@pipe-c-cursor-64x64-rapid-movement: - shard-tglb: [PASS][1] -> [TIMEOUT][2] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb6/igt at kms_cursor_crc@pipe-c-cursor-64x64-rapid-movement.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-tglb8/igt at kms_cursor_crc@pipe-c-cursor-64x64-rapid-movement.html Known issues ------------ Here are the changes found in Patchwork_18012_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_balancer@sliced: - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#1936] / [i915#1958]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb6/igt at gem_exec_balancer@sliced.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-tglb8/igt at gem_exec_balancer@sliced.html * igt at gem_exec_schedule@smoketest-all: - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk4/igt at gem_exec_schedule@smoketest-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-glk8/igt at gem_exec_schedule@smoketest-all.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / [i915#95]) +16 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl8/igt at i915_suspend@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-apl4/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk2/igt at kms_big_fb@linear-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_ccs@pipe-d-ccs-on-another-bo: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#402]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb3/igt at kms_ccs@pipe-d-ccs-on-another-bo.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-tglb1/igt at kms_ccs@pipe-d-ccs-on-another-bo.html * igt at kms_color@pipe-a-ctm-negative: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl2/igt at kms_color@pipe-a-ctm-negative.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl1/igt at kms_color@pipe-a-ctm-negative.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([i915#54] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_cursor_legacy@pipe-b-torture-bo: - shard-tglb: [PASS][17] -> [DMESG-WARN][18] ([i915#128]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb3/igt at kms_cursor_legacy@pipe-b-torture-bo.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-tglb2/igt at kms_cursor_legacy@pipe-b-torture-bo.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: - shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([fdo#108145] / [i915#54] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl7/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html * igt at kms_flip@flip-vs-expired-vblank at b-dp1: - shard-kbl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl6/igt at kms_flip@flip-vs-expired-vblank at b-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl4/igt at kms_flip@flip-vs-expired-vblank at b-dp1.html * igt at kms_flip@flip-vs-expired-vblank at c-edp1: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#46]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at c-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl6/igt at kms_flip@flip-vs-expired-vblank at c-edp1.html * igt at kms_flip@plain-flip-fb-recreate at c-edp1: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1928]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at kms_flip@plain-flip-fb-recreate at c-edp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl2/igt at kms_flip@plain-flip-fb-recreate at c-edp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][27] -> [DMESG-FAIL][28] ([i915#1635] / [i915#95]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-apl4/igt at kms_flip_tiling@flip-changes-tiling.html - shard-kbl: [PASS][29] -> [DMESG-FAIL][30] ([i915#95]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl1/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][33] -> [FAIL][34] ([i915#1188]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_invalid_dotclock: - shard-snb: [PASS][35] -> [TIMEOUT][36] ([i915#1958]) +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-snb2/igt at kms_invalid_dotclock.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-snb5/igt at kms_invalid_dotclock.html * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#93] / [i915#95]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl1/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html * igt at kms_setmode@basic: - shard-kbl: [PASS][39] -> [FAIL][40] ([i915#31]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl6/igt at kms_setmode@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#180]) +3 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl3/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][43] -> [FAIL][44] ([i915#1542]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-iclb5/igt at perf@blocking-parameterized.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-iclb6/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-kbl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl4/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][47] ([i915#1930]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-glk9/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][49] ([i915#69]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at gem_softpin@noreloc-s3.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl4/igt at gem_softpin@noreloc-s3.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][51] ([i915#402]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb5/igt at i915_module_load@reload.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][53] ([i915#118] / [i915#95]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-glk6/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-skl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +7 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl4/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_color@pipe-b-ctm-0-25: - shard-kbl: [DMESG-WARN][57] ([i915#93] / [i915#95]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl3/igt at kms_color@pipe-b-ctm-0-25.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl7/igt at kms_color@pipe-b-ctm-0-25.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-hdmi-a1: - shard-glk: [FAIL][59] ([i915#407]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk9/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-hdmi-a1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-glk6/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-hdmi-a1.html * igt at kms_flip@plain-flip-fb-recreate at b-edp1: - shard-skl: [FAIL][61] ([i915#1928]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at kms_flip@plain-flip-fb-recreate at b-edp1.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl2/igt at kms_flip@plain-flip-fb-recreate at b-edp1.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-iclb8/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm: - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +16 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl1/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-apl3/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][69] ([i915#1820]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl4/igt at perf_pmu@semaphore-busy at rcs0.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl3/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][71] ([i915#1930]) -> [TIMEOUT][72] ([i915#1958]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-psr: - shard-tglb: [FAIL][73] ([i915#454]) -> [SKIP][74] ([i915#468]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb7/igt at i915_pm_dc@dc6-psr.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-tglb2/igt at i915_pm_dc@dc6-psr.html * igt at kms_content_protection@atomic-dpms: - shard-kbl: [TIMEOUT][75] ([i915#1319] / [i915#1958]) -> [TIMEOUT][76] ([i915#1319]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl1/igt at kms_content_protection@atomic-dpms.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-kbl7/igt at kms_content_protection@atomic-dpms.html * igt at kms_draw_crc@draw-method-rgb565-render-ytiled: - shard-snb: [SKIP][77] ([fdo#109271]) -> [TIMEOUT][78] ([i915#1958]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-snb2/igt at kms_draw_crc@draw-method-rgb565-render-ytiled.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-snb5/igt at kms_draw_crc@draw-method-rgb565-render-ytiled.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-apl: [SKIP][79] ([fdo#109271]) -> [SKIP][80] ([fdo#109271] / [i915#1635]) +5 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-apl4/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: [DMESG-FAIL][81] ([fdo#108145] / [i915#1982]) -> [FAIL][82] ([fdo#108145] / [i915#265]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl1/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt at perf@gen12-unprivileged-single-ctx-counters: - shard-apl: [SKIP][83] ([fdo#109271] / [i915#1635]) -> [SKIP][84] ([fdo#109271]) +2 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl7/igt at perf@gen12-unprivileged-single-ctx-counters.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/shard-apl2/igt at perf@gen12-unprivileged-single-ctx-counters.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8658 -> Patchwork_18012 CI-20190529: 20190529 CI_DRM_8658: c86979e2fe3c106d95b5fcf2075709afa40f0f95 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18012: 71234d269281c8b8a934040ef4eab9d2313acf92 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18012/index.html From patchwork at emeril.freedesktop.org Wed Jun 24 02:15:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 02:15:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Add_support_for_HDCP_1=2E4_over_MST?= In-Reply-To: <20200623155907.22961-1-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> Message-ID: <159296493987.19237.2868302702897935748@emeril.freedesktop.org> == Series Details == Series: drm/i915: Add support for HDCP 1.4 over MST URL : https://patchwork.freedesktop.org/series/78749/ State : success == Summary == CI Bug Log - changes from CI_DRM_8658_full -> Patchwork_18013_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18013_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_fence@parallel at vcs0: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk7/igt at gem_exec_fence@parallel at vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-glk9/igt at gem_exec_fence@parallel at vcs0.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#95]) +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl8/igt at i915_suspend@sysfs-reader.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-apl6/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at kms_big_fb@linear-32bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl2/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_ccs@pipe-d-ccs-on-another-bo: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb3/igt at kms_ccs@pipe-d-ccs-on-another-bo.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-tglb1/igt at kms_ccs@pipe-d-ccs-on-another-bo.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [PASS][9] -> [DMESG-FAIL][10] ([i915#54] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl3/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-apl2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][13] -> [FAIL][14] ([IGT#5]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl4/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl1/igt at kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: - shard-kbl: [PASS][15] -> [DMESG-FAIL][16] ([fdo#108145] / [i915#54] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-kbl6/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +7 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-kbl7/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][19] -> [DMESG-FAIL][20] ([i915#1635] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-apl6/igt at kms_flip_tiling@flip-changes-tiling.html - shard-kbl: [PASS][21] -> [DMESG-FAIL][22] ([i915#95]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-kbl3/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#123] / [i915#69]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl3/igt at kms_frontbuffer_tracking@psr-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl7/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl10/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_invalid_dotclock: - shard-snb: [PASS][27] -> [TIMEOUT][28] ([i915#1958]) +3 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-snb2/igt at kms_invalid_dotclock.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-snb4/igt at kms_invalid_dotclock.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#69]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl10/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-kbl: [PASS][31] -> [DMESG-WARN][32] ([i915#93] / [i915#95]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-kbl3/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html #### Possible fixes #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][33] ([i915#1930]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-contexts-all: - shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk7/igt at gem_exec_whisper@basic-contexts-all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-glk9/igt at gem_exec_whisper@basic-contexts-all.html * igt at gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][37] ([i915#69]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at gem_softpin@noreloc-s3.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl1/igt at gem_softpin@noreloc-s3.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][39] ([i915#402]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb5/igt at i915_module_load@reload.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-tglb1/igt at i915_module_load@reload.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-glk1/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_big_fb@yf-tiled-32bpp-rotate-0: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +8 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl4/igt at kms_big_fb@yf-tiled-32bpp-rotate-0.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-hdmi-a1: - shard-glk: [FAIL][45] ([i915#407]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-glk9/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-hdmi-a1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-glk6/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-hdmi-a1.html * igt at kms_flip@plain-flip-fb-recreate at b-edp1: - shard-skl: [FAIL][47] ([i915#1928]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl5/igt at kms_flip@plain-flip-fb-recreate at b-edp1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl2/igt at kms_flip@plain-flip-fb-recreate at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: - shard-apl: [DMESG-WARN][49] ([i915#1635] / [i915#95]) -> [PASS][50] +13 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-apl1/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html * igt at kms_frontbuffer_tracking@fbc-rgb565-draw-blt: - shard-tglb: [DMESG-WARN][51] ([i915#1982]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb7/igt at kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-tglb2/igt at kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-iclb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-iclb7/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +4 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-kbl4/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [FAIL][59] ([i915#1930]) -> [TIMEOUT][60] ([i915#1958]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-snb4/igt at gem_exec_reloc@basic-concurrent16.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [FAIL][61] ([i915#454]) -> [SKIP][62] ([i915#468]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-tglb8/igt at i915_pm_dc@dc6-dpms.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html * igt at kms_color_chamelium@pipe-b-degamma: - shard-apl: [SKIP][63] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][64] ([fdo#109271] / [fdo#111827]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl7/igt at kms_color_chamelium@pipe-b-degamma.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-apl8/igt at kms_color_chamelium@pipe-b-degamma.html * igt at kms_draw_crc@draw-method-rgb565-render-ytiled: - shard-snb: [SKIP][65] ([fdo#109271]) -> [TIMEOUT][66] ([i915#1958]) +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-snb2/igt at kms_draw_crc@draw-method-rgb565-render-ytiled.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-snb4/igt at kms_draw_crc@draw-method-rgb565-render-ytiled.html * igt at kms_flip_tiling@flip-changes-tiling-yf: - shard-kbl: [DMESG-FAIL][67] ([i915#95]) -> [DMESG-WARN][68] ([i915#93] / [i915#95]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling-yf.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-kbl4/igt at kms_flip_tiling@flip-changes-tiling-yf.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc: - shard-apl: [SKIP][69] ([fdo#109271] / [i915#1635]) -> [SKIP][70] ([fdo#109271]) +5 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl4/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-apl8/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-apl: [SKIP][71] ([fdo#109271]) -> [SKIP][72] ([fdo#109271] / [i915#1635]) +5 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8658/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/shard-apl6/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8658 -> Patchwork_18013 CI-20190529: 20190529 CI_DRM_8658: c86979e2fe3c106d95b5fcf2075709afa40f0f95 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18013: ff0e9553b262afa612271f33b6f768d8f39093e0 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18013/index.html From thomas_os at shipmail.org Wed Jun 24 05:42:33 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Wed, 24 Jun 2020 07:42:33 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159294690652.3967.16801810632630360943@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> <159293768060.3967.16328770521784351822@build.alporthouse.com> <88f746c6-c6ad-8c19-7797-856ac6bb2f50@shipmail.org> <159294690652.3967.16801810632630360943@build.alporthouse.com> Message-ID: <ef797b36-22e9-887b-dca4-5a845c60aed7@shipmail.org> On 6/23/20 11:15 PM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-23 21:31:38) >> On 6/23/20 8:41 PM, Chris Wilson wrote: >>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 19:21:28) >>>> On 6/23/20 6:36 PM, Chris Wilson wrote: >>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) >>>>>> Hi, Chris, >>>>>> >>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: >>>>>>> In order to actually handle eviction and what not, we need to process >>>>>>> all the objects together under a common lock, reservation_ww_class. As >>>>>>> such, do a memory reservation pass after looking up the object/vma, >>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>>>>>> flushing and ofc execution]. >>>>>>> >>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>>>>>> --- >>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>>>> index 46fcbdf8161c..8db2e013465f 100644 >>>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>>>> @@ -53,10 +53,9 @@ struct eb_vma_array { >>>>>>> >>>>>>> #define __EXEC_OBJECT_HAS_PIN BIT(31) >>>>>>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) >>>>>>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) >>>>>>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) >>>>>>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) >>>>>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ >>>>>>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) >>>>>>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) >>>>>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ >>>>>>> >>>>>>> #define __EXEC_HAS_RELOC BIT(31) >>>>>>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) >>>>>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { >>>>>>> struct intel_context *context; /* logical state for the request */ >>>>>>> struct i915_gem_context *gem_context; /** caller's context */ >>>>>>> >>>>>>> + struct dma_fence *mm_fence; >>>>>>> + >>>>>>> struct i915_request *request; /** our request to build */ >>>>>>> struct eb_vma *batch; /** identity of the batch obj/vma */ >>>>>>> struct i915_vma *trampoline; /** trampoline used for chaining */ >>>>>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) >>>>>>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) >>>>>>> __i915_vma_unpin(vma); >>>>>>> >>>>>>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) >>>>>>> - i915_gem_object_unpin_pages(vma->obj); >>>>>>> - >>>>>>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | >>>>>>> - __EXEC_OBJECT_HAS_FENCE | >>>>>>> - __EXEC_OBJECT_HAS_PAGES); >>>>>>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); >>>>>>> } >>>>>>> >>>>>>> static void eb_vma_array_destroy(struct kref *kref) >>>>>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, >>>>>>> list_add_tail(&ev->lock_link, &eb->lock); >>>>>>> } >>>>>>> >>>>>>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, >>>>>>> + struct eb_vma *ev, >>>>>>> + u64 idx) >>>>>>> +{ >>>>>>> + struct i915_vma *vma = ev->vma; >>>>>>> + int err; >>>>>>> + >>>>>>> + /* XXX also preallocate PD for vma */ >>>>>>> + >>>>>>> + err = ____i915_gem_object_get_pages_async(vma->obj); >>>>>>> + if (err) >>>>>>> + return err; >>>>>>> + >>>>>>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); >>>>>>> +} >>>>>>> + >>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>>>>>> +{ >>>>>>> + const u64 idx = eb->context->timeline->fence_context; >>>>>>> + struct ww_acquire_ctx acquire; >>>>>>> + struct eb_vma *ev; >>>>>>> + int err; >>>>>>> + >>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); >>>>>>> + if (!eb->mm_fence) >>>>>>> + return -ENOMEM; >>>>>> Question: eb is local to this thread, right, so eb->mm_fence is not >>>>>> considered "published" yet? >>>>>> >>>>>>> + >>>>>>> + ww_acquire_init(&acquire, &reservation_ww_class); >>>>>>> + >>>>>>> + err = eb_lock_vma(eb, &acquire); >>>>>>> + if (err) >>>>>>> + goto out; >>>>>>> + >>>>>>> + ww_acquire_done(&acquire); >>>>>>> + >>>>>>> + list_for_each_entry(ev, &eb->lock, lock_link) { >>>>>>> + struct i915_vma *vma = ev->vma; >>>>>>> + >>>>>>> + if (err == 0) >>>>>>> + err = eb_vma_get_pages(eb, ev, idx); >>>>>> I figure this is where you publish the proxy fence? If so, the fence >>>>>> signaling critical path starts with this loop, >>>>> Hmm, actually at this moment, the fence is still very much internal >>>>> being only used as a reference token, >>>> I think as long as another thread, running in this driver or another gpu >>>> driver can theoretically reference the fence pointer from the >>>> reservation object and wait for the fence it's considered published. >>> It's not in the reservation object. >>> >>>> Also the ww_mutexes in this context are really all about grabbing a >>>> random set of resources and associate them with a point in a timeline, >>>> as the ww_mutexes are released, the fence pointer(s) need to point to >>>> published fence(s). >>> That's not the purpose of these fences, though. They exist to provide >>> reference counting on the backing store, along side the migration fence. >>> It's extra detail tacked on the equivalent of bo->moving. >>> >>> That is not to say that one could build up an async migration chain which >>> form a graph back to these, that chain could only be formed once the >>> operation itself has been published in the dma_resv though. >> Hmm. So let's say another thread grabs one of the just released >> ww_mutexes and wants to schedule a blit from one of the buffers in the >> current operation with high priority. How would that thread know how to >> order that blit operation w r t the current operation? > Why would it order? So let's say it's an eviction blit, needing to incorporate the data from the current operation. Or, for that matter a ttm-style cpu copy eviction: ww_mutex_lock wait_for_idle copy ww_mutex_unlock /Thomas From airlied at gmail.com Wed Jun 24 05:47:49 2020 From: airlied at gmail.com (Dave Airlie) Date: Wed, 24 Jun 2020 15:47:49 +1000 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree In-Reply-To: <20200624113452.54b72fcc@canb.auug.org.au> References: <20200617105929.534edd34@canb.auug.org.au> <20200624113452.54b72fcc@canb.auug.org.au> Message-ID: <CAPM=9tx5b1RaN5R4awqQ-BFpDrEZL1z05ZFv2MnGGS2t3mpBhQ@mail.gmail.com> On Wed, 24 Jun 2020 at 11:36, Stephen Rothwell <sfr at canb.auug.org.au> wrote: > > Hi all, > > On Wed, 17 Jun 2020 10:59:29 +1000 Stephen Rothwell <sfr at canb.auug.org.au> wrote: > > > > After merging the drm-misc tree, today's linux-next build (x86_64 > > allmodconfig) failed like this: > > > > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c: In function 'amdgpu_amdkfd_gpuvm_free_memory_of_gpu': > > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c:1357:2: error: implicit declaration of function 'drm_gem_object_put_unlocked'; did you mean 'drm_gem_object_put_locked'? [-Werror=implicit-function-declaration] > > 1357 | drm_gem_object_put_unlocked(&mem->bo->tbo.base); > > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ > > | drm_gem_object_put_locked > > > > Caused by commit > > > > ab15d56e27be ("drm: remove transient drm_gem_object_put_unlocked()") > > > > interacting with commit > > > > fd9a9f8801de ("drm/amdgpu: Use GEM obj reference for KFD BOs") > > > > from Linus' tree. > > > > I have applied the following merge fix up patch for today. > > > > From: Stephen Rothwell <sfr at canb.auug.org.au> > > Date: Wed, 17 Jun 2020 10:55:32 +1000 > > Subject: [PATCH] drm/amdgpu: remove stray drm_gem_object_put_unlocked > > > > Signed-off-by: Stephen Rothwell <sfr at canb.auug.org.au> > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > > index b91b5171270f..9015c7b76d60 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c > > @@ -1354,7 +1354,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( > > } > > > > /* Free the BO*/ > > - drm_gem_object_put_unlocked(&mem->bo->tbo.base); > > + drm_gem_object_put(&mem->bo->tbo.base); > > mutex_destroy(&mem->lock); > > kfree(mem); > > > > -- > > 2.26.2 > > This fix is now needed when I merge the drm tree :-( > > Given that the drm tree is based on v5.8-rc2 and the commit from Linus' > tree above was merged before v5.8-rc1, the above patch should be > applied to the drm tree (and should have been part of the patch that > merged the drm-misc tree). I am a bit suprised that the drm tree > currently passes CI. My bad, my local builds passed, as I had made the change but forgot the commit --amend Pushed out a new head with it in it now. Dave. From kunal1.joshi at intel.com Tue Jun 23 18:57:53 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Wed, 24 Jun 2020 00:27:53 +0530 Subject: [Intel-gfx] [PATCH v6 0/3] Send a hotplug when edid changes Message-ID: <20200623185756.19502-1-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> This series introduce to drm a way to determine if something else except connection_status had changed during probing, which can be used by other drivers as well. Another i915 specific part uses this approach to determine if edid had changed without changing the connection status and send a hotplug event. Stanislav Lisovskiy (3): drm: Add helper to compare edids. drm: Introduce epoch counter to drm_connector drm/i915: Send hotplug event if edid had changed drivers/gpu/drm/drm_connector.c | 16 ++++++++ drivers/gpu/drm/drm_edid.c | 39 +++++++++++++++++++- drivers/gpu/drm/drm_probe_helper.c | 38 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_hotplug.c | 26 +++++++------ include/drm/drm_connector.h | 2 + include/drm/drm_edid.h | 9 +++++ 6 files changed, 113 insertions(+), 17 deletions(-) -- 2.25.1 From kunal1.joshi at intel.com Tue Jun 23 18:57:54 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Wed, 24 Jun 2020 00:27:54 +0530 Subject: [Intel-gfx] [PATCH v6 1/3] drm: Add helper to compare edids. In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <20200623185756.19502-2-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Many drivers would benefit from using drm helper to compare edid, rather than bothering with own implementation. v2: Added documentation for this function. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/drm_edid.c | 33 +++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 9 +++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index d8372d63851b..34cabfddcdd3 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1615,6 +1615,39 @@ static bool drm_edid_is_zero(const u8 *in_edid, int length) return true; } +/** + * drm_edid_are_equal - compare two edid blobs. + * @edid1: pointer to first blob + * @edid2: pointer to second blob + * This helper can be used during probing to determine if + * edid had changed. + */ +bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) +{ + int edid1_len, edid2_len; + bool edid1_present = edid1 != NULL; + bool edid2_present = edid2 != NULL; + + if (edid1_present != edid2_present) + return false; + + if (edid1) { + + edid1_len = EDID_LENGTH * (1 + edid1->extensions); + edid2_len = EDID_LENGTH * (1 + edid2->extensions); + + if (edid1_len != edid2_len) + return false; + + if (memcmp(edid1, edid2, edid1_len)) + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_edid_are_equal); + + /** * drm_edid_block_valid - Sanity check the EDID block (base or extension) * @raw_edid: pointer to raw EDID block diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 34b15e3d070c..5c26cc65b786 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -359,6 +359,15 @@ drm_load_edid_firmware(struct drm_connector *connector) } #endif +/** + * drm_edid_are_equal - compare two edid blobs. + * @edid1: pointer to first blob + * @edid2: pointer to second blob + * This helper can be used during probing to determine if + * edid had changed. + */ +bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); + int drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, struct drm_connector *connector, -- 2.25.1 From kunal1.joshi at intel.com Tue Jun 23 18:57:55 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Wed, 24 Jun 2020 00:27:55 +0530 Subject: [Intel-gfx] [PATCH v6 2/3] drm: Introduce epoch counter to drm_connector In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <20200623185756.19502-3-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> This counter will be used by drm_helper_probe_detect caller to determine if anything had changed(including edid, connection status and etc). Hardware specific driver detect hooks are responsible for updating this counter when some change is detected to notify the drm part, which can trigger for example hotplug event. Also now call drm_connector_update_edid_property right after we get edid always to make sure there is a unified way to handle edid change, without having to change tons of source code as currently drm_connector_update_edid_property is called only in certain cases like reprobing and not right after edid is actually updated. v2: Added documentation for the new counter. Rename change_counter to epoch_counter. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105540 Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/drm_connector.c | 16 +++++++++++++ drivers/gpu/drm/drm_edid.c | 6 ++++- drivers/gpu/drm/drm_probe_helper.c | 38 ++++++++++++++++++++++++++---- include/drm/drm_connector.h | 2 ++ 4 files changed, 56 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index b7bd46033807..332686297e45 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -269,6 +269,7 @@ int drm_connector_init(struct drm_device *dev, INIT_LIST_HEAD(&connector->modes); mutex_init(&connector->mutex); connector->edid_blob_ptr = NULL; + connector->epoch_counter = 0; connector->tile_blob_ptr = NULL; connector->status = connector_status_unknown; connector->display_info.panel_orientation = @@ -1979,6 +1980,7 @@ int drm_connector_update_edid_property(struct drm_connector *connector, struct drm_device *dev = connector->dev; size_t size = 0; int ret; + const struct edid *old_edid; /* ignore requests to set edid when overridden */ if (connector->override_edid) @@ -2002,6 +2004,20 @@ int drm_connector_update_edid_property(struct drm_connector *connector, drm_update_tile_info(connector, edid); + if (connector->edid_blob_ptr) { + old_edid = (const struct edid *)connector->edid_blob_ptr->data; + if (old_edid) { + if (!drm_edid_are_equal(edid, old_edid)) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", + connector->base.id, connector->name); + + connector->epoch_counter += 1; + DRM_DEBUG_KMS("Updating change counter to %llu\n", + connector->epoch_counter); + } + } + } + drm_object_property_set_value(&connector->base, dev->mode_config.non_desktop_property, connector->display_info.non_desktop); diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 34cabfddcdd3..d029cbd5d037 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2050,13 +2050,17 @@ EXPORT_SYMBOL(drm_probe_ddc); struct edid *drm_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) { + struct edid *edid; + if (connector->force == DRM_FORCE_OFF) return NULL; if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) return NULL; - return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); + edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); + drm_connector_update_edid_property(connector, edid); + return edid; } EXPORT_SYMBOL(drm_get_edid); diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index 26e997f1524f..1d5f319d6213 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -290,6 +290,9 @@ drm_helper_probe_detect_ctx(struct drm_connector *connector, bool force) if (WARN_ON(ret < 0)) ret = connector_status_unknown; + if (ret != connector->status) + connector->epoch_counter += 1; + drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); @@ -323,11 +326,16 @@ drm_helper_probe_detect(struct drm_connector *connector, return ret; if (funcs->detect_ctx) - return funcs->detect_ctx(connector, ctx, force); + ret = funcs->detect_ctx(connector, ctx, force); else if (connector->funcs->detect) - return connector->funcs->detect(connector, force); + ret = connector->funcs->detect(connector, force); else - return connector_status_connected; + ret = connector_status_connected; + + if (ret != connector->status) + connector->epoch_counter += 1; + + return ret; } EXPORT_SYMBOL(drm_helper_probe_detect); @@ -777,6 +785,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) struct drm_connector_list_iter conn_iter; enum drm_connector_status old_status; bool changed = false; + uint64_t old_epoch_counter; if (!dev->mode_config.poll_enabled) return false; @@ -790,20 +799,39 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) old_status = connector->status; + old_epoch_counter = connector->epoch_counter; + + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Old epoch counter %llu\n", connector->base.id, + connector->name, + old_epoch_counter); + connector->status = drm_helper_probe_detect(connector, NULL, false); DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", connector->base.id, connector->name, drm_get_connector_status_name(old_status), drm_get_connector_status_name(connector->status)); - if (old_status != connector->status) + + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] New epoch counter %llu\n", + connector->base.id, + connector->name, + connector->epoch_counter); + + /* + * Check if epoch counter had changed, meaning that we need + * to send a uevent. + */ + if (old_epoch_counter != connector->epoch_counter) { changed = true; + } } drm_connector_list_iter_end(&conn_iter); mutex_unlock(&dev->mode_config.mutex); - if (changed) + if (changed) { drm_kms_helper_hotplug_event(dev); + DRM_DEBUG_KMS("Sent hotplug event\n"); + } return changed; } diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index fd543d1db9b2..20bdc16eefe2 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -1329,6 +1329,8 @@ struct drm_connector { enum drm_connector_force force; /** @override_edid: has the EDID been overwritten through debugfs for testing? */ bool override_edid; + /** @epoch_counter: used to detect any other changes in connector, besides status */ + uint64_t epoch_counter; /** * @possible_encoders: Bit mask of encoders that can drive this -- 2.25.1 From kunal1.joshi at intel.com Tue Jun 23 18:57:56 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Wed, 24 Jun 2020 00:27:56 +0530 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915: Send hotplug event if edid had changed In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <20200623185756.19502-4-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Added epoch counter checking to intel_encoder_hotplug in order to be able process all the connector changes, besides connection status. Also now any change in connector would result in epoch counter change, so no multiple checks are needed. v2: Renamed change counter to epoch counter. Fixed type name. v3: Fixed rebase conflict v4: Remove duplicate drm_edid_equal checks from hdmi and dp, lets use only once edid property is getting updated and increment epoch counter from there. Also lets now call drm_connector_update_edid_property right after we get edid always to make sure there is a unified way to handle edid change, without having to change tons of source code as currently drm_connector_update_edid_property is called only in certain cases like reprobing and not right after edid is actually updated. v5: Fixed const modifiers, removed blank line v6: Removed drm specific part from this patch, leaving only i915 specific changes here. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/i915/display/intel_hotplug.c | 26 +++++++++++--------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 2e94c1413c02..393813494523 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -283,6 +283,8 @@ intel_encoder_hotplug(struct intel_encoder *encoder, { struct drm_device *dev = connector->base.dev; enum drm_connector_status old_status; + u64 old_epoch_counter; + bool ret = false; drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex)); old_status = connector->base.status; @@ -290,17 +292,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder, connector->base.status = drm_helper_probe_detect(&connector->base, NULL, false); - if (old_status == connector->base.status) - return INTEL_HOTPLUG_UNCHANGED; - - drm_dbg_kms(&to_i915(dev)->drm, - "[CONNECTOR:%d:%s] status updated from %s to %s\n", - connector->base.base.id, - connector->base.name, - drm_get_connector_status_name(old_status), - drm_get_connector_status_name(connector->base.status)); - - return INTEL_HOTPLUG_CHANGED; + if (old_epoch_counter != connector->base.epoch_counter) + ret = true; + + if(ret) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s(epoch counter %llu)\n", + connector->base.base.id, + connector->base.name, + drm_get_connector_status_name(old_status), + drm_get_connector_status_name(connector->base.status), + connector->base.epoch_counter); + return INTEL_HOTPLUG_CHANGED; + } + return INTEL_HOTPLUG_UNCHANGED; } static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder) -- 2.25.1 From thomas_os at shipmail.org Wed Jun 24 07:10:43 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Wed, 24 Jun 2020 09:10:43 +0200 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> Message-ID: <a6c4e18e-7ba3-8ce7-caaf-78b3946441e6@shipmail.org> Hi, Maarten, On 6/23/20 4:28 PM, Maarten Lankhorst wrote: > i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory > eviction. We don't use it yet, but lets start adding the definition > first. > > To use it, we have to pass a non-NULL ww to gem_object_lock, and don't > unlock directly. It is done in i915_gem_ww_ctx_fini. > > Changes since v1: > - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- > .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- > .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- > .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- > .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- > .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- > .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- > drivers/gpu/drm/i915/i915_gem.h | 11 ++++ > drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ > drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- > .../drm/i915/selftests/intel_memory_region.c | 2 +- > 24 files changed, 173 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > index b1f82a11aef2..3740c0080e38 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > @@ -122,6 +122,15 @@ struct drm_i915_gem_object { > */ > struct list_head lut_list; > > + /** > + * @obj_link: Link into @i915_gem_ww_ctx.obj_list > + * > + * When we lock this object through i915_gem_object_lock() with a > + * context, we add it to the list to ensure we can unlock everything > + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. > + */ > + struct list_head obj_link; > + Since we don't refcount objects on the list, (and we shouldn't need to), perhaps a debug warning if during object destruction, this isn't an empty list head? Other than that, this patch looks good to me. Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> From daniel at ffwll.ch Wed Jun 24 07:15:53 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 24 Jun 2020 09:15:53 +0200 Subject: [Intel-gfx] [PATCH 8/8] drm/tiny/repaper: Drop edp->enabled In-Reply-To: <bc85bee0-9edf-7e24-9a6f-0a9ce5153fd8@tronnes.org> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-8-daniel.vetter@ffwll.ch> <bc85bee0-9edf-7e24-9a6f-0a9ce5153fd8@tronnes.org> Message-ID: <20200624071553.GQ20149@phenom.ffwll.local> On Sat, Jun 13, 2020 at 03:43:23PM +0200, Noralf Tr?nnes wrote: > > > Den 12.06.2020 18.00, skrev Daniel Vetter: > > Same patch as the mipi-dbi one, atomic tracks this for us already, we > > just have to check the right thing. > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > Cc: "Noralf Tr?nnes" <noralf at tronnes.org> > > --- > > Reviewed-by: Noralf Tr?nnes <noralf at tronnes.org> Thanks for your review, patch applied. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From sfr at canb.auug.org.au Wed Jun 24 07:16:24 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Wed, 24 Jun 2020 17:16:24 +1000 Subject: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree In-Reply-To: <CAPM=9tx5b1RaN5R4awqQ-BFpDrEZL1z05ZFv2MnGGS2t3mpBhQ@mail.gmail.com> References: <20200617105929.534edd34@canb.auug.org.au> <20200624113452.54b72fcc@canb.auug.org.au> <CAPM=9tx5b1RaN5R4awqQ-BFpDrEZL1z05ZFv2MnGGS2t3mpBhQ@mail.gmail.com> Message-ID: <20200624171624.0762edf5@canb.auug.org.au> Hi Dave, On Wed, 24 Jun 2020 15:47:49 +1000 Dave Airlie <airlied at gmail.com> wrote: > > My bad, my local builds passed, as I had made the change but forgot > the commit --amend > > Pushed out a new head with it in it now. Excellent, thanks. -- Cheers, Stephen Rothwell -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200624/c3b8e313/attachment.sig> From daniel at ffwll.ch Wed Jun 24 07:18:01 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 24 Jun 2020 09:18:01 +0200 Subject: [Intel-gfx] [PATCH 7/8] drm/mipi-dbi: Remove ->enabled In-Reply-To: <CAKMK7uFkXzMMWqaS52K6_tdi-xbsqWTySQATpJewLDL_ebXiMA@mail.gmail.com> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-7-daniel.vetter@ffwll.ch> <CACvgo51AVVOxhGK2Uin=ZLgPpihJiEsnc6pvAyKqFKPvLdOzLA@mail.gmail.com> <CAKMK7uEEkH+8BuFcFUVTv6p8swZZTwcho-HNx5GdZTO1vHDoeg@mail.gmail.com> <CACvgo51ZObyCiOeV+cdJo6xJ3ahuvBUxx1DrK+emDHTOfmVA_g@mail.gmail.com> <CAKMK7uFkXzMMWqaS52K6_tdi-xbsqWTySQATpJewLDL_ebXiMA@mail.gmail.com> Message-ID: <20200624071801.GR20149@phenom.ffwll.local> On Tue, Jun 16, 2020 at 07:16:45PM +0200, Daniel Vetter wrote: > On Tue, Jun 16, 2020 at 3:57 PM Emil Velikov <emil.l.velikov at gmail.com> wrote: > > > > On Tue, 16 Jun 2020 at 07:50, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > > > On Mon, Jun 15, 2020 at 11:35 PM Emil Velikov <emil.l.velikov at gmail.com> wrote: > > > > > > > > Hi Daniel, > > > > > > > > On Fri, 12 Jun 2020 at 17:01, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > > > > > > > > The atomic helpers try really hard to not lose track of things, > > > > > duplicating enabled tracking in the driver is at best confusing. > > > > > Double-enabling or disabling is a bug in atomic helpers. > > > > > > > > > > In the fb_dirty function we can just assume that the fb always exists, > > > > > simple display pipe helpers guarantee that the crtc is only enabled > > > > > together with the output, so we always have a primary plane around. > > > > > > > > > > Now in the update function we need to be a notch more careful, since > > > > > that can also get called when the crtc is off. And we don't want to > > > > > upload frames when that's the case, so filter that out too. > > > > > > > > > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > > > > > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > > > > Cc: Maxime Ripard <mripard at kernel.org> > > > > > Cc: Thomas Zimmermann <tzimmermann at suse.de> > > > > > Cc: David Airlie <airlied at linux.ie> > > > > > Cc: Daniel Vetter <daniel at ffwll.ch> > > > > > Cc: David Lechner <david at lechnology.com> > > > > > --- > > > > > drivers/gpu/drm/drm_mipi_dbi.c | 16 ++++++---------- > > > > > drivers/gpu/drm/tiny/ili9225.c | 12 +++--------- > > > > > drivers/gpu/drm/tiny/st7586.c | 11 +++-------- > > > > > include/drm/drm_mipi_dbi.h | 5 ----- > > > > > 4 files changed, 12 insertions(+), 32 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c > > > > > index fd8d672972a9..79532b9a324a 100644 > > > > > --- a/drivers/gpu/drm/drm_mipi_dbi.c > > > > > +++ b/drivers/gpu/drm/drm_mipi_dbi.c > > > > > @@ -268,7 +268,7 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect) > > > > > bool full; > > > > > void *tr; > > > > > > > > > > - if (!dbidev->enabled) > > > > > + if (WARN_ON(!fb)) > > > > > return; > > > > > > > > > AFAICT no other driver has such WARN_ON. Let's drop that - it is > > > > pretty confusing and misleading as-is. > > > > > > Yeah, this is a helper library which might be used wrongly by drivers. > > > That's why I put it in - if you don't put all the various calls > > > together correctly, this should at least catch one case. So really > > > would like to keep this, can I convince you? > > > > There are plenty of similar places where a drm library/helper can be > > misused, lacking a WARN. Nevertheless - sure feel free to keep it. > > Yeah I agree, we can't check for everything. Personally I think a > check is warranted in two conditions: > - drivers got it wrong, and the WARNING helps catch driver-bugs we've > seen in the wild. Not really the case here > - drivers do check something as defensive programming, but it's an > invariant enforced by higher levels or helpers. Those I like to > convert to WARNING so that other driver authors learn that this should > never happen. This is such a case imo, I removed a bunch of fb checks > from drivers here. > > But yeah I think we should only add WARNING checks if this is actually > something people have gotten wrong, otherwise there's just too many of > them, distracting from the code. Merged this patch here too, thanks everyone for reviewing. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From daniel at ffwll.ch Wed Jun 24 07:25:31 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 24 Jun 2020 09:25:31 +0200 Subject: [Intel-gfx] [PATCH 3/8] drm/imx: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-3-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-3-daniel.vetter@ffwll.ch> Message-ID: <20200624072531.GU20149@phenom.ffwll.local> On Fri, Jun 12, 2020 at 06:00:51PM +0200, Daniel Vetter wrote: > Now also comes with the added benefit of doing a drm_crtc_vblank_off(), > which means vblank state isn't ill-defined and fail-y at driver load > before the first modeset on each crtc. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Philipp Zabel <p.zabel at pengutronix.de> > Cc: Shawn Guo <shawnguo at kernel.org> > Cc: Sascha Hauer <s.hauer at pengutronix.de> > Cc: Pengutronix Kernel Team <kernel at pengutronix.de> > Cc: Fabio Estevam <festevam at gmail.com> > Cc: NXP Linux Team <linux-imx at nxp.com> > Cc: linux-arm-kernel at lists.infradead.org Ping for some ack/review on this pls. Thanks, Daniel > --- > drivers/gpu/drm/imx/ipuv3-crtc.c | 21 ++++++++------------- > 1 file changed, 8 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c > index 63c0284f8b3c..02c2f848f2d1 100644 > --- a/drivers/gpu/drm/imx/ipuv3-crtc.c > +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c > @@ -109,20 +109,15 @@ static void imx_drm_crtc_reset(struct drm_crtc *crtc) > { > struct imx_crtc_state *state; > > - if (crtc->state) { > - if (crtc->state->mode_blob) > - drm_property_blob_put(crtc->state->mode_blob); > - > - state = to_imx_crtc_state(crtc->state); > - memset(state, 0, sizeof(*state)); > - } else { > - state = kzalloc(sizeof(*state), GFP_KERNEL); > - if (!state) > - return; > - crtc->state = &state->base; > - } > + if (crtc->state) > + __drm_atomic_helper_crtc_destroy_state(crtc->state); > > - state->base.crtc = crtc; > + kfree(to_imx_crtc_state(crtc->state)); > + crtc->state = NULL; > + > + state = kzalloc(sizeof(*state), GFP_KERNEL); > + if (state) > + __drm_atomic_helper_crtc_reset(crtc, &state->base); > } > > static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc) > -- > 2.26.2 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From chris at chris-wilson.co.uk Wed Jun 24 07:43:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 08:43:23 +0100 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <a6c4e18e-7ba3-8ce7-caaf-78b3946441e6@shipmail.org> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> <a6c4e18e-7ba3-8ce7-caaf-78b3946441e6@shipmail.org> Message-ID: <159298460349.26399.12393580334647962128@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-24 08:10:43) > Hi, Maarten, > > > On 6/23/20 4:28 PM, Maarten Lankhorst wrote: > > i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory > > eviction. We don't use it yet, but lets start adding the definition > > first. > > > > To use it, we have to pass a non-NULL ww to gem_object_lock, and don't > > unlock directly. It is done in i915_gem_ww_ctx_fini. > > > > Changes since v1: > > - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) > > > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > > .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- > > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- > > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- > > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- > > drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- > > drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- > > .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ > > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- > > drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- > > .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- > > .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- > > .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- > > .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- > > .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- > > .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- > > .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > > drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- > > drivers/gpu/drm/i915/i915_gem.h | 11 ++++ > > drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ > > drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- > > .../drm/i915/selftests/intel_memory_region.c | 2 +- > > 24 files changed, 173 insertions(+), 42 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > > index b1f82a11aef2..3740c0080e38 100644 > > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > > @@ -122,6 +122,15 @@ struct drm_i915_gem_object { > > */ > > struct list_head lut_list; > > > > + /** > > + * @obj_link: Link into @i915_gem_ww_ctx.obj_list > > + * > > + * When we lock this object through i915_gem_object_lock() with a > > + * context, we add it to the list to ensure we can unlock everything > > + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. > > + */ > > + struct list_head obj_link; > > + > > Since we don't refcount objects on the list, (and we shouldn't need to), > perhaps a debug warning if during object destruction, this isn't an > empty list head? > > Other than that, this patch looks good to me. Aside it from being in the wrong layer, as was also mentioned several months ago. -Chris From thomas_os at shipmail.org Wed Jun 24 07:49:21 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Wed, 24 Jun 2020 09:49:21 +0200 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <159298460349.26399.12393580334647962128@build.alporthouse.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> <a6c4e18e-7ba3-8ce7-caaf-78b3946441e6@shipmail.org> <159298460349.26399.12393580334647962128@build.alporthouse.com> Message-ID: <05d07ef7-819a-95d1-7881-b1840a38516b@shipmail.org> Hi, Chris, On 6/24/20 9:43 AM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-24 08:10:43) >> Hi, Maarten, >> >> >> On 6/23/20 4:28 PM, Maarten Lankhorst wrote: >>> i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory >>> eviction. We don't use it yet, but lets start adding the definition >>> first. >>> >>> To use it, we have to pass a non-NULL ww to gem_object_lock, and don't >>> unlock directly. It is done in i915_gem_ww_ctx_fini. >>> >>> Changes since v1: >>> - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) >>> >>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> >>> --- >>> drivers/gpu/drm/i915/display/intel_display.c | 4 +- >>> .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- >>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- >>> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- >>> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- >>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- >>> drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- >>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- >>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ >>> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- >>> drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- >>> .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- >>> .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- >>> .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- >>> .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- >>> .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- >>> .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- >>> .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- >>> drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- >>> drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- >>> drivers/gpu/drm/i915/i915_gem.h | 11 ++++ >>> drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ >>> drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- >>> .../drm/i915/selftests/intel_memory_region.c | 2 +- >>> 24 files changed, 173 insertions(+), 42 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >>> index b1f82a11aef2..3740c0080e38 100644 >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >>> @@ -122,6 +122,15 @@ struct drm_i915_gem_object { >>> */ >>> struct list_head lut_list; >>> >>> + /** >>> + * @obj_link: Link into @i915_gem_ww_ctx.obj_list >>> + * >>> + * When we lock this object through i915_gem_object_lock() with a >>> + * context, we add it to the list to ensure we can unlock everything >>> + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. >>> + */ >>> + struct list_head obj_link; >>> + >> Since we don't refcount objects on the list, (and we shouldn't need to), >> perhaps a debug warning if during object destruction, this isn't an >> empty list head? >> >> Other than that, this patch looks good to me. > Aside it from being in the wrong layer, as was also mentioned several > months ago. > -Chris Could you send a pointer, or perhaps elaborate a bit? /Thomas From chris at chris-wilson.co.uk Wed Jun 24 08:02:48 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 09:02:48 +0100 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/gem: Use mmu_notifier_range_mayfail() to avoid waiting inside reclaim In-Reply-To: <20200624080248.3701-1-chris@chris-wilson.co.uk> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> Message-ID: <20200624080248.3701-2-chris@chris-wilson.co.uk> The direct reclaim path may trigger the mmu_notifier callback as part of try_to_unmap_one. As this is purely an opportunitistic attempt to reclaim pages, and will be called from any allocation context under unknown conditions (that include attempting to allocate pages for the userptr object itself and subsequently trying to reclaim parts of the partially acquired object) we have to be careful never to wait on anything being held by the calling context. Since that is unknown, we have to avoid waiting from inside direct reclaim. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index 9c53eb883400..72cfb91230ea 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -103,6 +103,7 @@ userptr_mn_invalidate_range_start(struct mmu_notifier *_mn, it = interval_tree_iter_first(&mn->objects, range->start, end); while (it) { struct drm_i915_gem_object *obj; + unsigned int flags; if (!mmu_notifier_range_blockable(range)) { ret = -EAGAIN; @@ -126,9 +127,12 @@ userptr_mn_invalidate_range_start(struct mmu_notifier *_mn, } spin_unlock(&mn->lock); - ret = i915_gem_object_unbind(obj, - I915_GEM_OBJECT_UNBIND_ACTIVE | - I915_GEM_OBJECT_UNBIND_BARRIER); + flags = (I915_GEM_OBJECT_UNBIND_ACTIVE | + I915_GEM_OBJECT_UNBIND_BARRIER); + if (mmu_notifier_range_mayfail(range)) + flags = 0; + + ret = i915_gem_object_unbind(obj, flags); if (ret == 0) ret = __i915_gem_object_put_pages(obj); i915_gem_object_put(obj); -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 24 08:02:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 09:02:47 +0100 Subject: [Intel-gfx] [PATCH 1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL Message-ID: <20200624080248.3701-1-chris@chris-wilson.co.uk> When direct reclaim enters the shrinker and tries to reclaim pages, it has to opportunitically unmap them [try_to_unmap_one]. For direct reclaim, the calling context is unknown and may include attempts to unmap one page of a dma object while attempting to allocate more pages for that object. Pass the information along that we are inside an opportunistic unmap that can allow that page to remain referenced and mapped, and let the callback opt in to avoiding a recursive wait. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Andrew Morton <akpm at linux-foundation.org> CC: Jason Gunthorpe <jgg at ziepe.ca> --- include/linux/mmu_notifier.h | 15 ++++++++++++++- mm/mmu_notifier.c | 3 +++ mm/rmap.c | 5 +++-- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h index fc68f3570e19..ee1ad008951c 100644 --- a/include/linux/mmu_notifier.h +++ b/include/linux/mmu_notifier.h @@ -48,7 +48,8 @@ enum mmu_notifier_event { MMU_NOTIFY_RELEASE, }; -#define MMU_NOTIFIER_RANGE_BLOCKABLE (1 << 0) +#define MMU_NOTIFIER_RANGE_BLOCKABLE BIT(0) +#define MMU_NOTIFIER_RANGE_MAYFAIL BIT(1) struct mmu_notifier_ops { /* @@ -169,6 +170,12 @@ struct mmu_notifier_ops { * a non-blocking behavior then the same applies to * invalidate_range_end. * + * If mayfail is set then the callback may return -EAGAIN while still + * holding its page references. This flag is set inside direct + * reclaim paths that are opportunistically trying to unmap pages + * from unknown contexts. The callback must be prepared to handle + * the matching invalidate_range_end even after failing the + * invalidate_range_start. */ int (*invalidate_range_start)(struct mmu_notifier *subscription, const struct mmu_notifier_range *range); @@ -397,6 +404,12 @@ mmu_notifier_range_blockable(const struct mmu_notifier_range *range) return (range->flags & MMU_NOTIFIER_RANGE_BLOCKABLE); } +static inline bool +mmu_notifier_range_mayfail(const struct mmu_notifier_range *range) +{ + return (range->flags & MMU_NOTIFIER_RANGE_MAYFAIL); +} + static inline void mmu_notifier_release(struct mm_struct *mm) { if (mm_has_notifiers(mm)) diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c index 352bb9f3ecc0..95b89cee7af4 100644 --- a/mm/mmu_notifier.c +++ b/mm/mmu_notifier.c @@ -493,6 +493,9 @@ static int mn_hlist_invalidate_range_start( _ret = ops->invalidate_range_start(subscription, range); if (!mmu_notifier_range_blockable(range)) non_block_end(); + if (_ret == -EAGAIN && + mmu_notifier_range_mayfail(range)) + _ret = 0; if (_ret) { pr_info("%pS callback failed with %d in %sblockable context.\n", ops->invalidate_range_start, _ret, diff --git a/mm/rmap.c b/mm/rmap.c index 5fe2dedce1fc..912b737a3353 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -1406,8 +1406,9 @@ static bool try_to_unmap_one(struct page *page, struct vm_area_struct *vma, * Note that the page can not be free in this function as call of * try_to_unmap() must hold a reference on the page. */ - mmu_notifier_range_init(&range, MMU_NOTIFY_CLEAR, 0, vma, vma->vm_mm, - address, + mmu_notifier_range_init(&range, + MMU_NOTIFY_CLEAR, MMU_NOTIFIER_RANGE_MAYFAIL, + vma, vma->vm_mm, address, min(vma->vm_end, address + page_size(page))); if (PageHuge(page)) { /* -- 2.20.1 From chris at chris-wilson.co.uk Wed Jun 24 08:08:27 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 09:08:27 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <ef797b36-22e9-887b-dca4-5a845c60aed7@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> <159293768060.3967.16328770521784351822@build.alporthouse.com> <88f746c6-c6ad-8c19-7797-856ac6bb2f50@shipmail.org> <159294690652.3967.16801810632630360943@build.alporthouse.com> <ef797b36-22e9-887b-dca4-5a845c60aed7@shipmail.org> Message-ID: <159298610762.26399.7546337779632693043@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-24 06:42:33) > > On 6/23/20 11:15 PM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 21:31:38) > >> On 6/23/20 8:41 PM, Chris Wilson wrote: > >>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 19:21:28) > >>>> On 6/23/20 6:36 PM, Chris Wilson wrote: > >>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) > >>>>>> Hi, Chris, > >>>>>> > >>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>>>>>> In order to actually handle eviction and what not, we need to process > >>>>>>> all the objects together under a common lock, reservation_ww_class. As > >>>>>>> such, do a memory reservation pass after looking up the object/vma, > >>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>>>>>> flushing and ofc execution]. > >>>>>>> > >>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>>>>>> --- > >>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>>>>>> > >>>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>>>> index 46fcbdf8161c..8db2e013465f 100644 > >>>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>>>> @@ -53,10 +53,9 @@ struct eb_vma_array { > >>>>>>> > >>>>>>> #define __EXEC_OBJECT_HAS_PIN BIT(31) > >>>>>>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) > >>>>>>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) > >>>>>>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) > >>>>>>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) > >>>>>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ > >>>>>>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) > >>>>>>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) > >>>>>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ > >>>>>>> > >>>>>>> #define __EXEC_HAS_RELOC BIT(31) > >>>>>>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) > >>>>>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { > >>>>>>> struct intel_context *context; /* logical state for the request */ > >>>>>>> struct i915_gem_context *gem_context; /** caller's context */ > >>>>>>> > >>>>>>> + struct dma_fence *mm_fence; > >>>>>>> + > >>>>>>> struct i915_request *request; /** our request to build */ > >>>>>>> struct eb_vma *batch; /** identity of the batch obj/vma */ > >>>>>>> struct i915_vma *trampoline; /** trampoline used for chaining */ > >>>>>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) > >>>>>>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) > >>>>>>> __i915_vma_unpin(vma); > >>>>>>> > >>>>>>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > >>>>>>> - i915_gem_object_unpin_pages(vma->obj); > >>>>>>> - > >>>>>>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > >>>>>>> - __EXEC_OBJECT_HAS_FENCE | > >>>>>>> - __EXEC_OBJECT_HAS_PAGES); > >>>>>>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > >>>>>>> } > >>>>>>> > >>>>>>> static void eb_vma_array_destroy(struct kref *kref) > >>>>>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > >>>>>>> list_add_tail(&ev->lock_link, &eb->lock); > >>>>>>> } > >>>>>>> > >>>>>>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, > >>>>>>> + struct eb_vma *ev, > >>>>>>> + u64 idx) > >>>>>>> +{ > >>>>>>> + struct i915_vma *vma = ev->vma; > >>>>>>> + int err; > >>>>>>> + > >>>>>>> + /* XXX also preallocate PD for vma */ > >>>>>>> + > >>>>>>> + err = ____i915_gem_object_get_pages_async(vma->obj); > >>>>>>> + if (err) > >>>>>>> + return err; > >>>>>>> + > >>>>>>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > >>>>>>> +} > >>>>>>> + > >>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>>>>>> +{ > >>>>>>> + const u64 idx = eb->context->timeline->fence_context; > >>>>>>> + struct ww_acquire_ctx acquire; > >>>>>>> + struct eb_vma *ev; > >>>>>>> + int err; > >>>>>>> + > >>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>>>>>> + if (!eb->mm_fence) > >>>>>>> + return -ENOMEM; > >>>>>> Question: eb is local to this thread, right, so eb->mm_fence is not > >>>>>> considered "published" yet? > >>>>>> > >>>>>>> + > >>>>>>> + ww_acquire_init(&acquire, &reservation_ww_class); > >>>>>>> + > >>>>>>> + err = eb_lock_vma(eb, &acquire); > >>>>>>> + if (err) > >>>>>>> + goto out; > >>>>>>> + > >>>>>>> + ww_acquire_done(&acquire); > >>>>>>> + > >>>>>>> + list_for_each_entry(ev, &eb->lock, lock_link) { > >>>>>>> + struct i915_vma *vma = ev->vma; > >>>>>>> + > >>>>>>> + if (err == 0) > >>>>>>> + err = eb_vma_get_pages(eb, ev, idx); > >>>>>> I figure this is where you publish the proxy fence? If so, the fence > >>>>>> signaling critical path starts with this loop, > >>>>> Hmm, actually at this moment, the fence is still very much internal > >>>>> being only used as a reference token, > >>>> I think as long as another thread, running in this driver or another gpu > >>>> driver can theoretically reference the fence pointer from the > >>>> reservation object and wait for the fence it's considered published. > >>> It's not in the reservation object. > >>> > >>>> Also the ww_mutexes in this context are really all about grabbing a > >>>> random set of resources and associate them with a point in a timeline, > >>>> as the ww_mutexes are released, the fence pointer(s) need to point to > >>>> published fence(s). > >>> That's not the purpose of these fences, though. They exist to provide > >>> reference counting on the backing store, along side the migration fence. > >>> It's extra detail tacked on the equivalent of bo->moving. > >>> > >>> That is not to say that one could build up an async migration chain which > >>> form a graph back to these, that chain could only be formed once the > >>> operation itself has been published in the dma_resv though. > >> Hmm. So let's say another thread grabs one of the just released > >> ww_mutexes and wants to schedule a blit from one of the buffers in the > >> current operation with high priority. How would that thread know how to > >> order that blit operation w r t the current operation? > > Why would it order? > So let's say it's an eviction blit, needing to incorporate the data from > the current operation. Or, for that matter a ttm-style cpu copy eviction: > > ww_mutex_lock > wait_for_idle > copy > ww_mutex_unlock We have a scheduler. Eviction does not block. Submission never blocks. lock swap allocation blocks unlock copy. -Chris From chris at chris-wilson.co.uk Wed Jun 24 08:27:01 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 09:27:01 +0100 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <05d07ef7-819a-95d1-7881-b1840a38516b@shipmail.org> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> <a6c4e18e-7ba3-8ce7-caaf-78b3946441e6@shipmail.org> <159298460349.26399.12393580334647962128@build.alporthouse.com> <05d07ef7-819a-95d1-7881-b1840a38516b@shipmail.org> Message-ID: <159298722115.26399.16332765813318015395@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-24 08:49:21) > Hi, Chris, > > On 6/24/20 9:43 AM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-24 08:10:43) > >> Hi, Maarten, > >> > >> > >> On 6/23/20 4:28 PM, Maarten Lankhorst wrote: > >>> i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory > >>> eviction. We don't use it yet, but lets start adding the definition > >>> first. > >>> > >>> To use it, we have to pass a non-NULL ww to gem_object_lock, and don't > >>> unlock directly. It is done in i915_gem_ww_ctx_fini. > >>> > >>> Changes since v1: > >>> - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) > >>> > >>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > >>> --- > >>> drivers/gpu/drm/i915/display/intel_display.c | 4 +- > >>> .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- > >>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- > >>> drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- > >>> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- > >>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- > >>> drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- > >>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- > >>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ > >>> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- > >>> drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- > >>> .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- > >>> .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- > >>> .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- > >>> .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- > >>> .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- > >>> .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- > >>> .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- > >>> drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > >>> drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- > >>> drivers/gpu/drm/i915/i915_gem.h | 11 ++++ > >>> drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ > >>> drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- > >>> .../drm/i915/selftests/intel_memory_region.c | 2 +- > >>> 24 files changed, 173 insertions(+), 42 deletions(-) > >>> > >>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > >>> index b1f82a11aef2..3740c0080e38 100644 > >>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > >>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > >>> @@ -122,6 +122,15 @@ struct drm_i915_gem_object { > >>> */ > >>> struct list_head lut_list; > >>> > >>> + /** > >>> + * @obj_link: Link into @i915_gem_ww_ctx.obj_list > >>> + * > >>> + * When we lock this object through i915_gem_object_lock() with a > >>> + * context, we add it to the list to ensure we can unlock everything > >>> + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. > >>> + */ > >>> + struct list_head obj_link; > >>> + > >> Since we don't refcount objects on the list, (and we shouldn't need to), > >> perhaps a debug warning if during object destruction, this isn't an > >> empty list head? > >> > >> Other than that, this patch looks good to me. > > Aside it from being in the wrong layer, as was also mentioned several > > months ago. > > -Chris > > Could you send a pointer, or perhaps elaborate a bit? We have been trying to extricate the GEM uAPI layer and objects from the memory management of the backing store with a view to bypassing the implicit rules imposed by GEM, and to remove the layering violation of the HW layer calling back into the upper API layer. For the moment the distinction is "should this be obj or obj->mm". Some might have been arguing for obj->mm to become its backing store object, [and had hoped ttm would have been usable for managing it] for we will have i915_vma that do not [need to] refer to GEM objects. Aside from first class user i915_vma, we also need to allocate PD as some sort of highly restricted object (and often tiny, so suballocations). And everything needs a severe diet. -Chris From maxime at cerno.tech Wed Jun 24 08:49:09 2020 From: maxime at cerno.tech (Maxime Ripard) Date: Wed, 24 Jun 2020 10:49:09 +0200 Subject: [Intel-gfx] [PATCH 5/8] drm/vc4: Use __drm_atomic_helper_crtc_reset In-Reply-To: <20200612160056.2082681-5-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> <20200612160056.2082681-5-daniel.vetter@ffwll.ch> Message-ID: <20200624084909.2vzvv3c7eqnarbko@gilmour.lan> On Fri, Jun 12, 2020 at 06:00:53PM +0200, Daniel Vetter wrote: > Now also comes with the added benefit of doing a drm_crtc_vblank_off(), > which means vblank state isn't ill-defined and fail-y at driver load > before the first modeset on each crtc. > > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> > Cc: Eric Anholt <eric at anholt.net> Reviewed-by: Maxime Ripard <mripard at kernel.org> Maxime From imre.deak at intel.com Wed Jun 24 09:06:10 2020 From: imre.deak at intel.com (Imre Deak) Date: Wed, 24 Jun 2020 12:06:10 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/dp=5Fmst=3A_Enable_VC_payload_allocation_after_transcoder?= =?utf-8?q?_is_enabled?= In-Reply-To: <159291648828.4210.6579151037024071394@emeril.freedesktop.org> References: <20200623082411.3889-1-imre.deak@intel.com> <159291648828.4210.6579151037024071394@emeril.freedesktop.org> Message-ID: <20200624090610.GA7080@ideak-desk.fi.intel.com> On Tue, Jun 23, 2020 at 12:48:08PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/dp_mst: Enable VC payload allocation after transcoder is enabled > URL : https://patchwork.freedesktop.org/series/78728/ > State : success Thanks for the review, patch pushed to -dinq. > > == Summary == > > CI Bug Log - changes from CI_DRM_8655_full -> Patchwork_18009_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_18009_full: > > ### Piglit changes ### > > #### Possible regressions #### > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2 (NEW): > - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] +7 similar issues > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2.html > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2 (NEW): > - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] +2 similar issues > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/pig-icl-1065g7/spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2.html > > > New tests > --------- > > New tests have been introduced between CI_DRM_8655_full and Patchwork_18009_full: > > ### New Piglit tests (11) ### > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-double_dmat3_array3-position-double_dmat3x4_array2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3-int_ivec3_array3: > - Statuses : 1 crash(s) > - Exec time: [1.00] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dmat3x2_array3-double_dmat3x2_array2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-double_dvec3-float_mat4x2_array3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-float_mat4x2_array3-double_dmat3x2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-int_ivec2-double_dmat3x4: > - Statuses : 1 crash(s) > - Exec time: [0.84] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-ubyte_uint-short_ivec4-double_dmat2: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-position-uint_uvec2_array3-double_dvec3_array2: > - Statuses : 1 crash(s) > - Exec time: [0.92] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-ubyte_uvec2-short_int-position-double_dmat2x4: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > * spec at arb_vertex_attrib_64bit@execution at vs_in@vs-input-uint_uint_array3-position-double_dmat4x3: > - Statuses : 1 incomplete(s) > - Exec time: [0.0] s > > > > Known issues > ------------ > > Here are the changes found in Patchwork_18009_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_isolation@preservation-s3 at vecs0: > - shard-glk: [PASS][3] -> [INCOMPLETE][4] ([i915#58] / [k.org#198133]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk1/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk8/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > > * igt at gem_exec_schedule@smoketest-all: > - shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95]) +1 similar issue > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at gem_exec_schedule@smoketest-all.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at gem_exec_schedule@smoketest-all.html > > * igt at gem_vm_create@isolation: > - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#1635] / [i915#95]) +16 similar issues > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl6/igt at gem_vm_create@isolation.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at gem_vm_create@isolation.html > > * igt at gen9_exec_parse@allowed-all: > - shard-skl: [PASS][9] -> [DMESG-WARN][10] ([i915#1436] / [i915#716]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at gen9_exec_parse@allowed-all.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl2/igt at gen9_exec_parse@allowed-all.html > - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1436] / [i915#716]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at gen9_exec_parse@allowed-all.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at gen9_exec_parse@allowed-all.html > > * igt at i915_suspend@forcewake: > - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([i915#636] / [i915#69]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at i915_suspend@forcewake.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at i915_suspend@forcewake.html > > * igt at kms_big_fb@x-tiled-8bpp-rotate-180: > - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl4/igt at kms_big_fb@x-tiled-8bpp-rotate-180.html > > * igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge: > - shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk6/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at kms_cursor_edge_walk@pipe-c-256x256-right-edge.html > > * igt at kms_flip@flip-vs-suspend-interruptible at c-dp1: > - shard-kbl: [PASS][19] -> [INCOMPLETE][20] ([i915#636]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at c-dp1.html > > * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu: > - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-rte: > - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-rte.html > > * igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a: > - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#93] / [i915#95]) +1 similar issue > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl3/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_pipe_crc_basic@nonblocking-crc-pipe-a.html > > * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: > - shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([i915#180]) +7 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_plane_cursor@pipe-b-viewport-size-128: > - shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +13 similar issues > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl7/igt at kms_plane_cursor@pipe-b-viewport-size-128.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl8/igt at kms_plane_cursor@pipe-b-viewport-size-128.html > > * igt at kms_plane_lowres@pipe-a-tiling-none: > - shard-glk: [PASS][33] -> [FAIL][34] ([i915#899]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_plane_lowres@pipe-a-tiling-none.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk7/igt at kms_plane_lowres@pipe-a-tiling-none.html > > * igt at perf@blocking-parameterized: > - shard-iclb: [PASS][35] -> [FAIL][36] ([i915#1542]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-iclb4/igt at perf@blocking-parameterized.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-iclb3/igt at perf@blocking-parameterized.html > > > #### Possible fixes #### > > * igt at gem_eio@kms: > - shard-kbl: [DMESG-WARN][37] ([i915#93] / [i915#95]) -> [PASS][38] > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at gem_eio@kms.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at gem_eio@kms.html > > * igt at gem_exec_whisper@basic-queues-forked-all: > - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk7/igt at gem_exec_whisper@basic-queues-forked-all.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk2/igt at gem_exec_whisper@basic-queues-forked-all.html > > * igt at kms_big_fb@linear-32bpp-rotate-180: > - shard-apl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_big_fb@linear-32bpp-rotate-180.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl1/igt at kms_big_fb@linear-32bpp-rotate-180.html > > * igt at kms_big_fb@x-tiled-64bpp-rotate-0: > - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk5/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html > > * igt at kms_big_fb@yf-tiled-32bpp-rotate-270: > - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +5 similar issues > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl3/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl10/igt at kms_big_fb@yf-tiled-32bpp-rotate-270.html > > * igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1: > - shard-glk: [FAIL][47] ([i915#46]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-glk9/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-glk1/igt at kms_flip@flip-vs-expired-vblank at a-hdmi-a1.html > > * igt at kms_flip@flip-vs-suspend at c-dp1: > - shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl1/igt at kms_flip@flip-vs-suspend at c-dp1.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html > > * igt at kms_flip_tiling@flip-changes-tiling-y: > - shard-skl: [FAIL][51] ([i915#699]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-changes-tiling-y.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-changes-tiling-y.html > > * igt at kms_flip_tiling@flip-to-x-tiled: > - shard-skl: [FAIL][53] ([i915#167]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_flip_tiling@flip-to-x-tiled.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_flip_tiling@flip-to-x-tiled.html > > * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render: > - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html > > * igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt: > - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-tglb7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html > > * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: > - shard-skl: [FAIL][59] ([i915#49]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl4/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_pipe_crc_basic@read-crc-pipe-a: > - shard-skl: [FAIL][63] ([i915#53]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl9/igt at kms_pipe_crc_basic@read-crc-pipe-a.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl3/igt at kms_pipe_crc_basic@read-crc-pipe-a.html > > * igt at kms_plane_multiple@atomic-pipe-b-tiling-yf: > - shard-kbl: [FAIL][65] ([i915#1779]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-kbl4/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-kbl6/igt at kms_plane_multiple@atomic-pipe-b-tiling-yf.html > > * igt at vgem_slow@nohang: > - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +11 similar issues > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at vgem_slow@nohang.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at vgem_slow@nohang.html > > > #### Warnings #### > > * igt at gem_exec_reloc@basic-concurrent16: > - shard-snb: [FAIL][69] ([i915#1930]) -> [TIMEOUT][70] ([i915#1958]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at gem_exec_reloc@basic-concurrent16.html > > * igt at i915_pm_rpm@gem-execbuf-stress-pc8: > - shard-apl: [SKIP][71] ([fdo#109271] / [i915#1635]) -> [SKIP][72] ([fdo#109271]) +4 similar issues > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl8/igt at i915_pm_rpm@gem-execbuf-stress-pc8.html > > * igt at kms_chamelium@dp-crc-multiple: > - shard-apl: [SKIP][73] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl7/igt at kms_chamelium@dp-crc-multiple.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl3/igt at kms_chamelium@dp-crc-multiple.html > > * igt at kms_chamelium@vga-hpd: > - shard-apl: [SKIP][75] ([fdo#109271] / [fdo#111827]) -> [SKIP][76] ([fdo#109271] / [fdo#111827] / [i915#1635]) +2 similar issues > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_chamelium@vga-hpd.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_chamelium@vga-hpd.html > > * igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled: > - shard-snb: [SKIP][77] ([fdo#109271]) -> [TIMEOUT][78] ([i915#1958]) +5 similar issues > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-snb2/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-snb1/igt at kms_draw_crc@draw-method-xrgb2101010-render-ytiled.html > > * igt at kms_flip@flip-vs-expired-vblank at a-edp1: > - shard-skl: [DMESG-WARN][79] ([i915#1982]) -> [DMESG-FAIL][80] ([i915#1982] / [i915#79]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at a-edp1.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render: > - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +6 similar issues > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-apl7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [DMESG-FAIL][83] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][84] ([i915#1982]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8655/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#167]: https://gitlab.freedesktop.org/drm/intel/issues/167 > [i915#1779]: https://gitlab.freedesktop.org/drm/intel/issues/1779 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 > [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 > [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8655 -> Patchwork_18009 > > CI-20190529: 20190529 > CI_DRM_8655: 25d43cec6c2200a9ebe8a8b0923b27b164a6f424 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5716: 71a22c37ae6541f9d991d81f15cbade1da402b75 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18009: c95fdf71011e7df7708cea81e3736b24fb8f5189 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18009/index.html From patchwork at emeril.freedesktop.org Wed Jun 24 09:37:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 09:37:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/2=5D_drm/i915/display/rkl=3A_Impl?= =?utf-8?q?ement_WA_14011471926?= In-Reply-To: <20200623215235.125665-1-jose.souza@intel.com> References: <20200623215235.125665-1-jose.souza@intel.com> Message-ID: <159299145308.19236.8153963028621366171@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/display/rkl: Implement WA 14011471926 URL : https://patchwork.freedesktop.org/series/78761/ State : warning == Summary == $ dim checkpatch origin/drm-tip bd24ac2db018 drm/i915/display/rkl: Implement WA 14011471926 3ac2f590c2c8 drm/i915/display: Rename COMP_INIT to CNL_PORT_COMP_DW0_COMP_INIT fe2335f73891 drm/i915/display: Implement new combo phy initialization step -:78: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #78: FILE: drivers/gpu/drm/i915/i915_reg.h:2091: +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) total: 0 errors, 1 warnings, 0 checks, 56 lines checked From maxime at cerno.tech Wed Jun 24 09:42:03 2020 From: maxime at cerno.tech (Maxime Ripard) Date: Wed, 24 Jun 2020 11:42:03 +0200 Subject: [Intel-gfx] [PATCH 1/8] drm/atomic-helper: reset vblank on crtc reset In-Reply-To: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> References: <20200612160056.2082681-1-daniel.vetter@ffwll.ch> Message-ID: <20200624094203.5dw267lb4c7ongvy@gilmour.lan> On Fri, Jun 12, 2020 at 06:00:49PM +0200, Daniel Vetter wrote: > Only when vblanks are supported ofc. > > Some drivers do this already, but most unfortunately missed it. This > opens up bugs after driver load, before the crtc is enabled for the > first time. syzbot spotted this when loading vkms as a secondary > output. Given how many drivers are buggy it's best to solve this once > and for all in shared helper code. > > Aside from moving the few existing calls to drm_crtc_vblank_reset into > helpers (i915 doesn't use helpers, so keeps its own) I think the > regression risk is minimal: atomic helpers already rely on drivers > calling drm_crtc_vblank_on/off correctly in their hooks when they > support vblanks. And driver that's failing to handle vblanks after > this is missing those calls already, and vblanks could only work by > accident when enabling a CRTC for the first time right after boot. > > Big thanks to Tetsuo for helping track down what's going wrong here. > > There's only a few drivers which already had the necessary call and > needed some updating: > - komeda, atmel and tidss also needed to be changed to call > __drm_atomic_helper_crtc_reset() intead of open coding it > - tegra and msm even had it in the same place already, just code > motion, and malidp already uses __drm_atomic_helper_crtc_reset(). > > Only call left is in i915, which doesn't use drm_mode_config_reset, > but has its own fastboot infrastructure. So that's the only case where > we actually want this in the driver still. > > I've also reviewed all other drivers which set up vblank support with > drm_vblank_init. After the previous patch fixing mxsfb all atomic > drivers do call drm_crtc_vblank_on/off as they should, the remaining > drivers are either legacy kms or legacy dri1 drivers, so not affected > by this change to atomic helpers. > > v2: Use the drm_dev_has_vblank() helper. > > v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off > instead of drm_crtc_vblank_reset. Adjust them too. > > v4: Laurent noticed that rcar-du and omap open-code their crtc reset > and hence would actually be broken by this patch now. So fix them up > by reusing the helpers, which brings the drm_crtc_vblank_reset() back. > > Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com> > Reviewed-by: Boris Brezillon <boris.brezillon at collabora.com> > Acked-by: Liviu Dudau <liviu.dudau at arm.com> > Acked-by: Thierry Reding <treding at nvidia.com> > Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb > Reported-by: Tetsuo Handa <penguin-kernel at I-love.SAKURA.ne.jp> > Reported-by: syzbot+0871b14ca2e2fb64f6e3 at syzkaller.appspotmail.com > Cc: Tetsuo Handa <penguin-kernel at I-love.SAKURA.ne.jp> > Cc: "James (Qian) Wang" <james.qian.wang at arm.com> > Cc: Liviu Dudau <liviu.dudau at arm.com> > Cc: Mihail Atanassov <mihail.atanassov at arm.com> > Cc: Brian Starkey <brian.starkey at arm.com> > Cc: Sam Ravnborg <sam at ravnborg.org> > Cc: Boris Brezillon <bbrezillon at kernel.org> > Cc: Nicolas Ferre <nicolas.ferre at microchip.com> > Cc: Alexandre Belloni <alexandre.belloni at bootlin.com> > Cc: Ludovic Desroches <ludovic.desroches at microchip.com> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Cc: Maxime Ripard <mripard at kernel.org> > Cc: Thomas Zimmermann <tzimmermann at suse.de> > Cc: David Airlie <airlied at linux.ie> > Cc: Daniel Vetter <daniel at ffwll.ch> > Cc: Thierry Reding <thierry.reding at gmail.com> > Cc: Jonathan Hunter <jonathanh at nvidia.com> > Cc: Jyri Sarha <jsarha at ti.com> > Cc: Tomi Valkeinen <tomi.valkeinen at ti.com> > Cc: Rob Clark <robdclark at gmail.com> > Cc: Sean Paul <seanpaul at chromium.org> > Cc: Brian Masney <masneyb at onstation.org> > Cc: Emil Velikov <emil.velikov at collabora.com> > Cc: zhengbin <zhengbin13 at huawei.com> > Cc: Thomas Gleixner <tglx at linutronix.de> > Cc: linux-tegra at vger.kernel.org > Cc: Kieran Bingham <kieran.bingham+renesas at ideasonboard.com> > Cc: linux-arm-kernel at lists.infradead.org > Cc: linux-renesas-soc at vger.kernel.org > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> Acked-by: Maxime Ripard <mripard at kernel.org> Maxime From thomas_os at shipmail.org Wed Jun 24 09:50:08 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Wed, 24 Jun 2020 11:50:08 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159298610762.26399.7546337779632693043@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> <159293768060.3967.16328770521784351822@build.alporthouse.com> <88f746c6-c6ad-8c19-7797-856ac6bb2f50@shipmail.org> <159294690652.3967.16801810632630360943@build.alporthouse.com> <ef797b36-22e9-887b-dca4-5a845c60aed7@shipmail.org> <159298610762.26399.7546337779632693043@build.alporthouse.com> Message-ID: <5c3295d2-2527-0b0f-8aed-2489204c2722@shipmail.org> On 6/24/20 10:08 AM, Chris Wilson wrote: > Quoting Thomas Hellstr?m (Intel) (2020-06-24 06:42:33) >> On 6/23/20 11:15 PM, Chris Wilson wrote: >>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 21:31:38) >>>> On 6/23/20 8:41 PM, Chris Wilson wrote: >>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 19:21:28) >>>>>> On 6/23/20 6:36 PM, Chris Wilson wrote: >>>>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) >>>>>>>> Hi, Chris, >>>>>>>> >>>>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: >>>>>>>>> In order to actually handle eviction and what not, we need to process >>>>>>>>> all the objects together under a common lock, reservation_ww_class. As >>>>>>>>> such, do a memory reservation pass after looking up the object/vma, >>>>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>>>>>>>> flushing and ofc execution]. >>>>>>>>> >>>>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>>>>>>>> --- >>>>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>>>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) >>>>>>>>> >>>>>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>>>>>> index 46fcbdf8161c..8db2e013465f 100644 >>>>>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >>>>>>>>> @@ -53,10 +53,9 @@ struct eb_vma_array { >>>>>>>>> >>>>>>>>> #define __EXEC_OBJECT_HAS_PIN BIT(31) >>>>>>>>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) >>>>>>>>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) >>>>>>>>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) >>>>>>>>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) >>>>>>>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ >>>>>>>>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) >>>>>>>>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) >>>>>>>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ >>>>>>>>> >>>>>>>>> #define __EXEC_HAS_RELOC BIT(31) >>>>>>>>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) >>>>>>>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { >>>>>>>>> struct intel_context *context; /* logical state for the request */ >>>>>>>>> struct i915_gem_context *gem_context; /** caller's context */ >>>>>>>>> >>>>>>>>> + struct dma_fence *mm_fence; >>>>>>>>> + >>>>>>>>> struct i915_request *request; /** our request to build */ >>>>>>>>> struct eb_vma *batch; /** identity of the batch obj/vma */ >>>>>>>>> struct i915_vma *trampoline; /** trampoline used for chaining */ >>>>>>>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) >>>>>>>>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) >>>>>>>>> __i915_vma_unpin(vma); >>>>>>>>> >>>>>>>>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) >>>>>>>>> - i915_gem_object_unpin_pages(vma->obj); >>>>>>>>> - >>>>>>>>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | >>>>>>>>> - __EXEC_OBJECT_HAS_FENCE | >>>>>>>>> - __EXEC_OBJECT_HAS_PAGES); >>>>>>>>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); >>>>>>>>> } >>>>>>>>> >>>>>>>>> static void eb_vma_array_destroy(struct kref *kref) >>>>>>>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, >>>>>>>>> list_add_tail(&ev->lock_link, &eb->lock); >>>>>>>>> } >>>>>>>>> >>>>>>>>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, >>>>>>>>> + struct eb_vma *ev, >>>>>>>>> + u64 idx) >>>>>>>>> +{ >>>>>>>>> + struct i915_vma *vma = ev->vma; >>>>>>>>> + int err; >>>>>>>>> + >>>>>>>>> + /* XXX also preallocate PD for vma */ >>>>>>>>> + >>>>>>>>> + err = ____i915_gem_object_get_pages_async(vma->obj); >>>>>>>>> + if (err) >>>>>>>>> + return err; >>>>>>>>> + >>>>>>>>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); >>>>>>>>> +} >>>>>>>>> + >>>>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>>>>>>>> +{ >>>>>>>>> + const u64 idx = eb->context->timeline->fence_context; >>>>>>>>> + struct ww_acquire_ctx acquire; >>>>>>>>> + struct eb_vma *ev; >>>>>>>>> + int err; >>>>>>>>> + >>>>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); >>>>>>>>> + if (!eb->mm_fence) >>>>>>>>> + return -ENOMEM; >>>>>>>> Question: eb is local to this thread, right, so eb->mm_fence is not >>>>>>>> considered "published" yet? >>>>>>>> >>>>>>>>> + >>>>>>>>> + ww_acquire_init(&acquire, &reservation_ww_class); >>>>>>>>> + >>>>>>>>> + err = eb_lock_vma(eb, &acquire); >>>>>>>>> + if (err) >>>>>>>>> + goto out; >>>>>>>>> + >>>>>>>>> + ww_acquire_done(&acquire); >>>>>>>>> + >>>>>>>>> + list_for_each_entry(ev, &eb->lock, lock_link) { >>>>>>>>> + struct i915_vma *vma = ev->vma; >>>>>>>>> + >>>>>>>>> + if (err == 0) >>>>>>>>> + err = eb_vma_get_pages(eb, ev, idx); >>>>>>>> I figure this is where you publish the proxy fence? If so, the fence >>>>>>>> signaling critical path starts with this loop, >>>>>>> Hmm, actually at this moment, the fence is still very much internal >>>>>>> being only used as a reference token, >>>>>> I think as long as another thread, running in this driver or another gpu >>>>>> driver can theoretically reference the fence pointer from the >>>>>> reservation object and wait for the fence it's considered published. >>>>> It's not in the reservation object. >>>>> >>>>>> Also the ww_mutexes in this context are really all about grabbing a >>>>>> random set of resources and associate them with a point in a timeline, >>>>>> as the ww_mutexes are released, the fence pointer(s) need to point to >>>>>> published fence(s). >>>>> That's not the purpose of these fences, though. They exist to provide >>>>> reference counting on the backing store, along side the migration fence. >>>>> It's extra detail tacked on the equivalent of bo->moving. >>>>> >>>>> That is not to say that one could build up an async migration chain which >>>>> form a graph back to these, that chain could only be formed once the >>>>> operation itself has been published in the dma_resv though. >>>> Hmm. So let's say another thread grabs one of the just released >>>> ww_mutexes and wants to schedule a blit from one of the buffers in the >>>> current operation with high priority. How would that thread know how to >>>> order that blit operation w r t the current operation? >>> Why would it order? >> So let's say it's an eviction blit, needing to incorporate the data from >> the current operation. Or, for that matter a ttm-style cpu copy eviction: >> >> ww_mutex_lock >> wait_for_idle >> copy >> ww_mutex_unlock > We have a scheduler. Eviction does not block. Submission never blocks. So regardless if we block or not, how does the scheduler know how to order the eviction blit after the current operation? Wouldn't it need to look at the proxy fence to determine that? Basically I'm trying to get an understanding where the fence signaling critical section starts. /Thomas From melissa.srw at gmail.com Wed Jun 24 09:54:00 2020 From: melissa.srw at gmail.com (Melissa Wen) Date: Wed, 24 Jun 2020 06:54:00 -0300 Subject: [Intel-gfx] [PATCH i-g-t 0/2] minor improvements to the kms_cursor_crc doc and some comments cleanup Message-ID: <cover.1592991729.git.melissa.srw@gmail.com> Hi, I was studying the code of kms_cursor_crc test, and I just adjusted some comments and added descriptions for subtests. Melissa Wen (2): lib/igt_fb: change comments with fd description test/kms_cursor_crc: update subtests descriptions and some comments lib/igt_fb.c | 6 +++--- tests/kms_cursor_crc.c | 38 ++++++++++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 13 deletions(-) -- 2.27.0 From melissa.srw at gmail.com Wed Jun 24 09:54:41 2020 From: melissa.srw at gmail.com (Melissa Wen) Date: Wed, 24 Jun 2020 06:54:41 -0300 Subject: [Intel-gfx] [PATCH i-g-t 1/2] lib/igt_fb: change comments with fd description In-Reply-To: <cover.1592991729.git.melissa.srw@gmail.com> References: <cover.1592991729.git.melissa.srw@gmail.com> Message-ID: <3c0e76d37030f0d08fff3d8b424be8b8efa40955.1592991729.git.melissa.srw@gmail.com> Generalize description of fd so as not restrict it to i915 driver Signed-off-by: Melissa Wen <melissa.srw at gmail.com> --- lib/igt_fb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 5ed586e7..5a219c57 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -3548,7 +3548,7 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb) /** * igt_get_cairo_ctx: - * @fd: open i915 drm file descriptor + * @fd: open drm file descriptor * @fb: pointer to an #igt_fb structure * * This initializes a cairo surface for @fb and then allocates a drawing context @@ -3578,7 +3578,7 @@ cairo_t *igt_get_cairo_ctx(int fd, struct igt_fb *fb) /** * igt_put_cairo_ctx: - * @fd: open i915 drm file descriptor + * @fd: open drm file descriptor * @fb: pointer to an #igt_fb structure * @cr: the cairo context returned by igt_get_cairo_ctx. * @@ -3596,7 +3596,7 @@ void igt_put_cairo_ctx(int fd, struct igt_fb *fb, cairo_t *cr) /** * igt_remove_fb: - * @fd: open i915 drm file descriptor + * @fd: open drm file descriptor * @fb: pointer to an #igt_fb structure * * This function releases all resources allocated in igt_create_fb() for @fb. -- 2.27.0 From melissa.srw at gmail.com Wed Jun 24 09:55:10 2020 From: melissa.srw at gmail.com (Melissa Wen) Date: Wed, 24 Jun 2020 06:55:10 -0300 Subject: [Intel-gfx] [PATCH i-g-t 2/2] test/kms_cursor_crc: update subtests descriptions and some comments In-Reply-To: <cover.1592991729.git.melissa.srw@gmail.com> References: <cover.1592991729.git.melissa.srw@gmail.com> Message-ID: <e1b9c469820c9625b0723680b76784f312564b4e.1592991729.git.melissa.srw@gmail.com> Add descriptions for some subtests and detail a little more the comments in test_cursor_alpha. Signed-off-by: Melissa Wen <melissa.srw at gmail.com> --- tests/kms_cursor_crc.c | 38 ++++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index f105e295..4dba1471 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -31,12 +31,13 @@ IGT_TEST_DESCRIPTION( - "Use the display CRC support to validate cursor plane functionality. " - "The test will position the cursor plane either fully onscreen, " - "partially onscreen, or fully offscreen, using either a fully opaque " - "or fully transparent surface. In each case it then reads the PF CRC " - "and compares it with the CRC value obtained when the cursor plane " - "was disabled."); + "Use the display CRC support to validate cursor plane functionality. "\ + "The test will position the cursor plane either fully onscreen, "\ + "partially onscreen, or fully offscreen, using either a fully opaque "\ + "or fully transparent surface. In each case, it enables the cursor plane "\ + "and then reads the PF CRC (hardware test) and compares it with the CRC "\ + "value obtained when the cursor plane was disabled and its drawing is " + "directly inserted on the PF by software."); #ifndef DRM_CAP_CURSOR_WIDTH #define DRM_CAP_CURSOR_WIDTH 0x8 @@ -485,7 +486,7 @@ static void test_cursor_alpha(data_t *data, double a) int curw = data->curw; int curh = data->curh; - /*alpha cursor fb*/ + /*Alpha cursor fb with white color*/ fb_id = igt_create_fb(data->drm_fd, curw, curh, DRM_FORMAT_ARGB8888, LOCAL_DRM_FORMAT_MOD_NONE, @@ -495,22 +496,24 @@ static void test_cursor_alpha(data_t *data, double a) igt_paint_color_alpha(cr, 0, 0, curw, curh, 1.0, 1.0, 1.0, a); igt_put_cairo_ctx(data->drm_fd, &data->fb, cr); - /*Hardware Test*/ + /*Hardware Test - enable cursor and get PF CRC*/ cursor_enable(data); igt_display_commit(display); igt_wait_for_vblank(data->drm_fd, data->pipe); igt_pipe_crc_get_current(data->drm_fd, pipe_crc, &crc); + cursor_disable(data); igt_remove_fb(data->drm_fd, &data->fb); - /*Software Test*/ + /*Software Test - render cursor in software, drawn it directly on PF*/ cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER]); igt_paint_color_alpha(cr, 0, 0, curw, curh, 1.0, 1.0, 1.0, a); igt_put_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER], cr); - igt_display_commit(display); igt_wait_for_vblank(data->drm_fd, data->pipe); igt_pipe_crc_get_current(data->drm_fd, pipe_crc, &ref_crc); + + /*Compare CRC from Hardware/Software tests*/ igt_assert_crc_equal(&crc, &ref_crc); /*Clear Screen*/ @@ -688,13 +691,19 @@ static void run_tests_on_pipe(data_t *data, enum pipe pipe) igt_require(data->output); } + igt_describe("Create a maximum size cursor, then change the size in "\ + "flight to smaller ones to see that the size is applied correctly."); igt_subtest_f("pipe-%s-cursor-size-change", kmstest_pipe_name(pipe)) run_test(data, test_cursor_size, data->cursor_max_w, data->cursor_max_h); + igt_describe("Validates the composition of a fully opaque cursor "\ + "plane, i.e., alpha channel equal to 1.0."); igt_subtest_f("pipe-%s-cursor-alpha-opaque", kmstest_pipe_name(pipe)) run_test(data, test_cursor_opaque, data->cursor_max_w, data->cursor_max_h); + igt_describe("Validates the composition of a fully transparent cursor "\ + "plane, i.e., alpha channel equal to 0.0."); igt_subtest_f("pipe-%s-cursor-alpha-transparent", kmstest_pipe_name(pipe)) run_test(data, test_cursor_transparent, data->cursor_max_w, data->cursor_max_h); @@ -728,15 +737,24 @@ static void run_tests_on_pipe(data_t *data, enum pipe pipe) } /* Using created cursor FBs to test cursor support */ + igt_describe("Check if a given-size cursor is well-positioned inside the screen."); igt_subtest_f("pipe-%s-cursor-%dx%d-onscreen", kmstest_pipe_name(pipe), w, h) run_test(data, test_crc_onscreen, w, h); + + igt_describe("Check if a given-size cursor is well-positioned outside the screen."); igt_subtest_f("pipe-%s-cursor-%dx%d-offscreen", kmstest_pipe_name(pipe), w, h) run_test(data, test_crc_offscreen, w, h); + + igt_describe("Check the smooth and pixel-by-pixel given-size cursor movements on"\ + "horizontal, vertical and diagonal."); igt_subtest_f("pipe-%s-cursor-%dx%d-sliding", kmstest_pipe_name(pipe), w, h) run_test(data, test_crc_sliding, w, h); + + igt_describe("Check random placement of a cursor with given size."); igt_subtest_f("pipe-%s-cursor-%dx%d-random", kmstest_pipe_name(pipe), w, h) run_test(data, test_crc_random, w, h); + igt_describe("Check the rapid update of given-size cursor movements."); igt_subtest_f("pipe-%s-cursor-%dx%d-rapid-movement", kmstest_pipe_name(pipe), w, h) { run_test(data, test_rapid_movement, w, h); } -- 2.27.0 From patchwork at emeril.freedesktop.org Wed Jun 24 09:59:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 09:59:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/display/rkl=3A_Implement_W?= =?utf-8?q?A_14011471926?= In-Reply-To: <20200623215235.125665-1-jose.souza@intel.com> References: <20200623215235.125665-1-jose.souza@intel.com> Message-ID: <159299276908.19238.760085646627717379@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/display/rkl: Implement WA 14011471926 URL : https://patchwork.freedesktop.org/series/78761/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8661 -> Patchwork_18014 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18014 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18014, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18014: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html Known issues ------------ Here are the changes found in Patchwork_18014 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-tgl-u2/igt at i915_module_load@reload.html * igt at kms_psr@primary_page_flip: - fi-tgl-u2: [PASS][5] -> [SKIP][6] ([i915#668]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at kms_psr@primary_page_flip.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-tgl-u2/igt at kms_psr@primary_page_flip.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [INCOMPLETE][7] ([i915#1242]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html - fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-dsi/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][17] ([fdo#109271]) -> [DMESG-FAIL][18] ([i915#62]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18014 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18014: fe2335f738918db439be654668df5b38c2034129 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fe2335f73891 drm/i915/display: Implement new combo phy initialization step 3ac2f590c2c8 drm/i915/display: Rename COMP_INIT to CNL_PORT_COMP_DW0_COMP_INIT bd24ac2db018 drm/i915/display/rkl: Implement WA 14011471926 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18014/index.html From patchwork at emeril.freedesktop.org Wed Jun 24 10:24:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 10:24:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/display/rkl=3A_Implement_W?= =?utf-8?q?A_14011471926?= In-Reply-To: <20200623215235.125665-1-jose.souza@intel.com> References: <20200623215235.125665-1-jose.souza@intel.com> Message-ID: <159299427599.19238.16321680003077013468@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/display/rkl: Implement WA 14011471926 URL : https://patchwork.freedesktop.org/series/78761/ State : success == Summary == CI Bug Log - changes from CI_DRM_8661 -> Patchwork_18015 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/index.html Known issues ------------ Here are the changes found in Patchwork_18015 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html * igt at kms_psr@primary_page_flip: - fi-tgl-u2: [PASS][3] -> [SKIP][4] ([i915#668]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at kms_psr@primary_page_flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-tgl-u2/igt at kms_psr@primary_page_flip.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][5] ([i915#1888]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-dsi/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at i915_selftest@live at gt_lrc: - fi-tgl-u2: [DMESG-FAIL][9] ([i915#1233]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-tgl-u2/igt at i915_selftest@live at gt_lrc.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18015 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18015: b6b9f0c4c19d69b948abeeecd9850c72f02875ef @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b6b9f0c4c19d drm/i915/display: Implement new combo phy initialization step 4f2b21d43ce8 drm/i915/display: Rename COMP_INIT to CNL_PORT_COMP_DW0_COMP_INIT baf9b15362c6 drm/i915/display/rkl: Implement WA 14011471926 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/index.html From chris at chris-wilson.co.uk Wed Jun 24 10:48:05 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 11:48:05 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <5c3295d2-2527-0b0f-8aed-2489204c2722@shipmail.org> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <1712fc5b-9b1e-0632-13c0-e0bc2c1d889d@shipmail.org> <159293017861.3967.12926784772086320588@build.alporthouse.com> <60e198c5-bfc1-2bc6-05a3-487763f7a609@shipmail.org> <159293768060.3967.16328770521784351822@build.alporthouse.com> <88f746c6-c6ad-8c19-7797-856ac6bb2f50@shipmail.org> <159294690652.3967.16801810632630360943@build.alporthouse.com> <ef797b36-22e9-887b-dca4-5a845c60aed7@shipmail.org> <159298610762.26399.7546337779632693043@build.alporthouse.com> <5c3295d2-2527-0b0f-8aed-2489204c2722@shipmail.org> Message-ID: <159299568508.4527.5185261864133053705@build.alporthouse.com> Quoting Thomas Hellstr?m (Intel) (2020-06-24 10:50:08) > > On 6/24/20 10:08 AM, Chris Wilson wrote: > > Quoting Thomas Hellstr?m (Intel) (2020-06-24 06:42:33) > >> On 6/23/20 11:15 PM, Chris Wilson wrote: > >>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 21:31:38) > >>>> On 6/23/20 8:41 PM, Chris Wilson wrote: > >>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 19:21:28) > >>>>>> On 6/23/20 6:36 PM, Chris Wilson wrote: > >>>>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 12:22:11) > >>>>>>>> Hi, Chris, > >>>>>>>> > >>>>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>>>>>>>> In order to actually handle eviction and what not, we need to process > >>>>>>>>> all the objects together under a common lock, reservation_ww_class. As > >>>>>>>>> such, do a memory reservation pass after looking up the object/vma, > >>>>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>>>>>>>> flushing and ofc execution]. > >>>>>>>>> > >>>>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>>>>>>>> --- > >>>>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>>>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>>>>>>>> > >>>>>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>>>>>> index 46fcbdf8161c..8db2e013465f 100644 > >>>>>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > >>>>>>>>> @@ -53,10 +53,9 @@ struct eb_vma_array { > >>>>>>>>> > >>>>>>>>> #define __EXEC_OBJECT_HAS_PIN BIT(31) > >>>>>>>>> #define __EXEC_OBJECT_HAS_FENCE BIT(30) > >>>>>>>>> -#define __EXEC_OBJECT_HAS_PAGES BIT(29) > >>>>>>>>> -#define __EXEC_OBJECT_NEEDS_MAP BIT(28) > >>>>>>>>> -#define __EXEC_OBJECT_NEEDS_BIAS BIT(27) > >>>>>>>>> -#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 27) /* all of the above */ > >>>>>>>>> +#define __EXEC_OBJECT_NEEDS_MAP BIT(29) > >>>>>>>>> +#define __EXEC_OBJECT_NEEDS_BIAS BIT(28) > >>>>>>>>> +#define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ > >>>>>>>>> > >>>>>>>>> #define __EXEC_HAS_RELOC BIT(31) > >>>>>>>>> #define __EXEC_INTERNAL_FLAGS (~0u << 31) > >>>>>>>>> @@ -241,6 +240,8 @@ struct i915_execbuffer { > >>>>>>>>> struct intel_context *context; /* logical state for the request */ > >>>>>>>>> struct i915_gem_context *gem_context; /** caller's context */ > >>>>>>>>> > >>>>>>>>> + struct dma_fence *mm_fence; > >>>>>>>>> + > >>>>>>>>> struct i915_request *request; /** our request to build */ > >>>>>>>>> struct eb_vma *batch; /** identity of the batch obj/vma */ > >>>>>>>>> struct i915_vma *trampoline; /** trampoline used for chaining */ > >>>>>>>>> @@ -331,12 +332,7 @@ static inline void eb_unreserve_vma(struct eb_vma *ev) > >>>>>>>>> if (ev->flags & __EXEC_OBJECT_HAS_PIN) > >>>>>>>>> __i915_vma_unpin(vma); > >>>>>>>>> > >>>>>>>>> - if (ev->flags & __EXEC_OBJECT_HAS_PAGES) > >>>>>>>>> - i915_gem_object_unpin_pages(vma->obj); > >>>>>>>>> - > >>>>>>>>> - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > >>>>>>>>> - __EXEC_OBJECT_HAS_FENCE | > >>>>>>>>> - __EXEC_OBJECT_HAS_PAGES); > >>>>>>>>> + ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE); > >>>>>>>>> } > >>>>>>>>> > >>>>>>>>> static void eb_vma_array_destroy(struct kref *kref) > >>>>>>>>> @@ -667,6 +663,55 @@ eb_add_vma(struct i915_execbuffer *eb, > >>>>>>>>> list_add_tail(&ev->lock_link, &eb->lock); > >>>>>>>>> } > >>>>>>>>> > >>>>>>>>> +static int eb_vma_get_pages(struct i915_execbuffer *eb, > >>>>>>>>> + struct eb_vma *ev, > >>>>>>>>> + u64 idx) > >>>>>>>>> +{ > >>>>>>>>> + struct i915_vma *vma = ev->vma; > >>>>>>>>> + int err; > >>>>>>>>> + > >>>>>>>>> + /* XXX also preallocate PD for vma */ > >>>>>>>>> + > >>>>>>>>> + err = ____i915_gem_object_get_pages_async(vma->obj); > >>>>>>>>> + if (err) > >>>>>>>>> + return err; > >>>>>>>>> + > >>>>>>>>> + return i915_active_ref(&vma->obj->mm.active, idx, eb->mm_fence); > >>>>>>>>> +} > >>>>>>>>> + > >>>>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>>>>>>>> +{ > >>>>>>>>> + const u64 idx = eb->context->timeline->fence_context; > >>>>>>>>> + struct ww_acquire_ctx acquire; > >>>>>>>>> + struct eb_vma *ev; > >>>>>>>>> + int err; > >>>>>>>>> + > >>>>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>>>>>>>> + if (!eb->mm_fence) > >>>>>>>>> + return -ENOMEM; > >>>>>>>> Question: eb is local to this thread, right, so eb->mm_fence is not > >>>>>>>> considered "published" yet? > >>>>>>>> > >>>>>>>>> + > >>>>>>>>> + ww_acquire_init(&acquire, &reservation_ww_class); > >>>>>>>>> + > >>>>>>>>> + err = eb_lock_vma(eb, &acquire); > >>>>>>>>> + if (err) > >>>>>>>>> + goto out; > >>>>>>>>> + > >>>>>>>>> + ww_acquire_done(&acquire); > >>>>>>>>> + > >>>>>>>>> + list_for_each_entry(ev, &eb->lock, lock_link) { > >>>>>>>>> + struct i915_vma *vma = ev->vma; > >>>>>>>>> + > >>>>>>>>> + if (err == 0) > >>>>>>>>> + err = eb_vma_get_pages(eb, ev, idx); > >>>>>>>> I figure this is where you publish the proxy fence? If so, the fence > >>>>>>>> signaling critical path starts with this loop, > >>>>>>> Hmm, actually at this moment, the fence is still very much internal > >>>>>>> being only used as a reference token, > >>>>>> I think as long as another thread, running in this driver or another gpu > >>>>>> driver can theoretically reference the fence pointer from the > >>>>>> reservation object and wait for the fence it's considered published. > >>>>> It's not in the reservation object. > >>>>> > >>>>>> Also the ww_mutexes in this context are really all about grabbing a > >>>>>> random set of resources and associate them with a point in a timeline, > >>>>>> as the ww_mutexes are released, the fence pointer(s) need to point to > >>>>>> published fence(s). > >>>>> That's not the purpose of these fences, though. They exist to provide > >>>>> reference counting on the backing store, along side the migration fence. > >>>>> It's extra detail tacked on the equivalent of bo->moving. > >>>>> > >>>>> That is not to say that one could build up an async migration chain which > >>>>> form a graph back to these, that chain could only be formed once the > >>>>> operation itself has been published in the dma_resv though. > >>>> Hmm. So let's say another thread grabs one of the just released > >>>> ww_mutexes and wants to schedule a blit from one of the buffers in the > >>>> current operation with high priority. How would that thread know how to > >>>> order that blit operation w r t the current operation? > >>> Why would it order? > >> So let's say it's an eviction blit, needing to incorporate the data from > >> the current operation. Or, for that matter a ttm-style cpu copy eviction: > >> > >> ww_mutex_lock > >> wait_for_idle > >> copy > >> ww_mutex_unlock > > We have a scheduler. Eviction does not block. Submission never blocks. > So regardless if we block or not, how does the scheduler know how to > order the eviction blit after the current operation? Wouldn't it need to > look at the proxy fence to determine that? Basically I'm trying to get > an understanding where the fence signaling critical section starts. Yes, via the eviction logic but that is only applicable to evictions within the critical section, and the easiest way to circumvent that is not to allow evictions within that region; that is evictions can only be scheduled en masse and not piecemeal. [All the same rules as pinning applies, since it is the same...] There is no disagreement in that ideally all reservations must be performed upfront. The issue is quite simply that we do not know all the reservations we will need up front -- there are many sequences which we can offload to the GPU but require arbitrary allocations to do so. For that, what I was expecting was to try to create requests without eviction (akin to GFP_ATOMIC), on running out of space commit what has been completed so far, and rolling back to reacquiring all objects plus a reserved mempool and continuing on, as many times as required to complete handing the payload to the GPU. (Experience might say that we start off with a reservation for a mempool in addition to the user and PD payload.) The other issue is that some objects are not trivially evictable, those that are in active use by the HW and have an implicit write after the fence. [And when that write occurs is unknown as we are expected to treat that as part of a black box, so we only know for certain after the fact as another context's request is signaled.] They also have a placeholder for a fence that is inserted by what is essentially a GC sweep. [That fence can be inserted on demand, hence the special perma-pinned kernel context to ensure that we can always force a context switch, also used for power management of the engines.] It's certainly a lot simpler if we can avoid including those as part of the eviction pass, only removing them when idle and avoid exposing them ever to a wide lock. It certainly needs to be treated with care to avoid regressing the driver. -Chris From patchwork at emeril.freedesktop.org Wed Jun 24 10:51:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 10:51:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Send_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <159299589741.19236.15323518631653361058@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev8) URL : https://patchwork.freedesktop.org/series/62816/ State : warning == Summary == $ dim checkpatch origin/drm-tip eeee75d80077 drm: Add helper to compare edids. -:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid1" #32: FILE: drivers/gpu/drm/drm_edid.c:1628: + bool edid1_present = edid1 != NULL; -:33: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid2" #33: FILE: drivers/gpu/drm/drm_edid.c:1629: + bool edid2_present = edid2 != NULL; -:39: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #39: FILE: drivers/gpu/drm/drm_edid.c:1635: + if (edid1) { + -:54: CHECK:LINE_SPACING: Please don't use multiple blank lines #54: FILE: drivers/gpu/drm/drm_edid.c:1650: + + total: 0 errors, 0 warnings, 4 checks, 54 lines checked 127303584a7e drm: Introduce epoch counter to drm_connector -:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #56: FILE: drivers/gpu/drm/drm_connector.c:2012: + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", + connector->base.id, connector->name); -:60: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #60: FILE: drivers/gpu/drm/drm_connector.c:2016: + DRM_DEBUG_KMS("Updating change counter to %llu\n", + connector->epoch_counter); -:129: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' #129: FILE: drivers/gpu/drm/drm_probe_helper.c:790: + uint64_t old_epoch_counter; -:160: WARNING:BRACES: braces {} are not necessary for single statement blocks #160: FILE: drivers/gpu/drm/drm_probe_helper.c:826: + if (old_epoch_counter != connector->epoch_counter) { changed = true; + } -:183: ERROR:CODE_INDENT: code indent should use tabs where possible #183: FILE: include/drm/drm_connector.h:1332: + /** @epoch_counter: used to detect any other changes in connector, besides status */$ -:184: ERROR:CODE_INDENT: code indent should use tabs where possible #184: FILE: include/drm/drm_connector.h:1333: + uint64_t epoch_counter;$ -:184: WARNING:LEADING_SPACE: please, no spaces at the start of a line #184: FILE: include/drm/drm_connector.h:1333: + uint64_t epoch_counter;$ -:184: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' #184: FILE: include/drm/drm_connector.h:1333: + uint64_t epoch_counter; total: 2 errors, 2 warnings, 4 checks, 136 lines checked 6f6d00bcff9f drm/i915: Send hotplug event if edid had changed -:42: ERROR:CODE_INDENT: code indent should use tabs where possible #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: + u64 old_epoch_counter;$ -:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: + u64 old_epoch_counter;$ -:43: ERROR:CODE_INDENT: code indent should use tabs where possible #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: + bool ret = false;$ -:43: WARNING:LEADING_SPACE: please, no spaces at the start of a line #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: + bool ret = false;$ -:62: ERROR:CODE_INDENT: code indent should use tabs where possible #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: + if (old_epoch_counter != connector->base.epoch_counter)$ -:62: WARNING:LEADING_SPACE: please, no spaces at the start of a line #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: + if (old_epoch_counter != connector->base.epoch_counter)$ -:63: ERROR:CODE_INDENT: code indent should use tabs where possible #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: + ret = true;$ -:63: WARNING:LEADING_SPACE: please, no spaces at the start of a line #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: + ret = true;$ -:65: ERROR:CODE_INDENT: code indent should use tabs where possible #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: + if(ret) {$ -:65: WARNING:LEADING_SPACE: please, no spaces at the start of a line #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: + if(ret) {$ -:65: ERROR:SPACING: space required before the open parenthesis '(' #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: + if(ret) { -:73: ERROR:CODE_INDENT: code indent should use tabs where possible #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: + }$ -:73: WARNING:LEADING_SPACE: please, no spaces at the start of a line #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: + }$ -:74: ERROR:CODE_INDENT: code indent should use tabs where possible #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: + return INTEL_HOTPLUG_UNCHANGED;$ -:74: WARNING:LEADING_SPACE: please, no spaces at the start of a line #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: + return INTEL_HOTPLUG_UNCHANGED;$ total: 8 errors, 7 warnings, 0 checks, 38 lines checked From patchwork at emeril.freedesktop.org Wed Jun 24 10:53:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 10:53:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Send_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <159299600590.19238.8758431459323313616@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev8) URL : https://patchwork.freedesktop.org/series/62816/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:184:13: warning: cast to restricted __le32 From karthik.b.s at intel.com Wed Jun 24 11:00:24 2020 From: karthik.b.s at intel.com (Karthik B S) Date: Wed, 24 Jun 2020 16:30:24 +0530 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> Message-ID: <97cd4e21-86a2-8caf-46a4-1c01293b1d5f@intel.com> On 6/11/2020 4:03 AM, Paulo Zanoni wrote: > Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: >> Add enable/disable flip done functions and the flip done handler >> function which handles the flip done interrupt. >> >> Enable the flip done interrupt in IER. >> >> Enable flip done function is called before writing the >> surface address register as the write to this register triggers >> the flip done interrupt >> >> Flip done handler is used to send the page flip event as soon as the >> surface address is written as per the requirement of async flips. >> The interrupt is disabled after the event is sent. >> >> v2: -Change function name from icl_* to skl_* (Paulo) >> -Move flip handler to this patch (Paulo) >> -Remove vblank_put() (Paulo) >> -Enable flip done interrupt for gen9+ only (Paulo) >> -Enable flip done interrupt in power_well_post_enable hook (Paulo) >> -Removed the event check in flip done handler to handle async >> flips without pageflip events. >> >> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) >> -Make the pending vblank event NULL in the begining of >> flip_done_handler to remove sporadic WARN_ON that is seen. >> >> Signed-off-by: Karthik B S <karthik.b.s at intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ >> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ >> drivers/gpu/drm/i915/i915_irq.h | 2 + >> 3 files changed, 64 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> index f40b909952cc..48cc1fc9bc5a 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_display.c >> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >> >> intel_dbuf_pre_plane_update(state); >> >> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >> + if (new_crtc_state->uapi.async_flip) { >> + skl_enable_flip_done(&crtc->base); >> + break; >> + } >> + } >> + >> /* Now enable the clocks, plane, pipe, and connectors that we set up. */ >> dev_priv->display.commit_modeset_enables(state); >> >> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >> drm_atomic_helper_wait_for_flip_done(dev, &state->base); >> >> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >> + if (new_crtc_state->uapi.async_flip) >> + skl_disable_flip_done(&crtc->base); >> + >> if (new_crtc_state->hw.active && >> !needs_modeset(new_crtc_state) && >> !new_crtc_state->preload_luts && >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> index efdd4c7b8e92..632e7b1deb87 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.c >> +++ b/drivers/gpu/drm/i915/i915_irq.c >> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >> u32 crc4) {} >> #endif >> >> +static void flip_done_handler(struct drm_i915_private *dev_priv, >> + unsigned int pipe) >> +{ >> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); >> + struct drm_crtc_state *crtc_state = crtc->base.state; >> + struct drm_pending_vblank_event *e = crtc_state->event; >> + struct drm_device *dev = &dev_priv->drm; >> + unsigned long irqflags; >> + >> + crtc_state->event = NULL; >> + >> + spin_lock_irqsave(&dev->event_lock, irqflags); >> + >> + drm_crtc_send_vblank_event(&crtc->base, e); > > I don't think this is what we want. With this, the events the Kernel > sends us all have the same sequence and timestamp. In fact, the IGT > test you submitted fails because of this. > > In my original hackish proof-of-concept patch I had changed > drm_update_vblank_count() to force diff=1 in order to always send > events and I also changed g4x_get_vblank_counter() to get the counter > from FLIPCOUNT (which updates every time there's a flip) instead of > FRMCOUNT (which doesn't seem to increment when you do async flips). > That is a drastic change, but the patch was just a PoC so I didn't care > about keeping anything else working. > > One thing that confused me a little bit when dealing the the > vblank/flip event interface from drm.ko is that "flips" and "vblanks" > seem to be changed interchangeably, which is confusing for async flips: > if you keep forever doing async flips in the very first few scanlines > you never actually reach the "vblank" period, yet you keep flipping > your frame. Then, what should your expectation regarding events be? > > I think we may need to check how the other drivers handle async vblanks > (or how drm.ko wants us to handle async vblanks). Should we increment > sequence on every async flip? What about the timestamp? > > Daniel, Ville, do you happen to know the proper semantics here? > > There's certainly some adjustment to do to both this patch and the IGT. Thanks for the review. I will find the proper way to implement the sequence and time stammping parts by looking into the other drivers implementation for this. Also will make the required changes regarding the events to be sent. Will also look into the other inputs received and make the required corrections. Regards, Karthik.B.S > >> + >> + spin_unlock_irqrestore(&dev->event_lock, irqflags); >> +} >> >> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >> enum pipe pipe) >> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) >> if (iir & GEN8_PIPE_VBLANK) >> intel_handle_vblank(dev_priv, pipe); >> >> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) >> + flip_done_handler(dev_priv, pipe); >> + >> if (iir & GEN8_PIPE_CDCLK_CRC_DONE) >> hsw_pipe_crc_irq_handler(dev_priv, pipe); >> >> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) >> return 0; >> } >> >> +void skl_enable_flip_done(struct drm_crtc *crtc) >> +{ >> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >> + unsigned long irqflags; >> + >> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >> + >> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >> + >> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >> +} >> + >> /* Called from drm generic code, passed 'crtc' which >> * we use as a pipe index >> */ >> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) >> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >> } >> >> +void skl_disable_flip_done(struct drm_crtc *crtc) >> +{ >> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >> + unsigned long irqflags; >> + >> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >> + >> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >> + >> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >> +} >> + >> static void ibx_irq_reset(struct drm_i915_private *dev_priv) >> { >> struct intel_uncore *uncore = &dev_priv->uncore; >> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, >> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; >> enum pipe pipe; >> >> + if (INTEL_GEN(dev_priv) >= 9) >> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; >> + >> spin_lock_irq(&dev_priv->irq_lock); >> >> if (!intel_irqs_enabled(dev_priv)) { >> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) >> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | >> GEN8_PIPE_FIFO_UNDERRUN; >> >> + if (INTEL_GEN(dev_priv) >= 9) >> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; >> + >> de_port_enables = de_port_masked; >> if (IS_GEN9_LP(dev_priv)) >> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; >> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h >> index 25f25cd95818..2f10c8135116 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.h >> +++ b/drivers/gpu/drm/i915/i915_irq.h >> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); >> int i965_enable_vblank(struct drm_crtc *crtc); >> int ilk_enable_vblank(struct drm_crtc *crtc); >> int bdw_enable_vblank(struct drm_crtc *crtc); >> +void skl_enable_flip_done(struct drm_crtc *crtc); >> void i8xx_disable_vblank(struct drm_crtc *crtc); >> void i915gm_disable_vblank(struct drm_crtc *crtc); >> void i965_disable_vblank(struct drm_crtc *crtc); >> void ilk_disable_vblank(struct drm_crtc *crtc); >> void bdw_disable_vblank(struct drm_crtc *crtc); >> +void skl_disable_flip_done(struct drm_crtc *crtc); >> >> void gen2_irq_reset(struct intel_uncore *uncore); >> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, > From maarten.lankhorst at linux.intel.com Wed Jun 24 11:05:15 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Wed, 24 Jun 2020 13:05:15 +0200 Subject: [Intel-gfx] [PATCH] drm/i915: Kill context before taking ctx->mutex In-Reply-To: <20200623142843.423594-26-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-26-maarten.lankhorst@linux.intel.com> Message-ID: <20200624110515.454665-1-maarten.lankhorst@linux.intel.com> Killing context before taking ctx->mutex fixes a hang in gem_ctx_persistence.close-replace-race, where lut_close takes obj->resv.lock which is already held by execbuf, causing a stalling indefinitely. [ 1904.342847] 2 locks held by gem_ctx_persist/11520: [ 1904.342849] #0: ffff8882188e4968 (&ctx->mutex){+.+.}-{3:3}, at: context_close+0xe6/0x850 [i915] [ 1904.342941] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: lut_close+0x2c2/0xba0 [i915] [ 1904.343033] 3 locks held by gem_ctx_persist/11521: [ 1904.343035] #0: ffffc900008ff938 (reservation_ww_class_acquire){+.+.}-{0:0}, at: i915_gem_do_execbuffer+0x103d/0x54c0 [i915] [ 1904.343157] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: eb_validate_vmas+0x602/0x2010 [i915] [ 1904.343267] #2: ffff88820afd9200 (&vm->mutex/1){+.+.}-{3:3}, at: i915_vma_pin_ww+0x335/0x2300 [i915] Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 22 ++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index a3519d5ee5a3..6d25c9c2be1a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -623,6 +623,17 @@ static void context_close(struct i915_gem_context *ctx) i915_gem_context_set_closed(ctx); mutex_unlock(&ctx->engines_mutex); + /* + * If the user has disabled hangchecking, we can not be sure that + * the batches will ever complete after the context is closed, + * keeping the context and all resources pinned forever. So in this + * case we opt to forcibly kill off all remaining requests on + * context close. + */ + if (!i915_gem_context_is_persistent(ctx) || + !ctx->i915->params.enable_hangcheck) + kill_context(ctx); + mutex_lock(&ctx->mutex); set_closed_name(ctx); @@ -642,17 +653,6 @@ static void context_close(struct i915_gem_context *ctx) mutex_unlock(&ctx->mutex); - /* - * If the user has disabled hangchecking, we can not be sure that - * the batches will ever complete after the context is closed, - * keeping the context and all resources pinned forever. So in this - * case we opt to forcibly kill off all remaining requests on - * context close. - */ - if (!i915_gem_context_is_persistent(ctx) || - !ctx->i915->params.enable_hangcheck) - kill_context(ctx); - i915_gem_context_put(ctx); } base-commit: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f prerequisite-patch-id: e6315738715ac4ffccaeb4c4bf5a94651fb8da1d prerequisite-patch-id: 7944bb01d1ec7530513eabddb9198275653cc451 prerequisite-patch-id: 052eda3b40906f0fbc16b4cc33dbcdce35e05441 prerequisite-patch-id: 35ff18a74e8bf9bfb0a517f69a98d0ec88bd3b51 prerequisite-patch-id: 7a34e785e951b1d3f4c0e20430c8111a15ddbe92 prerequisite-patch-id: 9b7faf3172e9f218a2589fcc96930af9ab05e70b prerequisite-patch-id: 3ce7c5b4508018631673e62d8725f866988bd08d prerequisite-patch-id: 5fd46caff26e53f9cb6df5f8490838b6ac15e015 prerequisite-patch-id: 41782208b1bc32e448ce29313112030c74bd8421 prerequisite-patch-id: b6c4d99cb554c0c2268cde5c43e878a48e005e45 prerequisite-patch-id: 418fdb031a232bba4056171917ee42e997991902 prerequisite-patch-id: ff5bf0dcdb9191761392b0707481aaf99396dbec prerequisite-patch-id: c3dbcef2f1a68f88ae99acbd01ee56847fb3e2da prerequisite-patch-id: 18c373676c9bbeb1c11fb2ba5bf4ad728cfea75d prerequisite-patch-id: 5b9d8e4535096365d365fdd1ec00f844a4135208 prerequisite-patch-id: 63bac64548acd514c4a0cb5acb896c8217fb8201 prerequisite-patch-id: e93b855dd97b24799c59f059cc548f46807ab207 prerequisite-patch-id: 3d7dc6ecbc2279fb48f0972a911fbffd8d899faa prerequisite-patch-id: f1d9e0b7165f80efe984dd0231d1dbd2a9a79950 prerequisite-patch-id: ed1a168ac98b81b8066f68a0738cfc44a79e8ef1 prerequisite-patch-id: f813cb8d4c2fe2c1d94b66c3f3fbb787ac241628 prerequisite-patch-id: 0f0f90eaa4a2e299adddfe1c7134af3810a8e9e2 prerequisite-patch-id: cb7ffeccd6429fc79aebffb84f62af5e78252461 prerequisite-patch-id: 78905449b46ad574757a7fb91f58847ea20e09cd prerequisite-patch-id: 6d937a49f3c8cd380121f72610072aaaf8c274b1 prerequisite-patch-id: 0c8d2dee1592395780258488be0350755e7ffd7d -- 2.27.0 From patchwork at emeril.freedesktop.org Wed Jun 24 11:12:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 11:12:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgU2Vu?= =?utf-8?q?d_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <159299716633.19235.9442849395428140345@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev8) URL : https://patchwork.freedesktop.org/series/62816/ State : success == Summary == CI Bug Log - changes from CI_DRM_8661 -> Patchwork_18016 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/index.html Known issues ------------ Here are the changes found in Patchwork_18016 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at coherency: - fi-gdg-551: [PASS][5] -> [DMESG-FAIL][6] ([i915#1748]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-gdg-551/igt at i915_selftest@live at coherency.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-gdg-551/igt at i915_selftest@live at coherency.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_psr@primary_page_flip: - fi-tgl-u2: [PASS][9] -> [SKIP][10] ([i915#668]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at kms_psr@primary_page_flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-tgl-u2/igt at kms_psr@primary_page_flip.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][11] ([i915#1888]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-dsi/igt at i915_module_load@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18016 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18016: 6f6d00bcff9fbea7969c94a52f4096a719e2733b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6f6d00bcff9f drm/i915: Send hotplug event if edid had changed 127303584a7e drm: Introduce epoch counter to drm_connector eeee75d80077 drm: Add helper to compare edids. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/index.html From karthik.b.s at intel.com Wed Jun 24 11:14:09 2020 From: karthik.b.s at intel.com (Karthik B S) Date: Wed, 24 Jun 2020 16:44:09 +0530 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> Message-ID: <7e5e2881-d3bf-aab1-8691-4b01affc863f@intel.com> On 6/17/2020 3:28 PM, Daniel Vetter wrote: > On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote: >> Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: >>> Add enable/disable flip done functions and the flip done handler >>> function which handles the flip done interrupt. >>> >>> Enable the flip done interrupt in IER. >>> >>> Enable flip done function is called before writing the >>> surface address register as the write to this register triggers >>> the flip done interrupt >>> >>> Flip done handler is used to send the page flip event as soon as the >>> surface address is written as per the requirement of async flips. >>> The interrupt is disabled after the event is sent. >>> >>> v2: -Change function name from icl_* to skl_* (Paulo) >>> -Move flip handler to this patch (Paulo) >>> -Remove vblank_put() (Paulo) >>> -Enable flip done interrupt for gen9+ only (Paulo) >>> -Enable flip done interrupt in power_well_post_enable hook (Paulo) >>> -Removed the event check in flip done handler to handle async >>> flips without pageflip events. >>> >>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) >>> -Make the pending vblank event NULL in the begining of >>> flip_done_handler to remove sporadic WARN_ON that is seen. >>> >>> Signed-off-by: Karthik B S <karthik.b.s at intel.com> >>> --- >>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ >>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ >>> drivers/gpu/drm/i915/i915_irq.h | 2 + >>> 3 files changed, 64 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >>> index f40b909952cc..48cc1fc9bc5a 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_display.c >>> +++ b/drivers/gpu/drm/i915/display/intel_display.c >>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >>> >>> intel_dbuf_pre_plane_update(state); >>> >>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>> + if (new_crtc_state->uapi.async_flip) { >>> + skl_enable_flip_done(&crtc->base); >>> + break; >>> + } >>> + } >>> + >>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */ >>> dev_priv->display.commit_modeset_enables(state); >>> >>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >>> drm_atomic_helper_wait_for_flip_done(dev, &state->base); >>> >>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>> + if (new_crtc_state->uapi.async_flip) >>> + skl_disable_flip_done(&crtc->base); >>> + >>> if (new_crtc_state->hw.active && >>> !needs_modeset(new_crtc_state) && >>> !new_crtc_state->preload_luts && >>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >>> index efdd4c7b8e92..632e7b1deb87 100644 >>> --- a/drivers/gpu/drm/i915/i915_irq.c >>> +++ b/drivers/gpu/drm/i915/i915_irq.c >>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >>> u32 crc4) {} >>> #endif >>> >>> +static void flip_done_handler(struct drm_i915_private *dev_priv, >>> + unsigned int pipe) >>> +{ >>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); >>> + struct drm_crtc_state *crtc_state = crtc->base.state; >>> + struct drm_pending_vblank_event *e = crtc_state->event; >>> + struct drm_device *dev = &dev_priv->drm; >>> + unsigned long irqflags; >>> + >>> + crtc_state->event = NULL; >>> + >>> + spin_lock_irqsave(&dev->event_lock, irqflags); >>> + >>> + drm_crtc_send_vblank_event(&crtc->base, e); >> >> I don't think this is what we want. With this, the events the Kernel >> sends us all have the same sequence and timestamp. In fact, the IGT >> test you submitted fails because of this. >> >> In my original hackish proof-of-concept patch I had changed >> drm_update_vblank_count() to force diff=1 in order to always send >> events and I also changed g4x_get_vblank_counter() to get the counter >> from FLIPCOUNT (which updates every time there's a flip) instead of >> FRMCOUNT (which doesn't seem to increment when you do async flips). >> That is a drastic change, but the patch was just a PoC so I didn't care >> about keeping anything else working. >> >> One thing that confused me a little bit when dealing the the >> vblank/flip event interface from drm.ko is that "flips" and "vblanks" >> seem to be changed interchangeably, which is confusing for async flips: >> if you keep forever doing async flips in the very first few scanlines >> you never actually reach the "vblank" period, yet you keep flipping >> your frame. Then, what should your expectation regarding events be? > > Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR > where that changes), no idea why we can't keep sending out vblank > interrupts. Thanks for the review. I was facing a race which lead the complete system to freeze with vblanks being enabled during async flips. Thus had made this change. But I'll find a proper implementation for this and enable the vblank interrupts as well. > > Now flip events look maybe conflated in drm.ko code with vblank events > since most of the time a flip complete happens at exactly the same time > the vblank event. But for async flip this is not the case. > > Probably worth it to have new helpers/function in drm_vblank.c for > async flips, so that this is less confusing. Plus good documentation. > Sure, I'll look into this and make the required additions. >> I think we may need to check how the other drivers handle async vblanks >> (or how drm.ko wants us to handle async vblanks). Should we increment >> sequence on every async flip? What about the timestamp? >> >> Daniel, Ville, do you happen to know the proper semantics here? >> >> There's certainly some adjustment to do to both this patch and the IGT. > > I think it would be really good if we cc dri-devel on this. amdgpu.ko is > currently the only implementation of async flips, we need to make sure we > are fully aligned on all the semantic details. > Sure, I'll look into the amddgpu.ko and make sure we are aligned. > That also means that the igt needs to be reviewed and tested by amdgpu > people. Might also be good to get the implementation acked by amd DC > people, just to make triple-sure we have the same semantics and generic > userspace compositors like mutter can use this across drivers. We've had > way too much pain here in the past, especially with the details you point > out here. > Sure, I'll get the IGT reviewed by the amdgpu and amd DC people. > Also, I think we need to have updated drm core documentation for async > flips, since the current ones are "do it like amdgpu does it". I think > just documenting the various pieces and flags in detail and how it all > interacts with e.g. other atomic commits and everything else would be > great. > Sure, I'll do this. > Harry and Nicholaus are the people you want from amd. Added everyone to cc. Thanks for this. Thanks and Regards, Karthik.B.S > -Daniel > > >> >>> + >>> + spin_unlock_irqrestore(&dev->event_lock, irqflags); >>> +} >>> >>> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >>> enum pipe pipe) >>> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) >>> if (iir & GEN8_PIPE_VBLANK) >>> intel_handle_vblank(dev_priv, pipe); >>> >>> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) >>> + flip_done_handler(dev_priv, pipe); >>> + >>> if (iir & GEN8_PIPE_CDCLK_CRC_DONE) >>> hsw_pipe_crc_irq_handler(dev_priv, pipe); >>> >>> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) >>> return 0; >>> } >>> >>> +void skl_enable_flip_done(struct drm_crtc *crtc) >>> +{ >>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >>> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >>> + unsigned long irqflags; >>> + >>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >>> + >>> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >>> + >>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>> +} >>> + >>> /* Called from drm generic code, passed 'crtc' which >>> * we use as a pipe index >>> */ >>> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) >>> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>> } >>> >>> +void skl_disable_flip_done(struct drm_crtc *crtc) >>> +{ >>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev); >>> + enum pipe pipe = to_intel_crtc(crtc)->pipe; >>> + unsigned long irqflags; >>> + >>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >>> + >>> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >>> + >>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>> +} >>> + >>> static void ibx_irq_reset(struct drm_i915_private *dev_priv) >>> { >>> struct intel_uncore *uncore = &dev_priv->uncore; >>> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, >>> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; >>> enum pipe pipe; >>> >>> + if (INTEL_GEN(dev_priv) >= 9) >>> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; >>> + >>> spin_lock_irq(&dev_priv->irq_lock); >>> >>> if (!intel_irqs_enabled(dev_priv)) { >>> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) >>> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | >>> GEN8_PIPE_FIFO_UNDERRUN; >>> >>> + if (INTEL_GEN(dev_priv) >= 9) >>> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; >>> + >>> de_port_enables = de_port_masked; >>> if (IS_GEN9_LP(dev_priv)) >>> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; >>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h >>> index 25f25cd95818..2f10c8135116 100644 >>> --- a/drivers/gpu/drm/i915/i915_irq.h >>> +++ b/drivers/gpu/drm/i915/i915_irq.h >>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); >>> int i965_enable_vblank(struct drm_crtc *crtc); >>> int ilk_enable_vblank(struct drm_crtc *crtc); >>> int bdw_enable_vblank(struct drm_crtc *crtc); >>> +void skl_enable_flip_done(struct drm_crtc *crtc); >>> void i8xx_disable_vblank(struct drm_crtc *crtc); >>> void i915gm_disable_vblank(struct drm_crtc *crtc); >>> void i965_disable_vblank(struct drm_crtc *crtc); >>> void ilk_disable_vblank(struct drm_crtc *crtc); >>> void bdw_disable_vblank(struct drm_crtc *crtc); >>> +void skl_disable_flip_done(struct drm_crtc *crtc); >>> >>> void gen2_irq_reset(struct intel_uncore *uncore); >>> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > From chris at chris-wilson.co.uk Wed Jun 24 11:19:25 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 12:19:25 +0100 Subject: [Intel-gfx] [PATCH 01/26] Revert "drm/i915/gem: Async GPU relocations only" In-Reply-To: <159292581164.3967.4508032507063193551@build.alporthouse.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <159292581164.3967.4508032507063193551@build.alporthouse.com> Message-ID: <159299756563.4527.12397689258939181513@build.alporthouse.com> Quoting Chris Wilson (2020-06-23 16:23:31) > Quoting Maarten Lankhorst (2020-06-23 15:28:18) > > This reverts commit 9e0f9464e2ab36b864359a59b0e9058fdef0ce47, > > and related commit 7ac2d2536dfa7 ("drm/i915/gem: Delete unused code"). > > Regardless that you haven't adapted the series... > > This still prevents concurrent submission between clients, and does not > remove the allocation mutexes. That latter we can do in a couple of > patches that preserve the status quo with just a name switch and the > forced removal of nestable shrinkers. To be clear, I think the first patch has to be https://patchwork.freedesktop.org/series/78772/ (provided the rebasing went ok) to fully commit ourselves to removing obj->mm.mutex. Empirically, we cannot use trylock inside the mmu_notifier as that often fails during normal unmap. -Chris From karthik.b.s at intel.com Wed Jun 24 11:29:14 2020 From: karthik.b.s at intel.com (Karthik B S) Date: Wed, 24 Jun 2020 16:59:14 +0530 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <b82053ef-03b1-8d4a-24d8-bc2c07037f84@amd.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> <b82053ef-03b1-8d4a-24d8-bc2c07037f84@amd.com> Message-ID: <8d2723ec-5507-3307-43e7-29c5d1bfdb15@intel.com> On 6/17/2020 8:15 PM, Kazlauskas, Nicholas wrote: > On 2020-06-17 5:58 a.m., Daniel Vetter wrote: >> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote: >>> Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: >>>> Add enable/disable flip done functions and the flip done handler >>>> function which handles the flip done interrupt. >>>> >>>> Enable the flip done interrupt in IER. >>>> >>>> Enable flip done function is called before writing the >>>> surface address register as the write to this register triggers >>>> the flip done interrupt >>>> >>>> Flip done handler is used to send the page flip event as soon as the >>>> surface address is written as per the requirement of async flips. >>>> The interrupt is disabled after the event is sent. >>>> >>>> v2: -Change function name from icl_* to skl_* (Paulo) >>>> ???? -Move flip handler to this patch (Paulo) >>>> ???? -Remove vblank_put() (Paulo) >>>> ???? -Enable flip done interrupt for gen9+ only (Paulo) >>>> ???? -Enable flip done interrupt in power_well_post_enable hook (Paulo) >>>> ???? -Removed the event check in flip done handler to handle async >>>> ????? flips without pageflip events. >>>> >>>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) >>>> ???? -Make the pending vblank event NULL in the begining of >>>> ????? flip_done_handler to remove sporadic WARN_ON that is seen. >>>> >>>> Signed-off-by: Karthik B S <karthik.b.s at intel.com> >>>> --- >>>> ? drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ >>>> ? drivers/gpu/drm/i915/i915_irq.c????????????? | 52 >>>> ++++++++++++++++++++ >>>> ? drivers/gpu/drm/i915/i915_irq.h????????????? |? 2 + >>>> ? 3 files changed, 64 insertions(+) >>>> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c >>>> b/drivers/gpu/drm/i915/display/intel_display.c >>>> index f40b909952cc..48cc1fc9bc5a 100644 >>>> --- a/drivers/gpu/drm/i915/display/intel_display.c >>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c >>>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct >>>> intel_atomic_state *state) >>>> >>>> ???? intel_dbuf_pre_plane_update(state); >>>> >>>> +?? for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>>> +?????????? if (new_crtc_state->uapi.async_flip) { >>>> +?????????????????? skl_enable_flip_done(&crtc->base); >>>> +?????????????????? break; >>>> +?????????? } >>>> +?? } >>>> + >>>> ???? /* Now enable the clocks, plane, pipe, and connectors that we >>>> set up. */ >>>> ???? dev_priv->display.commit_modeset_enables(state); >>>> >>>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct >>>> intel_atomic_state *state) >>>> ???? drm_atomic_helper_wait_for_flip_done(dev, &state->base); >>>> >>>> ???? for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>>> +?????????? if (new_crtc_state->uapi.async_flip) >>>> +?????????????????? skl_disable_flip_done(&crtc->base); >>>> + >>>> ???????????? if (new_crtc_state->hw.active && >>>> ???????????????? !needs_modeset(new_crtc_state) && >>>> ???????????????? !new_crtc_state->preload_luts && >>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c >>>> b/drivers/gpu/drm/i915/i915_irq.c >>>> index efdd4c7b8e92..632e7b1deb87 100644 >>>> --- a/drivers/gpu/drm/i915/i915_irq.c >>>> +++ b/drivers/gpu/drm/i915/i915_irq.c >>>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct >>>> drm_i915_private *dev_priv, >>>> ????????????????????????? u32 crc4) {} >>>> ? #endif >>>> >>>> +static void flip_done_handler(struct drm_i915_private *dev_priv, >>>> +???????????????????????? unsigned int pipe) >>>> +{ >>>> +?? struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); >>>> +?? struct drm_crtc_state *crtc_state = crtc->base.state; >>>> +?? struct drm_pending_vblank_event *e = crtc_state->event; >>>> +?? struct drm_device *dev = &dev_priv->drm; >>>> +?? unsigned long irqflags; >>>> + >>>> +?? crtc_state->event = NULL; >>>> + >>>> +?? spin_lock_irqsave(&dev->event_lock, irqflags); >>>> + >>>> +?? drm_crtc_send_vblank_event(&crtc->base, e); >>> >>> I don't think this is what we want. With this, the events the Kernel >>> sends us all have the same sequence and timestamp. In fact, the IGT >>> test you submitted fails because of this. >>> >>> In my original hackish proof-of-concept patch I had changed >>> drm_update_vblank_count() to force diff=1 in order to always send >>> events and I also changed g4x_get_vblank_counter() to get the counter >>> from FLIPCOUNT (which updates every time there's a flip) instead of >>> FRMCOUNT (which doesn't seem to increment when you do async flips). >>> That is a drastic change, but the patch was just a PoC so I didn't care >>> about keeping anything else working. >>> >>> One thing that confused me a little bit when dealing the the >>> vblank/flip event interface from drm.ko is that "flips" and "vblanks" >>> seem to be changed interchangeably, which is confusing for async flips: >>> if you keep forever doing async flips in the very first few scanlines >>> you never actually reach the "vblank" period, yet you keep flipping >>> your frame. Then, what should your expectation regarding events be? >> >> Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR >> where that changes), no idea why we can't keep sending out vblank >> interrupts. >> >> Now flip events look maybe conflated in drm.ko code with vblank events >> since most of the time a flip complete happens at exactly the same time >> the vblank event. But for async flip this is not the case. >> >> Probably worth it to have new helpers/function in drm_vblank.c for >> async flips, so that this is less confusing. Plus good documentation. >> >>> I think we may need to check how the other drivers handle async vblanks >>> (or how drm.ko wants us to handle async vblanks). Should we increment >>> sequence on every async flip? What about the timestamp? >>> >>> Daniel, Ville, do you happen to know the proper semantics here? >>> >>> There's certainly some adjustment to do to both this patch and the IGT. >> >> I think it would be really good if we cc dri-devel on this. amdgpu.ko is >> currently the only implementation of async flips, we need to make sure we >> are fully aligned on all the semantic details. >> >> That also means that the igt needs to be reviewed and tested by amdgpu >> people. Might also be good to get the implementation acked by amd DC >> people, just to make triple-sure we have the same semantics and generic >> userspace compositors like mutter can use this across drivers. We've had >> way too much pain here in the past, especially with the details you point >> out here. >> >> Also, I think we need to have updated drm core documentation for async >> flips, since the current ones are "do it like amdgpu does it". I think >> just documenting the various pieces and flags in detail and how it all >> interacts with e.g. other atomic commits and everything else would be >> great. >> >> Harry and Nicholaus are the people you want from amd. Added everyone >> to cc. >> -Daniel > > IIRC async flips are treated the same as regular flips from amdgpu > perspective. When the hardware latches the new flip address an interrupt > is triggered and we send back the vblank event from the interrupt > handler immediately > > I think we use the same timestamp calculation code for both paths in > this case where we take the current hpos/vpos and calculate when scanout > is going to actually occur. > > Technically we're actually scanning out the framebuffer immediately > though so the timestamp is probably bogus. > > The regular vblank handler continues to run as usual in the background, > there's no change to the timing. On newer hardware this triggers around > when the hardware starts preparing the next frame, so close to the > double buffer latch (which is typically in the back porch). Thanks for the review. Even in this implementation I've made the changes to send the flip done event from the interrupt handler itself. But I've not kept the vblank handler running in background. I'll make the appropriate changes based on your inputs and make sure the implementation is aligned with the amdgpu implementation for async flips. Thanks and Regards, Karthik.B.S > > Regards, > Nicholas Kazlauskas > >> >> >>> >>>> + >>>> +?? spin_unlock_irqrestore(&dev->event_lock, irqflags); >>>> +} >>>> >>>> ? static void hsw_pipe_crc_irq_handler(struct drm_i915_private >>>> *dev_priv, >>>> ????????????????????????????????? enum pipe pipe) >>>> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private >>>> *dev_priv, u32 master_ctl) >>>> ???????????? if (iir & GEN8_PIPE_VBLANK) >>>> ???????????????????? intel_handle_vblank(dev_priv, pipe); >>>> >>>> +?????????? if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) >>>> +?????????????????? flip_done_handler(dev_priv, pipe); >>>> + >>>> ???????????? if (iir & GEN8_PIPE_CDCLK_CRC_DONE) >>>> ???????????????????? hsw_pipe_crc_irq_handler(dev_priv, pipe); >>>> >>>> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) >>>> ???? return 0; >>>> ? } >>>> >>>> +void skl_enable_flip_done(struct drm_crtc *crtc) >>>> +{ >>>> +?? struct drm_i915_private *dev_priv = to_i915(crtc->dev); >>>> +?? enum pipe pipe = to_intel_crtc(crtc)->pipe; >>>> +?? unsigned long irqflags; >>>> + >>>> +?? spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >>>> + >>>> +?? bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >>>> + >>>> +?? spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>>> +} >>>> + >>>> ? /* Called from drm generic code, passed 'crtc' which >>>> ?? * we use as a pipe index >>>> ?? */ >>>> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) >>>> ???? spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>>> ? } >>>> >>>> +void skl_disable_flip_done(struct drm_crtc *crtc) >>>> +{ >>>> +?? struct drm_i915_private *dev_priv = to_i915(crtc->dev); >>>> +?? enum pipe pipe = to_intel_crtc(crtc)->pipe; >>>> +?? unsigned long irqflags; >>>> + >>>> +?? spin_lock_irqsave(&dev_priv->irq_lock, irqflags); >>>> + >>>> +?? bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); >>>> + >>>> +?? spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); >>>> +} >>>> + >>>> ? static void ibx_irq_reset(struct drm_i915_private *dev_priv) >>>> ? { >>>> ???? struct intel_uncore *uncore = &dev_priv->uncore; >>>> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct >>>> drm_i915_private *dev_priv, >>>> ???? u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; >>>> ???? enum pipe pipe; >>>> >>>> +?? if (INTEL_GEN(dev_priv) >= 9) >>>> +?????????? extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; >>>> + >>>> ???? spin_lock_irq(&dev_priv->irq_lock); >>>> >>>> ???? if (!intel_irqs_enabled(dev_priv)) { >>>> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct >>>> drm_i915_private *dev_priv) >>>> ???? de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | >>>> ??????????????????????????????????????? GEN8_PIPE_FIFO_UNDERRUN; >>>> >>>> +?? if (INTEL_GEN(dev_priv) >= 9) >>>> +?????????? de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; >>>> + >>>> ???? de_port_enables = de_port_masked; >>>> ???? if (IS_GEN9_LP(dev_priv)) >>>> ???????????? de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; >>>> diff --git a/drivers/gpu/drm/i915/i915_irq.h >>>> b/drivers/gpu/drm/i915/i915_irq.h >>>> index 25f25cd95818..2f10c8135116 100644 >>>> --- a/drivers/gpu/drm/i915/i915_irq.h >>>> +++ b/drivers/gpu/drm/i915/i915_irq.h >>>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); >>>> ? int i965_enable_vblank(struct drm_crtc *crtc); >>>> ? int ilk_enable_vblank(struct drm_crtc *crtc); >>>> ? int bdw_enable_vblank(struct drm_crtc *crtc); >>>> +void skl_enable_flip_done(struct drm_crtc *crtc); >>>> ? void i8xx_disable_vblank(struct drm_crtc *crtc); >>>> ? void i915gm_disable_vblank(struct drm_crtc *crtc); >>>> ? void i965_disable_vblank(struct drm_crtc *crtc); >>>> ? void ilk_disable_vblank(struct drm_crtc *crtc); >>>> ? void bdw_disable_vblank(struct drm_crtc *crtc); >>>> +void skl_disable_flip_done(struct drm_crtc *crtc); >>>> >>>> ? void gen2_irq_reset(struct intel_uncore *uncore); >>>> ? void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, >>> >>> _______________________________________________ >>> Intel-gfx mailing list >>> Intel-gfx at lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Daniel Vetter >> Software Engineer, Intel Corporation >> http://blog.ffwll.ch/ >> > From patchwork at emeril.freedesktop.org Wed Jun 24 11:34:03 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 11:34:03 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B1/2=5D_mm/mmu=5Fnotifier=3A_Mark_up_dir?= =?utf-8?q?ect_reclaim_paths_with_MAYFAIL?= In-Reply-To: <20200624080248.3701-1-chris@chris-wilson.co.uk> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> Message-ID: <159299844389.19238.13268490509287233322@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL URL : https://patchwork.freedesktop.org/series/78767/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:184:13: warning: cast to restricted __le32 From karthik.b.s at intel.com Wed Jun 24 11:39:49 2020 From: karthik.b.s at intel.com (Karthik B S) Date: Wed, 24 Jun 2020 17:09:49 +0530 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler In-Reply-To: <20200617153038.GM6112@intel.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-2-karthik.b.s@intel.com> <0c4f01e093ad373bad5449ff01ae41df18e88d56.camel@intel.com> <CAKMK7uGHWqReNX9eUPpUyfgUtsNK2neT1wuK3C-tS1eBbDzX=g@mail.gmail.com> <20200617153038.GM6112@intel.com> Message-ID: <040a49c0-b945-31ab-35f3-8c477662f7e1@intel.com> On 6/17/2020 9:00 PM, Ville Syrj?l? wrote: > On Wed, Jun 17, 2020 at 11:58:10AM +0200, Daniel Vetter wrote: >> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote: >>> Em qui, 2020-05-28 ?s 11:09 +0530, Karthik B S escreveu: >>>> Add enable/disable flip done functions and the flip done handler >>>> function which handles the flip done interrupt. >>>> >>>> Enable the flip done interrupt in IER. >>>> >>>> Enable flip done function is called before writing the >>>> surface address register as the write to this register triggers >>>> the flip done interrupt >>>> >>>> Flip done handler is used to send the page flip event as soon as the >>>> surface address is written as per the requirement of async flips. >>>> The interrupt is disabled after the event is sent. >>>> >>>> v2: -Change function name from icl_* to skl_* (Paulo) >>>> -Move flip handler to this patch (Paulo) >>>> -Remove vblank_put() (Paulo) >>>> -Enable flip done interrupt for gen9+ only (Paulo) >>>> -Enable flip done interrupt in power_well_post_enable hook (Paulo) >>>> -Removed the event check in flip done handler to handle async >>>> flips without pageflip events. >>>> >>>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) >>>> -Make the pending vblank event NULL in the begining of >>>> flip_done_handler to remove sporadic WARN_ON that is seen. >>>> >>>> Signed-off-by: Karthik B S <karthik.b.s at intel.com> >>>> --- >>>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++ >>>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++ >>>> drivers/gpu/drm/i915/i915_irq.h | 2 + >>>> 3 files changed, 64 insertions(+) >>>> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >>>> index f40b909952cc..48cc1fc9bc5a 100644 >>>> --- a/drivers/gpu/drm/i915/display/intel_display.c >>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c >>>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >>>> >>>> intel_dbuf_pre_plane_update(state); >>>> >>>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>>> + if (new_crtc_state->uapi.async_flip) { >>>> + skl_enable_flip_done(&crtc->base); >>>> + break; >>>> + } >>>> + } >>>> + >>>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */ >>>> dev_priv->display.commit_modeset_enables(state); >>>> >>>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) >>>> drm_atomic_helper_wait_for_flip_done(dev, &state->base); >>>> >>>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >>>> + if (new_crtc_state->uapi.async_flip) >>>> + skl_disable_flip_done(&crtc->base); >>>> + >>>> if (new_crtc_state->hw.active && >>>> !needs_modeset(new_crtc_state) && >>>> !new_crtc_state->preload_luts && >>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >>>> index efdd4c7b8e92..632e7b1deb87 100644 >>>> --- a/drivers/gpu/drm/i915/i915_irq.c >>>> +++ b/drivers/gpu/drm/i915/i915_irq.c >>>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, >>>> u32 crc4) {} >>>> #endif >>>> >>>> +static void flip_done_handler(struct drm_i915_private *dev_priv, >>>> + unsigned int pipe) >>>> +{ >>>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); >>>> + struct drm_crtc_state *crtc_state = crtc->base.state; >>>> + struct drm_pending_vblank_event *e = crtc_state->event; >>>> + struct drm_device *dev = &dev_priv->drm; >>>> + unsigned long irqflags; >>>> + >>>> + crtc_state->event = NULL; >>>> + >>>> + spin_lock_irqsave(&dev->event_lock, irqflags); >>>> + >>>> + drm_crtc_send_vblank_event(&crtc->base, e); >>> >>> I don't think this is what we want. With this, the events the Kernel >>> sends us all have the same sequence and timestamp. In fact, the IGT >>> test you submitted fails because of this. >>> >>> In my original hackish proof-of-concept patch I had changed >>> drm_update_vblank_count() to force diff=1 in order to always send >>> events and I also changed g4x_get_vblank_counter() to get the counter >>> from FLIPCOUNT (which updates every time there's a flip) instead of >>> FRMCOUNT (which doesn't seem to increment when you do async flips). >>> That is a drastic change, but the patch was just a PoC so I didn't care >>> about keeping anything else working. >>> >>> One thing that confused me a little bit when dealing the the >>> vblank/flip event interface from drm.ko is that "flips" and "vblanks" >>> seem to be changed interchangeably, which is confusing for async flips: >>> if you keep forever doing async flips in the very first few scanlines >>> you never actually reach the "vblank" period, yet you keep flipping >>> your frame. Then, what should your expectation regarding events be? >> >> Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR >> where that changes), no idea why we can't keep sending out vblank >> interrupts. >> >> Now flip events look maybe conflated in drm.ko code with vblank events >> since most of the time a flip complete happens at exactly the same time >> the vblank event. But for async flip this is not the case. >> >> Probably worth it to have new helpers/function in drm_vblank.c for >> async flips, so that this is less confusing. Plus good documentation. > > We're going to need three different ways to calculate the flip > timestamps: sync flip, vrr sync flip, async flip. > > First one we handle just fine currently since we know know when > the timestamp was sampled and when the vblank ends so we can do > the appropriate correction. > > VRR is going to be a bit more interesting since we don't really know how > long the vblank will be. I think we may have to use the frame timestamp > and current timestamp counter to first convert the monotonic timestamp > to correlate with the start of the vblank exit, and then we can move it > forward by the fixed (I think) length of the vblank exit procedure. > > For async flip I think we may want to do something similar with the > flip done timestamp and current timestamp (apart from adding the > fixed length of the vblank exit procedure of course, since there > is no vblank exit). Although I'm not entirely sure what we should do > if we do the async flip during the vblank. If we want to maintain > that the timestamp always correlates with the first pixel actually > getting scanned out then we should still correct the timestamp to > point past the end of vblank. And even with the corrections there > will be some amount of error due to the old data first having to > drain out of the FIFO. That error I think we're just going to > have to accept. > > Not sure how much surgery all that is going to require to the vblank > timestamping code. Thanks for the review. I'll check what changes needs to be done for this in the timestamping code and find the right implementation for timestamps based on your inputs. Thanks and Regards, Karthik.B.S > From karthik.b.s at intel.com Wed Jun 24 11:53:10 2020 From: karthik.b.s at intel.com (Karthik B S) Date: Wed, 24 Jun 2020 17:23:10 +0530 Subject: [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips In-Reply-To: <20200617155719.GN6112@intel.com> References: <20200528053931.29282-1-karthik.b.s@intel.com> <20200528053931.29282-4-karthik.b.s@intel.com> <20200617155719.GN6112@intel.com> Message-ID: <5a4f9bfe-6664-e388-6a69-bf5aa89087b9@intel.com> On 6/17/2020 9:27 PM, Ville Syrj?l? wrote: > On Thu, May 28, 2020 at 11:09:29AM +0530, Karthik B S wrote: >> Support added only for async flips on primary plane. >> If flip is requested on any other plane, reject it. >> >> Make sure there is no change in fbc, offset and framebuffer modifiers >> when async flip is requested. >> >> If any of these are modified, reject async flip. >> >> v2: -Replace DRM_ERROR (Paulo) >> -Add check for changes in OFFSET, FBC, RC(Paulo) >> >> v3: -Removed TODO as benchmarking tests have been run now. >> >> Signed-off-by: Karthik B S <karthik.b.s at intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++++++++ >> 1 file changed, 55 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> index eb1c360431ae..2307f924732c 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_display.c >> @@ -14798,6 +14798,53 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, >> return false; >> } >> >> +static int intel_atomic_check_async(struct intel_atomic_state *state) >> +{ >> + struct drm_plane *plane; >> + struct drm_plane_state *plane_state; >> + struct intel_crtc_state *old_crtc_state, *new_crtc_state; >> + struct intel_plane_state *new_plane_state, *old_plane_state; >> + struct intel_crtc *crtc; >> + struct intel_plane *intel_plane; >> + int i, j; >> + >> + /*FIXME: Async flip is only supported for primary plane currently >> + * Support for overlays to be added. >> + */ >> + for_each_new_plane_in_state(&state->base, plane, plane_state, j) { >> + if (plane->type != DRM_PLANE_TYPE_PRIMARY) { > > I think skl+ can do async flips on any universal planes. Earlier > platforms were limited to primary only I think. Can't remember if g4x > already had usable async flip via mmio. Pretty sure at least ilk+ had > it. > Thanks for the review. Sure I'll update this. > Also intel_ types are preferred, so this should use those, and I > think since we're talking about hw planes we should rather check for > PLANE_PRIMARY here. Sure, I'll change this. > >> + DRM_DEBUG_KMS("Async flips is NOT supported for non-primary plane\n"); >> + return -EINVAL; >> + } >> + } >> + >> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, >> + new_crtc_state, i) { >> + if (old_crtc_state->enable_fbc != new_crtc_state->enable_fbc) { > > enable_fbc is bork, so this probably doesn't do anything particularly > sensible. > Sure. I'll remove this. >> + DRM_DEBUG_KMS("FBC status cannot be changed in async flip\n"); >> + return -EINVAL; >> + } >> + } >> + >> + for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state, >> + new_plane_state, i) { >> + if ((old_plane_state->color_plane[0].x != >> + new_plane_state->color_plane[0].x) || >> + (old_plane_state->color_plane[0].y != >> + new_plane_state->color_plane[0].y)) { > > Don't think we've even calculated those by the time you call this. So > this stuff has to be called much later I think. > Sure. I'll check this and move it to the right place. >> + DRM_DEBUG_KMS("Offsets cannot be changed in async\n"); >> + return -EINVAL; >> + } >> + >> + if (old_plane_state->uapi.fb->modifier != >> + new_plane_state->uapi.fb->modifier) { > > We seem to be missing a lot of state here. Basically I think async flip > can *only* change the plane surface address, so anything else changing > we should reject. I guess if this comes in via the legacy page flip path > the code/helpers do prevent most other things changing, but not sure. > I don't really like relying on such core checks since someone could > blindly expose this via the atomic ioctl without having those same > restrictions in place. > Yes. I have not added the checks which were present in the legacy page flip path. Does it mean that I should add those checks also in here? Or Am I missing something in understanding the comment? Is there any other way to make sure only the plane surface address is changing. > We might also want a dedicated plane hook for async flips since writing > all the plane registers for these is rather pointless. I'm not even sure > what happens with all the other double buffered registers if you write > them and then do an async surface address update. > Sure. I'll make a dedicated plane hook for async flips so that we only update the Surface address register here. > Also if we want more accurate timestmaps based on the flip timestamp > register then we're going to have to limit async flips to single plane > per pipe at a time becasue the timestamp can only be sampled from > a single plane. > Sure. I'll make sure async flips are limited to a single plane per pipe. >> + DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n"); >> + return -EINVAL; >> + } >> + } >> + return 0; >> +} >> + >> /** >> * intel_atomic_check - validate state object >> * @dev: drm device >> @@ -14825,6 +14872,14 @@ static int intel_atomic_check(struct drm_device *dev, >> if (ret) >> goto fail; >> >> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { >> + if (new_crtc_state->uapi.async_flip) { >> + ret = intel_atomic_check_async(state); > > Kinda redundant to call this multiple times. I think the async_flip flag > is actually misplaced. It should probably be in the drm_atomic_state > instead of the crtc state. > > Also still not a huge fan of using the "async flip" termonology in > the drm core. IMO we should just adopt the vulkan terminology for > this stuff so it's obviuos what people mean when they talk about these > things. A little lost here.Could you please help me out? I should move the async_flip flag to drm_atomic_state from crtc_state and then change its name? What would be the proper vulkan terminology for this? Thanks and Regards, Karthik.B.S > >> + if (ret) >> + goto fail; >> + } >> + } >> + >> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, >> new_crtc_state, i) { >> if (!needs_modeset(new_crtc_state)) { >> -- >> 2.17.1 > From patchwork at emeril.freedesktop.org Wed Jun 24 11:54:46 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 11:54:46 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_mm/mmu=5Fnotifier=3A_Mark_up_direct?= =?utf-8?q?_reclaim_paths_with_MAYFAIL?= In-Reply-To: <20200624080248.3701-1-chris@chris-wilson.co.uk> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> Message-ID: <159299968673.19235.6946991787243611544@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL URL : https://patchwork.freedesktop.org/series/78767/ State : success == Summary == CI Bug Log - changes from CI_DRM_8661 -> Patchwork_18017 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/index.html Known issues ------------ Here are the changes found in Patchwork_18017 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [PASS][5] -> [INCOMPLETE][6] ([i915#1932]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [FAIL][11] ([i915#1888]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-dsi/igt at i915_module_load@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18017 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18017: 27ef1b293f573a01bbb73738a96ea64211628733 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 27ef1b293f57 drm/i915/gem: Use mmu_notifier_range_mayfail() to avoid waiting inside reclaim 0ef970ee1137 mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18017/index.html From patchwork at emeril.freedesktop.org Wed Jun 24 11:58:12 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 11:58:12 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B01/26=5D_Revert_=22drm/i915/gem=3A_?= =?utf-8?q?Async_GPU_relocations_only=22_=28rev2=29?= In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <159299989281.19235.2106322241332844046@emeril.freedesktop.org> == Series Details == Series: series starting with [01/26] Revert "drm/i915/gem: Async GPU relocations only" (rev2) URL : https://patchwork.freedesktop.org/series/78744/ State : warning == Summary == $ dim checkpatch origin/drm-tip 33892249d7d2 Revert "drm/i915/gem: Async GPU relocations only" -:113: WARNING:MEMORY_BARRIER: memory barrier without comment #113: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1102: + mb(); -:161: WARNING:MEMORY_BARRIER: memory barrier without comment #161: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1150: + mb(); -:181: CHECK:SPACING: No space is necessary after a cast #181: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1170: + io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr)); -:260: WARNING:MEMORY_BARRIER: memory barrier without comment #260: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1249: + mb(); -:274: CHECK:BRACES: Unbalanced braces around else statement #274: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1263: + } else total: 0 errors, 3 warnings, 2 checks, 455 lines checked cfe75ea198f9 drm/i915: Revert relocation chaining commits. -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: This reverts commit 964a9b0f611ee ("drm/i915/gem: Use chained reloc batches") -:221: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV) #221: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1306: + if (cache->rq_size > PAGE_SIZE/sizeof(u32) - (len + 1)) ^ total: 0 errors, 1 warnings, 1 checks, 281 lines checked 5fed26bab5d0 Revert "drm/i915/gem: Drop relocation slowpath". -:80: WARNING:LINE_SPACING: Missing a blank line after declarations #80: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1700: + int err = __get_user(c, addr); + if (err) total: 0 errors, 1 warnings, 0 checks, 267 lines checked 1de69bb5eb4b drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. -:484: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #484: FILE: drivers/gpu/drm/i915/i915_gem.c:1359: + while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { total: 0 errors, 1 warnings, 0 checks, 465 lines checked 28e0198d22f8 drm/i915: Remove locking from i915_gem_object_prepare_read/write d782b8ba0104 drm/i915: Parse command buffer earlier in eb_relocate(slow) c4c86dc1e12b Revert "drm/i915/gem: Split eb_vma into its own allocation" 8394062c0fec drm/i915/gem: Make eb_add_lut interruptible wait on object lock. 61248b8339e2 drm/i915: Use per object locking in execbuf, v12. -:473: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #473: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1404: +static int __reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, -:493: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #493: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1477: +static int reloc_entry_gpu(struct i915_execbuffer *eb, struct i915_vma *vma, -:505: ERROR:TRAILING_WHITESPACE: trailing whitespace #505: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1502: +^I$ -:782: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #782: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2873: + eb.reloc_pool = eb.batch_pool = NULL; total: 1 errors, 0 warnings, 3 checks, 885 lines checked 213e5283007d drm/i915: Use ww locking in intel_renderstate. -:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #10: Convert to using ww-waiting, and make sure we always pin intel_context_state, total: 0 errors, 1 warnings, 0 checks, 190 lines checked 209fd4f2593e drm/i915: Add ww context handling to context_barrier_task -:19: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #19: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.c:1097: + int (*pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void *data), total: 0 errors, 1 warnings, 0 checks, 146 lines checked 5e4739f5ae98 drm/i915: Nuke arguments to eb_pin_engine 47202c503661 drm/i915: Pin engine before pinning all objects, v4. bf7884fb26e5 drm/i915: Rework intel_context pinning to do everything outside of pin_mutex -:125: CHECK:LINE_SPACING: Please don't use multiple blank lines #125: FILE: drivers/gpu/drm/i915/gt/intel_context.c:176: + + -:338: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #338: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:3453: + *vaddr = i915_gem_object_pin_map(ce->state->obj, + i915_coherent_map_type(ce->engine->i915) | total: 0 errors, 0 warnings, 2 checks, 435 lines checked b4e39defb35f drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. -:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #95: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:594: + err = i915_vma_pin_ww(vma, &eb->ww, entry->pad_to_size, entry->alignment, -:204: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line #204: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2386: + * hsw should have this fixed, but bdw mucks it up again. */ total: 0 errors, 1 warnings, 1 checks, 842 lines checked f5d541f77361 drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. fb75fcfbd9d4 drm/i915: Kill last user of intel_context_create_request outside of selftests fe5408b9aa3f drm/i915: Convert i915_perf to ww locking as well e69c9075e596 drm/i915: Dirty hack to fix selftests locking inversion c5b10d3c7174 drm/i915/selftests: Fix locking inversion in lrc selftest. 49fb1cb8bfae drm/i915: Use ww pinning for intel_context_create_request() 756762ec32c7 drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2. dde2896028bb drm/i915: Add ww locking to vm_fault_gtt -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 91 lines checked 501388d7472e drm/i915: Add ww locking to pin_to_display_plane -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 129 lines checked 1d2a412696af drm/i915: Ensure we hold the pin mutex -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 39 lines checked 076ef058d638 drm/i915: Kill context before taking ctx->mutex From patchwork at emeril.freedesktop.org Wed Jun 24 11:59:29 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 11:59:29 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5B01/26=5D_Revert_=22drm/i915/gem=3A_Asyn?= =?utf-8?q?c_GPU_relocations_only=22_=28rev2=29?= In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <159299996926.19237.9506327803399612983@emeril.freedesktop.org> == Series Details == Series: series starting with [01/26] Revert "drm/i915/gem: Async GPU relocations only" (rev2) URL : https://patchwork.freedesktop.org/series/78744/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From chris at chris-wilson.co.uk Wed Jun 24 12:21:03 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 13:21:03 +0100 Subject: [Intel-gfx] [PATCH 1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL In-Reply-To: <20200624121053.GD6578@ziepe.ca> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> <20200624121053.GD6578@ziepe.ca> Message-ID: <159300126338.4527.3968787379471939056@build.alporthouse.com> Quoting Jason Gunthorpe (2020-06-24 13:10:53) > On Wed, Jun 24, 2020 at 09:02:47AM +0100, Chris Wilson wrote: > > When direct reclaim enters the shrinker and tries to reclaim pages, it > > has to opportunitically unmap them [try_to_unmap_one]. For direct > > reclaim, the calling context is unknown and may include attempts to > > unmap one page of a dma object while attempting to allocate more pages > > for that object. Pass the information along that we are inside an > > opportunistic unmap that can allow that page to remain referenced and > > mapped, and let the callback opt in to avoiding a recursive wait. > > i915 should already not be holding locks shared with the notifiers > across allocations that can trigger reclaim. This is already required > to use notifiers correctly anyhow - why do we need something in the > notifiers? for (n = 0; n < num_pages; n++) pin_user_page() may call try_to_unmap_page from the lru shrinker for [0, n-1]. We're in the middle of allocating the object, how are we best to untangle that? Or during allocation of something that is using the pages pinned by that object, how are we best to not to shrink that object as there is a mutual dependency? -Chris From patchwork at emeril.freedesktop.org Wed Jun 24 12:48:04 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 12:48:04 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B01/26=5D_Revert_=22drm/i915/gem=3A_Async_G?= =?utf-8?q?PU_relocations_only=22_=28rev2=29?= In-Reply-To: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> Message-ID: <159300288488.19235.13021529373852109099@emeril.freedesktop.org> == Series Details == Series: series starting with [01/26] Revert "drm/i915/gem: Async GPU relocations only" (rev2) URL : https://patchwork.freedesktop.org/series/78744/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8661 -> Patchwork_18018 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18018 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18018, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18018: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at gem_contexts: - fi-cfl-8109u: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-cfl-8109u/igt at i915_selftest@live at gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-cfl-8109u/igt at i915_selftest@live at gem_contexts.html * igt at i915_selftest@live at gem_execbuf: - fi-skl-6600u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-skl-6600u/igt at i915_selftest@live at gem_execbuf.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-skl-6600u/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-8809g: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-8809g/igt at i915_selftest@live at gem_execbuf.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-kbl-8809g/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-x1275: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at i915_selftest@live at gem_execbuf.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-kbl-x1275/igt at i915_selftest@live at gem_execbuf.html - fi-cfl-guc: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-cfl-guc/igt at i915_selftest@live at gem_execbuf.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-cfl-guc/igt at i915_selftest@live at gem_execbuf.html - fi-kbl-soraka: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-soraka/igt at i915_selftest@live at gem_execbuf.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-kbl-soraka/igt at i915_selftest@live at gem_execbuf.html - fi-snb-2600: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-snb-2600/igt at i915_selftest@live at gem_execbuf.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-snb-2600/igt at i915_selftest@live at gem_execbuf.html - fi-bsw-n3050: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-bsw-n3050/igt at i915_selftest@live at gem_execbuf.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-bsw-n3050/igt at i915_selftest@live at gem_execbuf.html - fi-tgl-u2: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at i915_selftest@live at gem_execbuf.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-tgl-u2/igt at i915_selftest@live at gem_execbuf.html - fi-cml-u2: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-cml-u2/igt at i915_selftest@live at gem_execbuf.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-cml-u2/igt at i915_selftest@live at gem_execbuf.html - fi-cfl-8700k: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-cfl-8700k/igt at i915_selftest@live at gem_execbuf.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-cfl-8700k/igt at i915_selftest@live at gem_execbuf.html - fi-hsw-4770: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-hsw-4770/igt at i915_selftest@live at gem_execbuf.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-hsw-4770/igt at i915_selftest@live at gem_execbuf.html - fi-icl-u2: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at i915_selftest@live at gem_execbuf.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-icl-u2/igt at i915_selftest@live at gem_execbuf.html - fi-snb-2520m: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-snb-2520m/igt at i915_selftest@live at gem_execbuf.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-snb-2520m/igt at i915_selftest@live at gem_execbuf.html * igt at runner@aborted: - fi-snb-2520m: NOTRUN -> [FAIL][29] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-snb-2520m/igt at runner@aborted.html - fi-snb-2600: NOTRUN -> [FAIL][30] [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-snb-2600/igt at runner@aborted.html - fi-elk-e7500: NOTRUN -> [FAIL][31] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-elk-e7500/igt at runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at gem_contexts: - {fi-kbl-7560u}: [PASS][32] -> [DMESG-WARN][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-7560u/igt at i915_selftest@live at gem_contexts.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-kbl-7560u/igt at i915_selftest@live at gem_contexts.html * igt at i915_selftest@live at gem_execbuf: - {fi-tgl-dsi}: [PASS][34] -> [INCOMPLETE][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-dsi/igt at i915_selftest@live at gem_execbuf.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-tgl-dsi/igt at i915_selftest@live at gem_execbuf.html Known issues ------------ Here are the changes found in Patchwork_18018 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][36] -> [DMESG-WARN][37] ([i915#1982]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at blt: - fi-snb-2600: [PASS][38] -> [INCOMPLETE][39] ([i915#82]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-snb-2600/igt at i915_selftest@live at blt.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-snb-2600/igt at i915_selftest@live at blt.html * igt at i915_selftest@live at gem_execbuf: - fi-elk-e7500: [PASS][40] -> [INCOMPLETE][41] ([i915#66]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-elk-e7500/igt at i915_selftest@live at gem_execbuf.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-elk-e7500/igt at i915_selftest@live at gem_execbuf.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][42] -> [DMESG-WARN][43] ([i915#402]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][44] ([i915#1888]) -> [PASS][45] [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - {fi-tgl-dsi}: [DMESG-WARN][46] ([i915#1982]) -> [PASS][47] +2 similar issues [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-tgl-dsi/igt at i915_module_load@reload.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-tgl-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][48] ([i915#1982]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html #### Warnings #### * igt at kms_pipe_crc_basic@read-crc-pipe-b: - fi-kbl-x1275: [DMESG-WARN][50] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][51] ([i915#62] / [i915#92]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-b.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][52] ([i915#62] / [i915#92]) -> [DMESG-WARN][53] ([i915#62] / [i915#92] / [i915#95]) +7 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#66]: https://gitlab.freedesktop.org/drm/intel/issues/66 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18018 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18018: 076ef058d63845db621e8d9149589dcb390e37e5 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 076ef058d638 drm/i915: Kill context before taking ctx->mutex 1d2a412696af drm/i915: Ensure we hold the pin mutex 501388d7472e drm/i915: Add ww locking to pin_to_display_plane dde2896028bb drm/i915: Add ww locking to vm_fault_gtt 756762ec32c7 drm/i915: Move i915_vma_lock in the selftests to avoid lock inversion, v2. 49fb1cb8bfae drm/i915: Use ww pinning for intel_context_create_request() c5b10d3c7174 drm/i915/selftests: Fix locking inversion in lrc selftest. e69c9075e596 drm/i915: Dirty hack to fix selftests locking inversion fe5408b9aa3f drm/i915: Convert i915_perf to ww locking as well fb75fcfbd9d4 drm/i915: Kill last user of intel_context_create_request outside of selftests f5d541f77361 drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2. b4e39defb35f drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. bf7884fb26e5 drm/i915: Rework intel_context pinning to do everything outside of pin_mutex 47202c503661 drm/i915: Pin engine before pinning all objects, v4. 5e4739f5ae98 drm/i915: Nuke arguments to eb_pin_engine 209fd4f2593e drm/i915: Add ww context handling to context_barrier_task 213e5283007d drm/i915: Use ww locking in intel_renderstate. 61248b8339e2 drm/i915: Use per object locking in execbuf, v12. 8394062c0fec drm/i915/gem: Make eb_add_lut interruptible wait on object lock. c4c86dc1e12b Revert "drm/i915/gem: Split eb_vma into its own allocation" d782b8ba0104 drm/i915: Parse command buffer earlier in eb_relocate(slow) 28e0198d22f8 drm/i915: Remove locking from i915_gem_object_prepare_read/write 1de69bb5eb4b drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. 5fed26bab5d0 Revert "drm/i915/gem: Drop relocation slowpath". cfe75ea198f9 drm/i915: Revert relocation chaining commits. 33892249d7d2 Revert "drm/i915/gem: Async GPU relocations only" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18018/index.html From patchwork at emeril.freedesktop.org Wed Jun 24 13:44:56 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 13:44:56 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/display/rkl=3A_Implement_W?= =?utf-8?q?A_14011471926?= In-Reply-To: <20200623215235.125665-1-jose.souza@intel.com> References: <20200623215235.125665-1-jose.souza@intel.com> Message-ID: <159300629632.19238.12460931133524104554@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/display/rkl: Implement WA 14011471926 URL : https://patchwork.freedesktop.org/series/78761/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8661_full -> Patchwork_18015_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18015_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18015_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18015_full: ### IGT changes ### #### Possible regressions #### * igt at kms_hdmi_inject@inject-audio: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb1/igt at kms_hdmi_inject@inject-audio.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-tglb7/igt at kms_hdmi_inject@inject-audio.html * igt at runner@aborted: - shard-tglb: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-tglb7/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_18015_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at vcs0: - shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#198]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl7/igt at gem_ctx_isolation@preservation-s3 at vcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl5/igt at gem_ctx_isolation@preservation-s3 at vcs0.html * igt at gem_ctx_persistence@close-replace-race: - shard-glk: [PASS][6] -> [TIMEOUT][7] ([i915#1340] / [i915#1958]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk6/igt at gem_ctx_persistence@close-replace-race.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-glk6/igt at gem_ctx_persistence@close-replace-race.html * igt at gem_exec_create@madvise: - shard-glk: [PASS][8] -> [DMESG-WARN][9] ([i915#118] / [i915#95]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk6/igt at gem_exec_create@madvise.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-glk6/igt at gem_exec_create@madvise.html * igt at gem_fenced_exec_thrash@too-many-fences: - shard-snb: [PASS][10] -> [INCOMPLETE][11] ([i915#82]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-snb2/igt at gem_fenced_exec_thrash@too-many-fences.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-snb6/igt at gem_fenced_exec_thrash@too-many-fences.html * igt at gem_userptr_blits@map-fixed-invalidate at gtt: - shard-tglb: [PASS][12] -> [DMESG-WARN][13] ([i915#402]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb7/igt at gem_userptr_blits@map-fixed-invalidate at gtt.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-tglb6/igt at gem_userptr_blits@map-fixed-invalidate at gtt.html * igt at i915_pm_rpm@system-suspend-execbuf: - shard-kbl: [PASS][14] -> [INCOMPLETE][15] ([i915#151] / [i915#155]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl7/igt at i915_pm_rpm@system-suspend-execbuf.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl6/igt at i915_pm_rpm@system-suspend-execbuf.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl3/igt at i915_suspend@forcewake.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl1/igt at i915_suspend@forcewake.html * igt at i915_suspend@sysfs-reader: - shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#1635] / [i915#95]) +15 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at i915_suspend@sysfs-reader.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl7/igt at i915_suspend@sysfs-reader.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-iclb: [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-iclb4/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-iclb3/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [PASS][22] -> [DMESG-FAIL][23] ([i915#54] / [i915#95]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl6/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [PASS][24] -> [DMESG-WARN][25] ([i915#1982]) +13 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl8/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: - shard-kbl: [PASS][26] -> [DMESG-FAIL][27] ([fdo#108145] / [i915#54] / [i915#95]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl6/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][28] -> [DMESG-FAIL][29] ([i915#1635] / [i915#95]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl7/igt at kms_flip_tiling@flip-changes-tiling.html - shard-kbl: [PASS][30] -> [DMESG-FAIL][31] ([i915#95]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt: - shard-tglb: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb6/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-tglb8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][34] -> [FAIL][35] ([i915#1188]) +1 similar issue [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl1/igt at kms_hdr@bpc-switch-dpms.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#69]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#93] / [i915#95]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][40] -> [FAIL][41] ([fdo#108145] / [i915#265]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl3/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_setmode@basic: - shard-kbl: [PASS][42] -> [FAIL][43] ([i915#31]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl3/igt at kms_setmode@basic.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl4/igt at kms_setmode@basic.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][44] -> [FAIL][45] ([i915#1820]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl4/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [FAIL][46] ([i915#1528]) -> [PASS][47] [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl9/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl5/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][48] ([i915#1930]) -> [PASS][49] [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-contexts: - shard-glk: [DMESG-WARN][50] ([i915#118] / [i915#95]) -> [PASS][51] [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk7/igt at gem_exec_whisper@basic-contexts.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-glk9/igt at gem_exec_whisper@basic-contexts.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][52] ([i915#402]) -> [PASS][53] +2 similar issues [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb7/igt at i915_module_load@reload.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-tglb5/igt at i915_module_load@reload.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +3 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_color@pipe-a-ctm-0-5.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl8/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_cursor_crc@pipe-c-cursor-128x128-rapid-movement: - shard-apl: [DMESG-WARN][56] ([i915#1635] / [i915#95]) -> [PASS][57] +16 similar issues [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl1/igt at kms_cursor_crc@pipe-c-cursor-128x128-rapid-movement.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl8/igt at kms_cursor_crc@pipe-c-cursor-128x128-rapid-movement.html * igt at kms_cursor_legacy@flip-vs-cursor-legacy: - shard-apl: [FAIL][58] ([IGT#5]) -> [PASS][59] [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl3/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl1/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html - shard-skl: [DMESG-FAIL][60] ([i915#1982]) -> [PASS][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2: - shard-glk: [FAIL][62] ([i915#79]) -> [PASS][63] +1 similar issue [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-glk1/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][64] ([i915#180]) -> [PASS][65] +5 similar issues [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [FAIL][66] ([i915#1928]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl8/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [FAIL][68] ([i915#699]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl1/igt at kms_flip_tiling@flip-changes-tiling.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl4/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][70] ([fdo#108145] / [i915#265]) -> [PASS][71] +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [TIMEOUT][72] ([i915#1635] / [i915#1958]) -> [INCOMPLETE][73] ([i915#1635] / [i915#1958]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at gem_exec_reloc@basic-concurrent16.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl6/igt at gem_exec_reloc@basic-concurrent16.html * igt at kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: [SKIP][74] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][75] ([fdo#109271] / [fdo#111827]) +2 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl1/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl3/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [DMESG-FAIL][76] ([i915#1635] / [i915#95]) -> [FAIL][77] ([i915#1525]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl1/igt at kms_fbcon_fbt@fbc-suspend.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl3/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite: - shard-apl: [SKIP][78] ([fdo#109271] / [i915#1635]) -> [SKIP][79] ([fdo#109271]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl7/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl2/igt at kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-apl: [SKIP][80] ([fdo#109271]) -> [SKIP][81] ([fdo#109271] / [i915#1635]) +5 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-apl7/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: [FAIL][82] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][83] ([fdo#108145] / [i915#1982]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1340]: https://gitlab.freedesktop.org/drm/intel/issues/1340 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18015 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18015: b6b9f0c4c19d69b948abeeecd9850c72f02875ef @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18015/index.html From chris at chris-wilson.co.uk Wed Jun 24 14:12:42 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 15:12:42 +0100 Subject: [Intel-gfx] [PATCH 1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL In-Reply-To: <20200624123910.GA3178169@ziepe.ca> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> <20200624121053.GD6578@ziepe.ca> <159300126338.4527.3968787379471939056@build.alporthouse.com> <20200624123910.GA3178169@ziepe.ca> Message-ID: <159300796224.4527.2014771396582759689@build.alporthouse.com> Quoting Jason Gunthorpe (2020-06-24 13:39:10) > On Wed, Jun 24, 2020 at 01:21:03PM +0100, Chris Wilson wrote: > > Quoting Jason Gunthorpe (2020-06-24 13:10:53) > > > On Wed, Jun 24, 2020 at 09:02:47AM +0100, Chris Wilson wrote: > > > > When direct reclaim enters the shrinker and tries to reclaim pages, it > > > > has to opportunitically unmap them [try_to_unmap_one]. For direct > > > > reclaim, the calling context is unknown and may include attempts to > > > > unmap one page of a dma object while attempting to allocate more pages > > > > for that object. Pass the information along that we are inside an > > > > opportunistic unmap that can allow that page to remain referenced and > > > > mapped, and let the callback opt in to avoiding a recursive wait. > > > > > > i915 should already not be holding locks shared with the notifiers > > > across allocations that can trigger reclaim. This is already required > > > to use notifiers correctly anyhow - why do we need something in the > > > notifiers? > > > > for (n = 0; n < num_pages; n++) > > pin_user_page() > > > > may call try_to_unmap_page from the lru shrinker for [0, n-1]. > > Yes, of course you can't hold any locks that intersect with notifiers > across pin_user_page()/get_user_page() What lock though? It's just the page refcount, shrinker asks us to drop it [via mmu], we reply we would like to keep using that page as freeing it for the current allocation is "robbing Peter to pay Paul". -Chris From chris at chris-wilson.co.uk Wed Jun 24 14:21:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 15:21:49 +0100 Subject: [Intel-gfx] [PATCH 1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL In-Reply-To: <20200624141604.GH6578@ziepe.ca> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> <20200624121053.GD6578@ziepe.ca> <159300126338.4527.3968787379471939056@build.alporthouse.com> <20200624123910.GA3178169@ziepe.ca> <159300796224.4527.2014771396582759689@build.alporthouse.com> <20200624141604.GH6578@ziepe.ca> Message-ID: <159300850942.4527.8335506003268197914@build.alporthouse.com> Quoting Jason Gunthorpe (2020-06-24 15:16:04) > On Wed, Jun 24, 2020 at 03:12:42PM +0100, Chris Wilson wrote: > > Quoting Jason Gunthorpe (2020-06-24 13:39:10) > > > On Wed, Jun 24, 2020 at 01:21:03PM +0100, Chris Wilson wrote: > > > > Quoting Jason Gunthorpe (2020-06-24 13:10:53) > > > > > On Wed, Jun 24, 2020 at 09:02:47AM +0100, Chris Wilson wrote: > > > > > > When direct reclaim enters the shrinker and tries to reclaim pages, it > > > > > > has to opportunitically unmap them [try_to_unmap_one]. For direct > > > > > > reclaim, the calling context is unknown and may include attempts to > > > > > > unmap one page of a dma object while attempting to allocate more pages > > > > > > for that object. Pass the information along that we are inside an > > > > > > opportunistic unmap that can allow that page to remain referenced and > > > > > > mapped, and let the callback opt in to avoiding a recursive wait. > > > > > > > > > > i915 should already not be holding locks shared with the notifiers > > > > > across allocations that can trigger reclaim. This is already required > > > > > to use notifiers correctly anyhow - why do we need something in the > > > > > notifiers? > > > > > > > > for (n = 0; n < num_pages; n++) > > > > pin_user_page() > > > > > > > > may call try_to_unmap_page from the lru shrinker for [0, n-1]. > > > > > > Yes, of course you can't hold any locks that intersect with notifiers > > > across pin_user_page()/get_user_page() > > > > What lock though? It's just the page refcount, shrinker asks us to drop > > it [via mmu], we reply we would like to keep using that page as freeing > > it for the current allocation is "robbing Peter to pay Paul". > > Maybe I'm unclear what this series is actually trying to fix? > > You said "avoiding a recursive wait" which sounds like some locking > deadlock to me. It's the shrinker being called while we are allocating for/on behalf of the object. As we are actively using the object, we don't want to free it -- the partial object allocation being the clearest, if the object consists of 2 pages, trying to free page 0 in order to allocate page 1 has to fail (and the shrinker should find another candidate to reclaim, or fail the allocation). -Chris From chris at chris-wilson.co.uk Wed Jun 24 14:37:32 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 15:37:32 +0100 Subject: [Intel-gfx] [PATCH 1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL In-Reply-To: <20200624142544.GI6578@ziepe.ca> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> <20200624121053.GD6578@ziepe.ca> <159300126338.4527.3968787379471939056@build.alporthouse.com> <20200624123910.GA3178169@ziepe.ca> <159300796224.4527.2014771396582759689@build.alporthouse.com> <20200624141604.GH6578@ziepe.ca> <159300850942.4527.8335506003268197914@build.alporthouse.com> <20200624142544.GI6578@ziepe.ca> Message-ID: <159300945202.4527.4366416413140642633@build.alporthouse.com> Quoting Jason Gunthorpe (2020-06-24 15:25:44) > On Wed, Jun 24, 2020 at 03:21:49PM +0100, Chris Wilson wrote: > > Quoting Jason Gunthorpe (2020-06-24 15:16:04) > > > On Wed, Jun 24, 2020 at 03:12:42PM +0100, Chris Wilson wrote: > > > > Quoting Jason Gunthorpe (2020-06-24 13:39:10) > > > > > On Wed, Jun 24, 2020 at 01:21:03PM +0100, Chris Wilson wrote: > > > > > > Quoting Jason Gunthorpe (2020-06-24 13:10:53) > > > > > > > On Wed, Jun 24, 2020 at 09:02:47AM +0100, Chris Wilson wrote: > > > > > > > > When direct reclaim enters the shrinker and tries to reclaim pages, it > > > > > > > > has to opportunitically unmap them [try_to_unmap_one]. For direct > > > > > > > > reclaim, the calling context is unknown and may include attempts to > > > > > > > > unmap one page of a dma object while attempting to allocate more pages > > > > > > > > for that object. Pass the information along that we are inside an > > > > > > > > opportunistic unmap that can allow that page to remain referenced and > > > > > > > > mapped, and let the callback opt in to avoiding a recursive wait. > > > > > > > > > > > > > > i915 should already not be holding locks shared with the notifiers > > > > > > > across allocations that can trigger reclaim. This is already required > > > > > > > to use notifiers correctly anyhow - why do we need something in the > > > > > > > notifiers? > > > > > > > > > > > > for (n = 0; n < num_pages; n++) > > > > > > pin_user_page() > > > > > > > > > > > > may call try_to_unmap_page from the lru shrinker for [0, n-1]. > > > > > > > > > > Yes, of course you can't hold any locks that intersect with notifiers > > > > > across pin_user_page()/get_user_page() > > > > > > > > What lock though? It's just the page refcount, shrinker asks us to drop > > > > it [via mmu], we reply we would like to keep using that page as freeing > > > > it for the current allocation is "robbing Peter to pay Paul". > > > > > > Maybe I'm unclear what this series is actually trying to fix? > > > > > > You said "avoiding a recursive wait" which sounds like some locking > > > deadlock to me. > > > > It's the shrinker being called while we are allocating for/on behalf of > > the object. As we are actively using the object, we don't want to free > > it -- the partial object allocation being the clearest, if the object > > consists of 2 pages, trying to free page 0 in order to allocate page 1 > > has to fail (and the shrinker should find another candidate to reclaim, > > or fail the allocation). > > mmu notifiers are not for influencing policy of the mm. It's policy is "this may fail" regardless of the mmu notifier at this point. That is not changed. Your suggestion is that we move the pages to the unevictable mapping so that the shrinker LRU is never invoked on pages we have grabbed with pin_user_page. Does that work with the rest of the mmu notifiers? -Chris From chris at chris-wilson.co.uk Wed Jun 24 17:58:49 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 18:58:49 +0100 Subject: [Intel-gfx] [PATCH 1/2] mm/mmu_notifier: Mark up direct reclaim paths with MAYFAIL In-Reply-To: <20200624165057.GJ6578@ziepe.ca> References: <20200624080248.3701-1-chris@chris-wilson.co.uk> <20200624121053.GD6578@ziepe.ca> <159300126338.4527.3968787379471939056@build.alporthouse.com> <20200624123910.GA3178169@ziepe.ca> <159300796224.4527.2014771396582759689@build.alporthouse.com> <20200624141604.GH6578@ziepe.ca> <159300850942.4527.8335506003268197914@build.alporthouse.com> <20200624142544.GI6578@ziepe.ca> <159300945202.4527.4366416413140642633@build.alporthouse.com> <20200624165057.GJ6578@ziepe.ca> Message-ID: <159302152915.4527.9099070806700792078@build.alporthouse.com> Quoting Jason Gunthorpe (2020-06-24 17:50:57) > On Wed, Jun 24, 2020 at 03:37:32PM +0100, Chris Wilson wrote: > > Quoting Jason Gunthorpe (2020-06-24 15:25:44) > > > On Wed, Jun 24, 2020 at 03:21:49PM +0100, Chris Wilson wrote: > > > > Quoting Jason Gunthorpe (2020-06-24 15:16:04) > > > > > On Wed, Jun 24, 2020 at 03:12:42PM +0100, Chris Wilson wrote: > > > > > > Quoting Jason Gunthorpe (2020-06-24 13:39:10) > > > > > > > On Wed, Jun 24, 2020 at 01:21:03PM +0100, Chris Wilson wrote: > > > > > > > > Quoting Jason Gunthorpe (2020-06-24 13:10:53) > > > > > > > > > On Wed, Jun 24, 2020 at 09:02:47AM +0100, Chris Wilson wrote: > > > > > > > > > > When direct reclaim enters the shrinker and tries to reclaim pages, it > > > > > > > > > > has to opportunitically unmap them [try_to_unmap_one]. For direct > > > > > > > > > > reclaim, the calling context is unknown and may include attempts to > > > > > > > > > > unmap one page of a dma object while attempting to allocate more pages > > > > > > > > > > for that object. Pass the information along that we are inside an > > > > > > > > > > opportunistic unmap that can allow that page to remain referenced and > > > > > > > > > > mapped, and let the callback opt in to avoiding a recursive wait. > > > > > > > > > > > > > > > > > > i915 should already not be holding locks shared with the notifiers > > > > > > > > > across allocations that can trigger reclaim. This is already required > > > > > > > > > to use notifiers correctly anyhow - why do we need something in the > > > > > > > > > notifiers? > > > > > > > > > > > > > > > > for (n = 0; n < num_pages; n++) > > > > > > > > pin_user_page() > > > > > > > > > > > > > > > > may call try_to_unmap_page from the lru shrinker for [0, n-1]. > > > > > > > > > > > > > > Yes, of course you can't hold any locks that intersect with notifiers > > > > > > > across pin_user_page()/get_user_page() > > > > > > > > > > > > What lock though? It's just the page refcount, shrinker asks us to drop > > > > > > it [via mmu], we reply we would like to keep using that page as freeing > > > > > > it for the current allocation is "robbing Peter to pay Paul". > > > > > > > > > > Maybe I'm unclear what this series is actually trying to fix? > > > > > > > > > > You said "avoiding a recursive wait" which sounds like some locking > > > > > deadlock to me. > > > > > > > > It's the shrinker being called while we are allocating for/on behalf of > > > > the object. As we are actively using the object, we don't want to free > > > > it -- the partial object allocation being the clearest, if the object > > > > consists of 2 pages, trying to free page 0 in order to allocate page 1 > > > > has to fail (and the shrinker should find another candidate to reclaim, > > > > or fail the allocation). > > > > > > mmu notifiers are not for influencing policy of the mm. > > > > It's policy is "this may fail" regardless of the mmu notifier at this > > point. That is not changed. > > MMU notifiers are for tracking updates, they are not allowed to fail. > The one slightly weird case of non-blocking is the only exception. > > > Your suggestion is that we move the pages to the unevictable mapping so > > that the shrinker LRU is never invoked on pages we have grabbed with > > pin_user_page. Does that work with the rest of the mmu notifiers? > > That is beyond what I'm familiar with - but generally - if you want to > influence decisions the MM is making then it needs to be at the > front of the process and not inside notifiers. > > So what you describe seems broadly appropriate to me. Sadly, it's a mlock_vma_page problem all over again. > I'm still a little unclear on what you are trying to fix - pinned > pages are definitely not freed, do you have some case where pages > which are pinned are being cleaned out from the MM despite being > pinned? Sounds a bit strange, maybe that is worth adressing directly? It suffices to say that pin_user_pages does not prevent try_to_unmap_one from trying to revoke the page. But we could perhaps slip a page_maybe_dma_pinned() in around there and see what happens. -Chris From matthew.s.atwood at intel.com Wed Jun 24 18:11:49 2020 From: matthew.s.atwood at intel.com (Matt Atwood) Date: Wed, 24 Jun 2020 11:11:49 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/gt: Implement WA_1406941453 In-Reply-To: <20200611233108.19205-1-clinton.a.taylor@intel.com> References: <20200611233108.19205-1-clinton.a.taylor@intel.com> Message-ID: <20200624181149.GA25763@msatwood-mobl> On Thu, Jun 11, 2020 at 04:31:08PM -0700, clinton.a.taylor at intel.com wrote: > From: Clint Taylor <clinton.a.taylor at intel.com> > > Enable HW Default flip for small PL. > > bspec: 52890 > bspec: 53508 > bspec: 53273 > > Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 2da366821dda..0b9091c05e06 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -628,6 +628,9 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, > WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, > GEN9_PREEMPT_GPGPU_LEVEL_MASK, > GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL); > + > + /* Wa_1406941453:gen12 */ > + WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE, ENABLE_SMALLPL); > } > > static void > @@ -1500,6 +1503,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) > whitelist_reg_ext(w, PS_INVOCATION_COUNT, > RING_FORCE_TO_NONPRIV_ACCESS_RD | > RING_FORCE_TO_NONPRIV_RANGE_4); > + > + /* Wa_1406941453:gen12 */ > + whitelist_reg(w, GEN10_SAMPLER_MODE); > break; > > case VIDEO_DECODE_CLASS: > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 19e1fed198c3..fbb095a94b3a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9223,6 +9223,7 @@ enum { > #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) > > #define GEN10_SAMPLER_MODE _MMIO(0xE18C) > +#define ENABLE_SMALLPL REG_BIT(15) > #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) > > /* IVYBRIDGE DPF */ > -- > 2.26.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From james.ausmus at intel.com Wed Jun 24 18:31:40 2020 From: james.ausmus at intel.com (James Ausmus) Date: Wed, 24 Jun 2020 11:31:40 -0700 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogIGZhaWx1cmUgZm9yIGRy?= =?utf-8?q?m/i915/gt=3A_Implement_WA=5F1406941453?= In-Reply-To: <159192027560.21335.2442323093114834329@emeril.freedesktop.org> References: <20200611233108.19205-1-clinton.a.taylor@intel.com> <159192027560.21335.2442323093114834329@emeril.freedesktop.org> Message-ID: <20200624183139.GB28937@jausmus-gentoo-dev6.jf.intel.com> On Fri, Jun 12, 2020 at 12:04:35AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/gt: Implement WA_1406941453 > URL : https://patchwork.freedesktop.org/series/78243/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17931 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17931 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17931, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17931: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at runner@aborted: > - fi-bdw-5557u: NOTRUN -> [FAIL][1] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bdw-5557u/igt at runner@aborted.html Lakshmi - this failure isn't related - can you re-report? Thanks! -James > > > Known issues > ------------ > > Here are the changes found in Patchwork_17931 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_suspend@basic-s0: > - fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html > > * igt at gem_sync@basic-all: > - fi-icl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-guc/igt at gem_sync@basic-all.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-guc/igt at gem_sync@basic-all.html > > * igt at i915_module_load@reload: > - fi-tgl-u2: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at i915_module_load@reload.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at i915_module_load@reload.html > > * igt at i915_pm_rpm@basic-pci-d3-state: > - fi-bsw-kefka: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html > > * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: > - fi-icl-u2: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 similar issue > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html > > > #### Possible fixes #### > > * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-byt-j1900: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: > - fi-tgl-u2: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html > > > #### Warnings #### > > * igt at gem_exec_suspend@basic-s0: > - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][17] ([i915#62] / [i915#92]) +2 similar issues > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html > > * igt at kms_flip@basic-flip-vs-modeset at a-dp1: > - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > > > [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (50 -> 42) > ------------------------------ > > Missing (8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * Linux: CI_DRM_8618 -> Patchwork_17931 > > CI-20190529: 20190529 > CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17931: 39466c9ac72e20913b60ada9fdf53b78e4a6f70b @ git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > 39466c9ac72e drm/i915/gt: Implement WA_1406941453 > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From airlied at gmail.com Wed Jun 24 19:04:02 2020 From: airlied at gmail.com (Dave Airlie) Date: Thu, 25 Jun 2020 05:04:02 +1000 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159294714433.24819.3044662904558073290@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> Message-ID: <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > Quoting Dave Airlie (2020-06-23 22:01:24) > > On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > > > > Hi, Chris! > > > > > > > > On 6/22/20 11:59 AM, Chris Wilson wrote: > > > > > In order to actually handle eviction and what not, we need to process > > > > > all the objects together under a common lock, reservation_ww_class. As > > > > > such, do a memory reservation pass after looking up the object/vma, > > > > > which then feeds into the rest of execbuf [relocation, cmdparsing, > > > > > flushing and ofc execution]. > > > > > > > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > > > > --- > > > > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > > > > > 1 file changed, 70 insertions(+), 21 deletions(-) > > > > > > > > > Which tree is this against? The series doesn't apply cleanly against > > > > drm-tip? > > > > > > It's continuing on from the scheduler patches, the bug fixes and the > > > iris-deferred-fence work. I thought throwing all of those old patches > > > into the pile would have been distracting. > > > > > > > ... > > > > > > > > > +static int eb_reserve_mm(struct i915_execbuffer *eb) > > > > > +{ > > > > > + const u64 idx = eb->context->timeline->fence_context; > > > > > + struct ww_acquire_ctx acquire; > > > > > + struct eb_vma *ev; > > > > > + int err; > > > > > + > > > > > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > > > > > + if (!eb->mm_fence) > > > > > + return -ENOMEM; > > > > > > > > Where are the proxy fence functions defined? > > > > > > In dma-fence-proxy.c ;) > > > > The dma-fence-proxy that Christian NAKed before? > > I do not have an email from Christian about dma-fence-proxy in the last > 3 years it has been on the list. https://lore.kernel.org/dri-devel/aeb0373d-0583-d922-3b73-93668c27d177 at amd.com/ I'm assuming this was about patch 8 there which to me looks like proxy fences but maybe by threading is off reading that. https://lore.kernel.org/dri-devel/1502491174-10913-9-git-send-email-jason.ekstrand at intel.com/ Dave. From chris at chris-wilson.co.uk Wed Jun 24 19:14:17 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 20:14:17 +0100 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages Message-ID: <20200624191417.16735-1-chris@chris-wilson.co.uk> A general rule of thumb is that shrinkers should be fast and effective. They are called from direct reclaim at the most incovenient of times when the caller is waiting for a page. If we attempt to reclaim a page being pinned for active dma [pin_user_pages()], we will incur far greater latency than a normal anonymous page mapped multiple times. Worse the page may be in use indefinitely by the HW and unable to be reclaimed in a timely manner. A side effect of the LRU shrinker not being dma aware is that we will often attempt to perform direct reclaim on the persistent group of dma pages while continuing to use the dma HW (an issue as the HW may already be actively waiting for the next user request), and even attempt to reclaim a partially allocated dma object in order to satisfy pinning the next user page for that object. It is to be expected that such pages are made available for reclaim at the end of the dma operation [unpin_user_pages()], and for truly longterm pins to be proactively recovered via device specific shrinkers [i.e. stop the HW, allow the pages to be returned to the system, and then compete again for the memory]. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Andrew Morton <akpm at linux-foundation.org> Cc: Jan Kara <jack at suse.cz> Cc: J?r?me Glisse <jglisse at redhat.com> Cc: John Hubbard <jhubbard at nvidia.com> Cc: Claudio Imbrenda <imbrenda at linux.ibm.com> Cc: Jan Kara <jack at suse.cz> Cc: Kirill A. Shutemov <kirill.shutemov at linux.intel.com> Cc: Jason Gunthorpe <jgg at ziepe.ca> --- This seems perhaps a little devious and overzealous. Is there a more appropriate TTU flag? Would there be a way to limit its effect to say FOLL_LONGTERM? Doing the migration first would seem to be sensible if we disable opportunistic migration for the duration of the pin. --- mm/rmap.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/mm/rmap.c b/mm/rmap.c index 5fe2dedce1fc..374c6e65551b 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -1393,6 +1393,22 @@ static bool try_to_unmap_one(struct page *page, struct vm_area_struct *vma, is_zone_device_page(page) && !is_device_private_page(page)) return true; + /* + * Try and fail early to revoke a costly DMA pinned page. + * + * Reclaiming an active DMA page requires stopping the hardware + * and flushing access. [Hardware that does support pagefaulting, + * and so can quickly revoke DMA pages at any time, does not need + * to pin the DMA page.] At worst, the page may be indefinitely in + * use by the hardware. Even at best it will take far longer to + * revoke the access via the mmu notifier, forcing that latency + * onto our callers rather than the consumer of the HW. As we are + * called during opportunistic direct reclaim, declare the + * opportunity cost too high and ignore the page. + */ + if (page_maybe_dma_pinned(page)) + return true; + if (flags & TTU_SPLIT_HUGE_PMD) { split_huge_pmd_address(vma, address, flags & TTU_SPLIT_FREEZE, page); -- 2.20.1 From patchwork at emeril.freedesktop.org Wed Jun 24 19:31:20 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Wed, 24 Jun 2020 19:31:20 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Implement_WA=5F1406941453?= In-Reply-To: <20200611233108.19205-1-clinton.a.taylor@intel.com> References: <20200611233108.19205-1-clinton.a.taylor@intel.com> Message-ID: <159302708085.19236.1191209539726889305@emeril.freedesktop.org> == Series Details == Series: drm/i915/gt: Implement WA_1406941453 URL : https://patchwork.freedesktop.org/series/78243/ State : success == Summary == CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17931 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html Known issues ------------ Here are the changes found in Patchwork_17931 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at gem_sync@basic-all: - fi-icl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-guc/igt at gem_sync@basic-all.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-guc/igt at gem_sync@basic-all.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Possible fixes #### * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (50 -> 42) ------------------------------ Missing (8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8618 -> Patchwork_17931 CI-20190529: 20190529 CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_17931: 39466c9ac72e20913b60ada9fdf53b78e4a6f70b @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 39466c9ac72e drm/i915/gt: Implement WA_1406941453 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html From jose.souza at intel.com Wed Jun 24 19:32:49 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Wed, 24 Jun 2020 12:32:49 -0700 Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Implement new combo phy initialization step Message-ID: <20200624193249.20725-1-jose.souza@intel.com> This is new step that was recently added to the combo phy initialization. v2: - using intel_de_rmw() BSpec: 49291 Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 23 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 ++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec62..115069833348 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -264,6 +264,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, if (!icl_combo_phy_enabled(dev_priv, phy)) return false; + if (INTEL_GEN(dev_priv) >= 12) { + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_GRP(phy), + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); + + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_GRP(phy), + DCC_MODE_SELECT_MASK, + DCC_MODE_SELECT_CONTINUOSLY); + } + ret = cnl_verify_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { @@ -375,6 +387,17 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); skip_phy_misc: + if (INTEL_GEN(dev_priv) >= 12) { + intel_de_rmw(dev_priv, ICL_PORT_TX_DW8_GRP(phy), + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); + + intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), + DCC_MODE_SELECT_MASK, + DCC_MODE_SELECT_CONTINUOSLY); + } + cnl_set_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..5469c9029f6d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1974,6 +1974,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) +#define DCC_MODE_SELECT_MASK (0x3 << 20) +#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) #define COMMON_KEEPER_EN (1 << 26) #define LATENCY_OPTIM_MASK (0x3 << 2) #define LATENCY_OPTIM_VAL(x) ((x) << 2) @@ -2072,6 +2074,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) +#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) + #define _ICL_DPHY_CHKN_REG 0x194 #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) -- 2.27.0 From daniel at ffwll.ch Wed Jun 24 19:32:45 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Wed, 24 Jun 2020 21:32:45 +0200 Subject: [Intel-gfx] [PATCH] dma-buf: minor doc touch-ups In-Reply-To: <20200612070535.1778368-1-daniel.vetter@ffwll.ch> References: <20200604081224.863494-3-daniel.vetter@ffwll.ch> <20200612070535.1778368-1-daniel.vetter@ffwll.ch> Message-ID: <20200624144431.GA3278063@phenom.ffwll.local> On Fri, Jun 12, 2020 at 09:05:35AM +0200, Daniel Vetter wrote: > Just some tiny edits: > - fix link to struct dma_fence > - give slightly more meaningful title - the polling here is about > implicit fences, explicit fences (in sync_file or drm_syncobj) also > have their own polling > > v2: I misplaced the .rst include change corresponding to this patch. > > Reviewed-by: Thomas Hellstrom <thomas.hellstrom at intel.com> > Signed-off-by: Daniel Vetter <daniel.vetter at intel.com> I went ahead and merged this one, shouldn't be the controversial part of the series :-) -Daniel > --- > Documentation/driver-api/dma-buf.rst | 6 +++--- > drivers/dma-buf/dma-buf.c | 6 +++--- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > index 63dec76d1d8d..7fb7b661febd 100644 > --- a/Documentation/driver-api/dma-buf.rst > +++ b/Documentation/driver-api/dma-buf.rst > @@ -100,11 +100,11 @@ CPU Access to DMA Buffer Objects > .. kernel-doc:: drivers/dma-buf/dma-buf.c > :doc: cpu access > > -Fence Poll Support > -~~~~~~~~~~~~~~~~~~ > +Implicit Fence Poll Support > +~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > .. kernel-doc:: drivers/dma-buf/dma-buf.c > - :doc: fence polling > + :doc: implicit fence polling > > Kernel Functions and Structures Reference > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c > index 01ce125f8e8d..e018ef80451e 100644 > --- a/drivers/dma-buf/dma-buf.c > +++ b/drivers/dma-buf/dma-buf.c > @@ -161,11 +161,11 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) > } > > /** > - * DOC: fence polling > + * DOC: implicit fence polling > * > * To support cross-device and cross-driver synchronization of buffer access > - * implicit fences (represented internally in the kernel with &struct fence) can > - * be attached to a &dma_buf. The glue for that and a few related things are > + * implicit fences (represented internally in the kernel with &struct dma_fence) > + * can be attached to a &dma_buf. The glue for that and a few related things are > * provided in the &dma_resv structure. > * > * Userspace can query the state of these implicitly tracked fences using poll() > -- > 2.26.2 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From chris at chris-wilson.co.uk Wed Jun 24 20:18:20 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 21:18:20 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> Message-ID: <159302990055.4527.16849537545776334660@build.alporthouse.com> Quoting Dave Airlie (2020-06-24 20:04:02) > On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > Quoting Dave Airlie (2020-06-23 22:01:24) > > > On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > > > > > Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > > > > > Hi, Chris! > > > > > > > > > > On 6/22/20 11:59 AM, Chris Wilson wrote: > > > > > > In order to actually handle eviction and what not, we need to process > > > > > > all the objects together under a common lock, reservation_ww_class. As > > > > > > such, do a memory reservation pass after looking up the object/vma, > > > > > > which then feeds into the rest of execbuf [relocation, cmdparsing, > > > > > > flushing and ofc execution]. > > > > > > > > > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > > > > > --- > > > > > > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > > > > > > 1 file changed, 70 insertions(+), 21 deletions(-) > > > > > > > > > > > Which tree is this against? The series doesn't apply cleanly against > > > > > drm-tip? > > > > > > > > It's continuing on from the scheduler patches, the bug fixes and the > > > > iris-deferred-fence work. I thought throwing all of those old patches > > > > into the pile would have been distracting. > > > > > > > > > ... > > > > > > > > > > > +static int eb_reserve_mm(struct i915_execbuffer *eb) > > > > > > +{ > > > > > > + const u64 idx = eb->context->timeline->fence_context; > > > > > > + struct ww_acquire_ctx acquire; > > > > > > + struct eb_vma *ev; > > > > > > + int err; > > > > > > + > > > > > > + eb->mm_fence = __dma_fence_create_proxy(0, 0); > > > > > > + if (!eb->mm_fence) > > > > > > + return -ENOMEM; > > > > > > > > > > Where are the proxy fence functions defined? > > > > > > > > In dma-fence-proxy.c ;) > > > > > > The dma-fence-proxy that Christian NAKed before? > > > > I do not have an email from Christian about dma-fence-proxy in the last > > 3 years it has been on the list. > > https://lore.kernel.org/dri-devel/aeb0373d-0583-d922-3b73-93668c27d177 at amd.com/ Darn, I skimmed the thread title and thought it was just about the timelines. > I'm assuming this was about patch 8 there which to me looks like proxy > fences but maybe by threading is off reading that. The deadlocks are easy to resolve. The fence is either signaled normally by userspace, they create a deadlock that is rejected by checking the dag and the fence signaled with an error (and work cancelled, error propagated back to userspace if they kept the output fence around), or userspace forgets entirely about the fence they were waiting on in which case it is signaled by closing the syncobjs [sadly not in error though, I hoping to report EPIPE] on process termination. https://patchwork.freedesktop.org/patch/372759/?series=78762&rev=1 We can always attach the dag resolver such that we resolve the deadlock for any importer and so only ever present a normal monotonic fence. That would make it illegal to wait on an external fence imported into that syncobj (as that would be outside of our dag). An option would be whether or not to force timeout slow userspace. But the simplicity of reusing the existing functionality to move intrabatch scheduling into iris is compelling. [In contrast, no one has yet finished the timeline patches to the point where they stopped throwing errors in igt, and we still then have to write patches for nonblocking wait-for-submit :[ The use here is trivial, chiefly used as a convenience to flesh out this argument to see if we can reduce the lock duration within submission [from the entirety of submission to ideally just reservation] by holding a fence for the submission process itself. And that boils down to at what point can someone else start to wait on that fence, and whether or not we can avoid any direct/indirect waits ourselves after point and before completing submission. [Usual rules about not being allowed to wait on a resource while holding contendable resources, but with the nuance of what/when exactly that resource becomes contendable.] The lock contention is quite real, as at the moment it is devolving into a global lock. With the amusing side effect that it then turns out to be quicker to wrap the entire thing in struct_mutex. -Chris From chris at chris-wilson.co.uk Wed Jun 24 20:23:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Wed, 24 Jun 2020 21:23:53 +0100 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200624192116.GO6578@ziepe.ca> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200624192116.GO6578@ziepe.ca> Message-ID: <159303023309.4527.5420769464370063531@build.alporthouse.com> Quoting Jason Gunthorpe (2020-06-24 20:21:16) > On Wed, Jun 24, 2020 at 08:14:17PM +0100, Chris Wilson wrote: > > A general rule of thumb is that shrinkers should be fast and effective. > > They are called from direct reclaim at the most incovenient of times when > > the caller is waiting for a page. If we attempt to reclaim a page being > > pinned for active dma [pin_user_pages()], we will incur far greater > > latency than a normal anonymous page mapped multiple times. Worse the > > page may be in use indefinitely by the HW and unable to be reclaimed > > in a timely manner. > > A pinned page can't be migrated, discarded or swapped by definition - > it would cause data corruption. > > So, how do things even get here and/or work today at all? I think the > explanation is missing something important. [<0>] userptr_mn_invalidate_range_start+0xa7/0x170 [i915] [<0>] __mmu_notifier_invalidate_range_start+0x110/0x150 [<0>] try_to_unmap_one+0x790/0x870 [<0>] rmap_walk_file+0xe9/0x230 [<0>] rmap_walk+0x27/0x30 [<0>] try_to_unmap+0x89/0xc0 [<0>] shrink_page_list+0x88a/0xf50 [<0>] shrink_inactive_list+0x137/0x2f0 [<0>] shrink_lruvec+0x4ec/0x5f0 [<0>] shrink_node+0x15d/0x410 [<0>] try_to_free_pages+0x17f/0x430 [<0>] __alloc_pages_slowpath+0x2ab/0xcc0 [<0>] __alloc_pages_nodemask+0x1ad/0x1e0 [<0>] new_slab+0x2d8/0x310 [<0>] ___slab_alloc.constprop.0+0x288/0x520 [<0>] __slab_alloc.constprop.0+0xd/0x20 [<0>] kmem_cache_alloc_trace+0x1ad/0x1c0 and that hits an active pin_user_pages object. Is there some information that would help in particular? -Chris From lakshminarayana.vudum at intel.com Wed Jun 24 20:30:06 2020 From: lakshminarayana.vudum at intel.com (Vudum, Lakshminarayana) Date: Wed, 24 Jun 2020 20:30:06 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/gt=3A_Implement_WA=5F1406941453?= In-Reply-To: <20200624183139.GB28937@jausmus-gentoo-dev6.jf.intel.com> References: <20200611233108.19205-1-clinton.a.taylor@intel.com> <159192027560.21335.2442323093114834329@emeril.freedesktop.org> <20200624183139.GB28937@jausmus-gentoo-dev6.jf.intel.com> Message-ID: <0c3605548e86437299af7c7888bed0f7@intel.com> Re-reported. -----Original Message----- From: Ausmus, James <james.ausmus at intel.com> Sent: Wednesday, June 24, 2020 9:32 PM To: intel-gfx at lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum at intel.com> Cc: Taylor, Clinton A <clinton.a.taylor at intel.com> Subject: Re: [Intel-gfx] ? Fi.CI.BAT: failure for drm/i915/gt: Implement WA_1406941453 On Fri, Jun 12, 2020 at 12:04:35AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/gt: Implement WA_1406941453 > URL : https://patchwork.freedesktop.org/series/78243/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17931 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_17931 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_17931, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_17931: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at runner@aborted: > - fi-bdw-5557u: NOTRUN -> [FAIL][1] > [1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bdw-5557u/ > igt at runner@aborted.html Lakshmi - this failure isn't related - can you re-report? Thanks! -James > > > Known issues > ------------ > > Here are the changes found in Patchwork_17931 that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_suspend@basic-s0: > - fi-tgl-u2: [PASS][2] -> [FAIL][3] ([i915#1888]) > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt > @gem_exec_suspend at basic-s0.html > > * igt at gem_sync@basic-all: > - fi-icl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-guc/igt at gem_sync@basic-all.html > [5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-guc/ig > t at gem_sync@basic-all.html > > * igt at i915_module_load@reload: > - fi-tgl-u2: [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at i915_module_load@reload.html > [7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt > @i915_module_load at reload.html > > * igt at i915_pm_rpm@basic-pci-d3-state: > - fi-bsw-kefka: [PASS][8] -> [DMESG-WARN][9] ([i915#1982]) > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bsw-kefka/ > igt at i915_pm_rpm@basic-pci-d3-state.html > > * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: > - fi-icl-u2: [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 similar issue > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-u2/igt > @kms_flip at basic-flip-vs-wf_vblank@b-edp1.html > > > #### Possible fixes #### > > * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: > - fi-byt-j1900: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > [13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-byt-j1900/ > igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html > > * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: > - fi-tgl-u2: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html > [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt > @kms_pipe_crc_basic at read-crc-pipe-a-frame-sequence.html > > > #### Warnings #### > > * igt at gem_exec_suspend@basic-s0: > - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][17] ([i915#62] / [i915#92]) +2 similar issues > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html > [17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/ > igt at gem_exec_suspend@basic-s0.html > > * igt at kms_flip@basic-flip-vs-modeset at a-dp1: > - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > [19]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/ > igt at kms_flip@basic-flip-vs-modeset at a-dp1.html > > > [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (50 -> 42) > ------------------------------ > > Missing (8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus > > > Build changes > ------------- > > * Linux: CI_DRM_8618 -> Patchwork_17931 > > CI-20190529: 20190529 > CI_DRM_8618: 88841e30e7f8c60ff464be277e5b8fef49ebaea0 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5703: c33471b4aa0a0ae9dd42202048e7037a661e0574 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_17931: 39466c9ac72e20913b60ada9fdf53b78e4a6f70b @ > git://anongit.freedesktop.org/gfx-ci/linux > > > == Linux commits == > > 39466c9ac72e drm/i915/gt: Implement WA_1406941453 > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 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From matthew.s.atwood at intel.com Wed Jun 24 21:57:23 2020 From: matthew.s.atwood at intel.com (Matt Atwood) Date: Wed, 24 Jun 2020 14:57:23 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: implement Wa_14011508470;gen12 Message-ID: <20200624215723.2316-1-matthew.s.atwood@intel.com> Update code to reflect recent bspec changes Bspec: 52890 Bspec: 53508 Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index c3eeebadc0b8..22395be35364 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -6007,6 +6007,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, { struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *well; + u32 val; gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); @@ -6043,6 +6044,13 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (resume && dev_priv->csr.dmc_payload) intel_csr_load_program(dev_priv); + + /* Wa_14011508470 */ + if (IS_GEN(dev_priv, 12)) { + val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | + DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR; + intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val); + } } static void icl_display_core_uninit(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 450564e28332..5344d20c9070 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8105,6 +8105,12 @@ enum hardware_error { #define MASK_WAKEMEM (1 << 13) #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) +#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) +#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) +#define DCPR_MASK_LPMODE REG_BIT(26) +#define DCPR_SEND_RESP_IMM REG_BIT(25) +#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) + #define SKL_DFSM _MMIO(0x51000) #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) -- 2.21.3 From manasi.d.navare at intel.com Wed Jun 24 22:11:08 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Wed, 24 Jun 2020 15:11:08 -0700 Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200624221108.10038-1-manasi.d.navare@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> Message-ID: <20200624221108.10038-2-manasi.d.navare@intel.com> Based on the platform, Bspec expects us to wait or poll with timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active after enabling DDI_BUF_CTL. v3: * Add a new function _active for DDI BUF CTL to be non idle (Ville) v2: * Based on platform, fixed delay or poll (Ville) * Use a helper to do this (Imre, Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 7d5c8ab88fc4..ff6b1e9d1b4e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, port_name(port)); } +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, + enum port port) +{ + if (INTEL_GEN(dev_priv) <= 9) { + usleep_range(600, 1000); + return; + } + + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + DDI_BUF_IS_IDLE), 600)) + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", + port_name(port)); +} + static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) { switch (pll->info->id) { @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); - udelay(600); + intel_wait_ddi_buf_active(dev_priv, port); } static void intel_ddi_set_link_train(struct intel_dp *intel_dp, -- 2.19.1 From manasi.d.navare at intel.com Wed Jun 24 22:11:07 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Wed, 24 Jun 2020 15:11:07 -0700 Subject: [Intel-gfx] [PATCH v3 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Message-ID: <20200624221108.10038-1-manasi.d.navare@intel.com> Modify the helper to add a fixed delay or poll with timeout based on platform specification to check for either Idle bit set (DDI_BUF_CTL is idle for disable case) v2: * Use 2 separate functions or idle and active (Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 884b507c5f55..7d5c8ab88fc4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port) { - i915_reg_t reg = DDI_BUF_CTL(port); - int i; - - for (i = 0; i < 16; i++) { - udelay(1); - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) - return; + if (IS_BROXTON(dev_priv)) { + udelay(16); + return; } - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", - port_name(port)); + + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + DDI_BUF_IS_IDLE), 600)) + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", + port_name(port)); } static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) -- 2.19.1 From manasi.d.navare at intel.com Wed Jun 24 22:48:30 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Wed, 24 Jun 2020 15:48:30 -0700 Subject: [Intel-gfx] [PATCH v2 3/3] Revert "drm/amd/display: Expose connector VRR range via debugfs" In-Reply-To: <20200622142519.16214-4-bhanuprakash.modem@intel.com> References: <20200622142519.16214-4-bhanuprakash.modem@intel.com> Message-ID: <20200624224830.26093-1-manasi.d.navare@intel.com> From: Bhanuprakash Modem <bhanuprakash.modem at intel.com> v2: * Rebase (Manasi) As both VRR min and max are already part of drm_display_info, drm can expose this VRR range for each connector. Hence this logic should move to core DRM. This reverts commit 727962f030c23422a01e8b22d0f463815fb15ec4. Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> Cc: Harry Wentland <harry.wentland at amd.com> Cc: Alex Deucher <alexander.deucher at amd.com> Cc: Manasi Navare <manasi.d.navare at intel.com> Cc: AMD gfx <amd-gfx at lists.freedesktop.org> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com> --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 20 ------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 076af267b488..71387d2af2ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -820,24 +820,6 @@ static int output_bpc_show(struct seq_file *m, void *data) return res; } -/* - * Returns the min and max vrr vfreq through the connector's debugfs file. - * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range - */ -static int vrr_range_show(struct seq_file *m, void *data) -{ - struct drm_connector *connector = m->private; - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - - if (connector->status != connector_status_connected) - return -ENODEV; - - seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq); - seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq); - - return 0; -} - #ifdef CONFIG_DRM_AMD_DC_HDCP /* * Returns the HDCP capability of the Display (1.4 for now). @@ -1001,7 +983,6 @@ static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf, DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); DEFINE_SHOW_ATTRIBUTE(output_bpc); -DEFINE_SHOW_ATTRIBUTE(vrr_range); #ifdef CONFIG_DRM_AMD_DC_HDCP DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); #endif @@ -1059,7 +1040,6 @@ static const struct { {"phy_settings", &dp_phy_settings_debugfs_fop}, {"test_pattern", &dp_phy_test_pattern_fops}, {"output_bpc", &output_bpc_fops}, - {"vrr_range", &vrr_range_fops}, #ifdef CONFIG_DRM_AMD_DC_HDCP {"hdcp_sink_capability", &hdcp_sink_capability_fops}, #endif -- 2.19.1 From lucas.demarchi at intel.com Thu Jun 25 00:11:14 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 24 Jun 2020 17:11:14 -0700 Subject: [Intel-gfx] [PATCH v2 0/6] display/ddi: keep register indexes in a table Message-ID: <20200625001120.22810-1-lucas.demarchi@intel.com> v2 of https://patchwork.freedesktop.org/series/71330/ I think I covered comments from Jani and Matt Roper here. This is still in the RFC phase and thus not properly tested. Change in this version is mostly that now it's not trying to generalize intel_setup_outputs(), but rather provide a function each platform can call to setup the outputs. As such, dsi initialization and port presence checks are left where they are. We now also have a PHY_MG/PHY_DKL rather than PHY_TC and one additional patch in the end doing more conversions. Hopefully this showcase better the final state I want to accomplish. There's a lot more conversions to do and even those done here I think will be in a different form in the end. This is *untested*, just sending it here for feedback on the direction. Patch 1 and 2 were for the first version, and are now optional. Lucas De Marchi (6): drm/i915: move ICL port F hack to intel_bios drm/i915/display: fix comment on skl straps drm/i915/display: start description-based ddi initialization drm/i915/display: add phy, vbt and ddi indexes drm/i915/display: use port_info in intel_ddi_init drm/i915/display: replace port to phy conversions in intel_ddi.c drivers/gpu/drm/i915/display/intel_bios.c | 23 +- drivers/gpu/drm/i915/display/intel_ddi.c | 197 +++++++++--------- drivers/gpu/drm/i915/display/intel_ddi.h | 8 +- drivers/gpu/drm/i915/display/intel_display.c | 156 +++++++++----- drivers/gpu/drm/i915/display/intel_display.h | 8 + .../drm/i915/display/intel_display_types.h | 12 ++ 6 files changed, 246 insertions(+), 158 deletions(-) -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 25 00:11:16 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 24 Jun 2020 17:11:16 -0700 Subject: [Intel-gfx] [PATCH v2 2/6] drm/i915/display: fix comment on skl straps In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <20200625001120.22810-3-lucas.demarchi@intel.com> We are not checking for specific SKUs and feedback from HW team is that it may not work since it was supposed to be fixed by the same time straps stopped to be used. So, just update comment. v2: Instead of removing the check, just update the comment since feedback from HW team was that it actually may not work Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 49772c82a299..effd6b65f270 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16863,8 +16863,9 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) /* * Haswell uses DDI functions to detect digital outputs. - * On SKL pre-D0 the strap isn't connected, so we assume - * it's there. + * On SKL pre-D0 the strap isn't connected. Later SKUs may or + * may not have it - it was supposed to be fixed by the same + * time we stopped using straps. Assume it's there. */ found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; /* WaIgnoreDDIAStrap: skl */ -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 25 00:11:15 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 24 Jun 2020 17:11:15 -0700 Subject: [Intel-gfx] [PATCH v2 1/6] drm/i915: move ICL port F hack to intel_bios In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <20200625001120.22810-2-lucas.demarchi@intel.com> Move the check for port F to intel_bios.c and just make intel_ddi_init() call it. This will allow the output initialization of ICL to be like platforms after it, allowing us to make it generic. Suggested-by: Jani Nikula <jani.nikula at linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 23 +++++++++++++++----- drivers/gpu/drm/i915/display/intel_display.c | 10 +-------- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 6593e2c38043..9d42ea3721cd 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1668,16 +1668,27 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, }; - if (IS_ROCKETLAKE(dev_priv)) + if (IS_ROCKETLAKE(dev_priv)) { return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), ARRAY_SIZE(rkl_port_mapping[0]), rkl_port_mapping, dvo_port); - else - return __dvo_port_to_port(ARRAY_SIZE(port_mapping), - ARRAY_SIZE(port_mapping[0]), - port_mapping, - dvo_port); + } else { + enum port port = __dvo_port_to_port(ARRAY_SIZE(port_mapping), + ARRAY_SIZE(port_mapping[0]), + port_mapping, + dvo_port); + + /* + * On some ICL SKUs port F is not present. Work around broken + * VBTs by allowing port F only on select SKUs. + */ + if (port == PORT_F && IS_ICELAKE(dev_priv) && + !IS_ICL_WITH_PORT_F(dev_priv)) + return PORT_NONE; + + return port; + } } static void parse_ddi_port(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a11bb675f9b3..49772c82a299 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16842,15 +16842,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_C); intel_ddi_init(dev_priv, PORT_D); intel_ddi_init(dev_priv, PORT_E); - /* - * On some ICL SKUs port F is not present. No strap bits for - * this, so rely on VBT. - * Work around broken VBTs on SKUs known to have no port F. - */ - if (IS_ICL_WITH_PORT_F(dev_priv) && - intel_bios_is_port_present(dev_priv, PORT_F)) - intel_ddi_init(dev_priv, PORT_F); - + intel_ddi_init(dev_priv, PORT_F); icl_dsi_init(dev_priv); } else if (IS_GEN9_LP(dev_priv)) { /* -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 25 00:11:17 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 24 Jun 2020 17:11:17 -0700 Subject: [Intel-gfx] [PATCH v2 3/6] drm/i915/display: start description-based ddi initialization In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <20200625001120.22810-4-lucas.demarchi@intel.com> Start adding per-platform relevant data into a table that we use for initialization. Intention is to keep the different indexes we need (e.g. phy, vbt, ddi, etc) and any other differences for each platform in these tables so we don't have to keep converting back and forth between them. For now, just add the naked table with name. Subsequent patches will start piping this in via intel_ddi_init(). v2: do not try to generalize the checks for port presence nor dsi initialization. Instead focus on getting the ddi table created for all platforms using DDI and keep their differences in the original function drm/i915/display: description-based initialization for remaining ddi platforms Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 141 ++++++++++++------ .../drm/i915/display/intel_display_types.h | 5 + 2 files changed, 99 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index effd6b65f270..c234b50212b0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16805,6 +16805,83 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) intel_pps_unlock_regs_wa(dev_priv); } +static const struct intel_ddi_port_info rkl_ports[] = { + { .name = "DDI A", .port = PORT_A }, + { .name = "DDI B", .port = PORT_B }, + { .name = "DDI TC1", .port = PORT_D }, + { .name = "DDI TC2", .port = PORT_E }, + { .port = PORT_NONE } +}; + +static const struct intel_ddi_port_info tgl_ports[] = { + { .name = "DDI A", .port = PORT_A }, + { .name = "DDI B", .port = PORT_B }, + { .name = "DDI TC1", .port = PORT_D }, + { .name = "DDI TC2", .port = PORT_E }, + { .name = "DDI TC3", .port = PORT_F }, + { .name = "DDI TC4", .port = PORT_G }, + { .name = "DDI TC5", .port = PORT_H }, + { .name = "DDI TC6", .port = PORT_I }, + { .port = PORT_NONE } +}; + +static const struct intel_ddi_port_info ehl_ports[] = { + { .name = "DDI A", .port = PORT_A }, + { .name = "DDI B", .port = PORT_B }, + { .name = "DDI C", .port = PORT_C }, + { .name = "DDI D", .port = PORT_D }, + { .port = PORT_NONE } +}; + +static const struct intel_ddi_port_info icl_ports[] = { + { .name = "DDI A", .port = PORT_A }, + { .name = "DDI B", .port = PORT_B }, + { .name = "DDI TC1", .port = PORT_C }, + { .name = "DDI TC2", .port = PORT_D }, + { .name = "DDI TC3", .port = PORT_E }, + { .name = "DDI TC4", .port = PORT_F }, + { .port = PORT_NONE } +}; + +static const struct intel_ddi_port_info gen9lp_ports[] = { + { .name = "DDI A", .port = PORT_A }, + { .name = "DDI B", .port = PORT_B }, + { .name = "DDI C", .port = PORT_C }, + { .port = PORT_NONE } +}; + +static const struct intel_ddi_port_info ddi_ports[] = { + { .name = "DDI A", .port = PORT_A }, + { .name = "DDI B", .port = PORT_B }, + { .name = "DDI C", .port = PORT_C }, + { .name = "DDI D", .port = PORT_D }, + { .name = "DDI E", .port = PORT_E }, + { .name = "DDI F", .port = PORT_F }, + { .port = PORT_NONE } +}; + +/* + * Use a description-based approach for platforms that can be supported with a + * static table + * + * @disable_mask: any port that should not be enabled due to being disabled by + * any reason + */ +static void setup_ddi_outputs_desc(struct drm_i915_private *i915, + const struct intel_ddi_port_info *ports, + unsigned long disable_mask) +{ + const struct intel_ddi_port_info *port_info; + + for (port_info = ports; + port_info->port != PORT_NONE; port_info++) { + if (test_bit(port_info->port, &disable_mask)) + continue; + + intel_ddi_init(i915, port_info->port); + } +} + static void intel_setup_outputs(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; @@ -16816,46 +16893,21 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) return; if (IS_ROCKETLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ - intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ + setup_ddi_outputs_desc(dev_priv, rkl_ports, 0); } else if (INTEL_GEN(dev_priv) >= 12) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_D); - intel_ddi_init(dev_priv, PORT_E); - intel_ddi_init(dev_priv, PORT_F); - intel_ddi_init(dev_priv, PORT_G); - intel_ddi_init(dev_priv, PORT_H); - intel_ddi_init(dev_priv, PORT_I); + setup_ddi_outputs_desc(dev_priv, tgl_ports, 0); icl_dsi_init(dev_priv); } else if (IS_ELKHARTLAKE(dev_priv)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_C); - intel_ddi_init(dev_priv, PORT_D); + setup_ddi_outputs_desc(dev_priv, ehl_ports, 0); icl_dsi_init(dev_priv); } else if (IS_GEN(dev_priv, 11)) { - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_C); - intel_ddi_init(dev_priv, PORT_D); - intel_ddi_init(dev_priv, PORT_E); - intel_ddi_init(dev_priv, PORT_F); + setup_ddi_outputs_desc(dev_priv, icl_ports, 0); icl_dsi_init(dev_priv); } else if (IS_GEN9_LP(dev_priv)) { - /* - * FIXME: Broxton doesn't support port detection via the - * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to - * detect the ports. - */ - intel_ddi_init(dev_priv, PORT_A); - intel_ddi_init(dev_priv, PORT_B); - intel_ddi_init(dev_priv, PORT_C); - + setup_ddi_outputs_desc(dev_priv, gen9lp_ports, 0); vlv_dsi_init(dev_priv); } else if (HAS_DDI(dev_priv)) { + unsigned long disable_mask = 0; int found; if (intel_ddi_crt_present(dev_priv)) @@ -16869,28 +16921,23 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) */ found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; /* WaIgnoreDDIAStrap: skl */ - if (found || IS_GEN9_BC(dev_priv)) - intel_ddi_init(dev_priv, PORT_A); + if (!found && !IS_GEN9_BC(dev_priv)) + disable_mask |= BIT(PORT_A); /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP * register */ found = intel_de_read(dev_priv, SFUSE_STRAP); - if (found & SFUSE_STRAP_DDIB_DETECTED) - intel_ddi_init(dev_priv, PORT_B); - if (found & SFUSE_STRAP_DDIC_DETECTED) - intel_ddi_init(dev_priv, PORT_C); - if (found & SFUSE_STRAP_DDID_DETECTED) - intel_ddi_init(dev_priv, PORT_D); - if (found & SFUSE_STRAP_DDIF_DETECTED) - intel_ddi_init(dev_priv, PORT_F); - /* - * On SKL we don't have a way to detect DDI-E so we rely on VBT. - */ - if (IS_GEN9_BC(dev_priv) && - intel_bios_is_port_present(dev_priv, PORT_E)) - intel_ddi_init(dev_priv, PORT_E); + if (!(found & SFUSE_STRAP_DDIB_DETECTED)) + disable_mask |= BIT(PORT_B); + if (!(found & SFUSE_STRAP_DDIC_DETECTED)) + disable_mask |= BIT(PORT_C); + if (!(found & SFUSE_STRAP_DDID_DETECTED)) + disable_mask |= BIT(PORT_D); + if (!(found & SFUSE_STRAP_DDIF_DETECTED)) + disable_mask |= BIT(PORT_F); + setup_ddi_outputs_desc(dev_priv, ddi_ports, disable_mask); } else if (HAS_PCH_SPLIT(dev_priv)) { int found; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..92cc7fc66bce 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1433,6 +1433,11 @@ struct intel_dp_mst_encoder { struct intel_connector *connector; }; +struct intel_ddi_port_info { + const char *name; + enum port port; +}; + static inline enum dpio_channel vlv_dport_to_channel(struct intel_digital_port *dport) { -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 25 00:11:20 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 24 Jun 2020 17:11:20 -0700 Subject: [Intel-gfx] [PATCH v2 6/6] drm/i915/display: replace port to phy conversions in intel_ddi.c In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <20200625001120.22810-7-lucas.demarchi@intel.com> This is the first level conversion to use port_info directly from intel_digital_port, rather than derive the phy or tc_port from the port. This touches only the functions which have the encoder or dig_port directly available. Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 158 +++++++++++------------ 1 file changed, 77 insertions(+), 81 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 27e2f29f47a2..aa0b478ab54a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1061,11 +1061,11 @@ tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, static int intel_ddi_hdmi_level(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); int n_entries, level, default_entry; - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (INTEL_GEN(dev_priv) >= 12) { - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_ddi_has_combo_phy(dig_port)) tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, &n_entries); else @@ -1073,7 +1073,7 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder) &n_entries); default_entry = n_entries - 1; } else if (INTEL_GEN(dev_priv) == 11) { - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_ddi_has_combo_phy(dig_port)) icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, &n_entries); else @@ -1453,9 +1453,9 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - if (intel_phy_is_tc(dev_priv, phy) && + if (intel_ddi_has_tc_phy(dig_port) && intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == DPLL_ID_ICL_TBTPLL) pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, @@ -1983,7 +1983,6 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port; - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); /* * TODO: Add support for MST encoders. Atm, the following should never @@ -1996,7 +1995,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, dig_port = enc_to_dig_port(encoder); - if (!intel_phy_is_tc(dev_priv, phy) || + if (!intel_ddi_has_tc_phy(dig_port) || dig_port->tc_mode != TC_PORT_TBT_ALT) intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); @@ -2006,7 +2005,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, * ports. */ if (intel_crtc_has_dp_encoder(crtc_state) || - intel_phy_is_tc(dev_priv, phy)) + intel_ddi_has_tc_phy(dig_port)) intel_display_power_get(dev_priv, intel_ddi_main_link_aux_domain(dig_port)); @@ -2142,14 +2141,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) { - struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); int n_entries; if (INTEL_GEN(dev_priv) >= 12) { - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_ddi_has_tc_phy(dig_port)) tgl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); else @@ -2159,7 +2158,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) if (IS_ELKHARTLAKE(dev_priv)) ehl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); - else if (intel_phy_is_combo(dev_priv, phy)) + if (intel_ddi_has_tc_phy(dig_port)) icl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); else @@ -2402,8 +2401,9 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level, enum intel_output_type type) { + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + u8 phy = dig_port->port_info->phy_idx; int width = 0; int rate = 0; u32 val; @@ -2473,7 +2473,8 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, enum intel_output_type type) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u8 phy = dig_port->port_info->phy_idx; const struct icl_mg_phy_ddi_buf_trans *ddi_translations; u32 n_entries, val; int ln, rate = 0; @@ -2496,33 +2497,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ for (ln = 0; ln < 2; ln++) { - val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, phy)); val &= ~CRI_USE_FS32; - intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, phy), val); - val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, phy)); val &= ~CRI_USE_FS32; - intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, phy), val); } /* Program MG_TX_SWINGCTRL with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, phy)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( ddi_translations[level].cri_txdeemph_override_17_12); - intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, phy), val); - val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, phy)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( ddi_translations[level].cri_txdeemph_override_17_12); - intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, phy), val); } /* Program MG_TX_DRVCTRL with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, phy)); val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( @@ -2530,9 +2531,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, CRI_TXDEEMPH_OVERRIDE_11_6( ddi_translations[level].cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; - intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, phy), val); - val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, phy)); val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( @@ -2540,7 +2541,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, CRI_TXDEEMPH_OVERRIDE_11_6( ddi_translations[level].cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; - intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, phy), val); /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ } @@ -2551,17 +2552,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * values from table for which TX1 and TX2 enabled. */ for (ln = 0; ln < 2; ln++) { - val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); + val = intel_de_read(dev_priv, MG_CLKHUB(ln, phy)); if (link_clock < 300000) val |= CFG_LOW_RATE_LKREN_EN; else val &= ~CFG_LOW_RATE_LKREN_EN; - intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); + intel_de_write(dev_priv, MG_CLKHUB(ln, phy), val); } /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ for (ln = 0; ln < 2; ln++) { - val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_DCC(ln, phy)); val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; if (link_clock <= 500000) { val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; @@ -2569,9 +2570,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val |= CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); } - intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_DCC(ln, phy), val); - val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_DCC(ln, phy)); val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; if (link_clock <= 500000) { val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; @@ -2579,21 +2580,21 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val |= CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); } - intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_DCC(ln, phy), val); } /* Program MG_TX_PISO_READLOAD with values from vswing table */ for (ln = 0; ln < 2; ln++) { val = intel_de_read(dev_priv, - MG_TX1_PISO_READLOAD(ln, tc_port)); + MG_TX1_PISO_READLOAD(ln, phy)); val |= CRI_CALCINIT; - intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), + intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, phy), val); val = intel_de_read(dev_priv, - MG_TX2_PISO_READLOAD(ln, tc_port)); + MG_TX2_PISO_READLOAD(ln, phy)); val |= CRI_CALCINIT; - intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), + intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, phy), val); } } @@ -2603,10 +2604,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level, enum intel_output_type type) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_ddi_has_combo_phy(dig_port)) icl_combo_phy_ddi_vswing_sequence(encoder, level, type); else icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level, @@ -2618,7 +2618,8 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, u32 level, enum intel_output_type type) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u8 phy = dig_port->port_info->phy_idx; const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; int rate = 0; @@ -2643,25 +2644,25 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); for (ln = 0; ln < 2; ln++) { - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), - HIP_INDEX_VAL(tc_port, ln)); + intel_de_write(dev_priv, HIP_INDEX_REG(phy), + HIP_INDEX_VAL(phy, ln)); - intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); + intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(phy), 0); /* All the registers are RMW */ - val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); + val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(phy)); val &= ~dpcnt_mask; val |= dpcnt_val; - intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); + intel_de_write(dev_priv, DKL_TX_DPCNTL0(phy), val); - val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); + val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(phy)); val &= ~dpcnt_mask; val |= dpcnt_val; - intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); + intel_de_write(dev_priv, DKL_TX_DPCNTL1(phy), val); - val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); + val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(phy)); val &= ~DKL_TX_DP20BITMODE; - intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); + intel_de_write(dev_priv, DKL_TX_DPCNTL2(phy), val); } } @@ -2670,10 +2671,9 @@ static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level, enum intel_output_type type) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - if (intel_phy_is_combo(dev_priv, phy)) + if (intel_ddi_has_combo_phy(dig_port)) icl_combo_phy_ddi_vswing_sequence(encoder, level, type); else tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type); @@ -2786,8 +2786,9 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_shared_dpll *pll = crtc_state->shared_dpll; - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + u8 phy = dig_port->port_info->phy_idx; u32 val; mutex_lock(&dev_priv->dpll.lock); @@ -2796,7 +2797,7 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, drm_WARN_ON(&dev_priv->drm, (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); - if (intel_phy_is_combo(dev_priv, phy)) { + if (intel_ddi_has_combo_phy(dig_port)) { /* * Even though this register references DDIs, note that we * want to pass the PHY rather than the port (DDI). For @@ -2822,7 +2823,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u8 phy = dig_port->port_info->phy_idx; u32 val; mutex_lock(&dev_priv->dpll.lock); @@ -2923,10 +2925,10 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + const struct intel_shared_dpll *pll = crtc_state->shared_dpll; enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); u32 val; - const struct intel_shared_dpll *pll = crtc_state->shared_dpll; if (drm_WARN_ON(&dev_priv->drm, !pll)) return; @@ -2934,7 +2936,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, mutex_lock(&dev_priv->dpll.lock); if (INTEL_GEN(dev_priv) >= 11) { - if (!intel_phy_is_combo(dev_priv, phy)) + if (intel_ddi_has_combo_phy(dig_port)) intel_de_write(dev_priv, DDI_CLK_SEL(port), icl_pll_to_ddi_clk_sel(encoder, crtc_state)); else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) @@ -2981,11 +2983,11 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, static void intel_ddi_clk_disable(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); if (INTEL_GEN(dev_priv) >= 11) { - if (!intel_phy_is_combo(dev_priv, phy) || + if (!intel_ddi_has_combo_phy(dig_port) || (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) intel_de_write(dev_priv, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); @@ -3150,8 +3152,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u8 phy = dig_port->port_info->phy_idx; bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); int level = intel_ddi_dp_level(intel_dp); enum transcoder transcoder = crtc_state->cpu_transcoder; @@ -3190,7 +3192,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_ddi_clk_select(encoder, crtc_state); /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ - if (!intel_phy_is_tc(dev_priv, phy) || + if (!intel_ddi_has_tc_phy(dig_port) || dig_port->tc_mode != TC_PORT_TBT_ALT) intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); @@ -3236,7 +3238,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up * the used lanes of the DDI. */ - if (intel_phy_is_combo(dev_priv, phy)) { + if (intel_ddi_has_combo_phy(dig_port)) { bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; @@ -3292,8 +3294,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u8 phy = dig_port->port_info->phy_idx; bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); int level = intel_ddi_dp_level(intel_dp); @@ -3310,7 +3312,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_ddi_clk_select(encoder, crtc_state); - if (!intel_phy_is_tc(dev_priv, phy) || + if (!intel_ddi_has_tc_phy(dig_port) || dig_port->tc_mode != TC_PORT_TBT_ALT) intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); @@ -3327,7 +3329,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, else intel_prepare_dp_ddi_buffers(encoder, crtc_state); - if (intel_phy_is_combo(dev_priv, phy)) { + if (intel_ddi_has_combo_phy(dig_port)) { bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; @@ -3508,7 +3510,6 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, struct intel_dp *intel_dp = &dig_port->dp; bool is_mst = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (!is_mst) intel_dp_set_infoframes(encoder, false, @@ -3551,7 +3552,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_edp_panel_vdd_on(intel_dp); intel_edp_panel_off(intel_dp); - if (!intel_phy_is_tc(dev_priv, phy) || + if (!intel_ddi_has_tc_phy(dig_port) || dig_port->tc_mode != TC_PORT_TBT_ALT) intel_display_power_put_unchecked(dev_priv, dig_port->ddi_io_power_domain); @@ -3590,8 +3591,6 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - bool is_tc_port = intel_phy_is_tc(dev_priv, phy); if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { intel_crtc_vblank_off(old_crtc_state); @@ -3631,11 +3630,12 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, if (INTEL_GEN(dev_priv) >= 11) icl_unmap_plls_to_ports(encoder); - if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) + if (intel_crtc_has_dp_encoder(old_crtc_state) || + intel_ddi_has_tc_phy(dig_port)) intel_display_power_put_unchecked(dev_priv, intel_ddi_main_link_aux_domain(dig_port)); - if (is_tc_port) + if (intel_ddi_has_tc_phy(dig_port)) intel_tc_port_put_link(dig_port); } @@ -3958,17 +3958,16 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - bool is_tc_port = intel_phy_is_tc(dev_priv, phy); - if (is_tc_port) + if (intel_ddi_has_tc_phy(dig_port)) intel_tc_port_get_link(dig_port, crtc_state->lane_count); - if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) + if (intel_crtc_has_dp_encoder(crtc_state) || intel_ddi_has_tc_phy(dig_port)) intel_display_power_get(dev_priv, intel_ddi_main_link_aux_domain(dig_port)); - if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) + if (intel_ddi_has_tc_phy(dig_port) && + dig_port->tc_mode != TC_PORT_TBT_ALT) /* * Program the lane count for static/dynamic connections on * Type-C ports. Skip this step for TBT. @@ -4682,10 +4681,7 @@ static enum intel_hotplug_state intel_ddi_hotplug(struct intel_encoder *encoder, struct intel_connector *connector) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - enum phy phy = intel_port_to_phy(i915, encoder->port); - bool is_tc = intel_phy_is_tc(i915, phy); struct drm_modeset_acquire_ctx ctx; enum intel_hotplug_state state; int ret; @@ -4736,7 +4732,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder, * connectors to account for this delay. */ if (state == INTEL_HOTPLUG_UNCHANGED && - connector->hotplug_retries < (is_tc ? 5 : 1) && + connector->hotplug_retries < (intel_ddi_has_tc_phy(dig_port) ? 5 : 1) && !dig_port->dp.is_mst) state = INTEL_HOTPLUG_RETRY; -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 25 00:11:18 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 24 Jun 2020 17:11:18 -0700 Subject: [Intel-gfx] [PATCH v2 4/6] drm/i915/display: add phy, vbt and ddi indexes In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <20200625001120.22810-5-lucas.demarchi@intel.com> Identify 3 possible cases in which the index numbers can be different from the "port" and add them to the description-based ddi initialization table. This can be used in place of additional functions mapping from one to the other. Right now we already cover part of this by creating kind of virtual phy numbering, but that comes with downsides: a) there's not really a "phy numbering" in the spec, this is purely a software thing; hardware uses whatever they want thinking mapping from one to the other arbitrarily is easy in software. b) currently the mapping occurs on "leaf" functions, making the decision based on the platform for each of those functions With this new table the approach will be: the port, as defined by the enum port, is merely a driver convention and won't be used anymore to define the register offset or register bits. For that we have the other 3 indexes, identified as being possibly different from the current usage of register bits: ddi, vbt and phy. The phy type is also added here, meant to replace the checks for combo vs tc. v2: Rebase and add RKL Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 64 ++++++++++--------- drivers/gpu/drm/i915/display/intel_display.h | 8 +++ .../drm/i915/display/intel_display_types.h | 4 ++ 3 files changed, 45 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c234b50212b0..d591063502c5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16806,57 +16806,59 @@ static void intel_pps_init(struct drm_i915_private *dev_priv) } static const struct intel_ddi_port_info rkl_ports[] = { - { .name = "DDI A", .port = PORT_A }, - { .name = "DDI B", .port = PORT_B }, - { .name = "DDI TC1", .port = PORT_D }, - { .name = "DDI TC2", .port = PORT_E }, + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, }, + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, }, + /* TODO: use continguous namespace for port once driver is converted */ + { .name = "DDI C", .port = PORT_D, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x3, .phy_idx = 0x2, .vbt_idx = 0x2, }, + { .name = "DDI D", .port = PORT_E, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x4, .phy_idx = 0x3, .vbt_idx = 0x3, }, { .port = PORT_NONE } }; static const struct intel_ddi_port_info tgl_ports[] = { - { .name = "DDI A", .port = PORT_A }, - { .name = "DDI B", .port = PORT_B }, - { .name = "DDI TC1", .port = PORT_D }, - { .name = "DDI TC2", .port = PORT_E }, - { .name = "DDI TC3", .port = PORT_F }, - { .name = "DDI TC4", .port = PORT_G }, - { .name = "DDI TC5", .port = PORT_H }, - { .name = "DDI TC6", .port = PORT_I }, + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, }, + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, }, + /* TODO: use continguous namespace for port once driver is converted */ + { .name = "DDI TC1", .port = PORT_D, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x3, .phy_idx = 0x0, .vbt_idx = 0x2, }, + { .name = "DDI TC2", .port = PORT_E, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x4, .phy_idx = 0x1, .vbt_idx = 0x3, }, + { .name = "DDI TC3", .port = PORT_F, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x5, .phy_idx = 0x2, .vbt_idx = 0x4, }, + { .name = "DDI TC4", .port = PORT_G, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x6, .phy_idx = 0x3, .vbt_idx = 0x5, }, + { .name = "DDI TC5", .port = PORT_H, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x7, .phy_idx = 0x4, .vbt_idx = 0x6, }, + { .name = "DDI TC6", .port = PORT_I, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x8, .phy_idx = 0x5, .vbt_idx = 0x7, }, { .port = PORT_NONE } }; static const struct intel_ddi_port_info ehl_ports[] = { - { .name = "DDI A", .port = PORT_A }, - { .name = "DDI B", .port = PORT_B }, - { .name = "DDI C", .port = PORT_C }, - { .name = "DDI D", .port = PORT_D }, + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, }, + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, }, + { .name = "DDI C", .port = PORT_C, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x2, .phy_idx = 0x2, .vbt_idx = 0x2, }, + { .name = "DDI D", .port = PORT_D, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x3, .phy_idx = 0x0, .vbt_idx = 0x3, }, { .port = PORT_NONE } }; static const struct intel_ddi_port_info icl_ports[] = { - { .name = "DDI A", .port = PORT_A }, - { .name = "DDI B", .port = PORT_B }, - { .name = "DDI TC1", .port = PORT_C }, - { .name = "DDI TC2", .port = PORT_D }, - { .name = "DDI TC3", .port = PORT_E }, - { .name = "DDI TC4", .port = PORT_F }, + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0,}, + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1,}, + { .name = "DDI TC1", .port = PORT_C, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x2, .phy_idx = 0x0, .vbt_idx = 0x2,}, + { .name = "DDI TC2", .port = PORT_D, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x3, .phy_idx = 0x1, .vbt_idx = 0x3,}, + { .name = "DDI TC3", .port = PORT_E, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x4, .phy_idx = 0x2, .vbt_idx = 0x4,}, + { .name = "DDI TC4", .port = PORT_F, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x5, .phy_idx = 0x3, .vbt_idx = 0x5,}, { .port = PORT_NONE } }; static const struct intel_ddi_port_info gen9lp_ports[] = { - { .name = "DDI A", .port = PORT_A }, - { .name = "DDI B", .port = PORT_B }, - { .name = "DDI C", .port = PORT_C }, + { .name = "DDI A", .port = PORT_A, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0 }, + { .name = "DDI B", .port = PORT_B, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1 }, + { .name = "DDI C", .port = PORT_C, .ddi_idx = 0x2, .phy_idx = 0x2, .vbt_idx = 0x2 }, { .port = PORT_NONE } }; static const struct intel_ddi_port_info ddi_ports[] = { - { .name = "DDI A", .port = PORT_A }, - { .name = "DDI B", .port = PORT_B }, - { .name = "DDI C", .port = PORT_C }, - { .name = "DDI D", .port = PORT_D }, - { .name = "DDI E", .port = PORT_E }, - { .name = "DDI F", .port = PORT_F }, + { .name = "DDI A", .port = PORT_A, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0 }, + { .name = "DDI B", .port = PORT_B, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1 }, + { .name = "DDI C", .port = PORT_C, .ddi_idx = 0x2, .phy_idx = 0x2, .vbt_idx = 0x2 }, + { .name = "DDI D", .port = PORT_D, .ddi_idx = 0x3, .phy_idx = 0x3, .vbt_idx = 0x3 }, + { .name = "DDI E", .port = PORT_E, .ddi_idx = 0x4, .phy_idx = 0x4, .vbt_idx = 0x4 }, + { .name = "DDI F", .port = PORT_F, .ddi_idx = 0x5, .phy_idx = 0x5, .vbt_idx = 0x5 }, { .port = PORT_NONE } }; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b7a6d56bac5f..22c999a54ff1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -311,6 +311,14 @@ enum phy { I915_MAX_PHYS }; +enum phy_type { + PHY_TYPE_NONE = 0, + + PHY_TYPE_COMBO, + PHY_TYPE_MG, + PHY_TYPE_DKL, +}; + #define phy_name(a) ((a) + 'A') enum phy_fia { diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 92cc7fc66bce..df587219c744 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1436,6 +1436,10 @@ struct intel_dp_mst_encoder { struct intel_ddi_port_info { const char *name; enum port port; + s8 phy_type; + u8 ddi_idx; + u8 phy_idx; + u8 vbt_idx; }; static inline enum dpio_channel -- 2.26.2 From lucas.demarchi at intel.com Thu Jun 25 00:11:19 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Wed, 24 Jun 2020 17:11:19 -0700 Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915/display: use port_info in intel_ddi_init In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <20200625001120.22810-6-lucas.demarchi@intel.com> Now that we have tables for all platforms using ddi, keep the port_info around so we can use it for decisions like "what phy does it have?" instead of keep checking the platform/gen everywhere. Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 39 ++++++++++++------- drivers/gpu/drm/i915/display/intel_ddi.h | 8 +++- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_types.h | 3 ++ 4 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ca7bb2294d2b..27e2f29f47a2 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4844,12 +4844,24 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) return max_lanes; } -void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) +bool intel_ddi_has_tc_phy(const struct intel_digital_port *dig_port) { + return dig_port->port_info->phy_type == PHY_TYPE_MG || + dig_port->port_info->phy_type == PHY_TYPE_DKL; +} + +bool intel_ddi_has_combo_phy(const struct intel_digital_port *dig_port) +{ + return dig_port->port_info->phy_type == PHY_TYPE_COMBO; +} + +void intel_ddi_init(struct drm_i915_private *dev_priv, + const struct intel_ddi_port_info *port_info) +{ + enum port port = port_info->port; struct intel_digital_port *intel_dig_port; struct intel_encoder *encoder; bool init_hdmi, init_dp, init_lspcon = false; - enum phy phy = intel_port_to_phy(dev_priv, port); init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || intel_bios_port_supports_hdmi(dev_priv, port); @@ -4864,14 +4876,14 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) init_dp = true; init_lspcon = true; init_hdmi = false; - drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", - port_name(port)); + drm_dbg_kms(&dev_priv->drm, "VBT says port %s has lspcon\n", + port_info->name); } if (!init_dp && !init_hdmi) { drm_dbg_kms(&dev_priv->drm, - "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", - port_name(port)); + "VBT says port %s is not DVI/HDMI/DP compatible, respect it\n", + port_info->name); return; } @@ -4882,7 +4894,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder = &intel_dig_port->base; drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, - DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); + DRM_MODE_ENCODER_TMDS, port_info->name); encoder->hotplug = intel_ddi_hotplug; encoder->compute_output_type = intel_ddi_compute_output_type; @@ -4917,8 +4929,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) intel_dig_port->dp.output_reg = INVALID_MMIO_REG; intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); + intel_dig_port->port_info = port_info; - if (intel_phy_is_tc(dev_priv, phy)) { + if (intel_ddi_has_tc_phy(intel_dig_port)) { bool is_legacy = !intel_bios_port_supports_typec_usb(dev_priv, port) && !intel_bios_port_supports_tbt(dev_priv, port); @@ -4951,20 +4964,20 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) if (lspcon_init(intel_dig_port)) /* TODO: handle hdmi info frame part */ drm_dbg_kms(&dev_priv->drm, - "LSPCON init success on port %c\n", - port_name(port)); + "LSPCON init success on port %s\n", + port_info->name); else /* * LSPCON init faied, but DP init was success, so * lets try to drive as DP++ port. */ drm_err(&dev_priv->drm, - "LSPCON init failed on port %c\n", - port_name(port)); + "LSPCON init failed on port %s\n", + port_info->name); } if (INTEL_GEN(dev_priv) >= 11) { - if (intel_phy_is_tc(dev_priv, phy)) + if (intel_ddi_has_tc_phy(intel_dig_port)) intel_dig_port->connected = intel_tc_port_connected; else intel_dig_port->connected = lpt_digital_port_connected; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 077e9dbbe367..059d87171c81 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -13,6 +13,7 @@ struct drm_i915_private; struct intel_connector; struct intel_crtc; struct intel_crtc_state; +struct intel_ddi_port_info; struct intel_dp; struct intel_dpll_hw_state; struct intel_encoder; @@ -23,7 +24,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state); void hsw_fdi_link_train(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); -void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); +void intel_ddi_init(struct drm_i915_private *dev_priv, + const struct intel_ddi_port_info *port_info); bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); @@ -46,4 +48,8 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, bool enable); void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); + +bool intel_ddi_has_tc_phy(const struct intel_digital_port *dig_port); +bool intel_ddi_has_combo_phy(const struct intel_digital_port *dig_port); + #endif /* __INTEL_DDI_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d591063502c5..001b44c004ab 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -16880,7 +16880,7 @@ static void setup_ddi_outputs_desc(struct drm_i915_private *i915, if (test_bit(port_info->port, &disable_mask)) continue; - intel_ddi_init(i915, port_info->port); + intel_ddi_init(i915, port_info); } } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index df587219c744..7f2156e6966f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1402,6 +1402,9 @@ struct intel_digital_port { enum intel_display_power_domain ddi_io_power_domain; struct mutex tc_lock; /* protects the TypeC port mode */ intel_wakeref_t tc_lock_wakeref; + + const struct intel_ddi_port_info *port_info; + int tc_link_refcount; bool tc_legacy_port:1; char tc_port_name[8]; -- 2.26.2 From jose.souza at intel.com Thu Jun 25 00:18:54 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 00:18:54 +0000 Subject: [Intel-gfx] [PATCH v2 2/3] drm/i915/display: Implement HOBL In-Reply-To: <57dcd40d816546b4aad57feeb73131817a8419fd.camel@intel.com> References: <20200603194308.78622-1-jose.souza@intel.com> <20200603194308.78622-2-jose.souza@intel.com> <20200603203346.GQ6112@intel.com> <57dcd40d816546b4aad57feeb73131817a8419fd.camel@intel.com> Message-ID: <e9e3774a6baa66f714dc954fd0c3e58dfe38bbcb.camel@intel.com> On Wed, 2020-06-03 at 20:55 +0000, Souza, Jose wrote: > On Wed, 2020-06-03 at 23:33 +0300, Ville Syrj?l? wrote: > > On Wed, Jun 03, 2020 at 12:43:07PM -0700, Jos? Roberto de Souza wrote: > > > Hours Of Battery Life is a new GEN12+ power-saving feature that allows > > > supported motherboards to use a special voltage swing table for eDP > > > panels that uses less power. > > > > > > So here if supported by HW, OEM will set it in VBT and i915 will try > > > to train link with HOBL vswing table if link training fails it fall > > > back to the original table. > > > > > > Just not sure if DP compliance should also use this new voltage swing > > > table too, cced some folks that worked in DP compliance. > > > > > > BSpec: 49291 > > > BSpec: 49399 > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Animesh Manna <animesh.manna at intel.com> > > > Cc: Manasi Navare <manasi.d.navare at intel.com> > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++-- > > > .../drm/i915/display/intel_display_types.h | 2 + > > > .../drm/i915/display/intel_dp_link_training.c | 20 +++++++- > > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > > drivers/gpu/drm/i915/i915_reg.h | 2 + > > > 5 files changed, 69 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 236f3762b6f9..57174a111976 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -692,6 +692,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = > > > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > > > }; > > > > > > +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { > > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 } > > > +}; > > > + > > > static const struct ddi_buf_trans * > > > bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > > > { > > > @@ -2301,14 +2305,51 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > > > intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); > > > } > > > > > > +/* > > > + * If supported return HOBL vswing table and set registers to enable HOBL > > > + * otherwise returns NULL and unset registers to enable HOBL. > > > + */ > > > +static const struct cnl_ddi_buf_trans * > > > +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv, > > > + struct intel_encoder *encoder, int type, int rate, > > > + u32 level, int *n_entries) > > > +{ > > > + const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; > > > + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > > + struct intel_dp *intel_dp; > > > + > > > + if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP) > > > + return NULL; > > > > Not a real fan of the "hobl" name. It just sounds like nonsense. Also > > bspec doesn't use that term at all. It only appears in the vbt spec. > > Not sure if there's a better one though. > > Maybe power_optimized_edp? In the lack of a better name will keep the current one, also it will allow for people to find some reference to it in BSpec. > > > > + > > > + intel_dp = enc_to_intel_dp(encoder); > > > + if (!intel_dp->try_hobl || rate > 540000) { > > > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0); > > > > I would vote for just doing this programming unconditionally in the normal > > sequence. > > Thought about that but intel_combo_phy_power_up_lanes() that program this ICL_PORT_CL_DW10 is called right after tgl_ddi_vswing_sequence(). > > > > + return NULL; > > > + } > > > + > > > + drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy)); > > > + drm_WARN_ON_ONCE(&dev_priv->drm, level > 0); > > > + > > > + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en); > > > + /* Same table applies to TGL, RKL and DG1 */ > > > + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); > > > + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; > > > +} > > > + > > > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > > > - u32 level, enum phy phy, int type, > > > - int rate) > > > + struct intel_encoder *encoder, > > > + u32 level, enum phy phy, int type, > > > + int rate) > > > > If we're passing in the encoder then a bunch of this other stuff is > > redundant. > > Okay Reduced to: static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, u32 level, enum intel_output_type type, int rate) type can't be removed because of HDMI paths, rate could but it is used in the caller too so I left it. > > > > { > > > const struct cnl_ddi_buf_trans *ddi_translations = NULL; > > > u32 n_entries, val; > > > int ln; > > > > > > + ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type, > > > + rate, level, &n_entries); > > > + if (ddi_translations) > > > + goto hobl_found; > > > > Why not just put it into tgl_get_combo_buf_trans(). Hmm. I guess to not > > upset .voltage_max(). This feels a bit hackish, but I don't have better > > ideas for now. > > Exactly. > > > > + > > > if (INTEL_GEN(dev_priv) >= 12) > > > ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, > > > &n_entries); > > > @@ -2321,6 +2362,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > > > if (!ddi_translations) > > > return; > > > > > > +hobl_found: > > > if (level >= n_entries) { > > > drm_dbg_kms(&dev_priv->drm, > > > "DDI translation not found for level %d. Using %d instead.", > > > @@ -2428,7 +2470,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > > intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); > > > > > > /* 5. Program swing and de-emphasis */ > > > - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); > > > + icl_ddi_combo_vswing_program(dev_priv, encoder, level, phy, type, rate); > > > > > > /* 6. Set training enable to trigger update */ > > > val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > > > index 4b0aaa3081c9..f8943b67819d 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -1375,6 +1375,8 @@ struct intel_dp { > > > > > > /* Display stream compression testing */ > > > bool force_dsc_en; > > > + > > > + bool try_hobl; > > > }; > > > > > > enum lspcon_vendor { > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > index b9e4ee2dbddc..88f366bb28d7 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > > > @@ -52,12 +52,24 @@ static u8 dp_voltage_max(u8 preemph) > > > void intel_dp_get_adjust_train(struct intel_dp *intel_dp, > > > const u8 link_status[DP_LINK_STATUS_SIZE]) > > > { > > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > u8 v = 0; > > > u8 p = 0; > > > int lane; > > > u8 voltage_max; > > > u8 preemph_max; > > > > > > + if (intel_dp->try_hobl) { > > > + /* > > > + * Do not adjust, try now with the regular table using VSwing 0 > > > + * and pre-emp 0 > > > + */ > > > > What if the sink is still asking for vswing 0 + preemph 0? The spec is > > rather ambiguous when it comes to this stuff. > > As it will fallback to regular table vswing 0 + preemph 0 that is not a issue. > > > The table also doesn't specify the vswing/preemph for which we should > > use this optimized value. Your interpretation of 0+0 seems like the most > > sensible thing, but given that the VBT can also specifiy the fast link > > training vswing/preemph as something else (and maybe there was also > > something like this for normal link training?) I'm not 100% sure. > > Yeah don't make much sense it not be vswing 0 + preemph 0 but lets wait for BSpec clarification then. > > > Hmm. Actually noticed that all the eDP tables are missing the > > vswing/preemph levels (they do have the raw mV/dB values but not the > > DP spec levels). I filed a few issues in the hopes of clarification. > > > > > + intel_dp->try_hobl = false; > > > + drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link " > > > + "training, switching back to regular table\n"); > > > + return; > > > + } > > > + > > > for (lane = 0; lane < intel_dp->lane_count; lane++) { > > > v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); > > > p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); > > > @@ -103,9 +115,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, > > > } > > > > > > static bool > > > -intel_dp_reset_link_train(struct intel_dp *intel_dp, > > > - u8 dp_train_pat) > > > +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) > > > { > > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > + > > > + if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) > > > + intel_dp->try_hobl = true; > > > > If it failed once does it make sense to keep trying to use it? > > It could pass in a different bit rate and would be to much complicated keep track of that. > > > Thanks for the review, lets wait for the BSpec clarifications that you asked. > > > > + > > > memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); > > > intel_dp_set_signal_levels(intel_dp); > > > return intel_dp_set_link_train(intel_dp, dp_train_pat); > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > > index 2336c9231eef..c7e7df17eef2 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > @@ -1687,6 +1687,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > > #define INTEL_DISPLAY_ENABLED(dev_priv) \ > > > (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !i915_modparams.disable_display) > > > > > > +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12) > > > + > > > static inline bool intel_vtd_active(void) > > > { > > > #ifdef CONFIG_INTEL_IOMMU > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > index 578cfe11cbb9..d4611171f075 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -1896,6 +1896,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > > #define PWR_DOWN_LN_3_1_0 (0xb << 4) > > > #define PWR_DOWN_LN_MASK (0xf << 4) > > > #define PWR_DOWN_LN_SHIFT 4 > > > +#define EDP4K2K_MODE_OVRD_EN (1 << 3) > > > +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) > > > > > > #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) > > > #define ICL_LANE_ENABLE_AUX (1 << 0) > > > -- > > > 2.27.0 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From jose.souza at intel.com Thu Jun 25 00:29:04 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Wed, 24 Jun 2020 17:29:04 -0700 Subject: [Intel-gfx] [PATCH v3 1/3] drm/i915/bios: Parse HOBL parameter Message-ID: <20200625002906.116594-1-jose.souza@intel.com> HOBL means hours of battery life, it is a power-saving feature were supported motherboards can use a special voltage swing table that uses less power. So here parsing the VBT to check if this feature is supported. BSpec: 20150 Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 3 +++ drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 + drivers/gpu/drm/i915/i915_drv.h | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 6593e2c38043..c53c85d38fa5 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -722,6 +722,9 @@ parse_power_conservation_features(struct drm_i915_private *dev_priv, */ if (!(power->drrs & BIT(panel_type))) dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; + + if (bdb->version >= 232) + dev_priv->vbt.edp.hobl = power->hobl & BIT(panel_type); } static void diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index aef7fe932d1a..6faabd4f6d49 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -820,6 +820,7 @@ struct bdb_lfp_power { u16 adb; u16 lace_enabled_status; struct agressiveness_profile_entry aggressivenes[16]; + u16 hobl; /* 232+ */ } __packed; /* diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9aad3ec979bd..16692c94351a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -690,6 +690,7 @@ struct intel_vbt_data { bool initialized; int bpp; struct edp_power_seq pps; + bool hobl; } edp; struct { -- 2.27.0 From jose.souza at intel.com Thu Jun 25 00:29:06 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Wed, 24 Jun 2020 17:29:06 -0700 Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Enable HOBL regardless the VBT value In-Reply-To: <20200625002906.116594-1-jose.souza@intel.com> References: <20200625002906.116594-1-jose.souza@intel.com> Message-ID: <20200625002906.116594-3-jose.souza@intel.com> HOBL worked in my TGL RVP even without the necessary HW support, also it worked in more than half of the TGL machines in CI so it is worthy to enable it by default. Even if link training fails with this new vswing table it will only cause one additional link training, that is worthy the try to get the additional power-savings. Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 88f366bb28d7..13f7bc0a4bc0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -119,7 +119,7 @@ intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) + if (HAS_HOBL(dev_priv) && intel_dp_is_edp(intel_dp)) intel_dp->try_hobl = true; memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); -- 2.27.0 From jose.souza at intel.com Thu Jun 25 00:29:05 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Wed, 24 Jun 2020 17:29:05 -0700 Subject: [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Implement HOBL In-Reply-To: <20200625002906.116594-1-jose.souza@intel.com> References: <20200625002906.116594-1-jose.souza@intel.com> Message-ID: <20200625002906.116594-2-jose.souza@intel.com> Hours Of Battery Life is a new GEN12+ power-saving feature that allows supported motherboards to use a special voltage swing table for eDP panels that uses less power. So here if supported by HW, OEM will set it in VBT and i915 will try to train link with HOBL vswing table if link training fails it fall back to the original table. Just not sure if DP compliance should also use this new voltage swing table too, cced some folks that worked in DP compliance. v3: - removed a few parameters of icl_ddi_combo_vswing_program() that can be taken from encoder BSpec: 49291 BSpec: 49399 Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Animesh Manna <animesh.manna at intel.com> Cc: Manasi Navare <manasi.d.navare at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 51 +++++++++++++++++-- .../drm/i915/display/intel_display_types.h | 2 + .../drm/i915/display/intel_dp_link_training.c | 20 +++++++- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 2 + 5 files changed, 71 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 884b507c5f55..56216aa0d74a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -706,6 +706,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ }; +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { + { 0x6, 0x7F, 0x3F, 0x00, 0x00 } +}; + static const struct ddi_buf_trans * bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) { @@ -2331,14 +2335,52 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); } -static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, - u32 level, enum phy phy, int type, - int rate) +/* + * If supported return HOBL vswing table and set registers to enable HOBL + * otherwise returns NULL and unset registers to enable HOBL. + */ +static const struct cnl_ddi_buf_trans * +hobl_get_combo_buf_trans(struct drm_i915_private *dev_priv, + struct intel_encoder *encoder, int type, int rate, + u32 level, int *n_entries) { + const u32 hobl_en = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + struct intel_dp *intel_dp; + + if (!HAS_HOBL(dev_priv) || type != INTEL_OUTPUT_EDP) + return NULL; + + intel_dp = enc_to_intel_dp(encoder); + if (!intel_dp->try_hobl || rate > 540000) { + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, 0); + return NULL; + } + + drm_dbg_kms(&dev_priv->drm, "Enabling HOBL in PHY %c\n", phy_name(phy)); + drm_WARN_ON_ONCE(&dev_priv->drm, level > 0); + + intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), hobl_en, hobl_en); + /* Same table applies to TGL, RKL and DG1 */ + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); + return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; +} + +static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, + u32 level, enum intel_output_type type, + int rate) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); const struct cnl_ddi_buf_trans *ddi_translations = NULL; u32 n_entries, val; int ln; + ddi_translations = hobl_get_combo_buf_trans(dev_priv, encoder, type, + rate, level, &n_entries); + if (ddi_translations) + goto table_found; + if (INTEL_GEN(dev_priv) >= 12) ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, &n_entries); @@ -2351,6 +2393,7 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, if (!ddi_translations) return; +table_found: if (level >= n_entries) { drm_dbg_kms(&dev_priv->drm, "DDI translation not found for level %d. Using %d instead.", @@ -2458,7 +2501,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); + icl_ddi_combo_vswing_program(encoder, level, type, rate); /* 6. Set training enable to trigger update */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..f8943b67819d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1375,6 +1375,8 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; + + bool try_hobl; }; enum lspcon_vendor { diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index b9e4ee2dbddc..88f366bb28d7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -52,12 +52,24 @@ static u8 dp_voltage_max(u8 preemph) void intel_dp_get_adjust_train(struct intel_dp *intel_dp, const u8 link_status[DP_LINK_STATUS_SIZE]) { + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 v = 0; u8 p = 0; int lane; u8 voltage_max; u8 preemph_max; + if (intel_dp->try_hobl) { + /* + * Do not adjust, try now with the regular table using VSwing 0 + * and pre-emp 0 + */ + intel_dp->try_hobl = false; + drm_dbg_kms(&dev_priv->drm, "HOBL vswing table failed link " + "training, switching back to regular table\n"); + return; + } + for (lane = 0; lane < intel_dp->lane_count; lane++) { v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); @@ -103,9 +115,13 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, } static bool -intel_dp_reset_link_train(struct intel_dp *intel_dp, - u8 dp_train_pat) +intel_dp_reset_link_train(struct intel_dp *intel_dp, u8 dp_train_pat) { + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.hobl) + intel_dp->try_hobl = true; + memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); intel_dp_set_signal_levels(intel_dp); return intel_dp_set_link_train(intel_dp, dp_train_pat); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 16692c94351a..984da03421c3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1697,6 +1697,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) +#define HAS_HOBL(dev_priv) (INTEL_GEN(dev_priv) >= 12) + static inline bool intel_vtd_active(void) { #ifdef CONFIG_INTEL_IOMMU diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..6be5087b5d92 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1898,6 +1898,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define PWR_DOWN_LN_3_1_0 (0xb << 4) #define PWR_DOWN_LN_MASK (0xf << 4) #define PWR_DOWN_LN_SHIFT 4 +#define EDP4K2K_MODE_OVRD_EN (1 << 3) +#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) #define ICL_LANE_ENABLE_AUX (1 << 0) -- 2.27.0 From jose.souza at intel.com Thu Jun 25 00:41:49 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 00:41:49 +0000 Subject: [Intel-gfx] [PATCH 08/12] drm/i915/fbc: Parametrize FBC_CONTROL In-Reply-To: <20200429101034.8208-9-ville.syrjala@linux.intel.com> References: <20200429101034.8208-1-ville.syrjala@linux.intel.com> <20200429101034.8208-9-ville.syrjala@linux.intel.com> Message-ID: <020dd40ec1ba20d07897ac37bfcaa047090358fd.camel@intel.com> On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Parametrize the FBC_CONTROL bits for neater code. > > Also add the one missing bit: "stop compression on modification". > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 8 ++++---- > drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++------- > 2 files changed, 15 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index 56eeafa645de..dbef58af4b94 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -133,13 +133,13 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) > > /* enable it... */ > fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); > - fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; > + fbc_ctl &= FBC_CTL_INTERVAL(0x3fff); > fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; > if (IS_I945GM(dev_priv)) > fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ > - fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; > + fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff); > if (params->fence_id >= 0) > - fbc_ctl |= params->fence_id; > + fbc_ctl |= FBC_CTL_FENCENO(params->fence_id); > intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); > } > > @@ -1452,7 +1452,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) > /* This value was pulled out of someone's hat */ > if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) > intel_de_write(dev_priv, FBC_CONTROL, > - 500 << FBC_CTL_INTERVAL_SHIFT); > + FBC_CTL_INTERVAL(500)); > > /* We still don't have any sort of hardware state readout for FBC, so > * deactivate it in case the BIOS activated it to make sure software > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 088215025661..e9fb64e8f28f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3194,13 +3194,17 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ > #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ > #define FBC_CONTROL _MMIO(0x3208) > -#define FBC_CTL_EN (1 << 31) > -#define FBC_CTL_PERIODIC (1 << 30) > -#define FBC_CTL_INTERVAL_SHIFT (16) > -#define FBC_CTL_UNCOMPRESSIBLE (1 << 14) > -#define FBC_CTL_C3_IDLE (1 << 13) > -#define FBC_CTL_STRIDE_SHIFT (5) > -#define FBC_CTL_FENCENO_SHIFT (0) > +#define FBC_CTL_EN REG_BIT(31) > +#define FBC_CTL_PERIODIC REG_BIT(30) > +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) > +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) > +#define FBC_CTL_STOP_ON_MOD REG_BIT(15) > +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ > +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */ > +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) > +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) > +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) > +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) > #define FBC_COMMAND _MMIO(0x320c) > #define FBC_CMD_COMPRESS (1 << 0) > #define FBC_STATUS _MMIO(0x3210) From jose.souza at intel.com Thu Jun 25 00:47:07 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 00:47:07 +0000 Subject: [Intel-gfx] [PATCH 09/12] drm/i915/fbc: Store the fbc1 compression interval in the params In-Reply-To: <20200429101034.8208-10-ville.syrjala@linux.intel.com> References: <20200429101034.8208-1-ville.syrjala@linux.intel.com> <20200429101034.8208-10-ville.syrjala@linux.intel.com> Message-ID: <841d8f8d66900609ebd1d37e4314cb3486d2a22a.camel@intel.com> On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Avoid the FBC_CONTROL rmw and just store the fbc compression > interval in the params/ Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 13 ++++++------- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > 2 files changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index dbef58af4b94..b1eb6a2ecc43 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -132,8 +132,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) > } > > /* enable it... */ > - fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); > - fbc_ctl &= FBC_CTL_INTERVAL(0x3fff); > + fbc_ctl = FBC_CTL_INTERVAL(params->interval); CI results are good so no need to keep any bit that we don't touch set. > fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; > if (IS_I945GM(dev_priv)) > fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ > @@ -728,6 +727,9 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, > cache->fb.modifier = fb->modifier; > cache->fb.stride = plane_state->color_plane[0].stride; > > + /* This value was pulled out of someone's hat */ > + cache->interval = 500; > + > cache->fence_y_offset = intel_plane_fence_y_offset(plane_state); > > drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE && > @@ -902,6 +904,8 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, > params->fence_id = cache->fence_id; > params->fence_y_offset = cache->fence_y_offset; > > + params->interval = cache->interval; > + > params->crtc.pipe = crtc->pipe; > params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane; > > @@ -1449,11 +1453,6 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) > return; > } > > - /* This value was pulled out of someone's hat */ > - if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) > - intel_de_write(dev_priv, FBC_CONTROL, > - FBC_CTL_INTERVAL(500)); > - > /* We still don't have any sort of hardware state readout for FBC, so > * deactivate it in case the BIOS activated it to make sure software > * matches the hardware state. */ > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a634fd2330c3..bc66a7cb886b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -419,6 +419,7 @@ struct intel_fbc { > > unsigned int fence_y_offset; > u16 gen9_wa_cfb_stride; > + u16 interval; > s8 fence_id; > } state_cache; > > @@ -443,6 +444,7 @@ struct intel_fbc { > int cfb_size; > unsigned int fence_y_offset; > u16 gen9_wa_cfb_stride; > + u16 interval; > s8 fence_id; > bool plane_visible; > } params; From jose.souza at intel.com Thu Jun 25 00:49:34 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 00:49:34 +0000 Subject: [Intel-gfx] [PATCH 10/12] drm/i915/fbc: Reduce fbc1 compression interval to 1 second In-Reply-To: <20200429101034.8208-11-ville.syrjala@linux.intel.com> References: <20200429101034.8208-1-ville.syrjala@linux.intel.com> <20200429101034.8208-11-ville.syrjala@linux.intel.com> Message-ID: <2f978af905a5f1417038396e1d1f62c393ec0ae4.camel@intel.com> On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > The default fbc1 compression interval we use is 500 frames. That > translates to over 8 seconds typically. That's rather excessive > so let's drop it to 1 second. > > The hardware will not attempt recompression unless at least one > line has been modified, so a shorter compression interval should > not cause extra bandwidth use in the purely idle scenario. Of > course in the mostly idle case we are possibly going to recompress > a bit more. > > Should really try to find some kind of sweet spot to minimize > the energy usage... Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index b1eb6a2ecc43..6ee45d634cf6 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -727,8 +727,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, > cache->fb.modifier = fb->modifier; > cache->fb.stride = plane_state->color_plane[0].stride; > > - /* This value was pulled out of someone's hat */ > - cache->interval = 500; > + /* FBC1 compression interval: arbitrary choice of 1 second */ > + cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); > > cache->fence_y_offset = intel_plane_fence_y_offset(plane_state); > From jose.souza at intel.com Thu Jun 25 00:59:35 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 00:59:35 +0000 Subject: [Intel-gfx] [PATCH 12/12] drm/i915: Suppress spurious underruns on gen2 In-Reply-To: <20200429101034.8208-13-ville.syrjala@linux.intel.com> References: <20200429101034.8208-1-ville.syrjala@linux.intel.com> <20200429101034.8208-13-ville.syrjala@linux.intel.com> Message-ID: <afd9ee010880718b31862b8b7cf478e36240ca91.camel@intel.com> On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Often we seem to detect an underrun right after modeset on gen2. > It seems to be a spurious detection (potentially the pipe is still > in a wonky state when we enable the planes). An extra vblank wait > seems to cure it. Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index a0d1057d75ee..f330054e64c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7517,6 +7517,10 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, > intel_crtc_vblank_on(new_crtc_state); > > intel_encoders_enable(state, crtc); > + > + /* prevents spurious underruns */ > + if (IS_GEN(dev_priv, 2)) > + intel_wait_for_vblank(dev_priv, pipe); > } > > static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) From jose.souza at intel.com Thu Jun 25 01:04:15 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 01:04:15 +0000 Subject: [Intel-gfx] [PATCH 11/12] drm/i915: Fix g4x fbc watermark enable In-Reply-To: <20200429101034.8208-12-ville.syrjala@linux.intel.com> References: <20200429101034.8208-1-ville.syrjala@linux.intel.com> <20200429101034.8208-12-ville.syrjala@linux.intel.com> Message-ID: <599be76dd4f2aaa242f48abe809ec089e5354acc.camel@intel.com> On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > 'level' here means the highest level we can't use, so when checking > the fbc watermarks we need a -1 to get at the last enabled level. > > While at if refactor the code a bit to declutter > g4x_compute_pipe_wm(). > Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 33 +++++++++++++++++++++------------ > 1 file changed, 21 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 1e99b35f007e..1c92ebf64a34 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1344,6 +1344,23 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc, > } > } > > +static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state, > + int level) > +{ > + if (level < G4X_WM_LEVEL_SR) > + return false; > + > + if (level >= G4X_WM_LEVEL_SR && > + wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) > + return false; > + > + if (level >= G4X_WM_LEVEL_HPLL && > + wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL)) > + return false; > + > + return true; > +} > + > static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > @@ -1383,7 +1400,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > wm_state->wm.plane[plane_id] = raw->plane[plane_id]; > > level = G4X_WM_LEVEL_SR; > - > if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) > goto out; > > @@ -1395,7 +1411,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); > > level = G4X_WM_LEVEL_HPLL; > - > if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) > goto out; > > @@ -1418,17 +1433,11 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > /* > * Determine if the FBC watermark(s) can be used. IF > * this isn't the case we prefer to disable the FBC > - ( watermark(s) rather than disable the SR/HPLL > - * level(s) entirely. > + * watermark(s) rather than disable the SR/HPLL > + * level(s) entirely. 'level-1' is the highest valid > + * level here. > */ > - wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL; > - > - if (level >= G4X_WM_LEVEL_SR && > - wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) > - wm_state->fbc_en = false; > - else if (level >= G4X_WM_LEVEL_HPLL && > - wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL)) > - wm_state->fbc_en = false; > + wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1); > > return 0; > } From jose.souza at intel.com Thu Jun 25 01:04:52 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 01:04:52 +0000 Subject: [Intel-gfx] [PATCH 06/12] drm/i915/fbc: Don't clear busy_bits for origin==GTT In-Reply-To: <20200429101034.8208-7-ville.syrjala@linux.intel.com> References: <20200429101034.8208-1-ville.syrjala@linux.intel.com> <20200429101034.8208-7-ville.syrjala@linux.intel.com> Message-ID: <a1ebf9b91335ae9b33ed3b88847492292f597c3c.camel@intel.com> On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > The hardware host tracking won't nuke the entire cfb (unless the > entire fb is written through the gtt) so don't clear the busy_bits > for gtt tracking. > > Not that it really matters anymore since we've lost ORIGIN_GTT usage > everywhere. Maybe drop it then? But for now this change looks good. Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index 983224e07eaf..56eeafa645de 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -1107,11 +1107,19 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, > if (!HAS_FBC(dev_priv)) > return; > > + /* > + * GTT tracking does not nuke the entire cfb > + * so don't clear busy_bits set for some other > + * reason. > + */ > + if (origin == ORIGIN_GTT) > + return; > + > mutex_lock(&fbc->lock); > > fbc->busy_bits &= ~frontbuffer_bits; > > - if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) > + if (origin == ORIGIN_FLIP) > goto out; > > if (!fbc->busy_bits && fbc->crtc && From mhocko at kernel.org Thu Jun 25 07:57:25 2020 From: mhocko at kernel.org (Michal Hocko) Date: Thu, 25 Jun 2020 09:57:25 +0200 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200624191417.16735-1-chris@chris-wilson.co.uk> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> Message-ID: <20200625075725.GC1320@dhcp22.suse.cz> On Wed 24-06-20 20:14:17, Chris Wilson wrote: > A general rule of thumb is that shrinkers should be fast and effective. > They are called from direct reclaim at the most incovenient of times when > the caller is waiting for a page. If we attempt to reclaim a page being > pinned for active dma [pin_user_pages()], we will incur far greater > latency than a normal anonymous page mapped multiple times. Worse the > page may be in use indefinitely by the HW and unable to be reclaimed > in a timely manner. > > A side effect of the LRU shrinker not being dma aware is that we will > often attempt to perform direct reclaim on the persistent group of dma > pages while continuing to use the dma HW (an issue as the HW may already > be actively waiting for the next user request), and even attempt to > reclaim a partially allocated dma object in order to satisfy pinning > the next user page for that object. You are talking about direct reclaim but this path is shared with the background reclaim. This is a bit confusing. Maybe you just want to outline the latency in the reclaim which is more noticeable in the direct reclaim to the userspace. This would be good to be clarified. How much memory are we talking about here btw? > It is to be expected that such pages are made available for reclaim at > the end of the dma operation [unpin_user_pages()], and for truly > longterm pins to be proactively recovered via device specific shrinkers > [i.e. stop the HW, allow the pages to be returned to the system, and > then compete again for the memory]. Is the later implemented? Btw. overall intention of the patch is not really clear to me. Do I get it right that this is going to reduce latency of the reclaim for pages that are not reclaimable anyway because they are pinned? If yes do we have any numbers for that. It would be also good to explain why the bail out is implemented in try_to_unmap rather than shrink_shrink_page_list. > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Andrew Morton <akpm at linux-foundation.org> > Cc: Jan Kara <jack at suse.cz> > Cc: J?r?me Glisse <jglisse at redhat.com> > Cc: John Hubbard <jhubbard at nvidia.com> > Cc: Claudio Imbrenda <imbrenda at linux.ibm.com> > Cc: Jan Kara <jack at suse.cz> > Cc: Kirill A. Shutemov <kirill.shutemov at linux.intel.com> > Cc: Jason Gunthorpe <jgg at ziepe.ca> > --- > This seems perhaps a little devious and overzealous. Is there a more > appropriate TTU flag? Would there be a way to limit its effect to say > FOLL_LONGTERM? Doing the migration first would seem to be sensible if > we disable opportunistic migration for the duration of the pin. > --- > mm/rmap.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/mm/rmap.c b/mm/rmap.c > index 5fe2dedce1fc..374c6e65551b 100644 > --- a/mm/rmap.c > +++ b/mm/rmap.c > @@ -1393,6 +1393,22 @@ static bool try_to_unmap_one(struct page *page, struct vm_area_struct *vma, > is_zone_device_page(page) && !is_device_private_page(page)) > return true; > > + /* > + * Try and fail early to revoke a costly DMA pinned page. > + * > + * Reclaiming an active DMA page requires stopping the hardware > + * and flushing access. [Hardware that does support pagefaulting, > + * and so can quickly revoke DMA pages at any time, does not need > + * to pin the DMA page.] At worst, the page may be indefinitely in > + * use by the hardware. Even at best it will take far longer to > + * revoke the access via the mmu notifier, forcing that latency > + * onto our callers rather than the consumer of the HW. As we are > + * called during opportunistic direct reclaim, declare the > + * opportunity cost too high and ignore the page. > + */ > + if (page_maybe_dma_pinned(page)) > + return true; I do not understand why the page table walk needs to be done. The page is going to be pinned no matter how many page tables are mapping it right? > + > if (flags & TTU_SPLIT_HUGE_PMD) { > split_huge_pmd_address(vma, address, > flags & TTU_SPLIT_FREEZE, page); > -- > 2.20.1 -- Michal Hocko SUSE Labs From tzimmermann at suse.de Thu Jun 25 08:27:17 2020 From: tzimmermann at suse.de (Thomas Zimmermann) Date: Thu, 25 Jun 2020 10:27:17 +0200 Subject: [Intel-gfx] [PULL] drm-misc-fixes Message-ID: <20200625082717.GA14856@linux-uq9g> Hi Dave and Daniel, there's the PR for the current patches in drm-misc-fixes. Besides the fixes there's also a merge of v.5.8-rc1. Best regards Thomas drm-misc-fixes-2020-06-25: Short summary of fixes pull (less than what git shortlog provides): * In mcde, set up fbdev after device registration and removde the last access to dev->dev_private. Fixes an error message and a segmentation fault. * Set the connector type for LogicPT Type 28 and newhaven_nhd_43_480272ef_atxl panels. * In uvesafb, fix the handling of the noblank option. * Fix panel orientation for Asus T101HA and Acer S1003. * Fix DMA configuration for sun4i if IOMMU is present. * Fix regression in VT restoration. Unbreaks userspace (i.e., Xorg) VT handling. The following changes since commit b3a9e3b9622ae10064826dccb4f7a52bd88c7407: Linux 5.8-rc1 (2020-06-14 12:45:04 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-fixes-2020-06-25 for you to fetch changes up to dc5bdb68b5b369d5bc7d1de96fa64cc1737a6320: drm/fb-helper: Fix vt restore (2020-06-24 21:34:11 +0200) ---------------------------------------------------------------- Short summary of fixes pull (less than what git shortlog provides): * In mcde, set up fbdev after device registration and removde the last access to dev->dev_private. Fixes an error message and a segmentation fault. * Set the connector type for LogicPT Type 28 and newhaven_nhd_43_480272ef_atxl panels. * In uvesafb, fix the handling of the noblank option. * Fix panel orientation for Asus T101HA and Acer S1003. * Fix DMA configuration for sun4i if IOMMU is present. * Fix regression in VT restoration. Unbreaks userspace (i.e., Xorg) VT handling. ---------------------------------------------------------------- Adam Ford (1): drm/panel-simple: fix connector type for LogicPD Type28 Display Bartlomiej Zolnierkiewicz (1): video: fbdev: uvesafb: fix "noblank" option handling Daniel Vetter (1): drm/fb-helper: Fix vt restore Hans de Goede (2): drm: panel-orientation-quirks: Add quirk for Asus T101HA panel drm: panel-orientation-quirks: Use generic orientation-data for Acer S1003 Linus Walleij (2): drm: mcde: Fix display initialization problem drm: mcde: Fix forgotten user of drm->dev_private Maxime Ripard (1): drm/sun4i: mixer: Call of_dma_configure if there's an IOMMU Thomas Zimmermann (1): Merge v5.8-rc1 into drm-misc-fixes Tomi Valkeinen (1): drm/panel-simple: fix connector type for newhaven_nhd_43_480272ef_atxl Xiyu Yang (2): drm/ttm: Fix dma_fence refcnt leak in ttm_bo_vm_fault_reserved drm/ttm: Fix dma_fence refcnt leak when adding move fence drivers/gpu/drm/drm_fb_helper.c | 63 ++++++++++++++++++++------ drivers/gpu/drm/drm_panel_orientation_quirks.c | 14 +++--- drivers/gpu/drm/mcde/mcde_display.c | 2 +- drivers/gpu/drm/mcde/mcde_drv.c | 3 +- drivers/gpu/drm/panel/panel-simple.c | 2 + drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 ++++++ drivers/gpu/drm/ttm/ttm_bo.c | 4 +- drivers/gpu/drm/ttm/ttm_bo_vm.c | 2 + drivers/video/fbdev/core/fbcon.c | 3 +- drivers/video/fbdev/uvesafb.c | 2 +- include/uapi/linux/fb.h | 1 + 11 files changed, 83 insertions(+), 26 deletions(-) From maarten.lankhorst at linux.intel.com Thu Jun 25 08:36:28 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Thu, 25 Jun 2020 10:36:28 +0200 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915: Send hotplug event if edid had changed In-Reply-To: <20200623185756.19502-4-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> <20200623185756.19502-4-kunal1.joshi@intel.com> Message-ID: <61952a12-bd15-92ce-fd81-88a35ed88acb@linux.intel.com> Op 23-06-2020 om 20:57 schreef Kunal Joshi: > From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > Added epoch counter checking to intel_encoder_hotplug > in order to be able process all the connector changes, > besides connection status. Also now any change in connector > would result in epoch counter change, so no multiple checks > are needed. > > v2: Renamed change counter to epoch counter. Fixed type name. > > v3: Fixed rebase conflict > > v4: Remove duplicate drm_edid_equal checks from hdmi and dp, > lets use only once edid property is getting updated and > increment epoch counter from there. > Also lets now call drm_connector_update_edid_property > right after we get edid always to make sure there is a > unified way to handle edid change, without having to > change tons of source code as currently > drm_connector_update_edid_property is called only in > certain cases like reprobing and not right after edid is > actually updated. > > v5: Fixed const modifiers, removed blank line > > v6: Removed drm specific part from this patch, leaving only > i915 specific changes here. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > --- Much better! Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> for whole series > drivers/gpu/drm/i915/display/intel_hotplug.c | 26 +++++++++++--------- > 1 file changed, 15 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c > index 2e94c1413c02..393813494523 100644 > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c > @@ -283,6 +283,8 @@ intel_encoder_hotplug(struct intel_encoder *encoder, > { > struct drm_device *dev = connector->base.dev; > enum drm_connector_status old_status; > + u64 old_epoch_counter; > + bool ret = false; > > drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex)); > old_status = connector->base.status; > @@ -290,17 +292,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder, > connector->base.status = > drm_helper_probe_detect(&connector->base, NULL, false); > > - if (old_status == connector->base.status) > - return INTEL_HOTPLUG_UNCHANGED; > - > - drm_dbg_kms(&to_i915(dev)->drm, > - "[CONNECTOR:%d:%s] status updated from %s to %s\n", > - connector->base.base.id, > - connector->base.name, > - drm_get_connector_status_name(old_status), > - drm_get_connector_status_name(connector->base.status)); > - > - return INTEL_HOTPLUG_CHANGED; > + if (old_epoch_counter != connector->base.epoch_counter) > + ret = true; > + > + if(ret) { > + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s(epoch counter %llu)\n", > + connector->base.base.id, > + connector->base.name, > + drm_get_connector_status_name(old_status), > + drm_get_connector_status_name(connector->base.status), > + connector->base.epoch_counter); > + return INTEL_HOTPLUG_CHANGED; > + } > + return INTEL_HOTPLUG_UNCHANGED; > } > > static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder) From melissa.srw at gmail.com Thu Jun 25 10:13:46 2020 From: melissa.srw at gmail.com (Melissa Wen) Date: Thu, 25 Jun 2020 07:13:46 -0300 Subject: [Intel-gfx] [RFC PATCH i-g-t] lib/igt_fb: remove extra parameters from igt_put_caito_ctx Message-ID: <20200625101346.xxm3hjepjj4gsedn@smtp.gmail.com> The function igt_put_caito_ctx has three parameters, but it looks like only one of them is actually used. If I'm not wrong about the unnecessary parameters, removing them makes the function more readable and simpler to understand. Since the function is used in many tests, this change is a little noisy. Signed-off-by: Melissa Wen <melissa.srw at gmail.com> --- lib/igt_fb.c | 18 ++++++++---------- lib/igt_fb.h | 2 +- tests/amdgpu/amd_color.c | 4 ++-- tests/i915/i915_pm_dc.c | 2 +- tests/kms_atomic.c | 6 +++--- tests/kms_available_modes_crc.c | 4 ++-- tests/kms_ccs.c | 2 +- tests/kms_color_helper.c | 4 ++-- tests/kms_concurrent.c | 2 +- tests/kms_crtc_background_color.c | 2 +- tests/kms_cursor_crc.c | 22 ++++++++++------------ tests/kms_cursor_edge_walk.c | 2 +- tests/kms_flip.c | 2 +- tests/kms_hdr.c | 2 +- tests/kms_mmap_write_crc.c | 4 ++-- tests/kms_plane.c | 8 ++++---- tests/kms_plane_alpha_blend.c | 10 +++++----- tests/kms_plane_cursor.c | 4 ++-- tests/kms_plane_lowres.c | 2 +- tests/kms_plane_multiple.c | 2 +- tests/kms_psr.c | 2 +- tests/kms_psr2_su.c | 4 ++-- tests/kms_rotation_crc.c | 2 +- tests/kms_setmode.c | 2 +- tests/kms_vrr.c | 2 +- tests/testdisplay.c | 4 ++-- 26 files changed, 58 insertions(+), 62 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 5ed586e7..fd33907b 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -1697,7 +1697,7 @@ unsigned int igt_create_color_fb(int fd, int width, int height, cr = igt_get_cairo_ctx(fd, fb); igt_paint_color(cr, 0, 0, width, height, r, g, b); - igt_put_cairo_ctx(fd, fb, cr); + igt_put_cairo_ctx(cr); return fb_id; } @@ -1734,7 +1734,7 @@ unsigned int igt_create_pattern_fb(int fd, int width, int height, cr = igt_get_cairo_ctx(fd, fb); igt_paint_test_pattern(cr, width, height); - igt_put_cairo_ctx(fd, fb, cr); + igt_put_cairo_ctx(cr); return fb_id; } @@ -1777,7 +1777,7 @@ unsigned int igt_create_color_pattern_fb(int fd, int width, int height, cr = igt_get_cairo_ctx(fd, fb); igt_paint_color(cr, 0, 0, width, height, r, g, b); igt_paint_test_pattern(cr, width, height); - igt_put_cairo_ctx(fd, fb, cr); + igt_put_cairo_ctx(cr); return fb_id; } @@ -1820,7 +1820,7 @@ unsigned int igt_create_image_fb(int fd, int width, int height, cr = igt_get_cairo_ctx(fd, fb); igt_paint_image(cr, filename, 0, 0, width, height); - igt_put_cairo_ctx(fd, fb, cr); + igt_put_cairo_ctx(cr); return fb_id; } @@ -1920,7 +1920,7 @@ unsigned int igt_create_stereo_fb(int drm_fd, drmModeModeInfo *mode, layout.right.x, layout.right.y, layout.right.width, layout.right.height); - igt_put_cairo_ctx(drm_fd, &fb, cr); + igt_put_cairo_ctx(cr); return fb_id; } @@ -3578,15 +3578,13 @@ cairo_t *igt_get_cairo_ctx(int fd, struct igt_fb *fb) /** * igt_put_cairo_ctx: - * @fd: open i915 drm file descriptor - * @fb: pointer to an #igt_fb structure * @cr: the cairo context returned by igt_get_cairo_ctx. * * This releases the cairo surface @cr returned by igt_get_cairo_ctx() - * for @fb, and writes the changes out to the framebuffer if cairo doesn't + * for fb, and writes the changes out to the framebuffer if cairo doesn't * have native support for the format. */ -void igt_put_cairo_ctx(int fd, struct igt_fb *fb, cairo_t *cr) +void igt_put_cairo_ctx(cairo_t *cr) { cairo_status_t ret = cairo_status(cr); igt_assert_f(ret == CAIRO_STATUS_SUCCESS, "Cairo failed to draw with %s\n", cairo_status_to_string(ret)); @@ -3657,7 +3655,7 @@ unsigned int igt_fb_convert_with_stride(struct igt_fb *dst, struct igt_fb *src, cr = igt_get_cairo_ctx(dst->fd, dst); cairo_set_source_surface(cr, surf, 0, 0); cairo_paint(cr); - igt_put_cairo_ctx(dst->fd, dst, cr); + igt_put_cairo_ctx(cr); cairo_surface_destroy(surf); diff --git a/lib/igt_fb.h b/lib/igt_fb.h index 587f7a44..5ec906b7 100644 --- a/lib/igt_fb.h +++ b/lib/igt_fb.h @@ -178,7 +178,7 @@ int igt_fb_ccs_to_main_plane(const struct igt_fb *fb, int ccs_plane); cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb); cairo_surface_t *igt_cairo_image_surface_create_from_png(const char *filename); cairo_t *igt_get_cairo_ctx(int fd, struct igt_fb *fb); -void igt_put_cairo_ctx(int fd, struct igt_fb *fb, cairo_t *cr); +void igt_put_cairo_ctx(cairo_t *cr); void igt_paint_color(cairo_t *cr, int x, int y, int w, int h, double r, double g, double b); void igt_paint_color_alpha(cairo_t *cr, int x, int y, int w, int h, diff --git a/tests/amdgpu/amd_color.c b/tests/amdgpu/amd_color.c index 0bbee43d..6d313bae 100644 --- a/tests/amdgpu/amd_color.c +++ b/tests/amdgpu/amd_color.c @@ -134,7 +134,7 @@ static void draw_color(igt_fb_t *fb, double r, double g, double b) cairo_set_operator(cr, CAIRO_OPERATOR_SOURCE); igt_paint_color(cr, 0, 0, fb->width, fb->height, r, g, b); - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } /* Generates the gamma test pattern. */ @@ -148,7 +148,7 @@ static void draw_gamma_test(igt_fb_t *fb) igt_paint_color_gradient(cr, 0, gh * 2, fb->width, gh, 0, 1, 0); igt_paint_color_gradient(cr, 0, gh * 3, fb->width, gh, 0, 0, 1); - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } /* Sets the degamma LUT. */ diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c index 3a302729..84bcf568 100644 --- a/tests/i915/i915_pm_dc.c +++ b/tests/i915/i915_pm_dc.c @@ -131,7 +131,7 @@ static void paint_rectangles(data_t *data, colors[i - 1].r, colors[i - 1].g, colors[i - 1].b); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } static void setup_primary(data_t *data) diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c index f672f554..fa6190c9 100644 --- a/tests/kms_atomic.c +++ b/tests/kms_atomic.c @@ -309,7 +309,7 @@ plane_primary_overlay_mutable_zpos(igt_pipe_t *pipe, igt_output_t *output, w_overlay / 2, h_overlay / 2, 0.0, 0.0, 0.0, 0.0); cairo_set_operator(cr, CAIRO_OPERATOR_OVER); - igt_put_cairo_ctx(pipe->display->drm_fd, &fb_overlay, cr); + igt_put_cairo_ctx(cr); igt_plane_set_fb(primary, &fb_primary); igt_plane_set_fb(overlay, &fb_overlay); @@ -343,7 +343,7 @@ plane_primary_overlay_mutable_zpos(igt_pipe_t *pipe, igt_output_t *output, w_overlay, h_overlay, 0.0, 0.0, 0.0, 0.5); cairo_set_operator(cr, CAIRO_OPERATOR_OVER); - igt_put_cairo_ctx(pipe->display->drm_fd, &fb_primary, cr); + igt_put_cairo_ctx(cr); igt_info("Committing with a hole in the primary through "\ "which the underlay should be seen\n"); @@ -398,7 +398,7 @@ plane_immutable_zpos(igt_display_t *display, igt_pipe_t *pipe, igt_assert(cairo_status(cr) == 0); igt_paint_color(cr, 0, 0, w_lower, h_lower, 0.0, 0.0, 1.0); igt_paint_color(cr, w_upper / 2, h_upper / 2, w_upper, h_upper, 1.0, 1.0, 0.0); - igt_put_cairo_ctx(display->drm_fd, &fb_ref, cr); + igt_put_cairo_ctx(cr); igt_plane_set_fb(primary, &fb_ref); igt_display_commit2(display, COMMIT_ATOMIC); diff --git a/tests/kms_available_modes_crc.c b/tests/kms_available_modes_crc.c index ed43d1fb..23d035f7 100644 --- a/tests/kms_available_modes_crc.c +++ b/tests/kms_available_modes_crc.c @@ -96,7 +96,7 @@ static void generate_comparison_crc_list(data_t *data, igt_output_t *output) 0.0, 0.0, 0.0); igt_paint_color(cr, 0, 0, w, h, 1.0, 1.0, 1.0); igt_assert(cairo_status(cr) == 0); - igt_put_cairo_ctx(data->gfx_fd, &data->primary_fb, cr); + igt_put_cairo_ctx(cr); primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, &data->primary_fb); @@ -108,7 +108,7 @@ static void generate_comparison_crc_list(data_t *data, igt_output_t *output) cr = igt_get_cairo_ctx(data->gfx_fd, &data->primary_fb); igt_paint_color(cr, 0, 0, mode->hdisplay, mode->vdisplay, 1.0, 1.0, 1.0); - igt_put_cairo_ctx(data->gfx_fd, &data->primary_fb, cr); + igt_put_cairo_ctx(cr); igt_plane_set_fb(primary, &data->primary_fb); igt_display_commit2(&data->display, data->commit); diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c index bc34aec5..b60e4908 100644 --- a/tests/kms_ccs.c +++ b/tests/kms_ccs.c @@ -246,7 +246,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb, cr = igt_get_cairo_ctx(data->drm_fd, fb); igt_paint_color(cr, 0, 0, width, height, colors[c].r, colors[c].g, colors[c].b); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } ret = drmIoctl(data->drm_fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, &f); diff --git a/tests/kms_color_helper.c b/tests/kms_color_helper.c index 9cb740f2..2605146a 100644 --- a/tests/kms_color_helper.c +++ b/tests/kms_color_helper.c @@ -57,7 +57,7 @@ void paint_gradient_rectangles(data_t *data, colors[i-1].g, colors[i-1].b); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } void paint_rectangles(data_t *data, @@ -79,7 +79,7 @@ void paint_rectangles(data_t *data, igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay, colors[i-1].r, colors[i-1].g, colors[i-1].b); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } gamma_lut_t *alloc_lut(int lut_size) diff --git a/tests/kms_concurrent.c b/tests/kms_concurrent.c index 89016563..9a4dab24 100644 --- a/tests/kms_concurrent.c +++ b/tests/kms_concurrent.c @@ -126,7 +126,7 @@ create_fb_for_mode_position(data_t *data, drmModeModeInfo *mode, rect_w[i], rect_h[i], 0.0, 0.0, 0.0); } - igt_put_cairo_ctx(data->drm_fd, &data->fb[primary->index], cr); + igt_put_cairo_ctx(cr); } static void diff --git a/tests/kms_crtc_background_color.c b/tests/kms_crtc_background_color.c index aca7ac3e..b4141b0d 100644 --- a/tests/kms_crtc_background_color.c +++ b/tests/kms_crtc_background_color.c @@ -69,7 +69,7 @@ paint_background(data_t *data, struct igt_fb *fb, drmModeModeInfo *mode, b = (double) ((background & 0xFF0000) >> 16) / 255.0; igt_paint_color_alpha(cr, 0, 0, w, h, r, g, b, alpha); - igt_put_cairo_ctx(data->gfx_fd, &data->fb, cr); + igt_put_cairo_ctx(cr); } static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe, diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index f105e295..7e6b24cc 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -167,8 +167,7 @@ static void restore_image(data_t *data) cairo_set_source_surface(cr, data->surface, 0, 0); cairo_rectangle(cr, 0, 0, data->screenw, data->screenh); cairo_fill(cr); - igt_put_cairo_ctx(data->drm_fd, - &data->primary_fb[FRONTBUFFER], cr); + igt_put_cairo_ctx(cr); } igt_dirty_fb(data->drm_fd, &data->primary_fb[FRONTBUFFER]); } @@ -235,7 +234,7 @@ static void do_single_test(data_t *data, int x, int y) /* Now render the same in software and collect crc */ cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER]); draw_cursor(cr, x, y, data->curw, data->curh, 1.0); - igt_put_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER], cr); + igt_put_cairo_ctx(cr); igt_display_commit(display); igt_dirty_fb(data->drm_fd, &data->primary_fb[FRONTBUFFER]); /* Extra vblank wait is because nonblocking cursor ioctl */ @@ -451,8 +450,7 @@ static void prepare_crtc(data_t *data, igt_output_t *output, &data->primary_fb[RESTOREBUFFER]); cairo_set_operator(cr, CAIRO_OPERATOR_SOURCE); igt_paint_test_pattern(cr, data->screenw, data->screenh); - igt_put_cairo_ctx(data->drm_fd, - &data->primary_fb[RESTOREBUFFER], cr); + igt_put_cairo_ctx(cr); data->drmibo[FRONTBUFFER] = gem_handle_to_libdrm_bo(data->bufmgr, data->drm_fd, @@ -493,7 +491,7 @@ static void test_cursor_alpha(data_t *data, double a) igt_assert(fb_id); cr = igt_get_cairo_ctx(data->drm_fd, &data->fb); igt_paint_color_alpha(cr, 0, 0, curw, curh, 1.0, 1.0, 1.0, a); - igt_put_cairo_ctx(data->drm_fd, &data->fb, cr); + igt_put_cairo_ctx(cr); /*Hardware Test*/ cursor_enable(data); @@ -506,7 +504,7 @@ static void test_cursor_alpha(data_t *data, double a) /*Software Test*/ cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER]); igt_paint_color_alpha(cr, 0, 0, curw, curh, 1.0, 1.0, 1.0, a); - igt_put_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER], cr); + igt_put_cairo_ctx(cr); igt_display_commit(display); igt_wait_for_vblank(data->drm_fd, data->pipe); @@ -517,7 +515,7 @@ static void test_cursor_alpha(data_t *data, double a) cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER]); igt_paint_color(cr, 0, 0, data->screenw, data->screenh, 0.0, 0.0, 0.0); - igt_put_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER], cr); + igt_put_cairo_ctx(cr); } static void test_cursor_transparent(data_t *data) @@ -559,7 +557,7 @@ static void create_cursor_fb(data_t *data, int cur_w, int cur_h) cr = igt_get_cairo_ctx(data->drm_fd, &data->fb); draw_cursor(cr, 0, 0, cur_w, cur_h, 1.0); - igt_put_cairo_ctx(data->drm_fd, &data->fb, cr); + igt_put_cairo_ctx(cr); } static bool has_nonsquare_cursors(data_t *data) @@ -605,7 +603,7 @@ static void test_cursor_size(data_t *data) /* Use a solid white rectangle as the cursor */ cr = igt_get_cairo_ctx(data->drm_fd, &data->fb); igt_paint_color_alpha(cr, 0, 0, cursor_max_size, cursor_max_size, 1.0, 1.0, 1.0, 1.0); - igt_put_cairo_ctx(data->drm_fd, &data->fb, cr); + igt_put_cairo_ctx(cr); /* Hardware test loop */ cursor_enable(data); @@ -625,7 +623,7 @@ static void test_cursor_size(data_t *data) /* Now render the same in software and collect crc */ cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER]); igt_paint_color_alpha(cr, 0, 0, size, size, 1.0, 1.0, 1.0, 1.0); - igt_put_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER], cr); + igt_put_cairo_ctx(cr); igt_display_commit(display); igt_wait_for_vblank(data->drm_fd, data->pipe); @@ -634,7 +632,7 @@ static void test_cursor_size(data_t *data) cr = igt_get_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER]); igt_paint_color(cr, 0, 0, data->screenw, data->screenh, 0.0, 0.0, 0.0); - igt_put_cairo_ctx(data->drm_fd, &data->primary_fb[FRONTBUFFER], cr); + igt_put_cairo_ctx(cr); igt_assert_crc_equal(&crc[i], &ref_crc); } } diff --git a/tests/kms_cursor_edge_walk.c b/tests/kms_cursor_edge_walk.c index 6feb32a8..96a78792 100644 --- a/tests/kms_cursor_edge_walk.c +++ b/tests/kms_cursor_edge_walk.c @@ -78,7 +78,7 @@ static void create_cursor_fb(data_t *data, int cur_w, int cur_h) else igt_paint_color_alpha(cr, 0, 0, data->fb.width, data->fb.height, 0.0, 0.0, 0.0, 0.0); - igt_put_cairo_ctx(data->drm_fd, &data->fb, cr); + igt_put_cairo_ctx(cr); } static void cursor_move(data_t *data, int x, int y, int i) diff --git a/tests/kms_flip.c b/tests/kms_flip.c index b7b42f85..adf72740 100755 --- a/tests/kms_flip.c +++ b/tests/kms_flip.c @@ -973,7 +973,7 @@ static void paint_flip_mode(struct igt_fb *fb, bool odd_frame) cairo_set_source_rgb(cr, 1, 1, 1); cairo_fill(cr); - igt_put_cairo_ctx(drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } static bool fb_is_bound(struct test_output *o, int fb) diff --git a/tests/kms_hdr.c b/tests/kms_hdr.c index 71372556..0574d5ff 100644 --- a/tests/kms_hdr.c +++ b/tests/kms_hdr.c @@ -141,7 +141,7 @@ static void draw_hdr_pattern(igt_fb_t *fb) igt_paint_color(cr, 0, 0, fb->width, fb->height, 1.0, 1.0, 1.0); igt_paint_test_pattern(cr, fb->width, fb->height); - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } /* Prepare test data. */ diff --git a/tests/kms_mmap_write_crc.c b/tests/kms_mmap_write_crc.c index 56e0c4d7..46013808 100644 --- a/tests/kms_mmap_write_crc.c +++ b/tests/kms_mmap_write_crc.c @@ -92,7 +92,7 @@ static void test(data_t *data) cr = igt_get_cairo_ctx(data->drm_fd, fb); igt_paint_test_pattern(cr, fb->width, fb->height); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); /* flip to it to make it UC/WC and fully flushed */ igt_plane_set_fb(data->primary, fb); @@ -135,7 +135,7 @@ static void test(data_t *data) * fully flushed */ cr = igt_get_cairo_ctx(data->drm_fd, fb); igt_paint_test_pattern(cr, fb->width, fb->height); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); igt_plane_set_fb(data->primary, fb); igt_display_commit(display); diff --git a/tests/kms_plane.c b/tests/kms_plane.c index c6ead813..e75c045b 100644 --- a/tests/kms_plane.c +++ b/tests/kms_plane.c @@ -149,7 +149,7 @@ create_fb_for_mode__position(data_t *data, drmModeModeInfo *mode, igt_paint_color(cr, 0, 0, mode->hdisplay, mode->vdisplay, 0.0, 1.0, 0.0); igt_paint_color(cr, rect_x, rect_y, rect_w, rect_h, 0.0, 0.0, 0.0); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } enum { @@ -284,7 +284,7 @@ create_fb_for_mode__panning(data_t *data, drmModeModeInfo *mode, mode->hdisplay, mode->vdisplay, 0.0, 0.0, 1.0); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } enum { @@ -460,7 +460,7 @@ static void prepare_format_color(data_t *data, enum pipe pipe, igt_paint_color(cr, 0, 0, width, height, c->red, c->green, c->blue); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } else { igt_create_fb_with_bo_size(data->drm_fd, width + data->crop * 2, @@ -485,7 +485,7 @@ static void prepare_format_color(data_t *data, enum pipe pipe, width, height, c->red, c->green, c->blue); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } igt_plane_set_fb(plane, fb); diff --git a/tests/kms_plane_alpha_blend.c b/tests/kms_plane_alpha_blend.c index ca7a6fa9..dd162546 100644 --- a/tests/kms_plane_alpha_blend.c +++ b/tests/kms_plane_alpha_blend.c @@ -60,7 +60,7 @@ static void draw_gradient(struct igt_fb *fb, int w, int h, double a) __draw_gradient(fb, w, h, a, cr); - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } static void draw_gradient_coverage(struct igt_fb *fb, int w, int h, uint8_t a) @@ -76,7 +76,7 @@ static void draw_gradient_coverage(struct igt_fb *fb, int w, int h, uint8_t a) for (i = 0; i < w; i++) data[i * 4 + 3] = a; - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } static void draw_squares(struct igt_fb *fb, int w, int h, double a) @@ -90,7 +90,7 @@ static void draw_squares(struct igt_fb *fb, int w, int h, double a) igt_paint_color_alpha(cr, w / 2, h / 2, w / 4, h / 2, 1., 1., 1., a); igt_paint_color_alpha(cr, 3 * w / 4, h / 2, w / 4, h / 2, 0., 0., 0., a); - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } static void draw_squares_coverage(struct igt_fb *fb, int w, int h, uint8_t as) @@ -120,7 +120,7 @@ static void draw_squares_coverage(struct igt_fb *fb, int w, int h, uint8_t as) data[j * stride + i] = a; } - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } static void reset_alpha(igt_display_t *display, enum pipe pipe) @@ -200,7 +200,7 @@ static void prepare_crtc(data_t *data, igt_output_t *output, enum pipe pipe) cr = igt_get_cairo_ctx(data->gfx_fd, &data->argb_fb_0); cairo_set_operator(cr, CAIRO_OPERATOR_SOURCE); igt_paint_color_alpha(cr, 0, 0, w, h, 0., 0., 0., 0.0); - igt_put_cairo_ctx(data->gfx_fd, &data->argb_fb_0, cr); + igt_put_cairo_ctx(cr); igt_create_fb(data->gfx_fd, w, h, DRM_FORMAT_ARGB8888, LOCAL_DRM_FORMAT_MOD_NONE, diff --git a/tests/kms_plane_cursor.c b/tests/kms_plane_cursor.c index adcdf5e8..f7d50484 100644 --- a/tests/kms_plane_cursor.c +++ b/tests/kms_plane_cursor.c @@ -102,7 +102,7 @@ static void draw_color(igt_fb_t *fb, double r, double g, double b) cairo_set_operator(cr, CAIRO_OPERATOR_SOURCE); igt_paint_color(cr, 0, 0, fb->width, fb->height, r, g, b); - igt_put_cairo_ctx(fb->fd, fb, cr); + igt_put_cairo_ctx(cr); } /* @@ -129,7 +129,7 @@ static void test_cursor_pos(data_t *data, igt_fb_t *pfb, igt_fb_t *ofb, igt_paint_color(cr, or->x, or->y, or->w, or->h, 0.5, 0.5, 0.5); igt_paint_color(cr, x, y, cw, ch, 1.0, 0.0, 1.0); - igt_put_cairo_ctx(pfb->fd, pfb, cr); + igt_put_cairo_ctx(cr); igt_plane_set_fb(data->overlay, NULL); igt_plane_set_fb(data->cursor, NULL); diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c index 012b25e3..94b18df6 100644 --- a/tests/kms_plane_lowres.c +++ b/tests/kms_plane_lowres.c @@ -158,7 +158,7 @@ static void create_ref_fb(data_t *data, uint64_t modifier, cr = igt_get_cairo_ctx(data->drm_fd, fb); blit(data, cr, &data->fb_primary, 0, 0); blit(data, cr, &data->fb_plane[0], data->x, data->y); - igt_put_cairo_ctx(data->drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } static unsigned diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c index 6cf060b3..29b6397b 100644 --- a/tests/kms_plane_multiple.c +++ b/tests/kms_plane_multiple.c @@ -159,7 +159,7 @@ create_fb_for_mode_position(data_t *data, igt_output_t *output, drmModeModeInfo rect_w[i], rect_h[i], 0.0, 0.0, 0.0); } - igt_put_cairo_ctx(data->drm_fd, &data->fb[primary->index], cr); + igt_put_cairo_ctx(cr); } diff --git a/tests/kms_psr.c b/tests/kms_psr.c index f40902fb..49ea446a 100644 --- a/tests/kms_psr.c +++ b/tests/kms_psr.c @@ -88,7 +88,7 @@ static void create_cursor_fb(data_t *data) cr = igt_get_cairo_ctx(data->drm_fd, &data->fb_white); igt_paint_color_alpha(cr, 0, 0, 64, 64, 1.0, 1.0, 1.0, 1.0); - igt_put_cairo_ctx(data->drm_fd, &data->fb_white, cr); + igt_put_cairo_ctx(cr); } static void setup_output(data_t *data) diff --git a/tests/kms_psr2_su.c b/tests/kms_psr2_su.c index 0ee02fc8..d549d9a3 100644 --- a/tests/kms_psr2_su.c +++ b/tests/kms_psr2_su.c @@ -132,7 +132,7 @@ static void prepare(data_t *data) /* paint a white square */ igt_paint_color_alpha(cr, 0, 0, SQUARE_SIZE, SQUARE_SIZE, 1.0, 1.0, 1.0, 1.0); - igt_put_cairo_ctx(data->drm_fd, &data->fb[1], cr); + igt_put_cairo_ctx(cr); } else if (data->op == FRONTBUFFER) { data->cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[0]); } @@ -226,7 +226,7 @@ static void cleanup(data_t *data) if (data->op == PAGE_FLIP) igt_remove_fb(data->drm_fd, &data->fb[1]); else if (data->op == FRONTBUFFER) - igt_put_cairo_ctx(data->drm_fd, &data->fb[0], data->cr); + igt_put_cairo_ctx(data->cr); igt_remove_fb(data->drm_fd, &data->fb[0]); } diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c index 164eade8..ffcc2cc2 100644 --- a/tests/kms_rotation_crc.c +++ b/tests/kms_rotation_crc.c @@ -148,7 +148,7 @@ paint_squares(data_t *data, igt_rotation_t rotation, igt_paint_color(cr, 0, h / 2, w / 2, h / 2, RGB_COLOR(bl)); igt_paint_color(cr, w / 2, h / 2, w / 2, h / 2, RGB_COLOR(br)); - igt_put_cairo_ctx(data->gfx_fd, fb, cr); + igt_put_cairo_ctx(cr); } static void remove_fbs(data_t *data) diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c index 802a9c3d..92f3ead2 100644 --- a/tests/kms_setmode.c +++ b/tests/kms_setmode.c @@ -161,7 +161,7 @@ static int paint_fb(struct igt_fb *fb, const char *test_name, crtc_str[i]); } - igt_put_cairo_ctx(drm_fd, fb, cr); + igt_put_cairo_ctx(cr); return 0; } diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c index 73115fef..559ef203 100644 --- a/tests/kms_vrr.c +++ b/tests/kms_vrr.c @@ -186,7 +186,7 @@ static void prepare_test(data_t *data, igt_output_t *output, enum pipe pipe) igt_paint_color(cr, 0, 0, mode.hdisplay / 10, mode.vdisplay / 10, 1.00, 0.00, 0.00); - igt_put_cairo_ctx(data->drm_fd, &data->fb0, cr); + igt_put_cairo_ctx(cr); /* Take care of any required modesetting before the test begins. */ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); diff --git a/tests/testdisplay.c b/tests/testdisplay.c index 5e2c4598..ef033dc6 100644 --- a/tests/testdisplay.c +++ b/tests/testdisplay.c @@ -232,7 +232,7 @@ paint_color_key(struct igt_fb *fb_info) cairo_set_source_rgb(cr, .8, .8, .8); cairo_fill(cr); - igt_put_cairo_ctx(drm_fd, fb_info, cr); + igt_put_cairo_ctx(cr); } static void paint_image(cairo_t *cr, const char *file) @@ -317,7 +317,7 @@ static void paint_output_info(struct connector *c, struct igt_fb *fb) if (qr_code) paint_image(cr, "pass.png"); - igt_put_cairo_ctx(drm_fd, fb, cr); + igt_put_cairo_ctx(cr); } static void sighandler(int signo) -- 2.27.0 From stanislav.lisovskiy at intel.com Thu Jun 25 10:46:24 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Thu, 25 Jun 2020 13:46:24 +0300 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915: Send hotplug event if edid had changed In-Reply-To: <61952a12-bd15-92ce-fd81-88a35ed88acb@linux.intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> <20200623185756.19502-4-kunal1.joshi@intel.com> <61952a12-bd15-92ce-fd81-88a35ed88acb@linux.intel.com> Message-ID: <20200625104624.GA29687@intel.com> On Thu, Jun 25, 2020 at 10:36:28AM +0200, Maarten Lankhorst wrote: > Op 23-06-2020 om 20:57 schreef Kunal Joshi: > > From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > Added epoch counter checking to intel_encoder_hotplug > > in order to be able process all the connector changes, > > besides connection status. Also now any change in connector > > would result in epoch counter change, so no multiple checks > > are needed. > > > > v2: Renamed change counter to epoch counter. Fixed type name. > > > > v3: Fixed rebase conflict > > > > v4: Remove duplicate drm_edid_equal checks from hdmi and dp, > > lets use only once edid property is getting updated and > > increment epoch counter from there. > > Also lets now call drm_connector_update_edid_property > > right after we get edid always to make sure there is a > > unified way to handle edid change, without having to > > change tons of source code as currently > > drm_connector_update_edid_property is called only in > > certain cases like reprobing and not right after edid is > > actually updated. > > > > v5: Fixed const modifiers, removed blank line > > > > v6: Removed drm specific part from this patch, leaving only > > i915 specific changes here. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > --- > > Much better! > > Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > > for whole series I think it had been for year in that state already :) At some point I was just distracted by some other things. Stan > > > drivers/gpu/drm/i915/display/intel_hotplug.c | 26 +++++++++++--------- > > 1 file changed, 15 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c > > index 2e94c1413c02..393813494523 100644 > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c > > @@ -283,6 +283,8 @@ intel_encoder_hotplug(struct intel_encoder *encoder, > > { > > struct drm_device *dev = connector->base.dev; > > enum drm_connector_status old_status; > > + u64 old_epoch_counter; > > + bool ret = false; > > > > drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex)); > > old_status = connector->base.status; > > @@ -290,17 +292,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder, > > connector->base.status = > > drm_helper_probe_detect(&connector->base, NULL, false); > > > > - if (old_status == connector->base.status) > > - return INTEL_HOTPLUG_UNCHANGED; > > - > > - drm_dbg_kms(&to_i915(dev)->drm, > > - "[CONNECTOR:%d:%s] status updated from %s to %s\n", > > - connector->base.base.id, > > - connector->base.name, > > - drm_get_connector_status_name(old_status), > > - drm_get_connector_status_name(connector->base.status)); > > - > > - return INTEL_HOTPLUG_CHANGED; > > + if (old_epoch_counter != connector->base.epoch_counter) > > + ret = true; > > + > > + if(ret) { > > + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s(epoch counter %llu)\n", > > + connector->base.base.id, > > + connector->base.name, > > + drm_get_connector_status_name(old_status), > > + drm_get_connector_status_name(connector->base.status), > > + connector->base.epoch_counter); > > + return INTEL_HOTPLUG_CHANGED; > > + } > > + return INTEL_HOTPLUG_UNCHANGED; > > } > > > > static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder) > > From chris at chris-wilson.co.uk Thu Jun 25 11:00:47 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 12:00:47 +0100 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200625075725.GC1320@dhcp22.suse.cz> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200625075725.GC1320@dhcp22.suse.cz> Message-ID: <159308284703.4527.16058577374955415124@build.alporthouse.com> Quoting Michal Hocko (2020-06-25 08:57:25) > On Wed 24-06-20 20:14:17, Chris Wilson wrote: > > A general rule of thumb is that shrinkers should be fast and effective. > > They are called from direct reclaim at the most incovenient of times when > > the caller is waiting for a page. If we attempt to reclaim a page being > > pinned for active dma [pin_user_pages()], we will incur far greater > > latency than a normal anonymous page mapped multiple times. Worse the > > page may be in use indefinitely by the HW and unable to be reclaimed > > in a timely manner. > > > > A side effect of the LRU shrinker not being dma aware is that we will > > often attempt to perform direct reclaim on the persistent group of dma > > pages while continuing to use the dma HW (an issue as the HW may already > > be actively waiting for the next user request), and even attempt to > > reclaim a partially allocated dma object in order to satisfy pinning > > the next user page for that object. > > You are talking about direct reclaim but this path is shared with the > background reclaim. This is a bit confusing. Maybe you just want to > outline the latency in the reclaim which is more noticeable in the > direct reclaim to the userspace. This would be good to be clarified. > > How much memory are we talking about here btw? It depends. In theory, it is used sparingly. But it is under userspace control, exposed via Vulkan, OpenGL, OpenCL, media and even old XShm. If all goes to plan the application memory is only pinned for as long as the HW is using it, but that is an indefinite period of time and an indefinite amount of memory. There are provisions in place to impose upper limits on how long an operation can last on the HW, and the mmu-notifier is there to ensure we do unpin the memory on demand. However cancelling a HW operation (which will result in data loss and often process termination due to an unfortunate sequence of events when userspace fails to recover) for a try_to_unmap on behalf of the LRU shrinker is not a good choice. > > It is to be expected that such pages are made available for reclaim at > > the end of the dma operation [unpin_user_pages()], and for truly > > longterm pins to be proactively recovered via device specific shrinkers > > [i.e. stop the HW, allow the pages to be returned to the system, and > > then compete again for the memory]. > > Is the later implemented? Depends on driver, for i915 we had a shrinker since before we introduced get_user_pages objects. We have the same problem with trying to mitigate userspace wanting to use all of memory for a single operation, whether it's from shmemfs or get_user_pages. > Btw. overall intention of the patch is not really clear to me. Do I get > it right that this is going to reduce latency of the reclaim for pages > that are not reclaimable anyway because they are pinned? If yes do we > have any numbers for that. I can plug it into a microbenchmark ala cycletest to show the impact... Memory filled with 64M gup objects, random utilisation of those with the GPU; background process filling the pagecache with find /; reporting the time difference from the expected expiry of a timer with the actual: [On a Geminilake Atom-class processor with 8GiB, average of 5 runs, each measuring mean latency for 20s -- mean is probably a really bad choice here, we need 50/90/95/99] direct reclaim calling mmu-notifier: gem_syslatency: cycles=2122, latency mean=1601.185us max=33572us skipping try_to_unmap_one with page_maybe_dma_pinned: gem_syslatency: cycles=1965, latency mean=597.971us max=28462us Baseline (background find /; application touched all memory, but no HW ops) gem_syslatency: cycles=0, latency mean=6.695us max=77us Compare with the time to allocate a single THP against load: Baseline: gem_syslatency: cycles=0, latency mean=1541.562us max=52196us Direct reclaim calling mmu-notifier: gem_syslatency: cycles=2115, latency mean=9050.930us max=396986us page_maybe_dma_pinned skip: gem_syslatency: cycles=2325, latency mean=7431.633us max=187960us Take with a massive pinch of salt. I expect, once I find the right sequence, to reliably control the induced latency on the RT thread. But first, I have to look at why there's a correlation with HW load and timer latency, even with steady state usage. That's quite surprising -- ah, I had it left to PREEMPT_VOLUNTARY and this machine has to scan every request submitted to HW. Just great. With PREEMPT: Timer: Base: gem_syslatency: cycles=0, latency mean=8.823us max=83us Reclaim: gem_syslatency: cycles=2224, latency mean=79.308us max=4805us Skip: gem_syslatency: cycles=2677, latency mean=70.306us max=4720us THP: Base: gem_syslatency: cycles=0, latency mean=1993.693us max=201958us Reclaim: gem_syslatency: cycles=1284, latency mean=2873.633us max=295962us Skip: gem_syslatency: cycles=1809, latency mean=1991.509us max=261050us Earlier caveats notwithstanding; confidence in results still low. And refine the testing somewhat, if at the very least gather enough samples for credible statistics. > It would be also good to explain why the bail out is implemented in > try_to_unmap rather than shrink_shrink_page_list. I'm in the process of working up the chain, having started with trying to circumvent the wait for reclaim in the mmu notifier callback in the driver. -Chris From jack at suse.cz Thu Jun 25 11:24:55 2020 From: jack at suse.cz (Jan Kara) Date: Thu, 25 Jun 2020 13:24:55 +0200 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <887ac706-65f0-3089-b51b-47aabf7d3847@nvidia.com> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200624192116.GO6578@ziepe.ca> <44708b2e-479f-7d58-fe01-29cfd6c70bdb@nvidia.com> <20200624232047.GP6578@ziepe.ca> <887ac706-65f0-3089-b51b-47aabf7d3847@nvidia.com> Message-ID: <20200625112455.GC17788@quack2.suse.cz> On Wed 24-06-20 17:11:30, John Hubbard wrote: > On 2020-06-24 16:20, Jason Gunthorpe wrote: > > > I do like this code change, though. And I *think* it's actually safe to > > > do this, as it stays away from writeback or other filesystem activity. > > > But let me double check that, in case I'm forgetting something. > > ...OK, I've checked, and I like it a little bit less now. Mainly for > structural reasons, though. I think it would work correctly. But > here's a concern: try_to_unmap() should only fail to unmap if there is a > reason to not unmap. Having a page be pinned for dma is a reason to not > *free* a page, and it's also a reason to be careful about writeback and > page buffers for writeback and such. But I'm not sure that it's a reason > to fail to remove mappings. > > True, most (all?) of the reasons that we remove mappings, generally are > for things that are not allowed while a page is dma-pinned...at least, > today. But still, there's nothing fundamental about a mapping that > should prevent it from coming or going while a page is undergoing > dma. > > So, it's merely a convenient, now-misnamed location in the call stack > to fail out. That's not great. It might be better, as Jason hints at > below, to fail out a little earlier, instead. That would lead to a more > places to call page_maybe_dma_pinned(), but that's not a real problem, > because it's still a small number of places. Agreed, I think that shrink_page_list() as Michal writes is a better place for the page_may_be_dma_pinned() check. But other than that I agree it is good to avoid all the unnecessary work of preparing a page for reclaim when we can now check there's no hope of reclaiming it (at this time). > > I don't know, but could it be that try_to_unmap() has to be done > > before checking the refcount as each mapping is included in the > > refcount? ie we couldn't know a DMA pin was active in advance? > > > > Now that we have your pin stuff we can detect a DMA pin without doing > > all the unmaps? > > > > Once something calls pin_user_page*(), then the pages will be marked > as dma-pinned, yes. So no, there is no need to wait until try_to_unmap() > to find out. Yeah, I'm pretty sure the page ref check happens so late because earlier it was impossible to tell whether there are "external" page references reclaim cannot get rid of - filesystem may (but need not!) hold a page reference for its private data, page tables will hold references as well, etc. Now with page_may_be_dma_pinned() we can detect at least one class of external references (i.e. pins) early so it's stupid not to do that. > A final note: depending on where page_maybe_dma_pinned() ends up > getting called, this might prevent a fair number of the problems that > Jan originally reported [1], and that I also reported separately! > > Well, not all of the problems, and only after the filesystems get > converted to call pin_user_pages() (working on that next), but...I think > it would actually avoid the crash our customer reported back in early > 2018. Even though we don't have the full file lease + pin_user_pages() > solution in place. > > That's because reclaim is what triggers the problems that we saw. And > with this patch, we bail out of reclaim early. I agree that with this change, some races will become much less likely for some usecases. But as you say, it's not a full solution. Honza -- Jan Kara <jack at suse.com> SUSE Labs, CR From willy at infradead.org Thu Jun 25 11:42:09 2020 From: willy at infradead.org (Matthew Wilcox) Date: Thu, 25 Jun 2020 12:42:09 +0100 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200624191417.16735-1-chris@chris-wilson.co.uk> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> Message-ID: <20200625114209.GA7703@casper.infradead.org> On Wed, Jun 24, 2020 at 08:14:17PM +0100, Chris Wilson wrote: > A side effect of the LRU shrinker not being dma aware is that we will > often attempt to perform direct reclaim on the persistent group of dma > pages while continuing to use the dma HW (an issue as the HW may already > be actively waiting for the next user request), and even attempt to > reclaim a partially allocated dma object in order to satisfy pinning > the next user page for that object. > > It is to be expected that such pages are made available for reclaim at > the end of the dma operation [unpin_user_pages()], and for truly > longterm pins to be proactively recovered via device specific shrinkers > [i.e. stop the HW, allow the pages to be returned to the system, and > then compete again for the memory]. Why are DMA pinned pages still on the LRU list at all? I never got an answer to this that made sense to me. By definition, a page which is pinned for DMA is being accessed, and needs to at the very least change position on the LRU list, so just take it off the list when DMA-pinned and put it back on the list when DMA-unpinned. This overly complex lease stuff must have some reason for existing, but I still don't get it. From lionel.g.landwerlin at intel.com Thu Jun 25 12:34:42 2020 From: lionel.g.landwerlin at intel.com (Lionel Landwerlin) Date: Thu, 25 Jun 2020 15:34:42 +0300 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" Message-ID: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> This reverts commit 5de376bb434f80a13138f0ebedc8351ab73d8b0d. This change breaks synchronization of a timeline. dma_fence_chain_find_seqno() might be a bit of a confusing name but this function is not trying to find a particular seqno, is supposed to give a fence to wait on for a particular point in the timeline. In a timeline, a particular value is reached when all the points up to and including that value have signaled. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com> --- drivers/dma-buf/dma-fence-chain.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c index c435bbba851c..3d123502ff12 100644 --- a/drivers/dma-buf/dma-fence-chain.c +++ b/drivers/dma-buf/dma-fence-chain.c @@ -99,12 +99,6 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) return -EINVAL; dma_fence_chain_for_each(*pfence, &chain->base) { - if ((*pfence)->seqno < seqno) { /* already signaled */ - dma_fence_put(*pfence); - *pfence = NULL; - break; - } - if ((*pfence)->context != chain->base.context || to_dma_fence_chain(*pfence)->prev_seqno < seqno) break; @@ -228,7 +222,6 @@ EXPORT_SYMBOL(dma_fence_chain_ops); * @chain: the chain node to initialize * @prev: the previous fence * @fence: the current fence - * @seqno: the sequence number (syncpt) of the fence within the chain * * Initialize a new chain node and either start a new chain or add the node to * the existing chain of the previous fence. -- 2.27.0 From lionel.g.landwerlin at intel.com Thu Jun 25 12:34:43 2020 From: lionel.g.landwerlin at intel.com (Lionel Landwerlin) Date: Thu, 25 Jun 2020 15:34:43 +0300 Subject: [Intel-gfx] [PATCH 2/2] dma-buf: fix dma-fence-chain out of order test In-Reply-To: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> Message-ID: <20200625123443.19680-2-lionel.g.landwerlin@intel.com> There was probably a misunderstand on how the dma-fence-chain is supposed to work or what dma_fence_chain_find_seqno() is supposed to return. dma_fence_chain_find_seqno() is here to give us the fence to wait upon for a particular point in the timeline. The timeline progresses only when all the points prior to a given number have completed. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com> Fixes: dc2f7e67a28a5c ("dma-buf: Exercise dma-fence-chain under selftests") --- drivers/dma-buf/st-dma-fence-chain.c | 43 ++++++++++++++-------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/dma-buf/st-dma-fence-chain.c b/drivers/dma-buf/st-dma-fence-chain.c index 5d45ba7ba3cd..9525f7f56119 100644 --- a/drivers/dma-buf/st-dma-fence-chain.c +++ b/drivers/dma-buf/st-dma-fence-chain.c @@ -318,15 +318,16 @@ static int find_out_of_order(void *arg) goto err; } - if (fence && fence != fc.chains[1]) { + /* + * We signaled the middle fence (2) of the 1-2-3 chain. The behavior + * of the dma-fence-chain is to make us wait for all the fences up to + * the point we want. Since fence 1 is still not signaled, this what + * we should get as fence to wait upon (fence 2 being garbage + * collected during the traversal of the chain). + */ + if (fence != fc.chains[0]) { pr_err("Incorrect chain-fence.seqno:%lld reported for completed seqno:2\n", - fence->seqno); - - dma_fence_get(fence); - err = dma_fence_chain_find_seqno(&fence, 2); - dma_fence_put(fence); - if (err) - pr_err("Reported %d for finding self!\n", err); + fence ? fence->seqno : 0); err = -EINVAL; } @@ -415,20 +416,18 @@ static int __find_race(void *arg) if (!fence) goto signal; - err = dma_fence_chain_find_seqno(&fence, seqno); - if (err) { - pr_err("Reported an invalid fence for find-self:%d\n", - seqno); - dma_fence_put(fence); - break; - } - - if (fence->seqno < seqno) { - pr_err("Reported an earlier fence.seqno:%lld for seqno:%d\n", - fence->seqno, seqno); - err = -EINVAL; - dma_fence_put(fence); - break; + /* + * We can only find ourselves if we are on fence we were + * looking for. + */ + if (fence->seqno == seqno) { + err = dma_fence_chain_find_seqno(&fence, seqno); + if (err) { + pr_err("Reported an invalid fence for find-self:%d\n", + seqno); + dma_fence_put(fence); + break; + } } dma_fence_put(fence); -- 2.27.0 From christian.koenig at amd.com Thu Jun 25 12:43:41 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Thu, 25 Jun 2020 14:43:41 +0200 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> Message-ID: <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> Am 25.06.20 um 14:34 schrieb Lionel Landwerlin: > This reverts commit 5de376bb434f80a13138f0ebedc8351ab73d8b0d. > > This change breaks synchronization of a timeline. > dma_fence_chain_find_seqno() might be a bit of a confusing name but > this function is not trying to find a particular seqno, is supposed to > give a fence to wait on for a particular point in the timeline. > > In a timeline, a particular value is reached when all the points up to > and including that value have signaled. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com> Reviewed-by: Christian K?nig <christian.koenig at amd.com> > --- > drivers/dma-buf/dma-fence-chain.c | 7 ------- > 1 file changed, 7 deletions(-) > > diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c > index c435bbba851c..3d123502ff12 100644 > --- a/drivers/dma-buf/dma-fence-chain.c > +++ b/drivers/dma-buf/dma-fence-chain.c > @@ -99,12 +99,6 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) > return -EINVAL; > > dma_fence_chain_for_each(*pfence, &chain->base) { > - if ((*pfence)->seqno < seqno) { /* already signaled */ > - dma_fence_put(*pfence); > - *pfence = NULL; > - break; > - } > - > if ((*pfence)->context != chain->base.context || > to_dma_fence_chain(*pfence)->prev_seqno < seqno) > break; > @@ -228,7 +222,6 @@ EXPORT_SYMBOL(dma_fence_chain_ops); > * @chain: the chain node to initialize > * @prev: the previous fence > * @fence: the current fence > - * @seqno: the sequence number (syncpt) of the fence within the chain > * > * Initialize a new chain node and either start a new chain or add the node to > * the existing chain of the previous fence. From christian.koenig at amd.com Thu Jun 25 12:44:08 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Thu, 25 Jun 2020 14:44:08 +0200 Subject: [Intel-gfx] [PATCH 2/2] dma-buf: fix dma-fence-chain out of order test In-Reply-To: <20200625123443.19680-2-lionel.g.landwerlin@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <20200625123443.19680-2-lionel.g.landwerlin@intel.com> Message-ID: <e782f2eb-2345-a66f-6d5a-78fe3aeaaa85@amd.com> Am 25.06.20 um 14:34 schrieb Lionel Landwerlin: > There was probably a misunderstand on how the dma-fence-chain is > supposed to work or what dma_fence_chain_find_seqno() is supposed to > return. > > dma_fence_chain_find_seqno() is here to give us the fence to wait upon > for a particular point in the timeline. The timeline progresses only > when all the points prior to a given number have completed. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com> > Fixes: dc2f7e67a28a5c ("dma-buf: Exercise dma-fence-chain under selftests") Acked-by: Christian K?nig <christian.koenig at amd.com> > --- > drivers/dma-buf/st-dma-fence-chain.c | 43 ++++++++++++++-------------- > 1 file changed, 21 insertions(+), 22 deletions(-) > > diff --git a/drivers/dma-buf/st-dma-fence-chain.c b/drivers/dma-buf/st-dma-fence-chain.c > index 5d45ba7ba3cd..9525f7f56119 100644 > --- a/drivers/dma-buf/st-dma-fence-chain.c > +++ b/drivers/dma-buf/st-dma-fence-chain.c > @@ -318,15 +318,16 @@ static int find_out_of_order(void *arg) > goto err; > } > > - if (fence && fence != fc.chains[1]) { > + /* > + * We signaled the middle fence (2) of the 1-2-3 chain. The behavior > + * of the dma-fence-chain is to make us wait for all the fences up to > + * the point we want. Since fence 1 is still not signaled, this what > + * we should get as fence to wait upon (fence 2 being garbage > + * collected during the traversal of the chain). > + */ > + if (fence != fc.chains[0]) { > pr_err("Incorrect chain-fence.seqno:%lld reported for completed seqno:2\n", > - fence->seqno); > - > - dma_fence_get(fence); > - err = dma_fence_chain_find_seqno(&fence, 2); > - dma_fence_put(fence); > - if (err) > - pr_err("Reported %d for finding self!\n", err); > + fence ? fence->seqno : 0); > > err = -EINVAL; > } > @@ -415,20 +416,18 @@ static int __find_race(void *arg) > if (!fence) > goto signal; > > - err = dma_fence_chain_find_seqno(&fence, seqno); > - if (err) { > - pr_err("Reported an invalid fence for find-self:%d\n", > - seqno); > - dma_fence_put(fence); > - break; > - } > - > - if (fence->seqno < seqno) { > - pr_err("Reported an earlier fence.seqno:%lld for seqno:%d\n", > - fence->seqno, seqno); > - err = -EINVAL; > - dma_fence_put(fence); > - break; > + /* > + * We can only find ourselves if we are on fence we were > + * looking for. > + */ > + if (fence->seqno == seqno) { > + err = dma_fence_chain_find_seqno(&fence, seqno); > + if (err) { > + pr_err("Reported an invalid fence for find-self:%d\n", > + seqno); > + dma_fence_put(fence); > + break; > + } > } > > dma_fence_put(fence); From chris at chris-wilson.co.uk Thu Jun 25 12:48:33 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 13:48:33 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> Message-ID: <159308931300.4527.14536354033703689604@build.alporthouse.com> Quoting Christian K?nig (2020-06-25 09:11:35) > Am 24.06.20 um 22:18 schrieb Chris Wilson: > > Quoting Dave Airlie (2020-06-24 20:04:02) > >> On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: > >>> Quoting Dave Airlie (2020-06-23 22:01:24) > >>>> On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: > >>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > >>>>>> Hi, Chris! > >>>>>> > >>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>>>>>> In order to actually handle eviction and what not, we need to process > >>>>>>> all the objects together under a common lock, reservation_ww_class. As > >>>>>>> such, do a memory reservation pass after looking up the object/vma, > >>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>>>>>> flushing and ofc execution]. > >>>>>>> > >>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>>>>>> --- > >>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>>>>>> > >>>>>> Which tree is this against? The series doesn't apply cleanly against > >>>>>> drm-tip? > >>>>> It's continuing on from the scheduler patches, the bug fixes and the > >>>>> iris-deferred-fence work. I thought throwing all of those old patches > >>>>> into the pile would have been distracting. > >>>>> > >>>>>> ... > >>>>>> > >>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>>>>>> +{ > >>>>>>> + const u64 idx = eb->context->timeline->fence_context; > >>>>>>> + struct ww_acquire_ctx acquire; > >>>>>>> + struct eb_vma *ev; > >>>>>>> + int err; > >>>>>>> + > >>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>>>>>> + if (!eb->mm_fence) > >>>>>>> + return -ENOMEM; > >>>>>> Where are the proxy fence functions defined? > >>>>> In dma-fence-proxy.c ;) > >>>> The dma-fence-proxy that Christian NAKed before? > >>> I do not have an email from Christian about dma-fence-proxy in the last > >>> 3 years it has been on the list. > >> https://lore.kernel.org/dri-devel/aeb0373d-0583-d922-3b73-93668c27d177 at amd.com/ > > Darn, I skimmed the thread title and thought it was just about the > > timelines. > > > >> I'm assuming this was about patch 8 there which to me looks like proxy > >> fences but maybe by threading is off reading that. > > The deadlocks are easy to resolve. The fence is either signaled normally > > by userspace, they create a deadlock that is rejected by checking the dag > > and the fence signaled with an error (and work cancelled, error > > propagated back to userspace if they kept the output fence around), or > > userspace forgets entirely about the fence they were waiting on in which > > case it is signaled by closing the syncobjs [sadly not in error though, > > I hoping to report EPIPE] on process termination. > > And exactly that concept is still a big NAK. > > The kernel memory management depends on dma_fences to be signaling as > soon as they are existing. > > Just imagine what Daniel's dependency patches would splat out when you > do something like this and correctly annotate the signaling code path. Nothing at all. Forward progress of the waiter does not solely depend on the signaler, just as in bc9c80fe01a2570a2fd78abbc492b377b5fda068. > Proxy fences, especially when they depend on userspace for signaling are > an absolutely NO-GO. We are in full control of the signaling and are able to cancel the pending userspace operation, move it off to one side and shutdown the HW, whatever. We can and do do dependency analysis of the fence contexts to avoid deadlocks, just as easily as detecting recursion. To claim that userspace is not already able to control signaling, is a false dichotomy. Userspace is fully able to lock the HW resources indefinitely (even if you cap every job, one can always build a chain of jobs to circumvent any imposed timeout, a couple of seconds timeout becomes several months of jobs before the GPU runs out of memory and is unable to accept any more jobs). Any ioctl that blocks while holding a HW resource renders itself liable to a user controllable livelock, you know this, because it is blocking the signaling of those earlier jobs. Worrying about things that are entirely within our control and hence avoidable, misses the point. -Chris From christian.koenig at amd.com Thu Jun 25 12:59:16 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Thu, 25 Jun 2020 14:59:16 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159308931300.4527.14536354033703689604@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> Message-ID: <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> Am 25.06.20 um 14:48 schrieb Chris Wilson: > Quoting Christian K?nig (2020-06-25 09:11:35) >> Am 24.06.20 um 22:18 schrieb Chris Wilson: >>> Quoting Dave Airlie (2020-06-24 20:04:02) >>>> On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: >>>>> Quoting Dave Airlie (2020-06-23 22:01:24) >>>>>> On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: >>>>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) >>>>>>>> Hi, Chris! >>>>>>>> >>>>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: >>>>>>>>> In order to actually handle eviction and what not, we need to process >>>>>>>>> all the objects together under a common lock, reservation_ww_class. As >>>>>>>>> such, do a memory reservation pass after looking up the object/vma, >>>>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>>>>>>>> flushing and ofc execution]. >>>>>>>>> >>>>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>>>>>>>> --- >>>>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>>>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) >>>>>>>>> >>>>>>>> Which tree is this against? The series doesn't apply cleanly against >>>>>>>> drm-tip? >>>>>>> It's continuing on from the scheduler patches, the bug fixes and the >>>>>>> iris-deferred-fence work. I thought throwing all of those old patches >>>>>>> into the pile would have been distracting. >>>>>>> >>>>>>>> ... >>>>>>>> >>>>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>>>>>>>> +{ >>>>>>>>> + const u64 idx = eb->context->timeline->fence_context; >>>>>>>>> + struct ww_acquire_ctx acquire; >>>>>>>>> + struct eb_vma *ev; >>>>>>>>> + int err; >>>>>>>>> + >>>>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); >>>>>>>>> + if (!eb->mm_fence) >>>>>>>>> + return -ENOMEM; >>>>>>>> Where are the proxy fence functions defined? >>>>>>> In dma-fence-proxy.c ;) >>>>>> The dma-fence-proxy that Christian NAKed before? >>>>> I do not have an email from Christian about dma-fence-proxy in the last >>>>> 3 years it has been on the list. >>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fdri-devel%2Faeb0373d-0583-d922-3b73-93668c27d177%40amd.com%2F&data=02%7C01%7Cchristian.koenig%40amd.com%7Ccb060e358d844784815708d819061868%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637286861292346372&sdata=DlHistmqPi%2BtwdcT%2FycrtRpoLGZ6xcBD%2FkPvVZcQ2YQ%3D&reserved=0 >>> Darn, I skimmed the thread title and thought it was just about the >>> timelines. >>> >>>> I'm assuming this was about patch 8 there which to me looks like proxy >>>> fences but maybe by threading is off reading that. >>> The deadlocks are easy to resolve. The fence is either signaled normally >>> by userspace, they create a deadlock that is rejected by checking the dag >>> and the fence signaled with an error (and work cancelled, error >>> propagated back to userspace if they kept the output fence around), or >>> userspace forgets entirely about the fence they were waiting on in which >>> case it is signaled by closing the syncobjs [sadly not in error though, >>> I hoping to report EPIPE] on process termination. >> And exactly that concept is still a big NAK. >> >> The kernel memory management depends on dma_fences to be signaling as >> soon as they are existing. >> >> Just imagine what Daniel's dependency patches would splat out when you >> do something like this and correctly annotate the signaling code path. > Nothing at all. Forward progress of the waiter does not solely depend on > the signaler, just as in bc9c80fe01a2570a2fd78abbc492b377b5fda068. > >> Proxy fences, especially when they depend on userspace for signaling are >> an absolutely NO-GO. > We are in full control of the signaling and are able to cancel the pending > userspace operation, move it off to one side and shutdown the HW, > whatever. We can and do do dependency analysis of the fence contexts to > avoid deadlocks, just as easily as detecting recursion. > > To claim that userspace is not already able to control signaling, is a > false dichotomy. Userspace is fully able to lock the HW resources > indefinitely (even if you cap every job, one can always build a chain of > jobs to circumvent any imposed timeout, a couple of seconds timeout > becomes several months of jobs before the GPU runs out of memory and is > unable to accept any more jobs). Any ioctl that blocks while holding a HW > resource renders itself liable to a user controllable livelock, you know > this, because it is blocking the signaling of those earlier jobs. > Worrying about things that are entirely within our control and hence > avoidable, misses the point. You are completely missing the problem here. As you correctly pointed out that an userspace thread blocks on something is perfectly acceptable. And that's how bc9c80fe01a2570a2fd78abbc492b377b5fda068 works as well. And bc9c80fe01a2570a2fd78abbc492b377b5fda068 only implements waiting so that during CS or WAIT IOCTL we can block for the fence to appear. What happens in your approach is that the kernel starts to wait for userspace in its memory reclaim path. That is exactly the kind of problem Daniels patches now point out immediately. So while the hardware can obviously get stuck in an endless loop and needs to be recovered, this here has the potential of a system wide kernel deadlock which is not recoverable. The whole approach is an absolutely clear NAK! Regards, Christian. > -Chris From joro at 8bytes.org Thu Jun 25 13:08:23 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:23 +0200 Subject: [Intel-gfx] [PATCH 00/13] iommu: Remove usage of dev->archdata.iommu Message-ID: <20200625130836.1916-1-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Hi, here is a patch-set to remove the usage of dev->archdata.iommu from the IOMMU code in the kernel and replace its uses by the iommu per-device private data field. The changes also remove the field entirely from the architectures which no longer need it. On PowerPC the field is called dev->archdata.iommu_domain and was only used by the PAMU IOMMU driver. It gets removed as well. The patches have been runtime tested on Intel VT-d and compile tested with allyesconfig for: * x86 (32 and 64 bit) * arm and arm64 * ia64 (only drivers/ because build failed for me in arch/ia64) * PPC64 Besides that the changes also survived my IOMMU tree compile tests. Please review. Regards, Joerg Joerg Roedel (13): iommu/exynos: Use dev_iommu_priv_get/set() iommu/vt-d: Use dev_iommu_priv_get/set() iommu/msm: Use dev_iommu_priv_get/set() iommu/omap: Use dev_iommu_priv_get/set() iommu/rockchip: Use dev_iommu_priv_get/set() iommu/tegra: Use dev_iommu_priv_get/set() iommu/pamu: Use dev_iommu_priv_get/set() iommu/mediatek: Do no use dev->archdata.iommu x86: Remove dev->archdata.iommu pointer ia64: Remove dev->archdata.iommu pointer arm: Remove dev->archdata.iommu pointer arm64: Remove dev->archdata.iommu pointer powerpc/dma: Remove dev->archdata.iommu_domain arch/arm/include/asm/device.h | 3 --- arch/arm64/include/asm/device.h | 3 --- arch/ia64/include/asm/device.h | 3 --- arch/powerpc/include/asm/device.h | 3 --- arch/x86/include/asm/device.h | 3 --- .../gpu/drm/i915/selftests/mock_gem_device.c | 10 ++++++++-- drivers/iommu/exynos-iommu.c | 20 +++++++++---------- drivers/iommu/fsl_pamu_domain.c | 8 ++++---- drivers/iommu/intel/iommu.c | 18 ++++++++--------- drivers/iommu/msm_iommu.c | 4 ++-- drivers/iommu/mtk_iommu.h | 2 ++ drivers/iommu/mtk_iommu_v1.c | 10 ++++------ drivers/iommu/omap-iommu.c | 20 +++++++++---------- drivers/iommu/rockchip-iommu.c | 8 ++++---- drivers/iommu/tegra-gart.c | 8 ++++---- drivers/iommu/tegra-smmu.c | 8 ++++---- .../media/platform/s5p-mfc/s5p_mfc_iommu.h | 4 +++- 17 files changed, 64 insertions(+), 71 deletions(-) -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:34 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:34 +0200 Subject: [Intel-gfx] [PATCH 11/13] arm: Remove dev->archdata.iommu pointer In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-12-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> There are no users left, all drivers have been converted to use the per-device private pointer offered by IOMMU core. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/arm/include/asm/device.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h index c675bc0d5aa8..be666f58bf7a 100644 --- a/arch/arm/include/asm/device.h +++ b/arch/arm/include/asm/device.h @@ -9,9 +9,6 @@ struct dev_archdata { #ifdef CONFIG_DMABOUNCE struct dmabounce_device_info *dmabounce; #endif -#ifdef CONFIG_IOMMU_API - void *iommu; /* private IOMMU data */ -#endif #ifdef CONFIG_ARM_DMA_USE_IOMMU struct dma_iommu_mapping *mapping; #endif -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:30 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:30 +0200 Subject: [Intel-gfx] [PATCH 07/13] iommu/pamu: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-8-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Remove the use of dev->archdata.iommu_domain and use the private per-device pointer provided by IOMMU core code instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/fsl_pamu_domain.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index 928d37771ece..b2110767caf4 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -323,7 +323,7 @@ static void remove_device_ref(struct device_domain_info *info, u32 win_cnt) pamu_disable_liodn(info->liodn); spin_unlock_irqrestore(&iommu_lock, flags); spin_lock_irqsave(&device_domain_lock, flags); - info->dev->archdata.iommu_domain = NULL; + dev_iommu_priv_set(info->dev, NULL); kmem_cache_free(iommu_devinfo_cache, info); spin_unlock_irqrestore(&device_domain_lock, flags); } @@ -352,7 +352,7 @@ static void attach_device(struct fsl_dma_domain *dma_domain, int liodn, struct d * Check here if the device is already attached to domain or not. * If the device is already attached to a domain detach it. */ - old_domain_info = dev->archdata.iommu_domain; + old_domain_info = dev_iommu_priv_get(dev); if (old_domain_info && old_domain_info->domain != dma_domain) { spin_unlock_irqrestore(&device_domain_lock, flags); detach_device(dev, old_domain_info->domain); @@ -371,8 +371,8 @@ static void attach_device(struct fsl_dma_domain *dma_domain, int liodn, struct d * the info for the first LIODN as all * LIODNs share the same domain */ - if (!dev->archdata.iommu_domain) - dev->archdata.iommu_domain = info; + if (!dev_iommu_priv_get(dev)) + dev_iommu_priv_set(dev, info); spin_unlock_irqrestore(&device_domain_lock, flags); } -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:26 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:26 +0200 Subject: [Intel-gfx] [PATCH 03/13] iommu/msm: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-4-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Remove the use of dev->archdata.iommu and use the private per-device pointer provided by IOMMU core code instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/msm_iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 3d8a63555c25..f773cc85f311 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -593,14 +593,14 @@ static void insert_iommu_master(struct device *dev, struct msm_iommu_dev **iommu, struct of_phandle_args *spec) { - struct msm_iommu_ctx_dev *master = dev->archdata.iommu; + struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev); int sid; if (list_empty(&(*iommu)->ctx_list)) { master = kzalloc(sizeof(*master), GFP_ATOMIC); master->of_node = dev->of_node; list_add(&master->list, &(*iommu)->ctx_list); - dev->archdata.iommu = master; + dev_iommu_priv_set(dev, master); } for (sid = 0; sid < master->num_mids; sid++) -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:27 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:27 +0200 Subject: [Intel-gfx] [PATCH 04/13] iommu/omap: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-5-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Remove the use of dev->archdata.iommu and use the private per-device pointer provided by IOMMU core code instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/omap-iommu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index c8282cc212cb..e84ead6fb234 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -71,7 +71,7 @@ static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom) **/ void omap_iommu_save_ctx(struct device *dev) { - struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); struct omap_iommu *obj; u32 *p; int i; @@ -101,7 +101,7 @@ EXPORT_SYMBOL_GPL(omap_iommu_save_ctx); **/ void omap_iommu_restore_ctx(struct device *dev) { - struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); struct omap_iommu *obj; u32 *p; int i; @@ -1398,7 +1398,7 @@ static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da, static int omap_iommu_count(struct device *dev) { - struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); int count = 0; while (arch_data->iommu_dev) { @@ -1459,8 +1459,8 @@ static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain) static int omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) { + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); struct omap_iommu_domain *omap_domain = to_omap_domain(domain); - struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; struct omap_iommu_device *iommu; struct omap_iommu *oiommu; int ret = 0; @@ -1524,7 +1524,7 @@ omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, struct device *dev) { - struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); struct omap_iommu_device *iommu = omap_domain->iommus; struct omap_iommu *oiommu; int i; @@ -1650,7 +1650,7 @@ static struct iommu_device *omap_iommu_probe_device(struct device *dev) int num_iommus, i; /* - * Allocate the archdata iommu structure for DT-based devices. + * Allocate the per-device iommu structure for DT-based devices. * * TODO: Simplify this when removing non-DT support completely from the * IOMMU users. @@ -1698,7 +1698,7 @@ static struct iommu_device *omap_iommu_probe_device(struct device *dev) of_node_put(np); } - dev->archdata.iommu = arch_data; + dev_iommu_priv_set(dev, arch_data); /* * use the first IOMMU alone for the sysfs device linking. @@ -1712,19 +1712,19 @@ static struct iommu_device *omap_iommu_probe_device(struct device *dev) static void omap_iommu_release_device(struct device *dev) { - struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); if (!dev->of_node || !arch_data) return; - dev->archdata.iommu = NULL; + dev_iommu_priv_set(dev, NULL); kfree(arch_data); } static struct iommu_group *omap_iommu_device_group(struct device *dev) { - struct omap_iommu_arch_data *arch_data = dev->archdata.iommu; + struct omap_iommu_arch_data *arch_data = dev_iommu_priv_get(dev); struct iommu_group *group = ERR_PTR(-EINVAL); if (!arch_data) -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:24 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:24 +0200 Subject: [Intel-gfx] [PATCH 01/13] iommu/exynos: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-2-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Remove the use of dev->archdata.iommu and use the private per-device pointer provided by IOMMU core code instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/exynos-iommu.c | 20 +++++++++---------- .../media/platform/s5p-mfc/s5p_mfc_iommu.h | 4 +++- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 60c8a56e4a3f..6a9b67302369 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -173,7 +173,7 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define REG_V5_FAULT_AR_VA 0x070 #define REG_V5_FAULT_AW_VA 0x080 -#define has_sysmmu(dev) (dev->archdata.iommu != NULL) +#define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) static struct device *dma_dev; static struct kmem_cache *lv2table_kmem_cache; @@ -226,7 +226,7 @@ static const struct sysmmu_fault_info sysmmu_v5_faults[] = { }; /* - * This structure is attached to dev.archdata.iommu of the master device + * This structure is attached to dev->iommu->priv of the master device * on device add, contains a list of SYSMMU controllers defined by device tree, * which are bound to given master device. It is usually referenced by 'owner' * pointer. @@ -670,7 +670,7 @@ static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) struct device *master = data->master; if (master) { - struct exynos_iommu_owner *owner = master->archdata.iommu; + struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); mutex_lock(&owner->rpm_lock); if (data->domain) { @@ -688,7 +688,7 @@ static int __maybe_unused exynos_sysmmu_resume(struct device *dev) struct device *master = data->master; if (master) { - struct exynos_iommu_owner *owner = master->archdata.iommu; + struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); mutex_lock(&owner->rpm_lock); if (data->domain) { @@ -837,8 +837,8 @@ static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, struct device *dev) { - struct exynos_iommu_owner *owner = dev->archdata.iommu; struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); phys_addr_t pagetable = virt_to_phys(domain->pgtable); struct sysmmu_drvdata *data, *next; unsigned long flags; @@ -875,8 +875,8 @@ static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, struct device *dev) { - struct exynos_iommu_owner *owner = dev->archdata.iommu; struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); struct sysmmu_drvdata *data; phys_addr_t pagetable = virt_to_phys(domain->pgtable); unsigned long flags; @@ -1237,7 +1237,7 @@ static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, static struct iommu_device *exynos_iommu_probe_device(struct device *dev) { - struct exynos_iommu_owner *owner = dev->archdata.iommu; + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); struct sysmmu_drvdata *data; if (!has_sysmmu(dev)) @@ -1263,7 +1263,7 @@ static struct iommu_device *exynos_iommu_probe_device(struct device *dev) static void exynos_iommu_release_device(struct device *dev) { - struct exynos_iommu_owner *owner = dev->archdata.iommu; + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); struct sysmmu_drvdata *data; if (!has_sysmmu(dev)) @@ -1287,8 +1287,8 @@ static void exynos_iommu_release_device(struct device *dev) static int exynos_iommu_of_xlate(struct device *dev, struct of_phandle_args *spec) { - struct exynos_iommu_owner *owner = dev->archdata.iommu; struct platform_device *sysmmu = of_find_device_by_node(spec->np); + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); struct sysmmu_drvdata *data, *entry; if (!sysmmu) @@ -1305,7 +1305,7 @@ static int exynos_iommu_of_xlate(struct device *dev, INIT_LIST_HEAD(&owner->controllers); mutex_init(&owner->rpm_lock); - dev->archdata.iommu = owner; + dev_iommu_priv_set(dev, owner); } list_for_each_entry(entry, &owner->controllers, owner_node) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h b/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h index 152a713fff78..1a32266b7ddc 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h @@ -9,9 +9,11 @@ #if defined(CONFIG_EXYNOS_IOMMU) +#include <linux/iommu.h> + static inline bool exynos_is_iommu_available(struct device *dev) { - return dev->archdata.iommu != NULL; + return dev_iommu_priv_get(dev) != NULL; } #else -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:36 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:36 +0200 Subject: [Intel-gfx] [PATCH 13/13] powerpc/dma: Remove dev->archdata.iommu_domain In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-14-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> There are no users left, so remove the pointer and save some memory. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/powerpc/include/asm/device.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h index 266542769e4b..1bc595213338 100644 --- a/arch/powerpc/include/asm/device.h +++ b/arch/powerpc/include/asm/device.h @@ -34,9 +34,6 @@ struct dev_archdata { struct iommu_table *iommu_table_base; #endif -#ifdef CONFIG_IOMMU_API - void *iommu_domain; -#endif #ifdef CONFIG_PPC64 struct pci_dn *pci_data; #endif -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:35 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:35 +0200 Subject: [Intel-gfx] [PATCH 12/13] arm64: Remove dev->archdata.iommu pointer In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-13-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> There are no users left, all drivers have been converted to use the per-device private pointer offered by IOMMU core. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/arm64/include/asm/device.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/include/asm/device.h b/arch/arm64/include/asm/device.h index 12b778d55342..996498751318 100644 --- a/arch/arm64/include/asm/device.h +++ b/arch/arm64/include/asm/device.h @@ -6,9 +6,6 @@ #define __ASM_DEVICE_H struct dev_archdata { -#ifdef CONFIG_IOMMU_API - void *iommu; /* private IOMMU data */ -#endif }; struct pdev_archdata { -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:33 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:33 +0200 Subject: [Intel-gfx] [PATCH 10/13] ia64: Remove dev->archdata.iommu pointer In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-11-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> There are no users left, all drivers have been converted to use the per-device private pointer offered by IOMMU core. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/ia64/include/asm/device.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/ia64/include/asm/device.h b/arch/ia64/include/asm/device.h index 3eb397415381..918b198cd5bb 100644 --- a/arch/ia64/include/asm/device.h +++ b/arch/ia64/include/asm/device.h @@ -6,9 +6,6 @@ #define _ASM_IA64_DEVICE_H struct dev_archdata { -#ifdef CONFIG_IOMMU_API - void *iommu; /* hook for IOMMU specific extension */ -#endif }; struct pdev_archdata { -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:31 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:31 +0200 Subject: [Intel-gfx] [PATCH 08/13] iommu/mediatek: Do no use dev->archdata.iommu In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-9-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> The iommu private pointer is already used in the Mediatek IOMMU v1 driver, so move the dma_iommu_mapping pointer into 'struct mtk_iommu_data' and do not use dev->archdata.iommu anymore. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/mtk_iommu.h | 2 ++ drivers/iommu/mtk_iommu_v1.c | 10 ++++------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index ea949a324e33..1682406e98dc 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -62,6 +62,8 @@ struct mtk_iommu_data { struct iommu_device iommu; const struct mtk_iommu_plat_data *plat_data; + struct dma_iommu_mapping *mapping; /* For mtk_iommu_v1.c */ + struct list_head list; struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; }; diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index c9d79cff4d17..82ddfe9170d4 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -269,7 +269,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain, int ret; /* Only allow the domain created internally. */ - mtk_mapping = data->dev->archdata.iommu; + mtk_mapping = data->mapping; if (mtk_mapping->domain != domain) return 0; @@ -369,7 +369,6 @@ static int mtk_iommu_create_mapping(struct device *dev, struct mtk_iommu_data *data; struct platform_device *m4updev; struct dma_iommu_mapping *mtk_mapping; - struct device *m4udev; int ret; if (args->args_count != 1) { @@ -401,8 +400,7 @@ static int mtk_iommu_create_mapping(struct device *dev, return ret; data = dev_iommu_priv_get(dev); - m4udev = data->dev; - mtk_mapping = m4udev->archdata.iommu; + mtk_mapping = data->mapping; if (!mtk_mapping) { /* MTK iommu support 4GB iova address space. */ mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, @@ -410,7 +408,7 @@ static int mtk_iommu_create_mapping(struct device *dev, if (IS_ERR(mtk_mapping)) return PTR_ERR(mtk_mapping); - m4udev->archdata.iommu = mtk_mapping; + data->mapping = mtk_mapping; } return 0; @@ -459,7 +457,7 @@ static void mtk_iommu_probe_finalize(struct device *dev) int err; data = dev_iommu_priv_get(dev); - mtk_mapping = data->dev->archdata.iommu; + mtk_mapping = data->mapping; err = arm_iommu_attach_device(dev, mtk_mapping); if (err) -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:29 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:29 +0200 Subject: [Intel-gfx] [PATCH 06/13] iommu/tegra: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-7-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Remove the use of dev->archdata.iommu and use the private per-device pointer provided by IOMMU core code instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/tegra-gart.c | 8 ++++---- drivers/iommu/tegra-smmu.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/tegra-gart.c b/drivers/iommu/tegra-gart.c index 5fbdff6ff41a..fac720273889 100644 --- a/drivers/iommu/tegra-gart.c +++ b/drivers/iommu/tegra-gart.c @@ -113,8 +113,8 @@ static int gart_iommu_attach_dev(struct iommu_domain *domain, if (gart->active_domain && gart->active_domain != domain) { ret = -EBUSY; - } else if (dev->archdata.iommu != domain) { - dev->archdata.iommu = domain; + } else if (dev_iommu_priv_get(dev) != domain) { + dev_iommu_priv_set(dev, domain); gart->active_domain = domain; gart->active_devices++; } @@ -131,8 +131,8 @@ static void gart_iommu_detach_dev(struct iommu_domain *domain, spin_lock(&gart->dom_lock); - if (dev->archdata.iommu == domain) { - dev->archdata.iommu = NULL; + if (dev_iommu_priv_get(dev) == domain) { + dev_iommu_priv_set(dev, NULL); if (--gart->active_devices == 0) gart->active_domain = NULL; diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 7426b7666e2b..124c8848ab7e 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -465,7 +465,7 @@ static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, static int tegra_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { - struct tegra_smmu *smmu = dev->archdata.iommu; + struct tegra_smmu *smmu = dev_iommu_priv_get(dev); struct tegra_smmu_as *as = to_smmu_as(domain); struct device_node *np = dev->of_node; struct of_phandle_args args; @@ -780,7 +780,7 @@ static struct iommu_device *tegra_smmu_probe_device(struct device *dev) * supported by the Linux kernel, so abort after the * first match. */ - dev->archdata.iommu = smmu; + dev_iommu_priv_set(dev, smmu); break; } @@ -797,7 +797,7 @@ static struct iommu_device *tegra_smmu_probe_device(struct device *dev) static void tegra_smmu_release_device(struct device *dev) { - dev->archdata.iommu = NULL; + dev_iommu_priv_set(dev, NULL); } static const struct tegra_smmu_group_soc * @@ -856,7 +856,7 @@ static struct iommu_group *tegra_smmu_group_get(struct tegra_smmu *smmu, static struct iommu_group *tegra_smmu_device_group(struct device *dev) { struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct tegra_smmu *smmu = dev->archdata.iommu; + struct tegra_smmu *smmu = dev_iommu_priv_get(dev); struct iommu_group *group; group = tegra_smmu_group_get(smmu, fwspec->ids[0]); -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:25 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:25 +0200 Subject: [Intel-gfx] [PATCH 02/13] iommu/vt-d: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-3-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Remove the use of dev->archdata.iommu and use the private per-device pointer provided by IOMMU core code instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- .../gpu/drm/i915/selftests/mock_gem_device.c | 10 ++++++++-- drivers/iommu/intel/iommu.c | 18 +++++++++--------- 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 9b105b811f1f..e08601905a64 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -24,6 +24,7 @@ #include <linux/pm_domain.h> #include <linux/pm_runtime.h> +#include <linux/iommu.h> #include <drm/drm_managed.h> @@ -118,6 +119,9 @@ struct drm_i915_private *mock_gem_device(void) { struct drm_i915_private *i915; struct pci_dev *pdev; +#if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU) + struct dev_iommu iommu; +#endif int err; pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); @@ -136,8 +140,10 @@ struct drm_i915_private *mock_gem_device(void) dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU) - /* hack to disable iommu for the fake device; force identity mapping */ - pdev->dev.archdata.iommu = (void *)-1; + /* HACK HACK HACK to disable iommu for the fake device; force identity mapping */ + memset(&iommu, 0, sizeof(iommu)); + iommu.priv = (void *)-1; + pdev->dev.iommu = &iommu; #endif pci_set_drvdata(pdev, i915); diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index d759e7234e98..2ce490c2eab8 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -372,7 +372,7 @@ struct device_domain_info *get_domain_info(struct device *dev) if (!dev) return NULL; - info = dev->archdata.iommu; + info = dev_iommu_priv_get(dev); if (unlikely(info == DUMMY_DEVICE_DOMAIN_INFO || info == DEFER_DEVICE_DOMAIN_INFO)) return NULL; @@ -743,12 +743,12 @@ struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, static int iommu_dummy(struct device *dev) { - return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; + return dev_iommu_priv_get(dev) == DUMMY_DEVICE_DOMAIN_INFO; } static bool attach_deferred(struct device *dev) { - return dev->archdata.iommu == DEFER_DEVICE_DOMAIN_INFO; + return dev_iommu_priv_get(dev) == DEFER_DEVICE_DOMAIN_INFO; } /** @@ -2420,7 +2420,7 @@ static inline void unlink_domain_info(struct device_domain_info *info) list_del(&info->link); list_del(&info->global); if (info->dev) - info->dev->archdata.iommu = NULL; + dev_iommu_priv_set(info->dev, NULL); } static void domain_remove_dev_info(struct dmar_domain *domain) @@ -2453,7 +2453,7 @@ static void do_deferred_attach(struct device *dev) { struct iommu_domain *domain; - dev->archdata.iommu = NULL; + dev_iommu_priv_set(dev, NULL); domain = iommu_get_domain_for_dev(dev); if (domain) intel_iommu_attach_device(domain, dev); @@ -2599,7 +2599,7 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, list_add(&info->link, &domain->devices); list_add(&info->global, &device_domain_list); if (dev) - dev->archdata.iommu = info; + dev_iommu_priv_set(dev, info); spin_unlock_irqrestore(&device_domain_lock, flags); /* PASID table is mandatory for a PCI device in scalable mode. */ @@ -4004,7 +4004,7 @@ static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) { pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"); add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); - pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; + dev_iommu_priv_set(&pdev->dev, DUMMY_DEVICE_DOMAIN_INFO); } } DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); @@ -4043,7 +4043,7 @@ static void __init init_no_remapping_devices(void) drhd->ignored = 1; for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) - dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; + dev_iommu_priv_set(dev, DUMMY_DEVICE_DOMAIN_INFO); } } } @@ -5665,7 +5665,7 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev) return ERR_PTR(-ENODEV); if (translation_pre_enabled(iommu)) - dev->archdata.iommu = DEFER_DEVICE_DOMAIN_INFO; + dev_iommu_priv_set(dev, DEFER_DEVICE_DOMAIN_INFO); return &iommu->iommu; } -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:32 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:32 +0200 Subject: [Intel-gfx] [PATCH 09/13] x86: Remove dev->archdata.iommu pointer In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-10-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> There are no users left, all drivers have been converted to use the per-device private pointer offered by IOMMU core. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- arch/x86/include/asm/device.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/x86/include/asm/device.h b/arch/x86/include/asm/device.h index 49bd6cf3eec9..7c0a52ca2f4d 100644 --- a/arch/x86/include/asm/device.h +++ b/arch/x86/include/asm/device.h @@ -3,9 +3,6 @@ #define _ASM_X86_DEVICE_H struct dev_archdata { -#ifdef CONFIG_IOMMU_API - void *iommu; /* hook for IOMMU specific extension */ -#endif }; struct pdev_archdata { -- 2.27.0 From joro at 8bytes.org Thu Jun 25 13:08:28 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Thu, 25 Jun 2020 15:08:28 +0200 Subject: [Intel-gfx] [PATCH 05/13] iommu/rockchip: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200625130836.1916-6-joro@8bytes.org> From: Joerg Roedel <jroedel at suse.de> Remove the use of dev->archdata.iommu and use the private per-device pointer provided by IOMMU core code instead. Signed-off-by: Joerg Roedel <jroedel at suse.de> --- drivers/iommu/rockchip-iommu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index d25c2486ca07..e5d86b7177de 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -836,7 +836,7 @@ static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, static struct rk_iommu *rk_iommu_from_dev(struct device *dev) { - struct rk_iommudata *data = dev->archdata.iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); return data ? data->iommu : NULL; } @@ -1059,7 +1059,7 @@ static struct iommu_device *rk_iommu_probe_device(struct device *dev) struct rk_iommudata *data; struct rk_iommu *iommu; - data = dev->archdata.iommu; + data = dev_iommu_priv_get(dev); if (!data) return ERR_PTR(-ENODEV); @@ -1073,7 +1073,7 @@ static struct iommu_device *rk_iommu_probe_device(struct device *dev) static void rk_iommu_release_device(struct device *dev) { - struct rk_iommudata *data = dev->archdata.iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); device_link_del(data->link); } @@ -1100,7 +1100,7 @@ static int rk_iommu_of_xlate(struct device *dev, iommu_dev = of_find_device_by_node(args->np); data->iommu = platform_get_drvdata(iommu_dev); - dev->archdata.iommu = data; + dev_iommu_priv_set(dev, data); platform_device_put(iommu_dev); -- 2.27.0 From chris at chris-wilson.co.uk Thu Jun 25 13:18:52 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 14:18:52 +0100 Subject: [Intel-gfx] [PATCH 2/2] dma-buf: fix dma-fence-chain out of order test In-Reply-To: <20200625123443.19680-2-lionel.g.landwerlin@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <20200625123443.19680-2-lionel.g.landwerlin@intel.com> Message-ID: <159309113252.4527.2883585204850736358@build.alporthouse.com> Quoting Lionel Landwerlin (2020-06-25 13:34:43) > There was probably a misunderstand on how the dma-fence-chain is > supposed to work or what dma_fence_chain_find_seqno() is supposed to > return. > > dma_fence_chain_find_seqno() is here to give us the fence to wait upon > for a particular point in the timeline. The timeline progresses only > when all the points prior to a given number have completed. Hmm, the question was what point is it supposed to wait for. For the simple chain of [1, 3], does 1 being signaled imply that all points up to 3 are signaled, or does 3 not being signaled imply that all points after 1 are not. If that's mentioned already somewhere, my bad. If not, could you put the answer somewhere. -Chris From lionel.g.landwerlin at intel.com Thu Jun 25 13:23:25 2020 From: lionel.g.landwerlin at intel.com (Lionel Landwerlin) Date: Thu, 25 Jun 2020 16:23:25 +0300 Subject: [Intel-gfx] [PATCH 2/2] dma-buf: fix dma-fence-chain out of order test In-Reply-To: <159309113252.4527.2883585204850736358@build.alporthouse.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <20200625123443.19680-2-lionel.g.landwerlin@intel.com> <159309113252.4527.2883585204850736358@build.alporthouse.com> Message-ID: <c6f72d4d-c8a0-c484-7c31-761e9c37b85e@intel.com> On 25/06/2020 16:18, Chris Wilson wrote: > Quoting Lionel Landwerlin (2020-06-25 13:34:43) >> There was probably a misunderstand on how the dma-fence-chain is >> supposed to work or what dma_fence_chain_find_seqno() is supposed to >> return. >> >> dma_fence_chain_find_seqno() is here to give us the fence to wait upon >> for a particular point in the timeline. The timeline progresses only >> when all the points prior to a given number have completed. > Hmm, the question was what point is it supposed to wait for. > > For the simple chain of [1, 3], does 1 being signaled imply that all > points up to 3 are signaled, or does 3 not being signaled imply that all > points after 1 are not. If that's mentioned already somewhere, my bad. > If not, could you put the answer somewhere. > -Chris In [1, 3], if 1 is signaled, the timeline value is 1. And find_seqno(2) should return NULL. In the out_of_order selftest the chain was [1, 2, 3], 2 was signaled and the test was expecting no fence to be returned by find_seqno(2). But we still have to wait on 1 to complete before find_seqno(2) can return NULL (as in you don't have to wait on anything). Hope that answer the question. -Lionel From chris at chris-wilson.co.uk Thu Jun 25 13:23:22 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 14:23:22 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> Message-ID: <159309140216.31486.2359580281725596670@build.alporthouse.com> Quoting Christian K?nig (2020-06-25 13:59:16) > Am 25.06.20 um 14:48 schrieb Chris Wilson: > > Quoting Christian K?nig (2020-06-25 09:11:35) > >> Am 24.06.20 um 22:18 schrieb Chris Wilson: > >>> Quoting Dave Airlie (2020-06-24 20:04:02) > >>>> On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: > >>>>> Quoting Dave Airlie (2020-06-23 22:01:24) > >>>>>> On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: > >>>>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > >>>>>>>> Hi, Chris! > >>>>>>>> > >>>>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>>>>>>>> In order to actually handle eviction and what not, we need to process > >>>>>>>>> all the objects together under a common lock, reservation_ww_class. As > >>>>>>>>> such, do a memory reservation pass after looking up the object/vma, > >>>>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>>>>>>>> flushing and ofc execution]. > >>>>>>>>> > >>>>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>>>>>>>> --- > >>>>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>>>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>>>>>>>> > >>>>>>>> Which tree is this against? The series doesn't apply cleanly against > >>>>>>>> drm-tip? > >>>>>>> It's continuing on from the scheduler patches, the bug fixes and the > >>>>>>> iris-deferred-fence work. I thought throwing all of those old patches > >>>>>>> into the pile would have been distracting. > >>>>>>> > >>>>>>>> ... > >>>>>>>> > >>>>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>>>>>>>> +{ > >>>>>>>>> + const u64 idx = eb->context->timeline->fence_context; > >>>>>>>>> + struct ww_acquire_ctx acquire; > >>>>>>>>> + struct eb_vma *ev; > >>>>>>>>> + int err; > >>>>>>>>> + > >>>>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>>>>>>>> + if (!eb->mm_fence) > >>>>>>>>> + return -ENOMEM; > >>>>>>>> Where are the proxy fence functions defined? > >>>>>>> In dma-fence-proxy.c ;) > >>>>>> The dma-fence-proxy that Christian NAKed before? > >>>>> I do not have an email from Christian about dma-fence-proxy in the last > >>>>> 3 years it has been on the list. > >>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fdri-devel%2Faeb0373d-0583-d922-3b73-93668c27d177%40amd.com%2F&data=02%7C01%7Cchristian.koenig%40amd.com%7Ccb060e358d844784815708d819061868%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637286861292346372&sdata=DlHistmqPi%2BtwdcT%2FycrtRpoLGZ6xcBD%2FkPvVZcQ2YQ%3D&reserved=0 > >>> Darn, I skimmed the thread title and thought it was just about the > >>> timelines. > >>> > >>>> I'm assuming this was about patch 8 there which to me looks like proxy > >>>> fences but maybe by threading is off reading that. > >>> The deadlocks are easy to resolve. The fence is either signaled normally > >>> by userspace, they create a deadlock that is rejected by checking the dag > >>> and the fence signaled with an error (and work cancelled, error > >>> propagated back to userspace if they kept the output fence around), or > >>> userspace forgets entirely about the fence they were waiting on in which > >>> case it is signaled by closing the syncobjs [sadly not in error though, > >>> I hoping to report EPIPE] on process termination. > >> And exactly that concept is still a big NAK. > >> > >> The kernel memory management depends on dma_fences to be signaling as > >> soon as they are existing. > >> > >> Just imagine what Daniel's dependency patches would splat out when you > >> do something like this and correctly annotate the signaling code path. > > Nothing at all. Forward progress of the waiter does not solely depend on > > the signaler, just as in bc9c80fe01a2570a2fd78abbc492b377b5fda068. > > > >> Proxy fences, especially when they depend on userspace for signaling are > >> an absolutely NO-GO. > > We are in full control of the signaling and are able to cancel the pending > > userspace operation, move it off to one side and shutdown the HW, > > whatever. We can and do do dependency analysis of the fence contexts to > > avoid deadlocks, just as easily as detecting recursion. > > > > To claim that userspace is not already able to control signaling, is a > > false dichotomy. Userspace is fully able to lock the HW resources > > indefinitely (even if you cap every job, one can always build a chain of > > jobs to circumvent any imposed timeout, a couple of seconds timeout > > becomes several months of jobs before the GPU runs out of memory and is > > unable to accept any more jobs). Any ioctl that blocks while holding a HW > > resource renders itself liable to a user controllable livelock, you know > > this, because it is blocking the signaling of those earlier jobs. > > Worrying about things that are entirely within our control and hence > > avoidable, misses the point. > > You are completely missing the problem here. > > As you correctly pointed out that an userspace thread blocks on > something is perfectly acceptable. And that's how > bc9c80fe01a2570a2fd78abbc492b377b5fda068 works as well. > > And bc9c80fe01a2570a2fd78abbc492b377b5fda068 only implements waiting so > that during CS or WAIT IOCTL we can block for the fence to appear. > > > What happens in your approach is that the kernel starts to wait for > userspace in its memory reclaim path. That is exactly the kind of > problem Daniels patches now point out immediately. No we don't. -Chris From baolu.lu at linux.intel.com Thu Jun 25 13:24:00 2020 From: baolu.lu at linux.intel.com (Lu Baolu) Date: Thu, 25 Jun 2020 21:24:00 +0800 Subject: [Intel-gfx] [PATCH 02/13] iommu/vt-d: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-3-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> <20200625130836.1916-3-joro@8bytes.org> Message-ID: <1f6c3feb-d8b0-3ade-db2e-133f40874c30@linux.intel.com> Hi Joerg, On 2020/6/25 21:08, Joerg Roedel wrote: > From: Joerg Roedel <jroedel at suse.de> > > Remove the use of dev->archdata.iommu and use the private per-device > pointer provided by IOMMU core code instead. > > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- > .../gpu/drm/i915/selftests/mock_gem_device.c | 10 ++++++++-- > drivers/iommu/intel/iommu.c | 18 +++++++++--------- For changes in VT-d driver, Reviewed-by: Lu Baolu <baolu.lu at linux.intel.com> Best regards, baolu > 2 files changed, 17 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c > index 9b105b811f1f..e08601905a64 100644 > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c > @@ -24,6 +24,7 @@ > > #include <linux/pm_domain.h> > #include <linux/pm_runtime.h> > +#include <linux/iommu.h> > > #include <drm/drm_managed.h> > > @@ -118,6 +119,9 @@ struct drm_i915_private *mock_gem_device(void) > { > struct drm_i915_private *i915; > struct pci_dev *pdev; > +#if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU) > + struct dev_iommu iommu; > +#endif > int err; > > pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); > @@ -136,8 +140,10 @@ struct drm_i915_private *mock_gem_device(void) > dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); > > #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU) > - /* hack to disable iommu for the fake device; force identity mapping */ > - pdev->dev.archdata.iommu = (void *)-1; > + /* HACK HACK HACK to disable iommu for the fake device; force identity mapping */ > + memset(&iommu, 0, sizeof(iommu)); > + iommu.priv = (void *)-1; > + pdev->dev.iommu = &iommu; > #endif > > pci_set_drvdata(pdev, i915); > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index d759e7234e98..2ce490c2eab8 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -372,7 +372,7 @@ struct device_domain_info *get_domain_info(struct device *dev) > if (!dev) > return NULL; > > - info = dev->archdata.iommu; > + info = dev_iommu_priv_get(dev); > if (unlikely(info == DUMMY_DEVICE_DOMAIN_INFO || > info == DEFER_DEVICE_DOMAIN_INFO)) > return NULL; > @@ -743,12 +743,12 @@ struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, > > static int iommu_dummy(struct device *dev) > { > - return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; > + return dev_iommu_priv_get(dev) == DUMMY_DEVICE_DOMAIN_INFO; > } > > static bool attach_deferred(struct device *dev) > { > - return dev->archdata.iommu == DEFER_DEVICE_DOMAIN_INFO; > + return dev_iommu_priv_get(dev) == DEFER_DEVICE_DOMAIN_INFO; > } > > /** > @@ -2420,7 +2420,7 @@ static inline void unlink_domain_info(struct device_domain_info *info) > list_del(&info->link); > list_del(&info->global); > if (info->dev) > - info->dev->archdata.iommu = NULL; > + dev_iommu_priv_set(info->dev, NULL); > } > > static void domain_remove_dev_info(struct dmar_domain *domain) > @@ -2453,7 +2453,7 @@ static void do_deferred_attach(struct device *dev) > { > struct iommu_domain *domain; > > - dev->archdata.iommu = NULL; > + dev_iommu_priv_set(dev, NULL); > domain = iommu_get_domain_for_dev(dev); > if (domain) > intel_iommu_attach_device(domain, dev); > @@ -2599,7 +2599,7 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, > list_add(&info->link, &domain->devices); > list_add(&info->global, &device_domain_list); > if (dev) > - dev->archdata.iommu = info; > + dev_iommu_priv_set(dev, info); > spin_unlock_irqrestore(&device_domain_lock, flags); > > /* PASID table is mandatory for a PCI device in scalable mode. */ > @@ -4004,7 +4004,7 @@ static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) > if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) { > pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"); > add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); > - pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; > + dev_iommu_priv_set(&pdev->dev, DUMMY_DEVICE_DOMAIN_INFO); > } > } > DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); > @@ -4043,7 +4043,7 @@ static void __init init_no_remapping_devices(void) > drhd->ignored = 1; > for_each_active_dev_scope(drhd->devices, > drhd->devices_cnt, i, dev) > - dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; > + dev_iommu_priv_set(dev, DUMMY_DEVICE_DOMAIN_INFO); > } > } > } > @@ -5665,7 +5665,7 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev) > return ERR_PTR(-ENODEV); > > if (translation_pre_enabled(iommu)) > - dev->archdata.iommu = DEFER_DEVICE_DOMAIN_INFO; > + dev_iommu_priv_set(dev, DEFER_DEVICE_DOMAIN_INFO); > > return &iommu->iommu; > } > From jack at suse.cz Thu Jun 25 13:40:44 2020 From: jack at suse.cz (Jan Kara) Date: Thu, 25 Jun 2020 15:40:44 +0200 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200625114209.GA7703@casper.infradead.org> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200625114209.GA7703@casper.infradead.org> Message-ID: <20200625134044.GD17788@quack2.suse.cz> On Thu 25-06-20 12:42:09, Matthew Wilcox wrote: > On Wed, Jun 24, 2020 at 08:14:17PM +0100, Chris Wilson wrote: > > A side effect of the LRU shrinker not being dma aware is that we will > > often attempt to perform direct reclaim on the persistent group of dma > > pages while continuing to use the dma HW (an issue as the HW may already > > be actively waiting for the next user request), and even attempt to > > reclaim a partially allocated dma object in order to satisfy pinning > > the next user page for that object. > > > > It is to be expected that such pages are made available for reclaim at > > the end of the dma operation [unpin_user_pages()], and for truly > > longterm pins to be proactively recovered via device specific shrinkers > > [i.e. stop the HW, allow the pages to be returned to the system, and > > then compete again for the memory]. > > Why are DMA pinned pages still on the LRU list at all? I never got an > answer to this that made sense to me. By definition, a page which is > pinned for DMA is being accessed, and needs to at the very least change > position on the LRU list, so just take it off the list when DMA-pinned > and put it back on the list when DMA-unpinned. Well, we do mark_page_accessed() when pinning in GUP. This is not perfect but it's as good as it gets with CPU having no control when the page is actually accessed. Also taking the page off and then back to LRU list would increase the contention on the LRU list locks and generally cost performance so for short term pins it is not desirable... Otherwise I agree that conceptually it would make some sence although I'm not sure some places wouldn't get confused by e.g. page cache pages not being on LRU list. Honza -- Jan Kara <jack at suse.com> SUSE Labs, CR From chris at chris-wilson.co.uk Thu Jun 25 13:47:24 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 14:47:24 +0100 Subject: [Intel-gfx] [PATCH 2/2] dma-buf: fix dma-fence-chain out of order test In-Reply-To: <c6f72d4d-c8a0-c484-7c31-761e9c37b85e@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <20200625123443.19680-2-lionel.g.landwerlin@intel.com> <159309113252.4527.2883585204850736358@build.alporthouse.com> <c6f72d4d-c8a0-c484-7c31-761e9c37b85e@intel.com> Message-ID: <159309284429.31486.10956987302705466275@build.alporthouse.com> Quoting Lionel Landwerlin (2020-06-25 14:23:25) > On 25/06/2020 16:18, Chris Wilson wrote: > > Quoting Lionel Landwerlin (2020-06-25 13:34:43) > >> There was probably a misunderstand on how the dma-fence-chain is > >> supposed to work or what dma_fence_chain_find_seqno() is supposed to > >> return. > >> > >> dma_fence_chain_find_seqno() is here to give us the fence to wait upon > >> for a particular point in the timeline. The timeline progresses only > >> when all the points prior to a given number have completed. > > Hmm, the question was what point is it supposed to wait for. > > > > For the simple chain of [1, 3], does 1 being signaled imply that all > > points up to 3 are signaled, or does 3 not being signaled imply that all > > points after 1 are not. If that's mentioned already somewhere, my bad. > > If not, could you put the answer somewhere. > > -Chris > > In [1, 3], if 1 is signaled, the timeline value is 1. And find_seqno(2) > should return NULL. > > > In the out_of_order selftest the chain was [1, 2, 3], 2 was signaled and > the test was expecting no fence to be returned by find_seqno(2). > > But we still have to wait on 1 to complete before find_seqno(2) can > return NULL (as in you don't have to wait on anything). * scratches head I thought it was meant to be expecting fc.chain[1] to still be present as the chain at that point was not yet signaled. Oh well, a mistake compounded. :| -Chris From lionel.g.landwerlin at intel.com Thu Jun 25 13:56:13 2020 From: lionel.g.landwerlin at intel.com (Lionel Landwerlin) Date: Thu, 25 Jun 2020 16:56:13 +0300 Subject: [Intel-gfx] [PATCH 2/2] dma-buf: fix dma-fence-chain out of order test In-Reply-To: <159309284429.31486.10956987302705466275@build.alporthouse.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <20200625123443.19680-2-lionel.g.landwerlin@intel.com> <159309113252.4527.2883585204850736358@build.alporthouse.com> <c6f72d4d-c8a0-c484-7c31-761e9c37b85e@intel.com> <159309284429.31486.10956987302705466275@build.alporthouse.com> Message-ID: <9547eed6-c90f-5f3a-b30e-22bbe8f95645@intel.com> On 25/06/2020 16:47, Chris Wilson wrote: > Quoting Lionel Landwerlin (2020-06-25 14:23:25) >> On 25/06/2020 16:18, Chris Wilson wrote: >>> Quoting Lionel Landwerlin (2020-06-25 13:34:43) >>>> There was probably a misunderstand on how the dma-fence-chain is >>>> supposed to work or what dma_fence_chain_find_seqno() is supposed to >>>> return. >>>> >>>> dma_fence_chain_find_seqno() is here to give us the fence to wait upon >>>> for a particular point in the timeline. The timeline progresses only >>>> when all the points prior to a given number have completed. >>> Hmm, the question was what point is it supposed to wait for. >>> >>> For the simple chain of [1, 3], does 1 being signaled imply that all >>> points up to 3 are signaled, or does 3 not being signaled imply that all >>> points after 1 are not. If that's mentioned already somewhere, my bad. >>> If not, could you put the answer somewhere. >>> -Chris >> In [1, 3], if 1 is signaled, the timeline value is 1. And find_seqno(2) >> should return NULL. >> >> >> In the out_of_order selftest the chain was [1, 2, 3], 2 was signaled and >> the test was expecting no fence to be returned by find_seqno(2). >> >> But we still have to wait on 1 to complete before find_seqno(2) can >> return NULL (as in you don't have to wait on anything). > * scratches head > > I thought it was meant to be expecting fc.chain[1] to still be present > as the chain at that point was not yet signaled. You're right that the point is not yet signaled. But it doesn't need to stay in the chain if you can wait on a previous point. chain[1] gets removed as we walk the chain backward in dma_fence_chain_walk. -Lionel > > Oh well, a mistake compounded. :| > -Chris From daniel at ffwll.ch Thu Jun 25 13:59:34 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Thu, 25 Jun 2020 15:59:34 +0200 Subject: [Intel-gfx] [PATCH 2/2] dma-buf: fix dma-fence-chain out of order test In-Reply-To: <c6f72d4d-c8a0-c484-7c31-761e9c37b85e@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <20200625123443.19680-2-lionel.g.landwerlin@intel.com> <159309113252.4527.2883585204850736358@build.alporthouse.com> <c6f72d4d-c8a0-c484-7c31-761e9c37b85e@intel.com> Message-ID: <CAKMK7uHgwUQYLDPJnmTqcX1=UPuinifm+Y7+z-krSzqXpKXnow@mail.gmail.com> On Thu, Jun 25, 2020 at 3:23 PM Lionel Landwerlin <lionel.g.landwerlin at intel.com> wrote: > > On 25/06/2020 16:18, Chris Wilson wrote: > > Quoting Lionel Landwerlin (2020-06-25 13:34:43) > >> There was probably a misunderstand on how the dma-fence-chain is > >> supposed to work or what dma_fence_chain_find_seqno() is supposed to > >> return. > >> > >> dma_fence_chain_find_seqno() is here to give us the fence to wait upon > >> for a particular point in the timeline. The timeline progresses only > >> when all the points prior to a given number have completed. > > Hmm, the question was what point is it supposed to wait for. > > > > For the simple chain of [1, 3], does 1 being signaled imply that all > > points up to 3 are signaled, or does 3 not being signaled imply that all > > points after 1 are not. If that's mentioned already somewhere, my bad. > > If not, could you put the answer somewhere. > > -Chris > > In [1, 3], if 1 is signaled, the timeline value is 1. And find_seqno(2) > should return NULL. > > > In the out_of_order selftest the chain was [1, 2, 3], 2 was signaled and > the test was expecting no fence to be returned by find_seqno(2). > > But we still have to wait on 1 to complete before find_seqno(2) can > return NULL (as in you don't have to wait on anything). > > > Hope that answer the question. I asked Christian to document why timeline works like this, but I can't find it in the kerneldoc right now. If it's missing I think we should fix that and add the explanation, iirc it was around gpu reset creating too much havoc otherwise. -Daniel > > > -Lionel > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From thomas_os at shipmail.org Thu Jun 25 14:32:17 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Thu, 25 Jun 2020 16:32:17 +0200 Subject: [Intel-gfx] [PATCH 15/26] drm/i915: Make sure execbuffer always passes ww state to i915_vma_pin. In-Reply-To: <20200623142843.423594-15-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-15-maarten.lankhorst@linux.intel.com> Message-ID: <b320bbd2-3a81-d5dc-f629-dc9144c1d227@shipmail.org> Hi, Maarten, On 6/23/20 4:28 PM, Maarten Lankhorst wrote: > As a preparation step for full object locking and wait/wound handling > during pin and object mapping, ensure that we always pass the ww context > in i915_gem_execbuffer.c to i915_vma_pin, use lockdep to ensure this > happens. > > This also requires changing the order of eb_parse slightly, to ensure > we pass ww at a point where we could still handle -EDEADLK safely. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 138 ++++++++++-------- > drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 4 +- > drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +- > drivers/gpu/drm/i915/gt/intel_context.c | 65 ++++++--- > drivers/gpu/drm/i915/gt/intel_context.h | 13 ++ > drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- > drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +- > drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +- > drivers/gpu/drm/i915/gt/intel_ring.c | 10 +- > drivers/gpu/drm/i915/gt/intel_ring.h | 3 +- > .../gpu/drm/i915/gt/intel_ring_submission.c | 15 +- > drivers/gpu/drm/i915/gt/intel_timeline.c | 12 +- > drivers/gpu/drm/i915/gt/intel_timeline.h | 3 +- > drivers/gpu/drm/i915/gt/mock_engine.c | 3 +- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 2 +- > drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 +- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 13 +- > drivers/gpu/drm/i915/i915_gem.c | 11 +- > drivers/gpu/drm/i915/i915_vma.c | 13 +- > drivers/gpu/drm/i915/i915_vma.h | 13 +- > 25 files changed, 214 insertions(+), 134 deletions(-) > From a quick bisect, it appears this patch is what's causing the contention in execbuf, ./gem_exec_alignment --run-subtest pi-isolated /Thomas From sashal at kernel.org Thu Jun 25 14:53:56 2020 From: sashal at kernel.org (Sasha Levin) Date: Thu, 25 Jun 2020 14:53:56 +0000 Subject: [Intel-gfx] [PATCH v7 02/17] drm/i915: Clear the repeater bit on HDCP disable In-Reply-To: <20200623155907.22961-3-sean@poorly.run> References: <20200623155907.22961-3-sean@poorly.run> Message-ID: <20200625145357.49F55207BB@mail.kernel.org> Hi [This is an automated email] This commit has been processed because it contains a "Fixes:" tag fixing commit: ee5e5e7a5e0f ("drm/i915: Add HDCP framework + base implementation"). The bot has tested the following trees: v5.7.5, v5.4.48, v4.19.129. v5.7.5: Build OK! v5.4.48: Failed to apply! Possible dependencies: 692059318c0fc ("drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+") v4.19.129: Failed to apply! Possible dependencies: 0e39037b31655 ("drm/i915: Cache the error string") 16e4dd0342a80 ("drm/i915: Markup paired operations on wakerefs") 39e2f501c1b43 ("drm/i915: Split struct intel_context definition to its own header") 408bd91786665 ("drm/i915: extract intel_hdcp.h from intel_drv.h") 52c0fdb25c7c9 ("drm/i915: Replace global breadcrumbs with per-context interrupt tracking") 538ef96b9dae7 ("drm/i915/gem: Track the rpm wakerefs") 692059318c0fc ("drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+") 6b048706f407f ("drm/i915: Forcibly flush unwanted requests in drop-caches") 87f1ef225242d ("drm/i915: Record the sseu configuration per-context & engine") 95fd94a645f75 ("drm/i915: avoid rebuilding i915_gpu_error.o on version string updates") c0a6aa7ec2c36 ("drm/i915: Show actual alongside requested frequency in debugfs/i915_rps_boost_info") c2400ec3b6d15 ("drm/i915: add Makefile magic for testing headers are self-contained") c44301fce6146 ("drm/i915: Allow control of PSR at runtime through debugfs, v6") e0516e83640e1 ("drm/i915: Move sandybride pcode access to intel_sideband.c") e1ef734eaec54 ("drm/i915: make intel_frontbuffer.h self-contained") e6154e4cb8b0d ("drm/i915: Skip the ERR_PTR error state") eb8d0f5af4ec2 ("drm/i915: Remove GPU reset dependence on struct_mutex") fb6f0b64e455b ("drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture") NOTE: The patch will not be queued to stable trees until it is upstream. How should we proceed with this patch? -- Thanks Sasha From sashal at kernel.org Thu Jun 25 14:53:59 2020 From: sashal at kernel.org (Sasha Levin) Date: Thu, 25 Jun 2020 14:53:59 +0000 Subject: [Intel-gfx] [PATCH v7 01/17] drm/i915: Fix sha_text population code In-Reply-To: <20200623155907.22961-2-sean@poorly.run> References: <20200623155907.22961-2-sean@poorly.run> Message-ID: <20200625145400.6837B20857@mail.kernel.org> Hi [This is an automated email] This commit has been processed because it contains a "Fixes:" tag fixing commit: ee5e5e7a5e0f ("drm/i915: Add HDCP framework + base implementation"). The bot has tested the following trees: v5.7.5, v5.4.48, v4.19.129. v5.7.5: Build OK! v5.4.48: Failed to apply! Possible dependencies: 65833c463886f ("drm/i915/hdcp: conversion to struct drm_device based logging macros.") 667944ad77f19 ("drm/i915/hdcp: use intel_de_*() functions for register access") 692059318c0fc ("drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+") v4.19.129: Failed to apply! Possible dependencies: 04707f9716363 ("drm/i915: Initialize HDCP2.2") 09d56393c1d8d ("drm/i915: hdcp1.4 CP_IRQ handling and SW encryption tracking") 2f80d7bd8d93c ("drm/i915: drop all drmP.h includes") 33b7f3ee6e008 ("drm/i915: Add CRTC output format YCBCR 4:2:0") 340a44bef2342 ("drm/i915/icl: program MG_DP_MODE") 342ac601df642 ("drm/i915: hdcp_check_link only on CP_IRQ") 47658556da857 ("drm/i915/dp: Do not grab crtc modeset lock in intel_dp_detect()") 667944ad77f19 ("drm/i915/hdcp: use intel_de_*() functions for register access") 668b6c176c33f ("drm/i915: Add YCBCR 4:2:0/4:4:4 support for LSPCON") 7b610f1fbed2a ("drm/i915/dp: Add DSC params and DSC config to intel_crtc_state") 9055aac76589c ("drm/i915: MEI interface implementation") 9844bc87cb7a5 ("drm/i915/dp: Fix duplication of DEVICE_SERVICE_IRQ handling") bdc93fe0eb82f ("drm/i915/debugfs: hdcp capability of a sink") cbfa8ac835cb4 ("drm/i915/dp: Kill intel_dp->detect_done flag") d3dacc70797b8 ("drm/i915: wrapping all hdcp var into intel_hdcp") d5acd97f55711 ("drm/i915/dp: Use a local variable for intel_encoder *") d78aa650670d2 ("drm: Add drm/drm_util.h header file") de25eb7f3075f ("drm/i915: introduce dp_to_i915() helper") f106d1005ac72 ("drm/i915: Pullout the bksv read and validation") NOTE: The patch will not be queued to stable trees until it is upstream. How should we proceed with this patch? -- Thanks Sasha From chris at chris-wilson.co.uk Thu Jun 25 15:10:23 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 16:10:23 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> Message-ID: <159309782319.31486.530565133539052103@build.alporthouse.com> Quoting Christian K?nig (2020-06-25 15:02:41) > Am 25.06.20 um 15:23 schrieb Chris Wilson: > > Quoting Christian K?nig (2020-06-25 13:59:16) > >> Am 25.06.20 um 14:48 schrieb Chris Wilson: > >>> Quoting Christian K?nig (2020-06-25 09:11:35) > >>>> Am 24.06.20 um 22:18 schrieb Chris Wilson: > >>>>> Quoting Dave Airlie (2020-06-24 20:04:02) > >>>>>> On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: > >>>>>>> Quoting Dave Airlie (2020-06-23 22:01:24) > >>>>>>>> On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: > >>>>>>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) > >>>>>>>>>> Hi, Chris! > >>>>>>>>>> > >>>>>>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: > >>>>>>>>>>> In order to actually handle eviction and what not, we need to process > >>>>>>>>>>> all the objects together under a common lock, reservation_ww_class. As > >>>>>>>>>>> such, do a memory reservation pass after looking up the object/vma, > >>>>>>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, > >>>>>>>>>>> flushing and ofc execution]. > >>>>>>>>>>> > >>>>>>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > >>>>>>>>>>> --- > >>>>>>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- > >>>>>>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) > >>>>>>>>>>> > >>>>>>>>>> Which tree is this against? The series doesn't apply cleanly against > >>>>>>>>>> drm-tip? > >>>>>>>>> It's continuing on from the scheduler patches, the bug fixes and the > >>>>>>>>> iris-deferred-fence work. I thought throwing all of those old patches > >>>>>>>>> into the pile would have been distracting. > >>>>>>>>> > >>>>>>>>>> ... > >>>>>>>>>> > >>>>>>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) > >>>>>>>>>>> +{ > >>>>>>>>>>> + const u64 idx = eb->context->timeline->fence_context; > >>>>>>>>>>> + struct ww_acquire_ctx acquire; > >>>>>>>>>>> + struct eb_vma *ev; > >>>>>>>>>>> + int err; > >>>>>>>>>>> + > >>>>>>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); > >>>>>>>>>>> + if (!eb->mm_fence) > >>>>>>>>>>> + return -ENOMEM; > >>>>>>>>>> Where are the proxy fence functions defined? > >>>>>>>>> In dma-fence-proxy.c ;) > >>>>>>>> The dma-fence-proxy that Christian NAKed before? > >>>>>>> I do not have an email from Christian about dma-fence-proxy in the last > >>>>>>> 3 years it has been on the list. > >>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fdri-devel%2Faeb0373d-0583-d922-3b73-93668c27d177%40amd.com%2F&data=02%7C01%7Cchristian.koenig%40amd.com%7Ccb060e358d844784815708d819061868%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637286861292346372&sdata=DlHistmqPi%2BtwdcT%2FycrtRpoLGZ6xcBD%2FkPvVZcQ2YQ%3D&reserved=0 > >>>>> Darn, I skimmed the thread title and thought it was just about the > >>>>> timelines. > >>>>> > >>>>>> I'm assuming this was about patch 8 there which to me looks like proxy > >>>>>> fences but maybe by threading is off reading that. > >>>>> The deadlocks are easy to resolve. The fence is either signaled normally > >>>>> by userspace, they create a deadlock that is rejected by checking the dag > >>>>> and the fence signaled with an error (and work cancelled, error > >>>>> propagated back to userspace if they kept the output fence around), or > >>>>> userspace forgets entirely about the fence they were waiting on in which > >>>>> case it is signaled by closing the syncobjs [sadly not in error though, > >>>>> I hoping to report EPIPE] on process termination. > >>>> And exactly that concept is still a big NAK. > >>>> > >>>> The kernel memory management depends on dma_fences to be signaling as > >>>> soon as they are existing. > >>>> > >>>> Just imagine what Daniel's dependency patches would splat out when you > >>>> do something like this and correctly annotate the signaling code path. > >>> Nothing at all. Forward progress of the waiter does not solely depend on > >>> the signaler, just as in bc9c80fe01a2570a2fd78abbc492b377b5fda068. > >>> > >>>> Proxy fences, especially when they depend on userspace for signaling are > >>>> an absolutely NO-GO. > >>> We are in full control of the signaling and are able to cancel the pending > >>> userspace operation, move it off to one side and shutdown the HW, > >>> whatever. We can and do do dependency analysis of the fence contexts to > >>> avoid deadlocks, just as easily as detecting recursion. > >>> > >>> To claim that userspace is not already able to control signaling, is a > >>> false dichotomy. Userspace is fully able to lock the HW resources > >>> indefinitely (even if you cap every job, one can always build a chain of > >>> jobs to circumvent any imposed timeout, a couple of seconds timeout > >>> becomes several months of jobs before the GPU runs out of memory and is > >>> unable to accept any more jobs). Any ioctl that blocks while holding a HW > >>> resource renders itself liable to a user controllable livelock, you know > >>> this, because it is blocking the signaling of those earlier jobs. > >>> Worrying about things that are entirely within our control and hence > >>> avoidable, misses the point. > >> You are completely missing the problem here. > >> > >> As you correctly pointed out that an userspace thread blocks on > >> something is perfectly acceptable. And that's how > >> bc9c80fe01a2570a2fd78abbc492b377b5fda068 works as well. > >> > >> And bc9c80fe01a2570a2fd78abbc492b377b5fda068 only implements waiting so > >> that during CS or WAIT IOCTL we can block for the fence to appear. > >> > >> > >> What happens in your approach is that the kernel starts to wait for > >> userspace in its memory reclaim path. That is exactly the kind of > >> problem Daniels patches now point out immediately. > > No we don't. To be clear, adding a wait to direct reclaim incurs latency across the whole system, and attracts the ire of users and core developers alike. Having fielded the bug reports for that, we try to avoid any case where we would wait inside direct reclaim. We still do cause kswapd to wait if there's nothing else left to clean up. We also try to apply backpressure to client memory allocators directly; I would like to improve that path to have memory prioritisation. So I still consider direct reclaim latency to be a serious enough issue that a blanket recommendation should be: don't wait. > Well then Daniels patches are still missing that case :) We have the DAG of fences, we can use that information to avoid adding an implicit coupling between execution contexts. Borrowing lockdep for its heavily aliased chains, when we have the finegrained information available for scheduling to solve what is essentially a scheduling issue seems shallow. > See when signaling a fence depends userspace doing something, we > obviously insert circle dependencies between whatever userspace might do > in a kernel system call and the kernel reclaim path. > > That this can't work correctly is actually completely obvious if you see > it from this side. The waits are unbounded, indefinite or even just a matter of milliseconds; ergo you are not allowed to wait inside direct reclaim. Userspace dictates forward progress of signaling chains, worse if one client can indirectly manipulate another's progress; the entire kernel is inside that execution context. Totally agree on that. [But inside the kernel, we do have the information to track even implicit execution coupling inside the drivers, and where we don't have that information we have to assume it is outside of our control.] -Chris From mhocko at kernel.org Thu Jun 25 15:12:27 2020 From: mhocko at kernel.org (Michal Hocko) Date: Thu, 25 Jun 2020 17:12:27 +0200 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <159308284703.4527.16058577374955415124@build.alporthouse.com> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200625075725.GC1320@dhcp22.suse.cz> <159308284703.4527.16058577374955415124@build.alporthouse.com> Message-ID: <20200625151227.GP1320@dhcp22.suse.cz> On Thu 25-06-20 12:00:47, Chris Wilson wrote: > Quoting Michal Hocko (2020-06-25 08:57:25) > > On Wed 24-06-20 20:14:17, Chris Wilson wrote: > > > A general rule of thumb is that shrinkers should be fast and effective. > > > They are called from direct reclaim at the most incovenient of times when > > > the caller is waiting for a page. If we attempt to reclaim a page being > > > pinned for active dma [pin_user_pages()], we will incur far greater > > > latency than a normal anonymous page mapped multiple times. Worse the > > > page may be in use indefinitely by the HW and unable to be reclaimed > > > in a timely manner. > > > > > > A side effect of the LRU shrinker not being dma aware is that we will > > > often attempt to perform direct reclaim on the persistent group of dma > > > pages while continuing to use the dma HW (an issue as the HW may already > > > be actively waiting for the next user request), and even attempt to > > > reclaim a partially allocated dma object in order to satisfy pinning > > > the next user page for that object. > > > > You are talking about direct reclaim but this path is shared with the > > background reclaim. This is a bit confusing. Maybe you just want to > > outline the latency in the reclaim which is more noticeable in the > > direct reclaim to the userspace. This would be good to be clarified. > > > > How much memory are we talking about here btw? > > It depends. In theory, it is used sparingly. But it is under userspace > control, exposed via Vulkan, OpenGL, OpenCL, media and even old XShm. If > all goes to plan the application memory is only pinned for as long as the > HW is using it, but that is an indefinite period of time and an indefinite > amount of memory. There are provisions in place to impose upper limits > on how long an operation can last on the HW, and the mmu-notifier is > there to ensure we do unpin the memory on demand. However cancelling a > HW operation (which will result in data loss and often process > termination due to an unfortunate sequence of events when userspace > fails to recover) for a try_to_unmap on behalf of the LRU shrinker is not > a good choice. OK, thanks for the clarification. What and when should MM intervene to prevent potential OOM? [...] > > Btw. overall intention of the patch is not really clear to me. Do I get > > it right that this is going to reduce latency of the reclaim for pages > > that are not reclaimable anyway because they are pinned? If yes do we > > have any numbers for that. > > I can plug it into a microbenchmark ala cycletest to show the impact... > Memory filled with 64M gup objects, random utilisation of those with > the GPU; background process filling the pagecache with find /; reporting > the time difference from the expected expiry of a timer with the actual: > [On a Geminilake Atom-class processor with 8GiB, average of 5 runs, each > measuring mean latency for 20s -- mean is probably a really bad choice > here, we need 50/90/95/99] > > direct reclaim calling mmu-notifier: > gem_syslatency: cycles=2122, latency mean=1601.185us max=33572us > > skipping try_to_unmap_one with page_maybe_dma_pinned: > gem_syslatency: cycles=1965, latency mean=597.971us max=28462us > > Baseline (background find /; application touched all memory, but no HW > ops) > gem_syslatency: cycles=0, latency mean=6.695us max=77us > > Compare with the time to allocate a single THP against load: > > Baseline: > gem_syslatency: cycles=0, latency mean=1541.562us max=52196us > Direct reclaim calling mmu-notifier: > gem_syslatency: cycles=2115, latency mean=9050.930us max=396986us > page_maybe_dma_pinned skip: > gem_syslatency: cycles=2325, latency mean=7431.633us max=187960us > > Take with a massive pinch of salt. I expect, once I find the right > sequence, to reliably control the induced latency on the RT thread. > > But first, I have to look at why there's a correlation with HW load and > timer latency, even with steady state usage. That's quite surprising -- > ah, I had it left to PREEMPT_VOLUNTARY and this machine has to scan > every request submitted to HW. Just great. > > With PREEMPT: > Timer: > Base: gem_syslatency: cycles=0, latency mean=8.823us max=83us > Reclaim: gem_syslatency: cycles=2224, latency mean=79.308us max=4805us > Skip: gem_syslatency: cycles=2677, latency mean=70.306us max=4720us > > THP: > Base: gem_syslatency: cycles=0, latency mean=1993.693us max=201958us > Reclaim: gem_syslatency: cycles=1284, latency mean=2873.633us max=295962us > Skip: gem_syslatency: cycles=1809, latency mean=1991.509us max=261050us > > Earlier caveats notwithstanding; confidence in results still low. > > And refine the testing somewhat, if at the very least gather enough > samples for credible statistics. OK, so my understanding is that the overall impact is very low. So what is the primary motivation for the patch? Prevent from a pointless work - aka invoke the notifier? -- Michal Hocko SUSE Labs From michal at hardline.pl Thu Jun 25 15:27:56 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 17:27:56 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 1/8] tests/core_hotunplug: Duplicate debug messages in dmesg In-Reply-To: <20200622164415.30352-2-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-2-janusz.krzysztofik@linux.intel.com> Message-ID: <159309887614.186992.12805428537676828006@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:08) > The purpose of debug messages displayed by the test is to make > identification of a subtest phase that fails more easy. Since issues > exhibited by the test are mostly reported to dmesg, print those debug > messages to /dev/kmsg as well. I'm not a fan of spamming dmesg from IGT and I'd prefer if you add this logging to the kernel, but let's go over this case-by-case. > v2: rebase on upstream > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > --- > tests/core_hotunplug.c | 38 ++++++++++++++++++++++---------------- > 1 file changed, 22 insertions(+), 16 deletions(-) > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > index e03f3b945..826645b1f 100644 > --- a/tests/core_hotunplug.c > +++ b/tests/core_hotunplug.c > @@ -49,6 +49,12 @@ struct hotunplug { > > /* Helpers */ > > +#define local_debug(msg...) \ > +({ \ > + igt_debug("%s: %s\n", __func__, msg); \ > + igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ > +}) > + > static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) > { > int len; > @@ -68,9 +74,9 @@ static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) > close(priv->fd.sysfs_dev); > } > > -static void prepare(struct hotunplug *priv, char *buf, int buflen) > +static inline void prepare(struct hotunplug *priv, char *buf, int buflen) > { > - igt_debug("opening device\n"); > + local_debug("opening device"); [ 220.458370] [drm:drm_open] pid = 194, minor = 128 [ 220.460062] [drm:i915_gem_open [i915]] > priv->fd.drm = __drm_open_driver(DRIVER_ANY); > igt_assert(priv->fd.drm >= 0); > > @@ -137,14 +143,14 @@ static void bus_rescan(int fd_sysfs_bus) > close(fd_sysfs_bus); > } > > -static void healthcheck(void) > +static inline void healthcheck(void) > { > int fd_drm; > > /* device name may have changed, rebuild IGT device list */ > igt_devices_scan(true); > > - igt_debug("reopening the device\n"); > + local_debug("reopening the device"); Well, this is going to look the same as open, except closing it won't print drm_lastclose. [ 293.957567] [drm:drm_release] open_count = 2 [ 293.958805] [drm:drm_file_free.part.0] pid = 194, device = 0xe280, open_count = 2 > fd_drm = __drm_open_driver(DRIVER_ANY); > igt_abort_on_f(fd_drm < 0, "Device reopen failure"); > > @@ -181,13 +187,13 @@ static void unbind_rebind(void) > > prepare(&priv, buf, sizeof(buf)); > > - igt_debug("closing the device\n"); > + local_debug("closing the device"); [ 250.157568] [drm:drm_release] open_count = 1 [ 250.158807] [drm:drm_file_free.part.0] pid = 194, device = 0xe280, open_count = 1 [ 250.161183] [drm:drm_lastclose] [ 250.162312] [drm:drm_lastclose] driver lastclose completed > close(priv.fd.drm); > > - igt_debug("unbinding the driver from the device\n"); > + local_debug("unbinding the driver from the device"); > driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); [ 1553.868235] bus: 'event_source': remove device i915_0000_00_02.0 > > - igt_debug("rebinding the driver to the device\n"); > + local_debug("rebinding the driver to the device"); > driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); [ 1592.758219] bus: 'pci': driver_probe_device: matched device 0000:00:02.0 with driver i915 [ 1592.760543] bus: 'pci': really_probe: probing driver i915 with device 0000:00:02.0 (...bunch of i915 logs...) [ 203.961656] driver: 'i915': driver_bound: bound to device '0000:00:02.0' [ 203.966421] bus: 'pci': really_probe: bound device 0000:00:02.0 to driver i915 > > healthcheck(); > @@ -199,13 +205,13 @@ static void unplug_rescan(void) > > prepare(&priv, NULL, 0); > > - igt_debug("closing the device\n"); > + local_debug("closing the device"); > close(priv.fd.drm); > > - igt_debug("unplugging the device\n"); > + local_debug("unplugging the device"); > device_unplug(priv.fd.sysfs_dev); [ 60.664163] bus: 'pci': remove device 0000:00:02.0 > - igt_debug("recovering the device\n"); > + local_debug("recovering the device"); > bus_rescan(priv.fd.sysfs_bus); [ 97.384479] bus: 'pci': add device 0000:00:02.0 > > healthcheck(); > @@ -218,13 +224,13 @@ static void hotunbind_lateclose(void) > > prepare(&priv, buf, sizeof(buf)); > > - igt_debug("hot unbinding the driver from the device\n"); > + local_debug("hot unbinding the driver from the device"); > driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); > > - igt_debug("rebinding the driver to the device\n"); > + local_debug("rebinding the driver to the device"); > driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); > > - igt_debug("late closing the unbound device instance\n"); > + local_debug("late closing the unbound device instance"); > close(priv.fd.drm); Would it be possible to add extra logging allowing us to distinguish this from regular unbind on i915 side? > > healthcheck(); > @@ -236,13 +242,13 @@ static void hotunplug_lateclose(void) > > prepare(&priv, NULL, 0); > > - igt_debug("hot unplugging the device\n"); > + local_debug("hot unplugging the device"); > device_unplug(priv.fd.sysfs_dev); > > - igt_debug("recovering the device\n"); > + local_debug("recovering the device"); > bus_rescan(priv.fd.sysfs_bus); > > - igt_debug("late closing the removed device instance\n"); > + local_debug("late closing the removed device instance"); > close(priv.fd.drm); Same thing here. So, not including the hot unplug/unbind, I think the logging is already there. Also - note, the "driver core" logs are probably disabled on CI, but I still think that figuring out how to enable those from IGT (and letting the kernel just do its regular logging) rather than adding kmsg prints from userspace is a better approach. -Micha? > > healthcheck(); > -- > 2.21.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From christian.koenig at amd.com Thu Jun 25 15:47:09 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Thu, 25 Jun 2020 17:47:09 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159309782319.31486.530565133539052103@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> Message-ID: <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> Am 25.06.20 um 17:10 schrieb Chris Wilson: > We have the DAG of fences, we can use that information to avoid adding > an implicit coupling between execution contexts. No, we can't. And it sounds like you still have not understood the underlying problem. See this has nothing to do with the fences itself or their DAG. When you depend on userspace to do another submission so your fence can start processing you end up depending on whatever userspace does. This in turn means when userspace calls a system call (or does page fault) it is possible that this ends up in the reclaim code path. And while we want to avoid it both Daniel and I already discussed this multiple times and we agree it is still a must have to be able to do fence waits in the reclaim code path. So what happens is that you have a dependency between fence submission -> userspace -> reclaim path -> fence submission. And that is a circle dependency, no matter what your DAG looks like. In other words this whole approach does not work, is a clear NAK and I can only advise Dave to *not* merge it. Regards, Christian. From chris at chris-wilson.co.uk Thu Jun 25 15:48:24 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 16:48:24 +0100 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200625151227.GP1320@dhcp22.suse.cz> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200625075725.GC1320@dhcp22.suse.cz> <159308284703.4527.16058577374955415124@build.alporthouse.com> <20200625151227.GP1320@dhcp22.suse.cz> Message-ID: <159310010426.31486.12265756858860973914@build.alporthouse.com> Quoting Michal Hocko (2020-06-25 16:12:27) > On Thu 25-06-20 12:00:47, Chris Wilson wrote: > > Quoting Michal Hocko (2020-06-25 08:57:25) > > > On Wed 24-06-20 20:14:17, Chris Wilson wrote: > > > > A general rule of thumb is that shrinkers should be fast and effective. > > > > They are called from direct reclaim at the most incovenient of times when > > > > the caller is waiting for a page. If we attempt to reclaim a page being > > > > pinned for active dma [pin_user_pages()], we will incur far greater > > > > latency than a normal anonymous page mapped multiple times. Worse the > > > > page may be in use indefinitely by the HW and unable to be reclaimed > > > > in a timely manner. > > > > > > > > A side effect of the LRU shrinker not being dma aware is that we will > > > > often attempt to perform direct reclaim on the persistent group of dma > > > > pages while continuing to use the dma HW (an issue as the HW may already > > > > be actively waiting for the next user request), and even attempt to > > > > reclaim a partially allocated dma object in order to satisfy pinning > > > > the next user page for that object. > > > > > > You are talking about direct reclaim but this path is shared with the > > > background reclaim. This is a bit confusing. Maybe you just want to > > > outline the latency in the reclaim which is more noticeable in the > > > direct reclaim to the userspace. This would be good to be clarified. > > > > > > How much memory are we talking about here btw? > > > > It depends. In theory, it is used sparingly. But it is under userspace > > control, exposed via Vulkan, OpenGL, OpenCL, media and even old XShm. If > > all goes to plan the application memory is only pinned for as long as the > > HW is using it, but that is an indefinite period of time and an indefinite > > amount of memory. There are provisions in place to impose upper limits > > on how long an operation can last on the HW, and the mmu-notifier is > > there to ensure we do unpin the memory on demand. However cancelling a > > HW operation (which will result in data loss and often process > > termination due to an unfortunate sequence of events when userspace > > fails to recover) for a try_to_unmap on behalf of the LRU shrinker is not > > a good choice. > > OK, thanks for the clarification. What and when should MM intervene to > prevent potential OOM? Open to any and all suggestions. At the moment we have the shrinkers for direct reclaim and kswapd [though for direct reclaim we don't like touching active dma pages for the same reason] and the oom-notifier as a last resort. At the moment, we start trying to flush work from the gpu inside kswapd, but that tbh is not particularly effective. If we used kswapd as a signal for lowmemory, we could/should be more proactive in releasing work and returning dirty pages to shmemfs as soon as it is complete [normally retiring completed work is lazy and does not immediately drop dirty pages]. That would also suggest a complementary signal for when we can go back to being lazy again. We are also a bit too lax in applying backpressure. The focus has been on making sure one hog does not prevent an innocent client from accessing the HW. We use cond_synchronize_rcu() on a per-client basis if it appears we are allocating new requests too fast when allocations start failing. That is very probably too little too late. It does achieve the original goal of preventing a single client from submitting requests faster than we can retire them. But we have nothing for page allocations, other than trying to reclaim shmemfs allocations after a NORETRY failure, hoping to stave off the shrinker. [That fails miserably as we are never alone on the system, ofc.] A cgroups interface to restrict memory allocations on a per client basis has never quite materialised. Even then we have to assume the worse and overcommitting is the norm. > [...] > > > Btw. overall intention of the patch is not really clear to me. Do I get > > > it right that this is going to reduce latency of the reclaim for pages > > > that are not reclaimable anyway because they are pinned? If yes do we > > > have any numbers for that. > > > > I can plug it into a microbenchmark ala cycletest to show the impact... > > Memory filled with 64M gup objects, random utilisation of those with > > the GPU; background process filling the pagecache with find /; reporting > > the time difference from the expected expiry of a timer with the actual: > > [On a Geminilake Atom-class processor with 8GiB, average of 5 runs, each > > measuring mean latency for 20s -- mean is probably a really bad choice > > here, we need 50/90/95/99] > > > > direct reclaim calling mmu-notifier: > > gem_syslatency: cycles=2122, latency mean=1601.185us max=33572us > > > > skipping try_to_unmap_one with page_maybe_dma_pinned: > > gem_syslatency: cycles=1965, latency mean=597.971us max=28462us > > > > Baseline (background find /; application touched all memory, but no HW > > ops) > > gem_syslatency: cycles=0, latency mean=6.695us max=77us > > > > Compare with the time to allocate a single THP against load: > > > > Baseline: > > gem_syslatency: cycles=0, latency mean=1541.562us max=52196us > > Direct reclaim calling mmu-notifier: > > gem_syslatency: cycles=2115, latency mean=9050.930us max=396986us > > page_maybe_dma_pinned skip: > > gem_syslatency: cycles=2325, latency mean=7431.633us max=187960us > > > > Take with a massive pinch of salt. I expect, once I find the right > > sequence, to reliably control the induced latency on the RT thread. > > > > But first, I have to look at why there's a correlation with HW load and > > timer latency, even with steady state usage. That's quite surprising -- > > ah, I had it left to PREEMPT_VOLUNTARY and this machine has to scan > > every request submitted to HW. Just great. > > > > With PREEMPT: > > Timer: > > Base: gem_syslatency: cycles=0, latency mean=8.823us max=83us > > Reclaim: gem_syslatency: cycles=2224, latency mean=79.308us max=4805us > > Skip: gem_syslatency: cycles=2677, latency mean=70.306us max=4720us > > > > THP: > > Base: gem_syslatency: cycles=0, latency mean=1993.693us max=201958us > > Reclaim: gem_syslatency: cycles=1284, latency mean=2873.633us max=295962us > > Skip: gem_syslatency: cycles=1809, latency mean=1991.509us max=261050us > > > > Earlier caveats notwithstanding; confidence in results still low. > > > > And refine the testing somewhat, if at the very least gather enough > > samples for credible statistics. > > OK, so my understanding is that the overall impact is very low. So what > is the primary motivation for the patch? Prevent from a pointless work - > aka invoke the notifier? I'm working on capturing the worst cases :) I just need to find the way to consistently steer reclaim to hitting active gup objects. And then wrap that inside a timer, without it appearing too contrived. Does populating a [THP] mmap seems reasonable way to measure page allocation latency? -Chris From willy at infradead.org Thu Jun 25 16:05:22 2020 From: willy at infradead.org (Matthew Wilcox) Date: Thu, 25 Jun 2020 17:05:22 +0100 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200625134044.GD17788@quack2.suse.cz> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200625114209.GA7703@casper.infradead.org> <20200625134044.GD17788@quack2.suse.cz> Message-ID: <20200625160522.GD7703@casper.infradead.org> On Thu, Jun 25, 2020 at 03:40:44PM +0200, Jan Kara wrote: > On Thu 25-06-20 12:42:09, Matthew Wilcox wrote: > > Why are DMA pinned pages still on the LRU list at all? I never got an > > answer to this that made sense to me. By definition, a page which is > > pinned for DMA is being accessed, and needs to at the very least change > > position on the LRU list, so just take it off the list when DMA-pinned > > and put it back on the list when DMA-unpinned. > > Well, we do mark_page_accessed() when pinning in GUP. This is not perfect > but it's as good as it gets with CPU having no control when the page is > actually accessed. Also taking the page off and then back to LRU list would > increase the contention on the LRU list locks and generally cost > performance so for short term pins it is not desirable... Otherwise I agree > that conceptually it would make some sence although I'm not sure some > places wouldn't get confused by e.g. page cache pages not being on LRU > list. We could/should do what we do for mlocked pages: Documentation/vm/unevictable-lru.rst I think 'case five' is wrong and needs to be removed. Pinning is inappropriate for "I'm going to modify the page myself". From radhakrishna.sripada at intel.com Thu Jun 25 17:03:58 2020 From: radhakrishna.sripada at intel.com (Radhakrishna Sripada) Date: Thu, 25 Jun 2020 10:03:58 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: implement Wa_14011508470;gen12 In-Reply-To: <20200624215723.2316-1-matthew.s.atwood@intel.com> References: <20200624215723.2316-1-matthew.s.atwood@intel.com> Message-ID: <20200625170358.GA25333@InViCtUs> On Wed, Jun 24, 2020 at 02:57:23PM -0700, Matt Atwood wrote: Set the title to drm/i915/gen12: Impl... and let go the semicolon. > Update code to reflect recent bspec changes > > Bspec: 52890 > Bspec: 53508 > > Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> With the title fixed, Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++ > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 2 files changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index c3eeebadc0b8..22395be35364 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -6007,6 +6007,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > { > struct i915_power_domains *power_domains = &dev_priv->power_domains; > struct i915_power_well *well; > + u32 val; > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > > @@ -6043,6 +6044,13 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > > if (resume && dev_priv->csr.dmc_payload) > intel_csr_load_program(dev_priv); > + > + /* Wa_14011508470 */ > + if (IS_GEN(dev_priv, 12)) { > + val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | > + DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR; > + intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val); > + } > } > > static void icl_display_core_uninit(struct drm_i915_private *dev_priv) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 450564e28332..5344d20c9070 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8105,6 +8105,12 @@ enum hardware_error { > #define MASK_WAKEMEM (1 << 13) > #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) > > +#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) > +#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) > +#define DCPR_MASK_LPMODE REG_BIT(26) > +#define DCPR_SEND_RESP_IMM REG_BIT(25) > +#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) > + > #define SKL_DFSM _MMIO(0x51000) > #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) > #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) > -- > 2.21.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From airlied at gmail.com Thu Jun 25 17:13:20 2020 From: airlied at gmail.com (Dave Airlie) Date: Fri, 26 Jun 2020 03:13:20 +1000 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> Message-ID: <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> WTUF? How did this ever land in my tree, there is no ACK on this from anyone in core dma-buf, Intel team, clean your house up here, I'm going to have to ask you to stop Chris merging stuff without oversight, if this sort of thing happens, this is totally unacceptable. Dave. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Tested-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> Reviewed-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> On Thu, 25 Jun 2020 at 22:43, Christian K?nig <christian.koenig at amd.com> wrote: > > Am 25.06.20 um 14:34 schrieb Lionel Landwerlin: > > This reverts commit 5de376bb434f80a13138f0ebedc8351ab73d8b0d. > > > > This change breaks synchronization of a timeline. > > dma_fence_chain_find_seqno() might be a bit of a confusing name but > > this function is not trying to find a particular seqno, is supposed to > > give a fence to wait on for a particular point in the timeline. > > > > In a timeline, a particular value is reached when all the points up to > > and including that value have signaled. > > > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com> > > Reviewed-by: Christian K?nig <christian.koenig at amd.com> > > > --- > > drivers/dma-buf/dma-fence-chain.c | 7 ------- > > 1 file changed, 7 deletions(-) > > > > diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c > > index c435bbba851c..3d123502ff12 100644 > > --- a/drivers/dma-buf/dma-fence-chain.c > > +++ b/drivers/dma-buf/dma-fence-chain.c > > @@ -99,12 +99,6 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) > > return -EINVAL; > > > > dma_fence_chain_for_each(*pfence, &chain->base) { > > - if ((*pfence)->seqno < seqno) { /* already signaled */ > > - dma_fence_put(*pfence); > > - *pfence = NULL; > > - break; > > - } > > - > > if ((*pfence)->context != chain->base.context || > > to_dma_fence_chain(*pfence)->prev_seqno < seqno) > > break; > > @@ -228,7 +222,6 @@ EXPORT_SYMBOL(dma_fence_chain_ops); > > * @chain: the chain node to initialize > > * @prev: the previous fence > > * @fence: the current fence > > - * @seqno: the sequence number (syncpt) of the fence within the chain > > * > > * Initialize a new chain node and either start a new chain or add the node to > > * the existing chain of the previous fence. > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From airlied at gmail.com Thu Jun 25 17:22:55 2020 From: airlied at gmail.com (Dave Airlie) Date: Fri, 26 Jun 2020 03:22:55 +1000 Subject: [Intel-gfx] [PATCH] RFC: i915: Drop relocation support on Gen12+ In-Reply-To: <158891748855.5249.8585589207741654136@jlahtine-desk.ger.corp.intel.com> References: <20200507153600.314454-1-jason@jlekstrand.net> <158886626795.20858.1870213936656066157@build.alporthouse.com> <CAPM=9tyhj+KNDFdw1nk0GASwfY5dwq2kAcxQ4oSHMt2BNyycVw@mail.gmail.com> <158891748855.5249.8585589207741654136@jlahtine-desk.ger.corp.intel.com> Message-ID: <CAPM=9twKHxG6L35UQpWEiVXQSLKgH1BepE6uhxb+RjUh3UpAKw@mail.gmail.com> On Fri, 8 May 2020 at 15:58, Joonas Lahtinen <joonas.lahtinen at linux.intel.com> wrote: > > Quoting Dave Airlie (2020-05-07 21:27:27) > > On Fri, 8 May 2020 at 01:44, Chris Wilson <chris at chris-wilson.co.uk> wrote: > > > > > > Quoting Jason Ekstrand (2020-05-07 16:36:00) > > > > The Vulkan driver in Mesa for Intel hardware never uses relocations if > > > > it's running on a version of i915 that supports at least softpin which > > > > all versions of i915 supporting Gen12 do. On the OpenGL side, Gen12 is > > > > only supported by iris which never uses relocations. The older i965 > > > > driver in Mesa does use relocations but it only supports Intel hardware > > > > through Gen11 and has been deprecated for all hardware Gen9+. The entire > > > > relocation UAPI and related infrastructure, therefore, doesn't have any > > > > open-source userspace consumer starting with Gen12. > > > > > > > > Rejecting relocations starting with Gen12 has the benefit that we don't > > > > have to bother supporting it on platforms with local memory. Given how > > > > much CPU touching of memory is required for relocations, not having to > > > > do so on platforms where not all memory is directly CPU-accessible > > > > carries significant advantages. > > > > > > You are not supplying them, the kernel is not checking them [as they > > > don't exist], so there is no material benefit. The only question is > > > maintainability. > > > > > > How confident are you that you will never use them and rewrite the > > > media-driver? The code exists, will be tested, and can just as easily > > > expire with the rest of execbuffer2. > > > > From an upstream POV I say hell yes, if the hw isn't generally available yet, > > and the media-driver/intel-compute-runtime people are warned in advance, > > > > I'm all in on ripping it out for new GENs. > > There have been discussions with our media driver team about eliminating > any relocations, but today they are still being used. They have started > partially using soft-pinning, which is a great first step to that > direction. > > The compute driver does not rely on relocations, they use soft-pinning > everywhere and explicitly manage the address space. > > Be assured that I'm also in favor of eliminating relocations (just like > execbuffer2, userptr and couple other things), just that we still need > to have a functional stack before they can be dropped for new hardware. > > Like Chris mentioned, enough optimization have been put in the code so > that there is zero impact from the relocations to the exclusively > soft-pinning drivers. So the sole benefit would be being able to drop > the relocations code in the future when the Gen11 hardware has gone > exctinct and that is a worthy goal, too. > > But for now the feature is still needed for Gen12, so forcefully > disabling it is untimely. > I'm going to ask that this be revisited for DG1. DG1 is a discrete GPU,a brand new thing that in no way requires relocations. If relocations are required for legacy software, that software is being updated to add local memory support, relocations should be removed at the same time. The main reason for this is I believe a lot of effort is being put into making relocations faster and better that is impacting all over the i915 driver. instead of just fixing userspace to not require them anymore moving forward. I'd rather DG1 support gets upstream in a sane fashion without having to worry about how super-optimised the relocation paths are for some corner case userspace code that if it was part of the mesa project would have been updated by now. Dave. From matthew.s.atwood at intel.com Thu Jun 25 17:32:00 2020 From: matthew.s.atwood at intel.com (Matt Atwood) Date: Thu, 25 Jun 2020 10:32:00 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/tgl: Add Wa_1409371443 In-Reply-To: <20200602014910.13019-1-aditya.swarup@intel.com> References: <20200602014910.13019-1-aditya.swarup@intel.com> Message-ID: <20200625173200.GA22095@msatwood-mobl> On Mon, Jun 01, 2020 at 06:49:10PM -0700, Aditya Swarup wrote: > Set GMBUS0 Pin Pair Select to 1 at boot and each FLR exit. > Return GMBUS0 Pin Pair Select to 1 after GMBUS transactions are done. > > Cc: Michal Wajdeczko <michal.wajdeczko at intel.com> > Cc: Piotr Pi?rkowski <piotr.piorkowski at intel.com> > Cc: Matt Roper <matthew.d.roper at intel.com> > Cc: Jose Souza <jose.souza at intel.com> > Signed-off-by: Aditya Swarup <aditya.swarup at intel.com> > --- > drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c > index a8d119b6b45c..8dd5aa025c3f 100644 > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c > @@ -139,11 +139,19 @@ to_intel_gmbus(struct i2c_adapter *i2c) > return container_of(i2c, struct intel_gmbus, adapter); > } > > +static void gmbus0_wa_reset(struct drm_i915_private *dev_priv) > +{ > + intel_de_write(dev_priv, GMBUS0, 0 | GMBUS_PIN_PAIR_1); or'ing with 0 doesnt make sense here, did you mean something else? > +} > + > void > intel_gmbus_reset(struct drm_i915_private *dev_priv) > { > intel_de_write(dev_priv, GMBUS0, 0); > intel_de_write(dev_priv, GMBUS4, 0); > + /* Wa_1409371443: tgl[a0] */ > + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) > + gmbus0_wa_reset(dev_priv); > } > > static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, > @@ -299,6 +307,10 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter) > > if (IS_PINEVIEW(dev_priv)) > pnv_gmbus_clock_gating(dev_priv, true); > + > + /* Wa_1409371443: tgl[a0] */ > + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) > + gmbus0_wa_reset(dev_priv); > } > > static void > @@ -955,4 +967,8 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv) > bus = &dev_priv->gmbus[pin]; > i2c_del_adapter(&bus->adapter); > } > + > + /* Wa_1409371443: tgl[a0] */ > + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) > + gmbus0_wa_reset(dev_priv); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 578cfe11cbb9..a1640476cefb 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3337,6 +3337,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ > #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ > #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) > +#define GMBUS_PIN_PAIR_MASK REG_GENMASK(4, 0) > +#define GMBUS_PIN_PAIR_1 REG_FIELD_PREP(GMBUS_PIN_PAIR_MASK, 1) > > #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ > #define GMBUS_SW_CLR_INT (1 << 31) > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From matthew.s.atwood at intel.com Thu Jun 25 17:34:25 2020 From: matthew.s.atwood at intel.com (Matt Atwood) Date: Thu, 25 Jun 2020 10:34:25 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Extend Wa_14010685332 to all ICP+ PCH's In-Reply-To: <20200617180006.4130501-1-matthew.d.roper@intel.com> References: <20200617180006.4130501-1-matthew.d.roper@intel.com> Message-ID: <20200625173425.GB22095@msatwood-mobl> O Wed, Jun 17, 2020 at 11:00:06AM -0700, Matt Roper wrote: > This workaround now also applies to TGL and RKL, so extend the PCH test > to just capture everthing ICP and beyond. > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 8e823ba25f5f..923822343311 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2907,10 +2907,8 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > GEN3_IRQ_RESET(uncore, SDE); > > - /* Wa_14010685332:icl,jsl,ehl */ > - if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP || > - INTEL_PCH_TYPE(dev_priv) == PCH_JSP || > - INTEL_PCH_TYPE(dev_priv) == PCH_MCC) { > + /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */ > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > intel_uncore_rmw(uncore, SOUTH_CHICKEN1, > SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); > intel_uncore_rmw(uncore, SOUTH_CHICKEN1, > -- > 2.24.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Thu Jun 25 17:42:41 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Thu, 25 Jun 2020 18:42:41 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> Message-ID: <159310696106.31486.9034080828697272264@build.alporthouse.com> Quoting Christian K?nig (2020-06-25 16:47:09) > Am 25.06.20 um 17:10 schrieb Chris Wilson: > > We have the DAG of fences, we can use that information to avoid adding > > an implicit coupling between execution contexts. > > No, we can't. And it sounds like you still have not understood the > underlying problem. > > See this has nothing to do with the fences itself or their DAG. > > When you depend on userspace to do another submission so your fence can > start processing you end up depending on whatever userspace does. HW dependency on userspace is explicit in the ABI and client APIs, and the direct control userspace has over the HW. > This in turn means when userspace calls a system call (or does page > fault) it is possible that this ends up in the reclaim code path. We have both said the very same thing. > And while we want to avoid it both Daniel and I already discussed this > multiple times and we agree it is still a must have to be able to do > fence waits in the reclaim code path. But came to the opposite conclusion. For doing that wait harms the unrelated caller and the reclaim is opportunistic. There is no need for that caller to reclaim that page, when it can have any other. Why did you even choose that page to reclaim? Inducing latency in the caller is a bug, has been reported previously as a bug, and still considered a bug. [But at the end of the day, if the system is out of memory, then you have to pick a victim.] > So what happens is that you have a dependency between fence submission > -> userspace -> reclaim path -> fence submission. And that is a circle > dependency, no matter what your DAG looks like. Sigh. We have both said the very same thing. > In other words this whole approach does not work, is a clear NAK and I > can only advise Dave to *not* merge it. If you are talking about the proxy? Then it looks like this [if you insist on having that wait in the reclaim] 1. userspace submits request, waiting for the future 2. other thread that is due to signal, enters kernel, hits direct reclaim, waits for the future fence [because you insist on this when it is not necessary and is a unbounded latency issue for general cases], 1. times out vs 1. userspace submits wait-for-submit; blocks 2. other thread enters kernel and waits for reclaim on another arbitrary fence, or anything, could even be waiting for a signal from 1. 1. times out Userspace directly controls fence signaling. Any wait whatsoever could be a deadlock on a resource that is outside of our [immediate] control. Further if that wait is underneath a mutex or other semaphore that it can cause another client to contend with, it is now able to inject its deadlock into an witting partner. -Chris From michal at hardline.pl Thu Jun 25 19:23:16 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 21:23:16 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 2/8] tests/core_hotunplug: Use PCI device sysfs entry, not DRM In-Reply-To: <20200622164415.30352-3-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-3-janusz.krzysztofik@linux.intel.com> Message-ID: <159311299636.202818.1800731180873353345@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:09) > Future subtests may want to access PCI attributes of the device after > driver unbind. Refactor prepare() helper. > > v2: rebase on upstream > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > --- > tests/core_hotunplug.c | 68 +++++++++++++++++++++++++----------------- > 1 file changed, 40 insertions(+), 28 deletions(-) > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > index 826645b1f..35eba9b8a 100644 > --- a/tests/core_hotunplug.c > +++ b/tests/core_hotunplug.c > @@ -55,42 +55,54 @@ struct hotunplug { > igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ > }) > > -static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) > +static inline int prepare_common(struct hotunplug *priv) > { > - int len; > + int fd_sysfs_drm; > + > + local_debug("opening device"); > + priv->fd.drm = __drm_open_driver(DRIVER_ANY); > + igt_assert(priv->fd.drm >= 0); > + > + fd_sysfs_drm = igt_sysfs_open(priv->fd.drm); > + igt_assert(fd_sysfs_drm >= 0); > + > + return fd_sysfs_drm; > +} > + > +static inline void prepare_for_rebind(struct hotunplug *priv, > + char *buf, int buflen) > +{ > + int fd_sysfs_drm, len; > > igt_assert(buflen); > > - priv->fd.sysfs_drv = openat(priv->fd.sysfs_dev, "device/driver", > - O_DIRECTORY); > - igt_assert(priv->fd.sysfs_drv >= 0); > + fd_sysfs_drm = prepare_common(priv); > + > + priv->fd.sysfs_drv = openat(fd_sysfs_drm, "device/driver", O_DIRECTORY); > > - len = readlinkat(priv->fd.sysfs_dev, "device", buf, buflen - 1); > + len = readlinkat(fd_sysfs_drm, "device", buf, buflen - 1); > buf[len] = '\0'; > priv->dev_bus_addr = strrchr(buf, '/'); > - igt_assert(priv->dev_bus_addr++); > > - /* sysfs_dev no longer needed */ > - close(priv->fd.sysfs_dev); > + close(fd_sysfs_drm); > + > + igt_assert(priv->fd.sysfs_drv >= 0); > + igt_assert(priv->dev_bus_addr++); > } > > -static inline void prepare(struct hotunplug *priv, char *buf, int buflen) > +static inline void prepare_for_rescan(struct hotunplug *priv) > { > - local_debug("opening device"); > - priv->fd.drm = __drm_open_driver(DRIVER_ANY); > - igt_assert(priv->fd.drm >= 0); > + int fd_sysfs_drm = prepare_common(priv); > > - priv->fd.sysfs_dev = igt_sysfs_open(priv->fd.drm); > - igt_assert(priv->fd.sysfs_dev >= 0); > + priv->fd.sysfs_dev = openat(fd_sysfs_drm, "device", O_DIRECTORY); > > - if (buf) { > - prepare_for_unbind(priv, buf, buflen); > - } else { > - /* prepare for bus rescan */ > - priv->fd.sysfs_bus = openat(priv->fd.sysfs_dev, > - "device/subsystem", O_DIRECTORY); > - igt_assert(priv->fd.sysfs_bus >= 0); > - } > + priv->fd.sysfs_bus = openat(fd_sysfs_drm, "device/subsystem", > + O_DIRECTORY); > + > + close(fd_sysfs_drm); > + > + igt_assert(priv->fd.sysfs_dev >= 0); > + igt_assert(priv->fd.sysfs_bus >= 0); > } I find the lifecycle of hotunplug.fd.sysfs_* difficult to follow now... Would it be possible to keep the "prepare" step simpler and just open everything everytime? (perhaps closing and opening new ones when called multiple times?) Or do we need to have drv separate from bus/dev? -Micha? > > static const char *failure; > @@ -124,7 +136,7 @@ static void device_unplug(int fd_sysfs_dev) > { > failure = "Device unplug timeout!"; > igt_set_timeout(60, failure); > - igt_sysfs_set(fd_sysfs_dev, "device/remove", "1"); > + igt_sysfs_set(fd_sysfs_dev, "remove", "1"); > igt_reset_timeout(); > failure = NULL; > > @@ -185,7 +197,7 @@ static void unbind_rebind(void) > struct hotunplug priv; > char buf[PATH_MAX]; > > - prepare(&priv, buf, sizeof(buf)); > + prepare_for_rebind(&priv, buf, sizeof(buf)); > > local_debug("closing the device"); > close(priv.fd.drm); > @@ -203,7 +215,7 @@ static void unplug_rescan(void) > { > struct hotunplug priv; > > - prepare(&priv, NULL, 0); > + prepare_for_rescan(&priv); > > local_debug("closing the device"); > close(priv.fd.drm); > @@ -222,7 +234,7 @@ static void hotunbind_lateclose(void) > struct hotunplug priv; > char buf[PATH_MAX]; > > - prepare(&priv, buf, sizeof(buf)); > + prepare_for_rebind(&priv, buf, sizeof(buf)); > > local_debug("hot unbinding the driver from the device"); > driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); > @@ -240,7 +252,7 @@ static void hotunplug_lateclose(void) > { > struct hotunplug priv; > > - prepare(&priv, NULL, 0); > + prepare_for_rescan(&priv); > > local_debug("hot unplugging the device"); > device_unplug(priv.fd.sysfs_dev); > -- > 2.21.1 > > _______________________________________________ > igt-dev mailing list > igt-dev at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/igt-dev From jani.nikula at linux.intel.com Thu Jun 25 19:27:52 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Thu, 25 Jun 2020 22:27:52 +0300 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> Message-ID: <874kqzndxj.fsf@intel.com> On Fri, 26 Jun 2020, Dave Airlie <airlied at gmail.com> wrote: > WTUF? > > How did this ever land in my tree, there is no ACK on this from anyone > in core dma-buf, > > Intel team, clean your house up here, I'm going to have to ask you to > stop Chris merging stuff without oversight, if this sort of thing > happens, this is totally unacceptable. There's no argument, an ack is required. In fairness to the i915 maintainers, though, this particular commit was merged via drm-misc-next [1]. As a side note, there seem to be extra checks in place for acks when applying non-i915 patches to drm-intel; there are no such checks for drm-misc. BR, Jani. [1] http://lore.kernel.org/r/20200414090738.GA16827 at linux-uq9g > > Dave. > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Tested-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> > Reviewed-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> > > > On Thu, 25 Jun 2020 at 22:43, Christian K?nig <christian.koenig at amd.com> wrote: >> >> Am 25.06.20 um 14:34 schrieb Lionel Landwerlin: >> > This reverts commit 5de376bb434f80a13138f0ebedc8351ab73d8b0d. >> > >> > This change breaks synchronization of a timeline. >> > dma_fence_chain_find_seqno() might be a bit of a confusing name but >> > this function is not trying to find a particular seqno, is supposed to >> > give a fence to wait on for a particular point in the timeline. >> > >> > In a timeline, a particular value is reached when all the points up to >> > and including that value have signaled. >> > >> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com> >> >> Reviewed-by: Christian K?nig <christian.koenig at amd.com> >> >> > --- >> > drivers/dma-buf/dma-fence-chain.c | 7 ------- >> > 1 file changed, 7 deletions(-) >> > >> > diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c >> > index c435bbba851c..3d123502ff12 100644 >> > --- a/drivers/dma-buf/dma-fence-chain.c >> > +++ b/drivers/dma-buf/dma-fence-chain.c >> > @@ -99,12 +99,6 @@ int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) >> > return -EINVAL; >> > >> > dma_fence_chain_for_each(*pfence, &chain->base) { >> > - if ((*pfence)->seqno < seqno) { /* already signaled */ >> > - dma_fence_put(*pfence); >> > - *pfence = NULL; >> > - break; >> > - } >> > - >> > if ((*pfence)->context != chain->base.context || >> > to_dma_fence_chain(*pfence)->prev_seqno < seqno) >> > break; >> > @@ -228,7 +222,6 @@ EXPORT_SYMBOL(dma_fence_chain_ops); >> > * @chain: the chain node to initialize >> > * @prev: the previous fence >> > * @fence: the current fence >> > - * @seqno: the sequence number (syncpt) of the fence within the chain >> > * >> > * Initialize a new chain node and either start a new chain or add the node to >> > * the existing chain of the previous fence. >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center From michal at hardline.pl Thu Jun 25 19:32:37 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 21:32:37 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 3/8] tests/core_hotunplug: Add unbind-unplug-rescan variant In-Reply-To: <20200622164415.30352-4-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-4-janusz.krzysztofik@linux.intel.com> Message-ID: <159311355771.202818.11936703389418397996@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:10) > Check if this 3-step procedure exhibits any issues with device recover > after unplug. Such issues may indicate insufficient device hardware > re-initialization performed by the device driver, or other kernel bugs > outside the driver code. > > v2: rebase on upstream > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> After addressing comments from preceding patches: Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> -Micha? > --- > tests/core_hotunplug.c | 40 ++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 38 insertions(+), 2 deletions(-) From michal at hardline.pl Thu Jun 25 19:39:39 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 21:39:39 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 4/8] tests/core_hotunplug: Add 'lateclose before recover' variants In-Reply-To: <20200622164415.30352-5-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-5-janusz.krzysztofik@linux.intel.com> Message-ID: <159311397998.202818.15659222080838800847@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:11) > If a GPU gets wedged during driver rebind or device re-plug for some > reason, current hotunbind/hotunplug test variants may time out before > lateclose phase, resulting in incomplete CI reports. Let's rename > those variants to more adequate hotrebind/hotreplug-lateclose and add > new variants focused on exercising the lateclose phase regardless of > potential rebind/re-plug issues under old names. > > v2: rebase on upstream > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> After addressing comments from preceding patches: Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> -Micha? > --- > tests/core_hotunplug.c | 57 +++++++++++++++++++++++++++++++++++++++--- > 1 file changed, 54 insertions(+), 3 deletions(-) From michal at hardline.pl Thu Jun 25 19:42:46 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 21:42:46 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 5/8] tests/core_hotunplug: Add 'GEM address space' variant In-Reply-To: <20200622164415.30352-6-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-6-janusz.krzysztofik@linux.intel.com> Message-ID: <159311416692.202818.5204035808205731710@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:12) > Verify if an additional address space associated with an open device > file descriptor is cleaned up correctly on device hotunplug. > > v2: rebase on upstream, update includes order > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > --- > tests/core_hotunplug.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > index 0892e1927..18a963564 100644 > --- a/tests/core_hotunplug.c > +++ b/tests/core_hotunplug.c > @@ -30,6 +30,7 @@ > #include <unistd.h> > > #include "i915/gem.h" > +#include "i915/gem_vm.h" > #include "igt.h" > #include "igt_device_scan.h" > #include "igt_kmod.h" > @@ -332,6 +333,29 @@ static void hotreplug_lateclose(void) > healthcheck(); > } > > +static void vm_hotunplug_lateclose(void) > +{ > + struct hotunplug priv; > + > + prepare_for_rescan(&priv); > + > + gem_require_vm(priv.fd.drm); > + > + local_debug("creating additional GEM user address space"); > + igt_ignore_warn(gem_vm_create(priv.fd.drm)); Why the "ignore_warn"? This deserves a comment. And perhaps a word of information about why we picked this partucular operation in the commit message (vm_create). This is a regression test, right? LGTM otherwise (but again - see previous patches): Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> -Micha? From jose.souza at intel.com Thu Jun 25 19:52:52 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Thu, 25 Jun 2020 12:52:52 -0700 Subject: [Intel-gfx] [PATCH v3] drm/i915/display: Implement new combo phy initialization step Message-ID: <20200625195252.39312-1-jose.souza@intel.com> This is new step that was recently added to the combo phy initialization. v2: - using intel_de_rmw() v3: - going back to read() modify and write() as group register can't be read BSpec: 49291 Cc: Clinton A Taylor <clinton.a.taylor at intel.com> Cc: Lucas De Marchi <lucas.demarchi at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- .../gpu/drm/i915/display/intel_combo_phy.c | 25 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 9 +++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 77b04bb3ec62..eccaa79cb4a9 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -264,6 +264,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, if (!icl_combo_phy_enabled(dev_priv, phy)) return false; + if (INTEL_GEN(dev_priv) >= 12) { + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy), + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, + ICL_PORT_TX_DW8_ODCC_CLK_SEL | + ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); + + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy), + DCC_MODE_SELECT_MASK, + DCC_MODE_SELECT_CONTINUOSLY); + } + ret = cnl_verify_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { @@ -375,6 +387,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); skip_phy_misc: + if (INTEL_GEN(dev_priv) >= 12) { + val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy)); + val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK; + val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL; + val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2; + intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); + + val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); + val &= ~DCC_MODE_SELECT_MASK; + val |= DCC_MODE_SELECT_CONTINUOSLY; + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); + } + cnl_set_procmon_ref_values(dev_priv, phy); if (phy_is_master(dev_priv, phy)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..ecac9adb1151 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1974,6 +1974,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) #define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) +#define DCC_MODE_SELECT_MASK (0x3 << 20) +#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) #define COMMON_KEEPER_EN (1 << 26) #define LATENCY_OPTIM_MASK (0x3 << 2) #define LATENCY_OPTIM_VAL(x) ((x) << 2) @@ -2072,6 +2074,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) +#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy)) +#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) +#define ICL_PORT_TX_DW8_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy)) +#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) + #define _ICL_DPHY_CHKN_REG 0x194 #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) -- 2.27.0 From michal at hardline.pl Thu Jun 25 19:51:24 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 21:51:24 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 6/8] tests/core_hotunplug: Add 'GEM object' variant In-Reply-To: <20200622164415.30352-7-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-7-janusz.krzysztofik@linux.intel.com> Message-ID: <159311468453.202818.18055756190300144808@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:13) > GEM objects belonging to user file descriptors still open on device > hotunplug may exhibit still more driver issues. Add a subtest that > implements this scenario. > > v2: rebase on upstream > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > --- > tests/core_hotunplug.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > index 18a963564..c30d98a69 100644 > --- a/tests/core_hotunplug.c > +++ b/tests/core_hotunplug.c > @@ -356,6 +356,29 @@ static void vm_hotunplug_lateclose(void) > healthcheck(); > } > > +static void gem_hotunplug_lateclose(void) > +{ > + struct hotunplug priv; > + > + prepare_for_rescan(&priv); > + > + igt_require_gem(priv.fd.drm); > + > + local_debug("creating a GEM user object"); > + igt_ignore_warn(gem_create(priv.fd.drm, 4096)); Same as previous one. (note - we could just check for proper error when we attempt to close this handle after unplug, and the same thing applies to the previous one with the vm) LGTM otherwise. Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> -Micha? From daniel at ffwll.ch Thu Jun 25 19:54:16 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Thu, 25 Jun 2020 21:54:16 +0200 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <874kqzndxj.fsf@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> <874kqzndxj.fsf@intel.com> Message-ID: <CAKMK7uErpxoFrT_K==7-PMGyg_eqF07T50eYfh5BFQLzra7TbQ@mail.gmail.com> Ignoring everything else ... On Thu, Jun 25, 2020 at 9:28 PM Jani Nikula <jani.nikula at linux.intel.com> wrote: > As a side note, there seem to be extra checks in place for acks when > applying non-i915 patches to drm-intel; there are no such checks for > drm-misc. One option to generalize that that I pondered is to consult get_maintainers.pl asking for git repo link, and if that returns something else, then insist that there's an ack from a relevant maintainer. It's a bit of typing, but I think the bigger problem is that there's a ton of false positives. But maybe that's a good thing, would give some motivation to keep MAINTAINERS updated. The other issue is though that drm-misc is plenty used to merge patches even when the respective maintainers are absent for weeks, or unresponsive. If we just blindly implement that rule, then the only possible Ack for these would be Dave&me as subsystem maintainers, and I don't want to be in the business of stamping approvals for all this stuff. Much better if people just collaborate. So I think an ack check would be nice, but probably not practical. Plus in this situation here drm-misc.git actually is the main repo, and we wont ever be able to teach a script to make a judgement call of whether that patch has the right amount of review on it. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From michal at hardline.pl Thu Jun 25 19:57:08 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 21:57:08 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 7/8] tests/core_hotunplug: Add 'PRIME handle' variant In-Reply-To: <20200622164415.30352-8-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-8-janusz.krzysztofik@linux.intel.com> Message-ID: <159311502818.202818.9312691111674456282@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:14) > Even if all device file descriptors are closed on device hotunplug, > PRIME exported objects may still exists, referenced by still open > dma-buf file handles. Add a subtest that keeps such handle open on > device hotunplug. > > v2: rebase on upstream Would be interesting to see what happens when someone actually imports an object from unplugged device (or the device is unplugged after it was imported). But perhaps that's something for the future. Also - the naming should probably be kept distinct from the other "lateclose" tests, since here we're closing the device FD before the unplug. Maybe just "prime-hotunplug"? But that's up to you - either way: Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> -Micha? > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > --- > tests/core_hotunplug.c | 36 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > index c30d98a69..7cb699cc2 100644 > --- a/tests/core_hotunplug.c > +++ b/tests/core_hotunplug.c > @@ -379,6 +379,35 @@ static void gem_hotunplug_lateclose(void) > healthcheck(); > } > > +static void prime_hotunplug_lateclose(void) > +{ > + struct hotunplug priv; > + uint32_t handle; > + int dmabuf; > + > + prepare_for_rescan(&priv); > + > + igt_require_gem(priv.fd.drm); > + > + local_debug("creating and PRIME-exporting a GEM object"); > + handle = gem_create(priv.fd.drm, 4096); > + dmabuf = prime_handle_to_fd(priv.fd.drm, handle); > + > + local_debug("closing the device"); > + close(priv.fd.drm); > + > + local_debug("hot unplugging the device"); > + device_unplug(priv.fd.sysfs_dev); > + > + local_debug("late closing the PRIME file handle"); > + close(dmabuf); > + > + local_debug("recovering the device"); > + bus_rescan(priv.fd.sysfs_bus); > + > + healthcheck(); > +} > + > /* Main */ > > igt_main > @@ -465,4 +494,11 @@ igt_main > > igt_fixture > igt_abort_on_f(failure, "%s\n", failure); > + > + igt_describe("Check if a device with a still open PRIME-exported object can be cleanly unplugged, then released and recovered"); > + igt_subtest("prime-hotunplug-lateclose") > + prime_hotunplug_lateclose(); > + > + igt_fixture > + igt_abort_on_f(failure, "%s\n", failure); > } > -- > 2.21.1 > > _______________________________________________ > igt-dev mailing list > igt-dev at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/igt-dev From ville.syrjala at linux.intel.com Thu Jun 25 20:00:03 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Thu, 25 Jun 2020 23:00:03 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec Message-ID: <20200625200003.12436-1-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> The linetime watermark is a 9 bit value, which gives us a maximum linetime of just below 64 usec. If the linetime exceeds that value we currently just discard the high bits and program the rest into the register, which angers the state checker. To avoid that let's just clamp the value to the max. I believe it should be perfectly fine to program a smaller linetime wm than strictly required, just means the hardware may fetch data sooner than strictly needed. We are further reassured by the fact that with DRRS the spec tells us to program the smaller of the two linetimes corresponding to the two refresh rates. Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a11bb675f9b3..d486d675166f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + int linetime_wm; if (!crtc_state->hw.enable) return 0; - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - adjusted_mode->crtc_clock); + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + adjusted_mode->crtc_clock); + + return min(linetime_wm, 0x1ff); } static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + int linetime_wm; if (!crtc_state->hw.enable) return 0; - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, - cdclk_state->logical.cdclk); + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + cdclk_state->logical.cdclk); + + return min(linetime_wm, 0x1ff); } static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - u16 linetime_wm; + int linetime_wm; if (!crtc_state->hw.enable) return 0; @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) linetime_wm /= 2; - return linetime_wm; + return min(linetime_wm, 0x1ff); } static int hsw_compute_linetime_wm(struct intel_atomic_state *state, -- 2.26.2 From michal at hardline.pl Thu Jun 25 20:02:11 2020 From: michal at hardline.pl (=?utf-8?q?Micha=C5=82?= Winiarski) Date: Thu, 25 Jun 2020 22:02:11 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 8/8] tests/core_hotunplug: Add 'GEM batch' variant In-Reply-To: <20200622164415.30352-9-janusz.krzysztofik@linux.intel.com> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-9-janusz.krzysztofik@linux.intel.com> Message-ID: <159311533123.202818.8673731295694520597@macragge.hardline.pl> Quoting Janusz Krzysztofik (2020-06-22 18:44:15) > Verify if a device with a GEM batch job still running on a GPU can be > hot-unplugged cleanly and released, then recovered. > > v2: rebase on upstream > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > --- > tests/core_hotunplug.c | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > index 7cb699cc2..672ff661d 100644 > --- a/tests/core_hotunplug.c > +++ b/tests/core_hotunplug.c > @@ -33,6 +33,7 @@ > #include "i915/gem_vm.h" > #include "igt.h" > #include "igt_device_scan.h" > +#include "igt_dummyload.h" > #include "igt_kmod.h" > #include "igt_sysfs.h" > > @@ -408,6 +409,32 @@ static void prime_hotunplug_lateclose(void) > healthcheck(); > } > > +static void batch_hotunplug_lateclose(void) > +{ > + struct hotunplug priv; > + igt_spin_t *spin; > + > + prepare_for_rescan(&priv); > + > + igt_require_gem(priv.fd.drm); > + > + local_debug("running dummy load"); > + spin = __igt_spin_new(priv.fd.drm, .flags = IGT_SPIN_POLL_RUN | > + IGT_SPIN_NO_PREEMPTION); Do we need IGT_SPIN_NO_PREEMPTION here? We're also leaking spin here... And I don't think we can just call igt_spin_free after unplug, can we? -Micha? > + igt_spin_busywait_until_started(spin); > + > + local_debug("hot unplugging the device"); > + device_unplug(priv.fd.sysfs_dev); > + > + local_debug("late closing the removed device instance"); > + close(priv.fd.drm); > + > + local_debug("recovering the device"); > + bus_rescan(priv.fd.sysfs_bus); > + > + healthcheck(); > +} > + > /* Main */ > > igt_main > @@ -501,4 +528,11 @@ igt_main > > igt_fixture > igt_abort_on_f(failure, "%s\n", failure); > + > + igt_describe("Check if a device with a still running batch can be cleanly unplugged, then released and recovered"); > + igt_subtest("batch-hotunplug-lateclose") > + batch_hotunplug_lateclose(); > + > + igt_fixture > + igt_abort_on_f(failure, "%s\n", failure); > } > -- > 2.21.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From imre.deak at intel.com Thu Jun 25 21:06:52 2020 From: imre.deak at intel.com (Imre Deak) Date: Fri, 26 Jun 2020 00:06:52 +0300 Subject: [Intel-gfx] [PATCH 6/7] drm/i915: Fix DP_TRAIN_MAX_{PRE_EMPHASIS, SWING}_REACHED handling In-Reply-To: <20200512174145.3186-7-ville.syrjala@linux.intel.com> References: <20200512174145.3186-1-ville.syrjala@linux.intel.com> <20200512174145.3186-7-ville.syrjala@linux.intel.com> Message-ID: <20200625210652.GA18750@ideak-desk.fi.intel.com> On Tue, May 12, 2020 at 08:41:44PM +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > The DP spec says: > "The transmitter shall support at least three levels of voltage > swing (Levels 0, 1, and 2). > > If only three levels of voltage swing are supported (VOLTAGE > SWING SET field (bits 1:0) are programmed to 10 (Level 2)), > this bit shall be set to 1, and cleared in all other cases. > > If all four levels of voltage swing are supported (VOLTAGE > SWING SET field (bits 1:0) are programmed to 11 (Level 3)), > this bit shall be set to 1,and cleared in all other cases." > > Let's follow that exactly instead of the current apporach > where we can set those also for vswing/preemph levels 0 or 1 > (or 2 when the platform max is 3). > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> Yep, so the sink could've incorrectly stopped asking for higher vswing levels after it asked for 0 vs+2 pe, when the max vs is 2 for instance. Matches the spec: Reviewed-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 573f93779449..aa7af531bcb8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -72,8 +72,9 @@ void intel_dp_get_adjust_train(struct intel_dp *intel_dp, > if (p >= preemph_max) > p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; > > - voltage_max = min(intel_dp->voltage_max(intel_dp), > - dp_voltage_max(p)); > + v = min(v, dp_voltage_max(p)); > + > + voltage_max = intel_dp->voltage_max(intel_dp); > if (v >= voltage_max) > v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; > > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From ville.syrjala at linux.intel.com Thu Jun 25 21:26:22 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 26 Jun 2020 00:26:22 +0300 Subject: [Intel-gfx] [PATCH v3 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200624221108.10038-1-manasi.d.navare@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> Message-ID: <20200625212622.GW6112@intel.com> On Wed, Jun 24, 2020 at 03:11:07PM -0700, Manasi Navare wrote: > Modify the helper to add a fixed delay or poll with timeout > based on platform specification to check for either Idle bit > set (DDI_BUF_CTL is idle for disable case) > > v2: > * Use 2 separate functions or idle and active (Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > 1 file changed, 8 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 884b507c5f55..7d5c8ab88fc4 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > enum port port) > { > - i915_reg_t reg = DDI_BUF_CTL(port); > - int i; > - > - for (i = 0; i < 16; i++) { > - udelay(1); > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > - return; > + if (IS_BROXTON(dev_priv)) { > + udelay(16); > + return; > } > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > - port_name(port)); > + > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 600)) Why 600? > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > + port_name(port)); > } > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > -- > 2.19.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Thu Jun 25 21:28:53 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 26 Jun 2020 00:28:53 +0300 Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200624221108.10038-2-manasi.d.navare@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> <20200624221108.10038-2-manasi.d.navare@intel.com> Message-ID: <20200625212853.GX6112@intel.com> On Wed, Jun 24, 2020 at 03:11:08PM -0700, Manasi Navare wrote: > Based on the platform, Bspec expects us to wait or poll with > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > after enabling DDI_BUF_CTL. > > v3: > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > v2: > * Based on platform, fixed delay or poll (Ville) > * Use a helper to do this (Imre, Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 7d5c8ab88fc4..ff6b1e9d1b4e 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > port_name(port)); > } > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > + enum port port) > +{ > + if (INTEL_GEN(dev_priv) <= 9) { Didn't we want the poll approach for glk+? > + usleep_range(600, 1000); > + return; > + } > + > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 600)) > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > + port_name(port)); > +} > + > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > { > switch (pll->info->id) { > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > - udelay(600); > + intel_wait_ddi_buf_active(dev_priv, port); Missed the FDI case. Also we're still missing this for HDMI, on icl+ I think? Can't quite remember if that was where the spec started to demand it. > } > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > -- > 2.19.1 -- Ville Syrj?l? Intel From jose.souza at intel.com Thu Jun 25 21:41:05 2020 From: jose.souza at intel.com (Souza, Jose) Date: Thu, 25 Jun 2020 21:41:05 +0000 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Add PSR2 software tracking registers In-Reply-To: <9b14efe375bb34a2dd59b45ea747dda514b38161.camel@intel.com> References: <20200526221447.64110-1-jose.souza@intel.com> <20200526221447.64110-4-jose.souza@intel.com> <0cd79dd50c476c01afddea6ca1ee2fe80b0b40c1.camel@intel.com> <a900639aa1065838eb841afbd4d8d3713fe9cf74.camel@intel.com> <41bec38440596890bea141b564235340709d414e.camel@intel.com> <9f6c388b49e0bb5c8045034ac64c4b710d1bc140.camel@intel.com> <9b14efe375bb34a2dd59b45ea747dda514b38161.camel@intel.com> Message-ID: <5ee38c188c3c4bf51b1c6a638f715ec90678f2e5.camel@intel.com> On Mon, 2020-06-15 at 19:23 +0000, Souza, Jose wrote: > On Mon, 2020-06-15 at 19:37 +0100, Mun, Gwan-gyeong wrote: > > On Fri, 2020-06-12 at 21:49 +0000, Mun, Gwan-gyeong wrote: > > > On Fri, 2020-06-12 at 14:18 -0700, Souza, Jose wrote: > > > > On Fri, 2020-06-12 at 21:57 +0100, Mun, Gwan-gyeong wrote: > > > > > On Tue, 2020-05-26 at 15:14 -0700, Jos? Roberto de Souza wrote: > > > > > > This registers will be used to implement PSR2 software > > > > > > tracking. > > > > > > > > > > > > BSpec: 55229 > > > > > > BSpec: 50424 > > > > > > BSpec: 50420 > > > > > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/i915_reg.h | 68 > > > > > > ++++++++++++++++++++++++++++++- > > > > > > -- > > > > > > 1 file changed, 63 insertions(+), 5 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > > > b/drivers/gpu/drm/i915/i915_reg.h > > > > > > index e9d50fe0f375..6f547e459d30 100644 > > > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > > > @@ -4566,6 +4566,18 @@ enum { > > > > > > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > > > > > > PSR2_SU_STATUS_SHIFT(frame)) > > > > > > #define PSR2_SU_STATUS_FRAMES 8 > > > > > > > > > > > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > > > > > > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > > > > > > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > > > > > > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > > > > > > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT > > > > > > (31) > > > > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK REG_GEN > > > > > > MASK(30, > > > > > > 21) > > > > > > +#define PSR2_MAN_TRK_CTL_REGION_START_ADDR(val) REG_FIE > > > > > > LD_PREP( > > > > > > PSR2_MAN_TRK_CTL_REGION_START_ADDR_MASK, val) > > > > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK REG_GEN > > > > > > MASK(20, 11) > > > > > > +#define PSR2_MAN_TRK_CTL_REGION_END_ADDR(val) REG_FIE > > > > > > LD_PREP(PSR2_MAN_TRK_CTL_REGION_END_ADDR_MASK, val) > > > > > > +#define PSR2_MAN_TRK_CTL_SINGLE_FULL_FRAME REG_BIT > > > > > > (3) > > > > > > +#define PSR2_MAN_TRK_CTL_CONTINUOS_FULL_FRAME REG_BIT > > > > > > (2) > > > > > > +#define PSR2_MAN_TRK_CTL_PARTIAL_FRAME_UPDATE REG_BIT > > > > > > (1) > > > > > > + > > > > > As per Bspec, it would be better that the names of bit as below. > > > > > > > > > > PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > > > > > PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > > > > > PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_ENABLE > > > > > > > > No problem in naming like this but MAN_TRK and SF is kind of > > > > redundant and the name was already big. > > > > Your call. > > > > > > > > > > /* VGA port control */ > > > > > > #define ADPA _MMIO(0x61100) > > > > > > #define PCH_ADPA _MMIO(0xe1100) > > > > > > @@ -7129,7 +7141,52 @@ enum { > > > > > > #define PLANE_COLOR_CTL(pipe, plane) \ > > > > > > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > > > > > > _PLANE_COLOR_CTL_2(pipe)) > > > > > > > > > > > > -#/* SKL new cursor registers */ > > > > > > +#define _PLANE_SEL_FETCH_BASE_1_A 0x70890 > > > > > > +#define _PLANE_SEL_FETCH_BASE_2_A 0x708B0 > > > > > > +#define _PLANE_SEL_FETCH_BASE_3_A 0x708D0 > > > > > > +#define _PLANE_SEL_FETCH_BASE_4_A 0x708F0 > > > > > > +#define _PLANE_SEL_FETCH_BASE_5_A 0x70920 > > > > > > +#define _PLANE_SEL_FETCH_BASE_6_A 0x70940 > > > > > > +#define _PLANE_SEL_FETCH_BASE_7_A 0x70960 > > > > > > +#define _PLANE_SEL_FETCH_BASE_CUR_A 0x70880 > > > > > > +#define _PLANE_SEL_FETCH_BASE_1_B 0x70990 > > > > > > + > > > > > And as per Bspec, the prefix _SEL_FETCH_PLANE_ is better than > > > > > _PLANE_SEL_FETCH_ . > > > > You mean just for the "internal" ones? For PLANE_SEL_FETCH_CTL, > > > > PLANE_SEL_FETCH_SIZE... would be better keep like this to match > > > > other > > > > plane register > > > > names. > > > Internals and externals. I also noticed your intention (match other > > > plane related registers), but when I checked other plane related > > > resiters, they followed bspec names. (But I am not confident on > > > register naming policy; we always have to follow documented register > > > names or not. ) I don't think we are that restrict as there is several registers that don't match. Will update the internal ones, anyone searching by BSpec name will find the internal ones and reach the exported ones. > > > > > > +#define _PLANE_SEL_FETCH_BASE_A(plane) _PICK(plane, \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_1_A, > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_2_A, > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_3_A, > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_4_A, > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_5_A, > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_6_A, > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_7_A, > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_B > > > > > > ASE_CUR_ > > > > > > A) > > > > > > +#define _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, > > > > > > _PLANE_SEL_FETCH_BASE_1_A, _PLANE_SEL_FETCH_BASE_1_A) > > > > It seems that indicates an wrong register name. > > IMHO, is it your intention like this? " #define > > _PLANE_SEL_FETCH_BASE_1(pipe) _PIPE(pipe, _PLANE_SEL_FETCH_BASE_1_A, > > _PLANE_SEL_FETCH_BASE_1_B) "? > > Yes, it should be _PLANE_SEL_FETCH_BASE_1_B, thanks for catching this. > Will send this 4 patches in a few days with the requested fixes. > > > > > > > +#define PLANE_SEL_FETCH_BASE(pipe, plane) > > > > > > (_PLANE_SEL_FETCH_BASE_1(pipe) - \ > > > > > > + _PLANE_SEL_FETCH_BAS > > > > > > E_1_A + > > > > > > \ > > > > > > + _PLANE_SEL_FETCH_BAS > > > > > > E_A(plan > > > > > > e)) > > > > > > + > > > > > > +#define _PLANE_SEL_FETCH_CTL_1_A 0x70890 > > > > > > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > > + _PLANE_SEL_FETCH > > > > > > _CTL_1_A > > > > > > - \ > > > > > > + _PLANE_SEL_FETCH > > > > > > _BASE_1_ > > > > > > A) > > > > > > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) > > > > > > + > > > > > > +#define _PLANE_SEL_FETCH_POS_1_A 0x70894 > > > > > > +#define PLANE_SEL_FETCH_POS(pipe, plane) > > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > > + _PLANE_SEL_FETCH > > > > > > _POS_1_A > > > > > > - \ > > > > > > + _PLANE_SEL_FETCH > > > > > > _BASE_1_ > > > > > > A) > > > > > > + > > > > > > +#define _PLANE_SEL_FETCH_SIZE_1_A 0x70898 > > > > > > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > > + _PLANE_SEL_FETC > > > > > > H_SIZE_1 > > > > > > _A - \ > > > > > > + _PLANE_SEL_FETC > > > > > > H_BASE_1 > > > > > > _A) > > > > > > + > > > > > > +#define _PLANE_SEL_FETCH_OFFSET_1_A 0x7089C > > > > > > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > > > > > > _MMIO(PLANE_SEL_FETCH_BASE(pipe, plane) + \ > > > > > > + _PLANE_SEL_FE > > > > > > TCH_OFFS > > > > > > ET_1_A - \ > > > > > > + _PLANE_SEL_FE > > > > > > TCH_BASE > > > > > > _1_A) > > > > > > + > > > > > > +/* SKL new cursor registers */ > > > > > > #define _CUR_BUF_CFG_A 0x7017c > > > > > > #define _CUR_BUF_CFG_B 0x7117c > > > > > > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, > > > > > > _CUR_BUF_CFG_A, > > > > > > _CUR_BUF_CFG_B) > > > > > > @@ -7775,11 +7832,12 @@ enum { > > > > > > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > > > > > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << > > > > > > 2) > > > > > > > > > > > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > > > > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > > > > > > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > > > > > > -#define DPA_MASK_VBLANK_SRD (1 << 15) > > > > > > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > > > > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > > > > +#define DPA_MASK_VBLANK_SRD (1 << 15) > > > > > > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > > > > > > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > > > > > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > > > > > > > > > > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > > > > > > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From manasi.d.navare at intel.com Thu Jun 25 21:55:28 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 25 Jun 2020 14:55:28 -0700 Subject: [Intel-gfx] [PATCH v3 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200625212622.GW6112@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> <20200625212622.GW6112@intel.com> Message-ID: <20200625215527.GA30431@intel.com> On Fri, Jun 26, 2020 at 12:26:22AM +0300, Ville Syrj?l? wrote: > On Wed, Jun 24, 2020 at 03:11:07PM -0700, Manasi Navare wrote: > > Modify the helper to add a fixed delay or poll with timeout > > based on platform specification to check for either Idle bit > > set (DDI_BUF_CTL is idle for disable case) > > > > v2: > > * Use 2 separate functions or idle and active (Ville) > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > > 1 file changed, 8 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 884b507c5f55..7d5c8ab88fc4 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > enum port port) > > { > > - i915_reg_t reg = DDI_BUF_CTL(port); > > - int i; > > - > > - for (i = 0; i < 16; i++) { > > - udelay(1); > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > - return; > > + if (IS_BROXTON(dev_priv)) { > > + udelay(16); > > + return; > > } > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > - port_name(port)); > > + > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 600)) > > Why 600? Yes thats a mistake, I will change it to 16usecs Manasi > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > > + port_name(port)); > > } > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From manasi.d.navare at intel.com Thu Jun 25 21:59:35 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 25 Jun 2020 14:59:35 -0700 Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200625212853.GX6112@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> <20200624221108.10038-2-manasi.d.navare@intel.com> <20200625212853.GX6112@intel.com> Message-ID: <20200625215935.GB30431@intel.com> On Fri, Jun 26, 2020 at 12:28:53AM +0300, Ville Syrj?l? wrote: > On Wed, Jun 24, 2020 at 03:11:08PM -0700, Manasi Navare wrote: > > Based on the platform, Bspec expects us to wait or poll with > > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > > after enabling DDI_BUF_CTL. > > > > v3: > > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > > v2: > > * Based on platform, fixed delay or poll (Ville) > > * Use a helper to do this (Imre, Ville) > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > > 1 file changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 7d5c8ab88fc4..ff6b1e9d1b4e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > port_name(port)); > > } > > > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > > + enum port port) > > +{ > > + if (INTEL_GEN(dev_priv) <= 9) { > > Didn't we want the poll approach for glk+? But other Gen9s like SKL is still a fixed delay so may be add a GEN <=9 & !GLK here would do? Manasi > > > + usleep_range(600, 1000); > > + return; > > + } > > + > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 600)) > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > > + port_name(port)); > > +} > > + > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > { > > switch (pll->info->id) { > > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > - udelay(600); > > + intel_wait_ddi_buf_active(dev_priv, port); > > Missed the FDI case. > > Also we're still missing this for HDMI, on icl+ I think? Can't quite > remember if that was where the spec started to demand it. > > > } > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From manasi.d.navare at intel.com Thu Jun 25 22:04:33 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 25 Jun 2020 15:04:33 -0700 Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200625212853.GX6112@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> <20200624221108.10038-2-manasi.d.navare@intel.com> <20200625212853.GX6112@intel.com> Message-ID: <20200625220432.GC30431@intel.com> On Fri, Jun 26, 2020 at 12:28:53AM +0300, Ville Syrj?l? wrote: > On Wed, Jun 24, 2020 at 03:11:08PM -0700, Manasi Navare wrote: > > Based on the platform, Bspec expects us to wait or poll with > > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > > after enabling DDI_BUF_CTL. > > > > v3: > > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > > v2: > > * Based on platform, fixed delay or poll (Ville) > > * Use a helper to do this (Imre, Ville) > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > > 1 file changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 7d5c8ab88fc4..ff6b1e9d1b4e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > port_name(port)); > > } > > > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > > + enum port port) > > +{ > > + if (INTEL_GEN(dev_priv) <= 9) { > > Didn't we want the poll approach for glk+? Actually in the bspec I only see Gen10+ has a 500usecs timeout Manasi > > > + usleep_range(600, 1000); > > + return; > > + } > > + > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 600)) > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > > + port_name(port)); > > +} > > + > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > { > > switch (pll->info->id) { > > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > - udelay(600); > > + intel_wait_ddi_buf_active(dev_priv, port); > > Missed the FDI case. > > Also we're still missing this for HDMI, on icl+ I think? Can't quite > remember if that was where the spec started to demand it. > > > } > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Thu Jun 25 22:16:42 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 26 Jun 2020 01:16:42 +0300 Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200625220432.GC30431@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> <20200624221108.10038-2-manasi.d.navare@intel.com> <20200625212853.GX6112@intel.com> <20200625220432.GC30431@intel.com> Message-ID: <20200625221642.GY6112@intel.com> On Thu, Jun 25, 2020 at 03:04:33PM -0700, Manasi Navare wrote: > On Fri, Jun 26, 2020 at 12:28:53AM +0300, Ville Syrj?l? wrote: > > On Wed, Jun 24, 2020 at 03:11:08PM -0700, Manasi Navare wrote: > > > Based on the platform, Bspec expects us to wait or poll with > > > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > > > after enabling DDI_BUF_CTL. > > > > > > v3: > > > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > > > v2: > > > * Based on platform, fixed delay or poll (Ville) > > > * Use a helper to do this (Imre, Ville) > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > > > 1 file changed, 15 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 7d5c8ab88fc4..ff6b1e9d1b4e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > > port_name(port)); > > > } > > > > > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > > > + enum port port) > > > +{ > > > + if (INTEL_GEN(dev_priv) <= 9) { > > > > Didn't we want the poll approach for glk+? > > Actually in the bspec I only see Gen10+ has a 500usecs timeout glk has (mostly) gen10 display. Defacto standard form to write that test is 'GEN < 10 && !IS_GLK'. > > Manasi > > > > > + usleep_range(600, 1000); > > > + return; > > > + } > > > + > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), 600)) > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > > > + port_name(port)); > > > +} > > > + > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > > { > > > switch (pll->info->id) { > > > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > > > - udelay(600); > > > + intel_wait_ddi_buf_active(dev_priv, port); > > > > Missed the FDI case. > > > > Also we're still missing this for HDMI, on icl+ I think? Can't quite > > remember if that was where the spec started to demand it. > > > > > } > > > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > > -- > > > 2.19.1 > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From manasi.d.navare at intel.com Thu Jun 25 22:27:18 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 25 Jun 2020 15:27:18 -0700 Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200625221642.GY6112@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> <20200624221108.10038-2-manasi.d.navare@intel.com> <20200625212853.GX6112@intel.com> <20200625220432.GC30431@intel.com> <20200625221642.GY6112@intel.com> Message-ID: <20200625222718.GD30431@intel.com> On Fri, Jun 26, 2020 at 01:16:42AM +0300, Ville Syrj?l? wrote: > On Thu, Jun 25, 2020 at 03:04:33PM -0700, Manasi Navare wrote: > > On Fri, Jun 26, 2020 at 12:28:53AM +0300, Ville Syrj?l? wrote: > > > On Wed, Jun 24, 2020 at 03:11:08PM -0700, Manasi Navare wrote: > > > > Based on the platform, Bspec expects us to wait or poll with > > > > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > > > > after enabling DDI_BUF_CTL. > > > > > > > > v3: > > > > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > > > > v2: > > > > * Based on platform, fixed delay or poll (Ville) > > > > * Use a helper to do this (Imre, Ville) > > > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Cc: Imre Deak <imre.deak at intel.com> > > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > > > > 1 file changed, 15 insertions(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > index 7d5c8ab88fc4..ff6b1e9d1b4e 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > > > port_name(port)); > > > > } > > > > > > > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > > > > + enum port port) > > > > +{ > > > > + if (INTEL_GEN(dev_priv) <= 9) { > > > > > > Didn't we want the poll approach for glk+? > > > > Actually in the bspec I only see Gen10+ has a 500usecs timeout > > glk has (mostly) gen10 display. > > Defacto standard form to write that test is > 'GEN < 10 && !IS_GLK'. Okay will update this and send in the next rev Manasi > > > > > Manasi > > > > > > > + usleep_range(600, 1000); > > > > + return; > > > > + } > > > > + > > > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > > + DDI_BUF_IS_IDLE), 600)) > > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > > > > + port_name(port)); > > > > +} > > > > + > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > > > { > > > > switch (pll->info->id) { > > > > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > > > > > - udelay(600); > > > > + intel_wait_ddi_buf_active(dev_priv, port); > > > > > > Missed the FDI case. > > > > > > Also we're still missing this for HDMI, on icl+ I think? Can't quite > > > remember if that was where the spec started to demand it. > > > > > > > } > > > > > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > > > -- > > > > 2.19.1 > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel From manasi.d.navare at intel.com Thu Jun 25 22:55:55 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Thu, 25 Jun 2020 15:55:55 -0700 Subject: [Intel-gfx] [v9 2/3] drm/debug: Expose connector VRR monitor range via debugfs In-Reply-To: <20200622142519.16214-3-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> <20200622142519.16214-3-bhanuprakash.modem@intel.com> Message-ID: <20200625225555.GE30431@intel.com> Thanks Bhanu for the patch, merged to drm-misc Manasi On Mon, Jun 22, 2020 at 07:55:18PM +0530, Bhanuprakash Modem wrote: > [Why] > It's useful to know the min and max vrr range for IGT testing. > > [How] > Expose the min and max vfreq for the connector via a debugfs file > on the connector, "vrr_range". > > Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > > v2: > * Fix the typo in max_vfreq (Manasi) > * Change the name of node to i915_vrr_info so we can add > other vrr info for more debug info (Manasi) > * Change the VRR capable to display Yes or No (Manasi) > * Fix indentation checkpatch errors (Manasi) > v3: > * Remove the unnecessary debug print (Manasi) > v4: > * Rebase > v5: > * Rename to vrr_range to match AMD debugfs > v6: > * Rebase (manasi) > v7: > * Fix cmpilation due to rebase > v8: > * Move debugfs node creation logic to DRM (Emil) > * Remove AMD specific logic (Emil) > v9: > * Seperate patch for removal of AMD specific logic (Manasi) > > Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > Cc: Jani Nikula <jani.nikula at linux.intel.com> > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Harry Wentland <harry.wentland at amd.com> > CC: Emil Velikov <emil.l.velikov at gmail.com> > --- > drivers/gpu/drm/drm_debugfs.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c > index bfe4602f206b..3d7182001004 100644 > --- a/drivers/gpu/drm/drm_debugfs.c > +++ b/drivers/gpu/drm/drm_debugfs.c > @@ -376,6 +376,24 @@ static ssize_t edid_write(struct file *file, const char __user *ubuf, > return (ret) ? ret : len; > } > > +/* > + * Returns the min and max vrr vfreq through the connector's debugfs file. > + * Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range > + */ > +static int vrr_range_show(struct seq_file *m, void *data) > +{ > + struct drm_connector *connector = m->private; > + > + if (connector->status != connector_status_connected) > + return -ENODEV; > + > + seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq); > + seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq); > + > + return 0; > +} > +DEFINE_SHOW_ATTRIBUTE(vrr_range); > + > static const struct file_operations drm_edid_fops = { > .owner = THIS_MODULE, > .open = edid_open, > @@ -413,6 +431,10 @@ void drm_debugfs_connector_add(struct drm_connector *connector) > /* edid */ > debugfs_create_file("edid_override", S_IRUGO | S_IWUSR, root, connector, > &drm_edid_fops); > + > + /* vrr range */ > + debugfs_create_file("vrr_range", S_IRUGO, root, connector, > + &vrr_range_fops); > } > > void drm_debugfs_connector_remove(struct drm_connector *connector) > -- > 2.20.1 > > _______________________________________________ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:05 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:05 -0700 Subject: [Intel-gfx] [PATCH 0/7] Move some device capabilities under intel_gt Message-ID: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Continuing our grouping of GT-related code under intel_gt, this series moves some of the runtime-detected device capabilities. In particular, the engine_mask and the sseu_info are placed under the gt structure, inside a newly added struct intel_gt_info. Error capture and info print at the intel_gt_info level have also been added. Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> Cc: Andi Shyti <andi.shyti at intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> Daniele Ceraolo Spurio (6): drm/i915: Convert device_info to uncore/de_read drm/i915: Use the gt in HAS_ENGINE drm/i915: Move engine-related mmio init to engines_init_mmio drm/i915: Move the engine mask to intel_gt_info drm/i915: Introduce gt_init_mmio drm/i915/sseu: Move sseu detection and dump to intel_sseu Venkata Sandeep Dhanalakota (1): drm/i915/sseu: Move sseu_info under gt_info drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 +- drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +- .../drm/i915/gem/selftests/i915_gem_context.c | 5 +- drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 87 ++- drivers/gpu/drm/i915/gt/intel_gt.c | 16 + drivers/gpu/drm/i915/gt/intel_gt.h | 5 + drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 11 + drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 6 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 592 +++++++++++++++- drivers/gpu/drm/i915/gt/intel_sseu.h | 10 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +- drivers/gpu/drm/i915/gvt/handlers.c | 4 +- drivers/gpu/drm/i915/gvt/interrupt.c | 2 +- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 12 +- drivers/gpu/drm/i915/i915_drv.c | 9 +- drivers/gpu/drm/i915/i915_drv.h | 17 +- drivers/gpu/drm/i915/i915_getparam.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 25 +- drivers/gpu/drm/i915/i915_gpu_error.h | 3 + drivers/gpu/drm/i915/i915_pci.c | 42 +- drivers/gpu/drm/i915/i915_perf.c | 9 +- drivers/gpu/drm/i915/i915_query.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 652 +----------------- drivers/gpu/drm/i915/intel_device_info.h | 14 +- drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 16 +- drivers/gpu/drm/i915/intel_uncore.h | 4 +- drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- 38 files changed, 835 insertions(+), 768 deletions(-) -- 2.24.1 From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:06 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:06 -0700 Subject: [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <20200625234212.22811-2-daniele.ceraolospurio@intel.com> Use intel_<uncore/de>_read instead of I915_READ to read the informational registers. Extended from an original sseu-only patch by Sandeep. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Andi Shyti <andi.shyti at intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> --- drivers/gpu/drm/i915/intel_device_info.c | 77 +++++++++++++++--------- 1 file changed, 47 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 544ac61fbc36..c27a56aff5de 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -26,6 +26,7 @@ #include <drm/i915_pciids.h> #include "display/intel_cdclk.h" +#include "display/intel_de.h" #include "intel_device_info.h" #include "i915_drv.h" @@ -237,6 +238,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) { struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; + struct intel_uncore *uncore = &dev_priv->uncore; u8 s_en; u32 dss_en; u16 eu_en = 0; @@ -250,12 +252,14 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) */ intel_sseu_set_info(sseu, 1, 6, 16); - s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & + GEN11_GT_S_ENA_MASK; - dss_en = I915_READ(GEN12_GT_DSS_ENABLE); + dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); /* one bit per pair of EUs */ - eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & + GEN11_EU_DIS_MASK); for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) if (eu_en_fuse & BIT(eu)) eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); @@ -269,6 +273,7 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) { struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; + struct intel_uncore *uncore = &dev_priv->uncore; u8 s_en; u32 ss_en; u8 eu_en; @@ -278,9 +283,12 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) else intel_sseu_set_info(sseu, 1, 8, 8); - s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; - ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); - eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & + GEN11_GT_S_ENA_MASK; + ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); + + eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & + GEN11_EU_DIS_MASK); gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); @@ -292,8 +300,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - const u32 fuse2 = I915_READ(GEN8_FUSE2); + const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); int s, ss; const int eu_mask = 0xff; u32 subslice_mask, eu_en; @@ -304,26 +313,26 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) GEN10_F2_S_ENA_SHIFT; /* Slice0 */ - eu_en = ~I915_READ(GEN8_EU_DISABLE0); + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); for (ss = 0; ss < sseu->max_subslices; ss++) sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); /* Slice1 */ sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); - eu_en = ~I915_READ(GEN8_EU_DISABLE1); + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); /* Slice2 */ sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); /* Slice3 */ sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); - eu_en = ~I915_READ(GEN8_EU_DISABLE2); + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); /* Slice4 */ sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); /* Slice5 */ sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); - eu_en = ~I915_READ(GEN10_EU_DISABLE3); + eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); subslice_mask = (1 << 4) - 1; @@ -372,7 +381,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) u32 fuse; u8 subslice_mask = 0; - fuse = I915_READ(CHV_FUSE_GT); + fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT); sseu->slice_mask = BIT(0); intel_sseu_set_info(sseu, 1, 2, 8); @@ -425,11 +434,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) { struct intel_device_info *info = mkwrite_device_info(dev_priv); struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; + struct intel_uncore *uncore = &dev_priv->uncore; int s, ss; u32 fuse2, eu_disable, subslice_mask; const u8 eu_mask = 0xff; - fuse2 = I915_READ(GEN8_FUSE2); + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; /* BXT has a single slice and at most 3 subslices. */ @@ -455,7 +465,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) intel_sseu_set_subslices(sseu, s, subslice_mask); - eu_disable = I915_READ(GEN9_EU_DISABLE(s)); + eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); for (ss = 0; ss < sseu->max_subslices; ss++) { int eu_per_ss; u8 eu_disabled_mask; @@ -528,10 +538,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) { struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; + struct intel_uncore *uncore = &dev_priv->uncore; int s, ss; u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ + u32 eu_disable0, eu_disable1, eu_disable2; - fuse2 = I915_READ(GEN8_FUSE2); + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; intel_sseu_set_info(sseu, 3, 3, 8); @@ -542,13 +554,15 @@ static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) subslice_mask = GENMASK(sseu->max_subslices - 1, 0); subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT); - - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; - eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | - ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << + eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); + eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); + eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); + eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; + eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | + ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << (32 - GEN8_EU_DIS0_S1_SHIFT)); - eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | - ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << + eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | + ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << (32 - GEN8_EU_DIS1_S2_SHIFT)); /* @@ -635,7 +649,7 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) break; } - fuse1 = I915_READ(HSW_PAVP_FUSE1); + fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1); switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { default: MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> @@ -675,7 +689,8 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) { - u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); + u32 ts_override = intel_uncore_read(&dev_priv->uncore, + GEN9_TIMESTAMP_OVERRIDE); u32 base_freq, frac_freq; base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> @@ -738,6 +753,7 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) { + struct intel_uncore *uncore = &dev_priv->uncore; u32 f12_5_mhz = 12500000; u32 f19_2_mhz = 19200000; u32 f24_mhz = 24000000; @@ -759,7 +775,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) */ return f12_5_mhz; } else if (INTEL_GEN(dev_priv) <= 9) { - u32 ctc_reg = I915_READ(CTC_MODE); + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); u32 freq = 0; if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { @@ -777,7 +793,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) return freq; } else if (INTEL_GEN(dev_priv) <= 12) { - u32 ctc_reg = I915_READ(CTC_MODE); + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); u32 freq = 0; /* First figure out the reference frequency. There are 2 ways @@ -788,7 +804,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { freq = read_reference_ts_freq(dev_priv); } else { - u32 rpm_config_reg = I915_READ(RPM_CONFIG0); + u32 rpm_config_reg = intel_uncore_read(uncore, RPM_CONFIG0); if (INTEL_GEN(dev_priv) <= 10) freq = gen10_get_crystal_clock_freq(dev_priv, @@ -967,8 +983,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && HAS_PCH_SPLIT(dev_priv)) { - u32 fuse_strap = I915_READ(FUSE_STRAP); - u32 sfuse_strap = I915_READ(SFUSE_STRAP); + u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); + u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); /* * SFUSE_STRAP is supposed to have a bit signalling the display @@ -993,7 +1009,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); } } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { - u32 dfsm = I915_READ(SKL_DFSM); + u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { info->pipe_mask &= ~BIT(PIPE_A); @@ -1083,6 +1099,7 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps, void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) { struct intel_device_info *info = mkwrite_device_info(dev_priv); + struct intel_uncore *uncore = &dev_priv->uncore; unsigned int logical_vdbox = 0; unsigned int i; u32 media_fuse; @@ -1092,7 +1109,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) < 11) return; - media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); + media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> -- 2.24.1 From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:09 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:09 -0700 Subject: [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <20200625234212.22811-5-daniele.ceraolospurio@intel.com> Since the engines belong to the GT, move the runtime-updated list of available engines to the intel_gt struct. The original mask has been renamed to indicate it contains the maximum engine list that can be found on a matching device. In preparation for other info being moved to the gt in follow up patches (sseu), introduce an intel_gt_info structure to group all gt-related runtime info. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> Cc: Andi Shyti <andi.shyti at intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 +++--- drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++ drivers/gpu/drm/i915/gt/intel_gt.h | 4 ++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 ++++ drivers/gpu/drm/i915/gt/intel_reset.c | 6 +-- .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 ++-- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 2 + drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 +-- drivers/gpu/drm/i915/i915_gpu_error.c | 23 ++++++---- drivers/gpu/drm/i915/i915_gpu_error.h | 3 ++ drivers/gpu/drm/i915/i915_pci.c | 42 +++++++++---------- drivers/gpu/drm/i915/intel_device_info.c | 1 - drivers/gpu/drm/i915/intel_device_info.h | 7 +--- drivers/gpu/drm/i915/intel_uncore.c | 2 +- drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- 21 files changed, 84 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..7ffac711e4b4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1973,8 +1973,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) static int num_vcs_engines(const struct drm_i915_private *i915) { - return hweight64(INTEL_INFO(i915)->engine_mask & - GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0)); + return hweight64(VDBOX_MASK(&i915->gt)); } /* diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 8497106eb3a6..3af58df3b13e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -370,7 +370,7 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine) * instances. */ if ((INTEL_GEN(i915) >= 11 && - RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) || + engine->gt->info.vdbox_sfc_access & engine->mask) || (INTEL_GEN(i915) >= 9 && engine->instance == 0)) engine->uabi_capabilities |= I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; @@ -459,7 +459,7 @@ void intel_engines_free(struct intel_gt *gt) static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; - struct intel_device_info *info = mkwrite_device_info(i915); + struct intel_gt_info *info = >->info; struct intel_uncore *uncore = gt->uncore; unsigned int logical_vdbox = 0; unsigned int i; @@ -467,6 +467,8 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) u16 vdbox_mask; u16 vebox_mask; + info->engine_mask = INTEL_INFO(i915)->max_engine_mask; + if (INTEL_GEN(i915) < 11) return info->engine_mask; @@ -494,7 +496,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) * In TGL each VDBOX has access to an SFC. */ if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) - RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i); + gt->info.vdbox_sfc_access |= BIT(i); } drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", vdbox_mask, VDBOX_MASK(gt)); @@ -527,7 +529,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) int intel_engines_init_mmio(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; - struct intel_device_info *device_info = mkwrite_device_info(i915); const unsigned int engine_mask = init_engine_mask(gt); unsigned int mask = 0; unsigned int i; @@ -557,9 +558,9 @@ int intel_engines_init_mmio(struct intel_gt *gt) * engines. */ if (drm_WARN_ON(&i915->drm, mask != engine_mask)) - device_info->engine_mask = mask; + gt->info.engine_mask = mask; - RUNTIME_INFO(i915)->num_engines = hweight32(mask); + gt->info.num_engines = hweight32(mask); intel_gt_check_and_clear_faults(gt); diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index ebc29b6ee86c..d0ae1cb5c7c9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -642,3 +642,9 @@ void intel_gt_driver_late_release(struct intel_gt *gt) intel_gt_fini_timelines(gt); intel_engines_free(gt); } + +void intel_gt_info_print(const struct intel_gt_info *info, + struct drm_printer *p) +{ + drm_printf(p, "available engines: %x\n", info->engine_mask); +} diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 4fac043750aa..15142e2a3b22 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -11,6 +11,7 @@ #include "intel_reset.h" struct drm_i915_private; +struct drm_printer; #define GT_TRACE(gt, fmt, ...) do { \ const struct intel_gt *gt__ __maybe_unused = (gt); \ @@ -68,4 +69,7 @@ static inline bool intel_gt_has_init_error(const struct intel_gt *gt) return test_bit(I915_WEDGED_ON_INIT, >->reset.flags); } +void intel_gt_info_print(const struct intel_gt_info *info, + struct drm_printer *p); + #endif /* __INTEL_GT_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 0cc1d6b185dc..bb7551867c00 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -109,6 +109,14 @@ struct intel_gt { struct intel_gt_buffer_pool buffer_pool; struct i915_vma *scratch; + + struct intel_gt_info { + intel_engine_mask_t engine_mask; + u8 num_engines; + + /* Media engine access to SFC per instance */ + u8 vdbox_sfc_access; + } info; }; enum intel_gt_scratch_field { diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 0156f1f5c736..952cd6e9b88e 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -342,7 +342,7 @@ static int gen6_reset_engines(struct intel_gt *gt, static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask) { struct intel_uncore *uncore = engine->uncore; - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access; + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; i915_reg_t sfc_forced_lock, sfc_forced_lock_ack; u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit; i915_reg_t sfc_usage; @@ -417,7 +417,7 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask) static void gen11_unlock_sfc(struct intel_engine_cs *engine) { struct intel_uncore *uncore = engine->uncore; - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access; + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; i915_reg_t sfc_forced_lock; u32 sfc_forced_lock_bit; @@ -1246,7 +1246,7 @@ void intel_gt_handle_error(struct intel_gt *gt, */ wakeref = intel_runtime_pm_get(gt->uncore->rpm); - engine_mask &= INTEL_INFO(gt->i915)->engine_mask; + engine_mask &= gt->info.engine_mask; if (flags & I915_ERROR_CAPTURE) { i915_capture_error_state(gt->i915); diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 68a08486fc87..b09b83deecef 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -649,7 +649,7 @@ static inline int mi_set_context(struct i915_request *rq, struct drm_i915_private *i915 = engine->i915; enum intel_engine_id id; const int num_engines = - IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; + IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; bool force_restore = false; int len; u32 *cs; diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index daa4aabab9a7..b3678b5f9655 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -963,7 +963,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer, goto out; if (i915_request_wait(head, 0, - 2 * RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3)) < 0) { + 2 * engine->gt->info.num_engines * (count + 2) * (count + 3)) < 0) { pr_err("Failed to slice along semaphore chain of length (%d, %d)!\n", count, n); GEM_TRACE_DUMP(); @@ -3569,8 +3569,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) } pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n", - count, flags, - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext); + count, flags, smoke->gt->info.num_engines, smoke->ncontext); return 0; } @@ -3597,8 +3596,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags) } while (count < smoke->ncontext && !__igt_timeout(end_time, NULL)); pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n", - count, flags, - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext); + count, flags, smoke->gt->info.num_engines, smoke->ncontext); return 0; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index fbdd6b0677db..c10ae1660e53 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -106,7 +106,7 @@ static void __guc_ads_init(struct intel_guc *guc) blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt); blob->system_info.vebox_enable_mask = VEBOX_MASK(gt); - blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; + blob->system_info.vdbox_sfc_support_mask = gt->info.vdbox_sfc_access; base = intel_guc_ggtt_offset(guc, guc->ads_vma); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index ddefc52f6e09..e047a4950f5f 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -347,7 +347,7 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; } - engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask; + engine_mask &= vgpu->gvt->gt->info.engine_mask; } /* vgpu_lock already hold by emulate mmio r/w */ diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8594a8ef08ce..cad1620d2a7e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -34,6 +34,7 @@ #include "gem/i915_gem_context.h" #include "gt/intel_gt_buffer_pool.h" #include "gt/intel_gt_clock_utils.h" +#include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" #include "gt/intel_gt_requests.h" #include "gt/intel_reset.h" @@ -61,6 +62,7 @@ static int i915_capabilities(struct seq_file *m, void *data) intel_device_info_print_static(INTEL_INFO(i915), &p); intel_device_info_print_runtime(RUNTIME_INFO(i915), &p); + intel_gt_info_print(&i915->gt.info, &p); intel_driver_caps_print(&i915->caps, &p); kernel_param_lock(THIS_MODULE); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 611287353420..67789df42be8 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -886,6 +886,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) intel_device_info_print_static(INTEL_INFO(dev_priv), &p); intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); + intel_gt_info_print(&dev_priv->gt.info, &p); } if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 17cad4e2cb9c..fa01bf0929e0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1254,7 +1254,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) /* Iterator over subset of engines selected by mask */ #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ - for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ + for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ (tmp__) ? \ ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 0;) @@ -1561,12 +1561,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) -#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id) +#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ unsigned int first__ = (first); \ unsigned int count__ = (count); \ - (INTEL_INFO((gt)->i915)->engine_mask & \ + ((gt)->info.engine_mask & \ GENMASK(first__ + count__ - 1, first__)) >> first__; \ }) #define VDBOX_MASK(gt) \ diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 866166ada10e..9cb9aa39c33d 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -42,6 +42,7 @@ #include "gem/i915_gem_context.h" #include "gem/i915_gem_lmem.h" +#include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" #include "i915_drv.h" @@ -619,16 +620,15 @@ static void print_error_vma(struct drm_i915_error_state_buf *m, } static void err_print_capabilities(struct drm_i915_error_state_buf *m, - const struct intel_device_info *info, - const struct intel_runtime_info *runtime, - const struct intel_driver_caps *caps) + struct i915_gpu_coredump *error) { struct drm_printer p = i915_error_printer(m); - intel_device_info_print_static(info, &p); - intel_device_info_print_runtime(runtime, &p); - intel_device_info_print_topology(&runtime->sseu, &p); - intel_driver_caps_print(caps, &p); + intel_device_info_print_static(&error->device_info, &p); + intel_device_info_print_runtime(&error->runtime_info, &p); + intel_device_info_print_topology(&error->runtime_info.sseu, &p); + intel_gt_info_print(&error->gt->info, &p); + intel_driver_caps_print(&error->driver_caps, &p); } static void err_print_params(struct drm_i915_error_state_buf *m, @@ -798,8 +798,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, if (error->display) intel_display_print_error_state(m, error->display); - err_print_capabilities(m, &error->device_info, &error->runtime_info, - &error->driver_caps); + err_print_capabilities(m, error); err_print_params(m, &error->params); } @@ -1630,6 +1629,11 @@ static void gt_record_regs(struct intel_gt_coredump *gt) gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); } +static void gt_record_info(struct intel_gt_coredump *gt) +{ + memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); +} + /* * Generate a semi-unique error code. The code is not meant to have meaning, The * code's only purpose is to try to prevent false duplicated bug reports by @@ -1808,6 +1812,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) return ERR_PTR(-ENOMEM); } + gt_record_info(error->gt); gt_record_engines(error->gt, compress); if (INTEL_INFO(i915)->has_gt_uc) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h index 76b80fbfb7e9..0220b0992808 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.h +++ b/drivers/gpu/drm/i915/i915_gpu_error.h @@ -15,6 +15,7 @@ #include <drm/drm_mm.h> #include "gt/intel_engine.h" +#include "gt/intel_gt_types.h" #include "gt/uc/intel_uc_fw.h" #include "intel_device_info.h" @@ -118,6 +119,8 @@ struct intel_gt_coredump { bool awake; bool simulated; + struct intel_gt_info info; + /* Generic register state */ u32 eir; u32 pgtbl_er; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index e5fdf17cd9cd..7658025a791f 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -168,7 +168,7 @@ .gpu_reset_clobbers_display = true, \ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ - .engine_mask = BIT(RCS0), \ + .max_engine_mask = BIT(RCS0), \ .has_snoop = true, \ .has_coherent_ggtt = false, \ .dma_mask_size = 32, \ @@ -188,7 +188,7 @@ .gpu_reset_clobbers_display = true, \ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ - .engine_mask = BIT(RCS0), \ + .max_engine_mask = BIT(RCS0), \ .has_snoop = true, \ .has_coherent_ggtt = false, \ .dma_mask_size = 32, \ @@ -225,7 +225,7 @@ static const struct intel_device_info i865g_info = { .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ .display.has_gmch = 1, \ .gpu_reset_clobbers_display = true, \ - .engine_mask = BIT(RCS0), \ + .max_engine_mask = BIT(RCS0), \ .has_snoop = true, \ .has_coherent_ggtt = true, \ .dma_mask_size = 32, \ @@ -316,7 +316,7 @@ static const struct intel_device_info pnv_m_info = { .display.has_hotplug = 1, \ .display.has_gmch = 1, \ .gpu_reset_clobbers_display = true, \ - .engine_mask = BIT(RCS0), \ + .max_engine_mask = BIT(RCS0), \ .has_snoop = true, \ .has_coherent_ggtt = true, \ .dma_mask_size = 36, \ @@ -348,7 +348,7 @@ static const struct intel_device_info i965gm_info = { static const struct intel_device_info g45_info = { GEN4_FEATURES, PLATFORM(INTEL_G45), - .engine_mask = BIT(RCS0) | BIT(VCS0), + .max_engine_mask = BIT(RCS0) | BIT(VCS0), .gpu_reset_clobbers_display = false, }; @@ -358,7 +358,7 @@ static const struct intel_device_info gm45_info = { .is_mobile = 1, .display.has_fbc = 1, .display.supports_tv = 1, - .engine_mask = BIT(RCS0) | BIT(VCS0), + .max_engine_mask = BIT(RCS0) | BIT(VCS0), .gpu_reset_clobbers_display = false, }; @@ -367,7 +367,7 @@ static const struct intel_device_info gm45_info = { .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ .display.has_hotplug = 1, \ - .engine_mask = BIT(RCS0) | BIT(VCS0), \ + .max_engine_mask = BIT(RCS0) | BIT(VCS0), \ .has_snoop = true, \ .has_coherent_ggtt = true, \ /* ilk does support rc6, but we do not implement [power] contexts */ \ @@ -397,7 +397,7 @@ static const struct intel_device_info ilk_m_info = { .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ .display.has_hotplug = 1, \ .display.has_fbc = 1, \ - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ .has_rc6 = 1, \ @@ -448,7 +448,7 @@ static const struct intel_device_info snb_m_gt2_info = { .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ .display.has_hotplug = 1, \ .display.has_fbc = 1, \ - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ .has_coherent_ggtt = true, \ .has_llc = 1, \ .has_rc6 = 1, \ @@ -519,7 +519,7 @@ static const struct intel_device_info vlv_info = { .ppgtt_size = 31, .has_snoop = true, .has_coherent_ggtt = false, - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), .display_mmio_offset = VLV_DISPLAY_BASE, I9XX_PIPE_OFFSETS, I9XX_CURSOR_OFFSETS, @@ -530,7 +530,7 @@ static const struct intel_device_info vlv_info = { #define G75_FEATURES \ GEN7_FEATURES, \ - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ .display.has_ddi = 1, \ @@ -597,7 +597,7 @@ static const struct intel_device_info bdw_rsvd_info = { static const struct intel_device_info bdw_gt3_info = { BDW_PLATFORM, .gt = 3, - .engine_mask = + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; @@ -608,7 +608,7 @@ static const struct intel_device_info chv_info = { .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), .display.has_hotplug = 1, .is_lp = 1, - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), .has_64bit_reloc = 1, .has_runtime_pm = 1, .has_rc6 = 1, @@ -661,7 +661,7 @@ static const struct intel_device_info skl_gt2_info = { #define SKL_GT3_PLUS_PLATFORM \ SKL_PLATFORM, \ - .engine_mask = \ + .max_engine_mask = \ BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) @@ -680,7 +680,7 @@ static const struct intel_device_info skl_gt4_info = { .is_lp = 1, \ .num_supported_dbuf_slices = 1, \ .display.has_hotplug = 1, \ - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ @@ -743,7 +743,7 @@ static const struct intel_device_info kbl_gt2_info = { static const struct intel_device_info kbl_gt3_info = { KBL_PLATFORM, .gt = 3, - .engine_mask = + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; @@ -764,7 +764,7 @@ static const struct intel_device_info cfl_gt2_info = { static const struct intel_device_info cfl_gt3_info = { CFL_PLATFORM, .gt = 3, - .engine_mask = + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; @@ -833,7 +833,7 @@ static const struct intel_device_info cnl_info = { static const struct intel_device_info icl_info = { GEN11_FEATURES, PLATFORM(INTEL_ICELAKE), - .engine_mask = + .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), }; @@ -841,7 +841,7 @@ static const struct intel_device_info ehl_info = { GEN11_FEATURES, PLATFORM(INTEL_ELKHARTLAKE), .require_force_probe = 1, - .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), + .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), .ppgtt_size = 36, }; @@ -877,7 +877,7 @@ static const struct intel_device_info tgl_info = { GEN12_FEATURES, PLATFORM(INTEL_TIGERLAKE), .display.has_modular_fia = 1, - .engine_mask = + .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), }; @@ -890,7 +890,7 @@ static const struct intel_device_info rkl_info = { BIT(TRANSCODER_C), .require_force_probe = 1, .display.has_psr_hw_tracking = 0, - .engine_mask = + .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), }; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 92ebea35c752..a362a66fce11 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -92,7 +92,6 @@ static const char *iommu_name(void) void intel_device_info_print_static(const struct intel_device_info *info, struct drm_printer *p) { - drm_printf(p, "engines: %x\n", info->engine_mask); drm_printf(p, "gen: %d\n", info->gen); drm_printf(p, "gt: %d\n", info->gt); drm_printf(p, "iommu: %s\n", iommu_name()); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index fa60fdc1d75a..f03ed95af190 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -157,7 +157,7 @@ struct intel_device_info { u8 gen; u8 gt; /* GT number, 0 if undefined */ - intel_engine_mask_t engine_mask; /* Engines supported by the HW */ + intel_engine_mask_t max_engine_mask; /* Engines supported by the HW */ enum intel_platform platform; @@ -219,8 +219,6 @@ struct intel_runtime_info { u8 num_sprites[I915_MAX_PIPES]; u8 num_scalers[I915_MAX_PIPES]; - u8 num_engines; - /* Slice/subslice/EU info */ struct sseu_dev_info sseu; @@ -228,9 +226,6 @@ struct intel_runtime_info { u32 cs_timestamp_frequency_hz; u32 cs_timestamp_period_ns; - - /* Media engine access to SFC per instance */ - u8 vdbox_sfc_access; }; struct intel_driver_caps { diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index bd4b45191f7b..f5548875836c 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1530,7 +1530,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) if (INTEL_GEN(i915) >= 11) { /* we'll prune the domains of missing engines later */ - intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask; + intel_engine_mask_t emask = INTEL_INFO(i915)->max_engine_mask; int i; uncore->funcs.force_wake_get = fw_domains_get_with_fallback; diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 9271aad7f779..57dd6f5122ee 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -1454,7 +1454,7 @@ static int live_breadcrumbs_smoketest(void *arg) idx++; } pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n", - num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus); + num_waits, num_fences, idx, ncpus); ret = igt_live_test_end(&live) ?: ret; out_contexts: diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c index 9b105b811f1f..0916efa31889 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c @@ -190,7 +190,8 @@ struct drm_i915_private *mock_gem_device(void) mock_init_ggtt(i915, &i915->ggtt); i915->gt.vm = i915_vm_get(&i915->ggtt.vm); - mkwrite_device_info(i915)->engine_mask = BIT(0); + mkwrite_device_info(i915)->max_engine_mask = BIT(0); + i915->gt.info.engine_mask = BIT(0); i915->gt.engine[RCS0] = mock_engine(i915, "mock", RCS0); if (!i915->gt.engine[RCS0]) -- 2.24.1 From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:10 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:10 -0700 Subject: [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <20200625234212.22811-6-daniele.ceraolospurio@intel.com> We already call 2 gt-related init_mmio functions in driver_mmio_probe and a 3rd one will be added by a follow-up patch, so pre-emptively introduce a gt_init_mmio function to group them. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> Cc: Andi Shyti <andi.shyti at intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++++ drivers/gpu/drm/i915/gt/intel_gt.h | 1 + drivers/gpu/drm/i915/i915_drv.c | 4 +--- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index d0ae1cb5c7c9..949114f09b82 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -44,6 +44,13 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) gt->ggtt = ggtt; } +int intel_gt_init_mmio(struct intel_gt *gt) +{ + intel_uc_init_mmio(>->uc); + + return intel_engines_init_mmio(gt); +} + static void init_unused_ring(struct intel_gt *gt, u32 base) { struct intel_uncore *uncore = gt->uncore; diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 15142e2a3b22..4bd64ab2b686 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -36,6 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc) void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915); void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt); +int intel_gt_init_mmio(struct intel_gt *gt); int __must_check intel_gt_init_hw(struct intel_gt *gt); int intel_gt_init(struct intel_gt *gt); void intel_gt_driver_register(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 67789df42be8..5fd5af4bc855 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -531,9 +531,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) /* Try to make sure MCHBAR is enabled before poking at it */ intel_setup_mchbar(dev_priv); - intel_uc_init_mmio(&dev_priv->gt.uc); - - ret = intel_engines_init_mmio(&dev_priv->gt); + ret = intel_gt_init_mmio(&dev_priv->gt); if (ret) goto err_uncore; -- 2.24.1 From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:07 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:07 -0700 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <20200625234212.22811-3-daniele.ceraolospurio@intel.com> A follow up patch will move the engine mask under the gt structure, so get ready for that. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> Cc: Andi Shyti <andi.shyti at intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 ++++--- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/gvt/interrupt.c | 2 +- drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++------- drivers/gpu/drm/i915/intel_device_info.c | 13 +++++++------ drivers/gpu/drm/i915/intel_pm.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 16 +++++++++------- drivers/gpu/drm/i915/intel_uncore.h | 4 +++- 12 files changed, 38 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 7bf2f76212f0..be92d1ef9aa9 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -473,7 +473,7 @@ int intel_engines_init_mmio(struct intel_gt *gt) return -ENODEV; for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { - if (!HAS_ENGINE(i915, i)) + if (!HAS_ENGINE(gt, i)) continue; err = intel_engine_setup(gt, i); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 0cc7dd54f4f9..e1964cf40fd6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -457,7 +457,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt) * RPS interrupts will get enabled/disabled on demand when RPS * itself is enabled/disabled. */ - if (HAS_ENGINE(gt->i915, VECS0)) { + if (HAS_ENGINE(gt, VECS0)) { pm_irqs |= PM_VEBOX_USER_INTERRUPT; gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 101728006ae9..fbdd6b0677db 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -67,7 +67,8 @@ struct __guc_ads_blob { static void __guc_ads_init(struct intel_guc *guc) { - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; + struct intel_gt *gt = guc_to_gt(guc); + struct drm_i915_private *dev_priv = gt->i915; struct __guc_ads_blob *blob = guc->ads_blob; const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; u32 base; @@ -103,8 +104,8 @@ static void __guc_ads_init(struct intel_guc *guc) blob->system_info.rcs_enabled = 1; blob->system_info.bcs_enabled = 1; - blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv); - blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv); + blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt); + blob->system_info.vebox_enable_mask = VEBOX_MASK(gt); blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; base = intel_guc_ggtt_offset(guc, guc->ads_vma); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 26cae4846c82..ddefc52f6e09 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ - if (HAS_ENGINE(dev_priv, VCS1)) \ + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \ MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ } while (0) diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c index 540017fed908..7498878e6289 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.c +++ b/drivers/gpu/drm/i915/gvt/interrupt.c @@ -540,7 +540,7 @@ static void gen8_init_irq( SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); - if (HAS_ENGINE(gvt->gt->i915, VCS1)) { + if (HAS_ENGINE(gvt->gt, VCS1)) { SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1); SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 2ccaf78f96e8..86a60bdf0818 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -171,7 +171,7 @@ static void load_render_mocs(const struct intel_engine_cs *engine) return; for (ring_id = 0; ring_id < cnt; ring_id++) { - if (!HAS_ENGINE(engine->i915, ring_id)) + if (!HAS_ENGINE(engine->gt, ring_id)) continue; offset.reg = regs[ring_id]; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 67102dc26fce..1f9c40cf10ae 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -533,7 +533,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) intel_device_info_init_mmio(dev_priv); - intel_uncore_prune_mmio_domains(&dev_priv->uncore); + intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt); intel_uc_init_mmio(&dev_priv->gt.uc); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9aad3ec979bd..17cad4e2cb9c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1560,18 +1560,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) -#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) +#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) +#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id) -#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ +#define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ unsigned int first__ = (first); \ unsigned int count__ = (count); \ - (INTEL_INFO(dev_priv)->engine_mask & \ + (INTEL_INFO((gt)->i915)->engine_mask & \ GENMASK(first__ + count__ - 1, first__)) >> first__; \ }) -#define VDBOX_MASK(dev_priv) \ - ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) -#define VEBOX_MASK(dev_priv) \ - ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) +#define VDBOX_MASK(gt) \ + ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) +#define VEBOX_MASK(gt) \ + ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) /* * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index c27a56aff5de..c0443afa12b9 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -1100,6 +1100,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) { struct intel_device_info *info = mkwrite_device_info(dev_priv); struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_gt *gt = &dev_priv->gt; unsigned int logical_vdbox = 0; unsigned int i; u32 media_fuse; @@ -1116,7 +1117,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) GEN11_GT_VEBOX_DISABLE_SHIFT; for (i = 0; i < I915_MAX_VCS; i++) { - if (!HAS_ENGINE(dev_priv, _VCS(i))) { + if (!HAS_ENGINE(gt, _VCS(i))) { vdbox_mask &= ~BIT(i); continue; } @@ -1136,11 +1137,11 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); } drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", - vdbox_mask, VDBOX_MASK(dev_priv)); - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); + vdbox_mask, VDBOX_MASK(gt)); + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); for (i = 0; i < I915_MAX_VECS; i++) { - if (!HAS_ENGINE(dev_priv, _VECS(i))) { + if (!HAS_ENGINE(gt, _VECS(i))) { vebox_mask &= ~BIT(i); continue; } @@ -1151,6 +1152,6 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) } } drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", - vebox_mask, VEBOX_MASK(dev_priv)); - GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); + vebox_mask, VEBOX_MASK(gt)); + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); } diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2a32d6230795..40f6fe69b70a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7105,7 +7105,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) /* This is not a WA. Enable VD HCP & MFX_ENC powergate */ for (i = 0; i < I915_MAX_VCS; i++) { - if (HAS_ENGINE(dev_priv, _VCS(i))) + if (HAS_ENGINE(&dev_priv->gt, _VCS(i))) vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) | VDN_MFX_POWERGATE_ENABLE(i); } diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 592364aed2da..bd4b45191f7b 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1529,6 +1529,8 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) if (INTEL_GEN(i915) >= 11) { + /* we'll prune the domains of missing engines later */ + intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask; int i; uncore->funcs.force_wake_get = fw_domains_get_with_fallback; @@ -1541,7 +1543,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) FORCEWAKE_ACK_BLITTER_GEN9); for (i = 0; i < I915_MAX_VCS; i++) { - if (!HAS_ENGINE(i915, _VCS(i))) + if (!__HAS_ENGINE(emask, _VCS(i))) continue; fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, @@ -1549,7 +1551,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); } for (i = 0; i < I915_MAX_VECS; i++) { - if (!HAS_ENGINE(i915, _VECS(i))) + if (!__HAS_ENGINE(emask, _VECS(i))) continue; fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, @@ -1844,20 +1846,20 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) * the forcewake domains. Prune them, to make sure they only reference existing * engines. */ -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) +void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, + struct intel_gt *gt) { - struct drm_i915_private *i915 = uncore->i915; enum forcewake_domains fw_domains = uncore->fw_domains; enum forcewake_domain_id domain_id; int i; - if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11) + if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11) return; for (i = 0; i < I915_MAX_VCS; i++) { domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; - if (HAS_ENGINE(i915, _VCS(i))) + if (HAS_ENGINE(gt, _VCS(i))) continue; if (fw_domains & BIT(domain_id)) @@ -1867,7 +1869,7 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) for (i = 0; i < I915_MAX_VECS; i++) { domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; - if (HAS_ENGINE(i915, _VECS(i))) + if (HAS_ENGINE(gt, _VECS(i))) continue; if (fw_domains & BIT(domain_id)) diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 8d3aa8b9acf9..c4b22d9d0b45 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -35,6 +35,7 @@ struct drm_i915_private; struct intel_runtime_pm; struct intel_uncore; +struct intel_gt; struct intel_uncore_mmio_debug { spinlock_t lock; /** lock is also taken in irq contexts. */ @@ -186,7 +187,8 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); void intel_uncore_init_early(struct intel_uncore *uncore, struct drm_i915_private *i915); int intel_uncore_init_mmio(struct intel_uncore *uncore); -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore); +void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, + struct intel_gt *gt); bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore); bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore); void intel_uncore_fini_mmio(struct intel_uncore *uncore); -- 2.24.1 From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:08 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:08 -0700 Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <20200625234212.22811-4-daniele.ceraolospurio@intel.com> All the info we read in intel_device_info_init_mmio are engine-related and since we already have an engine_init_mmio function we can just perform the operations from there. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> Cc: Andi Shyti <andi.shyti at intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.c | 4 -- drivers/gpu/drm/i915/intel_device_info.c | 66 --------------------- drivers/gpu/drm/i915/intel_device_info.h | 2 - 4 files changed, 71 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index be92d1ef9aa9..8497106eb3a6 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt) } } +/* + * Determine which engines are fused off in our particular hardware. Since the + * fuse register is in the blitter powerwell, we need forcewake to be ready at + * this point (but later we need to prune the forcewake domains for engines that + * are indeed fused off). + */ +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + struct intel_device_info *info = mkwrite_device_info(i915); + struct intel_uncore *uncore = gt->uncore; + unsigned int logical_vdbox = 0; + unsigned int i; + u32 media_fuse; + u16 vdbox_mask; + u16 vebox_mask; + + if (INTEL_GEN(i915) < 11) + return info->engine_mask; + + media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); + + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> + GEN11_GT_VEBOX_DISABLE_SHIFT; + + for (i = 0; i < I915_MAX_VCS; i++) { + if (!HAS_ENGINE(gt, _VCS(i))) { + vdbox_mask &= ~BIT(i); + continue; + } + + if (!(BIT(i) & vdbox_mask)) { + info->engine_mask &= ~BIT(_VCS(i)); + drm_dbg(&i915->drm, "vcs%u fused off\n", i); + continue; + } + + /* + * In Gen11, only even numbered logical VDBOXes are + * hooked up to an SFC (Scaler & Format Converter) unit. + * In TGL each VDBOX has access to an SFC. + */ + if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) + RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i); + } + drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", + vdbox_mask, VDBOX_MASK(gt)); + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); + + for (i = 0; i < I915_MAX_VECS; i++) { + if (!HAS_ENGINE(gt, _VECS(i))) { + vebox_mask &= ~BIT(i); + continue; + } + + if (!(BIT(i) & vebox_mask)) { + info->engine_mask &= ~BIT(_VECS(i)); + drm_dbg(&i915->drm, "vecs%u fused off\n", i); + } + } + drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", + vebox_mask, VEBOX_MASK(gt)); + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); + + return info->engine_mask; +} + /** * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers * @gt: pointer to struct intel_gt @@ -460,7 +528,7 @@ int intel_engines_init_mmio(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; struct intel_device_info *device_info = mkwrite_device_info(i915); - const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask; + const unsigned int engine_mask = init_engine_mask(gt); unsigned int mask = 0; unsigned int i; int err; @@ -497,6 +565,8 @@ int intel_engines_init_mmio(struct intel_gt *gt) intel_setup_engine_capabilities(gt); + intel_uncore_prune_engine_fw_domains(gt->uncore, gt); + return 0; cleanup: diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 1f9c40cf10ae..611287353420 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -531,10 +531,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) /* Try to make sure MCHBAR is enabled before poking at it */ intel_setup_mchbar(dev_priv); - intel_device_info_init_mmio(dev_priv); - - intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt); - intel_uc_init_mmio(&dev_priv->gt.uc); ret = intel_engines_init_mmio(&dev_priv->gt); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index c0443afa12b9..92ebea35c752 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -1089,69 +1089,3 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps, yesno(caps->has_logical_contexts)); drm_printf(p, "scheduler: %x\n", caps->scheduler); } - -/* - * Determine which engines are fused off in our particular hardware. Since the - * fuse register is in the blitter powerwell, we need forcewake to be ready at - * this point (but later we need to prune the forcewake domains for engines that - * are indeed fused off). - */ -void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) -{ - struct intel_device_info *info = mkwrite_device_info(dev_priv); - struct intel_uncore *uncore = &dev_priv->uncore; - struct intel_gt *gt = &dev_priv->gt; - unsigned int logical_vdbox = 0; - unsigned int i; - u32 media_fuse; - u16 vdbox_mask; - u16 vebox_mask; - - if (INTEL_GEN(dev_priv) < 11) - return; - - media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); - - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> - GEN11_GT_VEBOX_DISABLE_SHIFT; - - for (i = 0; i < I915_MAX_VCS; i++) { - if (!HAS_ENGINE(gt, _VCS(i))) { - vdbox_mask &= ~BIT(i); - continue; - } - - if (!(BIT(i) & vdbox_mask)) { - info->engine_mask &= ~BIT(_VCS(i)); - drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i); - continue; - } - - /* - * In Gen11, only even numbered logical VDBOXes are - * hooked up to an SFC (Scaler & Format Converter) unit. - * In TGL each VDBOX has access to an SFC. - */ - if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0) - RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); - } - drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", - vdbox_mask, VDBOX_MASK(gt)); - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); - - for (i = 0; i < I915_MAX_VECS; i++) { - if (!HAS_ENGINE(gt, _VECS(i))) { - vebox_mask &= ~BIT(i); - continue; - } - - if (!(BIT(i) & vebox_mask)) { - info->engine_mask &= ~BIT(_VECS(i)); - drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i); - } - } - drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", - vebox_mask, VEBOX_MASK(gt)); - GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); -} diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 8d62b8538585..fa60fdc1d75a 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -250,8 +250,6 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info, void intel_device_info_print_topology(const struct sseu_dev_info *sseu, struct drm_printer *p); -void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); - void intel_driver_caps_print(const struct intel_driver_caps *caps, struct drm_printer *p); -- 2.24.1 From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:11 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:11 -0700 Subject: [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <20200625234212.22811-7-daniele.ceraolospurio@intel.com> Keep all the SSEU code in the relevant file. The code has also been updated to use intel_gt instead of dev_priv. Based on an original patch by Sandeep. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> Cc: Andi Shyti <andi.shyti at intel.com> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> --- drivers/gpu/drm/i915/gt/intel_gt.c | 1 + drivers/gpu/drm/i915/gt/intel_sseu.c | 587 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_sseu.h | 8 + drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 584 +--------------------- drivers/gpu/drm/i915/intel_device_info.h | 2 - 7 files changed, 600 insertions(+), 586 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 949114f09b82..de95930f8627 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -47,6 +47,7 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) int intel_gt_init_mmio(struct intel_gt *gt) { intel_uc_init_mmio(>->uc); + intel_sseu_info_init(gt); return intel_engines_init_mmio(gt); } diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index d173271c7397..006f9118b319 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -60,6 +60,548 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) return hweight32(intel_sseu_get_subslices(sseu, slice)); } +static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, + int subslice) +{ + int slice_stride = sseu->max_subslices * sseu->eu_stride; + + return slice * slice_stride + subslice * sseu->eu_stride; +} + +static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, + int subslice) +{ + int i, offset = sseu_eu_idx(sseu, slice, subslice); + u16 eu_mask = 0; + + for (i = 0; i < sseu->eu_stride; i++) { + eu_mask |= ((u16)sseu->eu_mask[offset + i]) << + (i * BITS_PER_BYTE); + } + + return eu_mask; +} + +static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, + u16 eu_mask) +{ + int i, offset = sseu_eu_idx(sseu, slice, subslice); + + for (i = 0; i < sseu->eu_stride; i++) { + sseu->eu_mask[offset + i] = + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; + } +} + +static u16 compute_eu_total(const struct sseu_dev_info *sseu) +{ + u16 i, total = 0; + + for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) + total += hweight8(sseu->eu_mask[i]); + + return total; +} + +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, + u8 s_en, u32 ss_en, u16 eu_en) +{ + int s, ss; + + /* ss_en represents entire subslice mask across all slices */ + GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > + sizeof(ss_en) * BITS_PER_BYTE); + + for (s = 0; s < sseu->max_slices; s++) { + if ((s_en & BIT(s)) == 0) + continue; + + sseu->slice_mask |= BIT(s); + + intel_sseu_set_subslices(sseu, s, ss_en); + + for (ss = 0; ss < sseu->max_subslices; ss++) + if (intel_sseu_has_subslice(sseu, s, ss)) + sseu_set_eus(sseu, s, ss, eu_en); + } + sseu->eu_per_subslice = hweight16(eu_en); + sseu->eu_total = compute_eu_total(sseu); +} + +static void gen12_sseu_info_init(struct intel_gt *gt) +{ + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct intel_uncore *uncore = gt->uncore; + u8 s_en; + u32 dss_en; + u16 eu_en = 0; + u8 eu_en_fuse; + int eu; + + /* + * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. + * Instead of splitting these, provide userspace with an array + * of DSS to more closely represent the hardware resource. + */ + intel_sseu_set_info(sseu, 1, 6, 16); + + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & + GEN11_GT_S_ENA_MASK; + + dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); + + /* one bit per pair of EUs */ + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & + GEN11_EU_DIS_MASK); + for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) + if (eu_en_fuse & BIT(eu)) + eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); + + gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); + + /* TGL only supports slice-level power gating */ + sseu->has_slice_pg = 1; +} + +static void gen11_sseu_info_init(struct intel_gt *gt) +{ + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct intel_uncore *uncore = gt->uncore; + u8 s_en; + u32 ss_en; + u8 eu_en; + + if (IS_ELKHARTLAKE(gt->i915)) + intel_sseu_set_info(sseu, 1, 4, 8); + else + intel_sseu_set_info(sseu, 1, 8, 8); + + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & + GEN11_GT_S_ENA_MASK; + ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); + + eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & + GEN11_EU_DIS_MASK); + + gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); + + /* ICL has no power gating restrictions. */ + sseu->has_slice_pg = 1; + sseu->has_subslice_pg = 1; + sseu->has_eu_pg = 1; +} + +static void gen10_sseu_info_init(struct intel_gt *gt) +{ + struct intel_uncore *uncore = gt->uncore; + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); + int s, ss; + const int eu_mask = 0xff; + u32 subslice_mask, eu_en; + + intel_sseu_set_info(sseu, 6, 4, 8); + + sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> + GEN10_F2_S_ENA_SHIFT; + + /* Slice0 */ + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); + for (ss = 0; ss < sseu->max_subslices; ss++) + sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); + /* Slice1 */ + sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); + sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); + /* Slice2 */ + sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); + sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); + /* Slice3 */ + sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); + sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); + /* Slice4 */ + sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); + sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); + /* Slice5 */ + sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); + eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); + sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); + + subslice_mask = (1 << 4) - 1; + subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> + GEN10_F2_SS_DIS_SHIFT); + + for (s = 0; s < sseu->max_slices; s++) { + u32 subslice_mask_with_eus = subslice_mask; + + for (ss = 0; ss < sseu->max_subslices; ss++) { + if (sseu_get_eus(sseu, s, ss) == 0) + subslice_mask_with_eus &= ~BIT(ss); + } + + /* + * Slice0 can have up to 3 subslices, but there are only 2 in + * slice1/2. + */ + intel_sseu_set_subslices(sseu, s, s == 0 ? + subslice_mask_with_eus : + subslice_mask_with_eus & 0x3); + } + + sseu->eu_total = compute_eu_total(sseu); + + /* + * CNL is expected to always have a uniform distribution + * of EU across subslices with the exception that any one + * EU in any one subslice may be fused off for die + * recovery. + */ + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? + DIV_ROUND_UP(sseu->eu_total, + intel_sseu_subslice_total(sseu)) : + 0; + + /* No restrictions on Power Gating */ + sseu->has_slice_pg = 1; + sseu->has_subslice_pg = 1; + sseu->has_eu_pg = 1; +} + +static void cherryview_sseu_info_init(struct intel_gt *gt) +{ + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + u32 fuse; + u8 subslice_mask = 0; + + fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT); + + sseu->slice_mask = BIT(0); + intel_sseu_set_info(sseu, 1, 2, 8); + + if (!(fuse & CHV_FGT_DISABLE_SS0)) { + u8 disabled_mask = + ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> + CHV_FGT_EU_DIS_SS0_R0_SHIFT) | + (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> + CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); + + subslice_mask |= BIT(0); + sseu_set_eus(sseu, 0, 0, ~disabled_mask); + } + + if (!(fuse & CHV_FGT_DISABLE_SS1)) { + u8 disabled_mask = + ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> + CHV_FGT_EU_DIS_SS1_R0_SHIFT) | + (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> + CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); + + subslice_mask |= BIT(1); + sseu_set_eus(sseu, 0, 1, ~disabled_mask); + } + + intel_sseu_set_subslices(sseu, 0, subslice_mask); + + sseu->eu_total = compute_eu_total(sseu); + + /* + * CHV expected to always have a uniform distribution of EU + * across subslices. + */ + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? + sseu->eu_total / + intel_sseu_subslice_total(sseu) : + 0; + /* + * CHV supports subslice power gating on devices with more than + * one subslice, and supports EU power gating on devices with + * more than one EU pair per subslice. + */ + sseu->has_slice_pg = 0; + sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; + sseu->has_eu_pg = (sseu->eu_per_subslice > 2); +} + +static void gen9_sseu_info_init(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + struct intel_device_info *info = mkwrite_device_info(i915); + struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + struct intel_uncore *uncore = gt->uncore; + int s, ss; + u32 fuse2, eu_disable, subslice_mask; + const u8 eu_mask = 0xff; + + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; + + /* BXT has a single slice and at most 3 subslices. */ + intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3, + IS_GEN9_LP(i915) ? 3 : 4, 8); + + /* + * The subslice disable field is global, i.e. it applies + * to each of the enabled slices. + */ + subslice_mask = (1 << sseu->max_subslices) - 1; + subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> + GEN9_F2_SS_DIS_SHIFT); + + /* + * Iterate through enabled slices and subslices to + * count the total enabled EU. + */ + for (s = 0; s < sseu->max_slices; s++) { + if (!(sseu->slice_mask & BIT(s))) + /* skip disabled slice */ + continue; + + intel_sseu_set_subslices(sseu, s, subslice_mask); + + eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); + for (ss = 0; ss < sseu->max_subslices; ss++) { + int eu_per_ss; + u8 eu_disabled_mask; + + if (!intel_sseu_has_subslice(sseu, s, ss)) + /* skip disabled subslice */ + continue; + + eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; + + sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); + + eu_per_ss = sseu->max_eus_per_subslice - + hweight8(eu_disabled_mask); + + /* + * Record which subslice(s) has(have) 7 EUs. we + * can tune the hash used to spread work among + * subslices if they are unbalanced. + */ + if (eu_per_ss == 7) + sseu->subslice_7eu[s] |= BIT(ss); + } + } + + sseu->eu_total = compute_eu_total(sseu); + + /* + * SKL is expected to always have a uniform distribution + * of EU across subslices with the exception that any one + * EU in any one subslice may be fused off for die + * recovery. BXT is expected to be perfectly uniform in EU + * distribution. + */ + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? + DIV_ROUND_UP(sseu->eu_total, + intel_sseu_subslice_total(sseu)) : + 0; + /* + * SKL+ supports slice power gating on devices with more than + * one slice, and supports EU power gating on devices with + * more than one EU pair per subslice. BXT+ supports subslice + * power gating on devices with more than one subslice, and + * supports EU power gating on devices with more than one EU + * pair per subslice. + */ + sseu->has_slice_pg = + !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; + sseu->has_subslice_pg = + IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1; + sseu->has_eu_pg = sseu->eu_per_subslice > 2; + + if (IS_GEN9_LP(i915)) { +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) + info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; + + sseu->min_eu_in_pool = 0; + if (info->has_pooled_eu) { + if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) + sseu->min_eu_in_pool = 3; + else if (IS_SS_DISABLED(1)) + sseu->min_eu_in_pool = 6; + else + sseu->min_eu_in_pool = 9; + } +#undef IS_SS_DISABLED + } +} + +static void bdw_sseu_info_init(struct intel_gt *gt) +{ + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct intel_uncore *uncore = gt->uncore; + int s, ss; + u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ + u32 eu_disable0, eu_disable1, eu_disable2; + + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; + intel_sseu_set_info(sseu, 3, 3, 8); + + /* + * The subslice disable field is global, i.e. it applies + * to each of the enabled slices. + */ + subslice_mask = GENMASK(sseu->max_subslices - 1, 0); + subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> + GEN8_F2_SS_DIS_SHIFT); + eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); + eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); + eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); + eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; + eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | + ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << + (32 - GEN8_EU_DIS0_S1_SHIFT)); + eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | + ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << + (32 - GEN8_EU_DIS1_S2_SHIFT)); + + /* + * Iterate through enabled slices and subslices to + * count the total enabled EU. + */ + for (s = 0; s < sseu->max_slices; s++) { + if (!(sseu->slice_mask & BIT(s))) + /* skip disabled slice */ + continue; + + intel_sseu_set_subslices(sseu, s, subslice_mask); + + for (ss = 0; ss < sseu->max_subslices; ss++) { + u8 eu_disabled_mask; + u32 n_disabled; + + if (!intel_sseu_has_subslice(sseu, s, ss)) + /* skip disabled subslice */ + continue; + + eu_disabled_mask = + eu_disable[s] >> (ss * sseu->max_eus_per_subslice); + + sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); + + n_disabled = hweight8(eu_disabled_mask); + + /* + * Record which subslices have 7 EUs. + */ + if (sseu->max_eus_per_subslice - n_disabled == 7) + sseu->subslice_7eu[s] |= 1 << ss; + } + } + + sseu->eu_total = compute_eu_total(sseu); + + /* + * BDW is expected to always have a uniform distribution of EU across + * subslices with the exception that any one EU in any one subslice may + * be fused off for die recovery. + */ + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? + DIV_ROUND_UP(sseu->eu_total, + intel_sseu_subslice_total(sseu)) : + 0; + + /* + * BDW supports slice power gating on devices with more than + * one slice. + */ + sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; + sseu->has_subslice_pg = 0; + sseu->has_eu_pg = 0; +} + +static void hsw_sseu_info_init(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + u32 fuse1; + u8 subslice_mask = 0; + int s, ss; + + /* + * There isn't a register to tell us how many slices/subslices. We + * work off the PCI-ids here. + */ + switch (INTEL_INFO(i915)->gt) { + default: + MISSING_CASE(INTEL_INFO(i915)->gt); + /* fall through */ + case 1: + sseu->slice_mask = BIT(0); + subslice_mask = BIT(0); + break; + case 2: + sseu->slice_mask = BIT(0); + subslice_mask = BIT(0) | BIT(1); + break; + case 3: + sseu->slice_mask = BIT(0) | BIT(1); + subslice_mask = BIT(0) | BIT(1); + break; + } + + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); + switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { + default: + MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> + HSW_F1_EU_DIS_SHIFT); + /* fall through */ + case HSW_F1_EU_DIS_10EUS: + sseu->eu_per_subslice = 10; + break; + case HSW_F1_EU_DIS_8EUS: + sseu->eu_per_subslice = 8; + break; + case HSW_F1_EU_DIS_6EUS: + sseu->eu_per_subslice = 6; + break; + } + + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), + hweight8(subslice_mask), + sseu->eu_per_subslice); + + for (s = 0; s < sseu->max_slices; s++) { + intel_sseu_set_subslices(sseu, s, subslice_mask); + + for (ss = 0; ss < sseu->max_subslices; ss++) { + sseu_set_eus(sseu, s, ss, + (1UL << sseu->eu_per_subslice) - 1); + } + } + + sseu->eu_total = compute_eu_total(sseu); + + /* No powergating for you. */ + sseu->has_slice_pg = 0; + sseu->has_subslice_pg = 0; + sseu->has_eu_pg = 0; +} + +void intel_sseu_info_init(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + + if (IS_HASWELL(i915)) + hsw_sseu_info_init(gt); + else if (IS_CHERRYVIEW(i915)) + cherryview_sseu_info_init(gt); + else if (IS_BROADWELL(i915)) + bdw_sseu_info_init(gt); + else if (IS_GEN(i915, 9)) + gen9_sseu_info_init(gt); + else if (IS_GEN(i915, 10)) + gen10_sseu_info_init(gt); + else if (IS_GEN(i915, 11)) + gen11_sseu_info_init(gt); + else if (INTEL_GEN(i915) >= 12) + gen12_sseu_info_init(gt); +} + u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, const struct intel_sseu *req_sseu) { @@ -173,3 +715,48 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, return rpcs; } + +void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) +{ + int s; + + drm_printf(p, "slice total: %u, mask=%04x\n", + hweight8(sseu->slice_mask), sseu->slice_mask); + drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); + for (s = 0; s < sseu->max_slices; s++) { + drm_printf(p, "slice%d: %u subslices, mask=%08x\n", + s, intel_sseu_subslices_per_slice(sseu, s), + intel_sseu_get_subslices(sseu, s)); + } + drm_printf(p, "EU total: %u\n", sseu->eu_total); + drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); + drm_printf(p, "has slice power gating: %s\n", + yesno(sseu->has_slice_pg)); + drm_printf(p, "has subslice power gating: %s\n", + yesno(sseu->has_subslice_pg)); + drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); +} + +void intel_sseu_print_topology(const struct sseu_dev_info *sseu, + struct drm_printer *p) +{ + int s, ss; + + if (sseu->max_slices == 0) { + drm_printf(p, "Unavailable\n"); + return; + } + + for (s = 0; s < sseu->max_slices; s++) { + drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", + s, intel_sseu_subslices_per_slice(sseu, s), + intel_sseu_get_subslices(sseu, s)); + + for (ss = 0; ss < sseu->max_subslices; ss++) { + u16 enabled_eus = sseu_get_eus(sseu, s, ss); + + drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", + ss, hweight16(enabled_eus), enabled_eus); + } + } +} diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index d1d225204f09..f9c007f001e7 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -13,6 +13,8 @@ #include "i915_gem.h" struct drm_i915_private; +struct intel_gt; +struct drm_printer; #define GEN_MAX_SLICES (6) /* CNL upper bound */ #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ @@ -94,7 +96,13 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice); void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, u32 ss_mask); +void intel_sseu_info_init(struct intel_gt *gt); + u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, const struct intel_sseu *req_sseu); +void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); +void intel_sseu_print_topology(const struct sseu_dev_info *sseu, + struct drm_printer *p); + #endif /* __INTEL_SSEU_H__ */ diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index cad1620d2a7e..c893a82c2d99 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_printer p = drm_seq_file_printer(m); - intel_device_info_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); + intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); return 0; } diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 9cb9aa39c33d..99b4a0261b13 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -626,7 +626,7 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m, intel_device_info_print_static(&error->device_info, &p); intel_device_info_print_runtime(&error->runtime_info, &p); - intel_device_info_print_topology(&error->runtime_info.sseu, &p); + intel_sseu_print_topology(&error->runtime_info.sseu, &p); intel_gt_info_print(&error->gt->info, &p); intel_driver_caps_print(&error->driver_caps, &p); } diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index a362a66fce11..d8daf224cbd3 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -29,6 +29,7 @@ #include "display/intel_de.h" #include "intel_device_info.h" #include "i915_drv.h" +#include "gt/intel_sseu.h" #define PLATFORM_NAME(x) [INTEL_##x] = #x static const char * const platform_names[] = { @@ -111,581 +112,16 @@ void intel_device_info_print_static(const struct intel_device_info *info, #undef PRINT_FLAG } -static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) -{ - int s; - - drm_printf(p, "slice total: %u, mask=%04x\n", - hweight8(sseu->slice_mask), sseu->slice_mask); - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); - for (s = 0; s < sseu->max_slices; s++) { - drm_printf(p, "slice%d: %u subslices, mask=%08x\n", - s, intel_sseu_subslices_per_slice(sseu, s), - intel_sseu_get_subslices(sseu, s)); - } - drm_printf(p, "EU total: %u\n", sseu->eu_total); - drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); - drm_printf(p, "has slice power gating: %s\n", - yesno(sseu->has_slice_pg)); - drm_printf(p, "has subslice power gating: %s\n", - yesno(sseu->has_subslice_pg)); - drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); -} - void intel_device_info_print_runtime(const struct intel_runtime_info *info, struct drm_printer *p) { - sseu_dump(&info->sseu, p); + intel_sseu_dump(&info->sseu, p); drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); drm_printf(p, "CS timestamp frequency: %u Hz\n", info->cs_timestamp_frequency_hz); } -static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, - int subslice) -{ - int slice_stride = sseu->max_subslices * sseu->eu_stride; - - return slice * slice_stride + subslice * sseu->eu_stride; -} - -static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, - int subslice) -{ - int i, offset = sseu_eu_idx(sseu, slice, subslice); - u16 eu_mask = 0; - - for (i = 0; i < sseu->eu_stride; i++) { - eu_mask |= ((u16)sseu->eu_mask[offset + i]) << - (i * BITS_PER_BYTE); - } - - return eu_mask; -} - -static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, - u16 eu_mask) -{ - int i, offset = sseu_eu_idx(sseu, slice, subslice); - - for (i = 0; i < sseu->eu_stride; i++) { - sseu->eu_mask[offset + i] = - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; - } -} - -void intel_device_info_print_topology(const struct sseu_dev_info *sseu, - struct drm_printer *p) -{ - int s, ss; - - if (sseu->max_slices == 0) { - drm_printf(p, "Unavailable\n"); - return; - } - - for (s = 0; s < sseu->max_slices; s++) { - drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", - s, intel_sseu_subslices_per_slice(sseu, s), - intel_sseu_get_subslices(sseu, s)); - - for (ss = 0; ss < sseu->max_subslices; ss++) { - u16 enabled_eus = sseu_get_eus(sseu, s, ss); - - drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", - ss, hweight16(enabled_eus), enabled_eus); - } - } -} - -static u16 compute_eu_total(const struct sseu_dev_info *sseu) -{ - u16 i, total = 0; - - for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) - total += hweight8(sseu->eu_mask[i]); - - return total; -} - -static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, - u8 s_en, u32 ss_en, u16 eu_en) -{ - int s, ss; - - /* ss_en represents entire subslice mask across all slices */ - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > - sizeof(ss_en) * BITS_PER_BYTE); - - for (s = 0; s < sseu->max_slices; s++) { - if ((s_en & BIT(s)) == 0) - continue; - - sseu->slice_mask |= BIT(s); - - intel_sseu_set_subslices(sseu, s, ss_en); - - for (ss = 0; ss < sseu->max_subslices; ss++) - if (intel_sseu_has_subslice(sseu, s, ss)) - sseu_set_eus(sseu, s, ss, eu_en); - } - sseu->eu_per_subslice = hweight16(eu_en); - sseu->eu_total = compute_eu_total(sseu); -} - -static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) -{ - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - struct intel_uncore *uncore = &dev_priv->uncore; - u8 s_en; - u32 dss_en; - u16 eu_en = 0; - u8 eu_en_fuse; - int eu; - - /* - * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. - * Instead of splitting these, provide userspace with an array - * of DSS to more closely represent the hardware resource. - */ - intel_sseu_set_info(sseu, 1, 6, 16); - - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & - GEN11_GT_S_ENA_MASK; - - dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); - - /* one bit per pair of EUs */ - eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & - GEN11_EU_DIS_MASK); - for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) - if (eu_en_fuse & BIT(eu)) - eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); - - gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); - - /* TGL only supports slice-level power gating */ - sseu->has_slice_pg = 1; -} - -static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) -{ - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - struct intel_uncore *uncore = &dev_priv->uncore; - u8 s_en; - u32 ss_en; - u8 eu_en; - - if (IS_ELKHARTLAKE(dev_priv)) - intel_sseu_set_info(sseu, 1, 4, 8); - else - intel_sseu_set_info(sseu, 1, 8, 8); - - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & - GEN11_GT_S_ENA_MASK; - ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); - - eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & - GEN11_EU_DIS_MASK); - - gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); - - /* ICL has no power gating restrictions. */ - sseu->has_slice_pg = 1; - sseu->has_subslice_pg = 1; - sseu->has_eu_pg = 1; -} - -static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) -{ - struct intel_uncore *uncore = &dev_priv->uncore; - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); - int s, ss; - const int eu_mask = 0xff; - u32 subslice_mask, eu_en; - - intel_sseu_set_info(sseu, 6, 4, 8); - - sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> - GEN10_F2_S_ENA_SHIFT; - - /* Slice0 */ - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); - for (ss = 0; ss < sseu->max_subslices; ss++) - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); - /* Slice1 */ - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); - /* Slice2 */ - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); - /* Slice3 */ - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); - /* Slice4 */ - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); - /* Slice5 */ - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); - eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); - - subslice_mask = (1 << 4) - 1; - subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> - GEN10_F2_SS_DIS_SHIFT); - - for (s = 0; s < sseu->max_slices; s++) { - u32 subslice_mask_with_eus = subslice_mask; - - for (ss = 0; ss < sseu->max_subslices; ss++) { - if (sseu_get_eus(sseu, s, ss) == 0) - subslice_mask_with_eus &= ~BIT(ss); - } - - /* - * Slice0 can have up to 3 subslices, but there are only 2 in - * slice1/2. - */ - intel_sseu_set_subslices(sseu, s, s == 0 ? - subslice_mask_with_eus : - subslice_mask_with_eus & 0x3); - } - - sseu->eu_total = compute_eu_total(sseu); - - /* - * CNL is expected to always have a uniform distribution - * of EU across subslices with the exception that any one - * EU in any one subslice may be fused off for die - * recovery. - */ - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? - DIV_ROUND_UP(sseu->eu_total, - intel_sseu_subslice_total(sseu)) : - 0; - - /* No restrictions on Power Gating */ - sseu->has_slice_pg = 1; - sseu->has_subslice_pg = 1; - sseu->has_eu_pg = 1; -} - -static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) -{ - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - u32 fuse; - u8 subslice_mask = 0; - - fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT); - - sseu->slice_mask = BIT(0); - intel_sseu_set_info(sseu, 1, 2, 8); - - if (!(fuse & CHV_FGT_DISABLE_SS0)) { - u8 disabled_mask = - ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> - CHV_FGT_EU_DIS_SS0_R0_SHIFT) | - (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> - CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); - - subslice_mask |= BIT(0); - sseu_set_eus(sseu, 0, 0, ~disabled_mask); - } - - if (!(fuse & CHV_FGT_DISABLE_SS1)) { - u8 disabled_mask = - ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> - CHV_FGT_EU_DIS_SS1_R0_SHIFT) | - (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> - CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); - - subslice_mask |= BIT(1); - sseu_set_eus(sseu, 0, 1, ~disabled_mask); - } - - intel_sseu_set_subslices(sseu, 0, subslice_mask); - - sseu->eu_total = compute_eu_total(sseu); - - /* - * CHV expected to always have a uniform distribution of EU - * across subslices. - */ - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? - sseu->eu_total / - intel_sseu_subslice_total(sseu) : - 0; - /* - * CHV supports subslice power gating on devices with more than - * one subslice, and supports EU power gating on devices with - * more than one EU pair per subslice. - */ - sseu->has_slice_pg = 0; - sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; - sseu->has_eu_pg = (sseu->eu_per_subslice > 2); -} - -static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) -{ - struct intel_device_info *info = mkwrite_device_info(dev_priv); - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - struct intel_uncore *uncore = &dev_priv->uncore; - int s, ss; - u32 fuse2, eu_disable, subslice_mask; - const u8 eu_mask = 0xff; - - fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; - - /* BXT has a single slice and at most 3 subslices. */ - intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, - IS_GEN9_LP(dev_priv) ? 3 : 4, 8); - - /* - * The subslice disable field is global, i.e. it applies - * to each of the enabled slices. - */ - subslice_mask = (1 << sseu->max_subslices) - 1; - subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> - GEN9_F2_SS_DIS_SHIFT); - - /* - * Iterate through enabled slices and subslices to - * count the total enabled EU. - */ - for (s = 0; s < sseu->max_slices; s++) { - if (!(sseu->slice_mask & BIT(s))) - /* skip disabled slice */ - continue; - - intel_sseu_set_subslices(sseu, s, subslice_mask); - - eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); - for (ss = 0; ss < sseu->max_subslices; ss++) { - int eu_per_ss; - u8 eu_disabled_mask; - - if (!intel_sseu_has_subslice(sseu, s, ss)) - /* skip disabled subslice */ - continue; - - eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; - - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); - - eu_per_ss = sseu->max_eus_per_subslice - - hweight8(eu_disabled_mask); - - /* - * Record which subslice(s) has(have) 7 EUs. we - * can tune the hash used to spread work among - * subslices if they are unbalanced. - */ - if (eu_per_ss == 7) - sseu->subslice_7eu[s] |= BIT(ss); - } - } - - sseu->eu_total = compute_eu_total(sseu); - - /* - * SKL is expected to always have a uniform distribution - * of EU across subslices with the exception that any one - * EU in any one subslice may be fused off for die - * recovery. BXT is expected to be perfectly uniform in EU - * distribution. - */ - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? - DIV_ROUND_UP(sseu->eu_total, - intel_sseu_subslice_total(sseu)) : - 0; - /* - * SKL+ supports slice power gating on devices with more than - * one slice, and supports EU power gating on devices with - * more than one EU pair per subslice. BXT+ supports subslice - * power gating on devices with more than one subslice, and - * supports EU power gating on devices with more than one EU - * pair per subslice. - */ - sseu->has_slice_pg = - !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; - sseu->has_subslice_pg = - IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; - sseu->has_eu_pg = sseu->eu_per_subslice > 2; - - if (IS_GEN9_LP(dev_priv)) { -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; - - sseu->min_eu_in_pool = 0; - if (info->has_pooled_eu) { - if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) - sseu->min_eu_in_pool = 3; - else if (IS_SS_DISABLED(1)) - sseu->min_eu_in_pool = 6; - else - sseu->min_eu_in_pool = 9; - } -#undef IS_SS_DISABLED - } -} - -static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) -{ - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - struct intel_uncore *uncore = &dev_priv->uncore; - int s, ss; - u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ - u32 eu_disable0, eu_disable1, eu_disable2; - - fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; - intel_sseu_set_info(sseu, 3, 3, 8); - - /* - * The subslice disable field is global, i.e. it applies - * to each of the enabled slices. - */ - subslice_mask = GENMASK(sseu->max_subslices - 1, 0); - subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> - GEN8_F2_SS_DIS_SHIFT); - eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); - eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); - eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); - eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; - eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | - ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << - (32 - GEN8_EU_DIS0_S1_SHIFT)); - eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | - ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << - (32 - GEN8_EU_DIS1_S2_SHIFT)); - - /* - * Iterate through enabled slices and subslices to - * count the total enabled EU. - */ - for (s = 0; s < sseu->max_slices; s++) { - if (!(sseu->slice_mask & BIT(s))) - /* skip disabled slice */ - continue; - - intel_sseu_set_subslices(sseu, s, subslice_mask); - - for (ss = 0; ss < sseu->max_subslices; ss++) { - u8 eu_disabled_mask; - u32 n_disabled; - - if (!intel_sseu_has_subslice(sseu, s, ss)) - /* skip disabled subslice */ - continue; - - eu_disabled_mask = - eu_disable[s] >> (ss * sseu->max_eus_per_subslice); - - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); - - n_disabled = hweight8(eu_disabled_mask); - - /* - * Record which subslices have 7 EUs. - */ - if (sseu->max_eus_per_subslice - n_disabled == 7) - sseu->subslice_7eu[s] |= 1 << ss; - } - } - - sseu->eu_total = compute_eu_total(sseu); - - /* - * BDW is expected to always have a uniform distribution of EU across - * subslices with the exception that any one EU in any one subslice may - * be fused off for die recovery. - */ - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? - DIV_ROUND_UP(sseu->eu_total, - intel_sseu_subslice_total(sseu)) : - 0; - - /* - * BDW supports slice power gating on devices with more than - * one slice. - */ - sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; - sseu->has_subslice_pg = 0; - sseu->has_eu_pg = 0; -} - -static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) -{ - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; - u32 fuse1; - u8 subslice_mask = 0; - int s, ss; - - /* - * There isn't a register to tell us how many slices/subslices. We - * work off the PCI-ids here. - */ - switch (INTEL_INFO(dev_priv)->gt) { - default: - MISSING_CASE(INTEL_INFO(dev_priv)->gt); - /* fall through */ - case 1: - sseu->slice_mask = BIT(0); - subslice_mask = BIT(0); - break; - case 2: - sseu->slice_mask = BIT(0); - subslice_mask = BIT(0) | BIT(1); - break; - case 3: - sseu->slice_mask = BIT(0) | BIT(1); - subslice_mask = BIT(0) | BIT(1); - break; - } - - fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1); - switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { - default: - MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> - HSW_F1_EU_DIS_SHIFT); - /* fall through */ - case HSW_F1_EU_DIS_10EUS: - sseu->eu_per_subslice = 10; - break; - case HSW_F1_EU_DIS_8EUS: - sseu->eu_per_subslice = 8; - break; - case HSW_F1_EU_DIS_6EUS: - sseu->eu_per_subslice = 6; - break; - } - - intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), - hweight8(subslice_mask), - sseu->eu_per_subslice); - - for (s = 0; s < sseu->max_slices; s++) { - intel_sseu_set_subslices(sseu, s, subslice_mask); - - for (ss = 0; ss < sseu->max_subslices; ss++) { - sseu_set_eus(sseu, s, ss, - (1UL << sseu->eu_per_subslice) - 1); - } - } - - sseu->eu_total = compute_eu_total(sseu); - - /* No powergating for you. */ - sseu->has_slice_pg = 0; - sseu->has_subslice_pg = 0; - sseu->has_eu_pg = 0; -} - static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) { u32 ts_override = intel_uncore_read(&dev_priv->uncore, @@ -1042,22 +478,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) info->display.has_dsc = 0; } - /* Initialize slice/subslice/EU info */ - if (IS_HASWELL(dev_priv)) - hsw_sseu_info_init(dev_priv); - else if (IS_CHERRYVIEW(dev_priv)) - cherryview_sseu_info_init(dev_priv); - else if (IS_BROADWELL(dev_priv)) - bdw_sseu_info_init(dev_priv); - else if (IS_GEN(dev_priv, 9)) - gen9_sseu_info_init(dev_priv); - else if (IS_GEN(dev_priv, 10)) - gen10_sseu_info_init(dev_priv); - else if (IS_GEN(dev_priv, 11)) - gen11_sseu_info_init(dev_priv); - else if (INTEL_GEN(dev_priv) >= 12) - gen12_sseu_info_init(dev_priv); - if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { drm_info(&dev_priv->drm, "Disabling ppGTT for VT-d support\n"); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index f03ed95af190..ce2ccee9b49b 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -242,8 +242,6 @@ void intel_device_info_print_static(const struct intel_device_info *info, struct drm_printer *p); void intel_device_info_print_runtime(const struct intel_runtime_info *info, struct drm_printer *p); -void intel_device_info_print_topology(const struct sseu_dev_info *sseu, - struct drm_printer *p); void intel_driver_caps_print(const struct intel_driver_caps *caps, struct drm_printer *p); -- 2.24.1 From daniele.ceraolospurio at intel.com Thu Jun 25 23:42:12 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Thu, 25 Jun 2020 16:42:12 -0700 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <20200625234212.22811-8-daniele.ceraolospurio@intel.com> From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> SSEUs are a GT capability, so track them under gt_info. Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Cc: Andi Shyti <andi.shyti at intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 ++++--- drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +- .../drm/i915/gem/selftests/i915_gem_context.c | 5 ++++- drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++ drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 3 ++- drivers/gpu/drm/i915/gt/intel_sseu.c | 19 ++++++++++--------- drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++---- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +-- drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++----- drivers/gpu/drm/i915/i915_getparam.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++-- drivers/gpu/drm/i915/i915_perf.c | 9 ++++----- drivers/gpu/drm/i915/i915_query.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 3 --- drivers/gpu/drm/i915/intel_device_info.h | 3 --- 20 files changed, 49 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 5c13809dc3c8..4fc641d5cb68 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -1399,11 +1399,12 @@ static int get_ringsize(struct i915_gem_context *ctx, } int -i915_gem_user_to_context_sseu(struct drm_i915_private *i915, +i915_gem_user_to_context_sseu(struct intel_gt *gt, const struct drm_i915_gem_context_param_sseu *user, struct intel_sseu *context) { - const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu; + const struct sseu_dev_info *device = >->info.sseu; + struct drm_i915_private *i915 = gt->i915; /* No zeros in any field. */ if (!user->slice_mask || !user->subslice_mask || @@ -1536,7 +1537,7 @@ static int set_sseu(struct i915_gem_context *ctx, goto out_ce; } - ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu); + ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu); if (ret) goto out_ce; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h index 3702b2fb27ab..a133f92bbedb 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h @@ -225,7 +225,7 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it); struct i915_lut_handle *i915_lut_handle_alloc(void); void i915_lut_handle_free(struct i915_lut_handle *lut); -int i915_gem_user_to_context_sseu(struct drm_i915_private *i915, +int i915_gem_user_to_context_sseu(struct intel_gt *gt, const struct drm_i915_gem_context_param_sseu *user, struct intel_sseu *context); diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index b81978890641..7ffc3c751432 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915, int inst = 0; int ret = 0; - if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg) + if (INTEL_GEN(i915) < 9) return 0; if (flags & TEST_RESET) @@ -1255,6 +1255,9 @@ __igt_ctx_sseu(struct drm_i915_private *i915, if (hweight32(engine->sseu.slice_mask) < 2) continue; + if (!engine->gt->info.sseu.has_slice_pg) + continue; + /* * Gen11 VME friendly power-gated configuration with * half enabled sub-slices. diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c index 27ae48049239..b9c8163978a3 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq, *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = lower_32_bits(offset); *cs++ = upper_32_bits(offset); - *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu); + *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); intel_ring_advance(rq, cs); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 3af58df3b13e..af08fdddd972 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -705,7 +705,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) /* Use the whole device by default */ engine->sseu = - intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu); + intel_sseu_from_device_info(&engine->gt->info.sseu); intel_engine_init_workarounds(engine); intel_engine_init_whitelist(engine); @@ -1071,7 +1071,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine, struct intel_instdone *instdone) { struct drm_i915_private *i915 = engine->i915; - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + const struct sseu_dev_info *sseu = &engine->gt->info.sseu; struct intel_uncore *uncore = engine->uncore; u32 mmio_base = engine->mmio_base; int slice; diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index de95930f8627..b1748fa67eca 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -655,4 +655,6 @@ void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p) { drm_printf(p, "available engines: %x\n", info->engine_mask); + + intel_sseu_dump(&info->sseu, p); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index bb7551867c00..6d39a4a11bf3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -116,6 +116,9 @@ struct intel_gt { /* Media engine access to SFC per instance */ u8 vdbox_sfc_access; + + /* Slice/subslice/EU info */ + struct sseu_dev_info sseu; } info; }; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..9e28b2f9df72 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3422,7 +3422,7 @@ __execlists_update_reg_state(const struct intel_context *ce, /* RPCS */ if (engine->class == RENDER_CLASS) { regs[CTX_R_PWR_CLK_STATE] = - intel_sseu_make_rpcs(engine->i915, &ce->sseu); + intel_sseu_make_rpcs(engine->gt, &ce->sseu); i915_oa_init_reg_state(ce, engine); } diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 296391deeb94..97ba14ad52e4 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1062,11 +1062,12 @@ static bool gen6_rps_enable(struct intel_rps *rps) static int chv_rps_max_freq(struct intel_rps *rps) { struct drm_i915_private *i915 = rps_to_i915(rps); + struct intel_gt *gt = rps_to_gt(rps); u32 val; val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); - switch (RUNTIME_INFO(i915)->sseu.eu_total) { + switch (gt->info.sseu.eu_total) { case 8: /* (2 * 4) config */ val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT; diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 006f9118b319..e29f0785b3c5 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -130,7 +130,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, static void gen12_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; u8 s_en; u32 dss_en; @@ -165,7 +165,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt) static void gen11_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; u8 s_en; u32 ss_en; @@ -194,7 +194,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt) static void gen10_sseu_info_init(struct intel_gt *gt) { struct intel_uncore *uncore = gt->uncore; - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); int s, ss; const int eu_mask = 0xff; @@ -270,7 +270,7 @@ static void gen10_sseu_info_init(struct intel_gt *gt) static void cherryview_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; u32 fuse; u8 subslice_mask = 0; @@ -327,7 +327,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; struct intel_device_info *info = mkwrite_device_info(i915); - struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; int s, ss; u32 fuse2, eu_disable, subslice_mask; @@ -431,7 +431,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) static void bdw_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; int s, ss; u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ @@ -517,7 +517,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt) static void hsw_sseu_info_init(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; u32 fuse1; u8 subslice_mask = 0; int s, ss; @@ -602,10 +602,11 @@ void intel_sseu_info_init(struct intel_gt *gt) gen12_sseu_info_init(gt); } -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, +u32 intel_sseu_make_rpcs(struct intel_gt *gt, const struct intel_sseu *req_sseu) { - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + struct drm_i915_private *i915 = gt->i915; + const struct sseu_dev_info *sseu = >->info.sseu; bool subslice_pg = sseu->has_subslice_pg; u8 slices, subslices; u32 rpcs = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index f9c007f001e7..23ba6c2ebe70 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -98,7 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, void intel_sseu_info_init(struct intel_gt *gt); -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, +u32 intel_sseu_make_rpcs(struct intel_gt *gt, const struct intel_sseu *req_sseu); void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..dbafd923e5a1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -404,7 +404,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, static void skl_tune_iz_hashing(struct intel_engine_cs *engine, struct i915_wa_list *wal) { - struct drm_i915_private *i915 = engine->i915; + struct intel_gt *gt = engine->gt; u8 vals[3] = { 0, 0, 0 }; unsigned int i; @@ -415,7 +415,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine, * Only consider slices where one, and only one, subslice has 7 * EUs */ - if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) + if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) continue; /* @@ -424,7 +424,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine, * * -> 0 <= ss <= 3; */ - ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; + ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; vals[i] = 3 - ss; } @@ -1036,7 +1036,7 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) { - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + const struct sseu_dev_info *sseu = &i915->gt.info.sseu; unsigned int slice, subslice; u32 l3_en, mcr, mcr_mask; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index c10ae1660e53..d44061033f23 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -68,7 +68,6 @@ struct __guc_ads_blob { static void __guc_ads_init(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); - struct drm_i915_private *dev_priv = gt->i915; struct __guc_ads_blob *blob = guc->ads_blob; const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; u32 base; @@ -100,7 +99,7 @@ static void __guc_ads_init(struct intel_guc *guc) } /* System info */ - blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); + blob->system_info.slice_enabled = hweight8(gt->info.sseu.slice_mask); blob->system_info.rcs_enabled = 1; blob->system_info.bcs_enabled = 1; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c893a82c2d99..16b012b5673d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_printer p = drm_seq_file_printer(m); - intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); + intel_sseu_print_topology(&dev_priv->gt.info.sseu, &p); return 0; } @@ -1624,7 +1624,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { #define SS_MAX 6 - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); + const struct intel_gt_info *info = &dev_priv->gt.info; u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; int s, ss; @@ -1681,7 +1681,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { #define SS_MAX 3 - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); + const struct intel_gt_info *info = &dev_priv->gt.info; u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; int s, ss; @@ -1739,7 +1739,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, static void bdw_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); + const struct intel_gt_info *info = &dev_priv->gt.info; u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); int s; @@ -1802,7 +1802,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, static int i915_sseu_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); + const struct intel_gt_info *info = &dev_priv->gt.info; struct sseu_dev_info sseu; intel_wakeref_t wakeref; diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index 40390b2352b1..421613219ae9 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -12,7 +12,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_i915_private *i915 = to_i915(dev); - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + const struct sseu_dev_info *sseu = &i915->gt.info.sseu; drm_i915_getparam_t *param = data; int value; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 99b4a0261b13..678ddec3237f 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -426,7 +426,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m) static void error_print_instdone(struct drm_i915_error_state_buf *m, const struct intel_engine_coredump *ee) { - const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; + const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; int slice; int subslice; @@ -626,8 +626,8 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m, intel_device_info_print_static(&error->device_info, &p); intel_device_info_print_runtime(&error->runtime_info, &p); - intel_sseu_print_topology(&error->runtime_info.sseu, &p); intel_gt_info_print(&error->gt->info, &p); + intel_sseu_print_topology(&error->gt->info.sseu, &p); intel_driver_caps_print(&error->driver_caps, &p); } diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 25329b7600c9..37631ce0699b 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -2196,7 +2196,7 @@ static int gen8_configure_context(struct i915_gem_context *ctx, if (!intel_context_pin_if_active(ce)) continue; - flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu); + flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu); err = gen8_modify_context(ce, flex, count); intel_context_unpin(ce); @@ -2340,7 +2340,7 @@ oa_configure_all_contexts(struct i915_perf_stream *stream, if (engine->class != RENDER_CLASS) continue; - regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu); + regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu); err = gen8_modify_self(ce, regs, num_regs, active); if (err) @@ -2740,8 +2740,7 @@ static void get_default_sseu_config(struct intel_sseu *out_sseu, struct intel_engine_cs *engine) { - const struct sseu_dev_info *devinfo_sseu = - &RUNTIME_INFO(engine->i915)->sseu; + const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu; *out_sseu = intel_sseu_from_device_info(devinfo_sseu); @@ -2766,7 +2765,7 @@ get_sseu_config(struct intel_sseu *out_sseu, drm_sseu->engine.engine_instance != engine->uabi_instance) return -EINVAL; - return i915_gem_user_to_context_sseu(engine->i915, drm_sseu, out_sseu); + return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu); } /** diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index c1ebda9b5627..fed337ad7b68 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz, static int query_topology_info(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) { - const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; + const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu; struct drm_i915_query_topology_info topo; u32 slice_length, subslice_length, eu_length, total_length; int ret; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index d8daf224cbd3..3f5dc37d2b7c 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -29,7 +29,6 @@ #include "display/intel_de.h" #include "intel_device_info.h" #include "i915_drv.h" -#include "gt/intel_sseu.h" #define PLATFORM_NAME(x) [INTEL_##x] = #x static const char * const platform_names[] = { @@ -115,8 +114,6 @@ void intel_device_info_print_static(const struct intel_device_info *info, void intel_device_info_print_runtime(const struct intel_runtime_info *info, struct drm_printer *p) { - intel_sseu_dump(&info->sseu, p); - drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); drm_printf(p, "CS timestamp frequency: %u Hz\n", info->cs_timestamp_frequency_hz); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index ce2ccee9b49b..f6f897c06cc8 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -219,9 +219,6 @@ struct intel_runtime_info { u8 num_sprites[I915_MAX_PIPES]; u8 num_scalers[I915_MAX_PIPES]; - /* Slice/subslice/EU info */ - struct sseu_dev_info sseu; - u32 rawclk_freq; u32 cs_timestamp_frequency_hz; -- 2.24.1 From jose.souza at intel.com Fri Jun 26 01:01:47 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Thu, 25 Jun 2020 18:01:47 -0700 Subject: [Intel-gfx] [PATCH v2 1/5] drm/i915: Add plane damage clips property Message-ID: <20200626010151.221388-1-jose.souza@intel.com> This property will be used by PSR2 software tracking, adding it to GEN12+. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a11bb675f9b3..b66008b80589 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -35,6 +35,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_atomic_uapi.h> +#include <drm/drm_damage_helper.h> #include <drm/drm_dp_helper.h> #include <drm/drm_edid.h> #include <drm/drm_fourcc.h> @@ -16475,6 +16476,9 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; drm_plane_create_zpos_immutable_property(&cursor->base, zpos); + if (INTEL_GEN(dev_priv) >= 12) + drm_plane_enable_fb_damage_clips(&cursor->base); + drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); return cursor; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 3cd461bf9131..d03860fef2d7 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -34,6 +34,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_color_mgmt.h> #include <drm/drm_crtc.h> +#include <drm/drm_damage_helper.h> #include <drm/drm_fourcc.h> #include <drm/drm_plane_helper.h> #include <drm/drm_rect.h> @@ -3156,6 +3157,9 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, drm_plane_create_zpos_immutable_property(&plane->base, plane_id); + if (INTEL_GEN(dev_priv) >= 12) + drm_plane_enable_fb_damage_clips(&plane->base); + drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); return plane; -- 2.27.0 From jose.souza at intel.com Fri Jun 26 01:01:48 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Thu, 25 Jun 2020 18:01:48 -0700 Subject: [Intel-gfx] [PATCH v2 2/5] drm/i915: Reorder intel_psr2_config_valid() In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <20200626010151.221388-2-jose.souza@intel.com> Future patches will bring PSR2 selective fetch configuration validation but most of the configuration checks will be used for HW tracking and selective fetch so the reoder was necessary. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 50 ++++++++++++------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 86bf7a76f93d..611cb8d74811 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -681,21 +681,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - /* - * Some platforms lack PSR2 HW tracking and instead require manual - * tracking by software. In this case, the driver is required to track - * the areas that need updates and program hardware to send selective - * updates. - * - * So until the software tracking is implemented, PSR2 needs to be - * disabled for platforms without PSR2 HW tracking. - */ - if (!HAS_PSR_HW_TRACKING(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, - "No PSR2 HW tracking in the platform\n"); - return false; - } - /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC @@ -707,6 +692,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + if (crtc_state->crc_enabled) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); + return false; + } + if (INTEL_GEN(dev_priv) >= 12) { psr_max_h = 5120; psr_max_v = 3200; @@ -721,14 +712,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, max_bpp = 24; } - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", - crtc_hdisplay, crtc_vdisplay, - psr_max_h, psr_max_v); - return false; - } - if (crtc_state->pipe_bpp > max_bpp) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, pipe bpp %d > max supported %d\n", @@ -749,9 +732,26 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (crtc_state->crc_enabled) { + /* + * Some platforms lack PSR2 HW tracking and instead require manual + * tracking by software. In this case, the driver is required to track + * the areas that need updates and program hardware to send selective + * updates. + * + * So until the software tracking is implemented, PSR2 needs to be + * disabled for platforms without PSR2 HW tracking. + */ + if (!HAS_PSR_HW_TRACKING(dev_priv)) { drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); + "No PSR2 HW tracking in the platform\n"); + return false; + } + + if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", + crtc_hdisplay, crtc_vdisplay, + psr_max_h, psr_max_v); return false; } -- 2.27.0 From jose.souza at intel.com Fri Jun 26 01:01:49 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Thu, 25 Jun 2020 18:01:49 -0700 Subject: [Intel-gfx] [PATCH v2 3/5] drm/i915: Add PSR2 selective fetch registers In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <20200626010151.221388-3-jose.souza@intel.com> This registers will be used to implement PSR2 manual tracking/selective fetch. v2: - Fixed typo in _PLANE_SEL_FETCH_BASE - Renamed PSR2_MAN_TRK_CTL bits to better match spec names - Renamed _PLANE_SEL_FETCH_* to better match spec names BSpec: 55229 BSpec: 50424 BSpec: 50420 Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f09120cac89a..8b6eb42b63db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4585,6 +4585,18 @@ enum { #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) #define PSR2_SU_STATUS_FRAMES 8 +#define _PSR2_MAN_TRK_CTL_A 0x60910 +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 +#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) +#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) +#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) +#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) + /* VGA port control */ #define ADPA _MMIO(0x61100) #define PCH_ADPA _MMIO(0xe1100) @@ -7148,7 +7160,52 @@ enum { #define PLANE_COLOR_CTL(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) -#/* SKL new cursor registers */ +#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 +#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 +#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 +#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 +#define _SEL_FETCH_PLANE_BASE_5_A 0x70920 +#define _SEL_FETCH_PLANE_BASE_6_A 0x70940 +#define _SEL_FETCH_PLANE_BASE_7_A 0x70960 +#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 +#define _SEL_FETCH_PLANE_BASE_1_B 0x70990 + +#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ + _SEL_FETCH_PLANE_BASE_1_A, \ + _SEL_FETCH_PLANE_BASE_2_A, \ + _SEL_FETCH_PLANE_BASE_3_A, \ + _SEL_FETCH_PLANE_BASE_4_A, \ + _SEL_FETCH_PLANE_BASE_5_A, \ + _SEL_FETCH_PLANE_BASE_6_A, \ + _SEL_FETCH_PLANE_BASE_7_A, \ + _SEL_FETCH_PLANE_BASE_CUR_A) +#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) +#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ + _SEL_FETCH_PLANE_BASE_1_A + \ + _SEL_FETCH_PLANE_BASE_A(plane)) + +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 +#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ + _SEL_FETCH_PLANE_CTL_1_A - \ + _SEL_FETCH_PLANE_BASE_1_A) +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) + +#define _SEL_FETCH_PLANE_POS_1_A 0x70894 +#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ + _SEL_FETCH_PLANE_POS_1_A - \ + _SEL_FETCH_PLANE_BASE_1_A) + +#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 +#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ + _SEL_FETCH_PLANE_SIZE_1_A - \ + _SEL_FETCH_PLANE_BASE_1_A) + +#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ + _SEL_FETCH_PLANE_OFFSET_1_A - \ + _SEL_FETCH_PLANE_BASE_1_A) + +/* SKL new cursor registers */ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) @@ -7794,11 +7851,12 @@ enum { # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) -#define CHICKEN_PAR1_1 _MMIO(0x42080) +#define CHICKEN_PAR1_1 _MMIO(0x42080) #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) -#define DPA_MASK_VBLANK_SRD (1 << 15) -#define FORCE_ARB_IDLE_PLANES (1 << 14) -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) +#define DPA_MASK_VBLANK_SRD (1 << 15) +#define FORCE_ARB_IDLE_PLANES (1 << 14) +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) +#define IGNORE_PSR2_HW_TRACKING (1 << 1) #define CHICKEN_PAR2_1 _MMIO(0x42090) #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) -- 2.27.0 From jose.souza at intel.com Fri Jun 26 01:01:50 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Thu, 25 Jun 2020 18:01:50 -0700 Subject: [Intel-gfx] [PATCH v2 4/5] drm/i915: Initial implementation of PSR2 selective fetch In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <20200626010151.221388-4-jose.souza@intel.com> All GEN12 platforms supports PSR2 selective fetch but not all GEN12 platforms supports PSR2 hardware tracking(aka RKL). This feature consists in software programming registers with the damaged area of each plane this way hardware will only fetch from memory those areas and sent the PSR2 selective update blocks to panel, saving even more power. But as initial step it is only enabling the full frame fetch at every flip, the actual selective fetch part will come in a future patch. Also this is only handling the page flip side, it is still completely missing frontbuffer modifications, that is why the enable_psr2_sel_fetch parameter was added. BSpec: 55229 Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 3 + .../drm/i915/display/intel_display_debugfs.c | 3 + .../drm/i915/display/intel_display_types.h | 3 + drivers/gpu/drm/i915/display/intel_psr.c | 95 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_psr.h | 5 + drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_params.c | 5 + drivers/gpu/drm/i915/i915_params.h | 1 + 8 files changed, 103 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b66008b80589..eb3a4f317b01 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15114,6 +15114,8 @@ static void commit_pipe_config(struct intel_atomic_state *state, if (new_crtc_state->update_pipe) intel_pipe_fastset(old_crtc_state, new_crtc_state); + + intel_psr2_program_trans_man_trk_ctl(new_crtc_state); } if (dev_priv->display.atomic_update_watermarks) @@ -15155,6 +15157,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, intel_color_load_luts(new_crtc_state); intel_pre_plane_update(state, crtc); + intel_psr2_sel_fetch_update(state, crtc); if (new_crtc_state->update_pipe) intel_encoders_update_pipe(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d1cb48b3f462..4c9591f7ed92 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); seq_printf(m, "%d\t%d\n", frame, su_blocks); } + + seq_printf(m, "PSR2 selective fetch: %s\n", + enableddisabled(psr->psr2_sel_fetch_enabled)); } unlock: diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..44c98ae3964e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -931,6 +931,7 @@ struct intel_crtc_state { bool has_psr; bool has_psr2; + bool enable_psr2_sel_fetch; u32 dc3co_exitline; /* @@ -1073,6 +1074,8 @@ struct intel_crtc_state { /* For DSB related info */ struct intel_dsb *dsb; + + u32 psr2_man_track_ctl; }; enum intel_pipe_crc_source { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 611cb8d74811..078987a878b0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -553,6 +553,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FAST_WAKE(7); } + if (dev_priv->psr.psr2_sel_fetch_enabled) + intel_de_write(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), + PSR2_MAN_TRK_CTL_ENABLE); + else if (HAS_PSR2_SEL_FETCH(dev_priv)) + intel_de_write(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); + /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. @@ -663,6 +671,38 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; } +static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_plane_state *plane_state; + struct intel_plane *plane; + int i; + + if (!dev_priv->params.enable_psr2_sel_fetch) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 sel fetch not enabled, disabled by parameter\n"); + return false; + } + + if (crtc_state->uapi.async_flip) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 sel fetch not enabled, async flip enabled\n"); + return false; + } + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 sel fetch not enabled, plane rotated\n"); + return false; + } + } + + return crtc_state->enable_psr2_sel_fetch = true; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -732,22 +772,17 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - /* - * Some platforms lack PSR2 HW tracking and instead require manual - * tracking by software. In this case, the driver is required to track - * the areas that need updates and program hardware to send selective - * updates. - * - * So until the software tracking is implemented, PSR2 needs to be - * disabled for platforms without PSR2 HW tracking. - */ - if (!HAS_PSR_HW_TRACKING(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, - "No PSR2 HW tracking in the platform\n"); - return false; + if (HAS_PSR2_SEL_FETCH(dev_priv)) { + if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && + !HAS_PSR_HW_TRACKING(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, + "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); + return false; + } } - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { + if (!crtc_state->enable_psr2_sel_fetch && + (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", crtc_hdisplay, crtc_vdisplay, @@ -898,6 +933,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, val |= EXITLINE_ENABLE; intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); } + + if (HAS_PSR_HW_TRACKING(dev_priv)) + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, + dev_priv->psr.psr2_sel_fetch_enabled ? + IGNORE_PSR2_HW_TRACKING : 0); } static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, @@ -919,6 +959,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, /* DC5/DC6 requires at least 6 idle frames */ val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); dev_priv->psr.dc3co_exit_delay = val; + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; /* * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR @@ -1115,6 +1156,32 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) intel_psr_exit(dev_priv); } +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct i915_psr *psr = &dev_priv->psr; + + if (!HAS_PSR2_SEL_FETCH(dev_priv) || + !crtc_state->enable_psr2_sel_fetch) + return; + + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), + crtc_state->psr2_man_track_ctl); +} + +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + + if (!crtc_state->enable_psr2_sel_fetch) + return; + + crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE | + PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; +} + /** * intel_psr_update - Update PSR state * @intel_dp: Intel DP diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index b4515186d5f4..6a83c8e682e6 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -13,6 +13,8 @@ struct drm_connector_state; struct drm_i915_private; struct intel_crtc_state; struct intel_dp; +struct intel_crtc; +struct intel_atomic_state; #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) void intel_psr_init_dpcd(struct intel_dp *intel_dp); @@ -43,5 +45,8 @@ void intel_psr_atomic_check(struct drm_connector *connector, struct drm_connector_state *old_state, struct drm_connector_state *new_state); void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp); +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_PSR_H__ */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9aad3ec979bd..038bd57e429e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -503,6 +503,7 @@ struct i915_psr { bool link_standby; bool colorimetry_support; bool psr2_enabled; + bool psr2_sel_fetch_enabled; u8 sink_sync_latency; ktime_t last_entry_attempt; ktime_t last_exit; @@ -1651,6 +1652,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) #define HAS_PSR_HW_TRACKING(dev_priv) \ (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) +#define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12) #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index a7b61e6ec508..da686f8bcb09 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -102,6 +102,11 @@ i915_param_named(psr_safest_params, bool, 0400, "is helpfull to detect if PSR issues are related to bad values set in " " VBT. (0=use VBT paramters, 1=use safest parameters)"); +i915_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, + "Enable PSR2 selective fetch " + "(0=disabled, 1=enabled) " + "Default: 0"); + i915_param_named_unsafe(force_probe, charp, 0400, "Force probe the driver for specified devices. " "See CONFIG_DRM_I915_FORCE_PROBE for details."); diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 53fb5ba8fbed..330c03e2b4f7 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,6 +54,7 @@ struct drm_printer; param(int, enable_fbc, -1, 0600) \ param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0600) \ + param(bool, enable_psr2_sel_fetch, false, 0600) \ param(int, disable_power_well, -1, 0400) \ param(int, enable_ips, 1, 0600) \ param(int, invert_brightness, 0, 0600) \ -- 2.27.0 From jose.souza at intel.com Fri Jun 26 01:01:51 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Thu, 25 Jun 2020 18:01:51 -0700 Subject: [Intel-gfx] [PATCH v2 5/5] drm/i915/display: Implement WA 1408330847 In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <20200626010151.221388-5-jose.souza@intel.com> >From the 3 WAs for PSR2 man track/selective fetch this is only one needed when doing single full frames at every flip. Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 078987a878b0..8755ab87740d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -553,13 +553,21 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FAST_WAKE(7); } - if (dev_priv->psr.psr2_sel_fetch_enabled) + if (dev_priv->psr.psr2_sel_fetch_enabled) { + /* WA 1408330847 */ + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || + IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, + DIS_RAM_BYPASS_PSR2_MAN_TRACK, + DIS_RAM_BYPASS_PSR2_MAN_TRACK); + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), PSR2_MAN_TRK_CTL_ENABLE); - else if (HAS_PSR2_SEL_FETCH(dev_priv)) + } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); + } /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is @@ -1099,6 +1107,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) psr_status_mask, 2000)) drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); + /* WA 1408330847 */ + if (dev_priv->psr.psr2_sel_fetch_enabled && + (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) || + IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))) + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, + DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); + /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8b6eb42b63db..4ab491426210 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7852,6 +7852,7 @@ enum { # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) #define CHICKEN_PAR1_1 _MMIO(0x42080) +#define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) #define DPA_MASK_VBLANK_SRD (1 << 15) #define FORCE_ARB_IDLE_PLANES (1 << 14) -- 2.27.0 From airlied at gmail.com Fri Jun 26 01:36:54 2020 From: airlied at gmail.com (Dave Airlie) Date: Fri, 26 Jun 2020 11:36:54 +1000 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <874kqzndxj.fsf@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> <874kqzndxj.fsf@intel.com> Message-ID: <CAPM=9twpNDqS=HDANHOiqy0JeqkqfpiA3bBsZn3vB4QVGJLGGQ@mail.gmail.com> On Fri, 26 Jun 2020 at 05:27, Jani Nikula <jani.nikula at linux.intel.com> wrote: > > On Fri, 26 Jun 2020, Dave Airlie <airlied at gmail.com> wrote: > > WTUF? > > > > How did this ever land in my tree, there is no ACK on this from anyone > > in core dma-buf, > > > > Intel team, clean your house up here, I'm going to have to ask you to > > stop Chris merging stuff without oversight, if this sort of thing > > happens, this is totally unacceptable. > > There's no argument, an ack is required. > > In fairness to the i915 maintainers, though, this particular commit was > merged via drm-misc-next [1]. > > As a side note, there seem to be extra checks in place for acks when > applying non-i915 patches to drm-intel; there are no such checks for > drm-misc. Sorry Jani, thanks for chasing that down. drm-misc we need to oversight a bit more, I don't think we should be landing things that affect core code with single company acks. Dave. From jsnitsel at redhat.com Fri Jun 26 01:41:26 2020 From: jsnitsel at redhat.com (Jerry Snitselaar) Date: Thu, 25 Jun 2020 18:41:26 -0700 Subject: [Intel-gfx] [PATCH 00/13] iommu: Remove usage of dev->archdata.iommu In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200626014126.vbjw5jh7wqrpm4oc@cantor> On Thu Jun 25 20, Joerg Roedel wrote: >From: Joerg Roedel <jroedel at suse.de> > >Hi, > >here is a patch-set to remove the usage of dev->archdata.iommu from >the IOMMU code in the kernel and replace its uses by the iommu per-device >private data field. The changes also remove the field entirely from >the architectures which no longer need it. > >On PowerPC the field is called dev->archdata.iommu_domain and was only >used by the PAMU IOMMU driver. It gets removed as well. > >The patches have been runtime tested on Intel VT-d and compile tested >with allyesconfig for: > > * x86 (32 and 64 bit) > * arm and arm64 > * ia64 (only drivers/ because build failed for me in > arch/ia64) > * PPC64 > >Besides that the changes also survived my IOMMU tree compile tests. > >Please review. > >Regards, > > Joerg > >Joerg Roedel (13): > iommu/exynos: Use dev_iommu_priv_get/set() > iommu/vt-d: Use dev_iommu_priv_get/set() > iommu/msm: Use dev_iommu_priv_get/set() > iommu/omap: Use dev_iommu_priv_get/set() > iommu/rockchip: Use dev_iommu_priv_get/set() > iommu/tegra: Use dev_iommu_priv_get/set() > iommu/pamu: Use dev_iommu_priv_get/set() > iommu/mediatek: Do no use dev->archdata.iommu > x86: Remove dev->archdata.iommu pointer > ia64: Remove dev->archdata.iommu pointer > arm: Remove dev->archdata.iommu pointer > arm64: Remove dev->archdata.iommu pointer > powerpc/dma: Remove dev->archdata.iommu_domain > > arch/arm/include/asm/device.h | 3 --- > arch/arm64/include/asm/device.h | 3 --- > arch/ia64/include/asm/device.h | 3 --- > arch/powerpc/include/asm/device.h | 3 --- > arch/x86/include/asm/device.h | 3 --- > .../gpu/drm/i915/selftests/mock_gem_device.c | 10 ++++++++-- > drivers/iommu/exynos-iommu.c | 20 +++++++++---------- > drivers/iommu/fsl_pamu_domain.c | 8 ++++---- > drivers/iommu/intel/iommu.c | 18 ++++++++--------- > drivers/iommu/msm_iommu.c | 4 ++-- > drivers/iommu/mtk_iommu.h | 2 ++ > drivers/iommu/mtk_iommu_v1.c | 10 ++++------ > drivers/iommu/omap-iommu.c | 20 +++++++++---------- > drivers/iommu/rockchip-iommu.c | 8 ++++---- > drivers/iommu/tegra-gart.c | 8 ++++---- > drivers/iommu/tegra-smmu.c | 8 ++++---- > .../media/platform/s5p-mfc/s5p_mfc_iommu.h | 4 +++- > 17 files changed, 64 insertions(+), 71 deletions(-) > >-- >2.27.0 > Reviewed-by: Jerry Snitselaar <jsnitsel at redhat.com> From sfr at canb.auug.org.au Fri Jun 26 01:43:28 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Fri, 26 Jun 2020 11:43:28 +1000 Subject: [Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree Message-ID: <20200626114328.71ae6193@canb.auug.org.au> Hi all, Today's linux-next merge of the drm-misc tree got a conflict in: drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c between commit: eaad0c3aa978 ("drm/amdgpu: rename direct to immediate for VM updates") from the Linus' and commit: b1a8ef952a25 ("drm/amdgpu: move ttm bo->offset to amdgpu_bo") from the drm-misc tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 28bdfb3ac33d,2a7a6f62d627..000000000000 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@@ -144,8 -141,8 +144,8 @@@ static void amdgpu_vm_sdma_copy_ptes(st src += p->num_dw_left * 4; - pe += amdgpu_gmc_sign_extend(bo->tbo.offset); + pe += amdgpu_bo_gpu_offset_no_check(bo); - trace_amdgpu_vm_copy_ptes(pe, src, count, p->direct); + trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate); amdgpu_vm_copy_pte(p->adev, ib, pe, src, count); } @@@ -171,8 -168,8 +171,8 @@@ static void amdgpu_vm_sdma_set_ptes(str { struct amdgpu_ib *ib = p->job->ibs; - pe += amdgpu_gmc_sign_extend(bo->tbo.offset); + pe += amdgpu_bo_gpu_offset_no_check(bo); - trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->direct); + trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate); if (count < 3) { amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags, count, incr); -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200626/865de53c/attachment.sig> From airlied at gmail.com Fri Jun 26 04:37:57 2020 From: airlied at gmail.com (Dave Airlie) Date: Fri, 26 Jun 2020 14:37:57 +1000 Subject: [Intel-gfx] DG1 VRAM question Message-ID: <CAPM=9tyx209haPSokJhA_qOi1PRhoVNPX3MTyNHsq68b=Y5W2A@mail.gmail.com> I can't figure this out easily so I'd thought I'd just ask, but does DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of mappable VRAM vs non-mappable in patches, is it planned to just thrash the aperture if userspace ever ties to map too much of it. Are pagetables stored in the visible RAM space? Dave. From sumit.semwal at linaro.org Fri Jun 26 04:43:53 2020 From: sumit.semwal at linaro.org (Sumit Semwal) Date: Fri, 26 Jun 2020 10:13:53 +0530 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <CAKMK7uErpxoFrT_K==7-PMGyg_eqF07T50eYfh5BFQLzra7TbQ@mail.gmail.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> <874kqzndxj.fsf@intel.com> <CAKMK7uErpxoFrT_K==7-PMGyg_eqF07T50eYfh5BFQLzra7TbQ@mail.gmail.com> Message-ID: <CAO_48GEa2ZgMph-1ZdsMcOdomZc4zNuRcNn_DoBZS3sNZa-LTg@mail.gmail.com> On Fri, 26 Jun 2020 at 01:24, Daniel Vetter <daniel at ffwll.ch> wrote: > > Ignoring everything else ... > > On Thu, Jun 25, 2020 at 9:28 PM Jani Nikula <jani.nikula at linux.intel.com> wrote: > > As a side note, there seem to be extra checks in place for acks when > > applying non-i915 patches to drm-intel; there are no such checks for > > drm-misc. > > One option to generalize that that I pondered is to consult > get_maintainers.pl asking for git repo link, and if that returns > something else, then insist that there's an ack from a relevant > maintainer. It's a bit of typing, but I think the bigger problem is > that there's a ton of false positives. Right; for the particular patch, I wasn't even in the to: or cc: field and that made it slip from my radar. I would definitely ask any one sending patches for dma-buf directory to follow the get_maintainers.pl religiously. > > But maybe that's a good thing, would give some motivation to keep > MAINTAINERS updated. > > The other issue is though that drm-misc is plenty used to merge > patches even when the respective maintainers are absent for weeks, or > unresponsive. If we just blindly implement that rule, then the only > possible Ack for these would be Dave&me as subsystem maintainers, and > I don't want to be in the business of stamping approvals for all this > stuff. Much better if people just collaborate. > > So I think an ack check would be nice, but probably not practical. > > Plus in this situation here drm-misc.git actually is the main repo, > and we wont ever be able to teach a script to make a judgement call of > whether that patch has the right amount of review on it. > -Daniel Best, Sumit. From matthew.d.roper at intel.com Fri Jun 26 05:41:55 2020 From: matthew.d.roper at intel.com (Matt Roper) Date: Thu, 25 Jun 2020 22:41:55 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Extend Wa_14010685332 to all ICP+ PCH's In-Reply-To: <20200625173425.GB22095@msatwood-mobl> References: <20200617180006.4130501-1-matthew.d.roper@intel.com> <20200625173425.GB22095@msatwood-mobl> Message-ID: <20200626054155.GI544333@mdroper-desk1.amr.corp.intel.com> On Thu, Jun 25, 2020 at 10:34:25AM -0700, Matt Atwood wrote: > O Wed, Jun 17, 2020 at 11:00:06AM -0700, Matt Roper wrote: > > This workaround now also applies to TGL and RKL, so extend the PCH test > > to just capture everthing ICP and beyond. > > > > Signed-off-by: Matt Roper <matthew.d.roper at intel.com> > Reviewed-by: Matt Atwood <matthew.s.atwood at intel.com> Applied to dinq. Thanks for the review. Matt > > --- > > drivers/gpu/drm/i915/i915_irq.c | 6 ++---- > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 8e823ba25f5f..923822343311 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -2907,10 +2907,8 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) > > GEN3_IRQ_RESET(uncore, SDE); > > > > - /* Wa_14010685332:icl,jsl,ehl */ > > - if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP || > > - INTEL_PCH_TYPE(dev_priv) == PCH_JSP || > > - INTEL_PCH_TYPE(dev_priv) == PCH_MCC) { > > + /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */ > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { > > intel_uncore_rmw(uncore, SOUTH_CHICKEN1, > > SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); > > intel_uncore_rmw(uncore, SOUTH_CHICKEN1, > > -- > > 2.24.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 From christian.koenig at amd.com Fri Jun 26 07:03:31 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Fri, 26 Jun 2020 09:03:31 +0200 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <CAO_48GEa2ZgMph-1ZdsMcOdomZc4zNuRcNn_DoBZS3sNZa-LTg@mail.gmail.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> <874kqzndxj.fsf@intel.com> <CAKMK7uErpxoFrT_K==7-PMGyg_eqF07T50eYfh5BFQLzra7TbQ@mail.gmail.com> <CAO_48GEa2ZgMph-1ZdsMcOdomZc4zNuRcNn_DoBZS3sNZa-LTg@mail.gmail.com> Message-ID: <b7b1eb80-aa98-2d54-2344-dbc2e4bc0492@amd.com> Am 26.06.20 um 06:43 schrieb Sumit Semwal: > On Fri, 26 Jun 2020 at 01:24, Daniel Vetter <daniel at ffwll.ch> wrote: >> Ignoring everything else ... >> >> On Thu, Jun 25, 2020 at 9:28 PM Jani Nikula <jani.nikula at linux.intel.com> wrote: >>> As a side note, there seem to be extra checks in place for acks when >>> applying non-i915 patches to drm-intel; there are no such checks for >>> drm-misc. >> One option to generalize that that I pondered is to consult >> get_maintainers.pl asking for git repo link, and if that returns >> something else, then insist that there's an ack from a relevant >> maintainer. It's a bit of typing, but I think the bigger problem is >> that there's a ton of false positives. > Right; for the particular patch, I wasn't even in the to: or cc: field > and that made it slip from my radar. I would definitely ask any one > sending patches for dma-buf directory to follow the get_maintainers.pl > religiously. >> But maybe that's a good thing, would give some motivation to keep >> MAINTAINERS updated. Should I maybe add myself as maintainer as well? I've written enough stuff in there to know the code quite a bit. Christian. >> >> The other issue is though that drm-misc is plenty used to merge >> patches even when the respective maintainers are absent for weeks, or >> unresponsive. If we just blindly implement that rule, then the only >> possible Ack for these would be Dave&me as subsystem maintainers, and >> I don't want to be in the business of stamping approvals for all this >> stuff. Much better if people just collaborate. >> >> So I think an ack check would be nice, but probably not practical. >> >> Plus in this situation here drm-misc.git actually is the main repo, >> and we wont ever be able to teach a script to make a judgement call of >> whether that patch has the right amount of review on it. >> -Daniel > Best, > Sumit. From lucas.de.marchi at gmail.com Fri Jun 26 07:14:47 2020 From: lucas.de.marchi at gmail.com (Lucas De Marchi) Date: Fri, 26 Jun 2020 00:14:47 -0700 Subject: [Intel-gfx] DG1 VRAM question In-Reply-To: <CAPM=9tyx209haPSokJhA_qOi1PRhoVNPX3MTyNHsq68b=Y5W2A@mail.gmail.com> References: <CAPM=9tyx209haPSokJhA_qOi1PRhoVNPX3MTyNHsq68b=Y5W2A@mail.gmail.com> Message-ID: <CAKi4VA+3oEPXnH-EKgKkxohf=7+jrDPy-fNfX6QvGBj7QsNYLw@mail.gmail.com> Cc Matt and Daniele On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied at gmail.com> wrote: > > I can't figure this out easily so I'd thought I'd just ask, but does > DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of We'd need to go via lmem since there's no mappable aperture. There are a few patches in tree for that (see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not available.")) but more missing. Lucas De Marchi > mappable VRAM vs non-mappable in patches, is it planned to just thrash > the aperture if userspace ever ties to map too much of it. > > Are pagetables stored in the visible RAM space? > > Dave. > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi From janusz.krzysztofik at linux.intel.com Fri Jun 26 08:04:20 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Fri, 26 Jun 2020 10:04:20 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 5/8] tests/core_hotunplug: Add 'GEM address space' variant In-Reply-To: <159311416692.202818.5204035808205731710@macragge.hardline.pl> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-6-janusz.krzysztofik@linux.intel.com> <159311416692.202818.5204035808205731710@macragge.hardline.pl> Message-ID: <59b682f41b6779da22bbfe55ffec3cfda4e62729.camel@linux.intel.com> Hi Micha?, thanks for review. On Thu, 2020-06-25 at 21:42 +0200, Micha? Winiarski wrote: > Quoting Janusz Krzysztofik (2020-06-22 18:44:12) > > Verify if an additional address space associated with an open device > > file descriptor is cleaned up correctly on device hotunplug. > > > > v2: rebase on upstream, update includes order > > > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > > --- > > tests/core_hotunplug.c | 31 +++++++++++++++++++++++++++++++ > > 1 file changed, 31 insertions(+) > > > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > > index 0892e1927..18a963564 100644 > > --- a/tests/core_hotunplug.c > > +++ b/tests/core_hotunplug.c > > @@ -30,6 +30,7 @@ > > #include <unistd.h> > > > > #include "i915/gem.h" > > +#include "i915/gem_vm.h" > > #include "igt.h" > > #include "igt_device_scan.h" > > #include "igt_kmod.h" > > @@ -332,6 +333,29 @@ static void hotreplug_lateclose(void) > > healthcheck(); > > } > > > > +static void vm_hotunplug_lateclose(void) > > +{ > > + struct hotunplug priv; > > + > > + prepare_for_rescan(&priv); > > + > > + gem_require_vm(priv.fd.drm); > > + > > + local_debug("creating additional GEM user address space"); > > + igt_ignore_warn(gem_vm_create(priv.fd.drm)); > > Why the "ignore_warn"? This deserves a comment. > And perhaps a word of information about why we picked > this partucular operation in the commit message (vm_create). > This is a regression test, right? Hmm, I didn't intend it to be a regression test. The purpose was generally the same as of other hotunplug-lateclose subtests - exercise the driver behaviour on hotunplug and lateclose. This subtest was intended to perform still the same exercise, only under different conditions, or different use case of the driver. In particular, hotunplug is performed here with an additional address space associated with an open file descriptor. We are not interested in exercising that address space (that's why igt_ignore_warn), only in checking if it is cleaned up on time so hotunplug-lateclose operations are still safe from late dma_unmap issues. Let me try to reword the commit description so it better reflects this idea. Thanks, Janusz > > LGTM otherwise (but again - see previous patches): > > Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> > > -Micha? From chris at chris-wilson.co.uk Fri Jun 26 08:10:11 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 09:10:11 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159310696106.31486.9034080828697272264@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> <159310696106.31486.9034080828697272264@build.alporthouse.com> Message-ID: <159315901171.15982.4604268132167952820@build.alporthouse.com> Quoting Chris Wilson (2020-06-25 18:42:41) > Quoting Christian K?nig (2020-06-25 16:47:09) > > Am 25.06.20 um 17:10 schrieb Chris Wilson: > > > We have the DAG of fences, we can use that information to avoid adding > > > an implicit coupling between execution contexts. > > > > No, we can't. And it sounds like you still have not understood the > > underlying problem. > > > > See this has nothing to do with the fences itself or their DAG. > > > > When you depend on userspace to do another submission so your fence can > > start processing you end up depending on whatever userspace does. > > HW dependency on userspace is explicit in the ABI and client APIs, and > the direct control userspace has over the HW. > > > This in turn means when userspace calls a system call (or does page > > fault) it is possible that this ends up in the reclaim code path. > > We have both said the very same thing. > > > And while we want to avoid it both Daniel and I already discussed this > > multiple times and we agree it is still a must have to be able to do > > fence waits in the reclaim code path. > > But came to the opposite conclusion. For doing that wait harms the > unrelated caller and the reclaim is opportunistic. There is no need for > that caller to reclaim that page, when it can have any other. Why did you > even choose that page to reclaim? Inducing latency in the caller is a bug, > has been reported previously as a bug, and still considered a bug. [But at > the end of the day, if the system is out of memory, then you have to pick > a victim.] An example Thread A Thread B submit(VkCmdWaitEvents) recvfrom(ThreadB) ... sendto(ThreadB) \- alloc_page \- direct reclaim \- dma_fence_wait(A) VkSetEvent() Regardless of that actual deadlock, waiting on an arbitrary fence incurs an unbounded latency which is unacceptable for direct reclaim. Online debugging can indefinitely suspend fence signaling, and the only guarantee we make of forward progress, in some cases, is process termination. -Chris From janusz.krzysztofik at linux.intel.com Fri Jun 26 08:26:58 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Fri, 26 Jun 2020 10:26:58 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 6/8] tests/core_hotunplug: Add 'GEM object' variant In-Reply-To: <159311468453.202818.18055756190300144808@macragge.hardline.pl> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-7-janusz.krzysztofik@linux.intel.com> <159311468453.202818.18055756190300144808@macragge.hardline.pl> Message-ID: <1ce855eb72b4bb1205734f46ca95bd770b7ced62.camel@linux.intel.com> Hi Micha?, Thanks for review. On Thu, 2020-06-25 at 21:51 +0200, Micha? Winiarski wrote: > Quoting Janusz Krzysztofik (2020-06-22 18:44:13) > > GEM objects belonging to user file descriptors still open on device > > hotunplug may exhibit still more driver issues. Add a subtest that > > implements this scenario. > > > > v2: rebase on upstream > > > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > > --- > > tests/core_hotunplug.c | 30 ++++++++++++++++++++++++++++++ > > 1 file changed, 30 insertions(+) > > > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > > index 18a963564..c30d98a69 100644 > > --- a/tests/core_hotunplug.c > > +++ b/tests/core_hotunplug.c > > @@ -356,6 +356,29 @@ static void vm_hotunplug_lateclose(void) > > healthcheck(); > > } > > > > +static void gem_hotunplug_lateclose(void) > > +{ > > + struct hotunplug priv; > > + > > + prepare_for_rescan(&priv); > > + > > + igt_require_gem(priv.fd.drm); > > + > > + local_debug("creating a GEM user object"); > > + igt_ignore_warn(gem_create(priv.fd.drm, 4096)); > > Same as previous one. > (note - we could just check for proper error when we attempt to close this > handle after unplug, and the same thing applies to the previous one with the vm) Oh, now I see what you meant in case of the address space variant. I was thinking about that. We may need another subtests, or a group of subtests, for exercising the driver's safety from post-hotunplug attempts to use the removed device, not only to close it. I decided to provide those variants later and call them 'hotunplug-lateuse*'. However, now I see that we may perfectly exercise the driver's resistance to late use of additional user resources while having those resources already created. Then, let me extend applicable members of this patch series with those checks. Thanks, Janusz > > LGTM otherwise. > > Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> > > -Micha? From janusz.krzysztofik at linux.intel.com Fri Jun 26 08:51:26 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Fri, 26 Jun 2020 10:51:26 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 8/8] tests/core_hotunplug: Add 'GEM batch' variant In-Reply-To: <159311533123.202818.8673731295694520597@macragge.hardline.pl> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-9-janusz.krzysztofik@linux.intel.com> <159311533123.202818.8673731295694520597@macragge.hardline.pl> Message-ID: <b5710b0e9e4fdfe78a2def1e79ac977c936cefdb.camel@linux.intel.com> Hi Micha?, On Thu, 2020-06-25 at 22:02 +0200, Micha? Winiarski wrote: > Quoting Janusz Krzysztofik (2020-06-22 18:44:15) > > Verify if a device with a GEM batch job still running on a GPU can be > > hot-unplugged cleanly and released, then recovered. > > > > v2: rebase on upstream > > > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > > --- > > tests/core_hotunplug.c | 34 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 34 insertions(+) > > > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > > index 7cb699cc2..672ff661d 100644 > > --- a/tests/core_hotunplug.c > > +++ b/tests/core_hotunplug.c > > @@ -33,6 +33,7 @@ > > #include "i915/gem_vm.h" > > #include "igt.h" > > #include "igt_device_scan.h" > > +#include "igt_dummyload.h" > > #include "igt_kmod.h" > > #include "igt_sysfs.h" > > > > @@ -408,6 +409,32 @@ static void prime_hotunplug_lateclose(void) > > healthcheck(); > > } > > > > +static void batch_hotunplug_lateclose(void) > > +{ > > + struct hotunplug priv; > > + igt_spin_t *spin; > > + > > + prepare_for_rescan(&priv); > > + > > + igt_require_gem(priv.fd.drm); > > + > > + local_debug("running dummy load"); > > + spin = __igt_spin_new(priv.fd.drm, .flags = IGT_SPIN_POLL_RUN | > > + IGT_SPIN_NO_PREEMPTION); > > Do we need IGT_SPIN_NO_PREEMPTION here? Assuming my understanding of IGT_SPIN_NO_PREEMPTION was correct, my intention was to exercise the driver's ability to cancel persistent GPU tasks on hotunplug and clean up their associated resources on time in order to avoid late dma_unmap issues. Please advise if you still think this this flag not needed. > We're also leaking spin here... And I don't think we can just call igt_spin_free > after unplug, can we? If you mean memory occupied by the spin structure, I know leaking it looks bad but I think that shouldn't be a problem in a user space process that is going to exit soon. But ayway, let me try what happens on late igt_spin_free attempt. Thanks, Janusz > > -Micha? > > > + igt_spin_busywait_until_started(spin); > > + > > + local_debug("hot unplugging the device"); > > + device_unplug(priv.fd.sysfs_dev); > > + > > + local_debug("late closing the removed device instance"); > > + close(priv.fd.drm); > > + > > + local_debug("recovering the device"); > > + bus_rescan(priv.fd.sysfs_bus); > > + > > + healthcheck(); > > +} > > + > > /* Main */ > > > > igt_main > > @@ -501,4 +528,11 @@ igt_main > > > > igt_fixture > > igt_abort_on_f(failure, "%s\n", failure); > > + > > + igt_describe("Check if a device with a still running batch can be cleanly unplugged, then released and recovered"); > > + igt_subtest("batch-hotunplug-lateclose") > > + batch_hotunplug_lateclose(); > > + > > + igt_fixture > > + igt_abort_on_f(failure, "%s\n", failure); > > } > > -- > > 2.21.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From christian.koenig at amd.com Fri Jun 26 08:56:15 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Fri, 26 Jun 2020 10:56:15 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> <159310696106.31486.9034080828697272264@build.alporthouse.com> <159315901171.15982.4604268132167952820@build.alporthouse.com> <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> Message-ID: <9a3ce245-1169-9e10-517d-d78058cab0e1@amd.com> Hi Daniel, could you help my explaining to Christoph why this doesn't work? We have exercised this multiple times in the past month and I'm really surprised that anybody is still trying this approach. Thanks, Christian. Am 26.06.20 um 10:54 schrieb Christian K?nig: > Am 26.06.20 um 10:10 schrieb Chris Wilson: >> Quoting Chris Wilson (2020-06-25 18:42:41) >>> Quoting Christian K?nig (2020-06-25 16:47:09) >>>> Am 25.06.20 um 17:10 schrieb Chris Wilson: >>>>> We have the DAG of fences, we can use that information to avoid >>>>> adding >>>>> an implicit coupling between execution contexts. >>>> No, we can't. And it sounds like you still have not understood the >>>> underlying problem. >>>> >>>> See this has nothing to do with the fences itself or their DAG. >>>> >>>> When you depend on userspace to do another submission so your fence >>>> can >>>> start processing you end up depending on whatever userspace does. >>> HW dependency on userspace is explicit in the ABI and client APIs, and >>> the direct control userspace has over the HW. >>> >>>> This in turn means when userspace calls a system call (or does page >>>> fault) it is possible that this ends up in the reclaim code path. >>> We have both said the very same thing. > > Then I'm really wondering why you don't come to the same conclusion :) > >>>> And while we want to avoid it both Daniel and I already discussed this >>>> multiple times and we agree it is still a must have to be able to do >>>> fence waits in the reclaim code path. >>> But came to the opposite conclusion. For doing that wait harms the >>> unrelated caller and the reclaim is opportunistic. There is no need for >>> that caller to reclaim that page, when it can have any other. Why >>> did you >>> even choose that page to reclaim? Inducing latency in the caller is >>> a bug, >>> has been reported previously as a bug, and still considered a bug. >>> [But at >>> the end of the day, if the system is out of memory, then you have to >>> pick >>> a victim.] > > Correct. But this is also not limited to the reclaim path as any > kernel system call and page fault can cause a problem as well. > > In other words "fence -> userspace -> page fault -> fence" or "fence > -> userspace -> system call -> fence" can easily cause the same > problem and that is not avoidable. > >> An example >> >> Thread A??????????????? Thread B >> >> ????submit(VkCmdWaitEvents) >> ????recvfrom(ThreadB)??? ...??? sendto(ThreadB) >> ??????????????????? \- alloc_page >> ???????????????????? \- direct reclaim >> ????????????????????? \- dma_fence_wait(A) >> ????VkSetEvent() >> >> Regardless of that actual deadlock, waiting on an arbitrary fence incurs >> an unbounded latency which is unacceptable for direct reclaim. >> >> Online debugging can indefinitely suspend fence signaling, and the only >> guarantee we make of forward progress, in some cases, is process >> termination. > > And exactly that is what doesn't work. You don't have any forward > progress any more because you ran into a software deadlock. > > In other words the signaling of a fence depends on the welfare of > userspace. You can try to kill userspace, but this can wait for the > fence you try to signal in the first place. > > See the difference to a deadlock on the GPU is that you can can always > kill a running job or process even if it is stuck with something else. > But if the kernel is deadlocked with itself you can't kill the process > any more, the only option left to get cleanly out of this is to reboot > the kernel. > > The only way to avoid this would be to never ever wait for the fence > in the kernel and then your whole construct is not useful any more. > > I'm running out of ideas how to explain what the problem is here.... > > Regards, > Christian. > >> -Chris > From stanislav.lisovskiy at intel.com Fri Jun 26 09:16:06 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Fri, 26 Jun 2020 12:16:06 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200625200003.12436-1-ville.syrjala@linux.intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> Message-ID: <20200626091606.GA29269@intel.com> On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > The linetime watermark is a 9 bit value, which gives us > a maximum linetime of just below 64 usec. If the linetime > exceeds that value we currently just discard the high bits > and program the rest into the register, which angers the > state checker. > > To avoid that let's just clamp the value to the max. I believe > it should be perfectly fine to program a smaller linetime wm > than strictly required, just means the hardware may fetch data > sooner than strictly needed. We are further reassured by the > fact that with DRRS the spec tells us to program the smaller > of the two linetimes corresponding to the two refresh rates. > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index a11bb675f9b3..d486d675166f 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) > { > const struct drm_display_mode *adjusted_mode = > &crtc_state->hw.adjusted_mode; > + int linetime_wm; > > if (!crtc_state->hw.enable) > return 0; > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > - adjusted_mode->crtc_clock); > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > + adjusted_mode->crtc_clock); > + > + return min(linetime_wm, 0x1ff); Are we actually doing the right thing here? I just mean that we get value 543 in the bug because pixel rate is 14874 which doesn't seem correct. Stan > } > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > { > const struct drm_display_mode *adjusted_mode = > &crtc_state->hw.adjusted_mode; > + int linetime_wm; > > if (!crtc_state->hw.enable) > return 0; > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > - cdclk_state->logical.cdclk); > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > + cdclk_state->logical.cdclk); > + > + return min(linetime_wm, 0x1ff); > } > > static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > const struct drm_display_mode *adjusted_mode = > &crtc_state->hw.adjusted_mode; > - u16 linetime_wm; > + int linetime_wm; > > if (!crtc_state->hw.enable) > return 0; > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > linetime_wm /= 2; > > - return linetime_wm; > + return min(linetime_wm, 0x1ff); > } > > static int hsw_compute_linetime_wm(struct intel_atomic_state *state, > -- > 2.26.2 > From patchwork at emeril.freedesktop.org Fri Jun 26 09:59:03 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 09:59:03 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgU2Vu?= =?utf-8?q?d_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <159316554368.22986.130817435382883180@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev8) URL : https://patchwork.freedesktop.org/series/62816/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8661_full -> Patchwork_18016_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18016_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18016_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18016_full: ### IGT changes ### #### Possible regressions #### * igt at gem_ctx_persistence@legacy-engines-mixed at vebox: - shard-skl: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at gem_ctx_persistence@legacy-engines-mixed at vebox.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl4/igt at gem_ctx_persistence@legacy-engines-mixed at vebox.html Known issues ------------ Here are the changes found in Patchwork_18016_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-iclb: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-iclb1/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [PASS][9] -> [DMESG-FAIL][10] ([i915#54] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +10 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: - shard-kbl: [PASS][13] -> [DMESG-FAIL][14] ([fdo#108145] / [i915#54] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl4/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][15] -> [DMESG-FAIL][16] ([i915#1635] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl4/igt at kms_flip_tiling@flip-changes-tiling.html - shard-kbl: [PASS][17] -> [DMESG-FAIL][18] ([i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl6/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#93] / [i915#95]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl6/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_setmode@basic: - shard-kbl: [PASS][25] -> [FAIL][26] ([i915#31]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl3/igt at kms_setmode@basic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#95]) +12 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl3/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl1/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][29] -> [FAIL][30] ([i915#1820]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [FAIL][31] ([i915#1528]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl9/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl3/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_whisper@basic-queues-all: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk2/igt at gem_exec_whisper@basic-queues-all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-glk7/igt at gem_exec_whisper@basic-queues-all.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36] +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb7/igt at i915_module_load@reload.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][37] ([i915#118] / [i915#95]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-glk6/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_legacy@flip-vs-cursor-legacy: - shard-apl: [FAIL][39] ([IGT#5]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl3/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2: - shard-glk: [FAIL][41] ([i915#79]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-glk8/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +5 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [FAIL][47] ([i915#699]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl1/igt at kms_flip_tiling@flip-changes-tiling.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: - shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-iclb5/igt at kms_psr@psr2_sprite_plane_move.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-b-wait-idle-hang: - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl5/igt at kms_vblank@pipe-b-wait-idle-hang.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl6/igt at kms_vblank@pipe-b-wait-idle-hang.html * igt at kms_vblank@pipe-c-accuracy-idle: - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl3/igt at kms_vblank@pipe-c-accuracy-idle.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl6/igt at kms_vblank@pipe-c-accuracy-idle.html * igt at syncobj_wait@multi-wait-all-signaled: - shard-apl: [DMESG-WARN][61] ([i915#1635] / [i915#95]) -> [PASS][62] +13 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl6/igt at syncobj_wait@multi-wait-all-signaled.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at syncobj_wait@multi-wait-all-signaled.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [TIMEOUT][63] ([i915#1635] / [i915#1958]) -> [INCOMPLETE][64] ([i915#1635] / [i915#1958]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at gem_exec_reloc@basic-concurrent16.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl3/igt at gem_exec_reloc@basic-concurrent16.html * igt at kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: [SKIP][65] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][66] ([fdo#109271] / [fdo#111827]) +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl1/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html * igt at kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [DMESG-FAIL][67] ([i915#1982]) -> [DMESG-WARN][68] ([i915#1982]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl4/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [DMESG-FAIL][69] ([i915#1635] / [i915#95]) -> [FAIL][70] ([i915#1525]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl1/igt at kms_fbcon_fbt@fbc-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-apl: [SKIP][71] ([fdo#109271]) -> [SKIP][72] ([fdo#109271] / [i915#1635]) +5 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl4/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt at perf@gen12-unprivileged-single-ctx-counters: - shard-apl: [SKIP][75] ([fdo#109271] / [i915#1635]) -> [SKIP][76] ([fdo#109271]) +5 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl6/igt at perf@gen12-unprivileged-single-ctx-counters.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at perf@gen12-unprivileged-single-ctx-counters.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18016 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18016: 6f6d00bcff9fbea7969c94a52f4096a719e2733b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/index.html From patchwork at emeril.freedesktop.org Fri Jun 26 10:15:55 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 10:15:55 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_mm=3A_Skip_opportunistic_reclaim_for_dma_pinned_pages?= In-Reply-To: <20200624191417.16735-1-chris@chris-wilson.co.uk> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> Message-ID: <159316655541.22984.12342712279820833963@emeril.freedesktop.org> == Series Details == Series: mm: Skip opportunistic reclaim for dma pinned pages URL : https://patchwork.freedesktop.org/series/78795/ State : warning == Summary == $ dim checkpatch origin/drm-tip 92687c80eb20 mm: Skip opportunistic reclaim for dma pinned pages -:36: WARNING:BAD_SIGN_OFF: Duplicate signature #36: Cc: Jan Kara <jack at suse.cz> total: 0 errors, 1 warnings, 0 checks, 22 lines checked From janusz.krzysztofik at linux.intel.com Fri Jun 26 10:18:00 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Fri, 26 Jun 2020 12:18:00 +0200 Subject: [Intel-gfx] [RFC PATCH i-g-t v2 1/8] tests/core_hotunplug: Duplicate debug messages in dmesg In-Reply-To: <159309887614.186992.12805428537676828006@macragge.hardline.pl> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-2-janusz.krzysztofik@linux.intel.com> <159309887614.186992.12805428537676828006@macragge.hardline.pl> Message-ID: <632af55bd2d4395d3b51898bf51436d05a1bc06c.camel@linux.intel.com> Hi Micha?, Thanks for review. On Thu, 2020-06-25 at 17:27 +0200, Micha? Winiarski wrote: > Quoting Janusz Krzysztofik (2020-06-22 18:44:08) > > The purpose of debug messages displayed by the test is to make > > identification of a subtest phase that fails more easy. Since issues > > exhibited by the test are mostly reported to dmesg, print those debug > > messages to /dev/kmsg as well. > > I'm not a fan of spamming dmesg from IGT and I'd prefer if you add this logging > to the kernel, The idea was to simply log IGT actions, not to log kernel reactions on them which already happens. Doing that from the kernel would probably require modifications to PCI sysfs handling or to sysfs in general. If you see no benefits from that, let's drop this patch. Thanks, Janusz > but let's go over this case-by-case. > > > v2: rebase on upstream > > > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > > --- > > tests/core_hotunplug.c | 38 ++++++++++++++++++++++---------------- > > 1 file changed, 22 insertions(+), 16 deletions(-) > > > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > > index e03f3b945..826645b1f 100644 > > --- a/tests/core_hotunplug.c > > +++ b/tests/core_hotunplug.c > > @@ -49,6 +49,12 @@ struct hotunplug { > > > > /* Helpers */ > > > > +#define local_debug(msg...) \ > > +({ \ > > + igt_debug("%s: %s\n", __func__, msg); \ > > + igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ > > +}) > > + > > static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) > > { > > int len; > > @@ -68,9 +74,9 @@ static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) > > close(priv->fd.sysfs_dev); > > } > > > > -static void prepare(struct hotunplug *priv, char *buf, int buflen) > > +static inline void prepare(struct hotunplug *priv, char *buf, int buflen) > > { > > - igt_debug("opening device\n"); > > + local_debug("opening device"); > > [ 220.458370] [drm:drm_open] pid = 194, minor = 128 > [ 220.460062] [drm:i915_gem_open [i915]] > > > priv->fd.drm = __drm_open_driver(DRIVER_ANY); > > igt_assert(priv->fd.drm >= 0); > > > > @@ -137,14 +143,14 @@ static void bus_rescan(int fd_sysfs_bus) > > close(fd_sysfs_bus); > > } > > > > -static void healthcheck(void) > > +static inline void healthcheck(void) > > { > > int fd_drm; > > > > /* device name may have changed, rebuild IGT device list */ > > igt_devices_scan(true); > > > > - igt_debug("reopening the device\n"); > > + local_debug("reopening the device"); > > Well, this is going to look the same as open, except closing it won't print > drm_lastclose. > > [ 293.957567] [drm:drm_release] open_count = 2 > [ 293.958805] [drm:drm_file_free.part.0] pid = 194, device = 0xe280, open_count = 2 > > > fd_drm = __drm_open_driver(DRIVER_ANY); > > igt_abort_on_f(fd_drm < 0, "Device reopen failure"); > > > > @@ -181,13 +187,13 @@ static void unbind_rebind(void) > > > > prepare(&priv, buf, sizeof(buf)); > > > > - igt_debug("closing the device\n"); > > + local_debug("closing the device"); > > [ 250.157568] [drm:drm_release] open_count = 1 > [ 250.158807] [drm:drm_file_free.part.0] pid = 194, device = 0xe280, open_count = 1 > [ 250.161183] [drm:drm_lastclose] > [ 250.162312] [drm:drm_lastclose] driver lastclose completed > > > close(priv.fd.drm); > > > > - igt_debug("unbinding the driver from the device\n"); > > + local_debug("unbinding the driver from the device"); > > driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); > > [ 1553.868235] bus: 'event_source': remove device i915_0000_00_02.0 > > > > > - igt_debug("rebinding the driver to the device\n"); > > + local_debug("rebinding the driver to the device"); > > driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); > > [ 1592.758219] bus: 'pci': driver_probe_device: matched device 0000:00:02.0 with driver i915 > [ 1592.760543] bus: 'pci': really_probe: probing driver i915 with device 0000:00:02.0 > (...bunch of i915 logs...) > [ 203.961656] driver: 'i915': driver_bound: bound to device '0000:00:02.0' > [ 203.966421] bus: 'pci': really_probe: bound device 0000:00:02.0 to driver i915 > > > > > healthcheck(); > > @@ -199,13 +205,13 @@ static void unplug_rescan(void) > > > > prepare(&priv, NULL, 0); > > > > - igt_debug("closing the device\n"); > > + local_debug("closing the device"); > > close(priv.fd.drm); > > > > - igt_debug("unplugging the device\n"); > > + local_debug("unplugging the device"); > > device_unplug(priv.fd.sysfs_dev); > > [ 60.664163] bus: 'pci': remove device 0000:00:02.0 > > > - igt_debug("recovering the device\n"); > > + local_debug("recovering the device"); > > bus_rescan(priv.fd.sysfs_bus); > > [ 97.384479] bus: 'pci': add device 0000:00:02.0 > > > > > healthcheck(); > > @@ -218,13 +224,13 @@ static void hotunbind_lateclose(void) > > > > prepare(&priv, buf, sizeof(buf)); > > > > - igt_debug("hot unbinding the driver from the device\n"); > > + local_debug("hot unbinding the driver from the device"); > > driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); > > > > - igt_debug("rebinding the driver to the device\n"); > > + local_debug("rebinding the driver to the device"); > > driver_bind(priv.fd.sysfs_drv, priv.dev_bus_addr); > > > > - igt_debug("late closing the unbound device instance\n"); > > + local_debug("late closing the unbound device instance"); > > close(priv.fd.drm); > > Would it be possible to add extra logging allowing us to distinguish this from > regular unbind on i915 side? > > > > > healthcheck(); > > @@ -236,13 +242,13 @@ static void hotunplug_lateclose(void) > > > > prepare(&priv, NULL, 0); > > > > - igt_debug("hot unplugging the device\n"); > > + local_debug("hot unplugging the device"); > > device_unplug(priv.fd.sysfs_dev); > > > > - igt_debug("recovering the device\n"); > > + local_debug("recovering the device"); > > bus_rescan(priv.fd.sysfs_bus); > > > > - igt_debug("late closing the removed device instance\n"); > > + local_debug("late closing the removed device instance"); > > close(priv.fd.drm); > > Same thing here. > > So, not including the hot unplug/unbind, I think the logging is already there. > > Also - note, the "driver core" logs are probably disabled on CI, but I still > think that figuring out how to enable those from IGT (and letting the kernel > just do its regular logging) rather than adding kmsg prints from userspace is a > better approach. > > -Micha? > > > > > healthcheck(); > > -- > > 2.21.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From janusz.krzysztofik at linux.intel.com Fri Jun 26 10:20:48 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Fri, 26 Jun 2020 12:20:48 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 2/8] tests/core_hotunplug: Use PCI device sysfs entry, not DRM In-Reply-To: <159311299636.202818.1800731180873353345@macragge.hardline.pl> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-3-janusz.krzysztofik@linux.intel.com> <159311299636.202818.1800731180873353345@macragge.hardline.pl> Message-ID: <292e43f8d24e58383c40d460abf9fed760332e1b.camel@linux.intel.com> Hi Micha?, On Thu, 2020-06-25 at 21:23 +0200, Micha? Winiarski wrote: > Quoting Janusz Krzysztofik (2020-06-22 18:44:09) > > Future subtests may want to access PCI attributes of the device after > > driver unbind. Refactor prepare() helper. > > > > v2: rebase on upstream > > > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > > --- > > tests/core_hotunplug.c | 68 +++++++++++++++++++++++++----------------- > > 1 file changed, 40 insertions(+), 28 deletions(-) > > > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > > index 826645b1f..35eba9b8a 100644 > > --- a/tests/core_hotunplug.c > > +++ b/tests/core_hotunplug.c > > @@ -55,42 +55,54 @@ struct hotunplug { > > igt_kmsg(KMSG_DEBUG "%s: %s: %s\n", igt_test_name(), __func__, msg); \ > > }) > > > > -static void prepare_for_unbind(struct hotunplug *priv, char *buf, int buflen) > > +static inline int prepare_common(struct hotunplug *priv) > > { > > - int len; > > + int fd_sysfs_drm; > > + > > + local_debug("opening device"); > > + priv->fd.drm = __drm_open_driver(DRIVER_ANY); > > + igt_assert(priv->fd.drm >= 0); > > + > > + fd_sysfs_drm = igt_sysfs_open(priv->fd.drm); > > + igt_assert(fd_sysfs_drm >= 0); > > + > > + return fd_sysfs_drm; > > +} > > + > > +static inline void prepare_for_rebind(struct hotunplug *priv, > > + char *buf, int buflen) > > +{ > > + int fd_sysfs_drm, len; > > > > igt_assert(buflen); > > > > - priv->fd.sysfs_drv = openat(priv->fd.sysfs_dev, "device/driver", > > - O_DIRECTORY); > > - igt_assert(priv->fd.sysfs_drv >= 0); > > + fd_sysfs_drm = prepare_common(priv); > > + > > + priv->fd.sysfs_drv = openat(fd_sysfs_drm, "device/driver", O_DIRECTORY); > > > > - len = readlinkat(priv->fd.sysfs_dev, "device", buf, buflen - 1); > > + len = readlinkat(fd_sysfs_drm, "device", buf, buflen - 1); > > buf[len] = '\0'; > > priv->dev_bus_addr = strrchr(buf, '/'); > > - igt_assert(priv->dev_bus_addr++); > > > > - /* sysfs_dev no longer needed */ > > - close(priv->fd.sysfs_dev); > > + close(fd_sysfs_drm); > > + > > + igt_assert(priv->fd.sysfs_drv >= 0); > > + igt_assert(priv->dev_bus_addr++); > > } > > > > -static inline void prepare(struct hotunplug *priv, char *buf, int buflen) > > +static inline void prepare_for_rescan(struct hotunplug *priv) > > { > > - local_debug("opening device"); > > - priv->fd.drm = __drm_open_driver(DRIVER_ANY); > > - igt_assert(priv->fd.drm >= 0); > > + int fd_sysfs_drm = prepare_common(priv); > > > > - priv->fd.sysfs_dev = igt_sysfs_open(priv->fd.drm); > > - igt_assert(priv->fd.sysfs_dev >= 0); > > + priv->fd.sysfs_dev = openat(fd_sysfs_drm, "device", O_DIRECTORY); > > > > - if (buf) { > > - prepare_for_unbind(priv, buf, buflen); > > - } else { > > - /* prepare for bus rescan */ > > - priv->fd.sysfs_bus = openat(priv->fd.sysfs_dev, > > - "device/subsystem", O_DIRECTORY); > > - igt_assert(priv->fd.sysfs_bus >= 0); > > - } > > + priv->fd.sysfs_bus = openat(fd_sysfs_drm, "device/subsystem", > > + O_DIRECTORY); > > + > > + close(fd_sysfs_drm); > > + > > + igt_assert(priv->fd.sysfs_dev >= 0); > > + igt_assert(priv->fd.sysfs_bus >= 0); > > } > > I find the lifecycle of hotunplug.fd.sysfs_* difficult to follow now... > Would it be possible to keep the "prepare" step simpler and just open everything > everytime? (perhaps closing and opening new ones when called multiple times?) OK. Thanks, Janusz > Or do we need to have drv separate from bus/dev? > > -Micha? > > > > > static const char *failure; > > @@ -124,7 +136,7 @@ static void device_unplug(int fd_sysfs_dev) > > { > > failure = "Device unplug timeout!"; > > igt_set_timeout(60, failure); > > - igt_sysfs_set(fd_sysfs_dev, "device/remove", "1"); > > + igt_sysfs_set(fd_sysfs_dev, "remove", "1"); > > igt_reset_timeout(); > > failure = NULL; > > > > @@ -185,7 +197,7 @@ static void unbind_rebind(void) > > struct hotunplug priv; > > char buf[PATH_MAX]; > > > > - prepare(&priv, buf, sizeof(buf)); > > + prepare_for_rebind(&priv, buf, sizeof(buf)); > > > > local_debug("closing the device"); > > close(priv.fd.drm); > > @@ -203,7 +215,7 @@ static void unplug_rescan(void) > > { > > struct hotunplug priv; > > > > - prepare(&priv, NULL, 0); > > + prepare_for_rescan(&priv); > > > > local_debug("closing the device"); > > close(priv.fd.drm); > > @@ -222,7 +234,7 @@ static void hotunbind_lateclose(void) > > struct hotunplug priv; > > char buf[PATH_MAX]; > > > > - prepare(&priv, buf, sizeof(buf)); > > + prepare_for_rebind(&priv, buf, sizeof(buf)); > > > > local_debug("hot unbinding the driver from the device"); > > driver_unbind(priv.fd.sysfs_drv, priv.dev_bus_addr); > > @@ -240,7 +252,7 @@ static void hotunplug_lateclose(void) > > { > > struct hotunplug priv; > > > > - prepare(&priv, NULL, 0); > > + prepare_for_rescan(&priv); > > > > local_debug("hot unplugging the device"); > > device_unplug(priv.fd.sysfs_dev); > > -- > > 2.21.1 > > > > _______________________________________________ > > igt-dev mailing list > > igt-dev at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/igt-dev From patchwork at emeril.freedesktop.org Fri Jun 26 10:37:08 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 10:37:08 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgbW06?= =?utf-8?q?_Skip_opportunistic_reclaim_for_dma_pinned_pages?= In-Reply-To: <20200624191417.16735-1-chris@chris-wilson.co.uk> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> Message-ID: <159316782845.22983.9008890459165522037@emeril.freedesktop.org> == Series Details == Series: mm: Skip opportunistic reclaim for dma pinned pages URL : https://patchwork.freedesktop.org/series/78795/ State : success == Summary == CI Bug Log - changes from CI_DRM_8665 -> Patchwork_18019 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/index.html Known issues ------------ Here are the changes found in Patchwork_18019 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-bxt-dsi: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-bxt-dsi/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-bxt-dsi/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-byt-j1900/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 39) ------------------------------ Additional (1): fi-tgl-y Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8665 -> Patchwork_18019 CI-20190529: 20190529 CI_DRM_8665: 2cb786fa6506e20b5cb2a10decda11454111e026 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18019: 92687c80eb20bfd0f22e0ff64331fbfb1aa699fc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 92687c80eb20 mm: Skip opportunistic reclaim for dma pinned pages == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/index.html From maarten.lankhorst at linux.intel.com Fri Jun 26 10:52:57 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Fri, 26 Jun 2020 12:52:57 +0200 Subject: [Intel-gfx] [PULL] drm-misc-next Message-ID: <b1e53620-7937-895c-bfcf-ed208be59c7c@linux.intel.com> drm-misc-next-2020-06-26: drm-misc-next for v5.9: Cross-subsystem Changes: - Improve dma-buf docs. Core Changes: - Add NV15, Q410, Q401 yuv formats. - Add uncompressed AFBC modifier. - Add DP helepr for reading Ignore MSA from DPCD. - Add missing panel type for some panels - Optimize drm/mm hole handling. - Constify connector to infoframe functions. - Add debugfs for VRR monitor range. Driver Changes: - Assorted small bugfixes in panfrost, malidp, panel/otm8009a. - Convert tfp410 dt bindings to yaml, and rework time calculations. - Add support for a few more simple panels. - Cleanups and optimizations for ast. - Allow adv7511 and simple-bridge to be used without connector creation. - Cleanups to dw-hdmi function prototypes. - Remove enabled bool from tiny/repaper and mipi-dbi, atomic handles it. - Remove unused header file from dw-mipi-dsi - Begin removing ttm_bo->offset. The following changes since commit 114427b8927a4def2942b2b886f7e4aeae289ccb: drm/panfrost: Use kvfree() to free bo->sgts (2020-06-19 11:00:02 +0100) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2020-06-26 for you to fetch changes up to 41752663b410c6265e24ff0570350b0b05ecdafe: drm/debug: Expose connector VRR monitor range via debugfs (2020-06-25 15:47:14 -0700) ---------------------------------------------------------------- drm-misc-next for v5.9: Cross-subsystem Changes: - Improve dma-buf docs. Core Changes: - Add NV15, Q410, Q401 yuv formats. - Add uncompressed AFBC modifier. - Add DP helepr for reading Ignore MSA from DPCD. - Add missing panel type for some panels - Optimize drm/mm hole handling. - Constify connector to infoframe functions. - Add debugfs for VRR monitor range. Driver Changes: - Assorted small bugfixes in panfrost, malidp, panel/otm8009a. - Convert tfp410 dt bindings to yaml, and rework time calculations. - Add support for a few more simple panels. - Cleanups and optimizations for ast. - Allow adv7511 and simple-bridge to be used without connector creation. - Cleanups to dw-hdmi function prototypes. - Remove enabled bool from tiny/repaper and mipi-dbi, atomic handles it. - Remove unused header file from dw-mipi-dsi - Begin removing ttm_bo->offset. ---------------------------------------------------------------- Angelo Ribeiro (1): drm/bridge: dw-mipi-dsi.c: remove unused header file Ben Davis (2): drm: drm_fourcc: add NV15, Q410, Q401 YUV formats drm: drm_fourcc: Add uncompressed AFBC modifier Bhanuprakash Modem (1): drm/debug: Expose connector VRR monitor range via debugfs Christian K?nig (3): drm/mm: remove unused rb_hole_size() drm/mm: optimize find_hole() as well drm/mm: cleanup and improve next_hole_*_addr() Colin Ian King (1): drm/arm: fix unintentional integer overflow on left shift Daniel Vetter (3): drm/tiny/repaper: Drop edp->enabled drm/mipi-dbi: Remove ->enabled dma-buf: minor doc touch-ups Dmitry Osipenko (1): drm/panel-simple: Add missing connector type for some panels Laurent Pinchart (21): drm: bridge: adv7511: Split EDID read to a separate function drm: bridge: adv7511: Split connector creation to a separate function drm: bridge: adv7511: Implement bridge connector operations drm: bridge: adv7511: Make connector creation optional drm: bridge: Return NULL on error from drm_bridge_get_edid() drm: bridge: simple-bridge: Delegate operations to next bridge drm: bridge: simple-bridge: Make connector creation optional drm: edid: Constify connector argument to infoframe functions drm: bridge: Pass drm_display_info to drm_bridge_funcs .mode_valid() drm: bridge: dw-hdmi: Pass private data pointer to .mode_valid() drm: bridge: dw-hdmi: Pass private data pointer to .configure_phy() drm: bridge: dw-hdmi: Remove unused field from dw_hdmi_plat_data drm: meson: dw-hdmi: Use dw_hdmi context to replace hack drm: bridge: dw-hdmi: Pass drm_display_info to .mode_valid() drm: bridge: dw-hdmi: Constify mode argument to dw_hdmi_phy_ops .init() drm: bridge: dw-hdmi: Constify mode argument to internal functions drm: bridge: dw-hdmi: Pass drm_display_info to dw_hdmi_support_scdc() drm: bridge: dw-hdmi: Split connector creation to a separate function drm: bridge: dw-hdmi: Store current connector in struct dw_hdmi drm: bridge: dw-hdmi: Pass drm_connector to internal functions as needed drm: bridge: dw-hdmi: Make connector creation optional Manasi Navare (1): drm/dp: DRM DP helper for reading Ignore MSA from DPCD Matthias Schiffer (2): dt-bindings: display: simple: add CDTech S070PWS19HP-FC21 and S070SWV29HG-DC44 dt-bindings: display: simple: add Tianma TM070JVHG33 Max Merchel (1): drm/panel: simple: add Tianma TM070JVHG33 Michael Krummsdorf (1): drm/panel: simple: add CDTech S070PWS19HP-FC21 and S070SWV29HG-DC44 Nirmoy Das (6): drm/mm/selftests: fix wrong return type casting drm/amdgpu: move ttm bo->offset to amdgpu_bo drm/radeon: don't use ttm bo->offset drm/qxl: don't use ttm bo->offset drm/vram-helper: don't use ttm bo->offset v4 drm/bochs: use drm_gem_vram_offset to get bo offset v2 Ricardo Ca?uelo (4): dt-bindings: display: ti,tfp410.txt: convert to yaml dt-bindings: display: ti, tfp410.yaml: Redefine ti, deskew property drm/bridge: tfp410: fix de-skew value retrieval from DT drm/bridge: tfp410: Fix setup and hold time calculation Thomas Zimmermann (4): drm/ast: Remove unused code paths for AST 1180 drm/ast: Remove test for device from ast_pm_freeze() drm/ast: Upcast from DRM device to ast structure via to_ast_private() drm/ast: Use per-device logging macros Wei Yongjun (1): drm/panel: otm8009a: Drop unnessary backlight_device_unregister() .../bindings/display/bridge/ti,tfp410.txt | 66 ----- .../bindings/display/bridge/ti,tfp410.yaml | 131 +++++++++ .../bindings/display/panel/panel-simple.yaml | 6 + Documentation/driver-api/dma-buf.rst | 6 +- drivers/dma-buf/dma-buf.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 23 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 30 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 4 +- drivers/gpu/drm/arm/malidp_planes.c | 2 +- drivers/gpu/drm/ast/ast_dp501.c | 24 +- drivers/gpu/drm/ast/ast_drv.c | 4 - drivers/gpu/drm/ast/ast_drv.h | 7 +- drivers/gpu/drm/ast/ast_main.c | 115 ++++---- drivers/gpu/drm/ast/ast_mode.c | 73 +++-- drivers/gpu/drm/ast/ast_post.c | 28 +- drivers/gpu/drm/ast/ast_ttm.c | 2 +- drivers/gpu/drm/bochs/bochs_kms.c | 7 +- drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 137 ++++++--- drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 1 + drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 1 + drivers/gpu/drm/bridge/cdns-dsi.c | 1 + drivers/gpu/drm/bridge/chrontel-ch7033.c | 1 + drivers/gpu/drm/bridge/nwl-dsi.c | 1 + drivers/gpu/drm/bridge/sii9234.c | 1 + drivers/gpu/drm/bridge/sil-sii8620.c | 1 + drivers/gpu/drm/bridge/simple-bridge.c | 113 +++----- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 307 +++++++++++++-------- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 2 +- drivers/gpu/drm/bridge/tc358767.c | 1 + drivers/gpu/drm/bridge/tc358768.c | 1 + drivers/gpu/drm/bridge/thc63lvd1024.c | 1 + drivers/gpu/drm/bridge/ti-tfp410.c | 21 +- drivers/gpu/drm/drm_atomic_helper.c | 3 +- drivers/gpu/drm/drm_bridge.c | 10 +- drivers/gpu/drm/drm_debugfs.c | 22 ++ drivers/gpu/drm/drm_edid.c | 12 +- drivers/gpu/drm/drm_fourcc.c | 12 + drivers/gpu/drm/drm_gem_vram_helper.c | 11 +- drivers/gpu/drm/drm_mipi_dbi.c | 16 +- drivers/gpu/drm/drm_mm.c | 120 +++----- drivers/gpu/drm/drm_probe_helper.c | 4 +- drivers/gpu/drm/i2c/tda998x_drv.c | 1 + drivers/gpu/drm/imx/dw_hdmi-imx.c | 6 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 34 ++- drivers/gpu/drm/omapdrm/dss/dpi.c | 1 + drivers/gpu/drm/omapdrm/dss/sdi.c | 1 + drivers/gpu/drm/omapdrm/dss/venc.c | 1 + drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 1 - drivers/gpu/drm/panel/panel-simple.c | 82 ++++++ drivers/gpu/drm/qxl/qxl_drv.h | 6 +- drivers/gpu/drm/qxl/qxl_kms.c | 5 +- drivers/gpu/drm/qxl/qxl_object.h | 5 - drivers/gpu/drm/qxl/qxl_ttm.c | 9 - drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_object.h | 16 +- drivers/gpu/drm/radeon/radeon_ttm.c | 4 +- drivers/gpu/drm/rcar-du/rcar_dw_hdmi.c | 6 +- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 +- drivers/gpu/drm/selftests/test-drm_mm.c | 32 +-- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 6 +- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 3 +- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 +- drivers/gpu/drm/tiny/ili9225.c | 12 +- drivers/gpu/drm/tiny/repaper.c | 13 +- drivers/gpu/drm/tiny/st7586.c | 11 +- include/drm/bridge/dw_hdmi.h | 26 +- include/drm/drm_bridge.h | 3 + include/drm/drm_dp_helper.h | 8 + include/drm/drm_edid.h | 6 +- include/drm/drm_mipi_dbi.h | 5 - include/uapi/drm/drm_fourcc.h | 34 +++ 73 files changed, 1007 insertions(+), 676 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,tfp410.yaml From janusz.krzysztofik at linux.intel.com Fri Jun 26 10:56:48 2020 From: janusz.krzysztofik at linux.intel.com (Janusz Krzysztofik) Date: Fri, 26 Jun 2020 12:56:48 +0200 Subject: [Intel-gfx] [igt-dev] [RFC PATCH i-g-t v2 7/8] tests/core_hotunplug: Add 'PRIME handle' variant In-Reply-To: <159311502818.202818.9312691111674456282@macragge.hardline.pl> References: <20200622164415.30352-1-janusz.krzysztofik@linux.intel.com> <20200622164415.30352-8-janusz.krzysztofik@linux.intel.com> <159311502818.202818.9312691111674456282@macragge.hardline.pl> Message-ID: <03623ba15cb02bc6edba5d333a95b51baf59f4cd.camel@linux.intel.com> Hi Micha?, On Thu, 2020-06-25 at 21:57 +0200, Micha? Winiarski wrote: > Quoting Janusz Krzysztofik (2020-06-22 18:44:14) > > Even if all device file descriptors are closed on device hotunplug, > > PRIME exported objects may still exists, referenced by still open > > dma-buf file handles. Add a subtest that keeps such handle open on > > device hotunplug. > > > > v2: rebase on upstream > > Would be interesting to see what happens when someone actually imports an > object from unplugged device (or the device is unplugged after it was imported). > But perhaps that's something for the future. Yes, let's keep it relatively simple for now. There seems to be quite a few possible scenarios to cover. However, I'm going to add a very basic use-after-hotunplug check, similar to what we have (hopefully) agreed for context and address space variants. > > Also - the naming should probably be kept distinct from the other "lateclose" > tests, since here we're closing the device FD before the unplug. > Maybe just "prime-hotunplug"? Since we are still interested in exercising the driver behaviour on late closing the prime handle (now this case also explodes inside intel-iommu), let's keep that namig even if we close the device and only keep the prime file open. Thanks, Janusz > But that's up to you - either way: > > Reviewed-by: Micha? Winiarski <michal.winiarski at intel.com> > > -Micha? > > > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik at linux.intel.com> > > --- > > tests/core_hotunplug.c | 36 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 36 insertions(+) > > > > diff --git a/tests/core_hotunplug.c b/tests/core_hotunplug.c > > index c30d98a69..7cb699cc2 100644 > > --- a/tests/core_hotunplug.c > > +++ b/tests/core_hotunplug.c > > @@ -379,6 +379,35 @@ static void gem_hotunplug_lateclose(void) > > healthcheck(); > > } > > > > +static void prime_hotunplug_lateclose(void) > > +{ > > + struct hotunplug priv; > > + uint32_t handle; > > + int dmabuf; > > + > > + prepare_for_rescan(&priv); > > + > > + igt_require_gem(priv.fd.drm); > > + > > + local_debug("creating and PRIME-exporting a GEM object"); > > + handle = gem_create(priv.fd.drm, 4096); > > + dmabuf = prime_handle_to_fd(priv.fd.drm, handle); > > + > > + local_debug("closing the device"); > > + close(priv.fd.drm); > > + > > + local_debug("hot unplugging the device"); > > + device_unplug(priv.fd.sysfs_dev); > > + > > + local_debug("late closing the PRIME file handle"); > > + close(dmabuf); > > + > > + local_debug("recovering the device"); > > + bus_rescan(priv.fd.sysfs_bus); > > + > > + healthcheck(); > > +} > > + > > /* Main */ > > > > igt_main > > @@ -465,4 +494,11 @@ igt_main > > > > igt_fixture > > igt_abort_on_f(failure, "%s\n", failure); > > + > > + igt_describe("Check if a device with a still open PRIME-exported object can be cleanly unplugged, then released and recovered"); > > + igt_subtest("prime-hotunplug-lateclose") > > + prime_hotunplug_lateclose(); > > + > > + igt_fixture > > + igt_abort_on_f(failure, "%s\n", failure); > > } > > -- > > 2.21.1 > > > > _______________________________________________ > > igt-dev mailing list > > igt-dev at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/igt-dev From patchwork at emeril.freedesktop.org Fri Jun 26 11:02:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 11:02:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_implement_Wa=5F14011508470=3Bgen12?= In-Reply-To: <20200624215723.2316-1-matthew.s.atwood@intel.com> References: <20200624215723.2316-1-matthew.s.atwood@intel.com> Message-ID: <159316936351.22984.17089318109820869545@emeril.freedesktop.org> == Series Details == Series: drm/i915: implement Wa_14011508470;gen12 URL : https://patchwork.freedesktop.org/series/78799/ State : success == Summary == CI Bug Log - changes from CI_DRM_8665 -> Patchwork_18020 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/index.html Known issues ------------ Here are the changes found in Patchwork_18020 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [INCOMPLETE][7] ([i915#1242]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-byt-j1900/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-byt-j1900/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-kbl-7560u}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 39) ------------------------------ Additional (1): fi-tgl-y Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8665 -> Patchwork_18020 CI-20190529: 20190529 CI_DRM_8665: 2cb786fa6506e20b5cb2a10decda11454111e026 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18020: 2ac53d393597ee152a2392db4e6f1f47bd76bc78 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2ac53d393597 drm/i915: implement Wa_14011508470;gen12 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/index.html From patchwork at emeril.freedesktop.org Fri Jun 26 11:07:15 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 11:07:15 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv3=2C1/2=5D_drm/i915/dp=3A_Helper_f?= =?utf-8?q?or_checking_DDI=5FBUF=5FCTL_Idle_status?= In-Reply-To: <20200624221108.10038-1-manasi.d.navare@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> Message-ID: <159316963508.22984.3200367759418313844@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status URL : https://patchwork.freedesktop.org/series/78800/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1156c88678a4 drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status -:36: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #36: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1188: + udelay(16); total: 0 errors, 0 warnings, 1 checks, 24 lines checked 9488e350bd12 drm/i915/dp: Helper to check for DDI BUF status to get active From chris at chris-wilson.co.uk Fri Jun 26 11:10:38 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 12:10:38 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> <159310696106.31486.9034080828697272264@build.alporthouse.com> <159315901171.15982.4604268132167952820@build.alporthouse.com> <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> Message-ID: <159316983838.18415.16087585177754322983@build.alporthouse.com> Quoting Christian K?nig (2020-06-26 09:54:19) > Am 26.06.20 um 10:10 schrieb Chris Wilson: > > Quoting Chris Wilson (2020-06-25 18:42:41) > >> Quoting Christian K?nig (2020-06-25 16:47:09) > >>> Am 25.06.20 um 17:10 schrieb Chris Wilson: > >>>> We have the DAG of fences, we can use that information to avoid adding > >>>> an implicit coupling between execution contexts. > >>> No, we can't. And it sounds like you still have not understood the > >>> underlying problem. > >>> > >>> See this has nothing to do with the fences itself or their DAG. > >>> > >>> When you depend on userspace to do another submission so your fence can > >>> start processing you end up depending on whatever userspace does. > >> HW dependency on userspace is explicit in the ABI and client APIs, and > >> the direct control userspace has over the HW. > >> > >>> This in turn means when userspace calls a system call (or does page > >>> fault) it is possible that this ends up in the reclaim code path. > >> We have both said the very same thing. > > Then I'm really wondering why you don't come to the same conclusion :) > > >> > >>> And while we want to avoid it both Daniel and I already discussed this > >>> multiple times and we agree it is still a must have to be able to do > >>> fence waits in the reclaim code path. > >> But came to the opposite conclusion. For doing that wait harms the > >> unrelated caller and the reclaim is opportunistic. There is no need for > >> that caller to reclaim that page, when it can have any other. Why did you > >> even choose that page to reclaim? Inducing latency in the caller is a bug, > >> has been reported previously as a bug, and still considered a bug. [But at > >> the end of the day, if the system is out of memory, then you have to pick > >> a victim.] > > Correct. But this is also not limited to the reclaim path as any kernel > system call and page fault can cause a problem as well. Yes. Hence the effort to avoid blocking and implicit waits in those paths, and why flagging those waits is better than accepting them. The necessary evil should be annotated, everything that is unnecessary should be avoided. And that it is the user->kernel entry points that are important as they are uncontrolled; but directly nesting execution contexts is controlled. And yes direct reclaim is the easiest and most obvious case to avoid unbounded waits inside unknown contexts. > In other words "fence -> userspace -> page fault -> fence" or "fence -> > userspace -> system call -> fence" can easily cause the same problem and > that is not avoidable. > > > An example > > > > Thread A Thread B > > > > submit(VkCmdWaitEvents) > > recvfrom(ThreadB) ... sendto(ThreadB) > > \- alloc_page > > \- direct reclaim > > \- dma_fence_wait(A) > > VkSetEvent() > > > > Regardless of that actual deadlock, waiting on an arbitrary fence incurs > > an unbounded latency which is unacceptable for direct reclaim. > > > > Online debugging can indefinitely suspend fence signaling, and the only > > guarantee we make of forward progress, in some cases, is process > > termination. > > And exactly that is what doesn't work. You don't have any forward > progress any more because you ran into a software deadlock. Only one side is halted. Everything on that side comes to a grinding halt. What about checkpoint/restore, suspend/resume? Where we need to suspend all execution, move all the resources to one side, then put everything back, without cancelling the fences. Same halting problem, no? We also do similar for resets. Suspend the hanging context, move it and all dependent execution off to one side; record what we can, clean up what we have to, then move what remains of the execution back to finish signaling. > In other words the signaling of a fence depends on the welfare of > userspace. You can try to kill userspace, but this can wait for the > fence you try to signal in the first place. The only scenario that fits what you are describing here [userspace ignoring a signal] is if you used an uninterruptible wait. Under what circumstances during normal execution would you do that? If it's someone else's wait, a bug outside of our control. But if you have chosen to cancel the fences, there is nothing to stop the signaling. > See the difference to a deadlock on the GPU is that you can can always > kill a running job or process even if it is stuck with something else. > But if the kernel is deadlocked with itself you can't kill the process > any more, the only option left to get cleanly out of this is to reboot > the kernel. However, I say that is under our control. We know what fences are in an execution context, just as easily as we know that we are inside an execution context. And yes, the easiest, the most restrictive way to control it is to say don't bother. > The only way to avoid this would be to never ever wait for the fence in > the kernel and then your whole construct is not useful any more. I advocate for moving as much as is feasible, for some waits are required by userspace as a necessary evil, into the parallelised pipeline. > I'm running out of ideas how to explain what the problem is here.... Oh we agree on the problem, we appear to disagree that the implicit waits themselves are a serious existent problem. That they are worth effort to avoid or, at least, mitigate. -Chris From patchwork at emeril.freedesktop.org Fri Jun 26 11:29:02 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 11:29:02 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv3=2C1/2=5D_drm/i915/dp=3A_Helper_for_chec?= =?utf-8?q?king_DDI=5FBUF=5FCTL_Idle_status?= In-Reply-To: <20200624221108.10038-1-manasi.d.navare@intel.com> References: <20200624221108.10038-1-manasi.d.navare@intel.com> Message-ID: <159317094286.22986.17243282620677576980@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status URL : https://patchwork.freedesktop.org/series/78800/ State : success == Summary == CI Bug Log - changes from CI_DRM_8665 -> Patchwork_18021 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/index.html Known issues ------------ Here are the changes found in Patchwork_18021 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-byt-j1900/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 39) ------------------------------ Additional (1): fi-tgl-y Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8665 -> Patchwork_18021 CI-20190529: 20190529 CI_DRM_8665: 2cb786fa6506e20b5cb2a10decda11454111e026 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18021: 9488e350bd12e459062f7f9c469ae5229d8ea270 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9488e350bd12 drm/i915/dp: Helper to check for DDI BUF status to get active 1156c88678a4 drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18021/index.html From stanislav.lisovskiy at intel.com Fri Jun 26 11:34:42 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Fri, 26 Jun 2020 11:34:42 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgU2Vu?= =?utf-8?q?d_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <8bb621ba77744f599364bd096447db3d@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> <159316554368.22986.130817435382883180@emeril.freedesktop.org>, <8bb621ba77744f599364bd096447db3d@intel.com> Message-ID: <c42ac508dc914e92a454503607b1c488@intel.com> Sure it is gem as usual. gem_ctx_persistance test is absolutely orthogonal to any hotplug funcitonality. Also it fails almost on weekly basis. Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ________________________________________ From: Saarinen, Jani Sent: Friday, June 26, 2020 2:32:52 PM To: Lisovskiy, Stanislav Subject: FW: [Intel-gfx] ? Fi.CI.IGT: failure for Send a hotplug when edid changes (rev8) Hi, Can you comment if that issue is real on that gem test that fails... > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Patchwork > Sent: perjantai 26. kes?kuuta 2020 12.59 > To: Lisovskiy, Stanislav <stanislav.lisovskiy at intel.com> > Cc: intel-gfx at lists.freedesktop.org > Subject: [Intel-gfx] ? Fi.CI.IGT: failure for Send a hotplug when edid changes (rev8) > > == Series Details == > > Series: Send a hotplug when edid changes (rev8) > URL : https://patchwork.freedesktop.org/series/62816/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8661_full -> Patchwork_18016_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_18016_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_18016_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in > Patchwork_18016_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at gem_ctx_persistence@legacy-engines-mixed at vebox: > - shard-skl: [PASS][1] -> [FAIL][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl6/igt at gem_ctx_persistence@legacy-engines-mixed at vebox.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl4/igt at gem_ctx_persistence@legacy-engines-mixed at vebox.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_18016_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_ctx_isolation@preservation-s3 at rcs0: > - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +1 similar issue > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html > > * igt at i915_module_load@reload-with-fault-injection: > - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > tglb6/igt at i915_module_load@reload-with-fault-injection.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > tglb5/igt at i915_module_load@reload-with-fault-injection.html > > * igt at kms_big_fb@y-tiled-64bpp-rotate-0: > - shard-iclb: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > iclb1/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html > > * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: > - shard-kbl: [PASS][9] -> [DMESG-FAIL][10] ([i915#54] / [i915#95]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html > > * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: > - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +10 similar issues > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl6/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl7/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html > > * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: > - shard-kbl: [PASS][13] -> [DMESG-FAIL][14] ([fdo#108145] / [i915#54] / > [i915#95]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl4/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html > > * igt at kms_flip_tiling@flip-changes-tiling: > - shard-apl: [PASS][15] -> [DMESG-FAIL][16] ([i915#1635] / [i915#95]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl8/igt at kms_flip_tiling@flip-changes-tiling.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl4/igt at kms_flip_tiling@flip-changes-tiling.html > - shard-kbl: [PASS][17] -> [DMESG-FAIL][18] ([i915#95]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl7/igt at kms_flip_tiling@flip-changes-tiling.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl6/igt at kms_flip_tiling@flip-changes-tiling.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc: > - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap- > wc.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap- > wc.html > > * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: > - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#93] / [i915#95]) +1 > similar issue > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl6/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar > issue > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl4/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_setmode@basic: > - shard-kbl: [PASS][25] -> [FAIL][26] ([i915#31]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl3/igt at kms_setmode@basic.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl4/igt at kms_setmode@basic.html > > * igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm: > - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#95]) +12 > similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl3/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl1/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html > > * igt at perf_pmu@semaphore-busy at rcs0: > - shard-kbl: [PASS][29] -> [FAIL][30] ([i915#1820]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl6/igt at perf_pmu@semaphore-busy at rcs0.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl6/igt at perf_pmu@semaphore-busy at rcs0.html > > > #### Possible fixes #### > > * igt at gem_ctx_persistence@engines-mixed-process at vcs0: > - shard-skl: [FAIL][31] ([i915#1528]) -> [PASS][32] > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl9/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl3/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html > > * igt at gem_exec_whisper@basic-queues-all: > - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > glk2/igt at gem_exec_whisper@basic-queues-all.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > glk7/igt at gem_exec_whisper@basic-queues-all.html > > * igt at i915_module_load@reload: > - shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36] +2 similar issues > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > tglb7/igt at i915_module_load@reload.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > tglb7/igt at i915_module_load@reload.html > > * igt at kms_big_fb@x-tiled-64bpp-rotate-180: > - shard-glk: [DMESG-FAIL][37] ([i915#118] / [i915#95]) -> [PASS][38] +1 > similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > glk6/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html > > * igt at kms_cursor_legacy@flip-vs-cursor-legacy: > - shard-apl: [FAIL][39] ([IGT#5]) -> [PASS][40] > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl3/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2: > - shard-glk: [FAIL][41] ([i915#79]) -> [PASS][42] +1 similar issue > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > glk8/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html > > * igt at kms_flip@flip-vs-suspend at c-dp1: > - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +5 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html > > * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: > - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl6/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html > > * igt at kms_flip_tiling@flip-changes-tiling: > - shard-skl: [FAIL][47] ([i915#699]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl1/igt at kms_flip_tiling@flip-changes-tiling.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl7/igt at kms_flip_tiling@flip-changes-tiling.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: > - shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html > > * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: > - shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html > > * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +2 similar > issues > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > > * igt at kms_psr@psr2_sprite_plane_move: > - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > iclb5/igt at kms_psr@psr2_sprite_plane_move.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > iclb2/igt at kms_psr@psr2_sprite_plane_move.html > > * igt at kms_vblank@pipe-b-wait-idle-hang: > - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl5/igt at kms_vblank@pipe-b-wait-idle-hang.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl6/igt at kms_vblank@pipe-b-wait-idle-hang.html > > * igt at kms_vblank@pipe-c-accuracy-idle: > - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl3/igt at kms_vblank@pipe-c-accuracy-idle.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl6/igt at kms_vblank@pipe-c-accuracy-idle.html > > * igt at syncobj_wait@multi-wait-all-signaled: > - shard-apl: [DMESG-WARN][61] ([i915#1635] / [i915#95]) -> [PASS][62] +13 > similar issues > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl6/igt at syncobj_wait@multi-wait-all-signaled.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl8/igt at syncobj_wait@multi-wait-all-signaled.html > > > #### Warnings #### > > * igt at gem_exec_reloc@basic-concurrent16: > - shard-apl: [TIMEOUT][63] ([i915#1635] / [i915#1958]) -> > [INCOMPLETE][64] ([i915#1635] / [i915#1958]) > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl8/igt at gem_exec_reloc@basic-concurrent16.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl3/igt at gem_exec_reloc@basic-concurrent16.html > > * igt at kms_color_chamelium@pipe-a-ctm-limited-range: > - shard-apl: [SKIP][65] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> > [SKIP][66] ([fdo#109271] / [fdo#111827]) +2 similar issues > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl1/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl8/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html > > * igt at kms_cursor_legacy@flip-vs-cursor-legacy: > - shard-skl: [DMESG-FAIL][67] ([i915#1982]) -> [DMESG-WARN][68] > ([i915#1982]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl4/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html > > * igt at kms_fbcon_fbt@fbc-suspend: > - shard-apl: [DMESG-FAIL][69] ([i915#1635] / [i915#95]) -> [FAIL][70] > ([i915#1525]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl1/igt at kms_fbcon_fbt@fbc-suspend.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl8/igt at kms_fbcon_fbt@fbc-suspend.html > > * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: > - shard-apl: [SKIP][71] ([fdo#109271]) -> [SKIP][72] ([fdo#109271] / > [i915#1635]) +5 similar issues > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl8/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl4/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html > > * igt at kms_plane_alpha_blend@pipe-a-alpha-7efc: > - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] > ([fdo#108145] / [i915#1982]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > skl10/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > skl7/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html > > * igt at perf@gen12-unprivileged-single-ctx-counters: > - shard-apl: [SKIP][75] ([fdo#109271] / [i915#1635]) -> [SKIP][76] > ([fdo#109271]) +5 similar issues > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard- > apl6/igt at perf@gen12-unprivileged-single-ctx-counters.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard- > apl8/igt at perf@gen12-unprivileged-single-ctx-counters.html > > > [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 > [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8661 -> Patchwork_18016 > > CI-20190529: 20190529 > CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18016: 6f6d00bcff9fbea7969c94a52f4096a719e2733b @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm- > tip/Patchwork_18016/index.html > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From christian.koenig at amd.com Fri Jun 26 11:35:30 2020 From: christian.koenig at amd.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Fri, 26 Jun 2020 13:35:30 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159316983838.18415.16087585177754322983@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> <159310696106.31486.9034080828697272264@build.alporthouse.com> <159315901171.15982.4604268132167952820@build.alporthouse.com> <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> <159316983838.18415.16087585177754322983@build.alporthouse.com> Message-ID: <edfaedf3-f6ad-044d-8853-4ee0991a4903@amd.com> Am 26.06.20 um 13:10 schrieb Chris Wilson: > Quoting Christian K?nig (2020-06-26 09:54:19) > [SNIP] >> In other words "fence -> userspace -> page fault -> fence" or "fence -> >> userspace -> system call -> fence" can easily cause the same problem and >> that is not avoidable. >> >>> An example >>> >>> Thread A Thread B >>> >>> submit(VkCmdWaitEvents) >>> recvfrom(ThreadB) ... sendto(ThreadB) >>> \- alloc_page >>> \- direct reclaim >>> \- dma_fence_wait(A) >>> VkSetEvent() >>> >>> Regardless of that actual deadlock, waiting on an arbitrary fence incurs >>> an unbounded latency which is unacceptable for direct reclaim. >>> >>> Online debugging can indefinitely suspend fence signaling, and the only >>> guarantee we make of forward progress, in some cases, is process >>> termination. >> And exactly that is what doesn't work. You don't have any forward >> progress any more because you ran into a software deadlock. > Only one side is halted. Everything on that side comes to a grinding > halt. > > What about checkpoint/restore, suspend/resume? Where we need to suspend > all execution, move all the resources to one side, then put everything > back, without cancelling the fences. Same halting problem, no? What are you talking about? Of course we either wait for all fences to complete or cancel them on suspend. > We also do similar for resets. Suspend the hanging context, move it and > all dependent execution off to one side; record what we can, clean up > what we have to, then move what remains of the execution back to finish > signaling. Yes, but this is not possible in this situation. In the bad case you have a kernel deadlock and that can't be cleaned up in any way. The only solution left in that situation is to reset the system or at least reload the kernel and that is not acceptable. >> In other words the signaling of a fence depends on the welfare of >> userspace. You can try to kill userspace, but this can wait for the >> fence you try to signal in the first place. > The only scenario that fits what you are describing here [userspace > ignoring a signal] is if you used an uninterruptible wait. Under what > circumstances during normal execution would you do that? If it's > someone else's wait, a bug outside of our control. Uninterruptible waits are a necessity. Just take a look at the dma_fence_wait() interface. Why to you think we have ability to wait uninterruptible there? We need this when there is no other way of recovering. For example when operations are already partially flushed to the hardware and can't be aborted any more. > But if you have chosen to cancel the fences, there is nothing to stop > the signaling. And just to repeat myself: You can't cancel the fence! For example assume that canceling the proxy fence would mean that you send a SIGKILL to the process which issued it. But then you need to wait for the SIGKILL to be processed. Now what can happen is that the process is uninterruptible waiting for something which then needs the SIGKILL to be delivered -> kernel deadlock. >> See the difference to a deadlock on the GPU is that you can can always >> kill a running job or process even if it is stuck with something else. >> But if the kernel is deadlocked with itself you can't kill the process >> any more, the only option left to get cleanly out of this is to reboot >> the kernel. > However, I say that is under our control. We know what fences are in an > execution context, just as easily as we know that we are inside an > execution context. And yes, the easiest, the most restrictive way to > control it is to say don't bother. No, that is absolutely not under our control. dma_fences need to be waited on under a lot of different context, including the reclaim path as well as the MMU notifiers, memory pressure callbacks, OOM killer.... Just see Daniels patches on the lockdep fence signaling annotation and what this work bubbled up on problems. >> The only way to avoid this would be to never ever wait for the fence in >> the kernel and then your whole construct is not useful any more. > I advocate for moving as much as is feasible, for some waits are required > by userspace as a necessary evil, into the parallelised pipeline. > >> I'm running out of ideas how to explain what the problem is here.... > Oh we agree on the problem, we appear to disagree that the implicit waits > themselves are a serious existent problem. That they are worth effort to > avoid or, at least, mitigate. No, as far as I can see you don't seem to either understand the problem or the implications of it. The only way to solve this would be to audit the whole Linux kernel and remove all uninterruptible waits and that is not feasible. As long as you don't provide me with a working solution to the problem I've outlined here the whole approach is a clear NAK since it will allow to create really bad kernel deadlocks. Sorry to say that, but this whole thing doesn't look like it is thought through to the end. You should probably take a step back and talk to Daniel here. Regards, Christian. > -Chris From patchwork at emeril.freedesktop.org Fri Jun 26 11:40:49 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 11:40:49 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBW?= =?utf-8?q?RR_capable_attach_prop_in_i915=2C_VRR_debugfs_=28rev3=29?= In-Reply-To: <20200622142519.16214-1-bhanuprakash.modem@intel.com> References: <20200622142519.16214-1-bhanuprakash.modem@intel.com> Message-ID: <159317164923.22985.15672973434024272794@emeril.freedesktop.org> == Series Details == Series: VRR capable attach prop in i915, VRR debugfs (rev3) URL : https://patchwork.freedesktop.org/series/78670/ State : failure == Summary == Applying: drm/i915/dp: Attach and set drm connector VRR property Applying: drm/debug: Expose connector VRR monitor range via debugfs Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_debugfs.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. Applying: Revert "drm/amd/display: Expose connector VRR range via debugfs" Using index info to reconstruct a base tree... M drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c CONFLICT (content): Merge conflict in drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 Revert "drm/amd/display: Expose connector VRR range via debugfs" When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Fri Jun 26 11:46:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 11:46:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_display/ddi=3A_keep_register_indexes_in_a_table?= In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <159317201774.22985.5575110009824454623@emeril.freedesktop.org> == Series Details == Series: display/ddi: keep register indexes in a table URL : https://patchwork.freedesktop.org/series/78806/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1c318e3abcdc drm/i915: move ICL port F hack to intel_bios f1e31b8bd6eb drm/i915/display: fix comment on skl straps 50167b8d3287 drm/i915/display: start description-based ddi initialization 4bb4855c4a15 drm/i915/display: add phy, vbt and ddi indexes -:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #9: one to the other. Right now we already cover part of this by creating kind of -:42: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #42: FILE: drivers/gpu/drm/i915/display/intel_display.c:16809: + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, }, -:43: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #43: FILE: drivers/gpu/drm/i915/display/intel_display.c:16810: + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, }, -:45: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #45: FILE: drivers/gpu/drm/i915/display/intel_display.c:16812: + { .name = "DDI C", .port = PORT_D, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x3, .phy_idx = 0x2, .vbt_idx = 0x2, }, -:46: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #46: FILE: drivers/gpu/drm/i915/display/intel_display.c:16813: + { .name = "DDI D", .port = PORT_E, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x4, .phy_idx = 0x3, .vbt_idx = 0x3, }, -:59: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #59: FILE: drivers/gpu/drm/i915/display/intel_display.c:16818: + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, }, -:60: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #60: FILE: drivers/gpu/drm/i915/display/intel_display.c:16819: + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, }, -:62: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #62: FILE: drivers/gpu/drm/i915/display/intel_display.c:16821: + { .name = "DDI TC1", .port = PORT_D, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x3, .phy_idx = 0x0, .vbt_idx = 0x2, }, -:63: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #63: FILE: drivers/gpu/drm/i915/display/intel_display.c:16822: + { .name = "DDI TC2", .port = PORT_E, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x4, .phy_idx = 0x1, .vbt_idx = 0x3, }, -:64: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #64: FILE: drivers/gpu/drm/i915/display/intel_display.c:16823: + { .name = "DDI TC3", .port = PORT_F, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x5, .phy_idx = 0x2, .vbt_idx = 0x4, }, -:65: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #65: FILE: drivers/gpu/drm/i915/display/intel_display.c:16824: + { .name = "DDI TC4", .port = PORT_G, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x6, .phy_idx = 0x3, .vbt_idx = 0x5, }, -:66: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #66: FILE: drivers/gpu/drm/i915/display/intel_display.c:16825: + { .name = "DDI TC5", .port = PORT_H, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x7, .phy_idx = 0x4, .vbt_idx = 0x6, }, -:67: WARNING:LONG_LINE: line length of 123 exceeds 100 columns #67: FILE: drivers/gpu/drm/i915/display/intel_display.c:16826: + { .name = "DDI TC6", .port = PORT_I, .phy_type = PHY_TYPE_DKL, .ddi_idx = 0x8, .phy_idx = 0x5, .vbt_idx = 0x7, }, -:76: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #76: FILE: drivers/gpu/drm/i915/display/intel_display.c:16831: + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0, }, -:77: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #77: FILE: drivers/gpu/drm/i915/display/intel_display.c:16832: + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1, }, -:78: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #78: FILE: drivers/gpu/drm/i915/display/intel_display.c:16833: + { .name = "DDI C", .port = PORT_C, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x2, .phy_idx = 0x2, .vbt_idx = 0x2, }, -:79: WARNING:LONG_LINE: line length of 121 exceeds 100 columns #79: FILE: drivers/gpu/drm/i915/display/intel_display.c:16834: + { .name = "DDI D", .port = PORT_D, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x3, .phy_idx = 0x0, .vbt_idx = 0x3, }, -:90: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #90: FILE: drivers/gpu/drm/i915/display/intel_display.c:16839: + { .name = "DDI A", .port = PORT_A, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x0, .phy_idx = 0x0, .vbt_idx = 0x0,}, -:91: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #91: FILE: drivers/gpu/drm/i915/display/intel_display.c:16840: + { .name = "DDI B", .port = PORT_B, .phy_type = PHY_TYPE_COMBO, .ddi_idx = 0x1, .phy_idx = 0x1, .vbt_idx = 0x1,}, -:92: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #92: FILE: drivers/gpu/drm/i915/display/intel_display.c:16841: + { .name = "DDI TC1", .port = PORT_C, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x2, .phy_idx = 0x0, .vbt_idx = 0x2,}, -:93: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #93: FILE: drivers/gpu/drm/i915/display/intel_display.c:16842: + { .name = "DDI TC2", .port = PORT_D, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x3, .phy_idx = 0x1, .vbt_idx = 0x3,}, -:94: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #94: FILE: drivers/gpu/drm/i915/display/intel_display.c:16843: + { .name = "DDI TC3", .port = PORT_E, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x4, .phy_idx = 0x2, .vbt_idx = 0x4,}, -:95: WARNING:LONG_LINE: line length of 122 exceeds 100 columns #95: FILE: drivers/gpu/drm/i915/display/intel_display.c:16844: + { .name = "DDI TC4", .port = PORT_F, .phy_type = PHY_TYPE_MG, .ddi_idx = 0x5, .phy_idx = 0x3, .vbt_idx = 0x5,}, total: 0 errors, 23 warnings, 0 checks, 114 lines checked 90085cc968a8 drm/i915/display: use port_info in intel_ddi_init -:134: CHECK:LINE_SPACING: Please don't use multiple blank lines #134: FILE: drivers/gpu/drm/i915/display/intel_ddi.h:51: + total: 0 errors, 0 warnings, 1 checks, 128 lines checked 8e1bf7ebdffd drm/i915/display: replace port to phy conversions in intel_ddi.c From patchwork at emeril.freedesktop.org Fri Jun 26 11:48:11 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 11:48:11 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?display/ddi=3A_keep_register_indexes_in_a_table?= In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <159317209173.22986.3597637010167617470@emeril.freedesktop.org> == Series Details == Series: display/ddi: keep register indexes in a table URL : https://patchwork.freedesktop.org/series/78806/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From bp at alien8.de Fri Jun 26 11:46:03 2020 From: bp at alien8.de (Borislav Petkov) Date: Fri, 26 Jun 2020 13:46:03 +0200 Subject: [Intel-gfx] [PATCH 09/13] x86: Remove dev->archdata.iommu pointer In-Reply-To: <20200625130836.1916-10-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> <20200625130836.1916-10-joro@8bytes.org> Message-ID: <20200626114603.GC27151@zn.tnic> On Thu, Jun 25, 2020 at 03:08:32PM +0200, Joerg Roedel wrote: > From: Joerg Roedel <jroedel at suse.de> > > There are no users left, all drivers have been converted to use the > per-device private pointer offered by IOMMU core. > > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- > arch/x86/include/asm/device.h | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/arch/x86/include/asm/device.h b/arch/x86/include/asm/device.h > index 49bd6cf3eec9..7c0a52ca2f4d 100644 > --- a/arch/x86/include/asm/device.h > +++ b/arch/x86/include/asm/device.h > @@ -3,9 +3,6 @@ > #define _ASM_X86_DEVICE_H > > struct dev_archdata { > -#ifdef CONFIG_IOMMU_API > - void *iommu; /* hook for IOMMU specific extension */ > -#endif > }; > > struct pdev_archdata { > -- Acked-by: Borislav Petkov <bp at suse.de> -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette From patchwork at emeril.freedesktop.org Fri Jun 26 12:10:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 12:10:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgZGlz?= =?utf-8?q?play/ddi=3A_keep_register_indexes_in_a_table?= In-Reply-To: <20200625001120.22810-1-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> Message-ID: <159317343298.22985.15998832950658752373@emeril.freedesktop.org> == Series Details == Series: display/ddi: keep register indexes in a table URL : https://patchwork.freedesktop.org/series/78806/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8665 -> Patchwork_18023 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18023 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18023, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18023: ### CI changes ### #### Possible regressions #### * boot: - fi-hsw-4770: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-hsw-4770/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-hsw-4770/boot.html ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - fi-tgl-y: NOTRUN -> [FAIL][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-tgl-y/igt at runner@aborted.html - fi-tgl-u2: NOTRUN -> [FAIL][4] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-tgl-u2/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_18023 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-byt-j1900/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +3 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Additional (1): fi-tgl-y Missing (8): fi-ilk-m540 fi-ehl-1 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8665 -> Patchwork_18023 CI-20190529: 20190529 CI_DRM_8665: 2cb786fa6506e20b5cb2a10decda11454111e026 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18023: 8e1bf7ebdffd468b4f30978f703d89324e4791b8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8e1bf7ebdffd drm/i915/display: replace port to phy conversions in intel_ddi.c 90085cc968a8 drm/i915/display: use port_info in intel_ddi_init 4bb4855c4a15 drm/i915/display: add phy, vbt and ddi indexes 50167b8d3287 drm/i915/display: start description-based ddi initialization f1e31b8bd6eb drm/i915/display: fix comment on skl straps 1c318e3abcdc drm/i915: move ICL port F hack to intel_bios == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18023/index.html From patchwork at emeril.freedesktop.org Fri Jun 26 12:15:48 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 12:15:48 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5Bv3=2C1/3=5D_drm/i915/bios=3A_Parse_HOBL?= =?utf-8?q?_parameter?= In-Reply-To: <20200625002906.116594-1-jose.souza@intel.com> References: <20200625002906.116594-1-jose.souza@intel.com> Message-ID: <159317374821.22984.11722893292417371719@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/3] drm/i915/bios: Parse HOBL parameter URL : https://patchwork.freedesktop.org/series/78807/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Fri Jun 26 12:36:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 12:36:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv3=2C1/3=5D_drm/i915/bios=3A_Parse_HOBL_pa?= =?utf-8?q?rameter?= In-Reply-To: <20200625002906.116594-1-jose.souza@intel.com> References: <20200625002906.116594-1-jose.souza@intel.com> Message-ID: <159317497309.22985.3321956882063259720@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/3] drm/i915/bios: Parse HOBL parameter URL : https://patchwork.freedesktop.org/series/78807/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8665 -> Patchwork_18024 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18024 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18024, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18024: ### IGT changes ### #### Possible regressions #### * igt at runner@aborted: - fi-cml-s: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-cml-s/igt at runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_18024 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][2] -> [DMESG-WARN][3] ([i915#1982]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [INCOMPLETE][6] ([i915#1242]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-byt-j1900/igt at i915_module_load@reload.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at kms_busy@basic at flip.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][12] ([i915#1982]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][15] ([i915#62] / [i915#92]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92]) -> [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 39) ------------------------------ Additional (1): fi-tgl-y Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8665 -> Patchwork_18024 CI-20190529: 20190529 CI_DRM_8665: 2cb786fa6506e20b5cb2a10decda11454111e026 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18024: 64f114f63b3ea34d46cd6580f0526b2b6448a319 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 64f114f63b3e drm/i915/display: Enable HOBL regardless the VBT value 438abf3e5bc5 drm/i915/display: Implement HOBL 425c3b58202a drm/i915/bios: Parse HOBL parameter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18024/index.html From daniel at ffwll.ch Fri Jun 26 12:39:57 2020 From: daniel at ffwll.ch (Daniel Vetter) Date: Fri, 26 Jun 2020 14:39:57 +0200 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <b7b1eb80-aa98-2d54-2344-dbc2e4bc0492@amd.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> <874kqzndxj.fsf@intel.com> <CAKMK7uErpxoFrT_K==7-PMGyg_eqF07T50eYfh5BFQLzra7TbQ@mail.gmail.com> <CAO_48GEa2ZgMph-1ZdsMcOdomZc4zNuRcNn_DoBZS3sNZa-LTg@mail.gmail.com> <b7b1eb80-aa98-2d54-2344-dbc2e4bc0492@amd.com> Message-ID: <CAKMK7uE--1E59fOhQPZ3ib4a3bSK1Nf5ikLB_GHf2wRsFTvXhw@mail.gmail.com> On Fri, Jun 26, 2020 at 9:03 AM Christian K?nig <christian.koenig at amd.com> wrote: > > Am 26.06.20 um 06:43 schrieb Sumit Semwal: > > On Fri, 26 Jun 2020 at 01:24, Daniel Vetter <daniel at ffwll.ch> wrote: > >> Ignoring everything else ... > >> > >> On Thu, Jun 25, 2020 at 9:28 PM Jani Nikula <jani.nikula at linux.intel.com> wrote: > >>> As a side note, there seem to be extra checks in place for acks when > >>> applying non-i915 patches to drm-intel; there are no such checks for > >>> drm-misc. > >> One option to generalize that that I pondered is to consult > >> get_maintainers.pl asking for git repo link, and if that returns > >> something else, then insist that there's an ack from a relevant > >> maintainer. It's a bit of typing, but I think the bigger problem is > >> that there's a ton of false positives. > > Right; for the particular patch, I wasn't even in the to: or cc: field > > and that made it slip from my radar. I would definitely ask any one > > sending patches for dma-buf directory to follow the get_maintainers.pl > > religiously. > >> But maybe that's a good thing, would give some motivation to keep > >> MAINTAINERS updated. > > Should I maybe add myself as maintainer as well? I've written enough > stuff in there to know the code quite a bit. I think that makes lots of sense, since defacto you already are :-) If you feel like bikeshed, get_maintainers.pl also supports R: for reviewer, but given that you also push patches to drm-misc M: for maintainer feels more accurate. -Daniel > > Christian. > > >> > >> The other issue is though that drm-misc is plenty used to merge > >> patches even when the respective maintainers are absent for weeks, or > >> unresponsive. If we just blindly implement that rule, then the only > >> possible Ack for these would be Dave&me as subsystem maintainers, and > >> I don't want to be in the business of stamping approvals for all this > >> stuff. Much better if people just collaborate. > >> > >> So I think an ack check would be nice, but probably not practical. > >> > >> Plus in this situation here drm-misc.git actually is the main repo, > >> and we wont ever be able to teach a script to make a judgement call of > >> whether that patch has the right amount of review on it. > >> -Daniel > > Best, > > Sumit. > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From patchwork at emeril.freedesktop.org Fri Jun 26 12:53:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 12:53:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgbW06?= =?utf-8?q?_Skip_opportunistic_reclaim_for_dma_pinned_pages?= In-Reply-To: <20200624191417.16735-1-chris@chris-wilson.co.uk> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> Message-ID: <159317603269.22984.17769383283388355129@emeril.freedesktop.org> == Series Details == Series: mm: Skip opportunistic reclaim for dma pinned pages URL : https://patchwork.freedesktop.org/series/78795/ State : success == Summary == CI Bug Log - changes from CI_DRM_8665_full -> Patchwork_18019_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18019_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at drm_read@empty-nonblock: - shard-snb: [PASS][1] -> [SKIP][2] ([fdo#109271]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-snb2/igt at drm_read@empty-nonblock.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-snb2/igt at drm_read@empty-nonblock.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][3] -> [FAIL][4] ([i915#1930]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-glk4/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl1/igt at gem_workarounds@suspend-resume-fd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl3/igt at gem_workarounds@suspend-resume-fd.html * igt at i915_module_load@reload: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb1/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-tglb3/igt at i915_module_load@reload.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk4/igt at kms_big_fb@linear-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [PASS][11] -> [DMESG-FAIL][12] ([i915#54] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html - shard-glk: [PASS][13] -> [FAIL][14] ([i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk7/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-glk8/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_cursor_crc@pipe-b-cursor-128x42-random: - shard-hsw: [PASS][15] -> [INCOMPLETE][16] ([CI#80]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-hsw6/igt at kms_cursor_crc@pipe-b-cursor-128x42-random.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-hsw6/igt at kms_cursor_crc@pipe-b-cursor-128x42-random.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +13 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl2/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-skl2/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: - shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([fdo#108145] / [i915#54] / [i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl2/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl7/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@plain-flip-ts-check at b-dp1: - shard-kbl: [PASS][23] -> [FAIL][24] ([i915#1928]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl2/igt at kms_flip@plain-flip-ts-check at b-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl3/igt at kms_flip@plain-flip-ts-check at b-dp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][25] -> [DMESG-FAIL][26] ([i915#1635] / [i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling.html - shard-kbl: [PASS][27] -> [DMESG-FAIL][28] ([i915#95]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl1/igt at kms_flip_tiling@flip-changes-tiling.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-iclb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-iclb3/igt at kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html * igt at kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu: - shard-glk: [PASS][31] -> [FAIL][32] ([i915#49]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk7/igt at kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-glk8/igt at kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu.html * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#93] / [i915#95]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl1/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145] / [i915#265]) +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl10/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_cpu.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-iclb8/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-b: - shard-tglb: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb8/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-tglb5/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html * igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm: - shard-apl: [PASS][41] -> [DMESG-WARN][42] ([i915#1635] / [i915#95]) +13 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl2/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-apl6/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][43] -> [FAIL][44] ([i915#1542]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb4/igt at perf@blocking-parameterized.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-iclb2/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-kbl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl6/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_whisper@basic-fds: - shard-glk: [DMESG-WARN][47] ([i915#118] / [i915#95]) -> [PASS][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk3/igt at gem_exec_whisper@basic-fds.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-glk7/igt at gem_exec_whisper@basic-fds.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][49] ([i915#1436] / [i915#716]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl8/igt at gen9_exec_parse@allowed-single.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-skl5/igt at gen9_exec_parse@allowed-single.html * igt at i915_pm_rpm@system-suspend-execbuf: - shard-kbl: [INCOMPLETE][51] ([i915#151] / [i915#155]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl3/igt at i915_pm_rpm@system-suspend-execbuf.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-kbl7/igt at i915_pm_rpm@system-suspend-execbuf.html * igt at kms_color@pipe-c-ctm-0-5: - shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +3 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl2/igt at kms_color@pipe-c-ctm-0-5.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-skl2/igt at kms_color@pipe-c-ctm-0-5.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: [DMESG-WARN][55] ([i915#1635] / [i915#95]) -> [PASS][56] +9 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl3/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-apl8/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][59] ([fdo#109642] / [fdo#111068]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb4/igt at kms_psr2_su@page_flip.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][61] ([fdo#109441]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb5/igt at kms_psr@psr2_sprite_mmap_gtt.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at perf@blocking-parameterized: - shard-tglb: [FAIL][63] ([i915#1542]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb1/igt at perf@blocking-parameterized.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-tglb8/igt at perf@blocking-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][65] ([i915#468]) -> [FAIL][66] ([i915#454]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-tglb8/igt at i915_pm_dc@dc6-dpms.html * igt at kms_chamelium@hdmi-hpd-fast: - shard-apl: [SKIP][67] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][68] ([fdo#109271] / [fdo#111827]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl1/igt at kms_chamelium@hdmi-hpd-fast.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-apl3/igt at kms_chamelium@hdmi-hpd-fast.html * igt at kms_cursor_crc@pipe-b-cursor-512x170-onscreen: - shard-apl: [SKIP][69] ([fdo#109271]) -> [SKIP][70] ([fdo#109271] / [i915#1635]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl2/igt at kms_cursor_crc@pipe-b-cursor-512x170-onscreen.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-apl6/igt at kms_cursor_crc@pipe-b-cursor-512x170-onscreen.html * igt at kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: [FAIL][71] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][72] ([fdo#108145] / [i915#1982]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt at kms_plane_multiple@atomic-pipe-d-tiling-y: - shard-apl: [SKIP][73] ([fdo#109271] / [i915#1635]) -> [SKIP][74] ([fdo#109271]) +4 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl1/igt at kms_plane_multiple@atomic-pipe-d-tiling-y.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/shard-apl3/igt at kms_plane_multiple@atomic-pipe-d-tiling-y.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8665 -> Patchwork_18019 CI-20190529: 20190529 CI_DRM_8665: 2cb786fa6506e20b5cb2a10decda11454111e026 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18019: 92687c80eb20bfd0f22e0ff64331fbfb1aa699fc @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18019/index.html From patchwork at emeril.freedesktop.org Fri Jun 26 13:02:25 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 13:02:25 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgU2Vu?= =?utf-8?q?d_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <20200623185756.19502-1-kunal1.joshi@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> Message-ID: <159317654584.22985.369583521463070272@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev8) URL : https://patchwork.freedesktop.org/series/62816/ State : success == Summary == CI Bug Log - changes from CI_DRM_8661_full -> Patchwork_18016_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18016_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_ctx_persistence@legacy-engines-mixed at vebox: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#2064]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at gem_ctx_persistence@legacy-engines-mixed at vebox.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl4/igt at gem_ctx_persistence@legacy-engines-mixed at vebox.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb6/igt at i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@y-tiled-64bpp-rotate-0: - shard-iclb: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-iclb1/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-iclb3/igt at kms_big_fb@y-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [PASS][9] -> [DMESG-FAIL][10] ([i915#54] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +10 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: - shard-kbl: [PASS][13] -> [DMESG-FAIL][14] ([fdo#108145] / [i915#54] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl4/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-apl: [PASS][15] -> [DMESG-FAIL][16] ([i915#1635] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at kms_flip_tiling@flip-changes-tiling.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl4/igt at kms_flip_tiling@flip-changes-tiling.html - shard-kbl: [PASS][17] -> [DMESG-FAIL][18] ([i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl7/igt at kms_flip_tiling@flip-changes-tiling.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl6/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc: - shard-tglb: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#93] / [i915#95]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl7/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl6/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl4/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl8/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_setmode@basic: - shard-kbl: [PASS][25] -> [FAIL][26] ([i915#31]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl3/igt at kms_setmode@basic.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl4/igt at kms_setmode@basic.html * igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm: - shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#95]) +12 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl3/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl1/igt at kms_vblank@pipe-b-ts-continuation-dpms-rpm.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][29] -> [FAIL][30] ([i915#1820]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html #### Possible fixes #### * igt at gem_ctx_persistence@engines-mixed-process at vcs0: - shard-skl: [FAIL][31] ([i915#1528]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl9/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl3/igt at gem_ctx_persistence@engines-mixed-process at vcs0.html * igt at gem_exec_whisper@basic-queues-all: - shard-glk: [DMESG-WARN][33] ([i915#118] / [i915#95]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk2/igt at gem_exec_whisper@basic-queues-all.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-glk7/igt at gem_exec_whisper@basic-queues-all.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][35] ([i915#402]) -> [PASS][36] +2 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb7/igt at i915_module_load@reload.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][37] ([i915#118] / [i915#95]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-glk6/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_legacy@flip-vs-cursor-legacy: - shard-apl: [FAIL][39] ([IGT#5]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl3/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2: - shard-glk: [FAIL][41] ([i915#79]) -> [PASS][42] +1 similar issue [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-glk8/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +5 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-kbl6/igt at kms_flip@flip-vs-suspend at c-dp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-kbl2/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1: - shard-skl: [FAIL][45] ([i915#1928]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_flip@plain-flip-fb-recreate-interruptible at a-edp1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [FAIL][47] ([i915#699]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl1/igt at kms_flip_tiling@flip-changes-tiling.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt: - shard-tglb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [INCOMPLETE][51] ([i915#69]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56] +2 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-iclb5/igt at kms_psr@psr2_sprite_plane_move.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-b-wait-idle-hang: - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl5/igt at kms_vblank@pipe-b-wait-idle-hang.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl6/igt at kms_vblank@pipe-b-wait-idle-hang.html * igt at kms_vblank@pipe-c-accuracy-idle: - shard-apl: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl3/igt at kms_vblank@pipe-c-accuracy-idle.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl6/igt at kms_vblank@pipe-c-accuracy-idle.html * igt at syncobj_wait@multi-wait-all-signaled: - shard-apl: [DMESG-WARN][61] ([i915#1635] / [i915#95]) -> [PASS][62] +13 similar issues [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl6/igt at syncobj_wait@multi-wait-all-signaled.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at syncobj_wait@multi-wait-all-signaled.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-apl: [TIMEOUT][63] ([i915#1635] / [i915#1958]) -> [INCOMPLETE][64] ([i915#1635] / [i915#1958]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at gem_exec_reloc@basic-concurrent16.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl3/igt at gem_exec_reloc@basic-concurrent16.html * igt at kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: [SKIP][65] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][66] ([fdo#109271] / [fdo#111827]) +2 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl1/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at kms_color_chamelium@pipe-a-ctm-limited-range.html * igt at kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [DMESG-FAIL][67] ([i915#1982]) -> [DMESG-WARN][68] ([i915#1982]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl6/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl4/igt at kms_cursor_legacy@flip-vs-cursor-legacy.html * igt at kms_fbcon_fbt@fbc-suspend: - shard-apl: [DMESG-FAIL][69] ([i915#1635] / [i915#95]) -> [FAIL][70] ([i915#1525]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl1/igt at kms_fbcon_fbt@fbc-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at kms_fbcon_fbt@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-apl: [SKIP][71] ([fdo#109271]) -> [SKIP][72] ([fdo#109271] / [i915#1635]) +5 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl8/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl4/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-skl10/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt at perf@gen12-unprivileged-single-ctx-counters: - shard-apl: [SKIP][75] ([fdo#109271] / [i915#1635]) -> [SKIP][76] ([fdo#109271]) +5 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8661/shard-apl6/igt at perf@gen12-unprivileged-single-ctx-counters.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/shard-apl8/igt at perf@gen12-unprivileged-single-ctx-counters.html [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1525]: https://gitlab.freedesktop.org/drm/intel/issues/1525 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2064]: https://gitlab.freedesktop.org/drm/intel/issues/2064 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8661 -> Patchwork_18016 CI-20190529: 20190529 CI_DRM_8661: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18016: 6f6d00bcff9fbea7969c94a52f4096a719e2733b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18016/index.html From chris at chris-wilson.co.uk Fri Jun 26 13:08:40 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 14:08:40 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <edfaedf3-f6ad-044d-8853-4ee0991a4903@amd.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> <159310696106.31486.9034080828697272264@build.alporthouse.com> <159315901171.15982.4604268132167952820@build.alporthouse.com> <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> <159316983838.18415.16087585177754322983@build.alporthouse.com> <edfaedf3-f6ad-044d-8853-4ee0991a4903@amd.com> Message-ID: <159317692089.18415.8505405149005648608@build.alporthouse.com> Quoting Christian K?nig (2020-06-26 12:35:30) > Am 26.06.20 um 13:10 schrieb Chris Wilson: > > Quoting Christian K?nig (2020-06-26 09:54:19) > > [SNIP] > >> In other words "fence -> userspace -> page fault -> fence" or "fence -> > >> userspace -> system call -> fence" can easily cause the same problem and > >> that is not avoidable. > >> > >>> An example > >>> > >>> Thread A Thread B > >>> > >>> submit(VkCmdWaitEvents) > >>> recvfrom(ThreadB) ... sendto(ThreadB) > >>> \- alloc_page > >>> \- direct reclaim > >>> \- dma_fence_wait(A) > >>> VkSetEvent() > >>> > >>> Regardless of that actual deadlock, waiting on an arbitrary fence incurs > >>> an unbounded latency which is unacceptable for direct reclaim. > >>> > >>> Online debugging can indefinitely suspend fence signaling, and the only > >>> guarantee we make of forward progress, in some cases, is process > >>> termination. > >> And exactly that is what doesn't work. You don't have any forward > >> progress any more because you ran into a software deadlock. > > Only one side is halted. Everything on that side comes to a grinding > > halt. > > > > What about checkpoint/restore, suspend/resume? Where we need to suspend > > all execution, move all the resources to one side, then put everything > > back, without cancelling the fences. Same halting problem, no? > > What are you talking about? Of course we either wait for all fences to > complete or cancel them on suspend. I do not want to have to cancel incomplete fences as we do today. I want to restore the suspended execution back to waiting on its VkEvent. > > We also do similar for resets. Suspend the hanging context, move it and > > all dependent execution off to one side; record what we can, clean up > > what we have to, then move what remains of the execution back to finish > > signaling. > > Yes, but this is not possible in this situation. In the bad case you > have a kernel deadlock and that can't be cleaned up in any way. Fences are not disturbed in this process. > > The only solution left in that situation is to reset the system or at > least reload the kernel and that is not acceptable. > > >> In other words the signaling of a fence depends on the welfare of > >> userspace. You can try to kill userspace, but this can wait for the > >> fence you try to signal in the first place. > > The only scenario that fits what you are describing here [userspace > > ignoring a signal] is if you used an uninterruptible wait. Under what > > circumstances during normal execution would you do that? If it's > > someone else's wait, a bug outside of our control. > > Uninterruptible waits are a necessity. > > Just take a look at the dma_fence_wait() interface. Why to you think we > have ability to wait uninterruptible there? > > We need this when there is no other way of recovering. For example when > operations are already partially flushed to the hardware and can't be > aborted any more. So why wait in the middle of submission, rather than defer the submission to the fence callback if the HW wasn't ready? You then have your uninterruptible continuation. > > But if you have chosen to cancel the fences, there is nothing to stop > > the signaling. > > And just to repeat myself: You can't cancel the fence! > > For example assume that canceling the proxy fence would mean that you > send a SIGKILL to the process which issued it. But then you need to wait > for the SIGKILL to be processed. What? Where does SIGKILL come from for fence handling? The proxy fence is force signaled in an error state (e.g. -ETIMEDOUT), every waiter then inherits the error state and all of their waiters down the chain. Those waiters are now presumably ready to finish their own signaling. The proxy fence is constructed to always complete if it does not get resolved; after resolution, the onus is on the real fence to complete. The same as handling any other error or context cancellation during fence submission. > Now what can happen is that the process is uninterruptible waiting for > something which then needs the SIGKILL to be delivered -> kernel deadlock. > > >> See the difference to a deadlock on the GPU is that you can can always > >> kill a running job or process even if it is stuck with something else. > >> But if the kernel is deadlocked with itself you can't kill the process > >> any more, the only option left to get cleanly out of this is to reboot > >> the kernel. > > However, I say that is under our control. We know what fences are in an > > execution context, just as easily as we know that we are inside an > > execution context. And yes, the easiest, the most restrictive way to > > control it is to say don't bother. > > No, that is absolutely not under our control. > > dma_fences need to be waited on under a lot of different context, > including the reclaim path as well as the MMU notifiers, memory pressure > callbacks, OOM killer.... Oh yes, they are under our control. That list boils down to reclaim, since mmu notifiers outside of reclaim are outside of a nested context. That in particular is the same old question as whether GFP_IO should be a gfp_t or in the task_struct. If we are inside an execution context, we can track that and the fences on the task_struct if we wanted to, avoiding reclaim of fences being used by the outer context and their descendants... But as we have stated multiple times now, and that I thought you had agreed with for the VkEvents example, one cannot wait inside direct reclaim. Least of all because the latency in doing so impacts other users, sometimes severely. Which pushes the burden of work onto kswapd to make objects reclaimable, and the driver in general to not hold onto objects beyond their use. > Just see Daniels patches on the lockdep fence signaling annotation and > what this work bubbled up on problems. > > >> The only way to avoid this would be to never ever wait for the fence in > >> the kernel and then your whole construct is not useful any more. > > I advocate for moving as much as is feasible, for some waits are required > > by userspace as a necessary evil, into the parallelised pipeline. > > > >> I'm running out of ideas how to explain what the problem is here.... > > Oh we agree on the problem, we appear to disagree that the implicit waits > > themselves are a serious existent problem. That they are worth effort to > > avoid or, at least, mitigate. > > No, as far as I can see you don't seem to either understand the problem > or the implications of it. > > The only way to solve this would be to audit the whole Linux kernel and > remove all uninterruptible waits and that is not feasible. > > As long as you don't provide me with a working solution to the problem > I've outlined here the whole approach is a clear NAK since it will allow > to create really bad kernel deadlocks. You are confusing multiple things here. The VkEvents example is real. How do you avoid that deadlock? We avoid it by not waiting in direct reclaim. It has also shown up any waits in our submit ioctl [prior to fence publication, I might add] for their potential deadlock with userspace. -Chris From thomas_os at shipmail.org Fri Jun 26 13:32:29 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Fri, 26 Jun 2020 15:32:29 +0200 Subject: [Intel-gfx] [PATCH 05/26] drm/i915: Remove locking from i915_gem_object_prepare_read/write In-Reply-To: <20200623142843.423594-5-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-5-maarten.lankhorst@linux.intel.com> Message-ID: <a1f2527f-e3f3-b918-8b5c-06ff9c1308bb@shipmail.org> On 6/23/20 4:28 PM, Maarten Lankhorst wrote: > Execbuffer submission will perform its own WW locking, and we > cannot rely on the implicit lock there. > > This also makes it clear that the GVT code will get a lockdep splat when > multiple batchbuffer shadows need to be performed in the same instance, > fix that up. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 20 ++++++------------- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 13 ++++++++++-- > drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 - > .../gpu/drm/i915/gem/selftests/huge_pages.c | 5 ++++- > .../i915/gem/selftests/i915_gem_coherency.c | 14 +++++++++---- > .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++++++++--- > drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + > drivers/gpu/drm/i915/i915_gem.c | 20 +++++++++++++++++-- > 8 files changed, 59 insertions(+), 27 deletions(-) > ltgm. Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> From ville.syrjala at linux.intel.com Fri Jun 26 13:46:41 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 26 Jun 2020 16:46:41 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200626091606.GA29269@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> Message-ID: <20200626134641.GZ6112@intel.com> On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > The linetime watermark is a 9 bit value, which gives us > > a maximum linetime of just below 64 usec. If the linetime > > exceeds that value we currently just discard the high bits > > and program the rest into the register, which angers the > > state checker. > > > > To avoid that let's just clamp the value to the max. I believe > > it should be perfectly fine to program a smaller linetime wm > > than strictly required, just means the hardware may fetch data > > sooner than strictly needed. We are further reassured by the > > fact that with DRRS the spec tells us to program the smaller > > of the two linetimes corresponding to the two refresh rates. > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index a11bb675f9b3..d486d675166f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) > > { > > const struct drm_display_mode *adjusted_mode = > > &crtc_state->hw.adjusted_mode; > > + int linetime_wm; > > > > if (!crtc_state->hw.enable) > > return 0; > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > - adjusted_mode->crtc_clock); > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > + adjusted_mode->crtc_clock); > > + > > + return min(linetime_wm, 0x1ff); > > Are we actually doing the right thing here? I just mean that we get value > 543 in the bug because pixel rate is 14874 which doesn't seem correct. As explained in the commit msg programming this to lower than necessary value should be totally fine. It just won't be optimal. The values in the jira (was there an actual gitlab bug for this btw?) look quite sensible to me. Some kind of low res 848xsomething mode with dotclock of 14.874 Mhz, which gives us that linetime of ~68 usec. > > Stan > > } > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > { > > const struct drm_display_mode *adjusted_mode = > > &crtc_state->hw.adjusted_mode; > > + int linetime_wm; > > > > if (!crtc_state->hw.enable) > > return 0; > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > - cdclk_state->logical.cdclk); > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > + cdclk_state->logical.cdclk); > > + > > + return min(linetime_wm, 0x1ff); > > } > > > > static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > const struct drm_display_mode *adjusted_mode = > > &crtc_state->hw.adjusted_mode; > > - u16 linetime_wm; > > + int linetime_wm; > > > > if (!crtc_state->hw.enable) > > return 0; > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > linetime_wm /= 2; > > > > - return linetime_wm; > > + return min(linetime_wm, 0x1ff); > > } > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state *state, > > -- > > 2.26.2 > > -- Ville Syrj?l? Intel From thomas_os at shipmail.org Fri Jun 26 13:52:09 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Fri, 26 Jun 2020 15:52:09 +0200 Subject: [Intel-gfx] [PATCH 08/26] drm/i915/gem: Make eb_add_lut interruptible wait on object lock. In-Reply-To: <20200623142843.423594-8-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-8-maarten.lankhorst@linux.intel.com> Message-ID: <ff4734b0-b529-5598-d1ef-82813f439d49@shipmail.org> On 6/23/20 4:28 PM, Maarten Lankhorst wrote: > The lock here should be interruptible, so we can backoff if needed. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 2636a130fb57..aa441af81431 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -774,7 +774,12 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > if (err == 0) { /* And nor has this handle */ > struct drm_i915_gem_object *obj = vma->obj; > > - i915_gem_object_lock(obj, NULL); > + err = i915_gem_object_lock_interruptible(obj, NULL); > + if (err) { > + radix_tree_delete(&ctx->handles_vma, handle); > + goto unlock; > + } > + > if (idr_find(&eb->file->object_idr, handle) == obj) { > list_add(&lut->obj_link, &obj->lut_list); > } else { > @@ -783,6 +788,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > } > i915_gem_object_unlock(obj); > } > +unlock: > mutex_unlock(&ctx->mutex); > } > if (unlikely(err)) Reviewed-by: Thomas Hellstr?m <thomas.hellstrom at intel.com> From jani.saarinen at intel.com Fri Jun 26 14:03:23 2020 From: jani.saarinen at intel.com (Saarinen, Jani) Date: Fri, 26 Jun 2020 14:03:23 +0000 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200626134641.GZ6112@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> Message-ID: <967d55ae9ac24745ae4fde4ca846a475@intel.com> Hi, > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Ville Syrj?l? > Sent: perjantai 26. kes?kuuta 2020 16.47 > To: Lisovskiy, Stanislav <stanislav.lisovskiy at intel.com> > Cc: intel-gfx at lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec > > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > The linetime watermark is a 9 bit value, which gives us a maximum > > > linetime of just below 64 usec. If the linetime exceeds that value > > > we currently just discard the high bits and program the rest into > > > the register, which angers the state checker. > > > > > > To avoid that let's just clamp the value to the max. I believe it > > > should be perfectly fine to program a smaller linetime wm than > > > strictly required, just means the hardware may fetch data sooner > > > than strictly needed. We are further reassured by the fact that with > > > DRRS the spec tells us to program the smaller of the two linetimes > > > corresponding to the two refresh rates. > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 18 > > > ++++++++++++------ > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > index a11bb675f9b3..d486d675166f 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct > > > intel_crtc_state *crtc_state) { > > > const struct drm_display_mode *adjusted_mode = > > > &crtc_state->hw.adjusted_mode; > > > + int linetime_wm; > > > > > > if (!crtc_state->hw.enable) > > > return 0; > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * > 8, > > > - adjusted_mode- > >crtc_clock); > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * > 1000 * 8, > > > + > adjusted_mode->crtc_clock); > > > + > > > + return min(linetime_wm, 0x1ff); > > > > Are we actually doing the right thing here? I just mean that we get > > value > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > As explained in the commit msg programming this to lower than necessary value > should be totally fine. It just won't be optimal. > > The values in the jira (was there an actual gitlab bug for this btw?) look quite sensible No, there is no gtilab issue as no tiled display at CI. > to me. Some kind of low res 848xsomething mode with dotclock of 14.874 Mhz, > which gives us that linetime of ~68 usec. > > > > > Stan > > > } > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state > > > *crtc_state, @@ -12594,12 +12597,15 @@ static u16 > > > hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, { > > > const struct drm_display_mode *adjusted_mode = > > > &crtc_state->hw.adjusted_mode; > > > + int linetime_wm; > > > > > > if (!crtc_state->hw.enable) > > > return 0; > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * > 8, > > > - cdclk_state- > >logical.cdclk); > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * > 1000 * 8, > > > + > cdclk_state->logical.cdclk); > > > + > > > + return min(linetime_wm, 0x1ff); > > > } > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state > > > *crtc_state) @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const > struct intel_crtc_state *crtc_state) > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > const struct drm_display_mode *adjusted_mode = > > > &crtc_state->hw.adjusted_mode; > > > - u16 linetime_wm; > > > + int linetime_wm; > > > > > > if (!crtc_state->hw.enable) > > > return 0; > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct > intel_crtc_state *crtc_state) > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > linetime_wm /= 2; > > > > > > - return linetime_wm; > > > + return min(linetime_wm, 0x1ff); > > > } > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state > > > *state, > > > -- > > > 2.26.2 > > > > > -- > Ville Syrj?l? > Intel > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From ville.syrjala at linux.intel.com Fri Jun 26 14:09:18 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Fri, 26 Jun 2020 17:09:18 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <967d55ae9ac24745ae4fde4ca846a475@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> <967d55ae9ac24745ae4fde4ca846a475@intel.com> Message-ID: <20200626140918.GB6112@intel.com> On Fri, Jun 26, 2020 at 02:03:23PM +0000, Saarinen, Jani wrote: > Hi, > > > -----Original Message----- > > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Ville Syrj?l? > > Sent: perjantai 26. kes?kuuta 2020 16.47 > > To: Lisovskiy, Stanislav <stanislav.lisovskiy at intel.com> > > Cc: intel-gfx at lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec > > > > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > The linetime watermark is a 9 bit value, which gives us a maximum > > > > linetime of just below 64 usec. If the linetime exceeds that value > > > > we currently just discard the high bits and program the rest into > > > > the register, which angers the state checker. > > > > > > > > To avoid that let's just clamp the value to the max. I believe it > > > > should be perfectly fine to program a smaller linetime wm than > > > > strictly required, just means the hardware may fetch data sooner > > > > than strictly needed. We are further reassured by the fact that with > > > > DRRS the spec tells us to program the smaller of the two linetimes > > > > corresponding to the two refresh rates. > > > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_display.c | 18 > > > > ++++++++++++------ > > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > index a11bb675f9b3..d486d675166f 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct > > > > intel_crtc_state *crtc_state) { > > > > const struct drm_display_mode *adjusted_mode = > > > > &crtc_state->hw.adjusted_mode; > > > > + int linetime_wm; > > > > > > > > if (!crtc_state->hw.enable) > > > > return 0; > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * > > 8, > > > > - adjusted_mode- > > >crtc_clock); > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * > > 1000 * 8, > > > > + > > adjusted_mode->crtc_clock); > > > > + > > > > + return min(linetime_wm, 0x1ff); > > > > > > Are we actually doing the right thing here? I just mean that we get > > > value > > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > > > As explained in the commit msg programming this to lower than necessary value > > should be totally fine. It just won't be optimal. > > > > The values in the jira (was there an actual gitlab bug for this btw?) look quite sensible > No, there is no gtilab issue as no tiled display at CI. Can't see what this has to do with tiled displays. I guess we're talking about some specific display that just happens to have that super slow mode? > > > to me. Some kind of low res 848xsomething mode with dotclock of 14.874 Mhz, > > which gives us that linetime of ~68 usec. > > > > > > > > Stan > > > > } > > > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state > > > > *crtc_state, @@ -12594,12 +12597,15 @@ static u16 > > > > hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, { > > > > const struct drm_display_mode *adjusted_mode = > > > > &crtc_state->hw.adjusted_mode; > > > > + int linetime_wm; > > > > > > > > if (!crtc_state->hw.enable) > > > > return 0; > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * > > 8, > > > > - cdclk_state- > > >logical.cdclk); > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * > > 1000 * 8, > > > > + > > cdclk_state->logical.cdclk); > > > > + > > > > + return min(linetime_wm, 0x1ff); > > > > } > > > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state > > > > *crtc_state) @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const > > struct intel_crtc_state *crtc_state) > > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > const struct drm_display_mode *adjusted_mode = > > > > &crtc_state->hw.adjusted_mode; > > > > - u16 linetime_wm; > > > > + int linetime_wm; > > > > > > > > if (!crtc_state->hw.enable) > > > > return 0; > > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct > > intel_crtc_state *crtc_state) > > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > > linetime_wm /= 2; > > > > > > > > - return linetime_wm; > > > > + return min(linetime_wm, 0x1ff); > > > > } > > > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state > > > > *state, > > > > -- > > > > 2.26.2 > > > > > > > > -- > > Ville Syrj?l? > > Intel > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From gwan-gyeong.mun at intel.com Fri Jun 26 14:11:33 2020 From: gwan-gyeong.mun at intel.com (Mun, Gwan-gyeong) Date: Fri, 26 Jun 2020 14:11:33 +0000 Subject: [Intel-gfx] [PATCH v2 3/5] drm/i915: Add PSR2 selective fetch registers In-Reply-To: <20200626010151.221388-3-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> <20200626010151.221388-3-jose.souza@intel.com> Message-ID: <ec989aa029c98e7735c3a457be68137f90dc851f.camel@intel.com> On Thu, 2020-06-25 at 18:01 -0700, Jos? Roberto de Souza wrote: > This registers will be used to implement PSR2 manual > tracking/selective > fetch. > > v2: > - Fixed typo in _PLANE_SEL_FETCH_BASE > - Renamed PSR2_MAN_TRK_CTL bits to better match spec names > - Renamed _PLANE_SEL_FETCH_* to better match spec names > > BSpec: 55229 > BSpec: 50424 > BSpec: 50420 > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++- > -- > 1 file changed, 63 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index f09120cac89a..8b6eb42b63db 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4585,6 +4585,18 @@ enum { > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > PSR2_SU_STATUS_SHIFT(frame)) > #define PSR2_SU_STATUS_FRAMES 8 > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, > 21) > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP( > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) > +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GEN > MASK(20, 11) > +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIE > LD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) > +#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT > (3) > +#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) > +#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) > + > /* VGA port control */ > #define ADPA _MMIO(0x61100) > #define PCH_ADPA _MMIO(0xe1100) > @@ -7148,7 +7160,52 @@ enum { > #define PLANE_COLOR_CTL(pipe, plane) \ > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > _PLANE_COLOR_CTL_2(pipe)) > > -#/* SKL new cursor registers */ > +#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 > +#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 > +#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 > +#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 > +#define _SEL_FETCH_PLANE_BASE_5_A 0x70920 > +#define _SEL_FETCH_PLANE_BASE_6_A 0x70940 > +#define _SEL_FETCH_PLANE_BASE_7_A 0x70960 > +#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 > +#define _SEL_FETCH_PLANE_BASE_1_B 0x70990 > + > +#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ > + _SEL_FETCH_PLANE_BASE_1_A, > \ > + _SEL_FETCH_PLANE_BASE_2_A, > \ > + _SEL_FETCH_PLANE_BASE_3_A, > \ > + _SEL_FETCH_PLANE_BASE_4_A, > \ > + _SEL_FETCH_PLANE_BASE_5_A, > \ > + _SEL_FETCH_PLANE_BASE_6_A, > \ > + _SEL_FETCH_PLANE_BASE_7_A, > \ > + _SEL_FETCH_PLANE_BASE_CUR_ > A) > +#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, > _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) > +#define _SEL_FETCH_PLANE_BASE(pipe, plane) > (_SEL_FETCH_PLANE_BASE_1(pipe) - \ > + _SEL_FETCH_PLANE_BASE_1_A + > \ > + _SEL_FETCH_PLANE_BASE_A(pla > ne)) > + > +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > + _SEL_FETCH_PLANE_CTL_1_A > - \ > + _SEL_FETCH_PLANE_BASE_1_ > A) > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) it seems a typo of "PLANE_SEL_FETCH_CTL_ENABLE", except for this line, looks good to me. Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > + > +#define _SEL_FETCH_PLANE_POS_1_A 0x70894 > +#define PLANE_SEL_FETCH_POS(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > + _SEL_FETCH_PLANE_POS_1_A > - \ > + _SEL_FETCH_PLANE_BASE_1_ > A) > + > +#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > + _SEL_FETCH_PLANE_SIZE_1 > _A - \ > + _SEL_FETCH_PLANE_BASE_1 > _A) > + > +#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > + _SEL_FETCH_PLANE_OFFS > ET_1_A - \ > + _SEL_FETCH_PLANE_BASE > _1_A) > + > +/* SKL new cursor registers */ > #define _CUR_BUF_CFG_A 0x7017c > #define _CUR_BUF_CFG_B 0x7117c > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, > _CUR_BUF_CFG_B) > @@ -7794,11 +7851,12 @@ enum { > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > -#define DPA_MASK_VBLANK_SRD (1 << 15) > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > +#define DPA_MASK_VBLANK_SRD (1 << 15) > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) From patchwork at emeril.freedesktop.org Fri Jun 26 14:15:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 14:15:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_Revert_=22dma-buf=3A_Report_signale?= =?utf-8?q?d_links_inside_dma-fence-chain=22?= In-Reply-To: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> Message-ID: <159318090009.22986.10307641103028717489@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" URL : https://patchwork.freedesktop.org/series/78819/ State : success == Summary == CI Bug Log - changes from CI_DRM_8667 -> Patchwork_18025 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/index.html Known issues ------------ Here are the changes found in Patchwork_18025 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at core_auth@basic-auth: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-byt-n2820/igt at core_auth@basic-auth.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-byt-n2820/igt at core_auth@basic-auth.html * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] ([i915#1242]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_hangman@error-state-basic: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-y/igt at i915_hangman@error-state-basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-tgl-y/igt at i915_hangman@error-state-basic.html * igt at i915_module_load@reload: - fi-icl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-icl-y/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-icl-y/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html #### Possible fixes #### * igt at prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-y/igt at prime_self_import@basic-with_two_bos.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-tgl-y/igt at prime_self_import@basic-with_two_bos.html #### Warnings #### * igt at kms_flip@basic-flip-vs-dpms at a-dp1: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-dpms at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#1982] / [i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 39) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8667 -> Patchwork_18025 CI-20190529: 20190529 CI_DRM_8667: 57a1fc457c260002189382a406e920465d540d53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18025: 9d22b3c5b08feeea9b043fbb36c1868b78ffa7ab @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9d22b3c5b08f dma-buf: fix dma-fence-chain out of order test 3a63b08bb2b4 Revert "dma-buf: Report signaled links inside dma-fence-chain" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18025/index.html From jani.saarinen at intel.com Fri Jun 26 14:15:48 2020 From: jani.saarinen at intel.com (Saarinen, Jani) Date: Fri, 26 Jun 2020 14:15:48 +0000 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200626140918.GB6112@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> <967d55ae9ac24745ae4fde4ca846a475@intel.com> <20200626140918.GB6112@intel.com> Message-ID: <5169160f469d48d3b0a84aa2ef7fcb21@intel.com> Hi, > -----Original Message----- > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Sent: perjantai 26. kes?kuuta 2020 17.09 > To: Saarinen, Jani <jani.saarinen at intel.com> > Cc: Lisovskiy, Stanislav <stanislav.lisovskiy at intel.com>; intel- > gfx at lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec > > On Fri, Jun 26, 2020 at 02:03:23PM +0000, Saarinen, Jani wrote: > > Hi, > > > > > -----Original Message----- > > > From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf > > > Of Ville Syrj?l? > > > Sent: perjantai 26. kes?kuuta 2020 16.47 > > > To: Lisovskiy, Stanislav <stanislav.lisovskiy at intel.com> > > > Cc: intel-gfx at lists.freedesktop.org > > > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to > > > <64usec > > > > > > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > > > The linetime watermark is a 9 bit value, which gives us a > > > > > maximum linetime of just below 64 usec. If the linetime exceeds > > > > > that value we currently just discard the high bits and program > > > > > the rest into the register, which angers the state checker. > > > > > > > > > > To avoid that let's just clamp the value to the max. I believe > > > > > it should be perfectly fine to program a smaller linetime wm > > > > > than strictly required, just means the hardware may fetch data > > > > > sooner than strictly needed. We are further reassured by the > > > > > fact that with DRRS the spec tells us to program the smaller of > > > > > the two linetimes corresponding to the two refresh rates. > > > > > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_display.c | 18 > > > > > ++++++++++++------ > > > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > > > > b/drivers/gpu/drm/i915/display/intel_display.c > > > > > index a11bb675f9b3..d486d675166f 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const > > > > > struct intel_crtc_state *crtc_state) { > > > > > const struct drm_display_mode *adjusted_mode = > > > > > &crtc_state->hw.adjusted_mode; > > > > > + int linetime_wm; > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > return 0; > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * > > > 8, > > > > > - adjusted_mode- > > > >crtc_clock); > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * > > > 1000 * 8, > > > > > + > > > adjusted_mode->crtc_clock); > > > > > + > > > > > + return min(linetime_wm, 0x1ff); > > > > > > > > Are we actually doing the right thing here? I just mean that we > > > > get value > > > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > > > > > As explained in the commit msg programming this to lower than > > > necessary value should be totally fine. It just won't be optimal. > > > > > > The values in the jira (was there an actual gitlab bug for this > > > btw?) look quite sensible > > No, there is no gtilab issue as no tiled display at CI. > > Can't see what this has to do with tiled displays. I guess we're talking about some > specific display that just happens to have that super slow mode? Perhaps, issue where seen in Dell UP2715K. > > > > > > to me. Some kind of low res 848xsomething mode with dotclock of > > > 14.874 Mhz, which gives us that linetime of ~68 usec. > > > > > > > > > > > Stan > > > > > } > > > > > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state > > > > > *crtc_state, @@ -12594,12 +12597,15 @@ static u16 > > > > > hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, { > > > > > const struct drm_display_mode *adjusted_mode = > > > > > &crtc_state->hw.adjusted_mode; > > > > > + int linetime_wm; > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > return 0; > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * > > > 8, > > > > > - cdclk_state- > > > >logical.cdclk); > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * > > > 1000 * 8, > > > > > + > > > cdclk_state->logical.cdclk); > > > > > + > > > > > + return min(linetime_wm, 0x1ff); > > > > > } > > > > > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state > > > > > *crtc_state) @@ -12608,7 +12614,7 @@ static u16 > > > > > skl_linetime_wm(const > > > struct intel_crtc_state *crtc_state) > > > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > > const struct drm_display_mode *adjusted_mode = > > > > > &crtc_state->hw.adjusted_mode; > > > > > - u16 linetime_wm; > > > > > + int linetime_wm; > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > return 0; > > > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct > > > intel_crtc_state *crtc_state) > > > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > > > linetime_wm /= 2; > > > > > > > > > > - return linetime_wm; > > > > > + return min(linetime_wm, 0x1ff); > > > > > } > > > > > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state > > > > > *state, > > > > > -- > > > > > 2.26.2 > > > > > > > > > > > -- > > > Ville Syrj?l? > > > Intel > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx at lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj?l? > Intel From tvrtko.ursulin at linux.intel.com Fri Jun 26 14:18:02 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 26 Jun 2020 15:18:02 +0100 Subject: [Intel-gfx] [PATCH 1/7] drm/i915: Convert device_info to uncore/de_read In-Reply-To: <20200625234212.22811-2-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-2-daniele.ceraolospurio@intel.com> Message-ID: <7b75ffa4-8d96-d774-5d6d-7d3e3d9ff24b@linux.intel.com> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: > Use intel_<uncore/de>_read instead of I915_READ to read the > informational registers. > > Extended from an original sseu-only patch by Sandeep. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> > --- > drivers/gpu/drm/i915/intel_device_info.c | 77 +++++++++++++++--------- > 1 file changed, 47 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 544ac61fbc36..c27a56aff5de 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -26,6 +26,7 @@ > #include <drm/i915_pciids.h> > > #include "display/intel_cdclk.h" > +#include "display/intel_de.h" > #include "intel_device_info.h" > #include "i915_drv.h" > > @@ -237,6 +238,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, > static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) > { > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > + struct intel_uncore *uncore = &dev_priv->uncore; > u8 s_en; > u32 dss_en; > u16 eu_en = 0; > @@ -250,12 +252,14 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) > */ > intel_sseu_set_info(sseu, 1, 6, 16); > > - s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; > + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > + GEN11_GT_S_ENA_MASK; > > - dss_en = I915_READ(GEN12_GT_DSS_ENABLE); > + dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); > > /* one bit per pair of EUs */ > - eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); > + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > + GEN11_EU_DIS_MASK); > for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) > if (eu_en_fuse & BIT(eu)) > eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); > @@ -269,6 +273,7 @@ static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) > static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > { > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > + struct intel_uncore *uncore = &dev_priv->uncore; > u8 s_en; > u32 ss_en; > u8 eu_en; > @@ -278,9 +283,12 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > else > intel_sseu_set_info(sseu, 1, 8, 8); > > - s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK; > - ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE); > - eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK); > + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > + GEN11_GT_S_ENA_MASK; > + ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); > + > + eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > + GEN11_EU_DIS_MASK); > > gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); > > @@ -292,8 +300,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > > static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - const u32 fuse2 = I915_READ(GEN8_FUSE2); > + const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > int s, ss; > const int eu_mask = 0xff; > u32 subslice_mask, eu_en; > @@ -304,26 +313,26 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) > GEN10_F2_S_ENA_SHIFT; > > /* Slice0 */ > - eu_en = ~I915_READ(GEN8_EU_DISABLE0); > + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); > for (ss = 0; ss < sseu->max_subslices; ss++) > sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); > /* Slice1 */ > sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); > - eu_en = ~I915_READ(GEN8_EU_DISABLE1); > + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); > sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); > /* Slice2 */ > sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); > sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); > /* Slice3 */ > sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); > - eu_en = ~I915_READ(GEN8_EU_DISABLE2); > + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); > sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); > /* Slice4 */ > sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); > sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); > /* Slice5 */ > sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); > - eu_en = ~I915_READ(GEN10_EU_DISABLE3); > + eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); > sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); > > subslice_mask = (1 << 4) - 1; > @@ -372,7 +381,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > u32 fuse; > u8 subslice_mask = 0; > > - fuse = I915_READ(CHV_FUSE_GT); > + fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT); > > sseu->slice_mask = BIT(0); > intel_sseu_set_info(sseu, 1, 2, 8); > @@ -425,11 +434,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > { > struct intel_device_info *info = mkwrite_device_info(dev_priv); > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > + struct intel_uncore *uncore = &dev_priv->uncore; > int s, ss; > u32 fuse2, eu_disable, subslice_mask; > const u8 eu_mask = 0xff; > > - fuse2 = I915_READ(GEN8_FUSE2); > + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; > > /* BXT has a single slice and at most 3 subslices. */ > @@ -455,7 +465,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > > intel_sseu_set_subslices(sseu, s, subslice_mask); > > - eu_disable = I915_READ(GEN9_EU_DISABLE(s)); > + eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); > for (ss = 0; ss < sseu->max_subslices; ss++) { > int eu_per_ss; > u8 eu_disabled_mask; > @@ -528,10 +538,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) > { > struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > + struct intel_uncore *uncore = &dev_priv->uncore; > int s, ss; > u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ > + u32 eu_disable0, eu_disable1, eu_disable2; > > - fuse2 = I915_READ(GEN8_FUSE2); > + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; > intel_sseu_set_info(sseu, 3, 3, 8); > > @@ -542,13 +554,15 @@ static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) > subslice_mask = GENMASK(sseu->max_subslices - 1, 0); > subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> > GEN8_F2_SS_DIS_SHIFT); > - > - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; > - eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | > - ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << > + eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); > + eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); > + eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); > + eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; > + eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | > + ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << > (32 - GEN8_EU_DIS0_S1_SHIFT)); > - eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | > - ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << > + eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | > + ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << > (32 - GEN8_EU_DIS1_S2_SHIFT)); > > /* > @@ -635,7 +649,7 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) > break; > } > > - fuse1 = I915_READ(HSW_PAVP_FUSE1); > + fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1); > switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { > default: > MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> > @@ -675,7 +689,8 @@ static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) > > static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) > { > - u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); > + u32 ts_override = intel_uncore_read(&dev_priv->uncore, > + GEN9_TIMESTAMP_OVERRIDE); > u32 base_freq, frac_freq; > > base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> > @@ -738,6 +753,7 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv, > > static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) > { > + struct intel_uncore *uncore = &dev_priv->uncore; > u32 f12_5_mhz = 12500000; > u32 f19_2_mhz = 19200000; > u32 f24_mhz = 24000000; > @@ -759,7 +775,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) > */ > return f12_5_mhz; > } else if (INTEL_GEN(dev_priv) <= 9) { > - u32 ctc_reg = I915_READ(CTC_MODE); > + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); > u32 freq = 0; > > if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { > @@ -777,7 +793,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) > > return freq; > } else if (INTEL_GEN(dev_priv) <= 12) { > - u32 ctc_reg = I915_READ(CTC_MODE); > + u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); > u32 freq = 0; > > /* First figure out the reference frequency. There are 2 ways > @@ -788,7 +804,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) > if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { > freq = read_reference_ts_freq(dev_priv); > } else { > - u32 rpm_config_reg = I915_READ(RPM_CONFIG0); > + u32 rpm_config_reg = intel_uncore_read(uncore, RPM_CONFIG0); > > if (INTEL_GEN(dev_priv) <= 10) > freq = gen10_get_crystal_clock_freq(dev_priv, > @@ -967,8 +983,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > > if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) && > HAS_PCH_SPLIT(dev_priv)) { > - u32 fuse_strap = I915_READ(FUSE_STRAP); > - u32 sfuse_strap = I915_READ(SFUSE_STRAP); > + u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); > + u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); > > /* > * SFUSE_STRAP is supposed to have a bit signalling the display > @@ -993,7 +1009,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); > } > } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) { > - u32 dfsm = I915_READ(SKL_DFSM); > + u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); > > if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { > info->pipe_mask &= ~BIT(PIPE_A); > @@ -1083,6 +1099,7 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps, > void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > { > struct intel_device_info *info = mkwrite_device_info(dev_priv); > + struct intel_uncore *uncore = &dev_priv->uncore; > unsigned int logical_vdbox = 0; > unsigned int i; > u32 media_fuse; > @@ -1092,7 +1109,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > if (INTEL_GEN(dev_priv) < 11) > return; > > - media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); > + media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); > > vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; > vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From patchwork at emeril.freedesktop.org Fri Jun 26 14:19:22 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 14:19:22 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_iommu=3A_Remove_usage_of_dev-=3Earchdata=2Eiommu?= In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <159318116255.22986.13839496290193471327@emeril.freedesktop.org> == Series Details == Series: iommu: Remove usage of dev->archdata.iommu URL : https://patchwork.freedesktop.org/series/78822/ State : warning == Summary == $ dim checkpatch origin/drm-tip ea59789bb2c8 iommu/exynos: Use dev_iommu_priv_get/set() -:20: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "dev_iommu_priv_get" #20: FILE: drivers/iommu/exynos-iommu.c:176: +#define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) -:121: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "dev_iommu_priv_get" #121: FILE: drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h:16: + return dev_iommu_priv_get(dev) != NULL; total: 0 errors, 0 warnings, 2 checks, 95 lines checked 751d62a601db iommu/vt-d: Use dev_iommu_priv_get/set() 000b842cda59 iommu/msm: Use dev_iommu_priv_get/set() 79dfab955ac4 iommu/omap: Use dev_iommu_priv_get/set() 3168eb5065df iommu/rockchip: Use dev_iommu_priv_get/set() df87e91a4c59 iommu/tegra: Use dev_iommu_priv_get/set() d14eb31e19bb iommu/pamu: Use dev_iommu_priv_get/set() be1951b09735 iommu/mediatek: Do no use dev->archdata.iommu b86f57d96a87 x86: Remove dev->archdata.iommu pointer beb0e5de86ca ia64: Remove dev->archdata.iommu pointer e36fe82cd6d3 arm: Remove dev->archdata.iommu pointer c154e15c0d13 arm64: Remove dev->archdata.iommu pointer 1cd7039a6769 powerpc/dma: Remove dev->archdata.iommu_domain From tvrtko.ursulin at linux.intel.com Fri Jun 26 14:20:23 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 26 Jun 2020 15:20:23 +0100 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE In-Reply-To: <20200625234212.22811-3-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-3-daniele.ceraolospurio@intel.com> Message-ID: <93448b2b-0384-c839-d545-11fd1a2f6ec8@linux.intel.com> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: > A follow up patch will move the engine mask under the gt structure, > so get ready for that. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 ++++--- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > drivers/gpu/drm/i915/gvt/interrupt.c | 2 +- > drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++------- > drivers/gpu/drm/i915/intel_device_info.c | 13 +++++++------ > drivers/gpu/drm/i915/intel_pm.c | 2 +- > drivers/gpu/drm/i915/intel_uncore.c | 16 +++++++++------- > drivers/gpu/drm/i915/intel_uncore.h | 4 +++- > 12 files changed, 38 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 7bf2f76212f0..be92d1ef9aa9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -473,7 +473,7 @@ int intel_engines_init_mmio(struct intel_gt *gt) > return -ENODEV; > > for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { > - if (!HAS_ENGINE(i915, i)) > + if (!HAS_ENGINE(gt, i)) > continue; > > err = intel_engine_setup(gt, i); > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > index 0cc7dd54f4f9..e1964cf40fd6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > @@ -457,7 +457,7 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt) > * RPS interrupts will get enabled/disabled on demand when RPS > * itself is enabled/disabled. > */ > - if (HAS_ENGINE(gt->i915, VECS0)) { > + if (HAS_ENGINE(gt, VECS0)) { > pm_irqs |= PM_VEBOX_USER_INTERRUPT; > gt->pm_ier |= PM_VEBOX_USER_INTERRUPT; > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 101728006ae9..fbdd6b0677db 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -67,7 +67,8 @@ struct __guc_ads_blob { > > static void __guc_ads_init(struct intel_guc *guc) > { > - struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; > + struct intel_gt *gt = guc_to_gt(guc); > + struct drm_i915_private *dev_priv = gt->i915; > struct __guc_ads_blob *blob = guc->ads_blob; > const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; > u32 base; > @@ -103,8 +104,8 @@ static void __guc_ads_init(struct intel_guc *guc) > blob->system_info.rcs_enabled = 1; > blob->system_info.bcs_enabled = 1; > > - blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv); > - blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv); > + blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt); > + blob->system_info.vebox_enable_mask = VEBOX_MASK(gt); > blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; > > base = intel_guc_ggtt_offset(guc, guc->ads_vma); > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index 26cae4846c82..ddefc52f6e09 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, > MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ > MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ > MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ > - if (HAS_ENGINE(dev_priv, VCS1)) \ > + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \ > MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ > } while (0) > > diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c > index 540017fed908..7498878e6289 100644 > --- a/drivers/gpu/drm/i915/gvt/interrupt.c > +++ b/drivers/gpu/drm/i915/gvt/interrupt.c > @@ -540,7 +540,7 @@ static void gen8_init_irq( > SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); > SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); > > - if (HAS_ENGINE(gvt->gt->i915, VCS1)) { > + if (HAS_ENGINE(gvt->gt, VCS1)) { > SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, > INTEL_GVT_IRQ_INFO_GT1); > SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, > diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c > index 2ccaf78f96e8..86a60bdf0818 100644 > --- a/drivers/gpu/drm/i915/gvt/mmio_context.c > +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c > @@ -171,7 +171,7 @@ static void load_render_mocs(const struct intel_engine_cs *engine) > return; > > for (ring_id = 0; ring_id < cnt; ring_id++) { > - if (!HAS_ENGINE(engine->i915, ring_id)) > + if (!HAS_ENGINE(engine->gt, ring_id)) > continue; > > offset.reg = regs[ring_id]; > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 67102dc26fce..1f9c40cf10ae 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -533,7 +533,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) > > intel_device_info_init_mmio(dev_priv); > > - intel_uncore_prune_mmio_domains(&dev_priv->uncore); > + intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt); > > intel_uc_init_mmio(&dev_priv->gt.uc); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 9aad3ec979bd..17cad4e2cb9c 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1560,18 +1560,19 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) > #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > > -#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) > +#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) > +#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id) > > -#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \ > +#define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ > unsigned int first__ = (first); \ > unsigned int count__ = (count); \ > - (INTEL_INFO(dev_priv)->engine_mask & \ > + (INTEL_INFO((gt)->i915)->engine_mask & \ > GENMASK(first__ + count__ - 1, first__)) >> first__; \ > }) > -#define VDBOX_MASK(dev_priv) \ > - ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS) > -#define VEBOX_MASK(dev_priv) \ > - ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS) > +#define VDBOX_MASK(gt) \ > + ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) > +#define VEBOX_MASK(gt) \ > + ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) > > /* > * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index c27a56aff5de..c0443afa12b9 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -1100,6 +1100,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > { > struct intel_device_info *info = mkwrite_device_info(dev_priv); > struct intel_uncore *uncore = &dev_priv->uncore; > + struct intel_gt *gt = &dev_priv->gt; > unsigned int logical_vdbox = 0; > unsigned int i; > u32 media_fuse; > @@ -1116,7 +1117,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > GEN11_GT_VEBOX_DISABLE_SHIFT; > > for (i = 0; i < I915_MAX_VCS; i++) { > - if (!HAS_ENGINE(dev_priv, _VCS(i))) { > + if (!HAS_ENGINE(gt, _VCS(i))) { > vdbox_mask &= ~BIT(i); > continue; > } > @@ -1136,11 +1137,11 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); > } > drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", > - vdbox_mask, VDBOX_MASK(dev_priv)); > - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(dev_priv)); > + vdbox_mask, VDBOX_MASK(gt)); > + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); > > for (i = 0; i < I915_MAX_VECS; i++) { > - if (!HAS_ENGINE(dev_priv, _VECS(i))) { > + if (!HAS_ENGINE(gt, _VECS(i))) { > vebox_mask &= ~BIT(i); > continue; > } > @@ -1151,6 +1152,6 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > } > } > drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", > - vebox_mask, VEBOX_MASK(dev_priv)); > - GEM_BUG_ON(vebox_mask != VEBOX_MASK(dev_priv)); > + vebox_mask, VEBOX_MASK(gt)); > + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); > } > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2a32d6230795..40f6fe69b70a 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7105,7 +7105,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) > > /* This is not a WA. Enable VD HCP & MFX_ENC powergate */ > for (i = 0; i < I915_MAX_VCS; i++) { > - if (HAS_ENGINE(dev_priv, _VCS(i))) > + if (HAS_ENGINE(&dev_priv->gt, _VCS(i))) > vd_pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) | > VDN_MFX_POWERGATE_ENABLE(i); > } > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 592364aed2da..bd4b45191f7b 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1529,6 +1529,8 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) > (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) > > if (INTEL_GEN(i915) >= 11) { > + /* we'll prune the domains of missing engines later */ > + intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask; > int i; > > uncore->funcs.force_wake_get = fw_domains_get_with_fallback; > @@ -1541,7 +1543,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) > FORCEWAKE_ACK_BLITTER_GEN9); > > for (i = 0; i < I915_MAX_VCS; i++) { > - if (!HAS_ENGINE(i915, _VCS(i))) > + if (!__HAS_ENGINE(emask, _VCS(i))) > continue; > > fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, > @@ -1549,7 +1551,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) > FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); > } > for (i = 0; i < I915_MAX_VECS; i++) { > - if (!HAS_ENGINE(i915, _VECS(i))) > + if (!__HAS_ENGINE(emask, _VECS(i))) > continue; > > fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, > @@ -1844,20 +1846,20 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore) > * the forcewake domains. Prune them, to make sure they only reference existing > * engines. > */ > -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) > +void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, > + struct intel_gt *gt) > { > - struct drm_i915_private *i915 = uncore->i915; > enum forcewake_domains fw_domains = uncore->fw_domains; > enum forcewake_domain_id domain_id; > int i; > > - if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11) > + if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11) > return; > > for (i = 0; i < I915_MAX_VCS; i++) { > domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; > > - if (HAS_ENGINE(i915, _VCS(i))) > + if (HAS_ENGINE(gt, _VCS(i))) > continue; > > if (fw_domains & BIT(domain_id)) > @@ -1867,7 +1869,7 @@ void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore) > for (i = 0; i < I915_MAX_VECS; i++) { > domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; > > - if (HAS_ENGINE(i915, _VECS(i))) > + if (HAS_ENGINE(gt, _VECS(i))) > continue; > > if (fw_domains & BIT(domain_id)) > diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h > index 8d3aa8b9acf9..c4b22d9d0b45 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.h > +++ b/drivers/gpu/drm/i915/intel_uncore.h > @@ -35,6 +35,7 @@ > struct drm_i915_private; > struct intel_runtime_pm; > struct intel_uncore; > +struct intel_gt; > > struct intel_uncore_mmio_debug { > spinlock_t lock; /** lock is also taken in irq contexts. */ > @@ -186,7 +187,8 @@ intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); > void intel_uncore_init_early(struct intel_uncore *uncore, > struct drm_i915_private *i915); > int intel_uncore_init_mmio(struct intel_uncore *uncore); > -void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore); > +void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, > + struct intel_gt *gt); > bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore); > bool intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore); > void intel_uncore_fini_mmio(struct intel_uncore *uncore); > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From patchwork at emeril.freedesktop.org Fri Jun 26 14:21:34 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 14:21:34 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?iommu=3A_Remove_usage_of_dev-=3Earchdata=2Eiommu?= In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <159318129466.22985.3914755809005033094@emeril.freedesktop.org> == Series Details == Series: iommu: Remove usage of dev->archdata.iommu URL : https://patchwork.freedesktop.org/series/78822/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:184:13: warning: cast to restricted __le32 From chris at chris-wilson.co.uk Fri Jun 26 14:35:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 15:35:58 +0100 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE In-Reply-To: <20200625234212.22811-3-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-3-daniele.ceraolospurio@intel.com> Message-ID: <159318215858.13600.17747631516505792821@build.alporthouse.com> Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:07) > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index 26cae4846c82..ddefc52f6e09 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, > MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ > MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ > MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ > - if (HAS_ENGINE(dev_priv, VCS1)) \ > + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \ Implicit param! It can switch to gvt->gt for all callsites, killing the dev_priv locals. -Chris From tvrtko.ursulin at linux.intel.com Fri Jun 26 14:38:14 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 26 Jun 2020 15:38:14 +0100 Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio In-Reply-To: <20200625234212.22811-4-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-4-daniele.ceraolospurio@intel.com> Message-ID: <f4d46ba1-d908-07d6-5ef7-e982bb88af37@linux.intel.com> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: > All the info we read in intel_device_info_init_mmio are engine-related > and since we already have an engine_init_mmio function we can just > perform the operations from there. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++- > drivers/gpu/drm/i915/i915_drv.c | 4 -- > drivers/gpu/drm/i915/intel_device_info.c | 66 --------------------- > drivers/gpu/drm/i915/intel_device_info.h | 2 - > 4 files changed, 71 insertions(+), 73 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index be92d1ef9aa9..8497106eb3a6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt) > } > } > > +/* > + * Determine which engines are fused off in our particular hardware. Since the > + * fuse register is in the blitter powerwell, we need forcewake to be ready at > + * this point (but later we need to prune the forcewake domains for engines that > + * are indeed fused off). > + */ > +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > +{ > + struct drm_i915_private *i915 = gt->i915; > + struct intel_device_info *info = mkwrite_device_info(i915); > + struct intel_uncore *uncore = gt->uncore; > + unsigned int logical_vdbox = 0; > + unsigned int i; > + u32 media_fuse; > + u16 vdbox_mask; > + u16 vebox_mask; > + > + if (INTEL_GEN(i915) < 11) > + return info->engine_mask; > + > + media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); > + > + vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; > + vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> > + GEN11_GT_VEBOX_DISABLE_SHIFT; > + > + for (i = 0; i < I915_MAX_VCS; i++) { > + if (!HAS_ENGINE(gt, _VCS(i))) { > + vdbox_mask &= ~BIT(i); > + continue; > + } > + > + if (!(BIT(i) & vdbox_mask)) { > + info->engine_mask &= ~BIT(_VCS(i)); > + drm_dbg(&i915->drm, "vcs%u fused off\n", i); > + continue; > + } > + > + /* > + * In Gen11, only even numbered logical VDBOXes are > + * hooked up to an SFC (Scaler & Format Converter) unit. > + * In TGL each VDBOX has access to an SFC. > + */ > + if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) > + RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i); > + } > + drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", > + vdbox_mask, VDBOX_MASK(gt)); > + GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); > + > + for (i = 0; i < I915_MAX_VECS; i++) { > + if (!HAS_ENGINE(gt, _VECS(i))) { > + vebox_mask &= ~BIT(i); > + continue; > + } > + > + if (!(BIT(i) & vebox_mask)) { > + info->engine_mask &= ~BIT(_VECS(i)); > + drm_dbg(&i915->drm, "vecs%u fused off\n", i); > + } > + } > + drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n", > + vebox_mask, VEBOX_MASK(gt)); > + GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); > + > + return info->engine_mask; > +} > + > /** > * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers > * @gt: pointer to struct intel_gt > @@ -460,7 +528,7 @@ int intel_engines_init_mmio(struct intel_gt *gt) > { > struct drm_i915_private *i915 = gt->i915; > struct intel_device_info *device_info = mkwrite_device_info(i915); > - const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask; > + const unsigned int engine_mask = init_engine_mask(gt); > unsigned int mask = 0; > unsigned int i; > int err; > @@ -497,6 +565,8 @@ int intel_engines_init_mmio(struct intel_gt *gt) > > intel_setup_engine_capabilities(gt); > > + intel_uncore_prune_engine_fw_domains(gt->uncore, gt); > + > return 0; > > cleanup: > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 1f9c40cf10ae..611287353420 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -531,10 +531,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) > /* Try to make sure MCHBAR is enabled before poking at it */ > intel_setup_mchbar(dev_priv); > > - intel_device_info_init_mmio(dev_priv); > - > - intel_uncore_prune_engine_fw_domains(&dev_priv->uncore, &dev_priv->gt); > - > intel_uc_init_mmio(&dev_priv->gt.uc); > > ret = intel_engines_init_mmio(&dev_priv->gt); > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index c0443afa12b9..92ebea35c752 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -1089,69 +1089,3 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps, > yesno(caps->has_logical_contexts)); > drm_printf(p, "scheduler: %x\n", caps->scheduler); > } > - > -/* > - * Determine which engines are fused off in our particular hardware. Since the > - * fuse register is in the blitter powerwell, we need forcewake to be ready at > - * this point (but later we need to prune the forcewake domains for engines that > - * are indeed fused off). > - */ > -void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) > -{ > - struct intel_device_info *info = mkwrite_device_info(dev_priv); > - struct intel_uncore *uncore = &dev_priv->uncore; > - struct intel_gt *gt = &dev_priv->gt; > - unsigned int logical_vdbox = 0; > - unsigned int i; > - u32 media_fuse; > - u16 vdbox_mask; > - u16 vebox_mask; > - > - if (INTEL_GEN(dev_priv) < 11) > - return; > - > - media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); > - > - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; > - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> > - GEN11_GT_VEBOX_DISABLE_SHIFT; > - > - for (i = 0; i < I915_MAX_VCS; i++) { > - if (!HAS_ENGINE(gt, _VCS(i))) { > - vdbox_mask &= ~BIT(i); > - continue; > - } > - > - if (!(BIT(i) & vdbox_mask)) { > - info->engine_mask &= ~BIT(_VCS(i)); > - drm_dbg(&dev_priv->drm, "vcs%u fused off\n", i); > - continue; > - } > - > - /* > - * In Gen11, only even numbered logical VDBOXes are > - * hooked up to an SFC (Scaler & Format Converter) unit. > - * In TGL each VDBOX has access to an SFC. > - */ > - if (INTEL_GEN(dev_priv) >= 12 || logical_vdbox++ % 2 == 0) > - RUNTIME_INFO(dev_priv)->vdbox_sfc_access |= BIT(i); > - } > - drm_dbg(&dev_priv->drm, "vdbox enable: %04x, instances: %04lx\n", > - vdbox_mask, VDBOX_MASK(gt)); > - GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt)); > - > - for (i = 0; i < I915_MAX_VECS; i++) { > - if (!HAS_ENGINE(gt, _VECS(i))) { > - vebox_mask &= ~BIT(i); > - continue; > - } > - > - if (!(BIT(i) & vebox_mask)) { > - info->engine_mask &= ~BIT(_VECS(i)); > - drm_dbg(&dev_priv->drm, "vecs%u fused off\n", i); > - } > - } > - drm_dbg(&dev_priv->drm, "vebox enable: %04x, instances: %04lx\n", > - vebox_mask, VEBOX_MASK(gt)); > - GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt)); > -} > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 8d62b8538585..fa60fdc1d75a 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -250,8 +250,6 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info, > void intel_device_info_print_topology(const struct sseu_dev_info *sseu, > struct drm_printer *p); > > -void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); > - > void intel_driver_caps_print(const struct intel_driver_caps *caps, > struct drm_printer *p); > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From chris at chris-wilson.co.uk Fri Jun 26 14:38:58 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 15:38:58 +0100 Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio In-Reply-To: <20200625234212.22811-4-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-4-daniele.ceraolospurio@intel.com> Message-ID: <159318233803.13600.604722317964699116@build.alporthouse.com> Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:08) > All the info we read in intel_device_info_init_mmio are engine-related > and since we already have an engine_init_mmio function we can just > perform the operations from there. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++- > drivers/gpu/drm/i915/i915_drv.c | 4 -- > drivers/gpu/drm/i915/intel_device_info.c | 66 --------------------- > drivers/gpu/drm/i915/intel_device_info.h | 2 - > 4 files changed, 71 insertions(+), 73 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index be92d1ef9aa9..8497106eb3a6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt) > } > } > > +/* > + * Determine which engines are fused off in our particular hardware. Since the > + * fuse register is in the blitter powerwell, we need forcewake to be ready at > + * this point (but later we need to prune the forcewake domains for engines that > + * are indeed fused off). > + */ > +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > +{ > + struct drm_i915_private *i915 = gt->i915; > + struct intel_device_info *info = mkwrite_device_info(i915); > + struct intel_uncore *uncore = gt->uncore; > + unsigned int logical_vdbox = 0; > + unsigned int i; > + u32 media_fuse; > + u16 vdbox_mask; > + u16 vebox_mask; assert_forcewakes_active(uncore, FORCEWAKE_BLITTER) ? Since it's called out in the comment, might as well reinforce that with an assert. -Chris From patchwork at emeril.freedesktop.org Fri Jun 26 14:40:21 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 14:40:21 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgaW9t?= =?utf-8?q?mu=3A_Remove_usage_of_dev-=3Earchdata=2Eiommu?= In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <159318242192.22985.17120635021148186988@emeril.freedesktop.org> == Series Details == Series: iommu: Remove usage of dev->archdata.iommu URL : https://patchwork.freedesktop.org/series/78822/ State : success == Summary == CI Bug Log - changes from CI_DRM_8667 -> Patchwork_18026 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/index.html Known issues ------------ Here are the changes found in Patchwork_18026 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-y/igt at debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-tgl-y/igt at debugfs_test@read_all_entries.html * igt at gem_exec_store@basic: - fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-y/igt at gem_exec_store@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-tgl-y/igt at gem_exec_store@basic.html * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][5] -> [INCOMPLETE][6] ([i915#1242]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html - fi-tgl-u2: [PASS][7] -> [FAIL][8] ([i915#1888]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-n2820: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-byt-n2820/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html #### Possible fixes #### * igt at gem_render_linear_blits@basic: - fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-y/igt at gem_render_linear_blits@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-tgl-y/igt at gem_render_linear_blits@basic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][17] ([i915#402]) -> [PASS][18] +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_flip@basic-plain-flip at a-dp1: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at kms_flip@basic-plain-flip at a-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-kbl-x1275/igt at kms_flip@basic-plain-flip at a-dp1.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#1982] / [i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 39) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8667 -> Patchwork_18026 CI-20190529: 20190529 CI_DRM_8667: 57a1fc457c260002189382a406e920465d540d53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18026: 1cd7039a67696ccd0d9c7dde67aac0b868c40220 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 1cd7039a6769 powerpc/dma: Remove dev->archdata.iommu_domain c154e15c0d13 arm64: Remove dev->archdata.iommu pointer e36fe82cd6d3 arm: Remove dev->archdata.iommu pointer beb0e5de86ca ia64: Remove dev->archdata.iommu pointer b86f57d96a87 x86: Remove dev->archdata.iommu pointer be1951b09735 iommu/mediatek: Do no use dev->archdata.iommu d14eb31e19bb iommu/pamu: Use dev_iommu_priv_get/set() df87e91a4c59 iommu/tegra: Use dev_iommu_priv_get/set() 3168eb5065df iommu/rockchip: Use dev_iommu_priv_get/set() 79dfab955ac4 iommu/omap: Use dev_iommu_priv_get/set() 000b842cda59 iommu/msm: Use dev_iommu_priv_get/set() 751d62a601db iommu/vt-d: Use dev_iommu_priv_get/set() ea59789bb2c8 iommu/exynos: Use dev_iommu_priv_get/set() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18026/index.html From thomas_os at shipmail.org Fri Jun 26 14:41:20 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Fri, 26 Jun 2020 16:41:20 +0200 Subject: [Intel-gfx] [PATCH 06/26] drm/i915: Parse command buffer earlier in eb_relocate(slow) In-Reply-To: <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> Message-ID: <6f313791-d0f7-465a-e4ab-63826ef70bf8@shipmail.org> On 6/23/20 4:28 PM, Maarten Lankhorst wrote: > We want to introduce backoff logic, but we need to lock the > pool object as well for command parsing. Because of this, we > will need backoff logic for the engine pool obj, move the batch > validation up slightly to eb_lookup_vmas, and the actual command > parsing in a separate function which can get called from execbuf > relocation fast and slowpath. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 66 ++++++++++--------- > 1 file changed, 36 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index f896b1a4b38a..7cb44915cfc7 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -290,6 +290,8 @@ struct i915_execbuffer { > struct eb_vma_array *array; > }; > > +static int eb_parse(struct i915_execbuffer *eb); > + > static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) > { > return intel_engine_requires_cmd_parser(eb->engine) || > @@ -873,6 +875,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) > > static int eb_lookup_vmas(struct i915_execbuffer *eb) > { > + struct drm_i915_private *i915 = eb->i915; > unsigned int batch = eb_batch_index(eb); > unsigned int i; > int err = 0; > @@ -886,18 +889,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) > vma = eb_lookup_vma(eb, eb->exec[i].handle); > if (IS_ERR(vma)) { > err = PTR_ERR(vma); > - break; > + goto err; > } > > err = eb_validate_vma(eb, &eb->exec[i], vma); > if (unlikely(err)) { > i915_vma_put(vma); > - break; > + goto err; > } > > eb_add_vma(eb, i, batch, vma); > } > > + if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) { > + drm_dbg(&i915->drm, > + "Attempting to use self-modifying batch buffer\n"); > + return -EINVAL; > + } > + > + if (range_overflows_t(u64, > + eb->batch_start_offset, eb->batch_len, > + eb->batch->vma->size)) { > + drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); > + return -EINVAL; > + } > + > + if (eb->batch_len == 0) > + eb->batch_len = eb->batch->vma->size - eb->batch_start_offset; > + > + return 0; > + > +err: > eb->vma[i].vma = NULL; > return err; > } > @@ -1809,7 +1831,7 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb) > return 0; > } > > -static noinline int eb_relocate_slow(struct i915_execbuffer *eb) > +static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) > { > bool have_copy = false; > struct eb_vma *ev; > @@ -1872,6 +1894,11 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) > if (err) > goto err; > > + /* as last step, parse the command buffer */ > + err = eb_parse(eb); > + if (err) > + goto err; > + > /* > * Leave the user relocations as are, this is the painfully slow path, > * and we want to avoid the complication of dropping the lock whilst > @@ -1904,7 +1931,7 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) > return err; > } > > -static int eb_relocate(struct i915_execbuffer *eb) > +static int eb_relocate_parse(struct i915_execbuffer *eb) > { > int err; > > @@ -1932,7 +1959,7 @@ static int eb_relocate(struct i915_execbuffer *eb) > return eb_relocate_slow(eb); > } > > - return 0; > + return eb_parse(eb); > } > > static int eb_move_to_gpu(struct i915_execbuffer *eb) > @@ -2870,7 +2897,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, > if (unlikely(err)) > goto err_context; > > - err = eb_relocate(&eb); > + err = eb_relocate_parse(&eb); > if (err) { > /* > * If the user expects the execobject.offset and > @@ -2883,33 +2910,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, > goto err_vma; > } > > - if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) { > - drm_dbg(&i915->drm, > - "Attempting to use self-modifying batch buffer\n"); > - err = -EINVAL; > - goto err_vma; > - } > - > - if (range_overflows_t(u64, > - eb.batch_start_offset, eb.batch_len, > - eb.batch->vma->size)) { > - drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); > - err = -EINVAL; > - goto err_vma; > - } > - > - if (eb.batch_len == 0) > - eb.batch_len = eb.batch->vma->size - eb.batch_start_offset; > - > - err = eb_parse(&eb); > - if (err) > - goto err_vma; > - > /* > * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure > * batch" bit. Hence we need to pin secure batches into the global gtt. > * hsw should have this fixed, but bdw mucks it up again. */ > - batch = eb.batch->vma; > if (eb.batch_flags & I915_DISPATCH_SECURE) { > struct i915_vma *vma; > > @@ -2923,13 +2927,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, > * fitting due to fragmentation. > * So this is actually safe. > */ > - vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); > + vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); > if (IS_ERR(vma)) { > err = PTR_ERR(vma); > goto err_parse; > } > > batch = vma; > + } else { > + batch = eb.batch->vma; > } > Hmm, it's late friday afternoon so that might be the cause, but I fail to see what the above hunk is trying to achieve? > /* All GPU relocation batches must be submitted prior to the user rq */ From patchwork at emeril.freedesktop.org Fri Jun 26 14:44:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 14:44:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/display=3A_Implement_new_combo_phy_initialization_?= =?utf-8?q?step_=28rev2=29?= In-Reply-To: <20200625195252.39312-1-jose.souza@intel.com> References: <20200625195252.39312-1-jose.souza@intel.com> Message-ID: <159318268151.22983.9349251992760871840@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Implement new combo phy initialization step (rev2) URL : https://patchwork.freedesktop.org/series/78796/ State : warning == Summary == $ dim checkpatch origin/drm-tip faec0ee3d268 drm/i915/display: Implement new combo phy initialization step -:89: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #89: FILE: drivers/gpu/drm/i915/i915_reg.h:2082: +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) total: 0 errors, 1 warnings, 0 checks, 58 lines checked From tvrtko.ursulin at linux.intel.com Fri Jun 26 14:45:19 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 26 Jun 2020 15:45:19 +0100 Subject: [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info In-Reply-To: <20200625234212.22811-5-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-5-daniele.ceraolospurio@intel.com> Message-ID: <78523c30-5aa6-ee94-722f-a0ed40b320b8@linux.intel.com> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: > Since the engines belong to the GT, move the runtime-updated list of > available engines to the intel_gt struct. The original mask has been > renamed to indicate it contains the maximum engine list that can be > found on a matching device. > > In preparation for other info being moved to the gt in follow up patches > (sseu), introduce an intel_gt_info structure to group all gt-related > runtime info. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 +++--- > drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++ > drivers/gpu/drm/i915/gt/intel_gt.h | 4 ++ > drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 ++++ > drivers/gpu/drm/i915/gt/intel_reset.c | 6 +-- > .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 ++-- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > drivers/gpu/drm/i915/i915_debugfs.c | 2 + > drivers/gpu/drm/i915/i915_drv.c | 1 + > drivers/gpu/drm/i915/i915_drv.h | 6 +-- > drivers/gpu/drm/i915/i915_gpu_error.c | 23 ++++++---- > drivers/gpu/drm/i915/i915_gpu_error.h | 3 ++ > drivers/gpu/drm/i915/i915_pci.c | 42 +++++++++---------- > drivers/gpu/drm/i915/intel_device_info.c | 1 - > drivers/gpu/drm/i915/intel_device_info.h | 7 +--- > drivers/gpu/drm/i915/intel_uncore.c | 2 +- > drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- > .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +- > 21 files changed, 84 insertions(+), 62 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index c38ab51e82f0..7ffac711e4b4 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -1973,8 +1973,7 @@ static int eb_submit(struct i915_execbuffer *eb, struct i915_vma *batch) > > static int num_vcs_engines(const struct drm_i915_private *i915) > { > - return hweight64(INTEL_INFO(i915)->engine_mask & > - GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0)); > + return hweight64(VDBOX_MASK(&i915->gt)); > } > > /* > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 8497106eb3a6..3af58df3b13e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -370,7 +370,7 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine) > * instances. > */ > if ((INTEL_GEN(i915) >= 11 && > - RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) || > + engine->gt->info.vdbox_sfc_access & engine->mask) || > (INTEL_GEN(i915) >= 9 && engine->instance == 0)) > engine->uabi_capabilities |= > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; > @@ -459,7 +459,7 @@ void intel_engines_free(struct intel_gt *gt) > static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_device_info *info = mkwrite_device_info(i915); > + struct intel_gt_info *info = >->info; > struct intel_uncore *uncore = gt->uncore; > unsigned int logical_vdbox = 0; > unsigned int i; > @@ -467,6 +467,8 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > u16 vdbox_mask; > u16 vebox_mask; > > + info->engine_mask = INTEL_INFO(i915)->max_engine_mask; > + > if (INTEL_GEN(i915) < 11) > return info->engine_mask; > > @@ -494,7 +496,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > * In TGL each VDBOX has access to an SFC. > */ > if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) > - RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i); > + gt->info.vdbox_sfc_access |= BIT(i); > } > drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", > vdbox_mask, VDBOX_MASK(gt)); > @@ -527,7 +529,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > int intel_engines_init_mmio(struct intel_gt *gt) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_device_info *device_info = mkwrite_device_info(i915); > const unsigned int engine_mask = init_engine_mask(gt); > unsigned int mask = 0; > unsigned int i; > @@ -557,9 +558,9 @@ int intel_engines_init_mmio(struct intel_gt *gt) > * engines. > */ > if (drm_WARN_ON(&i915->drm, mask != engine_mask)) > - device_info->engine_mask = mask; > + gt->info.engine_mask = mask; > > - RUNTIME_INFO(i915)->num_engines = hweight32(mask); > + gt->info.num_engines = hweight32(mask); > > intel_gt_check_and_clear_faults(gt); > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index ebc29b6ee86c..d0ae1cb5c7c9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -642,3 +642,9 @@ void intel_gt_driver_late_release(struct intel_gt *gt) > intel_gt_fini_timelines(gt); > intel_engines_free(gt); > } > + > +void intel_gt_info_print(const struct intel_gt_info *info, > + struct drm_printer *p) > +{ > + drm_printf(p, "available engines: %x\n", info->engine_mask); > +} > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h > index 4fac043750aa..15142e2a3b22 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt.h > @@ -11,6 +11,7 @@ > #include "intel_reset.h" > > struct drm_i915_private; > +struct drm_printer; > > #define GT_TRACE(gt, fmt, ...) do { \ > const struct intel_gt *gt__ __maybe_unused = (gt); \ > @@ -68,4 +69,7 @@ static inline bool intel_gt_has_init_error(const struct intel_gt *gt) > return test_bit(I915_WEDGED_ON_INIT, >->reset.flags); > } > > +void intel_gt_info_print(const struct intel_gt_info *info, > + struct drm_printer *p); > + > #endif /* __INTEL_GT_H__ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h > index 0cc1d6b185dc..bb7551867c00 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h > @@ -109,6 +109,14 @@ struct intel_gt { > struct intel_gt_buffer_pool buffer_pool; > > struct i915_vma *scratch; > + > + struct intel_gt_info { > + intel_engine_mask_t engine_mask; > + u8 num_engines; > + > + /* Media engine access to SFC per instance */ > + u8 vdbox_sfc_access; > + } info; > }; > > enum intel_gt_scratch_field { > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c > index 0156f1f5c736..952cd6e9b88e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_reset.c > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c > @@ -342,7 +342,7 @@ static int gen6_reset_engines(struct intel_gt *gt, > static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask) > { > struct intel_uncore *uncore = engine->uncore; > - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access; > + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; > i915_reg_t sfc_forced_lock, sfc_forced_lock_ack; > u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit; > i915_reg_t sfc_usage; > @@ -417,7 +417,7 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask) > static void gen11_unlock_sfc(struct intel_engine_cs *engine) > { > struct intel_uncore *uncore = engine->uncore; > - u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access; > + u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; > i915_reg_t sfc_forced_lock; > u32 sfc_forced_lock_bit; > > @@ -1246,7 +1246,7 @@ void intel_gt_handle_error(struct intel_gt *gt, > */ > wakeref = intel_runtime_pm_get(gt->uncore->rpm); > > - engine_mask &= INTEL_INFO(gt->i915)->engine_mask; > + engine_mask &= gt->info.engine_mask; > > if (flags & I915_ERROR_CAPTURE) { > i915_capture_error_state(gt->i915); > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 68a08486fc87..b09b83deecef 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -649,7 +649,7 @@ static inline int mi_set_context(struct i915_request *rq, > struct drm_i915_private *i915 = engine->i915; > enum intel_engine_id id; > const int num_engines = > - IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; > + IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; > bool force_restore = false; > int len; > u32 *cs; > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index daa4aabab9a7..b3678b5f9655 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -963,7 +963,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer, > goto out; > > if (i915_request_wait(head, 0, > - 2 * RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3)) < 0) { > + 2 * engine->gt->info.num_engines * (count + 2) * (count + 3)) < 0) { > pr_err("Failed to slice along semaphore chain of length (%d, %d)!\n", > count, n); > GEM_TRACE_DUMP(); > @@ -3569,8 +3569,7 @@ static int smoke_crescendo(struct preempt_smoke *smoke, unsigned int flags) > } > > pr_info("Submitted %lu crescendo:%x requests across %d engines and %d contexts\n", > - count, flags, > - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext); > + count, flags, smoke->gt->info.num_engines, smoke->ncontext); > return 0; > } > > @@ -3597,8 +3596,7 @@ static int smoke_random(struct preempt_smoke *smoke, unsigned int flags) > } while (count < smoke->ncontext && !__igt_timeout(end_time, NULL)); > > pr_info("Submitted %lu random:%x requests across %d engines and %d contexts\n", > - count, flags, > - RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext); > + count, flags, smoke->gt->info.num_engines, smoke->ncontext); > return 0; > } > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index fbdd6b0677db..c10ae1660e53 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -106,7 +106,7 @@ static void __guc_ads_init(struct intel_guc *guc) > > blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt); > blob->system_info.vebox_enable_mask = VEBOX_MASK(gt); > - blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; > + blob->system_info.vdbox_sfc_support_mask = gt->info.vdbox_sfc_access; > > base = intel_guc_ggtt_offset(guc, guc->ads_vma); > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index ddefc52f6e09..e047a4950f5f 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -347,7 +347,7 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, > gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); > vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; > } > - engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask; > + engine_mask &= vgpu->gvt->gt->info.engine_mask; > } > > /* vgpu_lock already hold by emulate mmio r/w */ > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 8594a8ef08ce..cad1620d2a7e 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -34,6 +34,7 @@ > #include "gem/i915_gem_context.h" > #include "gt/intel_gt_buffer_pool.h" > #include "gt/intel_gt_clock_utils.h" > +#include "gt/intel_gt.h" > #include "gt/intel_gt_pm.h" > #include "gt/intel_gt_requests.h" > #include "gt/intel_reset.h" > @@ -61,6 +62,7 @@ static int i915_capabilities(struct seq_file *m, void *data) > > intel_device_info_print_static(INTEL_INFO(i915), &p); > intel_device_info_print_runtime(RUNTIME_INFO(i915), &p); > + intel_gt_info_print(&i915->gt.info, &p); > intel_driver_caps_print(&i915->caps, &p); > > kernel_param_lock(THIS_MODULE); > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 611287353420..67789df42be8 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -886,6 +886,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv) > > intel_device_info_print_static(INTEL_INFO(dev_priv), &p); > intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); > + intel_gt_info_print(&dev_priv->gt.info, &p); > } > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 17cad4e2cb9c..fa01bf0929e0 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1254,7 +1254,7 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) > > /* Iterator over subset of engines selected by mask */ > #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ > - for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ > + for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ > (tmp__) ? \ > ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ > 0;) > @@ -1561,12 +1561,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > > #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) > -#define HAS_ENGINE(gt, id) __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id) > +#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) > > #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ > unsigned int first__ = (first); \ > unsigned int count__ = (count); \ > - (INTEL_INFO((gt)->i915)->engine_mask & \ > + ((gt)->info.engine_mask & \ > GENMASK(first__ + count__ - 1, first__)) >> first__; \ > }) > #define VDBOX_MASK(gt) \ > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 866166ada10e..9cb9aa39c33d 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -42,6 +42,7 @@ > > #include "gem/i915_gem_context.h" > #include "gem/i915_gem_lmem.h" > +#include "gt/intel_gt.h" > #include "gt/intel_gt_pm.h" > > #include "i915_drv.h" > @@ -619,16 +620,15 @@ static void print_error_vma(struct drm_i915_error_state_buf *m, > } > > static void err_print_capabilities(struct drm_i915_error_state_buf *m, > - const struct intel_device_info *info, > - const struct intel_runtime_info *runtime, > - const struct intel_driver_caps *caps) > + struct i915_gpu_coredump *error) > { > struct drm_printer p = i915_error_printer(m); > > - intel_device_info_print_static(info, &p); > - intel_device_info_print_runtime(runtime, &p); > - intel_device_info_print_topology(&runtime->sseu, &p); > - intel_driver_caps_print(caps, &p); > + intel_device_info_print_static(&error->device_info, &p); > + intel_device_info_print_runtime(&error->runtime_info, &p); > + intel_device_info_print_topology(&error->runtime_info.sseu, &p); > + intel_gt_info_print(&error->gt->info, &p); > + intel_driver_caps_print(&error->driver_caps, &p); > } > > static void err_print_params(struct drm_i915_error_state_buf *m, > @@ -798,8 +798,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, > if (error->display) > intel_display_print_error_state(m, error->display); > > - err_print_capabilities(m, &error->device_info, &error->runtime_info, > - &error->driver_caps); > + err_print_capabilities(m, error); > err_print_params(m, &error->params); > } > > @@ -1630,6 +1629,11 @@ static void gt_record_regs(struct intel_gt_coredump *gt) > gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); > } > > +static void gt_record_info(struct intel_gt_coredump *gt) > +{ > + memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); > +} > + > /* > * Generate a semi-unique error code. The code is not meant to have meaning, The > * code's only purpose is to try to prevent false duplicated bug reports by > @@ -1808,6 +1812,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) > return ERR_PTR(-ENOMEM); > } > > + gt_record_info(error->gt); > gt_record_engines(error->gt, compress); > > if (INTEL_INFO(i915)->has_gt_uc) > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h > index 76b80fbfb7e9..0220b0992808 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.h > +++ b/drivers/gpu/drm/i915/i915_gpu_error.h > @@ -15,6 +15,7 @@ > #include <drm/drm_mm.h> > > #include "gt/intel_engine.h" > +#include "gt/intel_gt_types.h" > #include "gt/uc/intel_uc_fw.h" > > #include "intel_device_info.h" > @@ -118,6 +119,8 @@ struct intel_gt_coredump { > bool awake; > bool simulated; > > + struct intel_gt_info info; > + > /* Generic register state */ > u32 eir; > u32 pgtbl_er; > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index e5fdf17cd9cd..7658025a791f 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -168,7 +168,7 @@ > .gpu_reset_clobbers_display = true, \ > .hws_needs_physical = 1, \ > .unfenced_needs_alignment = 1, \ > - .engine_mask = BIT(RCS0), \ > + .max_engine_mask = BIT(RCS0), \ > .has_snoop = true, \ > .has_coherent_ggtt = false, \ > .dma_mask_size = 32, \ > @@ -188,7 +188,7 @@ > .gpu_reset_clobbers_display = true, \ > .hws_needs_physical = 1, \ > .unfenced_needs_alignment = 1, \ > - .engine_mask = BIT(RCS0), \ > + .max_engine_mask = BIT(RCS0), \ > .has_snoop = true, \ > .has_coherent_ggtt = false, \ > .dma_mask_size = 32, \ > @@ -225,7 +225,7 @@ static const struct intel_device_info i865g_info = { > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ > .display.has_gmch = 1, \ > .gpu_reset_clobbers_display = true, \ > - .engine_mask = BIT(RCS0), \ > + .max_engine_mask = BIT(RCS0), \ > .has_snoop = true, \ > .has_coherent_ggtt = true, \ > .dma_mask_size = 32, \ > @@ -316,7 +316,7 @@ static const struct intel_device_info pnv_m_info = { > .display.has_hotplug = 1, \ > .display.has_gmch = 1, \ > .gpu_reset_clobbers_display = true, \ > - .engine_mask = BIT(RCS0), \ > + .max_engine_mask = BIT(RCS0), \ > .has_snoop = true, \ > .has_coherent_ggtt = true, \ > .dma_mask_size = 36, \ > @@ -348,7 +348,7 @@ static const struct intel_device_info i965gm_info = { > static const struct intel_device_info g45_info = { > GEN4_FEATURES, > PLATFORM(INTEL_G45), > - .engine_mask = BIT(RCS0) | BIT(VCS0), > + .max_engine_mask = BIT(RCS0) | BIT(VCS0), > .gpu_reset_clobbers_display = false, > }; > > @@ -358,7 +358,7 @@ static const struct intel_device_info gm45_info = { > .is_mobile = 1, > .display.has_fbc = 1, > .display.supports_tv = 1, > - .engine_mask = BIT(RCS0) | BIT(VCS0), > + .max_engine_mask = BIT(RCS0) | BIT(VCS0), > .gpu_reset_clobbers_display = false, > }; > > @@ -367,7 +367,7 @@ static const struct intel_device_info gm45_info = { > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ > .display.has_hotplug = 1, \ > - .engine_mask = BIT(RCS0) | BIT(VCS0), \ > + .max_engine_mask = BIT(RCS0) | BIT(VCS0), \ > .has_snoop = true, \ > .has_coherent_ggtt = true, \ > /* ilk does support rc6, but we do not implement [power] contexts */ \ > @@ -397,7 +397,7 @@ static const struct intel_device_info ilk_m_info = { > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ > .display.has_hotplug = 1, \ > .display.has_fbc = 1, \ > - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ > + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ > .has_coherent_ggtt = true, \ > .has_llc = 1, \ > .has_rc6 = 1, \ > @@ -448,7 +448,7 @@ static const struct intel_device_info snb_m_gt2_info = { > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \ > .display.has_hotplug = 1, \ > .display.has_fbc = 1, \ > - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ > + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ > .has_coherent_ggtt = true, \ > .has_llc = 1, \ > .has_rc6 = 1, \ > @@ -519,7 +519,7 @@ static const struct intel_device_info vlv_info = { > .ppgtt_size = 31, > .has_snoop = true, > .has_coherent_ggtt = false, > - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), > + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), > .display_mmio_offset = VLV_DISPLAY_BASE, > I9XX_PIPE_OFFSETS, > I9XX_CURSOR_OFFSETS, > @@ -530,7 +530,7 @@ static const struct intel_device_info vlv_info = { > > #define G75_FEATURES \ > GEN7_FEATURES, \ > - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ > + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ > .display.has_ddi = 1, \ > @@ -597,7 +597,7 @@ static const struct intel_device_info bdw_rsvd_info = { > static const struct intel_device_info bdw_gt3_info = { > BDW_PLATFORM, > .gt = 3, > - .engine_mask = > + .max_engine_mask = > BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), > }; > > @@ -608,7 +608,7 @@ static const struct intel_device_info chv_info = { > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), > .display.has_hotplug = 1, > .is_lp = 1, > - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), > + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), > .has_64bit_reloc = 1, > .has_runtime_pm = 1, > .has_rc6 = 1, > @@ -661,7 +661,7 @@ static const struct intel_device_info skl_gt2_info = { > > #define SKL_GT3_PLUS_PLATFORM \ > SKL_PLATFORM, \ > - .engine_mask = \ > + .max_engine_mask = \ > BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) > > > @@ -680,7 +680,7 @@ static const struct intel_device_info skl_gt4_info = { > .is_lp = 1, \ > .num_supported_dbuf_slices = 1, \ > .display.has_hotplug = 1, \ > - .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ > + .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ > .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ > .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ > @@ -743,7 +743,7 @@ static const struct intel_device_info kbl_gt2_info = { > static const struct intel_device_info kbl_gt3_info = { > KBL_PLATFORM, > .gt = 3, > - .engine_mask = > + .max_engine_mask = > BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), > }; > > @@ -764,7 +764,7 @@ static const struct intel_device_info cfl_gt2_info = { > static const struct intel_device_info cfl_gt3_info = { > CFL_PLATFORM, > .gt = 3, > - .engine_mask = > + .max_engine_mask = > BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), > }; > > @@ -833,7 +833,7 @@ static const struct intel_device_info cnl_info = { > static const struct intel_device_info icl_info = { > GEN11_FEATURES, > PLATFORM(INTEL_ICELAKE), > - .engine_mask = > + .max_engine_mask = > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), > }; > > @@ -841,7 +841,7 @@ static const struct intel_device_info ehl_info = { > GEN11_FEATURES, > PLATFORM(INTEL_ELKHARTLAKE), > .require_force_probe = 1, > - .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), > + .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), > .ppgtt_size = 36, > }; > > @@ -877,7 +877,7 @@ static const struct intel_device_info tgl_info = { > GEN12_FEATURES, > PLATFORM(INTEL_TIGERLAKE), > .display.has_modular_fia = 1, > - .engine_mask = > + .max_engine_mask = > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), > }; > > @@ -890,7 +890,7 @@ static const struct intel_device_info rkl_info = { > BIT(TRANSCODER_C), > .require_force_probe = 1, > .display.has_psr_hw_tracking = 0, > - .engine_mask = > + .max_engine_mask = > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), > }; > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 92ebea35c752..a362a66fce11 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -92,7 +92,6 @@ static const char *iommu_name(void) > void intel_device_info_print_static(const struct intel_device_info *info, > struct drm_printer *p) > { > - drm_printf(p, "engines: %x\n", info->engine_mask); > drm_printf(p, "gen: %d\n", info->gen); > drm_printf(p, "gt: %d\n", info->gt); > drm_printf(p, "iommu: %s\n", iommu_name()); > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index fa60fdc1d75a..f03ed95af190 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -157,7 +157,7 @@ struct intel_device_info { > > u8 gen; > u8 gt; /* GT number, 0 if undefined */ > - intel_engine_mask_t engine_mask; /* Engines supported by the HW */ > + intel_engine_mask_t max_engine_mask; /* Engines supported by the HW */ > > enum intel_platform platform; > > @@ -219,8 +219,6 @@ struct intel_runtime_info { > u8 num_sprites[I915_MAX_PIPES]; > u8 num_scalers[I915_MAX_PIPES]; > > - u8 num_engines; > - > /* Slice/subslice/EU info */ > struct sseu_dev_info sseu; > > @@ -228,9 +226,6 @@ struct intel_runtime_info { > > u32 cs_timestamp_frequency_hz; > u32 cs_timestamp_period_ns; > - > - /* Media engine access to SFC per instance */ > - u8 vdbox_sfc_access; > }; > > struct intel_driver_caps { > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index bd4b45191f7b..f5548875836c 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1530,7 +1530,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) > > if (INTEL_GEN(i915) >= 11) { > /* we'll prune the domains of missing engines later */ > - intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask; > + intel_engine_mask_t emask = INTEL_INFO(i915)->max_engine_mask; > int i; > > uncore->funcs.force_wake_get = fw_domains_get_with_fallback; > diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c > index 9271aad7f779..57dd6f5122ee 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_request.c > +++ b/drivers/gpu/drm/i915/selftests/i915_request.c > @@ -1454,7 +1454,7 @@ static int live_breadcrumbs_smoketest(void *arg) > idx++; > } > pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n", > - num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus); > + num_waits, num_fences, idx, ncpus); > > ret = igt_live_test_end(&live) ?: ret; > out_contexts: > diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c > index 9b105b811f1f..0916efa31889 100644 > --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c > +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c > @@ -190,7 +190,8 @@ struct drm_i915_private *mock_gem_device(void) > mock_init_ggtt(i915, &i915->ggtt); > i915->gt.vm = i915_vm_get(&i915->ggtt.vm); > > - mkwrite_device_info(i915)->engine_mask = BIT(0); > + mkwrite_device_info(i915)->max_engine_mask = BIT(0); > + i915->gt.info.engine_mask = BIT(0); > > i915->gt.engine[RCS0] = mock_engine(i915, "mock", RCS0); > if (!i915->gt.engine[RCS0]) > Only thing which looks a bit sub-optimalis the name "max_engine_mask", but maybe it is just me, that max and masks do not go well together. Only alternative I have for the moment is platform_engine_mask? Or the usual double underscore approach. Either way: Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From tvrtko.ursulin at linux.intel.com Fri Jun 26 14:46:15 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 26 Jun 2020 15:46:15 +0100 Subject: [Intel-gfx] [PATCH 5/7] drm/i915: Introduce gt_init_mmio In-Reply-To: <20200625234212.22811-6-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-6-daniele.ceraolospurio@intel.com> Message-ID: <b2a2b011-e987-1508-f466-230c6e6b7f16@linux.intel.com> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: > We already call 2 gt-related init_mmio functions in driver_mmio_probe > and a 3rd one will be added by a follow-up patch, so pre-emptively > introduce a gt_init_mmio function to group them. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt.c | 7 +++++++ > drivers/gpu/drm/i915/gt/intel_gt.h | 1 + > drivers/gpu/drm/i915/i915_drv.c | 4 +--- > 3 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index d0ae1cb5c7c9..949114f09b82 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -44,6 +44,13 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) > gt->ggtt = ggtt; > } > > +int intel_gt_init_mmio(struct intel_gt *gt) > +{ > + intel_uc_init_mmio(>->uc); > + > + return intel_engines_init_mmio(gt); > +} > + > static void init_unused_ring(struct intel_gt *gt, u32 base) > { > struct intel_uncore *uncore = gt->uncore; > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h > index 15142e2a3b22..4bd64ab2b686 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt.h > @@ -36,6 +36,7 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc) > > void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915); > void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt); > +int intel_gt_init_mmio(struct intel_gt *gt); > int __must_check intel_gt_init_hw(struct intel_gt *gt); > int intel_gt_init(struct intel_gt *gt); > void intel_gt_driver_register(struct intel_gt *gt); > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 67789df42be8..5fd5af4bc855 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -531,9 +531,7 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) > /* Try to make sure MCHBAR is enabled before poking at it */ > intel_setup_mchbar(dev_priv); > > - intel_uc_init_mmio(&dev_priv->gt.uc); > - > - ret = intel_engines_init_mmio(&dev_priv->gt); > + ret = intel_gt_init_mmio(&dev_priv->gt); > if (ret) > goto err_uncore; > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From daniele.ceraolospurio at intel.com Fri Jun 26 14:46:53 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Fri, 26 Jun 2020 07:46:53 -0700 Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio In-Reply-To: <159318233803.13600.604722317964699116@build.alporthouse.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-4-daniele.ceraolospurio@intel.com> <159318233803.13600.604722317964699116@build.alporthouse.com> Message-ID: <f711551d-e5dd-0cbf-8bbf-db27425620b9@intel.com> On 6/26/20 7:38 AM, Chris Wilson wrote: > Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:08) >> All the info we read in intel_device_info_init_mmio are engine-related >> and since we already have an engine_init_mmio function we can just >> perform the operations from there. >> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> >> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> >> Cc: Andi Shyti <andi.shyti at intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++- >> drivers/gpu/drm/i915/i915_drv.c | 4 -- >> drivers/gpu/drm/i915/intel_device_info.c | 66 --------------------- >> drivers/gpu/drm/i915/intel_device_info.h | 2 - >> 4 files changed, 71 insertions(+), 73 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> index be92d1ef9aa9..8497106eb3a6 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt) >> } >> } >> >> +/* >> + * Determine which engines are fused off in our particular hardware. Since the >> + * fuse register is in the blitter powerwell, we need forcewake to be ready at >> + * this point (but later we need to prune the forcewake domains for engines that >> + * are indeed fused off). >> + */ >> +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) >> +{ >> + struct drm_i915_private *i915 = gt->i915; >> + struct intel_device_info *info = mkwrite_device_info(i915); >> + struct intel_uncore *uncore = gt->uncore; >> + unsigned int logical_vdbox = 0; >> + unsigned int i; >> + u32 media_fuse; >> + u16 vdbox_mask; >> + u16 vebox_mask; > > assert_forcewakes_active(uncore, FORCEWAKE_BLITTER) ? > > Since it's called out in the comment, might as well reinforce that with > an assert. We don't expect it to be active, just to be initialized/usable. This comment is there to remind us of the catch-22 issue we have where we need forcewake to be initialized to read the fuses, but we need the fuses values to know which engines are available and therefore which fw domains are there (and that's why we prune the domains later). Daniele > -Chris > From chris at chris-wilson.co.uk Fri Jun 26 14:51:14 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 15:51:14 +0100 Subject: [Intel-gfx] [PATCH 3/7] drm/i915: Move engine-related mmio init to engines_init_mmio In-Reply-To: <f711551d-e5dd-0cbf-8bbf-db27425620b9@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-4-daniele.ceraolospurio@intel.com> <159318233803.13600.604722317964699116@build.alporthouse.com> <f711551d-e5dd-0cbf-8bbf-db27425620b9@intel.com> Message-ID: <159318307440.13600.1953403213555208600@build.alporthouse.com> Quoting Daniele Ceraolo Spurio (2020-06-26 15:46:53) > > > On 6/26/20 7:38 AM, Chris Wilson wrote: > > Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:08) > >> All the info we read in intel_device_info_init_mmio are engine-related > >> and since we already have an engine_init_mmio function we can just > >> perform the operations from there. > >> > >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > >> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> > >> Cc: Andi Shyti <andi.shyti at intel.com> > >> --- > >> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 72 ++++++++++++++++++++++- > >> drivers/gpu/drm/i915/i915_drv.c | 4 -- > >> drivers/gpu/drm/i915/intel_device_info.c | 66 --------------------- > >> drivers/gpu/drm/i915/intel_device_info.h | 2 - > >> 4 files changed, 71 insertions(+), 73 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > >> index be92d1ef9aa9..8497106eb3a6 100644 > >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > >> @@ -450,6 +450,74 @@ void intel_engines_free(struct intel_gt *gt) > >> } > >> } > >> > >> +/* > >> + * Determine which engines are fused off in our particular hardware. Since the > >> + * fuse register is in the blitter powerwell, we need forcewake to be ready at > >> + * this point (but later we need to prune the forcewake domains for engines that > >> + * are indeed fused off). > >> + */ > >> +static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > >> +{ > >> + struct drm_i915_private *i915 = gt->i915; > >> + struct intel_device_info *info = mkwrite_device_info(i915); > >> + struct intel_uncore *uncore = gt->uncore; > >> + unsigned int logical_vdbox = 0; > >> + unsigned int i; > >> + u32 media_fuse; > >> + u16 vdbox_mask; > >> + u16 vebox_mask; > > > > assert_forcewakes_active(uncore, FORCEWAKE_BLITTER) ? > > > > Since it's called out in the comment, might as well reinforce that with > > an assert. > > We don't expect it to be active, just to be initialized/usable. > This comment is there to remind us of the catch-22 issue we have where > we need forcewake to be initialized to read the fuses, but we need the > fuses values to know which engines are available and therefore which fw > domains are there (and that's why we prune the domains later). Gotcha, I assumed 'ready' == 'powered up' How about adding that explanation to the comment :) -Chris From tvrtko.ursulin at linux.intel.com Fri Jun 26 15:00:53 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 26 Jun 2020 16:00:53 +0100 Subject: [Intel-gfx] [PATCH 6/7] drm/i915/sseu: Move sseu detection and dump to intel_sseu In-Reply-To: <20200625234212.22811-7-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-7-daniele.ceraolospurio@intel.com> Message-ID: <841291ae-40d8-c430-dbc8-6b16f7fbc713@linux.intel.com> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: > Keep all the SSEU code in the relevant file. The code has also been > updated to use intel_gt instead of dev_priv. > > Based on an original patch by Sandeep. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt.c | 1 + > drivers/gpu/drm/i915/gt/intel_sseu.c | 587 +++++++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_sseu.h | 8 + > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 584 +--------------------- > drivers/gpu/drm/i915/intel_device_info.h | 2 - > 7 files changed, 600 insertions(+), 586 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index 949114f09b82..de95930f8627 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -47,6 +47,7 @@ void intel_gt_init_hw_early(struct intel_gt *gt, struct i915_ggtt *ggtt) > int intel_gt_init_mmio(struct intel_gt *gt) > { > intel_uc_init_mmio(>->uc); > + intel_sseu_info_init(gt); > > return intel_engines_init_mmio(gt); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c > index d173271c7397..006f9118b319 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > @@ -60,6 +60,548 @@ intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice) > return hweight32(intel_sseu_get_subslices(sseu, slice)); > } > > +static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, > + int subslice) > +{ > + int slice_stride = sseu->max_subslices * sseu->eu_stride; > + > + return slice * slice_stride + subslice * sseu->eu_stride; > +} > + > +static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, > + int subslice) > +{ > + int i, offset = sseu_eu_idx(sseu, slice, subslice); > + u16 eu_mask = 0; > + > + for (i = 0; i < sseu->eu_stride; i++) { > + eu_mask |= ((u16)sseu->eu_mask[offset + i]) << > + (i * BITS_PER_BYTE); > + } > + > + return eu_mask; > +} > + > +static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, > + u16 eu_mask) > +{ > + int i, offset = sseu_eu_idx(sseu, slice, subslice); > + > + for (i = 0; i < sseu->eu_stride; i++) { > + sseu->eu_mask[offset + i] = > + (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; > + } > +} > + > +static u16 compute_eu_total(const struct sseu_dev_info *sseu) > +{ > + u16 i, total = 0; > + > + for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) > + total += hweight8(sseu->eu_mask[i]); > + > + return total; > +} > + > +static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, > + u8 s_en, u32 ss_en, u16 eu_en) > +{ > + int s, ss; > + > + /* ss_en represents entire subslice mask across all slices */ > + GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > > + sizeof(ss_en) * BITS_PER_BYTE); > + > + for (s = 0; s < sseu->max_slices; s++) { > + if ((s_en & BIT(s)) == 0) > + continue; > + > + sseu->slice_mask |= BIT(s); > + > + intel_sseu_set_subslices(sseu, s, ss_en); > + > + for (ss = 0; ss < sseu->max_subslices; ss++) > + if (intel_sseu_has_subslice(sseu, s, ss)) > + sseu_set_eus(sseu, s, ss, eu_en); > + } > + sseu->eu_per_subslice = hweight16(eu_en); > + sseu->eu_total = compute_eu_total(sseu); > +} > + > +static void gen12_sseu_info_init(struct intel_gt *gt) > +{ > + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct intel_uncore *uncore = gt->uncore; > + u8 s_en; > + u32 dss_en; > + u16 eu_en = 0; > + u8 eu_en_fuse; > + int eu; > + > + /* > + * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. > + * Instead of splitting these, provide userspace with an array > + * of DSS to more closely represent the hardware resource. > + */ > + intel_sseu_set_info(sseu, 1, 6, 16); > + > + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > + GEN11_GT_S_ENA_MASK; > + > + dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); > + > + /* one bit per pair of EUs */ > + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > + GEN11_EU_DIS_MASK); > + for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) > + if (eu_en_fuse & BIT(eu)) > + eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); > + > + gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); > + > + /* TGL only supports slice-level power gating */ > + sseu->has_slice_pg = 1; > +} > + > +static void gen11_sseu_info_init(struct intel_gt *gt) > +{ > + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct intel_uncore *uncore = gt->uncore; > + u8 s_en; > + u32 ss_en; > + u8 eu_en; > + > + if (IS_ELKHARTLAKE(gt->i915)) > + intel_sseu_set_info(sseu, 1, 4, 8); > + else > + intel_sseu_set_info(sseu, 1, 8, 8); > + > + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > + GEN11_GT_S_ENA_MASK; > + ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); > + > + eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > + GEN11_EU_DIS_MASK); > + > + gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); > + > + /* ICL has no power gating restrictions. */ > + sseu->has_slice_pg = 1; > + sseu->has_subslice_pg = 1; > + sseu->has_eu_pg = 1; > +} > + > +static void gen10_sseu_info_init(struct intel_gt *gt) > +{ > + struct intel_uncore *uncore = gt->uncore; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > + int s, ss; > + const int eu_mask = 0xff; > + u32 subslice_mask, eu_en; > + > + intel_sseu_set_info(sseu, 6, 4, 8); > + > + sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> > + GEN10_F2_S_ENA_SHIFT; > + > + /* Slice0 */ > + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); > + for (ss = 0; ss < sseu->max_subslices; ss++) > + sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); > + /* Slice1 */ > + sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); > + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); > + sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); > + /* Slice2 */ > + sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); > + sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); > + /* Slice3 */ > + sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); > + eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); > + sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); > + /* Slice4 */ > + sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); > + sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); > + /* Slice5 */ > + sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); > + eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); > + sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); > + > + subslice_mask = (1 << 4) - 1; > + subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> > + GEN10_F2_SS_DIS_SHIFT); > + > + for (s = 0; s < sseu->max_slices; s++) { > + u32 subslice_mask_with_eus = subslice_mask; > + > + for (ss = 0; ss < sseu->max_subslices; ss++) { > + if (sseu_get_eus(sseu, s, ss) == 0) > + subslice_mask_with_eus &= ~BIT(ss); > + } > + > + /* > + * Slice0 can have up to 3 subslices, but there are only 2 in > + * slice1/2. > + */ > + intel_sseu_set_subslices(sseu, s, s == 0 ? > + subslice_mask_with_eus : > + subslice_mask_with_eus & 0x3); > + } > + > + sseu->eu_total = compute_eu_total(sseu); > + > + /* > + * CNL is expected to always have a uniform distribution > + * of EU across subslices with the exception that any one > + * EU in any one subslice may be fused off for die > + * recovery. > + */ > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > + DIV_ROUND_UP(sseu->eu_total, > + intel_sseu_subslice_total(sseu)) : > + 0; > + > + /* No restrictions on Power Gating */ > + sseu->has_slice_pg = 1; > + sseu->has_subslice_pg = 1; > + sseu->has_eu_pg = 1; > +} > + > +static void cherryview_sseu_info_init(struct intel_gt *gt) > +{ > + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + u32 fuse; > + u8 subslice_mask = 0; > + > + fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT); > + > + sseu->slice_mask = BIT(0); > + intel_sseu_set_info(sseu, 1, 2, 8); > + > + if (!(fuse & CHV_FGT_DISABLE_SS0)) { > + u8 disabled_mask = > + ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> > + CHV_FGT_EU_DIS_SS0_R0_SHIFT) | > + (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> > + CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); > + > + subslice_mask |= BIT(0); > + sseu_set_eus(sseu, 0, 0, ~disabled_mask); > + } > + > + if (!(fuse & CHV_FGT_DISABLE_SS1)) { > + u8 disabled_mask = > + ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> > + CHV_FGT_EU_DIS_SS1_R0_SHIFT) | > + (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> > + CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); > + > + subslice_mask |= BIT(1); > + sseu_set_eus(sseu, 0, 1, ~disabled_mask); > + } > + > + intel_sseu_set_subslices(sseu, 0, subslice_mask); > + > + sseu->eu_total = compute_eu_total(sseu); > + > + /* > + * CHV expected to always have a uniform distribution of EU > + * across subslices. > + */ > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > + sseu->eu_total / > + intel_sseu_subslice_total(sseu) : > + 0; > + /* > + * CHV supports subslice power gating on devices with more than > + * one subslice, and supports EU power gating on devices with > + * more than one EU pair per subslice. > + */ > + sseu->has_slice_pg = 0; > + sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; > + sseu->has_eu_pg = (sseu->eu_per_subslice > 2); > +} > + > +static void gen9_sseu_info_init(struct intel_gt *gt) > +{ > + struct drm_i915_private *i915 = gt->i915; > + struct intel_device_info *info = mkwrite_device_info(i915); > + struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; > + struct intel_uncore *uncore = gt->uncore; > + int s, ss; > + u32 fuse2, eu_disable, subslice_mask; > + const u8 eu_mask = 0xff; > + > + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; > + > + /* BXT has a single slice and at most 3 subslices. */ > + intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3, > + IS_GEN9_LP(i915) ? 3 : 4, 8); > + > + /* > + * The subslice disable field is global, i.e. it applies > + * to each of the enabled slices. > + */ > + subslice_mask = (1 << sseu->max_subslices) - 1; > + subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> > + GEN9_F2_SS_DIS_SHIFT); > + > + /* > + * Iterate through enabled slices and subslices to > + * count the total enabled EU. > + */ > + for (s = 0; s < sseu->max_slices; s++) { > + if (!(sseu->slice_mask & BIT(s))) > + /* skip disabled slice */ > + continue; > + > + intel_sseu_set_subslices(sseu, s, subslice_mask); > + > + eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); > + for (ss = 0; ss < sseu->max_subslices; ss++) { > + int eu_per_ss; > + u8 eu_disabled_mask; > + > + if (!intel_sseu_has_subslice(sseu, s, ss)) > + /* skip disabled subslice */ > + continue; > + > + eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; > + > + sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > + > + eu_per_ss = sseu->max_eus_per_subslice - > + hweight8(eu_disabled_mask); > + > + /* > + * Record which subslice(s) has(have) 7 EUs. we > + * can tune the hash used to spread work among > + * subslices if they are unbalanced. > + */ > + if (eu_per_ss == 7) > + sseu->subslice_7eu[s] |= BIT(ss); > + } > + } > + > + sseu->eu_total = compute_eu_total(sseu); > + > + /* > + * SKL is expected to always have a uniform distribution > + * of EU across subslices with the exception that any one > + * EU in any one subslice may be fused off for die > + * recovery. BXT is expected to be perfectly uniform in EU > + * distribution. > + */ > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > + DIV_ROUND_UP(sseu->eu_total, > + intel_sseu_subslice_total(sseu)) : > + 0; > + /* > + * SKL+ supports slice power gating on devices with more than > + * one slice, and supports EU power gating on devices with > + * more than one EU pair per subslice. BXT+ supports subslice > + * power gating on devices with more than one subslice, and > + * supports EU power gating on devices with more than one EU > + * pair per subslice. > + */ > + sseu->has_slice_pg = > + !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; > + sseu->has_subslice_pg = > + IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1; > + sseu->has_eu_pg = sseu->eu_per_subslice > 2; > + > + if (IS_GEN9_LP(i915)) { > +#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) > + info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; > + > + sseu->min_eu_in_pool = 0; > + if (info->has_pooled_eu) { > + if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) > + sseu->min_eu_in_pool = 3; > + else if (IS_SS_DISABLED(1)) > + sseu->min_eu_in_pool = 6; > + else > + sseu->min_eu_in_pool = 9; > + } > +#undef IS_SS_DISABLED > + } > +} > + > +static void bdw_sseu_info_init(struct intel_gt *gt) > +{ > + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct intel_uncore *uncore = gt->uncore; > + int s, ss; > + u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ > + u32 eu_disable0, eu_disable1, eu_disable2; > + > + fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > + sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; > + intel_sseu_set_info(sseu, 3, 3, 8); > + > + /* > + * The subslice disable field is global, i.e. it applies > + * to each of the enabled slices. > + */ > + subslice_mask = GENMASK(sseu->max_subslices - 1, 0); > + subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> > + GEN8_F2_SS_DIS_SHIFT); > + eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); > + eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); > + eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); > + eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; > + eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | > + ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << > + (32 - GEN8_EU_DIS0_S1_SHIFT)); > + eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | > + ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << > + (32 - GEN8_EU_DIS1_S2_SHIFT)); > + > + /* > + * Iterate through enabled slices and subslices to > + * count the total enabled EU. > + */ > + for (s = 0; s < sseu->max_slices; s++) { > + if (!(sseu->slice_mask & BIT(s))) > + /* skip disabled slice */ > + continue; > + > + intel_sseu_set_subslices(sseu, s, subslice_mask); > + > + for (ss = 0; ss < sseu->max_subslices; ss++) { > + u8 eu_disabled_mask; > + u32 n_disabled; > + > + if (!intel_sseu_has_subslice(sseu, s, ss)) > + /* skip disabled subslice */ > + continue; > + > + eu_disabled_mask = > + eu_disable[s] >> (ss * sseu->max_eus_per_subslice); > + > + sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > + > + n_disabled = hweight8(eu_disabled_mask); > + > + /* > + * Record which subslices have 7 EUs. > + */ > + if (sseu->max_eus_per_subslice - n_disabled == 7) > + sseu->subslice_7eu[s] |= 1 << ss; > + } > + } > + > + sseu->eu_total = compute_eu_total(sseu); > + > + /* > + * BDW is expected to always have a uniform distribution of EU across > + * subslices with the exception that any one EU in any one subslice may > + * be fused off for die recovery. > + */ > + sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > + DIV_ROUND_UP(sseu->eu_total, > + intel_sseu_subslice_total(sseu)) : > + 0; > + > + /* > + * BDW supports slice power gating on devices with more than > + * one slice. > + */ > + sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; > + sseu->has_subslice_pg = 0; > + sseu->has_eu_pg = 0; > +} > + > +static void hsw_sseu_info_init(struct intel_gt *gt) > +{ > + struct drm_i915_private *i915 = gt->i915; > + struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + u32 fuse1; > + u8 subslice_mask = 0; > + int s, ss; > + > + /* > + * There isn't a register to tell us how many slices/subslices. We > + * work off the PCI-ids here. > + */ > + switch (INTEL_INFO(i915)->gt) { > + default: > + MISSING_CASE(INTEL_INFO(i915)->gt); > + /* fall through */ > + case 1: > + sseu->slice_mask = BIT(0); > + subslice_mask = BIT(0); > + break; > + case 2: > + sseu->slice_mask = BIT(0); > + subslice_mask = BIT(0) | BIT(1); > + break; > + case 3: > + sseu->slice_mask = BIT(0) | BIT(1); > + subslice_mask = BIT(0) | BIT(1); > + break; > + } > + > + fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); > + switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { > + default: > + MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> > + HSW_F1_EU_DIS_SHIFT); > + /* fall through */ > + case HSW_F1_EU_DIS_10EUS: > + sseu->eu_per_subslice = 10; > + break; > + case HSW_F1_EU_DIS_8EUS: > + sseu->eu_per_subslice = 8; > + break; > + case HSW_F1_EU_DIS_6EUS: > + sseu->eu_per_subslice = 6; > + break; > + } > + > + intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), > + hweight8(subslice_mask), > + sseu->eu_per_subslice); > + > + for (s = 0; s < sseu->max_slices; s++) { > + intel_sseu_set_subslices(sseu, s, subslice_mask); > + > + for (ss = 0; ss < sseu->max_subslices; ss++) { > + sseu_set_eus(sseu, s, ss, > + (1UL << sseu->eu_per_subslice) - 1); > + } > + } > + > + sseu->eu_total = compute_eu_total(sseu); > + > + /* No powergating for you. */ > + sseu->has_slice_pg = 0; > + sseu->has_subslice_pg = 0; > + sseu->has_eu_pg = 0; > +} > + > +void intel_sseu_info_init(struct intel_gt *gt) > +{ > + struct drm_i915_private *i915 = gt->i915; > + > + if (IS_HASWELL(i915)) > + hsw_sseu_info_init(gt); > + else if (IS_CHERRYVIEW(i915)) > + cherryview_sseu_info_init(gt); > + else if (IS_BROADWELL(i915)) > + bdw_sseu_info_init(gt); > + else if (IS_GEN(i915, 9)) > + gen9_sseu_info_init(gt); > + else if (IS_GEN(i915, 10)) > + gen10_sseu_info_init(gt); > + else if (IS_GEN(i915, 11)) > + gen11_sseu_info_init(gt); > + else if (INTEL_GEN(i915) >= 12) > + gen12_sseu_info_init(gt); > +} > + > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > const struct intel_sseu *req_sseu) > { > @@ -173,3 +715,48 @@ u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > > return rpcs; > } > + > +void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) > +{ > + int s; > + > + drm_printf(p, "slice total: %u, mask=%04x\n", > + hweight8(sseu->slice_mask), sseu->slice_mask); > + drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); > + for (s = 0; s < sseu->max_slices; s++) { > + drm_printf(p, "slice%d: %u subslices, mask=%08x\n", > + s, intel_sseu_subslices_per_slice(sseu, s), > + intel_sseu_get_subslices(sseu, s)); > + } > + drm_printf(p, "EU total: %u\n", sseu->eu_total); > + drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); > + drm_printf(p, "has slice power gating: %s\n", > + yesno(sseu->has_slice_pg)); > + drm_printf(p, "has subslice power gating: %s\n", > + yesno(sseu->has_subslice_pg)); > + drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); > +} > + > +void intel_sseu_print_topology(const struct sseu_dev_info *sseu, > + struct drm_printer *p) > +{ > + int s, ss; > + > + if (sseu->max_slices == 0) { > + drm_printf(p, "Unavailable\n"); > + return; > + } > + > + for (s = 0; s < sseu->max_slices; s++) { > + drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", > + s, intel_sseu_subslices_per_slice(sseu, s), > + intel_sseu_get_subslices(sseu, s)); > + > + for (ss = 0; ss < sseu->max_subslices; ss++) { > + u16 enabled_eus = sseu_get_eus(sseu, s, ss); > + > + drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", > + ss, hweight16(enabled_eus), enabled_eus); > + } > + } > +} > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h > index d1d225204f09..f9c007f001e7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h > @@ -13,6 +13,8 @@ > #include "i915_gem.h" > > struct drm_i915_private; > +struct intel_gt; > +struct drm_printer; > > #define GEN_MAX_SLICES (6) /* CNL upper bound */ > #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ > @@ -94,7 +96,13 @@ u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice); > void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, > u32 ss_mask); > > +void intel_sseu_info_init(struct intel_gt *gt); > + > u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > const struct intel_sseu *req_sseu); > > +void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); > +void intel_sseu_print_topology(const struct sseu_dev_info *sseu, > + struct drm_printer *p); > + > #endif /* __INTEL_SSEU_H__ */ > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index cad1620d2a7e..c893a82c2d99 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused) > struct drm_i915_private *dev_priv = node_to_i915(m->private); > struct drm_printer p = drm_seq_file_printer(m); > > - intel_device_info_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); > + intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); > > return 0; > } > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 9cb9aa39c33d..99b4a0261b13 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -626,7 +626,7 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m, > > intel_device_info_print_static(&error->device_info, &p); > intel_device_info_print_runtime(&error->runtime_info, &p); > - intel_device_info_print_topology(&error->runtime_info.sseu, &p); > + intel_sseu_print_topology(&error->runtime_info.sseu, &p); > intel_gt_info_print(&error->gt->info, &p); > intel_driver_caps_print(&error->driver_caps, &p); > } > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index a362a66fce11..d8daf224cbd3 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -29,6 +29,7 @@ > #include "display/intel_de.h" > #include "intel_device_info.h" > #include "i915_drv.h" > +#include "gt/intel_sseu.h" > > #define PLATFORM_NAME(x) [INTEL_##x] = #x > static const char * const platform_names[] = { > @@ -111,581 +112,16 @@ void intel_device_info_print_static(const struct intel_device_info *info, > #undef PRINT_FLAG > } > > -static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) > -{ > - int s; > - > - drm_printf(p, "slice total: %u, mask=%04x\n", > - hweight8(sseu->slice_mask), sseu->slice_mask); > - drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu)); > - for (s = 0; s < sseu->max_slices; s++) { > - drm_printf(p, "slice%d: %u subslices, mask=%08x\n", > - s, intel_sseu_subslices_per_slice(sseu, s), > - intel_sseu_get_subslices(sseu, s)); > - } > - drm_printf(p, "EU total: %u\n", sseu->eu_total); > - drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); > - drm_printf(p, "has slice power gating: %s\n", > - yesno(sseu->has_slice_pg)); > - drm_printf(p, "has subslice power gating: %s\n", > - yesno(sseu->has_subslice_pg)); > - drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); > -} > - > void intel_device_info_print_runtime(const struct intel_runtime_info *info, > struct drm_printer *p) > { > - sseu_dump(&info->sseu, p); > + intel_sseu_dump(&info->sseu, p); > > drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); > drm_printf(p, "CS timestamp frequency: %u Hz\n", > info->cs_timestamp_frequency_hz); > } > > -static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice, > - int subslice) > -{ > - int slice_stride = sseu->max_subslices * sseu->eu_stride; > - > - return slice * slice_stride + subslice * sseu->eu_stride; > -} > - > -static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, > - int subslice) > -{ > - int i, offset = sseu_eu_idx(sseu, slice, subslice); > - u16 eu_mask = 0; > - > - for (i = 0; i < sseu->eu_stride; i++) { > - eu_mask |= ((u16)sseu->eu_mask[offset + i]) << > - (i * BITS_PER_BYTE); > - } > - > - return eu_mask; > -} > - > -static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, > - u16 eu_mask) > -{ > - int i, offset = sseu_eu_idx(sseu, slice, subslice); > - > - for (i = 0; i < sseu->eu_stride; i++) { > - sseu->eu_mask[offset + i] = > - (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; > - } > -} > - > -void intel_device_info_print_topology(const struct sseu_dev_info *sseu, > - struct drm_printer *p) > -{ > - int s, ss; > - > - if (sseu->max_slices == 0) { > - drm_printf(p, "Unavailable\n"); > - return; > - } > - > - for (s = 0; s < sseu->max_slices; s++) { > - drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", > - s, intel_sseu_subslices_per_slice(sseu, s), > - intel_sseu_get_subslices(sseu, s)); > - > - for (ss = 0; ss < sseu->max_subslices; ss++) { > - u16 enabled_eus = sseu_get_eus(sseu, s, ss); > - > - drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", > - ss, hweight16(enabled_eus), enabled_eus); > - } > - } > -} > - > -static u16 compute_eu_total(const struct sseu_dev_info *sseu) > -{ > - u16 i, total = 0; > - > - for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) > - total += hweight8(sseu->eu_mask[i]); > - > - return total; > -} > - > -static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, > - u8 s_en, u32 ss_en, u16 eu_en) > -{ > - int s, ss; > - > - /* ss_en represents entire subslice mask across all slices */ > - GEM_BUG_ON(sseu->max_slices * sseu->max_subslices > > - sizeof(ss_en) * BITS_PER_BYTE); > - > - for (s = 0; s < sseu->max_slices; s++) { > - if ((s_en & BIT(s)) == 0) > - continue; > - > - sseu->slice_mask |= BIT(s); > - > - intel_sseu_set_subslices(sseu, s, ss_en); > - > - for (ss = 0; ss < sseu->max_subslices; ss++) > - if (intel_sseu_has_subslice(sseu, s, ss)) > - sseu_set_eus(sseu, s, ss, eu_en); > - } > - sseu->eu_per_subslice = hweight16(eu_en); > - sseu->eu_total = compute_eu_total(sseu); > -} > - > -static void gen12_sseu_info_init(struct drm_i915_private *dev_priv) > -{ > - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - struct intel_uncore *uncore = &dev_priv->uncore; > - u8 s_en; > - u32 dss_en; > - u16 eu_en = 0; > - u8 eu_en_fuse; > - int eu; > - > - /* > - * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. > - * Instead of splitting these, provide userspace with an array > - * of DSS to more closely represent the hardware resource. > - */ > - intel_sseu_set_info(sseu, 1, 6, 16); > - > - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > - GEN11_GT_S_ENA_MASK; > - > - dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); > - > - /* one bit per pair of EUs */ > - eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > - GEN11_EU_DIS_MASK); > - for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) > - if (eu_en_fuse & BIT(eu)) > - eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); > - > - gen11_compute_sseu_info(sseu, s_en, dss_en, eu_en); > - > - /* TGL only supports slice-level power gating */ > - sseu->has_slice_pg = 1; > -} > - > -static void gen11_sseu_info_init(struct drm_i915_private *dev_priv) > -{ > - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - struct intel_uncore *uncore = &dev_priv->uncore; > - u8 s_en; > - u32 ss_en; > - u8 eu_en; > - > - if (IS_ELKHARTLAKE(dev_priv)) > - intel_sseu_set_info(sseu, 1, 4, 8); > - else > - intel_sseu_set_info(sseu, 1, 8, 8); > - > - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > - GEN11_GT_S_ENA_MASK; > - ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); > - > - eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > - GEN11_EU_DIS_MASK); > - > - gen11_compute_sseu_info(sseu, s_en, ss_en, eu_en); > - > - /* ICL has no power gating restrictions. */ > - sseu->has_slice_pg = 1; > - sseu->has_subslice_pg = 1; > - sseu->has_eu_pg = 1; > -} > - > -static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) > -{ > - struct intel_uncore *uncore = &dev_priv->uncore; > - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > - int s, ss; > - const int eu_mask = 0xff; > - u32 subslice_mask, eu_en; > - > - intel_sseu_set_info(sseu, 6, 4, 8); > - > - sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> > - GEN10_F2_S_ENA_SHIFT; > - > - /* Slice0 */ > - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE0); > - for (ss = 0; ss < sseu->max_subslices; ss++) > - sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); > - /* Slice1 */ > - sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); > - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE1); > - sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); > - /* Slice2 */ > - sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); > - sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); > - /* Slice3 */ > - sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); > - eu_en = ~intel_uncore_read(uncore, GEN8_EU_DISABLE2); > - sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); > - /* Slice4 */ > - sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); > - sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); > - /* Slice5 */ > - sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); > - eu_en = ~intel_uncore_read(uncore, GEN10_EU_DISABLE3); > - sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); > - > - subslice_mask = (1 << 4) - 1; > - subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> > - GEN10_F2_SS_DIS_SHIFT); > - > - for (s = 0; s < sseu->max_slices; s++) { > - u32 subslice_mask_with_eus = subslice_mask; > - > - for (ss = 0; ss < sseu->max_subslices; ss++) { > - if (sseu_get_eus(sseu, s, ss) == 0) > - subslice_mask_with_eus &= ~BIT(ss); > - } > - > - /* > - * Slice0 can have up to 3 subslices, but there are only 2 in > - * slice1/2. > - */ > - intel_sseu_set_subslices(sseu, s, s == 0 ? > - subslice_mask_with_eus : > - subslice_mask_with_eus & 0x3); > - } > - > - sseu->eu_total = compute_eu_total(sseu); > - > - /* > - * CNL is expected to always have a uniform distribution > - * of EU across subslices with the exception that any one > - * EU in any one subslice may be fused off for die > - * recovery. > - */ > - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > - DIV_ROUND_UP(sseu->eu_total, > - intel_sseu_subslice_total(sseu)) : > - 0; > - > - /* No restrictions on Power Gating */ > - sseu->has_slice_pg = 1; > - sseu->has_subslice_pg = 1; > - sseu->has_eu_pg = 1; > -} > - > -static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) > -{ > - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - u32 fuse; > - u8 subslice_mask = 0; > - > - fuse = intel_uncore_read(&dev_priv->uncore, CHV_FUSE_GT); > - > - sseu->slice_mask = BIT(0); > - intel_sseu_set_info(sseu, 1, 2, 8); > - > - if (!(fuse & CHV_FGT_DISABLE_SS0)) { > - u8 disabled_mask = > - ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> > - CHV_FGT_EU_DIS_SS0_R0_SHIFT) | > - (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> > - CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); > - > - subslice_mask |= BIT(0); > - sseu_set_eus(sseu, 0, 0, ~disabled_mask); > - } > - > - if (!(fuse & CHV_FGT_DISABLE_SS1)) { > - u8 disabled_mask = > - ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> > - CHV_FGT_EU_DIS_SS1_R0_SHIFT) | > - (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> > - CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); > - > - subslice_mask |= BIT(1); > - sseu_set_eus(sseu, 0, 1, ~disabled_mask); > - } > - > - intel_sseu_set_subslices(sseu, 0, subslice_mask); > - > - sseu->eu_total = compute_eu_total(sseu); > - > - /* > - * CHV expected to always have a uniform distribution of EU > - * across subslices. > - */ > - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > - sseu->eu_total / > - intel_sseu_subslice_total(sseu) : > - 0; > - /* > - * CHV supports subslice power gating on devices with more than > - * one subslice, and supports EU power gating on devices with > - * more than one EU pair per subslice. > - */ > - sseu->has_slice_pg = 0; > - sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; > - sseu->has_eu_pg = (sseu->eu_per_subslice > 2); > -} > - > -static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > -{ > - struct intel_device_info *info = mkwrite_device_info(dev_priv); > - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - struct intel_uncore *uncore = &dev_priv->uncore; > - int s, ss; > - u32 fuse2, eu_disable, subslice_mask; > - const u8 eu_mask = 0xff; > - > - fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; > - > - /* BXT has a single slice and at most 3 subslices. */ > - intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3, > - IS_GEN9_LP(dev_priv) ? 3 : 4, 8); > - > - /* > - * The subslice disable field is global, i.e. it applies > - * to each of the enabled slices. > - */ > - subslice_mask = (1 << sseu->max_subslices) - 1; > - subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> > - GEN9_F2_SS_DIS_SHIFT); > - > - /* > - * Iterate through enabled slices and subslices to > - * count the total enabled EU. > - */ > - for (s = 0; s < sseu->max_slices; s++) { > - if (!(sseu->slice_mask & BIT(s))) > - /* skip disabled slice */ > - continue; > - > - intel_sseu_set_subslices(sseu, s, subslice_mask); > - > - eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); > - for (ss = 0; ss < sseu->max_subslices; ss++) { > - int eu_per_ss; > - u8 eu_disabled_mask; > - > - if (!intel_sseu_has_subslice(sseu, s, ss)) > - /* skip disabled subslice */ > - continue; > - > - eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; > - > - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > - > - eu_per_ss = sseu->max_eus_per_subslice - > - hweight8(eu_disabled_mask); > - > - /* > - * Record which subslice(s) has(have) 7 EUs. we > - * can tune the hash used to spread work among > - * subslices if they are unbalanced. > - */ > - if (eu_per_ss == 7) > - sseu->subslice_7eu[s] |= BIT(ss); > - } > - } > - > - sseu->eu_total = compute_eu_total(sseu); > - > - /* > - * SKL is expected to always have a uniform distribution > - * of EU across subslices with the exception that any one > - * EU in any one subslice may be fused off for die > - * recovery. BXT is expected to be perfectly uniform in EU > - * distribution. > - */ > - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > - DIV_ROUND_UP(sseu->eu_total, > - intel_sseu_subslice_total(sseu)) : > - 0; > - /* > - * SKL+ supports slice power gating on devices with more than > - * one slice, and supports EU power gating on devices with > - * more than one EU pair per subslice. BXT+ supports subslice > - * power gating on devices with more than one subslice, and > - * supports EU power gating on devices with more than one EU > - * pair per subslice. > - */ > - sseu->has_slice_pg = > - !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; > - sseu->has_subslice_pg = > - IS_GEN9_LP(dev_priv) && intel_sseu_subslice_total(sseu) > 1; > - sseu->has_eu_pg = sseu->eu_per_subslice > 2; > - > - if (IS_GEN9_LP(dev_priv)) { > -#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) > - info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; > - > - sseu->min_eu_in_pool = 0; > - if (info->has_pooled_eu) { > - if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) > - sseu->min_eu_in_pool = 3; > - else if (IS_SS_DISABLED(1)) > - sseu->min_eu_in_pool = 6; > - else > - sseu->min_eu_in_pool = 9; > - } > -#undef IS_SS_DISABLED > - } > -} > - > -static void bdw_sseu_info_init(struct drm_i915_private *dev_priv) > -{ > - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - struct intel_uncore *uncore = &dev_priv->uncore; > - int s, ss; > - u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ > - u32 eu_disable0, eu_disable1, eu_disable2; > - > - fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; > - intel_sseu_set_info(sseu, 3, 3, 8); > - > - /* > - * The subslice disable field is global, i.e. it applies > - * to each of the enabled slices. > - */ > - subslice_mask = GENMASK(sseu->max_subslices - 1, 0); > - subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> > - GEN8_F2_SS_DIS_SHIFT); > - eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); > - eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); > - eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); > - eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; > - eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | > - ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << > - (32 - GEN8_EU_DIS0_S1_SHIFT)); > - eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | > - ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << > - (32 - GEN8_EU_DIS1_S2_SHIFT)); > - > - /* > - * Iterate through enabled slices and subslices to > - * count the total enabled EU. > - */ > - for (s = 0; s < sseu->max_slices; s++) { > - if (!(sseu->slice_mask & BIT(s))) > - /* skip disabled slice */ > - continue; > - > - intel_sseu_set_subslices(sseu, s, subslice_mask); > - > - for (ss = 0; ss < sseu->max_subslices; ss++) { > - u8 eu_disabled_mask; > - u32 n_disabled; > - > - if (!intel_sseu_has_subslice(sseu, s, ss)) > - /* skip disabled subslice */ > - continue; > - > - eu_disabled_mask = > - eu_disable[s] >> (ss * sseu->max_eus_per_subslice); > - > - sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); > - > - n_disabled = hweight8(eu_disabled_mask); > - > - /* > - * Record which subslices have 7 EUs. > - */ > - if (sseu->max_eus_per_subslice - n_disabled == 7) > - sseu->subslice_7eu[s] |= 1 << ss; > - } > - } > - > - sseu->eu_total = compute_eu_total(sseu); > - > - /* > - * BDW is expected to always have a uniform distribution of EU across > - * subslices with the exception that any one EU in any one subslice may > - * be fused off for die recovery. > - */ > - sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? > - DIV_ROUND_UP(sseu->eu_total, > - intel_sseu_subslice_total(sseu)) : > - 0; > - > - /* > - * BDW supports slice power gating on devices with more than > - * one slice. > - */ > - sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; > - sseu->has_subslice_pg = 0; > - sseu->has_eu_pg = 0; > -} > - > -static void hsw_sseu_info_init(struct drm_i915_private *dev_priv) > -{ > - struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > - u32 fuse1; > - u8 subslice_mask = 0; > - int s, ss; > - > - /* > - * There isn't a register to tell us how many slices/subslices. We > - * work off the PCI-ids here. > - */ > - switch (INTEL_INFO(dev_priv)->gt) { > - default: > - MISSING_CASE(INTEL_INFO(dev_priv)->gt); > - /* fall through */ > - case 1: > - sseu->slice_mask = BIT(0); > - subslice_mask = BIT(0); > - break; > - case 2: > - sseu->slice_mask = BIT(0); > - subslice_mask = BIT(0) | BIT(1); > - break; > - case 3: > - sseu->slice_mask = BIT(0) | BIT(1); > - subslice_mask = BIT(0) | BIT(1); > - break; > - } > - > - fuse1 = intel_uncore_read(&dev_priv->uncore, HSW_PAVP_FUSE1); > - switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { > - default: > - MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> > - HSW_F1_EU_DIS_SHIFT); > - /* fall through */ > - case HSW_F1_EU_DIS_10EUS: > - sseu->eu_per_subslice = 10; > - break; > - case HSW_F1_EU_DIS_8EUS: > - sseu->eu_per_subslice = 8; > - break; > - case HSW_F1_EU_DIS_6EUS: > - sseu->eu_per_subslice = 6; > - break; > - } > - > - intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), > - hweight8(subslice_mask), > - sseu->eu_per_subslice); > - > - for (s = 0; s < sseu->max_slices; s++) { > - intel_sseu_set_subslices(sseu, s, subslice_mask); > - > - for (ss = 0; ss < sseu->max_subslices; ss++) { > - sseu_set_eus(sseu, s, ss, > - (1UL << sseu->eu_per_subslice) - 1); > - } > - } > - > - sseu->eu_total = compute_eu_total(sseu); > - > - /* No powergating for you. */ > - sseu->has_slice_pg = 0; > - sseu->has_subslice_pg = 0; > - sseu->has_eu_pg = 0; > -} > - > static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) > { > u32 ts_override = intel_uncore_read(&dev_priv->uncore, > @@ -1042,22 +478,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > info->display.has_dsc = 0; > } > > - /* Initialize slice/subslice/EU info */ > - if (IS_HASWELL(dev_priv)) > - hsw_sseu_info_init(dev_priv); > - else if (IS_CHERRYVIEW(dev_priv)) > - cherryview_sseu_info_init(dev_priv); > - else if (IS_BROADWELL(dev_priv)) > - bdw_sseu_info_init(dev_priv); > - else if (IS_GEN(dev_priv, 9)) > - gen9_sseu_info_init(dev_priv); > - else if (IS_GEN(dev_priv, 10)) > - gen10_sseu_info_init(dev_priv); > - else if (IS_GEN(dev_priv, 11)) > - gen11_sseu_info_init(dev_priv); > - else if (INTEL_GEN(dev_priv) >= 12) > - gen12_sseu_info_init(dev_priv); > - > if (IS_GEN(dev_priv, 6) && intel_vtd_active()) { > drm_info(&dev_priv->drm, > "Disabling ppGTT for VT-d support\n"); > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index f03ed95af190..ce2ccee9b49b 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -242,8 +242,6 @@ void intel_device_info_print_static(const struct intel_device_info *info, > struct drm_printer *p); > void intel_device_info_print_runtime(const struct intel_runtime_info *info, > struct drm_printer *p); > -void intel_device_info_print_topology(const struct sseu_dev_info *sseu, > - struct drm_printer *p); > > void intel_driver_caps_print(const struct intel_driver_caps *caps, > struct drm_printer *p); > I tried to check side by side as much as I could. Occasionaly cut&paste of wonky formatting strangely re-assured me move was good. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From patchwork at emeril.freedesktop.org Fri Jun 26 15:05:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 15:05:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_Implement_new_combo_phy_initialization_step_?= =?utf-8?b?KHJldjIp?= In-Reply-To: <20200625195252.39312-1-jose.souza@intel.com> References: <20200625195252.39312-1-jose.souza@intel.com> Message-ID: <159318395274.22986.6751058523418712899@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Implement new combo phy initialization step (rev2) URL : https://patchwork.freedesktop.org/series/78796/ State : success == Summary == CI Bug Log - changes from CI_DRM_8667 -> Patchwork_18027 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/index.html Known issues ------------ Here are the changes found in Patchwork_18027 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1242]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html * igt at vgem_basic@dmabuf-fence: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-y/igt at vgem_basic@dmabuf-fence.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-tgl-y/igt at vgem_basic@dmabuf-fence.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-tgl-y/igt at prime_self_import@basic-with_two_bos.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-tgl-y/igt at prime_self_import@basic-with_two_bos.html #### Warnings #### * igt at i915_module_load@reload: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at i915_module_load@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-kbl-x1275/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#1982] / [i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8667/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 39) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8667 -> Patchwork_18027 CI-20190529: 20190529 CI_DRM_8667: 57a1fc457c260002189382a406e920465d540d53 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18027: faec0ee3d268bb686fac06dd03db850f6bb770fe @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == faec0ee3d268 drm/i915/display: Implement new combo phy initialization step == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18027/index.html From patchwork at emeril.freedesktop.org Fri Jun 26 15:06:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Fri, 26 Jun 2020 15:06:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_implement_Wa=5F14011508470=3Bgen12?= In-Reply-To: <20200624215723.2316-1-matthew.s.atwood@intel.com> References: <20200624215723.2316-1-matthew.s.atwood@intel.com> Message-ID: <159318399233.22983.8313009094719100447@emeril.freedesktop.org> == Series Details == Series: drm/i915: implement Wa_14011508470;gen12 URL : https://patchwork.freedesktop.org/series/78799/ State : success == Summary == CI Bug Log - changes from CI_DRM_8665_full -> Patchwork_18020_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18020_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [PASS][1] -> [FAIL][2] ([i915#1930]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk8/igt at gem_exec_reloc@basic-concurrent0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb8/igt at i915_module_load@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_selftest@live at active: - shard-tglb: [PASS][5] -> [DMESG-FAIL][6] ([i915#666]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb7/igt at i915_selftest@live at active.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-tglb5/igt at i915_selftest@live at active.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk9/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_concurrent@pipe-a: - shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb7/igt at kms_concurrent@pipe-a.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-iclb7/igt at kms_concurrent@pipe-a.html * igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen: - shard-kbl: [PASS][11] -> [DMESG-FAIL][12] ([i915#54] / [i915#95]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-256x85-onscreen.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +5 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl2/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +12 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl1/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl9/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled: - shard-kbl: [PASS][17] -> [DMESG-FAIL][18] ([fdo#108145] / [i915#54] / [i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl2/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-kbl4/igt at kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html * igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk2/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-glk7/igt at kms_flip@2x-flip-vs-expired-vblank-interruptible at bc-hdmi-a1-hdmi-a2.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_flip@flip-vs-suspend at c-hdmi-a1: - shard-hsw: [PASS][23] -> [INCOMPLETE][24] ([i915#2055]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-hsw6/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-hsw4/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html * igt at kms_flip_tiling@flip-changes-tiling: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#699]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl1/igt at kms_flip_tiling@flip-changes-tiling.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl2/igt at kms_flip_tiling@flip-changes-tiling.html - shard-apl: [PASS][27] -> [DMESG-FAIL][28] ([i915#1635] / [i915#95]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl3/igt at kms_flip_tiling@flip-changes-tiling.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-apl4/igt at kms_flip_tiling@flip-changes-tiling.html - shard-kbl: [PASS][29] -> [DMESG-FAIL][30] ([i915#95]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl1/igt at kms_flip_tiling@flip-changes-tiling.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-kbl1/igt at kms_flip_tiling@flip-changes-tiling.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [PASS][31] -> [FAIL][32] ([i915#1188]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl1/igt at kms_hdr@bpc-switch-dpms.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl2/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane@plane-position-hole-dpms-pipe-a-planes: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#93] / [i915#95]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl1/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-kbl1/igt at kms_plane@plane-position-hole-dpms-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][35] -> [FAIL][36] ([fdo#108145] / [i915#265]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_cpu.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-iclb8/igt at kms_psr@psr2_sprite_mmap_cpu.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-b: - shard-tglb: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb8/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-tglb1/igt at kms_universal_plane@universal-plane-gen9-features-pipe-b.html * igt at perf@low-oa-exponent-permissions: - shard-apl: [PASS][41] -> [DMESG-WARN][42] ([i915#1635] / [i915#95]) +18 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl3/igt at perf@low-oa-exponent-permissions.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-apl1/igt at perf@low-oa-exponent-permissions.html #### Possible fixes #### * igt at gem_ctx_isolation@preservation-s3 at rcs0: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-kbl3/igt at gem_ctx_isolation@preservation-s3 at rcs0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at rcs0.html * igt at gem_exec_whisper@basic-fds: - shard-glk: [DMESG-WARN][45] ([i915#118] / [i915#95]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-glk3/igt at gem_exec_whisper@basic-fds.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-glk9/igt at gem_exec_whisper@basic-fds.html * igt at kms_color@pipe-a-ctm-0-5: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +5 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl1/igt at kms_color@pipe-a-ctm-0-5.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl9/igt at kms_color@pipe-a-ctm-0-5.html * igt at kms_invalid_dotclock: - shard-snb: [TIMEOUT][49] ([i915#1958]) -> [PASS][50] +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-snb5/igt at kms_invalid_dotclock.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-snb2/igt at kms_invalid_dotclock.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][51] ([fdo#108145] / [i915#265]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl4/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +2 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-iclb8/igt at kms_psr@psr2_cursor_blt.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-iclb2/igt at kms_psr@psr2_cursor_blt.html * igt at kms_setmode@basic: - shard-apl: [FAIL][55] ([i915#31]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl6/igt at kms_setmode@basic.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-apl8/igt at kms_setmode@basic.html * igt at perf@blocking-parameterized: - shard-tglb: [FAIL][57] ([i915#1542]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb1/igt at perf@blocking-parameterized.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-tglb3/igt at perf@blocking-parameterized.html * igt at syncobj_wait@multi-wait-all-signaled: - shard-apl: [DMESG-WARN][59] ([i915#1635] / [i915#95]) -> [PASS][60] +17 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl7/igt at syncobj_wait@multi-wait-all-signaled.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-apl8/igt at syncobj_wait@multi-wait-all-signaled.html #### Warnings #### * igt at gem_exec_reloc@basic-concurrent16: - shard-snb: [TIMEOUT][61] ([i915#1958]) -> [FAIL][62] ([i915#1930]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-snb5/igt at gem_exec_reloc@basic-concurrent16.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-snb2/igt at gem_exec_reloc@basic-concurrent16.html - shard-apl: [INCOMPLETE][63] ([i915#1635] / [i915#1958]) -> [TIMEOUT][64] ([i915#1635] / [i915#1958]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl1/igt at gem_exec_reloc@basic-concurrent16.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-apl4/igt at gem_exec_reloc@basic-concurrent16.html * igt at gem_exec_reloc@basic-spin-others at vcs0: - shard-snb: [WARN][65] ([i915#2036]) -> [WARN][66] ([i915#2021]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-snb2/igt at gem_exec_reloc@basic-spin-others at vcs0.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-snb5/igt at gem_exec_reloc@basic-spin-others at vcs0.html * igt at i915_pm_dc@dc6-dpms: - shard-tglb: [SKIP][67] ([i915#468]) -> [FAIL][68] ([i915#454]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-tglb2/igt at i915_pm_dc@dc6-dpms.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-tglb8/igt at i915_pm_dc@dc6-dpms.html * igt at kms_draw_crc@draw-method-rgb565-render-ytiled: - shard-snb: [TIMEOUT][69] ([i915#1958]) -> [SKIP][70] ([fdo#109271]) +1 similar issue [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-snb5/igt at kms_draw_crc@draw-method-rgb565-render-ytiled.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-snb2/igt at kms_draw_crc@draw-method-rgb565-render-ytiled.html * igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-apl: [SKIP][71] ([fdo#109271]) -> [SKIP][72] ([fdo#109271] / [i915#1635]) +2 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl3/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-apl4/igt at kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html * igt at kms_plane_alpha_blend@pipe-a-alpha-7efc: - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][74] ([fdo#108145] / [i915#1982]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-skl5/igt at kms_plane_alpha_blend@pipe-a-alpha-7efc.html * igt at perf@gen12-unprivileged-single-ctx-counters: - shard-apl: [SKIP][75] ([fdo#109271] / [i915#1635]) -> [SKIP][76] ([fdo#109271]) +7 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8665/shard-apl7/igt at perf@gen12-unprivileged-single-ctx-counters.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/shard-apl8/igt at perf@gen12-unprivileged-single-ctx-counters.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#666]: https://gitlab.freedesktop.org/drm/intel/issues/666 [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8665 -> Patchwork_18020 CI-20190529: 20190529 CI_DRM_8665: 2cb786fa6506e20b5cb2a10decda11454111e026 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5717: 725bf2dae51f0087eaa64f1931a2ef9d22f070dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18020: 2ac53d393597ee152a2392db4e6f1f47bd76bc78 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18020/index.html From stanislav.lisovskiy at intel.com Fri Jun 26 15:13:36 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Fri, 26 Jun 2020 18:13:36 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200626134641.GZ6112@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> Message-ID: <20200626151336.GA6490@intel.com> On Fri, Jun 26, 2020 at 04:46:41PM +0300, Ville Syrj?l? wrote: > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > The linetime watermark is a 9 bit value, which gives us > > > a maximum linetime of just below 64 usec. If the linetime > > > exceeds that value we currently just discard the high bits > > > and program the rest into the register, which angers the > > > state checker. > > > > > > To avoid that let's just clamp the value to the max. I believe > > > it should be perfectly fine to program a smaller linetime wm > > > than strictly required, just means the hardware may fetch data > > > sooner than strictly needed. We are further reassured by the > > > fact that with DRRS the spec tells us to program the smaller > > > of the two linetimes corresponding to the two refresh rates. > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > index a11bb675f9b3..d486d675166f 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) > > > { > > > const struct drm_display_mode *adjusted_mode = > > > &crtc_state->hw.adjusted_mode; > > > + int linetime_wm; > > > > > > if (!crtc_state->hw.enable) > > > return 0; > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > - adjusted_mode->crtc_clock); > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > + adjusted_mode->crtc_clock); > > > + > > > + return min(linetime_wm, 0x1ff); > > > > Are we actually doing the right thing here? I just mean that we get value > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > As explained in the commit msg programming this to lower than necessary > value should be totally fine. It just won't be optimal. > > The values in the jira (was there an actual gitlab bug for this btw?) > look quite sensible to me. Some kind of low res 848xsomething mode with > dotclock of 14.874 Mhz, which gives us that linetime of ~68 usec. Htotal from modeline "848x480": 30 14874 848 896 928 1008 480 483 488 494 0x40 0x9 is 1008. According to the formula above htotal(1008)*1000*8 / 14874(crtc_clock) = 542.154 So what's the catch? :) Stan > > > > > Stan > > > } > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > { > > > const struct drm_display_mode *adjusted_mode = > > > &crtc_state->hw.adjusted_mode; > > > + int linetime_wm; > > > > > > if (!crtc_state->hw.enable) > > > return 0; > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > - cdclk_state->logical.cdclk); > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > + cdclk_state->logical.cdclk); > > > + > > > + return min(linetime_wm, 0x1ff); > > > } > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > const struct drm_display_mode *adjusted_mode = > > > &crtc_state->hw.adjusted_mode; > > > - u16 linetime_wm; > > > + int linetime_wm; > > > > > > if (!crtc_state->hw.enable) > > > return 0; > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > linetime_wm /= 2; > > > > > > - return linetime_wm; > > > + return min(linetime_wm, 0x1ff); > > > } > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state *state, > > > -- > > > 2.26.2 > > > > > -- > Ville Syrj?l? > Intel From tvrtko.ursulin at linux.intel.com Fri Jun 26 15:22:23 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Fri, 26 Jun 2020 16:22:23 +0100 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info In-Reply-To: <20200625234212.22811-8-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-8-daniele.ceraolospurio@intel.com> Message-ID: <689ef3ca-284d-6f3c-1ee6-4abab6a536a2@linux.intel.com> On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: > From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> > > SSEUs are a GT capability, so track them under gt_info. > > Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > Cc: Andi Shyti <andi.shyti at intel.com> > --- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 7 ++++--- > drivers/gpu/drm/i915/gem/i915_gem_context.h | 2 +- > .../drm/i915/gem/selftests/i915_gem_context.c | 5 ++++- > drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++-- > drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++ > drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rps.c | 3 ++- > drivers/gpu/drm/i915/gt/intel_sseu.c | 19 ++++++++++--------- > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++---- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +-- > drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++----- Add SSEU to debugfs_gt.c / debugfs_sseu.c ? Regards, Tvrtko > drivers/gpu/drm/i915/i915_getparam.c | 2 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++-- > drivers/gpu/drm/i915/i915_perf.c | 9 ++++----- > drivers/gpu/drm/i915/i915_query.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 3 --- > drivers/gpu/drm/i915/intel_device_info.h | 3 --- > 20 files changed, 49 insertions(+), 46 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c > index 5c13809dc3c8..4fc641d5cb68 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > @@ -1399,11 +1399,12 @@ static int get_ringsize(struct i915_gem_context *ctx, > } > > int > -i915_gem_user_to_context_sseu(struct drm_i915_private *i915, > +i915_gem_user_to_context_sseu(struct intel_gt *gt, > const struct drm_i915_gem_context_param_sseu *user, > struct intel_sseu *context) > { > - const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu; > + const struct sseu_dev_info *device = >->info.sseu; > + struct drm_i915_private *i915 = gt->i915; > > /* No zeros in any field. */ > if (!user->slice_mask || !user->subslice_mask || > @@ -1536,7 +1537,7 @@ static int set_sseu(struct i915_gem_context *ctx, > goto out_ce; > } > > - ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu); > + ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, &sseu); > if (ret) > goto out_ce; > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h > index 3702b2fb27ab..a133f92bbedb 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h > @@ -225,7 +225,7 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it); > struct i915_lut_handle *i915_lut_handle_alloc(void); > void i915_lut_handle_free(struct i915_lut_handle *lut); > > -int i915_gem_user_to_context_sseu(struct drm_i915_private *i915, > +int i915_gem_user_to_context_sseu(struct intel_gt *gt, > const struct drm_i915_gem_context_param_sseu *user, > struct intel_sseu *context); > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > index b81978890641..7ffc3c751432 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > @@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915, > int inst = 0; > int ret = 0; > > - if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg) > + if (INTEL_GEN(i915) < 9) > return 0; > > if (flags & TEST_RESET) > @@ -1255,6 +1255,9 @@ __igt_ctx_sseu(struct drm_i915_private *i915, > if (hweight32(engine->sseu.slice_mask) < 2) > continue; > > + if (!engine->gt->info.sseu.has_slice_pg) > + continue; > + > /* > * Gen11 VME friendly power-gated configuration with > * half enabled sub-slices. > diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c > index 27ae48049239..b9c8163978a3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c > @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq, > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; > *cs++ = lower_32_bits(offset); > *cs++ = upper_32_bits(offset); > - *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu); > + *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); > > intel_ring_advance(rq, cs); > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 3af58df3b13e..af08fdddd972 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -705,7 +705,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) > > /* Use the whole device by default */ > engine->sseu = > - intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu); > + intel_sseu_from_device_info(&engine->gt->info.sseu); > > intel_engine_init_workarounds(engine); > intel_engine_init_whitelist(engine); > @@ -1071,7 +1071,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine, > struct intel_instdone *instdone) > { > struct drm_i915_private *i915 = engine->i915; > - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; > + const struct sseu_dev_info *sseu = &engine->gt->info.sseu; > struct intel_uncore *uncore = engine->uncore; > u32 mmio_base = engine->mmio_base; > int slice; > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c > index de95930f8627..b1748fa67eca 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -655,4 +655,6 @@ void intel_gt_info_print(const struct intel_gt_info *info, > struct drm_printer *p) > { > drm_printf(p, "available engines: %x\n", info->engine_mask); > + > + intel_sseu_dump(&info->sseu, p); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h > index bb7551867c00..6d39a4a11bf3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h > @@ -116,6 +116,9 @@ struct intel_gt { > > /* Media engine access to SFC per instance */ > u8 vdbox_sfc_access; > + > + /* Slice/subslice/EU info */ > + struct sseu_dev_info sseu; > } info; > }; > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index e866b8d721ed..9e28b2f9df72 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -3422,7 +3422,7 @@ __execlists_update_reg_state(const struct intel_context *ce, > /* RPCS */ > if (engine->class == RENDER_CLASS) { > regs[CTX_R_PWR_CLK_STATE] = > - intel_sseu_make_rpcs(engine->i915, &ce->sseu); > + intel_sseu_make_rpcs(engine->gt, &ce->sseu); > > i915_oa_init_reg_state(ce, engine); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index 296391deeb94..97ba14ad52e4 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -1062,11 +1062,12 @@ static bool gen6_rps_enable(struct intel_rps *rps) > static int chv_rps_max_freq(struct intel_rps *rps) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > + struct intel_gt *gt = rps_to_gt(rps); > u32 val; > > val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); > > - switch (RUNTIME_INFO(i915)->sseu.eu_total) { > + switch (gt->info.sseu.eu_total) { > case 8: > /* (2 * 4) config */ > val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT; > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c > index 006f9118b319..e29f0785b3c5 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > @@ -130,7 +130,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, > > static void gen12_sseu_info_init(struct intel_gt *gt) > { > - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct sseu_dev_info *sseu = >->info.sseu; > struct intel_uncore *uncore = gt->uncore; > u8 s_en; > u32 dss_en; > @@ -165,7 +165,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt) > > static void gen11_sseu_info_init(struct intel_gt *gt) > { > - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct sseu_dev_info *sseu = >->info.sseu; > struct intel_uncore *uncore = gt->uncore; > u8 s_en; > u32 ss_en; > @@ -194,7 +194,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt) > static void gen10_sseu_info_init(struct intel_gt *gt) > { > struct intel_uncore *uncore = gt->uncore; > - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct sseu_dev_info *sseu = >->info.sseu; > const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); > int s, ss; > const int eu_mask = 0xff; > @@ -270,7 +270,7 @@ static void gen10_sseu_info_init(struct intel_gt *gt) > > static void cherryview_sseu_info_init(struct intel_gt *gt) > { > - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct sseu_dev_info *sseu = >->info.sseu; > u32 fuse; > u8 subslice_mask = 0; > > @@ -327,7 +327,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) > { > struct drm_i915_private *i915 = gt->i915; > struct intel_device_info *info = mkwrite_device_info(i915); > - struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; > + struct sseu_dev_info *sseu = >->info.sseu; > struct intel_uncore *uncore = gt->uncore; > int s, ss; > u32 fuse2, eu_disable, subslice_mask; > @@ -431,7 +431,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) > > static void bdw_sseu_info_init(struct intel_gt *gt) > { > - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct sseu_dev_info *sseu = >->info.sseu; > struct intel_uncore *uncore = gt->uncore; > int s, ss; > u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ > @@ -517,7 +517,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt) > static void hsw_sseu_info_init(struct intel_gt *gt) > { > struct drm_i915_private *i915 = gt->i915; > - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; > + struct sseu_dev_info *sseu = >->info.sseu; > u32 fuse1; > u8 subslice_mask = 0; > int s, ss; > @@ -602,10 +602,11 @@ void intel_sseu_info_init(struct intel_gt *gt) > gen12_sseu_info_init(gt); > } > > -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > +u32 intel_sseu_make_rpcs(struct intel_gt *gt, > const struct intel_sseu *req_sseu) > { > - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; > + struct drm_i915_private *i915 = gt->i915; > + const struct sseu_dev_info *sseu = >->info.sseu; > bool subslice_pg = sseu->has_subslice_pg; > u8 slices, subslices; > u32 rpcs = 0; > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h > index f9c007f001e7..23ba6c2ebe70 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.h > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h > @@ -98,7 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, > > void intel_sseu_info_init(struct intel_gt *gt); > > -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, > +u32 intel_sseu_make_rpcs(struct intel_gt *gt, > const struct intel_sseu *req_sseu); > > void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 2da366821dda..dbafd923e5a1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -404,7 +404,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, > static void skl_tune_iz_hashing(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > { > - struct drm_i915_private *i915 = engine->i915; > + struct intel_gt *gt = engine->gt; > u8 vals[3] = { 0, 0, 0 }; > unsigned int i; > > @@ -415,7 +415,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine, > * Only consider slices where one, and only one, subslice has 7 > * EUs > */ > - if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) > + if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) > continue; > > /* > @@ -424,7 +424,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine, > * > * -> 0 <= ss <= 3; > */ > - ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; > + ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; > vals[i] = 3 - ss; > } > > @@ -1036,7 +1036,7 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > static void > wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) > { > - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; > + const struct sseu_dev_info *sseu = &i915->gt.info.sseu; > unsigned int slice, subslice; > u32 l3_en, mcr, mcr_mask; > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index c10ae1660e53..d44061033f23 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -68,7 +68,6 @@ struct __guc_ads_blob { > static void __guc_ads_init(struct intel_guc *guc) > { > struct intel_gt *gt = guc_to_gt(guc); > - struct drm_i915_private *dev_priv = gt->i915; > struct __guc_ads_blob *blob = guc->ads_blob; > const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; > u32 base; > @@ -100,7 +99,7 @@ static void __guc_ads_init(struct intel_guc *guc) > } > > /* System info */ > - blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); > + blob->system_info.slice_enabled = hweight8(gt->info.sseu.slice_mask); > blob->system_info.rcs_enabled = 1; > blob->system_info.bcs_enabled = 1; > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index c893a82c2d99..16b012b5673d 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, void *unused) > struct drm_i915_private *dev_priv = node_to_i915(m->private); > struct drm_printer p = drm_seq_file_printer(m); > > - intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); > + intel_sseu_print_topology(&dev_priv->gt.info.sseu, &p); > > return 0; > } > @@ -1624,7 +1624,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, > struct sseu_dev_info *sseu) > { > #define SS_MAX 6 > - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); > + const struct intel_gt_info *info = &dev_priv->gt.info; > u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; > int s, ss; > > @@ -1681,7 +1681,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, > struct sseu_dev_info *sseu) > { > #define SS_MAX 3 > - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); > + const struct intel_gt_info *info = &dev_priv->gt.info; > u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; > int s, ss; > > @@ -1739,7 +1739,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, > static void bdw_sseu_device_status(struct drm_i915_private *dev_priv, > struct sseu_dev_info *sseu) > { > - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); > + const struct intel_gt_info *info = &dev_priv->gt.info; > u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); > int s; > > @@ -1802,7 +1802,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, > static int i915_sseu_status(struct seq_file *m, void *unused) > { > struct drm_i915_private *dev_priv = node_to_i915(m->private); > - const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); > + const struct intel_gt_info *info = &dev_priv->gt.info; > struct sseu_dev_info sseu; > intel_wakeref_t wakeref; > > diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c > index 40390b2352b1..421613219ae9 100644 > --- a/drivers/gpu/drm/i915/i915_getparam.c > +++ b/drivers/gpu/drm/i915/i915_getparam.c > @@ -12,7 +12,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, > struct drm_file *file_priv) > { > struct drm_i915_private *i915 = to_i915(dev); > - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; > + const struct sseu_dev_info *sseu = &i915->gt.info.sseu; > drm_i915_getparam_t *param = data; > int value; > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 99b4a0261b13..678ddec3237f 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -426,7 +426,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m) > static void error_print_instdone(struct drm_i915_error_state_buf *m, > const struct intel_engine_coredump *ee) > { > - const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; > + const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; > int slice; > int subslice; > > @@ -626,8 +626,8 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m, > > intel_device_info_print_static(&error->device_info, &p); > intel_device_info_print_runtime(&error->runtime_info, &p); > - intel_sseu_print_topology(&error->runtime_info.sseu, &p); > intel_gt_info_print(&error->gt->info, &p); > + intel_sseu_print_topology(&error->gt->info.sseu, &p); > intel_driver_caps_print(&error->driver_caps, &p); > } > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 25329b7600c9..37631ce0699b 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -2196,7 +2196,7 @@ static int gen8_configure_context(struct i915_gem_context *ctx, > if (!intel_context_pin_if_active(ce)) > continue; > > - flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu); > + flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu); > err = gen8_modify_context(ce, flex, count); > > intel_context_unpin(ce); > @@ -2340,7 +2340,7 @@ oa_configure_all_contexts(struct i915_perf_stream *stream, > if (engine->class != RENDER_CLASS) > continue; > > - regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu); > + regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu); > > err = gen8_modify_self(ce, regs, num_regs, active); > if (err) > @@ -2740,8 +2740,7 @@ static void > get_default_sseu_config(struct intel_sseu *out_sseu, > struct intel_engine_cs *engine) > { > - const struct sseu_dev_info *devinfo_sseu = > - &RUNTIME_INFO(engine->i915)->sseu; > + const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu; > > *out_sseu = intel_sseu_from_device_info(devinfo_sseu); > > @@ -2766,7 +2765,7 @@ get_sseu_config(struct intel_sseu *out_sseu, > drm_sseu->engine.engine_instance != engine->uabi_instance) > return -EINVAL; > > - return i915_gem_user_to_context_sseu(engine->i915, drm_sseu, out_sseu); > + return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu); > } > > /** > diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c > index c1ebda9b5627..fed337ad7b68 100644 > --- a/drivers/gpu/drm/i915/i915_query.c > +++ b/drivers/gpu/drm/i915/i915_query.c > @@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t query_sz, > static int query_topology_info(struct drm_i915_private *dev_priv, > struct drm_i915_query_item *query_item) > { > - const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; > + const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu; > struct drm_i915_query_topology_info topo; > u32 slice_length, subslice_length, eu_length, total_length; > int ret; > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index d8daf224cbd3..3f5dc37d2b7c 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -29,7 +29,6 @@ > #include "display/intel_de.h" > #include "intel_device_info.h" > #include "i915_drv.h" > -#include "gt/intel_sseu.h" > > #define PLATFORM_NAME(x) [INTEL_##x] = #x > static const char * const platform_names[] = { > @@ -115,8 +114,6 @@ void intel_device_info_print_static(const struct intel_device_info *info, > void intel_device_info_print_runtime(const struct intel_runtime_info *info, > struct drm_printer *p) > { > - intel_sseu_dump(&info->sseu, p); > - > drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); > drm_printf(p, "CS timestamp frequency: %u Hz\n", > info->cs_timestamp_frequency_hz); > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index ce2ccee9b49b..f6f897c06cc8 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -219,9 +219,6 @@ struct intel_runtime_info { > u8 num_sprites[I915_MAX_PIPES]; > u8 num_scalers[I915_MAX_PIPES]; > > - /* Slice/subslice/EU info */ > - struct sseu_dev_info sseu; > - > u32 rawclk_freq; > > u32 cs_timestamp_frequency_hz; > From jani.nikula at linux.intel.com Fri Jun 26 15:22:31 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Fri, 26 Jun 2020 18:22:31 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Send_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <159299589741.19236.15323518631653361058@emeril.freedesktop.org> References: <20200623185756.19502-1-kunal1.joshi@intel.com> <159299589741.19236.15323518631653361058@emeril.freedesktop.org> Message-ID: <87zh8pn96w.fsf@intel.com> On Wed, 24 Jun 2020, Patchwork <patchwork at emeril.freedesktop.org> wrote: > == Series Details == > > Series: Send a hotplug when edid changes (rev8) > URL : https://patchwork.freedesktop.org/series/62816/ > State : warning > > == Summary == Please at least fix the spacing issues. Please don't use spaces for indentation. BR, Jani. > > $ dim checkpatch origin/drm-tip > eeee75d80077 drm: Add helper to compare edids. > -:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid1" > #32: FILE: drivers/gpu/drm/drm_edid.c:1628: > + bool edid1_present = edid1 != NULL; > > -:33: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid2" > #33: FILE: drivers/gpu/drm/drm_edid.c:1629: > + bool edid2_present = edid2 != NULL; > > -:39: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' > #39: FILE: drivers/gpu/drm/drm_edid.c:1635: > + if (edid1) { > + > > -:54: CHECK:LINE_SPACING: Please don't use multiple blank lines > #54: FILE: drivers/gpu/drm/drm_edid.c:1650: > + > + > > total: 0 errors, 0 warnings, 4 checks, 54 lines checked > 127303584a7e drm: Introduce epoch counter to drm_connector > -:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #56: FILE: drivers/gpu/drm/drm_connector.c:2012: > + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", > + connector->base.id, connector->name); > > -:60: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #60: FILE: drivers/gpu/drm/drm_connector.c:2016: > + DRM_DEBUG_KMS("Updating change counter to %llu\n", > + connector->epoch_counter); > > -:129: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' > #129: FILE: drivers/gpu/drm/drm_probe_helper.c:790: > + uint64_t old_epoch_counter; > > -:160: WARNING:BRACES: braces {} are not necessary for single statement blocks > #160: FILE: drivers/gpu/drm/drm_probe_helper.c:826: > + if (old_epoch_counter != connector->epoch_counter) { > changed = true; > + } > > -:183: ERROR:CODE_INDENT: code indent should use tabs where possible > #183: FILE: include/drm/drm_connector.h:1332: > + /** @epoch_counter: used to detect any other changes in connector, besides status */$ > > -:184: ERROR:CODE_INDENT: code indent should use tabs where possible > #184: FILE: include/drm/drm_connector.h:1333: > + uint64_t epoch_counter;$ > > -:184: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #184: FILE: include/drm/drm_connector.h:1333: > + uint64_t epoch_counter;$ > > -:184: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' > #184: FILE: include/drm/drm_connector.h:1333: > + uint64_t epoch_counter; > > total: 2 errors, 2 warnings, 4 checks, 136 lines checked > 6f6d00bcff9f drm/i915: Send hotplug event if edid had changed > -:42: ERROR:CODE_INDENT: code indent should use tabs where possible > #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: > + u64 old_epoch_counter;$ > > -:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: > + u64 old_epoch_counter;$ > > -:43: ERROR:CODE_INDENT: code indent should use tabs where possible > #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: > + bool ret = false;$ > > -:43: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: > + bool ret = false;$ > > -:62: ERROR:CODE_INDENT: code indent should use tabs where possible > #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: > + if (old_epoch_counter != connector->base.epoch_counter)$ > > -:62: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: > + if (old_epoch_counter != connector->base.epoch_counter)$ > > -:63: ERROR:CODE_INDENT: code indent should use tabs where possible > #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: > + ret = true;$ > > -:63: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: > + ret = true;$ > > -:65: ERROR:CODE_INDENT: code indent should use tabs where possible > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > + if(ret) {$ > > -:65: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > + if(ret) {$ > > -:65: ERROR:SPACING: space required before the open parenthesis '(' > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > + if(ret) { > > -:73: ERROR:CODE_INDENT: code indent should use tabs where possible > #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: > + }$ > > -:73: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: > + }$ > > -:74: ERROR:CODE_INDENT: code indent should use tabs where possible > #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: > + return INTEL_HOTPLUG_UNCHANGED;$ > > -:74: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: > + return INTEL_HOTPLUG_UNCHANGED;$ > > total: 8 errors, 7 warnings, 0 checks, 38 lines checked > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center From stanislav.lisovskiy at intel.com Fri Jun 26 15:25:24 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Fri, 26 Jun 2020 15:25:24 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Send_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <87zh8pn96w.fsf@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> <159299589741.19236.15323518631653361058@emeril.freedesktop.org>, <87zh8pn96w.fsf@intel.com> Message-ID: <3542d23ab420436ba0573b8575aa1376@intel.com> Omg, where did those come from?.. Joshi Kunal: will you fix or should I do that? Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ________________________________________ From: Jani Nikula <jani.nikula at linux.intel.com> Sent: Friday, June 26, 2020 6:22:31 PM To: Patchwork; Lisovskiy, Stanislav Cc: intel-gfx at lists.freedesktop.org; Joshi, Kunal1 Subject: Re: [Intel-gfx] ? Fi.CI.CHECKPATCH: warning for Send a hotplug when edid changes (rev8) On Wed, 24 Jun 2020, Patchwork <patchwork at emeril.freedesktop.org> wrote: > == Series Details == > > Series: Send a hotplug when edid changes (rev8) > URL : https://patchwork.freedesktop.org/series/62816/ > State : warning > > == Summary == Please at least fix the spacing issues. Please don't use spaces for indentation. BR, Jani. > > $ dim checkpatch origin/drm-tip > eeee75d80077 drm: Add helper to compare edids. > -:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid1" > #32: FILE: drivers/gpu/drm/drm_edid.c:1628: > + bool edid1_present = edid1 != NULL; > > -:33: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid2" > #33: FILE: drivers/gpu/drm/drm_edid.c:1629: > + bool edid2_present = edid2 != NULL; > > -:39: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' > #39: FILE: drivers/gpu/drm/drm_edid.c:1635: > + if (edid1) { > + > > -:54: CHECK:LINE_SPACING: Please don't use multiple blank lines > #54: FILE: drivers/gpu/drm/drm_edid.c:1650: > + > + > > total: 0 errors, 0 warnings, 4 checks, 54 lines checked > 127303584a7e drm: Introduce epoch counter to drm_connector > -:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #56: FILE: drivers/gpu/drm/drm_connector.c:2012: > + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", > + connector->base.id, connector->name); > > -:60: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > #60: FILE: drivers/gpu/drm/drm_connector.c:2016: > + DRM_DEBUG_KMS("Updating change counter to %llu\n", > + connector->epoch_counter); > > -:129: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' > #129: FILE: drivers/gpu/drm/drm_probe_helper.c:790: > + uint64_t old_epoch_counter; > > -:160: WARNING:BRACES: braces {} are not necessary for single statement blocks > #160: FILE: drivers/gpu/drm/drm_probe_helper.c:826: > + if (old_epoch_counter != connector->epoch_counter) { > changed = true; > + } > > -:183: ERROR:CODE_INDENT: code indent should use tabs where possible > #183: FILE: include/drm/drm_connector.h:1332: > + /** @epoch_counter: used to detect any other changes in connector, besides status */$ > > -:184: ERROR:CODE_INDENT: code indent should use tabs where possible > #184: FILE: include/drm/drm_connector.h:1333: > + uint64_t epoch_counter;$ > > -:184: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #184: FILE: include/drm/drm_connector.h:1333: > + uint64_t epoch_counter;$ > > -:184: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' > #184: FILE: include/drm/drm_connector.h:1333: > + uint64_t epoch_counter; > > total: 2 errors, 2 warnings, 4 checks, 136 lines checked > 6f6d00bcff9f drm/i915: Send hotplug event if edid had changed > -:42: ERROR:CODE_INDENT: code indent should use tabs where possible > #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: > + u64 old_epoch_counter;$ > > -:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: > + u64 old_epoch_counter;$ > > -:43: ERROR:CODE_INDENT: code indent should use tabs where possible > #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: > + bool ret = false;$ > > -:43: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: > + bool ret = false;$ > > -:62: ERROR:CODE_INDENT: code indent should use tabs where possible > #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: > + if (old_epoch_counter != connector->base.epoch_counter)$ > > -:62: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: > + if (old_epoch_counter != connector->base.epoch_counter)$ > > -:63: ERROR:CODE_INDENT: code indent should use tabs where possible > #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: > + ret = true;$ > > -:63: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: > + ret = true;$ > > -:65: ERROR:CODE_INDENT: code indent should use tabs where possible > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > + if(ret) {$ > > -:65: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > + if(ret) {$ > > -:65: ERROR:SPACING: space required before the open parenthesis '(' > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > + if(ret) { > > -:73: ERROR:CODE_INDENT: code indent should use tabs where possible > #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: > + }$ > > -:73: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: > + }$ > > -:74: ERROR:CODE_INDENT: code indent should use tabs where possible > #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: > + return INTEL_HOTPLUG_UNCHANGED;$ > > -:74: WARNING:LEADING_SPACE: please, no spaces at the start of a line > #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: > + return INTEL_HOTPLUG_UNCHANGED;$ > > total: 8 errors, 7 warnings, 0 checks, 38 lines checked > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center From sumit.semwal at linaro.org Fri Jun 26 15:34:39 2020 From: sumit.semwal at linaro.org (Sumit Semwal) Date: Fri, 26 Jun 2020 21:04:39 +0530 Subject: [Intel-gfx] [PATCH 1/2] Revert "dma-buf: Report signaled links inside dma-fence-chain" In-Reply-To: <CAKMK7uE--1E59fOhQPZ3ib4a3bSK1Nf5ikLB_GHf2wRsFTvXhw@mail.gmail.com> References: <20200625123443.19680-1-lionel.g.landwerlin@intel.com> <51e00eed-c8f1-aabf-ec2c-07be0453ab3b@amd.com> <CAPM=9txhX5TVUdWibRFc1C+ip5a8-c07jZawds=k5T5pBTPASA@mail.gmail.com> <874kqzndxj.fsf@intel.com> <CAKMK7uErpxoFrT_K==7-PMGyg_eqF07T50eYfh5BFQLzra7TbQ@mail.gmail.com> <CAO_48GEa2ZgMph-1ZdsMcOdomZc4zNuRcNn_DoBZS3sNZa-LTg@mail.gmail.com> <b7b1eb80-aa98-2d54-2344-dbc2e4bc0492@amd.com> <CAKMK7uE--1E59fOhQPZ3ib4a3bSK1Nf5ikLB_GHf2wRsFTvXhw@mail.gmail.com> Message-ID: <CAO_48GFBuO=c=ugenqo=m4_ydTn1s0J67oBCxCvHGkROU=EuGA@mail.gmail.com> Hi Christian, On Fri, 26 Jun 2020, 18:10 Daniel Vetter, <daniel at ffwll.ch> wrote: > On Fri, Jun 26, 2020 at 9:03 AM Christian K?nig > <christian.koenig at amd.com> wrote: > > > > Am 26.06.20 um 06:43 schrieb Sumit Semwal: > > > On Fri, 26 Jun 2020 at 01:24, Daniel Vetter <daniel at ffwll.ch> wrote: > > >> Ignoring everything else ... > > >> > > >> On Thu, Jun 25, 2020 at 9:28 PM Jani Nikula < > jani.nikula at linux.intel.com> wrote: > > >>> As a side note, there seem to be extra checks in place for acks when > > >>> applying non-i915 patches to drm-intel; there are no such checks for > > >>> drm-misc. > > >> One option to generalize that that I pondered is to consult > > >> get_maintainers.pl asking for git repo link, and if that returns > > >> something else, then insist that there's an ack from a relevant > > >> maintainer. It's a bit of typing, but I think the bigger problem is > > >> that there's a ton of false positives. > > > Right; for the particular patch, I wasn't even in the to: or cc: field > > > and that made it slip from my radar. I would definitely ask any one > > > sending patches for dma-buf directory to follow the get_maintainers.pl > > > religiously. > > >> But maybe that's a good thing, would give some motivation to keep > > >> MAINTAINERS updated. > > > > Should I maybe add myself as maintainer as well? I've written enough > > stuff in there to know the code quite a bit. > > I think that makes lots of sense, since defacto you already are :-) > > If you feel like bikeshed, get_maintainers.pl also supports R: for > reviewer, but given that you also push patches to drm-misc M: for > maintainer feels more accurate. > I think given you've been reviewing and changing most of the code around dma-fences, it should be ok to add you as the maintainer for those bits? -Daniel > Best, Sumit. -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200626/e618a590/attachment.htm> From kunal1.joshi at intel.com Fri Jun 26 09:13:30 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Fri, 26 Jun 2020 14:43:30 +0530 Subject: [Intel-gfx] [PATCH v6 0/3] Send a hotplug when edid changes Message-ID: <20200626091333.17516-1-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> This series introduce to drm a way to determine if something else except connection_status had changed during probing, which can be used by other drivers as well. Another i915 specific part uses this approach to determine if edid had changed without changing the connection status and send a hotplug event. Stanislav Lisovskiy (3): drm: Add helper to compare edids. drm: Introduce epoch counter to drm_connector drm/i915: Send hotplug event if edid had changed drivers/gpu/drm/drm_connector.c | 16 ++++++++ drivers/gpu/drm/drm_edid.c | 39 +++++++++++++++++++- drivers/gpu/drm/drm_probe_helper.c | 38 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_hotplug.c | 24 +++++++----- include/drm/drm_connector.h | 2 + include/drm/drm_edid.h | 9 +++++ 6 files changed, 112 insertions(+), 16 deletions(-) -- 2.25.1 From kunal1.joshi at intel.com Fri Jun 26 09:13:31 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Fri, 26 Jun 2020 14:43:31 +0530 Subject: [Intel-gfx] [PATCH v6 1/3] drm: Add helper to compare edids. In-Reply-To: <20200626091333.17516-1-kunal1.joshi@intel.com> References: <20200626091333.17516-1-kunal1.joshi@intel.com> Message-ID: <20200626091333.17516-2-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Many drivers would benefit from using drm helper to compare edid, rather than bothering with own implementation. v2: Added documentation for this function. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/drm_edid.c | 33 +++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 9 +++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 71ae0cd6d576..920ac9ef6018 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1615,6 +1615,39 @@ static bool drm_edid_is_zero(const u8 *in_edid, int length) return true; } +/** + * drm_edid_are_equal - compare two edid blobs. + * @edid1: pointer to first blob + * @edid2: pointer to second blob + * This helper can be used during probing to determine if + * edid had changed. + */ +bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) +{ + int edid1_len, edid2_len; + bool edid1_present = edid1 != NULL; + bool edid2_present = edid2 != NULL; + + if (edid1_present != edid2_present) + return false; + + if (edid1) { + + edid1_len = EDID_LENGTH * (1 + edid1->extensions); + edid2_len = EDID_LENGTH * (1 + edid2->extensions); + + if (edid1_len != edid2_len) + return false; + + if (memcmp(edid1, edid2, edid1_len)) + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_edid_are_equal); + + /** * drm_edid_block_valid - Sanity check the EDID block (base or extension) * @raw_edid: pointer to raw EDID block diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 43254319ab19..cfa4f5af49af 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -359,6 +359,15 @@ drm_load_edid_firmware(struct drm_connector *connector) } #endif +/** + * drm_edid_are_equal - compare two edid blobs. + * @edid1: pointer to first blob + * @edid2: pointer to second blob + * This helper can be used during probing to determine if + * edid had changed. + */ +bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); + int drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, const struct drm_connector *connector, -- 2.25.1 From kunal1.joshi at intel.com Fri Jun 26 09:13:32 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Fri, 26 Jun 2020 14:43:32 +0530 Subject: [Intel-gfx] [PATCH v6 2/3] drm: Introduce epoch counter to drm_connector In-Reply-To: <20200626091333.17516-1-kunal1.joshi@intel.com> References: <20200626091333.17516-1-kunal1.joshi@intel.com> Message-ID: <20200626091333.17516-3-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> This counter will be used by drm_helper_probe_detect caller to determine if anything had changed(including edid, connection status and etc). Hardware specific driver detect hooks are responsible for updating this counter when some change is detected to notify the drm part, which can trigger for example hotplug event. Also now call drm_connector_update_edid_property right after we get edid always to make sure there is a unified way to handle edid change, without having to change tons of source code as currently drm_connector_update_edid_property is called only in certain cases like reprobing and not right after edid is actually updated. v2: Added documentation for the new counter. Rename change_counter to epoch_counter. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105540 Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/drm_connector.c | 16 +++++++++++++ drivers/gpu/drm/drm_edid.c | 6 ++++- drivers/gpu/drm/drm_probe_helper.c | 38 ++++++++++++++++++++++++++---- include/drm/drm_connector.h | 2 ++ 4 files changed, 56 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index b7bd46033807..332686297e45 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -269,6 +269,7 @@ int drm_connector_init(struct drm_device *dev, INIT_LIST_HEAD(&connector->modes); mutex_init(&connector->mutex); connector->edid_blob_ptr = NULL; + connector->epoch_counter = 0; connector->tile_blob_ptr = NULL; connector->status = connector_status_unknown; connector->display_info.panel_orientation = @@ -1979,6 +1980,7 @@ int drm_connector_update_edid_property(struct drm_connector *connector, struct drm_device *dev = connector->dev; size_t size = 0; int ret; + const struct edid *old_edid; /* ignore requests to set edid when overridden */ if (connector->override_edid) @@ -2002,6 +2004,20 @@ int drm_connector_update_edid_property(struct drm_connector *connector, drm_update_tile_info(connector, edid); + if (connector->edid_blob_ptr) { + old_edid = (const struct edid *)connector->edid_blob_ptr->data; + if (old_edid) { + if (!drm_edid_are_equal(edid, old_edid)) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", + connector->base.id, connector->name); + + connector->epoch_counter += 1; + DRM_DEBUG_KMS("Updating change counter to %llu\n", + connector->epoch_counter); + } + } + } + drm_object_property_set_value(&connector->base, dev->mode_config.non_desktop_property, connector->display_info.non_desktop); diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 920ac9ef6018..b7530db4a93b 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2050,13 +2050,17 @@ EXPORT_SYMBOL(drm_probe_ddc); struct edid *drm_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) { + struct edid *edid; + if (connector->force == DRM_FORCE_OFF) return NULL; if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) return NULL; - return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); + edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); + drm_connector_update_edid_property(connector, edid); + return edid; } EXPORT_SYMBOL(drm_get_edid); diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index 09e872e61315..7378c61e7fcc 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -292,6 +292,9 @@ drm_helper_probe_detect_ctx(struct drm_connector *connector, bool force) if (WARN_ON(ret < 0)) ret = connector_status_unknown; + if (ret != connector->status) + connector->epoch_counter += 1; + drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); @@ -325,11 +328,16 @@ drm_helper_probe_detect(struct drm_connector *connector, return ret; if (funcs->detect_ctx) - return funcs->detect_ctx(connector, ctx, force); + ret = funcs->detect_ctx(connector, ctx, force); else if (connector->funcs->detect) - return connector->funcs->detect(connector, force); + ret = connector->funcs->detect(connector, force); else - return connector_status_connected; + ret = connector_status_connected; + + if (ret != connector->status) + connector->epoch_counter += 1; + + return ret; } EXPORT_SYMBOL(drm_helper_probe_detect); @@ -779,6 +787,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) struct drm_connector_list_iter conn_iter; enum drm_connector_status old_status; bool changed = false; + uint64_t old_epoch_counter; if (!dev->mode_config.poll_enabled) return false; @@ -792,20 +801,39 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) old_status = connector->status; + old_epoch_counter = connector->epoch_counter; + + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Old epoch counter %llu\n", connector->base.id, + connector->name, + old_epoch_counter); + connector->status = drm_helper_probe_detect(connector, NULL, false); DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", connector->base.id, connector->name, drm_get_connector_status_name(old_status), drm_get_connector_status_name(connector->status)); - if (old_status != connector->status) + + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] New epoch counter %llu\n", + connector->base.id, + connector->name, + connector->epoch_counter); + + /* + * Check if epoch counter had changed, meaning that we need + * to send a uevent. + */ + if (old_epoch_counter != connector->epoch_counter) { changed = true; + } } drm_connector_list_iter_end(&conn_iter); mutex_unlock(&dev->mode_config.mutex); - if (changed) + if (changed) { drm_kms_helper_hotplug_event(dev); + DRM_DEBUG_KMS("Sent hotplug event\n"); + } return changed; } diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index fd543d1db9b2..e82b367cdfc8 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -1329,6 +1329,8 @@ struct drm_connector { enum drm_connector_force force; /** @override_edid: has the EDID been overwritten through debugfs for testing? */ bool override_edid; + /** @epoch_counter: used to detect any other changes in connector, besides status */ + uint64_t epoch_counter; /** * @possible_encoders: Bit mask of encoders that can drive this -- 2.25.1 From kunal1.joshi at intel.com Fri Jun 26 09:13:33 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Fri, 26 Jun 2020 14:43:33 +0530 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915: Send hotplug event if edid had changed In-Reply-To: <20200626091333.17516-1-kunal1.joshi@intel.com> References: <20200626091333.17516-1-kunal1.joshi@intel.com> Message-ID: <20200626091333.17516-4-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Added epoch counter checking to intel_encoder_hotplug in order to be able process all the connector changes, besides connection status. Also now any change in connector would result in epoch counter change, so no multiple checks are needed. v2: Renamed change counter to epoch counter. Fixed type name. v3: Fixed rebase conflict v4: Remove duplicate drm_edid_equal checks from hdmi and dp, lets use only once edid property is getting updated and increment epoch counter from there. Also lets now call drm_connector_update_edid_property right after we get edid always to make sure there is a unified way to handle edid change, without having to change tons of source code as currently drm_connector_update_edid_property is called only in certain cases like reprobing and not right after edid is actually updated. v5: Fixed const modifiers, removed blank line v6: Removed drm specific part from this patch, leaving only i915 specific changes here. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/i915/display/intel_hotplug.c | 24 ++++++++++++-------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 2e94c1413c02..80bcfff032e9 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -283,6 +283,8 @@ intel_encoder_hotplug(struct intel_encoder *encoder, { struct drm_device *dev = connector->base.dev; enum drm_connector_status old_status; + u64 old_epoch_counter; + bool ret = false; drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex)); old_status = connector->base.status; @@ -290,17 +292,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder, connector->base.status = drm_helper_probe_detect(&connector->base, NULL, false); - if (old_status == connector->base.status) - return INTEL_HOTPLUG_UNCHANGED; - - drm_dbg_kms(&to_i915(dev)->drm, - "[CONNECTOR:%d:%s] status updated from %s to %s\n", - connector->base.base.id, - connector->base.name, - drm_get_connector_status_name(old_status), - drm_get_connector_status_name(connector->base.status)); + if (old_epoch_counter != connector->base.epoch_counter) + ret = true; - return INTEL_HOTPLUG_CHANGED; + if (ret) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s(epoch counter %llu)\n", + connector->base.base.id, + connector->base.name, + drm_get_connector_status_name(old_status), + drm_get_connector_status_name(connector->base.status), + connector->base.epoch_counter); + return INTEL_HOTPLUG_CHANGED; + } + return INTEL_HOTPLUG_UNCHANGED; } static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder) -- 2.25.1 From kunal1.joshi at intel.com Fri Jun 26 09:15:40 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Fri, 26 Jun 2020 14:45:40 +0530 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6ICB3YXJuaW5n?= =?utf-8?q?_for_Send_a_hotplug_when_edid_changes_=28rev8=29?= In-Reply-To: <3542d23ab420436ba0573b8575aa1376@intel.com> References: <20200623185756.19502-1-kunal1.joshi@intel.com> <159299589741.19236.15323518631653361058@emeril.freedesktop.org> <87zh8pn96w.fsf@intel.com> <3542d23ab420436ba0573b8575aa1376@intel.com> Message-ID: <20200626091540.GA17572@intel.com> On 2020-06-26 at 08:25:24 -0700, Lisovskiy, Stanislav wrote: > Omg, where did those come from?.. > > Joshi Kunal: will you fix or should I do that? > > > Best Regards, > > Lisovskiy Stanislav > > Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo > yes stan floated with checkpatch errors removed > ________________________________________ > From: Jani Nikula <jani.nikula at linux.intel.com> > Sent: Friday, June 26, 2020 6:22:31 PM > To: Patchwork; Lisovskiy, Stanislav > Cc: intel-gfx at lists.freedesktop.org; Joshi, Kunal1 > Subject: Re: [Intel-gfx] ? Fi.CI.CHECKPATCH: warning for Send a hotplug when edid changes (rev8) > > On Wed, 24 Jun 2020, Patchwork <patchwork at emeril.freedesktop.org> wrote: > > == Series Details == > > > > Series: Send a hotplug when edid changes (rev8) > > URL : https://patchwork.freedesktop.org/series/62816/ > > State : warning > > > > == Summary == > > Please at least fix the spacing issues. Please don't use spaces for > indentation. > > BR, > Jani. > > > > > > $ dim checkpatch origin/drm-tip > > eeee75d80077 drm: Add helper to compare edids. > > -:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid1" > > #32: FILE: drivers/gpu/drm/drm_edid.c:1628: > > + bool edid1_present = edid1 != NULL; > > > > -:33: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid2" > > #33: FILE: drivers/gpu/drm/drm_edid.c:1629: > > + bool edid2_present = edid2 != NULL; > > > > -:39: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' > > #39: FILE: drivers/gpu/drm/drm_edid.c:1635: > > + if (edid1) { > > + > > > > -:54: CHECK:LINE_SPACING: Please don't use multiple blank lines > > #54: FILE: drivers/gpu/drm/drm_edid.c:1650: > > + > > + > > > > total: 0 errors, 0 warnings, 4 checks, 54 lines checked > > 127303584a7e drm: Introduce epoch counter to drm_connector > > -:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > > #56: FILE: drivers/gpu/drm/drm_connector.c:2012: > > + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", > > + connector->base.id, connector->name); > > > > -:60: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis > > #60: FILE: drivers/gpu/drm/drm_connector.c:2016: > > + DRM_DEBUG_KMS("Updating change counter to %llu\n", > > + connector->epoch_counter); > > > > -:129: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' > > #129: FILE: drivers/gpu/drm/drm_probe_helper.c:790: > > + uint64_t old_epoch_counter; > > > > -:160: WARNING:BRACES: braces {} are not necessary for single statement blocks > > #160: FILE: drivers/gpu/drm/drm_probe_helper.c:826: > > + if (old_epoch_counter != connector->epoch_counter) { > > changed = true; > > + } > > > > -:183: ERROR:CODE_INDENT: code indent should use tabs where possible > > #183: FILE: include/drm/drm_connector.h:1332: > > + /** @epoch_counter: used to detect any other changes in connector, besides status */$ > > > > -:184: ERROR:CODE_INDENT: code indent should use tabs where possible > > #184: FILE: include/drm/drm_connector.h:1333: > > + uint64_t epoch_counter;$ > > > > -:184: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #184: FILE: include/drm/drm_connector.h:1333: > > + uint64_t epoch_counter;$ > > > > -:184: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' > > #184: FILE: include/drm/drm_connector.h:1333: > > + uint64_t epoch_counter; > > > > total: 2 errors, 2 warnings, 4 checks, 136 lines checked > > 6f6d00bcff9f drm/i915: Send hotplug event if edid had changed > > -:42: ERROR:CODE_INDENT: code indent should use tabs where possible > > #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: > > + u64 old_epoch_counter;$ > > > > -:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #42: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:286: > > + u64 old_epoch_counter;$ > > > > -:43: ERROR:CODE_INDENT: code indent should use tabs where possible > > #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: > > + bool ret = false;$ > > > > -:43: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #43: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:287: > > + bool ret = false;$ > > > > -:62: ERROR:CODE_INDENT: code indent should use tabs where possible > > #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: > > + if (old_epoch_counter != connector->base.epoch_counter)$ > > > > -:62: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #62: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:295: > > + if (old_epoch_counter != connector->base.epoch_counter)$ > > > > -:63: ERROR:CODE_INDENT: code indent should use tabs where possible > > #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: > > + ret = true;$ > > > > -:63: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #63: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:296: > > + ret = true;$ > > > > -:65: ERROR:CODE_INDENT: code indent should use tabs where possible > > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > > + if(ret) {$ > > > > -:65: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > > + if(ret) {$ > > > > -:65: ERROR:SPACING: space required before the open parenthesis '(' > > #65: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:298: > > + if(ret) { > > > > -:73: ERROR:CODE_INDENT: code indent should use tabs where possible > > #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: > > + }$ > > > > -:73: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #73: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:306: > > + }$ > > > > -:74: ERROR:CODE_INDENT: code indent should use tabs where possible > > #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: > > + return INTEL_HOTPLUG_UNCHANGED;$ > > > > -:74: WARNING:LEADING_SPACE: please, no spaces at the start of a line > > #74: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:307: > > + return INTEL_HOTPLUG_UNCHANGED;$ > > > > total: 8 errors, 7 warnings, 0 checks, 38 lines checked > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Jani Nikula, Intel Open Source Graphics Center From daniele.ceraolospurio at intel.com Fri Jun 26 16:44:20 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Fri, 26 Jun 2020 09:44:20 -0700 Subject: [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info In-Reply-To: <78523c30-5aa6-ee94-722f-a0ed40b320b8@linux.intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-5-daniele.ceraolospurio@intel.com> <78523c30-5aa6-ee94-722f-a0ed40b320b8@linux.intel.com> Message-ID: <f4549696-cc18-cf02-e2a3-c5d6c6970e80@intel.com> On 6/26/20 7:45 AM, Tvrtko Ursulin wrote: > > On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: >> Since the engines belong to the GT, move the runtime-updated list of >> available engines to the intel_gt struct. The original mask has been >> renamed to indicate it contains the maximum engine list that can be >> found on a matching device. >> >> In preparation for other info being moved to the gt in follow up patches >> (sseu), introduce an intel_gt_info structure to group all gt-related >> runtime info. >> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> >> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com> >> Cc: Andi Shyti <andi.shyti at intel.com> >> Cc: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> >> --- >> ? .../gpu/drm/i915/gem/i915_gem_execbuffer.c??? |? 3 +- >> ? drivers/gpu/drm/i915/gt/intel_engine_cs.c???? | 13 +++--- >> ? drivers/gpu/drm/i915/gt/intel_gt.c??????????? |? 6 +++ >> ? drivers/gpu/drm/i915/gt/intel_gt.h??????????? |? 4 ++ >> ? drivers/gpu/drm/i915/gt/intel_gt_types.h????? |? 8 ++++ >> ? drivers/gpu/drm/i915/gt/intel_reset.c???????? |? 6 +-- >> ? .../gpu/drm/i915/gt/intel_ring_submission.c?? |? 2 +- >> ? drivers/gpu/drm/i915/gt/selftest_lrc.c??????? |? 8 ++-- >> ? drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c??? |? 2 +- >> ? drivers/gpu/drm/i915/gvt/handlers.c?????????? |? 2 +- >> ? drivers/gpu/drm/i915/i915_debugfs.c?????????? |? 2 + >> ? drivers/gpu/drm/i915/i915_drv.c?????????????? |? 1 + >> ? drivers/gpu/drm/i915/i915_drv.h?????????????? |? 6 +-- >> ? drivers/gpu/drm/i915/i915_gpu_error.c???????? | 23 ++++++---- >> ? drivers/gpu/drm/i915/i915_gpu_error.h???????? |? 3 ++ >> ? drivers/gpu/drm/i915/i915_pci.c?????????????? | 42 +++++++++---------- >> ? drivers/gpu/drm/i915/intel_device_info.c????? |? 1 - >> ? drivers/gpu/drm/i915/intel_device_info.h????? |? 7 +--- >> ? drivers/gpu/drm/i915/intel_uncore.c?????????? |? 2 +- >> ? drivers/gpu/drm/i915/selftests/i915_request.c |? 2 +- >> ? .../gpu/drm/i915/selftests/mock_gem_device.c? |? 3 +- >> ? 21 files changed, 84 insertions(+), 62 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> index c38ab51e82f0..7ffac711e4b4 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> @@ -1973,8 +1973,7 @@ static int eb_submit(struct i915_execbuffer *eb, >> struct i915_vma *batch) >> ? static int num_vcs_engines(const struct drm_i915_private *i915) >> ? { >> -??? return hweight64(INTEL_INFO(i915)->engine_mask & >> -???????????? GENMASK_ULL(VCS0 + I915_MAX_VCS - 1, VCS0)); >> +??? return hweight64(VDBOX_MASK(&i915->gt)); >> ? } >> ? /* >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> index 8497106eb3a6..3af58df3b13e 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> @@ -370,7 +370,7 @@ static void __setup_engine_capabilities(struct >> intel_engine_cs *engine) >> ?????????? * instances. >> ?????????? */ >> ????????? if ((INTEL_GEN(i915) >= 11 && >> -???????????? RUNTIME_INFO(i915)->vdbox_sfc_access & engine->mask) || >> +???????????? engine->gt->info.vdbox_sfc_access & engine->mask) || >> ????????????? (INTEL_GEN(i915) >= 9 && engine->instance == 0)) >> ????????????? engine->uabi_capabilities |= >> ????????????????? I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; >> @@ -459,7 +459,7 @@ void intel_engines_free(struct intel_gt *gt) >> ? static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) >> ? { >> ????? struct drm_i915_private *i915 = gt->i915; >> -??? struct intel_device_info *info = mkwrite_device_info(i915); >> +??? struct intel_gt_info *info = >->info; >> ????? struct intel_uncore *uncore = gt->uncore; >> ????? unsigned int logical_vdbox = 0; >> ????? unsigned int i; >> @@ -467,6 +467,8 @@ static intel_engine_mask_t init_engine_mask(struct >> intel_gt *gt) >> ????? u16 vdbox_mask; >> ????? u16 vebox_mask; >> +??? info->engine_mask = INTEL_INFO(i915)->max_engine_mask; >> + >> ????? if (INTEL_GEN(i915) < 11) >> ????????? return info->engine_mask; >> @@ -494,7 +496,7 @@ static intel_engine_mask_t init_engine_mask(struct >> intel_gt *gt) >> ?????????? * In TGL each VDBOX has access to an SFC. >> ?????????? */ >> ????????? if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0) >> -??????????? RUNTIME_INFO(i915)->vdbox_sfc_access |= BIT(i); >> +??????????? gt->info.vdbox_sfc_access |= BIT(i); >> ????? } >> ????? drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n", >> ????????? vdbox_mask, VDBOX_MASK(gt)); >> @@ -527,7 +529,6 @@ static intel_engine_mask_t init_engine_mask(struct >> intel_gt *gt) >> ? int intel_engines_init_mmio(struct intel_gt *gt) >> ? { >> ????? struct drm_i915_private *i915 = gt->i915; >> -??? struct intel_device_info *device_info = mkwrite_device_info(i915); >> ????? const unsigned int engine_mask = init_engine_mask(gt); >> ????? unsigned int mask = 0; >> ????? unsigned int i; >> @@ -557,9 +558,9 @@ int intel_engines_init_mmio(struct intel_gt *gt) >> ?????? * engines. >> ?????? */ >> ????? if (drm_WARN_ON(&i915->drm, mask != engine_mask)) >> -??????? device_info->engine_mask = mask; >> +??????? gt->info.engine_mask = mask; >> -??? RUNTIME_INFO(i915)->num_engines = hweight32(mask); >> +??? gt->info.num_engines = hweight32(mask); >> ????? intel_gt_check_and_clear_faults(gt); >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c >> b/drivers/gpu/drm/i915/gt/intel_gt.c >> index ebc29b6ee86c..d0ae1cb5c7c9 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c >> @@ -642,3 +642,9 @@ void intel_gt_driver_late_release(struct intel_gt >> *gt) >> ????? intel_gt_fini_timelines(gt); >> ????? intel_engines_free(gt); >> ? } >> + >> +void intel_gt_info_print(const struct intel_gt_info *info, >> +???????????? struct drm_printer *p) >> +{ >> +??? drm_printf(p, "available engines: %x\n", info->engine_mask); >> +} >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h >> b/drivers/gpu/drm/i915/gt/intel_gt.h >> index 4fac043750aa..15142e2a3b22 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt.h >> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h >> @@ -11,6 +11,7 @@ >> ? #include "intel_reset.h" >> ? struct drm_i915_private; >> +struct drm_printer; >> ? #define GT_TRACE(gt, fmt, ...) do {??????????????????? \ >> ????? const struct intel_gt *gt__ __maybe_unused = (gt);??????? \ >> @@ -68,4 +69,7 @@ static inline bool intel_gt_has_init_error(const >> struct intel_gt *gt) >> ????? return test_bit(I915_WEDGED_ON_INIT, >->reset.flags); >> ? } >> +void intel_gt_info_print(const struct intel_gt_info *info, >> +???????????? struct drm_printer *p); >> + >> ? #endif /* __INTEL_GT_H__ */ >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h >> b/drivers/gpu/drm/i915/gt/intel_gt_types.h >> index 0cc1d6b185dc..bb7551867c00 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h >> @@ -109,6 +109,14 @@ struct intel_gt { >> ????? struct intel_gt_buffer_pool buffer_pool; >> ????? struct i915_vma *scratch; >> + >> +??? struct intel_gt_info { >> +??????? intel_engine_mask_t engine_mask; >> +??????? u8 num_engines; >> + >> +??????? /* Media engine access to SFC per instance */ >> +??????? u8 vdbox_sfc_access; >> +??? } info; >> ? }; >> ? enum intel_gt_scratch_field { >> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c >> b/drivers/gpu/drm/i915/gt/intel_reset.c >> index 0156f1f5c736..952cd6e9b88e 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_reset.c >> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c >> @@ -342,7 +342,7 @@ static int gen6_reset_engines(struct intel_gt *gt, >> ? static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask) >> ? { >> ????? struct intel_uncore *uncore = engine->uncore; >> -??? u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access; >> +??? u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; >> ????? i915_reg_t sfc_forced_lock, sfc_forced_lock_ack; >> ????? u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit; >> ????? i915_reg_t sfc_usage; >> @@ -417,7 +417,7 @@ static int gen11_lock_sfc(struct intel_engine_cs >> *engine, u32 *hw_mask) >> ? static void gen11_unlock_sfc(struct intel_engine_cs *engine) >> ? { >> ????? struct intel_uncore *uncore = engine->uncore; >> -??? u8 vdbox_sfc_access = RUNTIME_INFO(engine->i915)->vdbox_sfc_access; >> +??? u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access; >> ????? i915_reg_t sfc_forced_lock; >> ????? u32 sfc_forced_lock_bit; >> @@ -1246,7 +1246,7 @@ void intel_gt_handle_error(struct intel_gt *gt, >> ?????? */ >> ????? wakeref = intel_runtime_pm_get(gt->uncore->rpm); >> -??? engine_mask &= INTEL_INFO(gt->i915)->engine_mask; >> +??? engine_mask &= gt->info.engine_mask; >> ????? if (flags & I915_ERROR_CAPTURE) { >> ????????? i915_capture_error_state(gt->i915); >> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> index 68a08486fc87..b09b83deecef 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> @@ -649,7 +649,7 @@ static inline int mi_set_context(struct >> i915_request *rq, >> ????? struct drm_i915_private *i915 = engine->i915; >> ????? enum intel_engine_id id; >> ????? const int num_engines = >> -??????? IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; >> +??????? IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; >> ????? bool force_restore = false; >> ????? int len; >> ????? u32 *cs; >> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c >> b/drivers/gpu/drm/i915/gt/selftest_lrc.c >> index daa4aabab9a7..b3678b5f9655 100644 >> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c >> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c >> @@ -963,7 +963,7 @@ slice_semaphore_queue(struct intel_engine_cs *outer, >> ????????? goto out; >> ????? if (i915_request_wait(head, 0, >> -????????????????? 2 * RUNTIME_INFO(outer->i915)->num_engines * (count >> + 2) * (count + 3)) < 0) { >> +????????????????? 2 * engine->gt->info.num_engines * (count + 2) * >> (count + 3)) < 0) { >> ????????? pr_err("Failed to slice along semaphore chain of length (%d, >> %d)!\n", >> ???????????????? count, n); >> ????????? GEM_TRACE_DUMP(); >> @@ -3569,8 +3569,7 @@ static int smoke_crescendo(struct preempt_smoke >> *smoke, unsigned int flags) >> ????? } >> ????? pr_info("Submitted %lu crescendo:%x requests across %d engines >> and %d contexts\n", >> -??????? count, flags, >> -??????? RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext); >> +??????? count, flags, smoke->gt->info.num_engines, smoke->ncontext); >> ????? return 0; >> ? } >> @@ -3597,8 +3596,7 @@ static int smoke_random(struct preempt_smoke >> *smoke, unsigned int flags) >> ????? } while (count < smoke->ncontext && !__igt_timeout(end_time, >> NULL)); >> ????? pr_info("Submitted %lu random:%x requests across %d engines and >> %d contexts\n", >> -??????? count, flags, >> -??????? RUNTIME_INFO(smoke->gt->i915)->num_engines, smoke->ncontext); >> +??????? count, flags, smoke->gt->info.num_engines, smoke->ncontext); >> ????? return 0; >> ? } >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> index fbdd6b0677db..c10ae1660e53 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> @@ -106,7 +106,7 @@ static void __guc_ads_init(struct intel_guc *guc) >> ????? blob->system_info.vdbox_enable_mask = VDBOX_MASK(gt); >> ????? blob->system_info.vebox_enable_mask = VEBOX_MASK(gt); >> -??? blob->system_info.vdbox_sfc_support_mask = >> RUNTIME_INFO(dev_priv)->vdbox_sfc_access; >> +??? blob->system_info.vdbox_sfc_support_mask = >> gt->info.vdbox_sfc_access; >> ????? base = intel_guc_ggtt_offset(guc, guc->ads_vma); >> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c >> b/drivers/gpu/drm/i915/gvt/handlers.c >> index ddefc52f6e09..e047a4950f5f 100644 >> --- a/drivers/gpu/drm/i915/gvt/handlers.c >> +++ b/drivers/gpu/drm/i915/gvt/handlers.c >> @@ -347,7 +347,7 @@ static int gdrst_mmio_write(struct intel_vgpu >> *vgpu, unsigned int offset, >> ????????????? gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); >> ????????????? vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; >> ????????? } >> -??????? engine_mask &= INTEL_INFO(vgpu->gvt->gt->i915)->engine_mask; >> +??????? engine_mask &= vgpu->gvt->gt->info.engine_mask; >> ????? } >> ????? /* vgpu_lock already hold by emulate mmio r/w */ >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >> b/drivers/gpu/drm/i915/i915_debugfs.c >> index 8594a8ef08ce..cad1620d2a7e 100644 >> --- a/drivers/gpu/drm/i915/i915_debugfs.c >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c >> @@ -34,6 +34,7 @@ >> ? #include "gem/i915_gem_context.h" >> ? #include "gt/intel_gt_buffer_pool.h" >> ? #include "gt/intel_gt_clock_utils.h" >> +#include "gt/intel_gt.h" >> ? #include "gt/intel_gt_pm.h" >> ? #include "gt/intel_gt_requests.h" >> ? #include "gt/intel_reset.h" >> @@ -61,6 +62,7 @@ static int i915_capabilities(struct seq_file *m, >> void *data) >> ????? intel_device_info_print_static(INTEL_INFO(i915), &p); >> ????? intel_device_info_print_runtime(RUNTIME_INFO(i915), &p); >> +??? intel_gt_info_print(&i915->gt.info, &p); >> ????? intel_driver_caps_print(&i915->caps, &p); >> ????? kernel_param_lock(THIS_MODULE); >> diff --git a/drivers/gpu/drm/i915/i915_drv.c >> b/drivers/gpu/drm/i915/i915_drv.c >> index 611287353420..67789df42be8 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -886,6 +886,7 @@ static void i915_welcome_messages(struct >> drm_i915_private *dev_priv) >> ????????? intel_device_info_print_static(INTEL_INFO(dev_priv), &p); >> ????????? intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); >> +??????? intel_gt_info_print(&dev_priv->gt.info, &p); >> ????? } >> ????? if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) >> diff --git a/drivers/gpu/drm/i915/i915_drv.h >> b/drivers/gpu/drm/i915/i915_drv.h >> index 17cad4e2cb9c..fa01bf0929e0 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -1254,7 +1254,7 @@ static inline struct drm_i915_private >> *pdev_to_i915(struct pci_dev *pdev) >> ? /* Iterator over subset of engines selected by mask */ >> ? #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ >> -??? for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \ >> +??? for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ >> ?????????? (tmp__) ? \ >> ?????????? ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ >> ?????????? 0;) >> @@ -1561,12 +1561,12 @@ IS_SUBPLATFORM(const struct drm_i915_private >> *i915, >> ? #define IS_GEN9_BC(dev_priv)??? (IS_GEN(dev_priv, 9) && >> !IS_LP(dev_priv)) >> ? #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) >> -#define HAS_ENGINE(gt, id) >> __HAS_ENGINE(INTEL_INFO((gt)->i915)->engine_mask, id) >> +#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) >> ? #define ENGINE_INSTANCES_MASK(gt, first, count) ({??????? \ >> ????? unsigned int first__ = (first);??????????????????? \ >> ????? unsigned int count__ = (count);??????????????????? \ >> -??? (INTEL_INFO((gt)->i915)->engine_mask &??????????????? \ >> +??? ((gt)->info.engine_mask &??????????????????????? \ >> ?????? GENMASK(first__ + count__ - 1, first__)) >> first__;??????? \ >> ? }) >> ? #define VDBOX_MASK(gt) \ >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c >> b/drivers/gpu/drm/i915/i915_gpu_error.c >> index 866166ada10e..9cb9aa39c33d 100644 >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c >> @@ -42,6 +42,7 @@ >> ? #include "gem/i915_gem_context.h" >> ? #include "gem/i915_gem_lmem.h" >> +#include "gt/intel_gt.h" >> ? #include "gt/intel_gt_pm.h" >> ? #include "i915_drv.h" >> @@ -619,16 +620,15 @@ static void print_error_vma(struct >> drm_i915_error_state_buf *m, >> ? } >> ? static void err_print_capabilities(struct drm_i915_error_state_buf *m, >> -?????????????????? const struct intel_device_info *info, >> -?????????????????? const struct intel_runtime_info *runtime, >> -?????????????????? const struct intel_driver_caps *caps) >> +?????????????????? struct i915_gpu_coredump *error) >> ? { >> ????? struct drm_printer p = i915_error_printer(m); >> -??? intel_device_info_print_static(info, &p); >> -??? intel_device_info_print_runtime(runtime, &p); >> -??? intel_device_info_print_topology(&runtime->sseu, &p); >> -??? intel_driver_caps_print(caps, &p); >> +??? intel_device_info_print_static(&error->device_info, &p); >> +??? intel_device_info_print_runtime(&error->runtime_info, &p); >> +??? intel_device_info_print_topology(&error->runtime_info.sseu, &p); >> +??? intel_gt_info_print(&error->gt->info, &p); >> +??? intel_driver_caps_print(&error->driver_caps, &p); >> ? } >> ? static void err_print_params(struct drm_i915_error_state_buf *m, >> @@ -798,8 +798,7 @@ static void __err_print_to_sgl(struct >> drm_i915_error_state_buf *m, >> ????? if (error->display) >> ????????? intel_display_print_error_state(m, error->display); >> -??? err_print_capabilities(m, &error->device_info, &error->runtime_info, >> -?????????????????? &error->driver_caps); >> +??? err_print_capabilities(m, error); >> ????? err_print_params(m, &error->params); >> ? } >> @@ -1630,6 +1629,11 @@ static void gt_record_regs(struct >> intel_gt_coredump *gt) >> ????? gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); >> ? } >> +static void gt_record_info(struct intel_gt_coredump *gt) >> +{ >> +??? memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); >> +} >> + >> ? /* >> ?? * Generate a semi-unique error code. The code is not meant to have >> meaning, The >> ?? * code's only purpose is to try to prevent false duplicated bug >> reports by >> @@ -1808,6 +1812,7 @@ struct i915_gpu_coredump >> *i915_gpu_coredump(struct drm_i915_private *i915) >> ????????????? return ERR_PTR(-ENOMEM); >> ????????? } >> +??????? gt_record_info(error->gt); >> ????????? gt_record_engines(error->gt, compress); >> ????????? if (INTEL_INFO(i915)->has_gt_uc) >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h >> b/drivers/gpu/drm/i915/i915_gpu_error.h >> index 76b80fbfb7e9..0220b0992808 100644 >> --- a/drivers/gpu/drm/i915/i915_gpu_error.h >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h >> @@ -15,6 +15,7 @@ >> ? #include <drm/drm_mm.h> >> ? #include "gt/intel_engine.h" >> +#include "gt/intel_gt_types.h" >> ? #include "gt/uc/intel_uc_fw.h" >> ? #include "intel_device_info.h" >> @@ -118,6 +119,8 @@ struct intel_gt_coredump { >> ????? bool awake; >> ????? bool simulated; >> +??? struct intel_gt_info info; >> + >> ????? /* Generic register state */ >> ????? u32 eir; >> ????? u32 pgtbl_er; >> diff --git a/drivers/gpu/drm/i915/i915_pci.c >> b/drivers/gpu/drm/i915/i915_pci.c >> index e5fdf17cd9cd..7658025a791f 100644 >> --- a/drivers/gpu/drm/i915/i915_pci.c >> +++ b/drivers/gpu/drm/i915/i915_pci.c >> @@ -168,7 +168,7 @@ >> ????? .gpu_reset_clobbers_display = true, \ >> ????? .hws_needs_physical = 1, \ >> ????? .unfenced_needs_alignment = 1, \ >> -??? .engine_mask = BIT(RCS0), \ >> +??? .max_engine_mask = BIT(RCS0), \ >> ????? .has_snoop = true, \ >> ????? .has_coherent_ggtt = false, \ >> ????? .dma_mask_size = 32, \ >> @@ -188,7 +188,7 @@ >> ????? .gpu_reset_clobbers_display = true, \ >> ????? .hws_needs_physical = 1, \ >> ????? .unfenced_needs_alignment = 1, \ >> -??? .engine_mask = BIT(RCS0), \ >> +??? .max_engine_mask = BIT(RCS0), \ >> ????? .has_snoop = true, \ >> ????? .has_coherent_ggtt = false, \ >> ????? .dma_mask_size = 32, \ >> @@ -225,7 +225,7 @@ static const struct intel_device_info i865g_info = { >> ????? .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ >> ????? .display.has_gmch = 1, \ >> ????? .gpu_reset_clobbers_display = true, \ >> -??? .engine_mask = BIT(RCS0), \ >> +??? .max_engine_mask = BIT(RCS0), \ >> ????? .has_snoop = true, \ >> ????? .has_coherent_ggtt = true, \ >> ????? .dma_mask_size = 32, \ >> @@ -316,7 +316,7 @@ static const struct intel_device_info pnv_m_info = { >> ????? .display.has_hotplug = 1, \ >> ????? .display.has_gmch = 1, \ >> ????? .gpu_reset_clobbers_display = true, \ >> -??? .engine_mask = BIT(RCS0), \ >> +??? .max_engine_mask = BIT(RCS0), \ >> ????? .has_snoop = true, \ >> ????? .has_coherent_ggtt = true, \ >> ????? .dma_mask_size = 36, \ >> @@ -348,7 +348,7 @@ static const struct intel_device_info i965gm_info = { >> ? static const struct intel_device_info g45_info = { >> ????? GEN4_FEATURES, >> ????? PLATFORM(INTEL_G45), >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0), >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0), >> ????? .gpu_reset_clobbers_display = false, >> ? }; >> @@ -358,7 +358,7 @@ static const struct intel_device_info gm45_info = { >> ????? .is_mobile = 1, >> ????? .display.has_fbc = 1, >> ????? .display.supports_tv = 1, >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0), >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0), >> ????? .gpu_reset_clobbers_display = false, >> ? }; >> @@ -367,7 +367,7 @@ static const struct intel_device_info gm45_info = { >> ????? .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \ >> ????? .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ >> ????? .display.has_hotplug = 1, \ >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0), \ >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0), \ >> ????? .has_snoop = true, \ >> ????? .has_coherent_ggtt = true, \ >> ????? /* ilk does support rc6, but we do not implement [power] >> contexts */ \ >> @@ -397,7 +397,7 @@ static const struct intel_device_info ilk_m_info = { >> ????? .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ >> ????? .display.has_hotplug = 1, \ >> ????? .display.has_fbc = 1, \ >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ >> ????? .has_coherent_ggtt = true, \ >> ????? .has_llc = 1, \ >> ????? .has_rc6 = 1, \ >> @@ -448,7 +448,7 @@ static const struct intel_device_info >> snb_m_gt2_info = { >> ????? .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | >> BIT(TRANSCODER_C), \ >> ????? .display.has_hotplug = 1, \ >> ????? .display.has_fbc = 1, \ >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \ >> ????? .has_coherent_ggtt = true, \ >> ????? .has_llc = 1, \ >> ????? .has_rc6 = 1, \ >> @@ -519,7 +519,7 @@ static const struct intel_device_info vlv_info = { >> ????? .ppgtt_size = 31, >> ????? .has_snoop = true, >> ????? .has_coherent_ggtt = false, >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), >> ????? .display_mmio_offset = VLV_DISPLAY_BASE, >> ????? I9XX_PIPE_OFFSETS, >> ????? I9XX_CURSOR_OFFSETS, >> @@ -530,7 +530,7 @@ static const struct intel_device_info vlv_info = { >> ? #define G75_FEATURES? \ >> ????? GEN7_FEATURES, \ >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ >> ????? .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ >> ????????? BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ >> ????? .display.has_ddi = 1, \ >> @@ -597,7 +597,7 @@ static const struct intel_device_info >> bdw_rsvd_info = { >> ? static const struct intel_device_info bdw_gt3_info = { >> ????? BDW_PLATFORM, >> ????? .gt = 3, >> -??? .engine_mask = >> +??? .max_engine_mask = >> ????????? BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), >> ? }; >> @@ -608,7 +608,7 @@ static const struct intel_device_info chv_info = { >> ????? .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | >> BIT(TRANSCODER_C), >> ????? .display.has_hotplug = 1, >> ????? .is_lp = 1, >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), >> ????? .has_64bit_reloc = 1, >> ????? .has_runtime_pm = 1, >> ????? .has_rc6 = 1, >> @@ -661,7 +661,7 @@ static const struct intel_device_info skl_gt2_info >> = { >> ? #define SKL_GT3_PLUS_PLATFORM \ >> ????? SKL_PLATFORM, \ >> -??? .engine_mask = \ >> +??? .max_engine_mask = \ >> ????????? BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) >> @@ -680,7 +680,7 @@ static const struct intel_device_info skl_gt4_info >> = { >> ????? .is_lp = 1, \ >> ????? .num_supported_dbuf_slices = 1, \ >> ????? .display.has_hotplug = 1, \ >> -??? .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ >> +??? .max_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ >> ????? .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ >> ????? .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ >> ????????? BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \ >> @@ -743,7 +743,7 @@ static const struct intel_device_info kbl_gt2_info >> = { >> ? static const struct intel_device_info kbl_gt3_info = { >> ????? KBL_PLATFORM, >> ????? .gt = 3, >> -??? .engine_mask = >> +??? .max_engine_mask = >> ????????? BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), >> ? }; >> @@ -764,7 +764,7 @@ static const struct intel_device_info cfl_gt2_info >> = { >> ? static const struct intel_device_info cfl_gt3_info = { >> ????? CFL_PLATFORM, >> ????? .gt = 3, >> -??? .engine_mask = >> +??? .max_engine_mask = >> ????????? BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), >> ? }; >> @@ -833,7 +833,7 @@ static const struct intel_device_info cnl_info = { >> ? static const struct intel_device_info icl_info = { >> ????? GEN11_FEATURES, >> ????? PLATFORM(INTEL_ICELAKE), >> -??? .engine_mask = >> +??? .max_engine_mask = >> ????????? BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), >> ? }; >> @@ -841,7 +841,7 @@ static const struct intel_device_info ehl_info = { >> ????? GEN11_FEATURES, >> ????? PLATFORM(INTEL_ELKHARTLAKE), >> ????? .require_force_probe = 1, >> -??? .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), >> +??? .max_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), >> ????? .ppgtt_size = 36, >> ? }; >> @@ -877,7 +877,7 @@ static const struct intel_device_info tgl_info = { >> ????? GEN12_FEATURES, >> ????? PLATFORM(INTEL_TIGERLAKE), >> ????? .display.has_modular_fia = 1, >> -??? .engine_mask = >> +??? .max_engine_mask = >> ????????? BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), >> ? }; >> @@ -890,7 +890,7 @@ static const struct intel_device_info rkl_info = { >> ????????? BIT(TRANSCODER_C), >> ????? .require_force_probe = 1, >> ????? .display.has_psr_hw_tracking = 0, >> -??? .engine_mask = >> +??? .max_engine_mask = >> ????????? BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), >> ? }; >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c >> b/drivers/gpu/drm/i915/intel_device_info.c >> index 92ebea35c752..a362a66fce11 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.c >> +++ b/drivers/gpu/drm/i915/intel_device_info.c >> @@ -92,7 +92,6 @@ static const char *iommu_name(void) >> ? void intel_device_info_print_static(const struct intel_device_info >> *info, >> ????????????????????? struct drm_printer *p) >> ? { >> -??? drm_printf(p, "engines: %x\n", info->engine_mask); >> ????? drm_printf(p, "gen: %d\n", info->gen); >> ????? drm_printf(p, "gt: %d\n", info->gt); >> ????? drm_printf(p, "iommu: %s\n", iommu_name()); >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h >> b/drivers/gpu/drm/i915/intel_device_info.h >> index fa60fdc1d75a..f03ed95af190 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.h >> +++ b/drivers/gpu/drm/i915/intel_device_info.h >> @@ -157,7 +157,7 @@ struct intel_device_info { >> ????? u8 gen; >> ????? u8 gt; /* GT number, 0 if undefined */ >> -??? intel_engine_mask_t engine_mask; /* Engines supported by the HW */ >> +??? intel_engine_mask_t max_engine_mask; /* Engines supported by the >> HW */ >> ????? enum intel_platform platform; >> @@ -219,8 +219,6 @@ struct intel_runtime_info { >> ????? u8 num_sprites[I915_MAX_PIPES]; >> ????? u8 num_scalers[I915_MAX_PIPES]; >> -??? u8 num_engines; >> - >> ????? /* Slice/subslice/EU info */ >> ????? struct sseu_dev_info sseu; >> @@ -228,9 +226,6 @@ struct intel_runtime_info { >> ????? u32 cs_timestamp_frequency_hz; >> ????? u32 cs_timestamp_period_ns; >> - >> -??? /* Media engine access to SFC per instance */ >> -??? u8 vdbox_sfc_access; >> ? }; >> ? struct intel_driver_caps { >> diff --git a/drivers/gpu/drm/i915/intel_uncore.c >> b/drivers/gpu/drm/i915/intel_uncore.c >> index bd4b45191f7b..f5548875836c 100644 >> --- a/drivers/gpu/drm/i915/intel_uncore.c >> +++ b/drivers/gpu/drm/i915/intel_uncore.c >> @@ -1530,7 +1530,7 @@ static int intel_uncore_fw_domains_init(struct >> intel_uncore *uncore) >> ????? if (INTEL_GEN(i915) >= 11) { >> ????????? /* we'll prune the domains of missing engines later */ >> -??????? intel_engine_mask_t emask = INTEL_INFO(i915)->engine_mask; >> +??????? intel_engine_mask_t emask = INTEL_INFO(i915)->max_engine_mask; >> ????????? int i; >> ????????? uncore->funcs.force_wake_get = fw_domains_get_with_fallback; >> diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c >> b/drivers/gpu/drm/i915/selftests/i915_request.c >> index 9271aad7f779..57dd6f5122ee 100644 >> --- a/drivers/gpu/drm/i915/selftests/i915_request.c >> +++ b/drivers/gpu/drm/i915/selftests/i915_request.c >> @@ -1454,7 +1454,7 @@ static int live_breadcrumbs_smoketest(void *arg) >> ????????? idx++; >> ????? } >> ????? pr_info("Completed %lu waits for %lu fences across %d engines >> and %d cpus\n", >> -??????? num_waits, num_fences, RUNTIME_INFO(i915)->num_engines, ncpus); >> +??????? num_waits, num_fences, idx, ncpus); >> ????? ret = igt_live_test_end(&live) ?: ret; >> ? out_contexts: >> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c >> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c >> index 9b105b811f1f..0916efa31889 100644 >> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c >> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c >> @@ -190,7 +190,8 @@ struct drm_i915_private *mock_gem_device(void) >> ????? mock_init_ggtt(i915, &i915->ggtt); >> ????? i915->gt.vm = i915_vm_get(&i915->ggtt.vm); >> -??? mkwrite_device_info(i915)->engine_mask = BIT(0); >> +??? mkwrite_device_info(i915)->max_engine_mask = BIT(0); >> +??? i915->gt.info.engine_mask = BIT(0); >> ????? i915->gt.engine[RCS0] = mock_engine(i915, "mock", RCS0); >> ????? if (!i915->gt.engine[RCS0]) >> > > Only thing which looks a bit sub-optimalis the name "max_engine_mask", > but maybe it is just me, that max and masks do not go well together. > Only alternative I have for the moment is platform_engine_mask? Or the > usual double underscore approach. Either way: > I wasn't fully convinced of max_engine_mask either, buy I had no better ideas :) platform_engine_mask sounds good to me, I'll use that. Daniele > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> > > Regards, > > Tvrtko From daniele.ceraolospurio at intel.com Fri Jun 26 16:49:35 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Fri, 26 Jun 2020 09:49:35 -0700 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/sseu: Move sseu_info under gt_info In-Reply-To: <689ef3ca-284d-6f3c-1ee6-4abab6a536a2@linux.intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-8-daniele.ceraolospurio@intel.com> <689ef3ca-284d-6f3c-1ee6-4abab6a536a2@linux.intel.com> Message-ID: <1f9f05ee-b93e-4ea8-a2c4-3551f61a0e3c@intel.com> On 6/26/20 8:22 AM, Tvrtko Ursulin wrote: > > On 26/06/2020 00:42, Daniele Ceraolo Spurio wrote: >> From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota at intel.com> >> >> SSEUs are a GT capability, so track them under gt_info. >> >> Signed-off-by: Venkata Sandeep Dhanalakota >> <venkata.s.dhanalakota at intel.com> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> >> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com> >> Cc: Andi Shyti <andi.shyti at intel.com> >> --- >> ? drivers/gpu/drm/i915/gem/i915_gem_context.c?? |? 7 ++++--- >> ? drivers/gpu/drm/i915/gem/i915_gem_context.h?? |? 2 +- >> ? .../drm/i915/gem/selftests/i915_gem_context.c |? 5 ++++- >> ? drivers/gpu/drm/i915/gt/intel_context_sseu.c? |? 2 +- >> ? drivers/gpu/drm/i915/gt/intel_engine_cs.c???? |? 4 ++-- >> ? drivers/gpu/drm/i915/gt/intel_gt.c??????????? |? 2 ++ >> ? drivers/gpu/drm/i915/gt/intel_gt_types.h????? |? 3 +++ >> ? drivers/gpu/drm/i915/gt/intel_lrc.c?????????? |? 2 +- >> ? drivers/gpu/drm/i915/gt/intel_rps.c?????????? |? 3 ++- >> ? drivers/gpu/drm/i915/gt/intel_sseu.c????????? | 19 ++++++++++--------- >> ? drivers/gpu/drm/i915/gt/intel_sseu.h????????? |? 2 +- >> ? drivers/gpu/drm/i915/gt/intel_workarounds.c?? |? 8 ++++---- >> ? drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c??? |? 3 +-- >> ? drivers/gpu/drm/i915/i915_debugfs.c?????????? | 10 +++++----- > > Add SSEU to debugfs_gt.c / debugfs_sseu.c ? I'd prefer not to add it in this patch, to keep it focused on the move. I'll add an extra patch with the debugfs when I send v2 of the series. Do you think it is worth having an sseu file by itself or better to have an info/capabilities one printing both the gt_info and the topology? Daniele > > Regards, > > Tvrtko > >> ? drivers/gpu/drm/i915/i915_getparam.c????????? |? 2 +- >> ? drivers/gpu/drm/i915/i915_gpu_error.c???????? |? 4 ++-- >> ? drivers/gpu/drm/i915/i915_perf.c????????????? |? 9 ++++----- >> ? drivers/gpu/drm/i915/i915_query.c???????????? |? 2 +- >> ? drivers/gpu/drm/i915/intel_device_info.c????? |? 3 --- >> ? drivers/gpu/drm/i915/intel_device_info.h????? |? 3 --- >> ? 20 files changed, 49 insertions(+), 46 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c >> b/drivers/gpu/drm/i915/gem/i915_gem_context.c >> index 5c13809dc3c8..4fc641d5cb68 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c >> @@ -1399,11 +1399,12 @@ static int get_ringsize(struct >> i915_gem_context *ctx, >> ? } >> ? int >> -i915_gem_user_to_context_sseu(struct drm_i915_private *i915, >> +i915_gem_user_to_context_sseu(struct intel_gt *gt, >> ??????????????????? const struct drm_i915_gem_context_param_sseu *user, >> ??????????????????? struct intel_sseu *context) >> ? { >> -??? const struct sseu_dev_info *device = &RUNTIME_INFO(i915)->sseu; >> +??? const struct sseu_dev_info *device = >->info.sseu; >> +??? struct drm_i915_private *i915 = gt->i915; >> ????? /* No zeros in any field. */ >> ????? if (!user->slice_mask || !user->subslice_mask || >> @@ -1536,7 +1537,7 @@ static int set_sseu(struct i915_gem_context *ctx, >> ????????? goto out_ce; >> ????? } >> -??? ret = i915_gem_user_to_context_sseu(i915, &user_sseu, &sseu); >> +??? ret = i915_gem_user_to_context_sseu(ce->engine->gt, &user_sseu, >> &sseu); >> ????? if (ret) >> ????????? goto out_ce; >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h >> b/drivers/gpu/drm/i915/gem/i915_gem_context.h >> index 3702b2fb27ab..a133f92bbedb 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h >> @@ -225,7 +225,7 @@ i915_gem_engines_iter_next(struct >> i915_gem_engines_iter *it); >> ? struct i915_lut_handle *i915_lut_handle_alloc(void); >> ? void i915_lut_handle_free(struct i915_lut_handle *lut); >> -int i915_gem_user_to_context_sseu(struct drm_i915_private *i915, >> +int i915_gem_user_to_context_sseu(struct intel_gt *gt, >> ??????????????????? const struct drm_i915_gem_context_param_sseu *user, >> ??????????????????? struct intel_sseu *context); >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> index b81978890641..7ffc3c751432 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> @@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915, >> ????? int inst = 0; >> ????? int ret = 0; >> -??? if (INTEL_GEN(i915) < 9 || !RUNTIME_INFO(i915)->sseu.has_slice_pg) >> +??? if (INTEL_GEN(i915) < 9) >> ????????? return 0; >> ????? if (flags & TEST_RESET) >> @@ -1255,6 +1255,9 @@ __igt_ctx_sseu(struct drm_i915_private *i915, >> ????????? if (hweight32(engine->sseu.slice_mask) < 2) >> ????????????? continue; >> +??????? if (!engine->gt->info.sseu.has_slice_pg) >> +??????????? continue; >> + >> ????????? /* >> ?????????? * Gen11 VME friendly power-gated configuration with >> ?????????? * half enabled sub-slices. >> diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c >> b/drivers/gpu/drm/i915/gt/intel_context_sseu.c >> index 27ae48049239..b9c8163978a3 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c >> +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c >> @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request >> *rq, >> ????? *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; >> ????? *cs++ = lower_32_bits(offset); >> ????? *cs++ = upper_32_bits(offset); >> -??? *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu); >> +??? *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); >> ????? intel_ring_advance(rq, cs); >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> index 3af58df3b13e..af08fdddd972 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> @@ -705,7 +705,7 @@ static int engine_setup_common(struct >> intel_engine_cs *engine) >> ????? /* Use the whole device by default */ >> ????? engine->sseu = >> -??????? intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu); >> +??????? intel_sseu_from_device_info(&engine->gt->info.sseu); >> ????? intel_engine_init_workarounds(engine); >> ????? intel_engine_init_whitelist(engine); >> @@ -1071,7 +1071,7 @@ void intel_engine_get_instdone(const struct >> intel_engine_cs *engine, >> ???????????????????? struct intel_instdone *instdone) >> ? { >> ????? struct drm_i915_private *i915 = engine->i915; >> -??? const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; >> +??? const struct sseu_dev_info *sseu = &engine->gt->info.sseu; >> ????? struct intel_uncore *uncore = engine->uncore; >> ????? u32 mmio_base = engine->mmio_base; >> ????? int slice; >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c >> b/drivers/gpu/drm/i915/gt/intel_gt.c >> index de95930f8627..b1748fa67eca 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt.c >> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c >> @@ -655,4 +655,6 @@ void intel_gt_info_print(const struct >> intel_gt_info *info, >> ?????????????? struct drm_printer *p) >> ? { >> ????? drm_printf(p, "available engines: %x\n", info->engine_mask); >> + >> +??? intel_sseu_dump(&info->sseu, p); >> ? } >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h >> b/drivers/gpu/drm/i915/gt/intel_gt_types.h >> index bb7551867c00..6d39a4a11bf3 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h >> @@ -116,6 +116,9 @@ struct intel_gt { >> ????????? /* Media engine access to SFC per instance */ >> ????????? u8 vdbox_sfc_access; >> + >> +??????? /* Slice/subslice/EU info */ >> +??????? struct sseu_dev_info sseu; >> ????? } info; >> ? }; >> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c >> b/drivers/gpu/drm/i915/gt/intel_lrc.c >> index e866b8d721ed..9e28b2f9df72 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >> @@ -3422,7 +3422,7 @@ __execlists_update_reg_state(const struct >> intel_context *ce, >> ????? /* RPCS */ >> ????? if (engine->class == RENDER_CLASS) { >> ????????? regs[CTX_R_PWR_CLK_STATE] = >> -??????????? intel_sseu_make_rpcs(engine->i915, &ce->sseu); >> +??????????? intel_sseu_make_rpcs(engine->gt, &ce->sseu); >> ????????? i915_oa_init_reg_state(ce, engine); >> ????? } >> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c >> b/drivers/gpu/drm/i915/gt/intel_rps.c >> index 296391deeb94..97ba14ad52e4 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_rps.c >> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c >> @@ -1062,11 +1062,12 @@ static bool gen6_rps_enable(struct intel_rps >> *rps) >> ? static int chv_rps_max_freq(struct intel_rps *rps) >> ? { >> ????? struct drm_i915_private *i915 = rps_to_i915(rps); >> +??? struct intel_gt *gt = rps_to_gt(rps); >> ????? u32 val; >> ????? val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); >> -??? switch (RUNTIME_INFO(i915)->sseu.eu_total) { >> +??? switch (gt->info.sseu.eu_total) { >> ????? case 8: >> ????????? /* (2 * 4) config */ >> ????????? val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT; >> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c >> b/drivers/gpu/drm/i915/gt/intel_sseu.c >> index 006f9118b319..e29f0785b3c5 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c >> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c >> @@ -130,7 +130,7 @@ static void gen11_compute_sseu_info(struct >> sseu_dev_info *sseu, >> ? static void gen12_sseu_info_init(struct intel_gt *gt) >> ? { >> -??? struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; >> +??? struct sseu_dev_info *sseu = >->info.sseu; >> ????? struct intel_uncore *uncore = gt->uncore; >> ????? u8 s_en; >> ????? u32 dss_en; >> @@ -165,7 +165,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt) >> ? static void gen11_sseu_info_init(struct intel_gt *gt) >> ? { >> -??? struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; >> +??? struct sseu_dev_info *sseu = >->info.sseu; >> ????? struct intel_uncore *uncore = gt->uncore; >> ????? u8 s_en; >> ????? u32 ss_en; >> @@ -194,7 +194,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt) >> ? static void gen10_sseu_info_init(struct intel_gt *gt) >> ? { >> ????? struct intel_uncore *uncore = gt->uncore; >> -??? struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; >> +??? struct sseu_dev_info *sseu = >->info.sseu; >> ????? const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); >> ????? int s, ss; >> ????? const int eu_mask = 0xff; >> @@ -270,7 +270,7 @@ static void gen10_sseu_info_init(struct intel_gt *gt) >> ? static void cherryview_sseu_info_init(struct intel_gt *gt) >> ? { >> -??? struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; >> +??? struct sseu_dev_info *sseu = >->info.sseu; >> ????? u32 fuse; >> ????? u8 subslice_mask = 0; >> @@ -327,7 +327,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) >> ? { >> ????? struct drm_i915_private *i915 = gt->i915; >> ????? struct intel_device_info *info = mkwrite_device_info(i915); >> -??? struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; >> +??? struct sseu_dev_info *sseu = >->info.sseu; >> ????? struct intel_uncore *uncore = gt->uncore; >> ????? int s, ss; >> ????? u32 fuse2, eu_disable, subslice_mask; >> @@ -431,7 +431,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) >> ? static void bdw_sseu_info_init(struct intel_gt *gt) >> ? { >> -??? struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; >> +??? struct sseu_dev_info *sseu = >->info.sseu; >> ????? struct intel_uncore *uncore = gt->uncore; >> ????? int s, ss; >> ????? u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ >> @@ -517,7 +517,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt) >> ? static void hsw_sseu_info_init(struct intel_gt *gt) >> ? { >> ????? struct drm_i915_private *i915 = gt->i915; >> -??? struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; >> +??? struct sseu_dev_info *sseu = >->info.sseu; >> ????? u32 fuse1; >> ????? u8 subslice_mask = 0; >> ????? int s, ss; >> @@ -602,10 +602,11 @@ void intel_sseu_info_init(struct intel_gt *gt) >> ????????? gen12_sseu_info_init(gt); >> ? } >> -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, >> +u32 intel_sseu_make_rpcs(struct intel_gt *gt, >> ?????????????? const struct intel_sseu *req_sseu) >> ? { >> -??? const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; >> +??? struct drm_i915_private *i915 = gt->i915; >> +??? const struct sseu_dev_info *sseu = >->info.sseu; >> ????? bool subslice_pg = sseu->has_subslice_pg; >> ????? u8 slices, subslices; >> ????? u32 rpcs = 0; >> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h >> b/drivers/gpu/drm/i915/gt/intel_sseu.h >> index f9c007f001e7..23ba6c2ebe70 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h >> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h >> @@ -98,7 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info >> *sseu, int slice, >> ? void intel_sseu_info_init(struct intel_gt *gt); >> -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, >> +u32 intel_sseu_make_rpcs(struct intel_gt *gt, >> ?????????????? const struct intel_sseu *req_sseu); >> ? void intel_sseu_dump(const struct sseu_dev_info *sseu, struct >> drm_printer *p); >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 2da366821dda..dbafd923e5a1 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -404,7 +404,7 @@ static void gen9_ctx_workarounds_init(struct >> intel_engine_cs *engine, >> ? static void skl_tune_iz_hashing(struct intel_engine_cs *engine, >> ????????????????? struct i915_wa_list *wal) >> ? { >> -??? struct drm_i915_private *i915 = engine->i915; >> +??? struct intel_gt *gt = engine->gt; >> ????? u8 vals[3] = { 0, 0, 0 }; >> ????? unsigned int i; >> @@ -415,7 +415,7 @@ static void skl_tune_iz_hashing(struct >> intel_engine_cs *engine, >> ?????????? * Only consider slices where one, and only one, subslice has 7 >> ?????????? * EUs >> ?????????? */ >> -??????? if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) >> +??????? if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) >> ????????????? continue; >> ????????? /* >> @@ -424,7 +424,7 @@ static void skl_tune_iz_hashing(struct >> intel_engine_cs *engine, >> ?????????? * >> ?????????? * ->??? 0 <= ss <= 3; >> ?????????? */ >> -??????? ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; >> +??????? ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; >> ????????? vals[i] = 3 - ss; >> ????? } >> @@ -1036,7 +1036,7 @@ cfl_gt_workarounds_init(struct drm_i915_private >> *i915, struct i915_wa_list *wal) >> ? static void >> ? wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) >> ? { >> -??? const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; >> +??? const struct sseu_dev_info *sseu = &i915->gt.info.sseu; >> ????? unsigned int slice, subslice; >> ????? u32 l3_en, mcr, mcr_mask; >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> index c10ae1660e53..d44061033f23 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c >> @@ -68,7 +68,6 @@ struct __guc_ads_blob { >> ? static void __guc_ads_init(struct intel_guc *guc) >> ? { >> ????? struct intel_gt *gt = guc_to_gt(guc); >> -??? struct drm_i915_private *dev_priv = gt->i915; >> ????? struct __guc_ads_blob *blob = guc->ads_blob; >> ????? const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + >> LR_HW_CONTEXT_SIZE; >> ????? u32 base; >> @@ -100,7 +99,7 @@ static void __guc_ads_init(struct intel_guc *guc) >> ????? } >> ????? /* System info */ >> -??? blob->system_info.slice_enabled = >> hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); >> +??? blob->system_info.slice_enabled = >> hweight8(gt->info.sseu.slice_mask); >> ????? blob->system_info.rcs_enabled = 1; >> ????? blob->system_info.bcs_enabled = 1; >> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c >> b/drivers/gpu/drm/i915/i915_debugfs.c >> index c893a82c2d99..16b012b5673d 100644 >> --- a/drivers/gpu/drm/i915/i915_debugfs.c >> +++ b/drivers/gpu/drm/i915/i915_debugfs.c >> @@ -1323,7 +1323,7 @@ static int i915_rcs_topology(struct seq_file *m, >> void *unused) >> ????? struct drm_i915_private *dev_priv = node_to_i915(m->private); >> ????? struct drm_printer p = drm_seq_file_printer(m); >> -??? intel_sseu_print_topology(&RUNTIME_INFO(dev_priv)->sseu, &p); >> +??? intel_sseu_print_topology(&dev_priv->gt.info.sseu, &p); >> ????? return 0; >> ? } >> @@ -1624,7 +1624,7 @@ static void gen10_sseu_device_status(struct >> drm_i915_private *dev_priv, >> ?????????????????????? struct sseu_dev_info *sseu) >> ? { >> ? #define SS_MAX 6 >> -??? const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); >> +??? const struct intel_gt_info *info = &dev_priv->gt.info; >> ????? u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; >> ????? int s, ss; >> @@ -1681,7 +1681,7 @@ static void gen9_sseu_device_status(struct >> drm_i915_private *dev_priv, >> ????????????????????? struct sseu_dev_info *sseu) >> ? { >> ? #define SS_MAX 3 >> -??? const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); >> +??? const struct intel_gt_info *info = &dev_priv->gt.info; >> ????? u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2]; >> ????? int s, ss; >> @@ -1739,7 +1739,7 @@ static void gen9_sseu_device_status(struct >> drm_i915_private *dev_priv, >> ? static void bdw_sseu_device_status(struct drm_i915_private *dev_priv, >> ???????????????????? struct sseu_dev_info *sseu) >> ? { >> -??? const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); >> +??? const struct intel_gt_info *info = &dev_priv->gt.info; >> ????? u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); >> ????? int s; >> @@ -1802,7 +1802,7 @@ static void i915_print_sseu_info(struct seq_file >> *m, bool is_available_info, >> ? static int i915_sseu_status(struct seq_file *m, void *unused) >> ? { >> ????? struct drm_i915_private *dev_priv = node_to_i915(m->private); >> -??? const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv); >> +??? const struct intel_gt_info *info = &dev_priv->gt.info; >> ????? struct sseu_dev_info sseu; >> ????? intel_wakeref_t wakeref; >> diff --git a/drivers/gpu/drm/i915/i915_getparam.c >> b/drivers/gpu/drm/i915/i915_getparam.c >> index 40390b2352b1..421613219ae9 100644 >> --- a/drivers/gpu/drm/i915/i915_getparam.c >> +++ b/drivers/gpu/drm/i915/i915_getparam.c >> @@ -12,7 +12,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void >> *data, >> ????????????? struct drm_file *file_priv) >> ? { >> ????? struct drm_i915_private *i915 = to_i915(dev); >> -??? const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; >> +??? const struct sseu_dev_info *sseu = &i915->gt.info.sseu; >> ????? drm_i915_getparam_t *param = data; >> ????? int value; >> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c >> b/drivers/gpu/drm/i915/i915_gpu_error.c >> index 99b4a0261b13..678ddec3237f 100644 >> --- a/drivers/gpu/drm/i915/i915_gpu_error.c >> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c >> @@ -426,7 +426,7 @@ static void err_compression_marker(struct >> drm_i915_error_state_buf *m) >> ? static void error_print_instdone(struct drm_i915_error_state_buf *m, >> ?????????????????? const struct intel_engine_coredump *ee) >> ? { >> -??? const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; >> +??? const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; >> ????? int slice; >> ????? int subslice; >> @@ -626,8 +626,8 @@ static void err_print_capabilities(struct >> drm_i915_error_state_buf *m, >> ????? intel_device_info_print_static(&error->device_info, &p); >> ????? intel_device_info_print_runtime(&error->runtime_info, &p); >> -??? intel_sseu_print_topology(&error->runtime_info.sseu, &p); >> ????? intel_gt_info_print(&error->gt->info, &p); >> +??? intel_sseu_print_topology(&error->gt->info.sseu, &p); >> ????? intel_driver_caps_print(&error->driver_caps, &p); >> ? } >> diff --git a/drivers/gpu/drm/i915/i915_perf.c >> b/drivers/gpu/drm/i915/i915_perf.c >> index 25329b7600c9..37631ce0699b 100644 >> --- a/drivers/gpu/drm/i915/i915_perf.c >> +++ b/drivers/gpu/drm/i915/i915_perf.c >> @@ -2196,7 +2196,7 @@ static int gen8_configure_context(struct >> i915_gem_context *ctx, >> ????????? if (!intel_context_pin_if_active(ce)) >> ????????????? continue; >> -??????? flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu); >> +??????? flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu); >> ????????? err = gen8_modify_context(ce, flex, count); >> ????????? intel_context_unpin(ce); >> @@ -2340,7 +2340,7 @@ oa_configure_all_contexts(struct >> i915_perf_stream *stream, >> ????????? if (engine->class != RENDER_CLASS) >> ????????????? continue; >> -??????? regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu); >> +??????? regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu); >> ????????? err = gen8_modify_self(ce, regs, num_regs, active); >> ????????? if (err) >> @@ -2740,8 +2740,7 @@ static void >> ? get_default_sseu_config(struct intel_sseu *out_sseu, >> ????????????? struct intel_engine_cs *engine) >> ? { >> -??? const struct sseu_dev_info *devinfo_sseu = >> -??????? &RUNTIME_INFO(engine->i915)->sseu; >> +??? const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu; >> ????? *out_sseu = intel_sseu_from_device_info(devinfo_sseu); >> @@ -2766,7 +2765,7 @@ get_sseu_config(struct intel_sseu *out_sseu, >> ????????? drm_sseu->engine.engine_instance != engine->uabi_instance) >> ????????? return -EINVAL; >> -??? return i915_gem_user_to_context_sseu(engine->i915, drm_sseu, >> out_sseu); >> +??? return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, >> out_sseu); >> ? } >> ? /** >> diff --git a/drivers/gpu/drm/i915/i915_query.c >> b/drivers/gpu/drm/i915/i915_query.c >> index c1ebda9b5627..fed337ad7b68 100644 >> --- a/drivers/gpu/drm/i915/i915_query.c >> +++ b/drivers/gpu/drm/i915/i915_query.c >> @@ -31,7 +31,7 @@ static int copy_query_item(void *query_hdr, size_t >> query_sz, >> ? static int query_topology_info(struct drm_i915_private *dev_priv, >> ???????????????????? struct drm_i915_query_item *query_item) >> ? { >> -??? const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; >> +??? const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu; >> ????? struct drm_i915_query_topology_info topo; >> ????? u32 slice_length, subslice_length, eu_length, total_length; >> ????? int ret; >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c >> b/drivers/gpu/drm/i915/intel_device_info.c >> index d8daf224cbd3..3f5dc37d2b7c 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.c >> +++ b/drivers/gpu/drm/i915/intel_device_info.c >> @@ -29,7 +29,6 @@ >> ? #include "display/intel_de.h" >> ? #include "intel_device_info.h" >> ? #include "i915_drv.h" >> -#include "gt/intel_sseu.h" >> ? #define PLATFORM_NAME(x) [INTEL_##x] = #x >> ? static const char * const platform_names[] = { >> @@ -115,8 +114,6 @@ void intel_device_info_print_static(const struct >> intel_device_info *info, >> ? void intel_device_info_print_runtime(const struct intel_runtime_info >> *info, >> ?????????????????????? struct drm_printer *p) >> ? { >> -??? intel_sseu_dump(&info->sseu, p); >> - >> ????? drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); >> ????? drm_printf(p, "CS timestamp frequency: %u Hz\n", >> ???????????? info->cs_timestamp_frequency_hz); >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h >> b/drivers/gpu/drm/i915/intel_device_info.h >> index ce2ccee9b49b..f6f897c06cc8 100644 >> --- a/drivers/gpu/drm/i915/intel_device_info.h >> +++ b/drivers/gpu/drm/i915/intel_device_info.h >> @@ -219,9 +219,6 @@ struct intel_runtime_info { >> ????? u8 num_sprites[I915_MAX_PIPES]; >> ????? u8 num_scalers[I915_MAX_PIPES]; >> -??? /* Slice/subslice/EU info */ >> -??? struct sseu_dev_info sseu; >> - >> ????? u32 rawclk_freq; >> ????? u32 cs_timestamp_frequency_hz; >> From chris at chris-wilson.co.uk Fri Jun 26 16:50:26 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 17:50:26 +0100 Subject: [Intel-gfx] [PATCH 4/7] drm/i915: Move the engine mask to intel_gt_info In-Reply-To: <f4549696-cc18-cf02-e2a3-c5d6c6970e80@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-5-daniele.ceraolospurio@intel.com> <78523c30-5aa6-ee94-722f-a0ed40b320b8@linux.intel.com> <f4549696-cc18-cf02-e2a3-c5d6c6970e80@intel.com> Message-ID: <159319022639.13600.1018762874880323717@build.alporthouse.com> Quoting Daniele Ceraolo Spurio (2020-06-26 17:44:20) > > > On 6/26/20 7:45 AM, Tvrtko Ursulin wrote: > > > > Only thing which looks a bit sub-optimalis the name "max_engine_mask", > > but maybe it is just me, that max and masks do not go well together. > > Only alternative I have for the moment is platform_engine_mask? Or the > > usual double underscore approach. Either way: > > > > I wasn't fully convinced of max_engine_mask either, buy I had no better > ideas :) > > platform_engine_mask sounds good to me, I'll use that. all_engine_mask full_engine_mask possible_engine_mask platform_engine_mask +1 for platform_engine_mask -Chris From daniele.ceraolospurio at intel.com Fri Jun 26 17:17:33 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Fri, 26 Jun 2020 10:17:33 -0700 Subject: [Intel-gfx] DG1 VRAM question In-Reply-To: <CAKi4VA+3oEPXnH-EKgKkxohf=7+jrDPy-fNfX6QvGBj7QsNYLw@mail.gmail.com> References: <CAPM=9tyx209haPSokJhA_qOi1PRhoVNPX3MTyNHsq68b=Y5W2A@mail.gmail.com> <CAKi4VA+3oEPXnH-EKgKkxohf=7+jrDPy-fNfX6QvGBj7QsNYLw@mail.gmail.com> Message-ID: <5d75a3d4-4bb2-3307-8d85-2addc64633f4@intel.com> On 6/26/20 12:14 AM, Lucas De Marchi wrote: > Cc Matt and Daniele > > On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied at gmail.com> wrote: >> >> I can't figure this out easily so I'd thought I'd just ask, but does >> DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of > > We'd need to go via lmem since there's no mappable aperture. There are > a few patches in tree for that > (see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not > available.")) but more missing. > To clarify, although the legacy aperture mapping that allowed the CPU to access memory via the GGTT for swizzling is gone, VRAM/LMEM is still cpu-mappable via pci bar. Will leave the questions about possible trashing to Matt as he's more familiar than me with how this works. Daniele > Lucas De Marchi > >> mappable VRAM vs non-mappable in patches, is it planned to just thrash >> the aperture if userspace ever ties to map too much of it. >> >> Are pagetables stored in the visible RAM space? >> >> Dave. >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > From daniele.ceraolospurio at intel.com Fri Jun 26 17:45:56 2020 From: daniele.ceraolospurio at intel.com (Daniele Ceraolo Spurio) Date: Fri, 26 Jun 2020 10:45:56 -0700 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE In-Reply-To: <159318215858.13600.17747631516505792821@build.alporthouse.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-3-daniele.ceraolospurio@intel.com> <159318215858.13600.17747631516505792821@build.alporthouse.com> Message-ID: <f6b67b54-cd8d-adde-f260-1a7151e687a0@intel.com> On 6/26/20 7:35 AM, Chris Wilson wrote: > Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:07) >> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c >> index 26cae4846c82..ddefc52f6e09 100644 >> --- a/drivers/gpu/drm/i915/gvt/handlers.c >> +++ b/drivers/gpu/drm/i915/gvt/handlers.c >> @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, >> MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ >> MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ >> MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ >> - if (HAS_ENGINE(dev_priv, VCS1)) \ >> + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \ > > Implicit param! It can switch to gvt->gt for all callsites, killing the > dev_priv locals. I've switched this to gvt->gt, but unfortunately the locals will have to stay because some of the display register definitions still use dev_priv implicitly to access the display mmio base and the pipe_offsets/trans_offsets arrays. Daniele > -Chris > From chris at chris-wilson.co.uk Fri Jun 26 18:03:30 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Fri, 26 Jun 2020 19:03:30 +0100 Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Use the gt in HAS_ENGINE In-Reply-To: <f6b67b54-cd8d-adde-f260-1a7151e687a0@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> <20200625234212.22811-3-daniele.ceraolospurio@intel.com> <159318215858.13600.17747631516505792821@build.alporthouse.com> <f6b67b54-cd8d-adde-f260-1a7151e687a0@intel.com> Message-ID: <159319461031.13600.5443621922037104390@build.alporthouse.com> Quoting Daniele Ceraolo Spurio (2020-06-26 18:45:56) > > > On 6/26/20 7:35 AM, Chris Wilson wrote: > > Quoting Daniele Ceraolo Spurio (2020-06-26 00:42:07) > >> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > >> index 26cae4846c82..ddefc52f6e09 100644 > >> --- a/drivers/gpu/drm/i915/gvt/handlers.c > >> +++ b/drivers/gpu/drm/i915/gvt/handlers.c > >> @@ -1867,7 +1867,7 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, > >> MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ > >> MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ > >> MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ > >> - if (HAS_ENGINE(dev_priv, VCS1)) \ > >> + if (HAS_ENGINE(&dev_priv->gt, VCS1)) \ > > > > Implicit param! It can switch to gvt->gt for all callsites, killing the > > dev_priv locals. > > I've switched this to gvt->gt, but unfortunately the locals will have to > stay because some of the display register definitions still use dev_priv > implicitly to access the display mmio base and the > pipe_offsets/trans_offsets arrays. Curses. Maybe one day. -Chris From manasi.d.navare at intel.com Fri Jun 26 23:26:40 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 26 Jun 2020 16:26:40 -0700 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status Message-ID: <20200626232641.4557-1-manasi.d.navare@intel.com> Modify the helper to add a fixed delay or poll with timeout based on platform specification to check for either Idle bit set (DDI_BUF_CTL is idle for disable case) v3: * Change the timeout to 16usecs (Ville) v2: * Use 2 separate functions or idle and active (Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 884b507c5f55..052a74625a61 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port) { - i915_reg_t reg = DDI_BUF_CTL(port); - int i; - - for (i = 0; i < 16; i++) { - udelay(1); - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) - return; + if (IS_BROXTON(dev_priv)) { + udelay(16); + return; } - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", - port_name(port)); + + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + DDI_BUF_IS_IDLE), 16)) + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", + port_name(port)); } static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) -- 2.19.1 From manasi.d.navare at intel.com Fri Jun 26 23:26:41 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Fri, 26 Jun 2020 16:26:41 -0700 Subject: [Intel-gfx] [PATCH v4 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200626232641.4557-1-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> Message-ID: <20200626232641.4557-2-manasi.d.navare@intel.com> Based on the platform, Bspec expects us to wait or poll with timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active after enabling DDI_BUF_CTL. v4: * Use the timeout for GLK (Ville) v3: * Add a new function _active for DDI BUF CTL to be non idle (Ville) v2: * Based on platform, fixed delay or poll (Ville) * Use a helper to do this (Imre, Ville) Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> Cc: Imre Deak <imre.deak at intel.com> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 052a74625a61..94d57b57139b 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, port_name(port)); } +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, + enum port port) +{ + if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv) ) { + usleep_range(600, 1000); + return; + } + + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & + DDI_BUF_IS_IDLE), 600)) + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", + port_name(port)); +} + static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) { switch (pll->info->id) { @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); - udelay(600); + intel_wait_ddi_buf_active(dev_priv, port); } static void intel_ddi_set_link_train(struct intel_dp *intel_dp, -- 2.19.1 From lucas.demarchi at intel.com Fri Jun 26 23:48:31 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Fri, 26 Jun 2020 16:48:31 -0700 Subject: [Intel-gfx] [PATCH v2 0/2] Variable renames Message-ID: <20200626234834.26864-1-lucas.demarchi@intel.com> Sadly checkpatch is not working in this series and it passed even if there was a clear alignment violation. I fixed the one reported by Ville and reviewed the rest to check if there was others. Lucas De Marchi (2): drm/i915/display: remove alias to dig_port drm/i915/display: prefer dig_port to reference intel_digital_port drivers/gpu/drm/i915/display/intel_ddi.c | 154 ++++---- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- .../drm/i915/display/intel_display_debugfs.c | 12 +- .../drm/i915/display/intel_display_power.c | 4 +- .../drm/i915/display/intel_display_types.h | 40 +-- drivers/gpu/drm/i915/display/intel_dp.c | 338 +++++++++--------- drivers/gpu/drm/i915/display/intel_dp.h | 4 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 74 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.h | 6 +- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 38 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 118 +++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 252 ++++++------- drivers/gpu/drm/i915/display/intel_hdmi.h | 4 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 8 +- drivers/gpu/drm/i915/display/intel_lspcon.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +- 18 files changed, 535 insertions(+), 539 deletions(-) -- 2.26.2 From lucas.demarchi at intel.com Fri Jun 26 23:48:32 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Fri, 26 Jun 2020 16:48:32 -0700 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/display: remove alias to dig_port In-Reply-To: <20200626234834.26864-1-lucas.demarchi@intel.com> References: <20200626234834.26864-1-lucas.demarchi@intel.com> Message-ID: <20200626234834.26864-2-lucas.demarchi@intel.com> We don't need intel_dig_port and dig_port to refer to the same thing. Prefer the latter. v2: fix coding style Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Matt Roper <matthew.d.roper at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 884b507c5f55..025d4052f6f8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3380,11 +3380,10 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int level = intel_ddi_hdmi_level(encoder); - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); intel_ddi_clk_select(encoder, crtc_state); @@ -3411,9 +3410,9 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, intel_ddi_enable_pipe_clock(encoder, crtc_state); - intel_dig_port->set_infoframes(encoder, - crtc_state->has_infoframe, - crtc_state, conn_state); + dig_port->set_infoframes(encoder, + crtc_state->has_infoframe, + crtc_state, conn_state); } static void intel_ddi_pre_enable(struct intel_atomic_state *state, -- 2.26.2 From lucas.demarchi at intel.com Fri Jun 26 23:48:33 2020 From: lucas.demarchi at intel.com (Lucas De Marchi) Date: Fri, 26 Jun 2020 16:48:33 -0700 Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/display: prefer dig_port to reference intel_digital_port In-Reply-To: <20200626234834.26864-1-lucas.demarchi@intel.com> References: <20200626234834.26864-1-lucas.demarchi@intel.com> Message-ID: <20200626234834.26864-3-lucas.demarchi@intel.com> We have a mix of dport, intel_dport, intel_dig_port and dig_port to reference a intel_digital_port struct. Numbers are around 5 intel_dport 36 dport 479 intel_dig_port 352 dig_port Since we already removed the intel_ prefix from most of our other structs, do the same here and prefer dig_port. v2: rename everything in i915, not just a few display sources and reword commit message (from Matt Roper) Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 143 ++++---- drivers/gpu/drm/i915/display/intel_display.c | 6 +- drivers/gpu/drm/i915/display/intel_display.h | 2 +- .../drm/i915/display/intel_display_debugfs.c | 12 +- .../drm/i915/display/intel_display_power.c | 4 +- .../drm/i915/display/intel_display_types.h | 40 +-- drivers/gpu/drm/i915/display/intel_dp.c | 338 +++++++++--------- drivers/gpu/drm/i915/display/intel_dp.h | 4 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 74 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.h | 6 +- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 38 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 118 +++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 252 ++++++------- drivers/gpu/drm/i915/display/intel_hdmi.h | 4 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 8 +- drivers/gpu/drm/i915/display/intel_lspcon.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +- 18 files changed, 530 insertions(+), 533 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 025d4052f6f8..583170e73881 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1394,10 +1394,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *intel_dig_port = - enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - intel_dp->DP = intel_dig_port->saved_port_bits | + intel_dp->DP = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); } @@ -2070,7 +2069,7 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, static void skl_ddi_set_iboost(struct intel_encoder *encoder, int level, enum intel_output_type type) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; u8 iboost; @@ -2107,7 +2106,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, _skl_ddi_set_iboost(dev_priv, port, iboost); - if (port == PORT_A && intel_dig_port->max_lanes == 4) + if (port == PORT_A && dig_port->max_lanes == 4) _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); } @@ -3000,15 +2999,15 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } static void -icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, +icl_program_mg_dp_mode(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); - enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); u32 ln0, ln1, pin_assignment; u8 width; - if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) + if (dig_port->tc_mode == TC_PORT_TBT_ALT) return; if (INTEL_GEN(dev_priv) >= 12) { @@ -3027,13 +3026,13 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); /* DPPATC */ - pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); + pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); width = crtc_state->lane_count; switch (pin_assignment) { case 0x0: drm_WARN_ON(&dev_priv->drm, - intel_dig_port->tc_mode != TC_PORT_LEGACY); + dig_port->tc_mode != TC_PORT_LEGACY); if (width == 1) { ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; } else { @@ -3978,10 +3977,9 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = - to_i915(intel_dig_port->base.base.dev); - enum port port = intel_dig_port->base.port; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->base.port; u32 dp_tp_ctl, ddi_buf_ctl; bool wait = false; @@ -4536,42 +4534,41 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { }; static struct intel_connector * -intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) +intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); struct intel_connector *connector; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; connector = intel_connector_alloc(); if (!connector) return NULL; - intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); - intel_dig_port->dp.prepare_link_retrain = - intel_ddi_prepare_link_retrain; - intel_dig_port->dp.set_link_train = intel_ddi_set_link_train; - intel_dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; + dig_port->dp.output_reg = DDI_BUF_CTL(port); + dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; + dig_port->dp.set_link_train = intel_ddi_set_link_train; + dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; if (INTEL_GEN(dev_priv) >= 12) - intel_dig_port->dp.set_signal_levels = tgl_set_signal_levels; + dig_port->dp.set_signal_levels = tgl_set_signal_levels; else if (INTEL_GEN(dev_priv) >= 11) - intel_dig_port->dp.set_signal_levels = icl_set_signal_levels; + dig_port->dp.set_signal_levels = icl_set_signal_levels; else if (IS_CANNONLAKE(dev_priv)) - intel_dig_port->dp.set_signal_levels = cnl_set_signal_levels; + dig_port->dp.set_signal_levels = cnl_set_signal_levels; else if (IS_GEN9_LP(dev_priv)) - intel_dig_port->dp.set_signal_levels = bxt_set_signal_levels; + dig_port->dp.set_signal_levels = bxt_set_signal_levels; else - intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels; + dig_port->dp.set_signal_levels = hsw_set_signal_levels; - intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; - intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; + dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; + dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; if (INTEL_GEN(dev_priv) < 12) { - intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); - intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); + dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); + dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); } - if (!intel_dp_init_connector(intel_dig_port, connector)) { + if (!intel_dp_init_connector(dig_port, connector)) { kfree(connector); return NULL; } @@ -4770,29 +4767,29 @@ static bool bdw_digital_port_connected(struct intel_encoder *encoder) } static struct intel_connector * -intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) +intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) { struct intel_connector *connector; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; connector = intel_connector_alloc(); if (!connector) return NULL; - intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); - intel_hdmi_init_connector(intel_dig_port, connector); + dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); + intel_hdmi_init_connector(dig_port, connector); return connector; } -static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) +static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); - if (dport->base.port != PORT_A) + if (dig_port->base.port != PORT_A) return false; - if (dport->saved_port_bits & DDI_A_4_LANES) + if (dig_port->saved_port_bits & DDI_A_4_LANES) return false; /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only @@ -4814,10 +4811,10 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) } static int -intel_ddi_max_lanes(struct intel_digital_port *intel_dport) +intel_ddi_max_lanes(struct intel_digital_port *dig_port) { - struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); - enum port port = intel_dport->base.port; + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + enum port port = dig_port->base.port; int max_lanes = 4; if (INTEL_GEN(dev_priv) >= 11) @@ -4836,10 +4833,10 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) * wasn't lit up at boot. Force this bit set when needed * so we use the proper lane count for our calculations. */ - if (intel_ddi_a_force_4_lanes(intel_dport)) { + if (intel_ddi_a_force_4_lanes(dig_port)) { drm_dbg_kms(&dev_priv->drm, "Forcing DDI_A_4_LANES for port A\n"); - intel_dport->saved_port_bits |= DDI_A_4_LANES; + dig_port->saved_port_bits |= DDI_A_4_LANES; max_lanes = 4; } @@ -4848,7 +4845,7 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) { - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct intel_encoder *encoder; bool init_hdmi, init_dp, init_lspcon = false; enum phy phy = intel_port_to_phy(dev_priv, port); @@ -4877,11 +4874,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) return; } - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); - if (!intel_dig_port) + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); + if (!dig_port) return; - encoder = &intel_dig_port->base; + encoder = &dig_port->base; drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); @@ -4908,49 +4905,49 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->pipe_mask = ~0; if (INTEL_GEN(dev_priv) >= 11) - intel_dig_port->saved_port_bits = intel_de_read(dev_priv, - DDI_BUF_CTL(port)) & - DDI_BUF_PORT_REVERSAL; + dig_port->saved_port_bits = + intel_de_read(dev_priv, DDI_BUF_CTL(port)) + & DDI_BUF_PORT_REVERSAL; else - intel_dig_port->saved_port_bits = intel_de_read(dev_priv, - DDI_BUF_CTL(port)) & - (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); + dig_port->saved_port_bits = + intel_de_read(dev_priv, DDI_BUF_CTL(port)) + & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); - intel_dig_port->dp.output_reg = INVALID_MMIO_REG; - intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); + dig_port->dp.output_reg = INVALID_MMIO_REG; + dig_port->max_lanes = intel_ddi_max_lanes(dig_port); + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); if (intel_phy_is_tc(dev_priv, phy)) { bool is_legacy = !intel_bios_port_supports_typec_usb(dev_priv, port) && !intel_bios_port_supports_tbt(dev_priv, port); - intel_tc_port_init(intel_dig_port, is_legacy); + intel_tc_port_init(dig_port, is_legacy); encoder->update_prepare = intel_ddi_update_prepare; encoder->update_complete = intel_ddi_update_complete; } drm_WARN_ON(&dev_priv->drm, port > PORT_I); - intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + + dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + port - PORT_A; if (init_dp) { - if (!intel_ddi_init_dp_connector(intel_dig_port)) + if (!intel_ddi_init_dp_connector(dig_port)) goto err; - intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; + dig_port->hpd_pulse = intel_dp_hpd_pulse; } /* In theory we don't need the encoder->type check, but leave it just in * case we have some really bad VBTs... */ if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { - if (!intel_ddi_init_hdmi_connector(intel_dig_port)) + if (!intel_ddi_init_hdmi_connector(dig_port)) goto err; } if (init_lspcon) { - if (lspcon_init(intel_dig_port)) + if (lspcon_init(dig_port)) /* TODO: handle hdmi info frame part */ drm_dbg_kms(&dev_priv->drm, "LSPCON init success on port %c\n", @@ -4967,26 +4964,26 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) if (INTEL_GEN(dev_priv) >= 11) { if (intel_phy_is_tc(dev_priv, phy)) - intel_dig_port->connected = intel_tc_port_connected; + dig_port->connected = intel_tc_port_connected; else - intel_dig_port->connected = lpt_digital_port_connected; + dig_port->connected = lpt_digital_port_connected; } else if (INTEL_GEN(dev_priv) >= 8) { if (port == PORT_A || IS_GEN9_LP(dev_priv)) - intel_dig_port->connected = bdw_digital_port_connected; + dig_port->connected = bdw_digital_port_connected; else - intel_dig_port->connected = lpt_digital_port_connected; + dig_port->connected = lpt_digital_port_connected; } else { if (port == PORT_A) - intel_dig_port->connected = hsw_digital_port_connected; + dig_port->connected = hsw_digital_port_connected; else - intel_dig_port->connected = lpt_digital_port_connected; + dig_port->connected = lpt_digital_port_connected; } - intel_infoframe_init(intel_dig_port); + intel_infoframe_init(dig_port); return; err: drm_encoder_cleanup(&encoder->base); - kfree(intel_dig_port); + kfree(dig_port); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a11bb675f9b3..3b1f0b28e585 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1611,13 +1611,13 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport, + struct intel_digital_port *dig_port, unsigned int expected_mask) { u32 port_mask; i915_reg_t dpll_reg; - switch (dport->base.port) { + switch (dig_port->base.port) { case PORT_B: port_mask = DPLL_PORTB_READY_MASK; dpll_reg = DPLL(0); @@ -1639,7 +1639,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, port_mask, expected_mask, 1000)) drm_WARN(&dev_priv->drm, 1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", - dport->base.base.base.id, dport->base.base.name, + dig_port->base.base.base.id, dig_port->base.base.name, intel_de_read(dev_priv, dpll_reg) & port_mask, expected_mask); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b7a6d56bac5f..bc6021b994b1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -542,7 +542,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); void vlv_wait_port_ready(struct drm_i915_private *dev_priv, - struct intel_digital_port *dport, + struct intel_digital_port *dig_port, unsigned int expected_mask); int intel_get_load_detect_pipe(struct drm_connector *connector, struct intel_load_detect_pipe *old, diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index d1cb48b3f462..3644752cc5ec 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1194,7 +1194,7 @@ static int i915_dp_mst_info(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct drm_device *dev = &dev_priv->drm; struct intel_encoder *intel_encoder; - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct drm_connector *connector; struct drm_connector_list_iter conn_iter; @@ -1207,14 +1207,14 @@ static int i915_dp_mst_info(struct seq_file *m, void *unused) if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) continue; - intel_dig_port = enc_to_dig_port(intel_encoder); - if (!intel_dig_port->dp.can_mst) + dig_port = enc_to_dig_port(intel_encoder); + if (!dig_port->dp.can_mst) continue; seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); - drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); + dig_port->base.base.base.id, + dig_port->base.base.name); + drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 8a277dfbc070..0c713e83274d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1817,8 +1817,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct i915_power_domains *power_domains = &dev_priv->power_domains; - enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(encoder)); - enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(encoder)); + enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); + enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); mutex_lock(&power_domains->lock); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4b0aaa3081c9..e8f809161c75 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -279,10 +279,10 @@ enum check_link_response { */ struct intel_hdcp_shim { /* Outputs the transmitter's An and Aksv values to the receiver. */ - int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); + int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); /* Reads the receiver's key selection vector */ - int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); + int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); /* * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The @@ -290,52 +290,52 @@ struct intel_hdcp_shim { * different. Call it BSTATUS since that's the name the HDMI spec * uses and it was there first. */ - int (*read_bstatus)(struct intel_digital_port *intel_dig_port, + int (*read_bstatus)(struct intel_digital_port *dig_port, u8 *bstatus); /* Determines whether a repeater is present downstream */ - int (*repeater_present)(struct intel_digital_port *intel_dig_port, + int (*repeater_present)(struct intel_digital_port *dig_port, bool *repeater_present); /* Reads the receiver's Ri' value */ - int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); + int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); /* Determines if the receiver's KSV FIFO is ready for consumption */ - int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, + int (*read_ksv_ready)(struct intel_digital_port *dig_port, bool *ksv_ready); /* Reads the ksv fifo for num_downstream devices */ - int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, + int (*read_ksv_fifo)(struct intel_digital_port *dig_port, int num_downstream, u8 *ksv_fifo); /* Reads a 32-bit part of V' from the receiver */ - int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, + int (*read_v_prime_part)(struct intel_digital_port *dig_port, int i, u32 *part); /* Enables HDCP signalling on the port */ - int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, + int (*toggle_signalling)(struct intel_digital_port *dig_port, bool enable); /* Ensures the link is still protected */ - bool (*check_link)(struct intel_digital_port *intel_dig_port); + bool (*check_link)(struct intel_digital_port *dig_port); /* Detects panel's hdcp capability. This is optional for HDMI. */ - int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, + int (*hdcp_capable)(struct intel_digital_port *dig_port, bool *hdcp_capable); /* HDCP adaptation(DP/HDMI) required on the port */ enum hdcp_wired_protocol protocol; /* Detects whether sink is HDCP2.2 capable */ - int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port, + int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port, bool *capable); /* Write HDCP2.2 messages */ - int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port, + int (*write_2_2_msg)(struct intel_digital_port *dig_port, void *buf, size_t size); /* Read HDCP2.2 messages */ - int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port, + int (*read_2_2_msg)(struct intel_digital_port *dig_port, u8 msg_id, void *buf, size_t size); /* @@ -343,11 +343,11 @@ struct intel_hdcp_shim { * type to Receivers. In DP HDCP2.2 Stream type is one of the input to * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. */ - int (*config_stream_type)(struct intel_digital_port *intel_dig_port, + int (*config_stream_type)(struct intel_digital_port *dig_port, bool is_repeater, u8 type); /* HDCP2.2 Link Integrity Check */ - int (*check_2_2_link)(struct intel_digital_port *intel_dig_port); + int (*check_2_2_link)(struct intel_digital_port *dig_port); }; struct intel_hdcp { @@ -1434,9 +1434,9 @@ struct intel_dp_mst_encoder { }; static inline enum dpio_channel -vlv_dport_to_channel(struct intel_digital_port *dport) +vlv_dig_port_to_channel(struct intel_digital_port *dig_port) { - switch (dport->base.port) { + switch (dig_port->base.port) { case PORT_B: case PORT_D: return DPIO_CH0; @@ -1448,9 +1448,9 @@ vlv_dport_to_channel(struct intel_digital_port *dport) } static inline enum dpio_phy -vlv_dport_to_phy(struct intel_digital_port *dport) +vlv_dig_port_to_phy(struct intel_digital_port *dig_port) { - switch (dport->base.port) { + switch (dig_port->base.port) { case PORT_B: case PORT_C: return DPIO_PHY0; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3df5d901dd9d..d6295eb20b63 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -140,9 +140,9 @@ static const u8 valid_dsc_slicecount[] = {1, 2, 4}; */ bool intel_dp_is_edp(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - return intel_dig_port->base.type == INTEL_OUTPUT_EDP; + return dig_port->base.type == INTEL_OUTPUT_EDP; } static void intel_dp_link_down(struct intel_encoder *encoder, @@ -216,10 +216,10 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp) /* Theoretical max between source and sink */ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - int source_max = intel_dig_port->max_lanes; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + int source_max = dig_port->max_lanes; int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); - int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port); + int fia_max = intel_tc_port_fia_max_lane_count(dig_port); return min3(source_max, sink_max, fia_max); } @@ -251,8 +251,8 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) static int intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct intel_encoder *encoder = &intel_dig_port->base; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int max_dotclk = dev_priv->max_dotclk_freq; int ds_max_dotclk; @@ -778,7 +778,7 @@ static void vlv_power_sequencer_kick(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe = intel_dp->pps_pipe; bool pll_enabled, release_cl_override = false; enum dpio_phy phy = DPIO_PHY(pipe); @@ -788,14 +788,14 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) if (drm_WARN(&dev_priv->drm, intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name)) + pipe_name(pipe), dig_port->base.base.base.id, + dig_port->base.base.name)) return; drm_dbg_kms(&dev_priv->drm, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + pipe_name(pipe), dig_port->base.base.base.id, + dig_port->base.base.name); /* Preserve the BIOS-computed detected bit. This is * supposed to be read-only. @@ -891,7 +891,7 @@ static enum pipe vlv_power_sequencer_pipe(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe; lockdep_assert_held(&dev_priv->pps_mutex); @@ -920,8 +920,8 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) drm_dbg_kms(&dev_priv->drm, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", pipe_name(intel_dp->pps_pipe), - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); /* init power sequencer on this pipe and port */ intel_dp_init_panel_power_sequencer(intel_dp); @@ -1009,8 +1009,8 @@ static void vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - enum port port = intel_dig_port->base.port; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum port port = dig_port->base.port; lockdep_assert_held(&dev_priv->pps_mutex); @@ -1031,15 +1031,15 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) if (intel_dp->pps_pipe == INVALID_PIPE) { drm_dbg_kms(&dev_priv->drm, "no initial power sequencer for [ENCODER:%d:%s]\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); return; } drm_dbg_kms(&dev_priv->drm, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name, + dig_port->base.base.base.id, + dig_port->base.base.name, pipe_name(intel_dp->pps_pipe)); intel_dp_init_panel_power_sequencer(intel_dp); @@ -1304,9 +1304,9 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, int send_bytes, u32 aux_clock_divider) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = - to_i915(intel_dig_port->base.base.dev); + to_i915(dig_port->base.base.dev); u32 precharge, timeout; if (IS_GEN(dev_priv, 6)) @@ -1334,10 +1334,10 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, int send_bytes, u32 unused) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *i915 = - to_i915(intel_dig_port->base.base.dev); - enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); + to_i915(dig_port->base.base.dev); + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); u32 ret; ret = DP_AUX_CH_CTL_SEND_BUSY | @@ -1351,7 +1351,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); if (intel_phy_is_tc(i915, phy) && - intel_dig_port->tc_mode == TC_PORT_TBT_ALT) + dig_port->tc_mode == TC_PORT_TBT_ALT) ret |= DP_AUX_CH_CTL_TBT_IO; return ret; @@ -1363,11 +1363,11 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, u8 *recv, int recv_size, u32 aux_send_ctl_flags) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *i915 = - to_i915(intel_dig_port->base.base.dev); + to_i915(dig_port->base.base.dev); struct intel_uncore *uncore = &i915->uncore; - enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); bool is_tc_port = intel_phy_is_tc(i915, phy); i915_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; @@ -1384,9 +1384,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); if (is_tc_port) - intel_tc_port_lock(intel_dig_port); + intel_tc_port_lock(dig_port); - aux_domain = intel_aux_power_domain(intel_dig_port); + aux_domain = intel_aux_power_domain(dig_port); aux_wakeref = intel_display_power_get(i915, aux_domain); pps_wakeref = pps_lock(intel_dp); @@ -1545,7 +1545,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, intel_display_power_put_async(i915, aux_domain, aux_wakeref); if (is_tc_port) - intel_tc_port_unlock(intel_dig_port); + intel_tc_port_unlock(dig_port); return ret; } @@ -2891,7 +2891,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp) static bool edp_panel_vdd_on(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; bool need_to_disable = !intel_dp->want_panel_vdd; @@ -2908,11 +2908,11 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) return need_to_disable; intel_display_power_get(dev_priv, - intel_aux_power_domain(intel_dig_port)); + intel_aux_power_domain(dig_port)); drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); if (!edp_have_panel_power(intel_dp)) wait_panel_power_cycle(intel_dp); @@ -2934,8 +2934,8 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) if (!edp_have_panel_power(intel_dp)) { drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] panel power wasn't enabled\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); msleep(intel_dp->panel_power_up_delay); } @@ -2968,7 +2968,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; @@ -2981,8 +2981,8 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) return; drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); pp = ilk_get_pp_control(intel_dp); pp &= ~EDP_FORCE_VDD; @@ -3002,7 +3002,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) intel_dp->panel_power_off_time = ktime_get_boottime(); intel_display_power_put_unchecked(dev_priv, - intel_aux_power_domain(intel_dig_port)); + intel_aux_power_domain(dig_port)); } static void edp_panel_vdd_work(struct work_struct *__work) @@ -3833,8 +3833,8 @@ static void g4x_pre_enable_dp(struct intel_atomic_state *state, static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum pipe pipe = intel_dp->pps_pipe; i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); @@ -3856,8 +3856,8 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) */ drm_dbg_kms(&dev_priv->drm, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + pipe_name(pipe), dig_port->base.base.base.id, + dig_port->base.base.name); intel_de_write(dev_priv, pp_on_reg, 0); intel_de_posting_read(dev_priv, pp_on_reg); @@ -4923,7 +4923,7 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct dp_sdp sdp = {}; ssize_t len; @@ -4949,14 +4949,14 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, if (drm_WARN_ON(&dev_priv->drm, len < 0)) return; - intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); + dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); } void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, struct drm_dp_vsc_sdp *vsc) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct dp_sdp sdp = {}; ssize_t len; @@ -4966,7 +4966,7 @@ void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, if (drm_WARN_ON(&dev_priv->drm, len < 0)) return; - intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, + dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, &sdp, len); } @@ -5126,7 +5126,7 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_dp_vsc_sdp *vsc) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); unsigned int type = DP_SDP_VSC; @@ -5141,7 +5141,7 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, intel_hdmi_infoframe_enable(type)) == 0) return; - intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); + dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); @@ -5153,7 +5153,7 @@ static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encod struct intel_crtc_state *crtc_state, struct hdmi_drm_infoframe *drm_infoframe) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; struct dp_sdp sdp = {}; @@ -5163,8 +5163,8 @@ static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encod intel_hdmi_infoframe_enable(type)) == 0) return; - intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, - sizeof(sdp)); + dig_port->read_infoframe(encoder, crtc_state, type, &sdp, + sizeof(sdp)); ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, sizeof(sdp)); @@ -5366,10 +5366,10 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = to_i915(dp_to_dig_port(intel_dp)->base.base.dev); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_dp_phy_test_params *data = &intel_dp->compliance.test_data.phytest; - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; u32 pattern_val; @@ -5431,10 +5431,10 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) static void intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; @@ -5457,11 +5457,11 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) static void intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) { - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - enum port port = intel_dig_port->base.port; - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); + enum port port = dig_port->base.port; + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; @@ -6332,10 +6332,10 @@ intel_dp_connector_unregister(struct drm_connector *connector) void intel_dp_encoder_flush_work(struct drm_encoder *encoder) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder)); - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); + struct intel_dp *intel_dp = &dig_port->dp; - intel_dp_mst_encoder_cleanup(intel_dig_port); + intel_dp_mst_encoder_cleanup(dig_port); if (intel_dp_is_edp(intel_dp)) { intel_wakeref_t wakeref; @@ -6394,11 +6394,11 @@ static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) } static -int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, u8 *an) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base)); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&dig_port->base.base)); static const struct drm_dp_aux_msg msg = { .request = DP_AUX_NATIVE_WRITE, .address = DP_AUX_HDCP_AKSV, @@ -6409,7 +6409,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, int ret; /* Output An first, that's easy */ - dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, + dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, an, DRM_HDCP_AN_LEN); if (dpcd_ret != DRM_HDCP_AN_LEN) { drm_dbg_kms(&i915->drm, @@ -6448,13 +6448,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, return 0; } -static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, +static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, u8 *bksv) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, DRM_HDCP_KSV_LEN); if (ret != DRM_HDCP_KSV_LEN) { drm_dbg_kms(&i915->drm, @@ -6464,10 +6464,10 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, return 0; } -static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, +static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, u8 *bstatus) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; /* @@ -6475,7 +6475,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, * definition by different names. In the HDMI spec, it's called BSTATUS, * but in DP it's called BINFO. */ - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, bstatus, DRM_HDCP_BSTATUS_LEN); if (ret != DRM_HDCP_BSTATUS_LEN) { drm_dbg_kms(&i915->drm, @@ -6486,13 +6486,13 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port, u8 *bcaps) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS, bcaps, 1); if (ret != 1) { drm_dbg_kms(&i915->drm, @@ -6504,13 +6504,13 @@ int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, bool *repeater_present) { ssize_t ret; u8 bcaps; - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); if (ret) return ret; @@ -6519,13 +6519,13 @@ int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, u8 *ri_prime) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, ri_prime, DRM_HDCP_RI_LEN); if (ret != DRM_HDCP_RI_LEN) { drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", @@ -6536,14 +6536,14 @@ int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, bool *ksv_ready) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; u8 bstatus; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, &bstatus, 1); if (ret != 1) { drm_dbg_kms(&i915->drm, @@ -6555,17 +6555,17 @@ int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, int num_downstream, u8 *ksv_fifo) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; int i; /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ for (i = 0; i < num_downstream; i += 3) { size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_KSV_FIFO, ksv_fifo + i * DRM_HDCP_KSV_LEN, len); @@ -6580,16 +6580,16 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, int i, u32 *part) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) return -EINVAL; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_V_PRIME(i), part, DRM_HDCP_V_PRIME_PART_LEN); if (ret != DRM_HDCP_V_PRIME_PART_LEN) { @@ -6601,7 +6601,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, bool enable) { /* Not used for single stream DisplayPort setups */ @@ -6609,13 +6609,13 @@ int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, } static -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; u8 bstatus; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, &bstatus, 1); if (ret != 1) { drm_dbg_kms(&i915->drm, @@ -6627,13 +6627,13 @@ bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) } static -int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp_capable(struct intel_digital_port *dig_port, bool *hdcp_capable) { ssize_t ret; u8 bcaps; - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); + ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); if (ret) return ret; @@ -6691,13 +6691,13 @@ static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { }; static int -intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, +intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, u8 *rx_status) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, HDCP_2_2_DP_RXSTATUS_LEN); if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { @@ -6710,14 +6710,14 @@ intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, } static -int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, +int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, u8 msg_id, bool *msg_ready) { u8 rx_status; int ret; *msg_ready = false; - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); if (ret < 0) return ret; @@ -6743,11 +6743,11 @@ int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, } static ssize_t -intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, const struct hdcp2_dp_msg_data *hdcp2_msg_data) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *dp = &intel_dig_port->dp; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *dp = &dig_port->dp; struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; u8 msg_id = hdcp2_msg_data->msg_id; int ret, timeout; @@ -6771,7 +6771,7 @@ intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, * the timeout at wait for CP_IRQ. */ intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); - ret = hdcp2_detect_msg_availability(intel_dig_port, + ret = hdcp2_detect_msg_availability(dig_port, msg_id, &msg_ready); if (!msg_ready) ret = -ETIMEDOUT; @@ -6797,10 +6797,10 @@ static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) } static -int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, void *buf, size_t size) { - struct intel_dp *dp = &intel_dig_port->dp; + struct intel_dp *dp = &dig_port->dp; struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; unsigned int offset; u8 *byte = buf; @@ -6823,7 +6823,7 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; - ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_write(&dig_port->dp.aux, offset, (void *)byte, len); if (ret < 0) return ret; @@ -6837,13 +6837,13 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, } static -ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) +ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port) { u8 rx_info[HDCP_2_2_RXINFO_LEN]; u32 dev_cnt; ssize_t ret; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_HDCP_2_2_REG_RXINFO_OFFSET, (void *)rx_info, HDCP_2_2_RXINFO_LEN); if (ret != HDCP_2_2_RXINFO_LEN) @@ -6863,10 +6863,10 @@ ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) } static -int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, u8 msg_id, void *buf, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); unsigned int offset; u8 *byte = buf; ssize_t ret, bytes_to_recv, len; @@ -6877,12 +6877,12 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, return -EINVAL; offset = hdcp2_msg_data->offset; - ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); + ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data); if (ret < 0) return ret; if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { - ret = get_receiver_id_list_size(intel_dig_port); + ret = get_receiver_id_list_size(dig_port); if (ret < 0) return ret; @@ -6897,7 +6897,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset, (void *)byte, len); if (ret < 0) { drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", @@ -6916,7 +6916,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port, bool is_repeater, u8 content_type) { int ret; @@ -6935,7 +6935,7 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; stream_type_msg.stream_type = content_type; - ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, + ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg, sizeof(stream_type_msg)); return ret < 0 ? ret : 0; @@ -6943,12 +6943,12 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, } static -int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port) { u8 rx_status; int ret; - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); + ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); if (ret) return ret; @@ -6963,14 +6963,14 @@ int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) } static -int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, +int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port, bool *capable) { u8 rx_caps[3]; int ret; *capable = false; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_HDCP_2_2_REG_RX_CAPS_OFFSET, rx_caps, HDCP_2_2_RXCAPS_LEN); if (ret != HDCP_2_2_RXCAPS_LEN) @@ -7249,12 +7249,12 @@ static bool intel_edp_have_power(struct intel_dp *intel_dp) } enum irqreturn -intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) +intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *intel_dp = &dig_port->dp; - if (intel_dig_port->base.type == INTEL_OUTPUT_EDP && + if (dig_port->base.type == INTEL_OUTPUT_EDP && (long_hpd || !intel_edp_have_power(intel_dp))) { /* * vdd off can generate a long/short pulse on eDP which @@ -7265,14 +7265,14 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) drm_dbg_kms(&i915->drm, "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", long_hpd ? "long" : "short", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + dig_port->base.base.base.id, + dig_port->base.base.name); return IRQ_HANDLED; } drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name, + dig_port->base.base.base.id, + dig_port->base.base.name, long_hpd ? "long" : "short"); if (long_hpd) { @@ -8135,12 +8135,12 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work) } bool -intel_dp_init_connector(struct intel_digital_port *intel_dig_port, +intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector) { struct drm_connector *connector = &intel_connector->base; - struct intel_dp *intel_dp = &intel_dig_port->dp; - struct intel_encoder *intel_encoder = &intel_dig_port->base; + struct intel_dp *intel_dp = &dig_port->dp; + struct intel_encoder *intel_encoder = &dig_port->base; struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); enum port port = intel_encoder->port; @@ -8151,9 +8151,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, INIT_WORK(&intel_connector->modeset_retry_work, intel_dp_modeset_retry_work_fn); - if (drm_WARN(dev, intel_dig_port->max_lanes < 1, + if (drm_WARN(dev, dig_port->max_lanes < 1, "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, + dig_port->max_lanes, intel_encoder->base.base.id, intel_encoder->base.name)) return false; @@ -8224,12 +8224,12 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_connector->get_hw_state = intel_connector_get_hw_state; /* init MST on ports that can support it */ - intel_dp_mst_encoder_init(intel_dig_port, + intel_dp_mst_encoder_init(dig_port, intel_connector->base.base.id); if (!intel_edp_init_connector(intel_dp, intel_connector)) { intel_dp_aux_fini(intel_dp); - intel_dp_mst_encoder_cleanup(intel_dig_port); + intel_dp_mst_encoder_cleanup(dig_port); goto fail; } @@ -8264,20 +8264,20 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, enum port port) { - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; struct drm_encoder *encoder; struct intel_connector *intel_connector; - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); - if (!intel_dig_port) + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); + if (!dig_port) return false; intel_connector = intel_connector_alloc(); if (!intel_connector) goto err_connector_alloc; - intel_encoder = &intel_dig_port->base; + intel_encoder = &dig_port->base; encoder = &intel_encoder->base; if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, @@ -8313,34 +8313,34 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || (HAS_PCH_CPT(dev_priv) && port != PORT_A)) - intel_dig_port->dp.set_link_train = cpt_set_link_train; + dig_port->dp.set_link_train = cpt_set_link_train; else - intel_dig_port->dp.set_link_train = g4x_set_link_train; + dig_port->dp.set_link_train = g4x_set_link_train; if (IS_CHERRYVIEW(dev_priv)) - intel_dig_port->dp.set_signal_levels = chv_set_signal_levels; + dig_port->dp.set_signal_levels = chv_set_signal_levels; else if (IS_VALLEYVIEW(dev_priv)) - intel_dig_port->dp.set_signal_levels = vlv_set_signal_levels; + dig_port->dp.set_signal_levels = vlv_set_signal_levels; else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) - intel_dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; + dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; else if (IS_GEN(dev_priv, 6) && port == PORT_A) - intel_dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; + dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; else - intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels; + dig_port->dp.set_signal_levels = g4x_set_signal_levels; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { - intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3; - intel_dig_port->dp.voltage_max = intel_dp_voltage_max_3; + dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3; + dig_port->dp.voltage_max = intel_dp_voltage_max_3; } else { - intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2; - intel_dig_port->dp.voltage_max = intel_dp_voltage_max_2; + dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2; + dig_port->dp.voltage_max = intel_dp_voltage_max_2; } - intel_dig_port->dp.output_reg = output_reg; - intel_dig_port->max_lanes = 4; - intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); - intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); + dig_port->dp.output_reg = output_reg; + dig_port->max_lanes = 4; + dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); + dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); intel_encoder->type = INTEL_OUTPUT_DP; intel_encoder->power_domain = intel_port_to_power_domain(port); @@ -8355,25 +8355,25 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, intel_encoder->cloneable = 0; intel_encoder->port = port; - intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; + dig_port->hpd_pulse = intel_dp_hpd_pulse; if (HAS_GMCH(dev_priv)) { if (IS_GM45(dev_priv)) - intel_dig_port->connected = gm45_digital_port_connected; + dig_port->connected = gm45_digital_port_connected; else - intel_dig_port->connected = g4x_digital_port_connected; + dig_port->connected = g4x_digital_port_connected; } else { if (port == PORT_A) - intel_dig_port->connected = ilk_digital_port_connected; + dig_port->connected = ilk_digital_port_connected; else - intel_dig_port->connected = ibx_digital_port_connected; + dig_port->connected = ibx_digital_port_connected; } if (port != PORT_A) - intel_infoframe_init(intel_dig_port); + intel_infoframe_init(dig_port); - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); - if (!intel_dp_init_connector(intel_dig_port, intel_connector)) + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); + if (!intel_dp_init_connector(dig_port, intel_connector)) goto err_init_connector; return true; @@ -8383,7 +8383,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, err_encoder_init: kfree(intel_connector); err_connector_alloc: - kfree(intel_dig_port); + kfree(dig_port); return false; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..b901ab850cbd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -40,7 +40,7 @@ bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, enum pipe *pipe); bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, enum port port); -bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, +bool intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, u8 lane_count, @@ -61,7 +61,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); -enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, +enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd); void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 8273f2e07427..bdc19b04b2c1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -342,8 +342,8 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); @@ -369,8 +369,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); @@ -421,7 +421,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, * the transcoder clock select is set to none. */ if (last_mst_stream) - intel_dp_set_infoframes(&intel_dig_port->base, false, + intel_dp_set_infoframes(&dig_port->base, false, old_crtc_state, NULL); /* * From TGL spec: "If multi-stream slave transcoder: Configure @@ -436,7 +436,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_mst->connector = NULL; if (last_mst_stream) - intel_dig_port->base.post_disable(state, &intel_dig_port->base, + dig_port->base.post_disable(state, &dig_port->base, old_crtc_state, NULL); drm_dbg_kms(&dev_priv->drm, "active links %d\n", @@ -449,11 +449,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; if (intel_dp->active_mst_links == 0) - intel_dig_port->base.pre_pll_enable(state, &intel_dig_port->base, + dig_port->base.pre_pll_enable(state, &dig_port->base, pipe_config, NULL); } @@ -463,8 +463,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_connector *connector = to_intel_connector(conn_state->connector); @@ -490,7 +490,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); if (first_mst_stream) - intel_dig_port->base.pre_enable(state, &intel_dig_port->base, + dig_port->base.pre_enable(state, &dig_port->base, pipe_config, NULL); ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, @@ -506,7 +506,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, /* * Before Gen 12 this is not done as part of - * intel_dig_port->base.pre_enable() and should be done here. For + * dig_port->base.pre_enable() and should be done here. For * Gen 12+ the step in which this should be done is different for the * first MST stream, so it's done on the DDI for the first stream and * here for the following ones. @@ -525,8 +525,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_digital_port *dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &dig_port->dp; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 val; @@ -572,9 +572,9 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_digital_port *intel_dig_port = intel_mst->primary; + struct intel_digital_port *dig_port = intel_mst->primary; - intel_ddi_get_config(&intel_dig_port->base, pipe_config); + intel_ddi_get_config(&dig_port->base, pipe_config); } static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) @@ -732,8 +732,8 @@ static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) { struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_connector *intel_connector; struct drm_connector *connector; @@ -808,11 +808,11 @@ static const struct drm_dp_mst_topology_cbs mst_cbs = { }; static struct intel_dp_mst_encoder * -intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) +intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) { struct intel_dp_mst_encoder *intel_mst; struct intel_encoder *intel_encoder; - struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_device *dev = dig_port->base.base.dev; intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); @@ -821,14 +821,14 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum intel_mst->pipe = pipe; intel_encoder = &intel_mst->base; - intel_mst->primary = intel_dig_port; + intel_mst->primary = dig_port; drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); intel_encoder->type = INTEL_OUTPUT_DP_MST; - intel_encoder->power_domain = intel_dig_port->base.power_domain; - intel_encoder->port = intel_dig_port->base.port; + intel_encoder->power_domain = dig_port->base.power_domain; + intel_encoder->port = dig_port->base.port; intel_encoder->cloneable = 0; /* * This is wrong, but broken userspace uses the intersection @@ -855,29 +855,29 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum } static bool -intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) +intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) { - struct intel_dp *intel_dp = &intel_dig_port->dp; - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + struct intel_dp *intel_dp = &dig_port->dp; + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum pipe pipe; for_each_pipe(dev_priv, pipe) - intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(intel_dig_port, pipe); + intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); return true; } int -intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port) +intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) { - return intel_dig_port->dp.active_mst_links; + return dig_port->dp.active_mst_links; } int -intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) +intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_dp *intel_dp = &intel_dig_port->dp; - enum port port = intel_dig_port->base.port; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_dp *intel_dp = &dig_port->dp; + enum port port = dig_port->base.port; int ret; if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) @@ -892,7 +892,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_ba intel_dp->mst_mgr.cbs = &mst_cbs; /* create encoders */ - intel_dp_create_fake_mst_encoders(intel_dig_port); + intel_dp_create_fake_mst_encoders(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, &intel_dp->aux, 16, 3, conn_base_id); if (ret) @@ -904,9 +904,9 @@ intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_ba } void -intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) +intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) { - struct intel_dp *intel_dp = &intel_dig_port->dp; + struct intel_dp *intel_dp = &dig_port->dp; if (!intel_dp->can_mst) return; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h index 854724f68f09..6afda4e86b3c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h @@ -11,9 +11,9 @@ struct intel_digital_port; struct intel_crtc_state; -int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); -void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); -int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port); +int intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_id); +void intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port); +int intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port); bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state); bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 399a7edb4568..7910522273b2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -650,9 +650,9 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, bool uniq_trans_scale) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - enum dpio_channel ch = vlv_dport_to_channel(dport); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum pipe pipe = intel_crtc->pipe; u32 val; int i; @@ -746,7 +746,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, bool reset) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(encoder)); + enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; u32 val; @@ -789,10 +789,10 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, void chv_phy_pre_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel ch = vlv_dport_to_channel(dport); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; unsigned int lane_mask = intel_dp_unused_lane_mask(crtc_state->lane_count); @@ -803,7 +803,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, * Otherwise we can't even access the PLL. */ if (ch == DPIO_CH0 && pipe == PIPE_B) - dport->release_cl2_override = + dig_port->release_cl2_override = !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); chv_phy_powergate_lanes(encoder, true, lane_mask); @@ -870,10 +870,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel ch = vlv_dport_to_channel(dport); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; int data, i, stagger; u32 val; @@ -948,12 +948,12 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, void chv_phy_release_cl2_override(struct intel_encoder *encoder) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - if (dport->release_cl2_override) { + if (dig_port->release_cl2_override) { chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); - dport->release_cl2_override = false; + dig_port->release_cl2_override = false; } } @@ -997,8 +997,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); - struct intel_digital_port *dport = enc_to_dig_port(encoder); - enum dpio_channel port = vlv_dport_to_channel(dport); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = intel_crtc->pipe; vlv_dpio_get(dev_priv); @@ -1022,10 +1022,10 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dport_to_channel(dport); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; /* Program Tx lane resets to default */ @@ -1052,10 +1052,10 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *dport = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dport_to_channel(dport); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; u32 val; @@ -1081,10 +1081,10 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, void vlv_phy_reset_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dport_to_channel(dport); + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; vlv_dpio_get(dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 815b054bb167..1b6dadfce4eb 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -40,15 +40,15 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv) } static -int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, +int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, const struct intel_hdcp_shim *shim, u8 *bksv) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret, i, tries = 2; /* HDCP spec states that we must retry the bksv if it is invalid */ for (i = 0; i < tries; i++) { - ret = shim->read_bksv(intel_dig_port, bksv); + ret = shim->read_bksv(dig_port, bksv); if (ret) return ret; if (intel_hdcp_is_ksv_valid(bksv)) @@ -65,7 +65,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, /* Is HDCP1.4 capable on Platform and Sink */ bool intel_hdcp_capable(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); const struct intel_hdcp_shim *shim = connector->hdcp.shim; bool capable = false; u8 bksv[5]; @@ -74,9 +74,9 @@ bool intel_hdcp_capable(struct intel_connector *connector) return capable; if (shim->hdcp_capable) { - shim->hdcp_capable(intel_dig_port, &capable); + shim->hdcp_capable(dig_port, &capable); } else { - if (!intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv)) + if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) capable = true; } @@ -86,7 +86,7 @@ bool intel_hdcp_capable(struct intel_connector *connector) /* Is HDCP2.2 capable on Platform and Sink */ bool intel_hdcp2_capable(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; bool capable = false; @@ -104,7 +104,7 @@ bool intel_hdcp2_capable(struct intel_connector *connector) mutex_unlock(&dev_priv->hdcp_comp_mutex); /* Sink's capability for HDCP2.2 */ - hdcp->shim->hdcp_2_2_capable(intel_dig_port, &capable); + hdcp->shim->hdcp_2_2_capable(dig_port, &capable); return capable; } @@ -125,14 +125,14 @@ static bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv, LINK_ENCRYPTION_STATUS; } -static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port, +static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, const struct intel_hdcp_shim *shim) { int ret, read_ret; bool ksv_ready; /* Poll for ksv list ready (spec says max time allowed is 5s) */ - ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port, + ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready), read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 100 * 1000); @@ -300,16 +300,16 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, const struct intel_hdcp_shim *shim, u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; u32 vprime, sha_text, sha_leftovers, rep_ctl; int ret, i, j, sha_idx; /* Process V' values from the receiver */ for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { - ret = shim->read_v_prime_part(intel_dig_port, i, &vprime); + ret = shim->read_v_prime_part(dig_port, i, &vprime); if (ret) return ret; intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime); @@ -528,20 +528,20 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, static int intel_hdcp_auth_downstream(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); const struct intel_hdcp_shim *shim = connector->hdcp.shim; u8 bstatus[2], num_downstream, *ksv_fifo; int ret, i, tries = 3; - ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim); + ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); if (ret) { drm_dbg_kms(&dev_priv->drm, "KSV list failed to become ready (%d)\n", ret); return ret; } - ret = shim->read_bstatus(intel_dig_port, bstatus); + ret = shim->read_bstatus(dig_port, bstatus); if (ret) return ret; @@ -571,7 +571,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) return -ENOMEM; } - ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo); + ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); if (ret) goto err; @@ -611,12 +611,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) /* Implements Part 1 of the HDCP authorization procedure */ static int intel_hdcp_auth(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; const struct intel_hdcp_shim *shim = hdcp->shim; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; unsigned long r0_prime_gen_start; int ret, i, tries = 2; union { @@ -640,7 +640,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) * displays, this is not necessary. */ if (shim->hdcp_capable) { - ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable); + ret = shim->hdcp_capable(dig_port, &hdcp_capable); if (ret) return ret; if (!hdcp_capable) { @@ -670,7 +670,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) HDCP_ANLO(dev_priv, cpu_transcoder, port)); an.reg[1] = intel_de_read(dev_priv, HDCP_ANHI(dev_priv, cpu_transcoder, port)); - ret = shim->write_an_aksv(intel_dig_port, an.shim); + ret = shim->write_an_aksv(dig_port, an.shim); if (ret) return ret; @@ -678,7 +678,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) memset(&bksv, 0, sizeof(bksv)); - ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim); + ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); if (ret < 0) return ret; @@ -692,14 +692,14 @@ static int intel_hdcp_auth(struct intel_connector *connector) intel_de_write(dev_priv, HDCP_BKSVHI(dev_priv, cpu_transcoder, port), bksv.reg[1]); - ret = shim->repeater_present(intel_dig_port, &repeater_present); + ret = shim->repeater_present(dig_port, &repeater_present); if (ret) return ret; if (repeater_present) intel_de_write(dev_priv, HDCP_REP_CTL, intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port)); - ret = shim->toggle_signalling(intel_dig_port, true); + ret = shim->toggle_signalling(dig_port, true); if (ret) return ret; @@ -732,7 +732,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) */ for (i = 0; i < tries; i++) { ri.reg = 0; - ret = shim->read_ri_prime(intel_dig_port, ri.shim); + ret = shim->read_ri_prime(dig_port, ri.shim); if (ret) return ret; intel_de_write(dev_priv, @@ -776,10 +776,10 @@ static int intel_hdcp_auth(struct intel_connector *connector) static int _intel_hdcp_disable(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; @@ -796,7 +796,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) return -ETIMEDOUT; } - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); + ret = hdcp->shim->toggle_signalling(dig_port, false); if (ret) { drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n"); return ret; @@ -859,10 +859,10 @@ static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) /* Implements Part 3 of the HDCP authorization procedure */ static int intel_hdcp_check_link(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder; int ret = 0; @@ -888,7 +888,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; } - if (hdcp->shim->check_link(intel_dig_port)) { + if (hdcp->shim->check_link(dig_port)) { if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; schedule_work(&hdcp->prop_work); @@ -1242,7 +1242,7 @@ static int hdcp2_deauthenticate_port(struct intel_connector *connector) /* Authentication flow starts from here */ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; union { @@ -1264,12 +1264,12 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) if (ret < 0) return ret; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.ake_init, + ret = shim->write_2_2_msg(dig_port, &msgs.ake_init, sizeof(msgs.ake_init)); if (ret < 0) return ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_CERT, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_CERT, &msgs.send_cert, sizeof(msgs.send_cert)); if (ret < 0) return ret; @@ -1298,11 +1298,11 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) if (ret < 0) return ret; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.no_stored_km, size); + ret = shim->write_2_2_msg(dig_port, &msgs.no_stored_km, size); if (ret < 0) return ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_HPRIME, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_HPRIME, &msgs.send_hprime, sizeof(msgs.send_hprime)); if (ret < 0) return ret; @@ -1313,7 +1313,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) if (!hdcp->is_paired) { /* Pairing is required */ - ret = shim->read_2_2_msg(intel_dig_port, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_PAIRING_INFO, &msgs.pairing_info, sizeof(msgs.pairing_info)); @@ -1331,7 +1331,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) static int hdcp2_locality_check(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; union { struct hdcp2_lc_init lc_init; @@ -1345,12 +1345,12 @@ static int hdcp2_locality_check(struct intel_connector *connector) if (ret < 0) continue; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.lc_init, + ret = shim->write_2_2_msg(dig_port, &msgs.lc_init, sizeof(msgs.lc_init)); if (ret < 0) continue; - ret = shim->read_2_2_msg(intel_dig_port, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_LC_SEND_LPRIME, &msgs.send_lprime, sizeof(msgs.send_lprime)); @@ -1367,7 +1367,7 @@ static int hdcp2_locality_check(struct intel_connector *connector) static int hdcp2_session_key_exchange(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; struct hdcp2_ske_send_eks send_eks; int ret; @@ -1376,7 +1376,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) if (ret < 0) return ret; - ret = hdcp->shim->write_2_2_msg(intel_dig_port, &send_eks, + ret = hdcp->shim->write_2_2_msg(dig_port, &send_eks, sizeof(send_eks)); if (ret < 0) return ret; @@ -1387,7 +1387,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) static int hdcp2_propagate_stream_management_info(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; union { @@ -1409,12 +1409,12 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector) msgs.stream_manage.streams[0].stream_type = hdcp->content_type; /* Send it to Repeater */ - ret = shim->write_2_2_msg(intel_dig_port, &msgs.stream_manage, + ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage, sizeof(msgs.stream_manage)); if (ret < 0) return ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_STREAM_READY, &msgs.stream_ready, sizeof(msgs.stream_ready)); if (ret < 0) return ret; @@ -1439,7 +1439,7 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector) static int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; union { @@ -1451,7 +1451,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) u8 *rx_info; int ret; - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, &msgs.recvid_list, sizeof(msgs.recvid_list)); if (ret < 0) return ret; @@ -1496,7 +1496,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) return ret; hdcp->seq_num_v = seq_num_v; - ret = shim->write_2_2_msg(intel_dig_port, &msgs.rep_ack, + ret = shim->write_2_2_msg(dig_port, &msgs.rep_ack, sizeof(msgs.rep_ack)); if (ret < 0) return ret; @@ -1517,7 +1517,7 @@ static int hdcp2_authenticate_repeater(struct intel_connector *connector) static int hdcp2_authenticate_sink(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; const struct intel_hdcp_shim *shim = hdcp->shim; @@ -1543,7 +1543,7 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) } if (shim->config_stream_type) { - ret = shim->config_stream_type(intel_dig_port, + ret = shim->config_stream_type(dig_port, hdcp->is_repeater, hdcp->content_type); if (ret < 0) @@ -1569,10 +1569,10 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) static int hdcp2_enable_encryption(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; @@ -1580,7 +1580,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & LINK_ENCRYPTION_STATUS); if (hdcp->shim->toggle_signalling) { - ret = hdcp->shim->toggle_signalling(intel_dig_port, true); + ret = hdcp->shim->toggle_signalling(dig_port, true); if (ret) { drm_err(&dev_priv->drm, "Failed to enable HDCP signalling. %d\n", @@ -1608,10 +1608,10 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) static int hdcp2_disable_encryption(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; @@ -1630,7 +1630,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout"); if (hdcp->shim->toggle_signalling) { - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); + ret = hdcp->shim->toggle_signalling(dig_port, false); if (ret) { drm_err(&dev_priv->drm, "Failed to disable HDCP signalling. %d\n", @@ -1723,10 +1723,10 @@ static int _intel_hdcp2_disable(struct intel_connector *connector) /* Implements the Link Integrity Check for HDCP2.2 */ static int intel_hdcp2_check_link(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = intel_dig_port->base.port; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder; int ret = 0; @@ -1751,7 +1751,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) goto out; } - ret = hdcp->shim->check_2_2_link(intel_dig_port); + ret = hdcp->shim->check_2_2_link(dig_port); if (ret == HDCP_LINK_PROTECTED) { if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a31a98d26882..414a0de2aab3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -88,10 +88,10 @@ assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) { - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = container_of(&encoder->base, struct intel_digital_port, base.base); - return &intel_dig_port->hdmi; + return &dig_port->hdmi; } static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) @@ -660,7 +660,7 @@ static void intel_write_infoframe(struct intel_encoder *encoder, enum hdmi_infoframe_type type, const union hdmi_infoframe *frame) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u8 buffer[VIDEO_DIP_DATA_SIZE]; ssize_t len; @@ -681,7 +681,7 @@ static void intel_write_infoframe(struct intel_encoder *encoder, buffer[3] = 0; len++; - intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); + dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); } void intel_read_infoframe(struct intel_encoder *encoder, @@ -689,7 +689,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, enum hdmi_infoframe_type type, union hdmi_infoframe *frame) { - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u8 buffer[VIDEO_DIP_DATA_SIZE]; int ret; @@ -697,7 +697,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, intel_hdmi_infoframe_enable(type)) == 0) return; - intel_dig_port->read_infoframe(encoder, crtc_state, + dig_port->read_infoframe(encoder, crtc_state, type, buffer, sizeof(buffer)); /* Fill the 'hole' (see big comment above) at position 3 */ @@ -872,8 +872,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; i915_reg_t reg = VIDEO_DIP_CTL; u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1057,8 +1057,8 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1275,11 +1275,11 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) adapter, enable); } -static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, +static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, unsigned int offset, void *buffer, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; @@ -1304,11 +1304,11 @@ static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, return ret >= 0 ? -EIO : ret; } -static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, +static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, unsigned int offset, void *buffer, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; @@ -1338,16 +1338,16 @@ static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, u8 *an) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; - ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, + ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, DRM_HDCP_AN_LEN); if (ret) { drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", @@ -1363,13 +1363,13 @@ int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, return 0; } -static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, +static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, u8 *bksv) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, DRM_HDCP_KSV_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", @@ -1378,13 +1378,13 @@ static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, u8 *bstatus) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, bstatus, DRM_HDCP_BSTATUS_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", @@ -1393,14 +1393,14 @@ int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, bool *repeater_present) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; u8 val; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); if (ret) { drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", ret); @@ -1411,13 +1411,13 @@ int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, u8 *ri_prime) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, ri_prime, DRM_HDCP_RI_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", @@ -1426,14 +1426,14 @@ int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, bool *ksv_ready) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; u8 val; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); if (ret) { drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", ret); @@ -1444,12 +1444,12 @@ int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, int num_downstream, u8 *ksv_fifo) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); if (ret) { drm_dbg_kms(&i915->drm, @@ -1460,16 +1460,16 @@ int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, int i, u32 *part) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); int ret; if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) return -EINVAL; - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), part, DRM_HDCP_V_PRIME_PART_LEN); if (ret) drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", @@ -1480,7 +1480,7 @@ int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); struct drm_crtc *crtc = connector->base.state->crtc; struct intel_crtc *intel_crtc = container_of(crtc, struct intel_crtc, base); @@ -1494,13 +1494,13 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) usleep_range(25, 50); } - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, false); if (ret) { drm_err(&dev_priv->drm, "Disable HDCP signalling failed (%d)\n", ret); return ret; } - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, true); if (ret) { drm_err(&dev_priv->drm, "Enable HDCP signalling failed (%d)\n", ret); @@ -1511,10 +1511,10 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) } static -int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, bool enable) { - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct intel_hdmi *hdmi = &dig_port->hdmi; struct intel_connector *connector = hdmi->attached_connector; struct drm_i915_private *dev_priv = to_i915(connector->base.dev); int ret; @@ -1522,7 +1522,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, if (!enable) usleep_range(6, 60); /* Bspec says >= 6us */ - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, enable); if (ret) { drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", enable ? "Enable" : "Disable", ret); @@ -1540,12 +1540,12 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, } static -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); struct intel_connector *connector = - intel_dig_port->hdmi.attached_connector; - enum port port = intel_dig_port->base.port; + dig_port->hdmi.attached_connector; + enum port port = dig_port->base.port; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; int ret; union { @@ -1553,7 +1553,7 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) u8 shim[DRM_HDCP_RI_LEN]; } ri; - ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); + ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); if (ret) return false; @@ -1586,10 +1586,10 @@ static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { }; static -int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, u8 *rx_status) { - return intel_hdmi_hdcp_read(intel_dig_port, + return intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, rx_status, HDCP_2_2_HDMI_RXSTATUS_LEN); @@ -1615,15 +1615,15 @@ static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) } static int -hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, +hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, u8 msg_id, bool *msg_ready, ssize_t *msg_sz) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; int ret; - ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); + ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); if (ret < 0) { drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", ret); @@ -1643,10 +1643,10 @@ hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, } static ssize_t -intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, +intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, u8 msg_id, bool paired) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); bool msg_ready = false; int timeout, ret; ssize_t msg_sz = 0; @@ -1655,7 +1655,7 @@ intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, if (timeout < 0) return timeout; - ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, + ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, msg_id, &msg_ready, &msg_sz), !ret && msg_ready && msg_sz, timeout * 1000, @@ -1668,26 +1668,26 @@ intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, void *buf, size_t size) { unsigned int offset; offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; - return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); + return intel_hdmi_hdcp_write(dig_port, offset, buf, size); } static -int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, u8 msg_id, void *buf, size_t size) { - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_hdmi *hdmi = &dig_port->hdmi; struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; unsigned int offset; ssize_t ret; - ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, + ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, hdcp->is_paired); if (ret < 0) return ret; @@ -1704,7 +1704,7 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, } offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; - ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); + ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); if (ret) drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", msg_id, ret); @@ -1713,12 +1713,12 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, } static -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port) { u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; int ret; - ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); + ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); if (ret) return ret; @@ -1735,14 +1735,14 @@ int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) } static -int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, +int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, bool *capable) { u8 hdcp2_version; int ret; *capable = false; - ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, + ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, &hdcp2_version, sizeof(hdcp2_version)); if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) *capable = true; @@ -2050,7 +2050,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = hdmi_to_dig_port(intel_hdmi); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); u32 temp; @@ -2094,7 +2094,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } - intel_dig_port->set_infoframes(encoder, + dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); @@ -2709,12 +2709,12 @@ static void intel_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_hdmi_prepare(encoder, pipe_config); - intel_dig_port->set_infoframes(encoder, + dig_port->set_infoframes(encoder, pipe_config->has_infoframe, pipe_config, conn_state); } @@ -2724,7 +2724,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); vlv_phy_pre_encoder_enable(encoder, pipe_config); @@ -2733,13 +2733,13 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 0x2b247878); - dport->set_infoframes(encoder, + dig_port->set_infoframes(encoder, pipe_config->has_infoframe, pipe_config, conn_state); g4x_enable_hdmi(state, encoder, pipe_config, conn_state); - vlv_wait_port_ready(dev_priv, dport, 0x0); + vlv_wait_port_ready(dev_priv, dig_port, 0x0); } static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, @@ -2800,7 +2800,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_digital_port *dport = enc_to_dig_port(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -2810,13 +2810,13 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, /* Use 800mV-0dB */ chv_set_phy_signal_level(encoder, 128, 102, false); - dport->set_infoframes(encoder, + dig_port->set_infoframes(encoder, pipe_config->has_infoframe, pipe_config, conn_state); g4x_enable_hdmi(state, encoder, pipe_config, conn_state); - vlv_wait_port_ready(dev_priv, dport, 0x0); + vlv_wait_port_ready(dev_priv, dig_port, 0x0); /* Second common lane will stay alive on its own now */ chv_phy_release_cl2_override(encoder); @@ -2910,7 +2910,7 @@ static void intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->dev); - struct intel_digital_port *intel_dig_port = + struct intel_digital_port *dig_port = hdmi_to_dig_port(intel_hdmi); intel_attach_force_audio_property(connector); @@ -2922,7 +2922,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c * ToDo: This needs to be extended for LSPCON implementation * as well. Will be implemented separately. */ - if (!intel_dig_port->lspcon.active) + if (!dig_port->lspcon.active) intel_attach_colorspace_property(connector); drm_connector_attach_content_type_property(connector); @@ -3159,52 +3159,52 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) return ddc_pin; } -void intel_infoframe_init(struct intel_digital_port *intel_dig_port) +void intel_infoframe_init(struct intel_digital_port *dig_port) { struct drm_i915_private *dev_priv = - to_i915(intel_dig_port->base.base.dev); + to_i915(dig_port->base.base.dev); if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - intel_dig_port->write_infoframe = vlv_write_infoframe; - intel_dig_port->read_infoframe = vlv_read_infoframe; - intel_dig_port->set_infoframes = vlv_set_infoframes; - intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; + dig_port->write_infoframe = vlv_write_infoframe; + dig_port->read_infoframe = vlv_read_infoframe; + dig_port->set_infoframes = vlv_set_infoframes; + dig_port->infoframes_enabled = vlv_infoframes_enabled; } else if (IS_G4X(dev_priv)) { - intel_dig_port->write_infoframe = g4x_write_infoframe; - intel_dig_port->read_infoframe = g4x_read_infoframe; - intel_dig_port->set_infoframes = g4x_set_infoframes; - intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; + dig_port->write_infoframe = g4x_write_infoframe; + dig_port->read_infoframe = g4x_read_infoframe; + dig_port->set_infoframes = g4x_set_infoframes; + dig_port->infoframes_enabled = g4x_infoframes_enabled; } else if (HAS_DDI(dev_priv)) { - if (intel_dig_port->lspcon.active) { - intel_dig_port->write_infoframe = lspcon_write_infoframe; - intel_dig_port->read_infoframe = lspcon_read_infoframe; - intel_dig_port->set_infoframes = lspcon_set_infoframes; - intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; + if (dig_port->lspcon.active) { + dig_port->write_infoframe = lspcon_write_infoframe; + dig_port->read_infoframe = lspcon_read_infoframe; + dig_port->set_infoframes = lspcon_set_infoframes; + dig_port->infoframes_enabled = lspcon_infoframes_enabled; } else { - intel_dig_port->write_infoframe = hsw_write_infoframe; - intel_dig_port->read_infoframe = hsw_read_infoframe; - intel_dig_port->set_infoframes = hsw_set_infoframes; - intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; + dig_port->write_infoframe = hsw_write_infoframe; + dig_port->read_infoframe = hsw_read_infoframe; + dig_port->set_infoframes = hsw_set_infoframes; + dig_port->infoframes_enabled = hsw_infoframes_enabled; } } else if (HAS_PCH_IBX(dev_priv)) { - intel_dig_port->write_infoframe = ibx_write_infoframe; - intel_dig_port->read_infoframe = ibx_read_infoframe; - intel_dig_port->set_infoframes = ibx_set_infoframes; - intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; + dig_port->write_infoframe = ibx_write_infoframe; + dig_port->read_infoframe = ibx_read_infoframe; + dig_port->set_infoframes = ibx_set_infoframes; + dig_port->infoframes_enabled = ibx_infoframes_enabled; } else { - intel_dig_port->write_infoframe = cpt_write_infoframe; - intel_dig_port->read_infoframe = cpt_read_infoframe; - intel_dig_port->set_infoframes = cpt_set_infoframes; - intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; + dig_port->write_infoframe = cpt_write_infoframe; + dig_port->read_infoframe = cpt_read_infoframe; + dig_port->set_infoframes = cpt_set_infoframes; + dig_port->infoframes_enabled = cpt_infoframes_enabled; } } -void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, +void intel_hdmi_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector) { struct drm_connector *connector = &intel_connector->base; - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; - struct intel_encoder *intel_encoder = &intel_dig_port->base; + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; + struct intel_encoder *intel_encoder = &dig_port->base; struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct i2c_adapter *ddc; @@ -3218,9 +3218,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) return; - if (drm_WARN(dev, intel_dig_port->max_lanes < 4, + if (drm_WARN(dev, dig_port->max_lanes < 4, "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, + dig_port->max_lanes, intel_encoder->base.base.id, intel_encoder->base.name)) return; @@ -3309,21 +3309,21 @@ intel_hdmi_hotplug(struct intel_encoder *encoder, void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, enum port port) { - struct intel_digital_port *intel_dig_port; + struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; struct intel_connector *intel_connector; - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); - if (!intel_dig_port) + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); + if (!dig_port) return; intel_connector = intel_connector_alloc(); if (!intel_connector) { - kfree(intel_dig_port); + kfree(dig_port); return; } - intel_encoder = &intel_dig_port->base; + intel_encoder = &dig_port->base; drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, @@ -3380,12 +3380,12 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, if (IS_G4X(dev_priv)) intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; - intel_dig_port->hdmi.hdmi_reg = hdmi_reg; - intel_dig_port->dp.output_reg = INVALID_MMIO_REG; - intel_dig_port->max_lanes = 4; + dig_port->hdmi.hdmi_reg = hdmi_reg; + dig_port->dp.output_reg = INVALID_MMIO_REG; + dig_port->max_lanes = 4; - intel_infoframe_init(intel_dig_port); + intel_infoframe_init(dig_port); - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); - intel_hdmi_init_connector(intel_dig_port, intel_connector); + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); + intel_hdmi_init_connector(dig_port, intel_connector); } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 8ff1f76a63df..213ff24befde 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -25,7 +25,7 @@ enum port; void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, enum port port); -void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, +void intel_hdmi_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder); int intel_hdmi_compute_config(struct intel_encoder *encoder, @@ -36,7 +36,7 @@ bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, bool high_tmds_clock_ratio, bool scrambling); void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); -void intel_infoframe_init(struct intel_digital_port *intel_dig_port); +void intel_infoframe_init(struct intel_digital_port *dig_port); u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); u32 intel_hdmi_infoframe_enable(unsigned int type); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 6ff7b226f0a1..b781bf469644 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -550,11 +550,11 @@ void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); } -bool lspcon_init(struct intel_digital_port *intel_dig_port) +bool lspcon_init(struct intel_digital_port *dig_port) { - struct intel_dp *dp = &intel_dig_port->dp; - struct intel_lspcon *lspcon = &intel_dig_port->lspcon; - struct drm_device *dev = intel_dig_port->base.base.dev; + struct intel_dp *dp = &dig_port->dp; + struct intel_lspcon *lspcon = &dig_port->lspcon; + struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct drm_connector *connector = &dp->attached_connector->base; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index 37cfddf8a9c5..1cffe8a42a08 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -15,7 +15,7 @@ struct intel_digital_port; struct intel_encoder; struct intel_lspcon; -bool lspcon_init(struct intel_digital_port *intel_dig_port); +bool lspcon_init(struct intel_digital_port *dig_port); void lspcon_resume(struct intel_lspcon *lspcon); void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); void lspcon_write_infoframe(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 86bf7a76f93d..78762627a8ba 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -905,8 +905,8 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, const struct drm_connector_state *conn_state) { struct intel_dp *intel_dp = dev_priv->psr.dp; - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); - struct intel_encoder *encoder = &intel_dig_port->base; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; u32 val; drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index d145fe2bed81..c5735c365659 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1045,7 +1045,7 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; @@ -1055,9 +1055,9 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); - intel_dig_port->write_infoframe(encoder, crtc_state, - DP_SDP_PPS, &dp_dsc_pps_sdp, - sizeof(dp_dsc_pps_sdp)); + dig_port->write_infoframe(encoder, crtc_state, + DP_SDP_PPS, &dp_dsc_pps_sdp, + sizeof(dp_dsc_pps_sdp)); } void intel_dsc_enable(struct intel_encoder *encoder, -- 2.26.2 From drinkcat at chromium.org Sat Jun 27 07:03:03 2020 From: drinkcat at chromium.org (Nicolas Boichat) Date: Sat, 27 Jun 2020 15:03:03 +0800 Subject: [Intel-gfx] [PATCH 0/4] Detect and remove trace_printk Message-ID: <20200627070307.516803-1-drinkcat@chromium.org> trace_printk is meant as a debugging tool, and should not be compiled into production code without specific debug Kconfig options enabled or source code changes. Patches 1 to 3 remove/disable trace_printk that should not be enabled by default. Patch 4 adds a config option that can be used to detect such trace_printk at compile time (instead of printing a nasty warning at runtime). Nicolas Boichat (4): usb: cdns3: gadget: Replace trace_printk by dev_dbg media: atomisp: Replace trace_printk by pr_info media: camss: vfe: Use trace_printk for debugging only kernel/trace: Add TRACING_ALLOW_PRINTK config option drivers/gpu/drm/i915/Kconfig.debug | 4 ++-- .../media/platform/qcom/camss/camss-vfe-4-1.c | 2 ++ .../media/platform/qcom/camss/camss-vfe-4-7.c | 2 ++ drivers/staging/media/atomisp/pci/hmm/hmm.c | 10 +++++----- drivers/usb/cdns3/gadget.c | 2 +- fs/f2fs/Kconfig | 1 + include/linux/kernel.h | 17 ++++++++++++++++- kernel/trace/Kconfig | 10 ++++++++++ samples/Kconfig | 2 ++ 9 files changed, 41 insertions(+), 9 deletions(-) -- 2.27.0.212.ge8ba1cc988-goog From drinkcat at chromium.org Sat Jun 27 07:03:04 2020 From: drinkcat at chromium.org (Nicolas Boichat) Date: Sat, 27 Jun 2020 15:03:04 +0800 Subject: [Intel-gfx] [PATCH 1/4] usb: cdns3: gadget: Replace trace_printk by dev_dbg In-Reply-To: <20200627070307.516803-1-drinkcat@chromium.org> References: <20200627070307.516803-1-drinkcat@chromium.org> Message-ID: <20200627070307.516803-2-drinkcat@chromium.org> trace_printk should not be used in production code, replace it call with dev_dbg. Signed-off-by: Nicolas Boichat <drinkcat at chromium.org> --- Unclear why a trace_printk was used in the first place, it's possible that some rate-limiting is necessary here. drivers/usb/cdns3/gadget.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 5e24c2e57c0d8c8..c303ab7c62d1651 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -421,7 +421,7 @@ static int cdns3_start_all_request(struct cdns3_device *priv_dev, if ((priv_req->flags & REQUEST_INTERNAL) || (priv_ep->flags & EP_TDLCHK_EN) || priv_ep->use_streams) { - trace_printk("Blocking external request\n"); + dev_dbg(priv_dev->dev, "Blocking external request\n"); return ret; } } -- 2.27.0.212.ge8ba1cc988-goog From drinkcat at chromium.org Sat Jun 27 07:03:05 2020 From: drinkcat at chromium.org (Nicolas Boichat) Date: Sat, 27 Jun 2020 15:03:05 +0800 Subject: [Intel-gfx] [PATCH 2/4] media: atomisp: Replace trace_printk by pr_info In-Reply-To: <20200627070307.516803-1-drinkcat@chromium.org> References: <20200627070307.516803-1-drinkcat@chromium.org> Message-ID: <20200627070307.516803-3-drinkcat@chromium.org> trace_printk should not be used in production code, replace it call with pr_info. Signed-off-by: Nicolas Boichat <drinkcat at chromium.org> --- drivers/staging/media/atomisp/pci/hmm/hmm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/atomisp/pci/hmm/hmm.c b/drivers/staging/media/atomisp/pci/hmm/hmm.c index 42fef17798622f1..2bd39b4939f16d2 100644 --- a/drivers/staging/media/atomisp/pci/hmm/hmm.c +++ b/drivers/staging/media/atomisp/pci/hmm/hmm.c @@ -735,11 +735,11 @@ ia_css_ptr hmm_host_vaddr_to_hrt_vaddr(const void *ptr) void hmm_show_mem_stat(const char *func, const int line) { - trace_printk("tol_cnt=%d usr_size=%d res_size=%d res_cnt=%d sys_size=%d dyc_thr=%d dyc_size=%d.\n", - hmm_mem_stat.tol_cnt, - hmm_mem_stat.usr_size, hmm_mem_stat.res_size, - hmm_mem_stat.res_cnt, hmm_mem_stat.sys_size, - hmm_mem_stat.dyc_thr, hmm_mem_stat.dyc_size); + pr_info("tol_cnt=%d usr_size=%d res_size=%d res_cnt=%d sys_size=%d dyc_thr=%d dyc_size=%d.\n", + hmm_mem_stat.tol_cnt, + hmm_mem_stat.usr_size, hmm_mem_stat.res_size, + hmm_mem_stat.res_cnt, hmm_mem_stat.sys_size, + hmm_mem_stat.dyc_thr, hmm_mem_stat.dyc_size); } void hmm_init_mem_stat(int res_pgnr, int dyc_en, int dyc_pgnr) -- 2.27.0.212.ge8ba1cc988-goog From drinkcat at chromium.org Sat Jun 27 07:03:06 2020 From: drinkcat at chromium.org (Nicolas Boichat) Date: Sat, 27 Jun 2020 15:03:06 +0800 Subject: [Intel-gfx] [PATCH 3/4] media: camss: vfe: Use trace_printk for debugging only In-Reply-To: <20200627070307.516803-1-drinkcat@chromium.org> References: <20200627070307.516803-1-drinkcat@chromium.org> Message-ID: <20200627070307.516803-4-drinkcat@chromium.org> trace_printk should not be used in production code. Since tracing interrupts is presumably latency sensitive, pr_dbg is not appropriate, so guard the call with a preprocessor symbol that can be defined for debugging purpose. Signed-off-by: Nicolas Boichat <drinkcat at chromium.org> --- drivers/media/platform/qcom/camss/camss-vfe-4-1.c | 2 ++ drivers/media/platform/qcom/camss/camss-vfe-4-7.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c index 174a36be6f5d866..0c57171fae4f9e9 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c @@ -936,8 +936,10 @@ static irqreturn_t vfe_isr(int irq, void *dev) vfe->ops->isr_read(vfe, &value0, &value1); +#ifdef CAMSS_VFE_TRACE_IRQ trace_printk("VFE: status0 = 0x%08x, status1 = 0x%08x\n", value0, value1); +#endif if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) vfe->isr_ops.reset_ack(vfe); diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c index 0dca8bf9281e774..307675925e5c779 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c @@ -1058,8 +1058,10 @@ static irqreturn_t vfe_isr(int irq, void *dev) vfe->ops->isr_read(vfe, &value0, &value1); +#ifdef CAMSS_VFE_TRACE_IRQ trace_printk("VFE: status0 = 0x%08x, status1 = 0x%08x\n", value0, value1); +#endif if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) vfe->isr_ops.reset_ack(vfe); -- 2.27.0.212.ge8ba1cc988-goog From drinkcat at chromium.org Sat Jun 27 07:03:07 2020 From: drinkcat at chromium.org (Nicolas Boichat) Date: Sat, 27 Jun 2020 15:03:07 +0800 Subject: [Intel-gfx] [PATCH v2 4/4] kernel/trace: Add TRACING_ALLOW_PRINTK config option In-Reply-To: <20200627070307.516803-1-drinkcat@chromium.org> References: <20200627070307.516803-1-drinkcat@chromium.org> Message-ID: <20200627070307.516803-5-drinkcat@chromium.org> trace_printk is meant as a debugging tool, and should not be compiled into production code without specific debug Kconfig options enabled, or source code changes, as indicated by the warning that shows up on boot if any trace_printk is called: ** NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE NOTICE ** ** ** ** trace_printk() being used. Allocating extra memory. ** ** ** ** This means that this is a DEBUG kernel and it is ** ** unsafe for production use. ** If this option is set to n, the kernel will generate a build-time error if trace_printk is used. Note that the code to handle trace_printk is still present, so this does not prevent people from compiling out-of-tree kernel modules with the option set to =y, or BPF programs. Signed-off-by: Nicolas Boichat <drinkcat at chromium.org> --- Changes since v1: - Use static_assert instead of __static_assert (Jason Gunthorpe) - Fix issues that can be detected by this patch (running some randconfig in a loop, kernel test robot, or manual inspection), by: - Making some debug config options that use trace_printk depend on the new config option. - Adding 3 patches before this one. There is a question from Alexei whether the warning is warranted, and it's possibly too strongly worded, but the fact is, we do not want trace_printk to be sprinkled in kernel code by default, unless a very specific Kconfig command is enabled (or preprocessor macro). There's at least 3 reasons that I can come up with: 1. trace_printk introduces some overhead. 2. If the kernel keeps adding always-enabled trace_printk, it will be much harder for developers to make use of trace_printk for debugging. 3. People may assume that trace_printk is for debugging only, and may accidentally output sensitive data (theoritical at this stage). drivers/gpu/drm/i915/Kconfig.debug | 4 ++-- fs/f2fs/Kconfig | 1 + include/linux/kernel.h | 17 ++++++++++++++++- kernel/trace/Kconfig | 10 ++++++++++ samples/Kconfig | 2 ++ 5 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 1cb28c20807c59d..fa30f9bdc82311f 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -84,7 +84,7 @@ config DRM_I915_ERRLOG_GEM config DRM_I915_TRACE_GEM bool "Insert extra ftrace output from the GEM internals" depends on DRM_I915_DEBUG_GEM - select TRACING + depends on TRACING_ALLOW_PRINTK default n help Enable additional and verbose debugging output that will spam @@ -98,7 +98,7 @@ config DRM_I915_TRACE_GEM config DRM_I915_TRACE_GTT bool "Insert extra ftrace output from the GTT internals" depends on DRM_I915_DEBUG_GEM - select TRACING + depends on TRACING_ALLOW_PRINTK default n help Enable additional and verbose debugging output that will spam diff --git a/fs/f2fs/Kconfig b/fs/f2fs/Kconfig index d13c5c6a978769b..d161d96cc1b7418 100644 --- a/fs/f2fs/Kconfig +++ b/fs/f2fs/Kconfig @@ -80,6 +80,7 @@ config F2FS_IO_TRACE bool "F2FS IO tracer" depends on F2FS_FS depends on FUNCTION_TRACER + depends on TRACING_ALLOW_PRINTK help F2FS IO trace is based on a function trace, which gathers process information and block IO patterns in the filesystem level. diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 196607aaf653082..8abce95b0c95a0e 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -721,10 +721,15 @@ do { \ #define trace_printk(fmt, ...) \ do { \ char _______STR[] = __stringify((__VA_ARGS__)); \ + \ + static_assert( \ + IS_ENABLED(CONFIG_TRACING_ALLOW_PRINTK),\ + "trace_printk called, please enable CONFIG_TRACING_ALLOW_PRINTK."); \ + \ if (sizeof(_______STR) > 3) \ do_trace_printk(fmt, ##__VA_ARGS__); \ else \ - trace_puts(fmt); \ + do_trace_puts(fmt); \ } while (0) #define do_trace_printk(fmt, args...) \ @@ -773,6 +778,13 @@ int __trace_printk(unsigned long ip, const char *fmt, ...); */ #define trace_puts(str) ({ \ + static_assert( \ + IS_ENABLED(CONFIG_TRACING_ALLOW_PRINTK), \ + "trace_puts called, please enable CONFIG_TRACING_ALLOW_PRINTK."); \ + do_trace_puts(str); \ +}) + +#define do_trace_puts(str) ({ \ static const char *trace_printk_fmt __used \ __attribute__((section("__trace_printk_fmt"))) = \ __builtin_constant_p(str) ? str : NULL; \ @@ -794,6 +806,9 @@ extern void trace_dump_stack(int skip); */ #define ftrace_vprintk(fmt, vargs) \ do { \ + static_assert( \ + IS_ENABLED(CONFIG_TRACING_ALLOW_PRINTK), \ + "ftrace_vprintk called, please enable CONFIG_TRACING_ALLOW_PRINTK."); \ if (__builtin_constant_p(fmt)) { \ static const char *trace_printk_fmt __used \ __attribute__((section("__trace_printk_fmt"))) = \ diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index a4020c0b4508c99..971b6035b197823 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -111,6 +111,15 @@ config GENERIC_TRACER bool select TRACING +config TRACING_ALLOW_PRINTK + bool "Allow trace_printk" + default y if DEBUG_KERNEL + depends on TRACING + help + trace_printk is only meant as a debugging tool. If this option is + set to n, the kernel will generate a build-time error if trace_printk + is used. + # # Minimum requirements an architecture has to meet for us to # be able to offer generic tracing facilities: @@ -686,6 +695,7 @@ config TRACEPOINT_BENCHMARK config RING_BUFFER_BENCHMARK tristate "Ring buffer benchmark stress tester" depends on RING_BUFFER + depends on TRACING_ALLOW_PRINTK help This option creates a test to stress the ring buffer and benchmark it. It creates its own ring buffer such that it will not interfere with diff --git a/samples/Kconfig b/samples/Kconfig index 0ed6e4d71d87b16..6b1ade57f00dd5d 100644 --- a/samples/Kconfig +++ b/samples/Kconfig @@ -19,6 +19,7 @@ config SAMPLE_TRACE_EVENTS config SAMPLE_TRACE_PRINTK tristate "Build trace_printk module - tests various trace_printk formats" depends on EVENT_TRACING && m + depends on TRACING_ALLOW_PRINTK help This builds a module that calls trace_printk() and can be used to test various trace_printk() calls from a module. @@ -26,6 +27,7 @@ config SAMPLE_TRACE_PRINTK config SAMPLE_FTRACE_DIRECT tristate "Build register_ftrace_direct() example" depends on DYNAMIC_FTRACE_WITH_DIRECT_CALLS && m + depends on TRACING_ALLOW_PRINTK depends on X86_64 # has x86_64 inlined asm help This builds an ftrace direct function example -- 2.27.0.212.ge8ba1cc988-goog From patchwork at emeril.freedesktop.org Sat Jun 27 08:13:32 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 08:13:32 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Move_some_device_capabilities_under_intel=5Fgt?= In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <159324561259.5394.7769709589699311984@emeril.freedesktop.org> == Series Details == Series: Move some device capabilities under intel_gt URL : https://patchwork.freedesktop.org/series/78829/ State : warning == Summary == $ dim checkpatch origin/drm-tip 999ecfc5fc75 drm/i915: Convert device_info to uncore/de_read cb6b1a857f72 drm/i915: Use the gt in HAS_ENGINE 72189c790177 drm/i915: Move engine-related mmio init to engines_init_mmio f77f0e80766d drm/i915: Move the engine mask to intel_gt_info 09b520c7dacc drm/i915: Introduce gt_init_mmio 5ba87fdd277d drm/i915/sseu: Move sseu detection and dump to intel_sseu -:285: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line #285: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:311: + * across subslices. + */ -:294: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line #294: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:320: + * more than one EU pair per subslice. + */ -:320: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line #320: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:346: + * to each of the enabled slices. + */ -:328: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line #328: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:354: + * count the total enabled EU. + */ -:370: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line #370: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:396: + * distribution. + */ -:382: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line #382: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:408: + * pair per subslice. + */ -:506: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment #506: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:532: + /* fall through */ -:526: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment #526: FILE: drivers/gpu/drm/i915/gt/intel_sseu.c:552: + /* fall through */ total: 0 errors, 8 warnings, 0 checks, 1259 lines checked f739bfbef07e drm/i915/sseu: Move sseu_info under gt_info From patchwork at emeril.freedesktop.org Sat Jun 27 08:38:55 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 08:38:55 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgTW92?= =?utf-8?q?e_some_device_capabilities_under_intel=5Fgt?= In-Reply-To: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> References: <20200625234212.22811-1-daniele.ceraolospurio@intel.com> Message-ID: <159324713542.5397.11129147213699612290@emeril.freedesktop.org> == Series Details == Series: Move some device capabilities under intel_gt URL : https://patchwork.freedesktop.org/series/78829/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8668 -> Patchwork_18029 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18029 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18029, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18029: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cfl-8109u/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cfl-8109u/igt at i915_selftest@live at execlists.html - fi-apl-guc: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-apl-guc/igt at i915_selftest@live at execlists.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-apl-guc/igt at i915_selftest@live at execlists.html - fi-icl-u2: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-u2/igt at i915_selftest@live at execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-icl-u2/igt at i915_selftest@live at execlists.html - fi-skl-6600u: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-skl-6600u/igt at i915_selftest@live at execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-skl-6600u/igt at i915_selftest@live at execlists.html - fi-cfl-8700k: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cfl-8700k/igt at i915_selftest@live at execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cfl-8700k/igt at i915_selftest@live at execlists.html - fi-tgl-u2: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt at i915_selftest@live at execlists.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-tgl-u2/igt at i915_selftest@live at execlists.html - fi-cml-s: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cml-s/igt at i915_selftest@live at execlists.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cml-s/igt at i915_selftest@live at execlists.html - fi-skl-guc: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-skl-guc/igt at i915_selftest@live at execlists.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-skl-guc/igt at i915_selftest@live at execlists.html - fi-cfl-guc: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cfl-guc/igt at i915_selftest@live at execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cfl-guc/igt at i915_selftest@live at execlists.html - fi-icl-y: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-y/igt at i915_selftest@live at execlists.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-icl-y/igt at i915_selftest@live at execlists.html - fi-bxt-dsi: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bxt-dsi/igt at i915_selftest@live at execlists.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bxt-dsi/igt at i915_selftest@live at execlists.html - fi-whl-u: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-whl-u/igt at i915_selftest@live at execlists.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-whl-u/igt at i915_selftest@live at execlists.html - fi-cml-u2: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-cml-u2/igt at i915_selftest@live at execlists.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-cml-u2/igt at i915_selftest@live at execlists.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_selftest@live at execlists: - {fi-ehl-1}: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-ehl-1/igt at i915_selftest@live at execlists.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-ehl-1/igt at i915_selftest@live at execlists.html - {fi-tgl-dsi}: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-dsi/igt at i915_selftest@live at execlists.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-tgl-dsi/igt at i915_selftest@live at execlists.html Known issues ------------ Here are the changes found in Patchwork_18029 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-byt-j1900/igt at i915_module_load@reload.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-byt-j1900/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-kbl-guc: [PASS][33] -> [SKIP][34] ([fdo#109271]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-guc/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at execlists: - fi-glk-dsi: [PASS][35] -> [INCOMPLETE][36] ([i915#58] / [k.org#198133]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-glk-dsi/igt at i915_selftest@live at execlists.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-glk-dsi/igt at i915_selftest@live at execlists.html - fi-kbl-x1275: [PASS][37] -> [INCOMPLETE][38] ([i915#794]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at i915_selftest@live at execlists.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt at i915_selftest@live at execlists.html - fi-kbl-soraka: [PASS][39] -> [INCOMPLETE][40] ([i915#794]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-soraka/igt at i915_selftest@live at execlists.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-soraka/igt at i915_selftest@live at execlists.html - fi-kbl-guc: [PASS][41] -> [INCOMPLETE][42] ([i915#794]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-guc/igt at i915_selftest@live at execlists.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-guc/igt at i915_selftest@live at execlists.html - fi-kbl-8809g: [PASS][43] -> [INCOMPLETE][44] ([i915#794]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-8809g/igt at i915_selftest@live at execlists.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-8809g/igt at i915_selftest@live at execlists.html * igt at i915_selftest@live at gt_lrc: - fi-bsw-n3050: [PASS][45] -> [INCOMPLETE][46] ([i915#1436]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-n3050/igt at i915_selftest@live at gt_lrc.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-n3050/igt at i915_selftest@live at gt_lrc.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][47] -> [DMESG-WARN][48] ([i915#62] / [i915#92] / [i915#95]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_busy@basic at flip.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][49] -> [DMESG-WARN][50] ([i915#1982]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at debugfs_test@read_all_entries: - fi-bsw-nick: [INCOMPLETE][51] ([i915#1250] / [i915#1436]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-nick/igt at debugfs_test@read_all_entries.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-nick/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][53] ([i915#1888]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-bxt-dsi: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bxt-dsi/igt at i915_module_load@reload.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bxt-dsi/igt at i915_module_load@reload.html * igt at i915_pm_backlight@basic-brightness: - fi-whl-u: [DMESG-WARN][57] ([i915#95]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-whl-u/igt at i915_pm_backlight@basic-brightness.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-kbl-7560u}: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][63] ([i915#62] / [i915#92]) -> [DMESG-WARN][64] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][65] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][66] ([i915#62] / [i915#92]) +6 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (45 -> 38) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8668 -> Patchwork_18029 CI-20190529: 20190529 CI_DRM_8668: ebcb5923cc316fea9d46629cce83960511da889e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18029: f739bfbef07e9f83a169c892888fc16de307f0db @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == f739bfbef07e drm/i915/sseu: Move sseu_info under gt_info 5ba87fdd277d drm/i915/sseu: Move sseu detection and dump to intel_sseu 09b520c7dacc drm/i915: Introduce gt_init_mmio f77f0e80766d drm/i915: Move the engine mask to intel_gt_info 72189c790177 drm/i915: Move engine-related mmio init to engines_init_mmio cb6b1a857f72 drm/i915: Use the gt in HAS_ENGINE 999ecfc5fc75 drm/i915: Convert device_info to uncore/de_read == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18029/index.html From patchwork at emeril.freedesktop.org Sat Jun 27 08:42:06 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 08:42:06 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv2=2C1/5=5D_drm/i915=3A_Add_plane_d?= =?utf-8?q?amage_clips_property?= In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <159324732671.5397.11104628895904323217@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/5] drm/i915: Add plane damage clips property URL : https://patchwork.freedesktop.org/series/78830/ State : warning == Summary == $ dim checkpatch origin/drm-tip 93646a5debb4 drm/i915: Add plane damage clips property 876e57df337b drm/i915: Reorder intel_psr2_config_valid() 220cc1343ce6 drm/i915: Add PSR2 selective fetch registers -:37: WARNING:LONG_LINE: line length of 119 exceeds 100 columns #37: FILE: drivers/gpu/drm/i915/i915_reg.h:4593: +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) -:39: WARNING:LONG_LINE: line length of 125 exceeds 100 columns #39: FILE: drivers/gpu/drm/i915/i915_reg.h:4595: +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) -:71: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #71: FILE: drivers/gpu/drm/i915/i915_reg.h:7182: +#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) total: 0 errors, 3 warnings, 0 checks, 87 lines checked 0a361499f045 drm/i915: Initial implementation of PSR2 selective fetch -:283: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #283: FILE: drivers/gpu/drm/i915/i915_params.c:106: +i915_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, + "Enable PSR2 selective fetch " total: 0 errors, 0 warnings, 1 checks, 220 lines checked db04305684b4 drm/i915/display: Implement WA 1408330847 From patchwork at emeril.freedesktop.org Sat Jun 27 09:02:55 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 09:02:55 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/5=5D_drm/i915=3A_Add_plane_damage_c?= =?utf-8?q?lips_property?= In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <159324857584.5395.3072644951755767530@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/5] drm/i915: Add plane damage clips property URL : https://patchwork.freedesktop.org/series/78830/ State : success == Summary == CI Bug Log - changes from CI_DRM_8668 -> Patchwork_18030 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/index.html Known issues ------------ Here are the changes found in Patchwork_18030 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1242]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-byt-j1900/igt at i915_module_load@reload.html - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-tgl-u2/igt at i915_module_load@reload.html #### Possible fixes #### * igt at debugfs_test@read_all_entries: - fi-bsw-nick: [INCOMPLETE][7] ([i915#1250] / [i915#1436]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-nick/igt at debugfs_test@read_all_entries.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-bsw-nick/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][9] ([i915#1888]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-bxt-dsi: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bxt-dsi/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-bxt-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 39) ------------------------------ Additional (1): fi-tgl-y Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8668 -> Patchwork_18030 CI-20190529: 20190529 CI_DRM_8668: ebcb5923cc316fea9d46629cce83960511da889e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18030: db04305684b414fbffc815c1df478226971721e7 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == db04305684b4 drm/i915/display: Implement WA 1408330847 0a361499f045 drm/i915: Initial implementation of PSR2 selective fetch 220cc1343ce6 drm/i915: Add PSR2 selective fetch registers 876e57df337b drm/i915: Reorder intel_psr2_config_valid() 93646a5debb4 drm/i915: Add plane damage clips property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18030/index.html From patchwork at emeril.freedesktop.org Sat Jun 27 09:07:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 09:07:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Send_a_hotplug_when_edid_changes_=28rev9=29?= In-Reply-To: <20200626091333.17516-1-kunal1.joshi@intel.com> References: <20200626091333.17516-1-kunal1.joshi@intel.com> Message-ID: <159324884601.5394.12272927308480844512@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev9) URL : https://patchwork.freedesktop.org/series/62816/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8c236463353b drm: Add helper to compare edids. -:34: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid1" #34: FILE: drivers/gpu/drm/drm_edid.c:1628: + bool edid1_present = edid1 != NULL; -:35: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "edid2" #35: FILE: drivers/gpu/drm/drm_edid.c:1629: + bool edid2_present = edid2 != NULL; -:41: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #41: FILE: drivers/gpu/drm/drm_edid.c:1635: + if (edid1) { + -:56: CHECK:LINE_SPACING: Please don't use multiple blank lines #56: FILE: drivers/gpu/drm/drm_edid.c:1650: + + total: 0 errors, 0 warnings, 4 checks, 54 lines checked 67927d889ffe drm: Introduce epoch counter to drm_connector -:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #58: FILE: drivers/gpu/drm/drm_connector.c:2012: + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", + connector->base.id, connector->name); -:62: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #62: FILE: drivers/gpu/drm/drm_connector.c:2016: + DRM_DEBUG_KMS("Updating change counter to %llu\n", + connector->epoch_counter); -:131: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' #131: FILE: drivers/gpu/drm/drm_probe_helper.c:790: + uint64_t old_epoch_counter; -:162: WARNING:BRACES: braces {} are not necessary for single statement blocks #162: FILE: drivers/gpu/drm/drm_probe_helper.c:826: + if (old_epoch_counter != connector->epoch_counter) { changed = true; + } -:186: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u64' over 'uint64_t' #186: FILE: include/drm/drm_connector.h:1333: + uint64_t epoch_counter; total: 0 errors, 1 warnings, 4 checks, 136 lines checked 04bfaff00368 drm/i915: Send hotplug event if edid had changed From patchwork at emeril.freedesktop.org Sat Jun 27 09:09:13 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 09:09:13 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?Send_a_hotplug_when_edid_changes_=28rev9=29?= In-Reply-To: <20200626091333.17516-1-kunal1.joshi@intel.com> References: <20200626091333.17516-1-kunal1.joshi@intel.com> Message-ID: <159324895379.5395.16423389105357953781@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev9) URL : https://patchwork.freedesktop.org/series/62816/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: expected unsigned int [addressable] [usertype] ulClockParams +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: got restricted __le32 [usertype] +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1019:47: warning: incorrect type in assignment (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1028:50: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1029:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:1037:47: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:184:44: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:283:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:320:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:323:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:326:14: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:329:18: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:330:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:338:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:340:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:342:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:346:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:348:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:353:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:367:43: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:369:38: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:374:67: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:375:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:378:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:389:80: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:395:57: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:402:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:403:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:406:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:414:66: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:423:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:424:69: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:473:30: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:476:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:477:45: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:484:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:52:28: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:531:35: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:53:29: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:533:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:54:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:55:27: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:56:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:57:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:577:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:581:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:58:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:583:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:586:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:590:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:59:26: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:598:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:600:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:617:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:621:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:623:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:630:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:632:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:644:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:648:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:650:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:657:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:659:21: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:662:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:664:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:676:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:688:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:691:47: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:697:25: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:796:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:797:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:800:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:801:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:804:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:805:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:812:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:813:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:816:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:817:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:820:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:821:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:828:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:829:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:832:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:833:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:836:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:837:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:844:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:845:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:848:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:849:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:852:46: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:853:40: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:916:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:918:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:920:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:934:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:936:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:938:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:956:47: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:958:49: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c:960:52: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:296:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:330:34: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:360:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:362:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:369:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:383:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:406:40: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:44:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:447:53: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:451:33: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:454:61: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:455:64: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:457:54: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:483:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:486:21: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:64:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:80:17: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:85:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:86:24: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c:98:39: warning: cast to restricted __le16 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:222:29: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:226:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:227:37: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:233:43: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:236:44: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:239:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:458:41: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:464:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:465:30: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:466:39: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c:468:24: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: expected unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:140:26: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: got unsigned long long [usertype] *chunk_array_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:141:41: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: expected struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:160:27: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: expected struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: got void [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1613:21: warning: incorrect type in assignment (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: got struct drm_amdgpu_fence *fences_user +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:1614:36: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: expected void const [noderef] __user *from +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: got struct drm_amdgpu_cs_chunk [noderef] __user **chunk_ptr +drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:161:49: warning: incorrect type in argument 2 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1256:25: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1257:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1313:17: error: incompatible types in comparison expression (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: expected restricted __poll_t ( *poll )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: got unsigned int ( * )( ... ) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:138:17: warning: incorrect type in initializer (different base types) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:257:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:259:29: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:346:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:400:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:457:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:511:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:568:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:622:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: expected void const volatile [noderef] __user * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: got unsigned int [usertype] * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: cast removes address space '__user' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: incorrect type in argument 1 (different address spaces) +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:719:21: warning: too many warnings +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1618:65: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1625:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1626:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1627:50: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1628:56: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1630:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1631:45: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1632:51: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1633:55: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1634:57: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1636:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1637:53: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1639:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1641:25: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1642:46: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1646:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1648:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1650:33: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1661:73: warning: cast to restricted __le32 +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:260:16: error: incompatible types in comparison expression (different type sizes) +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:507:39: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:527:31: warning: cast removes address space '__iomem' of expression +drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:184:13: warning: cast to restricted __le32 From patchwork at emeril.freedesktop.org Sat Jun 27 09:28:31 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 09:28:31 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgU2Vu?= =?utf-8?q?d_a_hotplug_when_edid_changes_=28rev9=29?= In-Reply-To: <20200626091333.17516-1-kunal1.joshi@intel.com> References: <20200626091333.17516-1-kunal1.joshi@intel.com> Message-ID: <159325011178.5397.17081517195190820200@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev9) URL : https://patchwork.freedesktop.org/series/62816/ State : success == Summary == CI Bug Log - changes from CI_DRM_8668 -> Patchwork_18031 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/index.html Known issues ------------ Here are the changes found in Patchwork_18031 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-n2820: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at debugfs_test@read_all_entries: - fi-bsw-nick: [INCOMPLETE][9] ([i915#1250] / [i915#1436]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-nick/igt at debugfs_test@read_all_entries.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-bsw-nick/igt at debugfs_test@read_all_entries.html * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-wf_vblank at a-dp1.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 39) ------------------------------ Additional (1): fi-tgl-y Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8668 -> Patchwork_18031 CI-20190529: 20190529 CI_DRM_8668: ebcb5923cc316fea9d46629cce83960511da889e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18031: 04bfaff0036881053309d5267bf89bedad393443 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 04bfaff00368 drm/i915: Send hotplug event if edid had changed 67927d889ffe drm: Introduce epoch counter to drm_connector 8c236463353b drm: Add helper to compare edids. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18031/index.html From patchwork at emeril.freedesktop.org Sat Jun 27 09:32:45 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Sat, 27 Jun 2020 09:32:45 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv4=2C1/2=5D_drm/i915/dp=3A_Helper_f?= =?utf-8?q?or_checking_DDI=5FBUF=5FCTL_Idle_status?= In-Reply-To: <20200626232641.4557-1-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> Message-ID: <159325036521.5394.13328630417701316434@emeril.freedesktop.org> == Series Details == Series: series starting with [v4,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status URL : https://patchwork.freedesktop.org/series/78867/ State : warning == Summary == $ dim checkpatch origin/drm-tip e41b98b71f2b drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status -:38: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst #38: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1188: + udelay(16); total: 0 errors, 0 warnings, 1 checks, 24 lines checked 8d63e562ec8b drm/i915/dp: Helper to check for DDI BUF status to get active -:36: ERROR:SPACING: space prohibited before that close parenthesis ')' #36: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1201: + if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv) ) { total: 1 errors, 0 warnings, 0 checks, 28 lines checked From ville.syrjala at linux.intel.com Sat Jun 27 16:57:31 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Sat, 27 Jun 2020 19:57:31 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200626151336.GA6490@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> <20200626151336.GA6490@intel.com> Message-ID: <20200626180306.GC6112@intel.com> On Fri, Jun 26, 2020 at 06:13:36PM +0300, Lisovskiy, Stanislav wrote: > On Fri, Jun 26, 2020 at 04:46:41PM +0300, Ville Syrj?l? wrote: > > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > The linetime watermark is a 9 bit value, which gives us > > > > a maximum linetime of just below 64 usec. If the linetime > > > > exceeds that value we currently just discard the high bits > > > > and program the rest into the register, which angers the > > > > state checker. > > > > > > > > To avoid that let's just clamp the value to the max. I believe > > > > it should be perfectly fine to program a smaller linetime wm > > > > than strictly required, just means the hardware may fetch data > > > > sooner than strictly needed. We are further reassured by the > > > > fact that with DRRS the spec tells us to program the smaller > > > > of the two linetimes corresponding to the two refresh rates. > > > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ > > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > > index a11bb675f9b3..d486d675166f 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > { > > > > const struct drm_display_mode *adjusted_mode = > > > > &crtc_state->hw.adjusted_mode; > > > > + int linetime_wm; > > > > > > > > if (!crtc_state->hw.enable) > > > > return 0; > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > - adjusted_mode->crtc_clock); > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > + adjusted_mode->crtc_clock); > > > > + > > > > + return min(linetime_wm, 0x1ff); > > > > > > Are we actually doing the right thing here? I just mean that we get value > > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > > > As explained in the commit msg programming this to lower than necessary > > value should be totally fine. It just won't be optimal. > > > > The values in the jira (was there an actual gitlab bug for this btw?) > > look quite sensible to me. Some kind of low res 848xsomething mode with > > dotclock of 14.874 Mhz, which gives us that linetime of ~68 usec. > > Htotal from modeline "848x480": 30 14874 848 896 928 1008 480 483 488 494 0x40 0x9 > is 1008. > > According to the formula above htotal(1008)*1000*8 / 14874(crtc_clock) = 542.154 > > So what's the catch? :) What catch? Looks totally consistent to me. > > Stan > > > > > > > > Stan > > > > } > > > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > { > > > > const struct drm_display_mode *adjusted_mode = > > > > &crtc_state->hw.adjusted_mode; > > > > + int linetime_wm; > > > > > > > > if (!crtc_state->hw.enable) > > > > return 0; > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > - cdclk_state->logical.cdclk); > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > + cdclk_state->logical.cdclk); > > > > + > > > > + return min(linetime_wm, 0x1ff); > > > > } > > > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > const struct drm_display_mode *adjusted_mode = > > > > &crtc_state->hw.adjusted_mode; > > > > - u16 linetime_wm; > > > > + int linetime_wm; > > > > > > > > if (!crtc_state->hw.enable) > > > > return 0; > > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > > linetime_wm /= 2; > > > > > > > > - return linetime_wm; > > > > + return min(linetime_wm, 0x1ff); > > > > } > > > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state *state, > > > > -- > > > > 2.26.2 > > > > > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From sfr at canb.auug.org.au Mon Jun 29 01:14:58 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Mon, 29 Jun 2020 11:14:58 +1000 Subject: [Intel-gfx] linux-next: manual merge of the drm-misc tree with Linus' tree Message-ID: <20200629111458.1661446b@canb.auug.org.au> Hi all, Today's linux-next merge of the drm-misc tree got conflicts in: drivers/gpu/drm/nouveau/dispnv04/crtc.c drivers/gpu/drm/nouveau/dispnv04/overlay.c drivers/gpu/drm/nouveau/dispnv50/base507c.c drivers/gpu/drm/nouveau/dispnv50/wndw.c drivers/gpu/drm/nouveau/nouveau_dmem.c drivers/gpu/drm/nouveau/nouveau_fbcon.c between commits: 183405879255 ("drm/nouveau/kms: Remove field nvbo from struct nouveau_framebuffer") c586f30bf74c ("drm/nouveau/kms: Add format mod prop to base/ovly/nvdisp") 1d7f940c3a16 ("drm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocations") from Linus' tree and commit: 0dc9b286b8d2 ("drm/nouveau: don't use ttm bo->offset v3") from the drm-misc tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell diff --cc drivers/gpu/drm/nouveau/dispnv04/crtc.c index 640738f3196c,cc6ab3c2eec7..000000000000 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@@ -840,12 -839,13 +840,12 @@@ nv04_crtc_do_mode_set_base(struct drm_c */ if (atomic) { drm_fb = passed_fb; - fb = nouveau_framebuffer(passed_fb); } else { drm_fb = crtc->primary->fb; - fb = nouveau_framebuffer(crtc->primary->fb); } - nv_crtc->fb.offset = fb->nvbo->offset; + nvbo = nouveau_gem_object(drm_fb->obj[0]); - nv_crtc->fb.offset = nvbo->bo.offset; ++ nv_crtc->fb.offset = nvbo->offset; if (nv_crtc->lut.depth != drm_fb->format->depth) { nv_crtc->lut.depth = drm_fb->format->depth; diff --cc drivers/gpu/drm/nouveau/dispnv04/overlay.c index 6248fd1dbc6d,9529bd9053e7..000000000000 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@@ -152,7 -150,7 +152,7 @@@ nv10_update_plane(struct drm_plane *pla nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0); - nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nvbo->bo.offset); - nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->offset); ++ nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nvbo->offset); nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x); nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); @@@ -174,7 -172,7 +174,7 @@@ if (format & NV_PVIDEO_FORMAT_PLANAR) { nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), - nvbo->bo.offset + fb->offsets[1]); - nv_fb->nvbo->offset + fb->offsets[1]); ++ nvbo->offset + fb->offsets[1]); } nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format | fb->pitches[0]); nvif_wr32(dev, NV_PVIDEO_STOP, 0); @@@ -399,7 -396,7 +399,7 @@@ nv04_update_plane(struct drm_plane *pla for (i = 0; i < 2; i++) { nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i, - nvbo->bo.offset); - nv_fb->nvbo->offset); ++ nvbo->offset); nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, fb->pitches[0]); nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0); diff --cc drivers/gpu/drm/nouveau/dispnv50/base507c.c index 511258bfbcbc,b60aa987d7b4..000000000000 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@@ -274,9 -273,9 +274,9 @@@ base507c_new_(const struct nv50_wndw_fu if (*pwndw = wndw, ret) return ret; - ret = nv50_dmac_create(&drm->client.device, &disp->disp->object, + ret = nv50_dmac_create(&drm->client.device, &disp->disp.object, &oclass, head, &args, sizeof(args), - disp50->sync->bo.offset, &wndw->wndw); - disp->sync->offset, &wndw->wndw); ++ disp50->sync->offset, &wndw->wndw); if (ret) { NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret); return ret; diff --cc drivers/gpu/drm/nouveau/dispnv50/wndw.c index 99b9b681736d,ee0fd817185e..000000000000 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@@ -521,12 -507,11 +521,12 @@@ nv50_wndw_prepare_fb(struct drm_plane * return PTR_ERR(ctxdma); } - asyw->image.handle[0] = ctxdma->object.handle; + if (asyw->visible) + asyw->image.handle[0] = ctxdma->object.handle; } - asyw->state.fence = dma_resv_get_excl_rcu(fb->nvbo->bo.base.resv); - asyw->image.offset[0] = fb->nvbo->offset; + asyw->state.fence = dma_resv_get_excl_rcu(nvbo->bo.base.resv); - asyw->image.offset[0] = nvbo->bo.offset; ++ asyw->image.offset[0] = nvbo->offset; if (wndw->func->prepare) { asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); diff --cc drivers/gpu/drm/nouveau/nouveau_dmem.c index e5c230d9ae24,f13086a32f0f..000000000000 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@@ -75,32 -72,25 +75,32 @@@ struct nouveau_dmem_migrate struct nouveau_dmem { struct nouveau_drm *drm; - struct dev_pagemap pagemap; struct nouveau_dmem_migrate migrate; - struct list_head chunk_free; - struct list_head chunk_full; - struct list_head chunk_empty; + struct list_head chunks; struct mutex mutex; + struct page *free_pages; + spinlock_t lock; }; -static inline struct nouveau_dmem *page_to_dmem(struct page *page) +static struct nouveau_dmem_chunk *nouveau_page_to_chunk(struct page *page) { - return container_of(page->pgmap, struct nouveau_dmem, pagemap); + return container_of(page->pgmap, struct nouveau_dmem_chunk, pagemap); +} + +static struct nouveau_drm *page_to_drm(struct page *page) +{ + struct nouveau_dmem_chunk *chunk = nouveau_page_to_chunk(page); + + return chunk->drm; } -static unsigned long nouveau_dmem_page_addr(struct page *page) +unsigned long nouveau_dmem_page_addr(struct page *page) { - struct nouveau_dmem_chunk *chunk = page->zone_device_data; - unsigned long idx = page_to_pfn(page) - chunk->pfn_first; + struct nouveau_dmem_chunk *chunk = nouveau_page_to_chunk(page); + unsigned long off = (page_to_pfn(page) << PAGE_SHIFT) - + chunk->pagemap.res.start; - return chunk->bo->bo.offset + off; - return (idx << PAGE_SHIFT) + chunk->bo->offset; ++ return chunk->bo->offset + off; } static void nouveau_dmem_page_free(struct page *page) diff --cc drivers/gpu/drm/nouveau/nouveau_fbcon.c index 3d11b84d4cf9,1341c6fca3ed..000000000000 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@@ -393,7 -393,7 +393,7 @@@ nouveau_fbcon_create(struct drm_fb_help /* To allow resizeing without swapping buffers */ NV_INFO(drm, "allocated %dx%d fb: 0x%llx, bo %p\n", - fb->width, fb->height, nvbo->bo.offset, nvbo); - fb->base.width, fb->base.height, fb->nvbo->offset, nvbo); ++ fb->width, fb->height, nvbo->offset, nvbo); vga_switcheroo_client_fb_set(dev->pdev, info); return 0; -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200629/7ae12219/attachment.sig> From martin.peres at intel.com Mon Jun 29 07:47:04 2020 From: martin.peres at intel.com (Peres, Martin) Date: Mon, 29 Jun 2020 07:47:04 +0000 Subject: [Intel-gfx] Connectivity issue to the CI system Message-ID: <9114b53c837547c39a770b18002c7163@intel.com> Hi everyone, We have been experiencing connectivity issue for the past week to the CI system which led to abnormal CI latencies: https://intel-gfx-ci.01.org/latency.html?project=igt&test=Fi.CI.IGT The issue has been under investigation, but unfortunately we do not know when this issue will get resolved. It however got worse over the weekend to the point that the CI system is completely unavailable. Sorry about the issue, I will keep you updated as information becomes available to me. Martin, on behalf of the CI team -------------- next part -------------- A non-text attachment was scrubbed... Name: pEpkey.asc Type: application/pgp-keys Size: 1774 bytes Desc: pEpkey.asc URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200629/546cfb4d/attachment.key> From m.szyprowski at samsung.com Mon Jun 29 07:51:41 2020 From: m.szyprowski at samsung.com (Marek Szyprowski) Date: Mon, 29 Jun 2020 09:51:41 +0200 Subject: [Intel-gfx] [PATCH 01/13] iommu/exynos: Use dev_iommu_priv_get/set() In-Reply-To: <20200625130836.1916-2-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> <CGME20200625130845eucas1p2e7715cbd0b8ad95d5f5bc86728c3aabe@eucas1p2.samsung.com> <20200625130836.1916-2-joro@8bytes.org> Message-ID: <f69cc934-1fcc-c311-7bc0-22472befa796@samsung.com> On 25.06.2020 15:08, Joerg Roedel wrote: > From: Joerg Roedel <jroedel at suse.de> > > Remove the use of dev->archdata.iommu and use the private per-device > pointer provided by IOMMU core code instead. > > Signed-off-by: Joerg Roedel <jroedel at suse.de> Acked-by: Marek Szyprowski <m.szyprowski at samsung.com> > --- > drivers/iommu/exynos-iommu.c | 20 +++++++++---------- > .../media/platform/s5p-mfc/s5p_mfc_iommu.h | 4 +++- > 2 files changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c > index 60c8a56e4a3f..6a9b67302369 100644 > --- a/drivers/iommu/exynos-iommu.c > +++ b/drivers/iommu/exynos-iommu.c > @@ -173,7 +173,7 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) > #define REG_V5_FAULT_AR_VA 0x070 > #define REG_V5_FAULT_AW_VA 0x080 > > -#define has_sysmmu(dev) (dev->archdata.iommu != NULL) > +#define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) > > static struct device *dma_dev; > static struct kmem_cache *lv2table_kmem_cache; > @@ -226,7 +226,7 @@ static const struct sysmmu_fault_info sysmmu_v5_faults[] = { > }; > > /* > - * This structure is attached to dev.archdata.iommu of the master device > + * This structure is attached to dev->iommu->priv of the master device > * on device add, contains a list of SYSMMU controllers defined by device tree, > * which are bound to given master device. It is usually referenced by 'owner' > * pointer. > @@ -670,7 +670,7 @@ static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) > struct device *master = data->master; > > if (master) { > - struct exynos_iommu_owner *owner = master->archdata.iommu; > + struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); > > mutex_lock(&owner->rpm_lock); > if (data->domain) { > @@ -688,7 +688,7 @@ static int __maybe_unused exynos_sysmmu_resume(struct device *dev) > struct device *master = data->master; > > if (master) { > - struct exynos_iommu_owner *owner = master->archdata.iommu; > + struct exynos_iommu_owner *owner = dev_iommu_priv_get(master); > > mutex_lock(&owner->rpm_lock); > if (data->domain) { > @@ -837,8 +837,8 @@ static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) > static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, > struct device *dev) > { > - struct exynos_iommu_owner *owner = dev->archdata.iommu; > struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); > + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); > phys_addr_t pagetable = virt_to_phys(domain->pgtable); > struct sysmmu_drvdata *data, *next; > unsigned long flags; > @@ -875,8 +875,8 @@ static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, > static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, > struct device *dev) > { > - struct exynos_iommu_owner *owner = dev->archdata.iommu; > struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); > + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); > struct sysmmu_drvdata *data; > phys_addr_t pagetable = virt_to_phys(domain->pgtable); > unsigned long flags; > @@ -1237,7 +1237,7 @@ static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, > > static struct iommu_device *exynos_iommu_probe_device(struct device *dev) > { > - struct exynos_iommu_owner *owner = dev->archdata.iommu; > + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); > struct sysmmu_drvdata *data; > > if (!has_sysmmu(dev)) > @@ -1263,7 +1263,7 @@ static struct iommu_device *exynos_iommu_probe_device(struct device *dev) > > static void exynos_iommu_release_device(struct device *dev) > { > - struct exynos_iommu_owner *owner = dev->archdata.iommu; > + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); > struct sysmmu_drvdata *data; > > if (!has_sysmmu(dev)) > @@ -1287,8 +1287,8 @@ static void exynos_iommu_release_device(struct device *dev) > static int exynos_iommu_of_xlate(struct device *dev, > struct of_phandle_args *spec) > { > - struct exynos_iommu_owner *owner = dev->archdata.iommu; > struct platform_device *sysmmu = of_find_device_by_node(spec->np); > + struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); > struct sysmmu_drvdata *data, *entry; > > if (!sysmmu) > @@ -1305,7 +1305,7 @@ static int exynos_iommu_of_xlate(struct device *dev, > > INIT_LIST_HEAD(&owner->controllers); > mutex_init(&owner->rpm_lock); > - dev->archdata.iommu = owner; > + dev_iommu_priv_set(dev, owner); > } > > list_for_each_entry(entry, &owner->controllers, owner_node) > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h b/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h > index 152a713fff78..1a32266b7ddc 100644 > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_iommu.h > @@ -9,9 +9,11 @@ > > #if defined(CONFIG_EXYNOS_IOMMU) > > +#include <linux/iommu.h> > + > static inline bool exynos_is_iommu_available(struct device *dev) > { > - return dev->archdata.iommu != NULL; > + return dev_iommu_priv_get(dev) != NULL; > } > > #else Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland From patchwork at emeril.freedesktop.org Mon Jun 29 07:56:26 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 29 Jun 2020 07:56:26 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv4=2C1/2=5D_drm/i915/dp=3A_Helper_for_chec?= =?utf-8?q?king_DDI=5FBUF=5FCTL_Idle_status?= In-Reply-To: <20200626232641.4557-1-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> Message-ID: <159341738635.747.8120874006152093518@emeril.freedesktop.org> == Series Details == Series: series starting with [v4,1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status URL : https://patchwork.freedesktop.org/series/78867/ State : success == Summary == CI Bug Log - changes from CI_DRM_8668 -> Patchwork_18032 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/index.html Known issues ------------ Here are the changes found in Patchwork_18032 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-apl-guc: [PASS][1] -> [INCOMPLETE][2] ([i915#1242]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-apl-guc/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at debugfs_test@read_all_entries: - fi-bsw-nick: [INCOMPLETE][11] ([i915#1250] / [i915#1436]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bsw-nick/igt at debugfs_test@read_all_entries.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-bsw-nick/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][13] ([i915#1888]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at i915_module_load@reload: - fi-bxt-dsi: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-bxt-dsi/igt at i915_module_load@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-bxt-dsi/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +4 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8668/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1242]: https://gitlab.freedesktop.org/drm/intel/issues/1242 [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 39) ------------------------------ Additional (1): fi-tgl-y Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8668 -> Patchwork_18032 CI-20190529: 20190529 CI_DRM_8668: ebcb5923cc316fea9d46629cce83960511da889e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18032: 8d63e562ec8b0cecedc4569a51b0860494a1d006 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8d63e562ec8b drm/i915/dp: Helper to check for DDI BUF status to get active e41b98b71f2b drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18032/index.html From jani.nikula at intel.com Mon Jun 29 08:18:42 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Mon, 29 Jun 2020 11:18:42 +0300 Subject: [Intel-gfx] [PULL] gvt-fixes In-Reply-To: <20200623030711.GA5687@zhen-hp.sh.intel.com> References: <20200617043418.GQ5687@zhen-hp.sh.intel.com> <159248448107.8757.1901135788098329902@jlahtine-desk.ger.corp.intel.com> <20200623030711.GA5687@zhen-hp.sh.intel.com> Message-ID: <87wo3qmgil.fsf@intel.com> On Tue, 23 Jun 2020, Zhenyu Wang <zhenyuw at linux.intel.com> wrote: > On 2020.06.18 15:48:01 +0300, Joonas Lahtinen wrote: >> Quoting Zhenyu Wang (2020-06-17 07:34:18) >> > >> > Hi, >> > >> > This contains misc fixes for gvt. Two MMIO handler fixes on SKL/CFL, >> > one mask register bit checking fix exposed in suspend/resume path and >> > one lockdep error fix for debugfs entry access. >> >> Could not pull this one due to the extra hassle with CI this week. >> >> Jani, can you please pull this next week. >> > > Got it. Please help to pull then. Pulled, thanks. BR, Jani. > > One thing I forgot to mention that change in "drm/i915/gvt: Fix incorrect check of enabled bits in mask registers" > would cause a minor conflict if backmerging from linux master to dinq, which > is because of new IS_COMETLAKE. Change like below could resolve that. > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index 9f48db0bf9d5..78ba2857144e 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -1734,14 +1734,9 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, > return 0; > } > > -<<<<<<< HEAD > if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || > IS_COMETLAKE(vgpu->gvt->gt->i915)) && > - data & _MASKED_BIT_ENABLE(2)) { > -======= > - if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && > IS_MASKED_BITS_ENABLED(data, 2)) { > ->>>>>>> origin/gvt-next-fixes > enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); > return 0; > } > >> >> > Thanks. >> > -- >> > The following changes since commit 8e68c6340d5833077b3753eabedab40755571383: >> > >> > drm/i915/display: Fix the encoder type check (2020-06-16 11:34:24 +0300) >> > >> > are available in the Git repository at: >> > >> > https://github.com/intel/gvt-linux tags/gvt-fixes-2020-06-17 >> > >> > for you to fetch changes up to a291e4fba259a56a6a274c1989997acb6f0bb03a: >> > >> > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context (2020-06-17 12:36:19 +0800) >> > >> > ---------------------------------------------------------------- >> > gvt-fixes-2020-06-17 >> > >> > - Two missed MMIO handler fixes for SKL/CFL (Colin) >> > - Fix mask register bits check (Colin) >> > - Fix one lockdep error for debugfs entry access (Colin) >> > >> > ---------------------------------------------------------------- >> > Colin Xu (4): >> > drm/i915/gvt: Add one missing MMIO handler for D_SKL_PLUS >> > drm/i915/gvt: Fix two CFL MMIO handling caused by regression. >> > drm/i915/gvt: Fix incorrect check of enabled bits in mask registers >> > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context >> > >> > drivers/gpu/drm/i915/gvt/debugfs.c | 2 +- >> > drivers/gpu/drm/i915/gvt/handlers.c | 24 +++++++++++++----------- >> > drivers/gpu/drm/i915/gvt/mmio_context.h | 6 +++--- >> > drivers/gpu/drm/i915/gvt/reg.h | 5 +++++ >> > 4 files changed, 22 insertions(+), 15 deletions(-) >> _______________________________________________ >> intel-gvt-dev mailing list >> intel-gvt-dev at lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev -- Jani Nikula, Intel Open Source Graphics Center From stanislav.lisovskiy at intel.com Mon Jun 29 08:24:53 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Mon, 29 Jun 2020 11:24:53 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200626180306.GC6112@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> <20200626151336.GA6490@intel.com> <20200626180306.GC6112@intel.com> Message-ID: <20200629082432.GA1826@intel.com> On Sat, Jun 27, 2020 at 07:57:31PM +0300, Ville Syrj?l? wrote: > On Fri, Jun 26, 2020 at 06:13:36PM +0300, Lisovskiy, Stanislav wrote: > > On Fri, Jun 26, 2020 at 04:46:41PM +0300, Ville Syrj?l? wrote: > > > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > > > The linetime watermark is a 9 bit value, which gives us > > > > > a maximum linetime of just below 64 usec. If the linetime > > > > > exceeds that value we currently just discard the high bits > > > > > and program the rest into the register, which angers the > > > > > state checker. > > > > > > > > > > To avoid that let's just clamp the value to the max. I believe > > > > > it should be perfectly fine to program a smaller linetime wm > > > > > than strictly required, just means the hardware may fetch data > > > > > sooner than strictly needed. We are further reassured by the > > > > > fact that with DRRS the spec tells us to program the smaller > > > > > of the two linetimes corresponding to the two refresh rates. > > > > > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ > > > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > > > index a11bb675f9b3..d486d675166f 100644 > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > { > > > > > const struct drm_display_mode *adjusted_mode = > > > > > &crtc_state->hw.adjusted_mode; > > > > > + int linetime_wm; > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > return 0; > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > - adjusted_mode->crtc_clock); > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > + adjusted_mode->crtc_clock); > > > > > + > > > > > + return min(linetime_wm, 0x1ff); > > > > > > > > Are we actually doing the right thing here? I just mean that we get value > > > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > > > > > As explained in the commit msg programming this to lower than necessary > > > value should be totally fine. It just won't be optimal. > > > > > > The values in the jira (was there an actual gitlab bug for this btw?) > > > look quite sensible to me. Some kind of low res 848xsomething mode with > > > dotclock of 14.874 Mhz, which gives us that linetime of ~68 usec. > > > > Htotal from modeline "848x480": 30 14874 848 896 928 1008 480 483 488 494 0x40 0x9 > > is 1008. > > > > According to the formula above htotal(1008)*1000*8 / 14874(crtc_clock) = 542.154 > > > > So what's the catch? :) > > What catch? Looks totally consistent to me. I meant as I understood from your comment we were supposed to get 68 usec linetime, not 542. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > > Stan > > > > > > > > > > > Stan > > > > > } > > > > > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > > @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > > { > > > > > const struct drm_display_mode *adjusted_mode = > > > > > &crtc_state->hw.adjusted_mode; > > > > > + int linetime_wm; > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > return 0; > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > - cdclk_state->logical.cdclk); > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > + cdclk_state->logical.cdclk); > > > > > + > > > > > + return min(linetime_wm, 0x1ff); > > > > > } > > > > > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > > const struct drm_display_mode *adjusted_mode = > > > > > &crtc_state->hw.adjusted_mode; > > > > > - u16 linetime_wm; > > > > > + int linetime_wm; > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > return 0; > > > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > > > linetime_wm /= 2; > > > > > > > > > > - return linetime_wm; > > > > > + return min(linetime_wm, 0x1ff); > > > > > } > > > > > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state *state, > > > > > -- > > > > > 2.26.2 > > > > > > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel From chris at chris-wilson.co.uk Mon Jun 29 10:12:53 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 11:12:53 +0100 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/gem: Drop forced struct_mutex from shrinker_taints_mutex In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <20200629101256.13039-3-chris@chris-wilson.co.uk> Since we no longer always take struct_mutex around everything, and want the freedom to create GEM objects, actually taking struct_mutex inside the lock creation ends up pulling the mutex inside other looks. Since we don't use generally use struct_mutex, we can relax the tainting. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c index 5b65ce738b16..1ced1e5d2ec0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c @@ -408,26 +408,15 @@ void i915_gem_driver_unregister__shrinker(struct drm_i915_private *i915) void i915_gem_shrinker_taints_mutex(struct drm_i915_private *i915, struct mutex *mutex) { - bool unlock = false; - if (!IS_ENABLED(CONFIG_LOCKDEP)) return; - if (!lockdep_is_held_type(&i915->drm.struct_mutex, -1)) { - mutex_acquire(&i915->drm.struct_mutex.dep_map, - I915_MM_NORMAL, 0, _RET_IP_); - unlock = true; - } - fs_reclaim_acquire(GFP_KERNEL); mutex_acquire(&mutex->dep_map, 0, 0, _RET_IP_); mutex_release(&mutex->dep_map, _RET_IP_); fs_reclaim_release(GFP_KERNEL); - - if (unlock) - mutex_release(&i915->drm.struct_mutex.dep_map, _RET_IP_); } #define obj_to_i915(obj__) to_i915((obj__)->base.dev) -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 29 10:12:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 11:12:54 +0100 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Export ppgtt_bind_vma In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <20200629101256.13039-4-chris@chris-wilson.co.uk> Reuse the ppgtt_bind_vma() for aliasing_ppgtt_bind_vma() so we can reduce some code near-duplication. The catch is that we need to then pass along the i915_address_space and not rely on vma->vm, as they differ with the aliasing-ppgtt. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_client_blt.c | 9 ++-- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 7 +-- drivers/gpu/drm/i915/gt/intel_ggtt.c | 49 +++++++------------ drivers/gpu/drm/i915/gt/intel_gtt.h | 13 ++++- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 19 ++++--- drivers/gpu/drm/i915/i915_vma.c | 8 +-- drivers/gpu/drm/i915/i915_vma_types.h | 1 - drivers/gpu/drm/i915/selftests/mock_gtt.c | 12 +++-- 8 files changed, 58 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c index d3a86a4d5c04..278664f831e7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c @@ -32,16 +32,17 @@ static void vma_clear_pages(struct i915_vma *vma) vma->pages = NULL; } -static int vma_bind(struct i915_vma *vma, +static int vma_bind(struct i915_address_space *vm, + struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { - return vma->vm->vma_ops.bind_vma(vma, cache_level, flags); + return vm->vma_ops.bind_vma(vm, vma, cache_level, flags); } -static void vma_unbind(struct i915_vma *vma) +static void vma_unbind(struct i915_address_space *vm, struct i915_vma *vma) { - vma->vm->vma_ops.unbind_vma(vma); + vm->vma_ops.unbind_vma(vm, vma); } static const struct i915_vma_ops proxy_vma_ops = { diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index f4fec7eb4064..05497b50103f 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -299,11 +299,12 @@ static void pd_vma_clear_pages(struct i915_vma *vma) vma->pages = NULL; } -static int pd_vma_bind(struct i915_vma *vma, +static int pd_vma_bind(struct i915_address_space *vm, + struct i915_vma *vma, enum i915_cache_level cache_level, u32 unused) { - struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm); + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); struct gen6_ppgtt *ppgtt = vma->private; u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE; @@ -314,7 +315,7 @@ static int pd_vma_bind(struct i915_vma *vma, return 0; } -static void pd_vma_unbind(struct i915_vma *vma) +static void pd_vma_unbind(struct i915_address_space *vm, struct i915_vma *vma) { struct gen6_ppgtt *ppgtt = vma->private; struct i915_page_directory * const pd = ppgtt->base.pd; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 323c328d444a..62979ea591f0 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -436,7 +436,8 @@ static void i915_ggtt_clear_range(struct i915_address_space *vm, intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); } -static int ggtt_bind_vma(struct i915_vma *vma, +static int ggtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { @@ -451,15 +452,15 @@ static int ggtt_bind_vma(struct i915_vma *vma, if (i915_gem_object_is_readonly(obj)) pte_flags |= PTE_READ_ONLY; - vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); + vm->insert_entries(vm, vma, cache_level, pte_flags); vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; return 0; } -static void ggtt_unbind_vma(struct i915_vma *vma) +static void ggtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma) { - vma->vm->clear_range(vma->vm, vma->node.start, vma->size); + vm->clear_range(vm, vma->node.start, vma->size); } static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt) @@ -567,7 +568,8 @@ static int init_ggtt(struct i915_ggtt *ggtt) return ret; } -static int aliasing_gtt_bind_vma(struct i915_vma *vma, +static int aliasing_gtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { @@ -580,44 +582,27 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma, pte_flags |= PTE_READ_ONLY; if (flags & I915_VMA_LOCAL_BIND) { - struct i915_ppgtt *alias = i915_vm_to_ggtt(vma->vm)->alias; + struct i915_ppgtt *alias = i915_vm_to_ggtt(vm)->alias; - if (flags & I915_VMA_ALLOC) { - ret = alias->vm.allocate_va_range(&alias->vm, - vma->node.start, - vma->size); - if (ret) - return ret; - - set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)); - } - - GEM_BUG_ON(!test_bit(I915_VMA_ALLOC_BIT, - __i915_vma_flags(vma))); - alias->vm.insert_entries(&alias->vm, vma, - cache_level, pte_flags); + ret = ppgtt_bind_vma(&alias->vm, vma, cache_level, flags); + if (ret) + return ret; } if (flags & I915_VMA_GLOBAL_BIND) - vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); + vm->insert_entries(vm, vma, cache_level, pte_flags); return 0; } -static void aliasing_gtt_unbind_vma(struct i915_vma *vma) +static void aliasing_gtt_unbind_vma(struct i915_address_space *vm, + struct i915_vma *vma) { - if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) { - struct i915_address_space *vm = vma->vm; - + if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) vm->clear_range(vm, vma->node.start, vma->size); - } - - if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { - struct i915_address_space *vm = - &i915_vm_to_ggtt(vma->vm)->alias->vm; - vm->clear_range(vm, vma->node.start, vma->size); - } + if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND)) + ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma); } static int init_aliasing_ppgtt(struct i915_ggtt *ggtt) diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index d93ebdf3fa0e..f2b75078e05f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -198,14 +198,16 @@ struct intel_gt; struct i915_vma_ops { /* Map an object into an address space with the given cache flags. */ - int (*bind_vma)(struct i915_vma *vma, + int (*bind_vma)(struct i915_address_space *vm, + struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags); /* * Unmap an object from an address space. This usually consists of * setting the valid PTE entries to a reserved scratch page. */ - void (*unbind_vma)(struct i915_vma *vma); + void (*unbind_vma)(struct i915_address_space *vm, + struct i915_vma *vma); int (*set_pages)(struct i915_vma *vma); void (*clear_pages)(struct i915_vma *vma); @@ -566,6 +568,13 @@ int ggtt_set_pages(struct i915_vma *vma); int ppgtt_set_pages(struct i915_vma *vma); void clear_pages(struct i915_vma *vma); +int ppgtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags); +void ppgtt_unbind_vma(struct i915_address_space *vm, + struct i915_vma *vma); + void gtt_write_workarounds(struct intel_gt *gt); void setup_private_pat(struct intel_uncore *uncore); diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index f86f7e68ce5e..f0862e924d11 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -155,16 +155,16 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt) return ppgtt; } -static int ppgtt_bind_vma(struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +int ppgtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { u32 pte_flags; int err; - if (flags & I915_VMA_ALLOC) { - err = vma->vm->allocate_va_range(vma->vm, - vma->node.start, vma->size); + if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { + err = vm->allocate_va_range(vm, vma->node.start, vma->size); if (err) return err; @@ -176,17 +176,16 @@ static int ppgtt_bind_vma(struct i915_vma *vma, if (i915_gem_object_is_readonly(vma->obj)) pte_flags |= PTE_READ_ONLY; - GEM_BUG_ON(!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))); - vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags); + vm->insert_entries(vm, vma, cache_level, pte_flags); wmb(); return 0; } -static void ppgtt_unbind_vma(struct i915_vma *vma) +void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma) { if (test_and_clear_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) - vma->vm->clear_range(vma->vm, vma->node.start, vma->size); + vm->clear_range(vm, vma->node.start, vma->size); } int ppgtt_set_pages(struct i915_vma *vma) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 1f63c4a1f055..9c85c4f6e995 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -307,7 +307,7 @@ static int __vma_bind(struct dma_fence_work *work) struct i915_vma *vma = vw->vma; int err; - err = vma->ops->bind_vma(vma, vw->cache_level, vw->flags); + err = vma->ops->bind_vma(vma->vm, vma, vw->cache_level, vw->flags); if (err) atomic_or(I915_VMA_ERROR, &vma->flags); @@ -410,7 +410,7 @@ int i915_vma_bind(struct i915_vma *vma, work->vma = vma; work->cache_level = cache_level; - work->flags = bind_flags | I915_VMA_ALLOC; + work->flags = bind_flags; /* * Note we only want to chain up to the migration fence on @@ -436,7 +436,7 @@ int i915_vma_bind(struct i915_vma *vma, work->pinned = vma->obj; } } else { - ret = vma->ops->bind_vma(vma, cache_level, bind_flags); + ret = vma->ops->bind_vma(vma->vm, vma, cache_level, bind_flags); if (ret) return ret; } @@ -1264,7 +1264,7 @@ void __i915_vma_evict(struct i915_vma *vma) if (likely(atomic_read(&vma->vm->open))) { trace_i915_vma_unbind(vma); - vma->ops->unbind_vma(vma); + vma->ops->unbind_vma(vma->vm, vma); } atomic_and(~(I915_VMA_BIND_MASK | I915_VMA_ERROR | I915_VMA_GGTT_WRITE), &vma->flags); diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h index 63831cdb7402..9e9082dc8f4b 100644 --- a/drivers/gpu/drm/i915/i915_vma_types.h +++ b/drivers/gpu/drm/i915/i915_vma_types.h @@ -235,7 +235,6 @@ struct i915_vma { #define I915_VMA_BIND_MASK (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND) #define I915_VMA_ALLOC_BIT 12 -#define I915_VMA_ALLOC ((int)BIT(I915_VMA_ALLOC_BIT)) #define I915_VMA_ERROR_BIT 13 #define I915_VMA_ERROR ((int)BIT(I915_VMA_ERROR_BIT)) diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c index edc5e3dda8ca..b173086411ef 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -38,7 +38,8 @@ static void mock_insert_entries(struct i915_address_space *vm, { } -static int mock_bind_ppgtt(struct i915_vma *vma, +static int mock_bind_ppgtt(struct i915_address_space *vm, + struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { @@ -47,7 +48,8 @@ static int mock_bind_ppgtt(struct i915_vma *vma, return 0; } -static void mock_unbind_ppgtt(struct i915_vma *vma) +static void mock_unbind_ppgtt(struct i915_address_space *vm, + struct i915_vma *vma) { } @@ -88,7 +90,8 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) return ppgtt; } -static int mock_bind_ggtt(struct i915_vma *vma, +static int mock_bind_ggtt(struct i915_address_space *vm, + struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) { @@ -96,7 +99,8 @@ static int mock_bind_ggtt(struct i915_vma *vma, return 0; } -static void mock_unbind_ggtt(struct i915_vma *vma) +static void mock_unbind_ggtt(struct i915_address_space *vm, + struct i915_vma *vma) { } -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 29 10:12:52 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 11:12:52 +0100 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/gem: Split the context's obj:vma lut into its own mutex In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <20200629101256.13039-2-chris@chris-wilson.co.uk> Rather than reuse the common ctx->mutex for locking the execbuffer LUT, split it into its own lock to avoid being taken [as part of ctx->mutex] at inappropriate times. In particular to avoid the inversion from taking the timeline->mutex for the whole execbuf submission in the next patch. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 11 +++++++---- drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 1 + drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/gem/i915_gem_object.c | 4 ++-- drivers/gpu/drm/i915/gem/selftests/mock_context.c | 4 +++- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 6675447a47b9..6574af699233 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -101,8 +101,7 @@ static void lut_close(struct i915_gem_context *ctx) struct radix_tree_iter iter; void __rcu **slot; - lockdep_assert_held(&ctx->mutex); - + mutex_lock(&ctx->lut_mutex); rcu_read_lock(); radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) { struct i915_vma *vma = rcu_dereference_raw(*slot); @@ -135,6 +134,7 @@ static void lut_close(struct i915_gem_context *ctx) i915_gem_object_put(obj); } rcu_read_unlock(); + mutex_unlock(&ctx->lut_mutex); } static struct intel_context * @@ -342,6 +342,7 @@ static void i915_gem_context_free(struct i915_gem_context *ctx) spin_unlock(&ctx->i915->gem.contexts.lock); mutex_destroy(&ctx->engines_mutex); + mutex_destroy(&ctx->lut_mutex); if (ctx->timeline) intel_timeline_put(ctx->timeline); @@ -725,6 +726,7 @@ __create_context(struct drm_i915_private *i915) RCU_INIT_POINTER(ctx->engines, e); INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); + mutex_init(&ctx->lut_mutex); /* NB: Mark all slices as needing a remap so that when the context first * loads it will restore whatever remap state already exists. If there @@ -1312,11 +1314,11 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv, if (vm == rcu_access_pointer(ctx->vm)) goto unlock; + old = __set_ppgtt(ctx, vm); + /* Teardown the existing obj:vma cache, it will have to be rebuilt. */ lut_close(ctx); - old = __set_ppgtt(ctx, vm); - /* * We need to flush any requests using the current ppgtt before * we release it as the requests do not hold a reference themselves, @@ -1330,6 +1332,7 @@ static int set_ppgtt(struct drm_i915_file_private *file_priv, if (err) { i915_vm_close(__set_ppgtt(ctx, old)); i915_vm_close(old); + lut_close(ctx); /* rebuild the old obj:vma cache */ } unlock: diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h index 28760bd03265..ae14ca24a11f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h @@ -170,6 +170,7 @@ struct i915_gem_context { * per vm, which may be one per context or shared with the global GTT) */ struct radix_tree_root handles_vma; + struct mutex lut_mutex; /** * @name: arbitrary name, used for user debug diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index b4862afaaf28..6d4bf38dcda8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -782,7 +782,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, /* Check that the context hasn't been closed in the meantime */ err = -EINTR; - if (!mutex_lock_interruptible(&ctx->mutex)) { + if (!mutex_lock_interruptible(&ctx->lut_mutex)) { err = -ENOENT; if (likely(!i915_gem_context_is_closed(ctx))) err = radix_tree_insert(&ctx->handles_vma, handle, vma); @@ -798,7 +798,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, } spin_unlock(&obj->lut_lock); } - mutex_unlock(&ctx->mutex); + mutex_unlock(&ctx->lut_mutex); } if (unlikely(err)) goto err; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index 8222e8b33efd..07b5431b74a4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -135,14 +135,14 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) * vma, in the same fd namespace, by virtue of flink/open. */ - mutex_lock(&ctx->mutex); + mutex_lock(&ctx->lut_mutex); vma = radix_tree_delete(&ctx->handles_vma, lut->handle); if (vma) { GEM_BUG_ON(vma->obj != obj); GEM_BUG_ON(!atomic_read(&vma->open_count)); i915_vma_close(vma); } - mutex_unlock(&ctx->mutex); + mutex_unlock(&ctx->lut_mutex); i915_gem_context_put(lut->ctx); i915_lut_handle_free(lut); diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c b/drivers/gpu/drm/i915/gem/selftests/mock_context.c index aa0d06cf1903..51b5a3421b40 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c @@ -23,6 +23,8 @@ mock_context(struct drm_i915_private *i915, INIT_LIST_HEAD(&ctx->link); ctx->i915 = i915; + mutex_init(&ctx->mutex); + spin_lock_init(&ctx->stale.lock); INIT_LIST_HEAD(&ctx->stale.engines); @@ -35,7 +37,7 @@ mock_context(struct drm_i915_private *i915, RCU_INIT_POINTER(ctx->engines, e); INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL); - mutex_init(&ctx->mutex); + mutex_init(&ctx->lut_mutex); if (name) { struct i915_ppgtt *ppgtt; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 29 10:12:56 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 11:12:56 +0100 Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Switch to object allocations for page directories In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <20200629101256.13039-6-chris@chris-wilson.co.uk> The GEM object is grossly overweight for the practicality of tracking large numbers of individual pages, yet it is currently our only abstraction for tracking DMA allocations. Since those allocations need to be reserved upfront before an operation, and that we need to break away from simple system memory, we need to ditch using plain struct page wrappers. In the process, we drop the WC mapping as we ended up clflushing everything anyway due to various issues across a wider range of platforms. Though in a future step, we need to drop the kmap_atomic approach which suggests we need to pre-map all the pages and keep them mapped. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- Remaining problem here is coordinating the final free of objects from the ppgtt which is later than we shut down the GEM uAPI layer. --- .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 + .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- .../drm/i915/gem/selftests/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 46 ++- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 1 + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 64 ++-- drivers/gpu/drm/i915/gt/intel_ggtt.c | 31 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 291 +++--------------- drivers/gpu/drm/i915/gt/intel_gtt.h | 92 ++---- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 25 +- .../gpu/drm/i915/gt/intel_ring_submission.c | 16 +- drivers/gpu/drm/i915/gvt/scheduler.c | 17 +- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 5 - drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 + 15 files changed, 182 insertions(+), 414 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index 0fd677ad8ec8..b23895873926 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -282,6 +282,7 @@ struct drm_i915_gem_object { } userptr; unsigned long scratch; + u64 encode; void *gvt_info; }; diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index 8291ede6902c..9fb06fcc8f8f 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -393,7 +393,7 @@ static int igt_mock_exhaust_device_supported_pages(void *arg) */ for (i = 1; i < BIT(ARRAY_SIZE(page_sizes)); i++) { - unsigned int combination = 0; + unsigned int combination = SZ_4K; for (j = 0; j < ARRAY_SIZE(page_sizes); j++) { if (i & BIT(j)) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index b81978890641..1308198543d8 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1745,7 +1745,7 @@ static int check_scratch_page(struct i915_gem_context *ctx, u32 *out) if (!vm) return -ENODEV; - page = vm->scratch[0].base.page; + page = __px_page(vm->scratch[0]); if (!page) { pr_err("No scratch page!\n"); return -EINVAL; diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index dfde5fd452f1..909da7f36d18 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -16,8 +16,10 @@ static inline void gen6_write_pde(const struct gen6_ppgtt *ppgtt, const unsigned int pde, const struct i915_page_table *pt) { + dma_addr_t addr = pt ? px_dma(pt) : px_dma(ppgtt->base.vm.scratch[1]); + /* Caller needs to make sure the write completes if necessary */ - iowrite32(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID, + iowrite32(GEN6_PDE_ADDR_ENCODE(addr) | GEN6_PDE_VALID, ppgtt->pd_addr + pde); } @@ -79,7 +81,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm, { struct gen6_ppgtt * const ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm)); const unsigned int first_entry = start / I915_GTT_PAGE_SIZE; - const gen6_pte_t scratch_pte = vm->scratch[0].encode; + const gen6_pte_t scratch_pte = vm->scratch[0]->encode; unsigned int pde = first_entry / GEN6_PTES; unsigned int pte = first_entry % GEN6_PTES; unsigned int num_entries = length / I915_GTT_PAGE_SIZE; @@ -90,8 +92,6 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm, const unsigned int count = min(num_entries, GEN6_PTES - pte); gen6_pte_t *vaddr; - GEM_BUG_ON(px_base(pt) == px_base(&vm->scratch[1])); - num_entries -= count; GEM_BUG_ON(count > atomic_read(&pt->used)); @@ -127,7 +127,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, struct sgt_dma iter = sgt_dma(vma); gen6_pte_t *vaddr; - GEM_BUG_ON(pd->entry[act_pt] == &vm->scratch[1]); + GEM_BUG_ON(!pd->entry[act_pt]); vaddr = kmap_atomic_px(i915_pt_entry(pd, act_pt)); do { @@ -194,16 +194,16 @@ static void gen6_alloc_va_range(struct i915_address_space *vm, gen6_for_each_pde(pt, pd, start, length, pde) { const unsigned int count = gen6_pte_count(start, length); - if (px_base(pt) == px_base(&vm->scratch[1])) { + if (!pt) { spin_unlock(&pd->lock); pt = vma->pt_stash[0]; GEM_BUG_ON(!pt); - fill32_px(pt, vm->scratch[0].encode); + fill32_px(pt, vm->scratch[0]->encode); spin_lock(&pd->lock); - if (pd->entry[pde] == &vm->scratch[1]) { + if (!pd->entry[pde]) { vma->pt_stash[0] = pt->stash; atomic_set(&pt->used, 0); pd->entry[pde] = pt; @@ -227,24 +227,21 @@ static void gen6_alloc_va_range(struct i915_address_space *vm, static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt) { struct i915_address_space * const vm = &ppgtt->base.vm; - struct i915_page_directory * const pd = ppgtt->base.pd; int ret; - ret = setup_scratch_page(vm, __GFP_HIGHMEM); + ret = setup_scratch_page(vm); if (ret) return ret; - vm->scratch[0].encode = - vm->pte_encode(px_dma(&vm->scratch[0]), + vm->scratch[0]->encode = + vm->pte_encode(px_dma(vm->scratch[0]), I915_CACHE_NONE, PTE_READ_ONLY); - if (unlikely(setup_page_dma(vm, px_base(&vm->scratch[1])))) { - cleanup_scratch_page(vm); - return -ENOMEM; - } + vm->scratch[1] = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); + if (IS_ERR(vm->scratch[1])) + return PTR_ERR(vm->scratch[1]); - fill32_px(&vm->scratch[1], vm->scratch[0].encode); - memset_p(pd->entry, &vm->scratch[1], I915_PDES); + fill32_px(vm->scratch[1], vm->scratch[0]->encode); return 0; } @@ -252,13 +249,11 @@ static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt) static void gen6_ppgtt_free_pd(struct gen6_ppgtt *ppgtt) { struct i915_page_directory * const pd = ppgtt->base.pd; - struct i915_page_dma * const scratch = - px_base(&ppgtt->base.vm.scratch[1]); struct i915_page_table *pt; u32 pde; gen6_for_all_pdes(pt, pd, pde) - if (px_base(pt) != scratch) + if (pt) free_px(&ppgtt->base.vm, pt); } @@ -298,7 +293,7 @@ static void pd_vma_bind(struct i915_address_space *vm, struct gen6_ppgtt *ppgtt = vma->private; u32 ggtt_offset = i915_ggtt_offset(vma) / I915_GTT_PAGE_SIZE; - px_base(ppgtt->base.pd)->ggtt_offset = ggtt_offset * sizeof(gen6_pte_t); + ppgtt->pp_dir = ggtt_offset * sizeof(gen6_pte_t) << 10; ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset; gen6_flush_pd(ppgtt, 0, ppgtt->base.vm.total); @@ -308,8 +303,6 @@ static void pd_vma_unbind(struct i915_address_space *vm, struct i915_vma *vma) { struct gen6_ppgtt *ppgtt = vma->private; struct i915_page_directory * const pd = ppgtt->base.pd; - struct i915_page_dma * const scratch = - px_base(&ppgtt->base.vm.scratch[1]); struct i915_page_table *pt; unsigned int pde; @@ -318,11 +311,11 @@ static void pd_vma_unbind(struct i915_address_space *vm, struct i915_vma *vma) /* Free all no longer used page tables */ gen6_for_all_pdes(pt, ppgtt->base.pd, pde) { - if (px_base(pt) == scratch || atomic_read(&pt->used)) + if (!pt || atomic_read(&pt->used)) continue; free_px(&ppgtt->base.vm, pt); - pd->entry[pde] = scratch; + pd->entry[pde] = NULL; } ppgtt->scan_for_unused_pt = false; @@ -442,6 +435,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt) ppgtt->base.vm.insert_entries = gen6_ppgtt_insert_entries; ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup; + ppgtt->base.vm.alloc_pt_dma = alloc_pt_dma; ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode; ppgtt->base.pd = __alloc_pd(sizeof(*ppgtt->base.pd)); diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h index 72e481806c96..7249672e5802 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.h +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.h @@ -14,6 +14,7 @@ struct gen6_ppgtt { struct mutex flush; struct i915_vma *vma; gen6_pte_t __iomem *pd_addr; + u32 pp_dir; atomic_t pin_count; struct mutex pin_mutex; diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 58f5fd05f1e5..251a17c136fd 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -199,7 +199,7 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm, struct i915_page_directory * const pd, u64 start, const u64 end, int lvl) { - const struct i915_page_scratch * const scratch = &vm->scratch[lvl]; + const struct drm_i915_gem_object * const scratch = vm->scratch[lvl]; unsigned int idx, len; GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT); @@ -239,7 +239,7 @@ static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm, vaddr = kmap_atomic_px(pt); memset64(vaddr + gen8_pd_index(start, 0), - vm->scratch[0].encode, + vm->scratch[0]->encode, count); kunmap_atomic(vaddr); @@ -301,7 +301,7 @@ static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, if (lvl || gen8_pt_count(*start, end) < I915_PDES || intel_vgpu_active(vm->i915)) - fill_px(pt, vm->scratch[lvl].encode); + fill_px(pt, vm->scratch[lvl]->encode); spin_lock(&pd->lock); if (likely(!pd->entry[idx])) { @@ -357,16 +357,6 @@ static void gen8_ppgtt_alloc(struct i915_address_space *vm, i915_vma_free_pt_stash(vm, vma); } -static __always_inline void -write_pte(gen8_pte_t *pte, const gen8_pte_t val) -{ - /* Magic delays? Or can we refine these to flush all in one pass? */ - *pte = val; - wmb(); /* cpu to cache */ - clflush(pte); /* cache to memory */ - wmb(); /* visible to all */ -} - static __always_inline u64 gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, struct i915_page_directory *pdp, @@ -383,8 +373,7 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1))); do { GEM_BUG_ON(iter->sg->length < I915_GTT_PAGE_SIZE); - write_pte(&vaddr[gen8_pd_index(idx, 0)], - pte_encode | iter->dma); + vaddr[gen8_pd_index(idx, 0)] = pte_encode | iter->dma; iter->dma += I915_GTT_PAGE_SIZE; if (iter->dma >= iter->max) { @@ -407,10 +396,12 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, pd = pdp->entry[gen8_pd_index(idx, 2)]; } + clflush_cache_range(vaddr, PAGE_SIZE); kunmap_atomic(vaddr); vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1))); } } while (1); + clflush_cache_range(vaddr, PAGE_SIZE); kunmap_atomic(vaddr); return idx; @@ -466,7 +457,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, do { GEM_BUG_ON(iter->sg->length < page_size); - write_pte(&vaddr[index++], encode | iter->dma); + vaddr[index++] = encode | iter->dma; start += page_size; iter->dma += page_size; @@ -491,6 +482,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, } } while (rem >= page_size && index < I915_PDES); + clflush_cache_range(vaddr, PAGE_SIZE); kunmap_atomic(vaddr); /* @@ -522,7 +514,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) { u16 i; - encode = vma->vm->scratch[0].encode; + encode = vma->vm->scratch[0]->encode; vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K)); for (i = 1; i < index; i += 16) @@ -576,27 +568,31 @@ static int gen8_init_scratch(struct i915_address_space *vm) GEM_BUG_ON(!clone->has_read_only); vm->scratch_order = clone->scratch_order; - memcpy(vm->scratch, clone->scratch, sizeof(vm->scratch)); - px_dma(&vm->scratch[0]) = 0; /* no xfer of ownership */ + for (i = 0; i <= vm->top; i++) + vm->scratch[i] = i915_gem_object_get(clone->scratch[i]); + return 0; } - ret = setup_scratch_page(vm, __GFP_HIGHMEM); + ret = setup_scratch_page(vm); if (ret) return ret; - vm->scratch[0].encode = - gen8_pte_encode(px_dma(&vm->scratch[0]), + vm->scratch[0]->encode = + gen8_pte_encode(px_dma(vm->scratch[0]), I915_CACHE_LLC, vm->has_read_only); for (i = 1; i <= vm->top; i++) { - if (unlikely(setup_page_dma(vm, px_base(&vm->scratch[i])))) + struct drm_i915_gem_object *obj; + + obj = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); + if (IS_ERR(obj)) goto free_scratch; - fill_px(&vm->scratch[i], vm->scratch[i - 1].encode); - vm->scratch[i].encode = - gen8_pde_encode(px_dma(&vm->scratch[i]), - I915_CACHE_LLC); + fill_px(obj, vm->scratch[i - 1]->encode); + obj->encode = gen8_pde_encode(px_dma(obj), I915_CACHE_LLC); + + vm->scratch[i] = obj; } return 0; @@ -622,7 +618,7 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt) if (IS_ERR(pde)) return PTR_ERR(pde); - fill_px(pde, vm->scratch[1].encode); + fill_px(pde, vm->scratch[1]->encode); set_pd_entry(pd, idx, pde); atomic_inc(px_used(pde)); /* keep pinned */ } @@ -643,12 +639,13 @@ gen8_alloc_top_pd(struct i915_address_space *vm) if (unlikely(!pd)) return ERR_PTR(-ENOMEM); - if (unlikely(setup_page_dma(vm, px_base(pd)))) { + pd->pt.base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); + if (IS_ERR(pd->pt.base)) { kfree(pd); return ERR_PTR(-ENOMEM); } - fill_page_dma(px_base(pd), vm->scratch[vm->top].encode, count); + fill_page_dma(px_base(pd), vm->scratch[vm->top]->encode, count); atomic_inc(px_used(pd)); /* mark as pinned */ return pd; } @@ -682,12 +679,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt) */ ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12); - /* - * There are only few exceptions for gen >=6. chv and bxt. - * And we are not sure about the latter so play safe for now. - */ - if (IS_CHERRYVIEW(gt->i915) || IS_BROXTON(gt->i915)) - ppgtt->vm.pt_kmap_wc = true; + ppgtt->vm.alloc_pt_dma = alloc_pt_dma; err = gen8_init_scratch(&ppgtt->vm); if (err) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index e87568838034..cfba55c6050d 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -78,8 +78,6 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915) { int ret; - stash_init(&i915->mm.wc_stash); - /* * Note that we use page colouring to enforce a guard page at the * end of the address space. This is required as the CS may prefetch @@ -232,7 +230,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, /* Fill the allocated but "unused" space beyond the end of the buffer */ while (gte < end) - gen8_set_pte(gte++, vm->scratch[0].encode); + gen8_set_pte(gte++, vm->scratch[0]->encode); /* * We want to flush the TLBs only after we're certain all the PTE @@ -283,7 +281,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, /* Fill the allocated but "unused" space beyond the end of the buffer */ while (gte < end) - iowrite32(vm->scratch[0].encode, gte++); + iowrite32(vm->scratch[0]->encode, gte++); /* * We want to flush the TLBs only after we're certain all the PTE @@ -303,7 +301,7 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm, struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); unsigned int first_entry = start / I915_GTT_PAGE_SIZE; unsigned int num_entries = length / I915_GTT_PAGE_SIZE; - const gen8_pte_t scratch_pte = vm->scratch[0].encode; + const gen8_pte_t scratch_pte = vm->scratch[0]->encode; gen8_pte_t __iomem *gtt_base = (gen8_pte_t __iomem *)ggtt->gsm + first_entry; const int max_entries = ggtt_total_entries(ggtt) - first_entry; @@ -401,7 +399,7 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm, first_entry, num_entries, max_entries)) num_entries = max_entries; - scratch_pte = vm->scratch[0].encode; + scratch_pte = vm->scratch[0]->encode; for (i = 0; i < num_entries; i++) iowrite32(scratch_pte, >t_base[i]); } @@ -721,18 +719,11 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt) void i915_ggtt_driver_release(struct drm_i915_private *i915) { struct i915_ggtt *ggtt = &i915->ggtt; - struct pagevec *pvec; fini_aliasing_ppgtt(ggtt); intel_ggtt_fini_fences(ggtt); ggtt_cleanup_hw(ggtt); - - pvec = &i915->mm.wc_stash.pvec; - if (pvec->nr) { - set_pages_array_wb(pvec->pages, pvec->nr); - __pagevec_release(pvec); - } } static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) @@ -795,7 +786,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return -ENOMEM; } - ret = setup_scratch_page(&ggtt->vm, GFP_DMA32); + ret = setup_scratch_page(&ggtt->vm); if (ret) { drm_err(&i915->drm, "Scratch setup failed\n"); /* iounmap will also get called at remove, but meh */ @@ -803,8 +794,8 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) return ret; } - ggtt->vm.scratch[0].encode = - ggtt->vm.pte_encode(px_dma(&ggtt->vm.scratch[0]), + ggtt->vm.scratch[0]->encode = + ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]), I915_CACHE_NONE, 0); return 0; @@ -830,7 +821,7 @@ static void gen6_gmch_remove(struct i915_address_space *vm) struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); iounmap(ggtt->gsm); - cleanup_scratch_page(vm); + free_scratch(vm); } static struct resource pci_resource(struct pci_dev *pdev, int bar) @@ -858,6 +849,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) else size = gen8_get_total_gtt_size(snb_gmch_ctl); + ggtt->vm.alloc_pt_dma = alloc_pt_dma; + ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE; ggtt->vm.cleanup = gen6_gmch_remove; ggtt->vm.insert_page = gen8_ggtt_insert_page; @@ -1006,6 +999,8 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) size = gen6_get_total_gtt_size(snb_gmch_ctl); ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE; + ggtt->vm.alloc_pt_dma = alloc_pt_dma; + ggtt->vm.clear_range = nop_clear_range; if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915)) ggtt->vm.clear_range = gen6_ggtt_clear_range; @@ -1056,6 +1051,8 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt) ggtt->gmadr = (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end); + ggtt->vm.alloc_pt_dma = alloc_pt_dma; + ggtt->do_idle_maps = needs_idle_maps(i915); ggtt->vm.insert_page = i915_ggtt_insert_page; ggtt->vm.insert_entries = i915_ggtt_insert_entries; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 0e3827868e50..ab586ab160bb 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -11,160 +11,22 @@ #include "intel_gt.h" #include "intel_gtt.h" -void stash_init(struct pagestash *stash) +struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) { - pagevec_init(&stash->pvec); - spin_lock_init(&stash->lock); -} - -static struct page *stash_pop_page(struct pagestash *stash) -{ - struct page *page = NULL; - - spin_lock(&stash->lock); - if (likely(stash->pvec.nr)) - page = stash->pvec.pages[--stash->pvec.nr]; - spin_unlock(&stash->lock); - - return page; -} - -static void stash_push_pagevec(struct pagestash *stash, struct pagevec *pvec) -{ - unsigned int nr; - - spin_lock_nested(&stash->lock, SINGLE_DEPTH_NESTING); - - nr = min_t(typeof(nr), pvec->nr, pagevec_space(&stash->pvec)); - memcpy(stash->pvec.pages + stash->pvec.nr, - pvec->pages + pvec->nr - nr, - sizeof(pvec->pages[0]) * nr); - stash->pvec.nr += nr; - - spin_unlock(&stash->lock); - - pvec->nr -= nr; -} - -static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp) -{ - struct pagevec stack; - struct page *page; - - if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) - i915_gem_shrink_all(vm->i915); - - page = stash_pop_page(&vm->free_pages); - if (page) - return page; - - if (!vm->pt_kmap_wc) - return alloc_page(gfp); - - /* Look in our global stash of WC pages... */ - page = stash_pop_page(&vm->i915->mm.wc_stash); - if (page) - return page; - - /* - * Otherwise batch allocate pages to amortize cost of set_pages_wc. - * - * We have to be careful as page allocation may trigger the shrinker - * (via direct reclaim) which will fill up the WC stash underneath us. - * So we add our WB pages into a temporary pvec on the stack and merge - * them into the WC stash after all the allocations are complete. - */ - pagevec_init(&stack); - do { - struct page *page; - - page = alloc_page(gfp); - if (unlikely(!page)) - break; - - stack.pages[stack.nr++] = page; - } while (pagevec_space(&stack)); - - if (stack.nr && !set_pages_array_wc(stack.pages, stack.nr)) { - page = stack.pages[--stack.nr]; - - /* Merge spare WC pages to the global stash */ - if (stack.nr) - stash_push_pagevec(&vm->i915->mm.wc_stash, &stack); - - /* Push any surplus WC pages onto the local VM stash */ - if (stack.nr) - stash_push_pagevec(&vm->free_pages, &stack); - } - - /* Return unwanted leftovers */ - if (unlikely(stack.nr)) { - WARN_ON_ONCE(set_pages_array_wb(stack.pages, stack.nr)); - __pagevec_release(&stack); - } - - return page; -} - -static void vm_free_pages_release(struct i915_address_space *vm, - bool immediate) -{ - struct pagevec *pvec = &vm->free_pages.pvec; - struct pagevec stack; - - lockdep_assert_held(&vm->free_pages.lock); - GEM_BUG_ON(!pagevec_count(pvec)); - - if (vm->pt_kmap_wc) { - /* - * When we use WC, first fill up the global stash and then - * only if full immediately free the overflow. - */ - stash_push_pagevec(&vm->i915->mm.wc_stash, pvec); - - /* - * As we have made some room in the VM's free_pages, - * we can wait for it to fill again. Unless we are - * inside i915_address_space_fini() and must - * immediately release the pages! - */ - if (pvec->nr <= (immediate ? 0 : PAGEVEC_SIZE - 1)) - return; - - /* - * We have to drop the lock to allow ourselves to sleep, - * so take a copy of the pvec and clear the stash for - * others to use it as we sleep. - */ - stack = *pvec; - pagevec_reinit(pvec); - spin_unlock(&vm->free_pages.lock); + struct drm_i915_gem_object *obj; + int err; - pvec = &stack; - set_pages_array_wb(pvec->pages, pvec->nr); + obj = i915_gem_object_create_internal(vm->i915, sz); + if (IS_ERR(obj)) + return obj; - spin_lock(&vm->free_pages.lock); + err = i915_gem_object_pin_pages(obj); + if (err) { + i915_gem_object_put(obj); + return ERR_PTR(err); } - __pagevec_release(pvec); -} - -static void vm_free_page(struct i915_address_space *vm, struct page *page) -{ - /* - * On !llc, we need to change the pages back to WB. We only do so - * in bulk, so we rarely need to change the page attributes here, - * but doing so requires a stop_machine() from deep inside arch/x86/mm. - * To make detection of the possible sleep more likely, use an - * unconditional might_sleep() for everybody. - */ - might_sleep(); - spin_lock(&vm->free_pages.lock); - while (!pagevec_space(&vm->free_pages.pvec)) - vm_free_pages_release(vm, false); - GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec) >= PAGEVEC_SIZE); - pagevec_add(&vm->free_pages.pvec, page); - spin_unlock(&vm->free_pages.lock); + return obj; } void __i915_vm_close(struct i915_address_space *vm) @@ -194,14 +56,7 @@ void __i915_vm_close(struct i915_address_space *vm) void i915_address_space_fini(struct i915_address_space *vm) { - spin_lock(&vm->free_pages.lock); - if (pagevec_count(&vm->free_pages.pvec)) - vm_free_pages_release(vm, true); - GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec)); - spin_unlock(&vm->free_pages.lock); - drm_mm_takedown(&vm->mm); - mutex_destroy(&vm->mutex); } @@ -246,8 +101,6 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) drm_mm_init(&vm->mm, 0, vm->total); vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; - stash_init(&vm->free_pages); - INIT_LIST_HEAD(&vm->bound_list); } @@ -266,64 +119,47 @@ void clear_pages(struct i915_vma *vma) memset(&vma->page_sizes, 0, sizeof(vma->page_sizes)); } -static int __setup_page_dma(struct i915_address_space *vm, - struct i915_page_dma *p, - gfp_t gfp) -{ - p->page = vm_alloc_page(vm, gfp | I915_GFP_ALLOW_FAIL); - if (unlikely(!p->page)) - return -ENOMEM; - - p->daddr = dma_map_page_attrs(vm->dma, - p->page, 0, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL, - DMA_ATTR_SKIP_CPU_SYNC | - DMA_ATTR_NO_WARN); - if (unlikely(dma_mapping_error(vm->dma, p->daddr))) { - vm_free_page(vm, p->page); - return -ENOMEM; - } - - return 0; -} - -int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p) +dma_addr_t __px_dma(struct drm_i915_gem_object *p) { - return __setup_page_dma(vm, p, __GFP_HIGHMEM); + GEM_BUG_ON(!i915_gem_object_has_pages(p)); + return sg_dma_address(p->mm.pages->sgl); } -void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p) +struct page *__px_page(struct drm_i915_gem_object *p) { - dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - vm_free_page(vm, p->page); + GEM_BUG_ON(!i915_gem_object_has_pages(p)); + return sg_page(p->mm.pages->sgl); } void -fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count) +fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) { - kunmap_atomic(memset64(kmap_atomic(p->page), val, count)); + struct page *page = __px_page(p); + void *vaddr; + + vaddr = kmap(page); + memset64(vaddr, val, count); + kunmap(page); } -static void poison_scratch_page(struct page *page, unsigned long size) +static void poison_scratch_page(struct drm_i915_gem_object *scratch) { + struct sgt_iter sgt; + struct page *page; + if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) return; - GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE)); - - do { + for_each_sgt_page(page, sgt, scratch->mm.pages) { void *vaddr; vaddr = kmap(page); memset(vaddr, POISON_FREE, PAGE_SIZE); kunmap(page); - - page = pfn_to_page(page_to_pfn(page) + 1); - size -= PAGE_SIZE; - } while (size); + } } -int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) +int setup_scratch_page(struct i915_address_space *vm) { unsigned long size; @@ -340,21 +176,19 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) */ size = I915_GTT_PAGE_SIZE_4K; if (i915_vm_is_4lvl(vm) && - HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) { + HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K)) size = I915_GTT_PAGE_SIZE_64K; - gfp |= __GFP_NOWARN; - } - gfp |= __GFP_ZERO | __GFP_RETRY_MAYFAIL; do { - unsigned int order = get_order(size); - struct page *page; - dma_addr_t addr; + struct drm_i915_gem_object *obj; - page = alloc_pages(gfp, order); - if (unlikely(!page)) + obj = vm->alloc_pt_dma(vm, size); + if (IS_ERR(obj)) goto skip; + if (obj->mm.page_sizes.sg < size) + goto skip_obj; + /* * Use a non-zero scratch page for debugging. * @@ -364,61 +198,28 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp) * should it ever be accidentally used, the effect should be * fairly benign. */ - poison_scratch_page(page, size); - - addr = dma_map_page_attrs(vm->dma, - page, 0, size, - PCI_DMA_BIDIRECTIONAL, - DMA_ATTR_SKIP_CPU_SYNC | - DMA_ATTR_NO_WARN); - if (unlikely(dma_mapping_error(vm->dma, addr))) - goto free_page; - - if (unlikely(!IS_ALIGNED(addr, size))) - goto unmap_page; - - vm->scratch[0].base.page = page; - vm->scratch[0].base.daddr = addr; - vm->scratch_order = order; + poison_scratch_page(obj); + + vm->scratch[0] = obj; + vm->scratch_order = get_order(size); return 0; -unmap_page: - dma_unmap_page(vm->dma, addr, size, PCI_DMA_BIDIRECTIONAL); -free_page: - __free_pages(page, order); +skip_obj: + i915_gem_object_put(obj); skip: if (size == I915_GTT_PAGE_SIZE_4K) return -ENOMEM; size = I915_GTT_PAGE_SIZE_4K; - gfp &= ~__GFP_NOWARN; } while (1); } -void cleanup_scratch_page(struct i915_address_space *vm) -{ - struct i915_page_dma *p = px_base(&vm->scratch[0]); - unsigned int order = vm->scratch_order; - - dma_unmap_page(vm->dma, p->daddr, BIT(order) << PAGE_SHIFT, - PCI_DMA_BIDIRECTIONAL); - __free_pages(p->page, order); -} - void free_scratch(struct i915_address_space *vm) { int i; - if (!px_dma(&vm->scratch[0])) /* set to 0 on clones */ - return; - - for (i = 1; i <= vm->top; i++) { - if (!px_dma(&vm->scratch[i])) - break; - cleanup_page_dma(vm, px_base(&vm->scratch[i])); - } - - cleanup_scratch_page(vm); + for (i = 0; i <= vm->top; i++) + i915_gem_object_put(vm->scratch[i]); } void gtt_write_workarounds(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 9a80d15b2879..df36508e86df 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -134,31 +134,19 @@ typedef u64 gen8_pte_t; #define GEN8_PDE_IPS_64K BIT(11) #define GEN8_PDE_PS_2M BIT(7) +enum i915_cache_level; + +struct drm_i915_file_private; +struct drm_i915_gem_object; struct i915_fence_reg; +struct i915_vma; +struct intel_gt; #define for_each_sgt_daddr(__dp, __iter, __sgt) \ __for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE) -struct i915_page_dma { - struct page *page; - union { - dma_addr_t daddr; - - /* - * For gen6/gen7 only. This is the offset in the GGTT - * where the page directory entries for PPGTT begin - */ - u32 ggtt_offset; - }; -}; - -struct i915_page_scratch { - struct i915_page_dma base; - u64 encode; -}; - struct i915_page_table { - struct i915_page_dma base; + struct drm_i915_gem_object *base; union { atomic_t used; struct i915_page_table *stash; @@ -179,12 +167,14 @@ struct i915_page_directory { other) #define px_base(px) \ - __px_choose_expr(px, struct i915_page_dma *, __x, \ - __px_choose_expr(px, struct i915_page_scratch *, &__x->base, \ - __px_choose_expr(px, struct i915_page_table *, &__x->base, \ - __px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \ - (void)0)))) -#define px_dma(px) (px_base(px)->daddr) + __px_choose_expr(px, struct drm_i915_gem_object *, __x, \ + __px_choose_expr(px, struct i915_page_table *, __x->base, \ + __px_choose_expr(px, struct i915_page_directory *, __x->pt.base, \ + (void)0))) + +struct page *__px_page(struct drm_i915_gem_object *p); +dma_addr_t __px_dma(struct drm_i915_gem_object *p); +#define px_dma(px) (__px_dma(px_base(px))) #define px_pt(px) \ __px_choose_expr(px, struct i915_page_table *, __x, \ @@ -192,13 +182,6 @@ struct i915_page_directory { (void)0)) #define px_used(px) (&px_pt(px)->used) -enum i915_cache_level; - -struct drm_i915_file_private; -struct drm_i915_gem_object; -struct i915_vma; -struct intel_gt; - struct i915_vma_ops { /* Map an object into an address space with the given cache flags. */ void (*bind_vma)(struct i915_address_space *vm, @@ -216,13 +199,6 @@ struct i915_vma_ops { void (*clear_pages)(struct i915_vma *vma); }; -struct pagestash { - spinlock_t lock; - struct pagevec pvec; -}; - -void stash_init(struct pagestash *stash); - struct i915_address_space { struct kref ref; struct rcu_work rcu; @@ -259,7 +235,7 @@ struct i915_address_space { #define VM_CLASS_GGTT 0 #define VM_CLASS_PPGTT 1 - struct i915_page_scratch scratch[4]; + struct drm_i915_gem_object *scratch[4]; unsigned int scratch_order; unsigned int top; @@ -268,17 +244,15 @@ struct i915_address_space { */ struct list_head bound_list; - struct pagestash free_pages; - /* Global GTT */ bool is_ggtt:1; - /* Some systems require uncached updates of the page directories */ - bool pt_kmap_wc:1; - /* Some systems support read-only mappings for GGTT and/or PPGTT */ bool has_read_only:1; + struct drm_i915_gem_object * + (*alloc_pt_dma)(struct i915_address_space *vm, int sz); + u64 (*pte_encode)(dma_addr_t addr, enum i915_cache_level level, u32 flags); /* Create a valid PTE */ @@ -494,9 +468,9 @@ i915_pd_entry(const struct i915_page_directory * const pdp, static inline dma_addr_t i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n) { - struct i915_page_dma *pt = ppgtt->pd->entry[n]; + struct i915_page_table *pt = ppgtt->pd->entry[n]; - return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top])); + return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]); } void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt); @@ -521,13 +495,10 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt); void i915_ggtt_suspend(struct i915_ggtt *gtt); void i915_ggtt_resume(struct i915_ggtt *ggtt); -int setup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p); -void cleanup_page_dma(struct i915_address_space *vm, struct i915_page_dma *p); - -#define kmap_atomic_px(px) kmap_atomic(px_base(px)->page) +#define kmap_atomic_px(px) kmap_atomic(__px_page(px_base(px))) void -fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count); +fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count); #define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64)) #define fill32_px(px, v) do { \ @@ -535,37 +506,36 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count); fill_px((px), v__ << 32 | v__); \ } while (0) -int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp); -void cleanup_scratch_page(struct i915_address_space *vm); +int setup_scratch_page(struct i915_address_space *vm); void free_scratch(struct i915_address_space *vm); +struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz); struct i915_page_table *alloc_pt(struct i915_address_space *vm); struct i915_page_directory *alloc_pd(struct i915_address_space *vm); struct i915_page_directory *__alloc_pd(size_t sz); -void free_pd(struct i915_address_space *vm, struct i915_page_dma *pd); - -#define free_px(vm, px) free_pd(vm, px_base(px)) +void free_pt(struct i915_address_space *vm, struct i915_page_table *pt); +#define free_px(vm, px) free_pt(vm, px_pt(px)) void __set_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, - struct i915_page_dma * const to, + struct i915_page_table *pt, u64 (*encode)(const dma_addr_t, const enum i915_cache_level)); #define set_pd_entry(pd, idx, to) \ - __set_pd_entry((pd), (idx), px_base(to), gen8_pde_encode) + __set_pd_entry((pd), (idx), px_pt(to), gen8_pde_encode) void clear_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, - const struct i915_page_scratch * const scratch); + const struct drm_i915_gem_object * const scratch); bool release_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, struct i915_page_table * const pt, - const struct i915_page_scratch * const scratch); + const struct drm_i915_gem_object * const scratch); void gen6_ggtt_invalidate(struct i915_ggtt *ggtt); int ggtt_set_pages(struct i915_vma *vma); diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index e017351b8d03..54b8edf8c247 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -18,7 +18,8 @@ struct i915_page_table *alloc_pt(struct i915_address_space *vm) if (unlikely(!pt)) return ERR_PTR(-ENOMEM); - if (unlikely(setup_page_dma(vm, &pt->base))) { + pt->base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); + if (IS_ERR(pt->base)) { kfree(pt); return ERR_PTR(-ENOMEM); } @@ -47,7 +48,8 @@ struct i915_page_directory *alloc_pd(struct i915_address_space *vm) if (unlikely(!pd)) return ERR_PTR(-ENOMEM); - if (unlikely(setup_page_dma(vm, px_base(pd)))) { + pd->pt.base = vm->alloc_pt_dma(vm, I915_GTT_PAGE_SIZE_4K); + if (IS_ERR(pd->pt.base)) { kfree(pd); return ERR_PTR(-ENOMEM); } @@ -55,27 +57,28 @@ struct i915_page_directory *alloc_pd(struct i915_address_space *vm) return pd; } -void free_pd(struct i915_address_space *vm, struct i915_page_dma *pd) +void free_pt(struct i915_address_space *vm, struct i915_page_table *pt) { - cleanup_page_dma(vm, pd); - kfree(pd); + i915_gem_object_put(pt->base); + kfree(pt); } static inline void -write_dma_entry(struct i915_page_dma * const pdma, +write_dma_entry(struct drm_i915_gem_object * const pdma, const unsigned short idx, const u64 encoded_entry) { - u64 * const vaddr = kmap_atomic(pdma->page); + u64 * const vaddr = kmap_atomic(__px_page(pdma)); vaddr[idx] = encoded_entry; + clflush_cache_range(&vaddr[idx], sizeof(u64)); kunmap_atomic(vaddr); } void __set_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, - struct i915_page_dma * const to, + struct i915_page_table * const to, u64 (*encode)(const dma_addr_t, const enum i915_cache_level)) { /* Each thread pre-pins the pd, and we may have a thread per pde. */ @@ -83,13 +86,13 @@ __set_pd_entry(struct i915_page_directory * const pd, atomic_inc(px_used(pd)); pd->entry[idx] = to; - write_dma_entry(px_base(pd), idx, encode(to->daddr, I915_CACHE_LLC)); + write_dma_entry(px_base(pd), idx, encode(px_dma(to), I915_CACHE_LLC)); } void clear_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, - const struct i915_page_scratch * const scratch) + const struct drm_i915_gem_object * const scratch) { GEM_BUG_ON(atomic_read(px_used(pd)) == 0); @@ -102,7 +105,7 @@ bool release_pd_entry(struct i915_page_directory * const pd, const unsigned short idx, struct i915_page_table * const pt, - const struct i915_page_scratch * const scratch) + const struct drm_i915_gem_object * const scratch) { bool free = false; diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 68a08486fc87..f1f27b7fc746 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -201,16 +201,18 @@ static struct i915_address_space *vm_alias(struct i915_address_space *vm) return vm; } +static u32 pp_dir(struct i915_address_space *vm) +{ + return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir; +} + static void set_pp_dir(struct intel_engine_cs *engine) { struct i915_address_space *vm = vm_alias(engine->gt->vm); if (vm) { - struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); - ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G); - ENGINE_WRITE(engine, RING_PP_DIR_BASE, - px_base(ppgtt->pd)->ggtt_offset << 10); + ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm)); } } @@ -608,7 +610,7 @@ static const struct intel_context_ops ring_context_ops = { }; static int load_pd_dir(struct i915_request *rq, - const struct i915_ppgtt *ppgtt, + struct i915_address_space *vm, u32 valid) { const struct intel_engine_cs * const engine = rq->engine; @@ -624,7 +626,7 @@ static int load_pd_dir(struct i915_request *rq, *cs++ = MI_LOAD_REGISTER_IMM(1); *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); - *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10; + *cs++ = pp_dir(vm); /* Stall until the page table load is complete? */ *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; @@ -826,7 +828,7 @@ static int switch_mm(struct i915_request *rq, struct i915_address_space *vm) * post-sync op, this extra pass appears vital before a * mm switch! */ - ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm), PP_DIR_DCLV_2G); + ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 3c3b9842bbbd..1570eb8aa978 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -403,6 +403,14 @@ static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) wa_ctx->indirect_ctx.shadow_va = NULL; } +static void set_dma_address(struct i915_page_directory *pd, dma_addr_t addr) +{ + struct scatterlist *sg = pd->pt.base->mm.pages->sgl; + + /* This is not a good idea */ + sg->dma_address = addr; +} + static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, struct intel_context *ce) { @@ -411,7 +419,7 @@ static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, int i = 0; if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { - px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0]; + set_dma_address(ppgtt->pd, mm->ppgtt_mm.shadow_pdps[0]); } else { for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) { struct i915_page_directory * const pd = @@ -421,7 +429,8 @@ static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, shadow ppgtt. */ if (!pd) break; - px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i]; + + set_dma_address(pd, mm->ppgtt_mm.shadow_pdps[i]); } } } @@ -1240,13 +1249,13 @@ i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s, int i; if (i915_vm_is_4lvl(&ppgtt->vm)) { - px_dma(ppgtt->pd) = s->i915_context_pml4; + set_dma_address(ppgtt->pd, s->i915_context_pml4); } else { for (i = 0; i < GEN8_3LVL_PDPES; i++) { struct i915_page_directory * const pd = i915_pd_entry(ppgtt->pd, i); - px_dma(pd) = s->i915_context_pdps[i]; + set_dma_address(pd, s->i915_context_pdps[i]); } } } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 67102dc26fce..ea281d7b0630 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1080,6 +1080,7 @@ static void i915_driver_release(struct drm_device *dev) intel_memory_regions_driver_release(dev_priv); i915_ggtt_driver_release(dev_priv); + i915_gem_drain_freed_objects(dev_priv); i915_driver_mmio_release(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9aad3ec979bd..7fcc406b5597 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -588,11 +588,6 @@ struct i915_gem_mm { */ atomic_t free_count; - /** - * Small stash of WC pages - */ - struct pagestash wc_stash; - /** * tmpfs instance used for shmem backed objects */ diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c index 779ddcba101c..dc7ef2682fe8 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -77,6 +77,8 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT); + ppgtt->vm.alloc_pt_dma = alloc_pt_dma; + ppgtt->vm.clear_range = mock_clear_range; ppgtt->vm.insert_page = mock_insert_page; ppgtt->vm.insert_entries = mock_insert_entries; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 29 10:12:51 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 11:12:51 +0100 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/gem: Move obj->lut_list under its own lock Message-ID: <20200629101256.13039-1-chris@chris-wilson.co.uk> The obj->lut_list is traversed when the object is closed as the file table is destroyed during process termination. As this occurs before we kill any outstanding context if, due to some bug or another, the closure is blocked, then we fail to shootdown any inflight operations potentially leaving the GPU spinning forever. As we only need to guard the list against concurrent closures and insertions, the hold is short and merits being treated as a simple spinlock. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++---- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/gem/i915_gem_object.c | 5 +++-- drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 + 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 5c13809dc3c8..6675447a47b9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -112,8 +112,7 @@ static void lut_close(struct i915_gem_context *ctx) if (!kref_get_unless_zero(&obj->base.refcount)) continue; - rcu_read_unlock(); - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); list_for_each_entry(lut, &obj->lut_list, obj_link) { if (lut->ctx != ctx) continue; @@ -124,8 +123,7 @@ static void lut_close(struct i915_gem_context *ctx) list_del(&lut->obj_link); break; } - i915_gem_object_unlock(obj); - rcu_read_lock(); + spin_unlock(&obj->lut_lock); if (&lut->obj_link != &obj->lut_list) { i915_lut_handle_free(lut); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..b4862afaaf28 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -789,14 +789,14 @@ static int __eb_add_lut(struct i915_execbuffer *eb, if (err == 0) { /* And nor has this handle */ struct drm_i915_gem_object *obj = vma->obj; - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); if (idr_find(&eb->file->object_idr, handle) == obj) { list_add(&lut->obj_link, &obj->lut_list); } else { radix_tree_delete(&ctx->handles_vma, handle); err = -ENOENT; } - i915_gem_object_unlock(obj); + spin_unlock(&obj->lut_lock); } mutex_unlock(&ctx->mutex); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index b6ec5b50d93b..8222e8b33efd 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -61,6 +61,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, INIT_LIST_HEAD(&obj->mm.link); INIT_LIST_HEAD(&obj->lut_list); + spin_lock_init(&obj->lut_lock); spin_lock_init(&obj->mmo.lock); obj->mmo.offsets = RB_ROOT; @@ -108,7 +109,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) struct i915_lut_handle *lut, *ln; LIST_HEAD(close); - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { struct i915_gem_context *ctx = lut->ctx; @@ -118,7 +119,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) i915_gem_context_get(ctx); list_move(&lut->obj_link, &close); } - i915_gem_object_unlock(obj); + spin_unlock(&obj->lut_lock); spin_lock(&obj->mmo.lock); rbtree_postorder_for_each_entry_safe(mmo, mn, &obj->mmo.offsets, offset) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index b1f82a11aef2..0fd677ad8ec8 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -121,6 +121,7 @@ struct drm_i915_gem_object { * this translation from object to context->handles_vma. */ struct list_head lut_list; + spinlock_t lut_lock; /* guards for lut_list */ /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 29 10:12:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 11:12:55 +0100 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Preallocate stashes for vma page-directories In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <20200629101256.13039-5-chris@chris-wilson.co.uk> We need to make the DMA allocations used for page directories to be performed up front so that we can include those allocations in our memory reservation pass. The downside is that we have to assume the worst case, even before we know the final layout, and always allocate enough page directories for this object, even when there will be overlap. It should be noted that the lifetime for the page directories DMA is more or less decoupled from individual fences as they will be shared across objects across timelines. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- .../gpu/drm/i915/gem/i915_gem_client_blt.c | 17 ++-- drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 39 ++++----- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 76 +++++------------ drivers/gpu/drm/i915/gt/intel_ggtt.c | 54 ++++++------ drivers/gpu/drm/i915/gt/intel_gtt.c | 2 + drivers/gpu/drm/i915/gt/intel_gtt.h | 31 ++++--- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 82 ++++++++++++++++--- drivers/gpu/drm/i915/i915_vma.c | 13 +-- drivers/gpu/drm/i915/i915_vma_types.h | 2 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 59 +++++++------ drivers/gpu/drm/i915/selftests/mock_gtt.c | 20 ++--- 11 files changed, 218 insertions(+), 177 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c index 278664f831e7..eb1f433b7730 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c @@ -19,6 +19,11 @@ struct i915_sleeve { static int vma_set_pages(struct i915_vma *vma) { struct i915_sleeve *sleeve = vma->private; + int err; + + err = i915_vma_alloc_pt_stash(vma->vm, vma); + if (err) + return err; vma->pages = sleeve->pages; vma->page_sizes = sleeve->page_sizes; @@ -30,14 +35,16 @@ static void vma_clear_pages(struct i915_vma *vma) { GEM_BUG_ON(!vma->pages); vma->pages = NULL; + + i915_vma_free_pt_stash(vma->vm, vma); } -static int vma_bind(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +static void vma_bind(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { - return vm->vma_ops.bind_vma(vm, vma, cache_level, flags); + vm->vma_ops.bind_vma(vm, vma, cache_level, flags); } static void vma_unbind(struct i915_address_space *vm, struct i915_vma *vma) diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index 05497b50103f..dfde5fd452f1 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -177,16 +177,16 @@ static void gen6_flush_pd(struct gen6_ppgtt *ppgtt, u64 start, u64 end) mutex_unlock(&ppgtt->flush); } -static int gen6_alloc_va_range(struct i915_address_space *vm, - u64 start, u64 length) +static void gen6_alloc_va_range(struct i915_address_space *vm, + struct i915_vma *vma, + u64 start, u64 length) { struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm)); struct i915_page_directory * const pd = ppgtt->base.pd; - struct i915_page_table *pt, *alloc = NULL; + struct i915_page_table *pt; intel_wakeref_t wakeref; u64 from = start; unsigned int pde; - int ret = 0; wakeref = intel_runtime_pm_get(&vm->i915->runtime_pm); @@ -197,21 +197,17 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, if (px_base(pt) == px_base(&vm->scratch[1])) { spin_unlock(&pd->lock); - pt = fetch_and_zero(&alloc); - if (!pt) - pt = alloc_pt(vm); - if (IS_ERR(pt)) { - ret = PTR_ERR(pt); - goto unwind_out; - } + pt = vma->pt_stash[0]; + GEM_BUG_ON(!pt); fill32_px(pt, vm->scratch[0].encode); spin_lock(&pd->lock); if (pd->entry[pde] == &vm->scratch[1]) { + vma->pt_stash[0] = pt->stash; + atomic_set(&pt->used, 0); pd->entry[pde] = pt; } else { - alloc = pt; pt = pd->entry[pde]; } } @@ -223,15 +219,9 @@ static int gen6_alloc_va_range(struct i915_address_space *vm, if (i915_vma_is_bound(ppgtt->vma, I915_VMA_GLOBAL_BIND)) gen6_flush_pd(ppgtt, from, start); - goto out; - -unwind_out: - gen6_ppgtt_clear_range(vm, from, start - from); -out: - if (alloc) - free_px(vm, alloc); intel_runtime_pm_put(&vm->i915->runtime_pm, wakeref); - return ret; + + i915_vma_free_pt_stash(vm, vma); } static int gen6_ppgtt_init_scratch(struct gen6_ppgtt *ppgtt) @@ -299,10 +289,10 @@ static void pd_vma_clear_pages(struct i915_vma *vma) vma->pages = NULL; } -static int pd_vma_bind(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 unused) +static void pd_vma_bind(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 unused) { struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); struct gen6_ppgtt *ppgtt = vma->private; @@ -312,7 +302,6 @@ static int pd_vma_bind(struct i915_address_space *vm, ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset; gen6_flush_pd(ppgtt, 0, ppgtt->base.vm.total); - return 0; } static void pd_vma_unbind(struct i915_address_space *vm, struct i915_vma *vma) diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 699125928272..58f5fd05f1e5 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -269,14 +269,12 @@ static void gen8_ppgtt_clear(struct i915_address_space *vm, start, start + length, vm->top); } -static int __gen8_ppgtt_alloc(struct i915_address_space * const vm, - struct i915_page_directory * const pd, - u64 * const start, const u64 end, int lvl) +static void __gen8_ppgtt_alloc(struct i915_address_space * const vm, + struct i915_vma *vma, + struct i915_page_directory * const pd, + u64 * const start, const u64 end, int lvl) { - const struct i915_page_scratch * const scratch = &vm->scratch[lvl]; - struct i915_page_table *alloc = NULL; unsigned int idx, len; - int ret = 0; GEM_BUG_ON(end > vm->total >> GEN8_PTE_SHIFT); @@ -297,49 +295,29 @@ static int __gen8_ppgtt_alloc(struct i915_address_space * const vm, DBG("%s(%p):{ lvl:%d, idx:%d } allocating new tree\n", __func__, vm, lvl + 1, idx); - pt = fetch_and_zero(&alloc); - if (lvl) { - if (!pt) { - pt = &alloc_pd(vm)->pt; - if (IS_ERR(pt)) { - ret = PTR_ERR(pt); - goto out; - } - } + pt = vma->pt_stash[!!lvl]; + GEM_BUG_ON(!pt); + if (lvl || + gen8_pt_count(*start, end) < I915_PDES || + intel_vgpu_active(vm->i915)) fill_px(pt, vm->scratch[lvl].encode); - } else { - if (!pt) { - pt = alloc_pt(vm); - if (IS_ERR(pt)) { - ret = PTR_ERR(pt); - goto out; - } - } - - if (intel_vgpu_active(vm->i915) || - gen8_pt_count(*start, end) < I915_PDES) - fill_px(pt, vm->scratch[lvl].encode); - } spin_lock(&pd->lock); - if (likely(!pd->entry[idx])) + if (likely(!pd->entry[idx])) { + vma->pt_stash[!!lvl] = pt->stash; + atomic_set(&pt->used, 0); set_pd_entry(pd, idx, pt); - else - alloc = pt, pt = pd->entry[idx]; + } else { + pt = pd->entry[idx]; + } } if (lvl) { atomic_inc(&pt->used); spin_unlock(&pd->lock); - ret = __gen8_ppgtt_alloc(vm, as_pd(pt), - start, end, lvl); - if (unlikely(ret)) { - if (release_pd_entry(pd, idx, pt, scratch)) - free_px(vm, pt); - goto out; - } + __gen8_ppgtt_alloc(vm, vma, as_pd(pt), start, end, lvl); spin_lock(&pd->lock); atomic_dec(&pt->used); @@ -359,18 +337,12 @@ static int __gen8_ppgtt_alloc(struct i915_address_space * const vm, } } while (idx++, --len); spin_unlock(&pd->lock); -out: - if (alloc) - free_px(vm, alloc); - return ret; } -static int gen8_ppgtt_alloc(struct i915_address_space *vm, - u64 start, u64 length) +static void gen8_ppgtt_alloc(struct i915_address_space *vm, + struct i915_vma *vma, + u64 start, u64 length) { - u64 from; - int err; - GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT))); GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT))); GEM_BUG_ON(range_overflows(start, length, vm->total)); @@ -378,15 +350,11 @@ static int gen8_ppgtt_alloc(struct i915_address_space *vm, start >>= GEN8_PTE_SHIFT; length >>= GEN8_PTE_SHIFT; GEM_BUG_ON(length == 0); - from = start; - err = __gen8_ppgtt_alloc(vm, i915_vm_to_ppgtt(vm)->pd, - &start, start + length, vm->top); - if (unlikely(err && from != start)) - __gen8_ppgtt_clear(vm, i915_vm_to_ppgtt(vm)->pd, - from, start, vm->top); + __gen8_ppgtt_alloc(vm, vma, i915_vm_to_ppgtt(vm)->pd, + &start, start + length, vm->top); - return err; + i915_vma_free_pt_stash(vm, vma); } static __always_inline void diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 62979ea591f0..e87568838034 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -436,16 +436,16 @@ static void i915_ggtt_clear_range(struct i915_address_space *vm, intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); } -static int ggtt_bind_vma(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +static void ggtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { struct drm_i915_gem_object *obj = vma->obj; u32 pte_flags; if (i915_vma_is_bound(vma, ~flags & I915_VMA_BIND_MASK)) - return 0; + return; /* Applicable to VLV (gen8+ do not support RO in the GGTT) */ pte_flags = 0; @@ -454,8 +454,6 @@ static int ggtt_bind_vma(struct i915_address_space *vm, vm->insert_entries(vm, vma, cache_level, pte_flags); vma->page_sizes.gtt = I915_GTT_PAGE_SIZE; - - return 0; } static void ggtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma) @@ -568,31 +566,24 @@ static int init_ggtt(struct i915_ggtt *ggtt) return ret; } -static int aliasing_gtt_bind_vma(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +static void aliasing_gtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { u32 pte_flags; - int ret; /* Currently applicable only to VLV */ pte_flags = 0; if (i915_gem_object_is_readonly(vma->obj)) pte_flags |= PTE_READ_ONLY; - if (flags & I915_VMA_LOCAL_BIND) { - struct i915_ppgtt *alias = i915_vm_to_ggtt(vm)->alias; - - ret = ppgtt_bind_vma(&alias->vm, vma, cache_level, flags); - if (ret) - return ret; - } + if (flags & I915_VMA_LOCAL_BIND) + ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm, + vma, cache_level, flags); if (flags & I915_VMA_GLOBAL_BIND) vm->insert_entries(vm, vma, cache_level, pte_flags); - - return 0; } static void aliasing_gtt_unbind_vma(struct i915_address_space *vm, @@ -608,6 +599,7 @@ static void aliasing_gtt_unbind_vma(struct i915_address_space *vm, static int init_aliasing_ppgtt(struct i915_ggtt *ggtt) { struct i915_ppgtt *ppgtt; + struct i915_vma *stash; int err; ppgtt = i915_ppgtt_create(ggtt->vm.gt); @@ -619,15 +611,24 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt) goto err_ppgtt; } + stash = i915_vma_alloc(); + if (IS_ERR(stash)) { + err = PTR_ERR(stash); + goto err_ppgtt; + } + + stash->size = ggtt->vm.total; + err = i915_vma_alloc_pt_stash(&ppgtt->vm, stash); + if (err) + goto err_vma; + /* * Note we only pre-allocate as far as the end of the global * GTT. On 48b / 4-level page-tables, the difference is very, * very significant! We have to preallocate as GVT/vgpu does * not like the page directory disappearing. */ - err = ppgtt->vm.allocate_va_range(&ppgtt->vm, 0, ggtt->vm.total); - if (err) - goto err_ppgtt; + ppgtt->vm.allocate_va_range(&ppgtt->vm, stash, 0, ggtt->vm.total); ggtt->alias = ppgtt; ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags; @@ -638,8 +639,13 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt) GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma); ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma; + i915_vma_free(stash); + return 0; +err_vma: + i915_vma_free_pt_stash(&ppgtt->vm, stash); + i915_vma_free(stash); err_ppgtt: i915_vm_put(&ppgtt->vm); return err; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 2a72cce63fd9..0e3827868e50 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -255,6 +255,8 @@ void clear_pages(struct i915_vma *vma) { GEM_BUG_ON(!vma->pages); + i915_vma_free_pt_stash(vma->vm, vma); + if (vma->pages != vma->obj->mm.pages) { sg_free_table(vma->pages); kfree(vma->pages); diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index f2b75078e05f..9a80d15b2879 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -159,7 +159,10 @@ struct i915_page_scratch { struct i915_page_table { struct i915_page_dma base; - atomic_t used; + union { + atomic_t used; + struct i915_page_table *stash; + }; }; struct i915_page_directory { @@ -198,10 +201,10 @@ struct intel_gt; struct i915_vma_ops { /* Map an object into an address space with the given cache flags. */ - int (*bind_vma)(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags); + void (*bind_vma)(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags); /* * Unmap an object from an address space. This usually consists of * setting the valid PTE entries to a reserved scratch page. @@ -281,8 +284,9 @@ struct i915_address_space { u32 flags); /* Create a valid PTE */ #define PTE_READ_ONLY BIT(0) - int (*allocate_va_range)(struct i915_address_space *vm, - u64 start, u64 length); + void (*allocate_va_range)(struct i915_address_space *vm, + struct i915_vma *vma, + u64 start, u64 length); void (*clear_range)(struct i915_address_space *vm, u64 start, u64 length); void (*insert_page)(struct i915_address_space *vm, @@ -568,10 +572,10 @@ int ggtt_set_pages(struct i915_vma *vma); int ppgtt_set_pages(struct i915_vma *vma); void clear_pages(struct i915_vma *vma); -int ppgtt_bind_vma(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags); +void ppgtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags); void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma); @@ -579,6 +583,11 @@ void gtt_write_workarounds(struct intel_gt *gt); void setup_private_pat(struct intel_uncore *uncore); +int i915_vma_alloc_pt_stash(struct i915_address_space *vm, + struct i915_vma *vma); +void i915_vma_free_pt_stash(struct i915_address_space *vm, + struct i915_vma *vma); + static inline struct sgt_dma { struct scatterlist *sg; dma_addr_t dma, max; diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index f0862e924d11..e017351b8d03 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -155,18 +155,16 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt) return ppgtt; } -int ppgtt_bind_vma(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +void ppgtt_bind_vma(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { u32 pte_flags; - int err; if (!test_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma))) { - err = vm->allocate_va_range(vm, vma->node.start, vma->size); - if (err) - return err; + vm->allocate_va_range(vm, vma, + vma->node.start, vma->size); set_bit(I915_VMA_ALLOC_BIT, __i915_vma_flags(vma)); } @@ -178,8 +176,6 @@ int ppgtt_bind_vma(struct i915_address_space *vm, vm->insert_entries(vm, vma, cache_level, pte_flags); wmb(); - - return 0; } void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma) @@ -188,12 +184,76 @@ void ppgtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma) vm->clear_range(vm, vma->node.start, vma->size); } +static unsigned long pd_count(u64 size, int shift) +{ + size = (size + BIT_ULL(shift) - 1) >> shift; + return size + 1; /* beware later misalignment */ +} + +int i915_vma_alloc_pt_stash(struct i915_address_space *vm, struct i915_vma *vma) +{ + unsigned long count; + int shift = 21; + int n; + + count = pd_count(vma->size, shift); + while (count--) { + struct i915_page_table *pt; + + pt = alloc_pt(vm); + if (IS_ERR(pt)) { + i915_vma_free_pt_stash(vm, vma); + return PTR_ERR(pt); + } + + pt->stash = vma->pt_stash[0]; + vma->pt_stash[0] = pt; + } + + for (n = 1; n <= vm->top; n++) { + shift += 9; + count = pd_count(vma->size, shift); + while (count--) { + struct i915_page_directory *pd; + + pd = alloc_pd(vm); + if (IS_ERR(pd)) { + i915_vma_free_pt_stash(vm, vma); + return PTR_ERR(pd); + } + + pd->pt.stash = vma->pt_stash[1]; + vma->pt_stash[1] = &pd->pt; + } + } + + return 0; +} + +void i915_vma_free_pt_stash(struct i915_address_space *vm, struct i915_vma *vma) +{ + struct i915_page_table *pt; + int n; + + for (n = 0; n < ARRAY_SIZE(vma->pt_stash); n++) { + while ((pt = vma->pt_stash[n])) { + vma->pt_stash[n] = pt->stash; + free_px(vm, pt); + } + } +} + int ppgtt_set_pages(struct i915_vma *vma) { + int err; + GEM_BUG_ON(vma->pages); - vma->pages = vma->obj->mm.pages; + err = i915_vma_alloc_pt_stash(vma->vm, vma); + if(err) + return err; + vma->pages = vma->obj->mm.pages; vma->page_sizes = vma->obj->mm.page_sizes; return 0; diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 9c85c4f6e995..adaf1e95af02 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -305,13 +305,9 @@ static int __vma_bind(struct dma_fence_work *work) { struct i915_vma_work *vw = container_of(work, typeof(*vw), base); struct i915_vma *vma = vw->vma; - int err; - - err = vma->ops->bind_vma(vma->vm, vma, vw->cache_level, vw->flags); - if (err) - atomic_or(I915_VMA_ERROR, &vma->flags); - return err; + vma->ops->bind_vma(vma->vm, vma, vw->cache_level, vw->flags); + return 0; } static void __vma_release(struct dma_fence_work *work) @@ -379,7 +375,6 @@ int i915_vma_bind(struct i915_vma *vma, { u32 bind_flags; u32 vma_flags; - int ret; GEM_BUG_ON(!drm_mm_node_allocated(&vma->node)); GEM_BUG_ON(vma->size > vma->node.size); @@ -436,9 +431,7 @@ int i915_vma_bind(struct i915_vma *vma, work->pinned = vma->obj; } } else { - ret = vma->ops->bind_vma(vma->vm, vma, cache_level, bind_flags); - if (ret) - return ret; + vma->ops->bind_vma(vma->vm, vma, cache_level, bind_flags); } atomic_or(bind_flags, &vma->flags); diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h index 9e9082dc8f4b..6d7755858156 100644 --- a/drivers/gpu/drm/i915/i915_vma_types.h +++ b/drivers/gpu/drm/i915/i915_vma_types.h @@ -256,6 +256,8 @@ struct i915_vma { atomic_t pages_count; /* number of active binds to the pages */ struct mutex pages_mutex; /* protect acquire/release of backing pages */ + void *pt_stash[2]; /* preallocated stash of page tables/directories */ + /** * Support different GGTT views into the same object. * This means there can be multiple VMA mappings per object and per VM. diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c index 0016ffc7d914..4bd18b901c5e 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c @@ -146,6 +146,7 @@ static int igt_ppgtt_alloc(void *arg) struct drm_i915_private *dev_priv = arg; struct i915_ppgtt *ppgtt; u64 size, last, limit; + struct i915_vma *vma; int err = 0; /* Allocate a ppggt and try to fill the entire range */ @@ -160,6 +161,12 @@ static int igt_ppgtt_alloc(void *arg) if (!ppgtt->vm.allocate_va_range) goto err_ppgtt_cleanup; + vma = i915_vma_alloc(); + if (!vma) { + err = -ENOMEM; + goto err_ppgtt_cleanup; + } + /* * While we only allocate the page tables here and so we could * address a much larger GTT than we could actually fit into @@ -172,16 +179,12 @@ static int igt_ppgtt_alloc(void *arg) /* Check we can allocate the entire range */ for (size = 4096; size <= limit; size <<= 2) { - err = ppgtt->vm.allocate_va_range(&ppgtt->vm, 0, size); - if (err) { - if (err == -ENOMEM) { - pr_info("[1] Ran out of memory for va_range [0 + %llx] [bit %d]\n", - size, ilog2(size)); - err = 0; /* virtual space too large! */ - } - goto err_ppgtt_cleanup; - } + vma->size = size; + err = i915_vma_alloc_pt_stash(&ppgtt->vm, vma); + if (err) + goto err_vma; + ppgtt->vm.allocate_va_range(&ppgtt->vm, vma, 0, size); cond_resched(); ppgtt->vm.clear_range(&ppgtt->vm, 0, size); @@ -189,20 +192,18 @@ static int igt_ppgtt_alloc(void *arg) /* Check we can incrementally allocate the entire range */ for (last = 0, size = 4096; size <= limit; last = size, size <<= 2) { - err = ppgtt->vm.allocate_va_range(&ppgtt->vm, - last, size - last); - if (err) { - if (err == -ENOMEM) { - pr_info("[2] Ran out of memory for va_range [%llx + %llx] [bit %d]\n", - last, size - last, ilog2(size)); - err = 0; /* virtual space too large! */ - } - goto err_ppgtt_cleanup; - } + vma->size = size - last; + err = i915_vma_alloc_pt_stash(&ppgtt->vm, vma); + if (err) + goto err_vma; + ppgtt->vm.allocate_va_range(&ppgtt->vm, vma, last, size - last); cond_resched(); } +err_vma: + i915_vma_free_pt_stash(&ppgtt->vm, vma); + i915_vma_free(vma); err_ppgtt_cleanup: i915_vm_put(&ppgtt->vm); return err; @@ -284,9 +285,15 @@ static int lowlevel_hole(struct i915_address_space *vm, break; } - if (vm->allocate_va_range && - vm->allocate_va_range(vm, addr, BIT_ULL(size))) - break; + mock_vma->size = BIT_ULL(size); + + if (vm->allocate_va_range) { + if (i915_vma_alloc_pt_stash(vm, mock_vma)) + break; + + vm->allocate_va_range(vm, mock_vma, + addr, BIT_ULL(size)); + } mock_vma->pages = obj->mm.pages; mock_vma->node.size = BIT_ULL(size); @@ -316,6 +323,7 @@ static int lowlevel_hole(struct i915_address_space *vm, cleanup_freed_objects(vm->i915); } + i915_vma_free_pt_stash(vm, mock_vma); kfree(mock_vma); return 0; } @@ -1888,10 +1896,6 @@ static int igt_cs_tlb(void *arg) 0, vm->total - PAGE_SIZE, chunk_size, PAGE_SIZE); - err = vm->allocate_va_range(vm, offset, chunk_size); - if (err) - goto end; - memset32(result, STACK_MAGIC, PAGE_SIZE / sizeof(u32)); vma = i915_vma_instance(bbe, vm, NULL); @@ -1900,10 +1904,13 @@ static int igt_cs_tlb(void *arg) goto end; } + vma->size = chunk_size; err = vma->ops->set_pages(vma); if (err) goto end; + vm->allocate_va_range(vm, vma, offset, chunk_size); + /* Prime the TLB with the dummy pages */ for (i = 0; i < count; i++) { vma->node.start = offset + i * PAGE_SIZE; diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c index b173086411ef..779ddcba101c 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -38,14 +38,13 @@ static void mock_insert_entries(struct i915_address_space *vm, { } -static int mock_bind_ppgtt(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +static void mock_bind_ppgtt(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { GEM_BUG_ON(flags & I915_VMA_GLOBAL_BIND); set_bit(I915_VMA_LOCAL_BIND_BIT, __i915_vma_flags(vma)); - return 0; } static void mock_unbind_ppgtt(struct i915_address_space *vm, @@ -74,6 +73,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) ppgtt->vm.i915 = i915; ppgtt->vm.total = round_down(U64_MAX, PAGE_SIZE); ppgtt->vm.file = ERR_PTR(-ENODEV); + ppgtt->vm.dma = &i915->drm.pdev->dev; i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT); @@ -90,13 +90,11 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) return ppgtt; } -static int mock_bind_ggtt(struct i915_address_space *vm, - struct i915_vma *vma, - enum i915_cache_level cache_level, - u32 flags) +static void mock_bind_ggtt(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) { - atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags); - return 0; } static void mock_unbind_ggtt(struct i915_address_space *vm, -- 2.20.1 From patchwork at emeril.freedesktop.org Mon Jun 29 10:28:35 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 29 Jun 2020 10:28:35 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgVmFy?= =?utf-8?q?iable_renames?= In-Reply-To: <20200626234834.26864-1-lucas.demarchi@intel.com> References: <20200626234834.26864-1-lucas.demarchi@intel.com> Message-ID: <159342651546.746.14080228126994947768@emeril.freedesktop.org> == Series Details == Series: Variable renames URL : https://patchwork.freedesktop.org/series/78869/ State : success == Summary == CI Bug Log - changes from CI_DRM_8671 -> Patchwork_18033 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/index.html Known issues ------------ Here are the changes found in Patchwork_18033 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-tgl-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-byt-n2820: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-byt-n2820/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-byt-n2820/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-tgl-y/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-tgl-y/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-cml-s: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-cml-s/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-cml-s/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html * igt at vgem_basic@dmabuf-fence: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-tgl-y/igt at vgem_basic@dmabuf-fence.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-tgl-y/igt at vgem_basic@dmabuf-fence.html #### Possible fixes #### * igt at gem_render_linear_blits@basic: - fi-tgl-y: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-tgl-y/igt at gem_render_linear_blits@basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-tgl-y/igt at gem_render_linear_blits@basic.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at i915_selftest@live at blt: - fi-bsw-kefka: [INCOMPLETE][19] ([i915#392]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-bsw-kefka/igt at i915_selftest@live at blt.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-bsw-kefka/igt at i915_selftest@live at blt.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-kbl-x1275/igt at kms_busy@basic at flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [DMESG-WARN][23] ([i915#1982]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_flip@basic-flip-vs-wf_vblank at a-dsi1: - {fi-tgl-dsi}: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-wf_vblank at a-dsi1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-tgl-dsi/igt at kms_flip@basic-flip-vs-wf_vblank at a-dsi1.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [DMESG-WARN][27] ([i915#402]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +3 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_force_connector_basic@force-connector-state: - fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92]) -> [DMESG-WARN][32] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8671/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/fi-kbl-x1275/igt at kms_force_connector_basic@force-connector-state.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (46 -> 39) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8671 -> Patchwork_18033 CI-20190529: 20190529 CI_DRM_8671: d5765fff817aa868cbbb86ff3d3ef58d7e27251d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18033: 24d770b5b1a3f1ff36a3b93f78b059dd42a565ed @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 24d770b5b1a3 drm/i915/display: prefer dig_port to reference intel_digital_port 9284e42b0c14 drm/i915/display: remove alias to dig_port == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18033/index.html From maarten.lankhorst at linux.intel.com Mon Jun 29 10:40:43 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Mon, 29 Jun 2020 12:40:43 +0200 Subject: [Intel-gfx] [PATCH 06/26] drm/i915: Parse command buffer earlier in eb_relocate(slow) In-Reply-To: <6f313791-d0f7-465a-e4ab-63826ef70bf8@shipmail.org> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> <6f313791-d0f7-465a-e4ab-63826ef70bf8@shipmail.org> Message-ID: <cec259f8-170f-ad74-3eb1-f583cb01920f@linux.intel.com> Op 26-06-2020 om 16:41 schreef Thomas Hellstr?m (Intel): > > On 6/23/20 4:28 PM, Maarten Lankhorst wrote: >> We want to introduce backoff logic, but we need to lock the >> pool object as well for command parsing. Because of this, we >> will need backoff logic for the engine pool obj, move the batch >> validation up slightly to eb_lookup_vmas, and the actual command >> parsing in a separate function which can get called from execbuf >> relocation fast and slowpath. >> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> >> --- >> ? .../gpu/drm/i915/gem/i915_gem_execbuffer.c??? | 66 ++++++++++--------- >> ? 1 file changed, 36 insertions(+), 30 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> index f896b1a4b38a..7cb44915cfc7 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> @@ -290,6 +290,8 @@ struct i915_execbuffer { >> ????? struct eb_vma_array *array; >> ? }; >> ? +static int eb_parse(struct i915_execbuffer *eb); >> + >> ? static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) >> ? { >> ????? return intel_engine_requires_cmd_parser(eb->engine) || >> @@ -873,6 +875,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) >> ? ? static int eb_lookup_vmas(struct i915_execbuffer *eb) >> ? { >> +??? struct drm_i915_private *i915 = eb->i915; >> ????? unsigned int batch = eb_batch_index(eb); >> ????? unsigned int i; >> ????? int err = 0; >> @@ -886,18 +889,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) >> ????????? vma = eb_lookup_vma(eb, eb->exec[i].handle); >> ????????? if (IS_ERR(vma)) { >> ????????????? err = PTR_ERR(vma); >> -??????????? break; >> +??????????? goto err; >> ????????? } >> ? ????????? err = eb_validate_vma(eb, &eb->exec[i], vma); >> ????????? if (unlikely(err)) { >> ????????????? i915_vma_put(vma); >> -??????????? break; >> +??????????? goto err; >> ????????? } >> ? ????????? eb_add_vma(eb, i, batch, vma); >> ????? } >> ? +??? if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) { >> +??????? drm_dbg(&i915->drm, >> +??????????? "Attempting to use self-modifying batch buffer\n"); >> +??????? return -EINVAL; >> +??? } >> + >> +??? if (range_overflows_t(u64, >> +????????????????? eb->batch_start_offset, eb->batch_len, >> +????????????????? eb->batch->vma->size)) { >> +??????? drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); >> +??????? return -EINVAL; >> +??? } >> + >> +??? if (eb->batch_len == 0) >> +??????? eb->batch_len = eb->batch->vma->size - eb->batch_start_offset; >> + >> +??? return 0; >> + >> +err: >> ????? eb->vma[i].vma = NULL; >> ????? return err; >> ? } >> @@ -1809,7 +1831,7 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb) >> ????? return 0; >> ? } >> ? -static noinline int eb_relocate_slow(struct i915_execbuffer *eb) >> +static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) >> ? { >> ????? bool have_copy = false; >> ????? struct eb_vma *ev; >> @@ -1872,6 +1894,11 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) >> ????? if (err) >> ????????? goto err; >> ? +??? /* as last step, parse the command buffer */ >> +??? err = eb_parse(eb); >> +??? if (err) >> +??????? goto err; >> + >> ????? /* >> ?????? * Leave the user relocations as are, this is the painfully slow path, >> ?????? * and we want to avoid the complication of dropping the lock whilst >> @@ -1904,7 +1931,7 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) >> ????? return err; >> ? } >> ? -static int eb_relocate(struct i915_execbuffer *eb) >> +static int eb_relocate_parse(struct i915_execbuffer *eb) >> ? { >> ????? int err; >> ? @@ -1932,7 +1959,7 @@ static int eb_relocate(struct i915_execbuffer *eb) >> ????????????? return eb_relocate_slow(eb); >> ????? } >> ? -??? return 0; >> +??? return eb_parse(eb); >> ? } >> ? ? static int eb_move_to_gpu(struct i915_execbuffer *eb) >> @@ -2870,7 +2897,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, >> ????? if (unlikely(err)) >> ????????? goto err_context; >> ? -??? err = eb_relocate(&eb); >> +??? err = eb_relocate_parse(&eb); >> ????? if (err) { >> ????????? /* >> ?????????? * If the user expects the execobject.offset and >> @@ -2883,33 +2910,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, >> ????????? goto err_vma; >> ????? } >> ? -??? if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) { >> -??????? drm_dbg(&i915->drm, >> -??????????? "Attempting to use self-modifying batch buffer\n"); >> -??????? err = -EINVAL; >> -??????? goto err_vma; >> -??? } >> - >> -??? if (range_overflows_t(u64, >> -????????????????? eb.batch_start_offset, eb.batch_len, >> -????????????????? eb.batch->vma->size)) { >> -??????? drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); >> -??????? err = -EINVAL; >> -??????? goto err_vma; >> -??? } >> - >> -??? if (eb.batch_len == 0) >> -??????? eb.batch_len = eb.batch->vma->size - eb.batch_start_offset; >> - >> -??? err = eb_parse(&eb); >> -??? if (err) >> -??????? goto err_vma; >> - >> ????? /* >> ?????? * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure >> ?????? * batch" bit. Hence we need to pin secure batches into the global gtt. >> ?????? * hsw should have this fixed, but bdw mucks it up again. */ >> -??? batch = eb.batch->vma; >> ????? if (eb.batch_flags & I915_DISPATCH_SECURE) { >> ????????? struct i915_vma *vma; >> ? @@ -2923,13 +2927,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, >> ?????????? *?? fitting due to fragmentation. >> ?????????? * So this is actually safe. >> ?????????? */ >> -??????? vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); >> +??????? vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); >> ????????? if (IS_ERR(vma)) { >> ????????????? err = PTR_ERR(vma); >> ????????????? goto err_parse; >> ????????? } >> ? ????????? batch = vma; >> +??? } else { >> +??????? batch = eb.batch->vma; >> ????? } >> ? > > Hmm, it's late friday afternoon so that might be the cause, but I fail to see what the above hunk is trying to achieve? Execbuf parsing may create a shadow object which also needs to be locked, we do this inside eb_relocate() to ensure the normal rules for w/w handling can be used for eb parsing as well. :) ~Maarten From chris at chris-wilson.co.uk Mon Jun 29 10:50:57 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 11:50:57 +0100 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/gem: Move obj->lut_list under its own lock In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <159342785711.14343.17694396689978084998@build.alporthouse.com> Quoting Chris Wilson (2020-06-29 11:12:51) > @@ -108,7 +109,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) > struct i915_lut_handle *lut, *ln; > LIST_HEAD(close); > > - i915_gem_object_lock(obj); > + spin_lock(&obj->lut_lock); > list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { > struct i915_gem_context *ctx = lut->ctx; > > @@ -118,7 +119,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) > i915_gem_context_get(ctx); > list_move(&lut->obj_link, &close); > } > - i915_gem_object_unlock(obj); > + spin_unlock(&obj->lut_lock); This is only real worry, iterating under the spinlock. If we worry, we can do something like + struct i915_lut_handle bookmark = {}; LIST_HEAD(close); spin_lock(&obj->lut_lock); list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { struct i915_gem_context *ctx = lut->ctx; - if (ctx->file_priv != fpriv) - continue; + if (ctx && ctx->file_priv == fpriv) { + i915_gem_context_get(ctx); + list_move(&lut->obj_link, &close); + } - i915_gem_context_get(ctx); - list_move(&lut->obj_link, &close); + if (ln != &obj->lut_list) { + list_add(&bookmark->obj_link, &ln->obj_link); + if (cond_resched_lock(&obj->lut_lock)) + list_safe_reset_next(&bookmark, ln, obj_link); + list_del_entry(&bookmark->obj_link); + } } Might as well worry. -Chris From mpe at ellerman.id.au Mon Jun 29 10:57:07 2020 From: mpe at ellerman.id.au (Michael Ellerman) Date: Mon, 29 Jun 2020 20:57:07 +1000 Subject: [Intel-gfx] [PATCH 13/13] powerpc/dma: Remove dev->archdata.iommu_domain In-Reply-To: <20200625130836.1916-14-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> <20200625130836.1916-14-joro@8bytes.org> Message-ID: <87bll287i4.fsf@mpe.ellerman.id.au> Joerg Roedel <joro at 8bytes.org> writes: > From: Joerg Roedel <jroedel at suse.de> > > There are no users left, so remove the pointer and save some memory. > > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- > arch/powerpc/include/asm/device.h | 3 --- > 1 file changed, 3 deletions(-) It's a little hard to confirm there are no users left just with grep, but I think you've got them all, and the compiler should tell us if you've missed any. Acked-by: Michael Ellerman <mpe at ellerman.id.au> (powerpc) cheers > diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h > index 266542769e4b..1bc595213338 100644 > --- a/arch/powerpc/include/asm/device.h > +++ b/arch/powerpc/include/asm/device.h > @@ -34,9 +34,6 @@ struct dev_archdata { > struct iommu_table *iommu_table_base; > #endif > > -#ifdef CONFIG_IOMMU_API > - void *iommu_domain; > -#endif > #ifdef CONFIG_PPC64 > struct pci_dn *pci_data; > #endif > -- > 2.27.0 From thomas_os at shipmail.org Mon Jun 29 11:15:29 2020 From: thomas_os at shipmail.org (=?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?=) Date: Mon, 29 Jun 2020 13:15:29 +0200 Subject: [Intel-gfx] [PATCH 06/26] drm/i915: Parse command buffer earlier in eb_relocate(slow) In-Reply-To: <cec259f8-170f-ad74-3eb1-f583cb01920f@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> <6f313791-d0f7-465a-e4ab-63826ef70bf8@shipmail.org> <cec259f8-170f-ad74-3eb1-f583cb01920f@linux.intel.com> Message-ID: <11cd7a6a-af85-e68f-5936-0a8d4157da91@shipmail.org> Hi, On 6/29/20 12:40 PM, Maarten Lankhorst wrote: > >>> ????? /* >>> ?????? * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure >>> ?????? * batch" bit. Hence we need to pin secure batches into the global gtt. >>> ?????? * hsw should have this fixed, but bdw mucks it up again. */ >>> -??? batch = eb.batch->vma; >>> ????? if (eb.batch_flags & I915_DISPATCH_SECURE) { >>> ????????? struct i915_vma *vma; >>> ? @@ -2923,13 +2927,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, >>> ?????????? *?? fitting due to fragmentation. >>> ?????????? * So this is actually safe. >>> ?????????? */ >>> -??????? vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); >>> +??????? vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); >>> ????????? if (IS_ERR(vma)) { >>> ????????????? err = PTR_ERR(vma); >>> ????????????? goto err_parse; >>> ????????? } >>> ? ????????? batch = vma; >>> +??? } else { >>> +??????? batch = eb.batch->vma; >>> ????? } >>> >> Hmm, it's late friday afternoon so that might be the cause, but I fail to see what the above hunk is trying to achieve? > > Execbuf parsing may create a shadow object which also needs to be locked, we do this inside eb_relocate() to ensure the normal rules for w/w handling can be used for eb parsing as well. :) > > ~Maarten I meant the changed assignment of the batch variable? /Thomas From maarten.lankhorst at linux.intel.com Mon Jun 29 11:18:26 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Mon, 29 Jun 2020 13:18:26 +0200 Subject: [Intel-gfx] [PATCH 06/26] drm/i915: Parse command buffer earlier in eb_relocate(slow) In-Reply-To: <11cd7a6a-af85-e68f-5936-0a8d4157da91@shipmail.org> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> <6f313791-d0f7-465a-e4ab-63826ef70bf8@shipmail.org> <cec259f8-170f-ad74-3eb1-f583cb01920f@linux.intel.com> <11cd7a6a-af85-e68f-5936-0a8d4157da91@shipmail.org> Message-ID: <ff373032-c935-6a8b-a65d-feeb9e40af54@linux.intel.com> Op 29-06-2020 om 13:15 schreef Thomas Hellstr?m (Intel): > Hi, > > On 6/29/20 12:40 PM, Maarten Lankhorst wrote: >> >>>> ?????? /* >>>> ??????? * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure >>>> ??????? * batch" bit. Hence we need to pin secure batches into the global gtt. >>>> ??????? * hsw should have this fixed, but bdw mucks it up again. */ >>>> -??? batch = eb.batch->vma; >>>> ?????? if (eb.batch_flags & I915_DISPATCH_SECURE) { >>>> ?????????? struct i915_vma *vma; >>>> ?? @@ -2923,13 +2927,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, >>>> ??????????? *?? fitting due to fragmentation. >>>> ??????????? * So this is actually safe. >>>> ??????????? */ >>>> -??????? vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); >>>> +??????? vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); >>>> ?????????? if (IS_ERR(vma)) { >>>> ?????????????? err = PTR_ERR(vma); >>>> ?????????????? goto err_parse; >>>> ?????????? } >>>> ?? ????????? batch = vma; >>>> +??? } else { >>>> +??????? batch = eb.batch->vma; >>>> ?????? } >>>> ?? >>> Hmm, it's late friday afternoon so that might be the cause, but I fail to see what the above hunk is trying to achieve? >> >> Execbuf parsing may create a shadow object which also needs to be locked, we do this inside eb_relocate() to ensure the normal rules for w/w handling can be used for eb parsing as well. :) >> >> ~Maarten > > I meant the changed assignment of the batch variable? > > /Thomas > > Nothing, still ends up being the same. :) Was looking at changing that pin as well, didn't get around to it yet. ~Maarten From chris at chris-wilson.co.uk Mon Jun 29 11:22:09 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 12:22:09 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its own lock In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <20200629112209.10423-1-chris@chris-wilson.co.uk> The obj->lut_list is traversed when the object is closed as the file table is destroyed during process termination. As this occurs before we kill any outstanding context if, due to some bug or another, the closure is blocked, then we fail to shootdown any inflight operations potentially leaving the GPU spinning forever. As we only need to guard the list against concurrent closures and insertions, the hold is short and merits being treated as a simple spinlock. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++---- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/gem/i915_gem_object.c | 21 +++++++++++++------ .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 + 4 files changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 5c13809dc3c8..6675447a47b9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -112,8 +112,7 @@ static void lut_close(struct i915_gem_context *ctx) if (!kref_get_unless_zero(&obj->base.refcount)) continue; - rcu_read_unlock(); - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); list_for_each_entry(lut, &obj->lut_list, obj_link) { if (lut->ctx != ctx) continue; @@ -124,8 +123,7 @@ static void lut_close(struct i915_gem_context *ctx) list_del(&lut->obj_link); break; } - i915_gem_object_unlock(obj); - rcu_read_lock(); + spin_unlock(&obj->lut_lock); if (&lut->obj_link != &obj->lut_list) { i915_lut_handle_free(lut); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..b4862afaaf28 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -789,14 +789,14 @@ static int __eb_add_lut(struct i915_execbuffer *eb, if (err == 0) { /* And nor has this handle */ struct drm_i915_gem_object *obj = vma->obj; - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); if (idr_find(&eb->file->object_idr, handle) == obj) { list_add(&lut->obj_link, &obj->lut_list); } else { radix_tree_delete(&ctx->handles_vma, handle); err = -ENOENT; } - i915_gem_object_unlock(obj); + spin_unlock(&obj->lut_lock); } mutex_unlock(&ctx->mutex); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index b6ec5b50d93b..3f47fa4784ac 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -61,6 +61,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, INIT_LIST_HEAD(&obj->mm.link); INIT_LIST_HEAD(&obj->lut_list); + spin_lock_init(&obj->lut_lock); spin_lock_init(&obj->mmo.lock); obj->mmo.offsets = RB_ROOT; @@ -104,21 +105,29 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) { struct drm_i915_gem_object *obj = to_intel_bo(gem); struct drm_i915_file_private *fpriv = file->driver_priv; + struct i915_lut_handle bookmark = {}; struct i915_mmap_offset *mmo, *mn; struct i915_lut_handle *lut, *ln; LIST_HEAD(close); - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { struct i915_gem_context *ctx = lut->ctx; - if (ctx->file_priv != fpriv) - continue; + if (ctx && ctx->file_priv == fpriv) { + i915_gem_context_get(ctx); + list_move(&lut->obj_link, &close); + } - i915_gem_context_get(ctx); - list_move(&lut->obj_link, &close); + /* Break long locks, and carefully continue on from this spot */ + if (&ln->obj_link != &obj->lut_list) { + list_add(&bookmark.obj_link, &ln->obj_link); + if (cond_resched_lock(&obj->lut_lock)) + list_safe_reset_next(&bookmark, ln, obj_link); + __list_del_entry(&bookmark.obj_link); + } } - i915_gem_object_unlock(obj); + spin_unlock(&obj->lut_lock); spin_lock(&obj->mmo.lock); rbtree_postorder_for_each_entry_safe(mmo, mn, &obj->mmo.offsets, offset) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index b1f82a11aef2..5335f799b548 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -121,6 +121,7 @@ struct drm_i915_gem_object { * this translation from object to context->handles_vma. */ struct list_head lut_list; + spinlock_t lut_lock; /* guards lut_list */ /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; -- 2.20.1 From chris at chris-wilson.co.uk Mon Jun 29 11:36:16 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Mon, 29 Jun 2020 12:36:16 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its own lock In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <20200629113616.10618-1-chris@chris-wilson.co.uk> The obj->lut_list is traversed when the object is closed as the file table is destroyed during process termination. As this occurs before we kill any outstanding context if, due to some bug or another, the closure is blocked, then we fail to shootdown any inflight operations potentially leaving the GPU spinning forever. As we only need to guard the list against concurrent closures and insertions, the hold is short and merits being treated as a simple spinlock. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++---- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/gem/i915_gem_object.c | 21 +++++++++++++------ .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 + 4 files changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index 5c13809dc3c8..6675447a47b9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -112,8 +112,7 @@ static void lut_close(struct i915_gem_context *ctx) if (!kref_get_unless_zero(&obj->base.refcount)) continue; - rcu_read_unlock(); - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); list_for_each_entry(lut, &obj->lut_list, obj_link) { if (lut->ctx != ctx) continue; @@ -124,8 +123,7 @@ static void lut_close(struct i915_gem_context *ctx) list_del(&lut->obj_link); break; } - i915_gem_object_unlock(obj); - rcu_read_lock(); + spin_unlock(&obj->lut_lock); if (&lut->obj_link != &obj->lut_list) { i915_lut_handle_free(lut); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index c38ab51e82f0..b4862afaaf28 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -789,14 +789,14 @@ static int __eb_add_lut(struct i915_execbuffer *eb, if (err == 0) { /* And nor has this handle */ struct drm_i915_gem_object *obj = vma->obj; - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); if (idr_find(&eb->file->object_idr, handle) == obj) { list_add(&lut->obj_link, &obj->lut_list); } else { radix_tree_delete(&ctx->handles_vma, handle); err = -ENOENT; } - i915_gem_object_unlock(obj); + spin_unlock(&obj->lut_lock); } mutex_unlock(&ctx->mutex); } diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index b6ec5b50d93b..6b69191c5543 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -61,6 +61,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj, INIT_LIST_HEAD(&obj->mm.link); INIT_LIST_HEAD(&obj->lut_list); + spin_lock_init(&obj->lut_lock); spin_lock_init(&obj->mmo.lock); obj->mmo.offsets = RB_ROOT; @@ -104,21 +105,29 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) { struct drm_i915_gem_object *obj = to_intel_bo(gem); struct drm_i915_file_private *fpriv = file->driver_priv; + struct i915_lut_handle bookmark = {}; struct i915_mmap_offset *mmo, *mn; struct i915_lut_handle *lut, *ln; LIST_HEAD(close); - i915_gem_object_lock(obj); + spin_lock(&obj->lut_lock); list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { struct i915_gem_context *ctx = lut->ctx; - if (ctx->file_priv != fpriv) - continue; + if (ctx && ctx->file_priv == fpriv) { + i915_gem_context_get(ctx); + list_move(&lut->obj_link, &close); + } - i915_gem_context_get(ctx); - list_move(&lut->obj_link, &close); + /* Break long locks, and carefully continue on from this spot */ + if (&ln->obj_link != &obj->lut_list) { + list_add_tail(&bookmark.obj_link, &ln->obj_link); + if (cond_resched_lock(&obj->lut_lock)) + list_safe_reset_next(&bookmark, ln, obj_link); + __list_del_entry(&bookmark.obj_link); + } } - i915_gem_object_unlock(obj); + spin_unlock(&obj->lut_lock); spin_lock(&obj->mmo.lock); rbtree_postorder_for_each_entry_safe(mmo, mn, &obj->mmo.offsets, offset) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h index b1f82a11aef2..5335f799b548 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h @@ -121,6 +121,7 @@ struct drm_i915_gem_object { * this translation from object to context->handles_vma. */ struct list_head lut_list; + spinlock_t lut_lock; /* guards lut_list */ /** Stolen memory for this object, instead of being backed by shmem. */ struct drm_mm_node *stolen; -- 2.20.1 From tvrtko.ursulin at linux.intel.com Mon Jun 29 12:07:33 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 29 Jun 2020 13:07:33 +0100 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> Message-ID: <fb593721-4b84-bdfd-4385-4bb73512a5f3@linux.intel.com> On 23/06/2020 15:28, Maarten Lankhorst wrote: > i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory > eviction. We don't use it yet, but lets start adding the definition > first. > > To use it, we have to pass a non-NULL ww to gem_object_lock, and don't > unlock directly. It is done in i915_gem_ww_ctx_fini. > > Changes since v1: > - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) Do you envisage, by the end of refactoring (including obj->mm.lock) majority of i915_gem_object_lock() calls sites will be passing a context? I am thinking whether it would be easier, for maintaining the series, to keep i915_gem_object_lock() as is, and add new i915_gem_object_lock_ww to be used at select places only. Interestingly I think later in the series I will have an opposite feeling regarding some other entry points. So I might be wrong, or just not have the full picture at this point. :) Regards, Tvrtko > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- > .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- > .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- > .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- > .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- > .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- > .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- > drivers/gpu/drm/i915/i915_gem.h | 11 ++++ > drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ > drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- > .../drm/i915/selftests/intel_memory_region.c | 2 +- > 24 files changed, 173 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 7457813ef273..e909ccc37a54 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, > > void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) > { > - i915_gem_object_lock(vma->obj); > + i915_gem_object_lock(vma->obj, NULL); > if (flags & PLANE_HAS_FENCE) > i915_vma_unpin_fence(vma); > i915_gem_object_unpin_from_display_plane(vma); > @@ -17112,7 +17112,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, > if (!intel_fb->frontbuffer) > return -ENOMEM; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > tiling = i915_gem_object_get_tiling(obj); > stride = i915_gem_object_get_stride(obj); > i915_gem_object_unlock(obj); > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c > index d3a86a4d5c04..c182091c00ff 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c > @@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, > dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0); > i915_sw_fence_init(&work->wait, clear_pages_work_notify); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_sw_fence_await_reservation(&work->wait, > obj->base.resv, NULL, true, 0, > I915_FENCE_GFP); > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c > index 30c229fcb404..a996583640ee 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > @@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx) > continue; > > rcu_read_unlock(); > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > list_for_each_entry(lut, &obj->lut_list, obj_link) { > if (lut->ctx != ctx) > continue; > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > index 2679380159fc..27fddc22a7c6 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > @@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_dire > if (err) > return err; > > - err = i915_gem_object_lock_interruptible(obj); > + err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out; > > @@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direct > if (err) > return err; > > - err = i915_gem_object_lock_interruptible(obj); > + err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out; > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > index 7f76fc68f498..c0acfc97fae3 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > @@ -32,7 +32,7 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) > if (!i915_gem_object_is_framebuffer(obj)) > return; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > __i915_gem_object_flush_for_display(obj); > i915_gem_object_unlock(obj); > } > @@ -197,7 +197,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, > if (ret) > return ret; > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > @@ -536,7 +536,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, > if (err) > goto out; > > - err = i915_gem_object_lock_interruptible(obj); > + err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out_unpin; > > @@ -576,7 +576,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > @@ -630,7 +630,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 2b4c210638c1..391d22051b20 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -813,7 +813,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > if (err == 0) { /* And nor has this handle */ > struct drm_i915_gem_object *obj = vma->obj; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > if (idr_find(&eb->file->object_idr, handle) == obj) { > list_add(&lut->obj_link, &obj->lut_list); > } else { > @@ -1083,7 +1083,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, > if (use_cpu_reloc(cache, obj)) > return NULL; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c > index b6ec5b50d93b..b59e2d40c347 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c > @@ -108,7 +108,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) > struct i915_lut_handle *lut, *ln; > LIST_HEAD(close); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { > struct i915_gem_context *ctx = lut->ctx; > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h > index 2faa481cc18f..5103067269b0 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h > @@ -110,20 +110,44 @@ i915_gem_object_put(struct drm_i915_gem_object *obj) > > #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv) > > -static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj) > +static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj, > + struct i915_gem_ww_ctx *ww, > + bool intr) > { > - dma_resv_lock(obj->base.resv, NULL); > + int ret; > + > + if (intr) > + ret = dma_resv_lock_interruptible(obj->base.resv, ww ? &ww->ctx : NULL); > + else > + ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL); > + > + if (!ret && ww) > + list_add_tail(&obj->obj_link, &ww->obj_list); > + if (ret == -EALREADY) > + ret = 0; > + > + if (ret == -EDEADLK) > + ww->contended = obj; > + > + return ret; > } > > -static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) > +static inline int i915_gem_object_lock(struct drm_i915_gem_object *obj, > + struct i915_gem_ww_ctx *ww) > { > - return dma_resv_trylock(obj->base.resv); > + return __i915_gem_object_lock(obj, ww, ww && ww->intr); > } > > -static inline int > -i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj) > +static inline int i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj, > + struct i915_gem_ww_ctx *ww) > { > - return dma_resv_lock_interruptible(obj->base.resv, NULL); > + WARN_ON(ww && !ww->intr); > + return __i915_gem_object_lock(obj, ww, true); > +} > + > +static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) > +{ > + return dma_resv_trylock(obj->base.resv); > } > > static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj) > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > index b1f82a11aef2..3740c0080e38 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > @@ -122,6 +122,15 @@ struct drm_i915_gem_object { > */ > struct list_head lut_list; > > + /** > + * @obj_link: Link into @i915_gem_ww_ctx.obj_list > + * > + * When we lock this object through i915_gem_object_lock() with a > + * context, we add it to the list to ensure we can unlock everything > + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. > + */ > + struct list_head obj_link; > + > /** Stolen memory for this object, instead of being backed by shmem. */ > struct drm_mm_node *stolen; > union { > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c > index 3d215164dd5a..40d3e40500fa 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c > @@ -84,7 +84,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) > > spin_unlock_irqrestore(&i915->mm.obj_lock, flags); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > drm_WARN_ON(&i915->drm, > i915_gem_object_set_to_gtt_domain(obj, false)); > i915_gem_object_unlock(obj); > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > index 0158e49bf9bb..65fbf29c4852 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > @@ -249,7 +249,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, > * whilst executing a fenced command for an untiled object. > */ > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > if (i915_gem_object_is_framebuffer(obj)) { > i915_gem_object_unlock(obj); > return -EBUSY; > diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > index 8291ede6902c..eb2011ccb92b 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > @@ -947,7 +947,7 @@ static int gpu_write(struct intel_context *ce, > { > int err; > > - i915_gem_object_lock(vma->obj); > + i915_gem_object_lock(vma->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(vma->obj, true); > i915_gem_object_unlock(vma->obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > index 299c29e9ad86..4e36d4897ea6 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > @@ -75,7 +75,7 @@ static int __igt_client_fill(struct intel_engine_cs *engine) > if (err) > goto err_unpin; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > index 87d7d8aa080f..1de2959b153c 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > @@ -82,7 +82,7 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v) > u32 __iomem *map; > int err = 0; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -115,7 +115,7 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) > u32 __iomem *map; > int err = 0; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -147,7 +147,7 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v) > u32 *map; > int err; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_wc_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -170,7 +170,7 @@ static int wc_get(struct context *ctx, unsigned long offset, u32 *v) > u32 *map; > int err; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_wc_domain(ctx->obj, false); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -193,7 +193,7 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) > u32 *cs; > int err; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > index b81978890641..438c15ef2184 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > @@ -950,7 +950,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, > if (IS_ERR(vma)) > return PTR_ERR(vma); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) > @@ -1706,7 +1706,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, > > i915_request_add(rq); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > index 9c7402ce5bf9..9fb95a45bcad 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > @@ -103,7 +103,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj, > GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); > GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { > @@ -188,7 +188,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj, > GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); > GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c > index 34932871b3a5..a94243dc4c5c 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c > @@ -44,7 +44,7 @@ static int mock_phys_object(void *arg) > } > > /* Make the object dirty so that put_pages must do copy back the data */ > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > index febc9e6692ba..61a0532d0f3d 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > @@ -214,7 +214,7 @@ static int check_whitelist(struct i915_gem_context *ctx, > return PTR_ERR(results); > > err = 0; > - i915_gem_object_lock(results); > + i915_gem_object_lock(results, NULL); > intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */ > err = i915_gem_object_set_to_cpu_domain(results, false); > i915_gem_object_unlock(results); > diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c > index f1940939260a..943c8d232703 100644 > --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c > +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c > @@ -2982,7 +2982,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) > goto put_obj; > } > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > ret = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (ret) { > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 9aa3066cb75d..1e06752835e5 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -420,7 +420,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, > GEM_BUG_ON(!drm_mm_node_allocated(&node)); > } > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > goto out_unpin; > > @@ -619,7 +619,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, > GEM_BUG_ON(!drm_mm_node_allocated(&node)); > } > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > goto out_unpin; > > @@ -1290,7 +1290,7 @@ int i915_gem_freeze_late(struct drm_i915_private *i915) > i915_gem_drain_freed_objects(i915); > > list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) { > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > drm_WARN_ON(&i915->drm, > i915_gem_object_set_to_cpu_domain(obj, true)); > i915_gem_object_unlock(obj); > @@ -1344,6 +1344,52 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) > return ret; > } > > +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr) > +{ > + ww_acquire_init(&ww->ctx, &reservation_ww_class); > + INIT_LIST_HEAD(&ww->obj_list); > + ww->intr = intr; > + ww->contended = NULL; > +} > + > +static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) > +{ > + struct drm_i915_gem_object *obj; > + > + while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { > + list_del(&obj->obj_link); > + i915_gem_object_unlock(obj); > + } > +} > + > +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) > +{ > + i915_gem_ww_ctx_unlock_all(ww); > + WARN_ON(ww->contended); > + ww_acquire_fini(&ww->ctx); > +} > + > +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww) > +{ > + int ret = 0; > + > + if (WARN_ON(!ww->contended)) > + return -EINVAL; > + > + i915_gem_ww_ctx_unlock_all(ww); > + if (ww->intr) > + ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx); > + else > + dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx); > + > + if (!ret) > + list_add_tail(&ww->contended->obj_link, &ww->obj_list); > + > + ww->contended = NULL; > + > + return ret; > +} > + > #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > #include "selftests/mock_gem_device.c" > #include "selftests/i915_gem.c" > diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h > index 1753c84d6c0d..988755dbf4be 100644 > --- a/drivers/gpu/drm/i915/i915_gem.h > +++ b/drivers/gpu/drm/i915/i915_gem.h > @@ -116,4 +116,15 @@ static inline bool __tasklet_is_scheduled(struct tasklet_struct *t) > return test_bit(TASKLET_STATE_SCHED, &t->state); > } > > +struct i915_gem_ww_ctx { > + struct ww_acquire_ctx ctx; > + struct list_head obj_list; > + bool intr; > + struct drm_i915_gem_object *contended; > +}; > + > +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); > +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); > +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx); > + > #endif /* __I915_GEM_H__ */ > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c > index 88d400b9df88..23a6132c5f4e 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c > @@ -199,11 +199,52 @@ static int igt_gem_hibernate(void *arg) > return err; > } > > +static int igt_gem_ww_ctx(void *arg) > +{ > + struct drm_i915_private *i915 = arg; > + struct drm_i915_gem_object *obj, *obj2; > + struct i915_gem_ww_ctx ww; > + int err = 0; > + > + obj = i915_gem_object_create_internal(i915, PAGE_SIZE); > + if (IS_ERR(obj)) > + return PTR_ERR(obj); > + > + obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE); > + if (IS_ERR(obj)) { > + err = PTR_ERR(obj); > + goto put1; > + } > + > + i915_gem_ww_ctx_init(&ww, true); > +retry: > + /* Lock the objects, twice for good measure (-EALREADY handling) */ > + err = i915_gem_object_lock(obj, &ww); > + if (!err) > + err = i915_gem_object_lock_interruptible(obj, &ww); > + if (!err) > + err = i915_gem_object_lock_interruptible(obj2, &ww); > + if (!err) > + err = i915_gem_object_lock(obj2, &ww); > + > + if (err == -EDEADLK) { > + err = i915_gem_ww_ctx_backoff(&ww); > + if (!err) > + goto retry; > + } > + i915_gem_ww_ctx_fini(&ww); > + i915_gem_object_put(obj2); > +put1: > + i915_gem_object_put(obj); > + return err; > +} > + > int i915_gem_live_selftests(struct drm_i915_private *i915) > { > static const struct i915_subtest tests[] = { > SUBTEST(igt_gem_suspend), > SUBTEST(igt_gem_hibernate), > + SUBTEST(igt_gem_ww_ctx), > }; > > if (intel_gt_is_wedged(&i915->gt)) > diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c > index af89c7fc8f59..88c5e9acb84c 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_vma.c > +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c > @@ -892,7 +892,7 @@ static int igt_vma_remapped_gtt(void *arg) > unsigned int x, y; > int err; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > index 6e80d99048e4..957a7a52def7 100644 > --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c > +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > @@ -509,7 +509,7 @@ static int igt_lmem_write_cpu(void *arg) > if (err) > goto out_unpin; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_wc_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) > From tvrtko.ursulin at linux.intel.com Mon Jun 29 12:32:16 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 29 Jun 2020 13:32:16 +0100 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> Message-ID: <c03481f1-92c2-24ad-b56e-a92fbb70f9fe@linux.intel.com> On 23/06/2020 15:28, Maarten Lankhorst wrote: > i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory > eviction. We don't use it yet, but lets start adding the definition > first. > > To use it, we have to pass a non-NULL ww to gem_object_lock, and don't > unlock directly. It is done in i915_gem_ww_ctx_fini. > > Changes since v1: > - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 4 +- > .../gpu/drm/i915/gem/i915_gem_client_blt.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 10 ++-- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 +- > drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_object.h | 38 +++++++++++--- > .../gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++ > drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 2 +- > .../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +- > .../i915/gem/selftests/i915_gem_client_blt.c | 2 +- > .../i915/gem/selftests/i915_gem_coherency.c | 10 ++-- > .../drm/i915/gem/selftests/i915_gem_context.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_mman.c | 4 +- > .../drm/i915/gem/selftests/i915_gem_phys.c | 2 +- > .../gpu/drm/i915/gt/selftest_workarounds.c | 2 +- > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_gem.c | 52 +++++++++++++++++-- > drivers/gpu/drm/i915/i915_gem.h | 11 ++++ > drivers/gpu/drm/i915/selftests/i915_gem.c | 41 +++++++++++++++ > drivers/gpu/drm/i915/selftests/i915_vma.c | 2 +- > .../drm/i915/selftests/intel_memory_region.c | 2 +- > 24 files changed, 173 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 7457813ef273..e909ccc37a54 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, > > void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) > { > - i915_gem_object_lock(vma->obj); > + i915_gem_object_lock(vma->obj, NULL); > if (flags & PLANE_HAS_FENCE) > i915_vma_unpin_fence(vma); > i915_gem_object_unpin_from_display_plane(vma); > @@ -17112,7 +17112,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, > if (!intel_fb->frontbuffer) > return -ENOMEM; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > tiling = i915_gem_object_get_tiling(obj); > stride = i915_gem_object_get_stride(obj); > i915_gem_object_unlock(obj); > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c > index d3a86a4d5c04..c182091c00ff 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c > @@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, > dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0); > i915_sw_fence_init(&work->wait, clear_pages_work_notify); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_sw_fence_await_reservation(&work->wait, > obj->base.resv, NULL, true, 0, > I915_FENCE_GFP); > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c > index 30c229fcb404..a996583640ee 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > @@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx) > continue; > > rcu_read_unlock(); > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > list_for_each_entry(lut, &obj->lut_list, obj_link) { > if (lut->ctx != ctx) > continue; > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > index 2679380159fc..27fddc22a7c6 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c > @@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_dire > if (err) > return err; > > - err = i915_gem_object_lock_interruptible(obj); > + err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out; > > @@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direct > if (err) > return err; > > - err = i915_gem_object_lock_interruptible(obj); > + err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out; > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > index 7f76fc68f498..c0acfc97fae3 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > @@ -32,7 +32,7 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) > if (!i915_gem_object_is_framebuffer(obj)) > return; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > __i915_gem_object_flush_for_display(obj); > i915_gem_object_unlock(obj); > } > @@ -197,7 +197,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, > if (ret) > return ret; > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > @@ -536,7 +536,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, > if (err) > goto out; > > - err = i915_gem_object_lock_interruptible(obj); > + err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > goto out_unpin; > > @@ -576,7 +576,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > @@ -630,7 +630,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 2b4c210638c1..391d22051b20 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -813,7 +813,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > if (err == 0) { /* And nor has this handle */ > struct drm_i915_gem_object *obj = vma->obj; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > if (idr_find(&eb->file->object_idr, handle) == obj) { > list_add(&lut->obj_link, &obj->lut_list); > } else { > @@ -1083,7 +1083,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, > if (use_cpu_reloc(cache, obj)) > return NULL; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c > index b6ec5b50d93b..b59e2d40c347 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c > @@ -108,7 +108,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) > struct i915_lut_handle *lut, *ln; > LIST_HEAD(close); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { > struct i915_gem_context *ctx = lut->ctx; > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h > index 2faa481cc18f..5103067269b0 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h > @@ -110,20 +110,44 @@ i915_gem_object_put(struct drm_i915_gem_object *obj) > > #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv) > > -static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj) > +static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj, > + struct i915_gem_ww_ctx *ww, > + bool intr) > { > - dma_resv_lock(obj->base.resv, NULL); > + int ret; > + > + if (intr) > + ret = dma_resv_lock_interruptible(obj->base.resv, ww ? &ww->ctx : NULL); > + else > + ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL); > + > + if (!ret && ww) > + list_add_tail(&obj->obj_link, &ww->obj_list); > + if (ret == -EALREADY) > + ret = 0; > + > + if (ret == -EDEADLK) > + ww->contended = obj; > + > + return ret; Feels a bit on the large side for inline now, no? Quite a few conditionals. Or you are counting on compiler optimisation because ww and intr are passed in as mostly const? > } > > -static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) > +static inline int i915_gem_object_lock(struct drm_i915_gem_object *obj, > + struct i915_gem_ww_ctx *ww) > { > - return dma_resv_trylock(obj->base.resv); > + return __i915_gem_object_lock(obj, ww, ww && ww->intr); > } > > -static inline int > -i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj) > +static inline int i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj, > + struct i915_gem_ww_ctx *ww) > { > - return dma_resv_lock_interruptible(obj->base.resv, NULL); > + WARN_ON(ww && !ww->intr); > + return __i915_gem_object_lock(obj, ww, true); I see that ww->intr is set at ctx init time. At what times it is expected that the individual lock calls would override that? > +} > + > +static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) > +{ > + return dma_resv_trylock(obj->base.resv); > } > > static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj) > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > index b1f82a11aef2..3740c0080e38 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > @@ -122,6 +122,15 @@ struct drm_i915_gem_object { > */ > struct list_head lut_list; > > + /** > + * @obj_link: Link into @i915_gem_ww_ctx.obj_list > + * > + * When we lock this object through i915_gem_object_lock() with a > + * context, we add it to the list to ensure we can unlock everything > + * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. > + */ > + struct list_head obj_link; > + > /** Stolen memory for this object, instead of being backed by shmem. */ > struct drm_mm_node *stolen; > union { > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c > index 3d215164dd5a..40d3e40500fa 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c > @@ -84,7 +84,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) > > spin_unlock_irqrestore(&i915->mm.obj_lock, flags); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > drm_WARN_ON(&i915->drm, > i915_gem_object_set_to_gtt_domain(obj, false)); > i915_gem_object_unlock(obj); > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > index 0158e49bf9bb..65fbf29c4852 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > @@ -249,7 +249,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, > * whilst executing a fenced command for an untiled object. > */ > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > if (i915_gem_object_is_framebuffer(obj)) { > i915_gem_object_unlock(obj); > return -EBUSY; > diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > index 8291ede6902c..eb2011ccb92b 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > @@ -947,7 +947,7 @@ static int gpu_write(struct intel_context *ce, > { > int err; > > - i915_gem_object_lock(vma->obj); > + i915_gem_object_lock(vma->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(vma->obj, true); > i915_gem_object_unlock(vma->obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > index 299c29e9ad86..4e36d4897ea6 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > @@ -75,7 +75,7 @@ static int __igt_client_fill(struct intel_engine_cs *engine) > if (err) > goto err_unpin; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > index 87d7d8aa080f..1de2959b153c 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > @@ -82,7 +82,7 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v) > u32 __iomem *map; > int err = 0; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -115,7 +115,7 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) > u32 __iomem *map; > int err = 0; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -147,7 +147,7 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v) > u32 *map; > int err; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_wc_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -170,7 +170,7 @@ static int wc_get(struct context *ctx, unsigned long offset, u32 *v) > u32 *map; > int err; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_wc_domain(ctx->obj, false); > i915_gem_object_unlock(ctx->obj); > if (err) > @@ -193,7 +193,7 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) > u32 *cs; > int err; > > - i915_gem_object_lock(ctx->obj); > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); > i915_gem_object_unlock(ctx->obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > index b81978890641..438c15ef2184 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > @@ -950,7 +950,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, > if (IS_ERR(vma)) > return PTR_ERR(vma); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) > @@ -1706,7 +1706,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, > > i915_request_add(rq); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > index 9c7402ce5bf9..9fb95a45bcad 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c > @@ -103,7 +103,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj, > GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); > GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { > @@ -188,7 +188,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj, > GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); > GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c > index 34932871b3a5..a94243dc4c5c 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c > @@ -44,7 +44,7 @@ static int mock_phys_object(void *arg) > } > > /* Make the object dirty so that put_pages must do copy back the data */ > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) { > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > index febc9e6692ba..61a0532d0f3d 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > @@ -214,7 +214,7 @@ static int check_whitelist(struct i915_gem_context *ctx, > return PTR_ERR(results); > > err = 0; > - i915_gem_object_lock(results); > + i915_gem_object_lock(results, NULL); > intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */ > err = i915_gem_object_set_to_cpu_domain(results, false); > i915_gem_object_unlock(results); > diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c > index f1940939260a..943c8d232703 100644 > --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c > +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c > @@ -2982,7 +2982,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) > goto put_obj; > } > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > ret = i915_gem_object_set_to_cpu_domain(obj, false); > i915_gem_object_unlock(obj); > if (ret) { > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 9aa3066cb75d..1e06752835e5 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -420,7 +420,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, > GEM_BUG_ON(!drm_mm_node_allocated(&node)); > } > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > goto out_unpin; > > @@ -619,7 +619,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, > GEM_BUG_ON(!drm_mm_node_allocated(&node)); > } > > - ret = i915_gem_object_lock_interruptible(obj); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > goto out_unpin; > > @@ -1290,7 +1290,7 @@ int i915_gem_freeze_late(struct drm_i915_private *i915) > i915_gem_drain_freed_objects(i915); > > list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) { > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > drm_WARN_ON(&i915->drm, > i915_gem_object_set_to_cpu_domain(obj, true)); > i915_gem_object_unlock(obj); > @@ -1344,6 +1344,52 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) > return ret; > } > > +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr) > +{ > + ww_acquire_init(&ww->ctx, &reservation_ww_class); > + INIT_LIST_HEAD(&ww->obj_list); > + ww->intr = intr; > + ww->contended = NULL; > +} > + > +static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) > +{ > + struct drm_i915_gem_object *obj; > + > + while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { I wanted to ask whether you think this is faster than for_each_list_entry, but then also realized you can optimise further by not bothering to list_del (since you know the whole list is going away). If you are not allowing ww ctx reuse you don't even need to re-init the list_head at the end. > + list_del(&obj->obj_link); > + i915_gem_object_unlock(obj); > + } > +} > + > +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) > +{ > + i915_gem_ww_ctx_unlock_all(ww); > + WARN_ON(ww->contended); Unless I am missing something this feels like a GEM_BUG_ON condition (translated: we should be confident after testing it is impossible to hit). Or it is allowed to not try the backoff on -EDEADLK? Backoff is the only place which resets the ww->contended, right? In this case WARN_ON would be wrong, but you probably did not went for this design. Should it be supported? > + ww_acquire_fini(&ww->ctx); > +} > + > +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww) > +{ > + int ret = 0; > + > + if (WARN_ON(!ww->contended)) > + return -EINVAL; > + > + i915_gem_ww_ctx_unlock_all(ww); > + if (ww->intr) > + ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx); > + else > + dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx); > + > + if (!ret) > + list_add_tail(&ww->contended->obj_link, &ww->obj_list); > + > + ww->contended = NULL; > + > + return ret; > +} > + > #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) > #include "selftests/mock_gem_device.c" > #include "selftests/i915_gem.c" > diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h > index 1753c84d6c0d..988755dbf4be 100644 > --- a/drivers/gpu/drm/i915/i915_gem.h > +++ b/drivers/gpu/drm/i915/i915_gem.h > @@ -116,4 +116,15 @@ static inline bool __tasklet_is_scheduled(struct tasklet_struct *t) > return test_bit(TASKLET_STATE_SCHED, &t->state); > } > > +struct i915_gem_ww_ctx { > + struct ww_acquire_ctx ctx; > + struct list_head obj_list; > + bool intr; > + struct drm_i915_gem_object *contended; > +}; > + > +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); > +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); > +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx); > + > #endif /* __I915_GEM_H__ */ > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c > index 88d400b9df88..23a6132c5f4e 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c > @@ -199,11 +199,52 @@ static int igt_gem_hibernate(void *arg) > return err; > } > > +static int igt_gem_ww_ctx(void *arg) > +{ > + struct drm_i915_private *i915 = arg; > + struct drm_i915_gem_object *obj, *obj2; > + struct i915_gem_ww_ctx ww; > + int err = 0; > + > + obj = i915_gem_object_create_internal(i915, PAGE_SIZE); > + if (IS_ERR(obj)) > + return PTR_ERR(obj); > + > + obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE); > + if (IS_ERR(obj)) { Wrong obj ^^^ vvv. > + err = PTR_ERR(obj); > + goto put1; > + } > + > + i915_gem_ww_ctx_init(&ww, true); Need to expand with non-interruptible, interruptible and mixed. > +retry: > + /* Lock the objects, twice for good measure (-EALREADY handling) */ > + err = i915_gem_object_lock(obj, &ww); > + if (!err) > + err = i915_gem_object_lock_interruptible(obj, &ww); This is -EALREADY on the 1st pass. > + if (!err) > + err = i915_gem_object_lock_interruptible(obj2, &ww); > + if (!err) > + err = i915_gem_object_lock(obj2, &ww); And this is -EALREADY again? > + > + if (err == -EDEADLK) { How do we get here with a single locking context? > + err = i915_gem_ww_ctx_backoff(&ww); > + if (!err) > + goto retry; > + } > + i915_gem_ww_ctx_fini(&ww); > + i915_gem_object_put(obj2); > +put1: > + i915_gem_object_put(obj); > + return err; > +} > + > int i915_gem_live_selftests(struct drm_i915_private *i915) > { > static const struct i915_subtest tests[] = { > SUBTEST(igt_gem_suspend), > SUBTEST(igt_gem_hibernate), > + SUBTEST(igt_gem_ww_ctx), > }; > > if (intel_gt_is_wedged(&i915->gt)) > diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c > index af89c7fc8f59..88c5e9acb84c 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_vma.c > +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c > @@ -892,7 +892,7 @@ static int igt_vma_remapped_gtt(void *arg) > unsigned int x, y; > int err; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_gtt_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) > diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > index 6e80d99048e4..957a7a52def7 100644 > --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c > +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c > @@ -509,7 +509,7 @@ static int igt_lmem_write_cpu(void *arg) > if (err) > goto out_unpin; > > - i915_gem_object_lock(obj); > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_set_to_wc_domain(obj, true); > i915_gem_object_unlock(obj); > if (err) > Regards, Tvrtko From tvrtko.ursulin at linux.intel.com Mon Jun 29 12:56:09 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 29 Jun 2020 13:56:09 +0100 Subject: [Intel-gfx] [PATCH 05/26] drm/i915: Remove locking from i915_gem_object_prepare_read/write In-Reply-To: <20200623142843.423594-5-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-5-maarten.lankhorst@linux.intel.com> Message-ID: <0c35f812-b1fd-c7b9-b4e4-5f2a6598a268@linux.intel.com> On 23/06/2020 15:28, Maarten Lankhorst wrote: > Execbuffer submission will perform its own WW locking, and we > cannot rely on the implicit lock there. > > This also makes it clear that the GVT code will get a lockdep splat when > multiple batchbuffer shadows need to be performed in the same instance, > fix that up. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/gem/i915_gem_domain.c | 20 ++++++------------- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 13 ++++++++++-- > drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 - > .../gpu/drm/i915/gem/selftests/huge_pages.c | 5 ++++- > .../i915/gem/selftests/i915_gem_coherency.c | 14 +++++++++---- > .../drm/i915/gem/selftests/i915_gem_context.c | 12 ++++++++--- > drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + > drivers/gpu/drm/i915/i915_gem.c | 20 +++++++++++++++++-- > 8 files changed, 59 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > index c0acfc97fae3..8ebceebd11b0 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c > @@ -576,19 +576,17 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > > - ret = i915_gem_object_lock_interruptible(obj, NULL); > - if (ret) > - return ret; > + assert_object_held(obj); > > ret = i915_gem_object_wait(obj, > I915_WAIT_INTERRUPTIBLE, > MAX_SCHEDULE_TIMEOUT); > if (ret) > - goto err_unlock; > + return ret; > > ret = i915_gem_object_pin_pages(obj); > if (ret) > - goto err_unlock; > + return ret; > > if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || > !static_cpu_has(X86_FEATURE_CLFLUSH)) { > @@ -616,8 +614,6 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, > > err_unpin: > i915_gem_object_unpin_pages(obj); > -err_unlock: > - i915_gem_object_unlock(obj); > return ret; > } > > @@ -630,20 +626,18 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, > if (!i915_gem_object_has_struct_page(obj)) > return -ENODEV; > > - ret = i915_gem_object_lock_interruptible(obj, NULL); > - if (ret) > - return ret; > + assert_object_held(obj); > > ret = i915_gem_object_wait(obj, > I915_WAIT_INTERRUPTIBLE | > I915_WAIT_ALL, > MAX_SCHEDULE_TIMEOUT); > if (ret) > - goto err_unlock; > + return ret; > > ret = i915_gem_object_pin_pages(obj); > if (ret) > - goto err_unlock; > + return ret; > > if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || > !static_cpu_has(X86_FEATURE_CLFLUSH)) { > @@ -680,7 +674,5 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, > > err_unpin: > i915_gem_object_unpin_pages(obj); > -err_unlock: > - i915_gem_object_unlock(obj); > return ret; > } > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 391d22051b20..f896b1a4b38a 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -1003,11 +1003,14 @@ static void reloc_cache_reset(struct reloc_cache *cache) > > vaddr = unmask_page(cache->vaddr); > if (cache->vaddr & KMAP) { > + struct drm_i915_gem_object *obj = > + (struct drm_i915_gem_object *)cache->node.mm; > if (cache->vaddr & CLFLUSH_AFTER) > mb(); > > kunmap_atomic(vaddr); > - i915_gem_object_finish_access((struct drm_i915_gem_object *)cache->node.mm); > + i915_gem_object_finish_access(obj); > + i915_gem_object_unlock(obj); > } else { > struct i915_ggtt *ggtt = cache_to_ggtt(cache); > > @@ -1042,10 +1045,16 @@ static void *reloc_kmap(struct drm_i915_gem_object *obj, > unsigned int flushes; > int err; > > - err = i915_gem_object_prepare_write(obj, &flushes); > + err = i915_gem_object_lock_interruptible(obj, NULL); > if (err) > return ERR_PTR(err); > > + err = i915_gem_object_prepare_write(obj, &flushes); > + if (err) { > + i915_gem_object_unlock(obj); > + return ERR_PTR(err); > + } > + > BUILD_BUG_ON(KMAP & CLFLUSH_FLAGS); > BUILD_BUG_ON((KMAP | CLFLUSH_FLAGS) & PAGE_MASK); > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h > index 5103067269b0..11b8e2735071 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h > @@ -434,7 +434,6 @@ static inline void > i915_gem_object_finish_access(struct drm_i915_gem_object *obj) > { > i915_gem_object_unpin_pages(obj); > - i915_gem_object_unlock(obj); > } > > static inline struct intel_engine_cs * > diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > index eb2011ccb92b..fff11327a8da 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c > @@ -964,9 +964,10 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) > unsigned long n; > int err; > > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_prepare_read(obj, &needs_flush); > if (err) > - return err; > + goto err_unlock; > > for (n = 0; n < obj->base.size >> PAGE_SHIFT; ++n) { > u32 *ptr = kmap_atomic(i915_gem_object_get_page(obj, n)); > @@ -986,6 +987,8 @@ __cpu_check_shmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) > } > > i915_gem_object_finish_access(obj); > +err_unlock: > + i915_gem_object_unlock(obj); > > return err; > } > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > index 1de2959b153c..dcdfc396f2f8 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c > @@ -27,9 +27,10 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) > u32 *cpu; > int err; > > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); > if (err) > - return err; > + goto out; > > page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); > map = kmap_atomic(page); > @@ -46,7 +47,9 @@ static int cpu_set(struct context *ctx, unsigned long offset, u32 v) > kunmap_atomic(map); > i915_gem_object_finish_access(ctx->obj); > > - return 0; > +out: > + i915_gem_object_unlock(ctx->obj); > + return err; > } > > static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) > @@ -57,9 +60,10 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) > u32 *cpu; > int err; > > + i915_gem_object_lock(ctx->obj, NULL); > err = i915_gem_object_prepare_read(ctx->obj, &needs_clflush); > if (err) > - return err; > + goto out; > > page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); > map = kmap_atomic(page); > @@ -73,7 +77,9 @@ static int cpu_get(struct context *ctx, unsigned long offset, u32 *v) > kunmap_atomic(map); > i915_gem_object_finish_access(ctx->obj); > > - return 0; > +out: > + i915_gem_object_unlock(ctx->obj); > + return err; > } > > static int gtt_set(struct context *ctx, unsigned long offset, u32 v) > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > index 438c15ef2184..76671f587b9d 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c > @@ -461,9 +461,10 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) > unsigned int n, m, need_flush; > int err; > > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_prepare_write(obj, &need_flush); > if (err) > - return err; > + goto out; > > for (n = 0; n < real_page_count(obj); n++) { > u32 *map; > @@ -479,7 +480,9 @@ static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) > i915_gem_object_finish_access(obj); > obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU; > obj->write_domain = 0; > - return 0; > +out: > + i915_gem_object_unlock(obj); > + return err; > } > > static noinline int cpu_check(struct drm_i915_gem_object *obj, > @@ -488,9 +491,10 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, > unsigned int n, m, needs_flush; > int err; > > + i915_gem_object_lock(obj, NULL); > err = i915_gem_object_prepare_read(obj, &needs_flush); > if (err) > - return err; > + goto out_unlock; > > for (n = 0; n < real_page_count(obj); n++) { > u32 *map; > @@ -527,6 +531,8 @@ static noinline int cpu_check(struct drm_i915_gem_object *obj, > } > > i915_gem_object_finish_access(obj); > +out_unlock: > + i915_gem_object_unlock(obj); > return err; > } > > diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c > index 943c8d232703..d0a599b51bfe 100644 > --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c > +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c > @@ -1923,6 +1923,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) > if (ret) > goto err_unmap; > > + i915_gem_object_unlock(bb->obj); > INIT_LIST_HEAD(&bb->list); > list_add(&bb->list, &s->workload->shadow_bb); > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 1e06752835e5..33f6f88c8b08 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -335,12 +335,20 @@ i915_gem_shmem_pread(struct drm_i915_gem_object *obj, > u64 remain; > int ret; > > - ret = i915_gem_object_prepare_read(obj, &needs_clflush); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > + ret = i915_gem_object_prepare_read(obj, &needs_clflush); > + if (ret) { > + i915_gem_object_unlock(obj); > + return ret; > + } > + > fence = i915_gem_object_lock_fence(obj); > i915_gem_object_finish_access(obj); > + i915_gem_object_unlock(obj); > + > if (!fence) > return -ENOMEM; > > @@ -734,12 +742,20 @@ i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, > u64 remain; > int ret; > > - ret = i915_gem_object_prepare_write(obj, &needs_clflush); > + ret = i915_gem_object_lock_interruptible(obj, NULL); > if (ret) > return ret; > > + ret = i915_gem_object_prepare_write(obj, &needs_clflush); > + if (ret) { > + i915_gem_object_unlock(obj); > + return ret; > + } > + > fence = i915_gem_object_lock_fence(obj); > i915_gem_object_finish_access(obj); > + i915_gem_object_unlock(obj); > + > if (!fence) > return -ENOMEM; > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com> Regards, Tvrtko From rodrigo.vivi at intel.com Mon Jun 29 13:02:19 2020 From: rodrigo.vivi at intel.com (Rodrigo Vivi) Date: Mon, 29 Jun 2020 06:02:19 -0700 Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/display: prefer dig_port to reference intel_digital_port In-Reply-To: <20200626234834.26864-3-lucas.demarchi@intel.com> References: <20200626234834.26864-1-lucas.demarchi@intel.com> <20200626234834.26864-3-lucas.demarchi@intel.com> Message-ID: <20200629130219.GE3702810@intel.com> On Fri, Jun 26, 2020 at 04:48:33PM -0700, Lucas De Marchi wrote: > We have a mix of dport, intel_dport, intel_dig_port and dig_port to > reference a intel_digital_port struct. Numbers are around > > 5 intel_dport > 36 dport > 479 intel_dig_port > 352 dig_port > > Since we already removed the intel_ prefix from most of our other > structs, do the same here and prefer dig_port. > > v2: rename everything in i915, not just a few display sources and > reword commit message (from Matt Roper) > > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 143 ++++---- > drivers/gpu/drm/i915/display/intel_display.c | 6 +- > drivers/gpu/drm/i915/display/intel_display.h | 2 +- > .../drm/i915/display/intel_display_debugfs.c | 12 +- > .../drm/i915/display/intel_display_power.c | 4 +- > .../drm/i915/display/intel_display_types.h | 40 +-- > drivers/gpu/drm/i915/display/intel_dp.c | 338 +++++++++--------- > drivers/gpu/drm/i915/display/intel_dp.h | 4 +- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 74 ++-- > drivers/gpu/drm/i915/display/intel_dp_mst.h | 6 +- > drivers/gpu/drm/i915/display/intel_dpio_phy.c | 38 +- > drivers/gpu/drm/i915/display/intel_hdcp.c | 118 +++--- > drivers/gpu/drm/i915/display/intel_hdmi.c | 252 ++++++------- > drivers/gpu/drm/i915/display/intel_hdmi.h | 4 +- > drivers/gpu/drm/i915/display/intel_lspcon.c | 8 +- > drivers/gpu/drm/i915/display/intel_lspcon.h | 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 4 +- > drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +- > 18 files changed, 530 insertions(+), 533 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 025d4052f6f8..583170e73881 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1394,10 +1394,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) > { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > - struct intel_digital_port *intel_dig_port = > - enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > > - intel_dp->DP = intel_dig_port->saved_port_bits | > + intel_dp->DP = dig_port->saved_port_bits | > DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); > intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); > } > @@ -2070,7 +2069,7 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, > static void skl_ddi_set_iboost(struct intel_encoder *encoder, > int level, enum intel_output_type type) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > enum port port = encoder->port; > u8 iboost; > @@ -2107,7 +2106,7 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, > > _skl_ddi_set_iboost(dev_priv, port, iboost); > > - if (port == PORT_A && intel_dig_port->max_lanes == 4) > + if (port == PORT_A && dig_port->max_lanes == 4) > _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); > } > > @@ -3000,15 +2999,15 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) > } > > static void > -icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, > +icl_program_mg_dp_mode(struct intel_digital_port *dig_port, > const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); > - enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port); > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > + enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); > u32 ln0, ln1, pin_assignment; > u8 width; > > - if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) > + if (dig_port->tc_mode == TC_PORT_TBT_ALT) > return; > > if (INTEL_GEN(dev_priv) >= 12) { > @@ -3027,13 +3026,13 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, > ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); > > /* DPPATC */ > - pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port); > + pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); > width = crtc_state->lane_count; > > switch (pin_assignment) { > case 0x0: > drm_WARN_ON(&dev_priv->drm, > - intel_dig_port->tc_mode != TC_PORT_LEGACY); > + dig_port->tc_mode != TC_PORT_LEGACY); > if (width == 1) { > ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; > } else { > @@ -3978,10 +3977,9 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, > > static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_i915_private *dev_priv = > - to_i915(intel_dig_port->base.base.dev); > - enum port port = intel_dig_port->base.port; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > + enum port port = dig_port->base.port; > u32 dp_tp_ctl, ddi_buf_ctl; > bool wait = false; > > @@ -4536,42 +4534,41 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { > }; > > static struct intel_connector * > -intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) > +intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) > { > - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > struct intel_connector *connector; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > > connector = intel_connector_alloc(); > if (!connector) > return NULL; > > - intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); > - intel_dig_port->dp.prepare_link_retrain = > - intel_ddi_prepare_link_retrain; > - intel_dig_port->dp.set_link_train = intel_ddi_set_link_train; > - intel_dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; > + dig_port->dp.output_reg = DDI_BUF_CTL(port); > + dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; > + dig_port->dp.set_link_train = intel_ddi_set_link_train; > + dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; > > if (INTEL_GEN(dev_priv) >= 12) > - intel_dig_port->dp.set_signal_levels = tgl_set_signal_levels; > + dig_port->dp.set_signal_levels = tgl_set_signal_levels; > else if (INTEL_GEN(dev_priv) >= 11) > - intel_dig_port->dp.set_signal_levels = icl_set_signal_levels; > + dig_port->dp.set_signal_levels = icl_set_signal_levels; > else if (IS_CANNONLAKE(dev_priv)) > - intel_dig_port->dp.set_signal_levels = cnl_set_signal_levels; > + dig_port->dp.set_signal_levels = cnl_set_signal_levels; > else if (IS_GEN9_LP(dev_priv)) > - intel_dig_port->dp.set_signal_levels = bxt_set_signal_levels; > + dig_port->dp.set_signal_levels = bxt_set_signal_levels; > else > - intel_dig_port->dp.set_signal_levels = hsw_set_signal_levels; > + dig_port->dp.set_signal_levels = hsw_set_signal_levels; > > - intel_dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; > - intel_dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; > + dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; > + dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; > > if (INTEL_GEN(dev_priv) < 12) { > - intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); > - intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); > + dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); > + dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); > } > > - if (!intel_dp_init_connector(intel_dig_port, connector)) { > + if (!intel_dp_init_connector(dig_port, connector)) { > kfree(connector); > return NULL; > } > @@ -4770,29 +4767,29 @@ static bool bdw_digital_port_connected(struct intel_encoder *encoder) > } > > static struct intel_connector * > -intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) > +intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) > { > struct intel_connector *connector; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > > connector = intel_connector_alloc(); > if (!connector) > return NULL; > > - intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); > - intel_hdmi_init_connector(intel_dig_port, connector); > + dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); > + intel_hdmi_init_connector(dig_port, connector); > > return connector; > } > > -static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) > +static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) > { > - struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > > - if (dport->base.port != PORT_A) > + if (dig_port->base.port != PORT_A) > return false; > > - if (dport->saved_port_bits & DDI_A_4_LANES) > + if (dig_port->saved_port_bits & DDI_A_4_LANES) > return false; > > /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only > @@ -4814,10 +4811,10 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) > } > > static int > -intel_ddi_max_lanes(struct intel_digital_port *intel_dport) > +intel_ddi_max_lanes(struct intel_digital_port *dig_port) > { > - struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev); > - enum port port = intel_dport->base.port; > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > + enum port port = dig_port->base.port; > int max_lanes = 4; > > if (INTEL_GEN(dev_priv) >= 11) > @@ -4836,10 +4833,10 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) > * wasn't lit up at boot. Force this bit set when needed > * so we use the proper lane count for our calculations. > */ > - if (intel_ddi_a_force_4_lanes(intel_dport)) { > + if (intel_ddi_a_force_4_lanes(dig_port)) { > drm_dbg_kms(&dev_priv->drm, > "Forcing DDI_A_4_LANES for port A\n"); > - intel_dport->saved_port_bits |= DDI_A_4_LANES; > + dig_port->saved_port_bits |= DDI_A_4_LANES; > max_lanes = 4; > } > > @@ -4848,7 +4845,7 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) > > void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > { > - struct intel_digital_port *intel_dig_port; > + struct intel_digital_port *dig_port; > struct intel_encoder *encoder; > bool init_hdmi, init_dp, init_lspcon = false; > enum phy phy = intel_port_to_phy(dev_priv, port); > @@ -4877,11 +4874,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > return; > } > > - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); > - if (!intel_dig_port) > + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); > + if (!dig_port) > return; > > - encoder = &intel_dig_port->base; > + encoder = &dig_port->base; > > drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, > DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); > @@ -4908,49 +4905,49 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > encoder->pipe_mask = ~0; > > if (INTEL_GEN(dev_priv) >= 11) > - intel_dig_port->saved_port_bits = intel_de_read(dev_priv, > - DDI_BUF_CTL(port)) & > - DDI_BUF_PORT_REVERSAL; > + dig_port->saved_port_bits = > + intel_de_read(dev_priv, DDI_BUF_CTL(port)) > + & DDI_BUF_PORT_REVERSAL; > else > - intel_dig_port->saved_port_bits = intel_de_read(dev_priv, > - DDI_BUF_CTL(port)) & > - (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); > + dig_port->saved_port_bits = > + intel_de_read(dev_priv, DDI_BUF_CTL(port)) > + & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); > > - intel_dig_port->dp.output_reg = INVALID_MMIO_REG; > - intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port); > - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); > + dig_port->dp.output_reg = INVALID_MMIO_REG; > + dig_port->max_lanes = intel_ddi_max_lanes(dig_port); > + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); > > if (intel_phy_is_tc(dev_priv, phy)) { > bool is_legacy = > !intel_bios_port_supports_typec_usb(dev_priv, port) && > !intel_bios_port_supports_tbt(dev_priv, port); > > - intel_tc_port_init(intel_dig_port, is_legacy); > + intel_tc_port_init(dig_port, is_legacy); > > encoder->update_prepare = intel_ddi_update_prepare; > encoder->update_complete = intel_ddi_update_complete; > } > > drm_WARN_ON(&dev_priv->drm, port > PORT_I); > - intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + > + dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + > port - PORT_A; > > if (init_dp) { > - if (!intel_ddi_init_dp_connector(intel_dig_port)) > + if (!intel_ddi_init_dp_connector(dig_port)) > goto err; > > - intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; > + dig_port->hpd_pulse = intel_dp_hpd_pulse; > } > > /* In theory we don't need the encoder->type check, but leave it just in > * case we have some really bad VBTs... */ > if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { > - if (!intel_ddi_init_hdmi_connector(intel_dig_port)) > + if (!intel_ddi_init_hdmi_connector(dig_port)) > goto err; > } > > if (init_lspcon) { > - if (lspcon_init(intel_dig_port)) > + if (lspcon_init(dig_port)) > /* TODO: handle hdmi info frame part */ > drm_dbg_kms(&dev_priv->drm, > "LSPCON init success on port %c\n", > @@ -4967,26 +4964,26 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > > if (INTEL_GEN(dev_priv) >= 11) { > if (intel_phy_is_tc(dev_priv, phy)) > - intel_dig_port->connected = intel_tc_port_connected; > + dig_port->connected = intel_tc_port_connected; > else > - intel_dig_port->connected = lpt_digital_port_connected; > + dig_port->connected = lpt_digital_port_connected; > } else if (INTEL_GEN(dev_priv) >= 8) { > if (port == PORT_A || IS_GEN9_LP(dev_priv)) > - intel_dig_port->connected = bdw_digital_port_connected; > + dig_port->connected = bdw_digital_port_connected; > else > - intel_dig_port->connected = lpt_digital_port_connected; > + dig_port->connected = lpt_digital_port_connected; > } else { > if (port == PORT_A) > - intel_dig_port->connected = hsw_digital_port_connected; > + dig_port->connected = hsw_digital_port_connected; > else > - intel_dig_port->connected = lpt_digital_port_connected; > + dig_port->connected = lpt_digital_port_connected; > } > > - intel_infoframe_init(intel_dig_port); > + intel_infoframe_init(dig_port); > > return; > > err: > drm_encoder_cleanup(&encoder->base); > - kfree(intel_dig_port); > + kfree(dig_port); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index a11bb675f9b3..3b1f0b28e585 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1611,13 +1611,13 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > } > > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > - struct intel_digital_port *dport, > + struct intel_digital_port *dig_port, > unsigned int expected_mask) > { > u32 port_mask; > i915_reg_t dpll_reg; > > - switch (dport->base.port) { > + switch (dig_port->base.port) { > case PORT_B: > port_mask = DPLL_PORTB_READY_MASK; > dpll_reg = DPLL(0); > @@ -1639,7 +1639,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > port_mask, expected_mask, 1000)) > drm_WARN(&dev_priv->drm, 1, > "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", > - dport->base.base.base.id, dport->base.base.name, > + dig_port->base.base.base.id, dig_port->base.base.name, > intel_de_read(dev_priv, dpll_reg) & port_mask, > expected_mask); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h > index b7a6d56bac5f..bc6021b994b1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.h > +++ b/drivers/gpu/drm/i915/display/intel_display.h > @@ -542,7 +542,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); > > int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > - struct intel_digital_port *dport, > + struct intel_digital_port *dig_port, > unsigned int expected_mask); > int intel_get_load_detect_pipe(struct drm_connector *connector, > struct intel_load_detect_pipe *old, > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index d1cb48b3f462..3644752cc5ec 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -1194,7 +1194,7 @@ static int i915_dp_mst_info(struct seq_file *m, void *unused) > struct drm_i915_private *dev_priv = node_to_i915(m->private); > struct drm_device *dev = &dev_priv->drm; > struct intel_encoder *intel_encoder; > - struct intel_digital_port *intel_dig_port; > + struct intel_digital_port *dig_port; > struct drm_connector *connector; > struct drm_connector_list_iter conn_iter; > > @@ -1207,14 +1207,14 @@ static int i915_dp_mst_info(struct seq_file *m, void *unused) > if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) > continue; > > - intel_dig_port = enc_to_dig_port(intel_encoder); > - if (!intel_dig_port->dp.can_mst) > + dig_port = enc_to_dig_port(intel_encoder); > + if (!dig_port->dp.can_mst) > continue; > > seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > - drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); > + dig_port->base.base.base.id, > + dig_port->base.base.name); > + drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); > } > drm_connector_list_iter_end(&conn_iter); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 8a277dfbc070..0c713e83274d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -1817,8 +1817,8 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct i915_power_domains *power_domains = &dev_priv->power_domains; > - enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(encoder)); > - enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(encoder)); > + enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); > + enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); > > mutex_lock(&power_domains->lock); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 4b0aaa3081c9..e8f809161c75 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -279,10 +279,10 @@ enum check_link_response { > */ > struct intel_hdcp_shim { > /* Outputs the transmitter's An and Aksv values to the receiver. */ > - int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an); > + int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); > > /* Reads the receiver's key selection vector */ > - int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv); > + int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); > > /* > * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The > @@ -290,52 +290,52 @@ struct intel_hdcp_shim { > * different. Call it BSTATUS since that's the name the HDMI spec > * uses and it was there first. > */ > - int (*read_bstatus)(struct intel_digital_port *intel_dig_port, > + int (*read_bstatus)(struct intel_digital_port *dig_port, > u8 *bstatus); > > /* Determines whether a repeater is present downstream */ > - int (*repeater_present)(struct intel_digital_port *intel_dig_port, > + int (*repeater_present)(struct intel_digital_port *dig_port, > bool *repeater_present); > > /* Reads the receiver's Ri' value */ > - int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri); > + int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); > > /* Determines if the receiver's KSV FIFO is ready for consumption */ > - int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port, > + int (*read_ksv_ready)(struct intel_digital_port *dig_port, > bool *ksv_ready); > > /* Reads the ksv fifo for num_downstream devices */ > - int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port, > + int (*read_ksv_fifo)(struct intel_digital_port *dig_port, > int num_downstream, u8 *ksv_fifo); > > /* Reads a 32-bit part of V' from the receiver */ > - int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port, > + int (*read_v_prime_part)(struct intel_digital_port *dig_port, > int i, u32 *part); > > /* Enables HDCP signalling on the port */ > - int (*toggle_signalling)(struct intel_digital_port *intel_dig_port, > + int (*toggle_signalling)(struct intel_digital_port *dig_port, > bool enable); > > /* Ensures the link is still protected */ > - bool (*check_link)(struct intel_digital_port *intel_dig_port); > + bool (*check_link)(struct intel_digital_port *dig_port); > > /* Detects panel's hdcp capability. This is optional for HDMI. */ > - int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, > + int (*hdcp_capable)(struct intel_digital_port *dig_port, > bool *hdcp_capable); > > /* HDCP adaptation(DP/HDMI) required on the port */ > enum hdcp_wired_protocol protocol; > > /* Detects whether sink is HDCP2.2 capable */ > - int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port, > + int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port, > bool *capable); > > /* Write HDCP2.2 messages */ > - int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port, > + int (*write_2_2_msg)(struct intel_digital_port *dig_port, > void *buf, size_t size); > > /* Read HDCP2.2 messages */ > - int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port, > + int (*read_2_2_msg)(struct intel_digital_port *dig_port, > u8 msg_id, void *buf, size_t size); > > /* > @@ -343,11 +343,11 @@ struct intel_hdcp_shim { > * type to Receivers. In DP HDCP2.2 Stream type is one of the input to > * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. > */ > - int (*config_stream_type)(struct intel_digital_port *intel_dig_port, > + int (*config_stream_type)(struct intel_digital_port *dig_port, > bool is_repeater, u8 type); > > /* HDCP2.2 Link Integrity Check */ > - int (*check_2_2_link)(struct intel_digital_port *intel_dig_port); > + int (*check_2_2_link)(struct intel_digital_port *dig_port); > }; > > struct intel_hdcp { > @@ -1434,9 +1434,9 @@ struct intel_dp_mst_encoder { > }; > > static inline enum dpio_channel > -vlv_dport_to_channel(struct intel_digital_port *dport) > +vlv_dig_port_to_channel(struct intel_digital_port *dig_port) > { > - switch (dport->base.port) { > + switch (dig_port->base.port) { > case PORT_B: > case PORT_D: > return DPIO_CH0; > @@ -1448,9 +1448,9 @@ vlv_dport_to_channel(struct intel_digital_port *dport) > } > > static inline enum dpio_phy > -vlv_dport_to_phy(struct intel_digital_port *dport) > +vlv_dig_port_to_phy(struct intel_digital_port *dig_port) > { > - switch (dport->base.port) { > + switch (dig_port->base.port) { > case PORT_B: > case PORT_C: > return DPIO_PHY0; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 3df5d901dd9d..d6295eb20b63 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -140,9 +140,9 @@ static const u8 valid_dsc_slicecount[] = {1, 2, 4}; > */ > bool intel_dp_is_edp(struct intel_dp *intel_dp) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > > - return intel_dig_port->base.type == INTEL_OUTPUT_EDP; > + return dig_port->base.type == INTEL_OUTPUT_EDP; > } > > static void intel_dp_link_down(struct intel_encoder *encoder, > @@ -216,10 +216,10 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp) > /* Theoretical max between source and sink */ > static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - int source_max = intel_dig_port->max_lanes; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + int source_max = dig_port->max_lanes; > int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); > - int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port); > + int fia_max = intel_tc_port_fia_max_lane_count(dig_port); > > return min3(source_max, sink_max, fia_max); > } > @@ -251,8 +251,8 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes) > static int > intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct intel_encoder *encoder = &intel_dig_port->base; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct intel_encoder *encoder = &dig_port->base; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > int max_dotclk = dev_priv->max_dotclk_freq; > int ds_max_dotclk; > @@ -778,7 +778,7 @@ static void > vlv_power_sequencer_kick(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > enum pipe pipe = intel_dp->pps_pipe; > bool pll_enabled, release_cl_override = false; > enum dpio_phy phy = DPIO_PHY(pipe); > @@ -788,14 +788,14 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) > if (drm_WARN(&dev_priv->drm, > intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, > "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", > - pipe_name(pipe), intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name)) > + pipe_name(pipe), dig_port->base.base.base.id, > + dig_port->base.base.name)) > return; > > drm_dbg_kms(&dev_priv->drm, > "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", > - pipe_name(pipe), intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + pipe_name(pipe), dig_port->base.base.base.id, > + dig_port->base.base.name); > > /* Preserve the BIOS-computed detected bit. This is > * supposed to be read-only. > @@ -891,7 +891,7 @@ static enum pipe > vlv_power_sequencer_pipe(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > enum pipe pipe; > > lockdep_assert_held(&dev_priv->pps_mutex); > @@ -920,8 +920,8 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) > drm_dbg_kms(&dev_priv->drm, > "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", > pipe_name(intel_dp->pps_pipe), > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + dig_port->base.base.base.id, > + dig_port->base.base.name); > > /* init power sequencer on this pipe and port */ > intel_dp_init_panel_power_sequencer(intel_dp); > @@ -1009,8 +1009,8 @@ static void > vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - enum port port = intel_dig_port->base.port; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + enum port port = dig_port->base.port; > > lockdep_assert_held(&dev_priv->pps_mutex); > > @@ -1031,15 +1031,15 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) > if (intel_dp->pps_pipe == INVALID_PIPE) { > drm_dbg_kms(&dev_priv->drm, > "no initial power sequencer for [ENCODER:%d:%s]\n", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + dig_port->base.base.base.id, > + dig_port->base.base.name); > return; > } > > drm_dbg_kms(&dev_priv->drm, > "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name, > + dig_port->base.base.base.id, > + dig_port->base.base.name, > pipe_name(intel_dp->pps_pipe)); > > intel_dp_init_panel_power_sequencer(intel_dp); > @@ -1304,9 +1304,9 @@ static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, > int send_bytes, > u32 aux_clock_divider) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_i915_private *dev_priv = > - to_i915(intel_dig_port->base.base.dev); > + to_i915(dig_port->base.base.dev); > u32 precharge, timeout; > > if (IS_GEN(dev_priv, 6)) > @@ -1334,10 +1334,10 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, > int send_bytes, > u32 unused) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_i915_private *i915 = > - to_i915(intel_dig_port->base.base.dev); > - enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); > + to_i915(dig_port->base.base.dev); > + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); > u32 ret; > > ret = DP_AUX_CH_CTL_SEND_BUSY | > @@ -1351,7 +1351,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, > DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); > > if (intel_phy_is_tc(i915, phy) && > - intel_dig_port->tc_mode == TC_PORT_TBT_ALT) > + dig_port->tc_mode == TC_PORT_TBT_ALT) > ret |= DP_AUX_CH_CTL_TBT_IO; > > return ret; > @@ -1363,11 +1363,11 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, > u8 *recv, int recv_size, > u32 aux_send_ctl_flags) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_i915_private *i915 = > - to_i915(intel_dig_port->base.base.dev); > + to_i915(dig_port->base.base.dev); > struct intel_uncore *uncore = &i915->uncore; > - enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); > + enum phy phy = intel_port_to_phy(i915, dig_port->base.port); > bool is_tc_port = intel_phy_is_tc(i915, phy); > i915_reg_t ch_ctl, ch_data[5]; > u32 aux_clock_divider; > @@ -1384,9 +1384,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, > ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); > > if (is_tc_port) > - intel_tc_port_lock(intel_dig_port); > + intel_tc_port_lock(dig_port); > > - aux_domain = intel_aux_power_domain(intel_dig_port); > + aux_domain = intel_aux_power_domain(dig_port); > > aux_wakeref = intel_display_power_get(i915, aux_domain); > pps_wakeref = pps_lock(intel_dp); > @@ -1545,7 +1545,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, > intel_display_power_put_async(i915, aux_domain, aux_wakeref); > > if (is_tc_port) > - intel_tc_port_unlock(intel_dig_port); > + intel_tc_port_unlock(dig_port); > > return ret; > } > @@ -2891,7 +2891,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp) > static bool edp_panel_vdd_on(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > u32 pp; > i915_reg_t pp_stat_reg, pp_ctrl_reg; > bool need_to_disable = !intel_dp->want_panel_vdd; > @@ -2908,11 +2908,11 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) > return need_to_disable; > > intel_display_power_get(dev_priv, > - intel_aux_power_domain(intel_dig_port)); > + intel_aux_power_domain(dig_port)); > > drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + dig_port->base.base.base.id, > + dig_port->base.base.name); > > if (!edp_have_panel_power(intel_dp)) > wait_panel_power_cycle(intel_dp); > @@ -2934,8 +2934,8 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) > if (!edp_have_panel_power(intel_dp)) { > drm_dbg_kms(&dev_priv->drm, > "[ENCODER:%d:%s] panel power wasn't enabled\n", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + dig_port->base.base.base.id, > + dig_port->base.base.name); > msleep(intel_dp->panel_power_up_delay); > } > > @@ -2968,7 +2968,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) > static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > - struct intel_digital_port *intel_dig_port = > + struct intel_digital_port *dig_port = > dp_to_dig_port(intel_dp); > u32 pp; > i915_reg_t pp_stat_reg, pp_ctrl_reg; > @@ -2981,8 +2981,8 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) > return; > > drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + dig_port->base.base.base.id, > + dig_port->base.base.name); > > pp = ilk_get_pp_control(intel_dp); > pp &= ~EDP_FORCE_VDD; > @@ -3002,7 +3002,7 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) > intel_dp->panel_power_off_time = ktime_get_boottime(); > > intel_display_power_put_unchecked(dev_priv, > - intel_aux_power_domain(intel_dig_port)); > + intel_aux_power_domain(dig_port)); > } > > static void edp_panel_vdd_work(struct work_struct *__work) > @@ -3833,8 +3833,8 @@ static void g4x_pre_enable_dp(struct intel_atomic_state *state, > > static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > enum pipe pipe = intel_dp->pps_pipe; > i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); > > @@ -3856,8 +3856,8 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) > */ > drm_dbg_kms(&dev_priv->drm, > "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", > - pipe_name(pipe), intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + pipe_name(pipe), dig_port->base.base.base.id, > + dig_port->base.base.name); > intel_de_write(dev_priv, pp_on_reg, 0); > intel_de_posting_read(dev_priv, pp_on_reg); > > @@ -4923,7 +4923,7 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > unsigned int type) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct dp_sdp sdp = {}; > ssize_t len; > @@ -4949,14 +4949,14 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, > if (drm_WARN_ON(&dev_priv->drm, len < 0)) > return; > > - intel_dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); > + dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); > } > > void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > struct drm_dp_vsc_sdp *vsc) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct dp_sdp sdp = {}; > ssize_t len; > @@ -4966,7 +4966,7 @@ void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, > if (drm_WARN_ON(&dev_priv->drm, len < 0)) > return; > > - intel_dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, > + dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, > &sdp, len); > } > > @@ -5126,7 +5126,7 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, > struct intel_crtc_state *crtc_state, > struct drm_dp_vsc_sdp *vsc) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > unsigned int type = DP_SDP_VSC; > @@ -5141,7 +5141,7 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, > intel_hdmi_infoframe_enable(type)) == 0) > return; > > - intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); > + dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); > > ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); > > @@ -5153,7 +5153,7 @@ static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encod > struct intel_crtc_state *crtc_state, > struct hdmi_drm_infoframe *drm_infoframe) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; > struct dp_sdp sdp = {}; > @@ -5163,8 +5163,8 @@ static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encod > intel_hdmi_infoframe_enable(type)) == 0) > return; > > - intel_dig_port->read_infoframe(encoder, crtc_state, type, &sdp, > - sizeof(sdp)); > + dig_port->read_infoframe(encoder, crtc_state, type, &sdp, > + sizeof(sdp)); > > ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, > sizeof(sdp)); > @@ -5366,10 +5366,10 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = > to_i915(dp_to_dig_port(intel_dp)->base.base.dev); > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_dp_phy_test_params *data = > &intel_dp->compliance.test_data.phytest; > - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); > + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); > enum pipe pipe = crtc->pipe; > u32 pattern_val; > > @@ -5431,10 +5431,10 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > static void > intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_device *dev = intel_dig_port->base.base.dev; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct drm_device *dev = dig_port->base.base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); > + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); > enum pipe pipe = crtc->pipe; > u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; > > @@ -5457,11 +5457,11 @@ intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp) > static void > intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt) > { > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_device *dev = intel_dig_port->base.base.dev; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct drm_device *dev = dig_port->base.base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > - enum port port = intel_dig_port->base.port; > - struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); > + enum port port = dig_port->base.port; > + struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); > enum pipe pipe = crtc->pipe; > u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; > > @@ -6332,10 +6332,10 @@ intel_dp_connector_unregister(struct drm_connector *connector) > > void intel_dp_encoder_flush_work(struct drm_encoder *encoder) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder)); > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); > + struct intel_dp *intel_dp = &dig_port->dp; > > - intel_dp_mst_encoder_cleanup(intel_dig_port); > + intel_dp_mst_encoder_cleanup(dig_port); > if (intel_dp_is_edp(intel_dp)) { > intel_wakeref_t wakeref; > > @@ -6394,11 +6394,11 @@ static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) > } > > static > -int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, > u8 *an) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base)); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&dig_port->base.base)); > static const struct drm_dp_aux_msg msg = { > .request = DP_AUX_NATIVE_WRITE, > .address = DP_AUX_HDCP_AKSV, > @@ -6409,7 +6409,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, > int ret; > > /* Output An first, that's easy */ > - dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, > + dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, > an, DRM_HDCP_AN_LEN); > if (dpcd_ret != DRM_HDCP_AN_LEN) { > drm_dbg_kms(&i915->drm, > @@ -6448,13 +6448,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, > return 0; > } > > -static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, > +static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, > u8 *bksv) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, > DRM_HDCP_KSV_LEN); > if (ret != DRM_HDCP_KSV_LEN) { > drm_dbg_kms(&i915->drm, > @@ -6464,10 +6464,10 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, > return 0; > } > > -static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, > +static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, > u8 *bstatus) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > > /* > @@ -6475,7 +6475,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, > * definition by different names. In the HDMI spec, it's called BSTATUS, > * but in DP it's called BINFO. > */ > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, > bstatus, DRM_HDCP_BSTATUS_LEN); > if (ret != DRM_HDCP_BSTATUS_LEN) { > drm_dbg_kms(&i915->drm, > @@ -6486,13 +6486,13 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port, > u8 *bcaps) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS, > bcaps, 1); > if (ret != 1) { > drm_dbg_kms(&i915->drm, > @@ -6504,13 +6504,13 @@ int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, > bool *repeater_present) > { > ssize_t ret; > u8 bcaps; > > - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); > + ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); > if (ret) > return ret; > > @@ -6519,13 +6519,13 @@ int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, > u8 *ri_prime) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, > ri_prime, DRM_HDCP_RI_LEN); > if (ret != DRM_HDCP_RI_LEN) { > drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", > @@ -6536,14 +6536,14 @@ int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, > bool *ksv_ready) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > u8 bstatus; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, > &bstatus, 1); > if (ret != 1) { > drm_dbg_kms(&i915->drm, > @@ -6555,17 +6555,17 @@ int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, > int num_downstream, u8 *ksv_fifo) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > int i; > > /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ > for (i = 0; i < num_downstream; i += 3) { > size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, > DP_AUX_HDCP_KSV_FIFO, > ksv_fifo + i * DRM_HDCP_KSV_LEN, > len); > @@ -6580,16 +6580,16 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, > int i, u32 *part) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > > if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) > return -EINVAL; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, > DP_AUX_HDCP_V_PRIME(i), part, > DRM_HDCP_V_PRIME_PART_LEN); > if (ret != DRM_HDCP_V_PRIME_PART_LEN) { > @@ -6601,7 +6601,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, > bool enable) > { > /* Not used for single stream DisplayPort setups */ > @@ -6609,13 +6609,13 @@ int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, > } > > static > -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) > +bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > u8 bstatus; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, > &bstatus, 1); > if (ret != 1) { > drm_dbg_kms(&i915->drm, > @@ -6627,13 +6627,13 @@ bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) > } > > static > -int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp_capable(struct intel_digital_port *dig_port, > bool *hdcp_capable) > { > ssize_t ret; > u8 bcaps; > > - ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); > + ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); > if (ret) > return ret; > > @@ -6691,13 +6691,13 @@ static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { > }; > > static int > -intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, > +intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, > u8 *rx_status) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > ssize_t ret; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, > DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, > HDCP_2_2_DP_RXSTATUS_LEN); > if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { > @@ -6710,14 +6710,14 @@ intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, > } > > static > -int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, > +int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, > u8 msg_id, bool *msg_ready) > { > u8 rx_status; > int ret; > > *msg_ready = false; > - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); > + ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); > if (ret < 0) > return ret; > > @@ -6743,11 +6743,11 @@ int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, > } > > static ssize_t > -intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, > +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, > const struct hdcp2_dp_msg_data *hdcp2_msg_data) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_dp *dp = &intel_dig_port->dp; > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_dp *dp = &dig_port->dp; > struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; > u8 msg_id = hdcp2_msg_data->msg_id; > int ret, timeout; > @@ -6771,7 +6771,7 @@ intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, > * the timeout at wait for CP_IRQ. > */ > intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); > - ret = hdcp2_detect_msg_availability(intel_dig_port, > + ret = hdcp2_detect_msg_availability(dig_port, > msg_id, &msg_ready); > if (!msg_ready) > ret = -ETIMEDOUT; > @@ -6797,10 +6797,10 @@ static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) > } > > static > -int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, > void *buf, size_t size) > { > - struct intel_dp *dp = &intel_dig_port->dp; > + struct intel_dp *dp = &dig_port->dp; > struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; > unsigned int offset; > u8 *byte = buf; > @@ -6823,7 +6823,7 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, > len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? > DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; > > - ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, > + ret = drm_dp_dpcd_write(&dig_port->dp.aux, > offset, (void *)byte, len); > if (ret < 0) > return ret; > @@ -6837,13 +6837,13 @@ int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, > } > > static > -ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) > +ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port) > { > u8 rx_info[HDCP_2_2_RXINFO_LEN]; > u32 dev_cnt; > ssize_t ret; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, > DP_HDCP_2_2_REG_RXINFO_OFFSET, > (void *)rx_info, HDCP_2_2_RXINFO_LEN); > if (ret != HDCP_2_2_RXINFO_LEN) > @@ -6863,10 +6863,10 @@ ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) > } > > static > -int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, > u8 msg_id, void *buf, size_t size) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > unsigned int offset; > u8 *byte = buf; > ssize_t ret, bytes_to_recv, len; > @@ -6877,12 +6877,12 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > return -EINVAL; > offset = hdcp2_msg_data->offset; > > - ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); > + ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data); > if (ret < 0) > return ret; > > if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { > - ret = get_receiver_id_list_size(intel_dig_port); > + ret = get_receiver_id_list_size(dig_port); > if (ret < 0) > return ret; > > @@ -6897,7 +6897,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? > DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; > > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset, > (void *)byte, len); > if (ret < 0) { > drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", > @@ -6916,7 +6916,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port, > bool is_repeater, u8 content_type) > { > int ret; > @@ -6935,7 +6935,7 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, > stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; > stream_type_msg.stream_type = content_type; > > - ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, > + ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg, > sizeof(stream_type_msg)); > > return ret < 0 ? ret : 0; > @@ -6943,12 +6943,12 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) > +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port) > { > u8 rx_status; > int ret; > > - ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); > + ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); > if (ret) > return ret; > > @@ -6963,14 +6963,14 @@ int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) > } > > static > -int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, > +int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port, > bool *capable) > { > u8 rx_caps[3]; > int ret; > > *capable = false; > - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, > + ret = drm_dp_dpcd_read(&dig_port->dp.aux, > DP_HDCP_2_2_REG_RX_CAPS_OFFSET, > rx_caps, HDCP_2_2_RXCAPS_LEN); > if (ret != HDCP_2_2_RXCAPS_LEN) > @@ -7249,12 +7249,12 @@ static bool intel_edp_have_power(struct intel_dp *intel_dp) > } > > enum irqreturn > -intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > +intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_dp *intel_dp = &dig_port->dp; > > - if (intel_dig_port->base.type == INTEL_OUTPUT_EDP && > + if (dig_port->base.type == INTEL_OUTPUT_EDP && > (long_hpd || !intel_edp_have_power(intel_dp))) { > /* > * vdd off can generate a long/short pulse on eDP which > @@ -7265,14 +7265,14 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) > drm_dbg_kms(&i915->drm, > "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", > long_hpd ? "long" : "short", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name); > + dig_port->base.base.base.id, > + dig_port->base.base.name); > return IRQ_HANDLED; > } > > drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", > - intel_dig_port->base.base.base.id, > - intel_dig_port->base.base.name, > + dig_port->base.base.base.id, > + dig_port->base.base.name, > long_hpd ? "long" : "short"); > > if (long_hpd) { > @@ -8135,12 +8135,12 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work) > } > > bool > -intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > +intel_dp_init_connector(struct intel_digital_port *dig_port, > struct intel_connector *intel_connector) > { > struct drm_connector *connector = &intel_connector->base; > - struct intel_dp *intel_dp = &intel_dig_port->dp; > - struct intel_encoder *intel_encoder = &intel_dig_port->base; > + struct intel_dp *intel_dp = &dig_port->dp; > + struct intel_encoder *intel_encoder = &dig_port->base; > struct drm_device *dev = intel_encoder->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > enum port port = intel_encoder->port; > @@ -8151,9 +8151,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > INIT_WORK(&intel_connector->modeset_retry_work, > intel_dp_modeset_retry_work_fn); > > - if (drm_WARN(dev, intel_dig_port->max_lanes < 1, > + if (drm_WARN(dev, dig_port->max_lanes < 1, > "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", > - intel_dig_port->max_lanes, intel_encoder->base.base.id, > + dig_port->max_lanes, intel_encoder->base.base.id, > intel_encoder->base.name)) > return false; > > @@ -8224,12 +8224,12 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > intel_connector->get_hw_state = intel_connector_get_hw_state; > > /* init MST on ports that can support it */ > - intel_dp_mst_encoder_init(intel_dig_port, > + intel_dp_mst_encoder_init(dig_port, > intel_connector->base.base.id); > > if (!intel_edp_init_connector(intel_dp, intel_connector)) { > intel_dp_aux_fini(intel_dp); > - intel_dp_mst_encoder_cleanup(intel_dig_port); > + intel_dp_mst_encoder_cleanup(dig_port); > goto fail; > } > > @@ -8264,20 +8264,20 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, > i915_reg_t output_reg, > enum port port) > { > - struct intel_digital_port *intel_dig_port; > + struct intel_digital_port *dig_port; > struct intel_encoder *intel_encoder; > struct drm_encoder *encoder; > struct intel_connector *intel_connector; > > - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); > - if (!intel_dig_port) > + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); > + if (!dig_port) > return false; > > intel_connector = intel_connector_alloc(); > if (!intel_connector) > goto err_connector_alloc; > > - intel_encoder = &intel_dig_port->base; > + intel_encoder = &dig_port->base; > encoder = &intel_encoder->base; > > if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, > @@ -8313,34 +8313,34 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, > > if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || > (HAS_PCH_CPT(dev_priv) && port != PORT_A)) > - intel_dig_port->dp.set_link_train = cpt_set_link_train; > + dig_port->dp.set_link_train = cpt_set_link_train; > else > - intel_dig_port->dp.set_link_train = g4x_set_link_train; > + dig_port->dp.set_link_train = g4x_set_link_train; > > if (IS_CHERRYVIEW(dev_priv)) > - intel_dig_port->dp.set_signal_levels = chv_set_signal_levels; > + dig_port->dp.set_signal_levels = chv_set_signal_levels; > else if (IS_VALLEYVIEW(dev_priv)) > - intel_dig_port->dp.set_signal_levels = vlv_set_signal_levels; > + dig_port->dp.set_signal_levels = vlv_set_signal_levels; > else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) > - intel_dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; > + dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels; > else if (IS_GEN(dev_priv, 6) && port == PORT_A) > - intel_dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; > + dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels; > else > - intel_dig_port->dp.set_signal_levels = g4x_set_signal_levels; > + dig_port->dp.set_signal_levels = g4x_set_signal_levels; > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || > (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { > - intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3; > - intel_dig_port->dp.voltage_max = intel_dp_voltage_max_3; > + dig_port->dp.preemph_max = intel_dp_pre_empemph_max_3; > + dig_port->dp.voltage_max = intel_dp_voltage_max_3; > } else { > - intel_dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2; > - intel_dig_port->dp.voltage_max = intel_dp_voltage_max_2; > + dig_port->dp.preemph_max = intel_dp_pre_empemph_max_2; > + dig_port->dp.voltage_max = intel_dp_voltage_max_2; > } > > - intel_dig_port->dp.output_reg = output_reg; > - intel_dig_port->max_lanes = 4; > - intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); > - intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); > + dig_port->dp.output_reg = output_reg; > + dig_port->max_lanes = 4; > + dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); > + dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); > > intel_encoder->type = INTEL_OUTPUT_DP; > intel_encoder->power_domain = intel_port_to_power_domain(port); > @@ -8355,25 +8355,25 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, > intel_encoder->cloneable = 0; > intel_encoder->port = port; > > - intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; > + dig_port->hpd_pulse = intel_dp_hpd_pulse; > > if (HAS_GMCH(dev_priv)) { > if (IS_GM45(dev_priv)) > - intel_dig_port->connected = gm45_digital_port_connected; > + dig_port->connected = gm45_digital_port_connected; > else > - intel_dig_port->connected = g4x_digital_port_connected; > + dig_port->connected = g4x_digital_port_connected; > } else { > if (port == PORT_A) > - intel_dig_port->connected = ilk_digital_port_connected; > + dig_port->connected = ilk_digital_port_connected; > else > - intel_dig_port->connected = ibx_digital_port_connected; > + dig_port->connected = ibx_digital_port_connected; > } > > if (port != PORT_A) > - intel_infoframe_init(intel_dig_port); > + intel_infoframe_init(dig_port); > > - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); > - if (!intel_dp_init_connector(intel_dig_port, intel_connector)) > + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); > + if (!intel_dp_init_connector(dig_port, intel_connector)) > goto err_init_connector; > > return true; > @@ -8383,7 +8383,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, > err_encoder_init: > kfree(intel_connector); > err_connector_alloc: > - kfree(intel_dig_port); > + kfree(dig_port); > return false; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h > index 0a8950f744f6..b901ab850cbd 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -40,7 +40,7 @@ bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, > enum pipe *pipe); > bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, > enum port port); > -bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > +bool intel_dp_init_connector(struct intel_digital_port *dig_port, > struct intel_connector *intel_connector); > void intel_dp_set_link_params(struct intel_dp *intel_dp, > int link_rate, u8 lane_count, > @@ -61,7 +61,7 @@ int intel_dp_compute_config(struct intel_encoder *encoder, > struct drm_connector_state *conn_state); > bool intel_dp_is_edp(struct intel_dp *intel_dp); > bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); > -enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, > +enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, > bool long_hpd); > void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, > const struct drm_connector_state *conn_state); > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 8273f2e07427..bdc19b04b2c1 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -342,8 +342,8 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, > const struct drm_connector_state *old_conn_state) > { > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > - struct intel_digital_port *intel_dig_port = intel_mst->primary; > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct intel_digital_port *dig_port = intel_mst->primary; > + struct intel_dp *intel_dp = &dig_port->dp; > struct intel_connector *connector = > to_intel_connector(old_conn_state->connector); > struct drm_i915_private *i915 = to_i915(connector->base.dev); > @@ -369,8 +369,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > const struct drm_connector_state *old_conn_state) > { > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > - struct intel_digital_port *intel_dig_port = intel_mst->primary; > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct intel_digital_port *dig_port = intel_mst->primary; > + struct intel_dp *intel_dp = &dig_port->dp; > struct intel_connector *connector = > to_intel_connector(old_conn_state->connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > @@ -421,7 +421,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > * the transcoder clock select is set to none. > */ > if (last_mst_stream) > - intel_dp_set_infoframes(&intel_dig_port->base, false, > + intel_dp_set_infoframes(&dig_port->base, false, > old_crtc_state, NULL); > /* > * From TGL spec: "If multi-stream slave transcoder: Configure > @@ -436,7 +436,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, > > intel_mst->connector = NULL; > if (last_mst_stream) > - intel_dig_port->base.post_disable(state, &intel_dig_port->base, > + dig_port->base.post_disable(state, &dig_port->base, > old_crtc_state, NULL); > > drm_dbg_kms(&dev_priv->drm, "active links %d\n", > @@ -449,11 +449,11 @@ static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, > const struct drm_connector_state *conn_state) > { > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > - struct intel_digital_port *intel_dig_port = intel_mst->primary; > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct intel_digital_port *dig_port = intel_mst->primary; > + struct intel_dp *intel_dp = &dig_port->dp; > > if (intel_dp->active_mst_links == 0) > - intel_dig_port->base.pre_pll_enable(state, &intel_dig_port->base, > + dig_port->base.pre_pll_enable(state, &dig_port->base, > pipe_config, NULL); > } > > @@ -463,8 +463,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > const struct drm_connector_state *conn_state) > { > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > - struct intel_digital_port *intel_dig_port = intel_mst->primary; > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct intel_digital_port *dig_port = intel_mst->primary; > + struct intel_dp *intel_dp = &dig_port->dp; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_connector *connector = > to_intel_connector(conn_state->connector); > @@ -490,7 +490,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); > > if (first_mst_stream) > - intel_dig_port->base.pre_enable(state, &intel_dig_port->base, > + dig_port->base.pre_enable(state, &dig_port->base, > pipe_config, NULL); > > ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, > @@ -506,7 +506,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, > > /* > * Before Gen 12 this is not done as part of > - * intel_dig_port->base.pre_enable() and should be done here. For > + * dig_port->base.pre_enable() and should be done here. For > * Gen 12+ the step in which this should be done is different for the > * first MST stream, so it's done on the DDI for the first stream and > * here for the following ones. > @@ -525,8 +525,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > const struct drm_connector_state *conn_state) > { > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > - struct intel_digital_port *intel_dig_port = intel_mst->primary; > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct intel_digital_port *dig_port = intel_mst->primary; > + struct intel_dp *intel_dp = &dig_port->dp; > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > u32 val; > > @@ -572,9 +572,9 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); > - struct intel_digital_port *intel_dig_port = intel_mst->primary; > + struct intel_digital_port *dig_port = intel_mst->primary; > > - intel_ddi_get_config(&intel_dig_port->base, pipe_config); > + intel_ddi_get_config(&dig_port->base, pipe_config); > } > > static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) > @@ -732,8 +732,8 @@ static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) > static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) > { > struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct drm_device *dev = intel_dig_port->base.base.dev; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct drm_device *dev = dig_port->base.base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > struct intel_connector *intel_connector; > struct drm_connector *connector; > @@ -808,11 +808,11 @@ static const struct drm_dp_mst_topology_cbs mst_cbs = { > }; > > static struct intel_dp_mst_encoder * > -intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) > +intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) > { > struct intel_dp_mst_encoder *intel_mst; > struct intel_encoder *intel_encoder; > - struct drm_device *dev = intel_dig_port->base.base.dev; > + struct drm_device *dev = dig_port->base.base.dev; > > intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); > > @@ -821,14 +821,14 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum > > intel_mst->pipe = pipe; > intel_encoder = &intel_mst->base; > - intel_mst->primary = intel_dig_port; > + intel_mst->primary = dig_port; > > drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, > DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); > > intel_encoder->type = INTEL_OUTPUT_DP_MST; > - intel_encoder->power_domain = intel_dig_port->base.power_domain; > - intel_encoder->port = intel_dig_port->base.port; > + intel_encoder->power_domain = dig_port->base.power_domain; > + intel_encoder->port = dig_port->base.port; > intel_encoder->cloneable = 0; > /* > * This is wrong, but broken userspace uses the intersection > @@ -855,29 +855,29 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum > } > > static bool > -intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) > +intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) > { > - struct intel_dp *intel_dp = &intel_dig_port->dp; > - struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); > + struct intel_dp *intel_dp = &dig_port->dp; > + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); > enum pipe pipe; > > for_each_pipe(dev_priv, pipe) > - intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(intel_dig_port, pipe); > + intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); > return true; > } > > int > -intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port) > +intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) > { > - return intel_dig_port->dp.active_mst_links; > + return dig_port->dp.active_mst_links; > } > > int > -intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) > +intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_dp *intel_dp = &intel_dig_port->dp; > - enum port port = intel_dig_port->base.port; > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_dp *intel_dp = &dig_port->dp; > + enum port port = dig_port->base.port; > int ret; > > if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) > @@ -892,7 +892,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_ba > intel_dp->mst_mgr.cbs = &mst_cbs; > > /* create encoders */ > - intel_dp_create_fake_mst_encoders(intel_dig_port); > + intel_dp_create_fake_mst_encoders(dig_port); > ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, > &intel_dp->aux, 16, 3, conn_base_id); > if (ret) > @@ -904,9 +904,9 @@ intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_ba > } > > void > -intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) > +intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) > { > - struct intel_dp *intel_dp = &intel_dig_port->dp; > + struct intel_dp *intel_dp = &dig_port->dp; > > if (!intel_dp->can_mst) > return; > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h > index 854724f68f09..6afda4e86b3c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h > @@ -11,9 +11,9 @@ > struct intel_digital_port; > struct intel_crtc_state; > > -int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); > -void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); > -int intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port); > +int intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_id); > +void intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port); > +int intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port); > bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state); > bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > index 399a7edb4568..7910522273b2 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c > @@ -650,9 +650,9 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, > bool uniq_trans_scale) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > - enum dpio_channel ch = vlv_dport_to_channel(dport); > + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); > enum pipe pipe = intel_crtc->pipe; > u32 val; > int i; > @@ -746,7 +746,7 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, > bool reset) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(encoder)); > + enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > enum pipe pipe = crtc->pipe; > u32 val; > @@ -789,10 +789,10 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, > void chv_phy_pre_pll_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - enum dpio_channel ch = vlv_dport_to_channel(dport); > + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); > enum pipe pipe = crtc->pipe; > unsigned int lane_mask = > intel_dp_unused_lane_mask(crtc_state->lane_count); > @@ -803,7 +803,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, > * Otherwise we can't even access the PLL. > */ > if (ch == DPIO_CH0 && pipe == PIPE_B) > - dport->release_cl2_override = > + dig_port->release_cl2_override = > !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); > > chv_phy_powergate_lanes(encoder, true, lane_mask); > @@ -870,10 +870,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > - struct intel_digital_port *dport = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - enum dpio_channel ch = vlv_dport_to_channel(dport); > + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); > enum pipe pipe = crtc->pipe; > int data, i, stagger; > u32 val; > @@ -948,12 +948,12 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, > > void chv_phy_release_cl2_override(struct intel_encoder *encoder) > { > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > - if (dport->release_cl2_override) { > + if (dig_port->release_cl2_override) { > chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); > - dport->release_cl2_override = false; > + dig_port->release_cl2_override = false; > } > } > > @@ -997,8 +997,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > - enum dpio_channel port = vlv_dport_to_channel(dport); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); > enum pipe pipe = intel_crtc->pipe; > > vlv_dpio_get(dev_priv); > @@ -1022,10 +1022,10 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, > void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - enum dpio_channel port = vlv_dport_to_channel(dport); > + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); > enum pipe pipe = crtc->pipe; > > /* Program Tx lane resets to default */ > @@ -1052,10 +1052,10 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > - struct intel_digital_port *dport = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - enum dpio_channel port = vlv_dport_to_channel(dport); > + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); > enum pipe pipe = crtc->pipe; > u32 val; > > @@ -1081,10 +1081,10 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, > void vlv_phy_reset_lanes(struct intel_encoder *encoder, > const struct intel_crtc_state *old_crtc_state) > { > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); > - enum dpio_channel port = vlv_dport_to_channel(dport); > + enum dpio_channel port = vlv_dig_port_to_channel(dig_port); > enum pipe pipe = crtc->pipe; > > vlv_dpio_get(dev_priv); > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 815b054bb167..1b6dadfce4eb 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -40,15 +40,15 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv) > } > > static > -int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, > +int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, > const struct intel_hdcp_shim *shim, u8 *bksv) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > int ret, i, tries = 2; > > /* HDCP spec states that we must retry the bksv if it is invalid */ > for (i = 0; i < tries; i++) { > - ret = shim->read_bksv(intel_dig_port, bksv); > + ret = shim->read_bksv(dig_port, bksv); > if (ret) > return ret; > if (intel_hdcp_is_ksv_valid(bksv)) > @@ -65,7 +65,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, > /* Is HDCP1.4 capable on Platform and Sink */ > bool intel_hdcp_capable(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > const struct intel_hdcp_shim *shim = connector->hdcp.shim; > bool capable = false; > u8 bksv[5]; > @@ -74,9 +74,9 @@ bool intel_hdcp_capable(struct intel_connector *connector) > return capable; > > if (shim->hdcp_capable) { > - shim->hdcp_capable(intel_dig_port, &capable); > + shim->hdcp_capable(dig_port, &capable); > } else { > - if (!intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv)) > + if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) > capable = true; > } > > @@ -86,7 +86,7 @@ bool intel_hdcp_capable(struct intel_connector *connector) > /* Is HDCP2.2 capable on Platform and Sink */ > bool intel_hdcp2_capable(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > bool capable = false; > @@ -104,7 +104,7 @@ bool intel_hdcp2_capable(struct intel_connector *connector) > mutex_unlock(&dev_priv->hdcp_comp_mutex); > > /* Sink's capability for HDCP2.2 */ > - hdcp->shim->hdcp_2_2_capable(intel_dig_port, &capable); > + hdcp->shim->hdcp_2_2_capable(dig_port, &capable); > > return capable; > } > @@ -125,14 +125,14 @@ static bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv, > LINK_ENCRYPTION_STATUS; > } > > -static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port, > +static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, > const struct intel_hdcp_shim *shim) > { > int ret, read_ret; > bool ksv_ready; > > /* Poll for ksv list ready (spec says max time allowed is 5s) */ > - ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port, > + ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, > &ksv_ready), > read_ret || ksv_ready, 5 * 1000 * 1000, 1000, > 100 * 1000); > @@ -300,16 +300,16 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, > const struct intel_hdcp_shim *shim, > u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > u32 vprime, sha_text, sha_leftovers, rep_ctl; > int ret, i, j, sha_idx; > > /* Process V' values from the receiver */ > for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { > - ret = shim->read_v_prime_part(intel_dig_port, i, &vprime); > + ret = shim->read_v_prime_part(dig_port, i, &vprime); > if (ret) > return ret; > intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime); > @@ -528,20 +528,20 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, > static > int intel_hdcp_auth_downstream(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > const struct intel_hdcp_shim *shim = connector->hdcp.shim; > u8 bstatus[2], num_downstream, *ksv_fifo; > int ret, i, tries = 3; > > - ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim); > + ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); > if (ret) { > drm_dbg_kms(&dev_priv->drm, > "KSV list failed to become ready (%d)\n", ret); > return ret; > } > > - ret = shim->read_bstatus(intel_dig_port, bstatus); > + ret = shim->read_bstatus(dig_port, bstatus); > if (ret) > return ret; > > @@ -571,7 +571,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) > return -ENOMEM; > } > > - ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo); > + ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); > if (ret) > goto err; > > @@ -611,12 +611,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) > /* Implements Part 1 of the HDCP authorization procedure */ > static int intel_hdcp_auth(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > const struct intel_hdcp_shim *shim = hdcp->shim; > enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > unsigned long r0_prime_gen_start; > int ret, i, tries = 2; > union { > @@ -640,7 +640,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) > * displays, this is not necessary. > */ > if (shim->hdcp_capable) { > - ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable); > + ret = shim->hdcp_capable(dig_port, &hdcp_capable); > if (ret) > return ret; > if (!hdcp_capable) { > @@ -670,7 +670,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) > HDCP_ANLO(dev_priv, cpu_transcoder, port)); > an.reg[1] = intel_de_read(dev_priv, > HDCP_ANHI(dev_priv, cpu_transcoder, port)); > - ret = shim->write_an_aksv(intel_dig_port, an.shim); > + ret = shim->write_an_aksv(dig_port, an.shim); > if (ret) > return ret; > > @@ -678,7 +678,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) > > memset(&bksv, 0, sizeof(bksv)); > > - ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim); > + ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); > if (ret < 0) > return ret; > > @@ -692,14 +692,14 @@ static int intel_hdcp_auth(struct intel_connector *connector) > intel_de_write(dev_priv, HDCP_BKSVHI(dev_priv, cpu_transcoder, port), > bksv.reg[1]); > > - ret = shim->repeater_present(intel_dig_port, &repeater_present); > + ret = shim->repeater_present(dig_port, &repeater_present); > if (ret) > return ret; > if (repeater_present) > intel_de_write(dev_priv, HDCP_REP_CTL, > intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port)); > > - ret = shim->toggle_signalling(intel_dig_port, true); > + ret = shim->toggle_signalling(dig_port, true); > if (ret) > return ret; > > @@ -732,7 +732,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) > */ > for (i = 0; i < tries; i++) { > ri.reg = 0; > - ret = shim->read_ri_prime(intel_dig_port, ri.shim); > + ret = shim->read_ri_prime(dig_port, ri.shim); > if (ret) > return ret; > intel_de_write(dev_priv, > @@ -776,10 +776,10 @@ static int intel_hdcp_auth(struct intel_connector *connector) > > static int _intel_hdcp_disable(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > enum transcoder cpu_transcoder = hdcp->cpu_transcoder; > int ret; > > @@ -796,7 +796,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) > return -ETIMEDOUT; > } > > - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); > + ret = hdcp->shim->toggle_signalling(dig_port, false); > if (ret) { > drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n"); > return ret; > @@ -859,10 +859,10 @@ static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) > /* Implements Part 3 of the HDCP authorization procedure */ > static int intel_hdcp_check_link(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > enum transcoder cpu_transcoder; > int ret = 0; > > @@ -888,7 +888,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) > goto out; > } > > - if (hdcp->shim->check_link(intel_dig_port)) { > + if (hdcp->shim->check_link(dig_port)) { > if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { > hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; > schedule_work(&hdcp->prop_work); > @@ -1242,7 +1242,7 @@ static int hdcp2_deauthenticate_port(struct intel_connector *connector) > /* Authentication flow starts from here */ > static int hdcp2_authentication_key_exchange(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > union { > @@ -1264,12 +1264,12 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) > if (ret < 0) > return ret; > > - ret = shim->write_2_2_msg(intel_dig_port, &msgs.ake_init, > + ret = shim->write_2_2_msg(dig_port, &msgs.ake_init, > sizeof(msgs.ake_init)); > if (ret < 0) > return ret; > > - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_CERT, > + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_CERT, > &msgs.send_cert, sizeof(msgs.send_cert)); > if (ret < 0) > return ret; > @@ -1298,11 +1298,11 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) > if (ret < 0) > return ret; > > - ret = shim->write_2_2_msg(intel_dig_port, &msgs.no_stored_km, size); > + ret = shim->write_2_2_msg(dig_port, &msgs.no_stored_km, size); > if (ret < 0) > return ret; > > - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_HPRIME, > + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_AKE_SEND_HPRIME, > &msgs.send_hprime, sizeof(msgs.send_hprime)); > if (ret < 0) > return ret; > @@ -1313,7 +1313,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) > > if (!hdcp->is_paired) { > /* Pairing is required */ > - ret = shim->read_2_2_msg(intel_dig_port, > + ret = shim->read_2_2_msg(dig_port, > HDCP_2_2_AKE_SEND_PAIRING_INFO, > &msgs.pairing_info, > sizeof(msgs.pairing_info)); > @@ -1331,7 +1331,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) > > static int hdcp2_locality_check(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct intel_hdcp *hdcp = &connector->hdcp; > union { > struct hdcp2_lc_init lc_init; > @@ -1345,12 +1345,12 @@ static int hdcp2_locality_check(struct intel_connector *connector) > if (ret < 0) > continue; > > - ret = shim->write_2_2_msg(intel_dig_port, &msgs.lc_init, > + ret = shim->write_2_2_msg(dig_port, &msgs.lc_init, > sizeof(msgs.lc_init)); > if (ret < 0) > continue; > > - ret = shim->read_2_2_msg(intel_dig_port, > + ret = shim->read_2_2_msg(dig_port, > HDCP_2_2_LC_SEND_LPRIME, > &msgs.send_lprime, > sizeof(msgs.send_lprime)); > @@ -1367,7 +1367,7 @@ static int hdcp2_locality_check(struct intel_connector *connector) > > static int hdcp2_session_key_exchange(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct intel_hdcp *hdcp = &connector->hdcp; > struct hdcp2_ske_send_eks send_eks; > int ret; > @@ -1376,7 +1376,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) > if (ret < 0) > return ret; > > - ret = hdcp->shim->write_2_2_msg(intel_dig_port, &send_eks, > + ret = hdcp->shim->write_2_2_msg(dig_port, &send_eks, > sizeof(send_eks)); > if (ret < 0) > return ret; > @@ -1387,7 +1387,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) > static > int hdcp2_propagate_stream_management_info(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *i915 = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > union { > @@ -1409,12 +1409,12 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector) > msgs.stream_manage.streams[0].stream_type = hdcp->content_type; > > /* Send it to Repeater */ > - ret = shim->write_2_2_msg(intel_dig_port, &msgs.stream_manage, > + ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage, > sizeof(msgs.stream_manage)); > if (ret < 0) > return ret; > > - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY, > + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_STREAM_READY, > &msgs.stream_ready, sizeof(msgs.stream_ready)); > if (ret < 0) > return ret; > @@ -1439,7 +1439,7 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector) > static > int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > union { > @@ -1451,7 +1451,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) > u8 *rx_info; > int ret; > > - ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, > + ret = shim->read_2_2_msg(dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, > &msgs.recvid_list, sizeof(msgs.recvid_list)); > if (ret < 0) > return ret; > @@ -1496,7 +1496,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) > return ret; > > hdcp->seq_num_v = seq_num_v; > - ret = shim->write_2_2_msg(intel_dig_port, &msgs.rep_ack, > + ret = shim->write_2_2_msg(dig_port, &msgs.rep_ack, > sizeof(msgs.rep_ack)); > if (ret < 0) > return ret; > @@ -1517,7 +1517,7 @@ static int hdcp2_authenticate_repeater(struct intel_connector *connector) > > static int hdcp2_authenticate_sink(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *i915 = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > const struct intel_hdcp_shim *shim = hdcp->shim; > @@ -1543,7 +1543,7 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) > } > > if (shim->config_stream_type) { > - ret = shim->config_stream_type(intel_dig_port, > + ret = shim->config_stream_type(dig_port, > hdcp->is_repeater, > hdcp->content_type); > if (ret < 0) > @@ -1569,10 +1569,10 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) > > static int hdcp2_enable_encryption(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > enum transcoder cpu_transcoder = hdcp->cpu_transcoder; > int ret; > > @@ -1580,7 +1580,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) > intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & > LINK_ENCRYPTION_STATUS); > if (hdcp->shim->toggle_signalling) { > - ret = hdcp->shim->toggle_signalling(intel_dig_port, true); > + ret = hdcp->shim->toggle_signalling(dig_port, true); > if (ret) { > drm_err(&dev_priv->drm, > "Failed to enable HDCP signalling. %d\n", > @@ -1608,10 +1608,10 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) > > static int hdcp2_disable_encryption(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > enum transcoder cpu_transcoder = hdcp->cpu_transcoder; > int ret; > > @@ -1630,7 +1630,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) > drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout"); > > if (hdcp->shim->toggle_signalling) { > - ret = hdcp->shim->toggle_signalling(intel_dig_port, false); > + ret = hdcp->shim->toggle_signalling(dig_port, false); > if (ret) { > drm_err(&dev_priv->drm, > "Failed to disable HDCP signalling. %d\n", > @@ -1723,10 +1723,10 @@ static int _intel_hdcp2_disable(struct intel_connector *connector) > /* Implements the Link Integrity Check for HDCP2.2 */ > static int intel_hdcp2_check_link(struct intel_connector *connector) > { > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > - enum port port = intel_dig_port->base.port; > + enum port port = dig_port->base.port; > enum transcoder cpu_transcoder; > int ret = 0; > > @@ -1751,7 +1751,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) > goto out; > } > > - ret = hdcp->shim->check_2_2_link(intel_dig_port); > + ret = hdcp->shim->check_2_2_link(dig_port); > if (ret == HDCP_LINK_PROTECTED) { > if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { > hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c > index a31a98d26882..414a0de2aab3 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -88,10 +88,10 @@ assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, > > struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) > { > - struct intel_digital_port *intel_dig_port = > + struct intel_digital_port *dig_port = > container_of(&encoder->base, struct intel_digital_port, > base.base); > - return &intel_dig_port->hdmi; > + return &dig_port->hdmi; > } > > static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) > @@ -660,7 +660,7 @@ static void intel_write_infoframe(struct intel_encoder *encoder, > enum hdmi_infoframe_type type, > const union hdmi_infoframe *frame) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > u8 buffer[VIDEO_DIP_DATA_SIZE]; > ssize_t len; > > @@ -681,7 +681,7 @@ static void intel_write_infoframe(struct intel_encoder *encoder, > buffer[3] = 0; > len++; > > - intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); > + dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); > } > > void intel_read_infoframe(struct intel_encoder *encoder, > @@ -689,7 +689,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, > enum hdmi_infoframe_type type, > union hdmi_infoframe *frame) > { > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > u8 buffer[VIDEO_DIP_DATA_SIZE]; > int ret; > > @@ -697,7 +697,7 @@ void intel_read_infoframe(struct intel_encoder *encoder, > intel_hdmi_infoframe_enable(type)) == 0) > return; > > - intel_dig_port->read_infoframe(encoder, crtc_state, > + dig_port->read_infoframe(encoder, crtc_state, > type, buffer, sizeof(buffer)); > > /* Fill the 'hole' (see big comment above) at position 3 */ > @@ -872,8 +872,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, > const struct drm_connector_state *conn_state) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; > i915_reg_t reg = VIDEO_DIP_CTL; > u32 val = intel_de_read(dev_priv, reg); > u32 port = VIDEO_DIP_PORT(encoder->port); > @@ -1057,8 +1057,8 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); > - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); > - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; > i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); > u32 val = intel_de_read(dev_priv, reg); > u32 port = VIDEO_DIP_PORT(encoder->port); > @@ -1275,11 +1275,11 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) > adapter, enable); > } > > -static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, > +static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, > unsigned int offset, void *buffer, size_t size) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_hdmi *hdmi = &dig_port->hdmi; > struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, > hdmi->ddc_bus); > int ret; > @@ -1304,11 +1304,11 @@ static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, > return ret >= 0 ? -EIO : ret; > } > > -static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, > +static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, > unsigned int offset, void *buffer, size_t size) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_hdmi *hdmi = &dig_port->hdmi; > struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, > hdmi->ddc_bus); > int ret; > @@ -1338,16 +1338,16 @@ static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, > u8 *an) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_hdmi *hdmi = &dig_port->hdmi; > struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, > hdmi->ddc_bus); > int ret; > > - ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, > + ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, > DRM_HDCP_AN_LEN); > if (ret) { > drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", > @@ -1363,13 +1363,13 @@ int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, > return 0; > } > > -static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, > +static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, > u8 *bksv) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > int ret; > - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, > + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, > DRM_HDCP_KSV_LEN); > if (ret) > drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", > @@ -1378,13 +1378,13 @@ static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, > u8 *bstatus) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > int ret; > - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, > + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, > bstatus, DRM_HDCP_BSTATUS_LEN); > if (ret) > drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", > @@ -1393,14 +1393,14 @@ int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, > bool *repeater_present) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > int ret; > u8 val; > > - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); > + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); > if (ret) { > drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", > ret); > @@ -1411,13 +1411,13 @@ int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, > u8 *ri_prime) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > > int ret; > - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, > + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, > ri_prime, DRM_HDCP_RI_LEN); > if (ret) > drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", > @@ -1426,14 +1426,14 @@ int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, > bool *ksv_ready) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > int ret; > u8 val; > > - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); > + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); > if (ret) { > drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", > ret); > @@ -1444,12 +1444,12 @@ int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, > int num_downstream, u8 *ksv_fifo) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > int ret; > - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, > + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, > ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); > if (ret) { > drm_dbg_kms(&i915->drm, > @@ -1460,16 +1460,16 @@ int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, > int i, u32 *part) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > int ret; > > if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) > return -EINVAL; > > - ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), > + ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), > part, DRM_HDCP_V_PRIME_PART_LEN); > if (ret) > drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", > @@ -1480,7 +1480,7 @@ int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, > static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) > { > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > - struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); > + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); > struct drm_crtc *crtc = connector->base.state->crtc; > struct intel_crtc *intel_crtc = container_of(crtc, > struct intel_crtc, base); > @@ -1494,13 +1494,13 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) > usleep_range(25, 50); > } > > - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); > + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, false); > if (ret) { > drm_err(&dev_priv->drm, > "Disable HDCP signalling failed (%d)\n", ret); > return ret; > } > - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); > + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, true); > if (ret) { > drm_err(&dev_priv->drm, > "Enable HDCP signalling failed (%d)\n", ret); > @@ -1511,10 +1511,10 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) > } > > static > -int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, > bool enable) > { > - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; > + struct intel_hdmi *hdmi = &dig_port->hdmi; > struct intel_connector *connector = hdmi->attached_connector; > struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > int ret; > @@ -1522,7 +1522,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, > if (!enable) > usleep_range(6, 60); /* Bspec says >= 6us */ > > - ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); > + ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, enable); > if (ret) { > drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", > enable ? "Enable" : "Disable", ret); > @@ -1540,12 +1540,12 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, > } > > static > -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) > +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > struct intel_connector *connector = > - intel_dig_port->hdmi.attached_connector; > - enum port port = intel_dig_port->base.port; > + dig_port->hdmi.attached_connector; > + enum port port = dig_port->base.port; > enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; > int ret; > union { > @@ -1553,7 +1553,7 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) > u8 shim[DRM_HDCP_RI_LEN]; > } ri; > > - ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); > + ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); > if (ret) > return false; > > @@ -1586,10 +1586,10 @@ static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { > }; > > static > -int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, > u8 *rx_status) > { > - return intel_hdmi_hdcp_read(intel_dig_port, > + return intel_hdmi_hdcp_read(dig_port, > HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, > rx_status, > HDCP_2_2_HDMI_RXSTATUS_LEN); > @@ -1615,15 +1615,15 @@ static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) > } > > static int > -hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, > +hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, > u8 msg_id, bool *msg_ready, > ssize_t *msg_sz) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; > int ret; > > - ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); > + ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); > if (ret < 0) { > drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", > ret); > @@ -1643,10 +1643,10 @@ hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, > } > > static ssize_t > -intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, > +intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, > u8 msg_id, bool paired) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > bool msg_ready = false; > int timeout, ret; > ssize_t msg_sz = 0; > @@ -1655,7 +1655,7 @@ intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, > if (timeout < 0) > return timeout; > > - ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, > + ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, > msg_id, &msg_ready, > &msg_sz), > !ret && msg_ready && msg_sz, timeout * 1000, > @@ -1668,26 +1668,26 @@ intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, > void *buf, size_t size) > { > unsigned int offset; > > offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; > - return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); > + return intel_hdmi_hdcp_write(dig_port, offset, buf, size); > } > > static > -int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, > u8 msg_id, void *buf, size_t size) > { > - struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); > - struct intel_hdmi *hdmi = &intel_dig_port->hdmi; > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + struct intel_hdmi *hdmi = &dig_port->hdmi; > struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; > unsigned int offset; > ssize_t ret; > > - ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, > + ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, > hdcp->is_paired); > if (ret < 0) > return ret; > @@ -1704,7 +1704,7 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > } > > offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; > - ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); > + ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); > if (ret) > drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", > msg_id, ret); > @@ -1713,12 +1713,12 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, > } > > static > -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) > +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port) > { > u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; > int ret; > > - ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); > + ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); > if (ret) > return ret; > > @@ -1735,14 +1735,14 @@ int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) > } > > static > -int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, > +int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, > bool *capable) > { > u8 hdcp2_version; > int ret; > > *capable = false; > - ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, > + ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, > &hdcp2_version, sizeof(hdcp2_version)); > if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) > *capable = true; > @@ -2050,7 +2050,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, > struct drm_device *dev = encoder->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); > - struct intel_digital_port *intel_dig_port = > + struct intel_digital_port *dig_port = > hdmi_to_dig_port(intel_hdmi); > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); > u32 temp; > @@ -2094,7 +2094,7 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, > intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); > } > > - intel_dig_port->set_infoframes(encoder, > + dig_port->set_infoframes(encoder, > false, > old_crtc_state, old_conn_state); > > @@ -2709,12 +2709,12 @@ static void intel_hdmi_pre_enable(struct intel_atomic_state *state, > const struct intel_crtc_state *pipe_config, > const struct drm_connector_state *conn_state) > { > - struct intel_digital_port *intel_dig_port = > + struct intel_digital_port *dig_port = > enc_to_dig_port(encoder); > > intel_hdmi_prepare(encoder, pipe_config); > > - intel_dig_port->set_infoframes(encoder, > + dig_port->set_infoframes(encoder, > pipe_config->has_infoframe, > pipe_config, conn_state); > } > @@ -2724,7 +2724,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, > const struct intel_crtc_state *pipe_config, > const struct drm_connector_state *conn_state) > { > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > vlv_phy_pre_encoder_enable(encoder, pipe_config); > @@ -2733,13 +2733,13 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, > vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, > 0x2b247878); > > - dport->set_infoframes(encoder, > + dig_port->set_infoframes(encoder, > pipe_config->has_infoframe, > pipe_config, conn_state); > > g4x_enable_hdmi(state, encoder, pipe_config, conn_state); > > - vlv_wait_port_ready(dev_priv, dport, 0x0); > + vlv_wait_port_ready(dev_priv, dig_port, 0x0); > } > > static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, > @@ -2800,7 +2800,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, > const struct intel_crtc_state *pipe_config, > const struct drm_connector_state *conn_state) > { > - struct intel_digital_port *dport = enc_to_dig_port(encoder); > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > struct drm_device *dev = encoder->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > > @@ -2810,13 +2810,13 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, > /* Use 800mV-0dB */ > chv_set_phy_signal_level(encoder, 128, 102, false); > > - dport->set_infoframes(encoder, > + dig_port->set_infoframes(encoder, > pipe_config->has_infoframe, > pipe_config, conn_state); > > g4x_enable_hdmi(state, encoder, pipe_config, conn_state); > > - vlv_wait_port_ready(dev_priv, dport, 0x0); > + vlv_wait_port_ready(dev_priv, dig_port, 0x0); > > /* Second common lane will stay alive on its own now */ > chv_phy_release_cl2_override(encoder); > @@ -2910,7 +2910,7 @@ static void > intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) > { > struct drm_i915_private *dev_priv = to_i915(connector->dev); > - struct intel_digital_port *intel_dig_port = > + struct intel_digital_port *dig_port = > hdmi_to_dig_port(intel_hdmi); > > intel_attach_force_audio_property(connector); > @@ -2922,7 +2922,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c > * ToDo: This needs to be extended for LSPCON implementation > * as well. Will be implemented separately. > */ > - if (!intel_dig_port->lspcon.active) > + if (!dig_port->lspcon.active) > intel_attach_colorspace_property(connector); > > drm_connector_attach_content_type_property(connector); > @@ -3159,52 +3159,52 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) > return ddc_pin; > } > > -void intel_infoframe_init(struct intel_digital_port *intel_dig_port) > +void intel_infoframe_init(struct intel_digital_port *dig_port) > { > struct drm_i915_private *dev_priv = > - to_i915(intel_dig_port->base.base.dev); > + to_i915(dig_port->base.base.dev); > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > - intel_dig_port->write_infoframe = vlv_write_infoframe; > - intel_dig_port->read_infoframe = vlv_read_infoframe; > - intel_dig_port->set_infoframes = vlv_set_infoframes; > - intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; > + dig_port->write_infoframe = vlv_write_infoframe; > + dig_port->read_infoframe = vlv_read_infoframe; > + dig_port->set_infoframes = vlv_set_infoframes; > + dig_port->infoframes_enabled = vlv_infoframes_enabled; > } else if (IS_G4X(dev_priv)) { > - intel_dig_port->write_infoframe = g4x_write_infoframe; > - intel_dig_port->read_infoframe = g4x_read_infoframe; > - intel_dig_port->set_infoframes = g4x_set_infoframes; > - intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; > + dig_port->write_infoframe = g4x_write_infoframe; > + dig_port->read_infoframe = g4x_read_infoframe; > + dig_port->set_infoframes = g4x_set_infoframes; > + dig_port->infoframes_enabled = g4x_infoframes_enabled; > } else if (HAS_DDI(dev_priv)) { > - if (intel_dig_port->lspcon.active) { > - intel_dig_port->write_infoframe = lspcon_write_infoframe; > - intel_dig_port->read_infoframe = lspcon_read_infoframe; > - intel_dig_port->set_infoframes = lspcon_set_infoframes; > - intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; > + if (dig_port->lspcon.active) { > + dig_port->write_infoframe = lspcon_write_infoframe; > + dig_port->read_infoframe = lspcon_read_infoframe; > + dig_port->set_infoframes = lspcon_set_infoframes; > + dig_port->infoframes_enabled = lspcon_infoframes_enabled; > } else { > - intel_dig_port->write_infoframe = hsw_write_infoframe; > - intel_dig_port->read_infoframe = hsw_read_infoframe; > - intel_dig_port->set_infoframes = hsw_set_infoframes; > - intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; > + dig_port->write_infoframe = hsw_write_infoframe; > + dig_port->read_infoframe = hsw_read_infoframe; > + dig_port->set_infoframes = hsw_set_infoframes; > + dig_port->infoframes_enabled = hsw_infoframes_enabled; > } > } else if (HAS_PCH_IBX(dev_priv)) { > - intel_dig_port->write_infoframe = ibx_write_infoframe; > - intel_dig_port->read_infoframe = ibx_read_infoframe; > - intel_dig_port->set_infoframes = ibx_set_infoframes; > - intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; > + dig_port->write_infoframe = ibx_write_infoframe; > + dig_port->read_infoframe = ibx_read_infoframe; > + dig_port->set_infoframes = ibx_set_infoframes; > + dig_port->infoframes_enabled = ibx_infoframes_enabled; > } else { > - intel_dig_port->write_infoframe = cpt_write_infoframe; > - intel_dig_port->read_infoframe = cpt_read_infoframe; > - intel_dig_port->set_infoframes = cpt_set_infoframes; > - intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; > + dig_port->write_infoframe = cpt_write_infoframe; > + dig_port->read_infoframe = cpt_read_infoframe; > + dig_port->set_infoframes = cpt_set_infoframes; > + dig_port->infoframes_enabled = cpt_infoframes_enabled; > } > } > > -void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > +void intel_hdmi_init_connector(struct intel_digital_port *dig_port, > struct intel_connector *intel_connector) > { > struct drm_connector *connector = &intel_connector->base; > - struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; > - struct intel_encoder *intel_encoder = &intel_dig_port->base; > + struct intel_hdmi *intel_hdmi = &dig_port->hdmi; > + struct intel_encoder *intel_encoder = &dig_port->base; > struct drm_device *dev = intel_encoder->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > struct i2c_adapter *ddc; > @@ -3218,9 +3218,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) > return; > > - if (drm_WARN(dev, intel_dig_port->max_lanes < 4, > + if (drm_WARN(dev, dig_port->max_lanes < 4, > "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", > - intel_dig_port->max_lanes, intel_encoder->base.base.id, > + dig_port->max_lanes, intel_encoder->base.base.id, > intel_encoder->base.name)) > return; > > @@ -3309,21 +3309,21 @@ intel_hdmi_hotplug(struct intel_encoder *encoder, > void intel_hdmi_init(struct drm_i915_private *dev_priv, > i915_reg_t hdmi_reg, enum port port) > { > - struct intel_digital_port *intel_dig_port; > + struct intel_digital_port *dig_port; > struct intel_encoder *intel_encoder; > struct intel_connector *intel_connector; > > - intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); > - if (!intel_dig_port) > + dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); > + if (!dig_port) > return; > > intel_connector = intel_connector_alloc(); > if (!intel_connector) { > - kfree(intel_dig_port); > + kfree(dig_port); > return; > } > > - intel_encoder = &intel_dig_port->base; > + intel_encoder = &dig_port->base; > > drm_encoder_init(&dev_priv->drm, &intel_encoder->base, > &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, > @@ -3380,12 +3380,12 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, > if (IS_G4X(dev_priv)) > intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; > > - intel_dig_port->hdmi.hdmi_reg = hdmi_reg; > - intel_dig_port->dp.output_reg = INVALID_MMIO_REG; > - intel_dig_port->max_lanes = 4; > + dig_port->hdmi.hdmi_reg = hdmi_reg; > + dig_port->dp.output_reg = INVALID_MMIO_REG; > + dig_port->max_lanes = 4; > > - intel_infoframe_init(intel_dig_port); > + intel_infoframe_init(dig_port); > > - intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); > - intel_hdmi_init_connector(intel_dig_port, intel_connector); > + dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); > + intel_hdmi_init_connector(dig_port, intel_connector); > } > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h > index 8ff1f76a63df..213ff24befde 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.h > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h > @@ -25,7 +25,7 @@ enum port; > > void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg, > enum port port); > -void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > +void intel_hdmi_init_connector(struct intel_digital_port *dig_port, > struct intel_connector *intel_connector); > struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder); > int intel_hdmi_compute_config(struct intel_encoder *encoder, > @@ -36,7 +36,7 @@ bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, > bool high_tmds_clock_ratio, > bool scrambling); > void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable); > -void intel_infoframe_init(struct intel_digital_port *intel_dig_port); > +void intel_infoframe_init(struct intel_digital_port *dig_port); > u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state); > u32 intel_hdmi_infoframe_enable(unsigned int type); > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c > index 6ff7b226f0a1..b781bf469644 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > @@ -550,11 +550,11 @@ void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) > lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); > } > > -bool lspcon_init(struct intel_digital_port *intel_dig_port) > +bool lspcon_init(struct intel_digital_port *dig_port) > { > - struct intel_dp *dp = &intel_dig_port->dp; > - struct intel_lspcon *lspcon = &intel_dig_port->lspcon; > - struct drm_device *dev = intel_dig_port->base.base.dev; > + struct intel_dp *dp = &dig_port->dp; > + struct intel_lspcon *lspcon = &dig_port->lspcon; > + struct drm_device *dev = dig_port->base.base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > struct drm_connector *connector = &dp->attached_connector->base; > > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h > index 37cfddf8a9c5..1cffe8a42a08 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.h > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h > @@ -15,7 +15,7 @@ struct intel_digital_port; > struct intel_encoder; > struct intel_lspcon; > > -bool lspcon_init(struct intel_digital_port *intel_dig_port); > +bool lspcon_init(struct intel_digital_port *dig_port); > void lspcon_resume(struct intel_lspcon *lspcon); > void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); > void lspcon_write_infoframe(struct intel_encoder *encoder, > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 86bf7a76f93d..78762627a8ba 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -905,8 +905,8 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > const struct drm_connector_state *conn_state) > { > struct intel_dp *intel_dp = dev_priv->psr.dp; > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > - struct intel_encoder *encoder = &intel_dig_port->base; > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > + struct intel_encoder *encoder = &dig_port->base; > u32 val; > > drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index d145fe2bed81..c5735c365659 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -1045,7 +1045,7 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > - struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; > > @@ -1055,9 +1055,9 @@ static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, > /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ > drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg); > > - intel_dig_port->write_infoframe(encoder, crtc_state, > - DP_SDP_PPS, &dp_dsc_pps_sdp, > - sizeof(dp_dsc_pps_sdp)); > + dig_port->write_infoframe(encoder, crtc_state, > + DP_SDP_PPS, &dp_dsc_pps_sdp, > + sizeof(dp_dsc_pps_sdp)); > } > > void intel_dsc_enable(struct intel_encoder *encoder, > -- > 2.26.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From cai at lca.pw Tue Jun 23 22:29:58 2020 From: cai at lca.pw (Qian Cai) Date: Tue, 23 Jun 2020 18:29:58 -0400 Subject: [Intel-gfx] [PATCH] mm: Track mmu notifiers in fs_reclaim_acquire/release In-Reply-To: <CAKMK7uH90-k12KMHE0pWN6G_aCTr=YNhQsqoaAJC5FHygnf96g@mail.gmail.com> References: <CAKMK7uH90-k12KMHE0pWN6G_aCTr=YNhQsqoaAJC5FHygnf96g@mail.gmail.com> Message-ID: <CBC5DC63-241C-4291-8686-21CF758AC91B@lca.pw> > On Jun 23, 2020, at 6:13 PM, Daniel Vetter <daniel at ffwll.ch> wrote: > > Ok I tested this. I can't use your script to repro because > - I don't have a setup with xfs, and the splat points at an issue in xfs > - reproducing lockdep splats in shrinker callbacks is always a bit tricky What?s xfs setup are you talking about? This is simple xfs rootfs and then trigger swapping. Nothing tricky here as it hit on multiple machines within a few seconds on linux-next. > Summary: Everything is working as expected, there's no change in the > lockdep annotations. > I really think the problem is that either your testcase doesn't hit > the issue reliably enough, or that you're not actually testing the > same kernels and there's some other changes (xfs most likely, but > really it could be anywhere) which is causing this regression. I'm > rather convinced now after this test that it's not my stuff. Well, the memory pressure workloads have been running for years on daily linux-next builds and never saw this one happened once. Also, the reverting is ONLY to revert your patch on the top of linux-next will stop the splat, so there is no not testing the same kernel at all. From shy828301 at gmail.com Wed Jun 24 21:02:07 2020 From: shy828301 at gmail.com (Yang Shi) Date: Wed, 24 Jun 2020 14:02:07 -0700 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <CAHbLzkoy2kz7yirch7t9ruzJjNTyCCZHJFZst7OEz_DdmQyaaA@mail.gmail.com> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200624192116.GO6578@ziepe.ca> <CAHbLzkoy2kz7yirch7t9ruzJjNTyCCZHJFZst7OEz_DdmQyaaA@mail.gmail.com> Message-ID: <CAHbLzkomoxKE73SgZvRD0cLELBtx71jx+g07zZ5YMajUPPcRLw@mail.gmail.com> On Wed, Jun 24, 2020 at 1:23 PM Yang Shi <shy828301 at gmail.com> wrote: > > On Wed, Jun 24, 2020 at 12:21 PM Jason Gunthorpe <jgg at ziepe.ca> wrote: > > > > On Wed, Jun 24, 2020 at 08:14:17PM +0100, Chris Wilson wrote: > > > A general rule of thumb is that shrinkers should be fast and effective. > > > They are called from direct reclaim at the most incovenient of times when > > > the caller is waiting for a page. If we attempt to reclaim a page being > > > pinned for active dma [pin_user_pages()], we will incur far greater > > > latency than a normal anonymous page mapped multiple times. Worse the > > > page may be in use indefinitely by the HW and unable to be reclaimed > > > in a timely manner. > > > > A pinned page can't be migrated, discarded or swapped by definition - > > it would cause data corruption. > > > > So, how do things even get here and/or work today at all? I think the > > explanation is missing something important. > > The __remove_mapping() will try to freeze page count if the count is > expected otherwise just not discard the page. I'm not quite sure why > the check is done that late, my wild guess is to check the refcount at > the last minute so there might be a chance the pin gets released right > before it. > > But I noticed a bug in __remove_ampping() for THP since THP's dma > pinned count is recorded in the tail page's hpage_pinned_refcount > instead of refcount. So, the refcount freeze might be successful for > pinned THP. Chris's patch could solve this issue too, but I'm not This bug is not valid. I just realized try_grab_page() would increase both refcount and hpage_pinned_refcount. > sure if it is worth backing earlier once dma pinned page is met. If it > is worth, the follow-up question is why not just skip such page in > scan phase? > > > > > Jason > > From jhubbard at nvidia.com Thu Jun 25 00:11:30 2020 From: jhubbard at nvidia.com (John Hubbard) Date: Wed, 24 Jun 2020 17:11:30 -0700 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200624232047.GP6578@ziepe.ca> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200624192116.GO6578@ziepe.ca> <44708b2e-479f-7d58-fe01-29cfd6c70bdb@nvidia.com> <20200624232047.GP6578@ziepe.ca> Message-ID: <887ac706-65f0-3089-b51b-47aabf7d3847@nvidia.com> On 2020-06-24 16:20, Jason Gunthorpe wrote: ... > I think Yang explained it - the page is removed from the mappings but > freeing it does not happen because page_ref_freeze() does not succeed > due to the pin. > > Presumably the mappings can reconnect to the same physical page if > it is re-faulted to avoid any data corruption. > > So, the issue here is the mappings are trashed while the page remains > - and trashing the mapping triggers a mmu notifier which upsets i915. > >> What's less clear is why the comment and the commit description >> only talk about reclaim, when there are additional things that call >> try_to_unmap(), including: >> >> migrate_vma_unmap() >> split_huge_page_to_list() --> unmap_page() > > It looks like the same unmap first then abort if the refcount is still > elevated design as shrink_page_list() ? Yes. I was just wondering why the documentation here seems to ignore the other, non-reclaim cases. Anyway, though... > >> I do like this code change, though. And I *think* it's actually safe to >> do this, as it stays away from writeback or other filesystem activity. >> But let me double check that, in case I'm forgetting something. ...OK, I've checked, and I like it a little bit less now. Mainly for structural reasons, though. I think it would work correctly. But here's a concern: try_to_unmap() should only fail to unmap if there is a reason to not unmap. Having a page be pinned for dma is a reason to not *free* a page, and it's also a reason to be careful about writeback and page buffers for writeback and such. But I'm not sure that it's a reason to fail to remove mappings. True, most (all?) of the reasons that we remove mappings, generally are for things that are not allowed while a page is dma-pinned...at least, today. But still, there's nothing fundamental about a mapping that should prevent it from coming or going while a page is undergoing dma. So, it's merely a convenient, now-misnamed location in the call stack to fail out. That's not great. It might be better, as Jason hints at below, to fail out a little earlier, instead. That would lead to a more places to call page_maybe_dma_pinned(), but that's not a real problem, because it's still a small number of places. After writing all of that...I don't feel strongly about it, because TTU is kind of synonymous with "I'm about to do a dma-pin-unfriendly operation". Maybe some of the more experienced fs or mm people have strong opinions one way or the other? > > It would be nice to have an explanation why it is OK now to change > it.. Yes. Definitely good to explain that in the commit log. I think it's triggered by the existence of page_maybe_dma_pinned(). Until that was added, figuring out if dma was involved required basically just guesswork. Now we have a way to guess much more accurately. :) > > I don't know, but could it be that try_to_unmap() has to be done > before checking the refcount as each mapping is included in the > refcount? ie we couldn't know a DMA pin was active in advance? > > Now that we have your pin stuff we can detect a DMA pin without doing > all the unmaps? > Once something calls pin_user_page*(), then the pages will be marked as dma-pinned, yes. So no, there is no need to wait until try_to_unmap() to find out. A final note: depending on where page_maybe_dma_pinned() ends up getting called, this might prevent a fair number of the problems that Jan originally reported [1], and that I also reported separately! Well, not all of the problems, and only after the filesystems get converted to call pin_user_pages() (working on that next), but...I think it would actually avoid the crash our customer reported back in early 2018. Even though we don't have the full file lease + pin_user_pages() solution in place. That's because reclaim is what triggers the problems that we saw. And with this patch, we bail out of reclaim early. [1] https://www.spinics.net/lists/linux-mm/msg142700.html thanks, -- John Hubbard NVIDIA From jhubbard at nvidia.com Wed Jun 24 20:47:23 2020 From: jhubbard at nvidia.com (John Hubbard) Date: Wed, 24 Jun 2020 13:47:23 -0700 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200624192116.GO6578@ziepe.ca> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200624192116.GO6578@ziepe.ca> Message-ID: <44708b2e-479f-7d58-fe01-29cfd6c70bdb@nvidia.com> On 2020-06-24 12:21, Jason Gunthorpe wrote: > On Wed, Jun 24, 2020 at 08:14:17PM +0100, Chris Wilson wrote: >> A general rule of thumb is that shrinkers should be fast and effective. >> They are called from direct reclaim at the most incovenient of times when >> the caller is waiting for a page. If we attempt to reclaim a page being >> pinned for active dma [pin_user_pages()], we will incur far greater >> latency than a normal anonymous page mapped multiple times. Worse the >> page may be in use indefinitely by the HW and unable to be reclaimed >> in a timely manner. > > A pinned page can't be migrated, discarded or swapped by definition - > it would cause data corruption. > > So, how do things even get here and/or work today at all? I think the > explanation is missing something important. > Well, those activities generally try to unmap the page, and have to be prepared to deal with failure to unmap. From my reading, it seemed very clear. What's less clear is why the comment and the commit description only talk about reclaim, when there are additional things that call try_to_unmap(), including: migrate_vma_unmap() split_huge_page_to_list() --> unmap_page() I do like this code change, though. And I *think* it's actually safe to do this, as it stays away from writeback or other filesystem activity. But let me double check that, in case I'm forgetting something. thanks, -- John Hubbard NVIDIA From ckoenig.leichtzumerken at gmail.com Thu Jun 25 14:02:41 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Thu, 25 Jun 2020 16:02:41 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159309140216.31486.2359580281725596670@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> Message-ID: <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> Am 25.06.20 um 15:23 schrieb Chris Wilson: > Quoting Christian K?nig (2020-06-25 13:59:16) >> Am 25.06.20 um 14:48 schrieb Chris Wilson: >>> Quoting Christian K?nig (2020-06-25 09:11:35) >>>> Am 24.06.20 um 22:18 schrieb Chris Wilson: >>>>> Quoting Dave Airlie (2020-06-24 20:04:02) >>>>>> On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: >>>>>>> Quoting Dave Airlie (2020-06-23 22:01:24) >>>>>>>> On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: >>>>>>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) >>>>>>>>>> Hi, Chris! >>>>>>>>>> >>>>>>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: >>>>>>>>>>> In order to actually handle eviction and what not, we need to process >>>>>>>>>>> all the objects together under a common lock, reservation_ww_class. As >>>>>>>>>>> such, do a memory reservation pass after looking up the object/vma, >>>>>>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>>>>>>>>>> flushing and ofc execution]. >>>>>>>>>>> >>>>>>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>>>>>>>>>> --- >>>>>>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>>>>>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) >>>>>>>>>>> >>>>>>>>>> Which tree is this against? The series doesn't apply cleanly against >>>>>>>>>> drm-tip? >>>>>>>>> It's continuing on from the scheduler patches, the bug fixes and the >>>>>>>>> iris-deferred-fence work. I thought throwing all of those old patches >>>>>>>>> into the pile would have been distracting. >>>>>>>>> >>>>>>>>>> ... >>>>>>>>>> >>>>>>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>>>>>>>>>> +{ >>>>>>>>>>> + const u64 idx = eb->context->timeline->fence_context; >>>>>>>>>>> + struct ww_acquire_ctx acquire; >>>>>>>>>>> + struct eb_vma *ev; >>>>>>>>>>> + int err; >>>>>>>>>>> + >>>>>>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); >>>>>>>>>>> + if (!eb->mm_fence) >>>>>>>>>>> + return -ENOMEM; >>>>>>>>>> Where are the proxy fence functions defined? >>>>>>>>> In dma-fence-proxy.c ;) >>>>>>>> The dma-fence-proxy that Christian NAKed before? >>>>>>> I do not have an email from Christian about dma-fence-proxy in the last >>>>>>> 3 years it has been on the list. >>>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fdri-devel%2Faeb0373d-0583-d922-3b73-93668c27d177%40amd.com%2F&data=02%7C01%7Cchristian.koenig%40amd.com%7Ccb060e358d844784815708d819061868%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637286861292346372&sdata=DlHistmqPi%2BtwdcT%2FycrtRpoLGZ6xcBD%2FkPvVZcQ2YQ%3D&reserved=0 >>>>> Darn, I skimmed the thread title and thought it was just about the >>>>> timelines. >>>>> >>>>>> I'm assuming this was about patch 8 there which to me looks like proxy >>>>>> fences but maybe by threading is off reading that. >>>>> The deadlocks are easy to resolve. The fence is either signaled normally >>>>> by userspace, they create a deadlock that is rejected by checking the dag >>>>> and the fence signaled with an error (and work cancelled, error >>>>> propagated back to userspace if they kept the output fence around), or >>>>> userspace forgets entirely about the fence they were waiting on in which >>>>> case it is signaled by closing the syncobjs [sadly not in error though, >>>>> I hoping to report EPIPE] on process termination. >>>> And exactly that concept is still a big NAK. >>>> >>>> The kernel memory management depends on dma_fences to be signaling as >>>> soon as they are existing. >>>> >>>> Just imagine what Daniel's dependency patches would splat out when you >>>> do something like this and correctly annotate the signaling code path. >>> Nothing at all. Forward progress of the waiter does not solely depend on >>> the signaler, just as in bc9c80fe01a2570a2fd78abbc492b377b5fda068. >>> >>>> Proxy fences, especially when they depend on userspace for signaling are >>>> an absolutely NO-GO. >>> We are in full control of the signaling and are able to cancel the pending >>> userspace operation, move it off to one side and shutdown the HW, >>> whatever. We can and do do dependency analysis of the fence contexts to >>> avoid deadlocks, just as easily as detecting recursion. >>> >>> To claim that userspace is not already able to control signaling, is a >>> false dichotomy. Userspace is fully able to lock the HW resources >>> indefinitely (even if you cap every job, one can always build a chain of >>> jobs to circumvent any imposed timeout, a couple of seconds timeout >>> becomes several months of jobs before the GPU runs out of memory and is >>> unable to accept any more jobs). Any ioctl that blocks while holding a HW >>> resource renders itself liable to a user controllable livelock, you know >>> this, because it is blocking the signaling of those earlier jobs. >>> Worrying about things that are entirely within our control and hence >>> avoidable, misses the point. >> You are completely missing the problem here. >> >> As you correctly pointed out that an userspace thread blocks on >> something is perfectly acceptable. And that's how >> bc9c80fe01a2570a2fd78abbc492b377b5fda068 works as well. >> >> And bc9c80fe01a2570a2fd78abbc492b377b5fda068 only implements waiting so >> that during CS or WAIT IOCTL we can block for the fence to appear. >> >> >> What happens in your approach is that the kernel starts to wait for >> userspace in its memory reclaim path. That is exactly the kind of >> problem Daniels patches now point out immediately. > No we don't. Well then Daniels patches are still missing that case :) See when signaling a fence depends userspace doing something, we obviously insert circle dependencies between whatever userspace might do in a kernel system call and the kernel reclaim path. That this can't work correctly is actually completely obvious if you see it from this side. Regards, Christian. > -Chris From shy828301 at gmail.com Thu Jun 25 16:32:34 2020 From: shy828301 at gmail.com (Yang Shi) Date: Thu, 25 Jun 2020 09:32:34 -0700 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200625114209.GA7703@casper.infradead.org> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200625114209.GA7703@casper.infradead.org> Message-ID: <CAHbLzkqBJWx89tTSPXjCzMG8=2OGQSmzPNjhqZv55surP8oFCQ@mail.gmail.com> On Thu, Jun 25, 2020 at 4:42 AM Matthew Wilcox <willy at infradead.org> wrote: > > On Wed, Jun 24, 2020 at 08:14:17PM +0100, Chris Wilson wrote: > > A side effect of the LRU shrinker not being dma aware is that we will > > often attempt to perform direct reclaim on the persistent group of dma > > pages while continuing to use the dma HW (an issue as the HW may already > > be actively waiting for the next user request), and even attempt to > > reclaim a partially allocated dma object in order to satisfy pinning > > the next user page for that object. > > > > It is to be expected that such pages are made available for reclaim at > > the end of the dma operation [unpin_user_pages()], and for truly > > longterm pins to be proactively recovered via device specific shrinkers > > [i.e. stop the HW, allow the pages to be returned to the system, and > > then compete again for the memory]. > > Why are DMA pinned pages still on the LRU list at all? I never got an > answer to this that made sense to me. By definition, a page which is > pinned for DMA is being accessed, and needs to at the very least change > position on the LRU list, so just take it off the list when DMA-pinned > and put it back on the list when DMA-unpinned. Sounds reasonable to me. In the earlier email I suggested skip isolate dma pinned page in scan phase, but if they are long term pinned, it seems preferred to put them on the unevictable lru IMHO. > > This overly complex lease stuff must have some reason for existing, but > I still don't get it. > From ckoenig.leichtzumerken at gmail.com Fri Jun 26 08:54:19 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Fri, 26 Jun 2020 10:54:19 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159315901171.15982.4604268132167952820@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <159302990055.4527.16849537545776334660@build.alporthouse.com> <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> <159308931300.4527.14536354033703689604@build.alporthouse.com> <6d99c4d9-7294-9ce1-471a-f81de7dc2c4f@amd.com> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> <159310696106.31486.9034080828697272264@build.alporthouse.com> <159315901171.15982.4604268132167952820@build.alporthouse.com> Message-ID: <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> Am 26.06.20 um 10:10 schrieb Chris Wilson: > Quoting Chris Wilson (2020-06-25 18:42:41) >> Quoting Christian K?nig (2020-06-25 16:47:09) >>> Am 25.06.20 um 17:10 schrieb Chris Wilson: >>>> We have the DAG of fences, we can use that information to avoid adding >>>> an implicit coupling between execution contexts. >>> No, we can't. And it sounds like you still have not understood the >>> underlying problem. >>> >>> See this has nothing to do with the fences itself or their DAG. >>> >>> When you depend on userspace to do another submission so your fence can >>> start processing you end up depending on whatever userspace does. >> HW dependency on userspace is explicit in the ABI and client APIs, and >> the direct control userspace has over the HW. >> >>> This in turn means when userspace calls a system call (or does page >>> fault) it is possible that this ends up in the reclaim code path. >> We have both said the very same thing. Then I'm really wondering why you don't come to the same conclusion :) >> >>> And while we want to avoid it both Daniel and I already discussed this >>> multiple times and we agree it is still a must have to be able to do >>> fence waits in the reclaim code path. >> But came to the opposite conclusion. For doing that wait harms the >> unrelated caller and the reclaim is opportunistic. There is no need for >> that caller to reclaim that page, when it can have any other. Why did you >> even choose that page to reclaim? Inducing latency in the caller is a bug, >> has been reported previously as a bug, and still considered a bug. [But at >> the end of the day, if the system is out of memory, then you have to pick >> a victim.] Correct. But this is also not limited to the reclaim path as any kernel system call and page fault can cause a problem as well. In other words "fence -> userspace -> page fault -> fence" or "fence -> userspace -> system call -> fence" can easily cause the same problem and that is not avoidable. > An example > > Thread A Thread B > > submit(VkCmdWaitEvents) > recvfrom(ThreadB) ... sendto(ThreadB) > \- alloc_page > \- direct reclaim > \- dma_fence_wait(A) > VkSetEvent() > > Regardless of that actual deadlock, waiting on an arbitrary fence incurs > an unbounded latency which is unacceptable for direct reclaim. > > Online debugging can indefinitely suspend fence signaling, and the only > guarantee we make of forward progress, in some cases, is process > termination. And exactly that is what doesn't work. You don't have any forward progress any more because you ran into a software deadlock. In other words the signaling of a fence depends on the welfare of userspace. You can try to kill userspace, but this can wait for the fence you try to signal in the first place. See the difference to a deadlock on the GPU is that you can can always kill a running job or process even if it is stuck with something else. But if the kernel is deadlocked with itself you can't kill the process any more, the only option left to get cleanly out of this is to reboot the kernel. The only way to avoid this would be to never ever wait for the fence in the kernel and then your whole construct is not useful any more. I'm running out of ideas how to explain what the problem is here.... Regards, Christian. > -Chris From star at gmx.li Sun Jun 28 10:38:35 2020 From: star at gmx.li (Arno) Date: Sun, 28 Jun 2020 12:38:35 +0200 Subject: [Intel-gfx] intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun In-Reply-To: <5b9c291892c245b3becd3df45ba5f3f9@intel.com> References: <aab05507-450d-5643-20af-500dec6bc59b@gmx.li> <fab11a35-be96-40c4-3572-6879eb39364a@gmx.li> <267c19058bf64dc2851cc5b6c0c6383c@intel.com> <5b9c291892c245b3becd3df45ba5f3f9@intel.com> Message-ID: <03fa1eb0-610f-84af-3a1a-b7e439b86b99@gmx.li> Dear Lakshminarayana, dear Chris, dear Jani, thanks for opening this bug, but it seems nothing to happen with that. Can I do anything to trigger this and bring that back to focus. It is an really annoying bug and this flickering screen drives me crazy and with "intel_idle.max_cstate=4" runtime is dramatically reduced. From what I read maybe you Chris have biggest knowledge. Can you give me some feedback? Shall I give up hope? Best regards, Arno On 18.05.20 09:43, Vudum, Lakshminarayana wrote: > > Arno, I have created bug > https://gitlab.freedesktop.org/drm/intel/-/issues/1900 > <https://gitlab.freedesktop.org/drm/intel/-/issues/1900> for this issue. > > Now discussions can happen in the bug report directly. Thanks for > reporting the issue. > > Thanks, > > Lakshmi. > > *From:* Saarinen, Jani <jani.saarinen at intel.com> > *Sent:* Monday, May 18, 2020 10:21 AM > *To:* Arno <star at gmx.li>; intel-gfx at lists.freedesktop.org; > chris at chris-wilson.co.uk; Vudum, Lakshminarayana > <lakshminarayana.vudum at intel.com> > *Subject:* RE: [Intel-gfx] intel_cpu_fifo_underrun_irq_handler [i915]] > *ERROR* CPU pipe A FIFO underrun > > Please make gitlab issue if not already done. Lakshmi, please guide. > > *From:* Intel-gfx <intel-gfx-bounces at lists.freedesktop.org > <mailto:intel-gfx-bounces at lists.freedesktop.org>> *On Behalf Of *Arno > *Sent:* maanantai 18. toukokuuta 2020 10.07 > *To:* intel-gfx at lists.freedesktop.org > <mailto:intel-gfx at lists.freedesktop.org>; chris at chris-wilson.co.uk > <mailto:chris at chris-wilson.co.uk> > *Subject:* Re: [Intel-gfx] intel_cpu_fifo_underrun_irq_handler [i915]] > *ERROR* CPU pipe A FIFO underrun > > Is there another place to report this kind of issue? Didn't get any > feedback. Did I make mistakes in my mail? I already tried the Ubuntu > bug-tracker (see below) with no success. > > Thank you, > > Arno > > Am 11.05.20 um 10:18 schrieb Arno: > > My laptop (core m5-6y54) starts flickering after returning from > Suspend (to RAM) or other commands touching the video driver > (xrandr, powertop --calibrate, ...) > > From kernel (tested with up to 5.7) I get the message: > > [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe > A FIFO underrun > > I added a bug with more details here: > > https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1872760 > > but guys from Ubuntu seems not able to help (as it is an upstream > bug) !? > > This happend not in older kernels, but these have the problem not > to go in power save states. So I think the fix of that > > https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1863489 > > causes this regression. > > Hope someone can help. For a? laptop it is better to have both - > standby and power saving. Thank you. > > Arno > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > <mailto:Intel-gfx at lists.freedesktop.org> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > --------------------------------------------------------------------- > Intel Finland Oy > Registered Address: PL 281, 00181 Helsinki > Business Identity Code: 0357606 - 4 > Domiciled in Helsinki > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200628/f1808ebb/attachment-0001.htm> From peter.chen at nxp.com Mon Jun 29 03:31:11 2020 From: peter.chen at nxp.com (Peter Chen) Date: Mon, 29 Jun 2020 03:31:11 +0000 Subject: [Intel-gfx] [PATCH 1/4] usb: cdns3: gadget: Replace trace_printk by dev_dbg In-Reply-To: <20200627070307.516803-2-drinkcat@chromium.org> References: <20200627070307.516803-1-drinkcat@chromium.org> <20200627070307.516803-2-drinkcat@chromium.org> Message-ID: <20200629033134.GA30684@b29397-desktop> On 20-06-27 15:03:04, Nicolas Boichat wrote: > trace_printk should not be used in production code, replace it > call with dev_dbg. > > Signed-off-by: Nicolas Boichat <drinkcat at chromium.org> > > --- > > Unclear why a trace_printk was used in the first place, it's > possible that some rate-limiting is necessary here. > > drivers/usb/cdns3/gadget.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c > index 5e24c2e57c0d8c8..c303ab7c62d1651 100644 > --- a/drivers/usb/cdns3/gadget.c > +++ b/drivers/usb/cdns3/gadget.c > @@ -421,7 +421,7 @@ static int cdns3_start_all_request(struct cdns3_device *priv_dev, > if ((priv_req->flags & REQUEST_INTERNAL) || > (priv_ep->flags & EP_TDLCHK_EN) || > priv_ep->use_streams) { > - trace_printk("Blocking external request\n"); > + dev_dbg(priv_dev->dev, "Blocking external request\n"); > return ret; > } > } > -- Reviewed-by: Peter Chen <peter.chen at nxp.com> -- Thanks, Peter Chen From ckoenig.leichtzumerken at gmail.com Fri Jun 26 17:44:26 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Fri, 26 Jun 2020 19:44:26 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159317692089.18415.8505405149005648608@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <159309140216.31486.2359580281725596670@build.alporthouse.com> <011fe07b-1e2c-7cc2-ade8-2c8b4df80b90@gmail.com> <159309782319.31486.530565133539052103@build.alporthouse.com> <746b10ad-7521-78dd-9a2b-2f44b6594842@amd.com> <159310696106.31486.9034080828697272264@build.alporthouse.com> <159315901171.15982.4604268132167952820@build.alporthouse.com> <a5417984-202b-f252-2aa5-19e8cdaecf20@gmail.com> <159316983838.18415.16087585177754322983@build.alporthouse.com> <edfaedf3-f6ad-044d-8853-4ee0991a4903@amd.com> <159317692089.18415.8505405149005648608@build.alporthouse.com> Message-ID: <c4b22cc7-597a-f310-b283-a0e42bf9b5be@gmail.com> Am 26.06.20 um 15:08 schrieb Chris Wilson: > Quoting Christian K?nig (2020-06-26 12:35:30) >> Am 26.06.20 um 13:10 schrieb Chris Wilson: >>> Quoting Christian K?nig (2020-06-26 09:54:19) >>> [SNIP] >>> What about checkpoint/restore, suspend/resume? Where we need to suspend >>> all execution, move all the resources to one side, then put everything >>> back, without cancelling the fences. Same halting problem, no? >> What are you talking about? Of course we either wait for all fences to >> complete or cancel them on suspend. > I do not want to have to cancel incomplete fences as we do today. But this is a necessity. Putting away halve executed fences and starting them later on is not possible and most likely never will be. >> So why wait in the middle of submission, rather than defer the submission >> to the fence callback if the HW wasn't ready? You then have your >> uninterruptible continuation. Because you don't wait in the middle of the submission, but rather before the submission is made and resources or locks are acquired. That's also the reason why it is illegal to wait for a fence to appear with a reservation lock held and that is also what lockdep should be able to point out as well. See amdgpu_cs_ioctl() for an example of why this is necessary: ??????? r = amdgpu_cs_dependencies(adev, &parser); ... ??????? r = amdgpu_cs_parser_bos(&parser, data); amdgpu_cs_dependencies() is waiting for the wait before signal fences to appear and amdgpu_cs_parser_bos() is grabbing the reservation locks. Do it the other way around and lockdep at least should splat that this has deadlock potential. And you are running into exactly the same case here as well, just in a bit more complicated because userspace is involved. >>> But if you have chosen to cancel the fences, there is nothing to stop >>> the signaling. >> And just to repeat myself: You can't cancel the fence! >> >> For example assume that canceling the proxy fence would mean that you >> send a SIGKILL to the process which issued it. But then you need to wait >> for the SIGKILL to be processed. > What? Where does SIGKILL come from for fence handling? Sorry, that was just an example how to handle it. A lock or an event is also possible. > The proxy fence is force signaled in an error state (e.g. -ETIMEDOUT), > every waiter then inherits the error state and all of their waiters down > the chain. Those waiters are now presumably ready to finish their own > signaling. That alone is illegal. See currently fences are only allowed to signal if all their previous dependencies are signaled, even in an error case. This is because we replace all the fences in a dma_resv object when we add a new exclusive one. > The proxy fence is constructed to always complete if it does not get > resolved; after resolution, the onus is on the real fence to complete. But then it is not useful at all. See in this case you can't wait on the proxy fence at all. In other words when you try to wait and the underlying real submission has not yet appeared you must return with an error immediately. >>> However, I say that is under our control. We know what fences are in an >>> execution context, just as easily as we know that we are inside an >>> execution context. And yes, the easiest, the most restrictive way to >>> control it is to say don't bother. >> No, that is absolutely not under our control. >> >> dma_fences need to be waited on under a lot of different context, >> including the reclaim path as well as the MMU notifiers, memory pressure >> callbacks, OOM killer.... > Oh yes, they are under our control. That list boils down to reclaim, > since mmu notifiers outside of reclaim are outside of a nested context. Nested context is irrelevant here. Let's see the following example: We use dma_fence_proxy because userspace wants to do a delayed submission. This dma_fence_proxy is attached to a dma_resv object because we need the implicit dependency for DRI2/DRI3 handling. Now the process calls fork() and an MMU notifier is triggered. This MMU notifier then waits for the dma_resv object fences to complete. But to complete the fences the fork() call needs to complete first -> deadlock. > That in particular is the same old question as whether GFP_IO should be > a gfp_t or in the task_struct. If we are inside an execution context, we > can track that and the fences on the task_struct if we wanted to, > avoiding reclaim of fences being used by the outer context and their > descendants... Oh, yes that is correct and an absolutely brilliant example of why this doesn't work :D See the difference is that in this case userspace is involved. In other words in your example you would set the GFP_IO flag in the task_struct and then return from your IOCTL and waiting for the next IOCTL to clear it again. And that in turn is not something we can do. >> No, as far as I can see you don't seem to either understand the problem >> or the implications of it. >> >> The only way to solve this would be to audit the whole Linux kernel and >> remove all uninterruptible waits and that is not feasible. >> >> As long as you don't provide me with a working solution to the problem >> I've outlined here the whole approach is a clear NAK since it will allow >> to create really bad kernel deadlocks. > You are confusing multiple things here. The VkEvents example is real. > How do you avoid that deadlock? We avoid it by not waiting in direct > reclaim. I'm perfectly aware of what are you trying to do here cause the AMD engineers have suggested and tried the exact same thing. And yes we have already rejected that as well. > It has also shown up any waits in our submit ioctl [prior to fence > publication, I might add] for their potential deadlock with userspace. No that approach is provable deadlock free. See as I explained with the amdgpu_cs example above it is as simple as waiting for the fences to appear without any memory management relevant locks held. As soon as you leak waiting for fences to appear into other parts of the kernel you are making those parts depend on the welfare of the userspace process and that's what doesn't work. Sorry that I'm so insisting on this, but we have already tried this approach and discussed it more than once and it really does not work correctly. Regards, Christian. > -Chris From shy828301 at gmail.com Wed Jun 24 20:23:02 2020 From: shy828301 at gmail.com (Yang Shi) Date: Wed, 24 Jun 2020 13:23:02 -0700 Subject: [Intel-gfx] [PATCH] mm: Skip opportunistic reclaim for dma pinned pages In-Reply-To: <20200624192116.GO6578@ziepe.ca> References: <20200624191417.16735-1-chris@chris-wilson.co.uk> <20200624192116.GO6578@ziepe.ca> Message-ID: <CAHbLzkoy2kz7yirch7t9ruzJjNTyCCZHJFZst7OEz_DdmQyaaA@mail.gmail.com> On Wed, Jun 24, 2020 at 12:21 PM Jason Gunthorpe <jgg at ziepe.ca> wrote: > > On Wed, Jun 24, 2020 at 08:14:17PM +0100, Chris Wilson wrote: > > A general rule of thumb is that shrinkers should be fast and effective. > > They are called from direct reclaim at the most incovenient of times when > > the caller is waiting for a page. If we attempt to reclaim a page being > > pinned for active dma [pin_user_pages()], we will incur far greater > > latency than a normal anonymous page mapped multiple times. Worse the > > page may be in use indefinitely by the HW and unable to be reclaimed > > in a timely manner. > > A pinned page can't be migrated, discarded or swapped by definition - > it would cause data corruption. > > So, how do things even get here and/or work today at all? I think the > explanation is missing something important. The __remove_mapping() will try to freeze page count if the count is expected otherwise just not discard the page. I'm not quite sure why the check is done that late, my wild guess is to check the refcount at the last minute so there might be a chance the pin gets released right before it. But I noticed a bug in __remove_ampping() for THP since THP's dma pinned count is recorded in the tail page's hpage_pinned_refcount instead of refcount. So, the refcount freeze might be successful for pinned THP. Chris's patch could solve this issue too, but I'm not sure if it is worth backing earlier once dma pinned page is met. If it is worth, the follow-up question is why not just skip such page in scan phase? > > Jason > From ckoenig.leichtzumerken at gmail.com Thu Jun 25 08:11:35 2020 From: ckoenig.leichtzumerken at gmail.com (=?UTF-8?Q?Christian_K=c3=b6nig?=) Date: Thu, 25 Jun 2020 10:11:35 +0200 Subject: [Intel-gfx] [PATCH 7/7] drm/i915/gem: Acquire all vma/objects under reservation_ww_class In-Reply-To: <159302990055.4527.16849537545776334660@build.alporthouse.com> References: <20200622095921.15530-1-chris@chris-wilson.co.uk> <20200622095921.15530-7-chris@chris-wilson.co.uk> <2c65a714-cf5a-fae6-5342-b514351d03a5@shipmail.org> <159290661156.6856.12185315246799210214@build.alporthouse.com> <CAPM=9tx69Xv3xbAb1U+SGOuKk7wirZy6FbRejsajCt9Lvan9VA@mail.gmail.com> <159294714433.24819.3044662904558073290@build.alporthouse.com> <CAPM=9tzY0An5THnH=+KEv35LfX0DGt9q6u=t83id6OPgFsN-LQ@mail.gmail.com> <159302990055.4527.16849537545776334660@build.alporthouse.com> Message-ID: <de87a30b-3ac2-1bee-4ee0-5a05baef6146@gmail.com> Am 24.06.20 um 22:18 schrieb Chris Wilson: > Quoting Dave Airlie (2020-06-24 20:04:02) >> On Wed, 24 Jun 2020 at 07:19, Chris Wilson <chris at chris-wilson.co.uk> wrote: >>> Quoting Dave Airlie (2020-06-23 22:01:24) >>>> On Tue, 23 Jun 2020 at 20:03, Chris Wilson <chris at chris-wilson.co.uk> wrote: >>>>> Quoting Thomas Hellstr?m (Intel) (2020-06-23 10:33:20) >>>>>> Hi, Chris! >>>>>> >>>>>> On 6/22/20 11:59 AM, Chris Wilson wrote: >>>>>>> In order to actually handle eviction and what not, we need to process >>>>>>> all the objects together under a common lock, reservation_ww_class. As >>>>>>> such, do a memory reservation pass after looking up the object/vma, >>>>>>> which then feeds into the rest of execbuf [relocation, cmdparsing, >>>>>>> flushing and ofc execution]. >>>>>>> >>>>>>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >>>>>>> --- >>>>>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 91 ++++++++++++++----- >>>>>>> 1 file changed, 70 insertions(+), 21 deletions(-) >>>>>>> >>>>>> Which tree is this against? The series doesn't apply cleanly against >>>>>> drm-tip? >>>>> It's continuing on from the scheduler patches, the bug fixes and the >>>>> iris-deferred-fence work. I thought throwing all of those old patches >>>>> into the pile would have been distracting. >>>>> >>>>>> ... >>>>>> >>>>>>> +static int eb_reserve_mm(struct i915_execbuffer *eb) >>>>>>> +{ >>>>>>> + const u64 idx = eb->context->timeline->fence_context; >>>>>>> + struct ww_acquire_ctx acquire; >>>>>>> + struct eb_vma *ev; >>>>>>> + int err; >>>>>>> + >>>>>>> + eb->mm_fence = __dma_fence_create_proxy(0, 0); >>>>>>> + if (!eb->mm_fence) >>>>>>> + return -ENOMEM; >>>>>> Where are the proxy fence functions defined? >>>>> In dma-fence-proxy.c ;) >>>> The dma-fence-proxy that Christian NAKed before? >>> I do not have an email from Christian about dma-fence-proxy in the last >>> 3 years it has been on the list. >> https://lore.kernel.org/dri-devel/aeb0373d-0583-d922-3b73-93668c27d177 at amd.com/ > Darn, I skimmed the thread title and thought it was just about the > timelines. > >> I'm assuming this was about patch 8 there which to me looks like proxy >> fences but maybe by threading is off reading that. > The deadlocks are easy to resolve. The fence is either signaled normally > by userspace, they create a deadlock that is rejected by checking the dag > and the fence signaled with an error (and work cancelled, error > propagated back to userspace if they kept the output fence around), or > userspace forgets entirely about the fence they were waiting on in which > case it is signaled by closing the syncobjs [sadly not in error though, > I hoping to report EPIPE] on process termination. And exactly that concept is still a big NAK. The kernel memory management depends on dma_fences to be signaling as soon as they are existing. Just imagine what Daniel's dependency patches would splat out when you do something like this and correctly annotate the signaling code path. Proxy fences, especially when they depend on userspace for signaling are an absolutely NO-GO. Regards, Christian. > > https://patchwork.freedesktop.org/patch/372759/?series=78762&rev=1 > We can always attach the dag resolver such that we resolve the deadlock > for any importer and so only ever present a normal monotonic fence. > That would make it illegal to wait on an external fence imported into > that syncobj (as that would be outside of our dag). An option would > be whether or not to force timeout slow userspace. But the simplicity of > reusing the existing functionality to move intrabatch scheduling into > iris is compelling. [In contrast, no one has yet finished the timeline > patches to the point where they stopped throwing errors in igt, and we > still then have to write patches for nonblocking wait-for-submit :[ > > The use here is trivial, chiefly used as a convenience to flesh out this > argument to see if we can reduce the lock duration within submission > [from the entirety of submission to ideally just reservation] by holding > a fence for the submission process itself. And that boils down to at what > point can someone else start to wait on that fence, and whether or not we > can avoid any direct/indirect waits ourselves after point and before > completing submission. [Usual rules about not being allowed to wait on a > resource while holding contendable resources, but with the nuance of > what/when exactly that resource becomes contendable.] The lock contention > is quite real, as at the moment it is devolving into a global lock. With > the amusing side effect that it then turns out to be quicker to wrap the > entire thing in struct_mutex. > -Chris From will at kernel.org Thu Jun 25 13:16:20 2020 From: will at kernel.org (Will Deacon) Date: Thu, 25 Jun 2020 14:16:20 +0100 Subject: [Intel-gfx] [PATCH 12/13] arm64: Remove dev->archdata.iommu pointer In-Reply-To: <20200625130836.1916-13-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> <20200625130836.1916-13-joro@8bytes.org> Message-ID: <20200625131620.GA8161@willie-the-truck> On Thu, Jun 25, 2020 at 03:08:35PM +0200, Joerg Roedel wrote: > From: Joerg Roedel <jroedel at suse.de> > > There are no users left, all drivers have been converted to use the > per-device private pointer offered by IOMMU core. > > Signed-off-by: Joerg Roedel <jroedel at suse.de> > --- > arch/arm64/include/asm/device.h | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/arch/arm64/include/asm/device.h b/arch/arm64/include/asm/device.h > index 12b778d55342..996498751318 100644 > --- a/arch/arm64/include/asm/device.h > +++ b/arch/arm64/include/asm/device.h > @@ -6,9 +6,6 @@ > #define __ASM_DEVICE_H > > struct dev_archdata { > -#ifdef CONFIG_IOMMU_API > - void *iommu; /* private IOMMU data */ > -#endif > }; Acked-by: Will Deacon <will at kernel.org> Thanks, Joerg. Will From maarten.lankhorst at linux.intel.com Mon Jun 29 13:44:36 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Mon, 29 Jun 2020 15:44:36 +0200 Subject: [Intel-gfx] [PATCH 04/26] drm/i915: Add an implementation for i915_gem_ww_ctx locking, v2. In-Reply-To: <c03481f1-92c2-24ad-b56e-a92fbb70f9fe@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-4-maarten.lankhorst@linux.intel.com> <c03481f1-92c2-24ad-b56e-a92fbb70f9fe@linux.intel.com> Message-ID: <01dc9947-575a-aa22-b52b-8aa3da9aeede@linux.intel.com> Op 29-06-2020 om 14:32 schreef Tvrtko Ursulin: > > On 23/06/2020 15:28, Maarten Lankhorst wrote: >> i915_gem_ww_ctx is used to lock all gem bo's for pinning and memory >> eviction. We don't use it yet, but lets start adding the definition >> first. >> >> To use it, we have to pass a non-NULL ww to gem_object_lock, and don't >> unlock directly. It is done in i915_gem_ww_ctx_fini. >> >> Changes since v1: >> - Change ww_ctx and obj order in locking functions (Jonas Lahtinen) >> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> >> --- >> ? drivers/gpu/drm/i915/display/intel_display.c? |? 4 +- >> ? .../gpu/drm/i915/gem/i915_gem_client_blt.c??? |? 2 +- >> ? drivers/gpu/drm/i915/gem/i915_gem_context.c?? |? 2 +- >> ? drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c??? |? 4 +- >> ? drivers/gpu/drm/i915/gem/i915_gem_domain.c??? | 10 ++-- >> ? .../gpu/drm/i915/gem/i915_gem_execbuffer.c??? |? 4 +- >> ? drivers/gpu/drm/i915/gem/i915_gem_object.c??? |? 2 +- >> ? drivers/gpu/drm/i915/gem/i915_gem_object.h??? | 38 +++++++++++--- >> ? .../gpu/drm/i915/gem/i915_gem_object_types.h? |? 9 ++++ >> ? drivers/gpu/drm/i915/gem/i915_gem_pm.c??????? |? 2 +- >> ? drivers/gpu/drm/i915/gem/i915_gem_tiling.c??? |? 2 +- >> ? .../gpu/drm/i915/gem/selftests/huge_pages.c?? |? 2 +- >> ? .../i915/gem/selftests/i915_gem_client_blt.c? |? 2 +- >> ? .../i915/gem/selftests/i915_gem_coherency.c?? | 10 ++-- >> ? .../drm/i915/gem/selftests/i915_gem_context.c |? 4 +- >> ? .../drm/i915/gem/selftests/i915_gem_mman.c??? |? 4 +- >> ? .../drm/i915/gem/selftests/i915_gem_phys.c??? |? 2 +- >> ? .../gpu/drm/i915/gt/selftest_workarounds.c??? |? 2 +- >> ? drivers/gpu/drm/i915/gvt/cmd_parser.c???????? |? 2 +- >> ? drivers/gpu/drm/i915/i915_gem.c?????????????? | 52 +++++++++++++++++-- >> ? drivers/gpu/drm/i915/i915_gem.h?????????????? | 11 ++++ >> ? drivers/gpu/drm/i915/selftests/i915_gem.c???? | 41 +++++++++++++++ >> ? drivers/gpu/drm/i915/selftests/i915_vma.c???? |? 2 +- >> ? .../drm/i915/selftests/intel_memory_region.c? |? 2 +- >> ? 24 files changed, 173 insertions(+), 42 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c >> index 7457813ef273..e909ccc37a54 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display.c >> +++ b/drivers/gpu/drm/i915/display/intel_display.c >> @@ -2309,7 +2309,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, >> ? ? void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) >> ? { >> -??? i915_gem_object_lock(vma->obj); >> +??? i915_gem_object_lock(vma->obj, NULL); >> ????? if (flags & PLANE_HAS_FENCE) >> ????????? i915_vma_unpin_fence(vma); >> ????? i915_gem_object_unpin_from_display_plane(vma); >> @@ -17112,7 +17112,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, >> ????? if (!intel_fb->frontbuffer) >> ????????? return -ENOMEM; >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? tiling = i915_gem_object_get_tiling(obj); >> ????? stride = i915_gem_object_get_stride(obj); >> ????? i915_gem_object_unlock(obj); >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c >> index d3a86a4d5c04..c182091c00ff 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c >> @@ -286,7 +286,7 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, >> ????? dma_fence_init(&work->dma, &clear_pages_work_ops, &fence_lock, 0, 0); >> ????? i915_sw_fence_init(&work->wait, clear_pages_work_notify); >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? err = i915_sw_fence_await_reservation(&work->wait, >> ??????????????????????????? obj->base.resv, NULL, true, 0, >> ??????????????????????????? I915_FENCE_GFP); >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c >> index 30c229fcb404..a996583640ee 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c >> @@ -113,7 +113,7 @@ static void lut_close(struct i915_gem_context *ctx) >> ????????????? continue; >> ? ????????? rcu_read_unlock(); >> -??????? i915_gem_object_lock(obj); >> +??????? i915_gem_object_lock(obj, NULL); >> ????????? list_for_each_entry(lut, &obj->lut_list, obj_link) { >> ????????????? if (lut->ctx != ctx) >> ????????????????? continue; >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c >> index 2679380159fc..27fddc22a7c6 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c >> @@ -128,7 +128,7 @@ static int i915_gem_begin_cpu_access(struct dma_buf *dma_buf, enum dma_data_dire >> ????? if (err) >> ????????? return err; >> ? -??? err = i915_gem_object_lock_interruptible(obj); >> +??? err = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (err) >> ????????? goto out; >> ? @@ -149,7 +149,7 @@ static int i915_gem_end_cpu_access(struct dma_buf *dma_buf, enum dma_data_direct >> ????? if (err) >> ????????? return err; >> ? -??? err = i915_gem_object_lock_interruptible(obj); >> +??? err = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (err) >> ????????? goto out; >> ? diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c >> index 7f76fc68f498..c0acfc97fae3 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c >> @@ -32,7 +32,7 @@ void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) >> ????? if (!i915_gem_object_is_framebuffer(obj)) >> ????????? return; >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? __i915_gem_object_flush_for_display(obj); >> ????? i915_gem_object_unlock(obj); >> ? } >> @@ -197,7 +197,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, >> ????? if (ret) >> ????????? return ret; >> ? -??? ret = i915_gem_object_lock_interruptible(obj); >> +??? ret = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (ret) >> ????????? return ret; >> ? @@ -536,7 +536,7 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, >> ????? if (err) >> ????????? goto out; >> ? -??? err = i915_gem_object_lock_interruptible(obj); >> +??? err = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (err) >> ????????? goto out_unpin; >> ? @@ -576,7 +576,7 @@ int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj, >> ????? if (!i915_gem_object_has_struct_page(obj)) >> ????????? return -ENODEV; >> ? -??? ret = i915_gem_object_lock_interruptible(obj); >> +??? ret = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (ret) >> ????????? return ret; >> ? @@ -630,7 +630,7 @@ int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj, >> ????? if (!i915_gem_object_has_struct_page(obj)) >> ????????? return -ENODEV; >> ? -??? ret = i915_gem_object_lock_interruptible(obj); >> +??? ret = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (ret) >> ????????? return ret; >> ? diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> index 2b4c210638c1..391d22051b20 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> @@ -813,7 +813,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, >> ????????? if (err == 0) { /* And nor has this handle */ >> ????????????? struct drm_i915_gem_object *obj = vma->obj; >> ? -??????????? i915_gem_object_lock(obj); >> +??????????? i915_gem_object_lock(obj, NULL); >> ????????????? if (idr_find(&eb->file->object_idr, handle) == obj) { >> ????????????????? list_add(&lut->obj_link, &obj->lut_list); >> ????????????? } else { >> @@ -1083,7 +1083,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, >> ????????? if (use_cpu_reloc(cache, obj)) >> ????????????? return NULL; >> ? -??????? i915_gem_object_lock(obj); >> +??????? i915_gem_object_lock(obj, NULL); >> ????????? err = i915_gem_object_set_to_gtt_domain(obj, true); >> ????????? i915_gem_object_unlock(obj); >> ????????? if (err) >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c >> index b6ec5b50d93b..b59e2d40c347 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c >> @@ -108,7 +108,7 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) >> ????? struct i915_lut_handle *lut, *ln; >> ????? LIST_HEAD(close); >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { >> ????????? struct i915_gem_context *ctx = lut->ctx; >> ? diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h >> index 2faa481cc18f..5103067269b0 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h >> @@ -110,20 +110,44 @@ i915_gem_object_put(struct drm_i915_gem_object *obj) >> ? ? #define assert_object_held(obj) dma_resv_assert_held((obj)->base.resv) >> ? -static inline void i915_gem_object_lock(struct drm_i915_gem_object *obj) >> +static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj, >> +???????????????????? struct i915_gem_ww_ctx *ww, >> +???????????????????? bool intr) >> ? { >> -??? dma_resv_lock(obj->base.resv, NULL); >> +??? int ret; >> + >> +??? if (intr) >> +??????? ret = dma_resv_lock_interruptible(obj->base.resv, ww ? &ww->ctx : NULL); >> +??? else >> +??????? ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL); >> + >> +??? if (!ret && ww) >> +??????? list_add_tail(&obj->obj_link, &ww->obj_list); >> +??? if (ret == -EALREADY) >> +??????? ret = 0; >> + >> +??? if (ret == -EDEADLK) >> +??????? ww->contended = obj; >> + >> +??? return ret; > > Feels a bit on the large side for inline now, no? Quite a few conditionals. Or you are counting on compiler optimisation because ww and intr are passed in as mostly const? Slightly, not sure if it's really a problem in practice. ww is either null or a stack variable, so for null it should all go away. > >> ? } >> ? -static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) >> +static inline int i915_gem_object_lock(struct drm_i915_gem_object *obj, >> +?????????????????????? struct i915_gem_ww_ctx *ww) >> ? { >> -??? return dma_resv_trylock(obj->base.resv); >> +??? return __i915_gem_object_lock(obj, ww, ww && ww->intr); >> ? } >> ? -static inline int >> -i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj) >> +static inline int i915_gem_object_lock_interruptible(struct drm_i915_gem_object *obj, >> +???????????????????????????? struct i915_gem_ww_ctx *ww) >> ? { >> -??? return dma_resv_lock_interruptible(obj->base.resv, NULL); >> +??? WARN_ON(ww && !ww->intr); >> +??? return __i915_gem_object_lock(obj, ww, true); > > I see that ww->intr is set at ctx init time. At what times it is expected that the individual lock calls would override that? Never. :) Just politely allowing it when replacing calls. Could be removed and replaced with lock_single_interruptible without ww context. > >> +} >> + >> +static inline bool i915_gem_object_trylock(struct drm_i915_gem_object *obj) >> +{ >> +??? return dma_resv_trylock(obj->base.resv); >> ? } >> ? ? static inline void i915_gem_object_unlock(struct drm_i915_gem_object *obj) >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >> index b1f82a11aef2..3740c0080e38 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >> @@ -122,6 +122,15 @@ struct drm_i915_gem_object { >> ?????? */ >> ????? struct list_head lut_list; >> ? +??? /** >> +???? * @obj_link: Link into @i915_gem_ww_ctx.obj_list >> +???? * >> +???? * When we lock this object through i915_gem_object_lock() with a >> +???? * context, we add it to the list to ensure we can unlock everything >> +???? * when i915_gem_ww_ctx_backoff() or i915_gem_ww_ctx_fini() are called. >> +???? */ >> +??? struct list_head obj_link; >> + >> ????? /** Stolen memory for this object, instead of being backed by shmem. */ >> ????? struct drm_mm_node *stolen; >> ????? union { >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c >> index 3d215164dd5a..40d3e40500fa 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c >> @@ -84,7 +84,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) >> ? ????????????? spin_unlock_irqrestore(&i915->mm.obj_lock, flags); >> ? -??????????? i915_gem_object_lock(obj); >> +??????????? i915_gem_object_lock(obj, NULL); >> ????????????? drm_WARN_ON(&i915->drm, >> ????????????????? i915_gem_object_set_to_gtt_domain(obj, false)); >> ????????????? i915_gem_object_unlock(obj); >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c >> index 0158e49bf9bb..65fbf29c4852 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c >> @@ -249,7 +249,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj, >> ?????? * whilst executing a fenced command for an untiled object. >> ?????? */ >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? if (i915_gem_object_is_framebuffer(obj)) { >> ????????? i915_gem_object_unlock(obj); >> ????????? return -EBUSY; >> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c >> index 8291ede6902c..eb2011ccb92b 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c >> @@ -947,7 +947,7 @@ static int gpu_write(struct intel_context *ce, >> ? { >> ????? int err; >> ? -??? i915_gem_object_lock(vma->obj); >> +??? i915_gem_object_lock(vma->obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(vma->obj, true); >> ????? i915_gem_object_unlock(vma->obj); >> ????? if (err) >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> index 299c29e9ad86..4e36d4897ea6 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> @@ -75,7 +75,7 @@ static int __igt_client_fill(struct intel_engine_cs *engine) >> ????????? if (err) >> ????????????? goto err_unpin; >> ? -??????? i915_gem_object_lock(obj); >> +??????? i915_gem_object_lock(obj, NULL); >> ????????? err = i915_gem_object_set_to_cpu_domain(obj, false); >> ????????? i915_gem_object_unlock(obj); >> ????????? if (err) >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c >> index 87d7d8aa080f..1de2959b153c 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c >> @@ -82,7 +82,7 @@ static int gtt_set(struct context *ctx, unsigned long offset, u32 v) >> ????? u32 __iomem *map; >> ????? int err = 0; >> ? -??? i915_gem_object_lock(ctx->obj); >> +??? i915_gem_object_lock(ctx->obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); >> ????? i915_gem_object_unlock(ctx->obj); >> ????? if (err) >> @@ -115,7 +115,7 @@ static int gtt_get(struct context *ctx, unsigned long offset, u32 *v) >> ????? u32 __iomem *map; >> ????? int err = 0; >> ? -??? i915_gem_object_lock(ctx->obj); >> +??? i915_gem_object_lock(ctx->obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(ctx->obj, false); >> ????? i915_gem_object_unlock(ctx->obj); >> ????? if (err) >> @@ -147,7 +147,7 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v) >> ????? u32 *map; >> ????? int err; >> ? -??? i915_gem_object_lock(ctx->obj); >> +??? i915_gem_object_lock(ctx->obj, NULL); >> ????? err = i915_gem_object_set_to_wc_domain(ctx->obj, true); >> ????? i915_gem_object_unlock(ctx->obj); >> ????? if (err) >> @@ -170,7 +170,7 @@ static int wc_get(struct context *ctx, unsigned long offset, u32 *v) >> ????? u32 *map; >> ????? int err; >> ? -??? i915_gem_object_lock(ctx->obj); >> +??? i915_gem_object_lock(ctx->obj, NULL); >> ????? err = i915_gem_object_set_to_wc_domain(ctx->obj, false); >> ????? i915_gem_object_unlock(ctx->obj); >> ????? if (err) >> @@ -193,7 +193,7 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v) >> ????? u32 *cs; >> ????? int err; >> ? -??? i915_gem_object_lock(ctx->obj); >> +??? i915_gem_object_lock(ctx->obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(ctx->obj, true); >> ????? i915_gem_object_unlock(ctx->obj); >> ????? if (err) >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> index b81978890641..438c15ef2184 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c >> @@ -950,7 +950,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj, >> ????? if (IS_ERR(vma)) >> ????????? return PTR_ERR(vma); >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(obj, false); >> ????? i915_gem_object_unlock(obj); >> ????? if (err) >> @@ -1706,7 +1706,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, >> ? ????? i915_request_add(rq); >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? err = i915_gem_object_set_to_cpu_domain(obj, false); >> ????? i915_gem_object_unlock(obj); >> ????? if (err) >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c >> index 9c7402ce5bf9..9fb95a45bcad 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c >> @@ -103,7 +103,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj, >> ????? GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); >> ????? GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(obj, true); >> ????? i915_gem_object_unlock(obj); >> ????? if (err) { >> @@ -188,7 +188,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj, >> ????? GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling); >> ????? GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride); >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(obj, true); >> ????? i915_gem_object_unlock(obj); >> ????? if (err) { >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c >> index 34932871b3a5..a94243dc4c5c 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c >> @@ -44,7 +44,7 @@ static int mock_phys_object(void *arg) >> ????? } >> ? ????? /* Make the object dirty so that put_pages must do copy back the data */ >> -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? err = i915_gem_object_set_to_gtt_domain(obj, true); >> ????? i915_gem_object_unlock(obj); >> ????? if (err) { >> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c >> index febc9e6692ba..61a0532d0f3d 100644 >> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c >> @@ -214,7 +214,7 @@ static int check_whitelist(struct i915_gem_context *ctx, >> ????????? return PTR_ERR(results); >> ? ????? err = 0; >> -??? i915_gem_object_lock(results); >> +??? i915_gem_object_lock(results, NULL); >> ????? intel_wedge_on_timeout(&wedge, engine->gt, HZ / 5) /* safety net! */ >> ????????? err = i915_gem_object_set_to_cpu_domain(results, false); >> ????? i915_gem_object_unlock(results); >> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c >> index f1940939260a..943c8d232703 100644 >> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c >> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c >> @@ -2982,7 +2982,7 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) >> ????????? goto put_obj; >> ????? } >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? ret = i915_gem_object_set_to_cpu_domain(obj, false); >> ????? i915_gem_object_unlock(obj); >> ????? if (ret) { >> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c >> index 9aa3066cb75d..1e06752835e5 100644 >> --- a/drivers/gpu/drm/i915/i915_gem.c >> +++ b/drivers/gpu/drm/i915/i915_gem.c >> @@ -420,7 +420,7 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj, >> ????????? GEM_BUG_ON(!drm_mm_node_allocated(&node)); >> ????? } >> ? -??? ret = i915_gem_object_lock_interruptible(obj); >> +??? ret = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (ret) >> ????????? goto out_unpin; >> ? @@ -619,7 +619,7 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, >> ????????? GEM_BUG_ON(!drm_mm_node_allocated(&node)); >> ????? } >> ? -??? ret = i915_gem_object_lock_interruptible(obj); >> +??? ret = i915_gem_object_lock_interruptible(obj, NULL); >> ????? if (ret) >> ????????? goto out_unpin; >> ? @@ -1290,7 +1290,7 @@ int i915_gem_freeze_late(struct drm_i915_private *i915) >> ????? i915_gem_drain_freed_objects(i915); >> ? ????? list_for_each_entry(obj, &i915->mm.shrink_list, mm.link) { >> -??????? i915_gem_object_lock(obj); >> +??????? i915_gem_object_lock(obj, NULL); >> ????????? drm_WARN_ON(&i915->drm, >> ????????????????? i915_gem_object_set_to_cpu_domain(obj, true)); >> ????????? i915_gem_object_unlock(obj); >> @@ -1344,6 +1344,52 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) >> ????? return ret; >> ? } >> ? +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr) >> +{ >> +??? ww_acquire_init(&ww->ctx, &reservation_ww_class); >> +??? INIT_LIST_HEAD(&ww->obj_list); >> +??? ww->intr = intr; >> +??? ww->contended = NULL; >> +} >> + >> +static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww) >> +{ >> +??? struct drm_i915_gem_object *obj; >> + >> +??? while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) { > > I wanted to ask whether you think this is faster than for_each_list_entry, but then also realized you can optimise further by not bothering to list_del (since you know the whole list is going away). If you are not allowing ww ctx reuse you don't even need to re-init the list_head at the end. > >> +??????? list_del(&obj->obj_link); >> +??????? i915_gem_object_unlock(obj); >> +??? } >> +} >> + >> +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww) >> +{ >> +??? i915_gem_ww_ctx_unlock_all(ww); >> +??? WARN_ON(ww->contended); > > Unless I am missing something this feels like a GEM_BUG_ON condition (translated: we should be confident after testing it is impossible to hit). > > Or it is allowed to not try the backoff on -EDEADLK? Backoff is the only place which resets the ww->contended, right? In this case WARN_ON would be wrong, but you probably did not went for this design. Should it be supported? > >> +??? ww_acquire_fini(&ww->ctx); >> +} >> + >> +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww) >> +{ >> +??? int ret = 0; >> + >> +??? if (WARN_ON(!ww->contended)) >> +??????? return -EINVAL; >> + >> +??? i915_gem_ww_ctx_unlock_all(ww); >> +??? if (ww->intr) >> +??????? ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx); >> +??? else >> +??????? dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx); >> + >> +??? if (!ret) >> +??????? list_add_tail(&ww->contended->obj_link, &ww->obj_list); >> + >> +??? ww->contended = NULL; >> + >> +??? return ret; >> +} >> + >> ? #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) >> ? #include "selftests/mock_gem_device.c" >> ? #include "selftests/i915_gem.c" >> diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h >> index 1753c84d6c0d..988755dbf4be 100644 >> --- a/drivers/gpu/drm/i915/i915_gem.h >> +++ b/drivers/gpu/drm/i915/i915_gem.h >> @@ -116,4 +116,15 @@ static inline bool __tasklet_is_scheduled(struct tasklet_struct *t) >> ????? return test_bit(TASKLET_STATE_SCHED, &t->state); >> ? } >> ? +struct i915_gem_ww_ctx { >> +??? struct ww_acquire_ctx ctx; >> +??? struct list_head obj_list; >> +??? bool intr; >> +??? struct drm_i915_gem_object *contended; >> +}; >> + >> +void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr); >> +void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx); >> +int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx); >> + >> ? #endif /* __I915_GEM_H__ */ >> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c >> index 88d400b9df88..23a6132c5f4e 100644 >> --- a/drivers/gpu/drm/i915/selftests/i915_gem.c >> +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c >> @@ -199,11 +199,52 @@ static int igt_gem_hibernate(void *arg) >> ????? return err; >> ? } >> ? +static int igt_gem_ww_ctx(void *arg) >> +{ >> +??? struct drm_i915_private *i915 = arg; >> +??? struct drm_i915_gem_object *obj, *obj2; >> +??? struct i915_gem_ww_ctx ww; >> +??? int err = 0; >> + >> +??? obj = i915_gem_object_create_internal(i915, PAGE_SIZE); >> +??? if (IS_ERR(obj)) >> +??????? return PTR_ERR(obj); >> + >> +??? obj2 = i915_gem_object_create_internal(i915, PAGE_SIZE); >> +??? if (IS_ERR(obj)) { > > Wrong obj ^^^ vvv. > >> +??????? err = PTR_ERR(obj); >> +??????? goto put1; >> +??? } >> + >> +??? i915_gem_ww_ctx_init(&ww, true); > > Need to expand with non-interruptible, interruptible and mixed. > >> +retry: >> +??? /* Lock the objects, twice for good measure (-EALREADY handling) */ >> +??? err = i915_gem_object_lock(obj, &ww); >> +??? if (!err) >> +??????? err = i915_gem_object_lock_interruptible(obj, &ww); > > This is -EALREADY on the 1st pass. > >> +??? if (!err) >> +??????? err = i915_gem_object_lock_interruptible(obj2, &ww); >> +??? if (!err) >> +??????? err = i915_gem_object_lock(obj2, &ww); > > And this is -EALREADY again? > >> + >> +??? if (err == -EDEADLK) { > > How do we get here with a single locking context? > >> +??????? err = i915_gem_ww_ctx_backoff(&ww); >> +??????? if (!err) >> +??????????? goto retry; >> +??? } >> +??? i915_gem_ww_ctx_fini(&ww); >> +??? i915_gem_object_put(obj2); >> +put1: >> +??? i915_gem_object_put(obj); >> +??? return err; >> +} >> + >> ? int i915_gem_live_selftests(struct drm_i915_private *i915) >> ? { >> ????? static const struct i915_subtest tests[] = { >> ????????? SUBTEST(igt_gem_suspend), >> ????????? SUBTEST(igt_gem_hibernate), >> +??????? SUBTEST(igt_gem_ww_ctx), >> ????? }; >> ? ????? if (intel_gt_is_wedged(&i915->gt)) >> diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c >> index af89c7fc8f59..88c5e9acb84c 100644 >> --- a/drivers/gpu/drm/i915/selftests/i915_vma.c >> +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c >> @@ -892,7 +892,7 @@ static int igt_vma_remapped_gtt(void *arg) >> ????????????? unsigned int x, y; >> ????????????? int err; >> ? -??????????? i915_gem_object_lock(obj); >> +??????????? i915_gem_object_lock(obj, NULL); >> ????????????? err = i915_gem_object_set_to_gtt_domain(obj, true); >> ????????????? i915_gem_object_unlock(obj); >> ????????????? if (err) >> diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c >> index 6e80d99048e4..957a7a52def7 100644 >> --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c >> +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c >> @@ -509,7 +509,7 @@ static int igt_lmem_write_cpu(void *arg) >> ????? if (err) >> ????????? goto out_unpin; >> ? -??? i915_gem_object_lock(obj); >> +??? i915_gem_object_lock(obj, NULL); >> ????? err = i915_gem_object_set_to_wc_domain(obj, true); >> ????? i915_gem_object_unlock(obj); >> ????? if (err) >> > > Regards, > > Tvrtko From tvrtko.ursulin at linux.intel.com Mon Jun 29 14:42:06 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 29 Jun 2020 15:42:06 +0100 Subject: [Intel-gfx] [PATCH 06/26] drm/i915: Parse command buffer earlier in eb_relocate(slow) In-Reply-To: <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-6-maarten.lankhorst@linux.intel.com> Message-ID: <6af770d1-367d-52df-4aec-26af9e05e5d7@linux.intel.com> On 23/06/2020 15:28, Maarten Lankhorst wrote: > We want to introduce backoff logic, but we need to lock the > pool object as well for command parsing. Because of this, we > will need backoff logic for the engine pool obj, move the batch > validation up slightly to eb_lookup_vmas, and the actual command > parsing in a separate function which can get called from execbuf > relocation fast and slowpath. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 66 ++++++++++--------- > 1 file changed, 36 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index f896b1a4b38a..7cb44915cfc7 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -290,6 +290,8 @@ struct i915_execbuffer { > struct eb_vma_array *array; > }; > > +static int eb_parse(struct i915_execbuffer *eb); > + > static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) > { > return intel_engine_requires_cmd_parser(eb->engine) || > @@ -873,6 +875,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) > > static int eb_lookup_vmas(struct i915_execbuffer *eb) > { > + struct drm_i915_private *i915 = eb->i915; > unsigned int batch = eb_batch_index(eb); > unsigned int i; > int err = 0; > @@ -886,18 +889,37 @@ static int eb_lookup_vmas(struct i915_execbuffer *eb) > vma = eb_lookup_vma(eb, eb->exec[i].handle); > if (IS_ERR(vma)) { > err = PTR_ERR(vma); > - break; > + goto err; > } > > err = eb_validate_vma(eb, &eb->exec[i], vma); > if (unlikely(err)) { > i915_vma_put(vma); > - break; > + goto err; > } > > eb_add_vma(eb, i, batch, vma); > } > > + if (unlikely(eb->batch->flags & EXEC_OBJECT_WRITE)) { > + drm_dbg(&i915->drm, > + "Attempting to use self-modifying batch buffer\n"); > + return -EINVAL; > + } > + > + if (range_overflows_t(u64, > + eb->batch_start_offset, eb->batch_len, > + eb->batch->vma->size)) { > + drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); > + return -EINVAL; > + } > + > + if (eb->batch_len == 0) > + eb->batch_len = eb->batch->vma->size - eb->batch_start_offset; How about you move the parsing step at least into a helper? So it is more obvious this step is not simply about looking up vmas, even if it is called from eb_lookup_vmas. > + > + return 0; > + > +err: > eb->vma[i].vma = NULL; > return err; > } > @@ -1809,7 +1831,7 @@ static int eb_prefault_relocations(const struct i915_execbuffer *eb) > return 0; > } > > -static noinline int eb_relocate_slow(struct i915_execbuffer *eb) Something looks off - here you rename eb_relocate_slow but I don't see any callers changing in this patch. So I have to assume broken bisect stage. > +static noinline int eb_relocate_parse_slow(struct i915_execbuffer *eb) > { > bool have_copy = false; > struct eb_vma *ev; > @@ -1872,6 +1894,11 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) > if (err) > goto err; > > + /* as last step, parse the command buffer */ > + err = eb_parse(eb); > + if (err) > + goto err; > + > /* > * Leave the user relocations as are, this is the painfully slow path, > * and we want to avoid the complication of dropping the lock whilst > @@ -1904,7 +1931,7 @@ static noinline int eb_relocate_slow(struct i915_execbuffer *eb) > return err; > } > > -static int eb_relocate(struct i915_execbuffer *eb) > +static int eb_relocate_parse(struct i915_execbuffer *eb) > { > int err; > > @@ -1932,7 +1959,7 @@ static int eb_relocate(struct i915_execbuffer *eb) > return eb_relocate_slow(eb); > } > > - return 0; > + return eb_parse(eb); And I am not a fan of relocation stage calling parse. Why couldn't every stage be done separately at the call sites so the stages are explicit and clear? Commit message is explaining the parsing needs to go earlier, to come under the ww context block? But isn't it already after eb_lookup_vmas in current code? Oh wait.. I am looking at drm-tip and don't have your reverts. It was agreed you will remove them, right? So I can wait for the next round to figure this re-organization. Regards, Tvrtko > } > > static int eb_move_to_gpu(struct i915_execbuffer *eb) > @@ -2870,7 +2897,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, > if (unlikely(err)) > goto err_context; > > - err = eb_relocate(&eb); > + err = eb_relocate_parse(&eb); > if (err) { > /* > * If the user expects the execobject.offset and > @@ -2883,33 +2910,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, > goto err_vma; > } > > - if (unlikely(eb.batch->flags & EXEC_OBJECT_WRITE)) { > - drm_dbg(&i915->drm, > - "Attempting to use self-modifying batch buffer\n"); > - err = -EINVAL; > - goto err_vma; > - } > - > - if (range_overflows_t(u64, > - eb.batch_start_offset, eb.batch_len, > - eb.batch->vma->size)) { > - drm_dbg(&i915->drm, "Attempting to use out-of-bounds batch\n"); > - err = -EINVAL; > - goto err_vma; > - } > - > - if (eb.batch_len == 0) > - eb.batch_len = eb.batch->vma->size - eb.batch_start_offset; > - > - err = eb_parse(&eb); > - if (err) > - goto err_vma; > - > /* > * snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure > * batch" bit. Hence we need to pin secure batches into the global gtt. > * hsw should have this fixed, but bdw mucks it up again. */ > - batch = eb.batch->vma; > if (eb.batch_flags & I915_DISPATCH_SECURE) { > struct i915_vma *vma; > > @@ -2923,13 +2927,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, > * fitting due to fragmentation. > * So this is actually safe. > */ > - vma = i915_gem_object_ggtt_pin(batch->obj, NULL, 0, 0, 0); > + vma = i915_gem_object_ggtt_pin(eb.batch->vma->obj, NULL, 0, 0, 0); > if (IS_ERR(vma)) { > err = PTR_ERR(vma); > goto err_parse; > } > > batch = vma; > + } else { > + batch = eb.batch->vma; > } > > /* All GPU relocation batches must be submitted prior to the user rq */ > From tvrtko.ursulin at linux.intel.com Mon Jun 29 15:08:42 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 29 Jun 2020 16:08:42 +0100 Subject: [Intel-gfx] [PATCH 07/26] Revert "drm/i915/gem: Split eb_vma into its own allocation" In-Reply-To: <20200623142843.423594-7-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-7-maarten.lankhorst@linux.intel.com> Message-ID: <dacbaf04-a149-38e2-5c07-3d3e10589bd3@linux.intel.com> On 23/06/2020 15:28, Maarten Lankhorst wrote: > This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974. > This conflicts with the ww mutex handling, which needs to drop > the references after gpu submission anyway, because otherwise we > may risk unlocking a BO after first freeing it. What is the problem here? eb_vma_array_put in eb_move_to_gpu? If so, could you just move this put to later in the sequence? I am simply thinking how to avoid controversial reverts. Because on the other hand I did not figure out what 0f1dd02295f35dcdcbaafcbcbbec0753884ab974 fixed in a few minutes I spent staring at the patch. Regards, Tvrtko > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 124 +++++++----------- > 1 file changed, 51 insertions(+), 73 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 7cb44915cfc7..2636a130fb57 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -40,11 +40,6 @@ struct eb_vma { > u32 handle; > }; > > -struct eb_vma_array { > - struct kref kref; > - struct eb_vma vma[]; > -}; > - > enum { > FORCE_CPU_RELOC = 1, > FORCE_GTT_RELOC, > @@ -57,6 +52,7 @@ enum { > #define __EXEC_OBJECT_NEEDS_MAP BIT(29) > #define __EXEC_OBJECT_NEEDS_BIAS BIT(28) > #define __EXEC_OBJECT_INTERNAL_FLAGS (~0u << 28) /* all of the above */ > +#define __EXEC_OBJECT_RESERVED (__EXEC_OBJECT_HAS_PIN | __EXEC_OBJECT_HAS_FENCE) > > #define __EXEC_HAS_RELOC BIT(31) > #define __EXEC_INTERNAL_FLAGS (~0u << 31) > @@ -287,7 +283,6 @@ struct i915_execbuffer { > */ > int lut_size; > struct hlist_head *buckets; /** ht for relocation handles */ > - struct eb_vma_array *array; > }; > > static int eb_parse(struct i915_execbuffer *eb); > @@ -299,62 +294,8 @@ static inline bool eb_use_cmdparser(const struct i915_execbuffer *eb) > eb->args->batch_len); > } > > -static struct eb_vma_array *eb_vma_array_create(unsigned int count) > -{ > - struct eb_vma_array *arr; > - > - arr = kvmalloc(struct_size(arr, vma, count), GFP_KERNEL | __GFP_NOWARN); > - if (!arr) > - return NULL; > - > - kref_init(&arr->kref); > - arr->vma[0].vma = NULL; > - > - return arr; > -} > - > -static inline void eb_unreserve_vma(struct eb_vma *ev) > -{ > - struct i915_vma *vma = ev->vma; > - > - if (unlikely(ev->flags & __EXEC_OBJECT_HAS_FENCE)) > - __i915_vma_unpin_fence(vma); > - > - if (ev->flags & __EXEC_OBJECT_HAS_PIN) > - __i915_vma_unpin(vma); > - > - ev->flags &= ~(__EXEC_OBJECT_HAS_PIN | > - __EXEC_OBJECT_HAS_FENCE); > -} > - > -static void eb_vma_array_destroy(struct kref *kref) > -{ > - struct eb_vma_array *arr = container_of(kref, typeof(*arr), kref); > - struct eb_vma *ev = arr->vma; > - > - while (ev->vma) { > - eb_unreserve_vma(ev); > - i915_vma_put(ev->vma); > - ev++; > - } > - > - kvfree(arr); > -} > - > -static void eb_vma_array_put(struct eb_vma_array *arr) > -{ > - kref_put(&arr->kref, eb_vma_array_destroy); > -} > - > static int eb_create(struct i915_execbuffer *eb) > { > - /* Allocate an extra slot for use by the command parser + sentinel */ > - eb->array = eb_vma_array_create(eb->buffer_count + 2); > - if (!eb->array) > - return -ENOMEM; > - > - eb->vma = eb->array->vma; > - > if (!(eb->args->flags & I915_EXEC_HANDLE_LUT)) { > unsigned int size = 1 + ilog2(eb->buffer_count); > > @@ -388,10 +329,8 @@ static int eb_create(struct i915_execbuffer *eb) > break; > } while (--size); > > - if (unlikely(!size)) { > - eb_vma_array_put(eb->array); > + if (unlikely(!size)) > return -ENOMEM; > - } > > eb->lut_size = size; > } else { > @@ -502,6 +441,26 @@ eb_pin_vma(struct i915_execbuffer *eb, > return !eb_vma_misplaced(entry, vma, ev->flags); > } > > +static inline void __eb_unreserve_vma(struct i915_vma *vma, unsigned int flags) > +{ > + GEM_BUG_ON(!(flags & __EXEC_OBJECT_HAS_PIN)); > + > + if (unlikely(flags & __EXEC_OBJECT_HAS_FENCE)) > + __i915_vma_unpin_fence(vma); > + > + __i915_vma_unpin(vma); > +} > + > +static inline void > +eb_unreserve_vma(struct eb_vma *ev) > +{ > + if (!(ev->flags & __EXEC_OBJECT_HAS_PIN)) > + return; > + > + __eb_unreserve_vma(ev->vma, ev->flags); > + ev->flags &= ~__EXEC_OBJECT_RESERVED; > +} > + > static int > eb_validate_vma(struct i915_execbuffer *eb, > struct drm_i915_gem_exec_object2 *entry, > @@ -944,13 +903,31 @@ eb_get_vma(const struct i915_execbuffer *eb, unsigned long handle) > } > } > > +static void eb_release_vmas(const struct i915_execbuffer *eb) > +{ > + const unsigned int count = eb->buffer_count; > + unsigned int i; > + > + for (i = 0; i < count; i++) { > + struct eb_vma *ev = &eb->vma[i]; > + struct i915_vma *vma = ev->vma; > + > + if (!vma) > + break; > + > + eb->vma[i].vma = NULL; > + > + if (ev->flags & __EXEC_OBJECT_HAS_PIN) > + __eb_unreserve_vma(vma, ev->flags); > + > + i915_vma_put(vma); > + } > +} > + > static void eb_destroy(const struct i915_execbuffer *eb) > { > GEM_BUG_ON(eb->reloc_cache.rq); > > - if (eb->array) > - eb_vma_array_put(eb->array); > - > if (eb->lut_size > 0) > kfree(eb->buckets); > } > @@ -2039,12 +2016,9 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb) > err = i915_vma_move_to_active(vma, eb->request, flags); > > i915_vma_unlock(vma); > - eb_unreserve_vma(ev); > } > ww_acquire_fini(&acquire); > > - eb_vma_array_put(fetch_and_zero(&eb->array)); > - > if (unlikely(err)) > goto err_skip; > > @@ -2340,7 +2314,6 @@ static int eb_parse(struct i915_execbuffer *eb) > eb->vma[eb->buffer_count].vma = i915_vma_get(shadow); > eb->vma[eb->buffer_count].flags = __EXEC_OBJECT_HAS_PIN; > eb->batch = &eb->vma[eb->buffer_count++]; > - eb->vma[eb->buffer_count].vma = NULL; > > eb->trampoline = trampoline; > eb->batch_start_offset = 0; > @@ -2838,6 +2811,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, > args->flags |= __EXEC_HAS_RELOC; > > eb.exec = exec; > + eb.vma = (struct eb_vma *)(exec + args->buffer_count + 1); > + eb.vma[0].vma = NULL; > > eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; > reloc_cache_init(&eb.reloc_cache, eb.i915); > @@ -3014,6 +2989,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, > if (batch->private) > intel_gt_buffer_pool_put(batch->private); > err_vma: > + if (eb.exec) > + eb_release_vmas(&eb); > if (eb.trampoline) > i915_vma_unpin(eb.trampoline); > eb_unpin_engine(&eb); > @@ -3031,7 +3008,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, > > static size_t eb_element_size(void) > { > - return sizeof(struct drm_i915_gem_exec_object2); > + return sizeof(struct drm_i915_gem_exec_object2) + sizeof(struct eb_vma); > } > > static bool check_buffer_count(size_t count) > @@ -3087,7 +3064,7 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, > /* Copy in the exec list from userland */ > exec_list = kvmalloc_array(count, sizeof(*exec_list), > __GFP_NOWARN | GFP_KERNEL); > - exec2_list = kvmalloc_array(count, eb_element_size(), > + exec2_list = kvmalloc_array(count + 1, eb_element_size(), > __GFP_NOWARN | GFP_KERNEL); > if (exec_list == NULL || exec2_list == NULL) { > drm_dbg(&i915->drm, > @@ -3165,7 +3142,8 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, > if (err) > return err; > > - exec2_list = kvmalloc_array(count, eb_element_size(), > + /* Allocate an extra slot for use by the command parser */ > + exec2_list = kvmalloc_array(count + 1, eb_element_size(), > __GFP_NOWARN | GFP_KERNEL); > if (exec2_list == NULL) { > drm_dbg(&i915->drm, "Failed to allocate exec list for %zd buffers\n", > From tvrtko.ursulin at linux.intel.com Mon Jun 29 15:14:06 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Mon, 29 Jun 2020 16:14:06 +0100 Subject: [Intel-gfx] [PATCH 08/26] drm/i915/gem: Make eb_add_lut interruptible wait on object lock. In-Reply-To: <20200623142843.423594-8-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-8-maarten.lankhorst@linux.intel.com> Message-ID: <48435be5-d827-d785-9395-0d69a2b061a5@linux.intel.com> On 23/06/2020 15:28, Maarten Lankhorst wrote: > The lock here should be interruptible, so we can backoff if needed. I spied Chris posting "drm/i915/gem: Move obj->lut_list under its own lock" so maybe have a look at that. My question here is.. > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index 2636a130fb57..aa441af81431 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -774,7 +774,12 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > if (err == 0) { /* And nor has this handle */ > struct drm_i915_gem_object *obj = vma->obj; > > - i915_gem_object_lock(obj, NULL); > + err = i915_gem_object_lock_interruptible(obj, NULL); .. does this lock-unlock survive to the end of your series or gets completely subsumed by the ctx locking? Regards, Tvrtko > + if (err) { > + radix_tree_delete(&ctx->handles_vma, handle); > + goto unlock; > + } > + > if (idr_find(&eb->file->object_idr, handle) == obj) { > list_add(&lut->obj_link, &obj->lut_list); > } else { > @@ -783,6 +788,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > } > i915_gem_object_unlock(obj); > } > +unlock: > mutex_unlock(&ctx->mutex); > } > if (unlikely(err)) > From ville.syrjala at linux.intel.com Mon Jun 29 15:48:05 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Mon, 29 Jun 2020 18:48:05 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200629082432.GA1826@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> <20200626151336.GA6490@intel.com> <20200626180306.GC6112@intel.com> <20200629082432.GA1826@intel.com> Message-ID: <20200629154805.GD6112@intel.com> On Mon, Jun 29, 2020 at 11:24:53AM +0300, Lisovskiy, Stanislav wrote: > On Sat, Jun 27, 2020 at 07:57:31PM +0300, Ville Syrj?l? wrote: > > On Fri, Jun 26, 2020 at 06:13:36PM +0300, Lisovskiy, Stanislav wrote: > > > On Fri, Jun 26, 2020 at 04:46:41PM +0300, Ville Syrj?l? wrote: > > > > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > > > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > > > > > The linetime watermark is a 9 bit value, which gives us > > > > > > a maximum linetime of just below 64 usec. If the linetime > > > > > > exceeds that value we currently just discard the high bits > > > > > > and program the rest into the register, which angers the > > > > > > state checker. > > > > > > > > > > > > To avoid that let's just clamp the value to the max. I believe > > > > > > it should be perfectly fine to program a smaller linetime wm > > > > > > than strictly required, just means the hardware may fetch data > > > > > > sooner than strictly needed. We are further reassured by the > > > > > > fact that with DRRS the spec tells us to program the smaller > > > > > > of the two linetimes corresponding to the two refresh rates. > > > > > > > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ > > > > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > index a11bb675f9b3..d486d675166f 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > { > > > > > > const struct drm_display_mode *adjusted_mode = > > > > > > &crtc_state->hw.adjusted_mode; > > > > > > + int linetime_wm; > > > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > > return 0; > > > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > - adjusted_mode->crtc_clock); > > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > + adjusted_mode->crtc_clock); > > > > > > + > > > > > > + return min(linetime_wm, 0x1ff); > > > > > > > > > > Are we actually doing the right thing here? I just mean that we get value > > > > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > > > > > > > As explained in the commit msg programming this to lower than necessary > > > > value should be totally fine. It just won't be optimal. > > > > > > > > The values in the jira (was there an actual gitlab bug for this btw?) > > > > look quite sensible to me. Some kind of low res 848xsomething mode with > > > > dotclock of 14.874 Mhz, which gives us that linetime of ~68 usec. > > > > > > Htotal from modeline "848x480": 30 14874 848 896 928 1008 480 483 488 494 0x40 0x9 > > > is 1008. > > > > > > According to the formula above htotal(1008)*1000*8 / 14874(crtc_clock) = 542.154 > > > > > > So what's the catch? :) > > > > What catch? Looks totally consistent to me. > > I meant as I understood from your comment we were supposed to get 68 usec linetime, not > 542. It's in units of .125 usec, or put another way .3 binary fixed point. > > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > > > > > > Stan > > > > > > > > > > > > > > Stan > > > > > > } > > > > > > > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > > > @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > > > { > > > > > > const struct drm_display_mode *adjusted_mode = > > > > > > &crtc_state->hw.adjusted_mode; > > > > > > + int linetime_wm; > > > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > > return 0; > > > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > - cdclk_state->logical.cdclk); > > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > + cdclk_state->logical.cdclk); > > > > > > + > > > > > > + return min(linetime_wm, 0x1ff); > > > > > > } > > > > > > > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > > > const struct drm_display_mode *adjusted_mode = > > > > > > &crtc_state->hw.adjusted_mode; > > > > > > - u16 linetime_wm; > > > > > > + int linetime_wm; > > > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > > return 0; > > > > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > > > > linetime_wm /= 2; > > > > > > > > > > > > - return linetime_wm; > > > > > > + return min(linetime_wm, 0x1ff); > > > > > > } > > > > > > > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state *state, > > > > > > -- > > > > > > 2.26.2 > > > > > > > > > > > > > > -- > > > > Ville Syrj?l? > > > > Intel > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From stanislav.lisovskiy at intel.com Mon Jun 29 16:20:46 2020 From: stanislav.lisovskiy at intel.com (Lisovskiy, Stanislav) Date: Mon, 29 Jun 2020 19:20:46 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Clamp linetime wm to <64usec In-Reply-To: <20200629154805.GD6112@intel.com> References: <20200625200003.12436-1-ville.syrjala@linux.intel.com> <20200626091606.GA29269@intel.com> <20200626134641.GZ6112@intel.com> <20200626151336.GA6490@intel.com> <20200626180306.GC6112@intel.com> <20200629082432.GA1826@intel.com> <20200629154805.GD6112@intel.com> Message-ID: <20200629162046.GA605@intel.com> On Mon, Jun 29, 2020 at 06:48:05PM +0300, Ville Syrj?l? wrote: > On Mon, Jun 29, 2020 at 11:24:53AM +0300, Lisovskiy, Stanislav wrote: > > On Sat, Jun 27, 2020 at 07:57:31PM +0300, Ville Syrj?l? wrote: > > > On Fri, Jun 26, 2020 at 06:13:36PM +0300, Lisovskiy, Stanislav wrote: > > > > On Fri, Jun 26, 2020 at 04:46:41PM +0300, Ville Syrj?l? wrote: > > > > > On Fri, Jun 26, 2020 at 12:16:06PM +0300, Lisovskiy, Stanislav wrote: > > > > > > On Thu, Jun 25, 2020 at 11:00:03PM +0300, Ville Syrjala wrote: > > > > > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > > > > > > > > The linetime watermark is a 9 bit value, which gives us > > > > > > > a maximum linetime of just below 64 usec. If the linetime > > > > > > > exceeds that value we currently just discard the high bits > > > > > > > and program the rest into the register, which angers the > > > > > > > state checker. > > > > > > > > > > > > > > To avoid that let's just clamp the value to the max. I believe > > > > > > > it should be perfectly fine to program a smaller linetime wm > > > > > > > than strictly required, just means the hardware may fetch data > > > > > > > sooner than strictly needed. We are further reassured by the > > > > > > > fact that with DRRS the spec tells us to program the smaller > > > > > > > of the two linetimes corresponding to the two refresh rates. > > > > > > > > > > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------ > > > > > > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > index a11bb675f9b3..d486d675166f 100644 > > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > > > > > > @@ -12581,12 +12581,15 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > > { > > > > > > > const struct drm_display_mode *adjusted_mode = > > > > > > > &crtc_state->hw.adjusted_mode; > > > > > > > + int linetime_wm; > > > > > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > > > return 0; > > > > > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > > - adjusted_mode->crtc_clock); > > > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > > + adjusted_mode->crtc_clock); > > > > > > > + > > > > > > > + return min(linetime_wm, 0x1ff); > > > > > > > > > > > > Are we actually doing the right thing here? I just mean that we get value > > > > > > 543 in the bug because pixel rate is 14874 which doesn't seem correct. > > > > > > > > > > As explained in the commit msg programming this to lower than necessary > > > > > value should be totally fine. It just won't be optimal. > > > > > > > > > > The values in the jira (was there an actual gitlab bug for this btw?) > > > > > look quite sensible to me. Some kind of low res 848xsomething mode with > > > > > dotclock of 14.874 Mhz, which gives us that linetime of ~68 usec. > > > > > > > > Htotal from modeline "848x480": 30 14874 848 896 928 1008 480 483 488 494 0x40 0x9 > > > > is 1008. > > > > > > > > According to the formula above htotal(1008)*1000*8 / 14874(crtc_clock) = 542.154 > > > > > > > > So what's the catch? :) > > > > > > What catch? Looks totally consistent to me. > > > > I meant as I understood from your comment we were supposed to get 68 usec linetime, not > > 542. > > It's in units of .125 usec, or put another way .3 binary fixed point. Yep, found this in BSpec already for WM_LINETIME reg. > > > > > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > > > > > > > > > > > > Stan > > > > > > > > > > > > > > > > > Stan > > > > > > > } > > > > > > > > > > > > > > static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > > > > @@ -12594,12 +12597,15 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, > > > > > > > { > > > > > > > const struct drm_display_mode *adjusted_mode = > > > > > > > &crtc_state->hw.adjusted_mode; > > > > > > > + int linetime_wm; > > > > > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > > > return 0; > > > > > > > > > > > > > > - return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > > - cdclk_state->logical.cdclk); > > > > > > > + linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, > > > > > > > + cdclk_state->logical.cdclk); > > > > > > > + > > > > > > > + return min(linetime_wm, 0x1ff); > > > > > > > } > > > > > > > > > > > > > > static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > > @@ -12608,7 +12614,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > > > > > > const struct drm_display_mode *adjusted_mode = > > > > > > > &crtc_state->hw.adjusted_mode; > > > > > > > - u16 linetime_wm; > > > > > > > + int linetime_wm; > > > > > > > > > > > > > > if (!crtc_state->hw.enable) > > > > > > > return 0; > > > > > > > @@ -12620,7 +12626,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) > > > > > > > if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) > > > > > > > linetime_wm /= 2; > > > > > > > > > > > > > > - return linetime_wm; > > > > > > > + return min(linetime_wm, 0x1ff); > > > > > > > } > > > > > > > > > > > > > > static int hsw_compute_linetime_wm(struct intel_atomic_state *state, > > > > > > > -- > > > > > > > 2.26.2 > > > > > > > > > > > > > > > > > -- > > > > > Ville Syrj?l? > > > > > Intel > > > > > > -- > > > Ville Syrj?l? > > > Intel > > -- > Ville Syrj?l? > Intel From imre.deak at intel.com Mon Jun 29 18:58:47 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 29 Jun 2020 21:58:47 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock Message-ID: <20200629185848.20550-1-imre.deak@intel.com> When the reference clock is 38.4MHz, using the current TBT PLL fractional divider value results in a slightly off TBT link frequency. This causes an endless loop of link training success followed by a bad link signaling and retraining at least on a ThinkPad 40AC TBT dock. The workaround provided by the HW team is to divide the fractional divider value by two. This fixed the link training problem on the ThinkPad dock. The same workaround is needed on some EHL platforms and for combo PHY PLLs, these will be addressed in a follow-up. Bspec: 49204 References: HSDES#22010772725 References: HSDES#14011861142 Reported-and-tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com> Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b45185b80bec..f585053d02d8 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2937,6 +2937,12 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = { .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0, }; +static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = { + .dco_integer = 0x54, .dco_fraction = 0x1800, + /* the following params are unused */ + .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0, +}; + static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { @@ -2970,12 +2976,14 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, MISSING_CASE(dev_priv->dpll.ref_clks.nssc); /* fall-through */ case 19200: - case 38400: *pll_params = tgl_tbt_pll_19_2MHz_values; break; case 24000: *pll_params = tgl_tbt_pll_24MHz_values; break; + case 38400: + *pll_params = tgl_tbt_pll_38_4MHz_values; + break; } } else { switch (dev_priv->dpll.ref_clks.nssc) { -- 2.23.1 From imre.deak at intel.com Mon Jun 29 18:58:48 2020 From: imre.deak at intel.com (Imre Deak) Date: Mon, 29 Jun 2020 21:58:48 +0300 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/icl+: Simplify combo/TBT PLL calculation call-chain In-Reply-To: <20200629185848.20550-1-imre.deak@intel.com> References: <20200629185848.20550-1-imre.deak@intel.com> Message-ID: <20200629185848.20550-2-imre.deak@intel.com> To simplify things, call the combo PHY/TBT PLL calculation functions directly from the corresponding combo/TypeC PLL get functions, instead of calling the same calculation functions after having to recheck if the given PHY is combo or TypeC. Signed-off-by: Imre Deak <imre.deak at intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 64 ++++++++----------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index f585053d02d8..8306e92dc892 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3046,49 +3046,26 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, icl_wrpll_ref_clock(i915)); } -static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, - struct intel_encoder *encoder, +static void icl_calc_dpll_state(struct drm_i915_private *i915, + const struct skl_wrpll_params *pll_params, struct intel_dpll_hw_state *pll_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - u32 cfgcr0, cfgcr1; - struct skl_wrpll_params pll_params = { 0 }; - bool ret; - - if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, - encoder->port))) - ret = icl_calc_tbt_pll(crtc_state, &pll_params); - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) - ret = icl_calc_wrpll(crtc_state, &pll_params); - else - ret = icl_calc_dp_combo_pll(crtc_state, &pll_params); - - if (!ret) - return false; + memset(pll_state, 0, sizeof(*pll_state)); - cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) | - pll_params.dco_integer; + pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) | + pll_params->dco_integer; - cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) | - DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) | - DPLL_CFGCR1_KDIV(pll_params.kdiv) | - DPLL_CFGCR1_PDIV(pll_params.pdiv); + pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) | + DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) | + DPLL_CFGCR1_KDIV(pll_params->kdiv) | + DPLL_CFGCR1_PDIV(pll_params->pdiv); - if (INTEL_GEN(dev_priv) >= 12) - cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; + if (INTEL_GEN(i915) >= 12) + pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; else - cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; - - memset(pll_state, 0, sizeof(*pll_state)); - - pll_state->cfgcr0 = cfgcr0; - pll_state->cfgcr1 = cfgcr1; - - return true; + pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; } - static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) { return id - DPLL_ID_ICL_MGPLL1; @@ -3501,19 +3478,29 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct skl_wrpll_params pll_params = { }; struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum port port = encoder->port; unsigned long dpll_mask; + int ret; - if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) + ret = icl_calc_wrpll(crtc_state, &pll_params); + else + ret = icl_calc_dp_combo_pll(crtc_state, &pll_params); + + if (!ret) { drm_dbg_kms(&dev_priv->drm, "Could not calculate combo PHY PLL state.\n"); return false; } + icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); + if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | @@ -3547,16 +3534,19 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct skl_wrpll_params pll_params = { }; struct icl_port_dpll *port_dpll; enum intel_dpll_id dpll_id; port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; - if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { + if (!icl_calc_tbt_pll(crtc_state, &pll_params)) { drm_dbg_kms(&dev_priv->drm, "Could not calculate TBT PLL state.\n"); return false; } + icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); + port_dpll->pll = intel_find_shared_dpll(state, crtc, &port_dpll->hw_state, BIT(DPLL_ID_ICL_TBTPLL)); -- 2.23.1 From patchwork at emeril.freedesktop.org Mon Jun 29 19:04:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 29 Jun 2020 19:04:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3IgRGV0?= =?utf-8?q?ect_and_remove_trace=5Fprintk?= In-Reply-To: <20200627070307.516803-1-drinkcat@chromium.org> References: <20200627070307.516803-1-drinkcat@chromium.org> Message-ID: <159345749134.745.4372147372636508518@emeril.freedesktop.org> == Series Details == Series: Detect and remove trace_printk URL : https://patchwork.freedesktop.org/series/78870/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8673 -> Patchwork_18034 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18034 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18034, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18034: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bxt-dsi/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-bxt-dsi/igt at i915_selftest@live at execlists.html Known issues ------------ Here are the changes found in Patchwork_18034 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at debugfs_test@read_all_entries: - fi-bsw-nick: [PASS][3] -> [INCOMPLETE][4] ([i915#1250] / [i915#1436]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bsw-nick/igt at debugfs_test@read_all_entries.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-bsw-nick/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][5] -> [FAIL][6] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at gem_mmap_gtt@basic: - fi-tgl-y: [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at gem_mmap_gtt@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-tgl-y/igt at gem_mmap_gtt@basic.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-tgl-y: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at kms_busy@basic at flip.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-tgl-y/igt at kms_busy@basic at flip.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][15] -> [DMESG-WARN][16] ([i915#402]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][17] ([i915#1888]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at gem_flink_basic@double-flink: - fi-tgl-y: [DMESG-WARN][19] ([i915#402]) -> [PASS][20] +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at gem_flink_basic@double-flink.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-tgl-y/igt at gem_flink_basic@double-flink.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-n2820: [DMESG-WARN][21] ([i915#1982]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at coherency: - fi-gdg-551: [DMESG-FAIL][23] ([i915#1748]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-gdg-551/igt at i915_selftest@live at coherency.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-gdg-551/igt at i915_selftest@live at coherency.html * igt at i915_selftest@live at gt_pm: - fi-icl-y: [DMESG-FAIL][25] ([i915#2111]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-y/igt at i915_selftest@live at gt_pm.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-icl-y/igt at i915_selftest@live at gt_pm.html * igt at kms_psr@primary_page_flip: - fi-tgl-y: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at kms_psr@primary_page_flip.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-tgl-y/igt at kms_psr@primary_page_flip.html #### Warnings #### * igt at debugfs_test@read_all_entries: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92]) -> [DMESG-WARN][30] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-kbl-x1275/igt at debugfs_test@read_all_entries.html * igt at gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][32] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-kbl-x1275/igt at gem_exec_suspend@basic-s3.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][33] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][34] ([i915#62] / [i915#92]) +5 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [i915#1250]: https://gitlab.freedesktop.org/drm/intel/issues/1250 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2111]: https://gitlab.freedesktop.org/drm/intel/issues/2111 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 39) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8673 -> Patchwork_18034 CI-20190529: 20190529 CI_DRM_8673: ae0a2b45fe022c02a2779c2ae8c83473763c1feb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18034: 8cde1a0a4de00e3d77b8c6ed332486b887c6f5bb @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8cde1a0a4de0 kernel/trace: Add TRACING_ALLOW_PRINTK config option f240a00cdcd7 media: camss: vfe: Use trace_printk for debugging only 4c7d3ef5e566 media: atomisp: Replace trace_printk by pr_info 5f1b11fad802 usb: cdns3: gadget: Replace trace_printk by dev_dbg == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18034/index.html From patchwork at emeril.freedesktop.org Mon Jun 29 19:08:44 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 29 Jun 2020 19:08:44 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv2=5D_drm/i915/gem=3A_Move_obj-=3El?= =?utf-8?q?ut=5Flist_under_its_own_lock_=28rev3=29?= In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <159345772407.747.16043566553918040912@emeril.freedesktop.org> == Series Details == Series: series starting with [v2] drm/i915/gem: Move obj->lut_list under its own lock (rev3) URL : https://patchwork.freedesktop.org/series/78889/ State : warning == Summary == $ dim checkpatch origin/drm-tip c39cf9cd78da drm/i915/gem: Move obj->lut_list under its own lock 00af2c29ea68 drm/i915/gem: Split the context's obj:vma lut into its own mutex -:82: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment #82: FILE: drivers/gpu/drm/i915/gem/i915_gem_context_types.h:173: + struct mutex lut_mutex; total: 0 errors, 0 warnings, 1 checks, 105 lines checked 9e557cde27e4 drm/i915/gem: Drop forced struct_mutex from shrinker_taints_mutex c199e797c70d drm/i915: Export ppgtt_bind_vma ae5a264ca1f5 drm/i915: Preallocate stashes for vma page-directories -:590: ERROR:SPACING: space required before the open parenthesis '(' #590: FILE: drivers/gpu/drm/i915/gt/intel_ppgtt.c:253: + if(err) total: 1 errors, 0 warnings, 0 checks, 723 lines checked cfb7c88fb6fe drm/i915: Switch to object allocations for page directories From manasi.d.navare at intel.com Mon Jun 29 19:20:58 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Mon, 29 Jun 2020 12:20:58 -0700 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200626232641.4557-1-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> Message-ID: <20200629192057.GA16227@intel.com> @Ville @Imre, addressed your review comments, could you take a look? Manasi On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote: > Modify the helper to add a fixed delay or poll with timeout > based on platform specification to check for either Idle bit > set (DDI_BUF_CTL is idle for disable case) > > v3: > * Change the timeout to 16usecs (Ville) > v2: > * Use 2 separate functions or idle and active (Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > 1 file changed, 8 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 884b507c5f55..052a74625a61 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > enum port port) > { > - i915_reg_t reg = DDI_BUF_CTL(port); > - int i; > - > - for (i = 0; i < 16; i++) { > - udelay(1); > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > - return; > + if (IS_BROXTON(dev_priv)) { > + udelay(16); > + return; > } > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > - port_name(port)); > + > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 16)) > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > + port_name(port)); > } > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > -- > 2.19.1 > From manasi.d.navare at intel.com Mon Jun 29 19:21:31 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Mon, 29 Jun 2020 12:21:31 -0700 Subject: [Intel-gfx] [PATCH v4 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200626232641.4557-2-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> <20200626232641.4557-2-manasi.d.navare@intel.com> Message-ID: <20200629192131.GB16227@intel.com> @Ville, @Imre : addressed your review comments, could you please take a look? Regards Manasi On Fri, Jun 26, 2020 at 04:26:41PM -0700, Manasi Navare wrote: > Based on the platform, Bspec expects us to wait or poll with > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > after enabling DDI_BUF_CTL. > > v4: > * Use the timeout for GLK (Ville) > v3: > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > v2: > * Based on platform, fixed delay or poll (Ville) > * Use a helper to do this (Imre, Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 052a74625a61..94d57b57139b 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > port_name(port)); > } > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > + enum port port) > +{ > + if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv) ) { > + usleep_range(600, 1000); > + return; > + } > + > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 600)) > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > + port_name(port)); > +} > + > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > { > switch (pll->info->id) { > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > - udelay(600); > + intel_wait_ddi_buf_active(dev_priv, port); > } > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > -- > 2.19.1 > From patchwork at emeril.freedesktop.org Mon Jun 29 19:29:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 29 Jun 2020 19:29:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJBVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=5D_drm/i915/gem=3A_Move_obj-=3Elut=5Fli?= =?utf-8?q?st_under_its_own_lock_=28rev3=29?= In-Reply-To: <20200629101256.13039-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> Message-ID: <159345897346.746.605384504129217508@emeril.freedesktop.org> == Series Details == Series: series starting with [v2] drm/i915/gem: Move obj->lut_list under its own lock (rev3) URL : https://patchwork.freedesktop.org/series/78889/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8673 -> Patchwork_18035 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18035 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18035, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18035: ### IGT changes ### #### Possible regressions #### * igt at i915_module_load@reload: - fi-kbl-8809g: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-8809g/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-8809g/igt at i915_module_load@reload.html - fi-cml-u2: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-cml-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-cml-u2/igt at i915_module_load@reload.html - fi-cfl-8700k: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-cfl-8700k/igt at i915_module_load@reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-cfl-8700k/igt at i915_module_load@reload.html - fi-apl-guc: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-apl-guc/igt at i915_module_load@reload.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-apl-guc/igt at i915_module_load@reload.html - fi-snb-2520m: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-snb-2520m/igt at i915_module_load@reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-snb-2520m/igt at i915_module_load@reload.html - fi-bxt-dsi: [PASS][11] -> [INCOMPLETE][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bxt-dsi/igt at i915_module_load@reload.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-bxt-dsi/igt at i915_module_load@reload.html - fi-hsw-4770: [PASS][13] -> [INCOMPLETE][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-hsw-4770/igt at i915_module_load@reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-hsw-4770/igt at i915_module_load@reload.html - fi-kbl-soraka: [PASS][15] -> [INCOMPLETE][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-soraka/igt at i915_module_load@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-soraka/igt at i915_module_load@reload.html - fi-whl-u: [PASS][17] -> [INCOMPLETE][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-whl-u/igt at i915_module_load@reload.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-whl-u/igt at i915_module_load@reload.html - fi-cml-s: [PASS][19] -> [INCOMPLETE][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-cml-s/igt at i915_module_load@reload.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-cml-s/igt at i915_module_load@reload.html - fi-cfl-guc: [PASS][21] -> [INCOMPLETE][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-cfl-guc/igt at i915_module_load@reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-cfl-guc/igt at i915_module_load@reload.html - fi-bsw-n3050: [PASS][23] -> [INCOMPLETE][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bsw-n3050/igt at i915_module_load@reload.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-bsw-n3050/igt at i915_module_load@reload.html - fi-ivb-3770: [PASS][25] -> [INCOMPLETE][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-ivb-3770/igt at i915_module_load@reload.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-ivb-3770/igt at i915_module_load@reload.html - fi-bsw-kefka: [PASS][27] -> [INCOMPLETE][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bsw-kefka/igt at i915_module_load@reload.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-bsw-kefka/igt at i915_module_load@reload.html - fi-tgl-y: [PASS][29] -> [INCOMPLETE][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at i915_module_load@reload.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-tgl-y/igt at i915_module_load@reload.html - fi-skl-guc: [PASS][31] -> [INCOMPLETE][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-skl-guc/igt at i915_module_load@reload.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-skl-guc/igt at i915_module_load@reload.html - fi-kbl-guc: [PASS][33] -> [INCOMPLETE][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-guc/igt at i915_module_load@reload.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-guc/igt at i915_module_load@reload.html - fi-cfl-8109u: [PASS][35] -> [INCOMPLETE][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-cfl-8109u/igt at i915_module_load@reload.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-cfl-8109u/igt at i915_module_load@reload.html - fi-icl-y: [PASS][37] -> [INCOMPLETE][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-y/igt at i915_module_load@reload.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-icl-y/igt at i915_module_load@reload.html #### Warnings #### * igt at i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][39] ([i915#289]) -> [INCOMPLETE][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-u2/igt at i915_module_load@reload.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-icl-u2/igt at i915_module_load@reload.html - fi-tgl-u2: [DMESG-WARN][41] ([i915#402]) -> [INCOMPLETE][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt at i915_module_load@reload.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-tgl-u2/igt at i915_module_load@reload.html - fi-kbl-x1275: [DMESG-WARN][43] ([i915#62] / [i915#92] / [i915#95]) -> [INCOMPLETE][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at i915_module_load@reload.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-x1275/igt at i915_module_load@reload.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt at i915_module_load@reload: - {fi-tgl-dsi}: [PASS][45] -> [INCOMPLETE][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-dsi/igt at i915_module_load@reload.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-tgl-dsi/igt at i915_module_load@reload.html - {fi-kbl-7560u}: [PASS][47] -> [INCOMPLETE][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-7560u/igt at i915_module_load@reload.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-7560u/igt at i915_module_load@reload.html - {fi-ehl-1}: [PASS][49] -> [INCOMPLETE][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-ehl-1/igt at i915_module_load@reload.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-ehl-1/igt at i915_module_load@reload.html Known issues ------------ Here are the changes found in Patchwork_18035 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-skl-6600u: [PASS][51] -> [INCOMPLETE][52] ([i915#69]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-skl-6600u/igt at i915_module_load@reload.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-skl-6600u/igt at i915_module_load@reload.html - fi-byt-n2820: [PASS][53] -> [INCOMPLETE][54] ([i915#45]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-n2820/igt at i915_module_load@reload.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-byt-n2820/igt at i915_module_load@reload.html - fi-glk-dsi: [PASS][55] -> [INCOMPLETE][56] ([i915#58] / [k.org#198133]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-glk-dsi/igt at i915_module_load@reload.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-glk-dsi/igt at i915_module_load@reload.html - fi-snb-2600: [PASS][57] -> [INCOMPLETE][58] ([i915#82]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-snb-2600/igt at i915_module_load@reload.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-snb-2600/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][59] -> [INCOMPLETE][60] ([i915#45]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html - fi-bsw-nick: [PASS][61] -> [INCOMPLETE][62] ([i915#392]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bsw-nick/igt at i915_pm_rpm@module-reload.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-bsw-nick/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-icl-u2: [PASS][63] -> [DMESG-WARN][64] ([i915#1982]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at vgem_basic@setversion: - fi-tgl-y: [PASS][65] -> [DMESG-WARN][66] ([i915#402]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at vgem_basic@setversion.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-tgl-y/igt at vgem_basic@setversion.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-n2820: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at coherency: - fi-gdg-551: [DMESG-FAIL][69] ([i915#1748]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-gdg-551/igt at i915_selftest@live at coherency.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-gdg-551/igt at i915_selftest@live at coherency.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [DMESG-WARN][71] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at kms_busy@basic at flip.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-y: [DMESG-WARN][73] ([i915#1982]) -> [PASS][74] +2 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-tgl-y/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-n3050: [DMESG-WARN][75] ([i915#1982]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][77] ([i915#1982]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at prime_self_import@basic-with_two_bos: - fi-tgl-y: [DMESG-WARN][79] ([i915#402]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at prime_self_import@basic-with_two_bos.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-tgl-y/igt at prime_self_import@basic-with_two_bos.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][81] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][82] ([i915#62] / [i915#92]) +3 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][83] ([i915#62] / [i915#92]) -> [DMESG-WARN][84] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289 [i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (45 -> 39) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8673 -> Patchwork_18035 CI-20190529: 20190529 CI_DRM_8673: ae0a2b45fe022c02a2779c2ae8c83473763c1feb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18035: cfb7c88fb6fe6d3b949e5e5f0ec3d73237f56f0f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cfb7c88fb6fe drm/i915: Switch to object allocations for page directories ae5a264ca1f5 drm/i915: Preallocate stashes for vma page-directories c199e797c70d drm/i915: Export ppgtt_bind_vma 9e557cde27e4 drm/i915/gem: Drop forced struct_mutex from shrinker_taints_mutex 00af2c29ea68 drm/i915/gem: Split the context's obj:vma lut into its own mutex c39cf9cd78da drm/i915/gem: Move obj->lut_list under its own lock == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18035/index.html From patchwork at emeril.freedesktop.org Mon Jun 29 19:33:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Mon, 29 Jun 2020 19:33:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?series_starting_with_=5Bv3=2C1/3=5D_drm/i915/bios=3A_Parse_HOBL?= =?utf-8?q?_parameter_=28rev2=29?= In-Reply-To: <20200625002906.116594-1-jose.souza@intel.com> References: <20200625002906.116594-1-jose.souza@intel.com> Message-ID: <159345923304.746.18331207362539457580@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/3] drm/i915/bios: Parse HOBL parameter (rev2) URL : https://patchwork.freedesktop.org/series/78807/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From jose.souza at intel.com Mon Jun 29 19:41:15 2020 From: jose.souza at intel.com (Souza, Jose) Date: Mon, 29 Jun 2020 19:41:15 +0000 Subject: [Intel-gfx] [PATCH v2 3/5] drm/i915: Add PSR2 selective fetch registers In-Reply-To: <ec989aa029c98e7735c3a457be68137f90dc851f.camel@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> <20200626010151.221388-3-jose.souza@intel.com> <ec989aa029c98e7735c3a457be68137f90dc851f.camel@intel.com> Message-ID: <717d2c6a7b1bfac0e678c4e67041df74ed0da59a.camel@intel.com> On Fri, 2020-06-26 at 15:11 +0100, Mun, Gwan-gyeong wrote: > On Thu, 2020-06-25 at 18:01 -0700, Jos? Roberto de Souza wrote: > > This registers will be used to implement PSR2 manual > > tracking/selective > > fetch. > > > > v2: > > - Fixed typo in _PLANE_SEL_FETCH_BASE > > - Renamed PSR2_MAN_TRK_CTL bits to better match spec names > > - Renamed _PLANE_SEL_FETCH_* to better match spec names > > > > BSpec: 55229 > > BSpec: 50424 > > BSpec: 50420 > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 68 ++++++++++++++++++++++++++++++- > > -- > > 1 file changed, 63 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index f09120cac89a..8b6eb42b63db 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4585,6 +4585,18 @@ enum { > > #define PSR2_SU_STATUS_MASK(frame) (0x3ff << > > PSR2_SU_STATUS_SHIFT(frame)) > > #define PSR2_SU_STATUS_FRAMES 8 > > > > +#define _PSR2_MAN_TRK_CTL_A 0x60910 > > +#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 > > +#define PSR2_MAN_TRK_CTL(tran) _MMIO_T > > RANS2(tran, _PSR2_MAN_TRK_CTL_A) > > +#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) > > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, > > 21) > > +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP( > > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) > > +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GEN > > MASK(20, 11) > > +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIE > > LD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) > > +#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT > > (3) > > +#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) > > +#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) > > + > > /* VGA port control */ > > #define ADPA _MMIO(0x61100) > > #define PCH_ADPA _MMIO(0xe1100) > > @@ -7148,7 +7160,52 @@ enum { > > #define PLANE_COLOR_CTL(pipe, plane) \ > > _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), > > _PLANE_COLOR_CTL_2(pipe)) > > > > -#/* SKL new cursor registers */ > > +#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 > > +#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 > > +#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 > > +#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 > > +#define _SEL_FETCH_PLANE_BASE_5_A 0x70920 > > +#define _SEL_FETCH_PLANE_BASE_6_A 0x70940 > > +#define _SEL_FETCH_PLANE_BASE_7_A 0x70960 > > +#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 > > +#define _SEL_FETCH_PLANE_BASE_1_B 0x70990 > > + > > +#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ > > + _SEL_FETCH_PLANE_BASE_1_A, > > \ > > + _SEL_FETCH_PLANE_BASE_2_A, > > \ > > + _SEL_FETCH_PLANE_BASE_3_A, > > \ > > + _SEL_FETCH_PLANE_BASE_4_A, > > \ > > + _SEL_FETCH_PLANE_BASE_5_A, > > \ > > + _SEL_FETCH_PLANE_BASE_6_A, > > \ > > + _SEL_FETCH_PLANE_BASE_7_A, > > \ > > + _SEL_FETCH_PLANE_BASE_CUR_ > > A) > > +#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, > > _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) > > +#define _SEL_FETCH_PLANE_BASE(pipe, plane) > > (_SEL_FETCH_PLANE_BASE_1(pipe) - \ > > + _SEL_FETCH_PLANE_BASE_1_A + > > \ > > + _SEL_FETCH_PLANE_BASE_A(pla > > ne)) > > + > > +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 > > +#define PLANE_SEL_FETCH_CTL(pipe, plane) > > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > > + _SEL_FETCH_PLANE_CTL_1_A > > - \ > > + _SEL_FETCH_PLANE_BASE_1_ > > A) > > +#define PLANE_SET_FETCH_CTL_ENABLE REG_BIT(31) > it seems a typo of "PLANE_SEL_FETCH_CTL_ENABLE", > except for this line, looks good to me. Yep, thanks for catch up this. > > Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > > + > > +#define _SEL_FETCH_PLANE_POS_1_A 0x70894 > > +#define PLANE_SEL_FETCH_POS(pipe, plane) > > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > > + _SEL_FETCH_PLANE_POS_1_A > > - \ > > + _SEL_FETCH_PLANE_BASE_1_ > > A) > > + > > +#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 > > +#define PLANE_SEL_FETCH_SIZE(pipe, plane) > > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > > + _SEL_FETCH_PLANE_SIZE_1 > > _A - \ > > + _SEL_FETCH_PLANE_BASE_1 > > _A) > > + > > +#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C > > +#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > > + _SEL_FETCH_PLANE_OFFS > > ET_1_A - \ > > + _SEL_FETCH_PLANE_BASE > > _1_A) > > + > > +/* SKL new cursor registers */ > > #define _CUR_BUF_CFG_A 0x7017c > > #define _CUR_BUF_CFG_B 0x7117c > > #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, > > _CUR_BUF_CFG_B) > > @@ -7794,11 +7851,12 @@ enum { > > # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) > > > > -#define CHICKEN_PAR1_1 _MMIO(0x42080) > > +#define CHICKEN_PAR1_1 _MMIO(0x42080) > > #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) > > -#define DPA_MASK_VBLANK_SRD (1 << 15) > > -#define FORCE_ARB_IDLE_PLANES (1 << 14) > > -#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > +#define DPA_MASK_VBLANK_SRD (1 << 15) > > +#define FORCE_ARB_IDLE_PLANES (1 << 14) > > +#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) > > +#define IGNORE_PSR2_HW_TRACKING (1 << 1) > > > > #define CHICKEN_PAR2_1 _MMIO(0x42090) > > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) From khaled.almahallawy at intel.com Mon Jun 29 20:00:26 2020 From: khaled.almahallawy at intel.com (Almahallawy, Khaled) Date: Mon, 29 Jun 2020 20:00:26 +0000 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock In-Reply-To: <20200629185848.20550-1-imre.deak@intel.com> References: <20200629185848.20550-1-imre.deak@intel.com> Message-ID: <a874fc1c32c5c6e849b74362ef2a985b47fdfa9b.camel@intel.com> On Mon, 2020-06-29 at 21:58 +0300, Imre Deak wrote: > When the reference clock is 38.4MHz, using the current TBT PLL > fractional divider value results in a slightly off TBT link > frequency. > This causes an endless loop of link training success followed by a > bad > link signaling and retraining at least on a ThinkPad 40AC TBT > dock. The > workaround provided by the HW team is to divide the fractional > divider > value by two. This fixed the link training problem on the ThinkPad > dock. > > The same workaround is needed on some EHL platforms and for combo PHY > PLLs, these will be addressed in a follow-up. > > Bspec: 49204 > > References: HSDES#22010772725 > References: HSDES#14011861142 > Reported-and-tested-by: Khaled Almahallawy < > khaled.almahallawy at intel.com> > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index b45185b80bec..f585053d02d8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -2937,6 +2937,12 @@ static const struct skl_wrpll_params > tgl_tbt_pll_24MHz_values = { > .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0, > }; > > +static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = { > + .dco_integer = 0x54, .dco_fraction = 0x1800, > + /* the following params are unused */ > + .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0, > +}; > + > static bool icl_calc_dp_combo_pll(struct intel_crtc_state > *crtc_state, > struct skl_wrpll_params *pll_params) > { > @@ -2970,12 +2976,14 @@ static bool icl_calc_tbt_pll(struct > intel_crtc_state *crtc_state, > MISSING_CASE(dev_priv->dpll.ref_clks.nssc); > /* fall-through */ > case 19200: > - case 38400: > *pll_params = tgl_tbt_pll_19_2MHz_values; > break; > case 24000: > *pll_params = tgl_tbt_pll_24MHz_values; > break; > + case 38400: > + *pll_params = tgl_tbt_pll_38_4MHz_values; > + break; > } > } else { > switch (dev_priv->dpll.ref_clks.nssc) { Reviewed-by: Khaled Almahallawy <khaled.almahallawy at intel.com> From jose.souza at intel.com Mon Jun 29 20:06:09 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Mon, 29 Jun 2020 13:06:09 -0700 Subject: [Intel-gfx] [PATCH] drm/i915/ehl: Add new PCI ids Message-ID: <20200629200609.91058-1-jose.souza@intel.com> Two new PCI ids added to ehl. BSpec: 29153 Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- include/drm/i915_pciids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index bc989de2aac2..0c7fcb1632ac 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -588,6 +588,8 @@ INTEL_VGA_DEVICE(0x4551, info), \ INTEL_VGA_DEVICE(0x4541, info), \ INTEL_VGA_DEVICE(0x4E71, info), \ + INTEL_VGA_DEVICE(0x4557, info), \ + INTEL_VGA_DEVICE(0x4555, info), \ INTEL_VGA_DEVICE(0x4E61, info), \ INTEL_VGA_DEVICE(0x4E51, info) -- 2.27.0 From jose.souza at intel.com Mon Jun 29 21:20:58 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Mon, 29 Jun 2020 14:20:58 -0700 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement WA 18011464164 Message-ID: <20200629212059.108460-1-jose.souza@intel.com> This fix some possible corruptions. BSpec: 52755 BSpec: 52890 Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 284af0c6439c..797e036fa695 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4170,6 +4170,9 @@ enum { #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) #define CGPSF_CLKGATE_DIS (1 << 3) +#define SLICE_UNIT_LEVEL_CLOCK_GATING_CTL _MMIO(0x94D8) +#define GS_UNIT_CLOCK_GATING_DIS REG_BIT(24) + /* * Display engine regs */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2a32d6230795..86408173c435 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7113,7 +7113,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(POWERGATE_ENABLE, I915_READ(POWERGATE_ENABLE) | vd_pg_enable); - /* Wa_1409825376:tgl (pre-prod)*/ + /* Wa_1409825376:tgl (pre-prod) */ if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS); @@ -7121,6 +7121,12 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) /* Wa_14011059788:tgl */ intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, 0, DFR_DISABLE); + + /* Wa_18011464164:tgl */ + if (IS_TGL_REVID(dev_priv, TGL_REVID_B0, TGL_REVID_B0)) + intel_uncore_rmw(&dev_priv->uncore, + SLICE_UNIT_LEVEL_CLOCK_GATING_CTL, 0, + GS_UNIT_CLOCK_GATING_DIS); } static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) -- 2.27.0 From jose.souza at intel.com Mon Jun 29 21:20:59 2020 From: jose.souza at intel.com (=?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?=) Date: Mon, 29 Jun 2020 14:20:59 -0700 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: Implement WA 22010931296 In-Reply-To: <20200629212059.108460-1-jose.souza@intel.com> References: <20200629212059.108460-1-jose.souza@intel.com> Message-ID: <20200629212059.108460-2-jose.souza@intel.com> Fix another set of corruption issues. BSpec: 52758 BSpec: 52890 Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..c8bf09efd0dc 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1677,6 +1677,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) * Wa_14010229206:tgl */ wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); + + /* Wa_22010931296:tgl */ + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + TDSUNIT_CLKGATE_DIS); } if (IS_GEN(i915, 11)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 797e036fa695..9b365fc7a644 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4165,6 +4165,7 @@ enum { #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19) +#define TDSUNIT_CLKGATE_DIS REG_BIT(11) #define PSDUNIT_CLKGATE_DIS REG_BIT(5) #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) -- 2.27.0 From jose.souza at intel.com Tue Jun 30 00:02:31 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 30 Jun 2020 00:02:31 +0000 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/icl+: Simplify combo/TBT PLL calculation call-chain In-Reply-To: <20200629185848.20550-2-imre.deak@intel.com> References: <20200629185848.20550-1-imre.deak@intel.com> <20200629185848.20550-2-imre.deak@intel.com> Message-ID: <fbf506b25385a897a4ebfaef7d0272b0eee32049.camel@intel.com> On Mon, 2020-06-29 at 21:58 +0300, Imre Deak wrote: > To simplify things, call the combo PHY/TBT PLL calculation functions > directly from the corresponding combo/TypeC PLL get functions, instead of > calling the same calculation functions after having to recheck if the > given PHY is combo or TypeC. Looks cleaner. Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > > Signed-off-by: Imre Deak <imre.deak at intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 64 ++++++++----------- > 1 file changed, 27 insertions(+), 37 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index f585053d02d8..8306e92dc892 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -3046,49 +3046,26 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, > icl_wrpll_ref_clock(i915)); > } > > -static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, > - struct intel_encoder *encoder, > +static void icl_calc_dpll_state(struct drm_i915_private *i915, > + const struct skl_wrpll_params *pll_params, > struct intel_dpll_hw_state *pll_state) > { > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > - u32 cfgcr0, cfgcr1; > - struct skl_wrpll_params pll_params = { 0 }; > - bool ret; > - > - if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, > - encoder->port))) > - ret = icl_calc_tbt_pll(crtc_state, &pll_params); > - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || > - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) > - ret = icl_calc_wrpll(crtc_state, &pll_params); > - else > - ret = icl_calc_dp_combo_pll(crtc_state, &pll_params); > - > - if (!ret) > - return false; > + memset(pll_state, 0, sizeof(*pll_state)); > > - cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) | > - pll_params.dco_integer; > + pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) | > + pll_params->dco_integer; > > - cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) | > - DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) | > - DPLL_CFGCR1_KDIV(pll_params.kdiv) | > - DPLL_CFGCR1_PDIV(pll_params.pdiv); > + pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) | > + DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) | > + DPLL_CFGCR1_KDIV(pll_params->kdiv) | > + DPLL_CFGCR1_PDIV(pll_params->pdiv); > > - if (INTEL_GEN(dev_priv) >= 12) > - cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; > + if (INTEL_GEN(i915) >= 12) > + pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; > else > - cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; > - > - memset(pll_state, 0, sizeof(*pll_state)); > - > - pll_state->cfgcr0 = cfgcr0; > - pll_state->cfgcr1 = cfgcr1; > - > - return true; > + pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; > } > > - > static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id) > { > return id - DPLL_ID_ICL_MGPLL1; > @@ -3501,19 +3478,29 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, > { > struct intel_crtc_state *crtc_state = > intel_atomic_get_new_crtc_state(state, crtc); > + struct skl_wrpll_params pll_params = { }; > struct icl_port_dpll *port_dpll = > &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum port port = encoder->port; > unsigned long dpll_mask; > + int ret; > > - if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || > + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) > + ret = icl_calc_wrpll(crtc_state, &pll_params); > + else > + ret = icl_calc_dp_combo_pll(crtc_state, &pll_params); > + > + if (!ret) { > drm_dbg_kms(&dev_priv->drm, > "Could not calculate combo PHY PLL state.\n"); > > return false; > } > > + icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); > + > if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A) > dpll_mask = > BIT(DPLL_ID_EHL_DPLL4) | > @@ -3547,16 +3534,19 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > struct intel_crtc_state *crtc_state = > intel_atomic_get_new_crtc_state(state, crtc); > + struct skl_wrpll_params pll_params = { }; > struct icl_port_dpll *port_dpll; > enum intel_dpll_id dpll_id; > > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; > - if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { > + if (!icl_calc_tbt_pll(crtc_state, &pll_params)) { > drm_dbg_kms(&dev_priv->drm, > "Could not calculate TBT PLL state.\n"); > return false; > } > > + icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state); > + > port_dpll->pll = intel_find_shared_dpll(state, crtc, > &port_dpll->hw_state, > BIT(DPLL_ID_ICL_TBTPLL)); From sfr at canb.auug.org.au Tue Jun 30 01:52:02 2020 From: sfr at canb.auug.org.au (Stephen Rothwell) Date: Tue, 30 Jun 2020 11:52:02 +1000 Subject: [Intel-gfx] linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree Message-ID: <20200630115202.04c39f9b@canb.auug.org.au> Hi all, Today's linux-next merge of the drm-intel tree got a conflict in: drivers/gpu/drm/i915/gvt/handlers.c between commit: fc1e3aa0337c ("drm/i915/gvt: Fix incorrect check of enabled bits in mask registers") from the drm-intel-fixes tree and commit: 5f4ae2704d59 ("drm/i915: Identify Cometlake platform") from the drm-intel tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell diff --cc drivers/gpu/drm/i915/gvt/handlers.c index fadd2adb8030,26cae4846c82..000000000000 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@@ -1731,8 -1734,9 +1734,9 @@@ static int ring_mode_mmio_write(struct return 0; } - if (IS_COFFEELAKE(vgpu->gvt->gt->i915) && + if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || + IS_COMETLAKE(vgpu->gvt->gt->i915)) && - data & _MASKED_BIT_ENABLE(2)) { + IS_MASKED_BITS_ENABLED(data, 2)) { enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); return 0; } -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 488 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20200630/7807a7fc/attachment.sig> From linux at roeck-us.net Tue Jun 30 05:39:36 2020 From: linux at roeck-us.net (Guenter Roeck) Date: Mon, 29 Jun 2020 22:39:36 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Protect debugfs per_file_stats with RCU lock In-Reply-To: <20190903062133.27360-1-chris@chris-wilson.co.uk> References: <20190903062133.27360-1-chris@chris-wilson.co.uk> Message-ID: <20200630053936.GA168021@roeck-us.net> On Tue, Sep 03, 2019 at 07:21:33AM +0100, Chris Wilson wrote: > If we make sure we grab a strong reference to each object as we dump it, > we can reduce the locks outside of our iterators to an rcu_read_lock. > > This should prevent errors like: > [ 2138.371911] BUG: KASAN: use-after-free in per_file_stats+0x43/0x380 [i915] > [ 2138.371924] Read of size 8 at addr ffff888223651000 by task cat/8293 > > [ 2138.371947] CPU: 0 PID: 8293 Comm: cat Not tainted 5.3.0-rc6-CI-Custom_4352+ #1 > [ 2138.371953] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./J4205-ITX, BIOS P1.40 07/14/2017 > [ 2138.371959] Call Trace: > [ 2138.371974] dump_stack+0x7c/0xbb > [ 2138.372099] ? per_file_stats+0x43/0x380 [i915] > [ 2138.372108] print_address_description+0x73/0x3a0 > [ 2138.372231] ? per_file_stats+0x43/0x380 [i915] > [ 2138.372352] ? per_file_stats+0x43/0x380 [i915] > [ 2138.372362] __kasan_report+0x14e/0x192 > [ 2138.372489] ? per_file_stats+0x43/0x380 [i915] > [ 2138.372502] kasan_report+0xe/0x20 > [ 2138.372625] per_file_stats+0x43/0x380 [i915] > [ 2138.372751] ? i915_panel_show+0x110/0x110 [i915] > [ 2138.372761] idr_for_each+0xa7/0x160 > [ 2138.372773] ? idr_get_next_ul+0x110/0x110 > [ 2138.372782] ? do_raw_spin_lock+0x10a/0x1d0 > [ 2138.372923] print_context_stats+0x264/0x510 [i915] > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Tested-by: David Weinehall <david.weinehall at linux.intel.com> > Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 9798f27a697a..708855e051b5 100644 [ ... ] > } > @@ -328,9 +334,9 @@ static void print_context_stats(struct seq_file *m, > struct task_struct *task; > char name[80]; > > - spin_lock(&file->table_lock); > + rcu_read_lock(); > idr_for_each(&file->object_idr, per_file_stats, &stats); > - spin_unlock(&file->table_lock); > + rcu_read_unlock(); > For my education - is it indeed possible and valid to replace spin_lock() with rcu_read_lock() to prevent list manipulation for a list used by idr_for_each(), even if that list is otherwise manipulated under the spinlock ? Background: we are seeing a crash with the following call trace. [ 1016.651593] BUG: kernel NULL pointer dereference, address: 0000000000000000 ... [ 1016.651693] Call Trace: [ 1016.651703] idr_for_each+0x8a/0xe8 [ 1016.651711] i915_gem_object_info+0x2a3/0x3eb [ 1016.651720] seq_read+0x162/0x3ca [ 1016.651727] full_proxy_read+0x5b/0x8d [ 1016.651733] __vfs_read+0x45/0x1bb [ 1016.651741] vfs_read+0xc9/0x15e [ 1016.651746] ksys_read+0x7e/0xde [ 1016.651752] do_syscall_64+0x54/0x68 [ 1016.651758] entry_SYSCALL_64_after_hwframe+0x44/0xa9 I have not tried to track down what exactly is NULL in this case. Before spending more time on it, I'd like to understand the above change a little better. Thanks, Guenter From kunal1.joshi at intel.com Tue Jun 30 00:26:57 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Tue, 30 Jun 2020 05:56:57 +0530 Subject: [Intel-gfx] [PATCH v6 0/3] Send a hotplug when edid changes Message-ID: <20200630002700.5451-1-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> This series introduce to drm a way to determine if something else except connection_status had changed during probing, which can be used by other drivers as well. Another i915 specific part uses this approach to determine if edid had changed without changing the connection status and send a hotplug event. Stanislav Lisovskiy (3): drm: Add helper to compare edids. drm: Introduce epoch counter to drm_connector drm/i915: Send hotplug event if edid had changed drivers/gpu/drm/drm_connector.c | 16 +++++++++ drivers/gpu/drm/drm_edid.c | 37 ++++++++++++++++++- drivers/gpu/drm/drm_probe_helper.c | 38 +++++++++++++++++--- drivers/gpu/drm/i915/display/intel_hotplug.c | 24 +++++++------ include/drm/drm_connector.h | 2 ++ include/drm/drm_edid.h | 9 +++++ 6 files changed, 110 insertions(+), 16 deletions(-) -- 2.25.1 From kunal1.joshi at intel.com Tue Jun 30 00:26:58 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Tue, 30 Jun 2020 05:56:58 +0530 Subject: [Intel-gfx] [PATCH v6 1/3] drm: Add helper to compare edids. In-Reply-To: <20200630002700.5451-1-kunal1.joshi@intel.com> References: <20200630002700.5451-1-kunal1.joshi@intel.com> Message-ID: <20200630002700.5451-2-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Many drivers would benefit from using drm helper to compare edid, rather than bothering with own implementation. v2: Added documentation for this function. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/drm_edid.c | 33 +++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 9 +++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 71ae0cd6d576..920ac9ef6018 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1615,6 +1615,39 @@ static bool drm_edid_is_zero(const u8 *in_edid, int length) return true; } +/** + * drm_edid_are_equal - compare two edid blobs. + * @edid1: pointer to first blob + * @edid2: pointer to second blob + * This helper can be used during probing to determine if + * edid had changed. + */ +bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) +{ + int edid1_len, edid2_len; + bool edid1_present = edid1 != NULL; + bool edid2_present = edid2 != NULL; + + if (edid1_present != edid2_present) + return false; + + if (edid1) { + + edid1_len = EDID_LENGTH * (1 + edid1->extensions); + edid2_len = EDID_LENGTH * (1 + edid2->extensions); + + if (edid1_len != edid2_len) + return false; + + if (memcmp(edid1, edid2, edid1_len)) + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_edid_are_equal); + + /** * drm_edid_block_valid - Sanity check the EDID block (base or extension) * @raw_edid: pointer to raw EDID block diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 43254319ab19..cfa4f5af49af 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -359,6 +359,15 @@ drm_load_edid_firmware(struct drm_connector *connector) } #endif +/** + * drm_edid_are_equal - compare two edid blobs. + * @edid1: pointer to first blob + * @edid2: pointer to second blob + * This helper can be used during probing to determine if + * edid had changed. + */ +bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2); + int drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, const struct drm_connector *connector, -- 2.25.1 From kunal1.joshi at intel.com Tue Jun 30 00:26:59 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Tue, 30 Jun 2020 05:56:59 +0530 Subject: [Intel-gfx] [PATCH v6 2/3] drm: Introduce epoch counter to drm_connector In-Reply-To: <20200630002700.5451-1-kunal1.joshi@intel.com> References: <20200630002700.5451-1-kunal1.joshi@intel.com> Message-ID: <20200630002700.5451-3-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> This counter will be used by drm_helper_probe_detect caller to determine if anything had changed(including edid, connection status and etc). Hardware specific driver detect hooks are responsible for updating this counter when some change is detected to notify the drm part, which can trigger for example hotplug event. Also now call drm_connector_update_edid_property right after we get edid always to make sure there is a unified way to handle edid change, without having to change tons of source code as currently drm_connector_update_edid_property is called only in certain cases like reprobing and not right after edid is actually updated. v2: Added documentation for the new counter. Rename change_counter to epoch_counter. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105540 Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/drm_connector.c | 16 +++++++++++++ drivers/gpu/drm/drm_edid.c | 8 ++++--- drivers/gpu/drm/drm_probe_helper.c | 38 ++++++++++++++++++++++++++---- include/drm/drm_connector.h | 2 ++ 4 files changed, 56 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index b7bd46033807..328a6a0dfe32 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -269,6 +269,7 @@ int drm_connector_init(struct drm_device *dev, INIT_LIST_HEAD(&connector->modes); mutex_init(&connector->mutex); connector->edid_blob_ptr = NULL; + connector->epoch_counter = 0; connector->tile_blob_ptr = NULL; connector->status = connector_status_unknown; connector->display_info.panel_orientation = @@ -1979,6 +1980,7 @@ int drm_connector_update_edid_property(struct drm_connector *connector, struct drm_device *dev = connector->dev; size_t size = 0; int ret; + const struct edid *old_edid; /* ignore requests to set edid when overridden */ if (connector->override_edid) @@ -2002,6 +2004,20 @@ int drm_connector_update_edid_property(struct drm_connector *connector, drm_update_tile_info(connector, edid); + if (connector->edid_blob_ptr) { + old_edid = (const struct edid *)connector->edid_blob_ptr->data; + if (old_edid) { + if (!drm_edid_are_equal(edid, old_edid)) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Edid was changed.\n", + connector->base.id, connector->name); + + connector->epoch_counter += 1; + DRM_DEBUG_KMS("Updating change counter to %llu\n", + connector->epoch_counter); + } + } + } + drm_object_property_set_value(&connector->base, dev->mode_config.non_desktop_property, connector->display_info.non_desktop); diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 920ac9ef6018..8b559b82a15e 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -1632,7 +1632,6 @@ bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) return false; if (edid1) { - edid1_len = EDID_LENGTH * (1 + edid1->extensions); edid2_len = EDID_LENGTH * (1 + edid2->extensions); @@ -1647,7 +1646,6 @@ bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) } EXPORT_SYMBOL(drm_edid_are_equal); - /** * drm_edid_block_valid - Sanity check the EDID block (base or extension) * @raw_edid: pointer to raw EDID block @@ -2050,13 +2048,17 @@ EXPORT_SYMBOL(drm_probe_ddc); struct edid *drm_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) { + struct edid *edid; + if (connector->force == DRM_FORCE_OFF) return NULL; if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) return NULL; - return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); + edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); + drm_connector_update_edid_property(connector, edid); + return edid; } EXPORT_SYMBOL(drm_get_edid); diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index 09e872e61315..04a99c17b039 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -292,6 +292,9 @@ drm_helper_probe_detect_ctx(struct drm_connector *connector, bool force) if (WARN_ON(ret < 0)) ret = connector_status_unknown; + if (ret != connector->status) + connector->epoch_counter += 1; + drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); @@ -325,11 +328,16 @@ drm_helper_probe_detect(struct drm_connector *connector, return ret; if (funcs->detect_ctx) - return funcs->detect_ctx(connector, ctx, force); + ret = funcs->detect_ctx(connector, ctx, force); else if (connector->funcs->detect) - return connector->funcs->detect(connector, force); + ret = connector->funcs->detect(connector, force); else - return connector_status_connected; + ret = connector_status_connected; + + if (ret != connector->status) + connector->epoch_counter += 1; + + return ret; } EXPORT_SYMBOL(drm_helper_probe_detect); @@ -779,6 +787,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) struct drm_connector_list_iter conn_iter; enum drm_connector_status old_status; bool changed = false; + u64 old_epoch_counter; if (!dev->mode_config.poll_enabled) return false; @@ -792,20 +801,39 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) old_status = connector->status; + old_epoch_counter = connector->epoch_counter; + + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Old epoch counter %llu\n", connector->base.id, + connector->name, + old_epoch_counter); + connector->status = drm_helper_probe_detect(connector, NULL, false); DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", connector->base.id, connector->name, drm_get_connector_status_name(old_status), drm_get_connector_status_name(connector->status)); - if (old_status != connector->status) + + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] New epoch counter %llu\n", + connector->base.id, + connector->name, + connector->epoch_counter); + + /* + * Check if epoch counter had changed, meaning that we need + * to send a uevent. + */ + if (old_epoch_counter != connector->epoch_counter) changed = true; + } drm_connector_list_iter_end(&conn_iter); mutex_unlock(&dev->mode_config.mutex); - if (changed) + if (changed) { drm_kms_helper_hotplug_event(dev); + DRM_DEBUG_KMS("Sent hotplug event\n"); + } return changed; } diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index fd543d1db9b2..6a451b86c454 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -1329,6 +1329,8 @@ struct drm_connector { enum drm_connector_force force; /** @override_edid: has the EDID been overwritten through debugfs for testing? */ bool override_edid; + /** @epoch_counter: used to detect any other changes in connector, besides status */ + u64 epoch_counter; /** * @possible_encoders: Bit mask of encoders that can drive this -- 2.25.1 From kunal1.joshi at intel.com Tue Jun 30 00:27:00 2020 From: kunal1.joshi at intel.com (Kunal Joshi) Date: Tue, 30 Jun 2020 05:57:00 +0530 Subject: [Intel-gfx] [PATCH v6 3/3] drm/i915: Send hotplug event if edid had changed In-Reply-To: <20200630002700.5451-1-kunal1.joshi@intel.com> References: <20200630002700.5451-1-kunal1.joshi@intel.com> Message-ID: <20200630002700.5451-4-kunal1.joshi@intel.com> From: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> Added epoch counter checking to intel_encoder_hotplug in order to be able process all the connector changes, besides connection status. Also now any change in connector would result in epoch counter change, so no multiple checks are needed. v2: Renamed change counter to epoch counter. Fixed type name. v3: Fixed rebase conflict v4: Remove duplicate drm_edid_equal checks from hdmi and dp, lets use only once edid property is getting updated and increment epoch counter from there. Also lets now call drm_connector_update_edid_property right after we get edid always to make sure there is a unified way to handle edid change, without having to change tons of source code as currently drm_connector_update_edid_property is called only in certain cases like reprobing and not right after edid is actually updated. v5: Fixed const modifiers, removed blank line v6: Removed drm specific part from this patch, leaving only i915 specific changes here. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/i915/display/intel_hotplug.c | 24 ++++++++++++-------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 2e94c1413c02..80bcfff032e9 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -283,6 +283,8 @@ intel_encoder_hotplug(struct intel_encoder *encoder, { struct drm_device *dev = connector->base.dev; enum drm_connector_status old_status; + u64 old_epoch_counter; + bool ret = false; drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex)); old_status = connector->base.status; @@ -290,17 +292,19 @@ intel_encoder_hotplug(struct intel_encoder *encoder, connector->base.status = drm_helper_probe_detect(&connector->base, NULL, false); - if (old_status == connector->base.status) - return INTEL_HOTPLUG_UNCHANGED; - - drm_dbg_kms(&to_i915(dev)->drm, - "[CONNECTOR:%d:%s] status updated from %s to %s\n", - connector->base.base.id, - connector->base.name, - drm_get_connector_status_name(old_status), - drm_get_connector_status_name(connector->base.status)); + if (old_epoch_counter != connector->base.epoch_counter) + ret = true; - return INTEL_HOTPLUG_CHANGED; + if (ret) { + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s(epoch counter %llu)\n", + connector->base.base.id, + connector->base.name, + drm_get_connector_status_name(old_status), + drm_get_connector_status_name(connector->base.status), + connector->base.epoch_counter); + return INTEL_HOTPLUG_CHANGED; + } + return INTEL_HOTPLUG_UNCHANGED; } static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder) -- 2.25.1 From jani.nikula at linux.intel.com Tue Jun 30 08:06:30 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 11:06:30 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: HDCP: retry link integrity check on failure In-Reply-To: <20200505121213.GA24840@intel.com> References: <20200504123524.7731-1-oliver.barta@aptiv.com> <20200505073809.GA24093@intel.com> <CALJK04P5A0TV=eQ3QnmXNGbe76i5eUB+hdDxtTkyhV8kfpPeNQ@mail.gmail.com> <20200505121213.GA24840@intel.com> Message-ID: <87k0zpm0zd.fsf@intel.com> On Tue, 05 May 2020, Ramalingam C <ramalingam.c at intel.com> wrote: > On 2020-05-05 at 14:06:51 +0200, Oliver Barta wrote: >> On Tue, May 5, 2020 at 9:38 AM Ramalingam C <ramalingam.c at intel.com> wrote: >> > >> > On 2020-05-04 at 14:35:24 +0200, Oliver Barta wrote: >> > > From: Oliver Barta <oliver.barta at aptiv.com> >> > > >> > > A single Ri mismatch doesn't automatically mean that the link integrity >> > > is broken. Update and check of Ri and Ri' are done asynchronously. In >> > > case an update happens just between the read of Ri' and the check against >> > > Ri there will be a mismatch even if the link integrity is fine otherwise. >> > >> > Thanks for working on this. Btw, did you face this sporadic link check >> > failure or theoretically you are fixing it? >> > >> > IMO this change will rule out possible sporadic link check failures as >> > mentioned in the commit msg. Though I haven't faced this issue at my >> > testings. >> > >> > Reviewed-by: Ramalingam C <ramalingam.c at intel.com> >> > >> >> I found it by code inspection, the probability for this to happen is >> very low. In order to test the patch I'm decreasing the value of >> DRM_HDCP_CHECK_PERIOD_MS to just a few ms. Once you do that it happens >> every few seconds. > Ok. That make sense. Thanks for the explanation. Finally pushed, thanks for the patch and reviews. Ram, I was kind of expecting you to push this. BR, Jani. > > -Ram >> >> Thanks, >> Oliver >> >> > > >> > > Signed-off-by: Oliver Barta <oliver.barta at aptiv.com> >> > > --- >> > > drivers/gpu/drm/i915/display/intel_hdmi.c | 19 ++++++++++++++++--- >> > > 1 file changed, 16 insertions(+), 3 deletions(-) >> > > >> > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c >> > > index 010f37240710..3156fde392f2 100644 >> > > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c >> > > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c >> > > @@ -1540,7 +1540,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, >> > > } >> > > >> > > static >> > > -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) >> > > +bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *intel_dig_port) >> > > { >> > > struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); >> > > struct intel_connector *connector = >> > > @@ -1563,8 +1563,7 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) >> > > if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & >> > > (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == >> > > (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { >> > > - drm_err(&i915->drm, >> > > - "Ri' mismatch detected, link check failed (%x)\n", >> > > + drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", >> > > intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, >> > > port))); >> > > return false; >> > > @@ -1572,6 +1571,20 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) >> > > return true; >> > > } >> > > >> > > +static >> > > +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) >> > > +{ >> > > + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); >> > > + int retry; >> > > + >> > > + for (retry = 0; retry < 3; retry++) >> > > + if (intel_hdmi_hdcp_check_link_once(intel_dig_port)) >> > > + return true; >> > > + >> > > + drm_err(&i915->drm, "Link check failed\n"); >> > > + return false; >> > > +} >> > > + >> > > struct hdcp2_hdmi_msg_timeout { >> > > u8 msg_id; >> > > u16 timeout; >> > > -- >> > > 2.20.1 >> > > -- Jani Nikula, Intel Open Source Graphics Center From patchwork at emeril.freedesktop.org Tue Jun 30 08:17:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 08:17:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv3=2C1/3=5D_drm/i915/bios=3A_Parse_HOBL_pa?= =?utf-8?q?rameter_=28rev2=29?= In-Reply-To: <20200625002906.116594-1-jose.souza@intel.com> References: <20200625002906.116594-1-jose.souza@intel.com> Message-ID: <159350507762.22704.4586009353707117276@emeril.freedesktop.org> == Series Details == Series: series starting with [v3,1/3] drm/i915/bios: Parse HOBL parameter (rev2) URL : https://patchwork.freedesktop.org/series/78807/ State : success == Summary == CI Bug Log - changes from CI_DRM_8673 -> Patchwork_18036 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/index.html Known issues ------------ Here are the changes found in Patchwork_18036 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_flink_basic@bad-open: - fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at gem_flink_basic@bad-open.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-tgl-y/igt at gem_flink_basic@bad-open.html * igt at i915_module_load@reload: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-byt-j1900/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-kefka: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at gem_exec_suspend@basic-s3: - fi-tgl-u2: [FAIL][11] ([i915#1888]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-tgl-u2/igt at gem_exec_suspend@basic-s3.html * igt at gem_flink_basic@double-flink: - fi-tgl-y: [DMESG-WARN][13] ([i915#402]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at gem_flink_basic@double-flink.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-tgl-y/igt at gem_flink_basic@double-flink.html * igt at i915_module_load@reload: - fi-tgl-u2: [DMESG-WARN][15] ([i915#402]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-u2/igt at i915_module_load@reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-n2820: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-byt-n2820/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at coherency: - fi-gdg-551: [DMESG-FAIL][21] ([i915#1748]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-gdg-551/igt at i915_selftest@live at coherency.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-gdg-551/igt at i915_selftest@live at coherency.html * igt at i915_selftest@live at gt_pm: - fi-icl-y: [DMESG-FAIL][23] ([i915#2111]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-y/igt at i915_selftest@live at gt_pm.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-icl-y/igt at i915_selftest@live at gt_pm.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][25] ([i915#1982]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html * igt at kms_psr@primary_page_flip: - fi-tgl-y: [DMESG-WARN][27] ([i915#1982]) -> [PASS][28] +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-tgl-y/igt at kms_psr@primary_page_flip.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-tgl-y/igt at kms_psr@primary_page_flip.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +6 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92]) -> [DMESG-WARN][32] ([i915#62] / [i915#92] / [i915#95]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8673/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/fi-kbl-x1275/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [i915#1748]: https://gitlab.freedesktop.org/drm/intel/issues/1748 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2111]: https://gitlab.freedesktop.org/drm/intel/issues/2111 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (45 -> 39) ------------------------------ Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper Build changes ------------- * Linux: CI_DRM_8673 -> Patchwork_18036 CI-20190529: 20190529 CI_DRM_8673: ae0a2b45fe022c02a2779c2ae8c83473763c1feb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18036: 10b714937aa57067005770b803c88b83e28d33dc @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 10b714937aa5 drm/i915/display: Enable HOBL regardless the VBT value 722bca258f91 drm/i915/display: Implement HOBL 2d0792c76f54 drm/i915/bios: Parse HOBL parameter == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18036/index.html From anshuman.gupta at intel.com Tue Jun 30 08:20:48 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Tue, 30 Jun 2020 13:50:48 +0530 Subject: [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state Message-ID: <20200630082048.22308-1-anshuman.gupta@intel.com> Content Protection property should be updated as per the kernel internal state. Let's say if Content protection is disabled by userspace, CP property should be set to UNDESIRED so that reauthentication will not happen until userspace request it again, but when kernel disables the HDCP due to any DDI disabling sequences like modeset/DPMS operation, kernel should set the property to DESIRED, so that when opportunity arises, kernel will start the HDCP authentication on its own. Somewhere in the line, state machine to set content protection to DESIRED from kernel was broken and IGT coverage was missing for it. This patch fixes it. v2: - Fixing hdcp CP state in connector atomic check function intel_hdcp_atomic_check(). [Maarten] This will require to check hdcp->value in intel_hdcp_update_pipe() in order to avoid enabling hdcp, if it was already enabled. v3: - Rebased. Cc: Ramalingam C <ramalingam.c at intel.com> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Reviewed-by: Uma Shankar <uma.shankar at intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com> Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1 Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2 --- drivers/gpu/drm/i915/display/intel_hdcp.c | 27 +++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 815b054bb167..0d410652e194 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2086,6 +2086,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, (conn_state->hdcp_content_type != hdcp->content_type && conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED); + bool desired_and_not_enabled = false; /* * During the HDCP encryption session if Type change is requested, @@ -2108,8 +2109,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, } if (conn_state->content_protection == - DRM_MODE_CONTENT_PROTECTION_DESIRED || - content_protection_type_changed) + DRM_MODE_CONTENT_PROTECTION_DESIRED) { + mutex_lock(&hdcp->mutex); + /* Avoid enabling hdcp, if it already ENABLED */ + desired_and_not_enabled = + hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; + mutex_unlock(&hdcp->mutex); + } + + if (desired_and_not_enabled || content_protection_type_changed) intel_hdcp_enable(connector, crtc_state->cpu_transcoder, (u8)conn_state->hdcp_content_type); @@ -2158,6 +2166,19 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, return; } + crtc_state = drm_atomic_get_new_crtc_state(new_state->state, + new_state->crtc); + /* + * Fix the HDCP uapi content protection state in case of modeset. + * FIXME: As per HDCP content protection property uapi doc, an uevent() + * need to be sent if there is transition from ENABLED->DESIRED. + */ + if (drm_atomic_crtc_needs_modeset(crtc_state) && + (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && + new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) + new_state->content_protection = + DRM_MODE_CONTENT_PROTECTION_DESIRED; + /* * Nothing to do if the state didn't change, or HDCP was activated since * the last commit. And also no change in hdcp content type. @@ -2170,8 +2191,6 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, return; } - crtc_state = drm_atomic_get_new_crtc_state(new_state->state, - new_state->crtc); crtc_state->mode_changed = true; } -- 2.26.2 From kai.heng.feng at canonical.com Tue Jun 30 08:37:16 2020 From: kai.heng.feng at canonical.com (Kai-Heng Feng) Date: Tue, 30 Jun 2020 16:37:16 +0800 Subject: [Intel-gfx] [PATCH v6] drm/i915: Init lspcon after HPD in intel_dp_detect() In-Reply-To: <20200610075542.12882-1-kai.heng.feng@canonical.com> References: <20200610075542.12882-1-kai.heng.feng@canonical.com> Message-ID: <21A619C1-627F-49CC-B2F4-9B533F351DF3@canonical.com> > On Jun 10, 2020, at 15:55, Kai-Heng Feng <kai.heng.feng at canonical.com> wrote: > > On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port > becomes useless and never responds to cable hotplugging: > [ 3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon > [ 3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D > > Seems like the lspcon chip on the system only gets powered after the > cable is plugged. > > Consilidate lspcon_init() into lspcon_resume() to dynamically init > lspcon chip, and make HDMI port work. > > Signed-off-by: Kai-Heng Feng <kai.heng.feng at canonical.com> A gentle ping... > --- > v6: > - Rebase on latest for-linux-next. > > v5: > - Consolidate lspcon_resume() with lspcon_init(). > - Move more logic into lspcon code. > > v4: > - Trust VBT in intel_infoframe_init(). > - Init lspcon in intel_dp_detect(). > > v3: > - Make sure it's handled under long HPD case. > > v2: > - Move lspcon_init() inside of intel_dp_hpd_pulse(). > > drivers/gpu/drm/i915/display/intel_ddi.c | 19 +------ > drivers/gpu/drm/i915/display/intel_dp.c | 10 ++-- > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +- > drivers/gpu/drm/i915/display/intel_lspcon.c | 63 ++++++++++++--------- > drivers/gpu/drm/i915/display/intel_lspcon.h | 3 +- > 5 files changed, 43 insertions(+), 55 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index aa22465bb56e..af755b1aa24b 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4805,7 +4805,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > { > struct intel_digital_port *intel_dig_port; > struct intel_encoder *encoder; > - bool init_hdmi, init_dp, init_lspcon = false; > + bool init_hdmi, init_dp; > enum phy phy = intel_port_to_phy(dev_priv, port); > > init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || > @@ -4819,7 +4819,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > * is initialized before lspcon. > */ > init_dp = true; > - init_lspcon = true; > init_hdmi = false; > drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", > port_name(port)); > @@ -4904,22 +4903,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) > goto err; > } > > - if (init_lspcon) { > - if (lspcon_init(intel_dig_port)) > - /* TODO: handle hdmi info frame part */ > - drm_dbg_kms(&dev_priv->drm, > - "LSPCON init success on port %c\n", > - port_name(port)); > - else > - /* > - * LSPCON init faied, but DP init was success, so > - * lets try to drive as DP++ port. > - */ > - drm_err(&dev_priv->drm, > - "LSPCON init failed on port %c\n", > - port_name(port)); > - } > - > if (INTEL_GEN(dev_priv) >= 11) { > if (intel_phy_is_tc(dev_priv, phy)) > intel_dig_port->connected = intel_tc_port_connected; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index ed9e53c373a7..398a104158a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5962,15 +5962,14 @@ static enum drm_connector_status > intel_dp_detect_dpcd(struct intel_dp *intel_dp) > { > struct drm_i915_private *i915 = dp_to_i915(intel_dp); > - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > u8 *dpcd = intel_dp->dpcd; > u8 type; > > if (WARN_ON(intel_dp_is_edp(intel_dp))) > return connector_status_connected; > > - if (lspcon->active) > - lspcon_resume(lspcon); > + lspcon_resume(dig_port); > > if (!intel_dp_get_dpcd(intel_dp)) > return connector_status_disconnected; > @@ -7056,14 +7055,13 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder) > { > struct drm_i915_private *dev_priv = to_i915(encoder->dev); > struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); > - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); > + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > intel_wakeref_t wakeref; > > if (!HAS_DDI(dev_priv)) > intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); > > - if (lspcon->active) > - lspcon_resume(lspcon); > + lspcon_resume(dig_port); > > intel_dp->reset_link_params = true; > > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c > index 010f37240710..643ad2127931 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -3155,7 +3155,8 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port) > intel_dig_port->set_infoframes = g4x_set_infoframes; > intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; > } else if (HAS_DDI(dev_priv)) { > - if (intel_dig_port->lspcon.active) { > + if (intel_bios_is_lspcon_present(dev_priv, > + intel_dig_port->base.port)) { > intel_dig_port->write_infoframe = lspcon_write_infoframe; > intel_dig_port->read_infoframe = lspcon_read_infoframe; > intel_dig_port->set_infoframes = lspcon_set_infoframes; > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c > index 6ff7b226f0a1..e3dde4c25604 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > @@ -525,44 +525,17 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, > return 0; > } > > -void lspcon_resume(struct intel_lspcon *lspcon) > -{ > - enum drm_lspcon_mode expected_mode; > - > - if (lspcon_wake_native_aux_ch(lspcon)) { > - expected_mode = DRM_LSPCON_MODE_PCON; > - lspcon_resume_in_pcon_wa(lspcon); > - } else { > - expected_mode = DRM_LSPCON_MODE_LS; > - } > - > - if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) > - return; > - > - if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) > - DRM_ERROR("LSPCON resume failed\n"); > - else > - DRM_DEBUG_KMS("LSPCON resume success\n"); > -} > - > void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) > { > lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); > } > > -bool lspcon_init(struct intel_digital_port *intel_dig_port) > +static bool lspcon_init(struct intel_digital_port *intel_dig_port) > { > struct intel_dp *dp = &intel_dig_port->dp; > struct intel_lspcon *lspcon = &intel_dig_port->lspcon; > - struct drm_device *dev = intel_dig_port->base.base.dev; > - struct drm_i915_private *dev_priv = to_i915(dev); > struct drm_connector *connector = &dp->attached_connector->base; > > - if (!HAS_LSPCON(dev_priv)) { > - DRM_ERROR("LSPCON is not supported on this platform\n"); > - return false; > - } > - > lspcon->active = false; > lspcon->mode = DRM_LSPCON_MODE_INVALID; > > @@ -586,3 +559,37 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) > DRM_DEBUG_KMS("Success: LSPCON init\n"); > return true; > } > + > +void lspcon_resume(struct intel_digital_port *intel_dig_port) > +{ > + struct intel_lspcon *lspcon = &intel_dig_port->lspcon; > + struct drm_device *dev = intel_dig_port->base.base.dev; > + struct drm_i915_private *dev_priv = to_i915(dev); > + enum drm_lspcon_mode expected_mode; > + > + if (!intel_bios_is_lspcon_present(dev_priv, intel_dig_port->base.port)) > + return; > + > + if (!lspcon->active) { > + if (!lspcon_init(intel_dig_port)) { > + DRM_ERROR("LSPCON init failed on port %c\n", > + port_name(intel_dig_port->base.port)); > + return; > + } > + } > + > + if (lspcon_wake_native_aux_ch(lspcon)) { > + expected_mode = DRM_LSPCON_MODE_PCON; > + lspcon_resume_in_pcon_wa(lspcon); > + } else { > + expected_mode = DRM_LSPCON_MODE_LS; > + } > + > + if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON) > + return; > + > + if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) > + DRM_ERROR("LSPCON resume failed\n"); > + else > + DRM_DEBUG_KMS("LSPCON resume success\n"); > +} > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h > index 37cfddf8a9c5..169db35db13e 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.h > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h > @@ -15,8 +15,7 @@ struct intel_digital_port; > struct intel_encoder; > struct intel_lspcon; > > -bool lspcon_init(struct intel_digital_port *intel_dig_port); > -void lspcon_resume(struct intel_lspcon *lspcon); > +void lspcon_resume(struct intel_digital_port *intel_dig_port); > void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); > void lspcon_write_infoframe(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > -- > 2.17.1 > From chris at chris-wilson.co.uk Tue Jun 30 09:14:25 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 10:14:25 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Protect debugfs per_file_stats with RCU lock In-Reply-To: <20200630053936.GA168021@roeck-us.net> References: <20190903062133.27360-1-chris@chris-wilson.co.uk> <20200630053936.GA168021@roeck-us.net> Message-ID: <159350846525.9830.11510134258802464713@build.alporthouse.com> Quoting Guenter Roeck (2020-06-30 06:39:36) > On Tue, Sep 03, 2019 at 07:21:33AM +0100, Chris Wilson wrote: > > If we make sure we grab a strong reference to each object as we dump it, > > we can reduce the locks outside of our iterators to an rcu_read_lock. > > > > This should prevent errors like: > > [ 2138.371911] BUG: KASAN: use-after-free in per_file_stats+0x43/0x380 [i915] > > [ 2138.371924] Read of size 8 at addr ffff888223651000 by task cat/8293 > > > > [ 2138.371947] CPU: 0 PID: 8293 Comm: cat Not tainted 5.3.0-rc6-CI-Custom_4352+ #1 > > [ 2138.371953] Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./J4205-ITX, BIOS P1.40 07/14/2017 > > [ 2138.371959] Call Trace: > > [ 2138.371974] dump_stack+0x7c/0xbb > > [ 2138.372099] ? per_file_stats+0x43/0x380 [i915] > > [ 2138.372108] print_address_description+0x73/0x3a0 > > [ 2138.372231] ? per_file_stats+0x43/0x380 [i915] > > [ 2138.372352] ? per_file_stats+0x43/0x380 [i915] > > [ 2138.372362] __kasan_report+0x14e/0x192 > > [ 2138.372489] ? per_file_stats+0x43/0x380 [i915] > > [ 2138.372502] kasan_report+0xe/0x20 > > [ 2138.372625] per_file_stats+0x43/0x380 [i915] > > [ 2138.372751] ? i915_panel_show+0x110/0x110 [i915] > > [ 2138.372761] idr_for_each+0xa7/0x160 > > [ 2138.372773] ? idr_get_next_ul+0x110/0x110 > > [ 2138.372782] ? do_raw_spin_lock+0x10a/0x1d0 > > [ 2138.372923] print_context_stats+0x264/0x510 [i915] > > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > > Tested-by: David Weinehall <david.weinehall at linux.intel.com> > > Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > index 9798f27a697a..708855e051b5 100644 > [ ... ] > > } > > @@ -328,9 +334,9 @@ static void print_context_stats(struct seq_file *m, > > struct task_struct *task; > > char name[80]; > > > > - spin_lock(&file->table_lock); > > + rcu_read_lock(); > > idr_for_each(&file->object_idr, per_file_stats, &stats); > > - spin_unlock(&file->table_lock); > > + rcu_read_unlock(); > > > For my education - is it indeed possible and valid to replace spin_lock() > with rcu_read_lock() to prevent list manipulation for a list used by > idr_for_each(), even if that list is otherwise manipulated under the > spinlock ? It's a pure read of a radixtree here, and is supposed to be RCU safe: * idr_for_each() can be called concurrently with idr_alloc() and * idr_remove() if protected by RCU. Newly added entries may not be * seen and deleted entries may be seen, but adding and removing entries * will not cause other entries to be skipped, nor spurious ones to be seen. That is the tree structure is stable. > Background: we are seeing a crash with the following call trace. > > [ 1016.651593] BUG: kernel NULL pointer dereference, address: 0000000000000000 > ... > [ 1016.651693] Call Trace: > [ 1016.651703] idr_for_each+0x8a/0xe8 > [ 1016.651711] i915_gem_object_info+0x2a3/0x3eb > [ 1016.651720] seq_read+0x162/0x3ca > [ 1016.651727] full_proxy_read+0x5b/0x8d > [ 1016.651733] __vfs_read+0x45/0x1bb > [ 1016.651741] vfs_read+0xc9/0x15e > [ 1016.651746] ksys_read+0x7e/0xde > [ 1016.651752] do_syscall_64+0x54/0x68 > [ 1016.651758] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Is there a reason you are using this slow debugfs in the first place? -Chris From jani.nikula at linux.intel.com Tue Jun 30 09:41:11 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 12:41:11 +0300 Subject: [Intel-gfx] [PATCH][next] drm/i915: fix a couple of spelling mistakes in kernel parameter help text In-Reply-To: <20200616082129.65517-1-colin.king@canonical.com> References: <20200616082129.65517-1-colin.king@canonical.com> Message-ID: <87ftacnb60.fsf@intel.com> On Tue, 16 Jun 2020, Colin King <colin.king at canonical.com> wrote: > From: Colin Ian King <colin.king at canonical.com> > > There are a couple of spelling mistakes in kernel parameter help text, > namely "helpfull" and "paramters". Fix them. > > Signed-off-by: Colin Ian King <colin.king at canonical.com> Pushed, thanks for the patch. BR, Jani. > --- > drivers/gpu/drm/i915/i915_params.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c > index a7b61e6ec508..8d8db9ff0a48 100644 > --- a/drivers/gpu/drm/i915/i915_params.c > +++ b/drivers/gpu/drm/i915/i915_params.c > @@ -99,8 +99,8 @@ i915_param_named_unsafe(enable_psr, int, 0400, > > i915_param_named(psr_safest_params, bool, 0400, > "Replace PSR VBT parameters by the safest and not optimal ones. This " > - "is helpfull to detect if PSR issues are related to bad values set in " > - " VBT. (0=use VBT paramters, 1=use safest parameters)"); > + "is helpful to detect if PSR issues are related to bad values set in " > + " VBT. (0=use VBT parameters, 1=use safest parameters)"); > > i915_param_named_unsafe(force_probe, charp, 0400, > "Force probe the driver for specified devices. " -- Jani Nikula, Intel Open Source Graphics Center From joro at 8bytes.org Tue Jun 30 10:00:14 2020 From: joro at 8bytes.org (Joerg Roedel) Date: Tue, 30 Jun 2020 12:00:14 +0200 Subject: [Intel-gfx] [PATCH 00/13] iommu: Remove usage of dev->archdata.iommu In-Reply-To: <20200625130836.1916-1-joro@8bytes.org> References: <20200625130836.1916-1-joro@8bytes.org> Message-ID: <20200630100013.GJ28824@8bytes.org> On Thu, Jun 25, 2020 at 03:08:23PM +0200, Joerg Roedel wrote: > Joerg Roedel (13): > iommu/exynos: Use dev_iommu_priv_get/set() > iommu/vt-d: Use dev_iommu_priv_get/set() > iommu/msm: Use dev_iommu_priv_get/set() > iommu/omap: Use dev_iommu_priv_get/set() > iommu/rockchip: Use dev_iommu_priv_get/set() > iommu/tegra: Use dev_iommu_priv_get/set() > iommu/pamu: Use dev_iommu_priv_get/set() > iommu/mediatek: Do no use dev->archdata.iommu > x86: Remove dev->archdata.iommu pointer > ia64: Remove dev->archdata.iommu pointer > arm: Remove dev->archdata.iommu pointer > arm64: Remove dev->archdata.iommu pointer > powerpc/dma: Remove dev->archdata.iommu_domain Applied. From jani.nikula at intel.com Tue Jun 30 10:00:27 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 13:00:27 +0300 Subject: [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state In-Reply-To: <20200630082048.22308-1-anshuman.gupta@intel.com> References: <20200630082048.22308-1-anshuman.gupta@intel.com> Message-ID: <87d05gna9w.fsf@intel.com> Uma, is the R-b still valid? It's been a while. BR, Jani. On Tue, 30 Jun 2020, Anshuman Gupta <anshuman.gupta at intel.com> wrote: > Content Protection property should be updated as per the kernel > internal state. Let's say if Content protection is disabled > by userspace, CP property should be set to UNDESIRED so that > reauthentication will not happen until userspace request it again, > but when kernel disables the HDCP due to any DDI disabling sequences > like modeset/DPMS operation, kernel should set the property to > DESIRED, so that when opportunity arises, kernel will start the > HDCP authentication on its own. > > Somewhere in the line, state machine to set content protection to > DESIRED from kernel was broken and IGT coverage was missing for it. > This patch fixes it. > > v2: > - Fixing hdcp CP state in connector atomic check function > intel_hdcp_atomic_check(). [Maarten] > This will require to check hdcp->value in intel_hdcp_update_pipe() > in order to avoid enabling hdcp, if it was already enabled. > > v3: > - Rebased. > > Cc: Ramalingam C <ramalingam.c at intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Reviewed-by: Uma Shankar <uma.shankar at intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com> > Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1 > Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2 > --- > drivers/gpu/drm/i915/display/intel_hdcp.c | 27 +++++++++++++++++++---- > 1 file changed, 23 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 815b054bb167..0d410652e194 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -2086,6 +2086,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, > (conn_state->hdcp_content_type != hdcp->content_type && > conn_state->content_protection != > DRM_MODE_CONTENT_PROTECTION_UNDESIRED); > + bool desired_and_not_enabled = false; > > /* > * During the HDCP encryption session if Type change is requested, > @@ -2108,8 +2109,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, > } > > if (conn_state->content_protection == > - DRM_MODE_CONTENT_PROTECTION_DESIRED || > - content_protection_type_changed) > + DRM_MODE_CONTENT_PROTECTION_DESIRED) { > + mutex_lock(&hdcp->mutex); > + /* Avoid enabling hdcp, if it already ENABLED */ > + desired_and_not_enabled = > + hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; > + mutex_unlock(&hdcp->mutex); > + } > + > + if (desired_and_not_enabled || content_protection_type_changed) > intel_hdcp_enable(connector, > crtc_state->cpu_transcoder, > (u8)conn_state->hdcp_content_type); > @@ -2158,6 +2166,19 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, > return; > } > > + crtc_state = drm_atomic_get_new_crtc_state(new_state->state, > + new_state->crtc); > + /* > + * Fix the HDCP uapi content protection state in case of modeset. > + * FIXME: As per HDCP content protection property uapi doc, an uevent() > + * need to be sent if there is transition from ENABLED->DESIRED. > + */ > + if (drm_atomic_crtc_needs_modeset(crtc_state) && > + (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && > + new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) > + new_state->content_protection = > + DRM_MODE_CONTENT_PROTECTION_DESIRED; > + > /* > * Nothing to do if the state didn't change, or HDCP was activated since > * the last commit. And also no change in hdcp content type. > @@ -2170,8 +2191,6 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, > return; > } > > - crtc_state = drm_atomic_get_new_crtc_state(new_state->state, > - new_state->crtc); > crtc_state->mode_changed = true; > } -- Jani Nikula, Intel Open Source Graphics Center From jani.nikula at intel.com Tue Jun 30 10:01:06 2020 From: jani.nikula at intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 13:01:06 +0300 Subject: [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state In-Reply-To: <20200630082048.22308-1-anshuman.gupta@intel.com> References: <20200630082048.22308-1-anshuman.gupta@intel.com> Message-ID: <87a70kna8t.fsf@intel.com> Sean, Ram, good to go? BR, Jani. On Tue, 30 Jun 2020, Anshuman Gupta <anshuman.gupta at intel.com> wrote: > Content Protection property should be updated as per the kernel > internal state. Let's say if Content protection is disabled > by userspace, CP property should be set to UNDESIRED so that > reauthentication will not happen until userspace request it again, > but when kernel disables the HDCP due to any DDI disabling sequences > like modeset/DPMS operation, kernel should set the property to > DESIRED, so that when opportunity arises, kernel will start the > HDCP authentication on its own. > > Somewhere in the line, state machine to set content protection to > DESIRED from kernel was broken and IGT coverage was missing for it. > This patch fixes it. > > v2: > - Fixing hdcp CP state in connector atomic check function > intel_hdcp_atomic_check(). [Maarten] > This will require to check hdcp->value in intel_hdcp_update_pipe() > in order to avoid enabling hdcp, if it was already enabled. > > v3: > - Rebased. > > Cc: Ramalingam C <ramalingam.c at intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Reviewed-by: Uma Shankar <uma.shankar at intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com> > Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1 > Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2 > --- > drivers/gpu/drm/i915/display/intel_hdcp.c | 27 +++++++++++++++++++---- > 1 file changed, 23 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 815b054bb167..0d410652e194 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -2086,6 +2086,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, > (conn_state->hdcp_content_type != hdcp->content_type && > conn_state->content_protection != > DRM_MODE_CONTENT_PROTECTION_UNDESIRED); > + bool desired_and_not_enabled = false; > > /* > * During the HDCP encryption session if Type change is requested, > @@ -2108,8 +2109,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, > } > > if (conn_state->content_protection == > - DRM_MODE_CONTENT_PROTECTION_DESIRED || > - content_protection_type_changed) > + DRM_MODE_CONTENT_PROTECTION_DESIRED) { > + mutex_lock(&hdcp->mutex); > + /* Avoid enabling hdcp, if it already ENABLED */ > + desired_and_not_enabled = > + hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; > + mutex_unlock(&hdcp->mutex); > + } > + > + if (desired_and_not_enabled || content_protection_type_changed) > intel_hdcp_enable(connector, > crtc_state->cpu_transcoder, > (u8)conn_state->hdcp_content_type); > @@ -2158,6 +2166,19 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, > return; > } > > + crtc_state = drm_atomic_get_new_crtc_state(new_state->state, > + new_state->crtc); > + /* > + * Fix the HDCP uapi content protection state in case of modeset. > + * FIXME: As per HDCP content protection property uapi doc, an uevent() > + * need to be sent if there is transition from ENABLED->DESIRED. > + */ > + if (drm_atomic_crtc_needs_modeset(crtc_state) && > + (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && > + new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) > + new_state->content_protection = > + DRM_MODE_CONTENT_PROTECTION_DESIRED; > + > /* > * Nothing to do if the state didn't change, or HDCP was activated since > * the last commit. And also no change in hdcp content type. > @@ -2170,8 +2191,6 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, > return; > } > > - crtc_state = drm_atomic_get_new_crtc_state(new_state->state, > - new_state->crtc); > crtc_state->mode_changed = true; > } -- Jani Nikula, Intel Open Source Graphics Center From patchwork at emeril.freedesktop.org Tue Jun 30 10:46:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 10:46:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5B1/2=5D_drm/i915/tgl+=3A_Fix_TBT_DPL?= =?utf-8?q?L_fractional_divider_for_38=2E4MHz_ref_clock?= In-Reply-To: <20200629185848.20550-1-imre.deak@intel.com> References: <20200629185848.20550-1-imre.deak@intel.com> Message-ID: <159351399772.22701.3444573552724823694@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock URL : https://patchwork.freedesktop.org/series/78909/ State : warning == Summary == $ dim checkpatch origin/drm-tip ebc7448f0db7 drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock -:33: CHECK:CAMELCASE: Avoid CamelCase: <tgl_tbt_pll_38_4MHz_values> #33: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2940: +static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = { total: 0 errors, 0 warnings, 1 checks, 27 lines checked 06139c9eefa6 drm/i915/icl+: Simplify combo/TBT PLL calculation call-chain From chris at chris-wilson.co.uk Tue Jun 30 11:14:21 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 12:14:21 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gem: Delay attach mmu-notifier until we acquire the pinned userptr Message-ID: <20200630111421.12301-1-chris@chris-wilson.co.uk> On the fast path, we first try to pin the user pages and then attach the mmu-notifier. On the slow path, we did it the opposite way around, carrying the mmu-notifier over from the tail of the fast path. However, if we are mapping a fresh batch of user pages, we will always hit a pmd split operation (to replace the zero pages with real pages), triggering a invalidate-range callback for this userptr, and so we have to cancel the work [after completing the pinning] and cause the caller to retry (an extra EAGAIN return from an ioctl for some paths). If we follow the fast path and attach the callback after completion, we only see the invalidate-range for revocations of our pages. The risk (the same as for the fast path) is that if the mmu-notifier should have been run during the page lookup, we will have missed it and the pages will be mixed. One might conclude that the fast path is wrong, and we should always attach the mmu-notifier first and bear the cost of redundant repetition. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index e946032b13e4..c74c357cd180 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -479,6 +479,7 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) pinned += ret; } + __i915_gem_userptr_set_active(obj, true); if (locked) mmap_read_unlock(mm); mmput(mm); @@ -559,7 +560,6 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) struct mm_struct *mm = obj->userptr.mm->mm; struct page **pvec; struct sg_table *pages; - bool active; int pinned; unsigned int gup_flags = 0; @@ -614,19 +614,16 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) } } - active = false; if (pinned < 0) { pages = ERR_PTR(pinned); pinned = 0; } else if (pinned < num_pages) { pages = __i915_gem_userptr_get_pages_schedule(obj); - active = pages == ERR_PTR(-EAGAIN); } else { pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages); - active = !IS_ERR(pages); + if (!IS_ERR(pages)) + __i915_gem_userptr_set_active(obj, true); } - if (active) - __i915_gem_userptr_set_active(obj, true); if (IS_ERR(pages)) unpin_user_pages(pvec, pinned); -- 2.20.1 From stanislav.lisovskiy at intel.com Tue Jun 30 11:26:09 2020 From: stanislav.lisovskiy at intel.com (Stanislav Lisovskiy) Date: Tue, 30 Jun 2020 14:26:09 +0300 Subject: [Intel-gfx] [PATCH v1] drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K Message-ID: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> We still need "Bump up CDCLK" workaround otherwise getting underruns - however currently it blocks 8K as CDCLK = Pixel rate, in 8K case would require CDCLK to be around 1 Ghz which is not possible. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 45f7f33d1144..01a5bc6b08c4 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2080,9 +2080,21 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * Explicitly stating here that this seems to be currently * rather a Hack, than final solution. */ - if (IS_TIGERLAKE(dev_priv)) + if (IS_TIGERLAKE(dev_priv)) { min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + /* + * Clamp to max_cdclk_freq in order not to break an 8K, + * but still leave W/A at place. + */ + min_cdclk = min(min_cdclk, (int)dev_priv->max_cdclk_freq); + + /* + * max_cdclk_freq check obviously not needed - just return. + */ + return min_cdclk; + } + if (min_cdclk > dev_priv->max_cdclk_freq) { drm_dbg_kms(&dev_priv->drm, "required cdclk (%d kHz) exceeds max (%d kHz)\n", -- 2.24.1.485.gad05a3d8e5 From jani.nikula at linux.intel.com Tue Jun 30 11:28:47 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 14:28:47 +0300 Subject: [Intel-gfx] [PATCH] drm/i915/display: fix missing null check on allocated dsb object In-Reply-To: <45e8594c-14e5-ba67-9708-1b72fa2c51d3@canonical.com> References: <20200616114221.73971-1-colin.king@canonical.com> <20200616115459.GN4151@kadam> <45e8594c-14e5-ba67-9708-1b72fa2c51d3@canonical.com> Message-ID: <877dvon66o.fsf@intel.com> On Tue, 16 Jun 2020, Colin Ian King <colin.king at canonical.com> wrote: > On 16/06/2020 12:54, Dan Carpenter wrote: >> On Tue, Jun 16, 2020 at 12:42:21PM +0100, Colin King wrote: >>> From: Colin Ian King <colin.king at canonical.com> >>> >>> Currently there is no null check for a failed memory allocation >>> on the dsb object and without this a null pointer dereference >>> error can occur. Fix this by adding a null check. >>> >>> Note: added a drm_err message in keeping with the error message style >>> in the function. >> >> Don't give in to peer pressure! That's like being a lemming when Disney >> film makers come to push you off the cliff to create the 1958 nature >> film "White Wilderness". > > :-) Pushed, thanks for the patch and smile. BR, Jani. > >> >> regards, >> dan carpenter >> > -- Jani Nikula, Intel Open Source Graphics Center From chris at chris-wilson.co.uk Tue Jun 30 11:28:54 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 12:28:54 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gem: Always do pin_user_pages under the mmu-notifier Message-ID: <20200630112854.30361-1-chris@chris-wilson.co.uk> If the user replaces their vma as we are looking up their pages in the pin_user_pages fast path, we miss the revocation as the mmu-notifier is not yet installed. We end up with a bunch of stale pages mixed in with the fresh. However, the slow path is always run in the worker after first attaching to the notifier, and so will not miss a revocation as the pages are being looked up. Since this is safer, despite it hitting range-invalidate caused by the pin_user_pages themselves, always take the slow path. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 114 ++++---------------- 1 file changed, 21 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index e946032b13e4..9d4e69825987 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -512,58 +512,13 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) kfree(work); } -static struct sg_table * -__i915_gem_userptr_get_pages_schedule(struct drm_i915_gem_object *obj) -{ - struct get_pages_work *work; - - /* Spawn a worker so that we can acquire the - * user pages without holding our mutex. Access - * to the user pages requires mmap_lock, and we have - * a strict lock ordering of mmap_lock, struct_mutex - - * we already hold struct_mutex here and so cannot - * call gup without encountering a lock inversion. - * - * Userspace will keep on repeating the operation - * (thanks to EAGAIN) until either we hit the fast - * path or the worker completes. If the worker is - * cancelled or superseded, the task is still run - * but the results ignored. (This leads to - * complications that we may have a stray object - * refcount that we need to be wary of when - * checking for existing objects during creation.) - * If the worker encounters an error, it reports - * that error back to this function through - * obj->userptr.work = ERR_PTR. - */ - work = kmalloc(sizeof(*work), GFP_KERNEL); - if (work == NULL) - return ERR_PTR(-ENOMEM); - - obj->userptr.work = &work->work; - - work->obj = i915_gem_object_get(obj); - - work->task = current; - get_task_struct(work->task); - - INIT_WORK(&work->work, __i915_gem_userptr_get_pages_worker); - queue_work(to_i915(obj->base.dev)->mm.userptr_wq, &work->work); - - return ERR_PTR(-EAGAIN); -} - static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) { - const unsigned long num_pages = obj->base.size >> PAGE_SHIFT; - struct mm_struct *mm = obj->userptr.mm->mm; - struct page **pvec; - struct sg_table *pages; - bool active; - int pinned; - unsigned int gup_flags = 0; + struct get_pages_work *work; + struct work_struct *prev; - /* If userspace should engineer that these pages are replaced in + /* + * If userspace should engineer that these pages are replaced in * the vma between us binding this page into the GTT and completion * of rendering... Their loss. If they change the mapping of their * pages they need to create a new bo to point to the new vma. @@ -580,59 +535,32 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) * egregious cases from causing harm. */ - if (obj->userptr.work) { + prev = READ_ONCE(obj->userptr.work); + if (prev) { /* active flag should still be held for the pending work */ - if (IS_ERR(obj->userptr.work)) - return PTR_ERR(obj->userptr.work); + if (IS_ERR(prev)) + return PTR_ERR(prev); else return -EAGAIN; } - pvec = NULL; - pinned = 0; + work = kmalloc(sizeof(*work), GFP_KERNEL); + if (work == NULL) + return -ENOMEM; - if (mm == current->mm) { - pvec = kvmalloc_array(num_pages, sizeof(struct page *), - GFP_KERNEL | - __GFP_NORETRY | - __GFP_NOWARN); - /* - * Using __get_user_pages_fast() with a read-only - * access is questionable. A read-only page may be - * COW-broken, and then this might end up giving - * the wrong side of the COW.. - * - * We may or may not care. - */ - if (pvec) { - /* defer to worker if malloc fails */ - if (!i915_gem_object_is_readonly(obj)) - gup_flags |= FOLL_WRITE; - pinned = pin_user_pages_fast_only(obj->userptr.ptr, - num_pages, gup_flags, - pvec); - } - } + /* Attach our mmu-notifier first to catch revocations as we work */ + __i915_gem_userptr_set_active(obj, true); - active = false; - if (pinned < 0) { - pages = ERR_PTR(pinned); - pinned = 0; - } else if (pinned < num_pages) { - pages = __i915_gem_userptr_get_pages_schedule(obj); - active = pages == ERR_PTR(-EAGAIN); - } else { - pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages); - active = !IS_ERR(pages); - } - if (active) - __i915_gem_userptr_set_active(obj, true); + obj->userptr.work = &work->work; + work->obj = i915_gem_object_get(obj); - if (IS_ERR(pages)) - unpin_user_pages(pvec, pinned); - kvfree(pvec); + work->task = current; + get_task_struct(work->task); - return PTR_ERR_OR_ZERO(pages); + INIT_WORK(&work->work, __i915_gem_userptr_get_pages_worker); + queue_work(to_i915(obj->base.dev)->mm.userptr_wq, &work->work); + + return 0; } static void -- 2.20.1 From chris at chris-wilson.co.uk Tue Jun 30 11:32:26 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 12:32:26 +0100 Subject: [Intel-gfx] [PATCH] drm/i915/gem: Always do pin_user_pages under the mmu-notifier In-Reply-To: <20200630112854.30361-1-chris@chris-wilson.co.uk> References: <20200630112854.30361-1-chris@chris-wilson.co.uk> Message-ID: <20200630113226.30531-1-chris@chris-wilson.co.uk> If the user replaces their vma as we are looking up their pages in the pin_user_pages fast path, we miss the revocation as the mmu-notifier is not yet installed. We end up with a bunch of stale pages mixed in with the fresh. However, the slow path is always run in the worker after first attaching to the notifier, and so will not miss a revocation as the pages are being looked up. Since this is safer, despite it hitting range-invalidate caused by the pin_user_pages themselves, always take the slow path. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> --- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 114 ++++---------------- 1 file changed, 21 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c index e946032b13e4..fbc6f3dc9461 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c @@ -512,58 +512,13 @@ __i915_gem_userptr_get_pages_worker(struct work_struct *_work) kfree(work); } -static struct sg_table * -__i915_gem_userptr_get_pages_schedule(struct drm_i915_gem_object *obj) -{ - struct get_pages_work *work; - - /* Spawn a worker so that we can acquire the - * user pages without holding our mutex. Access - * to the user pages requires mmap_lock, and we have - * a strict lock ordering of mmap_lock, struct_mutex - - * we already hold struct_mutex here and so cannot - * call gup without encountering a lock inversion. - * - * Userspace will keep on repeating the operation - * (thanks to EAGAIN) until either we hit the fast - * path or the worker completes. If the worker is - * cancelled or superseded, the task is still run - * but the results ignored. (This leads to - * complications that we may have a stray object - * refcount that we need to be wary of when - * checking for existing objects during creation.) - * If the worker encounters an error, it reports - * that error back to this function through - * obj->userptr.work = ERR_PTR. - */ - work = kmalloc(sizeof(*work), GFP_KERNEL); - if (work == NULL) - return ERR_PTR(-ENOMEM); - - obj->userptr.work = &work->work; - - work->obj = i915_gem_object_get(obj); - - work->task = current; - get_task_struct(work->task); - - INIT_WORK(&work->work, __i915_gem_userptr_get_pages_worker); - queue_work(to_i915(obj->base.dev)->mm.userptr_wq, &work->work); - - return ERR_PTR(-EAGAIN); -} - static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) { - const unsigned long num_pages = obj->base.size >> PAGE_SHIFT; - struct mm_struct *mm = obj->userptr.mm->mm; - struct page **pvec; - struct sg_table *pages; - bool active; - int pinned; - unsigned int gup_flags = 0; + struct get_pages_work *work; + struct work_struct *prev; - /* If userspace should engineer that these pages are replaced in + /* + * If userspace should engineer that these pages are replaced in * the vma between us binding this page into the GTT and completion * of rendering... Their loss. If they change the mapping of their * pages they need to create a new bo to point to the new vma. @@ -580,59 +535,32 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) * egregious cases from causing harm. */ - if (obj->userptr.work) { + prev = READ_ONCE(obj->userptr.work); + if (prev) { /* active flag should still be held for the pending work */ - if (IS_ERR(obj->userptr.work)) - return PTR_ERR(obj->userptr.work); + if (IS_ERR(prev)) + return PTR_ERR(prev); else return -EAGAIN; } - pvec = NULL; - pinned = 0; + work = kmalloc(sizeof(*work), GFP_KERNEL); + if (work == NULL) + return -ENOMEM; - if (mm == current->mm) { - pvec = kvmalloc_array(num_pages, sizeof(struct page *), - GFP_KERNEL | - __GFP_NORETRY | - __GFP_NOWARN); - /* - * Using __get_user_pages_fast() with a read-only - * access is questionable. A read-only page may be - * COW-broken, and then this might end up giving - * the wrong side of the COW.. - * - * We may or may not care. - */ - if (pvec) { - /* defer to worker if malloc fails */ - if (!i915_gem_object_is_readonly(obj)) - gup_flags |= FOLL_WRITE; - pinned = pin_user_pages_fast_only(obj->userptr.ptr, - num_pages, gup_flags, - pvec); - } - } + /* Attach our mmu-notifier first to catch revocations as we work */ + __i915_gem_userptr_set_active(obj, true); - active = false; - if (pinned < 0) { - pages = ERR_PTR(pinned); - pinned = 0; - } else if (pinned < num_pages) { - pages = __i915_gem_userptr_get_pages_schedule(obj); - active = pages == ERR_PTR(-EAGAIN); - } else { - pages = __i915_gem_userptr_alloc_pages(obj, pvec, num_pages); - active = !IS_ERR(pages); - } - if (active) - __i915_gem_userptr_set_active(obj, true); + obj->userptr.work = &work->work; + work->obj = i915_gem_object_get(obj); - if (IS_ERR(pages)) - unpin_user_pages(pvec, pinned); - kvfree(pvec); + work->task = current; + get_task_struct(work->task); + + INIT_WORK(&work->work, __i915_gem_userptr_get_pages_worker); + queue_work(to_i915(obj->base.dev)->mm.userptr_wq, &work->work); - return PTR_ERR_OR_ZERO(pages); + return -EAGAIN; } static void -- 2.20.1 From maarten.lankhorst at linux.intel.com Tue Jun 30 11:52:34 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 30 Jun 2020 13:52:34 +0200 Subject: [Intel-gfx] [PATCH 07/26] Revert "drm/i915/gem: Split eb_vma into its own allocation" In-Reply-To: <dacbaf04-a149-38e2-5c07-3d3e10589bd3@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-7-maarten.lankhorst@linux.intel.com> <dacbaf04-a149-38e2-5c07-3d3e10589bd3@linux.intel.com> Message-ID: <c9123589-f0ce-0925-5ce0-d5e2277f1ca5@linux.intel.com> Op 29-06-2020 om 17:08 schreef Tvrtko Ursulin: > > On 23/06/2020 15:28, Maarten Lankhorst wrote: >> This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974. >> This conflicts with the ww mutex handling, which needs to drop >> the references after gpu submission anyway, because otherwise we >> may risk unlocking a BO after first freeing it. > > What is the problem here? eb_vma_array_put in eb_move_to_gpu? If so, could you just move this put to later in the sequence? I am simply thinking how to avoid controversial reverts. Because on the other hand I did not figure out what 0f1dd02295f35dcdcbaafcbcbbec0753884ab974 fixed in a few minutes I spent staring at the patch. We need to unlock before we unref to prevent a use-after-free in unlock, so freeing and releasing in eb_move_to_gpu() is too early. This means we only end up with 1 path for unlock, so it's fine to revert. From maarten.lankhorst at linux.intel.com Tue Jun 30 11:56:39 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 30 Jun 2020 13:56:39 +0200 Subject: [Intel-gfx] [PATCH 08/26] drm/i915/gem: Make eb_add_lut interruptible wait on object lock. In-Reply-To: <48435be5-d827-d785-9395-0d69a2b061a5@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-8-maarten.lankhorst@linux.intel.com> <48435be5-d827-d785-9395-0d69a2b061a5@linux.intel.com> Message-ID: <4d8e453a-e524-860f-594e-b59bf871d3fc@linux.intel.com> Op 29-06-2020 om 17:14 schreef Tvrtko Ursulin: > > On 23/06/2020 15:28, Maarten Lankhorst wrote: >> The lock here should be interruptible, so we can backoff if needed. > > I spied Chris posting "drm/i915/gem: Move obj->lut_list under its own lock" so maybe have a look at that. > > My question here is.. > >> >> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> >> --- >> ? drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++++++- >> ? 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> index 2636a130fb57..aa441af81431 100644 >> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >> @@ -774,7 +774,12 @@ static int __eb_add_lut(struct i915_execbuffer *eb, >> ????????? if (err == 0) { /* And nor has this handle */ >> ????????????? struct drm_i915_gem_object *obj = vma->obj; >> ? -??????????? i915_gem_object_lock(obj, NULL); >> +??????????? err = i915_gem_object_lock_interruptible(obj, NULL); > > .. does this lock-unlock survive to the end of your series or gets completely subsumed by the ctx locking? > > Regards, > > Tvrtko > Yeah it survives, it's too early to use ww waiting. Separate lut lock is fine as well as re-using ww is a bit overkill. >> +??????????? if (err) { >> +??????????????? radix_tree_delete(&ctx->handles_vma, handle); >> +??????????????? goto unlock; >> +??????????? } >> + >> ????????????? if (idr_find(&eb->file->object_idr, handle) == obj) { >> ????????????????? list_add(&lut->obj_link, &obj->lut_list); >> ????????????? } else { >> @@ -783,6 +788,7 @@ static int __eb_add_lut(struct i915_execbuffer *eb, >> ????????????? } >> ????????????? i915_gem_object_unlock(obj); >> ????????? } >> +unlock: >> ????????? mutex_unlock(&ctx->mutex); >> ????? } >> ????? if (unlikely(err)) >> From tvrtko.ursulin at linux.intel.com Tue Jun 30 12:31:46 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Tue, 30 Jun 2020 13:31:46 +0100 Subject: [Intel-gfx] [PATCH 07/26] Revert "drm/i915/gem: Split eb_vma into its own allocation" In-Reply-To: <c9123589-f0ce-0925-5ce0-d5e2277f1ca5@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-7-maarten.lankhorst@linux.intel.com> <dacbaf04-a149-38e2-5c07-3d3e10589bd3@linux.intel.com> <c9123589-f0ce-0925-5ce0-d5e2277f1ca5@linux.intel.com> Message-ID: <179cf932-2f5f-419e-10d3-dc6ce0934963@linux.intel.com> On 30/06/2020 12:52, Maarten Lankhorst wrote: > Op 29-06-2020 om 17:08 schreef Tvrtko Ursulin: >> >> On 23/06/2020 15:28, Maarten Lankhorst wrote: >>> This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974. >>> This conflicts with the ww mutex handling, which needs to drop >>> the references after gpu submission anyway, because otherwise we >>> may risk unlocking a BO after first freeing it. >> >> What is the problem here? eb_vma_array_put in eb_move_to_gpu? If so, could you just move this put to later in the sequence? I am simply thinking how to avoid controversial reverts. Because on the other hand I did not figure out what 0f1dd02295f35dcdcbaafcbcbbec0753884ab974 fixed in a few minutes I spent staring at the patch. > > > We need to unlock before we unref to prevent a use-after-free in unlock, so freeing and releasing in eb_move_to_gpu() is too early. This means we only end up with 1 path for unlock, so it's fine to revert. You are saying the reason 0f1dd02295f35dcdcbaafcbcbbec0753884ab974 was added for will not be there after your changes? Regards, Tvrtko From patchwork at emeril.freedesktop.org Tue Jun 30 12:46:16 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 12:46:16 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/ehl=3A_Add_new_PCI_ids?= In-Reply-To: <20200629200609.91058-1-jose.souza@intel.com> References: <20200629200609.91058-1-jose.souza@intel.com> Message-ID: <159352117685.22704.5147323031280329676@emeril.freedesktop.org> == Series Details == Series: drm/i915/ehl: Add new PCI ids URL : https://patchwork.freedesktop.org/series/78910/ State : success == Summary == CI Bug Log - changes from CI_DRM_8677 -> Patchwork_18038 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/index.html Known issues ------------ Here are the changes found in Patchwork_18038 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-byt-j1900/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-byt-j1900/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-byt-n2820: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-byt-n2820/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-byt-n2820/igt at i915_module_load@reload.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-icl-u2/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - fi-bsw-kefka: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-bsw-kefka/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html #### Possible fixes #### * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +5 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (43 -> 37) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8677 -> Patchwork_18038 CI-20190529: 20190529 CI_DRM_8677: 47bc281ce35e7872ee04238b2f5e81aeeeb2337b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18038: 8df9867d9a35c7d544a36e580c070bb46cf86479 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8df9867d9a35 drm/i915/ehl: Add new PCI ids == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/index.html From patchwork at emeril.freedesktop.org Tue Jun 30 12:50:44 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 12:50:44 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/display=3A_Implement_new_combo_phy_initialization_?= =?utf-8?q?step_=28rev3=29?= In-Reply-To: <20200625195252.39312-1-jose.souza@intel.com> References: <20200625195252.39312-1-jose.souza@intel.com> Message-ID: <159352144462.22703.7449095768194288797@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Implement new combo phy initialization step (rev3) URL : https://patchwork.freedesktop.org/series/78796/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4d7881077c25 drm/i915/display: Implement new combo phy initialization step -:89: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #89: FILE: drivers/gpu/drm/i915/i915_reg.h:2082: +#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) total: 0 errors, 1 warnings, 0 checks, 58 lines checked From patchwork at emeril.freedesktop.org Tue Jun 30 12:59:06 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 12:59:06 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl+=3A_Fix_TBT_DPLL_fract?= =?utf-8?q?ional_divider_for_38=2E4MHz_ref_clock?= In-Reply-To: <20200629185848.20550-1-imre.deak@intel.com> References: <20200629185848.20550-1-imre.deak@intel.com> Message-ID: <159352194676.22701.3262547131159853886@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock URL : https://patchwork.freedesktop.org/series/78909/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8676_full -> Patchwork_18037_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18037_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18037_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18037_full: ### IGT changes ### #### Possible regressions #### * igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1: - shard-hsw: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html * igt at kms_vblank@pipe-a-wait-forked: - shard-iclb: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_vblank@pipe-a-wait-forked.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at kms_vblank@pipe-a-wait-forked.html #### Warnings #### * igt at kms_atomic@plane-primary-overlay-mutable-zpos: - shard-iclb: [SKIP][5] ([i915#404]) -> [TIMEOUT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_atomic@plane-primary-overlay-mutable-zpos.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at kms_atomic@plane-primary-overlay-mutable-zpos.html Known issues ------------ Here are the changes found in Patchwork_18037_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_balancer@sliced: - shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#1958]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at gem_exec_balancer@sliced.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at gem_exec_balancer@sliced.html * igt at gem_mmap_gtt@ptrace: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#95]) +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gem_mmap_gtt@ptrace.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at gem_mmap_gtt@ptrace.html * igt at i915_selftest@mock at requests: - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#2110] / [i915#58] / [k.org#198133]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk7/igt at i915_selftest@mock at requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk3/igt at i915_selftest@mock at requests.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#93] / [i915#95]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_flip@basic-plain-flip at a-edp1: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +7 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at kms_flip@basic-plain-flip at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl9/igt at kms_flip@basic-plain-flip at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1: - shard-apl: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2: - shard-glk: [PASS][23] -> [FAIL][24] ([i915#79]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend at c-hdmi-a1: - shard-hsw: [PASS][27] -> [INCOMPLETE][28] ([i915#2055]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-hsw1/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-hsw8/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack: - shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][31] -> [FAIL][32] ([i915#1188]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][33] -> [DMESG-FAIL][34] ([fdo#108145] / [i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][35] -> [DMESG-FAIL][36] ([i915#95]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl6/igt at kms_prime@basic-crc at second-to-first.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl4/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_vblank@pipe-c-wait-idle: - shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at kms_vblank@pipe-c-wait-idle.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_vblank@pipe-c-wait-idle.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][41] -> [FAIL][42] ([i915#1820]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html * igt at prime_mmap_kms@buffer-sharing: - shard-tglb: [PASS][43] -> [DMESG-WARN][44] ([i915#402]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at prime_mmap_kms@buffer-sharing.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb2/igt at prime_mmap_kms@buffer-sharing.html #### Possible fixes #### * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-kbl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_exec_nop@basic-parallel: - shard-apl: [DMESG-WARN][47] ([i915#1635] / [i915#95]) -> [PASS][48] +22 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at gem_exec_nop@basic-parallel.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at gem_exec_nop@basic-parallel.html * igt at gem_mmap_gtt@cpuset-big-copy-odd: - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +10 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at gem_mmap_gtt@cpuset-big-copy-odd.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at gem_mmap_gtt@cpuset-big-copy-odd.html * igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc: - shard-iclb: [INCOMPLETE][51] -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb4/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb7/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html * igt at gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][53] ([i915#1436] / [i915#716]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gen9_exec_parse@allowed-all.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl1/igt at gen9_exec_parse@allowed-all.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][55] ([i915#1436] / [i915#716]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at gen9_exec_parse@allowed-single.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl5/igt at gen9_exec_parse@allowed-single.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][57] ([i915#402]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at i915_module_load@reload.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_atomic_interruptible@legacy-dpms: - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_atomic_interruptible@legacy-dpms.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_atomic_interruptible@legacy-dpms.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][61] ([i915#118] / [i915#95]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite: - shard-tglb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][65] ([fdo#108145] / [i915#1982]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +2 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][71] ([fdo#109642] / [fdo#111068]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr2_su@page_flip.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74] +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr@psr2_sprite_render.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr@psr2_sprite_render.html * igt at perf@polling-parameterized: - shard-iclb: [FAIL][75] ([i915#1542]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb1/igt at perf@polling-parameterized.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb3/igt at perf@polling-parameterized.html - shard-tglb: [FAIL][77] ([i915#1542]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb6/igt at perf@polling-parameterized.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb1/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][79] ([i915#588]) -> [SKIP][80] ([i915#658]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_color_chamelium@pipe-b-ctm-0-75: - shard-apl: [SKIP][81] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at kms_color_chamelium@pipe-b-ctm-0-75.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_color_chamelium@pipe-b-ctm-0-75.html * igt at kms_cursor_crc@pipe-d-cursor-512x512-random: - shard-apl: [SKIP][83] ([fdo#109271]) -> [SKIP][84] ([fdo#109271] / [i915#1635]) +5 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html * igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge: - shard-apl: [SKIP][85] ([fdo#109271] / [i915#1635]) -> [SKIP][86] ([fdo#109271]) +5 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html * igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1635] / [i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html * igt at runner@aborted: - shard-apl: ([FAIL][89], [FAIL][90], [FAIL][91]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#716]) -> [FAIL][92] ([i915#1635]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at runner@aborted.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at runner@aborted.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at runner@aborted.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8676 -> Patchwork_18037 CI-20190529: 20190529 CI_DRM_8676: 90573bcfde94b770410e07294c914b2c630d3999 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18037: 06139c9eefa6a6cebf31d6c8a560fe29aeee0a05 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/index.html From patchwork at emeril.freedesktop.org Tue Jun 30 13:11:57 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 13:11:57 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_Implement_new_combo_phy_initialization_step_?= =?utf-8?b?KHJldjMp?= In-Reply-To: <20200625195252.39312-1-jose.souza@intel.com> References: <20200625195252.39312-1-jose.souza@intel.com> Message-ID: <159352271772.22702.12545492147962095509@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Implement new combo phy initialization step (rev3) URL : https://patchwork.freedesktop.org/series/78796/ State : success == Summary == CI Bug Log - changes from CI_DRM_8677 -> Patchwork_18039 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/index.html Known issues ------------ Here are the changes found in Patchwork_18039 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (43 -> 37) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8677 -> Patchwork_18039 CI-20190529: 20190529 CI_DRM_8677: 47bc281ce35e7872ee04238b2f5e81aeeeb2337b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18039: 4d7881077c256917fd39d2633f0d66a4ec1b7077 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 4d7881077c25 drm/i915/display: Implement new combo phy initialization step == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/index.html From ramalingam.c at intel.com Tue Jun 30 13:30:47 2020 From: ramalingam.c at intel.com (Ramalingam C) Date: Tue, 30 Jun 2020 19:00:47 +0530 Subject: [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state In-Reply-To: <20200630082048.22308-1-anshuman.gupta@intel.com> References: <20200630082048.22308-1-anshuman.gupta@intel.com> Message-ID: <20200630133047.GD26598@intel.com> On 2020-06-30 at 13:50:48 +0530, Anshuman Gupta wrote: > Content Protection property should be updated as per the kernel > internal state. Let's say if Content protection is disabled > by userspace, CP property should be set to UNDESIRED so that > reauthentication will not happen until userspace request it again, > but when kernel disables the HDCP due to any DDI disabling sequences > like modeset/DPMS operation, kernel should set the property to > DESIRED, so that when opportunity arises, kernel will start the > HDCP authentication on its own. > > Somewhere in the line, state machine to set content protection to > DESIRED from kernel was broken and IGT coverage was missing for it. > This patch fixes it. > > v2: > - Fixing hdcp CP state in connector atomic check function > intel_hdcp_atomic_check(). [Maarten] > This will require to check hdcp->value in intel_hdcp_update_pipe() > in order to avoid enabling hdcp, if it was already enabled. > > v3: > - Rebased. > > Cc: Ramalingam C <ramalingam.c at intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > Reviewed-by: Uma Shankar <uma.shankar at intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com> > Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1 > Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2 > --- > drivers/gpu/drm/i915/display/intel_hdcp.c | 27 +++++++++++++++++++---- > 1 file changed, 23 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 815b054bb167..0d410652e194 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -2086,6 +2086,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, > (conn_state->hdcp_content_type != hdcp->content_type && > conn_state->content_protection != > DRM_MODE_CONTENT_PROTECTION_UNDESIRED); > + bool desired_and_not_enabled = false; > > /* > * During the HDCP encryption session if Type change is requested, > @@ -2108,8 +2109,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, > } > > if (conn_state->content_protection == > - DRM_MODE_CONTENT_PROTECTION_DESIRED || > - content_protection_type_changed) > + DRM_MODE_CONTENT_PROTECTION_DESIRED) { > + mutex_lock(&hdcp->mutex); > + /* Avoid enabling hdcp, if it already ENABLED */ > + desired_and_not_enabled = > + hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; It will be good to move before the hdcp->value modification as below, if (content_protection_type_changed) hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; But this will impact only when content_protection_type_changed is true. But when content_protection_type_changed is true we dont care the state of desired_and_not_enabled as we use them in logical OR. Either way. looks good to me. Reviewed-by: Ramalingam C <ramalingam.c at intel.com> > + mutex_unlock(&hdcp->mutex); > + } > + > + if (desired_and_not_enabled || content_protection_type_changed) > intel_hdcp_enable(connector, > crtc_state->cpu_transcoder, > (u8)conn_state->hdcp_content_type); > @@ -2158,6 +2166,19 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, > return; > } > > + crtc_state = drm_atomic_get_new_crtc_state(new_state->state, > + new_state->crtc); > + /* > + * Fix the HDCP uapi content protection state in case of modeset. > + * FIXME: As per HDCP content protection property uapi doc, an uevent() > + * need to be sent if there is transition from ENABLED->DESIRED. > + */ > + if (drm_atomic_crtc_needs_modeset(crtc_state) && Based on the IGT test result I infer needs_modeset status wont change from No->yes after this point. -ram > + (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && > + new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) > + new_state->content_protection = > + DRM_MODE_CONTENT_PROTECTION_DESIRED; > + > /* > * Nothing to do if the state didn't change, or HDCP was activated since > * the last commit. And also no change in hdcp content type. > @@ -2170,8 +2191,6 @@ void intel_hdcp_atomic_check(struct drm_connector *connector, > return; > } > > - crtc_state = drm_atomic_get_new_crtc_state(new_state->state, > - new_state->crtc); > crtc_state->mode_changed = true; > } > > -- > 2.26.2 > From imre.deak at intel.com Tue Jun 30 13:46:05 2020 From: imre.deak at intel.com (Imre Deak) Date: Tue, 30 Jun 2020 16:46:05 +0300 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl+=3A_Fix_TBT_DPLL_fract?= =?utf-8?q?ional_divider_for_38=2E4MHz_ref_clock?= In-Reply-To: <159352194676.22701.3262547131159853886@emeril.freedesktop.org> References: <20200629185848.20550-1-imre.deak@intel.com> <159352194676.22701.3262547131159853886@emeril.freedesktop.org> Message-ID: <20200630134605.GA2937@ideak-desk.fi.intel.com> Hi Lakshmi, On Tue, Jun 30, 2020 at 12:59:06PM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock > URL : https://patchwork.freedesktop.org/series/78909/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8676_full -> Patchwork_18037_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_18037_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_18037_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_18037_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1: > - shard-hsw: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html The platform is unrelated to the ICL+ only changes in the patchset. Suspend / resume hangs during the resume phase and I see a few power managmenet related pcode commands failing: <7>[ 269.795119] i915 0000:00:02.0: [drm:hsw_enable_pc8 [i915]] Enabling package C8+ <7>[ 269.795280] i915 0000:00:02.0: [drm:sandybridge_pcode_write_timeout [i915]] warning: pcode (write of 0x00000011 to mbox 11) mailbox access failed for hsw_write_dcomp [i915]: -6 <7>[ 269.915995] i915 0000:00:02.0: [drm:sandybridge_pcode_read [i915]] warning: pcode (read from mbox 5) mailbox access failed for intel_rc6_enable [i915]: -6 These errors may be related to the hang, I'd suggest tracking the s/r hang on HSW in a ticket for these errors. > > * igt at kms_vblank@pipe-a-wait-forked: > - shard-iclb: [PASS][3] -> [TIMEOUT][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_vblank@pipe-a-wait-forked.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at kms_vblank@pipe-a-wait-forked.html > > > #### Warnings #### > > * igt at kms_atomic@plane-primary-overlay-mutable-zpos: > - shard-iclb: [SKIP][5] ([i915#404]) -> [TIMEOUT][6] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_atomic@plane-primary-overlay-mutable-zpos.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at kms_atomic@plane-primary-overlay-mutable-zpos.html The above two timeouts are the same and actually happened already in gem_exec_balancer at sliced preceeding the above two tests. The https://gitlab.freedesktop.org/drm/intel/-/issues/1958 ticket is collecting similar timeouts. The pattern looks like: 6,58482,570332183,-;gem_exec_balanc D13040 1291 962 0x00000000 6,58483,570332186,-;Call Trace: 6,58484,570332189,-; __schedule+0x2f8/0x8d0 6,58485,570332194,-; schedule+0x37/0xe0 6,58486,570332229,-; intel_wakeref_wait_for_idle+0x7b/0xf0 [i915] 6,58487,570332233,-; ? wake_up_var+0x30/0x30 6,58488,570332257,-; i915_drop_caches_set+0x1c1/0x270 [i915] 6,58489,570332261,-; simple_attr_write+0xb0/0xd0 6,58490,570332266,-; full_proxy_write+0x51/0x80 6,58491,570332269,-; vfs_write+0xbc/0x1d0 6,58492,570332272,-; ksys_write+0xa2/0xe0 6,58493,570332275,-; do_syscall_64+0x56/0xe0 6,58494,570332277,-; entry_SYSCALL_64_after_hwframe+0x44/0xa9 as in https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8662/shard-tglb7/igt at gem_exec_balancer@sliced.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_18037_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_balancer@sliced: > - shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#1958]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at gem_exec_balancer@sliced.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at gem_exec_balancer@sliced.html > > * igt at gem_mmap_gtt@ptrace: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#95]) +15 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gem_mmap_gtt@ptrace.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at gem_mmap_gtt@ptrace.html > > * igt at i915_selftest@mock at requests: > - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#2110] / [i915#58] / [k.org#198133]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk7/igt at i915_selftest@mock at requests.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk3/igt at i915_selftest@mock at requests.html > > * igt at kms_big_fb@y-tiled-64bpp-rotate-180: > - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html > > * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: > - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#93] / [i915#95]) +2 similar issues > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html > > * igt at kms_flip@basic-plain-flip at a-edp1: > - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +7 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at kms_flip@basic-plain-flip at a-edp1.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl9/igt at kms_flip@basic-plain-flip at a-edp1.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1: > - shard-apl: [PASS][19] -> [FAIL][20] ([i915#79]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2: > - shard-glk: [PASS][23] -> [FAIL][24] ([i915#79]) > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html > > * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: > - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +5 similar issues > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * igt at kms_flip@flip-vs-suspend at c-hdmi-a1: > - shard-hsw: [PASS][27] -> [INCOMPLETE][28] ([i915#2055]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-hsw1/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-hsw8/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack: > - shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [PASS][31] -> [FAIL][32] ([i915#1188]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][33] -> [DMESG-FAIL][34] ([fdo#108145] / [i915#1982]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_prime@basic-crc at second-to-first: > - shard-kbl: [PASS][35] -> [DMESG-FAIL][36] ([i915#95]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl6/igt at kms_prime@basic-crc at second-to-first.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl4/igt at kms_prime@basic-crc at second-to-first.html > > * igt at kms_psr@psr2_cursor_mmap_cpu: > - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at kms_psr@psr2_cursor_mmap_cpu.html > > * igt at kms_vblank@pipe-c-wait-idle: > - shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at kms_vblank@pipe-c-wait-idle.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_vblank@pipe-c-wait-idle.html > > * igt at perf_pmu@semaphore-busy at rcs0: > - shard-kbl: [PASS][41] -> [FAIL][42] ([i915#1820]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html > > * igt at prime_mmap_kms@buffer-sharing: > - shard-tglb: [PASS][43] -> [DMESG-WARN][44] ([i915#402]) > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at prime_mmap_kms@buffer-sharing.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb2/igt at prime_mmap_kms@buffer-sharing.html > > > #### Possible fixes #### > > * igt at gem_ctx_isolation@preservation-s3 at vecs0: > - shard-kbl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > > * igt at gem_exec_nop@basic-parallel: > - shard-apl: [DMESG-WARN][47] ([i915#1635] / [i915#95]) -> [PASS][48] +22 similar issues > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at gem_exec_nop@basic-parallel.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at gem_exec_nop@basic-parallel.html > > * igt at gem_mmap_gtt@cpuset-big-copy-odd: > - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +10 similar issues > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > > * igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc: > - shard-iclb: [INCOMPLETE][51] -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb4/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb7/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html > > * igt at gen9_exec_parse@allowed-all: > - shard-apl: [DMESG-WARN][53] ([i915#1436] / [i915#716]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gen9_exec_parse@allowed-all.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl1/igt at gen9_exec_parse@allowed-all.html > > * igt at gen9_exec_parse@allowed-single: > - shard-skl: [DMESG-WARN][55] ([i915#1436] / [i915#716]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at gen9_exec_parse@allowed-single.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl5/igt at gen9_exec_parse@allowed-single.html > > * igt at i915_module_load@reload: > - shard-tglb: [DMESG-WARN][57] ([i915#402]) -> [PASS][58] +1 similar issue > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at i915_module_load@reload.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at i915_module_load@reload.html > > * igt at kms_atomic_interruptible@legacy-dpms: > - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] +1 similar issue > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_atomic_interruptible@legacy-dpms.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_atomic_interruptible@legacy-dpms.html > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - shard-glk: [DMESG-FAIL][61] ([i915#118] / [i915#95]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite: > - shard-tglb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +1 similar issue > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [DMESG-FAIL][65] ([fdo#108145] / [i915#1982]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68] +1 similar issue > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: > - shard-iclb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +2 similar issues > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html > > * igt at kms_psr2_su@page_flip: > - shard-iclb: [SKIP][71] ([fdo#109642] / [fdo#111068]) -> [PASS][72] > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr2_su@page_flip.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr2_su@page_flip.html > > * igt at kms_psr@psr2_sprite_render: > - shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74] +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr@psr2_sprite_render.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr@psr2_sprite_render.html > > * igt at perf@polling-parameterized: > - shard-iclb: [FAIL][75] ([i915#1542]) -> [PASS][76] > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb1/igt at perf@polling-parameterized.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb3/igt at perf@polling-parameterized.html > - shard-tglb: [FAIL][77] ([i915#1542]) -> [PASS][78] > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb6/igt at perf@polling-parameterized.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb1/igt at perf@polling-parameterized.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][79] ([i915#588]) -> [SKIP][80] ([i915#658]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at kms_color_chamelium@pipe-b-ctm-0-75: > - shard-apl: [SKIP][81] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +1 similar issue > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at kms_color_chamelium@pipe-b-ctm-0-75.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_color_chamelium@pipe-b-ctm-0-75.html > > * igt at kms_cursor_crc@pipe-d-cursor-512x512-random: > - shard-apl: [SKIP][83] ([fdo#109271]) -> [SKIP][84] ([fdo#109271] / [i915#1635]) +5 similar issues > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html > > * igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge: > - shard-apl: [SKIP][85] ([fdo#109271] / [i915#1635]) -> [SKIP][86] ([fdo#109271]) +5 similar issues > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: > - shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1635] / [i915#95]) > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html > > * igt at runner@aborted: > - shard-apl: ([FAIL][89], [FAIL][90], [FAIL][91]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#716]) -> [FAIL][92] ([i915#1635]) > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at runner@aborted.html > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at runner@aborted.html > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at runner@aborted.html > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at runner@aborted.html > > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 > [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8676 -> Patchwork_18037 > > CI-20190529: 20190529 > CI_DRM_8676: 90573bcfde94b770410e07294c914b2c630d3999 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18037: 06139c9eefa6a6cebf31d6c8a560fe29aeee0a05 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/index.html From jani.nikula at linux.intel.com Tue Jun 30 13:51:50 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 16:51:50 +0300 Subject: [Intel-gfx] [PATCH v3 00/15] acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API In-Reply-To: <20200620121758.14836-1-hdegoede@redhat.com> References: <20200620121758.14836-1-hdegoede@redhat.com> Message-ID: <874kqsmzk9.fsf@intel.com> On Sat, 20 Jun 2020, Hans de Goede <hdegoede at redhat.com> wrote: > Hi All, > > Here is v3 of my patch series converting the i915 driver's code for > controlling the panel's backlight with an external PWM controller to > use the atomic PWM API. See below for the changelog. > > Initially the plan was for this series to consist of 2 parts: > 1. convert the pwm-crc driver to support the atomic PWM API and > 2. convert the i915 driver's PWM code to use the atomic PWM API. > > But during testing I've found a number of bugs in the pwm-lpss and I > found that the acpi_lpss code needs some special handling because of > some ugliness found in most Cherry Trail DSDTs. > > So now this series has grown somewhat large and consists of 4 parts: > > 1. acpi_lpss fixes workarounds for Cherry Trail DSTD nastiness > 2. various fixes to the pwm-lpss driver > 3. convert the pwm-crc driver to support the atomic PWM API and > 4. convert the i915 driver's PWM code to use the atomic PWM API > > So we need to discuss how to merge this (once it passes review). > Although the inter-dependencies are only runtime I still think we should > make sure that 1-3 are in the drm-intel-next-queued (dinq) tree before > merging the i915 changes. Both to make sure that the intel-gfx CI system > does not become unhappy and for bisecting reasons. > > The involved acpi_lpss and pwm drivers do not see a whole lot of churn, so > it likely is the easiest to just merge everything through dinq. > > Rafael and Thierry, can I get your Acked-by for directly merging this into > dinq? > > This series has been tested (and re-tested after adding various bug-fixes) > extensively. It has been tested on the following devices: > > -Asus T100TA BYT + CRC-PMIC PWM > -Toshiba WT8-A BYT + CRC-PMIC PWM > -Thundersoft TS178 BYT + CRC-PMIC PWM, inverse PWM > -Asus T100HA CHT + CRC-PMIC PWM > -Terra Pad 1061 BYT + LPSS PWM > -Trekstor Twin 10.1 BYT + LPSS PWM > -Asus T101HA CHT + CRC-PMIC PWM > -GPD Pocket CHT + CRC-PMIC PWM For the drm/i915 patches 12-15, Acked-by: Jani Nikula <jani.nikula at intel.com> I eyeballed through them, and didn't spot anything obviously wrong, but at the same time didn't have the time to do an in-depth review. That said, I do have a lot of trust in you testing this with all the above devices. I think that's enough for merging. As for that matter, I'm fine with merging this via whichever tree you find best. Kind of stating the obvious, but please do ensure you have the proper acks in place for this. BR, Jani. > > Changelog: > > Changes in v2: > - Fix coverletter subject > - Drop accidentally included debugging patch > - "[PATCH v3 02/15] ACPI / LPSS: Save Cherry Trail PWM ctx registers only once ( > - Move #define LPSS_SAVE_CTX_ONCE define to group it with LPSS_SAVE_CTX > > Changes in v3: > - "[PATCH v3 04/15] pwm: lpss: Add range limit check for the base_unit register value" > - Use base_unit_range - 1 as maximum value for the clamp() > - "[PATCH v3 05/15] pwm: lpss: Use pwm_lpss_apply() when restoring state on resume" > - This replaces the "pwm: lpss: Set SW_UPDATE bit when enabling the PWM" > patch from previous versions of this patch-set, which really was a hack > working around the resume issue which this patch fixes properly. > - PATCH v3 6 - 11 pwm-crc changes: > - Various small changes resulting from the reviews by Andy and Uwe, > including some refactoring of the patches to reduce the amount of churn > in the patch-set > > Regards, > > Hans > -- Jani Nikula, Intel Open Source Graphics Center From maarten.lankhorst at linux.intel.com Tue Jun 30 14:07:04 2020 From: maarten.lankhorst at linux.intel.com (Maarten Lankhorst) Date: Tue, 30 Jun 2020 16:07:04 +0200 Subject: [Intel-gfx] [PATCH 07/26] Revert "drm/i915/gem: Split eb_vma into its own allocation" In-Reply-To: <179cf932-2f5f-419e-10d3-dc6ce0934963@linux.intel.com> References: <20200623142843.423594-1-maarten.lankhorst@linux.intel.com> <20200623142843.423594-7-maarten.lankhorst@linux.intel.com> <dacbaf04-a149-38e2-5c07-3d3e10589bd3@linux.intel.com> <c9123589-f0ce-0925-5ce0-d5e2277f1ca5@linux.intel.com> <179cf932-2f5f-419e-10d3-dc6ce0934963@linux.intel.com> Message-ID: <133c7c4e-f2ec-63a9-8688-14c94fa38e1f@linux.intel.com> Op 30-06-2020 om 14:31 schreef Tvrtko Ursulin: > > On 30/06/2020 12:52, Maarten Lankhorst wrote: >> Op 29-06-2020 om 17:08 schreef Tvrtko Ursulin: >>> >>> On 23/06/2020 15:28, Maarten Lankhorst wrote: >>>> This reverts commit 0f1dd02295f35dcdcbaafcbcbbec0753884ab974. >>>> This conflicts with the ww mutex handling, which needs to drop >>>> the references after gpu submission anyway, because otherwise we >>>> may risk unlocking a BO after first freeing it. >>> >>> What is the problem here? eb_vma_array_put in eb_move_to_gpu? If so, could you just move this put to later in the sequence? I am simply thinking how to avoid controversial reverts. Because on the other hand I did not figure out what 0f1dd02295f35dcdcbaafcbcbbec0753884ab974 fixed in a few minutes I spent staring at the patch. >> >> >> We need to unlock before we unref to prevent a use-after-free in unlock, so freeing and releasing in eb_move_to_gpu() is too early. This means we only end up with 1 path for unlock, so it's fine to revert. > > You are saying the reason 0f1dd02295f35dcdcbaafcbcbbec0753884ab974 was added for will not be there after your changes? > > Regards, > > Tvrtko Yes. :) From patchwork at emeril.freedesktop.org Tue Jun 30 14:12:52 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 14:12:52 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl=3A_Implement_WA_180114?= =?utf-8?q?64164?= In-Reply-To: <20200629212059.108460-1-jose.souza@intel.com> References: <20200629212059.108460-1-jose.souza@intel.com> Message-ID: <159352637213.22704.8836072838939583493@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/tgl: Implement WA 18011464164 URL : https://patchwork.freedesktop.org/series/78912/ State : success == Summary == CI Bug Log - changes from CI_DRM_8677 -> Patchwork_18040 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/index.html Known issues ------------ Here are the changes found in Patchwork_18040 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_cursor_legacy@basic-flip-after-cursor-atomic: - fi-icl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-after-cursor-atomic.html #### Possible fixes #### * igt at i915_module_load@reload: - fi-byt-j1900: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-byt-j1900/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/fi-byt-j1900/igt at i915_module_load@reload.html * igt at kms_cursor_legacy@basic-flip-before-cursor-legacy: - fi-icl-u2: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-legacy.html #### Warnings #### * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92]) -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html * igt at prime_vgem@basic-fence-flip: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][10] ([i915#62] / [i915#92]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/fi-kbl-x1275/igt at prime_vgem@basic-fence-flip.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (43 -> 37) ------------------------------ Additional (1): fi-tgl-u2 Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8677 -> Patchwork_18040 CI-20190529: 20190529 CI_DRM_8677: 47bc281ce35e7872ee04238b2f5e81aeeeb2337b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18040: 2eb704061edc4ae027f42cdc7a36f73cfec9d7ce @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2eb704061edc drm/i915/tgl: Implement WA 22010931296 98575b5b1bb3 drm/i915/tgl: Implement WA 18011464164 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/index.html From tvrtko.ursulin at linux.intel.com Tue Jun 30 14:16:48 2020 From: tvrtko.ursulin at linux.intel.com (Tvrtko Ursulin) Date: Tue, 30 Jun 2020 15:16:48 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Kill context before taking ctx->mutex In-Reply-To: <20200624110515.454665-1-maarten.lankhorst@linux.intel.com> References: <20200623142843.423594-26-maarten.lankhorst@linux.intel.com> <20200624110515.454665-1-maarten.lankhorst@linux.intel.com> Message-ID: <b32f5114-8268-c03c-967d-0348f3bdab4b@linux.intel.com> On 24/06/2020 12:05, Maarten Lankhorst wrote: > Killing context before taking ctx->mutex fixes a hang in > gem_ctx_persistence.close-replace-race, where lut_close > takes obj->resv.lock which is already held by execbuf, > causing a stalling indefinitely. If this is the consequence of inverting the locking order I think you need to move the fix earlier in the series, to precede the patch which creates the inversion. Otherwise AFAICT the re-order of kill_context vs lut_close seems fine. Regards, Tvrtko > [ 1904.342847] 2 locks held by gem_ctx_persist/11520: > [ 1904.342849] #0: ffff8882188e4968 (&ctx->mutex){+.+.}-{3:3}, at: context_close+0xe6/0x850 [i915] > [ 1904.342941] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: lut_close+0x2c2/0xba0 [i915] > [ 1904.343033] 3 locks held by gem_ctx_persist/11521: > [ 1904.343035] #0: ffffc900008ff938 (reservation_ww_class_acquire){+.+.}-{0:0}, at: i915_gem_do_execbuffer+0x103d/0x54c0 [i915] > [ 1904.343157] #1: ffff88821c58a5a8 (reservation_ww_class_mutex){+.+.}-{3:3}, at: eb_validate_vmas+0x602/0x2010 [i915] > [ 1904.343267] #2: ffff88820afd9200 (&vm->mutex/1){+.+.}-{3:3}, at: i915_vma_pin_ww+0x335/0x2300 [i915] > > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> > --- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 22 ++++++++++----------- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c > index a3519d5ee5a3..6d25c9c2be1a 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c > @@ -623,6 +623,17 @@ static void context_close(struct i915_gem_context *ctx) > i915_gem_context_set_closed(ctx); > mutex_unlock(&ctx->engines_mutex); > > + /* > + * If the user has disabled hangchecking, we can not be sure that > + * the batches will ever complete after the context is closed, > + * keeping the context and all resources pinned forever. So in this > + * case we opt to forcibly kill off all remaining requests on > + * context close. > + */ > + if (!i915_gem_context_is_persistent(ctx) || > + !ctx->i915->params.enable_hangcheck) > + kill_context(ctx); > + > mutex_lock(&ctx->mutex); > > set_closed_name(ctx); > @@ -642,17 +653,6 @@ static void context_close(struct i915_gem_context *ctx) > > mutex_unlock(&ctx->mutex); > > - /* > - * If the user has disabled hangchecking, we can not be sure that > - * the batches will ever complete after the context is closed, > - * keeping the context and all resources pinned forever. So in this > - * case we opt to forcibly kill off all remaining requests on > - * context close. > - */ > - if (!i915_gem_context_is_persistent(ctx) || > - !ctx->i915->params.enable_hangcheck) > - kill_context(ctx); > - > i915_gem_context_put(ctx); > } > > > base-commit: 64cab0b9f9bfeb14d3ec2452d76b56915cdeb09f > prerequisite-patch-id: e6315738715ac4ffccaeb4c4bf5a94651fb8da1d > prerequisite-patch-id: 7944bb01d1ec7530513eabddb9198275653cc451 > prerequisite-patch-id: 052eda3b40906f0fbc16b4cc33dbcdce35e05441 > prerequisite-patch-id: 35ff18a74e8bf9bfb0a517f69a98d0ec88bd3b51 > prerequisite-patch-id: 7a34e785e951b1d3f4c0e20430c8111a15ddbe92 > prerequisite-patch-id: 9b7faf3172e9f218a2589fcc96930af9ab05e70b > prerequisite-patch-id: 3ce7c5b4508018631673e62d8725f866988bd08d > prerequisite-patch-id: 5fd46caff26e53f9cb6df5f8490838b6ac15e015 > prerequisite-patch-id: 41782208b1bc32e448ce29313112030c74bd8421 > prerequisite-patch-id: b6c4d99cb554c0c2268cde5c43e878a48e005e45 > prerequisite-patch-id: 418fdb031a232bba4056171917ee42e997991902 > prerequisite-patch-id: ff5bf0dcdb9191761392b0707481aaf99396dbec > prerequisite-patch-id: c3dbcef2f1a68f88ae99acbd01ee56847fb3e2da > prerequisite-patch-id: 18c373676c9bbeb1c11fb2ba5bf4ad728cfea75d > prerequisite-patch-id: 5b9d8e4535096365d365fdd1ec00f844a4135208 > prerequisite-patch-id: 63bac64548acd514c4a0cb5acb896c8217fb8201 > prerequisite-patch-id: e93b855dd97b24799c59f059cc548f46807ab207 > prerequisite-patch-id: 3d7dc6ecbc2279fb48f0972a911fbffd8d899faa > prerequisite-patch-id: f1d9e0b7165f80efe984dd0231d1dbd2a9a79950 > prerequisite-patch-id: ed1a168ac98b81b8066f68a0738cfc44a79e8ef1 > prerequisite-patch-id: f813cb8d4c2fe2c1d94b66c3f3fbb787ac241628 > prerequisite-patch-id: 0f0f90eaa4a2e299adddfe1c7134af3810a8e9e2 > prerequisite-patch-id: cb7ffeccd6429fc79aebffb84f62af5e78252461 > prerequisite-patch-id: 78905449b46ad574757a7fb91f58847ea20e09cd > prerequisite-patch-id: 6d937a49f3c8cd380121f72610072aaaf8c274b1 > prerequisite-patch-id: 0c8d2dee1592395780258488be0350755e7ffd7d > From anshuman.gupta at intel.com Tue Jun 30 14:09:30 2020 From: anshuman.gupta at intel.com (Anshuman Gupta) Date: Tue, 30 Jun 2020 19:39:30 +0530 Subject: [Intel-gfx] [PATCH v7 15/17] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message In-Reply-To: <20200623155907.22961-16-sean@poorly.run> References: <20200623155907.22961-1-sean@poorly.run> <20200623155907.22961-16-sean@poorly.run> Message-ID: <20200630140929.GE15183@intel.com> On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote: Hi Sean, I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a. I have looked the entire series, i will take up this opportunity to review the series from HDCP over DP MST POV. I think theoretically this series should work or Gen12 as well, as DP MST streams are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction msg (generating Stream State Signature L?). I will test this on Gen12 H/W with DP MST support and will provide my inputs. Meanwhile while going through DP MST v1.2a specs(Page 262) came to know about a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h), Bit 2 : STREAM_STATUS_CHANGED. When this bit set to ?1? indicates the source must re-check the Stream Status with the QUERY_STREAM_ENCRYPTION_STATUS message. Currently i feel this irq support is missing, do we require to support above IRQ vector for DP MST stream encryption. Thanks, Anshuman Gupta. > From: Sean Paul <seanpaul at chromium.org> > > Used to query whether an MST stream is encrypted or not. > > Signed-off-by: Sean Paul <seanpaul at chromium.org> > > Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-sean at poorly.run #v4 > Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-sean at poorly.run #v5 > Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-sean at poorly.run #v6 > > Changes in v4: > -Added to the set > Changes in v5: > -None > Changes in v6: > -Use FIELD_PREP to generate request buffer bitfields (Lyude) > -Add mst selftest and dump/decode_sideband_req for QSES (Lyude) > Changes in v7: > -None > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++++++++++++++++ > .../drm/selftests/test-drm_dp_mst_helper.c | 17 +++ > include/drm/drm_dp_helper.h | 3 + > include/drm/drm_dp_mst_helper.h | 44 ++++++ > 4 files changed, 206 insertions(+) > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index b2f5a84b4cfb..fc68478eaeb4 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -20,11 +20,13 @@ > * OF THIS SOFTWARE. > */ > > +#include <linux/bitfield.h> > #include <linux/delay.h> > #include <linux/errno.h> > #include <linux/i2c.h> > #include <linux/init.h> > #include <linux/kernel.h> > +#include <linux/random.h> > #include <linux/sched.h> > #include <linux/seq_file.h> > #include <linux/iopoll.h> > @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, > memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes); > idx += req->u.i2c_write.num_bytes; > break; > + case DP_QUERY_STREAM_ENC_STATUS: { > + const struct drm_dp_query_stream_enc_status *msg; > + > + msg = &req->u.enc_status; > + buf[idx] = msg->stream_id; > + idx++; > + memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id)); > + idx += sizeof(msg->client_id); > + buf[idx] = 0; > + buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event); > + buf[idx] |= msg->valid_stream_event ? BIT(2) : 0; > + buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior); > + buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0; > + idx++; > + } > + break; > } > raw->cur_len = idx; > } > @@ -547,6 +565,20 @@ drm_dp_decode_sideband_req(const struct drm_dp_sideband_msg_tx *raw, > return -ENOMEM; > } > break; > + case DP_QUERY_STREAM_ENC_STATUS: > + req->u.enc_status.stream_id = buf[idx++]; > + for (i = 0; i < sizeof(req->u.enc_status.client_id); i++) > + req->u.enc_status.client_id[i] = buf[idx++]; > + > + req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0), > + buf[idx]); > + req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2), > + buf[idx]); > + req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3), > + buf[idx]); > + req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5), > + buf[idx]); > + break; > } > > return 0; > @@ -625,6 +657,16 @@ drm_dp_dump_sideband_msg_req_body(const struct drm_dp_sideband_msg_req_body *req > req->u.i2c_write.num_bytes, req->u.i2c_write.num_bytes, > req->u.i2c_write.bytes); > break; > + case DP_QUERY_STREAM_ENC_STATUS: > + P("stream_id=%u client_id=%*ph stream_event=%x " > + "valid_event=%d stream_behavior=%x valid_behavior=%d", > + req->u.enc_status.stream_id, > + (int)ARRAY_SIZE(req->u.enc_status.client_id), > + req->u.enc_status.client_id, req->u.enc_status.stream_event, > + req->u.enc_status.valid_stream_event, > + req->u.enc_status.stream_behavior, > + req->u.enc_status.valid_stream_behavior); > + break; > default: > P("???\n"); > break; > @@ -925,6 +967,34 @@ static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms > return true; > } > > +static bool > +drm_dp_sideband_parse_query_stream_enc_status( > + struct drm_dp_sideband_msg_rx *raw, > + struct drm_dp_sideband_msg_reply_body *repmsg) > +{ > + struct drm_dp_query_stream_enc_status_ack_reply *reply; > + > + reply = &repmsg->u.enc_status; > + > + reply->stream_id = raw->msg[3]; > + > + reply->reply_signed = raw->msg[2] & BIT(0); > + > + reply->hdcp_1x_device_present = raw->msg[2] & BIT(3); > + reply->hdcp_2x_device_present = raw->msg[2] & BIT(4); > + > + reply->query_capable_device_present = raw->msg[2] & BIT(5); > + reply->legacy_device_present = raw->msg[2] & BIT(6); > + reply->unauthorizable_device_present = raw->msg[2] & BIT(7); > + > + reply->auth_completed = !!(raw->msg[1] & BIT(3)); > + reply->encryption_enabled = !!(raw->msg[1] & BIT(4)); > + reply->repeater_present = !!(raw->msg[1] & BIT(5)); > + reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6; > + > + return true; > +} > + > static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, > struct drm_dp_sideband_msg_reply_body *msg) > { > @@ -959,6 +1029,8 @@ static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, > return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg); > case DP_CLEAR_PAYLOAD_ID_TABLE: > return true; /* since there's nothing to parse */ > + case DP_QUERY_STREAM_ENC_STATUS: > + return drm_dp_sideband_parse_query_stream_enc_status(raw, msg); > default: > DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type, > drm_dp_mst_req_type_str(msg->req_type)); > @@ -1109,6 +1181,25 @@ static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, > msg->path_msg = true; > } > > +static int > +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id, > + u8 *q_id) > +{ > + struct drm_dp_sideband_msg_req_body req; > + > + req.req_type = DP_QUERY_STREAM_ENC_STATUS; > + req.u.enc_status.stream_id = stream_id; > + memcpy(req.u.enc_status.client_id, q_id, > + sizeof(req.u.enc_status.client_id)); > + req.u.enc_status.stream_event = 0; > + req.u.enc_status.valid_stream_event = false; > + req.u.enc_status.stream_behavior = 0; > + req.u.enc_status.valid_stream_behavior = false; > + > + drm_dp_encode_sideband_req(&req, msg); > + return 0; > +} > + > static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr, > struct drm_dp_vcpi *vcpi) > { > @@ -3137,6 +3228,57 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, > } > EXPORT_SYMBOL(drm_dp_send_power_updown_phy); > > +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, > + struct drm_dp_mst_port *port, > + struct drm_dp_query_stream_enc_status_ack_reply *status) > +{ > + struct drm_dp_sideband_msg_tx *txmsg; > + u8 nonce[7]; > + int len, ret; > + > + txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); > + if (!txmsg) > + return -ENOMEM; > + > + port = drm_dp_mst_topology_get_port_validated(mgr, port); > + if (!port) { > + ret = -EINVAL; > + goto out_get_port; > + } > + > + get_random_bytes(nonce, sizeof(nonce)); > + > + /* > + * "Source device targets the QUERY_STREAM_ENCRYPTION_STATUS message > + * transaction at the MST Branch device directly connected to the > + * Source" > + */ > + txmsg->dst = mgr->mst_primary; > + > + len = build_query_stream_enc_status(txmsg, port->vcpi.vcpi, nonce); > + > + drm_dp_queue_down_tx(mgr, txmsg); > + > + ret = drm_dp_mst_wait_tx_reply(mgr->mst_primary, txmsg); > + if (ret < 0) { > + goto out; > + } else if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) { > + DRM_DEBUG_KMS("query encryption status nak received\n"); > + ret = -ENXIO; > + goto out; > + } > + > + ret = 0; > + memcpy(status, &txmsg->reply.u.enc_status, sizeof(*status)); > + > +out: > + drm_dp_mst_topology_put_port(port); > +out_get_port: > + kfree(txmsg); > + return ret; > +} > +EXPORT_SYMBOL(drm_dp_send_query_stream_enc_status); > + > static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr, > int id, > struct drm_dp_payload *payload) > diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c > index bd990d178765..1d696ec001cf 100644 > --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c > +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c > @@ -5,6 +5,8 @@ > > #define PREFIX_STR "[drm_dp_mst_helper]" > > +#include <linux/random.h> > + > #include <drm/drm_dp_mst_helper.h> > #include <drm/drm_print.h> > > @@ -237,6 +239,21 @@ int igt_dp_mst_sideband_msg_req_decode(void *unused) > in.u.i2c_write.bytes = data; > DO_TEST(); > > + in.req_type = DP_QUERY_STREAM_ENC_STATUS; > + in.u.enc_status.stream_id = 1; > + DO_TEST(); > + get_random_bytes(in.u.enc_status.client_id, > + sizeof(in.u.enc_status.client_id)); > + DO_TEST(); > + in.u.enc_status.stream_event = 3; > + DO_TEST(); > + in.u.enc_status.valid_stream_event = 0; > + DO_TEST(); > + in.u.enc_status.stream_behavior = 3; > + DO_TEST(); > + in.u.enc_status.valid_stream_behavior = 1; > + DO_TEST(); > + > #undef DO_TEST > return 0; > } > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e47dc22ebf50..e2d2df5e869e 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1108,6 +1108,9 @@ > #define DP_POWER_DOWN_PHY 0x25 > #define DP_SINK_EVENT_NOTIFY 0x30 > #define DP_QUERY_STREAM_ENC_STATUS 0x38 > +#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 > +#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 > +#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2 > > /* DP 1.2 MST sideband reply types */ > #define DP_SIDEBAND_REPLY_ACK 0x00 > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > index 8b9eb4db3381..371eef8798ad 100644 > --- a/include/drm/drm_dp_mst_helper.h > +++ b/include/drm/drm_dp_mst_helper.h > @@ -313,6 +313,34 @@ struct drm_dp_remote_i2c_write_ack_reply { > u8 port_number; > }; > > +struct drm_dp_query_stream_enc_status_ack_reply { > + /* Bit[23:16]- Stream Id */ > + u8 stream_id; > + > + /* Bit[15]- Signed */ > + bool reply_signed; > + > + /* Bit[10:8]- Stream Output Sink Type */ > + bool unauthorizable_device_present; > + bool legacy_device_present; > + bool query_capable_device_present; > + > + /* Bit[12:11]- Stream Output CP Type */ > + bool hdcp_1x_device_present; > + bool hdcp_2x_device_present; > + > + /* Bit[4]- Stream Authentication */ > + bool auth_completed; > + > + /* Bit[3]- Stream Encryption */ > + bool encryption_enabled; > + > + /* Bit[2]- Stream Repeater Function Present */ > + bool repeater_present; > + > + /* Bit[1:0]- Stream State */ > + u8 state; > +}; > > #define DRM_DP_MAX_SDP_STREAMS 16 > struct drm_dp_allocate_payload { > @@ -374,6 +402,15 @@ struct drm_dp_remote_i2c_write { > u8 *bytes; > }; > > +struct drm_dp_query_stream_enc_status { > + u8 stream_id; > + u8 client_id[7]; /* 56-bit nonce */ > + u8 stream_event; > + bool valid_stream_event; > + u8 stream_behavior; > + u8 valid_stream_behavior; > +}; > + > /* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ > struct drm_dp_port_number_req { > u8 port_number; > @@ -422,6 +459,8 @@ struct drm_dp_sideband_msg_req_body { > > struct drm_dp_remote_i2c_read i2c_read; > struct drm_dp_remote_i2c_write i2c_write; > + > + struct drm_dp_query_stream_enc_status enc_status; > } u; > }; > > @@ -444,6 +483,8 @@ struct drm_dp_sideband_msg_reply_body { > struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; > struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; > struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack; > + > + struct drm_dp_query_stream_enc_status_ack_reply enc_status; > } u; > }; > > @@ -808,6 +849,9 @@ drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, > struct drm_dp_mst_port *port); > int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, > struct drm_dp_mst_port *port, bool power_up); > +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, > + struct drm_dp_mst_port *port, > + struct drm_dp_query_stream_enc_status_ack_reply *status); > int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state); > > void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port); > -- > Sean Paul, Software Engineer, Google / Chromium OS > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Tue Jun 30 14:25:30 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 14:25:30 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl+=3A_Fix_TBT_DPLL_fract?= =?utf-8?q?ional_divider_for_38=2E4MHz_ref_clock?= In-Reply-To: <20200629185848.20550-1-imre.deak@intel.com> References: <20200629185848.20550-1-imre.deak@intel.com> Message-ID: <159352713080.22703.4576033759680340358@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock URL : https://patchwork.freedesktop.org/series/78909/ State : success == Summary == CI Bug Log - changes from CI_DRM_8676_full -> Patchwork_18037_full ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_18037_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18037_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18037_full: ### IGT changes ### #### Warnings #### * igt at kms_atomic@plane-primary-overlay-mutable-zpos: - shard-iclb: [SKIP][1] ([i915#404]) -> [TIMEOUT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_atomic@plane-primary-overlay-mutable-zpos.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at kms_atomic@plane-primary-overlay-mutable-zpos.html Known issues ------------ Here are the changes found in Patchwork_18037_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_balancer@sliced: - shard-iclb: [PASS][3] -> [TIMEOUT][4] ([i915#1958]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at gem_exec_balancer@sliced.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at gem_exec_balancer@sliced.html * igt at gem_mmap_gtt@ptrace: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / [i915#95]) +15 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gem_mmap_gtt@ptrace.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at gem_mmap_gtt@ptrace.html * igt at i915_selftest@mock at requests: - shard-glk: [PASS][7] -> [INCOMPLETE][8] ([i915#2110] / [i915#58] / [k.org#198133]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk7/igt at i915_selftest@mock at requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk3/igt at i915_selftest@mock at requests.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][9] -> [DMESG-FAIL][10] ([i915#118] / [i915#95]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_flip@basic-plain-flip at a-edp1: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at kms_flip@basic-plain-flip at a-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl9/igt at kms_flip@basic-plain-flip at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1: - shard-apl: [PASS][15] -> [FAIL][16] ([i915#79]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +5 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1: - shard-hsw: [PASS][23] -> [INCOMPLETE][24] ([i915#2055]) +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack: - shard-tglb: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][27] -> [FAIL][28] ([i915#1188]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][29] -> [DMESG-FAIL][30] ([fdo#108145] / [i915#1982]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][31] -> [DMESG-FAIL][32] ([i915#95]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl6/igt at kms_prime@basic-crc at second-to-first.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl4/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_vblank@pipe-a-wait-forked: - shard-iclb: [PASS][35] -> [TIMEOUT][36] ([i915#1936]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_vblank@pipe-a-wait-forked.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at kms_vblank@pipe-a-wait-forked.html * igt at kms_vblank@pipe-c-wait-idle: - shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at kms_vblank@pipe-c-wait-idle.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_vblank@pipe-c-wait-idle.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [PASS][39] -> [FAIL][40] ([i915#1820]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html * igt at prime_mmap_kms@buffer-sharing: - shard-tglb: [PASS][41] -> [DMESG-WARN][42] ([i915#402]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at prime_mmap_kms@buffer-sharing.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb2/igt at prime_mmap_kms@buffer-sharing.html #### Possible fixes #### * igt at gem_ctx_isolation@preservation-s3 at vecs0: - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +2 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html * igt at gem_exec_nop@basic-parallel: - shard-apl: [DMESG-WARN][45] ([i915#1635] / [i915#95]) -> [PASS][46] +22 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at gem_exec_nop@basic-parallel.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at gem_exec_nop@basic-parallel.html * igt at gem_mmap_gtt@cpuset-big-copy-odd: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +10 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at gem_mmap_gtt@cpuset-big-copy-odd.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at gem_mmap_gtt@cpuset-big-copy-odd.html * igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc: - shard-iclb: [INCOMPLETE][49] -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb4/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb7/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html * igt at gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][51] ([i915#1436] / [i915#716]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gen9_exec_parse@allowed-all.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl1/igt at gen9_exec_parse@allowed-all.html * igt at gen9_exec_parse@allowed-single: - shard-skl: [DMESG-WARN][53] ([i915#1436] / [i915#716]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at gen9_exec_parse@allowed-single.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl5/igt at gen9_exec_parse@allowed-single.html * igt at i915_module_load@reload: - shard-tglb: [DMESG-WARN][55] ([i915#402]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at i915_module_load@reload.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at i915_module_load@reload.html * igt at kms_atomic_interruptible@legacy-dpms: - shard-kbl: [DMESG-WARN][57] ([i915#93] / [i915#95]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_atomic_interruptible@legacy-dpms.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_atomic_interruptible@legacy-dpms.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][59] ([i915#118] / [i915#95]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite: - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][63] ([fdo#108145] / [i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] +2 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][69] ([fdo#109642] / [fdo#111068]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr2_su@page_flip.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_sprite_render: - shard-iclb: [SKIP][71] ([fdo#109441]) -> [PASS][72] +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr@psr2_sprite_render.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr@psr2_sprite_render.html * igt at perf@polling-parameterized: - shard-iclb: [FAIL][73] ([i915#1542]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb1/igt at perf@polling-parameterized.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb3/igt at perf@polling-parameterized.html - shard-tglb: [FAIL][75] ([i915#1542]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb6/igt at perf@polling-parameterized.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb1/igt at perf@polling-parameterized.html #### Warnings #### * igt at i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: [SKIP][77] ([i915#588]) -> [SKIP][78] ([i915#658]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html * igt at kms_color_chamelium@pipe-b-ctm-0-75: - shard-apl: [SKIP][79] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at kms_color_chamelium@pipe-b-ctm-0-75.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_color_chamelium@pipe-b-ctm-0-75.html * igt at kms_cursor_crc@pipe-d-cursor-512x512-random: - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +5 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html * igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge: - shard-apl: [SKIP][83] ([fdo#109271] / [i915#1635]) -> [SKIP][84] ([fdo#109271]) +5 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html * igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - shard-apl: [DMESG-FAIL][85] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) -> [DMESG-FAIL][86] ([fdo#108145] / [i915#1635] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html * igt at runner@aborted: - shard-apl: ([FAIL][87], [FAIL][88], [FAIL][89]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#716]) -> [FAIL][90] ([i915#1635]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at runner@aborted.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at runner@aborted.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at runner@aborted.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1936]: https://gitlab.freedesktop.org/drm/intel/issues/1936 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8676 -> Patchwork_18037 CI-20190529: 20190529 CI_DRM_8676: 90573bcfde94b770410e07294c914b2c630d3999 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18037: 06139c9eefa6a6cebf31d6c8a560fe29aeee0a05 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/index.html From ville.syrjala at linux.intel.com Tue Jun 30 14:28:12 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 30 Jun 2020 17:28:12 +0300 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tgl: Implement WA 18011464164 In-Reply-To: <20200629212059.108460-1-jose.souza@intel.com> References: <20200629212059.108460-1-jose.souza@intel.com> Message-ID: <20200630142812.GF6112@intel.com> On Mon, Jun 29, 2020 at 02:20:58PM -0700, Jos? Roberto de Souza wrote: > This fix some possible corruptions. > > BSpec: 52755 > BSpec: 52890 > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 284af0c6439c..797e036fa695 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4170,6 +4170,9 @@ enum { > #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) > #define CGPSF_CLKGATE_DIS (1 << 3) > > +#define SLICE_UNIT_LEVEL_CLOCK_GATING_CTL _MMIO(0x94D8) > +#define GS_UNIT_CLOCK_GATING_DIS REG_BIT(24) > + > /* > * Display engine regs > */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2a32d6230795..86408173c435 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7113,7 +7113,7 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) > I915_WRITE(POWERGATE_ENABLE, > I915_READ(POWERGATE_ENABLE) | vd_pg_enable); > > - /* Wa_1409825376:tgl (pre-prod)*/ > + /* Wa_1409825376:tgl (pre-prod) */ > if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)) > I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) | > TGL_VRH_GATING_DIS); > @@ -7121,6 +7121,12 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) > /* Wa_14011059788:tgl */ > intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN, > 0, DFR_DISABLE); > + > + /* Wa_18011464164:tgl */ > + if (IS_TGL_REVID(dev_priv, TGL_REVID_B0, TGL_REVID_B0)) > + intel_uncore_rmw(&dev_priv->uncore, > + SLICE_UNIT_LEVEL_CLOCK_GATING_CTL, 0, > + GS_UNIT_CLOCK_GATING_DIS); This looks like a gt w/a, so shouldn't be here preobably. We also have a very similarly named register already at 0x94d4, so the register name probably needs some work too. > } > > static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) > -- > 2.27.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From lakshminarayana.vudum at intel.com Tue Jun 30 14:31:32 2020 From: lakshminarayana.vudum at intel.com (Vudum, Lakshminarayana) Date: Tue, 30 Jun 2020 14:31:32 +0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl+=3A_Fix_TBT_DPLL_fract?= =?utf-8?q?ional_divider_for_38=2E4MHz_ref_clock?= In-Reply-To: <20200630134605.GA2937@ideak-desk.fi.intel.com> References: <20200629185848.20550-1-imre.deak@intel.com> <159352194676.22701.3262547131159853886@emeril.freedesktop.org> <20200630134605.GA2937@ideak-desk.fi.intel.com> Message-ID: <9d06c0528dc44f0b9f60ca1a2aac86f9@intel.com> Imre, I have re-reported. -----Original Message----- From: Imre Deak <imre.deak at intel.com> Sent: Tuesday, June 30, 2020 4:46 PM To: intel-gfx at lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum at intel.com> Subject: Re: ? Fi.CI.IGT: failure for series starting with [1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock Hi Lakshmi, On Tue, Jun 30, 2020 at 12:59:06PM +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [1/2] drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock > URL : https://patchwork.freedesktop.org/series/78909/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8676_full -> Patchwork_18037_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_18037_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_18037_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_18037_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1: > - shard-hsw: [PASS][1] -> [INCOMPLETE][2] > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-hsw2/igt at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-hsw2/ig > t at kms_flip@flip-vs-suspend-interruptible at b-hdmi-a1.html The platform is unrelated to the ICL+ only changes in the patchset. Suspend / resume hangs during the resume phase and I see a few power managmenet related pcode commands failing: <7>[ 269.795119] i915 0000:00:02.0: [drm:hsw_enable_pc8 [i915]] Enabling package C8+ <7>[ 269.795280] i915 0000:00:02.0: [drm:sandybridge_pcode_write_timeout [i915]] warning: pcode (write of 0x00000011 to mbox 11) mailbox access failed for hsw_write_dcomp [i915]: -6 <7>[ 269.915995] i915 0000:00:02.0: [drm:sandybridge_pcode_read [i915]] warning: pcode (read from mbox 5) mailbox access failed for intel_rc6_enable [i915]: -6 These errors may be related to the hang, I'd suggest tracking the s/r hang on HSW in a ticket for these errors. > > * igt at kms_vblank@pipe-a-wait-forked: > - shard-iclb: [PASS][3] -> [TIMEOUT][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_vblank@pipe-a-wait-forked.html > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/i > gt at kms_vblank@pipe-a-wait-forked.html > > > #### Warnings #### > > * igt at kms_atomic@plane-primary-overlay-mutable-zpos: > - shard-iclb: [SKIP][5] ([i915#404]) -> [TIMEOUT][6] > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at kms_atomic@plane-primary-overlay-mutable-zpos.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/i > gt at kms_atomic@plane-primary-overlay-mutable-zpos.html The above two timeouts are the same and actually happened already in gem_exec_balancer at sliced preceeding the above two tests. The https://gitlab.freedesktop.org/drm/intel/-/issues/1958 ticket is collecting similar timeouts. The pattern looks like: 6,58482,570332183,-;gem_exec_balanc D13040 1291 962 0x00000000 6,58483,570332186,-;Call Trace: 6,58484,570332189,-; __schedule+0x2f8/0x8d0 6,58485,570332194,-; schedule+0x37/0xe0 6,58486,570332229,-; intel_wakeref_wait_for_idle+0x7b/0xf0 [i915] 6,58487,570332233,-; ? wake_up_var+0x30/0x30 6,58488,570332257,-; i915_drop_caches_set+0x1c1/0x270 [i915] 6,58489,570332261,-; simple_attr_write+0xb0/0xd0 6,58490,570332266,-; full_proxy_write+0x51/0x80 6,58491,570332269,-; vfs_write+0xbc/0x1d0 6,58492,570332272,-; ksys_write+0xa2/0xe0 6,58493,570332275,-; do_syscall_64+0x56/0xe0 6,58494,570332277,-; entry_SYSCALL_64_after_hwframe+0x44/0xa9 as in https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8662/shard-tglb7/igt at gem_exec_balancer@sliced.html > > > Known issues > ------------ > > Here are the changes found in Patchwork_18037_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt at gem_exec_balancer@sliced: > - shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#1958]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb5/igt at gem_exec_balancer@sliced.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb4/igt at gem_exec_balancer@sliced.html > > * igt at gem_mmap_gtt@ptrace: > - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#95]) +15 similar issues > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gem_mmap_gtt@ptrace.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at gem_mmap_gtt@ptrace.html > > * igt at i915_selftest@mock at requests: > - shard-glk: [PASS][11] -> [INCOMPLETE][12] ([i915#2110] / [i915#58] / [k.org#198133]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk7/igt at i915_selftest@mock at requests.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk3/igt at i915_selftest@mock at requests.html > > * igt at kms_big_fb@y-tiled-64bpp-rotate-180: > - shard-glk: [PASS][13] -> [DMESG-FAIL][14] ([i915#118] / [i915#95]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk6/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html > > * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: > - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#93] / [i915#95]) +2 similar issues > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html > > * igt at kms_flip@basic-plain-flip at a-edp1: > - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +7 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at kms_flip@basic-plain-flip at a-edp1.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl9/igt at kms_flip@basic-plain-flip at a-edp1.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1: > - shard-apl: [PASS][19] -> [FAIL][20] ([i915#79]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-dp1.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: > - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl6/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html > > * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2: > - shard-glk: [PASS][23] -> [FAIL][24] ([i915#79]) > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-hdmi-a2.html > > * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: > - shard-kbl: [PASS][25] -> [DMESG-WARN][26] ([i915#180]) +5 similar issues > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html > > * igt at kms_flip@flip-vs-suspend at c-hdmi-a1: > - shard-hsw: [PASS][27] -> [INCOMPLETE][28] ([i915#2055]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-hsw1/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-hsw8/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html > > * igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack: > - shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html > > * igt at kms_hdr@bpc-switch-suspend: > - shard-skl: [PASS][31] -> [FAIL][32] ([i915#1188]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html > > * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: > - shard-skl: [PASS][33] -> [DMESG-FAIL][34] ([fdo#108145] / [i915#1982]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html > > * igt at kms_prime@basic-crc at second-to-first: > - shard-kbl: [PASS][35] -> [DMESG-FAIL][36] ([i915#95]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl6/igt at kms_prime@basic-crc at second-to-first.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl4/igt at kms_prime@basic-crc at second-to-first.html > > * igt at kms_psr@psr2_cursor_mmap_cpu: > - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at kms_psr@psr2_cursor_mmap_cpu.html > > * igt at kms_vblank@pipe-c-wait-idle: > - shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#1982]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at kms_vblank@pipe-c-wait-idle.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_vblank@pipe-c-wait-idle.html > > * igt at perf_pmu@semaphore-busy at rcs0: > - shard-kbl: [PASS][41] -> [FAIL][42] ([i915#1820]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html > > * igt at prime_mmap_kms@buffer-sharing: > - shard-tglb: [PASS][43] -> [DMESG-WARN][44] ([i915#402]) > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb7/igt at prime_mmap_kms@buffer-sharing.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb2/igt at prime_mmap_kms@buffer-sharing.html > > > #### Possible fixes #### > > * igt at gem_ctx_isolation@preservation-s3 at vecs0: > - shard-kbl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl7/igt at gem_ctx_isolation@preservation-s3 at vecs0.html > > * igt at gem_exec_nop@basic-parallel: > - shard-apl: [DMESG-WARN][47] ([i915#1635] / [i915#95]) -> [PASS][48] +22 similar issues > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl2/igt at gem_exec_nop@basic-parallel.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at gem_exec_nop@basic-parallel.html > > * igt at gem_mmap_gtt@cpuset-big-copy-odd: > - shard-skl: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50] +10 similar issues > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl7/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl3/igt at gem_mmap_gtt@cpuset-big-copy-odd.html > > * igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc: > - shard-iclb: [INCOMPLETE][51] -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb4/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb7/igt at gem_userptr_blits@invalid-mmap-offset-unsync at uc.html > > * igt at gen9_exec_parse@allowed-all: > - shard-apl: [DMESG-WARN][53] ([i915#1436] / [i915#716]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at gen9_exec_parse@allowed-all.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl1/igt at gen9_exec_parse@allowed-all.html > > * igt at gen9_exec_parse@allowed-single: > - shard-skl: [DMESG-WARN][55] ([i915#1436] / [i915#716]) -> [PASS][56] > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl4/igt at gen9_exec_parse@allowed-single.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl5/igt at gen9_exec_parse@allowed-single.html > > * igt at i915_module_load@reload: > - shard-tglb: [DMESG-WARN][57] ([i915#402]) -> [PASS][58] +1 similar issue > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at i915_module_load@reload.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at i915_module_load@reload.html > > * igt at kms_atomic_interruptible@legacy-dpms: > - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] +1 similar issue > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-kbl1/igt at kms_atomic_interruptible@legacy-dpms.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-kbl3/igt at kms_atomic_interruptible@legacy-dpms.html > > * igt at kms_big_fb@linear-64bpp-rotate-180: > - shard-glk: [DMESG-FAIL][61] ([i915#118] / [i915#95]) -> [PASS][62] > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-180.html > > * igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite: > - shard-tglb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +1 similar issue > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb2/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb7/igt at kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: > - shard-skl: [DMESG-FAIL][65] ([fdo#108145] / [i915#1982]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl9/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html > > * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [FAIL][67] ([fdo#108145] / [i915#265]) -> [PASS][68] +1 similar issue > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-skl8/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: > - shard-iclb: [DMESG-WARN][69] ([i915#1982]) -> [PASS][70] +2 similar issues > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html > > * igt at kms_psr2_su@page_flip: > - shard-iclb: [SKIP][71] ([fdo#109642] / [fdo#111068]) -> [PASS][72] > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr2_su@page_flip.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr2_su@page_flip.html > > * igt at kms_psr@psr2_sprite_render: > - shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74] +1 similar issue > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb3/igt at kms_psr@psr2_sprite_render.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb2/igt at kms_psr@psr2_sprite_render.html > > * igt at perf@polling-parameterized: > - shard-iclb: [FAIL][75] ([i915#1542]) -> [PASS][76] > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb1/igt at perf@polling-parameterized.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb3/igt at perf@polling-parameterized.html > - shard-tglb: [FAIL][77] ([i915#1542]) -> [PASS][78] > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-tglb6/igt at perf@polling-parameterized.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-tglb1/igt at perf@polling-parameterized.html > > > #### Warnings #### > > * igt at i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][79] ([i915#588]) -> [SKIP][80] ([i915#658]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-iclb2/igt at i915_pm_dc@dc3co-vpb-simulation.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-iclb1/igt at i915_pm_dc@dc3co-vpb-simulation.html > > * igt at kms_color_chamelium@pipe-b-ctm-0-75: > - shard-apl: [SKIP][81] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +1 similar issue > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at kms_color_chamelium@pipe-b-ctm-0-75.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_color_chamelium@pipe-b-ctm-0-75.html > > * igt at kms_cursor_crc@pipe-d-cursor-512x512-random: > - shard-apl: [SKIP][83] ([fdo#109271]) -> [SKIP][84] ([fdo#109271] / [i915#1635]) +5 similar issues > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html > > * igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge: > - shard-apl: [SKIP][85] ([fdo#109271] / [i915#1635]) -> [SKIP][86] ([fdo#109271]) +5 similar issues > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl8/igt at kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html > > * igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: > - shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1635] / [i915#95]) > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html > > * igt at runner@aborted: > - shard-apl: ([FAIL][89], [FAIL][90], [FAIL][91]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#716]) -> [FAIL][92] ([i915#1635]) > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl4/igt at runner@aborted.html > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl3/igt at runner@aborted.html > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8676/shard-apl8/igt at runner@aborted.html > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/shard-apl6/igt at runner@aborted.html > > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 > [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 > [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404 > [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 > [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8676 -> Patchwork_18037 > > CI-20190529: 20190529 > CI_DRM_8676: 90573bcfde94b770410e07294c914b2c630d3999 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18037: 06139c9eefa6a6cebf31d6c8a560fe29aeee0a05 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18037/index.html --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From patchwork at emeril.freedesktop.org Tue Jun 30 14:37:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 14:37:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkJVSUxEOiBmYWlsdXJlIGZvciBT?= =?utf-8?q?end_a_hotplug_when_edid_changes_=28rev10=29?= In-Reply-To: <20200630002700.5451-1-kunal1.joshi@intel.com> References: <20200630002700.5451-1-kunal1.joshi@intel.com> Message-ID: <159352785930.22704.2642567378748133067@emeril.freedesktop.org> == Series Details == Series: Send a hotplug when edid changes (rev10) URL : https://patchwork.freedesktop.org/series/62816/ State : failure == Summary == Applying: drm: Add helper to compare edids. Using index info to reconstruct a base tree... M drivers/gpu/drm/drm_edid.c M include/drm/drm_edid.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/drm_edid.c CONFLICT (content): Merge conflict in drivers/gpu/drm/drm_edid.c error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm: Add helper to compare edids. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". From patchwork at emeril.freedesktop.org Tue Jun 30 14:37:41 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 14:37:41 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgZHJt?= =?utf-8?q?/i915/ehl=3A_Add_new_PCI_ids?= In-Reply-To: <20200629200609.91058-1-jose.souza@intel.com> References: <20200629200609.91058-1-jose.souza@intel.com> Message-ID: <159352786195.22703.12045524884155621510@emeril.freedesktop.org> == Series Details == Series: drm/i915/ehl: Add new PCI ids URL : https://patchwork.freedesktop.org/series/78910/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8677_full -> Patchwork_18038_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18038_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18038_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18038_full: ### IGT changes ### #### Possible regressions #### * igt at prime_mmap_coherency@read: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb5/igt at prime_mmap_coherency@read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-tglb1/igt at prime_mmap_coherency@read.html Known issues ------------ Here are the changes found in Patchwork_18038_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-tglb7/igt at i915_module_load@reload-with-fault-injection.html * igt at i915_pm_dc@dc6-psr: - shard-iclb: [PASS][5] -> [FAIL][6] ([i915#454]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb6/igt at i915_pm_dc@dc6-psr.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-iclb6/igt at i915_pm_dc@dc6-psr.html * igt at i915_selftest@mock at requests: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#198] / [i915#2110]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl1/igt at i915_selftest@mock at requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl2/igt at i915_selftest@mock at requests.html * igt at i915_suspend@forcewake: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl1/igt at i915_suspend@forcewake.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl7/igt at i915_suspend@forcewake.html * igt at kms_big_fb@y-tiled-8bpp-rotate-180: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl6/igt at kms_big_fb@y-tiled-8bpp-rotate-180.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl6/igt at kms_big_fb@y-tiled-8bpp-rotate-180.html * igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding: - shard-apl: [PASS][13] -> [FAIL][14] ([i915#54]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl3/igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl4/igt at kms_cursor_crc@pipe-a-cursor-128x42-sliding.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#93] / [i915#95]) +2 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl7/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +10 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl2/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl10/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#1635] / [i915#95]) +18 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl8/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl7/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@pipe-d-torture-move: - shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#128]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb6/igt at kms_cursor_legacy@pipe-d-torture-move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-tglb5/igt at kms_cursor_legacy@pipe-d-torture-move.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#79]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl10/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-suspend at a-dp1: - shard-kbl: [PASS][25] -> [INCOMPLETE][26] ([i915#155]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl7/igt at kms_flip@flip-vs-suspend at a-dp1.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl4/igt at kms_flip@flip-vs-suspend at a-dp1.html * igt at kms_flip@flip-vs-suspend at c-edp1: - shard-skl: [PASS][27] -> [INCOMPLETE][28] ([i915#198]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at kms_flip@flip-vs-suspend at c-edp1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl7/igt at kms_flip@flip-vs-suspend at c-edp1.html * igt at kms_frontbuffer_tracking@psr-farfromfence: - shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb6/igt at kms_frontbuffer_tracking@psr-farfromfence.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-tglb5/igt at kms_frontbuffer_tracking@psr-farfromfence.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][31] -> [FAIL][32] ([i915#1188]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][33] -> [FAIL][34] ([fdo#108145] / [i915#265]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl5/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][35] -> [DMESG-FAIL][36] ([i915#95]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl3/igt at kms_prime@basic-crc at second-to-first.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl3/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-iclb8/igt at kms_psr@psr2_sprite_plane_move.html #### Possible fixes #### * igt at gem_cs_tlb@engines at vecs0: - shard-skl: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +6 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl5/igt at gem_cs_tlb@engines at vecs0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl3/igt at gem_cs_tlb@engines at vecs0.html * igt at gem_exec_nop@basic-parallel: - shard-apl: [DMESG-WARN][41] ([i915#1635] / [i915#95]) -> [PASS][42] +20 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl2/igt at gem_exec_nop@basic-parallel.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl1/igt at gem_exec_nop@basic-parallel.html * igt at gem_exec_whisper@basic-fds-priority-all: - shard-glk: [DMESG-WARN][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk4/igt at gem_exec_whisper@basic-fds-priority-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-glk2/igt at gem_exec_whisper@basic-fds-priority-all.html * igt at i915_pm_dc@dc5-psr: - shard-skl: [INCOMPLETE][45] ([i915#198]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl4/igt at i915_pm_dc@dc5-psr.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl8/igt at i915_pm_dc@dc5-psr.html * igt at kms_big_fb@linear-32bpp-rotate-0: - shard-apl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl8/igt at kms_big_fb@linear-32bpp-rotate-0.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl7/igt at kms_big_fb@linear-32bpp-rotate-0.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][49] ([i915#118] / [i915#95]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen: - shard-skl: [FAIL][51] ([i915#54]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl1/igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html * igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [FAIL][53] ([i915#96]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-hsw8/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-hsw6/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled: - shard-snb: [SKIP][55] ([fdo#109271]) -> [PASS][56] +3 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-snb1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-snb6/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html * igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][57] ([i915#1928]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk6/igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-glk5/igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1: - shard-skl: [FAIL][59] ([i915#1928]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl10/igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@fbc-stridechange: - shard-kbl: [DMESG-WARN][61] ([i915#93] / [i915#95]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-stridechange.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-stridechange.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-tglb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb3/igt at kms_frontbuffer_tracking@psr-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-tglb8/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][65] ([i915#1188]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl4/igt at kms_hdr@bpc-switch-dpms.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][67] ([fdo#108145] / [i915#1982]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl7/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +3 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb5/igt at kms_psr@psr2_cursor_mmap_cpu.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-iclb2/igt at kms_psr@psr2_cursor_mmap_cpu.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-tglb: [DMESG-WARN][71] ([i915#402]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb8/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-tglb3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +7 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl6/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@blocking-parameterized: - shard-iclb: [FAIL][75] ([i915#1542]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb4/igt at perf@blocking-parameterized.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-iclb1/igt at perf@blocking-parameterized.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][77] ([i915#1820]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl6/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at kms_color_chamelium@pipe-a-ctm-max: - shard-apl: [SKIP][79] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][80] ([fdo#109271] / [fdo#111827]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl6/igt at kms_color_chamelium@pipe-a-ctm-max.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl2/igt at kms_color_chamelium@pipe-a-ctm-max.html * igt at kms_color_chamelium@pipe-b-ctm-0-75: - shard-apl: [SKIP][81] ([fdo#109271] / [fdo#111827]) -> [SKIP][82] ([fdo#109271] / [fdo#111827] / [i915#1635]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl3/igt at kms_color_chamelium@pipe-b-ctm-0-75.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl6/igt at kms_color_chamelium@pipe-b-ctm-0-75.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][85] ([fdo#109349]) -> [DMESG-WARN][86] ([i915#1226]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb5/igt at kms_dp_dsc@basic-dsc-enable-edp.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-apl: [SKIP][87] ([fdo#109271] / [i915#1635]) -> [SKIP][88] ([fdo#109271]) +7 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl1/igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl2/igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@psr-1p-rte: - shard-apl: [SKIP][89] ([fdo#109271]) -> [SKIP][90] ([fdo#109271] / [i915#1635]) +5 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl1/igt at kms_frontbuffer_tracking@psr-1p-rte.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl2/igt at kms_frontbuffer_tracking@psr-1p-rte.html * igt at kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [DMESG-FAIL][91] ([fdo#108145] / [i915#1982]) -> [DMESG-WARN][92] ([i915#1982]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl10/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-skl7/igt at kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt at runner@aborted: - shard-apl: ([FAIL][93], [FAIL][94], [FAIL][95]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#716]) -> ([FAIL][96], [FAIL][97]) ([fdo#109271] / [i915#1635] / [i915#716]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl7/igt at runner@aborted.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl4/igt at runner@aborted.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl8/igt at runner@aborted.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl7/igt at runner@aborted.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/shard-apl4/igt at runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8677 -> Patchwork_18038 CI-20190529: 20190529 CI_DRM_8677: 47bc281ce35e7872ee04238b2f5e81aeeeb2337b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18038: 8df9867d9a35c7d544a36e580c070bb46cf86479 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18038/index.html From linux at roeck-us.net Tue Jun 30 15:01:05 2020 From: linux at roeck-us.net (Guenter Roeck) Date: Tue, 30 Jun 2020 08:01:05 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Protect debugfs per_file_stats with RCU lock In-Reply-To: <159350846525.9830.11510134258802464713@build.alporthouse.com> References: <20190903062133.27360-1-chris@chris-wilson.co.uk> <20200630053936.GA168021@roeck-us.net> <159350846525.9830.11510134258802464713@build.alporthouse.com> Message-ID: <20200630150105.GA13355@roeck-us.net> On Tue, Jun 30, 2020 at 10:14:25AM +0100, Chris Wilson wrote: [ ... ] > > > @@ -328,9 +334,9 @@ static void print_context_stats(struct seq_file *m, > > > struct task_struct *task; > > > char name[80]; > > > > > > - spin_lock(&file->table_lock); > > > + rcu_read_lock(); > > > idr_for_each(&file->object_idr, per_file_stats, &stats); > > > - spin_unlock(&file->table_lock); > > > + rcu_read_unlock(); > > > > > For my education - is it indeed possible and valid to replace spin_lock() > > with rcu_read_lock() to prevent list manipulation for a list used by > > idr_for_each(), even if that list is otherwise manipulated under the > > spinlock ? > > It's a pure read of a radixtree here, and is supposed to be RCU safe: > > * idr_for_each() can be called concurrently with idr_alloc() and > * idr_remove() if protected by RCU. Newly added entries may not be > * seen and deleted entries may be seen, but adding and removing entries > * will not cause other entries to be skipped, nor spurious ones to be seen. > > That is the tree structure is stable. > Ah, that makes sense. Thanks for the clarification. > > Background: we are seeing a crash with the following call trace. > > > > [ 1016.651593] BUG: kernel NULL pointer dereference, address: 0000000000000000 > > ... > > [ 1016.651693] Call Trace: > > [ 1016.651703] idr_for_each+0x8a/0xe8 > > [ 1016.651711] i915_gem_object_info+0x2a3/0x3eb > > [ 1016.651720] seq_read+0x162/0x3ca > > [ 1016.651727] full_proxy_read+0x5b/0x8d > > [ 1016.651733] __vfs_read+0x45/0x1bb > > [ 1016.651741] vfs_read+0xc9/0x15e > > [ 1016.651746] ksys_read+0x7e/0xde > > [ 1016.651752] do_syscall_64+0x54/0x68 > > [ 1016.651758] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > Actually, the crash is not in idr_for_each, but in per_file_stats: [ 1016.651637] RIP: 0010:per_file_stats+0xe/0x16e [ 1016.651646] Code: d2 41 0f b6 8e 69 8c 00 00 48 89 df 48 c7 c6 7b 74 8c be 31 c0 e8 0c 89 cf ff eb d2 0f 1f 44 00 00 55 48 89 e5 41 57 41 56 53 <8b> 06 85 c0 0f 84 4d 01 00 00 49 89 d6 48 89 f3 3d ff ff ff 7f 73 [ 1016.651651] RSP: 0018:ffffad3a01337ba0 EFLAGS: 00010293 [ 1016.651656] RAX: 0000000000000018 RBX: ffff96fe040d65e0 RCX: 0000000000000002 [ 1016.651660] RDX: ffffad3a01337c50 RSI: 0000000000000000 RDI: 00000000000001e8 [ 1016.651663] RBP: ffffad3a01337bb8 R08: 0000000000000000 R09: 00000000000001c0 [ 1016.651667] R10: 0000000000000000 R11: ffffffffbdbe5fce R12: 0000000000000000 [ 1016.651671] R13: ffffffffbdbe5fce R14: ffffad3a01337c50 R15: 0000000000000001 [ 1016.651676] FS: 00007a597e2d7480(0000) GS:ffff96ff3bb00000(0000) knlGS:0000000000000000 [ 1016.651680] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1016.651683] CR2: 0000000000000000 CR3: 0000000171fc2001 CR4: 00000000003606e0 [ 1016.651687] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 1016.651690] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 1016.651693] Call Trace: Sorry for the confusion. From the context it appears that the second parameter of per_file_stats() may be NULL, though I am not entirely sure if I got that correctly. > Is there a reason you are using this slow debugfs in the first place? AFAICS ChromeOS is using the information to calculate graphics memory use. Guenter From patchwork at emeril.freedesktop.org Tue Jun 30 15:04:33 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 15:04:33 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/hdcp=3A_Update_CP_as_per_the_kernel_internal_state_=28rev?= =?utf-8?q?5=29?= In-Reply-To: <20200630082048.22308-1-anshuman.gupta@intel.com> References: <20200630082048.22308-1-anshuman.gupta@intel.com> Message-ID: <159352947312.22702.14376614660712513078@emeril.freedesktop.org> == Series Details == Series: drm/i915/hdcp: Update CP as per the kernel internal state (rev5) URL : https://patchwork.freedesktop.org/series/72251/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678 -> Patchwork_18042 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/index.html Known issues ------------ Here are the changes found in Patchwork_18042 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-byt-j1900/igt at i915_pm_rpm@module-reload.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html * igt at kms_pipe_crc_basic@read-crc-pipe-a: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/fi-kbl-x1275/igt at kms_pipe_crc_basic@read-crc-pipe-a.html [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18042 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18042: b97d79fa049ee3f3da673cd51616695c69da60c2 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == b97d79fa049e drm/i915/hdcp: Update CP as per the kernel internal state == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/index.html From chris at chris-wilson.co.uk Tue Jun 30 15:08:00 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 16:08:00 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Protect debugfs per_file_stats with RCU lock In-Reply-To: <20200630150105.GA13355@roeck-us.net> References: <20190903062133.27360-1-chris@chris-wilson.co.uk> <20200630053936.GA168021@roeck-us.net> <159350846525.9830.11510134258802464713@build.alporthouse.com> <20200630150105.GA13355@roeck-us.net> Message-ID: <159352968098.22902.15606199075854362593@build.alporthouse.com> Quoting Guenter Roeck (2020-06-30 16:01:05) > On Tue, Jun 30, 2020 at 10:14:25AM +0100, Chris Wilson wrote: > [ ... ] > > > > @@ -328,9 +334,9 @@ static void print_context_stats(struct seq_file *m, > > > > struct task_struct *task; > > > > char name[80]; > > > > > > > > - spin_lock(&file->table_lock); > > > > + rcu_read_lock(); > > > > idr_for_each(&file->object_idr, per_file_stats, &stats); > > > > - spin_unlock(&file->table_lock); > > > > + rcu_read_unlock(); > > > > > > > For my education - is it indeed possible and valid to replace spin_lock() > > > with rcu_read_lock() to prevent list manipulation for a list used by > > > idr_for_each(), even if that list is otherwise manipulated under the > > > spinlock ? > > > > It's a pure read of a radixtree here, and is supposed to be RCU safe: > > > > * idr_for_each() can be called concurrently with idr_alloc() and > > * idr_remove() if protected by RCU. Newly added entries may not be > > * seen and deleted entries may be seen, but adding and removing entries > > * will not cause other entries to be skipped, nor spurious ones to be seen. > > > > That is the tree structure is stable. > > > Ah, that makes sense. Thanks for the clarification. > > > > Background: we are seeing a crash with the following call trace. > > > > > > [ 1016.651593] BUG: kernel NULL pointer dereference, address: 0000000000000000 > > > ... > > > [ 1016.651693] Call Trace: > > > [ 1016.651703] idr_for_each+0x8a/0xe8 > > > [ 1016.651711] i915_gem_object_info+0x2a3/0x3eb > > > [ 1016.651720] seq_read+0x162/0x3ca > > > [ 1016.651727] full_proxy_read+0x5b/0x8d > > > [ 1016.651733] __vfs_read+0x45/0x1bb > > > [ 1016.651741] vfs_read+0xc9/0x15e > > > [ 1016.651746] ksys_read+0x7e/0xde > > > [ 1016.651752] do_syscall_64+0x54/0x68 > > > [ 1016.651758] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > > > Actually, the crash is not in idr_for_each, but in per_file_stats: Ok, let's assume that the object is being closed as we read the idr. The idr will temporarily hold an error pointer for the handle to indicate the in-progress closure, so something like: @@ -230,7 +230,7 @@ static int per_file_stats(int id, void *ptr, void *data) struct file_stats *stats = data; struct i915_vma *vma; - if (!kref_get_unless_zero(&obj->base.refcount)) + if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount)) return 0; -Chris From patchwork at emeril.freedesktop.org Tue Jun 30 15:19:01 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 15:19:01 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/display=3A_Implement_new_combo_phy_initialization_step_?= =?utf-8?b?KHJldjMp?= In-Reply-To: <20200625195252.39312-1-jose.souza@intel.com> References: <20200625195252.39312-1-jose.souza@intel.com> Message-ID: <159353034184.22702.7903745831240645250@emeril.freedesktop.org> == Series Details == Series: drm/i915/display: Implement new combo phy initialization step (rev3) URL : https://patchwork.freedesktop.org/series/78796/ State : success == Summary == CI Bug Log - changes from CI_DRM_8677_full -> Patchwork_18039_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18039_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox: - shard-kbl: [PASS][1] -> [FAIL][2] ([i915#1528]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl7/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl4/igt at gem_ctx_persistence@legacy-engines-mixed-process at vebox.html * igt at i915_module_load@reload: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb3/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-tglb6/igt at i915_module_load@reload.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl7/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl6/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_legacy@pipe-b-torture-move: - shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#128]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb5/igt at kms_cursor_legacy@pipe-b-torture-move.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-tglb1/igt at kms_cursor_legacy@pipe-b-torture-move.html * igt at kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset at ab-vga1-hdmi-a1: - shard-hsw: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-hsw8/igt at kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset at ab-vga1-hdmi-a1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-hsw6/igt at kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset at ab-vga1-hdmi-a1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1: - shard-skl: [PASS][11] -> [FAIL][12] ([i915#79]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl10/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl1/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1: - shard-skl: [PASS][15] -> [FAIL][16] ([i915#1928]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl10/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl5/igt at kms_flip@plain-flip-fb-recreate-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#1635] / [i915#95]) +13 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl7/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-apl2/igt at kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb5/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-iclb6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145] / [i915#265]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][25] -> [DMESG-FAIL][26] ([i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl3/igt at kms_prime@basic-crc at second-to-first.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl7/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-b-query-idle: - shard-skl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +11 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl5/igt at kms_vblank@pipe-b-query-idle.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl5/igt at kms_vblank@pipe-b-query-idle.html * igt at kms_vblank@pipe-c-ts-continuation-suspend: - shard-skl: [PASS][31] -> [INCOMPLETE][32] ([i915#69]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl1/igt at kms_vblank@pipe-c-ts-continuation-suspend.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl4/igt at kms_vblank@pipe-c-ts-continuation-suspend.html * igt at perf@polling-parameterized: - shard-iclb: [PASS][33] -> [FAIL][34] ([i915#1542]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb6/igt at perf@polling-parameterized.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-iclb7/igt at perf@polling-parameterized.html #### Possible fixes #### * igt at gem_exec_whisper@basic-fds-priority-all: - shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk4/igt at gem_exec_whisper@basic-fds-priority-all.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-glk7/igt at gem_exec_whisper@basic-fds-priority-all.html * igt at i915_pm_dc@dc5-psr: - shard-skl: [INCOMPLETE][37] ([i915#198]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl4/igt at i915_pm_dc@dc5-psr.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl6/igt at i915_pm_dc@dc5-psr.html * igt at kms_busy@basic-modeset-pipe-b: - shard-kbl: [DMESG-WARN][39] ([i915#93] / [i915#95]) -> [PASS][40] +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl3/igt at kms_busy@basic-modeset-pipe-b.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl7/igt at kms_busy@basic-modeset-pipe-b.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42] +5 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl5/igt at kms_color@pipe-c-ctm-0-25.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl5/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen: - shard-skl: [FAIL][43] ([i915#54]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl3/igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html * igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: [FAIL][45] ([i915#96]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-hsw8/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-hsw1/igt at kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled: - shard-snb: [SKIP][47] ([fdo#109271]) -> [PASS][48] +3 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-snb1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-snb4/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html * igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][49] ([i915#1928]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk6/igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-glk9/igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1: - shard-skl: [FAIL][51] ([i915#1928]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl2/igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-tglb: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb3/igt at kms_frontbuffer_tracking@psr-suspend.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-tglb6/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][55] ([fdo#108145] / [i915#265]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl9/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl2/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_psr2_su@page_flip: - shard-iclb: [SKIP][57] ([fdo#109642] / [fdo#111068]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb7/igt at kms_psr2_su@page_flip.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-iclb2/igt at kms_psr2_su@page_flip.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb3/igt at kms_psr@psr2_primary_mmap_gtt.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-tglb: [DMESG-WARN][61] ([i915#402]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb8/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-tglb3/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +4 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl2/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@invalid-oa-metric-set-id: - shard-apl: [DMESG-WARN][65] ([i915#1635] / [i915#95]) -> [PASS][66] +17 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl3/igt at perf@invalid-oa-metric-set-id.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-apl4/igt at perf@invalid-oa-metric-set-id.html #### Warnings #### * igt at kms_color_chamelium@pipe-b-ctm-0-75: - shard-apl: [SKIP][67] ([fdo#109271] / [fdo#111827]) -> [SKIP][68] ([fdo#109271] / [fdo#111827] / [i915#1635]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl3/igt at kms_color_chamelium@pipe-b-ctm-0-75.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-apl6/igt at kms_color_chamelium@pipe-b-ctm-0-75.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][69] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][70] ([i915#93] / [i915#95]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu: - shard-apl: [SKIP][71] ([fdo#109271] / [i915#1635]) -> [SKIP][72] ([fdo#109271]) +3 similar issues [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl4/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-apl8/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html * igt at kms_frontbuffer_tracking@psr-rgb565-draw-render: - shard-apl: [SKIP][73] ([fdo#109271]) -> [SKIP][74] ([fdo#109271] / [i915#1635]) +5 similar issues [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-render.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-apl2/igt at kms_frontbuffer_tracking@psr-rgb565-draw-render.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [DMESG-WARN][75] ([i915#93] / [i915#95]) -> [DMESG-WARN][76] ([i915#180] / [i915#93] / [i915#95]) +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-kbl3/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][77] ([fdo#108145] / [i915#1982]) -> [FAIL][78] ([fdo#108145] / [i915#265]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-skl2/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at runner@aborted: - shard-apl: ([FAIL][79], [FAIL][80], [FAIL][81]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#716]) -> ([FAIL][82], [FAIL][83]) ([fdo#109271] / [i915#1635] / [i915#716]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl7/igt at runner@aborted.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl4/igt at runner@aborted.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl8/igt at runner@aborted.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-apl3/igt at runner@aborted.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-apl2/igt at runner@aborted.html - shard-tglb: [FAIL][84] ([i915#2110]) -> [FAIL][85] ([i915#1764] / [i915#2110]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb5/igt at runner@aborted.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/shard-tglb3/igt at runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8677 -> Patchwork_18039 CI-20190529: 20190529 CI_DRM_8677: 47bc281ce35e7872ee04238b2f5e81aeeeb2337b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18039: 4d7881077c256917fd39d2633f0d66a4ec1b7077 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18039/index.html From chris at chris-wilson.co.uk Tue Jun 30 15:27:24 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 16:27:24 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Skip stale object handle for debugfs per-file-stats Message-ID: <20200630152724.3734-1-chris@chris-wilson.co.uk> As we close a handle GEM object, we update the drm_file's idr with an error pointer to indicate the in-progress closure, and finally set it to NULL. If we read the idr directly, we may then see an invalid object pointer, and in our debugfs per_file_stats() we therefore need to protect against the entry being invalid. [ 1016.651637] RIP: 0010:per_file_stats+0xe/0x16e [ 1016.651646] Code: d2 41 0f b6 8e 69 8c 00 00 48 89 df 48 c7 c6 7b 74 8c be 31 c0 e8 0c 89 cf ff eb d2 0f 1f 44 00 00 55 48 89 e5 41 57 41 56 53 <8b> 06 85 c0 0f 84 4d 01 00 00 49 89 d6 48 89 f3 3d ff ff ff 7f 73 [ 1016.651651] RSP: 0018:ffffad3a01337ba0 EFLAGS: 00010293 [ 1016.651656] RAX: 0000000000000018 RBX: ffff96fe040d65e0 RCX: 0000000000000002 [ 1016.651660] RDX: ffffad3a01337c50 RSI: 0000000000000000 RDI: 00000000000001e8 [ 1016.651663] RBP: ffffad3a01337bb8 R08: 0000000000000000 R09: 00000000000001c0 [ 1016.651667] R10: 0000000000000000 R11: ffffffffbdbe5fce R12: 0000000000000000 [ 1016.651671] R13: ffffffffbdbe5fce R14: ffffad3a01337c50 R15: 0000000000000001 [ 1016.651676] FS: 00007a597e2d7480(0000) GS:ffff96ff3bb00000(0000) knlGS:0000000000000000 [ 1016.651680] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1016.651683] CR2: 0000000000000000 CR3: 0000000171fc2001 CR4: 00000000003606e0 [ 1016.651687] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 1016.651690] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 1016.651693] Call Trace: [ 1016.651693] Call Trace: [ 1016.651703] idr_for_each+0x8a/0xe8 [ 1016.651711] i915_gem_object_info+0x2a3/0x3eb [ 1016.651720] seq_read+0x162/0x3ca [ 1016.651727] full_proxy_read+0x5b/0x8d [ 1016.651733] __vfs_read+0x45/0x1bb [ 1016.651741] vfs_read+0xc9/0x15e [ 1016.651746] ksys_read+0x7e/0xde [ 1016.651752] do_syscall_64+0x54/0x68 [ 1016.651758] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Reported-by: Guenter Roeck <linux at roeck-us.net> Fixes: a8c15954d64a ("drm/i915: Protect debugfs per_file_stats with RCU lock") Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> Cc: Guenter Roeck <linux at roeck-us.net> Cc: stable at vger.kernel.org --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8594a8ef08ce..9ca94a435b75 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -230,7 +230,7 @@ static int per_file_stats(int id, void *ptr, void *data) struct file_stats *stats = data; struct i915_vma *vma; - if (!kref_get_unless_zero(&obj->base.refcount)) + if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount)) return 0; stats->count++; -- 2.20.1 From ville.syrjala at linux.intel.com Tue Jun 30 15:30:16 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 30 Jun 2020 18:30:16 +0300 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200626232641.4557-1-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> Message-ID: <20200630153016.GK6112@intel.com> On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote: > Modify the helper to add a fixed delay or poll with timeout > based on platform specification to check for either Idle bit > set (DDI_BUF_CTL is idle for disable case) > > v3: > * Change the timeout to 16usecs (Ville) > v2: > * Use 2 separate functions or idle and active (Ville) Missing changelog? Did somehting change? > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > 1 file changed, 8 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 884b507c5f55..052a74625a61 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > enum port port) > { > - i915_reg_t reg = DDI_BUF_CTL(port); > - int i; > - > - for (i = 0; i < 16; i++) { > - udelay(1); > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > - return; > + if (IS_BROXTON(dev_priv)) { > + udelay(16); > + return; > } > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > - port_name(port)); > + > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 16)) > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > + port_name(port)); > } > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > -- > 2.19.1 -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 30 15:33:41 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 30 Jun 2020 18:33:41 +0300 Subject: [Intel-gfx] [PATCH v2 4/5] drm/i915: Initial implementation of PSR2 selective fetch In-Reply-To: <20200626010151.221388-4-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> <20200626010151.221388-4-jose.souza@intel.com> Message-ID: <20200630153341.GL6112@intel.com> On Thu, Jun 25, 2020 at 06:01:50PM -0700, Jos? Roberto de Souza wrote: > All GEN12 platforms supports PSR2 selective fetch but not all GEN12 > platforms supports PSR2 hardware tracking(aka RKL). > > This feature consists in software programming registers with the > damaged area of each plane this way hardware will only fetch from > memory those areas and sent the PSR2 selective update blocks to panel, > saving even more power. > > But as initial step it is only enabling the full frame fetch at > every flip, the actual selective fetch part will come in a future > patch. > > Also this is only handling the page flip side, it is still completely > missing frontbuffer modifications, that is why the > enable_psr2_sel_fetch parameter was added. > > BSpec: 55229 > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com> > Signed-off-by: Jos? Roberto de Souza <jose.souza at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 + > .../drm/i915/display/intel_display_debugfs.c | 3 + > .../drm/i915/display/intel_display_types.h | 3 + > drivers/gpu/drm/i915/display/intel_psr.c | 95 ++++++++++++++++--- > drivers/gpu/drm/i915/display/intel_psr.h | 5 + > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/i915_params.c | 5 + > drivers/gpu/drm/i915/i915_params.h | 1 + > 8 files changed, 103 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index b66008b80589..eb3a4f317b01 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -15114,6 +15114,8 @@ static void commit_pipe_config(struct intel_atomic_state *state, > > if (new_crtc_state->update_pipe) > intel_pipe_fastset(old_crtc_state, new_crtc_state); > + > + intel_psr2_program_trans_man_trk_ctl(new_crtc_state); > } > > if (dev_priv->display.atomic_update_watermarks) > @@ -15155,6 +15157,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, > intel_color_load_luts(new_crtc_state); > > intel_pre_plane_update(state, crtc); > + intel_psr2_sel_fetch_update(state, crtc); You seem to be modifying the crtc state here. No good. Ideally the state should be const for the whole programming step. > > if (new_crtc_state->update_pipe) > intel_encoders_update_pipe(state, crtc); > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index d1cb48b3f462..4c9591f7ed92 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -417,6 +417,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); > seq_printf(m, "%d\t%d\n", frame, su_blocks); > } > + > + seq_printf(m, "PSR2 selective fetch: %s\n", > + enableddisabled(psr->psr2_sel_fetch_enabled)); > } > > unlock: > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 4b0aaa3081c9..44c98ae3964e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -931,6 +931,7 @@ struct intel_crtc_state { > > bool has_psr; > bool has_psr2; > + bool enable_psr2_sel_fetch; > u32 dc3co_exitline; > > /* > @@ -1073,6 +1074,8 @@ struct intel_crtc_state { > > /* For DSB related info */ > struct intel_dsb *dsb; > + > + u32 psr2_man_track_ctl; > }; > > enum intel_pipe_crc_source { > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 611cb8d74811..078987a878b0 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -553,6 +553,14 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > val |= EDP_PSR2_FAST_WAKE(7); > } > > + if (dev_priv->psr.psr2_sel_fetch_enabled) > + intel_de_write(dev_priv, > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), > + PSR2_MAN_TRK_CTL_ENABLE); > + else if (HAS_PSR2_SEL_FETCH(dev_priv)) > + intel_de_write(dev_priv, > + PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder), 0); > + > /* > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is > * recommending keep this bit unset while PSR2 is enabled. > @@ -663,6 +671,38 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, > crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; > } > > +static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, > + struct intel_crtc_state *crtc_state) > +{ > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > + struct intel_plane_state *plane_state; > + struct intel_plane *plane; > + int i; > + > + if (!dev_priv->params.enable_psr2_sel_fetch) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 sel fetch not enabled, disabled by parameter\n"); > + return false; > + } > + > + if (crtc_state->uapi.async_flip) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 sel fetch not enabled, async flip enabled\n"); > + return false; > + } > + > + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { > + if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 sel fetch not enabled, plane rotated\n"); > + return false; > + } > + } > + > + return crtc_state->enable_psr2_sel_fetch = true; > +} > + > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state) > { > @@ -732,22 +772,17 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > - /* > - * Some platforms lack PSR2 HW tracking and instead require manual > - * tracking by software. In this case, the driver is required to track > - * the areas that need updates and program hardware to send selective > - * updates. > - * > - * So until the software tracking is implemented, PSR2 needs to be > - * disabled for platforms without PSR2 HW tracking. > - */ > - if (!HAS_PSR_HW_TRACKING(dev_priv)) { > - drm_dbg_kms(&dev_priv->drm, > - "No PSR2 HW tracking in the platform\n"); > - return false; > + if (HAS_PSR2_SEL_FETCH(dev_priv)) { > + if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && > + !HAS_PSR_HW_TRACKING(dev_priv)) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); > + return false; > + } > } > > - if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { > + if (!crtc_state->enable_psr2_sel_fetch && > + (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { > drm_dbg_kms(&dev_priv->drm, > "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", > crtc_hdisplay, crtc_vdisplay, > @@ -898,6 +933,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, > val |= EXITLINE_ENABLE; > intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); > } > + > + if (HAS_PSR_HW_TRACKING(dev_priv)) > + intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, > + dev_priv->psr.psr2_sel_fetch_enabled ? > + IGNORE_PSR2_HW_TRACKING : 0); > } > > static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > @@ -919,6 +959,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, > /* DC5/DC6 requires at least 6 idle frames */ > val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > dev_priv->psr.dc3co_exit_delay = val; > + dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; > > /* > * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR > @@ -1115,6 +1156,32 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) > intel_psr_exit(dev_priv); > } > > +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + struct i915_psr *psr = &dev_priv->psr; > + > + if (!HAS_PSR2_SEL_FETCH(dev_priv) || > + !crtc_state->enable_psr2_sel_fetch) > + return; > + > + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder), > + crtc_state->psr2_man_track_ctl); > +} > + > +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > +{ > + struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); > + > + if (!crtc_state->enable_psr2_sel_fetch) > + return; > + > + crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE | > + PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; > +} > + > /** > * intel_psr_update - Update PSR state > * @intel_dp: Intel DP > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h > index b4515186d5f4..6a83c8e682e6 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.h > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > @@ -13,6 +13,8 @@ struct drm_connector_state; > struct drm_i915_private; > struct intel_crtc_state; > struct intel_dp; > +struct intel_crtc; > +struct intel_atomic_state; > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) > void intel_psr_init_dpcd(struct intel_dp *intel_dp); > @@ -43,5 +45,8 @@ void intel_psr_atomic_check(struct drm_connector *connector, > struct drm_connector_state *old_state, > struct drm_connector_state *new_state); > void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp); > +void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > + struct intel_crtc *crtc); > +void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); > > #endif /* __INTEL_PSR_H__ */ > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 9aad3ec979bd..038bd57e429e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -503,6 +503,7 @@ struct i915_psr { > bool link_standby; > bool colorimetry_support; > bool psr2_enabled; > + bool psr2_sel_fetch_enabled; > u8 sink_sync_latency; > ktime_t last_entry_attempt; > ktime_t last_exit; > @@ -1651,6 +1652,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > #define HAS_PSR_HW_TRACKING(dev_priv) \ > (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) > +#define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12) > #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) > > #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) > diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c > index a7b61e6ec508..da686f8bcb09 100644 > --- a/drivers/gpu/drm/i915/i915_params.c > +++ b/drivers/gpu/drm/i915/i915_params.c > @@ -102,6 +102,11 @@ i915_param_named(psr_safest_params, bool, 0400, > "is helpfull to detect if PSR issues are related to bad values set in " > " VBT. (0=use VBT paramters, 1=use safest parameters)"); > > +i915_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, > + "Enable PSR2 selective fetch " > + "(0=disabled, 1=enabled) " > + "Default: 0"); > + > i915_param_named_unsafe(force_probe, charp, 0400, > "Force probe the driver for specified devices. " > "See CONFIG_DRM_I915_FORCE_PROBE for details."); > diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h > index 53fb5ba8fbed..330c03e2b4f7 100644 > --- a/drivers/gpu/drm/i915/i915_params.h > +++ b/drivers/gpu/drm/i915/i915_params.h > @@ -54,6 +54,7 @@ struct drm_printer; > param(int, enable_fbc, -1, 0600) \ > param(int, enable_psr, -1, 0600) \ > param(bool, psr_safest_params, false, 0600) \ > + param(bool, enable_psr2_sel_fetch, false, 0600) \ > param(int, disable_power_well, -1, 0400) \ > param(int, enable_ips, 1, 0600) \ > param(int, invert_brightness, 0, 0600) \ > -- > 2.27.0 -- Ville Syrj?l? Intel From linux at roeck-us.net Tue Jun 30 15:48:53 2020 From: linux at roeck-us.net (Guenter Roeck) Date: Tue, 30 Jun 2020 08:48:53 -0700 Subject: [Intel-gfx] [PATCH] drm/i915: Protect debugfs per_file_stats with RCU lock In-Reply-To: <159352968098.22902.15606199075854362593@build.alporthouse.com> References: <20190903062133.27360-1-chris@chris-wilson.co.uk> <20200630053936.GA168021@roeck-us.net> <159350846525.9830.11510134258802464713@build.alporthouse.com> <20200630150105.GA13355@roeck-us.net> <159352968098.22902.15606199075854362593@build.alporthouse.com> Message-ID: <20200630154853.GA54681@roeck-us.net> On Tue, Jun 30, 2020 at 04:08:00PM +0100, Chris Wilson wrote: > Quoting Guenter Roeck (2020-06-30 16:01:05) > > On Tue, Jun 30, 2020 at 10:14:25AM +0100, Chris Wilson wrote: > > [ ... ] > > > > > @@ -328,9 +334,9 @@ static void print_context_stats(struct seq_file *m, > > > > > struct task_struct *task; > > > > > char name[80]; > > > > > > > > > > - spin_lock(&file->table_lock); > > > > > + rcu_read_lock(); > > > > > idr_for_each(&file->object_idr, per_file_stats, &stats); > > > > > - spin_unlock(&file->table_lock); > > > > > + rcu_read_unlock(); > > > > > > > > > For my education - is it indeed possible and valid to replace spin_lock() > > > > with rcu_read_lock() to prevent list manipulation for a list used by > > > > idr_for_each(), even if that list is otherwise manipulated under the > > > > spinlock ? > > > > > > It's a pure read of a radixtree here, and is supposed to be RCU safe: > > > > > > * idr_for_each() can be called concurrently with idr_alloc() and > > > * idr_remove() if protected by RCU. Newly added entries may not be > > > * seen and deleted entries may be seen, but adding and removing entries > > > * will not cause other entries to be skipped, nor spurious ones to be seen. > > > > > > That is the tree structure is stable. > > > > > Ah, that makes sense. Thanks for the clarification. > > > > > > Background: we are seeing a crash with the following call trace. > > > > > > > > [ 1016.651593] BUG: kernel NULL pointer dereference, address: 0000000000000000 > > > > ... > > > > [ 1016.651693] Call Trace: > > > > [ 1016.651703] idr_for_each+0x8a/0xe8 > > > > [ 1016.651711] i915_gem_object_info+0x2a3/0x3eb > > > > [ 1016.651720] seq_read+0x162/0x3ca > > > > [ 1016.651727] full_proxy_read+0x5b/0x8d > > > > [ 1016.651733] __vfs_read+0x45/0x1bb > > > > [ 1016.651741] vfs_read+0xc9/0x15e > > > > [ 1016.651746] ksys_read+0x7e/0xde > > > > [ 1016.651752] do_syscall_64+0x54/0x68 > > > > [ 1016.651758] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > > > > > Actually, the crash is not in idr_for_each, but in per_file_stats: > > Ok, let's assume that the object is being closed as we read the idr. The > idr will temporarily hold an error pointer for the handle to indicate the > in-progress closure, so something like: > > @@ -230,7 +230,7 @@ static int per_file_stats(int id, void *ptr, void *data) > struct file_stats *stats = data; > struct i915_vma *vma; > > - if (!kref_get_unless_zero(&obj->base.refcount)) > + if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount)) > return 0; > Makes sense. Thanks a lot for the patch! Guenter From patchwork at emeril.freedesktop.org Tue Jun 30 15:52:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 15:52:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Delay_attach_mmu-notifier_until_we_acquire_the_pin?= =?utf-8?q?ned_userptr?= In-Reply-To: <20200630111421.12301-1-chris@chris-wilson.co.uk> References: <20200630111421.12301-1-chris@chris-wilson.co.uk> Message-ID: <159353234469.22703.15842560452605086756@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Delay attach mmu-notifier until we acquire the pinned userptr URL : https://patchwork.freedesktop.org/series/78938/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678 -> Patchwork_18043 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/index.html Known issues ------------ Here are the changes found in Patchwork_18043 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-byt-n2820: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-byt-n2820/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/fi-byt-n2820/igt at i915_module_load@reload.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][3] -> [DMESG-WARN][4] ([i915#62] / [i915#92] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_busy@basic at flip.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/fi-kbl-x1275/igt at kms_busy@basic at flip.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1: - fi-icl-u2: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at b-edp1.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92]) -> [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][14] ([i915#62] / [i915#92]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18043 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18043: cd98f8cb0ad0febd089b3baa38b5c3385783b6ff @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == cd98f8cb0ad0 drm/i915/gem: Delay attach mmu-notifier until we acquire the pinned userptr == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/index.html From jani.nikula at linux.intel.com Tue Jun 30 15:54:21 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 18:54:21 +0300 Subject: [Intel-gfx] [PATCH v2 1/6] drm/i915: move ICL port F hack to intel_bios In-Reply-To: <20200625001120.22810-2-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> <20200625001120.22810-2-lucas.demarchi@intel.com> Message-ID: <871rlwmtw2.fsf@intel.com> On Wed, 24 Jun 2020, Lucas De Marchi <lucas.demarchi at intel.com> wrote: > Move the check for port F to intel_bios.c and just make intel_ddi_init() > call it. This will allow the output initialization of ICL to be like > platforms after it, allowing us to make it generic. > > Suggested-by: Jani Nikula <jani.nikula at linux.intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> > --- > drivers/gpu/drm/i915/display/intel_bios.c | 23 +++++++++++++++----- > drivers/gpu/drm/i915/display/intel_display.c | 10 +-------- > 2 files changed, 18 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c > index 6593e2c38043..9d42ea3721cd 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -1668,16 +1668,27 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, > [PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, > }; > > - if (IS_ROCKETLAKE(dev_priv)) > + if (IS_ROCKETLAKE(dev_priv)) { > return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), > ARRAY_SIZE(rkl_port_mapping[0]), > rkl_port_mapping, > dvo_port); > - else > - return __dvo_port_to_port(ARRAY_SIZE(port_mapping), > - ARRAY_SIZE(port_mapping[0]), > - port_mapping, > - dvo_port); > + } else { > + enum port port = __dvo_port_to_port(ARRAY_SIZE(port_mapping), > + ARRAY_SIZE(port_mapping[0]), > + port_mapping, > + dvo_port); > + > + /* > + * On some ICL SKUs port F is not present. Work around broken > + * VBTs by allowing port F only on select SKUs. > + */ > + if (port == PORT_F && IS_ICELAKE(dev_priv) && > + !IS_ICL_WITH_PORT_F(dev_priv)) I'd perhaps add a debug message here, but either way, Reviewed-by: Jani Nikula <jani.nikula at intel.com> > + return PORT_NONE; > + > + return port; > + } > } > > static void parse_ddi_port(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index a11bb675f9b3..49772c82a299 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -16842,15 +16842,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > intel_ddi_init(dev_priv, PORT_C); > intel_ddi_init(dev_priv, PORT_D); > intel_ddi_init(dev_priv, PORT_E); > - /* > - * On some ICL SKUs port F is not present. No strap bits for > - * this, so rely on VBT. > - * Work around broken VBTs on SKUs known to have no port F. > - */ > - if (IS_ICL_WITH_PORT_F(dev_priv) && > - intel_bios_is_port_present(dev_priv, PORT_F)) > - intel_ddi_init(dev_priv, PORT_F); > - > + intel_ddi_init(dev_priv, PORT_F); > icl_dsi_init(dev_priv); > } else if (IS_GEN9_LP(dev_priv)) { > /* -- Jani Nikula, Intel Open Source Graphics Center From jani.nikula at linux.intel.com Tue Jun 30 15:55:38 2020 From: jani.nikula at linux.intel.com (Jani Nikula) Date: Tue, 30 Jun 2020 18:55:38 +0300 Subject: [Intel-gfx] [PATCH v2 2/6] drm/i915/display: fix comment on skl straps In-Reply-To: <20200625001120.22810-3-lucas.demarchi@intel.com> References: <20200625001120.22810-1-lucas.demarchi@intel.com> <20200625001120.22810-3-lucas.demarchi@intel.com> Message-ID: <87y2o4lf9h.fsf@intel.com> On Wed, 24 Jun 2020, Lucas De Marchi <lucas.demarchi at intel.com> wrote: > We are not checking for specific SKUs and feedback from HW team is that > it may not work since it was supposed to be fixed by the same time > straps stopped to be used. So, just update comment. > > v2: Instead of removing the check, just update the comment since > feedback from HW team was that it actually may not work > > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com> Acked-by: Jani Nikula <jani.nikula at intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 49772c82a299..effd6b65f270 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -16863,8 +16863,9 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > /* > * Haswell uses DDI functions to detect digital outputs. > - * On SKL pre-D0 the strap isn't connected, so we assume > - * it's there. > + * On SKL pre-D0 the strap isn't connected. Later SKUs may or > + * may not have it - it was supposed to be fixed by the same > + * time we stopped using straps. Assume it's there. > */ > found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; > /* WaIgnoreDDIAStrap: skl */ -- Jani Nikula, Intel Open Source Graphics Center From patchwork at emeril.freedesktop.org Tue Jun 30 15:56:44 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 15:56:44 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915=3A_Clamp_min=5Fcdclk_to_max=5Fcdclk=5Ffreq_to_unbl?= =?utf-8?q?ock_8K?= In-Reply-To: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> References: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> Message-ID: <159353260416.22704.15974363712976543717@emeril.freedesktop.org> == Series Details == Series: drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K URL : https://patchwork.freedesktop.org/series/78940/ State : warning == Summary == $ dim checkpatch origin/drm-tip abfcf6db3529 drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K -:29: WARNING:MINMAX: min() should probably be min_t(int, min_cdclk, dev_priv->max_cdclk_freq) #29: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:2090: + min_cdclk = min(min_cdclk, (int)dev_priv->max_cdclk_freq); total: 0 errors, 1 warnings, 0 checks, 22 lines checked From mika.kuoppala at linux.intel.com Tue Jun 30 16:16:43 2020 From: mika.kuoppala at linux.intel.com (Mika Kuoppala) Date: Tue, 30 Jun 2020 19:16:43 +0300 Subject: [Intel-gfx] [PATCH] drm/i915: Skip stale object handle for debugfs per-file-stats In-Reply-To: <20200630152724.3734-1-chris@chris-wilson.co.uk> References: <20200630152724.3734-1-chris@chris-wilson.co.uk> Message-ID: <87imf84jh0.fsf@gaia.fi.intel.com> Chris Wilson <chris at chris-wilson.co.uk> writes: > As we close a handle GEM object, we update the drm_file's idr with an > error pointer to indicate the in-progress closure, and finally set it to The error pointer part stage seems to be missing. But the finding is valid. Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com> > NULL. If we read the idr directly, we may then see an invalid object > pointer, and in our debugfs per_file_stats() we therefore need to > protect against the entry being invalid. > > [ 1016.651637] RIP: 0010:per_file_stats+0xe/0x16e > [ 1016.651646] Code: d2 41 0f b6 8e 69 8c 00 00 48 89 df 48 c7 c6 7b 74 8c be 31 c0 e8 0c 89 cf ff eb d2 0f 1f 44 00 00 55 48 89 e5 41 > 57 41 56 53 <8b> 06 85 c0 0f 84 4d 01 00 00 49 89 d6 48 89 f3 3d ff ff ff 7f 73 > [ 1016.651651] RSP: 0018:ffffad3a01337ba0 EFLAGS: 00010293 > [ 1016.651656] RAX: 0000000000000018 RBX: ffff96fe040d65e0 RCX: 0000000000000002 > [ 1016.651660] RDX: ffffad3a01337c50 RSI: 0000000000000000 RDI: 00000000000001e8 > [ 1016.651663] RBP: ffffad3a01337bb8 R08: 0000000000000000 R09: 00000000000001c0 > [ 1016.651667] R10: 0000000000000000 R11: ffffffffbdbe5fce R12: 0000000000000000 > [ 1016.651671] R13: ffffffffbdbe5fce R14: ffffad3a01337c50 R15: 0000000000000001 > [ 1016.651676] FS: 00007a597e2d7480(0000) GS:ffff96ff3bb00000(0000) knlGS:0000000000000000 > [ 1016.651680] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 1016.651683] CR2: 0000000000000000 CR3: 0000000171fc2001 CR4: 00000000003606e0 > [ 1016.651687] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > [ 1016.651690] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 > [ 1016.651693] Call Trace: > [ 1016.651693] Call Trace: > [ 1016.651703] idr_for_each+0x8a/0xe8 > [ 1016.651711] i915_gem_object_info+0x2a3/0x3eb > [ 1016.651720] seq_read+0x162/0x3ca > [ 1016.651727] full_proxy_read+0x5b/0x8d > [ 1016.651733] __vfs_read+0x45/0x1bb > [ 1016.651741] vfs_read+0xc9/0x15e > [ 1016.651746] ksys_read+0x7e/0xde > [ 1016.651752] do_syscall_64+0x54/0x68 > [ 1016.651758] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > > Reported-by: Guenter Roeck <linux at roeck-us.net> > Fixes: a8c15954d64a ("drm/i915: Protect debugfs per_file_stats with RCU lock") > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com> > Cc: Guenter Roeck <linux at roeck-us.net> > Cc: stable at vger.kernel.org > --- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 8594a8ef08ce..9ca94a435b75 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -230,7 +230,7 @@ static int per_file_stats(int id, void *ptr, void *data) > struct file_stats *stats = data; > struct i915_vma *vma; > > - if (!kref_get_unless_zero(&obj->base.refcount)) > + if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount)) > return 0; > > stats->count++; > -- > 2.20.1 From patchwork at emeril.freedesktop.org Tue Jun 30 16:19:45 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 16:19:45 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Clamp_min=5Fcdclk_to_max=5Fcdclk=5Ffreq_to_unblock_8K?= In-Reply-To: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> References: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> Message-ID: <159353398568.22702.1471890659392890775@emeril.freedesktop.org> == Series Details == Series: drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K URL : https://patchwork.freedesktop.org/series/78940/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678 -> Patchwork_18044 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/index.html Known issues ------------ Here are the changes found in Patchwork_18044 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-tgl-u2/igt at i915_module_load@reload.html * igt at i915_pm_rpm@basic-pci-d3-state: - fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-byt-j1900/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_selftest@live at gem_contexts: - fi-tgl-u2: [PASS][7] -> [INCOMPLETE][8] ([i915#1932] / [i915#2045]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-tgl-u2/igt at i915_selftest@live at gem_contexts.html * igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1: - fi-icl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-icl-u2/igt at kms_flip@basic-flip-vs-wf_vblank at c-edp1.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html * igt at kms_force_connector_basic@prune-stale-modes: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/fi-kbl-x1275/igt at kms_force_connector_basic@prune-stale-modes.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1932]: https://gitlab.freedesktop.org/drm/intel/issues/1932 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2045]: https://gitlab.freedesktop.org/drm/intel/issues/2045 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18044 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18044: abfcf6db3529c248344aaeb3e113cec6eadcd592 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == abfcf6db3529 drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/index.html From ville.syrjala at linux.intel.com Tue Jun 30 16:29:09 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Tue, 30 Jun 2020 19:29:09 +0300 Subject: [Intel-gfx] [PATCH v1] drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K In-Reply-To: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> References: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> Message-ID: <20200630162909.GR6112@intel.com> On Tue, Jun 30, 2020 at 02:26:09PM +0300, Stanislav Lisovskiy wrote: > We still need "Bump up CDCLK" workaround otherwise getting > underruns - however currently it blocks 8K as CDCLK = Pixel rate, > in 8K case would require CDCLK to be around 1 Ghz which is not > possible. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 45f7f33d1144..01a5bc6b08c4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2080,9 +2080,21 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > * Explicitly stating here that this seems to be currently > * rather a Hack, than final solution. > */ > - if (IS_TIGERLAKE(dev_priv)) > + if (IS_TIGERLAKE(dev_priv)) { > min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > > + /* > + * Clamp to max_cdclk_freq in order not to break an 8K, > + * but still leave W/A at place. > + */ > + min_cdclk = min(min_cdclk, (int)dev_priv->max_cdclk_freq); > + > + /* > + * max_cdclk_freq check obviously not needed - just return. > + */ > + return min_cdclk; Pointless return. But I think we should actually keep the max_cdclk check. Something like: min_cdclk = max(min_cdclk, min(max_cdclk, pixel_rate)); Also what's with the (int) casts? There is min_t() if you actually need casts. But not sure why we need them though. > + } > + > if (min_cdclk > dev_priv->max_cdclk_freq) { > drm_dbg_kms(&dev_priv->drm, > "required cdclk (%d kHz) exceeds max (%d kHz)\n", > -- > 2.24.1.485.gad05a3d8e5 -- Ville Syrj?l? Intel From patchwork at emeril.freedesktop.org Tue Jun 30 16:45:24 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 16:45:24 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_drm/i915/gem=3A_Always_do_pin=5Fuser=5Fpages_under_the_mmu-?= =?utf-8?q?notifier_=28rev2=29?= In-Reply-To: <20200630112854.30361-1-chris@chris-wilson.co.uk> References: <20200630112854.30361-1-chris@chris-wilson.co.uk> Message-ID: <159353552439.22701.14005121342739071590@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Always do pin_user_pages under the mmu-notifier (rev2) URL : https://patchwork.freedesktop.org/series/78941/ State : warning == Summary == $ dim checkpatch origin/drm-tip 01fe075c6b02 drm/i915/gem: Always do pin_user_pages under the mmu-notifier -:103: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!work" #103: FILE: drivers/gpu/drm/i915/gem/i915_gem_userptr.c:551: + if (work == NULL) total: 0 errors, 0 warnings, 1 checks, 138 lines checked From sean at poorly.run Tue Jun 30 16:48:34 2020 From: sean at poorly.run (Sean Paul) Date: Tue, 30 Jun 2020 12:48:34 -0400 Subject: [Intel-gfx] [PATCH v7 15/17] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message In-Reply-To: <20200630140929.GE15183@intel.com> References: <20200623155907.22961-1-sean@poorly.run> <20200623155907.22961-16-sean@poorly.run> <20200630140929.GE15183@intel.com> Message-ID: <CAMavQK+mkmUWfV-F_+=qN1RuTDvJ6QF=UhjfPXZFhbk7FQwXwg@mail.gmail.com> On Tue, Jun 30, 2020 at 10:21 AM Anshuman Gupta <anshuman.gupta at intel.com> wrote: > > On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote: > Hi Sean, > I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a. > I have looked the entire series, i will take up this opportunity to review > the series from HDCP over DP MST POV. > I think theoretically this series should work or Gen12 as well, as DP MST streams > are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction msg > (generating Stream State Signature L?). > I will test this on Gen12 H/W with DP MST support and will provide my inputs. > > Meanwhile while going through DP MST v1.2a specs(Page 262) came to know about > a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h), > Bit 2 : STREAM_STATUS_CHANGED. > When this bit set to ?1? indicates the source must re-check the Stream Status > with the QUERY_STREAM_ENCRYPTION_STATUS message. > Currently i feel this irq support is missing, do we require to support > above IRQ vector for DP MST stream encryption. > Hi Anshuman, Thank you for your comments. QUERY_STREAM_ENCRYPTION_STATUS is not necessary for HDCP 1.x, I added this as a safety check to ensure that the streams were being encrypted. As such, the existing integrity checks in place for DP are sufficient to satisfy spec. When HDCP 2.2 support is added for MST, handling QSES will need to be addressed to meet spec. Note also that we're not validating the QSES signature for the same reason. Sean > Thanks, > Anshuman Gupta. > > > From: Sean Paul <seanpaul at chromium.org> > > > > Used to query whether an MST stream is encrypted or not. > > > > Signed-off-by: Sean Paul <seanpaul at chromium.org> > > > > Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-sean at poorly.run #v4 > > Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-sean at poorly.run #v5 > > Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-sean at poorly.run #v6 > > > > Changes in v4: > > -Added to the set > > Changes in v5: > > -None > > Changes in v6: > > -Use FIELD_PREP to generate request buffer bitfields (Lyude) > > -Add mst selftest and dump/decode_sideband_req for QSES (Lyude) > > Changes in v7: > > -None > > --- > > drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++++++++++++++++ > > .../drm/selftests/test-drm_dp_mst_helper.c | 17 +++ > > include/drm/drm_dp_helper.h | 3 + > > include/drm/drm_dp_mst_helper.h | 44 ++++++ > > 4 files changed, 206 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > > index b2f5a84b4cfb..fc68478eaeb4 100644 > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > @@ -20,11 +20,13 @@ > > * OF THIS SOFTWARE. > > */ > > > > +#include <linux/bitfield.h> > > #include <linux/delay.h> > > #include <linux/errno.h> > > #include <linux/i2c.h> > > #include <linux/init.h> > > #include <linux/kernel.h> > > +#include <linux/random.h> > > #include <linux/sched.h> > > #include <linux/seq_file.h> > > #include <linux/iopoll.h> > > @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, > > memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes); > > idx += req->u.i2c_write.num_bytes; > > break; > > + case DP_QUERY_STREAM_ENC_STATUS: { > > + const struct drm_dp_query_stream_enc_status *msg; > > + > > + msg = &req->u.enc_status; > > + buf[idx] = msg->stream_id; > > + idx++; > > + memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id)); > > + idx += sizeof(msg->client_id); > > + buf[idx] = 0; > > + buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event); > > + buf[idx] |= msg->valid_stream_event ? BIT(2) : 0; > > + buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior); > > + buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0; > > + idx++; > > + } > > + break; > > } > > raw->cur_len = idx; > > } > > @@ -547,6 +565,20 @@ drm_dp_decode_sideband_req(const struct drm_dp_sideband_msg_tx *raw, > > return -ENOMEM; > > } > > break; > > + case DP_QUERY_STREAM_ENC_STATUS: > > + req->u.enc_status.stream_id = buf[idx++]; > > + for (i = 0; i < sizeof(req->u.enc_status.client_id); i++) > > + req->u.enc_status.client_id[i] = buf[idx++]; > > + > > + req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0), > > + buf[idx]); > > + req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2), > > + buf[idx]); > > + req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3), > > + buf[idx]); > > + req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5), > > + buf[idx]); > > + break; > > } > > > > return 0; > > @@ -625,6 +657,16 @@ drm_dp_dump_sideband_msg_req_body(const struct drm_dp_sideband_msg_req_body *req > > req->u.i2c_write.num_bytes, req->u.i2c_write.num_bytes, > > req->u.i2c_write.bytes); > > break; > > + case DP_QUERY_STREAM_ENC_STATUS: > > + P("stream_id=%u client_id=%*ph stream_event=%x " > > + "valid_event=%d stream_behavior=%x valid_behavior=%d", > > + req->u.enc_status.stream_id, > > + (int)ARRAY_SIZE(req->u.enc_status.client_id), > > + req->u.enc_status.client_id, req->u.enc_status.stream_event, > > + req->u.enc_status.valid_stream_event, > > + req->u.enc_status.stream_behavior, > > + req->u.enc_status.valid_stream_behavior); > > + break; > > default: > > P("???\n"); > > break; > > @@ -925,6 +967,34 @@ static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms > > return true; > > } > > > > +static bool > > +drm_dp_sideband_parse_query_stream_enc_status( > > + struct drm_dp_sideband_msg_rx *raw, > > + struct drm_dp_sideband_msg_reply_body *repmsg) > > +{ > > + struct drm_dp_query_stream_enc_status_ack_reply *reply; > > + > > + reply = &repmsg->u.enc_status; > > + > > + reply->stream_id = raw->msg[3]; > > + > > + reply->reply_signed = raw->msg[2] & BIT(0); > > + > > + reply->hdcp_1x_device_present = raw->msg[2] & BIT(3); > > + reply->hdcp_2x_device_present = raw->msg[2] & BIT(4); > > + > > + reply->query_capable_device_present = raw->msg[2] & BIT(5); > > + reply->legacy_device_present = raw->msg[2] & BIT(6); > > + reply->unauthorizable_device_present = raw->msg[2] & BIT(7); > > + > > + reply->auth_completed = !!(raw->msg[1] & BIT(3)); > > + reply->encryption_enabled = !!(raw->msg[1] & BIT(4)); > > + reply->repeater_present = !!(raw->msg[1] & BIT(5)); > > + reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6; > > + > > + return true; > > +} > > + > > static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, > > struct drm_dp_sideband_msg_reply_body *msg) > > { > > @@ -959,6 +1029,8 @@ static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, > > return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg); > > case DP_CLEAR_PAYLOAD_ID_TABLE: > > return true; /* since there's nothing to parse */ > > + case DP_QUERY_STREAM_ENC_STATUS: > > + return drm_dp_sideband_parse_query_stream_enc_status(raw, msg); > > default: > > DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type, > > drm_dp_mst_req_type_str(msg->req_type)); > > @@ -1109,6 +1181,25 @@ static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, > > msg->path_msg = true; > > } > > > > +static int > > +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id, > > + u8 *q_id) > > +{ > > + struct drm_dp_sideband_msg_req_body req; > > + > > + req.req_type = DP_QUERY_STREAM_ENC_STATUS; > > + req.u.enc_status.stream_id = stream_id; > > + memcpy(req.u.enc_status.client_id, q_id, > > + sizeof(req.u.enc_status.client_id)); > > + req.u.enc_status.stream_event = 0; > > + req.u.enc_status.valid_stream_event = false; > > + req.u.enc_status.stream_behavior = 0; > > + req.u.enc_status.valid_stream_behavior = false; > > + > > + drm_dp_encode_sideband_req(&req, msg); > > + return 0; > > +} > > + > > static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr, > > struct drm_dp_vcpi *vcpi) > > { > > @@ -3137,6 +3228,57 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, > > } > > EXPORT_SYMBOL(drm_dp_send_power_updown_phy); > > > > +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, > > + struct drm_dp_mst_port *port, > > + struct drm_dp_query_stream_enc_status_ack_reply *status) > > +{ > > + struct drm_dp_sideband_msg_tx *txmsg; > > + u8 nonce[7]; > > + int len, ret; > > + > > + txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); > > + if (!txmsg) > > + return -ENOMEM; > > + > > + port = drm_dp_mst_topology_get_port_validated(mgr, port); > > + if (!port) { > > + ret = -EINVAL; > > + goto out_get_port; > > + } > > + > > + get_random_bytes(nonce, sizeof(nonce)); > > + > > + /* > > + * "Source device targets the QUERY_STREAM_ENCRYPTION_STATUS message > > + * transaction at the MST Branch device directly connected to the > > + * Source" > > + */ > > + txmsg->dst = mgr->mst_primary; > > + > > + len = build_query_stream_enc_status(txmsg, port->vcpi.vcpi, nonce); > > + > > + drm_dp_queue_down_tx(mgr, txmsg); > > + > > + ret = drm_dp_mst_wait_tx_reply(mgr->mst_primary, txmsg); > > + if (ret < 0) { > > + goto out; > > + } else if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) { > > + DRM_DEBUG_KMS("query encryption status nak received\n"); > > + ret = -ENXIO; > > + goto out; > > + } > > + > > + ret = 0; > > + memcpy(status, &txmsg->reply.u.enc_status, sizeof(*status)); > > + > > +out: > > + drm_dp_mst_topology_put_port(port); > > +out_get_port: > > + kfree(txmsg); > > + return ret; > > +} > > +EXPORT_SYMBOL(drm_dp_send_query_stream_enc_status); > > + > > static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr, > > int id, > > struct drm_dp_payload *payload) > > diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c > > index bd990d178765..1d696ec001cf 100644 > > --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c > > +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c > > @@ -5,6 +5,8 @@ > > > > #define PREFIX_STR "[drm_dp_mst_helper]" > > > > +#include <linux/random.h> > > + > > #include <drm/drm_dp_mst_helper.h> > > #include <drm/drm_print.h> > > > > @@ -237,6 +239,21 @@ int igt_dp_mst_sideband_msg_req_decode(void *unused) > > in.u.i2c_write.bytes = data; > > DO_TEST(); > > > > + in.req_type = DP_QUERY_STREAM_ENC_STATUS; > > + in.u.enc_status.stream_id = 1; > > + DO_TEST(); > > + get_random_bytes(in.u.enc_status.client_id, > > + sizeof(in.u.enc_status.client_id)); > > + DO_TEST(); > > + in.u.enc_status.stream_event = 3; > > + DO_TEST(); > > + in.u.enc_status.valid_stream_event = 0; > > + DO_TEST(); > > + in.u.enc_status.stream_behavior = 3; > > + DO_TEST(); > > + in.u.enc_status.valid_stream_behavior = 1; > > + DO_TEST(); > > + > > #undef DO_TEST > > return 0; > > } > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index e47dc22ebf50..e2d2df5e869e 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -1108,6 +1108,9 @@ > > #define DP_POWER_DOWN_PHY 0x25 > > #define DP_SINK_EVENT_NOTIFY 0x30 > > #define DP_QUERY_STREAM_ENC_STATUS 0x38 > > +#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 > > +#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 > > +#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2 > > > > /* DP 1.2 MST sideband reply types */ > > #define DP_SIDEBAND_REPLY_ACK 0x00 > > diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h > > index 8b9eb4db3381..371eef8798ad 100644 > > --- a/include/drm/drm_dp_mst_helper.h > > +++ b/include/drm/drm_dp_mst_helper.h > > @@ -313,6 +313,34 @@ struct drm_dp_remote_i2c_write_ack_reply { > > u8 port_number; > > }; > > > > +struct drm_dp_query_stream_enc_status_ack_reply { > > + /* Bit[23:16]- Stream Id */ > > + u8 stream_id; > > + > > + /* Bit[15]- Signed */ > > + bool reply_signed; > > + > > + /* Bit[10:8]- Stream Output Sink Type */ > > + bool unauthorizable_device_present; > > + bool legacy_device_present; > > + bool query_capable_device_present; > > + > > + /* Bit[12:11]- Stream Output CP Type */ > > + bool hdcp_1x_device_present; > > + bool hdcp_2x_device_present; > > + > > + /* Bit[4]- Stream Authentication */ > > + bool auth_completed; > > + > > + /* Bit[3]- Stream Encryption */ > > + bool encryption_enabled; > > + > > + /* Bit[2]- Stream Repeater Function Present */ > > + bool repeater_present; > > + > > + /* Bit[1:0]- Stream State */ > > + u8 state; > > +}; > > > > #define DRM_DP_MAX_SDP_STREAMS 16 > > struct drm_dp_allocate_payload { > > @@ -374,6 +402,15 @@ struct drm_dp_remote_i2c_write { > > u8 *bytes; > > }; > > > > +struct drm_dp_query_stream_enc_status { > > + u8 stream_id; > > + u8 client_id[7]; /* 56-bit nonce */ > > + u8 stream_event; > > + bool valid_stream_event; > > + u8 stream_behavior; > > + u8 valid_stream_behavior; > > +}; > > + > > /* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ > > struct drm_dp_port_number_req { > > u8 port_number; > > @@ -422,6 +459,8 @@ struct drm_dp_sideband_msg_req_body { > > > > struct drm_dp_remote_i2c_read i2c_read; > > struct drm_dp_remote_i2c_write i2c_write; > > + > > + struct drm_dp_query_stream_enc_status enc_status; > > } u; > > }; > > > > @@ -444,6 +483,8 @@ struct drm_dp_sideband_msg_reply_body { > > struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; > > struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; > > struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack; > > + > > + struct drm_dp_query_stream_enc_status_ack_reply enc_status; > > } u; > > }; > > > > @@ -808,6 +849,9 @@ drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, > > struct drm_dp_mst_port *port); > > int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, > > struct drm_dp_mst_port *port, bool power_up); > > +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, > > + struct drm_dp_mst_port *port, > > + struct drm_dp_query_stream_enc_status_ack_reply *status); > > int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state); > > > > void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port); > > -- > > Sean Paul, Software Engineer, Google / Chromium OS > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From patchwork at emeril.freedesktop.org Tue Jun 30 17:06:42 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 17:06:42 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Always_do_pin=5Fuser=5Fpages_under_the_mmu-notifie?= =?utf-8?q?r_=28rev2=29?= In-Reply-To: <20200630112854.30361-1-chris@chris-wilson.co.uk> References: <20200630112854.30361-1-chris@chris-wilson.co.uk> Message-ID: <159353680232.22701.17260665927870521911@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Always do pin_user_pages under the mmu-notifier (rev2) URL : https://patchwork.freedesktop.org/series/78941/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678 -> Patchwork_18045 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/index.html Known issues ------------ Here are the changes found in Patchwork_18045 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at fbdev@mmap: - fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-byt-j1900/igt at fbdev@mmap.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-byt-j1900/igt at fbdev@mmap.html * igt at gem_exec_suspend@basic-s0: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-glk-dsi/igt at gem_exec_suspend@basic-s0.html - fi-tgl-u2: [PASS][5] -> [FAIL][6] ([i915#1888]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at kms_busy@basic at flip: - fi-kbl-x1275: [PASS][7] -> [DMESG-WARN][8] ([i915#62] / [i915#92] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_busy@basic at flip.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-kbl-x1275/igt at kms_busy@basic at flip.html * igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-tgl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#402]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-tgl-u2/igt at kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - fi-bsw-kefka: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-bsw-n3050: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-bsw-n3050/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-kbl-7560u}: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html - {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at i915_module_load@reload: - fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#62] / [i915#92]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at i915_module_load@reload.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-kbl-x1275/igt at i915_module_load@reload.html * igt at kms_flip@basic-flip-vs-modeset at a-dp1: - fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/fi-kbl-x1275/igt at kms_flip@basic-flip-vs-modeset at a-dp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18045 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18045: 01fe075c6b02c195bc1d13679d69c4c17738c554 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 01fe075c6b02 drm/i915/gem: Always do pin_user_pages under the mmu-notifier == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/index.html From patchwork at emeril.freedesktop.org Tue Jun 30 17:26:51 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 17:26:51 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5B1/2=5D_drm/i915/tgl=3A_Implement_WA_180114?= =?utf-8?q?64164?= In-Reply-To: <20200629212059.108460-1-jose.souza@intel.com> References: <20200629212059.108460-1-jose.souza@intel.com> Message-ID: <159353801108.22702.8423118790077090206@emeril.freedesktop.org> == Series Details == Series: series starting with [1/2] drm/i915/tgl: Implement WA 18011464164 URL : https://patchwork.freedesktop.org/series/78912/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8677_full -> Patchwork_18040_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_18040_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_18040_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18040_full: ### IGT changes ### #### Possible regressions #### * igt at i915_selftest@live at execlists: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb2/igt at i915_selftest@live at execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-iclb1/igt at i915_selftest@live at execlists.html Known issues ------------ Here are the changes found in Patchwork_18040_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd: - shard-skl: [PASS][3] -> [FAIL][4] ([i915#1528]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl6/igt at gem_ctx_persistence@legacy-engines-mixed-process at bsd.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-tglb8/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk1/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#95]) +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl4/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl7/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl4/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +15 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl2/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl7/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk8/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-glk5/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl10/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk9/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-glk4/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-hdmi-a2.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +7 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary: - shard-iclb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb4/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-iclb3/igt at kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl5/igt at kms_hdr@bpc-switch-suspend.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl7/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][29] -> [DMESG-FAIL][30] ([i915#95]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl3/igt at kms_prime@basic-crc at second-to-first.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl1/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-iclb5/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-c-wait-idle: - shard-kbl: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl7/igt at kms_vblank@pipe-c-wait-idle.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl4/igt at kms_vblank@pipe-c-wait-idle.html - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb6/igt at kms_vblank@pipe-c-wait-idle.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-tglb1/igt at kms_vblank@pipe-c-wait-idle.html - shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#1982]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl2/igt at kms_vblank@pipe-c-wait-idle.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl1/igt at kms_vblank@pipe-c-wait-idle.html #### Possible fixes #### * igt at gem_exec_nop@basic-parallel: - shard-apl: [DMESG-WARN][39] ([i915#1635] / [i915#95]) -> [PASS][40] +19 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl2/igt at gem_exec_nop@basic-parallel.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl1/igt at gem_exec_nop@basic-parallel.html * igt at i915_pm_dc@dc5-psr: - shard-skl: [INCOMPLETE][41] ([i915#198]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl4/igt at i915_pm_dc@dc5-psr.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl2/igt at i915_pm_dc@dc5-psr.html * igt at i915_selftest@mock at requests: - shard-apl: [INCOMPLETE][43] ([i915#1635] / [i915#2110]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl8/igt at i915_selftest@mock at requests.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl6/igt at i915_selftest@mock at requests.html * igt at kms_big_fb@linear-64bpp-rotate-180: - shard-glk: [DMESG-FAIL][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-180.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-glk3/igt at kms_big_fb@linear-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-0-25: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +6 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl5/igt at kms_color@pipe-c-ctm-0-25.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl7/igt at kms_color@pipe-c-ctm-0-25.html * igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen: - shard-skl: [FAIL][49] ([i915#54]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl1/igt at kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled: - shard-snb: [SKIP][51] ([fdo#109271]) -> [PASS][52] +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-snb1/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-snb4/igt at kms_draw_crc@draw-method-xrgb8888-mmap-gtt-xtiled.html * igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][53] ([i915#1928]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-glk6/igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-glk2/igt at kms_flip@2x-plain-flip-fb-recreate at ab-hdmi-a1-hdmi-a2.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl6/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl6/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1: - shard-skl: [FAIL][57] ([i915#1928]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl9/igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl6/igt at kms_flip@plain-flip-ts-check-interruptible at c-edp1.html * igt at kms_frontbuffer_tracking@fbc-stridechange: - shard-kbl: [DMESG-WARN][59] ([i915#93] / [i915#95]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-stridechange.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl1/igt at kms_frontbuffer_tracking@fbc-stridechange.html * igt at kms_frontbuffer_tracking@psr-suspend: - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb3/igt at kms_frontbuffer_tracking@psr-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-tglb2/igt at kms_frontbuffer_tracking@psr-suspend.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +4 similar issues [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl2/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][65] ([fdo#108145] / [i915#265]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl6/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl4/igt at kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt at kms_psr@psr2_suspend: - shard-iclb: [SKIP][67] ([fdo#109441]) -> [PASS][68] +3 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb5/igt at kms_psr@psr2_suspend.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-iclb2/igt at kms_psr@psr2_suspend.html * igt at kms_setmode@basic: - shard-kbl: [FAIL][69] ([i915#31]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl2/igt at kms_setmode@basic.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl2/igt at kms_setmode@basic.html * igt at kms_universal_plane@universal-plane-gen9-features-pipe-a: - shard-tglb: [DMESG-WARN][71] ([i915#402]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-tglb8/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-tglb1/igt at kms_universal_plane@universal-plane-gen9-features-pipe-a.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][73] ([i915#1820]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html #### Warnings #### * igt at gem_exec_reloc@basic-spin-others at vcs0: - shard-snb: [WARN][75] ([i915#2036]) -> [WARN][76] ([i915#2021]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-snb2/igt at gem_exec_reloc@basic-spin-others at vcs0.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-snb4/igt at gem_exec_reloc@basic-spin-others at vcs0.html * igt at kms_color_chamelium@pipe-a-ctm-max: - shard-apl: [SKIP][77] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][78] ([fdo#109271] / [fdo#111827]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl6/igt at kms_color_chamelium@pipe-a-ctm-max.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl8/igt at kms_color_chamelium@pipe-a-ctm-max.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][79] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][80] ([i915#93] / [i915#95]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl4/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl7/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-d-cursor-512x512-random: - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +4 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl8/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl6/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html * igt at kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: [SKIP][83] ([fdo#109349]) -> [DMESG-WARN][84] ([i915#1226]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb5/igt at kms_dp_dsc@basic-dsc-enable-edp.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-iclb2/igt at kms_dp_dsc@basic-dsc-enable-edp.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][85] ([i915#93] / [i915#95]) -> [DMESG-WARN][86] ([i915#180] / [i915#93] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-kbl2/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu: - shard-apl: [SKIP][87] ([fdo#109271] / [i915#1635]) -> [SKIP][88] ([fdo#109271]) +6 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl4/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl2/igt at kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu.html * igt at kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [DMESG-FAIL][89] ([fdo#108145] / [i915#1982]) -> [FAIL][90] ([fdo#108145] / [i915#265]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-skl8/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-skl6/igt at kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - shard-apl: [DMESG-FAIL][91] ([fdo#108145] / [i915#1635] / [i915#95]) -> [DMESG-FAIL][92] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl7/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl1/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html * igt at runner@aborted: - shard-iclb: ([FAIL][93], [FAIL][94]) ([i915#2110]) -> ([FAIL][95], [FAIL][96]) ([i915#1580] / [i915#2110]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb6/igt at runner@aborted.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-iclb6/igt at runner@aborted.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-iclb4/igt at runner@aborted.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-iclb1/igt at runner@aborted.html - shard-apl: ([FAIL][97], [FAIL][98], [FAIL][99]) ([fdo#109271] / [i915#1610] / [i915#1635] / [i915#716]) -> [FAIL][100] ([fdo#109271] / [i915#1635] / [i915#716]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl4/igt at runner@aborted.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl7/igt at runner@aborted.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8677/shard-apl8/igt at runner@aborted.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/shard-apl7/igt at runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226 [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 [i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580 [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8677 -> Patchwork_18040 CI-20190529: 20190529 CI_DRM_8677: 47bc281ce35e7872ee04238b2f5e81aeeeb2337b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18040: 2eb704061edc4ae027f42cdc7a36f73cfec9d7ce @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18040/index.html From chris at chris-wilson.co.uk Tue Jun 30 17:29:55 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 18:29:55 +0100 Subject: [Intel-gfx] [PATCH] drm/i915: Skip stale object handle for debugfs per-file-stats In-Reply-To: <87imf84jh0.fsf@gaia.fi.intel.com> References: <20200630152724.3734-1-chris@chris-wilson.co.uk> <87imf84jh0.fsf@gaia.fi.intel.com> Message-ID: <159353819588.22902.3876380735847727824@build.alporthouse.com> Quoting Mika Kuoppala (2020-06-30 17:16:43) > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > As we close a handle GEM object, we update the drm_file's idr with an > > error pointer to indicate the in-progress closure, and finally set it to > > The error pointer part stage seems to be missing. Yeah, the ERR_PTR stage seems to be my faulty memory, we just set it to NULL to indicate in-progress. Ok, I'm not going totally mad: commit f6cd7daecff558fab2c45d15283d3e52f688342d Author: Chris Wilson <chris at chris-wilson.co.uk> Date: Fri Apr 15 12:55:08 2016 +0100 drm: Release driver references to handle before making it available again ... v2: Use NULL rather than an ERR_PTR to avoid having to adjust callers. idr_alloc() tracks existing handles using an internal bitmap, so we are free to use the NULL object as our stale identifier. -Chris From patchwork at emeril.freedesktop.org Tue Jun 30 17:31:43 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 17:31:43 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Skip_stale_object_handle_for_debugfs_per-file-stats?= In-Reply-To: <20200630152724.3734-1-chris@chris-wilson.co.uk> References: <20200630152724.3734-1-chris@chris-wilson.co.uk> Message-ID: <159353830392.22704.13634343298264029366@emeril.freedesktop.org> == Series Details == Series: drm/i915: Skip stale object handle for debugfs per-file-stats URL : https://patchwork.freedesktop.org/series/78948/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678 -> Patchwork_18046 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/index.html Known issues ------------ Here are the changes found in Patchwork_18046 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at i915_module_load@reload: - fi-kbl-soraka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-soraka/igt at i915_module_load@reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/fi-kbl-soraka/igt at i915_module_load@reload.html #### Possible fixes #### * igt at i915_pm_rpm@module-reload: - fi-glk-dsi: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/fi-glk-dsi/igt at i915_pm_rpm@module-reload.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/fi-tgl-dsi/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at kms_cursor_legacy@basic-flip-after-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92]) -> [DMESG-WARN][10] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/fi-kbl-x1275/igt at kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 37) ------------------------------ Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18046 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18046: 285874eca3c1ebdce8e44eb5badf0f7bcd6a52e3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 285874eca3c1 drm/i915: Skip stale object handle for debugfs per-file-stats == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/index.html From patchwork at emeril.freedesktop.org Tue Jun 30 17:36:06 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 17:36:06 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_series_starting_with_=5Bv2=2C1/5=5D_drm/i915=3A_Add_plane_d?= =?utf-8?q?amage_clips_property_=28rev2=29?= In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <159353856684.22701.17198535197750851855@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/5] drm/i915: Add plane damage clips property (rev2) URL : https://patchwork.freedesktop.org/series/78830/ State : warning == Summary == $ dim checkpatch origin/drm-tip fea9da6ff306 drm/i915: Add plane damage clips property 7f207be6dc9f drm/i915: Reorder intel_psr2_config_valid() 8c1795e3dca7 drm/i915: Add PSR2 selective fetch registers -:37: WARNING:LONG_LINE: line length of 119 exceeds 100 columns #37: FILE: drivers/gpu/drm/i915/i915_reg.h:4593: +#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) -:39: WARNING:LONG_LINE: line length of 125 exceeds 100 columns #39: FILE: drivers/gpu/drm/i915/i915_reg.h:4595: +#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) -:71: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #71: FILE: drivers/gpu/drm/i915/i915_reg.h:7182: +#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) total: 0 errors, 3 warnings, 0 checks, 87 lines checked e320b2f92dfb drm/i915: Initial implementation of PSR2 selective fetch -:283: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #283: FILE: drivers/gpu/drm/i915/i915_params.c:106: +i915_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, + "Enable PSR2 selective fetch " total: 0 errors, 0 warnings, 1 checks, 220 lines checked 07be6a858e0a drm/i915/display: Implement WA 1408330847 From patchwork at emeril.freedesktop.org Tue Jun 30 17:56:53 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 17:56:53 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3Igc2Vy?= =?utf-8?q?ies_starting_with_=5Bv2=2C1/5=5D_drm/i915=3A_Add_plane_damage_c?= =?utf-8?q?lips_property_=28rev2=29?= In-Reply-To: <20200626010151.221388-1-jose.souza@intel.com> References: <20200626010151.221388-1-jose.souza@intel.com> Message-ID: <159353981304.22702.17957570708036600206@emeril.freedesktop.org> == Series Details == Series: series starting with [v2,1/5] drm/i915: Add plane damage clips property (rev2) URL : https://patchwork.freedesktop.org/series/78830/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678 -> Patchwork_18047 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/index.html Known issues ------------ Here are the changes found in Patchwork_18047 that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_suspend@basic-s0: - fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-tgl-u2/igt at gem_exec_suspend@basic-s0.html * igt at i915_module_load@reload: - fi-tgl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-u2/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-tgl-u2/igt at i915_module_load@reload.html #### Possible fixes #### * igt at i915_pm_rpm@basic-pci-d3-state: - {fi-tgl-dsi}: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-tgl-dsi/igt at i915_pm_rpm@basic-pci-d3-state.html - fi-bsw-kefka: [DMESG-WARN][7] ([i915#1982]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-bsw-kefka/igt at i915_pm_rpm@basic-pci-d3-state.html * igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - {fi-kbl-7560u}: [DMESG-WARN][9] ([i915#1982]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-kbl-7560u/igt at kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt at kms_cursor_legacy@basic-flip-before-cursor-atomic: - fi-icl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-icl-u2/igt at kms_cursor_legacy@basic-flip-before-cursor-atomic.html #### Warnings #### * igt at gem_exec_suspend@basic-s0: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-kbl-x1275/igt at gem_exec_suspend@basic-s0.html * igt at i915_pm_rpm@module-reload: - fi-kbl-x1275: [SKIP][15] ([fdo#109271]) -> [DMESG-FAIL][16] ([i915#62] / [i915#95]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-kbl-x1275/igt at i915_pm_rpm@module-reload.html * igt at kms_force_connector_basic@force-edid: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/fi-kbl-x1275/igt at kms_force_connector_basic@force-edid.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (44 -> 36) ------------------------------ Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-icl-dsi fi-bdw-samus Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18047 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18047: 07be6a858e0a1a1b81f415c8be0867d062b7fa4d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 07be6a858e0a drm/i915/display: Implement WA 1408330847 e320b2f92dfb drm/i915: Initial implementation of PSR2 selective fetch 8c1795e3dca7 drm/i915: Add PSR2 selective fetch registers 7f207be6dc9f drm/i915: Reorder intel_psr2_config_valid() fea9da6ff306 drm/i915: Add plane damage clips property == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18047/index.html From patchwork at emeril.freedesktop.org Tue Jun 30 19:08:39 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 19:08:39 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/hdcp=3A_Update_CP_as_per_the_kernel_internal_state_=28rev?= =?utf-8?q?5=29?= In-Reply-To: <20200630082048.22308-1-anshuman.gupta@intel.com> References: <20200630082048.22308-1-anshuman.gupta@intel.com> Message-ID: <159354411926.22704.14846776609744125270@emeril.freedesktop.org> == Series Details == Series: drm/i915/hdcp: Update CP as per the kernel internal state (rev5) URL : https://patchwork.freedesktop.org/series/72251/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18042_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18042_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_balancer@nop: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#1635] / [i915#95]) +15 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl2/igt at gem_exec_balancer@nop.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-apl4/igt at gem_exec_balancer@nop.html * igt at kms_addfb_basic@invalid-set-prop: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt at kms_addfb_basic@invalid-set-prop.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-tglb3/igt at kms_addfb_basic@invalid-set-prop.html * igt at kms_big_fb@linear-32bpp-rotate-180: - shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +11 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_big_fb@linear-32bpp-rotate-180.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl10/igt at kms_big_fb@linear-32bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@2x-flip-vs-rmfb-interruptible at ab-vga1-hdmi-a1: - shard-hsw: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw4/igt at kms_flip@2x-flip-vs-rmfb-interruptible at ab-vga1-hdmi-a1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-hsw6/igt at kms_flip@2x-flip-vs-rmfb-interruptible at ab-vga1-hdmi-a1.html * igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1928]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl9/igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl2/igt at kms_flip@flip-vs-absolute-wf_vblank at b-edp1.html * igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb8/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-tglb2/igt at kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#1188]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl3/igt at kms_hdr@bpc-switch.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl4/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_plane_scaling@pipe-c-scaler-with-clipping-clamping: - shard-iclb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb4/igt at kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb3/igt at kms_plane_scaling@pipe-c-scaler-with-clipping-clamping.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][23] -> [DMESG-FAIL][24] ([i915#95]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_prime@basic-crc at second-to-first.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl1/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_primary_mmap_gtt: - shard-tglb: [PASS][25] -> [SKIP][26] ([i915#668]) +5 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb3/igt at kms_psr@psr2_primary_mmap_gtt.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-tglb5/igt at kms_psr@psr2_primary_mmap_gtt.html - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb2/igt at kms_psr@psr2_primary_mmap_gtt.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb7/igt at kms_psr@psr2_primary_mmap_gtt.html * igt at kms_vblank@pipe-b-query-idle-hang: - shard-apl: [PASS][29] -> [DMESG-WARN][30] ([i915#1982]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl4/igt at kms_vblank@pipe-b-query-idle-hang.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-apl2/igt at kms_vblank@pipe-b-query-idle-hang.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][31] -> [FAIL][32] ([i915#1542]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb4/igt at perf@blocking-parameterized.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb8/igt at perf@blocking-parameterized.html - shard-tglb: [PASS][33] -> [FAIL][34] ([i915#1542]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb5/igt at perf@blocking-parameterized.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-tglb7/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_exec_balancer@bonded-slice: - shard-iclb: [INCOMPLETE][35] -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at gem_exec_balancer@bonded-slice.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb5/igt at gem_exec_balancer@bonded-slice.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk3/igt at gem_exec_whisper@basic-contexts-priority-all.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-glk4/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_mmap_offset@bad-flags: - shard-kbl: [DMESG-WARN][39] ([i915#93] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at gem_mmap_offset@bad-flags.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl7/igt at gem_mmap_offset@bad-flags.html * igt at i915_pm_rpm@modeset-non-lpsp: - shard-apl: [DMESG-WARN][41] ([i915#1635] / [i915#95]) -> [PASS][42] +14 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt at i915_pm_rpm@modeset-non-lpsp.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-apl3/igt at i915_pm_rpm@modeset-non-lpsp.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-green-to-red: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +10 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_color@pipe-c-ctm-green-to-red.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl3/igt at kms_color@pipe-c-ctm-green-to-red.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][47] ([i915#300]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl10/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1: - shard-glk: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-glk3/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl10/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [FAIL][53] ([i915#46]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl3/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@flip-vs-suspend at c-dp1: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +8 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl3/igt at kms_flip@flip-vs-suspend at c-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl4/igt at kms_flip@flip-vs-suspend at c-dp1.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl2/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack: - shard-tglb: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-tglb6/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][61] ([i915#1188]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl6/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][63] ([CI#80] / [i915#69]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-glk: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-glk1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][67] ([i915#69]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min: - shard-skl: [FAIL][69] ([fdo#108145] / [i915#265]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl1/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-skl5/igt at kms_plane_alpha_blend@pipe-b-constant-alpha-min.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][71] ([i915#1982]) -> [PASS][72] +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb4/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][73] ([i915#173]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at kms_psr@no_drrs.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb5/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb3/igt at kms_psr@psr2_sprite_mmap_gtt.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb2/igt at kms_psr@psr2_sprite_mmap_gtt.html * igt at perf@polling-parameterized: - shard-iclb: [FAIL][77] ([i915#1542]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb6/igt at perf@polling-parameterized.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-iclb8/igt at perf@polling-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-spin-others at vcs0: - shard-snb: [WARN][79] ([i915#2021]) -> [WARN][80] ([i915#2036]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt at gem_exec_reloc@basic-spin-others at vcs0.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-snb2/igt at gem_exec_reloc@basic-spin-others at vcs0.html * igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs: - shard-apl: [SKIP][81] ([fdo#109271]) -> [SKIP][82] ([fdo#109271] / [i915#1635]) +8 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl2/igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-apl4/igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][83] ([i915#1319]) -> [TIMEOUT][84] ([i915#1319] / [i915#1958]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_content_protection@srm.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl1/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][85] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][86] ([i915#93] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-1p-rte: - shard-apl: [SKIP][87] ([fdo#109271] / [i915#1635]) -> [SKIP][88] ([fdo#109271]) +5 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_frontbuffer_tracking@psr-1p-rte.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/shard-apl6/igt at kms_frontbuffer_tracking@psr-1p-rte.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18042 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18042: b97d79fa049ee3f3da673cd51616695c69da60c2 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18042/index.html From michael.j.ruhl at intel.com Tue Jun 30 19:11:16 2020 From: michael.j.ruhl at intel.com (Ruhl, Michael J) Date: Tue, 30 Jun 2020 19:11:16 +0000 Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its own lock In-Reply-To: <20200629113616.10618-1-chris@chris-wilson.co.uk> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> <20200629113616.10618-1-chris@chris-wilson.co.uk> Message-ID: <14063C7AD467DE4B82DEDB5C278E8663011D9A4FBB@FMSMSX108.amr.corp.intel.com> >-----Original Message----- >From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Chris >Wilson >Sent: Monday, June 29, 2020 7:36 AM >To: intel-gfx at lists.freedesktop.org >Cc: Chris Wilson <chris at chris-wilson.co.uk> >Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its >own lock > >The obj->lut_list is traversed when the object is closed as the file >table is destroyed during process termination. As this occurs before we >kill any outstanding context if, due to some bug or another, the closure >is blocked, then we fail to shootdown any inflight operations >potentially leaving the GPU spinning forever. As we only need to guard >the list against concurrent closures and insertions, the hold is short >and merits being treated as a simple spinlock. The comment: /* Break long locks, and carefully continue on from this spot */ seems to be contrary to your "the hold is short" comment. Is calling out this apparent worst case scenario (i.e. how it could happen), worth documenting? >Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> >--- > drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++---- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++-- > drivers/gpu/drm/i915/gem/i915_gem_object.c | 21 +++++++++++++------ > .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 + > 4 files changed, 20 insertions(+), 12 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c >b/drivers/gpu/drm/i915/gem/i915_gem_context.c >index 5c13809dc3c8..6675447a47b9 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c >@@ -112,8 +112,7 @@ static void lut_close(struct i915_gem_context *ctx) > if (!kref_get_unless_zero(&obj->base.refcount)) > continue; > >- rcu_read_unlock(); >- i915_gem_object_lock(obj); >+ spin_lock(&obj->lut_lock); > list_for_each_entry(lut, &obj->lut_list, obj_link) { > if (lut->ctx != ctx) > continue; >@@ -124,8 +123,7 @@ static void lut_close(struct i915_gem_context *ctx) > list_del(&lut->obj_link); > break; > } >- i915_gem_object_unlock(obj); >- rcu_read_lock(); >+ spin_unlock(&obj->lut_lock); > > if (&lut->obj_link != &obj->lut_list) { > i915_lut_handle_free(lut); >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >index c38ab51e82f0..b4862afaaf28 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c >@@ -789,14 +789,14 @@ static int __eb_add_lut(struct i915_execbuffer *eb, > if (err == 0) { /* And nor has this handle */ > struct drm_i915_gem_object *obj = vma->obj; > >- i915_gem_object_lock(obj); >+ spin_lock(&obj->lut_lock); > if (idr_find(&eb->file->object_idr, handle) == obj) { > list_add(&lut->obj_link, &obj->lut_list); > } else { > radix_tree_delete(&ctx->handles_vma, >handle); > err = -ENOENT; > } >- i915_gem_object_unlock(obj); >+ spin_unlock(&obj->lut_lock); > } > mutex_unlock(&ctx->mutex); > } >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c >b/drivers/gpu/drm/i915/gem/i915_gem_object.c >index b6ec5b50d93b..6b69191c5543 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c >@@ -61,6 +61,7 @@ void i915_gem_object_init(struct drm_i915_gem_object >*obj, > INIT_LIST_HEAD(&obj->mm.link); > > INIT_LIST_HEAD(&obj->lut_list); >+ spin_lock_init(&obj->lut_lock); > > spin_lock_init(&obj->mmo.lock); > obj->mmo.offsets = RB_ROOT; >@@ -104,21 +105,29 @@ void i915_gem_close_object(struct >drm_gem_object *gem, struct drm_file *file) > { > struct drm_i915_gem_object *obj = to_intel_bo(gem); > struct drm_i915_file_private *fpriv = file->driver_priv; >+ struct i915_lut_handle bookmark = {}; > struct i915_mmap_offset *mmo, *mn; > struct i915_lut_handle *lut, *ln; > LIST_HEAD(close); > >- i915_gem_object_lock(obj); >+ spin_lock(&obj->lut_lock); > list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { > struct i915_gem_context *ctx = lut->ctx; > >- if (ctx->file_priv != fpriv) >- continue; >+ if (ctx && ctx->file_priv == fpriv) { Null checking ctx was not done before. I think this changed with the possible cond_resched? Or is this just being extra cautious? Thanks, Mike >+ i915_gem_context_get(ctx); >+ list_move(&lut->obj_link, &close); >+ } > >- i915_gem_context_get(ctx); >- list_move(&lut->obj_link, &close); >+ /* Break long locks, and carefully continue on from this spot */ >+ if (&ln->obj_link != &obj->lut_list) { >+ list_add_tail(&bookmark.obj_link, &ln->obj_link); >+ if (cond_resched_lock(&obj->lut_lock)) >+ list_safe_reset_next(&bookmark, ln, >obj_link); >+ __list_del_entry(&bookmark.obj_link); >+ } > } >- i915_gem_object_unlock(obj); >+ spin_unlock(&obj->lut_lock); > > spin_lock(&obj->mmo.lock); > rbtree_postorder_for_each_entry_safe(mmo, mn, &obj- >>mmo.offsets, offset) >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >index b1f82a11aef2..5335f799b548 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h >@@ -121,6 +121,7 @@ struct drm_i915_gem_object { > * this translation from object to context->handles_vma. > */ > struct list_head lut_list; >+ spinlock_t lut_lock; /* guards lut_list */ > > /** Stolen memory for this object, instead of being backed by >shmem. */ > struct drm_mm_node *stolen; >-- >2.20.1 > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx at lists.freedesktop.org >https://lists.freedesktop.org/mailman/listinfo/intel-gfx From chris at chris-wilson.co.uk Tue Jun 30 19:28:32 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 20:28:32 +0100 Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its own lock In-Reply-To: <14063C7AD467DE4B82DEDB5C278E8663011D9A4FBB@FMSMSX108.amr.corp.intel.com> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> <20200629113616.10618-1-chris@chris-wilson.co.uk> <14063C7AD467DE4B82DEDB5C278E8663011D9A4FBB@FMSMSX108.amr.corp.intel.com> Message-ID: <159354531220.22902.2935750807524355172@build.alporthouse.com> Quoting Ruhl, Michael J (2020-06-30 20:11:16) > >-----Original Message----- > >From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Chris > >Wilson > >Sent: Monday, June 29, 2020 7:36 AM > >To: intel-gfx at lists.freedesktop.org > >Cc: Chris Wilson <chris at chris-wilson.co.uk> > >Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its > >own lock > > > >The obj->lut_list is traversed when the object is closed as the file > >table is destroyed during process termination. As this occurs before we > >kill any outstanding context if, due to some bug or another, the closure > >is blocked, then we fail to shootdown any inflight operations > >potentially leaving the GPU spinning forever. As we only need to guard > >the list against concurrent closures and insertions, the hold is short > >and merits being treated as a simple spinlock. > > The comment: > > /* Break long locks, and carefully continue on from this spot */ > > seems to be contrary to your "the hold is short" comment. Is calling out > this apparent worst case scenario (i.e. how it could happen), worth > documenting? It's paranoia, because list iterating can be slow and historically slow object closure has been reported as an issue. Only a few objects will be shared between multiple contexts, and even then you would only expect a couple of contexts to share an object. One of the OglDrvCtx would show up here, which convinced us to move to the per-object lists to shrink the number of elements walked. Even the close race igts do not cause the list to become long enough to schedule, but it would be possible to create an object that was shared by 64k contexts. Just not wise in practice. [However, I should make sure an igt does hit the bookmark.] > >@@ -104,21 +105,29 @@ void i915_gem_close_object(struct > >drm_gem_object *gem, struct drm_file *file) > > { > > struct drm_i915_gem_object *obj = to_intel_bo(gem); > > struct drm_i915_file_private *fpriv = file->driver_priv; > >+ struct i915_lut_handle bookmark = {}; > > struct i915_mmap_offset *mmo, *mn; > > struct i915_lut_handle *lut, *ln; > > LIST_HEAD(close); > > > >- i915_gem_object_lock(obj); > >+ spin_lock(&obj->lut_lock); > > list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { > > struct i915_gem_context *ctx = lut->ctx; > > > >- if (ctx->file_priv != fpriv) > >- continue; > >+ if (ctx && ctx->file_priv == fpriv) { > > Null checking ctx was not done before. I think this changed with the possible cond_resched? The bookmark introduces the lut->ctx == NULL to identify it as being special, hence the need to check. -Chris From michael.j.ruhl at intel.com Tue Jun 30 20:01:51 2020 From: michael.j.ruhl at intel.com (Ruhl, Michael J) Date: Tue, 30 Jun 2020 20:01:51 +0000 Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its own lock In-Reply-To: <159354531220.22902.2935750807524355172@build.alporthouse.com> References: <20200629101256.13039-1-chris@chris-wilson.co.uk> <20200629113616.10618-1-chris@chris-wilson.co.uk> <14063C7AD467DE4B82DEDB5C278E8663011D9A4FBB@FMSMSX108.amr.corp.intel.com> <159354531220.22902.2935750807524355172@build.alporthouse.com> Message-ID: <14063C7AD467DE4B82DEDB5C278E8663011D9A52AC@FMSMSX108.amr.corp.intel.com> >-----Original Message----- >From: Chris Wilson <chris at chris-wilson.co.uk> >Sent: Tuesday, June 30, 2020 3:29 PM >To: Ruhl, Michael J <michael.j.ruhl at intel.com>; intel- >gfx at lists.freedesktop.org >Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under >its own lock > >Quoting Ruhl, Michael J (2020-06-30 20:11:16) >> >-----Original Message----- >> >From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of >Chris >> >Wilson >> >Sent: Monday, June 29, 2020 7:36 AM >> >To: intel-gfx at lists.freedesktop.org >> >Cc: Chris Wilson <chris at chris-wilson.co.uk> >> >Subject: [Intel-gfx] [PATCH v2] drm/i915/gem: Move obj->lut_list under its >> >own lock >> > >> >The obj->lut_list is traversed when the object is closed as the file >> >table is destroyed during process termination. As this occurs before we >> >kill any outstanding context if, due to some bug or another, the closure >> >is blocked, then we fail to shootdown any inflight operations >> >potentially leaving the GPU spinning forever. As we only need to guard >> >the list against concurrent closures and insertions, the hold is short >> >and merits being treated as a simple spinlock. >> >> The comment: >> >> /* Break long locks, and carefully continue on from this spot */ >> >> seems to be contrary to your "the hold is short" comment. Is calling out >> this apparent worst case scenario (i.e. how it could happen), worth >> documenting? > >It's paranoia, because list iterating can be slow and historically slow >object closure has been reported as an issue. Only a few objects will be >shared between multiple contexts, and even then you would only expect a >couple of contexts to share an object. One of the OglDrvCtx would show up >here, which convinced us to move to the per-object lists to shrink the >number of elements walked. > >Even the close race igts do not cause the list to become long enough to >schedule, but it would be possible to create an object that was shared >by 64k contexts. Just not wise in practice. [However, I should make sure >an igt does hit the bookmark.] I look forward to that igt. ? > >> >@@ -104,21 +105,29 @@ void i915_gem_close_object(struct >> >drm_gem_object *gem, struct drm_file *file) >> > { >> > struct drm_i915_gem_object *obj = to_intel_bo(gem); >> > struct drm_i915_file_private *fpriv = file->driver_priv; >> >+ struct i915_lut_handle bookmark = {}; >> > struct i915_mmap_offset *mmo, *mn; >> > struct i915_lut_handle *lut, *ln; >> > LIST_HEAD(close); >> > >> >- i915_gem_object_lock(obj); >> >+ spin_lock(&obj->lut_lock); >> > list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { >> > struct i915_gem_context *ctx = lut->ctx; >> > >> >- if (ctx->file_priv != fpriv) >> >- continue; >> >+ if (ctx && ctx->file_priv == fpriv) { >> >> Null checking ctx was not done before. I think this changed with the >possible cond_resched? > >The bookmark introduces the lut->ctx == NULL to identify it as being >special, hence the need to check. Ok, clean lock replacement with a paranoid worst case scenario, just in case. Reviewed-by: Michael J. Ruhl <michael.j.ruhl at intel.com> M >-Chris From patchwork at emeril.freedesktop.org Tue Jun 30 20:20:00 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 20:20:00 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Delay_attach_mmu-notifier_until_we_acquire_the_pin?= =?utf-8?q?ned_userptr?= In-Reply-To: <20200630111421.12301-1-chris@chris-wilson.co.uk> References: <20200630111421.12301-1-chris@chris-wilson.co.uk> Message-ID: <159354840033.22704.9642527907881374049@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Delay attach mmu-notifier until we acquire the pinned userptr URL : https://patchwork.freedesktop.org/series/78938/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18043_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18043_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_nop@basic-parallel: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#1635] / [i915#95]) +24 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt at gem_exec_nop@basic-parallel.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl3/igt at gem_exec_nop@basic-parallel.html * igt at i915_selftest@perf at request: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([i915#1823]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb8/igt at i915_selftest@perf at request.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-tglb8/igt at i915_selftest@perf at request.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl7/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl8/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size: - shard-snb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-snb5/igt at kms_cursor_legacy@basic-flip-after-cursor-varying-size.html * igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl3/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html * igt at kms_flip@flip-vs-expired-vblank at c-edp1: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#46]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_flip@flip-vs-expired-vblank at c-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at c-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-modesetfrombusy: - shard-tglb: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-tglb2/igt at kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl2/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][19] -> [DMESG-FAIL][20] ([i915#95]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_prime@basic-crc at second-to-first.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl7/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-iclb3/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +5 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl1/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at perf@blocking: - shard-glk: [PASS][25] -> [DMESG-WARN][26] ([i915#118] / [i915#95]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk3/igt at perf@blocking.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-glk3/igt at perf@blocking.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][27] -> [FAIL][28] ([i915#1542]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb4/igt at perf@blocking-parameterized.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-iclb4/igt at perf@blocking-parameterized.html * igt at perf@short-reads: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#51]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at perf@short-reads.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl7/igt at perf@short-reads.html #### Possible fixes #### * igt at gem_exec_balancer@bonded-slice: - shard-iclb: [INCOMPLETE][31] -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at gem_exec_balancer@bonded-slice.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-iclb5/igt at gem_exec_balancer@bonded-slice.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][33] ([i915#1930]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-glk1/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk2/igt at gem_exec_whisper@basic-contexts-forked.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-glk1/igt at gem_exec_whisper@basic-contexts-forked.html * igt at gem_mmap_gtt@ptrace: - shard-apl: [DMESG-WARN][37] ([i915#1635] / [i915#95]) -> [PASS][38] +20 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at gem_mmap_gtt@ptrace.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl7/igt at gem_mmap_gtt@ptrace.html * igt at gem_workarounds@suspend-resume-fd: - shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +7 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at gem_workarounds@suspend-resume-fd.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl3/igt at gem_workarounds@suspend-resume-fd.html * igt at gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][41] ([i915#1436] / [i915#716]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt at gen9_exec_parse@allowed-all.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl4/igt at gen9_exec_parse@allowed-all.html * igt at i915_selftest@mock at requests: - shard-skl: [INCOMPLETE][43] ([i915#198] / [i915#2110]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl10/igt at i915_selftest@mock at requests.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl9/igt at i915_selftest@mock at requests.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-glk5/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-green-to-red: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +6 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_color@pipe-c-ctm-green-to-red.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl1/igt at kms_color@pipe-c-ctm-green-to-red.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][49] ([i915#300]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl10/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-glk2/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [FAIL][53] ([i915#79]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl7/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [FAIL][55] ([i915#46]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl1/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl1/igt at kms_flip@modeset-vs-vblank-race-interruptible at a-dp1.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][59] ([CI#80] / [i915#69]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl1/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-glk: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-glk5/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][63] ([i915#69]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-iclb6/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][67] ([i915#173]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at kms_psr@no_drrs.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-iclb5/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +3 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb6/igt at kms_psr@psr2_primary_mmap_cpu.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-iclb2/igt at kms_psr@psr2_primary_mmap_cpu.html * igt at perf@polling-parameterized: - shard-iclb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb6/igt at perf@polling-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-iclb2/igt at perf@polling-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-spin-others at vcs0: - shard-snb: [WARN][73] ([i915#2021]) -> [WARN][74] ([i915#2036]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt at gem_exec_reloc@basic-spin-others at vcs0.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-snb5/igt at gem_exec_reloc@basic-spin-others at vcs0.html * igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs: - shard-apl: [SKIP][75] ([fdo#109271]) -> [SKIP][76] ([fdo#109271] / [i915#1635]) +7 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl2/igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl1/igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html * igt at kms_color_chamelium@pipe-b-ctm-0-75: - shard-apl: [SKIP][77] ([fdo#109271] / [fdo#111827]) -> [SKIP][78] ([fdo#109271] / [fdo#111827] / [i915#1635]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_color_chamelium@pipe-b-ctm-0-75.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl7/igt at kms_color_chamelium@pipe-b-ctm-0-75.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1958]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl7/igt at kms_content_protection@srm.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][81] ([i915#93] / [i915#95]) -> [DMESG-WARN][82] ([i915#180] / [i915#93] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@psr-rgb565-draw-render: - shard-apl: [SKIP][85] ([fdo#109271] / [i915#1635]) -> [SKIP][86] ([fdo#109271]) +10 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl8/igt at kms_frontbuffer_tracking@psr-rgb565-draw-render.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl4/igt at kms_frontbuffer_tracking@psr-rgb565-draw-render.html * igt at runner@aborted: - shard-apl: ([FAIL][87], [FAIL][88]) ([fdo#109271] / [i915#1635] / [i915#716]) -> [FAIL][89] ([i915#1635]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt at runner@aborted.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl8/igt at runner@aborted.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-apl2/igt at runner@aborted.html - shard-tglb: [FAIL][90] ([i915#2110]) -> ([FAIL][91], [FAIL][92]) ([i915#1759] / [i915#2110]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb1/igt at runner@aborted.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-tglb7/igt at runner@aborted.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/shard-tglb8/igt at runner@aborted.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1823]: https://gitlab.freedesktop.org/drm/intel/issues/1823 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18043 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18043: cd98f8cb0ad0febd089b3baa38b5c3385783b6ff @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18043/index.html From manasi.d.navare at intel.com Tue Jun 30 20:27:06 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 30 Jun 2020 13:27:06 -0700 Subject: [Intel-gfx] [PATCH v1] drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K In-Reply-To: <20200630162909.GR6112@intel.com> References: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> <20200630162909.GR6112@intel.com> Message-ID: <20200630202706.GA20459@intel.com> On Tue, Jun 30, 2020 at 07:29:09PM +0300, Ville Syrj?l? wrote: > On Tue, Jun 30, 2020 at 02:26:09PM +0300, Stanislav Lisovskiy wrote: > > We still need "Bump up CDCLK" workaround otherwise getting > > underruns - however currently it blocks 8K as CDCLK = Pixel rate, > > in 8K case would require CDCLK to be around 1 Ghz which is not > > possible. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 14 +++++++++++++- > > 1 file changed, 13 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index 45f7f33d1144..01a5bc6b08c4 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -2080,9 +2080,21 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > > * Explicitly stating here that this seems to be currently > > * rather a Hack, than final solution. > > */ > > - if (IS_TIGERLAKE(dev_priv)) > > + if (IS_TIGERLAKE(dev_priv)) { > > min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); > > > > + /* > > + * Clamp to max_cdclk_freq in order not to break an 8K, > > + * but still leave W/A at place. > > + */ > > + min_cdclk = min(min_cdclk, (int)dev_priv->max_cdclk_freq); > > + > > + /* > > + * max_cdclk_freq check obviously not needed - just return. > > + */ > > + return min_cdclk; > > Pointless return. But I think we should actually keep the max_cdclk > check. Something like: > > min_cdclk = max(min_cdclk, > min(max_cdclk, pixel_rate)); > > Also what's with the (int) casts? There is min_t() if you > actually need casts. But not sure why we need them though. Yes this logic suggested by Ville bumps up the min cdclock to either the pixel rate or max cdclk freq whichever is the min so we dont run into cdcclk not sufficient error for 8K since the 8K (3840 x 4320 1 tile) would need ~ 1066Mhz pixel rate. Changing to this logic, you can count my r-b Manasi > > > + } > > + > > if (min_cdclk > dev_priv->max_cdclk_freq) { > > drm_dbg_kms(&dev_priv->drm, > > "required cdclk (%d kHz) exceeds max (%d kHz)\n", > > -- > > 2.24.1.485.gad05a3d8e5 > > -- > Ville Syrj?l? > Intel From manasi.d.navare at intel.com Tue Jun 30 20:49:22 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 30 Jun 2020 13:49:22 -0700 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200630153016.GK6112@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> <20200630153016.GK6112@intel.com> Message-ID: <20200630204922.GB20459@intel.com> On Tue, Jun 30, 2020 at 06:30:16PM +0300, Ville Syrj?l? wrote: > On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote: > > Modify the helper to add a fixed delay or poll with timeout > > based on platform specification to check for either Idle bit > > set (DDI_BUF_CTL is idle for disable case) > > > > v3: > > * Change the timeout to 16usecs (Ville) > > v2: > > * Use 2 separate functions or idle and active (Ville) > > Missing changelog? Did somehting change? > No its a v3 for thsi patch, but patch 2/2 is a v4 so published both patches with a v4, does this now look good with v3, timeout changed to 16 usecs? Manasi > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > > 1 file changed, 8 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 884b507c5f55..052a74625a61 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > enum port port) > > { > > - i915_reg_t reg = DDI_BUF_CTL(port); > > - int i; > > - > > - for (i = 0; i < 16; i++) { > > - udelay(1); > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > - return; > > + if (IS_BROXTON(dev_priv)) { > > + udelay(16); > > + return; > > } > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > - port_name(port)); > > + > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 16)) > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > > + port_name(port)); > > } > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From ville.syrjala at linux.intel.com Tue Jun 30 21:00:07 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 1 Jul 2020 00:00:07 +0300 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200630204922.GB20459@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> <20200630153016.GK6112@intel.com> <20200630204922.GB20459@intel.com> Message-ID: <20200630210007.GT6112@intel.com> On Tue, Jun 30, 2020 at 01:49:22PM -0700, Manasi Navare wrote: > On Tue, Jun 30, 2020 at 06:30:16PM +0300, Ville Syrj?l? wrote: > > On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote: > > > Modify the helper to add a fixed delay or poll with timeout > > > based on platform specification to check for either Idle bit > > > set (DDI_BUF_CTL is idle for disable case) > > > > > > v3: > > > * Change the timeout to 16usecs (Ville) > > > v2: > > > * Use 2 separate functions or idle and active (Ville) > > > > Missing changelog? Did somehting change? > > > > No its a v3 for thsi patch, but patch 2/2 is a v4 so published > both patches with a v4, Doh. The changelog is backwards so didn't even notice. > > does this now look good with v3, timeout changed to 16 usecs? > > Manasi > > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > > > 1 file changed, 8 insertions(+), 9 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 884b507c5f55..052a74625a61 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > > enum port port) > > > { > > > - i915_reg_t reg = DDI_BUF_CTL(port); > > > - int i; > > > - > > > - for (i = 0; i < 16; i++) { > > > - udelay(1); > > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > > - return; > > > + if (IS_BROXTON(dev_priv)) { > > > + udelay(16); > > > + return; > > > } > > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > - port_name(port)); > > > + > > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), 16)) > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > > > + port_name(port)); > > > } > > > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > > -- > > > 2.19.1 > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From ville.syrjala at linux.intel.com Tue Jun 30 21:03:30 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 1 Jul 2020 00:03:30 +0300 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200626232641.4557-1-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> Message-ID: <20200630210330.GU6112@intel.com> On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote: > Modify the helper to add a fixed delay or poll with timeout > based on platform specification to check for either Idle bit > set (DDI_BUF_CTL is idle for disable case) > > v3: > * Change the timeout to 16usecs (Ville) > v2: > * Use 2 separate functions or idle and active (Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > 1 file changed, 8 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 884b507c5f55..052a74625a61 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > enum port port) > { > - i915_reg_t reg = DDI_BUF_CTL(port); > - int i; > - > - for (i = 0; i < 16; i++) { > - udelay(1); > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > - return; > + if (IS_BROXTON(dev_priv)) { > + udelay(16); > + return; > } > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > - port_name(port)); > + > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 16)) 16 is the BXT number. IIRC the spec said 8 usec for the other platforms. > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > + port_name(port)); > } > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > -- > 2.19.1 -- Ville Syrj?l? Intel From manasi.d.navare at intel.com Tue Jun 30 21:10:45 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 30 Jun 2020 14:10:45 -0700 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200630210330.GU6112@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> <20200630210330.GU6112@intel.com> Message-ID: <20200630211045.GA21520@intel.com> On Wed, Jul 01, 2020 at 12:03:30AM +0300, Ville Syrj?l? wrote: > On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote: > > Modify the helper to add a fixed delay or poll with timeout > > based on platform specification to check for either Idle bit > > set (DDI_BUF_CTL is idle for disable case) > > > > v3: > > * Change the timeout to 16usecs (Ville) > > v2: > > * Use 2 separate functions or idle and active (Ville) > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > > 1 file changed, 8 insertions(+), 9 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 884b507c5f55..052a74625a61 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > enum port port) > > { > > - i915_reg_t reg = DDI_BUF_CTL(port); > > - int i; > > - > > - for (i = 0; i < 16; i++) { > > - udelay(1); > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > - return; > > + if (IS_BROXTON(dev_priv)) { > > + udelay(16); > > + return; > > } > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > - port_name(port)); > > + > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 16)) > > 16 is the BXT number. IIRC the spec said 8 usec for the other platforms. > Yes I see for HSW atleast yes it says 8usecs but i left it at 16 since thats what we always had and the only change was that BXT add a fixed delay But if you prefer i will change it to 8us timeout? Manasi > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > > + port_name(port)); > > } > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Tue Jun 30 21:17:45 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 21:17:45 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Clamp_min=5Fcdclk_to_max=5Fcdclk=5Ffreq_to_unblock_8K?= In-Reply-To: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> References: <20200630112609.9998-1-stanislav.lisovskiy@intel.com> Message-ID: <159355186571.22704.14377345365288523314@emeril.freedesktop.org> == Series Details == Series: drm/i915: Clamp min_cdclk to max_cdclk_freq to unblock 8K URL : https://patchwork.freedesktop.org/series/78940/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18044_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18044_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_whisper@basic-fds-priority-all: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([i915#118] / [i915#95]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk9/igt at gem_exec_whisper@basic-fds-priority-all.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk4/igt at gem_exec_whisper@basic-fds-priority-all.html * igt at i915_module_load@reload: - shard-tglb: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb3/igt at i915_module_load@reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-tglb6/igt at i915_module_load@reload.html * igt at kms_addfb_basic@addfb25-modifier-no-flag: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#1635] / [i915#95]) +11 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_addfb_basic@addfb25-modifier-no-flag.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl4/igt at kms_addfb_basic@addfb25-modifier-no-flag.html * igt at kms_big_fb@x-tiled-64bpp-rotate-0: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk3/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-0.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#93] / [i915#95]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-kbl3/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +15 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl7/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl9/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled: - shard-snb: [PASS][15] -> [SKIP][16] ([fdo#109271]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt at kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-snb4/igt at kms_draw_crc@draw-method-xrgb8888-mmap-cpu-untiled.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1: - shard-skl: [PASS][17] -> [FAIL][18] ([i915#46]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-edp1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#79]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk3/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a2.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#79]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-tiling-y: - shard-tglb: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +2 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb5/igt at kms_frontbuffer_tracking@fbcpsr-tiling-y.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-tiling-y.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl7/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][27] -> [DMESG-FAIL][28] ([i915#95]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_prime@basic-crc at second-to-first.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-kbl4/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109441]) +2 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-iclb8/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-b-wait-forked-hang: - shard-apl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl7/igt at kms_vblank@pipe-b-wait-forked-hang.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl6/igt at kms_vblank@pipe-b-wait-forked-hang.html * igt at perf@blocking-parameterized: - shard-tglb: [PASS][33] -> [FAIL][34] ([i915#1542]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb5/igt at perf@blocking-parameterized.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-tglb1/igt at perf@blocking-parameterized.html #### Possible fixes #### * igt at gem_exec_balancer@bonded-slice: - shard-iclb: [INCOMPLETE][35] -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at gem_exec_balancer@bonded-slice.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-iclb6/igt at gem_exec_balancer@bonded-slice.html * igt at gem_exec_reloc@basic-concurrent0: - shard-glk: [FAIL][37] ([i915#1930]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at gem_exec_reloc@basic-concurrent0.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk2/igt at gem_exec_reloc@basic-concurrent0.html * igt at gem_exec_whisper@basic-contexts-priority-all: - shard-glk: [DMESG-WARN][39] ([i915#118] / [i915#95]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk3/igt at gem_exec_whisper@basic-contexts-priority-all.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk8/igt at gem_exec_whisper@basic-contexts-priority-all.html * igt at gem_mmap_gtt@ptrace: - shard-apl: [DMESG-WARN][41] ([i915#1635] / [i915#95]) -> [PASS][42] +8 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at gem_mmap_gtt@ptrace.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl1/igt at gem_mmap_gtt@ptrace.html * igt at gen9_exec_parse@allowed-all: - shard-apl: [DMESG-WARN][43] ([i915#1436] / [i915#716]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt at gen9_exec_parse@allowed-all.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl3/igt at gen9_exec_parse@allowed-all.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][45] ([i915#118] / [i915#95]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk7/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-green-to-red: - shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +8 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_color@pipe-c-ctm-green-to-red.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl10/igt at kms_color@pipe-c-ctm-green-to-red.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][49] ([i915#300]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl5/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1: - shard-glk: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk3/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [FAIL][53] ([i915#46]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl10/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +7 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-kbl1/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_flip@flip-vs-suspend at c-hdmi-a1: - shard-hsw: [INCOMPLETE][57] ([i915#2055]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-hsw1/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-hsw1/igt at kms_flip@flip-vs-suspend at c-hdmi-a1.html * igt at kms_hdr@bpc-switch-suspend: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl2/igt at kms_hdr@bpc-switch-suspend.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][61] ([CI#80] / [i915#69]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-glk: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-glk7/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][65] ([i915#69]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-skl1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-iclb4/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][69] ([fdo#109642] / [fdo#111068]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb7/igt at kms_psr2_su@frontbuffer.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][71] ([i915#173]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at kms_psr@no_drrs.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-iclb6/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_blt: - shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb8/igt at kms_psr@psr2_primary_blt.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-iclb2/igt at kms_psr@psr2_primary_blt.html * igt at perf@polling-parameterized: - shard-iclb: [FAIL][75] ([i915#1542]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb6/igt at perf@polling-parameterized.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-iclb1/igt at perf@polling-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-spin-others at vcs0: - shard-snb: [WARN][77] ([i915#2021]) -> [WARN][78] ([i915#2036]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt at gem_exec_reloc@basic-spin-others at vcs0.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-snb6/igt at gem_exec_reloc@basic-spin-others at vcs0.html * igt at kms_color_chamelium@pipe-b-ctm-0-75: - shard-apl: [SKIP][79] ([fdo#109271] / [fdo#111827]) -> [SKIP][80] ([fdo#109271] / [fdo#111827] / [i915#1635]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_color_chamelium@pipe-b-ctm-0-75.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl1/igt at kms_color_chamelium@pipe-b-ctm-0-75.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][81] ([i915#1319]) -> [TIMEOUT][82] ([i915#1319] / [i915#1958]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_content_protection@srm.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-kbl4/igt at kms_content_protection@srm.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][84] ([i915#93] / [i915#95]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-kbl3/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-apl: [SKIP][85] ([fdo#109271]) -> [SKIP][86] ([fdo#109271] / [i915#1635]) +2 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl1/igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@psr-1p-rte: - shard-apl: [SKIP][87] ([fdo#109271] / [i915#1635]) -> [SKIP][88] ([fdo#109271]) +3 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_frontbuffer_tracking@psr-1p-rte.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl1/igt at kms_frontbuffer_tracking@psr-1p-rte.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [DMESG-WARN][89] ([i915#93] / [i915#95]) -> [DMESG-WARN][90] ([i915#180] / [i915#93] / [i915#95]) [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-kbl6/igt at kms_hdr@bpc-switch-suspend.html * igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - shard-apl: [DMESG-FAIL][91] ([fdo#108145] / [i915#1635] / [i915#95]) -> [DMESG-FAIL][92] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html * igt at runner@aborted: - shard-apl: ([FAIL][93], [FAIL][94]) ([fdo#109271] / [i915#1635] / [i915#716]) -> [FAIL][95] ([i915#1635]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt at runner@aborted.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl8/igt at runner@aborted.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/shard-apl2/igt at runner@aborted.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18044 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18044: abfcf6db3529c248344aaeb3e113cec6eadcd592 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18044/index.html From ville.syrjala at linux.intel.com Tue Jun 30 21:20:26 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 1 Jul 2020 00:20:26 +0300 Subject: [Intel-gfx] [PATCH v4 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200626232641.4557-2-manasi.d.navare@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> <20200626232641.4557-2-manasi.d.navare@intel.com> Message-ID: <20200630212026.GV6112@intel.com> On Fri, Jun 26, 2020 at 04:26:41PM -0700, Manasi Navare wrote: > Based on the platform, Bspec expects us to wait or poll with > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > after enabling DDI_BUF_CTL. > > v4: > * Use the timeout for GLK (Ville) > v3: > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > v2: > * Based on platform, fixed delay or poll (Ville) > * Use a helper to do this (Imre, Ville) > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > Cc: Imre Deak <imre.deak at intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 052a74625a61..94d57b57139b 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > port_name(port)); > } > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > + enum port port) > +{ > + if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv) ) { > + usleep_range(600, 1000); I would probably put a spec quote here to make it clear what this is: "Wait >518 us for buffers to enable..." Or we could s/600/518/ to make it easier to figure out. But that could be a followup. > + return; > + } > + > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > + DDI_BUF_IS_IDLE), 600)) Spec says 500 usec for this. Is there a reason to not go with the spec value? I guess one argument is that we didn't do it before. But I'd probably change it, if not in this patch then as a followup. > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > + port_name(port)); > +} > + > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > { > switch (pll->info->id) { > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > - udelay(600); > + intel_wait_ddi_buf_active(dev_priv, port); Still can't see fdi anywhere. Whatever Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > } > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > -- > 2.19.1 -- Ville Syrj?l? Intel From chris at chris-wilson.co.uk Tue Jun 30 21:25:15 2020 From: chris at chris-wilson.co.uk (Chris Wilson) Date: Tue, 30 Jun 2020 22:25:15 +0100 Subject: [Intel-gfx] [PATCH i-g-t] i915/gem_close_race: Mix in a contexts and a small delay to closure Message-ID: <20200630212515.1132791-1-chris@chris-wilson.co.uk> Keep the old handles in a small ring so that we build up a small amount of pressure for i915_gem_close_object() and throw in a few concurrent contexts so we have to process an obj->lut_list containing more than one element. And to make sure the list is truly long enough to schedule, start leaking the contexts. Note that the only correctness check is that the selfcopy doesn't explode; the challenge would be to prove that the old handles are no longer accessible via the execbuf lut. However, this is sufficient to make sure we at least hit the interruptible spinlock used by close-objects. Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com> --- tests/i915/gem_close_race.c | 68 +++++++++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 15 deletions(-) diff --git a/tests/i915/gem_close_race.c b/tests/i915/gem_close_race.c index db570e8fd..4b72d353c 100644 --- a/tests/i915/gem_close_race.c +++ b/tests/i915/gem_close_race.c @@ -55,7 +55,7 @@ static bool has_64bit_relocations; #define sigev_notify_thread_id _sigev_un._tid -static void selfcopy(int fd, uint32_t handle, int loops) +static void selfcopy(int fd, uint32_t ctx, uint32_t handle, int loops) { struct drm_i915_gem_relocation_entry reloc[2]; struct drm_i915_gem_exec_object2 gem_exec[2]; @@ -113,6 +113,7 @@ static void selfcopy(int fd, uint32_t handle, int loops) execbuf.batch_len = (b - buf) * sizeof(*b); if (HAS_BLT_RING(devid)) execbuf.flags |= I915_EXEC_BLT; + execbuf.rsvd1 = ctx; memset(&gem_pwrite, 0, sizeof(gem_pwrite)); gem_pwrite.handle = create.handle; @@ -135,7 +136,7 @@ static uint32_t load(int fd) if (handle == 0) return 0; - selfcopy(fd, handle, 100); + selfcopy(fd, 0, handle, 100); return handle; } @@ -165,14 +166,19 @@ static void crashme_now(int sig) #define usec(x) (1000*(x)) #define msec(x) usec(1000*(x)) -static void threads(int timeout) +static void thread(int fd, struct drm_gem_open name, + int timeout, unsigned int flags) +#define CONTEXTS 0x1 { struct sigevent sev; struct sigaction act; - struct drm_gem_open name; struct itimerspec its; + uint32_t *history; +#define N_HISTORY (256) timer_t timer; - int fd; + + history = malloc(sizeof(*history) * N_HISTORY); + igt_assert(history); memset(&act, 0, sizeof(act)); act.sa_handler = crashme_now; @@ -184,28 +190,57 @@ static void threads(int timeout) sev.sigev_signo = SIGRTMIN; igt_assert(timer_create(CLOCK_MONOTONIC, &sev, &timer) == 0); - fd = drm_open_driver(DRIVER_INTEL); - name.name = gem_flink(fd, gem_create(fd, OBJECT_SIZE)); - igt_until_timeout(timeout) { - crashme.fd = drm_open_driver(DRIVER_INTEL); + unsigned int n = 0; + + memset(history, 0, sizeof(*history) * N_HISTORY); + + crashme.fd = gem_reopen_driver(fd); memset(&its, 0, sizeof(its)); - its.it_value.tv_nsec = msec(1) + (rand() % msec(10)); + its.it_value.tv_nsec = msec(1) + (rand() % msec(150)); igt_assert(timer_settime(timer, 0, &its, NULL) == 0); do { - if (drmIoctl(crashme.fd, DRM_IOCTL_GEM_OPEN, &name)) + uint32_t ctx = 0; + + if (drmIoctl(crashme.fd, + DRM_IOCTL_GEM_OPEN, + &name)) break; - selfcopy(crashme.fd, name.handle, 100); - drmIoctl(crashme.fd, DRM_IOCTL_GEM_CLOSE, &name.handle); + if (flags & CONTEXTS) + __gem_context_create(crashme.fd, &ctx); + + selfcopy(crashme.fd, ctx, name.handle, 1); + + ctx = history[n % N_HISTORY]; + if (ctx) + drmIoctl(crashme.fd, + DRM_IOCTL_GEM_CLOSE, + &ctx); + history[n % N_HISTORY] = name.handle; + n++; } while (1); close(crashme.fd); } timer_delete(timer); + free(history); +} + +static void threads(int timeout, unsigned int flags) +{ + struct drm_gem_open name; + int fd; + + fd = drm_open_driver(DRIVER_INTEL); + name.name = gem_flink(fd, gem_create(fd, OBJECT_SIZE)); + + igt_fork(child, sysconf(_SC_NPROCESSORS_ONLN)) + thread(fd, name, timeout, flags); + igt_waitchildren(); gem_quiescent_gpu(fd); close(fd); @@ -233,7 +268,7 @@ igt_main } igt_subtest("basic-threads") - threads(1); + threads(1, 0); igt_subtest("process-exit") { igt_fork(child, 768) @@ -241,8 +276,11 @@ igt_main igt_waitchildren(); } + igt_subtest("contexts") + threads(30, CONTEXTS); + igt_subtest("gem-close-race") - threads(150); + threads(150, 0); igt_fixture igt_stop_hang_detector(); -- 2.27.0 From ville.syrjala at linux.intel.com Tue Jun 30 21:25:38 2020 From: ville.syrjala at linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 1 Jul 2020 00:25:38 +0300 Subject: [Intel-gfx] [PATCH v4 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status In-Reply-To: <20200630211045.GA21520@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> <20200630210330.GU6112@intel.com> <20200630211045.GA21520@intel.com> Message-ID: <20200630212538.GW6112@intel.com> On Tue, Jun 30, 2020 at 02:10:45PM -0700, Manasi Navare wrote: > On Wed, Jul 01, 2020 at 12:03:30AM +0300, Ville Syrj?l? wrote: > > On Fri, Jun 26, 2020 at 04:26:40PM -0700, Manasi Navare wrote: > > > Modify the helper to add a fixed delay or poll with timeout > > > based on platform specification to check for either Idle bit > > > set (DDI_BUF_CTL is idle for disable case) > > > > > > v3: > > > * Change the timeout to 16usecs (Ville) > > > v2: > > > * Use 2 separate functions or idle and active (Ville) > > > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > Cc: Imre Deak <imre.deak at intel.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_ddi.c | 17 ++++++++--------- > > > 1 file changed, 8 insertions(+), 9 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > > index 884b507c5f55..052a74625a61 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > > @@ -1184,16 +1184,15 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > > > static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > > enum port port) > > > { > > > - i915_reg_t reg = DDI_BUF_CTL(port); > > > - int i; > > > - > > > - for (i = 0; i < 16; i++) { > > > - udelay(1); > > > - if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) > > > - return; > > > + if (IS_BROXTON(dev_priv)) { > > > + udelay(16); > > > + return; > > > } > > > - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n", > > > - port_name(port)); > > > + > > > + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > > + DDI_BUF_IS_IDLE), 16)) > > > > 16 is the BXT number. IIRC the spec said 8 usec for the other platforms. > > > > Yes I see for HSW atleast yes it says 8usecs but i left it at 16 since thats > what we always had and the only change was that BXT add a fixed delay > But if you prefer i will change it to 8us timeout? My usual approach is to a) just use the spec value, b) if there's a sane reason for not using it then include a comment documenting the spec value. Often b) is just for "spec say a few microseconds, let's just wait a full millisecond to make it simple", or for "old platforms want timeout N, new ones want M, just go with the larger of the two for simplicity". Arguably the current code was trying to follow the latter approach, except if was supposed to since bxt wasn't supposed to poll at all. Anyways, since the current code already used 16 usec without any clarification I guess this is no worse than what we had. Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Manasi > > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", > > > + port_name(port)); > > > } > > > > > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > > -- > > > 2.19.1 > > > > -- > > Ville Syrj?l? > > Intel -- Ville Syrj?l? Intel From anitha.chrisanthus at intel.com Tue Jun 30 21:27:12 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:12 -0700 Subject: [Intel-gfx] [PATCH 00/59] Add support for Keem Bay DRM driver Message-ID: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> This is a new DRM driver for Intel's KeemBay SOC. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU. This driver is tested with the KMB EVM board which is the refernce baord for Keem Bay SOC. The SOC's display pipeline is as follows +--------------+ +---------+ +-----------------------+ |LCD controller| -> |Mipi DSI | -> |Mipi to HDMI Converter | +--------------+ +---------+ +-----------------------+ LCD controller and Mipi DSI transmitter are part of the SOC and mipi to HDMI converter is ADV7535 for KMB EVM board. The DRM driver is a basic KMS atomic modesetting display driver and has no 2D or 3D graphics.It calls into the ADV bridge driver at the connector level. Only 1080p resolution and single plane is supported at this time. The usecase is for debugging video and camera outputs. Since we are just starting the upstream process, the KMB EVM board is not in mainline and so Device tree changes are missing. Anitha Chrisanthus (52): drm/kmb: Add support for KeemBay Display drm/kmb: Added id to kmb_plane drm/kmb: Set correct values in the LAYERn_CFG register drm/kmb: Use biwise operators for register definitions drm/kmb: Updated kmb_plane_atomic_check drm/kmb: Initial check-in for Mipi DSI drm/kmb: Set OUT_FORMAT_CFG register drm/kmb: Added mipi_dsi_host initialization drm/kmb: Part 1 of Mipi Tx Initialization drm/kmb: Part 2 of Mipi Tx Initialization drm/kmb: Use correct mmio offset from data book drm/kmb: Part3 of Mipi Tx initialization drm/kmb: Part4 of Mipi Tx Initialization drm/kmb: Correct address offsets for mipi registers drm/kmb: Part5 of Mipi Tx Intitialization drm/kmb: Part6 of Mipi Tx Initialization drm/kmb: Part7 of Mipi Tx Initialization drm/kmb: Part8 of Mipi Tx Initialization drm/kmb: Added ioremap/iounmap for register access drm/kmb: Register IRQ for LCD drm/kmb: IRQ handlers for LCD and mipi dsi drm/kmb: Set hardcoded values to LCD_VSYNC_START drm/kmb: Additional register programming to update_plane drm/kmb: Add ADV7535 bridge drm/kmb: Display clock enable/disable drm/kmb: rebase to newer kernel version drm/kmb: minor name change to match device tree drm/kmb: Changed MMIO size drm/kmb: Defer Probe drm/kmb: call bridge init in the very beginning drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable drm/kmb: Mipi DPHY initialization changes drm/kmb: Fixed driver unload drm/kmb: Added LCD_TEST config drm/kmb: Changes for LCD to Mipi drm/kmb: Update LCD programming to match MIPI drm/kmb: Changed name of driver to kmb-drm drm/kmb: Mipi settings from input timings drm/kmb: Enable LCD interrupts drm/kmb: Enable LCD interrupts during modeset drm/kmb: Don?t inadvertantly disable LCD controller drm/kmb: SWAP R and B LCD Layer order drm/kmb: Disable ping pong mode drm/kmb: Do the layer initializations only once drm/kmb: disable the LCD layer in EOF irq handler drm/kmb: Initialize uninitialized variables drm/kmb: Added useful messages in LCD ISR kmb/drm: Prune unsupported modes drm/kmb: workaround for dma undeflow issue drm/kmb: Get System Clock from SCMI drm/kmb: work around for planar formats Edmund Dea (7): drm/kmb: Cleanup probe functions drm/kmb: Revert dsi_host back to a static variable drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg. drm/kmb: Remove declaration of irq_lcd/irq_mipi drm/kmb: Enable MIPI TX HS Test Pattern Generation drm/kmb: Write to LCD_LAYERn_CFG only once drm/kmb: Cleaned up code drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/kmb/Kconfig | 12 + drivers/gpu/drm/kmb/Makefile | 2 + drivers/gpu/drm/kmb/kmb_crtc.c | 243 +++++ drivers/gpu/drm/kmb/kmb_crtc.h | 61 ++ drivers/gpu/drm/kmb/kmb_drv.c | 828 +++++++++++++++++ drivers/gpu/drm/kmb/kmb_drv.h | 196 ++++ drivers/gpu/drm/kmb/kmb_dsi.c | 1950 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 390 ++++++++ drivers/gpu/drm/kmb/kmb_plane.c | 538 +++++++++++ drivers/gpu/drm/kmb/kmb_plane.h | 142 +++ drivers/gpu/drm/kmb/kmb_regs.h | 758 +++++++++++++++ 13 files changed, 5123 insertions(+) create mode 100644 drivers/gpu/drm/kmb/Kconfig create mode 100644 drivers/gpu/drm/kmb/Makefile create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.c create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.h create mode 100644 drivers/gpu/drm/kmb/kmb_drv.c create mode 100644 drivers/gpu/drm/kmb/kmb_drv.h create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.c create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.h create mode 100644 drivers/gpu/drm/kmb/kmb_plane.c create mode 100644 drivers/gpu/drm/kmb/kmb_plane.h create mode 100644 drivers/gpu/drm/kmb/kmb_regs.h -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:13 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:13 -0700 Subject: [Intel-gfx] [PATCH 01/59] drm/kmb: Add support for KeemBay Display In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-2-git-send-email-anitha.chrisanthus@intel.com> Initial check-in for basic display driver for KeemBay family of SOCs. This is not tested and does not work and also there are many TBDs in the code which will be implemented in future commits. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/kmb/Kconfig | 12 ++ drivers/gpu/drm/kmb/Makefile | 2 + drivers/gpu/drm/kmb/kmb_crtc.c | 215 +++++++++++++++++++ drivers/gpu/drm/kmb/kmb_crtc.h | 59 ++++++ drivers/gpu/drm/kmb/kmb_drv.c | 372 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_drv.h | 67 ++++++ drivers/gpu/drm/kmb/kmb_plane.c | 252 ++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_plane.h | 52 +++++ drivers/gpu/drm/kmb/kmb_regs.h | 460 ++++++++++++++++++++++++++++++++++++++++ 11 files changed, 1494 insertions(+) create mode 100644 drivers/gpu/drm/kmb/Kconfig create mode 100644 drivers/gpu/drm/kmb/Makefile create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.c create mode 100644 drivers/gpu/drm/kmb/kmb_crtc.h create mode 100644 drivers/gpu/drm/kmb/kmb_drv.c create mode 100644 drivers/gpu/drm/kmb/kmb_drv.h create mode 100644 drivers/gpu/drm/kmb/kmb_plane.c create mode 100644 drivers/gpu/drm/kmb/kmb_plane.h create mode 100644 drivers/gpu/drm/kmb/kmb_regs.h diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c4fd57d..5292574 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -275,6 +275,8 @@ source "drivers/gpu/drm/nouveau/Kconfig" source "drivers/gpu/drm/i915/Kconfig" +source "drivers/gpu/drm/kmb/Kconfig" + config DRM_VGEM tristate "Virtual GEM provider" depends on DRM diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 2c0e5a7..bdbdc63 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/ obj-$(CONFIG_DRM_MGA) += mga/ obj-$(CONFIG_DRM_I810) += i810/ obj-$(CONFIG_DRM_I915) += i915/ +obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb/ obj-$(CONFIG_DRM_MGAG200) += mgag200/ obj-$(CONFIG_DRM_V3D) += v3d/ obj-$(CONFIG_DRM_VC4) += vc4/ diff --git a/drivers/gpu/drm/kmb/Kconfig b/drivers/gpu/drm/kmb/Kconfig new file mode 100644 index 0000000..005a9962 --- /dev/null +++ b/drivers/gpu/drm/kmb/Kconfig @@ -0,0 +1,12 @@ +config DRM_KMB_DISPLAY + tristate "KEEMBAY DISPLAY" + depends on DRM && OF && (ARM || ARM64) + depends on COMMON_CLK + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + select DRM_GEM_CMA_HELPER + select VIDEOMODE_HELPERS + help + Choose this option if you have an KEEMBAY DISPLAY controller. + + If M is selected the module will be called kmb-display. diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile new file mode 100644 index 0000000..be9f19c --- /dev/null +++ b/drivers/gpu/drm/kmb/Makefile @@ -0,0 +1,2 @@ +kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o +obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-display.o diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c new file mode 100644 index 0000000..ab1fff8 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright ? 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + */ + +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_plane_helper.h> +#include <linux/clk.h> +#include <linux/of_graph.h> +#include <linux/platform_data/simplefb.h> +#include <video/videomode.h> +#include "kmb_crtc.h" +#include "kmb_drv.h" +#include "kmb_plane.h" +#include "kmb_regs.h" + +static void kmb_crtc_cleanup(struct drm_crtc *crtc) +{ + struct kmb_crtc *l_crtc = to_kmb_crtc(crtc); + + drm_crtc_cleanup(crtc); + kfree(l_crtc); +} + +static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) +{ + struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); + + /*clear interrupt */ + kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP); + /*set which interval to generate vertical interrupt */ + kmb_write(lcd, LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC); + /* enable vertical interrupt */ + kmb_write(lcd, LCD_INT_ENABLE, LCD_INT_VERT_COMP); + return 0; +} + +static void kmb_crtc_disable_vblank(struct drm_crtc *crtc) +{ + struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); + + /*clear interrupt */ + kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP); + /* disable vertical interrupt */ + kmb_write(lcd, LCD_INT_ENABLE, 0); + +/* TBD + * set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register + * set the required bit LCD_VSTATUS_COMPARE register + * Not sure if anything needs to be done in the ICB + */ +} + +static const struct drm_crtc_funcs kmb_crtc_funcs = { + .destroy = kmb_crtc_cleanup, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .reset = drm_atomic_helper_crtc_reset, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, + .enable_vblank = kmb_crtc_enable_vblank, + .disable_vblank = kmb_crtc_disable_vblank, +}; + +static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) +{ + struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); + struct drm_display_mode *m = &crtc->state->adjusted_mode; + struct videomode vm; + int vsync_start_offset; + int vsync_end_offset; + unsigned int ctrl = 0; + + vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; + vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; + vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; + vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; + vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; + vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; + + vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; + vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; + + kmb_write(lcd, LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1); + kmb_write(lcd, LCD_V_BACKPORCH, vm.vback_porch - 1); + kmb_write(lcd, LCD_V_FRONTPORCH, vm.vfront_porch - 1); + kmb_write(lcd, LCD_VSYNC_WIDTH, vm.vsync_len - 1); + kmb_write(lcd, LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1); + kmb_write(lcd, LCD_H_BACKPORCH, vm.hback_porch - 1); + kmb_write(lcd, LCD_H_FRONTPORCH, vm.hfront_porch - 1); + kmb_write(lcd, LCD_HSYNC_WIDTH, vm.hsync_len - 1); + + if (m->flags == DRM_MODE_FLAG_INTERLACE) { + kmb_write(lcd, LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); + kmb_write(lcd, LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1); + kmb_write(lcd, LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); + kmb_write(lcd, LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); + kmb_write(lcd, LCD_VSYNC_START_EVEN, vsync_start_offset); + kmb_write(lcd, LCD_VSYNC_END_EVEN, vsync_end_offset); + } + /* enable all 4 layers */ + ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE + | LCD_CTRL_VL2_ENABLE | LCD_CTRL_GL1_ENABLE | LCD_CTRL_GL2_ENABLE; + ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_OUTPUT_ENABLED; + kmb_write(lcd, LCD_CONTROL, ctrl); + + kmb_write(lcd, LCD_TIMING_GEN_TRIG, ENABLE); + + /* TBD */ + /* set clocks here */ +} + +static void kmb_crtc_atomic_enable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); + + clk_prepare_enable(lcd->clk); + kmb_crtc_mode_set_nofb(crtc); + drm_crtc_vblank_on(crtc); +} + +static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); + + /* always disable planes on the CRTC that is being turned off */ + drm_atomic_helper_disable_planes_on_crtc(old_state, false); + + drm_crtc_vblank_off(crtc); + clk_disable_unprepare(lcd->clk); +} + +static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + /* TBD */ + /*disable vblank interrupts here + * clear BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE + */ +} + +static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + /* TBD */ + /*enable vblank interrupts after + * set BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE + */ + + spin_lock_irq(&crtc->dev->event_lock); + if (crtc->state->event) + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + spin_unlock_irq(&crtc->dev->event_lock); + +} + +static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = { + .atomic_begin = kmb_crtc_atomic_begin, + .atomic_enable = kmb_crtc_atomic_enable, + .atomic_disable = kmb_crtc_atomic_disable, + .atomic_flush = kmb_crtc_atomic_flush, +}; + +int kmb_setup_crtc(struct drm_device *drm) +{ + struct kmb_drm_private *lcd = drm->dev_private; + struct drm_plane *primary; + int ret; + + primary = kmb_plane_init(drm); + if (IS_ERR(primary)) + return PTR_ERR(primary); + + ret = drm_crtc_init_with_planes(drm, &lcd->crtc, primary, NULL, + &kmb_crtc_funcs, NULL); + if (ret) { + kmb_plane_destroy(primary); + return ret; + } + + drm_crtc_helper_add(&lcd->crtc, &kmb_crtc_helper_funcs); + return 0; +} diff --git a/drivers/gpu/drm/kmb/kmb_crtc.h b/drivers/gpu/drm/kmb/kmb_crtc.h new file mode 100644 index 0000000..0952733 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_crtc.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright ? 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + */ +#ifndef __KMB_CRTC_H__ +#define __KMB_CRTC_H__ + +#include <drm/drm_file.h> +#include <drm/drm_device.h> +#include <drm/drm_vblank.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_fourcc.h> +#include <drm/drm_debugfs.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_drv.h> +#include <drm/drm_print.h> +#include <linux/clk.h> +#include <linux/of_graph.h> +#include <linux/platform_data/simplefb.h> +#include <video/videomode.h> +#include <linux/mutex.h> +#include <linux/wait.h> +#include <linux/platform_device.h> +#include "kmb_drv.h" + +struct kmb_crtc { + struct drm_crtc crtc_base; + struct kmb_drm_private kmb_dev; +}; + +struct kmb_crtc_state { + struct drm_crtc_state crtc_base; +}; +#define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) +#define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base) +extern void kmb_plane_destroy(struct drm_plane *plane); +extern struct drm_plane *kmb_plane_init(struct drm_device *drm); +#endif /* __KMB_CRTC_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c new file mode 100644 index 0000000..fced630 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright ? 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * + */ +#include <linux/module.h> +#include <linux/spinlock.h> +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/console.h> +#include <linux/list.h> +#include <linux/of_graph.h> +#include <linux/of_reserved_mem.h> +#include <linux/pm_runtime.h> +#include <drm/drm.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_ioctl.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_irq.h> +#include "kmb_drv.h" +#include "kmb_regs.h" +#include "kmb_crtc.h" +#include "kmb_plane.h" + +static int kmb_load(struct drm_device *drm, unsigned long flags) +{ + struct kmb_drm_private *lcd = drm->dev_private; + struct platform_device *pdev = to_platform_device(drm->dev); + struct resource *res; + /*u32 version; */ + int ret; + + /* TBD - not sure if clock_get needs to be called here */ + /* + * lcd->clk = devm_clk_get(drm->dev, "pxlclk"); + * if (IS_ERR(lcd->clk)) + * return PTR_ERR(lcd->clk); + */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + lcd->mmio = devm_ioremap_resource(drm->dev, res); + if (IS_ERR(lcd->mmio)) { + DRM_ERROR("failed to map control registers area\n"); + ret = PTR_ERR(lcd->mmio); + lcd->mmio = NULL; + return ret; + } + /*TBD read and check for correct product version here */ + + /* Get the optional framebuffer memory resource */ + ret = of_reserved_mem_device_init(drm->dev); + if (ret && ret != -ENODEV) + return ret; + + ret = kmb_setup_crtc(drm); + if (ret < 0) { + DRM_ERROR("failed to create crtc\n"); + goto setup_fail; + } + + ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); + if (ret < 0) { + DRM_ERROR("failed to install IRQ handler\n"); + goto irq_fail; + } + + return 0; + +irq_fail: + drm_crtc_cleanup(&lcd->crtc); +setup_fail: + of_reserved_mem_device_release(drm->dev); + + return ret; +} + +static const struct drm_mode_config_funcs kmb_mode_config_funcs = { + .fb_create = drm_gem_fb_create, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, +}; + +static void kmb_setup_mode_config(struct drm_device *drm) +{ + drm_mode_config_init(drm); + drm->mode_config.min_width = 0; + drm->mode_config.min_height = 0; + drm->mode_config.max_width = KMB_MAX_WIDTH; + drm->mode_config.max_height = KMB_MAX_HEIGHT; + drm->mode_config.funcs = &kmb_mode_config_funcs; +} + +static irqreturn_t kmb_irq(int irq, void *arg) +{ + struct drm_device *dev = (struct drm_device *)arg; + struct kmb_drm_private *lcd = dev->dev_private; + unsigned long status, val; + + status = kmb_read(lcd, LCD_INT_STATUS); + if (status & LCD_INT_EOF) { + /*To DO - handle EOF interrupt? */ + kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_EOF); + } + if (status & LCD_INT_LINE_CMP) { + /* clear line compare interrupt */ + kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_LINE_CMP); + } + if (status & LCD_INT_VERT_COMP) { + /* read VSTATUS */ + val = kmb_read(lcd, LCD_VSTATUS); + /* BITS 13 and 14 */ + val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK) >> 12; + switch (val) { + case LCD_VSTATUS_COMPARE_VSYNC: + case LCD_VSTATUS_COMPARE_BACKPORCH: + case LCD_VSTATUS_COMPARE_ACTIVE: + case LCD_VSTATUS_COMPARE_FRONT_PORCH: + /* clear vertical compare interrupt */ + kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP); + drm_handle_vblank(dev, 0); + break; + } + } + + return IRQ_HANDLED; +} + +static void kmb_irq_reset(struct drm_device *drm) +{ + struct kmb_drm_private *lcd = drm->dev_private; + + kmb_write(lcd, LCD_INT_CLEAR, 0xFFFF); + kmb_write(lcd, LCD_INT_ENABLE, 0); +} + +DEFINE_DRM_GEM_CMA_FOPS(fops); + +static struct drm_driver kmb_driver = { + .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | + DRIVER_MODESET | DRIVER_ATOMIC, + .irq_handler = kmb_irq, + .irq_preinstall = kmb_irq_reset, + .irq_uninstall = kmb_irq_reset, + .gem_free_object_unlocked = drm_gem_cma_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + .dumb_create = drm_gem_cma_dumb_create, + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_export = drm_gem_prime_export, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, + .gem_prime_vmap = drm_gem_cma_prime_vmap, + .gem_prime_vunmap = drm_gem_cma_prime_vunmap, + .gem_prime_mmap = drm_gem_cma_prime_mmap, + .fops = &fops, + .name = "kmb", + .desc = "KEEMBAY DISPLAY DRIVER ", + .date = "20190122", + .major = 1, + .minor = 0, +}; + +static int kmb_drm_bind(struct device *dev) +{ + struct drm_device *drm; + struct kmb_drm_private *lcd; + int ret; + + drm = drm_dev_alloc(&kmb_driver, dev); + if (IS_ERR(drm)) + return PTR_ERR(drm); + + lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL); + if (!lcd) + return -ENOMEM; + + drm->dev_private = lcd; + dev_set_drvdata(dev, drm); + + kmb_setup_mode_config(drm); + ret = kmb_load(drm, 0); + if (ret) + goto err_free; + + /* Set the CRTC's port so that the encoder component can find it */ + lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); + + ret = component_bind_all(dev, drm); + if (ret) { + DRM_ERROR("Failed to bind all components\n"); + goto err_unload; + } + + ret = pm_runtime_set_active(dev); + if (ret) + goto err_pm_active; + + pm_runtime_enable(dev); + + ret = drm_vblank_init(drm, drm->mode_config.num_crtc); + if (ret < 0) { + DRM_ERROR("failed to initialise vblank\n"); + goto err_vblank; + } + + drm_mode_config_reset(drm); + drm_kms_helper_poll_init(drm); + + ret = drm_dev_register(drm, 0); + + lcd->n_layers = KMB_MAX_PLANES; + if (ret) + goto err_register; + + return 0; + +err_register: + drm_kms_helper_poll_fini(drm); +err_vblank: + pm_runtime_disable(drm->dev); +err_pm_active: + component_unbind_all(dev, drm); +err_unload: + of_node_put(lcd->crtc.port); + lcd->crtc.port = NULL; + drm_irq_uninstall(drm); + of_reserved_mem_device_release(drm->dev); +err_free: + drm_mode_config_cleanup(drm); + dev_set_drvdata(dev, NULL); + drm_dev_put(drm); + + return ret; +} + +static void kmb_drm_unbind(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct kmb_drm_private *lcd = drm->dev_private; + + drm_dev_unregister(drm); + drm_kms_helper_poll_fini(drm); + component_unbind_all(dev, drm); + of_node_put(lcd->crtc.port); + lcd->crtc.port = NULL; + pm_runtime_get_sync(drm->dev); + drm_irq_uninstall(drm); + pm_runtime_put_sync(drm->dev); + pm_runtime_disable(drm->dev); + of_reserved_mem_device_release(drm->dev); + drm_mode_config_cleanup(drm); + drm_dev_put(drm); + drm->dev_private = NULL; + dev_set_drvdata(dev, NULL); +} + +static const struct component_master_ops kmb_master_ops = { + .bind = kmb_drm_bind, + .unbind = kmb_drm_unbind, +}; + +static int compare_dev(struct device *dev, void *data) +{ + return dev->of_node == data; +} + +static int kmb_probe(struct platform_device *pdev) +{ + struct device_node *port; + struct component_match *match = NULL; + + /* there is only one output port inside each device, find it */ + port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); + if (!port) + return -ENODEV; + + drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); + of_node_put(port); + + return component_master_add_with_match(&pdev->dev, &kmb_master_ops, + match); +} + +static int kmb_remove(struct platform_device *pdev) +{ + component_master_del(&pdev->dev, &kmb_master_ops); + return 0; +} + +static const struct of_device_id kmb_of_match[] = { + {.compatible = "lcd"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, kmb_of_match); + +static int __maybe_unused kmb_pm_suspend(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct kmb_drm_private *lcd = drm ? drm->dev_private : NULL; + + if (!lcd) + return 0; + + drm_kms_helper_poll_disable(drm); + + lcd->state = drm_atomic_helper_suspend(drm); + if (IS_ERR(lcd->state)) { + drm_kms_helper_poll_enable(drm); + return PTR_ERR(lcd->state); + } + + return 0; +} + +static int __maybe_unused kmb_pm_resume(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + struct kmb_drm_private *lcd = drm ? drm->dev_private : NULL; + + if (!lcd) + return 0; + + drm_atomic_helper_resume(drm, lcd->state); + drm_kms_helper_poll_enable(drm); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume); + +static struct platform_driver kmb_platform_driver = { + .probe = kmb_probe, + .remove = kmb_remove, + .driver = { + .name = "Keembay_Display", + .pm = &kmb_pm_ops, + .of_match_table = kmb_of_match, + }, +}; + +module_platform_driver(kmb_platform_driver); + +MODULE_AUTHOR("Intel Corporation"); +MODULE_DESCRIPTION("Keembay Display driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h new file mode 100644 index 0000000..05e9791 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright ? 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + */ +#ifndef __KMB_DRV_H__ +#define __KMB_DRV_H__ + +#define KMB_MAX_WIDTH 16384 /*max width in pixels */ +#define KMB_MAX_HEIGHT 16384 /*max height in pixels */ + +struct kmb_drm_private { + struct drm_device drm; + void __iomem *mmio; + unsigned char n_layers; + struct clk *clk; + struct drm_fbdev_cma *fbdev; + struct drm_crtc crtc; + struct drm_plane *plane; + struct drm_atomic_state *state; +}; + +static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) +{ + return container_of(dev, struct kmb_drm_private, drm); +} + +#define crtc_to_kmb_priv(x) container_of(x, struct kmb_drm_private, crtc) + +struct blt_layer_config { + unsigned char layer_format; +}; + +static inline void kmb_write(struct kmb_drm_private *lcd, + unsigned int reg, u32 value) +{ + writel(value, lcd->mmio + reg); +} + +static inline u32 kmb_read(struct kmb_drm_private *lcd, unsigned int reg) +{ + return readl(lcd->mmio + reg); +} + +int kmb_setup_crtc(struct drm_device *dev); +void kmb_set_scanout(struct kmb_drm_private *lcd); +#endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c new file mode 100644 index 0000000..9ab3873 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright ? 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + */ +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_fb_helper.h> +#include <drm/drm_fb_cma_helper.h> +#include <drm/drm_gem_cma_helper.h> +#include <drm/drm_of.h> +#include <drm/drm_plane_helper.h> +#include <linux/clk.h> +#include <linux/of_graph.h> +#include <linux/platform_data/simplefb.h> +#include <video/videomode.h> +#include "kmb_plane.h" +#include "kmb_crtc.h" +#include "kmb_regs.h" +#include "kmb_drv.h" + +static int kmb_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ +/* TBD below structure will be used for implementation later + * struct drm_crtc_state *crtc_state; + */ + /* TBD */ + /* Plane based checking */ + + return 0; +} + +static void kmb_plane_atomic_update(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct drm_framebuffer *fb = plane->state->fb; + struct kmb_drm_private *lcd; + dma_addr_t addr; + unsigned int width; + unsigned int height; + unsigned int i; + unsigned int dma_len; + struct kmb_plane_state *kmb_state = to_kmb_plane_state(plane->state); + unsigned int dma_cfg; + + if (!fb) + return; + + lcd = plane->dev->dev_private; + + /* TBD */ + /*set LCD_LAYERn_WIDTH, LCD_LAYERn_HEIGHT, LCD_LAYERn_COL_START, + * LCD_LAYERn_ROW_START, LCD_LAYERn_CFG + * CFG should set the pixel format, FIFO level and BPP + */ + + /* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */ + dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE + | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1; + + for (i = 0; i < kmb_state->no_planes; i++) { + /* disable DMA first */ + kmb_write(lcd, LCD_LAYERn_DMA_CFG(i), ~LCD_DMA_LAYER_ENABLE); + + addr = drm_fb_cma_get_gem_addr(fb, plane->state, i); + kmb_write(lcd, LCD_LAYERn_DMA_START_ADDR(i), addr); + kmb_write(lcd, LCD_LAYERn_DMA_START_SHADOW(i), addr); + + width = fb->width; + height = fb->height; + dma_len = width * height * fb->format->cpp[i]; + kmb_write(lcd, LCD_LAYERn_DMA_LEN(i), dma_len); + + kmb_write(lcd, LCD_LAYERn_DMA_LINE_VSTRIDE(i), fb->pitches[0]); + kmb_write(lcd, LCD_LAYERn_DMA_LINE_WIDTH(i), + (width * fb->format->cpp[i])); + + /* enable DMA */ + kmb_write(lcd, LCD_LAYERn_DMA_CFG(i), dma_cfg); + } +} + +static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { + .atomic_check = kmb_plane_atomic_check, + .atomic_update = kmb_plane_atomic_update, +}; + +void kmb_plane_destroy(struct drm_plane *plane) +{ + drm_plane_cleanup(plane); +} + +static void kmb_destroy_plane_state(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct kmb_plane_state *kmb_state = to_kmb_plane_state(state); + + __drm_atomic_helper_plane_destroy_state(state); + kfree(kmb_state); +} + +struct drm_plane_state *kmb_plane_duplicate_state(struct drm_plane *plane) +{ + struct drm_plane_state *state; + struct kmb_plane_state *kmb_state; + + kmb_state = kmemdup(plane->state, sizeof(*kmb_state), GFP_KERNEL); + + if (!kmb_state) + return NULL; + + state = &kmb_state->base_plane_state; + __drm_atomic_helper_plane_duplicate_state(plane, state); + + return state; +} + +static void kmb_plane_reset(struct drm_plane *plane) +{ + struct kmb_plane_state *kmb_state = to_kmb_plane_state(plane->state); + + if (kmb_state) + __drm_atomic_helper_plane_destroy_state + (&kmb_state->base_plane_state); + kfree(kmb_state); + + plane->state = NULL; + kmb_state = kzalloc(sizeof(*kmb_state), GFP_KERNEL); + if (kmb_state) { + kmb_state->base_plane_state.plane = plane; + kmb_state->base_plane_state.rotation = DRM_MODE_ROTATE_0; + plane->state = &kmb_state->base_plane_state; + kmb_state->no_planes = KMB_MAX_PLANES; + } +} + +static const struct drm_plane_funcs kmb_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = kmb_plane_destroy, + .reset = kmb_plane_reset, + .atomic_duplicate_state = kmb_plane_duplicate_state, + .atomic_destroy_state = kmb_destroy_plane_state, +}; + +/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ +static const u32 kmb_formats_g[] = { + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010, + DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, +}; + +/* video layer (0 & 1) formats, packed and planar formats are supported */ +static const u32 kmb_formats_v[] = { + /* packed formats */ + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010, + DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, + /*planar formats */ + DRM_FORMAT_YUV411, DRM_FORMAT_YVU411, + DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, + DRM_FORMAT_NV12, DRM_FORMAT_NV21, +}; + +struct drm_plane *kmb_plane_init(struct drm_device *drm) +{ + struct kmb_drm_private *lcd = drm->dev_private; + struct drm_plane *plane = NULL; + struct drm_plane *primary = NULL; + int i = 0; + int ret; + enum drm_plane_type plane_type; + const uint32_t *plane_formats; + int num_plane_formats; + + for (i = 0; i < lcd->n_layers; i++) { + + plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); + + if (!plane) + return ERR_PTR(-ENOMEM); + + plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : + DRM_PLANE_TYPE_OVERLAY; + if (i < 2) { + plane_formats = kmb_formats_v; + num_plane_formats = ARRAY_SIZE(kmb_formats_v); + } else { + plane_formats = kmb_formats_g; + num_plane_formats = ARRAY_SIZE(kmb_formats_g); + } + + ret = drm_universal_plane_init(drm, plane, 0xFF, + &kmb_plane_funcs, plane_formats, + num_plane_formats, + NULL, plane_type, "plane %d", i); + if (ret < 0) + goto cleanup; + + drm_plane_helper_add(plane, &kmb_plane_helper_funcs); + if (plane_type == DRM_PLANE_TYPE_PRIMARY) { + primary = plane; + lcd->plane = plane; + } + } + +cleanup: + return primary; +} diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h new file mode 100644 index 0000000..84c7113 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright ? 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + */ +#ifndef __KMB_PLANE_H__ +#define __KMB_PLANE_H__ + +#include "kmb_drv.h" + +#define KMB_MAX_PLANES 4 + +/* this struct may be needed in the future + *struct kmb_plane { + * struct drm_plane base_plane; + * struct kmb_drm_private kmb_dev; + *}; + */ +struct kmb_plane_state { + struct drm_plane_state base_plane_state; + unsigned char no_planes; +}; + +/* may be needed in the future + *#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) + */ +#define to_kmb_plane_state(x) \ + container_of(x, struct kmb_plane_state, base_plane_state) + +struct drm_plane *kmb_plane_init(struct drm_device *drm); +void kmb_plane_destroy(struct drm_plane *plane); +#endif /* __KMB_PLANE_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h new file mode 100644 index 0000000..95cf932 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -0,0 +1,460 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright ? 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * + */ +#ifndef __KMB_REGS_H__ +#define __KMB_REGS_H__ + +/*LCD CONTROLLER REGISTERS */ +#define LCD_CONTROL (0x4 * 0x000) +#define LCD_INT_STATUS (0x4 * 0x001) +#define LCD_INT_ENABLE (0x4 * 0x002) +#define LCD_INT_CLEAR (0x4 * 0x003) +#define LCD_LINE_COUNT (0x4 * 0x004) +#define LCD_LINE_COMPARE (0x4 * 0x005) +#define LCD_VSTATUS (0x4 * 0x006) +#define LCD_VSTATUS_COMPARE (0x4 * 0x007) +#define LCD_SCREEN_WIDTH (0x4 * 0x008) +#define LCD_SCREEN_HEIGHT (0x4 * 0x009) +#define LCD_FIELD_INT_CFG (0x4 * 0x00a) +#define LCD_FIFO_FLUSH (0x4 * 0x00b) +#define LCD_BG_COLOUR_LS (0x4 * 0x00c) +#define LCD_BG_COLOUR_MS (0x4 * 0x00d) +#define LCD_RAM_CFG (0x4 * 0x00e) +#define LCD_LAYER0_CFG (0x4 * 0x100) +#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) +#define LCD_LAYER0_COL_START (0x4 * 0x101) +#define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400*N)) +#define LCD_LAYER0_ROW_START (0x4 * 0x102) +#define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400*N)) +#define LCD_LAYER0_WIDTH (0x4 * 0x103) +#define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400*N)) +#define LCD_LAYER0_HEIGHT (0x4 * 0x104) +#define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400*N)) +#define LCD_LAYER0_SCALE_CFG (0x4 * 0x105) +#define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400*N)) +#define LCD_LAYER0_ALPHA (0x4 * 0x106) +#define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400*N)) +#define LCD_LAYER0_INV_COLOUR_LS (0x4 * 0x107) +#define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + (0x400*N)) +#define LCD_LAYER0_INV_COLOUR_MS (0x4 * 0x108) +#define LCD_LAYERn_INV_COLOUR_MS(N) (LCD_LAYER0_INV_COLOUR_MS + (0x400*N)) +#define LCD_LAYER0_TRANS_COLOUR_LS (0x4 * 0x109) +#define LCD_LAYERn_TRANS_COLOUR_LS(N) (LCD_LAYER0_TRANS_COLOUR_LS + (0x400*N)) +#define LCD_LAYER0_TRANS_COLOUR_MS (0x4 * 0x10a) +#define LCD_LAYERn_TRANS_COLOUR_MS(N) (LCD_LAYER0_TRANS_COLOUR_MS + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF11 (0x4 * 0x10b) +#define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF12 (0x4 * 0x10c) +#define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF13 (0x4 * 0x10d) +#define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF21 (0x4 * 0x10e) +#define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF22 (0x4 * 0x10f) +#define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF23 (0x4 * 0x110) +#define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF31 (0x4 * 0x111) +#define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF32 (0x4 * 0x112) +#define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400*N)) +#define LCD_LAYER0_CSC_COEFF33 (0x4 * 0x113) +#define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400*N)) +#define LCD_LAYER0_CSC_OFF1 (0x4 * 0x114) +#define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400*N)) +#define LCD_LAYER0_CSC_OFF2 (0x4 * 0x115) +#define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400*N)) +#define LCD_LAYER0_CSC_OFF3 (0x4 * 0x116) +#define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400*N)) +#define LCD_LAYER0_DMA_CFG (0x4 * 0x117) +#define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + (0x400*N)) +#define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) +#define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR + (0x400*N)) +#define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119) +#define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW + (0x400*N)) +#define LCD_LAYER0_DMA_LEN (0x4 * 0x11a) +#define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + (0x400*N)) +#define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b) +#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + (0x400*N)) +#define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c) +#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + (0x400*N)) +#define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d) +#define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + (0x400*N)) +#define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e) +#define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE + (0x400*N)) +#define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f) +#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + (0x400*N)) +#define LCD_LAYER0_CFG2 (0x4 * 0x120) +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) + +#define LCD_LAYER1_CFG (0x4 * 0x200) +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) +#define LCD_LAYER1_COL_START (0x4 * 0x201) +#define LCD_LAYER1_ROW_START (0x4 * 0x202) +#define LCD_LAYER1_WIDTH (0x4 * 0x203) +#define LCD_LAYER1_HEIGHT (0x4 * 0x204) +#define LCD_LAYER1_SCALE_CFG (0x4 * 0x205) +#define LCD_LAYER1_ALPHA (0x4 * 0x206) +#define LCD_LAYER1_INV_COLOUR_LS (0x4 * 0x207) +#define LCD_LAYER1_INV_COLOUR_MS (0x4 * 0x208) +#define LCD_LAYER1_TRANS_COLOUR_LS (0x4 * 0x209) +#define LCD_LAYER1_TRANS_COLOUR_MS (0x4 * 0x20a) +#define LCD_LAYER1_CSC_COEFF11 (0x4 * 0x20b) +#define LCD_LAYER1_CSC_COEFF12 (0x4 * 0x20c) +#define LCD_LAYER1_CSC_COEFF13 (0x4 * 0x20d) +#define LCD_LAYER1_CSC_COEFF21 (0x4 * 0x20e) +#define LCD_LAYER1_CSC_COEFF22 (0x4 * 0x20f) +#define LCD_LAYER1_CSC_COEFF23 (0x4 * 0x210) +#define LCD_LAYER1_CSC_COEFF31 (0x4 * 0x211) +#define LCD_LAYER1_CSC_COEFF32 (0x4 * 0x212) +#define LCD_LAYER1_CSC_COEFF33 (0x4 * 0x213) +#define LCD_LAYER1_CSC_OFF1 (0x4 * 0x214) +#define LCD_LAYER1_CSC_OFF2 (0x4 * 0x215) +#define LCD_LAYER1_CSC_OFF3 (0x4 * 0x216) +#define LCD_LAYER1_DMA_CFG (0x4 * 0x217) +#define LCD_LAYER1_DMA_START_ADR (0x4 * 0x218) +#define LCD_LAYER1_DMA_START_SHADOW (0x4 * 0x219) +#define LCD_LAYER1_DMA_LEN (0x4 * 0x21a) +#define LCD_LAYER1_DMA_LEN_SHADOW (0x4 * 0x21b) +#define LCD_LAYER1_DMA_STATUS (0x4 * 0x21c) +#define LCD_LAYER1_DMA_LINE_WIDTH (0x4 * 0x21d) +#define LCD_LAYER1_DMA_LINE_VSTRIDE (0x4 * 0x21e) +#define LCD_LAYER1_DMA_FIFO_STATUS (0x4 * 0x21f) +#define LCD_LAYER1_CFG2 (0x4 * 0x220) +#define LCD_LAYER2_CFG (0x4 * 0x300) +#define LCD_LAYER2_COL_START (0x4 * 0x301) +#define LCD_LAYER2_ROW_START (0x4 * 0x302) +#define LCD_LAYER2_WIDTH (0x4 * 0x303) +#define LCD_LAYER2_HEIGHT (0x4 * 0x304) +#define LCD_LAYER2_SCALE_CFG (0x4 * 0x305) +#define LCD_LAYER2_ALPHA (0x4 * 0x306) +#define LCD_LAYER2_INV_COLOUR_LS (0x4 * 0x307) +#define LCD_LAYER2_INV_COLOUR_MS (0x4 * 0x308) +#define LCD_LAYER2_TRANS_COLOUR_LS (0x4 * 0x309) +#define LCD_LAYER2_TRANS_COLOUR_MS (0x4 * 0x30a) +#define LCD_LAYER2_CSC_COEFF11 (0x4 * 0x30b) +#define LCD_LAYER2_CSC_COEFF12 (0x4 * 0x30c) +#define LCD_LAYER2_CSC_COEFF13 (0x4 * 0x30d) +#define LCD_LAYER2_CSC_COEFF21 (0x4 * 0x30e) +#define LCD_LAYER2_CSC_COEFF22 (0x4 * 0x30f) +#define LCD_LAYER2_CSC_COEFF23 (0x4 * 0x310) +#define LCD_LAYER2_CSC_COEFF31 (0x4 * 0x311) +#define LCD_LAYER2_CSC_COEFF32 (0x4 * 0x312) +#define LCD_LAYER2_CSC_COEFF33 (0x4 * 0x313) +#define LCD_LAYER2_CSC_OFF1 (0x4 * 0x314) +#define LCD_LAYER2_CSC_OFF2 (0x4 * 0x315) +#define LCD_LAYER2_CSC_OFF3 (0x4 * 0x316) +#define LCD_LAYER2_DMA_CFG (0x4 * 0x317) +#define LCD_LAYER2_DMA_START_ADR (0x4 * 0x318) +#define LCD_LAYER2_DMA_START_SHADOW (0x4 * 0x319) +#define LCD_LAYER2_DMA_LEN (0x4 * 0x31a) +#define LCD_LAYER2_DMA_LEN_SHADOW (0x4 * 0x31b) +#define LCD_LAYER2_DMA_STATUS (0x4 * 0x31c) +#define LCD_LAYER2_DMA_LINE_WIDTH (0x4 * 0x31d) +#define LCD_LAYER2_DMA_LINE_VSTRIDE (0x4 * 0x31e) +#define LCD_LAYER2_DMA_FIFO_STATUS (0x4 * 0x31f) +#define LCD_LAYER2_CFG2 (0x4 * 0x320) +#define LCD_LAYER3_CFG (0x4 * 0x400) +#define LCD_LAYER3_COL_START (0x4 * 0x401) +#define LCD_LAYER3_ROW_START (0x4 * 0x402) +#define LCD_LAYER3_WIDTH (0x4 * 0x403) +#define LCD_LAYER3_HEIGHT (0x4 * 0x404) +#define LCD_LAYER3_SCALE_CFG (0x4 * 0x405) +#define LCD_LAYER3_ALPHA (0x4 * 0x406) +#define LCD_LAYER3_INV_COLOUR_LS (0x4 * 0x407) +#define LCD_LAYER3_INV_COLOUR_MS (0x4 * 0x408) +#define LCD_LAYER3_TRANS_COLOUR_LS (0x4 * 0x409) +#define LCD_LAYER3_TRANS_COLOUR_MS (0x4 * 0x40a) +#define LCD_LAYER3_CSC_COEFF11 (0x4 * 0x40b) +#define LCD_LAYER3_CSC_COEFF12 (0x4 * 0x40c) +#define LCD_LAYER3_CSC_COEFF13 (0x4 * 0x40d) +#define LCD_LAYER3_CSC_COEFF21 (0x4 * 0x40e) +#define LCD_LAYER3_CSC_COEFF22 (0x4 * 0x40f) +#define LCD_LAYER3_CSC_COEFF23 (0x4 * 0x410) +#define LCD_LAYER3_CSC_COEFF31 (0x4 * 0x411) +#define LCD_LAYER3_CSC_COEFF32 (0x4 * 0x412) +#define LCD_LAYER3_CSC_COEFF33 (0x4 * 0x413) +#define LCD_LAYER3_CSC_OFF1 (0x4 * 0x414) +#define LCD_LAYER3_CSC_OFF2 (0x4 * 0x415) +#define LCD_LAYER3_CSC_OFF3 (0x4 * 0x416) +#define LCD_LAYER3_DMA_CFG (0x4 * 0x417) +#define LCD_LAYER3_DMA_START_ADR (0x4 * 0x418) +#define LCD_LAYER3_DMA_START_SHADOW (0x4 * 0x419) +#define LCD_LAYER3_DMA_LEN (0x4 * 0x41a) +#define LCD_LAYER3_DMA_LEN_SHADOW (0x4 * 0x41b) +#define LCD_LAYER3_DMA_STATUS (0x4 * 0x41c) +#define LCD_LAYER3_DMA_LINE_WIDTH (0x4 * 0x41d) +#define LCD_LAYER3_DMA_LINE_VSTRIDE (0x4 * 0x41e) +#define LCD_LAYER3_DMA_FIFO_STATUS (0x4 * 0x41f) +#define LCD_LAYER3_CFG2 (0x4 * 0x420) +#define LCD_LAYER2_CLUT0 (0x4 * 0x500) +#define LCD_LAYER2_CLUT1 (0x4 * 0x501) +#define LCD_LAYER2_CLUT2 (0x4 * 0x502) +#define LCD_LAYER2_CLUT3 (0x4 * 0x503) +#define LCD_LAYER2_CLUT4 (0x4 * 0x504) +#define LCD_LAYER2_CLUT5 (0x4 * 0x505) +#define LCD_LAYER2_CLUT6 (0x4 * 0x506) +#define LCD_LAYER2_CLUT7 (0x4 * 0x507) +#define LCD_LAYER2_CLUT8 (0x4 * 0x508) +#define LCD_LAYER2_CLUT9 (0x4 * 0x509) +#define LCD_LAYER2_CLUT10 (0x4 * 0x50a) +#define LCD_LAYER2_CLUT11 (0x4 * 0x50b) +#define LCD_LAYER2_CLUT12 (0x4 * 0x50c) +#define LCD_LAYER2_CLUT13 (0x4 * 0x50d) +#define LCD_LAYER2_CLUT14 (0x4 * 0x50e) +#define LCD_LAYER2_CLUT15 (0x4 * 0x50f) +#define LCD_LAYER3_CLUT0 (0x4 * 0x600) +#define LCD_LAYER3_CLUT1 (0x4 * 0x601) +#define LCD_LAYER3_CLUT2 (0x4 * 0x602) +#define LCD_LAYER3_CLUT3 (0x4 * 0x603) +#define LCD_LAYER3_CLUT4 (0x4 * 0x604) +#define LCD_LAYER3_CLUT5 (0x4 * 0x605) +#define LCD_LAYER3_CLUT6 (0x4 * 0x606) +#define LCD_LAYER3_CLUT7 (0x4 * 0x607) +#define LCD_LAYER3_CLUT8 (0x4 * 0x608) +#define LCD_LAYER3_CLUT9 (0x4 * 0x609) +#define LCD_LAYER3_CLUT10 (0x4 * 0x60a) +#define LCD_LAYER3_CLUT11 (0x4 * 0x60b) +#define LCD_LAYER3_CLUT12 (0x4 * 0x60c) +#define LCD_LAYER3_CLUT13 (0x4 * 0x60d) +#define LCD_LAYER3_CLUT14 (0x4 * 0x60e) +#define LCD_LAYER3_CLUT15 (0x4 * 0x60f) +#define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) +#define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) +#define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) +#define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) +#define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) +#define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) +#define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) +#define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) +#define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) +#define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) +#define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) +#define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b) +#define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c) +#define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d) +#define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e) +#define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f) +#define LCD_OUT_FORMAT_CFG (0x4 * 0x800) +#define LCD_HSYNC_WIDTH (0x4 * 0x801) +#define LCD_H_BACKPORCH (0x4 * 0x802) +#define LCD_H_ACTIVEWIDTH (0x4 * 0x803) +#define LCD_H_FRONTPORCH (0x4 * 0x804) +#define LCD_VSYNC_WIDTH (0x4 * 0x805) +#define LCD_V_BACKPORCH (0x4 * 0x806) +#define LCD_V_ACTIVEHEIGHT (0x4 * 0x807) +#define LCD_V_FRONTPORCH (0x4 * 0x808) +#define LCD_VSYNC_START (0x4 * 0x809) +#define LCD_VSYNC_END (0x4 * 0x80a) +#define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b) +#define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c) +#define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d) +#define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e) +#define LCD_VSYNC_START_EVEN (0x4 * 0x80f) +#define LCD_VSYNC_END_EVEN (0x4 * 0x810) +#define LCD_TIMING_GEN_TRIG (0x4 * 0x811) +#define LCD_PWM0_CTRL (0x4 * 0x812) +#define LCD_PWM0_RPT_LEADIN (0x4 * 0x813) +#define LCD_PWM0_HIGH_LOW (0x4 * 0x814) +#define LCD_PWM1_CTRL (0x4 * 0x815) +#define LCD_PWM1_RPT_LEADIN (0x4 * 0x816) +#define LCD_PWM1_HIGH_LOW (0x4 * 0x817) +#define LCD_PWM2_CTRL (0x4 * 0x818) +#define LCD_PWM2_RPT_LEADIN (0x4 * 0x819) +#define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) +#define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) +#define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) +#define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) +#define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) +#define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) +#define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05) +#define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06) +#define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07) +#define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08) +#define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09) +#define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a) +#define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b) +#define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c) +#define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d) +#define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) +#define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f) + +#define LAYER3_DMA_FIFO_UNDERFLOW_BIT (1<<26) +#define LAYER3_DMA_OVERFLOW_BIT (1<<25) +#define LAYER3_DMA_IDLE_BIT (1<<24) +#define LAYER3_DMA_DONE_BIT (1<<23) + +#define LAYER2_DMA_FIFO_UNDERFLOW_BIT (1<<22) +#define LAYER2_DMA_OVERFLOW_BIT (1<<21) +#define LAYER2_DMA_IDLE_BIT (1<<20) +#define LAYER2_DMA_DONE_BIT (1<<19) + +#define LAYER1_DMA_CR_FIFO_UNDERFLOW_BIT (1<<18) +#define LAYER1_DMA_CR_FIFO_OVERFLOW_BIT (1<<17) +#define LAYER1_DMA_CB_FIFO_UNDERFLOW_BIT (1<<16) +#define LAYER1_DMA_CB_FIFO_OVERFLOW_BIT (1<<15) + +#define LAYER1_DMA_FIFO_UNDERFLOW_BIT (1<<14) +#define LAYER1_DMA_OVERFLOW_BIT (1<<13) +#define LAYER1_DMA_IDLE_BIT (1<<12) +#define LAYER1_DMA_DONE_BIT (1<<11) + +#define LAYER0_DMA_CR_FIFO_UNDERFLOW_BIT (1<<10) +#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9) +#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8) +#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7) + +#define LAYER0_DMA_FIFO_UNDEFLOW_BIT (1<<6) +#define LAYER0_DMA_OVERFLOW_BIT (1<<5) +#define LAYER0_DMA_IDLE_BIT (1<<4) +#define LAYER0_DMA_DONE_BIT (1<<3) + +#define BLT_VIDEOn_DMAm_STATE 0x00 +#define BLT_VIDEOn_DMAm_BYTES 0x00 +#define BLT_RAM_CFG 0x00 + +#define BLT_LAYERn_WIDTH(N) (0x40C + (0x400*N)) +#define BLT_LAYERn_HEIGHT_OFFSET(N) (0x410 + (0x400*N)) + +#define BLT_LAYERn_TRANS_COLOUR_MS 0x0 +#define BLT_LAYERn_TRANS_COLOUR_LS 0x0 +#define BLT_LAYERn_SCALE_CFG 0x0 +#define BLT_LAYERn_ROW_START 0x0 +#define BLT_LAYERn_INV_COLOUR_MS 0x0 +#define BLT_LAYERn_INV_COLOUR_LS 0x0 + +/* LCD controller Layer DMA config register */ + +/* bit 0 default is disabled */ +#define LCD_DMA_LAYER_ENABLE (0x001) +/* bit 1 this should be used only as a mask when reading the status from + * the DMA CFG register + */ +#define LCD_DMA_LAYER_STATUS (0x002) +/* bit 2 */ +#define LCD_DMA_LAYER_AUTO_UPDATE (0x004) +/* bit 3 */ +#define LCD_DMA_LAYER_CONT_UPDATE (0x008) +/* bit 2 + bit 3 */ +#define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (0x00C) +/* bit 4 set FIFO addressing mode, default is increment after each burst */ +#define LCD_DMA_LAYER_FIFO_ADR_MODE (0x010) +/* bit 5:9 default axi burst is 1 */ +#define LCD_DMA_LAYER_AXI_BURST_1 (0x020) +#define LCD_DMA_LAYER_AXI_BURST_2 (0x040) +#define LCD_DMA_LAYER_AXI_BURST_3 (0x060) +#define LCD_DMA_LAYER_AXI_BURST_4 (0x080) +#define LCD_DMA_LAYER_AXI_BURST_5 (0x0A0) +#define LCD_DMA_LAYER_AXI_BURST_6 (0x0C0) +#define LCD_DMA_LAYER_AXI_BURST_7 (0x0E0) +#define LCD_DMA_LAYER_AXI_BURST_8 (0x100) +#define LCD_DMA_LAYER_AXI_BURST_9 (0x120) +#define LCD_DMA_LAYER_AXI_BURST_10 (0x140) +#define LCD_DMA_LAYER_AXI_BURST_11 (0x160) +#define LCD_DMA_LAYER_AXI_BURST_12 (0x180) +#define LCD_DMA_LAYER_AXI_BURST_13 (0x1A0) +#define LCD_DMA_LAYER_AXI_BURST_14 (0x1C0) +#define LCD_DMA_LAYER_AXI_BURST_15 (0x1E0) +#define LCD_DMA_LAYER_AXI_BURST_16 (0x200) +/* bit 10 */ +#define LCD_DMA_LAYER_V_STRIDE_EN (0x400) + +/* ************************************************************************** + * LCD controller control register defines + **************************************************************************** + */ +/* --- bit 0 */ +#define LCD_CTRL_PROGRESSIVE (0x00) /* default */ +#define LCD_CTRL_INTERLACED (0x01) +/* --- bit 1 */ +#define LCD_CTRL_ENABLE (0x02) /* enable conrtoller */ +/* --- bits 2,3,4,5 */ +#define LCD_CTRL_VL1_ENABLE (0x04) /* enable video layer 1 */ +#define LCD_CTRL_VL2_ENABLE (0x08) /* enable video layer 2 */ +#define LCD_CTRL_GL1_ENABLE (0x10) /* enable graphics layer 1 */ +#define LCD_CTRL_GL2_ENABLE (0x20) /* enable graphics layer 2 */ +/* --- bits 6:7 */ +#define LCD_CTRL_ALPHA_BLEND_VL1 (0x00) /* video layer 1 - default */ +#define LCD_CTRL_ALPHA_BLEND_VL2 (0x40) /* video layer 2 */ +#define LCD_CTRL_ALPHA_BLEND_GL1 (0x80) /* graphics layer 1 */ +#define LCD_CTRL_ALPHA_BLEND_GL2 (0xC0) /* graphics layer 2 */ +/* --- bits 8:9 */ +#define LCD_CTRL_ALPHA_TOP_VL1 (0x000) /* video layer 1 - default */ +#define LCD_CTRL_ALPHA_TOP_VL2 (0x100) /* video layer 2 */ +#define LCD_CTRL_ALPHA_TOP_GL1 (0x200) /* graphics layer 1 */ +#define LCD_CTRL_ALPHA_TOP_GL2 (0x300) /* graphics layer 2 */ +/* --- bits 10:11 */ +#define LCD_CTRL_ALPHA_MIDDLE_VL1 (0x000) /* video layer 1 - default */ +#define LCD_CTRL_ALPHA_MIDDLE_VL2 (0x400) /* video layer 2 */ +#define LCD_CTRL_ALPHA_MIDDLE_GL1 (0x800) /* graphics layer 1 */ +#define LCD_CTRL_ALPHA_MIDDLE_GL2 (0xC00) /* graphics layer 2 */ +/* --- bits 12:13 */ +#define LCD_CTRL_ALPHA_BOTTOM_VL1 (0x0000) /* video layer 1 */ +#define LCD_CTRL_ALPHA_BOTTOM_VL2 (0x1000) /* video layer 2 */ +#define LCD_CTRL_ALPHA_BOTTOM_GL1 (0x2000) /* graphics layer 1 */ +#define LCD_CTRL_ALPHA_BOTTOM_GL2 (0x3000) /* graphics layer 2 */ +/* --- bit 14 */ +#define LCD_CTRL_TIM_GEN_ENABLE (0x4000) /* timing generator */ +/* --- bit 15 */ +#define LCD_CTRL_DISPLAY_MODE_ONE_SHOT (0x8000) /* default continuous */ +/* --- bits 16, 17, 18 */ +#define LCD_CTRL_PWM0_EN (0x10000) /* enable PWM 0 */ +#define LCD_CTRL_PWM1_EN (0x20000) /* enable PWM 1 */ +#define LCD_CTRL_PWM2_EN (0x40000) /* enable PWM 2 */ +/* --- bits 19:20 */ +#define LCD_CTRL_OUTPUT_DISABLED (0x000000) /* output disabled */ +#define LCD_CTRL_OUTPUT_ENABLED (0x080000) +/* --- bit 21 */ +#define LCD_CTRL_SHARP_TFT (0x200000) +/* = bit 21 VSYNC BACK PORCH LEVEL */ +#define LCD_CTRL_BPORCH_ENABLE (0x00200000) +/* = bit 22 VSYNC FRONT PORCH LEVEL */ +#define LCD_CTRL_FPORCH_ENABLE (0x00400000) +/* = bit 28 enable pipelined (outstanding) DMA reads */ +#define LCD_CTRL_PIPELINE_DMA (0x10000000) + +/* LCD Control register bit fields */ + +#define EIGHT_BITS 8 +#define SIXTEEN_BITS 8 +#define TWENTY_FOUR_BITS 8 +#define THIRT_TWO_BITS 8 + +#define ENABLE 1 +/*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal + * interval interrupt + */ +#define LCD_VSTATUS_VERTICAL_STATUS_MASK 0x60 /* BITS 13 and 14 */ +#define LCD_VSTATUS_COMPARE_VSYNC 0x00 +#define LCD_VSTATUS_COMPARE_BACKPORCH 0x01 +#define LCD_VSTATUS_COMPARE_ACTIVE 0x10 +#define LCD_VSTATUS_COMPARE_FRONT_PORCH 0x11 + +/*interrupt bits */ +#define LCD_INT_VERT_COMP (1 << 2) +#define LCD_INT_LINE_CMP (1 << 1) +#define LCD_INT_EOF (1 << 0) + +#endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:14 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:14 -0700 Subject: [Intel-gfx] [PATCH 02/59] drm/kmb: Added id to kmb_plane In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-3-git-send-email-anitha.chrisanthus@intel.com> This is to keep track of the id of the plane as there are 4 planes in Kmb and when update() is called, we need to know which plane need to be updated so that the corresponding plane's registers can be programmed. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 13 ++++--- drivers/gpu/drm/kmb/kmb_crtc.h | 2 +- drivers/gpu/drm/kmb/kmb_drv.h | 2 +- drivers/gpu/drm/kmb/kmb_plane.c | 80 +++++++++++++++++++++++++++-------------- drivers/gpu/drm/kmb/kmb_plane.h | 28 +++++++++------ 5 files changed, 79 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index ab1fff8..6f16410 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -126,9 +126,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write(lcd, LCD_VSYNC_START_EVEN, vsync_start_offset); kmb_write(lcd, LCD_VSYNC_END_EVEN, vsync_end_offset); } - /* enable all 4 layers */ - ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE - | LCD_CTRL_VL2_ENABLE | LCD_CTRL_GL1_ENABLE | LCD_CTRL_GL2_ENABLE; + /* enable VL1 layer as default */ + ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE; ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE | LCD_CTRL_OUTPUT_ENABLED; kmb_write(lcd, LCD_CONTROL, ctrl); @@ -196,17 +195,17 @@ static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = { int kmb_setup_crtc(struct drm_device *drm) { struct kmb_drm_private *lcd = drm->dev_private; - struct drm_plane *primary; + struct kmb_plane *primary; int ret; primary = kmb_plane_init(drm); if (IS_ERR(primary)) return PTR_ERR(primary); - ret = drm_crtc_init_with_planes(drm, &lcd->crtc, primary, NULL, - &kmb_crtc_funcs, NULL); + ret = drm_crtc_init_with_planes(drm, &lcd->crtc, &primary->base_plane, + NULL, &kmb_crtc_funcs, NULL); if (ret) { - kmb_plane_destroy(primary); + kmb_plane_destroy(&primary->base_plane); return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_crtc.h b/drivers/gpu/drm/kmb/kmb_crtc.h index 0952733..5fe8890 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.h +++ b/drivers/gpu/drm/kmb/kmb_crtc.h @@ -55,5 +55,5 @@ struct kmb_crtc_state { #define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) #define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base) extern void kmb_plane_destroy(struct drm_plane *plane); -extern struct drm_plane *kmb_plane_init(struct drm_device *drm); +extern struct kmb_plane *kmb_plane_init(struct drm_device *drm); #endif /* __KMB_CRTC_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 05e9791..637e9a2 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -36,7 +36,7 @@ struct kmb_drm_private { struct clk *clk; struct drm_fbdev_cma *fbdev; struct drm_crtc crtc; - struct drm_plane *plane; + struct kmb_plane *plane; struct drm_atomic_state *state; }; diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 9ab3873..b9d8d38 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -61,46 +61,69 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, dma_addr_t addr; unsigned int width; unsigned int height; - unsigned int i; unsigned int dma_len; - struct kmb_plane_state *kmb_state = to_kmb_plane_state(plane->state); + struct kmb_plane *kmb_plane = to_kmb_plane(plane); unsigned int dma_cfg; + unsigned int ctrl = 0; + unsigned char plane_id = kmb_plane->id; if (!fb) return; lcd = plane->dev->dev_private; + switch (plane_id) { + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; + } + + ctrl |= LCD_CTRL_ENABLE; + ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_OUTPUT_ENABLED; + kmb_write(lcd, LCD_CONTROL, ctrl); + /* TBD */ /*set LCD_LAYERn_WIDTH, LCD_LAYERn_HEIGHT, LCD_LAYERn_COL_START, * LCD_LAYERn_ROW_START, LCD_LAYERn_CFG * CFG should set the pixel format, FIFO level and BPP */ + /*TBD check visible? */ + /* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */ dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1; - for (i = 0; i < kmb_state->no_planes; i++) { - /* disable DMA first */ - kmb_write(lcd, LCD_LAYERn_DMA_CFG(i), ~LCD_DMA_LAYER_ENABLE); + /* disable DMA first */ + kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE); - addr = drm_fb_cma_get_gem_addr(fb, plane->state, i); - kmb_write(lcd, LCD_LAYERn_DMA_START_ADDR(i), addr); - kmb_write(lcd, LCD_LAYERn_DMA_START_SHADOW(i), addr); + addr = drm_fb_cma_get_gem_addr(fb, plane->state, plane_id); + kmb_write(lcd, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); + kmb_write(lcd, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); - width = fb->width; - height = fb->height; - dma_len = width * height * fb->format->cpp[i]; - kmb_write(lcd, LCD_LAYERn_DMA_LEN(i), dma_len); + width = fb->width; + height = fb->height; + dma_len = width * height * fb->format->cpp[plane_id]; + kmb_write(lcd, LCD_LAYERn_DMA_LEN(plane_id), dma_len); - kmb_write(lcd, LCD_LAYERn_DMA_LINE_VSTRIDE(i), fb->pitches[0]); - kmb_write(lcd, LCD_LAYERn_DMA_LINE_WIDTH(i), - (width * fb->format->cpp[i])); + kmb_write(lcd, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[plane_id]); + kmb_write(lcd, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), + (width * fb->format->cpp[plane_id])); + + /* enable DMA */ + kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); - /* enable DMA */ - kmb_write(lcd, LCD_LAYERn_DMA_CFG(i), dma_cfg); - } } static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { @@ -110,7 +133,9 @@ static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { void kmb_plane_destroy(struct drm_plane *plane) { + struct kmb_plane *kmb_plane = to_kmb_plane(plane); drm_plane_cleanup(plane); + kfree(kmb_plane); } static void kmb_destroy_plane_state(struct drm_plane *plane, @@ -205,11 +230,11 @@ static const u32 kmb_formats_v[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV21, }; -struct drm_plane *kmb_plane_init(struct drm_device *drm) +struct kmb_plane *kmb_plane_init(struct drm_device *drm) { struct kmb_drm_private *lcd = drm->dev_private; - struct drm_plane *plane = NULL; - struct drm_plane *primary = NULL; + struct kmb_plane *plane = NULL; + struct kmb_plane *primary = NULL; int i = 0; int ret; enum drm_plane_type plane_type; @@ -233,18 +258,21 @@ struct drm_plane *kmb_plane_init(struct drm_device *drm) num_plane_formats = ARRAY_SIZE(kmb_formats_g); } - ret = drm_universal_plane_init(drm, plane, 0xFF, - &kmb_plane_funcs, plane_formats, - num_plane_formats, - NULL, plane_type, "plane %d", i); + ret = + drm_universal_plane_init(drm, &plane->base_plane, + POSSIBLE_CRTCS, &kmb_plane_funcs, + plane_formats, num_plane_formats, + NULL, plane_type, "plane %d", i); if (ret < 0) goto cleanup; - drm_plane_helper_add(plane, &kmb_plane_helper_funcs); + drm_plane_helper_add(&plane->base_plane, + &kmb_plane_helper_funcs); if (plane_type == DRM_PLANE_TYPE_PRIMARY) { primary = plane; lcd->plane = plane; } + plane->id = i; } cleanup: diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index 84c7113..45bcec1 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -28,25 +28,31 @@ #include "kmb_drv.h" -#define KMB_MAX_PLANES 4 +enum layer_id { + LAYER_0, + LAYER_1, + LAYER_2, + LAYER_3, + KMB_MAX_PLANES, +}; + +struct kmb_plane { + struct drm_plane base_plane; + struct kmb_drm_private kmb_dev; + unsigned char id; +}; -/* this struct may be needed in the future - *struct kmb_plane { - * struct drm_plane base_plane; - * struct kmb_drm_private kmb_dev; - *}; - */ struct kmb_plane_state { struct drm_plane_state base_plane_state; unsigned char no_planes; }; -/* may be needed in the future - *#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) - */ +#define POSSIBLE_CRTCS 1 +#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) + #define to_kmb_plane_state(x) \ container_of(x, struct kmb_plane_state, base_plane_state) -struct drm_plane *kmb_plane_init(struct drm_device *drm); +struct kmb_plane *kmb_plane_init(struct drm_device *drm); void kmb_plane_destroy(struct drm_plane *plane); #endif /* __KMB_PLANE_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:15 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:15 -0700 Subject: [Intel-gfx] [PATCH 03/59] drm/kmb: Set correct values in the LAYERn_CFG register In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-4-git-send-email-anitha.chrisanthus@intel.com> During update plane, set the layer format, bpp, fifo level, RGB order, Cb/Cr order etc. in the LAYER_CFG register. v2: Return val in set_pixel and set_bpp instead of passing in pointer, Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 145 ++++++++++++++++++++++++++++++---- drivers/gpu/drm/kmb/kmb_regs.h | 167 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 298 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index b9d8d38..9f1e44f 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -53,6 +53,119 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, return 0; } +unsigned int set_pixel_format(u32 format) +{ + unsigned int val = 0; + + switch (format) { + /*planar formats */ + case DRM_FORMAT_YUV444: + val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE; + break; + case DRM_FORMAT_YVU444: + val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE + | LCD_LAYER_CRCB_ORDER; + break; + case DRM_FORMAT_YUV422: + val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE; + break; + case DRM_FORMAT_YVU422: + val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE + | LCD_LAYER_CRCB_ORDER; + break; + case DRM_FORMAT_YUV420: + val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE; + break; + case DRM_FORMAT_YVU420: + val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE + | LCD_LAYER_CRCB_ORDER; + break; + case DRM_FORMAT_NV12: + val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE; + break; + case DRM_FORMAT_NV21: + val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE + | LCD_LAYER_CRCB_ORDER; + break; + /* packed formats */ + case DRM_FORMAT_RGB332: + val = LCD_LAYER_FORMAT_RGB332; + break; + case DRM_FORMAT_XBGR4444: + val = LCD_LAYER_FORMAT_RGBX4444 | LCD_LAYER_BGR_ORDER; + break; + case DRM_FORMAT_ARGB4444: + val = LCD_LAYER_FORMAT_RGBA4444; + break; + case DRM_FORMAT_ABGR4444: + val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; + break; + case DRM_FORMAT_XRGB1555: + val = LCD_LAYER_FORMAT_XRGB1555; + break; + case DRM_FORMAT_XBGR1555: + val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; + break; + case DRM_FORMAT_ARGB1555: + val = LCD_LAYER_FORMAT_RGBA1555; + break; + case DRM_FORMAT_ABGR1555: + val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; + break; + case DRM_FORMAT_RGB565: + val = LCD_LAYER_FORMAT_RGB565; + break; + case DRM_FORMAT_BGR565: + val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; + break; + case DRM_FORMAT_RGB888: + val = LCD_LAYER_FORMAT_RGB888; + break; + case DRM_FORMAT_BGR888: + val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; + break; + case DRM_FORMAT_XRGB8888: + val = LCD_LAYER_FORMAT_RGBX8888; + break; + case DRM_FORMAT_XBGR8888: + val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; + break; + case DRM_FORMAT_ARGB8888: + val = LCD_LAYER_FORMAT_RGBA8888; + break; + case DRM_FORMAT_ABGR8888: + val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; + break; + } + return val; +} + +unsigned int set_bits_per_pixel(const struct drm_format_info *format) +{ + int i; + u32 bpp = 0; + unsigned int val = 0; + + for (i = 0; i < format->num_planes; i++) + bpp += 8*format->cpp[i]; + + switch (bpp) { + case 8: + val = LCD_LAYER_8BPP; + break; + case 16: + val = LCD_LAYER_16BPP; + break; + case 24: + val = LCD_LAYER_24BPP; + break; + case 32: + val = LCD_LAYER_32BPP; + break; + } + return val; +} + static void kmb_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *state) { @@ -64,7 +177,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned int dma_len; struct kmb_plane *kmb_plane = to_kmb_plane(plane); unsigned int dma_cfg; - unsigned int ctrl = 0; + unsigned int ctrl = 0, val = 0; + unsigned int src_w, src_h, crtc_x, crtc_y; unsigned char plane_id = kmb_plane->id; if (!fb) @@ -72,6 +186,22 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, lcd = plane->dev->dev_private; + src_w = plane->state->src_w >> 16; + src_h = plane->state->src_h >> 16; + crtc_x = plane->state->crtc_x; + crtc_y = plane->state->crtc_y; + + kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w-1); + kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write(lcd, LCD_LAYERn_COL_START(plane_id), crtc_x); + kmb_write(lcd, LCD_LAYERn_ROW_START(plane_id), crtc_y); + + val = set_pixel_format(fb->format->format); + val |= set_bits_per_pixel(fb->format); + /*CHECKME Leon drvr sets it to 50 try this for now */ + val |= LCD_LAYER_FIFO_50; + kmb_write(lcd, LCD_LAYERn_CFG(plane_id), val); + switch (plane_id) { case LAYER_0: ctrl = LCD_CTRL_VL1_ENABLE; @@ -92,12 +222,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, | LCD_CTRL_OUTPUT_ENABLED; kmb_write(lcd, LCD_CONTROL, ctrl); - /* TBD */ - /*set LCD_LAYERn_WIDTH, LCD_LAYERn_HEIGHT, LCD_LAYERn_COL_START, - * LCD_LAYERn_ROW_START, LCD_LAYERn_CFG - * CFG should set the pixel format, FIFO level and BPP - */ - /*TBD check visible? */ /* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */ @@ -202,9 +326,6 @@ static const u32 kmb_formats_g[] = { DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, - DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, - DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, }; /* video layer (0 & 1) formats, packed and planar formats are supported */ @@ -219,11 +340,7 @@ static const u32 kmb_formats_v[] = { DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, - DRM_FORMAT_XRGB2101010, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, - DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, /*planar formats */ - DRM_FORMAT_YUV411, DRM_FORMAT_YVU411, DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 95cf932..9bf2b9f 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -381,6 +381,173 @@ /* bit 10 */ #define LCD_DMA_LAYER_V_STRIDE_EN (0x400) +/****************************************************************************** + * LCD controller Layer config register + ******************************************************************************/ +/* ---bit 1:2 */ +/* enable horizontal scaling,default is + * no scaling + */ +#define LCD_LAYER_SCALE_H (0x0002) +/* enable vertical scaling*/ +#define LCD_LAYER_SCALE_V (0x0004) +/* enable vertical and horizontal + * scaling + */ +#define LCD_LAYER_SCALE_H_V (0x0006) +/* --- bit 3*/ +/* enable CSC, default is bypassed*/ +#define LCD_LAYER_CSC_EN (0x0008) +/* --- bit 4:5*/ +/* use static alpha value for layer, + * default is disabled + */ +#define LCD_LAYER_ALPHA_STATIC (0x10) +/* use embedded value for alpha blending*/ +#define LCD_LAYER_ALPHA_EMBED (0x20) +/* use static alpha and embedded value, + * by multiplication + */ +#define LCD_LAYER_ALPHA_COMBI (0x30) +/* --- bit 6*/ +/* indicates that the RGB values have + * been multiplied with alpha + */ +#define LCD_LAYER_ALPHA_PREMULT (0x40) +/* --- bit 7*/ +#define LCD_LAYER_INVERT_COL (0x80) +/* enable color inversion, + * default is not inverted + */ +/* --- bit 8*/ +/* enable transparency */ +#define LCD_LAYER_TRANSPARENT_EN (0x100) +/* --- bit 9:13*/ +/* default Layer config */ +#define LCD_LAYER_FORMAT_YCBCR444PLAN (0x0000) +#define LCD_LAYER_FORMAT_YCBCR422PLAN (0x0200) +#define LCD_LAYER_FORMAT_YCBCR420PLAN (0x0400) +#define LCD_LAYER_FORMAT_RGB888PLAN (0x0600) +#define LCD_LAYER_FORMAT_YCBCR444LIN (0x0800) +#define LCD_LAYER_FORMAT_YCBCR422LIN (0x0A00) +#define LCD_LAYER_FORMAT_RGB888 (0x0C00) +#define LCD_LAYER_FORMAT_RGBA8888 (0x0E00) +#define LCD_LAYER_FORMAT_RGBX8888 (0x1000) +#define LCD_LAYER_FORMAT_RGB565 (0x1200) +#define LCD_LAYER_FORMAT_RGBA1555 (0x1400) +#define LCD_LAYER_FORMAT_XRGB1555 (0x1600) +#define LCD_LAYER_FORMAT_RGB444 (0x1800) +#define LCD_LAYER_FORMAT_RGBA4444 (0x1A00) +#define LCD_LAYER_FORMAT_RGBX4444 (0x1C00) +#define LCD_LAYER_FORMAT_RGB332 (0x1E00) +#define LCD_LAYER_FORMAT_RGBA3328 (0x2000) +#define LCD_LAYER_FORMAT_RGBX3328 (0x2200) +#define LCD_LAYER_FORMAT_CLUT (0x2400) +#define LCD_LAYER_FORMAT_NV12 (0x3800) +/* --- bit 14*/ +/* planar storege format */ +#define LCD_LAYER_PLANAR_STORAGE (0x4000) +/* --- bit 15:16*/ +#define LCD_LAYER_8BPP (0x00000) +#define LCD_LAYER_16BPP (0x08000) +#define LCD_LAYER_24BPP (0x10000) +#define LCD_LAYER_32BPP (0x18000) +/* --- bit 17*/ +/* Y after CRCb, + * default is Y before crcb + */ +#define LCD_LAYER_Y_ORDER (0x020000) +/* --- bit 18*/ +/* CR before Cb, + * default is CB before Cr + */ +#define LCD_LAYER_CRCB_ORDER (0x040000) +/*--- but 19*/ +/* BGR order, default is RGB */ +#define LCD_LAYER_BGR_ORDER (0x080000) +/* ---bit 20:21*/ +/* 2 entry clut, 1bpp */ +#define LCD_LAYER_LUT_2ENT (0x000000) +/* 4 entry clut, 2bpp */ +#define LCD_LAYER_LUT_4ENT (0x100000) +/* 18 entry clut, 4bpp */ +#define LCD_LAYER_LUT_16ENT (0x200000) +/*--- bit 22:24*/ +/* no flip or rotaton */ +#define LCD_LAYER_NO_FLIP (0x000000) +/* flip vertical */ +#define LCD_LAYER_FLIP_V (0x400000) +/* flip horizontal */ +#define LCD_LAYER_FLIP_H (0x800000) +/* rotate right 90 */ +#define LCD_LAYER_ROT_R90 (0xC00000) +/* rotate left 90 */ +#define LCD_LAYER_ROT_L90 (0x1000000) +/* rotate 180 (flip H & V ) */ +#define LCD_LAYER_ROT_180 (0x1400000) +/* --- bit 25:26*/ +/* fifo empty */ +#define LCD_LAYER_FIFO_00 (0x0000000) +/* fifo 25% */ +#define LCD_LAYER_FIFO_25 (0x2000000) +/* fifo 50% */ +#define LCD_LAYER_FIFO_50 (0x4000000) +/* fifo 100% , full */ +#define LCD_LAYER_FIFO_100 (0x6000000) + +/* --- bit 27:29*/ +#define LCD_LAYER_INTERLEAVE_DIS (0x00000000) +#define LCD_LAYER_INTERLEAVE_V (0x08000000) +#define LCD_LAYER_INTERLEAVE_H (0x10000000) +#define LCD_LAYER_INTERLEAVE_CH (0x18000000) +#define LCD_LAYER_INTERLEAVE_V_SUB (0x20000000) +#define LCD_LAYER_INTERLEAVE_H_SUB (0x28000000) +#define LCD_LAYER_INTERLEAVE_CH_SUB (0x30000000) +/*bit 30*/ +#define LCD_LAYER_INTER_POS_EVEN (0x00000000) +#define LCD_LAYER_INTER_POS_ODD (0x40000000) + +/**************************************************************************** + * LCD controller output format register defines + ****************************************************************************/ +/* --- bits 0:4*/ +#define D_LCD_OUTF_FORMAT_RGB121212 (0x00 << 0) +#define D_LCD_OUTF_FORMAT_RGB101010 (0x01 << 0) +#define D_LCD_OUTF_FORMAT_RGB888 (0x02 << 0) +#define D_LCD_OUTF_FORMAT_RGB666 (0x03 << 0) +#define D_LCD_OUTF_FORMAT_RGB565 (0x04 << 0) +#define D_LCD_OUTF_FORMAT_RGB444 (0x05 << 0) +#define D_LCD_OUTF_FORMAT_MRGB121212 (0x10 << 0) +#define D_LCD_OUTF_FORMAT_MRGB101010 (0x11 << 0) +#define D_LCD_OUTF_FORMAT_MRGB888 (0x12 << 0) +#define D_LCD_OUTF_FORMAT_MRGB666 (0x13 << 0) +#define D_LCD_OUTF_FORMAT_MRGB565 (0x14 << 0) +#define D_LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08 << 0) +#define D_LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09 << 0) +#define D_LCD_OUTF_FORMAT_YCBCR420_8B (0x0A << 0) +#define D_LCD_OUTF_FORMAT_YCBCR420_10B (0x0B << 0) +#define D_LCD_OUTF_FORMAT_YCBCR420_12B (0x0C << 0) +#define D_LCD_OUTF_FORMAT_YCBCR422_8B (0x0D << 0) +#define D_LCD_OUTF_FORMAT_YCBCR422_10B (0x0E << 0) +#define D_LCD_OUTF_FORMAT_YCBCR444 (0x0F << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18 << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19 << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E << 0) +#define D_LCD_OUTF_FORMAT_MYCBCR444 (0x1F << 0) +/* --- bit 5*/ +/* default is 0, RGB order */ +#define D_LCD_OUTF_BGR_ORDER (1 << 5) +/* --- bit 6*/ +/* Y after CB/Cr, default is Y before CB/CR */ +#define D_LCD_OUTF_Y_ORDER (1 << 6) +/* --- bit 7*/ +/* Cr before Cb, default is Cb before Cr */ +#define D_LCD_OUTF_CRCB_ORDER (1 << 7) + /* ************************************************************************** * LCD controller control register defines **************************************************************************** -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:16 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:16 -0700 Subject: [Intel-gfx] [PATCH 04/59] drm/kmb: Use biwise operators for register definitions In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-5-git-send-email-anitha.chrisanthus@intel.com> Did some general clean up and organization. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 3 +- drivers/gpu/drm/kmb/kmb_regs.h | 852 +++++++++++++++-------------------------- 2 files changed, 307 insertions(+), 548 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index fced630..ee4e3bd 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -133,8 +133,7 @@ static irqreturn_t kmb_irq(int irq, void *arg) if (status & LCD_INT_VERT_COMP) { /* read VSTATUS */ val = kmb_read(lcd, LCD_VSTATUS); - /* BITS 13 and 14 */ - val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK) >> 12; + val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); switch (val) { case LCD_VSTATUS_COMPARE_VSYNC: case LCD_VSTATUS_COMPARE_BACKPORCH: diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 9bf2b9f..14466b8 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -26,35 +26,181 @@ #ifndef __KMB_REGS_H__ #define __KMB_REGS_H__ -/*LCD CONTROLLER REGISTERS */ -#define LCD_CONTROL (0x4 * 0x000) -#define LCD_INT_STATUS (0x4 * 0x001) -#define LCD_INT_ENABLE (0x4 * 0x002) -#define LCD_INT_CLEAR (0x4 * 0x003) -#define LCD_LINE_COUNT (0x4 * 0x004) -#define LCD_LINE_COMPARE (0x4 * 0x005) -#define LCD_VSTATUS (0x4 * 0x006) -#define LCD_VSTATUS_COMPARE (0x4 * 0x007) -#define LCD_SCREEN_WIDTH (0x4 * 0x008) -#define LCD_SCREEN_HEIGHT (0x4 * 0x009) -#define LCD_FIELD_INT_CFG (0x4 * 0x00a) -#define LCD_FIFO_FLUSH (0x4 * 0x00b) -#define LCD_BG_COLOUR_LS (0x4 * 0x00c) -#define LCD_BG_COLOUR_MS (0x4 * 0x00d) -#define LCD_RAM_CFG (0x4 * 0x00e) +#define ENABLE 1 +/*************************************************************************** + * LCD controller control register defines + ***************************************************************************/ +#define LCD_CONTROL (0x4 * 0x000) +#define LCD_CTRL_PROGRESSIVE (0<<0) +#define LCD_CTRL_INTERLACED (1<<0) +#define LCD_CTRL_ENABLE (1<<1) +#define LCD_CTRL_VL1_ENABLE (1<<2) +#define LCD_CTRL_VL2_ENABLE (1<<3) +#define LCD_CTRL_GL1_ENABLE (1<<4) +#define LCD_CTRL_GL2_ENABLE (1<<5) +#define LCD_CTRL_ALPHA_BLEND_VL1 (0<<6) +#define LCD_CTRL_ALPHA_BLEND_VL2 (1<<6) +#define LCD_CTRL_ALPHA_BLEND_GL1 (2<<6) +#define LCD_CTRL_ALPHA_BLEND_GL2 (3<<6) +#define LCD_CTRL_ALPHA_TOP_VL1 (0<<8) +#define LCD_CTRL_ALPHA_TOP_VL2 (1<<8) +#define LCD_CTRL_ALPHA_TOP_GL1 (2<<8) +#define LCD_CTRL_ALPHA_TOP_GL2 (3<<8) +#define LCD_CTRL_ALPHA_MIDDLE_VL1 (0<<10) +#define LCD_CTRL_ALPHA_MIDDLE_VL2 (1<<10) +#define LCD_CTRL_ALPHA_MIDDLE_GL1 (2<<10) +#define LCD_CTRL_ALPHA_MIDDLE_GL2 (3<<10) +#define LCD_CTRL_ALPHA_BOTTOM_VL1 (0<<12) +#define LCD_CTRL_ALPHA_BOTTOM_VL2 (1<<12) +#define LCD_CTRL_ALPHA_BOTTOM_GL1 (2<<12) +#define LCD_CTRL_ALPHA_BOTTOM_GL2 (3<<12) +#define LCD_CTRL_TIM_GEN_ENABLE (1<<14) +#define LCD_CTRL_DISPLAY_MODE_ONE_SHOT (1<<15) +#define LCD_CTRL_PWM0_EN (1<<16) +#define LCD_CTRL_PWM1_EN (1<<17) +#define LCD_CTRL_PWM2_EN (1<<18) +#define LCD_CTRL_OUTPUT_DISABLED (0<<19) +#define LCD_CTRL_OUTPUT_ENABLED (1<<19) +#define LCD_CTRL_BPORCH_ENABLE (1<<21) +#define LCD_CTRL_FPORCH_ENABLE (1<<22) +#define LCD_CTRL_PIPELINE_DMA (1<<28) + +/*interrupts */ +#define LCD_INT_STATUS (0x4 * 0x001) +#define LCD_INT_EOF (1<<0) +#define LCD_INT_LINE_CMP (1<<1) +#define LCD_INT_VERT_COMP (1<<2) +#define LAYER0_DMA_DONE_BIT (1<<3) +#define LAYER0_DMA_IDLE_BIT (1<<4) +#define LAYER0_DMA_OVERFLOW_BIT (1<<5) +#define LAYER0_DMA_FIFO_UNDEFLOW_BIT (1<<6) +#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7) +#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8) +#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9) +#define LAYER0_DMA_CR_FIFO_UNDERFLOW_BIT (1<<10) +#define LAYER1_DMA_DONE_BIT (1<<11) +#define LAYER1_DMA_IDLE_BIT (1<<12) +#define LAYER1_DMA_OVERFLOW_BIT (1<<13) +#define LAYER1_DMA_FIFO_UNDERFLOW_BIT (1<<14) +#define LAYER1_DMA_CB_FIFO_OVERFLOW_BIT (1<<15) +#define LAYER1_DMA_CB_FIFO_UNDERFLOW_BIT (1<<16) +#define LAYER1_DMA_CR_FIFO_OVERFLOW_BIT (1<<17) +#define LAYER1_DMA_CR_FIFO_UNDERFLOW_BIT (1<<18) +#define LAYER2_DMA_DONE_BIT (1<<19) +#define LAYER2_DMA_IDLE_BIT (1<<20) +#define LAYER2_DMA_OVERFLOW_BIT (1<<21) +#define LAYER2_DMA_FIFO_UNDERFLOW_BIT (1<<22) +#define LAYER3_DMA_DONE_BIT (1<<23) +#define LAYER3_DMA_IDLE_BIT (1<<24) +#define LAYER3_DMA_OVERFLOW_BIT (1<<25) +#define LAYER3_DMA_FIFO_UNDERFLOW_BIT (1<<26) + +#define LCD_INT_ENABLE (0x4 * 0x002) +#define LCD_INT_CLEAR (0x4 * 0x003) +#define LCD_LINE_COUNT (0x4 * 0x004) +#define LCD_LINE_COMPARE (0x4 * 0x005) +#define LCD_VSTATUS (0x4 * 0x006) + +/*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal + * interval interrupt + */ +/* BITS 13 and 14 */ +#define LCD_VSTATUS_COMPARE (0x4 * 0x007) +#define LCD_VSTATUS_VERTICAL_STATUS_MASK (3<<13) +#define LCD_VSTATUS_COMPARE_VSYNC (0<<13) +#define LCD_VSTATUS_COMPARE_BACKPORCH (1<<13) +#define LCD_VSTATUS_COMPARE_ACTIVE (2<<13) +#define LCD_VSTATUS_COMPARE_FRONT_PORCH (3<<13) + +#define LCD_SCREEN_WIDTH (0x4 * 0x008) +#define LCD_SCREEN_HEIGHT (0x4 * 0x009) +#define LCD_FIELD_INT_CFG (0x4 * 0x00a) +#define LCD_FIFO_FLUSH (0x4 * 0x00b) +#define LCD_BG_COLOUR_LS (0x4 * 0x00c) +#define LCD_BG_COLOUR_MS (0x4 * 0x00d) +#define LCD_RAM_CFG (0x4 * 0x00e) + +/**************************************************************************** + * LCD controller Layer config register + **************************************************************************** + */ #define LCD_LAYER0_CFG (0x4 * 0x100) -#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) +#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) +#define LCD_LAYER_SCALE_H (1<<1) +#define LCD_LAYER_SCALE_V (1<<2) +#define LCD_LAYER_SCALE_H_V (LCD_LAYER_SCALE_H | \ + LCD_LAYER_SCALE_V) +#define LCD_LAYER_CSC_EN (1<<3) +#define LCD_LAYER_ALPHA_STATIC (1<<4) +#define LCD_LAYER_ALPHA_EMBED (1<<5) +#define LCD_LAYER_ALPHA_COMBI (LCD_LAYER_ALPHA_STATIC | \ + LCD_LAYER_ALPHA_EMBED) +/* RGB multiplied with alpha */ +#define LCD_LAYER_ALPHA_PREMULT (1<<6) +#define LCD_LAYER_INVERT_COL (1<<7) +#define LCD_LAYER_TRANSPARENT_EN (1<<8) +#define LCD_LAYER_FORMAT_YCBCR444PLAN (0<<9) +#define LCD_LAYER_FORMAT_YCBCR422PLAN (1<<9) +#define LCD_LAYER_FORMAT_YCBCR420PLAN (2<<9) +#define LCD_LAYER_FORMAT_RGB888PLAN (3<<9) +#define LCD_LAYER_FORMAT_YCBCR444LIN (4<<9) +#define LCD_LAYER_FORMAT_YCBCR422LIN (5<<9) +#define LCD_LAYER_FORMAT_RGB888 (6<<9) +#define LCD_LAYER_FORMAT_RGBA8888 (7<<9) +#define LCD_LAYER_FORMAT_RGBX8888 (8<<9) +#define LCD_LAYER_FORMAT_RGB565 (9<<9) +#define LCD_LAYER_FORMAT_RGBA1555 (0xa<<9) +#define LCD_LAYER_FORMAT_XRGB1555 (0xb<<9) +#define LCD_LAYER_FORMAT_RGB444 (0xc<<9) +#define LCD_LAYER_FORMAT_RGBA4444 (0xd<<9) +#define LCD_LAYER_FORMAT_RGBX4444 (0xe<<9) +#define LCD_LAYER_FORMAT_RGB332 (0xf<<9) +#define LCD_LAYER_FORMAT_RGBA3328 (0x10<<9) +#define LCD_LAYER_FORMAT_RGBX3328 (0x11<<9) +#define LCD_LAYER_FORMAT_CLUT (0x12<<9) +#define LCD_LAYER_FORMAT_NV12 (0x1c<<9) +#define LCD_LAYER_PLANAR_STORAGE (1<<14) +#define LCD_LAYER_8BPP (0<<15) +#define LCD_LAYER_16BPP (1<<15) +#define LCD_LAYER_24BPP (2<<15) +#define LCD_LAYER_32BPP (3<<15) +#define LCD_LAYER_Y_ORDER (1<<17) +#define LCD_LAYER_CRCB_ORDER (1<<18) +#define LCD_LAYER_BGR_ORDER (1<<19) +#define LCD_LAYER_LUT_2ENT (0<<20) +#define LCD_LAYER_LUT_4ENT (1<<20) +#define LCD_LAYER_LUT_16ENT (2<<20) +#define LCD_LAYER_NO_FLIP (0<<22) +#define LCD_LAYER_FLIP_V (1<<22) +#define LCD_LAYER_FLIP_H (2<<22) +#define LCD_LAYER_ROT_R90 (3<<22) +#define LCD_LAYER_ROT_L90 (4<<22) +#define LCD_LAYER_ROT_180 (5<<22) +#define LCD_LAYER_FIFO_00 (0<<25) +#define LCD_LAYER_FIFO_25 (1<<25) +#define LCD_LAYER_FIFO_50 (2<<25) +#define LCD_LAYER_FIFO_100 (3<<25) +#define LCD_LAYER_INTERLEAVE_DIS (0<<27) +#define LCD_LAYER_INTERLEAVE_V (1<<27) +#define LCD_LAYER_INTERLEAVE_H (2<<27) +#define LCD_LAYER_INTERLEAVE_CH (3<<27) +#define LCD_LAYER_INTERLEAVE_V_SUB (4<<27) +#define LCD_LAYER_INTERLEAVE_H_SUB (5<<27) +#define LCD_LAYER_INTERLEAVE_CH_SUB (6<<27) +#define LCD_LAYER_INTER_POS_EVEN (0<<30) +#define LCD_LAYER_INTER_POS_ODD (1<<30) + #define LCD_LAYER0_COL_START (0x4 * 0x101) #define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400*N)) #define LCD_LAYER0_ROW_START (0x4 * 0x102) #define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400*N)) -#define LCD_LAYER0_WIDTH (0x4 * 0x103) +#define LCD_LAYER0_WIDTH (0x4 * 0x103) #define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400*N)) #define LCD_LAYER0_HEIGHT (0x4 * 0x104) #define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400*N)) #define LCD_LAYER0_SCALE_CFG (0x4 * 0x105) #define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400*N)) -#define LCD_LAYER0_ALPHA (0x4 * 0x106) +#define LCD_LAYER0_ALPHA (0x4 * 0x106) #define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400*N)) #define LCD_LAYER0_INV_COLOUR_LS (0x4 * 0x107) #define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + (0x400*N)) @@ -88,540 +234,154 @@ #define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400*N)) #define LCD_LAYER0_CSC_OFF3 (0x4 * 0x116) #define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400*N)) -#define LCD_LAYER0_DMA_CFG (0x4 * 0x117) -#define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + (0x400*N)) -#define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) -#define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR + (0x400*N)) -#define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119) -#define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW + (0x400*N)) -#define LCD_LAYER0_DMA_LEN (0x4 * 0x11a) -#define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + (0x400*N)) -#define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b) -#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + (0x400*N)) -#define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c) -#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + (0x400*N)) -#define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d) -#define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + (0x400*N)) -#define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e) -#define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE + (0x400*N)) -#define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f) -#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + (0x400*N)) -#define LCD_LAYER0_CFG2 (0x4 * 0x120) -#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) - -#define LCD_LAYER1_CFG (0x4 * 0x200) -#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) -#define LCD_LAYER1_COL_START (0x4 * 0x201) -#define LCD_LAYER1_ROW_START (0x4 * 0x202) -#define LCD_LAYER1_WIDTH (0x4 * 0x203) -#define LCD_LAYER1_HEIGHT (0x4 * 0x204) -#define LCD_LAYER1_SCALE_CFG (0x4 * 0x205) -#define LCD_LAYER1_ALPHA (0x4 * 0x206) -#define LCD_LAYER1_INV_COLOUR_LS (0x4 * 0x207) -#define LCD_LAYER1_INV_COLOUR_MS (0x4 * 0x208) -#define LCD_LAYER1_TRANS_COLOUR_LS (0x4 * 0x209) -#define LCD_LAYER1_TRANS_COLOUR_MS (0x4 * 0x20a) -#define LCD_LAYER1_CSC_COEFF11 (0x4 * 0x20b) -#define LCD_LAYER1_CSC_COEFF12 (0x4 * 0x20c) -#define LCD_LAYER1_CSC_COEFF13 (0x4 * 0x20d) -#define LCD_LAYER1_CSC_COEFF21 (0x4 * 0x20e) -#define LCD_LAYER1_CSC_COEFF22 (0x4 * 0x20f) -#define LCD_LAYER1_CSC_COEFF23 (0x4 * 0x210) -#define LCD_LAYER1_CSC_COEFF31 (0x4 * 0x211) -#define LCD_LAYER1_CSC_COEFF32 (0x4 * 0x212) -#define LCD_LAYER1_CSC_COEFF33 (0x4 * 0x213) -#define LCD_LAYER1_CSC_OFF1 (0x4 * 0x214) -#define LCD_LAYER1_CSC_OFF2 (0x4 * 0x215) -#define LCD_LAYER1_CSC_OFF3 (0x4 * 0x216) -#define LCD_LAYER1_DMA_CFG (0x4 * 0x217) -#define LCD_LAYER1_DMA_START_ADR (0x4 * 0x218) -#define LCD_LAYER1_DMA_START_SHADOW (0x4 * 0x219) -#define LCD_LAYER1_DMA_LEN (0x4 * 0x21a) -#define LCD_LAYER1_DMA_LEN_SHADOW (0x4 * 0x21b) -#define LCD_LAYER1_DMA_STATUS (0x4 * 0x21c) -#define LCD_LAYER1_DMA_LINE_WIDTH (0x4 * 0x21d) -#define LCD_LAYER1_DMA_LINE_VSTRIDE (0x4 * 0x21e) -#define LCD_LAYER1_DMA_FIFO_STATUS (0x4 * 0x21f) -#define LCD_LAYER1_CFG2 (0x4 * 0x220) -#define LCD_LAYER2_CFG (0x4 * 0x300) -#define LCD_LAYER2_COL_START (0x4 * 0x301) -#define LCD_LAYER2_ROW_START (0x4 * 0x302) -#define LCD_LAYER2_WIDTH (0x4 * 0x303) -#define LCD_LAYER2_HEIGHT (0x4 * 0x304) -#define LCD_LAYER2_SCALE_CFG (0x4 * 0x305) -#define LCD_LAYER2_ALPHA (0x4 * 0x306) -#define LCD_LAYER2_INV_COLOUR_LS (0x4 * 0x307) -#define LCD_LAYER2_INV_COLOUR_MS (0x4 * 0x308) -#define LCD_LAYER2_TRANS_COLOUR_LS (0x4 * 0x309) -#define LCD_LAYER2_TRANS_COLOUR_MS (0x4 * 0x30a) -#define LCD_LAYER2_CSC_COEFF11 (0x4 * 0x30b) -#define LCD_LAYER2_CSC_COEFF12 (0x4 * 0x30c) -#define LCD_LAYER2_CSC_COEFF13 (0x4 * 0x30d) -#define LCD_LAYER2_CSC_COEFF21 (0x4 * 0x30e) -#define LCD_LAYER2_CSC_COEFF22 (0x4 * 0x30f) -#define LCD_LAYER2_CSC_COEFF23 (0x4 * 0x310) -#define LCD_LAYER2_CSC_COEFF31 (0x4 * 0x311) -#define LCD_LAYER2_CSC_COEFF32 (0x4 * 0x312) -#define LCD_LAYER2_CSC_COEFF33 (0x4 * 0x313) -#define LCD_LAYER2_CSC_OFF1 (0x4 * 0x314) -#define LCD_LAYER2_CSC_OFF2 (0x4 * 0x315) -#define LCD_LAYER2_CSC_OFF3 (0x4 * 0x316) -#define LCD_LAYER2_DMA_CFG (0x4 * 0x317) -#define LCD_LAYER2_DMA_START_ADR (0x4 * 0x318) -#define LCD_LAYER2_DMA_START_SHADOW (0x4 * 0x319) -#define LCD_LAYER2_DMA_LEN (0x4 * 0x31a) -#define LCD_LAYER2_DMA_LEN_SHADOW (0x4 * 0x31b) -#define LCD_LAYER2_DMA_STATUS (0x4 * 0x31c) -#define LCD_LAYER2_DMA_LINE_WIDTH (0x4 * 0x31d) -#define LCD_LAYER2_DMA_LINE_VSTRIDE (0x4 * 0x31e) -#define LCD_LAYER2_DMA_FIFO_STATUS (0x4 * 0x31f) -#define LCD_LAYER2_CFG2 (0x4 * 0x320) -#define LCD_LAYER3_CFG (0x4 * 0x400) -#define LCD_LAYER3_COL_START (0x4 * 0x401) -#define LCD_LAYER3_ROW_START (0x4 * 0x402) -#define LCD_LAYER3_WIDTH (0x4 * 0x403) -#define LCD_LAYER3_HEIGHT (0x4 * 0x404) -#define LCD_LAYER3_SCALE_CFG (0x4 * 0x405) -#define LCD_LAYER3_ALPHA (0x4 * 0x406) -#define LCD_LAYER3_INV_COLOUR_LS (0x4 * 0x407) -#define LCD_LAYER3_INV_COLOUR_MS (0x4 * 0x408) -#define LCD_LAYER3_TRANS_COLOUR_LS (0x4 * 0x409) -#define LCD_LAYER3_TRANS_COLOUR_MS (0x4 * 0x40a) -#define LCD_LAYER3_CSC_COEFF11 (0x4 * 0x40b) -#define LCD_LAYER3_CSC_COEFF12 (0x4 * 0x40c) -#define LCD_LAYER3_CSC_COEFF13 (0x4 * 0x40d) -#define LCD_LAYER3_CSC_COEFF21 (0x4 * 0x40e) -#define LCD_LAYER3_CSC_COEFF22 (0x4 * 0x40f) -#define LCD_LAYER3_CSC_COEFF23 (0x4 * 0x410) -#define LCD_LAYER3_CSC_COEFF31 (0x4 * 0x411) -#define LCD_LAYER3_CSC_COEFF32 (0x4 * 0x412) -#define LCD_LAYER3_CSC_COEFF33 (0x4 * 0x413) -#define LCD_LAYER3_CSC_OFF1 (0x4 * 0x414) -#define LCD_LAYER3_CSC_OFF2 (0x4 * 0x415) -#define LCD_LAYER3_CSC_OFF3 (0x4 * 0x416) -#define LCD_LAYER3_DMA_CFG (0x4 * 0x417) -#define LCD_LAYER3_DMA_START_ADR (0x4 * 0x418) -#define LCD_LAYER3_DMA_START_SHADOW (0x4 * 0x419) -#define LCD_LAYER3_DMA_LEN (0x4 * 0x41a) -#define LCD_LAYER3_DMA_LEN_SHADOW (0x4 * 0x41b) -#define LCD_LAYER3_DMA_STATUS (0x4 * 0x41c) -#define LCD_LAYER3_DMA_LINE_WIDTH (0x4 * 0x41d) -#define LCD_LAYER3_DMA_LINE_VSTRIDE (0x4 * 0x41e) -#define LCD_LAYER3_DMA_FIFO_STATUS (0x4 * 0x41f) -#define LCD_LAYER3_CFG2 (0x4 * 0x420) -#define LCD_LAYER2_CLUT0 (0x4 * 0x500) -#define LCD_LAYER2_CLUT1 (0x4 * 0x501) -#define LCD_LAYER2_CLUT2 (0x4 * 0x502) -#define LCD_LAYER2_CLUT3 (0x4 * 0x503) -#define LCD_LAYER2_CLUT4 (0x4 * 0x504) -#define LCD_LAYER2_CLUT5 (0x4 * 0x505) -#define LCD_LAYER2_CLUT6 (0x4 * 0x506) -#define LCD_LAYER2_CLUT7 (0x4 * 0x507) -#define LCD_LAYER2_CLUT8 (0x4 * 0x508) -#define LCD_LAYER2_CLUT9 (0x4 * 0x509) -#define LCD_LAYER2_CLUT10 (0x4 * 0x50a) -#define LCD_LAYER2_CLUT11 (0x4 * 0x50b) -#define LCD_LAYER2_CLUT12 (0x4 * 0x50c) -#define LCD_LAYER2_CLUT13 (0x4 * 0x50d) -#define LCD_LAYER2_CLUT14 (0x4 * 0x50e) -#define LCD_LAYER2_CLUT15 (0x4 * 0x50f) -#define LCD_LAYER3_CLUT0 (0x4 * 0x600) -#define LCD_LAYER3_CLUT1 (0x4 * 0x601) -#define LCD_LAYER3_CLUT2 (0x4 * 0x602) -#define LCD_LAYER3_CLUT3 (0x4 * 0x603) -#define LCD_LAYER3_CLUT4 (0x4 * 0x604) -#define LCD_LAYER3_CLUT5 (0x4 * 0x605) -#define LCD_LAYER3_CLUT6 (0x4 * 0x606) -#define LCD_LAYER3_CLUT7 (0x4 * 0x607) -#define LCD_LAYER3_CLUT8 (0x4 * 0x608) -#define LCD_LAYER3_CLUT9 (0x4 * 0x609) -#define LCD_LAYER3_CLUT10 (0x4 * 0x60a) -#define LCD_LAYER3_CLUT11 (0x4 * 0x60b) -#define LCD_LAYER3_CLUT12 (0x4 * 0x60c) -#define LCD_LAYER3_CLUT13 (0x4 * 0x60d) -#define LCD_LAYER3_CLUT14 (0x4 * 0x60e) -#define LCD_LAYER3_CLUT15 (0x4 * 0x60f) -#define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) -#define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) -#define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) -#define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) -#define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) -#define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) -#define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) -#define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) -#define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) -#define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) -#define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) -#define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b) -#define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c) -#define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d) -#define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e) -#define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f) -#define LCD_OUT_FORMAT_CFG (0x4 * 0x800) -#define LCD_HSYNC_WIDTH (0x4 * 0x801) -#define LCD_H_BACKPORCH (0x4 * 0x802) -#define LCD_H_ACTIVEWIDTH (0x4 * 0x803) -#define LCD_H_FRONTPORCH (0x4 * 0x804) -#define LCD_VSYNC_WIDTH (0x4 * 0x805) -#define LCD_V_BACKPORCH (0x4 * 0x806) -#define LCD_V_ACTIVEHEIGHT (0x4 * 0x807) -#define LCD_V_FRONTPORCH (0x4 * 0x808) -#define LCD_VSYNC_START (0x4 * 0x809) -#define LCD_VSYNC_END (0x4 * 0x80a) -#define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b) -#define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c) -#define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d) -#define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e) -#define LCD_VSYNC_START_EVEN (0x4 * 0x80f) -#define LCD_VSYNC_END_EVEN (0x4 * 0x810) -#define LCD_TIMING_GEN_TRIG (0x4 * 0x811) -#define LCD_PWM0_CTRL (0x4 * 0x812) -#define LCD_PWM0_RPT_LEADIN (0x4 * 0x813) -#define LCD_PWM0_HIGH_LOW (0x4 * 0x814) -#define LCD_PWM1_CTRL (0x4 * 0x815) -#define LCD_PWM1_RPT_LEADIN (0x4 * 0x816) -#define LCD_PWM1_HIGH_LOW (0x4 * 0x817) -#define LCD_PWM2_CTRL (0x4 * 0x818) -#define LCD_PWM2_RPT_LEADIN (0x4 * 0x819) -#define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) -#define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) -#define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) -#define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) -#define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) -#define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) -#define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05) -#define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06) -#define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07) -#define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08) -#define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09) -#define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a) -#define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b) -#define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c) -#define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d) -#define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) -#define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f) - -#define LAYER3_DMA_FIFO_UNDERFLOW_BIT (1<<26) -#define LAYER3_DMA_OVERFLOW_BIT (1<<25) -#define LAYER3_DMA_IDLE_BIT (1<<24) -#define LAYER3_DMA_DONE_BIT (1<<23) - -#define LAYER2_DMA_FIFO_UNDERFLOW_BIT (1<<22) -#define LAYER2_DMA_OVERFLOW_BIT (1<<21) -#define LAYER2_DMA_IDLE_BIT (1<<20) -#define LAYER2_DMA_DONE_BIT (1<<19) - -#define LAYER1_DMA_CR_FIFO_UNDERFLOW_BIT (1<<18) -#define LAYER1_DMA_CR_FIFO_OVERFLOW_BIT (1<<17) -#define LAYER1_DMA_CB_FIFO_UNDERFLOW_BIT (1<<16) -#define LAYER1_DMA_CB_FIFO_OVERFLOW_BIT (1<<15) - -#define LAYER1_DMA_FIFO_UNDERFLOW_BIT (1<<14) -#define LAYER1_DMA_OVERFLOW_BIT (1<<13) -#define LAYER1_DMA_IDLE_BIT (1<<12) -#define LAYER1_DMA_DONE_BIT (1<<11) - -#define LAYER0_DMA_CR_FIFO_UNDERFLOW_BIT (1<<10) -#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9) -#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8) -#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7) - -#define LAYER0_DMA_FIFO_UNDEFLOW_BIT (1<<6) -#define LAYER0_DMA_OVERFLOW_BIT (1<<5) -#define LAYER0_DMA_IDLE_BIT (1<<4) -#define LAYER0_DMA_DONE_BIT (1<<3) - -#define BLT_VIDEOn_DMAm_STATE 0x00 -#define BLT_VIDEOn_DMAm_BYTES 0x00 -#define BLT_RAM_CFG 0x00 - -#define BLT_LAYERn_WIDTH(N) (0x40C + (0x400*N)) -#define BLT_LAYERn_HEIGHT_OFFSET(N) (0x410 + (0x400*N)) - -#define BLT_LAYERn_TRANS_COLOUR_MS 0x0 -#define BLT_LAYERn_TRANS_COLOUR_LS 0x0 -#define BLT_LAYERn_SCALE_CFG 0x0 -#define BLT_LAYERn_ROW_START 0x0 -#define BLT_LAYERn_INV_COLOUR_MS 0x0 -#define BLT_LAYERn_INV_COLOUR_LS 0x0 /* LCD controller Layer DMA config register */ +#define LCD_LAYER0_DMA_CFG (0x4 * 0x117) +#define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + (0x400*N)) +#define LCD_DMA_LAYER_ENABLE (1<<0) +#define LCD_DMA_LAYER_STATUS (1<<1) +#define LCD_DMA_LAYER_AUTO_UPDATE (1<<2) +#define LCD_DMA_LAYER_CONT_UPDATE (1<<3) +#define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (LCD_DMA_LAYER_AUTO_UPDATE \ + | LCD_DMA_LAYER_CONT_UPDATE) +#define LCD_DMA_LAYER_FIFO_ADR_MODE (1<<4) +#define LCD_DMA_LAYER_AXI_BURST_1 (1<<5) +#define LCD_DMA_LAYER_AXI_BURST_2 (2<<5) +#define LCD_DMA_LAYER_AXI_BURST_3 (3<<5) +#define LCD_DMA_LAYER_AXI_BURST_4 (4<<5) +#define LCD_DMA_LAYER_AXI_BURST_5 (5<<5) +#define LCD_DMA_LAYER_AXI_BURST_6 (6<<5) +#define LCD_DMA_LAYER_AXI_BURST_7 (7<<5) +#define LCD_DMA_LAYER_AXI_BURST_8 (8<<5) +#define LCD_DMA_LAYER_AXI_BURST_9 (9<<5) +#define LCD_DMA_LAYER_AXI_BURST_10 (0xa<<5) +#define LCD_DMA_LAYER_AXI_BURST_11 (0xb<<5) +#define LCD_DMA_LAYER_AXI_BURST_12 (0xc<<5) +#define LCD_DMA_LAYER_AXI_BURST_13 (0xd<<5) +#define LCD_DMA_LAYER_AXI_BURST_14 (0xe<<5) +#define LCD_DMA_LAYER_AXI_BURST_15 (0xf<<5) +#define LCD_DMA_LAYER_AXI_BURST_16 (0x10<<5) +#define LCD_DMA_LAYER_V_STRIDE_EN (1<<10) -/* bit 0 default is disabled */ -#define LCD_DMA_LAYER_ENABLE (0x001) -/* bit 1 this should be used only as a mask when reading the status from - * the DMA CFG register - */ -#define LCD_DMA_LAYER_STATUS (0x002) -/* bit 2 */ -#define LCD_DMA_LAYER_AUTO_UPDATE (0x004) -/* bit 3 */ -#define LCD_DMA_LAYER_CONT_UPDATE (0x008) -/* bit 2 + bit 3 */ -#define LCD_DMA_LAYER_CONT_PING_PONG_UPDATE (0x00C) -/* bit 4 set FIFO addressing mode, default is increment after each burst */ -#define LCD_DMA_LAYER_FIFO_ADR_MODE (0x010) -/* bit 5:9 default axi burst is 1 */ -#define LCD_DMA_LAYER_AXI_BURST_1 (0x020) -#define LCD_DMA_LAYER_AXI_BURST_2 (0x040) -#define LCD_DMA_LAYER_AXI_BURST_3 (0x060) -#define LCD_DMA_LAYER_AXI_BURST_4 (0x080) -#define LCD_DMA_LAYER_AXI_BURST_5 (0x0A0) -#define LCD_DMA_LAYER_AXI_BURST_6 (0x0C0) -#define LCD_DMA_LAYER_AXI_BURST_7 (0x0E0) -#define LCD_DMA_LAYER_AXI_BURST_8 (0x100) -#define LCD_DMA_LAYER_AXI_BURST_9 (0x120) -#define LCD_DMA_LAYER_AXI_BURST_10 (0x140) -#define LCD_DMA_LAYER_AXI_BURST_11 (0x160) -#define LCD_DMA_LAYER_AXI_BURST_12 (0x180) -#define LCD_DMA_LAYER_AXI_BURST_13 (0x1A0) -#define LCD_DMA_LAYER_AXI_BURST_14 (0x1C0) -#define LCD_DMA_LAYER_AXI_BURST_15 (0x1E0) -#define LCD_DMA_LAYER_AXI_BURST_16 (0x200) -/* bit 10 */ -#define LCD_DMA_LAYER_V_STRIDE_EN (0x400) - -/****************************************************************************** - * LCD controller Layer config register - ******************************************************************************/ -/* ---bit 1:2 */ -/* enable horizontal scaling,default is - * no scaling - */ -#define LCD_LAYER_SCALE_H (0x0002) -/* enable vertical scaling*/ -#define LCD_LAYER_SCALE_V (0x0004) -/* enable vertical and horizontal - * scaling - */ -#define LCD_LAYER_SCALE_H_V (0x0006) -/* --- bit 3*/ -/* enable CSC, default is bypassed*/ -#define LCD_LAYER_CSC_EN (0x0008) -/* --- bit 4:5*/ -/* use static alpha value for layer, - * default is disabled - */ -#define LCD_LAYER_ALPHA_STATIC (0x10) -/* use embedded value for alpha blending*/ -#define LCD_LAYER_ALPHA_EMBED (0x20) -/* use static alpha and embedded value, - * by multiplication - */ -#define LCD_LAYER_ALPHA_COMBI (0x30) -/* --- bit 6*/ -/* indicates that the RGB values have - * been multiplied with alpha - */ -#define LCD_LAYER_ALPHA_PREMULT (0x40) -/* --- bit 7*/ -#define LCD_LAYER_INVERT_COL (0x80) -/* enable color inversion, - * default is not inverted - */ -/* --- bit 8*/ -/* enable transparency */ -#define LCD_LAYER_TRANSPARENT_EN (0x100) -/* --- bit 9:13*/ -/* default Layer config */ -#define LCD_LAYER_FORMAT_YCBCR444PLAN (0x0000) -#define LCD_LAYER_FORMAT_YCBCR422PLAN (0x0200) -#define LCD_LAYER_FORMAT_YCBCR420PLAN (0x0400) -#define LCD_LAYER_FORMAT_RGB888PLAN (0x0600) -#define LCD_LAYER_FORMAT_YCBCR444LIN (0x0800) -#define LCD_LAYER_FORMAT_YCBCR422LIN (0x0A00) -#define LCD_LAYER_FORMAT_RGB888 (0x0C00) -#define LCD_LAYER_FORMAT_RGBA8888 (0x0E00) -#define LCD_LAYER_FORMAT_RGBX8888 (0x1000) -#define LCD_LAYER_FORMAT_RGB565 (0x1200) -#define LCD_LAYER_FORMAT_RGBA1555 (0x1400) -#define LCD_LAYER_FORMAT_XRGB1555 (0x1600) -#define LCD_LAYER_FORMAT_RGB444 (0x1800) -#define LCD_LAYER_FORMAT_RGBA4444 (0x1A00) -#define LCD_LAYER_FORMAT_RGBX4444 (0x1C00) -#define LCD_LAYER_FORMAT_RGB332 (0x1E00) -#define LCD_LAYER_FORMAT_RGBA3328 (0x2000) -#define LCD_LAYER_FORMAT_RGBX3328 (0x2200) -#define LCD_LAYER_FORMAT_CLUT (0x2400) -#define LCD_LAYER_FORMAT_NV12 (0x3800) -/* --- bit 14*/ -/* planar storege format */ -#define LCD_LAYER_PLANAR_STORAGE (0x4000) -/* --- bit 15:16*/ -#define LCD_LAYER_8BPP (0x00000) -#define LCD_LAYER_16BPP (0x08000) -#define LCD_LAYER_24BPP (0x10000) -#define LCD_LAYER_32BPP (0x18000) -/* --- bit 17*/ -/* Y after CRCb, - * default is Y before crcb - */ -#define LCD_LAYER_Y_ORDER (0x020000) -/* --- bit 18*/ -/* CR before Cb, - * default is CB before Cr - */ -#define LCD_LAYER_CRCB_ORDER (0x040000) -/*--- but 19*/ -/* BGR order, default is RGB */ -#define LCD_LAYER_BGR_ORDER (0x080000) -/* ---bit 20:21*/ -/* 2 entry clut, 1bpp */ -#define LCD_LAYER_LUT_2ENT (0x000000) -/* 4 entry clut, 2bpp */ -#define LCD_LAYER_LUT_4ENT (0x100000) -/* 18 entry clut, 4bpp */ -#define LCD_LAYER_LUT_16ENT (0x200000) -/*--- bit 22:24*/ -/* no flip or rotaton */ -#define LCD_LAYER_NO_FLIP (0x000000) -/* flip vertical */ -#define LCD_LAYER_FLIP_V (0x400000) -/* flip horizontal */ -#define LCD_LAYER_FLIP_H (0x800000) -/* rotate right 90 */ -#define LCD_LAYER_ROT_R90 (0xC00000) -/* rotate left 90 */ -#define LCD_LAYER_ROT_L90 (0x1000000) -/* rotate 180 (flip H & V ) */ -#define LCD_LAYER_ROT_180 (0x1400000) -/* --- bit 25:26*/ -/* fifo empty */ -#define LCD_LAYER_FIFO_00 (0x0000000) -/* fifo 25% */ -#define LCD_LAYER_FIFO_25 (0x2000000) -/* fifo 50% */ -#define LCD_LAYER_FIFO_50 (0x4000000) -/* fifo 100% , full */ -#define LCD_LAYER_FIFO_100 (0x6000000) - -/* --- bit 27:29*/ -#define LCD_LAYER_INTERLEAVE_DIS (0x00000000) -#define LCD_LAYER_INTERLEAVE_V (0x08000000) -#define LCD_LAYER_INTERLEAVE_H (0x10000000) -#define LCD_LAYER_INTERLEAVE_CH (0x18000000) -#define LCD_LAYER_INTERLEAVE_V_SUB (0x20000000) -#define LCD_LAYER_INTERLEAVE_H_SUB (0x28000000) -#define LCD_LAYER_INTERLEAVE_CH_SUB (0x30000000) -/*bit 30*/ -#define LCD_LAYER_INTER_POS_EVEN (0x00000000) -#define LCD_LAYER_INTER_POS_ODD (0x40000000) +#define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) +#define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR \ + + (0x400*N)) +#define LCD_LAYER0_DMA_START_SHADOW (0x4 * 0x119) +#define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW \ + + (0x400*N)) +#define LCD_LAYER0_DMA_LEN (0x4 * 0x11a) +#define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + \ + (0x400*N)) +#define LCD_LAYER0_DMA_LEN_SHADOW (0x4 * 0x11b) +#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + \ + (0x400*N)) +#define LCD_LAYER0_DMA_STATUS (0x4 * 0x11c) +#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + \ + (0x400*N)) +#define LCD_LAYER0_DMA_LINE_WIDTH (0x4 * 0x11d) +#define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + \ + (0x400*N)) +#define LCD_LAYER0_DMA_LINE_VSTRIDE (0x4 * 0x11e) +#define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE +\ + (0x400*N)) +#define LCD_LAYER0_DMA_FIFO_STATUS (0x4 * 0x11f) +#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + \ + (0x400*N)) +#define LCD_LAYER0_CFG2 (0x4 * 0x120) +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) +#define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) +#define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) +#define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) +#define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) +#define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) +#define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) +#define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) +#define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) +#define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) +#define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) +#define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) +#define LCD_LAYER1_DMA_CB_LINE_VSTRIDE (0x4 * 0x70b) +#define LCD_LAYER1_DMA_START_CR_ADR (0x4 * 0x70c) +#define LCD_LAYER1_DMA_START_CR_SHADOW (0x4 * 0x70d) +#define LCD_LAYER1_DMA_CR_LINE_WIDTH (0x4 * 0x70e) +#define LCD_LAYER1_DMA_CR_LINE_VSTRIDE (0x4 * 0x70f) /**************************************************************************** * LCD controller output format register defines ****************************************************************************/ -/* --- bits 0:4*/ -#define D_LCD_OUTF_FORMAT_RGB121212 (0x00 << 0) -#define D_LCD_OUTF_FORMAT_RGB101010 (0x01 << 0) -#define D_LCD_OUTF_FORMAT_RGB888 (0x02 << 0) -#define D_LCD_OUTF_FORMAT_RGB666 (0x03 << 0) -#define D_LCD_OUTF_FORMAT_RGB565 (0x04 << 0) -#define D_LCD_OUTF_FORMAT_RGB444 (0x05 << 0) -#define D_LCD_OUTF_FORMAT_MRGB121212 (0x10 << 0) -#define D_LCD_OUTF_FORMAT_MRGB101010 (0x11 << 0) -#define D_LCD_OUTF_FORMAT_MRGB888 (0x12 << 0) -#define D_LCD_OUTF_FORMAT_MRGB666 (0x13 << 0) -#define D_LCD_OUTF_FORMAT_MRGB565 (0x14 << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08 << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09 << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_8B (0x0A << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_10B (0x0B << 0) -#define D_LCD_OUTF_FORMAT_YCBCR420_12B (0x0C << 0) -#define D_LCD_OUTF_FORMAT_YCBCR422_8B (0x0D << 0) -#define D_LCD_OUTF_FORMAT_YCBCR422_10B (0x0E << 0) -#define D_LCD_OUTF_FORMAT_YCBCR444 (0x0F << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18 << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19 << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E << 0) -#define D_LCD_OUTF_FORMAT_MYCBCR444 (0x1F << 0) -/* --- bit 5*/ -/* default is 0, RGB order */ -#define D_LCD_OUTF_BGR_ORDER (1 << 5) -/* --- bit 6*/ -/* Y after CB/Cr, default is Y before CB/CR */ -#define D_LCD_OUTF_Y_ORDER (1 << 6) -/* --- bit 7*/ -/* Cr before Cb, default is Cb before Cr */ -#define D_LCD_OUTF_CRCB_ORDER (1 << 7) - -/* ************************************************************************** - * LCD controller control register defines - **************************************************************************** - */ -/* --- bit 0 */ -#define LCD_CTRL_PROGRESSIVE (0x00) /* default */ -#define LCD_CTRL_INTERLACED (0x01) -/* --- bit 1 */ -#define LCD_CTRL_ENABLE (0x02) /* enable conrtoller */ -/* --- bits 2,3,4,5 */ -#define LCD_CTRL_VL1_ENABLE (0x04) /* enable video layer 1 */ -#define LCD_CTRL_VL2_ENABLE (0x08) /* enable video layer 2 */ -#define LCD_CTRL_GL1_ENABLE (0x10) /* enable graphics layer 1 */ -#define LCD_CTRL_GL2_ENABLE (0x20) /* enable graphics layer 2 */ -/* --- bits 6:7 */ -#define LCD_CTRL_ALPHA_BLEND_VL1 (0x00) /* video layer 1 - default */ -#define LCD_CTRL_ALPHA_BLEND_VL2 (0x40) /* video layer 2 */ -#define LCD_CTRL_ALPHA_BLEND_GL1 (0x80) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_BLEND_GL2 (0xC0) /* graphics layer 2 */ -/* --- bits 8:9 */ -#define LCD_CTRL_ALPHA_TOP_VL1 (0x000) /* video layer 1 - default */ -#define LCD_CTRL_ALPHA_TOP_VL2 (0x100) /* video layer 2 */ -#define LCD_CTRL_ALPHA_TOP_GL1 (0x200) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_TOP_GL2 (0x300) /* graphics layer 2 */ -/* --- bits 10:11 */ -#define LCD_CTRL_ALPHA_MIDDLE_VL1 (0x000) /* video layer 1 - default */ -#define LCD_CTRL_ALPHA_MIDDLE_VL2 (0x400) /* video layer 2 */ -#define LCD_CTRL_ALPHA_MIDDLE_GL1 (0x800) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_MIDDLE_GL2 (0xC00) /* graphics layer 2 */ -/* --- bits 12:13 */ -#define LCD_CTRL_ALPHA_BOTTOM_VL1 (0x0000) /* video layer 1 */ -#define LCD_CTRL_ALPHA_BOTTOM_VL2 (0x1000) /* video layer 2 */ -#define LCD_CTRL_ALPHA_BOTTOM_GL1 (0x2000) /* graphics layer 1 */ -#define LCD_CTRL_ALPHA_BOTTOM_GL2 (0x3000) /* graphics layer 2 */ -/* --- bit 14 */ -#define LCD_CTRL_TIM_GEN_ENABLE (0x4000) /* timing generator */ -/* --- bit 15 */ -#define LCD_CTRL_DISPLAY_MODE_ONE_SHOT (0x8000) /* default continuous */ -/* --- bits 16, 17, 18 */ -#define LCD_CTRL_PWM0_EN (0x10000) /* enable PWM 0 */ -#define LCD_CTRL_PWM1_EN (0x20000) /* enable PWM 1 */ -#define LCD_CTRL_PWM2_EN (0x40000) /* enable PWM 2 */ -/* --- bits 19:20 */ -#define LCD_CTRL_OUTPUT_DISABLED (0x000000) /* output disabled */ -#define LCD_CTRL_OUTPUT_ENABLED (0x080000) -/* --- bit 21 */ -#define LCD_CTRL_SHARP_TFT (0x200000) -/* = bit 21 VSYNC BACK PORCH LEVEL */ -#define LCD_CTRL_BPORCH_ENABLE (0x00200000) -/* = bit 22 VSYNC FRONT PORCH LEVEL */ -#define LCD_CTRL_FPORCH_ENABLE (0x00400000) -/* = bit 28 enable pipelined (outstanding) DMA reads */ -#define LCD_CTRL_PIPELINE_DMA (0x10000000) - -/* LCD Control register bit fields */ - -#define EIGHT_BITS 8 -#define SIXTEEN_BITS 8 -#define TWENTY_FOUR_BITS 8 -#define THIRT_TWO_BITS 8 - -#define ENABLE 1 -/*LCD_VSTATUS_COMPARE Vertcal interval in which to generate vertcal - * interval interrupt - */ -#define LCD_VSTATUS_VERTICAL_STATUS_MASK 0x60 /* BITS 13 and 14 */ -#define LCD_VSTATUS_COMPARE_VSYNC 0x00 -#define LCD_VSTATUS_COMPARE_BACKPORCH 0x01 -#define LCD_VSTATUS_COMPARE_ACTIVE 0x10 -#define LCD_VSTATUS_COMPARE_FRONT_PORCH 0x11 +#define LCD_OUT_FORMAT_CFG (0x4 * 0x800) +#define LCD_OUTF_FORMAT_RGB121212 (0x00) +#define LCD_OUTF_FORMAT_RGB101010 (0x01) +#define LCD_OUTF_FORMAT_RGB888 (0x02) +#define LCD_OUTF_FORMAT_RGB666 (0x03) +#define LCD_OUTF_FORMAT_RGB565 (0x04) +#define LCD_OUTF_FORMAT_RGB444 (0x05) +#define LCD_OUTF_FORMAT_MRGB121212 (0x10) +#define LCD_OUTF_FORMAT_MRGB101010 (0x11) +#define LCD_OUTF_FORMAT_MRGB888 (0x12) +#define LCD_OUTF_FORMAT_MRGB666 (0x13) +#define LCD_OUTF_FORMAT_MRGB565 (0x14) +#define LCD_OUTF_FORMAT_YCBCR420_8B_LEGACY (0x08) +#define LCD_OUTF_FORMAT_YCBCR420_8B_DCI (0x09) +#define LCD_OUTF_FORMAT_YCBCR420_8B (0x0A) +#define LCD_OUTF_FORMAT_YCBCR420_10B (0x0B) +#define LCD_OUTF_FORMAT_YCBCR420_12B (0x0C) +#define LCD_OUTF_FORMAT_YCBCR422_8B (0x0D) +#define LCD_OUTF_FORMAT_YCBCR422_10B (0x0E) +#define LCD_OUTF_FORMAT_YCBCR444 (0x0F) +#define LCD_OUTF_FORMAT_MYCBCR420_8B_LEGACY (0x18) +#define LCD_OUTF_FORMAT_MYCBCR420_8B_DCI (0x19) +#define LCD_OUTF_FORMAT_MYCBCR420_8B (0x1A) +#define LCD_OUTF_FORMAT_MYCBCR420_10B (0x1B) +#define LCD_OUTF_FORMAT_MYCBCR420_12B (0x1C) +#define LCD_OUTF_FORMAT_MYCBCR422_8B (0x1D) +#define LCD_OUTF_FORMAT_MYCBCR422_10B (0x1E) +#define LCD_OUTF_FORMAT_MYCBCR444 (0x1F) +#define LCD_OUTF_BGR_ORDER (1 << 5) +#define LCD_OUTF_Y_ORDER (1 << 6) +#define LCD_OUTF_CRCB_ORDER (1 << 7) -/*interrupt bits */ -#define LCD_INT_VERT_COMP (1 << 2) -#define LCD_INT_LINE_CMP (1 << 1) -#define LCD_INT_EOF (1 << 0) +#define LCD_HSYNC_WIDTH (0x4 * 0x801) +#define LCD_H_BACKPORCH (0x4 * 0x802) +#define LCD_H_ACTIVEWIDTH (0x4 * 0x803) +#define LCD_H_FRONTPORCH (0x4 * 0x804) +#define LCD_VSYNC_WIDTH (0x4 * 0x805) +#define LCD_V_BACKPORCH (0x4 * 0x806) +#define LCD_V_ACTIVEHEIGHT (0x4 * 0x807) +#define LCD_V_FRONTPORCH (0x4 * 0x808) +#define LCD_VSYNC_START (0x4 * 0x809) +#define LCD_VSYNC_END (0x4 * 0x80a) +#define LCD_V_BACKPORCH_EVEN (0x4 * 0x80b) +#define LCD_VSYNC_WIDTH_EVEN (0x4 * 0x80c) +#define LCD_V_ACTIVEHEIGHT_EVEN (0x4 * 0x80d) +#define LCD_V_FRONTPORCH_EVEN (0x4 * 0x80e) +#define LCD_VSYNC_START_EVEN (0x4 * 0x80f) +#define LCD_VSYNC_END_EVEN (0x4 * 0x810) +#define LCD_TIMING_GEN_TRIG (0x4 * 0x811) +#define LCD_PWM0_CTRL (0x4 * 0x812) +#define LCD_PWM0_RPT_LEADIN (0x4 * 0x813) +#define LCD_PWM0_HIGH_LOW (0x4 * 0x814) +#define LCD_PWM1_CTRL (0x4 * 0x815) +#define LCD_PWM1_RPT_LEADIN (0x4 * 0x816) +#define LCD_PWM1_HIGH_LOW (0x4 * 0x817) +#define LCD_PWM2_CTRL (0x4 * 0x818) +#define LCD_PWM2_RPT_LEADIN (0x4 * 0x819) +#define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) +#define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) +#define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) +#define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) +#define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) +#define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) +#define LCD_VIDEO0_DMA2_STATE (0x4 * 0xb05) +#define LCD_VIDEO1_DMA0_BYTES (0x4 * 0xb06) +#define LCD_VIDEO1_DMA0_STATE (0x4 * 0xb07) +#define LCD_VIDEO1_DMA1_BYTES (0x4 * 0xb08) +#define LCD_VIDEO1_DMA1_STATE (0x4 * 0xb09) +#define LCD_VIDEO1_DMA2_BYTES (0x4 * 0xb0a) +#define LCD_VIDEO1_DMA2_STATE (0x4 * 0xb0b) +#define LCD_GRAPHIC0_DMA_BYTES (0x4 * 0xb0c) +#define LCD_GRAPHIC0_DMA_STATE (0x4 * 0xb0d) +#define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) +#define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:17 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:17 -0700 Subject: [Intel-gfx] [PATCH 05/59] drm/kmb: Updated kmb_plane_atomic_check In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-6-git-send-email-anitha.chrisanthus@intel.com> Check if format is supported and size is within limits. v2: simplified the code as per code review Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 111 +++++++++++++++++++++++----------------- 1 file changed, 65 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 9f1e44f..886229a 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -41,15 +41,66 @@ #include "kmb_regs.h" #include "kmb_drv.h" +/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ +static const u32 kmb_formats_g[] = { + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, +}; + +#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g)) +#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v)) + +/* video layer ( 0 & 1) formats, packed and planar formats are supported */ +static const u32 kmb_formats_v[] = { + /* packed formats */ + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, + /*planar formats */ + DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, + DRM_FORMAT_NV12, DRM_FORMAT_NV21, +}; + +static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) +{ + int i; + + for (i = 0; i < plane->format_count; i++) { + if (plane->format_types[i] == format) + return 0; + } + return -EINVAL; +} + static int kmb_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { -/* TBD below structure will be used for implementation later - * struct drm_crtc_state *crtc_state; - */ - /* TBD */ - /* Plane based checking */ + struct drm_framebuffer *fb; + int ret; + + fb = state->fb; + ret = check_pixel_format(plane, fb->format->format); + if (ret) + return ret; + + if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT) + return -EINVAL; return 0; } @@ -58,36 +109,36 @@ unsigned int set_pixel_format(u32 format) unsigned int val = 0; switch (format) { - /*planar formats */ + /*planar formats */ case DRM_FORMAT_YUV444: val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU444: val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_YUV422: val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU422: val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_YUV420: val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_YVU420: val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; case DRM_FORMAT_NV12: val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE; break; case DRM_FORMAT_NV21: val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE - | LCD_LAYER_CRCB_ORDER; + | LCD_LAYER_CRCB_ORDER; break; - /* packed formats */ + /* packed formats */ case DRM_FORMAT_RGB332: val = LCD_LAYER_FORMAT_RGB332; break; @@ -147,7 +198,7 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) unsigned int val = 0; for (i = 0; i < format->num_planes; i++) - bpp += 8*format->cpp[i]; + bpp += 8 * format->cpp[i]; switch (bpp) { case 8: @@ -191,8 +242,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w-1); - kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w - 1); + kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); kmb_write(lcd, LCD_LAYERn_COL_START(plane_id), crtc_x); kmb_write(lcd, LCD_LAYERn_ROW_START(plane_id), crtc_y); @@ -315,38 +366,6 @@ static const struct drm_plane_funcs kmb_plane_funcs = { .atomic_destroy_state = kmb_destroy_plane_state, }; -/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ -static const u32 kmb_formats_g[] = { - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, -}; - -/* video layer (0 & 1) formats, packed and planar formats are supported */ -static const u32 kmb_formats_v[] = { - /* packed formats */ - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, - /*planar formats */ - DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, - DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, - DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, - DRM_FORMAT_NV12, DRM_FORMAT_NV21, -}; - struct kmb_plane *kmb_plane_init(struct drm_device *drm) { struct kmb_drm_private *lcd = drm->dev_private; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:18 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:18 -0700 Subject: [Intel-gfx] [PATCH 06/59] drm/kmb: Initial check-in for Mipi DSI In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-7-git-send-email-anitha.chrisanthus@intel.com> Basic frame work for mipi encoder and connector. More hardware specific details will be added in the future commits. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/Makefile | 2 +- drivers/gpu/drm/kmb/kmb_drv.c | 2 + drivers/gpu/drm/kmb/kmb_dsi.c | 114 ++++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 58 +++++++++++++++++++++ 4 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.c create mode 100644 drivers/gpu/drm/kmb/kmb_dsi.h diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile index be9f19c..8102bc9 100644 --- a/drivers/gpu/drm/kmb/Makefile +++ b/drivers/gpu/drm/kmb/Makefile @@ -1,2 +1,2 @@ -kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o +kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o kmb_dsi.o obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-display.o diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index ee4e3bd..24e7c2b 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -47,6 +47,7 @@ #include "kmb_regs.h" #include "kmb_crtc.h" #include "kmb_plane.h" +#include "kmb_dsi.h" static int kmb_load(struct drm_device *drm, unsigned long flags) { @@ -83,6 +84,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } + kmb_dsi_init(drm); ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c new file mode 100644 index 0000000..b5c57e1 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright ? 2019 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + */ +#include <drm/drm_atomic_helper.h> +#include <drm/drm_crtc.h> +#include <drm/drm_probe_helper.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_connector.h> +#include <drm/drm_edid.h> +#include <drm/drm_mipi_dsi.h> +#include <linux/slab.h> +#include <linux/gpio/consumer.h> +#include "kmb_drv.h" +#include "kmb_dsi.h" + +static enum drm_mode_status +kmb_dsi_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + return MODE_OK; +} + +static int kmb_dsi_get_modes(struct drm_connector *connector) +{ + struct drm_display_mode *mode; + struct kmb_connector *kmb_connector = to_kmb_connector(connector); + + mode = drm_mode_duplicate(connector->dev, kmb_connector->fixed_mode); + drm_mode_probed_add(connector, mode); + return 1; +} + +static void kmb_dsi_connector_destroy(struct drm_connector *connector) +{ + struct kmb_connector *kmb_connector = to_kmb_connector(connector); + + drm_connector_cleanup(connector); + kfree(kmb_connector); +} + +static void kmb_dsi_encoder_destroy(struct drm_encoder *encoder) +{ + struct kmb_dsi *kmb_dsi = to_kmb_dsi(encoder); + + drm_encoder_cleanup(encoder); + kfree(kmb_dsi); +} + +static const struct drm_encoder_funcs kmb_dsi_funcs = { + .destroy = kmb_dsi_encoder_destroy, +}; + +static const struct +drm_connector_helper_funcs kmb_dsi_connector_helper_funcs = { + .get_modes = kmb_dsi_get_modes, + .mode_valid = kmb_dsi_mode_valid, +}; + +static const struct drm_connector_funcs kmb_dsi_connector_funcs = { + .destroy = kmb_dsi_connector_destroy, + .fill_modes = drm_helper_probe_single_connector_modes, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, +}; + +void kmb_dsi_init(struct drm_device *dev) +{ + struct kmb_dsi *kmb_dsi; + struct drm_encoder *encoder; + struct kmb_connector *kmb_connector; + struct drm_connector *connector; + + kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); + if (!kmb_dsi) + return; + + kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); + if (!kmb_connector) { + kfree(kmb_dsi); + return; + } + + kmb_dsi->attached_connector = kmb_connector; + + connector = &kmb_connector->base; + encoder = &kmb_dsi->base; + drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, + "MIPI-DSI"); + drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, + DRM_MODE_CONNECTOR_DSI); + drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); +} diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h new file mode 100644 index 0000000..3829360 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright ? 2019 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * + */ +#ifndef __KMB_DSI_H__ +#define __KMB_DSI_H__ + +#include <drm/drm_crtc.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include "kmb_drv.h" + +struct kmb_connector; + +struct kmb_dsi { + struct drm_encoder base; + struct kmb_connector *attached_connector; +}; + +struct kmb_dsi_host { + struct mipi_dsi_host base; + struct kmb_dsi *kmb_dsi; +}; + +struct kmb_connector { + struct drm_connector base; + struct drm_display_mode *fixed_mode; +}; + +void kmb_dsi_init(struct drm_device *dev); +void kmb_plane_destroy(struct drm_plane *plane); + +#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) +#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) +#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base) + +#endif /* __KMB_DSI_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:19 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:19 -0700 Subject: [Intel-gfx] [PATCH 07/59] drm/kmb: Set OUT_FORMAT_CFG register In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-8-git-send-email-anitha.chrisanthus@intel.com> v2: code review changes Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 14 +++++++++++++- drivers/gpu/drm/kmb/kmb_regs.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 886229a..f609283 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -228,7 +228,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned int dma_len; struct kmb_plane *kmb_plane = to_kmb_plane(plane); unsigned int dma_cfg; - unsigned int ctrl = 0, val = 0; + unsigned int ctrl = 0, val = 0, out_format = 0; unsigned int src_w, src_h, crtc_x, crtc_y; unsigned char plane_id = kmb_plane->id; @@ -299,6 +299,18 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* enable DMA */ kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + /* FIXME no doc on how to set output format - may need to change + * this later + */ + if (val & LCD_LAYER_BGR_ORDER) + out_format |= LCD_OUTF_BGR_ORDER; + else if (val & LCD_LAYER_CRCB_ORDER) + out_format |= LCD_OUTF_CRCB_ORDER; + /* do not interleave RGB channels for mipi Tx compatibility */ + out_format |= LCD_OUTF_MIPI_RGB_MODE; + /* pixel format from LCD_LAYER_CFG */ + out_format |= ((val >> 9) & 0x1F); + kmb_write(lcd, LCD_OUT_FORMAT_CFG, out_format); } static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 14466b8..299ab99 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -340,6 +340,7 @@ #define LCD_OUTF_BGR_ORDER (1 << 5) #define LCD_OUTF_Y_ORDER (1 << 6) #define LCD_OUTF_CRCB_ORDER (1 << 7) +#define LCD_OUTF_MIPI_RGB_MODE (1 << 18) #define LCD_HSYNC_WIDTH (0x4 * 0x801) #define LCD_H_BACKPORCH (0x4 * 0x802) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:20 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:20 -0700 Subject: [Intel-gfx] [PATCH 08/59] drm/kmb: Added mipi_dsi_host initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-9-git-send-email-anitha.chrisanthus@intel.com> Added mipi DSI host initialization functions Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 59 +++++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 4 +++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index b5c57e1..5e2aff1 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -85,12 +85,59 @@ static const struct drm_connector_funcs kmb_dsi_connector_funcs = { .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, }; +static ssize_t kmb_dsi_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + return 0; +} + +static int kmb_dsi_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *dev) +{ + return 0; +} + +static int kmb_dsi_host_detach(struct mipi_dsi_host *host, + struct mipi_dsi_device *dev) +{ + return 0; +} + +static const struct mipi_dsi_host_ops kmb_dsi_host_ops = { + .attach = kmb_dsi_host_attach, + .detach = kmb_dsi_host_detach, + .transfer = kmb_dsi_host_transfer, +}; + +static struct kmb_dsi_host *kmb_dsi_host_init(struct kmb_dsi *kmb_dsi) +{ + struct kmb_dsi_host *host; + struct mipi_dsi_device *device; + + host = kzalloc(sizeof(*host), GFP_KERNEL); + if (!host) + return NULL; + + host->base.ops = &kmb_dsi_host_ops; + host->kmb_dsi = kmb_dsi; + + device = kzalloc(sizeof(*device), GFP_KERNEL); + if (!device) { + kfree(host); + return NULL; + } + device->host = &host->base; + host->device = device; + return host; +} + void kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; struct kmb_connector *kmb_connector; struct drm_connector *connector; + struct kmb_dsi_host *host; kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); if (!kmb_dsi) @@ -108,7 +155,19 @@ void kmb_dsi_init(struct drm_device *dev) encoder = &kmb_dsi->base; drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI"); + + host = kmb_dsi_host_init(kmb_dsi); + if (!host) { + drm_encoder_cleanup(encoder); + kfree(kmb_dsi); + kfree(kmb_connector); + } + drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, DRM_MODE_CONNECTOR_DSI); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); + + connector->encoder = encoder; + drm_connector_attach_encoder(connector, encoder); + } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 3829360..88810ee 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -32,19 +32,23 @@ #include "kmb_drv.h" struct kmb_connector; +struct kmb_dsi_host; struct kmb_dsi { struct drm_encoder base; struct kmb_connector *attached_connector; + struct kmb_dsi_host *dsi_host; }; struct kmb_dsi_host { struct mipi_dsi_host base; struct kmb_dsi *kmb_dsi; + struct mipi_dsi_device *device; }; struct kmb_connector { struct drm_connector base; + struct drm_encoder *encoder; struct drm_display_mode *fixed_mode; }; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:21 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:21 -0700 Subject: [Intel-gfx] [PATCH 09/59] drm/kmb: Part 1 of Mipi Tx Initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-10-git-send-email-anitha.chrisanthus@intel.com> Mipi TX frame section configuration This is the first part in the MIPI controller initialization. Compute and set the right values in MIPI TX frame section configuration registers like packet header(PH), unpacked bytes and line config. v2: added more comments to clarify assumptions v3: improved code readability as per code review Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.h | 14 ++ drivers/gpu/drm/kmb/kmb_dsi.c | 330 +++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 232 +++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_regs.h | 25 ++++ 4 files changed, 601 insertions(+) diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 637e9a2..46be8cb 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -62,6 +62,20 @@ static inline u32 kmb_read(struct kmb_drm_private *lcd, unsigned int reg) return readl(lcd->mmio + reg); } +static inline void kmb_write_bits(struct kmb_drm_private *lcd, + unsigned int reg, u32 offset, u32 num_bits, + u32 value) +{ + u32 reg_val = kmb_read(lcd, reg); + u32 mask = (1 << num_bits) - 1; + + value &= mask; + mask <<= offset; + reg_val &= (~mask); + reg_val |= (value << offset); + writel(reg_val, lcd->mmio + reg); +} + int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); #endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 5e2aff1..17e1383 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -30,11 +30,83 @@ #include <drm/drm_connector.h> #include <drm/drm_edid.h> #include <drm/drm_mipi_dsi.h> +#include <drm/drm_print.h> #include <linux/slab.h> #include <linux/gpio/consumer.h> #include "kmb_drv.h" +#include "kmb_regs.h" #include "kmb_dsi.h" +#define IMG_WIDTH_PX 1920 +#define IMG_HEIGHT_LINES 1080 +#define LCD_BYTESPP 1 + +/*MIPI TX CFG*/ +#define MIPI_TX_ACTIVE_LANES 4 +#define MIPI_TX_LANE_DATA_RATE_MBPS 888 +#define MIPI_TX_REF_CLK_KHZ 24000 +#define MIPI_TX_CFG_CLK_KHZ 24000 + +/* + * These are added here only temporarily for testing, + * these will eventually go to the device tree sections, + * and can be used as a refernce later for device tree additions + */ +struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { + .width_pixels = IMG_WIDTH_PX, + .height_lines = IMG_HEIGHT_LINES, + .data_type = DSI_LP_DT_PPS_RGB888_24B, + .data_mode = MIPI_DATA_MODE1, + .dma_packed = 0 +}; + +struct mipi_tx_frame_cfg mipitx_frame0_cfg = { + .sections[0] = &mipi_tx_frame0_sect_cfg, + .sections[1] = NULL, + .sections[2] = NULL, + .sections[3] = NULL, + .vsync_width = 5, + .v_backporch = 36, + .v_frontporch = 4, + .hsync_width = 44, + .h_backporch = 148, + .h_frontporch = 88 +}; + +struct mipi_tx_dsi_cfg mipitx_dsi_cfg = { + .hfp_blank_en = 0, + .eotp_en = 0, + .lpm_last_vfp_line = 0, + .lpm_first_vsa_line = 0, + .sync_pulse_eventn = DSI_VIDEO_MODE_NO_BURST_EVENT, + .hfp_blanking = SEND_BLANK_PACKET, + .hbp_blanking = SEND_BLANK_PACKET, + .hsa_blanking = SEND_BLANK_PACKET, + .v_blanking = SEND_BLANK_PACKET, +}; + +struct mipi_ctrl_cfg mipi_tx_init_cfg = { + .index = MIPI_CTRL6, + .type = MIPI_DSI, + .dir = MIPI_TX, + .active_lanes = MIPI_TX_ACTIVE_LANES, + .lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS, + .ref_clk_khz = MIPI_TX_REF_CLK_KHZ, + .cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ, + .data_if = MIPI_IF_PARALLEL, + .tx_ctrl_cfg = { + .frames[0] = &mipitx_frame0_cfg, + .frames[1] = NULL, + .frames[2] = NULL, + .frames[3] = NULL, + .tx_dsi_cfg = &mipitx_dsi_cfg, + .line_sync_pkt_en = 0, + .line_counter_active = 0, + .frame_counter_active = 0, + } + +}; + static enum drm_mode_status kmb_dsi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -131,6 +203,261 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct kmb_dsi *kmb_dsi) return host; } +u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, + struct mipi_data_type_params *params) +{ + struct mipi_data_type_params data_type_parameters; + + switch (data_type) { + case DSI_LP_DT_PPS_YCBCR420_12B: + data_type_parameters.size_constraint_pixels = 2; + data_type_parameters.size_constraint_bytes = 3; + switch (data_mode) { + /* case 0 not supported according to MDK */ + case 1: + case 2: + case 3: + data_type_parameters.pixels_per_pclk = 2; + data_type_parameters.bits_per_pclk = 24; + break; + default: + DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); + return -EINVAL; + }; + break; + case DSI_LP_DT_PPS_YCBCR422_16B: + data_type_parameters.size_constraint_pixels = 2; + data_type_parameters.size_constraint_bytes = 4; + switch (data_mode) { + /* case 0 and 1 not supported according to MDK */ + case 2: + data_type_parameters.pixels_per_pclk = 1; + data_type_parameters.bits_per_pclk = 16; + break; + case 3: + data_type_parameters.pixels_per_pclk = 2; + data_type_parameters.bits_per_pclk = 32; + break; + default: + DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); + return -EINVAL; + }; + break; + case DSI_LP_DT_LPPS_YCBCR422_20B: + case DSI_LP_DT_PPS_YCBCR422_24B: + data_type_parameters.size_constraint_pixels = 2; + data_type_parameters.size_constraint_bytes = 6; + switch (data_mode) { + /* case 0 not supported according to MDK */ + case 1: + case 2: + case 3: + data_type_parameters.pixels_per_pclk = 1; + data_type_parameters.bits_per_pclk = 24; + break; + default: + DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); + return -EINVAL; + }; + break; + case DSI_LP_DT_PPS_RGB565_16B: + data_type_parameters.size_constraint_pixels = 1; + data_type_parameters.size_constraint_bytes = 2; + switch (data_mode) { + case 0: + case 1: + data_type_parameters.pixels_per_pclk = 1; + data_type_parameters.bits_per_pclk = 16; + break; + case 2: + case 3: + data_type_parameters.pixels_per_pclk = 2; + data_type_parameters.bits_per_pclk = 32; + break; + default: + DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); + return -EINVAL; + }; + break; + case DSI_LP_DT_PPS_RGB666_18B: + data_type_parameters.size_constraint_pixels = 4; + data_type_parameters.size_constraint_bytes = 9; + data_type_parameters.bits_per_pclk = 18; + data_type_parameters.pixels_per_pclk = 1; + break; + case DSI_LP_DT_LPPS_RGB666_18B: + case DSI_LP_DT_PPS_RGB888_24B: + data_type_parameters.size_constraint_pixels = 1; + data_type_parameters.size_constraint_bytes = 3; + data_type_parameters.bits_per_pclk = 24; + data_type_parameters.pixels_per_pclk = 1; + break; + case DSI_LP_DT_PPS_RGB101010_30B: + data_type_parameters.size_constraint_pixels = 4; + data_type_parameters.size_constraint_bytes = 15; + data_type_parameters.bits_per_pclk = 30; + data_type_parameters.pixels_per_pclk = 1; + break; + + default: + DRM_ERROR("DSI: Invalid data_type %d\n", data_type); + return -EINVAL; + } + + *params = data_type_parameters; + return 0; +} + +static u32 compute_wc(u32 width_px, u8 size_constr_p, u8 size_constr_b) +{ + /* calculate the word count for each long packet */ + return (((width_px / size_constr_p) * size_constr_b) & 0xffff); +} + +static u32 compute_unpacked_bytes(u32 wc, u8 bits_per_pclk) +{ + /*number of PCLK cycles needed to transfer a line */ + /* with each PCLK cycle, 4 Bytes are sent through the PPL module */ + return ((wc * 8) / bits_per_pclk) * 4; +} + +static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, + u8 frame_id, u8 section, + u32 height_lines, u32 unpacked_bytes, + struct mipi_tx_frame_sect_phcfg *ph_cfg) +{ + u32 cfg = 0; + u32 ctrl_no = MIPI_CTRL6; + u32 reg_adr; + + /*frame section packet header */ + /*word count */ + cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0] */ + /*data type */ + cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) + << MIPI_TX_SECT_DT_SHIFT); /* bits [21:16] */ + /* virtual channel */ + cfg |= ((ph_cfg->vchannel & MIPI_TX_SECT_VC_MASK) + << MIPI_TX_SECT_VC_SHIFT); /* bits [23:22] */ + /* data mode */ + cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) + << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ + cfg |= MIPI_TX_SECT_DMA_PACKED; + kmb_write(dev_priv, + (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, section)), cfg); + + /*unpacked bytes */ + /*there are 4 frame generators and each fg has 4 sections + *there are 2 registers for unpacked bytes - + *# bytes each section occupies in memory + *REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 + *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 + */ + reg_adr = + MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, + frame_id) + (section / 2) * 4; + kmb_write_bits(dev_priv, reg_adr, (section % 2) * 16, 16, + unpacked_bytes); + + /* line config */ + reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); + kmb_write(dev_priv, reg_adr, height_lines); + return 0; +} + +static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_priv, + u8 frame_id, + u8 section, + struct mipi_tx_frame_section_cfg *frame_scfg, + u32 *bits_per_pclk, u32 *wc) +{ + u32 ret = 0; + u32 unpacked_bytes; + struct mipi_data_type_params data_type_parameters; + struct mipi_tx_frame_sect_phcfg ph_cfg; + + ret = + mipi_get_datatype_params(frame_scfg->data_type, + frame_scfg->data_mode, + &data_type_parameters); + if (ret) + return ret; + /* + * packet width has to be a multiple of the minimum packet width + * (in pixels) set for each data type + */ + if (frame_scfg->width_pixels % + data_type_parameters.size_constraint_pixels != 0) + return -EINVAL; + + *wc = compute_wc(frame_scfg->width_pixels, + data_type_parameters.size_constraint_pixels, + data_type_parameters.size_constraint_bytes); + + unpacked_bytes = + compute_unpacked_bytes(*wc, data_type_parameters.bits_per_pclk); + + ph_cfg.wc = *wc; + ph_cfg.data_mode = frame_scfg->data_mode; + ph_cfg.data_type = frame_scfg->data_type; + ph_cfg.vchannel = frame_id; + + mipi_tx_fg_section_cfg_regs(dev_priv, frame_id, section, + frame_scfg->height_lines, unpacked_bytes, + &ph_cfg); + + /*caller needs bits_per_clk for additional caluclations */ + *bits_per_pclk = data_type_parameters.bits_per_pclk; + return 0; +} + +static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, + struct mipi_ctrl_cfg *ctrl_cfg) +{ + u32 ret; + u8 frame_id, sect; + u32 bits_per_pclk = 0; + u32 word_count = 0; + + /*This is the order in which mipi tx needs to be initialized + * set frame section parameters + * set frame specific parameters + * connect lcd to mipi + * multi channel fifo cfg + * set mipitxcctrlcfg + */ + + for (frame_id = 0; frame_id < 4; frame_id++) { + /* find valid frame, assume only one valid frame */ + if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id] == NULL) + continue; + + /*TODO - assume there is only one valid section in a frame, so + * bits_per_pclk and word_count are only set once + */ + for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { + if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] + == NULL) + continue; + + ret = mipi_tx_fg_section_cfg(dev_priv, frame_id, sect, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], + &bits_per_pclk, + &word_count); + if (ret) + return ret; + + } + + /*function for setting frame sepecific parameters will be + * called here bits_per_pclk and word_count will be passed + * in to this function + */ + + } + return ret; +} + void kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; @@ -138,6 +465,7 @@ void kmb_dsi_init(struct drm_device *dev) struct kmb_connector *kmb_connector; struct drm_connector *connector; struct kmb_dsi_host *host; + struct kmb_drm_private *dev_priv = dev->dev_private; kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); if (!kmb_dsi) @@ -170,4 +498,6 @@ void kmb_dsi_init(struct drm_device *dev) connector->encoder = encoder; drm_connector_attach_encoder(connector, encoder); + /* initialize mipi controller */ + mipi_tx_init_cntrl(dev_priv, &mipi_tx_init_cfg); } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 88810ee..88b865f 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -52,6 +52,238 @@ struct kmb_connector { struct drm_display_mode *fixed_mode; }; +#define MIPI_TX_FRAME_GEN 4 +#define MIPI_TX_FRAME_GEN_SECTIONS 4 +#define MIPI_CTRL_VIRTUAL_CHANNELS 4 + +enum mipi_ctrl_num { + MIPI_CTRL0 = 0, + MIPI_CTRL1, + MIPI_CTRL2, + MIPI_CTRL3, + MIPI_CTRL4, + MIPI_CTRL5, + MIPI_CTRL6, + MIPI_CTRL7, + MIPI_CTRL8, + MIPI_CTRL9, + MIPI_CTRL_NA +}; + +enum mipi_dphy_num { + MIPI_DPHY0 = 0, + MIPI_DPHY1, + MIPI_DPHY2, + MIPI_DPHY3, + MIPI_DPHY4, + MIPI_DPHY5, + MIPI_DPHY6, + MIPI_DPHY7, + MIPI_DPHY8, + MIPI_DPHY9, + MIPI_DPHY_NA +}; + +enum mipi_dir { + MIPI_RX, + MIPI_TX +}; + +enum mipi_ctrl_type { + MIPI_DSI, + MIPI_CSI +}; + +enum mipi_data_if { + MIPI_IF_DMA, + MIPI_IF_PARALLEL +}; + +enum mipi_data_mode { + MIPI_DATA_MODE0, + MIPI_DATA_MODE1, + MIPI_DATA_MODE2, + MIPI_DATA_MODE3 +}; + +enum mipi_dsi_video_mode { + DSI_VIDEO_MODE_NO_BURST_PULSE, + DSI_VIDEO_MODE_NO_BURST_EVENT, + DSI_VIDEO_MODE_BURST +}; + +enum mipi_dsi_blanking_mode { + TRANSITION_TO_LOW_POWER, + SEND_BLANK_PACKET +}; + +enum mipi_dsi_eotp { + DSI_EOTP_DISABLED, + DSI_EOTP_ENABLES +}; + +enum mipi_dsi_data_type { + DSI_SP_DT_RESERVED_00 = 0x00, + DSI_SP_DT_VSYNC_START = 0x01, + DSI_SP_DT_COLOR_MODE_OFF = 0x02, + DSI_SP_DT_GENERIC_SHORT_WR = 0x03, + DSI_SP_DT_GENERIC_RD = 0x04, + DSI_SP_DT_DCS_SHORT_WR = 0x05, + DSI_SP_DT_DCS_RD = 0x06, + DSI_SP_DT_EOTP = 0x08, + DSI_LP_DT_NULL = 0x09, + DSI_LP_DT_RESERVED_0A = 0x0a, + DSI_LP_DT_RESERVED_0B = 0x0b, + DSI_LP_DT_LPPS_YCBCR422_20B = 0x0c, + DSI_LP_DT_PPS_RGB101010_30B = 0x0d, + DSI_LP_DT_PPS_RGB565_16B = 0x0e, + DSI_LP_DT_RESERVED_0F = 0x0f, + + DSI_SP_DT_RESERVED_10 = 0x10, + DSI_SP_DT_VSYNC_END = 0x11, + DSI_SP_DT_COLOR_MODE_ON = 0x12, + DSI_SP_DT_GENERIC_SHORT_WR_1PAR = 0x13, + DSI_SP_DT_GENERIC_RD_1PAR = 0x14, + DSI_SP_DT_DCS_SHORT_WR_1PAR = 0x15, + DSI_SP_DT_RESERVED_16 = 0x16, + DSI_SP_DT_RESERVED_17 = 0x17, + DSI_SP_DT_RESERVED_18 = 0x18, + DSI_LP_DT_BLANK = 0x19, + DSI_LP_DT_RESERVED_1A = 0x1a, + DSI_LP_DT_RESERVED_1B = 0x1b, + DSI_LP_DT_PPS_YCBCR422_24B = 0x1c, + DSI_LP_DT_PPS_RGB121212_36B = 0x1d, + DSI_LP_DT_PPS_RGB666_18B = 0x1e, + DSI_LP_DT_RESERVED_1F = 0x1f, + + DSI_SP_DT_RESERVED_20 = 0x20, + DSI_SP_DT_HSYNC_START = 0x21, + DSI_SP_DT_SHUT_DOWN_PERIPH_CMD = 0x22, + DSI_SP_DT_GENERIC_SHORT_WR_2PAR = 0x23, + DSI_SP_DT_GENERIC_RD_2PAR = 0x24, + DSI_SP_DT_RESERVED_25 = 0x25, + DSI_SP_DT_RESERVED_26 = 0x26, + DSI_SP_DT_RESERVED_27 = 0x27, + DSI_SP_DT_RESERVED_28 = 0x28, + DSI_LP_DT_GENERIC_LONG_WR = 0x29, + DSI_LP_DT_RESERVED_2A = 0x2a, + DSI_LP_DT_RESERVED_2B = 0x2b, + DSI_LP_DT_PPS_YCBCR422_16B = 0x2c, + DSI_LP_DT_RESERVED_2D = 0x2d, + DSI_LP_DT_LPPS_RGB666_18B = 0x2e, + DSI_LP_DT_RESERVED_2F = 0x2f, + + DSI_SP_DT_RESERVED_30 = 0x30, + DSI_SP_DT_HSYNC_END = 0x31, + DSI_SP_DT_TURN_ON_PERIPH_CMD = 0x32, + DSI_SP_DT_RESERVED_33 = 0x33, + DSI_SP_DT_RESERVED_34 = 0x34, + DSI_SP_DT_RESERVED_35 = 0x35, + DSI_SP_DT_RESERVED_36 = 0x36, + DSI_SP_DT_SET_MAX_RETURN_PKT_SIZE = 0x37, + DSI_SP_DT_RESERVED_38 = 0x38, + DSI_LP_DT_DSC_LONG_WR = 0x39, + DSI_LP_DT_RESERVED_3A = 0x3a, + DSI_LP_DT_RESERVED_3B = 0x3b, + DSI_LP_DT_RESERVED_3C = 0x3c, + DSI_LP_DT_PPS_YCBCR420_12B = 0x3d, + DSI_LP_DT_PPS_RGB888_24B = 0x3e, + DSI_LP_DT_RESERVED_3F = 0x3f +}; + +struct mipi_data_type_params { + uint8_t size_constraint_pixels; + uint8_t size_constraint_bytes; + uint8_t pixels_per_pclk; + uint8_t bits_per_pclk; +}; +struct mipi_tx_dsi_cfg { + uint8_t hfp_blank_en; /*horizontal front porch blanking enable */ + uint8_t eotp_en; /*End of transmission packet enable */ + /*last vertical front porch blanking mode */ + uint8_t lpm_last_vfp_line; + /*first vertical sync active blanking mode */ + uint8_t lpm_first_vsa_line; + uint8_t sync_pulse_eventn; /*sync type */ + uint8_t hfp_blanking; /*horizontal front porch blanking mode */ + uint8_t hbp_blanking; /*horizontal back porch blanking mode */ + uint8_t hsa_blanking; /*horizontal sync active blanking mode */ + uint8_t v_blanking; /*vertical timing blanking mode */ +}; + +struct mipi_tx_frame_section_cfg { + uint32_t dma_v_stride; + uint16_t dma_v_scale_cfg; + uint16_t width_pixels; /* Frame width */ + uint16_t height_lines; + uint8_t dma_packed; + uint8_t bpp; + uint8_t bpp_unpacked; + uint8_t dma_h_stride; + uint8_t data_type; + uint8_t data_mode; + uint8_t dma_flip_rotate_sel; +}; + +struct mipi_tx_frame_timing_cfg { + uint32_t bpp; + uint32_t lane_rate_mbps; + uint32_t hsync_width; + uint32_t h_backporch; + uint32_t h_frontporch; + uint32_t h_active; + uint16_t vsync_width; + uint16_t v_backporch; + uint16_t v_frontporch; + uint16_t v_active; + uint8_t active_lanes; +}; + +struct mipi_tx_frame_sect_phcfg { + uint32_t wc; + enum mipi_data_mode data_mode; + enum mipi_dsi_data_type data_type; + uint8_t vchannel; +}; + +struct mipi_tx_frame_cfg { + struct mipi_tx_frame_section_cfg *sections[MIPI_TX_FRAME_GEN_SECTIONS]; + uint32_t hsync_width; /*in pixels */ + uint32_t h_backporch; /*in pixels */ + uint32_t h_frontporch; /*in pixels */ + uint16_t vsync_width; /*in lines */ + uint16_t v_backporch; /*in lines */ + uint16_t v_frontporch; /*in lines */ +}; + +struct mipi_tx_ctrl_cfg { + struct mipi_tx_frame_cfg *frames[MIPI_TX_FRAME_GEN]; + struct mipi_tx_dsi_cfg *tx_dsi_cfg; + uint8_t line_sync_pkt_en; + uint8_t line_counter_active; + uint8_t frame_counter_active; + uint8_t tx_hsclkkidle_cnt; + uint8_t tx_hsexit_cnt; + uint8_t tx_crc_en; + uint8_t tx_hact_wait_stop; + uint8_t tx_always_use_hact; + uint8_t tx_wait_trig; + uint8_t tx_wait_all_sect; +}; + +/*configuration structure for MIPI control */ +struct mipi_ctrl_cfg { + /* controller index : CTRL6 for connecting to LCD */ + uint8_t index; + uint8_t type; /* controller type : MIPI_DSI */ + uint8_t dir; /* controller direction : MIPI_TX */ + uint8_t active_lanes; /* # active lanes per controller 2/4 */ + uint32_t lane_rate_mbps; /*MBPS */ + uint32_t ref_clk_khz; + uint32_t cfg_clk_khz; + uint32_t data_if; /*MIPI_IF_DMA or MIPI_IF_PARALLEL */ + struct mipi_tx_ctrl_cfg tx_ctrl_cfg; +}; void kmb_dsi_init(struct drm_device *dev); void kmb_plane_destroy(struct drm_plane *plane); diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 299ab99..06324ba 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -385,4 +385,29 @@ #define LCD_GRAPHIC1_DMA_BYTES (0x4 * 0xb0e) #define LCD_GRAPHIC1_DMA_STATE (0x4 * 0xb0f) +/*************************************************************************** + * MIPI controller control register defines + ***********************************************i****************************/ +#define MIPI_BASE_ADDR (0x20900000) +#define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) +#define MIPI_CTRL_HS_BASE_ADDR (0x400) +#define MIPI_TX0_HS_FG0_SECT0_PH (0x40) +#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ + (0x400*M) + (0x2C*N) + (8*O)) +#define MIPI_TX_SECT_WC_MASK (0xffff) +#define MIPI_TX_SECT_VC_MASK (3) +#define MIPI_TX_SECT_VC_SHIFT (22) +#define MIPI_TX_SECT_DT_MASK (0x3f) +#define MIPI_TX_SECT_DT_SHIFT (16) +#define MIPI_TX_SECT_DM_MASK (3) +#define MIPI_TX_SECT_DM_SHIFT (24) +#define MIPI_TX_SECT_DMA_PACKED (1<<26) +#define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60) +#define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64) +#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ + (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N)) +#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) (MIPI_TX_HS_FG0_SECT0_LINE_CFG \ + + (0x400*M) + (0x2C*N) + (8*O)) +#define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) + #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:22 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:22 -0700 Subject: [Intel-gfx] [PATCH 10/59] drm/kmb: Part 2 of Mipi Tx Initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-11-git-send-email-anitha.chrisanthus@intel.com> Mipi TX Frame generator timing configuration Compute and set frame generator timings like hactive, front porch, back porch etc. v2: minor code review changes Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 132 ++++++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/kmb/kmb_regs.h | 37 ++++++++++++ 2 files changed, 166 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 17e1383..1435ed8 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -411,6 +411,123 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_priv, return 0; } +static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, + u8 frame_gen, + struct mipi_tx_frame_timing_cfg *fg_cfg) +{ + u32 sysclk; + /*float ppl_llp_ratio; */ + u32 ppl_llp_ratio; + u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset; + + /*Get system clock for blanking period cnfigurations */ + /*TODO need to get system clock from clock driver */ + /* Assume 700 Mhz system clock for now */ + sysclk = 700; + + /*ppl-pixel packing layer, llp-low level protocol + * frame genartor timing parameters are clocked on the system clock + * whereas as the equivalent parameters in the LLP blocks are clocked + * on LLP Tx clock from the D-PHY - BYTE clock + */ + + /*multiply by 1000 to keep the precision */ + ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / + ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); + + /*frame generator number of lines */ + reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->v_active); + + /*vsync width */ + /* + *there are 2 registers for vsync width -VSA in lines for channels 0-3 + *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 + *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 + */ + offset = (frame_gen % 2) * 16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->vsync_width); + + /*v backporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_backporch); + + /*v frontporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_frontporch); + + /*v active - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen); + kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_active); + + /*hsyc width */ + reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, + (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); + + /*h backporch */ + reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, + (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); + + /*h frontporch */ + reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, + (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); + + /*h active */ + reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); + /*convert h_active which is wc in bytes to cycles */ + val = (fg_cfg->h_active * sysclk * 1000) / + ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); + val /= 1000; + kmb_write(dev_priv, reg_adr, val); + + /* llp hsync width */ + reg_adr = MIPI_TXm_HS_LLP_HSYNC_WIDTHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); + + /* llp h backporch */ + reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); + + /* llp h frontporch */ + reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen); + kmb_write(dev_priv, reg_adr, fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); +} + +static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen, + u8 active_lanes, u32 bpp, u32 wc, + u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) +{ + u32 i, fg_num_lines = 0; + struct mipi_tx_frame_timing_cfg fg_t_cfg; + + /*calculate the total frame generator number of lines based on it's + * active sections + */ + for (i = 0; i < MIPI_TX_FRAME_GEN_SECTIONS; i++) { + if (fg_cfg->sections[i] != NULL) + fg_num_lines += fg_cfg->sections[i]->height_lines; + } + + fg_t_cfg.bpp = bpp; + fg_t_cfg.lane_rate_mbps = lane_rate_mbps; + fg_t_cfg.hsync_width = fg_cfg->hsync_width; + fg_t_cfg.h_backporch = fg_cfg->h_backporch; + fg_t_cfg.h_frontporch = fg_cfg->h_frontporch; + fg_t_cfg.h_active = wc; + fg_t_cfg.vsync_width = fg_cfg->vsync_width; + fg_t_cfg.v_backporch = fg_cfg->v_backporch; + fg_t_cfg.v_frontporch = fg_cfg->v_frontporch; + fg_t_cfg.v_active = fg_num_lines; + fg_t_cfg.active_lanes = active_lanes; + + /*apply frame generator timing setting */ + mipi_tx_fg_cfg_regs(dev_priv, frame_gen, &fg_t_cfg); +} + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, struct mipi_ctrl_cfg *ctrl_cfg) { @@ -432,12 +549,13 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id] == NULL) continue; + /* Frame Section configuration */ /*TODO - assume there is only one valid section in a frame, so * bits_per_pclk and word_count are only set once */ for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] - == NULL) + == NULL) continue; ret = mipi_tx_fg_section_cfg(dev_priv, frame_id, sect, @@ -449,9 +567,17 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, } + /* set frame specific parameters */ + mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, + bits_per_pclk, + word_count, + ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); /*function for setting frame sepecific parameters will be - * called here bits_per_pclk and word_count will be passed - * in to this function + * called here + */ + /*bits_per_pclk and word_count will be passed in to this + * function */ } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 06324ba..8715c7b 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -410,4 +410,41 @@ + (0x400*M) + (0x2C*N) + (8*O)) #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) +#define MIPI_TX_HS_FG0_NUM_LINES (0x68) +#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \ + (0x400*M) + (0x2C*N)) +#define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104) +#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) (MIPI_TX_HS_VSYNC_WIDTHS0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_V_BACKPORCHES0 (0x16c) +#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) (MIPI_TX_HS_V_BACKPORCHES0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_V_FRONTPORCHES0 (0x174) +#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) (MIPI_TX_HS_V_FRONTPORCHES0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_V_ACTIVE0 (0x17c) +#define MIPI_TXm_HS_V_ACTIVEn(M, N) (MIPI_TX_HS_V_ACTIVE0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c) +#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_HSYNC_WIDTH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_H_BACKPORCH0 (0x11c) +#define MIPI_TXm_HS_H_BACKPORCHn(M, N) (MIPI_TX_HS_H_BACKPORCH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_H_FRONTPORCH0 (0x12c) +#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) (MIPI_TX_HS_H_FRONTPORCH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_H_ACTIVE0 (0x184) +#define MIPI_TXm_HS_H_ACTIVEn(M, N) (MIPI_TX_HS_H_ACTIVE0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c) +#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c) +#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) (MIPI_TX_HS_LLP_H_BACKPORCH0 + \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) +#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ + + (0x400*M) + (0x4*N)) + #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:23 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:23 -0700 Subject: [Intel-gfx] [PATCH 11/59] drm/kmb: Use correct mmio offset from data book In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-12-git-send-email-anitha.chrisanthus@intel.com> Also added separate macros for lcd and mipi register accesses that use the corrected mmio offset. mmio oofset will be read from the device tree in the future. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 49 ++++++++++++++++++----------------------- drivers/gpu/drm/kmb/kmb_drv.c | 18 ++++++--------- drivers/gpu/drm/kmb/kmb_drv.h | 47 ++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/kmb/kmb_dsi.c | 41 +++++++++++++++------------------- drivers/gpu/drm/kmb/kmb_plane.c | 34 ++++++++++++++-------------- drivers/gpu/drm/kmb/kmb_regs.h | 6 ++++- 6 files changed, 113 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 6f16410..8e127ae 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -52,25 +52,21 @@ static void kmb_crtc_cleanup(struct drm_crtc *crtc) static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) { - struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); - /*clear interrupt */ - kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP); + kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP); /*set which interval to generate vertical interrupt */ - kmb_write(lcd, LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC); + kmb_write_lcd(LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC); /* enable vertical interrupt */ - kmb_write(lcd, LCD_INT_ENABLE, LCD_INT_VERT_COMP); + kmb_write_lcd(LCD_INT_ENABLE, LCD_INT_VERT_COMP); return 0; } static void kmb_crtc_disable_vblank(struct drm_crtc *crtc) { - struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); - /*clear interrupt */ - kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP); + kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP); /* disable vertical interrupt */ - kmb_write(lcd, LCD_INT_ENABLE, 0); + kmb_write_lcd(LCD_INT_ENABLE, 0); /* TBD * set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register @@ -92,7 +88,6 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = { static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) { - struct kmb_drm_private *lcd = crtc_to_kmb_priv(crtc); struct drm_display_mode *m = &crtc->state->adjusted_mode; struct videomode vm; int vsync_start_offset; @@ -109,30 +104,30 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; - kmb_write(lcd, LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1); - kmb_write(lcd, LCD_V_BACKPORCH, vm.vback_porch - 1); - kmb_write(lcd, LCD_V_FRONTPORCH, vm.vfront_porch - 1); - kmb_write(lcd, LCD_VSYNC_WIDTH, vm.vsync_len - 1); - kmb_write(lcd, LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1); - kmb_write(lcd, LCD_H_BACKPORCH, vm.hback_porch - 1); - kmb_write(lcd, LCD_H_FRONTPORCH, vm.hfront_porch - 1); - kmb_write(lcd, LCD_HSYNC_WIDTH, vm.hsync_len - 1); + kmb_write_lcd(LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1); + kmb_write_lcd(LCD_V_BACKPORCH, vm.vback_porch - 1); + kmb_write_lcd(LCD_V_FRONTPORCH, vm.vfront_porch - 1); + kmb_write_lcd(LCD_VSYNC_WIDTH, vm.vsync_len - 1); + kmb_write_lcd(LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1); + kmb_write_lcd(LCD_H_BACKPORCH, vm.hback_porch - 1); + kmb_write_lcd(LCD_H_FRONTPORCH, vm.hfront_porch - 1); + kmb_write_lcd(LCD_HSYNC_WIDTH, vm.hsync_len - 1); if (m->flags == DRM_MODE_FLAG_INTERLACE) { - kmb_write(lcd, LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); - kmb_write(lcd, LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1); - kmb_write(lcd, LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); - kmb_write(lcd, LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); - kmb_write(lcd, LCD_VSYNC_START_EVEN, vsync_start_offset); - kmb_write(lcd, LCD_VSYNC_END_EVEN, vsync_end_offset); + kmb_write_lcd(LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); + kmb_write_lcd(LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1); + kmb_write_lcd(LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); + kmb_write_lcd(LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); + kmb_write_lcd(LCD_VSYNC_START_EVEN, vsync_start_offset); + kmb_write_lcd(LCD_VSYNC_END_EVEN, vsync_end_offset); } /* enable VL1 layer as default */ ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE; ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_OUTPUT_ENABLED; - kmb_write(lcd, LCD_CONTROL, ctrl); + | LCD_CTRL_OUTPUT_ENABLED; + kmb_write_lcd(LCD_CONTROL, ctrl); - kmb_write(lcd, LCD_TIMING_GEN_TRIG, ENABLE); + kmb_write_lcd(LCD_TIMING_GEN_TRIG, ENABLE); /* TBD */ /* set clocks here */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 24e7c2b..0b99309 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -44,7 +44,6 @@ #include <drm/drm_of.h> #include <drm/drm_irq.h> #include "kmb_drv.h" -#include "kmb_regs.h" #include "kmb_crtc.h" #include "kmb_plane.h" #include "kmb_dsi.h" @@ -120,21 +119,20 @@ static void kmb_setup_mode_config(struct drm_device *drm) static irqreturn_t kmb_irq(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; - struct kmb_drm_private *lcd = dev->dev_private; unsigned long status, val; - status = kmb_read(lcd, LCD_INT_STATUS); + status = kmb_read_lcd(LCD_INT_STATUS); if (status & LCD_INT_EOF) { /*To DO - handle EOF interrupt? */ - kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_EOF); + kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_EOF); } if (status & LCD_INT_LINE_CMP) { /* clear line compare interrupt */ - kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_LINE_CMP); + kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_LINE_CMP); } if (status & LCD_INT_VERT_COMP) { /* read VSTATUS */ - val = kmb_read(lcd, LCD_VSTATUS); + val = kmb_read_lcd(LCD_VSTATUS); val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); switch (val) { case LCD_VSTATUS_COMPARE_VSYNC: @@ -142,7 +140,7 @@ static irqreturn_t kmb_irq(int irq, void *arg) case LCD_VSTATUS_COMPARE_ACTIVE: case LCD_VSTATUS_COMPARE_FRONT_PORCH: /* clear vertical compare interrupt */ - kmb_write(lcd, LCD_INT_CLEAR, LCD_INT_VERT_COMP); + kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP); drm_handle_vblank(dev, 0); break; } @@ -153,10 +151,8 @@ static irqreturn_t kmb_irq(int irq, void *arg) static void kmb_irq_reset(struct drm_device *drm) { - struct kmb_drm_private *lcd = drm->dev_private; - - kmb_write(lcd, LCD_INT_CLEAR, 0xFFFF); - kmb_write(lcd, LCD_INT_ENABLE, 0); + kmb_write_lcd(LCD_INT_CLEAR, 0xFFFF); + kmb_write_lcd(LCD_INT_ENABLE, 0); } DEFINE_DRM_GEM_CMA_FOPS(fops); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 46be8cb..a431785 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -26,8 +26,10 @@ #ifndef __KMB_DRV_H__ #define __KMB_DRV_H__ -#define KMB_MAX_WIDTH 16384 /*max width in pixels */ -#define KMB_MAX_HEIGHT 16384 /*max height in pixels */ +#include "kmb_regs.h" + +#define KMB_MAX_WIDTH 16384 /*max width in pixels */ +#define KMB_MAX_HEIGHT 16384 /*max height in pixels */ struct kmb_drm_private { struct drm_device drm; @@ -50,7 +52,12 @@ static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) struct blt_layer_config { unsigned char layer_format; }; - +/* + * commenting this out to use hardcoded address for registers + * TODO we may need this later if we decide to get the address from + * the device tree + */ +#ifdef KMB_WRITE static inline void kmb_write(struct kmb_drm_private *lcd, unsigned int reg, u32 value) { @@ -75,6 +82,40 @@ static inline void kmb_write_bits(struct kmb_drm_private *lcd, reg_val |= (value << offset); writel(reg_val, lcd->mmio + reg); } +#endif + +static inline void kmb_write_lcd(unsigned int reg, u32 value) +{ + writel(value, (LCD_BASE_ADDR + reg)); +} + +static inline void kmb_write_mipi(unsigned int reg, u32 value) +{ + writel(value, (MIPI_BASE_ADDR + reg)); +} + +static inline u32 kmb_read_lcd(unsigned int reg) +{ + return readl(LCD_BASE_ADDR + reg); +} + +static inline u32 kmb_read_mipi(unsigned int reg) +{ + return readl(MIPI_BASE_ADDR + reg); +} + +static inline void kmb_write_bits_mipi(unsigned int reg, u32 offset, + u32 num_bits, u32 value) +{ + u32 reg_val = kmb_read_mipi(reg); + u32 mask = (1 << num_bits) - 1; + + value &= mask; + mask <<= offset; + reg_val &= (~mask); + reg_val |= (value << offset); + kmb_write_mipi(reg, reg_val); +} int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 1435ed8..109c83b 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -343,8 +343,8 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ cfg |= MIPI_TX_SECT_DMA_PACKED; - kmb_write(dev_priv, - (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, section)), cfg); + kmb_write_mipi((MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, + section)), cfg); /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections @@ -353,15 +353,13 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, *REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 */ - reg_adr = - MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, - frame_id) + (section / 2) * 4; - kmb_write_bits(dev_priv, reg_adr, (section % 2) * 16, 16, - unpacked_bytes); + reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) + + (section/2)*4; + kmb_write_bits_mipi(reg_adr, (section % 2)*16, 16, unpacked_bytes); /* line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); - kmb_write(dev_priv, reg_adr, height_lines); + kmb_write_mipi(reg_adr, height_lines); return 0; } @@ -437,7 +435,7 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, /*frame generator number of lines */ reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); - kmb_write(dev_priv, reg_adr, fg_cfg->v_active); + kmb_write_mipi(reg_adr, fg_cfg->v_active); /*vsync width */ /* @@ -447,34 +445,31 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, */ offset = (frame_gen % 2) * 16; reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen); - kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->vsync_width); + kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width); /*v backporch - same register config like vsync width */ reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen); - kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_backporch); + kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch); /*v frontporch - same register config like vsync width */ reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen); - kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_frontporch); + kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch); /*v active - same register config like vsync width */ reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen); - kmb_write_bits(dev_priv, reg_adr, offset, 16, fg_cfg->v_active); + kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active); /*hsyc width */ reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); - kmb_write(dev_priv, reg_adr, - (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); + kmb_write_mipi(reg_adr, (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); /*h backporch */ reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); - kmb_write(dev_priv, reg_adr, - (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); + kmb_write_mipi(reg_adr, (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); /*h frontporch */ reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); - kmb_write(dev_priv, reg_adr, - (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); + kmb_write_mipi(reg_adr, (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); /*h active */ reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); @@ -482,19 +477,19 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, val = (fg_cfg->h_active * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); val /= 1000; - kmb_write(dev_priv, reg_adr, val); + kmb_write_mipi(reg_adr, val); /* llp hsync width */ reg_adr = MIPI_TXm_HS_LLP_HSYNC_WIDTHn(ctrl_no, frame_gen); - kmb_write(dev_priv, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); + kmb_write_mipi(reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); /* llp h backporch */ reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen); - kmb_write(dev_priv, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); + kmb_write_mipi(reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); /* llp h frontporch */ reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen); - kmb_write(dev_priv, reg_adr, fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); + kmb_write_mipi(reg_adr, fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); } static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen, diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index f609283..66d6c9f 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -242,16 +242,16 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - kmb_write(lcd, LCD_LAYERn_WIDTH(plane_id), src_w - 1); - kmb_write(lcd, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); - kmb_write(lcd, LCD_LAYERn_COL_START(plane_id), crtc_x); - kmb_write(lcd, LCD_LAYERn_ROW_START(plane_id), crtc_y); + kmb_write_lcd(LCD_LAYERn_WIDTH(plane_id), src_w-1); + kmb_write_lcd(LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write_lcd(LCD_LAYERn_COL_START(plane_id), crtc_x); + kmb_write_lcd(LCD_LAYERn_ROW_START(plane_id), crtc_y); val = set_pixel_format(fb->format->format); val |= set_bits_per_pixel(fb->format); /*CHECKME Leon drvr sets it to 50 try this for now */ val |= LCD_LAYER_FIFO_50; - kmb_write(lcd, LCD_LAYERn_CFG(plane_id), val); + kmb_write_lcd(LCD_LAYERn_CFG(plane_id), val); switch (plane_id) { case LAYER_0: @@ -270,8 +270,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, ctrl |= LCD_CTRL_ENABLE; ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_OUTPUT_ENABLED; - kmb_write(lcd, LCD_CONTROL, ctrl); + | LCD_CTRL_OUTPUT_ENABLED; + kmb_write_lcd(LCD_CONTROL, ctrl); /*TBD check visible? */ @@ -280,24 +280,24 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1; /* disable DMA first */ - kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE); addr = drm_fb_cma_get_gem_addr(fb, plane->state, plane_id); - kmb_write(lcd, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); - kmb_write(lcd, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); + kmb_write_lcd(LCD_LAYERn_DMA_START_ADDR(plane_id), addr); + kmb_write_lcd(LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); width = fb->width; height = fb->height; dma_len = width * height * fb->format->cpp[plane_id]; - kmb_write(lcd, LCD_LAYERn_DMA_LEN(plane_id), dma_len); + kmb_write_lcd(LCD_LAYERn_DMA_LEN(plane_id), dma_len); - kmb_write(lcd, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[plane_id]); - kmb_write(lcd, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width * fb->format->cpp[plane_id])); + kmb_write_lcd(LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[plane_id]); + kmb_write_lcd(LCD_LAYERn_DMA_LINE_WIDTH(plane_id), + (width*fb->format->cpp[plane_id])); /* enable DMA */ - kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + kmb_write_lcd(LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); /* FIXME no doc on how to set output format - may need to change * this later @@ -310,7 +310,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, out_format |= LCD_OUTF_MIPI_RGB_MODE; /* pixel format from LCD_LAYER_CFG */ out_format |= ((val >> 9) & 0x1F); - kmb_write(lcd, LCD_OUT_FORMAT_CFG, out_format); + kmb_write_lcd(LCD_OUT_FORMAT_CFG, out_format); } static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 8715c7b..d1f8174 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -27,6 +27,11 @@ #define __KMB_REGS_H__ #define ENABLE 1 +/*from Data Book section 12.5.8.1 page 4322 */ +#define MIPI_BASE_ADDR (void *)(0x20900000) +/*from Data Book section 12.11.6.1 page 4972 */ +#define LCD_BASE_ADDR (void *)(0x20930000) + /*************************************************************************** * LCD controller control register defines ***************************************************************************/ @@ -388,7 +393,6 @@ /*************************************************************************** * MIPI controller control register defines ***********************************************i****************************/ -#define MIPI_BASE_ADDR (0x20900000) #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) #define MIPI_CTRL_HS_BASE_ADDR (0x400) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:24 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:24 -0700 Subject: [Intel-gfx] [PATCH 12/59] drm/kmb: Part3 of Mipi Tx initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-13-git-send-email-anitha.chrisanthus@intel.com> This initializes the multichannel fifo in the mipi transmitter and sets the LCD to mipi interconnect which connects LCD to MIPI ctrl #6 v2: code review changes to make code simpler Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.h | 25 +++++++++++++++--- drivers/gpu/drm/kmb/kmb_dsi.c | 58 ++++++++++++++++++++++++++++++++++-------- drivers/gpu/drm/kmb/kmb_dsi.h | 3 +++ drivers/gpu/drm/kmb/kmb_regs.h | 30 +++++++++++++++++++--- 4 files changed, 99 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index a431785..ba5b3e0 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -28,8 +28,8 @@ #include "kmb_regs.h" -#define KMB_MAX_WIDTH 16384 /*max width in pixels */ -#define KMB_MAX_HEIGHT 16384 /*max height in pixels */ +#define KMB_MAX_WIDTH 16384 /*max width in pixels */ +#define KMB_MAX_HEIGHT 16384 /*max height in pixels */ struct kmb_drm_private { struct drm_device drm; @@ -84,6 +84,11 @@ static inline void kmb_write_bits(struct kmb_drm_private *lcd, } #endif +static inline void kmb_write(void *reg, u32 value) +{ + writel(value, reg); +} + static inline void kmb_write_lcd(unsigned int reg, u32 value) { writel(value, (LCD_BASE_ADDR + reg)); @@ -105,7 +110,7 @@ static inline u32 kmb_read_mipi(unsigned int reg) } static inline void kmb_write_bits_mipi(unsigned int reg, u32 offset, - u32 num_bits, u32 value) + u32 num_bits, u32 value) { u32 reg_val = kmb_read_mipi(reg); u32 mask = (1 << num_bits) - 1; @@ -117,6 +122,20 @@ static inline void kmb_write_bits_mipi(unsigned int reg, u32 offset, kmb_write_mipi(reg, reg_val); } +static inline void kmb_set_bit_mipi(unsigned int reg, u32 offset) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, reg_val | (1 << offset)); +} + +static inline void kmb_clr_bit_mipi(unsigned int reg, u32 offset) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, reg_val & (~(1 << offset))); +} + int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); #endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 109c83b..92a62e5 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -523,10 +523,41 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen, mipi_tx_fg_cfg_regs(dev_priv, frame_gen, &fg_t_cfg); } +static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) +{ + u32 fifo_size, fifo_rthreshold; + u32 ctrl_no = MIPI_CTRL6; + + /*clear all mc fifo channel sizes and thresholds*/ + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0); + kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0); + + fifo_size = (active_lanes > MIPI_D_LANES_PER_DPHY) ? + MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : + MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC; + /*MC fifo size for virtual channels 0-3 */ + /* + *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 + *REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 + */ + SET_MC_FIFO_CHAN_ALLOC(ctrl_no, vchannel_id, fifo_size); + + /*set threshold to half the fifo size, actual size=size*16*/ + fifo_rthreshold = ((fifo_size + 1) * 8) & BIT_MASK_16; + SET_MC_FIFO_RTHRESHOLD(ctrl_no, vchannel_id, fifo_rthreshold); + + /*enable the MC FIFO channel corresponding to the Virtual Channel */ + kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); +} + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, - struct mipi_ctrl_cfg *ctrl_cfg) + struct mipi_ctrl_cfg *ctrl_cfg) { u32 ret; + u8 active_vchannels = 0; u8 frame_id, sect; u32 bits_per_pclk = 0; u32 word_count = 0; @@ -564,18 +595,23 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, /* set frame specific parameters */ mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, - ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); - /*function for setting frame sepecific parameters will be - * called here - */ - /*bits_per_pclk and word_count will be passed in to this - * function - */ + bits_per_pclk, + word_count, + ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + + active_vchannels++; + /*connect lcd to mipi */ + kmb_write(MSS_CAM_BASE_ADDR + MIPI_TX_MSS_LCD_MIPI_CFG, 1); + + break; } + + if (active_vchannels == 0) + return -EINVAL; + /*Multi-Channel FIFO Configuration*/ + mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id); return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 88b865f..358373a 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -55,6 +55,9 @@ struct kmb_connector { #define MIPI_TX_FRAME_GEN 4 #define MIPI_TX_FRAME_GEN_SECTIONS 4 #define MIPI_CTRL_VIRTUAL_CHANNELS 4 +#define MIPI_D_LANES_PER_DPHY 2 +#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 +#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511 enum mipi_ctrl_num { MIPI_CTRL0 = 0, diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index d1f8174..d6fcead 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -31,6 +31,7 @@ #define MIPI_BASE_ADDR (void *)(0x20900000) /*from Data Book section 12.11.6.1 page 4972 */ #define LCD_BASE_ADDR (void *)(0x20930000) +#define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x10000) /*************************************************************************** * LCD controller control register defines @@ -395,6 +396,9 @@ ***********************************************i****************************/ #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) #define MIPI_CTRL_HS_BASE_ADDR (0x400) + +#define MIPI_TX_HS_CTRL (0x0) +#define MIPI_TX_HS_SYNC_CFG (0x8) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ (0x400*M) + (0x2C*N) + (8*O)) @@ -409,10 +413,10 @@ #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60) #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64) #define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ - (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N)) -#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) (MIPI_TX_HS_FG0_SECT0_LINE_CFG \ - + (0x400*M) + (0x2C*N) + (8*O)) + (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N)) #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) +#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ + (MIPI_TX_HS_FG0_SECT0_LINE_CFG + (0x400*M) + (0x2C*N) + (8*O)) #define MIPI_TX_HS_FG0_NUM_LINES (0x68) #define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \ @@ -451,4 +455,24 @@ #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ + (0x400*M) + (0x4*N)) +#define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) +#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \ + + (0x400*M)) +#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198) +#define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c) +#define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ + (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + (0x400*M) + (0x4*N)) +#define SET_MC_FIFO_CHAN_ALLOC(ctrl, vc, sz) \ + kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, vc/2), \ + (vc % 2)*16, 16, sz) +#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0) +#define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4) +#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ + (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + (0x400*M) + (0x4*N)) +#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \ + kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ + (vc % 2)*16, 16, th) + +#define MIPI_TX_MSS_LCD_MIPI_CFG (0x04) +#define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:25 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:25 -0700 Subject: [Intel-gfx] [PATCH 13/59] drm/kmb: Part4 of Mipi Tx Initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-14-git-send-email-anitha.chrisanthus@intel.com> This initializes the mipi high speed transmitter CTRL and SYNC configuration registers. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 55 ++++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/kmb/kmb_regs.h | 29 +++++++++++++++++++++- 2 files changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 92a62e5..886a8ac 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -553,6 +553,55 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); } +static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) +{ + u32 sync_cfg = 0, ctrl = 0, fg_en; + u32 ctrl_no = MIPI_CTRL6; + + /*MIPI_TX_HS_SYNC_CFG*/ + if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) + sync_cfg |= LINE_SYNC_PKT_ENABLE; + if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) + sync_cfg |= FRAME_COUNTER_ACTIVE; + if (ctrl_cfg->tx_ctrl_cfg.line_counter_active) + sync_cfg |= LINE_COUNTER_ACTIVE; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->v_blanking) + sync_cfg |= DSI_V_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) + sync_cfg |= DSI_HSA_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) + sync_cfg |= DSI_HBP_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) + sync_cfg |= DSI_HFP_BLANKING; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->sync_pulse_eventn) + sync_cfg |= DSI_SYNC_PULSE_EVENTN; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_first_vsa_line) + sync_cfg |= DSI_LPM_FIRST_VSA_LINE; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) + sync_cfg |= DSI_LPM_LAST_VFP_LINE; + /* enable frame generator */ + fg_en = 1 << fg_id; + sync_cfg |= FRAME_GEN_EN(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) + sync_cfg |= ALWAYS_USE_HACT(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) + sync_cfg |= HACT_WAIT_STOP(fg_en); + + /* MIPI_TX_HS_CTRL*/ + ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) + ctrl |= DSI_EOTP_EN; + if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) + ctrl |= DSI_CMD_HFP_EN; + ctrl |= LCD_VC(fg_id); + ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); + /*67 ns stop time*/ + ctrl |= HSEXIT_CNT(0x43); + + kmb_write_mipi(MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); + kmb_write_mipi(MIPI_TXm_HS_CTRL(ctrl_no), ctrl); +} + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, struct mipi_ctrl_cfg *ctrl_cfg) { @@ -596,8 +645,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, /* set frame specific parameters */ mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, bits_per_pclk, - word_count, - ctrl_cfg->lane_rate_mbps, + word_count, ctrl_cfg->lane_rate_mbps, ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); active_vchannels++; @@ -612,6 +660,9 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, return -EINVAL; /*Multi-Channel FIFO Configuration*/ mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id); + + /*Frame Generator Enable */ + mipi_tx_ctrl_cfg(frame_id, ctrl_cfg); return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index d6fcead..9a5f371 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -398,7 +398,35 @@ #define MIPI_CTRL_HS_BASE_ADDR (0x400) #define MIPI_TX_HS_CTRL (0x0) +#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M)) +#define HS_CTRL_EN (1 << 0) +#define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/ +#define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/ +#define ACTIVE_LANES(n) ((n) << 4) +#define LCD_VC(ch) ((ch) << 8) +#define DSI_EOTP_EN (1 << 11) +#define DSI_CMD_HFP_EN (1 << 12) +#define CRC_EN (1 << 14) +#define HSEXIT_CNT(n) ((n) << 16) +#define HSCLKIDLE_CNT (1 << 24) #define MIPI_TX_HS_SYNC_CFG (0x8) +#define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ + + (0x400*M)) +#define LINE_SYNC_PKT_ENABLE (1 << 0) +#define FRAME_COUNTER_ACTIVE (1 << 1) +#define LINE_COUNTER_ACTIVE (1 << 2) +#define DSI_V_BLANKING (1 << 4) +#define DSI_HSA_BLANKING (1 << 5) +#define DSI_HBP_BLANKING (1 << 6) +#define DSI_HFP_BLANKING (1 << 7) +#define DSI_SYNC_PULSE_EVENTN (1 << 8) +#define DSI_LPM_FIRST_VSA_LINE (1 << 9) +#define DSI_LPM_LAST_VFP_LINE (1 << 10) +#define WAIT_ALL_SECT (1 << 11) +#define WAIT_TRIG_POS (1 << 15) +#define ALWAYS_USE_HACT(f) ((f) << 19) +#define FRAME_GEN_EN(f) ((f) << 23) +#define HACT_WAIT_STOP(f) ((f) << 28) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) #define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ (0x400*M) + (0x2C*N) + (8*O)) @@ -454,7 +482,6 @@ #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) #define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ + (0x400*M) + (0x4*N)) - #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) #define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \ + (0x400*M)) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:26 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:26 -0700 Subject: [Intel-gfx] [PATCH 14/59] drm/kmb: Correct address offsets for mipi registers In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-15-git-send-email-anitha.chrisanthus@intel.com> Mipi HS registers start at an additional offset of 0x400 which needs to be added at the register macro definition and not at the read/write function level. v2: replaced calculations with macro to make code simpler Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 16 +++--- drivers/gpu/drm/kmb/kmb_regs.h | 116 ++++++++++++++++++++++++----------------- 2 files changed, 75 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 886a8ac..adcfe81 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -443,20 +443,20 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ - offset = (frame_gen % 2) * 16; - reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen); + offset = (frame_gen % 2)*16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width); - /*v backporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen); + /*v backporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch); - /*v frontporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen); + /*v frontporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch); - /*v active - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen); + /*v active - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active); /*hsyc width */ diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 9a5f371..4d6cf3d 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -395,10 +395,10 @@ * MIPI controller control register defines ***********************************************i****************************/ #define MIPI0_HS_BASE_ADDR (MIPI_BASE_ADDR + 0x400) -#define MIPI_CTRL_HS_BASE_ADDR (0x400) +#define HS_OFFSET(M) ((M + 1) * 0x400) #define MIPI_TX_HS_CTRL (0x0) -#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + (0x400*M)) +#define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) #define HS_CTRL_EN (1 << 0) #define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/ #define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/ @@ -411,7 +411,7 @@ #define HSCLKIDLE_CNT (1 << 24) #define MIPI_TX_HS_SYNC_CFG (0x8) #define MIPI_TXm_HS_SYNC_CFG(M) (MIPI_TX_HS_SYNC_CFG \ - + (0x400*M)) + + HS_OFFSET(M)) #define LINE_SYNC_PKT_ENABLE (1 << 0) #define FRAME_COUNTER_ACTIVE (1 << 1) #define LINE_COUNTER_ACTIVE (1 << 2) @@ -428,75 +428,93 @@ #define FRAME_GEN_EN(f) ((f) << 23) #define HACT_WAIT_STOP(f) ((f) << 28) #define MIPI_TX0_HS_FG0_SECT0_PH (0x40) -#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ - (0x400*M) + (0x2C*N) + (8*O)) -#define MIPI_TX_SECT_WC_MASK (0xffff) -#define MIPI_TX_SECT_VC_MASK (3) -#define MIPI_TX_SECT_VC_SHIFT (22) -#define MIPI_TX_SECT_DT_MASK (0x3f) -#define MIPI_TX_SECT_DT_SHIFT (16) -#define MIPI_TX_SECT_DM_MASK (3) -#define MIPI_TX_SECT_DM_SHIFT (24) -#define MIPI_TX_SECT_DMA_PACKED (1<<26) +#define MIPI_TXm_HS_FGn_SECTo_PH(M, N, O) (MIPI_TX0_HS_FG0_SECT0_PH + \ + HS_OFFSET(M) + (0x2C*N) + (8*O)) +#define MIPI_TX_SECT_WC_MASK (0xffff) +#define MIPI_TX_SECT_VC_MASK (3) +#define MIPI_TX_SECT_VC_SHIFT (22) +#define MIPI_TX_SECT_DT_MASK (0x3f) +#define MIPI_TX_SECT_DT_SHIFT (16) +#define MIPI_TX_SECT_DM_MASK (3) +#define MIPI_TX_SECT_DM_SHIFT (24) +#define MIPI_TX_SECT_DMA_PACKED (1<<26) #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 (0x60) #define MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES1 (0x64) -#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ - (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 + (0x400*M) + (0x2C*N)) +#define MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(M, N) \ + (MIPI_TX_HS_FG0_SECT_UNPACKED_BYTES0 \ + + HS_OFFSET(M) + (0x2C*N)) #define MIPI_TX_HS_FG0_SECT0_LINE_CFG (0x44) -#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ - (MIPI_TX_HS_FG0_SECT0_LINE_CFG + (0x400*M) + (0x2C*N) + (8*O)) +#define MIPI_TXm_HS_FGn_SECTo_LINE_CFG(M, N, O) \ + (MIPI_TX_HS_FG0_SECT0_LINE_CFG + HS_OFFSET(M) \ + + (0x2C*N) + (8*O)) #define MIPI_TX_HS_FG0_NUM_LINES (0x68) -#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) (MIPI_TX_HS_FG0_NUM_LINES + \ - (0x400*M) + (0x2C*N)) +#define MIPI_TXm_HS_FGn_NUM_LINES(M, N) \ + (MIPI_TX_HS_FG0_NUM_LINES + HS_OFFSET(M) \ + + (0x2C*N)) #define MIPI_TX_HS_VSYNC_WIDTHS0 (0x104) -#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) (MIPI_TX_HS_VSYNC_WIDTHS0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_VSYNC_WIDTHn(M, N) \ + (MIPI_TX_HS_VSYNC_WIDTHS0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_V_BACKPORCHES0 (0x16c) -#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) (MIPI_TX_HS_V_BACKPORCHES0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_V_BACKPORCHESn(M, N) \ + (MIPI_TX_HS_V_BACKPORCHES0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_V_FRONTPORCHES0 (0x174) -#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) (MIPI_TX_HS_V_FRONTPORCHES0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_V_FRONTPORCHESn(M, N) \ + (MIPI_TX_HS_V_FRONTPORCHES0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_V_ACTIVE0 (0x17c) -#define MIPI_TXm_HS_V_ACTIVEn(M, N) (MIPI_TX_HS_V_ACTIVE0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_V_ACTIVEn(M, N) \ + (MIPI_TX_HS_V_ACTIVE0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_HSYNC_WIDTH0 (0x10c) -#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_HSYNC_WIDTH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_HSYNC_WIDTHn(M, N) \ + (MIPI_TX_HS_HSYNC_WIDTH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_H_BACKPORCH0 (0x11c) -#define MIPI_TXm_HS_H_BACKPORCHn(M, N) (MIPI_TX_HS_H_BACKPORCH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_H_BACKPORCHn(M, N) \ + (MIPI_TX_HS_H_BACKPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_H_FRONTPORCH0 (0x12c) -#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) (MIPI_TX_HS_H_FRONTPORCH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_H_FRONTPORCHn(M, N) \ + (MIPI_TX_HS_H_FRONTPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_H_ACTIVE0 (0x184) -#define MIPI_TXm_HS_H_ACTIVEn(M, N) (MIPI_TX_HS_H_ACTIVE0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_H_ACTIVEn(M, N) \ + (MIPI_TX_HS_H_ACTIVE0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_LLP_HSYNC_WIDTH0 (0x13c) -#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_LLP_HSYNC_WIDTHn(M, N) \ + (MIPI_TX_HS_LLP_HSYNC_WIDTH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_LLP_H_BACKPORCH0 (0x14c) -#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) (MIPI_TX_HS_LLP_H_BACKPORCH0 + \ - (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_LLP_H_BACKPORCHn(M, N) \ + (MIPI_TX_HS_LLP_H_BACKPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) #define MIPI_TX_HS_LLP_H_FRONTPORCH0 (0x15c) -#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) (MIPI_TX_HS_LLP_H_FRONTPORCH0 \ - + (0x400*M) + (0x4*N)) +#define MIPI_TXm_HS_LLP_H_FRONTPORCHn(M, N) \ + (MIPI_TX_HS_LLP_H_FRONTPORCH0 + HS_OFFSET(M) \ + + (0x4*N)) + #define MIPI_TX_HS_MC_FIFO_CTRL_EN (0x194) -#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) (MIPI_TX_HS_MC_FIFO_CTRL_EN \ - + (0x400*M)) +#define MIPI_TXm_HS_MC_FIFO_CTRL_EN(M) \ + (MIPI_TX_HS_MC_FIFO_CTRL_EN + HS_OFFSET(M)) + #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198) #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c) #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ - (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + (0x400*M) + (0x4*N)) + (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \ + + (0x4*N)) #define SET_MC_FIFO_CHAN_ALLOC(ctrl, vc, sz) \ - kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, vc/2), \ - (vc % 2)*16, 16, sz) + kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \ + vc/2), (vc % 2)*16, 16, sz) #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0) #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4) -#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ - (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + (0x400*M) + (0x4*N)) -#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \ +#define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ + (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \ + + (0x4*N)) +#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \ kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:27 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:27 -0700 Subject: [Intel-gfx] [PATCH 15/59] drm/kmb: Part5 of Mipi Tx Intitialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-16-git-send-email-anitha.chrisanthus@intel.com> This is part1 of DPHY initialization. v2: remove kmb_write() as the function provides no benefit over calling writel() directly. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.h | 5 - drivers/gpu/drm/kmb/kmb_dsi.c | 346 ++++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/kmb/kmb_dsi.h | 10 ++ drivers/gpu/drm/kmb/kmb_regs.h | 48 +++++- 4 files changed, 376 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index ba5b3e0..434be1a 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -84,11 +84,6 @@ static inline void kmb_write_bits(struct kmb_drm_private *lcd, } #endif -static inline void kmb_write(void *reg, u32 value) -{ - writel(value, reg); -} - static inline void kmb_write_lcd(unsigned int reg, u32 value) { writel(value, (LCD_BASE_ADDR + reg)); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index adcfe81..d6cd1f9 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -47,6 +47,13 @@ #define MIPI_TX_REF_CLK_KHZ 24000 #define MIPI_TX_CFG_CLK_KHZ 24000 +/*DPHY Tx test codes*/ +#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 +#define TEST_CODE_PLL_ANALOG_PROG 0x1F +#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 +#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 +#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 + /* * These are added here only temporarily for testing, * these will eventually go to the device tree sections, @@ -107,6 +114,77 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { }; +typedef struct{ + uint16_t default_bit_rate_mbps; + uint8_t hsfreqrange_code; +} mipi_hs_freq_range_cfg; + +static mipi_hs_freq_range_cfg + mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = { + {.default_bit_rate_mbps = 80, .hsfreqrange_code = 0x00}, + {.default_bit_rate_mbps = 90, .hsfreqrange_code = 0x10}, + {.default_bit_rate_mbps = 100, .hsfreqrange_code = 0x20}, + {.default_bit_rate_mbps = 110, .hsfreqrange_code = 0x30}, + {.default_bit_rate_mbps = 120, .hsfreqrange_code = 0x01}, + {.default_bit_rate_mbps = 130, .hsfreqrange_code = 0x11}, + {.default_bit_rate_mbps = 140, .hsfreqrange_code = 0x21}, + {.default_bit_rate_mbps = 150, .hsfreqrange_code = 0x31}, + {.default_bit_rate_mbps = 160, .hsfreqrange_code = 0x02}, + {.default_bit_rate_mbps = 170, .hsfreqrange_code = 0x12}, + {.default_bit_rate_mbps = 180, .hsfreqrange_code = 0x22}, + {.default_bit_rate_mbps = 190, .hsfreqrange_code = 0x32}, + {.default_bit_rate_mbps = 205, .hsfreqrange_code = 0x03}, + {.default_bit_rate_mbps = 220, .hsfreqrange_code = 0x13}, + {.default_bit_rate_mbps = 235, .hsfreqrange_code = 0x23}, + {.default_bit_rate_mbps = 250, .hsfreqrange_code = 0x33}, + {.default_bit_rate_mbps = 275, .hsfreqrange_code = 0x04}, + {.default_bit_rate_mbps = 300, .hsfreqrange_code = 0x14}, + {.default_bit_rate_mbps = 325, .hsfreqrange_code = 0x25}, + {.default_bit_rate_mbps = 350, .hsfreqrange_code = 0x35}, + {.default_bit_rate_mbps = 400, .hsfreqrange_code = 0x05}, + {.default_bit_rate_mbps = 450, .hsfreqrange_code = 0x16}, + {.default_bit_rate_mbps = 500, .hsfreqrange_code = 0x26}, + {.default_bit_rate_mbps = 550, .hsfreqrange_code = 0x37}, + {.default_bit_rate_mbps = 600, .hsfreqrange_code = 0x07}, + {.default_bit_rate_mbps = 650, .hsfreqrange_code = 0x18}, + {.default_bit_rate_mbps = 700, .hsfreqrange_code = 0x28}, + {.default_bit_rate_mbps = 750, .hsfreqrange_code = 0x39}, + {.default_bit_rate_mbps = 800, .hsfreqrange_code = 0x09}, + {.default_bit_rate_mbps = 850, .hsfreqrange_code = 0x19}, + {.default_bit_rate_mbps = 900, .hsfreqrange_code = 0x29}, + {.default_bit_rate_mbps = 1000, .hsfreqrange_code = 0x0A}, + {.default_bit_rate_mbps = 1050, .hsfreqrange_code = 0x1A}, + {.default_bit_rate_mbps = 1100, .hsfreqrange_code = 0x2A}, + {.default_bit_rate_mbps = 1150, .hsfreqrange_code = 0x3B}, + {.default_bit_rate_mbps = 1200, .hsfreqrange_code = 0x0B}, + {.default_bit_rate_mbps = 1250, .hsfreqrange_code = 0x1B}, + {.default_bit_rate_mbps = 1300, .hsfreqrange_code = 0x2B}, + {.default_bit_rate_mbps = 1350, .hsfreqrange_code = 0x3C}, + {.default_bit_rate_mbps = 1400, .hsfreqrange_code = 0x0C}, + {.default_bit_rate_mbps = 1450, .hsfreqrange_code = 0x1C}, + {.default_bit_rate_mbps = 1500, .hsfreqrange_code = 0x2C}, + {.default_bit_rate_mbps = 1550, .hsfreqrange_code = 0x3D}, + {.default_bit_rate_mbps = 1600, .hsfreqrange_code = 0x0D}, + {.default_bit_rate_mbps = 1650, .hsfreqrange_code = 0x1D}, + {.default_bit_rate_mbps = 1700, .hsfreqrange_code = 0x2E}, + {.default_bit_rate_mbps = 1750, .hsfreqrange_code = 0x3E}, + {.default_bit_rate_mbps = 1800, .hsfreqrange_code = 0x0E}, + {.default_bit_rate_mbps = 1850, .hsfreqrange_code = 0x1E}, + {.default_bit_rate_mbps = 1900, .hsfreqrange_code = 0x2F}, + {.default_bit_rate_mbps = 1950, .hsfreqrange_code = 0x3F}, + {.default_bit_rate_mbps = 2000, .hsfreqrange_code = 0x0F}, + {.default_bit_rate_mbps = 2050, .hsfreqrange_code = 0x40}, + {.default_bit_rate_mbps = 2100, .hsfreqrange_code = 0x41}, + {.default_bit_rate_mbps = 2150, .hsfreqrange_code = 0x42}, + {.default_bit_rate_mbps = 2200, .hsfreqrange_code = 0x43}, + {.default_bit_rate_mbps = 2250, .hsfreqrange_code = 0x44}, + {.default_bit_rate_mbps = 2300, .hsfreqrange_code = 0x45}, + {.default_bit_rate_mbps = 2350, .hsfreqrange_code = 0x46}, + {.default_bit_rate_mbps = 2400, .hsfreqrange_code = 0x47}, + {.default_bit_rate_mbps = 2450, .hsfreqrange_code = 0x48}, + {.default_bit_rate_mbps = 2500, .hsfreqrange_code = 0x49} +}; + static enum drm_mode_status kmb_dsi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -344,7 +422,7 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ cfg |= MIPI_TX_SECT_DMA_PACKED; kmb_write_mipi((MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); + section)), cfg); /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections @@ -354,8 +432,8 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 */ reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) - + (section/2)*4; - kmb_write_bits_mipi(reg_adr, (section % 2)*16, 16, unpacked_bytes); + + (section / 2) * 4; + kmb_write_bits_mipi(reg_adr, (section % 2) * 16, 16, unpacked_bytes); /* line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); @@ -443,20 +521,20 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ - offset = (frame_gen % 2)*16; - reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2); + offset = (frame_gen % 2) * 16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width); - /*v backporch - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2); + /*v backporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch); - /*v frontporch - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2); + /*v frontporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch); - /*v active - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2); + /*v active - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active); /*hsyc width */ @@ -528,7 +606,7 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) u32 fifo_size, fifo_rthreshold; u32 ctrl_no = MIPI_CTRL6; - /*clear all mc fifo channel sizes and thresholds*/ + /*clear all mc fifo channel sizes and thresholds */ kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); @@ -536,8 +614,7 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0); fifo_size = (active_lanes > MIPI_D_LANES_PER_DPHY) ? - MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : - MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC; + MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC; /*MC fifo size for virtual channels 0-3 */ /* *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 @@ -545,7 +622,7 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) */ SET_MC_FIFO_CHAN_ALLOC(ctrl_no, vchannel_id, fifo_size); - /*set threshold to half the fifo size, actual size=size*16*/ + /*set threshold to half the fifo size, actual size=size*16 */ fifo_rthreshold = ((fifo_size + 1) * 8) & BIT_MASK_16; SET_MC_FIFO_RTHRESHOLD(ctrl_no, vchannel_id, fifo_rthreshold); @@ -558,7 +635,7 @@ static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6; - /*MIPI_TX_HS_SYNC_CFG*/ + /*MIPI_TX_HS_SYNC_CFG */ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) @@ -587,15 +664,15 @@ static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) sync_cfg |= HACT_WAIT_STOP(fg_en); - /* MIPI_TX_HS_CTRL*/ - ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + /* MIPI_TX_HS_CTRL */ + ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) ctrl |= DSI_EOTP_EN; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) ctrl |= DSI_CMD_HFP_EN; ctrl |= LCD_VC(fg_id); ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); - /*67 ns stop time*/ + /*67 ns stop time */ ctrl |= HSEXIT_CNT(0x43); kmb_write_mipi(MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); @@ -603,7 +680,7 @@ static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) } static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, - struct mipi_ctrl_cfg *ctrl_cfg) + struct mipi_ctrl_cfg *ctrl_cfg) { u32 ret; u8 active_vchannels = 0; @@ -644,21 +721,21 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, /* set frame specific parameters */ mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + bits_per_pclk, + word_count, ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); active_vchannels++; /*connect lcd to mipi */ - kmb_write(MSS_CAM_BASE_ADDR + MIPI_TX_MSS_LCD_MIPI_CFG, 1); + writel(1, MSS_CAM_BASE_ADDR + MIPI_TX_MSS_LCD_MIPI_CFG); break; } if (active_vchannels == 0) return -EINVAL; - /*Multi-Channel FIFO Configuration*/ + /*Multi-Channel FIFO Configuration */ mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id); /*Frame Generator Enable */ @@ -666,6 +743,222 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, return ret; } +static void test_mode_send(u32 dphy_no, u32 test_code, u32 test_data) +{ + /*send the test code first */ + /* Steps for code: + * - set testclk HIGH + * - set testdin with test code + * - set testen HIGH + * - set testclk LOW + * - set testen LOW + */ + SET_DPHY_TEST_CTRL1_CLK(dphy_no); + SET_TEST_DIN0_3(dphy_no, test_code); + SET_DPHY_TEST_CTRL1_EN(dphy_no); + CLR_DPHY_TEST_CTRL1_CLK(dphy_no); + CLR_DPHY_TEST_CTRL1_EN(dphy_no); + + /*send the test data next */ + /* Steps for data: + * - set testen LOW + * - set testclk LOW + * - set testdin with data + * - set testclk HIGH + */ + CLR_DPHY_TEST_CTRL1_EN(dphy_no); + CLR_DPHY_TEST_CTRL1_CLK(dphy_no); + SET_TEST_DIN0_3(dphy_no, test_data); + SET_DPHY_TEST_CTRL1_CLK(dphy_no); +} + +static inline void set_test_mode_src_osc_freq_target_low_bits(u32 dphy_no, + u32 freq) +{ + /*typical rise/fall time=166, + * refer Table 1207 databook,sr_osc_freq_target[7:0 + */ + test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); +} + +static inline void set_test_mode_slew_rate_calib_en(u32 dphy_no) +{ + /*do not bypass slew rate calibration algorithm */ + /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ + test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, + (0x03 | (1 << 6))); +} + +static inline void set_test_mode_src_osc_freq_target_hi_bits(u32 dphy_no, + u32 freq) +{ + u32 data; + /*typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[11:7 + */ + data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ + test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); +} + +static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, + enum dphy_mode mode) +{ + u32 test_code = 0; + u32 test_data = 0, val; + int i; + + /*Set D-PHY in shutdown mode */ + /*assert RSTZ signal */ + CLR_DPHY_INIT_CTRL0(dphy_no, RESETZ); + /* assert SHUTDOWNZ signal */ + CLR_DPHY_INIT_CTRL0(dphy_no, SHUTDOWNZ); + + /*Init D-PHY_n */ + /*Pulse testclear signal to make sure the d-phy configuration starts + * from a clean base + */ + SET_DPHY_TEST_CTRL0(dphy_no); + /*TODO may need to add 15ns delay here */ + CLR_DPHY_TEST_CTRL0(dphy_no); + + /*Set mastermacro bit - Master or slave mode */ + test_code = TEST_CODE_MULTIPLE_PHY_CTRL; + /*DPHY has its own clock lane enabled (master) */ + if (mode == MIPI_DPHY_MASTER) + test_data = 0x01; + else + test_data = 0x00; + + /*send the test code and data */ + test_mode_send(dphy_no, test_code, test_data); + + /*Set the lane data rate */ + for (i = 0; i < MIPI_DPHY_DEFAULT_BIT_RATES; i++) { + if (mipi_hs_freq_range[i].default_bit_rate_mbps < + cfg->lane_rate_mbps) + continue; + /* send the test code and data */ + /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ + test_mode_send(dphy_no, TEST_CODE_HS_FREQ_RANGE_CFG, + (mipi_hs_freq_range[i].hsfreqrange_code + & 0x7f) | (1 << 7)); + break; + } + /* + * High-Speed Tx Slew Rate Calibration + * BitRate: > 1.5 Gbps && <= 2.5 Gbps: slew rate control OFF + */ + if (cfg->lane_rate_mbps > 1500) { + /*bypass slew rate calibration algorithm */ + /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr */ + test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, + 0x02); + + /* disable slew rate calibration */ + test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, + 0x00); + } else if (cfg->lane_rate_mbps > 1000) { + /*BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON + * typical rise/fall times: 166 ps + */ + + /*do not bypass slew rate calibration algorithm */ + set_test_mode_slew_rate_calib_en(dphy_no); + + /* enable slew rate calibration */ + test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, + 0x01); + + /*set sr_osc_freq_target[6:0] */ + /*typical rise/fall time=166, refer Table 1207 databook */ + set_test_mode_src_osc_freq_target_low_bits(dphy_no, 0x72f); + /*set sr_osc_freq_target[11:7] */ + set_test_mode_src_osc_freq_target_hi_bits(dphy_no, 0x72f); + } else { + /*lane_rate_mbps <= 1000 Mbps */ + /*BitRate: <= 1 Gbps: + * - slew rate control ON + * - typical rise/fall times: 225 ps + */ + /*do not bypass slew rate calibration algorithm */ + set_test_mode_slew_rate_calib_en(dphy_no); + /* enable slew rate calibration */ + test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, + 0x01); + + /*typical rise/fall time=255, refer Table 1207 databook */ + set_test_mode_src_osc_freq_target_low_bits(dphy_no, 0x523); + /*set sr_osc_freq_target[11:7] */ + set_test_mode_src_osc_freq_target_hi_bits(dphy_no, 0x523); + } + + /*Set cfgclkfreqrange */ + val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; + SET_DPHY_FREQ_CTRL0_3(dphy_no, val); + + /*Enable config clk for the corresponding d-phy */ + kmb_set_bit_mipi(DPHY_CFG_CLK_EN, dphy_no); + + /* PLL setup */ + if (mode == MIPI_DPHY_MASTER) { + /*Set PLL regulator in bypass */ + test_mode_send(dphy_no, TEST_CODE_PLL_ANALOG_PROG, 0x01); + + /*TODO - PLL Parameters Setup */ + } + + /*Send NORMAL OPERATION test code */ + test_mode_send(dphy_no, 0x00, 0x00); + + /* Configure BASEDIR for data lanes + * NOTE: basedir only applies to LANE_0 of each D-PHY. + * The other lanes keep their direction based on the D-PHY type, + * either Rx or Tx. + * bits[5:0] - BaseDir: 1 = Rx + * bits[9:6] - BaseDir: 0 = Tx + */ + kmb_clr_bit_mipi(DPHY_INIT_CTRL2, dphy_no); + + /* Enable CLOCK LANE - */ + /*clock lane should be enabled regardless of the direction set for + * the D-PHY (Rx/Tx) + */ + kmb_clr_bit_mipi(DPHY_INIT_CTRL2, 12 + dphy_no); + + /* enable DATA LANES */ + kmb_write_bits_mipi(DPHY_ENABLE, dphy_no * 2, 2, + ((1 << cfg->active_lanes) - 1)); +} + +static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg) +{ + u32 dphy_no = MIPI_DPHY6; + + /*multiple D-PHYs needed */ + if (cfg->active_lanes > MIPI_DPHY_D_LANES) { + /* + *Initialization for Tx aggregation mode is done according to + *http://dub30.ir.intel.com/bugzilla/show_bug.cgi?id=27785#c12: + *a. start init PHY1 + *b. poll for PHY1 FSM state LOCK + * b1. reg addr 0x03[3:0] - state_main[3:0] == 5 (LOCK) + *c. poll for PHY1 calibrations done : + * c1. termination calibration lower section: addr 0x22[5] + * - rescal_done + * c2. slewrate calibration (if data rate < = 1500 Mbps): + * addr 0xA7[3:2] - srcal_done, sr_finished + *d. start init PHY0 + *e. poll for PHY0 stopstate + *f. poll for PHY1 stopstate + */ + /*PHY #N+1 ('slave') */ + dphy_init_sequence(cfg, dphy_no + 1, MIPI_DPHY_SLAVE); + /*TODO PHY #N master */ + } + /*TODO- Single DPHY */ + return 0; +} + void kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; @@ -708,4 +1001,7 @@ void kmb_dsi_init(struct drm_device *dev) /* initialize mipi controller */ mipi_tx_init_cntrl(dev_priv, &mipi_tx_init_cfg); + + /*d-phy initialization */ + mipi_tx_init_dphy(&mipi_tx_init_cfg); } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 358373a..d878d27 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -58,6 +58,11 @@ struct kmb_connector { #define MIPI_D_LANES_PER_DPHY 2 #define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 #define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511 +#define MIPI_DPHY_D_LANES 2 /* 2 Data Lanes per D-PHY*/ +#define MIPI_DPHY_DEFAULT_BIT_RATES 63 + +/*DPHY Tx test codes */ +#define TEST_CODE_MULTIPLE_PHY_CTRL 0x03 enum mipi_ctrl_num { MIPI_CTRL0 = 0, @@ -194,6 +199,11 @@ enum mipi_dsi_data_type { DSI_LP_DT_RESERVED_3F = 0x3f }; +enum dphy_mode { + MIPI_DPHY_SLAVE = 0, + MIPI_DPHY_MASTER +}; + struct mipi_data_type_params { uint8_t size_constraint_pixels; uint8_t size_constraint_bytes; diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 4d6cf3d..5921f709 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -27,6 +27,7 @@ #define __KMB_REGS_H__ #define ENABLE 1 +#define DISABLE 0 /*from Data Book section 12.5.8.1 page 4322 */ #define MIPI_BASE_ADDR (void *)(0x20900000) /*from Data Book section 12.11.6.1 page 4972 */ @@ -400,8 +401,10 @@ #define MIPI_TX_HS_CTRL (0x0) #define MIPI_TXm_HS_CTRL(M) (MIPI_TX_HS_CTRL + HS_OFFSET(M)) #define HS_CTRL_EN (1 << 0) -#define HS_CTRL_CSIDSIN (1 << 2) /*1:CSI 0:DSI*/ -#define TX_SOURCE (1 << 3) /*1:LCD, 0:DMA*/ +/*1:CSI 0:DSI */ +#define HS_CTRL_CSIDSIN (1 << 2) +/*1:LCD, 0:DMA */ +#define TX_SOURCE (1 << 3) #define ACTIVE_LANES(n) ((n) << 4) #define LCD_VC(ch) ((ch) << 8) #define DSI_EOTP_EN (1 << 11) @@ -518,6 +521,45 @@ kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th) +/* D-PHY regs */ +#define DPHY_ENABLE (0x100) +#define DPHY_INIT_CTRL0 (0x104) +#define SHUTDOWNZ 0 +#define RESETZ 12 +#define DPHY_INIT_CTRL2 (0x10c) +#define SET_DPHY_INIT_CTRL0(dphy, offset) \ + kmb_set_bit_mipi(DPHY_INIT_CTRL0, \ + (dphy+offset)) +#define CLR_DPHY_INIT_CTRL0(dphy, offset) \ + kmb_clr_bit_mipi(DPHY_INIT_CTRL0, \ + (dphy+offset)) +#define DPHY_FREQ_CTRL0_3 (0x11c) +#define SET_DPHY_FREQ_CTRL0_3(dphy, val) \ + kmb_write_bits_mipi(DPHY_FREQ_CTRL0_3 \ + + ((dphy/4)*4), (dphy % 4) * 8, \ + 6, val) +#define DPHY_TEST_CTRL0 (0x154) +#define SET_DPHY_TEST_CTRL0(dphy) kmb_set_bit_mipi(DPHY_TEST_CTRL0, \ + (dphy)) +#define CLR_DPHY_TEST_CTRL0(dphy) kmb_clr_bit_mipi(DPHY_TEST_CTRL0, \ + (dphy)) +#define DPHY_TEST_CTRL1 (0x158) +#define SET_DPHY_TEST_CTRL1_CLK(dphy) kmb_set_bit_mipi(DPHY_TEST_CTRL1, \ + (dphy)) +#define CLR_DPHY_TEST_CTRL1_CLK(dphy) kmb_clr_bit_mipi(DPHY_TEST_CTRL1, \ + (dphy)) +#define SET_DPHY_TEST_CTRL1_EN(dphy) kmb_set_bit_mipi(DPHY_TEST_CTRL1, \ + (dphy+12)) +#define CLR_DPHY_TEST_CTRL1_EN(dphy) kmb_clr_bit_mipi(DPHY_TEST_CTRL1, \ + (dphy+12)) +#define DPHY_TEST_DIN0_3 (0x15c) +#define SET_TEST_DIN0_3(dphy, val) kmb_write_mipi(DPHY_TEST_DIN0_3 + \ + 4, ((val) << (((dphy)%4)*8))) +#define DPHY_TEST_DOUT0_3 (0x168) +#define GET_TEST_DOUT0_3(dphy) (readl(DPHY_TEST_DOUT0_3 + 4) \ + >> (((dphy)%4)*8) & 0xff) +#define DPHY_CFG_CLK_EN (0x18c) + #define MIPI_TX_MSS_LCD_MIPI_CFG (0x04) -#define BIT_MASK_16 (0xffff) +#define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:29 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:29 -0700 Subject: [Intel-gfx] [PATCH 17/59] drm/kmb: Part7 of Mipi Tx Initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-18-git-send-email-anitha.chrisanthus@intel.com> This completes the DPHY initialization and Tx initialization. v2: minor code review changes Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 65 ++++++++++++++++++++++++++++++++++++++---- drivers/gpu/drm/kmb/kmb_dsi.h | 18 ++++++++++++ drivers/gpu/drm/kmb/kmb_regs.h | 15 ++++++++-- 3 files changed, 91 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index b7f23af..51bec35 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -48,6 +48,7 @@ #define MIPI_TX_CFG_CLK_KHZ 24000 /*DPHY Tx test codes*/ +#define TEST_CODE_FSM_CONTROL 0x03 #define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E #define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F #define TEST_CODE_PLL_VCO_CTRL 0x12 @@ -1081,10 +1082,10 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, cfg->lane_rate_mbps/2); /*Set clksel */ - kmb_write_bits_mipi(DPHY_INIT_CTRL1, 18, 2, 0x01); + kmb_write_bits_mipi(DPHY_INIT_CTRL1, PLL_CLKSEL_0, 2, 0x01); /*Set pll_shadow_control */ - kmb_write_bits_mipi(DPHY_INIT_CTRL1, 16, 1, 0x01); + kmb_set_bit_mipi(DPHY_INIT_CTRL1, PLL_SHADOW_CTRL); } /*Send NORMAL OPERATION test code */ @@ -1107,7 +1108,48 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, /* enable DATA LANES */ kmb_write_bits_mipi(DPHY_ENABLE, dphy_no * 2, 2, - ((1 << cfg->active_lanes) - 1)); + ((1 << cfg->active_lanes) - 1)); + + /*Take D-PHY out of shutdown mode */ + /* deassert SHUTDOWNZ signal*/ + SET_DPHY_INIT_CTRL0(dphy_no, SHUTDOWNZ); + /*deassert RSTZ signal */ + SET_DPHY_INIT_CTRL0(dphy_no, RESETZ); +} + +static void dphy_wait_fsm(u32 dphy_no, enum dphy_tx_fsm fsm_state) +{ + enum dphy_tx_fsm val = DPHY_TX_POWERDWN; + + do { + test_mode_send(dphy_no, TEST_CODE_FSM_CONTROL, 0x80); + /*TODO-need to add a time out and return failure */ + val = GET_TEST_DOUT0_3(dphy_no); + } while (val != fsm_state); + +} + +static u32 wait_init_done(u32 dphy_no, u32 active_lanes) +{ + u32 stopstatedata = 0; + u32 data_lanes = (1 << active_lanes) - 1; + + do { + stopstatedata = GET_STOPSTATE_DATA(dphy_no); + /*TODO-need to add a time out and return failure */ + } while (stopstatedata != data_lanes); + + return 0; +} + +static u32 wait_pll_lock(u32 dphy_no) +{ + do { + ; + /*TODO-need to add a time out and return failure */ + } while (!GET_PLL_LOCK(dphy_no)); + + return 0; } static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg) @@ -1133,9 +1175,22 @@ static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg) */ /*PHY #N+1 ('slave') */ dphy_init_sequence(cfg, dphy_no + 1, MIPI_DPHY_SLAVE); - /*TODO PHY #N master */ + + dphy_wait_fsm(dphy_no + 1, DPHY_TX_LOCK); + + /*PHY #N master*/ + dphy_init_sequence(cfg, dphy_no, MIPI_DPHY_MASTER); + /* wait for DPHY init to complete */ + wait_init_done(dphy_no, MIPI_DPHY_D_LANES); + wait_init_done(dphy_no + 1, + cfg->active_lanes - MIPI_DPHY_D_LANES); + wait_pll_lock(dphy_no); + wait_pll_lock(dphy_no + 1); + } else { /* Single DPHY */ + dphy_init_sequence(cfg, dphy_no, MIPI_DPHY_MASTER); + wait_init_done(dphy_no, cfg->active_lanes); + wait_pll_lock(dphy_no); } - /*TODO- Single DPHY */ return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index d878d27..eb38ae7 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -204,12 +204,30 @@ enum dphy_mode { MIPI_DPHY_MASTER }; +enum dphy_tx_fsm { + DPHY_TX_POWERDWN = 0, + DPHY_TX_BGPON, + DPHY_TX_TERMCAL, + DPHY_TX_TERMCALUP, + DPHY_TX_OFFSETCAL, + DPHY_TX_LOCK, + DPHY_TX_SRCAL, + DPHY_TX_IDLE, + DPHY_TX_ULP, + DPHY_TX_LANESTART, + DPHY_TX_CLKALIGN, + DPHY_TX_DDLTUNNING, + DPHY_TX_ULP_FORCE_PLL, + DPHY_TX_LOCK_LOSS +}; + struct mipi_data_type_params { uint8_t size_constraint_pixels; uint8_t size_constraint_bytes; uint8_t pixels_per_pclk; uint8_t bits_per_pclk; }; + struct mipi_tx_dsi_cfg { uint8_t hfp_blank_en; /*horizontal front porch blanking enable */ uint8_t eotp_en; /*End of transmission packet enable */ diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index dedee04..b6f6acf 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -524,9 +524,11 @@ /* D-PHY regs */ #define DPHY_ENABLE (0x100) #define DPHY_INIT_CTRL0 (0x104) -#define DPHY_INIT_CTRL1 (0x108) #define SHUTDOWNZ 0 #define RESETZ 12 +#define DPHY_INIT_CTRL1 (0x108) +#define PLL_CLKSEL_0 18 +#define PLL_SHADOW_CTRL 16 #define DPHY_INIT_CTRL2 (0x10c) #define SET_DPHY_INIT_CTRL0(dphy, offset) \ kmb_set_bit_mipi(DPHY_INIT_CTRL0, \ @@ -540,6 +542,12 @@ kmb_write_bits_mipi(DPHY_FREQ_CTRL0_3 \ + ((dphy/4)*4), (dphy % 4) * 8, \ 6, val) + +#define MIPI_DPHY_STAT0_3 (0x134) +#define GET_STOPSTATE_DATA(dphy) \ + (((kmb_read_mipi(MIPI_DPHY_STAT0_3 + \ + (dphy/4)*4)) \ + >> (((dphy % 4)*8)+4)) & 0x03) #define DPHY_TEST_CTRL0 (0x154) #define SET_DPHY_TEST_CTRL0(dphy) kmb_set_bit_mipi(DPHY_TEST_CTRL0, \ (dphy)) @@ -558,8 +566,11 @@ #define SET_TEST_DIN0_3(dphy, val) kmb_write_mipi(DPHY_TEST_DIN0_3 + \ 4, ((val) << (((dphy)%4)*8))) #define DPHY_TEST_DOUT0_3 (0x168) -#define GET_TEST_DOUT0_3(dphy) (readl(DPHY_TEST_DOUT0_3 + 4) \ +#define GET_TEST_DOUT0_3(dphy) (kmb_read_mipi(DPHY_TEST_DOUT0_3 + 4) \ >> (((dphy)%4)*8) & 0xff) +#define DPHY_PLL_LOCK (0x188) +#define GET_PLL_LOCK(dphy) (kmb_read_mipi(DPHY_PLL_LOCK) \ + & (1 << (dphy - MIPI_DPHY6))) #define DPHY_CFG_CLK_EN (0x18c) #define MIPI_TX_MSS_LCD_MIPI_CFG (0x04) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:28 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:28 -0700 Subject: [Intel-gfx] [PATCH 16/59] drm/kmb: Part6 of Mipi Tx Initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-17-git-send-email-anitha.chrisanthus@intel.com> This is part2 of DPHY initialization- sets up DPHY PLLs. v2: simplified mipi_tx_get_vco_params() based on review v3: added WARN_ON for invalid freq v4: fixed bug in mipi_tx_get_vco_params Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 194 +++++++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/kmb/kmb_regs.h | 2 + 2 files changed, 189 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index d6cd1f9..b7f23af 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -48,11 +48,33 @@ #define MIPI_TX_CFG_CLK_KHZ 24000 /*DPHY Tx test codes*/ -#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 -#define TEST_CODE_PLL_ANALOG_PROG 0x1F -#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 -#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 -#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 +#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E +#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F +#define TEST_CODE_PLL_VCO_CTRL 0x12 +#define TEST_CODE_PLL_GMP_CTRL 0x13 +#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14 +#define TEST_CODE_PLL_LOCK_FILTER 0x15 +#define TEST_CODE_PLL_UNLOCK_FILTER 0x16 +#define TEST_CODE_PLL_INPUT_DIVIDER 0x17 +#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18 +#define PLL_FEEDBACK_DIVIDER_HIGH (1 << 7) +#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 +#define PLL_N_OVR_EN (1 << 4) +#define PLL_M_OVR_EN (1 << 5) +#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C +#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D +#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 +#define TEST_CODE_PLL_ANALOG_PROG 0x1F +#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 +#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 +#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 + +/* D-Phy params */ +#define PLL_N_MIN 0 +#define PLL_N_MAX 15 +#define PLL_M_MIN 62 +#define PLL_M_MAX 623 +#define PLL_FVCO_MAX 1250 /* * These are added here only temporarily for testing, @@ -800,8 +822,158 @@ static inline void set_test_mode_src_osc_freq_target_hi_bits(u32 dphy_no, test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); } +struct vco_params { + u32 freq; + u32 range; + u32 divider; +}; + +static struct vco_params vco_table[] = { + {52, 0x3f, 8}, + {80, 0x39, 8}, + {105, 0x2f, 4}, + {160, 0x29, 4}, + {210, 0x1f, 2}, + {320, 0x19, 2}, + {420, 0x0f, 1}, + {630, 0x09, 1}, + {1100, 0x03, 1}, + {0xffff, 0x01, 1}, +}; + +static void mipi_tx_get_vco_params(struct vco_params *vco) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vco_table); i++) { + if (vco->freq < vco_table[i].freq) { + *vco = vco_table[i]; + return; + } + } + WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq); +} + +static void mipi_tx_pll_setup(u32 dphy_no, u32 ref_clk_mhz, u32 target_freq_mhz) +{ + /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz + * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) + * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) + * n: - valid range [0 15] + * N: - N = n + 1 + * -valid range: [1 16] + * -conditions: - (pll_ref_clk / N) >= 2 MHz + * -(pll_ref_clk / N) <= 8 MHz + * m: valid range [62 623] + * M: - M = m + 2 + * -valid range [64 625] + * -Fvco = (M/N) * pll_ref_clk + */ + struct vco_params vco_p = { + .range = 0, + .divider = 1, + }; + u32 best_n = 0, best_m = 0; + u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq; + u32 best_freq_delta = 3000; + + vco_p.freq = target_freq_mhz; + mipi_tx_get_vco_params(&vco_p); + /*search pll n parameter */ + for (n = PLL_N_MIN; n <= PLL_N_MAX; n++) { + /*calculate the pll input frequency division ratio + * multiply by 1000 for precision - + * no floating point, add n for rounding + */ + div = ((ref_clk_mhz * 1000) + n)/(n+1); + /*found a valid n parameter */ + if ((div < 2000 || div > 8000)) + continue; + /*search pll m parameter */ + for (m = PLL_M_MIN; m <= PLL_M_MAX; m++) { + /*calculate the Fvco(DPHY PLL output frequency) + * using the current n,m params + */ + freq = div * (m + 2); + freq /= 1000; + /* trim the potential pll freq to max supported*/ + if (freq > PLL_FVCO_MAX) + continue; + + delta = abs(freq - target_freq_mhz); + /*select the best (closest to target pll freq) + * n,m parameters so far + */ + if (delta < best_freq_delta) { + best_n = n; + best_m = m; + best_freq_delta = delta; + } + } + } + + /*Program vco_cntrl parameter + *PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr, + * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en + */ + test_mode_send(dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range + | (1 << 6))); + + /*Program m, n pll parameters */ + + /*PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ + test_mode_send(dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, (best_n & 0x0f)); + + /* m - low nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[4:0] */ + test_mode_send(dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, + (best_m & 0x1f)); + + /*m -high nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[9:5] */ + test_mode_send(dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, + ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH); + + /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en*/ + test_mode_send(dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, + (PLL_N_OVR_EN | PLL_M_OVR_EN)); + + /*Program Charge-Pump parameters */ + + /*pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ + t_freq = target_freq_mhz * vco_p.divider; + test_mode_send(dphy_no, TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, + ((t_freq > 1150) ? 0x0C : 0x0B)); + + /*pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ + test_mode_send(dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, + 0x00); + + /*pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ + test_mode_send(dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10); + + /*pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ + test_mode_send(dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10); + + /*PLL Lock Configuration */ + + /*pll_th1 -Lock Detector Phase error threshold, + * document gives fixed value + */ + test_mode_send(dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02); + + /*pll_th2 - Lock Filter length, document gives fixed value */ + test_mode_send(dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60); + + /*pll_th3- PLL Unlocking filter, document gives fixed value */ + test_mode_send(dphy_no, TEST_CODE_PLL_UNLOCK_FILTER, 0x03); + + /*pll_lock_sel-PLL Lock Detector Selection, document gives + * fixed value + */ + test_mode_send(dphy_no, TEST_CODE_PLL_LOCK_DETECTOR, 0x02); +} + static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, - enum dphy_mode mode) + enum dphy_mode mode) { u32 test_code = 0; u32 test_data = 0, val; @@ -904,7 +1076,15 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, /*Set PLL regulator in bypass */ test_mode_send(dphy_no, TEST_CODE_PLL_ANALOG_PROG, 0x01); - /*TODO - PLL Parameters Setup */ + /* PLL Parameters Setup */ + mipi_tx_pll_setup(dphy_no, cfg->ref_clk_khz/1000, + cfg->lane_rate_mbps/2); + + /*Set clksel */ + kmb_write_bits_mipi(DPHY_INIT_CTRL1, 18, 2, 0x01); + + /*Set pll_shadow_control */ + kmb_write_bits_mipi(DPHY_INIT_CTRL1, 16, 1, 0x01); } /*Send NORMAL OPERATION test code */ diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 5921f709..dedee04 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -524,6 +524,7 @@ /* D-PHY regs */ #define DPHY_ENABLE (0x100) #define DPHY_INIT_CTRL0 (0x104) +#define DPHY_INIT_CTRL1 (0x108) #define SHUTDOWNZ 0 #define RESETZ 12 #define DPHY_INIT_CTRL2 (0x10c) @@ -533,6 +534,7 @@ #define CLR_DPHY_INIT_CTRL0(dphy, offset) \ kmb_clr_bit_mipi(DPHY_INIT_CTRL0, \ (dphy+offset)) +#define DPHY_INIT_CTRL2 (0x10c) #define DPHY_FREQ_CTRL0_3 (0x11c) #define SET_DPHY_FREQ_CTRL0_3(dphy, val) \ kmb_write_bits_mipi(DPHY_FREQ_CTRL0_3 \ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:31 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:31 -0700 Subject: [Intel-gfx] [PATCH 19/59] drm/kmb: Added ioremap/iounmap for register access In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-20-git-send-email-anitha.chrisanthus@intel.com> Register physical addresses are remapped and the register mmio addresses for lcd,mipi and msscam are saved in drm_private. All register reads/writes are updated to get the mmio offset from this structure. We are using hardcoded values for register physical addresses and this will be modified to read from device tree in the future. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 56 +++--- drivers/gpu/drm/kmb/kmb_drv.c | 103 ++++++++--- drivers/gpu/drm/kmb/kmb_drv.h | 64 ++++--- drivers/gpu/drm/kmb/kmb_dsi.c | 401 +++++++++++++++++++++------------------- drivers/gpu/drm/kmb/kmb_plane.c | 35 ++-- drivers/gpu/drm/kmb/kmb_regs.h | 106 ++++++----- 6 files changed, 437 insertions(+), 328 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 8e127ae..b2b50cc 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -52,21 +52,26 @@ static void kmb_crtc_cleanup(struct drm_crtc *crtc) static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) { + struct drm_device *dev = crtc->dev; + /*clear interrupt */ - kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP); + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /*set which interval to generate vertical interrupt */ - kmb_write_lcd(LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC); + kmb_write_lcd(dev->dev_private, LCD_VSTATUS_COMPARE, + LCD_VSTATUS_COMPARE_VSYNC); /* enable vertical interrupt */ - kmb_write_lcd(LCD_INT_ENABLE, LCD_INT_VERT_COMP); + kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, LCD_INT_VERT_COMP); return 0; } static void kmb_crtc_disable_vblank(struct drm_crtc *crtc) { + struct drm_device *dev = crtc->dev; + /*clear interrupt */ - kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP); + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /* disable vertical interrupt */ - kmb_write_lcd(LCD_INT_ENABLE, 0); + kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, 0); /* TBD * set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register @@ -89,6 +94,7 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = { static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) { struct drm_display_mode *m = &crtc->state->adjusted_mode; + struct drm_device *dev = crtc->dev; struct videomode vm; int vsync_start_offset; int vsync_end_offset; @@ -104,30 +110,38 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; - kmb_write_lcd(LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1); - kmb_write_lcd(LCD_V_BACKPORCH, vm.vback_porch - 1); - kmb_write_lcd(LCD_V_FRONTPORCH, vm.vfront_porch - 1); - kmb_write_lcd(LCD_VSYNC_WIDTH, vm.vsync_len - 1); - kmb_write_lcd(LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1); - kmb_write_lcd(LCD_H_BACKPORCH, vm.hback_porch - 1); - kmb_write_lcd(LCD_H_FRONTPORCH, vm.hfront_porch - 1); - kmb_write_lcd(LCD_HSYNC_WIDTH, vm.hsync_len - 1); + kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT, + m->crtc_vdisplay - 1); + kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch - 1); + kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch - 1); + kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1); + kmb_write_lcd(dev->dev_private, LCD_H_ACTIVEWIDTH, + m->crtc_hdisplay - 1); + kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch - 1); + kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch - 1); + kmb_write_lcd(dev->dev_private, LCD_HSYNC_WIDTH, vm.hsync_len - 1); if (m->flags == DRM_MODE_FLAG_INTERLACE) { - kmb_write_lcd(LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); - kmb_write_lcd(LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1); - kmb_write_lcd(LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); - kmb_write_lcd(LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); - kmb_write_lcd(LCD_VSYNC_START_EVEN, vsync_start_offset); - kmb_write_lcd(LCD_VSYNC_END_EVEN, vsync_end_offset); + kmb_write_lcd(dev->dev_private, + LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); + kmb_write_lcd(dev->dev_private, + LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1); + kmb_write_lcd(dev->dev_private, + LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); + kmb_write_lcd(dev->dev_private, + LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); + kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, + vsync_start_offset); + kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, + vsync_end_offset); } /* enable VL1 layer as default */ ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE; ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE | LCD_CTRL_OUTPUT_ENABLED; - kmb_write_lcd(LCD_CONTROL, ctrl); + kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl); - kmb_write_lcd(LCD_TIMING_GEN_TRIG, ENABLE); + kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE); /* TBD */ /* set clocks here */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 8945199..a94d387 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -50,34 +50,68 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { - struct kmb_drm_private *lcd = drm->dev_private; + struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); - struct resource *res; - /*u32 version; */ + /*struct resource *res;*/ + /*u32 version;*/ int ret; /* TBD - not sure if clock_get needs to be called here */ /* - * lcd->clk = devm_clk_get(drm->dev, "pxlclk"); - * if (IS_ERR(lcd->clk)) - * return PTR_ERR(lcd->clk); + *dev_p->clk = devm_clk_get(drm->dev, "pxlclk"); + *if (IS_ERR(dev_p->clk)) + * return PTR_ERR(dev_p->clk); */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - lcd->mmio = devm_ioremap_resource(drm->dev, res); - if (IS_ERR(lcd->mmio)) { - DRM_ERROR("failed to map control registers area\n"); - ret = PTR_ERR(lcd->mmio); - lcd->mmio = NULL; - return ret; + /* + * TBD call this in the future when device tree is ready, + * use hardcoded value for now + */ + /*res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + *dev_p->lcd_mmio = devm_ioremap_resource(drm->dev, res); + * + *if (IS_ERR(dev_p->lcd_mmio)) { + * DRM_ERROR("failed to map control registers area\n"); + * ret = PTR_ERR(dev_p->lcd_mmio); + * dev_p->lcd_mmio = NULL; + * return ret; + *} + */ + /* LCD mmio */ + if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) { + DRM_ERROR("failed to reserve LCD registers\n"); + return -ENOMEM; + } + dev_p->lcd_mmio = ioremap_cache(LCD_BASE_ADDR, LCD_MMIO_SIZE); + if (!dev_p->lcd_mmio) { + DRM_ERROR("failed to map LCD registers\n"); + return -ENOMEM; + } + + /* Mipi mmio */ + if (!request_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE, "kmb-mipi")) { + DRM_ERROR("failed to reserve MIPI registers\n"); + iounmap(dev_p->lcd_mmio); + return -ENOMEM; + } + dev_p->mipi_mmio = ioremap_cache(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); + if (!dev_p->mipi_mmio) { + DRM_ERROR("failed to map MIPI registers\n"); + iounmap(dev_p->lcd_mmio); + return -ENOMEM; } - /*TBD read and check for correct product version here */ + + /*this is only for MIPI_TX_MSS_LCD_MIPI_CFG register */ + dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR, + MSS_CAM_MMIO_SIZE); + +/*TBD read and check for correct product version here */ /* Get the optional framebuffer memory resource */ ret = of_reserved_mem_device_init(drm->dev); if (ret && ret != -ENODEV) return ret; - spin_lock_init(&lcd->irq_lock); + spin_lock_init(&dev_p->irq_lock); ret = kmb_setup_crtc(drm); if (ret < 0) { DRM_ERROR("failed to create crtc\n"); @@ -94,7 +128,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) return 0; irq_fail: - drm_crtc_cleanup(&lcd->crtc); + drm_crtc_cleanup(&dev_p->crtc); setup_fail: of_reserved_mem_device_release(drm->dev); @@ -122,18 +156,19 @@ static irqreturn_t kmb_irq(int irq, void *arg) struct drm_device *dev = (struct drm_device *)arg; unsigned long status, val; - status = kmb_read_lcd(LCD_INT_STATUS); + status = kmb_read_lcd(dev->dev_private, LCD_INT_STATUS); if (status & LCD_INT_EOF) { /*To DO - handle EOF interrupt? */ - kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_EOF); + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_EOF); } if (status & LCD_INT_LINE_CMP) { /* clear line compare interrupt */ - kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_LINE_CMP); + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, + LCD_INT_LINE_CMP); } if (status & LCD_INT_VERT_COMP) { /* read VSTATUS */ - val = kmb_read_lcd(LCD_VSTATUS); + val = kmb_read_lcd(dev->dev_private, LCD_VSTATUS); val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); switch (val) { case LCD_VSTATUS_COMPARE_VSYNC: @@ -141,7 +176,8 @@ static irqreturn_t kmb_irq(int irq, void *arg) case LCD_VSTATUS_COMPARE_ACTIVE: case LCD_VSTATUS_COMPARE_FRONT_PORCH: /* clear vertical compare interrupt */ - kmb_write_lcd(LCD_INT_CLEAR, LCD_INT_VERT_COMP); + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, + LCD_INT_VERT_COMP); drm_handle_vblank(dev, 0); break; } @@ -152,8 +188,8 @@ static irqreturn_t kmb_irq(int irq, void *arg) static void kmb_irq_reset(struct drm_device *drm) { - kmb_write_lcd(LCD_INT_CLEAR, 0xFFFF); - kmb_write_lcd(LCD_INT_ENABLE, 0); + kmb_write_lcd(drm->dev_private, LCD_INT_CLEAR, 0xFFFF); + kmb_write_lcd(drm->dev_private, LCD_INT_ENABLE, 0); } DEFINE_DRM_GEM_CMA_FOPS(fops); @@ -260,19 +296,34 @@ static int kmb_drm_bind(struct device *dev) static void kmb_drm_unbind(struct device *dev) { struct drm_device *drm = dev_get_drvdata(dev); - struct kmb_drm_private *lcd = drm->dev_private; + struct kmb_drm_private *dev_p = drm->dev_private; drm_dev_unregister(drm); drm_kms_helper_poll_fini(drm); component_unbind_all(dev, drm); - of_node_put(lcd->crtc.port); - lcd->crtc.port = NULL; + of_node_put(dev_p->crtc.port); + dev_p->crtc.port = NULL; pm_runtime_get_sync(drm->dev); drm_irq_uninstall(drm); pm_runtime_put_sync(drm->dev); pm_runtime_disable(drm->dev); + + if (dev_p->lcd_mmio) { + iounmap(dev_p->lcd_mmio); + release_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE); + } + + if (dev_p->mipi_mmio) { + iounmap(dev_p->mipi_mmio); + release_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); + } + + if (dev_p->msscam_mmio) + iounmap(dev_p->msscam_mmio); + of_reserved_mem_device_release(drm->dev); drm_mode_config_cleanup(drm); + drm_dev_put(drm); drm->dev_private = NULL; dev_set_drvdata(dev, NULL); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 0a38d63..ad5f214 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -33,7 +33,9 @@ struct kmb_drm_private { struct drm_device drm; - void __iomem *mmio; + void __iomem *lcd_mmio; + void __iomem *mipi_mmio; + void __iomem *msscam_mmio; unsigned char n_layers; struct clk *clk; struct drm_fbdev_cma *fbdev; @@ -85,65 +87,77 @@ static inline void kmb_write_bits(struct kmb_drm_private *lcd, } #endif -static inline void kmb_write_lcd(unsigned int reg, u32 value) +static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, + unsigned int reg, u32 value) { - writel(value, (LCD_BASE_ADDR + reg)); + writel(value, (dev_p->lcd_mmio + reg)); } -static inline void kmb_write_mipi(unsigned int reg, u32 value) +static inline void kmb_write_mipi(struct kmb_drm_private *dev_p, + unsigned int reg, u32 value) { - writel(value, (MIPI_BASE_ADDR + reg)); + writel(value, (dev_p->mipi_mmio + reg)); } -static inline u32 kmb_read_lcd(unsigned int reg) +static inline void kmb_write_msscam(struct kmb_drm_private *dev_p, + unsigned int reg, u32 value) { - return readl(LCD_BASE_ADDR + reg); + writel(value, (dev_p->msscam_mmio + reg)); } -static inline u32 kmb_read_mipi(unsigned int reg) +static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) { - return readl(MIPI_BASE_ADDR + reg); + return readl(dev_p->lcd_mmio + reg); } -static inline void kmb_write_bits_mipi(unsigned int reg, u32 offset, - u32 num_bits, u32 value) +static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) { - u32 reg_val = kmb_read_mipi(reg); + return readl(dev_p->mipi_mmio + reg); +} + +static inline void kmb_write_bits_mipi(struct kmb_drm_private *dev_p, + unsigned int reg, u32 offset, u32 num_bits, u32 value) +{ + u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); u32 mask = (1 << num_bits) - 1; value &= mask; mask <<= offset; reg_val &= (~mask); reg_val |= (value << offset); - kmb_write_mipi(reg, reg_val); + kmb_write_mipi(dev_p->mipi_mmio, reg, reg_val); } -static inline void kmb_set_bit_mipi(unsigned int reg, u32 offset) +static inline void kmb_set_bit_mipi(struct kmb_drm_private *dev_p, + unsigned int reg, u32 offset) { - u32 reg_val = kmb_read_mipi(reg); + u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); - kmb_write_mipi(reg, reg_val | (1 << offset)); + kmb_write_mipi(dev_p->mipi_mmio, reg, reg_val | (1 << offset)); } -static inline void kmb_clr_bit_mipi(unsigned int reg, u32 offset) +static inline void kmb_clr_bit_mipi(struct kmb_drm_private *dev_p, + unsigned int reg, u32 offset) { - u32 reg_val = kmb_read_mipi(reg); + u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); - kmb_write_mipi(reg, reg_val & (~(1 << offset))); + kmb_write_mipi(dev_p->mipi_mmio, reg, reg_val & (~(1 << offset))); } -static inline void kmb_set_bitmask_mipi(unsigned int reg, u32 mask) +static inline void kmb_set_bitmask_mipi(struct kmb_drm_private *dev_p, + unsigned int reg, u32 mask) { - u32 reg_val = kmb_read_mipi(reg); + u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); - kmb_write_mipi(reg, (reg_val | mask)); + kmb_write_mipi(dev_p->mipi_mmio, reg, (reg_val | mask)); } -static inline void kmb_clr_bitmask_mipi(unsigned int reg, u32 mask) +static inline void kmb_clr_bitmask_mipi(struct kmb_drm_private *dev_p, + unsigned int reg, u32 mask) { - u32 reg_val = kmb_read_mipi(reg); + u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); - kmb_write_mipi(reg, (reg_val & (~mask))); + kmb_write_mipi(dev_p->mipi_mmio, reg, (reg_val & (~mask))); } int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 898b54c..4d2790f 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -428,10 +428,10 @@ static u32 compute_unpacked_bytes(u32 wc, u8 bits_per_pclk) return ((wc * 8) / bits_per_pclk) * 4; } -static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, - u8 frame_id, u8 section, - u32 height_lines, u32 unpacked_bytes, - struct mipi_tx_frame_sect_phcfg *ph_cfg) +static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, + u8 frame_id, + u8 section, u32 height_lines, + u32 unpacked_bytes, struct mipi_tx_frame_sect_phcfg *ph_cfg) { u32 cfg = 0; u32 ctrl_no = MIPI_CTRL6; @@ -450,8 +450,8 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ cfg |= MIPI_TX_SECT_DMA_PACKED; - kmb_write_mipi((MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); + kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, + section)), cfg); /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections @@ -461,20 +461,20 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_priv, *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 */ reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) - + (section / 2) * 4; - kmb_write_bits_mipi(reg_adr, (section % 2) * 16, 16, unpacked_bytes); + + (section/2)*4; + kmb_write_bits_mipi(dev_p, reg_adr, (section % 2)*16, 16, + unpacked_bytes); /* line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); - kmb_write_mipi(reg_adr, height_lines); + kmb_write_mipi(dev_p, reg_adr, height_lines); return 0; } -static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_priv, - u8 frame_id, - u8 section, - struct mipi_tx_frame_section_cfg *frame_scfg, - u32 *bits_per_pclk, u32 *wc) +static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, + u8 section, + struct mipi_tx_frame_section_cfg *frame_scfg, + u32 *bits_per_pclk, u32 *wc) { u32 ret = 0; u32 unpacked_bytes; @@ -507,18 +507,17 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_priv, ph_cfg.data_type = frame_scfg->data_type; ph_cfg.vchannel = frame_id; - mipi_tx_fg_section_cfg_regs(dev_priv, frame_id, section, - frame_scfg->height_lines, unpacked_bytes, - &ph_cfg); + mipi_tx_fg_section_cfg_regs(dev_p, frame_id, section, + frame_scfg->height_lines, + unpacked_bytes, &ph_cfg); /*caller needs bits_per_clk for additional caluclations */ *bits_per_pclk = data_type_parameters.bits_per_pclk; return 0; } -static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, - u8 frame_gen, - struct mipi_tx_frame_timing_cfg *fg_cfg) +static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, + u8 frame_gen, struct mipi_tx_frame_timing_cfg *fg_cfg) { u32 sysclk; /*float ppl_llp_ratio; */ @@ -542,7 +541,7 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, /*frame generator number of lines */ reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); - kmb_write_mipi(reg_adr, fg_cfg->v_active); + kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active); /*vsync width */ /* @@ -550,33 +549,36 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ - offset = (frame_gen % 2) * 16; - reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen / 2); - kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->vsync_width); + offset = (frame_gen % 2)*16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2); + kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->vsync_width); - /*v backporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen / 2); - kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_backporch); + /*v backporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2); + kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_backporch); - /*v frontporch - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen / 2); - kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_frontporch); + /*v frontporch - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2); + kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_frontporch); - /*v active - same register config like vsync width */ - reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen / 2); - kmb_write_bits_mipi(reg_adr, offset, 16, fg_cfg->v_active); + /*v active - same register config like vsync width*/ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2); + kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_active); /*hsyc width */ reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); - kmb_write_mipi(reg_adr, (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); + kmb_write_mipi(dev_p, reg_adr, + (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); /*h backporch */ reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); - kmb_write_mipi(reg_adr, (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); + kmb_write_mipi(dev_p, reg_adr, + (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); /*h frontporch */ reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); - kmb_write_mipi(reg_adr, (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); + kmb_write_mipi(dev_p, reg_adr, + (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); /*h active */ reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); @@ -584,24 +586,25 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_priv, val = (fg_cfg->h_active * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); val /= 1000; - kmb_write_mipi(reg_adr, val); + kmb_write_mipi(dev_p, reg_adr, val); /* llp hsync width */ reg_adr = MIPI_TXm_HS_LLP_HSYNC_WIDTHn(ctrl_no, frame_gen); - kmb_write_mipi(reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); + kmb_write_mipi(dev_p, reg_adr, fg_cfg->hsync_width * (fg_cfg->bpp / 8)); /* llp h backporch */ reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen); - kmb_write_mipi(reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); + kmb_write_mipi(dev_p, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); /* llp h frontporch */ reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen); - kmb_write_mipi(reg_adr, fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); + kmb_write_mipi(dev_p, reg_adr, + fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); } -static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen, - u8 active_lanes, u32 bpp, u32 wc, - u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) +static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, + u8 active_lanes, u32 bpp, u32 wc, + u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) { u32 i, fg_num_lines = 0; struct mipi_tx_frame_timing_cfg fg_t_cfg; @@ -627,20 +630,21 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_priv, u8 frame_gen, fg_t_cfg.active_lanes = active_lanes; /*apply frame generator timing setting */ - mipi_tx_fg_cfg_regs(dev_priv, frame_gen, &fg_t_cfg); + mipi_tx_fg_cfg_regs(dev_p, frame_gen, &fg_t_cfg); } -static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) +static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, + u8 active_lanes, u8 vchannel_id) { u32 fifo_size, fifo_rthreshold; u32 ctrl_no = MIPI_CTRL6; - /*clear all mc fifo channel sizes and thresholds */ - kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); - kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); - kmb_write_mipi(MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); - kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0); - kmb_write_mipi(MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0); + /*clear all mc fifo channel sizes and thresholds*/ + kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); + kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); + kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); + kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0); + kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0); fifo_size = (active_lanes > MIPI_D_LANES_PER_DPHY) ? MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC; @@ -649,17 +653,19 @@ static void mipi_tx_multichannel_fifo_cfg(u8 active_lanes, u8 vchannel_id) *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 *REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 */ - SET_MC_FIFO_CHAN_ALLOC(ctrl_no, vchannel_id, fifo_size); + SET_MC_FIFO_CHAN_ALLOC(dev_p, ctrl_no, vchannel_id, fifo_size); /*set threshold to half the fifo size, actual size=size*16 */ fifo_rthreshold = ((fifo_size + 1) * 8) & BIT_MASK_16; - SET_MC_FIFO_RTHRESHOLD(ctrl_no, vchannel_id, fifo_rthreshold); + SET_MC_FIFO_RTHRESHOLD(dev_p, ctrl_no, vchannel_id, fifo_rthreshold); /*enable the MC FIFO channel corresponding to the Virtual Channel */ - kmb_set_bit_mipi(MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); + kmb_set_bit_mipi(dev_p, MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), + vchannel_id); } -static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) +static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, + struct mipi_ctrl_cfg *ctrl_cfg) { u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6; @@ -704,12 +710,12 @@ static void mipi_tx_ctrl_cfg(u8 fg_id, struct mipi_ctrl_cfg *ctrl_cfg) /*67 ns stop time */ ctrl |= HSEXIT_CNT(0x43); - kmb_write_mipi(MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); - kmb_write_mipi(MIPI_TXm_HS_CTRL(ctrl_no), ctrl); + kmb_write_mipi(dev_p, MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); + kmb_write_mipi(dev_p, MIPI_TXm_HS_CTRL(ctrl_no), ctrl); } -static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, - struct mipi_ctrl_cfg *ctrl_cfg) +static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, + struct mipi_ctrl_cfg *ctrl_cfg) { u32 ret; u8 active_vchannels = 0; @@ -739,40 +745,41 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_priv, == NULL) continue; - ret = mipi_tx_fg_section_cfg(dev_priv, frame_id, sect, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], - &bits_per_pclk, - &word_count); + ret = mipi_tx_fg_section_cfg(dev_p, frame_id, sect, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], + &bits_per_pclk, &word_count); if (ret) return ret; } /* set frame specific parameters */ - mipi_tx_fg_cfg(dev_priv, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + mipi_tx_fg_cfg(dev_p, frame_id, ctrl_cfg->active_lanes, + bits_per_pclk, + word_count, ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); active_vchannels++; /*connect lcd to mipi */ - writel(1, MSS_CAM_BASE_ADDR + MIPI_TX_MSS_LCD_MIPI_CFG); + kmb_write_msscam(dev_p, MSS_CAM_BASE_ADDR + + MIPI_TX_MSS_LCD_MIPI_CFG, 1); break; } if (active_vchannels == 0) return -EINVAL; - /*Multi-Channel FIFO Configuration */ - mipi_tx_multichannel_fifo_cfg(ctrl_cfg->active_lanes, frame_id); + /*Multi-Channel FIFO Configuration*/ + mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id); /*Frame Generator Enable */ - mipi_tx_ctrl_cfg(frame_id, ctrl_cfg); + mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg); return ret; } -static void test_mode_send(u32 dphy_no, u32 test_code, u32 test_data) +static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, + u32 test_code, u32 test_data) { /*send the test code first */ /* Steps for code: @@ -782,11 +789,11 @@ static void test_mode_send(u32 dphy_no, u32 test_code, u32 test_data) * - set testclk LOW * - set testen LOW */ - SET_DPHY_TEST_CTRL1_CLK(dphy_no); - SET_TEST_DIN0_3(dphy_no, test_code); - SET_DPHY_TEST_CTRL1_EN(dphy_no); - CLR_DPHY_TEST_CTRL1_CLK(dphy_no); - CLR_DPHY_TEST_CTRL1_EN(dphy_no); + SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + SET_TEST_DIN0_3(dev_p, dphy_no, test_code); + SET_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); + CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); /*send the test data next */ /* Steps for data: @@ -795,38 +802,43 @@ static void test_mode_send(u32 dphy_no, u32 test_code, u32 test_data) * - set testdin with data * - set testclk HIGH */ - CLR_DPHY_TEST_CTRL1_EN(dphy_no); - CLR_DPHY_TEST_CTRL1_CLK(dphy_no); - SET_TEST_DIN0_3(dphy_no, test_data); - SET_DPHY_TEST_CTRL1_CLK(dphy_no); + CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); + CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + SET_TEST_DIN0_3(dev_p, dphy_no, test_data); + SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); } -static inline void set_test_mode_src_osc_freq_target_low_bits(u32 dphy_no, - u32 freq) +static inline void + set_test_mode_src_osc_freq_target_low_bits(struct kmb_drm_private + *dev_p, u32 dphy_no, u32 freq) { /*typical rise/fall time=166, * refer Table 1207 databook,sr_osc_freq_target[7:0 */ - test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); + test_mode_send(dev_p, dphy_no, + TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); } -static inline void set_test_mode_slew_rate_calib_en(u32 dphy_no) +static inline void + set_test_mode_slew_rate_calib_en(struct kmb_drm_private *dev_p, + u32 dphy_no) { /*do not bypass slew rate calibration algorithm */ - /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ - test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, - (0x03 | (1 << 6))); + /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range*/ + test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, + (0x03 | (1 << 6))); } -static inline void set_test_mode_src_osc_freq_target_hi_bits(u32 dphy_no, - u32 freq) +static inline void + set_test_mode_src_osc_freq_target_hi_bits(struct kmb_drm_private *dev_p, + u32 dphy_no, u32 freq) { u32 data; /*typical rise/fall time=166, refer Table 1207 databook, * sr_osc_freq_target[11:7 */ - data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ - test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); + data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ + test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); } struct vco_params { @@ -861,7 +873,8 @@ static void mipi_tx_get_vco_params(struct vco_params *vco) WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq); } -static void mipi_tx_pll_setup(u32 dphy_no, u32 ref_clk_mhz, u32 target_freq_mhz) +static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, + u32 ref_clk_mhz, u32 target_freq_mhz) { /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) @@ -923,64 +936,66 @@ static void mipi_tx_pll_setup(u32 dphy_no, u32 ref_clk_mhz, u32 target_freq_mhz) *PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr, * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en */ - test_mode_send(dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range | (1 << 6))); /*Program m, n pll parameters */ /*PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ - test_mode_send(dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, (best_n & 0x0f)); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, + (best_n & 0x0f)); /* m - low nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[4:0] */ - test_mode_send(dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, (best_m & 0x1f)); /*m -high nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[9:5] */ - test_mode_send(dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH); /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en*/ - test_mode_send(dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, (PLL_N_OVR_EN | PLL_M_OVR_EN)); /*Program Charge-Pump parameters */ /*pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ t_freq = target_freq_mhz * vco_p.divider; - test_mode_send(dphy_no, TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, + test_mode_send(dev_p, dphy_no, + TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, ((t_freq > 1150) ? 0x0C : 0x0B)); /*pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ - test_mode_send(dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, 0x00); /*pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ - test_mode_send(dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10); /*pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ - test_mode_send(dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10); /*PLL Lock Configuration */ /*pll_th1 -Lock Detector Phase error threshold, * document gives fixed value */ - test_mode_send(dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02); /*pll_th2 - Lock Filter length, document gives fixed value */ - test_mode_send(dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60); /*pll_th3- PLL Unlocking filter, document gives fixed value */ - test_mode_send(dphy_no, TEST_CODE_PLL_UNLOCK_FILTER, 0x03); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_UNLOCK_FILTER, 0x03); /*pll_lock_sel-PLL Lock Detector Selection, document gives * fixed value */ - test_mode_send(dphy_no, TEST_CODE_PLL_LOCK_DETECTOR, 0x02); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_DETECTOR, 0x02); } -static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, - enum dphy_mode mode) +static void dphy_init_sequence(struct kmb_drm_private *dev_p, + struct mipi_ctrl_cfg *cfg, u32 dphy_no, enum dphy_mode mode) { u32 test_code = 0; u32 test_data = 0, val; @@ -988,17 +1003,16 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, /*Set D-PHY in shutdown mode */ /*assert RSTZ signal */ - CLR_DPHY_INIT_CTRL0(dphy_no, RESETZ); - /* assert SHUTDOWNZ signal */ - CLR_DPHY_INIT_CTRL0(dphy_no, SHUTDOWNZ); - + CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); + /* assert SHUTDOWNZ signal*/ + CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); /*Init D-PHY_n */ /*Pulse testclear signal to make sure the d-phy configuration starts * from a clean base */ - SET_DPHY_TEST_CTRL0(dphy_no); - /*TODO may need to add 15ns delay here */ - CLR_DPHY_TEST_CTRL0(dphy_no); + SET_DPHY_TEST_CTRL0(dev_p, dphy_no); + /*TODO may need to add 15ns delay here*/ + CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); /*Set mastermacro bit - Master or slave mode */ test_code = TEST_CODE_MULTIPLE_PHY_CTRL; @@ -1009,18 +1023,18 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, test_data = 0x00; /*send the test code and data */ - test_mode_send(dphy_no, test_code, test_data); + test_mode_send(dev_p, dphy_no, test_code, test_data); /*Set the lane data rate */ for (i = 0; i < MIPI_DPHY_DEFAULT_BIT_RATES; i++) { if (mipi_hs_freq_range[i].default_bit_rate_mbps < cfg->lane_rate_mbps) continue; - /* send the test code and data */ - /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ - test_mode_send(dphy_no, TEST_CODE_HS_FREQ_RANGE_CFG, - (mipi_hs_freq_range[i].hsfreqrange_code - & 0x7f) | (1 << 7)); + /* send the test code and data*/ + /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en*/ + test_mode_send(dev_p, dphy_no, TEST_CODE_HS_FREQ_RANGE_CFG, + (mipi_hs_freq_range[i].hsfreqrange_code + & 0x7f) | (1 << 7)); break; } /* @@ -1029,30 +1043,32 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, */ if (cfg->lane_rate_mbps > 1500) { /*bypass slew rate calibration algorithm */ - /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr */ - test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, - 0x02); + /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr*/ + test_mode_send(dev_p, dphy_no, + TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, 0x02); - /* disable slew rate calibration */ - test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, - 0x00); + /* disable slew rate calibration*/ + test_mode_send(dev_p, dphy_no, + TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x00); } else if (cfg->lane_rate_mbps > 1000) { /*BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON * typical rise/fall times: 166 ps */ /*do not bypass slew rate calibration algorithm */ - set_test_mode_slew_rate_calib_en(dphy_no); + set_test_mode_slew_rate_calib_en(dev_p, dphy_no); - /* enable slew rate calibration */ - test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, - 0x01); + /* enable slew rate calibration*/ + test_mode_send(dev_p, dphy_no, + TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x01); /*set sr_osc_freq_target[6:0] */ - /*typical rise/fall time=166, refer Table 1207 databook */ - set_test_mode_src_osc_freq_target_low_bits(dphy_no, 0x72f); + /*typical rise/fall time=166, refer Table 1207 databook*/ + set_test_mode_src_osc_freq_target_low_bits(dev_p, + dphy_no, 0x72f); /*set sr_osc_freq_target[11:7] */ - set_test_mode_src_osc_freq_target_hi_bits(dphy_no, 0x72f); + set_test_mode_src_osc_freq_target_hi_bits(dev_p, dphy_no, + 0x72f); } else { /*lane_rate_mbps <= 1000 Mbps */ /*BitRate: <= 1 Gbps: @@ -1060,42 +1076,45 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, * - typical rise/fall times: 225 ps */ /*do not bypass slew rate calibration algorithm */ - set_test_mode_slew_rate_calib_en(dphy_no); - /* enable slew rate calibration */ - test_mode_send(dphy_no, TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, - 0x01); - - /*typical rise/fall time=255, refer Table 1207 databook */ - set_test_mode_src_osc_freq_target_low_bits(dphy_no, 0x523); + set_test_mode_slew_rate_calib_en(dev_p, dphy_no); + /* enable slew rate calibration*/ + test_mode_send(dev_p, dphy_no, + TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x01); + + /*typical rise/fall time=255, refer Table 1207 databook*/ + set_test_mode_src_osc_freq_target_low_bits(dev_p, + dphy_no, 0x523); /*set sr_osc_freq_target[11:7] */ - set_test_mode_src_osc_freq_target_hi_bits(dphy_no, 0x523); + set_test_mode_src_osc_freq_target_hi_bits(dev_p, dphy_no, + 0x523); } /*Set cfgclkfreqrange */ - val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; - SET_DPHY_FREQ_CTRL0_3(dphy_no, val); + val = (((cfg->cfg_clk_khz/1000) - 17) * 4) & 0x3f; + SET_DPHY_FREQ_CTRL0_3(dev_p, dphy_no, val); /*Enable config clk for the corresponding d-phy */ - kmb_set_bit_mipi(DPHY_CFG_CLK_EN, dphy_no); + kmb_set_bit_mipi(dev_p, DPHY_CFG_CLK_EN, dphy_no); /* PLL setup */ if (mode == MIPI_DPHY_MASTER) { /*Set PLL regulator in bypass */ - test_mode_send(dphy_no, TEST_CODE_PLL_ANALOG_PROG, 0x01); + test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_ANALOG_PROG, 0x01); /* PLL Parameters Setup */ - mipi_tx_pll_setup(dphy_no, cfg->ref_clk_khz/1000, + mipi_tx_pll_setup(dev_p, dphy_no, cfg->ref_clk_khz/1000, cfg->lane_rate_mbps/2); /*Set clksel */ - kmb_write_bits_mipi(DPHY_INIT_CTRL1, PLL_CLKSEL_0, 2, 0x01); + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, PLL_CLKSEL_0, 2, + 0x01); /*Set pll_shadow_control */ - kmb_set_bit_mipi(DPHY_INIT_CTRL1, PLL_SHADOW_CTRL); + kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL1, PLL_SHADOW_CTRL); } /*Send NORMAL OPERATION test code */ - test_mode_send(dphy_no, 0x00, 0x00); + test_mode_send(dev_p, dphy_no, 0x00, 0x00); /* Configure BASEDIR for data lanes * NOTE: basedir only applies to LANE_0 of each D-PHY. @@ -1104,61 +1123,64 @@ static void dphy_init_sequence(struct mipi_ctrl_cfg *cfg, u32 dphy_no, * bits[5:0] - BaseDir: 1 = Rx * bits[9:6] - BaseDir: 0 = Tx */ - kmb_clr_bit_mipi(DPHY_INIT_CTRL2, dphy_no); + kmb_clr_bit_mipi(dev_p, DPHY_INIT_CTRL2, dphy_no); /* Enable CLOCK LANE - */ /*clock lane should be enabled regardless of the direction set for * the D-PHY (Rx/Tx) */ - kmb_clr_bit_mipi(DPHY_INIT_CTRL2, 12 + dphy_no); + kmb_clr_bit_mipi(dev_p, DPHY_INIT_CTRL2, 12 + dphy_no); /* enable DATA LANES */ - kmb_write_bits_mipi(DPHY_ENABLE, dphy_no * 2, 2, + kmb_write_bits_mipi(dev_p, DPHY_ENABLE, dphy_no * 2, 2, ((1 << cfg->active_lanes) - 1)); /*Take D-PHY out of shutdown mode */ /* deassert SHUTDOWNZ signal*/ - SET_DPHY_INIT_CTRL0(dphy_no, SHUTDOWNZ); + SET_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); /*deassert RSTZ signal */ - SET_DPHY_INIT_CTRL0(dphy_no, RESETZ); + SET_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); } -static void dphy_wait_fsm(u32 dphy_no, enum dphy_tx_fsm fsm_state) +static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no, + enum dphy_tx_fsm fsm_state) { enum dphy_tx_fsm val = DPHY_TX_POWERDWN; do { - test_mode_send(dphy_no, TEST_CODE_FSM_CONTROL, 0x80); + test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); /*TODO-need to add a time out and return failure */ - val = GET_TEST_DOUT0_3(dphy_no); + val = GET_TEST_DOUT0_3(dev_p, dphy_no); } while (val != fsm_state); } -static u32 wait_init_done(u32 dphy_no, u32 active_lanes) +static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, + u32 active_lanes) { u32 stopstatedata = 0; u32 data_lanes = (1 << active_lanes) - 1; do { - stopstatedata = GET_STOPSTATE_DATA(dphy_no); + stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no); /*TODO-need to add a time out and return failure */ } while (stopstatedata != data_lanes); return 0; } -static u32 wait_pll_lock(u32 dphy_no) +static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) { do { ; /*TODO-need to add a time out and return failure */ - } while (!GET_PLL_LOCK(dphy_no)); + } while (!GET_PLL_LOCK(dev_p, dphy_no)); return 0; } -static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg) +static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, + struct mipi_ctrl_cfg *cfg) { u32 dphy_no = MIPI_DPHY6; @@ -1180,28 +1202,28 @@ static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg) *f. poll for PHY1 stopstate */ /*PHY #N+1 ('slave') */ - dphy_init_sequence(cfg, dphy_no + 1, MIPI_DPHY_SLAVE); + dphy_init_sequence(dev_p, cfg, dphy_no + 1, MIPI_DPHY_SLAVE); - dphy_wait_fsm(dphy_no + 1, DPHY_TX_LOCK); + dphy_wait_fsm(dev_p, dphy_no + 1, DPHY_TX_LOCK); /*PHY #N master*/ - dphy_init_sequence(cfg, dphy_no, MIPI_DPHY_MASTER); + dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_MASTER); /* wait for DPHY init to complete */ - wait_init_done(dphy_no, MIPI_DPHY_D_LANES); - wait_init_done(dphy_no + 1, + wait_init_done(dev_p, dphy_no, MIPI_DPHY_D_LANES); + wait_init_done(dev_p, dphy_no + 1, cfg->active_lanes - MIPI_DPHY_D_LANES); - wait_pll_lock(dphy_no); - wait_pll_lock(dphy_no + 1); + wait_pll_lock(dev_p, dphy_no); + wait_pll_lock(dev_p, dphy_no + 1); } else { /* Single DPHY */ - dphy_init_sequence(cfg, dphy_no, MIPI_DPHY_MASTER); - wait_init_done(dphy_no, cfg->active_lanes); - wait_pll_lock(dphy_no); + dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_MASTER); + wait_init_done(dev_p, dphy_no, cfg->active_lanes); + wait_pll_lock(dev_p, dphy_no); } return 0; } -static void mipi_tx_init_irqs(union mipi_irq_cfg *cfg, - struct kmb_drm_private *dev_priv, +static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, + union mipi_irq_cfg *cfg, struct mipi_tx_ctrl_cfg *tx_ctrl_cfg) { unsigned long irqflags; @@ -1209,32 +1231,33 @@ static void mipi_tx_init_irqs(union mipi_irq_cfg *cfg, /* clear all interrupts first */ /*local interrupts */ - SET_MIPI_TX_HS_IRQ_CLEAR(MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); + SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); /*global interrupts */ - SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_HS_IRQ); - SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ); - SET_MIPI_CTRL_IRQ_CLEAR1(MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR1(dev_p, MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); /*enable interrupts */ - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + spin_lock_irqsave(&dev_p->irq_lock, irqflags); for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) { if (tx_ctrl_cfg->frames[vc] == NULL) continue; /*enable FRAME_DONE interrupt if VC is configured */ - SET_HS_IRQ_ENABLE(MIPI_CTRL6, + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc); break; /*only one vc for LCD interface */ } /*enable user enabled interrupts */ if (cfg->irq_cfg.dphy_error) - SET_MIPI_CTRL_IRQ_ENABLE0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_ENABLE0(dev_p, MIPI_CTRL6, MIPI_DHY_ERR_IRQ); if (cfg->irq_cfg.line_compare) - SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_LINE_COMPARE); + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, + MIPI_TX_HS_IRQ_LINE_COMPARE); if (cfg->irq_cfg.ctrl_error) - SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR); + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR); - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); + spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); } void kmb_dsi_init(struct drm_device *dev) @@ -1244,7 +1267,7 @@ void kmb_dsi_init(struct drm_device *dev) struct kmb_connector *kmb_connector; struct drm_connector *connector; struct kmb_dsi_host *host; - struct kmb_drm_private *dev_priv = dev->dev_private; + struct kmb_drm_private *dev_p = dev->dev_private; kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); if (!kmb_dsi) @@ -1278,11 +1301,11 @@ void kmb_dsi_init(struct drm_device *dev) drm_connector_attach_encoder(connector, encoder); /* initialize mipi controller */ - mipi_tx_init_cntrl(dev_priv, &mipi_tx_init_cfg); + mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); /*d-phy initialization */ - mipi_tx_init_dphy(&mipi_tx_init_cfg); + mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); /* irq initialization */ - mipi_tx_init_irqs(&int_cfg, dev_priv, &mipi_tx_init_cfg.tx_ctrl_cfg); + mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); } diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 66d6c9f..3841d96 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -221,7 +221,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *state) { struct drm_framebuffer *fb = plane->state->fb; - struct kmb_drm_private *lcd; + struct kmb_drm_private *dev_p; dma_addr_t addr; unsigned int width; unsigned int height; @@ -235,23 +235,23 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, if (!fb) return; - lcd = plane->dev->dev_private; + dev_p = plane->dev->dev_private; src_w = plane->state->src_w >> 16; src_h = plane->state->src_h >> 16; crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - kmb_write_lcd(LCD_LAYERn_WIDTH(plane_id), src_w-1); - kmb_write_lcd(LCD_LAYERn_HEIGHT(plane_id), src_h-1); - kmb_write_lcd(LCD_LAYERn_COL_START(plane_id), crtc_x); - kmb_write_lcd(LCD_LAYERn_ROW_START(plane_id), crtc_y); + kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1); + kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); + kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y); val = set_pixel_format(fb->format->format); val |= set_bits_per_pixel(fb->format); /*CHECKME Leon drvr sets it to 50 try this for now */ val |= LCD_LAYER_FIFO_50; - kmb_write_lcd(LCD_LAYERn_CFG(plane_id), val); + kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); switch (plane_id) { case LAYER_0: @@ -271,7 +271,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, ctrl |= LCD_CTRL_ENABLE; ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE | LCD_CTRL_OUTPUT_ENABLED; - kmb_write_lcd(LCD_CONTROL, ctrl); + kmb_write_lcd(dev_p, LCD_CONTROL, ctrl); /*TBD check visible? */ @@ -280,24 +280,25 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1; /* disable DMA first */ - kmb_write_lcd(LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + ~LCD_DMA_LAYER_ENABLE); addr = drm_fb_cma_get_gem_addr(fb, plane->state, plane_id); - kmb_write_lcd(LCD_LAYERn_DMA_START_ADDR(plane_id), addr); - kmb_write_lcd(LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); width = fb->width; height = fb->height; dma_len = width * height * fb->format->cpp[plane_id]; - kmb_write_lcd(LCD_LAYERn_DMA_LEN(plane_id), dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); - kmb_write_lcd(LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[plane_id]); - kmb_write_lcd(LCD_LAYERn_DMA_LINE_WIDTH(plane_id), + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[plane_id]); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), (width*fb->format->cpp[plane_id])); /* enable DMA */ - kmb_write_lcd(LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); /* FIXME no doc on how to set output format - may need to change * this later @@ -310,7 +311,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, out_format |= LCD_OUTF_MIPI_RGB_MODE; /* pixel format from LCD_LAYER_CFG */ out_format |= ((val >> 9) & 0x1F); - kmb_write_lcd(LCD_OUT_FORMAT_CFG, out_format); + kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); } static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index e47e123..cfe2cc1 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -29,10 +29,13 @@ #define ENABLE 1 #define DISABLE 0 /*from Data Book section 12.5.8.1 page 4322 */ -#define MIPI_BASE_ADDR (void *)(0x20900000) +#define MIPI_BASE_ADDR (0x20900000) /*from Data Book section 12.11.6.1 page 4972 */ -#define LCD_BASE_ADDR (void *)(0x20930000) +#define LCD_BASE_ADDR (0x20930000) #define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x10000) +#define LCD_MMIO_SIZE (0x10000) +#define MIPI_MMIO_SIZE (0x10000) +#define MSS_CAM_MMIO_SIZE (0x10000) /*************************************************************************** * LCD controller control register defines @@ -507,18 +510,19 @@ #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 (0x198) #define MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1 (0x19c) #define MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(M, N) \ - (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \ - + (0x4*N)) -#define SET_MC_FIFO_CHAN_ALLOC(ctrl, vc, sz) \ - kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \ - vc/2), (vc % 2)*16, 16, sz) + (MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0 + HS_OFFSET(M) \ + + (0x4*N)) +#define SET_MC_FIFO_CHAN_ALLOC(dev, ctrl, vc, sz) \ + kmb_write_bits_mipi(dev, \ + MIPI_TXm_HS_MC_FIFO_CHAN_ALLOCn(ctrl, \ + vc/2), (vc % 2)*16, 16, sz) #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 (0x1a0) #define MIPI_TX_HS_MC_FIFO_RTHRESHOLD1 (0x1a4) #define MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(M, N) \ (MIPI_TX_HS_MC_FIFO_RTHRESHOLD0 + HS_OFFSET(M) \ + (0x4*N)) -#define SET_MC_FIFO_RTHRESHOLD(ctrl, vc, th) \ - kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ +#define SET_MC_FIFO_RTHRESHOLD(dev, ctrl, vc, th) \ + kmb_write_bits_mipi(dev, MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th) /* MIPI IRQ */ @@ -529,15 +533,15 @@ #define MIPI_CTRL_IRQ_STATUS1 (0x04) #define MIPI_HS_RX_EVENT_IRQ 0 #define MIPI_CTRL_IRQ_ENABLE0 (0x08) -#define SET_MIPI_CTRL_IRQ_ENABLE0(M, N) \ - kmb_set_bit_mipi(MIPI_CTRL_IRQ_ENABLE0, M+N) +#define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) \ + kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_ENABLE0, M+N) #define MIPI_CTRL_IRQ_ENABLE1 (0x0c) #define MIPI_CTRL_IRQ_CLEAR0 (0x010) -#define SET_MIPI_CTRL_IRQ_CLEAR0(M, N) \ - kmb_set_bit_mipi(MIPI_CTRL_IRQ_CLEAR0, M+N) +#define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) \ + kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR0, M+N) #define MIPI_CTRL_IRQ_CLEAR1 (0x014) -#define SET_MIPI_CTRL_IRQ_CLEAR1(M, N) \ - kmb_set_bit_mipi(MIPI_CTRL_IRQ_CLEAR1, M+N) +#define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \ + kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, M+N) #define MIPI_TX_HS_IRQ_STATUS (0x01c) #define MIPI_TX_HS_IRQ_STATUSm(M) \ (MIPI_TX_HS_IRQ_STATUS + HS_OFFSET(M)) @@ -594,12 +598,14 @@ MIPI_TX_HS_IRQ_ERROR) #define MIPI_TX_HS_IRQ_ENABLE (0x020) -#define SET_HS_IRQ_ENABLE(M, val) \ - kmb_set_bitmask_mipi(MIPI_TX_HS_IRQ_ENABLE \ +#define SET_HS_IRQ_ENABLE(dev, M, val) \ + kmb_set_bitmask_mipi(dev, \ + MIPI_TX_HS_IRQ_ENABLE \ + HS_OFFSET(M), val) #define MIPI_TX_HS_IRQ_CLEAR (0x024) -#define SET_MIPI_TX_HS_IRQ_CLEAR(M, val) \ - kmb_set_bitmask_mipi(MIPI_TX_HS_IRQ_CLEAR \ +#define SET_MIPI_TX_HS_IRQ_CLEAR(dev, M, val) \ + kmb_set_bitmask_mipi(dev, \ + MIPI_TX_HS_IRQ_CLEAR \ + HS_OFFSET(M), val) /* D-PHY regs */ @@ -611,47 +617,47 @@ #define PLL_CLKSEL_0 18 #define PLL_SHADOW_CTRL 16 #define DPHY_INIT_CTRL2 (0x10c) -#define SET_DPHY_INIT_CTRL0(dphy, offset) \ - kmb_set_bit_mipi(DPHY_INIT_CTRL0, \ - (dphy+offset)) -#define CLR_DPHY_INIT_CTRL0(dphy, offset) \ - kmb_clr_bit_mipi(DPHY_INIT_CTRL0, \ - (dphy+offset)) +#define SET_DPHY_INIT_CTRL0(dev, dphy, offset) \ + kmb_set_bit_mipi(dev, DPHY_INIT_CTRL0, (dphy+offset)) +#define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ + kmb_clr_bit_mipi(dev, DPHY_INIT_CTRL0, (dphy+offset)) #define DPHY_INIT_CTRL2 (0x10c) #define DPHY_FREQ_CTRL0_3 (0x11c) -#define SET_DPHY_FREQ_CTRL0_3(dphy, val) \ - kmb_write_bits_mipi(DPHY_FREQ_CTRL0_3 \ - + ((dphy/4)*4), (dphy % 4) * 8, \ - 6, val) +#define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ + kmb_write_bits_mipi(dev, DPHY_FREQ_CTRL0_3 \ + + ((dphy/4)*4), (dphy % 4) * 8, 6, val) #define MIPI_DPHY_STAT0_3 (0x134) -#define GET_STOPSTATE_DATA(dphy) \ - (((kmb_read_mipi(MIPI_DPHY_STAT0_3 + \ - (dphy/4)*4)) \ +#define GET_STOPSTATE_DATA(dev, dphy) \ + (((kmb_read_mipi(dev, MIPI_DPHY_STAT0_3 + (dphy/4)*4)) \ >> (((dphy % 4)*8)+4)) & 0x03) #define DPHY_TEST_CTRL0 (0x154) -#define SET_DPHY_TEST_CTRL0(dphy) kmb_set_bit_mipi(DPHY_TEST_CTRL0, \ - (dphy)) -#define CLR_DPHY_TEST_CTRL0(dphy) kmb_clr_bit_mipi(DPHY_TEST_CTRL0, \ - (dphy)) +#define SET_DPHY_TEST_CTRL0(dev, dphy) \ + kmb_set_bit_mipi(dev, DPHY_TEST_CTRL0, (dphy)) +#define CLR_DPHY_TEST_CTRL0(dev, dphy) \ + kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL0, \ + (dphy)) #define DPHY_TEST_CTRL1 (0x158) -#define SET_DPHY_TEST_CTRL1_CLK(dphy) kmb_set_bit_mipi(DPHY_TEST_CTRL1, \ - (dphy)) -#define CLR_DPHY_TEST_CTRL1_CLK(dphy) kmb_clr_bit_mipi(DPHY_TEST_CTRL1, \ - (dphy)) -#define SET_DPHY_TEST_CTRL1_EN(dphy) kmb_set_bit_mipi(DPHY_TEST_CTRL1, \ - (dphy+12)) -#define CLR_DPHY_TEST_CTRL1_EN(dphy) kmb_clr_bit_mipi(DPHY_TEST_CTRL1, \ - (dphy+12)) +#define SET_DPHY_TEST_CTRL1_CLK(dev, dphy) \ + kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy)) +#define CLR_DPHY_TEST_CTRL1_CLK(dev, dphy) \ + kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy)) +#define SET_DPHY_TEST_CTRL1_EN(dev, dphy) \ + kmb_set_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy+12)) +#define CLR_DPHY_TEST_CTRL1_EN(dev, dphy) \ + kmb_clr_bit_mipi(dev, DPHY_TEST_CTRL1, (dphy+12)) #define DPHY_TEST_DIN0_3 (0x15c) -#define SET_TEST_DIN0_3(dphy, val) kmb_write_mipi(DPHY_TEST_DIN0_3 + \ - 4, ((val) << (((dphy)%4)*8))) +#define SET_TEST_DIN0_3(dev, dphy, val) \ + kmb_write_mipi(dev, DPHY_TEST_DIN0_3 + \ + 4, ((val) << (((dphy)%4)*8))) #define DPHY_TEST_DOUT0_3 (0x168) -#define GET_TEST_DOUT0_3(dphy) (kmb_read_mipi(DPHY_TEST_DOUT0_3 + 4) \ - >> (((dphy)%4)*8) & 0xff) +#define GET_TEST_DOUT0_3(dev, dphy) \ + (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3 + 4) \ + >> (((dphy)%4)*8) & 0xff) #define DPHY_PLL_LOCK (0x188) -#define GET_PLL_LOCK(dphy) (kmb_read_mipi(DPHY_PLL_LOCK) \ - & (1 << (dphy - MIPI_DPHY6))) +#define GET_PLL_LOCK(dev, dphy) \ + (kmb_read_mipi(dev, DPHY_PLL_LOCK) \ + & (1 << (dphy - MIPI_DPHY6))) #define DPHY_CFG_CLK_EN (0x18c) #define MIPI_TX_MSS_LCD_MIPI_CFG (0x04) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:32 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:32 -0700 Subject: [Intel-gfx] [PATCH 20/59] drm/kmb: Register IRQ for LCD In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-21-git-send-email-anitha.chrisanthus@intel.com> This code is commented out until firmware is updated to redirect LCD IRQ from MSSCPU to A53. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index a94d387..d35f1b2 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -48,12 +48,16 @@ #include "kmb_plane.h" #include "kmb_dsi.h" +/*IRQ handler*/ +static irqreturn_t kmb_isr(int irq, void *arg); + static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); /*struct resource *res;*/ /*u32 version;*/ + /*int irq_lcd, irq_mipi; */ int ret; /* TBD - not sure if clock_get needs to be called here */ @@ -104,6 +108,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR, MSS_CAM_MMIO_SIZE); + /*TODO - register irqs here - section 17.3 in databook + * lists LCD at 79 under MSS CPU - firmware has to redirect it to A53 + * May be 33 for LCD and 34 for MIPI? Will wait till firmware + * finalizes the IRQ numbers for redirection + */ + /*TBD read and check for correct product version here */ /* Get the optional framebuffer memory resource */ @@ -151,7 +161,7 @@ static void kmb_setup_mode_config(struct drm_device *drm) drm->mode_config.funcs = &kmb_mode_config_funcs; } -static irqreturn_t kmb_irq(int irq, void *arg) +static irqreturn_t kmb_isr(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; unsigned long status, val; @@ -196,8 +206,9 @@ DEFINE_DRM_GEM_CMA_FOPS(fops); static struct drm_driver kmb_driver = { .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | - DRIVER_MODESET | DRIVER_ATOMIC, - .irq_handler = kmb_irq, + DRIVER_MODESET | + DRIVER_ATOMIC, + .irq_handler = kmb_isr, .irq_preinstall = kmb_irq_reset, .irq_uninstall = kmb_irq_reset, .gem_free_object_unlocked = drm_gem_cma_free_object, -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:33 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:33 -0700 Subject: [Intel-gfx] [PATCH 21/59] drm/kmb: IRQ handlers for LCD and mipi dsi In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-22-git-send-email-anitha.chrisanthus@intel.com> Added handlers for lcd and mipi, it only finds and clears the interrupt as of now, more functionality can be added as needed. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 51 ++++++++++++++++++++++++++++++++++++------ drivers/gpu/drm/kmb/kmb_drv.h | 2 ++ drivers/gpu/drm/kmb/kmb_dsi.c | 37 ++++++++++++++++++++++++++++-- drivers/gpu/drm/kmb/kmb_dsi.h | 1 + drivers/gpu/drm/kmb/kmb_regs.h | 35 +++++++++++++++++++++-------- 5 files changed, 108 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index d35f1b2..e5f4da1 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -57,7 +57,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) struct platform_device *pdev = to_platform_device(drm->dev); /*struct resource *res;*/ /*u32 version;*/ - /*int irq_lcd, irq_mipi; */ + int irq_lcd, irq_mipi; int ret; /* TBD - not sure if clock_get needs to be called here */ @@ -108,11 +108,29 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR, MSS_CAM_MMIO_SIZE); - /*TODO - register irqs here - section 17.3 in databook - * lists LCD at 79 under MSS CPU - firmware has to redirect it to A53 - * May be 33 for LCD and 34 for MIPI? Will wait till firmware - * finalizes the IRQ numbers for redirection + /* register irqs here - section 17.3 in databook + * lists LCD at 79 and 82 for MIPI under MSS CPU - + * firmware has to redirect it to A53 */ + irq_lcd = platform_get_irq_byname(pdev, "irq_lcd"); + if (irq_lcd < 0) { + DRM_ERROR("irq_lcd not found"); + return irq_lcd; + } + pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd); + ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p); + dev_p->irq_lcd = irq_lcd; + + irq_mipi = platform_get_irq_byname(pdev, "irq_mipi"); + if (irq_mipi < 0) { + DRM_ERROR("irq_mipi not found"); + return irq_mipi; + } + pr_info("irq_mipi platform_get_irq = %d\n", irq_mipi); + ret = request_irq(irq_mipi, kmb_isr, IRQF_SHARED, "irq_mipi", dev_p); + dev_p->irq_mipi = irq_mipi; + + /*TBD read and check for correct product version here */ @@ -161,9 +179,9 @@ static void kmb_setup_mode_config(struct drm_device *drm) drm->mode_config.funcs = &kmb_mode_config_funcs; } -static irqreturn_t kmb_isr(int irq, void *arg) + +static irqreturn_t handle_lcd_irq(struct drm_device *dev) { - struct drm_device *dev = (struct drm_device *)arg; unsigned long status, val; status = kmb_read_lcd(dev->dev_private, LCD_INT_STATUS); @@ -192,10 +210,29 @@ static irqreturn_t kmb_isr(int irq, void *arg) break; } } + return IRQ_HANDLED; +} +static irqreturn_t handle_mipi_irq(struct drm_device *dev) +{ + mipi_tx_handle_irqs(dev->dev_private); return IRQ_HANDLED; } +static irqreturn_t kmb_isr(int irq, void *arg) +{ + struct drm_device *dev = (struct drm_device *)arg; + struct kmb_drm_private *dev_p = dev->dev_private; + irqreturn_t ret = IRQ_NONE; + + if (irq == dev_p->irq_lcd) + ret = handle_lcd_irq(dev); + else if (irq == dev_p->irq_mipi) + ret = handle_mipi_irq(dev); + + return ret; +} + static void kmb_irq_reset(struct drm_device *drm) { kmb_write_lcd(drm->dev_private, LCD_INT_CLEAR, 0xFFFF); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index ad5f214..dcaeb11 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -43,6 +43,8 @@ struct kmb_drm_private { struct kmb_plane *plane; struct drm_atomic_state *state; spinlock_t irq_lock; + int irq_lcd; + int irq_mipi; }; static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 4d2790f..684ddbc 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -1234,7 +1234,7 @@ static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); /*global interrupts */ SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ); - SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); SET_MIPI_CTRL_IRQ_CLEAR1(dev_p, MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); /*enable interrupts */ @@ -1250,7 +1250,7 @@ static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, /*enable user enabled interrupts */ if (cfg->irq_cfg.dphy_error) - SET_MIPI_CTRL_IRQ_ENABLE0(dev_p, MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_ENABLE0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); if (cfg->irq_cfg.line_compare) SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_LINE_COMPARE); @@ -1260,6 +1260,39 @@ static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); } + +void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) +{ + uint32_t irq_ctrl_stat_0, hs_stat, hs_enable; + uint32_t irq_ctrl_enabled_0; + + irq_ctrl_stat_0 = MIPI_GET_IRQ_STAT0(dev_p); + irq_ctrl_enabled_0 = MIPI_GET_IRQ_ENABLED0(dev_p); + /*only service enabled interrupts */ + irq_ctrl_stat_0 &= irq_ctrl_enabled_0; + + if (irq_ctrl_stat_0 & MIPI_DPHY_ERR_MASK) { + if (irq_ctrl_stat_0 & ((1 << (MIPI_DPHY6 + 1)))) + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, + MIPI_DPHY_ERR_IRQ); + } else if (irq_ctrl_stat_0 & MIPI_HS_IRQ_MASK) { + hs_stat = GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6); + hs_enable = GET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6); + hs_stat &= hs_enable; + /*look for errors */ + if (hs_stat & MIPI_TX_HS_IRQ_ERROR) { + CLR_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, + (hs_stat & MIPI_TX_HS_IRQ_ERROR) | + MIPI_TX_HS_IRQ_DMA_DONE | + MIPI_TX_HS_IRQ_DMA_IDLE); + } + /* clear local, then global */ + SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, hs_stat); + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ); + } + +} + void kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 7645d03..8f4e0b9 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -330,6 +330,7 @@ union mipi_irq_cfg { void kmb_dsi_init(struct drm_device *dev); void kmb_plane_destroy(struct drm_plane *plane); +void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); #define to_kmb_connector(x) container_of(x, struct kmb_connector, base) #define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index cfe2cc1..5f7aff7 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -527,15 +527,25 @@ /* MIPI IRQ */ #define MIPI_CTRL_IRQ_STATUS0 (0x00) -#define MIPI_DHY_ERR_IRQ 1 +#define MIPI_DPHY_ERR_IRQ 1 +#define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */ #define MIPI_HS_IRQ 13 +#define MIPI_HS_IRQ_MASK 0x7FE000 /*bits 13-22 */ #define MIPI_LP_EVENT_IRQ 25 +#define MIPI_GET_IRQ_STAT0(dev) kmb_read_mipi(dev, \ + MIPI_CTRL_IRQ_STATUS0) #define MIPI_CTRL_IRQ_STATUS1 (0x04) #define MIPI_HS_RX_EVENT_IRQ 0 +#define MIPI_GET_IRQ_STAT1(dev) kmb_read_mipi(dev, \ + MIPI_CTRL_IRQ_STATUS1) #define MIPI_CTRL_IRQ_ENABLE0 (0x08) -#define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) \ - kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_ENABLE0, M+N) +#define SET_MIPI_CTRL_IRQ_ENABLE0(dev, M, N) kmb_set_bit_mipi(dev, \ + MIPI_CTRL_IRQ_ENABLE0, M+N) +#define MIPI_GET_IRQ_ENABLED0(dev) kmb_read_mipi(dev, \ + MIPI_CTRL_IRQ_ENABLE0) #define MIPI_CTRL_IRQ_ENABLE1 (0x0c) +#define MIPI_GET_IRQ_ENABLED1(dev) kmb_read_mipi(dev, \ + MIPI_CTRL_IRQ_ENABLE1) #define MIPI_CTRL_IRQ_CLEAR0 (0x010) #define SET_MIPI_CTRL_IRQ_CLEAR0(dev, M, N) \ kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR0, M+N) @@ -543,8 +553,10 @@ #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \ kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, M+N) #define MIPI_TX_HS_IRQ_STATUS (0x01c) -#define MIPI_TX_HS_IRQ_STATUSm(M) \ - (MIPI_TX_HS_IRQ_STATUS + HS_OFFSET(M)) +#define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \ + HS_OFFSET(M)) +#define GET_MIPI_TX_HS_IRQ_STATUS(dev, M) kmb_read_mipi(dev, \ + MIPI_TX_HS_IRQ_STATUSm(M)) #define MIPI_TX_HS_IRQ_LINE_COMPARE (1<<1) #define MIPI_TX_HS_IRQ_FRAME_DONE_0 (1<<2) #define MIPI_TX_HS_IRQ_FRAME_DONE_1 (1<<3) @@ -598,10 +610,15 @@ MIPI_TX_HS_IRQ_ERROR) #define MIPI_TX_HS_IRQ_ENABLE (0x020) -#define SET_HS_IRQ_ENABLE(dev, M, val) \ - kmb_set_bitmask_mipi(dev, \ - MIPI_TX_HS_IRQ_ENABLE \ - + HS_OFFSET(M), val) +#define SET_HS_IRQ_ENABLE(dev, M, val) kmb_set_bitmask_mipi(dev, \ + MIPI_TX_HS_IRQ_ENABLE \ + + HS_OFFSET(M), val) +#define CLR_HS_IRQ_ENABLE(dev, M, val) kmb_clr_bitmask_mipi(dev, \ + MIPI_TX_HS_IRQ_ENABLE \ + + HS_OFFSET(M), val) +#define GET_HS_IRQ_ENABLE(dev, M) kmb_read_mipi(dev, \ + MIPI_TX_HS_IRQ_ENABLE \ + + HS_OFFSET(M)) #define MIPI_TX_HS_IRQ_CLEAR (0x024) #define SET_MIPI_TX_HS_IRQ_CLEAR(dev, M, val) \ kmb_set_bitmask_mipi(dev, \ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:34 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:34 -0700 Subject: [Intel-gfx] [PATCH 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-23-git-send-email-anitha.chrisanthus@intel.com> Myriadx code has it set to these values. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index b2b50cc..053da17 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -120,6 +120,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch - 1); kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch - 1); kmb_write_lcd(dev->dev_private, LCD_HSYNC_WIDTH, vm.hsync_len - 1); + /*this is hardcoded as 0 in the Myriadx code */ + kmb_write_lcd(dev->dev_private, LCD_VSYNC_START, 0); + kmb_write_lcd(dev->dev_private, LCD_VSYNC_END, 0); if (m->flags == DRM_MODE_FLAG_INTERLACE) { kmb_write_lcd(dev->dev_private, @@ -128,12 +131,11 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1); kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); - kmb_write_lcd(dev->dev_private, - LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); - kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, - vsync_start_offset); - kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, - vsync_end_offset); + kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT_EVEN, + m->crtc_vdisplay - 1); + /*this is hardcoded as 10 in the Myriadx code*/ + kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, 10); + kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10); } /* enable VL1 layer as default */ ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:35 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:35 -0700 Subject: [Intel-gfx] [PATCH 23/59] drm/kmb: Additional register programming to update_plane In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-24-git-send-email-anitha.chrisanthus@intel.com> These changes are ported from Myriadx which has additional registers updated for planes. This change does the following reinitialize plane interrupts program Cb/Cr for planar formats set LCD_CTRL_VHSYNC_IDLE_LVL set output format and configure csc v2: code review changes Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.h | 16 ++++ drivers/gpu/drm/kmb/kmb_plane.c | 183 ++++++++++++++++++++++++++++++++-------- drivers/gpu/drm/kmb/kmb_regs.h | 72 ++++++++++------ 3 files changed, 210 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index dcaeb11..50efa8a 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -112,6 +112,22 @@ static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) return readl(dev_p->lcd_mmio + reg); } +static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, + unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_lcd(dev_p->lcd_mmio, reg); + + kmb_write_lcd(dev_p->lcd_mmio, reg, (reg_val | mask)); +} + +static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p, + unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_lcd(dev_p->lcd_mmio, reg); + + kmb_write_lcd(dev_p->lcd_mmio, reg, (reg_val & (~mask))); +} + static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) { return readl(dev_p->mipi_mmio + reg); diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 3841d96..026df49 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -76,6 +76,46 @@ static const u32 kmb_formats_v[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV21, }; +#define LCD_INT_VL0_ERR (LAYER0_DMA_FIFO_UNDEFLOW | \ + LAYER0_DMA_FIFO_OVERFLOW | \ + LAYER0_DMA_CB_FIFO_OVERFLOW | \ + LAYER0_DMA_CB_FIFO_UNDERFLOW | \ + LAYER0_DMA_CR_FIFO_OVERFLOW | \ + LAYER0_DMA_CR_FIFO_UNDERFLOW) + +#define LCD_INT_VL1_ERR (LAYER1_DMA_FIFO_UNDERFLOW | \ + LAYER1_DMA_FIFO_OVERFLOW | \ + LAYER1_DMA_CB_FIFO_OVERFLOW | \ + LAYER1_DMA_CB_FIFO_UNDERFLOW | \ + LAYER1_DMA_CR_FIFO_OVERFLOW | \ + LAYER1_DMA_CR_FIFO_UNDERFLOW) + +#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW) + +#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW) + +#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR) + +#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR) + +#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR) + +#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) + +const uint32_t layer_irqs[] = { + LCD_INT_VL0, + LCD_INT_VL1, + LCD_INT_GL0, + LCD_INT_GL1 + }; +/*Conversion (yuv->rgb) matrix from myriadx */ +static const u32 csc_coef_lcd[] = { + 1024, 0, 1436, + 1024, -352, -731, + 1024, 1814, 0, + -179, 125, -226 +}; + static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -217,6 +257,24 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) return val; } +static void config_csc(struct kmb_drm_private *dev_p, int plane_id) +{ + /*YUV to RGB conversion using the fixed matrix csc_coef_lcd */ + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]); + kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]); + kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_CFG(plane_id), LCD_LAYER_CSC_EN); +} + static void kmb_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *state) { @@ -231,6 +289,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned int ctrl = 0, val = 0, out_format = 0; unsigned int src_w, src_h, crtc_x, crtc_y; unsigned char plane_id = kmb_plane->id; + int num_planes = fb->format->num_planes; if (!fb) return; @@ -249,68 +308,122 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val = set_pixel_format(fb->format->format); val |= set_bits_per_pixel(fb->format); - /*CHECKME Leon drvr sets it to 50 try this for now */ - val |= LCD_LAYER_FIFO_50; + /*CHECKME Leon drvr sets it to 100 try this for now */ + val |= LCD_LAYER_FIFO_100; kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); - switch (plane_id) { - case LAYER_0: - ctrl = LCD_CTRL_VL1_ENABLE; - break; - case LAYER_1: - ctrl = LCD_CTRL_VL2_ENABLE; - break; - case LAYER_2: - ctrl = LCD_CTRL_GL1_ENABLE; - break; - case LAYER_3: - ctrl = LCD_CTRL_GL2_ENABLE; - break; - } - - ctrl |= LCD_CTRL_ENABLE; - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_OUTPUT_ENABLED; - kmb_write_lcd(dev_p, LCD_CONTROL, ctrl); + /*re-initialize interrupts */ + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]); + kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, layer_irqs[plane_id]); + kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]); /*TBD check visible? */ - /* we may have to set LCD_DMA_VSTRIDE_ENABLE in the future */ dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE - | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1; + | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1 + | LCD_DMA_LAYER_VSTRIDE_EN; /* disable DMA first */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE); - addr = drm_fb_cma_get_gem_addr(fb, plane->state, plane_id); + /* pinpong mode is enabled - at the end of DMA transfer, start new + * transfer alternatively using main and shadow register settings. + * So update both main and shadow registers + */ + addr = drm_fb_cma_get_gem_addr(fb, plane->state, 0); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); width = fb->width; height = fb->height; - dma_len = width * height * fb->format->cpp[plane_id]; + dma_len = width * height * fb->format->cpp[0]; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[plane_id]); + fb->pitches[0]); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width*fb->format->cpp[plane_id])); + (width*fb->format->cpp[0])); + + /*program Cb/Cr for planar formats*/ + if (num_planes > 1) { + if (fb->format->format == DRM_FORMAT_YUV420 || + fb->format->format == DRM_FORMAT_YVU420) + width /= 2; + addr = drm_fb_cma_get_gem_addr(fb, plane->state, LAYER_1); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), + addr); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_SHADOW(plane_id), + addr); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), + fb->pitches[LAYER_1]); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), + (width*fb->format->cpp[0])); + if (num_planes == 3) { + addr = drm_fb_cma_get_gem_addr(fb, plane->state, + LAYER_2); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CR_ADR(plane_id), + addr); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CR_SHADOW(plane_id), + addr); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), + fb->pitches[LAYER_2]); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), + (width*fb->format->cpp[0])); + } + } /* enable DMA */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); - /* FIXME no doc on how to set output format - may need to change - * this later + switch (plane_id) { + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; + } + + ctrl |= LCD_CTRL_ENABLE; + ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; + + /*LCD is connected to MIPI on kmb + * Therefore this bit is required for DSI Tx + */ + ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; + + kmb_write_lcd(dev_p, LCD_CONTROL, ctrl); + + /* FIXME no doc on how to set output format,these values are taken + * from the Myriadx tests */ - if (val & LCD_LAYER_BGR_ORDER) - out_format |= LCD_OUTF_BGR_ORDER; - else if (val & LCD_LAYER_CRCB_ORDER) - out_format |= LCD_OUTF_CRCB_ORDER; + out_format |= LCD_OUTF_FORMAT_RGB888; + + if (val & LCD_LAYER_PLANAR_STORAGE) { + /*enable CSC if input is planar and output is RGB */ + config_csc(dev_p, plane_id); + } + + /*set background color to white*/ + kmb_write_lcd(dev_p, LCD_BG_COLOUR_LS, 0xffffff); + /*leave RGB order,conversion mode and clip mode to default*/ /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; - /* pixel format from LCD_LAYER_CFG */ - out_format |= ((val >> 9) & 0x1F); kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 5f7aff7..bb80bc5 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -65,7 +65,8 @@ #define LCD_CTRL_ALPHA_BOTTOM_GL1 (2<<12) #define LCD_CTRL_ALPHA_BOTTOM_GL2 (3<<12) #define LCD_CTRL_TIM_GEN_ENABLE (1<<14) -#define LCD_CTRL_DISPLAY_MODE_ONE_SHOT (1<<15) +#define LCD_CTRL_CONTINUOUS (0<<15) +#define LCD_CTRL_ONE_SHOT (1<<15) #define LCD_CTRL_PWM0_EN (1<<16) #define LCD_CTRL_PWM1_EN (1<<17) #define LCD_CTRL_PWM2_EN (1<<18) @@ -74,36 +75,37 @@ #define LCD_CTRL_BPORCH_ENABLE (1<<21) #define LCD_CTRL_FPORCH_ENABLE (1<<22) #define LCD_CTRL_PIPELINE_DMA (1<<28) +#define LCD_CTRL_VHSYNC_IDLE_LVL (1<<31) /*interrupts */ #define LCD_INT_STATUS (0x4 * 0x001) #define LCD_INT_EOF (1<<0) #define LCD_INT_LINE_CMP (1<<1) #define LCD_INT_VERT_COMP (1<<2) -#define LAYER0_DMA_DONE_BIT (1<<3) -#define LAYER0_DMA_IDLE_BIT (1<<4) -#define LAYER0_DMA_OVERFLOW_BIT (1<<5) -#define LAYER0_DMA_FIFO_UNDEFLOW_BIT (1<<6) -#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7) -#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8) -#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9) -#define LAYER0_DMA_CR_FIFO_UNDERFLOW_BIT (1<<10) -#define LAYER1_DMA_DONE_BIT (1<<11) -#define LAYER1_DMA_IDLE_BIT (1<<12) -#define LAYER1_DMA_OVERFLOW_BIT (1<<13) -#define LAYER1_DMA_FIFO_UNDERFLOW_BIT (1<<14) -#define LAYER1_DMA_CB_FIFO_OVERFLOW_BIT (1<<15) -#define LAYER1_DMA_CB_FIFO_UNDERFLOW_BIT (1<<16) -#define LAYER1_DMA_CR_FIFO_OVERFLOW_BIT (1<<17) -#define LAYER1_DMA_CR_FIFO_UNDERFLOW_BIT (1<<18) -#define LAYER2_DMA_DONE_BIT (1<<19) -#define LAYER2_DMA_IDLE_BIT (1<<20) -#define LAYER2_DMA_OVERFLOW_BIT (1<<21) -#define LAYER2_DMA_FIFO_UNDERFLOW_BIT (1<<22) -#define LAYER3_DMA_DONE_BIT (1<<23) -#define LAYER3_DMA_IDLE_BIT (1<<24) -#define LAYER3_DMA_OVERFLOW_BIT (1<<25) -#define LAYER3_DMA_FIFO_UNDERFLOW_BIT (1<<26) +#define LAYER0_DMA_DONE (1<<3) +#define LAYER0_DMA_IDLE (1<<4) +#define LAYER0_DMA_FIFO_OVERFLOW (1<<5) +#define LAYER0_DMA_FIFO_UNDEFLOW (1<<6) +#define LAYER0_DMA_CB_FIFO_OVERFLOW (1<<7) +#define LAYER0_DMA_CB_FIFO_UNDERFLOW (1<<8) +#define LAYER0_DMA_CR_FIFO_OVERFLOW (1<<9) +#define LAYER0_DMA_CR_FIFO_UNDERFLOW (1<<10) +#define LAYER1_DMA_DONE (1<<11) +#define LAYER1_DMA_IDLE (1<<12) +#define LAYER1_DMA_FIFO_OVERFLOW (1<<13) +#define LAYER1_DMA_FIFO_UNDERFLOW (1<<14) +#define LAYER1_DMA_CB_FIFO_OVERFLOW (1<<15) +#define LAYER1_DMA_CB_FIFO_UNDERFLOW (1<<16) +#define LAYER1_DMA_CR_FIFO_OVERFLOW (1<<17) +#define LAYER1_DMA_CR_FIFO_UNDERFLOW (1<<18) +#define LAYER2_DMA_DONE (1<<19) +#define LAYER2_DMA_IDLE (1<<20) +#define LAYER2_DMA_FIFO_OVERFLOW (1<<21) +#define LAYER2_DMA_FIFO_UNDERFLOW (1<<22) +#define LAYER3_DMA_DONE (1<<23) +#define LAYER3_DMA_IDLE (1<<24) +#define LAYER3_DMA_FIFO_OVERFLOW (1<<25) +#define LAYER3_DMA_FIFO_UNDERFLOW (1<<26) #define LCD_INT_ENABLE (0x4 * 0x002) #define LCD_INT_CLEAR (0x4 * 0x003) @@ -271,7 +273,7 @@ #define LCD_DMA_LAYER_AXI_BURST_14 (0xe<<5) #define LCD_DMA_LAYER_AXI_BURST_15 (0xf<<5) #define LCD_DMA_LAYER_AXI_BURST_16 (0x10<<5) -#define LCD_DMA_LAYER_V_STRIDE_EN (1<<10) +#define LCD_DMA_LAYER_VSTRIDE_EN (1<<10) #define LCD_LAYER0_DMA_START_ADR (0x4 * 0x118) #define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR \ @@ -300,13 +302,30 @@ #define LCD_LAYER0_CFG2 (0x4 * 0x120) #define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) #define LCD_LAYER0_DMA_START_CB_ADR (0x4 * 0x700) +#define LCD_LAYERn_DMA_START_CB_ADR(N) (LCD_LAYER0_DMA_START_CB_ADR + \ + (0x20*N)) #define LCD_LAYER0_DMA_START_CB_SHADOW (0x4 * 0x701) +#define LCD_LAYERn_DMA_START_CB_SHADOW(N) (LCD_LAYER0_DMA_START_CB_SHADOW\ + + (0x20*N)) #define LCD_LAYER0_DMA_CB_LINE_WIDTH (0x4 * 0x702) +#define LCD_LAYERn_DMA_CB_LINE_WIDTH(N) (LCD_LAYER0_DMA_CB_LINE_WIDTH +\ + (0x20*N)) #define LCD_LAYER0_DMA_CB_LINE_VSTRIDE (0x4 * 0x703) +#define LCD_LAYERn_DMA_CB_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CB_LINE_VSTRIDE\ + + (0x20*N)) #define LCD_LAYER0_DMA_START_CR_ADR (0x4 * 0x704) +#define LCD_LAYERn_DMA_START_CR_ADR(N) (LCD_LAYER0_DMA_START_CR_ADR + \ + (0x20*N)) #define LCD_LAYER0_DMA_START_CR_SHADOW (0x4 * 0x705) +#define LCD_LAYERn_DMA_START_CR_SHADOW(N) \ + (LCD_LAYER0_DMA_START_CR_SHADOW\ + + (0x20*N)) #define LCD_LAYER0_DMA_CR_LINE_WIDTH (0x4 * 0x706) +#define LCD_LAYERn_DMA_CR_LINE_WIDTH(N) (LCD_LAYER0_DMA_CR_LINE_WIDTH +\ + (0x20*N)) #define LCD_LAYER0_DMA_CR_LINE_VSTRIDE (0x4 * 0x707) +#define LCD_LAYERn_DMA_CR_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_CR_LINE_VSTRIDE\ + + (0x20*N)) #define LCD_LAYER1_DMA_START_CB_ADR (0x4 * 0x708) #define LCD_LAYER1_DMA_START_CB_SHADOW (0x4 * 0x709) #define LCD_LAYER1_DMA_CB_LINE_WIDTH (0x4 * 0x70a) @@ -350,6 +369,7 @@ #define LCD_OUTF_BGR_ORDER (1 << 5) #define LCD_OUTF_Y_ORDER (1 << 6) #define LCD_OUTF_CRCB_ORDER (1 << 7) +#define LCD_OUTF_RGB_CONV_MODE (1 << 14) #define LCD_OUTF_MIPI_RGB_MODE (1 << 18) #define LCD_HSYNC_WIDTH (0x4 * 0x801) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:44 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:44 -0700 Subject: [Intel-gfx] [PATCH 32/59] drm/kmb: Revert dsi_host back to a static variable In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-33-git-send-email-anitha.chrisanthus@intel.com> From: Edmund Dea <edmund.j.dea at intel.com> revert dsi_host to static and instead add dsi_host_unregister. Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 6 +++--- drivers/gpu/drm/kmb/kmb_drv.h | 1 - drivers/gpu/drm/kmb/kmb_dsi.c | 9 +++++++-- drivers/gpu/drm/kmb/kmb_dsi.h | 1 + 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index f520ca9..0588bd0 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -398,7 +398,7 @@ static void kmb_drm_unload(struct device *dev) dev_set_drvdata(dev, NULL); /* Unregister DSI host */ - mipi_dsi_host_unregister(dsi_host); + dsi_host_unregister(); } static int kmb_probe(struct platform_device *pdev) @@ -434,7 +434,7 @@ static int kmb_probe(struct platform_device *pdev) drm->dev_private = lcd; kmb_setup_mode_config(drm); - dev_set_drvdata(dev, drm); + dev_set_drvdata(dev, drm); /* Load driver */ ret = kmb_load(drm, 0); @@ -475,7 +475,7 @@ static int kmb_probe(struct platform_device *pdev) drm_mode_config_cleanup(drm); dev_set_drvdata(dev, NULL); drm_dev_put(drm); - mipi_dsi_host_unregister(dsi_host); + dsi_host_unregister(); return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index c87e608..6c1d687 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -31,7 +31,6 @@ #define KMB_MAX_WIDTH 16384 /*max width in pixels */ #define KMB_MAX_HEIGHT 16384 /*max height in pixels */ -extern struct mipi_dsi_host *dsi_host; struct kmb_drm_private { struct drm_device drm; void __iomem *lcd_mmio; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 4b5adc7c..af04eb9 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -79,7 +79,7 @@ #define PLL_M_MAX 623 #define PLL_FVCO_MAX 1250 -struct mipi_dsi_host *dsi_host; +static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device; /* @@ -357,8 +357,13 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) return bridge; } +void dsi_host_unregister(void) +{ + mipi_dsi_host_unregister(dsi_host); +} + u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, - struct mipi_data_type_params *params) + struct mipi_data_type_params *params) { struct mipi_data_type_params data_type_parameters; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index cf234db..e85625b 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -333,6 +333,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev); int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); +void dsi_host_unregister(void); #define to_kmb_connector(x) container_of(x, struct kmb_connector, base) #define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:30 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:30 -0700 Subject: [Intel-gfx] [PATCH 18/59] drm/kmb: Part8 of Mipi Tx Initialization In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-19-git-send-email-anitha.chrisanthus@intel.com> This initializes the interrupts for DSI. This is the final part of mipi DSI initialization. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 1 + drivers/gpu/drm/kmb/kmb_drv.h | 30 +++++++++++----- drivers/gpu/drm/kmb/kmb_dsi.c | 46 ++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 13 +++++++ drivers/gpu/drm/kmb/kmb_regs.h | 81 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 163 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 0b99309..8945199 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -77,6 +77,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) if (ret && ret != -ENODEV) return ret; + spin_lock_init(&lcd->irq_lock); ret = kmb_setup_crtc(drm); if (ret < 0) { DRM_ERROR("failed to create crtc\n"); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 434be1a..0a38d63 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -32,14 +32,15 @@ #define KMB_MAX_HEIGHT 16384 /*max height in pixels */ struct kmb_drm_private { - struct drm_device drm; - void __iomem *mmio; - unsigned char n_layers; - struct clk *clk; - struct drm_fbdev_cma *fbdev; - struct drm_crtc crtc; - struct kmb_plane *plane; - struct drm_atomic_state *state; + struct drm_device drm; + void __iomem *mmio; + unsigned char n_layers; + struct clk *clk; + struct drm_fbdev_cma *fbdev; + struct drm_crtc crtc; + struct kmb_plane *plane; + struct drm_atomic_state *state; + spinlock_t irq_lock; }; static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) @@ -131,6 +132,19 @@ static inline void kmb_clr_bit_mipi(unsigned int reg, u32 offset) kmb_write_mipi(reg, reg_val & (~(1 << offset))); } +static inline void kmb_set_bitmask_mipi(unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, (reg_val | mask)); +} + +static inline void kmb_clr_bitmask_mipi(unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_mipi(reg); + + kmb_write_mipi(reg, (reg_val & (~mask))); +} int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); #endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 51bec35..898b54c 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -32,6 +32,7 @@ #include <drm/drm_mipi_dsi.h> #include <drm/drm_print.h> #include <linux/slab.h> +#include <linux/spinlock.h> #include <linux/gpio/consumer.h> #include "kmb_drv.h" #include "kmb_regs.h" @@ -208,6 +209,11 @@ static mipi_hs_freq_range_cfg {.default_bit_rate_mbps = 2500, .hsfreqrange_code = 0x49} }; +union mipi_irq_cfg int_cfg = { + .irq_cfg.frame_done = 1, + .irq_cfg.ctrl_error = 1, +}; + static enum drm_mode_status kmb_dsi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) @@ -1194,6 +1200,43 @@ static u32 mipi_tx_init_dphy(struct mipi_ctrl_cfg *cfg) return 0; } +static void mipi_tx_init_irqs(union mipi_irq_cfg *cfg, + struct kmb_drm_private *dev_priv, + struct mipi_tx_ctrl_cfg *tx_ctrl_cfg) +{ + unsigned long irqflags; + uint8_t vc; + + /* clear all interrupts first */ + /*local interrupts */ + SET_MIPI_TX_HS_IRQ_CLEAR(MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); + /*global interrupts */ + SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_HS_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR1(MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); + + /*enable interrupts */ + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) { + if (tx_ctrl_cfg->frames[vc] == NULL) + continue; + /*enable FRAME_DONE interrupt if VC is configured */ + SET_HS_IRQ_ENABLE(MIPI_CTRL6, + MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc); + break; /*only one vc for LCD interface */ + } + + /*enable user enabled interrupts */ + if (cfg->irq_cfg.dphy_error) + SET_MIPI_CTRL_IRQ_ENABLE0(MIPI_CTRL6, MIPI_DHY_ERR_IRQ); + if (cfg->irq_cfg.line_compare) + SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_LINE_COMPARE); + if (cfg->irq_cfg.ctrl_error) + SET_HS_IRQ_ENABLE(MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + void kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; @@ -1239,4 +1282,7 @@ void kmb_dsi_init(struct drm_device *dev) /*d-phy initialization */ mipi_tx_init_dphy(&mipi_tx_init_cfg); + + /* irq initialization */ + mipi_tx_init_irqs(&int_cfg, dev_priv, &mipi_tx_init_cfg.tx_ctrl_cfg); } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index eb38ae7..7645d03 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -315,6 +315,19 @@ struct mipi_ctrl_cfg { uint32_t data_if; /*MIPI_IF_DMA or MIPI_IF_PARALLEL */ struct mipi_tx_ctrl_cfg tx_ctrl_cfg; }; + +/*structure for storing user specified interrupts that are enabled */ +union mipi_irq_cfg { + uint8_t value; + struct { + uint8_t line_compare : 1; + uint8_t dma_event : 1; + uint8_t frame_done : 1; + uint8_t ctrl_error : 1; + uint8_t dphy_error : 1; + } irq_cfg; +}; + void kmb_dsi_init(struct drm_device *dev); void kmb_plane_destroy(struct drm_plane *plane); diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index b6f6acf..e47e123 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -521,6 +521,87 @@ kmb_write_bits_mipi(MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th) +/* MIPI IRQ */ +#define MIPI_CTRL_IRQ_STATUS0 (0x00) +#define MIPI_DHY_ERR_IRQ 1 +#define MIPI_HS_IRQ 13 +#define MIPI_LP_EVENT_IRQ 25 +#define MIPI_CTRL_IRQ_STATUS1 (0x04) +#define MIPI_HS_RX_EVENT_IRQ 0 +#define MIPI_CTRL_IRQ_ENABLE0 (0x08) +#define SET_MIPI_CTRL_IRQ_ENABLE0(M, N) \ + kmb_set_bit_mipi(MIPI_CTRL_IRQ_ENABLE0, M+N) +#define MIPI_CTRL_IRQ_ENABLE1 (0x0c) +#define MIPI_CTRL_IRQ_CLEAR0 (0x010) +#define SET_MIPI_CTRL_IRQ_CLEAR0(M, N) \ + kmb_set_bit_mipi(MIPI_CTRL_IRQ_CLEAR0, M+N) +#define MIPI_CTRL_IRQ_CLEAR1 (0x014) +#define SET_MIPI_CTRL_IRQ_CLEAR1(M, N) \ + kmb_set_bit_mipi(MIPI_CTRL_IRQ_CLEAR1, M+N) +#define MIPI_TX_HS_IRQ_STATUS (0x01c) +#define MIPI_TX_HS_IRQ_STATUSm(M) \ + (MIPI_TX_HS_IRQ_STATUS + HS_OFFSET(M)) +#define MIPI_TX_HS_IRQ_LINE_COMPARE (1<<1) +#define MIPI_TX_HS_IRQ_FRAME_DONE_0 (1<<2) +#define MIPI_TX_HS_IRQ_FRAME_DONE_1 (1<<3) +#define MIPI_TX_HS_IRQ_FRAME_DONE_2 (1<<4) +#define MIPI_TX_HS_IRQ_FRAME_DONE_3 (1<<5) +#define MIPI_TX_HS_IRQ_DMA_DONE_0 (1<<6) +#define MIPI_TX_HS_IRQ_DMA_IDLE_0 (1<<7) +#define MIPI_TX_HS_IRQ_DMA_DONE_1 (1<<8) +#define MIPI_TX_HS_IRQ_DMA_IDLE_1 (1<<9) +#define MIPI_TX_HS_IRQ_DMA_DONE_2 (1<<10) +#define MIPI_TX_HS_IRQ_DMA_IDLE_2 (1<<11) +#define MIPI_TX_HS_IRQ_DMA_DONE_3 (1<<12) +#define MIPI_TX_HS_IRQ_DMA_IDLE_3 (1<<13) +#define MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW (1<<14) +#define MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW (1<<15) +#define MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY (1<<16) +#define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL (1<<17) +#define MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR (1<<18) +#define MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR (1<<20) +#define MIPI_TX_HS_IRQ_FRAME_DONE \ + (MIPI_TX_HS_IRQ_FRAME_DONE_0 | \ + MIPI_TX_HS_IRQ_FRAME_DONE_1 | \ + MIPI_TX_HS_IRQ_FRAME_DONE_2 | \ + MIPI_TX_HS_IRQ_FRAME_DONE_3) + +#define MIPI_TX_HS_IRQ_DMA_DONE \ + (MIPI_TX_HS_IRQ_DMA_DONE_0 | \ + MIPI_TX_HS_IRQ_DMA_DONE_1 | \ + MIPI_TX_HS_IRQ_DMA_DONE_2 | \ + MIPI_TX_HS_IRQ_DMA_DONE_3) + +#define MIPI_TX_HS_IRQ_DMA_IDLE \ + (MIPI_TX_HS_IRQ_DMA_IDLE_0 | \ + MIPI_TX_HS_IRQ_DMA_IDLE_1 | \ + MIPI_TX_HS_IRQ_DMA_IDLE_2 | \ + MIPI_TX_HS_IRQ_DMA_IDLE_3) + +#define MIPI_TX_HS_IRQ_ERROR \ + (MIPI_TX_HS_IRQ_MC_FIFO_UNDERFLOW | \ + MIPI_TX_HS_IRQ_MC_FIFO_OVERFLOW | \ + MIPI_TX_HS_IRQ_LLP_FIFO_EMPTY | \ + MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_FULL | \ + MIPI_TX_HS_IRQ_LLP_REQUEST_QUEUE_ERROR | \ + MIPI_TX_HS_IRQ_LLP_WORD_COUNT_ERROR) + +#define MIPI_TX_HS_IRQ_ALL \ + (MIPI_TX_HS_IRQ_FRAME_DONE | \ + MIPI_TX_HS_IRQ_DMA_DONE | \ + MIPI_TX_HS_IRQ_DMA_IDLE | \ + MIPI_TX_HS_IRQ_LINE_COMPARE | \ + MIPI_TX_HS_IRQ_ERROR) + +#define MIPI_TX_HS_IRQ_ENABLE (0x020) +#define SET_HS_IRQ_ENABLE(M, val) \ + kmb_set_bitmask_mipi(MIPI_TX_HS_IRQ_ENABLE \ + + HS_OFFSET(M), val) +#define MIPI_TX_HS_IRQ_CLEAR (0x024) +#define SET_MIPI_TX_HS_IRQ_CLEAR(M, val) \ + kmb_set_bitmask_mipi(MIPI_TX_HS_IRQ_CLEAR \ + + HS_OFFSET(M), val) + /* D-PHY regs */ #define DPHY_ENABLE (0x100) #define DPHY_INIT_CTRL0 (0x104) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:36 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:36 -0700 Subject: [Intel-gfx] [PATCH 24/59] drm/kmb: Add ADV7535 bridge In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-25-git-send-email-anitha.chrisanthus@intel.com> Find ADV 7535 from the device tree and get the bridge driver and attach it to the DRM and the MIPI encoder. v2: check for valid encoder node Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 27 ++++++++++++++++++++++++++- drivers/gpu/drm/kmb/kmb_dsi.c | 26 +++++++++++++++++++++----- drivers/gpu/drm/kmb/kmb_dsi.h | 3 ++- 3 files changed, 49 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index e5f4da1..0aa910b 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -55,10 +55,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); + struct drm_bridge *bridge; /*struct resource *res;*/ /*u32 version;*/ int irq_lcd, irq_mipi; int ret; + struct device_node *encoder_node; /* TBD - not sure if clock_get needs to be called here */ /* @@ -146,7 +148,30 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } - kmb_dsi_init(drm); + /* find ADV7535 node and initialize it */ + encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0); + if (!encoder_node) { + DRM_ERROR("failed to get bridge info from DT\n"); + ret = -EPROBE_DEFER; + goto setup_fail; + } + + /* Locate drm bridge from the hdmi encoder DT node */ + bridge = of_drm_find_bridge(encoder_node); + if (!bridge) { + DRM_ERROR("failed to get bridge driver from DT\n"); + ret = -EPROBE_DEFER; + goto setup_fail; + } + + of_node_put(encoder_node); + + ret = kmb_dsi_init(drm, bridge); + if (ret) { + DRM_ERROR("failed to initialize DSI\n"); + goto setup_fail; + } + ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 684ddbc..01014c8 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -31,6 +31,7 @@ #include <drm/drm_edid.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_print.h> +#include <drm/drm_bridge.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/gpio/consumer.h> @@ -1260,7 +1261,6 @@ static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); } - void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) { uint32_t irq_ctrl_stat_0, hs_stat, hs_enable; @@ -1293,7 +1293,7 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) } -void kmb_dsi_init(struct drm_device *dev) +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; @@ -1301,21 +1301,27 @@ void kmb_dsi_init(struct drm_device *dev) struct drm_connector *connector; struct kmb_dsi_host *host; struct kmb_drm_private *dev_p = dev->dev_private; + int ret = 0; kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); - if (!kmb_dsi) - return; + if (!kmb_dsi) { + DRM_ERROR("failed to allocate kmb_dsi\n"); + return -ENOMEM; + } kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); if (!kmb_connector) { kfree(kmb_dsi); - return; + DRM_ERROR("failed to allocate kmb_connector\n"); + return -ENOMEM; } kmb_dsi->attached_connector = kmb_connector; connector = &kmb_connector->base; encoder = &kmb_dsi->base; + encoder->possible_crtcs = 1; + encoder->possible_clones = 0; drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI"); @@ -1333,6 +1339,14 @@ void kmb_dsi_init(struct drm_device *dev) connector->encoder = encoder; drm_connector_attach_encoder(connector, encoder); + /* Link drm_bridge to encoder */ + ret = drm_bridge_attach(encoder, bridge, NULL, 0); + if (ret) { + DRM_ERROR("failed to attach bridge to MIPI\n"); + drm_encoder_cleanup(encoder); + return ret; + } + /* initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); @@ -1341,4 +1355,6 @@ void kmb_dsi_init(struct drm_device *dev) /* irq initialization */ mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + + return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 8f4e0b9..8135252 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -38,6 +38,7 @@ struct kmb_dsi { struct drm_encoder base; struct kmb_connector *attached_connector; struct kmb_dsi_host *dsi_host; + struct drm_bridge *bridge; }; struct kmb_dsi_host { @@ -328,7 +329,7 @@ union mipi_irq_cfg { } irq_cfg; }; -void kmb_dsi_init(struct drm_device *dev); +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:38 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:38 -0700 Subject: [Intel-gfx] [PATCH 26/59] drm/kmb: rebase to newer kernel version In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-27-git-send-email-anitha.chrisanthus@intel.com> cleanup code Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 5 +++-- drivers/gpu/drm/kmb/kmb_drv.h | 1 - 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index b0ab40b..1f0dcbe 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -301,8 +301,7 @@ DEFINE_DRM_GEM_CMA_FOPS(fops); static struct drm_driver kmb_driver = { .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | - DRIVER_MODESET | - DRIVER_ATOMIC, + DRIVER_MODESET | DRIVER_ATOMIC, .irq_handler = kmb_isr, .irq_preinstall = kmb_irq_reset, .irq_uninstall = kmb_irq_reset, @@ -378,6 +377,8 @@ static int kmb_drm_bind(struct device *dev) if (ret) goto err_register; + drm_fbdev_generic_setup(drm, 32); + return 0; err_register: diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 50efa8a..6c1d687 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -38,7 +38,6 @@ struct kmb_drm_private { void __iomem *msscam_mmio; unsigned char n_layers; struct clk *clk; - struct drm_fbdev_cma *fbdev; struct drm_crtc crtc; struct kmb_plane *plane; struct drm_atomic_state *state; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:40 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:40 -0700 Subject: [Intel-gfx] [PATCH 28/59] drm/kmb: Changed MMIO size In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-29-git-send-email-anitha.chrisanthus@intel.com> Also added debug messages Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 19 +++++++++++++++++-- drivers/gpu/drm/kmb/kmb_regs.h | 6 +++--- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index b1cc8ad..b4e1e50 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -49,6 +49,7 @@ #include "kmb_plane.h" #include "kmb_dsi.h" +#define DEBUG /*IRQ handler*/ static irqreturn_t kmb_isr(int irq, void *arg); @@ -331,18 +332,22 @@ static int kmb_drm_bind(struct device *dev) struct kmb_drm_private *lcd; int ret; + DRM_DEBUG("kmb_bind : ENTER\n"); drm = drm_dev_alloc(&kmb_driver, dev); if (IS_ERR(drm)) return PTR_ERR(drm); + DRM_DEBUG("kmb_bind : after alloc drm\n"); lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL); if (!lcd) return -ENOMEM; + DRM_DEBUG("kmb_bind : after alloc lcd\n"); drm->dev_private = lcd; dev_set_drvdata(dev, drm); kmb_setup_mode_config(drm); + DRM_DEBUG("kmb_bind : after kmb_setup_mode_config\n"); ret = kmb_load(drm, 0); if (ret) goto err_free; @@ -455,17 +460,27 @@ static int kmb_probe(struct platform_device *pdev) { struct device_node *port; struct component_match *match = NULL; + int ret; /* there is only one output port inside each device, find it */ + DRM_DEBUG("%s : ENTER", __func__); + port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); + DRM_DEBUG("%s : port = 0x%pOF\n", __func__, port); if (!port) return -ENODEV; + DRM_DEBUG("%s : after get_remote", __func__); + DRM_DEBUG("Adding component %pOF\n", port); drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); + DRM_DEBUG("%s : after get_match", __func__); of_node_put(port); - return component_master_add_with_match(&pdev->dev, &kmb_master_ops, - match); + ret = component_master_add_with_match(&pdev->dev, &kmb_master_ops, + match); + + DRM_DEBUG("%s : EXIT ret=%d\n", __func__, ret); + return ret; } static int kmb_remove(struct platform_device *pdev) diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index bb80bc5..f8a7abf 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -33,9 +33,9 @@ /*from Data Book section 12.11.6.1 page 4972 */ #define LCD_BASE_ADDR (0x20930000) #define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x10000) -#define LCD_MMIO_SIZE (0x10000) -#define MIPI_MMIO_SIZE (0x10000) -#define MSS_CAM_MMIO_SIZE (0x10000) +#define LCD_MMIO_SIZE (0x3000) +#define MIPI_MMIO_SIZE (0x4000) +#define MSS_CAM_MMIO_SIZE (0x10) /*************************************************************************** * LCD controller control register defines -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:43 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:43 -0700 Subject: [Intel-gfx] [PATCH 31/59] drm/kmb: Cleanup probe functions In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-32-git-send-email-anitha.chrisanthus@intel.com> From: Edmund Dea <edmund.j.dea at intel.com> - Removed deprecated code blocks within probe functions - In kmb_remove, unregister MIPI DSI host - In kmb_probe, if kmb_load fails, then unregister MIPI DSI host - Change kmb_dsi_host_bridge_init to return error codes using ERR_PTR - Do clock intitialization earlier - Rename kmb_drm_unbind to kmb_drm_unload. - Get mmio info from device tree Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 336 +++++++++++++++++++++++------------------- drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_dsi.c | 85 ++++------- 3 files changed, 218 insertions(+), 204 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 81af972..f520ca9 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -50,18 +50,18 @@ #include "kmb_dsi.h" #define DEBUG + /*IRQ handler*/ static irqreturn_t kmb_isr(int irq, void *arg); static struct clk *clk_lcd; static struct clk *clk_mipi; -static int probe_deferred; struct drm_bridge *adv_bridge; static int kmb_display_clk_enable(void) { - int ret; + int ret = 0; ret = clk_prepare_enable(clk_lcd); if (ret) { @@ -87,86 +87,142 @@ static int kmb_display_clk_disable(void) return 0; } +static void __iomem *kmb_map_mmio(struct platform_device *pdev, char *name) +{ + struct resource *res; + u32 size; + void __iomem *mem; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); + if (!res) { + DRM_ERROR("failed to get resource for %s\n", name); + return ERR_PTR(-ENOMEM); + } + size = resource_size(res); + if (!request_mem_region(res->start, size, name)) { + DRM_ERROR("failed to reserve %s registers\n", name); + return ERR_PTR(-ENOMEM); + } + mem = ioremap_cache(res->start, size); + if (!mem) { + DRM_ERROR("failed to ioremap %s registers\n", name); + release_mem_region(res->start, size); + return ERR_PTR(-ENOMEM); + } + return mem; +} + static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); -/* struct drm_bridge *bridge;*/ - /*struct resource *res;*/ /*u32 version;*/ - int ret; -/* struct device_node *encoder_node;*/ - - /* TBD - not sure if clock_get needs to be called here */ - /* - *dev_p->clk = devm_clk_get(drm->dev, "pxlclk"); - *if (IS_ERR(dev_p->clk)) - * return PTR_ERR(dev_p->clk); - */ - /* - * TBD call this in the future when device tree is ready, - * use hardcoded value for now - */ - /* - * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - * dev_p->lcd_mmio = devm_ioremap_resource(drm->dev, res); - - *if (IS_ERR(dev_p->lcd_mmio)) { - * DRM_ERROR("failed to map control registers area\n"); - * ret = PTR_ERR(dev_p->lcd_mmio); - * dev_p->lcd_mmio = NULL; - * return ret; - *} - */ - /* LCD mmio */ - probe_deferred = 1; + int ret = 0; - if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) { - DRM_ERROR("failed to reserve LCD registers\n"); - return -ENOMEM; - } - dev_p->lcd_mmio = ioremap_cache(LCD_BASE_ADDR, LCD_MMIO_SIZE); - if (!dev_p->lcd_mmio) { + /* Map LCD MMIO registers */ + dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs"); + if (IS_ERR(dev_p->lcd_mmio)) { DRM_ERROR("failed to map LCD registers\n"); return -ENOMEM; } - /* Mipi mmio */ - if (!request_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE, "kmb-mipi")) { - DRM_ERROR("failed to reserve MIPI registers\n"); + + /* Map MIPI MMIO registers */ + dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs"); + + if (IS_ERR(dev_p->mipi_mmio)) { + DRM_ERROR("failed to map MIPI registers\n"); iounmap(dev_p->lcd_mmio); return -ENOMEM; } - dev_p->mipi_mmio = ioremap_cache(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); - if (!dev_p->mipi_mmio) { - DRM_ERROR("failed to map MIPI registers\n"); + + /* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and MSS_CAM_CLK_CTRL + * register + */ + dev_p->msscam_mmio = kmb_map_mmio(pdev, "msscam_regs"); + if (IS_ERR(dev_p->msscam_mmio)) { + DRM_ERROR("failed to map MSSCAM registers\n"); iounmap(dev_p->lcd_mmio); + iounmap(dev_p->mipi_mmio); return -ENOMEM; } - /*this is only for MIPI_TX_MSS_LCD_MIPI_CFG register */ - if (!dev_p->msscam_mmio) { - dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR, - MSS_CAM_MMIO_SIZE); + + /* enable display clocks*/ + clk_lcd = clk_get(&pdev->dev, "clk_lcd"); + if (!clk_lcd) { + DRM_ERROR("clk_get() failed clk_lcd\n"); + goto setup_fail; + } + DRM_INFO("%s : %d\n", __func__, __LINE__); + + clk_mipi = clk_get(&pdev->dev, "clk_mipi"); + if (!clk_mipi) { + DRM_ERROR("clk_get() failed clk_mipi\n"); + goto setup_fail; } + DRM_INFO("%s : %d\n", __func__, __LINE__); + ret = kmb_display_clk_enable(); - /* register irqs here - section 17.3 in databook + /* set LCD clock to 200 Mhz*/ + DRM_INFO("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); + ret = clk_set_rate(clk_lcd, 200000000); + DRM_INFO("Setting LCD clock tp 200Mhz ret = %d\n", ret); + DRM_INFO("Get clk_lcd after set = %ld\n", clk_get_rate(clk_lcd)); + /* set MIPI clock to 24 Mhz*/ + DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); + ret = clk_set_rate(clk_mipi, 24000000); + DRM_INFO("Setting MIPI clock tp 24Mhz ret = %d\n", ret); + DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); + +#ifdef WIP + /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - * firmware has to redirect it to A53 */ + DRM_INFO("platform_get_irq_byname %pOF\n", drm->dev->of_node); + + /* Allocate LCD interrupt resources, enable interrupt line, + * and setup IRQ handling + */ + irq_lcd = platform_get_irq_byname(pdev, "irq_lcd"); + if (irq_lcd < 0) { + DRM_ERROR("irq_lcd not found"); + return irq_lcd; + } + + pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd); + + ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p); + dev_p->irq_lcd = irq_lcd; + + /* Allocate MIPI interrupt resources, enable interrupt line, + * and setup IRQ handling + */ + irq_mipi = platform_get_irq_byname(pdev, "irq_mipi"); + if (irq_mipi < 0) { + DRM_ERROR("irq_mipi not found"); + return irq_mipi; + } - /*TBD read and check for correct product version here */ + pr_info("irq_mipi platform_get_irq = %d\n", irq_mipi); + ret = request_irq(irq_mipi, kmb_isr, IRQF_SHARED, "irq_mipi", dev_p); + dev_p->irq_mipi = irq_mipi; +#endif + /* TBD read and check for correct product version here */ - /* Get the optional framebuffer memory resource */ + /* Get the optional framebuffer memory resource */ ret = of_reserved_mem_device_init(drm->dev); if (ret && ret != -ENODEV) return ret; spin_lock_init(&dev_p->irq_lock); + ret = kmb_setup_crtc(drm); if (ret < 0) { DRM_ERROR("failed to create crtc\n"); goto setup_fail; } + /* Initialize MIPI DSI */ ret = kmb_dsi_init(drm, adv_bridge); if (ret == -EPROBE_DEFER) { DRM_INFO("%s: wait for external bridge driver DT", __func__); @@ -175,26 +231,23 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } - /* enable display clocks*/ - clk_lcd = clk_get(&pdev->dev, "clk_lcd"); - if (!clk_lcd) { - DRM_ERROR("clk_get() failed clk_lcd\n"); - goto setup_fail; - } + DRM_INFO("%s : %d\n", __func__, __LINE__); - clk_mipi = clk_get(&pdev->dev, "clk_mipi"); - if (!clk_mipi) { - DRM_ERROR("clk_get() failed clk_mipi\n"); - goto setup_fail; +#ifdef WIP + ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); + if (ret < 0) { + DRM_ERROR("failed to install IRQ handler\n"); + goto irq_fail; } - DRM_INFO("%s : %d\n", __func__, __LINE__); - ret = kmb_display_clk_enable(); - - DRM_INFO("%s : %d clk enabling ret=%d\n", __func__, __LINE__, ret); +#endif return 0; +#ifdef WIP +irq_fail: drm_crtc_cleanup(&dev_p->crtc); +#endif setup_fail: + DRM_INFO("%s : %d\n", __func__, __LINE__); of_reserved_mem_device_release(drm->dev); return ret; @@ -304,62 +357,113 @@ static struct drm_driver kmb_driver = { .minor = 0, }; -static int kmb_drm_bind(struct device *dev) +static void kmb_drm_unload(struct device *dev) { + struct drm_device *drm = dev_get_drvdata(dev); + struct kmb_drm_private *dev_p = drm->dev_private; + + dump_stack(); + drm_dev_unregister(drm); + drm_kms_helper_poll_fini(drm); + of_node_put(dev_p->crtc.port); + dev_p->crtc.port = NULL; + pm_runtime_get_sync(drm->dev); + drm_irq_uninstall(drm); + pm_runtime_put_sync(drm->dev); + pm_runtime_disable(drm->dev); + + if (dev_p->lcd_mmio) { + iounmap(dev_p->lcd_mmio); + release_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE); + } + + if (dev_p->mipi_mmio) { + iounmap(dev_p->mipi_mmio); + release_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); + } + + if (dev_p->msscam_mmio) + iounmap(dev_p->msscam_mmio); + + of_reserved_mem_device_release(drm->dev); + drm_mode_config_cleanup(drm); + + /*release clks */ + kmb_display_clk_disable(); + clk_put(clk_lcd); + clk_put(clk_mipi); + + drm_dev_put(drm); + drm->dev_private = NULL; + dev_set_drvdata(dev, NULL); + + /* Unregister DSI host */ + mipi_dsi_host_unregister(dsi_host); +} + +static int kmb_probe(struct platform_device *pdev) +{ + struct device *dev = get_device(&pdev->dev); struct drm_device *drm = NULL; struct kmb_drm_private *lcd; - int ret; + int ret = 0; + + /* The bridge (ADV 7535) will return -EPROBE_DEFER until it + * has a mipi_dsi_host to register its device to. So, we + * first register the DSI host during probe time, and then return + * -EPROBE_DEFER until the bridge is loaded. Probe will be called again + * and then the rest of the driver initialization can procees + * afterwards and the bridge can be successfully attached. + */ + adv_bridge = kmb_dsi_host_bridge_init(dev); + if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) + return -EPROBE_DEFER; + else if (IS_ERR(adv_bridge)) { + DRM_ERROR("probe failed to initialize DSI host bridge\n"); + return PTR_ERR(adv_bridge); + } - DRM_DEBUG("%s : ENTER", __func__); + /* Create DRM device */ drm = drm_dev_alloc(&kmb_driver, dev); if (IS_ERR(drm)) return PTR_ERR(drm); - DRM_DEBUG("%s : after alloc drm", __func__); lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL); if (!lcd) return -ENOMEM; - DRM_DEBUG("%s : after alloc lcd", __func__); drm->dev_private = lcd; - kmb_setup_mode_config(drm); dev_set_drvdata(dev, drm); - /* load the driver */ + /* Load driver */ ret = kmb_load(drm, 0); - DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); if (ret == -EPROBE_DEFER) { - DRM_INFO("kmb_bind: wait for external bridge driver DT\n"); + DRM_INFO("wait for external bridge driver DT\n"); return -EPROBE_DEFER; } else if (ret) goto err_free; - DRM_INFO("%s : %d\n", __func__, __LINE__); /* Set the CRTC's port so that the encoder component can find it */ lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); - DRM_INFO("crtc port = %pOF\n", lcd->crtc.port); + ret = drm_vblank_init(drm, drm->mode_config.num_crtc); if (ret < 0) { - DRM_ERROR("failed to initialise vblank\n"); + DRM_ERROR("failed to initialize vblank\n"); goto err_vblank; } - DRM_INFO("%s : %d\n", __func__, __LINE__); drm_mode_config_reset(drm); - DRM_INFO("%s : %d\n", __func__, __LINE__); drm_kms_helper_poll_init(drm); - DRM_INFO("%s : %d\n", __func__, __LINE__); + /* Register graphics device with the kernel */ ret = drm_dev_register(drm, 0); - DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); lcd->n_layers = KMB_MAX_PLANES; if (ret) goto err_register; drm_fbdev_generic_setup(drm, 32); - DRM_INFO("%s : %d\n", __func__, __LINE__); return 0; @@ -367,86 +471,18 @@ static int kmb_drm_bind(struct device *dev) drm_kms_helper_poll_fini(drm); err_vblank: pm_runtime_disable(drm->dev); - of_node_put(lcd->crtc.port); - lcd->crtc.port = NULL; - drm_irq_uninstall(drm); - of_reserved_mem_device_release(drm->dev); err_free: drm_mode_config_cleanup(drm); dev_set_drvdata(dev, NULL); drm_dev_put(drm); + mipi_dsi_host_unregister(dsi_host); return ret; } -static void kmb_drm_unbind(struct device *dev) -{ - struct drm_device *drm = dev_get_drvdata(dev); - struct kmb_drm_private *dev_p = drm->dev_private; - - dump_stack(); - drm_dev_unregister(drm); - drm_kms_helper_poll_fini(drm); - of_node_put(dev_p->crtc.port); - dev_p->crtc.port = NULL; - pm_runtime_get_sync(drm->dev); - drm_irq_uninstall(drm); - pm_runtime_put_sync(drm->dev); - pm_runtime_disable(drm->dev); - - DRM_INFO("%s : %d\n", __func__, __LINE__); - if (dev_p->lcd_mmio) { - DRM_INFO("%s : %d\n", __func__, __LINE__); - iounmap(dev_p->lcd_mmio); - release_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE); - } - - if (dev_p->mipi_mmio) { - DRM_INFO("%s : %d\n", __func__, __LINE__); - iounmap(dev_p->mipi_mmio); - release_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); - } - - if (dev_p->msscam_mmio) - iounmap(dev_p->msscam_mmio); - - DRM_INFO("%s : %d\n", __func__, __LINE__); - of_reserved_mem_device_release(drm->dev); - drm_mode_config_cleanup(drm); - - /*release clks */ - kmb_display_clk_disable(); - clk_put(clk_lcd); - clk_put(clk_mipi); - - drm_dev_put(drm); - drm->dev_private = NULL; - dev_set_drvdata(dev, NULL); - DRM_INFO("%s : %d\n", __func__, __LINE__); -} - -static int kmb_probe(struct platform_device *pdev) -{ - struct device *device = get_device(&pdev->dev); - - /* there is only one output port inside each device, find it */ - DRM_DEBUG("%s : ENTER", __func__); - - adv_bridge = kmb_dsi_host_bridge_init(device); - if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) - return -EPROBE_DEFER; - else if (adv_bridge < 0) { - DRM_ERROR(" PROBE failed\n"); - return -EINVAL; - } - - return kmb_drm_bind(&pdev->dev); -} - static int kmb_remove(struct platform_device *pdev) { -// component_master_del(&pdev->dev, &kmb_master_ops); - kmb_drm_unbind(&pdev->dev); + kmb_drm_unload(&pdev->dev); return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 6c1d687..c87e608 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -31,6 +31,7 @@ #define KMB_MAX_WIDTH 16384 /*max width in pixels */ #define KMB_MAX_HEIGHT 16384 /*max height in pixels */ +extern struct mipi_dsi_host *dsi_host; struct kmb_drm_private { struct drm_device drm; void __iomem *lcd_mmio; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 8741d78..4b5adc7c 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -79,7 +79,7 @@ #define PLL_M_MAX 623 #define PLL_FVCO_MAX 1250 -static struct mipi_dsi_host *dsi_host; +struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device; /* @@ -314,10 +314,10 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) { - int ret; struct device_node *encoder_node; struct drm_bridge *bridge; + /* Create and register MIPI DSI host */ if (!dsi_host) { dsi_host = kzalloc(sizeof(*dsi_host), GFP_KERNEL); if (!dsi_host) @@ -325,31 +325,27 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) dsi_host->ops = &kmb_dsi_host_ops; - if (!dsi_device) - dsi_device = kzalloc(sizeof(*dsi_device), GFP_KERNEL); if (!dsi_device) { - kfree(dsi_host); - return ERR_PTR(-ENOMEM); + dsi_device = kzalloc(sizeof(*dsi_device), GFP_KERNEL); + if (!dsi_device) { + kfree(dsi_host); + return ERR_PTR(-ENOMEM); + } } dsi_host->dev = dev; - ret = mipi_dsi_host_register(dsi_host); - if (ret < 0) { - DRM_ERROR("failed to register DSI host: %d\n", ret); - kfree(dsi_host); - kfree(dsi_device); - return ERR_PTR(ret); - } + mipi_dsi_host_register(dsi_host); } /* find ADV7535 node and initialize it */ - DRM_DEBUG("trying to get bridge info %pOF\n", dev->of_node); + DRM_INFO("trying to get bridge info %pOF\n", dev->of_node); encoder_node = of_parse_phandle(dev->of_node, "encoder-slave", 0); - DRM_DEBUG("encoder node = %pOF\n", encoder_node); + DRM_INFO("encoder node = %pOF\n", encoder_node); if (!encoder_node) { DRM_ERROR("failed to get bridge info from DT\n"); - ret = -EINVAL; + return ERR_PTR(-EINVAL); } + /* Locate drm bridge from the hdmi encoder DT node */ bridge = of_drm_find_bridge(encoder_node); of_node_put(encoder_node); @@ -357,6 +353,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) DRM_INFO("wait for external bridge driver DT\n"); return ERR_PTR(-EPROBE_DEFER); } + return bridge; } @@ -487,9 +484,9 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, u32 ctrl_no = MIPI_CTRL6; u32 reg_adr; - /*frame section packet header */ - /*word count */ - cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0] */ + /*frame section packet header*/ + /*word count*/ + cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0]*/ /*data type */ cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) << MIPI_TX_SECT_DT_SHIFT); /* bits [21:16] */ @@ -502,7 +499,6 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, cfg |= MIPI_TX_SECT_DMA_PACKED; kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, section)), cfg); - /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections *there are 2 registers for unpacked bytes - @@ -513,7 +509,7 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) + (section/2)*4; kmb_write_bits_mipi(dev_p, reg_adr, (section % 2)*16, 16, - unpacked_bytes); + unpacked_bytes); /* line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); @@ -531,10 +527,9 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, struct mipi_data_type_params data_type_parameters; struct mipi_tx_frame_sect_phcfg ph_cfg; - ret = - mipi_get_datatype_params(frame_scfg->data_type, - frame_scfg->data_mode, - &data_type_parameters); + ret = mipi_get_datatype_params(frame_scfg->data_type, + frame_scfg->data_mode, + &data_type_parameters); if (ret) return ret; /* @@ -542,7 +537,7 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, * (in pixels) set for each data type */ if (frame_scfg->width_pixels % - data_type_parameters.size_constraint_pixels != 0) + data_type_parameters.size_constraint_pixels != 0) return -EINVAL; *wc = compute_wc(frame_scfg->width_pixels, @@ -558,8 +553,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, ph_cfg.vchannel = frame_id; mipi_tx_fg_section_cfg_regs(dev_p, frame_id, section, - frame_scfg->height_lines, - unpacked_bytes, &ph_cfg); + frame_scfg->height_lines, + unpacked_bytes, &ph_cfg); /*caller needs bits_per_clk for additional caluclations */ *bits_per_pclk = data_type_parameters.bits_per_pclk; @@ -720,7 +715,6 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6; - DRM_INFO("%s : %d\n", __func__, __LINE__); /*MIPI_TX_HS_SYNC_CFG*/ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; @@ -732,7 +726,6 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, sync_cfg |= DSI_V_BLANKING; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) sync_cfg |= DSI_HSA_BLANKING; - DRM_INFO("%s : %d\n", __func__, __LINE__); if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) sync_cfg |= DSI_HBP_BLANKING; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) @@ -744,7 +737,6 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) sync_cfg |= DSI_LPM_LAST_VFP_LINE; /* enable frame generator */ - DRM_INFO("%s : %d\n", __func__, __LINE__); fg_en = 1 << fg_id; sync_cfg |= FRAME_GEN_EN(fg_en); if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) @@ -763,9 +755,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, /*67 ns stop time */ ctrl |= HSEXIT_CNT(0x43); - DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_write_mipi(dev_p, MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); - DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_write_mipi(dev_p, MIPI_TXm_HS_CTRL(ctrl_no), ctrl); } @@ -786,18 +776,20 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, * set mipitxcctrlcfg */ + DRM_INFO("%s : %d\n", __func__, __LINE__); for (frame_id = 0; frame_id < 4; frame_id++) { /* find valid frame, assume only one valid frame */ if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id] == NULL) continue; + DRM_INFO("%s : %d\n", __func__, __LINE__); /* Frame Section configuration */ /*TODO - assume there is only one valid section in a frame, so * bits_per_pclk and word_count are only set once */ for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] - == NULL) + == NULL) continue; ret = mipi_tx_fg_section_cfg(dev_p, frame_id, sect, @@ -810,9 +802,9 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, /* set frame specific parameters */ mipi_tx_fg_cfg(dev_p, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + bits_per_pclk, + word_count, ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); active_vchannels++; @@ -1348,7 +1340,6 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) } int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) -//int kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; @@ -1358,7 +1349,6 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) struct kmb_drm_private *dev_p = dev->dev_private; int ret = 0; - DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); if (!kmb_dsi) { DRM_ERROR("failed to allocate kmb_dsi\n"); @@ -1372,12 +1362,9 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return -ENOMEM; } - DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_dsi->attached_connector = kmb_connector; - DRM_INFO("%s : %d\n", __func__, __LINE__); host = kmb_dsi_host_init(dev, kmb_dsi); - DRM_INFO("%s : %d\n", __func__, __LINE__); if (!host) { DRM_ERROR("Faile to allocate host\n"); // drm_encoder_cleanup(encoder); @@ -1386,30 +1373,23 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return -ENOMEM; } - DRM_INFO("%s : %d\n", __func__, __LINE__); connector = &kmb_connector->base; - DRM_INFO("%s : %d\n", __func__, __LINE__); encoder = &kmb_dsi->base; encoder->possible_crtcs = 1; encoder->possible_clones = 0; - DRM_INFO("%s : %d\n", __func__, __LINE__); drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI"); - DRM_INFO("%s : %d\n", __func__, __LINE__); drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, DRM_MODE_CONNECTOR_DSI); - DRM_INFO("%s : %d\n", __func__, __LINE__); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); - DRM_INFO("%s : %d\n", __func__, __LINE__); -// connector->encoder = encoder; DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, __LINE__, connector->name, encoder->name); ret = drm_connector_attach_encoder(connector, encoder); + /* Link drm_bridge to encoder */ - DRM_INFO("%s : %d\n", __func__, __LINE__); ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) { DRM_ERROR("failed to attach bridge to MIPI\n"); @@ -1417,18 +1397,15 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return ret; } - DRM_INFO("%s : %d\n", __func__, __LINE__); + DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); /* initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); - DRM_INFO("%s : %d\n", __func__, __LINE__); /*d-phy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); - DRM_INFO("%s : %d\n", __func__, __LINE__); /* irq initialization */ mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); - DRM_INFO("%s : %d\n", __func__, __LINE__); return 0; } -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:47 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:47 -0700 Subject: [Intel-gfx] [PATCH 35/59] drm/kmb: Remove declaration of irq_lcd/irq_mipi In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-36-git-send-email-anitha.chrisanthus@intel.com> From: Edmund Dea <edmund.j.dea at intel.com> Made it conditionally compiled. Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 4eb472b..1aedcf8 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -143,7 +143,10 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); +#ifdef WIP /*u32 version;*/ + int irq_lcd, irq_mipi; +#endif int ret = 0; unsigned long clk; @@ -297,9 +300,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) pr_info("irq_mipi platform_get_irq = %d\n", irq_mipi); ret = request_irq(irq_mipi, kmb_isr, IRQF_SHARED, "irq_mipi", dev_p); dev_p->irq_mipi = irq_mipi; -#endif - /* TBD read and check for correct product version here */ + /* TBD read and check for correct product version here */ +#endif /* Get the optional framebuffer memory resource */ ret = of_reserved_mem_device_init(drm->dev); if (ret && ret != -ENODEV) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:48 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:48 -0700 Subject: [Intel-gfx] [PATCH 36/59] drm/kmb: Enable MIPI TX HS Test Pattern Generation In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-37-git-send-email-anitha.chrisanthus@intel.com> From: Edmund Dea <edmund.j.dea at intel.com> Added test pattern generator function. Enable this at compile time to test if mipi is working. mipi->hdmi section Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 31 +++++++++++++++++++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.h | 7 +++++++ drivers/gpu/drm/kmb/kmb_regs.h | 11 +++++++++++ 3 files changed, 49 insertions(+) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 8ab4de7..47ec2ab 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -764,6 +764,32 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, kmb_write_mipi(dev_p, MIPI_TXm_HS_CTRL(ctrl_no), ctrl); } +#ifdef MIPI_TX_TEST_PATTERN_GENERATION +static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, + int tp_sel, u32 stripe_width, u32 color0, u32 color1) +{ + u32 ctrl_no = MIPI_CTRL6; + + /* Select test pattern mode on the virtual channel */ + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), + TP_SEL_VCm(vc, tp_sel)); + + if (tp_sel == MIPI_TX_HS_TP_V_STRIPES || + tp_sel == MIPI_TX_HS_TP_H_STRIPES) { + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), + TP_STRIPE_WIDTH(stripe_width)); + } + + /* Configure test pattern colors */ + kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR0, color0); + kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR1, color1); + + /* Enable test pattern generation on the virtual channel */ + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), + TP_EN_VCm(vc)); +} +#endif + static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, struct mipi_ctrl_cfg *ctrl_cfg) { @@ -827,6 +853,11 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, /*Multi-Channel FIFO Configuration*/ mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id); +#ifdef MIPI_TX_TEST_PATTERN_GENERATION + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0, 0, + 0xffffffff, 0); +#endif + /*Frame Generator Enable */ mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg); return ret; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index e85625b..ef526b4 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -200,6 +200,13 @@ enum mipi_dsi_data_type { DSI_LP_DT_RESERVED_3F = 0x3f }; +enum mipi_tx_hs_tp_sel { + MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0 = 0, + MIPI_TX_HS_TP_WHOLE_FRAME_COLOR1, + MIPI_TX_HS_TP_V_STRIPES, + MIPI_TX_HS_TP_H_STRIPES, +}; + enum dphy_mode { MIPI_DPHY_SLAVE = 0, MIPI_DPHY_MASTER diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 20b331d..2377439 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -645,6 +645,17 @@ MIPI_TX_HS_IRQ_CLEAR \ + HS_OFFSET(M), val) +/* MIPI Test Pattern Generation */ +#define MIPI_TX_HS_TEST_PAT_CTRL (0x230) +#define MIPI_TXm_HS_TEST_PAT_CTRL(M) \ + (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M)) +#define TP_EN_VCm(M) ((M) * 0x04) +#define TP_SEL_VCm(M, N) \ + (N << (((M) * 0x04) + 1)) +#define TP_STRIPE_WIDTH(M) ((M) << 16) +#define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234) +#define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238) + /* D-PHY regs */ #define DPHY_ENABLE (0x100) #define DPHY_INIT_CTRL0 (0x104) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:49 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:49 -0700 Subject: [Intel-gfx] [PATCH 37/59] drm/kmb: Set MSS_CAM_RSTN_CTRL along with enable In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-38-git-send-email-anitha.chrisanthus@intel.com> Also moved num_planes init before load, time out for dsi fixed kmb regs read/write to only pass dev_p and few other minor changes. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 32 ++++++++++++++------------------ drivers/gpu/drm/kmb/kmb_drv.h | 34 +++++++++++++++++----------------- drivers/gpu/drm/kmb/kmb_dsi.c | 37 ++++++++++++++++++++++++++++--------- drivers/gpu/drm/kmb/kmb_plane.c | 27 +++++++++++++++++---------- drivers/gpu/drm/kmb/kmb_regs.h | 1 + 5 files changed, 77 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 1aedcf8..1fc0b2e 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -78,11 +78,12 @@ static int kmb_display_clk_enable(void) return ret; } - ret = clk_prepare_enable(clk_msscam); +/* ret = clk_prepare_enable(clk_msscam); if (ret) { DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret); return ret; } + */ ret = clk_prepare_enable(clk_mipi_ecfg); if (ret) { @@ -136,6 +137,8 @@ static void __iomem *kmb_map_mmio(struct platform_device *pdev, char *name) release_mem_region(res->start, size); return ERR_PTR(-ENOMEM); } + DRM_INFO("%s : %d mapped %s mmio size = %d\n", __func__, __LINE__, + name, size); return mem; } @@ -150,13 +153,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) int ret = 0; unsigned long clk; - /* Map LCD MMIO registers */ - dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs"); - if (IS_ERR(dev_p->lcd_mmio)) { - DRM_ERROR("failed to map LCD registers\n"); - return -ENOMEM; - } - /* Map MIPI MMIO registers */ dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs"); if (IS_ERR(dev_p->mipi_mmio)) { @@ -165,6 +161,13 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) return -ENOMEM; } + /* Map LCD MMIO registers */ + dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs"); + if (IS_ERR(dev_p->lcd_mmio)) { + DRM_ERROR("failed to map LCD registers\n"); + return -ENOMEM; + } + /* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and MSS_CAM_CLK_CTRL * register */ @@ -189,12 +192,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } - clk_msscam = clk_get(&pdev->dev, "clk_msscam"); - if (IS_ERR(clk_msscam)) { - DRM_ERROR("clk_get() failed clk_msscam\n"); - goto setup_fail; - } - clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); if (IS_ERR(clk_mipi_ecfg)) { DRM_ERROR("clk_get() failed clk_mipi_ecfg\n"); @@ -215,7 +212,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) if (clk_get_rate(clk_lcd) != KMB_LCD_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_lcd to %d\n", KMB_LCD_DEFAULT_CLK); - goto setup_fail; } DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n", KMB_LCD_DEFAULT_CLK/1000000, ret); @@ -265,8 +261,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) } /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ - kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, LCD | MIPI_COMMON | - MIPI_TX0); + kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0xfff); + kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xfff); #ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - @@ -528,6 +524,7 @@ static int kmb_probe(struct platform_device *pdev) dev_set_drvdata(dev, drm); /* Load driver */ + lcd->n_layers = KMB_MAX_PLANES; ret = kmb_load(drm, 0); if (ret == -EPROBE_DEFER) { DRM_INFO("wait for external bridge driver DT\n"); @@ -550,7 +547,6 @@ static int kmb_probe(struct platform_device *pdev) /* Register graphics device with the kernel */ ret = drm_dev_register(drm, 0); - lcd->n_layers = KMB_MAX_PLANES; if (ret) goto err_register; diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 596f4fe..1511cd1 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -28,9 +28,9 @@ #include "kmb_regs.h" -#define KMB_MAX_WIDTH 16384 /*max width in pixels */ -#define KMB_MAX_HEIGHT 16384 /*max height in pixels */ -#define KMB_LCD_DEFAULT_CLK 200000000 +#define KMB_MAX_WIDTH 1920 /*max width in pixels */ +#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ +#define KMB_LCD_DEFAULT_CLK 24000000 #define KMB_MIPI_DEFAULT_CLK 24000000 struct kmb_drm_private { @@ -130,17 +130,17 @@ static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { - u32 reg_val = kmb_read_lcd(dev_p->lcd_mmio, reg); + u32 reg_val = kmb_read_lcd(dev_p, reg); - kmb_write_lcd(dev_p->lcd_mmio, reg, (reg_val | mask)); + kmb_write_lcd(dev_p, reg, (reg_val | mask)); } static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { - u32 reg_val = kmb_read_lcd(dev_p->lcd_mmio, reg); + u32 reg_val = kmb_read_lcd(dev_p, reg); - kmb_write_lcd(dev_p->lcd_mmio, reg, (reg_val & (~mask))); + kmb_write_lcd(dev_p, reg, (reg_val & (~mask))); } static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) @@ -151,46 +151,46 @@ static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) static inline void kmb_write_bits_mipi(struct kmb_drm_private *dev_p, unsigned int reg, u32 offset, u32 num_bits, u32 value) { - u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); + u32 reg_val = kmb_read_mipi(dev_p, reg); u32 mask = (1 << num_bits) - 1; value &= mask; mask <<= offset; reg_val &= (~mask); reg_val |= (value << offset); - kmb_write_mipi(dev_p->mipi_mmio, reg, reg_val); + kmb_write_mipi(dev_p, reg, reg_val); } static inline void kmb_set_bit_mipi(struct kmb_drm_private *dev_p, unsigned int reg, u32 offset) { - u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); + u32 reg_val = kmb_read_mipi(dev_p, reg); - kmb_write_mipi(dev_p->mipi_mmio, reg, reg_val | (1 << offset)); + kmb_write_mipi(dev_p, reg, reg_val | (1 << offset)); } static inline void kmb_clr_bit_mipi(struct kmb_drm_private *dev_p, unsigned int reg, u32 offset) { - u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); + u32 reg_val = kmb_read_mipi(dev_p, reg); - kmb_write_mipi(dev_p->mipi_mmio, reg, reg_val & (~(1 << offset))); + kmb_write_mipi(dev_p, reg, reg_val & (~(1 << offset))); } static inline void kmb_set_bitmask_mipi(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { - u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); + u32 reg_val = kmb_read_mipi(dev_p, reg); - kmb_write_mipi(dev_p->mipi_mmio, reg, (reg_val | mask)); + kmb_write_mipi(dev_p, reg, (reg_val | mask)); } static inline void kmb_clr_bitmask_mipi(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { - u32 reg_val = kmb_read_mipi(dev_p->mipi_mmio, reg); + u32 reg_val = kmb_read_mipi(dev_p, reg); - kmb_write_mipi(dev_p->mipi_mmio, reg, (reg_val & (~mask))); + kmb_write_mipi(dev_p, reg, (reg_val & (~mask))); } int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 47ec2ab..40fe552 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -227,12 +227,12 @@ kmb_dsi_mode_valid(struct drm_connector *connector, static int kmb_dsi_get_modes(struct drm_connector *connector) { - struct drm_display_mode *mode; - struct kmb_connector *kmb_connector = to_kmb_connector(connector); + int num_modes = 0; - mode = drm_mode_duplicate(connector->dev, kmb_connector->fixed_mode); - drm_mode_probed_add(connector, mode); - return 1; + num_modes = drm_add_modes_noedid(connector, + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); + return num_modes; } static void kmb_dsi_connector_destroy(struct drm_connector *connector) @@ -502,6 +502,8 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ cfg |= MIPI_TX_SECT_DMA_PACKED; + DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x\n", + __func__, __LINE__, ctrl_no, frame_id, section, cfg); kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, section)), cfg); /*unpacked bytes */ @@ -574,7 +576,7 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, u32 ppl_llp_ratio; u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset; - /*Get system clock for blanking period cnfigurations */ + /*Get system clock for blanking period cnfigurations*/ /*TODO need to get system clock from clock driver */ /* Assume 700 Mhz system clock for now */ sysclk = 700; @@ -593,6 +595,7 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active); + DRM_INFO("%s : %d\n", __func__, __LINE__); /*vsync width */ /* *there are 2 registers for vsync width -VSA in lines for channels 0-3 @@ -646,6 +649,7 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); + DRM_INFO("%s : %d\n", __func__, __LINE__); /* llp h frontporch */ reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, @@ -807,13 +811,11 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, * set mipitxcctrlcfg */ - DRM_INFO("%s : %d\n", __func__, __LINE__); for (frame_id = 0; frame_id < 4; frame_id++) { /* find valid frame, assume only one valid frame */ if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id] == NULL) continue; - DRM_INFO("%s : %d\n", __func__, __LINE__); /* Frame Section configuration */ /*TODO - assume there is only one valid section in a frame, so * bits_per_pclk and word_count are only set once @@ -1231,13 +1233,18 @@ static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no, enum dphy_tx_fsm fsm_state) { enum dphy_tx_fsm val = DPHY_TX_POWERDWN; + int i = 0; do { test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); /*TODO-need to add a time out and return failure */ val = GET_TEST_DOUT0_3(dev_p, dphy_no); + i++; + if (i > 50000) { + DRM_INFO("%s: timing out\n", __func__); + break; + } } while (val != fsm_state); - } static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, @@ -1245,10 +1252,16 @@ static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, { u32 stopstatedata = 0; u32 data_lanes = (1 << active_lanes) - 1; + int i = 0; do { stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no); /*TODO-need to add a time out and return failure */ + i++; + if (i > 50000) { + DRM_INFO("%s: timing out", __func__); + break; + } } while (stopstatedata != data_lanes); return 0; @@ -1256,9 +1269,15 @@ static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) { + int i = 0; do { ; /*TODO-need to add a time out and return failure */ + i++; + if (i > 50000) { + DRM_INFO("wait_pll_lock: timing out\n"); + break; + } } while (!GET_PLL_LOCK(dev_p, dphy_no)); return 0; diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 026df49..de5ca88 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -498,7 +498,7 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) struct kmb_plane *plane = NULL; struct kmb_plane *primary = NULL; int i = 0; - int ret; + int ret = 0; enum drm_plane_type plane_type; const uint32_t *plane_formats; int num_plane_formats; @@ -507,11 +507,13 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); - if (!plane) + if (!plane) { + DRM_ERROR("Failed to allocate plane\n"); return ERR_PTR(-ENOMEM); + } plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : - DRM_PLANE_TYPE_OVERLAY; + DRM_PLANE_TYPE_OVERLAY; if (i < 2) { plane_formats = kmb_formats_v; num_plane_formats = ARRAY_SIZE(kmb_formats_v); @@ -520,13 +522,16 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) num_plane_formats = ARRAY_SIZE(kmb_formats_g); } - ret = - drm_universal_plane_init(drm, &plane->base_plane, - POSSIBLE_CRTCS, &kmb_plane_funcs, - plane_formats, num_plane_formats, - NULL, plane_type, "plane %d", i); - if (ret < 0) + ret = drm_universal_plane_init(drm, &plane->base_plane, + POSSIBLE_CRTCS, + &kmb_plane_funcs, plane_formats, + num_plane_formats, + NULL, plane_type, "plane %d", i); + if (ret < 0) { + DRM_ERROR("drm_universal_plane_init -failed with ret=%d" + , ret); goto cleanup; + } drm_plane_helper_add(&plane->base_plane, &kmb_plane_helper_funcs); @@ -537,6 +542,8 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) plane->id = i; } -cleanup: return primary; +cleanup: + kfree(plane); + return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 2377439..9ca7851 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -713,6 +713,7 @@ #define LCD (1<<1) #define MIPI_COMMON (1<<2) #define MIPI_TX0 (1<<9) +#define MSS_CAM_RSTN_CTRL (0x14) #define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:51 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:51 -0700 Subject: [Intel-gfx] [PATCH 39/59] drm/kmb: Fixed driver unload In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-40-git-send-email-anitha.chrisanthus@intel.com> unmap MSSCAM registers Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 15 +++------------ drivers/gpu/drm/kmb/kmb_drv.h | 1 - drivers/gpu/drm/kmb/kmb_regs.h | 2 +- 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index b5c8711..e9dd879 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -179,17 +179,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) iounmap(dev_p->mipi_mmio); return -ENOMEM; } -/*testing*/ - if (!request_mem_region(CPR_BASE_ADDR, 100, "cpr")) { - DRM_ERROR("failed to reserve %s registers\n", "cpr"); - return -ENOMEM; - } - dev_p->cpr_mmio = ioremap_cache(CPR_BASE_ADDR, 0x100); - if (!dev_p->cpr_mmio) { - DRM_ERROR("failed to ioremap %s registers\n", "CPR"); - release_mem_region(CPR_BASE_ADDR, 100); - return -ENOMEM; - } if (IS_ERR(dev_p->msscam_mmio)) { DRM_ERROR("failed to map MSSCAM registers\n"); @@ -509,8 +498,10 @@ static void kmb_drm_unload(struct device *dev) release_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); } - if (dev_p->msscam_mmio) + if (dev_p->msscam_mmio) { iounmap(dev_p->msscam_mmio); + release_mem_region(MSS_CAM_BASE_ADDR, MSS_CAM_MMIO_SIZE); + } of_reserved_mem_device_release(drm->dev); drm_mode_config_cleanup(drm); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 58bb967..da1df5c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -40,7 +40,6 @@ struct kmb_drm_private { void __iomem *lcd_mmio; void __iomem *mipi_mmio; void __iomem *msscam_mmio; - void __iomem *cpr_mmio; unsigned char n_layers; struct clk *clk; struct drm_crtc crtc; diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index eb84320..255c44d 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -36,7 +36,7 @@ #define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR + 0x10000) #define LCD_MMIO_SIZE (0x3000) #define MIPI_MMIO_SIZE (0x4000) -#define MSS_CAM_MMIO_SIZE (0x10) +#define MSS_CAM_MMIO_SIZE (0x30) /*************************************************************************** * LCD controller control register defines -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:50 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:50 -0700 Subject: [Intel-gfx] [PATCH 38/59] drm/kmb: Mipi DPHY initialization changes In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-39-git-send-email-anitha.chrisanthus@intel.com> Fix test_mode_send and dphy_wait_fsm for 2-lane MIPI - Fix test_mode_send when sending normal mode test codes - Change dphy_wait_fsm to check for IDLE status rather than LOCK status for 2-lane MIPI Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 23 +- drivers/gpu/drm/kmb/kmb_drv.c | 90 ++-- drivers/gpu/drm/kmb/kmb_drv.h | 23 +- drivers/gpu/drm/kmb/kmb_dsi.c | 904 +++++++++++++++++++++++++++++----------- drivers/gpu/drm/kmb/kmb_dsi.h | 2 +- drivers/gpu/drm/kmb/kmb_plane.c | 59 ++- drivers/gpu/drm/kmb/kmb_regs.h | 34 +- 7 files changed, 840 insertions(+), 295 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 053da17..01ad82e 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -41,6 +41,7 @@ #include "kmb_drv.h" #include "kmb_plane.h" #include "kmb_regs.h" +#include "kmb_dsi.h" static void kmb_crtc_cleanup(struct drm_crtc *crtc) { @@ -93,23 +94,33 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = { static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) { - struct drm_display_mode *m = &crtc->state->adjusted_mode; struct drm_device *dev = crtc->dev; +#ifdef LCD_TEST + struct drm_display_mode *m = &crtc->state->adjusted_mode; struct videomode vm; int vsync_start_offset; int vsync_end_offset; unsigned int ctrl = 0; - +#endif + /* initialize mipi */ + kmb_dsi_hw_init(dev); +#ifdef LCD_TEST vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; - vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; + //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; + vm.hfront_porch = 0; vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; + DRM_INFO("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d\n", + __func__, __LINE__, m->crtc_vdisplay, + vm.vback_porch, vm.vfront_porch, + vm.vsync_len, m->crtc_hdisplay, + vm.hback_porch, vm.hfront_porch, vm.hsync_len); kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1); kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch - 1); @@ -144,7 +155,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl); kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE); - +#endif /* TBD */ /* set clocks here */ } @@ -156,7 +167,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc, clk_prepare_enable(lcd->clk); kmb_crtc_mode_set_nofb(crtc); - drm_crtc_vblank_on(crtc); +// drm_crtc_vblank_on(crtc); } static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, @@ -167,7 +178,7 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, /* always disable planes on the CRTC that is being turned off */ drm_atomic_helper_disable_planes_on_crtc(old_state, false); - drm_crtc_vblank_off(crtc); +// drm_crtc_vblank_off(crtc); clk_disable_unprepare(lcd->clk); } diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 1fc0b2e..b5c8711 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -34,6 +34,7 @@ #include <linux/pm_runtime.h> #include <linux/clk.h> #include <drm/drm.h> +#include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_probe_helper.h> @@ -57,27 +58,27 @@ static irqreturn_t kmb_isr(int irq, void *arg); static struct clk *clk_lcd; static struct clk *clk_mipi; static struct clk *clk_msscam; +static struct clk *clk_pll0out0; static struct clk *clk_mipi_ecfg; static struct clk *clk_mipi_cfg; struct drm_bridge *adv_bridge; -static int kmb_display_clk_enable(void) +int kmb_display_clk_enable(void) { int ret = 0; - +#ifdef LCD_TEST ret = clk_prepare_enable(clk_lcd); if (ret) { DRM_ERROR("Failed to enable LCD clock: %d\n", ret); return ret; } - +#endif ret = clk_prepare_enable(clk_mipi); if (ret) { DRM_ERROR("Failed to enable MIPI clock: %d\n", ret); return ret; } - /* ret = clk_prepare_enable(clk_msscam); if (ret) { DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret); @@ -178,19 +179,47 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) iounmap(dev_p->mipi_mmio); return -ENOMEM; } +/*testing*/ + if (!request_mem_region(CPR_BASE_ADDR, 100, "cpr")) { + DRM_ERROR("failed to reserve %s registers\n", "cpr"); + return -ENOMEM; + } + dev_p->cpr_mmio = ioremap_cache(CPR_BASE_ADDR, 0x100); + if (!dev_p->cpr_mmio) { + DRM_ERROR("failed to ioremap %s registers\n", "CPR"); + release_mem_region(CPR_BASE_ADDR, 100); + return -ENOMEM; + } + if (IS_ERR(dev_p->msscam_mmio)) { + DRM_ERROR("failed to map MSSCAM registers\n"); + iounmap(dev_p->lcd_mmio); + iounmap(dev_p->mipi_mmio); + return -ENOMEM; + } + + + +#define KMB_CLOCKS +#ifdef KMB_CLOCKS /* Enable display clocks*/ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); if (IS_ERR(clk_lcd)) { DRM_ERROR("clk_get() failed clk_lcd\n"); goto setup_fail; } - clk_mipi = clk_get(&pdev->dev, "clk_mipi"); if (IS_ERR(clk_mipi)) { DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } + clk_pll0out0 = clk_get(&pdev->dev, "clk_pll0_out0"); + if (IS_ERR(clk_pll0out0)) + DRM_ERROR("clk_get() failed clk_pll0_out0\n"); + + if (clk_pll0out0) + DRM_INFO("Get clk_pll0out0 = %ld\n", + clk_get_rate(clk_pll0out0)); clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); if (IS_ERR(clk_mipi_ecfg)) { @@ -204,8 +233,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } - ret = kmb_display_clk_enable(); - +#ifdef LCD_TEST /* Set LCD clock to 200 Mhz*/ DRM_INFO("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); ret = clk_set_rate(clk_lcd, KMB_LCD_DEFAULT_CLK); @@ -216,10 +244,11 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n", KMB_LCD_DEFAULT_CLK/1000000, ret); DRM_INFO("Get clk_lcd after set = %ld\n", clk_get_rate(clk_lcd)); - +#endif /* Set MIPI clock to 24 Mhz*/ DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); + DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_mipi to %d\n", KMB_MIPI_DEFAULT_CLK); @@ -230,10 +259,10 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); clk = clk_get_rate(clk_mipi_ecfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { /* Set MIPI_ECFG clock to 24 Mhz*/ DRM_INFO("Get clk_mipi_ecfg before set = %ld\n", clk); - ret = clk_set_rate(clk_mipi_ecfg, KMB_MIPI_DEFAULT_CLK); + ret = clk_set_rate(clk_mipi_ecfg, KMB_MIPI_DEFAULT_CFG_CLK); clk = clk_get_rate(clk_mipi_ecfg); if (clk != KMB_MIPI_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_mipi_ecfg to %d\n", @@ -242,27 +271,29 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) } DRM_INFO("Setting MIPI_ECFG clock tp %d Mhz ret = %d\n", KMB_MIPI_DEFAULT_CLK/1000000, ret); - DRM_INFO("Get clk_mipi_ecfg after set = %ld\n", clk); } clk = clk_get_rate(clk_mipi_cfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { /* Set MIPI_CFG clock to 24 Mhz*/ DRM_INFO("Get clk_mipi_cfg before set = %ld\n", clk); ret = clk_set_rate(clk_mipi_cfg, 24000000); clk = clk_get_rate(clk_mipi_cfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { DRM_ERROR("failed to set to clk_mipi_cfg to %d\n", - KMB_MIPI_DEFAULT_CLK); + KMB_MIPI_DEFAULT_CFG_CLK); goto setup_fail; } DRM_INFO("Setting MIPI_CFG clock tp 24Mhz ret = %d\n", ret); DRM_INFO("Get clk_mipi_cfg after set = %ld\n", clk); } + ret = kmb_display_clk_enable(); + /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ - kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0xfff); - kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xfff); + kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); + kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); +#endif //KMB_CLOCKS #ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - @@ -312,6 +343,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } + /* Initialize MIPI DSI */ ret = kmb_dsi_init(drm, adv_bridge); if (ret) { @@ -340,9 +372,17 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) return ret; } +int kmb_atomic_helper_check(struct drm_device *dev, + struct drm_atomic_state *state) +{ + if (!state) + return 0; + return drm_atomic_helper_check(dev, state); +} + static const struct drm_mode_config_funcs kmb_mode_config_funcs = { .fb_create = drm_gem_fb_create, - .atomic_check = drm_atomic_helper_check, + .atomic_check = kmb_atomic_helper_check, .atomic_commit = drm_atomic_helper_commit, }; @@ -503,13 +543,14 @@ static int kmb_probe(struct platform_device *pdev) * afterwards and the bridge can be successfully attached. */ adv_bridge = kmb_dsi_host_bridge_init(dev); +#ifndef FCCTEST if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) return -EPROBE_DEFER; else if (IS_ERR(adv_bridge)) { DRM_ERROR("probe failed to initialize DSI host bridge\n"); return PTR_ERR(adv_bridge); } - +#endif /* Create DRM device */ drm = drm_dev_alloc(&kmb_driver, dev); if (IS_ERR(drm)) @@ -534,13 +575,6 @@ static int kmb_probe(struct platform_device *pdev) /* Set the CRTC's port so that the encoder component can find it */ lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); - - ret = drm_vblank_init(drm, drm->mode_config.num_crtc); - if (ret < 0) { - DRM_ERROR("failed to initialize vblank\n"); - goto err_vblank; - } - drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm); @@ -550,13 +584,13 @@ static int kmb_probe(struct platform_device *pdev) if (ret) goto err_register; - drm_fbdev_generic_setup(drm, 32); - +#ifndef FCCTEST +// drm_fbdev_generic_setup(drm, 32); +#endif return 0; err_register: drm_kms_helper_poll_fini(drm); -err_vblank: pm_runtime_disable(drm->dev); err_free: drm_mode_config_cleanup(drm); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 1511cd1..58bb967 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -28,16 +28,19 @@ #include "kmb_regs.h" +/*#define FCCTEST*/ #define KMB_MAX_WIDTH 1920 /*max width in pixels */ #define KMB_MAX_HEIGHT 1080 /*max height in pixels */ -#define KMB_LCD_DEFAULT_CLK 24000000 +#define KMB_LCD_DEFAULT_CLK 250000000 #define KMB_MIPI_DEFAULT_CLK 24000000 +#define KMB_MIPI_DEFAULT_CFG_CLK 24000000 struct kmb_drm_private { struct drm_device drm; void __iomem *lcd_mmio; void __iomem *mipi_mmio; void __iomem *msscam_mmio; + void __iomem *cpr_mmio; unsigned char n_layers; struct clk *clk; struct drm_crtc crtc; @@ -88,12 +91,23 @@ static inline void kmb_write_bits(struct kmb_drm_private *lcd, reg_val |= (value << offset); writel(reg_val, lcd->mmio + reg); } +static inline void kmb_write(unsigned int reg, u32 value) +{ + writel(value, reg); +} + +static inline u32 kmb_read(unsigned int reg) +{ + return readl(reg); +} #endif static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 value) { +#ifdef LCD_TEST writel(value, (dev_p->lcd_mmio + reg)); +#endif } static inline void kmb_write_mipi(struct kmb_drm_private *dev_p, @@ -124,23 +138,30 @@ static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p, static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) { +#ifdef LCD_TEST return readl(dev_p->lcd_mmio + reg); +#endif + return 0; } static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { +#ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg); kmb_write_lcd(dev_p, reg, (reg_val | mask)); +#endif } static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p, unsigned int reg, u32 mask) { +#ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg); kmb_write_lcd(dev_p, reg, (reg_val & (~mask))); +#endif } static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 40fe552..5f7683e 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -35,22 +35,32 @@ #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/gpio/consumer.h> +#include <linux/delay.h> #include "kmb_drv.h" #include "kmb_regs.h" #include "kmb_dsi.h" +#include <linux/fs.h> +#include <linux/buffer_head.h> -#define IMG_WIDTH_PX 1920 -#define IMG_HEIGHT_LINES 1080 +static int hw_initialized; +#define IMAGE_PATH "/home/root/1280x720.pnm" +#define MIPI_TX_TEST_PATTERN_GENERATION + +#define IMG_HEIGHT_LINES 720 +#define IMG_WIDTH_PX 1280 #define LCD_BYTESPP 1 /*MIPI TX CFG*/ -#define MIPI_TX_ACTIVE_LANES 4 -#define MIPI_TX_LANE_DATA_RATE_MBPS 888 +#define MIPI_TX_ACTIVE_LANES 2 +//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 +#define MIPI_TX_LANE_DATA_RATE_MBPS 891 +//#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 #define MIPI_TX_CFG_CLK_KHZ 24000 /*DPHY Tx test codes*/ #define TEST_CODE_FSM_CONTROL 0x03 +#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C #define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E #define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F #define TEST_CODE_PLL_VCO_CTRL 0x12 @@ -64,6 +74,7 @@ #define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 #define PLL_N_OVR_EN (1 << 4) #define PLL_M_OVR_EN (1 << 5) +#define TEST_CODE_VOD_LEVEL 0x24 #define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C #define TEST_CODE_PLL_LOCK_DETECTOR 0x1D #define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 @@ -79,6 +90,7 @@ #define PLL_M_MAX 623 #define PLL_FVCO_MAX 1250 +#define TIMEOUT 600 static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device; @@ -91,8 +103,9 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, .data_type = DSI_LP_DT_PPS_RGB888_24B, - .data_mode = MIPI_DATA_MODE1, - .dma_packed = 0 + //.data_mode = MIPI_DATA_MODE1, + .data_mode = MIPI_DATA_MODE0, + .dma_packed = 1 }; struct mipi_tx_frame_cfg mipitx_frame0_cfg = { @@ -101,11 +114,11 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .sections[2] = NULL, .sections[3] = NULL, .vsync_width = 5, - .v_backporch = 36, - .v_frontporch = 4, - .hsync_width = 44, - .h_backporch = 148, - .h_frontporch = 88 + .v_backporch = 20, + .v_frontporch = 5, + .hsync_width = 40, + .h_backporch = 220, + .h_frontporch = 110, }; struct mipi_tx_dsi_cfg mipitx_dsi_cfg = { @@ -128,7 +141,8 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS, .ref_clk_khz = MIPI_TX_REF_CLK_KHZ, .cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ, - .data_if = MIPI_IF_PARALLEL, +// .data_if = MIPI_IF_PARALLEL, + .data_if = MIPI_IF_DMA, .tx_ctrl_cfg = { .frames[0] = &mipitx_frame0_cfg, .frames[1] = NULL, @@ -138,16 +152,20 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .line_sync_pkt_en = 0, .line_counter_active = 0, .frame_counter_active = 0, + .tx_always_use_hact = 1, + .tx_hact_wait_stop = 1, } }; -typedef struct{ +u8 *iBuf; + +struct mipi_hs_freq_range_cfg { uint16_t default_bit_rate_mbps; uint8_t hsfreqrange_code; -} mipi_hs_freq_range_cfg; +}; -static mipi_hs_freq_range_cfg +static struct mipi_hs_freq_range_cfg mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = { {.default_bit_rate_mbps = 80, .hsfreqrange_code = 0x00}, {.default_bit_rate_mbps = 90, .hsfreqrange_code = 0x10}, @@ -230,8 +248,8 @@ static int kmb_dsi_get_modes(struct drm_connector *connector) int num_modes = 0; num_modes = drm_add_modes_noedid(connector, - connector->dev->mode_config.max_width, - connector->dev->mode_config.max_height); + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); return num_modes; } @@ -264,6 +282,7 @@ drm_connector_helper_funcs kmb_dsi_connector_helper_funcs = { static const struct drm_connector_funcs kmb_dsi_connector_funcs = { .destroy = kmb_dsi_connector_destroy, .fill_modes = drm_helper_probe_single_connector_modes, + .reset = drm_atomic_helper_connector_reset, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, }; @@ -293,10 +312,11 @@ static const struct mipi_dsi_host_ops kmb_dsi_host_ops = { }; static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, - struct kmb_dsi *kmb_dsi) + struct kmb_dsi *kmb_dsi) { struct kmb_dsi_host *host; + DRM_INFO("%s : %d\n", __func__, __LINE__); host = kzalloc(sizeof(*host), GFP_KERNEL); if (!host) return NULL; @@ -336,7 +356,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) dsi_host->dev = dev; mipi_dsi_host_register(dsi_host); } - +#ifndef FCCTEST /* find ADV7535 node and initialize it */ DRM_INFO("trying to get bridge info %pOF\n", dev->of_node); encoder_node = of_parse_phandle(dev->of_node, "encoder-slave", 0); @@ -353,7 +373,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) DRM_INFO("wait for external bridge driver DT\n"); return ERR_PTR(-EPROBE_DEFER); } - +#endif return bridge; } @@ -363,7 +383,7 @@ void dsi_host_unregister(void) } u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, - struct mipi_data_type_params *params) + struct mipi_data_type_params *params) { struct mipi_data_type_params data_type_parameters; @@ -481,17 +501,18 @@ static u32 compute_unpacked_bytes(u32 wc, u8 bits_per_pclk) } static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_id, - u8 section, u32 height_lines, - u32 unpacked_bytes, struct mipi_tx_frame_sect_phcfg *ph_cfg) + u8 frame_id, + u8 section, u32 height_lines, + u32 unpacked_bytes, + struct mipi_tx_frame_sect_phcfg *ph_cfg) { u32 cfg = 0; u32 ctrl_no = MIPI_CTRL6; u32 reg_adr; - /*frame section packet header*/ - /*word count*/ - cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0]*/ + /*frame section packet header */ + /*word count */ + cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0] */ /*data type */ cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) << MIPI_TX_SECT_DT_SHIFT); /* bits [21:16] */ @@ -503,9 +524,9 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ cfg |= MIPI_TX_SECT_DMA_PACKED; DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x\n", - __func__, __LINE__, ctrl_no, frame_id, section, cfg); + __func__, __LINE__, ctrl_no, frame_id, section, cfg); kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); + section)), cfg); /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections *there are 2 registers for unpacked bytes - @@ -514,9 +535,9 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 */ reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) - + (section/2)*4; - kmb_write_bits_mipi(dev_p, reg_adr, (section % 2)*16, 16, - unpacked_bytes); + + (section / 2) * 4; + kmb_write_bits_mipi(dev_p, reg_adr, (section % 2) * 16, 16, + unpacked_bytes); /* line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); @@ -525,9 +546,9 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, } static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, - u8 section, - struct mipi_tx_frame_section_cfg *frame_scfg, - u32 *bits_per_pclk, u32 *wc) + u8 section, + struct mipi_tx_frame_section_cfg *frame_scfg, + u32 *bits_per_pclk, u32 *wc) { u32 ret = 0; u32 unpacked_bytes; @@ -535,8 +556,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, struct mipi_tx_frame_sect_phcfg ph_cfg; ret = mipi_get_datatype_params(frame_scfg->data_type, - frame_scfg->data_mode, - &data_type_parameters); + frame_scfg->data_mode, + &data_type_parameters); if (ret) return ret; /* @@ -544,7 +565,7 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, * (in pixels) set for each data type */ if (frame_scfg->width_pixels % - data_type_parameters.size_constraint_pixels != 0) + data_type_parameters.size_constraint_pixels != 0) return -EINVAL; *wc = compute_wc(frame_scfg->width_pixels, @@ -560,8 +581,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, ph_cfg.vchannel = frame_id; mipi_tx_fg_section_cfg_regs(dev_p, frame_id, section, - frame_scfg->height_lines, - unpacked_bytes, &ph_cfg); + frame_scfg->height_lines, + unpacked_bytes, &ph_cfg); /*caller needs bits_per_clk for additional caluclations */ *bits_per_pclk = data_type_parameters.bits_per_pclk; @@ -569,17 +590,18 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, } static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_gen, struct mipi_tx_frame_timing_cfg *fg_cfg) + u8 frame_gen, + struct mipi_tx_frame_timing_cfg *fg_cfg) { u32 sysclk; /*float ppl_llp_ratio; */ u32 ppl_llp_ratio; u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset; - /*Get system clock for blanking period cnfigurations*/ + /*Get system clock for blanking period cnfigurations */ /*TODO need to get system clock from clock driver */ /* Assume 700 Mhz system clock for now */ - sysclk = 700; + sysclk = 500; /*ppl-pixel packing layer, llp-low level protocol * frame genartor timing parameters are clocked on the system clock @@ -595,43 +617,42 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active); - DRM_INFO("%s : %d\n", __func__, __LINE__); /*vsync width */ /* *there are 2 registers for vsync width -VSA in lines for channels 0-3 *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ - offset = (frame_gen % 2)*16; - reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen/2); + offset = (frame_gen % 2) * 16; + reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->vsync_width); - /*v backporch - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen/2); + /*v backporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_backporch); - /*v frontporch - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen/2); + /*v frontporch - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_frontporch); - /*v active - same register config like vsync width*/ - reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen/2); + /*v active - same register config like vsync width */ + reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_active); /*hsyc width */ reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); + (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); /*h backporch */ reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); + (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); /*h frontporch */ reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); + (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); /*h active */ reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); @@ -649,16 +670,15 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, reg_adr = MIPI_TXm_HS_LLP_H_BACKPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->h_backporch * (fg_cfg->bpp / 8)); - DRM_INFO("%s : %d\n", __func__, __LINE__); /* llp h frontporch */ reg_adr = MIPI_TXm_HS_LLP_H_FRONTPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, - fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); + fg_cfg->h_frontporch * (fg_cfg->bpp / 8)); } static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, - u8 active_lanes, u32 bpp, u32 wc, - u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) + u8 active_lanes, u32 bpp, u32 wc, + u32 lane_rate_mbps, struct mipi_tx_frame_cfg *fg_cfg) { u32 i, fg_num_lines = 0; struct mipi_tx_frame_timing_cfg fg_t_cfg; @@ -688,20 +708,21 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, } static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, - u8 active_lanes, u8 vchannel_id) + u8 active_lanes, u8 vchannel_id) { u32 fifo_size, fifo_rthreshold; u32 ctrl_no = MIPI_CTRL6; - /*clear all mc fifo channel sizes and thresholds*/ + /*clear all mc fifo channel sizes and thresholds */ kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_RTHRESHOLD0, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_RTHRESHOLD1, 0); - fifo_size = (active_lanes > MIPI_D_LANES_PER_DPHY) ? - MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC; + fifo_size = ((active_lanes > MIPI_D_LANES_PER_DPHY) ? + MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : + MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC) - 1; /*MC fifo size for virtual channels 0-3 */ /* *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 @@ -710,21 +731,21 @@ static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, SET_MC_FIFO_CHAN_ALLOC(dev_p, ctrl_no, vchannel_id, fifo_size); /*set threshold to half the fifo size, actual size=size*16 */ - fifo_rthreshold = ((fifo_size + 1) * 8) & BIT_MASK_16; + fifo_rthreshold = ((fifo_size) * 8) & BIT_MASK_16; SET_MC_FIFO_RTHRESHOLD(dev_p, ctrl_no, vchannel_id, fifo_rthreshold); /*enable the MC FIFO channel corresponding to the Virtual Channel */ kmb_set_bit_mipi(dev_p, MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), - vchannel_id); + vchannel_id); } static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, - struct mipi_ctrl_cfg *ctrl_cfg) + struct mipi_ctrl_cfg *ctrl_cfg) { u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6; - /*MIPI_TX_HS_SYNC_CFG*/ + /*MIPI_TX_HS_SYNC_CFG */ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) @@ -754,7 +775,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, sync_cfg |= HACT_WAIT_STOP(fg_en); /* MIPI_TX_HS_CTRL */ - ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + ctrl = HS_CTRL_EN; /* type:DSI,source:LCD */ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) ctrl |= DSI_EOTP_EN; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) @@ -770,32 +791,30 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, #ifdef MIPI_TX_TEST_PATTERN_GENERATION static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, - int tp_sel, u32 stripe_width, u32 color0, u32 color1) + int tp_sel, u32 stripe_width, u32 color0, + u32 color1, u32 ctrl_no) { - u32 ctrl_no = MIPI_CTRL6; - + int val = 0; /* Select test pattern mode on the virtual channel */ - kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), - TP_SEL_VCm(vc, tp_sel)); + val = TP_SEL_VCm(vc, tp_sel); if (tp_sel == MIPI_TX_HS_TP_V_STRIPES || - tp_sel == MIPI_TX_HS_TP_H_STRIPES) { - kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), - TP_STRIPE_WIDTH(stripe_width)); + tp_sel == MIPI_TX_HS_TP_H_STRIPES) { + val |= TP_STRIPE_WIDTH(stripe_width); } /* Configure test pattern colors */ - kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR0, color0); - kmb_write_mipi(dev_p, MIPI_TX_HS_TEST_PAT_COLOR1, color1); + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR0(ctrl_no), color0); + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR1(ctrl_no), color1); /* Enable test pattern generation on the virtual channel */ - kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), - TP_EN_VCm(vc)); + val |= TP_EN_VCm(vc); + kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), val); } #endif static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, - struct mipi_ctrl_cfg *ctrl_cfg) + struct mipi_ctrl_cfg *ctrl_cfg) { u32 ret; u8 active_vchannels = 0; @@ -822,12 +841,13 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, */ for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] - == NULL) + == NULL) continue; ret = mipi_tx_fg_section_cfg(dev_p, frame_id, sect, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], - &bits_per_pclk, &word_count); + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], + &bits_per_pclk, + &word_count); if (ret) return ret; @@ -835,14 +855,13 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, /* set frame specific parameters */ mipi_tx_fg_cfg(dev_p, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + bits_per_pclk, + word_count, ctrl_cfg->lane_rate_mbps, + ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); active_vchannels++; /*connect lcd to mipi */ - kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); /*stop iterating as only one virtual channel shall be used for * LCD connection @@ -852,23 +871,152 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, if (active_vchannels == 0) return -EINVAL; - /*Multi-Channel FIFO Configuration*/ + /*Multi-Channel FIFO Configuration */ mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id); -#ifdef MIPI_TX_TEST_PATTERN_GENERATION - mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0, 0, - 0xffffffff, 0); -#endif - /*Frame Generator Enable */ mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg); return ret; } +int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, + int test_code) +{ + u32 reg_wr_data; + u32 reg_rd_data; + int data; + + reg_wr_data = dphy_sel; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + data = 0; + reg_wr_data = 0; + reg_rd_data = 0; + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == + 1) | ((dphy_sel >> 8 & 0x1) == 1)) + reg_wr_data |= data << 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == + 1) | ((dphy_sel >> 9 & 0x1) == 1)) + reg_wr_data |= data << 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == + 1) | ((dphy_sel >> 10 & 0x1) == 1)) + reg_wr_data |= data << 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == + 1) | ((dphy_sel >> 11 & 0x1) == 1)) + reg_wr_data |= data << 24; + + if ((dphy_sel >> 0 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN0_3, reg_wr_data); + if ((dphy_sel >> 4 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN4_7, reg_wr_data); + if ((dphy_sel >> 8 & 0x3) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN8_9, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = (dphy_sel | dphy_sel << 12); + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = dphy_sel << 12; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + data = test_code >> 8 & 0xf; + reg_wr_data = 0; + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == + 1) | ((dphy_sel >> 8 & 0x1) == 1)) + reg_wr_data |= data << 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == + 1) | ((dphy_sel >> 9 & 0x1) == 1)) + reg_wr_data |= data << 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == + 1) | ((dphy_sel >> 10 & 0x1) == 1)) + reg_wr_data |= data << 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == + 1) | ((dphy_sel >> 11 & 0x1) == 1)) + reg_wr_data |= data << 24; + + if ((dphy_sel >> 0 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN0_3, reg_wr_data); + if ((dphy_sel >> 4 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN4_7, reg_wr_data); + if ((dphy_sel >> 8 & 0x3) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN8_9, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = dphy_sel; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + data = test_code & 0xff; + reg_wr_data = 0; + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == + 1) | ((dphy_sel >> 8 & 0x1) == 1)) + reg_wr_data |= data << 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == + 1) | ((dphy_sel >> 9 & 0x1) == 1)) + reg_wr_data |= data << 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == + 1) | ((dphy_sel >> 10 & 0x1) == 1)) + reg_wr_data |= data << 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == + 1) | ((dphy_sel >> 11 & 0x1) == 1)) + reg_wr_data |= data << 24; + + if ((dphy_sel >> 0 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN0_3, reg_wr_data); + if ((dphy_sel >> 4 & 0xf) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN4_7, reg_wr_data); + if ((dphy_sel >> 8 & 0x3) > 0) + kmb_write_mipi(dev_p, DPHY_TEST_DIN8_9, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = (dphy_sel | dphy_sel << 12); + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = dphy_sel << 12; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + reg_wr_data = 0; + kmb_write_mipi(dev_p, DPHY_TEST_CTRL1, reg_wr_data); + + if ((dphy_sel >> 0 & 0xf) > 0) + reg_rd_data = kmb_read_mipi(dev_p, DPHY_TEST_DOUT0_3); + if ((dphy_sel >> 4 & 0xf) > 0) + reg_rd_data = kmb_read_mipi(dev_p, DPHY_TEST_DOUT4_7); + if ((dphy_sel >> 8 & 0x3) > 0) + reg_rd_data = kmb_read_mipi(dev_p, DPHY_TEST_DOUT8_9); + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) + data = reg_rd_data >> 0; + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) + data = reg_rd_data >> 8; + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) + data = reg_rd_data >> 16; + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) + data = reg_rd_data >> 24; + + return data; + +} + static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 test_code, u32 test_data) + u32 test_code, u32 test_data) { - /*send the test code first */ +#ifdef DEBUG + if (test_code != TEST_CODE_FSM_CONTROL) + DRM_INFO("test_code = %02x, test_data = %08x\n", test_code, + test_data); +#endif + + /* send the test code first */ /* Steps for code: * - set testclk HIGH * - set testdin with test code @@ -876,55 +1024,77 @@ static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, * - set testclk LOW * - set testen LOW */ + + /* Set testclk high */ SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + + /* Set testdin */ SET_TEST_DIN0_3(dev_p, dphy_no, test_code); + + /* Set testen high */ SET_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); + + /* Set testclk low */ CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + + /* Set testen low */ CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); - /*send the test data next */ + /* Send the test data next */ /* Steps for data: * - set testen LOW * - set testclk LOW * - set testdin with data * - set testclk HIGH */ - CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); - CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); - SET_TEST_DIN0_3(dev_p, dphy_no, test_data); - SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + if (test_code) { + /* Set testen low */ + CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); + + /* Set testclk low */ + CLR_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + + /* Set data in testdin */ + kmb_write_mipi(dev_p, + DPHY_TEST_DIN0_3 + ((dphy_no / 0x4) * 0x4), + test_data << ((dphy_no % 4) * 8)); + + /* Set testclk high */ + SET_DPHY_TEST_CTRL1_CLK(dev_p, dphy_no); + } } static inline void set_test_mode_src_osc_freq_target_low_bits(struct kmb_drm_private - *dev_p, u32 dphy_no, u32 freq) + *dev_p, + u32 dphy_no, + u32 freq) { /*typical rise/fall time=166, * refer Table 1207 databook,sr_osc_freq_target[7:0 */ test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); + TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); } static inline void - set_test_mode_slew_rate_calib_en(struct kmb_drm_private *dev_p, - u32 dphy_no) +set_test_mode_slew_rate_calib_en(struct kmb_drm_private *dev_p, u32 dphy_no) { /*do not bypass slew rate calibration algorithm */ - /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range*/ + /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, - (0x03 | (1 << 6))); + (0x03 | (1 << 6))); } static inline void - set_test_mode_src_osc_freq_target_hi_bits(struct kmb_drm_private *dev_p, - u32 dphy_no, u32 freq) +set_test_mode_src_osc_freq_target_hi_bits(struct kmb_drm_private *dev_p, + u32 dphy_no, u32 freq) { u32 data; /*typical rise/fall time=166, refer Table 1207 databook, * sr_osc_freq_target[11:7 */ - data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ + data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); } @@ -961,20 +1131,20 @@ static void mipi_tx_get_vco_params(struct vco_params *vco) } static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 ref_clk_mhz, u32 target_freq_mhz) + u32 ref_clk_mhz, u32 target_freq_mhz) { /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) * n: - valid range [0 15] * N: - N = n + 1 - * -valid range: [1 16] - * -conditions: - (pll_ref_clk / N) >= 2 MHz - * -(pll_ref_clk / N) <= 8 MHz + * -valid range: [1 16] + * -conditions: - (pll_ref_clk / N) >= 2 MHz + * -(pll_ref_clk / N) <= 8 MHz * m: valid range [62 623] * M: - M = m + 2 - * -valid range [64 625] - * -Fvco = (M/N) * pll_ref_clk + * -valid range [64 625] + * -Fvco = (M/N) * pll_ref_clk */ struct vco_params vco_p = { .range = 0, @@ -992,7 +1162,7 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, * multiply by 1000 for precision - * no floating point, add n for rounding */ - div = ((ref_clk_mhz * 1000) + n)/(n+1); + div = ((ref_clk_mhz * 1000) + n) / (n + 1); /*found a valid n parameter */ if ((div < 2000 || div > 8000)) continue; @@ -1003,7 +1173,7 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, */ freq = div * (m + 2); freq /= 1000; - /* trim the potential pll freq to max supported*/ + /* trim the potential pll freq to max supported */ if (freq > PLL_FVCO_MAX) continue; @@ -1024,37 +1194,39 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range - | (1 << 6))); + | (1 << 6))); /*Program m, n pll parameters */ + DRM_INFO("%s : %d m = %d n = %d\n", __func__, __LINE__, best_m, best_n); + /*PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, - (best_n & 0x0f)); + (best_n & 0x0f)); /* m - low nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[4:0] */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, - (best_m & 0x1f)); + (best_m & 0x1f)); /*m -high nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[9:5] */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, - ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH); + ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH); - /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en*/ + /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, - (PLL_N_OVR_EN | PLL_M_OVR_EN)); + (PLL_N_OVR_EN | PLL_M_OVR_EN)); /*Program Charge-Pump parameters */ /*pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ t_freq = target_freq_mhz * vco_p.divider; test_mode_send(dev_p, dphy_no, - TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, - ((t_freq > 1150) ? 0x0C : 0x0B)); + TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, + ((t_freq > 1150) ? 0x0C : 0x0B)); /*pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, - 0x00); + 0x00); /*pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10); @@ -1062,13 +1234,13 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, /*pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10); - /*PLL Lock Configuration */ - - /*pll_th1 -Lock Detector Phase error threshold, - * document gives fixed value + /*pll_th1 -Lock Detector Phase error threshold, document gives fixed + * value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02); + /*PLL Lock Configuration */ + /*pll_th2 - Lock Filter length, document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60); @@ -1082,24 +1254,37 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, } static void dphy_init_sequence(struct kmb_drm_private *dev_p, - struct mipi_ctrl_cfg *cfg, u32 dphy_no, enum dphy_mode mode) + struct mipi_ctrl_cfg *cfg, u32 dphy_no, + int active_lanes, enum dphy_mode mode) { u32 test_code = 0; u32 test_data = 0, val; - int i; + int i = 0; + /* deassert SHUTDOWNZ signal */ + DRM_INFO("%s : %d MIPI_DPHY_STAT0_4_7 = 0x%x)\n", __func__, __LINE__, + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); /*Set D-PHY in shutdown mode */ /*assert RSTZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); - /* assert SHUTDOWNZ signal*/ + /* assert SHUTDOWNZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); + DRM_INFO("%s : %d DPHY_INIT_CTRL0 = 0x%x\n", __func__, __LINE__, val); + /*Init D-PHY_n */ /*Pulse testclear signal to make sure the d-phy configuration starts * from a clean base */ + CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); + ndelay(15); SET_DPHY_TEST_CTRL0(dev_p, dphy_no); - /*TODO may need to add 15ns delay here*/ + /*TODO may need to add 15ns delay here */ + ndelay(15); CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); + val = kmb_read_mipi(dev_p, DPHY_TEST_CTRL0); + DRM_INFO("%s : %d DPHY_TEST_CTRL0 = 0x%x\n", __func__, __LINE__, val); + ndelay(15); /*Set mastermacro bit - Master or slave mode */ test_code = TEST_CODE_MULTIPLE_PHY_CTRL; @@ -1111,17 +1296,17 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, /*send the test code and data */ test_mode_send(dev_p, dphy_no, test_code, test_data); - /*Set the lane data rate */ for (i = 0; i < MIPI_DPHY_DEFAULT_BIT_RATES; i++) { if (mipi_hs_freq_range[i].default_bit_rate_mbps < cfg->lane_rate_mbps) continue; - /* send the test code and data*/ - /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en*/ - test_mode_send(dev_p, dphy_no, TEST_CODE_HS_FREQ_RANGE_CFG, - (mipi_hs_freq_range[i].hsfreqrange_code - & 0x7f) | (1 << 7)); + /* send the test code and data */ + /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ + test_code = TEST_CODE_HS_FREQ_RANGE_CFG; + test_data = + (mipi_hs_freq_range[i].hsfreqrange_code & 0x7f) | (1 << 7); + test_mode_send(dev_p, dphy_no, test_code, test_data); break; } /* @@ -1130,78 +1315,136 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, */ if (cfg->lane_rate_mbps > 1500) { /*bypass slew rate calibration algorithm */ - /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, 0x02); + /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr */ + test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; + test_data = 0x02; + test_mode_send(dev_p, dphy_no, test_code, test_data); - /* disable slew rate calibration*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x00); + /* disable slew rate calibration */ + test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; + test_data = 0x00; + test_mode_send(dev_p, dphy_no, test_code, test_data); } else if (cfg->lane_rate_mbps > 1000) { /*BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON * typical rise/fall times: 166 ps */ /*do not bypass slew rate calibration algorithm */ - set_test_mode_slew_rate_calib_en(dev_p, dphy_no); + /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ + test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; + test_data = (0x03 | (1 << 6)); + test_mode_send(dev_p, dphy_no, test_code, test_data); + +// set_test_mode_slew_rate_calib_en(dev_p, dphy_no); - /* enable slew rate calibration*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x01); + /* enable slew rate calibration */ + test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; + test_data = 0x01; + test_mode_send(dev_p, dphy_no, test_code, test_data); /*set sr_osc_freq_target[6:0] */ - /*typical rise/fall time=166, refer Table 1207 databook*/ - set_test_mode_src_osc_freq_target_low_bits(dev_p, - dphy_no, 0x72f); + /*typical rise/fall time=166, refer Table 1207 databook */ + /*typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[7:0 + */ + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + test_data = (0x72f & 0x7f); + test_mode_send(dev_p, dphy_no, test_code, test_data); /*set sr_osc_freq_target[11:7] */ - set_test_mode_src_osc_freq_target_hi_bits(dev_p, dphy_no, - 0x72f); + /*typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[11:7 + */ + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + /*flag this as high nibble */ + test_data = ((0x72f >> 6) & 0x1f) | (1 << 7); + test_mode_send(dev_p, dphy_no, test_code, test_data); } else { /*lane_rate_mbps <= 1000 Mbps */ /*BitRate: <= 1 Gbps: * - slew rate control ON * - typical rise/fall times: 225 ps */ + /*do not bypass slew rate calibration algorithm */ - set_test_mode_slew_rate_calib_en(dev_p, dphy_no); - /* enable slew rate calibration*/ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL, 0x01); - - /*typical rise/fall time=255, refer Table 1207 databook*/ - set_test_mode_src_osc_freq_target_low_bits(dev_p, - dphy_no, 0x523); + test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; + test_data = (0x03 | (1 << 6)); + test_mode_send(dev_p, dphy_no, test_code, test_data); + + /* enable slew rate calibration */ + test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; + test_data = 0x01; + test_mode_send(dev_p, dphy_no, test_code, test_data); + + /*typical rise/fall time=255, refer Table 1207 databook */ + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + test_data = (0x523 & 0x7f); + test_mode_send(dev_p, dphy_no, test_code, test_data); + /*set sr_osc_freq_target[11:7] */ - set_test_mode_src_osc_freq_target_hi_bits(dev_p, dphy_no, - 0x523); - } + test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; + /*flag this as high nibble */ + test_data = ((0x523 >> 6) & 0x1f) | (1 << 7); + test_mode_send(dev_p, dphy_no, test_code, test_data); + } /*Set cfgclkfreqrange */ - val = (((cfg->cfg_clk_khz/1000) - 17) * 4) & 0x3f; + val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; SET_DPHY_FREQ_CTRL0_3(dev_p, dphy_no, val); + val = kmb_read_mipi(dev_p, DPHY_FREQ_CTRL0_3 + 4); /*Enable config clk for the corresponding d-phy */ kmb_set_bit_mipi(dev_p, DPHY_CFG_CLK_EN, dphy_no); - + val = kmb_read_mipi(dev_p, DPHY_CFG_CLK_EN); /* PLL setup */ if (mode == MIPI_DPHY_MASTER) { /*Set PLL regulator in bypass */ - test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_ANALOG_PROG, 0x01); + test_code = TEST_CODE_PLL_ANALOG_PROG; + test_data = 0x01; + test_mode_send(dev_p, dphy_no, test_code, test_data); /* PLL Parameters Setup */ - mipi_tx_pll_setup(dev_p, dphy_no, cfg->ref_clk_khz/1000, - cfg->lane_rate_mbps/2); + mipi_tx_pll_setup(dev_p, dphy_no, cfg->ref_clk_khz / 1000, + cfg->lane_rate_mbps / 2); /*Set clksel */ - kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, PLL_CLKSEL_0, 2, - 0x01); + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, PLL_CLKSEL_0, + 2, 0x01); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1); /*Set pll_shadow_control */ kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL1, PLL_SHADOW_CTRL); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1); } +#define MIPI_TX_FORCE_VOD +#ifdef MIPI_TX_FORCE_VOD +#define MIPI_TX_VOD_LVL 450 +#define TEST_CODE_BANDGAP 0x24 + /* Set bandgap/VOD level */ + switch (MIPI_TX_VOD_LVL) { + case 200: + test_data = 0x00; + break; + case 300: + test_data = 0x20; + break; + case 350: + test_data = 0x40; + break; + case 450: + test_data = 0x60; + break; + case 400: + default: + test_data = 0x70; + break; + } + test_mode_send(dev_p, dphy_no, TEST_CODE_BANDGAP, test_data); +#endif /*Send NORMAL OPERATION test code */ - test_mode_send(dev_p, dphy_no, 0x00, 0x00); + test_code = 0x0; + test_data = 0x0; + test_mode_send(dev_p, dphy_no, test_code, test_data); /* Configure BASEDIR for data lanes * NOTE: basedir only applies to LANE_0 of each D-PHY. @@ -1210,84 +1453,123 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, * bits[5:0] - BaseDir: 1 = Rx * bits[9:6] - BaseDir: 0 = Tx */ - kmb_clr_bit_mipi(dev_p, DPHY_INIT_CTRL2, dphy_no); + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL2, 0, 9, 0x03f); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2); + ndelay(15); /* Enable CLOCK LANE - */ /*clock lane should be enabled regardless of the direction set for * the D-PHY (Rx/Tx) */ - kmb_clr_bit_mipi(dev_p, DPHY_INIT_CTRL2, 12 + dphy_no); + kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL2, 12 + dphy_no); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2); /* enable DATA LANES */ kmb_write_bits_mipi(dev_p, DPHY_ENABLE, dphy_no * 2, 2, - ((1 << cfg->active_lanes) - 1)); + ((1 << active_lanes) - 1)); + val = kmb_read_mipi(dev_p, DPHY_ENABLE); + ndelay(15); /*Take D-PHY out of shutdown mode */ - /* deassert SHUTDOWNZ signal*/ + /* deassert SHUTDOWNZ signal */ SET_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); + ndelay(15); + /*deassert RSTZ signal */ SET_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); + val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); } static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no, - enum dphy_tx_fsm fsm_state) + enum dphy_tx_fsm fsm_state) { enum dphy_tx_fsm val = DPHY_TX_POWERDWN; int i = 0; + int status = 1; do { test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); /*TODO-need to add a time out and return failure */ - val = GET_TEST_DOUT0_3(dev_p, dphy_no); + val = GET_TEST_DOUT4_7(dev_p, dphy_no); i++; - if (i > 50000) { - DRM_INFO("%s: timing out\n", __func__); + if (i > TIMEOUT) { + status = 0; + DRM_INFO("%s: timing out fsm_state = %x GET_TEST_DOUT4_7 = %x", + __func__, fsm_state, kmb_read_mipi(dev_p, + DPHY_TEST_DOUT4_7)); break; } } while (val != fsm_state); + DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val); + + DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val); + DRM_INFO("********** DPHY %d WAIT_FSM %s **********\n", + dphy_no, status ? "SUCCESS" : "FAILED"); } static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 active_lanes) + u32 active_lanes) { u32 stopstatedata = 0; u32 data_lanes = (1 << active_lanes) - 1; - int i = 0; + int i = 0, val; + int status = 1; + + DRM_INFO("%s : %d dphy = %d active_lanes=%d data_lanes=%d\n", + __func__, __LINE__, dphy_no, active_lanes, data_lanes); do { - stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no); - /*TODO-need to add a time out and return failure */ + val = kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7); + stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no) & data_lanes; i++; - if (i > 50000) { - DRM_INFO("%s: timing out", __func__); + if (i > TIMEOUT) { + status = 0; + DRM_INFO("!WAIT_INIT_DONE: TIMING OUT! (err_stat=%d)n", + kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7)); break; } + udelay(1); } while (stopstatedata != data_lanes); + DRM_INFO("********** DPHY %d INIT - %s **********\n", + dphy_no, status ? "SUCCESS" : "FAILED"); + return 0; } static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) { int i = 0; + int status = 1; + do { ; /*TODO-need to add a time out and return failure */ i++; - if (i > 50000) { - DRM_INFO("wait_pll_lock: timing out\n"); + udelay(1); + if (i > TIMEOUT) { + status = 0; + DRM_INFO("%s: timing out", __func__); + DRM_INFO("%s : PLL_LOCK = 0x%x\n", __func__, + kmb_read_mipi(dev_p, DPHY_PLL_LOCK)); break; } + } while (!GET_PLL_LOCK(dev_p, dphy_no)); + DRM_INFO("********** PLL Locked for DPHY %d - %s **********\n", + dphy_no, status ? "SUCCESS" : "FAILED"); return 0; } static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, - struct mipi_ctrl_cfg *cfg) + struct mipi_ctrl_cfg *cfg) { u32 dphy_no = MIPI_DPHY6; + DRM_INFO("%s : %d active_lanes=%d lane_rate=%d\n", + __func__, __LINE__, cfg->active_lanes, + MIPI_TX_LANE_DATA_RATE_MBPS); /*multiple D-PHYs needed */ if (cfg->active_lanes > MIPI_DPHY_D_LANES) { /* @@ -1306,62 +1588,32 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, *f. poll for PHY1 stopstate */ /*PHY #N+1 ('slave') */ - dphy_init_sequence(dev_p, cfg, dphy_no + 1, MIPI_DPHY_SLAVE); + dphy_init_sequence(dev_p, cfg, dphy_no + 1, + (cfg->active_lanes - MIPI_DPHY_D_LANES), + MIPI_DPHY_SLAVE); dphy_wait_fsm(dev_p, dphy_no + 1, DPHY_TX_LOCK); - /*PHY #N master*/ - dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_MASTER); + /*PHY #N master */ + dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_D_LANES, + MIPI_DPHY_MASTER); /* wait for DPHY init to complete */ wait_init_done(dev_p, dphy_no, MIPI_DPHY_D_LANES); wait_init_done(dev_p, dphy_no + 1, - cfg->active_lanes - MIPI_DPHY_D_LANES); + cfg->active_lanes - MIPI_DPHY_D_LANES); wait_pll_lock(dev_p, dphy_no); wait_pll_lock(dev_p, dphy_no + 1); - } else { /* Single DPHY */ - dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_MASTER); + udelay(1000); + dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); + } else { /* Single DPHY */ + dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes, + MIPI_DPHY_MASTER); + dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); wait_init_done(dev_p, dphy_no, cfg->active_lanes); wait_pll_lock(dev_p, dphy_no); } - return 0; -} - -static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, - union mipi_irq_cfg *cfg, - struct mipi_tx_ctrl_cfg *tx_ctrl_cfg) -{ - unsigned long irqflags; - uint8_t vc; - - /* clear all interrupts first */ - /*local interrupts */ - SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); - /*global interrupts */ - SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ); - SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); - SET_MIPI_CTRL_IRQ_CLEAR1(dev_p, MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); - - /*enable interrupts */ - spin_lock_irqsave(&dev_p->irq_lock, irqflags); - for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) { - if (tx_ctrl_cfg->frames[vc] == NULL) - continue; - /*enable FRAME_DONE interrupt if VC is configured */ - SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, - MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc); - break; /*only one vc for LCD interface */ - } - /*enable user enabled interrupts */ - if (cfg->irq_cfg.dphy_error) - SET_MIPI_CTRL_IRQ_ENABLE0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); - if (cfg->irq_cfg.line_compare) - SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, - MIPI_TX_HS_IRQ_LINE_COMPARE); - if (cfg->irq_cfg.ctrl_error) - SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR); - - spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); + return 0; } void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) @@ -1377,7 +1629,7 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) if (irq_ctrl_stat_0 & MIPI_DPHY_ERR_MASK) { if (irq_ctrl_stat_0 & ((1 << (MIPI_DPHY6 + 1)))) SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, - MIPI_DPHY_ERR_IRQ); + MIPI_DPHY_ERR_IRQ); } else if (irq_ctrl_stat_0 & MIPI_HS_IRQ_MASK) { hs_stat = GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6); hs_enable = GET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6); @@ -1385,9 +1637,9 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) /*look for errors */ if (hs_stat & MIPI_TX_HS_IRQ_ERROR) { CLR_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, - (hs_stat & MIPI_TX_HS_IRQ_ERROR) | - MIPI_TX_HS_IRQ_DMA_DONE | - MIPI_TX_HS_IRQ_DMA_IDLE); + (hs_stat & MIPI_TX_HS_IRQ_ERROR) | + MIPI_TX_HS_IRQ_DMA_DONE | + MIPI_TX_HS_IRQ_DMA_IDLE); } /* clear local, then global */ SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, hs_stat); @@ -1396,6 +1648,152 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) } +void dma_transfer(struct kmb_drm_private *dev_p, int mipi_number, + u64 dma_start_address, int data_length) +{ + u64 dma_cfg_adr_offset; + u64 dma_start_adr_offset; + u64 dma_length_adr_offset; + u32 reg_wr_data; + int axi_burst_length; + int mipi_fifo_flush; + int dma_pipelined_axi_en; + int dma_en; + int dma_autorestart_mode_0; + int tx_rx; + + DRM_INFO("%s: starting a new DMA transfer for mipi %d ", __func__, + mipi_number); + + if (mipi_number < 6) + tx_rx = 0; + else + tx_rx = 1; + + dma_cfg_adr_offset = + MIPI_TX_HS_DMA_CFG + HS_OFFSET(mipi_number); + dma_start_adr_offset = + MIPI_TX_HS_DMA_START_ADR_CHAN0 + HS_OFFSET(mipi_number); + dma_length_adr_offset = + MIPI_TX_HS_DMA_LEN_CHAN0 + HS_OFFSET(mipi_number); + + reg_wr_data = 0; + reg_wr_data = dma_start_address; + kmb_write_mipi(dev_p, dma_start_adr_offset, reg_wr_data); + + reg_wr_data = 0; + reg_wr_data = data_length; + kmb_write_mipi(dev_p, dma_length_adr_offset, reg_wr_data); + + axi_burst_length = 16; + mipi_fifo_flush = 0; + dma_pipelined_axi_en = 1; + dma_en = 1; + dma_autorestart_mode_0 = 0; + + reg_wr_data = 0; + reg_wr_data = + ((axi_burst_length & 0x1ffff) << 0 | (mipi_fifo_flush & 0xf) << 9 | + (dma_pipelined_axi_en & 0x1) << 13 | (dma_en & 0xf) << 16 | + (dma_autorestart_mode_0 & 0x3) << 24); + + kmb_write_mipi(dev_p, dma_cfg_adr_offset, reg_wr_data); +} + +/** + * Reads specified number of bytes from the file. + * + * @param file - file structure. + * @param offset - offset in the file. + * @param addr - address of the buffer. + * @param count - size of the buffer . + * + * @return 0 if success or error code. + */ +int kmb_kernel_read(struct file *file, loff_t offset, + char *addr, unsigned long count) +{ + char __user *buf = (char __user *)addr; + ssize_t ret; + + if (!(file->f_mode & FMODE_READ)) + return -EBADF; + + ret = kernel_read(file, buf, count, &offset); + + return ret; +} + +int kmb_dsi_hw_init(struct drm_device *dev) +{ + struct kmb_drm_private *dev_p = dev->dev_private; + int i; + + if (hw_initialized) + return 0; + udelay(1000); + kmb_write_mipi(dev_p, DPHY_ENABLE, 0); + kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0); + kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0); + kmb_write_mipi(dev_p, DPHY_INIT_CTRL2, 0); + + /* initialize mipi controller */ + mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); + /* irq initialization */ + //mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + /*d-phy initialization */ + mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); +#ifdef MIPI_TX_TEST_PATTERN_GENERATION + for (i = MIPI_CTRL6; i < MIPI_CTRL6 + 1; i++) { + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, + 0x05, 0xffffff, 0xff00, i); + } + DRM_INFO("%s : %d MIPI_TXm_HS_CTRL = 0x%x\n", __func__, + __LINE__, kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6))); +#else + dma_data_length = image_height * image_width * unpacked_bytes; + file = filp_open(IMAGE_PATH, O_RDWR, 0); + if (IS_ERR(file)) { + DRM_ERROR("filp_open failed\n"); + return -EBADF; + } + + file_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (!file_buf) { + DRM_ERROR("file_buf alloc failed\n"); + return -ENOMEM; + } + + i_size = i_size_read(file_inode(file)); + while (offset < i_size) { + + file_buf_len = kmb_kernel_read(file, offset, + file_buf, PAGE_SIZE); + if (file_buf_len < 0) { + rc = file_buf_len; + break; + } + if (file_buf_len == 0) + break; + offset += file_buf_len; + count++; + dma_tx_start_address = file_buf; + dma_transfer(dev_p, MIPI_CTRL6, dma_tx_start_address, + PAGE_SIZE); + + } + DRM_INFO("count = %d\n", count); + kfree(file_buf); + filp_close(file, NULL); + +#endif //MIPI_TX_TEST_PATTERN_GENERATION + + hw_initialized = true; + DRM_INFO("%s : %d mipi hw_initialized = %d\n", __func__, __LINE__, + hw_initialized); + return 0; +} + int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) { struct kmb_dsi *kmb_dsi; @@ -1403,7 +1801,6 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) struct kmb_connector *kmb_connector; struct drm_connector *connector; struct kmb_dsi_host *host; - struct kmb_drm_private *dev_p = dev->dev_private; int ret = 0; kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); @@ -1412,6 +1809,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return -ENOMEM; } + DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); if (!kmb_connector) { kfree(kmb_dsi); @@ -1424,7 +1822,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) host = kmb_dsi_host_init(dev, kmb_dsi); if (!host) { DRM_ERROR("Faile to allocate host\n"); -// drm_encoder_cleanup(encoder); +// drm_encoder_cleanup(encoder); kfree(kmb_dsi); kfree(kmb_connector); return -ENOMEM; @@ -1435,34 +1833,34 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) encoder->possible_crtcs = 1; encoder->possible_clones = 0; drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, - "MIPI-DSI"); + "MIPI-DSI"); drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, - DRM_MODE_CONNECTOR_DSI); + DRM_MODE_CONNECTOR_DSI); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, - __LINE__, connector->name, encoder->name); + __LINE__, connector->name, encoder->name); + DRM_INFO("%s : %d\n", __func__, __LINE__); ret = drm_connector_attach_encoder(connector, encoder); /* Link drm_bridge to encoder */ +#ifndef FCCTEST ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) { DRM_ERROR("failed to attach bridge to MIPI\n"); drm_encoder_cleanup(encoder); return ret; } - +#endif +#ifndef FCCTEST DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); - /* initialize mipi controller */ - mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); - - /*d-phy initialization */ - mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); +#endif - /* irq initialization */ - mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); +#ifdef FCCTEST + kmb_dsi_hw_init(dev); +#endif return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index ef526b4..d0196a4 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -63,7 +63,6 @@ struct kmb_connector { #define MIPI_DPHY_DEFAULT_BIT_RATES 63 /*DPHY Tx test codes */ -#define TEST_CODE_MULTIPLE_PHY_CTRL 0x03 enum mipi_ctrl_num { MIPI_CTRL0 = 0, @@ -341,6 +340,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); void dsi_host_unregister(void); +int kmb_dsi_hw_init(struct drm_device *dev); #define to_kmb_connector(x) container_of(x, struct kmb_connector, base) #define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index de5ca88..2815ab3 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -133,8 +133,12 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, struct drm_framebuffer *fb; int ret; + fb = state->fb; + if (!fb || !state->crtc) + return 0; + ret = check_pixel_format(plane, fb->format->format); if (ret) return ret; @@ -144,6 +148,38 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, return 0; } +static void kmb_plane_atomic_disable(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct kmb_plane *kmb_plane = to_kmb_plane(plane); + int ctrl = 0; + struct kmb_drm_private *dev_p; + int plane_id; + + dev_p = plane->dev->dev_private; + plane_id = kmb_plane->id; + + switch (plane_id) { + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; + } + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + ~LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(dev_p, LCD_CONTROL, ~ctrl); +} + + unsigned int set_pixel_format(u32 format) { unsigned int val = 0; @@ -257,6 +293,7 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) return val; } +#ifdef LCD_TEST static void config_csc(struct kmb_drm_private *dev_p, int plane_id) { /*YUV to RGB conversion using the fixed matrix csc_coef_lcd */ @@ -274,26 +311,38 @@ static void config_csc(struct kmb_drm_private *dev_p, int plane_id) kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]); kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_CFG(plane_id), LCD_LAYER_CSC_EN); } +#endif static void kmb_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *state) { - struct drm_framebuffer *fb = plane->state->fb; +#ifdef LCD_TEST + struct drm_framebuffer *fb; struct kmb_drm_private *dev_p; dma_addr_t addr; unsigned int width; unsigned int height; unsigned int dma_len; - struct kmb_plane *kmb_plane = to_kmb_plane(plane); + struct kmb_plane *kmb_plane; unsigned int dma_cfg; unsigned int ctrl = 0, val = 0, out_format = 0; unsigned int src_w, src_h, crtc_x, crtc_y; - unsigned char plane_id = kmb_plane->id; - int num_planes = fb->format->num_planes; + unsigned char plane_id; + int num_planes; + + if (!plane || !plane->state || !state) + return; + fb = plane->state->fb; if (!fb) return; + num_planes = fb->format->num_planes; + kmb_plane = to_kmb_plane(plane); + plane_id = kmb_plane->id; + + + dev_p = plane->dev->dev_private; src_w = plane->state->src_w >> 16; @@ -425,11 +474,13 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); +#endif } static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { .atomic_check = kmb_plane_atomic_check, .atomic_update = kmb_plane_atomic_update, + .atomic_disable = kmb_plane_atomic_disable }; void kmb_plane_destroy(struct drm_plane *plane) diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 9ca7851..eb84320 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -29,6 +29,7 @@ #define ENABLE 1 #define DISABLE 0 /*from Data Book section 12.5.8.1 page 4322 */ +#define CPR_BASE_ADDR (0x20810000) #define MIPI_BASE_ADDR (0x20900000) /*from Data Book section 12.11.6.1 page 4972 */ #define LCD_BASE_ADDR (0x20930000) @@ -544,6 +545,9 @@ #define SET_MC_FIFO_RTHRESHOLD(dev, ctrl, vc, th) \ kmb_write_bits_mipi(dev, MIPI_TXm_HS_MC_FIFO_RTHRESHOLDn(ctrl, vc/2), \ (vc % 2)*16, 16, th) +#define MIPI_TX_HS_DMA_CFG (0x1a8) +#define MIPI_TX_HS_DMA_START_ADR_CHAN0 (0x1ac) +#define MIPI_TX_HS_DMA_LEN_CHAN0 (0x1b4) /* MIPI IRQ */ #define MIPI_CTRL_IRQ_STATUS0 (0x00) @@ -572,6 +576,7 @@ #define MIPI_CTRL_IRQ_CLEAR1 (0x014) #define SET_MIPI_CTRL_IRQ_CLEAR1(dev, M, N) \ kmb_set_bit_mipi(dev, MIPI_CTRL_IRQ_CLEAR1, M+N) +#define MIPI_CTRL_DIG_LOOPBACK (0x018) #define MIPI_TX_HS_IRQ_STATUS (0x01c) #define MIPI_TX_HS_IRQ_STATUSm(M) (MIPI_TX_HS_IRQ_STATUS + \ HS_OFFSET(M)) @@ -649,12 +654,16 @@ #define MIPI_TX_HS_TEST_PAT_CTRL (0x230) #define MIPI_TXm_HS_TEST_PAT_CTRL(M) \ (MIPI_TX_HS_TEST_PAT_CTRL + HS_OFFSET(M)) -#define TP_EN_VCm(M) ((M) * 0x04) +#define TP_EN_VCm(M) (1 << ((M) * 0x04)) #define TP_SEL_VCm(M, N) \ (N << (((M) * 0x04) + 1)) #define TP_STRIPE_WIDTH(M) ((M) << 16) #define MIPI_TX_HS_TEST_PAT_COLOR0 (0x234) +#define MIPI_TXm_HS_TEST_PAT_COLOR0(M) \ + (MIPI_TX_HS_TEST_PAT_COLOR0 + HS_OFFSET(M)) #define MIPI_TX_HS_TEST_PAT_COLOR1 (0x238) +#define MIPI_TXm_HS_TEST_PAT_COLOR1(M) \ + (MIPI_TX_HS_TEST_PAT_COLOR1 + HS_OFFSET(M)) /* D-PHY regs */ #define DPHY_ENABLE (0x100) @@ -670,15 +679,25 @@ #define CLR_DPHY_INIT_CTRL0(dev, dphy, offset) \ kmb_clr_bit_mipi(dev, DPHY_INIT_CTRL0, (dphy+offset)) #define DPHY_INIT_CTRL2 (0x10c) +#define DPHY_PLL_OBS0 (0x110) +#define DPHY_PLL_OBS1 (0x114) +#define DPHY_PLL_OBS2 (0x118) #define DPHY_FREQ_CTRL0_3 (0x11c) +#define DPHY_FREQ_CTRL4_7 (0x120) #define SET_DPHY_FREQ_CTRL0_3(dev, dphy, val) \ kmb_write_bits_mipi(dev, DPHY_FREQ_CTRL0_3 \ + ((dphy/4)*4), (dphy % 4) * 8, 6, val) +#define DPHY_FORCE_CTRL0 (0x128) +#define DPHY_FORCE_CTRL1 (0x12C) #define MIPI_DPHY_STAT0_3 (0x134) +#define MIPI_DPHY_STAT4_7 (0x138) #define GET_STOPSTATE_DATA(dev, dphy) \ (((kmb_read_mipi(dev, MIPI_DPHY_STAT0_3 + (dphy/4)*4)) \ >> (((dphy % 4)*8)+4)) & 0x03) + +#define MIPI_DPHY_ERR_STAT6_7 (0x14C) + #define DPHY_TEST_CTRL0 (0x154) #define SET_DPHY_TEST_CTRL0(dev, dphy) \ kmb_set_bit_mipi(dev, DPHY_TEST_CTRL0, (dphy)) @@ -700,8 +719,15 @@ 4, ((val) << (((dphy)%4)*8))) #define DPHY_TEST_DOUT0_3 (0x168) #define GET_TEST_DOUT0_3(dev, dphy) \ - (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3 + 4) \ + (kmb_read_mipi(dev, DPHY_TEST_DOUT0_3) \ + >> (((dphy)%4)*8) & 0xff) +#define DPHY_TEST_DOUT4_7 (0x16C) +#define GET_TEST_DOUT4_7(dev, dphy) \ + (kmb_read_mipi(dev, DPHY_TEST_DOUT4_7) \ >> (((dphy)%4)*8) & 0xff) +#define DPHY_TEST_DOUT8_9 (0x170) +#define DPHY_TEST_DIN4_7 (0x160) +#define DPHY_TEST_DIN8_9 (0x164) #define DPHY_PLL_LOCK (0x188) #define GET_PLL_LOCK(dev, dphy) \ (kmb_read_mipi(dev, DPHY_PLL_LOCK) \ @@ -714,6 +740,10 @@ #define MIPI_COMMON (1<<2) #define MIPI_TX0 (1<<9) #define MSS_CAM_RSTN_CTRL (0x14) +#define MSS_CAM_RSTN_SET (0x20) +#define MSS_CAM_RSTN_CLR (0x24) +#define MSSCPU_CPR_CLK_EN (0x0) +#define MSSCPU_CPR_RST_EN (0x10) #define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:52 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:52 -0700 Subject: [Intel-gfx] [PATCH 40/59] drm/kmb: Added LCD_TEST config In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-41-git-send-email-anitha.chrisanthus@intel.com> To run modetest without ADV driver, enable LCD_TEST and FCC_TEST. Also made front porches 0, and some changes in the plane init. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 13 +++---- drivers/gpu/drm/kmb/kmb_drv.c | 6 +-- drivers/gpu/drm/kmb/kmb_drv.h | 3 +- drivers/gpu/drm/kmb/kmb_dsi.c | 85 +++++++++++++++++++++++++++-------------- drivers/gpu/drm/kmb/kmb_plane.c | 15 ++++++-- 5 files changed, 78 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 01ad82e..9275f77 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -100,13 +100,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) struct videomode vm; int vsync_start_offset; int vsync_end_offset; - unsigned int ctrl = 0; #endif /* initialize mipi */ kmb_dsi_hw_init(dev); #ifdef LCD_TEST - vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; - vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; +// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; + vm.vfront_porch = 0; +// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; + vm.vback_porch = 0; vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; @@ -149,12 +150,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10); } /* enable VL1 layer as default */ - ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE; - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_OUTPUT_ENABLED; - kmb_write_lcd(dev->dev_private, LCD_CONTROL, ctrl); - kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE); + kmb_set_bitmask_lcd(dev->dev_private, LCD_CONTROL, LCD_CTRL_ENABLE); #endif /* TBD */ /* set clocks here */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index e9dd879..e2d57ca 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -236,6 +236,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) #endif /* Set MIPI clock to 24 Mhz*/ DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); +//#define MIPI_CLK +#ifdef MIPI_CLK ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) { @@ -243,6 +245,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) KMB_MIPI_DEFAULT_CLK); goto setup_fail; } +#endif DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n", KMB_MIPI_DEFAULT_CLK/1000000, ret); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); @@ -339,8 +342,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } - - DRM_INFO("%s : %d\n", __func__, __LINE__); #ifdef WIP ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); if (ret < 0) { @@ -355,7 +356,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) drm_crtc_cleanup(&dev_p->crtc); #endif setup_fail: - DRM_INFO("%s : %d\n", __func__, __LINE__); of_reserved_mem_device_release(drm->dev); return ret; diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index da1df5c..67ddf7a 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -28,7 +28,8 @@ #include "kmb_regs.h" -/*#define FCCTEST*/ +#define FCCTEST +#define LCD_TEST #define KMB_MAX_WIDTH 1920 /*max width in pixels */ #define KMB_MAX_HEIGHT 1080 /*max height in pixels */ #define KMB_LCD_DEFAULT_CLK 250000000 diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 5f7683e..91c6898 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -44,18 +44,19 @@ static int hw_initialized; #define IMAGE_PATH "/home/root/1280x720.pnm" -#define MIPI_TX_TEST_PATTERN_GENERATION +//#define MIPI_TX_TEST_PATTERN_GENERATION +//#define RTL_TEST +//#define IMG_WIDTH_PX 640 +//#define IMG_HEIGHT_LINES 10 -#define IMG_HEIGHT_LINES 720 -#define IMG_WIDTH_PX 1280 #define LCD_BYTESPP 1 /*MIPI TX CFG*/ -#define MIPI_TX_ACTIVE_LANES 2 //#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 #define MIPI_TX_LANE_DATA_RATE_MBPS 891 //#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 +//#define MIPI_TX_REF_CLK_KHZ 23809 #define MIPI_TX_CFG_CLK_KHZ 24000 /*DPHY Tx test codes*/ @@ -99,6 +100,18 @@ static struct mipi_dsi_device *dsi_device; * these will eventually go to the device tree sections, * and can be used as a refernce later for device tree additions */ +#ifdef RES_1920x1080 +#define IMG_HEIGHT_LINES 1080 +#define IMG_WIDTH_PX 1920 +#define MIPI_TX_ACTIVE_LANES 4 +#endif + +#define RES_1280x720 +#ifdef RES_1280x720 +#define IMG_HEIGHT_LINES 720 +#define IMG_WIDTH_PX 1280 +#define MIPI_TX_ACTIVE_LANES 2 +#endif struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, @@ -108,6 +121,22 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .dma_packed = 1 }; +#ifdef RES_1920x1080 +struct mipi_tx_frame_cfg mipitx_frame0_cfg = { + .sections[0] = &mipi_tx_frame0_sect_cfg, + .sections[1] = NULL, + .sections[2] = NULL, + .sections[3] = NULL, + .vsync_width = 5, + .v_backporch = 36, + .v_frontporch = 4, + .hsync_width = 44, + .h_backporch = 148, + .h_frontporch = 88 +}; +#endif + +#ifdef RES_1280x720 struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .sections[0] = &mipi_tx_frame0_sect_cfg, .sections[1] = NULL, @@ -120,6 +149,7 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .h_backporch = 220, .h_frontporch = 110, }; +#endif struct mipi_tx_dsi_cfg mipitx_dsi_cfg = { .hfp_blank_en = 0, @@ -141,8 +171,7 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .lane_rate_mbps = MIPI_TX_LANE_DATA_RATE_MBPS, .ref_clk_khz = MIPI_TX_REF_CLK_KHZ, .cfg_clk_khz = MIPI_TX_CFG_CLK_KHZ, -// .data_if = MIPI_IF_PARALLEL, - .data_if = MIPI_IF_DMA, + .data_if = MIPI_IF_PARALLEL, .tx_ctrl_cfg = { .frames[0] = &mipitx_frame0_cfg, .frames[1] = NULL, @@ -334,7 +363,6 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) { - struct device_node *encoder_node; struct drm_bridge *bridge; /* Create and register MIPI DSI host */ @@ -613,7 +641,13 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); - /*frame generator number of lines */ + DRM_INFO("%s : %d bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n", + __func__, __LINE__, fg_cfg->bpp, sysclk, + fg_cfg->lane_rate_mbps, fg_cfg->active_lanes); + + DRM_INFO("%s : %d ppl_llp_ratio=%d\n", __func__, __LINE__, + ppl_llp_ratio); + /*frame generator number of lines*/ reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active); @@ -774,8 +808,8 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) sync_cfg |= HACT_WAIT_STOP(fg_en); - /* MIPI_TX_HS_CTRL */ - ctrl = HS_CTRL_EN; /* type:DSI,source:LCD */ + /* MIPI_TX_HS_CTRL*/ + ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) ctrl |= DSI_EOTP_EN; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) @@ -862,6 +896,7 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, active_vchannels++; /*connect lcd to mipi */ + kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); /*stop iterating as only one virtual channel shall be used for * LCD connection @@ -1528,7 +1563,7 @@ static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7)); break; } - udelay(1); +// udelay(1); } while (stopstatedata != data_lanes); DRM_INFO("********** DPHY %d INIT - %s **********\n", @@ -1543,10 +1578,9 @@ static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) int status = 1; do { - ; /*TODO-need to add a time out and return failure */ i++; - udelay(1); + // udelay(1); if (i > TIMEOUT) { status = 0; DRM_INFO("%s: timing out", __func__); @@ -1603,7 +1637,7 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, cfg->active_lanes - MIPI_DPHY_D_LANES); wait_pll_lock(dev_p, dphy_no); wait_pll_lock(dev_p, dphy_no + 1); - udelay(1000); +// udelay(1000); dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); } else { /* Single DPHY */ dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes, @@ -1727,11 +1761,9 @@ int kmb_kernel_read(struct file *file, loff_t offset, int kmb_dsi_hw_init(struct drm_device *dev) { struct kmb_drm_private *dev_p = dev->dev_private; - int i; if (hw_initialized) return 0; - udelay(1000); kmb_write_mipi(dev_p, DPHY_ENABLE, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0); @@ -1739,19 +1771,15 @@ int kmb_dsi_hw_init(struct drm_device *dev) /* initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); - /* irq initialization */ - //mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); /*d-phy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); #ifdef MIPI_TX_TEST_PATTERN_GENERATION - for (i = MIPI_CTRL6; i < MIPI_CTRL6 + 1; i++) { - mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, - 0x05, 0xffffff, 0xff00, i); - } - DRM_INFO("%s : %d MIPI_TXm_HS_CTRL = 0x%x\n", __func__, - __LINE__, kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6))); -#else - dma_data_length = image_height * image_width * unpacked_bytes; + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, 0x15, 0xff, + 0xff00, MIPI_CTRL6); + DRM_INFO("%s : %d IRQ_STATUS = 0x%x\n", __func__, __LINE__, + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); +#elseif MIPI_DMA + dma_data_length = image_height * image_width * unpacked_bytes; file = filp_open(IMAGE_PATH, O_RDWR, 0); if (IS_ERR(file)) { DRM_ERROR("filp_open failed\n"); @@ -1785,7 +1813,6 @@ int kmb_dsi_hw_init(struct drm_device *dev) DRM_INFO("count = %d\n", count); kfree(file_buf); filp_close(file, NULL); - #endif //MIPI_TX_TEST_PATTERN_GENERATION hw_initialized = true; @@ -1854,13 +1881,15 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return ret; } #endif + #ifndef FCCTEST DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); #endif #ifdef FCCTEST +#ifndef LCD_TEST kmb_dsi_hw_init(dev); #endif - +#endif return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 2815ab3..008fd48 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -367,10 +367,14 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]); /*TBD check visible? */ - +/* dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1 | LCD_DMA_LAYER_VSTRIDE_EN; +*/ + dma_cfg = LCD_DMA_LAYER_ENABLE + | LCD_DMA_LAYER_AXI_BURST_1 + | LCD_DMA_LAYER_VSTRIDE_EN; /* disable DMA first */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), @@ -447,10 +451,12 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, break; } - ctrl |= LCD_CTRL_ENABLE; - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; +// ctrl |= LCD_CTRL_ENABLE; +// ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE +// | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; + ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_ONE_SHOT | LCD_CTRL_OUTPUT_ENABLED; /*LCD is connected to MIPI on kmb * Therefore this bit is required for DSI Tx */ @@ -474,6 +480,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); +// kmb_write_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE); #endif } -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:54 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:54 -0700 Subject: [Intel-gfx] [PATCH 42/59] drm/kmb: Update LCD programming to match MIPI In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-43-git-send-email-anitha.chrisanthus@intel.com> Mipi input expects the memory layout to be unpacked with 8 bits per pixel in RGB (BRG) order. If the LCD is not configured properly, corrupted output results, changed dma_unpacked to 0 in mipi FG. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 6 +++--- drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_dsi.c | 27 +++++++++++++++++---------- drivers/gpu/drm/kmb/kmb_dsi.h | 1 + drivers/gpu/drm/kmb/kmb_plane.c | 37 +++++++++++++++++++++++++++---------- drivers/gpu/drm/kmb/kmb_regs.h | 1 + 6 files changed, 50 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index f8b4fde..d9f6199 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -105,16 +105,16 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_dsi_hw_init(dev); #ifdef LCD_TEST // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; - vm.vfront_porch = 0; + vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; - vm.vback_porch = 0; + vm.vback_porch = 2; // vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; vm.vsync_len = 1; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; vm.hback_porch = 0; //vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; - vm.hsync_len = 1; + vm.hsync_len = 7; // vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index c376944..b194139 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -50,6 +50,7 @@ struct kmb_drm_private { spinlock_t irq_lock; int irq_lcd; int irq_mipi; + dma_addr_t fb_addr; }; static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index f06fd92..3b3bb0a 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -45,6 +45,7 @@ static int hw_initialized; #define IMAGE_PATH "/home/root/1280x720.pnm" //#define MIPI_TX_TEST_PATTERN_GENERATION +//#define MIPI_DMA //#define RTL_TEST //#define IMG_WIDTH_PX 640 //#define IMG_HEIGHT_LINES 10 @@ -53,6 +54,7 @@ static int hw_initialized; /*MIPI TX CFG*/ //#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 +//#define MIPI_TX_LANE_DATA_RATE_MBPS 800 #define MIPI_TX_LANE_DATA_RATE_MBPS 891 //#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 @@ -100,14 +102,14 @@ static struct mipi_dsi_device *dsi_device; * these will eventually go to the device tree sections, * and can be used as a refernce later for device tree additions */ -//#define RES_1920x1080 +#define RES_1920x1080 #ifdef RES_1920x1080 #define IMG_HEIGHT_LINES 1080 #define IMG_WIDTH_PX 1920 #define MIPI_TX_ACTIVE_LANES 4 #endif -#define RES_1280x720 +//#define RES_1280x720 #ifdef RES_1280x720 #define IMG_HEIGHT_LINES 720 #define IMG_WIDTH_PX 1280 @@ -117,9 +119,9 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, .data_type = DSI_LP_DT_PPS_RGB888_24B, - //.data_mode = MIPI_DATA_MODE1, - .data_mode = MIPI_DATA_MODE0, - .dma_packed = 1 + .data_mode = MIPI_DATA_MODE1, +// .data_mode = MIPI_DATA_MODE0, + .dma_packed = 0 }; #ifdef RES_1920x1080 @@ -564,12 +566,15 @@ static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, << MIPI_TX_SECT_VC_SHIFT); /* bits [23:22] */ /* data mode */ cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) - << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25] */ - cfg |= MIPI_TX_SECT_DMA_PACKED; - DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x\n", - __func__, __LINE__, ctrl_no, frame_id, section, cfg); + << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25]*/ + if (ph_cfg->dma_packed) + cfg |= MIPI_TX_SECT_DMA_PACKED; + DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n", + __func__, __LINE__, ctrl_no, frame_id, section, cfg, + ph_cfg->dma_packed); kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); + section)), cfg); + /*unpacked bytes */ /*there are 4 frame generators and each fg has 4 sections *there are 2 registers for unpacked bytes - @@ -621,6 +626,7 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, ph_cfg.wc = *wc; ph_cfg.data_mode = frame_scfg->data_mode; ph_cfg.data_type = frame_scfg->data_type; + ph_cfg.dma_packed = frame_scfg->dma_packed; ph_cfg.vchannel = frame_id; mipi_tx_fg_section_cfg_regs(dev_p, frame_id, section, @@ -647,6 +653,7 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, * mipi clock speed in RTL tests */ sysclk = KMB_SYS_CLK_MHZ - 50; +// sysclk = KMB_SYS_CLK_MHZ; /*ppl-pixel packing layer, llp-low level protocol * frame genartor timing parameters are clocked on the system clock diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index d74dc29..ece4ee1 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -282,6 +282,7 @@ struct mipi_tx_frame_sect_phcfg { enum mipi_data_mode data_mode; enum mipi_dsi_data_type data_type; uint8_t vchannel; + uint8_t dma_packed; }; struct mipi_tx_frame_cfg { diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 7aeca07..3cd9b0d 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -116,6 +116,7 @@ static const u32 csc_coef_lcd[] = { -179, 125, -226 }; + static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -264,17 +265,21 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; break; } + DRM_INFO("%s : %d layer format val=%d\n", __func__, __LINE__, val); return val; } unsigned int set_bits_per_pixel(const struct drm_format_info *format) { - int i; u32 bpp = 0; unsigned int val = 0; - for (i = 0; i < format->num_planes; i++) - bpp += 8 * format->cpp[i]; + if (format->num_planes > 1) { + val = LCD_LAYER_8BPP; + return val; + } + + bpp += 8*format->cpp[0]; switch (bpp) { case 8: @@ -290,8 +295,8 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) val = LCD_LAYER_32BPP; break; } - DRM_INFO("%s : %d bpp=0x%x\n", __func__, __LINE__, bpp); - val = LCD_LAYER_24BPP; + + DRM_INFO("%s : %d bpp=%d val=%d\n", __func__, __LINE__, bpp, val); return val; } @@ -347,11 +352,12 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, dev_p = plane->dev->dev_private; - src_w = plane->state->src_w >> 16; + src_w = (plane->state->src_w >> 16); src_h = plane->state->src_h >> 16; crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; + DRM_INFO("src_w=%d src_h=%d\n", src_w, src_h); kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1); kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1); kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); @@ -361,6 +367,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val |= set_bits_per_pixel(fb->format); /*CHECKME Leon drvr sets it to 100 try this for now */ val |= LCD_LAYER_FIFO_100; + val |= LCD_LAYER_BGR_ORDER; kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); /*re-initialize interrupts */ @@ -375,29 +382,33 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, | LCD_DMA_LAYER_VSTRIDE_EN; */ dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN - | LCD_DMA_LAYER_AXI_BURST_16 | LCD_DMA_LAYER_CONT_UPDATE; + | LCD_DMA_LAYER_AXI_BURST_16 | + LCD_DMA_LAYER_CONT_PING_PONG_UPDATE; /* disable DMA first */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), ~LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(dev_p, LCD_FIFO_FLUSH + plane_id*0x400, 1); /* pinpong mode is enabled - at the end of DMA transfer, start new * transfer alternatively using main and shadow register settings. * So update both main and shadow registers */ addr = drm_fb_cma_get_gem_addr(fb, plane->state, 0); + dev_p->fb_addr = addr; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); width = fb->width; height = fb->height; - dma_len = width * height * 1; + dma_len = width * height * fb->format->cpp[0]; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), width); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[0]); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width)); + (width*fb->format->cpp[0])); /*program Cb/Cr for planar formats*/ if (num_planes > 1) { @@ -435,6 +446,9 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* enable DMA */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + DRM_INFO("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", __func__, + __LINE__, dma_cfg, + kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); switch (plane_id) { case LAYER_0: @@ -468,6 +482,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, * from the Myriadx tests */ out_format |= LCD_OUTF_FORMAT_RGB888; +// out_format |= LCD_OUTF_BGR_ORDER; if (val & LCD_LAYER_PLANAR_STORAGE) { /*enable CSC if input is planar and output is RGB */ @@ -479,7 +494,9 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /*leave RGB order,conversion mode and clip mode to default*/ /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; +// out_format |= LCD_OUTF_SYNC_MODE ; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); + // kmb_write_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE); #endif } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 67dd1f4..c80646a 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -370,6 +370,7 @@ #define LCD_OUTF_BGR_ORDER (1 << 5) #define LCD_OUTF_Y_ORDER (1 << 6) #define LCD_OUTF_CRCB_ORDER (1 << 7) +#define LCD_OUTF_SYNC_MODE (1 << 11) #define LCD_OUTF_RGB_CONV_MODE (1 << 14) #define LCD_OUTF_MIPI_RGB_MODE (1 << 18) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:56 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:56 -0700 Subject: [Intel-gfx] [PATCH 44/59] drm/kmb: Mipi settings from input timings In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-45-git-send-email-anitha.chrisanthus@intel.com> Removed hardcoded timings, set timings based on the current mode's input timings. Also calculate and set the lane rate based on the timings. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 9 +++- drivers/gpu/drm/kmb/kmb_dsi.c | 93 +++++++++++++++++++++++------------------- drivers/gpu/drm/kmb/kmb_dsi.h | 2 +- 3 files changed, 61 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index d9f6199..75e78d7 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -102,7 +102,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) int vsync_end_offset; #endif /* initialize mipi */ - kmb_dsi_hw_init(dev); + kmb_dsi_hw_init(dev, m); + DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n", + m->crtc_vsync_start - m->crtc_vdisplay, + m->crtc_vtotal - m->crtc_vsync_end, + m->crtc_vsync_end - m->crtc_vsync_start, + m->crtc_hsync_start - m->crtc_hdisplay, + m->crtc_htotal - m->crtc_hsync_end, + m->crtc_hsync_end - m->crtc_hsync_start); #ifdef LCD_TEST // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 3b3bb0a..3368e97 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -47,19 +47,12 @@ static int hw_initialized; //#define MIPI_TX_TEST_PATTERN_GENERATION //#define MIPI_DMA //#define RTL_TEST -//#define IMG_WIDTH_PX 640 -//#define IMG_HEIGHT_LINES 10 - -#define LCD_BYTESPP 1 /*MIPI TX CFG*/ -//#define MIPI_TX_LANE_DATA_RATE_MBPS 1782 -//#define MIPI_TX_LANE_DATA_RATE_MBPS 800 #define MIPI_TX_LANE_DATA_RATE_MBPS 891 -//#define MIPI_TX_LANE_DATA_RATE_MBPS 80 #define MIPI_TX_REF_CLK_KHZ 24000 -//#define MIPI_TX_REF_CLK_KHZ 23809 #define MIPI_TX_CFG_CLK_KHZ 24000 +#define MIPI_TX_BPP 24 /*DPHY Tx test codes*/ #define TEST_CODE_FSM_CONTROL 0x03 @@ -98,23 +91,12 @@ static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device; /* - * These are added here only temporarily for testing, - * these will eventually go to the device tree sections, - * and can be used as a refernce later for device tree additions + * Default setting is 1080p, 4 lanes. */ -#define RES_1920x1080 -#ifdef RES_1920x1080 #define IMG_HEIGHT_LINES 1080 #define IMG_WIDTH_PX 1920 #define MIPI_TX_ACTIVE_LANES 4 -#endif -//#define RES_1280x720 -#ifdef RES_1280x720 -#define IMG_HEIGHT_LINES 720 -#define IMG_WIDTH_PX 1280 -#define MIPI_TX_ACTIVE_LANES 2 -#endif struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .width_pixels = IMG_WIDTH_PX, .height_lines = IMG_HEIGHT_LINES, @@ -124,7 +106,6 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .dma_packed = 0 }; -#ifdef RES_1920x1080 struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .sections[0] = &mipi_tx_frame0_sect_cfg, .sections[1] = NULL, @@ -137,22 +118,6 @@ struct mipi_tx_frame_cfg mipitx_frame0_cfg = { .h_backporch = 148, .h_frontporch = 88 }; -#endif - -#ifdef RES_1280x720 -struct mipi_tx_frame_cfg mipitx_frame0_cfg = { - .sections[0] = &mipi_tx_frame0_sect_cfg, - .sections[1] = NULL, - .sections[2] = NULL, - .sections[3] = NULL, - .vsync_width = 5, - .v_backporch = 20, - .v_frontporch = 5, - .hsync_width = 40, - .h_backporch = 220, - .h_frontporch = 110, -}; -#endif struct mipi_tx_dsi_cfg mipitx_dsi_cfg = { .hfp_blank_en = 0, @@ -1740,10 +1705,58 @@ int kmb_kernel_read(struct file *file, loff_t offset, return ret; } -int kmb_dsi_hw_init(struct drm_device *dev) +int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) { struct kmb_drm_private *dev_p = dev->dev_private; + u64 data_rate; + + mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES; + if (mode != NULL) { + mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay; + mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay; + mipitx_frame0_cfg.vsync_width = + mode->crtc_vsync_end - mode->crtc_vsync_start; + mipitx_frame0_cfg.v_backporch = + mode->crtc_vtotal - mode->crtc_vsync_end; + mipitx_frame0_cfg.v_frontporch = + mode->crtc_vsync_start - mode->crtc_vdisplay; + mipitx_frame0_cfg.hsync_width = + mode->crtc_hsync_end - mode->crtc_hsync_start; + mipitx_frame0_cfg.h_backporch = + mode->crtc_htotal - mode->crtc_hsync_end; + mipitx_frame0_cfg.h_frontporch = + mode->crtc_hsync_start - mode->crtc_hdisplay; + /*lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000 + * to convert to Mbps + */ + DRM_INFO("htotal = %d vtotal=%d refresh=%d\n", + mode->crtc_htotal, mode->crtc_vtotal, + drm_mode_vrefresh(mode)); + data_rate = + ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) + * (u32)(drm_mode_vrefresh(mode)) + * MIPI_TX_BPP)/mipi_tx_init_cfg.active_lanes) / 1000000; + DRM_INFO("data_rate = %llu active_lanes=%d\n", + data_rate, mipi_tx_init_cfg.active_lanes); + + /*when late rate < 800 - modeset fails with 4 lanes - + * so switch to 2 lanes + */ + if (data_rate < 800) { + mipi_tx_init_cfg.active_lanes = 2; + mipi_tx_init_cfg.lane_rate_mbps = data_rate * 2; + } else { + mipi_tx_init_cfg.lane_rate_mbps = data_rate; + } + DRM_INFO("lane rate=%d\n", mipi_tx_init_cfg.lane_rate_mbps); + DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d\n", + mipitx_frame0_cfg.v_frontporch, mipitx_frame0_cfg.v_backporch, + mipitx_frame0_cfg.vsync_width, + mipitx_frame0_cfg.h_frontporch, mipitx_frame0_cfg.h_backporch, + mipitx_frame0_cfg.hsync_width, + mipi_tx_init_cfg.lane_rate_mbps); + } if (hw_initialized) return 0; kmb_write_mipi(dev_p, DPHY_ENABLE, 0); @@ -1826,15 +1839,13 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) drm_encoder_cleanup(encoder); return ret; } -#endif -#ifndef FCCTEST DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); #endif #ifdef FCCTEST #ifndef LCD_TEST - kmb_dsi_hw_init(dev); + kmb_dsi_hw_init(dev, NULL); #endif #endif return 0; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index ece4ee1..1d4ca8d 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -341,7 +341,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); void kmb_dsi_host_unregister(void); -int kmb_dsi_hw_init(struct drm_device *dev); +int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode); #define to_kmb_connector(x) container_of(x, struct kmb_connector, base) #define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:58 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:58 -0700 Subject: [Intel-gfx] [PATCH 46/59] drm/kmb: Enable LCD interrupts during modeset In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-47-git-send-email-anitha.chrisanthus@intel.com> The issue was that spurious interrupts were happening before the LCD controller was enabled and system hangs. Fix is to clear LCD interrupts and disable them before modeset and re enable them after enabling LCD controller. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 6 +++++- drivers/gpu/drm/kmb/kmb_drv.c | 21 +++------------------ 2 files changed, 8 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index b617507..16f6c7f 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -97,6 +97,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) struct videomode vm; int vsync_start_offset; int vsync_end_offset; + unsigned int val = 0; /* initialize mipi */ kmb_dsi_hw_init(dev, m); @@ -107,6 +108,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) m->crtc_hsync_start - m->crtc_hdisplay, m->crtc_htotal - m->crtc_hsync_end, m->crtc_hsync_end - m->crtc_hsync_start); + val = kmb_read_lcd(dev->dev_private, LCD_INT_ENABLE); + kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, val); + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0); // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; @@ -155,9 +159,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, 10); kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10); } - /* enable VL1 layer as default */ kmb_write_lcd(dev->dev_private, LCD_TIMING_GEN_TRIG, ENABLE); kmb_set_bitmask_lcd(dev->dev_private, LCD_CONTROL, LCD_CTRL_ENABLE); + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, val); #endif /* TBD */ /* set clocks here */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index d987529..26d004c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -57,8 +57,6 @@ static irqreturn_t kmb_isr(int irq, void *arg); static struct clk *clk_lcd; static struct clk *clk_mipi; -static struct clk *clk_msscam; -static struct clk *clk_pll0out0; static struct clk *clk_mipi_ecfg; static struct clk *clk_mipi_cfg; @@ -79,12 +77,6 @@ int kmb_display_clk_enable(void) DRM_ERROR("Failed to enable MIPI clock: %d\n", ret); return ret; } -/* ret = clk_prepare_enable(clk_msscam); - if (ret) { - DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret); - return ret; - } - */ ret = clk_prepare_enable(clk_mipi_ecfg); if (ret) { @@ -107,8 +99,6 @@ static int kmb_display_clk_disable(void) clk_disable_unprepare(clk_lcd); if (clk_mipi) clk_disable_unprepare(clk_mipi); - if (clk_msscam) - clk_disable_unprepare(clk_msscam); if (clk_mipi_ecfg) clk_disable_unprepare(clk_mipi_ecfg); if (clk_mipi_cfg) @@ -200,14 +190,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } - clk_pll0out0 = clk_get(&pdev->dev, "clk_pll0_out0"); - if (IS_ERR(clk_pll0out0)) - DRM_ERROR("clk_get() failed clk_pll0_out0\n"); - - if (clk_pll0out0) - DRM_INFO("Get clk_pll0out0 = %ld\n", - clk_get_rate(clk_pll0out0)); - clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); if (IS_ERR(clk_mipi_ecfg)) { DRM_ERROR("clk_get() failed clk_mipi_ecfg\n"); @@ -413,6 +395,9 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) break; } } + + /* clear all interrupts */ + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0); return IRQ_HANDLED; } -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:01 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:01 -0700 Subject: [Intel-gfx] [PATCH 49/59] drm/kmb: Disable ping pong mode In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-50-git-send-email-anitha.chrisanthus@intel.com> Disable ping pong mode otherwise video corruption results, use continuous mode and also fetch the dma addresses before disabling dma. For now, only initialize the dma and planes once and for next plane updates only update the addresses for dma. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 303 ++++++++++++++++++++-------------------- drivers/gpu/drm/kmb/kmb_plane.h | 8 ++ 2 files changed, 159 insertions(+), 152 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 9f9ae57..35dece3 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -103,11 +103,12 @@ static const u32 kmb_formats_v[] = { #define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) const uint32_t layer_irqs[] = { - LCD_INT_VL0, - LCD_INT_VL1, - LCD_INT_GL0, - LCD_INT_GL1 - }; + LCD_INT_VL0, + LCD_INT_VL1, + LCD_INT_GL0, + LCD_INT_GL1 +}; + /*Conversion (yuv->rgb) matrix from myriadx */ static const u32 csc_coef_lcd[] = { 1024, 0, 1436, @@ -116,7 +117,6 @@ static const u32 csc_coef_lcd[] = { -179, 125, -226 }; - static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -134,7 +134,6 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, struct drm_framebuffer *fb; int ret; - fb = state->fb; if (!fb || !state->crtc) @@ -150,7 +149,7 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, } static void kmb_plane_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_plane_state *state) { struct kmb_plane *kmb_plane = to_kmb_plane(plane); int ctrl = 0; @@ -176,14 +175,13 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, } kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - LCD_DMA_LAYER_ENABLE); + LCD_DMA_LAYER_ENABLE); kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); DRM_INFO("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n", - __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), - kmb_read_lcd(dev_p, LCD_INT_ENABLE)); + __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), + kmb_read_lcd(dev_p, LCD_INT_ENABLE)); } - unsigned int set_pixel_format(u32 format) { unsigned int val = 0; @@ -218,8 +216,8 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE | LCD_LAYER_CRCB_ORDER; break; - /* packed formats */ - /* looks hw requires B & G to be swapped when RGB */ + /* packed formats */ + /* looks hw requires B & G to be swapped when RGB */ case DRM_FORMAT_RGB332: val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER; break; @@ -283,7 +281,7 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) return val; } - bpp += 8*format->cpp[0]; + bpp += 8 * format->cpp[0]; switch (bpp) { case 8: @@ -330,7 +328,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, #ifdef LCD_TEST struct drm_framebuffer *fb; struct kmb_drm_private *dev_p; - dma_addr_t addr; unsigned int width; unsigned int height; unsigned int dma_len; @@ -340,6 +337,9 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned int src_w, src_h, crtc_x, crtc_y; unsigned char plane_id; int num_planes; + /*plane initialization status */ + static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 }; + static dma_addr_t addr[MAX_SUB_PLANES] = { 0, 0, 0 }; if (!plane || !plane->state || !state) return; @@ -352,8 +352,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, kmb_plane = to_kmb_plane(plane); plane_id = kmb_plane->id; - - dev_p = plane->dev->dev_private; src_w = (plane->state->src_w >> 16); @@ -361,146 +359,145 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - DRM_INFO("src_w=%d src_h=%d\n", src_w, src_h); - kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1); - kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1); - kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); - kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y); - - val = set_pixel_format(fb->format->format); - val |= set_bits_per_pixel(fb->format); - /*CHECKME Leon drvr sets it to 100 try this for now */ - val |= LCD_LAYER_FIFO_100; - kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); - - /*re-initialize interrupts */ - kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]); - kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, layer_irqs[plane_id]); - kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, layer_irqs[plane_id]); - - /*TBD check visible? */ -/* - dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_AUTO_UPDATE - | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1 - | LCD_DMA_LAYER_VSTRIDE_EN; -*/ - dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN - | LCD_DMA_LAYER_AXI_BURST_16 | - LCD_DMA_LAYER_CONT_PING_PONG_UPDATE; - - /* disable DMA first */ - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - ~LCD_DMA_LAYER_ENABLE); - kmb_write_lcd(dev_p, LCD_FIFO_FLUSH + plane_id*0x400, 1); - - /* pinpong mode is enabled - at the end of DMA transfer, start new - * transfer alternatively using main and shadow register settings. - * So update both main and shadow registers - */ - addr = drm_fb_cma_get_gem_addr(fb, plane->state, 0); - dev_p->fb_addr = addr; - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_SHADOW(plane_id), addr); - - width = fb->width; - height = fb->height; - dma_len = width * height * fb->format->cpp[0]; - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); - - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[0]); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width*fb->format->cpp[0])); - - /*program Cb/Cr for planar formats*/ - if (num_planes > 1) { - if (fb->format->format == DRM_FORMAT_YUV420 || - fb->format->format == DRM_FORMAT_YVU420) - width /= 2; - addr = drm_fb_cma_get_gem_addr(fb, plane->state, LAYER_1); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), - addr); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_SHADOW(plane_id), - addr); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), - fb->pitches[LAYER_1]); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), - (width*fb->format->cpp[0])); - if (num_planes == 3) { - addr = drm_fb_cma_get_gem_addr(fb, plane->state, - LAYER_2); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_START_CR_ADR(plane_id), - addr); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_START_CR_SHADOW(plane_id), - addr); + DRM_INFO + ("%s : %d src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x", + __func__, __LINE__, src_w, src_h, fb->format->format, fb->flags); + if (plane_init_status[plane_id] != INITIALIZED) { + kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1); + kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); + kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); + kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y); + + val = set_pixel_format(fb->format->format); + val |= set_bits_per_pixel(fb->format); + /*CHECKME Leon drvr sets it to 100 try this for now */ + val |= LCD_LAYER_FIFO_100; + kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); + + /*re-initialize interrupts */ + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, + layer_irqs[plane_id]); + kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, layer_irqs[plane_id]); + + dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | + LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; + + width = fb->width; + height = fb->height; + dma_len = (width * height * fb->format->cpp[0]); + DRM_INFO("%s : %d dma_len=%d ", __func__, __LINE__, dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), + dma_len); + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[0]); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + + /*program Cb/Cr for planar formats */ + if (num_planes > 1) { + if (fb->format->format == DRM_FORMAT_YUV420 || + fb->format->format == DRM_FORMAT_YVU420) + width /= 2; kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), - fb->pitches[LAYER_2]); + LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), + fb->pitches[LAYER_1]); kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), - (width*fb->format->cpp[0])); + LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + if (num_planes == 3) { + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_VSTRIDE + (plane_id), fb->pitches[LAYER_2]); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_WIDTH + (plane_id), + (width * fb->format->cpp[0])); + } } - } - /* enable DMA */ - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); - DRM_INFO("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", __func__, - __LINE__, dma_cfg, - kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); + /* enable DMA */ + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + DRM_INFO("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", + __func__, __LINE__, dma_cfg, + kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); + + switch (plane_id) { + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; + } - switch (plane_id) { - case LAYER_0: - ctrl = LCD_CTRL_VL1_ENABLE; - break; - case LAYER_1: - ctrl = LCD_CTRL_VL2_ENABLE; - break; - case LAYER_2: - ctrl = LCD_CTRL_GL1_ENABLE; - break; - case LAYER_3: - ctrl = LCD_CTRL_GL2_ENABLE; - break; - } + ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; -// ctrl |= LCD_CTRL_ENABLE; - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; + /*LCD is connected to MIPI on kmb + * Therefore this bit is required for DSI Tx + */ + ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; -// ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE -// | LCD_CTRL_ONE_SHOT | LCD_CTRL_OUTPUT_ENABLED; - /*LCD is connected to MIPI on kmb - * Therefore this bit is required for DSI Tx - */ - ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; + kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); - kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); + /* FIXME no doc on how to set output format,these values are + * taken from the Myriadx tests + */ + out_format |= LCD_OUTF_FORMAT_RGB888; - /* FIXME no doc on how to set output format,these values are taken - * from the Myriadx tests - */ - out_format |= LCD_OUTF_FORMAT_RGB888; -// out_format |= LCD_OUTF_BGR_ORDER; + if (val & LCD_LAYER_PLANAR_STORAGE) { + /*enable CSC if input is planar and output is RGB */ + config_csc(dev_p, plane_id); + } + + /*set background color to white */ + // kmb_write_lcd(dev_p, LCD_BG_COLOUR_LS, 0xffffff); + /*leave RGB order,conversion mode and clip mode to default */ + /* do not interleave RGB channels for mipi Tx compatibility */ + out_format |= LCD_OUTF_MIPI_RGB_MODE; + kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); - if (val & LCD_LAYER_PLANAR_STORAGE) { - /*enable CSC if input is planar and output is RGB */ - config_csc(dev_p, plane_id); + kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, + layer_irqs[plane_id]); + plane_init_status[plane_id] = INITIALIZED; } - /*set background color to white*/ -// kmb_write_lcd(dev_p, LCD_BG_COLOUR_LS, 0xffffff); - /*leave RGB order,conversion mode and clip mode to default*/ - /* do not interleave RGB channels for mipi Tx compatibility */ - out_format |= LCD_OUTF_MIPI_RGB_MODE; -// out_format |= LCD_OUTF_SYNC_MODE ; - kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); + addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); + dev_p->fb_addr = (dma_addr_t) addr; + if (num_planes > 1) { + addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, + U_PLANE); + if (num_planes == 3) + addr[V_PLANE] = + drm_fb_cma_get_gem_addr(fb, plane->state, V_PLANE); + } + /* disable DMA first */ + kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), + addr[Y_PLANE] + fb->offsets[0]); + if (num_planes > 1) { + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), + addr[U_PLANE]); + if (num_planes == 3) + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CR_ADR(plane_id), + addr[V_PLANE]); + } + /* Enable DMA */ + kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + LCD_DMA_LAYER_ENABLE); + DRM_INFO("%s : %d flipping.....\n", __func__, __LINE__); + return; -// kmb_write_lcd(dev_p, LCD_CONTROL, LCD_CTRL_ENABLE); #endif } @@ -513,6 +510,7 @@ static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { void kmb_plane_destroy(struct drm_plane *plane) { struct kmb_plane *kmb_plane = to_kmb_plane(plane); + drm_plane_cleanup(plane); kfree(kmb_plane); } @@ -591,7 +589,7 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) } plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY : - DRM_PLANE_TYPE_OVERLAY; + DRM_PLANE_TYPE_OVERLAY; if (i < 2) { plane_formats = kmb_formats_v; num_plane_formats = ARRAY_SIZE(kmb_formats_v); @@ -601,13 +599,14 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) } ret = drm_universal_plane_init(drm, &plane->base_plane, - POSSIBLE_CRTCS, - &kmb_plane_funcs, plane_formats, - num_plane_formats, - NULL, plane_type, "plane %d", i); + POSSIBLE_CRTCS, + &kmb_plane_funcs, plane_formats, + num_plane_formats, + NULL, plane_type, "plane %d", i); if (ret < 0) { - DRM_ERROR("drm_universal_plane_init -failed with ret=%d" - , ret); + DRM_ERROR + ("drm_universal_plane_init -failed with ret=%d", + ret); goto cleanup; } diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index 45bcec1..8411219 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -36,6 +36,13 @@ enum layer_id { KMB_MAX_PLANES, }; +enum sub_plane_id { + Y_PLANE, + U_PLANE, + V_PLANE, + MAX_SUB_PLANES, +}; + struct kmb_plane { struct drm_plane base_plane; struct kmb_drm_private kmb_dev; @@ -48,6 +55,7 @@ struct kmb_plane_state { }; #define POSSIBLE_CRTCS 1 +#define INITIALIZED 1 #define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) #define to_kmb_plane_state(x) \ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:02 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:02 -0700 Subject: [Intel-gfx] [PATCH 50/59] drm/kmb: Do the layer initializations only once In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-51-git-send-email-anitha.chrisanthus@intel.com> The issue was video starts fine, but towards the end, the color disappers. Do the layer initializations only once, but update the DMA registers for every frame. Also changed DRM_INFO to DRM_DEBUG. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 150 ++++++++++++++++++---------------------- 1 file changed, 66 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 35dece3..8aa48b5 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -117,6 +117,9 @@ static const u32 csc_coef_lcd[] = { -179, 125, -226 }; +/*plane initialization status */ +static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 }; + static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -177,9 +180,9 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), LCD_DMA_LAYER_ENABLE); kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); - DRM_INFO("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n", - __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), - kmb_read_lcd(dev_p, LCD_INT_ENABLE)); + DRM_DEBUG("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n", + __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), + kmb_read_lcd(dev_p, LCD_INT_ENABLE)); } unsigned int set_pixel_format(u32 format) @@ -337,8 +340,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned int src_w, src_h, crtc_x, crtc_y; unsigned char plane_id; int num_planes; - /*plane initialization status */ - static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 }; static dma_addr_t addr[MAX_SUB_PLANES] = { 0, 0, 0 }; if (!plane || !plane->state || !state) @@ -359,9 +360,56 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - DRM_INFO + DRM_DEBUG ("%s : %d src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x", __func__, __LINE__, src_w, src_h, fb->format->format, fb->flags); + + width = fb->width; + height = fb->height; + dma_len = (width * height * fb->format->cpp[0]); + DRM_DEBUG("%s : %d dma_len=%d ", __func__, __LINE__, dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), + fb->pitches[0]); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + + addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); + dev_p->fb_addr = (dma_addr_t) addr; + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), + addr[Y_PLANE] + fb->offsets[0]); + /*program Cb/Cr for planar formats */ + if (num_planes > 1) { + if (fb->format->format == DRM_FORMAT_YUV420 || + fb->format->format == DRM_FORMAT_YVU420) + width /= 2; + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), + fb->pitches[LAYER_1]); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, + U_PLANE); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), + addr[U_PLANE]); + if (num_planes == 3) { + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), + fb->pitches[LAYER_2]); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), + (width * fb->format->cpp[0])); + addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, + plane->state, + V_PLANE); + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CR_ADR(plane_id), + addr[V_PLANE]); + } + } if (plane_init_status[plane_id] != INITIALIZED) { kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1); kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); @@ -374,55 +422,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val |= LCD_LAYER_FIFO_100; kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); - /*re-initialize interrupts */ - kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, - layer_irqs[plane_id]); - kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, layer_irqs[plane_id]); - - dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | - LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; - - width = fb->width; - height = fb->height; - dma_len = (width * height * fb->format->cpp[0]); - DRM_INFO("%s : %d dma_len=%d ", __func__, __LINE__, dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), - dma_len); - - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[0]); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width * fb->format->cpp[0])); - - /*program Cb/Cr for planar formats */ - if (num_planes > 1) { - if (fb->format->format == DRM_FORMAT_YUV420 || - fb->format->format == DRM_FORMAT_YVU420) - width /= 2; - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), - fb->pitches[LAYER_1]); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), - (width * fb->format->cpp[0])); - if (num_planes == 3) { - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_VSTRIDE - (plane_id), fb->pitches[LAYER_2]); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_WIDTH - (plane_id), - (width * fb->format->cpp[0])); - } - } - - /* enable DMA */ - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); - DRM_INFO("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", - __func__, __LINE__, dma_cfg, - kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); - switch (plane_id) { case LAYER_0: ctrl = LCD_CTRL_VL1_ENABLE; @@ -464,38 +463,18 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); - - kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, - layer_irqs[plane_id]); plane_init_status[plane_id] = INITIALIZED; } - addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); - dev_p->fb_addr = (dma_addr_t) addr; - if (num_planes > 1) { - addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, - U_PLANE); - if (num_planes == 3) - addr[V_PLANE] = - drm_fb_cma_get_gem_addr(fb, plane->state, V_PLANE); - } - /* disable DMA first */ - kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - LCD_DMA_LAYER_ENABLE); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), - addr[Y_PLANE] + fb->offsets[0]); - if (num_planes > 1) { - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), - addr[U_PLANE]); - if (num_planes == 3) - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_START_CR_ADR(plane_id), - addr[V_PLANE]); - } - /* Enable DMA */ - kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - LCD_DMA_LAYER_ENABLE); - DRM_INFO("%s : %d flipping.....\n", __func__, __LINE__); + dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | + LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; + + /* enable DMA */ + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); + DRM_DEBUG("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", + __func__, __LINE__, dma_cfg, + kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); + return; #endif @@ -609,6 +588,9 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) ret); goto cleanup; } + DRM_DEBUG("%s : %d plane=%px\n i=%d type=%d", + __func__, __LINE__, &plane->base_plane, + i, plane_type); drm_plane_helper_add(&plane->base_plane, &kmb_plane_helper_funcs); -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:05 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:05 -0700 Subject: [Intel-gfx] [PATCH 53/59] drm/kmb: disable the LCD layer in EOF irq handler In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-54-git-send-email-anitha.chrisanthus@intel.com> When disabling/enabling LCD layers, the change takes effect immediately and does not wait for EOF (end of frame). If we disable an LCD layer in kmb_plane_atomic_disable, then the frame reappears with incorrect display offsets. The solution is to mark the plane as disabled when kmb_plane_atomic_disable is called but actually disable the LCD layer when EOF irq is being handled. Also only enable one plane (video plane0) as there is no use case for multiple planes. Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 37 +++++++++++++++++++++++++++++++------ drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_plane.c | 24 ++++++++---------------- drivers/gpu/drm/kmb/kmb_plane.h | 9 ++++++++- 4 files changed, 48 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index c699f01..79ab0bc 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -62,6 +62,8 @@ static struct clk *clk_mipi_cfg; struct drm_bridge *adv_bridge; +extern struct layer_status plane_status[KMB_MAX_PLANES]; + int kmb_display_clk_enable(void) { int ret = 0; @@ -367,25 +369,48 @@ static void kmb_setup_mode_config(struct drm_device *drm) static irqreturn_t handle_lcd_irq(struct drm_device *dev) { unsigned long status, val; + int plane_id; + struct kmb_drm_private *dev_p = dev->dev_private; status = kmb_read_lcd(dev->dev_private, LCD_INT_STATUS); if (status & LCD_INT_EOF) { /* TODO - handle EOF interrupt? */ - kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_EOF); + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_EOF); + + /* When disabling/enabling LCD layers, the change takes effect + * immediately and does not wait for EOF (end of frame). + * When kmb_plane_atomic_disable is called, mark the plane as + * disabled but actually disable the plane when EOF irq is + * being handled. + */ + for (plane_id = LAYER_0; plane_id < KMB_MAX_PLANES; + plane_id++) { + if (plane_status[plane_id].disable) { + kmb_clr_bitmask_lcd(dev_p, + LCD_LAYERn_DMA_CFG(plane_id), + LCD_DMA_LAYER_ENABLE); + + kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, + plane_status[plane_id].ctrl); + + plane_status[plane_id].disable = false; + } + } } + if (status & LCD_INT_LINE_CMP) { /* clear line compare interrupt */ - kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, - LCD_INT_LINE_CMP); + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LINE_CMP); } + if (status & LCD_INT_LAYER) { /* Clear layer interrupts */ - kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LAYER); + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LAYER); } if (status & LCD_INT_VERT_COMP) { /* Read VSTATUS */ - val = kmb_read_lcd(dev->dev_private, LCD_VSTATUS); + val = kmb_read_lcd(dev_p, LCD_VSTATUS); val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); switch (val) { case LCD_VSTATUS_COMPARE_VSYNC: @@ -401,7 +426,7 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) } /* Clear all interrupts */ - kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0); + kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, 1); return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 4916b217..83824f7 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -39,6 +39,7 @@ #define crtc_to_kmb_priv(x) container_of(x, struct kmb_drm_private, crtc) + struct kmb_drm_private { struct drm_device drm; void __iomem *lcd_mmio; diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 8d83238..81250e1 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -41,6 +41,8 @@ #include "kmb_regs.h" #include "kmb_drv.h" +struct layer_status plane_status[KMB_MAX_PLANES]; + const uint32_t layer_irqs[] = { LCD_INT_VL0, LCD_INT_VL1, @@ -82,34 +84,24 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_state *state) { struct kmb_plane *kmb_plane = to_kmb_plane(plane); - int ctrl = 0; - struct kmb_drm_private *dev_p; - int plane_id; - - dev_p = plane->dev->dev_private; - plane_id = kmb_plane->id; + int plane_id = kmb_plane->id; switch (plane_id) { case LAYER_0: - ctrl = LCD_CTRL_VL1_ENABLE; + plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE; break; case LAYER_1: - ctrl = LCD_CTRL_VL2_ENABLE; + plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE; break; case LAYER_2: - ctrl = LCD_CTRL_GL1_ENABLE; + plane_status[plane_id].ctrl = LCD_CTRL_GL1_ENABLE; break; case LAYER_3: - ctrl = LCD_CTRL_GL2_ENABLE; + plane_status[plane_id].ctrl = LCD_CTRL_GL2_ENABLE; break; } - kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - LCD_DMA_LAYER_ENABLE); - kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); - DRM_DEBUG("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n", - __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), - kmb_read_lcd(dev_p, LCD_INT_ENABLE)); + plane_status[plane_id].disable = true; } unsigned int set_pixel_format(u32 format) diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index 1872ed0..ae8e308 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -61,9 +61,11 @@ enum layer_id { LAYER_1, LAYER_2, LAYER_3, - KMB_MAX_PLANES, +// KMB_MAX_PLANES, }; +#define KMB_MAX_PLANES 1 + enum sub_plane_id { Y_PLANE, U_PLANE, @@ -125,6 +127,11 @@ static const u32 csc_coef_lcd[] = { -179, 125, -226 }; +struct layer_status { + bool disable; + u32 ctrl; +}; + struct kmb_plane *kmb_plane_init(struct drm_device *drm); void kmb_plane_destroy(struct drm_plane *plane); #endif /* __KMB_PLANE_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:04 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:04 -0700 Subject: [Intel-gfx] [PATCH 52/59] drm/kmb: Cleaned up code In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-53-git-send-email-anitha.chrisanthus@intel.com> From: Edmund Dea <edmund.j.dea at intel.com> to remove compiler warnings and general clean up Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 48 +- drivers/gpu/drm/kmb/kmb_crtc.h | 6 +- drivers/gpu/drm/kmb/kmb_drv.c | 115 +++-- drivers/gpu/drm/kmb/kmb_drv.h | 107 ++-- drivers/gpu/drm/kmb/kmb_dsi.c | 1073 +++++++++++++++++++++------------------ drivers/gpu/drm/kmb/kmb_dsi.h | 84 ++- drivers/gpu/drm/kmb/kmb_plane.c | 155 ++---- drivers/gpu/drm/kmb/kmb_plane.h | 74 ++- drivers/gpu/drm/kmb/kmb_regs.h | 29 +- 9 files changed, 898 insertions(+), 793 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 16f6c7f..c01977b 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -59,10 +59,10 @@ static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /*set which interval to generate vertical interrupt */ kmb_write_lcd(dev->dev_private, LCD_VSTATUS_COMPARE, - LCD_VSTATUS_COMPARE_VSYNC); + LCD_VSTATUS_COMPARE_VSYNC); /* enable vertical interrupt */ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP); return 0; } @@ -74,7 +74,7 @@ static void kmb_crtc_disable_vblank(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /* disable vertical interrupt */ kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP); } @@ -102,38 +102,38 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) /* initialize mipi */ kmb_dsi_hw_init(dev, m); DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n", - m->crtc_vsync_start - m->crtc_vdisplay, - m->crtc_vtotal - m->crtc_vsync_end, - m->crtc_vsync_end - m->crtc_vsync_start, - m->crtc_hsync_start - m->crtc_hdisplay, - m->crtc_htotal - m->crtc_hsync_end, - m->crtc_hsync_end - m->crtc_hsync_start); + m->crtc_vsync_start - m->crtc_vdisplay, + m->crtc_vtotal - m->crtc_vsync_end, + m->crtc_vsync_end - m->crtc_vsync_start, + m->crtc_hsync_start - m->crtc_hdisplay, + m->crtc_htotal - m->crtc_hsync_end, + m->crtc_hsync_end - m->crtc_hsync_start); val = kmb_read_lcd(dev->dev_private, LCD_INT_ENABLE); kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, val); kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0); -// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; +// vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; -// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; +// vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; vm.vback_porch = 2; -// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; +// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; vm.vsync_len = 1; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; vm.hback_porch = 0; //vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; vm.hsync_len = 7; -// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; +// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; - DRM_INFO("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d\n", - __func__, __LINE__, m->crtc_vdisplay, - vm.vback_porch, vm.vfront_porch, - vm.vsync_len, m->crtc_hdisplay, - vm.hback_porch, vm.hfront_porch, vm.hsync_len); + DRM_DEBUG + ("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d", + __func__, __LINE__, m->crtc_vdisplay, vm.vback_porch, + vm.vfront_porch, vm.vsync_len, m->crtc_hdisplay, vm.hback_porch, + vm.hfront_porch, vm.hsync_len); kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT, - m->crtc_vdisplay - 1); + m->crtc_vdisplay - 1); kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch); kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch); kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1); @@ -148,14 +148,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) if (m->flags == DRM_MODE_FLAG_INTERLACE) { kmb_write_lcd(dev->dev_private, - LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); + LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH_EVEN, vm.vback_porch); kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH_EVEN, vm.vfront_porch); kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT_EVEN, - m->crtc_vdisplay - 1); - /*this is hardcoded as 10 in the Myriadx code*/ + m->crtc_vdisplay - 1); + /*this is hardcoded as 10 in the Myriadx code */ kmb_write_lcd(dev->dev_private, LCD_VSYNC_START_EVEN, 10); kmb_write_lcd(dev->dev_private, LCD_VSYNC_END_EVEN, 10); } @@ -195,7 +195,7 @@ static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP); } static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, @@ -204,7 +204,7 @@ static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP); spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.h b/drivers/gpu/drm/kmb/kmb_crtc.h index 5fe8890..2c05240 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.h +++ b/drivers/gpu/drm/kmb/kmb_crtc.h @@ -44,6 +44,9 @@ #include <linux/platform_device.h> #include "kmb_drv.h" +#define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) +#define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base) + struct kmb_crtc { struct drm_crtc crtc_base; struct kmb_drm_private kmb_dev; @@ -52,8 +55,7 @@ struct kmb_crtc { struct kmb_crtc_state { struct drm_crtc_state crtc_base; }; -#define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) -#define to_kmb_crtc(x) container_of(x, struct kmb_crtc, crtc_base) + extern void kmb_plane_destroy(struct drm_plane *plane); extern struct kmb_plane *kmb_plane_init(struct drm_device *drm); #endif /* __KMB_CRTC_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 26d004c..c699f01 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -26,7 +26,7 @@ #include <linux/module.h> #include <linux/spinlock.h> #include <linux/clk.h> -#include <linux/component.h> +//#include <linux/component.h> #include <linux/console.h> #include <linux/list.h> #include <linux/of_graph.h> @@ -50,9 +50,9 @@ #include "kmb_plane.h" #include "kmb_dsi.h" -#define DEBUG +//#define DEBUG -/*IRQ handler*/ +/* IRQ handler */ static irqreturn_t kmb_isr(int irq, void *arg); static struct clk *clk_lcd; @@ -128,8 +128,6 @@ static void __iomem *kmb_map_mmio(struct platform_device *pdev, char *name) release_mem_region(res->start, size); return ERR_PTR(-ENOMEM); } - DRM_INFO("%s : %d mapped %s mmio size = %d\n", __func__, __LINE__, - name, size); return mem; } @@ -137,8 +135,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); - /*u32 version;*/ - int irq_lcd;// irq_mipi; + int irq_lcd; int ret = 0; unsigned long clk; @@ -157,8 +154,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) return -ENOMEM; } - /* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and MSS_CAM_CLK_CTRL - * register + /* This is only for MIPI_TX_MSS_LCD_MIPI_CFG and + * MSS_CAM_CLK_CTRL register */ dev_p->msscam_mmio = kmb_map_mmio(pdev, "msscam_regs"); if (IS_ERR(dev_p->msscam_mmio)) { @@ -174,22 +171,21 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) iounmap(dev_p->mipi_mmio); return -ENOMEM; } - - - #define KMB_CLOCKS #ifdef KMB_CLOCKS - /* Enable display clocks*/ + /* Enable display clocks */ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); if (IS_ERR(clk_lcd)) { DRM_ERROR("clk_get() failed clk_lcd\n"); goto setup_fail; } + clk_mipi = clk_get(&pdev->dev, "clk_mipi"); if (IS_ERR(clk_mipi)) { DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } + clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); if (IS_ERR(clk_mipi_ecfg)) { DRM_ERROR("clk_get() failed clk_mipi_ecfg\n"); @@ -201,59 +197,63 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("clk_get() failed clk_mipi_cfg\n"); goto setup_fail; } - #ifdef LCD_TEST - /* Set LCD clock to 200 Mhz*/ - DRM_INFO("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); + /* Set LCD clock to 200 Mhz */ + DRM_DEBUG("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); ret = clk_set_rate(clk_lcd, KMB_LCD_DEFAULT_CLK); if (clk_get_rate(clk_lcd) != KMB_LCD_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_lcd to %d\n", - KMB_LCD_DEFAULT_CLK); + KMB_LCD_DEFAULT_CLK); } - DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n", - KMB_LCD_DEFAULT_CLK/1000000, ret); + DRM_INFO("Setting LCD clock tp %d Mhz ret = %d\n", + KMB_LCD_DEFAULT_CLK / 1000000, ret); DRM_INFO("Get clk_lcd after set = %ld\n", clk_get_rate(clk_lcd)); #endif - /* Set MIPI clock to 24 Mhz*/ - DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); + #define MIPI_CLK #ifdef MIPI_CLK + /* Set MIPI clock to 24 Mhz */ + DRM_DEBUG("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) { DRM_ERROR("failed to set to clk_mipi to %d\n", - KMB_MIPI_DEFAULT_CLK); + KMB_MIPI_DEFAULT_CLK); goto setup_fail; } #endif DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n", - KMB_MIPI_DEFAULT_CLK/1000000, ret); + KMB_MIPI_DEFAULT_CLK / 1000000, ret); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); clk = clk_get_rate(clk_mipi_ecfg); if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { - /* Set MIPI_ECFG clock to 24 Mhz*/ + /* Set MIPI_ECFG clock to 24 Mhz */ DRM_INFO("Get clk_mipi_ecfg before set = %ld\n", clk); + ret = clk_set_rate(clk_mipi_ecfg, KMB_MIPI_DEFAULT_CFG_CLK); clk = clk_get_rate(clk_mipi_ecfg); - if (clk != KMB_MIPI_DEFAULT_CLK) { + if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { DRM_ERROR("failed to set to clk_mipi_ecfg to %d\n", - KMB_MIPI_DEFAULT_CLK); + KMB_MIPI_DEFAULT_CFG_CLK); goto setup_fail; } + DRM_INFO("Setting MIPI_ECFG clock tp %d Mhz ret = %d\n", - KMB_MIPI_DEFAULT_CLK/1000000, ret); + KMB_MIPI_DEFAULT_CFG_CLK / 1000000, ret); + DRM_INFO("Get clk_mipi_ecfg after set = %ld\n", clk); } clk = clk_get_rate(clk_mipi_cfg); if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { - /* Set MIPI_CFG clock to 24 Mhz*/ + /* Set MIPI_CFG clock to 24 Mhz */ DRM_INFO("Get clk_mipi_cfg before set = %ld\n", clk); + ret = clk_set_rate(clk_mipi_cfg, 24000000); clk = clk_get_rate(clk_mipi_cfg); if (clk != KMB_MIPI_DEFAULT_CFG_CLK) { DRM_ERROR("failed to set to clk_mipi_cfg to %d\n", - KMB_MIPI_DEFAULT_CFG_CLK); + KMB_MIPI_DEFAULT_CFG_CLK); goto setup_fail; } DRM_INFO("Setting MIPI_CFG clock tp 24Mhz ret = %d\n", ret); @@ -262,10 +262,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) ret = kmb_display_clk_enable(); - /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ + /* Enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); + #endif //KMB_CLOCKS + /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - * firmware has redirected 79 to A53 IRQ 33 @@ -312,19 +314,21 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } - /* Initialize MIPI DSI */ ret = kmb_dsi_init(drm, adv_bridge); if (ret) { DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } + ret = drm_irq_install(drm, irq_lcd); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); goto irq_fail; } + dev_p->irq_lcd = irq_lcd; + return 0; irq_fail: @@ -336,10 +340,11 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) } int kmb_atomic_helper_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_state *state) { if (!state) return 0; + return drm_atomic_helper_check(dev, state); } @@ -359,28 +364,27 @@ static void kmb_setup_mode_config(struct drm_device *drm) drm->mode_config.funcs = &kmb_mode_config_funcs; } - static irqreturn_t handle_lcd_irq(struct drm_device *dev) { unsigned long status, val; status = kmb_read_lcd(dev->dev_private, LCD_INT_STATUS); if (status & LCD_INT_EOF) { - /*To DO - handle EOF interrupt? */ + /* TODO - handle EOF interrupt? */ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_EOF); } if (status & LCD_INT_LINE_CMP) { /* clear line compare interrupt */ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, - LCD_INT_LINE_CMP); + LCD_INT_LINE_CMP); } if (status & LCD_INT_LAYER) { - /* clear layer interrupts */ + /* Clear layer interrupts */ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LAYER); } if (status & LCD_INT_VERT_COMP) { - /* read VSTATUS */ + /* Read VSTATUS */ val = kmb_read_lcd(dev->dev_private, LCD_VSTATUS); val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); switch (val) { @@ -390,19 +394,19 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) case LCD_VSTATUS_COMPARE_FRONT_PORCH: /* clear vertical compare interrupt */ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, - LCD_INT_VERT_COMP); + LCD_INT_VERT_COMP); drm_handle_vblank(dev, 0); break; } } - /* clear all interrupts */ + /* Clear all interrupts */ kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_CLEAR, ~0x0); return IRQ_HANDLED; } #ifdef MIPI_IRQ -static irqreturn_t handle_mipi_irq(struct drm_device *dev) +static irqreturn_t handle_mipi_irq(struct drm_device *dev) { mipi_tx_handle_irqs(dev->dev_private); return IRQ_HANDLED; @@ -428,7 +432,7 @@ DEFINE_DRM_GEM_CMA_FOPS(fops); static struct drm_driver kmb_driver = { .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | - DRIVER_MODESET | DRIVER_ATOMIC, + DRIVER_MODESET | DRIVER_ATOMIC, .irq_handler = kmb_isr, .irq_preinstall = kmb_irq_reset, .irq_uninstall = kmb_irq_reset, @@ -457,7 +461,9 @@ static void kmb_drm_unload(struct device *dev) struct drm_device *drm = dev_get_drvdata(dev); struct kmb_drm_private *dev_p = drm->dev_private; +#ifdef DEBUG dump_stack(); +#endif drm_dev_unregister(drm); drm_kms_helper_poll_fini(drm); of_node_put(dev_p->crtc.port); @@ -485,7 +491,7 @@ static void kmb_drm_unload(struct device *dev) of_reserved_mem_device_release(drm->dev); drm_mode_config_cleanup(drm); - /*release clks */ + /* Release clks */ kmb_display_clk_disable(); clk_put(clk_lcd); clk_put(clk_mipi); @@ -512,7 +518,8 @@ static int kmb_probe(struct platform_device *pdev) * and then the rest of the driver initialization can procees * afterwards and the bridge can be successfully attached. */ - adv_bridge = kmb_dsi_host_bridge_init(dev); + adv_bridge = kmb_dsi_host_bridge_init(dev); + #ifndef FCCTEST if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) return -EPROBE_DEFER; @@ -521,6 +528,7 @@ static int kmb_probe(struct platform_device *pdev) return PTR_ERR(adv_bridge); } #endif + /* Create DRM device */ drm = drm_dev_alloc(&kmb_driver, dev); if (IS_ERR(drm)) @@ -532,7 +540,7 @@ static int kmb_probe(struct platform_device *pdev) drm->dev_private = lcd; kmb_setup_mode_config(drm); - dev_set_drvdata(dev, drm); + dev_set_drvdata(dev, drm); /* Load driver */ lcd->n_layers = KMB_MAX_PLANES; @@ -551,6 +559,7 @@ static int kmb_probe(struct platform_device *pdev) DRM_ERROR("failed to initialize vblank\n"); goto err_vblank; } + drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm); @@ -561,7 +570,7 @@ static int kmb_probe(struct platform_device *pdev) goto err_register; #ifndef FCCTEST -// drm_fbdev_generic_setup(drm, 32); + //drm_fbdev_generic_setup(drm, 32); #endif return 0; @@ -584,7 +593,7 @@ static int kmb_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id kmb_of_match[] = { +static const struct of_device_id kmb_of_match[] = { {.compatible = "intel,kmb_display"}, {}, }; @@ -627,13 +636,13 @@ static int __maybe_unused kmb_pm_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume); static struct platform_driver kmb_platform_driver = { - .probe = kmb_probe, - .remove = kmb_remove, - .driver = { - .name = "kmb-drm", - .pm = &kmb_pm_ops, - .of_match_table = kmb_of_match, - }, + .probe = kmb_probe, + .remove = kmb_remove, + .driver = { + .name = "kmb-drm", + .pm = &kmb_pm_ops, + .of_match_table = kmb_of_match, + }, }; module_platform_driver(kmb_platform_driver); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index b194139..4916b217 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -30,27 +30,29 @@ #define FCCTEST #define LCD_TEST -#define KMB_MAX_WIDTH 1920 /*max width in pixels */ -#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ +#define KMB_MAX_WIDTH 1920 /*max width in pixels */ +#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ #define KMB_LCD_DEFAULT_CLK 250000000 #define KMB_MIPI_DEFAULT_CLK 24000000 #define KMB_MIPI_DEFAULT_CFG_CLK 24000000 #define KMB_SYS_CLK_MHZ 500 +#define crtc_to_kmb_priv(x) container_of(x, struct kmb_drm_private, crtc) + struct kmb_drm_private { - struct drm_device drm; - void __iomem *lcd_mmio; - void __iomem *mipi_mmio; - void __iomem *msscam_mmio; - unsigned char n_layers; - struct clk *clk; - struct drm_crtc crtc; - struct kmb_plane *plane; - struct drm_atomic_state *state; - spinlock_t irq_lock; - int irq_lcd; - int irq_mipi; - dma_addr_t fb_addr; + struct drm_device drm; + void __iomem *lcd_mmio; + void __iomem *mipi_mmio; + void __iomem *msscam_mmio; + unsigned char n_layers; + struct clk *clk; + struct drm_crtc crtc; + struct kmb_plane *plane; + struct drm_atomic_state *state; + spinlock_t irq_lock; + int irq_lcd; + int irq_mipi; + dma_addr_t fb_addr; }; static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) @@ -58,54 +60,12 @@ static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) return container_of(dev, struct kmb_drm_private, drm); } -#define crtc_to_kmb_priv(x) container_of(x, struct kmb_drm_private, crtc) - struct blt_layer_config { unsigned char layer_format; }; -/* - * commenting this out to use hardcoded address for registers - * TODO we may need this later if we decide to get the address from - * the device tree - */ -#ifdef KMB_WRITE -static inline void kmb_write(struct kmb_drm_private *lcd, - unsigned int reg, u32 value) -{ - writel(value, lcd->mmio + reg); -} - -static inline u32 kmb_read(struct kmb_drm_private *lcd, unsigned int reg) -{ - return readl(lcd->mmio + reg); -} - -static inline void kmb_write_bits(struct kmb_drm_private *lcd, - unsigned int reg, u32 offset, u32 num_bits, - u32 value) -{ - u32 reg_val = kmb_read(lcd, reg); - u32 mask = (1 << num_bits) - 1; - - value &= mask; - mask <<= offset; - reg_val &= (~mask); - reg_val |= (value << offset); - writel(reg_val, lcd->mmio + reg); -} -static inline void kmb_write(unsigned int reg, u32 value) -{ - writel(value, reg); -} - -static inline u32 kmb_read(unsigned int reg) -{ - return readl(reg); -} -#endif static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, - unsigned int reg, u32 value) + unsigned int reg, u32 value) { #ifdef LCD_TEST writel(value, (dev_p->lcd_mmio + reg)); @@ -113,25 +73,25 @@ static inline void kmb_write_lcd(struct kmb_drm_private *dev_p, } static inline void kmb_write_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 value) + unsigned int reg, u32 value) { writel(value, (dev_p->mipi_mmio + reg)); } static inline void kmb_write_msscam(struct kmb_drm_private *dev_p, - unsigned int reg, u32 value) + unsigned int reg, u32 value) { writel(value, (dev_p->msscam_mmio + reg)); } static inline u32 kmb_read_msscam(struct kmb_drm_private *dev_p, - unsigned int reg) + unsigned int reg) { return readl(dev_p->msscam_mmio + reg); } static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { u32 reg_val = kmb_read_msscam(dev_p, reg); @@ -147,7 +107,7 @@ static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) } static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { #ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg); @@ -157,7 +117,7 @@ static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p, } static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { #ifdef LCD_TEST u32 reg_val = kmb_read_lcd(dev_p, reg); @@ -172,7 +132,8 @@ static inline u32 kmb_read_mipi(struct kmb_drm_private *dev_p, unsigned int reg) } static inline void kmb_write_bits_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 offset, u32 num_bits, u32 value) + unsigned int reg, u32 offset, + u32 num_bits, u32 value) { u32 reg_val = kmb_read_mipi(dev_p, reg); u32 mask = (1 << num_bits) - 1; @@ -181,11 +142,18 @@ static inline void kmb_write_bits_mipi(struct kmb_drm_private *dev_p, mask <<= offset; reg_val &= (~mask); reg_val |= (value << offset); +#ifdef DEBUG + if (reg == DPHY_FREQ_CTRL0_3 + 4) { + DRM_INFO("%s : %d reg=0x%x offset=%d num_bits=%d val=0x%x\n", + __func__, __LINE__, reg, offset, num_bits, + reg_val); + } +#endif kmb_write_mipi(dev_p, reg, reg_val); } static inline void kmb_set_bit_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 offset) + unsigned int reg, u32 offset) { u32 reg_val = kmb_read_mipi(dev_p, reg); @@ -193,7 +161,7 @@ static inline void kmb_set_bit_mipi(struct kmb_drm_private *dev_p, } static inline void kmb_clr_bit_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 offset) + unsigned int reg, u32 offset) { u32 reg_val = kmb_read_mipi(dev_p, reg); @@ -201,7 +169,7 @@ static inline void kmb_clr_bit_mipi(struct kmb_drm_private *dev_p, } static inline void kmb_set_bitmask_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { u32 reg_val = kmb_read_mipi(dev_p, reg); @@ -209,12 +177,13 @@ static inline void kmb_set_bitmask_mipi(struct kmb_drm_private *dev_p, } static inline void kmb_clr_bitmask_mipi(struct kmb_drm_private *dev_p, - unsigned int reg, u32 mask) + unsigned int reg, u32 mask) { u32 reg_val = kmb_read_mipi(dev_p, reg); kmb_write_mipi(dev_p, reg, (reg_val & (~mask))); } + int kmb_setup_crtc(struct drm_device *dev); void kmb_set_scanout(struct kmb_drm_private *lcd); #endif /* __KMB_DRV_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 3368e97..977fcb8 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -32,6 +32,7 @@ #include <drm/drm_mipi_dsi.h> #include <drm/drm_print.h> #include <drm/drm_bridge.h> +#include <drm/drm_print.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/gpio/consumer.h> @@ -43,56 +44,19 @@ #include <linux/buffer_head.h> static int hw_initialized; -#define IMAGE_PATH "/home/root/1280x720.pnm" //#define MIPI_TX_TEST_PATTERN_GENERATION //#define MIPI_DMA //#define RTL_TEST +//#define DPHY_GET_FSM +//#define MIPI_TX_INIT_IRQS +//#define GET_SYS_CLK +//#define DPHY_READ_TESTCODE +//#define MIPI_TX_HANDLE_IRQS -/*MIPI TX CFG*/ -#define MIPI_TX_LANE_DATA_RATE_MBPS 891 -#define MIPI_TX_REF_CLK_KHZ 24000 -#define MIPI_TX_CFG_CLK_KHZ 24000 -#define MIPI_TX_BPP 24 - -/*DPHY Tx test codes*/ -#define TEST_CODE_FSM_CONTROL 0x03 -#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C -#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E -#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F -#define TEST_CODE_PLL_VCO_CTRL 0x12 -#define TEST_CODE_PLL_GMP_CTRL 0x13 -#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14 -#define TEST_CODE_PLL_LOCK_FILTER 0x15 -#define TEST_CODE_PLL_UNLOCK_FILTER 0x16 -#define TEST_CODE_PLL_INPUT_DIVIDER 0x17 -#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18 -#define PLL_FEEDBACK_DIVIDER_HIGH (1 << 7) -#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 -#define PLL_N_OVR_EN (1 << 4) -#define PLL_M_OVR_EN (1 << 5) -#define TEST_CODE_VOD_LEVEL 0x24 -#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C -#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D -#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 -#define TEST_CODE_PLL_ANALOG_PROG 0x1F -#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 -#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 -#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 - -/* D-Phy params */ -#define PLL_N_MIN 0 -#define PLL_N_MAX 15 -#define PLL_M_MIN 62 -#define PLL_M_MAX 623 -#define PLL_FVCO_MAX 1250 - -#define TIMEOUT 600 static struct mipi_dsi_host *dsi_host; static struct mipi_dsi_device *dsi_device; -/* - * Default setting is 1080p, 4 lanes. - */ +/* Default setting is 1080p, 4 lanes */ #define IMG_HEIGHT_LINES 1080 #define IMG_WIDTH_PX 1920 #define MIPI_TX_ACTIVE_LANES 4 @@ -102,7 +66,6 @@ struct mipi_tx_frame_section_cfg mipi_tx_frame0_sect_cfg = { .height_lines = IMG_HEIGHT_LINES, .data_type = DSI_LP_DT_PPS_RGB888_24B, .data_mode = MIPI_DATA_MODE1, -// .data_mode = MIPI_DATA_MODE0, .dma_packed = 0 }; @@ -152,18 +115,34 @@ struct mipi_ctrl_cfg mipi_tx_init_cfg = { .tx_always_use_hact = 1, .tx_hact_wait_stop = 1, } - }; -u8 *iBuf; - -struct mipi_hs_freq_range_cfg { +struct mipi_hs_freq_range_cfg { uint16_t default_bit_rate_mbps; uint8_t hsfreqrange_code; }; +struct vco_params { + u32 freq; + u32 range; + u32 divider; +}; + +static struct vco_params vco_table[] = { + {52, 0x3f, 8}, + {80, 0x39, 8}, + {105, 0x2f, 4}, + {160, 0x29, 4}, + {210, 0x1f, 2}, + {320, 0x19, 2}, + {420, 0x0f, 1}, + {630, 0x09, 1}, + {1100, 0x03, 1}, + {0xffff, 0x01, 1}, +}; + static struct mipi_hs_freq_range_cfg - mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = { +mipi_hs_freq_range[MIPI_DPHY_DEFAULT_BIT_RATES] = { {.default_bit_rate_mbps = 80, .hsfreqrange_code = 0x00}, {.default_bit_rate_mbps = 90, .hsfreqrange_code = 0x10}, {.default_bit_rate_mbps = 100, .hsfreqrange_code = 0x20}, @@ -245,14 +224,19 @@ static int kmb_dsi_get_modes(struct drm_connector *connector) int num_modes = 0; num_modes = drm_add_modes_noedid(connector, - connector->dev->mode_config.max_width, - connector->dev->mode_config.max_height); + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); + + DRM_INFO("width=%d height=%d\n", + connector->dev->mode_config.max_width, + connector->dev->mode_config.max_height); + DRM_INFO("num modes=%d\n", num_modes); + return num_modes; } void kmb_dsi_host_unregister(void) { - DRM_INFO("%s : %d\n", __func__, __LINE__); mipi_dsi_host_unregister(dsi_host); kfree(dsi_host); } @@ -260,8 +244,6 @@ void kmb_dsi_host_unregister(void) static void kmb_dsi_connector_destroy(struct drm_connector *connector) { struct kmb_connector *kmb_connector = to_kmb_connector(connector); - - DRM_INFO("%s : %d\n", __func__, __LINE__); drm_connector_cleanup(connector); kfree(kmb_connector); } @@ -270,7 +252,6 @@ static void kmb_dsi_encoder_destroy(struct drm_encoder *encoder) { struct kmb_dsi *kmb_dsi = to_kmb_dsi(encoder); - DRM_INFO("%s : %d\n", __func__, __LINE__); if (!kmb_dsi) return; @@ -332,7 +313,6 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, { struct kmb_dsi_host *host; - DRM_INFO("%s : %d\n", __func__, __LINE__); host = kzalloc(sizeof(*host), GFP_KERNEL); if (!host) return NULL; @@ -351,6 +331,9 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) { struct drm_bridge *bridge; +#ifndef FCCTEST + struct device_node *encoder_node; +#endif /* Create and register MIPI DSI host */ if (!dsi_host) { @@ -372,12 +355,11 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) mipi_dsi_host_register(dsi_host); } #ifndef FCCTEST - /* find ADV7535 node and initialize it */ - DRM_INFO("trying to get bridge info %pOF\n", dev->of_node); + /* Find ADV7535 node and initialize it */ encoder_node = of_parse_phandle(dev->of_node, "encoder-slave", 0); - DRM_INFO("encoder node = %pOF\n", encoder_node); + if (!encoder_node) { - DRM_ERROR("failed to get bridge info from DT\n"); + DRM_ERROR("Failed to get bridge info from DT\n"); return ERR_PTR(-EINVAL); } @@ -385,7 +367,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) bridge = of_drm_find_bridge(encoder_node); of_node_put(encoder_node); if (!bridge) { - DRM_INFO("wait for external bridge driver DT\n"); + DRM_INFO("Wait for external bridge driver DT\n"); return ERR_PTR(-EPROBE_DEFER); } #endif @@ -393,21 +375,21 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) } u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, - struct mipi_data_type_params *params) + struct mipi_data_type_params *params) { - struct mipi_data_type_params data_type_parameters; + struct mipi_data_type_params data_type_param; switch (data_type) { case DSI_LP_DT_PPS_YCBCR420_12B: - data_type_parameters.size_constraint_pixels = 2; - data_type_parameters.size_constraint_bytes = 3; + data_type_param.size_constraint_pixels = 2; + data_type_param.size_constraint_bytes = 3; switch (data_mode) { - /* case 0 not supported according to MDK */ + /* Case 0 not supported according to MDK */ case 1: case 2: case 3: - data_type_parameters.pixels_per_pclk = 2; - data_type_parameters.bits_per_pclk = 24; + data_type_param.pixels_per_pclk = 2; + data_type_param.bits_per_pclk = 24; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -415,17 +397,19 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, }; break; case DSI_LP_DT_PPS_YCBCR422_16B: - data_type_parameters.size_constraint_pixels = 2; - data_type_parameters.size_constraint_bytes = 4; + data_type_param.size_constraint_pixels = 2; + data_type_param.size_constraint_bytes = 4; switch (data_mode) { - /* case 0 and 1 not supported according to MDK */ + /* Case 0 and 1 not supported according + * to MDK + */ case 2: - data_type_parameters.pixels_per_pclk = 1; - data_type_parameters.bits_per_pclk = 16; + data_type_param.pixels_per_pclk = 1; + data_type_param.bits_per_pclk = 16; break; case 3: - data_type_parameters.pixels_per_pclk = 2; - data_type_parameters.bits_per_pclk = 32; + data_type_param.pixels_per_pclk = 2; + data_type_param.bits_per_pclk = 32; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -434,15 +418,15 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, break; case DSI_LP_DT_LPPS_YCBCR422_20B: case DSI_LP_DT_PPS_YCBCR422_24B: - data_type_parameters.size_constraint_pixels = 2; - data_type_parameters.size_constraint_bytes = 6; + data_type_param.size_constraint_pixels = 2; + data_type_param.size_constraint_bytes = 6; switch (data_mode) { - /* case 0 not supported according to MDK */ + /* Case 0 not supported according to MDK */ case 1: case 2: case 3: - data_type_parameters.pixels_per_pclk = 1; - data_type_parameters.bits_per_pclk = 24; + data_type_param.pixels_per_pclk = 1; + data_type_param.bits_per_pclk = 24; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -450,18 +434,18 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, }; break; case DSI_LP_DT_PPS_RGB565_16B: - data_type_parameters.size_constraint_pixels = 1; - data_type_parameters.size_constraint_bytes = 2; + data_type_param.size_constraint_pixels = 1; + data_type_param.size_constraint_bytes = 2; switch (data_mode) { case 0: case 1: - data_type_parameters.pixels_per_pclk = 1; - data_type_parameters.bits_per_pclk = 16; + data_type_param.pixels_per_pclk = 1; + data_type_param.bits_per_pclk = 16; break; case 2: case 3: - data_type_parameters.pixels_per_pclk = 2; - data_type_parameters.bits_per_pclk = 32; + data_type_param.pixels_per_pclk = 2; + data_type_param.bits_per_pclk = 32; break; default: DRM_ERROR("DSI: Invalid data_mode %d\n", data_mode); @@ -469,97 +453,104 @@ u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, }; break; case DSI_LP_DT_PPS_RGB666_18B: - data_type_parameters.size_constraint_pixels = 4; - data_type_parameters.size_constraint_bytes = 9; - data_type_parameters.bits_per_pclk = 18; - data_type_parameters.pixels_per_pclk = 1; + data_type_param.size_constraint_pixels = 4; + data_type_param.size_constraint_bytes = 9; + data_type_param.bits_per_pclk = 18; + data_type_param.pixels_per_pclk = 1; break; case DSI_LP_DT_LPPS_RGB666_18B: case DSI_LP_DT_PPS_RGB888_24B: - data_type_parameters.size_constraint_pixels = 1; - data_type_parameters.size_constraint_bytes = 3; - data_type_parameters.bits_per_pclk = 24; - data_type_parameters.pixels_per_pclk = 1; + data_type_param.size_constraint_pixels = 1; + data_type_param.size_constraint_bytes = 3; + data_type_param.bits_per_pclk = 24; + data_type_param.pixels_per_pclk = 1; break; case DSI_LP_DT_PPS_RGB101010_30B: - data_type_parameters.size_constraint_pixels = 4; - data_type_parameters.size_constraint_bytes = 15; - data_type_parameters.bits_per_pclk = 30; - data_type_parameters.pixels_per_pclk = 1; + data_type_param.size_constraint_pixels = 4; + data_type_param.size_constraint_bytes = 15; + data_type_param.bits_per_pclk = 30; + data_type_param.pixels_per_pclk = 1; break; - default: DRM_ERROR("DSI: Invalid data_type %d\n", data_type); return -EINVAL; - } + }; - *params = data_type_parameters; + *params = data_type_param; return 0; } static u32 compute_wc(u32 width_px, u8 size_constr_p, u8 size_constr_b) { - /* calculate the word count for each long packet */ + /* Calculate the word count for each long packet */ return (((width_px / size_constr_p) * size_constr_b) & 0xffff); } static u32 compute_unpacked_bytes(u32 wc, u8 bits_per_pclk) { - /*number of PCLK cycles needed to transfer a line */ - /* with each PCLK cycle, 4 Bytes are sent through the PPL module */ + /* Number of PCLK cycles needed to transfer a line + * with each PCLK cycle, 4 Bytes are sent through the PPL module + */ return ((wc * 8) / bits_per_pclk) * 4; } static u32 mipi_tx_fg_section_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_id, - u8 section, u32 height_lines, - u32 unpacked_bytes, + u8 frame_id, u8 section, + u32 height_lines, u32 unpacked_bytes, struct mipi_tx_frame_sect_phcfg *ph_cfg) { u32 cfg = 0; u32 ctrl_no = MIPI_CTRL6; u32 reg_adr; - /*frame section packet header */ - /*word count */ - cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; /* bits [15:0] */ - /*data type */ + /* Frame section packet header */ + /* Word count bits [15:0] */ + cfg = (ph_cfg->wc & MIPI_TX_SECT_WC_MASK) << 0; + + /* Data type (bits [21:16]) */ cfg |= ((ph_cfg->data_type & MIPI_TX_SECT_DT_MASK) - << MIPI_TX_SECT_DT_SHIFT); /* bits [21:16] */ - /* virtual channel */ + << MIPI_TX_SECT_DT_SHIFT); + + /* Virtual channel (bits [23:22]) */ cfg |= ((ph_cfg->vchannel & MIPI_TX_SECT_VC_MASK) - << MIPI_TX_SECT_VC_SHIFT); /* bits [23:22] */ - /* data mode */ + << MIPI_TX_SECT_VC_SHIFT); + + /* Data mode (bits [24:25]) */ cfg |= ((ph_cfg->data_mode & MIPI_TX_SECT_DM_MASK) - << MIPI_TX_SECT_DM_SHIFT); /* bits [24:25]*/ + << MIPI_TX_SECT_DM_SHIFT); if (ph_cfg->dma_packed) cfg |= MIPI_TX_SECT_DMA_PACKED; - DRM_INFO("%s : %d ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n", - __func__, __LINE__, ctrl_no, frame_id, section, cfg, - ph_cfg->dma_packed); - kmb_write_mipi(dev_p, (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, - section)), cfg); - - /*unpacked bytes */ - /*there are 4 frame generators and each fg has 4 sections - *there are 2 registers for unpacked bytes - - *# bytes each section occupies in memory - *REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 - *REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 + + DRM_DEBUG("ctrl=%d frame_id=%d section=%d cfg=%x packed=%d\n", + ctrl_no, frame_id, section, cfg, ph_cfg->dma_packed); + kmb_write_mipi(dev_p, + (MIPI_TXm_HS_FGn_SECTo_PH(ctrl_no, frame_id, section)), + cfg); + + /* Unpacked bytes */ + + /* There are 4 frame generators and each fg has 4 sections + * There are 2 registers for unpacked bytes (# bytes each + * section occupies in memory) + * REG_UNPACKED_BYTES0: [15:0]-BYTES0, [31:16]-BYTES1 + * REG_UNPACKED_BYTES1: [15:0]-BYTES2, [31:16]-BYTES3 */ - reg_adr = MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, frame_id) - + (section / 2) * 4; + reg_adr = + MIPI_TXm_HS_FGn_SECT_UNPACKED_BYTES0(ctrl_no, + frame_id) + (section / 2) * 4; kmb_write_bits_mipi(dev_p, reg_adr, (section % 2) * 16, 16, unpacked_bytes); + DRM_DEBUG("unpacked_bytes = %d, wordcount = %d\n", unpacked_bytes, + ph_cfg->wc); - /* line config */ + /* Line config */ reg_adr = MIPI_TXm_HS_FGn_SECTo_LINE_CFG(ctrl_no, frame_id, section); kmb_write_mipi(dev_p, reg_adr, height_lines); return 0; } -static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, - u8 section, +static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, + u8 frame_id, u8 section, struct mipi_tx_frame_section_cfg *frame_scfg, u32 *bits_per_pclk, u32 *wc) { @@ -573,8 +564,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, &data_type_parameters); if (ret) return ret; - /* - * packet width has to be a multiple of the minimum packet width + + /* Packet width has to be a multiple of the minimum packet width * (in pixels) set for each data type */ if (frame_scfg->width_pixels % @@ -584,10 +575,8 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, *wc = compute_wc(frame_scfg->width_pixels, data_type_parameters.size_constraint_pixels, data_type_parameters.size_constraint_bytes); - - unpacked_bytes = - compute_unpacked_bytes(*wc, data_type_parameters.bits_per_pclk); - + unpacked_bytes = compute_unpacked_bytes(*wc, + data_type_parameters.bits_per_pclk); ph_cfg.wc = *wc; ph_cfg.data_mode = frame_scfg->data_mode; ph_cfg.data_type = frame_scfg->data_type; @@ -598,88 +587,94 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_drm_private *dev_p, u8 frame_id, frame_scfg->height_lines, unpacked_bytes, &ph_cfg); - /*caller needs bits_per_clk for additional caluclations */ + /* Caller needs bits_per_clk for additional caluclations */ *bits_per_pclk = data_type_parameters.bits_per_pclk; + return 0; } -static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, - u8 frame_gen, +static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, u8 frame_gen, struct mipi_tx_frame_timing_cfg *fg_cfg) { u32 sysclk; - /*float ppl_llp_ratio; */ u32 ppl_llp_ratio; u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset; - /*Get system clock for blanking period cnfigurations */ - /*TODO need to get system clock from clock driver */ - /* 500 Mhz system clock minus 50 - to account for the difference in - * mipi clock speed in RTL tests +#ifdef GET_SYS_CLK + /* Get system clock for blanking period cnfigurations */ + sc = get_clock_frequency(CPR_CLK_SYSTEM, &sysclk); + if (sc) + return sc; + + /* Convert to MHZ */ + sysclk /= 1000; +#else + /* 500 Mhz system clock minus 50 to account for the difference in + * MIPI clock speed in RTL tests */ sysclk = KMB_SYS_CLK_MHZ - 50; -// sysclk = KMB_SYS_CLK_MHZ; +#endif - /*ppl-pixel packing layer, llp-low level protocol - * frame genartor timing parameters are clocked on the system clock + /* PPL-Pixel Packing Layer, LLP-Low Level Protocol + * Frame genartor timing parameters are clocked on the system clock, * whereas as the equivalent parameters in the LLP blocks are clocked * on LLP Tx clock from the D-PHY - BYTE clock */ - /*multiply by 1000 to keep the precision */ + /* Multiply by 1000 to maintain precision */ ppl_llp_ratio = ((fg_cfg->bpp / 8) * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); - DRM_INFO("%s : %d bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n", - __func__, __LINE__, fg_cfg->bpp, sysclk, - fg_cfg->lane_rate_mbps, fg_cfg->active_lanes); + DRM_INFO("ppl_llp_ratio=%d\n", ppl_llp_ratio); + DRM_INFO("bpp=%d sysclk=%d lane-rate=%d activ-lanes=%d\n", + fg_cfg->bpp, sysclk, fg_cfg->lane_rate_mbps, + fg_cfg->active_lanes); - DRM_INFO("%s : %d ppl_llp_ratio=%d\n", __func__, __LINE__, - ppl_llp_ratio); - /*frame generator number of lines*/ + /* Frame generator number of lines */ reg_adr = MIPI_TXm_HS_FGn_NUM_LINES(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, fg_cfg->v_active); - /*vsync width */ - /* - *there are 2 registers for vsync width -VSA in lines for channels 0-3 - *REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 - *REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 + /* vsync width + * There are 2 registers for vsync width (VSA in lines for + * channels 0-3) + * REG_VSYNC_WIDTH0: [15:0]-VSA for channel0, [31:16]-VSA for channel1 + * REG_VSYNC_WIDTH1: [15:0]-VSA for channel2, [31:16]-VSA for channel3 */ offset = (frame_gen % 2) * 16; reg_adr = MIPI_TXm_HS_VSYNC_WIDTHn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->vsync_width); - /*v backporch - same register config like vsync width */ + /* vertical backporch (vbp) */ reg_adr = MIPI_TXm_HS_V_BACKPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_backporch); - /*v frontporch - same register config like vsync width */ + /* vertical frontporch (vfp) */ reg_adr = MIPI_TXm_HS_V_FRONTPORCHESn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_frontporch); - /*v active - same register config like vsync width */ + /* vertical active (vactive) */ reg_adr = MIPI_TXm_HS_V_ACTIVEn(ctrl_no, frame_gen / 2); kmb_write_bits_mipi(dev_p, reg_adr, offset, 16, fg_cfg->v_active); - /*hsyc width */ + /* hsync width */ reg_adr = MIPI_TXm_HS_HSYNC_WIDTHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, (fg_cfg->hsync_width * ppl_llp_ratio) / 1000); - /*h backporch */ + /* horizontal backporch (hbp) */ reg_adr = MIPI_TXm_HS_H_BACKPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, (fg_cfg->h_backporch * ppl_llp_ratio) / 1000); - /*h frontporch */ + /* horizontal frontporch (hfp) */ reg_adr = MIPI_TXm_HS_H_FRONTPORCHn(ctrl_no, frame_gen); kmb_write_mipi(dev_p, reg_adr, (fg_cfg->h_frontporch * ppl_llp_ratio) / 1000); - /*h active */ + /* horizontal active (ha) */ reg_adr = MIPI_TXm_HS_H_ACTIVEn(ctrl_no, frame_gen); - /*convert h_active which is wc in bytes to cycles */ + + /* convert h_active which is wc in bytes to cycles */ val = (fg_cfg->h_active * sysclk * 1000) / ((fg_cfg->lane_rate_mbps / 8) * fg_cfg->active_lanes); val /= 1000; @@ -706,8 +701,8 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, u32 i, fg_num_lines = 0; struct mipi_tx_frame_timing_cfg fg_t_cfg; - /*calculate the total frame generator number of lines based on it's - * active sections + /* Calculate the total frame generator number of + * lines based on it's active sections */ for (i = 0; i < MIPI_TX_FRAME_GEN_SECTIONS; i++) { if (fg_cfg->sections[i] != NULL) @@ -726,7 +721,7 @@ static void mipi_tx_fg_cfg(struct kmb_drm_private *dev_p, u8 frame_gen, fg_t_cfg.v_active = fg_num_lines; fg_t_cfg.active_lanes = active_lanes; - /*apply frame generator timing setting */ + /* Apply frame generator timing setting */ mipi_tx_fg_cfg_regs(dev_p, frame_gen, &fg_t_cfg); } @@ -736,7 +731,7 @@ static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, u32 fifo_size, fifo_rthreshold; u32 ctrl_no = MIPI_CTRL6; - /*clear all mc fifo channel sizes and thresholds */ + /* Clear all mc fifo channel sizes and thresholds */ kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CTRL_EN, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC0, 0); kmb_write_mipi(dev_p, MIPI_TX_HS_MC_FIFO_CHAN_ALLOC1, 0); @@ -746,18 +741,18 @@ static void mipi_tx_multichannel_fifo_cfg(struct kmb_drm_private *dev_p, fifo_size = ((active_lanes > MIPI_D_LANES_PER_DPHY) ? MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC : MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC) - 1; - /*MC fifo size for virtual channels 0-3 */ - /* - *REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 - *REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 + + /* MC fifo size for virtual channels 0-3 + * REG_MC_FIFO_CHAN_ALLOC0: [8:0]-channel0, [24:16]-channel1 + * REG_MC_FIFO_CHAN_ALLOC1: [8:0]-2, [24:16]-channel3 */ SET_MC_FIFO_CHAN_ALLOC(dev_p, ctrl_no, vchannel_id, fifo_size); - /*set threshold to half the fifo size, actual size=size*16 */ + /* Set threshold to half the fifo size, actual size=size*16 */ fifo_rthreshold = ((fifo_size) * 8) & BIT_MASK_16; SET_MC_FIFO_RTHRESHOLD(dev_p, ctrl_no, vchannel_id, fifo_rthreshold); - /*enable the MC FIFO channel corresponding to the Virtual Channel */ + /* Enable the MC FIFO channel corresponding to the Virtual Channel */ kmb_set_bit_mipi(dev_p, MIPI_TXm_HS_MC_FIFO_CTRL_EN(ctrl_no), vchannel_id); } @@ -768,7 +763,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6; - /*MIPI_TX_HS_SYNC_CFG */ + /* MIPI_TX_HS_SYNC_CFG */ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) @@ -789,22 +784,29 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, sync_cfg |= DSI_LPM_FIRST_VSA_LINE; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) sync_cfg |= DSI_LPM_LAST_VFP_LINE; - /* enable frame generator */ + + /* Enable frame generator */ fg_en = 1 << fg_id; sync_cfg |= FRAME_GEN_EN(fg_en); + if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) sync_cfg |= ALWAYS_USE_HACT(fg_en); if (ctrl_cfg->tx_ctrl_cfg.tx_hact_wait_stop) sync_cfg |= HACT_WAIT_STOP(fg_en); - /* MIPI_TX_HS_CTRL*/ - ctrl = HS_CTRL_EN | TX_SOURCE; /* type:DSI,source:LCD */ + DRM_DEBUG("sync_cfg=%d fg_en=%d\n", sync_cfg, fg_en); + + /* MIPI_TX_HS_CTRL */ + + /* type:DSI, source:LCD */ + ctrl = HS_CTRL_EN | TX_SOURCE; + ctrl |= LCD_VC(fg_id); + ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->eotp_en) ctrl |= DSI_EOTP_EN; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blank_en) ctrl |= DSI_CMD_HFP_EN; - ctrl |= LCD_VC(fg_id); - ctrl |= ACTIVE_LANES(ctrl_cfg->active_lanes - 1); + /*67 ns stop time */ ctrl |= HSEXIT_CNT(0x43); @@ -818,14 +820,10 @@ static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, u32 color1, u32 ctrl_no) { int val = 0; + /* Select test pattern mode on the virtual channel */ val = TP_SEL_VCm(vc, tp_sel); - if (tp_sel == MIPI_TX_HS_TP_V_STRIPES || - tp_sel == MIPI_TX_HS_TP_H_STRIPES) { - val |= TP_STRIPE_WIDTH(stripe_width); - } - /* Configure test pattern colors */ kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR0(ctrl_no), color0); kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_COLOR1(ctrl_no), color1); @@ -833,6 +831,7 @@ static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, /* Enable test pattern generation on the virtual channel */ val |= TP_EN_VCm(vc); kmb_write_mipi(dev_p, MIPI_TXm_HS_TEST_PAT_CTRL(ctrl_no), val); + } #endif @@ -844,31 +843,33 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, u8 frame_id, sect; u32 bits_per_pclk = 0; u32 word_count = 0; - - /*This is the order in which mipi tx needs to be initialized - * set frame section parameters - * set frame specific parameters - * connect lcd to mipi - * multi channel fifo cfg - * set mipitxcctrlcfg + struct mipi_tx_frame_cfg *frame; + + /* This is the order to initialize MIPI TX: + * 1. set frame section parameters + * 2. set frame specific parameters + * 3. connect lcd to mipi + * 4. multi channel fifo cfg + * 5. set mipitxcctrlcfg */ for (frame_id = 0; frame_id < 4; frame_id++) { - /* find valid frame, assume only one valid frame */ - if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id] == NULL) + frame = ctrl_cfg->tx_ctrl_cfg.frames[frame_id]; + + /* Find valid frame, assume only one valid frame */ + if (frame == NULL) continue; /* Frame Section configuration */ - /*TODO - assume there is only one valid section in a frame, so - * bits_per_pclk and word_count are only set once + /* TODO - assume there is only one valid section in a frame, + * so bits_per_pclk and word_count are only set once */ for (sect = 0; sect < MIPI_CTRL_VIRTUAL_CHANNELS; sect++) { - if (ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect] - == NULL) + if (frame->sections[sect] == NULL) continue; ret = mipi_tx_fg_section_cfg(dev_p, frame_id, sect, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]->sections[sect], + frame->sections[sect], &bits_per_pclk, &word_count); if (ret) @@ -876,30 +877,39 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, } - /* set frame specific parameters */ + /* Set frame specific parameters */ mipi_tx_fg_cfg(dev_p, frame_id, ctrl_cfg->active_lanes, - bits_per_pclk, - word_count, ctrl_cfg->lane_rate_mbps, - ctrl_cfg->tx_ctrl_cfg.frames[frame_id]); + bits_per_pclk, word_count, + ctrl_cfg->lane_rate_mbps, frame); active_vchannels++; - /*stop iterating as only one virtual channel shall be used for - * LCD connection + /* Stop iterating as only one virtual channel + * shall be used for LCD connection */ break; } if (active_vchannels == 0) return -EINVAL; - /*Multi-Channel FIFO Configuration */ + /* Multi-Channel FIFO Configuration */ mipi_tx_multichannel_fifo_cfg(dev_p, ctrl_cfg->active_lanes, frame_id); - /*Frame Generator Enable */ + /* Frame Generator Enable */ mipi_tx_ctrl_cfg(dev_p, frame_id, ctrl_cfg); + +#ifdef MIPI_TX_TEST_PATTERN_GENERATION + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, + 0x8, 0xff, 0xff00, MIPI_CTRL6); +#endif + + DRM_DEBUG("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); + return ret; } +#ifdef DPHY_READ_TESTCODE int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, int test_code) { @@ -914,17 +924,17 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, reg_wr_data = 0; reg_rd_data = 0; - if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == - 1) | ((dphy_sel >> 8 & 0x1) == 1)) + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) reg_wr_data |= data << 0; - if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == - 1) | ((dphy_sel >> 9 & 0x1) == 1)) + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) reg_wr_data |= data << 8; - if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == - 1) | ((dphy_sel >> 10 & 0x1) == 1)) + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) reg_wr_data |= data << 16; - if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == - 1) | ((dphy_sel >> 11 & 0x1) == 1)) + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) reg_wr_data |= data << 24; if ((dphy_sel >> 0 & 0xf) > 0) @@ -947,17 +957,18 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, data = test_code >> 8 & 0xf; reg_wr_data = 0; - if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == - 1) | ((dphy_sel >> 8 & 0x1) == 1)) + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) reg_wr_data |= data << 0; - if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == - 1) | ((dphy_sel >> 9 & 0x1) == 1)) + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) reg_wr_data |= data << 8; - if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == - 1) | ((dphy_sel >> 10 & 0x1) == 1)) + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) reg_wr_data |= data << 16; - if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == - 1) | ((dphy_sel >> 11 & 0x1) == 1)) + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) reg_wr_data |= data << 24; if ((dphy_sel >> 0 & 0xf) > 0) @@ -973,17 +984,18 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, data = test_code & 0xff; reg_wr_data = 0; - if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == - 1) | ((dphy_sel >> 8 & 0x1) == 1)) + + if (((dphy_sel >> 0 & 0x1) == 1) | ((dphy_sel >> 4 & 0x1) == 1) | + ((dphy_sel >> 8 & 0x1) == 1)) reg_wr_data |= data << 0; - if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == - 1) | ((dphy_sel >> 9 & 0x1) == 1)) + if (((dphy_sel >> 1 & 0x1) == 1) | ((dphy_sel >> 5 & 0x1) == 1) | + ((dphy_sel >> 9 & 0x1) == 1)) reg_wr_data |= data << 8; - if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == - 1) | ((dphy_sel >> 10 & 0x1) == 1)) + if (((dphy_sel >> 2 & 0x1) == 1) | ((dphy_sel >> 6 & 0x1) == 1) | + ((dphy_sel >> 10 & 0x1) == 1)) reg_wr_data |= data << 16; - if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == - 1) | ((dphy_sel >> 11 & 0x1) == 1)) + if (((dphy_sel >> 3 & 0x1) == 1) | ((dphy_sel >> 7 & 0x1) == 1) | + ((dphy_sel >> 11 & 0x1) == 1)) reg_wr_data |= data << 24; if ((dphy_sel >> 0 & 0xf) > 0) @@ -1025,20 +1037,16 @@ int dphy_read_testcode(struct kmb_drm_private *dev_p, int dphy_sel, data = reg_rd_data >> 24; return data; - } +#endif static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, u32 test_code, u32 test_data) { -#ifdef DEBUG if (test_code != TEST_CODE_FSM_CONTROL) - DRM_INFO("test_code = %02x, test_data = %08x\n", test_code, + DRM_DEBUG("test_code = %02x, test_data = %08x\n", test_code, test_data); -#endif - - /* send the test code first */ - /* Steps for code: + /* Steps to send test code: * - set testclk HIGH * - set testdin with test code * - set testen HIGH @@ -1061,14 +1069,14 @@ static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, /* Set testen low */ CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); - /* Send the test data next */ - /* Steps for data: - * - set testen LOW - * - set testclk LOW - * - set testdin with data - * - set testclk HIGH - */ if (test_code) { + /* Steps to send test data: + * - set testen LOW + * - set testclk LOW + * - set testdin with data + * - set testclk HIGH + */ + /* Set testen low */ CLR_DPHY_TEST_CTRL1_EN(dev_p, dphy_no); @@ -1085,59 +1093,36 @@ static void test_mode_send(struct kmb_drm_private *dev_p, u32 dphy_no, } } -static inline void - set_test_mode_src_osc_freq_target_low_bits(struct kmb_drm_private +static inline void set_test_mode_src_osc_freq_target_low_bits(struct + kmb_drm_private *dev_p, u32 dphy_no, u32 freq) { - /*typical rise/fall time=166, - * refer Table 1207 databook,sr_osc_freq_target[7:0 + /* Typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[7:0] */ - test_mode_send(dev_p, dphy_no, - TEST_CODE_SLEW_RATE_DDL_CYCLES, (freq & 0x7f)); -} - -static inline void -set_test_mode_slew_rate_calib_en(struct kmb_drm_private *dev_p, u32 dphy_no) -{ - /*do not bypass slew rate calibration algorithm */ - /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ - test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_OVERRIDE_CTRL, - (0x03 | (1 << 6))); + test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, + (freq & 0x7f)); } -static inline void -set_test_mode_src_osc_freq_target_hi_bits(struct kmb_drm_private *dev_p, - u32 dphy_no, u32 freq) +static inline void set_test_mode_src_osc_freq_target_hi_bits(struct + kmb_drm_private + *dev_p, + u32 dphy_no, + u32 freq) { u32 data; - /*typical rise/fall time=166, refer Table 1207 databook, - * sr_osc_freq_target[11:7 + + /* Flag this as high nibble */ + data = ((freq >> 6) & 0x1f) | (1 << 7); + + /* Typical rise/fall time=166, refer Table 1207 databook, + * sr_osc_freq_target[11:7] */ - data = ((freq >> 6) & 0x1f) | (1 << 7); /*flag this as high nibble */ test_mode_send(dev_p, dphy_no, TEST_CODE_SLEW_RATE_DDL_CYCLES, data); } -struct vco_params { - u32 freq; - u32 range; - u32 divider; -}; - -static struct vco_params vco_table[] = { - {52, 0x3f, 8}, - {80, 0x39, 8}, - {105, 0x2f, 4}, - {160, 0x29, 4}, - {210, 0x1f, 2}, - {320, 0x19, 2}, - {420, 0x0f, 1}, - {630, 0x09, 1}, - {1100, 0x03, 1}, - {0xffff, 0x01, 1}, -}; - static void mipi_tx_get_vco_params(struct vco_params *vco) { int i; @@ -1148,12 +1133,17 @@ static void mipi_tx_get_vco_params(struct vco_params *vco) return; } } + WARN_ONCE(1, "Invalid vco freq = %u for PLL setup\n", vco->freq); } static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, u32 ref_clk_mhz, u32 target_freq_mhz) { + u32 best_n = 0, best_m = 0; + u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq; + u32 best_freq_delta = 3000; + /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz * Fvco: - valid range: 320~1250 MHz (Gen3 D-PHY) * Fout: - valid range: 40~1250 MHz (Gen3 D-PHY) @@ -1171,35 +1161,37 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, .range = 0, .divider = 1, }; - u32 best_n = 0, best_m = 0; - u32 n = 0, m = 0, div = 0, delta, freq = 0, t_freq; - u32 best_freq_delta = 3000; vco_p.freq = target_freq_mhz; mipi_tx_get_vco_params(&vco_p); - /*search pll n parameter */ + + /* Search pll n parameter */ for (n = PLL_N_MIN; n <= PLL_N_MAX; n++) { - /*calculate the pll input frequency division ratio + /* Calculate the pll input frequency division ratio * multiply by 1000 for precision - * no floating point, add n for rounding */ div = ((ref_clk_mhz * 1000) + n) / (n + 1); - /*found a valid n parameter */ + + /* Found a valid n parameter */ if ((div < 2000 || div > 8000)) continue; - /*search pll m parameter */ + + /* Search pll m parameter */ for (m = PLL_M_MIN; m <= PLL_M_MAX; m++) { - /*calculate the Fvco(DPHY PLL output frequency) + /* Calculate the Fvco(DPHY PLL output frequency) * using the current n,m params */ freq = div * (m + 2); freq /= 1000; - /* trim the potential pll freq to max supported */ + + /* Trim the potential pll freq to max supported */ if (freq > PLL_FVCO_MAX) continue; delta = abs(freq - target_freq_mhz); - /*select the best (closest to target pll freq) + + /* Select the best (closest to target pll freq) * n,m parameters so far */ if (delta < best_freq_delta) { @@ -1210,212 +1202,235 @@ static void mipi_tx_pll_setup(struct kmb_drm_private *dev_p, u32 dphy_no, } } - /*Program vco_cntrl parameter - *PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr, + /* Program vco_cntrl parameter + * PLL_VCO_Control[5:0] = pll_vco_cntrl_ovr, * PLL_VCO_Control[6] = pll_vco_cntrl_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_VCO_CTRL, (vco_p.range | (1 << 6))); - /*Program m, n pll parameters */ + /* Program m, n pll parameters */ + DRM_INFO("m = %d n = %d\n", best_m, best_n); - DRM_INFO("%s : %d m = %d n = %d\n", __func__, __LINE__, best_m, best_n); - - /*PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ + /* PLL_Input_Divider_Ratio[3:0] = pll_n_ovr */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INPUT_DIVIDER, (best_n & 0x0f)); - /* m - low nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[4:0] */ + /* m - low nibble PLL_Loop_Divider_Ratio[4:0] + * pll_m_ovr[4:0] + */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, (best_m & 0x1f)); - /*m -high nibble PLL_Loop_Divider_Ratio[4:0] = pll_m_ovr[9:5] */ + /* m - high nibble PLL_Loop_Divider_Ratio[4:0] + * pll_m_ovr[9:5] + */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_FEEDBACK_DIVIDER, ((best_m >> 5) & 0x1f) | PLL_FEEDBACK_DIVIDER_HIGH); - /*enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en */ + /* Enable overwrite of n,m parameters :pll_n_ovr_en, pll_m_ovr_en */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_OUTPUT_CLK_SEL, (PLL_N_OVR_EN | PLL_M_OVR_EN)); - /*Program Charge-Pump parameters */ + /* Program Charge-Pump parameters */ - /*pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ + /* pll_prop_cntrl-fixed values for prop_cntrl from DPHY doc */ t_freq = target_freq_mhz * vco_p.divider; test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL, ((t_freq > 1150) ? 0x0C : 0x0B)); - /*pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ + /* pll_int_cntrl-fixed value for int_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL, 0x00); - /*pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ + /* pll_gmp_cntrl-fixed value for gmp_cntrl from DPHY doci */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_GMP_CTRL, 0x10); - /*pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ + /* pll_cpbias_cntrl-fixed value for cpbias_cntrl from DPHY doc */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_CHARGE_PUMP_BIAS, 0x10); - /*pll_th1 -Lock Detector Phase error threshold, document gives fixed - * value + /* pll_th1 -Lock Detector Phase error threshold, + * document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_PHASE_ERR_CTRL, 0x02); - /*PLL Lock Configuration */ + /* PLL Lock Configuration */ - /*pll_th2 - Lock Filter length, document gives fixed value */ + /* pll_th2 - Lock Filter length, document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_FILTER, 0x60); - /*pll_th3- PLL Unlocking filter, document gives fixed value */ + /* pll_th3- PLL Unlocking filter, document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_UNLOCK_FILTER, 0x03); - /*pll_lock_sel-PLL Lock Detector Selection, document gives - * fixed value + /* pll_lock_sel-PLL Lock Detector Selection, + * document gives fixed value */ test_mode_send(dev_p, dphy_no, TEST_CODE_PLL_LOCK_DETECTOR, 0x02); } +#ifdef DPHY_GET_FSM +static void dphy_get_fsm(struct kmb_drm_private *dev_p, u32 dphy_no) +{ + test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); + + DRM_INFO("dphy %d fsm_state = 0%x\n", dphy_no, + kmb_read_mipi(dev_p, DPHY_TEST_DOUT4_7)); +} +#endif + static void dphy_init_sequence(struct kmb_drm_private *dev_p, struct mipi_ctrl_cfg *cfg, u32 dphy_no, int active_lanes, enum dphy_mode mode) { - u32 test_code = 0; - u32 test_data = 0, val; + u32 test_code = 0, test_data = 0, val; int i = 0; - /* deassert SHUTDOWNZ signal */ - DRM_INFO("%s : %d MIPI_DPHY_STAT0_4_7 = 0x%x)\n", __func__, __LINE__, - kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); - /*Set D-PHY in shutdown mode */ - /*assert RSTZ signal */ + DRM_INFO("dphy=%d mode=%d active_lanes=%d\n", dphy_no, mode, + active_lanes); + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + + /* Set D-PHY in shutdown mode */ + /* Assert RSTZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); - /* assert SHUTDOWNZ signal */ + + /* Assert SHUTDOWNZ signal */ CLR_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); - DRM_INFO("%s : %d DPHY_INIT_CTRL0 = 0x%x\n", __func__, __LINE__, val); - /*Init D-PHY_n */ - /*Pulse testclear signal to make sure the d-phy configuration starts - * from a clean base + DRM_INFO("DPHY_INIT_CTRL0 = 0x%x\n", val); + + /* Init D-PHY_n + * Pulse testclear signal to make sure the d-phy configuration + * starts from a clean base */ CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); ndelay(15); SET_DPHY_TEST_CTRL0(dev_p, dphy_no); - /*TODO may need to add 15ns delay here */ ndelay(15); CLR_DPHY_TEST_CTRL0(dev_p, dphy_no); - val = kmb_read_mipi(dev_p, DPHY_TEST_CTRL0); - DRM_INFO("%s : %d DPHY_TEST_CTRL0 = 0x%x\n", __func__, __LINE__, val); ndelay(15); - /*Set mastermacro bit - Master or slave mode */ + DRM_DEBUG("DPHY_TEST_CTRL0=0x%x\n", + kmb_read_mipi(dev_p, DPHY_TEST_CTRL0)); + + /* Set mastermacro bit - Master or slave mode */ test_code = TEST_CODE_MULTIPLE_PHY_CTRL; - /*DPHY has its own clock lane enabled (master) */ + + /* DPHY has its own clock lane enabled (master) */ if (mode == MIPI_DPHY_MASTER) test_data = 0x01; else test_data = 0x00; - /*send the test code and data */ + /* Send the test code and data */ test_mode_send(dev_p, dphy_no, test_code, test_data); - /*Set the lane data rate */ + + /* Set the lane data rate */ for (i = 0; i < MIPI_DPHY_DEFAULT_BIT_RATES; i++) { if (mipi_hs_freq_range[i].default_bit_rate_mbps < cfg->lane_rate_mbps) continue; - /* send the test code and data */ - /*bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ + + /* Send the test code and data */ + /* bit[6:0] = hsfreqrange_ovr bit[7] = hsfreqrange_ovr_en */ test_code = TEST_CODE_HS_FREQ_RANGE_CFG; - test_data = - (mipi_hs_freq_range[i].hsfreqrange_code & 0x7f) | (1 << 7); + test_data = (mipi_hs_freq_range[i].hsfreqrange_code & 0x7f) | + (1 << 7); test_mode_send(dev_p, dphy_no, test_code, test_data); break; } - /* - * High-Speed Tx Slew Rate Calibration + + /* High-Speed Tx Slew Rate Calibration * BitRate: > 1.5 Gbps && <= 2.5 Gbps: slew rate control OFF */ if (cfg->lane_rate_mbps > 1500) { - /*bypass slew rate calibration algorithm */ - /*bits[1:0} srcal_en_ovr_en, srcal_en_ovr */ + /* Bypass slew rate calibration algorithm + * bits[1:0} srcal_en_ovr_en, srcal_en_ovr + */ test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; test_data = 0x02; test_mode_send(dev_p, dphy_no, test_code, test_data); - /* disable slew rate calibration */ + /* Disable slew rate calibration */ test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; test_data = 0x00; test_mode_send(dev_p, dphy_no, test_code, test_data); } else if (cfg->lane_rate_mbps > 1000) { - /*BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON + /* BitRate: > 1 Gbps && <= 1.5 Gbps: - slew rate control ON * typical rise/fall times: 166 ps */ - /*do not bypass slew rate calibration algorithm */ - /*bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range */ + /* Do not bypass slew rate calibration algorithm + * bits[1:0}=srcal_en_ovr_en, srcal_en_ovr, bit[6]=sr_range + */ test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; test_data = (0x03 | (1 << 6)); test_mode_send(dev_p, dphy_no, test_code, test_data); -// set_test_mode_slew_rate_calib_en(dev_p, dphy_no); - - /* enable slew rate calibration */ + /* Enable slew rate calibration */ test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; test_data = 0x01; test_mode_send(dev_p, dphy_no, test_code, test_data); - /*set sr_osc_freq_target[6:0] */ - /*typical rise/fall time=166, refer Table 1207 databook */ - /*typical rise/fall time=166, refer Table 1207 databook, - * sr_osc_freq_target[7:0 + /* Set sr_osc_freq_target[6:0] low nibble + * typical rise/fall time=166, refer Table 1207 databook */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; test_data = (0x72f & 0x7f); test_mode_send(dev_p, dphy_no, test_code, test_data); - /*set sr_osc_freq_target[11:7] */ - /*typical rise/fall time=166, refer Table 1207 databook, - * sr_osc_freq_target[11:7 + + /* Set sr_osc_freq_target[11:7] high nibble + * Typical rise/fall time=166, refer Table 1207 databook */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; - /*flag this as high nibble */ test_data = ((0x72f >> 6) & 0x1f) | (1 << 7); test_mode_send(dev_p, dphy_no, test_code, test_data); } else { - /*lane_rate_mbps <= 1000 Mbps */ - /*BitRate: <= 1 Gbps: + /* lane_rate_mbps <= 1000 Mbps + * BitRate: <= 1 Gbps: * - slew rate control ON * - typical rise/fall times: 225 ps */ - /*do not bypass slew rate calibration algorithm */ + /* Do not bypass slew rate calibration algorithm */ test_code = TEST_CODE_SLEW_RATE_OVERRIDE_CTRL; test_data = (0x03 | (1 << 6)); test_mode_send(dev_p, dphy_no, test_code, test_data); - /* enable slew rate calibration */ + /* Enable slew rate calibration */ test_code = TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL; test_data = 0x01; test_mode_send(dev_p, dphy_no, test_code, test_data); - /*typical rise/fall time=255, refer Table 1207 databook */ + /* Typical rise/fall time=255, refer Table 1207 databook */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; test_data = (0x523 & 0x7f); test_mode_send(dev_p, dphy_no, test_code, test_data); - /*set sr_osc_freq_target[11:7] */ + /* Set sr_osc_freq_target[11:7] high nibble */ test_code = TEST_CODE_SLEW_RATE_DDL_CYCLES; - /*flag this as high nibble */ test_data = ((0x523 >> 6) & 0x1f) | (1 << 7); test_mode_send(dev_p, dphy_no, test_code, test_data); } - /*Set cfgclkfreqrange */ + + /* Set cfgclkfreqrange */ val = (((cfg->cfg_clk_khz / 1000) - 17) * 4) & 0x3f; SET_DPHY_FREQ_CTRL0_3(dev_p, dphy_no, val); - val = kmb_read_mipi(dev_p, DPHY_FREQ_CTRL0_3 + 4); - /*Enable config clk for the corresponding d-phy */ + DRM_INFO("DPHY_FREQ = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_FREQ_CTRL0_3 + 4)); + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + + /* Enable config clk for the corresponding d-phy */ kmb_set_bit_mipi(dev_p, DPHY_CFG_CLK_EN, dphy_no); - val = kmb_read_mipi(dev_p, DPHY_CFG_CLK_EN); + + DRM_INFO("DPHY_CFG_CLK_EN = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_CFG_CLK_EN)); + /* PLL setup */ if (mode == MIPI_DPHY_MASTER) { /*Set PLL regulator in bypass */ @@ -1427,16 +1442,21 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, mipi_tx_pll_setup(dev_p, dphy_no, cfg->ref_clk_khz / 1000, cfg->lane_rate_mbps / 2); - /*Set clksel */ - kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, PLL_CLKSEL_0, - 2, 0x01); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1); + /* Set clksel */ + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL1, + PLL_CLKSEL_0, 2, 0x01); - /*Set pll_shadow_control */ + /* Set pll_shadow_control */ kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL1, PLL_SHADOW_CTRL); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL1); + + DRM_INFO("DPHY_INIT_CTRL1 = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_INIT_CTRL1)); } -#define MIPI_TX_FORCE_VOD + + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + +//#define MIPI_TX_FORCE_VOD #ifdef MIPI_TX_FORCE_VOD #define MIPI_TX_VOD_LVL 450 #define TEST_CODE_BANDGAP 0x24 @@ -1474,31 +1494,39 @@ static void dphy_init_sequence(struct kmb_drm_private *dev_p, * bits[5:0] - BaseDir: 1 = Rx * bits[9:6] - BaseDir: 0 = Tx */ + DRM_DEBUG("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); + kmb_write_bits_mipi(dev_p, DPHY_INIT_CTRL2, 0, 9, 0x03f); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2); ndelay(15); - /* Enable CLOCK LANE - */ - /*clock lane should be enabled regardless of the direction set for - * the D-PHY (Rx/Tx) + /* Enable CLOCK LANE + * Clock lane should be enabled regardless of the direction + * set for the D-PHY (Rx/Tx) */ kmb_set_bit_mipi(dev_p, DPHY_INIT_CTRL2, 12 + dphy_no); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL2); - /* enable DATA LANES */ + DRM_INFO("DPHY_INIT_CTRL2 = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_INIT_CTRL2)); + + /* Enable DATA LANES */ kmb_write_bits_mipi(dev_p, DPHY_ENABLE, dphy_no * 2, 2, ((1 << active_lanes) - 1)); - val = kmb_read_mipi(dev_p, DPHY_ENABLE); + DRM_INFO("DPHY_ENABLE = 0x%x\n", kmb_read_mipi(dev_p, DPHY_ENABLE)); ndelay(15); - /*Take D-PHY out of shutdown mode */ - /* deassert SHUTDOWNZ signal */ + + /* Take D-PHY out of shutdown mode */ + /* Deassert SHUTDOWNZ signal */ + DRM_INFO("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", + kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7)); SET_DPHY_INIT_CTRL0(dev_p, dphy_no, SHUTDOWNZ); ndelay(15); - /*deassert RSTZ signal */ + /* Deassert RSTZ signal */ SET_DPHY_INIT_CTRL0(dev_p, dphy_no, RESETZ); - val = kmb_read_mipi(dev_p, DPHY_INIT_CTRL0); + DRM_INFO("DPHY_INIT_CTRL0 = 0x%x\n", + kmb_read_mipi(dev_p, DPHY_INIT_CTRL0)); } static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no, @@ -1510,76 +1538,87 @@ static void dphy_wait_fsm(struct kmb_drm_private *dev_p, u32 dphy_no, do { test_mode_send(dev_p, dphy_no, TEST_CODE_FSM_CONTROL, 0x80); - /*TODO-need to add a time out and return failure */ + + /* TODO - need to add a time out and return failure */ val = GET_TEST_DOUT4_7(dev_p, dphy_no); i++; if (i > TIMEOUT) { status = 0; - DRM_INFO("%s: timing out fsm_state = %x GET_TEST_DOUT4_7 = %x", - __func__, fsm_state, kmb_read_mipi(dev_p, - DPHY_TEST_DOUT4_7)); break; } } while (val != fsm_state); - DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val); DRM_INFO("%s: dphy %d val = %x\n", __func__, dphy_no, val); DRM_INFO("********** DPHY %d WAIT_FSM %s **********\n", dphy_no, status ? "SUCCESS" : "FAILED"); } -static u32 wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, - u32 active_lanes) +static void wait_init_done(struct kmb_drm_private *dev_p, u32 dphy_no, + u32 active_lanes) { u32 stopstatedata = 0; u32 data_lanes = (1 << active_lanes) - 1; int i = 0, val; int status = 1; - DRM_INFO("%s : %d dphy = %d active_lanes=%d data_lanes=%d\n", - __func__, __LINE__, dphy_no, active_lanes, data_lanes); + DRM_INFO("dphy=%d active_lanes=%d data_lanes=%d\n", dphy_no, + active_lanes, data_lanes); do { val = kmb_read_mipi(dev_p, MIPI_DPHY_STAT4_7); stopstatedata = GET_STOPSTATE_DATA(dev_p, dphy_no) & data_lanes; + + /* TODO-need to add a time out and return failure */ i++; + if (i > TIMEOUT) { status = 0; - DRM_INFO("!WAIT_INIT_DONE: TIMING OUT! (err_stat=%d)n", + + DRM_INFO("! WAIT_INIT_DONE: TIMING OUT!(err_stat=%d)", kmb_read_mipi(dev_p, MIPI_DPHY_ERR_STAT6_7)); + DRM_INFO("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", val); + DRM_INFO("stopdata = 0x%x data_lanes=0x%x\n", + stopstatedata, data_lanes); + break; } -// udelay(1); + + if (i < 3) { + DRM_INFO("stopdata = 0x%x data_lanes=0x%x\n", + stopstatedata, data_lanes); + DRM_INFO("MIPI_DPHY_STAT0_4_7 = 0x%x)\n", val); + } } while (stopstatedata != data_lanes); DRM_INFO("********** DPHY %d INIT - %s **********\n", dphy_no, status ? "SUCCESS" : "FAILED"); - - return 0; } -static u32 wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) +static void wait_pll_lock(struct kmb_drm_private *dev_p, u32 dphy_no) { int i = 0; int status = 1; do { - /*TODO-need to add a time out and return failure */ + /* TODO-need to add a time out and return failure */ i++; - // udelay(1); if (i > TIMEOUT) { status = 0; + DRM_INFO("%s: timing out", __func__); - DRM_INFO("%s : PLL_LOCK = 0x%x\n", __func__, + DRM_INFO("%s : PLL_LOCK = 0x%x ", __func__, kmb_read_mipi(dev_p, DPHY_PLL_LOCK)); + break; } + if ((i % 100) == 0) + DRM_INFO("%s : PLL_LOCK = 0x%x\n", __func__, + kmb_read_mipi(dev_p, DPHY_PLL_LOCK)); } while (!GET_PLL_LOCK(dev_p, dphy_no)); DRM_INFO("********** PLL Locked for DPHY %d - %s **********\n", dphy_no, status ? "SUCCESS" : "FAILED"); - return 0; } static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, @@ -1587,10 +1626,10 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, { u32 dphy_no = MIPI_DPHY6; - DRM_INFO("%s : %d active_lanes=%d lane_rate=%d\n", - __func__, __LINE__, cfg->active_lanes, + DRM_INFO("active_lanes=%d lane_rate=%d\n", cfg->active_lanes, MIPI_TX_LANE_DATA_RATE_MBPS); - /*multiple D-PHYs needed */ + + /* Multiple D-PHYs needed */ if (cfg->active_lanes > MIPI_DPHY_D_LANES) { /* *Initialization for Tx aggregation mode is done according to @@ -1614,16 +1653,16 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, MIPI_DPHY_SLAVE); dphy_wait_fsm(dev_p, dphy_no + 1, DPHY_TX_LOCK); - /*PHY #N master */ + /* PHY #N master */ dphy_init_sequence(dev_p, cfg, dphy_no, MIPI_DPHY_D_LANES, MIPI_DPHY_MASTER); - /* wait for DPHY init to complete */ + + /* Wait for DPHY init to complete */ wait_init_done(dev_p, dphy_no, MIPI_DPHY_D_LANES); wait_init_done(dev_p, dphy_no + 1, cfg->active_lanes - MIPI_DPHY_D_LANES); wait_pll_lock(dev_p, dphy_no); wait_pll_lock(dev_p, dphy_no + 1); -// udelay(1000); dphy_wait_fsm(dev_p, dphy_no, DPHY_TX_IDLE); } else { /* Single DPHY */ dphy_init_sequence(dev_p, cfg, dphy_no, cfg->active_lanes, @@ -1636,6 +1675,51 @@ static u32 mipi_tx_init_dphy(struct kmb_drm_private *dev_p, return 0; } +#ifdef MIPI_TX_INIT_IRQS +static void mipi_tx_init_irqs(struct kmb_drm_private *dev_p, + union mipi_irq_cfg *cfg, + struct mipi_tx_ctrl_cfg *tx_ctrl_cfg) +{ + unsigned long irqflags; + uint8_t vc; + + /* Clear all interrupts first */ + /* Local interrupts */ + SET_MIPI_TX_HS_IRQ_CLEAR(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ALL); + + /* Global interrupts */ + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_HS_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); + SET_MIPI_CTRL_IRQ_CLEAR1(dev_p, MIPI_CTRL6, MIPI_HS_RX_EVENT_IRQ); + + /* Enable interrupts */ + spin_lock_irqsave(&dev_p->irq_lock, irqflags); + for (vc = 0; vc < MIPI_CTRL_VIRTUAL_CHANNELS; vc++) { + if (tx_ctrl_cfg->frames[vc] == NULL) + continue; + + /*enable FRAME_DONE interrupt if VC is configured */ + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, + MIPI_TX_HS_IRQ_FRAME_DONE_0 << vc); + + /* Only one vc for LCD interface */ + break; + } + + /* Eenable user enabled interrupts */ + if (cfg->irq_cfg.dphy_error) + SET_MIPI_CTRL_IRQ_ENABLE0(dev_p, MIPI_CTRL6, MIPI_DPHY_ERR_IRQ); + if (cfg->irq_cfg.line_compare) + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, + MIPI_TX_HS_IRQ_LINE_COMPARE); + if (cfg->irq_cfg.ctrl_error) + SET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, MIPI_TX_HS_IRQ_ERROR); + + spin_unlock_irqrestore(&dev_p->irq_lock, irqflags); +} +#endif + +#ifdef MIPI_TX_HANDLE_IRQS void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) { uint32_t irq_ctrl_stat_0, hs_stat, hs_enable; @@ -1643,7 +1727,8 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) irq_ctrl_stat_0 = MIPI_GET_IRQ_STAT0(dev_p); irq_ctrl_enabled_0 = MIPI_GET_IRQ_ENABLED0(dev_p); - /*only service enabled interrupts */ + + /* Only service enabled interrupts */ irq_ctrl_stat_0 &= irq_ctrl_enabled_0; if (irq_ctrl_stat_0 & MIPI_DPHY_ERR_MASK) { @@ -1654,7 +1739,8 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) hs_stat = GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6); hs_enable = GET_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6); hs_stat &= hs_enable; - /*look for errors */ + + /* Check for errors */ if (hs_stat & MIPI_TX_HS_IRQ_ERROR) { CLR_HS_IRQ_ENABLE(dev_p, MIPI_CTRL6, (hs_stat & MIPI_TX_HS_IRQ_ERROR) | @@ -1667,43 +1753,21 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) } } +#endif +#ifdef LCD_TEST void connect_lcd_to_mipi(struct kmb_drm_private *dev_p) { -#ifdef LCD_TEST - /*connect lcd to mipi */ - /*DISABLE MIPI->CIF CONNECTION*/ + /* DISABLE MIPI->CIF CONNECTION */ kmb_write_msscam(dev_p, MSS_MIPI_CIF_CFG, 0); - /*ENABLE LCD->MIPI CONNECTION */ - kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); - /*DISABLE LCD->CIF LOOPBACK */ - kmb_write_msscam(dev_p, MSS_LOOPBACK_CFG, 0); -#endif -} -/** - * Reads specified number of bytes from the file. - * - * @param file - file structure. - * @param offset - offset in the file. - * @param addr - address of the buffer. - * @param count - size of the buffer . - * - * @return 0 if success or error code. - */ -int kmb_kernel_read(struct file *file, loff_t offset, - char *addr, unsigned long count) -{ - char __user *buf = (char __user *)addr; - ssize_t ret; - - if (!(file->f_mode & FMODE_READ)) - return -EBADF; - - ret = kernel_read(file, buf, count, &offset); + /* ENABLE LCD->MIPI CONNECTION */ + kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); - return ret; + /* DISABLE LCD->CIF LOOPBACK */ + kmb_write_msscam(dev_p, MSS_LOOPBACK_CFG, 0); } +#endif int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) { @@ -1711,35 +1775,39 @@ int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) u64 data_rate; mipi_tx_init_cfg.active_lanes = MIPI_TX_ACTIVE_LANES; + if (mode != NULL) { mipi_tx_frame0_sect_cfg.width_pixels = mode->crtc_hdisplay; mipi_tx_frame0_sect_cfg.height_lines = mode->crtc_vdisplay; mipitx_frame0_cfg.vsync_width = - mode->crtc_vsync_end - mode->crtc_vsync_start; + mode->crtc_vsync_end - mode->crtc_vsync_start; mipitx_frame0_cfg.v_backporch = - mode->crtc_vtotal - mode->crtc_vsync_end; + mode->crtc_vtotal - mode->crtc_vsync_end; mipitx_frame0_cfg.v_frontporch = - mode->crtc_vsync_start - mode->crtc_vdisplay; + mode->crtc_vsync_start - mode->crtc_vdisplay; mipitx_frame0_cfg.hsync_width = - mode->crtc_hsync_end - mode->crtc_hsync_start; + mode->crtc_hsync_end - mode->crtc_hsync_start; mipitx_frame0_cfg.h_backporch = - mode->crtc_htotal - mode->crtc_hsync_end; + mode->crtc_htotal - mode->crtc_hsync_end; mipitx_frame0_cfg.h_frontporch = - mode->crtc_hsync_start - mode->crtc_hdisplay; - /*lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000 + mode->crtc_hsync_start - mode->crtc_hdisplay; + + /* Lane rate = (vtotal*htotal*fps*bpp)/4 / 1000000 * to convert to Mbps */ - DRM_INFO("htotal = %d vtotal=%d refresh=%d\n", - mode->crtc_htotal, mode->crtc_vtotal, - drm_mode_vrefresh(mode)); - data_rate = - ((((u32)mode->crtc_vtotal * (u32)mode->crtc_htotal) - * (u32)(drm_mode_vrefresh(mode)) - * MIPI_TX_BPP)/mipi_tx_init_cfg.active_lanes) / 1000000; - DRM_INFO("data_rate = %llu active_lanes=%d\n", - data_rate, mipi_tx_init_cfg.active_lanes); - - /*when late rate < 800 - modeset fails with 4 lanes - + data_rate = ((((u32) mode->crtc_vtotal * + (u32) mode->crtc_htotal) * + (u32)(drm_mode_vrefresh(mode)) * + MIPI_TX_BPP) / mipi_tx_init_cfg.active_lanes) / + 1000000; + + DRM_INFO("htotal=%d vtotal=%d refresh=%d\n", + mode->crtc_htotal, mode->crtc_vtotal, + drm_mode_vrefresh(mode)); + DRM_INFO("data_rate=%u active_lanes=%d\n", + (u32) data_rate, mipi_tx_init_cfg.active_lanes); + + /* When late rate < 800, modeset fails with 4 lanes, * so switch to 2 lanes */ if (data_rate < 800) { @@ -1749,36 +1817,62 @@ int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode) mipi_tx_init_cfg.lane_rate_mbps = data_rate; } DRM_INFO("lane rate=%d\n", mipi_tx_init_cfg.lane_rate_mbps); - DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d\n", - mipitx_frame0_cfg.v_frontporch, mipitx_frame0_cfg.v_backporch, - mipitx_frame0_cfg.vsync_width, - mipitx_frame0_cfg.h_frontporch, mipitx_frame0_cfg.h_backporch, - mipitx_frame0_cfg.hsync_width, - mipi_tx_init_cfg.lane_rate_mbps); + DRM_INFO + ("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d lane-rate=%d", + mipitx_frame0_cfg.v_frontporch, + mipitx_frame0_cfg.v_backporch, + mipitx_frame0_cfg.vsync_width, + mipitx_frame0_cfg.h_frontporch, + mipitx_frame0_cfg.h_backporch, + mipitx_frame0_cfg.hsync_width, + mipi_tx_init_cfg.lane_rate_mbps); } + if (hw_initialized) return 0; + kmb_write_mipi(dev_p, DPHY_ENABLE, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL0, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL1, 0); kmb_write_mipi(dev_p, DPHY_INIT_CTRL2, 0); - /* initialize mipi controller */ + /* Initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); - /*d-phy initialization */ + + /* Dphy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); + DRM_INFO("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); + +#ifdef LCD_TEST connect_lcd_to_mipi(dev_p); +#endif + +#ifdef MIPI_TX_INIT_IRQS + /* IRQ initialization */ + mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + + DRM_INFO("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); +#endif + #ifdef MIPI_TX_TEST_PATTERN_GENERATION - mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, 0x15, 0xff, - 0xff00, MIPI_CTRL6); - DRM_INFO("%s : %d IRQ_STATUS = 0x%x\n", __func__, __LINE__, - GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); + mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, + 0x15, 0xff, 0xff00, MIPI_CTRL6); + + DRM_INFO("IRQ_STATUS = 0x%x\n", + GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); #endif //MIPI_TX_TEST_PATTERN_GENERATION hw_initialized = true; - DRM_INFO("%s : %d mipi hw_initialized = %d\n", __func__, __LINE__, - hw_initialized); + + DRM_INFO("MIPI_TXm_HS_CTRL = 0x%x\n", + kmb_read_mipi(dev_p, MIPI_TXm_HS_CTRL(6))); + DRM_INFO("MIPI LOOP BACK = %x\n", + kmb_read_mipi(dev_p, MIPI_CTRL_DIG_LOOPBACK)); + DRM_INFO("mipi hw_initialized = %d\n", hw_initialized); + return 0; } @@ -1797,7 +1891,6 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) return -ENOMEM; } - DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_connector = kzalloc(sizeof(*kmb_connector), GFP_KERNEL); if (!kmb_connector) { kfree(kmb_dsi); @@ -1809,38 +1902,42 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) host = kmb_dsi_host_init(dev, kmb_dsi); if (!host) { - DRM_ERROR("Faile to allocate host\n"); + DRM_ERROR("Failed to allocate host\n"); kfree(kmb_dsi); kfree(kmb_connector); return -ENOMEM; } + kmb_dsi->dsi_host = host; connector = &kmb_connector->base; encoder = &kmb_dsi->base; encoder->possible_crtcs = 1; encoder->possible_clones = 0; + drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI"); drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, DRM_MODE_CONNECTOR_DSI); + drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); - DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, - __LINE__, connector->name, encoder->name); + DRM_INFO("connector = %s encoder = %s\n", connector->name, + encoder->name); ret = drm_connector_attach_encoder(connector, encoder); + DRM_INFO("connector->encoder = 0x%p ret = %d\n", connector->encoder, + ret); - /* Link drm_bridge to encoder */ #ifndef FCCTEST + /* Link drm_bridge to encoder */ ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) { DRM_ERROR("failed to attach bridge to MIPI\n"); drm_encoder_cleanup(encoder); return ret; } - - DRM_INFO("%s : %d Bridge attached : SUCCESS\n", __func__, __LINE__); + DRM_INFO("Bridge attached : SUCCESS\n"); #endif #ifdef FCCTEST diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 1d4ca8d..68508e0 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -31,6 +31,60 @@ #include <drm/drm_modes.h> #include "kmb_drv.h" +/* MIPI TX CFG*/ +#define MIPI_TX_LANE_DATA_RATE_MBPS 891 +#define MIPI_TX_REF_CLK_KHZ 24000 +#define MIPI_TX_CFG_CLK_KHZ 24000 +#define MIPI_TX_BPP 24 + +/* DPHY Tx test codes*/ +#define TEST_CODE_FSM_CONTROL 0x03 +#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C +#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E +#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F +#define TEST_CODE_PLL_VCO_CTRL 0x12 +#define TEST_CODE_PLL_GMP_CTRL 0x13 +#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14 +#define TEST_CODE_PLL_LOCK_FILTER 0x15 +#define TEST_CODE_PLL_UNLOCK_FILTER 0x16 +#define TEST_CODE_PLL_INPUT_DIVIDER 0x17 +#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18 +#define PLL_FEEDBACK_DIVIDER_HIGH (1 << 7) +#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19 +#define PLL_N_OVR_EN (1 << 4) +#define PLL_M_OVR_EN (1 << 5) +#define TEST_CODE_VOD_LEVEL 0x24 +#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C +#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D +#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44 +#define TEST_CODE_PLL_ANALOG_PROG 0x1F +#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0 +#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3 +#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4 + +/* DPHY params */ +#define PLL_N_MIN 0 +#define PLL_N_MAX 15 +#define PLL_M_MIN 62 +#define PLL_M_MAX 623 +#define PLL_FVCO_MAX 1250 + +#define TIMEOUT 600 + +#define MIPI_TX_FRAME_GEN 4 +#define MIPI_TX_FRAME_GEN_SECTIONS 4 +#define MIPI_CTRL_VIRTUAL_CHANNELS 4 +#define MIPI_D_LANES_PER_DPHY 2 +#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 +#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511 +/* 2 Data Lanes per D-PHY */ +#define MIPI_DPHY_D_LANES 2 +#define MIPI_DPHY_DEFAULT_BIT_RATES 63 + +#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) +#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) +#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base) + struct kmb_connector; struct kmb_dsi_host; @@ -53,16 +107,7 @@ struct kmb_connector { struct drm_display_mode *fixed_mode; }; -#define MIPI_TX_FRAME_GEN 4 -#define MIPI_TX_FRAME_GEN_SECTIONS 4 -#define MIPI_CTRL_VIRTUAL_CHANNELS 4 -#define MIPI_D_LANES_PER_DPHY 2 -#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255 -#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511 -#define MIPI_DPHY_D_LANES 2 /* 2 Data Lanes per D-PHY*/ -#define MIPI_DPHY_DEFAULT_BIT_RATES 63 - -/*DPHY Tx test codes */ +/* DPHY Tx test codes */ enum mipi_ctrl_num { MIPI_CTRL0 = 0, @@ -252,7 +297,7 @@ struct mipi_tx_dsi_cfg { struct mipi_tx_frame_section_cfg { uint32_t dma_v_stride; uint16_t dma_v_scale_cfg; - uint16_t width_pixels; /* Frame width */ + uint16_t width_pixels; uint16_t height_lines; uint8_t dma_packed; uint8_t bpp; @@ -324,15 +369,15 @@ struct mipi_ctrl_cfg { struct mipi_tx_ctrl_cfg tx_ctrl_cfg; }; -/*structure for storing user specified interrupts that are enabled */ +/* Structure for storing user specified interrupts that are enabled */ union mipi_irq_cfg { uint8_t value; struct { - uint8_t line_compare : 1; - uint8_t dma_event : 1; - uint8_t frame_done : 1; - uint8_t ctrl_error : 1; - uint8_t dphy_error : 1; + uint8_t line_compare:1; + uint8_t dma_event:1; + uint8_t frame_done:1; + uint8_t ctrl_error:1; + uint8_t dphy_error:1; } irq_cfg; }; @@ -342,9 +387,4 @@ void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); void kmb_dsi_host_unregister(void); int kmb_dsi_hw_init(struct drm_device *dev, struct drm_display_mode *mode); - -#define to_kmb_connector(x) container_of(x, struct kmb_connector, base) -#define to_kmb_host(x) container_of(x, struct kmb_dsi_host, base) -#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base) - #endif /* __KMB_DSI_H__ */ diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index ebf29b2..8d83238 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -41,67 +41,6 @@ #include "kmb_regs.h" #include "kmb_drv.h" -/* graphics layer ( layers 2 & 3) formats, only packed formats are supported*/ -static const u32 kmb_formats_g[] = { - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, -}; - -#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g)) -#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v)) - -/* video layer ( 0 & 1) formats, packed and planar formats are supported */ -static const u32 kmb_formats_v[] = { - /* packed formats */ - DRM_FORMAT_RGB332, - DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, - DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, - DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, - DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, - DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, - DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, - /*planar formats */ - DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, - DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, - DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, - DRM_FORMAT_NV12, DRM_FORMAT_NV21, -}; - -#define LCD_INT_VL0_ERR (LAYER0_DMA_FIFO_UNDEFLOW | \ - LAYER0_DMA_FIFO_OVERFLOW | \ - LAYER0_DMA_CB_FIFO_OVERFLOW | \ - LAYER0_DMA_CB_FIFO_UNDERFLOW | \ - LAYER0_DMA_CR_FIFO_OVERFLOW | \ - LAYER0_DMA_CR_FIFO_UNDERFLOW) - -#define LCD_INT_VL1_ERR (LAYER1_DMA_FIFO_UNDERFLOW | \ - LAYER1_DMA_FIFO_OVERFLOW | \ - LAYER1_DMA_CB_FIFO_OVERFLOW | \ - LAYER1_DMA_CB_FIFO_UNDERFLOW | \ - LAYER1_DMA_CR_FIFO_OVERFLOW | \ - LAYER1_DMA_CR_FIFO_UNDERFLOW) - -#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW) - -#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW) - -#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR) - -#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR) - -#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR) - -#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) - const uint32_t layer_irqs[] = { LCD_INT_VL0, LCD_INT_VL1, @@ -109,16 +48,6 @@ const uint32_t layer_irqs[] = { LCD_INT_GL1 }; -/*Conversion (yuv->rgb) matrix from myriadx */ -static const u32 csc_coef_lcd[] = { - 1024, 0, 1436, - 1024, -352, -731, - 1024, 1814, 0, - -179, 125, -226 -}; - -/*plane initialization status */ - static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { int i; @@ -137,7 +66,6 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, int ret; fb = state->fb; - if (!fb || !state->crtc) return 0; @@ -269,7 +197,6 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_RGBA8888; break; } - DRM_INFO("%s : %d layer format val=%d\n", __func__, __LINE__, val); return val; } @@ -300,14 +227,14 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) break; } - DRM_INFO("%s : %d bpp=%d val=%d\n", __func__, __LINE__, bpp, val); + DRM_DEBUG("bpp=%d val=0x%x\n", bpp, val); return val; } #ifdef LCD_TEST static void config_csc(struct kmb_drm_private *dev_p, int plane_id) { - /*YUV to RGB conversion using the fixed matrix csc_coef_lcd */ + /* YUV to RGB conversion using the fixed matrix csc_coef_lcd */ kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]); kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]); kmb_write_lcd(dev_p, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]); @@ -358,9 +285,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, crtc_x = plane->state->crtc_x; crtc_y = plane->state->crtc_y; - DRM_DEBUG - ("%s : %d src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x", - __func__, __LINE__, src_w, src_h, fb->format->format, fb->flags); + DRM_DEBUG("src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x\n", + src_w, src_h, fb->format->format, fb->flags); width = fb->width; height = fb->height; @@ -368,38 +294,41 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, DRM_DEBUG("%s : %d dma_len=%d ", __func__, __LINE__, dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), fb->pitches[0]); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), (width * fb->format->cpp[0])); addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0); - dev_p->fb_addr = (dma_addr_t) addr; + dev_p->fb_addr = addr[Y_PLANE]; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr[Y_PLANE] + fb->offsets[0]); - /*program Cb/Cr for planar formats */ + /* Program Cb/Cr for planar formats */ if (num_planes > 1) { if (fb->format->format == DRM_FORMAT_YUV420 || fb->format->format == DRM_FORMAT_YVU420) width /= 2; - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), fb->pitches[LAYER_1]); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), + + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), (width * fb->format->cpp[0])); + addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, U_PLANE); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), addr[U_PLANE]); + if (num_planes == 3) { kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), fb->pitches[LAYER_2]); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), (width * fb->format->cpp[0])); + addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, V_PLANE); @@ -409,8 +338,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, } } - kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1); - kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1); + kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y); @@ -422,25 +351,25 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, if (val & LCD_LAYER_PLANAR_STORAGE) { val |= LCD_LAYER_CSC_EN; - /*enable CSC if input is planar and output is RGB */ + /* Enable CSC if input is planar and output is RGB */ config_csc(dev_p, plane_id); } kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); switch (plane_id) { - case LAYER_0: - ctrl = LCD_CTRL_VL1_ENABLE; - break; - case LAYER_1: - ctrl = LCD_CTRL_VL2_ENABLE; - break; - case LAYER_2: - ctrl = LCD_CTRL_GL1_ENABLE; - break; - case LAYER_3: - ctrl = LCD_CTRL_GL2_ENABLE; - break; + case LAYER_0: + ctrl = LCD_CTRL_VL1_ENABLE; + break; + case LAYER_1: + ctrl = LCD_CTRL_VL2_ENABLE; + break; + case LAYER_2: + ctrl = LCD_CTRL_GL1_ENABLE; + break; + case LAYER_3: + ctrl = LCD_CTRL_GL2_ENABLE; + break; } ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE @@ -461,16 +390,14 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* Leave RGB order,conversion mode and clip mode to default */ /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; - // out_format |= LCD_OUTF_SYNC_MODE; kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; - /* enable DMA */ + /* Enable DMA */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); - DRM_DEBUG("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", - __func__, __LINE__, dma_cfg, + DRM_DEBUG("dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg, kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); #endif } @@ -493,7 +420,6 @@ static void kmb_destroy_plane_state(struct drm_plane *plane, struct drm_plane_state *state) { struct kmb_plane_state *kmb_state = to_kmb_plane_state(state); - __drm_atomic_helper_plane_destroy_state(state); kfree(kmb_state); } @@ -504,7 +430,6 @@ struct drm_plane_state *kmb_plane_duplicate_state(struct drm_plane *plane) struct kmb_plane_state *kmb_state; kmb_state = kmemdup(plane->state, sizeof(*kmb_state), GFP_KERNEL); - if (!kmb_state) return NULL; @@ -554,7 +479,6 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) int num_plane_formats; for (i = 0; i < lcd->n_layers; i++) { - plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL); if (!plane) { @@ -573,26 +497,25 @@ struct kmb_plane *kmb_plane_init(struct drm_device *drm) } ret = drm_universal_plane_init(drm, &plane->base_plane, - POSSIBLE_CRTCS, - &kmb_plane_funcs, plane_formats, - num_plane_formats, + POSSIBLE_CRTCS, &kmb_plane_funcs, + plane_formats, num_plane_formats, NULL, plane_type, "plane %d", i); if (ret < 0) { - DRM_ERROR - ("drm_universal_plane_init -failed with ret=%d", - ret); + DRM_ERROR("drm_universal_plane_init failed (ret=%d)", + ret); goto cleanup; } DRM_DEBUG("%s : %d plane=%px\n i=%d type=%d", - __func__, __LINE__, &plane->base_plane, - i, plane_type); - + __func__, __LINE__, + &plane->base_plane, i, plane_type); drm_plane_helper_add(&plane->base_plane, &kmb_plane_helper_funcs); if (plane_type == DRM_PLANE_TYPE_PRIMARY) { primary = plane; lcd->plane = plane; } + DRM_DEBUG("%s : %d primary=%px\n", __func__, __LINE__, + &primary->base_plane); plane->id = i; } diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index 8411219..1872ed0 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -28,6 +28,34 @@ #include "kmb_drv.h" +#define LCD_INT_VL0_ERR (LAYER0_DMA_FIFO_UNDEFLOW | \ + LAYER0_DMA_FIFO_OVERFLOW | \ + LAYER0_DMA_CB_FIFO_OVERFLOW | \ + LAYER0_DMA_CB_FIFO_UNDERFLOW | \ + LAYER0_DMA_CR_FIFO_OVERFLOW | \ + LAYER0_DMA_CR_FIFO_UNDERFLOW) + +#define LCD_INT_VL1_ERR (LAYER1_DMA_FIFO_UNDERFLOW | \ + LAYER1_DMA_FIFO_OVERFLOW | \ + LAYER1_DMA_CB_FIFO_OVERFLOW | \ + LAYER1_DMA_CB_FIFO_UNDERFLOW | \ + LAYER1_DMA_CR_FIFO_OVERFLOW | \ + LAYER1_DMA_CR_FIFO_UNDERFLOW) + +#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW) +#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW) +#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR) +#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR) +#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR) +#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) + +#define POSSIBLE_CRTCS 1 +#define INITIALIZED 1 +#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) + +#define to_kmb_plane_state(x) \ + container_of(x, struct kmb_plane_state, base_plane_state) + enum layer_id { LAYER_0, LAYER_1, @@ -54,12 +82,48 @@ struct kmb_plane_state { unsigned char no_planes; }; -#define POSSIBLE_CRTCS 1 -#define INITIALIZED 1 -#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane) +/* Graphics layer (layers 2 & 3) formats, only packed formats are supported */ +static const u32 kmb_formats_g[] = { + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, +}; -#define to_kmb_plane_state(x) \ - container_of(x, struct kmb_plane_state, base_plane_state) +#define MAX_FORMAT_G (ARRAY_SIZE(kmb_formats_g)) +#define MAX_FORMAT_V (ARRAY_SIZE(kmb_formats_v)) + +/* Video layer ( 0 & 1) formats, packed and planar formats are supported */ +static const u32 kmb_formats_v[] = { + /* packed formats */ + DRM_FORMAT_RGB332, + DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444, + DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, DRM_FORMAT_BGR565, + DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, + DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888, + /*planar formats */ + DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, + DRM_FORMAT_YUV422, DRM_FORMAT_YVU422, + DRM_FORMAT_YUV444, DRM_FORMAT_YVU444, + DRM_FORMAT_NV12, DRM_FORMAT_NV21, +}; + +/* Conversion (yuv->rgb) matrix from myriadx */ +static const u32 csc_coef_lcd[] = { + 1024, 0, 1436, + 1024, -352, -731, + 1024, 1814, 0, + -179, 125, -226 +}; struct kmb_plane *kmb_plane_init(struct drm_device *drm); void kmb_plane_destroy(struct drm_plane *plane); diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 0249ea5..f904a5c 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -553,9 +553,10 @@ /* MIPI IRQ */ #define MIPI_CTRL_IRQ_STATUS0 (0x00) #define MIPI_DPHY_ERR_IRQ 1 -#define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */ +#define MIPI_DPHY_ERR_MASK 0x7FE /*bits 1-10 */ #define MIPI_HS_IRQ 13 -#define MIPI_HS_IRQ_MASK 0x7FE000 /*bits 13-22 */ +/*bits 13-22 */ +#define MIPI_HS_IRQ_MASK 0x7FE000 #define MIPI_LP_EVENT_IRQ 25 #define MIPI_GET_IRQ_STAT0(dev) kmb_read_mipi(dev, \ MIPI_CTRL_IRQ_STATUS0) @@ -735,18 +736,18 @@ & (1 << (dphy - MIPI_DPHY6))) #define DPHY_CFG_CLK_EN (0x18c) -#define MSS_MIPI_CIF_CFG (0x00) -#define MSS_LCD_MIPI_CFG (0x04) -#define MSS_CAM_CLK_CTRL (0x10) -#define MSS_LOOPBACK_CFG (0x0C) -#define LCD (1<<1) -#define MIPI_COMMON (1<<2) -#define MIPI_TX0 (1<<9) -#define MSS_CAM_RSTN_CTRL (0x14) -#define MSS_CAM_RSTN_SET (0x20) -#define MSS_CAM_RSTN_CLR (0x24) +#define MSS_MIPI_CIF_CFG (0x00) +#define MSS_LCD_MIPI_CFG (0x04) +#define MSS_CAM_CLK_CTRL (0x10) +#define MSS_LOOPBACK_CFG (0x0C) +#define LCD (1<<1) +#define MIPI_COMMON (1<<2) +#define MIPI_TX0 (1<<9) +#define MSS_CAM_RSTN_CTRL (0x14) +#define MSS_CAM_RSTN_SET (0x20) +#define MSS_CAM_RSTN_CLR (0x24) -#define MSSCPU_CPR_CLK_EN (0x0) -#define MSSCPU_CPR_RST_EN (0x10) +#define MSSCPU_CPR_CLK_EN (0x0) +#define MSSCPU_CPR_RST_EN (0x10) #define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:07 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:07 -0700 Subject: [Intel-gfx] [PATCH 55/59] drm/kmb: Added useful messages in LCD ISR In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-56-git-send-email-anitha.chrisanthus@intel.com> Print messages for LCD DMA FIFO errors. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 68 +++++++++++++++++++++++++++++++++++------ drivers/gpu/drm/kmb/kmb_plane.h | 2 ++ 2 files changed, 60 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 79ab0bc..f8894d3 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -383,15 +383,15 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) * disabled but actually disable the plane when EOF irq is * being handled. */ - for (plane_id = LAYER_0; plane_id < KMB_MAX_PLANES; - plane_id++) { + for (plane_id = LAYER_0; plane_id < KMB_MAX_PLANES; plane_id++) { if (plane_status[plane_id].disable) { kmb_clr_bitmask_lcd(dev_p, - LCD_LAYERn_DMA_CFG(plane_id), - LCD_DMA_LAYER_ENABLE); + LCD_LAYERn_DMA_CFG + (plane_id), + LCD_DMA_LAYER_ENABLE); kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, - plane_status[plane_id].ctrl); + plane_status[plane_id].ctrl); plane_status[plane_id].disable = false; } @@ -403,11 +403,6 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LINE_CMP); } - if (status & LCD_INT_LAYER) { - /* Clear layer interrupts */ - kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LAYER); - } - if (status & LCD_INT_VERT_COMP) { /* Read VSTATUS */ val = kmb_read_lcd(dev_p, LCD_VSTATUS); @@ -425,6 +420,59 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) } } + if (status & LCD_INT_DMA_ERR) { + val = (status & LCD_INT_DMA_ERR); + /* LAYER0 - VL0 */ + if (val & LAYER0_DMA_FIFO_UNDEFLOW) + DRM_INFO("LAYER0:VL0 DMA UNDERFLOW val = 0x%lx", val); + if (val & LAYER0_DMA_FIFO_OVERFLOW) + DRM_INFO("LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val); + if (val & LAYER0_DMA_CB_FIFO_OVERFLOW) + DRM_INFO("LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val); + if (val & LAYER0_DMA_CB_FIFO_UNDERFLOW) + DRM_INFO("LAYER0:VL0 DMA CB UNDERFLOW val = 0x%lx", + val); + if (val & LAYER0_DMA_CR_FIFO_UNDERFLOW) + DRM_INFO("LAYER0:VL0 DMA CR UNDERFLOW val = 0x%lx", + val); + if (val & LAYER0_DMA_CR_FIFO_OVERFLOW) + DRM_INFO("LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val); + + /* LAYER1 - VL1 */ + if (val & LAYER1_DMA_FIFO_UNDERFLOW) + DRM_INFO("LAYER1:VL1 DMA UNDERFLOW val = 0x%lx", val); + if (val & LAYER1_DMA_FIFO_OVERFLOW) + DRM_INFO("LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val); + if (val & LAYER1_DMA_CB_FIFO_OVERFLOW) + DRM_INFO("LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val); + if (val & LAYER1_DMA_CB_FIFO_UNDERFLOW) + DRM_INFO("LAYER1:VL1 DMA CB UNDERFLOW val = 0x%lx", + val); + if (val & LAYER1_DMA_CR_FIFO_UNDERFLOW) + DRM_INFO("LAYER1:VL1 DMA CR UNDERFLOW val = 0x%lx", + val); + if (val & LAYER1_DMA_CR_FIFO_OVERFLOW) + DRM_INFO("LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val); + + /* LAYER2 - GL0 */ + if (val & LAYER2_DMA_FIFO_UNDERFLOW) + DRM_INFO("LAYER2:GL0 DMA UNDERFLOW val = 0x%lx", val); + if (val & LAYER2_DMA_FIFO_OVERFLOW) + DRM_INFO("LAYER2:GL0 DMA OVERFLOW val = 0x%lx", val); + + /* LAYER3 - GL1 */ + if (val & LAYER3_DMA_FIFO_UNDERFLOW) + DRM_INFO("LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val); + if (val & LAYER3_DMA_FIFO_UNDERFLOW) + DRM_INFO("LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val); + + } + + if (status & LCD_INT_LAYER) { + /* Clear layer interrupts */ + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_LAYER); + } + /* Clear all interrupts */ kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, 1); return IRQ_HANDLED; diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index ae8e308..af0d091 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -48,6 +48,8 @@ #define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR) #define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR) #define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR) +#define LCD_INT_DMA_ERR (LCD_INT_VL0_ERR | LCD_INT_VL1_ERR \ + | LCD_INT_GL0_ERR | LCD_INT_GL1_ERR) #define POSSIBLE_CRTCS 1 #define INITIALIZED 1 -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:06 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:06 -0700 Subject: [Intel-gfx] [PATCH 54/59] drm/kmb: Initialize uninitialized variables In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-55-git-send-email-anitha.chrisanthus@intel.com> general cleaning Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 977fcb8..8a12d6d 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -330,7 +330,7 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) { - struct drm_bridge *bridge; + struct drm_bridge *bridge = NULL; #ifndef FCCTEST struct device_node *encoder_node; #endif @@ -838,7 +838,7 @@ static void mipi_tx_hs_tp_gen(struct kmb_drm_private *dev_p, int vc, static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, struct mipi_ctrl_cfg *ctrl_cfg) { - u32 ret; + u32 ret = 0; u8 active_vchannels = 0; u8 frame_id, sect; u32 bits_per_pclk = 0; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:08 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:08 -0700 Subject: [Intel-gfx] [PATCH 56/59] kmb/drm: Prune unsupported modes In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-57-git-send-email-anitha.chrisanthus@intel.com> KMB display pipeline is LCD->Mipi->HDMI. Mipi->HDMI converter chip only accepts 4-lane input from mipi. With 4-lane mipi, KMB hardware can only support 1080p resolution. Therefore, limit supported mode to 1080p. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 4 ++-- drivers/gpu/drm/kmb/kmb_drv.h | 8 +++++--- drivers/gpu/drm/kmb/kmb_dsi.c | 11 +++++++++++ drivers/gpu/drm/kmb/kmb_plane.c | 2 ++ 4 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index f8894d3..68e7b5c 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -359,8 +359,8 @@ static const struct drm_mode_config_funcs kmb_mode_config_funcs = { static void kmb_setup_mode_config(struct drm_device *drm) { drm_mode_config_init(drm); - drm->mode_config.min_width = 0; - drm->mode_config.min_height = 0; + drm->mode_config.min_width = KMB_MIN_WIDTH; + drm->mode_config.min_height = KMB_MIN_HEIGHT; drm->mode_config.max_width = KMB_MAX_WIDTH; drm->mode_config.max_height = KMB_MAX_HEIGHT; drm->mode_config.funcs = &kmb_mode_config_funcs; diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 83824f7..eef2d8b 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -28,10 +28,12 @@ #include "kmb_regs.h" -#define FCCTEST +//#define FCCTEST #define LCD_TEST -#define KMB_MAX_WIDTH 1920 /*max width in pixels */ -#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ +#define KMB_MAX_WIDTH 1920 /*max width in pixels */ +#define KMB_MAX_HEIGHT 1080 /*max height in pixels */ +#define KMB_MIN_WIDTH 1920 /*max width in pixels */ +#define KMB_MIN_HEIGHT 1080 /*max height in pixels */ #define KMB_LCD_DEFAULT_CLK 250000000 #define KMB_MIPI_DEFAULT_CLK 24000000 #define KMB_MIPI_DEFAULT_CFG_CLK 24000000 diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 8a12d6d..ec974da 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -216,6 +216,17 @@ static enum drm_mode_status kmb_dsi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { + struct drm_device *dev = connector->dev; + struct drm_mode_config *mode_config = &dev->mode_config; + + if (mode->hdisplay < mode_config->min_width || + mode->hdisplay > mode_config->max_width) + return MODE_BAD_HVALUE; + + if (mode->vdisplay < mode_config->min_height || + mode->vdisplay > mode_config->max_height) + return MODE_BAD_VVALUE; + return MODE_OK; } diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 81250e1..5e040f7 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -77,6 +77,8 @@ static int kmb_plane_atomic_check(struct drm_plane *plane, if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT) return -EINVAL; + if (state->crtc_w < KMB_MIN_WIDTH || state->crtc_h < KMB_MIN_HEIGHT) + return -EINVAL; return 0; } -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:37 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:37 -0700 Subject: [Intel-gfx] [PATCH 25/59] drm/kmb: Display clock enable/disable In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-26-git-send-email-anitha.chrisanthus@intel.com> Get clock info from DT and enable it during initialization. Also changed name of the driver to "kmb,display" to match other entries in the DT. v2: fixed error in clk_disable Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 42 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 0aa910b..b0ab40b 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -32,6 +32,7 @@ #include <linux/of_graph.h> #include <linux/of_reserved_mem.h> #include <linux/pm_runtime.h> +#include <linux/clk.h> #include <drm/drm.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> @@ -51,6 +52,25 @@ /*IRQ handler*/ static irqreturn_t kmb_isr(int irq, void *arg); +static struct clk *clk_lcd; +static struct clk *clk_mipi; + +static int kmb_display_clk_enable(void) +{ + clk_prepare_enable(clk_lcd); + clk_prepare_enable(clk_mipi); + return 0; +} + +static int kmb_display_clk_disable(void) +{ + if (clk_lcd) + clk_disable_unprepare(clk_lcd); + if (clk_mipi) + clk_disable_unprepare(clk_mipi); + return 0; +} + static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; @@ -172,6 +192,19 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } + /* enable display clocks*/ + clk_lcd = clk_get(&pdev->dev, "clk_lcd"); + if (!clk_lcd) { + DRM_ERROR("clk_get() failed clk_lcd\n"); + goto setup_fail; + } + clk_mipi = clk_get(&pdev->dev, "clk_mipi"); + if (!clk_mipi) { + DRM_ERROR("clk_get() failed clk_mipi\n"); + goto setup_fail; + } + kmb_display_clk_enable(); + ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); @@ -397,6 +430,11 @@ static void kmb_drm_unbind(struct device *dev) of_reserved_mem_device_release(drm->dev); drm_mode_config_cleanup(drm); + /*release clks */ + kmb_display_clk_disable(); + clk_put(clk_lcd); + clk_put(clk_mipi); + drm_dev_put(drm); drm->dev_private = NULL; dev_set_drvdata(dev, NULL); @@ -435,8 +473,8 @@ static int kmb_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id kmb_of_match[] = { - {.compatible = "lcd"}, +static const struct of_device_id kmb_of_match[] = { + {.compatible = "kmb,display"}, {}, }; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:39 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:39 -0700 Subject: [Intel-gfx] [PATCH 27/59] drm/kmb: minor name change to match device tree In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-28-git-send-email-anitha.chrisanthus@intel.com> name change Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 1f0dcbe..b1cc8ad 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -475,7 +475,7 @@ static int kmb_remove(struct platform_device *pdev) } static const struct of_device_id kmb_of_match[] = { - {.compatible = "kmb,display"}, + {.compatible = "intel,kmb_display"}, {}, }; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:41 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:41 -0700 Subject: [Intel-gfx] [PATCH 29/59] drm/kmb: Defer Probe In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-30-git-send-email-anitha.chrisanthus@intel.com> Register DSI host first and then defer probe until ADV bridge is initialized. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 144 ++++++++++++++---------------------------- drivers/gpu/drm/kmb/kmb_dsi.c | 46 ++++++++++++-- drivers/gpu/drm/kmb/kmb_dsi.h | 3 +- 3 files changed, 89 insertions(+), 104 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index b4e1e50..f1bf258 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -56,6 +56,8 @@ static irqreturn_t kmb_isr(int irq, void *arg); static struct clk *clk_lcd; static struct clk *clk_mipi; +static int probe_deferred; + static int kmb_display_clk_enable(void) { clk_prepare_enable(clk_lcd); @@ -76,12 +78,11 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); - struct drm_bridge *bridge; +/* struct drm_bridge *bridge;*/ /*struct resource *res;*/ /*u32 version;*/ - int irq_lcd, irq_mipi; int ret; - struct device_node *encoder_node; +/* struct device_node *encoder_node;*/ /* TBD - not sure if clock_get needs to be called here */ /* @@ -93,9 +94,10 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) * TBD call this in the future when device tree is ready, * use hardcoded value for now */ - /*res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - *dev_p->lcd_mmio = devm_ioremap_resource(drm->dev, res); - * + /* + * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + * dev_p->lcd_mmio = devm_ioremap_resource(drm->dev, res); + *if (IS_ERR(dev_p->lcd_mmio)) { * DRM_ERROR("failed to map control registers area\n"); * ret = PTR_ERR(dev_p->lcd_mmio); @@ -103,7 +105,10 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) * return ret; *} */ - /* LCD mmio */ + /* LCD mmio */ + if (!probe_deferred) { + probe_deferred = 1; + if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) { DRM_ERROR("failed to reserve LCD registers\n"); return -ENOMEM; @@ -113,7 +118,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to map LCD registers\n"); return -ENOMEM; } - /* Mipi mmio */ if (!request_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE, "kmb-mipi")) { DRM_ERROR("failed to reserve MIPI registers\n"); @@ -126,35 +130,16 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) iounmap(dev_p->lcd_mmio); return -ENOMEM; } - /*this is only for MIPI_TX_MSS_LCD_MIPI_CFG register */ - dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR, + if (!dev_p->msscam_mmio) { + dev_p->msscam_mmio = ioremap_cache(MSS_CAM_BASE_ADDR, MSS_CAM_MMIO_SIZE); + } /* register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - * firmware has to redirect it to A53 */ - irq_lcd = platform_get_irq_byname(pdev, "irq_lcd"); - if (irq_lcd < 0) { - DRM_ERROR("irq_lcd not found"); - return irq_lcd; - } - pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd); - ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p); - dev_p->irq_lcd = irq_lcd; - - irq_mipi = platform_get_irq_byname(pdev, "irq_mipi"); - if (irq_mipi < 0) { - DRM_ERROR("irq_mipi not found"); - return irq_mipi; - } - pr_info("irq_mipi platform_get_irq = %d\n", irq_mipi); - ret = request_irq(irq_mipi, kmb_isr, IRQF_SHARED, "irq_mipi", dev_p); - dev_p->irq_mipi = irq_mipi; - - - /*TBD read and check for correct product version here */ /* Get the optional framebuffer memory resource */ @@ -169,52 +154,35 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } - /* find ADV7535 node and initialize it */ - encoder_node = of_parse_phandle(drm->dev->of_node, "encoder-slave", 0); - if (!encoder_node) { - DRM_ERROR("failed to get bridge info from DT\n"); - ret = -EPROBE_DEFER; - goto setup_fail; - } - - /* Locate drm bridge from the hdmi encoder DT node */ - bridge = of_drm_find_bridge(encoder_node); - if (!bridge) { - DRM_ERROR("failed to get bridge driver from DT\n"); - ret = -EPROBE_DEFER; - goto setup_fail; - } - - of_node_put(encoder_node); - - ret = kmb_dsi_init(drm, bridge); - if (ret) { +/* ret = kmb_dsi_init(drm, bridge);*/ + ret = kmb_dsi_init(drm); + if (ret == -EPROBE_DEFER) { + DRM_INFO("%s: wait for external bridge driver DT", __func__); + return -EPROBE_DEFER; + } else if (ret) { DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } - +} /* enable display clocks*/ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); if (!clk_lcd) { DRM_ERROR("clk_get() failed clk_lcd\n"); goto setup_fail; } + DRM_INFO("%s : %d\n", __func__, __LINE__); clk_mipi = clk_get(&pdev->dev, "clk_mipi"); if (!clk_mipi) { DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } + DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_display_clk_enable(); - ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); - if (ret < 0) { - DRM_ERROR("failed to install IRQ handler\n"); - goto irq_fail; - } + DRM_INFO("%s : %d\n", __func__, __LINE__); return 0; -irq_fail: drm_crtc_cleanup(&dev_p->crtc); setup_fail: of_reserved_mem_device_release(drm->dev); @@ -349,40 +317,38 @@ static int kmb_drm_bind(struct device *dev) kmb_setup_mode_config(drm); DRM_DEBUG("kmb_bind : after kmb_setup_mode_config\n"); ret = kmb_load(drm, 0); - if (ret) + DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); + if (ret == -EPROBE_DEFER) { + DRM_INFO("kmb_bind: wait for external bridge driver DT\n"); + return -EPROBE_DEFER; + } else if (ret) goto err_free; + DRM_INFO("%s : %d\n", __func__, __LINE__); /* Set the CRTC's port so that the encoder component can find it */ lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); - - ret = component_bind_all(dev, drm); - if (ret) { - DRM_ERROR("Failed to bind all components\n"); - goto err_unload; - } - - ret = pm_runtime_set_active(dev); - if (ret) - goto err_pm_active; - - pm_runtime_enable(dev); - + DRM_INFO("crtc port = %pOF\n", lcd->crtc.port); ret = drm_vblank_init(drm, drm->mode_config.num_crtc); if (ret < 0) { DRM_ERROR("failed to initialise vblank\n"); goto err_vblank; } + DRM_INFO("%s : %d\n", __func__, __LINE__); drm_mode_config_reset(drm); + DRM_INFO("%s : %d\n", __func__, __LINE__); drm_kms_helper_poll_init(drm); + DRM_INFO("%s : %d\n", __func__, __LINE__); ret = drm_dev_register(drm, 0); + DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); lcd->n_layers = KMB_MAX_PLANES; if (ret) goto err_register; drm_fbdev_generic_setup(drm, 32); + DRM_INFO("%s : %d\n", __func__, __LINE__); return 0; @@ -390,9 +356,7 @@ static int kmb_drm_bind(struct device *dev) drm_kms_helper_poll_fini(drm); err_vblank: pm_runtime_disable(drm->dev); -err_pm_active: component_unbind_all(dev, drm); -err_unload: of_node_put(lcd->crtc.port); lcd->crtc.port = NULL; drm_irq_uninstall(drm); @@ -451,16 +415,10 @@ static const struct component_master_ops kmb_master_ops = { .unbind = kmb_drm_unbind, }; -static int compare_dev(struct device *dev, void *data) -{ - return dev->of_node == data; -} - static int kmb_probe(struct platform_device *pdev) { struct device_node *port; - struct component_match *match = NULL; - int ret; + int ret = 0; /* there is only one output port inside each device, find it */ DRM_DEBUG("%s : ENTER", __func__); @@ -469,18 +427,8 @@ static int kmb_probe(struct platform_device *pdev) DRM_DEBUG("%s : port = 0x%pOF\n", __func__, port); if (!port) return -ENODEV; - - DRM_DEBUG("%s : after get_remote", __func__); - DRM_DEBUG("Adding component %pOF\n", port); - drm_of_component_match_add(&pdev->dev, &match, compare_dev, port); - DRM_DEBUG("%s : after get_match", __func__); - of_node_put(port); - - ret = component_master_add_with_match(&pdev->dev, &kmb_master_ops, - match); - DRM_DEBUG("%s : EXIT ret=%d\n", __func__, ret); - return ret; + return kmb_drm_bind(&pdev->dev); } static int kmb_remove(struct platform_device *pdev) @@ -532,13 +480,13 @@ static int __maybe_unused kmb_pm_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(kmb_pm_ops, kmb_pm_suspend, kmb_pm_resume); static struct platform_driver kmb_platform_driver = { - .probe = kmb_probe, - .remove = kmb_remove, - .driver = { - .name = "Keembay_Display", - .pm = &kmb_pm_ops, - .of_match_table = kmb_of_match, - }, + .probe = kmb_probe, + .remove = kmb_remove, + .driver = { + .name = "kmb_display", + .pm = &kmb_pm_ops, + .of_match_table = kmb_of_match, + }, }; module_platform_driver(kmb_platform_driver); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 01014c8..cc7fb0e 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -289,10 +289,12 @@ static const struct mipi_dsi_host_ops kmb_dsi_host_ops = { .transfer = kmb_dsi_host_transfer, }; -static struct kmb_dsi_host *kmb_dsi_host_init(struct kmb_dsi *kmb_dsi) +static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, + struct kmb_dsi *kmb_dsi) { struct kmb_dsi_host *host; struct mipi_dsi_device *device; + int err; host = kzalloc(sizeof(*host), GFP_KERNEL); if (!host) @@ -306,6 +308,15 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct kmb_dsi *kmb_dsi) kfree(host); return NULL; } + + host->base.dev = drm->dev; + err = mipi_dsi_host_register(&host->base); + if (err < 0) { + DRM_ERROR("failed to register DSI host: %d\n", err); + kfree(host); + kfree(device); + } + device->host = &host->base; host->device = device; return host; @@ -1293,7 +1304,8 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) } -int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) +//int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) +int kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; @@ -1301,6 +1313,8 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) struct drm_connector *connector; struct kmb_dsi_host *host; struct kmb_drm_private *dev_p = dev->dev_private; + struct device_node *encoder_node; + struct drm_bridge *bridge; int ret = 0; kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); @@ -1325,7 +1339,7 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, "MIPI-DSI"); - host = kmb_dsi_host_init(kmb_dsi); + host = kmb_dsi_host_init(dev, kmb_dsi); if (!host) { drm_encoder_cleanup(encoder); kfree(kmb_dsi); @@ -1336,8 +1350,30 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) DRM_MODE_CONNECTOR_DSI); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); - connector->encoder = encoder; - drm_connector_attach_encoder(connector, encoder); +// connector->encoder = encoder; + DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, __LINE__, + connector->name, encoder->name); + DRM_INFO("%s : %d connector->encoder = 0x%p\n", __func__, __LINE__, + connector->encoder); + + ret = drm_connector_attach_encoder(connector, encoder); + DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); + + /* find ADV7535 node and initialize it */ + DRM_DEBUG("trying to get bridge info %pOF\n", dev->dev->of_node); + encoder_node = of_parse_phandle(dev->dev->of_node, "encoder-slave", 0); + DRM_DEBUG("encoder node = %pOF\n", encoder_node); + if (!encoder_node) { + DRM_ERROR("failed to get bridge info from DT\n"); + ret = -EINVAL; + } + /* Locate drm bridge from the hdmi encoder DT node */ + bridge = of_drm_find_bridge(encoder_node); + of_node_put(encoder_node); + if (!bridge) { + DRM_INFO("wait for external bridge driver DT\n"); + return -EPROBE_DEFER; + } /* Link drm_bridge to encoder */ ret = drm_bridge_attach(encoder, bridge, NULL, 0); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 8135252..5da52c7 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -329,7 +329,8 @@ union mipi_irq_cfg { } irq_cfg; }; -int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); +//int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); +int kmb_dsi_init(struct drm_device *dev); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:42 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:42 -0700 Subject: [Intel-gfx] [PATCH 30/59] drm/kmb: call bridge init in the very beginning In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-31-git-send-email-anitha.chrisanthus@intel.com> of probe and return probe_defer early on, so that all the other initializations can be done after adv driver is loaded successfully. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 81 ++++++++++++++---------- drivers/gpu/drm/kmb/kmb_dsi.c | 144 ++++++++++++++++++++++++++---------------- drivers/gpu/drm/kmb/kmb_dsi.h | 6 +- 3 files changed, 141 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index f1bf258..81af972 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -57,11 +57,24 @@ static struct clk *clk_lcd; static struct clk *clk_mipi; static int probe_deferred; +struct drm_bridge *adv_bridge; static int kmb_display_clk_enable(void) { - clk_prepare_enable(clk_lcd); - clk_prepare_enable(clk_mipi); + int ret; + + ret = clk_prepare_enable(clk_lcd); + if (ret) { + DRM_ERROR("Failed to enable LCD clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(clk_mipi); + if (ret) { + DRM_ERROR("Failed to enable MIPI clock: %d\n", ret); + return ret; + } + DRM_INFO("SUCCESS : enabled LCD MIPI clocks\n"); return 0; } @@ -106,8 +119,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) *} */ /* LCD mmio */ - if (!probe_deferred) { - probe_deferred = 1; + probe_deferred = 1; if (!request_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE, "kmb-lcd")) { DRM_ERROR("failed to reserve LCD registers\n"); @@ -140,9 +152,10 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) * lists LCD at 79 and 82 for MIPI under MSS CPU - * firmware has to redirect it to A53 */ -/*TBD read and check for correct product version here */ - /* Get the optional framebuffer memory resource */ + /*TBD read and check for correct product version here */ + + /* Get the optional framebuffer memory resource */ ret = of_reserved_mem_device_init(drm->dev); if (ret && ret != -ENODEV) return ret; @@ -154,8 +167,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } -/* ret = kmb_dsi_init(drm, bridge);*/ - ret = kmb_dsi_init(drm); + ret = kmb_dsi_init(drm, adv_bridge); if (ret == -EPROBE_DEFER) { DRM_INFO("%s: wait for external bridge driver DT", __func__); return -EPROBE_DEFER; @@ -163,7 +175,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } -} /* enable display clocks*/ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); if (!clk_lcd) { @@ -177,10 +188,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) goto setup_fail; } DRM_INFO("%s : %d\n", __func__, __LINE__); - kmb_display_clk_enable(); - - DRM_INFO("%s : %d\n", __func__, __LINE__); + ret = kmb_display_clk_enable(); + DRM_INFO("%s : %d clk enabling ret=%d\n", __func__, __LINE__, ret); return 0; drm_crtc_cleanup(&dev_p->crtc); @@ -287,7 +297,7 @@ static struct drm_driver kmb_driver = { .gem_prime_vunmap = drm_gem_cma_prime_vunmap, .gem_prime_mmap = drm_gem_cma_prime_mmap, .fops = &fops, - .name = "kmb", + .name = "kmb_display", .desc = "KEEMBAY DISPLAY DRIVER ", .date = "20190122", .major = 1, @@ -296,26 +306,27 @@ static struct drm_driver kmb_driver = { static int kmb_drm_bind(struct device *dev) { - struct drm_device *drm; + struct drm_device *drm = NULL; struct kmb_drm_private *lcd; int ret; - DRM_DEBUG("kmb_bind : ENTER\n"); + DRM_DEBUG("%s : ENTER", __func__); drm = drm_dev_alloc(&kmb_driver, dev); if (IS_ERR(drm)) return PTR_ERR(drm); - DRM_DEBUG("kmb_bind : after alloc drm\n"); + DRM_DEBUG("%s : after alloc drm", __func__); lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL); if (!lcd) return -ENOMEM; - DRM_DEBUG("kmb_bind : after alloc lcd\n"); + DRM_DEBUG("%s : after alloc lcd", __func__); drm->dev_private = lcd; - dev_set_drvdata(dev, drm); kmb_setup_mode_config(drm); - DRM_DEBUG("kmb_bind : after kmb_setup_mode_config\n"); + dev_set_drvdata(dev, drm); + + /* load the driver */ ret = kmb_load(drm, 0); DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); if (ret == -EPROBE_DEFER) { @@ -356,7 +367,6 @@ static int kmb_drm_bind(struct device *dev) drm_kms_helper_poll_fini(drm); err_vblank: pm_runtime_disable(drm->dev); - component_unbind_all(dev, drm); of_node_put(lcd->crtc.port); lcd->crtc.port = NULL; drm_irq_uninstall(drm); @@ -374,9 +384,9 @@ static void kmb_drm_unbind(struct device *dev) struct drm_device *drm = dev_get_drvdata(dev); struct kmb_drm_private *dev_p = drm->dev_private; + dump_stack(); drm_dev_unregister(drm); drm_kms_helper_poll_fini(drm); - component_unbind_all(dev, drm); of_node_put(dev_p->crtc.port); dev_p->crtc.port = NULL; pm_runtime_get_sync(drm->dev); @@ -384,12 +394,15 @@ static void kmb_drm_unbind(struct device *dev) pm_runtime_put_sync(drm->dev); pm_runtime_disable(drm->dev); + DRM_INFO("%s : %d\n", __func__, __LINE__); if (dev_p->lcd_mmio) { + DRM_INFO("%s : %d\n", __func__, __LINE__); iounmap(dev_p->lcd_mmio); release_mem_region(LCD_BASE_ADDR, LCD_MMIO_SIZE); } if (dev_p->mipi_mmio) { + DRM_INFO("%s : %d\n", __func__, __LINE__); iounmap(dev_p->mipi_mmio); release_mem_region(MIPI_BASE_ADDR, MIPI_MMIO_SIZE); } @@ -397,6 +410,7 @@ static void kmb_drm_unbind(struct device *dev) if (dev_p->msscam_mmio) iounmap(dev_p->msscam_mmio); + DRM_INFO("%s : %d\n", __func__, __LINE__); of_reserved_mem_device_release(drm->dev); drm_mode_config_cleanup(drm); @@ -408,32 +422,31 @@ static void kmb_drm_unbind(struct device *dev) drm_dev_put(drm); drm->dev_private = NULL; dev_set_drvdata(dev, NULL); + DRM_INFO("%s : %d\n", __func__, __LINE__); } -static const struct component_master_ops kmb_master_ops = { - .bind = kmb_drm_bind, - .unbind = kmb_drm_unbind, -}; - static int kmb_probe(struct platform_device *pdev) { - struct device_node *port; - int ret = 0; + struct device *device = get_device(&pdev->dev); /* there is only one output port inside each device, find it */ DRM_DEBUG("%s : ENTER", __func__); - port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0); - DRM_DEBUG("%s : port = 0x%pOF\n", __func__, port); - if (!port) - return -ENODEV; - DRM_DEBUG("%s : EXIT ret=%d\n", __func__, ret); + adv_bridge = kmb_dsi_host_bridge_init(device); + if (adv_bridge == ERR_PTR(-EPROBE_DEFER)) + return -EPROBE_DEFER; + else if (adv_bridge < 0) { + DRM_ERROR(" PROBE failed\n"); + return -EINVAL; + } + return kmb_drm_bind(&pdev->dev); } static int kmb_remove(struct platform_device *pdev) { - component_master_del(&pdev->dev, &kmb_master_ops); +// component_master_del(&pdev->dev, &kmb_master_ops); + kmb_drm_unbind(&pdev->dev); return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index cc7fb0e..8741d78 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -79,6 +79,9 @@ #define PLL_M_MAX 623 #define PLL_FVCO_MAX 1250 +static struct mipi_dsi_host *dsi_host; +static struct mipi_dsi_device *dsi_device; + /* * These are added here only temporarily for testing, * these will eventually go to the device tree sections, @@ -293,33 +296,68 @@ static struct kmb_dsi_host *kmb_dsi_host_init(struct drm_device *drm, struct kmb_dsi *kmb_dsi) { struct kmb_dsi_host *host; - struct mipi_dsi_device *device; - int err; host = kzalloc(sizeof(*host), GFP_KERNEL); if (!host) return NULL; - host->base.ops = &kmb_dsi_host_ops; + host->base = dsi_host; + host->base->ops = &kmb_dsi_host_ops; host->kmb_dsi = kmb_dsi; - device = kzalloc(sizeof(*device), GFP_KERNEL); - if (!device) { - kfree(host); - return NULL; - } + host->base->dev = drm->dev; + + dsi_device->host = host->base; + host->device = dsi_device; + return host; +} - host->base.dev = drm->dev; - err = mipi_dsi_host_register(&host->base); - if (err < 0) { - DRM_ERROR("failed to register DSI host: %d\n", err); - kfree(host); - kfree(device); +struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) +{ + int ret; + struct device_node *encoder_node; + struct drm_bridge *bridge; + + if (!dsi_host) { + dsi_host = kzalloc(sizeof(*dsi_host), GFP_KERNEL); + if (!dsi_host) + return ERR_PTR(-ENOMEM); + + dsi_host->ops = &kmb_dsi_host_ops; + + if (!dsi_device) + dsi_device = kzalloc(sizeof(*dsi_device), GFP_KERNEL); + if (!dsi_device) { + kfree(dsi_host); + return ERR_PTR(-ENOMEM); + } + + dsi_host->dev = dev; + ret = mipi_dsi_host_register(dsi_host); + if (ret < 0) { + DRM_ERROR("failed to register DSI host: %d\n", ret); + kfree(dsi_host); + kfree(dsi_device); + return ERR_PTR(ret); + } } - device->host = &host->base; - host->device = device; - return host; + /* find ADV7535 node and initialize it */ + DRM_DEBUG("trying to get bridge info %pOF\n", dev->of_node); + encoder_node = of_parse_phandle(dev->of_node, "encoder-slave", 0); + DRM_DEBUG("encoder node = %pOF\n", encoder_node); + if (!encoder_node) { + DRM_ERROR("failed to get bridge info from DT\n"); + ret = -EINVAL; + } + /* Locate drm bridge from the hdmi encoder DT node */ + bridge = of_drm_find_bridge(encoder_node); + of_node_put(encoder_node); + if (!bridge) { + DRM_INFO("wait for external bridge driver DT\n"); + return ERR_PTR(-EPROBE_DEFER); + } + return bridge; } u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, @@ -682,7 +720,8 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, u32 sync_cfg = 0, ctrl = 0, fg_en; u32 ctrl_no = MIPI_CTRL6; - /*MIPI_TX_HS_SYNC_CFG */ + DRM_INFO("%s : %d\n", __func__, __LINE__); + /*MIPI_TX_HS_SYNC_CFG*/ if (ctrl_cfg->tx_ctrl_cfg.line_sync_pkt_en) sync_cfg |= LINE_SYNC_PKT_ENABLE; if (ctrl_cfg->tx_ctrl_cfg.frame_counter_active) @@ -693,6 +732,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, sync_cfg |= DSI_V_BLANKING; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hsa_blanking) sync_cfg |= DSI_HSA_BLANKING; + DRM_INFO("%s : %d\n", __func__, __LINE__); if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hbp_blanking) sync_cfg |= DSI_HBP_BLANKING; if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->hfp_blanking) @@ -704,6 +744,7 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, if (ctrl_cfg->tx_ctrl_cfg.tx_dsi_cfg->lpm_last_vfp_line) sync_cfg |= DSI_LPM_LAST_VFP_LINE; /* enable frame generator */ + DRM_INFO("%s : %d\n", __func__, __LINE__); fg_en = 1 << fg_id; sync_cfg |= FRAME_GEN_EN(fg_en); if (ctrl_cfg->tx_ctrl_cfg.tx_always_use_hact) @@ -722,7 +763,9 @@ static void mipi_tx_ctrl_cfg(struct kmb_drm_private *dev_p, u8 fg_id, /*67 ns stop time */ ctrl |= HSEXIT_CNT(0x43); + DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_write_mipi(dev_p, MIPI_TXm_HS_SYNC_CFG(ctrl_no), sync_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_write_mipi(dev_p, MIPI_TXm_HS_CTRL(ctrl_no), ctrl); } @@ -1304,8 +1347,8 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) } -//int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) -int kmb_dsi_init(struct drm_device *dev) +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) +//int kmb_dsi_init(struct drm_device *dev) { struct kmb_dsi *kmb_dsi; struct drm_encoder *encoder; @@ -1313,10 +1356,9 @@ int kmb_dsi_init(struct drm_device *dev) struct drm_connector *connector; struct kmb_dsi_host *host; struct kmb_drm_private *dev_p = dev->dev_private; - struct device_node *encoder_node; - struct drm_bridge *bridge; int ret = 0; + DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_dsi = kzalloc(sizeof(*kmb_dsi), GFP_KERNEL); if (!kmb_dsi) { DRM_ERROR("failed to allocate kmb_dsi\n"); @@ -1330,52 +1372,44 @@ int kmb_dsi_init(struct drm_device *dev) return -ENOMEM; } + DRM_INFO("%s : %d\n", __func__, __LINE__); kmb_dsi->attached_connector = kmb_connector; - connector = &kmb_connector->base; - encoder = &kmb_dsi->base; - encoder->possible_crtcs = 1; - encoder->possible_clones = 0; - drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, - "MIPI-DSI"); - + DRM_INFO("%s : %d\n", __func__, __LINE__); host = kmb_dsi_host_init(dev, kmb_dsi); + DRM_INFO("%s : %d\n", __func__, __LINE__); if (!host) { - drm_encoder_cleanup(encoder); + DRM_ERROR("Faile to allocate host\n"); +// drm_encoder_cleanup(encoder); kfree(kmb_dsi); kfree(kmb_connector); + return -ENOMEM; } + DRM_INFO("%s : %d\n", __func__, __LINE__); + connector = &kmb_connector->base; + DRM_INFO("%s : %d\n", __func__, __LINE__); + encoder = &kmb_dsi->base; + encoder->possible_crtcs = 1; + encoder->possible_clones = 0; + DRM_INFO("%s : %d\n", __func__, __LINE__); + drm_encoder_init(dev, encoder, &kmb_dsi_funcs, DRM_MODE_ENCODER_DSI, + "MIPI-DSI"); + DRM_INFO("%s : %d\n", __func__, __LINE__); + drm_connector_init(dev, connector, &kmb_dsi_connector_funcs, - DRM_MODE_CONNECTOR_DSI); + DRM_MODE_CONNECTOR_DSI); + DRM_INFO("%s : %d\n", __func__, __LINE__); drm_connector_helper_add(connector, &kmb_dsi_connector_helper_funcs); + DRM_INFO("%s : %d\n", __func__, __LINE__); // connector->encoder = encoder; - DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, __LINE__, - connector->name, encoder->name); - DRM_INFO("%s : %d connector->encoder = 0x%p\n", __func__, __LINE__, - connector->encoder); + DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, + __LINE__, connector->name, encoder->name); ret = drm_connector_attach_encoder(connector, encoder); - DRM_INFO("%s : %d ret = %d\n", __func__, __LINE__, ret); - - /* find ADV7535 node and initialize it */ - DRM_DEBUG("trying to get bridge info %pOF\n", dev->dev->of_node); - encoder_node = of_parse_phandle(dev->dev->of_node, "encoder-slave", 0); - DRM_DEBUG("encoder node = %pOF\n", encoder_node); - if (!encoder_node) { - DRM_ERROR("failed to get bridge info from DT\n"); - ret = -EINVAL; - } - /* Locate drm bridge from the hdmi encoder DT node */ - bridge = of_drm_find_bridge(encoder_node); - of_node_put(encoder_node); - if (!bridge) { - DRM_INFO("wait for external bridge driver DT\n"); - return -EPROBE_DEFER; - } - /* Link drm_bridge to encoder */ + DRM_INFO("%s : %d\n", __func__, __LINE__); ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) { DRM_ERROR("failed to attach bridge to MIPI\n"); @@ -1383,14 +1417,18 @@ int kmb_dsi_init(struct drm_device *dev) return ret; } + DRM_INFO("%s : %d\n", __func__, __LINE__); /* initialize mipi controller */ mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__); /*d-phy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__); /* irq initialization */ mipi_tx_init_irqs(dev_p, &int_cfg, &mipi_tx_init_cfg.tx_ctrl_cfg); + DRM_INFO("%s : %d\n", __func__, __LINE__); return 0; } diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index 5da52c7..cf234db 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -42,7 +42,7 @@ struct kmb_dsi { }; struct kmb_dsi_host { - struct mipi_dsi_host base; + struct mipi_dsi_host *base; struct kmb_dsi *kmb_dsi; struct mipi_dsi_device *device; }; @@ -329,8 +329,8 @@ union mipi_irq_cfg { } irq_cfg; }; -//int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); -int kmb_dsi_init(struct drm_device *dev); +struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev); +int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:45 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:45 -0700 Subject: [Intel-gfx] [PATCH 33/59] drm/kmb: Initialize clocks for clk_msscam, clk_mipi_ecfg, & clk_mipi_cfg. In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-34-git-send-email-anitha.chrisanthus@intel.com> From: Edmund Dea <edmund.j.dea at intel.com> Note that we enable clk_msscam but do not set clk_msscam. However, we do enable and set clk_mipi_ecfg and clk_mipi_cfg. Verify that LCD and MIPI clocks are set successfully. Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 112 +++++++++++++++++++++++++++++++++++++----- drivers/gpu/drm/kmb/kmb_drv.h | 2 + 2 files changed, 102 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 0588bd0..48c2b28 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -56,6 +56,9 @@ static irqreturn_t kmb_isr(int irq, void *arg); static struct clk *clk_lcd; static struct clk *clk_mipi; +static struct clk *clk_msscam; +static struct clk *clk_mipi_ecfg; +static struct clk *clk_mipi_cfg; struct drm_bridge *adv_bridge; @@ -74,6 +77,24 @@ static int kmb_display_clk_enable(void) DRM_ERROR("Failed to enable MIPI clock: %d\n", ret); return ret; } + + ret = clk_prepare_enable(clk_msscam); + if (ret) { + DRM_ERROR("Failed to enable MSSCAM clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(clk_mipi_ecfg); + if (ret) { + DRM_ERROR("Failed to enable MIPI_ECFG clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(clk_mipi_cfg); + if (ret) { + DRM_ERROR("Failed to enable MIPI_CFG clock: %d\n", ret); + return ret; + } DRM_INFO("SUCCESS : enabled LCD MIPI clocks\n"); return 0; } @@ -84,6 +105,12 @@ static int kmb_display_clk_disable(void) clk_disable_unprepare(clk_lcd); if (clk_mipi) clk_disable_unprepare(clk_mipi); + if (clk_msscam) + clk_disable_unprepare(clk_msscam); + if (clk_mipi_ecfg) + clk_disable_unprepare(clk_mipi_ecfg); + if (clk_mipi_cfg) + clk_disable_unprepare(clk_mipi_cfg); return 0; } @@ -118,6 +145,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) struct platform_device *pdev = to_platform_device(drm->dev); /*u32 version;*/ int ret = 0; + unsigned long clk; /* Map LCD MMIO registers */ dev_p->lcd_mmio = kmb_map_mmio(pdev, "lcd_regs"); @@ -128,7 +156,6 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) /* Map MIPI MMIO registers */ dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs"); - if (IS_ERR(dev_p->mipi_mmio)) { DRM_ERROR("failed to map MIPI registers\n"); iounmap(dev_p->lcd_mmio); @@ -146,33 +173,94 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) return -ENOMEM; } - /* enable display clocks*/ + /* Enable display clocks*/ clk_lcd = clk_get(&pdev->dev, "clk_lcd"); - if (!clk_lcd) { + if (IS_ERR(clk_lcd)) { DRM_ERROR("clk_get() failed clk_lcd\n"); goto setup_fail; } - DRM_INFO("%s : %d\n", __func__, __LINE__); clk_mipi = clk_get(&pdev->dev, "clk_mipi"); - if (!clk_mipi) { + if (IS_ERR(clk_mipi)) { DRM_ERROR("clk_get() failed clk_mipi\n"); goto setup_fail; } - DRM_INFO("%s : %d\n", __func__, __LINE__); + + clk_msscam = clk_get(&pdev->dev, "clk_msscam"); + if (IS_ERR(clk_msscam)) { + DRM_ERROR("clk_get() failed clk_msscam\n"); + goto setup_fail; + } + + clk_mipi_ecfg = clk_get(&pdev->dev, "clk_mipi_ecfg"); + if (IS_ERR(clk_mipi_ecfg)) { + DRM_ERROR("clk_get() failed clk_mipi_ecfg\n"); + goto setup_fail; + } + + clk_mipi_cfg = clk_get(&pdev->dev, "clk_mipi_cfg"); + if (IS_ERR(clk_mipi_cfg)) { + DRM_ERROR("clk_get() failed clk_mipi_cfg\n"); + goto setup_fail; + } + ret = kmb_display_clk_enable(); - /* set LCD clock to 200 Mhz*/ + /* Set LCD clock to 200 Mhz*/ DRM_INFO("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); - ret = clk_set_rate(clk_lcd, 200000000); - DRM_INFO("Setting LCD clock tp 200Mhz ret = %d\n", ret); + ret = clk_set_rate(clk_lcd, KMB_LCD_DEFAULT_CLK); + if (clk_get_rate(clk_lcd) != KMB_LCD_DEFAULT_CLK) { + DRM_ERROR("failed to set to clk_lcd to %d\n", + KMB_LCD_DEFAULT_CLK); + goto setup_fail; + } + DRM_INFO("Setting LCD clock to %d Mhz ret = %d\n", + KMB_LCD_DEFAULT_CLK/1000000, ret); DRM_INFO("Get clk_lcd after set = %ld\n", clk_get_rate(clk_lcd)); - /* set MIPI clock to 24 Mhz*/ + + /* Set MIPI clock to 24 Mhz*/ DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); - ret = clk_set_rate(clk_mipi, 24000000); - DRM_INFO("Setting MIPI clock tp 24Mhz ret = %d\n", ret); + ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); + if (clk_get_rate(clk_mipi) != KMB_MIPI_DEFAULT_CLK) { + DRM_ERROR("failed to set to clk_mipi to %d\n", + KMB_MIPI_DEFAULT_CLK); + goto setup_fail; + } + DRM_INFO("Setting MIPI clock to %d Mhz ret = %d\n", + KMB_MIPI_DEFAULT_CLK/1000000, ret); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); + clk = clk_get_rate(clk_mipi_ecfg); + if (clk != KMB_MIPI_DEFAULT_CLK) { + /* Set MIPI_ECFG clock to 24 Mhz*/ + DRM_INFO("Get clk_mipi_ecfg before set = %ld\n", clk); + ret = clk_set_rate(clk_mipi_ecfg, KMB_MIPI_DEFAULT_CLK); + clk = clk_get_rate(clk_mipi_ecfg); + if (clk != KMB_MIPI_DEFAULT_CLK) { + DRM_ERROR("failed to set to clk_mipi_ecfg to %d\n", + KMB_MIPI_DEFAULT_CLK); + goto setup_fail; + } + DRM_INFO("Setting MIPI_ECFG clock tp %d Mhz ret = %d\n", + KMB_MIPI_DEFAULT_CLK/1000000, ret); + DRM_INFO("Get clk_mipi_ecfg after set = %ld\n", clk); + } + + clk = clk_get_rate(clk_mipi_cfg); + if (clk != KMB_MIPI_DEFAULT_CLK) { + /* Set MIPI_CFG clock to 24 Mhz*/ + DRM_INFO("Get clk_mipi_cfg before set = %ld\n", clk); + ret = clk_set_rate(clk_mipi_cfg, 24000000); + clk = clk_get_rate(clk_mipi_cfg); + if (clk != KMB_MIPI_DEFAULT_CLK) { + DRM_ERROR("failed to set to clk_mipi_cfg to %d\n", + KMB_MIPI_DEFAULT_CLK); + goto setup_fail; + } + DRM_INFO("Setting MIPI_CFG clock tp 24Mhz ret = %d\n", ret); + DRM_INFO("Get clk_mipi_cfg after set = %ld\n", clk); + } + #ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 6c1d687..9e3bb83 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -30,6 +30,8 @@ #define KMB_MAX_WIDTH 16384 /*max width in pixels */ #define KMB_MAX_HEIGHT 16384 /*max height in pixels */ +#define KMB_LCD_DEFAULT_CLK 200000000 +#define KMB_MIPI_DEFAULT_CLK 24000000 struct kmb_drm_private { struct drm_device drm; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:46 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:46 -0700 Subject: [Intel-gfx] [PATCH 34/59] drm/kmb: Enable MSS_CAM_CLK_CTRL for LCD and MIPI In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-35-git-send-email-anitha.chrisanthus@intel.com> Enable clocks for LCD, mipi common and mipi tx0 Renamed MSS_CAM_CLK_CTRL and also fixed bug in the call to set this register. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 8 ++++---- drivers/gpu/drm/kmb/kmb_drv.h | 14 ++++++++++++++ drivers/gpu/drm/kmb/kmb_dsi.c | 6 ++++-- drivers/gpu/drm/kmb/kmb_regs.h | 7 ++++++- 4 files changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 48c2b28..4eb472b 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -261,6 +261,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_INFO("Get clk_mipi_cfg after set = %ld\n", clk); } + /* enable MSS_CAM_CLK_CTRL for MIPI TX and LCD */ + kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, LCD | MIPI_COMMON | + MIPI_TX0); #ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - @@ -312,10 +315,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) /* Initialize MIPI DSI */ ret = kmb_dsi_init(drm, adv_bridge); - if (ret == -EPROBE_DEFER) { - DRM_INFO("%s: wait for external bridge driver DT", __func__); - return -EPROBE_DEFER; - } else if (ret) { + if (ret) { DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 9e3bb83..596f4fe 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -108,6 +108,20 @@ static inline void kmb_write_msscam(struct kmb_drm_private *dev_p, writel(value, (dev_p->msscam_mmio + reg)); } +static inline u32 kmb_read_msscam(struct kmb_drm_private *dev_p, + unsigned int reg) +{ + return readl(dev_p->msscam_mmio + reg); +} + +static inline void kmb_set_bitmask_msscam(struct kmb_drm_private *dev_p, + unsigned int reg, u32 mask) +{ + u32 reg_val = kmb_read_msscam(dev_p, reg); + + kmb_write_msscam(dev_p, reg, (reg_val | mask)); +} + static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg) { return readl(dev_p->lcd_mmio + reg); diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index af04eb9..8ab4de7 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -814,9 +814,11 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, active_vchannels++; /*connect lcd to mipi */ - kmb_write_msscam(dev_p, MSS_CAM_BASE_ADDR + - MIPI_TX_MSS_LCD_MIPI_CFG, 1); + kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); + /*stop iterating as only one virtual channel shall be used for + * LCD connection + */ break; } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index f8a7abf..20b331d 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -697,6 +697,11 @@ & (1 << (dphy - MIPI_DPHY6))) #define DPHY_CFG_CLK_EN (0x18c) -#define MIPI_TX_MSS_LCD_MIPI_CFG (0x04) +#define MSS_LCD_MIPI_CFG (0x04) +#define MSS_CAM_CLK_CTRL (0x10) +#define LCD (1<<1) +#define MIPI_COMMON (1<<2) +#define MIPI_TX0 (1<<9) + #define BIT_MASK_16 (0xffff) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:53 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:53 -0700 Subject: [Intel-gfx] [PATCH 41/59] drm/kmb: Changes for LCD to Mipi In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-42-git-send-email-anitha.chrisanthus@intel.com> Also free dsi resources on driver unload. System clock frequency change for llp ratio calculation. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 21 ++++--- drivers/gpu/drm/kmb/kmb_drv.c | 6 +- drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_dsi.c | 135 +++++++++++----------------------------- drivers/gpu/drm/kmb/kmb_dsi.h | 2 +- drivers/gpu/drm/kmb/kmb_plane.c | 24 +++---- drivers/gpu/drm/kmb/kmb_regs.h | 2 + 7 files changed, 68 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 9275f77..f8b4fde 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -108,11 +108,14 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) vm.vfront_porch = 0; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; vm.vback_porch = 0; - vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; +// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; + vm.vsync_len = 1; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; - vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; - vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; + vm.hback_porch = 0; + //vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; + vm.hsync_len = 1; +// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; @@ -124,13 +127,13 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) vm.hback_porch, vm.hfront_porch, vm.hsync_len); kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT, m->crtc_vdisplay - 1); - kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch - 1); - kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch - 1); + kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch); + kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch); kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1); kmb_write_lcd(dev->dev_private, LCD_H_ACTIVEWIDTH, m->crtc_hdisplay - 1); - kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch - 1); - kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch - 1); + kmb_write_lcd(dev->dev_private, LCD_H_BACKPORCH, vm.hback_porch); + kmb_write_lcd(dev->dev_private, LCD_H_FRONTPORCH, vm.hfront_porch); kmb_write_lcd(dev->dev_private, LCD_HSYNC_WIDTH, vm.hsync_len - 1); /*this is hardcoded as 0 in the Myriadx code */ kmb_write_lcd(dev->dev_private, LCD_VSYNC_START, 0); @@ -140,9 +143,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); kmb_write_lcd(dev->dev_private, - LCD_V_BACKPORCH_EVEN, vm.vback_porch - 1); + LCD_V_BACKPORCH_EVEN, vm.vback_porch); kmb_write_lcd(dev->dev_private, - LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); + LCD_V_FRONTPORCH_EVEN, vm.vfront_porch); kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); /*this is hardcoded as 10 in the Myriadx code*/ diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index e2d57ca..3b4b7a1 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -236,7 +236,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) #endif /* Set MIPI clock to 24 Mhz*/ DRM_INFO("Get clk_mipi before set = %ld\n", clk_get_rate(clk_mipi)); -//#define MIPI_CLK +#define MIPI_CLK #ifdef MIPI_CLK ret = clk_set_rate(clk_mipi, KMB_MIPI_DEFAULT_CLK); DRM_INFO("Get clk_mipi after set = %ld\n", clk_get_rate(clk_mipi)); @@ -516,7 +516,7 @@ static void kmb_drm_unload(struct device *dev) dev_set_drvdata(dev, NULL); /* Unregister DSI host */ - dsi_host_unregister(); + kmb_dsi_host_unregister(); } static int kmb_probe(struct platform_device *pdev) @@ -587,7 +587,7 @@ static int kmb_probe(struct platform_device *pdev) drm_mode_config_cleanup(drm); dev_set_drvdata(dev, NULL); drm_dev_put(drm); - dsi_host_unregister(); + kmb_dsi_host_unregister(); return ret; } diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index 67ddf7a..c376944 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -35,6 +35,7 @@ #define KMB_LCD_DEFAULT_CLK 250000000 #define KMB_MIPI_DEFAULT_CLK 24000000 #define KMB_MIPI_DEFAULT_CFG_CLK 24000000 +#define KMB_SYS_CLK_MHZ 500 struct kmb_drm_private { struct drm_device drm; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index 91c6898..f06fd92 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -100,6 +100,7 @@ static struct mipi_dsi_device *dsi_device; * these will eventually go to the device tree sections, * and can be used as a refernce later for device tree additions */ +//#define RES_1920x1080 #ifdef RES_1920x1080 #define IMG_HEIGHT_LINES 1080 #define IMG_WIDTH_PX 1920 @@ -282,10 +283,18 @@ static int kmb_dsi_get_modes(struct drm_connector *connector) return num_modes; } +void kmb_dsi_host_unregister(void) +{ + DRM_INFO("%s : %d\n", __func__, __LINE__); + mipi_dsi_host_unregister(dsi_host); + kfree(dsi_host); +} + static void kmb_dsi_connector_destroy(struct drm_connector *connector) { struct kmb_connector *kmb_connector = to_kmb_connector(connector); + DRM_INFO("%s : %d\n", __func__, __LINE__); drm_connector_cleanup(connector); kfree(kmb_connector); } @@ -294,8 +303,19 @@ static void kmb_dsi_encoder_destroy(struct drm_encoder *encoder) { struct kmb_dsi *kmb_dsi = to_kmb_dsi(encoder); + DRM_INFO("%s : %d\n", __func__, __LINE__); + if (!kmb_dsi) + return; + + kfree(kmb_dsi->dsi_host); + drm_encoder_cleanup(encoder); + + kmb_dsi_connector_destroy(&kmb_dsi->attached_connector->base); + kfree(kmb_dsi); + if (!dsi_device) + kfree(dsi_device); } static const struct drm_encoder_funcs kmb_dsi_funcs = { @@ -405,13 +425,8 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev) return bridge; } -void dsi_host_unregister(void) -{ - mipi_dsi_host_unregister(dsi_host); -} - u32 mipi_get_datatype_params(u32 data_type, u32 data_mode, - struct mipi_data_type_params *params) + struct mipi_data_type_params *params) { struct mipi_data_type_params data_type_parameters; @@ -628,8 +643,10 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, /*Get system clock for blanking period cnfigurations */ /*TODO need to get system clock from clock driver */ - /* Assume 700 Mhz system clock for now */ - sysclk = 500; + /* 500 Mhz system clock minus 50 - to account for the difference in + * mipi clock speed in RTL tests + */ + sysclk = KMB_SYS_CLK_MHZ - 50; /*ppl-pixel packing layer, llp-low level protocol * frame genartor timing parameters are clocked on the system clock @@ -895,9 +912,6 @@ static u32 mipi_tx_init_cntrl(struct kmb_drm_private *dev_p, active_vchannels++; - /*connect lcd to mipi */ - kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); - /*stop iterating as only one virtual channel shall be used for * LCD connection */ @@ -1682,56 +1696,17 @@ void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p) } -void dma_transfer(struct kmb_drm_private *dev_p, int mipi_number, - u64 dma_start_address, int data_length) +void connect_lcd_to_mipi(struct kmb_drm_private *dev_p) { - u64 dma_cfg_adr_offset; - u64 dma_start_adr_offset; - u64 dma_length_adr_offset; - u32 reg_wr_data; - int axi_burst_length; - int mipi_fifo_flush; - int dma_pipelined_axi_en; - int dma_en; - int dma_autorestart_mode_0; - int tx_rx; - - DRM_INFO("%s: starting a new DMA transfer for mipi %d ", __func__, - mipi_number); - - if (mipi_number < 6) - tx_rx = 0; - else - tx_rx = 1; - - dma_cfg_adr_offset = - MIPI_TX_HS_DMA_CFG + HS_OFFSET(mipi_number); - dma_start_adr_offset = - MIPI_TX_HS_DMA_START_ADR_CHAN0 + HS_OFFSET(mipi_number); - dma_length_adr_offset = - MIPI_TX_HS_DMA_LEN_CHAN0 + HS_OFFSET(mipi_number); - - reg_wr_data = 0; - reg_wr_data = dma_start_address; - kmb_write_mipi(dev_p, dma_start_adr_offset, reg_wr_data); - - reg_wr_data = 0; - reg_wr_data = data_length; - kmb_write_mipi(dev_p, dma_length_adr_offset, reg_wr_data); - - axi_burst_length = 16; - mipi_fifo_flush = 0; - dma_pipelined_axi_en = 1; - dma_en = 1; - dma_autorestart_mode_0 = 0; - - reg_wr_data = 0; - reg_wr_data = - ((axi_burst_length & 0x1ffff) << 0 | (mipi_fifo_flush & 0xf) << 9 | - (dma_pipelined_axi_en & 0x1) << 13 | (dma_en & 0xf) << 16 | - (dma_autorestart_mode_0 & 0x3) << 24); - - kmb_write_mipi(dev_p, dma_cfg_adr_offset, reg_wr_data); +#ifdef LCD_TEST + /*connect lcd to mipi */ + /*DISABLE MIPI->CIF CONNECTION*/ + kmb_write_msscam(dev_p, MSS_MIPI_CIF_CFG, 0); + /*ENABLE LCD->MIPI CONNECTION */ + kmb_write_msscam(dev_p, MSS_LCD_MIPI_CFG, 1); + /*DISABLE LCD->CIF LOOPBACK */ + kmb_write_msscam(dev_p, MSS_LOOPBACK_CFG, 0); +#endif } /** @@ -1773,46 +1748,12 @@ int kmb_dsi_hw_init(struct drm_device *dev) mipi_tx_init_cntrl(dev_p, &mipi_tx_init_cfg); /*d-phy initialization */ mipi_tx_init_dphy(dev_p, &mipi_tx_init_cfg); + connect_lcd_to_mipi(dev_p); #ifdef MIPI_TX_TEST_PATTERN_GENERATION mipi_tx_hs_tp_gen(dev_p, 0, MIPI_TX_HS_TP_V_STRIPES, 0x15, 0xff, 0xff00, MIPI_CTRL6); DRM_INFO("%s : %d IRQ_STATUS = 0x%x\n", __func__, __LINE__, GET_MIPI_TX_HS_IRQ_STATUS(dev_p, MIPI_CTRL6)); -#elseif MIPI_DMA - dma_data_length = image_height * image_width * unpacked_bytes; - file = filp_open(IMAGE_PATH, O_RDWR, 0); - if (IS_ERR(file)) { - DRM_ERROR("filp_open failed\n"); - return -EBADF; - } - - file_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); - if (!file_buf) { - DRM_ERROR("file_buf alloc failed\n"); - return -ENOMEM; - } - - i_size = i_size_read(file_inode(file)); - while (offset < i_size) { - - file_buf_len = kmb_kernel_read(file, offset, - file_buf, PAGE_SIZE); - if (file_buf_len < 0) { - rc = file_buf_len; - break; - } - if (file_buf_len == 0) - break; - offset += file_buf_len; - count++; - dma_tx_start_address = file_buf; - dma_transfer(dev_p, MIPI_CTRL6, dma_tx_start_address, - PAGE_SIZE); - - } - DRM_INFO("count = %d\n", count); - kfree(file_buf); - filp_close(file, NULL); #endif //MIPI_TX_TEST_PATTERN_GENERATION hw_initialized = true; @@ -1849,12 +1790,11 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) host = kmb_dsi_host_init(dev, kmb_dsi); if (!host) { DRM_ERROR("Faile to allocate host\n"); -// drm_encoder_cleanup(encoder); kfree(kmb_dsi); kfree(kmb_connector); return -ENOMEM; } - + kmb_dsi->dsi_host = host; connector = &kmb_connector->base; encoder = &kmb_dsi->base; encoder->possible_crtcs = 1; @@ -1869,7 +1809,6 @@ int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge) DRM_INFO("%s : %d connector = %s encoder = %s\n", __func__, __LINE__, connector->name, encoder->name); - DRM_INFO("%s : %d\n", __func__, __LINE__); ret = drm_connector_attach_encoder(connector, encoder); /* Link drm_bridge to encoder */ diff --git a/drivers/gpu/drm/kmb/kmb_dsi.h b/drivers/gpu/drm/kmb/kmb_dsi.h index d0196a4..d74dc29 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.h +++ b/drivers/gpu/drm/kmb/kmb_dsi.h @@ -339,7 +339,7 @@ struct drm_bridge *kmb_dsi_host_bridge_init(struct device *dev); int kmb_dsi_init(struct drm_device *dev, struct drm_bridge *bridge); void kmb_plane_destroy(struct drm_plane *plane); void mipi_tx_handle_irqs(struct kmb_drm_private *dev_p); -void dsi_host_unregister(void); +void kmb_dsi_host_unregister(void); int kmb_dsi_hw_init(struct drm_device *dev); #define to_kmb_connector(x) container_of(x, struct kmb_connector, base) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 008fd48..7aeca07 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -290,6 +290,8 @@ unsigned int set_bits_per_pixel(const struct drm_format_info *format) val = LCD_LAYER_32BPP; break; } + DRM_INFO("%s : %d bpp=0x%x\n", __func__, __LINE__, bpp); + val = LCD_LAYER_24BPP; return val; } @@ -372,9 +374,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_1 | LCD_DMA_LAYER_VSTRIDE_EN; */ - dma_cfg = LCD_DMA_LAYER_ENABLE - | LCD_DMA_LAYER_AXI_BURST_1 - | LCD_DMA_LAYER_VSTRIDE_EN; + dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN + | LCD_DMA_LAYER_AXI_BURST_16 | LCD_DMA_LAYER_CONT_UPDATE; /* disable DMA first */ kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), @@ -390,14 +391,13 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, width = fb->width; height = fb->height; - dma_len = width * height * fb->format->cpp[0]; + dma_len = width * height * 1; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN(plane_id), dma_len); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), - fb->pitches[0]); + kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id), width); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_LINE_WIDTH(plane_id), - (width*fb->format->cpp[0])); + (width)); /*program Cb/Cr for planar formats*/ if (num_planes > 1) { @@ -452,11 +452,11 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, } // ctrl |= LCD_CTRL_ENABLE; -// ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE -// | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_ONE_SHOT | LCD_CTRL_OUTPUT_ENABLED; + | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; + +// ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE +// | LCD_CTRL_ONE_SHOT | LCD_CTRL_OUTPUT_ENABLED; /*LCD is connected to MIPI on kmb * Therefore this bit is required for DSI Tx */ @@ -475,7 +475,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, } /*set background color to white*/ - kmb_write_lcd(dev_p, LCD_BG_COLOUR_LS, 0xffffff); +// kmb_write_lcd(dev_p, LCD_BG_COLOUR_LS, 0xffffff); /*leave RGB order,conversion mode and clip mode to default*/ /* do not interleave RGB channels for mipi Tx compatibility */ out_format |= LCD_OUTF_MIPI_RGB_MODE; diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 255c44d..67dd1f4 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -734,8 +734,10 @@ & (1 << (dphy - MIPI_DPHY6))) #define DPHY_CFG_CLK_EN (0x18c) +#define MSS_MIPI_CIF_CFG (0x00) #define MSS_LCD_MIPI_CFG (0x04) #define MSS_CAM_CLK_CTRL (0x10) +#define MSS_LOOPBACK_CFG (0x0C) #define LCD (1<<1) #define MIPI_COMMON (1<<2) #define MIPI_TX0 (1<<9) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:55 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:55 -0700 Subject: [Intel-gfx] [PATCH 43/59] drm/kmb: Changed name of driver to kmb-drm In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-44-git-send-email-anitha.chrisanthus@intel.com> name change Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/Makefile | 4 ++-- drivers/gpu/drm/kmb/kmb_drv.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/kmb/Makefile b/drivers/gpu/drm/kmb/Makefile index 8102bc9..527d737 100644 --- a/drivers/gpu/drm/kmb/Makefile +++ b/drivers/gpu/drm/kmb/Makefile @@ -1,2 +1,2 @@ -kmb-display-y := kmb_crtc.o kmb_drv.o kmb_plane.o kmb_dsi.o -obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-display.o +kmb-drm-y := kmb_crtc.o kmb_drv.o kmb_plane.o kmb_dsi.o +obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb-drm.o diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 3b4b7a1..64e45e7 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -466,7 +466,7 @@ static struct drm_driver kmb_driver = { .gem_prime_vunmap = drm_gem_cma_prime_vunmap, .gem_prime_mmap = drm_gem_cma_prime_mmap, .fops = &fops, - .name = "kmb_display", + .name = "kmb-drm", .desc = "KEEMBAY DISPLAY DRIVER ", .date = "20190122", .major = 1, @@ -644,7 +644,7 @@ static struct platform_driver kmb_platform_driver = { .probe = kmb_probe, .remove = kmb_remove, .driver = { - .name = "kmb_display", + .name = "kmb-drm", .pm = &kmb_pm_ops, .of_match_table = kmb_of_match, }, -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:57 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:57 -0700 Subject: [Intel-gfx] [PATCH 45/59] drm/kmb: Enable LCD interrupts In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-46-git-send-email-anitha.chrisanthus@intel.com> Enabled vblank interrupts for LCD. Signed-off-by: Anitha Chrisanithus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 35 +++++++++++++++-------------------- drivers/gpu/drm/kmb/kmb_drv.c | 41 +++++++++++++++++++++-------------------- drivers/gpu/drm/kmb/kmb_plane.c | 6 +++--- drivers/gpu/drm/kmb/kmb_regs.h | 2 +- 4 files changed, 40 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 75e78d7..b617507 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -61,7 +61,8 @@ static int kmb_crtc_enable_vblank(struct drm_crtc *crtc) kmb_write_lcd(dev->dev_private, LCD_VSTATUS_COMPARE, LCD_VSTATUS_COMPARE_VSYNC); /* enable vertical interrupt */ - kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, LCD_INT_VERT_COMP); + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); return 0; } @@ -72,13 +73,9 @@ static void kmb_crtc_disable_vblank(struct drm_crtc *crtc) /*clear interrupt */ kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_VERT_COMP); /* disable vertical interrupt */ - kmb_write_lcd(dev->dev_private, LCD_INT_ENABLE, 0); + kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); -/* TBD - * set the BIT2 (VERTICAL_COMPARE_INTERRUPT) of the LCD_INT_ENABLE register - * set the required bit LCD_VSTATUS_COMPARE register - * Not sure if anything needs to be done in the ICB - */ } static const struct drm_crtc_funcs kmb_crtc_funcs = { @@ -100,7 +97,7 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) struct videomode vm; int vsync_start_offset; int vsync_end_offset; -#endif + /* initialize mipi */ kmb_dsi_hw_init(dev, m); DRM_INFO("vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n", @@ -110,7 +107,6 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) m->crtc_hsync_start - m->crtc_hdisplay, m->crtc_htotal - m->crtc_hsync_end, m->crtc_hsync_end - m->crtc_hsync_start); -#ifdef LCD_TEST // vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay; vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; @@ -174,7 +170,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc, clk_prepare_enable(lcd->clk); kmb_crtc_mode_set_nofb(crtc); -// drm_crtc_vblank_on(crtc); + drm_crtc_vblank_on(crtc); } static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, @@ -185,33 +181,32 @@ static void kmb_crtc_atomic_disable(struct drm_crtc *crtc, /* always disable planes on the CRTC that is being turned off */ drm_atomic_helper_disable_planes_on_crtc(old_state, false); -// drm_crtc_vblank_off(crtc); + drm_crtc_vblank_off(crtc); clk_disable_unprepare(lcd->clk); } static void kmb_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *state) { - /* TBD */ - /*disable vblank interrupts here - * clear BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE - */ + struct drm_device *dev = crtc->dev; + + kmb_clr_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); } static void kmb_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state) { - /* TBD */ - /*enable vblank interrupts after - * set BIT 2 (VERTICAL_COMPARE_INTERRUPT) LCD_INT_ENABLE - */ + struct drm_device *dev = crtc->dev; + + kmb_set_bitmask_lcd(dev->dev_private, LCD_INT_ENABLE, + LCD_INT_VERT_COMP); spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event) drm_crtc_send_vblank_event(crtc, crtc->state->event); crtc->state->event = NULL; spin_unlock_irq(&crtc->dev->event_lock); - } static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = { diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 64e45e7..d987529 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -147,10 +147,8 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; struct platform_device *pdev = to_platform_device(drm->dev); -#ifdef WIP /*u32 version;*/ - int irq_lcd, irq_mipi; -#endif + int irq_lcd;// irq_mipi; int ret = 0; unsigned long clk; @@ -286,10 +284,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); #endif //KMB_CLOCKS -#ifdef WIP /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - - * firmware has to redirect it to A53 + * firmware has redirected 79 to A53 IRQ 33 */ DRM_INFO("platform_get_irq_byname %pOF\n", drm->dev->of_node); @@ -299,14 +296,12 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) irq_lcd = platform_get_irq_byname(pdev, "irq_lcd"); if (irq_lcd < 0) { DRM_ERROR("irq_lcd not found"); - return irq_lcd; + goto setup_fail; } pr_info("irq_lcd platform_get_irq = %d\n", irq_lcd); - ret = request_irq(irq_lcd, kmb_isr, IRQF_SHARED, "irq_lcd", dev_p); - dev_p->irq_lcd = irq_lcd; - +#ifdef WIP /* Allocate MIPI interrupt resources, enable interrupt line, * and setup IRQ handling */ @@ -342,19 +337,16 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("failed to initialize DSI\n"); goto setup_fail; } -#ifdef WIP - ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); + ret = drm_irq_install(drm, irq_lcd); if (ret < 0) { DRM_ERROR("failed to install IRQ handler\n"); goto irq_fail; } -#endif + dev_p->irq_lcd = irq_lcd; return 0; -#ifdef WIP irq_fail: drm_crtc_cleanup(&dev_p->crtc); -#endif setup_fail: of_reserved_mem_device_release(drm->dev); @@ -400,6 +392,11 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LINE_CMP); } + if (status & LCD_INT_LAYER) { + /* clear layer interrupts */ + kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, LCD_INT_LAYER); + } + if (status & LCD_INT_VERT_COMP) { /* read VSTATUS */ val = kmb_read_lcd(dev->dev_private, LCD_VSTATUS); @@ -419,23 +416,20 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) return IRQ_HANDLED; } +#ifdef MIPI_IRQ static irqreturn_t handle_mipi_irq(struct drm_device *dev) { mipi_tx_handle_irqs(dev->dev_private); return IRQ_HANDLED; } +#endif static irqreturn_t kmb_isr(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; - struct kmb_drm_private *dev_p = dev->dev_private; irqreturn_t ret = IRQ_NONE; - if (irq == dev_p->irq_lcd) - ret = handle_lcd_irq(dev); - else if (irq == dev_p->irq_mipi) - ret = handle_mipi_irq(dev); - + ret = handle_lcd_irq(dev); return ret; } @@ -566,6 +560,12 @@ static int kmb_probe(struct platform_device *pdev) /* Set the CRTC's port so that the encoder component can find it */ lcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0); + ret = drm_vblank_init(drm, drm->mode_config.num_crtc); + DRM_INFO("mode_config.num_crtc=%d\n", drm->mode_config.num_crtc); + if (ret < 0) { + DRM_ERROR("failed to initialize vblank\n"); + goto err_vblank; + } drm_mode_config_reset(drm); drm_kms_helper_poll_init(drm); @@ -582,6 +582,7 @@ static int kmb_probe(struct platform_device *pdev) err_register: drm_kms_helper_poll_fini(drm); +err_vblank: pm_runtime_disable(drm->dev); err_free: drm_mode_config_cleanup(drm); diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 3cd9b0d..1990e8c 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -175,9 +175,9 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, break; } - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), - ~LCD_DMA_LAYER_ENABLE); - kmb_write_lcd(dev_p, LCD_CONTROL, ~ctrl); + kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), + LCD_DMA_LAYER_ENABLE); + kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); } diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index c80646a..0249ea5 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -107,7 +107,7 @@ #define LAYER3_DMA_IDLE (1<<24) #define LAYER3_DMA_FIFO_OVERFLOW (1<<25) #define LAYER3_DMA_FIFO_UNDERFLOW (1<<26) - +#define LCD_INT_LAYER (0x07fffff8) #define LCD_INT_ENABLE (0x4 * 0x002) #define LCD_INT_CLEAR (0x4 * 0x003) #define LCD_LINE_COUNT (0x4 * 0x004) -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:27:59 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:27:59 -0700 Subject: [Intel-gfx] =?utf-8?b?W1BBVENIIDQ3LzU5XSBkcm0va21iOiBEb27igJl0?= =?utf-8?q?_inadvertantly_disable_LCD_controller?= In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-48-git-send-email-anitha.chrisanthus@intel.com> setbits instead of write dword for LCD_CONTROL register this was inadvertantly disabling the LCD controller. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 1990e8c..d87a3a2 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -178,6 +178,9 @@ static void kmb_plane_atomic_disable(struct drm_plane *plane, kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), LCD_DMA_LAYER_ENABLE); kmb_clr_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); + DRM_INFO("%s : %d lcd_ctrl = 0x%x lcd_int_enable=0x%x\n", + __func__, __LINE__, kmb_read_lcd(dev_p, LCD_CONTROL), + kmb_read_lcd(dev_p, LCD_INT_ENABLE)); } @@ -476,7 +479,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, */ ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; - kmb_write_lcd(dev_p, LCD_CONTROL, ctrl); + kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); /* FIXME no doc on how to set output format,these values are taken * from the Myriadx tests -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:00 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:00 -0700 Subject: [Intel-gfx] [PATCH 48/59] drm/kmb: SWAP R and B LCD Layer order In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-49-git-send-email-anitha.chrisanthus@intel.com> Set swap bit for the colors to display correctly when the format is RGB and not set when its BGR. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index d87a3a2..9f9ae57 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -218,54 +218,55 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE | LCD_LAYER_CRCB_ORDER; break; - /* packed formats */ + /* packed formats */ + /* looks hw requires B & G to be swapped when RGB */ case DRM_FORMAT_RGB332: - val = LCD_LAYER_FORMAT_RGB332; + val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_XBGR4444: - val = LCD_LAYER_FORMAT_RGBX4444 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBX4444; break; case DRM_FORMAT_ARGB4444: - val = LCD_LAYER_FORMAT_RGBA4444; + val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_ABGR4444: - val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBA4444; break; case DRM_FORMAT_XRGB1555: - val = LCD_LAYER_FORMAT_XRGB1555; + val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_XBGR1555: - val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_XRGB1555; break; case DRM_FORMAT_ARGB1555: - val = LCD_LAYER_FORMAT_RGBA1555; + val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_ABGR1555: - val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBA1555; break; case DRM_FORMAT_RGB565: - val = LCD_LAYER_FORMAT_RGB565; + val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_BGR565: - val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGB565; break; case DRM_FORMAT_RGB888: - val = LCD_LAYER_FORMAT_RGB888; + val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_BGR888: - val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGB888; break; case DRM_FORMAT_XRGB8888: - val = LCD_LAYER_FORMAT_RGBX8888; + val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_XBGR8888: - val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBX8888; break; case DRM_FORMAT_ARGB8888: - val = LCD_LAYER_FORMAT_RGBA8888; + val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; break; case DRM_FORMAT_ABGR8888: - val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER; + val = LCD_LAYER_FORMAT_RGBA8888; break; } DRM_INFO("%s : %d layer format val=%d\n", __func__, __LINE__, val); @@ -370,7 +371,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, val |= set_bits_per_pixel(fb->format); /*CHECKME Leon drvr sets it to 100 try this for now */ val |= LCD_LAYER_FIFO_100; - val |= LCD_LAYER_BGR_ORDER; kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); /*re-initialize interrupts */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:03 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:03 -0700 Subject: [Intel-gfx] [PATCH 51/59] drm/kmb: Write to LCD_LAYERn_CFG only once In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-52-git-send-email-anitha.chrisanthus@intel.com> From: Edmund Dea <edmund.j.dea at intel.com> Video artifacts appear during playback as horizontal lines that sporadically appear every few frames. Issue was caused by writing to LCD_LAYERn_CFG register twice during plane updates. Issue is fixed by writing to LCD_LAYERn_CFG only once. Removed plane_init_status so that there are no initialization dependencies during plane updates. Signed-off-by: Edmund Dea <edmund.j.dea at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 81 +++++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 8aa48b5..ebf29b2 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -118,7 +118,6 @@ static const u32 csc_coef_lcd[] = { }; /*plane initialization status */ -static int plane_init_status[KMB_MAX_PLANES] = { 0, 0, 0, 0 }; static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) { @@ -321,7 +320,6 @@ static void config_csc(struct kmb_drm_private *dev_p, int plane_id) kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]); kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]); kmb_write_lcd(dev_p, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]); - kmb_set_bitmask_lcd(dev_p, LCD_LAYERn_CFG(plane_id), LCD_LAYER_CSC_EN); } #endif @@ -410,19 +408,27 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, addr[V_PLANE]); } } - if (plane_init_status[plane_id] != INITIALIZED) { - kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w - 1); - kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h - 1); - kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); - kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y); - - val = set_pixel_format(fb->format->format); - val |= set_bits_per_pixel(fb->format); - /*CHECKME Leon drvr sets it to 100 try this for now */ - val |= LCD_LAYER_FIFO_100; - kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); - - switch (plane_id) { + + kmb_write_lcd(dev_p, LCD_LAYERn_WIDTH(plane_id), src_w-1); + kmb_write_lcd(dev_p, LCD_LAYERn_HEIGHT(plane_id), src_h-1); + kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); + kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y); + + val = set_pixel_format(fb->format->format); + val |= set_bits_per_pixel(fb->format); + /*CHECKME Leon drvr sets it to 100 try this for now */ + val |= LCD_LAYER_FIFO_100; + + if (val & LCD_LAYER_PLANAR_STORAGE) { + val |= LCD_LAYER_CSC_EN; + + /*enable CSC if input is planar and output is RGB */ + config_csc(dev_p, plane_id); + } + + kmb_write_lcd(dev_p, LCD_LAYERn_CFG(plane_id), val); + + switch (plane_id) { case LAYER_0: ctrl = LCD_CTRL_VL1_ENABLE; break; @@ -435,36 +441,28 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, case LAYER_3: ctrl = LCD_CTRL_GL2_ENABLE; break; - } + } - ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE - | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; + ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE + | LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED; - /*LCD is connected to MIPI on kmb - * Therefore this bit is required for DSI Tx - */ - ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; + /*LCD is connected to MIPI on kmb + * Therefore this bit is required for DSI Tx + */ + ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL; - kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); + kmb_set_bitmask_lcd(dev_p, LCD_CONTROL, ctrl); - /* FIXME no doc on how to set output format,these values are - * taken from the Myriadx tests - */ - out_format |= LCD_OUTF_FORMAT_RGB888; + /* FIXME no doc on how to set output format,these values are + * taken from the Myriadx tests + */ + out_format |= LCD_OUTF_FORMAT_RGB888; - if (val & LCD_LAYER_PLANAR_STORAGE) { - /*enable CSC if input is planar and output is RGB */ - config_csc(dev_p, plane_id); - } - - /*set background color to white */ - // kmb_write_lcd(dev_p, LCD_BG_COLOUR_LS, 0xffffff); - /*leave RGB order,conversion mode and clip mode to default */ - /* do not interleave RGB channels for mipi Tx compatibility */ - out_format |= LCD_OUTF_MIPI_RGB_MODE; - kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); - plane_init_status[plane_id] = INITIALIZED; - } + /* Leave RGB order,conversion mode and clip mode to default */ + /* do not interleave RGB channels for mipi Tx compatibility */ + out_format |= LCD_OUTF_MIPI_RGB_MODE; + // out_format |= LCD_OUTF_SYNC_MODE; + kmb_write_lcd(dev_p, LCD_OUT_FORMAT_CFG, out_format); dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN | LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16; @@ -474,9 +472,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, DRM_DEBUG("%s : %d dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", __func__, __LINE__, dma_cfg, kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); - - return; - #endif } -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:09 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:09 -0700 Subject: [Intel-gfx] [PATCH 57/59] drm/kmb: workaround for dma undeflow issue In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-58-git-send-email-anitha.chrisanthus@intel.com> Initial issue was that display remains shifted after undeflow, this fix is to recover the dma after underflow so display is clean. Major changes are reduce LCD_CLK to 200Mhz and some changes in the lcd timing params run recovery sequence at the EOF after underflow happens do nothing in plan_update() during recovery reenable dma at the vsync interrupt after recovery is done Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_crtc.c | 27 +++---- drivers/gpu/drm/kmb/kmb_drv.c | 156 +++++++++++++++++++++++++++++++--------- drivers/gpu/drm/kmb/kmb_drv.h | 33 +++++---- drivers/gpu/drm/kmb/kmb_plane.c | 12 +++- drivers/gpu/drm/kmb/kmb_plane.h | 29 ++++---- drivers/gpu/drm/kmb/kmb_regs.h | 7 +- 6 files changed, 188 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index c01977b..c70928c 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -115,25 +115,25 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) vm.vfront_porch = 2; // vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end; vm.vback_porch = 2; -// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; - vm.vsync_len = 1; +// vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start; + vm.vsync_len = 8; //vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay; vm.hfront_porch = 0; vm.hback_porch = 0; //vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end; - vm.hsync_len = 7; -// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; + vm.hsync_len = 28; +// vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start; - vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; - vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; + vsync_start_offset = m->crtc_vsync_start - m->crtc_hsync_start; + vsync_end_offset = m->crtc_vsync_end - m->crtc_hsync_end; - DRM_DEBUG - ("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d", - __func__, __LINE__, m->crtc_vdisplay, vm.vback_porch, - vm.vfront_porch, vm.vsync_len, m->crtc_hdisplay, vm.hback_porch, - vm.hfront_porch, vm.hsync_len); + DRM_DEBUG("%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d", + __func__, __LINE__, + m->crtc_vdisplay, vm.vback_porch, vm.vfront_porch, + vm.vsync_len, m->crtc_hdisplay, vm.hback_porch, + vm.hfront_porch, vm.hsync_len); kmb_write_lcd(dev->dev_private, LCD_V_ACTIVEHEIGHT, - m->crtc_vdisplay - 1); + m->crtc_vdisplay - 1); kmb_write_lcd(dev->dev_private, LCD_V_BACKPORCH, vm.vback_porch); kmb_write_lcd(dev->dev_private, LCD_V_FRONTPORCH, vm.vfront_porch); kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH, vm.vsync_len - 1); @@ -145,7 +145,8 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) /*this is hardcoded as 0 in the Myriadx code */ kmb_write_lcd(dev->dev_private, LCD_VSYNC_START, 0); kmb_write_lcd(dev->dev_private, LCD_VSYNC_END, 0); - + /* back ground color */ + kmb_write_lcd(dev->dev_private, LCD_BG_COLOUR_LS, 0x4); if (m->flags == DRM_MODE_FLAG_INTERLACE) { kmb_write_lcd(dev->dev_private, LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1); diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index 68e7b5c..bafc02a 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -51,10 +51,10 @@ #include "kmb_dsi.h" //#define DEBUG - /* IRQ handler */ static irqreturn_t kmb_isr(int irq, void *arg); +int under_flow = 0, flush_done = 0, layer_no = 0; static struct clk *clk_lcd; static struct clk *clk_mipi; static struct clk *clk_mipi_ecfg; @@ -133,6 +133,7 @@ static void __iomem *kmb_map_mmio(struct platform_device *pdev, char *name) return mem; } +//#define ICAM_LCD_QOS static int kmb_load(struct drm_device *drm, unsigned long flags) { struct kmb_drm_private *dev_p = drm->dev_private; @@ -140,6 +141,9 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) int irq_lcd; int ret = 0; unsigned long clk; +#ifdef ICAM_LCD_QOS + int val = 0; +#endif /* Map MIPI MMIO registers */ dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs"); @@ -173,6 +177,13 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) iounmap(dev_p->mipi_mmio); return -ENOMEM; } +#ifdef ICAM_LCD_QOS + dev_p->icamlcd_mmio = ioremap_nocache(ICAM_MMIO, ICAM_MMIO_SIZE); + if (IS_ERR(dev_p->icamlcd_mmio)) { + DRM_ERROR("failed to map ICAM registers\n"); + return -ENOMEM; + } +#endif #define KMB_CLOCKS #ifdef KMB_CLOCKS /* Enable display clocks */ @@ -268,7 +279,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) kmb_set_bitmask_msscam(dev_p, MSS_CAM_CLK_CTRL, 0x1fff); kmb_set_bitmask_msscam(dev_p, MSS_CAM_RSTN_CTRL, 0xffffffff); -#endif //KMB_CLOCKS +#endif //KMB_CLOCKS /* Register irqs here - section 17.3 in databook * lists LCD at 79 and 82 for MIPI under MSS CPU - @@ -331,11 +342,29 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) dev_p->irq_lcd = irq_lcd; + /* icam tests */ +#ifdef ICAM_LCD_QOS + /*generator mode = 0 fixed mode=1 limiter */ + writel(1, (dev_p->icamlcd_mmio + ICAM_LCD_OFFSET + LCD_QOS_MODE)); + /* b/w */ + writel(0x60, (dev_p->icamlcd_mmio + ICAM_LCD_OFFSET + LCD_QOS_BW)); + + /* set priority.p1 */ + val = readl(dev_p->icamlcd_mmio + ICAM_LCD_OFFSET + LCD_QOS_PRORITY); + val &= ~(0x700); + writel(val | 0x100, + (dev_p->icamlcd_mmio + ICAM_LCD_OFFSET + LCD_QOS_PRORITY)); + + DRM_INFO("ICAM mode = 0x%x, priority = 0x%x bandwidth=0x%x", + readl(dev_p->icamlcd_mmio + 0x1080 + LCD_QOS_MODE), + readl(dev_p->icamlcd_mmio + 0x1080 + LCD_QOS_PRORITY), + readl(dev_p->icamlcd_mmio + 0x1080 + LCD_QOS_BW)); +#endif return 0; -irq_fail: + irq_fail: drm_crtc_cleanup(&dev_p->crtc); -setup_fail: + setup_fail: of_reserved_mem_device_release(drm->dev); return ret; @@ -368,13 +397,15 @@ static void kmb_setup_mode_config(struct drm_device *drm) static irqreturn_t handle_lcd_irq(struct drm_device *dev) { - unsigned long status, val; - int plane_id; + volatile unsigned long status, val, val1; + int plane_id, dma0_state, dma1_state; struct kmb_drm_private *dev_p = dev->dev_private; status = kmb_read_lcd(dev->dev_private, LCD_INT_STATUS); + if (status & LCD_INT_EOF) { /* TODO - handle EOF interrupt? */ + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_EOF); /* When disabling/enabling LCD layers, the change takes effect @@ -396,6 +427,30 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) plane_status[plane_id].disable = false; } } + if (under_flow) { + /*DMA Recovery after underflow */ + DRM_INFO("EOF:S"); + dma0_state = (layer_no == 0) ? + LCD_VIDEO0_DMA0_STATE : LCD_VIDEO1_DMA0_STATE; + dma1_state = (layer_no == 0) ? + LCD_VIDEO0_DMA1_STATE : LCD_VIDEO1_DMA1_STATE; + + do { + kmb_write_lcd(dev_p, LCD_FIFO_FLUSH, 1); + val = kmb_read_lcd(dev_p, dma0_state) + & LCD_DMA_STATE_ACTIVE; + val1 = kmb_read_lcd(dev_p, dma1_state) + & LCD_DMA_STATE_ACTIVE; + } while ((val || val1)); + /*disable dma */ + kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(layer_no), + LCD_DMA_LAYER_ENABLE); + kmb_write_lcd(dev_p, LCD_FIFO_FLUSH, 1); + flush_done = 1; + under_flow = 0; + DRM_INFO("EOF:E "); + } + } if (status & LCD_INT_LINE_CMP) { @@ -409,48 +464,86 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) val = (val & LCD_VSTATUS_VERTICAL_STATUS_MASK); switch (val) { case LCD_VSTATUS_COMPARE_VSYNC: + /* Clear vertical compare interrupt */ + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_VERT_COMP); + if (flush_done) { + kmb_set_bitmask_lcd(dev_p, + LCD_LAYERn_DMA_CFG + (layer_no), + LCD_DMA_LAYER_ENABLE); + flush_done = 0; + } + drm_handle_vblank(dev, 0); + break; case LCD_VSTATUS_COMPARE_BACKPORCH: case LCD_VSTATUS_COMPARE_ACTIVE: case LCD_VSTATUS_COMPARE_FRONT_PORCH: - /* clear vertical compare interrupt */ - kmb_write_lcd(dev->dev_private, LCD_INT_CLEAR, - LCD_INT_VERT_COMP); - drm_handle_vblank(dev, 0); + kmb_write_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_VERT_COMP); break; } } - if (status & LCD_INT_DMA_ERR) { - val = (status & LCD_INT_DMA_ERR); + val = + (status & LCD_INT_DMA_ERR & + kmb_read_lcd(dev_p, LCD_INT_ENABLE)); /* LAYER0 - VL0 */ - if (val & LAYER0_DMA_FIFO_UNDEFLOW) - DRM_INFO("LAYER0:VL0 DMA UNDERFLOW val = 0x%lx", val); + if (val & (LAYER0_DMA_FIFO_UNDERFLOW | + LAYER0_DMA_CB_FIFO_UNDERFLOW | + LAYER0_DMA_CR_FIFO_UNDERFLOW)) { + under_flow++; + DRM_INFO + ("!LAYER0:VL0 DMA UNDERFLOW val = 0x%lx,under_flow=%d", + val, under_flow); + /*disable underflow inerrupt */ + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, + LAYER0_DMA_FIFO_UNDERFLOW | + LAYER0_DMA_CB_FIFO_UNDERFLOW | + LAYER0_DMA_CR_FIFO_UNDERFLOW); + kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, + LAYER0_DMA_CB_FIFO_UNDERFLOW | + LAYER0_DMA_FIFO_UNDERFLOW | + LAYER0_DMA_CR_FIFO_UNDERFLOW); + /*disable auto restart mode */ + kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(0), + LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); + layer_no = 0; + } + if (val & LAYER0_DMA_FIFO_OVERFLOW) DRM_INFO("LAYER0:VL0 DMA OVERFLOW val = 0x%lx", val); if (val & LAYER0_DMA_CB_FIFO_OVERFLOW) DRM_INFO("LAYER0:VL0 DMA CB OVERFLOW val = 0x%lx", val); - if (val & LAYER0_DMA_CB_FIFO_UNDERFLOW) - DRM_INFO("LAYER0:VL0 DMA CB UNDERFLOW val = 0x%lx", - val); - if (val & LAYER0_DMA_CR_FIFO_UNDERFLOW) - DRM_INFO("LAYER0:VL0 DMA CR UNDERFLOW val = 0x%lx", - val); if (val & LAYER0_DMA_CR_FIFO_OVERFLOW) DRM_INFO("LAYER0:VL0 DMA CR OVERFLOW val = 0x%lx", val); /* LAYER1 - VL1 */ - if (val & LAYER1_DMA_FIFO_UNDERFLOW) - DRM_INFO("LAYER1:VL1 DMA UNDERFLOW val = 0x%lx", val); + if (val & (LAYER1_DMA_FIFO_UNDERFLOW | + LAYER1_DMA_CB_FIFO_UNDERFLOW | + LAYER1_DMA_CR_FIFO_UNDERFLOW)) { + under_flow++; + DRM_INFO + ("!LAYER1:VL1 DMA UNDERFLOW val = 0x%lx, under_flow=%d", + val, under_flow); + /*disable underflow inerrupt */ + kmb_clr_bitmask_lcd(dev_p, LCD_INT_ENABLE, + LAYER1_DMA_FIFO_UNDERFLOW | + LAYER1_DMA_CB_FIFO_UNDERFLOW | + LAYER1_DMA_CR_FIFO_UNDERFLOW); + kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, + LAYER1_DMA_CB_FIFO_UNDERFLOW | + LAYER1_DMA_FIFO_UNDERFLOW | + LAYER1_DMA_CR_FIFO_UNDERFLOW); + /*disable auto restart mode */ + kmb_clr_bitmask_lcd(dev_p, LCD_LAYERn_DMA_CFG(1), + LCD_DMA_LAYER_CONT_PING_PONG_UPDATE); + layer_no = 1; + } + + /* LAYER1 - VL1 */ if (val & LAYER1_DMA_FIFO_OVERFLOW) DRM_INFO("LAYER1:VL1 DMA OVERFLOW val = 0x%lx", val); if (val & LAYER1_DMA_CB_FIFO_OVERFLOW) DRM_INFO("LAYER1:VL1 DMA CB OVERFLOW val = 0x%lx", val); - if (val & LAYER1_DMA_CB_FIFO_UNDERFLOW) - DRM_INFO("LAYER1:VL1 DMA CB UNDERFLOW val = 0x%lx", - val); - if (val & LAYER1_DMA_CR_FIFO_UNDERFLOW) - DRM_INFO("LAYER1:VL1 DMA CR UNDERFLOW val = 0x%lx", - val); if (val & LAYER1_DMA_CR_FIFO_OVERFLOW) DRM_INFO("LAYER1:VL1 DMA CR OVERFLOW val = 0x%lx", val); @@ -465,7 +558,6 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev) DRM_INFO("LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val); if (val & LAYER3_DMA_FIFO_UNDERFLOW) DRM_INFO("LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val); - } if (status & LCD_INT_LAYER) { @@ -647,11 +739,11 @@ static int kmb_probe(struct platform_device *pdev) #endif return 0; -err_register: + err_register: drm_kms_helper_poll_fini(drm); -err_vblank: + err_vblank: pm_runtime_disable(drm->dev); -err_free: + err_free: drm_mode_config_cleanup(drm); dev_set_drvdata(dev, NULL); drm_dev_put(drm); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index eef2d8b..a066aba 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -34,28 +34,31 @@ #define KMB_MAX_HEIGHT 1080 /*max height in pixels */ #define KMB_MIN_WIDTH 1920 /*max width in pixels */ #define KMB_MIN_HEIGHT 1080 /*max height in pixels */ -#define KMB_LCD_DEFAULT_CLK 250000000 +#define KMB_LCD_DEFAULT_CLK 200000000 #define KMB_MIPI_DEFAULT_CLK 24000000 #define KMB_MIPI_DEFAULT_CFG_CLK 24000000 #define KMB_SYS_CLK_MHZ 500 #define crtc_to_kmb_priv(x) container_of(x, struct kmb_drm_private, crtc) - +#define ICAM_MMIO 0x3b100000 +#define ICAM_LCD_OFFSET 0x1080 +#define ICAM_MMIO_SIZE 0x2000 struct kmb_drm_private { - struct drm_device drm; - void __iomem *lcd_mmio; - void __iomem *mipi_mmio; - void __iomem *msscam_mmio; - unsigned char n_layers; - struct clk *clk; - struct drm_crtc crtc; - struct kmb_plane *plane; - struct drm_atomic_state *state; - spinlock_t irq_lock; - int irq_lcd; - int irq_mipi; - dma_addr_t fb_addr; + struct drm_device drm; + void __iomem *lcd_mmio; + void __iomem *mipi_mmio; + void __iomem *msscam_mmio; + void __iomem *icamlcd_mmio; + unsigned char n_layers; + struct clk *clk; + struct drm_crtc crtc; + struct kmb_plane *plane; + struct drm_atomic_state *state; + spinlock_t irq_lock; + int irq_lcd; + int irq_mipi; + dma_addr_t fb_addr; }; static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 5e040f7..e278347 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -42,7 +42,6 @@ #include "kmb_drv.h" struct layer_status plane_status[KMB_MAX_PLANES]; - const uint32_t layer_irqs[] = { LCD_INT_VL0, LCD_INT_VL1, @@ -267,13 +266,17 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, fb = plane->state->fb; if (!fb) return; - num_planes = fb->format->num_planes; kmb_plane = to_kmb_plane(plane); plane_id = kmb_plane->id; dev_p = plane->dev->dev_private; + if (under_flow || flush_done) { + DRM_DEBUG("plane_update:underflow!!!! returning"); + return; + } + src_w = (plane->state->src_w >> 16); src_h = plane->state->src_h >> 16; crtc_x = plane->state->crtc_x; @@ -393,6 +396,11 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg); DRM_DEBUG("dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg, kmb_read_lcd(dev_p, LCD_LAYERn_DMA_CFG(plane_id))); + + kmb_set_bitmask_lcd(dev_p, LCD_INT_CLEAR, LCD_INT_EOF | + LCD_INT_DMA_ERR); + kmb_set_bitmask_lcd(dev_p, LCD_INT_ENABLE, LCD_INT_EOF | + LCD_INT_DMA_ERR); #endif } diff --git a/drivers/gpu/drm/kmb/kmb_plane.h b/drivers/gpu/drm/kmb/kmb_plane.h index af0d091..d09dfd6 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.h +++ b/drivers/gpu/drm/kmb/kmb_plane.h @@ -28,19 +28,22 @@ #include "kmb_drv.h" -#define LCD_INT_VL0_ERR (LAYER0_DMA_FIFO_UNDEFLOW | \ - LAYER0_DMA_FIFO_OVERFLOW | \ - LAYER0_DMA_CB_FIFO_OVERFLOW | \ - LAYER0_DMA_CB_FIFO_UNDERFLOW | \ - LAYER0_DMA_CR_FIFO_OVERFLOW | \ - LAYER0_DMA_CR_FIFO_UNDERFLOW) - -#define LCD_INT_VL1_ERR (LAYER1_DMA_FIFO_UNDERFLOW | \ - LAYER1_DMA_FIFO_OVERFLOW | \ - LAYER1_DMA_CB_FIFO_OVERFLOW | \ - LAYER1_DMA_CB_FIFO_UNDERFLOW | \ - LAYER1_DMA_CR_FIFO_OVERFLOW | \ - LAYER1_DMA_CR_FIFO_UNDERFLOW) +extern int under_flow; +extern int flush_done; + +#define LCD_INT_VL0_ERR ((LAYER0_DMA_FIFO_UNDERFLOW) | \ + (LAYER0_DMA_FIFO_OVERFLOW) | \ + (LAYER0_DMA_CB_FIFO_OVERFLOW) | \ + (LAYER0_DMA_CB_FIFO_UNDERFLOW) | \ + (LAYER0_DMA_CR_FIFO_OVERFLOW) | \ + (LAYER0_DMA_CR_FIFO_UNDERFLOW)) + +#define LCD_INT_VL1_ERR ((LAYER1_DMA_FIFO_UNDERFLOW) | \ + (LAYER1_DMA_FIFO_OVERFLOW) | \ + (LAYER1_DMA_CB_FIFO_OVERFLOW) | \ + (LAYER1_DMA_CB_FIFO_UNDERFLOW) | \ + (LAYER1_DMA_CR_FIFO_OVERFLOW) | \ + (LAYER1_DMA_CR_FIFO_UNDERFLOW)) #define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW) #define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW) diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index f904a5c..2c86d2a 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -86,7 +86,7 @@ #define LAYER0_DMA_DONE (1<<3) #define LAYER0_DMA_IDLE (1<<4) #define LAYER0_DMA_FIFO_OVERFLOW (1<<5) -#define LAYER0_DMA_FIFO_UNDEFLOW (1<<6) +#define LAYER0_DMA_FIFO_UNDERFLOW (1<<6) #define LAYER0_DMA_CB_FIFO_OVERFLOW (1<<7) #define LAYER0_DMA_CB_FIFO_UNDERFLOW (1<<8) #define LAYER0_DMA_CR_FIFO_OVERFLOW (1<<9) @@ -402,6 +402,7 @@ #define LCD_PWM2_HIGH_LOW (0x4 * 0x81a) #define LCD_VIDEO0_DMA0_BYTES (0x4 * 0xb00) #define LCD_VIDEO0_DMA0_STATE (0x4 * 0xb01) +#define LCD_DMA_STATE_ACTIVE (1 << 3) #define LCD_VIDEO0_DMA1_BYTES (0x4 * 0xb02) #define LCD_VIDEO0_DMA1_STATE (0x4 * 0xb03) #define LCD_VIDEO0_DMA2_BYTES (0x4 * 0xb04) @@ -750,4 +751,8 @@ #define MSSCPU_CPR_CLK_EN (0x0) #define MSSCPU_CPR_RST_EN (0x10) #define BIT_MASK_16 (0xffff) +/*icam lcd qos */ +#define LCD_QOS_PRORITY (0x8) +#define LCD_QOS_MODE (0xC) +#define LCD_QOS_BW (0x10) #endif /* __KMB_REGS_H__ */ -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:11 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:11 -0700 Subject: [Intel-gfx] [PATCH 59/59] drm/kmb: work around for planar formats In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-60-git-send-email-anitha.chrisanthus@intel.com> Set the DMA Vstride and Line width for U and V planes to the same as the Y plane and not the actual pitch. Bit18 of layer config does not have any effect when U and V planes are swapped, so swap it in the driver. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Edmund Dea <edmund.j.dea at intel.com> --- drivers/gpu/drm/kmb/kmb_plane.c | 50 ++++++++++++++++++++++++----------------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index e278347..eb1652d 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -190,6 +190,8 @@ unsigned int set_pixel_format(u32 format) val = LCD_LAYER_FORMAT_RGBA8888; break; } + DRM_INFO_ONCE("%s : %d format=0x%x val=0x%x\n", + __func__, __LINE__, format, val); return val; } @@ -300,38 +302,48 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, dev_p->fb_addr = addr[Y_PLANE]; kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_ADDR(plane_id), addr[Y_PLANE] + fb->offsets[0]); + val = set_pixel_format(fb->format->format); + val |= set_bits_per_pixel(fb->format); /* Program Cb/Cr for planar formats */ if (num_planes > 1) { - if (fb->format->format == DRM_FORMAT_YUV420 || - fb->format->format == DRM_FORMAT_YVU420) - width /= 2; - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id), - fb->pitches[LAYER_1]); - + width*fb->format->cpp[0]); kmb_write_lcd(dev_p, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id), (width * fb->format->cpp[0])); addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, - U_PLANE); - kmb_write_lcd(dev_p, LCD_LAYERn_DMA_START_CB_ADR(plane_id), - addr[U_PLANE]); + U_PLANE); + /* check if Cb/Cr is swapped*/ + if ((num_planes == 3) && (val & LCD_LAYER_CRCB_ORDER)) + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CR_ADR(plane_id), + addr[U_PLANE]); + else + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CB_ADR(plane_id), + addr[U_PLANE]); if (num_planes == 3) { kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), - fb->pitches[LAYER_2]); + LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id), + ((width)*fb->format->cpp[0])); kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), - (width * fb->format->cpp[0])); + LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id), + ((width)*fb->format->cpp[0])); addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb, - plane->state, - V_PLANE); - kmb_write_lcd(dev_p, - LCD_LAYERn_DMA_START_CR_ADR(plane_id), - addr[V_PLANE]); + plane->state, V_PLANE); + + /* check if Cb/Cr is swapped*/ + if (val & LCD_LAYER_CRCB_ORDER) + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CB_ADR(plane_id), + addr[V_PLANE]); + else + kmb_write_lcd(dev_p, + LCD_LAYERn_DMA_START_CR_ADR(plane_id), + addr[V_PLANE]); } } @@ -340,8 +352,6 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, kmb_write_lcd(dev_p, LCD_LAYERn_COL_START(plane_id), crtc_x); kmb_write_lcd(dev_p, LCD_LAYERn_ROW_START(plane_id), crtc_y); - val = set_pixel_format(fb->format->format); - val |= set_bits_per_pixel(fb->format); /*CHECKME Leon drvr sets it to 100 try this for now */ val |= LCD_LAYER_FIFO_100; -- 2.7.4 From anitha.chrisanthus at intel.com Tue Jun 30 21:28:10 2020 From: anitha.chrisanthus at intel.com (Anitha Chrisanthus) Date: Tue, 30 Jun 2020 14:28:10 -0700 Subject: [Intel-gfx] [PATCH 58/59] drm/kmb: Get System Clock from SCMI In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <1593552491-23698-59-git-send-email-anitha.chrisanthus@intel.com> System clock is different for A0 and B0 silicons, so get it directly from clk_PLL0 through SCMI calls. Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus at intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com> --- drivers/gpu/drm/kmb/kmb_drv.c | 11 +++++++++++ drivers/gpu/drm/kmb/kmb_drv.h | 1 + drivers/gpu/drm/kmb/kmb_dsi.c | 12 +----------- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_drv.c b/drivers/gpu/drm/kmb/kmb_drv.c index bafc02a..74f57b3 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.c +++ b/drivers/gpu/drm/kmb/kmb_drv.c @@ -59,6 +59,7 @@ static struct clk *clk_lcd; static struct clk *clk_mipi; static struct clk *clk_mipi_ecfg; static struct clk *clk_mipi_cfg; +static struct clk *clk_pll0; struct drm_bridge *adv_bridge; @@ -144,6 +145,7 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) #ifdef ICAM_LCD_QOS int val = 0; #endif + struct device_node *vpu_dev; /* Map MIPI MMIO registers */ dev_p->mipi_mmio = kmb_map_mmio(pdev, "mipi_regs"); @@ -210,6 +212,15 @@ static int kmb_load(struct drm_device *drm, unsigned long flags) DRM_ERROR("clk_get() failed clk_mipi_cfg\n"); goto setup_fail; } + vpu_dev = of_find_node_by_path("/soc/vpu-ipc"); + DRM_INFO("vpu node = %pOF", vpu_dev); + clk_pll0 = of_clk_get_by_name(vpu_dev, "pll_0_out_0"); + if (IS_ERR(clk_pll0)) { + DRM_ERROR("clk_get() failed clk_pll0 "); + goto setup_fail; + } + dev_p->sys_clk_mhz = clk_get_rate(clk_pll0)/1000000; + DRM_INFO("system clk = %d Mhz", dev_p->sys_clk_mhz); #ifdef LCD_TEST /* Set LCD clock to 200 Mhz */ DRM_DEBUG("Get clk_lcd before set = %ld\n", clk_get_rate(clk_lcd)); diff --git a/drivers/gpu/drm/kmb/kmb_drv.h b/drivers/gpu/drm/kmb/kmb_drv.h index a066aba..35872a5 100644 --- a/drivers/gpu/drm/kmb/kmb_drv.h +++ b/drivers/gpu/drm/kmb/kmb_drv.h @@ -58,6 +58,7 @@ struct kmb_drm_private { spinlock_t irq_lock; int irq_lcd; int irq_mipi; + int sys_clk_mhz; dma_addr_t fb_addr; }; diff --git a/drivers/gpu/drm/kmb/kmb_dsi.c b/drivers/gpu/drm/kmb/kmb_dsi.c index ec974da..81678a3 100644 --- a/drivers/gpu/drm/kmb/kmb_dsi.c +++ b/drivers/gpu/drm/kmb/kmb_dsi.c @@ -611,20 +611,10 @@ static void mipi_tx_fg_cfg_regs(struct kmb_drm_private *dev_p, u8 frame_gen, u32 ppl_llp_ratio; u32 ctrl_no = MIPI_CTRL6, reg_adr, val, offset; -#ifdef GET_SYS_CLK - /* Get system clock for blanking period cnfigurations */ - sc = get_clock_frequency(CPR_CLK_SYSTEM, &sysclk); - if (sc) - return sc; - - /* Convert to MHZ */ - sysclk /= 1000; -#else /* 500 Mhz system clock minus 50 to account for the difference in * MIPI clock speed in RTL tests */ - sysclk = KMB_SYS_CLK_MHZ - 50; -#endif + sysclk = dev_p->sys_clk_mhz - 50; /* PPL-Pixel Packing Layer, LLP-Low Level Protocol * Frame genartor timing parameters are clocked on the system clock, -- 2.7.4 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:49 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:49 +0300 Subject: [Intel-gfx] [PATCH 00/12] drm/i915: Futher hotplug cleanups Message-ID: <20200630215601.28557-1-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> Our hotplug interrupt handling is still a mess. Continue the cleanup. Ville Syrj?l? (12): drm/i915: Add more AUX CHs to the enum drm/i915: Add PORT_{H,I} to intel_port_to_power_domain() drm/i915: Add AUX_CH_{H,I} power domain handling drm/i915: Add VBT DVO ports H and I drm/i915: Add VBT AUX CH H and I drm/i915: Nuke the redundant TC/TBT HPD bit defines drm/i915: Configure GEN11_{TBT,TC}_HOTPLUG_CTL for ports TC5/6 drm/i915: Split icp_hpd_detection_setup() into ddi vs. tc parts drm/i915: Move hpd_pin setup to encoder init drm/i915: Introduce HPD_PORT_TC<n> drm/i915: Introduce intel_hpd_hotplug_irqs() drm/i915: Nuke pointless variable drivers/gpu/drm/i915/display/intel_bios.c | 8 + drivers/gpu/drm/i915/display/intel_ddi.c | 64 +++++ drivers/gpu/drm/i915/display/intel_display.c | 12 + drivers/gpu/drm/i915/display/intel_display.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/display/intel_hotplug.c | 28 +-- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 10 +- drivers/gpu/drm/i915/i915_drv.h | 17 +- drivers/gpu/drm/i915/i915_irq.c | 227 +++++++----------- drivers/gpu/drm/i915/i915_reg.h | 36 +-- 11 files changed, 203 insertions(+), 205 deletions(-) -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:50 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:50 +0300 Subject: [Intel-gfx] [PATCH 01/12] drm/i915: Add more AUX CHs to the enum In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-2-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> We need to go up to AUX_CH_I (aka. AUX CH USBC6) these days. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index f68007ff8a13..5b736883cd11 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -282,6 +282,8 @@ enum aux_ch { AUX_CH_E, /* ICL+ */ AUX_CH_F, AUX_CH_G, + AUX_CH_H, + AUX_CH_I, }; #define aux_ch_name(a) ((a) + 'A') -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:51 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:51 +0300 Subject: [Intel-gfx] [PATCH 02/12] drm/i915: Add PORT_{H, I} to intel_port_to_power_domain() In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-3-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> We need to go up to PORT_I (aka. TC6) these days. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 182cef0dc2fd..665aa4283fb9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7289,6 +7289,10 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port) return POWER_DOMAIN_PORT_DDI_F_LANES; case PORT_G: return POWER_DOMAIN_PORT_DDI_G_LANES; + case PORT_H: + return POWER_DOMAIN_PORT_DDI_H_LANES; + case PORT_I: + return POWER_DOMAIN_PORT_DDI_I_LANES; default: MISSING_CASE(port); return POWER_DOMAIN_PORT_OTHER; -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:52 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:52 +0300 Subject: [Intel-gfx] [PATCH 03/12] drm/i915: Add AUX_CH_{H, I} power domain handling In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-4-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> AUX CH H/I need their power domains too. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 665aa4283fb9..87831fd9e1e1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7318,6 +7318,10 @@ intel_aux_power_domain(struct intel_digital_port *dig_port) return POWER_DOMAIN_AUX_F_TBT; case AUX_CH_G: return POWER_DOMAIN_AUX_G_TBT; + case AUX_CH_H: + return POWER_DOMAIN_AUX_H_TBT; + case AUX_CH_I: + return POWER_DOMAIN_AUX_I_TBT; default: MISSING_CASE(dig_port->aux_ch); return POWER_DOMAIN_AUX_C_TBT; @@ -7349,6 +7353,10 @@ intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) return POWER_DOMAIN_AUX_F; case AUX_CH_G: return POWER_DOMAIN_AUX_G; + case AUX_CH_H: + return POWER_DOMAIN_AUX_H; + case AUX_CH_I: + return POWER_DOMAIN_AUX_I; default: MISSING_CASE(aux_ch); return POWER_DOMAIN_AUX_A; -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:53 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:53 +0300 Subject: [Intel-gfx] [PATCH 04/12] drm/i915: Add VBT DVO ports H and I In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-5-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> VBT has ports H and I since version 217. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 2 ++ drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 6593e2c38043..2bf0bc0deee8 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1653,6 +1653,8 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv, [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, + [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, + [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, }; /* * Bspec lists the ports as A, B, C, D - however internally in our diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index aef7fe932d1a..e502d65300fa 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -293,8 +293,12 @@ struct bdb_general_features { #define DVO_PORT_HDMIE 12 /* 193 */ #define DVO_PORT_DPF 13 /* N/A */ #define DVO_PORT_HDMIF 14 /* N/A */ -#define DVO_PORT_DPG 15 -#define DVO_PORT_HDMIG 16 +#define DVO_PORT_DPG 15 /* 217 */ +#define DVO_PORT_HDMIG 16 /* 217 */ +#define DVO_PORT_DPH 17 /* 217 */ +#define DVO_PORT_HDMIH 18 /* 217 */ +#define DVO_PORT_DPI 19 /* 217 */ +#define DVO_PORT_HDMII 20 /* 217 */ #define DVO_PORT_MIPIA 21 /* 171 */ #define DVO_PORT_MIPIB 22 /* 171 */ #define DVO_PORT_MIPIC 23 /* 171 */ -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:54 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:54 +0300 Subject: [Intel-gfx] [PATCH 05/12] drm/i915: Add VBT AUX CH H and I In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-6-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> As with everything else VBT can now specify AUX CH H or I. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_bios.c | 6 ++++++ drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 2bf0bc0deee8..05eb88ee73f8 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2649,6 +2649,12 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, case DP_AUX_G: aux_ch = AUX_CH_G; break; + case DP_AUX_H: + aux_ch = AUX_CH_H; + break; + case DP_AUX_I: + aux_ch = AUX_CH_I; + break; default: MISSING_CASE(info->alternate_aux_channel); aux_ch = AUX_CH_A; diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index e502d65300fa..b5f7a52f751a 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -334,6 +334,8 @@ enum vbt_gmbus_ddi { #define DP_AUX_E 0x50 #define DP_AUX_F 0x60 #define DP_AUX_G 0x70 +#define DP_AUX_H 0x80 +#define DP_AUX_I 0x90 #define VBT_DP_MAX_LINK_RATE_HBR3 0 #define VBT_DP_MAX_LINK_RATE_HBR2 1 -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:55 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:55 +0300 Subject: [Intel-gfx] [PATCH 06/12] drm/i915: Nuke the redundant TC/TBT HPD bit defines In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-7-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> We have nice parametrized GEN11_{TC,TBT}_HOTPLUG() so nuke the overlapping defines. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 20 +++++++++--------- drivers/gpu/drm/i915/i915_reg.h | 36 +++++++++++---------------------- 2 files changed, 22 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 562b43ed077f..ad52109c747d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -131,19 +131,19 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { }; static const u32 hpd_gen11[HPD_NUM_PINS] = { - [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG, - [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG, - [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG, - [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG, + [HPD_PORT_C] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1), + [HPD_PORT_D] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2), + [HPD_PORT_E] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3), + [HPD_PORT_F] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4), }; static const u32 hpd_gen12[HPD_NUM_PINS] = { - [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG, - [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG, - [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG, - [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG, - [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG, - [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG, + [HPD_PORT_D] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1), + [HPD_PORT_E] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2), + [HPD_PORT_F] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3), + [HPD_PORT_G] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4), + [HPD_PORT_H] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5), + [HPD_PORT_I] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6), }; static const u32 hpd_icp[HPD_NUM_PINS] = { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2ecde5c2e357..d7359f3bbc64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7681,32 +7681,20 @@ enum { #define GEN11_DE_HPD_IMR _MMIO(0x44474) #define GEN11_DE_HPD_IIR _MMIO(0x44478) #define GEN11_DE_HPD_IER _MMIO(0x4447c) -#define GEN12_TC6_HOTPLUG (1 << 21) -#define GEN12_TC5_HOTPLUG (1 << 20) -#define GEN11_TC4_HOTPLUG (1 << 19) -#define GEN11_TC3_HOTPLUG (1 << 18) -#define GEN11_TC2_HOTPLUG (1 << 17) -#define GEN11_TC1_HOTPLUG (1 << 16) #define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) -#define GEN11_DE_TC_HOTPLUG_MASK (GEN12_TC6_HOTPLUG | \ - GEN12_TC5_HOTPLUG | \ - GEN11_TC4_HOTPLUG | \ - GEN11_TC3_HOTPLUG | \ - GEN11_TC2_HOTPLUG | \ - GEN11_TC1_HOTPLUG) -#define GEN12_TBT6_HOTPLUG (1 << 5) -#define GEN12_TBT5_HOTPLUG (1 << 4) -#define GEN11_TBT4_HOTPLUG (1 << 3) -#define GEN11_TBT3_HOTPLUG (1 << 2) -#define GEN11_TBT2_HOTPLUG (1 << 1) -#define GEN11_TBT1_HOTPLUG (1 << 0) +#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \ + GEN11_TC_HOTPLUG(PORT_TC5) | \ + GEN11_TC_HOTPLUG(PORT_TC4) | \ + GEN11_TC_HOTPLUG(PORT_TC3) | \ + GEN11_TC_HOTPLUG(PORT_TC2) | \ + GEN11_TC_HOTPLUG(PORT_TC1)) #define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) -#define GEN11_DE_TBT_HOTPLUG_MASK (GEN12_TBT6_HOTPLUG | \ - GEN12_TBT5_HOTPLUG | \ - GEN11_TBT4_HOTPLUG | \ - GEN11_TBT3_HOTPLUG | \ - GEN11_TBT2_HOTPLUG | \ - GEN11_TBT1_HOTPLUG) +#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \ + GEN11_TBT_HOTPLUG(PORT_TC5) | \ + GEN11_TBT_HOTPLUG(PORT_TC4) | \ + GEN11_TBT_HOTPLUG(PORT_TC3) | \ + GEN11_TBT_HOTPLUG(PORT_TC2) | \ + GEN11_TBT_HOTPLUG(PORT_TC1)) #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:56 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:56 +0300 Subject: [Intel-gfx] [PATCH 07/12] drm/i915: Configure GEN11_{TBT, TC}_HOTPLUG_CTL for ports TC5/6 In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-8-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> gen11_hpd_detection_setup() is missing ports TC5/6. Add them. TODO: Might be nice to only enable the hpd detection logic for ports we actually have. Should be rolled out for all platforms if/when done... Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index ad52109c747d..839ae674bc44 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3109,14 +3109,18 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6); I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug); hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL); hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) | GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) | - GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4); + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) | + GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6); I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug); } -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:57 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:57 +0300 Subject: [Intel-gfx] [PATCH 08/12] drm/i915: Split icp_hpd_detection_setup() into ddi vs. tc parts In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-9-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> No reason to stuff both DDI and TC port handling into the same function. Split it into two. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 48 ++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 839ae674bc44..92d74448ee03 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3045,21 +3045,24 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) ibx_hpd_detection_setup(dev_priv); } -static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv, - u32 ddi_hotplug_enable_mask, - u32 tc_hotplug_enable_mask) +static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv, + u32 enable_mask) { u32 hotplug; hotplug = I915_READ(SHOTPLUG_CTL_DDI); - hotplug |= ddi_hotplug_enable_mask; + hotplug |= enable_mask; I915_WRITE(SHOTPLUG_CTL_DDI, hotplug); +} - if (tc_hotplug_enable_mask) { - hotplug = I915_READ(SHOTPLUG_CTL_TC); - hotplug |= tc_hotplug_enable_mask; - I915_WRITE(SHOTPLUG_CTL_TC, hotplug); - } +static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv, + u32 enable_mask) +{ + u32 hotplug; + + hotplug = I915_READ(SHOTPLUG_CTL_TC); + hotplug |= enable_mask; + I915_WRITE(SHOTPLUG_CTL_TC, hotplug); } static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, @@ -3075,7 +3078,9 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); - icp_hpd_detection_setup(dev_priv, ddi_enable_mask, tc_enable_mask); + icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask); + if (tc_enable_mask) + icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask); } /* @@ -3493,17 +3498,18 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv) gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); I915_WRITE(SDEIMR, ~mask); - if (HAS_PCH_TGP(dev_priv)) - icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, - TGP_TC_HPD_ENABLE_MASK); - else if (HAS_PCH_JSP(dev_priv)) - icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0); - else if (HAS_PCH_MCC(dev_priv)) - icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK, - ICP_TC_HPD_ENABLE(PORT_TC1)); - else - icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK, - ICP_TC_HPD_ENABLE_MASK); + if (HAS_PCH_TGP(dev_priv)) { + icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); + icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK); + } else if (HAS_PCH_JSP(dev_priv)) { + icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); + } else if (HAS_PCH_MCC(dev_priv)) { + icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); + icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1)); + } else { + icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); + icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK); + } } static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:58 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:58 +0300 Subject: [Intel-gfx] [PATCH 09/12] drm/i915: Move hpd_pin setup to encoder init In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-10-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> Currently DP/HDMI/DDI encoders init their hpd_pin from the connector init. Let's move it to the encoder init so that we don't need to add platform specific junk to the connector init (which is shared by all g4x+ platforms). Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 884b507c5f55..d024491738b3 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4907,6 +4907,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->port = port; encoder->cloneable = 0; encoder->pipe_mask = ~0; + encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); if (INTEL_GEN(dev_priv) >= 11) intel_dig_port->saved_port_bits = intel_de_read(dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3df5d901dd9d..cd516cd8acb8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -8211,7 +8211,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, if (INTEL_GEN(dev_priv) >= 11) connector->ycbcr_420_allowed = true; - intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); intel_connector->polled = DRM_CONNECTOR_POLL_HPD; intel_dp_aux_init(intel_dp); @@ -8354,6 +8353,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, } intel_encoder->cloneable = 0; intel_encoder->port = port; + intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 864a1642e81c..f515d0fce968 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3253,7 +3253,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) connector->ycbcr_420_allowed = true; - intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); intel_connector->polled = DRM_CONNECTOR_POLL_HPD; if (HAS_DDI(dev_priv)) @@ -3385,6 +3384,7 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, intel_encoder->pipe_mask = ~0; } intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; + intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); /* * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems * to work on real hardware. And since g4x can send infoframes to -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:55:59 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:55:59 +0300 Subject: [Intel-gfx] [PATCH 10/12] drm/i915: Introduce HPD_PORT_TC<n> In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-11-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> Make a clean split between hpd pins for DDI vs. TC. This matches how the actual hardware is split. And with this we move the DDI/PHY->HPD pin mapping into the encoder init instead of having to remap yet again in the interrupt code. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 65 +++++++++- drivers/gpu/drm/i915/display/intel_hotplug.c | 25 +--- drivers/gpu/drm/i915/i915_drv.h | 17 +-- drivers/gpu/drm/i915/i915_irq.c | 121 +++++-------------- 4 files changed, 102 insertions(+), 126 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d024491738b3..a2c9815c5abc 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4847,6 +4847,57 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) return max_lanes; } +static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + if (port >= PORT_D) + return HPD_PORT_TC1 + port - PORT_D; + else + return HPD_PORT_A + port - PORT_A; +} + +static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + if (HAS_PCH_TGP(dev_priv)) + return tgl_hpd_pin(dev_priv, port); + + if (port >= PORT_D) + return HPD_PORT_C + port - PORT_D; + else + return HPD_PORT_A + port - PORT_A; +} + +static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + if (port >= PORT_C) + return HPD_PORT_TC1 + port - PORT_C; + else + return HPD_PORT_A + port - PORT_A; +} + +static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + if (port == PORT_D) + return HPD_PORT_A; + + if (HAS_PCH_MCC(dev_priv)) + return icl_hpd_pin(dev_priv, port); + + return HPD_PORT_A + port - PORT_A; +} + +static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, + enum port port) +{ + if (port == PORT_F) + return HPD_PORT_E; + + return HPD_PORT_A + port - PORT_A; +} + void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) { struct intel_digital_port *intel_dig_port; @@ -4907,7 +4958,19 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->port = port; encoder->cloneable = 0; encoder->pipe_mask = ~0; - encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + + if (IS_ROCKETLAKE(dev_priv)) + encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); + else if (INTEL_GEN(dev_priv) >= 12) + encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); + else if (IS_ELKHARTLAKE(dev_priv)) + encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); + else if (IS_GEN(dev_priv, 11)) + encoder->hpd_pin = icl_hpd_pin(dev_priv, port); + else if (IS_GEN(dev_priv, 10)) + encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); + else + encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); if (INTEL_GEN(dev_priv) >= 11) intel_dig_port->saved_port_bits = intel_de_read(dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 80bcfff032e9..8a8e77314a4e 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -81,33 +81,12 @@ * * It is only valid and used by digital port encoder. * - * Return pin that is associatade with @port and HDP_NONE if no pin is - * hard associated with that @port. + * Return pin that is associatade with @port. */ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, enum port port) { - enum phy phy = intel_port_to_phy(dev_priv, port); - - /* - * RKL + TGP PCH is a special case; we effectively choose the hpd_pin - * based on the DDI rather than the PHY (i.e., the last two outputs - * shold be HPD_PORT_{D,E} rather than {C,D}. Note that this differs - * from the behavior of both TGL+TGP and RKL+CMP. - */ - if (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)) - return HPD_PORT_A + port - PORT_A; - - switch (phy) { - case PHY_F: - return IS_CNL_WITH_PORT_F(dev_priv) ? HPD_PORT_E : HPD_PORT_F; - case PHY_A ... PHY_E: - case PHY_G ... PHY_I: - return HPD_PORT_A + phy - PHY_A; - default: - MISSING_CASE(phy); - return HPD_NONE; - } + return HPD_PORT_A + port - PORT_A; } #define HPD_STORM_DETECT_PERIOD 1000 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6e9072ab30a1..dcd35cd97f01 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -113,13 +113,6 @@ struct drm_i915_gem_object; -/* - * The code assumes that the hpd_pins below have consecutive values and - * starting with HPD_PORT_A, the HPD pin associated with any port can be - * retrieved by adding the corresponding port (or phy) enum value to - * HPD_PORT_A in most cases. For example: - * HPD_PORT_C = HPD_PORT_A + PHY_C - PHY_A - */ enum hpd_pin { HPD_NONE = 0, HPD_TV = HPD_NONE, /* TV is known to be unreliable */ @@ -131,10 +124,12 @@ enum hpd_pin { HPD_PORT_C, HPD_PORT_D, HPD_PORT_E, - HPD_PORT_F, - HPD_PORT_G, - HPD_PORT_H, - HPD_PORT_I, + HPD_PORT_TC1, + HPD_PORT_TC2, + HPD_PORT_TC3, + HPD_PORT_TC4, + HPD_PORT_TC5, + HPD_PORT_TC6, HPD_NUM_PINS }; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 92d74448ee03..95ab4432a87d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -131,40 +131,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { }; static const u32 hpd_gen11[HPD_NUM_PINS] = { - [HPD_PORT_C] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1), - [HPD_PORT_D] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2), - [HPD_PORT_E] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3), - [HPD_PORT_F] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4), -}; - -static const u32 hpd_gen12[HPD_NUM_PINS] = { - [HPD_PORT_D] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1), - [HPD_PORT_E] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2), - [HPD_PORT_F] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3), - [HPD_PORT_G] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4), - [HPD_PORT_H] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5), - [HPD_PORT_I] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6), + [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1), + [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2), + [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3), + [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4), + [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5), + [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6), }; static const u32 hpd_icp[HPD_NUM_PINS] = { - [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), - [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), - [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1), - [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2), - [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC3), - [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC4), -}; - -static const u32 hpd_tgp[HPD_NUM_PINS] = { [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A), [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B), [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C), - [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC1), - [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC2), - [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC3), - [HPD_PORT_G] = SDE_TC_HOTPLUG_ICP(PORT_TC4), - [HPD_PORT_H] = SDE_TC_HOTPLUG_ICP(PORT_TC5), - [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6), + [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1), + [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2), + [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3), + [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4), + [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5), + [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6), }; static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) @@ -180,9 +164,7 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) return; } - if (INTEL_GEN(dev_priv) >= 12) - hpd->hpd = hpd_gen12; - else if (INTEL_GEN(dev_priv) >= 11) + if (INTEL_GEN(dev_priv) >= 11) hpd->hpd = hpd_gen11; else if (IS_GEN9_LP(dev_priv)) hpd->hpd = hpd_bxt; @@ -196,9 +178,8 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) return; - if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv)) - hpd->pch_hpd = hpd_tgp; - else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) + if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) || + HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) hpd->pch_hpd = hpd_icp; else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) hpd->pch_hpd = hpd_spt; @@ -1048,33 +1029,17 @@ static void ivb_parity_work(struct work_struct *work) static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { - case HPD_PORT_C: + case HPD_PORT_TC1: return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1); - case HPD_PORT_D: + case HPD_PORT_TC2: return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2); - case HPD_PORT_E: + case HPD_PORT_TC3: return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3); - case HPD_PORT_F: + case HPD_PORT_TC4: return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4); - default: - return false; - } -} - -static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val) -{ - switch (pin) { - case HPD_PORT_D: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1); - case HPD_PORT_E: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2); - case HPD_PORT_F: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3); - case HPD_PORT_G: - return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4); - case HPD_PORT_H: + case HPD_PORT_TC5: return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5); - case HPD_PORT_I: + case HPD_PORT_TC6: return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6); default: return false; @@ -1112,33 +1077,17 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) { switch (pin) { - case HPD_PORT_C: + case HPD_PORT_TC1: return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); - case HPD_PORT_D: + case HPD_PORT_TC2: return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); - case HPD_PORT_E: + case HPD_PORT_TC3: return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); - case HPD_PORT_F: + case HPD_PORT_TC4: return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); - default: - return false; - } -} - -static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) -{ - switch (pin) { - case HPD_PORT_D: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1); - case HPD_PORT_E: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2); - case HPD_PORT_F: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3); - case HPD_PORT_G: - return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4); - case HPD_PORT_H: + case HPD_PORT_TC5: return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5); - case HPD_PORT_I: + case HPD_PORT_TC6: return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6); default: return false; @@ -1892,19 +1841,16 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) { u32 ddi_hotplug_trigger, tc_hotplug_trigger; u32 pin_mask = 0, long_mask = 0; - bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val); if (HAS_PCH_TGP(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP; - tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect; } else if (HAS_PCH_JSP(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP; tc_hotplug_trigger = 0; } else if (HAS_PCH_MCC(dev_priv)) { ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1); - tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; } else { drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv), "Unrecognized PCH type 0x%x\n", @@ -1912,7 +1858,6 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP; tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP; - tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect; } if (ddi_hotplug_trigger) { @@ -1936,7 +1881,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, tc_hotplug_trigger, dig_hotplug_reg, dev_priv->hotplug.pch_hpd, - tc_port_hotplug_long_detect); + icp_tc_port_hotplug_long_detect); } if (pin_mask) @@ -2184,12 +2129,6 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) u32 pin_mask = 0, long_mask = 0; u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; - long_pulse_detect_func long_pulse_detect; - - if (INTEL_GEN(dev_priv) >= 12) - long_pulse_detect = gen12_port_hotplug_long_detect; - else - long_pulse_detect = gen11_port_hotplug_long_detect; if (trigger_tc) { u32 dig_hotplug_reg; @@ -2200,7 +2139,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc, dig_hotplug_reg, dev_priv->hotplug.hpd, - long_pulse_detect); + gen11_port_hotplug_long_detect); } if (trigger_tbt) { @@ -2212,7 +2151,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt, dig_hotplug_reg, dev_priv->hotplug.hpd, - long_pulse_detect); + gen11_port_hotplug_long_detect); } if (pin_mask) -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:56:00 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:56:00 +0300 Subject: [Intel-gfx] [PATCH 11/12] drm/i915: Introduce intel_hpd_hotplug_irqs() In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-12-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> Introduce intel_hpd_hotplug_irqs() as a partner to intel_hpd_enabled_irqs(). There's no need to care about the encoders which we're not exposing, so we can avoid hardocoding the masks in various places. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 50 +++++++++++++++------------------ 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 95ab4432a87d..b8a6a21f4c54 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2943,6 +2943,18 @@ static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, return enabled_irqs; } +static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, + const u32 hpd[HPD_NUM_PINS]) +{ + struct intel_encoder *encoder; + u32 hotplug_irqs = 0; + + for_each_intel_encoder(&dev_priv->drm, encoder) + hotplug_irqs |= hpd[encoder->hpd_pin]; + + return hotplug_irqs; +} + static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) { u32 hotplug; @@ -2972,12 +2984,8 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; - if (HAS_PCH_IBX(dev_priv)) - hotplug_irqs = SDE_HOTPLUG_MASK; - else - hotplug_irqs = SDE_HOTPLUG_MASK_CPT; - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); + hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); @@ -3005,13 +3013,12 @@ static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv, } static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, - u32 sde_ddi_mask, u32 sde_tc_mask, u32 ddi_enable_mask, u32 tc_enable_mask) { u32 hotplug_irqs, enabled_irqs; - hotplug_irqs = sde_ddi_mask | sde_tc_mask; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); + hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); @@ -3029,7 +3036,6 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) { icp_hpd_irq_setup(dev_priv, - SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1), ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1)); } @@ -3041,7 +3047,6 @@ static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) { icp_hpd_irq_setup(dev_priv, - SDE_DDI_MASK_TGP, 0, TGP_DDI_HPD_ENABLE_MASK, 0); } @@ -3074,7 +3079,7 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) u32 val; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); - hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; + hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); val = I915_READ(GEN11_DE_HPD_IMR); val &= ~hotplug_irqs; @@ -3085,10 +3090,10 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) gen11_hpd_detection_setup(dev_priv); if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) - icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_TGP, SDE_TC_MASK_TGP, + icp_hpd_irq_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK); else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) - icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_ICP, SDE_TC_MASK_ICP, + icp_hpd_irq_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK); } @@ -3124,8 +3129,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); - hotplug_irqs = SDE_HOTPLUG_MASK_SPT; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); + hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); @@ -3152,22 +3157,13 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; - if (INTEL_GEN(dev_priv) >= 8) { - hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); + hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); + if (INTEL_GEN(dev_priv) >= 8) bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); - } else if (INTEL_GEN(dev_priv) >= 7) { - hotplug_irqs = DE_DP_A_HOTPLUG_IVB; - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); - + else ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); - } else { - hotplug_irqs = DE_DP_A_HOTPLUG; - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); - - ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); - } ilk_hpd_detection_setup(dev_priv); @@ -3216,7 +3212,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) u32 hotplug_irqs, enabled_irqs; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); - hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; + hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); -- 2.26.2 From ville.syrjala at linux.intel.com Tue Jun 30 21:56:01 2020 From: ville.syrjala at linux.intel.com (Ville Syrjala) Date: Wed, 1 Jul 2020 00:56:01 +0300 Subject: [Intel-gfx] [PATCH 12/12] drm/i915: Nuke pointless variable In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <20200630215601.28557-13-ville.syrjala@linux.intel.com> From: Ville Syrj?l? <ville.syrjala at linux.intel.com> No point in assigning the function return value to a local variable if we're just going to use it the one time. Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> --- drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 8a8e77314a4e..938466b2c9d1 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -480,7 +480,6 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, * only the one of them (DP) will have ->hpd_pulse(). */ for_each_intel_encoder(&dev_priv->drm, encoder) { - bool has_hpd_pulse = intel_encoder_has_hpd_pulse(encoder); enum port port = encoder->port; bool long_hpd; @@ -488,7 +487,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, if (!(BIT(pin) & pin_mask)) continue; - if (!has_hpd_pulse) + if (!intel_encoder_has_hpd_pulse(encoder)) continue; long_hpd = long_mask & BIT(pin); -- 2.26.2 From patchwork at emeril.freedesktop.org Tue Jun 30 22:11:05 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 22:11:05 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLkNIRUNLUEFUQ0g6IHdhcm5pbmcg?= =?utf-8?q?for_Add_support_for_Keem_Bay_DRM_driver?= In-Reply-To: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> References: <1593552491-23698-1-git-send-email-anitha.chrisanthus@intel.com> Message-ID: <159355506570.22701.16003768513373898481@emeril.freedesktop.org> == Series Details == Series: Add support for Keem Bay DRM driver URL : https://patchwork.freedesktop.org/series/78961/ State : warning == Summary == $ dim checkpatch origin/drm-tip c489c4330583 drm/kmb: Add support for KeemBay Display -:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #39: new file mode 100644 -:256: CHECK:BRACES: Blank lines aren't necessary before a close brace '}' #256: FILE: drivers/gpu/drm/kmb/kmb_crtc.c:187: + +} -:345: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #345: FILE: drivers/gpu/drm/kmb/kmb_crtc.h:55: +}; +#define to_kmb_crtc_state(x) container_of(x, struct kmb_crtc_state, crtc_base) -:347: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #347: FILE: drivers/gpu/drm/kmb/kmb_crtc.h:57: +extern void kmb_plane_destroy(struct drm_plane *plane); -:348: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files #348: FILE: drivers/gpu/drm/kmb/kmb_crtc.h:58: +extern struct drm_plane *kmb_plane_init(struct drm_device *drm); -:892: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_CFG> #892: FILE: drivers/gpu/drm/kmb/kmb_plane.c:86: + kmb_write(lcd, LCD_LAYERn_DMA_CFG(i), ~LCD_DMA_LAYER_ENABLE); -:895: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_START_ADDR> #895: FILE: drivers/gpu/drm/kmb/kmb_plane.c:89: + kmb_write(lcd, LCD_LAYERn_DMA_START_ADDR(i), addr); -:896: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_START_SHADOW> #896: FILE: drivers/gpu/drm/kmb/kmb_plane.c:90: + kmb_write(lcd, LCD_LAYERn_DMA_START_SHADOW(i), addr); -:901: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_LEN> #901: FILE: drivers/gpu/drm/kmb/kmb_plane.c:95: + kmb_write(lcd, LCD_LAYERn_DMA_LEN(i), dma_len); -:903: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_LINE_VSTRIDE> #903: FILE: drivers/gpu/drm/kmb/kmb_plane.c:97: + kmb_write(lcd, LCD_LAYERn_DMA_LINE_VSTRIDE(i), fb->pitches[0]); -:904: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_LINE_WIDTH> #904: FILE: drivers/gpu/drm/kmb/kmb_plane.c:98: + kmb_write(lcd, LCD_LAYERn_DMA_LINE_WIDTH(i), -:1022: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t' #1022: FILE: drivers/gpu/drm/kmb/kmb_plane.c:216: + const uint32_t *plane_formats; -:1026: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #1026: FILE: drivers/gpu/drm/kmb/kmb_plane.c:220: + for (i = 0; i < lcd->n_layers; i++) { + -:1043: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #1043: FILE: drivers/gpu/drm/kmb/kmb_plane.c:237: + ret = drm_universal_plane_init(drm, plane, 0xFF, + &kmb_plane_funcs, plane_formats, -:1168: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1168: FILE: drivers/gpu/drm/kmb/kmb_regs.h:46: +#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) ^ -:1168: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CFG> #1168: FILE: drivers/gpu/drm/kmb/kmb_regs.h:46: +#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) -:1168: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1168: FILE: drivers/gpu/drm/kmb/kmb_regs.h:46: +#define LCD_LAYERn_CFG(N) (LCD_LAYER0_CFG + (0x400*N)) -:1170: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1170: FILE: drivers/gpu/drm/kmb/kmb_regs.h:48: +#define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400*N)) ^ -:1170: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_COL_START> #1170: FILE: drivers/gpu/drm/kmb/kmb_regs.h:48: +#define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400*N)) -:1170: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1170: FILE: drivers/gpu/drm/kmb/kmb_regs.h:48: +#define LCD_LAYERn_COL_START(N) (LCD_LAYER0_COL_START + (0x400*N)) -:1172: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1172: FILE: drivers/gpu/drm/kmb/kmb_regs.h:50: +#define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400*N)) ^ -:1172: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_ROW_START> #1172: FILE: drivers/gpu/drm/kmb/kmb_regs.h:50: +#define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400*N)) -:1172: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1172: FILE: drivers/gpu/drm/kmb/kmb_regs.h:50: +#define LCD_LAYERn_ROW_START(N) (LCD_LAYER0_ROW_START + (0x400*N)) -:1174: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1174: FILE: drivers/gpu/drm/kmb/kmb_regs.h:52: +#define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400*N)) ^ -:1174: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_WIDTH> #1174: FILE: drivers/gpu/drm/kmb/kmb_regs.h:52: +#define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400*N)) -:1174: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1174: FILE: drivers/gpu/drm/kmb/kmb_regs.h:52: +#define LCD_LAYERn_WIDTH(N) (LCD_LAYER0_WIDTH + (0x400*N)) -:1176: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1176: FILE: drivers/gpu/drm/kmb/kmb_regs.h:54: +#define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400*N)) ^ -:1176: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_HEIGHT> #1176: FILE: drivers/gpu/drm/kmb/kmb_regs.h:54: +#define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400*N)) -:1176: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1176: FILE: drivers/gpu/drm/kmb/kmb_regs.h:54: +#define LCD_LAYERn_HEIGHT(N) (LCD_LAYER0_HEIGHT + (0x400*N)) -:1178: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1178: FILE: drivers/gpu/drm/kmb/kmb_regs.h:56: +#define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400*N)) ^ -:1178: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_SCALE_CFG> #1178: FILE: drivers/gpu/drm/kmb/kmb_regs.h:56: +#define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400*N)) -:1178: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1178: FILE: drivers/gpu/drm/kmb/kmb_regs.h:56: +#define LCD_LAYERn_SCALE_CFG(N) (LCD_LAYER0_SCALE_CFG + (0x400*N)) -:1180: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1180: FILE: drivers/gpu/drm/kmb/kmb_regs.h:58: +#define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400*N)) ^ -:1180: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_ALPHA> #1180: FILE: drivers/gpu/drm/kmb/kmb_regs.h:58: +#define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400*N)) -:1180: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1180: FILE: drivers/gpu/drm/kmb/kmb_regs.h:58: +#define LCD_LAYERn_ALPHA(N) (LCD_LAYER0_ALPHA + (0x400*N)) -:1182: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1182: FILE: drivers/gpu/drm/kmb/kmb_regs.h:60: +#define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + (0x400*N)) ^ -:1182: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_INV_COLOUR_LS> #1182: FILE: drivers/gpu/drm/kmb/kmb_regs.h:60: +#define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + (0x400*N)) -:1182: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1182: FILE: drivers/gpu/drm/kmb/kmb_regs.h:60: +#define LCD_LAYERn_INV_COLOUR_LS(N) (LCD_LAYER0_INV_COLOUR_LS + (0x400*N)) -:1184: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1184: FILE: drivers/gpu/drm/kmb/kmb_regs.h:62: +#define LCD_LAYERn_INV_COLOUR_MS(N) (LCD_LAYER0_INV_COLOUR_MS + (0x400*N)) ^ -:1184: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_INV_COLOUR_MS> #1184: FILE: drivers/gpu/drm/kmb/kmb_regs.h:62: +#define LCD_LAYERn_INV_COLOUR_MS(N) (LCD_LAYER0_INV_COLOUR_MS + (0x400*N)) -:1184: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1184: FILE: drivers/gpu/drm/kmb/kmb_regs.h:62: +#define LCD_LAYERn_INV_COLOUR_MS(N) (LCD_LAYER0_INV_COLOUR_MS + (0x400*N)) -:1186: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1186: FILE: drivers/gpu/drm/kmb/kmb_regs.h:64: +#define LCD_LAYERn_TRANS_COLOUR_LS(N) (LCD_LAYER0_TRANS_COLOUR_LS + (0x400*N)) ^ -:1186: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_TRANS_COLOUR_LS> #1186: FILE: drivers/gpu/drm/kmb/kmb_regs.h:64: +#define LCD_LAYERn_TRANS_COLOUR_LS(N) (LCD_LAYER0_TRANS_COLOUR_LS + (0x400*N)) -:1186: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1186: FILE: drivers/gpu/drm/kmb/kmb_regs.h:64: +#define LCD_LAYERn_TRANS_COLOUR_LS(N) (LCD_LAYER0_TRANS_COLOUR_LS + (0x400*N)) -:1188: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1188: FILE: drivers/gpu/drm/kmb/kmb_regs.h:66: +#define LCD_LAYERn_TRANS_COLOUR_MS(N) (LCD_LAYER0_TRANS_COLOUR_MS + (0x400*N)) ^ -:1188: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_TRANS_COLOUR_MS> #1188: FILE: drivers/gpu/drm/kmb/kmb_regs.h:66: +#define LCD_LAYERn_TRANS_COLOUR_MS(N) (LCD_LAYER0_TRANS_COLOUR_MS + (0x400*N)) -:1188: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1188: FILE: drivers/gpu/drm/kmb/kmb_regs.h:66: +#define LCD_LAYERn_TRANS_COLOUR_MS(N) (LCD_LAYER0_TRANS_COLOUR_MS + (0x400*N)) -:1190: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1190: FILE: drivers/gpu/drm/kmb/kmb_regs.h:68: +#define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400*N)) ^ -:1190: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF11> #1190: FILE: drivers/gpu/drm/kmb/kmb_regs.h:68: +#define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400*N)) -:1190: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1190: FILE: drivers/gpu/drm/kmb/kmb_regs.h:68: +#define LCD_LAYERn_CSC_COEFF11(N) (LCD_LAYER0_CSC_COEFF11 + (0x400*N)) -:1192: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1192: FILE: drivers/gpu/drm/kmb/kmb_regs.h:70: +#define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400*N)) ^ -:1192: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF12> #1192: FILE: drivers/gpu/drm/kmb/kmb_regs.h:70: +#define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400*N)) -:1192: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1192: FILE: drivers/gpu/drm/kmb/kmb_regs.h:70: +#define LCD_LAYERn_CSC_COEFF12(N) (LCD_LAYER0_CSC_COEFF12 + (0x400*N)) -:1194: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1194: FILE: drivers/gpu/drm/kmb/kmb_regs.h:72: +#define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400*N)) ^ -:1194: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF13> #1194: FILE: drivers/gpu/drm/kmb/kmb_regs.h:72: +#define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400*N)) -:1194: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1194: FILE: drivers/gpu/drm/kmb/kmb_regs.h:72: +#define LCD_LAYERn_CSC_COEFF13(N) (LCD_LAYER0_CSC_COEFF13 + (0x400*N)) -:1196: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1196: FILE: drivers/gpu/drm/kmb/kmb_regs.h:74: +#define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400*N)) ^ -:1196: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF21> #1196: FILE: drivers/gpu/drm/kmb/kmb_regs.h:74: +#define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400*N)) -:1196: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1196: FILE: drivers/gpu/drm/kmb/kmb_regs.h:74: +#define LCD_LAYERn_CSC_COEFF21(N) (LCD_LAYER0_CSC_COEFF21 + (0x400*N)) -:1198: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1198: FILE: drivers/gpu/drm/kmb/kmb_regs.h:76: +#define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400*N)) ^ -:1198: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF22> #1198: FILE: drivers/gpu/drm/kmb/kmb_regs.h:76: +#define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400*N)) -:1198: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1198: FILE: drivers/gpu/drm/kmb/kmb_regs.h:76: +#define LCD_LAYERn_CSC_COEFF22(N) (LCD_LAYER0_CSC_COEFF22 + (0x400*N)) -:1200: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1200: FILE: drivers/gpu/drm/kmb/kmb_regs.h:78: +#define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400*N)) ^ -:1200: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF23> #1200: FILE: drivers/gpu/drm/kmb/kmb_regs.h:78: +#define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400*N)) -:1200: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1200: FILE: drivers/gpu/drm/kmb/kmb_regs.h:78: +#define LCD_LAYERn_CSC_COEFF23(N) (LCD_LAYER0_CSC_COEFF23 + (0x400*N)) -:1202: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1202: FILE: drivers/gpu/drm/kmb/kmb_regs.h:80: +#define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400*N)) ^ -:1202: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF31> #1202: FILE: drivers/gpu/drm/kmb/kmb_regs.h:80: +#define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400*N)) -:1202: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1202: FILE: drivers/gpu/drm/kmb/kmb_regs.h:80: +#define LCD_LAYERn_CSC_COEFF31(N) (LCD_LAYER0_CSC_COEFF31 + (0x400*N)) -:1204: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1204: FILE: drivers/gpu/drm/kmb/kmb_regs.h:82: +#define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400*N)) ^ -:1204: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF32> #1204: FILE: drivers/gpu/drm/kmb/kmb_regs.h:82: +#define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400*N)) -:1204: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1204: FILE: drivers/gpu/drm/kmb/kmb_regs.h:82: +#define LCD_LAYERn_CSC_COEFF32(N) (LCD_LAYER0_CSC_COEFF32 + (0x400*N)) -:1206: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1206: FILE: drivers/gpu/drm/kmb/kmb_regs.h:84: +#define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400*N)) ^ -:1206: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_COEFF33> #1206: FILE: drivers/gpu/drm/kmb/kmb_regs.h:84: +#define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400*N)) -:1206: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1206: FILE: drivers/gpu/drm/kmb/kmb_regs.h:84: +#define LCD_LAYERn_CSC_COEFF33(N) (LCD_LAYER0_CSC_COEFF33 + (0x400*N)) -:1208: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1208: FILE: drivers/gpu/drm/kmb/kmb_regs.h:86: +#define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400*N)) ^ -:1208: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_OFF1> #1208: FILE: drivers/gpu/drm/kmb/kmb_regs.h:86: +#define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400*N)) -:1208: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1208: FILE: drivers/gpu/drm/kmb/kmb_regs.h:86: +#define LCD_LAYERn_CSC_OFF1(N) (LCD_LAYER0_CSC_OFF1 + (0x400*N)) -:1210: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1210: FILE: drivers/gpu/drm/kmb/kmb_regs.h:88: +#define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400*N)) ^ -:1210: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_OFF2> #1210: FILE: drivers/gpu/drm/kmb/kmb_regs.h:88: +#define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400*N)) -:1210: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1210: FILE: drivers/gpu/drm/kmb/kmb_regs.h:88: +#define LCD_LAYERn_CSC_OFF2(N) (LCD_LAYER0_CSC_OFF2 + (0x400*N)) -:1212: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1212: FILE: drivers/gpu/drm/kmb/kmb_regs.h:90: +#define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400*N)) ^ -:1212: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CSC_OFF3> #1212: FILE: drivers/gpu/drm/kmb/kmb_regs.h:90: +#define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400*N)) -:1212: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1212: FILE: drivers/gpu/drm/kmb/kmb_regs.h:90: +#define LCD_LAYERn_CSC_OFF3(N) (LCD_LAYER0_CSC_OFF3 + (0x400*N)) -:1214: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1214: FILE: drivers/gpu/drm/kmb/kmb_regs.h:92: +#define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + (0x400*N)) ^ -:1214: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1214: FILE: drivers/gpu/drm/kmb/kmb_regs.h:92: +#define LCD_LAYERn_DMA_CFG(N) (LCD_LAYER0_DMA_CFG + (0x400*N)) -:1216: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1216: FILE: drivers/gpu/drm/kmb/kmb_regs.h:94: +#define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR + (0x400*N)) ^ -:1216: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1216: FILE: drivers/gpu/drm/kmb/kmb_regs.h:94: +#define LCD_LAYERn_DMA_START_ADDR(N) (LCD_LAYER0_DMA_START_ADR + (0x400*N)) -:1218: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1218: FILE: drivers/gpu/drm/kmb/kmb_regs.h:96: +#define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW + (0x400*N)) ^ -:1218: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1218: FILE: drivers/gpu/drm/kmb/kmb_regs.h:96: +#define LCD_LAYERn_DMA_START_SHADOW(N) (LCD_LAYER0_DMA_START_SHADOW + (0x400*N)) -:1220: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1220: FILE: drivers/gpu/drm/kmb/kmb_regs.h:98: +#define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + (0x400*N)) ^ -:1220: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1220: FILE: drivers/gpu/drm/kmb/kmb_regs.h:98: +#define LCD_LAYERn_DMA_LEN(N) (LCD_LAYER0_DMA_LEN + (0x400*N)) -:1222: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1222: FILE: drivers/gpu/drm/kmb/kmb_regs.h:100: +#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + (0x400*N)) ^ -:1222: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_LEN_SHADOW> #1222: FILE: drivers/gpu/drm/kmb/kmb_regs.h:100: +#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + (0x400*N)) -:1222: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1222: FILE: drivers/gpu/drm/kmb/kmb_regs.h:100: +#define LCD_LAYERn_DMA_LEN_SHADOW(N) (LCD_LAYER0_DMA_LEN_SHADOW + (0x400*N)) -:1224: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1224: FILE: drivers/gpu/drm/kmb/kmb_regs.h:102: +#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + (0x400*N)) ^ -:1224: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_STATUS> #1224: FILE: drivers/gpu/drm/kmb/kmb_regs.h:102: +#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + (0x400*N)) -:1224: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1224: FILE: drivers/gpu/drm/kmb/kmb_regs.h:102: +#define LCD_LAYERn_DMA_STATUS(N) (LCD_LAYER0_DMA_STATUS + (0x400*N)) -:1226: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1226: FILE: drivers/gpu/drm/kmb/kmb_regs.h:104: +#define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + (0x400*N)) ^ -:1226: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1226: FILE: drivers/gpu/drm/kmb/kmb_regs.h:104: +#define LCD_LAYERn_DMA_LINE_WIDTH(N) (LCD_LAYER0_DMA_LINE_WIDTH + (0x400*N)) -:1228: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1228: FILE: drivers/gpu/drm/kmb/kmb_regs.h:106: +#define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE + (0x400*N)) ^ -:1228: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1228: FILE: drivers/gpu/drm/kmb/kmb_regs.h:106: +#define LCD_LAYERn_DMA_LINE_VSTRIDE(N) (LCD_LAYER0_DMA_LINE_VSTRIDE + (0x400*N)) -:1230: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1230: FILE: drivers/gpu/drm/kmb/kmb_regs.h:108: +#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + (0x400*N)) ^ -:1230: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_DMA_FIFO_STATUS> #1230: FILE: drivers/gpu/drm/kmb/kmb_regs.h:108: +#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + (0x400*N)) -:1230: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1230: FILE: drivers/gpu/drm/kmb/kmb_regs.h:108: +#define LCD_LAYERn_DMA_FIFO_STATUS(N) (LCD_LAYER0_DMA_FIFO_STATUS + (0x400*N)) -:1232: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1232: FILE: drivers/gpu/drm/kmb/kmb_regs.h:110: +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) ^ -:1232: CHECK:CAMELCASE: Avoid CamelCase: <LCD_LAYERn_CFG2> #1232: FILE: drivers/gpu/drm/kmb/kmb_regs.h:110: +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) -:1232: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1232: FILE: drivers/gpu/drm/kmb/kmb_regs.h:110: +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) -:1235: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1235: FILE: drivers/gpu/drm/kmb/kmb_regs.h:113: +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) ^ -:1235: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1235: FILE: drivers/gpu/drm/kmb/kmb_regs.h:113: +#define LCD_LAYERn_CFG2(N) (LCD_LAYER0_CFG2 + (0x400*N)) -:1426: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1426: FILE: drivers/gpu/drm/kmb/kmb_regs.h:304: +#define LAYER3_DMA_FIFO_UNDERFLOW_BIT (1<<26) ^ -:1427: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1427: FILE: drivers/gpu/drm/kmb/kmb_regs.h:305: +#define LAYER3_DMA_OVERFLOW_BIT (1<<25) ^ -:1428: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1428: FILE: drivers/gpu/drm/kmb/kmb_regs.h:306: +#define LAYER3_DMA_IDLE_BIT (1<<24) ^ -:1429: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1429: FILE: drivers/gpu/drm/kmb/kmb_regs.h:307: +#define LAYER3_DMA_DONE_BIT (1<<23) ^ -:1431: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1431: FILE: drivers/gpu/drm/kmb/kmb_regs.h:309: +#define LAYER2_DMA_FIFO_UNDERFLOW_BIT (1<<22) ^ -:1432: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1432: FILE: drivers/gpu/drm/kmb/kmb_regs.h:310: +#define LAYER2_DMA_OVERFLOW_BIT (1<<21) ^ -:1433: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1433: FILE: drivers/gpu/drm/kmb/kmb_regs.h:311: +#define LAYER2_DMA_IDLE_BIT (1<<20) ^ -:1434: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1434: FILE: drivers/gpu/drm/kmb/kmb_regs.h:312: +#define LAYER2_DMA_DONE_BIT (1<<19) ^ -:1436: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1436: FILE: drivers/gpu/drm/kmb/kmb_regs.h:314: +#define LAYER1_DMA_CR_FIFO_UNDERFLOW_BIT (1<<18) ^ -:1437: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1437: FILE: drivers/gpu/drm/kmb/kmb_regs.h:315: +#define LAYER1_DMA_CR_FIFO_OVERFLOW_BIT (1<<17) ^ -:1438: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1438: FILE: drivers/gpu/drm/kmb/kmb_regs.h:316: +#define LAYER1_DMA_CB_FIFO_UNDERFLOW_BIT (1<<16) ^ -:1439: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1439: FILE: drivers/gpu/drm/kmb/kmb_regs.h:317: +#define LAYER1_DMA_CB_FIFO_OVERFLOW_BIT (1<<15) ^ -:1441: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1441: FILE: drivers/gpu/drm/kmb/kmb_regs.h:319: +#define LAYER1_DMA_FIFO_UNDERFLOW_BIT (1<<14) ^ -:1442: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1442: FILE: drivers/gpu/drm/kmb/kmb_regs.h:320: +#define LAYER1_DMA_OVERFLOW_BIT (1<<13) ^ -:1443: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1443: FILE: drivers/gpu/drm/kmb/kmb_regs.h:321: +#define LAYER1_DMA_IDLE_BIT (1<<12) ^ -:1444: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1444: FILE: drivers/gpu/drm/kmb/kmb_regs.h:322: +#define LAYER1_DMA_DONE_BIT (1<<11) ^ -:1446: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1446: FILE: drivers/gpu/drm/kmb/kmb_regs.h:324: +#define LAYER0_DMA_CR_FIFO_UNDERFLOW_BIT (1<<10) ^ -:1447: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1447: FILE: drivers/gpu/drm/kmb/kmb_regs.h:325: +#define LAYER0_DMA_CR_FIFO_OVERFLOW_BIT (1<<9) ^ -:1448: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1448: FILE: drivers/gpu/drm/kmb/kmb_regs.h:326: +#define LAYER0_DMA_CB_FIFO_UNDERFLOW_BIT (1<<8) ^ -:1449: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1449: FILE: drivers/gpu/drm/kmb/kmb_regs.h:327: +#define LAYER0_DMA_CB_FIFO_OVERFLOW_BIT (1<<7) ^ -:1451: WARNING:TYPO_SPELLING: 'UNDEFLOW' may be misspelled - perhaps 'UNDERFLOW'? #1451: FILE: drivers/gpu/drm/kmb/kmb_regs.h:329: +#define LAYER0_DMA_FIFO_UNDEFLOW_BIT (1<<6) -:1451: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1451: FILE: drivers/gpu/drm/kmb/kmb_regs.h:329: +#define LAYER0_DMA_FIFO_UNDEFLOW_BIT (1<<6) ^ -:1452: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1452: FILE: drivers/gpu/drm/kmb/kmb_regs.h:330: +#define LAYER0_DMA_OVERFLOW_BIT (1<<5) ^ -:1453: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1453: FILE: drivers/gpu/drm/kmb/kmb_regs.h:331: +#define LAYER0_DMA_IDLE_BIT (1<<4) ^ -:1454: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #1454: FILE: drivers/gpu/drm/kmb/kmb_regs.h:332: +#define LAYER0_DMA_DONE_BIT (1<<3) ^ -:1456: CHECK:CAMELCASE: Avoid CamelCase: <BLT_VIDEOn_DMAm_STATE> #1456: FILE: drivers/gpu/drm/kmb/kmb_regs.h:334: +#define BLT_VIDEOn_DMAm_STATE 0x00 -:1457: CHECK:CAMELCASE: Avoid CamelCase: <BLT_VIDEOn_DMAm_BYTES> #1457: FILE: drivers/gpu/drm/kmb/kmb_regs.h:335: +#define BLT_VIDEOn_DMAm_BYTES 0x00 -:1460: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1460: FILE: drivers/gpu/drm/kmb/kmb_regs.h:338: +#define BLT_LAYERn_WIDTH(N) (0x40C + (0x400*N)) ^ -:1460: CHECK:CAMELCASE: Avoid CamelCase: <BLT_LAYERn_WIDTH> #1460: FILE: drivers/gpu/drm/kmb/kmb_regs.h:338: +#define BLT_LAYERn_WIDTH(N) (0x40C + (0x400*N)) -:1460: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'N' may be better as '(N)' to avoid precedence issues #1460: FILE: drivers/gpu/drm/kmb/kmb_regs.h:338: +#define BLT_LAYERn_WIDTH(N) (0x40C + (0x400*N)) -:1461: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV) #1461: FILE: drivers/gpu/drm/kmb/kmb_regs.h:339: +#define BLT_LAYERn_HEIGHT_OFFSET(N) (0x410 + (0x400*N)) ^ -:1461: CHECK:CAME From patchwork at emeril.freedesktop.org Tue Jun 30 22:36:58 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 22:36:58 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyXIEZpLkNJLlNQQVJTRTogd2FybmluZyBmb3Ig?= =?utf-8?q?drm/i915=3A_Futher_hotplug_cleanups?= In-Reply-To: <20200630215601.28557-1-ville.syrjala@linux.intel.com> References: <20200630215601.28557-1-ville.syrjala@linux.intel.com> Message-ID: <159355661890.22703.3356970657552382484@emeril.freedesktop.org> == Series Details == Series: drm/i915: Futher hotplug cleanups URL : https://patchwork.freedesktop.org/series/78962/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.0 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/display/intel_display.c:1222:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1225:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1228:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/display/intel_display.c:1231:22: error: Expected constant expression in case statement +drivers/gpu/drm/i915/gem/i915_gem_context.c:2269:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2270:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2271:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2272:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2273:17: error: bad integer constant expression +drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_lrc.c:2785:17: error: too long token expansion +drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression +drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression +drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040 +drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block +./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block From patchwork at emeril.freedesktop.org Tue Jun 30 22:44:40 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 22:44:40 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915/gem=3A_Always_do_pin=5Fuser=5Fpages_under_the_mmu-notifie?= =?utf-8?q?r_=28rev2=29?= In-Reply-To: <20200630112854.30361-1-chris@chris-wilson.co.uk> References: <20200630112854.30361-1-chris@chris-wilson.co.uk> Message-ID: <159355708084.22701.7780826696643814345@emeril.freedesktop.org> == Series Details == Series: drm/i915/gem: Always do pin_user_pages under the mmu-notifier (rev2) URL : https://patchwork.freedesktop.org/series/78941/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18045_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_18045_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at kms_addfb_basic@addfb25-modifier-no-flag: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#1635] / [i915#95]) +13 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_addfb_basic@addfb25-modifier-no-flag.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-apl4/igt at kms_addfb_basic@addfb25-modifier-no-flag.html * igt at kms_big_fb@x-tiled-64bpp-rotate-180: - shard-glk: [PASS][3] -> [DMESG-FAIL][4] ([i915#118] / [i915#95]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk2/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-glk8/igt at kms_big_fb@x-tiled-64bpp-rotate-180.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#93] / [i915#95]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +9 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl7/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl7/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1: - shard-skl: [PASS][9] -> [FAIL][10] ([i915#79]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl10/igt at kms_flip@flip-vs-expired-vblank-interruptible at b-edp1.html * igt at kms_frontbuffer_tracking@fbcpsr-modesetfrombusy: - shard-tglb: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb1/igt at kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl3/igt at kms_hdr@bpc-switch.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl6/igt at kms_hdr@bpc-switch.html * igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl9/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl1/igt at kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][17] -> [DMESG-FAIL][18] ([i915#95]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_prime@basic-crc at second-to-first.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl1/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb7/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +4 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt at kms_vblank@pipe-a-ts-continuation-suspend.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl4/igt at kms_vblank@pipe-a-ts-continuation-suspend.html * igt at kms_vblank@pipe-c-wait-idle: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_vblank@pipe-c-wait-idle.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl1/igt at kms_vblank@pipe-c-wait-idle.html - shard-apl: [PASS][25] -> [DMESG-WARN][26] ([i915#1982]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt at kms_vblank@pipe-c-wait-idle.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-apl7/igt at kms_vblank@pipe-c-wait-idle.html * igt at perf@blocking: - shard-glk: [PASS][27] -> [DMESG-WARN][28] ([i915#118] / [i915#95]) +1 similar issue [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk3/igt at perf@blocking.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-glk5/igt at perf@blocking.html * igt at perf@blocking-parameterized: - shard-iclb: [PASS][29] -> [FAIL][30] ([i915#1542]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb4/igt at perf@blocking-parameterized.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb7/igt at perf@blocking-parameterized.html * igt at prime_mmap_kms@buffer-sharing: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#402]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb6/igt at prime_mmap_kms@buffer-sharing.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-tglb7/igt at prime_mmap_kms@buffer-sharing.html #### Possible fixes #### * igt at gem_exec_balancer@bonded-slice: - shard-iclb: [INCOMPLETE][33] -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at gem_exec_balancer@bonded-slice.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb4/igt at gem_exec_balancer@bonded-slice.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [DMESG-WARN][35] ([i915#118] / [i915#95]) -> [PASS][36] +1 similar issue [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk2/igt at gem_exec_whisper@basic-contexts-forked.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-glk7/igt at gem_exec_whisper@basic-contexts-forked.html * igt at gem_mmap_gtt@ptrace: - shard-apl: [DMESG-WARN][37] ([i915#1635] / [i915#95]) -> [PASS][38] +11 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at gem_mmap_gtt@ptrace.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-apl1/igt at gem_mmap_gtt@ptrace.html * igt at i915_selftest@mock at requests: - shard-skl: [INCOMPLETE][39] ([i915#198] / [i915#2110]) -> [PASS][40] [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl10/igt at i915_selftest@mock at requests.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl5/igt at i915_selftest@mock at requests.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][41] ([i915#118] / [i915#95]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-green-to-red: - shard-skl: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +10 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_color@pipe-c-ctm-green-to-red.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl9/igt at kms_color@pipe-c-ctm-green-to-red.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][45] ([i915#300]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl9/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1: - shard-glk: [FAIL][47] ([i915#79]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-glk8/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl10/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [FAIL][51] ([i915#46]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl9/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +8 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl2/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][55] ([i915#1188]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl2/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][57] ([CI#80] / [i915#69]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl6/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-glk: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-glk1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][61] ([i915#69]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb8/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb7/igt at kms_psr2_su@frontbuffer.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][67] ([i915#173]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at kms_psr@no_drrs.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb4/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_blt: - shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb8/igt at kms_psr@psr2_primary_blt.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb2/igt at kms_psr@psr2_primary_blt.html * igt at perf@polling-parameterized: - shard-iclb: [FAIL][71] ([i915#1542]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb6/igt at perf@polling-parameterized.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-iclb3/igt at perf@polling-parameterized.html #### Warnings #### * igt at gem_exec_reloc@basic-spin-others at vcs0: - shard-snb: [WARN][73] ([i915#2021]) -> [WARN][74] ([i915#2036]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt at gem_exec_reloc@basic-spin-others at vcs0.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-snb1/igt at gem_exec_reloc@basic-spin-others at vcs0.html * igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs: - shard-apl: [SKIP][75] ([fdo#109271]) -> [SKIP][76] ([fdo#109271] / [i915#1635]) +1 similar issue [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl2/igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-apl7/igt at gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html * igt at kms_color_chamelium@pipe-b-ctm-0-75: - shard-apl: [SKIP][77] ([fdo#109271] / [fdo#111827]) -> [SKIP][78] ([fdo#109271] / [fdo#111827] / [i915#1635]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_color_chamelium@pipe-b-ctm-0-75.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-apl1/igt at kms_color_chamelium@pipe-b-ctm-0-75.html * igt at kms_content_protection@srm: - shard-kbl: [TIMEOUT][79] ([i915#1319]) -> [TIMEOUT][80] ([i915#1319] / [i915#1958]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_content_protection@srm.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl1/igt at kms_content_protection@srm.html * igt at kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [DMESG-WARN][81] ([i915#93] / [i915#95]) -> [DMESG-WARN][82] ([i915#180] / [i915#93] / [i915#95]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_cursor_crc@pipe-a-cursor-suspend.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl3/igt at kms_cursor_crc@pipe-a-cursor-suspend.html * igt at kms_cursor_crc@pipe-d-cursor-512x512-random: - shard-apl: [SKIP][83] ([fdo#109271] / [i915#1635]) -> [SKIP][84] ([fdo#109271]) +4 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl6/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-apl3/igt at kms_cursor_crc@pipe-d-cursor-512x512-random.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][85] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][86] ([i915#93] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-kbl4/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant: - shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#1635] / [i915#95]) -> [DMESG-FAIL][88] ([fdo#108145] / [i915#1635] / [i915#1982] / [i915#95]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/shard-apl4/igt at kms_plane_alpha_blend@pipe-a-coverage-vs-premult-vs-constant.html [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18045 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18045: 01fe075c6b02c195bc1d13679d69c4c17738c554 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18045/index.html From manasi.d.navare at intel.com Tue Jun 30 23:14:06 2020 From: manasi.d.navare at intel.com (Manasi Navare) Date: Tue, 30 Jun 2020 16:14:06 -0700 Subject: [Intel-gfx] [PATCH v4 2/2] drm/i915/dp: Helper to check for DDI BUF status to get active In-Reply-To: <20200630212026.GV6112@intel.com> References: <20200626232641.4557-1-manasi.d.navare@intel.com> <20200626232641.4557-2-manasi.d.navare@intel.com> <20200630212026.GV6112@intel.com> Message-ID: <20200630231405.GA21950@intel.com> On Wed, Jul 01, 2020 at 12:20:26AM +0300, Ville Syrj?l? wrote: > On Fri, Jun 26, 2020 at 04:26:41PM -0700, Manasi Navare wrote: > > Based on the platform, Bspec expects us to wait or poll with > > timeout for DDI BUF IDLE bit to be set to 0 (non idle) or get active > > after enabling DDI_BUF_CTL. > > > > v4: > > * Use the timeout for GLK (Ville) > > v3: > > * Add a new function _active for DDI BUF CTL to be non idle (Ville) > > v2: > > * Based on platform, fixed delay or poll (Ville) > > * Use a helper to do this (Imre, Ville) > > > > Cc: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Cc: Imre Deak <imre.deak at intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare at intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 16 +++++++++++++++- > > 1 file changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 052a74625a61..94d57b57139b 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -1195,6 +1195,20 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, > > port_name(port)); > > } > > > > +static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, > > + enum port port) > > +{ > > + if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv) ) { > > + usleep_range(600, 1000); > > I would probably put a spec quote here to make it clear what this is: > "Wait >518 us for buffers to enable..." > > Or we could s/600/518/ to make it easier to figure out. But that could > be a followup. Yes I can change this to 518,1000 and add a comment in the next rev > > > + return; > > + } > > + > > + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & > > + DDI_BUF_IS_IDLE), 600)) > > Spec says 500 usec for this. Is there a reason to not go with the spec > value? I guess one argument is that we didn't do it before. But I'd > probably change it, if not in this patch then as a followup. Hmm yes probably the HSDs said 600 but since spec says 500usecs, I will change the timeout to 500 Manasi > > > + drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", > > + port_name(port)); > > +} > > + > > static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) > > { > > switch (pll->info->id) { > > @@ -4020,7 +4034,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) > > intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); > > > > - udelay(600); > > + intel_wait_ddi_buf_active(dev_priv, port); > > Still can't see fdi anywhere. > > Whatever > Reviewed-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > } > > > > static void intel_ddi_set_link_train(struct intel_dp *intel_dp, > > -- > > 2.19.1 > > -- > Ville Syrj?l? > Intel From patchwork at emeril.freedesktop.org Tue Jun 30 23:18:37 2020 From: patchwork at emeril.freedesktop.org (Patchwork) Date: Tue, 30 Jun 2020 23:18:37 -0000 Subject: [Intel-gfx] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgZHJt?= =?utf-8?q?/i915=3A_Skip_stale_object_handle_for_debugfs_per-file-stats?= In-Reply-To: <20200630152724.3734-1-chris@chris-wilson.co.uk> References: <20200630152724.3734-1-chris@chris-wilson.co.uk> Message-ID: <159355911734.22701.12648334530668299443@emeril.freedesktop.org> == Series Details == Series: drm/i915: Skip stale object handle for debugfs per-file-stats URL : https://patchwork.freedesktop.org/series/78948/ State : success == Summary == CI Bug Log - changes from CI_DRM_8678_full -> Patchwork_18046_full ==================================================== Summary ------- **SUCCESS** No regressions found. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_18046_full: ### Piglit changes ### #### Possible regressions #### * spec at glsl-4.00@execution at built-in-functions@gs-fract-dvec3 (NEW): - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][1] +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/pig-icl-1065g7/spec at glsl-4.00@execution at built-in-functions@gs-fract-dvec3.html * spec at glsl-4.00@execution at built-in-functions@vs-op-mult-dmat4-dmat2x4 (NEW): - {pig-icl-1065g7}: NOTRUN -> [CRASH][2] +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/pig-icl-1065g7/spec at glsl-4.00@execution at built-in-functions@vs-op-mult-dmat4-dmat2x4.html New tests --------- New tests have been introduced between CI_DRM_8678_full and Patchwork_18046_full: ### New Piglit tests (5) ### * spec at glsl-4.00@execution at built-in-functions@fs-mod-dvec3-double: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at glsl-4.00@execution at built-in-functions@gs-fract-dvec3: - Statuses : 1 incomplete(s) - Exec time: [0.0] s * spec at glsl-4.00@execution at built-in-functions@gs-op-mult-dmat3x4-dmat4x3: - Statuses : 1 crash(s) - Exec time: [63.21] s * spec at glsl-4.00@execution at built-in-functions@vs-op-div-double-dmat2x4: - Statuses : 1 crash(s) - Exec time: [8.08] s * spec at glsl-4.00@execution at built-in-functions@vs-op-mult-dmat4-dmat2x4: - Statuses : 1 crash(s) - Exec time: [24.79] s Known issues ------------ Here are the changes found in Patchwork_18046_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt at gem_exec_nop@basic-parallel: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#95]) +20 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt at gem_exec_nop@basic-parallel.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-apl2/igt at gem_exec_nop@basic-parallel.html * igt at i915_module_load@reload-with-fault-injection: - shard-tglb: [PASS][5] -> [DMESG-WARN][6] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb1/igt at i915_module_load@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-tglb5/igt at i915_module_load@reload-with-fault-injection.html * igt at kms_big_fb@y-tiled-64bpp-rotate-180: - shard-glk: [PASS][7] -> [DMESG-FAIL][8] ([i915#118] / [i915#95]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk4/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-glk8/igt at kms_big_fb@y-tiled-64bpp-rotate-180.html * igt at kms_color@pipe-c-ctm-negative: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#78]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt at kms_color@pipe-c-ctm-negative.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl2/igt at kms_color@pipe-c-ctm-negative.html * igt at kms_cursor_crc@pipe-b-cursor-64x64-random: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#93] / [i915#95]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl1/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl3/igt at kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt at kms_cursor_crc@pipe-b-cursor-suspend: - shard-tglb: [PASS][13] -> [TIMEOUT][14] ([i915#1958]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt at kms_cursor_crc@pipe-b-cursor-suspend.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-tglb5/igt at kms_cursor_crc@pipe-b-cursor-suspend.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +4 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl7/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +13 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl7/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl6/igt at kms_cursor_edge_walk@pipe-a-256x256-right-edge.html * igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#1982]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-apl1/igt at kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html * igt at kms_hdr@bpc-switch: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#1188]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl3/igt at kms_hdr@bpc-switch.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl2/igt at kms_hdr@bpc-switch.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([i915#648] / [i915#69]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl3/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_prime@basic-crc at second-to-first: - shard-kbl: [PASS][25] -> [DMESG-FAIL][26] ([i915#95]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl2/igt at kms_prime@basic-crc at second-to-first.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl2/igt at kms_prime@basic-crc at second-to-first.html * igt at kms_psr@psr2_sprite_plane_move: - shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb2/igt at kms_psr@psr2_sprite_plane_move.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-iclb1/igt at kms_psr@psr2_sprite_plane_move.html * igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-tglb: [PASS][29] -> [INCOMPLETE][30] ([i915#456]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-tglb5/igt at kms_vblank@pipe-a-ts-continuation-dpms-suspend.html * igt at kms_vblank@pipe-c-wait-idle: - shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb3/igt at kms_vblank@pipe-c-wait-idle.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-tglb1/igt at kms_vblank@pipe-c-wait-idle.html * igt at perf@blocking: - shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#118] / [i915#95]) +2 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk3/igt at perf@blocking.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-glk7/igt at perf@blocking.html #### Possible fixes #### * igt at gem_exec_balancer@bonded-slice: - shard-iclb: [INCOMPLETE][35] -> [PASS][36] [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at gem_exec_balancer@bonded-slice.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-iclb7/igt at gem_exec_balancer@bonded-slice.html * igt at gem_exec_whisper@basic-contexts-forked: - shard-glk: [DMESG-WARN][37] ([i915#118] / [i915#95]) -> [PASS][38] +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk2/igt at gem_exec_whisper@basic-contexts-forked.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-glk4/igt at gem_exec_whisper@basic-contexts-forked.html * igt at i915_pm_rpm@modeset-non-lpsp: - shard-apl: [DMESG-WARN][39] ([i915#1635] / [i915#95]) -> [PASS][40] +16 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl1/igt at i915_pm_rpm@modeset-non-lpsp.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-apl2/igt at i915_pm_rpm@modeset-non-lpsp.html * igt at i915_selftest@mock at requests: - shard-skl: [INCOMPLETE][41] ([i915#198] / [i915#2110]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl10/igt at i915_selftest@mock at requests.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl1/igt at i915_selftest@mock at requests.html * igt at kms_big_fb@linear-64bpp-rotate-0: - shard-glk: [DMESG-FAIL][43] ([i915#118] / [i915#95]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_big_fb@linear-64bpp-rotate-0.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-glk1/igt at kms_big_fb@linear-64bpp-rotate-0.html * igt at kms_color@pipe-c-ctm-green-to-red: - shard-skl: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46] +10 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_color@pipe-c-ctm-green-to-red.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl4/igt at kms_color@pipe-c-ctm-green-to-red.html * igt at kms_cursor_crc@pipe-c-cursor-suspend: - shard-skl: [INCOMPLETE][47] ([i915#300]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl2/igt at kms_cursor_crc@pipe-c-cursor-suspend.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl5/igt at kms_cursor_crc@pipe-c-cursor-suspend.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1: - shard-glk: [FAIL][49] ([i915#79]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk5/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-glk6/igt at kms_flip@flip-vs-expired-vblank-interruptible at a-hdmi-a1.html * igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1: - shard-skl: [FAIL][51] ([i915#79]) -> [PASS][52] [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl4/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl5/igt at kms_flip@flip-vs-expired-vblank-interruptible at c-edp1.html * igt at kms_flip@flip-vs-expired-vblank at b-edp1: - shard-skl: [FAIL][53] ([i915#46]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl4/igt at kms_flip@flip-vs-expired-vblank at b-edp1.html * igt at kms_flip@flip-vs-suspend-interruptible at a-dp1: - shard-kbl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56] +9 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl3/igt at kms_flip@flip-vs-suspend-interruptible at a-dp1.html * igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack: - shard-tglb: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +1 similar issue [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb7/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-tglb8/igt at kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack.html * igt at kms_hdr@bpc-switch-dpms: - shard-skl: [FAIL][59] ([i915#1188]) -> [PASS][60] +1 similar issue [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl5/igt at kms_hdr@bpc-switch-dpms.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl7/igt at kms_hdr@bpc-switch-dpms.html * igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][61] ([CI#80] / [i915#69]) -> [PASS][62] +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl8/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl7/igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-glk: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-glk8/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-glk1/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: [INCOMPLETE][65] ([i915#69]) -> [PASS][66] +1 similar issue [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-skl6/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-skl9/igt at kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping: - shard-iclb: [DMESG-WARN][67] ([i915#1982]) -> [PASS][68] +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb3/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-iclb6/igt at kms_plane_scaling@pipe-a-scaler-with-clipping-clamping.html * igt at kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][69] ([fdo#109642] / [fdo#111068]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb7/igt at kms_psr2_su@frontbuffer.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-iclb2/igt at kms_psr2_su@frontbuffer.html * igt at kms_psr@no_drrs: - shard-iclb: [FAIL][71] ([i915#173]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb1/igt at kms_psr@no_drrs.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-iclb7/igt at kms_psr@no_drrs.html * igt at kms_psr@psr2_primary_blt: - shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb8/igt at kms_psr@psr2_primary_blt.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-iclb2/igt at kms_psr@psr2_primary_blt.html * igt at kms_psr@psr2_sprite_plane_onoff: - shard-tglb: [DMESG-WARN][75] ([i915#402]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-tglb2/igt at kms_psr@psr2_sprite_plane_onoff.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-tglb1/igt at kms_psr@psr2_sprite_plane_onoff.html * igt at perf@polling-parameterized: - shard-iclb: [FAIL][77] ([i915#1542]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-iclb6/igt at perf@polling-parameterized.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-iclb5/igt at perf@polling-parameterized.html * igt at perf_pmu@semaphore-busy at rcs0: - shard-kbl: [FAIL][79] ([i915#1820]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt at perf_pmu@semaphore-busy at rcs0.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl2/igt at perf_pmu@semaphore-busy at rcs0.html * igt at syncobj_wait@invalid-wait-bad-flags: - shard-kbl: [DMESG-WARN][81] ([i915#93] / [i915#95]) -> [PASS][82] +3 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl7/igt at syncobj_wait@invalid-wait-bad-flags.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl2/igt at syncobj_wait@invalid-wait-bad-flags.html #### Warnings #### * igt at gem_exec_reloc@basic-spin-others at vcs0: - shard-snb: [WARN][83] ([i915#2021]) -> [WARN][84] ([i915#2036]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-snb6/igt at gem_exec_reloc@basic-spin-others at vcs0.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-snb4/igt at gem_exec_reloc@basic-spin-others at vcs0.html * igt at kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [DMESG-WARN][85] ([i915#180] / [i915#93] / [i915#95]) -> [DMESG-WARN][86] ([i915#93] / [i915#95]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl6/igt at kms_frontbuffer_tracking@fbc-suspend.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl7/igt at kms_frontbuffer_tracking@fbc-suspend.html * igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc: - shard-apl: [SKIP][87] ([fdo#109271]) -> [SKIP][88] ([fdo#109271] / [i915#1635]) +9 similar issues [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl3/igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-apl6/igt at kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc.html * igt at kms_frontbuffer_tracking@psr-rgb565-draw-render: - shard-apl: [SKIP][89] ([fdo#109271] / [i915#1635]) -> [SKIP][90] ([fdo#109271]) +7 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-apl8/igt at kms_frontbuffer_tracking@psr-rgb565-draw-render.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-apl7/igt at kms_frontbuffer_tracking@psr-rgb565-draw-render.html * igt at kms_hdr@bpc-switch-suspend: - shard-kbl: [DMESG-WARN][91] ([i915#93] / [i915#95]) -> [DMESG-WARN][92] ([i915#180] / [i915#93] / [i915#95]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8678/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/shard-kbl4/igt at kms_hdr@bpc-switch-suspend.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2021]: https://gitlab.freedesktop.org/drm/intel/issues/2021 [i915#2036]: https://gitlab.freedesktop.org/drm/intel/issues/2036 [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * Linux: CI_DRM_8678 -> Patchwork_18046 CI-20190529: 20190529 CI_DRM_8678: 7cafa8aeca728d8abd1bc9d31d2fca60757a00c4 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5718: af1ef32bfae90bcdbaf1b5d84c61ff4e04368505 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_18046: 285874eca3c1ebdce8e44eb5badf0f7bcd6a52e3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18046/index.html From airlied at gmail.com Tue Jun 30 23:27:51 2020 From: airlied at gmail.com (Dave Airlie) Date: Wed, 1 Jul 2020 09:27:51 +1000 Subject: [Intel-gfx] DG1 VRAM question In-Reply-To: <5d75a3d4-4bb2-3307-8d85-2addc64633f4@intel.com> References: <CAPM=9tyx209haPSokJhA_qOi1PRhoVNPX3MTyNHsq68b=Y5W2A@mail.gmail.com> <CAKi4VA+3oEPXnH-EKgKkxohf=7+jrDPy-fNfX6QvGBj7QsNYLw@mail.gmail.com> <5d75a3d4-4bb2-3307-8d85-2addc64633f4@intel.com> Message-ID: <CAPM=9tzBrvMPtwaEkAyMYaOv1W71De3-ZM82GpFfeHV_+XKq8g@mail.gmail.com> On Sat, 27 Jun 2020 at 03:17, Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> wrote: > > > > On 6/26/20 12:14 AM, Lucas De Marchi wrote: > > Cc Matt and Daniele > > > > On Thu, Jun 25, 2020 at 9:38 PM Dave Airlie <airlied at gmail.com> wrote: > >> > >> I can't figure this out easily so I'd thought I'd just ask, but does > >> DG1 have VRAM > PCIE aperture, I'm not sure I've see any mention of > > > > We'd need to go via lmem since there's no mappable aperture. There are > > a few patches in tree for that > > (see e.g. 54b512cd7a6d ("drm/i915: do not map aperture if it is not > > available.")) but more missing. > > > > To clarify, although the legacy aperture mapping that allowed the CPU to > access memory via the GGTT for swizzling is gone, VRAM/LMEM is still > cpu-mappable via pci bar. > Will leave the questions about possible trashing to Matt as he's more > familiar than me with how this works. Matt? Is DG1 assuming we can get 64-bit BARs always and the CPU will have access to the complete VRAM? or is there any ideas about what happens in those situations where 64-bit BARs aren't available and there is memory pressure on the PCI BAR space. With other discrete GPUs we've got lots of things like visible VRAM limitations, writing page tables with GPU hw instead of from the CPU, having mapping bring things into the visible area, so you can stream something into VRAM, but then it'll migrated to non-visible area if it's unmapped and there is memory pressure. Dave. From matthew.s.atwood at intel.com Tue Jun 30 23:33:10 2020 From: matthew.s.atwood at intel.com (Matt Atwood) Date: Tue, 30 Jun 2020 16:33:10 -0700 Subject: [Intel-gfx] [PATCH v2] drm/i915/dp: Correctly advertise HBR3 for GEN11+ Message-ID: <20200630233310.10191-1-matthew.s.atwood@intel.com> intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to use before encoder_type is set. This caused GEN11+ to incorrectly strip HBR3 from source rates for edp. Move intel_dp_set_source_rates() to after encoder_type is set. Add comment to intel_dp_is_edp() describing unsafe usages. v2: Alter intel_dp_set_source_rates final position (Ville/Manasi). Remove outdated comment (Ville). Slight optimization of control flow in intel_dp_init_connector. Slight rewording in commit message. Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 28 ++++++++++--------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3df5d901dd9d..c9b93c5706af 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -137,6 +137,8 @@ static const u8 valid_dsc_slicecount[] = {1, 2, 4}; * * If a CPU or PCH DP output is attached to an eDP panel, this function * will return true, and false otherwise. + * + * This function is not safe to use prior to encoder type being set. */ bool intel_dp_is_edp(struct intel_dp *intel_dp) { @@ -8157,8 +8159,6 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_encoder->base.name)) return false; - intel_dp_set_source_rates(intel_dp); - intel_dp->reset_link_params = true; intel_dp->pps_pipe = INVALID_PIPE; intel_dp->active_pipe = INVALID_PIPE; @@ -8174,28 +8174,22 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, */ drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); type = DRM_MODE_CONNECTOR_eDP; + intel_encoder->type = INTEL_OUTPUT_EDP; + + /* eDP only on port B and/or C on vlv/chv */ + if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || + IS_CHERRYVIEW(dev_priv)) && + port != PORT_B && port != PORT_C)) + return false; } else { type = DRM_MODE_CONNECTOR_DisplayPort; } + intel_dp_set_source_rates(intel_dp); + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) intel_dp->active_pipe = vlv_active_pipe(intel_dp); - /* - * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but - * for DP the encoder type can be set by the caller to - * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. - */ - if (type == DRM_MODE_CONNECTOR_eDP) - intel_encoder->type = INTEL_OUTPUT_EDP; - - /* eDP only on port B and/or C on vlv/chv */ - if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || - IS_CHERRYVIEW(dev_priv)) && - intel_dp_is_edp(intel_dp) && - port != PORT_B && port != PORT_C)) - return false; - drm_dbg_kms(&dev_priv->drm, "Adding %s connector on [ENCODER:%d:%s]\n", type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", -- 2.21.3 From jose.souza at intel.com Tue Jun 30 23:42:36 2020 From: jose.souza at intel.com (Souza, Jose) Date: Tue, 30 Jun 2020 23:42:36 +0000 Subject: [Intel-gfx] [PATCH 1/3] drm/edid: Allow looking for ext blocks starting from a specified index In-Reply-To: <20200527130310.27099-1-ville.syrjala@linux.intel.com> References: <20200527130310.27099-1-ville.syrjala@linux.intel.com> Message-ID: <8f1e0c7ad218ddf20167ae90d623fb7eec9422c9.camel@intel.com> On Wed, 2020-05-27 at 16:03 +0300, Ville Syrjala wrote: > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Apparently EDIDs with multiple DispID ext blocks is a thing, so prepare > for iterating through multiple ext blocks of the same type by > passing the starting ext block index to drm_find_edid_extension(). Well > also have drm_find_edid_extension() update the index to point to the > next ext block on success. Thus we should be able to call > drm_find_edid_extension() in loop. > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > --- > drivers/gpu/drm/drm_edid.c | 30 +++++++++++++++++++++--------- > 1 file changed, 21 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index d8372d63851b..f2531d51dfa2 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -3188,7 +3188,8 @@ add_detailed_modes(struct drm_connector *connector, struct edid *edid, > /* > * Search EDID for CEA extension block. > */ > -static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) > +static u8 *drm_find_edid_extension(const struct edid *edid, > + int ext_id, int *ext_index) > { > u8 *edid_ext = NULL; > int i; > @@ -3198,23 +3199,26 @@ static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) > return NULL; > > /* Find CEA extension */ > - for (i = 0; i < edid->extensions; i++) { > + for (i = *ext_index; i < edid->extensions; i++) { > edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); > if (edid_ext[0] == ext_id) > break; > } > > - if (i == edid->extensions) > + if (i >= edid->extensions) > return NULL; > > + *ext_index = i + 1; > + > return edid_ext; > } > I would add something like drm_find_edid_n_extension() with the implementation above and then implement drm_find_edid_extension() calling drm_find_edid_n_extension() but it is just one caller that is not using ext_index so LGTM. > > static u8 *drm_find_displayid_extension(const struct edid *edid, > - int *length, int *idx) > + int *length, int *idx, > + int *ext_index) > { > - u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT); > + u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index); > struct displayid_hdr *base; > int ret; > > @@ -3241,14 +3245,18 @@ static u8 *drm_find_cea_extension(const struct edid *edid) > struct displayid_block *block; > u8 *cea; > u8 *displayid; > + int ext_index; > > /* Look for a top level CEA extension block */ > - cea = drm_find_edid_extension(edid, CEA_EXT); > + ext_index = 0; In 2 places ext_index is initialized in the variable declaration and in 2 other places is not, all of it could be done in the declaration or if you really want to leave the context close to the users, initialize it in the "for (;;)" in the next patch. With the change above: Reviewed-by: Jos? Roberto de Souza <jose.souza at intel.com> > + cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index); > if (cea) > return cea; > > /* CEA blocks can also be found embedded in a DisplayID block */ > - displayid = drm_find_displayid_extension(edid, &length, &idx); > + ext_index = 0; > + displayid = drm_find_displayid_extension(edid, &length, &idx, > + &ext_index); > if (!displayid) > return NULL; > > @@ -5195,8 +5203,10 @@ static int add_displayid_detailed_modes(struct drm_connector *connector, > int length, idx; > struct displayid_block *block; > int num_modes = 0; > + int ext_index = 0; > > - displayid = drm_find_displayid_extension(edid, &length, &idx); > + displayid = drm_find_displayid_extension(edid, &length, &idx, > + &ext_index); > if (!displayid) > return 0; > > @@ -5870,11 +5880,13 @@ void drm_update_tile_info(struct drm_connector *connector, > const struct edid *edid) > { > const void *displayid = NULL; > + int ext_index = 0; > int length, idx; > int ret; > > connector->has_tile = false; > - displayid = drm_find_displayid_extension(edid, &length, &idx); > + displayid = drm_find_displayid_extension(edid, &length, &idx, > + &ext_index); > if (!displayid) { > /* drop reference to any tile group we had */ > goto out_drop_ref;